mirror of
https://gitlab.rtems.org/rtems/rtos/rtems.git
synced 2026-04-05 10:09:54 +00:00
committed by
Kinsey Moore
parent
8ed01d70cc
commit
7f46d3ca7a
@@ -8,8 +8,9 @@
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*/
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/*
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* Copyright (C) 2026 Gedare Bloom
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* Copyright (C) 2018, 2023 embedded brains GmbH & Co. KG
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* COPYRIGHT (c) 2015 Hesham Alatary <hesham@alumni.york.ac.uk>
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* Copyright (C) 2015 Hesham Alatary <hesham@alumni.york.ac.uk>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@@ -105,16 +106,16 @@ static uint64_t riscv_clock_read_mtime(volatile RISCV_CLINT_timer_reg *mtime)
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static void riscv_clock_at_tick(riscv_timecounter *tc)
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{
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#ifndef RISCV_USE_S_MODE
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uint64_t value;
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#endif
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#ifndef RISCV_USE_S_MODE
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#ifdef RISCV_USE_S_MODE
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value = read_csr(stimecmp);
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value += tc->interval;
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write_csr(stimecmp, value);
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#else
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value = riscv_clock_read_mtimecmp();
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value += tc->interval;
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riscv_clock_write_mtimecmp(value);
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#else
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(void) tc;
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#endif
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}
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@@ -136,15 +137,14 @@ static void riscv_clock_handler_install(rtems_interrupt_handler handler)
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static uint32_t riscv_clock_get_timecount(struct timecounter *base)
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{
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riscv_timecounter *tc = (riscv_timecounter *) base;
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uint32_t timecount = 0;
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uint32_t timecount;
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(void) tc;
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(void) base;
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#ifndef RISCV_USE_S_MODE
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timecount = riscv_clint->mtime.val_32[0];
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#ifdef RISCV_USE_S_MODE
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timecount = (uint32_t) rdtime();
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#else
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timecount = riscv_clint->mtime.val_32[0];
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#endif
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return timecount;
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@@ -189,16 +189,16 @@ static uint64_t riscv_clock_read_timer(riscv_timecounter *tc)
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static void riscv_clock_local_set_timer(uint64_t cmpval)
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{
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#ifdef RISCV_USE_S_MODE
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(void) cmpval;
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write_csr(stimecmp, cmpval);
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#else
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riscv_clock_write_mtimecmp(cmpval);
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#endif
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}
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static void riscv_clock_local_enable()
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static void riscv_clock_local_enable_isr()
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{
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#ifdef RISCV_USE_S_MODE
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set_csr(sie, SIP_STIP);
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#else
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set_csr(mie, MIP_MTIP);
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#endif
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@@ -207,7 +207,7 @@ static void riscv_clock_local_enable()
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static void riscv_clock_local_init(uint64_t cmpval)
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{
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riscv_clock_local_set_timer(cmpval);
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riscv_clock_local_enable();
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riscv_clock_local_enable_isr();
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}
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#if defined(RTEMS_SMP) && !defined(CLOCK_DRIVER_USE_ONLY_BOOT_PROCESSOR)
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