2001-02-01 Greg Menke <gregory.menke@gsfc.nasa.gov>

* Update of BSP to address problems restarting, provide more information during boot, and better handle ROM vs RAM images. * README, include/bsp.h, start/regs.S, start/start.S, startup/bspstart.c, startup/linkcmds, timer/timer.c: Updated
2025-12-27 15:00:16 +00:00 · 2002-02-01 16:45:18 +00:00
parent 2835b3a568
commit 7de5823954
8 changed files with 1050 additions and 404 deletions
--- a/c/src/lib/libbsp/mips/genmongoosev/ChangeLog
+++ b/c/src/lib/libbsp/mips/genmongoosev/ChangeLog
@@ -1,3 +1,10 @@
+2001-02-01	Greg Menke <gregory.menke@gsfc.nasa.gov>
+
+	* Update of BSP to address problems restarting, provide more
+	information during boot, and better handle ROM vs RAM images.
+	* README, include/bsp.h, start/regs.S, start/start.S,
+	startup/bspstart.c, startup/linkcmds, timer/timer.c: Updated
+
 2002-02-07	Ralf Corsepius <corsepiu@faw.uni-ulm.de>

 	* configure.ac: Remove RTEMS_OUTPUT_BUILD_SUBDIRS.
--- a/c/src/lib/libbsp/mips/genmongoosev/README
+++ b/c/src/lib/libbsp/mips/genmongoosev/README
@@ -38,28 +38,52 @@ The Mongoose-V on this board is at 12 Mhz.
 Downloading
 ===========

-At startup, PMON looks for a <space> to be pressed.  If it is pressed,
-then a PMON prompt is displayed.  Otherwise, PMON automatically jumps
-to the code at 0xBFC4_0000.  This code may be a boot manager or
-simply a collection of noop's that fall into the code at 
-0xBFC5_0000.  If the code at 0xBFC4_0000 is a boot manager, then it
-can determine which program image to load.  This layout allows for the
-possible compression of program images.  Given that there is much
-more RAM than EEPROM, compression could be desirable for certain
-applications.
+On the breadboard, a locally hacked PMON waits for a space to be pressed
+while the board is reset/powered up.  If found, the PMON console is
+entered, else PMON jumps to the EEPROM address above, presuming a user
+program is located there.
+
+The default output of an RTEMS link is an image linked to run from
+80020000, but has had its LMA shifted up to BFC40000.  It is suitable
+for copying to S3 records or can be burned to ROMs in whatever manner
+the user desires.
+
+Operation
+=========
+
+A small relocator is supplied in the bsp startup code which copies the
+image down to RAM for execution before doing any other initialization.
+This locator code is location independent, and will do nothing if the
+image is already located at its run location.  The LMA and VMA are both
+controlled via the bsp's link script.  The above behavior is produced by
+using the default script.  If this is not desirable, something like the
+following may be added to the user's RTEMS link statement to override
+the default linkcmds with a user-supplied version;
+
+-qnolinkcmds -Wl,-T -Wl,mips-rtems-linkcmds-eprom
+
+this causes the file ./mips-rtems-linkcmds-eprom to override the default
+linkcmds.
+
+Before relocating the RTEMS image, the bsp startup routine attempts to
+configure the processor into a rational state.  During this process,
+status characters are emitted at 19200N81 baud on UART port 0.
+

 Questions
 =========

-+  XXX
- 
+Why can I send characters slowly to a Mongoose V, but get framing errors
+when sending them fast?
+
+- The MongooseV chip seems to <require> that all incoming data have 2
+  stop bits.  When typing on a serial terminal, this is not an issue
+  because the idle state of an RS232 line looks just like a stop bit-
+  but when streaming in data, such pacing is required.  The manual does
+  not indicate anything along these lines, instead, we suspect a
+  somewhat faulty UART design.
+
+
 Status
 ======

-+ untested
-
-+ no mkeeprom script
-
-+ start code must copy from EEPROM to RAM and then run.
-
-+ XXX
--- a/c/src/lib/libbsp/mips/genmongoosev/include/bsp.h
+++ b/c/src/lib/libbsp/mips/genmongoosev/include/bsp.h
@@ -129,12 +129,12 @@ extern rtems_configuration_table BSP_Configuration;

 void bsp_cleanup( void );

-rtems_isr_entry set_vector(
-  rtems_isr_entry, rtems_vector_number, int );
-
+rtems_isr_entry set_vector( rtems_isr_entry, rtems_vector_number, int );
+   
 #ifdef __cplusplus
 }
 #endif

 #endif
+
 /* end of include file */
--- a/c/src/lib/libbsp/mips/genmongoosev/start/regs.S
+++ b/c/src/lib/libbsp/mips/genmongoosev/start/regs.S
@@ -16,104 +16,110 @@
 */

 /* Standard MIPS register names: */
-#define zero	$0
-#define z0	$0
-#define v0	$2
-#define v1	$3
-#define a0	$4
-#define a1	$5
-#define a2	$6
-#define a3	$7
-#define t0	$8
-#define t1	$9
-#define t2	$10
-#define t3	$11
-#define t4	$12
-#define t5	$13
-#define t6	$14
-#define t7	$15
-#define s0	$16
-#define s1	$17
-#define s2	$18
-#define s3	$19
-#define s4	$20
-#define s5	$21
-#define s6	$22
-#define s7	$23
-#define t8	$24
-#define t9	$25
-#define k0	$26	/* kernel private register 0 */
-#define k1	$27	/* kernel private register 1 */
-#define gp	$28	/* global data pointer */
-#define sp 	$29	/* stack-pointer */
-#define fp	$30	/* frame-pointer */
-#define ra	$31	/* return address */
-#define pc	$pc	/* pc, used on mips16 */
+#define zero    $0
+#define z0  $0
+#define v0  $2
+#define v1  $3
+#define a0  $4
+#define a1  $5
+#define a2  $6
+#define a3  $7
+#define t0  $8
+#define t1  $9
+#define t2  $10
+#define t3  $11
+#define t4  $12
+#define t5  $13
+#define t6  $14
+#define t7  $15
+#define s0  $16
+#define s1  $17
+#define s2  $18
+#define s3  $19
+#define s4  $20
+#define s5  $21
+#define s6  $22
+#define s7  $23
+#define t8  $24
+#define t9  $25
+#define k0  $26 /* kernel private register 0 */
+#define k1  $27 /* kernel private register 1 */
+#define gp  $28 /* global data pointer */
+#define sp  $29 /* stack-pointer */
+#define fp  $30 /* frame-pointer */
+#define ra  $31 /* return address */
+#define pc  $pc /* pc, used on mips16 */

-#define fp0	$f0
-#define fp1	$f1
+#define fp0 $f0
+#define fp1 $f1

-#define WATCHDOG	0xBE000000
+#define WATCHDOG    0xBE000000

 /* Useful memory constants: */
-#define K0BASE		0x80000000
+#define K0BASE      0x80000000
 #ifndef __mips64
-#define K1BASE		0xA0000000
+   #define K1BASE       0xA0000000
 #else
-#define K1BASE		0xFFFFFFFFA0000000LL
+#define K1BASE      0xFFFFFFFFA0000000LL
 #endif

 #define PHYS_TO_K1(a)   ((unsigned)(a) | K1BASE)

-/* Standard Co-Processor 0 register numbers:
-#define C0_COUNT	$9		/* Count Register */
-#define C0_SR		$12		/* Status Register */
-#define C0_CAUSE	$13		/* last exception description */
-#define C0_EPC		$14		/* Exception error address */
-#define C0_CONFIG	$16		/* CPU configuration */
+/* Standard Co-Processor 0 register numbers: */
+#define C0_DCIC     $7      /* debug & cache invalidate control */
+#define C0_COUNT    $9      /* Count Register */
+#define C0_SR           $12         /* Status Register */
+#define C0_CAUSE    $13     /* last exception description */
+#define C0_EPC      $14         /* Exception error address */
+#define C0_CONFIG   $16     /* CPU configuration */

 /* Standard Status Register bitmasks: */
-#define SR_CU1		0x20000000	/* Mark CP1 as usable */
-#define SR_FR		0x04000000	/* Enable MIPS III FP registers */
-#define SR_BEV		0x00400000	/* Controls location of exception vectors */
-#define SR_PE		0x00100000	/* Mark soft reset (clear parity error) */
+#define SR_CU0          0x10000000
+#define SR_CU1      0x20000000  /* Mark CP1 as usable */
+#define SR_FR       0x04000000  /* Enable MIPS III FP registers */
+#define SR_BEV      0x00400000  /* Controls location of exception vectors */
+#define SR_PE       0x00100000  /* Mark soft reset (clear parity error) */

-#define SR_KX		0x00000080	/* Kernel extended addressing enabled */
-#define SR_SX		0x00000040	/* Supervisor extended addressing enabled */
-#define SR_UX		0x00000020	/* User extended addressing enabled */
+/* defined differently for Mongoose5- we don't use these anymore */
+//#define SR_KX     0x00000080  /* Kernel extended addressing enabled */
+//#define SR_SX     0x00000040  /* Supervisor extended addressing enabled */
+//#define SR_UX     0x00000020  /* User extended addressing enabled */
+
+/* R3000 */
+#define SR_ISC      0x00010000  /* Isolate data cache */

 /* Standard (R4000) cache operations. Taken from "MIPS R4000
   Microprocessor User's Manual" 2nd edition: */

-#define CACHE_I		(0)	/* primary instruction */
-#define CACHE_D		(1)	/* primary data */
-#define CACHE_SI	(2)	/* secondary instruction */
-#define CACHE_SD	(3)	/* secondary data (or combined instruction/data) */
+#define CACHE_I     (0) /* primary instruction */
+#define CACHE_D     (1) /* primary data */
+#define CACHE_SI    (2) /* secondary instruction */
+#define CACHE_SD    (3) /* secondary data (or combined instruction/data) */

-#define INDEX_INVALIDATE		(0)	/* also encodes WRITEBACK if CACHE_D or CACHE_SD */
-#define INDEX_LOAD_TAG			(1)
-#define INDEX_STORE_TAG			(2)
-#define CREATE_DIRTY_EXCLUSIVE		(3)	/* CACHE_D and CACHE_SD only */
-#define HIT_INVALIDATE			(4)
-#define CACHE_FILL			(5)	/* CACHE_I only */
-#define HIT_WRITEBACK_INVALIDATE	(5)	/* CACHE_D and CACHE_SD only */
-#define HIT_WRITEBACK			(6)	/* CACHE_I, CACHE_D and CACHE_SD only */
-#define HIT_SET_VIRTUAL			(7)	/* CACHE_SI and CACHE_SD only */
+#define INDEX_INVALIDATE        (0) /* also encodes WRITEBACK if CACHE_D or CACHE_SD */
+#define INDEX_LOAD_TAG          (1)
+#define INDEX_STORE_TAG         (2)
+#define CREATE_DIRTY_EXCLUSIVE      (3) /* CACHE_D and CACHE_SD only */
+#define HIT_INVALIDATE          (4)
+#define CACHE_FILL          (5) /* CACHE_I only */
+#define HIT_WRITEBACK_INVALIDATE    (5) /* CACHE_D and CACHE_SD only */
+#define HIT_WRITEBACK           (6) /* CACHE_I, CACHE_D and CACHE_SD only */
+#define HIT_SET_VIRTUAL         (7) /* CACHE_SI and CACHE_SD only */

-#define BUILD_CACHE_OP(o,c)		(((o) << 2) | (c))
+#define BUILD_CACHE_OP(o,c)     (((o) << 2) | (c))

 /* Individual cache operations: */
-#define INDEX_INVALIDATE_I		BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_I)
-#define INDEX_WRITEBACK_INVALIDATE_D	BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_D)
+#define INDEX_INVALIDATE_I      BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_I)
+#define INDEX_WRITEBACK_INVALIDATE_D    BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_D)
 #define INDEX_INVALIDATE_SI             BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SI)
-#define INDEX_WRITEBACK_INVALIDATE_SD	BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SD)
+#define INDEX_WRITEBACK_INVALIDATE_SD   BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SD)

-#define INDEX_LOAD_TAG_I		BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_I)
+#define INDEX_LOAD_TAG_I        BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_I)
 #define INDEX_LOAD_TAG_D                BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_D)
 #define INDEX_LOAD_TAG_SI               BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SI)
 #define INDEX_LOAD_TAG_SD               BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SD)

-#define INDEX_STORE_TAG_I              	BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_I)
+#define INDEX_STORE_TAG_I               BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_I)
 #define INDEX_STORE_TAG_D               BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_D)
 #define INDEX_STORE_TAG_SI              BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SI)
 #define INDEX_STORE_TAG_SD              BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SD)
@@ -134,7 +140,7 @@
 #define HIT_WRITEBACK_D                 BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_D)
 #define HIT_WRITEBACK_SD                BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_SD)

-#define HIT_SET_VIRTUAL_SI		BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SI)
+#define HIT_SET_VIRTUAL_SI      BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SI)
 #define HIT_SET_VIRTUAL_SD              BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SD)

 /*> EOF regs.S <*/
--- a/c/src/lib/libbsp/mips/genmongoosev/start/start.S
+++ b/c/src/lib/libbsp/mips/genmongoosev/start/start.S
--- a/c/src/lib/libbsp/mips/genmongoosev/startup/bspstart.c
+++ b/c/src/lib/libbsp/mips/genmongoosev/startup/bspstart.c
@@ -1,18 +1,22 @@
 /*
- *  This routine starts the application.  It includes application,
- *  board, and monitor specific initialization and configuration.
- *  The generic CPU dependent initialization has been performed
- *  before this routine is invoked.
- *
- *  COPYRIGHT (c) 1989-2001.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.OARcorp.com/rtems/license.html.
- *
- *  $Id$
- */
+**  This routine starts the application.  It includes application,
+**  board, and monitor specific initialization and configuration.
+**  The generic CPU dependent initialization has been performed
+**  before this routine is invoked.
+**
+**  COPYRIGHT (c) 1989-2001.
+**  On-Line Applications Research Corporation (OAR).
+**
+**  The license and distribution terms for this file may be
+**  found in the file LICENSE in this distribution or at
+**  http://www.OARcorp.com/rtems/license.html.
+**
+**  $Id$
+**
+** Modification History:
+**        12/10/01  A.Ferrer, NASA/GSFC, Code 582
+**           Set interrupt mask to 0xAF00 (Line 139).
+*/

 #include <string.h>

@@ -39,7 +43,7 @@ char *rtems_progname;
 /*
 *  Use the shared implementations of the following routines
 */
- 
+
 void bsp_postdriver_hook(void);
 void bsp_libc_init( void *, unsigned32, int );

@@ -56,7 +60,7 @@ void bsp_libc_init( void *, unsigned32, int );
 *      not yet initialized.
 *
 */
- 
+
 void bsp_pretasking_hook(void)
 {
    extern int HeapBase;
@@ -83,8 +87,8 @@ void bsp_pretasking_hook(void)

 void bsp_start( void )
 {
-  extern int _end;
  extern int WorkspaceBase;
+  extern void mips_install_isr_entries();

  /* Configure Number of Register Caches */

@@ -93,11 +97,14 @@ void bsp_start( void )
  Cpu_table.interrupt_stack_size = 4096;

  /* HACK -- tied to value linkcmds */
-  if ( BSP_Configuration.work_space_size >(4096*1024) )
-   _sys_exit( 1 );
+  if ( BSP_Configuration.work_space_size > (4096*1024) )
+     _sys_exit( 1 );

  BSP_Configuration.work_space_start = (void *) &WorkspaceBase;

+  /* mask off any interrupts */
+  MONGOOSEV_WRITE( MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_MASK_REGISTER, 0 );
+
  MONGOOSEV_WRITE( MONGOOSEV_WATCHDOG, 0xA0 );

  /* reset the config register & clear any pending peripheral interrupts */
@@ -112,14 +119,26 @@ void bsp_start( void )
  MONGOOSEV_WRITE_REGISTER( MONGOOSEV_TIMER2_BASE, MONGOOSEV_TIMER_INITIAL_COUNTER_REGISTER, 0xffffffff );
  MONGOOSEV_WRITE_REGISTER( MONGOOSEV_TIMER2_BASE, MONGOOSEV_TIMER_CONTROL_REGISTER, 0);

-  MONGOOSEV_WRITE( MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_MASK_REGISTER, 0 );
+  /* clear any pending interrupts */
  MONGOOSEV_WRITE( MONGOOSEV_PERIPHERAL_STATUS_REGISTER, 0xffffffff );

  /* clear any writable bits in the cause register */
  mips_set_cause( 0 );

-  /*all interrupts unmasked but globally off.  depend on the IRC to take care of things */
-  mips_set_sr( (SR_CU0 | SR_CU1 | 0xff00) );
+  /* set interrupt mask, but globally off. */
+
+  /*
+  **  Bit 15 | Bit 14 | Bit 13 | Bit 12 | Bit 11 | Bit 10 | Bit  9 | Bit  8 |
+  **  periph | unused |  FPU   | unused | timer2 | timer1 | swint1 | swint2 |
+  **  extern |        |        |        |        |        |        |        |
+  **
+  **    1        0        1        0        0        1        0        0
+  **
+  **    0x8C00   Enable only internal Mongoose V timers.
+  **    0xA400   Enable Peripherial ints, FPU and timer1
+  */
+
+  mips_set_sr( (SR_CU0 | SR_CU1 | 0xA400) );

  mips_install_isr_entries();
 }
@@ -140,10 +159,11 @@ struct s_mem
 };


-void
-get_mem_info (mem)
-     struct s_mem *mem;
+
+extern unsigned32 _RamSize;
+
+void get_mem_info ( struct s_mem *mem )
 {
-  mem->size = 0x1000000;        /* XXX figure out something here */
+   mem->size = (unsigned32)&_RamSize;
 }

--- a/c/src/lib/libbsp/mips/genmongoosev/startup/linkcmds
+++ b/c/src/lib/libbsp/mips/genmongoosev/startup/linkcmds
@@ -5,24 +5,28 @@
 *  $Id$
 */

+/*    . = 0x80020000; */
+
 /*
 * Declare some sizes.
 */
+
 _RamBase = DEFINED(_RamBase) ? _RamBase : 0x80000000;
 _RamSize = DEFINED(_RamSize) ? _RamSize : 32M;
-HeapSize = DEFINED(HeapSize) ? HeapSize : 0x10000;
+HeapSize = DEFINED(HeapSize) ? HeapSize : 0x40000;
 _StackSize = DEFINED(_StackSize) ? _StackSize : 0x1000;
 ClockRate = DEFINED(ClockRate) ? ClockRate : 12000000;

+
+
+MEMORY
+{
+   romstore : ORIGIN = 0xbfc40000, LENGTH = 4M
+   ram      : ORIGIN = 0x80020000, LENGTH = 4M
+}
+
 SECTIONS
 { 
-/*
-Ken's response is correct.  Locate it at 0x80020000 or higher.  The PMON 
-data segment after the exception vectors and below 0x80020000,
-
-. = 0x80020000;
-*/
-    . = 0x80020000;
    .text : 
    { 
       _ftext = . ;
@@ -35,12 +39,12 @@ data segment after the exception vectors and below 0x80020000,
      *(.mips16.call.*)
      PROVIDE (__runtime_reloc_start = .);
      *(.rel.sdata)
+      *(.rel.dyn)
      PROVIDE (__runtime_reloc_stop = .);
      *(.fini)
-       etext  =  .;
-       _etext  =  .;
-    }  
-  .ctors    :
+    } >ram  AT>romstore
+
+  .ctors    : 
  {
    /* gcc uses crtbegin.o to find the start of
       the constructors, so we make sure it is
@@ -62,54 +66,76 @@ data segment after the exception vectors and below 0x80020000,
    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
    KEEP (*(SORT(.ctors.*)))
    KEEP (*(.ctors))
-  }
+  } >ram  AT>romstore

-  .dtors    :
+  .dtors    : 
  {
    KEEP (*crtbegin.o(.dtors))
    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
    KEEP (*(SORT(.dtors.*)))
    KEEP (*(.dtors))
-  }

-    . = .;
-  .rdata : {
+    etext  =  .;
+    _etext  =  .;
+  } >ram  AT>romstore
+
+/*    . = .; */
+
+  .rdata : 
+  {
    *(.rdata)
    *(.rodata)
    *(.rodata.*)
    *(.gnu.linkonce.r*)
-  }
-   _fdata = ALIGN(16);
-  .data : {
+  } >ram  AT>romstore
+
+  .data : 
+  {
+    _fdata = ALIGN(16);
+
    *(.data)
    *(.data.*)
    *(.gnu.linkonce.d*)
-  }
-  . = ALIGN(8);
-  _gp = . + 0x8000;
-  __global = _gp;
-  .lit8 : {
+  } >ram  AT>romstore
+
+
+  .lit8 : 
+  {
+    . = ALIGN(8);
+
+    _gp = . + 0x8000;
+    __global = _gp;
    *(.lit8)
-  }
-  .lit4 : {
+  } >ram  AT>romstore
+
+  .lit4 : 
+  {
    *(.lit4)
-  }
-  .sdata : {
+  } >ram  AT>romstore 
+
+  .sdata :   
+  {
    *(.sdata)
    *(.sdata.*)
    *(.gnu.linkonce.s*)
-  }
+  } >ram  AT>romstore
+
+  .sbss : 
+  {
  . = ALIGN(4);
   edata  =  .;
   _edata  =  .;
   _fbss = .;
-  .sbss : {
    *(.sbss)
    *(.scommon)
-  }
-  .bss : {
+  } >ram  AT>romstore 
+
+
+  .bss : 
+  {
    _bss_start = . ;
    *(.bss)
+    *(.reginfo)
    *(COMMON)
    . = ALIGN (64);
    _stack_limit = .;
@@ -120,42 +146,41 @@ data segment after the exception vectors and below 0x80020000,
    HeapBase = .;
    . += HeapSize;    /* reserve some memory for heap */
    WorkspaceBase = .;
-  }
- end = .;
- _end = .;
+    end = .;
+    _end = .;
+  } >ram  AT>romstore 


-/* Put starting stack in SRAM (8 Kb); this size is the same as the stack from
-      the original script (when everything was in SRAM). */
-   /* __stack = 0x8000A000; */
-  /* DWARF debug sections.
-     Symbols in the DWARF debugging sections are relative to
-     the beginning of the section so we begin them at 0.  */
+/* 
+** DWARF debug sections.
+** Symbols in the DWARF debugging sections are relative to
+** the beginning of the section so we begin them at 0.  
+*/

  /* DWARF 1 */
-  .debug          0 : { *(.debug) }
-  .line           0 : { *(.line) }
+  .debug          0 : { *(.debug) } AT>romstore
+  .line           0 : { *(.line) } AT>romstore

  /* GNU DWARF 1 extensions */
-  .debug_srcinfo  0 : { *(.debug_srcinfo) }
-  .debug_sfnames  0 : { *(.debug_sfnames) }
+  .debug_srcinfo  0 : { *(.debug_srcinfo) } AT>romstore
+  .debug_sfnames  0 : { *(.debug_sfnames) } AT>romstore

  /* DWARF 1.1 and DWARF 2 */
-  .debug_aranges  0 : { *(.debug_aranges) }
-  .debug_pubnames 0 : { *(.debug_pubnames) }
+  .debug_aranges  0 : { *(.debug_aranges) } AT>romstore
+  .debug_pubnames 0 : { *(.debug_pubnames) } AT>romstore

  /* DWARF 2 */
-  .debug_info     0 : { *(.debug_info) }
-  .debug_abbrev   0 : { *(.debug_abbrev) }
-  .debug_line     0 : { *(.debug_line) }
-  .debug_frame    0 : { *(.debug_frame) }
-  .debug_str      0 : { *(.debug_str) }
-  .debug_loc      0 : { *(.debug_loc) }
-  .debug_macinfo  0 : { *(.debug_macinfo) }
+  .debug_info     0 : { *(.debug_info) }    AT>romstore
+  .debug_abbrev   0 : { *(.debug_abbrev) }  AT>romstore
+  .debug_line     0 : { *(.debug_line) }    AT>romstore
+  .debug_frame    0 : { *(.debug_frame)}    AT>romstore
+  .debug_str      0 : { *(.debug_str) }     AT>romstore
+  .debug_loc      0 : { *(.debug_loc) }     AT>romstore
+  .debug_macinfo  0 : { *(.debug_macinfo) } AT>romstore

  /* SGI/MIPS DWARF 2 extensions */
-  .debug_weaknames 0 : { *(.debug_weaknames) }
-  .debug_funcnames 0 : { *(.debug_funcnames) }
-  .debug_typenames 0 : { *(.debug_typenames) }
-  .debug_varnames  0 : { *(.debug_varnames) }
+  .debug_weaknames 0 : { *(.debug_weaknames) } AT>romstore
+  .debug_funcnames 0 : { *(.debug_funcnames) } AT>romstore
+  .debug_typenames 0 : { *(.debug_typenames) } AT>romstore
+  .debug_varnames  0 : { *(.debug_varnames) }  AT>romstore
 }
--- a/c/src/lib/libbsp/mips/genmongoosev/timer/timer.c
+++ b/c/src/lib/libbsp/mips/genmongoosev/timer/timer.c
@@ -54,7 +54,7 @@ void Timer_initialize()

 #define LEAST_VALID       1  /* Don't trust a value lower than this */
                             /* mongoose-v can count cycles. :) */
-#include <rtems/bspIo.h>
+#include <bspIo.h>

 int Read_timer()
 {