bsps/zynqmp: Added I2C support for ZynqMP

Added I2C drivers for ZynqMP and updated build system accordingly.

bsps/aarch64/xilinx-zynqmp/include/bsp.h

@@ -70,6 +70,10 @@ BSP_START_TEXT_SECTION void zynqmp_setup_mmu_and_cache(void);
 
 void zynqmp_debug_console_flush(void);
 
+uint32_t zynqmp_clock_i2c0(void);
+
+uint32_t zynqmp_clock_i2c1(void);
+
 #ifdef __cplusplus
 }
 #endif /* __cplusplus */

bsps/aarch64/xilinx-zynqmp/include/bsp/i2c.h

@@ -0,0 +1,64 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (C) 2021 On-Line Applications Research (OAR)
+ * Copyright (C) 2014 embedded brains GmbH
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_ARM_XILINX_ZYNQ_I2C_H
+#define LIBBSP_ARM_XILINX_ZYNQ_I2C_H
+
+#include <dev/i2c/cadence-i2c.h>
+#include <bsp/irq.h>
+#include <bsp.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+static inline int zynqmp_register_i2c_0(void)
+{
+  return i2c_bus_register_cadence(
+    "/dev/i2c-0",
+    0x00FF020000,
+    zynqmp_clock_i2c0(),
+    ZYNQMP_IRQ_I2C_0
+  );
+}
+
+static inline int zynqmp_register_i2c_1(void)
+{
+  return i2c_bus_register_cadence(
+    "/dev/i2c-1",
+    0x00FF030000,
+    zynqmp_clock_i2c1(),
+    ZYNQMP_IRQ_I2C_1
+  );
+}
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_XILINX_ZYNQ_I2C_H */

bsps/aarch64/xilinx-zynqmp/include/bsp/irq.h

@@ -53,6 +53,8 @@ extern "C" {
 /* Interrupts vectors */
 #define BSP_TIMER_VIRT_PPI 27
 #define BSP_TIMER_PHYS_NS_PPI 30
+#define ZYNQMP_IRQ_I2C_0 49
+#define ZYNQMP_IRQ_I2C_1 50
 #define ZYNQMP_IRQ_UART_0 54
 #define ZYNQMP_IRQ_UART_1 53
 #define ZYNQMP_IRQ_ETHERNET_0 89

bsps/aarch64/xilinx-zynqmp/start/bspstart.c

@@ -39,6 +39,16 @@
 #include <bsp/irq-generic.h>
 #include <bsp/linker-symbols.h>
 
+__attribute__ ((weak)) uint32_t zynqmp_clock_i2c0(void)
+{
+  return ZYNQMP_CLOCK_I2C0;
+}
+
+__attribute__ ((weak)) uint32_t zynqmp_clock_i2c1(void)
+{
+  return ZYNQMP_CLOCK_I2C1;
+}
+
 void bsp_start( void )
 {
   bsp_interrupt_initialize();

spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml

@@ -27,6 +27,10 @@ links:
   uid: optramlen
 - role: build-dependency
   uid: optramori
+- role: build-dependency
+  uid: optclki2c0
+- role: build-dependency
+  uid: optclki2c1
 - role: build-dependency
   uid: optclkuart
 - role: build-dependency

spec/build/bsps/aarch64/xilinx-zynqmp/grp_zu3eg.yml

@@ -11,6 +11,8 @@ links:
   uid: grp
 - role: build-dependency
   uid: tstzu3eg
+- role : build-dependency
+  uid: objcadencei2c
 type: build
 use-after: []
 use-before: []

spec/build/bsps/aarch64/xilinx-zynqmp/objcadencei2c.yml

@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: objects
+cflags: []
+copyrights:
+- Copyright (C) 2021 On-Line Applications Research (OAR)
+cppflags: []
+cxxflags: []
+enabled-by: true
+includes: []
+install:
+- destination: ${BSP_INCLUDEDIR}/bsp
+  source:
+  - bsps/include/dev/i2c/cadence-i2c-regs.h
+  - bsps/include/dev/i2c/cadence-i2c.h
+  - bsps/aarch64/xilinx-zynqmp/include/bsp/i2c.h
+links: []
+source:
+- bsps/shared/dev/i2c/cadence-i2c.c
+type: build

spec/build/bsps/aarch64/xilinx-zynqmp/optclki2c0.yml

@@ -0,0 +1,31 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- define: null
+build-type: option
+copyrights: |
+  Copyright (C) 2021 On-Line Applications Research (OAR)
+  Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+default: 111111111
+default-by-family: []
+default-by-variant:
+- value: 111111111
+  variants:
+  - aarch64/xilinx_zynqmp_ilp32_qemu.*
+- value: 111111111
+  variants:
+  - aarch64/xilinx_zynqmp_ilp32_zu3eg.*
+- value: 111111111
+  variants:
+  - aarch64/xilinx_zynqmp_lp64_qemu.*
+- value: 111111111
+  variants:
+  - aarch64/xilinx_zynqmp_lp64_zu3eg.*
+description: |
+  ZynqMP i2c0 clock frequency in Hz. This is the frequency after the signal
+  has been processed using the values passed to the I2C0_REF_CTRL register.
+enabled-by: true
+format: '{}'
+links: []
+name: ZYNQMP_CLOCK_I2C0
+type: build

spec/build/bsps/aarch64/xilinx-zynqmp/optclki2c1.yml

@@ -0,0 +1,31 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- define: null
+build-type: option
+copyrights: |
+  Copyright (C) 2021 On-Line Applications Research (OAR)
+  Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+default: 111111111
+default-by-family: []
+default-by-variant:
+- value: 111111111
+  variants:
+  - aarch64/xilinx_zynqmp_ilp32_qemu.*
+- value: 111111111
+  variants:
+  - aarch64/xilinx_zynqmp_ilp32_zu3eg.*
+- value: 111111111
+  variants:
+  - aarch64/xilinx_zynqmp_lp64_qemu.*
+- value: 111111111
+  variants:
+  - aarch64/xilinx_zynqmp_lp64_zu3eg.*
+description: |
+  ZynqMP i2c1 clock frequency in Hz. This is the frequency after the signal
+  has been processed using the values passed to the I2C1_REF_CTRL register.
+enabled-by: true
+format: '{}'
+links: []
+name: ZYNQMP_CLOCK_I2C1
+type: build