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Switched from presenting timing data based on CPU models to presenting it

Browse Source 
based on board model.
This commit is contained in:
Joel Sherrill
1998-08-13 21:24:50 +00:00
parent fba4a16cb0
commit 6ddf0543b4
19 changed files with 162 additions and 155 deletions
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1
doc/supplements/hppa1_1/SIMHPPA_TIMES
View File

@@ -7,6 +7,7 @@
#
# CPU Model Information
#
RTEMS_BSP simhppa
RTEMS_CPU_MODEL HP-7100
#
# Interrupt Latency

1
doc/supplements/hppa1_1/TIMES
View File

@@ -7,6 +7,7 @@
#
# CPU Model Information
#
RTEMS_BSP simhppa
RTEMS_CPU_MODEL HP-7100
#
# Interrupt Latency

1
doc/supplements/i386/FORCE386_TIMES
View File

@@ -7,6 +7,7 @@
#
# CPU Model Information
#
RTEMS_BSP CPU386
RTEMS_CPU_MODEL i386
#
# Interrupt Latency

2
doc/supplements/i386/Makefile
View File

@@ -61,7 +61,7 @@ timedata.texi: timedata.t FORCE386_TIMES
wksheets.t: ../../common/wksheets.t
sed -e 's/WORKSHEETS_PREVIOUS_LINK/Processor Dependent Information Table CPU Dependent Information Table/' \
-e 's/WORKSHEETS_NEXT_LINK/i386 Timing Data/' \
-e 's/WORKSHEETS_NEXT_LINK/CPU386 Timing Data/' \
<../../common/wksheets.t >wksheets.t
wksheets.texi: wksheets.t FORCE386_TIMES

4
doc/supplements/i386/i386.texi
View File

@@ -91,7 +91,7 @@ Applications Supplement.
* Processor Dependent Information Table::
* Memory Requirements::
* Timing Specification::
* i386 Timing Data::
* CPU386 Timing Data::
* Command and Variable Index::
* Concept Index::
@end menu
@@ -102,7 +102,7 @@ Applications Supplement.
@c Need to copy the emacs stuff and "trailer stuff" (index, toc) into here
@c
@node Command and Variable Index, Concept Index, i386 Timing Data Rate Monotonic Manager, Top
@node Command and Variable Index, Concept Index, CPU386 Timing Data Rate Monotonic Manager, Top
@unnumbered Command and Variable Index
There are currently no Command and Variable Index entries.

48
doc/supplements/i386/timeFORCE386.t
View File

@@ -12,34 +12,34 @@
@end tex
@ifinfo
@node i386 Timing Data, i386 Timing Data Introduction, Memory Requirements RTEMS RAM Workspace Worksheet, Top
@node CPU386 Timing Data, CPU386 Timing Data Introduction, Memory Requirements RTEMS RAM Workspace Worksheet, Top
@end ifinfo
@chapter i386 Timing Data
@chapter CPU386 Timing Data
@ifinfo
@menu
* i386 Timing Data Introduction::
* i386 Timing Data Hardware Platform::
* i386 Timing Data Interrupt Latency::
* i386 Timing Data Context Switch::
* i386 Timing Data Directive Times::
* i386 Timing Data Task Manager::
* i386 Timing Data Interrupt Manager::
* i386 Timing Data Clock Manager::
* i386 Timing Data Timer Manager::
* i386 Timing Data Semaphore Manager::
* i386 Timing Data Message Manager::
* i386 Timing Data Event Manager::
* i386 Timing Data Signal Manager::
* i386 Timing Data Partition Manager::
* i386 Timing Data Region Manager::
* i386 Timing Data Dual-Ported Memory Manager::
* i386 Timing Data I/O Manager::
* i386 Timing Data Rate Monotonic Manager::
* CPU386 Timing Data Introduction::
* CPU386 Timing Data Hardware Platform::
* CPU386 Timing Data Interrupt Latency::
* CPU386 Timing Data Context Switch::
* CPU386 Timing Data Directive Times::
* CPU386 Timing Data Task Manager::
* CPU386 Timing Data Interrupt Manager::
* CPU386 Timing Data Clock Manager::
* CPU386 Timing Data Timer Manager::
* CPU386 Timing Data Semaphore Manager::
* CPU386 Timing Data Message Manager::
* CPU386 Timing Data Event Manager::
* CPU386 Timing Data Signal Manager::
* CPU386 Timing Data Partition Manager::
* CPU386 Timing Data Region Manager::
* CPU386 Timing Data Dual-Ported Memory Manager::
* CPU386 Timing Data I/O Manager::
* CPU386 Timing Data Rate Monotonic Manager::
@end menu
@end ifinfo
@ifinfo
@node i386 Timing Data Introduction, i386 Timing Data Hardware Platform, i386 Timing Data, i386 Timing Data
@node CPU386 Timing Data Introduction, CPU386 Timing Data Hardware Platform, CPU386 Timing Data, CPU386 Timing Data
@end ifinfo
@section Introduction
@@ -52,7 +52,7 @@ is a description of the interrupt latency and the context
switch times as they pertain to the i386 version of RTEMS.
@ifinfo
@node i386 Timing Data Hardware Platform, i386 Timing Data Interrupt Latency, i386 Timing Data Introduction, i386 Timing Data
@node CPU386 Timing Data Hardware Platform, CPU386 Timing Data Interrupt Latency, CPU386 Timing Data Introduction, CPU386 Timing Data
@end ifinfo
@section Hardware Platform
@@ -74,7 +74,7 @@ instructions to disable and enable interrupts, was divided by 16
to simulate a i386 executing at 16 Mhz.
@ifinfo
@node i386 Timing Data Interrupt Latency, i386 Timing Data Context Switch, i386 Timing Data Hardware Platform, i386 Timing Data
@node CPU386 Timing Data Interrupt Latency, CPU386 Timing Data Context Switch, CPU386 Timing Data Hardware Platform, CPU386 Timing Data
@end ifinfo
@section Interrupt Latency
@@ -99,7 +99,7 @@ Computers CPU386 benchmark platform using the int instruction as
the interrupt source.
@ifinfo
@node i386 Timing Data Context Switch, i386 Timing Data Directive Times, i386 Timing Data Interrupt Latency, i386 Timing Data
@node CPU386 Timing Data Context Switch, CPU386 Timing Data Directive Times, CPU386 Timing Data Interrupt Latency, CPU386 Timing Data
@end ifinfo
@section Context Switch

48
doc/supplements/i386/timedata.t
View File

@@ -12,34 +12,34 @@
@end tex
@ifinfo
@node i386 Timing Data, i386 Timing Data Introduction, Memory Requirements RTEMS RAM Workspace Worksheet, Top
@node CPU386 Timing Data, CPU386 Timing Data Introduction, Memory Requirements RTEMS RAM Workspace Worksheet, Top
@end ifinfo
@chapter i386 Timing Data
@chapter CPU386 Timing Data
@ifinfo
@menu
* i386 Timing Data Introduction::
* i386 Timing Data Hardware Platform::
* i386 Timing Data Interrupt Latency::
* i386 Timing Data Context Switch::
* i386 Timing Data Directive Times::
* i386 Timing Data Task Manager::
* i386 Timing Data Interrupt Manager::
* i386 Timing Data Clock Manager::
* i386 Timing Data Timer Manager::
* i386 Timing Data Semaphore Manager::
* i386 Timing Data Message Manager::
* i386 Timing Data Event Manager::
* i386 Timing Data Signal Manager::
* i386 Timing Data Partition Manager::
* i386 Timing Data Region Manager::
* i386 Timing Data Dual-Ported Memory Manager::
* i386 Timing Data I/O Manager::
* i386 Timing Data Rate Monotonic Manager::
* CPU386 Timing Data Introduction::
* CPU386 Timing Data Hardware Platform::
* CPU386 Timing Data Interrupt Latency::
* CPU386 Timing Data Context Switch::
* CPU386 Timing Data Directive Times::
* CPU386 Timing Data Task Manager::
* CPU386 Timing Data Interrupt Manager::
* CPU386 Timing Data Clock Manager::
* CPU386 Timing Data Timer Manager::
* CPU386 Timing Data Semaphore Manager::
* CPU386 Timing Data Message Manager::
* CPU386 Timing Data Event Manager::
* CPU386 Timing Data Signal Manager::
* CPU386 Timing Data Partition Manager::
* CPU386 Timing Data Region Manager::
* CPU386 Timing Data Dual-Ported Memory Manager::
* CPU386 Timing Data I/O Manager::
* CPU386 Timing Data Rate Monotonic Manager::
@end menu
@end ifinfo
@ifinfo
@node i386 Timing Data Introduction, i386 Timing Data Hardware Platform, i386 Timing Data, i386 Timing Data
@node CPU386 Timing Data Introduction, CPU386 Timing Data Hardware Platform, CPU386 Timing Data, CPU386 Timing Data
@end ifinfo
@section Introduction
@@ -52,7 +52,7 @@ is a description of the interrupt latency and the context
switch times as they pertain to the i386 version of RTEMS.
@ifinfo
@node i386 Timing Data Hardware Platform, i386 Timing Data Interrupt Latency, i386 Timing Data Introduction, i386 Timing Data
@node CPU386 Timing Data Hardware Platform, CPU386 Timing Data Interrupt Latency, CPU386 Timing Data Introduction, CPU386 Timing Data
@end ifinfo
@section Hardware Platform
@@ -74,7 +74,7 @@ instructions to disable and enable interrupts, was divided by 16
to simulate a i386 executing at 16 Mhz.
@ifinfo
@node i386 Timing Data Interrupt Latency, i386 Timing Data Context Switch, i386 Timing Data Hardware Platform, i386 Timing Data
@node CPU386 Timing Data Interrupt Latency, CPU386 Timing Data Context Switch, CPU386 Timing Data Hardware Platform, CPU386 Timing Data
@end ifinfo
@section Interrupt Latency
@@ -99,7 +99,7 @@ Computers CPU386 benchmark platform using the int instruction as
the interrupt source.
@ifinfo
@node i386 Timing Data Context Switch, i386 Timing Data Directive Times, i386 Timing Data Interrupt Latency, i386 Timing Data
@node CPU386 Timing Data Context Switch, CPU386 Timing Data Directive Times, CPU386 Timing Data Interrupt Latency, CPU386 Timing Data
@end ifinfo
@section Context Switch

1
doc/supplements/i960/CVME961_TIMES
View File

@@ -7,6 +7,7 @@
#
# CPU Model Information
#
RTEMS_BSP CVME961
RTEMS_CPU_MODEL i960CA
#
# Interrupt Latency

2
doc/supplements/i960/Makefile
View File

@@ -61,7 +61,7 @@ timedata.texi: timedata.t CVME961_TIMES
wksheets.t: ../../common/wksheets.t
sed -e 's/WORKSHEETS_PREVIOUS_LINK/Processor Dependent Information Table CPU Dependent Information Table/' \
-e 's/WORKSHEETS_NEXT_LINK/i960CA Timing Data/' \
-e 's/WORKSHEETS_NEXT_LINK/CVME961 Timing Data/' \
<../../common/wksheets.t >wksheets.t
wksheets.texi: wksheets.t CVME961_TIMES

4
doc/supplements/i960/i960.texi
View File

@@ -91,7 +91,7 @@ Applications Supplement.
* Processor Dependent Information Table::
* Memory Requirements::
* Timing Specification::
* i960CA Timing Data::
* CVME961 Timing Data::
* Command and Variable Index::
* Concept Index::
@end menu
@@ -102,7 +102,7 @@ Applications Supplement.
@c Need to copy the emacs stuff and "trailer stuff" (index, toc) into here
@c
@node Command and Variable Index, Concept Index, i960CA Timing Data Rate Monotonic Manager, Top
@node Command and Variable Index, Concept Index, CVME961 Timing Data Rate Monotonic Manager, Top
@unnumbered Command and Variable Index
There are currently no Command and Variable Index entries.

50
doc/supplements/i960/timeCVME961.t
View File

@@ -12,38 +12,38 @@
@end tex
@ifinfo
@node i960CA Timing Data, i960CA Timing Data Introduction, Memory Requirements RTEMS RAM Workspace Worksheet, Top
@node CVME961 Timing Data, CVME961 Timing Data Introduction, Memory Requirements RTEMS RAM Workspace Worksheet, Top
@end ifinfo
@chapter Timing Data
@ifinfo
@menu
* i960CA Timing Data Introduction::
* i960CA Timing Data Hardware Platform::
* i960CA Timing Data Interrupt Latency::
* i960CA Timing Data Context Switch::
* i960CA Timing Data Directive Times::
* i960CA Timing Data Task Manager::
* i960CA Timing Data Interrupt Manager::
* i960CA Timing Data Clock Manager::
* i960CA Timing Data Timer Manager::
* i960CA Timing Data Semaphore Manager::
* i960CA Timing Data Message Manager::
* i960CA Timing Data Event Manager::
* i960CA Timing Data Signal Manager::
* i960CA Timing Data Partition Manager::
* i960CA Timing Data Region Manager::
* i960CA Timing Data Dual-Ported Memory Manager::
* i960CA Timing Data I/O Manager::
* i960CA Timing Data Rate Monotonic Manager::
* CVME961 Timing Data Introduction::
* CVME961 Timing Data Hardware Platform::
* CVME961 Timing Data Interrupt Latency::
* CVME961 Timing Data Context Switch::
* CVME961 Timing Data Directive Times::
* CVME961 Timing Data Task Manager::
* CVME961 Timing Data Interrupt Manager::
* CVME961 Timing Data Clock Manager::
* CVME961 Timing Data Timer Manager::
* CVME961 Timing Data Semaphore Manager::
* CVME961 Timing Data Message Manager::
* CVME961 Timing Data Event Manager::
* CVME961 Timing Data Signal Manager::
* CVME961 Timing Data Partition Manager::
* CVME961 Timing Data Region Manager::
* CVME961 Timing Data Dual-Ported Memory Manager::
* CVME961 Timing Data I/O Manager::
* CVME961 Timing Data Rate Monotonic Manager::
@end menu
@end ifinfo
NOTE: The i960CA board used by the RTEMS Project to
NOTE: The CVME961 board used by the RTEMS Project to
obtain i960CA times is currently broken. The information in
this chapter was obtained using Release 3.2.1.
@ifinfo
@node i960CA Timing Data Introduction, i960CA Timing Data Hardware Platform, i960CA Timing Data, i960CA Timing Data
@node CVME961 Timing Data Introduction, CVME961 Timing Data Hardware Platform, CVME961 Timing Data, CVME961 Timing Data
@end ifinfo
@section Introduction
@@ -56,7 +56,7 @@ is a description of the interrupt latency and the context
switch times as they pertain to the i960CA version of RTEMS.
@ifinfo
@node i960CA Timing Data Hardware Platform, i960CA Timing Data Interrupt Latency, i960CA Timing Data Introduction, i960CA Timing Data
@node CVME961 Timing Data Hardware Platform, CVME961 Timing Data Interrupt Latency, CVME961 Timing Data Introduction, CVME961 Timing Data
@end ifinfo
@section Hardware Platform
@@ -79,7 +79,7 @@ disable and enable interrupts, was divided by 33 to simulate a
i960CA executing at 33 Mhz with zero wait states.
@ifinfo
@node i960CA Timing Data Interrupt Latency, i960CA Timing Data Context Switch, i960CA Timing Data Hardware Platform, i960CA Timing Data
@node CVME961 Timing Data Interrupt Latency, CVME961 Timing Data Context Switch, CVME961 Timing Data Hardware Platform, CVME961 Timing Data
@end ifinfo
@section Interrupt Latency
@@ -105,7 +105,7 @@ CVME961 benchmark platform using the sysctl instruction as the
interrupt source.
@ifinfo
@node i960CA Timing Data Context Switch, i960CA Timing Data Directive Times, i960CA Timing Data Interrupt Latency, i960CA Timing Data
@node CVME961 Timing Data Context Switch, CVME961 Timing Data Directive Times, CVME961 Timing Data Interrupt Latency, CVME961 Timing Data
@end ifinfo
@section Context Switch
@@ -117,7 +117,7 @@ when a TSWITCH user extension is configured. The use of the
TSWITCH extension is application dependent. Thus, its execution
time is not considered part of the base context switch time.
The i960CA has no hardware floating point capability
The CVME961 has no hardware floating point capability
and floating point tasks are not supported.
The following table summarizes the context switch

50
doc/supplements/i960/timedata.t
View File

@@ -12,38 +12,38 @@
@end tex
@ifinfo
@node i960CA Timing Data, i960CA Timing Data Introduction, Memory Requirements RTEMS RAM Workspace Worksheet, Top
@node CVME961 Timing Data, CVME961 Timing Data Introduction, Memory Requirements RTEMS RAM Workspace Worksheet, Top
@end ifinfo
@chapter Timing Data
@ifinfo
@menu
* i960CA Timing Data Introduction::
* i960CA Timing Data Hardware Platform::
* i960CA Timing Data Interrupt Latency::
* i960CA Timing Data Context Switch::
* i960CA Timing Data Directive Times::
* i960CA Timing Data Task Manager::
* i960CA Timing Data Interrupt Manager::
* i960CA Timing Data Clock Manager::
* i960CA Timing Data Timer Manager::
* i960CA Timing Data Semaphore Manager::
* i960CA Timing Data Message Manager::
* i960CA Timing Data Event Manager::
* i960CA Timing Data Signal Manager::
* i960CA Timing Data Partition Manager::
* i960CA Timing Data Region Manager::
* i960CA Timing Data Dual-Ported Memory Manager::
* i960CA Timing Data I/O Manager::
* i960CA Timing Data Rate Monotonic Manager::
* CVME961 Timing Data Introduction::
* CVME961 Timing Data Hardware Platform::
* CVME961 Timing Data Interrupt Latency::
* CVME961 Timing Data Context Switch::
* CVME961 Timing Data Directive Times::
* CVME961 Timing Data Task Manager::
* CVME961 Timing Data Interrupt Manager::
* CVME961 Timing Data Clock Manager::
* CVME961 Timing Data Timer Manager::
* CVME961 Timing Data Semaphore Manager::
* CVME961 Timing Data Message Manager::
* CVME961 Timing Data Event Manager::
* CVME961 Timing Data Signal Manager::
* CVME961 Timing Data Partition Manager::
* CVME961 Timing Data Region Manager::
* CVME961 Timing Data Dual-Ported Memory Manager::
* CVME961 Timing Data I/O Manager::
* CVME961 Timing Data Rate Monotonic Manager::
@end menu
@end ifinfo
NOTE: The i960CA board used by the RTEMS Project to
NOTE: The CVME961 board used by the RTEMS Project to
obtain i960CA times is currently broken. The information in
this chapter was obtained using Release 3.2.1.
@ifinfo
@node i960CA Timing Data Introduction, i960CA Timing Data Hardware Platform, i960CA Timing Data, i960CA Timing Data
@node CVME961 Timing Data Introduction, CVME961 Timing Data Hardware Platform, CVME961 Timing Data, CVME961 Timing Data
@end ifinfo
@section Introduction
@@ -56,7 +56,7 @@ is a description of the interrupt latency and the context
switch times as they pertain to the i960CA version of RTEMS.
@ifinfo
@node i960CA Timing Data Hardware Platform, i960CA Timing Data Interrupt Latency, i960CA Timing Data Introduction, i960CA Timing Data
@node CVME961 Timing Data Hardware Platform, CVME961 Timing Data Interrupt Latency, CVME961 Timing Data Introduction, CVME961 Timing Data
@end ifinfo
@section Hardware Platform
@@ -79,7 +79,7 @@ disable and enable interrupts, was divided by 33 to simulate a
i960CA executing at 33 Mhz with zero wait states.
@ifinfo
@node i960CA Timing Data Interrupt Latency, i960CA Timing Data Context Switch, i960CA Timing Data Hardware Platform, i960CA Timing Data
@node CVME961 Timing Data Interrupt Latency, CVME961 Timing Data Context Switch, CVME961 Timing Data Hardware Platform, CVME961 Timing Data
@end ifinfo
@section Interrupt Latency
@@ -105,7 +105,7 @@ CVME961 benchmark platform using the sysctl instruction as the
interrupt source.
@ifinfo
@node i960CA Timing Data Context Switch, i960CA Timing Data Directive Times, i960CA Timing Data Interrupt Latency, i960CA Timing Data
@node CVME961 Timing Data Context Switch, CVME961 Timing Data Directive Times, CVME961 Timing Data Interrupt Latency, CVME961 Timing Data
@end ifinfo
@section Context Switch
@@ -117,7 +117,7 @@ when a TSWITCH user extension is configured. The use of the
TSWITCH extension is application dependent. Thus, its execution
time is not considered part of the base context switch time.
The i960CA has no hardware floating point capability
The CVME961 has no hardware floating point capability
and floating point tasks are not supported.
The following table summarizes the context switch

1
doc/supplements/m68k/MVME136_TIMES
View File

@@ -7,6 +7,7 @@
#
# CPU Model Information
#
RTEMS_BSP MVME136
RTEMS_CPU_MODEL MC68020
#
# Interrupt Latency

2
doc/supplements/m68k/Makefile
View File

@@ -61,7 +61,7 @@ timedata.texi: timedata.t MVME136_TIMES
wksheets.t: ../../common/wksheets.t
sed -e 's/WORKSHEETS_PREVIOUS_LINK/Processor Dependent Information Table CPU Dependent Information Table/' \
-e 's/WORKSHEETS_NEXT_LINK/MC68020 Timing Data/' \
-e 's/WORKSHEETS_NEXT_LINK/MVME136 Timing Data/' \
<../../common/wksheets.t >wksheets.t
wksheets.texi: wksheets.t MVME136_TIMES

4
doc/supplements/m68k/m68k.texi
View File

@@ -92,7 +92,7 @@ Applications Supplement.
* Processor Dependent Information Table::
* Memory Requirements::
* Timing Specification::
* MC68020 Timing Data::
* MVME136 Timing Data::
* Command and Variable Index::
* Concept Index::
@end menu
@@ -103,7 +103,7 @@ Applications Supplement.
@c Need to copy the emacs stuff and "trailer stuff" (index, toc) into here
@c
@node Command and Variable Index, Concept Index, MC68020 Timing Data Rate Monotonic Manager, Top
@node Command and Variable Index, Concept Index, MVME136 Timing Data Rate Monotonic Manager, Top
@unnumbered Command and Variable Index
There are currently no Command and Variable Index entries.

48
doc/supplements/m68k/timeMVME136.t
View File

@@ -12,34 +12,34 @@
@end tex
@ifinfo
@node MC68020 Timing Data, MC68020 Timing Data Introduction, Memory Requirements RTEMS RAM Workspace Worksheet, Top
@node MVME136 Timing Data, MVME136 Timing Data Introduction, Memory Requirements RTEMS RAM Workspace Worksheet, Top
@end ifinfo
@chapter MC68020 Timing Data
@chapter MVME136 Timing Data
@ifinfo
@menu
* MC68020 Timing Data Introduction::
* MC68020 Timing Data Hardware Platform::
* MC68020 Timing Data Interrupt Latency::
* MC68020 Timing Data Context Switch::
* MC68020 Timing Data Directive Times::
* MC68020 Timing Data Task Manager::
* MC68020 Timing Data Interrupt Manager::
* MC68020 Timing Data Clock Manager::
* MC68020 Timing Data Timer Manager::
* MC68020 Timing Data Semaphore Manager::
* MC68020 Timing Data Message Manager::
* MC68020 Timing Data Event Manager::
* MC68020 Timing Data Signal Manager::
* MC68020 Timing Data Partition Manager::
* MC68020 Timing Data Region Manager::
* MC68020 Timing Data Dual-Ported Memory Manager::
* MC68020 Timing Data I/O Manager::
* MC68020 Timing Data Rate Monotonic Manager::
* MVME136 Timing Data Introduction::
* MVME136 Timing Data Hardware Platform::
* MVME136 Timing Data Interrupt Latency::
* MVME136 Timing Data Context Switch::
* MVME136 Timing Data Directive Times::
* MVME136 Timing Data Task Manager::
* MVME136 Timing Data Interrupt Manager::
* MVME136 Timing Data Clock Manager::
* MVME136 Timing Data Timer Manager::
* MVME136 Timing Data Semaphore Manager::
* MVME136 Timing Data Message Manager::
* MVME136 Timing Data Event Manager::
* MVME136 Timing Data Signal Manager::
* MVME136 Timing Data Partition Manager::
* MVME136 Timing Data Region Manager::
* MVME136 Timing Data Dual-Ported Memory Manager::
* MVME136 Timing Data I/O Manager::
* MVME136 Timing Data Rate Monotonic Manager::
@end menu
@end ifinfo
@ifinfo
@node MC68020 Timing Data Introduction, MC68020 Timing Data Hardware Platform, MC68020 Timing Data, MC68020 Timing Data
@node MVME136 Timing Data Introduction, MVME136 Timing Data Hardware Platform, MVME136 Timing Data, MVME136 Timing Data
@end ifinfo
@section Introduction
@@ -52,7 +52,7 @@ is a description of the interrupt latency and the context switch
times as they pertain to the MC68020 version of RTEMS.
@ifinfo
@node MC68020 Timing Data Hardware Platform, MC68020 Timing Data Interrupt Latency, MC68020 Timing Data Introduction, MC68020 Timing Data
@node MVME136 Timing Data Hardware Platform, MVME136 Timing Data Interrupt Latency, MVME136 Timing Data Introduction, MVME136 Timing Data
@end ifinfo
@section Hardware Platform
@@ -78,7 +78,7 @@ MC68020 assume that the internal cache is disabled and that no
instructions overlap.
@ifinfo
@node MC68020 Timing Data Interrupt Latency, MC68020 Timing Data Context Switch, MC68020 Timing Data Hardware Platform, MC68020 Timing Data
@node MVME136 Timing Data Interrupt Latency, MVME136 Timing Data Context Switch, MVME136 Timing Data Hardware Platform, MVME136 Timing Data
@end ifinfo
@section Interrupt Latency
@@ -105,7 +105,7 @@ using the Multiprocessing Communications registers to generate
as the interrupt source.
@ifinfo
@node MC68020 Timing Data Context Switch, MC68020 Timing Data Directive Times, MC68020 Timing Data Interrupt Latency, MC68020 Timing Data
@node MVME136 Timing Data Context Switch, MVME136 Timing Data Directive Times, MVME136 Timing Data Interrupt Latency, MVME136 Timing Data
@end ifinfo
@section Context Switch

48
doc/supplements/m68k/timedata.t
View File

@@ -12,34 +12,34 @@
@end tex
@ifinfo
@node MC68020 Timing Data, MC68020 Timing Data Introduction, Memory Requirements RTEMS RAM Workspace Worksheet, Top
@node MVME136 Timing Data, MVME136 Timing Data Introduction, Memory Requirements RTEMS RAM Workspace Worksheet, Top
@end ifinfo
@chapter MC68020 Timing Data
@chapter MVME136 Timing Data
@ifinfo
@menu
* MC68020 Timing Data Introduction::
* MC68020 Timing Data Hardware Platform::
* MC68020 Timing Data Interrupt Latency::
* MC68020 Timing Data Context Switch::
* MC68020 Timing Data Directive Times::
* MC68020 Timing Data Task Manager::
* MC68020 Timing Data Interrupt Manager::
* MC68020 Timing Data Clock Manager::
* MC68020 Timing Data Timer Manager::
* MC68020 Timing Data Semaphore Manager::
* MC68020 Timing Data Message Manager::
* MC68020 Timing Data Event Manager::
* MC68020 Timing Data Signal Manager::
* MC68020 Timing Data Partition Manager::
* MC68020 Timing Data Region Manager::
* MC68020 Timing Data Dual-Ported Memory Manager::
* MC68020 Timing Data I/O Manager::
* MC68020 Timing Data Rate Monotonic Manager::
* MVME136 Timing Data Introduction::
* MVME136 Timing Data Hardware Platform::
* MVME136 Timing Data Interrupt Latency::
* MVME136 Timing Data Context Switch::
* MVME136 Timing Data Directive Times::
* MVME136 Timing Data Task Manager::
* MVME136 Timing Data Interrupt Manager::
* MVME136 Timing Data Clock Manager::
* MVME136 Timing Data Timer Manager::
* MVME136 Timing Data Semaphore Manager::
* MVME136 Timing Data Message Manager::
* MVME136 Timing Data Event Manager::
* MVME136 Timing Data Signal Manager::
* MVME136 Timing Data Partition Manager::
* MVME136 Timing Data Region Manager::
* MVME136 Timing Data Dual-Ported Memory Manager::
* MVME136 Timing Data I/O Manager::
* MVME136 Timing Data Rate Monotonic Manager::
@end menu
@end ifinfo
@ifinfo
@node MC68020 Timing Data Introduction, MC68020 Timing Data Hardware Platform, MC68020 Timing Data, MC68020 Timing Data
@node MVME136 Timing Data Introduction, MVME136 Timing Data Hardware Platform, MVME136 Timing Data, MVME136 Timing Data
@end ifinfo
@section Introduction
@@ -52,7 +52,7 @@ is a description of the interrupt latency and the context switch
times as they pertain to the MC68020 version of RTEMS.
@ifinfo
@node MC68020 Timing Data Hardware Platform, MC68020 Timing Data Interrupt Latency, MC68020 Timing Data Introduction, MC68020 Timing Data
@node MVME136 Timing Data Hardware Platform, MVME136 Timing Data Interrupt Latency, MVME136 Timing Data Introduction, MVME136 Timing Data
@end ifinfo
@section Hardware Platform
@@ -78,7 +78,7 @@ MC68020 assume that the internal cache is disabled and that no
instructions overlap.
@ifinfo
@node MC68020 Timing Data Interrupt Latency, MC68020 Timing Data Context Switch, MC68020 Timing Data Hardware Platform, MC68020 Timing Data
@node MVME136 Timing Data Interrupt Latency, MVME136 Timing Data Context Switch, MVME136 Timing Data Hardware Platform, MVME136 Timing Data
@end ifinfo
@section Interrupt Latency
@@ -105,7 +105,7 @@ using the Multiprocessing Communications registers to generate
as the interrupt source.
@ifinfo
@node MC68020 Timing Data Context Switch, MC68020 Timing Data Directive Times, MC68020 Timing Data Interrupt Latency, MC68020 Timing Data
@node MVME136 Timing Data Context Switch, MVME136 Timing Data Directive Times, MVME136 Timing Data Interrupt Latency, MVME136 Timing Data
@end ifinfo
@section Context Switch

1
doc/supplements/sparc/ERC32_TIMES
View File

@@ -7,6 +7,7 @@
#
# CPU Model Information
#
RTEMS_BSP ERC32
RTEMS_CPU_MODEL ERC32
#
# Interrupt Latency

1
doc/supplements/sparc/SIS_TIMES
View File

@@ -7,6 +7,7 @@
#
# CPU Model Information
#
RTEMS_BSP ERC32
RTEMS_CPU_MODEL ERC32
#
# Interrupt Latency