Imagelibrary/rtems
1
0
Fork 1
mirror of https://gitlab.rtems.org/rtems/rtos/rtems.git synced 2025-12-26 06:08:20 +00:00
Code Issues Packages Projects Releases Wiki Activity

Patch from Daniel Kelley <dank@icube.com>:

Browse Source 
I found a small buglet in the mips64orion _CPU_ISR_Set_level; the
    original was wiping out the level argument, and then comparing the
    current interrupt level with some random value of v0. See patch below.
This commit is contained in:
Joel Sherrill
1999-05-18 17:41:16 +00:00
parent fbec4a149f
commit 5a064dca14
4 changed files with 16 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
c/src/exec/score/cpu/mips/cpu_asm.S
View File

@@ -153,12 +153,12 @@ ENDFRAME(_CPU_ISR_Get_level)
FRAME(_CPU_ISR_Set_level,sp,0,ra)
nop
mfc0 a0,C0_SR
mfc0 v0,C0_SR
nop
andi a0,SR_EXL
beqz a0,_CPU_ISR_Set_1 /* normalize a0 */
andi v0,SR_EXL
beqz v0,_CPU_ISR_Set_1 /* normalize v0 */
nop
li a0,1
li v0,1
_CPU_ISR_Set_1:
beq v0,a0,_CPU_ISR_Set_exit /* if (current_level != new_level ) */
nop

8
c/src/exec/score/cpu/mips64orion/cpu_asm.S
View File

@@ -153,12 +153,12 @@ ENDFRAME(_CPU_ISR_Get_level)
FRAME(_CPU_ISR_Set_level,sp,0,ra)
nop
mfc0 a0,C0_SR
mfc0 v0,C0_SR
nop
andi a0,SR_EXL
beqz a0,_CPU_ISR_Set_1 /* normalize a0 */
andi v0,SR_EXL
beqz v0,_CPU_ISR_Set_1 /* normalize v0 */
nop
li a0,1
li v0,1
_CPU_ISR_Set_1:
beq v0,a0,_CPU_ISR_Set_exit /* if (current_level != new_level ) */
nop