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2006-01-16 Joel Sherrill <joel@OARcorp.com>

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* rtems/new-exceptions/cpu.h, rtems/old-exceptions/cpu.h,
	rtems/score/cpu.h: Part of a large patch to improve Doxygen output.
	As a side-effect, grammar and spelling errors were corrected, spacing
	errors were address, and some variable names were improved.
This commit is contained in:
Joel Sherrill
2006-01-16 15:12:30 +00:00
parent 22b3bedc4a
commit 5961b4c784
4 changed files with 13 additions and 8 deletions
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7
cpukit/score/cpu/powerpc/ChangeLog
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@@ -1,3 +1,10 @@
2006-01-16 Joel Sherrill <joel@OARcorp.com>
* rtems/new-exceptions/cpu.h, rtems/old-exceptions/cpu.h,
rtems/score/cpu.h: Part of a large patch to improve Doxygen output.
As a side-effect, grammar and spelling errors were corrected, spacing
errors were address, and some variable names were improved.
2005-11-08 Ralf Corsepius <ralf.corsepius@rtems.org> 2005-11-08 Ralf Corsepius <ralf.corsepius@rtems.org>
* rtems/score/types.h: Eliminate unsigned16, unsigned32. * rtems/score/types.h: Eliminate unsigned16, unsigned32.

5
cpukit/score/cpu/powerpc/rtems/new-exceptions/cpu.h
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@@ -23,7 +23,7 @@
* *
* Derived from c/src/exec/cpu/no_cpu/cpu.h: * Derived from c/src/exec/cpu/no_cpu/cpu.h:
* *
* COPYRIGHT (c) 1989-1997. * COPYRIGHT (c) 1989-2006.
* On-Line Applications Research Corporation (OAR). * On-Line Applications Research Corporation (OAR).
* *
* The license and distribution terms for this file may be found in * The license and distribution terms for this file may be found in
@@ -97,8 +97,7 @@ extern "C" {
* If TRUE, then the memory is allocated during initialization. * If TRUE, then the memory is allocated during initialization.
* If FALSE, then the memory is allocated during initialization. * If FALSE, then the memory is allocated during initialization.
* *
* This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
* or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
*/ */
#define CPU_ALLOCATE_INTERRUPT_STACK FALSE #define CPU_ALLOCATE_INTERRUPT_STACK FALSE

5
cpukit/score/cpu/powerpc/rtems/old-exceptions/cpu.h
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@@ -20,7 +20,7 @@
* *
* Derived from c/src/exec/cpu/no_cpu/cpu.h: * Derived from c/src/exec/cpu/no_cpu/cpu.h:
* *
* COPYRIGHT (c) 1989-1997. * COPYRIGHT (c) 1989-2006.
* On-Line Applications Research Corporation (OAR). * On-Line Applications Research Corporation (OAR).
* *
* The license and distribution terms for this file may in * The license and distribution terms for this file may in
@@ -102,8 +102,7 @@ typedef void ( *ppc_isr_entry )( int, struct CPU_Interrupt_frame * );
* If TRUE, then the memory is allocated during initialization. * If TRUE, then the memory is allocated during initialization.
* If FALSE, then the memory is allocated during initialization. * If FALSE, then the memory is allocated during initialization.
* *
* This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
* or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
*/ */
#define CPU_ALLOCATE_INTERRUPT_STACK TRUE #define CPU_ALLOCATE_INTERRUPT_STACK TRUE

4
cpukit/score/cpu/powerpc/rtems/score/cpu.h
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@@ -299,7 +299,7 @@ typedef struct CPU_Interrupt_frame {
#endif #endif
/* /*
* Should be large enough to run all RTEMS tests. This insures * Should be large enough to run all RTEMS tests. This ensures
* that a "reasonable" small application should not have any problems. * that a "reasonable" small application should not have any problems.
*/ */
@@ -365,7 +365,7 @@ typedef struct CPU_Interrupt_frame {
* Some CPUs have special instructions which swap a 32-bit quantity in * Some CPUs have special instructions which swap a 32-bit quantity in
* a single instruction (e.g. i486). It is probably best to avoid * a single instruction (e.g. i486). It is probably best to avoid
* an "endian swapping control bit" in the CPU. One good reason is * an "endian swapping control bit" in the CPU. One good reason is
* that interrupts would probably have to be disabled to insure that * that interrupts would probably have to be disabled to ensure that
* an interrupt does not try to access the same "chunk" with the wrong * an interrupt does not try to access the same "chunk" with the wrong
* endian. Another good reason is that on some CPUs, the endian bit * endian. Another good reason is that on some CPUs, the endian bit
* endianness for ALL fetches -- both code and data -- so the code * endianness for ALL fetches -- both code and data -- so the code