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2005-04-11 Jennifer Averett<jennifer.averett@oarcorp.com>

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PR 778/bsps
	* include/bsp.h, include/gen2.h, startup/FPGA.c, startup/Hwr_init.c,
	startup/bspstart.c, tod/tod.c:
        modify SCORE_.. to BSP_.. for externally used define's.
This commit is contained in:
Jennifer Averett
2005-04-11 20:18:20 +00:00
parent 64c3f790a2
commit 53923e8377
7 changed files with 61 additions and 49 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
c/src/lib/libbsp/powerpc/score603e/ChangeLog
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@@ -1,3 +1,10 @@
2005-04-11 Jennifer Averett<jennifer.averett@oarcorp.com>
PR 778/bsps
* include/bsp.h, include/gen2.h, startup/FPGA.c, startup/Hwr_init.c,
startup/bspstart.c, tod/tod.c:
modify SCORE_.. to BSP_.. for externally used define's.
2003-09-04 Joel Sherrill <joel@OARcorp.com>
* PCI_bus/PCI.h, clock/clock.c, console/85c30.c, console/85c30.h,

8
c/src/lib/libbsp/powerpc/score603e/include/bsp.h
View File

@@ -69,7 +69,10 @@ extern "C" {
#define Initialize_Board_ctrl_register() \
*SCORE603E_BOARD_CTRL_REG = (*SCORE603E_BOARD_CTRL_REG | \
SCORE603E_BRD_FLASH_DISABLE_MASK) \
SCORE603E_BRD_FLASH_DISABLE_MASK)
#define Processor_Synchronize() \
asm(" eieio ")
/*
* Define the time limits for RTEMS Test Suite test durations.
@@ -249,6 +252,9 @@ unsigned int SCORE603e_FLASH_Enable_writes(
rtems_unsigned32 area /* Unused */
);
#define BSP_FLASH_ENABLE_WRITES( _area) SCORE603e_FLASH_Enable_writes( _area )
#define BSP_FLASH_DISABLE_WRITES(_area) SCORE603e_FLASH_Disable( _area )
#define Convert_Endian_32( _data ) \
( ((_data&0x000000ff)<<24) | ((_data&0x0000ff00)<<8) | \
((_data&0x00ff0000)>>8) | ((_data&0xff000000)>>24) )

67
c/src/lib/libbsp/powerpc/score603e/include/gen2.h
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@@ -25,7 +25,7 @@ extern "C" {
* ISA/PCI I/O space.
*/
#define SCORE603E_VME_JUMPER_ADDR 0x00e20000
#define SCORE603E_FLASH_BASE_ADDR 0x04000000
#define BSP_FLASH_BASE 0x04000000
#define SCORE603E_ISA_PCI_IO_BASE 0x80000000
#define SCORE603E_TIMER_PORT_C 0xfd000000
#define SCORE603E_TIMER_INT_ACK 0xfd000000
@@ -47,62 +47,61 @@ extern "C" {
/*
* PSC8 - PMC Card
*/
#define SCORE603E_PCI_CONFIGURATION_BASE 0x80800000
#define SCORE603E_PMC_BASE SCORE603E_PCI_CONFIGURATION_BASE
#define SCORE603E_PCI_PMC_DEVICE_BASE 0x80808000
#define BSP_PCI_CONFIGURATION_BASE 0x80800000
#define BSP_PMC_BASE BSP_PCI_CONFIGURATION_BASE
#define BSP_PCI_PMC_DEVICE_BASE 0x80808000
#define SCORE603E_PCI_REGISTER_BASE 0xfc000000
#define BSP_PCI_REGISTER_BASE 0xfc000000
#define SCORE603E_PCI_DEVICE_ADDRESS( _offset) \
((volatile rtems_unsigned32 *)( SCORE603E_PCI_PMC_DEVICE_BASE + _offset ))
#define BSP_PCI_DEVICE_ADDRESS( _offset) \
((volatile rtems_unsigned32 *)( BSP_PCI_PMC_DEVICE_BASE + _offset ))
#define SCORE603E_PMC_SERIAL_ADDRESS( _offset ) \
((volatile rtems_unsigned8 *)(SCORE603E_PCI_REGISTER_BASE + _offset))
#define BSP_PMC_SERIAL_ADDRESS( _offset ) \
((volatile rtems_unsigned8 *)(BSP_PCI_REGISTER_BASE + _offset))
/*
* PMC serial channels - (4-7: 232 and 8-11: 422)
*/
#define SCORE603E_85C30_CTRL_4 SCORE603E_PMC_SERIAL_ADDRESS(0x200020)
#define SCORE603E_85C30_DATA_4 SCORE603E_PMC_SERIAL_ADDRESS(0x200024)
#define SCORE603E_85C30_CTRL_5 SCORE603E_PMC_SERIAL_ADDRESS(0x200028)
#define SCORE603E_85C30_DATA_5 SCORE603E_PMC_SERIAL_ADDRESS(0x20002c)
#define SCORE603E_85C30_CTRL_6 SCORE603E_PMC_SERIAL_ADDRESS(0x200030)
#define SCORE603E_85C30_DATA_6 SCORE603E_PMC_SERIAL_ADDRESS(0x200034)
#define SCORE603E_85C30_CTRL_7 SCORE603E_PMC_SERIAL_ADDRESS(0x200038)
#define SCORE603E_85C30_DATA_7 SCORE603E_PMC_SERIAL_ADDRESS(0x20003c)
#define SCORE603E_85C30_CTRL_8 SCORE603E_PMC_SERIAL_ADDRESS(0x200000)
#define SCORE603E_85C30_DATA_8 SCORE603E_PMC_SERIAL_ADDRESS(0x200004)
#define SCORE603E_85C30_CTRL_9 SCORE603E_PMC_SERIAL_ADDRESS(0x200008)
#define SCORE603E_85C30_DATA_9 SCORE603E_PMC_SERIAL_ADDRESS(0x20000c)
#define SCORE603E_85C30_CTRL_10 SCORE603E_PMC_SERIAL_ADDRESS(0x200010)
#define SCORE603E_85C30_DATA_10 SCORE603E_PMC_SERIAL_ADDRESS(0x200014)
#define SCORE603E_85C30_CTRL_11 SCORE603E_PMC_SERIAL_ADDRESS(0x200018)
#define SCORE603E_85C30_DATA_11 SCORE603E_PMC_SERIAL_ADDRESS(0x20001c)
#define SCORE603E_85C30_CTRL_4 BSP_PMC_SERIAL_ADDRESS(0x200020)
#define SCORE603E_85C30_DATA_4 BSP_PMC_SERIAL_ADDRESS(0x200024)
#define SCORE603E_85C30_CTRL_5 BSP_PMC_SERIAL_ADDRESS(0x200028)
#define SCORE603E_85C30_DATA_5 BSP_PMC_SERIAL_ADDRESS(0x20002c)
#define SCORE603E_85C30_CTRL_6 BSP_PMC_SERIAL_ADDRESS(0x200030)
#define SCORE603E_85C30_DATA_6 BSP_PMC_SERIAL_ADDRESS(0x200034)
#define SCORE603E_85C30_CTRL_7 BSP_PMC_SERIAL_ADDRESS(0x200038)
#define SCORE603E_85C30_DATA_7 BSP_PMC_SERIAL_ADDRESS(0x20003c)
#define SCORE603E_85C30_CTRL_8 BSP_PMC_SERIAL_ADDRESS(0x200000)
#define SCORE603E_85C30_DATA_8 BSP_PMC_SERIAL_ADDRESS(0x200004)
#define SCORE603E_85C30_CTRL_9 BSP_PMC_SERIAL_ADDRESS(0x200008)
#define SCORE603E_85C30_DATA_9 BSP_PMC_SERIAL_ADDRESS(0x20000c)
#define SCORE603E_85C30_CTRL_10 BSP_PMC_SERIAL_ADDRESS(0x200010)
#define SCORE603E_85C30_DATA_10 BSP_PMC_SERIAL_ADDRESS(0x200014)
#define SCORE603E_85C30_CTRL_11 BSP_PMC_SERIAL_ADDRESS(0x200018)
#define SCORE603E_85C30_DATA_11 BSP_PMC_SERIAL_ADDRESS(0x20001c)
#define SCORE603E_PCI_IO_CFG_ADDR 0x80000cf8
#define SCORE603E_PCI_IO_CFG_DATA 0x80000cfc
#define SCORE603E_UNIVERSE_BASE 0x80030000
#define SCORE603E_IO_VME_UNIVERSE_BASE 0x80007000
#define SCORE603E_PCI_MEM_BASE 0xc0000000
#define SCORE603E_NVRAM_BASE 0xfd100000
#define SCORE603E_RTC_ADDRESS ((volatile unsigned char *)0xfd180000)
#define BSP_PCI_MEM_BASE 0xc0000000
#define BSP_NVRAM_BASE 0xfd100000
#define BSP_RTC_ADDRESS ((volatile unsigned char *)0xfd180000)
#define SCORE603E_JP1_JP2_PROM_BASE 0xfff00000
#define SCORE603E_NOT_JP1_2_FLASH_BASE 0xff800000
#if (SCORE603E_USE_SDS) | (SCORE603E_USE_OPEN_FIRMWARE) | (SCORE603E_USE_NONE)
#define SCORE603E_VME_A16_OFFSET 0x04000000
#elif (SCORE603E_USE_DINK)
#define SCORE603E_VME_A16_OFFSET 0x11000000
#define SCORE603E_VME_A24_OFFSET 0x10000000
#define SCORE603E_VME_A24_BASE (SCORE603E_PCI_MEM_BASE+SCORE603E_VME_A24_OFFSET)
#define BSP_VME_A24_BASE (BSP_PCI_MEM_BASE+SCORE603E_VME_A24_OFFSET)
#else
#error "SCORE603E gen2.h -- what ROM monitor are you using"
#endif
#define SCORE603E_VME_A16_BASE (SCORE603E_PCI_MEM_BASE+SCORE603E_VME_A16_OFFSET)
#define BSP_VME_A16_BASE (BSP_PCI_MEM_BASE+SCORE603E_VME_A16_OFFSET)
/*
* Definations for the ICM 1770 RTC chip
@@ -115,7 +114,7 @@ extern "C" {
#define ICM1770_CRYSTAL_FREQ_2M 0x02
#define ICM1770_CRYSTAL_FREQ_4M 0x03
#define SCORE_RTC_FREQUENCY ICM1770_CRYSTAL_FREQ_32K
#define BSP_RTC_FREQUENCY ICM1770_CRYSTAL_FREQ_32K
/*
* Z85C30 Definations for the 423 interface.
@@ -158,13 +157,13 @@ extern "C" {
/*
* The PMC status word is at the PMC base address
*/
#define SCORE603E_PMC_STATUS_ADDRESS (SCORE603E_PMC_SERIAL_ADDRESS (0))
#define BSP_PMC_STATUS_ADDRESS (BSP_PMC_SERIAL_ADDRESS (0))
#define Is_PMC_85C30_4_IRQ( _status ) (_status & 0x80) /* SCC 422-1 */
#define Is_PMC_85C30_2_IRQ( _status ) (_status & 0x40) /* SCC 232-1 */
#define Is_PMC_85C30_5_IRQ( _status ) (_status & 0x20) /* SCC 422-2 */
#define Is_PMC_85C30_3_IRQ( _status ) (_status & 0x08) /* SCC 232-2 */
#define SCORE603E_PMC_CONTROL_ADDRESS SCORE603E_PMC_SERIAL_ADDRESS(0x100000)
#define SCORE603E_PMC_CONTROL_ADDRESS BSP_PMC_SERIAL_ADDRESS(0x100000)
#define SCORE603E_PMC_SCC_232_LOOPBACK (_word) (_word|0x20)
#define PMC_SET_232_LOOPBACK(_word) (_word | 0x02)

2
c/src/lib/libbsp/powerpc/score603e/startup/FPGA.c
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@@ -115,7 +115,7 @@ rtems_unsigned16 read_and_clear_PMC_irq(
{
rtems_unsigned16 status_word = irq;
status_word = (*SCORE603E_PMC_STATUS_ADDRESS);
status_word = (*BSP_PMC_STATUS_ADDRESS);
return status_word;
}

2
c/src/lib/libbsp/powerpc/score603e/startup/Hwr_init.c
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@@ -76,7 +76,7 @@ void init_RTC()
{
volatile Harris_RTC *the_RTC;
the_RTC = (volatile Harris_RTC *)SCORE603E_RTC_ADDRESS;
the_RTC = (volatile Harris_RTC *)BSP_RTC_ADDRESS;
the_RTC->command_register = 0x0;
}

16
c/src/lib/libbsp/powerpc/score603e/startup/bspstart.c
View File

@@ -116,20 +116,20 @@ void initialize_PMC() {
/*
* set PMC base address.
*/
PMC_addr = SCORE603E_PCI_DEVICE_ADDRESS( 0x14 );
*PMC_addr = (SCORE603E_PCI_REGISTER_BASE >> 24) & 0x3f;
PMC_addr = BSP_PCI_DEVICE_ADDRESS( 0x14 );
*PMC_addr = (BSP_PCI_REGISTER_BASE >> 24) & 0x3f;
/*
* Clear status, enable SERR and memory space only.
*/
PMC_addr = SCORE603E_PCI_DEVICE_ADDRESS( 0x4 );
PMC_addr = BSP_PCI_DEVICE_ADDRESS( 0x4 );
*PMC_addr = 0x0201ff37;
/*
* Bit 0 and 1 HI cause Medium Loopback to occur.
*/
PMC_addr = (volatile rtems_unsigned32 *)
SCORE603E_PMC_SERIAL_ADDRESS( 0x100000 );
BSP_PMC_SERIAL_ADDRESS( 0x100000 );
data = *PMC_addr;
/* *PMC_addr = data | 0x3; */
*PMC_addr = data & 0xfc;
@@ -142,17 +142,17 @@ void initialize_PMC() {
/*
* Clear status, enable SERR and memory space only.
*/
PMC_addr = SCORE603E_PCI_DEVICE_ADDRESS( 0x4 );
PMC_addr = BSP_PCI_DEVICE_ADDRESS( 0x4 );
*PMC_addr = 0x020080cc;
/*
* set PMC base address.
*/
PMC_addr = SCORE603E_PCI_DEVICE_ADDRESS( 0x14 );
*PMC_addr = (SCORE603E_PCI_REGISTER_BASE >> 24) & 0x3f;
PMC_addr = BSP_PCI_DEVICE_ADDRESS( 0x14 );
*PMC_addr = (BSP_PCI_REGISTER_BASE >> 24) & 0x3f;
PMC_addr = (volatile rtems_unsigned32 *)
SCORE603E_PMC_SERIAL_ADDRESS( 0x100000 );
BSP_PMC_SERIAL_ADDRESS( 0x100000 );
data = *PMC_addr;
*PMC_addr = data & 0xfc;

6
c/src/lib/libbsp/powerpc/score603e/tod/tod.c
View File

@@ -43,7 +43,7 @@ void setRealTimeToRTEMS()
{
rtems_time_of_day rtc_tod;
ICM7170_GetTOD( SCORE603E_RTC_ADDRESS, SCORE_RTC_FREQUENCY, &rtc_tod );
ICM7170_GetTOD( BSP_RTC_ADDRESS, BSP_RTC_FREQUENCY, &rtc_tod );
rtems_clock_set( &rtc_tod );
}
@@ -52,7 +52,7 @@ void setRealTimeFromRTEMS()
rtems_time_of_day rtems_tod;
rtems_clock_get( RTEMS_CLOCK_GET_TOD, &rtems_tod );
ICM7170_SetTOD( SCORE603E_RTC_ADDRESS, SCORE_RTC_FREQUENCY, &rtems_tod );
ICM7170_SetTOD( BSP_RTC_ADDRESS, BSP_RTC_FREQUENCY, &rtems_tod );
}
int checkRealTime()
@@ -60,7 +60,7 @@ int checkRealTime()
rtems_time_of_day rtems_tod;
rtems_time_of_day rtc_tod;
ICM7170_GetTOD( SCORE603E_RTC_ADDRESS, SCORE_RTC_FREQUENCY, &rtc_tod );
ICM7170_GetTOD( BSP_RTC_ADDRESS, BSP_RTC_FREQUENCY, &rtc_tod );
rtems_clock_get( RTEMS_CLOCK_GET_TOD, &rtems_tod );
if( rtems_tod.year == rtc_tod.year &&