From 52448f35e958eaee3c299f27607ef48ff6298176 Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Mon, 3 Apr 2000 13:57:34 +0000 Subject: [PATCH] Patch from Jay Kulpinski that addresses a floating point support problem discovered with the mvme2307 BSP. A floating point not available exception would occur when trying to switch to a new thread with the floating point attribute. Floating point instructions were disabled, but floating point loads and stores were needed to save and/or restore the context. --- c/src/lib/libbsp/powerpc/shared/irq/irq_asm.S | 7 +++++++ c/src/lib/libbsp/powerpc/shared/start/start.S | 7 ++++++- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/c/src/lib/libbsp/powerpc/shared/irq/irq_asm.S b/c/src/lib/libbsp/powerpc/shared/irq/irq_asm.S index 0d8ab62452..9e77146e11 100644 --- a/c/src/lib/libbsp/powerpc/shared/irq/irq_asm.S +++ b/c/src/lib/libbsp/powerpc/shared/irq/irq_asm.S @@ -85,8 +85,15 @@ SYM (shared_raw_irq_code_entry): stw r2, SRR1_FRAME_OFFSET(r1) /* * Enable data and instruction address translation, exception recovery + * + * also, on CPUs with FP, enable FP so that FP context can be + * saved and restored (using FP instructions) */ +#if (PPC_HAS_FPU == 0) ori r3, r3, MSR_RI | MSR_IR | MSR_DR +#else + ori r3, r3, MSR_RI | MSR_IR | MSR_DR | MSR_FP +#endif mtmsr r3 SYNC /* diff --git a/c/src/lib/libbsp/powerpc/shared/start/start.S b/c/src/lib/libbsp/powerpc/shared/start/start.S index ee09686659..9f91cb7365 100644 --- a/c/src/lib/libbsp/powerpc/shared/start/start.S +++ b/c/src/lib/libbsp/powerpc/shared/start/start.S @@ -106,8 +106,13 @@ enter_C_code: .type MMUon,@function MMUon: mfmsr r0 - ori r0,r0, MSR_IP | MSR_RI | MSR_IR | MSR_DR | MSR_EE | MSR_FE0 | MSR_FE1 +#if (PPC_HAS_FPU == 0) + ori r0,r0, MSR_IP | MSR_RI | MSR_IR | MSR_DR | MSR_EE | MSR_FE0 | MSR_FE1 | MSR_FP xori r0, r0, MSR_EE | MSR_IP | MSR_FP +#else + ori r0,r0, MSR_IP | MSR_RI | MSR_IR | MSR_DR | MSR_EE | MSR_FE0 | MSR_FE1 | MSR_FP + xori r0, r0, MSR_EE | MSR_IP | MSR_FE0 | MSR_FE1 +#endif mflr r11 mtsrr0 r11 mtsrr1 r0