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bsps: Rework cache manager implementation

Browse Source 
The previous cache manager support used a single souce file
(cache_manager.c) which included an implementation header (cache_.h).
This required the use of specialized include paths to find the right
header file.  Change this to include a generic implementation header
(cacheimpl.h) in specialized source files.

Use the following directories and files:

* bsps/shared/cache

* bsps/@RTEMS_CPU@/shared/cache

* bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILY/start/cache.c

Update #3285.
This commit is contained in:
Sebastian Huber
2018-01-27 14:37:51 +01:00
parent d8d6a08d46
commit 4cf93658ef
133 changed files with 382 additions and 1032 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am
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@@ -52,7 +52,6 @@ noinst_LIBRARIES = libbsp.a
libbsp_a_SOURCES =
libbsp_a_CPPFLAGS = $(AM_CPPFLAGS)
libbsp_a_LIBADD =
# for the Altera hwlib
libbsp_a_CPPFLAGS += -I${srcdir}/hwlib/include
@@ -133,10 +132,7 @@ libbsp_a_SOURCES += ../../shared/tod.c
libbsp_a_SOURCES += rtc/rtc.c
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
libbsp_a_SOURCES += ../shared/arm-l2c-310/cache_.h
libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/arm-l2c-310
libbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cache/cache-l2c-310.c
###############################################################################
# Special Rules #

4
c/src/lib/libbsp/arm/atsam/Makefile.am
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@@ -136,9 +136,7 @@ libbsp_a_SOURCES += clock/systick-freq.c
libbsp_a_SOURCES += ../../shared/timerstub.c
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
libbsp_a_SOURCES += ../shared/armv7m/include/cache_.h
libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv7m/include
libbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cache/cache-v7m.c
# Network
if HAS_NETWORKING

6
c/src/lib/libbsp/arm/beagle/Makefile.am
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@@ -36,7 +36,6 @@ dist_project_lib_DATA += startup/linkcmds.beagle
noinst_LIBRARIES = libbsp.a
libbsp_a_SOURCES =
libbsp_a_CPPFLAGS = $(AM_CPPFLAGS)
libbsp_a_LIBADD =
# Shared
@@ -97,10 +96,7 @@ libbsp_a_SOURCES += clock.c
libbsp_a_SOURCES += ../../shared/clockdrv_shell.h
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h
libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache
libbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cache/cache-cp15.c
###############################################################################
# Special Rules #

7
c/src/lib/libbsp/arm/csb336/Makefile.am
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@@ -6,8 +6,6 @@ include $(top_srcdir)/../../bsp.am
dist_project_lib_DATA = startup/bsp_specs
libbsp_a_CPPFLAGS = $(AM_CPPFLAGS)
DISTCLEANFILES = include/bspopts.h
noinst_PROGRAMS =
@@ -45,10 +43,7 @@ libbsp_a_SOURCES += ../../shared/src/irq-shell.c
libbsp_a_SOURCES += irq/irq.c
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h
libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache
libbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cache/cache-cp15.c
if HAS_NETWORKING
libbsp_a_SOURCES += network/lan91c11x.c

7
c/src/lib/libbsp/arm/csb337/Makefile.am
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@@ -9,8 +9,6 @@ dist_project_lib_DATA = startup/bsp_specs
if ENABLE_LCD
endif
libbsp_a_CPPFLAGS = $(AM_CPPFLAGS)
if ENABLE_UMON
endif
@@ -76,10 +74,7 @@ libbsp_a_SOURCES += ../../shared/umon/umoncons.c
endif
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h
libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache
libbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cache/cache-cp15.c
if HAS_NETWORKING
libbsp_a_SOURCES += network/network.c

4
c/src/lib/libbsp/arm/edb7312/Makefile.am
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@@ -50,9 +50,7 @@ libbsp_a_SOURCES += irq/irq.c
libbsp_a_SOURCES += irq/bsp_irq_asm.S
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
libbsp_a_SOURCES += ../../shared/include/cache_.h
libbsp_a_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/../../shared/include
libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
if HAS_NETWORKING
libbsp_a_SOURCES += network/network.c

4
c/src/lib/libbsp/arm/gdbarmsim/Makefile.am
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@@ -50,9 +50,7 @@ libbsp_a_SOURCES += ../../shared/src/irq-server.c
libbsp_a_SOURCES += ../../shared/src/irq-shell.c
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
libbsp_a_SOURCES += ../../shared/include/cache_.h
libbsp_a_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/../../shared/include
libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
#libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/arm920.rel \
# ../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/clock.rel \

4
c/src/lib/libbsp/arm/gumstix/Makefile.am
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@@ -46,9 +46,7 @@ libbsp_a_SOURCES += ../../shared/src/irq-shell.c
libbsp_a_SOURCES += irq/irq.c
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
libbsp_a_SOURCES += ../../shared/include/cache_.h
libbsp_a_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/../../shared/include
libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
if ON_SKYEYE
libbsp_a_SOURCES += fb/fb.c

7
c/src/lib/libbsp/arm/imx/Makefile.am
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@@ -29,8 +29,6 @@ dist_project_lib_DATA += startup/linkcmds.imx7
noinst_LIBRARIES = libbsp.a
libbsp_a_SOURCES =
libbsp_a_CPPFLAGS = $(AM_CPPFLAGS)
libbsp_a_LIBADD =
# Shared
libbsp_a_SOURCES += ../../shared/bootcard.c
@@ -76,10 +74,7 @@ libbsp_a_SOURCES += ../../shared/clockdrv_shell.h
libbsp_a_SOURCES += ../shared/arm-generic-timer-clock-config.c
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h
libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache
libbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cache/cache-cp15.c
# I2C
libbsp_a_SOURCES += i2c/imx-i2c.c

6
c/src/lib/libbsp/arm/lm3s69xx/Makefile.am
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@@ -31,8 +31,6 @@ dist_project_lib_DATA += startup/linkcmds.lm3s6965_qemu
noinst_LIBRARIES = libbsp.a
libbsp_a_SOURCES =
libbsp_a_CPPFLAGS = $(AM_CPPFLAGS)
libbsp_a_LIBADD =
# Shared
libbsp_a_SOURCES += ../../shared/bootcard.c
@@ -81,9 +79,7 @@ libbsp_a_SOURCES += ../shared/armv7m/clock/armv7m-clock-config.c
libbsp_a_SOURCES += ../../shared/timerstub.c
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
libbsp_a_SOURCES += ../../../libcpu/arm/shared/cache/cache_.h
libbsp_a_CPPFLAGS += -I$(srcdir)/../../../libcpu/arm/shared/include
libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
# SSI
libbsp_a_SOURCES += ssi/ssi.c

6
c/src/lib/libbsp/arm/lpc176x/Makefile.am
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@@ -40,8 +40,6 @@ dist_project_lib_DATA += startup/linkcmds.lpc1768_mbed_ahb_ram_eth
noinst_LIBRARIES = libbsp.a
libbsp_a_SOURCES =
libbsp_a_CPPFLAGS = $(AM_CPPFLAGS)
libbsp_a_LIBADD =
# Shared
libbsp_a_SOURCES += ../../shared/bootcard.c
@@ -114,9 +112,7 @@ libbsp_a_SOURCES += misc/restart.c
libbsp_a_SOURCES += watchdog/watchdog.c
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
libbsp_a_SOURCES += ../../../libcpu/arm/shared/include/cache_.h
libbsp_a_CPPFLAGS += -I$(srcdir)/../../../libcpu/arm/shared/include
libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
# Start hooks
libbsp_a_SOURCES += startup/bspstarthooks.c

6
c/src/lib/libbsp/arm/lpc24xx/Makefile.am
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@@ -49,8 +49,6 @@ dist_project_lib_DATA += startup/linkcmds.lpc40xx_ea_rom_int
noinst_LIBRARIES = libbsp.a
libbsp_a_SOURCES =
libbsp_a_CPPFLAGS = $(AM_CPPFLAGS)
libbsp_a_LIBADD =
# Shared
libbsp_a_SOURCES += ../../shared/bootcard.c \
@@ -121,9 +119,7 @@ libbsp_a_SOURCES += ../shared/arm-pl111-fb.c
libbsp_a_SOURCES += startup/fb-config.c
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
libbsp_a_SOURCES += ../../../libcpu/arm/shared/include/cache_.h
libbsp_a_CPPFLAGS += -I$(srcdir)/../../../libcpu/arm/shared/include
libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
# Start hooks
libbsp_a_SOURCES += startup/bspstarthooks.c

8
c/src/lib/libbsp/arm/lpc32xx/Makefile.am
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@@ -40,8 +40,6 @@ dist_project_lib_DATA += startup/linkcmds.lpc32xx_mzx
noinst_LIBRARIES = libbsp.a
libbsp_a_SOURCES =
libbsp_a_CPPFLAGS = $(AM_CPPFLAGS)
libbsp_a_LIBADD =
# Shared
libbsp_a_SOURCES += ../../shared/bootcard.c
@@ -103,11 +101,7 @@ libbsp_a_SOURCES += misc/idle-thread.c
# I2C
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h
libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache
libbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cache/cache-cp15.c
# Start hooks
libbsp_a_SOURCES += startup/bspstarthooks.c

5
c/src/lib/libbsp/arm/raspberrypi/Makefile.am
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@@ -114,10 +114,7 @@ libbsp_a_SOURCES += i2c/i2c.c
libbsp_a_SOURCES += spi/spi.c
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h
libbsp_a_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/../shared/armv467ar-basic-cache
libbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cache/cache-cp15.c
# Start hooks
libbsp_a_SOURCES += startup/bspstarthooks.c

7
c/src/lib/libbsp/arm/realview-pbx-a9/Makefile.am
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@@ -37,8 +37,6 @@ dist_project_lib_DATA += startup/linkcmds.realview_pbx_a9_qemu_smp
noinst_LIBRARIES = libbsp.a
libbsp_a_SOURCES =
libbsp_a_CPPFLAGS = $(AM_CPPFLAGS)
libbsp_a_LIBADD =
# Shared
libbsp_a_SOURCES += ../../shared/bootcard.c
@@ -85,10 +83,7 @@ libbsp_a_SOURCES += ../../shared/clockdrv_shell.h
libbsp_a_SOURCES += ../shared/arm-a9mpcore-clock-config.c
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h
libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache
libbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cache/cache-cp15.c
# Start hooks
libbsp_a_SOURCES += startup/bspstarthooks.c

4
c/src/lib/libbsp/arm/rtl22xx/Makefile.am
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@@ -49,9 +49,7 @@ libbsp_a_SOURCES += irq/irq.c
libbsp_a_SOURCES += console/uart.c
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
libbsp_a_SOURCES += ../../shared/include/cache_.h
libbsp_a_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/../../shared/include
libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
if HAS_NETWORKING
libbsp_a_SOURCES += network/network.c

1348
c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
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File diff suppressed because it is too large Load Diff

187
c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h
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@@ -1,187 +0,0 @@
/**
* @file
*
* @ingroup arm
*
* @brief ARM cache defines and implementation.
*/
/*
* Copyright (c) 2009-2011 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Obere Lagerstr. 30
* 82178 Puchheim
* Germany
* <rtems@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef LIBBSP_ARM_ARMV467AR_BASIC_CACHE_H
#define LIBBSP_ARM_ARMV467AR_BASIC_CACHE_H
#include <libcpu/arm-cp15.h>
#include "../include/arm-cache-l1.h"
#define CPU_DATA_CACHE_ALIGNMENT 32
#define CPU_INSTRUCTION_CACHE_ALIGNMENT 32
#if defined(__ARM_ARCH_7A__)
/* Some/many ARM Cortex-A cores have L1 data line length 64 bytes */
#define CPU_MAXIMAL_CACHE_ALIGNMENT 64
#endif
#define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS \
ARM_CACHE_L1_CPU_SUPPORT_PROVIDES_RANGE_FUNCTIONS
static inline void _CPU_cache_flush_1_data_line(const void *d_addr)
{
arm_cache_l1_flush_1_data_line(d_addr);
}
static inline void
_CPU_cache_flush_data_range(
const void *d_addr,
size_t n_bytes
)
{
_ARM_Data_synchronization_barrier();
arm_cache_l1_flush_data_range(
d_addr,
n_bytes
);
#if !defined(__ARM_ARCH_7A__)
arm_cp15_drain_write_buffer();
#endif
_ARM_Data_synchronization_barrier();
}
static inline void _CPU_cache_invalidate_1_data_line(const void *d_addr)
{
arm_cache_l1_invalidate_1_data_line(d_addr);
}
static inline void
_CPU_cache_invalidate_data_range(
const void *addr_first,
size_t n_bytes
)
{
arm_cache_l1_invalidate_data_range(
addr_first,
n_bytes
);
}
static inline void _CPU_cache_freeze_data(void)
{
/* TODO */
}
static inline void _CPU_cache_unfreeze_data(void)
{
/* TODO */
}
static inline void _CPU_cache_invalidate_1_instruction_line(const void *d_addr)
{
arm_cache_l1_invalidate_1_instruction_line(d_addr);
}
static inline void
_CPU_cache_invalidate_instruction_range( const void *i_addr, size_t n_bytes)
{
arm_cache_l1_invalidate_instruction_range( i_addr, n_bytes );
_ARM_Instruction_synchronization_barrier();
}
static inline void _CPU_cache_freeze_instruction(void)
{
/* TODO */
}
static inline void _CPU_cache_unfreeze_instruction(void)
{
/* TODO */
}
static inline void _CPU_cache_flush_entire_data(void)
{
_ARM_Data_synchronization_barrier();
#if defined(__ARM_ARCH_7A__)
arm_cp15_data_cache_clean_all_levels();
#else
arm_cp15_data_cache_clean_and_invalidate();
arm_cp15_drain_write_buffer();
#endif
_ARM_Data_synchronization_barrier();
}
static inline void _CPU_cache_invalidate_entire_data(void)
{
#if defined(__ARM_ARCH_7A__)
arm_cp15_data_cache_invalidate_all_levels();
#else
arm_cp15_data_cache_invalidate();
#endif
}
static inline void _CPU_cache_enable_data(void)
{
rtems_interrupt_level level;
uint32_t ctrl;
rtems_interrupt_local_disable(level);
ctrl = arm_cp15_get_control();
ctrl |= ARM_CP15_CTRL_C;
arm_cp15_set_control(ctrl);
rtems_interrupt_local_enable(level);
}
static inline void _CPU_cache_disable_data(void)
{
rtems_interrupt_level level;
uint32_t ctrl;
rtems_interrupt_local_disable(level);
arm_cp15_data_cache_test_and_clean_and_invalidate();
ctrl = arm_cp15_get_control();
ctrl &= ~ARM_CP15_CTRL_C;
arm_cp15_set_control(ctrl);
rtems_interrupt_local_enable(level);
}
static inline void _CPU_cache_invalidate_entire_instruction(void)
{
arm_cache_l1_invalidate_entire_instruction();
_ARM_Instruction_synchronization_barrier();
}
static inline void _CPU_cache_enable_instruction(void)
{
rtems_interrupt_level level;
uint32_t ctrl;
rtems_interrupt_local_disable(level);
ctrl = arm_cp15_get_control();
ctrl |= ARM_CP15_CTRL_I;
arm_cp15_set_control(ctrl);
rtems_interrupt_local_enable(level);
}
static inline void _CPU_cache_disable_instruction(void)
{
rtems_interrupt_level level;
uint32_t ctrl;
rtems_interrupt_local_disable(level);
ctrl = arm_cp15_get_control();
ctrl &= ~ARM_CP15_CTRL_I;
arm_cp15_set_control(ctrl);
rtems_interrupt_local_enable(level);
}
#endif /* LIBBSP_ARM_ARMV467AR_BASIC_CACHE_H */

144
c/src/lib/libbsp/arm/shared/armv7m/include/cache_.h
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@@ -1,144 +0,0 @@
/*
* Copyright (c) 2016 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Dornierstr. 4
* 82178 Puchheim
* Germany
* <rtems@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef LIBBSP_ARM_ARMV7M_CACHE__H
#define LIBBSP_ARM_ARMV7M_CACHE__H
#include <rtems.h>
#include <chip.h>
#define CPU_DATA_CACHE_ALIGNMENT 32
#define CPU_INSTRUCTION_CACHE_ALIGNMENT 32
#define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS
static inline void _CPU_cache_flush_data_range(
const void *d_addr,
size_t n_bytes
)
{
SCB_CleanInvalidateDCache_by_Addr(
RTEMS_DECONST(uint32_t *, (const uint32_t *) d_addr),
n_bytes
);
}
static inline void _CPU_cache_invalidate_data_range(
const void *d_addr,
size_t n_bytes
)
{
SCB_InvalidateDCache_by_Addr(
RTEMS_DECONST(uint32_t *, (const uint32_t *) d_addr),
n_bytes
);
}
static inline void _CPU_cache_freeze_data(void)
{
/* TODO */
}
static inline void _CPU_cache_unfreeze_data(void)
{
/* TODO */
}
static inline void _CPU_cache_invalidate_instruction_range(
const void *i_addr,
size_t n_bytes
)
{
rtems_interrupt_level level;
rtems_interrupt_disable(level);
SCB_InvalidateICache();
rtems_interrupt_enable(level);
}
static inline void _CPU_cache_freeze_instruction(void)
{
/* TODO */
}
static inline void _CPU_cache_unfreeze_instruction(void)
{
/* TODO */
}
static inline void _CPU_cache_flush_entire_data(void)
{
rtems_interrupt_level level;
rtems_interrupt_disable(level);
SCB_CleanDCache();
rtems_interrupt_enable(level);
}
static inline void _CPU_cache_invalidate_entire_data(void)
{
rtems_interrupt_level level;
rtems_interrupt_disable(level);
SCB_InvalidateDCache();
rtems_interrupt_enable(level);
}
static inline void _CPU_cache_enable_data(void)
{
rtems_interrupt_level level;
rtems_interrupt_disable(level);
SCB_EnableDCache();
rtems_interrupt_enable(level);
}
static inline void _CPU_cache_disable_data(void)
{
rtems_interrupt_level level;
rtems_interrupt_disable(level);
SCB_DisableDCache();
rtems_interrupt_enable(level);
}
static inline void _CPU_cache_invalidate_entire_instruction(void)
{
rtems_interrupt_level level;
rtems_interrupt_disable(level);
SCB_InvalidateICache();
rtems_interrupt_enable(level);
}
static inline void _CPU_cache_enable_instruction(void)
{
rtems_interrupt_level level;
rtems_interrupt_disable(level);
SCB_EnableICache();
rtems_interrupt_enable(level);
}
static inline void _CPU_cache_disable_instruction(void)
{
rtems_interrupt_level level;
rtems_interrupt_disable(level);
SCB_DisableICache();
rtems_interrupt_enable(level);
}
#endif /* LIBBSP_ARM_ARMV7M_CACHE__H */

409
c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h
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@@ -1,409 +0,0 @@
/**
* @file arm-cache-l1.h
*
* @ingroup arm_shared
*
* @brief Level 1 Cache definitions and functions.
*
* This file implements handling for the ARM Level 1 cache controller
*/
/*
* Copyright (c) 2014 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Dornierstr. 4
* 82178 Puchheim
* Germany
* <rtems@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef LIBBSP_ARM_SHARED_CACHE_L1_H
#define LIBBSP_ARM_SHARED_CACHE_L1_H
#include <bsp.h>
#include <libcpu/arm-cp15.h>
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* These two defines also ensure that the rtems_cache_* functions have bodies */
#define ARM_CACHE_L1_CPU_DATA_ALIGNMENT 32
#define ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT 32
#define ARM_CACHE_L1_CPU_SUPPORT_PROVIDES_RANGE_FUNCTIONS
#define ARM_CACHE_L1_CSS_ID_DATA \
(ARM_CP15_CACHE_CSS_ID_DATA | ARM_CP15_CACHE_CSS_LEVEL(0))
#define ARM_CACHE_L1_CSS_ID_INSTRUCTION \
(ARM_CP15_CACHE_CSS_ID_INSTRUCTION | ARM_CP15_CACHE_CSS_LEVEL(0))
#define ARM_CACHE_L1_DATA_LINE_MASK ( ARM_CACHE_L1_CPU_DATA_ALIGNMENT - 1 )
#define ARM_CACHE_L1_INSTRUCTION_LINE_MASK \
( ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT \
- 1 )
/* Errata Handlers */
static void arm_cache_l1_errata_764369_handler( void )
{
#ifdef RTEMS_SMP
_ARM_Data_synchronization_barrier();
#endif
}
/*
* @param l1LineSize Number of bytes in cache line expressed as power of
* 2 value
* @param l1Associativity Associativity of cache. The associativity does not
* have to be a power of 2.
* qparam liNumSets Number of sets in cache
* */
static inline void arm_cache_l1_properties_for_level(
uint32_t *l1LineSize,
uint32_t *l1Associativity,
uint32_t *l1NumSets,
uint32_t level_and_inst_dat
)
{
uint32_t ccsidr;
ccsidr = arm_cp15_get_cache_size_id_for_level(level_and_inst_dat);
/* Cache line size in words + 2 -> bytes) */
*l1LineSize = arm_ccsidr_get_line_power(ccsidr);
/* Number of Ways */
*l1Associativity = arm_ccsidr_get_associativity(ccsidr);
/* Number of Sets */
*l1NumSets = arm_ccsidr_get_num_sets(ccsidr);
}
/*
* @param log_2_line_bytes The number of bytes per cache line expressed in log2
* @param associativity The associativity of the cache beeing operated
* @param cache_level_idx The level of the cache beeing operated minus 1 e.g 0
* for cache level 1
* @param set Number of the set to operate on
* @param way Number of the way to operate on
* */
static inline uint32_t arm_cache_l1_get_set_way_param(
const uint32_t log_2_line_bytes,
const uint32_t associativity,
const uint32_t cache_level_idx,
const uint32_t set,
const uint32_t way )
{
uint32_t way_shift = __builtin_clz( associativity - 1 );
return ( 0
| ( way
<< way_shift ) | ( set << log_2_line_bytes ) | ( cache_level_idx << 1 ) );
}
static inline void arm_cache_l1_flush_1_data_line( const void *d_addr )
{
/* Flush the Data cache */
arm_cp15_data_cache_clean_and_invalidate_line( d_addr );
/* Wait for L1 flush to complete */
_ARM_Data_synchronization_barrier();
}
static inline void arm_cache_l1_flush_entire_data( void )
{
uint32_t l1LineSize, l1Associativity, l1NumSets;
uint32_t s, w;
uint32_t set_way_param;
/* ensure ordering with previous memory accesses */
_ARM_Data_memory_barrier();
/* Get the L1 cache properties */
arm_cache_l1_properties_for_level( &l1LineSize,
&l1Associativity, &l1NumSets,
ARM_CACHE_L1_CSS_ID_DATA);
for ( w = 0; w < l1Associativity; ++w ) {
for ( s = 0; s < l1NumSets; ++s ) {
set_way_param = arm_cache_l1_get_set_way_param(
l1LineSize,
l1Associativity,
0,
s,
w
);
arm_cp15_data_cache_clean_line_by_set_and_way( set_way_param );
}
}
/* Wait for L1 flush to complete */
_ARM_Data_synchronization_barrier();
}
static inline void arm_cache_l1_invalidate_entire_data( void )
{
uint32_t l1LineSize, l1Associativity, l1NumSets;
uint32_t s, w;
uint32_t set_way_param;
/* ensure ordering with previous memory accesses */
_ARM_Data_memory_barrier();
/* Get the L1 cache properties */
arm_cache_l1_properties_for_level( &l1LineSize,
&l1Associativity, &l1NumSets,
ARM_CACHE_L1_CSS_ID_DATA);
for ( w = 0; w < l1Associativity; ++w ) {
for ( s = 0; s < l1NumSets; ++s ) {
set_way_param = arm_cache_l1_get_set_way_param(
l1LineSize,
l1Associativity,
0,
s,
w
);
arm_cp15_data_cache_invalidate_line_by_set_and_way( set_way_param );
}
}
/* Wait for L1 invalidate to complete */
_ARM_Data_synchronization_barrier();
}
static inline void arm_cache_l1_clean_and_invalidate_entire_data( void )
{
uint32_t l1LineSize, l1Associativity, l1NumSets;
uint32_t s, w;
uint32_t set_way_param;
/* ensure ordering with previous memory accesses */
_ARM_Data_memory_barrier();
/* Get the L1 cache properties */
arm_cache_l1_properties_for_level( &l1LineSize,
&l1Associativity, &l1NumSets,
ARM_CACHE_L1_CSS_ID_DATA);
for ( w = 0; w < l1Associativity; ++w ) {
for ( s = 0; s < l1NumSets; ++s ) {
set_way_param = arm_cache_l1_get_set_way_param(
l1LineSize,
l1Associativity,
0,
s,
w
);
arm_cp15_data_cache_clean_and_invalidate_line_by_set_and_way(
set_way_param );
}
}
/* Wait for L1 invalidate to complete */
_ARM_Data_synchronization_barrier();
}
static inline void arm_cache_l1_flush_data_range(
const void *d_addr,
size_t n_bytes
)
{
if ( n_bytes != 0 ) {
uint32_t adx = (uint32_t) d_addr
& ~ARM_CACHE_L1_DATA_LINE_MASK;
const uint32_t ADDR_LAST =
(uint32_t)( (size_t) d_addr + n_bytes - 1 );
arm_cache_l1_errata_764369_handler();
for (; adx <= ADDR_LAST; adx += ARM_CACHE_L1_CPU_DATA_ALIGNMENT ) {
/* Store and invalidate the Data cache line */
arm_cp15_data_cache_clean_and_invalidate_line( (void*)adx );
}
/* Wait for L1 store to complete */
_ARM_Data_synchronization_barrier();
}
}
static inline void arm_cache_l1_invalidate_1_data_line(
const void *d_addr )
{
/* Invalidate the data cache line */
arm_cp15_data_cache_invalidate_line( d_addr );
/* Wait for L1 invalidate to complete */
_ARM_Data_synchronization_barrier();
}
static inline void arm_cache_l1_freeze_data( void )
{
/* To be implemented as needed, if supported by hardware at all */
}
static inline void arm_cache_l1_unfreeze_data( void )
{
/* To be implemented as needed, if supported by hardware at all */
}
static inline void arm_cache_l1_invalidate_1_instruction_line(
const void *i_addr )
{
/* Invalidate the Instruction cache line */
arm_cp15_instruction_cache_invalidate_line( i_addr );
/* Wait for L1 invalidate to complete */
_ARM_Data_synchronization_barrier();
}
static inline void arm_cache_l1_invalidate_data_range(
const void *d_addr,
size_t n_bytes
)
{
if ( n_bytes != 0 ) {
uint32_t adx = (uint32_t) d_addr
& ~ARM_CACHE_L1_DATA_LINE_MASK;
const uint32_t end =
(uint32_t)( (size_t)d_addr + n_bytes -1);
arm_cache_l1_errata_764369_handler();
/* Back starting address up to start of a line and invalidate until end */
for (;
adx <= end;
adx += ARM_CACHE_L1_CPU_DATA_ALIGNMENT ) {
/* Invalidate the Instruction cache line */
arm_cp15_data_cache_invalidate_line( (void*)adx );
}
/* Wait for L1 invalidate to complete */
_ARM_Data_synchronization_barrier();
}
}
static inline void arm_cache_l1_invalidate_instruction_range(
const void *i_addr,
size_t n_bytes
)
{
if ( n_bytes != 0 ) {
uint32_t adx = (uint32_t) i_addr
& ~ARM_CACHE_L1_INSTRUCTION_LINE_MASK;
const uint32_t end =
(uint32_t)( (size_t)i_addr + n_bytes -1);
arm_cache_l1_errata_764369_handler();
/* Back starting address up to start of a line and invalidate until end */
for (;
adx <= end;
adx += ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT ) {
/* Invalidate the Instruction cache line */
arm_cp15_instruction_cache_invalidate_line( (void*)adx );
}
/* Wait for L1 invalidate to complete */
_ARM_Data_synchronization_barrier();
}
}
static inline void arm_cache_l1_invalidate_entire_instruction( void )
{
uint32_t ctrl = arm_cp15_get_control();
#ifdef RTEMS_SMP
/* invalidate I-cache inner shareable */
arm_cp15_instruction_cache_inner_shareable_invalidate_all();
/* I+BTB cache invalidate */
arm_cp15_instruction_cache_invalidate();
#else /* RTEMS_SMP */
/* I+BTB cache invalidate */
arm_cp15_instruction_cache_invalidate();
#endif /* RTEMS_SMP */
if ( ( ctrl & ARM_CP15_CTRL_Z ) != 0 ) {
#if defined(__ARM_ARCH_7A__)
arm_cp15_branch_predictor_inner_shareable_invalidate_all();
#endif
#if defined(__ARM_ARCH_6KZ__) || defined(__ARM_ARCH_7A__)
arm_cp15_branch_predictor_invalidate_all();
#endif
}
}
static inline void arm_cache_l1_freeze_instruction( void )
{
/* To be implemented as needed, if supported by hardware at all */
}
static inline void arm_cache_l1_unfreeze_instruction( void )
{
/* To be implemented as needed, if supported by hardware at all */
}
static inline void arm_cache_l1_disable_data( void )
{
/* Clean and invalidate the Data cache */
arm_cache_l1_flush_entire_data();
/* Disable the Data cache */
arm_cp15_set_control( arm_cp15_get_control() & ~ARM_CP15_CTRL_C );
}
static inline void arm_cache_l1_disable_instruction( void )
{
/* Synchronize the processor */
_ARM_Data_synchronization_barrier();
/* Invalidate the Instruction cache */
arm_cache_l1_invalidate_entire_instruction();
/* Disable the Instruction cache */
arm_cp15_set_control( arm_cp15_get_control() & ~ARM_CP15_CTRL_I );
}
static inline size_t arm_cache_l1_get_data_cache_size( void )
{
size_t size;
uint32_t line_size = 0;
uint32_t associativity = 0;
uint32_t num_sets = 0;
arm_cache_l1_properties_for_level( &line_size,
&associativity, &num_sets,
ARM_CACHE_L1_CSS_ID_DATA);
size = (1 << line_size) * associativity * num_sets;
return size;
}
static inline size_t arm_cache_l1_get_instruction_cache_size( void )
{
size_t size;
uint32_t line_size = 0;
uint32_t associativity = 0;
uint32_t num_sets = 0;
arm_cache_l1_properties_for_level( &line_size,
&associativity, &num_sets,
ARM_CACHE_L1_CSS_ID_INSTRUCTION);
size = (1 << line_size) * associativity * num_sets;
return size;
}
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* LIBBSP_ARM_SHARED_CACHE_L1_H */

7
c/src/lib/libbsp/arm/smdk2410/Makefile.am
View File

@@ -6,8 +6,6 @@ include $(top_srcdir)/../../bsp.am
dist_project_lib_DATA = startup/bsp_specs
libbsp_a_CPPFLAGS = $(AM_CPPFLAGS)
DISTCLEANFILES = include/bspopts.h
EXTRA_DIST += start/start.S
@@ -58,10 +56,7 @@ libbsp_a_SOURCES += smc/smc.c
libbsp_a_SOURCES += smc/smc.h
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h
libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache
libbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cache/cache-cp15.c
libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/arm920.rel

6
c/src/lib/libbsp/arm/stm32f4/Makefile.am
View File

@@ -30,8 +30,6 @@ dist_project_lib_DATA += startup/linkcmds.stm32f4
noinst_LIBRARIES = libbsp.a
libbsp_a_SOURCES =
libbsp_a_CPPFLAGS = $(AM_CPPFLAGS)
libbsp_a_LIBADD =
# Shared
libbsp_a_SOURCES += ../../shared/bootcard.c
@@ -85,9 +83,7 @@ libbsp_a_SOURCES += ../shared/armv7m/clock/armv7m-clock-config.c
libbsp_a_SOURCES += ../../shared/timerstub.c
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
libbsp_a_SOURCES += ../../../libcpu/arm/shared/cache/cache_.h
libbsp_a_CPPFLAGS += -I$(srcdir)/../../../libcpu/arm/shared/include
libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
###############################################################################
# Special Rules #

6
c/src/lib/libbsp/arm/tms570/Makefile.am
View File

@@ -39,8 +39,6 @@ dist_project_lib_DATA += startup/linkcmds.tms570ls3137_hdk_with_loader
noinst_LIBRARIES = libbsp.a
libbsp_a_SOURCES =
libbsp_a_CPPFLAGS = $(AM_CPPFLAGS)
libbsp_a_LIBADD =
# Shared
libbsp_a_SOURCES += ../../shared/bootcard.c
@@ -96,9 +94,7 @@ libbsp_a_SOURCES += misc/cpucounterread.c
# Watchdog
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
libbsp_a_SOURCES += ../../../libcpu/arm/shared/include/cache_.h
libbsp_a_CPPFLAGS += -I$(srcdir)/../../../libcpu/arm/shared/include
libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
if TMS570_USE_HWINIT_STARTUP
libbsp_a_SOURCES += hwinit/tms570_sys_core.S

7
c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am
View File

@@ -35,8 +35,6 @@ project_lib_DATA += linkcmds
noinst_LIBRARIES = libbsp.a
libbsp_a_SOURCES =
libbsp_a_CPPFLAGS = $(AM_CPPFLAGS)
libbsp_a_LIBADD =
# Shared
libbsp_a_SOURCES += ../../shared/bootcard.c
@@ -84,10 +82,7 @@ libbsp_a_SOURCES += ../shared/arm-a9mpcore-clock-config.c
libbsp_a_SOURCES += i2c/cadence-i2c.c
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
libbsp_a_SOURCES += ../shared/arm-l2c-310/cache_.h
libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/arm-l2c-310
libbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cache/cache-l2c-310.c
# Start hooks
libbsp_a_SOURCES += startup/bspstarthooks.c startup/bspstartmmu.c

2
c/src/lib/libbsp/bfin/TLL6527M/Makefile.am
View File

@@ -29,10 +29,10 @@ libbsp_a_SOURCES = \
libbsp_a_SOURCES += ../../shared/bspreset.c
libbsp_a_SOURCES += console/console.c
libbsp_a_SOURCES += ../../../../../../bsps/bfin/shared/cache/cache.c
libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/mmu.rel
libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/interrupt.rel
libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/cache.rel
libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/uart.rel
libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/clock.rel
libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/rtc.rel

2
c/src/lib/libbsp/bfin/bf537Stamp/Makefile.am
View File

@@ -30,6 +30,7 @@ libbsp_a_SOURCES += \
libbsp_a_SOURCES += ../../shared/bspreset.c
libbsp_a_SOURCES += console/console.c
libbsp_a_SOURCES += ../../../../../../bsps/bfin/shared/cache/cache.c
if HAS_NETWORKING
libbsp_a_SOURCES += network/networkconfig.c
@@ -37,7 +38,6 @@ endif
libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/mmu.rel
libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/interrupt.rel
libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/cache.rel
libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/uart.rel
libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/clock.rel
libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/rtc.rel

2
c/src/lib/libbsp/bfin/eZKit533/Makefile.am
View File

@@ -30,10 +30,10 @@ libbsp_a_SOURCES += \
libbsp_a_SOURCES += ../../shared/bspreset.c
libbsp_a_SOURCES += console/console-io.c
libbsp_a_SOURCES += ../../../../../../bsps/bfin/shared/cache/cache.c
libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/mmu.rel
libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/interrupt.rel
libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/cache.rel
libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/uart.rel
libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/clock.rel
libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/rtc.rel

4
c/src/lib/libbsp/epiphany/epiphany_sim/Makefile.am
View File

@@ -62,9 +62,7 @@ libbsp_a_SOURCES += ../../shared/src/irq-info.c
libbsp_a_SOURCES += irq/irq.c
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
libbsp_a_SOURCES += ../../shared/include/cache_.h
libbsp_a_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/../../shared/include
libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
# debugio
libbsp_a_SOURCES += console/console-io.c

5
c/src/lib/libbsp/i386/pc386/Makefile.am
View File

@@ -170,8 +170,9 @@ libbsp_a_SOURCES += ne2000/ne2000.c
libbsp_a_SOURCES += wd8003/wd8003.c
endif
libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/cache.rel
libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/page.rel
libbsp_a_SOURCES += ../../../../../../bsps/i386/shared/cache/cache.c
libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/page.rel
libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/score.rel
if HAS_SMP

4
c/src/lib/libbsp/lm32/lm32_evr/Makefile.am
View File

@@ -41,9 +41,7 @@ libbsp_a_SOURCES += ../../lm32/shared/console/uart.c
libbsp_a_SOURCES += ../../lm32/shared/timer/timer.c
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
libbsp_a_SOURCES += ../../shared/include/cache_.h
libbsp_a_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/../../shared/include
libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
if HAS_NETWORKING
libbsp_a_SOURCES += ../../lm32/shared/tsmac/tsmac.c

4
c/src/lib/libbsp/lm32/milkymist/Makefile.am
View File

@@ -88,9 +88,7 @@ libbsp_a_SOURCES += ../../lm32/shared/milkymist_video/video.c
libbsp_a_SOURCES += ../../lm32/shared/milkymist_versions/versions.c
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
libbsp_a_SOURCES += ../../shared/include/cache_.h
libbsp_a_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/../../shared/include
libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
if HAS_NETWORKING
libbsp_a_SOURCES += ../../lm32/shared/milkymist_networking/network.c

4
c/src/lib/libbsp/m32c/m32cbsp/Makefile.am
View File

@@ -34,9 +34,7 @@ libbsp_a_SOURCES = $(startup_SOURCES) $(clock_SOURCES) $(console_SOURCES) \
$(timer_SOURCES)
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
libbsp_a_SOURCES += ../../shared/include/cache_.h
libbsp_a_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/../../shared/include
libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
include $(top_srcdir)/../../../../automake/local.am
include $(srcdir)/../../../../../../bsps/m32c/m32cbsp/headers.am

4
c/src/lib/libbsp/m68k/av5282/Makefile.am
View File

@@ -40,9 +40,9 @@ if HAS_NETWORKING
libbsp_a_SOURCES += network/network.c
endif
libbsp_a_SOURCES += ../../../../../../bsps/m68k/shared/cache/cache-mcf5282.c
libbsp_a_LIBADD = \
../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
../../../libcpu/@RTEMS_CPU@/mcf5282/cachepd.rel \
../../../libcpu/@RTEMS_CPU@/shared/misc.rel
include $(top_srcdir)/../../../../automake/local.am

4
c/src/lib/libbsp/m68k/csb360/Makefile.am
View File

@@ -34,9 +34,7 @@ libbsp_a_SOURCES += ../../shared/bspreset.c
libbsp_a_SOURCES += console/console-io.c ../../shared/console-polled.c
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
libbsp_a_SOURCES += ../../shared/include/cache_.h
libbsp_a_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/../../shared/include
libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
libbsp_a_LIBADD = \
../../../libcpu/@RTEMS_CPU@/shared/misc.rel \

3
c/src/lib/libbsp/m68k/gen68340/Makefile.am
View File

@@ -37,8 +37,9 @@ libbsp_a_SOURCES += console/console.c console/m340uart.c \
# timer
libbsp_a_SOURCES += timer/timer.c
libbsp_a_SOURCES += ../../../../../../bsps/m68k/shared/cache/cache.c
libbsp_a_LIBADD = \
../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
../../../libcpu/@RTEMS_CPU@/shared/misc.rel
include $(top_srcdir)/../../../../automake/local.am

3
c/src/lib/libbsp/m68k/gen68360/Makefile.am
View File

@@ -42,8 +42,9 @@ if HAS_NETWORKING
libbsp_a_SOURCES += network/network.c
endif
libbsp_a_SOURCES += ../../../../../../bsps/m68k/shared/cache/cache.c
libbsp_a_LIBADD = \
../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
../../../libcpu/@RTEMS_CPU@/shared/misc.rel
if HAS_FPSP
libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/fpsp.rel

4
c/src/lib/libbsp/m68k/genmcf548x/Makefile.am
View File

@@ -49,9 +49,7 @@ libbsp_a_SOURCES += irq/irq.c
libbsp_a_SOURCES += irq/intc-icr-init-values.c
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
libbsp_a_SOURCES += ../include/cache_.h
libbsp_a_CPPFLAGS += -I$(srcdir)/include
libbsp_a_SOURCES += ../../../../../../bsps/m68k/genmcf548x/start/cache.c
if HAS_NETWORKING
libbsp_a_SOURCES += network/network.c

117
c/src/lib/libbsp/m68k/genmcf548x/include/cache_.h
View File

@@ -1,117 +0,0 @@
/*
* Copyright (c) 2007-2014 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Dornierstr. 4
* 82178 Puchheim
* Germany
* <rtems@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef LIBBSP_M68K_GENMCF548X_CACHE_H
#define LIBBSP_M68K_GENMCF548X_CACHE_H
#include <bsp.h>
#define CPU_DATA_CACHE_ALIGNMENT 16
#define CPU_INSTRUCTION_CACHE_ALIGNMENT 16
/*
* There is no complete cache lock (only 2 ways of 4 can be locked)
*/
static inline void _CPU_cache_freeze_data(void)
{
/* Do nothing */
}
static inline void _CPU_cache_unfreeze_data(void)
{
/* Do nothing */
}
static inline void _CPU_cache_freeze_instruction(void)
{
/* Do nothing */
}
static inline void _CPU_cache_unfreeze_instruction(void)
{
/* Do nothing */
}
static inline void _CPU_cache_enable_instruction(void)
{
bsp_cacr_clear_flags( MCF548X_CACR_IDCM);
}
static inline void _CPU_cache_disable_instruction(void)
{
bsp_cacr_set_flags( MCF548X_CACR_IDCM);
}
static inline void _CPU_cache_invalidate_entire_instruction(void)
{
bsp_cacr_set_self_clear_flags( MCF548X_CACR_ICINVA);
}
static inline void _CPU_cache_invalidate_1_instruction_line(const void *addr)
{
uint32_t a = (uint32_t) addr & ~0x3;
__asm__ volatile ("cpushl %%ic,(%0)" :: "a" (a | 0x0));
__asm__ volatile ("cpushl %%ic,(%0)" :: "a" (a | 0x1));
__asm__ volatile ("cpushl %%ic,(%0)" :: "a" (a | 0x2));
__asm__ volatile ("cpushl %%ic,(%0)" :: "a" (a | 0x3));
}
static inline void _CPU_cache_enable_data(void)
{
bsp_cacr_clear_flags( MCF548X_CACR_DDCM( DCACHE_OFF_IMPRECISE));
}
static inline void _CPU_cache_disable_data(void)
{
bsp_cacr_set_flags( MCF548X_CACR_DDCM( DCACHE_OFF_IMPRECISE));
}
static inline void _CPU_cache_invalidate_entire_data(void)
{
bsp_cacr_set_self_clear_flags( MCF548X_CACR_DCINVA);
}
static inline void _CPU_cache_invalidate_1_data_line( const void *addr)
{
uint32_t a = (uint32_t) addr & ~0x3;
__asm__ volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x0));
__asm__ volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x1));
__asm__ volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x2));
__asm__ volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x3));
}
static inline void _CPU_cache_flush_1_data_line( const void *addr)
{
uint32_t a = (uint32_t) addr & ~0x3;
__asm__ volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x0));
__asm__ volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x1));
__asm__ volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x2));
__asm__ volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x3));
}
static inline void _CPU_cache_flush_entire_data( void)
{
uint32_t line = 0;
for (line = 0; line < 512; ++line) {
_CPU_cache_flush_1_data_line( (const void *) (line * 16));
}
}
#endif /* LIBBSP_M68K_GENMCF548X_CACHE_H */

4
c/src/lib/libbsp/m68k/mcf5206elite/Makefile.am
View File

@@ -44,9 +44,7 @@ libbsp_a_SOURCES += tod/ds1307.c tod/todcfg.c ../../shared/tod.c
libbsp_a_SOURCES += nvram/nvram.c
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
libbsp_a_SOURCES += ../../shared/include/cache_.h
libbsp_a_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/../../shared/include
libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
libbsp_a_LIBADD = \
../../../libcpu/@RTEMS_CPU@/shared/misc.rel \

4
c/src/lib/libbsp/m68k/mcf52235/Makefile.am
View File

@@ -38,9 +38,9 @@ libbsp_a_SOURCES += console/debugio.c
# timer
libbsp_a_SOURCES += timer/timer.c
libbsp_a_SOURCES += ../../../../../../bsps/m68k/shared/cache/cache-mcf5223x.c
libbsp_a_LIBADD = \
../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
../../../libcpu/@RTEMS_CPU@/mcf5223x/cachepd.rel \
../../../libcpu/@RTEMS_CPU@/shared/misc.rel
include $(top_srcdir)/../../../../automake/local.am

4
c/src/lib/libbsp/m68k/mcf5225x/Makefile.am
View File

@@ -33,9 +33,9 @@ libbsp_a_SOURCES += console/console.c
libbsp_a_SOURCES += console/debugio.c
libbsp_a_SOURCES += timer/timer.c
libbsp_a_SOURCES += ../../../../../../bsps/m68k/shared/cache/cache-mcf5225x.c
libbsp_a_LIBADD = \
../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
../../../libcpu/@RTEMS_CPU@/mcf5225x/cachepd.rel \
../../../libcpu/@RTEMS_CPU@/shared/misc.rel
include $(top_srcdir)/../../../../automake/local.am

4
c/src/lib/libbsp/m68k/mcf5235/Makefile.am
View File

@@ -42,9 +42,9 @@ if HAS_NETWORKING
libbsp_a_SOURCES += network/network.c
endif
libbsp_a_SOURCES += ../../../../../../bsps/m68k/shared/cache/cache-mcf5235.c
libbsp_a_LIBADD = \
../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
../../../libcpu/@RTEMS_CPU@/mcf5235/cachepd.rel \
../../../libcpu/@RTEMS_CPU@/shared/misc.rel
include $(top_srcdir)/../../../../automake/local.am

6
c/src/lib/libbsp/m68k/mcf5329/Makefile.am
View File

@@ -41,10 +41,10 @@ if HAS_NETWORKING
libbsp_a_SOURCES += network/network.c
endif
libbsp_a_SOURCES += ../../../../../../bsps/m68k/shared/cache/cache-mcf532x.c
libbsp_a_LIBADD = \
../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
../../../libcpu/@RTEMS_CPU@/shared/misc.rel \
../../../libcpu/@RTEMS_CPU@/mcf532x/cachepd.rel
../../../libcpu/@RTEMS_CPU@/shared/misc.rel
include $(top_srcdir)/../../../../automake/local.am
include $(srcdir)/../../../../../../bsps/m68k/mcf5329/headers.am

3
c/src/lib/libbsp/m68k/mrm332/Makefile.am
View File

@@ -38,8 +38,9 @@ libbsp_a_SOURCES += spurious/spinit.c
# timer
libbsp_a_SOURCES += timer/timer.c
libbsp_a_SOURCES += ../../../../../../bsps/m68k/shared/cache/cache.c
libbsp_a_LIBADD = \
../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
../../../libcpu/@RTEMS_CPU@/shared/misc.rel
include $(top_srcdir)/../../../../automake/local.am

3
c/src/lib/libbsp/m68k/mvme147/Makefile.am
View File

@@ -37,8 +37,9 @@ libbsp_a_SOURCES += console/console.c ../../shared/dummy_printk_support.c
# timer
libbsp_a_SOURCES += timer/timer.c timer/timerisr.S
libbsp_a_SOURCES += ../../../../../../bsps/m68k/shared/cache/cache.c
libbsp_a_LIBADD = \
../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
../../../libcpu/@RTEMS_CPU@/shared/misc.rel
EXTRA_DIST += times

3
c/src/lib/libbsp/m68k/mvme147s/Makefile.am
View File

@@ -45,8 +45,9 @@ libbsp_a_SOURCES += shmsupp/addrconv.c shmsupp/getcfg.c shmsupp/lock.c \
shmsupp/mpisr.c
endif
libbsp_a_SOURCES += ../../../../../../bsps/m68k/shared/cache/cache.c
libbsp_a_LIBADD = \
../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
../../../libcpu/@RTEMS_CPU@/shared/misc.rel
EXTRA_DIST += times

3
c/src/lib/libbsp/m68k/mvme162/Makefile.am
View File

@@ -44,8 +44,9 @@ if HAS_NETWORKING
libbsp_a_SOURCES += ../mvme167/network/network.c
endif
libbsp_a_SOURCES += ../../../../../../bsps/m68k/shared/cache/cache.c
libbsp_a_LIBADD = \
../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
../../../libcpu/@RTEMS_CPU@/shared/misc.rel
if HAS_FPSP
libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/fpsp.rel

3
c/src/lib/libbsp/m68k/mvme167/Makefile.am
View File

@@ -41,8 +41,9 @@ if HAS_NETWORKING
libbsp_a_SOURCES += network/network.c
endif
libbsp_a_SOURCES += ../../../../../../bsps/m68k/shared/cache/cache.c
libbsp_a_LIBADD = \
../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
../../../libcpu/@RTEMS_CPU@/shared/misc.rel \
../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/fpsp.rel

6
c/src/lib/libbsp/m68k/uC5282/Makefile.am
View File

@@ -39,9 +39,9 @@ if HAS_NETWORKING
libbsp_a_SOURCES += network/network.c
endif
libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
../../../libcpu/@RTEMS_CPU@/mcf5282/cachepd.rel \
../../../libcpu/@RTEMS_CPU@/shared/misc.rel
libbsp_a_SOURCES += ../../../../../../bsps/m68k/shared/cache/cache-mcf5282.c
libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/misc.rel
include $(top_srcdir)/../../../../automake/local.am
include $(srcdir)/../../../../../../bsps/m68k/uC5282/headers.am

5
c/src/lib/libbsp/mips/csb350/Makefile.am
View File

@@ -53,8 +53,9 @@ if HAS_NETWORKING
libbsp_a_SOURCES += network/network.c
endif
libbsp_a_LIBADD = ../../../libcpu/mips/shared/cache.rel
libbsp_a_LIBADD += ../../../libcpu/mips/shared/interrupts.rel
libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
libbsp_a_LIBADD = ../../../libcpu/mips/shared/interrupts.rel
include $(top_srcdir)/../../../../automake/local.am
include $(srcdir)/../../../../../../bsps/mips/csb350/headers.am

5
c/src/lib/libbsp/mips/hurricane/Makefile.am
View File

@@ -55,8 +55,9 @@ libbsp_a_SOURCES += ../shared/irq/irq.c
libbsp_a_SOURCES += irq/vectorisrs.c
libbsp_a_SOURCES += ../shared/irq/interruptmask.c
libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/cache.rel
libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/shared/interrupts.rel
libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/interrupts.rel
libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/rm52xx/timer.rel
include $(top_srcdir)/../../../../automake/local.am

5
c/src/lib/libbsp/mips/jmr3904/Makefile.am
View File

@@ -47,8 +47,9 @@ libbsp_a_SOURCES += ../shared/irq/irq.c
libbsp_a_SOURCES += irq/vectorisrs.c
libbsp_a_SOURCES += ../shared/irq/interruptmask.c
libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/cache.rel
libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/shared/interrupts.rel
libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/interrupts.rel
include $(top_srcdir)/../../../../automake/local.am
include $(srcdir)/../../../../../../bsps/mips/jmr3904/headers.am

5
c/src/lib/libbsp/mips/malta/Makefile.am
View File

@@ -54,8 +54,9 @@ libbsp_a_SOURCES += ../../shared/console_control.c
# timer
libbsp_a_SOURCES += ../../shared/timerstub.c
libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/cache.rel
libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/shared/interrupts.rel
libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/interrupts.rel
# pci
libbsp_a_SOURCES += pci/pci.c

5
c/src/lib/libbsp/mips/rbtx4925/Makefile.am
View File

@@ -55,8 +55,9 @@ libbsp_a_SOURCES += ../shared/irq/irq.c
libbsp_a_SOURCES += irq/vectorisrs.c
libbsp_a_SOURCES += ../shared/irq/interruptmask_TX49.c
libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/cache.rel
libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/shared/interrupts.rel
libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/interrupts.rel
libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/tx49/timer.rel
include $(top_srcdir)/../../../../automake/local.am

5
c/src/lib/libbsp/mips/rbtx4938/Makefile.am
View File

@@ -55,8 +55,9 @@ libbsp_a_SOURCES += ../shared/irq/irq.c
libbsp_a_SOURCES += irq/vectorisrs.c
libbsp_a_SOURCES += ../shared/irq/interruptmask_TX49.c
libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/cache.rel
libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/shared/interrupts.rel
libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/interrupts.rel
libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/tx49/timer.rel
include $(top_srcdir)/../../../../automake/local.am

4
c/src/lib/libbsp/moxie/moxiesim/Makefile.am
View File

@@ -40,9 +40,7 @@ libbsp_a_SOURCES += ../../shared/console-polled.c console/console-io.c \
libbsp_a_SOURCES += ../../shared/timerstub.c
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
libbsp_a_SOURCES += ../../shared/include/cache_.h
libbsp_a_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/../../shared/include
libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
EXTRA_DIST += times

2
c/src/lib/libbsp/nios2/nios2_iss/Makefile.am
View File

@@ -44,7 +44,7 @@ libbsp_a_SOURCES += console/console.c ../../shared/console-polled.c
libbsp_a_SOURCES += timer/timer.c
# Cache
libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/cache.rel
libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
include $(top_srcdir)/../../../../automake/local.am
include $(srcdir)/../../../../../../bsps/nios2/nios2_iss/headers.am

2
c/src/lib/libbsp/or1k/generic_or1k/Makefile.am
View File

@@ -74,7 +74,7 @@ libbsp_a_SOURCES += ../../shared/src/irq-info.c
libbsp_a_SOURCES += irq/irq.c
# Cache
libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/shared/cache.rel
libbsp_a_SOURCES += ../../../../../../bsps/or1k/shared/cache/cache.c
###############################################################################
# Special Rules #

3
c/src/lib/libbsp/powerpc/beatnik/Makefile.am
View File

@@ -163,8 +163,9 @@ endif
# tod
libbsp_a_SOURCES += ../../shared/tod.c tod/todcfg.c
libbsp_a_SOURCES += ../../../../../../bsps/powerpc/shared/cache/cache.c
libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
../../../libcpu/@RTEMS_CPU@/shared/stack.rel \
../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \

3
c/src/lib/libbsp/powerpc/gen5200/Makefile.am
View File

@@ -110,8 +110,9 @@ if HAS_NETWORKING
libbsp_a_SOURCES += network_5200/network.c
endif
libbsp_a_SOURCES += ../../../../../../bsps/powerpc/shared/cache/cache.c
libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
../../../libcpu/@RTEMS_CPU@/shared/stack.rel \
../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \

11
c/src/lib/libbsp/powerpc/gen83xx/Makefile.am
View File

@@ -73,13 +73,9 @@ libbsp_a_SOURCES += i2c/i2c_init.c
# bsp_spi
libbsp_a_SOURCES += spi/spi_init.c
if HAS_NETWORKING
libbsp_a_SOURCES += network/network.c
libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/mpc83xx/tsec.rel
endif
libbsp_a_SOURCES += ../../../../../../bsps/powerpc/shared/cache/cache.c
libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \
../../../libcpu/@RTEMS_CPU@/mpc6xx/mmu.rel \
@@ -88,6 +84,11 @@ libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
../../../libcpu/@RTEMS_CPU@/mpc83xx/spi.rel \
../../../libcpu/@RTEMS_CPU@/mpc83xx/gtm.rel
if HAS_NETWORKING
libbsp_a_SOURCES += network/network.c
libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/mpc83xx/tsec.rel
endif
EXTRA_DIST += README.mpc8349eamds
include $(top_srcdir)/../../../../automake/local.am

3
c/src/lib/libbsp/powerpc/haleakala/Makefile.am
View File

@@ -42,10 +42,11 @@ if HAS_NETWORKING
libbsp_a_SOURCES += network/network.c
endif
libbsp_a_SOURCES += ../../../../../../bsps/powerpc/shared/cache/cache.c
libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \
../../../libcpu/@RTEMS_CPU@/@exceptions@/irq_bspsupport.rel \
../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
../../../libcpu/@RTEMS_CPU@/ppc403/clock.rel \
../../../libcpu/@RTEMS_CPU@/ppc403/timer.rel

3
c/src/lib/libbsp/powerpc/motorola_powerpc/Makefile.am
View File

@@ -114,9 +114,10 @@ libbsp_a_SOURCES += ../../i386/pc386/ne2000/ne2000.c
endif
endif
libbsp_a_SOURCES += ../../../../../../bsps/powerpc/shared/cache/cache.c
libbsp_a_LIBADD = \
polledIO.rel \
../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
../../../libcpu/@RTEMS_CPU@/shared/stack.rel \
../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \

3
c/src/lib/libbsp/powerpc/mpc55xxevb/Makefile.am
View File

@@ -106,8 +106,9 @@ endif
# BSP library
libbsp_a_SOURCES += ../../../../../../bsps/powerpc/shared/cache/cache.c
libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
../../../libcpu/@RTEMS_CPU@/shared/stack.rel \
../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/misc.rel \
../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/irq.rel \

3
c/src/lib/libbsp/powerpc/mpc8260ads/Makefile.am
View File

@@ -54,8 +54,9 @@ libbsp_a_SOURCES += network/if_hdlcsubr.c
libbsp_a_SOURCES += network/network.c
endif
libbsp_a_SOURCES += ../../../../../../bsps/powerpc/shared/cache/cache.c
libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \
../../../libcpu/@RTEMS_CPU@/mpc8260/console-generic.rel \

3
c/src/lib/libbsp/powerpc/mvme3100/Makefile.am
View File

@@ -105,8 +105,9 @@ network_rel_CPPFLAGS = $(AM_CPPFLAGS)
network_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
endif
libbsp_a_SOURCES += ../../../../../../bsps/powerpc/shared/cache/cache.c
libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
../../../libcpu/@RTEMS_CPU@/shared/stack.rel \
../../../libcpu/@RTEMS_CPU@/e500/clock.rel \
../../../libcpu/@RTEMS_CPU@/e500/timer.rel \

3
c/src/lib/libbsp/powerpc/mvme5500/Makefile.am
View File

@@ -83,10 +83,11 @@ project_lib_DATA += mvme5500start.$(OBJEXT)
project_lib_DATA += linkcmds
dist_project_lib_DATA += ../shared/startup/linkcmds.share
libbsp_a_SOURCES += ../../../../../../bsps/powerpc/shared/cache/cache.c
libbsp_a_LIBADD = \
../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
../../../libcpu/@RTEMS_CPU@/shared/stack.rel \
../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
../../../libcpu/@RTEMS_CPU@/mpc6xx/clock.rel \
../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \

3
c/src/lib/libbsp/powerpc/psim/Makefile.am
View File

@@ -60,8 +60,9 @@ if HAS_NETWORKING
libbsp_a_SOURCES += network/if_sim.c
endif
libbsp_a_SOURCES += ../../../../../../bsps/powerpc/shared/cache/cache.c
libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
../../../libcpu/@RTEMS_CPU@/shared/stack.rel \
../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
../../../libcpu/@RTEMS_CPU@/mpc6xx/clock.rel \

3
c/src/lib/libbsp/powerpc/qemuppc/Makefile.am
View File

@@ -51,8 +51,9 @@ noinst_LIBRARIES = libbsp.a
libbsp_a_SOURCES = $(startup_SOURCES) $(clock_SOURCES) $(console_SOURCES) \
$(irq_SOURCES)
libbsp_a_SOURCES += ../../../../../../bsps/powerpc/shared/cache/cache.c
libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
../../../libcpu/@RTEMS_CPU@/shared/stack.rel \
../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \

3
c/src/lib/libbsp/powerpc/qoriq/Makefile.am
View File

@@ -96,8 +96,9 @@ libbsp_a_SOURCES += shmsupp/lock.S \
shmsupp/intercom.c \
shmsupp/intercom-mpci.c
libbsp_a_SOURCES += ../../../../../../bsps/powerpc/shared/cache/cache.c
libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \
../../../libcpu/@RTEMS_CPU@/e500/mmu.rel

3
c/src/lib/libbsp/powerpc/ss555/Makefile.am
View File

@@ -35,9 +35,10 @@ libbsp_a_SOURCES += ../../shared/bspreset.c
# tm27supp
libbsp_a_SOURCES += startup/tm27supp.c
libbsp_a_SOURCES += ../../../../../../bsps/powerpc/shared/cache/cache.c
libbsp_a_LIBADD = \
../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
../../../libcpu/@RTEMS_CPU@/mpc5xx/clock.rel \
../../../libcpu/@RTEMS_CPU@/mpc5xx/console-generic.rel \

3
c/src/lib/libbsp/powerpc/t32mppc/Makefile.am
View File

@@ -64,8 +64,9 @@ libbsp_a_SOURCES += irq/irq.c
libbsp_a_SOURCES += ../../shared/console-termios.c
libbsp_a_SOURCES += console/console.c
libbsp_a_SOURCES += ../../../../../../bsps/powerpc/shared/cache/cache.c
libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel

3
c/src/lib/libbsp/powerpc/tqm8xx/Makefile.am
View File

@@ -62,9 +62,10 @@ libbsp_a_SOURCES += network/network_fec.c
libbsp_a_SOURCES += network/network_scc.c
endif
libbsp_a_SOURCES += ../../../../../../bsps/powerpc/shared/cache/cache.c
libbsp_a_LIBADD = \
../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \
../../../libcpu/@RTEMS_CPU@/mpc8xx/console-generic.rel \

3
c/src/lib/libbsp/powerpc/virtex/Makefile.am
View File

@@ -66,10 +66,11 @@ endif
libbsp_a_SOURCES += timer/timer-config.c
libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/ppc403/timer.rel
libbsp_a_SOURCES += ../../../../../../bsps/powerpc/shared/cache/cache.c
libbsp_a_LIBADD += \
../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \
../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel
include $(top_srcdir)/../../../../automake/local.am

3
c/src/lib/libbsp/powerpc/virtex4/Makefile.am
View File

@@ -45,9 +45,10 @@ libbsp_a_SOURCES += irq/irq_init.c
# mmu
libbsp_a_SOURCES += mmu/mmu.c
libbsp_a_SOURCES += ../../../../../../bsps/powerpc/shared/cache/cache.c
libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \
../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
../../../libcpu/@RTEMS_CPU@/ppc403/clock.rel \
../../../libcpu/@RTEMS_CPU@/ppc403/timer.rel

3
c/src/lib/libbsp/powerpc/virtex5/Makefile.am
View File

@@ -47,9 +47,10 @@ libbsp_a_SOURCES += irq/irq_init.c
# mmu
libbsp_a_SOURCES += mmu/mmu.c
libbsp_a_SOURCES += ../../../../../../bsps/powerpc/shared/cache/cache.c
libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \
../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
../../../libcpu/@RTEMS_CPU@/e500/clock.rel \
../../../libcpu/@RTEMS_CPU@/e500/timer.rel

4
c/src/lib/libbsp/riscv/riscv_generic/Makefile.am
View File

@@ -63,9 +63,7 @@ libbsp_a_SOURCES += ../../shared/src/irq-info.c
libbsp_a_SOURCES += irq/irq.c
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
libbsp_a_SOURCES += ../../shared/include/cache_.h
libbsp_a_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/../../shared/include
libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
# debugio
libbsp_a_SOURCES += console/console-io.c

4
c/src/lib/libbsp/sh/gensh1/Makefile.am
View File

@@ -47,9 +47,7 @@ libbsp_a_SOURCES += console/sci.c
libbsp_a_SOURCES += ../../shared/dummy_printk_support.c
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
libbsp_a_SOURCES += ../../shared/include/cache_.h
libbsp_a_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/../../shared/include
libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
EXTRA_DIST += times

4
c/src/lib/libbsp/sh/gensh2/Makefile.am
View File

@@ -51,9 +51,7 @@ libbsp_a_SOURCES += console/sci_termios.c
libbsp_a_SOURCES += ../../shared/dummy_printk_support.c
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
libbsp_a_SOURCES += ../../shared/include/cache_.h
libbsp_a_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/../../shared/include
libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
include $(top_srcdir)/../../../../automake/local.am
include $(srcdir)/../../../../../../bsps/sh/gensh2/headers.am

4
c/src/lib/libbsp/sh/gensh4/Makefile.am
View File

@@ -38,9 +38,7 @@ libbsp_a_SOURCES += console/sh4uart.c
libbsp_a_SOURCES += hw_init/hw_init.c
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
libbsp_a_SOURCES += ../../shared/include/cache_.h
libbsp_a_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/../../shared/include
libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
EXTRA_DIST += times

4
c/src/lib/libbsp/sh/shsim/Makefile.am
View File

@@ -47,9 +47,7 @@ libbsp_a_SOURCES += console/console-debugio.c
libbsp_a_SOURCES += ../../shared/timerstub.c
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
libbsp_a_SOURCES += ../../shared/include/cache_.h
libbsp_a_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/../../shared/include
libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
include $(top_srcdir)/../../../../automake/local.am
include $(srcdir)/../../../../../../bsps/sh/shsim/headers.am

1
c/src/lib/libbsp/shared/include/cache_.h
View File

@@ -1 +0,0 @@
/* Empty */

3
c/src/lib/libbsp/sparc/erc32/Makefile.am
View File

@@ -76,9 +76,10 @@ if HAS_NETWORKING
libbsp_a_SOURCES += erc32sonic/erc32sonic.c
endif
libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
libbsp_a_LIBADD = \
../../../libcpu/@RTEMS_CPU@/access.rel \
../../../libcpu/@RTEMS_CPU@/cache.rel \
../../../libcpu/@RTEMS_CPU@/reg_win.rel \
../../../libcpu/@RTEMS_CPU@/syscall.rel

2
c/src/lib/libbsp/sparc/leon2/Makefile.am
View File

@@ -143,6 +143,7 @@ libbsp_a_SOURCES += ../../sparc/shared/analog/gradcdac.c
libbsp_a_SOURCES += ../../sparc/shared/mem/mctrl.c
# l2cache
libbsp_a_SOURCES += ../../sparc/shared/l2c/l2c.c
libbsp_a_SOURCES += ../../../../../../bsps/sparc/leon2/start/cache.c
# griommu
libbsp_a_SOURCES += ../../sparc/shared/iommu/griommu.c
# timer
@@ -177,7 +178,6 @@ endif
libbsp_a_LIBADD = \
../../../libcpu/@RTEMS_CPU@/access.rel \
../../../libcpu/@RTEMS_CPU@/cache.rel \
../../../libcpu/@RTEMS_CPU@/reg_win.rel \
../../../libcpu/@RTEMS_CPU@/syscall.rel

5
c/src/lib/libbsp/sparc/leon3/Makefile.am
View File

@@ -155,15 +155,12 @@ libbsp_a_SOURCES += ../../sparc/shared/analog/gradcdac.c
libbsp_a_SOURCES += ../../sparc/shared/mem/mctrl.c
# l2cache
libbsp_a_SOURCES += ../../sparc/shared/l2c/l2c.c
libbsp_a_SOURCES += ../../../../../../bsps/sparc/leon3/start/cache.c
# griommu
libbsp_a_SOURCES += ../../sparc/shared/iommu/griommu.c
# timer
libbsp_a_SOURCES += timer/timer.c
libbsp_a_SOURCES += timer/watchdog.c
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
libbsp_a_SOURCES += include/cache_.h
libbsp_a_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/include
# GR712
libbsp_a_SOURCES += ../../sparc/shared/ascs/grascs.c

202
c/src/lib/libbsp/sparc/leon3/include/cache_.h
View File

@@ -1,202 +0,0 @@
/*
* Copyright (c) 2014 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Dornierstr. 4
* 82178 Puchheim
* Germany
* <rtems@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef LEON3_CACHE_H
#define LEON3_CACHE_H
#include <amba.h>
#include <leon.h>
#ifdef __cplusplus
extern "C" {
#endif
#define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS
#define CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS
#define CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING
#define CPU_INSTRUCTION_CACHE_ALIGNMENT 64
#define CPU_DATA_CACHE_ALIGNMENT 64
static inline volatile struct l2c_regs *get_l2c_regs(void)
{
volatile struct l2c_regs *l2c = NULL;
struct ambapp_dev *adev;
adev = (void *) ambapp_for_each(
&ambapp_plb,
OPTIONS_ALL | OPTIONS_AHB_SLVS,
VENDOR_GAISLER,
GAISLER_L2CACHE,
ambapp_find_by_idx,
NULL
);
if (adev != NULL) {
l2c = (volatile struct l2c_regs *) DEV_TO_AHB(adev)->start[1];
}
return l2c;
}
static inline size_t get_l2_size(void)
{
size_t size = 0;
volatile struct l2c_regs *l2c = get_l2c_regs();
if (l2c != NULL) {
unsigned status = l2c->status;
unsigned ways = (status & 0x3) + 1;
unsigned set_size = ((status & 0x7ff) >> 2) * 1024;
size = ways * set_size;
}
return size;
}
static inline size_t get_l1_size(uint32_t l1_cfg)
{
uint32_t ways = ((l1_cfg >> 24) & 0x7) + 1;
uint32_t wsize = UINT32_C(1) << (((l1_cfg >> 20) & 0xf) + 10);
return ways * wsize;
}
static inline size_t get_max_size(size_t a, size_t b)
{
return a < b ? b : a;
}
static inline size_t get_cache_size(uint32_t level, uint32_t l1_cfg)
{
size_t size;
switch (level) {
case 0:
size = get_max_size(get_l1_size(l1_cfg), get_l2_size());
break;
case 1:
size = get_l1_size(l1_cfg);
break;
case 2:
size = get_l2_size();
break;
default:
size = 0;
break;
}
return size;
}
static inline size_t _CPU_cache_get_data_cache_size(uint32_t level)
{
return get_cache_size(level, leon3_get_data_cache_config_register());
}
static inline void _CPU_cache_flush_data_range(
const void *d_addr,
size_t n_bytes
)
{
/* TODO */
}
static inline void _CPU_cache_invalidate_data_range(
const void *d_addr,
size_t n_bytes
)
{
/* TODO */
}
static inline void _CPU_cache_freeze_data(void)
{
/* TODO */
}
static inline void _CPU_cache_unfreeze_data(void)
{
/* TODO */
}
static inline void _CPU_cache_invalidate_entire_instruction(void)
{
uint32_t cache_reg = leon3_get_cache_control_register();
cache_reg |= LEON3_REG_CACHE_CTRL_FI;
leon3_set_cache_control_register(cache_reg);
}
static inline void _CPU_cache_invalidate_instruction_range(
const void *i_addr,
size_t n_bytes
)
{
_CPU_cache_invalidate_entire_instruction();
}
static inline void _CPU_cache_freeze_instruction(void)
{
/* TODO */
}
static inline void _CPU_cache_unfreeze_instruction(void)
{
/* TODO */
}
static inline void _CPU_cache_flush_entire_data(void)
{
/* TODO */
}
static inline void _CPU_cache_invalidate_entire_data(void)
{
/* TODO */
}
static inline void _CPU_cache_enable_data(void)
{
/* TODO */
}
static inline void _CPU_cache_disable_data(void)
{
/* TODO */
}
static inline size_t _CPU_cache_get_instruction_cache_size( uint32_t level )
{
return get_cache_size(level, leon3_get_inst_cache_config_register());
}
static inline void _CPU_cache_enable_instruction(void)
{
/* TODO */
}
static inline void _CPU_cache_disable_instruction(void)
{
/* TODO */
}
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* LEON3_CACHE_H */

3
c/src/lib/libbsp/sparc64/niagara/Makefile.am
View File

@@ -50,9 +50,10 @@ noinst_LIBRARIES = libbsp.a
libbsp_a_SOURCES = $(startup_SOURCES) $(clock_SOURCES) $(console_SOURCES) \
$(timer_SOURCES)
libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
libbsp_a_LIBADD = \
../../../libcpu/@RTEMS_CPU@/shared/shared-score.rel \
../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
../../../libcpu/@RTEMS_CPU@/shared/sparc64-syscall.rel
include $(top_srcdir)/../../../../automake/local.am

2
c/src/lib/libbsp/sparc64/usiii/Makefile.am
View File

@@ -63,10 +63,10 @@ noinst_LIBRARIES = libbsp.a
libbsp_a_SOURCES = $(startup_SOURCES) $(mmu_SOURCES) $(clock_SOURCES) $(console_SOURCES) \
$(timer_SOURCES)
libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
libbsp_a_LIBADD = \
../../../libcpu/@RTEMS_CPU@/shared/shared-score.rel \
../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
../../../libcpu/@RTEMS_CPU@/shared/sparc64-syscall.rel
include $(top_srcdir)/../../../../automake/local.am

4
c/src/lib/libbsp/v850/gdbv850sim/Makefile.am
View File

@@ -38,9 +38,7 @@ libbsp_a_SOURCES += console/console-io.c
libbsp_a_SOURCES += ../../shared/timerstub.c
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
libbsp_a_SOURCES += ../../shared/include/cache_.h
libbsp_a_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/../../shared/include
libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
noinst_LIBRARIES = libbsp.a

2
c/src/lib/libcpu/Makefile.am
View File

@@ -1,6 +1,4 @@
EXTRA_DIST =
EXTRA_DIST += shared/include/cache.h
EXTRA_DIST += shared/src/cache_manager.c
_SUBDIRS = @libcpu_cpu_subdir@
DIST_SUBDIRS = @libcpu_cpu_subdir@

58
c/src/lib/libcpu/arm/shared/include/cache_.h
View File

@@ -1,58 +0,0 @@
/**
* @file
*
* @ingroup arm
*
* @brief ARM cache dummy include for chips without cache
*/
/*
* Copyright (c) 2009-2011 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Obere Lagerstr. 30
* 82178 Puchheim
* Germany
* <rtems@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef LIBCPU_ARM_CACHE__H
#define LIBCPU_ARM_CACHE__H
/*
* The ARM targets equipped by cache should include
* which kind and implementation they support.
* Next options are available
*
* c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h
* basic ARM cache integrated on the CPU core directly
* which requires only CP15 oparations
*
* c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
* support for case where ARM L2C-310 cache controller
* is used. It is accessible as mmaped peripheral.
*
* c/src/lib/libbsp/arm/shared/armv7m/include/cache_.h
* Cortex-M specific cache support
*
* Cache support should be included in BSP Makefile.am
*
* Example how to include cache support
*
* # Cache
* libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
* libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
* libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h
* libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache
*/
#if defined(__ARM_ARCH_5TEJ__) || defined(__ARM_ARCH_7A__)
#warning ARM 5TEJ and ARMv7/Cortex-A cores include usually cache
#warning change BSP to include appropriate cache implementation
#endif
#endif /* LIBCPU_ARM_CACHE__H */

6
c/src/lib/libcpu/bfin/Makefile.am
View File

@@ -22,12 +22,6 @@ endif
# endof bf52x
############
noinst_PROGRAMS += cache.rel
cache_rel_SOURCES = cache/cache.c \
../shared/src/cache_manager.c cache/cache_.h
cache_rel_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/cache
cache_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
noinst_PROGRAMS += mmu.rel
mmu_rel_SOURCES = mmu/mmu.c
mmu_rel_CPPFLAGS = $(AM_CPPFLAGS)

125
c/src/lib/libcpu/bfin/cache/cache.c vendored
View File

@@ -1,125 +0,0 @@
/* Blackfin Cache Support
*
* Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA
* written by Allan Hessenflow <allanh@kallisti.com>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <rtems.h>
#include <bsp.h>
#include <libcpu/memoryRegs.h>
#include "cache_.h"
/* There are many syncs in the following code because they should be
harmless except for wasting time, and this is easier than figuring out
exactly where they're needed to protect from the effects of write
buffers and queued reads. Many of them are likely unnecessary. */
void _CPU_cache_flush_1_data_line(const void *d_addr) {
__asm__ __volatile__ ("ssync; flush [%0]; ssync" :: "a" (d_addr));
}
/* Blackfins can't just invalidate cache; they can only do flush +
invalidate. If the line isn't dirty then this is equivalent to
just an invalidate. Even if it is dirty, this should still be
okay since with a pure invalidate method the caller would have no
way to insure the dirty line hadn't been written out anyway prior
to the invalidate. */
void _CPU_cache_invalidate_1_data_line(const void *d_addr) {
__asm__ __volatile__ ("ssync; flushinv [%0]; ssync" :: "a" (d_addr));
}
void _CPU_cache_freeze_data(void) {
}
void _CPU_cache_unfreeze_data(void) {
}
void _CPU_cache_invalidate_1_instruction_line(const void *d_addr) {
__asm__ __volatile__ ("ssync; iflush [%0]; ssync" :: "a" (d_addr));
}
void _CPU_cache_freeze_instruction(void) {
}
void _CPU_cache_unfreeze_instruction(void) {
}
/* incredibly inefficient... It would be better to make use of the
DTEST_COMMAND/DTEST_DATAx registers to find the addresses in each
cache line and flush just those. However the documentation I've
seen on those is a bit sketchy, and I sure wouldn't want to get it
wrong. */
void _CPU_cache_flush_entire_data(void) {
uint32_t i;
i = 0;
__asm__ __volatile__ ("ssync");
do {
__asm__ __volatile__ ("flush [%0]" :: "a" (i));
i += CPU_DATA_CACHE_ALIGNMENT;
} while (i);
__asm__ __volatile__ ("ssync");
}
void _CPU_cache_invalidate_entire_data(void) {
uint32_t dmemControl;
__asm__ __volatile__ ("ssync");
dmemControl = *(uint32_t volatile *) DMEM_CONTROL;
*(uint32_t volatile *) DMEM_CONTROL = dmemControl & ~DMEM_CONTROL_DMC_MASK;
*(uint32_t volatile *) DMEM_CONTROL = dmemControl;
__asm__ __volatile__ ("ssync");
}
/* this does not actually enable data cache unless CPLBs are also enabled.
LIBCPU_DATA_CACHE_CONFIG contains the DMEM_CONTROL_DMC bits to set. */
void _CPU_cache_enable_data(void) {
__asm__ __volatile__ ("ssync");
*(uint32_t volatile *) DMEM_CONTROL |= LIBCPU_DATA_CACHE_CONFIG;
__asm__ __volatile__ ("ssync");
}
void _CPU_cache_disable_data(void) {
__asm__ __volatile__ ("ssync");
*(uint32_t volatile *) DMEM_CONTROL &= ~DMEM_CONTROL_DMC_MASK;
__asm__ __volatile__ ("ssync");
}
void _CPU_cache_invalidate_entire_instruction(void) {
uint32_t imemControl;
__asm__ __volatile__ ("ssync");
imemControl = *(uint32_t volatile *) IMEM_CONTROL;
*(uint32_t volatile *) IMEM_CONTROL = imemControl & ~IMEM_CONTROL_IMC;
*(uint32_t volatile *) IMEM_CONTROL = imemControl;
__asm__ __volatile__ ("ssync");
}
/* this only actually enables the instruction cache if the CPLBs are also
enabled. */
void _CPU_cache_enable_instruction(void) {
__asm__ __volatile__ ("ssync");
*(uint32_t volatile *) IMEM_CONTROL |= IMEM_CONTROL_IMC;
__asm__ __volatile__ ("ssync");
}
void _CPU_cache_disable_instruction(void) {
__asm__ __volatile__ ("ssync");
*(uint32_t volatile *) IMEM_CONTROL &= ~IMEM_CONTROL_IMC;
__asm__ __volatile__ ("ssync");
}

21
c/src/lib/libcpu/bfin/cache/cache_.h vendored
View File

@@ -1,21 +0,0 @@
/*
* Blackfin Cache Manager Support
*/
#ifndef _cache__h_
#define _cache__h_
#include "../../shared/include/cache.h"
#define CPU_DATA_CACHE_ALIGNMENT 32
#define CPU_INSTRUCTION_CACHE_ALIGNMENT 32
#ifdef BSP_DATA_CACHE_CONFIG
#define LIBCPU_DATA_CACHE_CONFIG BSP_DATA_CACHE_CONFIG
#else
/* use 16K of each SRAM bank */
#define LIBCPU_DATA_CACHE_CONFIG (3 << DMEM_CONTROL_DMC_SHIFT)
#endif
#endif /* _cache__h_ */

6
c/src/lib/libcpu/i386/Makefile.am
View File

@@ -4,12 +4,6 @@ noinst_PROGRAMS =
include $(top_srcdir)/../../../automake/compile.am
noinst_PROGRAMS += cache.rel
cache_rel_SOURCES = cache.c cache_.h \
../shared/src/cache_manager.c ../shared/include/cache.h
cache_rel_CPPFLAGS = $(AM_CPPFLAGS)
cache_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
noinst_PROGRAMS += score.rel
score_rel_SOURCES = displayCpu.c cpuModel.S cpuModel.h idtr.S cpu.h
score_rel_CPPFLAGS = $(AM_CPPFLAGS)

88
c/src/lib/libcpu/i386/cache.c
View File

@@ -1,88 +0,0 @@
/*
* Cache Management Support Routines for the i386
*/
#include <rtems.h>
#include "cache_.h"
#include <rtems/score/cpu.h>
#include <libcpu/page.h>
void _CPU_disable_cache(void)
{
unsigned int regCr0;
regCr0 = i386_get_cr0();
regCr0 |= CR0_PAGE_LEVEL_CACHE_DISABLE;
regCr0 |= CR0_NO_WRITE_THROUGH;
i386_set_cr0( regCr0 );
rtems_cache_flush_entire_data();
}
/*
* Enable the entire cache
*/
void _CPU_enable_cache(void)
{
unsigned int regCr0;
regCr0 = i386_get_cr0();
regCr0 &= ~(CR0_PAGE_LEVEL_CACHE_DISABLE);
regCr0 &= ~(CR0_NO_WRITE_THROUGH);
i386_set_cr0( regCr0 );
/*rtems_cache_flush_entire_data();*/
}
/*
* CACHE MANAGER: The following functions are CPU-specific.
* They provide the basic implementation for the rtems_* cache
* management routines. If a given function has no meaning for the CPU,
* it does nothing by default.
*
* FIXME: The routines below should be implemented per CPU,
* to accomodate the capabilities of each.
*/
#if defined(I386_CACHE_ALIGNMENT)
void _CPU_cache_flush_1_data_line(const void *d_addr) {}
void _CPU_cache_invalidate_1_data_line(const void *d_addr) {}
void _CPU_cache_freeze_data(void) {}
void _CPU_cache_unfreeze_data(void) {}
void _CPU_cache_invalidate_1_instruction_line ( const void *d_addr ) {}
void _CPU_cache_freeze_instruction(void) {}
void _CPU_cache_unfreeze_instruction(void) {}
void _CPU_cache_flush_entire_data(void)
{
__asm__ volatile ("wbinvd");
}
void _CPU_cache_invalidate_entire_data(void)
{
__asm__ volatile ("invd");
}
void _CPU_cache_enable_data(void)
{
_CPU_enable_cache();
}
void _CPU_cache_disable_data(void)
{
_CPU_disable_cache();
}
void _CPU_cache_invalidate_entire_instruction(void)
{
__asm__ volatile ("invd");
}
void _CPU_cache_enable_instruction(void)
{
_CPU_enable_cache();
}
void _CPU_cache_disable_instruction( void )
{
_CPU_disable_cache();
}
#endif

15
c/src/lib/libcpu/i386/cache_.h
View File

@@ -1,15 +0,0 @@
/*
* i386 Cache Manager Wrapper
*/
#ifndef __i386_CACHE_h
#define __i386_CACHE_h
#define I386_CACHE_ALIGNMENT 16
#define CPU_DATA_CACHE_ALIGNMENT I386_CACHE_ALIGNMENT
#define CPU_INSTRUCTION_CACHE_ALIGNEMNT I386_CACHE_ALIGNMENT
#include "../shared/include/cache.h"
#endif
/* end of include file */

7
c/src/lib/libcpu/lm32/Makefile.am
View File

@@ -7,13 +7,6 @@ DISTCLEANFILES =
noinst_PROGRAMS =
if shared
noinst_PROGRAMS += shared/cache.rel
shared_cache_rel_SOURCES = ../shared/src/no_cache.c shared/cache/cache_.h \
../shared/src/cache_manager.c
shared_cache_rel_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/shared/cache
shared_cache_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
## shared/misc
noinst_PROGRAMS += shared/misc.rel
shared_misc_rel_SOURCES = shared/misc/memcpy.c

11
c/src/lib/libcpu/lm32/shared/cache/cache_.h vendored
View File

@@ -1,11 +0,0 @@
/*
* LM32 Cache Manager Support
*/
#ifndef __LM32_CACHE_h
#define __LM32_CACHE_h
#include "../../../shared/include/cache.h"
#endif
/* end of include file */

55
c/src/lib/libcpu/m68k/Makefile.am
View File

@@ -6,13 +6,6 @@ noinst_PROGRAMS =
if shared
noinst_PROGRAMS += shared/cache.rel
shared_cache_rel_SOURCES = shared/cache/cache.c
shared_cache_rel_SOURCES += shared/cache/cache_.h
shared_cache_rel_SOURCES += ../shared/src/cache_manager.c
shared_cache_rel_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/shared/cache
shared_cache_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
## shared/misc
# gcc doesn't recognize difference between the cpu32 and cpu32+ so we have to
@@ -92,46 +85,6 @@ mcf5206_timer_rel_CPPFLAGS = $(AM_CPPFLAGS)
mcf5206_timer_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
endif
if mcf5223x
## mcf5223x/include
## mcf5223x/cache
noinst_PROGRAMS += mcf5223x/cachepd.rel
mcf5223x_cachepd_rel_SOURCES = mcf5223x/cache/cachepd.c
mcf5223x_cachepd_rel_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/shared/cache
mcf5223x_cachepd_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
endif
if mcf5225x
## mcf5225x/include
# mcf5225x/cache
noinst_PROGRAMS += mcf5225x/cachepd.rel
mcf5225x_cachepd_rel_SOURCES = mcf5225x/cache/cachepd.c
mcf5225x_cachepd_rel_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/shared/cache
mcf5225x_cachepd_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
# Network
if HAS_NETWORKING
endif ## HAS_NETWORKING
endif
if mcf5235
## mcf5235/include
## mcf5235/cache
noinst_PROGRAMS += mcf5235/cachepd.rel
mcf5235_cachepd_rel_SOURCES = mcf5235/cache/cachepd.c
mcf5235_cachepd_rel_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/shared/cache
mcf5235_cachepd_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
endif
if mcf532x
## mcf532x/include
## mcf532x/cache
noinst_PROGRAMS += mcf532x/cachepd.rel
mcf532x_cachepd_rel_SOURCES = mcf532x/cache/cachepd.c
mcf532x_cachepd_rel_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/shared/cache
mcf532x_cachepd_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
endif
if mcf5272
## mcf5272/include
## clock
@@ -147,14 +100,6 @@ mcf5272_timer_rel_CPPFLAGS = $(AM_CPPFLAGS)
mcf5272_timer_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
endif
if mcf5282
## mcf5282/include
noinst_PROGRAMS += mcf5282/cachepd.rel
mcf5282_cachepd_rel_SOURCES = mcf5282/cache/cachepd.c
mcf5282_cachepd_rel_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/shared/cache
mcf5282_cachepd_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
endif
if mcf548x
## mcf548x/include
## mcf548x/mcdma

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