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Clean up UART2 pin setup. Protect pin setup code.

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This commit is contained in:
Eric Norum
2005-11-11 15:48:24 +00:00
parent dc35ca4374
commit 46fa1f6404
3 changed files with 12 additions and 2 deletions
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4
c/src/lib/libbsp/m68k/uC5282/ChangeLog
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@@ -1,3 +1,7 @@
2005-11-11 Eric Norum <norume@aps.anl.gov>
* console/console.c: Clean up UART2 pin setup. Protect pin setup code.
2005-11-08 Eric Norum <norume@aps.anl.gov> 2005-11-08 Eric Norum <norume@aps.anl.gov>
* console/console.c: Add code to set up pin assignments * console/console.c: Add code to set up pin assignments

3
c/src/lib/libbsp/m68k/uC5282/README
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@@ -26,7 +26,8 @@ The bsp relies on the Arcturus monitor to set up DRAM and all chip selects.
This seems OK to me, but others may find it lame..... This seems OK to me, but others may find it lame.....
I/O pin restrictions make simultaneous operation I/O pin restrictions make simultaneous operation
of I2C, CAN and UART2 impossible. of I2C, CAN and UART2 impossible. The BSP configures UART2 to
use the CAN pins and leaves the I2C pins available for use.
BSP NAME: uC5282 BSP NAME: uC5282
BOARD: Arcturus Netrworks uCdimm 5282 BOARD: Arcturus Netrworks uCdimm 5282

7
c/src/lib/libbsp/m68k/uC5282/console/console.c
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@@ -472,10 +472,12 @@ static int
IntUartInterruptOpen(int major, int minor, void *arg) IntUartInterruptOpen(int major, int minor, void *arg)
{ {
struct IntUartInfoStruct *info = &IntUartInfo[minor]; struct IntUartInfoStruct *info = &IntUartInfo[minor];
int level;
/* /*
* Enable serial I/O pin assignments * Enable serial I/O pin assignments
*/ */
rtems_interrupt_disable(level);
switch(minor) { switch(minor) {
case 0: case 0:
MCF5282_GPIO_PUAPAR |= MCF5282_GPIO_PUAPAR_PUAPA1|MCF5282_GPIO_PUAPAR_PUAPA0; MCF5282_GPIO_PUAPAR |= MCF5282_GPIO_PUAPAR_PUAPA1|MCF5282_GPIO_PUAPAR_PUAPA0;
@@ -484,9 +486,12 @@ IntUartInterruptOpen(int major, int minor, void *arg)
MCF5282_GPIO_PUAPAR |= MCF5282_GPIO_PUAPAR_PUAPA3|MCF5282_GPIO_PUAPAR_PUAPA2; MCF5282_GPIO_PUAPAR |= MCF5282_GPIO_PUAPAR_PUAPA3|MCF5282_GPIO_PUAPAR_PUAPA2;
break; break;
case 2: case 2:
MCF5282_GPIO_PASPAR |= MCF5282_GPIO_PASPAR_PASPA3(2)|MCF5282_GPIO_PASPAR_PASPA2(2); MCF5282_GPIO_PASPAR = MCF5282_GPIO_PASPAR
& ~(MCF5282_GPIO_PASPAR_PASPA3(3)|MCF5282_GPIO_PASPAR_PASPA2(3))
| (MCF5282_GPIO_PASPAR_PASPA3(2)|MCF5282_GPIO_PASPAR_PASPA2(2));
break; break;
} }
rtems_interrupt_enable(level);
/* enable the uart */ /* enable the uart */
MCF5282_UART_UCR(minor) = (MCF5282_UART_UCR_TX_ENABLED | MCF5282_UART_UCR_RX_ENABLED); MCF5282_UART_UCR(minor) = (MCF5282_UART_UCR_TX_ENABLED | MCF5282_UART_UCR_RX_ENABLED);