mirror of
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Remove (dead port).
This commit is contained in:
Ralf Corsepius
@@ -1,2 +0,0 @@
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Makefile
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Makefile.in
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@@ -1,422 +0,0 @@
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2010-03-27 Joel Sherrill <joel.sherrill@oarcorp.com>
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* cpu.c, cpu_asm.S, irq.c: Add include of config.h
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2009-02-12 Joel Sherrill <joel.sherrill@oarcorp.com>
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* cpu.c: Change prototype of IDLE thread to consistently return void *
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and take a uintptr_t argument.
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2009-02-11 Joel Sherrill <joel.sherrill@oarcorp.com>
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* cpu.c, rtems/score/cpu.h: Eliminate _CPU_Thread_dispatch_pointer and
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passing address of _Thread_Dispatch to _CPU_Initialize. Clean up
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comments.
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2008-09-11 Ralf Corsépius <ralf.corsepius@rtems.org>
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* rtems/score/types.h: Do not define boolean, single_precision,
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double_precision unless RTEMS_DEPRECATED_TYPES is given.
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2008-08-21 Ralf Corsépius <ralf.corsepius@rtems.org>
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* rtems/score/types.h: Include stdbool.h.
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Use bool as base-type for boolean.
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2008-07-31 Joel Sherrill <joel.sherrill@OARcorp.com>
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* cpu.c, rtems/score/cpu.h: Correct prototype of Idle threads.
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2008-06-05 Joel Sherrill <joel.sherrill@OARcorp.com>
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* rtems/score/cpu.h: Add CPU_SIMPLE_VECTORED_INTERRUPTS porting
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parameter to indicate that the port uses the Simple Vectored
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Interrupt model or the Programmable Interrupt Controller Model. The
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PIC model is implemented primarily in the BSP and it is responsible
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for all memory allocation.
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2007-12-17 Joel Sherrill <joel.sherrill@oarcorp.com>
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* rtems/score/cpu.h: Add _CPU_Context_Get_SP() for stack check utility.
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2007-12-17 Joel Sherrill <joel.sherrill@OARcorp.com>
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* rtems/tic4x/c4xio.h: Sweep to make sure grep for COPYRIGHT passes.
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2007-12-04 Joel Sherrill <joel.sherrill@OARcorp.com>
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* cpu.c, rtems/score/cpu.h: Move interrupt_stack_size field from CPU
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Table to Configuration Table. Eliminate CPU Table from all ports.
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Delete references to CPU Table in all forms.
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2007-12-03 Joel Sherrill <joel.sherrill@OARcorp.com>
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* rtems/score/cpu.h: Moved most of the remaining CPU Table fields to
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the Configuration Table. This included pretasking_hook,
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predriver_hook, postdriver_hook, idle_task, do_zero_of_workspace,
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extra_mpci_receive_server_stack, stack_allocate_hook, and
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stack_free_hook. As a side-effect of this effort some multiprocessing
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code was made conditional and some style clean up occurred.
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2007-05-09 Ralf Corsépius <ralf.corsepius@rtems.org>
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* rtems/score/cpu.h: Remove CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES.
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2007-04-17 Ralf Corsépius <ralf.corsepius@rtems.org>
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* rtems/score/cpu.h:
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Use Context_Control_fp* instead of void* for fp_contexts.
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Eliminate evil casts.
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2007-01-30 Ralf Corsépius <ralf.corsepius@rtems.org>
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* rtems/score/types.h: Use uint_least16_t for
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Priority_Bit_map_control;
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2006-11-17 Ralf Corsépius <ralf.corsepius@rtems.org>
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* rtems/score/types.h: Remove unsigned64, signed64.
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2006-01-16 Joel Sherrill <joel@OARcorp.com>
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* rtems/score/cpu.h: Part of a large patch to improve Doxygen output.
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As a side-effect, grammar and spelling errors were corrected, spacing
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errors were address, and some variable names were improved.
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2005-11-08 Ralf Corsepius <ralf.corsepius@rtems.org>
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* rtems/score/types.h: Eliminate unsigned16, unsigned32.
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2005-10-27 Ralf Corsepius <ralf.corsepius@rtems.org>
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* rtems/asm.h: Remove private version of CONCAT macros.
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Include <rtems/concat.h> instead.
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2005-02-08 Ralf Corsepius <ralf.corsepius@rtems.org>
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* Makefile.am: Split out preinstallation rules.
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* preinstall.am: New (Split out from Makefile.am).
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2005-02-04 Ralf Corsepius <ralf.corsepius@rtems.org>
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PR 754/rtems
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* rtems/asm.h: New (relocated from .).
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* asm.h: Remove (moved to rtems/asm.h).
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* Makefile.am: Reflect changes above.
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2005-02-02 Ralf Corsepius <ralf.corsepius@rtems.org>
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PR rtems/752
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* rtems/tic4x/c4xio.h: New (relocated from .).
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New header guard.
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* c4xio.h: Remove.
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* Makefile.am: Reflect changes above.
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2004-01-28 Ralf Corsepius <ralf.corsepiu@rtems.org>
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* asm.h, rtems/score/c4x.h, rtems/score/cpu.h,
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rtems/score/cpu_asm.h, rtems/score/types.h: New header guards.
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2005-01-24 Ralf Corsepius <ralf.corsepius@rtems.org>
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* rtems/score/types.h: Remove signed8, signed16, signed32,
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unsigned8, unsigned16, unsigned32.
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2005-01-24 Ralf Corsepius <ralf.corsepius@rtems.org>
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* rtems/score/cpu.h: *_swap_u32( uint32_t ).
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2005-01-24 Ralf Corsepius <ralf.corsepius@rtems.org>
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* rtems/score/types.h: #include <rtems/stdint.h>.
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2005-01-07 Ralf Corsepius <ralf.corsepius@rtems.org>
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* Makefile.am: Eliminate CFLAGS_OPTIMIZE_V.
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2005-01-01 Ralf Corsepius <ralf.corsepius@rtems.org>
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* Makefile.am: Remove build-variant support.
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2004-11-21 Ralf Corsepius <ralf.corsepius@rtems.org>
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* rtems/score/types.h: Use __rtems_score_types_h as preprocessor
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guard.
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2004-11-21 Ralf Corsepius <ralf.corsepius@rtems.org>
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* asm.h: Add doxygen preamble.
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2004-10-02 Ralf Corsepius <ralf_corsepius@rtems.org>
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* rtems/score/c4x.h: Add doxygen preamble.
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* rtems/score/cpu.h: Add doxygen preamble.
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||||
* rtems/score/cpu_asm.h: Add doxygen preamble.
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* rtems/score/types.h: Add doxygen preamble.
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2004-09-29 Joel Sherrill <joel@OARcorp.com>
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* rtems/score/cpu.h: i960 obsoleted and all references removed.
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||||
2004-04-06 Ralf Corsepius <ralf_corsepius@rtems.org>
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* configure.ac: Remove (Merged into $(top_srcdir)/configure.ac).
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* Makefile.am: Don't include multilib.am.
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Reflect merging configure.ac into $(top_srcdir)/configure.ac.
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2004-04-02 Ralf Corsepius <ralf_corsepius@rtems.org>
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||||
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* Makefile.am: Install c4xio.h to $(includedir)/rtems/c4x.
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2004-04-01 Ralf Corsepius <ralf_corsepius@rtems.org>
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* Makefile.am: Install asm.h to $(includedir)/rtems.
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2004-04-01 Ralf Corsepius <ralf_corsepius@rtems.org>
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* cpu_asm.S: Include <rtems/asm.h> instead of <asm.h>.
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2004-03-30 Ralf Corsepius <ralf_corsepius@rtems.org>
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* c4xio.h, cpu.c, irq.c, rtems/score/cpu.h: Convert to using c99
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fixed size types.
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2004-03-29 Ralf Corsepius <ralf_corsepius@rtems.org>
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* configure.ac: RTEMS_TOP([../../../..]).
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2004-01-21 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
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* configure.ac: Move RTEMS_TOP one subdir down.
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2004-01-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
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* Makefile.am: Add PREINSTALL_DIRS.
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2004-01-14 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
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* Makefile.am: Re-add dirstamps to PREINSTALL_FILES.
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Add PREINSTALL_FILES to CLEANFILES.
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2004-01-12 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
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* configure.ac: Requires automake >= 1.8.1.
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2004-01-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
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* Makefile.am: Include compile.am, again.
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||||
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||||
2004-01-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
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||||
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||||
* Makefile.am: Convert to using automake compilation rules.
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||||
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||||
2003-12-12 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
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* Makefile.am: Use mkdir_p. Remove dirs from PREINSTALL_FILES.
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||||
2003-12-12 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
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||||
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||||
* configure.ac: Require automake >= 1.8, autoconf >= 2.59.
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||||
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||||
2003-12-01 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
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||||
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||||
* Makefile.am: Remove TMPINSTALL_FILES.
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||||
|
||||
2003-11-30 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
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||||
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||||
* Makefile.am: Add $(dirstamp) to preinstallation rules.
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||||
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||||
2003-11-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
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||||
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* Makefile.am: Don't use gmake rules for preinstallation.
|
||||
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||||
2003-10-21 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
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||||
* configure.ac: Remove RTEMS_CANONICAL_HOST.
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||||
|
||||
2003-10-21 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
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||||
* configure.ac: Remove RTEMS_CHECK_CPU.
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||||
|
||||
2003-09-26 Joel Sherrill <joel@OARcorp.com>
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||||
|
||||
* rtems/score/cpu.h: Obsoleting HP PA-RISC port and removing all
|
||||
references.
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||||
|
||||
2003-09-04 Joel Sherrill <joel@OARcorp.com>
|
||||
|
||||
* cpu.c, cpu_asm.S, irq.c, rtems/score/c4x.h, rtems/score/cpu.h,
|
||||
rtems/score/cpu_asm.h, rtems/score/types.h: URL for license changed.
|
||||
|
||||
2003-08-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* configure.ac: Use rtems-bugs@rtems.com as bug report email address.
|
||||
|
||||
2003-03-06 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* configure.ac: Remove AC_CONFIG_AUX_DIR.
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||||
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2003-02-11 Joel Sherrill <joel@OARcorp.com>
|
||||
|
||||
* irq.c: Rework logic that decides when to call
|
||||
_Thread_Dispatch. Analysis by Sergei Organov <osv@javad.ru>
|
||||
determined that _ISR_Signals_to_thread_executing was not being
|
||||
honored and/or cleared properly.
|
||||
|
||||
2002-12-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* configure.ac: Require autoconf-2.57 + automake-1.7.2.
|
||||
* Makefile.am: Eliminate C_O_FILES, S_O_FILES, libscorecpu_a_OBJECTS.
|
||||
|
||||
2002-11-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* configure.ac: Fix package name.
|
||||
|
||||
2002-10-25 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* configure.ac: Add nostdinc to AM_INIT_AUTOMAKE.
|
||||
|
||||
2002-10-21 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* .cvsignore: Reformat.
|
||||
Add autom4te*cache.
|
||||
Remove autom4te.cache.
|
||||
|
||||
2002-07-26 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* Makefile.am: Build libscorecpu.a instead of rtems-cpu.rel.
|
||||
|
||||
2002-07-22 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* Makefile.am: Use .$(OBJEXT) instead of .o.
|
||||
|
||||
2002-07-22 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* Makefile.am: Use . instead of .o.
|
||||
|
||||
2002-07-05 Joel Sherrill <joel@OARcorp.com>
|
||||
|
||||
* cpu.c, irq.c, rtems/score/cpu.h: Filled in something that was
|
||||
marked XXX.
|
||||
|
||||
2002-07-05 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* configure.ac: RTEMS_TOP(../../../..).
|
||||
|
||||
2002-07-03 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* rtems.c: Remove.
|
||||
* Makefile.am: Reflect changes above.
|
||||
|
||||
2002-07-01 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* configure.ac: Remove RTEMS_PROJECT_ROOT.
|
||||
|
||||
2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* configure.ac: Add RTEMS_PROG_CCAS
|
||||
|
||||
2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* configure.ac: Use AC_CONFIG_AUX_DIR(../../../..).
|
||||
Add AC_PROG_RANLIB.
|
||||
|
||||
2002-06-17 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* Makefile.am: Include $(top_srcdir)/../../../automake/*.am.
|
||||
Use ../../../aclocal.
|
||||
|
||||
2001-04-03 Joel Sherrill <joel@OARcorp.com>
|
||||
|
||||
* Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
|
||||
* rtems/score/c4xtypes.h: Removed.
|
||||
* rtems/score/types.h: New file via CVS magic.
|
||||
* Makefile.am, rtems/score/cpu.h: Account for name change.
|
||||
|
||||
2002-03-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* configure.ac:
|
||||
AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS).
|
||||
AM_INIT_AUTOMAKE([no-define foreign 1.6]).
|
||||
* Makefile.am: Remove AUTOMAKE_OPTIONS.
|
||||
|
||||
2002-01-29 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* rtems/Makefile.am: Removed.
|
||||
* rtems/score/Makefile.am: Removed.
|
||||
* configure.ac: Reflect changes above.
|
||||
* Makefile.am: Reflect changes above.
|
||||
|
||||
2002-02-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* asm.h: Remove #include <rtems/score/targopts.h>.
|
||||
Add #include <rtems/score/cpuopts.h>.
|
||||
|
||||
|
||||
|
||||
2002-02-05 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP.
|
||||
|
||||
2001-12-20 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* configure.ac: Use RTEMS_ENV_RTEMSCPU.
|
||||
|
||||
2001-12-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* Makefile.am: Add multilib support.
|
||||
|
||||
2001-11-28 Joel Sherrill <joel@OARcorp.com>,
|
||||
|
||||
This was tracked as PR91.
|
||||
* rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
|
||||
is used to specify if the port uses the standard macro for this (FALSE).
|
||||
A TRUE setting indicates the port provides its own implementation.
|
||||
|
||||
2001-10-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* .cvsignore: Add autom4te.cache for autoconf > 2.52.
|
||||
* configure.in: Remove.
|
||||
* configure.ac: New file, generated from configure.in by autoupdate.
|
||||
|
||||
2001-09-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
|
||||
* Makefile.am: Use 'PREINSTALL_FILES ='.
|
||||
|
||||
2001-02-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* Makefile.am, rtems/score/Makefile.am:
|
||||
Apply include_*HEADERS instead of H_FILES.
|
||||
|
||||
2001-01-03 Joel Sherrill <joel@OARcorp.com>
|
||||
|
||||
* rtems/score/cpu.h: Added _CPU_Initialize_vectors().
|
||||
|
||||
2000-11-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
|
||||
|
||||
2000-11-02 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
|
||||
|
||||
2000-10-25 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
|
||||
Switch to GNU canonicalization.
|
||||
|
||||
2000-10-18 Joel Sherrill <joel@OARcorp.com>
|
||||
|
||||
* rtems/score/c4x.h: Modified to properly multilib. This required
|
||||
using only macros predefined by gcc.
|
||||
|
||||
2000-09-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
|
||||
|
||||
* Makefile.am: Include compile.am, formatting.
|
||||
* rtems/Makefile.am: formatting.
|
||||
* rtems/score/Makefile.am: formatting.
|
||||
|
||||
2000-08-10 Joel Sherrill <joel@OARcorp.com>
|
||||
|
||||
* ChangeLog: New file.
|
||||
@@ -1,22 +0,0 @@
|
||||
##
|
||||
## $Id$
|
||||
##
|
||||
|
||||
include $(top_srcdir)/automake/compile.am
|
||||
|
||||
include_rtemsdir = $(includedir)/rtems
|
||||
include_rtems_HEADERS = rtems/asm.h
|
||||
|
||||
include_rtems_tic4xdir = $(includedir)/rtems/tic4x
|
||||
include_rtems_tic4x_HEADERS = rtems/tic4x/c4xio.h
|
||||
|
||||
include_rtems_scoredir = $(includedir)/rtems/score
|
||||
include_rtems_score_HEADERS = rtems/score/cpu.h rtems/score/c4x.h \
|
||||
rtems/score/types.h rtems/score/cpu_asm.h
|
||||
|
||||
noinst_LIBRARIES = libscorecpu.a
|
||||
libscorecpu_a_SOURCES = cpu.c irq.c cpu_asm.S
|
||||
libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS)
|
||||
|
||||
include $(srcdir)/preinstall.am
|
||||
include $(top_srcdir)/automake/local.am
|
||||
@@ -1,180 +0,0 @@
|
||||
/*
|
||||
* C4x CPU Dependent Source
|
||||
*
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1999.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.com/license/LICENSE.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifdef HAVE_CONFIG_H
|
||||
#include "config.h"
|
||||
#endif
|
||||
|
||||
#include <rtems/system.h>
|
||||
#include <rtems/score/isr.h>
|
||||
#include <rtems/score/wkspace.h>
|
||||
|
||||
/* _CPU_Initialize
|
||||
*
|
||||
* This routine performs processor dependent initialization.
|
||||
*
|
||||
* INPUT PARAMETERS: NONE
|
||||
*
|
||||
* C4x Specific Information:
|
||||
*
|
||||
*/
|
||||
|
||||
void _CPU_Initialize(void)
|
||||
{
|
||||
#if (CPU_HARDWARE_FP == TRUE)
|
||||
/*
|
||||
* If there is not an easy way to initialize the FP context
|
||||
* during Context_Initialize, then it is usually easier to
|
||||
* save an "uninitialized" FP context here and copy it to
|
||||
* the task's during Context_Initialize.
|
||||
*/
|
||||
|
||||
/* FP context initialization support goes here */
|
||||
#endif
|
||||
}
|
||||
|
||||
/*PAGE
|
||||
*
|
||||
* _CPU_ISR_install_raw_handler
|
||||
*
|
||||
* C4x Specific Information:
|
||||
*
|
||||
*/
|
||||
|
||||
void _CPU_ISR_install_raw_handler(
|
||||
uint32_t vector,
|
||||
proc_ptr new_handler,
|
||||
proc_ptr *old_handler
|
||||
)
|
||||
{
|
||||
void **ittp;
|
||||
|
||||
/*
|
||||
* This is where we install the interrupt handler into the "raw" interrupt
|
||||
* table used by the CPU to dispatch interrupt handlers.
|
||||
*/
|
||||
|
||||
ittp = c4x_get_ittp();
|
||||
*old_handler = ittp[ vector ];
|
||||
ittp[ vector ] = new_handler;
|
||||
}
|
||||
|
||||
/*XXX */
|
||||
|
||||
#define C4X_CACHE 1
|
||||
#define C4X_BASE_ST (C4X_CACHE==1) ? 0x4800 : 0x4000
|
||||
|
||||
void _CPU_Context_Initialize(
|
||||
Context_Control *_the_context,
|
||||
void *_stack_base,
|
||||
uint32_t _size,
|
||||
uint32_t _isr,
|
||||
void (*_entry_point)(void),
|
||||
int _is_fp
|
||||
)
|
||||
{
|
||||
unsigned int *_stack;
|
||||
_stack = (unsigned int *)_stack_base;
|
||||
|
||||
*_stack = (unsigned int) _entry_point;
|
||||
_the_context->sp = (unsigned int) _stack;
|
||||
_the_context->st = C4X_BASE_ST;
|
||||
if ( _isr == 0 )
|
||||
_the_context->st |= C4X_ST_GIE;
|
||||
}
|
||||
|
||||
/*PAGE
|
||||
*
|
||||
* _CPU_ISR_install_vector
|
||||
*
|
||||
* This kernel routine installs the RTEMS handler for the
|
||||
* specified vector.
|
||||
*
|
||||
* Input parameters:
|
||||
* vector - interrupt vector number
|
||||
* old_handler - former ISR for this vector number
|
||||
* new_handler - replacement ISR for this vector number
|
||||
*
|
||||
* Output parameters: NONE
|
||||
*
|
||||
*
|
||||
* C4x Specific Information:
|
||||
*
|
||||
*/
|
||||
|
||||
void _CPU_ISR_install_vector(
|
||||
uint32_t vector,
|
||||
proc_ptr new_handler,
|
||||
proc_ptr *old_handler
|
||||
)
|
||||
{
|
||||
proc_ptr ignored;
|
||||
extern void rtems_irq_prologue_0(void);
|
||||
extern void rtems_irq_prologue_1(void);
|
||||
void *entry;
|
||||
|
||||
*old_handler = _ISR_Vector_table[ vector ];
|
||||
|
||||
/*
|
||||
* If the interrupt vector table is a table of pointer to isr entry
|
||||
* points, then we need to install the appropriate RTEMS interrupt
|
||||
* handler for this vector number.
|
||||
*/
|
||||
|
||||
entry = (void *)rtems_irq_prologue_0 +
|
||||
((rtems_irq_prologue_1 - rtems_irq_prologue_0) * vector);
|
||||
_CPU_ISR_install_raw_handler( vector, entry, &ignored );
|
||||
|
||||
/*
|
||||
* We put the actual user ISR address in '_ISR_vector_table'. This will
|
||||
* be used by the _ISR_Handler so the user gets control.
|
||||
*/
|
||||
|
||||
_ISR_Vector_table[ vector ] = new_handler;
|
||||
}
|
||||
|
||||
/*PAGE
|
||||
*
|
||||
* _CPU_Thread_Idle_body
|
||||
*
|
||||
* NOTES:
|
||||
*
|
||||
* 1. This is the same as the regular CPU independent algorithm.
|
||||
*
|
||||
* 2. If you implement this using a "halt", "idle", or "shutdown"
|
||||
* instruction, then don't forget to put it in an infinite loop.
|
||||
*
|
||||
* 3. Be warned. Some processors with onboard DMA have been known
|
||||
* to stop the DMA if the CPU were put in IDLE mode. This might
|
||||
* also be a problem with other on-chip peripherals. So use this
|
||||
* hook with caution.
|
||||
*
|
||||
* C4x Specific Information:
|
||||
*
|
||||
*
|
||||
*/
|
||||
|
||||
#if (CPU_PROVIDES_IDLE_THREAD_BODY == 1)
|
||||
void *_CPU_Thread_Idle_body( uintptr_t ignored )
|
||||
{
|
||||
|
||||
for( ; ; ) {
|
||||
__asm__( "idle" );
|
||||
__asm__( "nop" );
|
||||
__asm__( "nop" );
|
||||
__asm__( "nop" );
|
||||
/* insert your "halt" instruction here */ ;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
@@ -1,773 +0,0 @@
|
||||
/* cpu_asm.c ===> cpu_asm.S or cpu_asm.s
|
||||
*
|
||||
* This file contains the basic algorithms for all assembly code used
|
||||
* in an specific CPU port of RTEMS. These algorithms must be implemented
|
||||
* in assembly language
|
||||
*
|
||||
* NOTE: This is supposed to be a .S or .s file NOT a C file.
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1999.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.com/license/LICENSE.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifdef HAVE_CONFIG_H
|
||||
#include "config.h"
|
||||
#endif
|
||||
|
||||
#include <rtems/asm.h>
|
||||
|
||||
/*
|
||||
* _CPU_Context_save_fp_context
|
||||
*
|
||||
* This routine is responsible for saving the FP context
|
||||
* at *fp_context_ptr. If the point to load the FP context
|
||||
* from is changed then the pointer is modified by this routine.
|
||||
*
|
||||
* Sometimes a macro implementation of this is in cpu.h which dereferences
|
||||
* the ** and a similarly named routine in this file is passed something
|
||||
* like a (Context_Control_fp *). The general rule on making this decision
|
||||
* is to avoid writing assembly language.
|
||||
*
|
||||
* void _CPU_Context_save_fp(
|
||||
* void **fp_context_ptr
|
||||
*
|
||||
* C4x Specific Information:
|
||||
*
|
||||
* There is no distiniction between FP and integer context in this port.
|
||||
*/
|
||||
|
||||
/*
|
||||
* _CPU_Context_restore_fp_context
|
||||
*
|
||||
* This routine is responsible for restoring the FP context
|
||||
* at *fp_context_ptr. If the point to load the FP context
|
||||
* from is changed then the pointer is modified by this routine.
|
||||
*
|
||||
* Sometimes a macro implementation of this is in cpu.h which dereferences
|
||||
* the ** and a similarly named routine in this file is passed something
|
||||
* like a (Context_Control_fp *). The general rule on making this decision
|
||||
* is to avoid writing assembly language.
|
||||
*
|
||||
* void _CPU_Context_restore_fp(
|
||||
* void **fp_context_ptr
|
||||
* )
|
||||
*
|
||||
* C4x Specific Information:
|
||||
*
|
||||
* There is no distiniction between FP and integer context in this port.
|
||||
*/
|
||||
|
||||
|
||||
/* _CPU_Context_switch
|
||||
*
|
||||
* This routine performs a normal non-FP context switch.
|
||||
*
|
||||
* void _CPU_Context_switch(
|
||||
* Context_Control *run,
|
||||
* Context_Control *heir
|
||||
* )
|
||||
*
|
||||
* TMS320C3x General-Purpose Applications User's Guide, section 2.4
|
||||
* (p 2-11 and following), Context Switching in Interrupts and
|
||||
* Subroutines states that "If the program is in a subroutine, it
|
||||
* must preserve the dedicated C registers as follows:"
|
||||
*
|
||||
* Save as Integers Save as Floating-Point
|
||||
* ================ ======================
|
||||
* R4 R8 R6 R7
|
||||
* AR4 AR5
|
||||
* AR6 AR7
|
||||
* FP DP (small model only)
|
||||
* SP
|
||||
*/
|
||||
|
||||
.global SYM(_CPU_Context_switch)
|
||||
SYM(_CPU_Context_switch):
|
||||
.if .REGPARM == 0
|
||||
ldi sp, ar0
|
||||
ldi *ar0, ar2 ; get the location of running context
|
||||
.endif
|
||||
sti st,*ar2++ ; store status word
|
||||
sti ar3,*ar2++ ; store ar3
|
||||
sti ar4,*ar2++ ; store ar4
|
||||
sti ar5,*ar2++ ; store ar5
|
||||
sti ar6,*ar2++ ; store ar6
|
||||
sti ar7,*ar2++ ; store ar7
|
||||
sti r4,*ar2++ ; store integer portion of r4
|
||||
sti r5,*ar2++ ; store integer portion of r5
|
||||
stf r6,*ar2++ ; store float portion of r6
|
||||
stf r7,*ar2++ ; store float portion of r7
|
||||
.if .TMS320C40
|
||||
sti r8,*ar2++ ; store integer portion of r8
|
||||
.endif
|
||||
sti sp,*ar2++ ; store sp
|
||||
|
||||
; end of save
|
||||
|
||||
.if .REGPARM == 0
|
||||
ldi *-ar0(2), ar2 ; get the location of heir context
|
||||
.else
|
||||
ldi r2,ar2
|
||||
.endif
|
||||
_local_restore:
|
||||
ldi *ar2++,ar0 ; load status word into register
|
||||
ldi *ar2++,ar3 ; load ar3
|
||||
ldi *ar2++,ar4 ; load ar4
|
||||
ldi *ar2++,ar5 ; load ar5
|
||||
ldi *ar2++,ar6 ; load ar6
|
||||
ldi *ar2++,ar7 ; load ar7
|
||||
ldi *ar2++,r4 ; load integer portion of r4
|
||||
ldi *ar2++,r5 ; load integer portion of r5
|
||||
ldf *ar2++,r6 ; load float portion of r6
|
||||
ldf *ar2++,r7 ; load float portion of r7
|
||||
.if .TMS320C40
|
||||
ldi *ar2++,r8 ; load integer portion of r8
|
||||
.endif
|
||||
ldi *ar2++,sp ; load sp
|
||||
ldi ar0,st ; restore status word and interrupts
|
||||
rets
|
||||
|
||||
/*
|
||||
* _CPU_Context_restore
|
||||
*
|
||||
* This routine is generally used only to restart self in an
|
||||
* efficient manner. It may simply be a label in _CPU_Context_switch.
|
||||
*
|
||||
* NOTE: May be unnecessary to reload some registers.
|
||||
*
|
||||
* void _CPU_Context_restore(
|
||||
* Context_Control *new_context
|
||||
* )
|
||||
*/
|
||||
|
||||
.global SYM(_CPU_Context_restore)
|
||||
SYM(_CPU_Context_restore):
|
||||
.if .REGPARM == 0
|
||||
ldi sp, ar0
|
||||
ldi *ar0, ar2 ; get the location of context to restore
|
||||
.endif
|
||||
br _local_restore
|
||||
|
||||
/* void _ISR_Handler()
|
||||
*
|
||||
* This routine provides the RTEMS interrupt management.
|
||||
*
|
||||
* void _ISR_Handler()
|
||||
*/
|
||||
|
||||
/*
|
||||
* At entry to "common" _ISR_Handler, the vector number must be
|
||||
* available. On some CPUs the hardware puts either the vector
|
||||
* number or the offset into the vector table for this ISR in a
|
||||
* known place. If the hardware does not give us this information,
|
||||
* then the assembly portion of RTEMS for this port will contain
|
||||
* a set of distinct interrupt entry points which somehow place
|
||||
* the vector number in a known place (which is safe if another
|
||||
* interrupt nests this one) and branches to _ISR_Handler.
|
||||
*/
|
||||
|
||||
/*
|
||||
* save some or all context on stack
|
||||
* may need to save some special interrupt information for exit
|
||||
*
|
||||
* #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
|
||||
* if ( _ISR_Nest_level == 0 )
|
||||
* switch to software interrupt stack
|
||||
* #endif
|
||||
*
|
||||
* _ISR_Nest_level++;
|
||||
*
|
||||
* _Thread_Dispatch_disable_level++;
|
||||
*
|
||||
* (*_ISR_Vector_table[ vector ])( vector );
|
||||
*
|
||||
* --_ISR_Nest_level;
|
||||
*
|
||||
* if ( _ISR_Nest_level )
|
||||
* goto the label "exit interrupt (simple case)"
|
||||
*
|
||||
* #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
|
||||
* restore stack
|
||||
* #endif
|
||||
*
|
||||
* if ( !_Context_Switch_necessary )
|
||||
* goto the label "exit interrupt (simple case)"
|
||||
*
|
||||
* if ( !_ISR_Signals_to_thread_executing )
|
||||
* _ISR_Signals_to_thread_executing = FALSE;
|
||||
* goto the label "exit interrupt (simple case)"
|
||||
*
|
||||
* call _Thread_Dispatch() or prepare to return to _ISR_Dispatch
|
||||
*
|
||||
* prepare to get out of interrupt
|
||||
* return from interrupt (maybe to _ISR_Dispatch)
|
||||
*
|
||||
* LABEL "exit interrupt (simple case):
|
||||
* prepare to get out of interrupt
|
||||
* return from interrupt
|
||||
*/
|
||||
|
||||
.global SYM(_ISR_Handler_save_registers)
|
||||
SYM(_ISR_Handler_save_registers):
|
||||
; no push st because it is already pushed
|
||||
; no push ar2 because it is already pushed and vector number loaded
|
||||
push ar0
|
||||
push ar1
|
||||
push dp
|
||||
push ir0
|
||||
push ir1
|
||||
push rs
|
||||
push re
|
||||
push rc
|
||||
push bk
|
||||
|
||||
push r0
|
||||
pushf r0
|
||||
push r1
|
||||
pushf r1
|
||||
push r2
|
||||
pushf r2
|
||||
push r3
|
||||
pushf r3
|
||||
; no push r4 because other part of register is in basic context
|
||||
push r4
|
||||
pushf r4
|
||||
; no push r5 because other part of register is in basic context
|
||||
push r5
|
||||
pushf r5
|
||||
push r6
|
||||
pushf r6
|
||||
; no pushf r6 because other part of register is in basic context
|
||||
push r7
|
||||
pushf r7
|
||||
; no pushf r7 because other part of register is in basic context
|
||||
.if .TMS320C40
|
||||
push r8
|
||||
; no pushf r8 because other part of register is in basic context
|
||||
push r9
|
||||
pushf r9
|
||||
push r10
|
||||
pushf r10
|
||||
push r11
|
||||
pushf r11
|
||||
.endif
|
||||
|
||||
ldi sp,r2
|
||||
call SYM(__ISR_Handler)
|
||||
|
||||
.if .TMS320C40
|
||||
popf r11
|
||||
pop r11
|
||||
popf r10
|
||||
pop r10
|
||||
popf r9
|
||||
pop r9
|
||||
; no popf r8 because other part of register is in basic context
|
||||
pop r8
|
||||
.endif
|
||||
; no popf r7 because other part of register is in basic context
|
||||
popf r7
|
||||
pop r7
|
||||
; no popf r6 because other part of register is in basic context
|
||||
popf r6
|
||||
pop r6
|
||||
; no popf r5 because other part of register is in basic context
|
||||
popf r5
|
||||
pop r5
|
||||
; no pop r4 because other part of register is in basic context
|
||||
popf r4
|
||||
pop r4
|
||||
popf r3
|
||||
pop r3
|
||||
popf r2
|
||||
pop r2
|
||||
popf r1
|
||||
pop r1
|
||||
popf r0
|
||||
pop r0
|
||||
|
||||
pop bk
|
||||
pop rc
|
||||
pop re
|
||||
pop rs
|
||||
pop ir1
|
||||
pop ir0
|
||||
pop dp
|
||||
pop ar1
|
||||
pop ar0
|
||||
pop ar2 ; because the vector numbers goes here
|
||||
pop st
|
||||
reti
|
||||
|
||||
/*
|
||||
* Prologues so we can know the vector number. Generated by this script:
|
||||
*
|
||||
* i=0
|
||||
* while test $i -lt 64
|
||||
* do
|
||||
*
|
||||
* printf "\t.global\tSYM(rtems_irq_prologue_%X)\n" $i
|
||||
* printf "SYM(rtems_irq_prologue_%X):\n" $i
|
||||
* printf "\tpush\tst\n"
|
||||
* printf "\tpush\tar2\n"
|
||||
* printf "\tldi\t0x%x,ar2\n" $i
|
||||
* printf "\tbr\tSYM(_ISR_Handler_save_registers)\n"
|
||||
* printf "\n"
|
||||
* i=`expr $i + 1`
|
||||
*
|
||||
* done
|
||||
*/
|
||||
|
||||
.global SYM(rtems_irq_prologue_0)
|
||||
SYM(rtems_irq_prologue_0):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x0,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_1)
|
||||
SYM(rtems_irq_prologue_1):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x1,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_2)
|
||||
SYM(rtems_irq_prologue_2):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x2,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_3)
|
||||
SYM(rtems_irq_prologue_3):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x3,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_4)
|
||||
SYM(rtems_irq_prologue_4):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x4,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_5)
|
||||
SYM(rtems_irq_prologue_5):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x5,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_6)
|
||||
SYM(rtems_irq_prologue_6):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x6,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_7)
|
||||
SYM(rtems_irq_prologue_7):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x7,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_8)
|
||||
SYM(rtems_irq_prologue_8):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x8,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_9)
|
||||
SYM(rtems_irq_prologue_9):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x9,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_A)
|
||||
SYM(rtems_irq_prologue_A):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0xa,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_B)
|
||||
SYM(rtems_irq_prologue_B):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0xb,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_C)
|
||||
SYM(rtems_irq_prologue_C):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0xc,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_D)
|
||||
SYM(rtems_irq_prologue_D):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0xd,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_E)
|
||||
SYM(rtems_irq_prologue_E):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0xe,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_F)
|
||||
SYM(rtems_irq_prologue_F):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0xf,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_10)
|
||||
SYM(rtems_irq_prologue_10):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x10,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_11)
|
||||
SYM(rtems_irq_prologue_11):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x11,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_12)
|
||||
SYM(rtems_irq_prologue_12):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x12,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_13)
|
||||
SYM(rtems_irq_prologue_13):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x13,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_14)
|
||||
SYM(rtems_irq_prologue_14):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x14,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_15)
|
||||
SYM(rtems_irq_prologue_15):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x15,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_16)
|
||||
SYM(rtems_irq_prologue_16):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x16,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_17)
|
||||
SYM(rtems_irq_prologue_17):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x17,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_18)
|
||||
SYM(rtems_irq_prologue_18):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x18,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_19)
|
||||
SYM(rtems_irq_prologue_19):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x19,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_1A)
|
||||
SYM(rtems_irq_prologue_1A):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x1a,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_1B)
|
||||
SYM(rtems_irq_prologue_1B):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x1b,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_1C)
|
||||
SYM(rtems_irq_prologue_1C):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x1c,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_1D)
|
||||
SYM(rtems_irq_prologue_1D):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x1d,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_1E)
|
||||
SYM(rtems_irq_prologue_1E):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x1e,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_1F)
|
||||
SYM(rtems_irq_prologue_1F):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x1f,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_20)
|
||||
SYM(rtems_irq_prologue_20):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x20,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_21)
|
||||
SYM(rtems_irq_prologue_21):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x21,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_22)
|
||||
SYM(rtems_irq_prologue_22):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x22,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_23)
|
||||
SYM(rtems_irq_prologue_23):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x23,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_24)
|
||||
SYM(rtems_irq_prologue_24):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x24,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_25)
|
||||
SYM(rtems_irq_prologue_25):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x25,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_26)
|
||||
SYM(rtems_irq_prologue_26):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x26,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_27)
|
||||
SYM(rtems_irq_prologue_27):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x27,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_28)
|
||||
SYM(rtems_irq_prologue_28):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x28,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_29)
|
||||
SYM(rtems_irq_prologue_29):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x29,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_2A)
|
||||
SYM(rtems_irq_prologue_2A):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x2a,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_2B)
|
||||
SYM(rtems_irq_prologue_2B):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x2b,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_2C)
|
||||
SYM(rtems_irq_prologue_2C):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x2c,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_2D)
|
||||
SYM(rtems_irq_prologue_2D):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x2d,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_2E)
|
||||
SYM(rtems_irq_prologue_2E):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x2e,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_2F)
|
||||
SYM(rtems_irq_prologue_2F):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x2f,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_30)
|
||||
SYM(rtems_irq_prologue_30):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x30,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_31)
|
||||
SYM(rtems_irq_prologue_31):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x31,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_32)
|
||||
SYM(rtems_irq_prologue_32):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x32,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_33)
|
||||
SYM(rtems_irq_prologue_33):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x33,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_34)
|
||||
SYM(rtems_irq_prologue_34):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x34,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_35)
|
||||
SYM(rtems_irq_prologue_35):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x35,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_36)
|
||||
SYM(rtems_irq_prologue_36):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x36,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_37)
|
||||
SYM(rtems_irq_prologue_37):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x37,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_38)
|
||||
SYM(rtems_irq_prologue_38):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x38,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_39)
|
||||
SYM(rtems_irq_prologue_39):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x39,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_3A)
|
||||
SYM(rtems_irq_prologue_3A):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x3a,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_3B)
|
||||
SYM(rtems_irq_prologue_3B):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x3b,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_3C)
|
||||
SYM(rtems_irq_prologue_3C):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x3c,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_3D)
|
||||
SYM(rtems_irq_prologue_3D):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x3d,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_3E)
|
||||
SYM(rtems_irq_prologue_3E):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x3e,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
|
||||
.global SYM(rtems_irq_prologue_3F)
|
||||
SYM(rtems_irq_prologue_3F):
|
||||
push st
|
||||
push ar2
|
||||
ldi 0x3f,ar2
|
||||
br SYM(_ISR_Handler_save_registers)
|
||||
@@ -1,93 +0,0 @@
|
||||
/*
|
||||
* C4x CPU Dependent Source
|
||||
*
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1999.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.com/license/LICENSE.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifdef HAVE_CONFIG_H
|
||||
#include "config.h"
|
||||
#endif
|
||||
|
||||
#include <rtems/system.h>
|
||||
#include <rtems/score/cpu.h>
|
||||
#include <rtems/score/isr.h>
|
||||
#include <rtems/score/thread.h>
|
||||
|
||||
/*
|
||||
* This routine provides the RTEMS interrupt management.
|
||||
*/
|
||||
|
||||
#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
|
||||
unsigned long *_old_stack_ptr;
|
||||
#endif
|
||||
|
||||
register unsigned long *stack_ptr asm("sp");
|
||||
|
||||
void __ISR_Handler(uint32_t vector, void *isr_sp)
|
||||
{
|
||||
register uint32_t level;
|
||||
|
||||
/* already disabled when we get here */
|
||||
/* _CPU_ISR_Disable( level ); */
|
||||
|
||||
_Thread_Dispatch_disable_level++;
|
||||
|
||||
#if 0
|
||||
if ( stack_ptr > (_Thread_Executing->Start.stack +
|
||||
_Thread_Executing->Start.Initial_stack.size) ) {
|
||||
printk( "Blown interrupt stack at 0x%x\n", stack_ptr );
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
|
||||
if ( _ISR_Nest_level == 0 ) {
|
||||
/* Install irq stack */
|
||||
_old_stack_ptr = stack_ptr;
|
||||
stack_ptr = _CPU_Interrupt_stack_low;
|
||||
}
|
||||
#endif
|
||||
|
||||
_ISR_Nest_level++;
|
||||
|
||||
/* leave it to the ISR to decide if they get reenabled */
|
||||
/* _CPU_ISR_Enable( level ); */
|
||||
|
||||
/* call isp */
|
||||
if ( _ISR_Vector_table[ vector] )
|
||||
(*_ISR_Vector_table[ vector ])(
|
||||
vector, isr_sp - sizeof(CPU_Interrupt_frame) + 1 );
|
||||
|
||||
_CPU_ISR_Disable( level );
|
||||
|
||||
_ISR_Nest_level--;
|
||||
|
||||
#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
|
||||
if ( _ISR_Nest_level == 0 ) /* restore old stack pointer */
|
||||
stack_ptr = _old_stack_ptr;
|
||||
#endif
|
||||
|
||||
_Thread_Dispatch_disable_level--;
|
||||
|
||||
_CPU_ISR_Enable( level );
|
||||
|
||||
if ( _ISR_Nest_level )
|
||||
return;
|
||||
|
||||
if ( _Thread_Dispatch_disable_level ) {
|
||||
_ISR_Signals_to_thread_executing = FALSE;
|
||||
return;
|
||||
}
|
||||
|
||||
if ( _Context_Switch_necessary || _ISR_Signals_to_thread_executing ) {
|
||||
_ISR_Signals_to_thread_executing = FALSE;
|
||||
_Thread_Dispatch();
|
||||
}
|
||||
}
|
||||
@@ -1,54 +0,0 @@
|
||||
## Automatically generated by ampolish3 - Do not edit
|
||||
|
||||
if AMPOLISH3
|
||||
$(srcdir)/preinstall.am: Makefile.am
|
||||
$(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am
|
||||
endif
|
||||
|
||||
PREINSTALL_DIRS =
|
||||
DISTCLEANFILES = $(PREINSTALL_DIRS)
|
||||
|
||||
all-am: $(PREINSTALL_FILES)
|
||||
|
||||
PREINSTALL_FILES =
|
||||
CLEANFILES = $(PREINSTALL_FILES)
|
||||
|
||||
$(PROJECT_INCLUDE)/rtems/$(dirstamp):
|
||||
@$(MKDIR_P) $(PROJECT_INCLUDE)/rtems
|
||||
@: > $(PROJECT_INCLUDE)/rtems/$(dirstamp)
|
||||
PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/$(dirstamp)
|
||||
|
||||
$(PROJECT_INCLUDE)/rtems/asm.h: rtems/asm.h $(PROJECT_INCLUDE)/rtems/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/asm.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/asm.h
|
||||
|
||||
$(PROJECT_INCLUDE)/rtems/tic4x/$(dirstamp):
|
||||
@$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/tic4x
|
||||
@: > $(PROJECT_INCLUDE)/rtems/tic4x/$(dirstamp)
|
||||
PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/tic4x/$(dirstamp)
|
||||
|
||||
$(PROJECT_INCLUDE)/rtems/tic4x/c4xio.h: rtems/tic4x/c4xio.h $(PROJECT_INCLUDE)/rtems/tic4x/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/tic4x/c4xio.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/tic4x/c4xio.h
|
||||
|
||||
$(PROJECT_INCLUDE)/rtems/score/$(dirstamp):
|
||||
@$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/score
|
||||
@: > $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
|
||||
PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
|
||||
|
||||
$(PROJECT_INCLUDE)/rtems/score/cpu.h: rtems/score/cpu.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu.h
|
||||
|
||||
$(PROJECT_INCLUDE)/rtems/score/c4x.h: rtems/score/c4x.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/c4x.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/c4x.h
|
||||
|
||||
$(PROJECT_INCLUDE)/rtems/score/types.h: rtems/score/types.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/types.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/types.h
|
||||
|
||||
$(PROJECT_INCLUDE)/rtems/score/cpu_asm.h: rtems/score/cpu_asm.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h
|
||||
|
||||
@@ -1,97 +0,0 @@
|
||||
/**
|
||||
* @file rtems/asm.h
|
||||
*
|
||||
* This include file attempts to address the problems
|
||||
* caused by incompatible flavors of assemblers and
|
||||
* toolsets. It primarily addresses variations in the
|
||||
* use of leading underscores on symbols and the requirement
|
||||
* that register names be preceded by a %.
|
||||
*/
|
||||
|
||||
/*
|
||||
* NOTE: The spacing in the use of these macros
|
||||
* is critical to them working as advertised.
|
||||
*
|
||||
* COPYRIGHT:
|
||||
*
|
||||
* This file is based on similar code found in newlib available
|
||||
* from ftp.cygnus.com. The file which was used had no copyright
|
||||
* notice. This file is freely distributable as long as the source
|
||||
* of the file is noted. This file is:
|
||||
*
|
||||
* COPYRIGHT (c) 1994-1997.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _RTEMS_ASM_H
|
||||
#define _RTEMS_ASM_H
|
||||
|
||||
/*
|
||||
* Indicate we are in an assembly file and get the basic CPU definitions.
|
||||
*/
|
||||
|
||||
#ifndef ASM
|
||||
#define ASM
|
||||
#endif
|
||||
#include <rtems/score/cpuopts.h>
|
||||
#include <rtems/score/c4x.h>
|
||||
|
||||
/*
|
||||
* Recent versions of GNU cpp define variables which indicate the
|
||||
* need for underscores and percents. If not using GNU cpp or
|
||||
* the version does not support this, then you will obviously
|
||||
* have to define these as appropriate.
|
||||
*/
|
||||
|
||||
#ifndef __USER_LABEL_PREFIX__
|
||||
#define __USER_LABEL_PREFIX__ _
|
||||
#endif
|
||||
|
||||
#ifndef __REGISTER_PREFIX__
|
||||
#define __REGISTER_PREFIX__
|
||||
#endif
|
||||
|
||||
#include <rtems/concat.h>
|
||||
|
||||
/* Use the right prefix for global labels. */
|
||||
|
||||
#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
|
||||
|
||||
/* Use the right prefix for registers. */
|
||||
|
||||
#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)
|
||||
|
||||
/*
|
||||
* define macros for all of the registers on this CPU
|
||||
*
|
||||
* EXAMPLE: #define d0 REG (d0)
|
||||
*/
|
||||
|
||||
/*
|
||||
* Define macros to handle section beginning and ends.
|
||||
*/
|
||||
|
||||
|
||||
#define BEGIN_CODE_DCL .text
|
||||
#define END_CODE_DCL
|
||||
#define BEGIN_DATA_DCL .data
|
||||
#define END_DATA_DCL
|
||||
#define BEGIN_CODE .text
|
||||
#define END_CODE
|
||||
#define BEGIN_DATA
|
||||
#define END_DATA
|
||||
#define BEGIN_BSS
|
||||
#define END_BSS
|
||||
#define END
|
||||
|
||||
/*
|
||||
* Following must be tailor for a particular flavor of the C compiler.
|
||||
* They may need to put underscores in front of the symbols.
|
||||
*/
|
||||
|
||||
#define PUBLIC(sym) .globl SYM (sym)
|
||||
#define EXTERN(sym) .globl SYM (sym)
|
||||
|
||||
#endif
|
||||
@@ -1,367 +0,0 @@
|
||||
/**
|
||||
* @file rtems/score/c4x.h
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file is an example (i.e. "no CPU") of the file which is
|
||||
* created for each CPU family port of RTEMS.
|
||||
*
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1999.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.com/license/LICENSE.
|
||||
*
|
||||
* $Id$
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _RTEMS_SCORE_C4X_H
|
||||
#define _RTEMS_SCORE_C4X_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* This file contains the information required to build
|
||||
* RTEMS for a particular member of the "no cpu"
|
||||
* family when executing in protected mode. It does
|
||||
* this by setting variables to indicate which implementation
|
||||
* dependent features are present in a particular member
|
||||
* of the family.
|
||||
*/
|
||||
|
||||
#if defined(_C30)
|
||||
#define CPU_MODEL_NAME "C30"
|
||||
|
||||
#elif defined(_C31)
|
||||
#define CPU_MODEL_NAME "C31"
|
||||
|
||||
#elif defined(_C32)
|
||||
#define CPU_MODEL_NAME "C32"
|
||||
|
||||
#elif defined(_C33)
|
||||
#define CPU_MODEL_NAME "C33"
|
||||
|
||||
#elif defined(_C40)
|
||||
#define CPU_MODEL_NAME "C40"
|
||||
|
||||
#elif defined(_C44)
|
||||
#define CPU_MODEL_NAME "C44"
|
||||
|
||||
#else
|
||||
|
||||
#error "Unsupported CPU Model"
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Define the name of the CPU family.
|
||||
*/
|
||||
|
||||
#define CPU_NAME "Texas Instruments C3x/C4x"
|
||||
|
||||
/*
|
||||
* This port is a little unusual in that even though there are "floating
|
||||
* point registers", the notion of floating point is very inherent to
|
||||
* applications. In addition, the calling conventions require that
|
||||
* only a few extended registers be preserved across subroutine calls.
|
||||
* The overhead of including these few registers in the basic
|
||||
* context is small compared to the overhead of managing the notion
|
||||
* of separate floating point contexts. So we decided to pretend that
|
||||
* there is no FPU on the C3x or C4x.
|
||||
*/
|
||||
|
||||
#define C4X_HAS_FPU 0
|
||||
|
||||
/*
|
||||
* Routines to manipulate the bits in the Status Word (ST).
|
||||
*/
|
||||
|
||||
#define C4X_ST_C 0x0001
|
||||
#define C4X_ST_V 0x0002
|
||||
#define C4X_ST_Z 0x0004
|
||||
#define C4X_ST_N 0x0008
|
||||
#define C4X_ST_UF 0x0010
|
||||
#define C4X_ST_LV 0x0020
|
||||
#define C4X_ST_LUF 0x0040
|
||||
#define C4X_ST_OVM 0x0080
|
||||
#define C4X_ST_RM 0x0100
|
||||
#define C4X_ST_CF 0x0400
|
||||
#define C4X_ST_CE 0x0800
|
||||
#define C4X_ST_CC 0x1000
|
||||
#define C4X_ST_GIE 0x2000
|
||||
|
||||
#ifndef _TMS320C40
|
||||
#define C3X_IE_INTERRUPT_MASK_BITS 0xffff
|
||||
#define C3x_IE_INTERRUPTS_ALL_ENABLED 0x0000
|
||||
#define C3x_IE_INTERRUPTS_ALL_DISABLED 0xffff
|
||||
#endif
|
||||
|
||||
#ifndef ASM
|
||||
|
||||
/*
|
||||
* A nop macro.
|
||||
*/
|
||||
|
||||
#define c4x_nop() \
|
||||
__asm__("nop");
|
||||
|
||||
/*
|
||||
* Routines to set and clear individual bits in the ST (status word).
|
||||
*
|
||||
* cpu_st_bit_clear - clear bit in ST
|
||||
* cpu_st_bit_set - set bit in ST
|
||||
* cpu_st_get - obtain entire ST
|
||||
*/
|
||||
|
||||
#ifdef _TMS320C40
|
||||
#define c4x_gie_nop()
|
||||
#else
|
||||
#define c4x_gie_nop() { c4x_nop(); c4x_nop(); }
|
||||
#endif
|
||||
|
||||
#define cpu_st_bit_clear(_st_bit) \
|
||||
do { \
|
||||
__asm__("andn %0,st" : : "g" (_st_bit) : "cc"); \
|
||||
c4x_gie_nop(); \
|
||||
} while (0)
|
||||
|
||||
#define cpu_st_bit_set(_st_bit) \
|
||||
do { \
|
||||
__asm__("or %0,st" : : "g" (_st_bit) : "cc"); \
|
||||
c4x_gie_nop(); \
|
||||
} while (0)
|
||||
|
||||
static inline unsigned int cpu_st_get(void)
|
||||
{
|
||||
register unsigned int st_value;
|
||||
__asm__("ldi st, %0" : "=r" (st_value));
|
||||
return st_value;
|
||||
}
|
||||
|
||||
/*
|
||||
* Routines to manipulate the Global Interrupt Enable (GIE) bit in
|
||||
* the Status Word (ST).
|
||||
*
|
||||
* c4x_global_interrupts_get - returns current GIE setting
|
||||
* c4x_global_interrupts_disable - disables global interrupts
|
||||
* c4x_global_interrupts_enable - enables global interrupts
|
||||
* c4x_global_interrupts_restore - restores GIE to pre-disable state
|
||||
* c4x_global_interrupts_flash - temporarily enable global interrupts
|
||||
*/
|
||||
|
||||
#define c4x_global_interrupts_get() \
|
||||
(cpu_st_get() & C4X_ST_GIE)
|
||||
|
||||
#define c4x_global_interrupts_disable() \
|
||||
cpu_st_bit_clear(C4X_ST_GIE)
|
||||
|
||||
#define c4x_global_interrupts_enable() \
|
||||
cpu_st_bit_set(C4X_ST_GIE)
|
||||
|
||||
#define c4x_global_interrupts_restore(_old_level) \
|
||||
cpu_st_bit_set(_old_level)
|
||||
|
||||
#define c4x_global_interrupts_flash(_old_level) \
|
||||
do { \
|
||||
cpu_st_bit_set(_old_level); \
|
||||
cpu_st_bit_clear(C4X_ST_GIE); \
|
||||
} while (0)
|
||||
|
||||
#ifndef _TMS320C40
|
||||
|
||||
/*
|
||||
* Routines to set and get the IF register
|
||||
*
|
||||
* c3x_get_if - obtains IF register
|
||||
* c3x_set_if - sets IF register
|
||||
*/
|
||||
|
||||
static inline unsigned int c3x_get_if(void)
|
||||
{
|
||||
register unsigned int _if_value;
|
||||
|
||||
__asm__( "ldi if, %0" : "=r" (_if_value) );
|
||||
return _if_value;
|
||||
}
|
||||
|
||||
static inline void c3x_set_if(unsigned int _if_value)
|
||||
{
|
||||
__asm__( "ldi %0, if" : : "g" (_if_value) : "if", "cc");
|
||||
}
|
||||
|
||||
/*
|
||||
* Routines to set and get the IE register
|
||||
*
|
||||
* c3x_get_ie - obtains IE register
|
||||
* c3x_set_ie - sets IE register
|
||||
*/
|
||||
|
||||
static inline unsigned int c3x_get_ie(void)
|
||||
{
|
||||
register unsigned int _ie_value;
|
||||
|
||||
__asm__ volatile ( "ldi ie, %0" : "=r" (_ie_value) );
|
||||
return _ie_value;
|
||||
}
|
||||
|
||||
static inline void c3x_set_ie(unsigned int _ie_value)
|
||||
{
|
||||
__asm__ volatile ( "ldi %0, ie" : : "g" (_ie_value) : "ie", "cc");
|
||||
}
|
||||
|
||||
/*
|
||||
* Routines to manipulates the mask portion of the IE register.
|
||||
*
|
||||
* c3x_ie_mask_all - returns previous IE mask
|
||||
* c3x_ie_mask_restore - restores previous IE mask
|
||||
* c3x_ie_mask_flash - temporarily restores previous IE mask
|
||||
* c3x_ie_mask_set - sets a specific set of the IE mask
|
||||
*/
|
||||
|
||||
#define c3x_ie_mask_all( _isr_cookie ) \
|
||||
do { \
|
||||
__asm__("ldi ie,%0\n" \
|
||||
"\tandn 0ffffh, ie" \
|
||||
: "=r" (_isr_cookie): : "ie", "cc" ); \
|
||||
} while (0)
|
||||
|
||||
#define c3x_ie_mask_restore( _isr_cookie ) \
|
||||
do { \
|
||||
__asm__("or %0, ie" \
|
||||
: : "g" (_isr_cookie) : "ie", "cc" ); \
|
||||
} while (0)
|
||||
|
||||
#define c3x_ie_mask_flash( _isr_cookie ) \
|
||||
do { \
|
||||
__asm__("or %0, ie\n" \
|
||||
"\tandn 0ffffh, ie" \
|
||||
: : "g" (_isr_cookie) : "ie", "cc" ); \
|
||||
} while (0)
|
||||
|
||||
#define c3x_ie_mask_set( _new_mask ) \
|
||||
do { unsigned int _ie_mask; \
|
||||
unsigned int _ie_value; \
|
||||
\
|
||||
if ( _new_mask == 0 ) _ie_mask = 0; \
|
||||
else _ie_mask = 0xffff; \
|
||||
_ie_value = c3x_get_ie(); \
|
||||
_ie_value &= C4X_IE_INTERRUPT_MASK_BITS; \
|
||||
_ie_value |= _ie_mask; \
|
||||
c3x_set_ie(_ie_value); \
|
||||
} while (0)
|
||||
#endif
|
||||
/* end of C3x specific interrupt flag routines */
|
||||
|
||||
/*
|
||||
* This is a section of C4x specific interrupt flag management routines.
|
||||
*/
|
||||
|
||||
#ifdef _TMS320C40
|
||||
|
||||
/*
|
||||
* Routines to set and get the IIF register
|
||||
*
|
||||
* c4x_get_iif - obtains IIF register
|
||||
* c4x_set_iif - sets IIF register
|
||||
*/
|
||||
|
||||
static inline unsigned int c4x_get_iif(void)
|
||||
{
|
||||
register unsigned int _iif_value;
|
||||
|
||||
__asm__( "ldi iif, %0" : "=r" (_iif_value) );
|
||||
return _iif_value;
|
||||
}
|
||||
|
||||
static inline void c4x_set_iif(unsigned int _iif_value)
|
||||
{
|
||||
__asm__( "ldi %0, iif" : : "g" (_iif_value) : "iif", "cc");
|
||||
}
|
||||
|
||||
/*
|
||||
* Routines to set and get the IIE register
|
||||
*
|
||||
* c4x_get_iie - obtains IIE register
|
||||
* c4x_set_iie - sets IIE register
|
||||
*/
|
||||
|
||||
static inline unsigned int c4x_get_iie(void)
|
||||
{
|
||||
register unsigned int _iie_value;
|
||||
|
||||
__asm__( "ldi iie, %0" : "=r" (_iie_value) );
|
||||
return _iie_value;
|
||||
}
|
||||
|
||||
static inline void c4x_set_iie(unsigned int _iie_value)
|
||||
{
|
||||
__asm__( "ldi %0, iie" : : "g" (_iie_value) : "iie", "cc");
|
||||
}
|
||||
|
||||
/*
|
||||
* Routines to manipulates the mask portion of the IIE register.
|
||||
*
|
||||
* c4x_ie_mask_all - returns previous IIE mask
|
||||
* c4x_ie_mask_restore - restores previous IIE mask
|
||||
* c4x_ie_mask_flash - temporarily restores previous IIE mask
|
||||
* c4x_ie_mask_set - sets a specific set of the IIE mask
|
||||
*/
|
||||
|
||||
#if 0
|
||||
#warning "C4x IIE masking routines not implemented."
|
||||
#define c4x_iie_mask_all( _isr_cookie )
|
||||
#define c4x_iie_mask_restore( _isr_cookie )
|
||||
#define c4x_iie_mask_flash( _isr_cookie )
|
||||
#define c4x_iie_mask_set( _new_mask )
|
||||
#endif
|
||||
|
||||
#endif
|
||||
/* end of C4x specific interrupt flag routines */
|
||||
|
||||
/*
|
||||
* Routines to access the Interrupt Trap Table Pointer
|
||||
*
|
||||
* c4x_get_ittp - get ITTP
|
||||
* c4x_set_ittp - set ITTP
|
||||
*/
|
||||
|
||||
static inline void * c4x_get_ittp(void)
|
||||
{
|
||||
register unsigned int _if_value;
|
||||
|
||||
__asm__( "ldi if, %0" : "=r" (_if_value) );
|
||||
return (void *)((_if_value & 0xffff0000) >> 8);
|
||||
}
|
||||
|
||||
static inline void c4x_set_ittp(void *_ittp_value)
|
||||
{
|
||||
unsigned int _if_value;
|
||||
unsigned int _ittp_field;
|
||||
|
||||
#ifdef _TMS320C40
|
||||
_if_value = c4x_get_iif();
|
||||
#else
|
||||
_if_value = c3x_get_if();
|
||||
#endif
|
||||
_if_value &= 0xffff;
|
||||
_ittp_field = (((unsigned int) _ittp_value) >> 8);
|
||||
_if_value |= _ittp_field << 16 ;
|
||||
#ifdef _TMS320C40
|
||||
c4x_set_iif( _if_value );
|
||||
#else
|
||||
c3x_set_if( _if_value );
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* ifndef ASM */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _RTEMS_SCORE_C4X_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,72 +0,0 @@
|
||||
/**
|
||||
* @file rtems/score/cpu_asm.h
|
||||
*/
|
||||
|
||||
/*
|
||||
* Very loose template for an include file for the cpu_asm.? file
|
||||
* if it is implemented as a ".S" file (preprocessed by cpp) instead
|
||||
* of a ".s" file (preprocessed by gm4 or gasp).
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1999.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.com/license/LICENSE.
|
||||
*
|
||||
* $Id$
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _RTEMS_SCORE_CPU_ASM_H
|
||||
#define _RTEMS_SCORE_CPU_ASM_H
|
||||
|
||||
/* pull in the generated offsets */
|
||||
|
||||
#include <rtems/score/offsets.h>
|
||||
|
||||
/*
|
||||
* Hardware General Registers
|
||||
*/
|
||||
|
||||
/* put something here */
|
||||
|
||||
/*
|
||||
* Hardware Floating Point Registers
|
||||
*/
|
||||
|
||||
/* put something here */
|
||||
|
||||
/*
|
||||
* Hardware Control Registers
|
||||
*/
|
||||
|
||||
/* put something here */
|
||||
|
||||
/*
|
||||
* Calling Convention
|
||||
*/
|
||||
|
||||
/* put something here */
|
||||
|
||||
/*
|
||||
* Temporary registers
|
||||
*/
|
||||
|
||||
/* put something here */
|
||||
|
||||
/*
|
||||
* Floating Point Registers - SW Conventions
|
||||
*/
|
||||
|
||||
/* put something here */
|
||||
|
||||
/*
|
||||
* Temporary floating point registers
|
||||
*/
|
||||
|
||||
/* put something here */
|
||||
|
||||
#endif
|
||||
|
||||
/* end of file */
|
||||
@@ -1,51 +0,0 @@
|
||||
/**
|
||||
* @file rtems/score/types.h
|
||||
*/
|
||||
|
||||
/*
|
||||
* This include file contains type definitions pertaining to the
|
||||
* Texas Instruments C4x processor family.
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1999.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.com/license/LICENSE.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _RTEMS_SCORE_TYPES_H
|
||||
#define _RTEMS_SCORE_TYPES_H
|
||||
|
||||
#ifndef ASM
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* This section defines the basic types for this processor.
|
||||
*/
|
||||
|
||||
typedef uint_least16_t Priority_Bit_map_control;
|
||||
typedef void c4x_isr;
|
||||
typedef void ( *c4x_isr_entry )( void );
|
||||
|
||||
#ifdef RTEMS_DEPRECATED_TYPES
|
||||
typedef bool boolean; /* Boolean value */
|
||||
typedef float single_precision; /* single precision float */
|
||||
typedef double double_precision; /* double precision float */
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* !ASM */
|
||||
|
||||
#endif
|
||||
@@ -1,117 +0,0 @@
|
||||
/*
|
||||
* C4X IO Information
|
||||
*
|
||||
* COPYRIGHT (c) 1989-2007.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.com/license/LICENSE.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _RTEMS_TIC4X_C4XIO_H
|
||||
#define _RTEMS_TIC4X_C4XIO_H
|
||||
|
||||
/*
|
||||
* Address defines
|
||||
*/
|
||||
|
||||
#ifdef _TMS320C40
|
||||
#define C4X_TIMER_0 ((struct c4x_timer*)0x100020)
|
||||
#else
|
||||
#define C4X_TIMER_0 ((struct c4x_timer*)0x808020)
|
||||
#define C4X_TIMER_1 ((struct c4x_timer*)0x808030)
|
||||
#endif
|
||||
|
||||
/* XXX how portable */
|
||||
|
||||
/* C32 Internal Control Registers */
|
||||
#define C4X_STRB0_REG 0x808064
|
||||
#define C4X_STRB1_REG 0x808068
|
||||
#define C4X_IOSTRB_REG 0x808060
|
||||
|
||||
/* C32 Internal RAM Locations */
|
||||
/* XXX how long */
|
||||
#define C4X_RAM_BLK_0 0x87fe00
|
||||
#define C4X_RAM_BLK_1 0x87ff00
|
||||
|
||||
/*
|
||||
* Data Structures to Overlay the Peripherals on the CPU
|
||||
*/
|
||||
|
||||
struct c4x_timer {
|
||||
volatile int tcontrol;
|
||||
volatile int r1[3];
|
||||
volatile int tcounter;
|
||||
volatile int r2[3];
|
||||
volatile int tperiod;
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Timer Support Routines
|
||||
*
|
||||
* The following section of C4x timer code is based on C40 specific
|
||||
* timer code from Ran Cabell <rcabell@norfolk.infi.net>. The
|
||||
* only C3x/C4x difference spotted was the address of the timer.
|
||||
* The names have been changed to be more RTEMS like.
|
||||
*/
|
||||
|
||||
#define c4x_timer_get_control( _timer ) (volatile int)(_timer->tcontrol)
|
||||
|
||||
#define c4x_timer_set_control( _timer, _value ) \
|
||||
do { \
|
||||
(volatile int)(_timer->tcontrol) = _value; \
|
||||
} while (0);
|
||||
|
||||
#define c4x_timer_start( _timer ) \
|
||||
c4x_timer_set_control(_timer, 0x02c1 )
|
||||
|
||||
#define c4x_timer_stop( _timer ) _timer->tcontrol = 0
|
||||
|
||||
#define c4x_timer_get_counter( _timer ) (volatile int)(_timer->tcounter)
|
||||
|
||||
#define c4x_timer_set_counter( _timer, _value ) \
|
||||
do { \
|
||||
(volatile int)(_timer->tcounter) = _value; \
|
||||
} while (0);
|
||||
|
||||
#define c4x_timer_get_period( _timer ) (volatile int)(_timer->tperiod)
|
||||
|
||||
#define c4x_timer_set_period( _timer, _value ) \
|
||||
do { \
|
||||
(volatile int)(_timer->tperiod) = _value; \
|
||||
} while (0);
|
||||
|
||||
/*
|
||||
* IO Flags
|
||||
*
|
||||
* NOTE: iof on c3x, iiof on c4x
|
||||
*/
|
||||
|
||||
#ifdef _TMS320C40
|
||||
|
||||
#else
|
||||
|
||||
static inline uint32_t c3x_get_iof( void )
|
||||
{
|
||||
register uint32_t iof_value;
|
||||
|
||||
__asm__ volatile ("ldi iof, %0" : "=r" (iof_value));
|
||||
return iof_value;
|
||||
}
|
||||
|
||||
static inline void c3x_set_iof( uint32_t value )
|
||||
{
|
||||
__asm__ volatile ("ldi %0,iof" : : "g" (value) : "iof", "cc");
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#endif
|
||||
/* end if include file */
|
||||
Reference in New Issue
Block a user