microblaze: Add support for libbsd networking

This includes fixes and improvements necessary to get libbsd networking
running.

bsps/microblaze/microblaze_fpga/dts/system.dts

@@ -222,7 +222,7 @@
 			phandle = <0x6>;
 			dmas = <&dma 0
 				&dma 1>;
-			dma-names = "rx", "tx";
+			dma-names = "tx", "rx";
 			memory-region = <&dma_reserved>;
 			mdio {
 				#address-cells = <0x1>;
@@ -230,7 +230,7 @@
 
 				phy@1 {
 					device_type = "ethernet-phy";
-					reg = <0x1>;
+					reg = <0x7>;
 					phandle = <0x5>;
 				};
 			};

bsps/microblaze/microblaze_fpga/fdt/bsp_fdt.c

@@ -8,6 +8,9 @@
  */
 
 #include <bsp.h>
+#include <bsp/fdt.h>
+
+#include BSP_MICROBLAZE_FPGA_DTB_HEADER_PATH
 
 const void *bsp_fdt_get(void)
 {

bsps/microblaze/microblaze_fpga/include/bsp.h

@@ -50,6 +50,11 @@ extern "C" {
 extern const unsigned char system_dtb[];
 extern const size_t system_dtb_size;
 
+void microblaze_enable_icache(void);
+void microblaze_enable_dcache(void);
+void microblaze_invalidate_icache(void);
+void microblaze_invalidate_dcache(void);
+
 #ifdef __cplusplus
 }
 #endif

bsps/microblaze/microblaze_fpga/include/bsp/microblaze-dtb.h

@@ -4,9 +4,13 @@
  *  WARNING: Automatically generated -- do not edit!
  */
 
+#ifndef __microblaze_dtb_h
+#define __microblaze_dtb_h
+
+#include <rtems/score/basedefs.h>
 #include <sys/types.h>
 
-const unsigned char system_dtb[] = {
+const unsigned char system_dtb[] RTEMS_ALIGNED(8) = {
   0xd0, 0x0d, 0xfe, 0xed, 0x00, 0x00, 0x2c, 0x85, 0x00, 0x00, 0x00, 0x38,
   0x00, 0x00, 0x1c, 0xa0, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x11,
   0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xe5,
@@ -307,7 +311,7 @@ const unsigned char system_dtb[] = {
   0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x10,
   0x00, 0x00, 0x0c, 0xcc, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x0c, 0xd1, 0x72, 0x78, 0x00, 0x74,
+  0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x0c, 0xd1, 0x74, 0x78, 0x00, 0x72,
   0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
   0x00, 0x00, 0x0c, 0xdb, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x01,
   0x6d, 0x64, 0x69, 0x6f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
@@ -317,7 +321,7 @@ const unsigned char system_dtb[] = {
   0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0d,
   0x00, 0x00, 0x00, 0x95, 0x65, 0x74, 0x68, 0x65, 0x72, 0x6e, 0x65, 0x74,
   0x2d, 0x70, 0x68, 0x79, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xf3, 0x00, 0x00, 0x00, 0x01,
+  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xf3, 0x00, 0x00, 0x00, 0x07,
   0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x0a, 0x62,
   0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02,
   0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, 0x64, 0x6d, 0x61, 0x40,
@@ -960,3 +964,5 @@ const unsigned char system_dtb[] = {
 };
 
 const size_t system_dtb_size = sizeof(system_dtb);
+
+#endif /* __microblaze_dtb_h */

bsps/microblaze/microblaze_fpga/irq/irq.c

@@ -141,7 +141,7 @@ void bsp_interrupt_dispatch( uint32_t source )
 
   if ( source == 0xFF ) {
     /* Read interrupt controller to get the source */
-    vector_number = intc->isr;
+    vector_number = intc->isr & intc->ier;
 
     /* Handle and the first interrupt that is set */
     uint8_t interrupt_status = 0;

bsps/microblaze/microblaze_fpga/start/bspstart.c

@@ -39,5 +39,11 @@
 
 void bsp_start( void )
 {
+  microblaze_invalidate_icache();
+  microblaze_enable_icache();
+
+  microblaze_invalidate_dcache();
+  microblaze_enable_dcache();
+
   bsp_interrupt_initialize();
 }

bsps/microblaze/microblaze_fpga/start/microblaze_enable_dcache.S

@@ -0,0 +1,20 @@
+/******************************************************************************
+* Copyright (c) 2004 - 2020 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+	.text
+	.globl	microblaze_enable_dcache
+	.ent	microblaze_enable_dcache
+	.align	2
+microblaze_enable_dcache:
+    /* Read the MSR register */
+	mfs	r8, rmsr
+	/* Set the interrupt enable bit */
+	ori	r8, r8, 0x80
+	/* Save the MSR register */
+	mts	rmsr, r8
+	/* Return */
+	rtsd	r15, 8
+	nop
+    .end	microblaze_enable_dcache

bsps/microblaze/microblaze_fpga/start/microblaze_enable_icache.S

@@ -0,0 +1,20 @@
+/******************************************************************************
+* Copyright (c) 2004 - 2020 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+	.text
+	.globl	microblaze_enable_icache
+	.ent	microblaze_enable_icache
+	.align	2
+microblaze_enable_icache:
+	/* Read the MSR register */
+	mfs	r8, rmsr
+	/* Set the interrupt enable bit */
+	ori	r8, r8, 0x20
+	/* Save the MSR register */
+	mts	rmsr, r8
+	/* Return */
+	rtsd	r15, 8
+	nop
+	.end	microblaze_enable_icache

bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_dcache.S

@@ -0,0 +1,29 @@
+/******************************************************************************
+* Copyright (c) 2008 - 2020 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+#include <bspopts.h>
+
+	.text
+	.globl	microblaze_invalidate_dcache
+	.ent	microblaze_invalidate_dcache
+	.align	2
+
+microblaze_invalidate_dcache:
+	addik 	r5, r0, BSP_MICROBLAZE_FPGA_DCACHE_BASE & (-(4 * BSP_MICROBLAZE_FPGA_DCACHE_LINE_LEN))
+	addik	r6, r5, BSP_MICROBLAZE_FPGA_DCACHE_SIZE &  (-(4 * BSP_MICROBLAZE_FPGA_DCACHE_LINE_LEN))
+
+L_start:
+	wdc	r5, r0                                          /* Invalidate the Cache */
+
+	cmpu	r18, r5, r6                                     /* Are we at the end? */
+	blei	r18, L_done
+
+	brid	L_start                                         /* Branch to the beginning of the loop */
+	addik	r5, r5, (BSP_MICROBLAZE_FPGA_DCACHE_LINE_LEN * 4)   /* Increment the address by 4 (delay slot) */
+L_done:
+	rtsd	r15, 8                                          /* Return */
+	nop
+
+	.end	microblaze_invalidate_dcache

bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_icache.S

@@ -0,0 +1,28 @@
+/******************************************************************************
+* Copyright (c) 2008 - 2020 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+#include <bspopts.h>
+
+	.text
+	.globl	microblaze_invalidate_icache
+	.ent	microblaze_invalidate_icache
+	.align	2
+
+microblaze_invalidate_icache:
+    addik 	r5, r0, BSP_MICROBLAZE_FPGA_ICACHE_BASE & (-(4 * BSP_MICROBLAZE_FPGA_ICACHE_LINE_LEN))  /* Align to cache line */
+	addik	r6, r5, BSP_MICROBLAZE_FPGA_ICACHE_SIZE & (-(4 * BSP_MICROBLAZE_FPGA_ICACHE_LINE_LEN))  /* Compute end */
+
+L_start:
+	wic	r5, r0                                          /* Invalidate the Cache */
+
+	cmpu	r18, r5, r6                                     /* Are we at the end? */
+	blei	r18, L_done
+
+	brid	L_start                                         /* Branch to the beginning of the loop */
+	addik	r5, r5, (BSP_MICROBLAZE_FPGA_ICACHE_LINE_LEN * 4)   /* Increment the address by 4 (delay slot) */
+L_done:
+	rtsd	r15, 8                                          /* Return */
+    nop
+	.end	microblaze_invalidate_icache

cpukit/score/cpu/microblaze/cpu.c

@@ -116,6 +116,5 @@ void _CPU_ISR_install_vector(
 void *_CPU_Thread_Idle_body( uintptr_t ignored )
 {
   while ( true ) {
-    __asm__ volatile ( "sleep" );
   }
 }

cpukit/score/cpu/microblaze/cpu_asm.S

@@ -116,9 +116,7 @@ after_stack_switch:
 	beqi r3, quick_exit
 
 	/* Return to interrupted thread and make it do a dispatch */
-	addik r14, r0, thread_dispatch
+	bri thread_dispatch
-	rtid r14, 0
-	nop
 
 quick_exit:
 	/* Simple return from nested interrupt */

spec/build/bsps/microblaze/microblaze_fpga/grp.yml

@@ -17,6 +17,20 @@ links:
   uid: start
 - role: build-dependency
   uid: optconsoleinterrupts
+- role: build-dependency
+  uid: optdcachebaseaddress
+- role: build-dependency
+  uid: optdcachelinelen
+- role: build-dependency
+  uid: optdcachesize
+- role: build-dependency
+  uid: optdtbheaderpath
+- role: build-dependency
+  uid: opticachebaseaddress
+- role: build-dependency
+  uid: opticachelinelen
+- role: build-dependency
+  uid: opticachesize
 - role: build-dependency
   uid: optintcbaseaddress
 - role: build-dependency

spec/build/bsps/microblaze/microblaze_fpga/obj.yml

@@ -23,7 +23,6 @@ source:
 - bsps/microblaze/microblaze_fpga/clock/clock.c
 - bsps/microblaze/microblaze_fpga/console/console-io.c
 - bsps/microblaze/microblaze_fpga/console/debug-io.c
-- bsps/microblaze/microblaze_fpga/dts/microblaze-dtb.c
 - bsps/microblaze/microblaze_fpga/fdt/bsp_fdt.c
 - bsps/microblaze/microblaze_fpga/irq/irq.c
 - bsps/microblaze/microblaze_fpga/start/_exception_handler.S
@@ -32,6 +31,10 @@ source:
 - bsps/microblaze/microblaze_fpga/start/bspreset.c
 - bsps/microblaze/microblaze_fpga/start/bspstart.c
 - bsps/microblaze/microblaze_fpga/start/crtinit.S
+- bsps/microblaze/microblaze_fpga/start/microblaze_enable_dcache.S
+- bsps/microblaze/microblaze_fpga/start/microblaze_enable_icache.S
+- bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_dcache.S
+- bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_icache.S
 - bsps/microblaze/shared/dev/serial/uartlite.c
 - bsps/microblaze/shared/dev/serial/uartlite_l.c
 - bsps/shared/cache/nocache.c

spec/build/bsps/microblaze/microblaze_fpga/optdcachebaseaddress.yml

@@ -0,0 +1,18 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- env-assign: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+default: 0x80000000
+default-by-variant: []
+description: |
+  base address of the data cache
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: BSP_MICROBLAZE_FPGA_DCACHE_BASE
+type: build

spec/build/bsps/microblaze/microblaze_fpga/optdcachelinelen.yml

@@ -0,0 +1,17 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- define: null
+build-type: option
+copyrights:
+- Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+default: 4
+default-by-variant: []
+description: |
+  length of the data cache line
+enabled-by: true
+format: '{}'
+links: []
+name: BSP_MICROBLAZE_FPGA_DCACHE_LINE_LEN
+type: build

spec/build/bsps/microblaze/microblaze_fpga/optdcachesize.yml

@@ -0,0 +1,17 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- define: null
+build-type: option
+copyrights:
+- Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+default: 32768
+default-by-variant: []
+description: |
+  size of the data cache in bytes
+enabled-by: true
+format: '{}'
+links: []
+name: BSP_MICROBLAZE_FPGA_DCACHE_SIZE
+type: build

spec/build/bsps/microblaze/microblaze_fpga/optdtbheaderpath.yml

@@ -0,0 +1,17 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-string: null
+- define: null
+build-type: option
+copyrights:
+- Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
+default: bsp/microblaze-dtb.h
+default-by-variant: []
+description: |
+  the path to the header file containing the device tree binary. See the BSP
+  documentation for more information.
+enabled-by: true
+format: '{}'
+links: []
+name: BSP_MICROBLAZE_FPGA_DTB_HEADER_PATH
+type: build

spec/build/bsps/microblaze/microblaze_fpga/opticachebaseaddress.yml

@@ -0,0 +1,18 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- env-assign: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+default: 0x80000000
+default-by-variant: []
+description: |
+  base address of the instruction cache
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: BSP_MICROBLAZE_FPGA_ICACHE_BASE
+type: build

spec/build/bsps/microblaze/microblaze_fpga/opticachelinelen.yml

@@ -0,0 +1,17 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- define: null
+build-type: option
+copyrights:
+- Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+default: 8
+default-by-variant: []
+description: |
+  length of the instruction cache line
+enabled-by: true
+format: '{}'
+links: []
+name: BSP_MICROBLAZE_FPGA_ICACHE_LINE_LEN
+type: build

spec/build/bsps/microblaze/microblaze_fpga/opticachesize.yml

@@ -0,0 +1,17 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- define: null
+build-type: option
+copyrights:
+- Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+default: 32768
+default-by-variant: []
+description: |
+  size of the instruction cache in bytes
+enabled-by: true
+format: '{}'
+links: []
+name: BSP_MICROBLAZE_FPGA_ICACHE_SIZE
+type: build