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https://gitlab.rtems.org/rtems/rtos/rtems.git
synced 2025-12-06 07:33:17 +00:00
libdebugger/arm: Clean up the building on arm variants.
This commit is contained in:
@@ -51,13 +51,13 @@
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/*
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/*
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* ARM Variant controls.
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* ARM Variant controls.
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*/
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*/
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#if defined(__ARM_ARCH_7A__) || \
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#if (__ARM_ARCH >= 7) && \
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defined(__ARM_ARCH_7R__)
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(__ARM_ARCH_PROFILE == 'A' || __ARM_ARCH_PROFILE == 'R')
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#define ARM_CP15 1
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#define ARM_CP15 1
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#endif
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#endif
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#if (defined(__ARM_ARCH_7M__) || \
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#if (__ARM_ARCH >= 7) && \
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defined(__ARM_ARCH_7EM__))
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(__ARM_ARCH_PROFILE == 'M')
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#define ARM_THUMB_ONLY 1
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#define ARM_THUMB_ONLY 1
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#else
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#else
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#define ARM_THUMB_ONLY 0
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#define ARM_THUMB_ONLY 0
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@@ -80,7 +80,9 @@
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*
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*
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* If the variant only supports thumb insturctions disable the support.
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* If the variant only supports thumb insturctions disable the support.
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*/
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*/
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#if !ARM_THUMB_ONLY && defined(__thumb__)
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#define NEEDS_THUMB_SWITCH !ARM_THUMB_ONLY && defined(__thumb__)
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#if NEEDS_THUMB_SWITCH
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#define ARM_SWITCH_REG uint32_t arm_switch_reg
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#define ARM_SWITCH_REG uint32_t arm_switch_reg
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#define ARM_SWITCH_REG_ASM [arm_switch_reg] "=&r" (arm_switch_reg)
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#define ARM_SWITCH_REG_ASM [arm_switch_reg] "=&r" (arm_switch_reg)
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#define ARM_SWITCH_REG_ASM_L ARM_SWITCH_REG_ASM,
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#define ARM_SWITCH_REG_ASM_L ARM_SWITCH_REG_ASM,
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@@ -205,7 +207,7 @@ static const size_t arm_reg_offsets[RTEMS_DEBUGGER_NUMREGS + 1] =
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/**
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/**
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* The various status registers.
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* The various status registers.
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*/
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*/
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#if defined(ARM_MULTILIB_ARCH_V4)
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#if defined(ARM_MULTILIB_ARCH_V4) || defined(ARM_MULTILIB_ARCH_V6M)
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#define FRAME_SR(_frame) (_frame)->register_cpsr
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#define FRAME_SR(_frame) (_frame)->register_cpsr
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#elif defined(ARM_MULTILIB_ARCH_V7M)
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#elif defined(ARM_MULTILIB_ARCH_V7M)
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#define FRAME_SR(_frame) (_frame)->register_xpsr
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#define FRAME_SR(_frame) (_frame)->register_xpsr
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@@ -343,7 +345,9 @@ static arm_debug_hwbreak hw_breaks[ARM_HW_BREAKPOINT_MAX];
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/*
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/*
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* Use to locally probe and catch exceptions when accessinf suspect addresses.
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* Use to locally probe and catch exceptions when accessinf suspect addresses.
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*/
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*/
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#if ARM_CP15
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static void __attribute__((naked)) arm_debug_unlock_abort(void);
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static void __attribute__((naked)) arm_debug_unlock_abort(void);
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#endif
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/*
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/*
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* Target debugging support. Use this to debug the backend.
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* Target debugging support. Use this to debug the backend.
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@@ -823,9 +827,12 @@ static int
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arm_debug_mmap_enable(rtems_debugger_target* target, uint32_t dbgdidr)
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arm_debug_mmap_enable(rtems_debugger_target* target, uint32_t dbgdidr)
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{
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{
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uint32_t val;
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uint32_t val;
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void* abort_handler;
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int rc = -1;
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int rc = -1;
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#if ARM_CP15
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void* abort_handler;
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#endif
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/*
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/*
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* File scope as setjmp/longjmp effect the local stack variables.
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* File scope as setjmp/longjmp effect the local stack variables.
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*/
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*/
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@@ -1399,7 +1406,7 @@ target_exception(CPU_Exception_frame* frame)
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* Note, the code currently assumes cp15 has been set up to match the
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* Note, the code currently assumes cp15 has been set up to match the
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* instruction set being used.
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* instruction set being used.
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*/
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*/
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#define EXCEPTION_ENTRY_EXC_V4() \
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#define EXCEPTION_ENTRY_EXC() \
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__asm__ volatile( \
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__asm__ volatile( \
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ASM_ARM_MODE \
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ASM_ARM_MODE \
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"sub sp, %[frame_size]\n" /* alloc the frame and CPSR */ \
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"sub sp, %[frame_size]\n" /* alloc the frame and CPSR */ \
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@@ -1444,7 +1451,7 @@ target_exception(CPU_Exception_frame* frame)
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#define ARM_CLEAR_THUMB_MODE "bic r1, r1, %[psr_t]\n" /* clear thumb */
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#define ARM_CLEAR_THUMB_MODE "bic r1, r1, %[psr_t]\n" /* clear thumb */
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#define EXCEPTION_ENTRY_THREAD_V4(_frame) \
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#define EXCEPTION_ENTRY_THREAD(_frame) \
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__asm__ volatile( \
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__asm__ volatile( \
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ASM_ARM_MODE \
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ASM_ARM_MODE \
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"ldr lr, [sp]\n" /* recover the link reg */ \
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"ldr lr, [sp]\n" /* recover the link reg */ \
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@@ -1528,7 +1535,7 @@ target_exception(CPU_Exception_frame* frame)
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* Note, the code currently assumes cp15 has been set up to match the
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* Note, the code currently assumes cp15 has been set up to match the
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* instruction set being used.
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* instruction set being used.
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*/
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*/
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#define EXCEPTION_EXIT_THREAD_V4(_frame) \
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#define EXCEPTION_EXIT_THREAD(_frame) \
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__asm__ volatile( \
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__asm__ volatile( \
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ASM_ARM_MODE \
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ASM_ARM_MODE \
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"mov r0, %[i_frame]\n" /* get the frame */ \
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"mov r0, %[i_frame]\n" /* get the frame */ \
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@@ -1569,38 +1576,22 @@ target_exception(CPU_Exception_frame* frame)
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[i_frame] "r" (_frame) \
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[i_frame] "r" (_frame) \
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: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "memory")
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: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "memory")
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#define EXCEPTION_EXIT_EXC_V4() \
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#define EXCEPTION_EXIT_EXC() \
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__asm__ volatile( \
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__asm__ volatile( \
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ASM_ARM_MODE \
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ASM_ARM_MODE \
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"ldr lr, [sp]\n" /* recover the link reg */ \
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"ldr lr, [sp]\n" /* recover the link reg */ \
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"add sp, #4\n" \
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"add sp, #4\n" \
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"ldm sp, {r0-r12}\n" /* restore the trhead's context */ \
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"ldm sp, {r0-r12}\n" /* restore the thread's context */ \
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"add sp, %[frame_size]\n" /* free the frame */ \
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"add sp, %[frame_size]\n" /* free the frame */ \
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"subs pc, lr, #0\n" /* return from the exc */ \
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"subs pc, lr, #0\n" /* return from the exc */ \
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: \
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: \
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: [frame_size] "i" (EXCEPTION_FRAME_SIZE) \
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: [frame_size] "i" (EXCEPTION_FRAME_SIZE) \
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: "memory")
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: "memory")
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/**
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* ARM Variant support.
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*/
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#if defined(ARM_MULTILIB_ARCH_V4)
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#define EXCEPTION_ENTRY_EXC() EXCEPTION_ENTRY_EXC_V4()
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#define EXCEPTION_ENTRY_THREAD(_frame) EXCEPTION_ENTRY_THREAD_V4(_frame)
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#define EXCEPTION_EXIT_THREAD(_frame) EXCEPTION_EXIT_THREAD_V4(_frame)
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#define EXCEPTION_EXIT_EXC() EXCEPTION_EXIT_EXC_V4()
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#elif defined(ARM_MULTILIB_ARCH_V7M)
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#define EXCEPTION_ENTRY_EXC() (void) arm_switch_reg
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#define EXCEPTION_ENTRY_THREAD(_frame) (_frame) = NULL
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#define EXCEPTION_EXIT_THREAD(_frame) (_frame) = NULL
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#define EXCEPTION_EXIT_EXC() (void) arm_switch_reg
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#else
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#error ARM architecture is not supported.
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#endif
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/*
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/*
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* This is used to catch faulting accesses.
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* This is used to catch faulting accesses.
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*/
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*/
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#if ARM_CP15
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static void __attribute__((naked))
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static void __attribute__((naked))
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arm_debug_unlock_abort(void)
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arm_debug_unlock_abort(void)
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{
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{
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@@ -1610,6 +1601,7 @@ arm_debug_unlock_abort(void)
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EXCEPTION_ENTRY_THREAD(frame);
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EXCEPTION_ENTRY_THREAD(frame);
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longjmp(unlock_abort_jmpbuf, -1);
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longjmp(unlock_abort_jmpbuf, -1);
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}
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}
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#endif
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static void __attribute__((naked))
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static void __attribute__((naked))
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target_exception_undefined_instruction(void)
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target_exception_undefined_instruction(void)
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