mirror of
https://gitlab.rtems.org/rtems/rtos/rtems.git
synced 2025-12-05 15:15:44 +00:00
@@ -9,6 +9,7 @@
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*/
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*/
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/*
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/*
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* Copyright (C) 2023 embedded brains GmbH & Co. KG
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* Copyright (C) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz>
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* Copyright (C) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz>
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*
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*
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* Czech Technical University in Prague
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* Czech Technical University in Prague
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@@ -50,7 +51,32 @@
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#define PBIST_March13N_SP 0x00000008U /**< March13 N Algo for 1 Port mem */
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#define PBIST_March13N_SP 0x00000008U /**< March13 N Algo for 1 Port mem */
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BSP_START_TEXT_SECTION void bsp_start_hook_0( void )
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/* Use assembly code to avoid using the stack */
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__attribute__((__naked__)) void bsp_start_hook_0( void )
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{
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__asm__ volatile (
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/* Check if we run in SRAM */
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"ldr r0, =#" RTEMS_XSTRING( TMS570_MEMORY_SRAM_ORIGIN ) "\n"
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"ldr r1, =#" RTEMS_XSTRING( TMS570_MEMORY_SRAM_SIZE ) "\n"
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"sub r0, lr, r0\n"
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"cmp r1, r0\n"
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"blt 1f\n"
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/*
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* Initialize the SRAM if we are not running in SRAM. While we are called,
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* non-volatile register r7 is not used by start.S.
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*/
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"movs r0, #0x1\n"
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"mov r7, lr\n"
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"bl tms570_memory_init\n"
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"mov lr, r7\n"
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/* Jump to the high level start hook */
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"1: b tms570_start_hook_0\n"
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);
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}
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static RTEMS_USED void tms570_start_hook_0( void )
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{
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{
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#if TMS570_VARIANT == 3137
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#if TMS570_VARIANT == 3137
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/*
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/*
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@@ -170,15 +196,6 @@ BSP_START_TEXT_SECTION void bsp_start_hook_0( void )
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tms570_pbist_run_and_check( 0x08300020U, /* ESRAM Single Port PBIST */
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tms570_pbist_run_and_check( 0x08300020U, /* ESRAM Single Port PBIST */
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(uint32_t) PBIST_March13N_SP );
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(uint32_t) PBIST_March13N_SP );
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/*
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* Initialize CPU RAM.
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* This function uses the system module's hardware for auto-initialization of memories and their
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* associated protection schemes. The CPU RAM is initialized by setting bit 0 of the MSIENA register.
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* Hence the value 0x1 passed to the function.
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* This function will initialize the entire CPU RAM and the corresponding ECC locations.
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*/
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tms570_memory_init( 0x1U );
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/*
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/*
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* Enable ECC checking for TCRAM accesses.
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* Enable ECC checking for TCRAM accesses.
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* This function enables the CPU's ECC logic for accesses to B0TCM and B1TCM.
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* This function enables the CPU's ECC logic for accesses to B0TCM and B1TCM.
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