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2002-03-13 Greg Menke <gregory.menke@gsfc.nasa.gov>

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* cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
	* rtems/score/cpu.h: Fixed register numbering in comments and made
	interrupt enable/disable more robust.
This commit is contained in:
Joel Sherrill
2002-03-15 19:47:36 +00:00
parent 5ab8aef571
commit 293c0e30f8
6 changed files with 84 additions and 48 deletions
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7
c/src/exec/score/cpu/mips/ChangeLog
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@@ -1,5 +1,10 @@
2002-03-05 Greg Menke <gregory.menke@gsfc.nasa.gov>
2002-03-13 Greg Menke <gregory.menke@gsfc.nasa.gov>
* cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
* rtems/score/cpu.h: Fixed register numbering in comments and made
interrupt enable/disable more robust.
2002-03-05 Greg Menke <gregory.menke@gsfc.nasa.gov>
* cpu_asm.S: Added support for the debug exception vector, cleaned
up the exception processing & exception return stuff. Re-added
EPC in the task context structure so the gdb stub will know where

11
c/src/exec/score/cpu/mips/cpu_asm.S
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@@ -945,10 +945,19 @@ _ISR_Handler_1:
#if __mips == 3
li t1,SR_EXL | SR_IE
#elif __mips == 1
li t1,SR_IEC | SR_KUC /* ints off, kernel mode on (kernel mode enabled is bit clear..argh!) */
/* ints off, current & prev kernel mode on (kernel mode enabled is bit clear..argh!) */
li t1,SR_IEC | SR_KUP | SR_KUC
#endif
not t1
and t0, t1
#if __mips == 1
/* make sure previous int enable is on because we're returning from an interrupt
** which means interrupts have to be enabled
*/
li t1,SR_IEP
or t0,t1
#endif
MTC0 t0, C0_SR
NOP

48
c/src/exec/score/cpu/mips/rtems/score/cpu.h
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@@ -553,24 +553,25 @@ typedef struct
__MIPS_REGISTER_TYPE exctype; /* 77 -- NOT FILLED IN (not enough info) */
__MIPS_REGISTER_TYPE mode; /* 78 -- NOT FILLED IN (not enough info) */
__MIPS_REGISTER_TYPE prid; /* 79 -- NOT FILLED IN (not need to do so) */
/* end of __mips == 1 so NREGS == 80 */
__MIPS_REGISTER_TYPE tar ; /* 80 -- target address register, filled on exceptions */
/* end of __mips == 1 so NREGS == 81 */
#if __mips == 3
__MIPS_REGISTER_TYPE tlblo1; /* 80 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE pagemask; /* 81 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE wired; /* 82 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE count; /* 83 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE compare; /* 84 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE config; /* 85 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE lladdr; /* 86 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE watchlo; /* 87 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE watchhi; /* 88 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE ecc; /* 89 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE cacheerr; /* 90 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE taglo; /* 91 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE taghi; /* 92 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE errpc; /* 93 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE xctxt; /* 94 -- NOT FILLED IN */
/* end of __mips == 3 so NREGS == 95 */
__MIPS_REGISTER_TYPE tlblo1; /* 81 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE pagemask; /* 82 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE wired; /* 83 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE count; /* 84 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE compare; /* 85 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE config; /* 86 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE lladdr; /* 87 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE watchlo; /* 88 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE watchhi; /* 89 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE ecc; /* 90 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE cacheerr; /* 91 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE taglo; /* 92 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE taghi; /* 93 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE errpc; /* 94 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE xctxt; /* 95 -- NOT FILLED IN */
/* end of __mips == 3 so NREGS == 96 */
#endif
} CPU_Interrupt_frame;
@@ -755,9 +756,10 @@ extern unsigned int mips_interrupt_number_of_vectors;
#define _CPU_ISR_Disable( _level ) \
do { \
mips_get_sr( _level ); \
mips_set_sr( _level & ~SR_INTERRUPT_ENABLE_BITS ); \
_level &= SR_INTERRUPT_ENABLE_BITS; \
unsigned int _scratch; \
mips_get_sr( _scratch ); \
mips_set_sr( _scratch & ~SR_INTERRUPT_ENABLE_BITS ); \
_level = _scratch & SR_INTERRUPT_ENABLE_BITS; \
} while(0)
/*
@@ -782,8 +784,10 @@ extern unsigned int mips_interrupt_number_of_vectors;
#define _CPU_ISR_Flash( _xlevel ) \
do { \
_CPU_ISR_Enable( _xlevel ); \
_CPU_ISR_Disable( _xlevel ); \
unsigned int _scratch2 = _xlevel; \
_CPU_ISR_Enable( _scratch2 ); \
_CPU_ISR_Disable( _scratch2 ); \
_xlevel = _scratch2; \
} while(0)
/*