Imagelibrary/rtems
1
0
Fork 1
mirror of https://gitlab.rtems.org/rtems/rtos/rtems.git synced 2025-12-05 15:15:44 +00:00
Code Issues Packages Projects Releases Wiki Activity

2005-04-28 Joel Sherrill <joel@OARcorp.com>

Browse Source 
* acinclude.m4: Remove dmv177 and ppcn_60x.
	* dmv177/.cvsignore, dmv177/ChangeLog, dmv177/Makefile.am,
	dmv177/QUIRKS, dmv177/README, dmv177/README.net, dmv177/STATUS,
	dmv177/bsp_specs, dmv177/cable.doc, dmv177/configure.ac,
	dmv177/times, dmv177/clock/clock.c, dmv177/console/conscfg.c,
	dmv177/console/debugio.c, dmv177/include/.cvsignore,
	dmv177/include/bsp.h, dmv177/include/dmv170.h, dmv177/include/tm27.h,
	dmv177/scv64/scv64.c, dmv177/sonic/dmvsonic.c, dmv177/start/start.S,
	dmv177/startup/bspclean.c, dmv177/startup/bspstart.c,
	dmv177/startup/genpvec.c, dmv177/startup/linkcmds,
	dmv177/startup/setvec.c, dmv177/startup/vmeintr.c,
	dmv177/timer/timer.c, dmv177/tod/todcfg.c, ppcn_60x/.cvsignore,
	ppcn_60x/ChangeLog, ppcn_60x/Makefile.am, ppcn_60x/README,
	ppcn_60x/STATUS, ppcn_60x/bsp_specs, ppcn_60x/configure.ac,
	ppcn_60x/clock/clock.c, ppcn_60x/console/config.c,
	ppcn_60x/console/console.c, ppcn_60x/console/console.h,
	ppcn_60x/console/debugio.c, ppcn_60x/console/i8042.c,
	ppcn_60x/console/i8042_p.h, ppcn_60x/console/i8042vga.c,
	ppcn_60x/console/i8042vga.h, ppcn_60x/console/ns16550cfg.c,
	ppcn_60x/console/ns16550cfg.h, ppcn_60x/console/vga.c,
	ppcn_60x/console/vga_p.h, ppcn_60x/console/z85c30cfg.c,
	ppcn_60x/console/z85c30cfg.h, ppcn_60x/include/.cvsignore,
	ppcn_60x/include/bsp.h, ppcn_60x/include/extisrdrv.h,
	ppcn_60x/include/nvram.h, ppcn_60x/include/pci.h,
	ppcn_60x/include/tm27.h, ppcn_60x/network/amd79c970.c,
	ppcn_60x/network/amd79c970.h, ppcn_60x/nvram/ds1385.h,
	ppcn_60x/nvram/mk48t18.h, ppcn_60x/nvram/nvram.c,
	ppcn_60x/nvram/prepnvr.h, ppcn_60x/nvram/stk11c68.h,
	ppcn_60x/pci/pci.c, ppcn_60x/start/start.S,
	ppcn_60x/startup/bspclean.c, ppcn_60x/startup/bspstart.c,
	ppcn_60x/startup/bsptrap.S, ppcn_60x/startup/genpvec.c,
	ppcn_60x/startup/linkcmds, ppcn_60x/startup/rtems-ctor.cc,
	ppcn_60x/startup/setvec.c, ppcn_60x/startup/spurious.c,
	ppcn_60x/startup/swap.c, ppcn_60x/timer/timer.c, ppcn_60x/tod/cmos.h,
	ppcn_60x/tod/tod.c, ppcn_60x/universe/universe.c,
	ppcn_60x/vectors/README, ppcn_60x/vectors/align_h.S,
	ppcn_60x/vectors/vectors.S: Removed.
This commit is contained in:
Joel Sherrill
2005-04-28 16:17:39 +00:00
parent a34d5dc122
commit 27d619b86b
84 changed files with 40 additions and 14646 deletions
Download Patch File Download Diff File Expand all files Collapse all files

40
c/src/lib/libbsp/powerpc/ChangeLog
View File

@@ -1,3 +1,43 @@
2005-04-28 Joel Sherrill <joel@OARcorp.com>
* acinclude.m4: Remove dmv177 and ppcn_60x.
* dmv177/.cvsignore, dmv177/ChangeLog, dmv177/Makefile.am,
dmv177/QUIRKS, dmv177/README, dmv177/README.net, dmv177/STATUS,
dmv177/bsp_specs, dmv177/cable.doc, dmv177/configure.ac,
dmv177/times, dmv177/clock/clock.c, dmv177/console/conscfg.c,
dmv177/console/debugio.c, dmv177/include/.cvsignore,
dmv177/include/bsp.h, dmv177/include/dmv170.h, dmv177/include/tm27.h,
dmv177/scv64/scv64.c, dmv177/sonic/dmvsonic.c, dmv177/start/start.S,
dmv177/startup/bspclean.c, dmv177/startup/bspstart.c,
dmv177/startup/genpvec.c, dmv177/startup/linkcmds,
dmv177/startup/setvec.c, dmv177/startup/vmeintr.c,
dmv177/timer/timer.c, dmv177/tod/todcfg.c, ppcn_60x/.cvsignore,
ppcn_60x/ChangeLog, ppcn_60x/Makefile.am, ppcn_60x/README,
ppcn_60x/STATUS, ppcn_60x/bsp_specs, ppcn_60x/configure.ac,
ppcn_60x/clock/clock.c, ppcn_60x/console/config.c,
ppcn_60x/console/console.c, ppcn_60x/console/console.h,
ppcn_60x/console/debugio.c, ppcn_60x/console/i8042.c,
ppcn_60x/console/i8042_p.h, ppcn_60x/console/i8042vga.c,
ppcn_60x/console/i8042vga.h, ppcn_60x/console/ns16550cfg.c,
ppcn_60x/console/ns16550cfg.h, ppcn_60x/console/vga.c,
ppcn_60x/console/vga_p.h, ppcn_60x/console/z85c30cfg.c,
ppcn_60x/console/z85c30cfg.h, ppcn_60x/include/.cvsignore,
ppcn_60x/include/bsp.h, ppcn_60x/include/extisrdrv.h,
ppcn_60x/include/nvram.h, ppcn_60x/include/pci.h,
ppcn_60x/include/tm27.h, ppcn_60x/network/amd79c970.c,
ppcn_60x/network/amd79c970.h, ppcn_60x/nvram/ds1385.h,
ppcn_60x/nvram/mk48t18.h, ppcn_60x/nvram/nvram.c,
ppcn_60x/nvram/prepnvr.h, ppcn_60x/nvram/stk11c68.h,
ppcn_60x/pci/pci.c, ppcn_60x/start/start.S,
ppcn_60x/startup/bspclean.c, ppcn_60x/startup/bspstart.c,
ppcn_60x/startup/bsptrap.S, ppcn_60x/startup/genpvec.c,
ppcn_60x/startup/linkcmds, ppcn_60x/startup/rtems-ctor.cc,
ppcn_60x/startup/setvec.c, ppcn_60x/startup/spurious.c,
ppcn_60x/startup/swap.c, ppcn_60x/timer/timer.c, ppcn_60x/tod/cmos.h,
ppcn_60x/tod/tod.c, ppcn_60x/universe/universe.c,
ppcn_60x/vectors/README, ppcn_60x/vectors/align_h.S,
ppcn_60x/vectors/vectors.S: Removed.
2005-04-28 Jennifer Averett <jennifer.averett@oarcorp.com> 2005-04-28 Jennifer Averett <jennifer.averett@oarcorp.com>
* score603e/Makefile.am, score603e/configure.ac, * score603e/Makefile.am, score603e/configure.ac,

4
c/src/lib/libbsp/powerpc/acinclude.m4
View File

@@ -2,8 +2,6 @@
AC_DEFUN([RTEMS_CHECK_BSPDIR], AC_DEFUN([RTEMS_CHECK_BSPDIR],
[ [
case "$1" in case "$1" in
dmv177 )
AC_CONFIG_SUBDIRS([dmv177]);;
ep1a ) ep1a )
AC_CONFIG_SUBDIRS([ep1a]);; AC_CONFIG_SUBDIRS([ep1a]);;
gen405 ) gen405 )
@@ -18,8 +16,6 @@ AC_DEFUN([RTEMS_CHECK_BSPDIR],
AC_CONFIG_SUBDIRS([mpc8260ads]);; AC_CONFIG_SUBDIRS([mpc8260ads]);;
mvme5500 ) mvme5500 )
AC_CONFIG_SUBDIRS([mvme5500]);; AC_CONFIG_SUBDIRS([mvme5500]);;
ppcn_60x )
AC_CONFIG_SUBDIRS([ppcn_60x]);;
psim ) psim )
AC_CONFIG_SUBDIRS([psim]);; AC_CONFIG_SUBDIRS([psim]);;
score603e ) score603e )

14
c/src/lib/libbsp/powerpc/dmv177/.cvsignore
View File

@@ -1,14 +0,0 @@
aclocal.m4
autom4te*.cache
config.cache
config.guess
config.log
config.status
config.sub
configure
depcomp
install-sh
Makefile
Makefile.in
missing
mkinstalldirs

430
c/src/lib/libbsp/powerpc/dmv177/ChangeLog
View File

@@ -1,430 +0,0 @@
2005-02-16 Ralf Corsepius <ralf.corsepius@rtems.org>
* configure.ac: Remove argument from RTEMS_PPC_EXCEPTIONS.
2005-02-11 Ralf Corsepius <ralf.corsepius@rtems.org>
* Makefile.am: Merge-in wrapup/Makefile.am.
* wrapup/Makefile.am: Remove.
* configure.ac: Reflect changes above.
2005-01-22 Ralf Corsepius <ralf.corsepius@rtems.org>
* tod/todcfg.c: size_t RTC_Count.
2005-01-07 Ralf Corsepius <ralf.corsepius@rtems.org>
* Makefile.am: Eliminate CFLAGS_OPTIMIZE_V.
2005-01-02 Ralf Corsepius <ralf.corsepius@rtems.org>
* Makefile.am, wrapup/Makefile.am: Remove build-variant support.
2004-09-24 Ralf Corsepius <ralf_corsepius@rtems.org>
* configure.ac: Require automake > 1.9.
2004-04-23 Ralf Corsepius <ralf_corsepius@rtems.org>
PR 610/bsps
* Makefile.am: Add include/tm27.h, Cosmetics.
* include/tm27.h: Final cosmetics.
2004-04-22 Ralf Corsepius <ralf_corsepius@rtems.org>
* include/bsp.h: Split out tmtest27 support.
* include/tm27.h: New.
2004-04-21 Ralf Corsepius <ralf_corsepius@rtems.org>
PR 613/bsps
* include/bsp.h: Remove MAX_LONG_TEST_DURATION.
2004-04-21 Ralf Corsepius <ralf_corsepius@rtems.org>
PR 614/bsps
* include/bsp.h: Remove MAX_SHORT_TEST_DURATION (Unused).
2004-04-01 Ralf Corsepius <ralf_corsepius@rtems.org>
* startup/genpvec.c: Include <rtems/chain.h> instead of <chain.h>.
* include/bsp.h: Include <rtems/clockdrv.h> instead of <clockdrv.h>.
* include/bsp.h: Include <rtems/console.h> instead of <console.h>.
* include/bsp.h: Include <rtems/iosupp.h> instead of <iosupp.h>.
* startup/vmeintr.c: Include <rtems/vmeintr.h> instead of <vmeintr.h>.
2004-03-31 Ralf Corsepius <ralf_corsepius@rtems.org>
* clock/clock.c, console/conscfg.c, console/debugio.c,
include/bsp.h, include/dmv170.h, scv64/scv64.c, sonic/dmvsonic.c,
startup/bspstart.c, startup/genpvec.c, startup/vmeintr.c,
timer/timer.c, tod/todcfg.c: Convert to using c99 fixed size types.
2004-02-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: Reflect changes to bsp.am.
Preinstall dist_project_lib*.
2004-02-14 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: Reflect changes to bsp.am.
2004-02-12 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: Use CPPASCOMPILE instead of CCASCOMPILE.
2004-02-06 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* wrapup/Makefile.am: Convert to automake-building rules.
2004-01-30 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: Merge-in clock/Makefile.am, console/Makefile.am,
scv64/Makefile.am, sonic/Makefile.am, start/Makefile.am,
startup/Makefile.am, timer/Makefile.am, tod/Makefile.am. Use automake
compilation rules.
* clock/Makefile.am, console/Makefile.am, scv64/Makefile.am,
sonic/Makefile.am, start/Makefile.am, startup/Makefile.am,
timer/Makefile.am, tod/Makefile.am: Remove.
* configure.ac, wrapup/Makefile.am: Reflect changes above.
2004-01-30 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: Merge-in start/Makefile.am.
* start/Makefile.am: Remove.
* configure.ac: Reflect changes above.
2004-01-30 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* wrapup/Makefile.am: Reflect changes to
../support/*exception_processing/*.
2004-01-28 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* configure.ac: Add nostdinc to AUTOMAKE_OPTIONS.
Add RTEMS_PROG_CCAS.
2004-01-21 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: Add PREINSTALL_DIRS.
2004-01-14 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: Re-add dirstamps to PRE/TMPINSTALL_FILES.
Add PRE/TMPINSTALL_FILES to CLEANFILES.
* start/Makefile.am: Ditto.
* startup/Makefile.am: Ditto.
2004-01-05 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* wrapup/Makefile.am: Eliminate $(LIB).
Use noinst_DATA to trigger building libbsp.a.
2003-12-30 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* tod/Makefile.am: Cosmetics.
* console/Makefile.am: Cosmetics.
2003-12-22 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* clock/Makefile.am: Eliminate VPATH.
* console/Makefile.am: Eliminate VPATH.
* scv64/Makefile.am: Eliminate VPATH.
* sonic/Makefile.am: Eliminate VPATH.
* start/Makefile.am: Eliminate VPATH.
* startup/Makefile.am: Eliminate VPATH.
* timer/Makefile.am: Eliminate VPATH.
* tod/Makefile.am: Eliminate VPATH.
2003-12-13 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* start/Makefile.am: s,${PROJECT_RELEASE}/lib,$(PROJECT_LIB),g.
* startup/Makefile.am: s,${PROJECT_RELEASE}/lib,$(PROJECT_LIB),g.
2003-12-12 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* start/Makefile.am: Use mkdir_p. Remove dirs from PRE/TMPINSTALL_FILES.
* startup/Makefile.am: Use mkdir_p. Remove dirs from PRE/TMPINSTALL_FILES.
2003-12-12 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* configure.ac: Require automake >= 1.8, autoconf >= 2.59.
2003-12-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* start/Makefile.am: Misc cleanups and fixes.
* startup/Makefile.am: Misc cleanups and fixes.
* wrapup/Makefile.am: Misc cleanups and fixes.
2003-12-03 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: Add preinstallation dirstamp support.
* clock/Makefile.am: Cosmetics.
* console/Makefile.am: Cosmetics.
* scv64/Makefile.am: Cosmetics.
* sonic/Makefile.am: Cosmetics.
* startup/Makefile.am: Cosmetics.
* timer/Makefile.am: Cosmetics.
* tod/Makefile.am: Cosmetics.
* wrapup/Makefile.am: Cosmetics.
2003-12-02 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* clock/Makefile.am: Remove all-local: $(ARCH).
* console/Makefile.am: Remove all-local: $(ARCH).
* scv64/Makefile.am: Remove all-local: $(ARCH).
* sonic/Makefile.am: Remove all-local: $(ARCH).
* start/Makefile.am: Remove all-local: $(ARCH).
* startup/Makefile.am: Remove all-local: $(ARCH).
* timer/Makefile.am: Remove all-local: $(ARCH).
* tod/Makefile.am: Remove all-local: $(ARCH).
* wrapup/Makefile.am: Remove all-local: $(ARCH).
2003-09-29 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: Merge-in include/Makefile.am.
Reflect changes to bsp.am.
* include/Makefile.am: Remove.
* configure.ac: Reflect changes above.
2003-09-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* bsp_specs: Remove *lib:.
2003-09-04 Joel Sherrill <joel@OARcorp.com>
* clock/clock.c, console/debugio.c, include/dmv170.h,
startup/bspclean.c, startup/genpvec.c, startup/setvec.c,
startup/vmeintr.c, timer/timer.c: URL for license changed.
2003-09-04 Joel Sherrill <joel@OARcorp.com>
* console/conscfg.c, include/bsp.h, scv64/scv64.c, startup/bspstart.c,
tod/todcfg.c: Removed incorrect statement about copyright assignment.
2003-08-18 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: Reflect having moved aclocal/.
2003-08-16 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: Reflect having moved automake/.
* clock/Makefile.am: Reflect having moved automake/.
* console/Makefile.am: Reflect having moved automake/.
* include/Makefile.am: Reflect having moved automake/.
* scv64/Makefile.am: Reflect having moved automake/.
* sonic/Makefile.am: Reflect having moved automake/.
* start/Makefile.am: Reflect having moved automake/.
* startup/Makefile.am: Reflect having moved automake/.
* timer/Makefile.am: Reflect having moved automake/.
* tod/Makefile.am: Reflect having moved automake/.
* wrapup/Makefile.am: Reflect having moved automake/.
2003-08-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* configure.ac: Use rtems-bugs@rtems.com as bug report email address.
2003-08-06 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
PR 445/bsps
* bsp_specs: Remove -D__embedded__ -Asystem(embedded) from cpp.
Remove cpp, old_cpp (now unused).
2003-03-06 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* configure.ac: Remove AC_CONFIG_AUX_DIR.
2003-02-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* configure.ac: AM_INIT_AUTOMAKE([1.7.2]).
2003-02-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* configure.ac: AC_PREREQ(2.57).
2003-01-20 Joel Sherrill <joel@OARcorp.com>
* startup/linkcmds*: Add FreeBSD sysctl() sections.
2002-12-16 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* clock/Makefile.am: Don't include @RTEMS_BSP@.cfg.
* console/Makefile.am: Don't include @RTEMS_BSP@.cfg.
* scv64/Makefile.am: Don't include @RTEMS_BSP@.cfg.
* sonic/Makefile.am: Don't include @RTEMS_BSP@.cfg.
* start/Makefile.am: Don't include @RTEMS_BSP@.cfg.
* startup/Makefile.am: Don't include @RTEMS_BSP@.cfg.
* timer/Makefile.am: Don't include @RTEMS_BSP@.cfg.
* tod/Makefile.am: Don't include @RTEMS_BSP@.cfg.
2002-12-12 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* start/Makefile.am: Use install-data-local to install startfile.
2002-12-10 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* wrapup/Makefile.am: Don't include @RTEMS_BSP@.cfg.
2002-11-04 Joel Sherrill <joel@OARcorp.com>
* clock/clock.c: Removed warnings.
2002-11-01 Joel Sherrill <joel@OARcorp.com>
* startup/genpvec.c, tod/todcfg.c: Removed warnings.
2002-10-21 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* .cvsignore: Reformat.
Add autom4te*cache.
Remove autom4te.cache.
2002-08-21 Joel Sherrill <joel@OARcorp.com>
* bsp_specs: Added support for -nostdlibs.
2002-08-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* clock/Makefile.am: Use .$(OBJEXT) instead of .o.
* console/Makefile.am: Use .$(OBJEXT) instead of .o.
* scv64/Makefile.am: Use .$(OBJEXT) instead of .o.
* sonic/Makefile.am: Use .$(OBJEXT) instead of .o.
* start/Makefile.am: Use .$(OBJEXT) instead of .o.
* startup/Makefile.am: Use .$(OBJEXT) instead of .o.
* timer/Makefile.am: Use .$(OBJEXT) instead of .o.
* tod/Makefile.am: Use .$(OBJEXT) instead of .o.
* wrapup/Makefile.am: Use .$(OBJEXT) instead of .o.
2002-07-21 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* start/Makefile.am: Eliminate PGMS.
Add bsplib_DATA = $(PROJECT_RELEASE)/lib/start$(LIB_VARIANT).o.
2002-07-20 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* startup/Makefile.am: Add bsplib_DATA = linkcmds.
2002-07-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* wrapup/Makefile.am: Eliminate TMPINSTALL_FILES.
Remove $(OBJS) from all-local.
2002-06-29 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* wrapup/Makefile.am: Remove preinstallation of libbsp.a,
2001-05-09 Joel Sherrill <joel@OARcorp.com>
* startup/linkcmds: In support of gcc 3.1, added one of more
of the sections .jcr, .rodata*, .data.*, .gnu.linkonce.s2.*,
.gnu.linkonce.sb2.*, and .gnu.linkonce.s.*. Spacing corrections
and direction of segments to memory regions may also have been
addressed. This was a sweep across all BSPs.
2001-04-08 Joel Sherrill <joel@OARcorp.com>
* startup/linkcmds: Per PR170, PR171, and PR172 add .eh_frame
2002-03-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* configure.ac:
AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS).
AM_INIT_AUTOMAKE([no-define foreign 1.6]).
* clock/Makefile.am: Remove AUTOMAKE_OPTIONS.
* Makefile.am: Remove AUTOMAKE_OPTIONS.
* console/Makefile.am: Remove AUTOMAKE_OPTIONS.
* include/Makefile.am: Remove AUTOMAKE_OPTIONS.
* scv64/Makefile.am: Remove AUTOMAKE_OPTIONS.
* sonic/Makefile.am: Remove AUTOMAKE_OPTIONS.
* start/Makefile.am: Remove AUTOMAKE_OPTIONS.
* startup/Makefile.am: Remove AUTOMAKE_OPTIONS.
* timer/Makefile.am: Remove AUTOMAKE_OPTIONS.
* tod/Makefile.am: Remove AUTOMAKE_OPTIONS.
* wrapup/Makefile.am: Remove AUTOMAKE_OPTIONS.
2001-12-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* configure.ac: Remove RTEMS_ENABLE_NETWORKING.
2001-11-30 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* configure.ac: Introduce RTEMS_BSP_CONFIGURE.
2001-11-16 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: Add @exceptions@ to SUBDIRS.
* configure.ac: Apply RTEMS_BSPOPTS_*(*) to merge-in settings from
make/custom/dmv177.cfg;
Rename PPC_USE_INSTRUCTION_CACHE to DMV177_USE_INSTRUCTION_CACHE,
Add RTEMS_PPC_EXCEPTIONS([old]).
* include/Makefile.am: include force-preinstall.am.
* startup/bspstart.c: Rename PPC_USE_INSTRUCTION_CACHE to
DMV177_USE_INSTRUCTION_CACHE.
* wrapup/Makefile.am: Apply @exceptions@.
2001-10-25 Joel Sherrill <joel@OARcorp.com>
* startup/linkcmds: Added _init and _fini.
2001-10-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* .cvsignore: Add autom4te.cache for autoconf > 2.52.
* configure.in: Remove.
* configure.ac: New file, generated from configure.in by autoupdate.
2001-09-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* include/Makefile.am: Use 'CLEANFILES ='.
* include/Makefile.am: Use 'TMPINSTALL_FILES ='.
2001-05-25 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* configure.in: Remove CONSOLE_USE_POLLED, HAS_RTC.
2001-05-22 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* configure.in: Add bspopts.h, AC_DEFINE CONSOLE_USE_INTERRUPTS,
CONSOLE_USE_POLLED, HAS_RTC.
* include/.cvsignore: Add bspopts.h*, stamp-h*, coverhd.h, tod.h.
* include/Makefile.am: Use *_HEADERS instead of *H_FILES, New
treatment of tod.h, coverhd.h.
* include/bsp.h: Add include bspopts.h.
2001-05-10 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* configure.in: Use RTEMS_PROG_CC_FOR_TARGET([-ansi -fasm]).
2001-01-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* startup/genpvec.c: #include <chain.h> instead of "chain.h".
2000-11-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
2000-11-02 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
2000-11-01 Joel Sherrill <joel@OARcorp.com>
* startup/bspstart.c: assoc.h, error.h, libio_.h, libio.h,
and libcsupport.h moved from libc to lib/include/rtems and
now must be referenced as <rtems/XXX.h>. Header file order
was cleaned up while doing this.
2000-10-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
Switch to GNU canonicalization.
2000-09-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* clock/Makefile.am, console/Makefile.am, scv64/Makefile.am,
sonic/Makefile.am, start/Makefile.am, startup/Makefile.am,
timer/Makefile.am, tod/Makefile.am, wrapup/Makefile.am: Include
compile.am
2000-08-10 Joel Sherrill <joel@OARcorp.com>
* ChangeLog: New file.

144
c/src/lib/libbsp/powerpc/dmv177/Makefile.am
View File

@@ -1,144 +0,0 @@
##
## $Id$
##
ACLOCAL_AMFLAGS = -I ../../../../aclocal
include $(top_srcdir)/../../../../automake/compile.am
include $(top_srcdir)/../../bsp.am
dist_project_lib_DATA = bsp_specs
include_HEADERS = include/bsp.h
include_HEADERS += include/tm27.h
nodist_include_HEADERS = include/bspopts.h
DISTCLEANFILES = include/bspopts.h
noinst_PROGRAMS =
include_HEADERS += include/dmv170.h
nodist_include_HEADERS += ../../shared/tod.h
nodist_include_HEADERS += ../../shared/include/coverhd.h
EXTRA_DIST = start/start.S
start.$(OBJEXT): start/start.S
$(CPPASCOMPILE) -DASM -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)
dist_project_lib_DATA += startup/linkcmds
noinst_PROGRAMS += clock.rel
clock_rel_SOURCES = clock/clock.c
clock_rel_CPPFLAGS = $(AM_CPPFLAGS)
clock_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
noinst_PROGRAMS += console.rel
console_rel_SOURCES = console/conscfg.c console/debugio.c \
../../shared/console.c
console_rel_CPPFLAGS = $(AM_CPPFLAGS)
console_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
noinst_PROGRAMS += scv64.rel
scv64_rel_SOURCES = scv64/scv64.c
scv64_rel_CPPFLAGS = $(AM_CPPFLAGS)
scv64_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
noinst_PROGRAMS += startup.rel
startup_rel_SOURCES = startup/bspclean.c ../../shared/bsplibc.c \
../../shared/bsppost.c startup/bspstart.c ../../shared/bootcard.c \
../../shared/main.c ../../shared/sbrk.c startup/setvec.c \
startup/genpvec.c startup/vmeintr.c ../../shared/gnatinstallhandler.c
startup_rel_CPPFLAGS = $(AM_CPPFLAGS)
startup_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
noinst_PROGRAMS += timer.rel
timer_rel_SOURCES = timer/timer.c
timer_rel_CPPFLAGS = $(AM_CPPFLAGS)
timer_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
noinst_PROGRAMS += tod.rel
tod_rel_SOURCES = tod/todcfg.c ../../shared/tod.c
tod_rel_CPPFLAGS = $(AM_CPPFLAGS)
tod_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
if HAS_NETWORKING
sonic_CPPFLAGS = -D__INSIDE_RTEMS_BSD_TCPIP_STACK__
noinst_PROGRAMS += sonic.rel
sonic_rel_SOURCES = sonic/dmvsonic.c
sonic_rel_CPPFLAGS = $(AM_CPPFLAGS) $(sonic_CPPFLAGS)
sonic_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
endif
noinst_LIBRARIES = libbsp.a
CLEANFILES = libbsp.a
libbsp_a_SOURCES =
libbsp_a_LIBADD = startup.rel clock.rel console.rel scv64.rel timer.rel \
tod.rel
if HAS_NETWORKING
libbsp_a_LIBADD += sonic.rel
endif
libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
../../../libcpu/@RTEMS_CPU@/shared/cache.rel
all-local: $(PREINSTALL_FILES) $(TMPINSTALL_FILES)
EXTRA_DIST += QUIRKS README.net STATUS cable.doc times
PREINSTALL_DIRS =
PREINSTALL_FILES =
TMPINSTALL_FILES =
$(PROJECT_INCLUDE)/$(dirstamp):
@$(mkdir_p) $(PROJECT_INCLUDE)
@: > $(PROJECT_INCLUDE)/$(dirstamp)
PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp)
$(PROJECT_LIB)/$(dirstamp):
@$(mkdir_p) $(PROJECT_LIB)
@: > $(PROJECT_LIB)/$(dirstamp)
PREINSTALL_DIRS += $(PROJECT_LIB)/$(dirstamp)
$(PROJECT_LIB)/bsp_specs: bsp_specs $(PROJECT_LIB)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_LIB)/bsp_specs
PREINSTALL_FILES += $(PROJECT_LIB)/bsp_specs
$(PROJECT_INCLUDE)/bsp.h: include/bsp.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp.h
$(PROJECT_INCLUDE)/tm27.h: include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h
$(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h
$(PROJECT_INCLUDE)/dmv170.h: include/dmv170.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/dmv170.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/dmv170.h
$(PROJECT_INCLUDE)/tod.h: ../../shared/tod.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tod.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/tod.h
$(PROJECT_INCLUDE)/coverhd.h: ../../shared/include/coverhd.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/coverhd.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/coverhd.h
$(PROJECT_LIB)/start.$(OBJEXT): start.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_LIB)/start.$(OBJEXT)
TMPINSTALL_FILES += $(PROJECT_LIB)/start.$(OBJEXT)
$(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds
PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds
CLEANFILES += $(PREINSTALL_FILES)
DISTCLEANFILES += $(PREINSTALL_DIRS)
CLEANFILES += $(TMPINSTALL_FILES)
include $(top_srcdir)/../../../../automake/subdirs.am
include $(top_srcdir)/../../../../automake/local.am

74
c/src/lib/libbsp/powerpc/dmv177/QUIRKS
View File

@@ -1,74 +0,0 @@
#
# Quirks in the DY-4 DMV177
#
# $Id$
#
JTAG and Caching
================
If data or code caching is enabled on certain revisions of the PPC603e,
then the JTAG emulator interface become disfunctional. You can not
debug using the emulator on these chip revisions. On certain revisions,
it is so bad that when code caching is enabled, you can not even
download code reliably to the board.
Caching and Peripherals
=======================
When caching is enabled, care must be exercised to insure that all
peripheral addresses are still uncached.
Exar 88681 Clock
================
This board uses a different clock for the Exar 88681 DUART than is
documented in the Exar manual or the original MC68681 manual. This
resulted in the need for the the mc68681 libchip driver to support
BSP specific baud rate tables and the development of a DMV177
specific baud rate table.
In the end, this all works but you have a very limited range of
useful baud rates on the 88681 ports compared to what would have
been supported had DY-4 just followed the Exar or Motorola manual.
SCC Addresses
=============
The full set of SCC addresses is not documented in the DY-4 manual
and they are not ordered as one would expect. Normally the four
SCC registers are ordered Control A, Data A, Control B, and Data B.
DY-4 orders them with B first.
This required extra time to debug.
SCV64 and the Foundation Firmware
=================================
DY-4 technical support did not offer code to determine which interrupt
sources were pending at the SCV64. They recommended calling into the
Foundation Firmware ROM monitor to figure this out. The Foundation
Firmware did not recognize enough interrupts on this board to be useful.
In the end, we gave up on their technical support's recommendation
and directly manipulated the SVC64. This is what we wanted to do in
the first place but we got no information from them to aid in this.
Luckily, the manual does document enough of DY-4's mapping of the specific
interrupt sources to make this work.
Z85C30 SCC Clock Speed
======================
The Z85C30 SCC can be factory configured for 10 Mhz or 2.4616 Mhz. Code
had to be added to dynamically determine which clock was installed.
The board we had used a 10 Mhz clock. No testing was done with a 2.4616 Mhz
clock.
P2 Octopus Cable
================
DY-4's P2 breakout is large and a bit unwieldy. It was difficult to
fight into the VME cage we used. The SCSI connector comes off the
side and is very stiff thus making it difficult to route around
anything in the back of the cage. We gave up on trying to use
it in the first few slots of OAR's cage.

49
c/src/lib/libbsp/powerpc/dmv177/README
View File

@@ -1,49 +0,0 @@
#
# $Id$
#
BSP NAME: dmv177
BOARD: DY-4 DMV177
BUS: VMEBus
CPU FAMILY: powerpc
CPU: PowerPC 603e
COPROCESSORS: N/A
MODE: 32 bit mode
DEBUG MONITOR: DY-4 General Purpose Monitor (GPM)
PERIPHERALS
===========
TIMERS: PPC internal Timebase register
RESOLUTION: ???
SERIAL PORTS: 2 RS-232 provided by a Exar 88681
2 RS-422 provided by a Zilog Z8530
REAL-TIME CLOCK: PPC internal Decrementer register
DMA: none
RTC: Harris ICM7170
VIDEO: none
SCSI: QLogic FAS216 SCSI-2 (unsupported)
NETWORKING: National Semiconductor SONIC DP83932B (Ethernet)
DRIVER INFORMATION
==================
CLOCK DRIVER: PPC internal
SHMSUPP: N/A
TIMER DRIVER: PPC internal
CONSOLE DRIVER: Uses libchip drivers for Exar 88681 and Zilog Z8530.
STDIO
=====
These are the default settings.
PORT: Console port 0
ELECTRICAL: RS-232
BAUD: 9600
BITS PER CHARACTER: 8
PARITY: N
STOP BITS: 1
Notes
=====
The console and real-time clock drivers use the libchip library.

44
c/src/lib/libbsp/powerpc/dmv177/README.net
View File

@@ -1,44 +0,0 @@
#
# $Id$
#
Setting the Ethernet Hardware Address
=====================================
The hardware Ethernet address is not set at the factory. It is the
responsibility of the end-user to insure that it is set properly.
This file describes the standard procedure recommended by DY-4
technical support for setting this address. This procedure is
similar to that followed by VxWorks as documented in DY-4
Document Number #807885.
The hardware Ethernet address and OS configuration information
must be stored in the SEEPROM non-volatile memory of the
SVME/DMV-176/177. The Foundation Firmware (FFW) reserves the
first 256 bytes of the SEEPROM for its own use and the remaining
remaining 256 bytes are available for OS specific information.
Three bytes in the Serial EEPROM are used for the lowest three bytes
of the hardware Ethernet address These should be set to the serial
number of your SVME/DMV-176/177 card to ensure a unique Ethernet
address on your network. The three high bytes are hard coded in the
BSP and represent the vendor-specific Ethernet codes (0x00, 0x80, 0x7F).
Together these six bytes form the target's Ethernet address.
Address is of the form ...
NOTE: The serial number is found on the packaging (box) that the
board came in OR it is also located on the solder side of the board and
looks something like SERNO:XXXXXX. It can not be determined dynamically
by software.
Prior to using the Ethernet controller on the SVME/DMV-176/177 for the
first time, the Ethernet address bytes must be programmed into the
Serial EEPROM on the target card. The 'emm' (EEPROM Memory Modification)
command in the General Purpose Monitor (GPM) can be used to do this.
In this example we will assume that the serial number of the target card
is 123456.

82
c/src/lib/libbsp/powerpc/dmv177/STATUS
View File

@@ -1,82 +0,0 @@
#
# This is a status file for the update effort.
#
make/custom
===========
dmv17x.cfg
TOP
===
README
Makefile.in
bsp_specs
clock
=====
clock.c
Makefile.in
console
=======
Changed console from
duart.c
console.c
To
consolebsp.h
console.c
85c30.c
tbl85c30.c
Note: Check the number of serial ports and modify
tbl85c30.c values to indicate the correct values.
Makefile.in - Modified with new file names.
timer
=======
timer.c
Makefile.in
include
=======
chain.h
dmv170.h
bsp.h
Makefile
Makefile.in
coverhd.h
network
=======
Eric's problem
startup
=======
device-tree - remove
linkcmds
setvec.c - Modified to acount for general purpose vector.
sbrk.c - Ok
rtems-ctor.cc - Ok
bspclean.s - Ok
vmeintr.c
Makefile.in - Added genpvec.c
bspstart.c - Modified with changes from vista bsp.
Added:
genpvec.c
Note: Need to add routine which connects the general purpose interupt with the
various interupt handlers. genpvec.c uses this routine and may need
to be modified.
wrapup
=======
wrapup/Makefile.in
vectors
=======
start
=======
start/Makefile.in
start/start.s - Made modifications based upon Score603e mods.

15
c/src/lib/libbsp/powerpc/dmv177/bsp_specs
View File

@@ -1,15 +0,0 @@
%rename endfile old_endfile
%rename startfile old_startfile
%rename link old_link
*startfile:
%{!qrtems: %(old_startfile)} %{!nostdlib: %{qrtems: ecrti%O%s \
%{!qrtems_debug: start.o%s} \
%{qrtems_debug: start_g.o%s}}}
*endfile:
%{!qrtems: %(old_endfile)} %{qrtems: ecrtn%O%s}
*link:
%{!qrtems: %(old_link)} %{qrtems: -Qy -dp -Bstatic -e _start -u __vectors}

97
c/src/lib/libbsp/powerpc/dmv177/cable.doc
View File

@@ -1,97 +0,0 @@
#
# Cable information for the DY-4 DMV177
#
# $Id$
#
Background
==========
All serial cables described in this file were built using RJ-45 ribbon
cables which were plugged into DB-25 or DB-9 adapters wired as described.
Matching the colors of the wires in the shell is the easiest way to
make sure the cable is built properly.
The board is configured as follows:
- An MC68681 is the first two serial ports. These are RS-232 and may
be accessed via the front panel or the P2. The front panel connector
has both A and B serial ports on a single connector. DY-4 part number
"OBYC3ASSY901132-000 Rev-" brings these ports out to two DB-25
female connectors.
- The MC68681 serial ports are also accessible on the P2 connector.
DY-4 part number "OBYC3ASSY901080-004 Rev A" brings these out
to DB-9 female connectors. These were not used in this effort.
- A Z85C30 is used for the third and fourth serial ports. These are
RS-422 and may only be accessed via the P2 connector. These are
brought out to DB-25 male connectors. An RS-422 to RS-232 converter
was used to interface with these serial ports.
References
==========
- Linux Serial FAQ
- http://ahmed.egypt.com/electronics/serial
- DY-4 Documentation
RS-422 Converter
================
An RS-422 to RS-232 converter from B&B Electronics was used to
adapt the RS-422 signals so they could be used with a normal
RS-232 serial port. Here is the information required to purchase
one of these:
RS-232/RS-422 Converter: Model 422LCON
Power Supply: Model 422PS
B&B Electronics Manufacturing Company
707 Dayton Road
PO Box 1040
Ottawa, IL 61350
Voice: (815) 433-5100
FAX: (815)434-7094
Front Panel RS-232 Connection to a PC
=====================================
Board's DB-25 PC's DB-9 Color in
Channel A COM1 Shell
============= ============ =========
RX on pin 2 TX on pin 2 Red
TX on pin 3 RX on pin 3 Blue
GND on pin 7 GND on pin 5 Black
DTR on pin 20 DTR on pin 4 Brown
No other signals are used.
RS-422 Connection to a PC
=========================
This requires two cables with the converter connecting them.
P2 RS-422 to the RS-422/RS-232 Converter
========================================
Board's Converter's Color in
DB-25 RS-422 DB-25 Shell
=============== ============== ========
TXD_A on pin 2 RDA on pin 5 Red
TXD_B on pin 14 RDB on pin 17 Blue
RX_A on pin 3 TDA on pin 2 Brown
RX_B on pin 16 TDB on pin 14 Green
GND on pin 7 GND on pin 7 Black
Converter's PC's DB-9 Color in
RS-232 DB-25 COM1 Shell
=============== ============== ========
TX on pin 2 TX on pin 2 Blue
RX on pin 3 RX on pin 3 Red
GND on pin 5 GND on pin 5 Black
DTR on pin 4 DTR on pin 4 Brown
No other signals

234
c/src/lib/libbsp/powerpc/dmv177/clock/clock.c
View File

@@ -1,234 +0,0 @@
/*
* Clock Tick Device Driver
*
* This routine utilizes the Decrementer Register common to the PPC family.
*
* The tick frequency is directly programmed to the configured number of
* microseconds per tick.
*
* COPYRIGHT (c) 1989-1997.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may in
* the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
#include <stdlib.h>
#include <bsp.h>
#include <rtems/libio.h>
extern rtems_cpu_table Cpu_table;
/*
* The Real Time Clock Counter Timer uses this trap type.
*/
#define CLOCK_VECTOR PPC_IRQ_DECREMENTER
/*
* Clock ticks since initialization
*/
volatile uint32_t Clock_driver_ticks;
/*
* This is the value programmed into the count down timer.
*/
uint32_t Clock_Decrementer_value;
/*
* This is the value of the old isr routine.
*/
rtems_isr_entry Old_ticker;
void Clock_exit( void );
/*
* These are set by clock driver during its init
*/
rtems_device_major_number rtems_clock_major = ~0;
rtems_device_minor_number rtems_clock_minor;
/*PAGE
*
* Clock_isr
*
* This is the clock tick interrupt handler.
*
* Input parameters:
* vector - vector number
*
* Output parameters: NONE
*
* Return values: NONE
*
*/
rtems_isr Clock_isr(
rtems_vector_number vector,
CPU_Interrupt_frame *frame
)
{
/*
* Set the decrementer.
*/
PPC_Set_decrementer( Clock_Decrementer_value );
/*
* The driver has seen another tick.
*/
Clock_driver_ticks += 1;
/*
* Real Time Clock counter/timer is set to automatically reload.
*/
rtems_clock_tick();
}
/*PAGE
*
* Install_clock
*
* This routine actually performs the hardware initialization for the clock.
*
* Input parameters:
* clock_isr - clock interrupt service routine entry point
*
* Output parameters: NONE
*
* Return values: NONE
*
*/
extern int CLOCK_SPEED;
void Install_clock(
rtems_isr_entry clock_isr
)
{
Clock_driver_ticks = 0;
Old_ticker = (rtems_isr_entry) set_vector( clock_isr, CLOCK_VECTOR, 1 );
PPC_Set_decrementer( Clock_Decrementer_value );
atexit( Clock_exit );
}
/*PAGE
*
* Clock_exit
*
* This routine allows the clock driver to exit by masking the interrupt and
* disabling the clock's counter.
*
* Input parameters: NONE
*
* Output parameters: NONE
*
* Return values: NONE
*
*/
void Clock_exit( void )
{
/* nothing to do */;
/* do not restore old vector */
}
/*PAGE
*
* Clock_initialize
*
* This routine initializes the clock driver.
*
* Input parameters:
* major - clock device major number
* minor - clock device minor number
* parg - pointer to optional device driver arguments
*
* Output parameters: NONE
*
* Return values:
* rtems_device_driver status code
*/
rtems_device_driver Clock_initialize(
rtems_device_major_number major,
rtems_device_minor_number minor,
void *pargp
)
{
Clock_Decrementer_value = Cpu_table.clicks_per_usec *
BSP_Configuration.microseconds_per_tick;
Install_clock( (rtems_isr_entry) Clock_isr );
/*
* make major/minor avail to others such as shared memory driver
*/
rtems_clock_major = major;
rtems_clock_minor = minor;
return RTEMS_SUCCESSFUL;
}
/* PAGE
*
* Clock_control
*
* This routine is the clock device driver control entry point.
*
* Input parameters:
* major - clock device major number
* minor - clock device minor number
* parg - pointer to optional device driver arguments
*
* Output parameters: NONE
*
* Return values:
* rtems_device_driver status code
*/
rtems_device_driver Clock_control(
rtems_device_major_number major,
rtems_device_minor_number minor,
void *pargp
)
{
uint32_t isrlevel;
rtems_libio_ioctl_args_t *args = pargp;
if (args == 0)
goto done;
/*
* This is hokey, but until we get a defined interface
* to do this, it will just be this simple...
*/
if (args->command == rtems_build_name('I', 'S', 'R', ' '))
{
Clock_isr( CLOCK_VECTOR, pargp );
}
else if (args->command == rtems_build_name('N', 'E', 'W', ' '))
{
rtems_interrupt_disable( isrlevel );
(void) set_vector( args->buffer, CLOCK_VECTOR, 1 );
rtems_interrupt_enable( isrlevel );
}
done:
return RTEMS_SUCCESSFUL;
}

54
c/src/lib/libbsp/powerpc/dmv177/configure.ac
View File

@@ -1,54 +0,0 @@
## Process this file with autoconf to produce a configure script.
##
## $Id$
AC_PREREQ(2.59)
AC_INIT([rtems-c-src-lib-libbsp-powerpc-dmv177],[_RTEMS_VERSION],[rtems-bugs@rtems.com])
AC_CONFIG_SRCDIR([bsp_specs])
RTEMS_TOP(../../../../../..)
RTEMS_CANONICAL_TARGET_CPU
AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.9])
RTEMS_BSP_CONFIGURE
RTEMS_PROG_CC_FOR_TARGET([-ansi -fasm])
RTEMS_CANONICALIZE_TOOLS
RTEMS_PROG_CCAS
RTEMS_CHECK_NETWORKING
AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes")
## bsp-specific options
RTEMS_BSPOPTS_SET([CONSOLE_USE_INTERRUPTS],[*],[0])
RTEMS_BSPOPTS_HELP([CONSOLE_USE_INTERRUPTS],
[whether using console interrupts])
RTEMS_BSPOPTS_SET([PPC_USE_SPRG],[*],[0])
RTEMS_BSPOPTS_HELP([PPC_USE_SPRG],
[If defined, then the PowerPC specific code in RTEMS will use some
of the special purpose registers to slightly optimize interrupt
response time. The use of these registers can conflict with
other tools like debuggers.])
RTEMS_BSPOPTS_SET([PPC_USE_DATA_CACHE],[*],[0])
RTEMS_BSPOPTS_HELP([PPC_USE_DATA_CACHE],
[If set != 0, then the PowerPC specific code in RTEMS will use
data cache instructions to optimize the context switch code.
This code can conflict with debuggers or emulators. It is known
to break the Corelis PowerPC emulator with at least some combinations
of PowerPC 603e revisions and emulator versions.
The BSP actually contains the call that enables this.])
RTEMS_BSPOPTS_SET([DMV177_USE_INSTRUCTION_CACHE],[*],[1])
RTEMS_BSPOPTS_HELP([DMV177_USE_INSTRUCTION_CACHE],
[If set != 0, then the PowerPC specific code in RTEMS will use
data cache instructions to optimize the context switch code.
This code can conflict with debuggers or emulators.
The BSP actually contains the call that enables this.])
# Explicitly list all Makefiles here
AC_CONFIG_FILES([Makefile])
RTEMS_PPC_EXCEPTIONS
AC_OUTPUT

282
c/src/lib/libbsp/powerpc/dmv177/console/conscfg.c
View File

@@ -1,282 +0,0 @@
/*
* This file contains the TTY driver table for the DY-4 DMV177.
*
* COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994, 1997.
* On-Line Applications Research Corporation (OAR).
*
* $Id$
*/
#include <bsp.h>
#include <libchip/serial.h>
#include <libchip/mc68681.h>
#include <libchip/z85c30.h>
/*
* Configuration specific probe routines
*
*
* NOTE: There are no DMV177 specific configuration routines. These
* routines could be written to dynamically determine which serial
* ports are on a board. Debugging this would require access to
* multiple board models.
*/
/* NONE CURRENTLY PROVIDED */
/*
* The following table configures the console drivers used in this BSP.
*
* The first entry which, when probed, is available, will be named /dev/console,
* all others being given the name indicated.
*/
mc68681_baud_t
dmv177_mc68681_baud_table[4][RTEMS_TERMIOS_NUMBER_BAUD_RATES] = {
{ /* ACR[7] = 0, X = 0 */
MC68681_BAUD_NOT_VALID, /* B0 */
MC68681_BAUD_NOT_VALID, /* B50 */
0x01, /* B75 */
MC68681_BAUD_NOT_VALID, /* B110 */
0x03, /* B134 */
MC68681_BAUD_NOT_VALID, /* B150 */
0x04, /* B200 */
MC68681_BAUD_NOT_VALID, /* B300 */
MC68681_BAUD_NOT_VALID, /* B600 */
MC68681_BAUD_NOT_VALID, /* B1200 */
MC68681_BAUD_NOT_VALID, /* B1800 */
MC68681_BAUD_NOT_VALID, /* B2400 */
0x0A, /* B4800 */
MC68681_BAUD_NOT_VALID, /* B9600 */
MC68681_BAUD_NOT_VALID, /* B19200 */
MC68681_BAUD_NOT_VALID, /* B38400 */
MC68681_BAUD_NOT_VALID, /* B57600 */
MC68681_BAUD_NOT_VALID, /* B115200 */
MC68681_BAUD_NOT_VALID, /* B230400 */
MC68681_BAUD_NOT_VALID /* B460800 */
},
{ /* ACR[7] = 1, X = 0 */
MC68681_BAUD_NOT_VALID, /* B0 */
0x00, /* B50 */
0x01, /* B75 */
MC68681_BAUD_NOT_VALID, /* B110 */
MC68681_BAUD_NOT_VALID, /* B134 */
MC68681_BAUD_NOT_VALID, /* B150 */
0x04, /* B200 */
MC68681_BAUD_NOT_VALID, /* B300 */
MC68681_BAUD_NOT_VALID, /* B600 */
0x0A, /* B1200 */
MC68681_BAUD_NOT_VALID, /* B1800 */
MC68681_BAUD_NOT_VALID, /* B2400 */
MC68681_BAUD_NOT_VALID, /* B4800 */
MC68681_BAUD_NOT_VALID, /* B9600 */
MC68681_BAUD_NOT_VALID, /* B19200 */
MC68681_BAUD_NOT_VALID, /* B38400 */
MC68681_BAUD_NOT_VALID, /* B57600 */
MC68681_BAUD_NOT_VALID, /* B115200 */
MC68681_BAUD_NOT_VALID, /* B230400 */
MC68681_BAUD_NOT_VALID /* B460800 */
},
{ /* ACR[7] = 0, X = 1 */
MC68681_BAUD_NOT_VALID, /* B0 */
0x00, /* B50 */
0x01, /* B75 */
MC68681_BAUD_NOT_VALID, /* B110 */
MC68681_BAUD_NOT_VALID, /* B134 */
MC68681_BAUD_NOT_VALID, /* B150 */
MC68681_BAUD_NOT_VALID, /* B200 */
MC68681_BAUD_NOT_VALID, /* B300 */
MC68681_BAUD_NOT_VALID, /* B600 */
MC68681_BAUD_NOT_VALID, /* B1200 */
MC68681_BAUD_NOT_VALID, /* B1800 */
0x04, /* B2400 */
MC68681_BAUD_NOT_VALID, /* B4800 */
0x05, /* B9600 */
0x06, /* B19200 */
0x07, /* B38400 */
MC68681_BAUD_NOT_VALID, /* B57600 */
MC68681_BAUD_NOT_VALID, /* B115200 */
MC68681_BAUD_NOT_VALID, /* B230400 */
MC68681_BAUD_NOT_VALID /* B460800 */
},
{ /* ACR[7] = 1, X = 1 */
MC68681_BAUD_NOT_VALID, /* B0 */
MC68681_BAUD_NOT_VALID, /* B50 */
0x01, /* B75 */
MC68681_BAUD_NOT_VALID, /* B110 */
0x03, /* B134 */
MC68681_BAUD_NOT_VALID, /* B150 */
MC68681_BAUD_NOT_VALID, /* B200 */
MC68681_BAUD_NOT_VALID, /* B300 */
MC68681_BAUD_NOT_VALID, /* B600 */
MC68681_BAUD_NOT_VALID, /* B1200 */
MC68681_BAUD_NOT_VALID, /* B1800 */
0x04, /* B2400 */
0x0A, /* B4800 */
0x05, /* B9600 */
0x06, /* B19200 */
0x07, /* B38400 */
MC68681_BAUD_NOT_VALID, /* B57600 */
MC68681_BAUD_NOT_VALID, /* B115200 */
MC68681_BAUD_NOT_VALID, /* B230400 */
MC68681_BAUD_NOT_VALID /* B460800 */
},
};
#define MC68681_PORT_CONFIG \
(MC68681_DATA_BAUD_RATE_SET_1|MC68681_XBRG_ENABLED)
/*
* Based on BSP configuration information decide whether to do polling IO
* or interrupt driven IO.
*/
#if (CONSOLE_USE_INTERRUPTS)
#define MC68681_FUNCTIONS &mc68681_fns
#define Z85C30_FUNCTIONS &z85c30_fns
#else
#define MC68681_FUNCTIONS &mc68681_fns_polled
#define Z85C30_FUNCTIONS &z85c30_fns_polled
#endif
boolean dmv177_z85c30_probe(int minor);
boolean dmv177_mc68681_probe(int minor);
console_tbl Console_Port_Tbl[] = {
{
"/dev/com0", /* sDeviceName */
SERIAL_MC68681, /* deviceType */
MC68681_FUNCTIONS, /* pDeviceFns */
dmv177_mc68681_probe, /* deviceProbe */
NULL, /* pDeviceFlow */
16, /* ulMargin */
8, /* ulHysteresis */
(void *)9600, /* baud rate */ /* pDeviceParams */
MC68681_ADDR, /* ulCtrlPort1 */
MC68681_PORT1_ADDR, /* ulCtrlPort2 */
MC68681_PORT_CONFIG, /* ulDataPort */
mc68681_get_register_8, /* getRegister */
mc68681_set_register_8, /* setRegister */
NULL, /* unused */ /* getData */
NULL, /* unused */ /* setData */
(uint32_t)dmv177_mc68681_baud_table, /* ulClock */
DMV170_DUART_IRQ /* ulIntVector */
},
{
"/dev/com1", /* sDeviceName */
SERIAL_MC68681, /* deviceType */
MC68681_FUNCTIONS, /* pDeviceFns */
dmv177_mc68681_probe, /* deviceProbe */
NULL, /* pDeviceFlow */
16, /* ulMargin */
8, /* ulHysteresis */
(void *)9600, /* baud rate */ /* pDeviceParams */
MC68681_ADDR, /* ulCtrlPort1 */
MC68681_PORT2_ADDR, /* ulCtrlPort2 */
MC68681_PORT_CONFIG, /* ulDataPort */
mc68681_get_register_8, /* getRegister */
mc68681_set_register_8, /* setRegister */
NULL, /* unused */ /* getData */
NULL, /* unused */ /* setData */
(uint32_t)dmv177_mc68681_baud_table, /* ulClock */
DMV170_DUART_IRQ /* ulIntVector */
},
{
"/dev/com3", /* sDeviceName */
SERIAL_Z85C30, /* deviceType */
Z85C30_FUNCTIONS, /* pDeviceFns */
dmv177_z85c30_probe, /* deviceProbe */
NULL, /* pDeviceFlow */
16, /* ulMargin */
8, /* ulHysteresis */
(void *)9600, /* baud rate */ /* pDeviceParams */
Z85C30_CTRL_A, /* ulCtrlPort1 */
Z85C30_CTRL_A, /* ulCtrlPort2 */
0, /* ulDataPort */
z85c30_get_register, /* getRegister */
z85c30_set_register, /* setRegister */
NULL, /* getData */
NULL, /* setData */
0, /* filled in by probe */ /* ulClock */
DMV170_SCC_IRQ /* ulIntVector */
},
{
"/dev/com4", /* sDeviceName */
SERIAL_Z85C30, /* deviceType */
Z85C30_FUNCTIONS, /* pDeviceFns */
dmv177_z85c30_probe, /* deviceProbe */
NULL, /* pDeviceFlow */
16, /* ulMargin */
8, /* ulHysteresis */
(void *)9600, /* baud rate */ /* pDeviceParams */
Z85C30_CTRL_B, /* ulCtrlPort1 */
Z85C30_CTRL_A, /* ulCtrlPort2 */
0, /* ulDataPort */
z85c30_get_register, /* getRegister */
z85c30_set_register, /* setRegister */
NULL, /* getData */
NULL, /* setData */
0, /* filled in by probe */ /* ulClock */
DMV170_SCC_IRQ /* ulIntVector */
}
};
/*
* Declare some information used by the console driver
*/
#define NUM_CONSOLE_PORTS (sizeof(Console_Port_Tbl)/sizeof(console_tbl))
unsigned long Console_Port_Count = NUM_CONSOLE_PORTS;
console_data Console_Port_Data[NUM_CONSOLE_PORTS];
rtems_device_minor_number Console_Port_Minor;
/*
* Hopefully, by checking the card resource register, this BSP
* will be able to operate on the DMV171, DMV176, or DMV177.
*/
boolean dmv177_z85c30_probe(int minor)
{
volatile uint32_t *dma_control_status_reg;
volatile uint16_t *card_resource_reg;
uint16_t v;
card_resource_reg = (volatile uint16_t*) DMV170_CARD_RESORCE_REG;
v = *card_resource_reg & DMV170_SCC_INST_MASK;
if ( v != DMV170_SCC_INSTALLED )
return FALSE;
/*
* Figure out the clock speed of the Z85C30 SCC
*/
dma_control_status_reg = (volatile uint32_t*)DMV170_DMA_CONTROL_STATUS_REG;
if ( *dma_control_status_reg & DMV170_SCC_10MHZ )
Console_Port_Tbl[minor].ulClock = Z85C30_CLOCK_10;
else
Console_Port_Tbl[minor].ulClock = Z85C30_CLOCK_2;
return TRUE;
}
boolean dmv177_mc68681_probe(int minor)
{
volatile uint16_t *card_resource_reg;
uint16_t v;
card_resource_reg = (volatile uint16_t*) DMV170_CARD_RESORCE_REG;
v = *card_resource_reg & DMV170_DUART_INST_MASK;
if ( v == DMV170_DUART_INSTALLED )
return TRUE;
return FALSE;
}

112
c/src/lib/libbsp/powerpc/dmv177/console/debugio.c
View File

@@ -1,112 +0,0 @@
/*
* This file contains the debug IO support.
*
* COPYRIGHT (c) 1998 by Radstone Technology
*
*
* THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
* KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
* AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
*
* You are hereby granted permission to use, copy, modify, and distribute
* this file, provided that this notice, plus the above copyright notice
* and disclaimer, appears in all copies. Radstone Technology will provide
* no support for this code.
*
* COPYRIGHT (c) 1989-1997.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
#include <bsp.h>
#include <rtems/libio.h>
#include <stdlib.h>
#include <assert.h>
#include <termios.h>
#include <libchip/serial.h>
/*
* Load configuration table
*/
extern console_data Console_Port_Data[];
extern rtems_device_minor_number Console_Port_Minor;
/* PAGE
*
* DEBUG_puts
*
* This should be safe in the event of an error. It attempts to ensure
* that no TX empty interrupts occur while it is doing polled IO. Then
* it restores the state of that external interrupt.
*
* Input parameters:
* string - pointer to debug output string
*
* Output parameters: NONE
*
* Return values: NONE
*/
void DEBUG_puts(
char *string
)
{
char *s;
uint32_t Irql;
rtems_interrupt_disable(Irql);
for ( s = string ; *s ; s++ ) {
Console_Port_Tbl[Console_Port_Minor].pDeviceFns->
deviceWritePolled(Console_Port_Minor, *s);
}
rtems_interrupt_enable(Irql);
}
/* PAGE
*
* DEBUG_puth
*
* This should be safe in the event of an error. It attempts to ensure
* that no TX empty interrupts occur while it is doing polled IO. Then
* it restores the state of that external interrupt.
*
* Input parameters:
* ulHexNum - value to display
*
* Output parameters: NONE
*
* Return values: NONE
*/
void DEBUG_puth(
uint32_t ulHexNum
)
{
unsigned long i,d;
uint32_t Irql;
void (*poll)(int minor, char cChar);
poll = Console_Port_Tbl[Console_Port_Minor].pDeviceFns->deviceWritePolled;
rtems_interrupt_disable(Irql);
(*poll)(Console_Port_Minor, '0');
(*poll)(Console_Port_Minor, 'x');
for ( i=32 ; i ; ) {
i -= 4;
d = (ulHexNum>>i)&0xf;
(*poll)(Console_Port_Minor, (d<=9) ? d+'0' : d+'a'-0xa);
}
rtems_interrupt_enable(Irql);
}

6
c/src/lib/libbsp/powerpc/dmv177/include/.cvsignore
View File

@@ -1,6 +0,0 @@
coverhd.h
tod.h
bspopts.h
bspopts.h.in
stamp-h
stamp-h.in

150
c/src/lib/libbsp/powerpc/dmv177/include/bsp.h
View File

@@ -1,150 +0,0 @@
/* bsp.h
*
* This include file contains all DY-4 DMV170 board IO definitions.
*
* COPYRIGHT (c) 1989-1997.
* On-Line Applications Research Corporation (OAR).
*
* $Id$
*/
#ifndef __DMV170_BSP_h
#define __DMV170_BSP_h
#ifdef __cplusplus
extern "C" {
#endif
#include <bspopts.h>
/*
* confdefs.h overrides for this BSP:
* - termios serial ports (defaults to 1)
* - Interrupt stack space is not minimum if defined.
*/
#define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 4
#define CONFIGURE_INTERRUPT_STACK_MEMORY (12 * 1024)
#ifdef ASM
/* Definition of where to store registers in alignment handler */
#define ALIGN_REGS 0x0140
#else
#include <rtems.h>
#include <rtems/console.h>
#include <rtems/clockdrv.h>
#include <rtems/console.h>
#include <rtems/iosupp.h>
#include <dmv170.h>
#if 0
#define Enable_Debug() \
DMV170_WRITE( 0xffffbd0c, 0 )
#define Debug_Entry( num ) \
DMV170_WRITE( 0xffffbd06, num )
#else
#define Enable_Debug()
#define Debug_Entry( num )
#endif
/*
* Network driver configuration
*/
struct rtems_bsdnet_ifconfig;
int rtems_dmv177_sonic_driver_attach(struct rtems_bsdnet_ifconfig *config);
#define RTEMS_BSP_NETWORK_DRIVER_NAME "sonic1"
#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_dmv177_sonic_driver_attach
/*
* The following macro calculates the Baud constant. For the Z8530 chip.
*/
#define Z8530_Baud( _frequency, _clock_by, _baud_rate ) \
( (_frequency /( _clock_by * 2 * _baud_rate)) - 2)
/* Constants */
/*
* Device Driver Table Entries
*/
/*
* NOTE: Use the standard Console driver entry
*/
/*
* NOTE: Use the standard Clock driver entry
*/
/*
* Information placed in the linkcmds file.
*/
extern int RAM_START;
extern int RAM_END;
extern int RAM_SIZE;
extern int PROM_START;
extern int PROM_END;
extern int PROM_SIZE;
extern int CLOCK_SPEED;
extern int end; /* last address in the program */
/*
* How many libio files we want
*/
#define BSP_LIBIO_MAX_FDS 20
/* functions */
/*
* genvec.c
*/
rtems_isr_entry set_EE_vector(
rtems_isr_entry handler, /* isr routine */
rtems_vector_number vector /* vector number */
);
void initialize_external_exception_vector ();
/*
* console.c
*/
void DEBUG_puts( char *string );
void BSP_fatal_return( void );
void bsp_start( void );
void bsp_cleanup( void );
rtems_isr_entry set_vector( /* returns old vector */
rtems_isr_entry handler, /* isr routine */
rtems_vector_number vector, /* vector number */
int type /* RTEMS or RAW intr */
);
void BSP_fatal_return( void );
void bsp_spurious_initialize( void );
extern rtems_configuration_table BSP_Configuration; /* owned by BSP */
extern rtems_cpu_table Cpu_table; /* owned by BSP */
extern uint32_t bsp_isr_level;
extern int CPU_PPC_CLICKS_PER_MS;
#endif /* ASM */
#ifdef __cplusplus
}
#endif
#endif
/* end of include file */

284
c/src/lib/libbsp/powerpc/dmv177/include/dmv170.h
View File

@@ -1,284 +0,0 @@
/* dmv170.h
*
* This include file contains information pertaining to the DMV170.
*
* NOTE: Other than where absolutely required, this version currently
* supports only the peripherals and bits used by the basic board
* support package. This includes at least significant pieces of
* the following items:
*
* + UART Channels A and B
*
* COPYRIGHT (c) 1989-1997.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may in
* the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
#ifndef _INCLUDE_DMV170_h
#define _INCLUDE_DMV170_h
/*
* DY-4 uses a non-standard clock for the Exar 88681.
*/
#undef MC68681_BAUD_RATE_MASK_9600
#define MC68681_BAUD_RATE_MASK_9600
#define DMV17x_MC68681_BAUD_RATE_MASK_9600
#if 0
#define MC68681_OFFSET_MULTIPLIER 8
#endif
#ifdef __cplusplus
extern "C" {
#endif
/* Note: Move address defs to the linker files. XXX */
/* Real Time Clock Base Address */
#define DMV170_RTC_ADDRESS 0xf2c00000
/* base address of the DUART (68681) */
#define MC68681_ADDR 0xf2800000
#define MC68681_PORT1_ADDR 0xf2800000
#define MC68681_PORT2_ADDR 0xf2800040
/*
* SONIC Information
*/
#define DMV170_SONIC_ADDR 0xf3000000
#define SONIC_BASE_ADDRESS DMV170_SONIC_ADDR
#define SONIC_VECTOR DMV170_ETHERNET_IRQ
/* base address for the SCC (85C30) */
#define Z85C30_ADDR 0xfb000010
#define Z85C30_CTRL_A 0xfb000010
#define Z85C30_DATA_A 0xfb000018
#define Z85C30_CTRL_B 0xfb000000
#define Z85C30_DATA_B 0xfb000008
#define Z85C30_CLOCK_10 (10485760) /* 10 Mhz */
#define Z85C30_CLOCK_2 (2581175) /* 2.4616 Mhz */
/* base address for the SCV64 */
#define DMV170_SCV64_BASE_ADDRESS 0xf2000000
#define DMV170_LOCAL_CONTROL_STATUS_REG 0xf2400000
#define DMV170_TIMER0_COUNT_INTERVAL_REG 0xf2400008
#define DMV170_TIMER1_COUNT_INTERVAL_REG 0xf2400010
#define DMV170_TIMER2_COUNT_INTERVAL_REG 0xf2400018
#define DMV170_TIMER_CONTROL_REG 0xf2400020
#define DMV170_CARD_RESORCE_REG 0xf2400040
#define DMV170_WRITE( _reg, _data ) \
*((volatile uint16_t*)(_reg)) = (_data)
#define DMV170_READ( _reg, _data ) \
(_data) = *((volatile uint16_t*)(_reg))
/*
* The following defines the bits in the DMA Control and Status Register
*/
/* XXX fill in the other bits */
#define DMV170_DMA_CONTROL_STATUS_REG 0xfc000090
#define DMV170_SCC_10MHZ 0x00010000
/*
* The following defines the bits in the Local Control and Status Register.
*/
#define DMV170_IPLx_MASK 0x0007
#define DMV170_MAXPACK_SENSE_MASK 0x0008
#define DMV170_MAXPACK_NOT_INSTALLED 0x0008
#define DMV170_MAXPACK_INSTALLED 0x0000
#define DMV170_MAXPACK_RESET_MASK 0x0010
#define DMV170_MAXPACK_RESET_NEGATE 0x0010
#define DMV170_MAXPACK_RESET_ASSERT 0x0000
#define DMV170_EEPROM_READ_WRITE_MASK 0x0020
#define DMV170_EEPROM_READ 0x0020
#define DMV170_EEPROM_WRITE 0x0000
#define DMV170_EEPROM_CLOCK_CTRL_MASK 0x0040
#define DMV170_EEPROM_CLOCK_ASSERT 0x0040
#define DMV170_EEPROM_CLOCK_NEGATE 0x0000
#define DMV170_EEPROM_DATA_MASK 0x0080
#define DMV170_EEPROM_DATA_HIGH 0x0080
#define DMV170_EEPROM_DATA_LOW 0x0000
/* Bits 8-10: 68040 Transfer Modifer Codes represent the Transfer
* Modifier to be used on MAXPack Accesses.
*
* Bit 11 : 68040 Transfer Type (TT) 0:TT are both low 1:TT are both high
*/
#define DMV170_USER_LINK0_STATUS_MASK 0x1000
#define DMV170_USER_LINK0_OPEN 0x1000
#define DMV170_USER_LINK0_INSTALLED 0x0000
#define DMV170_LOWER_STATUS_LED_CONTROL_MASK 0x2000
#define DMV170_LOWER_STATUS_LED_IS_OFF 0x2000
#define DMV170_LOWER_STATUS_LED_IS_ON 0x0000
#ifdef DMV176
/* The following are not available for the DMV171 */
#define DMV170_RAM_TYPE_MASK 0x4000
#define DMV170_RAM_TYPE_IS_DRAM 0x4000
#define DMV170_RAM_TYPE_IS_SRAM 0x0000
#define DMV170_IACK_VECTOR_AUTOVECTOR_MASK 0x8000
#define DMV170_IACK_VECTOR_AUTOVECTOR_IS_VECTOR 0x8000
#define DMV170_IACK_VECTOR_AUTOVECTOR_IS_NOT_VECTOR 0x0000
#endif
/*
* The following defines the bits in the Timer Control Register.
*/
#define DMV170_TIMER0_ENABLE_MASK 0x0001
#define DMV170_TIMER0_IS_ENABLED 0x0001
#define DMV170_TIMER0_IS_DISABLED 0x0000
#define DMV170_TIMER1_ENABLE_MASK 0x0002
#define DMV170_TIMER1_IS_ENABLED 0x0002
#define DMV170_TIMER1_IS_DISABLED 0x0000
#define DMV170_TIMER2_ENABLE_MASK 0x0004
#define DMV170_TIMER2_IS_ENABLED 0x0004
#define DMV170_TIMER2_IS_DISABLED 0x0000
#define DMV170_TIMER1_CLOCK_MASK 0x0008
#define DMV170_TIMER1_CLOCK_AT_TIMER0 0x0008
#define DMV170_TIMER1_CLOCK_AT_1MHZ 0x0000
#define DMV170_TIMER2_CLOCK_MASK 0x0010
#define DMV170_TIMER2_CLOCK_AT_TIMER0 0x0010
#define DMV170_TIMER2_CLOCK_AT_1MHZ 0x0000
#define DMV170_TIMER0_INTERRUPT_MASK 0x0020
#define DMV170_TIMER0_INTERRUPT_ENABLE 0x0020
#define DMV170_TIMER0_INTERRUPT_CLEAR 0x0000
#define DMV170_TIMER1_INTERRUPT_MASK 0x0040
#define DMV170_TIMER1_INTERRUPT_ENABLE 0x0040
#define DMV170_TIMER1_INTERRUPT_CLEAR 0x0000
#define DMV170_TIMER2_INTERRUPT_MASK 0x0080
#define DMV170_TIMER2_INTERRUPT_ENABLE 0x0080
#define DMV170_TIMER2_INTERRUPT_CLEAR 0x0000
/*
* The Following define the bits for the Card Resource Register.
*/
#define DMV170_DUART_INTERRUPT_MASK 0x0001 /* DUART Interrupt Sense Bit */
#define DMV170_DUART_INTERRUPT_NEGATE 0x0001
#define DMV170_DUART_INTERRUPT_ASSERT 0x0000
#define DMV170_SONIC_INTERRUPT_MASK 0x0002 /* SONIC Interrupt Sense Bit */
#define DMV170_SONIC_INTERRUPT_NEGATE 0x0002
#define DMV170_SONIC_INTERRUPT_ASSERT 0x0000
#define DMV170_SCSI_INTERRUPT_MASK 0x0004 /* SCSI Interrupt Sense Bit */
#define DMV170_SCSI_INTERRUPT_NEGATE 0x0004
#define DMV170_SCSI_INTERRUPT_ASSERT 0x0000
#define DMV170_SCC_INTERRUPT_MASK 0x0008 /* SCC Interrupt Sense Bit */
#define DMV170_SCC_INTERRUPT_NEGATE 0x0008
#define DMV170_SCC_INTERRUPT_ASSERT 0x0000
#define DMV170_SNOOP_ENABLE_MASK 0x0010 /* CPU Snoop Enable Bit */
#define DMV170_SNOOP_DISABLE 0x0010
#define DMV170_SNOOP_ENABLE 0x0000
#define DMV170_SONIC_RESET_MASK 0x0020 /* SONIC RESET Control */
#define DMV170_SONIC_RESET_CLEAR 0x0020
#define DMV170_SONIC_RESET_HOLD 0x0000
#define DMV170_NV64_WE_MASK 0x0040 /* 64-bit Non-Volital Memory */
#define DMV170_NV64_WRITE_ENABLE 0x0040 /* Write Enable */
#define DMV170_NV64_WRITE_DISABLE 0x0000
#define DMV170_BOOT_NV16_MASK 0x0080 /* BOOT Device Type */
#define DMV170_BOOT_64_BIT 0x0080
#define DMV170_BOOT_16_BIT 0x0000
#define DMV170_DUART_INST_MASK 0x0100 /* DUART Sense Bit */
#define DMV170_DUART_INSTALLED 0x0100
#define DMV170_DUART_NOT_INSTALLED 0x0000
#define DMV170_SONIC_INST_MASK 0x0200 /* SONIC Sense Bit */
#define DMV170_SONIC_INSTALLED 0x0200
#define DMV170_SONIC_NOT_INSTALLED 0x0000
#define DMV170_16M_NV64_MASK 0x0400 /* 16 Mb of 64bit Flash Sense */
#define DMV170_16Mb_FLASH_INSTALLED 0x0400
#define DMV170_8Mb_FLASH_INSTALLED 0x0000
#define DMV170_SCC_INST_MASK 0x0800 /* SCC Sense Bit */
#define DMV170_SCC_INSTALLED 0x0800
#define DMV170_SCC_NOT_INSTALLED 0x0000
#define DMV170_RTC_INST_MASK 0x1000 /* RTC Sense Bit */
#define DMV170_RTC_INSTALLED 0x1000
#define DMV170_RTC_NOT_INSTALLED 0x0000
#define DMV170_NV64_INST_MASK 0x2000 /* 64bit Non-Volital Mem Sense*/
#define DMV170_64_BIT_NON_VOLITAL_MEM_INSTALLED 0x2000
#define DMV170_64_BIT_NON_VOLITAL_MEM_NOT_INSTALLED 0x0000
/*
* DUART Baud Rate Definitions.
*/
#define DMV170_DUART_9621 MC68681_BAUD_RATE_MASK_600 /* close to 9600 */
#define DMV170_RTC_FREQUENCY 0x0000
/*
* CPU General Purpose Interrupt definations (PPC_IRQ_EXTERNAL).
* Note: For the interrupt level read the lower 3 bits of the
* Local Control and Status Register.
*/
#define DMV170_IRQ_FIRST ( PPC_IRQ_LAST + 1 )
#define DMV170_LIRQ0 ( DMV170_IRQ_FIRST + 0 )
#define DMV170_LIRQ1 ( DMV170_IRQ_FIRST + 1 )
#define DMV170_LIRQ2 ( DMV170_IRQ_FIRST + 2 )
#define DMV170_LIRQ3 ( DMV170_IRQ_FIRST + 3 )
#define DMV170_LIRQ4 ( DMV170_IRQ_FIRST + 4 )
#define DMV170_LIRQ5 ( DMV170_IRQ_FIRST + 5 )
#define DMV170_L7IACF ( DMV170_IRQ_FIRST + 6 )
#define DMV170_L7ISYS ( DMV170_IRQ_FIRST + 7 )
#define DMV170_L7IMNI ( DMV170_IRQ_FIRST + 8 )
#define DMV170_BIMODE ( DMV170_IRQ_FIRST + 9 )
#define DMV170_DUART_IRQ DMV170_LIRQ5
#define DMV170_ETHERNET_IRQ DMV170_LIRQ5
#define DMV170_SCSI_IRQ DMV170_LIRQ5
#define DMV170_SCC_IRQ DMV170_LIRQ5
#define DMV170_MEZZANINE_IRQ_0 DMV170_LIRQ4
#define DMV170_TICK_IRQ DMV170_LIRQ3
#define DMV170_LOCATION_MON_IRQ DMV170_LIRQ2
#define DMV170_SCV64_IRQ DMV170_LIRQ1
#define DMV170_RTC_IRQ DMV170_LIRQ0
#define DMV170_ACFAIL_IRQ DMV170_L7IACF
#define DMV170_SYSFAIL_IRQ DMV170_L7ISYS
#define DMV170_WATCHDOG_IRQ DMV170_L7IMNI
#define DMV170_BI_IRQ DMV170_BIMODE
#define DMV170_RAM_PARITY_IRQ ( DMV170_IRQ_FIRST + 10)
#define DMV170_DARF_BUS_ERROR_IRQ ( DMV170_IRQ_FIRST + 11)
#define DMV170_PERIPHERAL_IRQ ( DMV170_IRQ_FIRST + 12)
#define MAX_BOARD_IRQS DMV170_PERIPHERAL_IRQ
#define SCV64_Is_IRQ0( _status ) (_status&0x01)
#define SCV64_Is_IRQ1( _status ) (_status&0x02)
#define SCV64_Is_IRQ2( _status ) (_status&0x04)
#define SCV64_Is_IRQ3( _status ) (_status&0x08)
#define SCV64_Is_IRQ4( _status ) (_status&0x10)
#define SCV64_Is_IRQ5( _status ) (_status&0x20)
/*
* scv64.c
*/
void SCV64_Generate_DUART_Interrupts();
uint32_t SCV64_Get_Interrupt();
uint32_t SCV64_Get_Interrupt_Enable();
#ifdef __cplusplus
}
#endif
#endif /* !_INCLUDE_DMV170_h */
/* end of include file */

53
c/src/lib/libbsp/powerpc/dmv177/include/tm27.h
View File

@@ -1,53 +0,0 @@
/*
* tm27.h
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
#ifndef _RTEMS_TMTEST27
#error "This is an RTEMS internal file you must not include directly."
#endif
#ifndef __tm27_h
#define __tm27_h
/*
* Stuff for Time Test 27
*/
#define MUST_WAIT_FOR_INTERRUPT 1
#define Install_tm27_vector( _handler ) \
set_vector( (_handler), PPC_IRQ_DECREMENTER, 1 )
#define Cause_tm27_intr() \
do { \
uint32_t _clicks = 1; \
asm volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \
} while (0)
#define Clear_tm27_intr() \
do { \
uint32_t _clicks = 0xffffffff; \
uint32_t _msr = 0; \
_ISR_Set_level( 0 ); \
asm volatile( "mfmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \
_msr &= ~0x8000; \
asm volatile( "mtmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \
asm volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \
} while (0)
#define Lower_tm27_intr() \
do { \
uint32_t _msr = 0; \
_ISR_Set_level( 0 ); \
asm volatile( "mfmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \
_msr |= 0x8002; \
asm volatile( "mtmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \
} while (0)
#endif

169
c/src/lib/libbsp/powerpc/dmv177/scv64/scv64.c
View File

@@ -1,169 +0,0 @@
/* scv64.c
*
* This set of routines control the scv64 chip on the DMV177 board.
*
*
* COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994, 1997.
* On-Line Applications Research Corporation (OAR).
*
* $Id$
*/
#include <rtems.h>
#include <bsp.h>
typedef struct {
/* DARF Registers */
volatile uint32_t DMALAR; /* 0x00 */
volatile uint32_t DMAVAR; /* 0x04 */
volatile uint32_t DMATC; /* 0x08 */
volatile uint32_t DCSR; /* 0x0c */
volatile uint32_t VMEBAR; /* 0x10 */
volatile uint32_t RXDATA; /* 0x14 */
volatile uint32_t RXADDR; /* 0x18 */
volatile uint32_t RXCTL; /* 0x1c */
volatile uint32_t BUSSEL; /* 0x20 */
volatile uint32_t IVECT; /* 0x24 */
volatile uint32_t APBR; /* 0x28 */
volatile uint32_t TXDATA; /* 0x2c */
volatile uint32_t TXADDR; /* 0x30 */
volatile uint32_t TXCTL; /* 0x34 */
volatile uint32_t LMFIFO; /* 0x38 */
volatile uint32_t MODE; /* 0x3c */
volatile uint32_t SA64BAR; /* 0x40 */
volatile uint32_t MA64BAR; /* 0x44 */
volatile uint32_t LAG; /* 0x48 */
volatile uint32_t DMAVTC; /* 0x4c */
/* Reserved */
volatile uint32_t reserved_50_7F[12];
/* ACC Registers */
volatile uint8_t STAT0_pad[3]; /* 0x80 */
volatile uint8_t STAT0;
volatile uint8_t STAT1_pad[3]; /* 0x84 */
volatile uint8_t STAT1;
volatile uint8_t GENCTL_pad[3]; /* 0x88 */
volatile uint8_t GENCTL;
volatile uint8_t VINT_pad[3]; /* 0x8c */
volatile uint8_t VINT;
volatile uint8_t VREQ_pad[3]; /* 0x90 */
volatile uint8_t VREQ;
volatile uint8_t VARB_pad[3]; /* 0x94 */
volatile uint8_t VARB;
volatile uint8_t ID_pad[3]; /* 0x98 */
volatile uint8_t ID;
volatile uint8_t NA_pad[3]; /* 0x9c */
volatile uint8_t NA;
volatile uint8_t _7IS_pad[3]; /* 0xa0 */
volatile uint8_t _7IS;
volatile uint8_t LIS_pad[3]; /* 0xa4 */
volatile uint8_t LIS;
volatile uint8_t UIE_pad[3]; /* 0xa8 */
volatile uint8_t UIE;
volatile uint8_t LIE_pad[3]; /* 0xac */
volatile uint8_t LIE;
volatile uint8_t VIE_pad[3]; /* 0xb0 */
volatile uint8_t VIE;
volatile uint8_t IC10_pad[3]; /* 0xb4 */
volatile uint8_t IC10;
volatile uint8_t IC32_pad[3]; /* 0xb8 */
volatile uint8_t IC32;
volatile uint8_t IC54_pad[3]; /* 0xbc */
volatile uint8_t IC54;
/* Utility Registers */
volatile uint32_t MISC;
volatile uint32_t delay_line[3];
volatile uint32_t MBOX0;
volatile uint32_t MBOX1;
volatile uint32_t MBOX2;
volatile uint32_t MBOX3;
} SCV64_Registers;
/*
* LIE Register
*/
#define LOCAL_INTERRUPT_ENABLE_0 0x01
#define LOCAL_INTERRUPT_ENABLE_1 0x02
#define LOCAL_INTERRUPT_ENABLE_2 0x04
#define LOCAL_INTERRUPT_ENABLE_3 0x08
#define LOCAL_INTERRUPT_ENABLE_4 0x10
#define LOCAL_INTERRUPT_ENABLE_5 0x20
/*
* IC54 Register
*/
#define AUTOVECTOR_5 0x80
/*
* Set the registers pointer to the base address of the SCV64
*/
SCV64_Registers *SCV64 = (void *)DMV170_SCV64_BASE_ADDRESS;
/*PAGE
*
* SCV64_Initialize
*
* This routine initializes the SCV64.
*/
void SCV64_Initialize() {
SCV64->LIE = 0;
}
/*PAGE
*
* SCV64_Generate_DUART_Interrupts
*
* This sets the SCV64 to generate duart interrupts for
* the DMV177 board.
*/
void SCV64_Generate_DUART_Interrupts() {
uint8_t data;
/*
* Set Local Interrupt 5 enable
*/
data = SCV64->LIE;
data |= LOCAL_INTERRUPT_ENABLE_5;
SCV64->LIE = data;
/*
* Set Autovector.
*/
data = SCV64->IC54;
data |= AUTOVECTOR_5;
SCV64->IC54 = data;
}
/*PAGE
*
* SCV64_Get_Interrupt
*
* This routine returns the SCV64 status register.
*/
uint32_t SCV64_Get_Interrupt()
{
uint8_t data;
/*
* Put the LIS data into the lower byte of the result
*/
data = SCV64->LIS;
return data;
}
/*PAGE
*
* SCV64_Get_Interrupt_Enable
*
* This routine returns the interrupt enable mask.
*/
uint32_t SCV64_Get_Interrupt_Enable()
{
/*
* Return the set of interrupts enabled.
*/
return SCV64->LIE;
}

114
c/src/lib/libbsp/powerpc/dmv177/sonic/dmvsonic.c
View File

@@ -1,114 +0,0 @@
/*
* DMV177 SONIC Configuration Information
*
* References:
*
* 1) SVME/DMV-171 Single Board Computer Documentation Package, #805905,
* DY 4 Systems Inc., Kanata, Ontario, September, 1996.
*
* $Id$
*/
#include <bsp.h>
#include <rtems/rtems_bsdnet.h>
#include <libchip/sonic.h>
void dmv177_sonic_write_register(
void *base,
uint32_t regno,
uint32_t value
)
{
volatile uint32_t *p = base;
#if (SONIC_DEBUG & SONIC_DEBUG_PRINT_REGISTERS)
printf( "%p Write 0x%04x to %s (0x%02x)\n",
&p[regno], value, SONIC_Reg_name[regno], regno );
fflush( stdout );
#endif
p[regno] = value;
}
uint32_t dmv177_sonic_read_register(
void *base,
uint32_t regno
)
{
volatile uint32_t *p = base;
uint32_t value;
value = p[regno];
#if (SONIC_DEBUG & SONIC_DEBUG_PRINT_REGISTERS)
printf( "%p Read 0x%04x from %s (0x%02x)\n",
&p[regno], value, SONIC_Reg_name[regno], regno );
fflush( stdout );
#endif
return value;
}
/*
* Default sizes of transmit and receive descriptor areas
*/
#define RDA_COUNT 20 /* 20 */
#define TDA_COUNT 20 /* 10 */
/*
* Default device configuration register values
* Conservative, generic values.
* DCR:
* No extended bus mode
* Unlatched bus retry
* Programmable outputs unused
* Asynchronous bus mode
* User definable pins unused
* No wait states (access time controlled by DTACK*)
* 32-bit DMA
* Empty/Fill DMA mode
* Maximum Transmit/Receive FIFO
* DC2:
* Extended programmable outputs unused
* Normal HOLD request
* Packet compress output unused
* No reject on CAM match
*/
#define SONIC_DCR \
(DCR_DW32 | DCR_WAIT0 | DCR_PO0 | DCR_PO1 | DCR_RFT24 | DCR_TFT28)
#ifndef SONIC_DCR
# define SONIC_DCR (DCR_DW32 | DCR_TFT28)
#endif
#ifndef SONIC_DC2
# define SONIC_DC2 (0)
#endif
/*
* Default location of device registers
*/
#ifndef SONIC_BASE_ADDRESS
# define SONIC_BASE_ADDRESS 0xF3000000
# warning "Using default SONIC_BASE_ADDRESS."
#endif
/*
* Default interrupt vector
*/
#ifndef SONIC_VECTOR
# define SONIC_VECTOR 1
# warning "Using default SONIC_VECTOR."
#endif
sonic_configuration_t dmv177_sonic_configuration = {
SONIC_BASE_ADDRESS, /* base address */
SONIC_VECTOR, /* vector number */
SONIC_DCR, /* DCR register value */
SONIC_DC2, /* DC2 register value */
TDA_COUNT, /* number of transmit descriptors */
RDA_COUNT, /* number of receive descriptors */
dmv177_sonic_write_register,
dmv177_sonic_read_register
};
int rtems_dmv177_sonic_driver_attach(struct rtems_bsdnet_ifconfig *config)
{
return rtems_sonic_driver_attach( config, &dmv177_sonic_configuration );
}

120
c/src/lib/libbsp/powerpc/dmv177/start/start.S
View File

@@ -1,120 +0,0 @@
/*
* This is based on the mvme-crt0.S file from libgloss/rs6000.
* crt0.S -- startup file for PowerPC systems.
*
* Copyright (c) 1995 Cygnus Support
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*
* $Id$
*/
#include "ppc-asm.h"
.file "start.s"
.section ".got2","aw"
.align 2
.LCTOC1 = .+32768
.extern FUNC_NAME(atexit)
.globl FUNC_NAME(__atexit)
.section ".sdata","aw"
.align 2
FUNC_NAME(__atexit): /* tell C's eabi-ctor's we have an atexit function */
.long FUNC_NAME(atexit)@fixup /* and that it is to register __do_global_dtors */
.section ".fixup","aw"
.align 2
.long FUNC_NAME(__atexit)
.section ".got2","aw"
.Ltable = .-.LCTOC1
.long .LCTOC1 /* address we think .LCTOC1 is loaded at */
.Lbss_start = .-.LCTOC1
.long __bss_start
.Lend = .-.LCTOC1
.long _end
.Lstack = .-.LCTOC1 /* stack address if set by user */
.long __stack
.text
.Lptr:
.long .LCTOC1-.Laddr
.globl _start
.type _start,@function
_start:
lis r5,0
mr r4,r5
ori r4,r4,0x0000 /* 0x2030 */
mtmsr r4
/* Add special purpose register initialization based upon the console driver
* initialization of these registers XXXXX
*/
bl .Laddr /* get current address */
.Laddr:
mflr r4 /* real address of .Laddr */
lwz r5,(.Lptr-.Laddr)(r4) /* linker generated address of .LCTOC1 */
add r5,r5,r4 /* correct to real pointer */
lwz r4,.Ltable(r5) /* get linker's idea of where .Laddr is */
subf r4,r4,r5 /* calculate difference between where linked and current */
/* clear bss */
lwz r6,.Lbss_start(r5) /* calculate beginning of the BSS */
lwz r7,.Lend(r5) /* calculate end of the BSS */
add r6,r6,r4 /* adjust pointers */
add r7,r7,r4
cmplw 1,r6,r7
bc 4,4,.Ldone
subf r8,r6,r7 /* number of bytes to zero */
srwi r9,r8,2 /* number of words to zero */
mtctr r9
li r0,0 /* zero to clear memory */
addi r6,r6,-4 /* adjust so we can use stwu */
.Lloop:
stwu r0,4(r6) /* zero bss */
bdnz .Lloop
.Ldone:
lwz r0,.Lstack(r5) /* stack address or 0 */
cmplwi 1,r0,0 /* equal to 0? */
bc 12,6,.Lnostack /* use default stack if == 0 */
mr sp,r0 /* use user defined stack */
.Lnostack:
/* set up initial stack frame */
addi sp,sp,-4 /* make sure we don't overwrite debug mem */
lis r0,0
stw r0,0(sp) /* clear back chain */
stwu sp,-56(sp) /* push another stack frame */
lis r5,environ@ha
la r5,environ@l(r5) /* environp */
li r4, 0 /* argv */
li r3, 0 /* argc */
/* Let her rip */
bl FUNC_NAME(boot_card)
/* return value from boot_card is argument to exit */
/* bl FUNC_NAME(exit) */
trap
.Lstart:
.size _start,.Lstart-_start

18
c/src/lib/libbsp/powerpc/dmv177/startup/bspclean.c
View File

@@ -1,18 +0,0 @@
/*
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
void bsp_cleanup( void )
{
#if 0
asm volatile( "li 10,99" ); /* 0x63 */
asm volatile( "sc" );
#endif
}

138
c/src/lib/libbsp/powerpc/dmv177/startup/bspstart.c
View File

@@ -1,138 +0,0 @@
/* bspstart.c
*
* This set of routines starts the application. It includes application,
* board, and monitor specific initialization and configuration.
* The generic CPU dependent initialization has been performed
* before any of these are invoked.
*
* COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994, 1997.
* On-Line Applications Research Corporation (OAR).
*
* $Id$
*/
#include <string.h>
#include <bsp.h>
#include <rtems/libio.h>
#include <rtems/libcsupport.h>
/*
* The original table from the application and our copy of it with
* some changes.
*/
extern rtems_configuration_table Configuration;
rtems_configuration_table BSP_Configuration;
rtems_cpu_table Cpu_table;
uint32_t bsp_isr_level;
/*
* Use the shared implementations of the following routines
*/
void bsp_postdriver_hook(void);
void bsp_libc_init( void *, uint32_t, int );
/*PAGE
*
* bsp_pretasking_hook
*
* BSP pretasking hook. Called just before drivers are initialized.
* Used to setup libc and install any BSP extensions.
*/
void bsp_pretasking_hook(void)
{
extern int end;
uint32_t heap_start;
uint32_t heap_size;
heap_start = (uint32_t) &end;
if (heap_start & (CPU_ALIGNMENT-1))
heap_start = (heap_start + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1);
heap_size = BSP_Configuration.work_space_start - (void *)&end;
heap_size &= 0xfffffff0; /* keep it as a multiple of 16 bytes */
bsp_libc_init((void *) heap_start, heap_size, 0);
#ifdef RTEMS_DEBUG
rtems_debug_enable( RTEMS_DEBUG_ALL_MASK );
#endif
}
/* PAGE
*
* bsp_predriver_hook
*
* Initialization before drivers are setup.
*/
void bsp_predriver_hook(void)
{
initialize_external_exception_vector();
}
/*PAGE
*
* bsp_start
*
* This routine does the bulk of the system initialization.
*/
void bsp_start( void )
{
unsigned char *work_space_start;
unsigned int msr_value = 0x2030;
/*
* Set BSP to initial value. Note: This value is a guess
* check how the real board comes up. This is critical to
* getting the source to work with the debugger.
*/
_CPU_MSR_SET( msr_value );
/*
* Need to "allocate" the memory for the RTEMS Workspace and
* tell the RTEMS configuration where it is. This memory is
* not malloc'ed. It is just "pulled from the air".
*/
work_space_start =
(unsigned char *)&RAM_END - BSP_Configuration.work_space_size;
if ( work_space_start <= (unsigned char *)&end ) {
DEBUG_puts( "bspstart: Not enough RAM!!!\n" );
bsp_cleanup();
}
BSP_Configuration.work_space_start = work_space_start;
/*
* initialize the CPU table for this BSP
*/
Cpu_table.exceptions_in_RAM = TRUE;
Cpu_table.pretasking_hook = bsp_pretasking_hook; /* init libc, etc. */
Cpu_table.predriver_hook = bsp_predriver_hook;
Cpu_table.postdriver_hook = bsp_postdriver_hook;
/* Cpu_table.clicks_per_usec = 66666667 / 4000000; */
Cpu_table.clicks_per_usec = 66666667 / 4000000 / 2;
Cpu_table.do_zero_of_workspace = TRUE;
Cpu_table.interrupt_stack_size = CONFIGURE_INTERRUPT_STACK_MEMORY;
/*
* Enable whatever caching is desired
*/
#if ( DMV177_USE_INSTRUCTION_CACHE )
rtems_cache_enable_instruction();
#endif
#if ( PPC_USE_DATA_CACHE )
rtems_cache_enable_data();
#endif
}

226
c/src/lib/libbsp/powerpc/dmv177/startup/genpvec.c
View File

@@ -1,226 +0,0 @@
/* genpvec.c
*
* These routines handle the external exception. Multiple ISRs occur off
* of this one interrupt. This method will allow multiple ISRs to be
* called using the same IRQ index. However, removing the ISR routines is
* presently not supported.
*
* The external exception vector numbers begin with DMV170_IRQ_FIRST.
* DMV170_IRQ_FIRST is defined to be one greater than the last processor
* interrupt.
*
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may in
* the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
#include <bsp.h>
#include <rtems/chain.h>
#include <assert.h>
#define NUM_LIRQ_HANDLERS 20
#define NUM_LIRQ ( MAX_BOARD_IRQS - PPC_IRQ_LAST )
/*
* Structure to for one of possible multiple interrupt handlers for
* a given interrupt.
*/
typedef struct
{
Chain_Node Node;
rtems_isr_entry handler; /* isr routine */
rtems_vector_number vector; /* vector number */
} EE_ISR_Type;
/*
* Note: The following will not work if we add a method to remove
* handlers at a later time.
*/
EE_ISR_Type ISR_Nodes [NUM_LIRQ_HANDLERS];
uint16_t Nodes_Used;
Chain_Control ISR_Array [NUM_LIRQ];
/*PAGE
*
* external_exception_ISR
*
* This interrupt service routine is called for an External Exception.
*
* Input parameters:
* vector - vector number representing the external exception vector.
*
* Output parameters: NONE
*
* Return values:
*/
rtems_isr external_exception_ISR (
rtems_vector_number vector /* IN */
)
{
uint16_t index;
rtems_boolean is_active=FALSE;
uint32_t scv64_status;
Chain_Node *node;
EE_ISR_Type *ee_isr;
/*
* Get all active interrupts.
*/
scv64_status = SCV64_Get_Interrupt();
scv64_status &= SCV64_Get_Interrupt_Enable();
/*
* Process any set interrupts.
*/
for (index = 0; index <= 5; index++) {
switch(index) {
case 0:
is_active = SCV64_Is_IRQ0( scv64_status );
break;
case 1:
is_active = SCV64_Is_IRQ1( scv64_status );
break;
case 2:
is_active = SCV64_Is_IRQ2( scv64_status );
break;
case 3:
is_active = SCV64_Is_IRQ3( scv64_status );
break;
case 4:
is_active = SCV64_Is_IRQ4( scv64_status );
break;
case 5:
is_active = SCV64_Is_IRQ5( scv64_status );
break;
}
if (is_active) {
/*
* Read vector.
*/
node = ISR_Array[ index ].first;
while ( !_Chain_Is_tail( &ISR_Array[ index ], node ) ) {
ee_isr = (EE_ISR_Type *) node;
(*ee_isr->handler)( ee_isr->vector );
node = node->next;
}
}
}
}
/*PAGE
*
* initialize_external_exception_vector
*
* This routine initializes the external exception vector
*
* Input parameters: NONE
*
* Output parameters: NONE
*
* Return values: NONE
*/
void initialize_external_exception_vector ()
{
int i;
rtems_isr_entry previous_isr;
rtems_status_code status;
extern void SCV64_Initialize( void );
Nodes_Used = 0;
/*
* Initialize the SCV64 chip
*/
SCV64_Initialize();
for (i=0; i <NUM_LIRQ; i++)
Chain_Initialize_empty( &ISR_Array[i] );
/*
* Install external_exception_ISR () as the handler for
* the General Purpose Interrupt.
*/
status = rtems_interrupt_catch( external_exception_ISR,
PPC_IRQ_EXTERNAL , (rtems_isr_entry *) &previous_isr );
}
/*PAGE
*
* set_EE_vector
*
* This routine installs one of multiple ISRs for the general purpose
* inerrupt.
*
* Input parameters:
* handler - handler to call at exception
* vector - vector number associated with this handler.
*
* Output parameters: NONE
*
* Return values:
*/
rtems_isr_entry set_EE_vector(
rtems_isr_entry handler, /* isr routine */
rtems_vector_number vector /* vector number */
)
{
uint16_t vec_idx = vector - DMV170_IRQ_FIRST;
uint32_t index;
/*
* Verify that all of the nodes have not been used.
*/
assert (Nodes_Used < NUM_LIRQ_HANDLERS);
/*
* If we have already installed this handler for this vector, then
* just reset it.
*/
for ( index=0 ; index <= Nodes_Used ; index++ ) {
if ( ISR_Nodes[index].vector == vector &&
ISR_Nodes[index].handler == handler )
return 0;
}
/*
* Increment the number of nedes used and set the index for the node
* array.
*/
Nodes_Used++;
index = Nodes_Used - 1;
/*
* Write the values of the handler and the vector to this node.
*/
ISR_Nodes[index].handler = handler;
ISR_Nodes[index].vector = vector;
/*
* Connect this node to the chain at the location of the
* vector index.
*/
Chain_Append( &ISR_Array[vec_idx], &ISR_Nodes[index].Node );
/*
* Enable the LIRQ interrupt.
*/
SCV64_Generate_DUART_Interrupts();
/*
* No interrupt service routine was removed so return 0
*/
return 0;
}

198
c/src/lib/libbsp/powerpc/dmv177/startup/linkcmds
View File

@@ -1,198 +0,0 @@
OUTPUT_FORMAT("elf32-powerpc", "elf32-powerpc",
"elf32-powerpc")
OUTPUT_ARCH(powerpc)
ENTRY(_start)
/*
* Number of Decrementer countdowns per millisecond
*
* Calculated by: (66.67 Mhz * 1000) / 4 cycles per click
*
PROVIDE(CPU_PPC_CLICKS_PER_MS = 16667);
*/
MEMORY
{
RAM : ORIGIN = 0x41000, LENGTH = 32M
EPROM : ORIGIN = 0xFFF00000, LENGTH = 0x20000
}
SECTIONS
{
/* Read-only sections, merged into text segment: */
/* . = 0x40000 + SIZEOF_HEADERS; */
/* . = 0x1000000;*/
. = 0x41000;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rela.text : { *(.rela.text) }
.rela.data : { *(.rela.data) }
.rela.rodata : { *(.rela.rodata) }
.rela.got : { *(.rela.got) }
.rela.got1 : { *(.rela.got1) }
.rela.got2 : { *(.rela.got2) }
.rela.ctors : { *(.rela.ctors) }
.rela.dtors : { *(.rela.dtors) }
.rela.init : { *(.rela.init) }
.rela.fini : { *(.rela.fini) }
.rela.bss : { *(.rela.bss) }
.rela.plt : { *(.rela.plt) }
.rela.sdata : { *(.rela.sdata2) }
.rela.sbss : { *(.rela.sbss2) }
.rela.sdata2 : { *(.rela.sdata2) }
.rela.sbss2 : { *(.rela.sbss2) }
.plt : { *(.plt) }
.text :
{
*(.text)
*(.gnu.linkonce.t.*)
*(.descriptors)
/*
* Special FreeBSD sysctl sections.
*/
. = ALIGN (16);
__start_set_sysctl_set = .;
*(set_sysctl_*);
__stop_set_sysctl_set = ABSOLUTE(.);
*(set_domain_*);
*(set_pseudo_*);
/* .gnu.warning sections are handled specially by elf32.em. */
*(.gnu.warning)
} >RAM
.init : { _init = .; *(.init) } >RAM
.fini : { _fini = .; *(.fini) } >RAM
.eh_frame : { *.(eh_frame) } >RAM
.rodata : { *(.rodata*) *(.gnu.linkonce.r*) } >RAM
.rodata1 : { *(.rodata1) } >RAM
_etext = .;
PROVIDE (etext = .);
PROVIDE (__SDATA2_START__ = .);
.sdata2 : { *(.sdata2) *(.gnu.linkonce.s2.*) } >RAM
.sbss2 : { *(.sbss2) *(.gnu.linkonce.sb2.*) } >RAM
PROVIDE (__SBSS2_END__ = .);
/* Adjust the address for the data segment. We want to adjust up to
the same address within the page on the next page up. It would
be more correct to do this:
. = ALIGN(0x40000) + (ALIGN(8) & (0x40000 - 1));
The current expression does not correctly handle the case of a
text segment ending precisely at the end of a page; it causes the
data segment to skip a page. The above expression does not have
this problem, but it will currently (2/95) cause BFD to allocate
a single segment, combining both text and data, for this case.
This will prevent the text segment from being shared among
multiple executions of the program; I think that is more
important than losing a page of the virtual address space (note
that no actual memory is lost; the page which is skipped can not
be referenced). */
. = ALIGN(8) + 0x40000;
PROVIDE (sdata = .);
.data :
{
*(.data)
*(.gnu.linkonce.d.*)
CONSTRUCTORS
} >RAM
PROVIDE (__EXCEPT_START__ = .);
.gcc_except_table : { *(.gcc_except_table) } >RAM
PROVIDE (__EXCEPT_END__ = .);
.data1 : { *(.data1) } >RAM
.got1 : { *(.got1) } >RAM
.dynamic : { *(.dynamic) } >RAM
/* Put .ctors and .dtors next to the .got2 section, so that the pointers
get relocated with -mrelocatable. Also put in the .fixup pointers.
The current compiler no longer needs this, but keep it around for 2.7.2 */
PROVIDE (_GOT2_START_ = .);
PROVIDE (__GOT2_START__ = .);
.got2 : { *(.got2) } >RAM
PROVIDE (_GOT2_END_ = .);
PROVIDE (__GOT2_END__ = .);
PROVIDE (__CTOR_LIST__ = .);
.ctors : { *(.ctors) } >RAM
PROVIDE (__CTOR_END__ = .);
PROVIDE (__DTOR_LIST__ = .);
.dtors : { *(.dtors) } >RAM
PROVIDE (__DTOR_END__ = .);
PROVIDE (_FIXUP_START_ = .);
PROVIDE (__FIXUP_START__ = .);
.fixup : { *(.fixup) } >RAM
PROVIDE (_FIXUP_END_ = .);
PROVIDE (__FIXUP_END__ = .);
PROVIDE (_GOT2_END_ = .);
PROVIDE (_GOT_START_ = .);
s.got = .;
.got : { *(.got) } >RAM
.got.plt : { *(.got.plt) } >RAM
PROVIDE (_GOT_END_ = .);
PROVIDE (__GOT_END__ = .);
/* We want the small data sections together, so single-instruction offsets
can access them all, and initialized data all before uninitialized, so
we can shorten the on-disk segment size. */
PROVIDE (__SDATA_START__ = .);
.sdata : { *(.sdata) *(.gnu.linkonce.s.*) } >RAM
_edata = .;
PROVIDE (edata = .);
PROVIDE (RAM_END = 4M);
.sbss :
{
PROVIDE (__sbss_start = .);
*(.sbss)
*(.scommon)
PROVIDE (__sbss_end = .);
} >RAM
PROVIDE (__SBSS_END__ = .);
.bss :
{
PROVIDE (__bss_start = .);
*(.dynbss)
*(.bss)
*(COMMON)
} >RAM
. = ALIGN(8) + 0x8000;
PROVIDE (__stack = .);
_end = . ;
PROVIDE (end = .);
/* These are needed for ELF backends which have not yet been
converted to the new style linker. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
/* These must appear regardless of . */
}

56
c/src/lib/libbsp/powerpc/dmv177/startup/setvec.c
View File

@@ -1,56 +0,0 @@
/* set_vector
*
* This routine installs an interrupt vector on the target Board/CPU.
* This routine is allowed to be as board dependent as necessary.
*
* INPUT:
* handler - interrupt handler entry point
* vector - vector number
* type - 0 indicates raw hardware connect
* 1 indicates RTEMS interrupt connect
*
* RETURNS:
* address of previous interrupt handler
*
* COPYRIGHT (c) 1989-1997.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may in
* the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
#include <rtems.h>
#include <bsp.h>
/*PAGE
*
* set_vector
*
* This routine installs an interrupt handler for vector.
*/
rtems_isr_entry set_vector( /* returns old vector */
rtems_isr_entry handler, /* isr routine */
rtems_vector_number vector, /* vector number */
int type /* RTEMS or RAW intr */
)
{
rtems_isr_entry previous_isr;
rtems_status_code status;
/*
* vectors greater than PPC603e_IRQ_LAST are handled by the General purpose
* interupt handler.
*/
if ( vector > PPC_IRQ_LAST ) {
set_EE_vector ( handler, vector );
}
else {
status = rtems_interrupt_catch(
handler, vector, (rtems_isr_entry *) &previous_isr );
}
return previous_isr;
}

83
c/src/lib/libbsp/powerpc/dmv177/startup/vmeintr.c
View File

@@ -1,83 +0,0 @@
/* vmeintr.c
*
* VMEbus support routines for the DMV170.
*
* COPYRIGHT (c) 1989-1997.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may in
* the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
#include <rtems.h>
#include <bsp.h>
#include <rtems/vmeintr.h>
/* PAGE
*
* VME_interrupt_Disable
*
* This routine disables vme interupts
*
* Input parameters:
* mask - interupt mask
*
* Output parameters: NONE
*
* Return values: NONE
*/
void VME_interrupt_Disable (
VME_interrupt_Mask mask /* IN */
)
{
volatile uint8_t *VME_interrupt_enable;
uint8_t value;
#if 0
VME_interrupt_enable = ACC_VIE;
#else
VME_interrupt_enable = 0;
#endif
value = *VME_interrupt_enable;
value &= ~mask; /* turn off interrupts for all levels in mask */
*VME_interrupt_enable = value;
}
/* PAGE
*
* VME_interrupt_Enable
*
* This routine enables vme interupts
*
* Input parameters:
* mask - interupt mask
*
* Output parameters: NONE
*
* Return values:
*/
void VME_interrupt_Enable (
VME_interrupt_Mask mask /* IN */
)
{
volatile uint8_t *VME_interrupt_enable;
uint8_t value;
#if 0
VME_interrupt_enable = ACC_VIE;
#else
VME_interrupt_enable = 0;
#endif
value = *VME_interrupt_enable;
value |= mask; /* turn on interrupts for all levels in mask */
*VME_interrupt_enable = value;
}

130
c/src/lib/libbsp/powerpc/dmv177/timer/timer.c
View File

@@ -1,130 +0,0 @@
/* timer.c
*
* This file implements a benchmark timer using the General Purpose Timer on
* the MEC.
*
* The license and distribution terms for this file are in
* the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
#include <assert.h>
#include <bsp.h>
uint64_t Timer_driver_Start_time;
rtems_boolean Timer_driver_Find_average_overhead;
/*PAGE
*
* Timer_initialize
*
* This routine initializes the timer.
*
* Input parameters: NONE
*
* Output parameters: NONE
*
* Return values: NONE
*
*/
void Timer_initialize()
{
/*
* Timer runs long and accurate enough not to require an interrupt.
*/
Timer_driver_Start_time = PPC_Get_timebase_register();
}
#define AVG_OVERHEAD 24 /* It typically takes 24 instructions */
/* to start/stop the timer. */
#define LEAST_VALID 1 /* Don't trust a value lower than this */
/* PAGE
*
* Read_timer
*
* This routine reads the timer.
*
* Input parameters: NONE
*
* Output parameters: NONE
*
* Return values: timer in ms units
*
*/
int Read_timer()
{
uint64_t clicks;
uint64_t total64;
uint32_t total;
/* approximately CLOCK_SPEED clicks per microsecond */
clicks = PPC_Get_timebase_register();
assert( clicks > Timer_driver_Start_time );
total64 = clicks - Timer_driver_Start_time;
assert( total64 <= 0xffffffff ); /* fits into a uint32_t */
total = (uint32_t) total64;
if ( Timer_driver_Find_average_overhead == 1 )
return total; /* in one microsecond units */
if ( total < LEAST_VALID )
return 0; /* below timer resolution */
return total - AVG_OVERHEAD;
}
/* PAGE
*
* Empty_function
*
* This routine is called during the idle loop.
*
* Input parameters: NONE
*
* Output parameters:
* status code of successful
*
* Return values: NONE
*
*/
rtems_status_code Empty_function( void )
{
return RTEMS_SUCCESSFUL;
}
/* PAGE
*
* Set_find_average_overhead
*
* This routine sets a global boolean to the value passed in.
*
* Input parameters:
* find_flag - flag to indicate to find the average overhead.
*
* Output parameters: NONE
*
* Return values: NONE
*
*/
void Set_find_average_overhead(
rtems_boolean find_flag
)
{
Timer_driver_Find_average_overhead = find_flag;
}

191
c/src/lib/libbsp/powerpc/dmv177/times
View File

@@ -1,191 +0,0 @@
#
# Timing Test Suite Results for the DY-4 DMV177
#
# $Id$
#
Board: DY-4 DMV177
CPU: PPC 603e
Clock Speed: 100 Mhz
Memory Configuration: 32 Mbyte DRAM
Wait States: XXX
Times Reported in: cycles
Timer Source: on-CPU General Purpose Count Down Timer
Column A: 4.0.0-lmco
Column B: unused
# DESCRIPTION A B
== ================================================================= ==== ====
1 rtems_semaphore_create 571
rtems_semaphore_delete 575
rtems_semaphore_obtain: available 414
rtems_semaphore_obtain: not available -- NO_WAIT 414
rtems_semaphore_release: no waiting tasks 501
2 rtems_semaphore_obtain: not available -- caller blocks 1254
3 rtems_semaphore_release: task readied -- preempts caller 982
4 rtems_task_restart: blocked task -- preempts caller 1640
rtems_task_restart: ready task -- preempts caller 1601
rtems_semaphore_release: task readied -- returns to caller 636
rtems_task_create 2301
rtems_task_start 794
rtems_task_restart: suspended task -- returns to caller 906
rtems_task_delete: suspended task 1555
rtems_task_restart: ready task -- returns to caller 928
rtems_task_restart: blocked task -- returns to caller 1102
rtems_task_delete: blocked task 1609
5 rtems_task_suspend: calling task 960
rtems_task_resume: task readied -- preempts caller 803
6 rtems_task_restart: calling task 1137
rtems_task_suspend: returns to caller 433
rtems_task_resume: task readied -- returns to caller 451
rtems_task_delete: ready task 1620
7 rtems_task_restart: suspended task -- preempts caller 1483
8 rtems_task_set_priority: obtain current priority 368
rtems_task_set_priority: returns to caller 633
rtems_task_mode: obtain current mode 184
rtems_task_mode: no reschedule 213
rtems_task_mode: reschedule -- returns to caller 247
rtems_task_mode: reschedule -- preempts caller 919
rtems_task_set_note 383
rtems_task_get_note 382
rtems_clock_set 792
rtems_clock_get 78
9 rtems_message_queue_create 2270
rtems_message_queue_send: no waiting tasks 923
rtems_message_queue_urgent: no waiting tasks 919
rtems_message_queue_receive: available 755
rtems_message_queue_flush: no messages flushed 369
rtems_message_queue_flush: messages flushed 431
rtems_message_queue_delete 708
10 rtems_message_queue_receive: not available -- NO_WAIT 467
rtems_message_queue_receive: not available -- caller blocks 1283
11 rtems_message_queue_send: task readied -- preempts caller 1322
12 rtems_message_queue_send: task readied -- returns to caller 955
13 rtems_message_queue_urgent: task readied -- preempts caller 1322
14 rtems_message_queue_urgent: task readied -- returns to caller 955
15 rtems_event_receive: obtain current events 43
rtems_event_receive: not available -- NO_WAIT 331
rtems_event_receive: not available -- caller blocks 1043
rtems_event_send: no task readied 354
rtems_event_receive: available 357
rtems_event_send: task readied -- returns to caller 571
16 rtems_event_send: task readied -- preempts caller 946
17 rtems_task_set_priority: preempts caller 1211
18 rtems_task_delete: calling task 2117
19 rtems_signal_catch 267
rtems_signal_send: returns to caller 408
rtems_signal_send: signal to self 607
exit ASR overhead: returns to calling task 464
exit ASR overhead: returns to preempting task 752
20 rtems_partition_create 762
rtems_region_create 614
rtems_partition_get_buffer: available 394
rtems_partition_get_buffer: not available 376
rtems_partition_return_buffer 420
rtems_partition_delete 426
rtems_region_get_segment: available 515
rtems_region_get_segment: not available -- NO_WAIT 472
rtems_region_return_segment: no waiting tasks 544
rtems_region_get_segment: not available -- caller blocks 1345
rtems_region_return_segment: task readied -- preempts caller 1296
rtems_region_return_segment: task readied -- returns to caller 935
rtems_region_delete 425
rtems_io_initialize 52
rtems_io_open 42
rtems_io_close 44
rtems_io_read 42
rtems_io_write 44
rtems_io_control 42
21 rtems_task_ident 2900
rtems_message_queue_ident 2828
rtems_semaphore_ident 3243
rtems_partition_ident 2828
rtems_region_ident 2878
rtems_port_ident 2828
rtems_timer_ident 2828
rtems_rate_monotonic_ident 2826
22 rtems_message_queue_broadcast: task readied -- returns to caller 1079
rtems_message_queue_broadcast: no waiting tasks 589
rtems_message_queue_broadcast: task readied -- preempts caller 1435
23 rtems_timer_create 357
rtems_timer_fire_after: inactive 607
rtems_timer_fire_after: active 646
rtems_timer_cancel: active 378
rtems_timer_cancel: inactive 339
rtems_timer_reset: inactive 552
rtems_timer_reset: active 591
rtems_timer_fire_when: inactive 766
rtems_timer_fire_when: active 764
rtems_timer_delete: active 471
rtems_timer_delete: inactive 432
rtems_task_wake_when 1275
24 rtems_task_wake_after: yield -- returns to caller 245
rtems_task_wake_after: yields -- preempts caller 851
25 rtems_clock_tick 214
26 _ISR_Disable 24
_ISR_Flash 21
_ISR_Enable 19
_Thread_Disable_dispatch 27
_Thread_Enable_dispatch 211
_Thread_Set_state 177
_Thread_Disptach (NO FP) 761
context switch: no floating point contexts 585
context switch: self 230
context switch: to another task 236
context switch: restore 1st FP task 730
fp context switch: save idle, restore idle 478
fp context switch: save idle, restore initialized 828
fp context switch: save initialized, restore initialized 478
_Thread_Resume 143
_Thread_Unblock 143
_Thread_Ready 147
_Thread_Get 93
_Semaphore_Get 77
_Thread_Get: invalid id 20
27 interrupt entry overhead: returns to interrupted task 206
interrupt exit overhead: returns to interrupted task 213
interrupt entry overhead: returns to nested interrupt 201
interrupt exit overhead: returns to nested interrupt 186
interrupt entry overhead: returns to preempting task 202
interrupt exit overhead: returns to preempting task 857
28 rtems_port_create 428
rtems_port_external_to_internal 339
rtems_port_internal_to_external 339
rtems_port_delete 421
29 rtems_rate_monotonic_create 388
rtems_rate_monotonic_period: initiate period -- returns to caller 556
rtems_rate_monotonic_period: obtain status 377
rtems_rate_monotonic_cancel 427
rtems_rate_monotonic_delete: inactive 465
rtems_rate_monotonic_delete: active 519
rtems_rate_monotonic_period: conclude periods -- caller blocks 843

77
c/src/lib/libbsp/powerpc/dmv177/tod/todcfg.c
View File

@@ -1,77 +0,0 @@
/*
* This file contains the RTC driver table for the DY-4 DMV177.
*
* COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994, 1997.
* On-Line Applications Research Corporation (OAR).
*
* $Id$
*/
#include <bsp.h>
#include <libchip/rtc.h>
#include <libchip/icm7170.h>
/*
* Configuration specific probe routines
*
* NOTE: There are no DMV177 specific configuration routines. These
* routines could be written to dynamically determine what type
* of real-time clock is on this board. This would be useful for
* a BSP supporting multiple board models.
*/
/* NONE CURRENTLY PROVIDED */
/*
* The following table configures the RTC drivers used in this BSP.
*
* The first entry which, when probed, is available, will be named /dev/rtc,
* all others being given the name indicated.
*/
boolean dmv177_icm7170_probe(int minor);
rtc_tbl RTC_Table[] = {
{
"/dev/rtc0", /* sDeviceName */
RTC_ICM7170, /* deviceType */
&icm7170_fns, /* pDeviceFns */
dmv177_icm7170_probe, /* deviceProbe */
(void *) ICM7170_AT_1_MHZ, /* pDeviceParams */
DMV170_RTC_ADDRESS, /* ulCtrlPort1 */
0, /* ulDataPort */
icm7170_get_register_8, /* getRegister */
icm7170_set_register_8, /* setRegister */
}
};
/*
* Declare some information used by the RTC driver
*/
#define NUM_RTCS (sizeof(RTC_Table)/sizeof(rtc_tbl))
size_t RTC_Count = NUM_RTCS;
rtems_device_minor_number RTC_Minor;
/*
* Hopefully, by checking the card resource register, this BSP
* will be able to operate on the DMV171, DMV176, or DMV177.
*/
boolean dmv177_icm7170_probe(int minor)
{
volatile uint16_t *card_resource_reg;
uint16_t v;
card_resource_reg = (volatile uint16_t*) DMV170_CARD_RESORCE_REG;
v = *card_resource_reg & DMV170_RTC_INST_MASK;
if ( v == DMV170_RTC_INSTALLED )
return TRUE;
return FALSE;
}

14
c/src/lib/libbsp/powerpc/ppcn_60x/.cvsignore
View File

@@ -1,14 +0,0 @@
aclocal.m4
autom4te*.cache
config.cache
config.guess
config.log
config.status
config.sub
configure
depcomp
install-sh
Makefile
Makefile.in
missing
mkinstalldirs

520
c/src/lib/libbsp/powerpc/ppcn_60x/ChangeLog
View File

@@ -1,520 +0,0 @@
2005-04-26 Joel Sherrill <joel@OARcorp.com>
* clock/clock.c: Eliminate warning for duplicate definition of
PPC_Set_decrementer.
2005-03-04 Joel Sherrill <joel@OARcorp.com>
* include/bsp.h, pci/pci.c, startup/bspstart.c: Make PCI initialize
function part of the unified PCI API as pci_initialize().
2005-02-16 Ralf Corsepius <ralf.corsepius@rtems.org>
* configure.ac: Remove argument from RTEMS_PPC_EXCEPTIONS.
2005-02-14 Ralf Corsepius <ralf.corsepius@rtems.org>
* startup/spurious.c: Merge ppc603 and ppc603e.
Remove digits (Unused).
2005-02-12 Ralf Corsepius <ralf.corsepius@rtems.org>
* Makefile.am: Fix typo in previous patch.
2005-02-11 Ralf Corsepius <ralf.corsepius@rtems.org>
* Makefile.am: Merge-in wrapup/Makefile.am.
* wrapup/Makefile.am: Remove.
* configure.ac: Reflect changes above.
2005-02-10 Ralf Corsepius <ralf.corsepius@rtems.org>
* vectors/vectors.S: Remove PPC_ABI_POWEROPEN.
2005-02-09 Ralf Corsepius <ralf.corsepius@rtems.org>
* vectors/vectors.S: Remove PPC_ABI_GCC27.
2005-02-09 Ralf Corsepius <ralf.corsepius@rtems.org>
* vectors/vectors.S: Remove XCOFF support.
2005-01-18 Ralf Corsepius <ralf.corsepius@rtems.org>
* Makefile.am: Use ../../shared/tod.h instead of include/tod.h.
* console/config.c: Remove typos from 2005-01-04 changes.
* include/tod.h: Remove.
2005-01-07 Ralf Corsepius <ralf.corsepius@rtems.org>
* Makefile.am: Eliminate CFLAGS_OPTIMIZE_V.
2005-01-04 Joel Sherrill <joel@OARcorp.com>
* console/config.c: Remove warnings.
2005-01-02 Ralf Corsepius <ralf.corsepius@rtems.org>
* Makefile.am, wrapup/Makefile.am: Remove build-variant support.
2004-09-24 Ralf Corsepius <ralf_corsepius@rtems.org>
* configure.ac: Require automake > 1.9.
2004-04-23 Ralf Corsepius <ralf_corsepius@rtems.org>
PR 610/bsps
* Makefile.am: Add include/tm27.h, Cosmetics.
* include/tm27.h: Final cosmetics.
2004-04-22 Ralf Corsepius <ralf_corsepius@rtems.org>
* include/bsp.h: Split out tmtest27 support.
* include/tm27.h: New.
2004-04-21 Ralf Corsepius <ralf_corsepius@rtems.org>
PR 613/bsps
* include/bsp.h: Remove MAX_LONG_TEST_DURATION.
2004-04-21 Ralf Corsepius <ralf_corsepius@rtems.org>
PR 614/bsps
* include/bsp.h: Remove MAX_SHORT_TEST_DURATION (Unused).
2004-04-02 Ralf Corsepius <ralf_corsepius@rtems.org>
* vectors/align_h.S: Include <rtems/asm.h> instead of <asm.h>.
* vectors/vectors.S: Include <rtems/asm.h> instead of <asm.h>.
2004-04-01 Ralf Corsepius <ralf_corsepius@rtems.org>
* startup/genpvec.c: Include <rtems/chain.h> instead of <chain.h>.
* include/bsp.h: Include <rtems/clockdrv.h> instead of <clockdrv.h>.
* include/bsp.h: Include <rtems/console.h> instead of <console.h>.
* include/bsp.h: Include <rtems/iosupp.h> instead of <iosupp.h>.
* console/i8042.c: Include <rtems/ringbuf.h> instead of <ringbuf.h>.
* console/console.h: Include <rtems/ringbuf.h> instead of <ringbuf.h>.
2004-03-31 Ralf Corsepius <ralf_corsepius@rtems.org>
* clock/clock.c, console/config.c, console/console.c,
console/debugio.c, console/i8042.c, console/ns16550cfg.c,
console/ns16550cfg.h, console/vga.c, console/vga_p.h,
console/z85c30cfg.c, console/z85c30cfg.h, include/bsp.h,
include/nvram.h, include/pci.h, network/amd79c970.c,
network/amd79c970.h, nvram/mk48t18.h, nvram/nvram.c,
nvram/stk11c68.h, pci/pci.c, startup/bspstart.c, startup/genpvec.c,
startup/spurious.c, startup/swap.c, timer/timer.c, tod/cmos.h,
tod/tod.c, universe/universe.c: Convert to using c99 fixed size
types.
2004-02-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: Reflect changes to bsp.am.
Preinstall dist_project_lib*.
2004-02-14 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: Reflect changes to bsp.am.
2004-02-12 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: Use CPPASCOMPILE instead of CCASCOMPILE.
2004-02-06 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* wrapup/Makefile.am: Convert to automake-building rules.
2004-01-31 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: Merge-in clock/Makefile.am, console/Makefile.am,
network/Makefile.am, nvram/Makefile.am, pci/Makefile.am,
startup/Makefile.am, timer/Makefile.am, tod/Makefile.am,
universe/Makefile.am, vectors/Makefile.am. Use automake compilation
rules.
* clock/Makefile.am, console/Makefile.am, network/Makefile.am,
nvram/Makefile.am, pci/Makefile.am, startup/Makefile.am,
timer/Makefile.am, tod/Makefile.am, universe/Makefile.am,
vectors/Makefile.am: Remove.
* configure.ac: Reflect changes above.
* wrapup/Makefile.am: Reflect changes above.
2004-01-30 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: Merge-in start/Makefile.am.
* start/Makefile.am: Remove.
* configure.ac: Reflect changes above.
2004-01-30 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* wrapup/Makefile.am: Reflect changes to
../support/*exception_processing/*.
2004-01-28 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* configure.ac: Add nostdinc to AUTOMAKE_OPTIONS.
Add RTEMS_PROG_CCAS.
2004-01-21 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: Add PREINSTALL_DIRS.
* wrapup/Makefile.am: Reflect changes to libcpu.
2004-01-14 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: Re-add dirstamps to PRE/TMPINSTALL_FILES.
Add PRE/TMPINSTALL_FILES to CLEANFILES.
* start/Makefile.am: Ditto.
* startup/Makefile.am: Ditto.
2004-01-05 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* wrapup/Makefile.am: Eliminate $(LIB).
Use noinst_DATA to trigger building libbsp.a.
2003-12-30 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* startup/Makefile.am: Cosmetics.
2003-12-22 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* clock/Makefile.am: Eliminate VPATH.
* console/Makefile.am: Eliminate VPATH.
* network/Makefile.am: Eliminate VPATH.
* nvram/Makefile.am: Eliminate VPATH.
* pci/Makefile.am: Eliminate VPATH.
* start/Makefile.am: Eliminate VPATH.
* startup/Makefile.am: Eliminate VPATH.
* timer/Makefile.am: Eliminate VPATH.
* tod/Makefile.am: Eliminate VPATH.
* universe/Makefile.am: Eliminate VPATH.
* vectors/Makefile.am: Eliminate VPATH.
2003-12-13 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* start/Makefile.am: s,${PROJECT_RELEASE}/lib,$(PROJECT_LIB),g.
* startup/Makefile.am: s,${PROJECT_RELEASE}/lib,$(PROJECT_LIB),g.
2003-12-12 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* start/Makefile.am: Use mkdir_p. Remove dirs from PRE/TMPINSTALL_FILES.
* startup/Makefile.am: Use mkdir_p. Remove dirs from PRE/TMPINSTALL_FILES.
2003-12-12 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* configure.ac: Require automake >= 1.8, autoconf >= 2.59.
2003-12-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* start/Makefile.am: Misc cleanups and fixes.
* startup/Makefile.am: Misc cleanups and fixes.
* wrapup/Makefile.am: Misc cleanups and fixes.
2003-12-03 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: Add preinstallation dirstamp support.
* clock/Makefile.am: Cosmetics.
* console/Makefile.am: Cosmetics.
* network/Makefile.am: Cosmetics.
* nvram/Makefile.am: Cosmetics.
* pci/Makefile.am: Cosmetics.
* startup/Makefile.am: Cosmetics.
* timer/Makefile.am: Cosmetics.
* tod/Makefile.am: Cosmetics.
* universe/Makefile.am: Cosmetics.
* vectors/Makefile.am: Cosmetics.
* wrapup/Makefile.am: Cosmetics.
2003-12-02 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* clock/Makefile.am: Remove all-local: $(ARCH).
* console/Makefile.am: Remove all-local: $(ARCH).
* network/Makefile.am: Remove all-local: $(ARCH).
* nvram/Makefile.am: Remove all-local: $(ARCH).
* pci/Makefile.am: Remove all-local: $(ARCH).
* start/Makefile.am: Remove all-local: $(ARCH).
* startup/Makefile.am: Remove all-local: $(ARCH).
* timer/Makefile.am: Remove all-local: $(ARCH).
* tod/Makefile.am: Remove all-local: $(ARCH).
* universe/Makefile.am: Remove all-local: $(ARCH).
* vectors/Makefile.am: Remove all-local: $(ARCH).
* wrapup/Makefile.am: Remove all-local: $(ARCH).
2003-09-29 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: Merge-in include/Makefile.am.
Reflect changes to bsp.am.
* include/Makefile.am: Remove.
* configure.ac: Reflect changes above.
2003-09-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* bsp_specs: Remove *lib:.
2003-09-04 Joel Sherrill <joel@OARcorp.com>
* clock/clock.c, console/console.c, console/debugio.c,
console/ns16550cfg.c, console/ns16550cfg.h, console/z85c30cfg.c,
console/z85c30cfg.h, include/tod.h, startup/bspstart.c,
startup/genpvec.c, startup/rtems-ctor.cc, startup/setvec.c,
timer/timer.c: URL for license changed.
2003-09-04 Joel Sherrill <joel@OARcorp.com>
* console/vga.c, universe/universe.c: Removed incorrect statement about
copyright assignment.
2003-08-18 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: Reflect having moved aclocal/.
2003-08-16 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: Reflect having moved automake/.
* clock/Makefile.am: Reflect having moved automake/.
* console/Makefile.am: Reflect having moved automake/.
* include/Makefile.am: Reflect having moved automake/.
* network/Makefile.am: Reflect having moved automake/.
* nvram/Makefile.am: Reflect having moved automake/.
* pci/Makefile.am: Reflect having moved automake/.
* start/Makefile.am: Reflect having moved automake/.
* startup/Makefile.am: Reflect having moved automake/.
* timer/Makefile.am: Reflect having moved automake/.
* tod/Makefile.am: Reflect having moved automake/.
* universe/Makefile.am: Reflect having moved automake/.
* vectors/Makefile.am: Reflect having moved automake/.
* wrapup/Makefile.am: Reflect having moved automake/.
2003-08-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* configure.ac: Use rtems-bugs@rtems.com as bug report email address.
2003-08-06 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
PR 445/bsps
* bsp_specs: Remove -D__embedded__ -Asystem(embedded) from cpp.
Remove cpp, old_cpp (now unused).
2003-03-06 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* configure.ac: Remove AC_CONFIG_AUX_DIR.
2003-02-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* configure.ac: AM_INIT_AUTOMAKE([1.7.2]).
2003-02-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* configure.ac: AC_PREREQ(2.57).
2003-01-20 Joel Sherrill <joel@OARcorp.com>
* startup/linkcmds*: Add FreeBSD sysctl() sections.
2002-12-17 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* clock/Makefile.am: Don't include @RTEMS_BSP@.cfg.
* console/Makefile.am: Don't include @RTEMS_BSP@.cfg.
* network/Makefile.am: Don't include @RTEMS_BSP@.cfg.
* nvram/Makefile.am: Don't include @RTEMS_BSP@.cfg.
* pci/Makefile.am: Don't include @RTEMS_BSP@.cfg.
* start/Makefile.am: Don't include @RTEMS_BSP@.cfg.
* startup/Makefile.am: Don't include @RTEMS_BSP@.cfg.
* timer/Makefile.am: Don't include @RTEMS_BSP@.cfg.
* tod/Makefile.am: Don't include @RTEMS_BSP@.cfg.
* universe/Makefile.am: Don't include @RTEMS_BSP@.cfg.
* vectors/Makefile.am: Don't include @RTEMS_BSP@.cfg.
2002-12-12 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* start/Makefile.am: Use install-data-local to install startfile.
2002-12-10 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* wrapup/Makefile.am: Don't include @RTEMS_BSP@.cfg.
2002-11-04 Joel Sherrill <joel@OARcorp.com>
* console/i8042.c: Removed warnings.
2002-10-21 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* .cvsignore: Reformat.
Add autom4te*cache.
Remove autom4te.cache.
2002-08-21 Joel Sherrill <joel@OARcorp.com>
* bsp_specs: Added support for -nostdlibs.
2002-08-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* clock/Makefile.am: Use .$(OBJEXT) instead of .o.
* console/Makefile.am: Use .$(OBJEXT) instead of .o.
* network/Makefile.am: Use .$(OBJEXT) instead of .o.
* nvram/Makefile.am: Use .$(OBJEXT) instead of .o.
* pci/Makefile.am: Use .$(OBJEXT) instead of .o.
* start/Makefile.am: Use .$(OBJEXT) instead of .o.
* startup/Makefile.am: Use .$(OBJEXT) instead of .o.
* timer/Makefile.am: Use .$(OBJEXT) instead of .o.
* tod/Makefile.am: Use .$(OBJEXT) instead of .o.
* universe/Makefile.am: Use .$(OBJEXT) instead of .o.
* vectors/Makefile.am: Use .$(OBJEXT) instead of .o.
* wrapup/Makefile.am: Use .$(OBJEXT) instead of .o.
2002-07-21 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* start/Makefile.am: Eliminate PGM.
Add bsplib_DATA = $(PROJECT_RELEASE)/lib/start$(LIB_VARIANT).o.
2002-07-20 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* startup/Makefile.am: Add bsplib_DATA = linkcmds.
2002-07-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* wrapup/Makefile.am: Eliminate TMPINSTALL_FILES.
Remove $(OBJS) from all-local.
2002-06-29 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* wrapup/Makefile.am: Remove preinstallation of libbsp.a,
2001-05-09 Joel Sherrill <joel@OARcorp.com>
* startup/linkcmds: In support of gcc 3.1, added one of more
of the sections .jcr, .rodata*, .data.*, .gnu.linkonce.s2.*,
.gnu.linkonce.sb2.*, and .gnu.linkonce.s.*. Spacing corrections
and direction of segments to memory regions may also have been
addressed. This was a sweep across all BSPs.
2002-04-22 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* startup/spurious.c: Use defined(mpc604) instead of defined(ppc604).
2002-04-18 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* start/start.S: remove targopts.h.
2001-04-08 Joel Sherrill <joel@OARcorp.com>
* startup/linkcmds: Per PR170, PR171, and PR172 add .eh_frame
2002-03-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* configure.ac:
AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS).
AM_INIT_AUTOMAKE([no-define foreign 1.6]).
* clock/Makefile.am: Remove AUTOMAKE_OPTIONS.
* Makefile.am: Remove AUTOMAKE_OPTIONS.
* console/Makefile.am: Remove AUTOMAKE_OPTIONS.
* include/Makefile.am: Remove AUTOMAKE_OPTIONS.
* network/Makefile.am: Remove AUTOMAKE_OPTIONS.
* nvram/Makefile.am: Remove AUTOMAKE_OPTIONS.
* pci/Makefile.am: Remove AUTOMAKE_OPTIONS.
* start/Makefile.am: Remove AUTOMAKE_OPTIONS.
* startup/Makefile.am: Remove AUTOMAKE_OPTIONS.
* timer/Makefile.am: Remove AUTOMAKE_OPTIONS.
* tod/Makefile.am: Remove AUTOMAKE_OPTIONS.
* universe/Makefile.am: Remove AUTOMAKE_OPTIONS.
* vectors/Makefile.am: Remove AUTOMAKE_OPTIONS.
* wrapup/Makefile.am: Remove AUTOMAKE_OPTIONS.
2001-11-30 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* configure.ac: Introduce RTEMS_BSP_CONFIGURE.
2001-11-21 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: Add @exceptions@ to SUBDIRS.
* configure.ac: Apply RTEMS_BSPOPTS_*(*) to merge-in settings from
make/custom/ppcn_60x.cfg;
Add RTEMS_PPC_EXCEPTIONS([old]).
* include/Makefile.am: include force-preinstall.am.
* wrapup/Makefile.am: Apply @exceptions@.
2001-11-08 Dennis Ehlin (ECS) <Dennis.Ehlin@ecs.ericsson.se>
This modification is part of the submitted modifications necessary to
support the IBM PPC405 family. This submission was reviewed by
Thomas Doerfler <Thomas.Doerfler@imd-systems.de> who ensured it did
not negatively impact the ppc403 BSPs. The submission and tracking
process was captured as PR50.
* startup/spurious.c: Added ppc405 support.
2001-10-25 Joel Sherrill <joel@OARcorp.com>
* startup/linkcmds: Added _init and _fini.
2001-10-12 Joel Sherrill <joel@OARcorp.com>
* clock/clock.c, console/console.c, console/debugio.c,
console/ns16550cfg.c, console/ns16550cfg.h, console/z85c30cfg.c,
console/z85c30cfg.h, include/bsp.h, startup/bspstart.c,
startup/genpvec.c, startup/rtems-ctor.cc, startup/setvec.c,
timer/timer.c: Fixed typo.
2001-10-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* .cvsignore: Add autom4te.cache for autoconf > 2.52.
* configure.in: Remove.
* configure.ac: New file, generated from configure.in by autoupdate.
2001-09-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* include/Makefile.am: Use 'TMPINSTALL_FILES ='.
2001-06-19 Joel Sherrill <joel@OARcorp.com>
* include/Makefile.am: Fixed typo.
2001-05-26 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* configure.in: Add bspopts.h.
* include/.cvsignore: Add bspopts.h*, stamp-h*.
* include/Makefile.am: Use *_HEADERS instead of *H_FILES.
* include/bsp.h: Include bspopts.h.
2001-05-10 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* configure.in: Use RTEMS_PROG_CC_FOR_TARGET([-ansi -fasm]).
2001-01-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* startup/genpvec.c: #include <chain.h> instead of "chain.h", fix
CVS-Id.
* include/chain.h: Remove.
* include/Makefile.am: Remove chain.h.
2000-11-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
2000-11-02 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
2000-11-01 Joel Sherrill <joel@OARcorp.com>
* startup/bspstart.c: assoc.h, error.h, libio_.h, libio.h,
and libcsupport.h moved from libc to lib/include/rtems and
now must be referenced as <rtems/XXX.h>. Header file order
was cleaned up while doing this.
2000-10-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
Switch to GNU canonicalization.
2000-09-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* clock/Makefile.am, console/Makefile.am, network/Makefile.am,
nvram/Makefile.am, pci/Makefile.am, start/Makefile.am,
startup/Makefile.am, timer/Makefile.am, tod/Makefile.am,
universe/Makefile.am, vectors/Makefile.am, wrapup/Makefile.am:
Include compile.am
2000-08-10 Joel Sherrill <joel@OARcorp.com>
* ChangeLog: New file.

166
c/src/lib/libbsp/powerpc/ppcn_60x/Makefile.am
View File

@@ -1,166 +0,0 @@
##
## $Id$
##
ACLOCAL_AMFLAGS = -I ../../../../aclocal
include $(top_srcdir)/../../../../automake/compile.am
include $(top_srcdir)/../../bsp.am
dist_project_lib_DATA = bsp_specs
include_HEADERS = include/bsp.h
include_HEADERS += include/tm27.h
nodist_include_HEADERS = include/bspopts.h
DISTCLEANFILES = include/bspopts.h
noinst_PROGRAMS =
nodist_include_HEADERS += $(top_srcdir)/../../shared/include/coverhd.h
include_HEADERS += ../../shared/tod.h
include_HEADERS += include/nvram.h include/pci.h
EXTRA_DIST = start/start.S
start.$(OBJEXT): start/start.S
$(CPPASCOMPILE) -DASM -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)
dist_project_lib_DATA += startup/linkcmds
noinst_PROGRAMS += clock.rel
clock_rel_SOURCES = clock/clock.c
clock_rel_CPPFLAGS = $(AM_CPPFLAGS)
clock_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
noinst_PROGRAMS += console.rel
console_rel_SOURCES = console/console.c console/i8042vga.c \
console/i8042vga.h console/i8042.c console/i8042_p.h \
console/ns16550cfg.c console/ns16550cfg.h console/z85c30cfg.c \
console/z85c30cfg.h console/vga.c console/vga_p.h
console_rel_CPPFLAGS = $(AM_CPPFLAGS)
console_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
noinst_PROGRAMS += pci.rel
pci_rel_SOURCES = pci/pci.c
pci_rel_CPPFLAGS = $(AM_CPPFLAGS)
pci_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
noinst_PROGRAMS += nvram.rel
nvram_rel_SOURCES = nvram/nvram.c nvram/ds1385.h nvram/mk48t18.h \
nvram/prepnvr.h nvram/stk11c68.h
nvram_rel_CPPFLAGS = $(AM_CPPFLAGS)
nvram_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
noinst_PROGRAMS += startup.rel
startup_rel_SOURCES = startup/bspstart.c startup/bspclean.c \
../../shared/sbrk.c startup/setvec.c startup/spurious.c \
startup/genpvec.c startup/swap.c ../../shared/main.c \
../../shared/bootcard.c ../../shared/bsplibc.c ../../shared/bsppost.c \
../../shared/gnatinstallhandler.c startup/bsptrap.S
startup_rel_CPPFLAGS = $(AM_CPPFLAGS)
startup_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
noinst_PROGRAMS += timer.rel
timer_rel_SOURCES = timer/timer.c
timer_rel_CPPFLAGS = $(AM_CPPFLAGS)
timer_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
noinst_PROGRAMS += tod.rel
tod_rel_SOURCES = tod/tod.c tod/cmos.h
tod_rel_CPPFLAGS = $(AM_CPPFLAGS)
tod_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
noinst_PROGRAMS += universe.rel
universe_rel_SOURCES = universe/universe.c
universe_rel_CPPFLAGS = $(AM_CPPFLAGS)
universe_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
EXTRA_DIST += vectors/README vectors/align_h.S
noinst_PROGRAMS += vectors.rel
vectors_rel_SOURCES = vectors/vectors.S
vectors_rel_CPPFLAGS = $(AM_CPPFLAGS)
vectors_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
if HAS_NETWORKING
network_CPPFLAGS = -D__INSIDE_RTEMS_BSD_TCPIP_STACK__
noinst_PROGRAMS += network.rel
network_rel_SOURCES = network/amd79c970.c network/amd79c970.h
network_rel_CPPFLAGS = $(AM_CPPFLAGS) $(network_CPPFLAGS)
network_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
endif
noinst_LIBRARIES = libbsp.a
libbsp_a_SOURCES =
libbsp_a_LIBADD = startup.rel clock.rel console.rel timer.rel tod.rel \
nvram.rel universe.rel pci.rel vectors.rel
if HAS_NETWORKING
libbsp_a_LIBADD += network.rel
endif
libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel
all-local: $(PREINSTALL_FILES) $(TMPINSTALL_FILES)
EXTRA_DIST += STATUS
PREINSTALL_DIRS =
PREINSTALL_FILES =
TMPINSTALL_FILES =
$(PROJECT_INCLUDE)/$(dirstamp):
@$(mkdir_p) $(PROJECT_INCLUDE)
@: > $(PROJECT_INCLUDE)/$(dirstamp)
PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp)
$(PROJECT_LIB)/$(dirstamp):
@$(mkdir_p) $(PROJECT_LIB)
@: > $(PROJECT_LIB)/$(dirstamp)
PREINSTALL_DIRS += $(PROJECT_LIB)/$(dirstamp)
$(PROJECT_LIB)/bsp_specs: bsp_specs $(PROJECT_LIB)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_LIB)/bsp_specs
PREINSTALL_FILES += $(PROJECT_LIB)/bsp_specs
$(PROJECT_INCLUDE)/bsp.h: include/bsp.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp.h
$(PROJECT_INCLUDE)/tm27.h: include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h
$(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h
$(PROJECT_INCLUDE)/coverhd.h: $(top_srcdir)/../../shared/include/coverhd.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/coverhd.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/coverhd.h
$(PROJECT_INCLUDE)/tod.h: ../../shared/tod.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tod.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/tod.h
$(PROJECT_INCLUDE)/nvram.h: include/nvram.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/nvram.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/nvram.h
$(PROJECT_INCLUDE)/pci.h: include/pci.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/pci.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/pci.h
$(PROJECT_LIB)/start.$(OBJEXT): start.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_LIB)/start.$(OBJEXT)
TMPINSTALL_FILES += $(PROJECT_LIB)/start.$(OBJEXT)
$(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds
PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds
CLEANFILES = $(PREINSTALL_FILES)
DISTCLEANFILES += $(PREINSTALL_DIRS)
CLEANFILES += $(TMPINSTALL_FILES)
include $(top_srcdir)/../../../../automake/subdirs.am
include $(top_srcdir)/../../../../automake/local.am

48
c/src/lib/libbsp/powerpc/ppcn_60x/README
View File

@@ -1,48 +0,0 @@
#
# $Id$
#
BSP NAME: psim
BOARD: PowerPC Simulator
BUS: N/A
CPU FAMILY: ppc
CPU: PowerPC 603, 603e, 604
COPROCESSORS: N/A
MODE: 32 bit mode
DEBUG MONITOR: BUG mode (emulates Motorola debug monitor)
PERIPHERALS
===========
TIMERS: PPC internal Timebase register
RESOLUTION: ???
SERIAL PORTS: simulated via bug
REAL-TIME CLOCK: PPC internal Decrementer register
DMA: none
VIDEO: none
SCSI: none
NETWORKING: none
DRIVER INFORMATION
==================
CLOCK DRIVER: PPC internal
IOSUPP DRIVER: N/A
SHMSUPP: N/A
TIMER DRIVER: PPC internal
TTY DRIVER: PPC internal
STDIO
=====
PORT: Console port 0
ELECTRICAL: na
BAUD: na
BITS PER CHARACTER: na
PARITY: na
STOP BITS: na
Notes
=====
Based on papyrus bsp which only really supports
the PowerOpen ABI with an ELF assembler.

8
c/src/lib/libbsp/powerpc/ppcn_60x/STATUS
View File

@@ -1,8 +0,0 @@
#
# $Id$
#
These are the notes made while updating this BSP to a more current
RTEMS version.
+ device-tree is psim specific and was removed

15
c/src/lib/libbsp/powerpc/ppcn_60x/bsp_specs
View File

@@ -1,15 +0,0 @@
%rename endfile old_endfile
%rename startfile old_startfile
%rename link old_link
*startfile:
%{!qrtems: %(old_startfile)} %{!nostdlib: %{qrtems: ecrti%O%s \
%{!qrtems_debug: start.o%s} \
%{qrtems_debug: start_g.o%s}}}
*endfile:
%{!qrtems: %(old_endfile)} %{qrtems: ecrtn%O%s}
*link:
%{!qrtems: %(old_link)} %{qrtems: -Qy -dp -Bstatic -e _start -u __vectors}

224
c/src/lib/libbsp/powerpc/ppcn_60x/clock/clock.c
View File

@@ -1,224 +0,0 @@
/*
* Clock Tick Device Driver
*
* This routine utilizes the Decrementer Register common to the PPC family.
*
* The tick frequency is directly programmed to the configured number of
* microseconds per tick.
*
* COPYRIGHT (c) 1989-1997.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may in
* the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
#include <stdlib.h>
#include <bsp.h>
#include <rtems/libio.h>
#include <assert.h>
/*
* The Real Time Clock Counter Timer uses this trap type.
*/
#define CLOCK_VECTOR PPC_IRQ_DECREMENTER
/*
* Clock ticks since initialization
*/
volatile uint32_t Clock_driver_ticks;
/*
* This is the value programmed into the count down timer.
*/
uint32_t Clock_Decrementer_value;
rtems_isr_entry Old_ticker;
void Clock_exit( void );
/*
* These are set by clock driver during its init
*/
rtems_device_major_number rtems_clock_major = ~0;
rtems_device_minor_number rtems_clock_minor;
/*
* Clock_isr
*
* This is the clock tick interrupt handler.
*
* Input parameters:
* vector - vector number
*
* Output parameters: NONE
*
* Return values: NONE
*
*/
rtems_isr Clock_isr(
rtems_vector_number vector,
CPU_Interrupt_frame *frame
)
{
/*
* Set the decrementer.
*/
PPC_Set_decrementer( Clock_Decrementer_value );
/*
* The driver has seen another tick.
*/
Clock_driver_ticks += 1;
/*
* Real Time Clock counter/timer is set to automatically reload.
*/
rtems_clock_tick();
}
/*
* Install_clock
*
* This routine actually performs the hardware initialization for the clock.
*
* Input parameters:
* clock_isr - clock interrupt service routine entry point
*
* Output parameters: NONE
*
* Return values: NONE
*
*/
extern int CLOCK_SPEED;
void Install_clock(
rtems_isr_entry clock_isr
)
{
Clock_driver_ticks = 0;
Old_ticker = (rtems_isr_entry) set_vector( clock_isr, CLOCK_VECTOR, 1 );
PPC_Set_decrementer( Clock_Decrementer_value );
atexit( Clock_exit );
}
/*
* Clock_exit
*
* This routine allows the clock driver to exit by masking the interrupt and
* disabling the clock's counter.
*
* Input parameters: NONE
*
* Output parameters: NONE
*
* Return values: NONE
*
*/
void Clock_exit( void )
{
/* nothing to do */;
/* do not restore old vector */
}
/*
* Clock_initialize
*
* This routine initializes the clock driver.
*
* Input parameters:
* major - clock device major number
* minor - clock device minor number
* parg - pointer to optional device driver arguments
*
* Output parameters: NONE
*
* Return values:
* rtems_device_driver status code
*/
rtems_device_driver Clock_initialize(
rtems_device_major_number major,
rtems_device_minor_number minor,
void *pargp
)
{
Clock_Decrementer_value = (ulCpuBusClock/4000)*
(BSP_Configuration.microseconds_per_tick/1000);
Install_clock((rtems_isr_entry)Clock_isr);
/*
* make major/minor avail to others such as shared memory driver
*/
rtems_clock_major = major;
rtems_clock_minor = minor;
return RTEMS_SUCCESSFUL;
}
/*
* Clock_control
*
* This routine is the clock device driver control entry point.
*
* Input parameters:
* major - clock device major number
* minor - clock device minor number
* parg - pointer to optional device driver arguments
*
* Output parameters: NONE
*
* Return values:
* rtems_device_driver status code
*/
rtems_device_driver Clock_control(
rtems_device_major_number major,
rtems_device_minor_number minor,
void *pargp
)
{
uint32_t isrlevel;
rtems_libio_ioctl_args_t *args = pargp;
if (args == 0)
goto done;
/*
* This is hokey, but until we get a defined interface
* to do this, it will just be this simple...
*/
if (args->command == rtems_build_name('I', 'S', 'R', ' '))
{
Clock_isr( CLOCK_VECTOR, pargp );
}
else if (args->command == rtems_build_name('N', 'E', 'W', ' '))
{
rtems_interrupt_disable( isrlevel );
(void) set_vector( args->buffer, CLOCK_VECTOR, 1 );
rtems_interrupt_enable( isrlevel );
}
done:
return RTEMS_SUCCESSFUL;
}

67
c/src/lib/libbsp/powerpc/ppcn_60x/configure.ac
View File

@@ -1,67 +0,0 @@
## Process this file with autoconf to produce a configure script.
##
## $Id$
AC_PREREQ(2.59)
AC_INIT([rtems-c-src-lib-libbsp-powerpc-ppcn_60x],[_RTEMS_VERSION],[rtems-bugs@rtems.com])
AC_CONFIG_SRCDIR([bsp_specs])
RTEMS_TOP(../../../../../..)
RTEMS_CANONICAL_TARGET_CPU
AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.9])
RTEMS_BSP_CONFIGURE
RTEMS_PROG_CC_FOR_TARGET([-ansi -fasm])
RTEMS_CANONICALIZE_TOOLS
RTEMS_PROG_CCAS
RTEMS_CHECK_NETWORKING
# Don't build the network directory
# The problem is that the code there has not yet been converted to
# bsd networking
AM_CONDITIONAL(HAS_NETWORKING,false)
# AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes")
RTEMS_BSPOPTS_SET([PPC_USE_SPRG],[*],[0])
RTEMS_BSPOPTS_HELP([PPC_USE_SPRG],
[If defined, then the PowerPC specific code in RTEMS will use some
of the special purpose registers to slightly optimize interrupt
response time. The use of these registers can conflict with
other tools like debuggers.])
RTEMS_BSPOPTS_SET([PPC_USE_DATA_CACHE],[*],[1])
RTEMS_BSPOPTS_HELP([PPC_USE_DATA_CACHE],
[If defined, then the PowerPC specific code in RTEMS will use
data cache instructions to optimize the context switch code.
This code can conflict with debuggers or emulators. It is known
to break the Corelis PowerPC emulator with at least some combinations
of PowerPC 603e revisions and emulator versions.
The BSP actually contains the call that enables this.])
# FIXME: This should be a 1 out of 2 (3??) selection.
RTEMS_BSPOPTS_SET([PPCN_60X_USE_DINK],[*],[1])
RTEMS_BSPOPTS_HELP([PPCN_60X_USE_DINK],
[The Score603e board can be configured with 3 ROM monitors. Only two
are appropriate for use with RTEMS. Set exactly one of these to "1"
to indicate which ROM monitor is on the board you are using. Corresponds to
PPCN_60X_USE_NONE])
RTEMS_BSPOPTS_SET([PPCN_60X_USE_NONE],[*],[0])
RTEMS_BSPOPTS_HELP([PPCN_60X_USE_NONE],
[The Score603e board can be configured with 3 ROM monitors. Only two
are appropriate for use with RTEMS. Set exactly one of these to "1"
to indicate which ROM monitor is on the board you are using. Corresponds to
PPCN_60X_USE_DINK])
RTEMS_BSPOPTS_SET([PPC_VECTOR_FILE_BASE],[*],[0x0100])
RTEMS_BSPOPTS_HELP([PPC_VECTOR_FILE_BASE],
[This defines the base address of the exception table.
NOTE: Vectors are actually at 0xFFF00000 but file starts at offset.])
# Explicitly list all Makefiles here
AC_CONFIG_FILES([Makefile])
RTEMS_PPC_EXCEPTIONS
AC_OUTPUT

487
c/src/lib/libbsp/powerpc/ppcn_60x/console/config.c
View File

@@ -1,487 +0,0 @@
/*
* This file contains the TTY driver table for the PPCn_60x
*
* COPYRIGHT (c) 1998 by Radstone Technology
*
*
* THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
* KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
* AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
*
* You are hereby granted permission to use, copy, modify, and distribute
* this file, provided that this notice, plus the above copyright notice
* and disclaimer, appears in all copies. Radstone Technology will provide
* no support for this code.
*
* $Id$
*/
#include <libchip/serial.h>
#include <libchip/mc68681.h>
#include <libchip/z85c30.h>
#include "i8042vga.h"
#include "ns16550cfg.h"
#include "z85c30cfg.h"
#include <pci.h>
#define PMX1553_BUS 2
#define PMX1553_SLOT 1
/*
* Based on BSP configuration information decide whether to do polling IO
* or interrupt driven IO.
*/
#if (CONSOLE_USE_INTERRUPTS)
#define NS16550_FUNCTIONS &ns16550_fns
#define Z85C30_FUNCTIONS &z85c30_fns
#else
#define NS16550_FUNCTIONS &ns16550_fns_polled
#define Z85C30_FUNCTIONS &z85c30_fns_polled
#endif
/*
* Configuration specific probe routines
*/
static boolean config_PMX1553_probe(int minor);
static boolean config_z85c30_probe(int minor);
/*
* The following table configures the console drivers used in this BSP.
*
* The first entry which, when probed, is available, will be named /dev/console,
* all others being given the name indicated.
*
* Each field is interpreted thus:
*
* sDeviceName This is the name of the device.
* pDeviceFns This is a pointer to the set of driver routines to use.
* pDeviceFlow This is a pointer to the set of flow control routines to
* use. Serial device drivers will typically supply RTSCTS
* and DTRCTS handshake routines for DCE to DCE communication,
* however for DCE to DTE communication, no such routines
* should be necessary as RTS will be driven automatically
* when the transmitter is active.
* ulMargin The high water mark in the input buffer is set to the buffer
* size less ulMargin. Once this level is reached, the driver's
* flow control routine used to stop the remote transmitter will
* be called. This figure should be greater than or equal to
* the number of stages of FIFO between the transmitter and
* receiver.
* ulHysteresis After the high water mark specified by ulMargin has been
* reached, the driver's routine to re-start the remote
* transmitter will be called once the level in the input
* buffer has fallen by ulHysteresis bytes.
* pDeviceParams This contains either device specific data or a pointer to a
* device specific structure containing additional information
* not provided in this table.
* ulCtrlPort1 This is the primary control port number for the device. This
* may be used to specify different instances of the same device
* type.
* ulCtrlPort2 This is the secondary control port number, of use when a given
* device has more than one available channel.
* ulDataPort This is the port number for the data port of the device
* ulIntVector This encodes the interrupt vector of the device.
*
*/
console_tbl Console_Port_Tbl[] = {
{
"/dev/vga", /* sDeviceName */
SERIAL_CUSTOM, /* deviceType */
&i8042vga_fns, /* pDeviceFns */
NULL, /* deviceProbe */
NULL, /* pDeviceFlow */
0, /* ulMargin */
0, /* ulHysteresis */
(void *)0, /* pDeviceParams */
I8042_CS, /* ulCtrlPort1 */
0, /* ulCtrlPort2 */
I8042_DATA, /* ulDataPort */
Read_ns16550_register, /* getRegister */
Write_ns16550_register, /* setRegister */
NULL, /* getData */
NULL, /* setData */
0, /* ulClock */
PPCN_60X_IRQ_KBD /* ulIntVector */
},
{
"/dev/com1", /* sDeviceName */
SERIAL_NS16550, /* deviceType */
NS16550_FUNCTIONS, /* pDeviceFns */
NULL, /* deviceProbe */
&ns16550_flow_RTSCTS, /* pDeviceFlow */
16, /* ulMargin */
8, /* ulHysteresis */
(void *)9600, /* baud rate */ /* pDeviceParams */
NS16550_PORT_A, /* ulCtrlPort1 */
0, /* ulCtrlPort2 */
NS16550_PORT_A, /* ulDataPort */
Read_ns16550_register, /* getRegister */
Write_ns16550_register, /* setRegister */
NULL, /* getData */
NULL, /* setData */
0, /* ulClock */
PPCN_60X_IRQ_COM1 /* ulIntVector */
},
{
"/dev/ser1", /* sDeviceName */
SERIAL_NS16550, /* deviceType */
NS16550_FUNCTIONS, /* pDeviceFns */
config_PMX1553_probe, /* deviceProbe */
&ns16550_flow_RTSCTS, /* pDeviceFlow */
80, /* ulMargin */
8, /* ulHysteresis */
(void *)9600, /* baud rate */ /* pDeviceParams */
PMX1553_BUS, /* PCI bus */ /* ulCtrlPort1 */
PMX1553_SLOT, /* PCI slot */ /* ulCtrlPort2 */
1, /* Channel 1-4 */ /* ulDataPort */
NULL, /* getRegister */
NULL, /* setRegister */
NULL, /* getData */
NULL, /* setData */
0, /* ulClock */
0 /* RS232 */ /* ulIntVector */
},
{
"/dev/ser2", /* sDeviceName */
SERIAL_NS16550, /* deviceType */
NS16550_FUNCTIONS, /* pDeviceFns */
config_PMX1553_probe, /* deviceProbe */
&ns16550_flow_RTSCTS, /* pDeviceFlow */
80, /* ulMargin */
8, /* ulHysteresis */
(void *)9600, /* baud rate */ /* pDeviceParams */
PMX1553_BUS, /* PCI bus */ /* ulCtrlPort1 */
PMX1553_SLOT, /* PCI slot */ /* ulCtrlPort2 */
2, /* Channel 1-4 */ /* ulDataPort */
Read_ns16550_register, /* getRegister */
Write_ns16550_register, /* setRegister */
NULL, /* getData */
NULL, /* setData */
0, /* ulClock */
0 /* RS232 */ /* ulIntVector */
},
{
"/dev/ser3", /* sDeviceName */
SERIAL_NS16550, /* deviceType */
NS16550_FUNCTIONS, /* pDeviceFns */
config_PMX1553_probe, /* deviceProbe */
&ns16550_flow_RTSCTS, /* pDeviceFlow */
96, /* ulMargin */
8, /* ulHysteresis */
(void *)57600, /* baud rate */ /* pDeviceParams */
PMX1553_BUS, /* PCI bus */ /* ulCtrlPort1 */
PMX1553_SLOT, /* PCI slot */ /* ulCtrlPort2 */
3, /* Channel 1-4 */ /* ulDataPort */
Read_ns16550_register, /* getRegister */
Write_ns16550_register, /* setRegister */
NULL, /* getData */
NULL, /* setData */
0, /* ulClock */
0 /* RS232 */ /* ulIntVector */
},
{
"/dev/ser4", /* sDeviceName */
SERIAL_NS16550, /* deviceType */
NS16550_FUNCTIONS, /* pDeviceFns */
config_PMX1553_probe, /* deviceProbe */
&ns16550_flow_RTSCTS, /* pDeviceFlow */
96, /* ulMargin */
8, /* ulHysteresis */
(void *)57600, /* baud rate */ /* pDeviceParams */
PMX1553_BUS, /* PCI bus */ /* ulCtrlPort1 */
PMX1553_SLOT, /* PCI slot */ /* ulCtrlPort2 */
4, /* Channel 1-4 */ /* ulDataPort */
Read_ns16550_register, /* getRegister */
Write_ns16550_register, /* setRegister */
NULL, /* getData */
NULL, /* setData */
0, /* ulClock */
0 /* RS232 */ /* ulIntVector */
},
#if !PPCN_60X_USE_DINK
{
"/dev/com2", /* sDeviceName */
SERIAL_NS16550, /* deviceType */
NS16550_FUNCTIONS, /* pDeviceFns */
NULL, /* deviceProbe */
&ns16550_flow_RTSCTS, /* pDeviceFlow */
16, /* ulMargin */
8, /* ulHysteresis */
(void *)9600, /* baud rate */ /* pDeviceParams */
NS16550_PORT_B, /* ulCtrlPort1 */
0, /* ulCtrlPort2 */
NS16550_PORT_B, /* ulDataPort */
Read_ns16550_register, /* getRegister */
Write_ns16550_register, /* setRegister */
NULL, /* getData */
NULL, /* setData */
0, /* ulClock */
PPCN_60X_IRQ_COM2 /* ulIntVector */
},
#endif
{
"/dev/com3", /* sDeviceName */
SERIAL_Z85C30, /* deviceType */
Z85C30_FUNCTIONS, /* pDeviceFns */
config_z85c30_probe, /* deviceProbe */
&z85c30_flow_RTSCTS, /* pDeviceFlow */
16, /* ulMargin */
8, /* ulHysteresis */
(void *)9600, /* baud rate */ /* pDeviceParams */
Z85C30_CTRL_A, /* ulCtrlPort1 */
Z85C30_CTRL_A, /* ulCtrlPort2 */
Z85C30_DATA_A, /* ulDataPort */
Read_85c30_register, /* getRegister */
Write_85c30_register, /* setRegister */
Read_85c30_data, /* getData */
Write_85c30_data, /* setData */
0, /* ulClock */
PPCN_60X_IRQ_COM3_4 /* ulIntVector */
},
{
"/dev/com4", /* sDeviceName */
SERIAL_Z85C30, /* deviceType */
Z85C30_FUNCTIONS, /* pDeviceFns */
config_z85c30_probe, /* deviceProbe */
&z85c30_flow_RTSCTS, /* pDeviceFlow */
16, /* ulMargin */
8, /* ulHysteresis */
(void *)9600, /* baud rate */ /* pDeviceParams */
Z85C30_CTRL_B, /* ulCtrlPort1 */
Z85C30_CTRL_A, /* ulCtrlPort2 */
Z85C30_DATA_B, /* ulDataPort */
Read_85c30_register, /* getRegister */
Write_85c30_register, /* setRegister */
Read_85c30_data, /* getData */
Write_85c30_data, /* setData */
0, /* ulClock */
PPCN_60X_IRQ_COM3_4 /* ulIntVector */
}
};
/*
* Define serial port write registers structure.
*/
typedef volatile struct _SP_WRITE_REGISTERS {
unsigned char TransmitBuffer;
unsigned char InterruptEnable;
unsigned char FifoControl;
unsigned char LineControl;
unsigned char ModemControl;
unsigned char Reserved1;
unsigned char ModemStatus;
unsigned char ScratchPad;
} SP_WRITE_REGISTERS, *PSP_WRITE_REGISTERS;
static boolean config_PMX1553_probe(int minor)
{
uint8_t ucBusNumber, ucSlotNumber, ucChannel;
uint8_t ucIntLine;
uint32_t ulPortBase, ulMemBase, ulDeviceID, ulTemp;
uint8_t *pucSIO_cir, *pucUart_int_sr, *pucUartDevIntReg;
PSP_WRITE_REGISTERS pNS16550Write;
/*
* Extract PCI bus/slot and channel number
*/
ucBusNumber=Console_Port_Tbl[minor].ulCtrlPort1;
ucSlotNumber=Console_Port_Tbl[minor].ulCtrlPort2;
ucChannel=Console_Port_Tbl[minor].ulDataPort;
PCIConfigRead32(ucBusNumber,
ucSlotNumber,
0,
PCI_CONFIG_VENDOR_LOW,
&ulDeviceID);
if(ulDeviceID!=0x000111b5)
{
return FALSE;
}
/*
* At this point we know we have a PMC1553 or PMX1553 card
*
* Check for PMX1553 uart legacy IO ports
*/
PCIConfigRead32(ucBusNumber,
ucSlotNumber,
0,
PCI_CONFIG_BAR_3,
&ulPortBase);
if(ulPortBase==0)
{
/*
* This is either a PMC1553 or we can't see the uart
* registers
*/
return FALSE;
}
PCIConfigRead32(ucBusNumber,
ucSlotNumber,
0,
PCI_CONFIG_BAR_2,
&ulMemBase);
pucUartDevIntReg=(uint8_t*)(PCI_MEM_BASE+ulMemBase);
pucUart_int_sr=(uint8_t*)(PCI_MEM_BASE+ulMemBase+0x10);
pucSIO_cir=(uint8_t*)(PCI_MEM_BASE+ulMemBase+0x18);
/*
* Use ulIntVector field to select RS232/RS422
*/
if(Console_Port_Tbl[minor].ulIntVector==0)
{
/*
* Select RS232 mode
*/
*pucSIO_cir&=~(1<<(ucChannel-1));
}
else
{
/*
* Select RS422 mode
*/
*pucSIO_cir|=1<<(ucChannel-1);
}
EIEIO;
/*
* Bring device out of reset
*/
*pucSIO_cir&=0xbf;
EIEIO;
/*
* Enable all channels as active
*/
*pucSIO_cir|=0x10;
EIEIO;
*pucSIO_cir&=0xdf;
PCIConfigRead8(ucBusNumber,
ucSlotNumber,
0,
PCI_CONFIG_INTERRUPTLINE,
&ucIntLine);
ulPortBase&=~PCI_ADDRESS_IO_SPACE;
ulPortBase+=8*(ucChannel-1);
Console_Port_Tbl[minor].ulCtrlPort1=
Console_Port_Tbl[minor].ulDataPort=ulPortBase;
if(Console_Port_Tbl[minor].pDeviceFns!=&ns16550_fns_polled)
{
Console_Port_Tbl[minor].ulIntVector=PPCN_60X_IRQ_PCI(ucIntLine);
/*
* Enable interrupt
*/
*pucUart_int_sr=(~*pucUart_int_sr)&(0x08<<ucChannel);
/*
* Enable interrupt to PCI
*/
*pucUartDevIntReg=(~*pucUartDevIntReg)&0x80;
}
else
{
/*
* Disable interrupt
*/
*pucUart_int_sr&=(0x08<<ucChannel);
}
/*
* Enable Auto CTS to facilitate flow control
*/
pNS16550Write=(PSP_WRITE_REGISTERS)Console_Port_Tbl[minor].ulCtrlPort1;
/*
* Enable special register set and unlock Enhanced Feature Register
*/
outport_byte(&pNS16550Write->LineControl, 0xbf);
/*
* Unlock enhanced function bits
*/
outport_byte(&pNS16550Write->FifoControl, 0x10);
/*
* Disable special register set and lock Enhanced Feature Register
*/
outport_byte(&pNS16550Write->LineControl, 0);
/*
* Select div 1
*/
outport_byte(&pNS16550Write->ModemControl, 0x00);
/*
* Enable special register set and unlock Enhanced Feature Register
*/
outport_byte(&pNS16550Write->LineControl, 0xbf);
/*
* Lock enhanced function bits and enable auto CTS
*/
outport_byte(&pNS16550Write->FifoControl, 0x80);
/*
* Disable special register set and lock Enhanced Feature Register
*/
outport_byte(&pNS16550Write->LineControl, 0);
/*
* The PMX1553 currently uses a 16 MHz clock rather than the
* 7.3728 MHz clock described in the ST16C654 data sheet. When
* available, 22.1184 MHz will be used allowing rates up to
* 1382400 baud (RS422 only).
*/
ulTemp = (uint32_t)Console_Port_Tbl[minor].pDeviceParams;
#if 1
/*
* Scale requested baud rate for 16 MHz clock
*/
ulTemp *= 7373;
ulTemp /= 16000;
#else
/*
* Scale requested baud rate for 22.1184 MHz clock
*/
ulTemp /= 3;
#endif
/*
* In order to maintain maximum data rate accuracy, we will
* apply a div 4 here rather than in hardware (using MCR bit 7).
*/
ulTemp /= 4;
Console_Port_Tbl[minor].pDeviceParams = (void *)ulTemp;
return(TRUE);
}
static boolean config_z85c30_probe(int minor)
{
/*
* PPC1 and PPC1a do not have this device
*/
if((ucSystemType==SYS_TYPE_PPC1) ||
(ucSystemType==SYS_TYPE_PPC1a))
{
return (FALSE);
}
/*
* All other boards supported by this BSP have the z85c30 device
*/
/*
* Ensure that CIO port B is configured for
* default driver enable
*/
outport_byte(0x861, 0x33);
return(TRUE);
}

348
c/src/lib/libbsp/powerpc/ppcn_60x/console/console.c
View File

@@ -1,348 +0,0 @@
/*
* This file contains the TTY driver for the PPCn_60x
*
* This driver uses the termios pseudo driver.
*
* COPYRIGHT (c) 1998 by Radstone Technology
*
*
* THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
* KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
* AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
*
* You are hereby granted permission to use, copy, modify, and distribute
* this file, provided that this notice, plus the above copyright notice
* and disclaimer, appears in all copies. Radstone Technology will provide
* no support for this code.
*
* COPYRIGHT (c) 1989-1997.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
#include <bsp.h>
#include <rtems/libio.h>
#include <stdlib.h>
#include <assert.h>
#include <termios.h>
#include "console.h"
/*
* Load configuration table
*/
#include "config.c"
#define NUM_CONSOLE_PORTS (sizeof(Console_Port_Tbl)/sizeof(console_tbl))
console_data Console_Port_Data[NUM_CONSOLE_PORTS];
unsigned long Console_Port_Count;
rtems_device_minor_number Console_Port_Minor;
/* PAGE
*
* console_open
*
* open a port as a termios console.
*
*/
rtems_device_driver console_open(
rtems_device_major_number major,
rtems_device_minor_number minor,
void * arg
)
{
rtems_status_code status;
rtems_libio_open_close_args_t *args = arg;
rtems_libio_ioctl_args_t IoctlArgs;
struct termios Termios;
rtems_termios_callbacks Callbacks;
console_fns *c;
/*
* Verify the port number is valid.
*/
if(minor>Console_Port_Count)
{
return RTEMS_INVALID_NUMBER;
}
/*
* open the port as a termios console driver.
*/
c = Console_Port_Tbl[minor].pDeviceFns;
Callbacks.firstOpen = c->deviceFirstOpen;
Callbacks.lastClose = c->deviceLastClose;
Callbacks.pollRead = c->deviceRead;
Callbacks.write = c->deviceWrite;
Callbacks.setAttributes = c->deviceSetAttributes;
Callbacks.stopRemoteTx =
Console_Port_Tbl[minor].pDeviceFlow->deviceStopRemoteTx;
Callbacks.startRemoteTx =
Console_Port_Tbl[minor].pDeviceFlow->deviceStartRemoteTx;
Callbacks.outputUsesInterrupts = c->deviceOutputUsesInterrupts;
status = rtems_termios_open ( major, minor, arg, &Callbacks);
Console_Port_Data[minor].termios_data = args->iop->data1;
/*
* Patch in flow control routines
*/
/* XXX */
#if 0
if((status==RTEMS_SUCCESSFUL) &&
(Console_Port_Tbl[minor].pDeviceFlow))
{
status=rtems_termios_flow_control(
major, minor, arg,
Console_Port_Tbl[minor].pDeviceFlow->
deviceStartRemoteTx,
Console_Port_Tbl[minor].pDeviceFlow->deviceStopRemoteTx,
Console_Port_Tbl[minor].ulMargin,
Console_Port_Tbl[minor].ulHysteresis);
}
#endif
if(minor!=Console_Port_Minor)
{
/*
* If this is not the console we do not want ECHO and
* so forth
*/
IoctlArgs.iop=args->iop;
IoctlArgs.command=RTEMS_IO_GET_ATTRIBUTES;
IoctlArgs.buffer=&Termios;
rtems_termios_ioctl(&IoctlArgs);
Termios.c_lflag=ICANON;
IoctlArgs.command=RTEMS_IO_SET_ATTRIBUTES;
rtems_termios_ioctl(&IoctlArgs);
}
if((args->iop->flags&LIBIO_FLAGS_READ) &&
Console_Port_Tbl[minor].pDeviceFlow &&
Console_Port_Tbl[minor].pDeviceFlow->deviceStartRemoteTx)
{
Console_Port_Tbl[minor].pDeviceFlow->deviceStartRemoteTx(minor);
}
return status;
}
rtems_device_driver console_close(
rtems_device_major_number major,
rtems_device_minor_number minor,
void * arg
)
{
rtems_libio_open_close_args_t *args = arg;
if((args->iop->flags&LIBIO_FLAGS_READ) &&
Console_Port_Tbl[minor].pDeviceFlow &&
Console_Port_Tbl[minor].pDeviceFlow->deviceStopRemoteTx)
{
Console_Port_Tbl[minor].pDeviceFlow->deviceStopRemoteTx(minor);
}
return rtems_termios_close (arg);
}
rtems_device_driver console_read(
rtems_device_major_number major,
rtems_device_minor_number minor,
void * arg
)
{
return rtems_termios_read (arg);
}
rtems_device_driver console_write(
rtems_device_major_number major,
rtems_device_minor_number minor,
void * arg
)
{
return rtems_termios_write (arg);
}
rtems_device_driver console_control(
rtems_device_major_number major,
rtems_device_minor_number minor,
void * arg
)
{
return rtems_termios_ioctl (arg);
}
/* PAGE
*
* console_initialize
*
* Routine called to initialize the console device driver.
*/
rtems_device_driver console_initialize(
rtems_device_major_number major,
rtems_device_minor_number minor,
void *arg
)
{
rtems_status_code status;
/*
* initialize the termio interface.
*/
rtems_termios_initialize();
Console_Port_Count=NUM_CONSOLE_PORTS;
for(minor=0;
minor<Console_Port_Count;
minor++)
{
/*
* First perform the configuration dependant probe, then the
* device dependant probe
*/
if((!Console_Port_Tbl[minor].deviceProbe ||
Console_Port_Tbl[minor].deviceProbe(minor)) &&
Console_Port_Tbl[minor].pDeviceFns->deviceProbe(minor))
{
/*
* Use this device for the console
*/
break;
}
}
if(minor==Console_Port_Count)
{
/*
* Failed to find a working device
*/
rtems_fatal_error_occurred(RTEMS_IO_ERROR);
}
Console_Port_Minor=minor;
/*
* Register Device Names
*/
status = rtems_io_register_name("/dev/console",
major,
Console_Port_Minor );
if (status != RTEMS_SUCCESSFUL)
{
rtems_fatal_error_occurred(status);
}
Console_Port_Tbl[minor].pDeviceFns->deviceInitialize(
Console_Port_Minor);
for(minor++;minor<Console_Port_Count;minor++)
{
/*
* First perform the configuration dependant probe, then the
* device dependant probe
*/
if((!Console_Port_Tbl[minor].deviceProbe ||
Console_Port_Tbl[minor].deviceProbe(minor)) &&
Console_Port_Tbl[minor].pDeviceFns->deviceProbe(minor))
{
status = rtems_io_register_name(
Console_Port_Tbl[minor].sDeviceName,
major,
minor );
if (status != RTEMS_SUCCESSFUL)
{
rtems_fatal_error_occurred(status);
}
/*
* Initialize the hardware device.
*/
Console_Port_Tbl[minor].pDeviceFns->deviceInitialize(
minor);
}
}
return RTEMS_SUCCESSFUL;
}
/* PAGE
*
* DEBUG_puts
*
* This should be safe in the event of an error. It attempts to ensure
* that no TX empty interrupts occur while it is doing polled IO. Then
* it restores the state of that external interrupt.
*
* Input parameters:
* string - pointer to debug output string
*
* Output parameters: NONE
*
* Return values: NONE
*/
void DEBUG_puts(
char *string
)
{
char *s;
uint32_t Irql;
rtems_interrupt_disable(Irql);
for ( s = string ; *s ; s++ )
{
Console_Port_Tbl[Console_Port_Minor].pDeviceFns->
deviceWritePolled(Console_Port_Minor, *s);
}
rtems_interrupt_enable(Irql);
}
/* PAGE
*
* DEBUG_puth
*
* This should be safe in the event of an error. It attempts to ensure
* that no TX empty interrupts occur while it is doing polled IO. Then
* it restores the state of that external interrupt.
*
* Input parameters:
* ulHexNum - value to display
*
* Output parameters: NONE
*
* Return values: NONE
*/
void
DEBUG_puth(
uint32_t ulHexNum
)
{
unsigned long i,d;
uint32_t Irql;
rtems_interrupt_disable(Irql);
Console_Port_Tbl[Console_Port_Minor].pDeviceFns->
deviceWritePolled(Console_Port_Minor, '0');
Console_Port_Tbl[Console_Port_Minor].pDeviceFns->
deviceWritePolled(Console_Port_Minor, 'x');
for(i=32;i;)
{
i-=4;
d=(ulHexNum>>i)&0xf;
Console_Port_Tbl[Console_Port_Minor].pDeviceFns->
deviceWritePolled(Console_Port_Minor,
(d<=9) ? d+'0' : d+'a'-0xa);
}
rtems_interrupt_enable(Irql);
}

29
c/src/lib/libbsp/powerpc/ppcn_60x/console/console.h
View File

@@ -1,29 +0,0 @@
/*
* This file contains the TTY driver table definition for the PPCn_60x
*
* This driver uses the termios pseudo driver.
*
* COPYRIGHT (c) 1998 by Radstone Technology
*
*
* THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
* KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
* AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
*
* You are hereby granted permission to use, copy, modify, and distribute
* this file, provided that this notice, plus the above copyright notice
* and disclaimer, appears in all copies. Radstone Technology will provide
* no support for this code.
*
* $Id$
*/
#include <rtems/ringbuf.h>
#include <libchip/serial.h>
#include <libchip/ns16550.h>
#include <libchip/z85c30.h>
extern console_tbl Console_Port_Tbl[];
extern console_data Console_Port_Data[];
extern unsigned long Console_Port_Count;

112
c/src/lib/libbsp/powerpc/ppcn_60x/console/debugio.c
View File

@@ -1,112 +0,0 @@
/*
* This file contains the debug IO support.
*
* COPYRIGHT (c) 1998 by Radstone Technology
*
*
* THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
* KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
* AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
*
* You are hereby granted permission to use, copy, modify, and distribute
* this file, provided that this notice, plus the above copyright notice
* and disclaimer, appears in all copies. Radstone Technology will provide
* no support for this code.
*
* COPYRIGHT (c) 1989-1997.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
#include <bsp.h>
#include <rtems/libio.h>
#include <stdlib.h>
#include <assert.h>
#include <termios.h>
#include <libchip/serial.h>
/*
* Load configuration table
*/
extern console_data Console_Port_Data[];
extern rtems_device_minor_number Console_Port_Minor;
/* PAGE
*
* DEBUG_puts
*
* This should be safe in the event of an error. It attempts to ensure
* that no TX empty interrupts occur while it is doing polled IO. Then
* it restores the state of that external interrupt.
*
* Input parameters:
* string - pointer to debug output string
*
* Output parameters: NONE
*
* Return values: NONE
*/
void DEBUG_puts(
char *string
)
{
char *s;
uint32_t Irql;
rtems_interrupt_disable(Irql);
for ( s = string ; *s ; s++ ) {
Console_Port_Tbl[Console_Port_Minor].pDeviceFns->
deviceWritePolled(Console_Port_Minor, *s);
}
rtems_interrupt_enable(Irql);
}
/* PAGE
*
* DEBUG_puth
*
* This should be safe in the event of an error. It attempts to ensure
* that no TX empty interrupts occur while it is doing polled IO. Then
* it restores the state of that external interrupt.
*
* Input parameters:
* ulHexNum - value to display
*
* Output parameters: NONE
*
* Return values: NONE
*/
void DEBUG_puth(
uint32_t ulHexNum
)
{
unsigned long i,d;
uint32_t Irql;
void (*poll)(int minor, char cChar);
poll = Console_Port_Tbl[Console_Port_Minor].pDeviceFns->deviceWritePolled;
rtems_interrupt_disable(Irql);
(*poll)(Console_Port_Minor, '0');
(*poll)(Console_Port_Minor, 'x');
for ( i=32 ; i ; ) {
i -= 4;
d = (ulHexNum>>i)&0xf;
(*poll)(Console_Port_Minor, (d<=9) ? d+'0' : d+'a'-0xa);
}
rtems_interrupt_enable(Irql);
}

1077
c/src/lib/libbsp/powerpc/ppcn_60x/console/i8042.c
View File

File diff suppressed because it is too large Load Diff

196
c/src/lib/libbsp/powerpc/ppcn_60x/console/i8042_p.h
View File

@@ -1,196 +0,0 @@
/*
* COPYRIGHT (c) 1998 by Radstone Technology
*
*
* THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
* KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
* AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
*
* You are hereby granted permission to use, copy, modify, and distribute
* this file, provided that this notice, plus the above copyright notice
* and disclaimer, appears in all copies. Radstone Technology will provide
* no support for this code.
*
*/
#ifndef _I8042_P_H_
#define _I8042_P_H_
#ifdef __cplusplus
extern "C" {
#endif
#define KBD_CTR_WRITE_COMMAND 0x60
#define KBD_CTR_READ_COMMAND 0x20
#define KBD_CTR_TEST_PASSWORD 0xA4
#define KBD_CTR_LOAD_PASSWORD 0xA5
#define KBD_CTR_ENABLE_PASSWORD 0xA6
#define KBD_CTR_DISABLE_AUX 0xA7
#define KBD_CTR_ENABLE_AUX 0xA8
#define KBD_CTR_AUXLINES_TEST 0xA9
#define KBD_CTR_SELFTEST 0xAA
#define KBD_CTR_KBDLINES_TEST 0xAB
#define KBD_CTR_DISABLE_KBD 0xAD
#define KBD_CTR_ENABLE_KBD 0xAE
#define KBD_CTR_WRITE_AUX 0xD4
#define KBD_CTR_READ_REV 0xD5
#define KBD_CTR_READ_VER 0xD6
#define KBD_CTR_READ_MODEL 0xD7
/* Keyboard Controller Data */
#define KBD_CTR_SELFTEST_PASSED 0x55
#define KBD_CTR_PASSWORD_INSTALLED 0xFA
#define KBD_CTR_PASSWORD_NOT_INSTALLED 0xF1
/* Controller Command Byte bit definitions. */
#define KBD_CMD_BYTE_DISABLE_AUX 0x20
#define KBD_CMD_BYTE_DISABLE_KBD 0x10
#define KBD_CMD_ENABLE_AUX_INT 0x02
#define KBD_CMD_ENABLE_KBD_INT 0x01
/* Keyboard Controller Status byte masks */
#define KBD_OBF_MASK 0x1 /* Output buffer full */
#define KBD_IBF_MASK 0x2 /* Input buffer full */
#define KBD_FROM_AUX_MASK 0x20 /* Byte from Aux Port. */
/* Interface Test Results */
#define INTERFACE_NO_ERROR 0x00
#define CLOCK_STUCK_LOW 0x01
#define CLOCK_STUCK_HIGH 0x02
#define DATA_STUCK_LOW 0x03
#define DATA_STUCK_HIGH 0x04
/* Timeout */
#define KBD_TIMEOUT 500000 /* Effectively ISA read access times */
/* Keyboard Commands */
#define KBD_CMD_SET_LEDS 0xed /* Set/Reset LEDs */
#define KBD_CMD_ECHO 0xee /* request keyboard echo resp. "EE" */
#define KBD_CMD_SEL_SCAN_CODE 0xf0 /* Scan codes 1,2,3 or 0 = rquest current. */
#define KBD_CMD_READ_ID 0xf2 /* Request for two byte response */
#define KBD_CMD_SET_RATE 0xf3 /* Set tellematic Rate */
#define KBD_CMD_ENABLE 0xf4 /* Clears Buffer and Starts Scanning. */
#define KBD_CMD_DISABLE 0xf5 /* reset to power up */
#define KBD_CMD_SET_DEFAULT 0xf6
#define KBD_CMD_SET_ALL_TLMTIC 0xf7 /* Set all keys telematic */
#define KBD_CMD_SET_ALL_MKBR 0xf8 /* Set all keys Make /Break */
#define KBD_CMD_SET_ALL_MAKE 0xf9 /* Set all keys Make only */
#define KBD_CMD_SET_KEY_TLMTIC 0xfb /* Set individual key telemativ */
#define KBD_CMD_SET_KEY_MKBR 0xfc /* set individual key make/break */
#define KBD_CMD_SET_KEY_MK 0xfd /* set individual key make only */
#define KBD_CMD_RESEND 0xfe /* request to resend last transfer */
#define KBD_CMD_RESET 0xff /* request to start a program reset */
#define KBD_CMD_ACK 0xfa /* keyboard ack after reset */
#define KBD_CMD_BAT 0xaa /* Keyboard Bat completion Response */
/*
* Define LED encodings for use with the KbdSetLEDs command
*/
#define KBD_LED_CAPS 0x04
#define KBD_LED_NUM 0x02
#define KBD_LED_SCROLL 0x01
/*
* Define two code scan codes in keycode order
*/
#define KEY_TWO_KEY 0xe0
#define KEY_ALT 0x38
#define KEY_CONTROL 0x1d
#define KEY_INSERT 0x52
#define KEY_DELETE 0x53
#define KEY_LEFT_ARROW 0x4b
#define KEY_HOME 0x47
#define KEY_END 0x4F
#define KEY_UP_ARROW 0x48
#define KEY_DOWN_ARROW 0x50
#define KEY_PAGE_UP 0x49
#define KEY_PAGE_DOWN 0x51
#define KEY_RIGHT_ARROW 0x4d
#define KEY_KEYPAD_SLASH 0x35
#define KEY_KEYPAD_ENTER 0x1c
#define KEY_SYS_REQUEST 0x2a
#define KEY_PRINT_SCREEN 0x37
#define KEY_LEFT_SHIFT 0x2a
#define KEY_RIGHT_SHIFT 0x36
#define KEY_TAB 0x0f
#define KEY_CAPS_LOCK 0x3a
#define KEY_NUM_LOCK 0x45
#define KEY_SCROLL_LOCK 0x46
#define KEY_ESC 0x01
#define KEY_F1 0x3b
#define KEY_F2 0x3c
#define KEY_F3 0x3d
#define KEY_F4 0x3e
#define KEY_F5 0x3f
#define KEY_F6 0x40
#define KEY_F7 0x41
#define KEY_F8 0x42
#define KEY_F9 0x43
#define KEY_F10 0x44
#define KEY_F11 0x57
#define KEY_F12 0x58
/*
* ASCII control codes
*/
#define ASCII_NUL 0x00
#define ASCII_SOH 0x01
#define ASCII_STX 0x02
#define ASCII_ETX 0x03
#define ASCII_EOT 0x04
#define ASCII_ENQ 0x05
#define ASCII_ACK 0x06
#define ASCII_BEL 0x07
#define ASCII_BS 0x08
#define ASCII_HT 0x09
#define ASCII_LF 0x0a
#define ASCII_VT 0x0b
#define ASCII_FF 0x0c
#define ASCII_CR 0x0d
#define ASCII_SO 0x0e
#define ASCII_SI 0x0f
#define ASCII_DLE 0x10
#define ASCII_XON 0x11
#define ASCII_DC1 0x11
#define ASCII_DC2 0x12
#define ASCII_XOFF 0x13
#define ASCII_DC3 0x13
#define ASCII_DC4 0x14
#define ASCII_NAK 0x15
#define ASCII_SYN 0x16
#define ASCII_ETB 0x17
#define ASCII_CAN 0x18
#define ASCII_EM 0x19
#define ASCII_SUB 0x1a
#define ASCII_ESC 0x1b
#define ASCII_FS 0x1c
#define ASCII_GS 0x1d
#define ASCII_RS 0x1e
#define ASCII_US 0x1f
#define ASCII_DEL 0x7f
#define ASCII_SYSRQ 0x80
#define ASCII_CSI 0x9b
/*
* Exported functions
*/
extern boolean i8042_probe(int minor);
extern void i8042_init(int minor);
#if CONSOLE_USE_INTERRUPTS
extern void i8042_initialize_interrupts(int minor);
#else
extern int i8042_inbyte_nonblocking_polled(
int minor
);
#endif /* CONSOLE_USE_INTERRUPTS */
#ifdef __cplusplus
}
#endif
#endif /* _I8042_P_H_ */

46
c/src/lib/libbsp/powerpc/ppcn_60x/console/i8042vga.c
View File

@@ -1,46 +0,0 @@
/*
* This file contains the TTY driver for the VGA/i8042 console
*
* COPYRIGHT (c) 1998 by Radstone Technology
*
*
* THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
* KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
* AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
*
* You are hereby granted permission to use, copy, modify, and distribute
* this file, provided that this notice, plus the above copyright notice
* and disclaimer, appears in all copies. Radstone Technology will provide
* no support for this code.
*
* This driver uses the termios pseudo driver.
*
* $Id$
*/
#include <rtems.h>
#include <bsp.h>
#include <rtems/libio.h>
#include "console.h"
#include "vga_p.h"
#include "i8042_p.h"
console_fns i8042vga_fns =
{
i8042_probe, /* deviceProbe */
NULL, /* deviceFirstOpen */
NULL, /* deviceLastClose */
#if CONSOLE_USE_INTERRUPTS
NULL, /* deviceRead */
vga_write_support, /* deviceWrite */
i8042_initialize_interrupts, /* deviceInitialize */
#else
i8042_inbyte_nonblocking_polled, /* deviceRead */
vga_write_support, /* deviceWrite */
i8042_init, /* deviceInitialize */
#endif
vga_write, /* deviceWritePolled */
FALSE, /* deviceOutputUsesInterrupts */
};

34
c/src/lib/libbsp/powerpc/ppcn_60x/console/i8042vga.h
View File

@@ -1,34 +0,0 @@
/*
* COPYRIGHT (c) 1998 by Radstone Technology
*
*
* THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
* KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
* AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
*
* You are hereby granted permission to use, copy, modify, and distribute
* this file, provided that this notice, plus the above copyright notice
* and disclaimer, appears in all copies. Radstone Technology will provide
* no support for this code.
*
* $Id$
*/
#ifndef _I8042VGA_H_
#define _I8042VGA_H_
#ifdef __cplusplus
extern "C" {
#endif
/*
* Driver function table
*/
extern console_fns i8042vga_fns;
#ifdef __cplusplus
}
#endif
#endif /* _I8042VGA_H_ */

52
c/src/lib/libbsp/powerpc/ppcn_60x/console/ns16550cfg.c
View File

@@ -1,52 +0,0 @@
/* nc16550cfg.c
*
* This include file contains all console driver definations for the nc16550
*
* COPYRIGHT (c) 1998 by Radstone Technology
*
*
* THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
* KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
* AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
*
* You are hereby granted permission to use, copy, modify, and distribute
* this file, provided that this notice, plus the above copyright notice
* and disclaimer, appears in all copies. Radstone Technology will provide
* no support for this code.
*
* COPYRIGHT (c) 1989-1997.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may in
* the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
#include <rtems.h>
#include <bsp.h>
uint8_t Read_ns16550_register(
uint32_t ulCtrlPort,
uint8_t ucRegNum
)
{
unsigned char *p = (unsigned char *)ulCtrlPort;
unsigned char ucData;
inport_byte( &p[ucRegNum], ucData );
return ucData;
}
void Write_ns16550_register(
uint32_t ulCtrlPort,
uint8_t ucRegNum,
uint8_t ucData
)
{
unsigned char *p = (unsigned char *)ulCtrlPort;
outport_byte( &p[ucRegNum], ucData );
}

54
c/src/lib/libbsp/powerpc/ppcn_60x/console/ns16550cfg.h
View File

@@ -1,54 +0,0 @@
/* nc16550cfg.h
*
* This include file contains all console driver definations for the nc16550
*
* COPYRIGHT (c) 1998 by Radstone Technology
*
*
* THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
* KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
* AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
*
* You are hereby granted permission to use, copy, modify, and distribute
* this file, provided that this notice, plus the above copyright notice
* and disclaimer, appears in all copies. Radstone Technology will provide
* no support for this code.
*
* COPYRIGHT (c) 1989-1997.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may in
* the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
#ifndef __NS16550_CONFIG_H
#define __NS16550_CONFIG_H
#ifdef __cplusplus
extern "C" {
#endif
/*
* Board specific register access routines
*/
uint8_t Read_ns16550_register(
uint32_t ulCtrlPort,
uint8_t ucRegNum
);
void Write_ns16550_register(
uint32_t ulCtrlPort,
uint8_t ucRegNum,
uint8_t ucData
);
#ifdef __cplusplus
}
#endif
#endif

355
c/src/lib/libbsp/powerpc/ppcn_60x/console/vga.c
View File

@@ -1,355 +0,0 @@
/*
* This file contains the TTY driver for VGA
*
* COPYRIGHT (c) 1998 by Radstone Technology
*
*
* THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
* KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
* AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
*
* You are hereby granted permission to use, copy, modify, and distribute
* this file, provided that this notice, plus the above copyright notice
* and disclaimer, appears in all copies. Radstone Technology will provide
* no support for this code.
*
* This driver uses the termios pseudo driver.
*/
/*-------------------------------------------------------------------------+
| (C) Copyright 1997 -
| - NavIST Group - Real-Time Distributed Systems and Industrial Automation
|
| http://pandora.ist.utl.pt
|
| Instituto Superior Tecnico * Lisboa * PORTUGAL
+--------------------------------------------------------------------------+
| Disclaimer:
|
| This file is provided "AS IS" without warranty of any kind, either
| expressed or implied.
+--------------------------------------------------------------------------+
| This code is based on:
| outch.c,v 1.4 1995/12/19 20:07:27 joel Exp - go32 BSP
| With the following copyright notice:
| **************************************************************************
| * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. *
| * On-Line Applications Research Corporation (OAR). *
| **************************************************************************
+--------------------------------------------------------------------------*/
#include <bsp.h>
#include <stdlib.h>
#include <string.h>
#include "vga_p.h"
/*-------------------------------------------------------------------------+
| Constants
+--------------------------------------------------------------------------*/
#define DISPLAY_CELL_COUNT (VGA_NUM_ROWS * VGA_NUM_COLS)
/* Number of display cells. */
#define TABSIZE 4 /* Number of spaces for TAB (\t) char. */
#define WHITE 0x0007 /* White on Black background colour. */
#define BLANK (WHITE | (' '<<8)) /* Blank character. */
/*
* This is imported from i8042.c to provide flow control
*/
extern volatile boolean bScrollLock;
/*-------------------------------------------------------------------------+
| Global Variables
+--------------------------------------------------------------------------*/
/* Physical address of start of video text memory. */
static uint16_t *videoRam = (uint16_t*)VGA_FB;
/* Pointer for current output position in display. */
static uint16_t *videoRamPtr = (uint16_t*)VGA_FB;
static uint8_t videoRows = VGA_NUM_ROWS; /* Number of rows in display. */
static uint8_t videoCols = VGA_NUM_COLS; /* Number of columns in display. */
static uint8_t cursRow = 0; /* Current cursor row. */
static uint8_t cursCol = 0; /* Current cursor column. */
/*-------------------------------------------------------------------------+
| Function: setHardwareCursorPos
| Description: Set hardware video cursor at given offset into video RAM.
| Global Variables: None.
| Arguments: videoCursor - Offset into video memory.
| Returns: Nothing.
+--------------------------------------------------------------------------*/
static inline void
setHardwareCursorPos(uint16_t videoCursor)
{
VGA_WRITE_CRTC(0x0e, (videoCursor >> 8) & 0xff);
VGA_WRITE_CRTC(0x0f, videoCursor & 0xff);
} /* setHardwareCursorPos */
/*-------------------------------------------------------------------------+
| Function: updateVideoRamPtr
| Description: Updates value of global variable "videoRamPtr" based on
| current window's cursor position.
| Global Variables: videoRamPtr, cursRow, cursCol.
| Arguments: None.
| Returns: Nothing.
+--------------------------------------------------------------------------*/
static inline void
updateVideoRamPtr(void)
{
videoRamPtr = videoRam + cursRow * videoCols + cursCol;
} /* updateVideoRamPtr */
/*-------------------------------------------------------------------------+
| Function: scrollUp
| Description: Scrolls display up n lines.
| Global Variables: None.
| Arguments: lines - number of lines to scroll.
| Returns: Nothing.
+--------------------------------------------------------------------------*/
static void
scrollUp(uint8_t lines)
{
/* Number of blank display cells on bottom of window. */
uint16_t blankCount;
/* Source and destination pointers for memory copy operations. */
uint16_t *ptrDst, *ptrSrc;
if(lines<videoRows) /* Move window's contents up. */
{
/*
* Number of non-blank cells on upper part
* of display (total - blank).
*/
uint16_t nonBlankCount;
blankCount = lines * videoCols;
nonBlankCount = DISPLAY_CELL_COUNT - blankCount;
ptrSrc = videoRam + blankCount;
ptrDst = videoRam;
while(nonBlankCount--)
{
*ptrDst++ = *ptrSrc++;
}
}
else
{
/*
* Clear the whole display.
*/
blankCount = DISPLAY_CELL_COUNT;
ptrDst = videoRam;
}
/* Fill bottom with blanks. */
while (blankCount-->0)
{
*ptrDst++ = BLANK;
}
} /* scrollUp */
/*-------------------------------------------------------------------------+
| Function: printCHAR
| Description: Print printable character to display.
| Global Variables: videoRamPtr, cursRow, cursCol.
| Arguments: c - character to write to display.
| Returns: Nothing.
+--------------------------------------------------------------------------*/
static void
printCHAR(char c)
{
*videoRamPtr++ = (c<<8) | WHITE;
cursCol++;
if(cursCol==videoCols)
{
cursCol = 0;
cursRow++;
if(cursRow==videoRows)
{
cursRow--;
scrollUp(1);
videoRamPtr -= videoCols;
}
}
} /* printCHAR */
/*-------------------------------------------------------------------------+
| Function: printBS
| Description: Print BS (BackSpace - '\b') character to display.
| Global Variables: videoRamPtr, cursRow, cursCol.
| Arguments: None.
| Returns: Nothing.
+--------------------------------------------------------------------------*/
static inline void
printBS(void)
{
/* Move cursor back one cell. */
if(cursCol>0)
{
cursCol--;
}
else if(cursRow>0)
{
cursRow--;
cursCol = videoCols - 1;
}
else
{
return;
}
/* Write a whitespace. */
*(--videoRamPtr) = BLANK;
} /* printBS */
/*-------------------------------------------------------------------------+
| Function: printHT
| Description: Print HT (Horizontal Tab - '\t') character to display.
| Global Variables: cursCol.
| Arguments: None.
| Returns: Nothing.
+--------------------------------------------------------------------------*/
static inline void
printHT(void)
{
do
{
printCHAR(' ');
}
while (cursCol % TABSIZE);
} /* printHT */
/*-------------------------------------------------------------------------+
| Function: printLF
| Description: Print LF (Line Feed - '\n') character to display.
| Global Variables: cursRow.
| Arguments: None.
| Returns: Nothing.
+--------------------------------------------------------------------------*/
static inline void
printLF(void)
{
cursRow++;
if(cursRow==videoRows)
{
cursRow--;
scrollUp(1);
}
updateVideoRamPtr();
} /* printLF */
/*-------------------------------------------------------------------------+
| Function: printCR
| Description: Print CR (Carriage Return - '\r') to display.
| Global Variables: cursCol.
| Arguments: None.
| Returns: Nothing.
+--------------------------------------------------------------------------*/
static inline void
printCR(void)
{
cursCol = 0;
updateVideoRamPtr();
} /* printCR */
/*
* Console Device Driver Entry Points
*/
void
vga_write(
int minor,
char cChar)
{
switch (cChar)
{
case '\b':
printBS();
break;
case '\t':
printHT();
break;
case '\n':
printLF();
break;
case '\r':
printCR();
break;
default:
printCHAR(cChar);
break;
}
setHardwareCursorPos(videoRamPtr - videoRam);
} /* vga_write */
/*
* vga_write_support
*
* Console Termios output entry point.
*
*/
int vga_write_support(
int minor,
const char *buf,
int len
)
{
int nwrite = 0;
while(bScrollLock)
{
/*
* The Scroll lock on the keyboard is active
*/
/*
* Yield while we wait
*/
rtems_task_wake_after(RTEMS_YIELD_PROCESSOR);
}
/*
* Write each byte in the string to the display
*/
while (nwrite<len)
{
/*
* transmit character
*/
vga_write(minor, *buf++);
nwrite++;
}
/*
* return the number of bytes written.
*/
return nwrite;
}
boolean vga_probe(int minor)
{
uint8_t ucMiscIn;
/*
* Check for presence of VGA adaptor
*/
inport_byte(0x3cc, ucMiscIn);
if(ucMiscIn!=0xff)
{
/*
* VGA device is present
*/
return(TRUE);
}
return(FALSE);
}
void vga_init(int minor)
{
scrollUp(videoRows); /* Clear entire screen */
setHardwareCursorPos(0); /* Cursor at upper left corner */
/*
* Enable the cursor
*/
VGA_WRITE_CRTC(0x0a, 0x0e); /* Crt cursor start */
}

70
c/src/lib/libbsp/powerpc/ppcn_60x/console/vga_p.h
View File

@@ -1,70 +0,0 @@
/*
* COPYRIGHT (c) 1998 by Radstone Technology
*
*
* THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
* KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
* AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
*
* You are hereby granted permission to use, copy, modify, and distribute
* this file, provided that this notice, plus the above copyright notice
* and disclaimer, appears in all copies. Radstone Technology will provide
* no support for this code.
*
*/
#ifndef _VGA_P_H_
#define _VGA_P_H_
#ifdef __cplusplus
extern "C" {
#endif
#define VGA_FB ((uint32_t)PCI_MEM_BASE+0xb8000)
#define VGA_NUM_ROWS 25
#define VGA_NUM_COLS 80
#define VGA_WRITE_SEQ(reg, val) \
outport_byte(0x3c4, reg); \
outport_byte(0x3c5, val)
#define VGA_READ_SEQ(reg, val) \
outport_byte(0x3c4, reg); \
inport_byte(0x3c5, val)
#define VGA_WRITE_CRTC(reg, val) \
outport_byte(0x3d4, reg); \
outport_byte(0x3d5, val)
#define VGA_WRITE_GRA(reg, val) \
outport_byte(0x3ce, reg); \
outport_byte(0x3cf, val)
#define VGA_WRITE_ATT(reg, val) \
{ \
volatile uint8_t ucDummy; \
inport_byte(0x3da, ucDummy); \
outport_byte(0x3c0, reg); \
outport_byte(0x3c0, val); \
}
/*
* Exported functions
*/
extern boolean vga_probe(int minor);
extern void vga_init(int minor);
extern void vga_write(
int minor,
char cChar
);
extern int vga_write_support(
int minor,
const char *buf,
int len
);
#ifdef __cplusplus
}
#endif
#endif /* _VGA_P_H_ */

95
c/src/lib/libbsp/powerpc/ppcn_60x/console/z85c30cfg.c
View File

@@ -1,95 +0,0 @@
/*
* This file contains the console driver chip level routines for the
* z85c30 chip.
*
* COPYRIGHT (c) 1998 by Radstone Technology
*
*
* THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
* KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
* AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
*
* You are hereby granted permission to use, copy, modify, and distribute
* this file, provided that this notice, plus the above copyright notice
* and disclaimer, appears in all copies. Radstone Technology will provide
* no support for this code.
*
* COPYRIGHT (c) 1989-1997.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
#include <rtems.h>
#include <bsp.h>
/*
* Read_85c30_register
*
* Read a Z85c30 register
*/
uint8_t Read_85c30_register(
uint32_t ulCtrlPort,
uint8_t ucRegNum
)
{
uint8_t ucData;
outport_byte(ulCtrlPort, ucRegNum);
inport_byte(ulCtrlPort, ucData);
return ucData;
}
/*
* Write_85c30_register
*
* Write a Z85c30 register
*/
void Write_85c30_register(
uint32_t ulCtrlPort,
uint8_t ucRegNum,
uint8_t ucData
)
{
if(ucRegNum) {
outport_byte(ulCtrlPort, ucRegNum);
}
outport_byte(ulCtrlPort, ucData);
}
/*
* Read_85c30_data
*
* Read a Z85c30 data register
*/
uint8_t Read_85c30_data(
uint32_t ulDataPort
)
{
uint8_t ucData;
inport_byte(ulDataPort, ucData);
return ucData;
}
/*
* Write_85c30_data
*
* Write a Z85c30 data register
*/
void Write_85c30_data(
uint32_t ulDataPort,
uint8_t ucData
)
{
outport_byte(ulDataPort, ucData);
}

63
c/src/lib/libbsp/powerpc/ppcn_60x/console/z85c30cfg.h
View File

@@ -1,63 +0,0 @@
/* z85c30cfg.h
*
* This include file contains all console driver definations for the z85c30
*
* COPYRIGHT (c) 1998 by Radstone Technology
*
*
* THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
* KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
* AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
*
* You are hereby granted permission to use, copy, modify, and distribute
* this file, provided that this notice, plus the above copyright notice
* and disclaimer, appears in all copies. Radstone Technology will provide
* no support for this code.
*
* COPYRIGHT (c) 1989-1997.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may in
* the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
#ifndef __Z85C30_CONFIG_H
#define __Z85C30_CONFIG_H
#ifdef __cplusplus
extern "C" {
#endif
/*
* Board specific register access routines
*/
uint8_t Read_85c30_register(
uint32_t ulCtrlPort,
uint8_t ucRegNum
);
void Write_85c30_register(
uint32_t ulCtrlPort,
uint8_t ucRegNum,
uint8_t ucData
);
uint8_t Read_85c30_data(
uint32_t ulDataPort
);
void Write_85c30_data(
uint32_t ulDataPort,
uint8_t ucData
);
#ifdef __cplusplus
}
#endif
#endif

4
c/src/lib/libbsp/powerpc/ppcn_60x/include/.cvsignore
View File

@@ -1,4 +0,0 @@
bspopts.h
bspopts.h.in
stamp-h
stamp-h.in

430
c/src/lib/libbsp/powerpc/ppcn_60x/include/bsp.h
View File

@@ -1,430 +0,0 @@
/* bsp.h
*
* This include file contains all board IO definitions.
*
* COPYRIGHT (c) 1998 by Radstone Technology
*
*
* THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
* KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
* AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
*
* You are hereby granted permission to use, copy, modify, and distribute
* this file, provided that this notice, plus the above copyright notice
* and disclaimer, appears in all copies. Radstone Technology will provide
* no support for this code.
*
* COPYRIGHT (c) 1989-1997.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may in
* the file LICENSE in this distribution or at
* http:www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef __BSP_h
#define __BSP_h
#include <bspopts.h>
#ifdef __cplusplus
extern "C" {
#endif
/*
* confdefs.h overrides for this BSP:
* - termios serial ports (defaults to 1)
* - Interrupt stack space is not minimum if defined.
*/
#define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 2
#define CONFIGURE_INTERRUPT_STACK_MEMORY (32 * 1024)
/* Define processor identification. */
#define MPC601 1
#define MPC603 3
#define MPC604 4
#define MPC603e 6
#define MPC603ev 7
#define MPC604e 9
#ifdef ASM
/* Definition of where to store registers in alignment handler */
#define ALIGN_REGS 0x0140
/* BAT register definitions for the MPC603 and MPC604. */
/* Define bit fields for upper MPC603/4 BAT registers. */
#define BEPI_FIELD_60X 0xFFFE0000
#define VALID_SUPERVISOR 0x2
#define VALID_PROBLEM 0x1
#define KEY_USER_60X 0x1
#define BL_128K 0x0
#define BL_256K (0x1<2)
#define BL_512K (0x3<2)
#define BL_1M (0x7<2)
#define BL_2M (0xF<2)
#define BL_4M (0x1F<2)
#define BL_8M (0x3F<2)
#define BL_16M (0x7F<2)
#define BL_32M (0xFF<2)
#define BL_64M (0x1FF<2)
#define BL_128M (0x3FF<2)
#define BL_256M (0x7FF<2)
/* Define bit fields for lower MPC603/4 BAT registers. */
#define BRPN_FIELD_60X 0xFFFE0000
/* Common defines for BAT registers. */
/* Depending on the processor, the following may be in the upper */
/* and lower BAT register. */
#define WRITE_THRU 0x40
#define WRITE_BK 0x0
#define COHERE_EN 0x10
#define COHERE_DIS 0x0
#define CACHE_DIS 0x20
#define CACHE_EN 0x0
#define GUARDED_EN 0x8
#define GUARDED_DIS 0x0
#define PP_00 0x0
#define PP_01 0x1
#define PP_10 0x2
#define PP_11 0x3
/* HID0 definitions for MPC603 and MPC604 */
#define HID0 0x3f0 /* HID0 Special Purpose Register # */
/* HID1 definitions for MPC603e and MPC604e */
#define HID1 0x3f1 /* HID1 Special Purpose Register # */
#define H0_603_ICFI 0x0800 /* HID0 I-Cache Flash Invalidate */
#define H0_603_DCI 0x0400 /* HID0 D-Cache Flash Invalidate */
#define H0_60X_ICE 0x8000 /* HID0 I-Cache Enable */
#define H0_60X_DCE 0x4000 /* HID0 D-Cache Enable */
#define H0_604_BHTE 0x0004 /* HID0 Branch History Table enable */
#define H0_604_SIED 0x0080 /* HID0 Serial Instruction Execution */
#define H0_604_ICIA 0x0800 /* HID0 I-Cache Invalidate All */
#define H0_604_DCIA 0x0400 /* HID0 D-Cache Invalidate All */
#define BAT0U 528
#define BAT0L 529
#define BAT1U 530
#define BAT1L 531
#define BAT2U 532
#define BAT2L 533
#define BAT3U 534
#define BAT3L 535
#define SPRG0 272
#define SPRG1 273
/* MSR bit settings */
#define MSR_LE 0x0001
#define MSR_RI 0x0002
#define MSR_DR 0x0010
#define MSR_IR 0x0020
#define MSR_IP 0x0040
#define MSR_FE1 0x0100
#define MSR_BE 0x0200
#define MSR_SE 0x0400
#define MSR_FE0 0x0800
#define MSR_ME 0x1000
#define MSR_FP 0x2000
#define MSR_PR 0x4000
#define MSR_EE 0x8000
#define MSR_ILE 0x0001 /* Upper 16 bits */
#define MSR_POW 0x0004 /* Upper 16 bits */
#else
#include <rtems.h>
#include <rtems/console.h>
#include <rtems/clockdrv.h>
#include <rtems/iosupp.h>
#include <tod.h>
#include <nvram.h>
/*
* PPCn_60x Interupt Definations.
*/
#define PPCN_60X_8259_IRQ_BASE ( PPC_IRQ_LAST + 1 )
/*
* 8259 IRQ definations.
*/
#define PPCN_60X_IRQ_SYS_TIMER (PPCN_60X_8259_IRQ_BASE + 0)
#define PPCN_60X_IRQ_KBD (PPCN_60X_8259_IRQ_BASE + 1)
#define PPCN_60X_IRQ_COM2 (PPCN_60X_8259_IRQ_BASE + 3)
#define PPCN_60X_IRQ_COM1 (PPCN_60X_8259_IRQ_BASE + 4)
#define PPCN_60X_IRQ_CIO (PPCN_60X_8259_IRQ_BASE + 5)
#define PPCN_60X_IRQ_FDC (PPCN_60X_8259_IRQ_BASE + 6)
#define PPCN_60X_IRQ_LPT (PPCN_60X_8259_IRQ_BASE + 7)
#define PPCN_60X_IRQ_RTC (PPCN_60X_8259_IRQ_BASE + 8)
#define PPCN_60X_IRQ_COM3_4 (PPCN_60X_8259_IRQ_BASE + 10)
#define PPCN_60X_IRQ_MSE (PPCN_60X_8259_IRQ_BASE + 12)
#define PPCN_60X_IRQ_SCSI (PPCN_60X_8259_IRQ_BASE + 13)
/*
* PCI interrupts as read from line register map directly to
* ISA interrupt lines 9, 11, 14 and 15.
*/
#define PPCN_60X_IRQ_PCI(n) (PPCN_60X_8259_IRQ_BASE + (n))
#define MAX_BOARD_IRQS (PPCN_60X_8259_IRQ_BASE + 15)
#define ISA8259_M_CTRL 0x20
#define ISA8259_S_CTRL 0xa0
#define ISA8259_M_MASK 0x21
#define ISA8259_S_MASK 0xa1
#define ISA8259_M_ELCR 0x4d0
#define ISA8259_S_ELCR 0x4d1
#define ELCRS_INT15_LVL 0x80
#define ELCRS_INT14_LVL 0x40
#define ELCRS_INT12_LVL 0x10
#define ELCRS_INT11_LVL 0x08
#define ELCRS_INT10_LVL 0x04
#define ELCRS_INT9_LVL 0x02
#define ELCRS_INT8_LVL 0x01
#define ELCRM_INT7_LVL 0x80
#define ELCRM_INT5_LVL 0x20
#define NONSPECIFIC_EOI 0x20
extern void En_Ext_Interrupt(int level);
extern void Dis_Ext_Interrupt(int level);
#define IRQ_VECTOR_BASE 0xbffffff0
/*
* i8042 addresses
*/
#define I8042_DATA 0x60
#define I8042_CS 0x64
/*
* ns16550 addresses
*/
#define NS16550_PORT_A 0x3f8
#define NS16550_PORT_B 0x2f8
/*
* z85c30 addresses
*/
#define Z85C30_CTRL_B 0x840
#define Z85C30_DATA_B 0x841
#define Z85C30_CTRL_A 0x842
#define Z85C30_DATA_A 0x843
/*
* Z85C30 Definations for the 422 interface.
*/
#define Z85C30_CLOCK 14745600
#define PCI_SYS_MEM_BASE 0x80000000
#define PCI_MEM_BASE 0xc0000000
#define PCI_IO_BASE 0x80000000
#define EIEIO asm volatile("eieio")
/*
* As ports are all little endian we will perform swaps here on 16 and 32
* bit transfers
*/
extern uint16_t Swap16(uint16_t usVal);
extern uint32_t Swap32(uint32_t ulVal);
#define outport_byte(port, val) \
EIEIO; \
*(volatile uint8_t*)(PCI_IO_BASE+ \
(unsigned long)(port))=(val)
#define outport_16(port, val) \
EIEIO; \
*(volatile uint16_t*)(PCI_IO_BASE+ \
(unsigned long)(port))=Swap16(val)
#define outport_32(port, val) \
EIEIO; \
*(volatile uint32_t*)(PCI_IO_BASE+ \
(unsigned long)(port))=Swap32(val)
#define inport_byte(port, val) \
EIEIO; \
(val)=*(volatile uint8_t*)(PCI_IO_BASE+ \
(unsigned long)(port))
#define inport_16(port, val) \
EIEIO; \
(val)=Swap16(*(volatile uint16_t*)(PCI_IO_BASE+ \
(unsigned long)(port)))
#define inport_32(port, val) \
EIEIO; \
(val)=Swap32(*(volatile uint32_t*)(PCI_IO_BASE+ \
(unsigned long)(port)))
/*
* System Planar Board Registers
*/
typedef volatile struct _PLANARREGISTERS{
uint8_t Reserved0[0x803]; /* Offset 0x000 */
uint8_t SimmId; /* Offset 0x803 */
uint8_t SimmPresent; /* Offset 0x804 */
uint8_t Reserved1[3];
uint8_t HardfileLight; /* Offset 0x808 */
uint8_t Reserved2[3];
uint8_t EquipmentPresent1; /* Offset 0x80C */
uint8_t Reserved3;
uint8_t EquipmentPresent2; /* Offset 0x80e */
uint8_t Reserved4;
uint8_t PasswordProtect1; /* Offset 0x810 */
uint8_t Reserved5;
uint8_t PasswordProtect2; /* Offset 0x812 */
uint8_t Reserved6;
uint8_t L2Flush; /* Offset 0x814 */
uint8_t Reserved7[3];
uint8_t Keylock; /* Offset 0x818 */
uint8_t Reserved8[0x3c];
uint8_t BoardRevision; /* Offset 0x854 */
uint8_t Reserved9[0xf];
uint8_t BoardID; /* Offset 0x864 */
uint8_t Reserved10;
uint8_t MotherboardMemoryType; /* Offset 0x866 */
uint8_t Reserved11;
uint8_t MezzanineMemoryType; /* Offset 0x868 */
} PLANARREGISTERS, *PPLANARREGISTERS;
extern unsigned char ucSystemType;
extern unsigned char ucBoardRevMaj;
extern unsigned char ucBoardRevMin;
extern unsigned long ulMemorySize;
extern unsigned long ulCpuBusClock;
#define SYS_TYPE_PPC1 0
#define SYS_TYPE_PPC2 1
#define SYS_TYPE_PPC1a 2
#define SYS_TYPE_PPC2a 3
#define SYS_TYPE_PPC4 4
/*
* PCI initialisation
*/
void pci_initialize(void);
/*
* VME initiaisation
*/
void InitializeUniverse();
/*
* RTC initialisation
*/
void InitializeRTC(void);
/*
* NvRAM initialisation
*/
void InitializeNvRAM(void);
/*
* BSP_TIMER_AVG_OVERHEAD and BSP_TIMER_LEAST_VALID for the shared timer
* driver.
*/
#define BSP_TIMER_AVG_OVERHEAD 4 /* It typically takes xx clicks */
/* to start/stop the timer. */
#define BSP_TIMER_LEAST_VALID 1 /* Don't trust a value lower than this */
/*
* Convert decrement value to tenths of microsecnds (used by
* shared timer driver).
*
* + There are 4 bus cycles per click
* + We return value in 1/10 microsecond units.
* Modified following equation to integer equation to remove
* floating point math.
* (int) ((float)(_value) / ((66.67 * 0.1) / 4.0))
*/
#define BSP_Convert_decrementer( _value ) \
(int) (((_value) * 4000) / (ulCpuBusClock/10000))
/* Constants */
/*
* Device Driver Table Entries
*/
/*
* NOTE: Use the standard Console driver entry
*/
/*
* NOTE: Use the standard Clock driver entry
*/
/*
* How many libio files we want
*/
#define BSP_LIBIO_MAX_FDS 20
/* functions */
void bsp_start( void );
void bsp_cleanup( void );
rtems_isr_entry set_vector( /* returns old vector */
rtems_isr_entry handler, /* isr routine */
rtems_vector_number vector, /* vector number */
int type /* RTEMS or RAW intr */
);
/*
* spurious.c
*/
rtems_isr bsp_stub_handler(
rtems_vector_number trap
);
rtems_isr bsp_spurious_handler(
rtems_vector_number trap
);
void bsp_spurious_initialize();
/*
* genvec.c
*/
void set_EE_vector(
rtems_isr_entry handler, /* isr routine */
rtems_vector_number vector /* vector number */
);
void initialize_external_exception_vector();
/*
* console.c
*/
void DEBUG_puts( char *string );
void DEBUG_puth( uint32_t ulHexNum );
void BSP_fatal_return( void );
extern rtems_configuration_table BSP_Configuration; /* owned by BSP */
extern rtems_cpu_table Cpu_table; /* owned by BSP */
extern uint32_t bsp_isr_level;
#endif /* ASM */
#ifdef __cplusplus
}
#endif
#endif
/* end of include file */

41
c/src/lib/libbsp/powerpc/ppcn_60x/include/extisrdrv.h
View File

@@ -1,41 +0,0 @@
/* extisrdrv.h
*
* This file describes the external interrupt driver
*
*/
#ifndef __EXT_ISR_DRIVER_H
#define __EXT_ISR_DRIVER_H
#ifdef __cplusplus
extern "C" {
#endif
/* variables */
extern rtems_device_major_number rtems_externalISR_major;
extern rtems_device_minor_number rtems_externalISR_minor;
/* default external ISR driver entry */
#define EXTISR_DRIVER_TABLE_ENTRY \
{ ExternalISR_initialize, NULL, NULL, NULL, NULL, ExternalISR_control }
rtems_device_driver ExternalISR_initialize(
rtems_device_major_number,
rtems_device_minor_number,
void *
);
rtems_device_driver ExternalISR_control(
rtems_device_major_number major,
rtems_device_minor_number minor,
void *pargp
);
#ifdef __cplusplus
}
#endif
#endif
/* end of include file */

59
c/src/lib/libbsp/powerpc/ppcn_60x/include/nvram.h
View File

@@ -1,59 +0,0 @@
/*
* This file contains the NvRAM driver definitions for the PPCn_60x
*
* COPYRIGHT (c) 1998 by Radstone Technology
*
*
* THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
* KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
* AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
*
* You are hereby granted permission to use, copy, modify, and distribute
* this file, provided that this notice, plus the above copyright notice
* and disclaimer, appears in all copies. Radstone Technology will provide
* no support for this code.
*
*/
#ifndef _NVRAM_H
#define _NVRAM_H
#ifdef __cplusplus
extern "C" {
#endif
/*
* This initializes the NvRAM driver
*/
void InitializeNvRAM(void);
/*
* These routines access data in the NvRAM's OS area
*/
extern rtems_status_code ReadNvRAM8(uint32_t ulOffset, uint8_t *pucData);
extern rtems_status_code WriteNvRAM8(uint32_t ulOffset, uint8_t ucValue);
extern rtems_status_code ReadNvRAM16(uint32_t ulOffset, uint16_t *pusData);
extern rtems_status_code WriteNvRAM16(uint32_t ulOffset, uint16_t usValue);
extern rtems_status_code ReadNvRAM32(uint32_t ulOffset, uint32_t *pulData);
extern rtems_status_code WriteNvRAM32(uint32_t ulOffset, uint32_t ulValue);
rtems_status_code ReadNvRAMBlock(
uint32_t ulOffset, uint8_t *pucData, uint32_t length);
rtems_status_code WriteNvRAMBlock(
uint32_t ulOffset, uint8_t *ucValue, uint32_t length);
/*
* This routine returns the size of the NvRAM
*/
extern uint32_t SizeNvRAM();
/*
* This routine commits changes to the NvRAM
*/
extern void CommitNvRAM();
#ifdef __cplusplus
}
#endif
#endif /* _NVRAM_H */

322
c/src/lib/libbsp/powerpc/ppcn_60x/include/pci.h
View File

@@ -1,322 +0,0 @@
/*
* COPYRIGHT (c) 1998 by Radstone Technology
*
*
* THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
* KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
* AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
*
* You are hereby granted permission to use, copy, modify, and distribute
* this file, provided that this notice, plus the above copyright notice
* and disclaimer, appears in all copies. Radstone Technology will provide
* no support for this code.
*
*/
#ifndef _PCI_H_
#define _PCI_H_
/*
* PCI Configuration space definitions
*/
#define PCI_CONFIG_ADDR 0xcf8
#define PCI_CONFIG_DATA 0xcfc
#define PCI_MAX_DEVICES 16
#define PCI_MAX_FUNCTIONS 8
#define PCI_CONFIG_VENDOR_LOW 0x00
#define PCI_CONFIG_VENDOR_HIGH 0x01
#define PCI_CONFIG_DEVICE_LOW 0x02
#define PCI_CONFIG_DEVICE_HIGH 0x03
#define PCI_CONFIG_COMMAND 0x04
#define PCI_CONFIG_STATUS 0x06
#define PCI_CONFIG_REVISIONID 0x08
#define PCI_CONFIG_CLASS_CODE_L 0x09
#define PCI_CONFIG_CLASS_CODE_M 0x0a
#define PCI_CONFIG_CLASS_CODE_U 0x0b
#define PCI_CONFIG_CACHE_LINE_SIZE 0x0c
#define PCI_CONFIG_LATENCY_TIMER 0x0d
#define PCI_CONFIG_HEADER_TYPE 0x0e
#define PCI_CONFIG_BIST 0x0f
#define PCI_CONFIG_BAR_0 0x10
#define PCI_CONFIG_BAR_1 0x14
#define PCI_CONFIG_BAR_2 0x18
#define PCI_CONFIG_BAR_3 0x1c
#define PCI_CONFIG_BAR_4 0x20
#define PCI_CONFIG_BAR_5 0x24
#define PCI_CONFIG_SUBVENDOR_LOW 0x2c
#define PCI_CONFIG_SUBVENDOR_HIGH 0x2d
#define PCI_CONFIG_SUBDEVICE_LOW 0x2e
#define PCI_CONFIG_SUBDEVICE_HIGH 0x2f
#define PCI_CONFIG_ROM_BAR 0x30
#define PCI_CONFIG_INTERRUPTLINE 0x3c
#define PCI_CONFIG_INTERRUPTPIN 0x3d
#define PCI_CONFIG_MIN_GNT 0x3e
#define PCI_CONFIG_MAX_LAT 0x3f
/*
* PCI Status register definitions
*/
#define PCI_STATUS_66MHZ_CAPABLE 0x0020
#define PCI_STATUS_UDF_SUPPORTED 0x0040
#define PCI_STATUS_FAST_BACK_TO_BACK 0x0080
#define PCI_STATUS_DET_DPAR_ERR 0x0100
#define PCI_STATUS_DEVSEL_MSK 0x0600
#define PCI_STATUS_DEVSEL_SLOW 0x0400
#define PCI_STATUS_DEVSEL_MED 0x0200
#define PCI_STATUS_DEVSEL_FAST 0x0000
#define PCI_STATUS_SIG_TARG_ABT 0x0800
#define PCI_STATUS_REC_TARG_ABT 0x1000
#define PCI_STATUS_REC_MAST_ABT 0x2000
#define PCI_STATUS_SIG_SYS_ERR 0x4000
#define PCI_STATUS_DET_PAR_ERR 0x8000
/*
* PCI Enable register definitions
*/
#define PCI_ENABLE_IO_SPACE 0x0001
#define PCI_ENABLE_MEMORY_SPACE 0x0002
#define PCI_ENABLE_BUS_MASTER 0x0004
#define PCI_ENABLE_SPECIAL_CYCLES 0x0008
#define PCI_ENABLE_WRITE_AND_INVALIDATE 0x0010
#define PCI_ENABLE_VGA_COMPATIBLE_PALETTE 0x0020
#define PCI_ENABLE_PARITY 0x0040
#define PCI_ENABLE_WAIT_CYCLE 0x0080
#define PCI_ENABLE_SERR 0x0100
#define PCI_ENABLE_FAST_BACK_TO_BACK 0x0200
/*
* Bit encode for PCI_CONFIG_HEADER_TYPE register
*/
#define PCI_MULTI_FUNCTION 0x80
/*
* Bit encodes for PCI Config BaseAddressesRegisters (BARs)
*/
#define PCI_ADDRESS_IO_SPACE 0x00000001
#define PCI_ADDRESS_MEMORY_TYPE_MASK 0x00000007
#define PCI_ADDRESS_MEMORY_PREFETCHABLE 0x00000008
#define PCI_TYPE_32BIT 0
#define PCI_TYPE_20BIT 2
#define PCI_TYPE_64BIT 4
/*
* Bit encodes for PCI Config ROMBaseAddresses
*/
#define PCI_ROMADDRESS_ENABLED 0x00000001
/*
* PCI Bridge Configuration space definitions
*/
#define PCI_BRIDGE_PRIMARY_BUS 0x18
#define PCI_BRIDGE_SECONDARY_BUS 0x19
#define PCI_BRIDGE_SUBORDINATE_BUS 0x1a
#define PCI_BRIDGE_SECONDARY_LAT 0x1b
#define PCI_BRIDGE_IO_BASE 0x1c
#define PCI_BRIDGE_IO_LIMIT 0x1d
#define PCI_BRIDGE_SECONDARY_STATUS 0x1e
#define PCI_BRIDGE_MEMORY_BASE 0x20
#define PCI_BRIDGE_MEMORY_LIMIT 0x22
#define PCI_BRIDGE_PRE_MEMORY_BASE 0x24
#define PCI_BRIDGE_PRE_MEMORY_LIMIT 0x26
#define PCI_BRIDGE_PRE_BASE_U 0x28
#define PCI_BRIDGE_PRE_LIMIT_U 0x2c
#define PCI_BRIDGE_IO_BASE_U 0x30
#define PCI_BRIDGE_IO_LIMIT_U 0x32
#define PCI_BRIDGE_ROM_BAR 0x38
#define PCI_BRIDGE_CONTROL 0x3e
/*
* PCI Bridge Control register definitions
*/
#define PCI_BRIDGE_PAR_ERR_RESPONSE 0x01
#define PCI_BRIDGE_S_SERR_L_FWD_EN 0x02
#define PCI_BRIDGE_ENABLE_ISA 0x04
#define PCI_BRIDGE_ENABLE_VGA 0x08
#define PCI_BRIDGE_MASTER_ABORT 0x20
#define PCI_BRIDGE_SECONDARY_RESET 0x40
#define PCI_BRIDGE_BACK_TO_BACK_EN 0x80
/*
* PCI IO address forwarding capability
*/
#define PCI_BRIDGE_IO_CAPABILITY 0x0f
#define PCI_BRIDGE_IO_16BIT 0x00
#define PCI_BRIDGE_IO_32BIT 0x01
/*
* Class codes
*/
#define PCI_BASE_CLASS_NULL 0x00
#define PCI_BASE_CLASS_STORAGE 0x01
#define PCI_BASE_CLASS_NETWORK 0x02
#define PCI_BASE_CLASS_DISPLAY 0x03
#define PCI_BASE_CLASS_MULTIMEDIA 0x04
#define PCI_BASE_CLASS_MEMORY 0x05
#define PCI_BASE_CLASS_BRIDGE 0x06
#define PCI_BASE_CLASS_COM_CTRL 0x07
#define PCI_BASE_CLASS_BASEPERIPH 0x08
#define PCI_BASE_CLASS_INPUTDEV 0x09
#define PCI_BASE_CLASS_DOCKING 0x0a
#define PCI_BASE_CLASS_PROC 0x0b
#define PCI_BASE_CLASS_SERBUSCTRL 0x0c
#define PCI_BASE_CLASS_UNDEFINED 0xff
#define PCI_SUB_CLASS_NULL_NVGA 0x00
#define PCI_IF_CLASS_DISPLAY_VGA 0x00
#define PCI_IF_CLASS_DISPLAY_VGA8514 0x01
#define PCI_SUB_CLASS_NULL_VGA 0x01
#define PCI_SUB_CLASS_STORAGE_SCSI 0x00
#define PCI_SUB_CLASS_STORAGE_IDE 0x01
#define PCI_SUB_CLASS_STORAGE_FLOPPY 0x02
#define PCI_SUB_CLASS_STORAGE_IPI 0x03
#define PCI_SUB_CLASS_STORAGE_RAID 0x04
#define PCI_SUB_CLASS_STORAGE_OTHER 0x80
#define PCI_SUB_CLASS_NETWORK_ETH 0x00
#define PCI_SUB_CLASS_NETWORK_TOKEN 0x01
#define PCI_SUB_CLASS_NETWORK_FDDI 0x02
#define PCI_SUB_CLASS_NETWORK_ATM 0x03
#define PCI_SUB_CLASS_NETWORK_OTHER 0x80
#define PCI_SUB_CLASS_DISPLAY_VGA 0x00
#define PCI_SUB_CLASS_DISPLAY_XGA 0x01
#define PCI_SUB_CLASS_DISPLAY_OTHER 0x80
#define PCI_SUB_CLASS_MULTIMEDIA_VIDEO 0x00
#define PCI_SUB_CLASS_MULTIMEDIA_AUDIO 0x01
#define PCI_SUB_CLASS_MULTIMEDIA_OTHER 0x80
#define PCI_SUB_CLASS_MEMORY_RAM 0x00
#define PCI_SUB_CLASS_MEMORY_FLASH 0x01
#define PCI_SUB_CLASS_MEMORY_OTHER 0x80
#define PCI_SUB_CLASS_BRIDGE_HOST 0x00
#define PCI_SUB_CLASS_BRIDGE_ISA 0x01
#define PCI_SUB_CLASS_BRIDGE_EISA 0x02
#define PCI_SUB_CLASS_BRIDGE_MC 0x03
#define PCI_SUB_CLASS_BRIDGE_PCI 0x04
#define PCI_SUB_CLASS_BRIDGE_PCMCIA 0x05
#define PCI_SUB_CLASS_BRIDGE_NUBUS 0x06
#define PCI_SUB_CLASS_BRIDGE_CARDBUS 0x07
#define PCI_SUB_CLASS_BRIDGE_OTHER 0x80
#define PCI_SUB_CLASS_COM_CTRL_SERIAL 0x00
#define PCI_IF_CLASS_COM_SER_XT 0x00
#define PCI_IF_CLASS_COM_SER_16450 0x01
#define PCI_IF_CLASS_COM_SER_16550 0x02
#define PCI_SUB_CLASS_COM_CTRL_PARALLEL 0x01
#define PCI_IF_CLASS_COM_PAR 0x00
#define PCI_IF_CLASS_COM_PAR_BI 0x01
#define PCI_IF_CLASS_COM_PAR_ECP 0x02
#define PCI_SUB_CLASS_COM_CTRL_OTHER 0x80
#define PCI_SUB_CLASS_BASEPERIPH_PIC 0x00
#define PCI_IF_CLASS_BASEPERIPH_PIC 0x00
#define PCI_IF_CLASS_BASEPERIPH_PIC_ISA 0x01
#define PCI_IF_CLASS_BASEPERIPH_PIC_EISA 0x02
#define PCI_SUB_CLASS_BASEPERIPH_DMA 0x01
#define PCI_IF_CLASS_BASEPERIPH_DMA 0x00
#define PCI_IF_CLASS_BASEPERIPH_DMA_ISA 0x01
#define PCI_IF_CLASS_BASEPERIPH_DMA_EISA 0x02
#define PCI_SUB_CLASS_BASEPERIPH_TIMER 0x02
#define PCI_IF_CLASS_BASEPERIPH_TIMER 0x00
#define PCI_IF_CLASS_BASEPERIPH_TIMER_ISA 0x01
#define PCI_IF_CLASS_BASEPERIPH_TIMER_EISA 0x02
#define PCI_SUB_CLASS_BASEPERIPH_RTC 0x03
#define PCI_IF_CLASS_BASEPERIPH_RTC 0x00
#define PCI_IF_CLASS_BASEPERIPH_RTC_ISA 0x01
#define PCI_SUB_CLASS_BASEPERIPH_OTHER 0x80
#define PCI_SUB_CLASS_INPUTDEV_KEYBOARD 0x00
#define PCI_SUB_CLASS_INPUTDEV_PEN 0x01
#define PCI_SUB_CLASS_INPUTDEV_MOUSE 0x02
#define PCI_SUB_CLASS_INPUTDEV_OTHER 0x80
#define PCI_SUB_CLASS_DOCKING_GENERIC 0x00
#define PCI_SUB_CLASS_DOCKING_OTHER 0x80
#define PCI_SUB_CLASS_PROC_386 0x00
#define PCI_SUB_CLASS_PROC_486 0x01
#define PCI_SUB_CLASS_PROC_PENTIUM 0x02
#define PCI_SUB_CLASS_PROC_ALPHA 0x10
#define PCI_SUB_CLASS_PROC_POWERPC 0x20
#define PCI_SUB_CLASS_PROC_COPROC 0x40
#define PCI_SUB_CLASS_SERBUSCTRL_FIREWIRE 0x00
#define PCI_SUB_CLASS_SERBUSCTRL_ACCESS 0x01
#define PCI_SUB_CLASS_SERBUSCTRL_SSA 0x02
#define PCI_SUB_CLASS_SERBUSCTRL_USB 0x03
#define PCI_SUB_CLASS_SERBUSCTRL_FIBRECHAN 0x04
#define PCI_INVALID_VENDORDEVICEID 0xffffffff
#define PCI_ID(v, d) ((d << 16) | v)
/*
* PCI access functions
*/
extern rtems_status_code PCIConfigWrite8(
uint8_t ucBusNumber,
uint8_t ucSlotNumber,
uint8_t ucFunctionNumber,
uint8_t ucOffset,
uint8_t ucValue
);
extern rtems_status_code PCIConfigWrite16(
uint8_t ucBusNumber,
uint8_t ucSlotNumber,
uint8_t ucFunctionNumber,
uint8_t ucOffset,
uint16_t usValue
);
extern rtems_status_code PCIConfigWrite32(
uint8_t ucBusNumber,
uint8_t ucSlotNumber,
uint8_t ucFunctionNumber,
uint8_t ucOffset,
uint32_t ulValue
);
extern rtems_status_code PCIConfigRead8(
uint8_t ucBusNumber,
uint8_t ucSlotNumber,
uint8_t ucFunctionNumber,
uint8_t ucOffset,
uint8_t *pucValue
);
extern rtems_status_code PCIConfigRead16(
uint8_t ucBusNumber,
uint8_t ucSlotNumber,
uint8_t ucFunctionNumber,
uint8_t ucOffset,
uint16_t *pusValue
);
extern rtems_status_code PCIConfigRead32(
uint8_t ucBusNumber,
uint8_t ucSlotNumber,
uint8_t ucFunctionNumber,
uint8_t ucOffset,
uint32_t *pulValue
);
/*
* Return the number of PCI busses in the system
*/
extern uint8_t BusCountPCI();
#endif /* _PCI_H_ */

48
c/src/lib/libbsp/powerpc/ppcn_60x/include/tm27.h
View File

@@ -1,48 +0,0 @@
/*
* tm27.h
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
#ifndef _RTEMS_TMTEST27
#error "This is an RTEMS internal file you must not include directly."
#endif
#ifndef __tm27_h
#define __tm27_h
/*
* Stuff for Time Test 27
*/
#define MUST_WAIT_FOR_INTERRUPT 1
#define Install_tm27_vector( _handler ) \
set_vector( (_handler), PPC_IRQ_DECREMENTER, 1 )
#define Cause_tm27_intr() \
do { \
uint32_t _clicks = 8; \
asm volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \
} while (0)
#define Clear_tm27_intr() \
do { \
uint32_t _clicks = 0xffffffff; \
asm volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \
} while (0)
#define Lower_tm27_intr() \
do { \
uint32_t _msr = 0; \
_ISR_Set_level( 0 ); \
asm volatile( "mfmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \
_msr |= 0x8002; \
asm volatile( "mtmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \
} while (0)
#endif

1010
c/src/lib/libbsp/powerpc/ppcn_60x/network/amd79c970.c
View File

File diff suppressed because it is too large Load Diff

424
c/src/lib/libbsp/powerpc/ppcn_60x/network/amd79c970.h
View File

@@ -1,424 +0,0 @@
/*
* COPYRIGHT (c) 1998 by Radstone Technology
*
*
* THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
* KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
* AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
*
* You are hereby granted permission to use, copy, modify, and distribute
* this file, provided that this notice, plus the above copyright notice
* and disclaimer, appears in all copies. Radstone Technology will provide
* no support for this code.
*
*/
#ifndef _PCNET_H
#define _PCNET_H
/*
* IO space structure for the AMD79C970 device
*/
typedef volatile struct pc_net
{
union
{
struct {
uint16_t aprom[8]; /* 0x00 */
uint16_t rdp; /* 0x10 */
uint16_t rap; /* 0x14 */
uint16_t reset; /* 0x18 */
uint16_t bdp; /* 0x1C */
} wio;
struct {
uint32_t aprom[4]; /* 0x00 */
uint32_t rdp; /* 0x10 */
uint32_t rap; /* 0x12 */
uint32_t reset; /* 0x14 */
uint32_t bdp; /* 0x16 */
} dwio;
} u;
} pc_net_t;
/*
* The EEPROM is 2Kbit (128bytes)
*/
#define EEPROM_SIZE 128
#define EEPROM_HEAD_SIZE 36
typedef struct pc_net_eeprom {
uint8_t EthNumber[6];
uint16_t Reserved1; /* Must be 0x0000 */
uint16_t Reserved2; /* Must be 0x1000 */
uint16_t User1;
uint16_t checksum;
uint16_t Reserved3; /* Must be 0x5757 */
uint16_t bcr16;
uint16_t bcr17;
uint16_t bcr18;
uint16_t bcr2;
uint16_t bcr21;
uint16_t Reserved4; /* Must be 0x0000 */
uint16_t Reserved5; /* Must be 0x0000 */
uint8_t Reserved6; /* Must be 0x00 */
uint8_t checksumAdjust;
uint16_t Reserved7; /* Must be 0x0000 */
uint16_t crc; /* CCITT checksum from Serial[] onwards */
uint8_t Serial[16]; /* Radstone Serial Number */
} pc_net_eeprom_t;
/*
* PCnet-PCI Single Chip Ethernet Controller for PCI Local Bus
*/
/*
* Register and bit definitions
*/
#define CSR0 0
#define CSR1 1
#define CSR2 2
#define CSR3 3
#define CSR4 4
#define CSR5 5
#define CSR6 6
#define CSR7 7
#define CSR8 8
#define CSR9 9
#define CSR15 15
#define CSR47 47
#define CSR82 82 /* Bus Activity Timer */
#define CSR100 100 /* Memory Error Timeout register */
#define CSR114 114
#define CSR122 122 /* Receiver Packet Alignment Register */
#define BCR2 2 /* Misc. Configuration */
#define BCR18 18 /* Bus size and burst control */
#define DEFAULT_BCR18 0x2162 /* default BCR18 value - was 0x21e2*/
#define BCR19 19
#define BCR20 20 /* Software Style */
#define BCR21 21
#define APROM0 0x00
#define APROM1 0x04
#define APROM2 0x08
/*
* CSR0: Bit definitions
*/
#define CSR0_ERR 0x8000 /* error summary */
#define CSR0_BABL 0x4000 /* babble error */
#define CSR0_CERR 0x2000 /* collision error */
#define CSR0_MISS 0x1000 /* missed packet */
#define CSR0_MERR 0x0800 /* memory error */
#define CSR0_RINT 0x0400 /* receiver interrupt */
#define CSR0_TINT 0x0200 /* transmitter interrupt */
#define CSR0_IDON 0x0100 /* initialization done */
#define CSR0_INTR 0x0080 /* interrupt flag */
#define CSR0_IENA 0x0040 /* interrupt enable */
#define CSR0_RXON 0x0020 /* receiver on */
#define CSR0_TXON 0x0010 /* transmitter on */
#define CSR0_TDMD 0x0008 /* transmit demand */
#define CSR0_STOP 0x0004 /* stop the ilacc */
#define CSR0_STRT 0x0002 /* start the ilacc */
#define CSR0_INIT 0x0001 /* initialize the ilacc */
#define CSR3_BABLM 0x4000 /* BABL Mask */
#define CSR3_MISSM 0x1000 /* Missed packet Mask */
#define CSR3_MERRM 0x0800 /* Memory error Mask */
#define CSR3_RINTM 0x0400 /* Receive Interrupt Mask */
#define CSR3_TINTM 0x0200 /* Transmit Interrupt Mask */
#define CSR3_IDONM 0x0100 /* Initialization Done Mask */
#define CSR3_DXSUFLO 0x0040 /* Disable tx stop on underrun */
#define CSR3_LAPPEN 0x0020 /* lookahead packet proc enable */
#define CSR3_DXMT2PD 0x0010 /* disable 2 part deferral */
#define CSR3_EMBA 0x0008 /* enable modified backoff */
#define CSR3_BSWP 0x0004 /* byte swap */
#define CSR4_DMAPLUS 0x4000 /* DMA burst transfer until FIFO empty */
#define CSR4_BACON_68K 0x0040 /* 32 bit 680x0 */
#define CSR4_TXSTRT 0x0008 /* Transmit STaRT status */
#define CSR4_TXSTRTM 0x0004 /* Transmit STaRT interrupt Mask */
#define CSR4_ENTST 0x8000 /* enable test mode */
#define CSR4_TIMER 0x2000 /* enable bus timer csr82 */
#define CSR4_DPOLL 0x1000 /* disable tx polling */
#define CSR4_APADXMIT 0x0800 /* auto pad tx to 64 */
#define CSR4_ASTRPRCV 0x0400 /* auto strip rx pad and fcs */
#define CSR4_MFCO 0x0200 /* missed frame counter oflo interrupt */
#define CSR4_MFCOM 0x0100 /* mask to disable */
#define CSR4_RCVCCO 0x0020 /* rx collision counter oflo interrupt */
#define CSR4_RCVCCOM 0x0010 /* mask to disable */
#define CSR4_JAB 0x0002 /* jabber error 10baseT interrupt */
#define CSR4_JABM 0x0001 /* mask to disable */
#define CSR5_SPND 0x0001 /* Suspend */
#define CSR15_PROM 0x8000 /* Promiscuous */
#define CSR15_DRCVBC 0x4000 /* Disable receiver broadcast */
#define CSR15_DRCVPA 0x2000 /* Disable receiver phys. addr. */
#define CSR15_DLNKTST 0x1000 /* Disable link status */
#define CSR15_DAPC 0x0800 /* Disable auto polarity det. */
#define CSR15_MENDECL 0x0400 /* MENDEC loopback mode */
#define CSR15_LRT 0x0200 /* Low receiver threshold */
#define CSR15_TSEL 0x0200 /* Transmit mode select */
#define CSR15_INTL 0x0040 /* Internal loopback */
#define CSR15_DRTY 0x0020 /* Disable retry */
#define CSR15_FCOLL 0x0010 /* Force collision */
#define CSR15_DXMTFCS 0x0008 /* Disable transmit CRC */
#define CSR15_LOOP 0x0004 /* Loopback enable */
#define CSR15_DTX 0x0002 /* Disable transmitter */
#define CSR15_DRX 0x0001 /* Disable receiver */
#define CSR58_PCISTYLE 0x0002 /* software style */
#define CSR80_RCVFW16 (0<<12) /* fifo level to trigger rx dma */
#define CSR80_RCVFW32 (1<<12)
#define CSR80_RCVFW64 (2<<12)
#define CSR80_XMTSP4 (0<<10) /* fifo level to trigger tx */
#define CSR80_XMTSP16 (1<<10)
#define CSR80_XMTSP64 (2<<10)
#define CSR80_XMTSP112 (3<<10)
#define CSR80_XMTFW16 (0<<8) /* fifo level to stop dma */
#define CSR80_XMTFW32 (1<<8)
#define CSR80_XMTFW64 (2<<8)
/* must also clear csr4 CSR4_DMAPLUS: */
#define CSR80_DMATC(x) ((x)&0xff) /* max transfers per burst. deflt 16 */
/*
* must also set csr4 CSR4_TIMER:
*/
#define CSR82_DMABAT(x) ((x)&0xffff) /* max burst time nanosecs*100 */
#define BCR18_MUSTSET 0x0100 /* this bit must be written as 1 !! */
#define BCR18_BREADE 0x0040 /* linear burst enable. yes ! on pci */
#define BCR18_BWRITE 0x0020 /* in write direction */
#define BCR18_LINBC4 0x0001 /* linear burst count 4 8 or 16 */
#define BCR18_LINBC8 0x0002 /* NOTE LINBC must be <= fifo trigger*/
#define BCR18_LINBC16 0x0004
#define BCR19_PVALID 0x8000 /* aprom (eeprom) read checksum ok */
/*
* initial setting of csr0
*/
#define CSR0_IVALUE (CSR0_IDON | CSR0_IENA | CSR0_STRT | CSR0_INIT)
/*
* our setting of csr3
*/
#define CSR3_VALUE (CSR3_ACON | CSR3_BSWP)
/*
* Initialization Block.
* Chip initialization includes the reading of the init block to obtain
* the operating parameters.
*
* This essentially consists of 7, 32 bit LE words. In the following the
* fields are ordered so that they map correctly in BE mode, however each
* 16 and 32 byte field will require swapping.
*/
typedef volatile struct initblk {
/* mode can be set in csr15 */
uint16_t ib_mode; /* Chip's operating parameters */
uint8_t ib_rlen; /* rx ring length (power of 2) */
uint8_t ib_tlen; /* tx ring length (power of 2) */
/*
* The bytes must be swapped within the word, so that, for example,
* the address 8:0:20:1:25:5a is written in the order
* 0 8 1 20 5a 25
* For PCI970 that is long word swapped: so no swapping needed, since
* the bus will swap.
*/
uint8_t ib_padr[8]; /* physical address */
uint16_t ib_ladrf[4]; /* logical address filter */
uint32_t ib_rdra; /* rcv ring desc addr */
uint32_t ib_tdra; /* xmit ring desc addr */
} initblk_t;
/*
* bits in mode register: allows alteration of the chips operating parameters
*/
#define IBM_PROM 0x8000 /* promiscuous mode */
/*
* mode is also in cr15
*/
#define MODE_DRCVBC 0x4000 /* disable receive broadcast */
#define MODE_DRCVPA 0x2000 /* disable receive physical address */
#define MODE_DLNKTST 0x1000 /* disable link status monitoring 10T */
#define MODE_DAPC 0x0800 /* disable auto polarity 10T */
#define MODE_MENDECL 0x0400 /* mendec loopback */
#define MODE_LRT 0x0200 /* low receive threshold/tx mode sel tmau */
#define MODE_PORTSEL10T 0x0080 /* port select 10T ?? */
#define MODE_PORTSELAUI 0x0000 /* port select aui ?? */
#define IBM_INTL 0x0040 /* internal loopback */
#define IBM_DRTY 0x0020 /* disable retry */
#define IBM_COLL 0x0010 /* force collision */
#define IBM_DTCR 0x0008 /* disable transmit crc */
#define IBM_LOOP 0x0004 /* loopback */
#define IBM_DTX 0x0002 /* disable transmitter */
#define IBM_DRX 0x0001 /* disable receiver */
/*
* Buffer Management is accomplished through message descriptors organized
* in ring structures in main memory. There are two rings allocated for the
* device: a receive ring and a transmit ring. The following defines the
* structure of the descriptor rings.
*/
/*
* Receive List type definition
*
* This essentially consists of 4, 32 bit LE words. In the following the
* fields are ordered so that they map correctly in BE mode, however each
* 16 and 32 byte field will require swapping.
*/
typedef volatile struct rmde {
uint32_t rmde_addr; /* buf addr */
uint16_t rmde_bcnt;
uint16_t rmde_flags;
uint16_t rmde_mcnt;
uint16_t rmde_misc;
uint32_t align;
} rmde_t;
/*
* bits in the flags field
*/
#define RFLG_OWN 0x8000 /* ownership bit, 1==LANCE */
#define RFLG_ERR 0x4000 /* error summary */
#define RFLG_FRAM 0x2000 /* framing error */
#define RFLG_OFLO 0x1000 /* overflow error */
#define RFLG_CRC 0x0800 /* crc error */
#define RFLG_BUFF 0x0400 /* buffer error */
#define RFLG_STP 0x0200 /* start of packet */
#define RFLG_ENP 0x0100 /* end of packet */
/*
* bits in the buffer byte count field
*/
#define RBCNT_ONES 0xf000 /* must be ones */
#define RBCNT_BCNT 0x0fff /* buf byte count, in 2's compl */
/*
* bits in the message byte count field
*/
#define RMCNT_RES 0xf000 /* reserved, read as zeros */
#define RMCNT_BCNT 0x0fff /* message byte count */
/*
* Transmit List type definition
*
* This essentially consists of 4, 32 bit LE words. In the following the
* fields are ordered so that they map correctly in BE mode, however each
* 16 and 32 byte field will require swapping.
*/
typedef volatile struct tmde {
uint32_t tmde_addr; /* buf addr */
uint16_t tmde_bcnt;
uint16_t tmde_status; /* misc error and status bits */
uint32_t tmde_error;
uint32_t align;
} tmde_t;
/*
* bits in the status field
*/
#define TST_OWN 0x8000 /* ownership bit, 1==LANCE */
#define TST_ERR 0x4000 /* error summary */
#define TST_RES 0x2000 /* reserved bit */
#define TST_MORE 0x1000 /* more than one retry was needed */
#define TST_ONE 0x0800 /* one retry was needed */
#define TST_DEF 0x0400 /* defer while trying to transmit */
#define TST_STP 0x0200 /* start of packet */
#define TST_ENP 0x0100 /* end of packet */
/*
* setting of status field when packet is to be transmitted
*/
#define TST_XMIT (TST_STP | TST_ENP | TST_OWN)
/*
* bits in the buffer byte count field
*/
#define TBCNT_ONES 0xf000 /* must be ones */
#define TBCNT_BCNT 0x0fff /* buf byte count, in 2's compl */
/*
* bits in the error field
*/
#define TERR_BUFF 0x8000 /* buffer error */
#define TERR_UFLO 0x4000 /* underflow error */
#define TERR_EXDEF 0x2000 /* excessive deferral */
#define TERR_LCOL 0x1000 /* late collision */
#define TERR_LCAR 0x0800 /* loss of carrier */
#define TERR_RTRY 0x0400 /* retry error */
#define TERR_TDR 0x03ff /* time domain reflectometry */
/*
* Defines pertaining to statistics gathering (diagnostic only)
*/
/*
* receive errors
*/
#define ERR_FRAM 0 /* framing error */
#define ERR_OFLO 1 /* overflow error */
#define ERR_CRC 2 /* crc error */
#define ERR_RBUFF 3 /* receive buffer error */
/*
* transmit errors
*/
#define ERR_MORE 4 /* more than one retry */
#define ERR_ONE 5 /* one retry */
#define ERR_DEF 6 /* defer'd packet */
#define ERR_TBUFF 7 /* transmit buffer error */
#define ERR_UFLO 8 /* underflow error */
#define ERR_LCOL 9 /* late collision */
#define ERR_LCAR 10 /* loss of carrier */
#define ERR_RTRY 11 /* retry error, >16 retries */
/*
* errors reported in csr0
*/
#define ERR_BABL 12 /* transmitter timeout error */
#define ERR_MISS 13 /* missed packet */
#define ERR_MEM 14 /* memory error */
#define ERR_CERR 15 /* collision errors */
#define XMIT_INT 16 /* transmit interrupts */
#define RCV_INT 17 /* receive interrupts */
#define NHARD_ERRORS 18 /* error types used in diagnostic */
/*
* other statistics
*/
#define ERR_TTOUT 18 /* transmit timeouts */
#define ERR_ITOUT 19 /* init timeouts */
#define ERR_INITS 20 /* reinitializations */
#define ERR_RSILO 21 /* silo ptrs misaligned on recv */
#define ERR_TSILO 22 /* silo ptrs misaligned on xmit */
#define ERR_SINTR 23 /* spurious interrupts */
#define NUM_ERRORS 24 /* number of errors types */
/*
* Bit definitions for BCR19
*/
#define prom_EDI (uint16_t)0x0001
#define prom_EDO (uint16_t)0x0001
#define prom_ESK (uint16_t)0x0002
#define prom_ECS (uint16_t)0x0004
#define prom_EEN (uint16_t)0x0010
#define prom_EEDET (uint16_t)0x2000
#define prom_PVALID (uint16_t)0x8000
#define prom_PREAD (uint16_t)0x4000
#endif

38
c/src/lib/libbsp/powerpc/ppcn_60x/nvram/ds1385.h
View File

@@ -1,38 +0,0 @@
/*
* COPYRIGHT (c) 1998 by Radstone Technology
*
*
* THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
* KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
* AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
*
* You are hereby granted permission to use, copy, modify, and distribute
* this file, provided that this notice, plus the above copyright notice
* and disclaimer, appears in all copies. Radstone Technology will provide
* no support for this code.
*
*/
/*
* Definitions for the ds1385 NvRAM
*/
#ifndef _DS1385_H
#define _DS1385_H
#include "prepnvr.h"
#define DS1385_NVSIZE 4096 /* size of NVRAM */
#define DS1385_GESIZE (DS1385_NVSIZE-CONFSIZE-OSAREASIZE-sizeof(HEADER))
#define DS1385_PORT_BASE 0x74
/* Here is the whole map of the DS1385 NVRAM */
typedef struct _DS1385_NVRAM_MAP {
HEADER Header;
unsigned char GEArea[DS1385_GESIZE];
unsigned char OSArea[OSAREASIZE];
unsigned char ConfigArea[CONFSIZE];
} DS1385_NVRAM_MAP, *PDS1385_NVRAM_MAP;
#endif /* _DS1385_H */

87
c/src/lib/libbsp/powerpc/ppcn_60x/nvram/mk48t18.h
View File

@@ -1,87 +0,0 @@
/*
* COPYRIGHT (c) 1998 by Radstone Technology
*
*
* THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
* KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
* AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
*
* You are hereby granted permission to use, copy, modify, and distribute
* this file, provided that this notice, plus the above copyright notice
* and disclaimer, appears in all copies. Radstone Technology will provide
* no support for this code.
*
*/
/*
* Definitions for the mk48t18 RTC/NvRAM
*/
#ifndef _MK48T18_H
#define _MK48T18_H
#include "prepnvr.h"
/*
* This structure maps to the top of the NvRAM. It is based on the standard
* CMOS.h file for the ds1385. Feature and system dependant areas are preserved
* for potential compatibility issues.
*
* The CRC's are computed with x**16+x**12+x**5 + 1 polynomial
* The clock is kept in 24 hour BCD mode and should be set to UT(GMT)
*/
typedef struct _MK48T18_CMOS_MAP {
uint8_t SystemDependentArea2[8];
uint8_t FeatureByte0[1];
uint8_t FeatureByte1[1];
uint8_t Century; /* century byte in BCD */
uint8_t FeatureByte3[1];
uint8_t FeatureByte4[1];
uint8_t FeatureByte5[1];
uint8_t FeatureByte6[1];
uint8_t FeatureByte7[1];
uint8_t BootPW[14];
uint16_t BootCrc; /* CRC on BootPW */
uint8_t ConfigPW[14];
uint16_t ConfigCrc; /* CRC on ConfigPW */
uint8_t SystemDependentArea1[8];
/*
* The following are the RTC registers
*/
volatile uint8_t Control;
volatile uint8_t Second:7; /* 0-59 */
volatile uint8_t Stop:1;
volatile uint8_t Minute; /* 0-59 */
volatile uint8_t Hour; /* 0-23 */
volatile uint8_t Day:3; /* 1-7 */
volatile uint8_t Resvd1:3; /* 0 */
volatile uint8_t FT:1; /* Frequency test bit - must be 0 */
volatile uint8_t Resvd2:1; /* 0 */
volatile uint8_t Date; /* 1-31 */
volatile uint8_t Month; /* 1-12 */
volatile uint8_t Year; /* 0-99 */
} MK48T18_CMOS_MAP, *PMK48T18_CMOS_MAP;
/*
* Control register definitions
*/
#define MK48T18_CTRL_WRITE 0x80
#define MK48T18_CTRL_READ 0x40
#define MK48T18_CTRL_SIGN 0x20
#define MK48T18_NVSIZE 8192-sizeof(MK48T18_CMOS_MAP)
#define MK48T18_GESIZE (MK48T18_NVSIZE-CONFSIZE-OSAREASIZE-sizeof(HEADER))
#define MK48T18_BASE (PMK48T18_NVRAM_MAP)((uint8_t*)PCI_MEM_BASE+0x00800000)
/* Here is the whole map of the MK48T18 NVRAM */
typedef struct _MK48T18_NVRAM_MAP {
HEADER Header;
uint8_t GEArea[MK48T18_GESIZE];
uint8_t OSArea[OSAREASIZE];
uint8_t ConfigArea[CONFSIZE];
MK48T18_CMOS_MAP CMOS;
} MK48T18_NVRAM_MAP, *PMK48T18_NVRAM_MAP;
#endif /* _MK48T18_H */

513
c/src/lib/libbsp/powerpc/ppcn_60x/nvram/nvram.c
View File

@@ -1,513 +0,0 @@
/*
* This file contains the NvRAM driver for the PPCn_60x
*
* COPYRIGHT (c) 1998 by Radstone Technology
*
*
* THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
* KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
* AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
*
* You are hereby granted permission to use, copy, modify, and distribute
* this file, provided that this notice, plus the above copyright notice
* and disclaimer, appears in all copies. Radstone Technology will provide
* no support for this code.
*
*/
#include <bsp.h>
#include "ds1385.h"
#include "mk48t18.h"
#include "stk11c68.h"
/*
* Private types
*/
typedef
void
(*PNVRAMWRITE)
(
uint32_t ulOffset,
uint8_t ucByte
);
typedef
uint8_t
(*PNVRAMREAD)
(
uint32_t ulOffset
);
typedef
void
(*PNVRAMCOMMIT)
(
);
typedef struct _NVRAM_ENTRY_TABLE
{
PNVRAMWRITE nvramWrite;
PNVRAMREAD nvramRead;
PNVRAMCOMMIT nvramCommit;
uint32_t nvramSize;
} NVRAM_ENTRY_TABLE, *PNVRAM_ENTRY_TABLE;
/*
* Private routines
*/
/*
* This routine provides a stub for NvRAM devices which
* do not require a commit operation
*/
static void nvramCommitStub();
/*
* DS1385 specific routines
*/
static void nvramDsWrite(uint32_t ulOffset, uint8_t ucByte);
static uint8_t nvramDsRead(uint32_t ulOffset);
/*
* MK48T18 specific routines
*/
static void nvramMkWrite(uint32_t ulOffset, uint8_t ucByte);
static uint8_t nvramMkRead(uint32_t ulOffset);
/*
* STK11C68 specific routines
*/
static void nvramStk11C68Commit();
/*
* STK11C88 specific routines
*/
static void nvramStk11C88Commit();
/*
* NvRAM hook tables
*/
NVRAM_ENTRY_TABLE nvramDsTable =
{
nvramDsWrite,
nvramDsRead,
nvramCommitStub,
DS1385_NVSIZE
};
NVRAM_ENTRY_TABLE nvramMkTable =
{
nvramMkWrite,
nvramMkRead,
nvramCommitStub,
MK48T18_NVSIZE
};
/*
* As the STK devicxe is at the same address as the MK device,
* the MK read/write routines may be used
*/
NVRAM_ENTRY_TABLE nvramStkTable =
{
nvramMkWrite,
nvramMkRead,
nvramStk11C68Commit,
STK11C68_NVSIZE
};
NVRAM_ENTRY_TABLE nvramStk88Table =
{
nvramMkWrite,
nvramMkRead,
nvramStk11C88Commit,
STK11C88_NVSIZE
};
/*
* Private variables
*/
static PNVRAM_ENTRY_TABLE pNvRAMFunc;
static boolean bNvRAMChanged=FALSE;
static uint32_t ulPRePOSAreaLength;
static uint32_t ulPRePOSAreaOffset;
/*
* Mutual-exclusion semaphore
*/
static rtems_id semNvRAM;
/*
* These routines support the ds1385
*/
static uint8_t nvramDsRead(uint32_t ulOffset)
{
uint8_t ucTemp;
ucTemp = ulOffset & 0xff;
outport_byte(DS1385_PORT_BASE, ucTemp);
ucTemp = (ulOffset >> 8) & 0xf;
outport_byte((DS1385_PORT_BASE + 1) , ucTemp);
inport_byte(DS1385_PORT_BASE+3, ucTemp);
return(ucTemp);
}
static void nvramDsWrite(uint32_t ulOffset, uint8_t ucData)
{
uint8_t ucTemp;
ucTemp = (uint8_t)(ulOffset & 0xff);
outport_byte(DS1385_PORT_BASE, (uint8_t) ucTemp);
ucTemp = (uint8_t)((ulOffset >> 8) & 0xf);
outport_byte((DS1385_PORT_BASE + 1) , (uint8_t)ucTemp);
outport_byte((DS1385_PORT_BASE+3), ucData);
}
/*
* These routines support the MK48T18 and STK11C68
*/
static uint8_t nvramMkRead(uint32_t ulOffset)
{
uint8_t *pNvRAM = (uint8_t*)MK48T18_BASE;
return(pNvRAM[ulOffset]);
}
static void nvramMkWrite(uint32_t ulOffset, uint8_t ucData)
{
uint8_t *pNvRAM = (uint8_t*)MK48T18_BASE;
pNvRAM[ulOffset]=ucData;
}
/*
* This routine provides a stub for NvRAM devices which
* do not require a commit operation
*/
static void nvramCommitStub()
{
}
/*
* This routine triggers a transfer from the NvRAM to the
* EE array in the STK11C68 device
*/
static void nvramStk11C68Commit()
{
#if 0
rtems_interval ticks_per_second;
rtems_status_code status;
#endif
rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
/*
* Issue Store command
*/
EIEIO;
(void)pNvRAMFunc->nvramRead(0x0000);
EIEIO;
(void)pNvRAMFunc->nvramRead(0x1555);
EIEIO;
(void)pNvRAMFunc->nvramRead(0x0aaa);
EIEIO;
(void)pNvRAMFunc->nvramRead(0x1fff);
EIEIO;
(void)pNvRAMFunc->nvramRead(0x10f0);
EIEIO;
(void)pNvRAMFunc->nvramRead(0x0f0f);
EIEIO;
/*
* Delay for 10mS to allow store to
* complete
*/
#if 0
status = rtems_clock_get(
RTEMS_CLOCK_GET_TICKS_PER_SECOND,
&ticks_per_second
);
status = rtems_task_wake_after(ticks_per_second/100);
#endif
bNvRAMChanged=FALSE;
rtems_semaphore_release(semNvRAM);
}
/*
* This routine triggers a transfer from the NvRAM to the
* EE array in the STK11C88 device
*/
static void nvramStk11C88Commit()
{
#if 0
rtems_interval ticks_per_second;
rtems_status_code status;
#endif
rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
/*
* Issue Store command
*/
EIEIO;
(void)pNvRAMFunc->nvramRead(0x0e38);
EIEIO;
(void)pNvRAMFunc->nvramRead(0x31c7);
EIEIO;
(void)pNvRAMFunc->nvramRead(0x03e0);
EIEIO;
(void)pNvRAMFunc->nvramRead(0x3c1f);
EIEIO;
(void)pNvRAMFunc->nvramRead(0x303f);
EIEIO;
(void)pNvRAMFunc->nvramRead(0x0fc0);
EIEIO;
/*
* Delay for 10mS to allow store to
* complete
*/
#if 0
status = rtems_clock_get(
RTEMS_CLOCK_GET_TICKS_PER_SECOND,
&ticks_per_second
);
status = rtems_task_wake_after(ticks_per_second/100);
#endif
bNvRAMChanged=FALSE;
rtems_semaphore_release(semNvRAM);
}
/*
* These are the publically accessable routines
*/
/*
* This routine returns the size of the NvRAM
*/
uint32_t SizeNvRAM()
{
return(ulPRePOSAreaLength);
}
/*
* This routine commits changes to the NvRAM
*/
void CommitNvRAM()
{
if(bNvRAMChanged)
{
(pNvRAMFunc->nvramCommit)();
}
}
/*
* This routine reads a byte from the NvRAM
*/
rtems_status_code ReadNvRAM8(uint32_t ulOffset, uint8_t *pucData)
{
if(ulOffset>ulPRePOSAreaLength)
{
return RTEMS_INVALID_ADDRESS;
}
rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
*pucData=pNvRAMFunc->nvramRead(ulPRePOSAreaOffset+ulOffset);
rtems_semaphore_release(semNvRAM);
return(RTEMS_SUCCESSFUL);
}
/*
* This routine writes a byte to the NvRAM
*/
rtems_status_code WriteNvRAM8(uint32_t ulOffset, uint8_t ucValue)
{
if(ulOffset>ulPRePOSAreaLength)
{
return RTEMS_INVALID_ADDRESS;
}
rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
pNvRAMFunc->nvramWrite(ulPRePOSAreaOffset+ulOffset, ucValue);
bNvRAMChanged=TRUE;
rtems_semaphore_release(semNvRAM);
return(RTEMS_SUCCESSFUL);
}
/*
* This routine reads a block of bytes from the NvRAM
*/
rtems_status_code ReadNvRAMBlock(
uint32_t ulOffset, uint8_t *pucData, uint32_t length)
{
uint32_t i;
if((ulOffset + length) > ulPRePOSAreaLength)
{
return RTEMS_INVALID_ADDRESS;
}
rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
for ( i=0 ; i<length ; i++ )
pucData[i] =
pNvRAMFunc->nvramRead(ulPRePOSAreaOffset+ulOffset+i);
rtems_semaphore_release(semNvRAM);
return(RTEMS_SUCCESSFUL);
}
/*
* This routine writes a block of bytes to the NvRAM
*/
rtems_status_code WriteNvRAMBlock(
uint32_t ulOffset, uint8_t *ucValue, uint32_t length)
{
uint32_t i;
if((ulOffset + length) > ulPRePOSAreaLength)
{
return RTEMS_INVALID_ADDRESS;
}
rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
for ( i=0 ; i<length ; i++ )
pNvRAMFunc->nvramWrite(
ulPRePOSAreaOffset+ulOffset+i, ucValue[i]);
bNvRAMChanged=TRUE;
rtems_semaphore_release(semNvRAM);
return(RTEMS_SUCCESSFUL);
}
/*
* The NVRAM holds data in Big-Endian format
*/
rtems_status_code ReadNvRAM16 (uint32_t ulOffset, uint16_t *pusData)
{
uint32_t ulTrueOffset=ulPRePOSAreaOffset+ulOffset;
if(ulOffset>ulPRePOSAreaLength)
{
return RTEMS_INVALID_ADDRESS;
}
rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
*pusData=(pNvRAMFunc->nvramRead(ulTrueOffset) << 8) +
(pNvRAMFunc->nvramRead(ulTrueOffset + 1));
rtems_semaphore_release(semNvRAM);
return(RTEMS_SUCCESSFUL);
}
rtems_status_code WriteNvRAM16 (uint32_t ulOffset, uint16_t usValue)
{
uint32_t ulTrueOffset=ulPRePOSAreaOffset+ulOffset;
if(ulOffset>ulPRePOSAreaLength)
{
return RTEMS_INVALID_ADDRESS;
}
rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
pNvRAMFunc->nvramWrite(ulTrueOffset, (uint8_t) (usValue >> 8));
pNvRAMFunc->nvramWrite(ulTrueOffset + 1, (uint8_t) usValue);
bNvRAMChanged=TRUE;
rtems_semaphore_release(semNvRAM);
return(RTEMS_SUCCESSFUL);
}
rtems_status_code ReadNvRAM32 (uint32_t ulOffset, uint32_t *pulData)
{
uint32_t ulTrueOffset=ulPRePOSAreaOffset+ulOffset;
if(ulOffset>ulPRePOSAreaLength)
{
return RTEMS_INVALID_ADDRESS;
}
rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
*pulData=(pNvRAMFunc->nvramRead(ulTrueOffset) << 24) +
(pNvRAMFunc->nvramRead(ulTrueOffset + 1) << 16) +
(pNvRAMFunc->nvramRead(ulTrueOffset + 2) << 8) +
(pNvRAMFunc->nvramRead(ulTrueOffset + 3));
rtems_semaphore_release(semNvRAM);
return(RTEMS_SUCCESSFUL);
}
rtems_status_code WriteNvRAM32 (uint32_t ulOffset, uint32_t ulValue)
{
uint32_t ulTrueOffset=ulPRePOSAreaOffset+ulOffset;
if(ulOffset>ulPRePOSAreaLength)
{
return RTEMS_INVALID_ADDRESS;
}
rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
pNvRAMFunc->nvramWrite(ulTrueOffset, (uint8_t) (ulValue >> 24));
pNvRAMFunc->nvramWrite(ulTrueOffset + 1, (uint8_t) (ulValue >> 16));
pNvRAMFunc->nvramWrite(ulTrueOffset + 2, (uint8_t) (ulValue >> 8));
pNvRAMFunc->nvramWrite(ulTrueOffset + 3, (uint8_t) ulValue);
bNvRAMChanged=TRUE;
rtems_semaphore_release(semNvRAM);
return(RTEMS_SUCCESSFUL);
}
void
InitializeNvRAM(void)
{
PHEADER pNvHeader = (PHEADER)0;
rtems_status_code sc;
uint32_t ulLength, ulOffset;
if(ucSystemType==SYS_TYPE_PPC1)
{
if(ucBoardRevMaj<5)
{
pNvRAMFunc=&nvramDsTable;
}
else
{
pNvRAMFunc=&nvramMkTable;
}
}
else if(ucSystemType==SYS_TYPE_PPC1a)
{
pNvRAMFunc=&nvramMkTable;
}
else if(ucSystemType==SYS_TYPE_PPC4)
{
pNvRAMFunc=&nvramStk88Table;
}
else
{
pNvRAMFunc=&nvramStkTable;
}
/*
* Set up mutex semaphore
*/
sc = rtems_semaphore_create (
rtems_build_name ('N', 'V', 'R', 's'),
1,
RTEMS_BINARY_SEMAPHORE |
RTEMS_INHERIT_PRIORITY |
RTEMS_PRIORITY,
RTEMS_NO_PRIORITY,
&semNvRAM);
if (sc != RTEMS_SUCCESSFUL)
{
rtems_fatal_error_occurred (sc);
}
/*
* Initially access the whole of NvRAM until we determine where the
* OS Area is located.
*/
ulPRePOSAreaLength=0xffffffff;
ulPRePOSAreaOffset=0;
/*
* Access the header at the start of NvRAM
*/
ReadNvRAM32((uint32_t)(&pNvHeader->OSAreaLength), &ulLength);
ReadNvRAM32((uint32_t)(&pNvHeader->OSAreaAddress), &ulOffset);
/*
* Now set limits for future accesses
*/
ulPRePOSAreaLength=ulLength;
ulPRePOSAreaOffset=ulOffset;
}

127
c/src/lib/libbsp/powerpc/ppcn_60x/nvram/prepnvr.h
View File

@@ -1,127 +0,0 @@
/* Structure map for NVRAM on PowerPC Reference Platform */
/* Revision 1 changes (8/25/94):
- Power Management (RESTART_BLOCK struct)
- Normal added to PM_MODE
- OSIRQMask (HEADER struct) */
/* All fields are either character/byte strings which are valid either
endian or they are big-endian numbers.
There are a number of Date and Time fields which are in RTC format,
big-endian. These are stored in UT (GMT).
For enum's: if given in hex then they are bit significant, i.e. only
one bit is on for each enum.
*/
#ifndef _NVRAM_
#define _NVRAM_
#define VERSION 1
#define REVISION 0
#define OSAREASIZE 1024 /* size of OSArea space */
#define CONFSIZE 512 /* guess at size of Configuration space */
typedef struct _SECURITY {
unsigned long BootErrCnt; /* Count of boot password errors */
unsigned long ConfigErrCnt; /* Count of config password errors */
unsigned long BootErrorDT[2]; /* Date&Time from RTC of last error in pw */
unsigned long ConfigErrorDT[2]; /* Date&Time from RTC of last error in pw */
unsigned long BootCorrectDT[2]; /* Date&Time from RTC of last correct pw */
unsigned long ConfigCorrectDT[2]; /* Date&Time from RTC of last correct pw */
unsigned long BootSetDT[2]; /* Date&Time from RTC of last set of pw */
unsigned long ConfigSetDT[2]; /* Date&Time from RTC of last set of pw */
unsigned char Serial[16]; /* Box serial number */
} SECURITY;
typedef enum _OS_ID {
Unknown = 0,
Firmware = 1,
AIX = 2,
NT = 3,
WPOS2 = 4,
WPAIX = 5,
Taligent = 6,
Solaris = 7,
Netware = 8,
USL = 9,
Low_End_Client = 10,
SCO = 11
} OS_ID;
typedef struct _ERROR_LOG {
unsigned char ErrorLogEntry[40]; /* To be architected */
} ERROR_LOG;
/*---Revision 1: Change the following struct:---*/
typedef struct _RESUME_BLOCK {
/* Hibernation Resume Device will be an
environment variable */
unsigned long CheckSum; /* Checksum of RESUME_BLOCK */
volatile unsigned long BootStatus;
void * ResumeAddr; /* For Suspend Resume */
void * SaveAreaAddr; /* For Suspend Resume */
unsigned long SaveAreaLength; /* For Suspend Resume */
unsigned long HibResumeImageRBA; /* RBA (512B blocks) of compressed OS
memory image to be loaded by FW
on Resume from hibernation */
unsigned long HibResumeImageRBACount; /* Size of image in 512B blocks*/
unsigned long Reserved;
} RESUME_BLOCK;
typedef enum _OSAREA_USAGE {
Empty = 0,
Used = 1
} OSAREA_USAGE;
typedef enum _PM_MODE {
Suspend = 0x80, /* Part of state is in memory */
Hibernate = 0x40, /* Nothing in memory - state saved elsewhere */
/* Revision 1: Normal added (actually was already here) */
Normal = 0x00 /* No power management in effect */
} PMMode;
typedef struct _HEADER {
unsigned short Size; /* NVRAM size in K(1024) */
unsigned char Version; /* Structure map different */
unsigned char Revision; /* Structure map the same -
may be new values in old fields
in other words old code still works */
unsigned short Crc1; /* check sum from beginning of nvram to OSArea */
unsigned short Crc2; /* check sum of config */
unsigned char LastOS; /* OS_ID */
unsigned char Endian; /* B if big endian, L if little endian */
unsigned char OSAreaUsage; /* OSAREA_USAGE */
unsigned char PMMode; /* Shutdown mode */
RESUME_BLOCK ResumeBlock;
SECURITY Security;
ERROR_LOG ErrorLog[2];
/* Global Environment information */
void * GEAddress;
unsigned long GELength;
/* Date&Time from RTC of last change to Global Environment */
unsigned long GELastWriteDT[2];
/* Configuration information */
void * ConfigAddress;
unsigned long ConfigLength;
/* Date&Time from RTC of last change to Configuration */
unsigned long ConfigLastWriteDT[2];
unsigned long ConfigCount; /* Count of entries in Configuration */
/* OS dependent temp area */
void * OSAreaAddress;
unsigned long OSAreaLength;
/* Date&Time from RTC of last change to OSAreaArea */
unsigned long OSAreaLastWriteDT[2];
/* Revision 1: add this mask - function tbd */
/*unsigned short OSIRQMask; OS to FW IRQ Mask - "I've used this one" */
} HEADER, *PHEADER;
#endif /* ndef _NVRAM_ */

46
c/src/lib/libbsp/powerpc/ppcn_60x/nvram/stk11c68.h
View File

@@ -1,46 +0,0 @@
/*
* COPYRIGHT (c) 1998 by Radstone Technology
*
*
* THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
* KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
* AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
*
* You are hereby granted permission to use, copy, modify, and distribute
* this file, provided that this notice, plus the above copyright notice
* and disclaimer, appears in all copies. Radstone Technology will provide
* no support for this code.
*
*/
/*
* Definitions for the stk11C68 NvRAM
*/
#ifndef _STK11C68_H
#define _STK11C68_H
#include "prepnvr.h"
/*
* STK11C68 definitions
*/
#define STK11C68_NVSIZE 8192
#define STK11C68_GESIZE (STK11C68_NVSIZE-CONFSIZE-OSAREASIZE-sizeof(HEADER))
#define STK11C68_BASE (PSTK11C68_NVRAM_MAP)((uint8_t*)PCI_MEM_BASE+0x00800000)
/*
* STK11C88 definitions
*/
#define STK11C88_NVSIZE 0x8000-sizeof(MK48T18_CMOS_MAP)
/* Here is the whole map of the STK11C68 NVRAM */
typedef struct _STK11C68_NVRAM_MAP {
HEADER Header;
uint8_t GEArea[STK11C68_GESIZE];
uint8_t OSArea[OSAREASIZE];
uint8_t ConfigArea[CONFSIZE];
} STK11C68_NVRAM_MAP, *PSTK11C68_NVRAM_MAP;
#endif /* _STK11C68_H */

342
c/src/lib/libbsp/powerpc/ppcn_60x/pci/pci.c
View File

@@ -1,342 +0,0 @@
/*
* COPYRIGHT (c) 1998 by Radstone Technology
*
*
* THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
* KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
* AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
*
* You are hereby granted permission to use, copy, modify, and distribute
* this file, provided that this notice, plus the above copyright notice
* and disclaimer, appears in all copies. Radstone Technology will provide
* no support for this code.
*
*/
#include <bsp.h>
#include <pci.h>
/* SCE 97/4/9
*
* Use PCI configuration space access mechanism 1
*
* This is the preferred access mechanism and must be used when accessing
* bridged PCI busses.
*
* The address to be written to the PCI_CONFIG_ADDRESS port is constructed
* thus (the representation below is little endian):
*
* 31 30 24 23 16 15 11 10 8 7 2 1 0
* ----------------------------------------------------------------------
* | 1 | Resvd | Bus Number | Dev Number | Fn Number | Reg Number | 0 | 0 |
* ----------------------------------------------------------------------
*
* On bus 0, the first 'real' device is at Device number 11, the Eagle being
* device 0. On all other busses, device numbering starts at 0.
*/
/*
* Normal PCI device numbering on busses other than 0 is such that
* that the first device (0) is attached to AD16, second (1) to AD17 etc.
*/
#define CONFIG_ADDRESS(Bus, Device, Function, Offset) \
(0x80000000 | (Bus<<16) | \
((Device+(((Bus==0)&&(Device>0)) ? 10 : 0))<<11) | \
(Function<<8) | \
(Offset&~0x03))
#define BYTE_LANE_OFFSET(Offset) ((Offset)&0x3)
/*
* Private data
*/
static uint8_t ucMaxPCIBus;
/*
* Public routines
*/
rtems_status_code PCIConfigWrite8(
uint8_t ucBusNumber,
uint8_t ucSlotNumber,
uint8_t ucFunctionNumber,
uint8_t ucOffset,
uint8_t ucValue
)
{
ISR_Level Irql;
/*
* Ensure that accesses to the addr/data ports are indivisible
*/
_ISR_Disable(Irql);
/*
* Write to the configuration space address register
*/
outport_32(PCI_CONFIG_ADDR,
CONFIG_ADDRESS(ucBusNumber, ucSlotNumber,
ucFunctionNumber, ucOffset));
/*
* Write to the configuration space data register with the appropriate
* offset
*/
outport_byte(PCI_CONFIG_DATA+BYTE_LANE_OFFSET(ucOffset), ucValue);
_ISR_Enable(Irql);
return(RTEMS_SUCCESSFUL);
}
rtems_status_code PCIConfigWrite16(
uint8_t ucBusNumber,
uint8_t ucSlotNumber,
uint8_t ucFunctionNumber,
uint8_t ucOffset,
uint16_t usValue
)
{
ISR_Level Irql;
/*
* Ensure that accesses to the addr/data ports are indivisible
*/
_ISR_Disable(Irql);
/*
* Write to the configuration space address register
*/
outport_32(PCI_CONFIG_ADDR,
CONFIG_ADDRESS(ucBusNumber, ucSlotNumber,
ucFunctionNumber, ucOffset));
/*
* Write to the configuration space data register with the appropriate
* offset
*/
outport_16(PCI_CONFIG_DATA+BYTE_LANE_OFFSET(ucOffset), usValue);
_ISR_Enable(Irql);
return(RTEMS_SUCCESSFUL);
}
rtems_status_code PCIConfigWrite32(
uint8_t ucBusNumber,
uint8_t ucSlotNumber,
uint8_t ucFunctionNumber,
uint8_t ucOffset,
uint32_t ulValue
)
{
ISR_Level Irql;
/*
* Ensure that accesses to the addr/data ports are indivisible
*/
_ISR_Disable(Irql);
/*
* Write to the configuration space address register
*/
outport_32(PCI_CONFIG_ADDR,
CONFIG_ADDRESS(ucBusNumber, ucSlotNumber,
ucFunctionNumber, ucOffset));
/*
* Write to the configuration space data register with the appropriate
* offset
*/
outport_32(PCI_CONFIG_DATA, ulValue);
_ISR_Enable(Irql);
return(RTEMS_SUCCESSFUL);
}
rtems_status_code PCIConfigRead8(
uint8_t ucBusNumber,
uint8_t ucSlotNumber,
uint8_t ucFunctionNumber,
uint8_t ucOffset,
uint8_t *pucValue
)
{
ISR_Level Irql;
/*
* Ensure that accesses to the addr/data ports are indivisible
*/
_ISR_Disable(Irql);
/*
* Write to the configuration space address register
*/
outport_32(PCI_CONFIG_ADDR,
CONFIG_ADDRESS(ucBusNumber, ucSlotNumber,
ucFunctionNumber, ucOffset));
/*
* Read from the configuration space data register with the appropriate
* offset
*/
inport_byte(PCI_CONFIG_DATA+BYTE_LANE_OFFSET(ucOffset), *pucValue);
_ISR_Enable(Irql);
return(RTEMS_SUCCESSFUL);
}
rtems_status_code PCIConfigRead16(
uint8_t ucBusNumber,
uint8_t ucSlotNumber,
uint8_t ucFunctionNumber,
uint8_t ucOffset,
uint16_t *pusValue
)
{
ISR_Level Irql;
/*
* Ensure that accesses to the addr/data ports are indivisible
*/
_ISR_Disable(Irql);
/*
* Write to the configuration space address register
*/
outport_32(PCI_CONFIG_ADDR,
CONFIG_ADDRESS(ucBusNumber, ucSlotNumber,
ucFunctionNumber, ucOffset));
/*
* Read from the configuration space data register with the appropriate
* offset
*/
inport_16(PCI_CONFIG_DATA+BYTE_LANE_OFFSET(ucOffset), *pusValue);
_ISR_Enable(Irql);
return(RTEMS_SUCCESSFUL);
}
rtems_status_code PCIConfigRead32(
uint8_t ucBusNumber,
uint8_t ucSlotNumber,
uint8_t ucFunctionNumber,
uint8_t ucOffset,
uint32_t *pulValue
)
{
ISR_Level Irql;
/*
* Ensure that accesses to the addr/data ports are indivisible
*/
_ISR_Disable(Irql);
/*
* Write to the configuration space address register
*/
outport_32(PCI_CONFIG_ADDR,
CONFIG_ADDRESS(ucBusNumber, ucSlotNumber,
ucFunctionNumber, ucOffset));
/*
* Read from the configuration space data register with the appropriate
* offset
*/
inport_32(PCI_CONFIG_DATA, *pulValue);
_ISR_Enable(Irql);
return(RTEMS_SUCCESSFUL);
}
/*
* This routine determines the maximum bus number in the system
*/
void pci_initialize()
{
uint8_t ucSlotNumber, ucFnNumber, ucNumFuncs;
uint8_t ucHeader;
uint8_t ucBaseClass, ucSubClass, ucMaxSubordinate;
uint32_t ulDeviceID;
/*
* Scan PCI bus 0 looking for PCI-PCI bridges
*/
for(ucSlotNumber=0;ucSlotNumber<PCI_MAX_DEVICES;ucSlotNumber++)
{
(void)PCIConfigRead32(0,
ucSlotNumber,
0,
PCI_CONFIG_VENDOR_LOW,
&ulDeviceID);
if(ulDeviceID==PCI_INVALID_VENDORDEVICEID)
{
/*
* This slot is empty
*/
continue;
}
(void)PCIConfigRead8(0,
ucSlotNumber,
0,
PCI_CONFIG_HEADER_TYPE,
&ucHeader);
if(ucHeader&PCI_MULTI_FUNCTION)
{
ucNumFuncs=PCI_MAX_FUNCTIONS;
}
else
{
ucNumFuncs=1;
}
for(ucFnNumber=0;ucFnNumber<ucNumFuncs;ucFnNumber++)
{
(void)PCIConfigRead32(0,
ucSlotNumber,
ucFnNumber,
PCI_CONFIG_VENDOR_LOW,
&ulDeviceID);
if(ulDeviceID==PCI_INVALID_VENDORDEVICEID)
{
/*
* This slot/function is empty
*/
continue;
}
/*
* This slot/function has a device fitted.
*/
(void)PCIConfigRead8(0,
ucSlotNumber,
ucFnNumber,
PCI_CONFIG_CLASS_CODE_U,
&ucBaseClass);
(void)PCIConfigRead8(0,
ucSlotNumber,
ucFnNumber,
PCI_CONFIG_CLASS_CODE_M,
&ucSubClass);
if((ucBaseClass==PCI_BASE_CLASS_BRIDGE) &&
(ucSubClass==PCI_SUB_CLASS_BRIDGE_PCI))
{
/*
* We have found a PCI-PCI bridge
*/
(void)PCIConfigRead8(0,
ucSlotNumber,
ucFnNumber,
PCI_BRIDGE_SUBORDINATE_BUS,
&ucMaxSubordinate);
if(ucMaxSubordinate>ucMaxPCIBus)
{
ucMaxPCIBus=ucMaxSubordinate;
}
}
}
}
}
/*
* Return the number of PCI busses in the system
*/
uint8_t BusCountPCI()
{
return(ucMaxPCIBus+1);
}

153
c/src/lib/libbsp/powerpc/ppcn_60x/start/start.S
View File

@@ -1,153 +0,0 @@
/*
* This is based on the mvme-crt0.S file from libgloss/rs6000.
* crt0.S -- startup file for PowerPC systems.
*
* (c) 1998, Radstone Technology plc.
*
*
* This is an unpublished work the copyright in which vests
* in Radstone Technology plc. All rights reserved.
*
* The information contained herein is the property of Radstone
* Technology plc. and is supplied without liability for
* errors or omissions and no part may be reproduced, used or
* disclosed except as authorized by contract or other written
* permission. The copyright and the foregoing
* restriction on reproduction, use and disclosure extend to
* all the media in which this information may be
* embodied.
*
* Copyright (c) 1995 Cygnus Support
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*
* $Id$
*/
#include <ppc-asm.h>
#include <bsp.h>
.file "start.s"
.extern FUNC_NAME(atexit)
.globl FUNC_NAME(__atexit)
.section ".sdata","aw"
.align 2
FUNC_NAME(__atexit): /* tell C's eabi-ctor's we have an atexit function */
.long FUNC_NAME(atexit)@fixup /* and that it is to register __do_global_dtors */
.section ".fixup","aw"
.align 2
.long FUNC_NAME(__atexit)
.text
.globl _start
.type _start,@function
_start:
/* Set MSR */
/*
* Enable data and instruction address translation and floating point
*/
li r3,MSR_IR | MSR_DR | MSR_FP
mtmsr r3
/*
* The caches are already flushed by the firmware so just enable
*/
mfspr r3,HID0
#if PPC_USE_DATA_CACHE
/*
* Enable data and instruction cache
*/
ori r3,r3 ,H0_60X_ICE | H0_60X_DCE
#else
/*
* Enable instruction cache only
*/
ori r3,r3 ,H0_60X_ICE
#endif
mtspr HID0,r3
/* clear bss */
lis r6,__bss_start@h
ori r6,r6,__bss_start@l
lis r7,__bss_end@h
ori r7,r7,__bss_end@l
cmplw 1,r6,r7
bc 4,4,.Lbss_done
subf r8,r6,r7 /* number of bytes to zero */
srwi r9,r8,2 /* number of words to zero */
mtctr r9
li r0,0 /* zero to clear memory */
addi r6,r6,-4 /* adjust so we can use stwu */
.Lbss_loop:
stwu r0,4(r6) /* zero bss */
bdnz .Lbss_loop
.Lbss_done:
/* clear sbss */
lis r6,__sbss_start@h
ori r6,r6,__sbss_start@l
lis r7,__sbss_end@h
ori r7,r7,__sbss_end@l
cmplw 1,r6,r7
bc 4,4,.Lsbss_done
subf r8,r6,r7 /* number of bytes to zero */
srwi r9,r8,2 /* number of words to zero */
mtctr r9
li r0,0 /* zero to clear memory */
addi r6,r6,-4 /* adjust so we can use stwu */
.Lsbss_loop:
stwu r0,4(r6) /* zero sbss */
bdnz .Lsbss_loop
.Lsbss_done:
lis sp,__stack@h
ori sp,sp,__stack@l
/* set up initial stack frame */
addi sp,sp,-4 /* make sure we don't overwrite debug mem */
lis r0,0
stw r0,0(sp) /* clear back chain */
stwu sp,-56(sp) /* push another stack frame */
lis r5,environ@ha
la r5,environ@l(r5) /* environp */
li r4, 0 /* argv */
li r3, 0 /* argc */
/* Let her rip */
bl FUNC_NAME(boot_card)
/*
* This should never get reached
*/
/*
* Return MSR to its reset state
*/
li r3,0
mtmsr r3
isync
/*
* Call reset entry point
*/
lis r3,0xfff0
ori r3,r3,0x100
mtlr r3
blr
.Lstart:
.size _start,.Lstart-_start

30
c/src/lib/libbsp/powerpc/ppcn_60x/startup/bspclean.c
View File

@@ -1,30 +0,0 @@
/*
* COPYRIGHT (c) 1998 by Radstone Technology
*
*
* THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
* KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
* AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
*
* You are hereby granted permission to use, copy, modify, and distribute
* this file, provided that this notice, plus the above copyright notice
* and disclaimer, appears in all copies. Radstone Technology will provide
* no support for this code.
*
*/
/*
* bsp_cleanup()
*/
#include <rtems.h>
#include <bsp.h>
extern void bsp_trap();
void bsp_cleanup( void )
{
#if PPCN_60X_USE_DINK
bsp_trap();
#endif
}

288
c/src/lib/libbsp/powerpc/ppcn_60x/startup/bspstart.c
View File

@@ -1,288 +0,0 @@
/*
* COPYRIGHT (c) 1998 by Radstone Technology
*
*
* THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
* KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
* AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
*
* You are hereby granted permission to use, copy, modify, and distribute
* this file, provided that this notice, plus the above copyright notice
* and disclaimer, appears in all copies. Radstone Technology will provide
* no support for this code.
*
*/
/* bspstart.c
*
* This set of routines starts the application. It includes application,
* board, and monitor specific initialization and configuration.
* The generic CPU dependent initialization has been performed
* before any of these are invoked.
*
* COPYRIGHT (c) 1989-1997.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may in
* the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id:
*/
#include <string.h>
#include <bsp.h>
#include <rtems/libio.h>
#include <rtems/libcsupport.h>
#include <pci.h>
unsigned char ucSystemType;
unsigned char ucBoardRevMaj;
unsigned char ucBoardRevMin;
unsigned long ulMemorySize;
unsigned long ulCpuBusClock;
/*
* The bus speed is expressed in MHz
*/
static unsigned long ulBusSpeed[] = {
56250000,
60000000,
64300000,
66666667,
75000000,
83333333,
100000000,
66666667
};
/*
* The original table from the application and our copy of it with
* some changes.
*/
extern rtems_configuration_table Configuration;
rtems_configuration_table BSP_Configuration;
rtems_cpu_table Cpu_table;
uint32_t bsp_isr_level;
static int stdin_fd, stdout_fd, stderr_fd;
/*
* End of RTEMs image imported from linker
*/
extern int end;
/*
* Use the shared implementations of the following routines
*/
void bsp_postdriver_hook(void);
void bsp_libc_init( void *, uint32_t, int );
/*
* bsp_pretasking_hook
*
* BSP pretasking hook. Called just before drivers are initialized.
* Used to setup libc and install any BSP extensions.
*/
void bsp_pretasking_hook(void)
{
uint32_t heap_start;
uint32_t heap_size;
heap_start = (uint32_t) &end;
if (heap_start & (CPU_ALIGNMENT-1))
heap_start = (heap_start + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1);
heap_size = BSP_Configuration.work_space_start - (void *)&end;
heap_size &= 0xfffffff0; /* keep it as a multiple of 16 bytes */
bsp_libc_init((void *) heap_start, heap_size, 0);
/*
* Initialise RTC hooks based on system type
*/
InitializeRTC();
/*
* Initialise NvRAM hooks based on system type
*/
InitializeNvRAM();
/*
* Initialise the PCI bus(ses)
*/
pci_initialize();
/*
* Initialize the Universe PCI-VME bridge
*/
InitializeUniverse();
#ifdef RTEMS_DEBUG
rtems_debug_enable( RTEMS_DEBUG_ALL_MASK );
#endif
}
/*
* bsp_std_close
*
* Simple routine to close all standard IO streams.
*/
void bsp_std_close( void )
{
close(stdin_fd);
close(stdout_fd);
close(stderr_fd);
}
/*
* bsp_predriver_hook
*
* Before drivers are setup.
*/
void bsp_predriver_hook(void)
{
/* bsp_spurious_initialize; ??*/
initialize_external_exception_vector();
}
/*
* bsp_start
*
* This routine does the bulk of the system initialization.
*/
void bsp_start( void )
{
unsigned char *work_space_start;
unsigned char ucBoardRev, ucMothMemType, ucEquipPres1, ucEquipPres2;
uint16_t usPVR=0;
uint8_t ucTempl, ucTemph;
uint8_t ucBanksPresent;
uint8_t ucSimmPresent;
uint32_t ulCurBank, ulTopBank;
/*
* Determine system type
*/
inport_byte(&((PPLANARREGISTERS)0)->MotherboardMemoryType, ucMothMemType);
inport_byte(&((PPLANARREGISTERS)0)->SimmPresent, ucSimmPresent);
inport_byte(&((PPLANARREGISTERS)0)->EquipmentPresent1, ucEquipPres1);
inport_byte(&((PPLANARREGISTERS)0)->EquipmentPresent2, ucEquipPres2);
ucSystemType=((ucMothMemType&0x03)<<1) | ((ucEquipPres1&0x80)>>7);
ucSystemType^=7;
/*
* Determine board revision for use by rev. specific code
*/
inport_byte(&((PPLANARREGISTERS)0)->BoardRevision, ucBoardRev);
ucBoardRevMaj=ucBoardRev>>5;
ucBoardRevMin=ucBoardRev&0x1f;
/*
* Determine the memory size by reading the end address for top
* assigned bank in the memory controller
*/
(void)PCIConfigRead8(0,0,0,0xa0, &ucBanksPresent);
for(ulCurBank=0;ulCurBank<8;ulCurBank++)
{
if((ucBanksPresent>>ulCurBank)&0x01)
{
ulTopBank=ulCurBank;
}
}
(void)PCIConfigRead8(0,0,0,0x90+ulTopBank, &ucTempl);
(void)PCIConfigRead8(0,0,0,0x98+ulTopBank, &ucTemph);
ulMemorySize=(ucTempl+(ucTemph<<8)+1)<<20;
#if PPCN_60X_USE_DINK
ulMemorySize=0x01fe0000;
#endif
/*
* Determine processor bus clock
*/
asm volatile ("mfpvr %0" : "=r" ((usPVR)) : "0" ((usPVR)));
/*
* Determine processor internal clock
*/
if(ucSystemType==SYS_TYPE_PPC4)
{
if(((ucBoardRevMaj==1) && (ucBoardRevMin==0)) ||
((ucSimmPresent&0x40)==0))
{
/*
* Rev. 1A is always 66MHz
*/
ulCpuBusClock=66666667;
}
else
{
ulCpuBusClock=83333333;
}
}
else if((((usPVR>>16)==MPC603e) && (ucSystemType!=SYS_TYPE_PPC1)) ||
((usPVR>>16)==MPC603ev) ||
((usPVR>>16)==MPC604e))
{
ulCpuBusClock=ulBusSpeed[(ucEquipPres2&0x1c)>>2];
}
else
{
if(((ucSystemType>SYS_TYPE_PPC1) || (ucBoardRevMaj>=5)) &&
(ucEquipPres1&0x08))
{
/*
* 66 MHz bus clock for 005 if indicated
*/
ulCpuBusClock=66666667;
}
else
{
/*
* 33 MHz bus clock for 004 always
*/
ulCpuBusClock=33333333;
}
}
/*
* Allocate the memory for the RTEMS Work Space. This can come from
* a variety of places: hard coded address, malloc'ed from outside
* RTEMS world (e.g. simulator or primitive memory manager), or (as
* typically done by stock BSPs) by subtracting the required amount
* of work space from the last physical address on the CPU board.
*/
work_space_start =
(unsigned char *)ulMemorySize - BSP_Configuration.work_space_size;
if ( work_space_start <= (unsigned char *)&end ) {
DEBUG_puts( "bspstart: Not enough RAM!!!\n" );
bsp_cleanup();
}
BSP_Configuration.work_space_start = work_space_start;
/*
* initialize the CPU table for this BSP
*/
Cpu_table.exceptions_in_RAM = TRUE;
Cpu_table.pretasking_hook = bsp_pretasking_hook; /* init libc, etc. */
Cpu_table.predriver_hook = bsp_predriver_hook;
Cpu_table.postdriver_hook = bsp_postdriver_hook;
Cpu_table.do_zero_of_workspace = TRUE;
Cpu_table.interrupt_stack_size = CONFIGURE_INTERRUPT_STACK_MEMORY;
Cpu_table.clicks_per_usec = ulCpuBusClock/4000000;
}

25
c/src/lib/libbsp/powerpc/ppcn_60x/startup/bsptrap.S
View File

@@ -1,25 +0,0 @@
/*
* (c) 1998, Radstone Technology plc.
*
*
* This is an unpublished work the copyright in which vests
* in Radstone Technology plc. All rights reserved.
*
* The information contained herein is the property of Radstone
* Technology plc. and is supplied without liability for
* errors or omissions and no part may be reproduced, used or
* disclosed except as authorized by contract or other written
* permission. The copyright and the foregoing
* restriction on reproduction, use and disclosure extend to
* all the media in which this information may be
* embodied.
*
*/
#include "ppc-asm.h"
.file "bsptrap.s"
.text
FUNC_START(bsp_trap)
sc
FUNC_END(bsp_trap)

352
c/src/lib/libbsp/powerpc/ppcn_60x/startup/genpvec.c
View File

@@ -1,352 +0,0 @@
/*
* COPYRIGHT (c) 1998 by Radstone Technology
*
*
* THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
* KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
* AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
*
* You are hereby granted permission to use, copy, modify, and distribute
* this file, provided that this notice, plus the above copyright notice
* and disclaimer, appears in all copies. Radstone Technology will provide
* no support for this code.
*
*/
/* genpvec.c
*
* These routines handle the external exception. Multiple ISRs occur off
* of this one interrupt.
*
* COPYRIGHT (c) 1989-1997.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may in
* the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
#include <bsp.h>
#include <rtems/chain.h>
#include <assert.h>
/*
* Proto types for this file
*/
rtems_isr external_exception_ISR (
rtems_vector_number vector /* IN */
);
#define NUM_LIRQ_HANDLERS 20
#define NUM_LIRQ ( MAX_BOARD_IRQS - PPC_IRQ_LAST )
/*
* Current 8259 masks
*/
uint8_t ucMaster8259Mask;
uint8_t ucSlave8259Mask;
/*
* Structure to for one of possible multiple interrupt handlers for
* a given interrupt.
*/
typedef struct
{
Chain_Node Node;
rtems_isr_entry handler; /* isr routine */
rtems_vector_number vector; /* vector number */
} EE_ISR_Type;
/* Note: The following will not work if we add a method to remove
* handlers at a later time.
*/
EE_ISR_Type ISR_Nodes [NUM_LIRQ_HANDLERS];
uint16_t Nodes_Used;
Chain_Control ISR_Array [NUM_LIRQ];
void initialize_external_exception_vector()
{
rtems_isr_entry previous_isr;
rtems_status_code status;
int i;
Nodes_Used = 0;
for (i=0; i <NUM_LIRQ; i++)
{
Chain_Initialize_empty( &ISR_Array[i] );
}
/*
* Initialise the 8259s
*/
outport_byte(ISA8259_M_CTRL, 0x11); /* ICW1 */
outport_byte(ISA8259_S_CTRL, 0x11); /* ICW1 */
outport_byte(ISA8259_M_MASK, 0x00); /* ICW2 vectors 0-7 */
outport_byte(ISA8259_S_MASK, 0x08); /* ICW2 vectors 8-15 */
outport_byte(ISA8259_M_MASK, 0x04); /* ICW3 cascade on IRQ2 */
outport_byte(ISA8259_S_MASK, 0x02); /* ICW3 cascade on IRQ2 */
outport_byte(ISA8259_M_MASK, 0x01); /* ICW4 x86 normal EOI */
outport_byte(ISA8259_S_MASK, 0x01); /* ICW4 x86 normal EOI */
/*
* Enable IRQ2 cascade and disable all other interrupts
*/
ucMaster8259Mask=0xfb;
ucSlave8259Mask=0xff;
outport_byte(ISA8259_M_MASK, ucMaster8259Mask);
outport_byte(ISA8259_S_MASK, ucSlave8259Mask);
/*
* Set up edge/level
*/
switch(ucSystemType)
{
case SYS_TYPE_PPC1:
{
if(ucBoardRevMaj<5)
{
outport_byte(ISA8259_S_ELCR,
ELCRS_INT15_LVL);
}
else
{
outport_byte(ISA8259_S_ELCR,
ELCRS_INT9_LVL |
ELCRS_INT11_LVL |
ELCRS_INT14_LVL |
ELCRS_INT15_LVL);
}
outport_byte(ISA8259_M_ELCR,
ELCRM_INT5_LVL |
ELCRM_INT7_LVL);
break;
}
case SYS_TYPE_PPC1a:
{
outport_byte(ISA8259_S_ELCR,
ELCRS_INT9_LVL |
ELCRS_INT11_LVL |
ELCRS_INT14_LVL |
ELCRS_INT15_LVL);
outport_byte(ISA8259_M_ELCR,
ELCRM_INT5_LVL);
break;
}
case SYS_TYPE_PPC2:
case SYS_TYPE_PPC2a:
case SYS_TYPE_PPC4:
default:
{
outport_byte(ISA8259_S_ELCR,
ELCRS_INT9_LVL |
ELCRS_INT10_LVL |
ELCRS_INT11_LVL |
ELCRS_INT14_LVL |
ELCRS_INT15_LVL);
outport_byte(ISA8259_M_ELCR,
ELCRM_INT5_LVL |
ELCRM_INT7_LVL);
break;
}
}
/*
* Install external_exception_ISR () as the handler for
* the General Purpose Interrupt.
*/
status = rtems_interrupt_catch( external_exception_ISR,
PPC_IRQ_EXTERNAL,
(rtems_isr_entry *) &previous_isr );
}
/*
* This routine installs one of multiple ISRs for the general purpose
* inerrupt.
*/
void set_EE_vector(
rtems_isr_entry handler, /* isr routine */
rtems_vector_number vector /* vector number */
)
{
uint16_t vec_idx = vector - PPCN_60X_8259_IRQ_BASE;
uint32_t index;
assert (Nodes_Used < NUM_LIRQ_HANDLERS);
/*
* If we have already installed this handler for this vector, then
* just reset it.
*/
for ( index=0 ; index < Nodes_Used ; index++ )
{
if(ISR_Nodes[index].vector == vector &&
ISR_Nodes[index].handler == handler)
{
return;
}
}
/*
* Doing things in this order makes them more atomic
*/
Nodes_Used++;
index = Nodes_Used - 1;
ISR_Nodes[index].handler = handler;
ISR_Nodes[index].vector = vector;
Chain_Append( &ISR_Array[vec_idx], &ISR_Nodes[index].Node );
/*
* Enable the interrupt
*/
En_Ext_Interrupt(vector);
}
/*
* This interrupt service routine is called for an External Exception.
*/
rtems_isr external_exception_ISR (
rtems_vector_number vector /* IN */
)
{
uint16_t index;
uint8_t ucISr;
EE_ISR_Type *node;
index = *((volatile uint8_t*)IRQ_VECTOR_BASE);
/*
* check for spurious interrupt
*/
if(index==7)
{
/*
* OCW3 select IS register
*/
outport_byte(ISA8259_M_CTRL, 0x0b);
/*
* Read IS register
*/
inport_byte(ISA8259_M_CTRL, ucISr);
if(!(ucISr & 0x80))
{
/*
* Spurious interrupt
*/
return;
}
}
node=(EE_ISR_Type *)ISR_Array[index].first;
while(!_Chain_Is_tail(&ISR_Array[index], (Chain_Node *)node))
{
(*node->handler)( node->vector );
node = (EE_ISR_Type *)node->Node.next;
}
/*
* Dismiss the interrupt
*/
if(index&8)
{
/*
* Dismiss the interrupt in Slave first as it
* is cascaded
*/
outport_byte(ISA8259_S_CTRL, NONSPECIFIC_EOI);
}
/*
* Dismiss the interrupt in Master
*/
outport_byte(ISA8259_M_CTRL, NONSPECIFIC_EOI);
}
void Dis_Ext_Interrupt(int level)
{
ISR_Level Irql;
level-=PPCN_60X_8259_IRQ_BASE;
if(level==2)
{
/*
* Level 2 is for cascade and must not be fiddled with
*/
return;
}
/*
* Ensure that accesses to the mask are indivisible
*/
_ISR_Disable(Irql);
if(level<8)
{
/*
* Interrupt is handled by Master
*/
ucMaster8259Mask|=1<<level;
outport_byte(ISA8259_M_MASK, ucMaster8259Mask);
}
else
{
/*
* Interrupt is handled by Slave
*/
ucSlave8259Mask|=1<<(level-8);
outport_byte(ISA8259_S_MASK, ucSlave8259Mask);
}
_ISR_Enable(Irql);
}
void En_Ext_Interrupt(int level)
{
ISR_Level Irql;
level-=PPCN_60X_8259_IRQ_BASE;
if(level==2)
{
/*
* Level 2 is for cascade and must not be fiddled with
*/
return;
}
/*
* Ensure that accesses to the mask are indivisible
*/
_ISR_Disable(Irql);
if(level<8)
{
/*
* Interrupt is handled by Master
*/
ucMaster8259Mask&=~(1<<level);
outport_byte(ISA8259_M_MASK, ucMaster8259Mask);
}
else
{
/*
* Interrupt is handled by Slave
*/
ucSlave8259Mask&=~(1<<(level-8));
outport_byte(ISA8259_S_MASK, ucSlave8259Mask);
}
_ISR_Enable(Irql);
}

188
c/src/lib/libbsp/powerpc/ppcn_60x/startup/linkcmds
View File

@@ -1,188 +0,0 @@
OUTPUT_FORMAT("elf32-powerpc", "elf32-powerpc",
"elf32-powerpc")
OUTPUT_ARCH(powerpc)
ENTRY(_start)
/*
* Number of Decrementer countdowns per millisecond
*
* Calculated by: (66.67 Mhz * 1000) / 4 cycles per click
*/
SECTIONS
{
.vectors 0x00100 :
{
*(.vectors)
}
/* Read-only sections, merged into text segment: */
/* SDS ROM worked at 0x30000 */
. = 0x30000;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rela.text : { *(.rela.text) }
.rela.data : { *(.rela.data) }
.rela.rodata : { *(.rela.rodata) }
.rela.got : { *(.rela.got) }
.rela.got1 : { *(.rela.got1) }
.rela.got2 : { *(.rela.got2) }
.rela.ctors : { *(.rela.ctors) }
.rela.dtors : { *(.rela.dtors) }
.rela.init : { *(.rela.init) }
.rela.fini : { *(.rela.fini) }
.rela.bss : { *(.rela.bss) }
.rela.plt : { *(.rela.plt) }
.rela.sdata : { *(.rela.sdata2) }
.rela.sbss : { *(.rela.sbss2) }
.rela.sdata2 : { *(.rela.sdata2) }
.rela.sbss2 : { *(.rela.sbss2) }
.plt : { *(.plt) }
.text :
{
*(.text)
/*
* Special FreeBSD sysctl sections.
*/
. = ALIGN (16);
__start_set_sysctl_set = .;
*(set_sysctl_*);
__stop_set_sysctl_set = ABSOLUTE(.);
*(set_domain_*);
*(set_pseudo_*);
*(.gnu.linkonce.t.*)
*(.descriptors)
/* .gnu.warning sections are handled specially by elf32.em. */
*(.gnu.warning)
} =0
.init : { _init = .; *(.init) }
.fini : { _fini = .; *(.fini) }
.rodata : { *(.rodata*) *(.gnu.linkonce.r*) }
.rodata1 : { *(.rodata1) }
.eh_frame : { *.(eh_frame) }
_etext = .;
PROVIDE (etext = .);
PROVIDE (__SDATA2_START__ = .);
.sdata2 : { *(.sdata2) *(.gnu.linkonce.s2.*) }
.sbss2 : { *(.sbss2) *(.gnu.linkonce.sb2.*) }
PROVIDE (__SBSS2_START__ = .);
.sbss2 : { *(.sbss2) }
PROVIDE (__SBSS2_END__ = .);
/* Adjust the address for the data segment. We want to adjust up to
the same address within the page on the next page up. It would
be more correct to do this:
. = ALIGN(0x40000) + (ALIGN(8) & (0x40000 - 1));
The current expression does not correctly handle the case of a
text segment ending precisely at the end of a page; it causes the
data segment to skip a page. The above expression does not have
this problem, but it will currently (2/95) cause BFD to allocate
a single segment, combining both text and data, for this case.
This will prevent the text segment from being shared among
multiple executions of the program; I think that is more
important than losing a page of the virtual address space (note
that no actual memory is lost; the page which is skipped can not
be referenced). */
. = ALIGN(8) + 0x40000;
PROVIDE (sdata = .);
.data :
{
*(.data)
*(.gnu.linkonce.d.*)
CONSTRUCTORS
}
PROVIDE (__EXCEPT_START__ = .);
.gcc_except_table : { *(.gcc_except_table) }
PROVIDE (__EXCEPT_END__ = .);
.data1 : { *(.data1) }
.got1 : { *(.got1) }
.dynamic : { *(.dynamic) }
/* Put .ctors and .dtors next to the .got2 section, so that the pointers
get relocated with -mrelocatable. Also put in the .fixup pointers.
The current compiler no longer needs this, but keep it around for 2.7.2 */
PROVIDE (_GOT2_START_ = .);
.got2 : { *(.got2) }
PROVIDE (__GOT2_END__ = .);
PROVIDE (__CTOR_LIST__ = .);
.ctors : { *(.ctors) }
PROVIDE (__CTOR_END__ = .);
PROVIDE (__DTOR_LIST__ = .);
.dtors : { *(.dtors) }
PROVIDE (__DTOR_END__ = .);
PROVIDE (_FIXUP_START_ = .);
.fixup : { *(.fixup) }
PROVIDE (_FIXUP_END_ = .);
PROVIDE (__FIXUP_END__ = .);
PROVIDE (_GOT2_END_ = .);
PROVIDE (_GOT_START_ = .);
s.got = .;
.got : { *(.got) }
.got.plt : { *(.got.plt) }
PROVIDE (_GOT_END_ = .);
PROVIDE (__GOT_END__ = .);
/* We want the small data sections together, so single-instruction offsets
can access them all, and initialized data all before uninitialized, so
we can shorten the on-disk segment size. */
PROVIDE (__SDATA_START__ = .);
.sdata : { *(.sdata) *(.gnu.linkonce.s.*) }
_edata = .;
PROVIDE (edata = .);
. = ALIGN(8) + 0x1000;
PROVIDE (__SBSS_START__ = .);
.sbss :
{
PROVIDE (__sbss_start = .);
*(.sbss)
*(.scommon)
PROVIDE (__sbss_end = .);
}
PROVIDE (__SBSS_END__ = .);
.bss :
{
PROVIDE (__bss_start = .);
*(.dynbss)
*(.bss)
*(COMMON)
PROVIDE (__bss_end = .);
}
. = ALIGN(8) + 0x8000;
PROVIDE (__stack = .);
_end = . ;
PROVIDE (end = .);
/* These are needed for ELF backends which have not yet been
converted to the new style linker. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
/* These must appear regardless of . */
}

123
c/src/lib/libbsp/powerpc/ppcn_60x/startup/rtems-ctor.cc
View File

@@ -1,123 +0,0 @@
/*
* rtems-ctor.cc
*
* Description:
* This file exists solely to (try to) ensure RTEMS is initialized
* before any global constructors are run.
*
* The problem:
* Global constructors might reasonably expect that new() will
* work, but since new() uses malloc() which uses RTEMS regions,
* it can not be called until after initialize_executive().
*
* Global constructors are called in GNU systems one of 2 ways:
*
* an "invisible" call to __main() inserted by compiler
* This __main() calls __do_global_ctors() which
* walks thru the table and calls all global
* constructors.
*
* or -
* A special section is put into the linked binary. The
* system startup code knows to run the constructors in
* this special section before calling main().
*
* By making RTEMS initialization a constructor, we avoid having
* too much about all this. All we have to guarantee is that
* this constructor is the first one run.
*
*
* So for the first case above, this is what happens
*
* host crt0
* main()
* __main()
* __do_global_ctors()
* bsp_start()
* init_executive_early()
* <<any other constructors>>
*
* rtems_init_executive_late()
* bsp_cleanup()
*
* TODO:
*
*
* COPYRIGHT (c) 1989-1997.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may in
* the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id:
*/
#include <bsp.h>
/*
* RTEMS program name
* Probably not used by anyone, but it is nice to have it.
* Actually the UNIX version of CPU_INVOKE_DEBUGGER will probably
* need to use it
*/
char *rtems_progname;
char **rtems_environp;
#ifdef USE_CONSTRUCTORS_FOR_INIT_EXEC
class RTEMS {
public:
RTEMS();
~RTEMS();
};
RTEMS rtems_constructor;
RTEMS::RTEMS()
{
bsp_start();
}
RTEMS::~RTEMS()
{
bsp_cleanup();
}
#endif
extern "C" {
int
main(int argc,
char **argv,
char **environp)
{
#ifndef USE_CONSTRUCTORS_FOR_INIT_EXEC
bsp_start();
#endif
if ((argc > 0) && argv && argv[0])
rtems_progname = argv[0];
else
rtems_progname = "RTEMS";
rtems_environp = environp;
/*
* Start multitasking
*/
rtems_initialize_executive_late( bsp_isr_level );
#ifndef USE_CONSTRUCTORS_FOR_INIT_EXEC
bsp_cleanup();
#endif
/*
* Returns when multitasking is stopped
* This allows our destructors to get run normally
*/
return 0;
}
}

53
c/src/lib/libbsp/powerpc/ppcn_60x/startup/setvec.c
View File

@@ -1,53 +0,0 @@
/* set_vector
*
* This routine installs an interrupt vector on the target Board/CPU.
* This routine is allowed to be as board dependent as necessary.
*
* INPUT:
* handler - interrupt handler entry point
* vector - vector number
* type - 0 indicates raw hardware connect
* 1 indicates RTEMS interrupt connect
*
* RETURNS:
* address of previous interrupt handler
*
* COPYRIGHT (c) 1989-1997.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may in
* the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id:
*/
#include <rtems.h>
#include <bsp.h>
/*
* This routine installs vector number vector.
*
*/
rtems_isr_entry set_vector( /* returns old vector */
rtems_isr_entry handler, /* isr routine */
rtems_vector_number vector, /* vector number */
int type /* RTEMS or RAW intr */
)
{
rtems_isr_entry previous_isr;
rtems_status_code status;
/*
* vectors greater than PPC_IRQ_LAST are handled by the General purpose
* interupt handler. (8259)
*/
if ( vector > PPC_IRQ_LAST ) {
set_EE_vector ( handler, vector );
}
else {
status = rtems_interrupt_catch
( handler, vector, (rtems_isr_entry *) &previous_isr );
}
return previous_isr;
}

171
c/src/lib/libbsp/powerpc/ppcn_60x/startup/spurious.c
View File

@@ -1,171 +0,0 @@
/*
* PPCn_60x Spurious Trap Handler
*
* This is just enough of a trap handler to let us know what
* the likely source of the trap was.
*
* Based upon the SPARC ERC32 version which was developed as
* part of the port of RTEMS to the ERC32 implementation
* of the SPARC by On-Line Applications Research Corporation (OAR)
* under contract to the European Space Agency (ESA).
*
* COPYRIGHT (c) 1995. European Space Agency.
*
* This terms of the RTEMS license apply to this file.
*
* $Id$
*/
#include <bsp.h>
#include <string.h>
rtems_isr bsp_stub_handler(
rtems_vector_number trap
)
{
}
/*
* bsp_spurious_handler
*
* Print a message on the debug console and then die
*/
rtems_isr bsp_spurious_handler(
rtems_vector_number trap
)
{
DEBUG_puts( "Spurious Trap" );
switch ( trap ) {
case PPC_IRQ_SYSTEM_RESET:
DEBUG_puts( "System reset" );
break;
case PPC_IRQ_MCHECK:
DEBUG_puts( "Machine check" );
break;
case PPC_IRQ_PROTECT:
DEBUG_puts( "DSI" );
break;
case PPC_IRQ_ISI:
DEBUG_puts( "ISI" );
break;
case PPC_IRQ_EXTERNAL:
DEBUG_puts( "External interupt" );
break;
case PPC_IRQ_ALIGNMENT:
DEBUG_puts( "Alignment Exception" );
break;
case PPC_IRQ_PROGRAM:
DEBUG_puts( "Program" );
break;
case PPC_IRQ_NOFP:
DEBUG_puts( "Floating point unavailable" );
break;
case PPC_IRQ_DECREMENTER:
DEBUG_puts( "Decrementer" );
break;
case PPC_IRQ_RESERVED_A:
DEBUG_puts( "Reserved 0x00a00" );
break;
case PPC_IRQ_RESERVED_B:
DEBUG_puts( "Reserved 0x00b00" );
break;
case PPC_IRQ_SCALL:
DEBUG_puts( "System call" );
break;
case PPC_IRQ_TRACE:
DEBUG_puts( "Trace" );
break;
case PPC_IRQ_FP_ASST:
DEBUG_puts( "Floating point Assist" );
break;
#if defined(ppc403) || defined(ppc405)
case PPC_IRQ_CRIT :
DEBUG_puts( "Critical Error ");
break;
case PPC_IRQ_PIT:
DEBUG_puts( "Prog. Interval Timer " );
break;
case PPC_IRQ_FIT:
DEBUG_puts( "Fixed Interval Timer " );
break;
case PPC_IRQ_WATCHDOG :
DEBUG_puts( "Watchdog Timer " );
break;
case PPC_IRQ_DEBUG :
DEBUG_puts( "Debug " );
break;
#elif defined(ppc601)
#error "Please fill in names. "
case PPC_IRQ_TRACE :
DEBUG_puts( "0x02000" );
break;
#elif defined(ppc603) || defined(ppc603e)
case PPC_IRQ_TRANS_MISS:
DEBUG_puts( "Instruction Translation Miss" );
break;
case PPC_IRQ_DATA_LOAD:
DEBUG_puts( "Data Load Translation Miss" );
break;
case PPC_IRQ_DATA_STORE:
DEBUG_puts( "Data store Translation Miss");
break;
case PPC_IRQ_ADDR_BRK:
DEBUG_puts( "Instruction address break point" );
break;
case PPC_IRQ_SYS_MGT:
DEBUG_puts( "System management interrupt" );
break;
#elif defined(mpc604)
#error "Please fill in names. "
case PPC_IRQ_ADDR_BRK:
DEBUG_puts( "0x1300" );
break;
case PPC_IRQ_SYS_MGT:
DEBUG_puts( "0x1400" );
break;
#endif
default:
DEBUG_puts( "Undefined exception " );
break;
}
/*
* What else can we do but stop ...
*/
/*
asm volatile( "" );
*/
}
/*
* bsp_spurious_initialize
*
* Install the spurious handler for most traps.
*/
void bsp_spurious_initialize()
{
uint32_t trap;
for ( trap=0 ; trap < PPC_IRQ_LAST ; trap++ ) {
/*
* Skip window overflow, underflow, and flush as well as software
* trap 0 which we will use as a shutdown.
*/
set_vector( bsp_spurious_handler, trap, 1 );
}
set_vector( bsp_stub_handler, PPC_IRQ_DECREMENTER, 1 );
set_vector( bsp_stub_handler, PPC_IRQ_TRACE, 1 );
set_vector( bsp_stub_handler, PPC_IRQ_SYS_MGT, 1 );
}

63
c/src/lib/libbsp/powerpc/ppcn_60x/startup/swap.c
View File

@@ -1,63 +0,0 @@
/*
* COPYRIGHT (c) 1998 by Radstone Technology
*
*
* THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
* KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
* AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
*
* You are hereby granted permission to use, copy, modify, and distribute
* this file, provided that this notice, plus the above copyright notice
* and disclaimer, appears in all copies. Radstone Technology will provide
* no support for this code.
*
*/
#include <rtems.h>
/*
* JRS - February 20, 1998
*
* There is a swap32 in each port. So this should be removed.
*
* Adding a swap16 to the port would be useful.
*
* The end of all this would be to remove this file.
*/
inline unsigned int Swap32(
uint32_t ulValue
)
{
uint32_t ulSwapped;
asm volatile(
"rlwimi %0,%1,8,24,31;"
"rlwimi %0,%1,24,16,23;"
"rlwimi %0,%1,8,8,15;"
"rlwimi %0,%1,24,0,7;" :
"=&r" ((ulSwapped)) :
"r" ((ulValue))
);
return( ulSwapped );
}
inline unsigned int Swap16(
uint16_t usValue
)
{
uint16_t usSwapped;
asm volatile(
"rlwimi %0,%1,24,24,31;"
"rlwimi %0,%1,8,16,23;" :
"=&r" ((usSwapped)) :
"r" ((usValue))
);
return( usSwapped );
}

81
c/src/lib/libbsp/powerpc/ppcn_60x/timer/timer.c
View File

@@ -1,81 +0,0 @@
/* timer.c
*
* This file implements a benchmark timer using the General Purpose Timer.
*
* Notes:
*
* BSP_TIMER_AVG_OVERHEAD and BSP_TIMER_LEAST_VALID are required to be
* provided in bsp.h
*
* COPYRIGHT (c) 1989-1997.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may in
* the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
#include <assert.h>
#include <bsp.h>
uint64_t Timer_driver_Start_time;
rtems_boolean Timer_driver_Find_average_overhead;
/*
* Timer_initialize
*/
void Timer_initialize()
{
/*
* Timer runs long and accurate enough not to require an interrupt.
*/
Timer_driver_Start_time = PPC_Get_timebase_register();
}
/*
* Read_timer
*/
int Read_timer()
{
uint64_t clicks;
uint64_t total64;
uint32_t total;
/* approximately CLOCK_SPEED clicks per microsecond */
clicks = PPC_Get_timebase_register();
assert( clicks > Timer_driver_Start_time );
total64 = clicks - Timer_driver_Start_time;
assert( total64 <= 0xffffffff ); /* fits into a uint32_t */
total = (uint32_t) total64;
if ( Timer_driver_Find_average_overhead == 1 )
return total; /* in "clicks" of the decrementer units */
if ( total < BSP_TIMER_LEAST_VALID )
return 0; /* below timer resolution */
return BSP_Convert_decrementer(total - BSP_TIMER_AVG_OVERHEAD);
}
rtems_status_code Empty_function( void )
{
return RTEMS_SUCCESSFUL;
}
void Set_find_average_overhead(
rtems_boolean find_flag
)
{
Timer_driver_Find_average_overhead = find_flag;
}

95
c/src/lib/libbsp/powerpc/ppcn_60x/tod/cmos.h
View File

@@ -1,95 +0,0 @@
/* Structure map for CMOS on PowerPC Reference Platform */
/*
* COPYRIGHT (c) 1998 by Radstone Technology
*
*
* THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
* KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
* AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
*
* You are hereby granted permission to use, copy, modify, and distribute
* this file, provided that this notice, plus the above copyright notice
* and disclaimer, appears in all copies. Radstone Technology will provide
* no support for this code.
*
*/
/* CMOS is the 64 bytes of RAM in the DS1385 chip */
/* The CRC's are computed with x**16+x**12+x**5 + 1 polynomial */
/* The clock is kept in 24 hour BCD mode and should be set to UT(GMT) */
#ifndef _CMOS_
#define _CMOS_
/*
* Address port is at 0x70, data at 0x71
*/
#define RTC_PORT 0x70
/* Define Realtime Clock register numbers. */
#define RTC_SECOND 0 /* second of minute [0..59] */
#define RTC_SECOND_ALARM 1 /* seconds to alarm */
#define RTC_MINUTE 2 /* minute of hour [0..59] */
#define RTC_MINUTE_ALARM 3 /* minutes to alarm */
#define RTC_HOUR 4 /* hour of day [0..23] */
#define RTC_HOUR_ALARM 5 /* hours to alarm */
#define RTC_DAY_OF_WEEK 6 /* day of week [1..7] */
#define RTC_DAY_OF_MONTH 7 /* day of month [1..31] */
#define RTC_MONTH 8 /* month of year [1..12] */
#define RTC_YEAR 9 /* year [00..99] */
#define RTC_CONTROL_REGISTERA 10 /* control register A */
#define RTC_CONTROL_REGISTERB 11 /* control register B */
#define RTC_CONTROL_REGISTERC 12 /* control register C */
#define RTC_CONTROL_REGISTERD 13 /* control register D */
#define RTC_BATTERY_BACKED_UP_RAM 14 /* battery backed up RAM [0..49] */
/* Define Control Register A structure. */
#define DS1385_REGA_UIP 0x80
/* Define Control Register B structure. */
#define DS1385_REGB_SET_TIME 0x80
#define DS1385_REGB_TIM_IRQ_EN 0x40
#define DS1385_REGB_ALM_IRQ_EN 0x20
#define DS1385_REGB_UPD_IRQ_EN 0x10
#define DS1385_REGB_SQR_EN 0x08
#define DS1385_REGB_DATA_M 0x04
#define DS1385_REGB_HOURS_FMT 0x02
#define DS1385_REGB_DLS_EN 0x01
/* Define Control Register C structure. */
#define DS1385_REGC_IRQ_REQ 0x08
#define DS1385_REGC_IRQ_TIME 0x04
#define DS1385_REGC_IRQ_ALM 0x02
#define DS1385_REGC_IRQ_UPD 0x01
/* Define Control Register D structure. */
#define DS1385_REGD_VALID 0x80
typedef struct _CMOS_MAP {
volatile uint8_t DateAndTime[14];
uint8_t SystemDependentArea1[2];
uint8_t SystemDependentArea2[8];
uint8_t FeatureByte0[1];
uint8_t FeatureByte1[1]; /* 19 = PW Flag;
attribute = write protect */
uint8_t Century[1]; /* century byte in BCD, e.g. 0x19 currently */
uint8_t FeatureByte3[1];
uint8_t FeatureByte4[1];
uint8_t FeatureByte5[1];
uint8_t FeatureByte6[1];
uint8_t FeatureByte7[1]; /* 1F = Alternate PW Flag;
attribute = write protect */
uint8_t BootPW[14]; /* Power-on password needed to boot system;
reset value = 0x00000000000000005a5a5a5a5a5a);
attribute = lock */
uint8_t BootCrc[2]; /* CRC on BootPW */
uint8_t ConfigPW[14]; /* Configuration Password needed to
change configuration of system;
reset value = 0x00000000000000005a5a5a5a5a5a);
attribute = lock */
uint8_t ConfigCrc[2]; /* CRC on ConfigPW */
} CMOS_MAP, *PCMOS_MAP;
#endif /* _CMOS_ */

614
c/src/lib/libbsp/powerpc/ppcn_60x/tod/tod.c
View File

@@ -1,614 +0,0 @@
/*
* COPYRIGHT (c) 1998 by Radstone Technology
*
*
* THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
* KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
* AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
*
* You are hereby granted permission to use, copy, modify, and distribute
* this file, provided that this notice, plus the above copyright notice
* and disclaimer, appears in all copies. Radstone Technology will provide
* no support for this code.
*
*/
#define MIN_YEAR 1996
#include <stdlib.h>
#include "bsp.h"
#include "cmos.h"
#include "../nvram/mk48t18.h"
#define Bin2BCD(Value) (((Value / 10) << 4) | (Value % 10))
#define BCD2Bin(BcdValue) ((BcdValue >> 4) * 10 + (BcdValue & 0x0f))
/*
* Private types
*/
typedef
void
(*PTIMESET)
(
rtems_time_of_day *pTOD
);
typedef
boolean
(*PTIMEGET)
(
rtems_time_of_day *pTOD
);
typedef struct _TIME_ENTRY_TABLE
{
PTIMESET SetTime;
PTIMEGET GetTime;
} TIME_ENTRY_TABLE, *PTIME_ENTRY_TABLE;
/*
* Private routines
*/
/*
* DS1385 specific routines
*/
static void timeDsSet(rtems_time_of_day *pTOD);
static boolean timeDsGet(rtems_time_of_day *pTOD);
/*
* MK48T18 specific routines
*/
static void timeMkSet(rtems_time_of_day *pTOD);
static boolean timeMkGet(rtems_time_of_day *pTOD);
TIME_ENTRY_TABLE timeDsTable =
{
timeDsSet,
timeDsGet
};
TIME_ENTRY_TABLE timeMkTable =
{
timeMkSet,
timeMkGet
};
/*
* Private variables
*/
static PTIME_ENTRY_TABLE pTimeFunc;
/*
* Mutual-exclusion semaphore
*/
static rtems_id semRTC;
/*
* This only works for the Gregorian calendar - i.e. after 1752 (in the UK)
*/
uint8_t
GregorianDay(rtems_time_of_day *pTOD)
{
boolean isLeap;
unsigned long leapsToDate;
unsigned long lastYear;
unsigned long day;
unsigned long MonthOffset[] = { 0, 31, 59, 90, 120, 151,
181, 212, 243, 273, 304, 334 };
lastYear=pTOD->year-1;
/*
* Number of leap corrections to apply up to end of last year
*/
leapsToDate = lastYear/4 - lastYear/100 + lastYear/400;
/*
* This year is a leap year if it is divisible by 4 except when it is
* divisible by 100 unless it is divisible by 400
*
* e.g. 1904 was a leap year, 1900 was not, 1996 is, and 2000 will be
*/
isLeap = (pTOD->year%4==0) &&
((pTOD->year%100!=0) || (pTOD->year%400==0));
if(isLeap && (pTOD->month>2))
{
day=1;
}
else
{
day=0;
}
day += lastYear*365 + leapsToDate + MonthOffset[pTOD->month-1] +
pTOD->day;
return((uint8_t)(day%7));
}
void
DsWriteRawClockRegister (
uint8_t Register,
uint8_t Value
)
/*++
Routine Description:
This routine reads the specified realtime clock register.
This function was added to bridge the BCD format of the IBM roms
and the binary formate of NT
Arguments:
Register - Supplies the number of the register whose value is read.
Return Value:
The value of the register is returned as the function value.
--*/
{
outport_byte((uint8_t*)RTC_PORT, Register & 0x7f);
/* Read the realtime clock register value. */
outport_byte((uint8_t*)(RTC_PORT + 1), Value);
return;
}
uint8_t
DsReadRawClockRegister (
uint8_t Register
)
/*++
Routine Description:
This routine reads the specified realtime clock register.
This function was added to bridge the BCD format of the IBM roms
and the binary formate of NT
Arguments:
Register - Supplies the number of the register whose value is read.
Return Value:
The value of the register is returned as the function value.
--*/
{
uint8_t ucDataByte;
outport_byte((uint8_t*)RTC_PORT, Register & 0x7f);
/* Read the realtime clock register value. */
inport_byte((uint8_t*)(RTC_PORT + 1), ucDataByte);
return ucDataByte;
}
void
DsWriteClockRegister (
uint8_t Register,
uint8_t Value
)
/*++
Routine Description:
This routine writes the specified value to the specified realtime
clock register.
Arguments:
Register - Supplies the number of the register whose value is written.
Value - Supplies the value that is written to the specified register.
Return Value:
The value of the register is returned as the function value.
--*/
{
uint8_t BcdValue;
BcdValue = Bin2BCD(Value);
DsWriteRawClockRegister(Register, BcdValue);
return;
}
uint8_t
DsReadClockRegister (
uint8_t Register
)
/*++
Routine Description:
This routine reads the specified realtime clock register.
Arguments:
Register - Supplies the number of the register whose value is read.
Return Value:
The value of the register is returned as the function value.
--*/
{
uint8_t BcdValue;
BcdValue = DsReadRawClockRegister(Register);
return BCD2Bin(BcdValue);
}
void
timeDsSet (
rtems_time_of_day *pTOD
)
/*++
Routine Description:
This routine sets the realtime clock.
N.B. This routine assumes that the caller has provided any required
synchronization to set the realtime clock information.
Arguments:
pTOD - Supplies a pointer to a time structure that specifies the
realtime clock information.
Return Value:
If the power to the realtime clock has not failed, then the time
values are written to the realtime clock and a value of TRUE is
returned. Otherwise, a value of FALSE is returned.
--*/
{
uint8_t ucDataByte;
PCMOS_MAP pCMOS = (PCMOS_MAP)0;
/* If the realtime clock battery is still functioning, then write */
/* the realtime clock values, and return a function value of TRUE. */
/* Otherwise, return a function value of FALSE. */
ucDataByte = DsReadRawClockRegister(RTC_CONTROL_REGISTERD);
if (ucDataByte&DS1385_REGD_VALID)
{
/* Set the realtime clock control to set the time. */
ucDataByte = DS1385_REGB_HOURS_FMT | DS1385_REGB_SET_TIME;
DsWriteRawClockRegister(RTC_CONTROL_REGISTERB, ucDataByte);
/* Write the realtime clock values. */
DsWriteClockRegister(RTC_YEAR,
(uint8_t)(pTOD->year%100));
if(pTOD->year>=100)
{
DsWriteClockRegister((uint8_t)
((unsigned long)&pCMOS->Century),
pTOD->year/100);
}
DsWriteClockRegister(RTC_MONTH,
(uint8_t)pTOD->month);
DsWriteClockRegister(RTC_DAY_OF_MONTH,
(uint8_t)pTOD->day);
DsWriteClockRegister(RTC_DAY_OF_WEEK,
(uint8_t)
(GregorianDay(pTOD) + 1));
DsWriteClockRegister(RTC_HOUR,
(uint8_t)pTOD->hour);
DsWriteClockRegister(RTC_MINUTE,
(uint8_t)pTOD->minute);
DsWriteClockRegister(RTC_SECOND,
(uint8_t)pTOD->second);
/* Set the realtime clock control to update the time. */
ucDataByte &= ~DS1385_REGB_SET_TIME;
DsWriteRawClockRegister(RTC_CONTROL_REGISTERB, ucDataByte);
return;
}
else
{
return;
}
}
boolean
timeDsGet (
rtems_time_of_day *pTOD
)
/*++
Routine Description:
This routine queries the realtime clock.
Arguments:
pTOD - Supplies a pointer to a time structure that receives
the realtime clock information.
Return Value:
If the power to the realtime clock has not failed, then the time
values are read from the realtime clock and a value of TRUE is
returned. Otherwise, a value of FALSE is returned.
--*/
{
uint8_t ucDataByte;
PCMOS_MAP pCMOS = (PCMOS_MAP)0;
/* If the realtime clock battery is still functioning, then read */
/* the realtime clock values, and return a function value of TRUE. */
/* Otherwise, return a function value of FALSE. */
ucDataByte = DsReadRawClockRegister(RTC_CONTROL_REGISTERD);
if(ucDataByte&DS1385_REGD_VALID)
{
/* Wait until the realtime clock is not being updated. */
do
{
ucDataByte=DsReadRawClockRegister(RTC_CONTROL_REGISTERA);
} while (ucDataByte&DS1385_REGA_UIP);
/* Read the realtime clock values. */
pTOD->year=(uint16_t)
(DsReadClockRegister(
(uint8_t)
(unsigned long)&pCMOS->Century)
*100 + DsReadClockRegister(RTC_YEAR));
pTOD->month=DsReadClockRegister(RTC_MONTH);
pTOD->day=DsReadClockRegister(RTC_DAY_OF_MONTH);
pTOD->hour=DsReadClockRegister(RTC_HOUR);
pTOD->minute=DsReadClockRegister(RTC_MINUTE);
pTOD->second=DsReadClockRegister(RTC_SECOND);
return TRUE;
}
else
{
return FALSE;
}
}
void
timeMkSet (
rtems_time_of_day *pTOD
)
/*++
Routine Description:
This routine sets the realtime clock.
N.B. This routine assumes that the caller has provided any required
synchronization to set the realtime clock information.
Arguments:
pTOD - Supplies a pointer to a time structure that specifies the
realtime clock information.
Return Value:
If the power to the realtime clock has not failed, then the time
values are written to the realtime clock and a value of TRUE is
returned. Otherwise, a value of FALSE is returned.
--*/
{
PMK48T18_NVRAM_MAP pNvRAM = MK48T18_BASE;
/*
* Set the RTC into write mode
*/
pNvRAM->CMOS.Control|=MK48T18_CTRL_WRITE;
EIEIO;
/*
* Write the realtime clock values.
*/
pNvRAM->CMOS.Year = (uint8_t)Bin2BCD(pTOD->year%100);
if(pTOD->year>=100)
{
pNvRAM->CMOS.Century=(uint8_t)
Bin2BCD(pTOD->year/100);
}
pNvRAM->CMOS.Month = (uint8_t)Bin2BCD(pTOD->month);
pNvRAM->CMOS.Date = (uint8_t)Bin2BCD(pTOD->day);
pNvRAM->CMOS.Day = (uint8_t)(GregorianDay(pTOD) + 1);
pNvRAM->CMOS.Hour = (uint8_t)Bin2BCD(pTOD->hour);
pNvRAM->CMOS.Minute = (uint8_t)Bin2BCD(pTOD->minute);
pNvRAM->CMOS.Second = (uint8_t)Bin2BCD(pTOD->second);
/*
* Set the realtime clock control to update the time.
*/
EIEIO;
pNvRAM->CMOS.Control&=~MK48T18_CTRL_WRITE;
}
boolean
timeMkGet (
rtems_time_of_day *pTOD
)
/*++
Routine Description:
This routine queries the realtime clock.
N.B. This routine is required to provide any synchronization necessary
to query the realtime clock information.
Arguments:
pTOD - Supplies a pointer to a time structure that receives
the realtime clock information.
Return Value:
If the power to the realtime clock has not failed, then the time
values are read from the realtime clock and a value of TRUE is
returned. Otherwise, a value of FALSE is returned.
--*/
{
PMK48T18_NVRAM_MAP pNvRAM = MK48T18_BASE;
/*
* Set the RTC into read mode
*/
pNvRAM->CMOS.Control|=MK48T18_CTRL_READ;
EIEIO;
/*
* Read the realtime clock values.
*/
pTOD->year = (uint16_t)(100*BCD2Bin(pNvRAM->CMOS.Century)+
BCD2Bin(pNvRAM->CMOS.Year));
pTOD->month = (uint8_t)BCD2Bin(pNvRAM->CMOS.Month);
pTOD->day = (uint8_t)BCD2Bin(pNvRAM->CMOS.Date);
pTOD->hour = (uint8_t)BCD2Bin(pNvRAM->CMOS.Hour);
pTOD->minute = (uint8_t)BCD2Bin(pNvRAM->CMOS.Minute);
pTOD->second = (uint8_t)BCD2Bin(pNvRAM->CMOS.Second);
/*
* Set the realtime clock control to normal mode.
*/
EIEIO;
pNvRAM->CMOS.Control&=~MK48T18_CTRL_READ;
return TRUE;
}
/*
* Set up entry table
*/
void
InitializeRTC(void)
{
rtems_status_code sc;
switch(ucSystemType)
{
case SYS_TYPE_PPC1:
{
if(ucBoardRevMaj<5)
{
pTimeFunc=&timeDsTable;
break;
}
/*
* For the 005 and later drop through to the PPC1a support
*/
}
case SYS_TYPE_PPC1a:
{
pTimeFunc=&timeMkTable;
break;
}
default:
{
pTimeFunc=&timeDsTable;
break;
}
}
/*
* Set up mutex semaphore
*/
sc = rtems_semaphore_create (
rtems_build_name ('R', 'T', 'C', 's'),
1,
RTEMS_BINARY_SEMAPHORE |
RTEMS_INHERIT_PRIORITY |
RTEMS_PRIORITY,
RTEMS_NO_PRIORITY,
&semRTC);
if (sc != RTEMS_SUCCESSFUL)
{
rtems_fatal_error_occurred (sc);
}
}
void setRealTimeToRTEMS()
{
rtems_time_of_day rtc_tod;
rtems_semaphore_obtain(semRTC, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
(pTimeFunc->GetTime)(&rtc_tod);
rtems_semaphore_release(semRTC);
/*
* Millenium fix...
*
* If year is earlier than MIN_YEAR then assume the clock has wrapped from
* 1999 to 1900 so advance by a century
*/
if(rtc_tod.year<MIN_YEAR)
{
rtc_tod.year+=100;
rtems_semaphore_obtain(semRTC, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
(pTimeFunc->SetTime)(&rtc_tod);
rtems_semaphore_release(semRTC);
}
rtc_tod.ticks=0;
rtems_clock_set( &rtc_tod );
}
void setRealTimeFromRTEMS()
{
rtems_time_of_day rtems_tod;
rtems_clock_get( RTEMS_CLOCK_GET_TOD, &rtems_tod );
rtems_semaphore_obtain(semRTC, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
(pTimeFunc->SetTime)(&rtems_tod);
rtems_semaphore_release(semRTC);
}
int checkRealTime()
{
return 0;
}

442
c/src/lib/libbsp/powerpc/ppcn_60x/universe/universe.c
View File

@@ -1,442 +0,0 @@
/*
* COPYRIGHT (c) 1998 by Radstone Technology
*
*
* THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
* KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
* AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
*
* You are hereby granted permission to use, copy, modify, and distribute
* this file, provided that this notice, plus the above copyright notice
* and disclaimer, appears in all copies. Radstone Technology will provide
* no support for this code.
*
* COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994, 1997.
* On-Line Applications Research Corporation (OAR).
*
* $Id$
*/
#include <rtems.h>
#include <assert.h>
#include <stdio.h>
#include <bsp.h>
#include <pci.h>
/********************************************************************
********************************************************************
********* *********
********* Prototypes *********
********* *********
********************************************************************
********************************************************************/
typedef struct {
uint32_t PCI_ID; /* Offset 0x0000 */
uint32_t PCI_CSR; /* Offset 0x0004 */
uint32_t PCI_CLASS; /* Offset 0x0008 */
uint32_t PCI_MISC0; /* Offset 0x000C */
uint32_t PCI_BS; /* Offset 0x0010 */
uint32_t Buf_Offset_0x0014[ 0x0A ]; /* Offset 0x0014 */
uint32_t PCI_MISC1; /* Offset 0x003C */
uint32_t Buf_Offset_0x0040[ 0x30 ]; /* Offset 0x0040 */
uint32_t LSI0_CTL; /* Offset 0x0100 */
uint32_t LSI0_BS; /* Offset 0x0104 */
uint32_t LSI0_BD; /* Offset 0x0108 */
uint32_t LSI0_TO; /* Offset 0x010C */
uint32_t Buf_Offset_0x0110; /* Offset 0x0110 */
uint32_t LSI1_CTL; /* Offset 0x0114 */
uint32_t LSI1_BS; /* Offset 0x0118 */
uint32_t LSI1_BD; /* Offset 0x011C */
uint32_t LSI1_TO; /* Offset 0x0120 */
uint32_t Buf_Offset_0x0124; /* Offset 0x0124 */
uint32_t LSI2_CTL; /* Offset 0x0128 */
uint32_t LSI2_BS; /* Offset 0x012C */
uint32_t LSI2_BD; /* Offset 0x0130 */
uint32_t LSI2_TO; /* Offset 0x0134 */
uint32_t Buf_Offset_0x0138; /* Offset 0x0138 */
uint32_t LSI3_CTL; /* Offset 0x013C */
uint32_t LSI3_BS; /* Offset 0x0140 */
uint32_t LSI3_BD; /* Offset 0x0144 */
uint32_t LSI3_TO; /* Offset 0x0148 */
uint32_t Buf_Offset_0x014C[ 0x09 ]; /* Offset 0x014C */
uint32_t SCYC_CTL; /* Offset 0x0170 */
uint32_t SCYC_ADDR; /* Offset 0x0174 */
uint32_t SCYC_EN; /* Offset 0x0178 */
uint32_t SCYC_CMP; /* Offset 0x017C */
uint32_t SCYC_SWP; /* Offset 0x0180 */
uint32_t LMISC; /* Offset 0x0184 */
uint32_t SLSI; /* Offset 0x0188 */
uint32_t L_CMDERR; /* Offset 0x018C */
uint32_t LAERR; /* Offset 0x0190 */
uint32_t Buf_Offset_0x0194[ 0x1B ]; /* Offset 0x0194 */
uint32_t DCTL; /* Offset 0x0200 */
uint32_t DTBC; /* Offset 0x0204 */
uint32_t DLA; /* Offset 0x0208 */
uint32_t Buf_Offset_0x020C; /* Offset 0x020C */
uint32_t DVA; /* Offset 0x0210 */
uint32_t Buf_Offset_0x0214; /* Offset 0x0214 */
uint32_t DCPP; /* Offset 0x0218 */
uint32_t Buf_Offset_0x021C; /* Offset 0x021C */
uint32_t DGCS; /* Offset 0x0220 */
uint32_t D_LLUE; /* Offset 0x0224 */
uint32_t Buf_Offset_0x0228[ 0x36 ]; /* Offset 0x0228 */
uint32_t LINT_EN; /* Offset 0x0300 */
uint32_t LINT_STAT; /* Offset 0x0304 */
uint32_t LINT_MAP0; /* Offset 0x0308 */
uint32_t LINT_MAP1; /* Offset 0x030C */
uint32_t VINT_EN; /* Offset 0x0310 */
uint32_t VINT_STAT; /* Offset 0x0314 */
uint32_t VINT_MAP0; /* Offset 0x0318 */
uint32_t VINT_MAP1; /* Offset 0x031C */
uint32_t STATID; /* Offset 0x0320 */
uint32_t V1_STATID; /* Offset 0x0324 */
uint32_t V2_STATID; /* Offset 0x0328 */
uint32_t V3_STATID; /* Offset 0x032C */
uint32_t V4_STATID; /* Offset 0x0330 */
uint32_t V5_STATID; /* Offset 0x0334 */
uint32_t V6_STATID; /* Offset 0x0338 */
uint32_t V7_STATID; /* Offset 0x033C */
uint32_t Buf_Offset_0x0340[ 0x30 ]; /* Offset 0x0340 */
uint32_t MAST_CTL; /* Offset 0x0400 */
uint32_t MISC_CTL; /* Offset 0x0404 */
uint32_t MISC_STAT; /* Offset 0x0408 */
uint32_t USER_AM; /* Offset 0x040C */
uint32_t Buf_Offset_0x0410[ 0x2bc ];/* Offset 0x0410 */
uint32_t VSI0_CTL; /* Offset 0x0F00 */
uint32_t VSI0_BS; /* Offset 0x0F04 */
uint32_t VSI0_BD; /* Offset 0x0F08 */
uint32_t VSI0_TO; /* Offset 0x0F0C */
uint32_t Buf_Offset_0x0f10; /* Offset 0x0F10 */
uint32_t VSI1_CTL; /* Offset 0x0F14 */
uint32_t VSI1_BS; /* Offset 0x0F18 */
uint32_t VSI1_BD; /* Offset 0x0F1C */
uint32_t VSI1_TO; /* Offset 0x0F20 */
uint32_t Buf_Offset_0x0F24; /* Offset 0x0F24 */
uint32_t VSI2_CTL; /* Offset 0x0F28 */
uint32_t VSI2_BS; /* Offset 0x0F2C */
uint32_t VSI2_BD; /* Offset 0x0F30 */
uint32_t VSI2_TO; /* Offset 0x0F34 */
uint32_t Buf_Offset_0x0F38; /* Offset 0x0F38 */
uint32_t VSI3_CTL; /* Offset 0x0F3C */
uint32_t VSI3_BS; /* Offset 0x0F40 */
uint32_t VSI3_BD; /* Offset 0x0F44 */
uint32_t VSI3_TO; /* Offset 0x0F48 */
uint32_t Buf_Offset_0x0F4C[ 0x9 ]; /* Offset 0x0F4C */
uint32_t VRAI_CTL; /* Offset 0x0F70 */
uint32_t VRAI_BS; /* Offset 0x0F74 */
uint32_t Buf_Offset_0x0F78[ 0x2 ]; /* Offset 0x0F78 */
uint32_t VCSR_CTL; /* Offset 0x0F80 */
uint32_t VCSR_TO; /* Offset 0x0F84 */
uint32_t V_AMERR; /* Offset 0x0F88 */
uint32_t VAERR; /* Offset 0x0F8C */
uint32_t Buf_Offset_0x0F90[ 0x19 ]; /* Offset 0x0F90 */
uint32_t VCSR_CLR; /* Offset 0x0FF4 */
uint32_t VCSR_SET; /* Offset 0x0FF8 */
uint32_t VCSR_BS; /* Offset 0x0FFC */
} Universe_Memory;
volatile Universe_Memory *UNIVERSE;
/*
* PCI_bus_write
*/
void PCI_bus_write(
volatile uint32_t * _addr, /* IN */
uint32_t _data /* IN */
)
{
outport_32(_addr, _data);
}
uint32_t PCI_bus_read(
volatile uint32_t * _addr /* IN */
)
{
uint32_t data;
inport_32(_addr, data);
return data;
}
/********************************************************************
********************************************************************
********* *********
********* *********
********* *********
********************************************************************
********************************************************************/
/*
* Initializes the UNIVERSE chip. This routine is called automatically
* by the boot code. This routine should be called by user code only if
* a complete PPCn_60x VME initialization is required.
*/
void InitializeUniverse()
{
uint32_t pci_id;
uint32_t universe_temp_value;
/*
* Verify the UNIVERSE CHIP ID
*/
(void)PCIConfigRead32(0,4,0,PCI_CONFIG_VENDOR_LOW, &pci_id);
/*
* compare to known ID
*/
if (pci_id != 0x000010e3 ){
DEBUG_puts ("Invalid PPCN_60X_UNIVERSE_CHIP_ID: ");
rtems_fatal_error_occurred( 0x603e0bad );
}
(void)PCIConfigRead32(0,4,0,PCI_CONFIG_BAR_0, &universe_temp_value);
UNIVERSE = (Universe_Memory *)(universe_temp_value & ~PCI_ADDRESS_IO_SPACE);
/*
* Set the UNIVERSE PCI Configuration Space Control and Status Register to
* medium speed device, Target Back to Back Capable, Master Enable, Target
* Memory Enable and Target IO Enable
*/
PCIConfigWrite32(0,4,0,PCI_CONFIG_COMMAND, PCI_ENABLE_IO_SPACE |
PCI_ENABLE_MEMORY_SPACE |
PCI_ENABLE_BUS_MASTER);
/*
* Turn off the sysfail by setting SYSFAIL bit to 1 on the VCSR_CLR register
*/
PCI_bus_write( &UNIVERSE->VCSR_CLR, 0x40000000 );
#if 0
/*
* Set VMEbus Slave Image 0 Base Address to 0x04000000 on VSI0_BS register.
*/
PCI_bus_write( &UNIVERSE->VSI0_BS, 0x04000000 );
/*
* Set VMEbus Slave Image 0 Bound Address to 0x05000000 on VSI0_BD register.
*/
PCI_bus_write( &UNIVERSE->VSI0_BD, 0x05000000 );
/*
* VMEbus Slave Image 0 Translation Offset to 0x7C000000 on VSI0_TO
* register. Map the VME base address 0x4000000 to local memory address 0x0
*/
PCI_bus_write( &UNIVERSE->VSI0_TO, 0x7C000000 );
/*
* Set the VMEbus Slave Image 0 Control register with write posted,
* read prefetch and AM code set for program, data, supervisor and user mode
*/
PCI_bus_write( &UNIVERSE->VSI0_CTL, 0xE0F20000 );
#endif
/*
* Set the VMEbus Master Control register with retry forever, 256 bytes
* posted write transfer count, VMEbus request level 3, RWD, PCI 32 bytes
* aligned burst size and PCI bus number to be zero
*/
PCI_bus_write( &UNIVERSE->MAST_CTL, 0x01C00000 );
/*
* VMEbus DMA Transfer Control register with 32 bit VMEbus Maximum Data
* width, A32 VMEbus Address Space, AM code to be data, none-privilleged,
* single and BLT cycles on VME bus and 64-bit PCI Bus Transactions enable
PCI_bus_write( &UNIVERSE->DCTL, 0x00820180 );
*/
PCI_bus_write( &UNIVERSE->LSI0_CTL, 0x80700040 );
PCI_bus_write( &UNIVERSE->LSI0_BS, 0x04000000 );
PCI_bus_write( &UNIVERSE->LSI0_BD, 0x05000000 );
PCI_bus_write( &UNIVERSE->LSI0_TO, 0x7C000000 );
#if 0
/*
* Set the PCI Slave Image 0 Control register with posted write enable,
* 32 bit data width, A32 VMEbus address base, AM code to be data,
* none-privilleged, single and BLT cycles on VME bus with PCI
* bus memory space.
PCI_bus_write( &UNIVERSE->LSI0_CTL, 0xC0820100 );
*/
PCI_bus_write( &UNIVERSE->LSI0_CTL, 0x80700040 );
/*
* Set the PCI Slave Image 0 Base Address to be
* 0x0 on LSI0_BS register.
*/
PCI_bus_write( &UNIVERSE->LSI0_BS, 0x00FF0000 );
/*
* Set the PCI Slave Image 0 Bound Address to be
* 0xFFFFF000 on VSI0_BD register.
*/
PCI_bus_write( &UNIVERSE->LSI0_BD, 0x00FFF000 );
/*
* Set the PCI Slave Image 0 Translation Offset to be
* 0x0 on VSI0_TO register.
* Note: If the actual VME address is bigger than 0x40000000, we need
* to set the PCI Slave Image 0 Translation Offset = 0x40000000
* register.
* i.e. if actual VME ADRR = 0x50000000, then we
* need to subtract it by 0x40000000 and set
* the LSI0_T0 register to be 0x40000000 and then
* perform a PCI data access by adding 0xC0000000 to
* 0x10000000 -- which is came form the result of
* (0x50000000 - 0x40000000).
*/
PCI_bus_write( &UNIVERSE->LSI0_TO, 0x0 );
#endif
/*
* Remove the Universe from VMEbus BI-Mode (bus-isolation). Once out of
* BI-Mode VMEbus accesses can be made.
*/
universe_temp_value = PCI_bus_read( &UNIVERSE->MISC_CTL );
if (universe_temp_value & 0x100000)
PCI_bus_write( &UNIVERSE->MISC_CTL,(universe_temp_value | ~0xFF0FFFFF));
}
/*
* Set the slave VME base address to the specified base address.
* Note: Lower 12 bits[11:0] will be masked out prior to setting the VMEbus
* Slave Image 0 registers.
*/
void set_vme_base_address (
uint32_t base_address
)
{
volatile uint32_t temp;
/*
* Calculate the current size of the Slave VME image 0
*/
temp = ( PCI_bus_read( &UNIVERSE->VSI0_BD) & 0xFFFFF000) -
( PCI_bus_read( &UNIVERSE->VSI0_BS) & 0xFFFFF000);
/*
* Set the VMEbus Slave Image 0 Base Address to be
* the specifed base address on VSI0_BS register.
*/
PCI_bus_write( &UNIVERSE->VSI0_BS, (base_address & 0xFFFFF000) );
/*
* Update the VMEbus Slave Image 0 Bound Address.
*/
PCI_bus_write( &UNIVERSE->VSI0_BD, temp );
/*
* Update the VMEbus Slave Image 0 Translation Offset
*/
temp = 0xFFFFFFFF - (base_address & 0xFFFFF000) + 1 + 0x80000000;
PCI_bus_write( &UNIVERSE->VSI0_TO, temp );
}
/*
* Gets the VME base address
*/
uint32_t get_vme_base_address ()
{
volatile uint32_t temp;
temp = PCI_bus_read( &UNIVERSE->VSI0_BS );
temp &= 0xFFFFF000;
return (temp);
}
uint32_t get_vme_slave_size()
{
volatile uint32_t temp;
temp = PCI_bus_read( &UNIVERSE->VSI0_BD);
temp &= 0xFFFFF000;
temp = temp - get_vme_base_address ();
return temp;
}
/*
* Set the size of the VME slave image
* Note: The maximum size is up to 24 M bytes. (00000000 - 017FFFFF)
*/
void set_vme_slave_size (uint32_t size)
{
volatile uint32_t temp;
if (size<0)
size = 0;
if (size > 0x17FFFFF)
size = 0x17FFFFF;
/*
* Read the VME slave image base address
*/
temp = get_vme_base_address ();
/*
* Update the VMEbus Slave Image 0 Bound Address.
*/
temp = temp + (size & 0xFFFFF000);
PCI_bus_write( &UNIVERSE->VSI0_BD, temp );
}
#if 0
/* XXXXX */
/*
* Returns the 16 bit location specified by vme_ptr, which must be a
* pointer to VME D16 space
*/
uint16_t get_vme(
uint16_t *vme_ptr
)
{
uint16_t result;
if (vme_ptr > (uint16_t*)0x3EFFFFFF)
{
/*
* LSI0_TO register to 0x3EFFF000 if it had not been updated already
*/
if (( PCI_bus_read( &UNIVERSE->LSI0_TO ) & 0xFFFFF000) != 0x3EFFF000)
PCI_bus_write( &UNIVERSE->LSI0_TO, 0x3EFFF000 );
result = (*(uint16_t*)(
((uint32_t)vme_ptr - 0x3EFFF000)+
PPCN_60X_PCI_MEM_BASE) );
}
else
result = (*(uint16_t*)
((uint32_t)vme_ptr+PPCN_60X_PCI_MEM_BASE));
return result;
}
/*
* Stores the 16 bit word at the location specified by vme_ptr, which must
* be a pointer to VME D16 space
*/
void put_vme(
uint16_t *vme_ptr,
uint16_t value
)
{
if (vme_ptr > (uint16_t*)0x3EFFFFFF) {
/*
* LSI0_TO register to 0x3EFFF000 if it had not been updated already
*/
if (( PCI_bus_read( &UNIVERSE->LSI0_TO) & 0xFFFFF000) != 0x3EFFF000)
PCI_bus_write( &UNIVERSE->LSI0_TO, 0x3EFFF000 );
*(uint16_t*) (((uint32_t)vme_ptr - 0x3EFFF000) +
PPCN_60X_PCI_MEM_BASE) = value;
}
else
*(uint16_t*)((uint32_t)vme_ptr +
PPCN_60X_PCI_MEM_BASE) = value;
}
#endif

25
c/src/lib/libbsp/powerpc/ppcn_60x/vectors/README
View File

@@ -1,25 +0,0 @@
#
# $Id$
#
The location of the vectors file object is critical.
From the comments at the head of vectors.s:
The issue with this file is getting it loaded at the right place.
The first vector MUST be at address 0x????0100.
How this is achieved is dependant on the tool chain.
However the basic mechanism for ELF assemblers is to create a
section called ".vectors", which will be loaded to an address
between 0x????0000 and 0x????0100 (inclusive) via a link script.
The basic mechanism for XCOFF assemblers is to place it in the
normal text section, and arrange for this file to be located
at an appropriate position on the linker command line.
The variable 'PPC_VECTOR_FILE_BASE' must be defined to be the
offset from 0x????0000 to the first location in the file. This
will usually be 0x0000 or 0x0100.
Andrew Bray 18/8/1995

433
c/src/lib/libbsp/powerpc/ppcn_60x/vectors/align_h.S
View File

@@ -1,433 +0,0 @@
/* align_h.s 1.1 - 95/12/04
*
* This file contains the assembly code for the PowerPC 403
* alignment exception handler for RTEMS.
*
* Based upon IBM provided code with the following release:
*
* This source code has been made available to you by IBM on an AS-IS
* basis. Anyone receiving this source is licensed under IBM
* copyrights to use it in any way he or she deems fit, including
* copying it, modifying it, compiling it, and redistributing it either
* with or without modifications. No license under IBM patents or
* patent applications is to be implied by the copyright license.
*
* Any user of this software should understand that IBM cannot provide
* technical support for this software and will not be responsible for
* any consequences resulting from the use of this software.
*
* Any person who transfers this source code or any derivative work
* must include the IBM copyright notice, this paragraph, and the
* preceding two paragraphs in the transferred software.
*
* COPYRIGHT I B M CORPORATION 1995
* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
*
* Modifications:
*
* Author: Andrew Bray <andy@i-cubed.co.uk>
*
* COPYRIGHT (c) 1995 by i-cubed ltd.
*
* To anyone who acknowledges that this file is provided "AS IS"
* without any express or implied warranty:
* permission to use, copy, modify, and distribute this file
* for any purpose is hereby granted without fee, provided that
* the above copyright notice and this notice appears in all
* copies, and that the name of i-cubed limited not be used in
* advertising or publicity pertaining to distribution of the
* software without specific, written prior permission.
* i-cubed limited makes no representations about the suitability
* of this software for any purpose.
*
* $Id$
*/
#include <rtems/asm.h>
#include "bsp.h"
.set CACHE_SIZE,16 # cache line size of 32 bytes
.set CACHE_SIZE_L2,4 # cache line size, log 2
.set Open_gpr0,0
.set Open_gpr1,4
.set Open_gpr2,8
.set Open_gpr3,12
.set Open_gpr4,16
.set Open_gpr5,20
.set Open_gpr6,24
.set Open_gpr7,28
.set Open_gpr8,32
.set Open_gpr9,36
.set Open_gpr10,40
.set Open_gpr11,44
.set Open_gpr12,48
.set Open_gpr13,52
.set Open_gpr14,56
.set Open_gpr15,60
.set Open_gpr16,64
.set Open_gpr17,68
.set Open_gpr18,72
.set Open_gpr19,76
.set Open_gpr20,80
.set Open_gpr21,84
.set Open_gpr22,88
.set Open_gpr23,92
.set Open_gpr24,96
.set Open_gpr25,100
.set Open_gpr26,104
.set Open_gpr27,108
.set Open_gpr28,112
.set Open_gpr29,116
.set Open_gpr30,120
.set Open_gpr31,124
.set Open_xer,128
.set Open_lr,132
.set Open_ctr,136
.set Open_cr,140
.set Open_srr2,144
.set Open_srr3,148
.set Open_srr0,152
.set Open_srr1,156
/*
* This code makes several assumptions for processing efficiency
* * General purpose registers are continuous in the image, beginning with
* Open_gpr0
* * Hash table is highly dependent on opcodes - opcode changes *will*
* require rework of the instruction decode mechanism.
*/
.text
.globl align_h
.align CACHE_SIZE_L2
align_h:
/*-----------------------------------------------------------------------
* Store GPRs in Open Reg save area
* Set up r2 as base reg, r1 pointing to Open Reg save area
*----------------------------------------------------------------------*/
stmw r0,ALIGN_REGS(r0)
li r1,ALIGN_REGS
/*-----------------------------------------------------------------------
* Store special purpose registers in reg save area
*----------------------------------------------------------------------*/
mfxer r7
mflr r8
mfcr r9
mfctr r10
stw r7,Open_xer(r1)
stw r8,Open_lr(r1)
stw r9,Open_cr(r1)
stw r10,Open_ctr(r1)
mfspr r7, srr2 /* SRR 2 */
mfspr r8, srr3 /* SRR 3 */
mfspr r9, srr0 /* SRR 0 */
mfspr r10, srr1 /* SRR 1 */
stw r7,Open_srr2(r1)
stw r8,Open_srr3(r1)
stw r9,Open_srr0(r1)
stw r10,Open_srr1(r1)
/* Set up common registers */
mfspr r5, dear /* DEAR: R5 is data exception address */
lwz r9,Open_srr0(r1) /* get faulting instruction */
addi r7,r9,4 /* bump instruction */
stw r7,Open_srr0(r1) /* restore to image */
lwz r9, 0(r9) /* retrieve actual instruction */
rlwinm r6,r9,18,25,29 /* r6 is RA * 4 field from instruction */
rlwinm r7,r9,6,26,31 /* r7 is primary opcode */
bl ref_point /* establish addressibility */
ref_point:
mflr r11 /* r11 is the anchor point for ref_point */
addi r10, r7, -31 /* r10 = r7 - 31 */
rlwinm r10,r10,2,2,31 /* r10 *= 4 */
add r10, r10, r11 /* r10 += anchor point */
lwz r10, primary_jt-ref_point(r10)
mtlr r10
rlwinm r8,r9,13,25,29 /* r8 is RD * 4 */
la r7,Open_gpr0(r1) /* r7 is address of GPR 0 in list */
blr
primary_jt:
.long xform
.long lwz
.long lwzu
.long 0
.long 0
.long stw
.long stwu
.long 0
.long 0
.long lhz
.long lhzu
.long lha
.long lhau
.long sth
.long sthu
.long lmw
.long stmw
/*
* handlers
*/
/*
* xform instructions require an additional decode. Fortunately, a relatively
* simple hash step breaks the instructions out with no collisions
*/
xform:
rlwinm r7,r9,31,22,31 /* r7 is secondary opcode */
rlwinm r10,r7,27,5,31 /* r10 = r7 >> 5 */
add r10,r7,r10 /* r10 = r7 + r10 */
rlwinm r10,r10,2,25,29 /* r10 = (r10 & 0x1F) * 4 */
add r10,r10,r11 /* r10 += anchor point */
lwz r10, secondary_ht-ref_point(r10)
mtlr r10
la r7,Open_gpr0(r1) /* r7 is address of GPR 0 in list */
rlwinm r8,r9,13,25,29 /* r8 is RD * 4 */
blrl
secondary_ht:
.long lhzux /* b 0 0x137 */
.long lhax /* b 1 0x157 */
.long lhaux /* b 2 0x177 */
.long sthx /* b 3 0x197 */
.long sthux /* b 4 0x1b7 */
.long 0 /* b 5 */
.long lwbrx /* b 6 0x216 */
.long 0 /* b 7 */
.long 0 /* b 8 */
.long 0 /* b 9 */
.long stwbrx /* b A 0x296 */
.long 0 /* b B */
.long 0 /* b C */
.long 0 /* b D */
.long lhbrx /* b E 0x316 */
.long 0 /* b F */
.long 0 /* b 10 */
.long 0 /* b 11 */
.long sthbrx /* b 12 0x396 */
.long 0 /* b 13 */
.long lwarx /* b 14 0x014 */
.long dcbz /* b 15 0x3f6 */
.long 0 /* b 16 */
.long lwzx /* b 17 0x017 */
.long lwzux /* b 18 0x037 */
.long 0 /* b 19 */
.long stwcx /* b 1A 0x096 */
.long stwx /* b 1B 0x097 */
.long stwux /* b 1C 0x0B7 */
.long 0 /* b 1D */
.long 0 /* b 1E */
.long lhzx /* b 1F 0x117 */
/*
* for all handlers
* r4 - Addressability to interrupt context
* r5 - DEAR address (faulting data address)
* r6 - RA field * 4
* r7 - Address of GPR 0 in image
* r8 - RD field * 4
* r9 - Failing instruction
*/
/* Load halfword algebraic with update */
lhau:
/* Load halfword algebraic with update indexed */
lhaux:
stwx r5,r7,r6 /* update RA with effective addr */
/* Load halfword algebraic */
lha:
/* Load halfword algebraic indexed */
lhax:
lswi r10,r5,2 /* load two bytes into r10 */
srawi r10,r10,16 /* shift right 2 bytes, extending sign */
stwx r10,r7,r8 /* update reg image */
b align_complete /* return */
/* Load Half Word Byte-Reversed Indexed */
lhbrx:
lswi r10,r5,2 /* load two bytes from DEAR into r10 */
rlwinm r10,r10,0,0,15 /* mask off lower 2 bytes */
stwbrx r10,r7,r8 /* store reversed in reg image */
b align_complete /* return */
/* Load Half Word and Zero with Update */
lhzu:
/* Load Half Word and Zero with Update Indexed */
lhzux:
stwx r5,r7,r6 /* update RA with effective addr */
/* Load Half Word and Zero */
lhz:
/* Load Half Word and Zero Indexed */
lhzx:
lswi r10,r5,2 /* load two bytes from DEAR into r10 */
rlwinm r10,r10,16,16,31 /* shift right 2 bytes, with zero fill */
stwx r10,r7,r8 /* update reg image */
b align_complete /* return */
/*
* Load Multiple Word
*/
lmw:
lwzx r9,r6,r7 /* R9 contains saved value of RA */
addi r10,r7,32*4 /* r10 points to r31 in image + 4 */
rlwinm r8,r8,30,2,31 /* r8 >>= 2 (recovers RT) */
subfic r8,r8,32 /* r8 is reg count to load */
mtctr r8 /* load counter */
addi r8,r8,-1 /* r8-- */
rlwinm r8,r8,2,2,31 /* r8 *= 4 */
add r5,r5,r8 /* update DEAR to point to last reg */
lwmloop:
lswi r11,r5,4 /* load r11 with 4 bytes from DEAR */
stwu r11,-4(r10) /* load image and decrement pointer */
addi r5,r5,-4 /* decrement effective address */
bdnz lwmloop
stwx r9,r6,r7 /* restore RA (in case it was trashed) */
b align_complete /* return */
/*
* Load Word and Reserve Indexed
*/
lwarx:
lswi r10,r5,4 /* load four bytes from DEAR into r10 */
stwx r10,r7,r8 /* update reg image */
rlwinm r5,r5,0,0,29 /* Word align address */
lwarx r10,0,r5 /* Set reservation */
b align_complete /* return */
/*
* Load Word Byte-Reversed Indexed
*/
lwbrx:
lswi r10,r5,4 /* load four bytes from DEAR into r10 */
stwbrx r10,r7,r8 /* store reversed in reg image */
b align_complete /* return */
/* Load Word and Zero with Update */
lwzu:
/* Load Word and Zero with Update Indexed */
lwzux:
stwx r5,r7,r6 /* update RA with effective addr */
/* Load Word and Zero */
lwz:
/* Load Word and Zero Indexed */
lwzx:
lswi r10,r5,4 /* load four bytes from DEAR into r10 */
stwx r10,r7,r8 /* update reg image */
b align_complete /* return */
/* Store instructions */
/* */
/* Store Half Word and Update */
sthu:
/* Store Half Word and Update Indexed */
sthux:
stwx r5,r7,r6 /* Update RA with effective address */
/* Store Half Word */
sth:
/* Store Half Word Indexed */
sthx:
lwzx r10,r8,r7 /* retrieve source register value */
rlwinm r10,r10,16,0,15 /* move two bytes to high end of reg */
stswi r10,r5,2 /* store bytes to DEAR address */
b align_complete /* return */
/* */
/* Store Half Word Byte-Reversed Indexed */
sthbrx:
lwbrx r10,r8,r7 /* retrieve src reg value byte reversed */
stswi r10,r5,2 /* move two bytes to DEAR address */
b align_complete /* return */
/* */
/* Store Multiple Word */
stmw:
addi r10,r7,32*4 /* r10 points to r31 in image + 4 */
rlwinm r8,r8,30,2,31 /* r8 >>= 2 (recovers RT) */
subfic r8,r8,32 /* r8 is reg count to load */
mtctr r8 /* load counter */
addi r8,r8,-1 /* r8-- */
rlwinm r8,r8,2,2,31 /* r8 *= 4 */
add r5,r5,r8 /* update DEAR to point to last reg */
stmloop:
lwzu r11,-4(r10) /* get register value */
stswi r11,r5,4 /* output to DEAR address */
addi r5,r5,-4 /* decrement effective address */
bdnz stmloop
b align_complete /* return */
/* */
/* Store Word and Update */
stwu:
/* Store Word and Update Indexed */
stwux:
stwx r5,r7,r6 /* Update RA with effective address */
/* Store Word */
stw:
/* Store Word Indexed */
stwx:
lwzx r10,r8,r7 /* retrieve source register value */
stswi r10,r5,4 /* store bytes to DEAR address */
b align_complete /* return */
/* */
/* Store Word Byte-Reversed Indexed */
stwbrx:
lwbrx r10,r8,r7 /* retrieve src reg value byte reversed */
stswi r10,r5,4 /* move two bytes to DEAR address */
b align_complete /* return */
/* */
/* Store Word Conditional Indexed */
stwcx:
rlwinm r10,r5,0,0,29 /* r10 = word aligned DEAR */
lwz r11,0(r10) /* save original value of store */
stwcx. r11,r0,r10 /* attempt store to address */
bne stwcx_moveon /* store failed, move on */
stw r11,0(r10) /* repair damage */
lwzx r9,r7,r8 /* get register value */
stswi r10,r5,4 /* store bytes to DEAR address */
stwcx_moveon:
mfcr r11 /* get condition reg */
lwz r9,Open_cr(r1) /* get condition reg image */
rlwimi r9,r11,0,0,2 /* insert 3 CR bits into cr image */
lwz r11,Open_xer(r1) /* get XER reg */
rlwimi r9,r11,29,2,2 /* insert XER SO bit into cr image */
stw r9,Open_cr(r1) /* store cr image */
b align_complete /* return */
/* */
/* Data Cache Block Zero */
dcbz:
rlwinm r5,r5,0,0,31-CACHE_SIZE_L2
/* get address to nearest Cache line */
addi r5,r5,-4 /* adjust by a word */
addi r10,r0,CACHE_SIZE/4 /* set counter value */
mtctr r10
addi r11,r0,0 /* r11 = 0 */
dcbz_loop:
stwu r11,4(r5) /* store a word and update EA */
bdnz dcbz_loop
b align_complete /* return */
align_complete:
/*-----------------------------------------------------------------------
* Restore regs and return from the interrupt
*----------------------------------------------------------------------*/
lmw r24,Open_xer+ALIGN_REGS(r0)
mtxer r24
mtlr r25
mtctr r26
mtcrf 0xFF, r27
mtspr srr2, r28 /* SRR 2 */
mtspr srr3, r29 /* SRR 3 */
mtspr srr0, r30 /* SRR 0 */
mtspr srr1, r31 /* SRR 1 */
lmw r1,Open_gpr1+ALIGN_REGS(r0)
lwz r0,Open_gpr0+ALIGN_REGS(r0)
rfi

291
c/src/lib/libbsp/powerpc/ppcn_60x/vectors/vectors.S
View File

@@ -1,291 +0,0 @@
/*
* (c) 1998, Radstone Technology plc.
*
*
* This is an unpublished work the copyright in which vests
* in Radstone Technology plc. All rights reserved.
*
* The information contained herein is the property of Radstone
* Technology plc. and is supplied without liability for
* errors or omissions and no part may be reproduced, used or
* disclosed except as authorized by contract or other written
* permission. The copyright and the foregoing
* restriction on reproduction, use and disclosure extend to
* all the media in which this information may be
* embodied.
*
*/
/* vectors.s 1.1 - 95/12/04
*
* This file contains the assembly code for the PowerPC
* interrupt veneers for RTEMS.
*
*/
/*
* The issue with this file is getting it loaded at the right place.
* The first vector MUST be at address 0x????0100.
* How this is achieved is dependant on the tool chain.
*
* However the basic mechanism for ELF assemblers is to create a
* section called ".vectors", which will be loaded to an address
* between 0x????0000 and 0x????0100 (inclusive) via a link script.
*
* The basic mechanism for XCOFF assemblers is to place it in the
* normal text section, and arrange for this file to be located
* at an appropriate position on the linker command line.
*
* The variable 'PPC_VECTOR_FILE_BASE' must be defined to be the
* offset from 0x????0000 to the first location in the file. This
* will usually be 0x0000 or 0x0100.
*
* $Id$
*/
#include <rtems/asm.h>
#include "bsp.h"
#ifndef PPC_VECTOR_FILE_BASE
#error "PPC_VECTOR_FILE_BASE is not defined."
#endif
.set IP_LINK, 0
/* PPC_ABI_EABI */
.set IP_0, (IP_LINK + 8)
.set IP_2, (IP_0 + 4)
.set IP_3, (IP_2 + 4)
.set IP_4, (IP_3 + 4)
.set IP_5, (IP_4 + 4)
.set IP_6, (IP_5 + 4)
.set IP_7, (IP_6 + 4)
.set IP_8, (IP_7 + 4)
.set IP_9, (IP_8 + 4)
.set IP_10, (IP_9 + 4)
.set IP_11, (IP_10 + 4)
.set IP_12, (IP_11 + 4)
.set IP_13, (IP_12 + 4)
.set IP_28, (IP_13 + 4)
.set IP_29, (IP_28 + 4)
.set IP_30, (IP_29 + 4)
.set IP_31, (IP_30 + 4)
.set IP_CR, (IP_31 + 4)
.set IP_CTR, (IP_CR + 4)
.set IP_XER, (IP_CTR + 4)
.set IP_LR, (IP_XER + 4)
.set IP_PC, (IP_LR + 4)
.set IP_MSR, (IP_PC + 4)
.set IP_END, (IP_MSR + 16)
/* Where this file will be loaded */
.set file_base, PPC_VECTOR_FILE_BASE
/* Vector offsets */
.set reset_vector,0x0100
.set mach_vector,0x0200
.set prot_vector,0x0300
.set isi_vector,0x0400
.set ext_vector,0x0500
.set align_vector,0x0600
.set prog_vector,0x0700
.set float_vector,0x0800
.set dec_vector,0x0900
.set sys_vector,0x00C00
.set trace_vector, 0x0d00
.set itm_vector,0x01000
.set dltm_vector,0x1100
.set dstm_vector,0x1200
.set addr_vector,0x1300
.set sysmgmt_vector,0x1400
/* Go to the right section */
#if PPC_ASM == PPC_ASM_ELF
.section .vectors,"awx",@progbits
#endif
PUBLIC_VAR (__vectors)
SYM (__vectors):
#if PPCN_60X_USE_DINK
.org reset_vector - file_base
/* This is where the DINK soft reset handler is located */
ba 0xfff00180
.org mach_vector - file_base
ba 0xfff00200
.org prot_vector - file_base
ba 0xfff00300
.org isi_vector - file_base
ba 0xfff00400
.org ext_vector - file_base
rfi
.org align_vector - file_base
ba 0xfff00600
.org prog_vector - file_base
ba 0xfff00700
.org float_vector - file_base
ba 0xfff00800
.org dec_vector - file_base
rfi
.org sys_vector - file_base
ba 0xfff00C00
.org trace_vector - file_base
ba 0xfff00d00
.org itm_vector - file_base
ba 0xfff01000
.org dltm_vector - file_base
ba 0xfff01100
.org dstm_vector - file_base
ba 0xfff01200
.org addr_vector - file_base
ba 0xfff01300
.org sysmgmt_vector - file_base
ba 0xfff01400
#else
.org reset_vector - file_base
stwu r1, -(IP_END)(r1)
stw r4,IP_4(r1)
li r4,1
display_exc:
stw r3,IP_3(r1)
stw r5,IP_5(r1)
/*
* Enable data and instruction address translation
*/
li r3,MSR_IR | MSR_DR
mtmsr r3
lis r3,0x8000
stb r4,0x860(r3)
addi r4,r4,0x30
waitfortx:
lbz r5,0x3fd(r3)
andi. r5,r5,0x20
beq waitfortx
stb r4,0x3f8(r3)
li r5,0
stw r4,0x00(r5)
mfsrr0 r4
stw r4,0x04(r5)
mfsrr1 r4
stw r4,0x08(r5)
lwz r4,IP_4(r1)
lwz r5,IP_5(r1)
lwz r3,IP_3(r1)
addi r1,r1,IP_END
rfi
.org mach_vector - file_base
stwu r1, -(IP_END)(r1)
stw r4,IP_4(r1)
stw r3,IP_3(r1)
lis r4,0
mfspr r3,srr0
stw r3,0x00(r4)
mfspr r3,srr1
stw r3,0x04(r4)
stw r5,0x08(r4)
stw r2,0x0c(r4)
stw r11,0x10(r4)
stw r12,0x14(r4)
dcbst 0,r4
li r4,0x02
b display_exc
.org prot_vector - file_base
stwu r1, -(IP_END)(r1)
stw r4,IP_4(r1)
li r4,0x03
b display_exc
.org isi_vector - file_base
stwu r1, -(IP_END)(r1)
stw r4,IP_4(r1)
li r4,0x04
b display_exc
.org ext_vector - file_base
rfi
.org align_vector - file_base
stwu r1, -(IP_END)(r1)
stw r4,IP_4(r1)
li r4,0x06
b display_exc
.org prog_vector - file_base
stwu r1, -(IP_END)(r1)
stw r4,IP_4(r1)
li r4,0x07
b display_exc
.org float_vector - file_base
stwu r1, -(IP_END)(r1)
stw r4,IP_4(r1)
li r4,0x08
b display_exc
.org dec_vector - file_base
rfi
.org sys_vector - file_base
stwu r1, -(IP_END)(r1)
stw r4,IP_4(r1)
li r4,0x0a
b display_exc
.org trace_vector - file_base
stwu r1, -(IP_END)(r1)
stw r4,IP_4(r1)
li r4,0x0b
b display_exc
.org itm_vector - file_base
stwu r1, -(IP_END)(r1)
stw r4,IP_4(r1)
li r4,0x0c
b display_exc
.org dltm_vector - file_base
stwu r1, -(IP_END)(r1)
stw r4,IP_4(r1)
li r4,0x0d
b display_exc
.org dstm_vector - file_base
stwu r1, -(IP_END)(r1)
stw r4,IP_4(r1)
li r4,0x0e
b display_exc
.org addr_vector - file_base
stwu r1, -(IP_END)(r1)
stw r4,IP_4(r1)
li r4,0x0f
b display_exc
.org sysmgmt_vector - file_base
stwu r1, -(IP_END)(r1)
stw r4,IP_4(r1)
li r4,0x00
b display_exc
#endif