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https://gitlab.rtems.org/rtems/rtos/rtems.git
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2008-07-21 Till Straumann <strauman@slac.stanford.edu>
* new-exceptions/raw_exception,h, new-exceptions/raw_exception.c: Added more vectors for PPC405: watchdog, fpu-unavail, apu-unavail, itlbmiss, dtlbmiss, debug.
This commit is contained in:
@@ -1,3 +1,9 @@
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2008-07-21 Till Straumann <strauman@slac.stanford.edu>
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* new-exceptions/raw_exception,h,
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new-exceptions/raw_exception.c: Added more vectors for PPC405:
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watchdog, fpu-unavail, apu-unavail, itlbmiss, dtlbmiss, debug.
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2008-07-18 Sebastian Huber <sebastian.huber@embedded-brains.de>
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2008-07-18 Sebastian Huber <sebastian.huber@embedded-brains.de>
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* shared/include/powerpc-utility.h: Changed special purpose register
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* shared/include/powerpc-utility.h: Changed special purpose register
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@@ -79,23 +79,37 @@ void* ppc_get_vector_addr(rtems_vector vector)
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vaddr = ASM_60X_VEC_VECTOR_OFFSET;
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vaddr = ASM_60X_VEC_VECTOR_OFFSET;
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break;
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break;
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case ASM_BOOKE_FIT_VECTOR:
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#ifndef ASM_BOOKE_FIT_VECTOR_OFFSET
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#define ASM_BOOKE_FIT_VECTOR_OFFSET 0x1010
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#endif
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if ( PPC_405 == current_ppc_cpu )
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vaddr = ASM_BOOKE_FIT_VECTOR_OFFSET;
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break;
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case ASM_BOOKE_WDOG_VECTOR:
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#ifndef ASM_BOOKE_WDOG_VECTOR_OFFSET
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#define ASM_BOOKE_WDOG_VECTOR_OFFSET 0x1020
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#endif
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if ( PPC_405 == current_ppc_cpu )
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vaddr = ASM_BOOKE_WDOG_VECTOR_OFFSET;
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break;
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default:
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default:
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break;
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break;
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}
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}
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if ( PPC_405 == current_ppc_cpu ) {
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switch ( vector ) {
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case ASM_BOOKE_FIT_VECTOR:
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#ifndef ASM_PPC405_FIT_VECTOR_OFFSET
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#define ASM_PPC405_FIT_VECTOR_OFFSET 0x1010
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#endif
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vaddr = ASM_PPC405_FIT_VECTOR_OFFSET;
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break;
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case ASM_BOOKE_WDOG_VECTOR:
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#ifndef ASM_PPC405_WDOG_VECTOR_OFFSET
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#define ASM_PPC405_WDOG_VECTOR_OFFSET 0x1020
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#endif
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vaddr = ASM_PPC405_WDOG_VECTOR_OFFSET;
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break;
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case ASM_TRACE_VECTOR:
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#ifndef ASM_PPC405_TRACE_VECTOR_OFFSET
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#define ASM_PPC405_TRACE_VECTOR_OFFSET 0x2000
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#endif
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vaddr = ASM_PPC405_TRACE_VECTOR_OFFSET;
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break;
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case ASM_PPC405_APU_UNAVAIL_VECTOR:
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vaddr = ASM_60X_VEC_VECTOR_OFFSET;
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default:
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break;
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}
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}
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if (bsp_exceptions_in_RAM) {
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if (bsp_exceptions_in_RAM) {
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if (ppc_cpu_has_ivpr_and_ivor()) {
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if (ppc_cpu_has_ivpr_and_ivor()) {
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return ((void*) ((vaddr >> 4) + ppc_exc_vector_base));
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return ((void*) ((vaddr >> 4) + ppc_exc_vector_base));
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@@ -161,20 +175,27 @@ static const cat_ini_t mpc_5xx_vector_categories[LAST_VALID_EXC + 1] = {
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};
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};
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static const cat_ini_t ppc_405_vector_categories[LAST_VALID_EXC + 1] = {
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static const cat_ini_t ppc_405_vector_categories[LAST_VALID_EXC + 1] = {
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[ ASM_EXT_VECTOR ] = PPC_EXC_CLASSIC | PPC_EXC_ASYNC,
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[ ASM_BOOKE_DEC_VECTOR ] = PPC_EXC_CLASSIC | PPC_EXC_ASYNC, /* PIT */
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[ ASM_BOOKE_FIT_VECTOR ] = PPC_EXC_CLASSIC | PPC_EXC_ASYNC, /* FIT */
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[ ASM_PROT_VECTOR ] = PPC_EXC_CLASSIC,
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[ ASM_ISI_VECTOR ] = PPC_EXC_CLASSIC,
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[ ASM_ALIGN_VECTOR ] = PPC_EXC_CLASSIC,
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[ ASM_PROG_VECTOR ] = PPC_EXC_CLASSIC,
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[ ASM_SYS_VECTOR ] = PPC_EXC_CLASSIC,
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[ ASM_BOOKE_ITLBMISS_VECTOR ] = PPC_EXC_CLASSIC,
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[ ASM_BOOKE_DTLBMISS_VECTOR ] = PPC_EXC_CLASSIC,
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[ ASM_BOOKE_CRIT_VECTOR ] = PPC_EXC_405_CRITICAL | PPC_EXC_ASYNC,
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[ ASM_BOOKE_CRIT_VECTOR ] = PPC_EXC_405_CRITICAL | PPC_EXC_ASYNC,
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[ ASM_MACH_VECTOR ] = PPC_EXC_405_CRITICAL,
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[ ASM_MACH_VECTOR ] = PPC_EXC_405_CRITICAL,
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[ ASM_PROT_VECTOR ] = PPC_EXC_CLASSIC,
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[ ASM_ISI_VECTOR ] = PPC_EXC_CLASSIC,
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[ ASM_EXT_VECTOR ] = PPC_EXC_CLASSIC | PPC_EXC_ASYNC,
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[ ASM_ALIGN_VECTOR ] = PPC_EXC_CLASSIC,
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[ ASM_PROG_VECTOR ] = PPC_EXC_CLASSIC,
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[ ASM_FLOAT_VECTOR ] = PPC_EXC_CLASSIC,
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[ ASM_PPC405_APU_UNAVAIL_VECTOR] = PPC_EXC_CLASSIC,
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[ ASM_SYS_VECTOR ] = PPC_EXC_CLASSIC,
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[ ASM_BOOKE_DEC_VECTOR ] = PPC_EXC_CLASSIC | PPC_EXC_ASYNC, /* PIT */
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[ ASM_BOOKE_FIT_VECTOR ] = PPC_EXC_CLASSIC | PPC_EXC_ASYNC, /* FIT */
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[ ASM_BOOKE_WDOG_VECTOR ] = PPC_EXC_405_CRITICAL | PPC_EXC_ASYNC,
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[ ASM_BOOKE_DTLBMISS_VECTOR ] = PPC_EXC_CLASSIC,
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[ ASM_BOOKE_ITLBMISS_VECTOR ] = PPC_EXC_CLASSIC,
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[ ASM_TRACE_VECTOR ] = PPC_EXC_405_CRITICAL,
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};
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};
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@@ -58,6 +58,8 @@
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#define ASM_BOOKE_FIT_VECTOR 0x13
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#define ASM_BOOKE_FIT_VECTOR 0x13
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#define ASM_BOOKE_WDOG_VECTOR 0x14
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#define ASM_BOOKE_WDOG_VECTOR 0x14
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#define ASM_PPC405_APU_UNAVAIL_VECTOR ASM_60X_VEC_ASSIST_VECTOR
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#define ASM_8XX_FLOATASSIST_VECTOR 0x0E
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#define ASM_8XX_FLOATASSIST_VECTOR 0x0E
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#define ASM_8XX_SOFTEMUL_VECTOR 0x10
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#define ASM_8XX_SOFTEMUL_VECTOR 0x10
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#define ASM_8XX_ITLBMISS_VECTOR 0x11
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#define ASM_8XX_ITLBMISS_VECTOR 0x11
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