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2002-07-30 Joel Sherrill <joel@OARcorp.com>

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* intr_NOTIMES.t, timeBSP.t: Replaced XXX's with real info.
This commit is contained in:
Joel Sherrill
2002-07-31 00:17:12 +00:00
parent 52c5689ecd
commit 0b93b97856
9 changed files with 51 additions and 27 deletions
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20
doc/supplements/sh/timeBSP.t
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@@ -15,19 +15,20 @@
@section Introduction
The timing data for the XXX version of RTEMS is
The timing data for the SH version of RTEMS is
provided along with the target dependent aspects concerning the
gathering of the timing data. The hardware platform used to
gather the times is described to give the reader a better
understanding of each directive time provided. Also, provided
is a description of the interrupt latency and the context switch
times as they pertain to the XXX version of RTEMS.
times as they pertain to the SH version of RTEMS.
@section Hardware Platform
All times reported except for the maximum period
interrupts are disabled by RTEMS were measured using a Motorola
BSP_FOR_TIMES CPU board. The BSP_FOR_TIMES is a 20Mhz board with one wait
BSP_FOR_TIMES CPU board. The BSP_FOR_TIMES is a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
Mhz board with one wait
state dynamic memory and a XXX numeric coprocessor. The
Zilog 8036 countdown timer on this board was used to measure
elapsed time with a one-half microsecond resolution. All
@@ -41,9 +42,10 @@ disabled. The worst case times of the XXX microprocessor
were used for each instruction. Zero wait state memory was
assumed. The total CPU cycles executed with interrupts
disabled, including the instructions to disable and enable
interrupts, was divided by 20 to simulate a 20Mhz XXX. It
interrupts, was divided by 20 to simulate a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
Mhz processor. It
should be noted that the worst case instruction times for the
XXX assume that the internal cache is disabled and that no
processor assume that the internal cache is disabled and that no
instructions overlap.
@section Interrupt Latency
@@ -52,20 +54,22 @@ The maximum period with interrupts disabled within
RTEMS is less than RTEMS_MAXIMUM_DISABLE_PERIOD
microseconds including the instructions
which disable and re-enable interrupts. The time required for
the XXX to vector an interrupt and for the RTEMS entry
the processor to vector an interrupt and for the RTEMS entry
overhead before invoking the user's interrupt handler are a
total of RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK
microseconds. These combine to yield a worst case
interrupt latency of less than
RTEMS_MAXIMUM_DISABLE_PERIOD + RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK
microseconds at 20Mhz. [NOTE: The maximum period with interrupts
microseconds at RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
Mhz. [NOTE: The maximum period with interrupts
disabled was last determined for Release
RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.]
It should be noted again that the maximum period with
interrupts disabled within RTEMS is hand-timed and based upon
worst case (i.e. CPU cache disabled and no instruction overlap)
times for a 20Mhz XXX. The interrupt vector and entry
times for a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
Mhz processor. The interrupt vector and entry
overhead time was generated on an BSP_FOR_TIMES benchmark platform
using the Multiprocessing Communications registers to generate
as the interrupt source.