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Remove rtems_cache_*_processor_set() functions

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The following rtems_cache_*_processor_set() cache manager API functions
are exotic, complex, very hard to use correctly, not used in the RTEMS
code base, and apparently unused by applications.

Close #3622.
This commit is contained in:
Sebastian Huber
2018-11-26 14:04:59 +01:00
parent 6378978940
commit 0a75a4aa65
3 changed files with 7 additions and 215 deletions
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91
bsps/shared/cache/cacheimpl.h vendored
View File

@@ -49,97 +49,6 @@
#error "CPU_INSTRUCTION_CACHE_ALIGNMENT is greater than CPU_CACHE_LINE_BYTES" #error "CPU_INSTRUCTION_CACHE_ALIGNMENT is greater than CPU_CACHE_LINE_BYTES"
#endif #endif
#if defined(RTEMS_SMP)
#include <rtems/score/smpimpl.h>
typedef struct {
const void *addr;
size_t size;
} smp_cache_area;
#if defined(CPU_DATA_CACHE_ALIGNMENT)
static void smp_cache_data_flush(void *arg)
{
smp_cache_area *area = arg;
rtems_cache_flush_multiple_data_lines(area->addr, area->size);
}
static void smp_cache_data_inv(void *arg)
{
smp_cache_area *area = arg;
rtems_cache_invalidate_multiple_data_lines(area->addr, area->size);
}
static void smp_cache_data_flush_all(void *arg)
{
rtems_cache_flush_entire_data();
}
static void smp_cache_data_inv_all(void *arg)
{
rtems_cache_invalidate_entire_data();
}
#endif /* defined(CPU_DATA_CACHE_ALIGNMENT) */
void
rtems_cache_flush_multiple_data_lines_processor_set(
const void *addr,
size_t size,
const size_t setsize,
const cpu_set_t *set
)
{
#if defined(CPU_DATA_CACHE_ALIGNMENT)
smp_cache_area area = { addr, size };
_SMP_Multicast_action( setsize, set, smp_cache_data_flush, &area );
#endif
}
void
rtems_cache_invalidate_multiple_data_lines_processor_set(
const void *addr,
size_t size,
const size_t setsize,
const cpu_set_t *set
)
{
#if defined(CPU_DATA_CACHE_ALIGNMENT)
smp_cache_area area = { addr, size };
_SMP_Multicast_action( setsize, set, smp_cache_data_inv, &area );
#endif
}
void
rtems_cache_flush_entire_data_processor_set(
const size_t setsize,
const cpu_set_t *set
)
{
#if defined(CPU_DATA_CACHE_ALIGNMENT)
_SMP_Multicast_action( setsize, set, smp_cache_data_flush_all, NULL );
#endif
}
void
rtems_cache_invalidate_entire_data_processor_set(
const size_t setsize,
const cpu_set_t *set
)
{
#if defined(CPU_DATA_CACHE_ALIGNMENT)
_SMP_Multicast_action( setsize, set, smp_cache_data_inv_all, NULL );
#endif
}
#endif /* defined(RTEMS_SMP) */
/* /*
* THESE FUNCTIONS ONLY HAVE BODIES IF WE HAVE A DATA CACHE * THESE FUNCTIONS ONLY HAVE BODIES IF WE HAVE A DATA CACHE
*/ */

79
cpukit/include/rtems/rtems/cache.h
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@@ -284,85 +284,6 @@ void rtems_cache_coherent_add_area(
uintptr_t area_size uintptr_t area_size
); );
#if defined( RTEMS_SMP )
/**
* @brief Flushes multiple data cache lines for a set of processors
*
* Dirty cache lines covering the area are transferred to memory.
* Depending on the cache implementation this may mark the lines as invalid.
*
* This operation should not be called from interrupt context.
*
* @param[in] addr The start address of the area to flush.
* @param[in] size The size in bytes of the area to flush.
* @param[in] setsize The size of the processor set.
* @param[in] set The target processor set.
*/
void rtems_cache_flush_multiple_data_lines_processor_set(
const void *addr,
size_t size,
const size_t setsize,
const cpu_set_t *set
);
/**
* @brief Invalidates multiple data cache lines for a set of processors
*
* The cache lines covering the area are marked as invalid. A later read
* access in the area will load the data from memory.
*
* In case the area is not aligned on cache line boundaries, then this
* operation may destroy unrelated data.
*
* This operation should not be called from interrupt context.
*
* @param[in] addr The start address of the area to invalidate.
* @param[in] size The size in bytes of the area to invalidate.
* @param[in] setsize The size of the processor set.
* @param[in] set The target processor set.
*/
void rtems_cache_invalidate_multiple_data_lines_processor_set(
const void *addr,
size_t size,
const size_t setsize,
const cpu_set_t *set
);
/**
* @brief Flushes the entire data cache for a set of processors
*
* This operation should not be called from interrupt context.
*
* @see rtems_cache_flush_multiple_data_lines().
*
* @param[in] setsize The size of the processor set.
* @param[in] set The target processor set.
*/
void rtems_cache_flush_entire_data_processor_set(
const size_t setsize,
const cpu_set_t *set
);
/**
* @brief Invalidates the entire cache for a set of processors
*
* This function is responsible for performing a data cache
* invalidate. It invalidates the entire cache for a set of
* processors.
*
* This operation should not be called from interrupt context.
*
* @param[in] setsize The size of the processor set.
* @param[in] set The target processor set.
*/
void rtems_cache_invalidate_entire_data_processor_set(
const size_t setsize,
const cpu_set_t *set
);
#endif
/**@}*/ /**@}*/
#ifdef __cplusplus #ifdef __cplusplus

52
testsuites/smptests/smpcache01/init.c
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@@ -23,8 +23,6 @@
const char rtems_test_name[] = "SMPCACHE 1"; const char rtems_test_name[] = "SMPCACHE 1";
CPU_STRUCTURE_ALIGNMENT static int data_to_flush[1024];
#define CPU_COUNT 32 #define CPU_COUNT 32
#define WORKER_PRIORITY 100 #define WORKER_PRIORITY 100
@@ -54,43 +52,12 @@ static void test_action( void *arg )
typedef void ( *test_case )( typedef void ( *test_case )(
size_t set_size, size_t set_size,
const cpu_set_t *cpu_set, const cpu_set_t *cpu_set
SMP_barrier_State *bs
); );
static void test_cache_flush_multiple_data_lines(
size_t set_size,
const cpu_set_t *cpu_set,
SMP_barrier_State *bs
)
{
rtems_cache_flush_multiple_data_lines_processor_set( &data_to_flush,
sizeof(data_to_flush), set_size, cpu_set );
}
static void test_cache_invalidate_multiple_data_lines(
size_t set_size,
const cpu_set_t *cpu_set,
SMP_barrier_State *bs
)
{
rtems_cache_invalidate_multiple_data_lines_processor_set( &data_to_flush,
sizeof(data_to_flush), set_size, cpu_set );
}
static void test_cache_flush_entire_data(
size_t set_size,
const cpu_set_t *cpu_set,
SMP_barrier_State *bs
)
{
rtems_cache_flush_entire_data_processor_set( set_size, cpu_set );
}
static void test_cache_invalidate_entire_instruction( static void test_cache_invalidate_entire_instruction(
size_t set_size, size_t set_size,
const cpu_set_t *cpu_set, const cpu_set_t *cpu_set
SMP_barrier_State *bs
) )
{ {
rtems_cache_invalidate_entire_instruction(); rtems_cache_invalidate_entire_instruction();
@@ -98,8 +65,7 @@ static void test_cache_invalidate_entire_instruction(
static void test_cache_invalidate_multiple_instruction_lines( static void test_cache_invalidate_multiple_instruction_lines(
size_t set_size, size_t set_size,
const cpu_set_t *cpu_set, const cpu_set_t *cpu_set
SMP_barrier_State *bs
) )
{ {
uint32_t self = rtems_get_current_processor(); uint32_t self = rtems_get_current_processor();
@@ -126,8 +92,7 @@ static void broadcast_test_init( void )
static void broadcast_test_body( static void broadcast_test_body(
size_t set_size, size_t set_size,
const cpu_set_t *cpu_set, const cpu_set_t *cpu_set
SMP_barrier_State *bs
) )
{ {
_SMP_Multicast_action( set_size, cpu_set, test_action, &ctx ); _SMP_Multicast_action( set_size, cpu_set, test_action, &ctx );
@@ -141,9 +106,6 @@ static void broadcast_test_fini( void )
} }
static test_case test_cases[] = { static test_case test_cases[] = {
test_cache_flush_multiple_data_lines,
test_cache_invalidate_multiple_data_lines,
test_cache_flush_entire_data,
test_cache_invalidate_entire_instruction, test_cache_invalidate_entire_instruction,
test_cache_invalidate_multiple_instruction_lines, test_cache_invalidate_multiple_instruction_lines,
broadcast_test_body broadcast_test_body
@@ -158,7 +120,7 @@ static void call_tests( size_t set_size,
for (i = 0; i < RTEMS_ARRAY_SIZE( test_cases ); ++i) { for (i = 0; i < RTEMS_ARRAY_SIZE( test_cases ); ++i) {
barrier( bs ); barrier( bs );
( *test_cases[ i ] )( set_size, cpu_set, bs ); ( *test_cases[ i ] )( set_size, cpu_set );
barrier( bs ); barrier( bs );
} }
@@ -177,7 +139,7 @@ static void call_tests_isr_disabled( size_t set_size,
_ISR_Local_disable( isr_level ); _ISR_Local_disable( isr_level );
barrier( bs ); barrier( bs );
( *test_cases[ i ] )( set_size, cpu_set, bs ); ( *test_cases[ i ] )( set_size, cpu_set );
_ISR_Local_enable( isr_level ); _ISR_Local_enable( isr_level );
barrier( bs ); barrier( bs );
} }
@@ -197,7 +159,7 @@ static void call_tests_with_thread_dispatch_disabled( size_t set_size,
cpu_self = _Thread_Dispatch_disable(); cpu_self = _Thread_Dispatch_disable();
barrier( bs ); barrier( bs );
( *test_cases[ i ] )( set_size, cpu_set, bs ); ( *test_cases[ i ] )( set_size, cpu_set );
barrier( bs ); barrier( bs );
_Thread_Dispatch_enable( cpu_self ); _Thread_Dispatch_enable( cpu_self );
} }