Patch from Thomas Doerfler <td@imd.m.isar.de> to improve 403 support.

- c/src/exec/score/cpu/powerpc/ppc.h: some small changes
      (added ppc403 characteristics like a exception vector prefix
      register, some special register definitions). I am quite sure, they
      are compatible with the existing sources, although I did not check

    - c/src/exec/score/cpu/powerpc/cpu.c: There is one severe
      limitation in the exception entries: Due to the current code
      arrangement, the "branch absolute" to the ISR handler may only
      jump to the first 128MByte or the last 128MByte of the 4GByte
      address range. When the ppc403 is running out of ROM, the ROM
      functions are located in the last 128MByte (0xFFF00000 and up).
      These addresses were not handled correctly (sign reduced) in
      "install_raw_handler". The change I added should work on existing
      ppc BSPs aswell...

c/src/exec/score/cpu/powerpc/TODO

@@ -5,3 +5,4 @@
 Todo list:
 
 Maybe decode external interrupts like the HPPA does.
+   See c/src/lib/libcpu/powerpc/ppc403/ictrl/* for implementation on ppc403

c/src/exec/score/cpu/powerpc/cpu.c

@@ -33,6 +33,7 @@
 #include <rtems/score/isr.h>
 #include <rtems/score/context.h>
 #include <rtems/score/thread.h>
+#include <rtems/score/interr.h>
 
 /*
  *  These are for testing purposes.
@@ -474,6 +475,12 @@ void _CPU_ISR_install_raw_handler(
      * Set u32_handler = to target address  
      */
     u32_handler = slot->b_Handler & 0x03fffffc;
+
+    /* IMD FIX: sign extend address fragment... */
+    if (u32_handler & 0x02000000) {
+      u32_handler  |= 0xfc000000;
+    }
+
     *old_handler =  (proc_ptr) u32_handler;
   } else
     *old_handler = 0;
@@ -484,6 +491,21 @@ void _CPU_ISR_install_raw_handler(
   *slot = _CPU_Trap_slot_template;
 
   u32_handler = (unsigned32) new_handler;
+
+  /* 
+   * IMD FIX: insert address fragment only (bits 6..29) 
+   *          therefore check for proper address range 
+   *          and remove unwanted bits
+   */
+  if ((u32_handler & 0xfc000000) == 0xfc000000) {
+    u32_handler  &= ~0xfc000000;
+  }
+  else if ((u32_handler & 0xfc000000) != 0x00000000) {
+    _Internal_error_Occurred(INTERNAL_ERROR_CORE,
+			     TRUE,
+			     u32_handler);
+  }
+
   slot->b_Handler |= u32_handler;
 
   slot->li_r0_IRQ  |= vector;
@@ -495,13 +517,20 @@ unsigned32  ppc_exception_vector_addr(
   unsigned32 vector
 )
 {
+#if (!PPC_HAS_EVPR)
   unsigned32 Msr;
+#endif
   unsigned32 Top = 0;
   unsigned32 Offset = 0x000;
 
+#if (PPC_HAS_EXCEPTION_PREFIX)
   _CPU_MSR_Value ( Msr );
   if ( ( Msr & PPC_MSR_EP) != 0 ) /* Vectors at FFFx_xxxx */
     Top = 0xfff00000;
+#elif (PPC_HAS_EVPR)
+  asm volatile( "mfspr %0,0x3d6" : "=r" (Top)); /* EVPR */
+  Top = Top & 0xffff0000;
+#endif
 
   switch ( vector ) {
     case PPC_IRQ_SYSTEM_RESET:   /* on 40x aka PPC_IRQ_CRIT */

c/src/exec/score/cpu/powerpc/cpu.h

@@ -481,7 +481,8 @@ typedef struct {
   boolean      serial_cts_rts;
   unsigned32   serial_rate;
   unsigned32   timer_average_overhead; /* Average overhead of timer in ticks */
-  unsigned32   timer_least_valid;      /* Least valid number from timer */
+  unsigned32   timer_least_valid;      /* Least valid number from timer      */
+  boolean      timer_internal_clock;   /* TRUE, when timer runs with CPU clk */
 #endif
 }   rtems_cpu_table;
 

c/src/exec/score/cpu/powerpc/ppc.h

@@ -112,6 +112,7 @@ extern "C" {
 
 #define PPC_DEBUG_MODEL          PPC_DEBUG_MODEL_IBM4xx
 #define PPC_HAS_EXCEPTION_PREFIX 0
+#define PPC_HAS_EVPR             1
 
 #elif defined(ppc601)
 /*
@@ -286,6 +287,15 @@ extern "C" {
 #define PPC_HAS_EXCEPTION_PREFIX 1
 #endif
 
+/*
+ *  Unless otherwise specified, assume the model does NOT have
+ *  403 style EVPR register to set the exception address prefix.
+ */
+
+#ifndef PPC_HAS_EVPR
+#define PPC_HAS_EVPR 0
+#endif
+
 /*
  *  If no low power mode model was specified, then assume there is none.
  */