PR 1381/networking
* netinet/ip_output.c: If a null or unreachable gateway is
specified either statically in networkconfig.h or from dhcp/bootp,
sendto() fails on multicast send with errno "118 Host is unreachable".
The failure occurs in networking file ip_output.c since it currently
requires all multicasts to have a valid route to the outside world.
PR 1381/networking
* libnetworking/netinet/ip_output.c: If a null or unreachable gateway
is specified either statically in networkconfig.h or from dhcp/bootp,
sendto() fails on multicast send with errno 118 Host
PR 1832/libcpu
* at91rm9200/irq/irq.c: he bsp_interrupt_dispatch routine does not
determine the correct interrupt source number. According to the
datasheet, the reading of the interrupt vector register (AIC_IVR)
notifies the hardware that the OS is taken care of the interrupt.
Only after AIC_IVR have been read can the correct source number be
read from the interrupt status register (AIC_ISR).
PR 1775/filesystem
* libfs/src/nfsclient/src/nfs.c: NFSAddress NFS issue where read/write
problems when requested bytes greater than nfsStBlksize. Failure to
create files and symlinks.
PR 1786/bsps
* Makefile.am: Add support for Altivec.
* startup/bspstart.c, Makefile.am: Use shared/startup/zerobss.c instead.
* make/custom/mvme5500.cfg: Change CPU_CFLAGS to
"-mcpu=7450 -mtune=7450 -Dmpc7455"
* irq/BSP_irq.c, pci/detect_host_bridge.c, pci.c, pcifinddevice.c:
Remove warnings.
* vme/VMEConfig.h, include/bsp.h: use VME shared IRQ handlers.
* network/if_100MHz/GT64260eth.c: Recycle the Rx mbuf if there
is any Rx error.
PR 1781/bsps
* console/console-io.c: The UART RX and TX are different ISR
now. So the array containing the registeration changes. The
change is due to change in the libcup uart function.
PR 1781/bsps
* ChangeLog, Makefile.am, README, bsp_specs, configure.ac,
preinstall.am, times, console/console.c, include/bsp.h,
include/cplb.h, include/tm27.h, make/custom/TLL6527M.cfg,
startup/bspstart.c, startup/linkcmds: New files.
Initial port for the TLL6527Mboard that contains blackfin 52X
range of processors. Used eZKit533 as a reference for building
the port.
PR 1781/bsps
* bf52x/include: Added additional MMR.
* bf52x/interrupt: The BF52X processors have a different
System interrupt controller than present in the 53X range of
processors. The 52X have 8 interrupt assignment registers. The
implementation uses tables to increase predictability.
* serial/uart.?: Added DMA based and interrupt based transfer
support. The uart code used a single ISR for TX and RX and tried
to identify and multiplex inside the ISR. In the new code the
type of interrupt is identified by the central ISR dispatcher
bf52x/interrupt or interrupt/. This simplifies the UART ISR.
PR 1781/bsps
* bfin/rtems/bf52x.h: This file defines basic MMR for the Blackfin
52x CPU. The MMR have been taken from the ADSP-BF52x Blackfin
Processor Hardware Reference from Analog Devices. Mentioned
Chapters refer to this Documentation.
