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added BSP hsc_cm01

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This commit is contained in:
Thomas Doerfler
2007-08-10 08:15:58 +00:00
parent 38630e9849
commit e35c6965bf
14 changed files with 641 additions and 39 deletions
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4
README.configure
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@@ -202,8 +202,10 @@ mips : csb350 genmongoosev hurricane jmr3904 rbtx4925 rbtx4938
powerpc : psim score603e mcp750 mvme2100 mvme2307 mpc8260ads ss555 powerpc : psim score603e mcp750 mvme2100 mvme2307 mpc8260ads ss555
mvme5500 ep1a pm520_cr825 pm520_ze30 gen405 helas403 mvme5500 ep1a pm520_cr825 pm520_ze30 gen405 helas403
mbx821_001 mbx821_002 mbx821_002b mbx860_001b mbx821_001 mbx821_002 mbx821_002b mbx860_001b
mbx860_002 mbx860_005b mtx603e brs5l gen5200 ep5200
virtex gen83xx mpc8349eamds
mbx860_002 mbx860_005b mtx603e brs5l gen5200 icecube mbx860_002 mbx860_005b mtx603e brs5l gen5200 icecube
virtex gen83xx mpc8349eamds virtex gen83xx mpc8349eamds hsc_cm01
NOTE: The "motorola_powerpc" BSP is a single BSP which NOTE: The "motorola_powerpc" BSP is a single BSP which
can be conditionally compiled to support most Motorola can be conditionally compiled to support most Motorola

1
aclocal/bsp-alias.m4
View File

@@ -27,6 +27,7 @@ AC_DEFUN([_RTEMS_BSP_ALIAS],
pm520*) $2=gen5200 ;; # MPC5200 based board pm520*) $2=gen5200 ;; # MPC5200 based board
icecube) $2=gen5200 ;; # MPC5200 based board - LITE5200B icecube) $2=gen5200 ;; # MPC5200 based board - LITE5200B
mpc8349eamds) $2=gen83xx ;; # MPC8349 based board mpc8349eamds) $2=gen83xx ;; # MPC8349 based board
hsc_cm01) $2=gen83xx ;; # MPC8349 based board
simcpu32) $2=sim68000 ;; # BSVC CPU32 variant simcpu32) $2=sim68000 ;; # BSVC CPU32 variant
simsh7032) $2=shsim ;; # SH7032 simulator simsh7032) $2=shsim ;; # SH7032 simulator
simsh7045) $2=shsim ;; # SH7045 simulator simsh7045) $2=shsim ;; # SH7045 simulator

2
aclocal/check-bsps.m4
View File

@@ -26,7 +26,7 @@ AC_MSG_CHECKING([for available BSPs])
bsps="$bsps mbx860_005b" bsps="$bsps mbx860_005b"
;; ;;
gen5200) bsps="pm520_cr825 pm520_ze30 brs5l";; gen5200) bsps="pm520_cr825 pm520_ze30 brs5l";;
gen83xx) bsps="mpc8349eamds";; gen83xx) bsps="mpc8349eamds hsc_cm01";;
motorola_powerpc) bsps="mvme2307 mcp750 mtx603e mvme2100";; motorola_powerpc) bsps="mvme2307 mcp750 mtx603e mvme2100";;
pc386) bsps="pc386 pc386dx pc486 pc586 pc686 pck6";; pc386) bsps="pc386 pc386dx pc486 pc586 pc686 pck6";;
erc32) bsps="erc32 sis";; erc32) bsps="erc32 sis";;

4
c/src/lib/libbsp/powerpc/gen83xx/ChangeLog
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@@ -1,3 +1,7 @@
2007-08-08 Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
* Makefile.am, i2c/i2c_init.c: add i2c initialization
2007-07-13 Joel Sherrill <joel.sherrill@OARcorp.com> 2007-07-13 Joel Sherrill <joel.sherrill@OARcorp.com>
* Makefile.am, preinstall.am: Install a linkcmds all the time. * Makefile.am, preinstall.am: Install a linkcmds all the time.

14
c/src/lib/libbsp/powerpc/gen83xx/Makefile.am
View File

@@ -33,7 +33,9 @@ rtems_crti.$(OBJEXT): ../../powerpc/shared/start/rtems_crti.S
$(CPPASCOMPILE) -o $@ -c $< $(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA += rtems_crti.$(OBJEXT) project_lib_DATA += rtems_crti.$(OBJEXT)
dist_project_lib_DATA += startup/linkcmds startup/linkcmds.mpc8349eamds dist_project_lib_DATA += startup/linkcmds \
startup/linkcmds.mpc8349eamds \
startup/linkcmds.hsc_cm01
noinst_PROGRAMS += mpc83xx_regs.rel noinst_PROGRAMS += mpc83xx_regs.rel
mpc83xx_regs_rel_SOURCES = startup/mpc83xx_regs.c mpc83xx_regs_rel_SOURCES = startup/mpc83xx_regs.c
@@ -85,11 +87,16 @@ network_rel_CPPFLAGS += -D__INSIDE_RTEMS_BSD_TCPIP_STACK__ -D__BSD_VISIBLE
network_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) network_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
noinst_PROGRAMS += bsp_i2c.rel
bsp_i2c_rel_SOURCES = i2c/i2c_init.c
bsp_i2c_rel_CPPFLAGS = $(AM_CPPFLAGS)
bsp_i2c_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
noinst_LIBRARIES = libbsp.a noinst_LIBRARIES = libbsp.a
libbsp_a_SOURCES = libbsp_a_SOURCES =
libbsp_a_LIBADD = startup.rel pclock.rel console.rel \ libbsp_a_LIBADD = startup.rel pclock.rel console.rel \
vectors.rel irq.rel mpc83xx_regs.rel vectors.rel irq.rel mpc83xx_regs.rel
libbsp_a_LIBADD += network.rel libbsp_a_LIBADD += network.rel bsp_i2c.rel
libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \ libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
../../../libcpu/@RTEMS_CPU@/shared/cache.rel \ ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \ ../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
@@ -99,7 +106,8 @@ libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
../../../libcpu/@RTEMS_CPU@/mpc6xx/clock.rel \ ../../../libcpu/@RTEMS_CPU@/mpc6xx/clock.rel \
../../../libcpu/@RTEMS_CPU@/mpc6xx/mmu.rel \ ../../../libcpu/@RTEMS_CPU@/mpc6xx/mmu.rel \
../../../libcpu/@RTEMS_CPU@/mpc6xx/timer.rel \ ../../../libcpu/@RTEMS_CPU@/mpc6xx/timer.rel \
../../../libcpu/@RTEMS_CPU@/mpc83xx/tsec.rel ../../../libcpu/@RTEMS_CPU@/mpc83xx/tsec.rel \
../../../libcpu/@RTEMS_CPU@/mpc83xx/i2c.rel
EXTRA_DIST += README.mpc8349eamds EXTRA_DIST += README.mpc8349eamds
EXTRA_DIST += times.mpc8349eamds EXTRA_DIST += times.mpc8349eamds

111
c/src/lib/libbsp/powerpc/gen83xx/i2c/i2c_init.c Normal file
View File

@@ -0,0 +1,111 @@
/*===============================================================*\
| Project: RTEMS support for MPC83xx |
+-----------------------------------------------------------------+
| Copyright (c) 2007 |
| Embedded Brains GmbH |
| Obere Lagerstr. 30 |
| D-82178 Puchheim |
| Germany |
| rtems@embedded-brains.de |
+-----------------------------------------------------------------+
| The license and distribution terms for this file may be |
| found in the file LICENSE in this distribution or at |
| |
| http://www.rtems.com/license/LICENSE. |
| |
+-----------------------------------------------------------------+
| this file contains the low level MPC83xx I2C driver parameters |
\*===============================================================*/
#include <mpc83xx/mpc83xx_i2cdrv.h>
#include <libchip/i2c-2b-eeprom.h>
#include <bsp/irq.h>
#include <bsp.h>
static mpc83xx_i2c_desc_t mpc83xx_i2c_bus_tbl[2] = {
/* first channel */
{
{/* public fields */
ops: &mpc83xx_i2c_ops,
size: sizeof(mpc83xx_i2c_bus_tbl[0]),
},
{ /* our private fields */
reg_ptr: &mpc83xx.i2c[0],
initialized: FALSE,
irq_number: BSP_IPIC_IRQ_I2C1
}
},
/* second channel */
{
{ /* public fields */
ops: &mpc83xx_i2c_ops,
size: sizeof(mpc83xx_i2c_bus_tbl[1]),
},
{ /* our private fields */
reg_ptr: &mpc83xx.i2c[1],
initialized: FALSE,
irq_number: BSP_IPIC_IRQ_I2C2
}
}
};
rtems_libi2c_bus_t *mpc83xx_i2c_bus_descriptor[2] = {
&mpc83xx_i2c_bus_tbl[0].bus_desc,
&mpc83xx_i2c_bus_tbl[1].bus_desc
};
/*=========================================================================*\
| Function: |
\*-------------------------------------------------------------------------*/
rtems_status_code bsp_register_i2c
(
/*-------------------------------------------------------------------------*\
| Purpose: |
| register I2C busses and devices |
+---------------------------------------------------------------------------+
| Input Parameters: |
\*-------------------------------------------------------------------------*/
void /* <none> */
)
/*-------------------------------------------------------------------------*\
| Return Value: |
| 0 or error code |
\*=========================================================================*/
{
int ret_code;
/*
* init I2C library
*/
rtems_libi2c_initialize ();
/*
* register first I2C bus
*/
ret_code = rtems_libi2c_register_bus("/dev/i2c1",
mpc83xx_i2c_bus_descriptor[0]);
if (ret_code < 0) {
return -ret_code;
}
/*
* register second I2C bus
*/
ret_code = rtems_libi2c_register_bus("/dev/i2c2",
mpc83xx_i2c_bus_descriptor[1]);
if (ret_code < 0) {
return -ret_code;
}
/*
* register EEPROM to bus 1, Address 0x50
*/
ret_code = rtems_libi2c_register_drv(RTEMS_BSP_I2C_EEPROM_DEVICE_NAME,
i2c_2b_eeprom_driver_descriptor,
0,0x50);
if (ret_code < 0) {
return -ret_code;
}
/*
* FIXME: register RTC driver, when available
*/
return 0;
}

91
c/src/lib/libbsp/powerpc/gen83xx/include/bsp.h
View File

@@ -40,12 +40,81 @@
#define BSP_CLKIN_FRQ 66000000L #define BSP_CLKIN_FRQ 66000000L
#define BSP_SYSPLL_MF 4 /* FIXME: derive from clock register */ #define BSP_SYSPLL_MF 4 /* FIXME: derive from clock register */
/*
* Reset configuration words
*/
#define RESET_CONF_WRD_L (RCWLR_LBIUCM_1_1 | \
RCWLR_DDRCM_1_1 | \
RCWLR_SPMF(4) | \
RCWLR_COREPLL(4))
#define RESET_CONF_WRD_H (RCWHR_PCI_HOST | \
RCWHR_PCI_32 | \
RCWHR_PCI1ARB_EN | \
RCWHR_PCI2ARB_EN | \
RCWHR_CORE_EN | \
RCWHR_BMS_LOW | \
RCWHR_BOOTSEQ_NONE | \
RCWHR_SW_DIS | \
RCWHR_ROMLOC_LB16 | \
RCWHR_TSEC1M_GMII | \
RCWHR_TSEC2M_GMII | \
RCWHR_ENDIAN_BIG | \
RCWHR_LALE_NORM | \
RCWHR_LDP_PAR)
/*
* for JPK HSC_CM01
*/
#elsif defined(HSC_CM01)
/*
* one DUART channel (UART1) supported
*/
#define GEN83xx_DUART_AVAIL_MASK 0x01
/* we need the low level initialization in start.S*/
#define NEED_LOW_LEVEL_INIT
/*
* clocking infos
*/
#define BSP_CLKIN_FRQ 66000000L
#define BSP_SYSPLL_MF 4 /* FIXME: derive from clock register */
/*
* Reset configuration words
*/
#define RESET_CONF_WRD_L (RCWLR_LBIUCM_1_1 | \
RCWLR_DDRCM_1_1 | \
RCWLR_SPMF(4) | \
RCWLR_COREPLL(4))
#define RESET_CONF_WRD_H (RCWHR_PCI_HOST | \
RCWHR_PCI_32 | \
RCWHR_PCI1ARB_EN | \
RCWHR_PCI2ARB_EN | \
RCWHR_CORE_EN | \
RCWHR_BMS_LOW | \
RCWHR_BOOTSEQ_NONE | \
RCWHR_SW_DIS | \
RCWHR_ROMLOC_LB16 | \
RCWHR_TSEC1M_RGMII | \
RCWHR_TSEC2M_GMII | \
RCWHR_ENDIAN_BIG | \
RCWHR_LALE_NORM | \
RCWHR_LDP_PAR)
#else
#error "board type not defined"
#endif
/*
* for JPK HSC_CM01 and freescale MPC8349EAMDS
*/
#if defined(MPC8349EAMDS) || defined(HSC_CM01)
/* /*
* address range definitions * address range definitions
*/ */
/* ROM definitions (2 MB) */ /* ROM definitions (8 MB, mirrored multiple times) */
#define ROM_START 0xFFE00000 #define ROM_START 0xFE000000
#define ROM_SIZE 0x00200000 #define ROM_SIZE 0x02000000
#define ROM_END (ROM_START+ROM_SIZE-1) #define ROM_END (ROM_START+ROM_SIZE-1)
#define BOOT_START ROM_START #define BOOT_START ROM_START
#define BOOT_END ROM_END #define BOOT_END ROM_END
@@ -55,6 +124,7 @@
#define RAM_SIZE 0x10000000 #define RAM_SIZE 0x10000000
#define RAM_END (RAM_START+RAM_SIZE-1) #define RAM_END (RAM_START+RAM_SIZE-1)
/* working internal memory map base address */ /* working internal memory map base address */
#define IMMRBAR 0xE0000000 #define IMMRBAR 0xE0000000
@@ -125,14 +195,6 @@ extern "C" {
#include <bsp/irq.h> #include <bsp/irq.h>
#include <bsp/vectors.h> #include <bsp/vectors.h>
/*
* Network driver configuration
*/
struct rtems_bsdnet_ifconfig;
extern int rtems_mpc83xx_tsec_driver_attach_detach (struct rtems_bsdnet_ifconfig *config, int attaching);
#define RTEMS_BSP_NETWORK_DRIVER_NAME "tsec1"
#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_mpc83xx_tsec_driver_attach_detach
/* miscellaneous stuff assumed to exist */ /* miscellaneous stuff assumed to exist */
extern rtems_configuration_table BSP_Configuration; extern rtems_configuration_table BSP_Configuration;
@@ -176,6 +238,7 @@ extern rtems_configuration_table BSP_Configuration;
/* functions */ /* functions */
void bsp_cleanup(void); void bsp_cleanup(void);
rtems_status_code bsp_register_i2c(void);
/* console modes (only termios) */ /* console modes (only termios) */
#ifdef PRINTK_MINOR #ifdef PRINTK_MINOR
@@ -211,6 +274,12 @@ extern int BSP_tsec_attach(struct rtems_bsdnet_ifconfig *config,int attaching);
#define RTEMS_BSP_NETWORK_DRIVER_NAME2 "tsec2" #define RTEMS_BSP_NETWORK_DRIVER_NAME2 "tsec2"
/*
* i2c EEPROM device name
*/
#define RTEMS_BSP_I2C_EEPROM_DEVICE_NAME "eeprom"
#define RTEMS_BSP_I2C_EEPROM_DEVICE_PATH "/dev/i2c1.eeprom"
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

4
c/src/lib/libbsp/powerpc/gen83xx/preinstall.am
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@@ -73,6 +73,10 @@ $(PROJECT_LIB)/linkcmds.mpc8349eamds: startup/linkcmds.mpc8349eamds $(PROJECT_LI
$(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.mpc8349eamds $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.mpc8349eamds
PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.mpc8349eamds PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.mpc8349eamds
$(PROJECT_LIB)/linkcmds.hsc_cm01: startup/linkcmds.hsc_cm01 $(PROJECT_LIB)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.hsc_cm01
PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.hsc_cm01
$(PROJECT_INCLUDE)/bsp/irq.h: ./irq/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) $(PROJECT_INCLUDE)/bsp/irq.h: ./irq/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h

92
c/src/lib/libbsp/powerpc/gen83xx/start/start.S
View File

@@ -73,6 +73,8 @@
sync sync
.endm .endm
#define REP8(l) l ; l; l; l; l; l; l; l;
.extern _bss_start .extern _bss_start
.extern _bss_size .extern _bss_size
.extern _data_start .extern _data_start
@@ -83,31 +85,48 @@
.extern boot_card .extern boot_card
.extern MBAR .extern MBAR
.section ".vectors" .section ".resconf","ax"
PUBLIC_VAR (reset_conf_words)
reset_conf_words:
REP8( .byte ((RESET_CONF_WRD_L >> 24) & 0xff))
REP8( .byte ((RESET_CONF_WRD_L >> 16) & 0xff))
REP8( .byte ((RESET_CONF_WRD_L >> 8) & 0xff))
REP8( .byte ((RESET_CONF_WRD_L >> 0) & 0xff))
REP8( .byte ((RESET_CONF_WRD_H >> 24) & 0xff))
REP8( .byte ((RESET_CONF_WRD_H >> 16) & 0xff))
REP8( .byte ((RESET_CONF_WRD_H >> 8) & 0xff))
REP8( .byte ((RESET_CONF_WRD_H >> 0) & 0xff))
.section ".vectors","ax"
PUBLIC_VAR (reset_vec) PUBLIC_VAR (reset_vec)
reset_vec: reset_vec:
bl start bl rom_entry
.section ".entry" .section ".entry"
PUBLIC_VAR (start) PUBLIC_VAR (start)
start: start:
/* /*
* FIXME: basic CPU setup: * basic CPU setup:
* init MSR * init MSR
*/ */
mfmsr r30 mfmsr r30
SETBITS r30, r29, MSR_ME|MSR_RI SETBITS r30, r29, MSR_ME|MSR_RI
CLRBITS r30, r29, MSR_IP|MSR_EE CLRBITS r30, r29, MSR_IP|MSR_EE
mtmsr r30 /* Set RI/ME, Clr EE in MSR */ mtmsr r30 /* Set RI/ME, Clr EE in MSR */
b start_rom_skip
PUBLIC_VAR (rom_entry)
rom_entry:
/* /*
* check, wether we are starting from ROM * basic CPU setup:
* detect this using the absolute code address: * init MSR
* when the upper 4 bits are 0xF, then we are in ROM
*/ */
bl 1f mfmsr r30
1: mflr r28 SETBITS r30, r29, MSR_ME|MSR_RI
LWI r29,0xF0000000 CLRBITS r30, r29, MSR_IP|MSR_EE
TSTBITS r28,r29,r30,0xF0000000 mtmsr r30 /* Set RI/ME, Clr EE in MSR */
bne start_rom_skip
/* /*
* ROM startup: remap IMMR to 0xE0000000 * ROM startup: remap IMMR to 0xE0000000
* use special sequence from MPC8349EA RM Rev 1, 5.2.4.1.1 "Updating IMMRBAR" * use special sequence from MPC8349EA RM Rev 1, 5.2.4.1.1 "Updating IMMRBAR"
@@ -116,22 +135,49 @@ start:
LWI r31,IMMRBAR LWI r31,IMMRBAR
lwz r29,0(r30) lwz r29,0(r30)
stw r31,0(r30) stw r31,0(r30)
#if 0
lwz r29,0(r28) /* read from ROM... */ lwz r29,0(r28) /* read from ROM... */
#endif
isync isync
lwz r29,0(r31) /* read from IMMRBAR... */ lwz r29,0(r31) /* read from IMMRBAR... */
isync isync
/* /*
* NOTE: now r31 points to onchip registers * NOTE: now r31 points to onchip registers
*/
/* /*
* ROM startup: init local access windows * FIXME:
* we start from 0x100, so ROM is currently mapped to
* 0x00000000..
* in the next step, ROM will be remapped to its final location
* at 0xfe000000... (using LBLAWBAR1 with LBLAWBAR0 value)
* and we jump to that location.
* then we remove the ROM mapping to zero
*/ */
#ifdef LBLAWBAR0_VAL
SET_IMM_REGW r31,r30,LBLAWBAR1_OFF,LBLAWBAR0_VAL
#endif
#ifdef LBLAWAR0_VAL
SET_IMM_REGW r31,r30,LBLAWAR1_OFF,LBLAWAR0_VAL
#endif
/*
* ROM startup: jump to code final ROM location
*/
LA r20, ROM_START /* ROM-RAM reloc in r20 */
LA r29, start_code_in_rom /* get compile time addr of label */
add r29,r20,r29 /* compute exec address */
mtlr r29
blr /* now further execution in upper ROM */
start_code_in_rom:
#ifdef LBLAWBAR0_VAL #ifdef LBLAWBAR0_VAL
SET_IMM_REGW r31,r30,LBLAWBAR0_OFF,LBLAWBAR0_VAL SET_IMM_REGW r31,r30,LBLAWBAR0_OFF,LBLAWBAR0_VAL
#endif #endif
#ifdef LBLAWAR0_VAL #ifdef LBLAWAR0_VAL
SET_IMM_REGW r31,r30,LBLAWAR0_OFF,LBLAWAR0_VAL SET_IMM_REGW r31,r30,LBLAWAR0_OFF,LBLAWAR0_VAL
#endif #endif
#ifdef LBLAWBAR1_VAL #ifdef LBLAWBAR1_VAL
SET_IMM_REGW r31,r30,LBLAWBAR1_OFF,LBLAWBAR1_VAL SET_IMM_REGW r31,r30,LBLAWBAR1_OFF,LBLAWBAR1_VAL
#endif #endif
@@ -275,20 +321,22 @@ start:
LA r29, _data_start /* get start address of data section in RAM */ LA r29, _data_start /* get start address of data section in RAM */
LA r28, _data_size /* get size of RAM image */ LA r28, _data_size /* get size of RAM image */
bl copy_image /* copy initialized data section from ROM to RAM location */ bl copy_image /* copy initialized data section from ROM to RAM location */
start_rom_skip:
/*
* ROM startup: clear bss in SDRAM
*/
LWI r30, _bss_start /* get start address of bss section */
LWI r29, _bss_size /* get size of bss section */
bl clr_mem /* Clear the bss section */
/* /*
* ROM startup: jump to code copy in SDRAM * ROM startup: jump to code copy in SDRAM
*/ */
LA r29, start_code_in_ram /* get compile time address of label */ LA r29, start_code_in_ram /* get compile time address of label */
mtlr r29 mtlr r29
blr /* now further execution RAM */ blr /* now further execution RAM */
start_code_in_ram: start_code_in_ram:
start_rom_skip:
/*
* ROM/RAM startup: clear bss in SDRAM
*/
LWI r30, _bss_start /* get start address of bss section */
LWI r29, _bss_size /* get size of bss section */
bl clr_mem /* Clear the bss section */
/* /*
* call boot_card * call boot_card
*/ */

5
c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds
View File

@@ -46,6 +46,11 @@ SECTIONS
*mpc83xx_regs*(*) *mpc83xx_regs*(*)
} > mpc83xx_regs } > mpc83xx_regs
.resconf 0x000 :
{
*(.resconf)
} > ram
.vectors 0x100 : .vectors 0x100 :
{ {
*(.vectors) *(.vectors)

329
c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds.hsc_cm01 Normal file
View File

@@ -0,0 +1,329 @@
/*
* This file contains directives for the GNU linker which are specific
* to a hsc_cm01 board
*
* $Id$
*/
OUTPUT_FORMAT("elf32-powerpc", "elf32-powerpc",
"elf32-powerpc")
OUTPUT_ARCH(powerpc)
ENTRY(start)
/*
* Declare some sizes.
* XXX: The assignment of ". += XyzSize;" fails in older gld's if the
* number used there is not constant. If this happens to you, edit
* the lines marked XXX below to use a constant value.
*/
HeapSize = DEFINED(HeapSize) ? HeapSize : 0x6800000; /* 104M Heap */
StackSize = DEFINED(StackSize) ? StackSize : 0x80000; /* 512 kB */
WorkSpaceSize = DEFINED(WorkSpaceSize) ? WorkSpaceSize : 0x80000; /* 512k */
RamDiskSize = DEFINED(RamDiskSize) ? RamDiskSize : 0x80000; /* 512 ram disk */
/*
* optionally reserve additional space
*/
TopRamReserved = DEFINED(TopRamReserved) ? TopRamReserved : 0;
MEMORY
{
ram : org = 0x0, l = 256M
mpc83xx_regs : org = 0xE0000000, l = 256k
}
SECTIONS
{
mpc83xx_regs (NOLOAD) :
{
IMMRBAR = .;
*mpc83xx_regs*(*)
} > mpc83xx_regs
.resconf 0x000 :
{
*(.resconf)
} > ram
.vectors 0x100 :
{
*(.vectors)
}
> ram
/*
* The stack will live in this area - between the vectors and
* the text section.
*/
.text 0x10000:
{
_textbase = .;
text.start = .;
/* Entry point is the .entry section */
*(.entry)
*(.entry2)
/* Actual Code */
*(.text*)
*(.rodata*)
*(.rodata1)
/*
* Special FreeBSD sysctl sections.
*/
. = ALIGN (16);
__start_set_sysctl_set = .;
*(set_sysctl_*);
__stop_set_sysctl_set = ABSOLUTE(.);
*(set_domain_*);
*(set_pseudo_*);
/* C++ constructors/destructors */
*(.gnu.linkonce.t*)
/* Initialization and finalization code.
*
* Various files can provide initialization and finalization functions.
* The bodies of these functions are in .init and .fini sections. We
* accumulate the bodies here, and prepend function prologues from
* ecrti.o and function epilogues from ecrtn.o. ecrti.o must be linked
* first; ecrtn.o must be linked last. Because these are wildcards, it
* doesn't matter if the user does not actually link against ecrti.o and
* ecrtn.o; the linker won't look for a file to match a wildcard. The
* wildcard also means that it doesn't matter which directory ecrti.o
* and ecrtn.o are in.
*/
PROVIDE (_init = .);
*ecrti.o(.init)
*(.init)
*ecrtn.o(.init)
PROVIDE (_fini = .);
*ecrti.o(.fini)
*(.fini)
*ecrtn.o(.init)
/*
* C++ constructors and destructors for static objects.
* PowerPC EABI does not use crtstuff yet, so we build "old-style"
* constructor and destructor lists that begin with the list lenght
* end terminate with a NULL entry.
*/
PROVIDE (__CTOR_LIST__ = .);
*crtbegin.o(.ctors)
*(.ctors)
*crtend.o(.ctors)
LONG(0)
PROVIDE (__CTOR_END__ = .);
PROVIDE (__DTOR_LIST__ = .);
*crtbegin.o(.dtors)
*(.dtors)
*crtend.o(.dtors)
LONG(0)
PROVIDE (__DTOR_END__ = .);
/* Exception frame info */
*(.eh_frame)
/* Miscellaneous read-only data */
_rodata_start = . ;
*(.gnu.linkonce.r*)
*(.lit)
*(.shdata)
*(.rodata)
*(.rodata1)
*(.descriptors)
*(rom_ver)
_erodata = .;
PROVIDE (__EXCEPT_START__ = .);
*(.gcc_except_table)
PROVIDE (__EXCEPT_END__ = .);
__GOT_START__ = .;
s.got = .;
*(.got.plt)
*(.got)
*(.got1)
PROVIDE (__GOT2_START__ = .);
PROVIDE (_GOT2_START_ = .);
*(.got2)
PROVIDE (__GOT2_END__ = .);
PROVIDE (_GOT2_END_ = .);
PROVIDE (__FIXUP_START__ = .);
PROVIDE (_FIXUP_START_ = .);
*(.fixup)
PROVIDE (_FIXUP_END_ = .);
PROVIDE (__FIXUP_END__ = .);
/* Various possible names for the end of the .text section */
etext = ALIGN(0x10);
_etext = .;
_endtext = .;
text.end = .;
PROVIDE (etext = .);
PROVIDE (__etext = .);
} > ram
.jcr : { KEEP (*(.jcr)) } > ram
.rel.dyn : {
*(.rel.init)
*(.rel.text .rel.text.* .rel.gnu.linkonce.t.*)
*(.rel.fini)
*(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)
*(.rel.data.rel.ro* .rel.gnu.linkonce.d.rel.ro.*)
*(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)
*(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)
*(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)
*(.rel.ctors)
*(.rel.dtors)
*(.rel.got)
*(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*)
*(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*)
*(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*)
*(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*)
*(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)
} >ram
.rela.dyn : {
*(.rela.init)
*(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
*(.rela.fini)
*(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
*(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
*(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
*(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
*(.rela.ctors)
*(.rela.dtors)
*(.rela.got)
*(.rela.got1)
*(.rela.got2)
*(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*)
*(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*)
*(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*)
*(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*)
*(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
} >ram
PROVIDE (__SDATA2_START__ = .);
.sdata2 : { *(.sdata2) *(.gnu.linkonce.s2.*) } >ram
.sbss2 : { *(.sbss2) *(.gnu.linkonce.sb2.*) } >ram
PROVIDE (__SBSS2_END__ = .);
.sbss2 : { *(.sbss2) } >ram
PROVIDE (__SBSS2_END__ = .);
/* R/W Data */
.data ( . ) :
{
. = ALIGN (4);
data.start = .;
*(.data)
*(.data1)
*(.data.* .gnu.linkonce.d.*)
PROVIDE (__SDATA_START__ = .);
*(.sdata*)
*(.gnu.linkonce.s.*)
data.end = .;
} > ram
__SBSS_START__ = .;
.bss :
{
bss.start = .;
*(.bss .bss* .gnu.linkonce.b*)
*(.sbss*) *(COMMON)
. = ALIGN(4);
bss.end = .;
} > ram
__SBSS_END__ = .;
PROVIDE(_bss_start = ADDR(.bss));
PROVIDE(_bss_size = SIZEOF(.bss));
PROVIDE(_data_start = ADDR(.data));
PROVIDE(_data_size = SIZEOF(.data));
PROVIDE(_text_start = ADDR(.text));
PROVIDE(_text_size = SIZEOF(.text));
PROVIDE(_end = data.end);
.gzipmalloc : {
. = ALIGN (16);
_startmalloc = .;
} >ram
/*
* Interrupt stack setup
*/
IntrStack_start = ALIGN(0x10);
. += 0x4000;
intrStack = .;
PROVIDE(intrStackPtr = intrStack);
_WorkspaceBase = .;
__WorkspaceBase = .;
. += WorkSpaceSize;
_RamDiskBase = .;
__RamDiskBase = .;
. += RamDiskSize;
_RamDiskEnd = .;
__RamDiskEnd = .;
PROVIDE( _RamDiskSize = _RamDiskEnd - _RamDiskBase );
_HeapStart = .;
__HeapStart = .;
. += HeapSize;
_HeapEnd = .;
__HeapEnd = .;
clear_end = .;
/* Sections for compressed .text and .data */
/* after the .datarom section is an int specifying */
/* the length of the following compressed image */
/* Executes once then could get overwritten */
.textrom 0x100000 :
{
*(.textrom)
_endloader = .;
} > ram
.datarom :
{
_dr_start = .;
*(.datarom)
_dr_end = .;
} > ram
dr_len = _dr_end - _dr_start;
.line 0 : { *(.line) }
.debug 0 : { *(.debug) }
.debug_sfnames 0 : { *(.debug_sfnames) }
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
.debug_aregion 0 : { *(.debug_aregion) }
.debug_macinfo 0 : { *(.debug_macinfo) }
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
}

5
c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds.mpc8349eamds
View File

@@ -43,6 +43,11 @@ SECTIONS
*mpc83xx_regs*(*) *mpc83xx_regs*(*)
} > mpc83xx_regs } > mpc83xx_regs
.resconf 0x000 :
{
*(.resconf)
} > ram
.vectors 0x100 : .vectors 0x100 :
{ {
*(.vectors) *(.vectors)

16
make/custom/hsc_cm01.cfg Normal file
View File

@@ -0,0 +1,16 @@
#
# Config file for customer specific MPC8349 board
#
# $Id$
#
#
# All GEN83xx configurations share the same base file, only a few
# parameters differ.
#
RTEMS_BOARD_MODEL=HSC-CM01
RTEMS_83XX_DERIVATE=MPC8349
RTEMS_LINKCMDS=linkcmds.hsc_cm01
include $(RTEMS_ROOT)/make/custom/gen83xx.cfg

2
make/custom/mpc8349eamds.cfg
View File

@@ -1,5 +1,5 @@
# #
# Config file for customer specific MPC5200 board # Config file for freescale's MPC8349EAMDS evaluation board
# #
# $Id$ # $Id$
# #