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https://github.com/t-crest/rtems.git
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2009-04-19 Joel Sherrill <joel.sherrill@oarcorp.com>
* cpu_supplement/.cvsignore, cpu_supplement/Makefile.am, cpu_supplement/cpu_supplement.texi: Add shell for Atmel AVR chapter. * cpu_supplement/avr.t: New file.
This commit is contained in:
Joel Sherrill
@@ -1,3 +1,9 @@
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2009-04-19 Joel Sherrill <joel.sherrill@oarcorp.com>
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* cpu_supplement/.cvsignore, cpu_supplement/Makefile.am,
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cpu_supplement/cpu_supplement.texi: Add shell for Atmel AVR chapter.
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* cpu_supplement/avr.t: New file.
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2009-03-30 Sebastian Huber <sebastian.huber@embedded-brains.de>
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* shell/confinit.t: New argument sequence for rtems_shell_init().
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@@ -1,4 +1,5 @@
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arm.texi
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avr.texi
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bfin.texi
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cpu_supplement
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cpu_supplement-?
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@@ -21,7 +21,7 @@ TEXI2WWW_ARGS=\
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-header rtems_header.html \
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-footer rtems_footer.html \
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-icons ../images
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GENERATED_FILES = general.texi arm.texi bfin.texi i386.texi lm32.texi \
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GENERATED_FILES = general.texi arm.texi avr.texi bfin.texi i386.texi lm32.texi \
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m68k.texi mips.texi powerpc.texi sh.texi sparc.texi tic4x.texi
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COMMON_FILES += $(top_srcdir)/common/cpright.texi
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@@ -45,6 +45,11 @@ arm.texi: arm.t
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-u "Top" \
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-n "" < $< > $@
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avr.texi: avr.t
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$(BMENU2) -p "" \
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-u "Top" \
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-n "" < $< > $@
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bfin.texi: bfin.t
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$(BMENU2) -p "" \
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-u "Top" \
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128
doc/cpu_supplement/avr.t
Normal file
128
doc/cpu_supplement/avr.t
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@@ -0,0 +1,128 @@
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@c
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@c COPYRIGHT (c) 1988-2009.
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@c On-Line Applications Research Corporation (OAR).
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@c All rights reserved.
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@c
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@c $Id$
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@c
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@ifinfo
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@end ifinfo
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@chapter Atmel AVR Specific Information
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This chapter discusses the AVR architecture dependencies in this
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port of RTEMS.
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@subheading Architecture Documents
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For information on the AVR architecture, refer to the following
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documents available from Atmel.
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TBD
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@itemize @bullet
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@item See other CPUs for documentation reference formatting examples.
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@end itemize
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@section CPU Model Dependent Features
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CPUs of the AVR 53X only differ in the peripherals and thus in the
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device drivers. This port does not yet support the 56X dual core variants.
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@subsection Count Leading Zeroes Instruction
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The AVR CPU has the XXX instruction which could be used to speed
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up the find first bit operation. The use of this instruction should
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significantly speed up the scheduling associated with a thread blocking.
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@section Calling Conventions
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@subsection Processor Background
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The AVR architecture supports a simple call and return mechanism.
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A subroutine is invoked via the call (@code{call}) instruction.
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This instruction saves the return address in the @code{RETS} register
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and transfers the execution to the given address.
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It is the called funcions responsability to use the link instruction
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to reserve space on the stack for the local variables. Returning from
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a subroutine is done by using the RTS (@code{RTS}) instruction which
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loads the PC with the adress stored in RETS.
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It is is important to note that the @code{call} instruction does not
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automatically save or restore any registers. It is the responsibility
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of the high-level language compiler to define the register preservation
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and usage convention.
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@subsection Register Usage
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A called function may clobber all registers, except RETS, R4-R7, P3-P5,
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FP and SP. It may also modify the first 12 bytes in the caller’s stack
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frame which is used as an argument area for the first three arguments
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(which are passed in R0...R3 but may be placed on the stack by the
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called function).
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@subsection Parameter Passing
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RTEMS assumes that the AVR GCC calling convention is followed.
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The first three parameters are stored in registers R0, R1, and R2.
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All other parameters are put pushed on the stack. The result is returned
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through register R0.
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@section Memory Model
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The AVR family architecutre support a single unified 4 GB byte
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address space using 32-bit addresses. It maps all resources like internal
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and external memory and IO registers into separate sections of this
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common address space.
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The AVR architcture supports some form of memory
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protection via its Memory Management Unit. Since the
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AVR port runs in supervisior mode this memory
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protection mechanisms are not used.
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@section Interrupt Processing
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Discussed in this chapter are the AVR's interrupt response and
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control mechanisms as they pertain to RTEMS.
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@subsection Vectoring of an Interrupt Handler
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TBD
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@subsection Disabling of Interrupts by RTEMS
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During interrupt disable critical sections, RTEMS disables interrupts to
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level N (N) before the execution of this section and restores them
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to the previous level upon completion of the section. RTEMS uses the
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instructions CLI and STI to enable and disable Interrupts. Emulation,
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Reset, NMI and Exception Interrupts are never disabled.
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@subsection Interrupt Stack
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The AVR Architecture works with two different kind of stacks,
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User and Supervisor Stack. Since RTEMS and its Application run
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in supervisor mode, all interrupts will use the interrupted
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tasks stack for execution.
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@section Default Fatal Error Processing
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The default fatal error handler for the AVR performs the following
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actions:
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@itemize @bullet
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@item disables processor interrupts,
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@item places the error code in @b{r0}, and
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@item executes an infinite loop (@code{while(0);} to
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simulate a halt processor instruction.
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@end itemize
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@section Board Support Packages
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@subsection System Reset
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TBD
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@@ -8,7 +8,7 @@
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@c %**end of header
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@c
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@c COPYRIGHT (c) 1988-2008.
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@c COPYRIGHT (c) 1988-2009.
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@c On-Line Applications Research Corporation (OAR).
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@c All rights reserved.
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@c
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@@ -61,6 +61,7 @@
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@include preface.texi
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@include general.texi
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@include arm.texi
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@include avr.texi
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@include bfin.texi
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@include i386.texi
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@include lm32.texi
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@@ -80,6 +81,7 @@ This is the online version of the RTEMS CPU Architecture Supplement.
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* Preface::
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* Port Specific Information::
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* ARM Specific Information::
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* Atmel AVR Specific Information::
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* Blackfin Specific Information::
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* Intel/AMD x86 Specific Information::
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* Lattice Mico32 Specific Information::
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