mirror of
https://github.com/t-crest/rtems.git
synced 2025-11-16 12:34:47 +00:00
* README: Added NCS.
* Makefile.am, configure.ac, preinstall.am: Added BSP variants. * console/console-config.c, clock/clock-config.c, ssp/ssp.c: Fixed register settings. Cleanup. * include/bsp.h: Added network defines and functions. * include/lpc24xx.h: Added AHB and EMC defines. Fixed Ethernet status sizes. * include/system-clocks.h, misc/system-clocks.c: Added micro seconds delay function that uses Timer 1. Changed PLL setup. * network/network.c, startup/bspreset.c, startup/linkcmds.lpc2478, startup/linkcmds.lpc2478_ncs, startup/linkcmds.lpc2478_ncs_ram: New files. * startup/bspstart.c: Added EMC initialization. Changes for ROM boot.
This commit is contained in:
Thomas Doerfler
@@ -1,3 +1,8 @@
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2009-02-27 Sebastian Huber <sebastian.huber@embedded-brains.de>
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* aclocal/bsp-alias.m4, aclocal/check-bsps.m4: Added defines for
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LPC2478 BSP variants.
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2009-02-19 Joel Sherrill <joel.sherrill@oarcorp.com>
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* aclocal/bsp-alias.m4: Add simsh2e.
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@@ -38,6 +38,8 @@ AC_DEFUN([_RTEMS_BSP_ALIAS],
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mpc8313erdb) $2=gen83xx ;; # MPC83XX based board
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rtl22xx_t) $2=rtl22xx ;; # rtl22xx bsp in thumb mode
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lpc2478) $2=lpc24xx ;; # LPC2478 (QVGA Base Board from Embedded Artists)
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lpc2478_ncs) $2=lpc24xx ;; # LPC2478 (NCS)
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lpc2478_ncs_ram) $2=lpc24xx ;; # LPC2478 (NCS, code and data in external RAM)
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simcpu32) $2=sim68000 ;; # BSVC CPU32 variant
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simsh1) $2=shsim ;; # SH1 simulator in GDB
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simsh2) $2=shsim ;; # SH2 simulator in GDB
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@@ -35,7 +35,7 @@ AC_MSG_CHECKING([for available BSPs])
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pc386) bsps="pc386 pc386dx pc486 pc586 pc686";;
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erc32) bsps="erc32 sis";;
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rtl22xx) bsps="rtl22xx rtl22xx_t";;
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lpc24xx) bsps="lpc2478";;
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lpc24xx) bsps="lpc2478 lpc2478_ncs lpc2478_ncs_ram";;
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sim68000) bsps="sim68000 simcpu32";;
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shsim) bsps="simsh1 simsh2 simsh4";;
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m32cbsp) bsps="m32csim";;
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@@ -1,3 +1,9 @@
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2009-02-27 Sebastian Huber <sebastian.huber@embedded-brains.de>
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* shared/startup/linkcmds.rom: New file
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* shared/include/start.h: Added declaration of start().
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* shared/start/start.S: Fixed vector table for ROM boot.
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2008-09-23 Joel Sherrill <joel.sherrill@OARcorp.com>
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* acinclude.m4: New BSP -- lpc24xx.
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@@ -1,3 +1,19 @@
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2009-02-27 Sebastian Huber <sebastian.huber@embedded-brains.de>
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* README: Added NCS.
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* Makefile.am, configure.ac, preinstall.am: Added BSP variants.
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* console/console-config.c, clock/clock-config.c, ssp/ssp.c: Fixed
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register settings. Cleanup.
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* include/bsp.h: Added network defines and functions.
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* include/lpc24xx.h: Added AHB and EMC defines. Fixed Ethernet status
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sizes.
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* include/system-clocks.h, misc/system-clocks.c: Added micro seconds
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delay function that uses Timer 1. Changed PLL setup.
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* network/network.c, startup/bspreset.c, startup/linkcmds.lpc2478,
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startup/linkcmds.lpc2478_ncs, startup/linkcmds.lpc2478_ncs_ram: New
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files.
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* startup/bspstart.c: Added EMC initialization. Changes for ROM boot.
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2009-02-17 Ralf Corsépius <ralf.corsepius@rtems.org>
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* Makefile.am: Fix breakage introduced in 2009-02-13 changes.
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@@ -21,14 +21,15 @@ dist_project_lib_DATA = bsp_specs
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include_HEADERS = include/bsp.h
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nodist_include_HEADERS = include/bspopts.h
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nodist_include_HEADERS = ../../shared/include/coverhd.h \
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include/bspopts.h
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nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h
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nodist_include_HEADERS += ../../shared/include/coverhd.h
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include_bsp_HEADERS =
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include_bsp_HEADERS += ../../shared/include/utility.h
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include_bsp_HEADERS += ../../shared/include/irq-generic.h
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include_bsp_HEADERS += ../../shared/include/irq-info.h
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include_bsp_HEADERS += ../../shared/tod.h
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include_bsp_HEADERS += ../shared/include/linker-symbols.h
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include_bsp_HEADERS += ../shared/include/start.h
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@@ -38,6 +39,7 @@ include_bsp_HEADERS += include/lpc24xx.h
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include_bsp_HEADERS += include/system-clocks.h
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include_bsp_HEADERS += include/ssp.h
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include_bsp_HEADERS += include/dma.h
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include_HEADERS += ../../shared/include/tm27.h
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###############################################################################
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@@ -51,7 +53,10 @@ libbspstart_a_SOURCES = ../shared/start/start.S
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project_lib_DATA = start.$(OBJEXT)
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dist_project_lib_DATA += ../shared/startup/linkcmds.base \
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startup/linkcmds
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../shared/startup/linkcmds.rom \
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startup/linkcmds.lpc2478 \
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startup/linkcmds.lpc2478_ncs \
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startup/linkcmds.lpc2478_ncs_ram
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###############################################################################
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# LibBSP #
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@@ -64,7 +69,6 @@ libbsp_a_SOURCES =
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# Shared
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libbsp_a_SOURCES += ../../shared/bootcard.c \
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../../shared/bspclean.c \
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../../shared/bspreset.c \
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../../shared/bspgetworkarea.c \
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../../shared/bsplibc.c \
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../../shared/bsppost.c \
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@@ -75,11 +79,14 @@ libbsp_a_SOURCES += ../../shared/bootcard.c \
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../shared/abort/simple_abort.c
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# Startup
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libbsp_a_SOURCES += startup/bspstart.c
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libbsp_a_SOURCES += startup/bspstart.c \
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startup/bspreset.c
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# IRQ
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libbsp_a_SOURCES += ../../shared/src/irq-generic.c \
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../../shared/src/irq-legacy.c \
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../../shared/src/irq-info.c \
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../../shared/src/irq-shell.c \
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../shared/irq/irq_asm.S \
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irq/irq.c
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@@ -104,6 +111,22 @@ libbsp_a_SOURCES += misc/system-clocks.c \
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# SSP
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libbsp_a_SOURCES += ssp/ssp.c
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###############################################################################
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# Network #
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###############################################################################
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if HAS_NETWORKING
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noinst_PROGRAMS = network.rel
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network_rel_SOURCES = network/network.c
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network_rel_CPPFLAGS = $(AM_CPPFLAGS) -D__INSIDE_RTEMS_BSD_TCPIP_STACK__ -D__BSD_VISIBLE
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network_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
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libbsp_a_LIBADD = network.rel
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endif
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###############################################################################
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# Special Rules #
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###############################################################################
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@@ -7,7 +7,39 @@ Development Board: QVGA Base Board from Embedded Artists
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http://www.embeddedartists.com/products/uclinux/oem_lpc2478.php
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Drivers:
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o Console
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o Clock
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o RTC
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o SSP (SPI mode): This driver is in active development. Use with care.
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o Network
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Howto setup QVGA Base Board?
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o Unpack board.
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o Connect board via USB to your PC.
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o Verify that demo application runs.
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o Disconnect board.
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o Change jumpers to enable ISP.
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o Connect board.
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o Load U-Boot image 'u-boot_v1.1.6_lpc2468oem_v1_8_16bit.hex'
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(available from the EA support page) into the flash (flash tool
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FlashMagic is availabe from NXP).
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o Change jumbers back to disable ISP.
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o Use a terminal program to change the U-Boot settings via the console.
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o U-Boot settings:
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set ethaddr '00:1a:f1:X:X:X'
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set serverip 'X.X.X.X'
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set ipaddr 'X.X.X.X'
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set rtems 'tftp a1000000 lpc2478.img;bootm'
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set bootcmd 'echo Booting RTEMS ...;run rtems'
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saveenv
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Application Board: NCS (Nurse Control Station)
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Board: NextGenNCS
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Processor: NXP LPC2478
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SDRAM: 8MByte, 16 bit wide
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Ext. Flash: 1MByte, 16 bit wide
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Console: UART, 115200 Baud
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Network: 100Base-T
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@@ -57,7 +57,8 @@ static void lpc24xx_clock_initialize( void)
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/* Set timer pclk to cclk */
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rtems_interrupt_disable( level);
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SET_PCLKSEL0_PCLK_TIMER0( PCLKSEL0, 1);
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PCONP = SET_FLAGS( PCONP, 0x02);
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PCLKSEL0 = SET_FLAGS( PCLKSEL0, 0x04);
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rtems_interrupt_enable( level);
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/* Reset timer */
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@@ -106,7 +107,7 @@ static void lpc24xx_clock_cleanup( void)
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static uint32_t lpc24xx_clock_nanoseconds_since_last_tick( void)
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{
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uint64_t clock = lpc24xx_cclk();
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uint64_t clock = LPC24XX_CCLK;
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uint32_t clicks = T0TC;
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uint64_t ns = ((uint64_t) clicks * 1000000000) / clock;
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@@ -23,15 +23,28 @@ RTEMS_PROG_CCAS
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RTEMS_CHECK_NETWORKING
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AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes")
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RTEMS_BSPOPTS_SET([LPC24XX_OSCILLATOR_MAIN],[lpc2478],
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[12000000U])
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RTEMS_BSPOPTS_HELP([LPC24XX_OSCILLATOR_MAIN],
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[Main oscillator frequency in Hz])
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RTEMS_BSPOPTS_SET([LPC24XX_OSCILLATOR_MAIN],[*],[12000000U])
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RTEMS_BSPOPTS_HELP([LPC24XX_OSCILLATOR_MAIN],[Main oscillator frequency in Hz])
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RTEMS_BSPOPTS_SET([LPC24XX_OSCILLATOR_RTC],[lpc2478],
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[32768])
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RTEMS_BSPOPTS_HELP([LPC24XX_OSCILLATOR_RTC],
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[RTC oscillator frequency in Hz])
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RTEMS_BSPOPTS_SET([LPC24XX_OSCILLATOR_RTC],[*],[32768])
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RTEMS_BSPOPTS_HELP([LPC24XX_OSCILLATOR_RTC],[RTC oscillator frequency in Hz])
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RTEMS_BSPOPTS_SET([LPC24XX_CCLK],[*],[72000000])
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RTEMS_BSPOPTS_HELP([LPC24XX_CCLK],[CPU clock in Hz])
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RTEMS_BSPOPTS_SET([LPC24XX_UART_BAUD],[*],[115200])
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RTEMS_BSPOPTS_HELP([LPC24XX_UART_BAUD],[Baud for UARTs])
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RTEMS_BSPOPTS_SET([LPC24XX_HAS_UBOOT],[lpc2478],[1])
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RTEMS_BSPOPTS_SET([LPC24XX_HAS_UBOOT],[lpc2478_ncs_ram],[1])
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RTEMS_BSPOPTS_HELP([LPC24XX_HAS_UBOOT],[Enable U-Boot startup])
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RTEMS_BSPOPTS_SET([LPC24XX_ETHERNET_RMII],[lpc2478_ncs],[1])
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RTEMS_BSPOPTS_SET([LPC24XX_ETHERNET_RMII],[lpc2478_ncs_ram],[1])
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RTEMS_BSPOPTS_HELP([LPC24XX_ETHERNET_RMII],[Enable RMII for Ethernet])
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RTEMS_BSPOPTS_SET([LPC24XX_EMC_MICRON],[lpc2478_ncs],[1])
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RTEMS_BSPOPTS_HELP([LPC24XX_EMC_MICRON],[Enable RMII for Ethernet])
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BSP_BOOTCARD_OPTIONS
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@@ -21,6 +21,7 @@
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#include <libchip/serial.h>
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#include <libchip/ns16550.h>
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#include <bsp.h>
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#include <bsp/lpc24xx.h>
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#include <bsp/irq.h>
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@@ -55,7 +56,7 @@ console_tbl Console_Port_Tbl [LPC24XX_UART_NUMBER] = {
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.pDeviceFlow = NULL,
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.ulMargin = 16,
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.ulHysteresis = 8,
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.pDeviceParams = (void *) 38400,
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.pDeviceParams = (void *) LPC24XX_UART_BAUD,
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.ulCtrlPort1 = UART0_BASE_ADDR,
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.ulCtrlPort2 = 0,
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.ulDataPort = UART0_BASE_ADDR,
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@@ -63,7 +64,7 @@ console_tbl Console_Port_Tbl [LPC24XX_UART_NUMBER] = {
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.setRegister = lpc24xx_uart_set_register,
|
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.getData = NULL,
|
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.setData = NULL,
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.ulClock = 57600000,
|
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.ulClock = LPC24XX_CCLK,
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.ulIntVector = LPC24XX_IRQ_UART_0
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}
|
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};
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|
||||
@@ -35,6 +35,19 @@ extern "C" {
|
||||
|
||||
#ifndef ASM
|
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|
||||
/* Network driver configuration */
|
||||
|
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struct rtems_bsdnet_ifconfig;
|
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|
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int lpc24xx_eth_attach_detach(
|
||||
struct rtems_bsdnet_ifconfig *config,
|
||||
int attaching
|
||||
);
|
||||
|
||||
#define RTEMS_BSP_NETWORK_DRIVER_ATTACH lpc24xx_eth_attach_detach
|
||||
|
||||
#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0"
|
||||
|
||||
#endif /* ASM */
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
@@ -1854,14 +1854,13 @@ typedef struct {
|
||||
typedef struct {
|
||||
uint32_t status;
|
||||
uint32_t hash_crc;
|
||||
} lpc24xx_eth_transfer_status;
|
||||
} lpc24xx_eth_receive_info;
|
||||
|
||||
#define ETH_TRANSFER_DESCRIPTOR_SIZE 8
|
||||
|
||||
#define ETH_TRANSFER_STATUS_SIZE 8
|
||||
#define ETH_RECEIVE_INFO_SIZE 8
|
||||
|
||||
#define ETH_TRANSFER_CTRL_SIZE \
|
||||
(ETH_TRANSFER_DESCRIPTOR_SIZE + ETH_TRANSFER_STATUS_SIZE)
|
||||
#define ETH_TRANSMIT_STATUS_SIZE 4
|
||||
|
||||
/* ETH_RX_CTRL */
|
||||
|
||||
@@ -2023,4 +2022,88 @@ typedef struct {
|
||||
|
||||
#define ETH_CMD_FULL_DUPLEX 0x00000400U
|
||||
|
||||
/* AHBCFG */
|
||||
|
||||
#define AHBCFG_SCHEDULER_UNIFORM 0x00000001U
|
||||
|
||||
#define AHBCFG_BREAK_BURST_MASK 0x00000006U
|
||||
|
||||
#define GET_AHBCFG_BREAK_BURST( reg) \
|
||||
GET_FIELD( reg, AHBCFG_BREAK_BURST_MASK, 1)
|
||||
|
||||
#define SET_AHBCFG_BREAK_BURST( reg, val) \
|
||||
SET_FIELD( reg, val, AHBCFG_BREAK_BURST_MASK, 1)
|
||||
|
||||
#define AHBCFG_QUANTUM_BUS_CYCLE 0x00000008U
|
||||
|
||||
#define AHBCFG_QUANTUM_SIZE_MASK 0x000000f0U
|
||||
|
||||
#define GET_AHBCFG_QUANTUM_SIZE( reg) \
|
||||
GET_FIELD( reg, AHBCFG_QUANTUM_SIZE_MASK, 4)
|
||||
|
||||
#define SET_AHBCFG_QUANTUM_SIZE( reg, val) \
|
||||
SET_FIELD( reg, val, AHBCFG_QUANTUM_SIZE_MASK, 4)
|
||||
|
||||
#define AHBCFG_DEFAULT_MASTER_MASK 0x00000700U
|
||||
|
||||
#define GET_AHBCFG_DEFAULT_MASTER( reg) \
|
||||
GET_FIELD( reg, AHBCFG_DEFAULT_MASTER_MASK, 8)
|
||||
|
||||
#define SET_AHBCFG_DEFAULT_MASTER( reg, val) \
|
||||
SET_FIELD( reg, val, AHBCFG_DEFAULT_MASTER_MASK, 8)
|
||||
|
||||
#define AHBCFG_EP1_MASK 0x00007000U
|
||||
|
||||
#define GET_AHBCFG_EP1( reg) \
|
||||
GET_FIELD( reg, AHBCFG_EP1_MASK, 12)
|
||||
|
||||
#define SET_AHBCFG_EP1( reg, val) \
|
||||
SET_FIELD( reg, val, AHBCFG_EP1_MASK, 12)
|
||||
|
||||
#define AHBCFG_EP2_MASK 0x00070000U
|
||||
|
||||
#define GET_AHBCFG_EP2( reg) \
|
||||
GET_FIELD( reg, AHBCFG_EP2_MASK, 16)
|
||||
|
||||
#define SET_AHBCFG_EP2( reg, val) \
|
||||
SET_FIELD( reg, val, AHBCFG_EP2_MASK, 16)
|
||||
|
||||
#define AHBCFG_EP3_MASK 0x00700000U
|
||||
|
||||
#define GET_AHBCFG_EP3( reg) \
|
||||
GET_FIELD( reg, AHBCFG_EP3_MASK, 20)
|
||||
|
||||
#define SET_AHBCFG_EP3( reg, val) \
|
||||
SET_FIELD( reg, val, AHBCFG_EP3_MASK, 20)
|
||||
|
||||
#define AHBCFG_EP4_MASK 0x07000000U
|
||||
|
||||
#define GET_AHBCFG_EP4( reg) \
|
||||
GET_FIELD( reg, AHBCFG_EP4_MASK, 24)
|
||||
|
||||
#define SET_AHBCFG_EP4( reg, val) \
|
||||
SET_FIELD( reg, val, AHBCFG_EP4_MASK, 24)
|
||||
|
||||
#define AHBCFG_EP5_MASK 0x70000000U
|
||||
|
||||
#define GET_AHBCFG_EP5( reg) \
|
||||
GET_FIELD( reg, AHBCFG_EP5_MASK, 28)
|
||||
|
||||
#define SET_AHBCFG_EP5( reg, val) \
|
||||
SET_FIELD( reg, val, AHBCFG_EP5_MASK, 28)
|
||||
|
||||
/* EMC */
|
||||
|
||||
#define EMC_DYN_CTRL_CE 0x00000001U
|
||||
|
||||
#define EMC_DYN_CTRL_CS 0x00000002U
|
||||
|
||||
#define EMC_DYN_CTRL_CMD_NORMAL 0x00000000U
|
||||
|
||||
#define EMC_DYN_CTRL_CMD_MODE 0x00000080U
|
||||
|
||||
#define EMC_DYN_CTRL_CMD_PALL 0x00000100U
|
||||
|
||||
#define EMC_DYN_CTRL_CMD_NOP 0x00000180U
|
||||
|
||||
#endif /* LIBBSP_ARM_LPC24XX_LPC24XX_H */
|
||||
|
||||
@@ -25,6 +25,8 @@
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
void lpc24xx_micro_seconds_delay( unsigned us);
|
||||
|
||||
unsigned lpc24xx_cclk( void);
|
||||
|
||||
void lpc24xx_set_pll( unsigned clksrc, unsigned nsel, unsigned msel, unsigned cclksel);
|
||||
|
||||
@@ -28,16 +28,49 @@
|
||||
*/
|
||||
#define LPC24XX_OSCILLATOR_INTERNAL 4000000U
|
||||
|
||||
#if !defined(LPC24XX_OSCILLATOR_MAIN)
|
||||
#error unknown main oscillator frequency
|
||||
#ifndef LPC24XX_OSCILLATOR_MAIN
|
||||
#error "unknown main oscillator frequency"
|
||||
#endif
|
||||
|
||||
#if !defined(LPC24XX_OSCILLATOR_RTC)
|
||||
#error unknown rtc oscillator frequency
|
||||
#ifndef LPC24XX_OSCILLATOR_RTC
|
||||
#error "unknown RTC oscillator frequency"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Delay for @a us micro seconds.
|
||||
*
|
||||
* @note Uses Timer 1.
|
||||
*/
|
||||
void lpc24xx_micro_seconds_delay( unsigned us)
|
||||
{
|
||||
/* Stop and reset timer */
|
||||
T1TCR = 0x02;
|
||||
|
||||
/* Set prescaler to zero */
|
||||
T1PR = 0x00;
|
||||
|
||||
/* Set match value */
|
||||
T1MR0 = (uint32_t) ((uint64_t) 4000000 * (uint64_t) us / (uint64_t) lpc24xx_cclk()) + 1;
|
||||
|
||||
/* Reset all interrupt flags */
|
||||
T1IR = 0xff;
|
||||
|
||||
/* Stop timer on match */
|
||||
T1MCR = 0x04;
|
||||
|
||||
/* Start timer */
|
||||
T1TCR = 0x01;
|
||||
|
||||
/* Wait until delay time has elapsed */
|
||||
while ((T1TCR & 0x01) != 0) {
|
||||
/* Wait */
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the CPU clock frequency in [Hz].
|
||||
*
|
||||
* Return zero in case of an unexpected PLL input frequency.
|
||||
*/
|
||||
unsigned lpc24xx_cclk( void)
|
||||
{
|
||||
@@ -58,9 +91,6 @@ unsigned lpc24xx_cclk( void)
|
||||
pllinclk = LPC24XX_OSCILLATOR_RTC;
|
||||
break;
|
||||
default:
|
||||
while (1) {
|
||||
/* Spin forever */
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -116,7 +146,7 @@ void lpc24xx_set_pll( unsigned clksrc, unsigned nsel, unsigned msel, unsigned cc
|
||||
}
|
||||
|
||||
/* Set CPU clock divider to a reasonable save value */
|
||||
CCLKCFG = SET_CCLKCFG_CCLKSEL( 0, 1);
|
||||
CCLKCFG = 0;
|
||||
|
||||
/* Disable PLL if necessary */
|
||||
if (pll_enabled) {
|
||||
|
||||
@@ -41,6 +41,10 @@ $(PROJECT_INCLUDE)/bsp.h: include/bsp.h $(PROJECT_INCLUDE)/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp.h
|
||||
|
||||
$(PROJECT_INCLUDE)/coverhd.h: ../../shared/include/coverhd.h $(PROJECT_INCLUDE)/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/coverhd.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/coverhd.h
|
||||
|
||||
$(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h
|
||||
@@ -49,10 +53,6 @@ $(PROJECT_INCLUDE)/bsp/bootcard.h: ../../shared/include/bootcard.h $(PROJECT_INC
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bootcard.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bootcard.h
|
||||
|
||||
$(PROJECT_INCLUDE)/coverhd.h: ../../shared/include/coverhd.h $(PROJECT_INCLUDE)/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/coverhd.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/coverhd.h
|
||||
|
||||
$(PROJECT_INCLUDE)/bsp/utility.h: ../../shared/include/utility.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/utility.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/utility.h
|
||||
@@ -61,6 +61,10 @@ $(PROJECT_INCLUDE)/bsp/irq-generic.h: ../../shared/include/irq-generic.h $(PROJE
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-generic.h
|
||||
|
||||
$(PROJECT_INCLUDE)/bsp/irq-info.h: ../../shared/include/irq-info.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-info.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-info.h
|
||||
|
||||
$(PROJECT_INCLUDE)/bsp/tod.h: ../../shared/tod.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/tod.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/tod.h
|
||||
@@ -109,7 +113,19 @@ $(PROJECT_LIB)/linkcmds.base: ../shared/startup/linkcmds.base $(PROJECT_LIB)/$(d
|
||||
$(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.base
|
||||
PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.base
|
||||
|
||||
$(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds
|
||||
PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds
|
||||
$(PROJECT_LIB)/linkcmds.rom: ../shared/startup/linkcmds.rom $(PROJECT_LIB)/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.rom
|
||||
PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.rom
|
||||
|
||||
$(PROJECT_LIB)/linkcmds.lpc2478: startup/linkcmds.lpc2478 $(PROJECT_LIB)/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.lpc2478
|
||||
PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.lpc2478
|
||||
|
||||
$(PROJECT_LIB)/linkcmds.lpc2478_ncs: startup/linkcmds.lpc2478_ncs $(PROJECT_LIB)/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.lpc2478_ncs
|
||||
PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.lpc2478_ncs
|
||||
|
||||
$(PROJECT_LIB)/linkcmds.lpc2478_ncs_ram: startup/linkcmds.lpc2478_ncs_ram $(PROJECT_LIB)/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.lpc2478_ncs_ram
|
||||
PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.lpc2478_ncs_ram
|
||||
|
||||
|
||||
@@ -217,14 +217,14 @@ static rtems_status_code lpc24xx_ssp_init( rtems_libi2c_bus_t *bus)
|
||||
switch ((uintptr_t) regs) {
|
||||
case SSP0_BASE_ADDR:
|
||||
rtems_interrupt_disable( level);
|
||||
SET_PCLKSEL1_PCLK_SSP0( PCLKSEL1, 1);
|
||||
PCLKSEL1 = SET_PCLKSEL1_PCLK_SSP0( PCLKSEL1, 1);
|
||||
rtems_interrupt_enable( level);
|
||||
|
||||
vector = LPC24XX_IRQ_SPI_SSP_0;
|
||||
break;
|
||||
case SSP1_BASE_ADDR:
|
||||
rtems_interrupt_disable( level);
|
||||
SET_PCLKSEL0_PCLK_SSP1( PCLKSEL0, 1);
|
||||
PCLKSEL0 = SET_PCLKSEL0_PCLK_SSP1( PCLKSEL0, 1);
|
||||
rtems_interrupt_enable( level);
|
||||
|
||||
vector = LPC24XX_IRQ_SSP_1;
|
||||
@@ -402,7 +402,7 @@ static int lpc24xx_ssp_read_write(
|
||||
}
|
||||
|
||||
/* Disable DMA on SSP */
|
||||
regs->dmacr = SSP_DMACR_RXDMAE | SSP_DMACR_TXDMAE;
|
||||
regs->dmacr = 0;
|
||||
|
||||
if (in == NULL) {
|
||||
dr = 0;
|
||||
|
||||
@@ -29,27 +29,290 @@
|
||||
#include <bsp/start.h>
|
||||
#include <bsp/system-clocks.h>
|
||||
|
||||
void bsp_start_hook_0( void)
|
||||
static void lpc24xx_fatal_error( void)
|
||||
{
|
||||
/* Re-map interrupt vectors to internal RAM */
|
||||
SET_MEMMAP_MAP( MEMMAP, 2);
|
||||
while (true) {
|
||||
/* Spin forever */
|
||||
}
|
||||
}
|
||||
|
||||
void bsp_start_hook_1( void)
|
||||
static void lpc24xx_ram_test_32( void)
|
||||
{
|
||||
unsigned zero = 0;
|
||||
unsigned *out = bsp_section_bss_start;
|
||||
volatile unsigned *out = (volatile unsigned *) bsp_ram_ext_start;
|
||||
|
||||
/* Clear BSS */
|
||||
while (out < bsp_section_bss_end) {
|
||||
*out = zero;
|
||||
while (out < (volatile unsigned *) bsp_ram_ext_end) {
|
||||
*out = (unsigned) out;
|
||||
++out;
|
||||
}
|
||||
|
||||
out = (volatile unsigned *) bsp_ram_ext_start;
|
||||
while (out < (volatile unsigned *) bsp_ram_ext_end) {
|
||||
if (*out != (unsigned) out) {
|
||||
lpc24xx_fatal_error();
|
||||
}
|
||||
++out;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief EMC initialization.
|
||||
*
|
||||
* Dynamic Memory 0: Micron M T48LC 4M16 A2 P 75 IT
|
||||
*/
|
||||
static void lpc24xx_init_emc( void)
|
||||
{
|
||||
#ifdef LPC24XX_EMC_MICRON
|
||||
int i = 0;
|
||||
uint32_t mode = 0;
|
||||
|
||||
/* Enable power */
|
||||
PCONP = SET_FLAGS( PCONP, 0x0800);
|
||||
|
||||
/* Set PIN selects */
|
||||
PINSEL5 = SET_FLAGS( PINSEL5, 0x05050555);
|
||||
PINSEL6 = SET_FLAGS( PINSEL6, 0x55555555);
|
||||
PINSEL8 = SET_FLAGS( PINSEL8, 0x55555555);
|
||||
PINSEL9 = SET_FLAGS( PINSEL9, 0x50555555);
|
||||
|
||||
/* Enable module, normal memory map and normal power mode */
|
||||
EMC_CTRL = 1;
|
||||
|
||||
/* Use little-endian mode and 1:1 clock ratio */
|
||||
EMC_CONFIG = 0;
|
||||
|
||||
/* Global dynamic settings */
|
||||
|
||||
/* FIXME */
|
||||
EMC_DYN_APR = 2;
|
||||
|
||||
/* Data-in to active command period tWR + tRP */
|
||||
EMC_DYN_DAL = 4;
|
||||
|
||||
/* Load mode register to active or refresh command period 2 tCK */
|
||||
EMC_DYN_MRD = 1;
|
||||
|
||||
/* Active to precharge command period 44 ns */
|
||||
EMC_DYN_RAS = 3;
|
||||
|
||||
/* Active to active command period 66 ns */
|
||||
EMC_DYN_RC = 4;
|
||||
|
||||
/* Use command delayed strategy */
|
||||
EMC_DYN_RD_CFG = 1;
|
||||
|
||||
/* Auto refresh period 66 ns */
|
||||
EMC_DYN_RFC = 4;
|
||||
|
||||
/* Precharge command period 20 ns */
|
||||
EMC_DYN_RP = 1;
|
||||
|
||||
/* Active bank a to active bank b command period 15 ns */
|
||||
EMC_DYN_RRD = 1;
|
||||
|
||||
/* FIXME */
|
||||
EMC_DYN_SREX = 5;
|
||||
|
||||
/* Write recovery time 15 ns */
|
||||
EMC_DYN_WR = 1;
|
||||
|
||||
/* Exit self refresh to active command period 75 ns */
|
||||
EMC_DYN_XSR = 5;
|
||||
|
||||
/* Dynamic Memory 0 settings */
|
||||
|
||||
/*
|
||||
* Use SDRAM, 0 0 001 01 address mapping, disabled buffer, unprotected writes
|
||||
*/
|
||||
EMC_DYN_CFG0 = 0x0280;
|
||||
|
||||
/* CAS and RAS latency */
|
||||
EMC_DYN_RASCAS0 = 0x0202;
|
||||
|
||||
/* Wait 50 micro seconds */
|
||||
lpc24xx_micro_seconds_delay( 50);
|
||||
|
||||
/* Send command: NOP */
|
||||
EMC_DYN_CTRL = EMC_DYN_CTRL_CE | EMC_DYN_CTRL_CS | EMC_DYN_CTRL_CMD_NOP;
|
||||
|
||||
/* Wait 50 micro seconds */
|
||||
lpc24xx_micro_seconds_delay( 50);
|
||||
|
||||
/* Send command: PRECHARGE ALL */
|
||||
EMC_DYN_CTRL = EMC_DYN_CTRL_CE | EMC_DYN_CTRL_CS | EMC_DYN_CTRL_CMD_PALL;
|
||||
|
||||
/* Shortest possible refresh period */
|
||||
EMC_DYN_RFSH = 0x01;
|
||||
|
||||
/* Wait at least 128 ABH clock cycles */
|
||||
for (i = 0; i < 128; ++i) {
|
||||
asm volatile (" nop");
|
||||
}
|
||||
|
||||
/* Wait 1 micro second */
|
||||
lpc24xx_micro_seconds_delay( 1);
|
||||
|
||||
/* Set refresh period */
|
||||
EMC_DYN_RFSH = 0x46;
|
||||
|
||||
/* Send command: MODE */
|
||||
EMC_DYN_CTRL = EMC_DYN_CTRL_CE | EMC_DYN_CTRL_CS | EMC_DYN_CTRL_CMD_MODE;
|
||||
|
||||
/* Set mode registerin SDRAM */
|
||||
mode = *((volatile uint32_t *) (0xa0000000 | (0x23 << (1 + 2 + 8))));
|
||||
|
||||
/* Send command: NORMAL */
|
||||
EMC_DYN_CTRL = 0;
|
||||
|
||||
/* Enable buffer */
|
||||
EMC_DYN_CFG0 |= 0x00080000;
|
||||
|
||||
/* Static Memory 0 settings */
|
||||
EMC_STA_WAITWEN0 = 0x02;
|
||||
EMC_STA_WAITOEN0 = 0x02;
|
||||
EMC_STA_WAITRD0 = 0x1f;
|
||||
EMC_STA_WAITPAGE0 = 0x1f;
|
||||
EMC_STA_WAITWR0 = 0x1f;
|
||||
EMC_STA_WAITTURN0 = 0x0f;
|
||||
EMC_STA_CFG0 = 0x81;
|
||||
|
||||
/* Static Memory 1 settings */
|
||||
EMC_STA_WAITWEN1 = 0x02;
|
||||
EMC_STA_WAITOEN1 = 0x02;
|
||||
EMC_STA_WAITRD1 = 0x08;
|
||||
EMC_STA_WAITPAGE1 = 0x1f;
|
||||
EMC_STA_WAITWR1 = 0x08;
|
||||
EMC_STA_WAITTURN1 = 0x0f;
|
||||
EMC_STA_CFG1 = 0x80;
|
||||
|
||||
/* RAM test */
|
||||
lpc24xx_ram_test_32();
|
||||
#endif /* LPC24XX_EMC_MICRON */
|
||||
}
|
||||
|
||||
static void lpc24xx_init_pll( void)
|
||||
{
|
||||
#ifndef LPC24XX_HAS_UBOOT
|
||||
/* Enable main oscillator */
|
||||
SCS = SET_FLAGS( SCS, 0x20);
|
||||
while (IS_FLAG_CLEARED( SCS, 0x40)) {
|
||||
/* Wait */
|
||||
}
|
||||
|
||||
/* Set PLL */
|
||||
lpc24xx_set_pll( 1, 0, 11, 3);
|
||||
#endif /* LPC24XX_HAS_UBOOT */
|
||||
}
|
||||
|
||||
void /* __attribute__ ((section (".entry"))) */ bsp_start_hook_0( void)
|
||||
{
|
||||
/* Initialize PLL */
|
||||
lpc24xx_init_pll();
|
||||
|
||||
#ifndef LPC24XX_HAS_UBOOT
|
||||
/* Set pin functions */
|
||||
PINSEL0 = 0;
|
||||
PINSEL1 = 0;
|
||||
PINSEL2 = 0;
|
||||
PINSEL3 = 0;
|
||||
PINSEL4 = 0;
|
||||
PINSEL5 = 0;
|
||||
PINSEL6 = 0;
|
||||
PINSEL7 = 0;
|
||||
PINSEL8 = 0;
|
||||
PINSEL9 = 0;
|
||||
PINSEL10 = 0;
|
||||
|
||||
/* Set periperal clocks */
|
||||
PCLKSEL0 = 0;
|
||||
PCLKSEL1 = 0;
|
||||
|
||||
/* Disable power for all modules */
|
||||
PCONP = 0;
|
||||
|
||||
/* Set memory accelerator module (MAM) */
|
||||
MAMCR = 0;
|
||||
MAMTIM = 4;
|
||||
|
||||
/* Set general purpose IO */
|
||||
IODIR0 = 0;
|
||||
IODIR1 = 0;
|
||||
IOSET0 = 0xffffffff;
|
||||
IOSET1 = 0xffffffff;
|
||||
|
||||
/* Set fast IO */
|
||||
FIO0DIR = 0;
|
||||
FIO1DIR = 0;
|
||||
FIO2DIR = 0;
|
||||
FIO3DIR = 0;
|
||||
FIO4DIR = 0;
|
||||
FIO0SET = 0xffffffff;
|
||||
FIO1SET = 0xffffffff;
|
||||
FIO2SET = 0xffffffff;
|
||||
FIO3SET = 0xffffffff;
|
||||
FIO4SET = 0xffffffff;
|
||||
|
||||
/* Initialize UART 0 */
|
||||
PCONP = SET_FLAGS( PCONP, 0x08);
|
||||
PCLKSEL0 = SET_FLAGS( PCLKSEL0, 0x40);
|
||||
PINSEL0 = SET_FLAGS( PINSEL0, 0x50);
|
||||
U0LCR = 0;
|
||||
U0IER = 0;
|
||||
U0LCR = 0x80;
|
||||
U0DLL = lpc24xx_cclk() / 16 / LPC24XX_UART_BAUD;
|
||||
U0DLM = 0;
|
||||
U0LCR = 0x03;
|
||||
U0FCR = 0x07;
|
||||
|
||||
/* Initialize Timer 1 */
|
||||
PCONP = SET_FLAGS( PCONP, 0x04);
|
||||
PCLKSEL0 = SET_FLAGS( PCLKSEL0, 0x10);
|
||||
#endif /* LPC24XX_HAS_UBOOT */
|
||||
}
|
||||
|
||||
static void lpc24xx_copy_data( void)
|
||||
{
|
||||
#ifndef LPC24XX_HAS_UBOOT
|
||||
unsigned *in = bsp_section_text_end;
|
||||
unsigned *out = bsp_section_data_start;
|
||||
|
||||
/* Copy data */
|
||||
while (out < bsp_section_data_end) {
|
||||
*out = *in;
|
||||
++out;
|
||||
++in;
|
||||
}
|
||||
#endif /* LPC24XX_HAS_UBOOT */
|
||||
}
|
||||
|
||||
static void lpc24xx_clear_bss( void)
|
||||
{
|
||||
unsigned *out = bsp_section_bss_start;
|
||||
|
||||
/* Clear BSS */
|
||||
while (out < bsp_section_bss_end) {
|
||||
*out = 0;
|
||||
++out;
|
||||
}
|
||||
}
|
||||
|
||||
void /* __attribute__ ((section (".entry"))) */ bsp_start_hook_1( void)
|
||||
{
|
||||
/* Re-map interrupt vectors to internal RAM */
|
||||
MEMMAP = SET_MEMMAP_MAP( MEMMAP, 2);
|
||||
|
||||
/* Initialize External Memory Controller (EMC) */
|
||||
lpc24xx_init_emc();
|
||||
|
||||
/* Copy data */
|
||||
lpc24xx_copy_data();
|
||||
|
||||
/* Clear BSS */
|
||||
lpc24xx_clear_bss();
|
||||
}
|
||||
|
||||
void bsp_start( void)
|
||||
{
|
||||
printk( "CPU Clock: %u\n", lpc24xx_cclk());
|
||||
printk( "CPU clock (CCLK): %u\n", lpc24xx_cclk());
|
||||
|
||||
/* Exceptions */
|
||||
rtems_exception_init_mngt();
|
||||
@@ -57,10 +320,8 @@ void bsp_start( void)
|
||||
/* Interrupts */
|
||||
if (bsp_interrupt_initialize() != RTEMS_SUCCESSFUL) {
|
||||
/* FIXME */
|
||||
printk( "Cannot intitialize interrupt support\n");
|
||||
while (1) {
|
||||
/* Spin forever */
|
||||
}
|
||||
printk( "cannot intitialize interrupt support\n");
|
||||
lpc24xx_fatal_error();
|
||||
}
|
||||
|
||||
/* DMA */
|
||||
|
||||
@@ -21,6 +21,11 @@
|
||||
|
||||
#ifndef ASM
|
||||
|
||||
/**
|
||||
* @brief System start entry.
|
||||
*/
|
||||
void start( void);
|
||||
|
||||
/**
|
||||
* @brief Start entry hook 0.
|
||||
*
|
||||
|
||||
@@ -27,14 +27,7 @@
|
||||
/* Global symbols */
|
||||
|
||||
.globl start
|
||||
|
||||
.globl Reset_Handler
|
||||
.globl Undefined_Handler
|
||||
.globl SWI_Handler
|
||||
.globl Prefetch_Handler
|
||||
.globl Abort_Handler
|
||||
.globl IRQ_Handler
|
||||
.globl FIQ_Handler
|
||||
|
||||
/* Program Status Register definitions */
|
||||
|
||||
@@ -49,9 +42,61 @@
|
||||
.equ PSR_F, 0x40
|
||||
.equ PSR_T, 0x20
|
||||
|
||||
.section ".entry"
|
||||
|
||||
/*
|
||||
* This is the exception vector table and the pointers to the default
|
||||
* exceptions handlers.
|
||||
*/
|
||||
|
||||
vector_block:
|
||||
|
||||
ldr pc, handler_addr_reset
|
||||
ldr pc, handler_addr_undef
|
||||
ldr pc, handler_addr_swi
|
||||
ldr pc, handler_addr_prefetch
|
||||
ldr pc, handler_addr_abort
|
||||
|
||||
/* Program signature checked by boot loader */
|
||||
.word 0xb8a06f58
|
||||
|
||||
ldr pc, handler_addr_irq
|
||||
ldr pc, handler_addr_fiq
|
||||
|
||||
handler_addr_reset:
|
||||
|
||||
.word start
|
||||
|
||||
handler_addr_undef:
|
||||
|
||||
.word twiddle
|
||||
|
||||
handler_addr_swi:
|
||||
|
||||
.word twiddle
|
||||
|
||||
handler_addr_prefetch:
|
||||
|
||||
.word twiddle
|
||||
|
||||
handler_addr_abort:
|
||||
|
||||
.word twiddle
|
||||
|
||||
handler_addr_reserved:
|
||||
|
||||
.word twiddle
|
||||
|
||||
handler_addr_irq:
|
||||
|
||||
.word twiddle
|
||||
|
||||
handler_addr_fiq:
|
||||
|
||||
.word twiddle
|
||||
|
||||
/* Start entry */
|
||||
|
||||
.section ".entry"
|
||||
start:
|
||||
|
||||
/*
|
||||
@@ -112,7 +157,7 @@ start:
|
||||
* vectors and the pointers to the default exception handlers.
|
||||
*/
|
||||
|
||||
mov r0, #0
|
||||
ldr r0, =bsp_section_vector_start
|
||||
adr r1, vector_block
|
||||
ldmia r1!, {r2-r9}
|
||||
stmia r0!, {r2-r9}
|
||||
@@ -131,52 +176,8 @@ start:
|
||||
|
||||
/* Spin forever */
|
||||
|
||||
SWI_Handler:
|
||||
|
||||
twiddle:
|
||||
|
||||
b twiddle
|
||||
|
||||
/*
|
||||
* This is the exception vector table and the pointers to the default
|
||||
* exceptions handlers.
|
||||
*/
|
||||
|
||||
vector_block:
|
||||
|
||||
ldr pc, Reset_Handler
|
||||
ldr pc, Undefined_Handler
|
||||
ldr pc, SWI_Handler
|
||||
ldr pc, Prefetch_Handler
|
||||
ldr pc, Abort_Handler
|
||||
nop
|
||||
ldr pc, IRQ_Handler
|
||||
ldr pc, FIQ_Handler
|
||||
|
||||
Reset_Handler:
|
||||
|
||||
b bsp_reset
|
||||
|
||||
Undefined_Handler:
|
||||
|
||||
b Undefined_Handler
|
||||
|
||||
SWI_Handler:
|
||||
|
||||
b SWI_Handler
|
||||
|
||||
Prefetch_Handler:
|
||||
|
||||
b Prefetch_Handler
|
||||
|
||||
Abort_Handler:
|
||||
|
||||
b Abort_Handler
|
||||
|
||||
nop
|
||||
|
||||
IRQ_Handler:
|
||||
|
||||
b IRQ_Handler
|
||||
|
||||
FIQ_Handler:
|
||||
|
||||
b FIQ_Handler
|
||||
|
||||
@@ -1,3 +1,8 @@
|
||||
2009-02-27 Sebastian Huber <sebastian.huber@embedded-brains.de>
|
||||
|
||||
* include/utility.h: Added define.
|
||||
* include/irq-generic.h: Added missing prototypes.
|
||||
|
||||
2009-02-11 Joel Sherrill <joel.sherrill@oarcorp.com>
|
||||
|
||||
* tod.c: Use rtems_clock_get_tod().
|
||||
|
||||
@@ -146,7 +146,7 @@ static inline bool bsp_interrupt_is_valid_vector( rtems_vector_number vector)
|
||||
*/
|
||||
void bsp_interrupt_handler_default( rtems_vector_number vector);
|
||||
|
||||
rtems_status_code bsp_interrupt_initialize();
|
||||
rtems_status_code bsp_interrupt_initialize( void);
|
||||
|
||||
/**
|
||||
* @brief BSP specific initialization.
|
||||
@@ -163,7 +163,7 @@ rtems_status_code bsp_interrupt_initialize();
|
||||
*
|
||||
* @return On success RTEMS_SUCCESSFUL shall be returned.
|
||||
*/
|
||||
rtems_status_code bsp_interrupt_facility_initialize();
|
||||
rtems_status_code bsp_interrupt_facility_initialize( void);
|
||||
|
||||
/**
|
||||
* @brief Enables the interrupt vector with number @a vector.
|
||||
|
||||
@@ -41,6 +41,9 @@ extern "C" {
|
||||
#define ARE_FLAGS_SET( val, flags) \
|
||||
(((val) & (flags)) == (flags))
|
||||
|
||||
#define IS_ANY_FLAG_SET( val, flags) \
|
||||
(((val) & (flags)) != 0)
|
||||
|
||||
#define ARE_FLAGS_CLEARED( val, flags) \
|
||||
(((val) & (flags)) == 0)
|
||||
|
||||
|
||||
@@ -4,20 +4,13 @@
|
||||
# $Id$
|
||||
#
|
||||
|
||||
include $(RTEMS_ROOT)/make/custom/default.cfg
|
||||
LPC24XX_LINKCMDS = linkcmds.lpc2478
|
||||
|
||||
RTEMS_CPU = arm
|
||||
RTEMS_BSP_FAMILY = lpc24xx
|
||||
include $(RTEMS_ROOT)/make/custom/lpc24xx.cfg
|
||||
|
||||
CPU_CFLAGS = -mcpu=arm7tdmi -mstructure-size-boundary=8 -mapcs-frame
|
||||
|
||||
CFLAGS_OPTIMIZE_V = -Os -g
|
||||
|
||||
define bsp-post-link
|
||||
$(OBJCOPY) -O binary '$@' '$(basename $@).bin'
|
||||
gzip -f -9 '$(basename $@).bin'
|
||||
# mkimage -A arm -O rtems -T kernel -C gzip \
|
||||
# -a a0000000 -e a0000000 -name '$(notdir $@)' \
|
||||
# -d '$(basename $@).bin.gz' '$(basename $@).img'
|
||||
$(default-bsp-post-link)
|
||||
endef
|
||||
# define bsp-post-link
|
||||
# $(OBJCOPY) -O binary '$@' '$(basename $@).bin'
|
||||
# gzip -f -9 '$(basename $@).bin'
|
||||
# mkimage -A arm -O rtems -T kernel -C gzip -a a0000000 -e a0000040 -name '$(notdir $@)' -d '$(basename $@).bin.gz' '$(basename $@).img'
|
||||
# $(default-bsp-post-link)
|
||||
# endef
|
||||
|
||||
Reference in New Issue
Block a user