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Using defines instead of linker symbols for IO device addresses

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This commit is contained in:
Stefan Hepp
2015-06-23 01:12:13 +02:00
parent 32175e9a6f
commit 0b58689f36
7 changed files with 59 additions and 75 deletions
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40
c/src/lib/libbsp/patmos/pasim/include/pasim.h
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@@ -39,14 +39,13 @@ typedef _IODEV unsigned int volatile * const _iodev_ptr_t;
/* /*
* CPU Info Management * CPU Info Management
*/ */
#define __PATMOS_CPUINFO_BASE 0xF0000000
extern char _cpuinfo_base; /* linker symbol giving the address of the CPU info */
/* Address to access the CPU id */ /* Address to access the CPU id */
#define __PATMOS_CPU_ID_ADDR (&_cpuinfo_base + 0x00) #define __PATMOS_CPU_ID_ADDR (__PATMOS_CPUINFO_BASE + 0x00)
/* Address to access the CPU frequency */ /* Address to access the CPU frequency */
#define __PATMOS_CPU_FREQ_ADDR (&_cpuinfo_base + 0x04) #define __PATMOS_CPU_FREQ_ADDR (__PATMOS_CPUINFO_BASE + 0x04)
/* Macro to read the CPU id */ /* Macro to read the CPU id */
#define __PATMOS_CPU_RD_ID(res) res = *((_iodev_ptr_t)__PATMOS_CPU_ID_ADDR); #define __PATMOS_CPU_RD_ID(res) res = *((_iodev_ptr_t)__PATMOS_CPU_ID_ADDR);
@@ -62,10 +61,7 @@ extern char _cpuinfo_base; /* linker symbol giving the address of the CPU info *
/* /*
* UART Management * UART Management
*/ */
#define __PATMOS_UART_BASE 0xF0080000
extern char _iomap_base; /* linker symbol giving the base address of the IO map address range */
extern char _uart_base; /* linker symbol giving the address of the UART */
/* /*
* The following defines the bits in the PASIM UART Status Registers. * The following defines the bits in the PASIM UART Status Registers.
@@ -79,12 +75,12 @@ extern char _uart_base; /* linker symbol giving the address of the UART */
/* /*
* Address to access the status register of the UART coming with Patmos * Address to access the status register of the UART coming with Patmos
*/ */
#define __PATMOS_UART_STATUS_ADDR (&_uart_base + 0x00) #define __PATMOS_UART_STATUS_ADDR (__PATMOS_UART_BASE + 0x00)
/* /*
* Address to access the data register of the UART coming with Patmos * Address to access the data register of the UART coming with Patmos
*/ */
#define __PATMOS_UART_DATA_ADDR (&_uart_base + 0x04) #define __PATMOS_UART_DATA_ADDR (__PATMOS_UART_BASE + 0x04)
/* /*
@@ -111,25 +107,25 @@ extern char _uart_base; /* linker symbol giving the address of the UART */
/* /*
* RTC Management * RTC Management
*/ */
#define __PATMOS_TIMER_BASE 0xF0020000
extern char _timer_base; /* linker symbol giving the address of the RTC */ #define __PATMOS_EXCUNIT_BASE 0xF0010000
extern uint64_t get_cpu_usecs (void); extern uint64_t get_cpu_usecs (void);
/* Address to access the cycle counter low register of the RTC */ /* Address to access the cycle counter low register of the RTC */
#define __PATMOS_RTC_CYCLE_LOW_ADDR (&_timer_base + 0x04) #define __PATMOS_RTC_CYCLE_LOW_ADDR (__PATMOS_TIMER_BASE + 0x04)
/* Address to access the cycle counter up register of the RTC */ /* Address to access the cycle counter up register of the RTC */
#define __PATMOS_RTC_CYCLE_UP_ADDR (&_timer_base + 0x00) #define __PATMOS_RTC_CYCLE_UP_ADDR (__PATMOS_TIMER_BASE + 0x00)
/* Address to access the time in microseconds low register of the RTC */ /* Address to access the time in microseconds low register of the RTC */
#define __PATMOS_RTC_TIME_LOW_ADDR (&_timer_base + 0x0C) #define __PATMOS_RTC_TIME_LOW_ADDR (__PATMOS_TIMER_BASE + 0x0C)
/* Address to access the time in microseconds up register of the RTC */ /* Address to access the time in microseconds up register of the RTC */
#define __PATMOS_RTC_TIME_UP_ADDR (&_timer_base + 0x08) #define __PATMOS_RTC_TIME_UP_ADDR (__PATMOS_TIMER_BASE + 0x08)
/* Address to access the ISR address register of the RTC cycle timer */ /* Address to access the ISR address register of the RTC cycle timer */
#define __PATMOS_RTC_ISR_ADDR (&_excunit_base + 0xc0) #define __PATMOS_RTC_ISR_ADDR (__PATMOS_EXCUNIT_BASE + 0xc0)
/* Macro to read the RTC's cycle counter low register of the RTC */ /* Macro to read the RTC's cycle counter low register of the RTC */
#define __PATMOS_RTC_RD_CYCLE_LOW(res) res = *((_iodev_ptr_t)__PATMOS_RTC_CYCLE_LOW_ADDR); #define __PATMOS_RTC_RD_CYCLE_LOW(res) res = *((_iodev_ptr_t)__PATMOS_RTC_CYCLE_LOW_ADDR);
@@ -161,19 +157,17 @@ extern uint64_t get_cpu_usecs (void);
* Exception Management * Exception Management
*/ */
extern char _excunit_base; /* linker symbol giving the base address of the exception handling unit */
/* The status register of the exception unit */ /* The status register of the exception unit */
#define EXC_STATUS (*((_iodev_ptr_t)(&_excunit_base+0x00))) #define EXC_STATUS (*((_iodev_ptr_t)(__PATMOS_EXCUNIT_BASE+0x00)))
/* The interrupt mask register */ /* The interrupt mask register */
#define EXC_MASK (*((_iodev_ptr_t)(&_excunit_base+0x04))) #define EXC_MASK (*((_iodev_ptr_t)(__PATMOS_EXCUNIT_BASE+0x04)))
/* The pending interrupts register */ /* The pending interrupts register */
#define EXC_PEND (*((_iodev_ptr_t)(&_excunit_base+0x08))) #define EXC_PEND (*((_iodev_ptr_t)(__PATMOS_EXCUNIT_BASE+0x08)))
/* The exception source register */ /* The exception source register */
#define EXC_SOURCE (*((_iodev_ptr_t)(&_excunit_base+0x0c))) #define EXC_SOURCE (*((_iodev_ptr_t)(__PATMOS_EXCUNIT_BASE+0x0c)))
/* /*
* End of Exception Management * End of Exception Management

4
c/src/lib/libbsp/patmos/shared/clock/ckinit.c
View File

@@ -234,7 +234,7 @@ rtems_isr Clock_isr(
"i" (ISR_r30_OFFSET), "i" (ISR_ssize_OFFSET), "i" (ISR_s0_OFFSET), "i" (ISR_s1_OFFSET), "i" (ISR_s2_OFFSET), "i" (ISR_r30_OFFSET), "i" (ISR_ssize_OFFSET), "i" (ISR_s0_OFFSET), "i" (ISR_s1_OFFSET), "i" (ISR_s2_OFFSET),
"i" (ISR_s3_OFFSET), "i" (ISR_s4_OFFSET), "i" (ISR_s6_OFFSET), "i" (ISR_s7_OFFSET), "i" (ISR_s8_OFFSET), "i" (ISR_s3_OFFSET), "i" (ISR_s4_OFFSET), "i" (ISR_s6_OFFSET), "i" (ISR_s7_OFFSET), "i" (ISR_s8_OFFSET),
"i" (ISR_s9_OFFSET), "i" (ISR_s10_OFFSET), "i" (ISR_s11_OFFSET), "i" (ISR_s12_OFFSET), "i" (ISR_s13_OFFSET), "i" (ISR_s9_OFFSET), "i" (ISR_s10_OFFSET), "i" (ISR_s11_OFFSET), "i" (ISR_s12_OFFSET), "i" (ISR_s13_OFFSET),
"i" (ISR_s14_OFFSET), "i" (ISR_s15_OFFSET), "i" (&_excunit_base), "i" (ISR_exc_OFFSET)); "i" (ISR_s14_OFFSET), "i" (ISR_s15_OFFSET), "i" (__PATMOS_EXCUNIT_BASE), "i" (ISR_exc_OFFSET));
Clock_isr_no_inline(); Clock_isr_no_inline();
@@ -320,7 +320,7 @@ rtems_isr Clock_isr(
"i" (ISR_s2_OFFSET), "i" (ISR_s3_OFFSET), "i" (ISR_s4_OFFSET), "i" (ISR_s6_OFFSET), "i" (ISR_s7_OFFSET), "i" (ISR_s2_OFFSET), "i" (ISR_s3_OFFSET), "i" (ISR_s4_OFFSET), "i" (ISR_s6_OFFSET), "i" (ISR_s7_OFFSET),
"i" (ISR_s8_OFFSET), "i" (ISR_s9_OFFSET), "i" (ISR_s10_OFFSET), "i" (ISR_s11_OFFSET), "i" (ISR_s12_OFFSET), "i" (ISR_s8_OFFSET), "i" (ISR_s9_OFFSET), "i" (ISR_s10_OFFSET), "i" (ISR_s11_OFFSET), "i" (ISR_s12_OFFSET),
"i" (ISR_s13_OFFSET), "i" (ISR_s14_OFFSET), "i" (ISR_s15_OFFSET), "i" (ISR_ssize_OFFSET), "i" (ISR_exc_OFFSET), "i" (ISR_s13_OFFSET), "i" (ISR_s14_OFFSET), "i" (ISR_s15_OFFSET), "i" (ISR_ssize_OFFSET), "i" (ISR_exc_OFFSET),
"i" (&_excunit_base), "i" (ISR_r1_OFFSET), "i" (ISR_r2_OFFSET), "i" (ISR_CONTEXT_CONTROL_SIZE)); "i" (__PATMOS_EXCUNIT_BASE), "i" (ISR_r1_OFFSET), "i" (ISR_r2_OFFSET), "i" (ISR_CONTEXT_CONTROL_SIZE));
} }

4
c/src/lib/libbsp/patmos/shared/startup/start.S
View File

@@ -34,7 +34,7 @@ SYM(hard_reset):
/* /*
* save loader return information * save loader return information
*/ */
li $r1 = _cpuinfo_base li $r1 = __PATMOS_CPUINFO_BASE
lwl $r1 = [$r1] lwl $r1 = [$r1]
mfs $r29 = $srb mfs $r29 = $srb
shadd2 $r2 = $r1, _loader_baseaddr shadd2 $r2 = $r1, _loader_baseaddr
@@ -114,7 +114,7 @@ SYM(hard_reset):
PUBLIC(__exit) PUBLIC(__exit)
SYM(__exit): SYM(__exit):
li $r1 = _cpuinfo_base li $r1 = __PATMOS_CPUINFO_BASE
lwl $r1 = [$r1] lwl $r1 = [$r1]
nop nop
shadd2 $r2 = $r1, _loader_baseaddr shadd2 $r2 = $r1, _loader_baseaddr

40
c/src/lib/libbsp/patmos/tcrest/include/tcrest.h
View File

@@ -55,14 +55,13 @@ typedef volatile int (*entrypoint_t)(void);
/* /*
* CPU Info Management * CPU Info Management
*/ */
#define __PATMOS_CPUINFO_BASE 0xF0000000
extern char _cpuinfo_base; /* linker symbol giving the address of the CPU info */
/* Address to access the CPU id */ /* Address to access the CPU id */
#define __PATMOS_CPU_ID_ADDR (&_cpuinfo_base + 0x00) #define __PATMOS_CPU_ID_ADDR (__PATMOS_CPUINFO_BASE + 0x00)
/* Address to access the CPU frequency */ /* Address to access the CPU frequency */
#define __PATMOS_CPU_FREQ_ADDR (&_cpuinfo_base + 0x04) #define __PATMOS_CPU_FREQ_ADDR (__PATMOS_CPUINFO_BASE + 0x04)
/* Macro to read the CPU id */ /* Macro to read the CPU id */
#define __PATMOS_CPU_RD_ID(res) res = *((_iodev_ptr_t)__PATMOS_CPU_ID_ADDR); #define __PATMOS_CPU_RD_ID(res) res = *((_iodev_ptr_t)__PATMOS_CPU_ID_ADDR);
@@ -78,10 +77,7 @@ extern char _cpuinfo_base; /* linker symbol giving the address of the CPU info *
/* /*
* UART Management * UART Management
*/ */
#define __PATMOS_UART_BASE 0xF0080000
extern char _iomap_base; /* linker symbol giving the base address of the IO map address range */
extern char _uart_base; /* linker symbol giving the address of the UART */
/* /*
* The following defines the bits in the TCREST UART Status Registers. * The following defines the bits in the TCREST UART Status Registers.
@@ -95,12 +91,12 @@ extern char _uart_base; /* linker symbol giving the address of the UART */
/* /*
* Address to access the status register of the UART coming with Patmos * Address to access the status register of the UART coming with Patmos
*/ */
#define __PATMOS_UART_STATUS_ADDR (&_uart_base + 0x00) #define __PATMOS_UART_STATUS_ADDR (__PATMOS_UART_BASE + 0x00)
/* /*
* Address to access the data register of the UART coming with Patmos * Address to access the data register of the UART coming with Patmos
*/ */
#define __PATMOS_UART_DATA_ADDR (&_uart_base + 0x04) #define __PATMOS_UART_DATA_ADDR (__PATMOS_UART_BASE + 0x04)
/* /*
@@ -127,25 +123,25 @@ extern char _uart_base; /* linker symbol giving the address of the UART */
/* /*
* RTC Management * RTC Management
*/ */
#define __PATMOS_TIMER_BASE 0xF0020000
extern char _timer_base; /* linker symbol giving the address of the RTC */ #define __PATMOS_EXCUNIT_BASE 0xF0010000
extern uint64_t get_cpu_usecs (void); extern uint64_t get_cpu_usecs (void);
/* Address to access the cycle counter low register of the RTC */ /* Address to access the cycle counter low register of the RTC */
#define __PATMOS_RTC_CYCLE_LOW_ADDR (&_timer_base + 0x04) #define __PATMOS_RTC_CYCLE_LOW_ADDR (__PATMOS_TIMER_BASE + 0x04)
/* Address to access the cycle counter up register of the RTC */ /* Address to access the cycle counter up register of the RTC */
#define __PATMOS_RTC_CYCLE_UP_ADDR (&_timer_base + 0x00) #define __PATMOS_RTC_CYCLE_UP_ADDR (__PATMOS_TIMER_BASE + 0x00)
/* Address to access the time in microseconds low register of the RTC */ /* Address to access the time in microseconds low register of the RTC */
#define __PATMOS_RTC_TIME_LOW_ADDR (&_timer_base + 0x0C) #define __PATMOS_RTC_TIME_LOW_ADDR (__PATMOS_TIMER_BASE + 0x0C)
/* Address to access the time in microseconds up register of the RTC */ /* Address to access the time in microseconds up register of the RTC */
#define __PATMOS_RTC_TIME_UP_ADDR (&_timer_base + 0x08) #define __PATMOS_RTC_TIME_UP_ADDR (__PATMOS_TIMER_BASE + 0x08)
/* Address to access the ISR address register of the RTC cycle timer */ /* Address to access the ISR address register of the RTC cycle timer */
#define __PATMOS_RTC_ISR_ADDR (&_excunit_base + 0xc0) #define __PATMOS_RTC_ISR_ADDR (__PATMOS_EXCUNIT_BASE + 0xc0)
/* Macro to read the RTC's cycle counter low register of the RTC */ /* Macro to read the RTC's cycle counter low register of the RTC */
#define __PATMOS_RTC_RD_CYCLE_LOW(res) res = *((_iodev_ptr_t)__PATMOS_RTC_CYCLE_LOW_ADDR); #define __PATMOS_RTC_RD_CYCLE_LOW(res) res = *((_iodev_ptr_t)__PATMOS_RTC_CYCLE_LOW_ADDR);
@@ -177,19 +173,17 @@ extern uint64_t get_cpu_usecs (void);
* Exception Management * Exception Management
*/ */
extern char _excunit_base; /* linker symbol giving the base address of the exception handling unit */
/* The status register of the exception unit */ /* The status register of the exception unit */
#define EXC_STATUS (*((_iodev_ptr_t)(&_excunit_base+0x00))) #define EXC_STATUS (*((_iodev_ptr_t)(__PATMOS_EXCUNIT_BASE+0x00)))
/* The interrupt mask register */ /* The interrupt mask register */
#define EXC_MASK (*((_iodev_ptr_t)(&_excunit_base+0x04))) #define EXC_MASK (*((_iodev_ptr_t)(__PATMOS_EXCUNIT_BASE+0x04)))
/* The pending interrupts register */ /* The pending interrupts register */
#define EXC_PEND (*((_iodev_ptr_t)(&_excunit_base+0x08))) #define EXC_PEND (*((_iodev_ptr_t)(__PATMOS_EXCUNIT_BASE+0x08)))
/* The exception source register */ /* The exception source register */
#define EXC_SOURCE (*((_iodev_ptr_t)(&_excunit_base+0x0c))) #define EXC_SOURCE (*((_iodev_ptr_t)(__PATMOS_EXCUNIT_BASE+0x0c)))
/* /*
* End of Exception Management * End of Exception Management

38
c/src/lib/libbsp/patmos/tcrestmp/include/tcrestmp.h
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@@ -55,14 +55,13 @@ typedef volatile int (*entrypoint_t)(void);
/* /*
* CPU Info Management * CPU Info Management
*/ */
#define __PATMOS_CPUINFO_BASE 0xF0000000
extern char _cpuinfo_base; /* linker symbol giving the address of the CPU info */
/* Address to access the CPU id */ /* Address to access the CPU id */
#define __PATMOS_CPU_ID_ADDR (&_cpuinfo_base + 0x00) #define __PATMOS_CPU_ID_ADDR (__PATMOS_CPUINFO_BASE + 0x00)
/* Address to access the CPU frequency */ /* Address to access the CPU frequency */
#define __PATMOS_CPU_FREQ_ADDR (&_cpuinfo_base + 0x04) #define __PATMOS_CPU_FREQ_ADDR (__PATMOS_CPUINFO_BASE + 0x04)
/* Macro to read the CPU id */ /* Macro to read the CPU id */
#define __PATMOS_CPU_RD_ID(res) res = *((_iodev_ptr_t)__PATMOS_CPU_ID_ADDR); #define __PATMOS_CPU_RD_ID(res) res = *((_iodev_ptr_t)__PATMOS_CPU_ID_ADDR);
@@ -78,10 +77,7 @@ extern char _cpuinfo_base; /* linker symbol giving the address of the CPU info *
/* /*
* UART Management * UART Management
*/ */
#define __PATMOS_UART_BASE 0xF0080000
extern char _iomap_base; /* linker symbol giving the base address of the IO map address range */
extern char _uart_base; /* linker symbol giving the address of the UART */
/* /*
* The following defines the bits in the TCREST UART Status Registers. * The following defines the bits in the TCREST UART Status Registers.
@@ -95,12 +91,12 @@ extern char _uart_base; /* linker symbol giving the address of the UART */
/* /*
* Address to access the status register of the UART coming with Patmos * Address to access the status register of the UART coming with Patmos
*/ */
#define __PATMOS_UART_STATUS_ADDR (&_uart_base + 0x00) #define __PATMOS_UART_STATUS_ADDR (__PATMOS_UART_BASE + 0x00)
/* /*
* Address to access the data register of the UART coming with Patmos * Address to access the data register of the UART coming with Patmos
*/ */
#define __PATMOS_UART_DATA_ADDR (&_uart_base + 0x04) #define __PATMOS_UART_DATA_ADDR (__PATMOS_UART_BASE + 0x04)
/* /*
@@ -128,24 +124,25 @@ extern char _uart_base; /* linker symbol giving the address of the UART */
* RTC Management * RTC Management
*/ */
extern char _timer_base; /* linker symbol giving the address of the RTC */ #define __PATMOS_TIMER_BASE 0xF0020000
#define __PATMOS_EXCUNIT_BASE 0xF0010000
extern uint64_t get_cpu_usecs (void); extern uint64_t get_cpu_usecs (void);
/* Address to access the cycle counter low register of the RTC */ /* Address to access the cycle counter low register of the RTC */
#define __PATMOS_RTC_CYCLE_LOW_ADDR (&_timer_base + 0x04) #define __PATMOS_RTC_CYCLE_LOW_ADDR (__PATMOS_TIMER_BASE + 0x04)
/* Address to access the cycle counter up register of the RTC */ /* Address to access the cycle counter up register of the RTC */
#define __PATMOS_RTC_CYCLE_UP_ADDR (&_timer_base + 0x00) #define __PATMOS_RTC_CYCLE_UP_ADDR (__PATMOS_TIMER_BASE + 0x00)
/* Address to access the time in microseconds low register of the RTC */ /* Address to access the time in microseconds low register of the RTC */
#define __PATMOS_RTC_TIME_LOW_ADDR (&_timer_base + 0x0C) #define __PATMOS_RTC_TIME_LOW_ADDR (__PATMOS_TIMER_BASE + 0x0C)
/* Address to access the time in microseconds up register of the RTC */ /* Address to access the time in microseconds up register of the RTC */
#define __PATMOS_RTC_TIME_UP_ADDR (&_timer_base + 0x08) #define __PATMOS_RTC_TIME_UP_ADDR (__PATMOS_TIMER_BASE + 0x08)
/* Address to access the ISR address register of the RTC cycle timer */ /* Address to access the ISR address register of the RTC cycle timer */
#define __PATMOS_RTC_ISR_ADDR (&_excunit_base + 0xc0) #define __PATMOS_RTC_ISR_ADDR (__PATMOS_EXCUNIT_BASE + 0xc0)
/* Macro to read the RTC's cycle counter low register of the RTC */ /* Macro to read the RTC's cycle counter low register of the RTC */
#define __PATMOS_RTC_RD_CYCLE_LOW(res) res = *((_iodev_ptr_t)__PATMOS_RTC_CYCLE_LOW_ADDR); #define __PATMOS_RTC_RD_CYCLE_LOW(res) res = *((_iodev_ptr_t)__PATMOS_RTC_CYCLE_LOW_ADDR);
@@ -177,19 +174,18 @@ extern uint64_t get_cpu_usecs (void);
* Exception Management * Exception Management
*/ */
extern char _excunit_base; /* linker symbol giving the base address of the exception handling unit */
/* The status register of the exception unit */ /* The status register of the exception unit */
#define EXC_STATUS (*((_iodev_ptr_t)(&_excunit_base+0x00))) #define EXC_STATUS (*((_iodev_ptr_t)(__PATMOS_EXCUNIT_BASE+0x00)))
/* The interrupt mask register */ /* The interrupt mask register */
#define EXC_MASK (*((_iodev_ptr_t)(&_excunit_base+0x04))) #define EXC_MASK (*((_iodev_ptr_t)(__PATMOS_EXCUNIT_BASE+0x04)))
/* The pending interrupts register */ /* The pending interrupts register */
#define EXC_PEND (*((_iodev_ptr_t)(&_excunit_base+0x08))) #define EXC_PEND (*((_iodev_ptr_t)(__PATMOS_EXCUNIT_BASE+0x08)))
/* The exception source register */ /* The exception source register */
#define EXC_SOURCE (*((_iodev_ptr_t)(&_excunit_base+0x0c))) #define EXC_SOURCE (*((_iodev_ptr_t)(__PATMOS_EXCUNIT_BASE+0x0c)))
/* /*
* End of Exception Management * End of Exception Management

2
c/src/lib/libcpu/patmos/exceptions/exceptions.h
View File

@@ -22,7 +22,7 @@ typedef void (*exc_handler_t)(void);
/* /*
* The exception vector array * The exception vector array
*/ */
#define EXC_VEC(I) (((_IODEV exc_handler_t volatile * const)(&_excunit_base+0x80))[I]) #define EXC_VEC(I) (((_IODEV exc_handler_t volatile * const)(__PATMOS_EXCUNIT_BASE+0x80))[I])
/* /*
* Various named exception vector entry numbers * Various named exception vector entry numbers

6
cpukit/score/cpu/patmos/cpu.c
View File

@@ -262,7 +262,7 @@ void _CPU_Context_switch(
: : "{$r3}" (run), "i" (s0_OFFSET), "i" (s1_OFFSET), "i" (s2_OFFSET), "i" (s3_OFFSET), : : "{$r3}" (run), "i" (s0_OFFSET), "i" (s1_OFFSET), "i" (s2_OFFSET), "i" (s3_OFFSET),
"i" (s4_OFFSET), "i" (s5_OFFSET), "i" (s6_OFFSET), "i" (s7_OFFSET), "i" (s8_OFFSET), "i" (s4_OFFSET), "i" (s5_OFFSET), "i" (s6_OFFSET), "i" (s7_OFFSET), "i" (s8_OFFSET),
"i" (s9_OFFSET), "i" (s10_OFFSET),"i" (s11_OFFSET), "i" (s12_OFFSET), "i" (s13_OFFSET), "i" (s9_OFFSET), "i" (s10_OFFSET),"i" (s11_OFFSET), "i" (s12_OFFSET), "i" (s13_OFFSET),
"i" (s14_OFFSET), "i" (s15_OFFSET), "i" (&_excunit_base), "i" (exc_OFFSET) "i" (s14_OFFSET), "i" (s15_OFFSET), "i" (__PATMOS_EXCUNIT_BASE), "i" (exc_OFFSET)
// clobber r1 so that the compiler does not use it for %0 // clobber r1 so that the compiler does not use it for %0
: "$r1"); : "$r1");
@@ -357,7 +357,7 @@ void _CPU_Context_switch(
"lwc $r1 = [ %0 + %4 ] \n\t" //load r1 "lwc $r1 = [ %0 + %4 ] \n\t" //load r1
"lwc $r2 = [ %0 + %5 ] \n\t" //load r2 "lwc $r2 = [ %0 + %5 ] \n\t" //load r2
"lwc $r4 = [ %0 + %6 ] \n\t" //load r4 "lwc $r4 = [ %0 + %6 ] \n\t" //load r4
: : "{$r4}" (heir), "i" (ssize_OFFSET), "i" (exc_OFFSET), "i" (&_excunit_base), "i" (r1_OFFSET), : : "{$r4}" (heir), "i" (ssize_OFFSET), "i" (exc_OFFSET), "i" (__PATMOS_EXCUNIT_BASE), "i" (r1_OFFSET),
"i" (r2_OFFSET), "i" (r4_OFFSET)); "i" (r2_OFFSET), "i" (r4_OFFSET));
} }
@@ -457,7 +457,7 @@ void _CPU_Context_restore(
"lwc $r1 = [ %0 + %4 ] \n\t" //load r1 "lwc $r1 = [ %0 + %4 ] \n\t" //load r1
"lwc $r2 = [ %0 + %5 ] \n\t" //load r2 "lwc $r2 = [ %0 + %5 ] \n\t" //load r2
"lwc $r3 = [ %0 + %6 ] \n\t" //load r3 "lwc $r3 = [ %0 + %6 ] \n\t" //load r3
: : "{$r3}" (new_context), "i" (ssize_OFFSET), "i" (exc_OFFSET), "i" (&_excunit_base), "i" (r1_OFFSET), : : "{$r3}" (new_context), "i" (ssize_OFFSET), "i" (exc_OFFSET), "i" (__PATMOS_EXCUNIT_BASE), "i" (r1_OFFSET),
"i" (r2_OFFSET), "i" (r3_OFFSET)); "i" (r2_OFFSET), "i" (r3_OFFSET));
} }