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acef64ed2a
1.Add the necessary function declarations for SMP enablement and implement the corresponding functionalities, including rt_hw_secondary_cpu_up, secondary_cpu_entry, rt_hw_local_irq_disable, rt_hw_local_irq_enable, rt_hw_secondary_cpu_idle_exec, rt_hw_spin_lock_init, rt_hw_spin_lock, rt_hw_spin_unlock, rt_hw_ipi_send, rt_hw_interrupt_set_priority, rt_hw_interrupt_get_priority, rt_hw_ipi_init, rt_hw_ipi_handler_install, and rt_hw_ipi_handler. 2.In the two functions (rt_hw_context_switch_to and rt_hw_context_switch) in context_gcc.S, add a call to rt_cpus_lock_status_restore to update the scheduler information. 3.If the MMU is enabled, use the .percpu section and record different hartids by configuring special page tables; if the MMU is not enabled, record them directly in the satp register. Additionally, add dynamic startup based on core configuration.The .percpu section is only used when both ARCH_MM_MMU and RT_USING_SMP are enabled. However, there is a certain amount of space waste since no macro guard is added for it in the link script currently. 4.The physical memory of QEMU started in CI is 128MB, so RT_HW_PAGE_END is modified from the original +256MB to +128MB. Modify the SConscript file under the common64 directory to include common/atomic_riscv.c in the compilation process. Signed-off-by: Mengchen Teng <teng_mengchen@163.com>
56 lines
960 B
C
56 lines
960 B
C
/*
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* Copyright (c) 2006-2024, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-10-03 Bernard The first version
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*/
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#ifndef CPUPORT_H__
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#define CPUPORT_H__
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#include <rtconfig.h>
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#include <opcode.h>
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#ifndef __ASSEMBLY__
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#ifdef RT_USING_SMP
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typedef union {
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unsigned long slock;
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struct __arch_tickets {
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unsigned short owner;
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unsigned short next;
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} tickets;
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} rt_hw_spinlock_t;
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#endif
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#include <rtcompiler.h>
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rt_inline void rt_hw_dsb(void)
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{
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__asm__ volatile("fence":::"memory");
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}
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rt_inline void rt_hw_dmb(void)
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{
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__asm__ volatile("fence":::"memory");
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}
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rt_inline void rt_hw_isb(void)
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{
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__asm__ volatile(OPC_FENCE_I:::"memory");
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}
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#ifdef ARCH_MM_MMU
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void rt_hw_percpu_hartid_init(rt_ubase_t *percpu_ptr, rt_ubase_t hartid);
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#endif
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#endif
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#endif
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#ifdef RISCV_U_MODE
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#define RISCV_USER_ENTRY 0xFFFFFFE000000000ULL
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#endif
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