The context_gcc.S file was incorrectly marked as cortex-m4 in both the
doxygen comment and .cpu directive, while the IAR and KEIL versions
correctly specify cortex-m33. This file uses ARMv8-M specific features
(PSPLIM register, TrustZone support) that are not available in Cortex-M4.
Changes:
- Update doxygen group from cortex-m4 to cortex-m33
- Change .cpu directive from cortex-m4 to cortex-m33
[cpp_check.py 80 INFO] bsp/w60x/drivers/drv_rtc.c:58:11: error: Syntax Error: AST broken, binary operator '&=' doesn't have two operands. [internalAstError]
[cpp_check.py 80 INFO] libcpu/arm/s3c24x0/rtc.c:34:12: error: Expression 'RTCCON|=RTCCON|=0x01' depends on order of evaluation of side effects [unknownEvaluationOrder]
The boot EL will save in x0, when current EL is EL3,
kernel will jump to the EL2 after EL3.
But the x0 value is **3**, The init for EL2 will not work.
To fix it: the EL3 should jump to the EL2 init branch with not check,
and when SoC boot in EL2, kernel will jump to the EL2 test branch.
Link: https://club.rt-thread.org/ask/question/ec320a6765389f67.html
Signed-off-by: wusongjie <wusongjie@rt-thread.com>
1. Configure the kernel default vaddr by RAM and TEXT offset.
2. Check the p_addr 2M align when set the stride in `rt_hw_mmu_map`.
Signed-off-by: GuEe-GUI <2991707448@qq.com>
libcpu/risc-v/common64/mmu.c uses the external
symbol "__bss_end" (this symbol generally is
defined in the link script file) and depends
on the extern declaration of this symbol in
the bsp's "board.h". This is not a problem in
implementation, but it is not a good habit.
If this extern symbol is used locally, just
declare it locally should be better.
In this way, there will be no dependency of
the kernel core on the bsp header file. And
there will be no special requirements for the
bsp board code, such as the need to make
extern declarations for these "__bss_end"
symbols in "board.h".
This patch currently only explicitly externly
declares "__bss_end" inside libcpu itself.
The code of "#include <board.h>" is kept, because
the modification involved is too large, it is
necessary to clean up the bsp involved before
cleaning this include code line uniformly.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
* libcpu: cleanup undefined rt_hw_mmu_kernel_map_init
rt_hw_mmu_kernel_map_init() is declared in header files but
no definition found, cleanup the code.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
* bsp: allwinner: d1: remove calling of rt_hw_mmu_kernel_map_init
rt_hw_mmu_kernel_map_init is an undefined function, calling it
is meaningless.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
---------
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
This patch introduces a tagged pages allocator to address the existing problems
of page aliasing on specific platforms and the requirement of page coloring.
It implements an affinity-id aware page manager by separating the runtime page
list into two types: a normal single linked-list and a multi-dimensional affinity-list.
Changes:
- Introduced tagged pages allocator and managing algorithm for affinity pages list
- Modified components to support affinity-id list management
- Updated page allocation and freeing functions to handle tagged pages
- Added configuration options for page affinity block size and debugging
- Modified mmap and elf loading to respect affinity settings
- Enhanced page list management to support multi-dimensional affinity-list
Signed-off-by: Shell <smokewood@qq.com>
description: Using the vector instruction set to trigger
an illegal instruction exception when ARCH_SISCV_VECTOR=y.
analysis: When initializing the thread stack,
the rt_cw_stack_init function did not enable VS for SSTATUS.
Solution: When ARCH_SISCV_VECTOR=y,
increment the initial value of sstatus by 0x600(SSTATUS_VS).
Signed-off-by: Liu Gui <kenneth.liu@sophgo.com>
