Commit Graph

1048 Commits

Author SHA1 Message Date
Tang Qingmei
6c2b9a8f20 [libcpu][aarch64] Replace x8 with a callee-saved register 2026-01-13 13:42:26 +08:00
Copilot
570cc03579 [risc-v][common64] Make rt_hw_cpu_shutdown weak to resolve multiple definition with RT_USING_DM (#11100)
* Initial plan

* [risc-v][common64] Make rt_hw_cpu_shutdown weak to fix multiple definition error

Co-authored-by: BernardXiong <1241087+BernardXiong@users.noreply.github.com>

---------

Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com>
Co-authored-by: BernardXiong <1241087+BernardXiong@users.noreply.github.com>
2026-01-12 17:15:42 +08:00
laidene
68a5c6a83b [libcpu][arm][cortex-a] Fixup mmu setup early
Correct the starting virtual address of _reset alignment to 16MB
2026-01-10 13:30:09 +08:00
laidene
9c60c5fb06 Update libcpu/arm/cortex-a/gic.c 2026-01-09 10:19:52 +08:00
laidene
ff5c5eab6b [docs][libcpu][arm][cortex-a] add comment for gic.c 2026-01-09 10:19:52 +08:00
caicunjun
a73f5d1032 [docs][libcpu][arm][cortex-a] add comment for mmu.h (#11104)
* [docs][libcpu][arm][cortex-a] add comment for mmu.h

* [docs][libcpu][arm][cortex-a] beautify comment for mmu.h

* [docs][libcpu][arm][cortex-a] delete extra space at the end of lines
2026-01-04 17:03:20 +08:00
caicunjun
71d802c415 [docs][libcpu][arm][cortex-a] update comment for start_gcc.S #11089 2025-12-26 21:04:23 +08:00
GuEe-GUI
77fbed5744 [libcpu][aarch64] Update for DM
1. PSCI port to system power.
2. Support builtin fdt.
3. Update system aspace size.
4. Support DMA memory probe.
5. Fixup not backtrace in Serror for device bus fault.

Signed-off-by: GuEe-GUI <2991707448@qq.com>
2025-12-19 21:18:54 +08:00
Fan YANG
7330df69f6 update: [libcpu][risc-v][common] allow overriding isr numbers for MCU
- allow overriding the isr numbers via RT_HW_ISR_NUM macro

Signed-off-by: Fan YANG <fan.yang@hpmicro.com>
2025-12-11 17:04:14 +08:00
Tm-C-mT
acef64ed2a [libcpu-riscv]: [surpport SMP]: Add SMP support for qemu-virt64-riscv
1.Add the necessary function declarations for SMP enablement and implement the corresponding
functionalities, including rt_hw_secondary_cpu_up, secondary_cpu_entry, rt_hw_local_irq_disable,
rt_hw_local_irq_enable, rt_hw_secondary_cpu_idle_exec, rt_hw_spin_lock_init, rt_hw_spin_lock,
rt_hw_spin_unlock, rt_hw_ipi_send, rt_hw_interrupt_set_priority, rt_hw_interrupt_get_priority,
rt_hw_ipi_init, rt_hw_ipi_handler_install, and rt_hw_ipi_handler.

2.In the two functions (rt_hw_context_switch_to and rt_hw_context_switch) in context_gcc.S,
add a call to rt_cpus_lock_status_restore to update the scheduler information.

3.If the MMU is enabled, use the .percpu section and record different hartids by configuring
special page tables; if the MMU is not enabled, record them directly in the satp register.
Additionally, add dynamic startup based on core configuration.The .percpu section is only used
when both ARCH_MM_MMU and RT_USING_SMP are enabled. However, there is a certain amount of space
waste since no macro guard is added for it in the link script currently.

4.The physical memory of QEMU started in CI is 128MB, so RT_HW_PAGE_END is modified from the
original +256MB to +128MB. Modify the SConscript file under the common64 directory to include
common/atomic_riscv.c in the compilation process.

Signed-off-by: Mengchen Teng <teng_mengchen@163.com>
2025-12-04 15:42:09 +08:00
Copilot
30e1e5e9dc Reorganize Group names in build system for clarity and IDE integration #10923 2025-11-16 11:40:53 +08:00
Copilot
e525c38cb8 [libcpu][cortex-a] Refactor FPU stack initialization for maintainability (#10919)
* Initial plan

* [libcpu][cortex-a] Improve FPU stack initialization implementation

Co-authored-by: BernardXiong <1241087+BernardXiong@users.noreply.github.com>

* [libcpu][cortex-a] Replace FPU init loop with rt_memset

Co-authored-by: BernardXiong <1241087+BernardXiong@users.noreply.github.com>

---------

Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com>
Co-authored-by: BernardXiong <1241087+BernardXiong@users.noreply.github.com>
2025-11-12 04:34:34 +08:00
Copilot
c631b39317 [Components] Remove vbus component and realview-a8-vmm libcpu (#10863)
* Initial plan

* Remove vbus component and related code

Co-authored-by: BernardXiong <1241087+BernardXiong@users.noreply.github.com>

---------

Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com>
Co-authored-by: BernardXiong <1241087+BernardXiong@users.noreply.github.com>
2025-11-07 17:03:05 +08:00
Yucai Liu
c91a7f46f5 [libcpu/arm/cortex-m33]: Fix incorrect CPU architecture in GCC context switch
The context_gcc.S file was incorrectly marked as cortex-m4 in both the
doxygen comment and .cpu directive, while the IAR and KEIL versions
correctly specify cortex-m33. This file uses ARMv8-M specific features
(PSPLIM register, TrustZone support) that are not available in Cortex-M4.

Changes:
- Update doxygen group from cortex-m4 to cortex-m33
- Change .cpu directive from cortex-m4 to cortex-m33
2025-11-02 16:23:31 +08:00
Yonggang Luo
0cf096e064 aarch64: document the CNTFRQ_EL0
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
2025-10-23 22:08:05 +08:00
Siwei Xu
1efceab071 [aarch64] Fix rt_aspace_init error when KERNEL_VADDR_START >= 0x80000000 2025-10-21 10:12:35 +08:00
Yonggang Luo
27e3460b88 Remove unused rt_hw_set_gtimer_frq 2025-10-13 21:44:36 +08:00
Yonggang Luo
5ae232b6d0 bsp/w60x: fixes cppcheck: (#10781)
[cpp_check.py 80 INFO] bsp/w60x/drivers/drv_rtc.c:58:11: error: Syntax Error: AST broken, binary operator '&=' doesn't have two operands. [internalAstError]

[cpp_check.py 80 INFO] libcpu/arm/s3c24x0/rtc.c:34:12: error: Expression 'RTCCON|=RTCCON|=0x01' depends on order of evaluation of side effects [unknownEvaluationOrder]
2025-10-11 09:28:52 +08:00
Yonggang Luo
62bc4ba774 Remove rarely used rt_time_t
next_delay should be rt_tick_t

Use time_t for RT_DEVICE_CTRL_RTC_GET_TIME
2025-10-10 20:21:40 +08:00
zhangyan
cc72712173 [CPU/AARCH64] 增加 libcpu/aarch64 KERNEL_ASPACE_START 配置 #10757
针对不同的 Aarch64 BSP 针对 KERNEL_VADDR_START 宏定义进行区分
2025-10-10 11:02:28 +08:00
R b b666
2b65a6f2a7 fix:Fixed compilation error for libcpu/cortex-m4. (#10756) 2025-09-28 16:08:02 +08:00
Haojin Tang
893ae7d7ba fix(risc-v, virt64, plic): use volatile rw for claim and complete 2025-09-03 09:48:22 +08:00
Haojin Tang
db4fb4c243 fix(risc-v, mmu): fix type mismatch of _query 2025-09-01 18:44:24 +08:00
Haojin Tang
157d809634 fix(risc-v/virt64, cpp): add spaces to fix Wliteral-suffix 2025-09-01 18:43:04 +08:00
Haojin Tang
b27e405faa fix(riscv, cpp): remove rt_hw_cpu_id in cpuport.h to fix error 2025-09-01 18:42:08 +08:00
maosql
9567564e86 fix: warnings generated by Kconfig. 2025-09-01 11:50:41 +08:00
Rbb666
882d1958dd [libcpu][cortex-m33]Added HardFault_Handler to save floating point registers 2025-08-20 18:17:19 +08:00
Rbb666
990fc23628 [libcpu][cortex-m4]Added HardFault_Handler to save floating point registers. 2025-08-19 21:40:57 +08:00
R b b666
2f19ba6ce7 [libcpu ][cm3]The parameter passed to the unified rt_exception_hook is exception_stack. (#10619) 2025-08-19 21:15:47 +08:00
Yulong Wang
e7a40ae6ec [lwp][rv64] restore tp register in arch_thread_signal_enter to fix user-mode memory access 2025-07-23 09:38:35 +08:00
GuEe-GUI
8a4890a9e5 [ARCH/AARCH64] Update Hypercall API
Signed-off-by: GuEe-GUI <2991707448@qq.com>
2025-07-16 12:52:51 +08:00
GUI
3d72290b38 [aarch64]Fixup linker warning #10466 2025-07-08 14:10:04 +08:00
GuEe-GUI
d698bb487e Fixup the boot EL check
The boot EL will save in x0, when current EL is EL3,
kernel will jump to the EL2 after EL3.
But the x0 value is **3**, The init for EL2 will not work.
To fix it: the EL3 should jump to the EL2 init branch with not check,
and when SoC boot in EL2, kernel will jump to the EL2 test branch.

Link: https://club.rt-thread.org/ask/question/ec320a6765389f67.html

Signed-off-by: wusongjie <wusongjie@rt-thread.com>
2025-07-07 10:58:52 +08:00
GuEe-GUI
a894796566 [CPU/AARCH64] Fixup MMU
1. Configure the kernel default vaddr by RAM and TEXT offset.
2. Check the p_addr 2M align when set the stride in `rt_hw_mmu_map`.

Signed-off-by: GuEe-GUI <2991707448@qq.com>
2025-07-04 16:37:29 +08:00
kurisaw
4f903298a2 libcpu/bsp: fix the M33 assembly syntax errors and fix the compilation error of bsp 2025-06-24 11:04:01 +08:00
ZhangJing
c3d33f39d4 [bsp]增加超睿DP1000 bsp支持 2025-05-30 13:32:58 +08:00
Yaochenger
f4e619a17c 移除无用文件,该文件未被任何BSP使用 2025-05-30 09:32:08 +08:00
Yaochenger
5889db6819 [libcpu/common] 修正对RV32E的支持,RV32E不支持s2寄存器,修改为s1寄存器 2025-05-30 09:32:08 +08:00
zhangjing
e3d7bbb47c [libcpu][risc-v]:add comment for the round down of symb_pc 2025-05-28 19:37:51 +08:00
zhangjing
3922ec7e99 [libcpu][risc-v] fix:only map the 1GB space where the original code segment is located 2025-05-28 19:37:51 +08:00
rcitach
aee8920d07 import re 2025-04-28 10:52:58 +08:00
rcitach
5833e02e2f Fix Aarch64 architecture runtime issues
该问题由5b3320624da5149fc21c2d3e1f321d855e3d0dfe引入,导致工具链编译时加上了 -std=gnu99,其他架构是否出问题暂时未知
2025-04-28 10:52:58 +08:00
mouch6131
86df886c7f libcpu: aarch64: Fix NORMAL_NOCACHE_MEM attr (#10180)
Signed-off-by: Cliff Chen <cliff.chen@rock-chips.com>
Signed-off-by: mouch6131 <187177037@qq.com>
Co-authored-by: Cliff Chen <cliff.chen@rock-chips.com>
2025-04-13 22:12:00 +08:00
Chen Wang
312f9dbc08 libcpu: riscv: declare external symbols inside
libcpu/risc-v/common64/mmu.c uses the external
symbol "__bss_end" (this symbol generally is
defined in the link script file) and depends
on the extern declaration of this symbol in
the bsp's "board.h". This is not a problem in
implementation, but it is not a good habit.

If this extern symbol is used locally, just
declare it locally should be better.

In this way, there will be no dependency of
the kernel core on the bsp header file. And
there will be no special requirements for the
bsp board code, such as the need to make
extern declarations for these "__bss_end"
symbols in "board.h".

This patch currently only explicitly externly
declares "__bss_end" inside libcpu itself.
The code of "#include <board.h>" is kept, because
the modification involved is too large, it is
necessary to clean up the bsp involved before
cleaning this include code line uniformly.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2025-04-11 14:15:12 +08:00
Chen Wang
5c9f61879c libcpu: cleanup undefined rt_hw_mmu_kernel_map_init (#10177)
* libcpu: cleanup undefined rt_hw_mmu_kernel_map_init

rt_hw_mmu_kernel_map_init() is declared in header files but
no definition found, cleanup the code.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>

* bsp: allwinner: d1: remove calling of rt_hw_mmu_kernel_map_init

rt_hw_mmu_kernel_map_init is an undefined function, calling it
is meaningless.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>

---------

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2025-04-11 07:54:21 +08:00
zms123456
883bdfa9ef [libcpu][aarch64]fix gicv3 mpidr table (#9284)
* fix gicv3 mpidr error

* phytium should support rt_cpu_mpidr_table by using common_setup
2025-03-28 11:08:28 +08:00
CYFS
b0e7cba9fd [bsp][stm32][artpi]:fix artpi nano (#10122) 2025-03-18 22:55:13 +08:00
Rbb666
cb098c4eea [fix]Fix cm33 compilation problem when block is turned on 2025-03-17 19:13:34 +08:00
ligr
9da813b151 [libcpu][risc-v]add code for handling exception scenarios in _unmap_area. 2025-03-17 17:40:55 +08:00
ligr
b04aacbd94 [libcpu][risc-v]remove unused parameter 'size' for func _unmap_area.
Signed-off-by: ligr <liguorui1213@163.com>
2025-03-17 17:40:55 +08:00