Otherwise report runtime error:
[E/kernel.obj] Object name sys workq exceeds RT_NAME_MAX=8, consider increasing RT_NAME_MAX.
(obj_name_len <= RT_NAME_MAX - 1) assertion failed at function:rt_object_allocate, line number:520
Increase the value of RT_NAME_MAX to 16 for c906B.
The value of RT_NAME_MAX for BSP of C906L and ARM core already meet
the requirement of more than 8.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Regarding link script, some memory offsets and sizes are different
between the standard version and the smart version (such as
"__STACKSIZE__", kernel start address, kernel memory size, etc.).
Original solution is replacing link scripts and use INCLUDE,
which is relatively complicated.
This improvement uses macros to replace constants in the link
script. The preprocessing mechanism provided by gcc is used
to dynamically replace constant values during the build process.
In addition, the kernel load address (the corresponding
KERNEL_VADDR_START for smart) was originally configured as
0xFFFFFFC000200000, which is default value of riscv with
kernelmap enabled (0xffffffc000000000) plus offset to skip over
bootloader (0x200000). This caused a trouble: due to
default bsp configuration is for smart, if we switched to the
standard version and build, and then switched back to the smart
version, the value of KERNEL_VADDR_START will be default back to
0xffffffc000000000, which is different from the original configuration
value, resulting in the need to manually reconfigure it, which
is easy to forget and cause problems.
The current solution is to use the default value
0xffffffc000000000 in the configuration. Add offset to the code
and link script when using it.
This patch update the default .config and rtconfig.h for cv18xx_riscv.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Add description on how to configure pinmux in menuconfig for
cvitek products.
Add myself to maintainer list in README.md.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Build error: 'struct _device_spi' has no member named 'base_addr'
Analyze: the name should be dws.regs
Solution: change base_addr to dws.regs
Signed-off-by: zdtyuiop4444 <ign7798540@gmail.com>
In actual operation, we often forget how to connect
the wires, so we just put the schematic diagram in
the readme document for quick recall.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
This patch fixed the error "bash: mksdimg.sh: No such file
or directory" when building cv18xx_aarch64.
The issue is introduced by commit "bsp: cvitek: removed
useless files after using rttpkgtool".
In addition, in order to unify the logic with riscv as much
as possible, the name of the "milkv-duo256m" directory under
cv18xx_aarch64 is uniformly changed to "duo256m".
This patch also improve the README, adding instructions to
install xz-utils.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
When building bsp/cvitek/c906_little, compiler warns:
```
board/board.c: In function 'rt_hw_board_init':
board/board.c:26:5: warning: implicit declaration of
function 'rt_hw_tick_init'; did you mean 'rt_hw_stack_init'?
[-Wimplicit-function-declaration]
26 | rt_hw_tick_init();
| ^~~~~~~~~~~~~~~
| rt_hw_stack_init
board/board.c:29:5: warning: implicit declaration of
function 'rt_hw_uart_init'; did you mean 'rt_hw_board_init'?
[-Wimplicit-function-declaration]
29 | rt_hw_uart_init();
| ^~~~~~~~~~~~~~~
| rt_hw_board_init
```
To remove these build warnings, include header files
which declare these functions.
Plus, remove the decalartion of `tick_isr()`, this
function does not exist.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Based on the patch "bsp: cvitek: use rttpkgtool
to replace cvitek_bootloader", continue cleanup useless files.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Originally, for riscv big and little cores under bsp/cvitek,
after generating rtthread.bin, the cvitek_bootloader tool
would be used to package it and generate fip.bin and boot.sd
files that can be burned into sdcard. However, the
cvitek_bootloader tool repository is relatively large, and
it compiles and generates firmware such as fsbl, opensbi and
uboot from the source code level. And when using it, it
needs to be downloaded to the bsp/cvitek directory, which
will introduce pollution to source files in the RTT repository
under the original working path.
The new solution uses rttpkgtool, which is similar to
cvitek_bootloader, but it uses prebuilt firmware, so it is
very small and does not introduce pollution to the source file.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
build warning: passing argument 1 of 'inv_icache_range' makes integer
from pointer without a cast [-Wint-conversion]
Analyze: The passed parameter type is void*, which is a pointer type,
but the required type is uintptr_t, which is an integer type. Therefore,
there will be a 'makes integer from pointer without a cast' warning.
Solution: casting the void* pointer to uintptr_t, ensure that the
function receives the correct type.
Signed-off-by: zdtyuiop4444 <ign7798540@gmail.com>
For bsp/cvitek, duo256m, the operation process is
slightly different when building images for riscv
and arm64.
To improve the user experience, unify the building
process and steps of the two as follows:
- Enter c906_little and execute `scons`
- Enter cv18xx_riscv/cv18xx_aarch64 and execute `scons`
That's all. Finally, we can get `fip.bin` and
`boot.sd` under `bsp/cvitek/output/milkv-duo256m`.
Update the README.md accordingly.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Duo's CPU combination is more complicated:
| BSP | B/L core| ISA | UART |
| ------------- | ------- |---------------- |-------|
| cv18xx_risc-v | Big | RISC-V C906 | UART0 |
| c906-little | Littel | RISC-V C906 | UART1 |
| cv18xx_aarch64| Big | ARM Cortex A53 | UART0 |
Printing ISA and big and small core information
during the boot process helps developers/testers
determine the CPU and serial port corresponding to
the current console.
In addition, the RTT logo printing has already
distinguished whether it is smart, so the bsp
printing no longer distinguishes.
Updated README to sync with this change.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
By default, the small core enables D-Cache without ensuring cache
coherence. Therefore, when using shared memory, inconsistencies can
occur in the data read by the small core and the big core.
Solution: Migrate cache-related functions from the official
duo-buildroot-sdk library to implement cache-related operations in
rthw.h. This allows you to either disable D-Cache or call the
flush_dcache_range function before reading and after writing for
synchronization.
It is recommended to use the flush_dcache_range function, as disabling
D-Cache can have a significant performance impact.
Signed-off-by: zdtyuiop4444 <ign7798540@gmail.com>
description: In the bsp/cvitek/c906_little/board/interrupt.c, There is an issue with
setting the PLIC_PRIORITY[n].
analysis: PLIC_PRIORITY[n] each register corresponds to the priority of
a hardware interrupt number.
Solution: Each register is 4 bytes.
Multiply the total number of IRQs by 4 instead of dividing by 4.
Signed-off-by: Liu Gui <kenneth.liu@sophgo.com>
Confirmed with milkv, only the sd card version is sold
by default for duo in the market. The spi pins are
provided through stamp holes, so that users can solder
the corresponding components on their baseboard during
secondary development.
In order to simplify maintenance work, the mainline
will only support the sd-card version and no longer
support spinor/spinand.
Updated config files the same in this patch.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
duo is a real hardware, no need for virtio.
Disable RT_USING_VIRTIO and update configuration to latest.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Move the combine.sh to under cv18xx_aarch64, so we can
run this script the same as scons and no need to change
cwd.
Rename the folder boot to prebuild just becuase all the
files under boot are prebuild binaries.
Move the prebuilt fip.bin to under prebuild/milkv-duo256m
because it's only for 256.
Update combine.sh accordingly and output fip.bin to the output
folder where we create fip.bin/boot.sd as other bsp.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
For ARM, RT-smart and RT-standard both enable mmc (see
rt_hw_board_init() in bsp/cvitek/cv18xx_aarch64/board/board.c,
rt_hw_mmu_setup is called both for smart or standard).
So ioremap is must to do for ARM.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Now lwext4 package has supported ext4. Add description in README
to introduce how to create rootfs of type ext4.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
When RTC is enabled, a warning appear during compiling:
warning: implicit declaration of function 'rtc_alarm_enable' [-Wimplicit-function-declaration]
366 | rtc_alarm_enable(alarm->enable);
| ^~~~~~~~~~~~~~~~
It's due to _rtc_set_alarm is not covered by RT_USING_ALARM. It's wrong.
Solution: cover all functions including _rtc_get_alarm & _rtc_set_alarm
under RT_USING_ALARM macro conditional defintion.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
README.md: add introduction about how to make rootfs(fat) and
booting kernel with it.
Plus some cleanup for this documentation.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Support mount rootfs automaticly during booting up.
First try ext, then fat.
Plus some code cleanup, such as remove BSP_USING_ON_CHIP_FLASH_FS,
which is not defined and unused.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
ROMFS is Read-Only Memory Filesystem. But ext4/fat are not read-only.
So renamed:
- mnt_romfs.c -> mnt_diskfs.c
- BSP_ROOTFS_TYPE_ROMFS -> BSP_ROOTFS_TYPE_DISKFS
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
CV18xx RISC-V C906L.
Configuration value for CPU and ARCH are already defined in rtconfig.py.
Remove these duplication from SConstruct.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
After first called from uart open, the dw8250_uart_configure
API cannot be called again. Otherwise, this will mess up the
device, and uart will not act properly to interrupt again.
Analysis: Configure uart device will close recive interrupte,
causing uart device to malfunction.
Solution: After configure uart device, enable the device's
recive interrupte.
Signed-off-by: Shicheng Chu <1468559561@qq.com>
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Supports both big and little cores of RISC-V C906,
but does not support ARM cores. Currently, only UART
drivers are supported on the peripherals.
Signed-off-by: Shicheng Chu <1468559561@qq.com>
