diff --git a/libcpu/arm/cortex-a/cpuport.h b/libcpu/arm/cortex-a/cpuport.h
index 5fb067999c..c18ae246b2 100644
--- a/libcpu/arm/cortex-a/cpuport.h
+++ b/libcpu/arm/cortex-a/cpuport.h
@@ -72,6 +72,11 @@ struct rt_hw_stack
 #define E_Bit       (1<<9)
 #define J_Bit       (1<<24)
 
+/* VFP/NEON register count for FPU context */
+#ifndef VFP_DATA_NR
+#define VFP_DATA_NR 64  /* 32 double-precision registers = 64 words */
+#endif
+
 #ifdef RT_USING_SMP
 typedef union {
     unsigned long slock;
diff --git a/libcpu/arm/cortex-a/stack.c b/libcpu/arm/cortex-a/stack.c
index 4c955677f8..5bb57ca4dd 100644
--- a/libcpu/arm/cortex-a/stack.c
+++ b/libcpu/arm/cortex-a/stack.c
@@ -61,7 +61,13 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
     *(--stk) = 0;       /* user sp*/
 #endif
 #ifdef RT_USING_FPU
-    *(--stk) = 0;       /* not use fpu*/
+    /* FPU context initialization matches context_gcc.S restore order:
+     * Stack layout (high to low): FPEXC -> FPSCR -> D16-D31 -> D0-D15
+     */
+    stk -= VFP_DATA_NR;
+    rt_memset(stk, 0, VFP_DATA_NR * sizeof(rt_uint32_t));  /* Initialize D0-D31 (64 words for 32 double regs) */
+    *(--stk) = 0;       /* FPSCR: Floating-Point Status and Control Register */
+    *(--stk) = 0x40000000;  /* FPEXC: Enable FPU (bit 30 = EN) */
 #endif
 
     /* return task's current stack address */