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Fixup the boot EL check

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The boot EL will save in x0, when current EL is EL3,
kernel will jump to the EL2 after EL3.
But the x0 value is **3**, The init for EL2 will not work.
To fix it: the EL3 should jump to the EL2 init branch with not check,
and when SoC boot in EL2, kernel will jump to the EL2 test branch.

Link: https://club.rt-thread.org/ask/question/ec320a6765389f67.html

Signed-off-by: wusongjie <wusongjie@rt-thread.com>
This commit is contained in:
GuEe-GUI
2025-07-04 16:51:55 +08:00
committed by Rbb666
parent e00143904f
commit d698bb487e
1 changed files with 3 additions and 3 deletions
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6
libcpu/aarch64/cortex-a/entry_point.S
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@@ -180,13 +180,12 @@ init_cpu_el:
/* running at EL3? */
cmp x0, #3
bne .init_cpu_hyp
bne .init_cpu_hyp_test
/* should never be executed, just for completeness. (EL3) */
mov x1, #(1 << 0) /* EL0 and EL1 are in Non-Secure state */
orr x1, x1, #(1 << 4) /* RES1 */
orr x1, x1, #(1 << 5) /* RES1 */
/* bic x1, x1, #(1 << 7) disable Secure Monitor Call */
orr x1, x1, #(1 << 10) /* The next lower level is AArch64 */
msr scr_el3, x1
@@ -201,11 +200,12 @@ init_cpu_el:
msr elr_el3, x1
eret
.init_cpu_hyp:
.init_cpu_hyp_test:
/* running at EL2? */
cmp x0, #2 /* EL2 = 0b10 */
bne .init_cpu_sys
.init_cpu_hyp:
/* Enable CNTP for EL1 */
mrs x0, cnthctl_el2 /* Counter-timer Hypervisor Control register */
orr x0, x0, #(1 << 0) /* Don't traps NS EL0/1 accesses to the physical counter */