diff --git a/bsp/bl808/README.md b/bsp/bl808/README.md deleted file mode 100644 index 9a609207ec..0000000000 --- a/bsp/bl808/README.md +++ /dev/null @@ -1,128 +0,0 @@ -# 博流智能 BL808板级支持包说明 - -## 1. 简介 - -BL808 是高度集成的 AIoT 芯片组，具有 Wi-Fi/BT/BLE/Zigbee 等无线互联单元，包含多个 CPU 以及音频编码译码器、视频编码译码器和 AI 硬件加速器，适用于各种高性能和低功耗应用领域。 - -BL808 系列芯片主要包含无线和多媒体两个子系统。 - -无线子系统包含一颗 RISC-V 32-bit 高性能 CPU（m0），集成 Wi-Fi/BT/Zigbee 无线子系统，可以实现多种无线连接和数据传输，提供多样化的连接与传输体验。 -多媒体子系统包含一颗 RISC-V 64-bit 超高性能 CPU（d0），集成 DVP/CSI/ H264/NPU 等视频处理模块，可以广泛应用于视频监控/智能音箱等多种 AI 领域 - -多媒体子系统组成部分如下： - -- NPU HW NN 协处理器 (BLAI-100)，适用于人工智能应用领域 -- 摄像头接口 -- 音频编码译码器 -- 视频编码解码器 -- 传感器 -- 显示接口 - -电源管理单元控制低功耗模式。此外，还支持各种安全功能。 - -外围接口包括 USB2.0、 Ethernet、 SD/MMC、 SPI、 UART、 I2C、 I2S、 PWM、 GPDAC/GPADC、 ACOMP、 PIR、 Touch、 -IR remote、 Display 和 GPIO。 - -支持灵活的 GPIO 配置， BL808 最多可达 40 个 GPIO。 - -芯片规格包括如下： - -| 硬件 | 描述 | -| -- | -- | -|芯片型号| bl808 | -|CPU| 三核异构RISC-V CPUs：
RV64GCV 480MHz
RV32GCP 320MHz
RV32EMC 160MHz | -|RAM| 768KB SRAM + 64MB UHS PSRAM | -| 外设 | 内嵌AES与SHA256算法加速器 | -| AI NN 通用硬件加速器 | BLAI-100 用于视频/音频检测/识别，100GOPS 算力 | -| 摄像头接口 | DVP 和 MIPI-CSI | -| 显示接口 | SPI、DBI、DPI(RGB) | -| 无线 | 支持 Wi-Fi 802.11 b/g/n
支持 Bluetooth 5.x Dual-mode(BT+BLE)
支持 Wi-Fi / 蓝牙 共存 | - -## 2. 编译说明 - -BL808是多核异构架构，分为m0和d0，每个核需要单独编译，并烧录到对应的位置。 - -### 2.1. 交叉编译期路径设置 -下载risc-v的工具链，[下载地址1](https://occ.t-head.cn/community/download?id=4073475960903634944)或[下载地址2](https://dl.sipeed.com/shareURL/others/toolchain) - -Windows下请使用使用[env工具][1]，使用命令 `tar -xvf Xuantie-900-gcc-elf-newlib-mingw-V2.6.1-20220906.tar.gz` 解压交叉编译器，使用Windows下解压工具直接解压可能出现Windows下编译错误。 - -在`rtconfig.py`中将risc-v工具链的本地路径加入 `EXEC_PATH` 或通过 `RTT_EXEC_PATH` 环境变量指定路径 - -Windows： -``` -set RTT_EXEC_PATH=C:\Users\xxxx\Downloads\Xuantie-900-gcc-elf-newlib-x86_64-V2.6.1\bin -``` - -Linux: -``` -export RTT_EXEC_PATH=/opt/Xuantie-900-gcc-elf-newlib-x86_64-V2.6.1/bin -``` - -### 2.2. 编译 - -Windows下推荐使用[env工具][1]，在console下进入bsp/bl808目录中，选择需要编译的核心，m0或d0，运行： - - cd bsp/bl808/m0 - menuconfig - pkgs --update - -如果在Linux平台下，可以先执行： - - scons --menuconfig - -它会自动下载env相关脚本到~/.env目录，然后执行 - - source ~/.env/env.sh - - cd bsp/bl808/m0 - pkgs --update - -更新完软件包后，执行 `scons -j10` 或 `scons -j10 --verbose` 来编译这个板级支持包。或者通过 `scons --exec-path="GCC工具链路径"` 命令，在指定工具链位置的同时直接编译。 - -如果编译正确无误，会产生rtthread.elf、rtthread_m0.bin文件。其中rtthread_m0.bin需要烧写到设备中进行运行。 - -## 3. 烧写及执行 - -连接好串口，然后使用[Bouffalo Lab Dev Cube](https://dev.bouffalolab.com/download)工具进行烧写bin文件。 - -![Bouffalo Lab Dev Cube](figures/program.jpg) - -### 3.1 运行结果 - -如果编译 & 烧写无误，当复位设备后，会在串口上看到RT-Thread的启动logo信息： - -![terminal](figures/bl808.jpg) - -## 4. 驱动支持情况及计划 - -| 驱动 | 支持情况 | 备注 | -| ------ | ---- | :------: | -| UART | 支持 | UART0，用于shell，默认波特率2000000 | -| GPIO | 支持 | | -| I2C | 支持 | 软件 I2C1，默认 SCL——20，SDA——21 | - -## 5. 联系人信息 - -维护人：[flyingcys](https://github.com/flyingcys) - -## 6. 支持开发板列表 - -| | 开发板型号 | -| ------ | ---------- | -| Sipeed | M1s Dock | -| | | - - -## 7. 参考 -* 芯片[datasheet][2] - - [1]: https://www.rt-thread.org/page/download.html - [2]: https://github.com/bouffalolab/bl_docs - -## 8. FAQ - -- 在 windows 环境下，通过 UART 接口将开发板连接至电脑时，仅能识别到两个 USB converter 设备，但是识别不到对应的串口设备。 - - 进入到设备管理器中，右击对应的 USB converter 设备，进入到属性中的高级设置，钩选 vcp 选项，刷新后即可看到对应的串口设备。 - - 也可通过安装以下驱动解决问题： https://dl.sipeed.com/shareURL/MAIX/tools/ftdi_vcp_driver -- 使用 TypeC 数据线将电脑与板子的 UART 口连接起来，此时电脑上会出现两个串口 （如果出现鼠标不能动的现象请拔掉 USB 并且查看 [更新板载 bl702 固件](https://wiki.sipeed.com/hardware/zh/maix/m1s/other/start.html#给板载-bl702-进行烧录) 相关内容来修复问题)。 diff --git a/bsp/bl808/figures/program.jpg b/bsp/bl808/figures/program.jpg deleted file mode 100644 index dc9d9c262f..0000000000 Binary files a/bsp/bl808/figures/program.jpg and /dev/null differ diff --git a/bsp/bl808/m0/drivers/Kconfig b/bsp/bl808/m0/drivers/Kconfig deleted file mode 100644 index ac17b47215..0000000000 --- a/bsp/bl808/m0/drivers/Kconfig +++ /dev/null @@ -1,63 +0,0 @@ -menu "BL808_M0 Hardware Drivers Config" -config SOC_BL808 - bool - select RT_USING_COMPONENTS_INIT - select RT_USING_USER_MAIN - select ARCH_RISCV_FPU_S - default y - - -config BSP_USING_JTAG_M0 - bool "Enable M0 JTAG " - default n - -menu "On-chip Peripheral Drivers" - - config BSP_USING_GPIO - bool "Enable GPIO" - select RT_USING_PIN - default y - - menuconfig BSP_USING_I2C1 - bool "Enable I2C1 BUS (software simulation)" - default n - select RT_USING_I2C - select RT_USING_I2C_BITOPS - select RT_USING_PIN - if BSP_USING_I2C1 - config BSP_I2C1_SCL_PIN - int "i2c1 scl pin number" - range 0 33 - default 20 - config BSP_I2C1_SDA_PIN - int "I2C1 sda pin number" - range 0 33 - default 21 - endif - - menuconfig BSP_USING_UART - bool "Enable UART" - default y - select RT_USING_SERIAL - if BSP_USING_UART - config BSP_USING_UART0 - bool "Enable UART0" - default y - - if BSP_USING_UART0 - config BSP_UART0_TXD_PIN - int "uart0 TXD pin number" - default 14 - - config BSP_UART0_RXD_PIN - int "uart0 RXD pin number" - default 15 - - endif - - endif - -endmenu - -endmenu - diff --git a/bsp/bl808/m0/drivers/SConscript b/bsp/bl808/m0/drivers/SConscript deleted file mode 100644 index 3cd7a608dd..0000000000 --- a/bsp/bl808/m0/drivers/SConscript +++ /dev/null @@ -1,53 +0,0 @@ -# RT-Thread building script for component - -from building import * - -cwd = GetCurrentDir() -src = Split(''' - board.c -''') - -CPPPATH = [cwd] - -if GetDepend(['RT_USING_SERIAL']): - if GetDepend(['RT_USING_SERIAL_V2']): - src += ['drv_uart_v2.c'] - else: - src += ['drv_uart.c'] - -if GetDepend('RT_USING_PIN'): - src += ['drv_gpio.c'] - -if GetDepend('RT_USING_I2C'): - src += ['drv_i2c.c'] - -# if GetDepend('BSP_USING_LCD'): -# src += ['drv_lcd.c'] -# src += ['drv_mpylcd.c'] - -# if GetDepend('RT_USING_HWTIMER'): -# src += ['drv_hw_timer.c'] - -# if GetDepend('RT_USING_CPUTIME'): -# src += ['drv_cputime.c'] - -# if GetDepend('RT_USING_SPI'): -# src += ['drv_spi.c'] - -# if GetDepend('RT_USING_PWM'): -# src += ['drv_pwm.c'] - -# if GetDepend('RT_USING_WDT'): -# src += ['drv_wdt.c'] - -group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) - -objs = [group] - -list = os.listdir(cwd) - -for item in list: - if os.path.isfile(os.path.join(cwd, item, 'SConscript')): - objs = objs + SConscript(os.path.join(item, 'SConscript')) - -Return('objs') diff --git a/bsp/bl808/m0/drivers/board.c b/bsp/bl808/m0/drivers/board.c deleted file mode 100644 index a5c823ac8d..0000000000 --- a/bsp/bl808/m0/drivers/board.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2022/12/25 flyingcys first version - * 2023/01/17 chushicheng add pin and i2c - */ -#include -#include - -#include "board.h" -#include "drv_uart.h" - -static void sipeed_bl_sys_enabe_jtag(int cpuid) -{ - GLB_GPIO_Cfg_Type gpio_cfg; - - gpio_cfg.drive = 0; - gpio_cfg.smtCtrl = 1; - gpio_cfg.pullType = GPIO_PULL_NONE; - - gpio_cfg.gpioMode = GPIO_MODE_AF; - switch (cpuid) { - case 0: { - gpio_cfg.gpioFun = GPIO_FUN_JTAG_M0; - } break; - case 1: { - gpio_cfg.gpioFun = GPIO_FUN_JTAG_D0; - } break; - default: { - } break; - } - gpio_cfg.gpioPin = GLB_GPIO_PIN_0; - GLB_GPIO_Init(&gpio_cfg); - - gpio_cfg.gpioPin = GLB_GPIO_PIN_1; - GLB_GPIO_Init(&gpio_cfg); - - gpio_cfg.gpioPin = GLB_GPIO_PIN_2; - GLB_GPIO_Init(&gpio_cfg); - - gpio_cfg.gpioPin = GLB_GPIO_PIN_3; - GLB_GPIO_Init(&gpio_cfg); -} - -static void cmd_jtag_m0(void) -{ - sipeed_bl_sys_enabe_jtag(0); -} - -static void cmd_jtag_cpu0(void) -{ - sipeed_bl_sys_enabe_jtag(1); -} - -/* This is the timer interrupt service routine. */ -static void mtime_handler(void) -{ - rt_tick_increase(); - - csi_coret_config(CPU_Get_MTimer_Clock() / RT_TICK_PER_SECOND, MTIME_IRQn); -} - -void rt_hw_board_init(void) -{ - bl_sys_lowlevel_init(); - - csi_coret_config(CPU_Get_MTimer_Clock() / RT_TICK_PER_SECOND, MTIME_IRQn); - bl_irq_register(MTIME_IRQn, mtime_handler); - bl_irq_enable(MTIME_IRQn); - -#ifdef RT_USING_HEAP - /* initialize memory system */ - rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); -#endif - - /* GPIO driver initialization is open by default */ -#ifdef RT_USING_PIN - rt_hw_pin_init(); -#endif - - /* I2C driver initialization is open by default */ -#ifdef RT_USING_I2C - rt_hw_i2c_init(); -#endif - - /* UART driver initialization is open by default */ -#ifdef RT_USING_SERIAL - rt_hw_uart_init(); -#endif - - /* Set the shell console output device */ -#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE) - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); -#endif - -#ifdef RT_USING_COMPONENTS_INIT - rt_components_board_init(); -#endif - -#ifdef BSP_USING_JTAG_M0 - cmd_jtag_m0(); -#endif -} - -void rt_hw_cpu_reset(void) -{ - bl_sys_reset_por(); - while(1); -} - -MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reset machine); diff --git a/bsp/bl808/m0/drivers/board.h b/bsp/bl808/m0/drivers/board.h deleted file mode 100644 index ead8fbdf84..0000000000 --- a/bsp/bl808/m0/drivers/board.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2022/12/25 flyingcys first version - */ - -#ifndef BOARD_H__ -#define BOARD_H__ - -#include - -#include "core_rv32.h" -#include "bl_sys.h" -#include "bl_irq.h" -#include "bl808_clock.h" - -#ifdef BL808 -#include "bl808.h" -#elif defined(BL606P) -#include "bl606p.h" -#endif - -extern uint8_t _heap_start; -extern uint8_t _heap_size; - -#define RT_HW_HEAP_BEGIN (void*)&_heap_start -#define RT_HW_HEAP_END (void*)(&_heap_start + (rt_ubase_t)&_heap_size) - -void rt_hw_board_init(void); - -#endif diff --git a/bsp/bl808/m0/drivers/drv_gpio.c b/bsp/bl808/m0/drivers/drv_gpio.c deleted file mode 100644 index ab43565f81..0000000000 --- a/bsp/bl808/m0/drivers/drv_gpio.c +++ /dev/null @@ -1,208 +0,0 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2023/01/5 chushicheng first version - * - */ - -#include "drv_gpio.h" -#include -#include "bl808_gpio.h" -#include "bl808_glb.h" -#include "bl808.h" - -#ifdef RT_USING_PIN - -#define DBG_TAG "drv.gpio" -#define DBG_LVL DBG_INFO -#include - -static void GPIO0_IRQHandler(void); - -struct gpio_int_cfg_private -{ - slist_t list; - uint32_t pin; - void (*hdr)(uint32_t pin); -}; - -static slist_t gpio_int_head = SLIST_OBJECT_INIT(gpio_int_head); - - -static void bl808_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) -{ - GLB_GPIO_Write(pin, value); -} - -static int bl808_pin_read(rt_device_t dev, rt_base_t pin) -{ - int value; - value = GLB_GPIO_Read(pin);; - return value; -} - -static void bl808_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) -{ - GLB_GPIO_Cfg_Type gpio_cfg; - - gpio_cfg.gpioFun = GPIO_FUN_GPIO; - gpio_cfg.gpioPin = pin; - gpio_cfg.drive = 0; - gpio_cfg.smtCtrl = 1; - gpio_cfg.outputMode = 0; - - switch (mode) - { - case GPIO_OUTPUT_MODE: - gpio_cfg.gpioMode = GPIO_MODE_OUTPUT; - gpio_cfg.pullType = GPIO_PULL_NONE; - break; - - case GPIO_OUTPUT_PP_MODE: - gpio_cfg.gpioMode = GPIO_MODE_OUTPUT; - gpio_cfg.pullType = GPIO_PULL_UP; - break; - - case GPIO_OUTPUT_PD_MODE: - gpio_cfg.gpioMode = GPIO_MODE_OUTPUT; - gpio_cfg.pullType = GPIO_PULL_DOWN; - break; - - case GPIO_INPUT_MODE: - gpio_cfg.gpioMode = GPIO_MODE_INPUT; - gpio_cfg.pullType = GPIO_PULL_NONE; - break; - - case GPIO_INPUT_PP_MODE: - gpio_cfg.gpioMode = GPIO_MODE_INPUT; - gpio_cfg.pullType = GPIO_PULL_UP; - break; - - case GPIO_INPUT_PD_MODE: - gpio_cfg.gpioMode = GPIO_MODE_INPUT; - gpio_cfg.pullType = GPIO_PULL_DOWN; - break; - case GPIO_HZ_MODE: - GLB_GPIO_Set_HZ(pin); - default: - CPU_Interrupt_Disable(GPIO_INT0_IRQn); - GLB_GPIO_IntMask(pin, MASK); - - GLB_GPIO_INT_Cfg_Type intCfg; - - intCfg.gpioPin = pin; - intCfg.intMask = MASK; - - gpio_cfg.gpioMode = GPIO_MODE_INPUT; - - if (mode == GPIO_ASYNC_RISING_TRIGER_INT_MODE) - { - gpio_cfg.pullType = GPIO_PULL_DOWN; - intCfg.trig = GLB_GPIO_INT_TRIG_ASYNC_RISING_EDGE; - } - else if (mode == GPIO_ASYNC_FALLING_TRIGER_INT_MODE) - { - gpio_cfg.pullType = GPIO_PULL_UP; - intCfg.trig = GLB_GPIO_INT_TRIG_ASYNC_FALLING_EDGE; - } - else if (mode == GPIO_ASYNC_HIGH_LEVEL_INT_MODE) - { - gpio_cfg.pullType = GPIO_PULL_DOWN; - intCfg.trig = GLB_GPIO_INT_TRIG_ASYNC_HIGH_LEVEL; - } - else if (mode == GPIO_ASYNC_LOW_LEVEL_INT_MODE) - { - gpio_cfg.pullType = GPIO_PULL_UP; - intCfg.trig = GLB_GPIO_INT_TRIG_ASYNC_LOW_LEVEL; - } - else if (mode == GPIO_SYNC_RISING_TRIGER_INT_MODE) - { - gpio_cfg.pullType = GPIO_PULL_DOWN; - intCfg.trig = GLB_GPIO_INT_TRIG_SYNC_RISING_EDGE; - } - else if (mode == GPIO_SYNC_FALLING_TRIGER_INT_MODE) - { - gpio_cfg.pullType = GPIO_PULL_UP; - intCfg.trig = GLB_GPIO_INT_TRIG_SYNC_FALLING_EDGE; - } - else if (mode == GPIO_SYNC_FALLING_TRIGER_INT_MODE) - { - gpio_cfg.pullType = GPIO_PULL_NONE; - intCfg.trig = GLB_GPIO_INT_TRIG_SYNC_FALLING_RISING_EDGE; - } - else if (mode == GPIO_SYNC_HIGH_LEVEL_INT_MODE) - { - gpio_cfg.pullType = GPIO_PULL_DOWN; - intCfg.trig = GLB_GPIO_INT_TRIG_SYNC_HIGH_LEVEL; - } - else if (mode == GPIO_SYNC_LOW_LEVEL_INT_MODE) - { - gpio_cfg.pullType = GPIO_PULL_UP; - intCfg.trig = GLB_GPIO_INT_TRIG_SYNC_LOW_LEVEL; - } - - GLB_GPIO_Int_Init(&intCfg); - break; - } - - GLB_GPIO_Init(&gpio_cfg); -} - - -static rt_err_t bl808_pin_attach_irq(struct rt_device *device, rt_int32_t pin, - rt_uint32_t irq_mode, void (*hdr)(void *args), void *args) -{ - struct gpio_int_cfg_private *int_cfg = malloc(sizeof(struct gpio_int_cfg_private)); - int_cfg->hdr = hdr; - int_cfg->pin = pin; - slist_add_tail(&gpio_int_head, &int_cfg->list); - CPU_Interrupt_Disable(GPIO_INT0_IRQn); - Interrupt_Handler_Register(GPIO_INT0_IRQn, GPIO0_IRQHandler); - CPU_Interrupt_Enable(GPIO_INT0_IRQn); - return RT_EOK; -} - - -static rt_err_t bl808_pin_irq_enable(struct rt_device *device, rt_base_t pin, - rt_uint32_t enabled) -{ - if (enabled) - { - GLB_GPIO_IntMask(pin, UNMASK); - } - else - { - GLB_GPIO_IntMask(pin, MASK); - } - return RT_EOK; -} - -const static struct rt_pin_ops _bl808_pin_ops = -{ - bl808_pin_mode, - bl808_pin_write, - bl808_pin_read, - bl808_pin_attach_irq, - bl808_pin_irq_enable, - NULL, -}; - -int rt_hw_pin_init(void) -{ - return rt_device_pin_register("pin", &_bl808_pin_ops, RT_NULL); -} -INIT_BOARD_EXPORT(rt_hw_pin_init); - -/* irq handle */ -void GPIO0_IRQHandler(void) -{ - rt_interrupt_enter(); - // GPIO_INT0_IRQHandler(); - rt_interrupt_leave(); -} - -#endif /* RT_USING_PIN */ diff --git a/bsp/bl808/m0/drivers/drv_gpio.h b/bsp/bl808/m0/drivers/drv_gpio.h deleted file mode 100644 index ff60c9ec79..0000000000 --- a/bsp/bl808/m0/drivers/drv_gpio.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2023/01/5 chushicheng first version - * - */ - -#ifndef __DRV_GPIO_H__ -#define __DRV_GPIO_H__ - -#include -#include -#include "drv_device.h" - -#define GPIO_OUTPUT_MODE 0 -#define GPIO_OUTPUT_PP_MODE 1 -#define GPIO_OUTPUT_PD_MODE 2 -#define GPIO_INPUT_MODE 3 -#define GPIO_INPUT_PP_MODE 4 -#define GPIO_INPUT_PD_MODE 5 -#define GPIO_ASYNC_RISING_TRIGER_INT_MODE 6 -#define GPIO_ASYNC_FALLING_TRIGER_INT_MODE 7 -#define GPIO_ASYNC_HIGH_LEVEL_INT_MODE 8 -#define GPIO_ASYNC_LOW_LEVEL_INT_MODE 9 -#define GPIO_SYNC_RISING_TRIGER_INT_MODE 10 -#define GPIO_SYNC_FALLING_TRIGER_INT_MODE 11 -#define GPIO_SYNC_RISING_FALLING_TRIGER_INT_MODE 12 -#define GPIO_SYNC_HIGH_LEVEL_INT_MODE 13 -#define GPIO_SYNC_LOW_LEVEL_INT_MODE 14 -#define GPIO_HZ_MODE 15 - - -int rt_hw_pin_init(void); - -#endif /* __DRV_GPIO_H__ */ diff --git a/bsp/bl808/m0/drivers/drv_i2c.c b/bsp/bl808/m0/drivers/drv_i2c.c deleted file mode 100644 index b69c6e623f..0000000000 --- a/bsp/bl808/m0/drivers/drv_i2c.c +++ /dev/null @@ -1,186 +0,0 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2023/01/17 chushicheng first version - */ - -#include -#include "drv_i2c.h" -#include "bl808_common.h" - -#ifdef RT_USING_I2C - -#define DBG_TAG "drv.i2c" -#define DBG_LVL DBG_INFO -#include - -#if !defined(BSP_USING_I2C1) -#error "Please define at least one BSP_USING_I2Cx" -/* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */ -#endif - -static const struct bl808_soft_i2c_config soft_i2c_config[] = -{ -#ifdef BSP_USING_I2C1 - I2C1_BUS_CONFIG, -#endif -}; - -static struct bl808_i2c i2c_obj[sizeof(soft_i2c_config) / sizeof(soft_i2c_config[0])]; - -/** - * This function initializes the i2c pin. - * - * @param bl808 i2c dirver class. - */ -static void bl808_i2c_gpio_init(struct bl808_i2c *i2c) -{ - struct bl808_soft_i2c_config* cfg = (struct bl808_soft_i2c_config*)i2c->ops.data; - - rt_pin_mode(cfg->scl, PIN_MODE_OUTPUT_OD); - rt_pin_mode(cfg->sda, PIN_MODE_OUTPUT_OD); - - rt_pin_write(cfg->scl, PIN_HIGH); - rt_pin_write(cfg->sda, PIN_HIGH); -} - -/** - * This function sets the sda pin. - * - * @param bl808 config class. - * @param The sda pin state. - */ -static void bl808_set_sda(void *data, rt_int32_t state) -{ - struct bl808_soft_i2c_config* cfg = (struct bl808_soft_i2c_config*)data; - if (state) - { - rt_pin_write(cfg->sda, PIN_HIGH); - } - else - { - rt_pin_write(cfg->sda, PIN_LOW); - } -} - -/** - * This function sets the scl pin. - * - * @param bl808 config class. - * @param The scl pin state. - */ -static void bl808_set_scl(void *data, rt_int32_t state) -{ - struct bl808_soft_i2c_config* cfg = (struct bl808_soft_i2c_config*)data; - if (state) - { - rt_pin_write(cfg->scl, PIN_HIGH); - } - else - { - rt_pin_write(cfg->scl, PIN_LOW); - } -} - -/** - * This function gets the sda pin state. - * - * @param The sda pin state. - */ -static rt_int32_t bl808_get_sda(void *data) -{ - struct bl808_soft_i2c_config* cfg = (struct bl808_soft_i2c_config*)data; - return rt_pin_read(cfg->sda); -} - -/** - * This function gets the scl pin state. - * - * @param The scl pin state. - */ -static rt_int32_t bl808_get_scl(void *data) -{ - struct bl808_soft_i2c_config* cfg = (struct bl808_soft_i2c_config*)data; - return rt_pin_read(cfg->scl); -} -/** - * The time delay function. - * - * @param microseconds. - */ -static void bl808_udelay(rt_uint32_t us) -{ - arch_delay_us(us); -} - -static const struct rt_i2c_bit_ops bl808_bit_ops_default = -{ - .data = RT_NULL, - .set_sda = bl808_set_sda, - .set_scl = bl808_set_scl, - .get_sda = bl808_get_sda, - .get_scl = bl808_get_scl, - .udelay = bl808_udelay, - .delay_us = 1, - .timeout = 100 -}; - -/** - * if i2c is locked, this function will unlock it - * - * @param bl808 config class - * - * @return RT_EOK indicates successful unlock. - */ -static rt_err_t bl808_i2c_bus_unlock(const struct bl808_soft_i2c_config *cfg) -{ - rt_int32_t i = 0; - - if (PIN_LOW == rt_pin_read(cfg->sda)) - { - while (i++ < 9) - { - rt_pin_write(cfg->scl, PIN_HIGH); - bl808_udelay(100); - rt_pin_write(cfg->scl, PIN_LOW); - bl808_udelay(100); - } - } - if (PIN_LOW == rt_pin_read(cfg->sda)) - { - return -RT_ERROR; - } - - return RT_EOK; -} - -/* I2C initialization function */ -int rt_hw_i2c_init(void) -{ - rt_err_t result; - - for (rt_size_t i = 0; i < sizeof(i2c_obj) / sizeof(struct bl808_i2c); i++) - { - i2c_obj[i].ops = bl808_bit_ops_default; - i2c_obj[i].ops.data = (void*)&soft_i2c_config[i]; - i2c_obj[i].i2c2_bus.priv = &i2c_obj[i].ops; - bl808_i2c_gpio_init(&i2c_obj[i]); - result = rt_i2c_bit_add_bus(&i2c_obj[i].i2c2_bus, soft_i2c_config[i].bus_name); - RT_ASSERT(result == RT_EOK); - bl808_i2c_bus_unlock(&soft_i2c_config[i]); - - LOG_D("software simulation %s init done, pin scl: %d, pin sda %d", - soft_i2c_config[i].bus_name, - soft_i2c_config[i].scl, - soft_i2c_config[i].sda); - } - - return RT_EOK; -} -INIT_BOARD_EXPORT(rt_hw_i2c_init); - -#endif /* RT_USING_I2C */ diff --git a/bsp/bl808/m0/drivers/drv_i2c.h b/bsp/bl808/m0/drivers/drv_i2c.h deleted file mode 100644 index 4add722a00..0000000000 --- a/bsp/bl808/m0/drivers/drv_i2c.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2023/01/17 chushicheng first version - */ - -#ifndef __DRV_I2C__ -#define __DRV_I2C__ - -#include -#include -#include - -/* bl808 config class */ -struct bl808_soft_i2c_config -{ - rt_uint8_t scl; - rt_uint8_t sda; - const char *bus_name; -}; -/* bl808 i2c dirver class */ -struct bl808_i2c -{ - struct rt_i2c_bit_ops ops; - struct rt_i2c_bus_device i2c2_bus; -}; - -#ifdef BSP_USING_I2C1 -#define I2C1_BUS_CONFIG \ - { \ - .scl = BSP_I2C1_SCL_PIN, \ - .sda = BSP_I2C1_SDA_PIN, \ - .bus_name = "i2c1", \ - } -#endif - -int rt_hw_i2c_init(void); - -#endif diff --git a/bsp/bl808/m0/drivers/drv_uart.c b/bsp/bl808/m0/drivers/drv_uart.c deleted file mode 100644 index 5f880cae9f..0000000000 --- a/bsp/bl808/m0/drivers/drv_uart.c +++ /dev/null @@ -1,318 +0,0 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes -* 2022/12/25 flyingcys first version -*/ - -#include -#include -#include - -#include "board.h" -#include "drv_uart.h" - - -struct device_uart -{ - struct rt_serial_device serial; - uint8_t port; - uint8_t tx_pin; - uint8_t rx_pin; -}; - -static void _uart_rx_irq(void *param) -{ - struct device_uart *uart = (struct device_uart *)param;; - - struct rt_serial_device *serial = &uart->serial; - - rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); -} - -static int uart_signal_get(uint8_t pin) -{ - //TODO no magic number is allowed here - if (pin >= 12 && pin <=23) { - return (pin + 6) % 12; - } else if (pin >= 36 && pin <=45) { - return (pin + 6) % 12; - } - return (pin % 12); -} - -static int uart_func_get(uint8_t id, GLB_UART_SIG_FUN_Type uartfunc) -{ - switch (id) { - case 0: - return uartfunc; - case 1: - return (GLB_UART_SIG_FUN_UART1_RTS - GLB_UART_SIG_FUN_UART0_RTS) * 1 + uartfunc; - case 2: - return (GLB_UART_SIG_FUN_UART1_RTS - GLB_UART_SIG_FUN_UART0_RTS) * 1 + uartfunc; - default: - /*empty here*/ - //TODO should assert here? - return uartfunc; - } -} -static void uart_gpio_demo(uint8_t id, uint8_t tx_pin, uint8_t rx_pin, uint8_t cts_pin, uint8_t rts_pin) -{ - GLB_GPIO_Cfg_Type gpio_cfg; - uint8_t uart_func, uart_sig; - - //FIXME SWAP set is NOT put here - GLB_UART_Sig_Swap_Set(GLB_UART_SIG_SWAP_GRP_GPIO12_GPIO23, 1); - GLB_UART_Sig_Swap_Set(GLB_UART_SIG_SWAP_GRP_GPIO36_GPIO45, 1); - - //common GPIO cfg - gpio_cfg.drive = 0; - gpio_cfg.smtCtrl = 1; - gpio_cfg.gpioMode = GPIO_MODE_AF; - gpio_cfg.pullType = GPIO_PULL_UP; - gpio_cfg.gpioFun = GPIO_FUN_UART; - - //cfg for UART Tx - gpio_cfg.gpioPin = GLB_GPIO_PIN_0 + tx_pin; - uart_func = uart_func_get(id, GLB_UART_SIG_FUN_UART0_TXD); - uart_sig = uart_signal_get(gpio_cfg.gpioPin); - GLB_UART_Fun_Sel((GLB_UART_SIG_Type)uart_sig, (GLB_UART_SIG_FUN_Type)uart_func); - GLB_UART_Fun_Sel((GLB_UART_SIG_Type)uart_func, (GLB_UART_SIG_FUN_Type)uart_sig); - GLB_GPIO_Init(&gpio_cfg); - - //cfg for UART Rx - gpio_cfg.gpioPin = GLB_GPIO_PIN_0 + rx_pin; - uart_func = uart_func_get(id, GLB_UART_SIG_FUN_UART0_RXD); - uart_sig = uart_signal_get(gpio_cfg.gpioPin); - GLB_UART_Fun_Sel((GLB_UART_SIG_Type)uart_sig, (GLB_UART_SIG_FUN_Type)uart_func); - GLB_UART_Fun_Sel((GLB_UART_SIG_Type)uart_func, (GLB_UART_SIG_FUN_Type)uart_sig); - GLB_GPIO_Init(&gpio_cfg); - - //Enable UART clock - GLB_Set_UART_CLK(1, 0, 0); -} - -static rt_err_t _uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) -{ - struct device_uart *uart; - uint8_t id; - - RT_ASSERT(serial != RT_NULL); - RT_ASSERT(cfg != RT_NULL); - - uart = serial->parent.user_data; - RT_ASSERT(uart != RT_NULL); - - id = uart->port; - - UART_CFG_Type uart_cfg = { - 80*1000*1000, /*UART clock from XTAL*/ - 2000000, /* baudrate */ - UART_DATABITS_8, /* data bits */ - UART_STOPBITS_1, /* stop bits */ - UART_PARITY_NONE, /* parity */ - DISABLE, /* Disable auto flow control */ - DISABLE, /* Disable rx input de-glitch function */ - DISABLE, /* Disable RTS output SW control mode */ - DISABLE, /* Disable tx output SW control mode */ - DISABLE, /* Disable tx lin mode */ - DISABLE, /* Disable rx lin mode */ - 0, /* Tx break bit count for lin mode */ - UART_LSB_FIRST, /* UART each data byte is send out LSB-first */ - }; - - UART_FifoCfg_Type fifoCfg = { - 16, /* TX FIFO threshold */ - 16, /* RX FIFO threshold */ - DISABLE, /* Disable tx dma req/ack interface */ - DISABLE /* Disable rx dma req/ack interface */ - }; - - /* init debug uart gpio first */ - uart_gpio_demo(id, uart->tx_pin, uart->rx_pin, 0xff, 0xff); - - /* disable all interrupt */ - UART_IntMask(id, UART_INT_ALL, MASK); - - /* disable uart before config */ - UART_Disable(id, UART_TXRX); - - uart_cfg.baudRate = cfg->baud_rate; - - switch (cfg->data_bits) - { - case DATA_BITS_5: - uart_cfg.dataBits = UART_DATABITS_5; - break; - - case DATA_BITS_6: - uart_cfg.dataBits = UART_DATABITS_6; - break; - - case DATA_BITS_7: - uart_cfg.dataBits = UART_DATABITS_7; - break; - - case DATA_BITS_8: - uart_cfg.dataBits = UART_DATABITS_8; - break; - - default: - uart_cfg.dataBits = UART_DATABITS_8; - break; - } - - switch (cfg->stop_bits) - { - case STOP_BITS_1: - uart_cfg.stopBits = UART_STOPBITS_1; - break; - - case STOP_BITS_2: - uart_cfg.stopBits = UART_STOPBITS_2; - break; - - default: - uart_cfg.stopBits = UART_STOPBITS_1; - break; - } - - switch (cfg->parity) - { - case PARITY_NONE: - uart_cfg.parity = UART_PARITY_NONE; - break; - - case PARITY_ODD: - uart_cfg.parity = UART_PARITY_ODD; - break; - - case PARITY_EVEN: - uart_cfg.parity = UART_PARITY_EVEN; - break; - - default: - uart_cfg.parity = UART_PARITY_NONE; - break; - } - - /* uart init with configuration */ - UART_Init(id, &uart_cfg); - - /* UART fifo configuration */ - UART_FifoConfig(id, &fifoCfg); - - /* Enable tx free run mode */ - UART_TxFreeRun(id, ENABLE); - - /* Set rx time-out value */ - UART_SetRxTimeoutValue(id, UART_DEFAULT_RTO_TIMEOUT); - - /* enable uart */ - UART_AutoBaudDetection(id, 0); - UART_Enable(id, UART_TXRX); - - return RT_EOK; -} - -static rt_err_t _uart_control(struct rt_serial_device *serial, int cmd, void *arg) -{ - struct device_uart *uart; - - RT_ASSERT(serial != RT_NULL); - - uart = serial->parent.user_data; - RT_ASSERT(uart != RT_NULL); - - switch (cmd) - { - /* disable interrupt */ - case RT_DEVICE_CTRL_CLR_INT: - bl_uart_int_disable(uart->port); - bl_uart_int_rx_notify_unregister(uart->port, _uart_rx_irq, uart); - break; - - /* enable interrupt */ - case RT_DEVICE_CTRL_SET_INT: - bl_uart_int_rx_notify_register(uart->port, _uart_rx_irq, uart); - bl_uart_int_enable(uart->port); - break; - } - return RT_EOK; -} - -static int _uart_putc(struct rt_serial_device *serial, char c) -{ - struct device_uart *uart; - - RT_ASSERT(serial != RT_NULL); - - uart = serial->parent.user_data; - RT_ASSERT(uart != RT_NULL); - - bl_uart_data_send(uart->port, c); - - return 1; -} - -static int _uart_getc(struct rt_serial_device *serial) -{ - int ch = -1; - struct device_uart *uart; - - RT_ASSERT(serial != RT_NULL); - uart = serial->parent.user_data; - RT_ASSERT(uart != RT_NULL); - - ch = bl_uart_data_recv(uart->port); - - return ch; -} - -static const struct rt_uart_ops _uart_ops = -{ - .configure = _uart_configure, - .control = _uart_control, - .putc = _uart_putc, - .getc = _uart_getc, - .dma_transmit = RT_NULL -}; - -/* - * UART Initiation - */ -int rt_hw_uart_init(void) -{ - rt_err_t result = 0; - - struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; - struct rt_serial_device *serial; - struct device_uart *uart; - -#ifdef BSP_USING_UART0 - static struct device_uart uart0; - - serial = &uart0.serial; - uart = &uart0; - - serial->ops = &_uart_ops; - serial->config = config; - serial->config.baud_rate = 2000000; - - uart->port = 0; - uart->tx_pin = BSP_UART0_TXD_PIN; - uart->rx_pin = BSP_UART0_RXD_PIN; - - /* register USART device */ - result = rt_hw_serial_register(serial, - "uart0", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, - uart); - RT_ASSERT(result == RT_EOK); -#endif - - return 0; -} diff --git a/bsp/bl808/m0/libraries/SConscript b/bsp/bl808/m0/libraries/SConscript deleted file mode 100644 index c8b2699f66..0000000000 --- a/bsp/bl808/m0/libraries/SConscript +++ /dev/null @@ -1,103 +0,0 @@ -import os -from building import * - -cwd = GetCurrentDir() - -# add general drivers -src = Split(''' - platform/soc/bl808/startup_bl808/evb/src/startup_interrupt.c - platform/soc/bl808/startup_bl808/evb/src/startup_bl606p.c - platform/soc/bl808/startup_bl808/evb/src/debug.c - platform/soc/bl808/startup_bl808/evb/src/boot/gcc/start_load.c - platform/soc/bl808/startup_bl808/evb/src/boot/gcc/startup.S -''') - -path = [cwd, - cwd + r'/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs', - cwd + r'/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/source', - cwd + r'/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc', - cwd + r'/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/Core/Include', - cwd + r'/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/default_config', - cwd + r'/platform/soc/bl808/bl808_e907_std/common/misc', - cwd + r'/platform/soc/bl808/bl808_e907_std/common/soft_crc'] - -src += Split(""" - stage/blog/blog.c - utils/src/utils_log.c - stage/blfdt/src/fdt.c - stage/blfdt/src/fdt_ro.c - stage/blfdt/src/fdt_wip.c - stage/blfdt/src/fdt_sw.c - stage/blfdt/src/fdt_rw.c - stage/blfdt/src/fdt_strerror.c - stage/blfdt/src/fdt_empty_tree.c - stage/blfdt/src/fdt_addresses.c - stage/blfdt/src/fdt_overlay.c -""") - -path += [cwd + r'/stage/blog', - cwd + r'/stage/blfdt/inc', - cwd + r'/utils/include' -] - - # platform/hosal/bl808_e907_hal/bl_pm.c - # platform/hosal/bl808_e907_hal/bl_sec.c - # platform/hosal/bl808_e907_hal/bl_timer.c - # platform/hosal/bl808_e907_hal/hal_board.c - # platform/hosal/bl808_e907_hal/hal_sdh.c - # platform/hosal/bl808_e907_hal/hosal_adc.c - # platform/hosal/bl808_e907_hal/hosal_dma.c - # platform/hosal/bl808_e907_hal/hosal_pwm.c - # platform/hosal/bl808_e907_hal/hosal_spi.c - # platform/hosal/bl808_e907_hal/hosal_uart.c - # platform/hosal/bl808_e907_hal/hal_sdh.c - - -src += Split(""" - platform/hosal/bl808_e907_hal/bl_uart.c - platform/hosal/bl808_e907_hal/bl_irq.c - platform/hosal/bl808_e907_hal/bl_chip.c - platform/hosal/bl808_e907_hal/bl_flash.c - platform/hosal/bl808_e907_hal/bl_wifi.c - platform/hosal/bl808_e907_hal/bl_efuse.c - platform/hosal/bl808_e907_hal/bl_sys.c - platform/hosal/bl808_e907_hal/bl_boot2.c - platform/hosal/bl808_e907_hal/bl_ipc.c - platform/hosal/bl808_e907_hal/bl_cam.c - platform/hosal/bl808_e907_hal/bl_audio.c - platform/hosal/bl808_e907_hal/bl_sdh.c - platform/hosal/bl808_e907_hal/hal_boot2.c - platform/hosal/bl808_e907_hal/hal_sys.c - platform/hosal/bl808_e907_hal/bl_psram.c - platform/hosal/bl808_e907_hal/bl_mm_clock.c - platform/hosal/bl808_e907_hal/hal_board.c - platform/soc/bl808/bl808_e907_std/common/misc/misc.c - platform/soc/bl808/bl808_e907_std/common/soft_crc/softcrc.c -""") - -src += Split(""" - platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_common.c - platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_clock.c - platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_uart.c - platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_glb.c - platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_glb_gpio.c - platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_pds.c - platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_hbn.c - platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sflash.c - platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_xip_sflash.c - platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sf_cfg.c - platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_ef_ctrl.c - platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sf_ctrl.c -""") - -path += [cwd + r'/platform/hosal/bl808_e907_hal'] -path += [cwd + r'/platform/soc/bl808/bl808_e907_std/common/device', - cwd + r'/platform/soc/bl808/bl808_e907_std/common/list'] - -libpath = [] -libs = [] - -group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, LIBS = libs, LIBPATH = libpath) - - -Return('group') diff --git a/bsp/bl808/m0/libraries/platform/hosal/adapter/hosal_adapter.h b/bsp/bl808/m0/libraries/platform/hosal/adapter/hosal_adapter.h deleted file mode 100644 index d4faed1793..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/adapter/hosal_adapter.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _HOSAL_ADAPTER_H_ -#define _HOSAL_ADAPTER_H_ - -#include - -uintptr_t hosal_adpt_critical_enter(void); -void hosal_adpt_critical_exit(uintptr_t); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/adapter/hosal_adpt_iotsdk.c b/bsp/bl808/m0/libraries/platform/hosal/adapter/hosal_adpt_iotsdk.c deleted file mode 100644 index 37f2868c8c..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/adapter/hosal_adpt_iotsdk.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "hosal_adapter.h" -#include "FreeRTOS.h" -#include "task.h" - -uintptr_t hosal_adpt_critical_enter(void) -{ - taskENTER_CRITICAL(); - return 0; -} - -void hosal_adpt_critical_exit(uintptr_t irq_state) -{ - (void)irq_state; - taskEXIT_CRITICAL(); -} - diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_audio.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_audio.c deleted file mode 100644 index 65edf03c10..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_audio.c +++ /dev/null @@ -1,545 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "bl_audio.h" - -#include "bl808.h" -#include "bl808_audio.h" -#include "bl808_glb.h" -#include "bl808_hbn.h" -#include "bl808_dma.h" -#include "bl_irq.h" -// #include -// #include - -static bl_audio_dev_t *gp_audio_dac_dev = NULL; - -#define AUDIO_DMA_ID DMA0_ID -#define AUDIO_TX_DMA_CHANNLE DMA_CH0 -#define AUDIO_RX_DMA_CHANNLE DMA_CH1 - -static struct DMA_Control_Reg dmaCtrlRegVal={ - .TransferSize = 1000, - .SBSize = DMA_BURST_SIZE_8, - .DBSize = DMA_BURST_SIZE_8, - .SWidth = DMA_TRNS_WIDTH_16BITS, - .DWidth = DMA_TRNS_WIDTH_16BITS, - .SI = DMA_MINC_ENABLE, - .DI = DMA_MINC_DISABLE, - .dst_min_mode = DISABLE, - .dst_add_mode = DISABLE, - .fix_cnt = 0, - .I = 1, -}; - -static DMA_LLI_Cfg_Type lliCfg={ - DMA_TRNS_M2P, - DMA_REQ_NONE, - DMA_REQ_AUDIO_TX, -}; - -static int __hw_init(bl_audio_dev_t *p_dev) -{ - Audio_FifoCfg_Type audioFifoCfg; - - Audio_Clock_CFG_Type audioClockCfg = { - AUDIO_ADC_16_KHZ, - AUDIO_DAC_16_KHZ, - DISABLE, - DISABLE, - DISABLE, - }; - - Audio_Volume_Cfg_Type audioVolumeCfg = { - AUIDO_MUTE_DIRECTLY, - AUIDO_RAMP_RATE_2_FS, - AUIDO_RAMP_RATE_2_FS, - AUIDO_VOLUME_UPDATE_FORCE, - AUIDO_ZERO_CROSS_RATE_2_FS, - AUIDO_RAMP_RATE_2_FS, - AUIDO_ZERO_CROSS_RATE_2_FS, - }; - - GLB_Config_AUDIO_PLL(GLB_XTAL_40M, audioPllCfg_451P584M); - /* ungate audio */ - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_AUDIO); - - /* enable dac clock*/ - GLB_Set_Audio_DAC_CLK(ENABLE, 19); - /* enable adc clock*/ - GLB_Set_Audio_ADC_CLK(ENABLE, 19); - - Audio_Poweron(); - - switch (p_dev->samplerate) { - case AUDIO_8_KHZ: - audioClockCfg.dac_clock = AUDIO_DAC_8_KHZ; - printf("samplerate 8K\r\n"); - break; - case AUDIO_16_KHZ: - audioClockCfg.dac_clock = AUDIO_DAC_16_KHZ; - printf("samplerate 16K\r\n"); - break; - case AUDIO_24_KHZ: - audioClockCfg.dac_clock = AUDIO_DAC_24_KHZ; - printf("samplerate 24K\r\n"); - break; - case AUDIO_32_KHZ: - audioClockCfg.dac_clock = AUDIO_DAC_32_KHZ; - printf("samplerate 32K\r\n"); - break; - case AUDIO_48_KHZ: - audioClockCfg.dac_clock = AUDIO_DAC_48_KHZ; - printf("samplerate 48K\r\n"); - break; - case AUDIO_96_KHZ: - audioClockCfg.dac_clock = AUDIO_DAC_96_KHZ; - printf("samplerate 96K\r\n"); - break; - case AUDIO_192_KHZ: - audioClockCfg.dac_clock = AUDIO_DAC_192_KHZ; - printf("samplerate 192K\r\n"); - break; - default: - printf("samplerate NULL\r\n"); - break; - } - - Audio_Clock_Init(&audioClockCfg); - //set mute ramp - Audio_DAC_Software_Volume_Config(AUDIO_DAC_0, &audioVolumeCfg); - if (p_dev->rx_channel == STEREO_CHANNEL) { - Audio_DAC_Software_Volume_Config(AUDIO_DAC_1, &audioVolumeCfg); - } - - Audio_DAC_Set_Volume_Reg(ENABLE, 0, AUDIO_PLAY_DEFAULT_INITIAL_VOLUME); - - Audio_DAC_Enable(AUDIO_DAC_0); - if (p_dev->rx_channel == STEREO_CHANNEL) { - Audio_DAC_Enable(AUDIO_DAC_1); - } - - Audio_DAC_Set_Mute(ENABLE, 0, AUDIO_UNMUTE); - - switch (p_dev->playBitWidth) { - case AUDIO_BIT_WIDTH_16: - audioFifoCfg.resolution = AUDIO_RES_16_BITS; - audioFifoCfg.ailgnMode = AUDIO_FIFO_AILGN_MSB_AT_BIT15; - printf("BitWidth 16\r\n"); - break; - case AUDIO_BIT_WIDTH_24: - audioFifoCfg.resolution = AUDIO_RES_20_BITS; - audioFifoCfg.ailgnMode = AUDIO_FIFO_AILGN_MSB_AT_BIT23; - printf("BitWidth 24\r\n"); - break; - case AUDIO_BIT_WIDTH_32: - audioFifoCfg.resolution = AUDIO_RES_20_BITS; - audioFifoCfg.ailgnMode = AUDIO_FIFO_AILGN_MSB_AT_BIT31; - printf("BitWidth 32\r\n"); - break; - default: - printf("BitWidth NULL\r\n"); - break; - } - audioFifoCfg.FifoIntThreshold = AUDIO_DEFAULT_TX_DRQ_THR; - audioFifoCfg.dmaThresholdMode = AUDIO_DRQ_EQUEL_TO_IRQ; - audioFifoCfg.dmaEn = ENABLE; - - Audio_TxFifoConfig(&audioFifoCfg); - - Audio_TxFifoDisable(p_dev->tx_channel); - - if (p_dev->rx_enable) { - Audio_ADC_Software_Volume_Config(AUDIO_ADC_0, &audioVolumeCfg); - if (p_dev->rx_channel == STEREO_CHANNEL) { - Audio_ADC_Software_Volume_Config(AUDIO_ADC_1, &audioVolumeCfg); - } - - Audio_ADC_Set_Volume_Reg(ENABLE, 0, AUDIO_PLAY_DEFAULT_INITIAL_VOLUME); - - Audio_ADC_Enable(AUDIO_ADC_0); - if (p_dev->rx_channel == STEREO_CHANNEL) { - Audio_ADC_Enable(AUDIO_ADC_1); - } - - Audio_ADC_Set_Mute(ENABLE, 0, AUDIO_UNMUTE); - - audioFifoCfg.FifoIntThreshold = AUDIO_DEFAULT_RX_DRQ_THR; - Audio_RxFifoConfig(&audioFifoCfg); - Audio_RxFifoDisable(p_dev->rx_channel); - } - Auido_IntMask(AUDIO_INT_NUM_ALL, MASK); - - return 0; -} - -static void __audio_lli_init(bl_audio_dev_t *p_dev) -{ - p_dev->lli_tx_buffer_size = p_dev->lli_tx_buffer_size / 2; - - switch (p_dev->playBitWidth) { - case AUDIO_BIT_WIDTH_16: - dmaCtrlRegVal.SWidth = DMA_TRNS_WIDTH_16BITS; - dmaCtrlRegVal.DWidth = DMA_TRNS_WIDTH_16BITS; - dmaCtrlRegVal.SBSize = DMA_BURST_SIZE_8; - dmaCtrlRegVal.DBSize = DMA_BURST_SIZE_8; - dmaCtrlRegVal.TransferSize = p_dev->lli_tx_buffer_size / 2; - break; - case AUDIO_BIT_WIDTH_24: - dmaCtrlRegVal.SWidth = DMA_TRNS_WIDTH_32BITS; - dmaCtrlRegVal.DWidth = DMA_TRNS_WIDTH_32BITS; - dmaCtrlRegVal.SBSize = DMA_BURST_SIZE_4; - dmaCtrlRegVal.DBSize = DMA_BURST_SIZE_4; - dmaCtrlRegVal.TransferSize = p_dev->lli_tx_buffer_size / 4; - break; - case AUDIO_BIT_WIDTH_32: - dmaCtrlRegVal.SWidth = DMA_TRNS_WIDTH_32BITS; - dmaCtrlRegVal.DWidth = DMA_TRNS_WIDTH_32BITS; - dmaCtrlRegVal.SBSize = DMA_BURST_SIZE_4; - dmaCtrlRegVal.DBSize = DMA_BURST_SIZE_4; - dmaCtrlRegVal.TransferSize = p_dev->lli_tx_buffer_size / 4; - break; - - default: - //private_bflb_platform_printf("BIT WIDTH Is Invaild\r\n"); - break; - } - - p_dev->lli_tx_list[0].srcDmaAddr = (uint32_t)p_dev->lli_tx_buffer; - p_dev->lli_tx_list[0].destDmaAddr = AUDIO_TX_FIFO_ADDR; - p_dev->lli_tx_list[0].nextLLI = (uint32_t)&p_dev->lli_tx_list[1]; - p_dev->lli_tx_list[0].dmaCtrl= dmaCtrlRegVal; - - p_dev->lli_tx_list[1].srcDmaAddr = (uint32_t)p_dev->lli_tx_buffer + p_dev->lli_tx_buffer_size; - p_dev->lli_tx_list[1].destDmaAddr = AUDIO_TX_FIFO_ADDR; - p_dev->lli_tx_list[1].nextLLI=(uint32_t)&p_dev->lli_tx_list[0]; - p_dev->lli_tx_list[1].dmaCtrl= dmaCtrlRegVal; - - DMA_LLI_Init(AUDIO_DMA_ID, AUDIO_TX_DMA_CHANNLE, &lliCfg); - DMA_LLI_Update(AUDIO_DMA_ID, AUDIO_TX_DMA_CHANNLE, (uint32_t)&gp_audio_dac_dev->lli_tx_list); - - if (p_dev->rx_enable) { - p_dev->lli_rx_buffer_size = p_dev->lli_rx_buffer_size / 2; - - switch (p_dev->playBitWidth) { - case AUDIO_BIT_WIDTH_16: - dmaCtrlRegVal.SWidth = DMA_TRNS_WIDTH_16BITS; - dmaCtrlRegVal.DWidth = DMA_TRNS_WIDTH_16BITS; - dmaCtrlRegVal.SBSize = DMA_BURST_SIZE_8; - dmaCtrlRegVal.DBSize = DMA_BURST_SIZE_8; - dmaCtrlRegVal.TransferSize = p_dev->lli_rx_buffer_size / 2; - break; - case AUDIO_BIT_WIDTH_24: - dmaCtrlRegVal.SWidth = DMA_TRNS_WIDTH_32BITS; - dmaCtrlRegVal.DWidth = DMA_TRNS_WIDTH_32BITS; - dmaCtrlRegVal.SBSize = DMA_BURST_SIZE_4; - dmaCtrlRegVal.DBSize = DMA_BURST_SIZE_4; - dmaCtrlRegVal.TransferSize = p_dev->lli_rx_buffer_size / 4; - break; - case AUDIO_BIT_WIDTH_32: - dmaCtrlRegVal.SWidth = DMA_TRNS_WIDTH_32BITS; - dmaCtrlRegVal.DWidth = DMA_TRNS_WIDTH_32BITS; - dmaCtrlRegVal.SBSize = DMA_BURST_SIZE_4; - dmaCtrlRegVal.DBSize = DMA_BURST_SIZE_4; - dmaCtrlRegVal.TransferSize = p_dev->lli_rx_buffer_size / 4; - break; - - default: - //private_bflb_platform_printf("BIT WIDTH Is Invaild\r\n"); - break; - } - - dmaCtrlRegVal.SI = DMA_MINC_DISABLE; - dmaCtrlRegVal.DI = DMA_MINC_ENABLE; - - p_dev->lli_rx_list[0].srcDmaAddr = AUDIO_RX_FIFO_ADDR; - p_dev->lli_rx_list[0].destDmaAddr = (uint32_t)p_dev->lli_rx_buffer; - p_dev->lli_rx_list[0].nextLLI = (uint32_t)&p_dev->lli_rx_list[1]; - p_dev->lli_rx_list[0].dmaCtrl= dmaCtrlRegVal; - - p_dev->lli_rx_list[1].srcDmaAddr = AUDIO_RX_FIFO_ADDR; - p_dev->lli_rx_list[1].destDmaAddr = (uint32_t)p_dev->lli_rx_buffer + p_dev->lli_rx_buffer_size; - p_dev->lli_rx_list[1].nextLLI=(uint32_t)&p_dev->lli_rx_list[0]; - p_dev->lli_rx_list[1].dmaCtrl= dmaCtrlRegVal; - - lliCfg.dir = DMA_TRNS_P2M; - lliCfg.srcPeriph = DMA_REQ_AUDIO_RX; - lliCfg.dstPeriph = DMA_REQ_NONE; - - DMA_LLI_Init(AUDIO_DMA_ID, AUDIO_RX_DMA_CHANNLE, &lliCfg); - DMA_LLI_Update(AUDIO_DMA_ID, AUDIO_RX_DMA_CHANNLE, (uint32_t)&gp_audio_dac_dev->lli_rx_list); - } -} - -static int __dma_int_clear(DMA_ID_Type dma_id, int ch) -{ - uint32_t tmpVal; - uint32_t intClr; - /* Get DMA register */ - - const uint32_t dmaAddr[] = { DMA0_BASE, DMA1_BASE, DMA2_BASE }; - uint32_t DMAChs = dmaAddr[dma_id]; - - tmpVal = BL_RD_REG(DMAChs, DMA_INTTCSTATUS); - if((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCSTATUS) & (1 << ch)) != 0) { - /* Clear interrupt */ - tmpVal = BL_RD_REG(DMAChs, DMA_INTTCCLEAR); - intClr = BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCCLEAR); - intClr |= (1 << ch); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_INTTCCLEAR, intClr); - BL_WR_REG(DMAChs, DMA_INTTCCLEAR, tmpVal); - } - - tmpVal = BL_RD_REG(DMAChs, DMA_INTERRORSTATUS); - if((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRORSTATUS) & (1 << ch)) != 0) { - /*Clear interrupt */ - tmpVal = BL_RD_REG(DMAChs, DMA_INTERRCLR); - intClr = BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRCLR); - intClr |= (1 << ch); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_INTERRCLR, intClr); - BL_WR_REG(DMAChs, DMA_INTERRCLR, tmpVal); - } - - return 0; -} - -static void __dma_irq_handler(void) -{ - uint32_t tmpVal, count; - int ret, size; - tmpVal = BL_RD_REG(DMA0_BASE, DMA_INTTCSTATUS); - if ((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCSTATUS) & (1 << AUDIO_TX_DMA_CHANNLE)) != 0) { - __dma_int_clear(AUDIO_DMA_ID, AUDIO_TX_DMA_CHANNLE); //clear int first - - if ( NULL == gp_audio_dac_dev) { - return; - } - size = gp_audio_dac_dev->lli_tx_buffer_size; - /*FIXME: set dma chain resonable option first 2 chain*/ - if (gp_audio_dac_dev->usr_cb) { - /* software count may reliable*/ - //if (++gp_audio_dac_dev->pingpang >= 2) { - // gp_audio_dac_dev->pingpang = 0; - //} - - count = ((*(volatile uint32_t *)0x2000c110) & (0x3FF << 20)) >> 20; - if (0x01 == (count & 0x01)) { - ret = gp_audio_dac_dev->usr_cb(gp_audio_dac_dev->p_usr_arg, - gp_audio_dac_dev->lli_tx_buffer, - size, - gp_audio_dac_dev->is_underrun); - } else { - ret = gp_audio_dac_dev->usr_cb(gp_audio_dac_dev->p_usr_arg, - gp_audio_dac_dev->lli_tx_buffer + size, - size, - gp_audio_dac_dev->is_underrun); - } - if (ret != 0) { - gp_audio_dac_dev->is_underrun = 1; - } else { - gp_audio_dac_dev->is_underrun = 0; - } - } - } - - if((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCSTATUS) & (1 << AUDIO_RX_DMA_CHANNLE)) != 0) { - __dma_int_clear(AUDIO_DMA_ID, AUDIO_RX_DMA_CHANNLE); //clear int first - if ( NULL == gp_audio_dac_dev) { - return; - } - size = gp_audio_dac_dev->lli_rx_buffer_size; - if (gp_audio_dac_dev->usr_rx_cb) { - count = ((*(volatile uint32_t *)0x2000c210) & (0x3FF << 20)) >> 20; - /*FIXME: set dma multi chains*/ - if (0x01 == (count & 0x01)) { - ret = gp_audio_dac_dev->usr_rx_cb(gp_audio_dac_dev->p_usr_rx_arg, - gp_audio_dac_dev->lli_rx_buffer, - size, - gp_audio_dac_dev->is_overflow); - } else { - ret = gp_audio_dac_dev->usr_rx_cb(gp_audio_dac_dev->p_usr_rx_arg, - gp_audio_dac_dev->lli_rx_buffer + size, - size, - gp_audio_dac_dev->is_overflow); - } - if (ret != 0) { - gp_audio_dac_dev->is_overflow = 1; - } else { - gp_audio_dac_dev->is_overflow = 0; - } - } - } -} - -int bl_audio_samplerate_set (bl_audio_dev_t *p_dev, Audio_Samplerate_Type samplerate) -{ - p_dev->samplerate = samplerate; - - return 0; -} - -int bl_audio_tx_ready_config(bl_audio_dev_t *p_dev, - audio_callback_tx_ready_t cb, - void *p_arg) -{ - if (NULL == p_dev) { - printf("tx ready config fail dev is null\r\n"); - return -1; - } - p_dev->usr_cb = cb; - p_dev->p_usr_arg = p_arg; - return 0; -} - -int bl_audio_rx_ready_config(bl_audio_dev_t *p_dev, - audio_callback_rx_ready_t cb, - void *p_arg) -{ - if (NULL == p_dev) { - printf("rx ready config fail dev is null\r\n"); - return -1; - } - p_dev->usr_rx_cb = cb; - p_dev->p_usr_rx_arg = p_arg; - return 0; -} - -int bl_audio_tx_buffer_config (bl_audio_dev_t *p_dev, void **ptr_mem, uint32_t bufsize) -{ - if (NULL == p_dev->lli_tx_buffer) { - p_dev->lli_tx_buffer = pvPortMalloc(bufsize); - } - - if (NULL == p_dev->lli_tx_buffer) { - printf("malloc tx buffer fail\r\n"); - return -1; - } - - memset(p_dev->lli_tx_buffer, 0, bufsize); - csi_dcache_clean_range((void *)(p_dev->lli_tx_buffer), bufsize); - *ptr_mem = p_dev->lli_tx_buffer; - p_dev->lli_tx_buffer_size = bufsize; - - return 0; -} - -int bl_audio_rx_buffer_config (bl_audio_dev_t *p_dev, - void **ptr_mem, - uint32_t bufsize) -{ - if (NULL == p_dev->lli_rx_buffer) { - p_dev->lli_rx_buffer = pvPortMalloc(bufsize); - } - - if (NULL == p_dev->lli_rx_buffer) { - printf("malloc rx buffer fail\r\n"); - return -1; - } - - memset(p_dev->lli_rx_buffer, 0, bufsize); - csi_dcache_clean_range((void *)(p_dev->lli_rx_buffer), bufsize); - *ptr_mem = p_dev->lli_rx_buffer; - p_dev->lli_rx_buffer_size = bufsize; - - return 0; -} - -int bl_audio_start (bl_audio_dev_t *p_dev) -{ - if (NULL == p_dev) { - printf("audio start fail dev is NULL\r\n"); - return -1; - } - - __hw_init(p_dev); - - GLB_Set_DMA_CLK(ENABLE, GLB_DMA0_CLK_CH0); - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_DMA_0); - - DMA_Disable(AUDIO_DMA_ID); - DMA_Channel_Disable(AUDIO_DMA_ID, AUDIO_TX_DMA_CHANNLE); - DMA_Channel_Disable(AUDIO_DMA_ID, AUDIO_RX_DMA_CHANNLE); - - DMA_IntMask(AUDIO_DMA_ID, AUDIO_TX_DMA_CHANNLE, DMA_INT_ALL, MASK); - DMA_IntMask(AUDIO_DMA_ID, AUDIO_TX_DMA_CHANNLE, DMA_INT_TCOMPLETED, UNMASK); - DMA_IntMask(AUDIO_DMA_ID, AUDIO_RX_DMA_CHANNLE, DMA_INT_ALL, MASK); - DMA_IntMask(AUDIO_DMA_ID, AUDIO_RX_DMA_CHANNLE, DMA_INT_TCOMPLETED, UNMASK); - bl_irq_register(DMA0_ALL_IRQn, __dma_irq_handler); - bl_irq_enable(DMA0_ALL_IRQn); - - __audio_lli_init(p_dev); - - csi_dcache_clean(); - DMA_Enable(AUDIO_DMA_ID); - DMA_Channel_Enable(AUDIO_DMA_ID, AUDIO_TX_DMA_CHANNLE); - - Audio_TxFifoEnable(p_dev->tx_channel); - - if (p_dev->rx_enable) { - DMA_Channel_Enable(AUDIO_DMA_ID, AUDIO_RX_DMA_CHANNLE); - Audio_RxFifoEnable(p_dev->rx_channel); - } - return 0; -} - -int bl_audio_stop (bl_audio_dev_t *p_dev) -{ - gp_audio_dac_dev->pingpang = 0; - - DMA_Disable(AUDIO_DMA_ID); - DMA_Channel_Disable(AUDIO_DMA_ID, AUDIO_TX_DMA_CHANNLE); - if (p_dev->rx_enable) { - DMA_Channel_Disable(AUDIO_DMA_ID, AUDIO_RX_DMA_CHANNLE); - } - bl_irq_disable(DMA0_ALL_IRQn); - - return 0; -} - -int bl_audio_init (bl_audio_dev_t *p_dev) -{ - if (NULL == p_dev) { - printf("init audio fail dev is null\r\n"); - return -1; - } - memset(p_dev, 0, sizeof(bl_audio_dev_t)); - gp_audio_dac_dev = p_dev; - - return 0; -} - -int bl_audio_deinit (bl_audio_dev_t *p_dev) -{ - vPortFree(p_dev->lli_tx_buffer); - p_dev->lli_tx_buffer = NULL; - - vPortFree(p_dev->lli_rx_buffer); - p_dev->lli_tx_buffer = NULL; - return 0; -} diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_audio.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_audio.h deleted file mode 100644 index 620edef1f9..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_audio.h +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __BL_AUDIO_H__ -#define __BL_AUDIO_H__ - -#include -#include -#include "bl808_audio.h" - -typedef int (*audio_callback_rx_ready_t)(void *usrdata, uint8_t *audiodata, int len, int is_overflow); -typedef int (*audio_callback_tx_ready_t)(void *uerdata, uint8_t *audiodata, int len, int is_underrun); - -#define AUDIO_PLAY_DEFAULT_INITIAL_VOLUME 0x0 -#define AUDIO_TX_FIFO_ADDR AUDIO_BASE + 0x94 -#define AUDIO_RX_FIFO_ADDR AUDIO_BASE + 0x88 -#define AUDIO_DEFAULT_TX_DRQ_THR 8 -#define AUDIO_DEFAULT_RX_DRQ_THR 8 - -typedef enum { - LEFT_CHANNEL = 1, /*!< select mono mode left only */ - RIGHT_CHANNEL = 2, /*!< select mono mode right only */ - STEREO_CHANNEL = 3, /*!< select stereo */ - THREE_CHANNEL = 7, /*!< select Three */ -} Audio_Channel_Type; - -typedef enum { - AUDIO_BIT_WIDTH_16, /*!< 16 bit */ - AUDIO_BIT_WIDTH_24, /*!< 24 bit */ - AUDIO_BIT_WIDTH_32, /*!< 32 bit */ -} Audio_BitWidth_Type; - -typedef enum { - AUDIO_8_KHZ, /*!< Audio DAC Clock set as 8KHZ */ - AUDIO_16_KHZ, /*!< Audio DAC Clock set as 16KHZ */ - AUDIO_24_KHZ, /*!< Audio DAC Clock set as 24KHZ */ - AUDIO_32_KHZ, /*!< Audio DAC Clock set as 32KHZ */ - AUDIO_48_KHZ, /*!< Audio DAC Clock set as 48KHZ */ - AUDIO_96_KHZ, /*!< Audio DAC Clock set as 96KHZ */ - AUDIO_192_KHZ, /*!< Audio DAC Clock set as 192KHZ */ -} Audio_Samplerate_Type; - -typedef struct { - uint8_t pingpang; - DMA_LLI_Ctrl_Type lli_tx_list[2]; - DMA_LLI_Ctrl_Type lli_rx_list[2]; - uint8_t *lli_tx_buffer; - uint32_t lli_tx_buffer_size; - uint8_t *lli_rx_buffer; - uint32_t lli_rx_buffer_size; - - int is_underrun; - int is_overflow; - audio_callback_tx_ready_t usr_cb; - audio_callback_rx_ready_t usr_rx_cb; - void *p_usr_arg; - void *p_usr_rx_arg; - - Audio_Samplerate_Type samplerate; - Audio_BitWidth_Type playBitWidth; - Audio_Channel_Type tx_channel; - Audio_Channel_Type rx_channel; - uint8_t rx_enable; - -} bl_audio_dev_t; - -int bl_audio_init (bl_audio_dev_t *p_dev); - -int bl_audio_deinit (bl_audio_dev_t *p_dev); - -int bl_audio_start (bl_audio_dev_t *p_dev); - -int bl_audio_stop (bl_audio_dev_t *p_dev); - -int bl_audio_tx_buffer_config (bl_audio_dev_t *p_dev, - void **ptr_mem, - uint32_t bufsize); - -int bl_audio_rx_buffer_config (bl_audio_dev_t *p_dev, - void **ptr_mem, - uint32_t bufsize); - -int bl_audio_tx_ready_config(bl_audio_dev_t *p_dev, - audio_callback_tx_ready_t cb, - void *p_arg); - -int bl_audio_rx_ready_config(bl_audio_dev_t *p_dev, - audio_callback_rx_ready_t cb, - void *p_arg); - -int bl_audio_samplerate_set (bl_audio_dev_t *p_dev, - Audio_Samplerate_Type samplerate); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_boot2.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_boot2.c deleted file mode 100644 index 78abe66492..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_boot2.c +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include -#include -#include -PtTable_Error_Type PtTable_Update_Entry(const SPI_Flash_Cfg_Type *pFlashCfg, - PtTable_ID_Type targetTableID, - PtTable_Stuff_Config *ptStuff, - PtTable_Entry_Config *ptEntry) -{ - uint32_t i=0; - BL_Err_Type ret; - uint32_t writeAddr; - uint32_t entriesLen; - PtTable_Config *ptTable; - PtTable_Entry_Config *ptEntries; - uint32_t *pCrc32; - - if(ptEntry==NULL||ptStuff==NULL){ - return PT_ERROR_PARAMETER; - } - - ptTable=&ptStuff->ptTable; - ptEntries=ptStuff->ptEntries; - - if(targetTableID==PT_TABLE_ID_INVALID){ - return PT_ERROR_TABLE_NOT_VALID; - } - - if(targetTableID==PT_TABLE_ID_0){ - writeAddr=BFLB_PT_TABLE0_ADDRESS; - }else{ - writeAddr=BFLB_PT_TABLE1_ADDRESS; - } - for (i=0; i < ptTable->entryCnt; i++) { - if (ptEntries[i].type == ptEntry->type){ - memcpy(&ptEntries[i],ptEntry,sizeof(PtTable_Entry_Config)); - break; - } - } - if(i==ptTable->entryCnt){ - /* Not found this entry ,add new one */ - if(ptTable->entryCntentryCnt],ptEntry,sizeof(PtTable_Entry_Config)); - ptTable->entryCnt++; - }else{ - return PT_ERROR_ENTRY_UPDATE_FAIL; - } - } - - /* Prepare write back to flash */ - /* Update age */ - ptTable->age++; - ptTable->crc32=BFLB_Soft_CRC32((uint8_t*)ptTable,sizeof(PtTable_Config)-4); - - /* Update entries CRC */ - entriesLen=ptTable->entryCnt*sizeof(PtTable_Entry_Config); - pCrc32=(uint32_t *)((uint32_t)ptEntries+entriesLen); - *pCrc32=BFLB_Soft_CRC32((uint8_t *)&ptEntries[0],entriesLen); - - /* Write back to flash */ - /* Erase flash first */ - ret=bl_flash_erase(writeAddr,sizeof(PtTable_Config)+entriesLen+4); - if(ret!=SUCCESS){ - //MSG_ERR("Flash Erase error\r\n"); - return PT_ERROR_FALSH_WRITE; - } - /* Write flash */ - ret=bl_flash_write(writeAddr,(uint8_t *)ptStuff,sizeof(PtTable_Stuff_Config)); - if(ret!=SUCCESS){ - //MSG_ERR("Flash Write error\r\n"); - return PT_ERROR_FALSH_WRITE; - } - - return PT_ERROR_SUCCESS; -} - -PtTable_Error_Type PtTable_Get_Active_Entries(PtTable_Stuff_Config *ptStuff, - PtTable_Entry_Type type, - PtTable_Entry_Config *ptEntry) -{ - uint32_t i=0; - - if(ptStuff==NULL||ptEntry==NULL){ - return PT_ERROR_PARAMETER; - } - for (i=0; i < ptStuff->ptTable.entryCnt; i++) { - if (ptStuff->ptEntries[i].type == type){ - memcpy(ptEntry,&ptStuff->ptEntries[i],sizeof(PtTable_Entry_Config)); - return PT_ERROR_SUCCESS; - } - } - return PT_ERROR_ENTRY_NOT_FOUND; -} - -PtTable_Error_Type PtTable_Get_Active_Entries_By_Name(PtTable_Stuff_Config *ptStuff, - uint8_t *name, - PtTable_Entry_Config *ptEntry) -{ - uint32_t i=0; - uint32_t len=strlen((char *)name); - - if(ptStuff==NULL||ptEntry==NULL){ - return PT_ERROR_PARAMETER; - } - for (i=0; i < ptStuff->ptTable.entryCnt; i++) { - if (strlen((char *)ptStuff->ptEntries[i].name) == len && - memcmp((char *)ptStuff->ptEntries[i].name,(char *)name,len) == 0){ - //BL602_MemCpy_Fast(ptEntry,&ptStuff->ptEntries[i],sizeof(PtTable_Entry_Config)); - /*FIXME :need fast memory copy*/ - memcpy(ptEntry,&ptStuff->ptEntries[i],sizeof(PtTable_Entry_Config)); - return PT_ERROR_SUCCESS; - } - } - return PT_ERROR_ENTRY_NOT_FOUND; -} - diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_boot2.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_boot2.h deleted file mode 100644 index 04f5747ce1..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_boot2.h +++ /dev/null @@ -1,197 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __BL606_PARTITION_H__ -#define __BL606_PARTITION_H__ - -#include - -//FIXME no BL808/BL606p header file including is Allowed here -#ifdef BL808 -#include -#include -#elif defined(BL606P) -#include -#include -#else -#error "Use CHIP BL808/BL606P for this module" -#endif - -/** @addtogroup BL606_Common_Driver - * @{ - */ - -/** @addtogroup PARTITION - * @{ - */ - -/** @defgroup PARTITION_Public_Types - * @{ - */ - -/** - * @brief Partition table error type definition - */ -typedef enum { - PT_ERROR_SUCCESS, /*!< Partition table error type:success */ - PT_ERROR_TABLE_NOT_VALID, /*!< Partition table error type:entry not found */ - PT_ERROR_ENTRY_NOT_FOUND, /*!< Partition table error type:entry not found */ - PT_ERROR_ENTRY_UPDATE_FAIL, /*!< Partition table error type:entry update fail */ - PT_ERROR_CRC32, /*!< Partition table error type:crc32 error */ - PT_ERROR_PARAMETER, /*!< Partition table error type:input parameter error */ - PT_ERROR_FALSH_READ, /*!< Partition table error type:flash read error */ - PT_ERROR_FALSH_WRITE, /*!< Partition table error type:flash write error */ - PT_ERROR_FALSH_ERASE, /*!< Partition table error type:flash erase error */ -}PtTable_Error_Type; - -/** - * @brief Partition id type definition - */ -typedef enum { - PT_TABLE_ID_0, /*!< Partition table ID 0 */ - PT_TABLE_ID_1, /*!< Partition table ID 1 */ - PT_TABLE_ID_INVALID, /*!< Partition table ID invalid */ -}PtTable_ID_Type; - -/** - * @brief Partition id type definition - */ -typedef enum { - PT_ENTRY_FW_CPU0, /*!< Partition entry type:CPU0 firmware */ - PT_ENTRY_FW_CPU1, /*!< Partition entry type:CPU1 firmware */ - PT_ENTRY_MAX=16, /*!< Partition entry type:Max */ -}PtTable_Entry_Type; - -/** - * @brief Partition table config definition - */ -typedef struct { - uint32_t magicCode; /*!< Partition table magic code */ - uint16_t version; /*!< Partition table verdion */ - uint16_t entryCnt; /*!< Partition table entry count */ - uint32_t age; /*!< Partition table age */ - uint32_t crc32; /*!< Partition table CRC32 value */ -}PtTable_Config; - -/** - * @brief Partition table entry config definition - */ -typedef struct { - uint8_t type; /*!< Partition entry type */ - uint8_t device; /*!< Partition entry device */ - uint8_t activeIndex; /*!< Partition entry active index */ - uint8_t name[9]; /*!< Partition entry name */ - uint32_t Address[2]; /*!< Partition entry start address */ - uint32_t maxLen[2]; /*!< Partition entry max length */ - uint32_t len; /*!< Partition entry length */ - uint32_t age; /*!< Partition entry age */ -}PtTable_Entry_Config; - -/** - * @brief Partition table stuff config definition - */ -typedef struct { - PtTable_Config ptTable; /*!< Partition table */ - PtTable_Entry_Config ptEntries[PT_ENTRY_MAX]; /*!< Partition entries */ - uint32_t crc32; /*!< Partition entries crc32 */ -}PtTable_Stuff_Config; - -/*@} end of group PARTITION_Public_Types */ - -/** @defgroup PARTITION_Public_Constants - * @{ - */ - -/** @defgroup PTTABLE_ERROR_TYPE - * @{ - */ -#define IS_PTTABLE_ERROR_TYPE(type) (((type) == PT_ERROR_SUCCESS) || \ - ((type) == PT_ERROR_TABLE_NOT_VALID) || \ - ((type) == PT_ERROR_ENTRY_NOT_FOUND) || \ - ((type) == PT_ERROR_ENTRY_UPDATE_FAIL) || \ - ((type) == PT_ERROR_CRC32) || \ - ((type) == PT_ERROR_PARAMETER) || \ - ((type) == PT_ERROR_FALSH_READ) || \ - ((type) == PT_ERROR_FALSH_WRITE) || \ - ((type) == PT_ERROR_FALSH_ERASE)) - -/** @defgroup PTTABLE_ID_TYPE - * @{ - */ -#define IS_PTTABLE_ID_TYPE(type) (((type) == PT_TABLE_ID_0) || \ - ((type) == PT_TABLE_ID_1) || \ - ((type) == PT_TABLE_ID_INVALID)) - -/** @defgroup PTTABLE_ENTRY_TYPE - * @{ - */ -#define IS_PTTABLE_ENTRY_TYPE(type) (((type) == PT_ENTRY_FW_CPU0) || \ - ((type) == PT_ENTRY_FW_CPU1) || \ - ((type) == PT_ENTRY_MAX)) - -/*@} end of group PARTITION_Public_Constants */ - -/** @defgroup PARTITION_Public_Macros - * @{ - */ -#define BFLB_PT_TABLE0_ADDRESS 0xE000 -#define BFLB_PT_TABLE1_ADDRESS 0xF000 -#define BFLB_PT_MAGIC_CODE 0x54504642 -typedef BL_Err_Type (*pPtTable_Flash_Erase)(uint32_t startaddr,uint32_t endaddr); -typedef BL_Err_Type (*pPtTable_Flash_Write)(uint32_t addr,uint8_t *data, uint32_t len); -typedef BL_Err_Type (*pPtTable_Flash_Read)(uint32_t addr,uint8_t *data, uint32_t len); - -/*@} end of group PARTITION_Public_Macros */ - -/** @defgroup PARTITION_Public_Functions - * @{ - */ -void PtTable_Set_Flash_Operation(pPtTable_Flash_Erase erase,pPtTable_Flash_Write write); -PtTable_ID_Type PtTable_Get_Active_Partition(const SPI_Flash_Cfg_Type *pFlashCfg, - PtTable_Stuff_Config ptStuff[2]); -PtTable_Error_Type PtTable_Get_Active_Entries(PtTable_Stuff_Config *ptStuff, -PtTable_Entry_Type type, - PtTable_Entry_Config *ptEntry); -PtTable_Error_Type PtTable_Update_Entry(const SPI_Flash_Cfg_Type *pFlashCfg, -PtTable_ID_Type targetTableID, - PtTable_Stuff_Config *ptStuff, -PtTable_Entry_Config *ptEntry); -PtTable_Error_Type PtTable_Create(const SPI_Flash_Cfg_Type *pFlashCfg,PtTable_ID_Type ptID); -PtTable_Error_Type PtTable_Get_Active_Entries_By_Name(PtTable_Stuff_Config *ptStuff, - uint8_t *name, - PtTable_Entry_Config *ptEntry); - -/*@} end of group PARTITION_Public_Functions */ - -/*@} end of group PARTITION */ - -/*@} end of group BL606_Common_Driver */ - -#endif /* __BL606_PARTITION_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_cam.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_cam.c deleted file mode 100644 index 3af88bcfce..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_cam.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include -#include -#include "bl_cam.h" - -#define MJPEG_DEFAULT_ADDR 0x80400000 - -int bl_cam_mjpeg_buffer_info_get(uint32_t *mjpeg_addr, uint32_t *mjpeg_size) -{ - int ret = 0; - uint32_t tmpVal; - - *mjpeg_addr = BL_RD_REG(MJPEG_BASE, MJPEG_JPEG_FRAME_ADDR); - if (*mjpeg_addr == MJPEG_DEFAULT_ADDR) { - *mjpeg_addr = 0; - ret = -1; - goto exit; - } - - tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_1); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, MJPEG_REG_W_XLEN); - /*get memory brust size 0 sigle; 1 INCR4; 2 INCR8; 3 INCR16*/ - *mjpeg_size = BL_RD_REG(MJPEG_BASE, MJPEG_JPEG_STORE_MEMORY); - *mjpeg_size = *mjpeg_size << (3 + tmpVal + (tmpVal > 0 ? 1 : 0)); - -exit: - return ret; -} - -int bl_cam_mjpeg_get(uint8_t **ptr, uint32_t *len) -{ - int ret = 0; - MJPEG_Frame_Info mjpeg_info; - MJPEG_Get_Frame_Info(&mjpeg_info); - - if (mjpeg_info.validFrames > 0) { - *ptr = (uint8_t *)(uintptr_t)mjpeg_info.curFrameAddr; - *len = mjpeg_info.curFrameBytes; - } else { - ret = -1; - } - return ret; -} - -int bl_cam_mjpeg_pop(void) -{ - MJPEG_Pop_Frame(); - return 0; -} - diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_cam.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_cam.h deleted file mode 100644 index 4860fc47b5..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_cam.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __BL_CAM_H__ -#define __BL_CAM_H__ -int bl_cam_mjpeg_get(uint8_t **ptr, uint32_t *len); -int bl_cam_mjpeg_pop(); -int bl_cam_mjpeg_buffer_info_get(uint32_t *mjpeg_addr, uint32_t *mjpeg_size); -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_chip.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_chip.c deleted file mode 100644 index b0ae92815c..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_chip.c +++ /dev/null @@ -1,188 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include - -#include "bl_chip.h" - -static unsigned long _risc_isa_info(void) -{ - volatile unsigned long misa = 0; - - __asm volatile( "csrr %0, misa" : "=r"( misa ) ); - - return misa; -} - - -int bl_chip_info(char *info) -{ - unsigned long misa; - int i; - i = sizeof(misa) * 8 - 2; // MXL field pos - - misa = _risc_isa_info(); - - /*Get base ISA*/ - i = (misa >> i); - switch (i) { - case 1: - { - memcpy(info, "RV32", 4); - info += 4; - } - break; - case 2: - { - memcpy(info, "RV64", 4); - info += 4; - } - break; - case 3: - { - memcpy(info, "RV128", 5); - info += 5; - } - break; - default: - { - memcpy(info, "RVxx", 4); - info += 4; - } - break; - } - - /*add switch*/ - *(info++) = '-'; - - /*add feature set*/ - for (i = 0; i < 26; i++) { - if (misa & (1 << i)) { - /*Feature bit is set*/ - *(info++) = ('A' + i); - } - } - *info = '\0'; - - return 0; -} - -static const char bannder_shadow_bl602[] = { - 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, - 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x95, 0x97, 0x20, 0xe2, 0x96, - 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x95, 0x97, 0x20, 0x20, 0x20, 0x20, 0x20, - 0x20, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, - 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x95, 0x97, 0x20, 0x20, - 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, - 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x95, 0x97, 0x20, 0xe2, 0x96, - 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, - 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x95, 0x97, 0x0a, 0x0d, 0xe2, 0x96, 0x88, 0xe2, - 0x96, 0x88, 0xe2, 0x95, 0x94, 0xe2, 0x95, 0x90, 0xe2, 0x95, 0x90, 0xe2, - 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x95, 0x97, 0xe2, 0x96, 0x88, 0xe2, - 0x96, 0x88, 0xe2, 0x95, 0x91, 0x20, 0x20, 0x20, 0x20, 0x20, 0xe2, 0x96, - 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x95, 0x94, 0xe2, 0x95, 0x90, 0xe2, 0x95, - 0x90, 0xe2, 0x95, 0x90, 0xe2, 0x95, 0x90, 0xe2, 0x95, 0x9d, 0x20, 0xe2, - 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x95, 0x94, 0xe2, 0x95, 0x90, 0xe2, - 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, - 0x95, 0x97, 0xe2, 0x95, 0x9a, 0xe2, 0x95, 0x90, 0xe2, 0x95, 0x90, 0xe2, - 0x95, 0x90, 0xe2, 0x95, 0x90, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, - 0x95, 0x97, 0x0a, 0x0d, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, - 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x95, 0x94, - 0xe2, 0x95, 0x9d, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x95, 0x91, - 0x20, 0x20, 0x20, 0x20, 0x20, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, - 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, - 0x96, 0x88, 0xe2, 0x95, 0x97, 0x20, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, - 0xe2, 0x95, 0x91, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x95, 0x94, - 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x95, 0x91, 0x20, 0xe2, 0x96, - 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, - 0x88, 0xe2, 0x95, 0x94, 0xe2, 0x95, 0x9d, 0x0a, 0x0d, 0xe2, 0x96, 0x88, 0xe2, - 0x96, 0x88, 0xe2, 0x95, 0x94, 0xe2, 0x95, 0x90, 0xe2, 0x95, 0x90, 0xe2, - 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x95, 0x97, 0xe2, 0x96, 0x88, 0xe2, - 0x96, 0x88, 0xe2, 0x95, 0x91, 0x20, 0x20, 0x20, 0x20, 0x20, 0xe2, 0x96, - 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x95, 0x94, 0xe2, 0x95, 0x90, 0xe2, 0x95, - 0x90, 0xe2, 0x95, 0x90, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x95, - 0x97, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, - 0x88, 0xe2, 0x95, 0x94, 0xe2, 0x95, 0x9d, 0xe2, 0x96, 0x88, 0xe2, 0x96, - 0x88, 0xe2, 0x95, 0x91, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x95, - 0x94, 0xe2, 0x95, 0x90, 0xe2, 0x95, 0x90, 0xe2, 0x95, 0x90, 0xe2, 0x95, - 0x9d, 0x0a, 0x0d, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, - 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x95, 0x94, 0xe2, - 0x95, 0x9d, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, - 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, - 0x95, 0x97, 0xe2, 0x95, 0x9a, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, - 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, - 0x95, 0x94, 0xe2, 0x95, 0x9d, 0xe2, 0x95, 0x9a, 0xe2, 0x96, 0x88, 0xe2, - 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, - 0x96, 0x88, 0xe2, 0x95, 0x94, 0xe2, 0x95, 0x9d, 0xe2, 0x96, 0x88, 0xe2, - 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, - 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x95, 0x97, 0x0a, 0x0d, 0xe2, 0x95, 0x9a, - 0xe2, 0x95, 0x90, 0xe2, 0x95, 0x90, 0xe2, 0x95, 0x90, 0xe2, 0x95, 0x90, - 0xe2, 0x95, 0x90, 0xe2, 0x95, 0x9d, 0x20, 0xe2, 0x95, 0x9a, 0xe2, 0x95, - 0x90, 0xe2, 0x95, 0x90, 0xe2, 0x95, 0x90, 0xe2, 0x95, 0x90, 0xe2, 0x95, - 0x90, 0xe2, 0x95, 0x90, 0xe2, 0x95, 0x9d, 0x20, 0xe2, 0x95, 0x9a, 0xe2, - 0x95, 0x90, 0xe2, 0x95, 0x90, 0xe2, 0x95, 0x90, 0xe2, 0x95, 0x90, 0xe2, - 0x95, 0x90, 0xe2, 0x95, 0x9d, 0x20, 0x20, 0xe2, 0x95, 0x9a, 0xe2, 0x95, - 0x90, 0xe2, 0x95, 0x90, 0xe2, 0x95, 0x90, 0xe2, 0x95, 0x90, 0xe2, 0x95, - 0x90, 0xe2, 0x95, 0x9d, 0x20, 0xe2, 0x95, 0x9a, 0xe2, 0x95, 0x90, 0xe2, - 0x95, 0x90, 0xe2, 0x95, 0x90, 0xe2, 0x95, 0x90, 0xe2, 0x95, 0x90, 0xe2, - 0x95, 0x90, 0xe2, 0x95, 0x9d, 0x0a, 0x0d, 0x00 -}; - -int bl_chip_banner(const char **banner) -{ - *banner = bannder_shadow_bl602; - return 0; -} - -int bl_chip_memory_ram(int *num, unsigned int addr[], unsigned int size[], char desc[][6]) -{ - return -1; -#if 0 - if (*num < 3) { - /*only one block memory*/ - return -1; - } - *num = 3; - -extern uint8_t _ld_ram_size0, _ld_ram_addr0; -extern uint8_t _ld_ram_size1, _ld_ram_addr1; -extern uint8_t _ld_ram_size2, _ld_ram_addr2; - addr[0] = (unsigned int)&_ld_ram_addr0; - size[0] = (unsigned int)&_ld_ram_size0; - strcpy(desc[0], "flash"); - addr[1] = (unsigned int)&_ld_ram_addr1; - size[1] = (unsigned int)&_ld_ram_size1; - strcpy(desc[1], "tcm"); - addr[2] = (unsigned int)&_ld_ram_addr2; - size[2] = (unsigned int)&_ld_ram_size2; - strcpy(desc[2], "wifi"); - return 0; -#endif -} diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_chip.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_chip.h deleted file mode 100644 index 3f8744eea4..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_chip.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __BL_CHIP_H__ -#define __BL_CHIP_H__ -int bl_chip_info(char *info); -int bl_chip_banner(const char **banner); -int bl_chip_memory_ram(int *num, unsigned int addr[], unsigned int size[], char desc[][6]); -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_efuse.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_efuse.c deleted file mode 100644 index 80a9015464..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_efuse.c +++ /dev/null @@ -1,127 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "bl_efuse.h" -#ifdef BL808 -#include -#include "bl808_mfg_media.h" -#include "bl808_glb.h" -#endif - -int bl_efuse_read_mac(uint8_t mac[6]) -{ - EF_Ctrl_Read_MAC_Address(mac); - return 0; -} - -int bl_efuse_read_mac_factory(uint8_t mac[6]) -{ - // if (0 == mfg_media_read_macaddr(mac, 1)) { - // return 0; - //zys } - return -1; -} - -int bl_efuse_read_capcode(uint8_t *capcode) -{ -// if (0 == mfg_media_read_xtal_capcode(capcode, 1)) { - // return 0; - //zys } - return -1; -} - -int bl_efuse_read_pwroft(int8_t poweroffset[14]) -{ - // if (0 == mfg_media_read_poweroffset(poweroffset, 1)) { - // return 0; - //} - return -1; -} - -int bl_efuse_ctrl_program_R0(uint32_t index, uint32_t *data, uint32_t len) -{ - uint8_t hdiv=0, bdiv=0; - HBN_MCU_ROOT_CLK_Type rtClk=(HBN_MCU_ROOT_CLK_Type)HBN_Get_MCU_Root_CLK_Sel(); - -// bdiv=GLB_Get_BCLK_Div(); -// hdiv=GLB_Get_HCLK_Div(); - hdiv = BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_SYS_CFG0), GLB_REG_HCLK_DIV); - bdiv = BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_SYS_CFG0), GLB_REG_BCLK_DIV); - - HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK); - - EF_Ctrl_Program_Direct_R0(index, data, len); - - GLB_Set_System_CLK_Div(hdiv, bdiv); - HBN_Set_MCU_Root_CLK_Sel(rtClk); - - return 0; -} - -int bl_efuse_ctrl_read_R0(uint32_t index, uint32_t *data, uint32_t len) -{ - uint8_t hdiv=0, bdiv=0; - HBN_MCU_ROOT_CLK_Type rtClk=(HBN_MCU_ROOT_CLK_Type)HBN_Get_MCU_Root_CLK_Sel(); - -// bdiv=GLB_Get_BCLK_Div(); -// hdiv=GLB_Get_HCLK_Div(); - hdiv = BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_SYS_CFG0), GLB_REG_HCLK_DIV); - bdiv = BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_SYS_CFG0), GLB_REG_BCLK_DIV); - - - HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK); - - EF_Ctrl_Read_Direct_R0(index, data, len); - - GLB_Set_System_CLK_Div(hdiv, bdiv); - HBN_Set_MCU_Root_CLK_Sel(rtClk); - - return 0; -} - -int bl_efuse_read_mac_opt(uint8_t slot, uint8_t mac[6], uint8_t reload) -{ - uint8_t hdiv=0, bdiv=0; - HBN_MCU_ROOT_CLK_Type rtClk=(HBN_MCU_ROOT_CLK_Type)HBN_Get_MCU_Root_CLK_Sel(); - -// bdiv=GLB_Get_BCLK_Div(); -// hdiv=GLB_Get_HCLK_Div(); - hdiv = BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_SYS_CFG0), GLB_REG_HCLK_DIV); - bdiv = BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_SYS_CFG0), GLB_REG_BCLK_DIV); - - HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK); - -// EF_Ctrl_Read_MAC_Address_Opt(slot, mac, reload); - EF_Ctrl_Read_MAC_Address_Raw(mac); - - GLB_Set_System_CLK_Div(hdiv, bdiv); - HBN_Set_MCU_Root_CLK_Sel(rtClk); - - return 0; -} diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_efuse.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_efuse.h deleted file mode 100644 index 48a6bc864e..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_efuse.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __BL_EFUSE_H__ -#define __BL_EFUSE_H__ -#include -int bl_efuse_read_mac(uint8_t mac[6]); -int bl_efuse_read_mac_factory(uint8_t mac[6]); -int bl_efuse_read_capcode(uint8_t *capcode); -int bl_efuse_read_pwroft(int8_t poweroffset[14]); -int bl_efuse_ctrl_program_R0(uint32_t index, uint32_t *data, uint32_t len); -int bl_efuse_ctrl_read_R0(uint32_t index, uint32_t *data, uint32_t len); -int bl_efuse_read_mac_opt(uint8_t slot, uint8_t mac[6], uint8_t reload); -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_ethernetif.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_ethernetif.c deleted file mode 100644 index b5e463da8b..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_ethernetif.c +++ /dev/null @@ -1,746 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* Includes ------------------------------------------------------------------*/ -#include "lwip/opt.h" -#include "lwip/timeouts.h" -#include "lwip/netif.h" -#include "lwip/err.h" -#define LWIP_DHCP 1 -#if LWIP_DHCP -#include "lwip/dhcp.h" -#endif -#include "netif/etharp.h" -#include "bl_ethernetif.h" -#include -#include "hal_emac.h" -#include -#include "semphr.h" -#if CTX_TYPE -#include -#endif -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Network interface name */ -#define IFNAME0 'b' -#define IFNAME1 'l' - -#define ETH_DMA_TRANSMIT_TIMEOUT (20U) - -#define BL702_EMAC 0 -#define EMAC_OUTPUT BL702_EMAC - -#if LWIP_DHCP -#define MAX_DHCP_TRIES 4 -uint32_t DHCPfineTimer = 0; -uint8_t DHCP_state = DHCP_OFF; -// #else -/*Static IP ADDRESS: IP_ADDR0.IP_ADDR1.IP_ADDR2.IP_ADDR3 */ -#define IP_ADDR0 (uint8_t)192 -#define IP_ADDR1 (uint8_t)168 -#define IP_ADDR2 (uint8_t)10 -#define IP_ADDR3 (uint8_t)221 - -/*NETMASK*/ -#define NETMASK_ADDR0 (uint8_t)255 -#define NETMASK_ADDR1 (uint8_t)255 -#define NETMASK_ADDR2 (uint8_t)255 -#define NETMASK_ADDR3 (uint8_t)0 - -/*Gateway Address*/ -#define GW_ADDR0 (uint8_t)192 -#define GW_ADDR1 (uint8_t)168 -#define GW_ADDR2 (uint8_t)10 -#define GW_ADDR3 (uint8_t)1 -#endif - -#if CTX_TYPE -extern EMAC_Handle_Type *thiz; -eth_context *ctx = NULL; -TaskHandle_t DequeueTaskHandle; -TaskHandle_t OutputTaskHandle; -#endif -/* Private function prototypes -----------------------------------------------*/ -void pbuf_free_custom(struct pbuf *p); -void ethernetif_input(struct netif *netif); -SemaphoreHandle_t emac_rx_sem = NULL; -static StackType_t emac_rx_stack[256]; -static StaticTask_t emac_rx_handle; -#if LWIP_DHCP -static StackType_t emac_dhcp_stack[256]; -static StaticTask_t emac_dhcp_handle; -#endif -static uint8_t emac_rx_buffer[ETH_RX_BUFFER_SIZE] __attribute__((aligned(16))) = { 0 }; - -LWIP_MEMPOOL_DECLARE(RX_POOL, 10, sizeof(struct pbuf_custom), "Zero-copy RX PBUF pool"); - -/* Private functions ---------------------------------------------------------*/ -/******************************************************************************* - LL Driver Interface ( LwIP stack --> ETH) -*******************************************************************************/ -/** - * @brief In this function, the hardware should be initialized. - * Called from ethernetif_init(). - * - * @param netif the already initialized lwip network interface structure - * for this ethernetif - */ -extern void emac_init_txrx_buffer(void); -extern int emac_phy_init(emac_phy_cfg_t *cfg); - -/* For emac tx and rx,we put here to make controlling it's size easy */ -#define ETH_RXBUFNB 6 -#define ETH_TXBUFNB 4 -#define ATTR_NOCACHE_RAM_SECTION __attribute__((section(".nocache_ram"))) -ATTR_NOCACHE_RAM_SECTION ATTR_EALIGN(4) uint8_t ethRxBuff[ETH_RXBUFNB][ETH_RX_BUFFER_SIZE] ATTR_EALIGN(4) = { 0 }; /* Ethernet Receive Buffers */ -ATTR_NOCACHE_RAM_SECTION ATTR_EALIGN(4) uint8_t ethTxBuff[ETH_TXBUFNB][ETH_TX_BUFFER_SIZE] ATTR_EALIGN(4); /* Ethernet Transmit Buffers */ -void emac_init_txrx_buffer(void) -{ -#if CTX_TYPE - ctx = pvPortMalloc(sizeof(eth_context)); - memset(ctx, 0, sizeof(eth_context)); - utils_list_init(&ctx->unsent); -#endif - - emac_bd_init((uint8_t *)ethTxBuff, ETH_TXBUFNB, (uint8_t *)ethRxBuff, ETH_RXBUFNB); -} -void dhcp_thread(void const *argument); -void low_level_init(struct netif *netif) -{ - int ret = 0; - - emac_device_t emac_cfg = { - .mac_addr[0] = 0x18, - .mac_addr[1] = 0xB9, - .mac_addr[2] = 0x05, - .mac_addr[3] = 0x12, - .mac_addr[4] = 0x34, - .mac_addr[5] = 0x56, - }; - - /* set phy cfg */ - emac_phy_cfg_t phy_cfg = { - .auto_negotiation = 1, /*!< Speed and mode auto negotiation */ - .full_duplex = 0, /*!< Duplex mode */ - .speed = 0, /*!< Speed mode */ - .phy_address = 1, /*!< PHY address */ - .phy_id = 0x7c0f0, /*!< PHY OUI, masked */ - .phy_state = PHY_STATE_DOWN, - }; - - /* set MAC hardware address length */ - netif->hwaddr_len = ETH_HWADDR_LEN; - - /* set MAC hardware address */ - netif->hwaddr[0] = emac_cfg.mac_addr[0]; - netif->hwaddr[1] = emac_cfg.mac_addr[1]; - netif->hwaddr[2] = emac_cfg.mac_addr[2]; - netif->hwaddr[3] = emac_cfg.mac_addr[3]; - netif->hwaddr[4] = emac_cfg.mac_addr[4]; - netif->hwaddr[5] = emac_cfg.mac_addr[5]; - - /* maximum transfer unit */ - netif->mtu = 1500; - - /* emac init,configure ethernet peripheral (GPIOs, clocks, MAC, DMA) */ - MSG("emac_init\r\n"); - emac_init(&emac_cfg); - - ret = emac_phy_init(&phy_cfg); - if (PHY_STATE_UP == phy_cfg.phy_state) { - MSG("PHY[%x] @%d ready on %dMbps, %s duplex\n\r", (int)phy_cfg.phy_id, (int)phy_cfg.phy_address, - (int)phy_cfg.speed, - phy_cfg.full_duplex ? "full" : "half"); - } else { - MSG("PHY Init fail\n\r"); - BL_CASE_FAIL; - while (1) - ; - } - emac_init_txrx_buffer(); - emac_start(); - // emac_start_tx(); - - /* device capabilities */ - /* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */ - netif->flags |= NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP; - - /* Initialize the RX POOL */ - LWIP_MEMPOOL_INIT(RX_POOL); - - /* create a binary semaphore used for informing ethernetif of frame reception */ - //vSemaphoreCreateBinary(emac_rx_sem); - emac_rx_sem = xSemaphoreCreateBinary(); - -#if !CTX_TYPE - /* create the task that handles the ETH_MAC */ - MSG("[OS] Starting emac rx task...\r\n"); - xTaskCreateStatic(ethernetif_input, (char *)"emac_rx_task", sizeof(emac_rx_stack) / 4, netif, 16, emac_rx_stack, &emac_rx_handle); -#endif -#if LWIP_DHCP - MSG("[OS] Starting emac dhcp task...\r\n"); - xTaskCreateStatic(dhcp_thread, (char *)"emac_dhcp_task", sizeof(emac_dhcp_stack) / 4, netif, 16, emac_dhcp_stack, &emac_dhcp_handle); -#endif - - if (ret == 0) { - MSG("[OS] %s Netif is up\r\n", netif->name); - netif_set_up(netif); - netif_set_link_up(netif); - } -} - -void emac_tx_error_callback_app() -{ - MSG("EMAC tx error callback\r\n"); -} - -void emac_rx_error_callback_app() -{ - MSG("EMAC rx error callback\r\n"); - // MSG("EMAC tx bd num 0x%x\r\n", BL_RD_WORD(0x4000D020)); - // MSG("EMAC rx bd description0 0x%x\r\n", BL_RD_WORD(0x4000D400 + ((5 + 5) * 8))); - // MSG("EMAC rx bd description1 0x%x\r\n", BL_RD_WORD(0x4000D400 + ((5 + 5) * 8) + 0x4)); -} -/** - * @brief This function should do the actual transmission of the packet. The packet is - * contained in the pbuf that is passed to the function. This pbuf - * might be chained. - * - * @param netif the lwip network interface structure for this ethernetif - * @param p the MAC packet to send (e.g. IP packet including MAC addresses and type) - * @return ERR_OK if the packet could be sent - * an err_t value if the packet couldn't be sent - * - * @note Returning ERR_MEM here if a DMA queue of your MAC is full can lead to - * strange results. You might consider waiting for space in the DMA queue - * to become available since the stack doesn't retry to send a packet - * dropped because of memory failure (except for the TCP timers). - */ - -static unsigned char emac_send_buf[1514]; -static err_t low_level_output(struct netif *netif, struct pbuf *p) -{ -#if CTX_TYPE - struct unsent_item *item; - - if (pbuf_header(p, PBUF_LINK_ENCAPSULATION_HLEN)) { - printf("[TX] Reserve room failed for header\r\n"); - return ERR_IF; - } - item = (struct unsent_item *)(((uintptr_t)(p->payload + 3))&(~3)); - item->p = p; - - pbuf_ref(p); - __disable_irq(); - utils_list_push_back(&ctx->unsent, (struct utils_list_hdr *)&(item->hdr)); - ctx->unsent_num++; - __enable_irq(); - xTaskNotify(DequeueTaskHandle, 0x01, eSetBits); - - return ERR_OK; -#else - err_t errval = ERR_OK; - struct pbuf *q; - - if (!emac_bd_fragment_support()){ - - uint32_t byteslefttocopy = 0; - // uint32_t payloadoffset = 0; - // uint32_t bufferoffset = 0; - uint32_t framelength = 0; - uint32_t flags = (EMAC_NORMAL_PACKET); - - for (q = p; q != NULL; q = q->next) { - // MSG("p->tot_len:%d,q->len:%d, q->next:%d,f:%d\r\n", q->tot_len, q->len, q->next, framelength); - - byteslefttocopy = q->len; - // payloadoffset = 0; - - // check is copy data is larger than emac tx buf - while ((byteslefttocopy + framelength) > ETH_TX_BUFFER_SIZE) { - // copy data to tx buf - MSG("tx buf is too larger!\r\n"); - flags = EMAC_FRAGMENT_PACKET; - // ARCH_MemCpy_Fast(&emac_send_buf[framelength + bufferoffset], q->payload + payloadoffset, (ETH_TX_BUFFER_SIZE - bufferoffset)); - } - ARCH_MemCpy_Fast(&emac_send_buf[framelength], q->payload, byteslefttocopy); - // bufferoffset = bufferoffset + byteslefttocopy; - framelength = framelength + byteslefttocopy; - } - - if (0 != emac_bd_tx_enqueue(flags, framelength, emac_send_buf)) { - MSG("emac_bd_tx_enqueue error!\r\n"); - return ERR_IF; - } - - }else{ - for (q = p; q != NULL; q = q->next) { - //MSG("p->tot_len:%d,q->len:%d, q->next:%d\r\n", q->tot_len, q->len, q->next); - if (q->len == q->tot_len) { - if (0 != emac_bd_tx_enqueue(EMAC_NORMAL_PACKET, q->len, q->payload)) { - MSG("emac_bd_tx_enqueue error!\r\n"); - return ERR_IF; - } - } else if (q->len < q->tot_len) { - if (0 != emac_bd_tx_enqueue(EMAC_FRAGMENT_PACKET, q->len, q->payload)) { - MSG("emac_bd_tx_enqueue error!\r\n"); - return ERR_IF; - } - } else { - MSG("low_level_output error! Wrong packet!\r\n"); - } - } - } - - return errval; -#endif -} - -/** - * @brief Should allocate a pbuf and transfer the bytes of the incoming - * packet from the interface into the pbuf. - * - * @param netif the lwip network interface structure for this ethernetif - * @return a pbuf filled with the received packet (including MAC header) - * NULL on memory error - */ -static struct pbuf *low_level_input(struct netif *netif) -{ -#if CTX_TYPE - uint16_t pkt_len; - uint16_t max_len, min_len; - struct pbuf *h = NULL; - EMAC_BD_Desc_Type *bd; - bd = &thiz->bd[thiz->rxIndexCPU]; - if(bd->C_S_L & EMAC_BD_FIELD_MSK(RX_E)){ - // MSG("RX BD is empty\r\n"); - h = NULL; - } else { - emac_get_fram_len(&max_len, &min_len); - pkt_len = (bd->C_S_L & EMAC_BD_FIELD_MSK(RX_LEN)) >> BD_RX_LEN_POS; - //check length - if (pkt_len > max_len) { - MSG("pkt is too huge %d\r\n", pkt_len); - return NULL; - } - if (bd->C_S_L & 0xFF) { - // MSG("RX bd %x\r\n", (int)bd->C_S_L & 0xFF); - } - if ((bd->C_S_L >>16) == ETH_MAX_BUFFER_SIZE) { - puts("Bug now...\r\n"); - } - - h = pbuf_alloc(PBUF_RAW, pkt_len, PBUF_POOL); - if (h) { - pbuf_take(h, bd->Buffer, pkt_len); - } - if ((++thiz->rxIndexCPU) > thiz->rxBuffLimit) { - /* wrap back */ - thiz->rxIndexCPU = thiz->txBuffLimit + 1; - bd->C_S_L = (EMAC_BD_FIELD_MSK(RX_IRQ) | EMAC_BD_FIELD_MSK(RX_E) | (ETH_MAX_BUFFER_SIZE << 16) | EMAC_BD_FIELD_MSK(RX_WR)); - } else { - bd->C_S_L = (EMAC_BD_FIELD_MSK(RX_IRQ) | EMAC_BD_FIELD_MSK(RX_E) | (ETH_MAX_BUFFER_SIZE << 16)); - } - } - return h; -#else - uint32_t rx_len = 0; - struct pbuf *p = NULL, *q; - - emac_bd_rx_dequeue(-1, &rx_len, emac_rx_buffer); - - if (rx_len <= 0) { - //MSG("Recv Null Data\r\n"); - return NULL; - } - - //MSG("Recv full Data\r\n"); - - p = pbuf_alloc(PBUF_RAW, rx_len, PBUF_POOL); - - if (p != NULL) { - for (q = p; q != NULL; q = q->next) { - memcpy(q->payload, emac_rx_buffer + rx_len - q->tot_len, q->len); - } - } - - return p; -#endif -} - -void emac_rx_done_callback_app(void) -{ - BaseType_t xHigherPriorityTaskWoken; - - /* Is it time for vATask() to run? */ - xHigherPriorityTaskWoken = pdFALSE; - //MSG("emac_rx_done_callback_app\r\n"); - //low_level_input(NULL); - xSemaphoreGiveFromISR(emac_rx_sem, &xHigherPriorityTaskWoken); - /* If xHigherPriorityTaskWoken was set to true you - we should yield. The actual macro used here is - port specific. */ - portYIELD_FROM_ISR(xHigherPriorityTaskWoken); -} - -#if CTX_TYPE -void ethernetif_output(struct netif *netif) -{ - struct unsent_item *item; - struct pbuf *q, *p; - EMAC_BD_Desc_Type *bd; - int wrap_found, offset; - - bd = &thiz->bd[thiz->txIndexCPU]; - while (0 == (bd->C_S_L & EMAC_BD_FIELD_MSK(TX_RD)) && ctx->unsent_num) { - - __disable_irq(); - item = (struct unsent_item *)utils_list_pop_front(&ctx->unsent); - ctx->unsent_num--; - __enable_irq(); - - p = item->p; - p->len -= PBUF_LINK_ENCAPSULATION_HLEN; - p->tot_len -= PBUF_LINK_ENCAPSULATION_HLEN; - p->payload += PBUF_LINK_ENCAPSULATION_HLEN; - if ((++thiz->txIndexCPU) > thiz->txBuffLimit) { - /* wrap back */ - thiz->txIndexCPU = 0; - wrap_found = 1; - } else { - wrap_found = 0; - } - - offset = 0; - for (q = p; q != NULL; q = q->next) { - memcpy((uint8_t *)bd->Buffer + offset, (uint8_t*)q->payload, q->len); - offset += q->len; - } - - bd->C_S_L = (wrap_found ? EMAC_BD_FIELD_MSK(TX_WR) : 0) | EMAC_TX_COMMON_FLAGS | p->tot_len << BD_TX_LEN_POS; - pbuf_free(p); - bd = &thiz->bd[thiz->txIndexCPU]; - } -} -#endif - -/** - * @brief This function is the ethernetif_input task, it is processed when a packet - * is ready to be read from the interface. It uses the function low_level_input() - * that should handle the actual reception of bytes from the network - * interface. Then the type of the received packet is determined and - * the appropriate input function is called. - * - * @param netif the lwip network interface structure for this ethernetif - */ -void ethernetif_input(struct netif *netif) -{ - struct pbuf *p = NULL; - -#if CTX_TYPE - static unsigned int rx_counter; - err_t err = ERR_OK; - EMAC_BD_Desc_Type *bd; - - /* move received packet into a new pbuf */ - do { - p = low_level_input(netif); - bd = &thiz->bd[thiz->rxIndexCPU]; - - rx_counter++; - /* no packet could be read, silently ignore this */ - if (p == NULL) return; - - /* entry point to the LwIP stack */ - err = netif->input(p, netif); - - if (err != ERR_OK) - { - LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_input: IP input error\n")); - pbuf_free(p); - } - } while (!(bd->C_S_L & EMAC_BD_FIELD_MSK(RX_E))); - return; -#else - for (;;) { - if (xSemaphoreTake(emac_rx_sem, portMAX_DELAY) == pdTRUE) { - do { - p = low_level_input(netif); - - if (p != NULL) { - if (netif->input(p, netif) != ERR_OK) { - pbuf_free(p); - } - } - } while (p != NULL); - } - } -#endif -} - -#if CTX_TYPE -void unsent_recv_task(void *pvParameters) -{ - struct netif *netif = (struct netif *)pvParameters; - uint32_t NotifyValue; - BaseType_t recv; - printf("unsent_recv_task.\r\n"); - while(1) { - NotifyValue = 0; - recv = xTaskNotifyWait(0, ULONG_MAX, &NotifyValue, 200); - if (recv == pdTRUE) { - if (NotifyValue & (1 << 0)) { - ethernetif_output(netif); - emac_intmask(EMAC_INT_TX_DONE, UNMASK); - } - if (NotifyValue & (1 << 1)) { - ethernetif_input(netif); - emac_intmask(EMAC_INT_RX_DONE, UNMASK); - } - } else { - /*XXX only work when we has no EVENT. Maybe buggy here??*/ - // _emac_phy_if_init(); - // printf("no EVENT!\r\n"); - } - } -} -#endif - -/** - * @brief Should be called at the beginning of the program to set up the - * network interface. It calls the function low_level_init() to do the - * actual setup of the hardware. - * - * This function should be passed as a parameter to netif_add(). - * - * @param netif the lwip network interface structure for this ethernetif - * @return ERR_OK if the loopif is initialized - * ERR_MEM if private data couldn't be allocated - * any other err_t on error - */ -err_t ethernetif_init(struct netif *netif) -{ - LWIP_ASSERT("netif != NULL", (netif != NULL)); - -#if LWIP_NETIF_HOSTNAME - /* Initialize interface hostname */ - netif->hostname = "lwip"; -#endif /* LWIP_NETIF_HOSTNAME */ - - netif->name[0] = IFNAME0; - netif->name[1] = IFNAME1; - /* We directly use etharp_output() here to save a function call. - * You can instead declare your own function an call etharp_output() - * from it if you have to do some checks before sending (e.g. if link - * is available...) */ - netif->output = etharp_output; - netif->linkoutput = low_level_output; - - /* initialize the hardware */ - low_level_init(netif); -#if CTX_TYPE - xTaskCreate(unsent_recv_task, (const char *)"Ontput_Unsent_queue", 1024, netif, 29, &DequeueTaskHandle); -#endif - - return ERR_OK; -} - -/** - * @brief Custom Rx pbuf free callback - * @param pbuf: pbuf to be freed - * @retval None - */ -void pbuf_free_custom(struct pbuf *p) -{ - struct pbuf_custom *custom_pbuf = (struct pbuf_custom *)p; - LWIP_MEMPOOL_FREE(RX_POOL, custom_pbuf); -} - -static void ethernet_set_static_ip(struct netif *netif) -{ - ip_addr_t ipaddr; - ip_addr_t netmask; - ip_addr_t gw; - - IP4_ADDR(&ipaddr, IP_ADDR0, IP_ADDR1, IP_ADDR2, IP_ADDR3); - IP4_ADDR(&netmask, NETMASK_ADDR0, NETMASK_ADDR1, NETMASK_ADDR2, NETMASK_ADDR3); - IP4_ADDR(&gw, GW_ADDR0, GW_ADDR1, GW_ADDR2, GW_ADDR3); - netif_set_addr(netif, ip_2_ip4(&ipaddr), ip_2_ip4(&netmask), ip_2_ip4(&gw)); -} - -/** - * @brief Notify the User about the network interface config status - * @param netif: the network interface - * @retval None - */ -void ethernet_link_status_updated(struct netif *netif) -{ - if (netif_is_link_up(netif)) { -#if LWIP_DHCP - /* Update DHCP state machine */ - DHCP_state = DHCP_START; - MSG("DHCP Start\r\n"); -#else - /* IP address default setting */ - ethernet_set_static_ip(netif); - uint8_t iptxt[20]; - sprintf((char *)iptxt, "%s", ip4addr_ntoa(netif_ip4_addr(netif))); - MSG("Static IP address: %s\r\n", iptxt); -#endif - } else { -#if LWIP_DHCP - /* Update DHCP state machine */ - DHCP_state = DHCP_LINK_DOWN; -#else - MSG("The network cable is not connected.\r\n"); -#endif /* LWIP_DHCP */ - } -} - -/** - * @brief - * @retval None - */ -void ethernet_link_check_state(struct netif *netif) -{ - emac_phy_status_t phy_state; - - uint32_t linkchanged = 0; - // uint32_t speed = 0, duplex = 0; - - phy_state = ethernet_phy_status_get(); - - if (netif_is_link_up(netif) && (phy_state <= EMAC_PHY_STAT_LINK_DOWN)) { - MSG("Link Down\n"); - emac_stop(); - netif_set_down(netif); - netif_set_link_down(netif); - } else if (!netif_is_link_up(netif) && (phy_state <= EMAC_PHY_STAT_LINK_DOWN)) { - MSG("Reinit\n"); - emac_phy_init(NULL); - } else if (!netif_is_link_up(netif) && (phy_state > EMAC_PHY_STAT_LINK_UP)) { - // switch (phy_state) { - // case EMAC_PHY_STAT_100MBITS_FULLDUPLEX: - // duplex = 1; - // speed = 100; - // linkchanged = 1; - // break; - - // case EMAC_PHY_STAT_100MBITS_HALFDUPLEX: - // duplex = 0; - // speed = 100; - // linkchanged = 1; - // break; - - // case EMAC_PHY_STAT_10MBITS_FULLDUPLEX: - // duplex = 1; - // speed = 10; - // linkchanged = 1; - // break; - - // case EMAC_PHY_STAT_10MBITS_HALFDUPLEX: - // duplex = 0; - // speed = 10; - // linkchanged = 1; - // break; - - // default: - // break; - // } - - if (linkchanged) { - /* Get MAC Config MAC */ - //HAL_ETH_GetMACConfig(&EthHandle, &MACConf); - //MACConf.DuplexMode = duplex; - //MACConf.Speed = speed; - //HAL_ETH_SetMACConfig(&EthHandle, &MACConf); - //HAL_ETH_Start(&EthHandle); - netif_set_up(netif); - netif_set_link_up(netif); - } - } -} - -#if LWIP_DHCP -/** - * @brief DHCP Process - * @param argument: network interface - * @retval None - */ -void dhcp_thread(void const *argument) -{ - struct netif *netif = (struct netif *)argument; - ip_addr_t ipaddr; - ip_addr_t netmask; - ip_addr_t gw; - struct dhcp *dhcp; - uint8_t iptxt[20]; - - for (;;) { - switch (DHCP_state) { - case DHCP_START: { - ip_addr_set_zero_ip4(&netif->ip_addr); - ip_addr_set_zero_ip4(&netif->netmask); - ip_addr_set_zero_ip4(&netif->gw); - DHCP_state = DHCP_WAIT_ADDRESS; - MSG("State: Looking for DHCP server ...\r\n"); - dhcp_start(netif); - } break; - case DHCP_WAIT_ADDRESS: { - if (dhcp_supplied_address(netif)) { - DHCP_state = DHCP_ADDRESS_ASSIGNED; - sprintf((char *)iptxt, "%s", ip4addr_ntoa(netif_ip4_addr(netif))); - MSG("IP address assigned by a DHCP server: %s\r\n", iptxt); - } else { - dhcp = (struct dhcp *)netif_get_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_DHCP); - - /* DHCP timeout */ - if (dhcp->tries > MAX_DHCP_TRIES) { - DHCP_state = DHCP_TIMEOUT; - - /* Static address used */ - ethernet_set_static_ip(netif); - sprintf((char *)iptxt, "%s", ip4addr_ntoa(netif_ip4_addr(netif))); - MSG("DHCP Timeout !!\r\n"); - MSG("Static IP address: %s\r\n", iptxt); - } - } - } break; - case DHCP_LINK_DOWN: { - DHCP_state = DHCP_OFF; - MSG("The network cable is not connected \r\n"); - } break; - default: - break; - } - vTaskDelay(100); - } -} -#endif /* LWIP_DHCP */ diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_ethernetif.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_ethernetif.h deleted file mode 100644 index 2f2746c124..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_ethernetif.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __ETHERNETIF_H__ -#define __ETHERNETIF_H__ -#include "hal_emac.h" -#if CTX_TYPE -#include -#endif -#include "lwip/err.h" -#include "lwip/netif.h" -#include "ethernet_phy.h" - -#define DHCP_OFF (uint8_t)0 -#define DHCP_START (uint8_t)1 -#define DHCP_WAIT_ADDRESS (uint8_t)2 -#define DHCP_ADDRESS_ASSIGNED (uint8_t)3 -#define DHCP_TIMEOUT (uint8_t)4 -#define DHCP_LINK_DOWN (uint8_t)5 - -#if CTX_TYPE -#define ETH_MAX_BUFFER_SIZE (ETH_MAX_PACKET_SIZE) -#define EMAC_TX_COMMON_FLAGS (EMAC_BD_FIELD_MSK(TX_RD) | \ - EMAC_BD_FIELD_MSK(TX_IRQ) | \ - EMAC_BD_FIELD_MSK(TX_PAD) | \ - EMAC_BD_FIELD_MSK(TX_CRC) | \ - EMAC_BD_FIELD_MSK(TX_EOF) ) - -struct unsent_item{ - struct utils_list_hdr hdr; - struct pbuf *p; -}; - -typedef struct { - struct utils_list unsent; - uint8_t Tx_free_bd_num; - uint8_t Rx_free_bd_num; - volatile uint16_t unsent_num; - uint32_t tx_pkt_cnt; - uint32_t rx_pkt_cnt; - uint32_t out_tmr; - uint32_t done_tmr; -}eth_context; -#endif -/* Exported types ------------------------------------------------------------*/ -err_t ethernetif_init(struct netif *netif); -void ethernet_link_check_state(struct netif *netif); -void ethernet_link_status_updated(struct netif *netif); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_flash.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_flash.c deleted file mode 100644 index eb6fcdec81..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_flash.c +++ /dev/null @@ -1,184 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#ifdef BL808 -#include -#include -#include -#include -#elif defined(BL606P) -#include -#include -#include -#include -#include -#else -#error "Use CHIP BL808/BL606P for this module" -#endif - -#include "bl_irq.h" - -#define XIP_START_ADDR (0x58000000) -#define ADDR_LIMIT (0x1000000) - -#define USER_UNUSED(a) ((void)(a)) -static SPI_Flash_Cfg_Type g_flash_cfg; - -/** - * @brief flash read data - * - * @param addr - * @param data - * @param len - * @return BL_Err_Type - */ -int ATTR_TCM_SECTION bl_flash_read(uint32_t startaddr, void *data, uint32_t len) -{ - BL_Err_Type stat; - uint8_t isAesEnable=0; - - GLOBAL_IRQ_SAVE(); - XIP_SFlash_Opt_Enter(&isAesEnable); - stat = XIP_SFlash_Read_Need_Lock(&g_flash_cfg, startaddr, data, len, 0, 0); - XIP_SFlash_Opt_Exit(isAesEnable); - GLOBAL_IRQ_RESTORE(); - - return stat; -} - -/** - * @brief flash write data - * - * @param addr - * @param data - * @param len - * @return BL_Err_Type - */ -int ATTR_TCM_SECTION bl_flash_write(uint32_t startaddr, void *data, uint32_t len) -{ - BL_Err_Type stat; - uint8_t isAesEnable=0; - - GLOBAL_IRQ_SAVE(); - XIP_SFlash_Opt_Enter(&isAesEnable); - stat = XIP_SFlash_Write_Need_Lock(&g_flash_cfg, startaddr, data, len, 0, 0); - XIP_SFlash_Opt_Exit(isAesEnable); - GLOBAL_IRQ_RESTORE(); - - return stat; -} - -/** - * @brief flash erase - * - * @param startaddr - * @param endaddr - * @return BL_Err_Type - */ -int ATTR_TCM_SECTION bl_flash_erase(uint32_t startaddr, uint32_t len) -{ - BL_Err_Type stat; - uint8_t isAesEnable=0; - - GLOBAL_IRQ_SAVE(); - XIP_SFlash_Opt_Enter(&isAesEnable); - stat = XIP_SFlash_Erase_Need_Lock(&g_flash_cfg, startaddr, len-1, 0, 0); - XIP_SFlash_Opt_Exit(isAesEnable); - GLOBAL_IRQ_RESTORE(); - - return stat; -} - -/** - * @brief flash read from xip - * - * @param xip addr - * @param dst - * @param len - * @return BL_Err_Type - */ -int bl_flash_read_byxip(uint32_t addr, uint8_t *dst, int len) -{ - uint32_t offset; - uint32_t xipaddr; - - offset = RomDriver_SF_Ctrl_Get_Flash_Image_Offset(0, 0); - - if ((addr < offset) || (addr >= ADDR_LIMIT)) { - // not support or arg err ? - return -1; - } - - xipaddr = XIP_START_ADDR - offset + addr; - memcpy(dst, (void *)xipaddr, len); - - return 0; -} - -/** - * @brief multi flash adapter - * - * @return BL_Err_Type - */ -int ATTR_TCM_SECTION bl_flash_init(void) -{ - uint8_t isAesEnable=0; - - /* Get flash config identify */ - GLOBAL_IRQ_SAVE(); - XIP_SFlash_Opt_Enter(&isAesEnable); - SF_Cfg_Flash_Identify_Ext(1, 0x80, 0, &g_flash_cfg, 0, 0); - XIP_SFlash_Opt_Exit(isAesEnable); - GLOBAL_IRQ_RESTORE(); - - return 0; -} - -static void _dump_flash_config() -{ - extern uint8_t __boot2_flashCfg_src; - - USER_UNUSED(__boot2_flashCfg_src); - - blog_info("======= FlashCfg magiccode @%p=======\r\n", &__boot2_flashCfg_src); - blog_info("mid \t\t0x%X\r\n", g_flash_cfg.mid); - blog_info("clkDelay \t0x%X\r\n", g_flash_cfg.clkDelay); - blog_info("clkInvert \t0x%X\r\n", g_flash_cfg.clkInvert); - blog_info("sector size\t%uKBytes\r\n", g_flash_cfg.sectorSize); - blog_info("page size\t%uBytes\r\n", g_flash_cfg.pageSize); - blog_info("---------------------------------------------------------------\r\n"); -} - -int bl_flash_config_update(void) -{ - _dump_flash_config(); - - return 0; -} diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_flash.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_flash.h deleted file mode 100644 index 1bf262137b..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_flash.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __BL_FLASH_H__ -#define __BL_FLASH_H__ -#include - -int bl_flash_erase(uint32_t addr, int len); -int bl_flash_write(uint32_t addr, void *src, int len); -int bl_flash_read(uint32_t addr, void *dst, int len); -int bl_flash_config_update(void); -void* bl_flash_get_flashCfg(void); - -int bl_flash_read_byxip(uint32_t addr, uint8_t *dst, int len); -int bl_flash_init(void); -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_ipc.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_ipc.c deleted file mode 100644 index 328841c527..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_ipc.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "bl_ipc.h" - -//FIXME no BL808/BL606p header file including is Allowed here -#ifdef BL808 -#include -#include -#elif defined(BL606P) -#include -#include -#else -#error "Use CHIP BL808/BL606P for this module" -#endif - - -extern void IPC_Common_Interrupt_Handler(uint32_t irqStatus, ipcIntCallback *callBack[GLB_CORE_ID_MAX -1]); -extern ipcIntCallback *m0IpcIntCbfArra[GLB_CORE_ID_MAX - 1]; - -static void ipc_m0_handler(void) -{ - uint32_t irqStatus; - irqStatus = IPC_M0_Get_Int_Raw_Status(); - IPC_Common_Interrupt_Handler(irqStatus, m0IpcIntCbfArra); - IPC_M0_Clear_Int_By_Word(irqStatus); -} -//FIXME no BL808/BL606p header file including is Allowed here -#ifdef BL808 -#include -#elif defined(BL606P) -#include -#else -#error "Use CHIP BL808/BL606P for this module" -#endif - -void ipc_m0_init(ipcIntCallback *onLPTriggerCallBack, - ipcIntCallback *onD0TriggerCallBack) -{ - IPC_M0_Init(onLPTriggerCallBack, onD0TriggerCallBack); - -#ifdef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(IPC_M0_IRQn, ipc_m0_handler); -#endif - - System_NVIC_SetPriority(IPC_M0_IRQn, 5, 0); -} diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_ipc.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_ipc.h deleted file mode 100644 index 1bb38c92ea..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_ipc.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __BL_IPC_H__ -#define __BL_IPC_H__ - -#include -typedef void(ipcIntCallback)(uint32_t src); -void ipc_m0_init(ipcIntCallback *onLPTriggerCallBack, ipcIntCallback *onD0TriggerCallBack); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_irq.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_irq.c deleted file mode 100644 index d9b3113c7f..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_irq.c +++ /dev/null @@ -1,418 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include - -//FIXME no BL808/BL606p header file including is Allowed here -#ifdef BL808 -#include -#elif defined(BL606P) -#include -#else -#error "Use CHIP BL808/BL606P for this module" -#endif - -#include "clic.h" - -#include -#include "bl_irq.h" - -#ifdef SYS_ENABLE_COREDUMP -#include -#endif - -void CPU_Interrupt_Enable(uint32_t irq_num); -void CPU_Interrupt_Disable(uint32_t irq_num); -void bl_irq_enable(unsigned int source) -{ - CPU_Interrupt_Enable(source); - //*(volatile uint8_t*)(CLIC_HART0_ADDR + CLIC_INTIE + source) = 1; -} - -void bl_irq_disable(unsigned int source) -{ - CPU_Interrupt_Disable(source); - //*(volatile uint8_t*)(CLIC_HART0_ADDR + CLIC_INTIE + source) = 0; -} - -void bl_irq_pending_set(unsigned int source) -{ - *(volatile uint8_t*)(CLIC_HART0_ADDR + CLIC_INTIP + source) = 1; -} - -void bl_irq_pending_clear(unsigned int source) -{ - *(volatile uint8_t*)(CLIC_HART0_ADDR + CLIC_INTIP + source) = 0; -} - -void bl_irq_exception_trigger(BL_IRQ_EXCEPTION_TYPE_T type, void *ptr) -{ - uint32_t val = 0x12345678;; - - switch (type) { - case BL_IRQ_EXCEPTION_TYPE_LOAD_MISALIGN: - { - val = *(uint32_t*)ptr; - } - break; - case BL_IRQ_EXCEPTION_TYPE_STORE_MISALIGN: - { - *(uint32_t*)ptr = val; - } - break; - case BL_IRQ_EXCEPTION_TYPE_ACCESS_ILLEGAL: - { - *(uint32_t*)ptr = val; - } - break; - case BL_IRQ_EXCEPTION_TYPE_ILLEGAL_INSTRUCTION: - { - uint32_t fun_val = 0; - typedef void (*ins_ptr_t)(void); - ins_ptr_t func = (ins_ptr_t)&fun_val; - - func(); - } - break; - default: - { - /*nothing here*/ - } - } - printf("Trigger exception val is %08lx\r\n", val); -} - -void bl_irq_default(void) -{ - while (1) { - /*dead loop*/ - } -} - -static void (*handler_list[2][16 + 64])(void) = { - -}; - - -static inline void _irq_num_check(int irqnum) -{ - if (irqnum < 0 || irqnum >= sizeof(handler_list[0])/sizeof(handler_list[0][0])) { - blog_error("illegal irqnum %d\r\n", irqnum); - while (1) { - /*Deap loop here, TODO ass blog_assert*/ - } - } -} - -void bl_irq_register_with_ctx(int irqnum, void *handler, void *ctx) -{ - _irq_num_check(irqnum); - if (handler_list[0][irqnum] && handler_list[0][irqnum] != handler) { - blog_warn("IRQ %d already registered with %p \r\n", - irqnum, - handler_list[0][irqnum] - ); - } - - if (handler == NULL) { - blog_error("handler is NULL pointer! \r\n"); - return; - } - - if (NULL == ctx) { - handler_list[0][irqnum] = handler; - handler_list[1][irqnum] = NULL; - } - else { - handler_list[0][irqnum] = handler; - handler_list[1][irqnum] = ctx; - } - - return; - -} - -void bl_irq_ctx_get(int irqnum, void **ctx) -{ - _irq_num_check(irqnum); - *ctx = handler_list[1][irqnum]; - - return; -} - -struct irq_ctx **bl_irq_ctx_list(int *num) -{ - *num = 16 + 64; - return (struct irq_ctx **)handler_list[1]; -} - -void bl_irq_ctx_count_cost(int irqnum, uint64_t cost) -{ - struct irq_ctx *ctx; - _irq_num_check(irqnum); - if(handler_list[0][irqnum] != NULL) { - ctx = (struct irq_ctx *)(handler_list[1][irqnum]); - ctx->irq_run_time += cost; - } -} - -//void Interrupt_Handler_Register(IRQn_Type irq,void * interruptFun); -void Interrupt_Handler_Register(IRQn_Type irq,pFunc interruptFun); -void bl_irq_register(int irqnum, void *handler) -{ - - Interrupt_Handler_Register(irqnum, handler); - //bl_irq_register_with_ctx(irqnum, handler, NULL); -} - -void bl_irq_unregister(int irqnum, void *handler) -{ -#if 0 - _irq_num_check(irqnum); - if (handler_list[0][irqnum] != handler) { - blog_warn("IRQ %d:%p Not match with registered %p\r\n", - irqnum, - handler, - handler_list[0][irqnum] - ); - } - handler_list[0][irqnum] = handler; -#endif -} - -void interrupt_entry(uint32_t mcause) -{ - void *handler = NULL; - mcause &= 0x7FFFFFF; - if (mcause < sizeof(handler_list[0])/sizeof(handler_list[0][0])) { - handler = handler_list[0][mcause]; - } - if (handler) { - if (handler_list[1][mcause]) { - ((void (*)(void *))handler)(handler_list[1][mcause]);//handler(ctx) - } - else { - ((void (*)(void))handler)(); - } - } else { - printf("Cannot handle mcause 0x%lx:%lu, adjust to externel(0x%lx:%lu)\r\n", - mcause, - mcause, - mcause - 16, - mcause - 16 - ); - while (1) { - /*dead loop now*/ - } - } -} - -static void __dump_exception_code_str(uint32_t code) -{ - printf("Exception code: %lu\r\n", code); - switch (code) { - case 0x00: - /*Instruction address misaligned*/ - { - puts(" msg: Instruction address misaligned\r\n"); - } - break; - case 0x01: - /*Instruction access fault*/ - { - puts(" msg: Instruction access fault\r\n"); - } - break; - case 0x02: - /*Illegal instruction*/ - { - puts(" msg: Illegal instruction\r\n"); - } - break; - case 0x03: - /*Breakpoint*/ - { - puts(" msg: Breakpoint\r\n"); - } - break; - case 0x04: - /*Load address misaligned*/ - { - puts(" msg: Load address misaligned\r\n"); - } - break; - case 0x05: - /*Load access fault*/ - { - puts(" msg: Load access fault\r\n"); - } - break; - case 0x06: - /*Store/AMO access misaligned*/ - { - puts(" msg: Store/AMO access misaligned\r\n"); - } - break; - case 0x07: - /*Store/AMO access fault*/ - { - puts(" msg: Store/AMO access fault\r\n"); - } - break; - case 0x08: - /*Environment call from U-mode*/ - { - puts(" msg: Environment call from U-mode\r\n"); - } - break; - case 0x09: - /*Environment call from S-mode*/ - { - puts(" msg: Environment call from S-mode\r\n"); - } - break; - case 0x0a: - case 0x0e: - /*Reserved*/ - { - puts(" msg: Reserved\r\n"); - } - break; - case 0x0b: - /*Environment call from M-mode*/ - { - puts(" msg: Environment call from M-mode\r\n"); - } - break; - case 0x0c: - /*Instruction page fault*/ - { - puts(" msg: Instruction page fault\r\n"); - } - break; - case 0x0d: - /*Load page fault*/ - { - puts(" msg: Load page fault\r\n"); - } - break; - case 0x0f: - /*Store/AMO page fault*/ - { - puts(" msg: Store/AMO page fault\r\n"); - } - break; - default:{ - puts(" msg: Reserved default exception\r\n"); - } - } -} - -extern void misaligned_load_trap(uintptr_t* regs, uintptr_t mcause, uintptr_t mepc); -extern void misaligned_store_trap(uintptr_t* regs, uintptr_t mcause, uintptr_t mepc); - -#define EXCPT_LOAD_MISALIGNED 4 -#define EXCPT_STORE_MISALIGNED 6 - -#ifdef DBG_RECORD_EXCEP_VAL -struct{ - uint32_t mcause; - uint32_t mepc; - uint32_t mtval; -}rval[4]; -int rval_idx; -#endif /* DBG_RECORD_EXCEP_VAL */ - -void exception_entry(uint32_t mcause, uint32_t mepc, uint32_t mtval, uintptr_t *regs) -{ -#ifdef DBG_RECORD_EXCEP_VAL - rval[rval_idx&0x3].mcause = mcause; - rval[rval_idx&0x3].mepc = mepc; - rval[rval_idx&0x3].mtval = mtval; - rval_idx++; -#endif /* DBG_RECORD_EXCEP_VAL */ - if ((mcause & 0x3ff) == EXCPT_LOAD_MISALIGNED) { - //misaligned_load_trap(regs, mcause, mepc); - } else if ((mcause & 0x3ff) == EXCPT_STORE_MISALIGNED){ - //misaligned_store_trap(regs, mcause, mepc); - } - { - //registerdump(tasksp); - puts("Exception Entry--->>>\r\n"); - blog_info("mcause %08lx, mepc %08lx, mtval %08lx\r\n", - mcause, - mepc, - mtval - ); - __dump_exception_code_str(mcause & 0xFFFF); - //backtrace_now_task((int (*)(const char *s))puts, regs); - while (1) { - /*Deap loop now*/ -#ifdef SYS_ENABLE_COREDUMP - /* For stack check */ - extern uintptr_t _sp_main, _sp_base; - - /* XXX change sp to irq stack base */ - __asm__ volatile("add sp, x0, %0" ::"r"(&_sp_main)); - bl_coredump_run(); -#endif - } - } -} - -int bl_irq_save(void) -{ - uint32_t oldstat; - - /* Read mstatus & clear machine interrupt enable (MIE) in mstatus */ - __asm volatile("csrrc %0, mstatus, %1" : "=r"(oldstat) : "r"(8)); - return oldstat; -} - -void bl_irq_restore(int flags) -{ - __asm volatile("csrw mstatus, %0" - : /* no output */ - : "r"(flags)); -} -void bl_irq_init(void) -{ - uint32_t ptr; - - // puts("[IRQ] Clearing and Disable all the pending IRQ...\r\n"); - - /*clear mask*/ - for (ptr = 0x02800400; ptr < 0x02800400 + 128; ptr++) { - *(uint8_t*)ptr = 0; - } - /*clear pending*/ - for (ptr = 0x02800000; ptr < 0x02800000 + 128; ptr++) { - *(uint8_t*)ptr = 0; - } -} diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_irq.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_irq.h deleted file mode 100644 index a70b2733bc..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_irq.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __BL_IRQ_H__ -#define __BL_IRQ_H__ -void bl_irq_enable(unsigned int source); -void bl_irq_disable(unsigned int source); -typedef enum { - BL_IRQ_EXCEPTION_TYPE_LOAD_MISALIGN, - BL_IRQ_EXCEPTION_TYPE_STORE_MISALIGN, - BL_IRQ_EXCEPTION_TYPE_ACCESS_ILLEGAL, - BL_IRQ_EXCEPTION_TYPE_ILLEGAL_INSTRUCTION, -} BL_IRQ_EXCEPTION_TYPE_T; - -struct irq_ctx { - char *name; - int irqnum; - uint64_t irq_run_time; -}; - -struct irq_ctx **bl_irq_ctx_list(int *num); -void bl_irq_exception_trigger(BL_IRQ_EXCEPTION_TYPE_T type, void *ptr); - -void bl_irq_init(void); -/*The following section define the IRQ handler for other files*/ -void bl_sec_aes_IRQHandler(void); -void bl_sec_sha_IRQHandler(void); -void bl_sec_pka_IRQHandler(void); -void bl_dma_IRQHandler(void); -void intc_irq(void);//MAC IRQ -void bl_irq_handler(void);//IPC host IRQ -void bl_irq_register_with_ctx(int irqnum, void *handler, void *ctx); -void bl_irq_register(int irqnum, void *handler); -void bl_irq_unregister(int irqnum, void *handler); -void bl_irq_ctx_get(int irqnum, void **ctx); - - -int bl_irq_save(void); -void bl_irq_restore(int flags); -void __attribute__((noreturn)) bl_sys_abort(const char *details); - -#define GLOBAL_IRQ_SAVE() if (1) { \ - int ____global_prev_mie_irq____ = bl_irq_save(); - -#define GLOBAL_IRQ_RESTORE() \ - bl_irq_restore(____global_prev_mie_irq____ ); \ -} -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_mm_clock.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_mm_clock.c deleted file mode 100644 index d02bd63c46..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_mm_clock.c +++ /dev/null @@ -1,272 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include -#include "bl_mm_clock.h" -//FIXME no BL808/BL606p header file including is Allowed here -#ifdef BL808 -#include -#include -#elif defined(BL606P) -//TODO BL606P H FILE -#include -#include -#else -#error "Use CHIP BL808/BL606P for this module" -#endif - -static void get_mm_xclk(uint32_t reg_val) -{ - uint32_t cpu_pll_clk = 0; - cpu_pll_clk = BL_GET_REG_BITS_VAL(reg_val, MM_GLB_REG_XCLK_CLK_SEL); - - switch (cpu_pll_clk) { - case 0: - printf("XCLK select RC32M\r\n"); - break; - case 1: - printf("XCLK select XTAL\r\n"); - break; - default: - break; - } -} - -static void get_mm_cpu_pll_clk(uint32_t reg_val) -{ - uint32_t cpu_pll_clk = 0; - cpu_pll_clk = BL_GET_REG_BITS_VAL(reg_val, MM_GLB_REG_CPU_CLK_SEL); - - switch (cpu_pll_clk) { - case 0: - printf("MM CPU select 240Mhz\r\n"); - break; - case 1: - printf("MM CPU select 320Mhz\r\n"); - break; - case 2: - printf("MM CPU select 400Mhz\r\n"); - break; - default: - break; - } - -} - -static void dump_mm_cpu_clk(void) -{ - uint32_t tmpVal = 0, cpu_root_clk = 0; - - tmpVal = BL_RD_REG(CLKRST_CTRL_BASE, MM_GLB_MM_CLK_CTRL_CPU); - cpu_root_clk = BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_ROOT_CLK_SEL); - switch (cpu_root_clk) { - case 0: - printf("MM CPU select XCLK--->"); - get_mm_xclk(tmpVal); - break; - case 1: - printf("MM CPU select PLL--->"); - get_mm_cpu_pll_clk(tmpVal); - break; - default: - break; - } -} - -static void dump_mm_bus_clk(void) -{ - uint32_t tmpVal = 0, mm_bus_clk = 0; - - tmpVal = BL_RD_REG(CLKRST_CTRL_BASE, MM_GLB_MM_CLK_CTRL_CPU); - mm_bus_clk = BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK1X_SEL); - - switch (mm_bus_clk) { - case 0: - printf("MM BUS CLK select XCLK--->"); - get_mm_xclk(tmpVal); - break; - case 2: - printf("MM BUS CLK select 160Mhz\r\n"); - break; - case 3: - printf("MM BUS CLK select 240Mhz\r\n"); - break; - default: - break; - } - -} - -static void dump_mm_xclk(void) -{ - uint32_t tmpVal = 0; - tmpVal = BL_RD_REG(CLKRST_CTRL_BASE, MM_GLB_MM_CLK_CTRL_CPU); - get_mm_xclk(tmpVal); -} - -static void dump_mm_uart_clk(void) -{ - uint32_t tmpVal = 0, mm_uart_clk = 0; - - tmpVal = BL_RD_REG(CLKRST_CTRL_BASE, MM_GLB_MM_CLK_CTRL_CPU); - mm_uart_clk = BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_UART_CLK_SEL); - - switch (mm_uart_clk) { - case 0: - printf("UART CLK select MM BUS CLK--->"); - dump_mm_bus_clk(); - break; - case 1: - printf("UART CLK select 160Mhz\r\n"); - break; - case 2: - case 3: - printf("UART CLK select MM XCLK--->"); - get_mm_xclk(tmpVal); - break; - default: - break; - } -} - -static void dump_mm_i2c_clk(void) -{ - uint32_t tmpVal = 0, mm_i2c_clk = 0; - - tmpVal = BL_RD_REG(CLKRST_CTRL_BASE, MM_GLB_MM_CLK_CTRL_CPU); - mm_i2c_clk = BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_I2C_CLK_SEL); - - switch (mm_i2c_clk) { - case 0: - printf("I2C CLK select MM BUS CLK--->"); - dump_mm_bus_clk(); - break; - case 1: - printf("I2C CLK select MM XCLK--->"); - get_mm_xclk(tmpVal); - break; - default: - break; - } -} - -static void dump_mm_spi_clk(void) -{ - uint32_t tmpVal = 0, mm_spi_clk = 0; - - tmpVal = BL_RD_REG(CLKRST_CTRL_BASE, MM_GLB_MM_CLK_CTRL_CPU); - mm_spi_clk = BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_SPI_CLK_SEL); - - switch (mm_spi_clk) { - case 0: - printf("SPI CLK select 160Mhz\r\n"); - break; - case 1: - printf("SPI CLK select MM XCLK--->"); - get_mm_xclk(tmpVal); - break; - default: - break; - } -} - -void bl_mm_clk_dump(void) -{ - dump_mm_cpu_clk(); - dump_mm_uart_clk(); - dump_mm_i2c_clk(); - dump_mm_spi_clk(); - dump_mm_bus_clk(); - dump_mm_xclk(); -} - -void bl_mm_xclk_config(mm_xclk_type xclk_num) -{ - uint32_t tmpVal; - tmpVal = BL_RD_REG(CLKRST_CTRL_BASE, MM_GLB_MM_CLK_CTRL_CPU); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_XCLK_CLK_SEL, xclk_num); - - BL_WR_REG(CLKRST_CTRL_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal); -} - -void bl_mm_bclk_config(mm_bclk_type bclk_num) -{ - uint32_t tmpVal; - tmpVal = BL_RD_REG(CLKRST_CTRL_BASE, MM_GLB_MM_CLK_CTRL_CPU); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK1X_SEL, bclk_num); - - BL_WR_REG(CLKRST_CTRL_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal); -} - -void bl_mm_cpu_root_clk_config(mm_cpu_root_clk_type cpu_root_clk_num) -{ - uint32_t tmpVal; - tmpVal = BL_RD_REG(CLKRST_CTRL_BASE, MM_GLB_MM_CLK_CTRL_CPU); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_ROOT_CLK_SEL, cpu_root_clk_num); - - BL_WR_REG(CLKRST_CTRL_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal); -} - -void bl_mm_cpu_clk_config(mm_cpu_clk_type cpu_clk_num) -{ - uint32_t tmpVal; - tmpVal = BL_RD_REG(CLKRST_CTRL_BASE, MM_GLB_MM_CLK_CTRL_CPU); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_CLK_SEL, cpu_clk_num); - - BL_WR_REG(CLKRST_CTRL_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal); -} - -void bl_mm_spi_clk_config(mm_spi_clk_type spi_clk_num) -{ - uint32_t tmpVal; - tmpVal = BL_RD_REG(CLKRST_CTRL_BASE, MM_GLB_MM_CLK_CTRL_CPU); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_SPI_CLK_SEL, spi_clk_num); - - BL_WR_REG(CLKRST_CTRL_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal); -} - -void bl_mm_i2c_clk_config(mm_i2c_clk_type i2c_clk_num) -{ - uint32_t tmpVal; - tmpVal = BL_RD_REG(CLKRST_CTRL_BASE, MM_GLB_MM_CLK_CTRL_CPU); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_I2C_CLK_SEL, i2c_clk_num); - - BL_WR_REG(CLKRST_CTRL_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal); -} - -void bl_mm_uart_clk_config(mm_uart_clk_type uart_clk_num) -{ - uint32_t tmpVal; - tmpVal = BL_RD_REG(CLKRST_CTRL_BASE, MM_GLB_MM_CLK_CTRL_CPU); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_UART_CLK_SEL, uart_clk_num); - - BL_WR_REG(CLKRST_CTRL_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal); -} - diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_mm_clock.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_mm_clock.h deleted file mode 100644 index ef8946c9f4..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_mm_clock.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __BL_MM_CLOCK__ -#define __BL_MM_CLOCK__ -/*MM XCLK select*/ -typedef enum { - XCLK_RC32M = 0, - XCLK_XTAL, -}mm_xclk_type; - -/*MM BCLK1x select*/ -typedef enum { - BCLK_XCLK = 0, - BCLK_MUXPLL_160M = 2, - BCLK_MUXPLL_240M = 3, -}mm_bclk_type; - -/*MM CPU PLL select*/ -typedef enum { - CPU_CLK_MUXPLL_240M = 0, - CPU_CLK_MUXPLL_320M, - CPU_CLK_MUXPLL_400M, -}mm_cpu_clk_type; - -/*MM CPU ROOT CLK select*/ -typedef enum { - CPU_ROOT_CLK_XCLK = 0, - CPU_ROOT_CLK_PLL, -}mm_cpu_root_clk_type; - -/*MM SPI CLK select*/ -typedef enum { - SPI_CLK_MUXPLL_160M = 0, - SPI_CLK_XCLK, -}mm_spi_clk_type; - -/*MM I2C CLK select*/ -typedef enum { - I2C_CLK_BCLK = 0, - I2C_CLK_XCLK, -}mm_i2c_clk_type; - -/*MM UART CLK select*/ -typedef enum { - UART_CLK_BCLK = 0, - UART_CLK_MUXPLL_160M, - UART_CLK_XCLK1, //2 or 3 all select MM XCLK - UART_CLK_XCLK2, -}mm_uart_clk_type; - -void bl_mm_clk_dump(void); -void bl_mm_xclk_config(mm_xclk_type xclk_num); -void bl_mm_bclk_config(mm_bclk_type bclk_num); -void bl_mm_cpu_clk_config(mm_cpu_clk_type cpu_clk_num); -void bl_mm_cpu_root_clk_config(mm_cpu_root_clk_type cpu_root_clk_num); -void bl_mm_spi_clk_config(mm_spi_clk_type spi_clk_num); -void bl_mm_i2c_clk_config(mm_i2c_clk_type i2c_clk_num); -void bl_mm_uart_clk_config(mm_uart_clk_type uart_clk_num); -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_pm.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_pm.c deleted file mode 100644 index a9a1b0dfb5..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_pm.c +++ /dev/null @@ -1,489 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include -#include - -#include -#include -#include -#include "bl_pm.h" -#include - -enum PM_STATE { - PM_STATE_INITED = 0, - PM_STATE_STOP, - PM_STATE_START, - PM_STATE_STOPPED, - PM_STATE_RUNNING, -}; - -union ps_cap { - uint32_t cap; - struct { - unsigned int uapsd_mode : 1; - unsigned int mac_idle : 1; - unsigned int ma_doze : 1; - unsigned int rf_onoff : 1; - unsigned int pti_pta_config : 1; - unsigned int force_sleep : 1; - } bits; -}; - -struct pm_env -{ - uint32_t level; - union ps_cap wlan_capacity; - union ps_cap bt_capacity; - enum PM_STATE state; - SemaphoreHandle_t pm_mux; - utils_dlist_t *pm_list; -}; - -struct pm_node -{ - utils_dlist_t dlist_item; - enum PM_EVEMT event; - uint32_t code; - uint16_t priority; - uint32_t cap_bit; - bl_pm_cb_t ops; - enum PM_EVENT_ABLE enable; - void *ctx; -}; - -static struct pm_env *gp_pm_env = NULL; - -static int pm_env_init(void) -{ - int i = 0; - - assert(!gp_pm_env); - - gp_pm_env = pvPortMalloc(sizeof(struct pm_env)); - assert(gp_pm_env); - - memset(gp_pm_env, 0, sizeof(struct pm_env)); - gp_pm_env->pm_list = pvPortMalloc(sizeof(utils_dlist_t) * PM_EVENT_MAX); - assert(gp_pm_env->pm_list); - - memset(gp_pm_env->pm_list, 0, sizeof(bl_pm_cb_t) * PM_EVENT_MAX); - - gp_pm_env->pm_mux = xSemaphoreCreateMutex(); - assert(gp_pm_env->pm_mux); - - for (i = 0; i < PM_EVENT_MAX; i++) { - INIT_UTILS_DLIST_HEAD(&(gp_pm_env->pm_list)[i]); - } - - gp_pm_env->state = PM_STATE_INITED; - - ///for debug - gp_pm_env->bt_capacity.cap = 0xffff; - - return 0; -} - -static void pm_node_delete(utils_dlist_t *queue) -{ - struct pm_node *node = NULL; - utils_dlist_t *tmp; - - utils_dlist_for_each_entry_safe(queue, tmp, node, struct pm_node, dlist_item) { - xSemaphoreTake(gp_pm_env->pm_mux, portMAX_DELAY); - utils_dlist_del(&(node->dlist_item)); - vPortFree(node); - xSemaphoreGive(gp_pm_env->pm_mux); - } -} - -static int pm_deinit(void) -{ - int i = 0; - - assert(gp_pm_env); - - for (i = 0; i < PM_EVENT_MAX; i++) { - pm_node_delete(&(gp_pm_env->pm_list)[i]); - } - - vPortFree(gp_pm_env->pm_list); - gp_pm_env->pm_list = NULL; - - vSemaphoreDelete(gp_pm_env->pm_mux); - gp_pm_env->pm_mux = NULL; - - vPortFree(gp_pm_env); - gp_pm_env = NULL; - - return 0; -} - -static int pm_set_wlan_capacity(uint32_t capacity) -{ - assert(gp_pm_env); - - gp_pm_env->wlan_capacity.cap = capacity; - - return 0; -} - -static int pm_set_state(enum PM_STATE state) -{ - gp_pm_env->state = state; - - return 0; -} - -static enum PM_STATE pm_get_state(void) -{ - return gp_pm_env->state; -} - -static void pm_node_add(struct pm_node *pnode, utils_dlist_t *queue) -{ - struct pm_node *node = NULL; - utils_dlist_t *tmp; - utils_dlist_t *pre_save; - - pre_save = queue; - utils_dlist_for_each_entry_safe(queue, tmp, node, struct pm_node, dlist_item) { - if (pnode->priority < node->priority) { - xSemaphoreTake(gp_pm_env->pm_mux, portMAX_DELAY); - utils_dlist_add(&(pnode->dlist_item), pre_save); - xSemaphoreGive(gp_pm_env->pm_mux); - break; - } - - pre_save = &(node->dlist_item); - } - - if (&(node->dlist_item) == queue) { - xSemaphoreTake(gp_pm_env->pm_mux, portMAX_DELAY); - utils_dlist_add_tail(&(pnode->dlist_item), queue); - xSemaphoreGive(gp_pm_env->pm_mux); - } -} - -static int pm_node_ops_exec(struct pm_node *node) -{ - if (node->ops == NULL) { - return 0; - } - - return node->ops(node->ctx); -} - -static int pm_state_exec_func_check(enum PM_EVEMT event, uint32_t code) -{ - int ret; - - if ((WLAN_PM_EVENT_CONTROL == event) || (PM_STATE_RUNNING == gp_pm_env->state)) { - ret = 0; - } else { - ret = 1; - } - - return ret; -} - -static int pm_pmlist_traverse(enum PM_EVEMT event, utils_dlist_t *queue, uint32_t code, uint32_t *retval) -{ - struct pm_node *node = NULL; - int ret = 0; - utils_dlist_t *tmp; - - if (retval) { - *retval = 0; - } - - utils_dlist_for_each_entry_safe(queue, tmp, node, struct pm_node, dlist_item) { - if ((node->enable) && (code == node->code) && (gp_pm_env->wlan_capacity.cap & node->cap_bit) && - (gp_pm_env->bt_capacity.cap & node->cap_bit)) { - - if (pm_state_exec_func_check(event, code)) { - return -1; - } - - ret = pm_node_ops_exec(node); - if (ret && retval) { - *retval |= 1; - } - } - } - - return 0; -} - -static int pm_internal_process_event(enum PM_EVEMT event, uint32_t code) -{ - int ret = 0; - - switch (event) { - case WLAN_PM_EVENT_CONTROL: - { - switch (code) { - case WLAN_CODE_PM_NOTIFY_START: - { - if ((PM_STATE_INITED != pm_get_state()) && (PM_STATE_STOPPED != pm_get_state())) { - blog_error("pm not init or is running.\r\n"); - ret = -1; - - return ret; - } - pm_set_state(PM_STATE_START); - } - break; - - case WLAN_CODE_PM_NOTIFY_STOP: - { - if (PM_STATE_RUNNING != pm_get_state()) { - blog_error("pm is not running.\r\n"); - ret = -1; - - return ret; - } - - pm_set_state(PM_STATE_STOP); - } - break; - - default: - { - } - } - } - break; - - default: - { - - } - } - - return ret; -} - -int pm_post_event(enum PM_EVEMT event, uint32_t code, uint32_t *retval) -{ - if (!gp_pm_env) { - return -1; - } - - pm_pmlist_traverse(event, &(gp_pm_env->pm_list)[event], code, retval); - pm_internal_process_event(event, code); - - return 0; -} - -int bl_pm_event_register(enum PM_EVEMT event, uint32_t code, uint32_t cap_bit, uint16_t priority, bl_pm_cb_t ops, void *arg, enum PM_EVENT_ABLE enable) -{ - struct pm_node *p_node; - - if (!gp_pm_env) { - return -1; - } - - p_node = pvPortMalloc(sizeof(struct pm_node)); - assert(p_node); - - memset(p_node, 0, sizeof(struct pm_node)); - p_node->event = event; - p_node->code = code; - p_node->cap_bit = cap_bit; - p_node->priority = priority; - p_node->ops = ops; - p_node->ctx = arg; - p_node->enable = enable; - - pm_node_add(p_node, &(gp_pm_env->pm_list)[event]); - - return 0; -} - -int bl_pm_event_switch(enum PM_EVEMT event, uint32_t code, enum PM_EVENT_ABLE enable) -{ - struct pm_node *node = NULL; - utils_dlist_t *tmp; - utils_dlist_t *queue; - int ret = -1; - - if (!gp_pm_env) { - return -1; - } - - queue = &(gp_pm_env->pm_list)[event]; - - utils_dlist_for_each_entry_safe(queue, tmp, node, struct pm_node, dlist_item) { - if (code == node->code) { - node->enable = enable; - - ret = 0; - } - } - - return ret; -} - -int bl_pm_state_run(void) -{ - int ret = -1; - - if (!gp_pm_env) { - return -1; - } - - switch (gp_pm_env->state) { - case PM_STATE_INITED: - { - } - break; - - case PM_STATE_START: - { - pm_set_state(PM_STATE_RUNNING); - pm_post_event(WLAN_PM_EVENT_CONTROL, WLAN_CODE_PM_START, NULL);; - ret = 0; - } - break; - - case PM_STATE_STOP: - { - pm_set_state(PM_STATE_STOPPED); - pm_post_event(WLAN_PM_EVENT_CONTROL, WLAN_CODE_PM_STOP, NULL); - } - break; - - case PM_STATE_RUNNING: - { - ret = 0; - } - break; - - case PM_STATE_STOPPED: - { - } - break; - - default: - { - - } - } - - return ret; -} - -int bl_pm_capacity_set(enum PM_LEVEL level) -{ - uint32_t capacity = 0; - - switch (level) { - case PM_MODE_STA_NONE: - { - return -1; - } - break; - - case PM_MODE_STA_IDLE: - { - capacity |= NODE_CAP_BIT_UAPSD_MODE; - capacity |= NODE_CAP_BIT_MAC_IDLE; - } - break; - - case PM_MODE_STA_MESH: - { - capacity |= NODE_CAP_BIT_UAPSD_MODE; - capacity |= NODE_CAP_BIT_MAC_IDLE; - capacity |= NODE_CAP_BIT_WLAN_BLE_ABORT; - capacity |= NODE_CAP_BIT_FORCE_SLEEP; - } - break; - - case PM_MODE_STA_DOZE: - { - capacity |= NODE_CAP_BIT_UAPSD_MODE; - capacity |= NODE_CAP_BIT_MAC_IDLE; - capacity |= NODE_CAP_BIT_MAC_DOZE; - capacity |= NODE_CAP_BIT_RF_ONOFF; - capacity |= NODE_CAP_BIT_FORCE_SLEEP; - } - break; - - case PM_MODE_STA_COEX: - { - capacity |= NODE_CAP_BIT_UAPSD_MODE; - capacity |= NODE_CAP_BIT_MAC_IDLE; - capacity |= NODE_CAP_BIT_MAC_DOZE; - capacity |= NODE_CAP_BIT_RF_ONOFF; - capacity |= NODE_CAP_BIT_WLAN_BLE_ABORT; - } - break; - - case PM_MODE_STA_DOWN: - { - capacity |= NODE_CAP_BIT_MAC_IDLE; - capacity |= NODE_CAP_BIT_MAC_DOZE; - capacity |= NODE_CAP_BIT_RF_ONOFF; - } - break; - - case PM_MODE_AP_IDLE: - { - capacity |= NODE_CAP_BIT_MAC_IDLE; - capacity |= NODE_CAP_BIT_MAC_DOZE; - } - break; - - default: - { - return -1; - } - } - - pm_set_wlan_capacity(capacity); - - return 0; -} - -int bl_pm_init(void) -{ - pm_env_init(); - - return 0; -} - -int bl_pm_deinit(void) -{ - pm_deinit(); - - return 0; -} diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_pm.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_pm.h deleted file mode 100644 index 174863be2c..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_pm.h +++ /dev/null @@ -1,111 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __BL_PM_H__ -#define __BL_PM_H__ -#include -#include - -#define NODE_CAP_BIT_UAPSD_MODE (1 << 0) -#define NODE_CAP_BIT_MAC_IDLE (1 << 1) -#define NODE_CAP_BIT_MAC_DOZE (1 << 2) -#define NODE_CAP_BIT_RF_ONOFF (1 << 3) -#define NODE_CAP_BIT_WLAN_BLE_ABORT (1 << 4) -#define NODE_CAP_BIT_FORCE_SLEEP (1 << 5) -#define NODE_CAP_BIT_ALL_ALLOWED (0xffff) - -enum PM_EVENT_ABLE { - PM_DISABLE = 0, - PM_ENABLE, -}; - -enum WLAN_CODE_SLEEP_CONTROL { - WLAN_CODE_PM_NOTIFY_START = 0, - WLAN_CODE_PM_NOTIFY_STOP, - WLAN_CODE_PM_START, - WLAN_CODE_PM_STOP, -}; - -enum WLAN_CODE_ENTER_SLEEP { - WLAN_CODE_PM_ENTER_SLEEP_PRE = 0, - WLAN_CODE_PM_ENTER_SLEEP, -}; - -enum WLAN_CODE_EXIT_SLEEP { - WLAN_CODE_PM_ENTER_SLEEP_PRE_FAILED = 0, - WLAN_CODE_PM_EXIT_SLEEP_PRE, - WLAN_CODE_PM_EXIT_SLEEP, -}; - -enum WLAN_CODE_BEACON_LOSS { - WLAN_CODE_BEACON_LOSS = 0, -}; - -enum WLAN_CODE_SEND_NULLDATA { - WLAN_CODE_PM_PAUSE = 0, - WLAN_CODE_PM_NULLDATA_NOACK, - WLAN_CODE_PM_NULLDATA_SEND_ERROR, -}; - -enum BLE_CODE_BLE_CONTROL { - BLE_CODE_PM_TURNON_RF = 0, - BLE_CODE_PM_TURNOFF_RF, -}; - -enum PM_LEVEL{ - PM_MODE_STA_NONE = 0, - PM_MODE_STA_IDLE, - PM_MODE_STA_MESH, - PM_MODE_STA_DOZE, - PM_MODE_STA_COEX, - PM_MODE_STA_DOWN, - PM_MODE_AP_IDLE, - PM_MODE_MAX, -}; - -enum PM_EVEMT{ - WLAN_PM_EVENT_CONTROL = 0, - WLAN_PM_EVENT_ENTER_SLEEP, - WLAN_PM_EVENT_EXIT_SLEEP, - WLAN_PM_EVENT_BEACON_LOSS, - WLAN_PM_EVENT_SEND_NULLDATA, - BLE_PM_EVENT_CONTROL, - PM_EVENT_MAX, -}; - -typedef int (*bl_pm_cb_t)(void *arg); - -int bl_pm_init(void); -int bl_pm_event_register(enum PM_EVEMT event, uint32_t code, uint32_t cap_bit, uint16_t pirority, bl_pm_cb_t ops, void *arg, enum PM_EVENT_ABLE enable); -int bl_pm_deinit(void); -int bl_pm_state_run(void); -int bl_pm_capacity_set(enum PM_LEVEL level); -int pm_post_event(enum PM_EVEMT event, uint32_t code, uint32_t *retval); -int bl_pm_event_switch(enum PM_EVEMT event, uint32_t code, enum PM_EVENT_ABLE enable); -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_psram.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_psram.c deleted file mode 100644 index b922b5695a..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_psram.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "bl_psram.h" -#ifdef BL808 -#include -#include - -int bl_psram_init(void) -{ - GLB_Config_UHS_PLL(GLB_XTAL_40M, uhsPllCfg_2000M); - Psram_UHS_x16_Init(2000); - printf("Done. \r\nData @0x5000_0000 is %08lx\r\n", *(uint32_t*)0x50000000); - return 0; -} - -#elif defined(BL606P) -#include -int bl_psram_init(void) -{ - puts("--> dummy PSRAM init implemented\r\n"); - return 0; -} -#endif - diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_psram.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_psram.h deleted file mode 100644 index 7120c15781..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_psram.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __BL_PSRAM_H__ -#define __BL_PSRAM_H__ - -int bl_psram_init(void); -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_sdh.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_sdh.c deleted file mode 100644 index 2ab832702c..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_sdh.c +++ /dev/null @@ -1,1715 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include "bl_sdh.h" - -#define SDH_CLK_PIN GLB_GPIO_PIN_0 -#define SDH_CMD_PIN GLB_GPIO_PIN_1 -#define SDH_DAT0_PIN GLB_GPIO_PIN_2 -#define SDH_DAT1_PIN GLB_GPIO_PIN_3 -#define SDH_DAT2_PIN GLB_GPIO_PIN_4 -#define SDH_DAT3_PIN GLB_GPIO_PIN_5 - -#define SDH_CLK_PIN_FUN GPIO_FUN_SDH -#define SDH_CMD_PIN_FUN GPIO_FUN_SDH -#define SDH_DAT0_PIN_FUN GPIO_FUN_SDH -#define SDH_DAT1_PIN_FUN GPIO_FUN_SDH -#define SDH_DAT2_PIN_FUN GPIO_FUN_SDH -#define SDH_DAT3_PIN_FUN GPIO_FUN_SDH - - -#if SDIO_SDCARD_INT_MODE -#define SDH_SDCARD_IRQn SDH_IRQn -#endif - -/* Private variables ---------------------------------------------------------*/ - -static uint32_t sdhClockInit = 400000ul; -static uint32_t sdhClockSrc = 96000000ul; -static uint32_t sdhClockTransfer = 48000000ul; - -static sd_card_t *pSDCardInfo = NULL; -static SDH_Cfg_Type SDH_Cfg_Type_Instance; - -#if SDIO_SDCARD_INT_MODE -static volatile SD_Error SDH_DataWaitStatus = SD_WAITING; -static volatile SD_Error SDH_CMDWaitStatus = SD_WAITING; - -static SDH_Trans_Callback_Cfg_Type SDH_Trans_Callback_Cfg_TypeInstance; -static SDH_Handle_Cfg_Type SDH_Handle_Cfg_TypeInstance; -#endif - -static SDH_DMA_Cfg_Type SDH_DMA_Cfg_TypeInstance; -/*causion: ADMA related variables must on OCRAM or shared ram*/ -static __EALIGN(64) SDH_ADMA2_Desc_Type adma2Entries[32]; - -/* Private function prototypes -----------------------------------------------*/ -static void SD_DecodeCid(sd_card_t *card, uint32_t *rawCid); -static void SD_DecodeCsd(sd_card_t *card, uint32_t *rawCsd); -static void SD_DecodeScr(sd_card_t *card, uint32_t *rawScr); -#if SDIO_SDCARD_INT_MODE -static void SDH_INT_Init(void); -#endif -static status_t SDH_SendCardCommand(SDH_CMD_Cfg_Type *cmd); -static void SDH_HostInit(void); -static status_t SDH_GoIdle(void); -static status_t SD_SendApplicationCmd(uint32_t relativeAddress); -static status_t SD_SendInterfaceCondition(void); -static status_t SD_ApplicationSendOperationCondition(sd_card_t *card, uint32_t argument); -static status_t SD_AllSendCid(sd_card_t *card); -static status_t SD_SendRca(sd_card_t *card); -static status_t SD_SendCsd(sd_card_t *card); -static status_t SD_SelectCard(sd_card_t *card, BL_Fun_Type NewState); -static status_t SD_SendScr(sd_card_t *card); -static status_t SD_SendSsr(sd_card_t *card); -static status_t SD_SetDataBusWidth(sd_card_t *card, SDH_Data_Bus_Width_Type width); -static status_t SD_SwitchFunction(uint32_t mode, uint32_t group, uint32_t number, uint32_t status[16]); -static status_t SD_SelectFunction(uint32_t group, uint32_t function); -static status_t SD_SetBlockSize(uint32_t blockSize); -static status_t SDH_SDCardInit(uint32_t bus_wide, sd_card_t *card); -static status_t WaitInProgramming(void); -static status_t IsCardProgramming(uint8_t *pstatus); -static status_t SDH_CardTransferNonBlocking(SDH_DMA_Cfg_Type *dmaCfg, SDH_Trans_Cfg_Type *transfer); - -static void SD_DecodeCid(sd_card_t *card, uint32_t *rawCid) -{ - sd_cid_t *cid; - - cid = &(card->cid); - cid->manufacturerID = (uint8_t)((rawCid[3U] & 0xFF0000U) >> 16U); - cid->applicationID = (uint16_t)((rawCid[3U] & 0xFFFFU) >> 0U); - - cid->productName[0U] = (uint8_t)((rawCid[1U] & 0xFF000000U) >> 24); - cid->productName[1U] = (uint8_t)((rawCid[2U] & 0xFF) >> 0U); - cid->productName[2U] = (uint8_t)((rawCid[2U] & 0xFF00U) >> 8U); - cid->productName[3U] = (uint8_t)((rawCid[2U] & 0xFF0000U) >> 16U); - cid->productName[4U] = (uint8_t)((rawCid[2U] & 0xFF000000U) >> 24U); - - cid->productVersion = (uint8_t)((rawCid[1U] & 0xFF0000U) >> 16U); - - cid->productSerialNumber = (uint32_t)((rawCid[1U] & 0xFFFFU) << 16U); - cid->productSerialNumber |= (uint32_t)((rawCid[0U] & 0xFFFF0000U) >> 16U); - - cid->manufacturerData = (uint16_t)((rawCid[0U] & 0xFFFU) >> 0U); -} -static void SD_DecodeCsd(sd_card_t *card, uint32_t *rawCsd) -{ - sd_csd_t *csd; - - csd = &(card->csd); - csd->csdStructure = (uint8_t)((rawCsd[3U] & 0xC00000U) >> 22U); - csd->dataReadAccessTime1 = (uint8_t)((rawCsd[3U] & 0xFF00U) >> 8U); - csd->dataReadAccessTime2 = (uint8_t)((rawCsd[3U] & 0xFFU) >> 0U); - - csd->transferSpeed = (uint8_t)((rawCsd[2U] & 0xFF000000U) >> 24); - csd->cardCommandClass = (uint16_t)((rawCsd[2U] & 0xFFF000U) >> 12U); - csd->readBlockLength = (uint8_t)((rawCsd[2U] & 0xF00U) >> 8U); - - switch (csd->csdStructure) { - /*csd version 1.1*/ - case 0: - csd->deviceSize = (uint32_t)((rawCsd[2U] & 0x3U) << 10U); - csd->deviceSize |= (uint32_t)((rawCsd[1U] & 0xFFC00000U) >> 22U); - - csd->deviceSizeMultiplier = (uint8_t)((rawCsd[1U] & 0x380U) >> 7U); - - /* Get card total block count and block size. */ - card->blockCount = ((csd->deviceSize + 1U) << (csd->deviceSizeMultiplier + 2U)); - card->blockSize = (1U << (csd->readBlockLength)); - - if (card->blockSize != SDH_DEFAULT_BLOCK_SIZE) { - card->blockCount = (card->blockCount * card->blockSize); - card->blockSize = SDH_DEFAULT_BLOCK_SIZE; - card->blockCount = (card->blockCount / card->blockSize); - } - - break; - - /*csd version 2.0*/ - case 1: - card->blockSize = SDH_DEFAULT_BLOCK_SIZE; - csd->deviceSize = (uint32_t)((rawCsd[1U] & 0x3FFFFF00U) >> 8U); - - if (csd->deviceSize >= 0xFFFFU) { - card->flags |= SD_SupportSdxcFlag; - } - - card->blockCount = ((csd->deviceSize + 1U) * 1024U); - break; - - default: - break; - } -} -static void SD_DecodeScr(sd_card_t *card, uint32_t *rawScr) -{ - sd_scr_t *scr; - - scr = &(card->scr); - scr->scrStructure = (uint8_t)((rawScr[1U] & 0xF0000000U) >> 28U); - scr->sdSpecification = (uint8_t)((rawScr[1U] & 0xF000000U) >> 24U); - - if ((uint8_t)((rawScr[1U] & 0x800000U) >> 23U)) { - scr->flags |= SD_ScrDataStatusAfterErase; - } - - scr->sdSecurity = (uint8_t)((rawScr[1U] & 0x700000U) >> 20U); - scr->sdBusWidths = (uint8_t)((rawScr[1U] & 0xF0000U) >> 16U); - - if ((uint8_t)((rawScr[0U] & 0x8000U) >> 15U)) { - scr->flags |= SD_ScrSdSpecification3; - } - - scr->extendedSecurity = (uint8_t)((rawScr[1U] & 0x7800U) >> 10U); - scr->commandSupport = (uint8_t)(rawScr[1U] & 0x3U); - scr->reservedForManufacturer = rawScr[0U]; - - /* Get specification version. */ - switch (scr->sdSpecification) { - case 0U: - card->version = SD_SpecificationVersion1_0; - break; - - case 1U: - card->version = SD_SpecificationVersion1_1; - break; - - case 2U: - card->version = SD_SpecificationVersion2_0; - - if (card->scr.flags & SD_ScrSdSpecification3) { - card->version = SD_SpecificationVersion3_0; - } - - break; - - default: - break; - } - - if (card->scr.sdBusWidths & 0x4U) { - card->flags |= SD_Support4BitWidthFlag; - } - - /* speed class control cmd */ - if (card->scr.commandSupport & 0x01U) { - card->flags |= SD_SupportSpeedClassControlCmd; - } - - /* set block count cmd */ - if (card->scr.commandSupport & 0x02U) { - card->flags |= SD_SupportSetBlockCountCmd; - } -} - -#if SDIO_SDCARD_INT_MODE -/*!< SDH transfer complete callback */ -void SDH_DataTransferFinished_CallBack(SDH_Handle_Cfg_Type *handle, SDH_Stat_Type status, void *userData) -{ - //bflb_platform_printf("Interrupt occurs! intFlag=0x%02lX,\r\n",handle->intFlag); - if (status != SDH_STAT_SUCCESS) { - SDH_DataWaitStatus = SD_DataCfg_ERROR; - } else { - SDH_DataWaitStatus = SD_OK; - } -} -/*!< SDH transfer complete callback */ -void SDH_CMDTransferFinished_CallBack(SDH_Handle_Cfg_Type *handle, SDH_Stat_Type status, void *userData) -{ - //bflb_platform_printf("Interrupt occurs! intFlag=0x%02lX,\r\n",handle->intFlag); - if (status != SDH_STAT_SUCCESS) { - SDH_CMDWaitStatus = SD_CMD_ERROR; - } else { - SDH_CMDWaitStatus = SD_OK; - } -} - -/****************************************************************************/ /** - * @brief SDH INT init - * - * @param None - * - * @return None - * -*******************************************************************************/ -static void SDH_INT_Init(void) -{ - System_NVIC_SetPriority(SDH_SDCARD_IRQn, 7, 1); - CPU_Interrupt_Enable(SDH_SDCARD_IRQn); - - SDH_EnableIntStatus(SDH_INT_ALL); - SDH_DisableIntSource(SDH_INT_ALL); - SDH_Trans_Callback_Cfg_TypeInstance.SDH_CallBack_TransferFinished = SDH_DataTransferFinished_CallBack; - SDH_Trans_Callback_Cfg_TypeInstance.SDH_CMDCallBack_TransferFinished = SDH_CMDTransferFinished_CallBack; - SDH_InstallHandleCallback(&SDH_Handle_Cfg_TypeInstance, &SDH_Trans_Callback_Cfg_TypeInstance, NULL); -} -#endif - -static status_t SDH_SendCardCommand(SDH_CMD_Cfg_Type *cmd) -{ - status_t errorstatus = Status_Success; - SD_Error sd_status; - uint32_t time_node; - - SDH_ClearIntStatus(SDH_INT_CMD_COMPLETED | SDH_INT_CMD_ERRORS); - - SDH_SendCommand(cmd); - time_node = (uint32_t)SDH_GET_TIME(); - -#if SDIO_SDCARD_INT_MODE - - SDH_CMDWaitStatus = SD_WAITING; - SDH_EnableIntSource(SDH_INT_CMD_COMPLETED | SDH_INT_CMD_ERRORS); - - /*wait for Xfer status. might pending here in multi-task OS*/ - while (SDH_CMDWaitStatus == SD_WAITING) { - if ((uint32_t)SDH_GET_TIME() - time_node > SDIO_CMDTIMEOUT_MS) { - SDH_MSG("SDH send CMD%ld timeout: %ld ms\r\n", cmd->index, (uint32_t)SDH_GET_TIME() - time_node); - SDH_DisableIntSource(SDH_INT_CMD_COMPLETED | SDH_INT_CMD_ERRORS); - return Status_Timeout; - } - BL_DRV_DUMMY; - BL_DRV_DUMMY; - } - sd_status = SDH_CMDWaitStatus; - SDH_DisableIntSource(SDH_INT_CMD_COMPLETED | SDH_INT_CMD_ERRORS); - -#else - - uint32_t intFlag; - while (1) { - intFlag = SDH_GetIntStatus(); - if (intFlag & SDH_INT_CMD_ERRORS) { - sd_status = SD_CMD_ERROR; - break; - - } else if (intFlag & SDH_INT_CMD_COMPLETED) { - sd_status = SD_OK; - break; - - } else if ((uint32_t)SDH_GET_TIME() - time_node > SDIO_CMDTIMEOUT_MS) { - SDH_MSG("SDH send CMD%ld timeout: %ld ms\r\n", cmd->index, (uint32_t)SDH_GET_TIME() - time_node); - return Status_Timeout; - } - BL_DRV_DUMMY; - BL_DRV_DUMMY; - } - SDH_ClearIntStatus(intFlag); - -#endif - - // SDH_MSG("SDH send CMD%ld used time : %ld\r\n", cmd->index, (uint32_t)SDH_GET_TIME() - time_node); - - if (sd_status != SD_OK) { - SDH_MSG("SDH send CMD%ld error\r\n", cmd->index); - errorstatus = Status_SDH_CmdResponseError; - } else { - SDH_GetCmdResp(cmd); - SDH_MSG("SDH send CMD%ld success\r\n", cmd->index); - } - - return errorstatus; -} - -static void SDH_GPIO_Init(uint32_t bus_wide) -{ - GLB_GPIO_Cfg_Type cfg; - uint8_t gpiopins[6]; - uint8_t gpiofuns[6]; - uint8_t i = 0; - - cfg.gpioMode = GPIO_MODE_AF; - cfg.pullType = GPIO_PULL_UP; - cfg.drive = 2; - cfg.smtCtrl = 1; - - gpiopins[0] = SDH_CLK_PIN; - gpiopins[1] = SDH_CMD_PIN; - gpiopins[2] = SDH_DAT0_PIN; - gpiopins[3] = SDH_DAT1_PIN; - gpiopins[4] = SDH_DAT2_PIN; - gpiopins[5] = SDH_DAT3_PIN; - - gpiofuns[0] = SDH_CLK_PIN_FUN; - gpiofuns[1] = SDH_CMD_PIN_FUN; - gpiofuns[2] = SDH_DAT0_PIN_FUN; - gpiofuns[3] = SDH_DAT1_PIN_FUN; - gpiofuns[4] = SDH_DAT2_PIN_FUN; - gpiofuns[5] = SDH_DAT3_PIN_FUN; - switch (bus_wide) { - case SDH_DATA_BUS_WIDTH_1BIT: - for (i = 1; i < sizeof(gpiopins) - 3; i++) { - cfg.gpioPin = gpiopins[i]; - cfg.gpioFun = gpiofuns[i]; - GLB_GPIO_Init(&cfg); - } - break; - - case SDH_DATA_BUS_WIDTH_4BITS: - for (i = 1; i < sizeof(gpiopins); i++) { - cfg.gpioPin = gpiopins[i]; - cfg.gpioFun = gpiofuns[i]; - GLB_GPIO_Init(&cfg); - } - break; - - /*set 1bit as default*/ - default: - for (i = 1; i < sizeof(gpiopins) - 3; i++) { - cfg.gpioPin = gpiopins[i]; - cfg.gpioFun = gpiofuns[i]; - GLB_GPIO_Init(&cfg); - } - break; - } - - cfg.gpioPin = gpiopins[0]; - cfg.gpioFun = gpiofuns[0]; - cfg.pullType = GPIO_PULL_NONE; - GLB_GPIO_Init(&cfg); -} - -static void SDH_HostInit(void) -{ - /* initialise SDH controller*/ - SDH_Cfg_Type_Instance.vlot18Enable = DISABLE; - SDH_Cfg_Type_Instance.highSpeed = ENABLE; - SDH_Cfg_Type_Instance.dataWidth = SDH_DATA_BUS_WIDTH_1BIT; - SDH_Cfg_Type_Instance.volt = SDH_VOLTAGE_3P3V; - SDH_Cfg_Type_Instance.srcClock = sdhClockSrc; - SDH_Cfg_Type_Instance.busClock = sdhClockInit; - SDH_Ctrl_Init(&SDH_Cfg_Type_Instance); - - /*setup timeout counter*/ - SDH_Set_Timeout(0x0e); - - /*power on host controller*/ - SDH_Powon(); -} - -/* -* GO_IDLE_STATE, send card to reset state -*/ -static status_t SDH_GoIdle(void) -{ - status_t errorstatus = Status_Success; - SDH_CMD_Cfg_Type SDH_CMD_Cfg_TypeInstance; - - /*CMD0: GO_IDLE_STATE, send card to reset state*/ - SDH_CMD_Cfg_TypeInstance.index = SD_CMD_GO_IDLE_STATE; - SDH_CMD_Cfg_TypeInstance.argument = 0; - SDH_CMD_Cfg_TypeInstance.type = SDH_CMD_NORMAL; - SDH_CMD_Cfg_TypeInstance.respType = SDH_RESP_NONE; - SDH_CMD_Cfg_TypeInstance.flag = SDH_TRANS_FLAG_NONE; - - errorstatus = SDH_SendCardCommand(&SDH_CMD_Cfg_TypeInstance); - return errorstatus; -} - -static status_t SD_SendApplicationCmd(uint32_t relativeAddress) -{ - status_t errorstatus = Status_Success; - SDH_CMD_Cfg_Type SDH_CMD_Cfg_TypeInstance; - - /* send CMD55 */ - SDH_CMD_Cfg_TypeInstance.index = SD_CMD_APP_CMD; - SDH_CMD_Cfg_TypeInstance.argument = relativeAddress; - SDH_CMD_Cfg_TypeInstance.type = SDH_CMD_NORMAL; - SDH_CMD_Cfg_TypeInstance.respType = SDH_RESP_R1; - SDH_CMD_Cfg_TypeInstance.flag = SDH_TRANS_FLAG_NONE; - - errorstatus = SDH_SendCardCommand(&SDH_CMD_Cfg_TypeInstance); - - if (errorstatus != Status_Success) { - return Status_SDH_CmdResponseError; - } else if (SDH_CMD_Cfg_TypeInstance.response[0] & SD_CSR_ERRORBITS) { - return Status_SDH_CmdResponseError; - } - - return errorstatus; -} - -static status_t SD_SendInterfaceCondition(void) -{ - status_t errorstatus = Status_Success; - SDH_CMD_Cfg_Type SDH_CMD_Cfg_TypeInstance; - - /* CMD8: SEND_IF_COND */ - SDH_CMD_Cfg_TypeInstance.index = SD_CMD_HS_SEND_EXT_CSD; - SDH_CMD_Cfg_TypeInstance.argument = SD_CHECK_PATTERN; - SDH_CMD_Cfg_TypeInstance.type = SDH_CMD_NORMAL; - SDH_CMD_Cfg_TypeInstance.respType = SDH_RESP_R7; - SDH_CMD_Cfg_TypeInstance.flag = SDH_TRANS_FLAG_NONE; - - errorstatus = SDH_SendCardCommand(&SDH_CMD_Cfg_TypeInstance); - - if (errorstatus != Status_Success) { - return Status_SDH_CmdResponseError; - } - - SDH_MSG("Response to CMD8 is: 0x%02lX.\r\n", SDH_CMD_Cfg_TypeInstance.response[0]); - - if ((SDH_CMD_Cfg_TypeInstance.response[0U] & 0xFFU) != (SD_CHECK_PATTERN & 0xff)) { - return Status_SDH_CardNotSupport; - } - - return errorstatus; -} - -static status_t SD_ApplicationSendOperationCondition(sd_card_t *card, uint32_t argument) -{ - status_t errorstatus = Status_Success; - uint32_t response = 0, count = 0, validvoltage = 0; - SDH_CMD_Cfg_Type SDH_CMD_Cfg_TypeInstance; - - do { - if (Status_Success != (errorstatus = SD_SendApplicationCmd(0))) { - return errorstatus; - } - - /*ACMD41*/ - SDH_CMD_Cfg_TypeInstance.index = SD_CMD_SD_APP_OP_COND; - SDH_CMD_Cfg_TypeInstance.argument = argument; - SDH_CMD_Cfg_TypeInstance.type = SDH_CMD_NORMAL; - SDH_CMD_Cfg_TypeInstance.respType = SDH_RESP_R3; - SDH_CMD_Cfg_TypeInstance.flag = SDH_TRANS_FLAG_NONE; - - errorstatus = SDH_SendCardCommand(&SDH_CMD_Cfg_TypeInstance); - - if (errorstatus != Status_Success) { - return Status_SDH_CmdResponseError; - } - - response = SDH_CMD_Cfg_TypeInstance.response[0]; - validvoltage = (((response >> 31) == 1) ? 1 : 0); - count++; - } while ((!validvoltage) && (count < SD_MAX_VOLT_TRIAL)); - - if (count == SD_MAX_VOLT_TRIAL) { - return Status_Timeout; - } else { - card->ocr = response; - - if (response &= SD_OcrHostCapacitySupportFlag) { - /* change from sdsc to sdhc */ - card->flags |= SD_SupportHighCapacityFlag; - } - } - - return errorstatus; -} -static status_t SD_AllSendCid(sd_card_t *card) -{ - status_t errorstatus = Status_Success; - SDH_CMD_Cfg_Type SDH_CMD_Cfg_TypeInstance; - - /* CMD2: SD_CMD_ALL_SEND_CID */ - SDH_CMD_Cfg_TypeInstance.index = SD_CMD_ALL_SEND_CID; - SDH_CMD_Cfg_TypeInstance.argument = 0; - SDH_CMD_Cfg_TypeInstance.type = SDH_CMD_NORMAL; - SDH_CMD_Cfg_TypeInstance.respType = SDH_RESP_R2; - SDH_CMD_Cfg_TypeInstance.flag = SDH_TRANS_FLAG_NONE; - - errorstatus = SDH_SendCardCommand(&SDH_CMD_Cfg_TypeInstance); - - if (errorstatus != Status_Success) { - return Status_SDH_CmdResponseError; - } - - card->rawCid[0] = SDH_CMD_Cfg_TypeInstance.response[0]; - card->rawCid[1] = SDH_CMD_Cfg_TypeInstance.response[1]; - card->rawCid[2] = SDH_CMD_Cfg_TypeInstance.response[2]; - card->rawCid[3] = SDH_CMD_Cfg_TypeInstance.response[3]; - - SD_DecodeCid(card, card->rawCid); - - return errorstatus; -} - -static status_t SD_SendRca(sd_card_t *card) -{ - status_t errorstatus = Status_Success; - SDH_CMD_Cfg_Type SDH_CMD_Cfg_TypeInstance; - - /*CMD3: send relative card address*/ - SDH_CMD_Cfg_TypeInstance.index = SD_CMD_SET_REL_ADDR; - SDH_CMD_Cfg_TypeInstance.argument = 0; - SDH_CMD_Cfg_TypeInstance.type = SDH_CMD_NORMAL; - SDH_CMD_Cfg_TypeInstance.respType = SDH_RESP_R6; - SDH_CMD_Cfg_TypeInstance.flag = SDH_TRANS_FLAG_NONE; - - errorstatus = SDH_SendCardCommand(&SDH_CMD_Cfg_TypeInstance); - - if (errorstatus != Status_Success) { - return Status_SDH_CmdResponseError; - } - - card->relativeAddress = SDH_CMD_Cfg_TypeInstance.response[0] >> 16; - - return errorstatus; -} - -static status_t SD_SendCsd(sd_card_t *card) -{ - status_t errorstatus = Status_Success; - SDH_CMD_Cfg_Type SDH_CMD_Cfg_TypeInstance; - - /*CMD9: send card-specific data(CSD)*/ - SDH_CMD_Cfg_TypeInstance.index = SD_CMD_SEND_CSD; - SDH_CMD_Cfg_TypeInstance.argument = (uint32_t)((card->relativeAddress) << 16); - SDH_CMD_Cfg_TypeInstance.type = SDH_CMD_NORMAL; - SDH_CMD_Cfg_TypeInstance.respType = SDH_RESP_R2; - SDH_CMD_Cfg_TypeInstance.flag = SDH_TRANS_FLAG_NONE; - - errorstatus = SDH_SendCardCommand(&SDH_CMD_Cfg_TypeInstance); - - if (errorstatus != Status_Success) { - return Status_SDH_CmdResponseError; - } - - card->rawCsd[0] = SDH_CMD_Cfg_TypeInstance.response[0]; - card->rawCsd[1] = SDH_CMD_Cfg_TypeInstance.response[1]; - card->rawCsd[2] = SDH_CMD_Cfg_TypeInstance.response[2]; - card->rawCsd[3] = SDH_CMD_Cfg_TypeInstance.response[3]; - - SD_DecodeCsd(card, card->rawCsd); - - return errorstatus; -} - -static status_t SD_SelectCard(sd_card_t *card, BL_Fun_Type NewState) -{ - status_t errorstatus = Status_Success; - SDH_CMD_Cfg_Type SDH_CMD_Cfg_TypeInstance; - - /* CMD7: select/deselect specified card */ - SDH_CMD_Cfg_TypeInstance.index = SD_CMD_SEL_DESEL_CARD; - - if (NewState == ENABLE) { - SDH_CMD_Cfg_TypeInstance.argument = (uint32_t)((card->relativeAddress) << 16); - SDH_CMD_Cfg_TypeInstance.respType = SDH_RESP_R1B; - } else { - SDH_CMD_Cfg_TypeInstance.argument = 0; - SDH_CMD_Cfg_TypeInstance.respType = SDH_RESP_NONE; - } - - SDH_CMD_Cfg_TypeInstance.type = SDH_CMD_NORMAL; - SDH_CMD_Cfg_TypeInstance.flag = SDH_TRANS_FLAG_NONE; - - errorstatus = SDH_SendCardCommand(&SDH_CMD_Cfg_TypeInstance); - - if (errorstatus != Status_Success) { - return Status_SDH_TransferFailed; - } else if ((NewState == ENABLE) && (SDH_CMD_Cfg_TypeInstance.response[0] & SD_CSR_ERRORBITS)) { - return Status_SDH_CmdResponseError; - } - - return errorstatus; -} - -/* get CSR */ -static status_t SD_SendScr(sd_card_t *card) -{ - status_t errorstatus = Status_Success; - SDH_Stat_Type stat = SDH_STAT_SUCCESS; - SD_Error sd_status; - - SDH_CMD_Cfg_Type SDH_CMD_Cfg_TypeInstance; - SDH_Data_Cfg_Type SDH_Data_Cfg_TypeInstance; - uint32_t tempscr[2] = { 0, 0 }; - uint32_t time_node; - - /* send CMD55 */ - errorstatus = SD_SendApplicationCmd((uint32_t)((card->relativeAddress) << 16)); - - if (errorstatus != Status_Success) { - goto out; - } - - /*!< Set Block Size To 8 Bytes */ - SDH_Data_Cfg_TypeInstance.enableAutoCommand12 = DISABLE; - SDH_Data_Cfg_TypeInstance.enableAutoCommand23 = DISABLE; - SDH_Data_Cfg_TypeInstance.enableIgnoreError = DISABLE; - SDH_Data_Cfg_TypeInstance.dataType = SDH_TRANS_DATA_NORMAL; - SDH_Data_Cfg_TypeInstance.blockSize = 8; - SDH_Data_Cfg_TypeInstance.blockCount = 1; - SDH_Data_Cfg_TypeInstance.rxDataLen = 0; - SDH_Data_Cfg_TypeInstance.rxData = tempscr; - SDH_Data_Cfg_TypeInstance.txDataLen = 0; - SDH_Data_Cfg_TypeInstance.txData = NULL; - /* Config the data transfer parameter */ - stat = SDH_ConfigDataTranfer(&SDH_Data_Cfg_TypeInstance); - - if (SDH_STAT_SUCCESS != stat) { - return Status_SDH_TransferFailed; - } - - /*!< Send ACMD51 SD_APP_SEND_SCR with argument as 0 */ - SDH_CMD_Cfg_TypeInstance.index = SD_CMD_SD_APP_SEND_SCR; - SDH_CMD_Cfg_TypeInstance.argument = 0; - SDH_CMD_Cfg_TypeInstance.type = SDH_CMD_NORMAL; - SDH_CMD_Cfg_TypeInstance.respType = SDH_RESP_R1; - SDH_CMD_Cfg_TypeInstance.flag = SDH_TRANS_FLAG_DATA_PRESENT; - - errorstatus = SDH_SendCardCommand(&SDH_CMD_Cfg_TypeInstance); - - if (errorstatus != Status_Success) { - goto out; - } else if (SDH_CMD_Cfg_TypeInstance.response[0] & SD_CSR_ERRORBITS) { - errorstatus = Status_SDH_CmdResponseError; - goto out; - } - - /* Waiting for CSR data */ - time_node = (uint32_t)SDH_GET_TIME(); - -#if SDIO_SDCARD_INT_MODE - - SDH_DataWaitStatus = SD_WAITING; - SDH_EnableIntSource(SDH_INT_BUFFER_READ_READY | SDH_INT_DATA_COMPLETED | SDH_INT_DATA_ERRORS | SDH_INT_DMA_ERROR | SDH_INT_AUTO_CMD12_ERROR); - - /*wait for Xfer status. might pending here in multi-task OS*/ - while (SDH_DataWaitStatus == SD_WAITING) { - if ((uint32_t)SDH_GET_TIME() - time_node > SDIO_CMDTIMEOUT_MS) { - SDH_MSG("sdh get csr data timeout: %ld ms\r\n", (uint32_t)SDH_GET_TIME() - time_node); - SDH_DisableIntSource(SDH_INT_BUFFER_READ_READY | SDH_INT_DATA_COMPLETED | SDH_INT_DATA_ERRORS | SDH_INT_DMA_ERROR | SDH_INT_AUTO_CMD12_ERROR); - errorstatus = Status_Timeout; - goto out; - } - BL_DRV_DUMMY; - BL_DRV_DUMMY; - } - - SDH_DisableIntSource(SDH_INT_BUFFER_READ_READY | SDH_INT_DATA_COMPLETED | SDH_INT_DATA_ERRORS | SDH_INT_DMA_ERROR | SDH_INT_AUTO_CMD12_ERROR); - sd_status = SDH_DataWaitStatus; - -#else - - uint32_t intFlag; - while (1) { - intFlag = SDH_GetIntStatus(); - if (intFlag & SDH_INT_DATA_ERRORS || intFlag & SDH_INT_DMA_ERROR) { - sd_status = SD_DataCfg_ERROR; - break; - - } else if (intFlag & SDH_INT_BUFFER_READ_READY || intFlag & SDH_INT_DATA_COMPLETED) { - sd_status = SD_OK; - break; - - } else if ((uint32_t)SDH_GET_TIME() - time_node > SDIO_CMDTIMEOUT_MS) { - SDH_MSG("SDH get csr data timeout: %ld ms\r\n", (uint32_t)SDH_GET_TIME() - time_node); - return Status_Timeout; - } - BL_DRV_DUMMY; - BL_DRV_DUMMY; - } - SDH_ClearIntStatus(intFlag); - -#endif - - if (sd_status == SD_OK) { - SDH_ReadDataPort(&SDH_Data_Cfg_TypeInstance); - card->rawScr[1] = ((tempscr[0] & SD_0TO7BITS) << 24) | ((tempscr[0] & SD_8TO15BITS) << 8) | ((tempscr[0] & SD_16TO23BITS) >> 8) | ((tempscr[0] & SD_24TO31BITS) >> 24); - card->rawScr[0] = ((tempscr[1] & SD_0TO7BITS) << 24) | ((tempscr[1] & SD_8TO15BITS) << 8) | ((tempscr[1] & SD_16TO23BITS) >> 8) | ((tempscr[1] & SD_24TO31BITS) >> 24); - SD_DecodeScr(card, card->rawScr); - SDH_MSG("SDH get csr success\r\n"); - } else { - errorstatus = Status_SDH_TransferFailed; - SDH_MSG("SDH get csr failed\r\n"); - goto out; - } - -out: - return errorstatus; -} - -/* get SSR */ -static status_t SD_SendSsr(sd_card_t *card) -{ - status_t errorstatus = Status_Success; - SDH_Stat_Type stat = SDH_STAT_SUCCESS; - SD_Error sd_status; - uint32_t time_node; - - SDH_CMD_Cfg_Type SDH_CMD_Cfg_TypeInstance; - SDH_Data_Cfg_Type SDH_Data_Cfg_TypeInstance; - - errorstatus = SD_SendApplicationCmd((uint32_t)((card->relativeAddress) << 16)); - - if (errorstatus != Status_Success) { - goto out; - } - - /*!< Set Block Size To 512 Bytes */ - SDH_Data_Cfg_TypeInstance.enableAutoCommand12 = DISABLE; - SDH_Data_Cfg_TypeInstance.enableAutoCommand23 = DISABLE; - SDH_Data_Cfg_TypeInstance.enableIgnoreError = DISABLE; - SDH_Data_Cfg_TypeInstance.dataType = SDH_TRANS_DATA_NORMAL; - SDH_Data_Cfg_TypeInstance.blockSize = 64; - SDH_Data_Cfg_TypeInstance.blockCount = 1; - SDH_Data_Cfg_TypeInstance.rxDataLen = 0; - SDH_Data_Cfg_TypeInstance.rxData = card->rawSsr; - SDH_Data_Cfg_TypeInstance.txDataLen = 0; - SDH_Data_Cfg_TypeInstance.txData = NULL; - /* Config the data transfer parameter */ - stat = SDH_ConfigDataTranfer(&SDH_Data_Cfg_TypeInstance); - - if (SDH_STAT_SUCCESS != stat) { - return Status_SDH_TransferFailed; - } - - /*!< Send ACMD13 SD_APP_SEND_SCR with argument as 0 */ - SDH_CMD_Cfg_TypeInstance.index = SD_CMD_SD_APP_STAUS; - SDH_CMD_Cfg_TypeInstance.argument = 0; - SDH_CMD_Cfg_TypeInstance.type = SDH_CMD_NORMAL; - SDH_CMD_Cfg_TypeInstance.respType = SDH_RESP_R1; - SDH_CMD_Cfg_TypeInstance.flag = SDH_TRANS_FLAG_DATA_PRESENT; - - errorstatus = SDH_SendCardCommand(&SDH_CMD_Cfg_TypeInstance); - - if (errorstatus != Status_Success) { - goto out; - } else if (SDH_CMD_Cfg_TypeInstance.response[0] & SD_CSR_ERRORBITS) { - errorstatus = Status_SDH_CmdResponseError; - goto out; - } - - /* Waiting for SSR data */ - time_node = (uint32_t)SDH_GET_TIME(); - -#if SDIO_SDCARD_INT_MODE - - SDH_DataWaitStatus = SD_WAITING; - SDH_EnableIntSource(SDH_INT_BUFFER_READ_READY | SDH_INT_DATA_COMPLETED | SDH_INT_DATA_ERRORS | SDH_INT_DMA_ERROR | SDH_INT_AUTO_CMD12_ERROR); - - /*wait for Xfer status. might pending here in multi-task OS*/ - while (SDH_DataWaitStatus == SD_WAITING) { - if ((uint32_t)SDH_GET_TIME() - time_node > SDIO_CMDTIMEOUT_MS) { - SDH_MSG("SDH get ssr data timeout: %ld ms\r\n", (uint32_t)SDH_GET_TIME() - time_node); - SDH_DisableIntSource(SDH_INT_BUFFER_READ_READY | SDH_INT_DATA_COMPLETED | SDH_INT_DATA_ERRORS | SDH_INT_DMA_ERROR | SDH_INT_AUTO_CMD12_ERROR); - errorstatus = Status_Timeout; - goto out; - } - BL_DRV_DUMMY; - BL_DRV_DUMMY; - } - - SDH_DisableIntSource(SDH_INT_BUFFER_READ_READY | SDH_INT_DATA_COMPLETED | SDH_INT_DATA_ERRORS | SDH_INT_DMA_ERROR | SDH_INT_AUTO_CMD12_ERROR); - sd_status = SDH_DataWaitStatus; - -#else - - uint32_t intFlag; - while (1) { - intFlag = SDH_GetIntStatus(); - if (intFlag & SDH_INT_DATA_ERRORS || intFlag & SDH_INT_DMA_ERROR) { - sd_status = SD_DataCfg_ERROR; - break; - - } else if (intFlag & SDH_INT_BUFFER_READ_READY || intFlag & SDH_INT_DATA_COMPLETED) { - sd_status = SD_OK; - break; - - } else if ((uint32_t)SDH_GET_TIME() - time_node > SDIO_CMDTIMEOUT_MS) { - SDH_MSG("SDH get ssr data timeout: %ld ms\r\n", (uint32_t)SDH_GET_TIME() - time_node); - errorstatus = Status_Timeout; - goto out; - } - BL_DRV_DUMMY; - BL_DRV_DUMMY; - } - SDH_ClearIntStatus(intFlag); - -#endif - - if (sd_status == SD_OK) { - SDH_ReadDataPort(&SDH_Data_Cfg_TypeInstance); - SDH_MSG("SDH get ssr success\r\n"); - } else { - errorstatus = Status_SDH_TransferFailed; - SDH_MSG("SDH get ssr failed\r\n"); - goto out; - } - -out: - return errorstatus; -} - -/* Set Data Bus Width */ -static status_t SD_SetDataBusWidth(sd_card_t *card, SDH_Data_Bus_Width_Type width) -{ - status_t errorstatus = Status_Success; - SDH_CMD_Cfg_Type SDH_CMD_Cfg_TypeInstance; - - if (width == SDH_DATA_BUS_WIDTH_1BIT) { - SDH_CMD_Cfg_TypeInstance.argument = 0; - } else if (width == SDH_DATA_BUS_WIDTH_4BITS) { - SDH_CMD_Cfg_TypeInstance.argument = 2; - } else { - return Status_InvalidArgument; - } - - errorstatus = SD_SendApplicationCmd((uint32_t)((card->relativeAddress) << 16)); - - if (errorstatus != Status_Success) { - goto out; - } - - /*!< Send ACMD6 APP_CMD with argument as 2 for wide bus mode */ - SDH_CMD_Cfg_TypeInstance.index = SD_CMD_APP_SD_SET_BUSWIDTH; - - SDH_CMD_Cfg_TypeInstance.type = SDH_CMD_NORMAL; - SDH_CMD_Cfg_TypeInstance.respType = SDH_RESP_R1; - SDH_CMD_Cfg_TypeInstance.flag = SDH_TRANS_FLAG_NONE; - - errorstatus = SDH_SendCardCommand(&SDH_CMD_Cfg_TypeInstance); - - if (errorstatus != Status_Success) { - goto out; - } else if (SDH_CMD_Cfg_TypeInstance.response[0] & SD_CSR_ERRORBITS) { - errorstatus = Status_SDH_CmdResponseError; - goto out; - } - - /* reinitialise SDH controller*/ - SDH_Cfg_Type_Instance.vlot18Enable = DISABLE; - SDH_Cfg_Type_Instance.highSpeed = ENABLE; - SDH_Cfg_Type_Instance.dataWidth = width; - SDH_Cfg_Type_Instance.volt = SDH_VOLTAGE_3P3V; - SDH_Cfg_Type_Instance.srcClock = sdhClockSrc; - SDH_Cfg_Type_Instance.busClock = sdhClockTransfer; - SDH_Ctrl_Init(&SDH_Cfg_Type_Instance); - -out: - return errorstatus; -} - -/* switch function - mode: 0 check function, 1 set function - group: group number,1~6 - number: - */ -static status_t SD_SwitchFunction(uint32_t mode, uint32_t group, uint32_t number, uint32_t status[16]) -{ - status_t errorstatus = Status_Success; - SDH_Stat_Type stat = SDH_STAT_SUCCESS; - SD_Error sd_status; - uint32_t time_node; - - SDH_CMD_Cfg_Type SDH_CMD_Cfg_TypeInstance; - SDH_Data_Cfg_Type SDH_Data_Cfg_TypeInstance; - - /*!< Set Block Size To 64 Bytes */ - SDH_Data_Cfg_TypeInstance.enableAutoCommand12 = DISABLE; - SDH_Data_Cfg_TypeInstance.enableAutoCommand23 = DISABLE; - SDH_Data_Cfg_TypeInstance.enableIgnoreError = DISABLE; - SDH_Data_Cfg_TypeInstance.dataType = SDH_TRANS_DATA_NORMAL; - SDH_Data_Cfg_TypeInstance.blockSize = 64; - SDH_Data_Cfg_TypeInstance.blockCount = 1; - SDH_Data_Cfg_TypeInstance.rxDataLen = 0; - SDH_Data_Cfg_TypeInstance.rxData = status; - SDH_Data_Cfg_TypeInstance.txDataLen = 0; - SDH_Data_Cfg_TypeInstance.txData = NULL; - /* Config the data transfer parameter */ - stat = SDH_ConfigDataTranfer(&SDH_Data_Cfg_TypeInstance); - - if (SDH_STAT_SUCCESS != stat) { - return Status_SDH_TransferFailed; - } - - /*!< Send CMD6 SD_CMD_HS_SWITCH with argument as 0 */ - SDH_CMD_Cfg_TypeInstance.index = SD_CMD_HS_SWITCH; - SDH_CMD_Cfg_TypeInstance.argument = (mode << 31U | 0x00FFFFFFU); - SDH_CMD_Cfg_TypeInstance.argument &= ~((uint32_t)(0xFU) << (group * 4U)); - SDH_CMD_Cfg_TypeInstance.argument |= (number << (group * 4U)); - SDH_CMD_Cfg_TypeInstance.type = SDH_CMD_NORMAL; - SDH_CMD_Cfg_TypeInstance.respType = SDH_RESP_R1; - SDH_CMD_Cfg_TypeInstance.flag = SDH_TRANS_FLAG_DATA_PRESENT; - - errorstatus = SDH_SendCardCommand(&SDH_CMD_Cfg_TypeInstance); - - if (errorstatus != Status_Success) { - goto out; - } else if (SDH_CMD_Cfg_TypeInstance.response[0] & SD_CSR_ERRORBITS) { - errorstatus = Status_SDH_CmdResponseError; - goto out; - } - - /* Waiting for CSR data */ - time_node = (uint32_t)SDH_GET_TIME(); - -#if SDIO_SDCARD_INT_MODE - - SDH_DataWaitStatus = SD_WAITING; - SDH_EnableIntSource(SDH_INT_BUFFER_READ_READY | SDH_INT_DATA_COMPLETED | SDH_INT_DATA_ERRORS | SDH_INT_DMA_ERROR); - - /*wait for Xfer status. might pending here in multi-task OS*/ - while (SDH_DataWaitStatus == SD_WAITING) { - if ((uint32_t)SDH_GET_TIME() - time_node > SDIO_CMDTIMEOUT_MS) { - SDH_MSG("SDH get CMD6 status data timeout: %ld ms\r\n", (uint32_t)SDH_GET_TIME() - time_node); - SDH_DisableIntSource(SDH_INT_BUFFER_READ_READY | SDH_INT_DATA_COMPLETED | SDH_INT_DATA_ERRORS | SDH_INT_DMA_ERROR); - errorstatus = Status_Timeout; - goto out; - } - BL_DRV_DUMMY; - BL_DRV_DUMMY; - } - - SDH_DisableIntSource(SDH_INT_BUFFER_READ_READY | SDH_INT_DATA_COMPLETED | SDH_INT_DATA_ERRORS | SDH_INT_DMA_ERROR); - sd_status = SDH_DataWaitStatus; - -#else - - uint32_t intFlag; - while (1) { - intFlag = SDH_GetIntStatus(); - if (intFlag & SDH_INT_DATA_ERRORS || intFlag & SDH_INT_DMA_ERROR) { - sd_status = SD_DataCfg_ERROR; - break; - - } else if (intFlag & SDH_INT_BUFFER_READ_READY || intFlag & SDH_INT_DATA_COMPLETED) { - sd_status = SD_OK; - break; - - } else if ((uint32_t)SDH_GET_TIME() - time_node > SDIO_CMDTIMEOUT_MS) { - SDH_MSG("SDH get CMD6 status data timeout: %ld ms\r\n", (uint32_t)SDH_GET_TIME() - time_node); - return Status_Timeout; - } - BL_DRV_DUMMY; - BL_DRV_DUMMY; - } - SDH_ClearIntStatus(intFlag); - -#endif - - if (sd_status == SD_OK) { - SDH_ReadDataPort(&SDH_Data_Cfg_TypeInstance); - SDH_MSG("SDH get CMD6 status data success\r\n"); - } else { - errorstatus = Status_SDH_TransferFailed; - SDH_MSG("SDH get CMD6 status data failed\r\n"); - goto out; - } - -out: - return errorstatus; -} - -/* */ -static ATTR_USED status_t SD_SelectFunction(uint32_t group, uint32_t function) -{ - status_t errorstatus = Status_Success; - uint32_t cmd6Status[16] = { 0 }; - uint16_t functionGroupInfo[6U] = { 0 }; - uint32_t currentFunctionStatus = 0U; - - uint32_t i; - - /* Check if card support high speed mode. */ - if (Status_Success != SD_SwitchFunction(SDH_SwitchCheck, group, function, cmd6Status)) { - return Status_SDH_SDIO_SwitchHighSpeedFail; - } - - for (i = 0; i < 16; i++) { - SDH_MSG("cmd6Status[%ld]=0x%lX.\r\n", i, cmd6Status[i]); - } - - /* In little endian mode, SD bus byte transferred first is the byte stored in lowest byte position in - a word which will cause 4 byte's sequence in a word is not consistent with their original sequence from - card. So the sequence of 4 bytes received in a word should be converted. */ - cmd6Status[0U] = SWAP_WORD_BYTE_SEQUENCE(cmd6Status[0U]); - cmd6Status[1U] = SWAP_WORD_BYTE_SEQUENCE(cmd6Status[1U]); - cmd6Status[2U] = SWAP_WORD_BYTE_SEQUENCE(cmd6Status[2U]); - cmd6Status[3U] = SWAP_WORD_BYTE_SEQUENCE(cmd6Status[3U]); - cmd6Status[4U] = SWAP_WORD_BYTE_SEQUENCE(cmd6Status[4U]); - - functionGroupInfo[5U] = (uint16_t)cmd6Status[0U]; - functionGroupInfo[4U] = (uint16_t)(cmd6Status[1U] >> 16U); - functionGroupInfo[3U] = (uint16_t)(cmd6Status[1U]); - functionGroupInfo[2U] = (uint16_t)(cmd6Status[2U] >> 16U); - functionGroupInfo[1U] = (uint16_t)(cmd6Status[2U]); - functionGroupInfo[0U] = (uint16_t)(cmd6Status[3U] >> 16U); - currentFunctionStatus = ((cmd6Status[3U] & 0xFFFFU) << 8U) | (cmd6Status[4U] >> 24U); - - for (i = 0; i < 6; i++) { - SDH_MSG("functionGroupInfo[%ld]=0x%X.\r\n", i, functionGroupInfo[i]); - } - - SDH_MSG("currentFunctionStatus = 0x%lX.\r\n", currentFunctionStatus); - - /* check if function is support */ - if (((functionGroupInfo[group] & (1 << function)) == 0U) || - ((currentFunctionStatus >> (group * 4U)) & 0xFU) != function) { - return Status_SDH_SDIO_SwitchHighSpeedFail; - } - - /* Check if card support high speed mode. */ - if (Status_Success != SD_SwitchFunction(SDH_SwitchSet, group, function, cmd6Status)) { - return Status_SDH_SDIO_SwitchHighSpeedFail; - } - - /* In little endian mode is little endian, SD bus byte transferred first is the byte stored in lowest byte - position in a word which will cause 4 byte's sequence in a word is not consistent with their original - sequence from card. So the sequence of 4 bytes received in a word should be converted. */ - cmd6Status[3U] = SWAP_WORD_BYTE_SEQUENCE(cmd6Status[3U]); - cmd6Status[4U] = SWAP_WORD_BYTE_SEQUENCE(cmd6Status[4U]); - - /* According to the "switch function status[bits 511~0]" return by switch command in mode "set function": - -check if group 1 is successfully changed to function 1 by checking if bits 379~376 equal value 1; - */ - currentFunctionStatus = ((cmd6Status[3U] & 0xFFFFU) << 8U) | (cmd6Status[4U] >> 24U); - SDH_MSG("currentFunctionStatus = 0x%lX.\r\n", currentFunctionStatus); - - if (((currentFunctionStatus >> (group * 4U)) & 0xFU) != function) { - return Status_SDH_SDIO_SwitchHighSpeedFail; - } - - return errorstatus; -} - -static status_t SD_SetBlockSize(uint32_t blockSize) -{ - status_t errorstatus = Status_Success; - SDH_CMD_Cfg_Type SDH_CMD_Cfg_TypeInstance; - - /*!< Set Block Size for SDSC Card,cmd16,no impact on SDHC card */ - SDH_CMD_Cfg_TypeInstance.index = SD_CMD_SET_BLOCKLEN; - SDH_CMD_Cfg_TypeInstance.argument = (uint32_t)blockSize; - SDH_CMD_Cfg_TypeInstance.type = SDH_CMD_NORMAL; - SDH_CMD_Cfg_TypeInstance.respType = SDH_RESP_R1; - SDH_CMD_Cfg_TypeInstance.flag = SDH_TRANS_FLAG_NONE; - - errorstatus = SDH_SendCardCommand(&SDH_CMD_Cfg_TypeInstance); - - if (errorstatus != Status_Success) { - goto out; - } else if (SDH_CMD_Cfg_TypeInstance.response[0] & SD_CSR_ERRORBITS) { - errorstatus = Status_SDH_CmdResponseError; - goto out; - } - -out: - return errorstatus; -} - -static status_t SDH_SDCardInit(uint32_t bus_wide, sd_card_t *card) -{ - status_t errorstatus = Status_Success; - uint32_t applicationCommand41Argument = SD_OcrVdd33_34Flag | SD_OcrVdd32_33Flag; - - /* reset variables */ - card->flags = 0U; - - SDH_MSG("SD CARD GO IDEL...\r\n"); - errorstatus = SDH_GoIdle(); - - if (errorstatus != SD_OK) { - return Status_SDH_GoIdleFailed; - } - - SDH_MSG("SD CARD GO IDEL END\r\n"); - - for (uint16_t i = 0; i < 4; i++) { - /* send CMD8 */ - errorstatus = SD_SendInterfaceCondition(); - /* check response */ - if (errorstatus == Status_Success) { - /* SDHC or SDXC card */ - applicationCommand41Argument |= SD_OcrHostCapacitySupportFlag; - card->flags |= SD_SupportSdhcFlag; - break; - } else { - /* Try sending CMD8 again */ - SDH_MSG("Try sending CMD8 again:%d\r\n", i + 1); - errorstatus = SDH_GoIdle(); - if (errorstatus != Status_Success) { - return Status_SDH_GoIdleFailed; - } - } - } - - /* Set card interface condition according to SDHC capability and card's supported interface condition. */ - errorstatus = SD_ApplicationSendOperationCondition(card, applicationCommand41Argument); - - if (errorstatus != Status_Success) { - return Status_SDH_SendApplicationCommandFailed; - } - - SDH_MSG("\r\nOCR is: 0x%02lX.\r\n", card->ocr); - SDH_MSG("\t SDHC supported[%s].\r\n\r\n", ((card->flags & SD_SupportHighCapacityFlag) ? "YES" : "NO")); - - errorstatus = SD_AllSendCid(card); - - if (errorstatus != Status_Success) { - return Status_SDH_AllSendCidFailed; - } - - SDH_MSG("\r\nCID is: 0x%02lX-0x%02lX-0x%02lX-0x%02lX.\r\n", - card->rawCid[0], card->rawCid[1], card->rawCid[2], card->rawCid[3]); - SDH_MSG("\t manufacturerID is: 0x%02X.\r\n", card->cid.manufacturerID); - SDH_MSG("\t applicationID is: %c%c.\r\n", (card->cid.applicationID) >> 8, card->cid.applicationID); - SDH_MSG("\t productName is: %c%c%c%c%c.\r\n", - card->cid.productName[0], card->cid.productName[1], card->cid.productName[2], card->cid.productName[3], card->cid.productName[4]); - SDH_MSG("\t manufacturerData is: 0x%02X.\r\n\r\n", card->cid.manufacturerData); - - errorstatus = SD_SendRca(card); - - if (errorstatus != Status_Success) { - return Status_SDH_SendRelativeAddressFailed; - } - - SDH_MSG("\r\nRCA is: 0x%02lX.\r\n\r\n", card->relativeAddress); - - errorstatus = SD_SendCsd(card); - - if (errorstatus != Status_Success) { - return Status_SDH_SendCsdFailed; - } - - SDH_MSG("\r\nCSD is: 0x%02lX-0x%02lX-0x%02lX-0x%02lX.\r\n", - card->rawCsd[0], card->rawCsd[1], card->rawCsd[2], card->rawCsd[3]); - SDH_MSG("\t CSD Version is: %s .\r\n", card->csd.csdStructure ? "csd version 2.0" : "csd version 1.0"); - SDH_MSG("\t blockLen=%ld, blockCounter=%ld, CardSize is %ld[MBytes].\r\n\r\n", card->blockSize, card->blockCount, (card->blockCount) >> 11); - - errorstatus = SD_SelectCard(card, ENABLE); - - if (errorstatus != Status_Success) { - return Status_SDH_SelectCardFailed; - } - - errorstatus = SD_SendScr(card); - - if (errorstatus != Status_Success) { - return Status_SDH_SendScrFailed; - } - - SDH_MSG("\r\nSCR is: 0x%lX-0x%lX.\r\n", card->rawScr[0], card->rawScr[1]); - SDH_MSG("\t SD Spec Version is: [0x%02lX]%s.\r\n", card->version, - (card->version & SD_SpecificationVersion3_0) ? "V3.0" : ((card->version & SD_SpecificationVersion2_0) ? "V2.0" : ((card->version & SD_SpecificationVersion1_1) ? "V1.1" : "V1.0"))); - SDH_MSG("\t Erased bit is %d.\r\n", (card->scr.flags & SD_ScrDataStatusAfterErase)); - SDH_MSG("\t 4-line supported[%s].\r\n", ((card->flags & SD_Support4BitWidthFlag) ? "YES" : "NO")); - SDH_MSG("\t SetBlockCountCmd supported[%s].\r\n", ((card->flags & SD_SupportSetBlockCountCmd) ? "YES" : "NO")); - SDH_MSG("\t SDXC supported[%s].\r\n\r\n", ((card->flags & SD_SupportSdxcFlag) ? "YES" : "NO")); - - if (card->flags & SD_Support4BitWidthFlag) { - errorstatus = SD_SetDataBusWidth(card, (SDH_Data_Bus_Width_Type)bus_wide); - } else { - errorstatus = SD_SetDataBusWidth(card, SDH_DATA_BUS_WIDTH_1BIT); - } - - if (errorstatus != Status_Success) { - return Status_SDH_SetDataBusWidthFailed; - } - - errorstatus = SD_SendSsr(card); - - if (errorstatus != Status_Success) { - return Status_SDH_SendSsrFailed; - } - - SDH_MSG("\r\nSSR[0] is: 0x%lX.\r\n", card->rawSsr[0]); - SDH_MSG("\t Current is %d-line mode.\r\n\r\n", (card->rawSsr[0] & 0x80) ? 4 : 1); - - errorstatus = SD_SetBlockSize(SDH_DEFAULT_BLOCK_SIZE); - - if (errorstatus != Status_Success) { - return Status_SDH_SetCardBlockSizeFailed; - } - - //SD_SelectFunction(SDH_GroupTimingMode,SDH_TimingSDR25HighSpeedMode); - - return errorstatus; -} - -/** - * @brief Initializes SD Card clock. - * @retval SD status - */ -status_t SDH_ClockSet(uint32_t clockInit, uint32_t clockSrc, uint32_t clockTransfer) -{ - sdhClockInit = clockInit; - sdhClockSrc = clockSrc; - sdhClockTransfer = clockTransfer; - - return Status_Success; -} - -/** - * @brief Initializes the SD card device. - * @retval SD status - */ -status_t SDH_Init(uint32_t bus_wide, sd_card_t *pOutCardInfo) -{ - pSDCardInfo = pOutCardInfo; - - /* gpio init */ - SDH_GPIO_Init(bus_wide); - - /* config sdh clock */ - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_SDH); - GLB_Set_SDH_CLK(1, GLB_SDH_CLK_WIFIPLL_96M, 0); - SDH_ClockSet(400000, 96000000, 96000000); - -#if SDIO_SDCARD_INT_MODE - SDH_INT_Init(); -#endif - - /* reset SDH controller*/ - SDH_Reset(); - - SDH_HostInit(); - - if (pOutCardInfo == NULL) { - return Status_InvalidArgument; - } else { - return SDH_SDCardInit(bus_wide, pOutCardInfo); - } -} - -/** - * @brief Allows to erase memory area specified for the given card. - * @param startaddr: the start address. - * @param endaddr: the end address. - * @retval SD_Error: SD Card Error code. - */ -status_t SD_Erase(uint32_t startaddr, uint32_t endaddr) -{ - status_t errorstatus = Status_Success; - uint8_t cardstate = 0; - - SDH_CMD_Cfg_Type SDH_CMD_Cfg_TypeInstance; - - /* SDSC card uses byte unit address*/ - if (!(pSDCardInfo->flags & SD_SupportHighCapacityFlag)) { - startaddr *= 512; - endaddr *= 512; - } - - /*!< Send CMD32 SD_ERASE_GRP_START with argument as addr */ - SDH_CMD_Cfg_TypeInstance.index = SD_CMD_SD_ERASE_GRP_START; - SDH_CMD_Cfg_TypeInstance.argument = startaddr; - SDH_CMD_Cfg_TypeInstance.type = SDH_CMD_NORMAL; - SDH_CMD_Cfg_TypeInstance.respType = SDH_RESP_R1; - SDH_CMD_Cfg_TypeInstance.flag = SDH_TRANS_FLAG_NONE; - - errorstatus = SDH_SendCardCommand(&SDH_CMD_Cfg_TypeInstance); - - if (errorstatus != Status_Success) { - goto out; - } else if (SDH_CMD_Cfg_TypeInstance.response[0] & SD_CSR_ERRORBITS) { - errorstatus = Status_SDH_CmdResponseError; - goto out; - } - - /*!< Send CMD33 SD_ERASE_GRP_END with argument as addr */ - SDH_CMD_Cfg_TypeInstance.index = SD_CMD_SD_ERASE_GRP_END; - SDH_CMD_Cfg_TypeInstance.argument = endaddr; - SDH_CMD_Cfg_TypeInstance.type = SDH_CMD_NORMAL; - SDH_CMD_Cfg_TypeInstance.respType = SDH_RESP_R1; - SDH_CMD_Cfg_TypeInstance.flag = SDH_TRANS_FLAG_NONE; - - errorstatus = SDH_SendCardCommand(&SDH_CMD_Cfg_TypeInstance); - - if (errorstatus != Status_Success) { - goto out; - } else if (SDH_CMD_Cfg_TypeInstance.response[0] & SD_CSR_ERRORBITS) { - errorstatus = Status_SDH_CmdResponseError; - goto out; - } - - /*!< Send CMD38 ERASE */ - SDH_CMD_Cfg_TypeInstance.index = SD_CMD_ERASE; - SDH_CMD_Cfg_TypeInstance.argument = 0; - SDH_CMD_Cfg_TypeInstance.type = SDH_CMD_NORMAL; - SDH_CMD_Cfg_TypeInstance.respType = SDH_RESP_R1B; - SDH_CMD_Cfg_TypeInstance.flag = SDH_TRANS_FLAG_NONE; - - errorstatus = SDH_SendCardCommand(&SDH_CMD_Cfg_TypeInstance); - - if (errorstatus != Status_Success) { - goto out; - } else if (SDH_CMD_Cfg_TypeInstance.response[0] & SD_CSR_ERRORBITS) { - errorstatus = Status_SDH_CmdResponseError; - goto out; - } - - /*!< Wait till the card is in programming state */ - errorstatus = IsCardProgramming(&cardstate); - - while ((errorstatus == SD_OK) && ((SD_CARD_PROGRAMMING == cardstate) || (SD_CARD_RECEIVING == cardstate))) { - errorstatus = IsCardProgramming(&cardstate); - } - -out: - return errorstatus; -} - -static status_t WaitInProgramming(void) -{ - uint8_t cardstate = 0; - status_t errorstatus = Status_Success; - //uint32_t maxdelay = 0; - //maxdelay = 120000/(sdhClockSrc/sdhClockTransfer); - - //while(maxdelay--){} - /*!< Wait till the card is in programming state */ - errorstatus = IsCardProgramming(&cardstate); - - while ((errorstatus == Status_Success) && ((SD_CARD_PROGRAMMING == cardstate) || (SD_CARD_RECEIVING == cardstate))) { - errorstatus = IsCardProgramming(&cardstate); - } - - return errorstatus; -} - -/*check sd card state*/ -static status_t IsCardProgramming(uint8_t *pstatus) -{ - status_t errorstatus = Status_Success; - SDH_CMD_Cfg_Type SDH_CMD_Cfg_TypeInstance; - - /*cmd13 addressed card send its status*/ - SDH_CMD_Cfg_TypeInstance.index = SD_CMD_SEND_STATUS; - SDH_CMD_Cfg_TypeInstance.argument = (uint32_t)(pSDCardInfo->relativeAddress) << 16; - SDH_CMD_Cfg_TypeInstance.type = SDH_CMD_NORMAL; - SDH_CMD_Cfg_TypeInstance.respType = SDH_RESP_R1; - SDH_CMD_Cfg_TypeInstance.flag = SDH_TRANS_FLAG_NONE; - - errorstatus = SDH_SendCardCommand(&SDH_CMD_Cfg_TypeInstance); - - if (errorstatus != Status_Success) { - goto out; - } else if (SDH_CMD_Cfg_TypeInstance.response[0] & SD_CSR_ERRORBITS) { - errorstatus = Status_SDH_CmdResponseError; - goto out; - } - - /*!< Find out card status */ - *pstatus = (uint8_t)((SDH_CMD_Cfg_TypeInstance.response[0] >> 9) & 0x0000000F); //status[12:9] :cardstate - -out: - return (errorstatus); -} - -/* Transmit data in non-blocking mode, Only the sending status of commands is checked */ -static status_t SDH_CardTransferNonBlocking(SDH_DMA_Cfg_Type *dmaCfg, SDH_Trans_Cfg_Type *transfer) -{ - status_t errorstatus = Status_Success; - SDH_Stat_Type stat = SDH_STAT_SUCCESS; - - stat = SDH_TransferNonBlocking(dmaCfg, transfer); - - if (stat != SDH_STAT_SUCCESS) { - return Status_SDH_TransferFailed; - } - - /* Flush ADMA2-descriptor-table to RAM, Otherwise ADMA2 will fail */ - L1C_DCache_Clean_By_Addr((uintptr_t)(dmaCfg->admaEntries), dmaCfg->maxEntries * sizeof(SDH_ADMA2_Desc_Type)); - - errorstatus = SDH_SendCardCommand(transfer->cmdCfg); - - if (errorstatus != Status_Success) { - return errorstatus; - } else if (transfer->cmdCfg->response[0] & SD_CSR_ERRORBITS) { - return Status_SDH_CmdResponseError; - } - - return errorstatus; -} - -status_t SDH_ReadMultiBlocks(uint8_t *readbuff, uint32_t ReadAddr, uint16_t BlockSize, uint32_t NumberOfBlocks) -{ - status_t errorstatus = Status_Success; - SD_Error sd_status; - uint32_t time_node; - - static SDH_CMD_Cfg_Type SDH_CMD_Cfg_TypeInstance; - static SDH_Data_Cfg_Type SDH_Data_Cfg_TypeInstance; - static SDH_Trans_Cfg_Type SDH_Trans_Cfg_TypeInstance = { &SDH_Data_Cfg_TypeInstance, &SDH_CMD_Cfg_TypeInstance }; - -#if defined(BL808) || defined(BL606P) - /* BL808/BL606 supports only 8-byte aligned addresses */ - if ((uintptr_t)readbuff % 8 != 0) { - return Status_InvalidArgument; - } -#endif - - /* SDSC card uses byte unit address*/ - if (!(pSDCardInfo->flags & SD_SupportHighCapacityFlag)) { - BlockSize = 512; - ReadAddr *= 512; - } - - SDH_MSG("\r\nRead-->IN, block num: %ld, block addr: %ld, read buffer addr: 0x%p.\r\n", NumberOfBlocks, ReadAddr, readbuff); - - /*set cmd parameter for READ_MULTIPLE_BLOCK*/ - if (NumberOfBlocks <= 1) { - SDH_CMD_Cfg_TypeInstance.index = SD_CMD_READ_SINGLE_BLOCK; - } else { - SDH_CMD_Cfg_TypeInstance.index = SD_CMD_READ_MULT_BLOCK; - } - - SDH_CMD_Cfg_TypeInstance.argument = (uint32_t)ReadAddr; - SDH_CMD_Cfg_TypeInstance.type = SDH_CMD_NORMAL; - SDH_CMD_Cfg_TypeInstance.respType = SDH_RESP_R1; - SDH_CMD_Cfg_TypeInstance.flag = SDH_TRANS_FLAG_DATA_PRESENT; - - /*set data parameter for READ_MULTIPLE_BLOCK*/ - if (NumberOfBlocks <= 1) { - SDH_Data_Cfg_TypeInstance.enableAutoCommand12 = DISABLE; - } else { - if (pSDCardInfo->flags & SD_SupportSetBlockCountCmd) { - SDH_Data_Cfg_TypeInstance.enableAutoCommand23 = ENABLE; - SDH_Data_Cfg_TypeInstance.enableAutoCommand12 = DISABLE; - } else { - SDH_Data_Cfg_TypeInstance.enableAutoCommand23 = DISABLE; - SDH_Data_Cfg_TypeInstance.enableAutoCommand12 = ENABLE; - } - } - - SDH_Data_Cfg_TypeInstance.enableIgnoreError = DISABLE; - SDH_Data_Cfg_TypeInstance.dataType = SDH_TRANS_DATA_NORMAL; - SDH_Data_Cfg_TypeInstance.blockSize = BlockSize; - SDH_Data_Cfg_TypeInstance.blockCount = NumberOfBlocks; - SDH_Data_Cfg_TypeInstance.rxDataLen = 0; - SDH_Data_Cfg_TypeInstance.rxData = (uint32_t *)readbuff; - SDH_Data_Cfg_TypeInstance.txDataLen = 0; - SDH_Data_Cfg_TypeInstance.txData = NULL; - SDH_Data_Cfg_TypeInstance.txDataLen = 0; - SDH_Data_Cfg_TypeInstance.txData = NULL; - - /*set parameters for SDH_DMA_Cfg_TypeInstance*/ - SDH_DMA_Cfg_TypeInstance.dmaMode = SDH_DMA_MODE_ADMA2; - SDH_DMA_Cfg_TypeInstance.burstSize = SDH_BURST_SIZE_64_BYTES; - SDH_DMA_Cfg_TypeInstance.fifoThreshold = SDH_FIFO_THRESHOLD_256_BYTES; - SDH_DMA_Cfg_TypeInstance.admaEntries = (uint32_t *)adma2Entries; - SDH_DMA_Cfg_TypeInstance.maxEntries = sizeof(adma2Entries) / sizeof(adma2Entries[0]); - - L1C_DCache_Clean_By_Addr((uintptr_t)(readbuff), 0); - L1C_DCache_Clean_By_Addr((uintptr_t)(readbuff) + BlockSize * NumberOfBlocks, 0); - L1C_DCache_Invalid_By_Addr((uintptr_t)(readbuff), BlockSize * NumberOfBlocks); - - errorstatus = SDH_CardTransferNonBlocking(&SDH_DMA_Cfg_TypeInstance, &SDH_Trans_Cfg_TypeInstance); - - if (errorstatus != Status_Success) { - SDH_MSG("SDH Transfer err:%ld\r\n", errorstatus); - goto out; - } - - time_node = (uint32_t)SDH_GET_TIME(); - -#if SDIO_SDCARD_INT_MODE - - SDH_DataWaitStatus = SD_WAITING; - SDH_EnableIntSource(SDH_INT_DATA_COMPLETED | SDH_INT_DATA_ERRORS | SDH_INT_DMA_ERROR | SDH_INT_AUTO_CMD12_ERROR); - - /*wait for Xfer status. might pending here in multi-task OS*/ - while (SDH_DataWaitStatus == SD_WAITING) { - if ((uint32_t)SDH_GET_TIME() - time_node > SDIO_CMDTIMEOUT_MS) { - SDH_MSG("SDH read data timeout: %ld", (uint32_t)SDH_GET_TIME() - time_node); - SDH_DisableIntSource(SDH_INT_DATA_COMPLETED | SDH_INT_DATA_ERRORS | SDH_INT_DMA_ERROR | SDH_INT_AUTO_CMD12_ERROR); - return Status_Timeout; - } - BL_DRV_DUMMY; - BL_DRV_DUMMY; - } - sd_status = SDH_DataWaitStatus; - SDH_DisableIntSource(SDH_INT_DATA_COMPLETED | SDH_INT_DATA_ERRORS | SDH_INT_DMA_ERROR | SDH_INT_AUTO_CMD12_ERROR); - -#else - - uint32_t intFlag; - while (1) { - intFlag = SDH_GetIntStatus(); - if (intFlag & SDH_INT_DATA_ERRORS || intFlag & SDH_INT_DMA_ERROR || intFlag & SDH_INT_AUTO_CMD12_ERROR) { - sd_status = SD_CMD_ERROR; - break; - - } else if (intFlag & SDH_INT_DATA_COMPLETED) { - sd_status = SD_OK; - break; - - } else if ((uint32_t)SDH_GET_TIME() - time_node > SDIO_CMDTIMEOUT_MS) { - SDH_MSG("SDH read data timeout: %ld ms\r\n", (uint32_t)SDH_GET_TIME() - time_node); - return Status_Timeout; - } - BL_DRV_DUMMY; - BL_DRV_DUMMY; - } - SDH_ClearIntStatus(intFlag); - -#endif - - if (sd_status != SD_OK) { - errorstatus = Status_SDH_TransferFailed; - goto out; - } - - SDH_MSG("Read data used time: %ld ms\r\n", (uint32_t)SDH_GET_TIME() - time_node); - SDH_MSG("Read-->OUT, block num: %ld, block addr: %ld, read buffer addr: 0x%p.\r\n", NumberOfBlocks, ReadAddr, readbuff); - -out: - return (errorstatus); -} - -status_t SDH_WriteMultiBlocks(uint8_t *writebuff, uint32_t WriteAddr, uint16_t BlockSize, uint32_t NumberOfBlocks) -{ - status_t errorstatus = Status_Success; - SD_Error sd_status; - uint32_t time_node; - - static SDH_CMD_Cfg_Type SDH_CMD_Cfg_TypeInstance; - static SDH_Data_Cfg_Type SDH_Data_Cfg_TypeInstance; - static SDH_Trans_Cfg_Type SDH_Trans_Cfg_TypeInstance = { &SDH_Data_Cfg_TypeInstance, &SDH_CMD_Cfg_TypeInstance }; - -#if defined(BL808) || defined(BL606P) - /* BL808/BL606 supports only 8-byte aligned addresses */ - if ((uintptr_t)writebuff % 8 != 0) { - return Status_InvalidArgument; - } -#endif - - if ((pSDCardInfo != NULL) && (!(pSDCardInfo->flags & SD_SupportHighCapacityFlag))) { - /* It's SDCS card,SDSC card uses byte unit address*/ - BlockSize = 512; - WriteAddr *= 512; - } - - SDH_MSG("\r\nWrite-->IN, block num: %ld, block addr: %ld, read buffer addr: 0x%p.\r\n", NumberOfBlocks, WriteAddr, writebuff); - - /*set cmd parameter for SD_CMD_WRITE_MULT_BLOCK*/ - if (NumberOfBlocks <= 1) { - SDH_CMD_Cfg_TypeInstance.index = SD_CMD_WRITE_SINGLE_BLOCK; - } else { - SDH_CMD_Cfg_TypeInstance.index = SD_CMD_WRITE_MULT_BLOCK; - } - - SDH_CMD_Cfg_TypeInstance.argument = (uint32_t)WriteAddr; - SDH_CMD_Cfg_TypeInstance.type = SDH_CMD_NORMAL; - SDH_CMD_Cfg_TypeInstance.respType = SDH_RESP_R1; - SDH_CMD_Cfg_TypeInstance.flag = SDH_TRANS_FLAG_DATA_PRESENT; - - /*set data parameter for WRITE_MULTIPLE_BLOCK*/ - if (NumberOfBlocks <= 1) { - SDH_Data_Cfg_TypeInstance.enableAutoCommand12 = DISABLE; - } else { - if (pSDCardInfo->flags & SD_SupportSetBlockCountCmd) { - SDH_Data_Cfg_TypeInstance.enableAutoCommand23 = ENABLE; - SDH_Data_Cfg_TypeInstance.enableAutoCommand12 = DISABLE; - } else { - SDH_Data_Cfg_TypeInstance.enableAutoCommand23 = DISABLE; - SDH_Data_Cfg_TypeInstance.enableAutoCommand12 = ENABLE; - } - } - - SDH_Data_Cfg_TypeInstance.enableIgnoreError = DISABLE; - SDH_Data_Cfg_TypeInstance.dataType = SDH_TRANS_DATA_NORMAL; - SDH_Data_Cfg_TypeInstance.blockSize = BlockSize; - SDH_Data_Cfg_TypeInstance.blockCount = NumberOfBlocks; - SDH_Data_Cfg_TypeInstance.rxDataLen = 0; - SDH_Data_Cfg_TypeInstance.rxData = NULL; - SDH_Data_Cfg_TypeInstance.txDataLen = 0; - SDH_Data_Cfg_TypeInstance.txData = (uint32_t *)writebuff; - /*set parameters for SDH_DMA_Cfg_TypeInstance*/ - SDH_DMA_Cfg_TypeInstance.dmaMode = SDH_DMA_MODE_ADMA2; - SDH_DMA_Cfg_TypeInstance.burstSize = SDH_BURST_SIZE_64_BYTES; - SDH_DMA_Cfg_TypeInstance.fifoThreshold = SDH_FIFO_THRESHOLD_256_BYTES; - SDH_DMA_Cfg_TypeInstance.admaEntries = (uint32_t *)adma2Entries; - SDH_DMA_Cfg_TypeInstance.maxEntries = sizeof(adma2Entries) / sizeof(adma2Entries[0]); - - L1C_DCache_Clean_By_Addr((uintptr_t)(writebuff), BlockSize * NumberOfBlocks); - - errorstatus = SDH_CardTransferNonBlocking(&SDH_DMA_Cfg_TypeInstance, &SDH_Trans_Cfg_TypeInstance); - - if (errorstatus != Status_Success) { - SDH_MSG("SDH Transfer err:%ld\r\n", errorstatus); - return errorstatus; - } - - time_node = (uint32_t)SDH_GET_TIME(); - -#if SDIO_SDCARD_INT_MODE - - SDH_DataWaitStatus = SD_WAITING; - SDH_EnableIntSource(SDH_INT_DATA_COMPLETED | SDH_INT_DATA_ERRORS | SDH_INT_DMA_ERROR | SDH_INT_AUTO_CMD12_ERROR); - - /*wait for Xfer status. might pending here in multi-task OS*/ - while (SDH_DataWaitStatus == SD_WAITING) { - if ((uint32_t)SDH_GET_TIME() - time_node > SDIO_CMDTIMEOUT_MS) { - SDH_MSG("SDH write data timeout: %ld ms\r\n", (uint32_t)SDH_GET_TIME() - time_node); - SDH_DisableIntSource(SDH_INT_DATA_COMPLETED | SDH_INT_DATA_ERRORS | SDH_INT_DMA_ERROR | SDH_INT_AUTO_CMD12_ERROR); - errorstatus = Status_Timeout; - goto out; - } - BL_DRV_DUMMY; - BL_DRV_DUMMY; - } - - SDH_DisableIntSource(SDH_INT_DATA_COMPLETED | SDH_INT_DATA_ERRORS | SDH_INT_DMA_ERROR | SDH_INT_AUTO_CMD12_ERROR); - sd_status = SDH_DataWaitStatus; - -#else - - uint32_t intFlag; - while (1) { - intFlag = SDH_GetIntStatus(); - if (intFlag & SDH_INT_DATA_ERRORS || intFlag & SDH_INT_DMA_ERROR || intFlag & SDH_INT_AUTO_CMD12_ERROR) { - sd_status = SD_DataCfg_ERROR; - break; - - } else if (intFlag & SDH_INT_DATA_COMPLETED) { - sd_status = SD_OK; - break; - - } else if ((uint32_t)SDH_GET_TIME() - time_node > SDIO_CMDTIMEOUT_MS) { - SDH_MSG("SDH write data timeout: %ld ms\r\n", (uint32_t)SDH_GET_TIME() - time_node); - return Status_Timeout; - } - BL_DRV_DUMMY; - BL_DRV_DUMMY; - } - SDH_ClearIntStatus(intFlag); - -#endif - - if (sd_status != SD_OK) { - errorstatus = Status_SDH_TransferFailed; - goto out; - } else { - errorstatus = WaitInProgramming(); - } - - SDH_MSG("Write data used time: %ld ms\r\n", (uint32_t)SDH_GET_TIME() - time_node); - SDH_MSG("Write-->OUT, block num: %ld, block addr: %ld, read buffer addr: 0x%p.\r\n", NumberOfBlocks, WriteAddr, writebuff); - -out: - return (errorstatus); -} - diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_sdh.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_sdh.h deleted file mode 100644 index ccb4772ea3..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_sdh.h +++ /dev/null @@ -1,516 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __SDIO_SDCARD_H -#define __SDIO_SDCARD_H -#include "bl808_common.h" -#include "bl808_glb.h" -#include "bl808_sdh.h" - -#define SDIO_CMDTIMEOUT_MS (100) /* time out */ -#define SDH_GET_TIME() (0) /* get time */ -#define SDIO_SDCARD_INT_MODE (0) /* Interrupt mode, which can be paired with the OS */ -#define SDH_DEBUG 0 /* debug printf */ - -/*! @brief Reverse byte sequence in uint32_t */ -#define SWAP_WORD_BYTE_SEQUENCE(x) (__REV(x)) -#define __OCRAM __attribute__ ((section (".system_ram"))) -#define __EALIGN(x) __attribute((aligned (x))) - -/*! @brief Default block size */ -#define SDH_DEFAULT_BLOCK_SIZE (512U) - -typedef enum { - SD_OK = 0, - SD_CMD_ERROR, - SD_DataCfg_ERROR, - SD_WAITING, -} SD_Error; - -/*! @brief Type used for all status and error return values. */ -typedef int32_t status_t; -/*! @brief Construct a status code value from a group and code number. */ -#define MAKE_STATUS(group, code) ((((group)*100) + (code))) - -/*! @brief Status group numbers. */ -enum _status_groups { - StatusGroup_Generic = 0, /*!< Group number for generic status codes. */ - StatusGroup_SDH = 1, /*!< Group number for SDHC status code */ -}; - -/*! @brief Generic status return codes. */ -enum _generic_status { - Status_Success = MAKE_STATUS(StatusGroup_Generic, 0), - Status_Fail = MAKE_STATUS(StatusGroup_Generic, 1), - Status_OutOfRange = MAKE_STATUS(StatusGroup_Generic, 2), - Status_InvalidArgument = MAKE_STATUS(StatusGroup_Generic, 3), - Status_Timeout = MAKE_STATUS(StatusGroup_Generic, 4), - -}; -/*! @brief SD/MMC card API's running status. */ -enum _sdmmc_status { - Status_SDH_NotSupportYet = MAKE_STATUS(StatusGroup_SDH, 0U), /*!< Haven't supported */ - Status_SDH_TransferFailed = MAKE_STATUS(StatusGroup_SDH, 1U), /*!< Send command failed */ - Status_SDH_SetCardBlockSizeFailed = MAKE_STATUS(StatusGroup_SDH, 2U), /*!< Set block size failed */ - Status_SDH_HostNotSupport = MAKE_STATUS(StatusGroup_SDH, 3U), /*!< Host doesn't support */ - Status_SDH_CardNotSupport = MAKE_STATUS(StatusGroup_SDH, 4U), /*!< Card doesn't support */ - Status_SDH_AllSendCidFailed = MAKE_STATUS(StatusGroup_SDH, 5U), /*!< Send CID failed */ - Status_SDH_SendRelativeAddressFailed = MAKE_STATUS(StatusGroup_SDH, 6U), /*!< Send relative address failed */ - Status_SDH_SendCsdFailed = MAKE_STATUS(StatusGroup_SDH, 7U), /*!< Send CSD failed */ - Status_SDH_SelectCardFailed = MAKE_STATUS(StatusGroup_SDH, 8U), /*!< Select card failed */ - Status_SDH_SendScrFailed = MAKE_STATUS(StatusGroup_SDH, 9U), /*!< Send SCR failed */ - Status_SDH_SetDataBusWidthFailed = MAKE_STATUS(StatusGroup_SDH, 10U), /*!< Set bus width failed */ - Status_SDH_GoIdleFailed = MAKE_STATUS(StatusGroup_SDH, 11U), /*!< Go idle failed */ - Status_SDH_HandShakeOperationConditionFailed = MAKE_STATUS(StatusGroup_SDH, 12U), /*!< Send Operation Condition failed */ - Status_SDH_SendApplicationCommandFailed = MAKE_STATUS(StatusGroup_SDH, 13U), /*!< Send application command failed */ - Status_SDH_SwitchFailed = MAKE_STATUS(StatusGroup_SDH, 14U), /*!< Switch command failed */ - Status_SDH_StopTransmissionFailed = MAKE_STATUS(StatusGroup_SDH, 15U), /*!< Stop transmission failed */ - Status_SDH_WaitWriteCompleteFailed = MAKE_STATUS(StatusGroup_SDH, 16U), /*!< Wait write complete failed */ - Status_SDH_SetBlockCountFailed = MAKE_STATUS(StatusGroup_SDH, 17U), /*!< Set block count failed */ - Status_SDH_SetRelativeAddressFailed = MAKE_STATUS(StatusGroup_SDH, 18U), /*!< Set relative address failed */ - Status_SDH_SwitchBusTimingFailed = MAKE_STATUS(StatusGroup_SDH, 19U), /*!< Switch high speed failed */ - Status_SDH_SendExtendedCsdFailed = MAKE_STATUS(StatusGroup_SDH, 20U), /*!< Send EXT_CSD failed */ - Status_SDH_ConfigureBootFailed = MAKE_STATUS(StatusGroup_SDH, 21U), /*!< Configure boot failed */ - Status_SDH_ConfigureExtendedCsdFailed = MAKE_STATUS(StatusGroup_SDH, 22U), /*!< Configure EXT_CSD failed */ - Status_SDH_EnableHighCapacityEraseFailed = MAKE_STATUS(StatusGroup_SDH, 23U), /*!< Enable high capacity erase failed */ - Status_SDH_SendTestPatternFailed = MAKE_STATUS(StatusGroup_SDH, 24U), /*!< Send test pattern failed */ - Status_SDH_ReceiveTestPatternFailed = MAKE_STATUS(StatusGroup_SDH, 25U), /*!< Receive test pattern failed */ - Status_SDH_SDIO_ResponseError = MAKE_STATUS(StatusGroup_SDH, 26U), /*!< sdio response error */ - Status_SDH_SDIO_InvalidArgument = MAKE_STATUS(StatusGroup_SDH, 27U), /*!< sdio invalid argument response error */ - Status_SDH_SDIO_SendOperationConditionFail = MAKE_STATUS(StatusGroup_SDH, 28U), /*!< sdio send operation condition fail */ - Status_SDH_InvalidVoltage = MAKE_STATUS(StatusGroup_SDH, 29U), /*!< invaild voltage */ - Status_SDH_SDIO_SwitchHighSpeedFail = MAKE_STATUS(StatusGroup_SDH, 30U), /*!< switch to high speed fail */ - Status_SDH_SDIO_ReadCISFail = MAKE_STATUS(StatusGroup_SDH, 31U), /*!< read CIS fail */ - Status_SDH_SDIO_InvalidCard = MAKE_STATUS(StatusGroup_SDH, 32U), /*!< invaild SDIO card */ - Status_SDH_TuningFail = MAKE_STATUS(StatusGroup_SDH, 33U), /*!< tuning fail */ - Status_SDH_SwitchVoltageFail = MAKE_STATUS(StatusGroup_SDH, 34U), /*!< switch voltage fail*/ - Status_SDH_ReTuningRequest = MAKE_STATUS(StatusGroup_SDH, 35U), /*!< retuning request */ - Status_SDH_SetDriverStrengthFail = MAKE_STATUS(StatusGroup_SDH, 36U), /*!< set driver strength fail */ - Status_SDH_SetPowerClassFail = MAKE_STATUS(StatusGroup_SDH, 37U), /*!< set power class fail */ - Status_SDH_HostNotReady = MAKE_STATUS(StatusGroup_SDH, 38U), /*!< host controller not ready */ - Status_SDH_CardDetectFailed = MAKE_STATUS(StatusGroup_SDH, 39U), /*!< card detect failed */ - Status_SDH_CmdResponseError = MAKE_STATUS(StatusGroup_SDH, 40U), /*!< cmd response timeout */ - Status_SDH_SendSsrFailed = MAKE_STATUS(StatusGroup_SDH, 41U), /*!< Send SSR failed */ -}; -/** - * @brief SDIO Transfer state - */ -typedef enum { - SD_TRANSFER_OK = 0, - SD_TRANSFER_BUSY = 1, - SD_TRANSFER_ERROR -} SDTransferState; - -/** - * @brief SD Card States - */ -typedef enum { - SD_CARD_READY = ((uint32_t)0x00000001), - SD_CARD_IDENTIFICATION = ((uint32_t)0x00000002), - SD_CARD_STANDBY = ((uint32_t)0x00000003), - SD_CARD_TRANSFER = ((uint32_t)0x00000004), - SD_CARD_SENDING = ((uint32_t)0x00000005), - SD_CARD_RECEIVING = ((uint32_t)0x00000006), - SD_CARD_PROGRAMMING = ((uint32_t)0x00000007), - SD_CARD_DISCONNECTED = ((uint32_t)0x00000008), - SD_CARD_ERROR = ((uint32_t)0x000000FF) -} SDCardState; - -/** - * @brief Card Specific Data: CSD Register - */ -typedef struct -{ - uint8_t CSDStruct; /*!< CSD structure */ - uint8_t SysSpecVersion; /*!< System specification version */ - uint8_t Reserved1; /*!< Reserved */ - uint8_t TAAC; /*!< Data read access-time 1 */ - uint8_t NSAC; /*!< Data read access-time 2 in CLK cycles */ - uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */ - uint16_t CardComdClasses; /*!< Card command classes */ - uint8_t RdBlockLen; /*!< Max. read data block length */ - uint8_t PartBlockRead; /*!< Partial blocks for read allowed */ - uint8_t WrBlockMisalign; /*!< Write block misalignment */ - uint8_t RdBlockMisalign; /*!< Read block misalignment */ - uint8_t DSRImpl; /*!< DSR implemented */ - uint8_t Reserved2; /*!< Reserved */ - uint32_t DeviceSize; /*!< Device Size */ - uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */ - uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */ - uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */ - uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */ - uint8_t DeviceSizeMul; /*!< Device size multiplier */ - uint8_t EraseGrSize; /*!< Erase group size */ - uint8_t EraseGrMul; /*!< Erase group size multiplier */ - uint8_t WrProtectGrSize; /*!< Write protect group size */ - uint8_t WrProtectGrEnable; /*!< Write protect group enable */ - uint8_t ManDeflECC; /*!< Manufacturer default ECC */ - uint8_t WrSpeedFact; /*!< Write speed factor */ - uint8_t MaxWrBlockLen; /*!< Max. write data block length */ - uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */ - uint8_t Reserved3; /*!< Reserded */ - uint8_t ContentProtectAppli; /*!< Content protection application */ - uint8_t FileFormatGrouop; /*!< File format group */ - uint8_t CopyFlag; /*!< Copy flag (OTP) */ - uint8_t PermWrProtect; /*!< Permanent write protection */ - uint8_t TempWrProtect; /*!< Temporary write protection */ - uint8_t FileFormat; /*!< File Format */ - uint8_t ECC; /*!< ECC code */ -} SD_CSD; - -/** - * @brief Card Identification Data: CID Register - */ -typedef struct -{ - uint8_t ManufacturerID; /*!< ManufacturerID */ - uint8_t OEM_AppliID[3]; /*!< OEM/Application ID end with 0 for str display*/ - uint8_t ProdName[6]; /*!< Product Name part1 end with 0 for str display*/ - uint8_t ProdRev; /*!< Product Revision */ - uint32_t ProdSN; /*!< Product Serial Number */ - uint8_t month; /*!< Reserved1 */ - uint32_t year; /*!< Manufacturing Date */ -} SD_CID; - -/** - * @brief SD Card Status - */ -typedef struct -{ - uint8_t DAT_BUS_WIDTH; - uint8_t SECURED_MODE; - uint16_t SD_CARD_TYPE; - uint32_t SIZE_OF_PROTECTED_AREA; - uint8_t SPEED_CLASS; - uint8_t PERFORMANCE_MOVE; - uint8_t AU_SIZE; - uint16_t ERASE_SIZE; - uint8_t ERASE_TIMEOUT; - uint8_t ERASE_OFFSET; -} SD_CardStatus; - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! @brief OCR register in SD card */ -enum _sd_ocr_flag { - - SD_OcrHostCapacitySupportFlag = (1U << 30U), /*!< Card capacity status */ - SD_OcrCardCapacitySupportFlag = SD_OcrHostCapacitySupportFlag, /*!< Card capacity status */ - SD_OcrSwitch18RequestFlag = (1U << 24U), /*!< Switch to 1.8V request */ - SD_OcrSwitch18AcceptFlag = SD_OcrSwitch18RequestFlag, /*!< Switch to 1.8V accepted */ - SD_OcrVdd27_28Flag = (1U << 15U), /*!< VDD 2.7-2.8 */ - SD_OcrVdd28_29Flag = (1U << 16U), /*!< VDD 2.8-2.9 */ - SD_OcrVdd29_30Flag = (1U << 17U), /*!< VDD 2.9-3.0 */ - SD_OcrVdd30_31Flag = (1U << 18U), /*!< VDD 2.9-3.0 */ - SD_OcrVdd31_32Flag = (1U << 19U), /*!< VDD 3.0-3.1 */ - SD_OcrVdd32_33Flag = (1U << 20U), /*!< VDD 3.1-3.2 */ - SD_OcrVdd33_34Flag = (1U << 21U), /*!< VDD 3.2-3.3 */ - SD_OcrVdd34_35Flag = (1U << 22U), /*!< VDD 3.3-3.4 */ - SD_OcrVdd35_36Flag = (1U << 23U), /*!< VDD 3.4-3.5 */ -}; -/*! @brief SD card flags */ -enum _sd_card_flag { - SD_SupportHighCapacityFlag = (1U << 1U), /*!< Support high capacity */ - SD_Support4BitWidthFlag = (1U << 2U), /*!< Support 4-bit data width */ - SD_SupportSdhcFlag = (1U << 3U), /*!< Card is SDHC */ - SD_SupportSdxcFlag = (1U << 4U), /*!< Card is SDXC */ - SD_SupportVoltage180v = (1U << 5U), /*!< card support 1.8v voltage*/ - SD_SupportSetBlockCountCmd = (1U << 6U), /*!< card support cmd23 flag*/ - SD_SupportSpeedClassControlCmd = (1U << 7U), /*!< card support speed class control flag */ -}; -/*! @brief SD card CID register */ -typedef struct _sd_cid { - uint8_t manufacturerID; /*!< Manufacturer ID [127:120] */ - uint16_t applicationID; /*!< OEM/Application ID [119:104] */ - uint8_t productName[5]; /*!< Product name [103:64] */ - uint8_t productVersion; /*!< Product revision [63:56] */ - uint32_t productSerialNumber; /*!< Product serial number [55:24] */ - uint16_t manufacturerData; /*!< Manufacturing date [19:8] */ -} sd_cid_t; - -/*! @brief SD card SCR register flags */ -enum _sd_scr_flag { - SD_ScrDataStatusAfterErase = (1U << 0U), /*!< Data status after erases [55:55] */ - SD_ScrSdSpecification3 = (1U << 1U), /*!< Specification version 3.00 or higher [47:47]*/ -}; -/*! @brief SD card CSD register */ -typedef struct _sd_csd { - uint8_t csdStructure; /*!< CSD structure [127:126] */ - uint8_t dataReadAccessTime1; /*!< Data read access-time-1 [119:112] */ - uint8_t dataReadAccessTime2; /*!< Data read access-time-2 in clock cycles (NSAC*100) [111:104] */ - uint8_t transferSpeed; /*!< Maximum data transfer rate [103:96] */ - uint16_t cardCommandClass; /*!< Card command classes [95:84] */ - uint8_t readBlockLength; /*!< Maximum read data block length [83:80] */ - uint16_t flags; /*!< Flags in _sd_csd_flag */ - uint32_t deviceSize; /*!< Device size [73:62] */ - /* Following fields from 'readCurrentVddMin' to 'deviceSizeMultiplier' exist in CSD version 1 */ - uint8_t readCurrentVddMin; /*!< Maximum read current at VDD min [61:59] */ - uint8_t readCurrentVddMax; /*!< Maximum read current at VDD max [58:56] */ - uint8_t writeCurrentVddMin; /*!< Maximum write current at VDD min [55:53] */ - uint8_t writeCurrentVddMax; /*!< Maximum write current at VDD max [52:50] */ - uint8_t deviceSizeMultiplier; /*!< Device size multiplier [49:47] */ - - uint8_t eraseSectorSize; /*!< Erase sector size [45:39] */ - uint8_t writeProtectGroupSize; /*!< Write protect group size [38:32] */ - uint8_t writeSpeedFactor; /*!< Write speed factor [28:26] */ - uint8_t writeBlockLength; /*!< Maximum write data block length [25:22] */ - uint8_t fileFormat; /*!< File format [11:10] */ -} sd_csd_t; -/*! @brief SD card SCR register */ -typedef struct _sd_scr { - uint8_t scrStructure; /*!< SCR Structure [63:60] */ - uint8_t sdSpecification; /*!< SD memory card specification version [59:56] */ - uint16_t flags; /*!< SCR flags in _sd_scr_flag */ - uint8_t sdSecurity; /*!< Security specification supported [54:52] */ - uint8_t sdBusWidths; /*!< Data bus widths supported [51:48] */ - uint8_t extendedSecurity; /*!< Extended security support [46:43] */ - uint8_t commandSupport; /*!< Command support bits [33:32] 33-support CMD23, 32-support cmd20*/ - uint32_t reservedForManufacturer; /*!< reserved for manufacturer usage [31:0] */ -} sd_scr_t; -/*! @brief SD Status register */ -typedef struct _sd_ssr { - uint8_t dataBusWidth; /*!< Data Bus Width [511:510] 0b00--1line, 0b10--4line*/ - uint8_t secureMode; /*!< Secure Mode [509] */ - uint16_t SDCardType; /*!< SD Card Type [495:480] */ - uint32_t sizeOfProtectedArea; /*!< Size Of Protected area [479:448] */ - uint8_t speedClass; /*!< speed classes [447:440] */ - uint8_t performanceMove; /*!< performance move [439:432] */ - uint8_t AUSize; /*!< AU size [431:428] */ - - uint16_t eraseSize; /*!< erase size [423:408] */ - uint8_t eraseTimeOut; /*!< erase timeout [407:402] */ - uint8_t eraseOffset; /*!< erase offset [401:400] */ - uint8_t UHSSpeedGrade; /*!< UHS speed grade [399:396] */ - uint8_t UHSAUSize; /*!< UHS AU size [395:392] */ -} sd_ssr_t; -/*! - * @brief SD card state - * - * Define the card structure including the necessary fields to identify and describe the card. - */ -typedef struct _sd_card { - uint32_t relativeAddress; /*!< Relative address of the card */ - uint32_t version; /*!< Card version */ - uint32_t flags; /*!< Flags in _sd_card_flag */ - uint32_t rawCid[4U]; /*!< Raw CID content */ - uint32_t rawCsd[4U]; /*!< Raw CSD content */ - uint32_t rawScr[2U]; /*!< Raw CSD content */ - uint32_t rawSsr[16U]; /*!< Raw CSD content */ - uint32_t ocr; /*!< Raw OCR content */ - sd_cid_t cid; /*!< CID */ - sd_csd_t csd; /*!< CSD */ - sd_scr_t scr; /*!< SCR */ - sd_ssr_t ssr; /*!< SCR */ - uint32_t blockCount; /*!< Card total block number */ - uint32_t blockSize; /*!< Card block size */ -} sd_card_t; -/** - * @brief SDIO Commands Index - */ -#define SD_CMD_GO_IDLE_STATE ((uint8_t)0) -#define SD_CMD_SEND_OP_COND ((uint8_t)1) -#define SD_CMD_ALL_SEND_CID ((uint8_t)2) -#define SD_CMD_SET_REL_ADDR ((uint8_t)3) /*!< SDIO_SEND_REL_ADDR for SD Card */ -#define SD_CMD_SET_DSR ((uint8_t)4) -#define SD_CMD_SDIO_SEN_OP_COND ((uint8_t)5) -#define SD_CMD_HS_SWITCH ((uint8_t)6) -#define SD_CMD_SEL_DESEL_CARD ((uint8_t)7) -#define SD_CMD_HS_SEND_EXT_CSD ((uint8_t)8) -#define SDIO_SEND_IF_COND ((uint8_t)8) -#define SD_CMD_SEND_CSD ((uint8_t)9) -#define SD_CMD_SEND_CID ((uint8_t)10) -#define SD_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11) /*!< SD Card doesn't support it */ -#define SD_CMD_STOP_TRANSMISSION ((uint8_t)12) -#define SD_CMD_SEND_STATUS ((uint8_t)13) -#define SD_CMD_HS_BUSTEST_READ ((uint8_t)14) -#define SD_CMD_GO_INACTIVE_STATE ((uint8_t)15) -#define SD_CMD_SET_BLOCKLEN ((uint8_t)16) -#define SD_CMD_READ_SINGLE_BLOCK ((uint8_t)17) -#define SD_CMD_READ_MULT_BLOCK ((uint8_t)18) -#define SD_CMD_HS_BUSTEST_WRITE ((uint8_t)19) -#define SD_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20) /*!< SD Card doesn't support it */ -#define SD_CMD_SET_BLOCK_COUNT ((uint8_t)23) /*!< SD Card doesn't support it */ -#define SD_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24) -#define SD_CMD_WRITE_MULT_BLOCK ((uint8_t)25) -#define SD_CMD_PROG_CID ((uint8_t)26) /*!< reserved for manufacturers */ -#define SD_CMD_PROG_CSD ((uint8_t)27) -#define SD_CMD_SET_WRITE_PROT ((uint8_t)28) -#define SD_CMD_CLR_WRITE_PROT ((uint8_t)29) -#define SD_CMD_SEND_WRITE_PROT ((uint8_t)30) -#define SD_CMD_SD_ERASE_GRP_START ((uint8_t)32) /*!< To set the address of the first write - block to be erased. (For SD card only) */ -#define SD_CMD_SD_ERASE_GRP_END ((uint8_t)33) /*!< To set the address of the last write block of the - continuous range to be erased. (For SD card only) */ -#define SD_CMD_ERASE_GRP_START ((uint8_t)35) /*!< To set the address of the first write block to be erased. - (For MMC card only spec 3.31) */ - -#define SD_CMD_ERASE_GRP_END ((uint8_t)36) /*!< To set the address of the last write block of the - continuous range to be erased. (For MMC card only spec 3.31) */ - -#define SD_CMD_ERASE ((uint8_t)38) -#define SD_CMD_FAST_IO ((uint8_t)39) /*!< SD Card doesn't support it */ -#define SD_CMD_GO_IRQ_STATE ((uint8_t)40) /*!< SD Card doesn't support it */ -#define SD_CMD_LOCK_UNLOCK ((uint8_t)42) -#define SD_CMD_APP_CMD ((uint8_t)55) -#define SD_CMD_GEN_CMD ((uint8_t)56) -#define SD_CMD_NO_CMD ((uint8_t)64) - -/** - * @brief Following commands are SD Card Specific commands. - * SDIO_APP_CMD :CMD55 should be sent before sending these commands. - */ -#define SD_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) /*!< For SD Card only */ -#define SD_CMD_SD_APP_STAUS ((uint8_t)13) /*!< For SD Card only */ -#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) /*!< For SD Card only */ -#define SD_CMD_SD_APP_OP_COND ((uint8_t)41) /*!< For SD Card only */ -#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42) /*!< For SD Card only */ -#define SD_CMD_SD_APP_SEND_SCR ((uint8_t)51) /*!< For SD Card only */ -#define SD_CMD_SDIO_RW_DIRECT ((uint8_t)52) /*!< For SD I/O Card only */ -#define SD_CMD_SDIO_RW_EXTENDED ((uint8_t)53) /*!< For SD I/O Card only */ - -/** - * @brief Following commands are SD Card Specific security commands. - * SDIO_APP_CMD should be sent before sending these commands. - */ -#define SD_CMD_SD_APP_GET_MKB ((uint8_t)43) /*!< For SD Card only */ -#define SD_CMD_SD_APP_GET_MID ((uint8_t)44) /*!< For SD Card only */ -#define SD_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45) /*!< For SD Card only */ -#define SD_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46) /*!< For SD Card only */ -#define SD_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47) /*!< For SD Card only */ -#define SD_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48) /*!< For SD Card only */ -#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18) /*!< For SD Card only */ -#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25) /*!< For SD Card only */ -#define SD_CMD_SD_APP_SECURE_ERASE ((uint8_t)38) /*!< For SD Card only */ -#define SD_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49) /*!< For SD Card only */ -#define SD_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48) /*!< For SD Card only */ - -/** - * @brief Mask for errors Card Status R1 (CSR Register) - */ -#define SD_CSR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000) -#define SD_CSR_ADDR_MISALIGNED ((uint32_t)0x40000000) -#define SD_CSR_BLOCK_LEN_ERR ((uint32_t)0x20000000) -#define SD_CSR_ERASE_SEQ_ERR ((uint32_t)0x10000000) -#define SD_CSR_BAD_ERASE_PARAM ((uint32_t)0x08000000) -#define SD_CSR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000) -#define SD_CSR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000) -#define SD_CSR_COM_CRC_FAILED ((uint32_t)0x00800000) -#define SD_CSR_ILLEGAL_CMD ((uint32_t)0x00400000) -#define SD_CSR_CARD_ECC_FAILED ((uint32_t)0x00200000) -#define SD_CSR_CC_ERROR ((uint32_t)0x00100000) -#define SD_CSR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000) -#define SD_CSR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000) -#define SD_CSR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000) -#define SD_CSR_CID_CSD_OVERWRIETE ((uint32_t)0x00010000) -#define SD_CSR_WP_ERASE_SKIP ((uint32_t)0x00008000) -#define SD_CSR_CARD_ECC_DISABLED ((uint32_t)0x00004000) -#define SD_CSR_ERASE_RESET ((uint32_t)0x00002000) -#define SD_CSR_AKE_SEQ_ERROR ((uint32_t)0x00000008) -#define SD_CSR_ERRORBITS ((uint32_t)0xFDFFE008) - -#define SD_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFF) -#define SD_ALLZERO ((uint32_t)0x00000000) - -#define SD_WIDE_BUS_SUPPORT ((uint32_t)0x00040000) -#define SD_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000) -#define SD_CARD_LOCKED ((uint32_t)0x02000000) - -#define SD_0TO7BITS ((uint32_t)0x000000FF) -#define SD_8TO15BITS ((uint32_t)0x0000FF00) -#define SD_16TO23BITS ((uint32_t)0x00FF0000) -#define SD_24TO31BITS ((uint32_t)0xFF000000) -#define SD_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFF) -/** - * @brief Masks for R7 Response - */ -#define SD_VOLTAGE_WINDOW_SD ((uint32_t)0x00100000) -#define SD_HIGH_CAPACITY ((uint32_t)0x40000000) -#define SD_STD_CAPACITY ((uint32_t)0x00000000) -#define SD_CHECK_PATTERN ((uint32_t)0x000001AA) - -/** - * @brief Supported SD Memory Cards - */ -#define SDIO_STD_CAPACITY_SD_CARD_V1_1 ((uint32_t)0x00000000) -#define SDIO_STD_CAPACITY_SD_CARD_V2_0 ((uint32_t)0x00000001) -#define SDIO_HIGH_CAPACITY_SD_CARD ((uint32_t)0x00000002) -#define SDIO_MULTIMEDIA_CARD ((uint32_t)0x00000003) -#define SDIO_SECURE_DIGITAL_IO_CARD ((uint32_t)0x00000004) -#define SDIO_HIGH_SPEED_MULTIMEDIA_CARD ((uint32_t)0x00000005) -#define SDIO_SECURE_DIGITAL_IO_COMBO_CARD ((uint32_t)0x00000006) -#define SDIO_HIGH_CAPACITY_MMC_CARD ((uint32_t)0x00000007) - -/*! @brief SD group number */ -typedef enum _sd_group_num { - SDH_GroupTimingMode = 0U, /*!< acess mode group*/ - SDH_GroupCommandSystem = 1U, /*!< command system group*/ - SDH_GroupDriverStrength = 2U, /*!< driver strength group*/ - SDH_GroupCurrentLimit = 3U, /*!< current limit group*/ -} sd_group_num; - -/*! @brief SD card timing mode flags */ -typedef enum _sd_timing_mode { - SDH_TimingSDR12DefaultMode = 0U, /*!< Identification mode & SDR12 */ - SDH_TimingSDR25HighSpeedMode = 1U, /*!< High speed mode & SDR25 */ - SDH_TimingSDR50Mode = 2U, /*!< SDR50 mode*/ - SDH_TimingSDR104Mode = 3U, /*!< SDR104 mode */ - SDH_TimingDDR50Mode = 4U, /*!< DDR50 mode */ -} sd_timing_mode_t; - -/*! @brief SD card specification version number */ -enum _sd_specification_version { - SD_SpecificationVersion1_0 = (1U << 0U), /*!< SD card version 1.0-1.01 */ - SD_SpecificationVersion1_1 = (1U << 1U), /*!< SD card version 1.10 */ - SD_SpecificationVersion2_0 = (1U << 2U), /*!< SD card version 2.00 */ - SD_SpecificationVersion3_0 = (1U << 3U), /*!< SD card version 3.0 */ -}; - -/*! @brief SD card switch mode */ -typedef enum _sd_switch_mode { - SDH_SwitchCheck = 0U, /*!< SD switch mode 0: check function */ - SDH_SwitchSet = 1U, /*!< SD switch mode 1: set function */ -} sd_switch_mode_t; - - -#if SDH_DEBUG -#define SDH_MSG(a, ...) printf(a, ##__VA_ARGS__) -#else -#define SDH_MSG(a, ...) -#endif - -/* -bus_wide shoud be SDH_DATA_BUS_WIDTH_1BIT/SDH_DATA_BUS_WIDTH_4BITS/SDH_DATA_BUS_WIDTH_8BITS -*/ -status_t SDH_ClockSet(uint32_t clockInit, uint32_t clockSrc, uint32_t clockTransfer); -status_t SDH_Init(uint32_t bus_wide, sd_card_t *pOutCardInfo); -status_t SD_Erase(uint32_t startaddr, uint32_t endaddr); -status_t SDH_ReadMultiBlocks(uint8_t *readbuff, uint32_t ReadAddr, uint16_t BlockSize, uint32_t NumberOfBlocks); -status_t SDH_WriteMultiBlocks(uint8_t *writebuff, uint32_t WriteAddr, uint16_t BlockSize, uint32_t NumberOfBlocks); -#endif /* __SDCARD_H */ diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_sec.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_sec.c deleted file mode 100644 index 3a9d62d8ca..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_sec.c +++ /dev/null @@ -1,797 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include - -#include -//FIXME no BL808/BL606p header file including is Allowed here -#ifdef BL808 -#include -#elif defined(BL606P) -#include -#else -#error "Use CHIP BL808/BL606P for this module" -#endif - -#include - -#include "bl_sec.h" -#include "bl_irq.h" - -#include - -#define xstr(a) str_macro(a) -#define str_macro(a) #a -#define TRNG_LOOP_COUNTER (17) - -#define TRNG_SIZE_IN_WORD (8) -#define TRNG_SIZE_IN_BYTES (32) -static uint32_t trng_buffer[TRNG_SIZE_IN_WORD]; -static unsigned int trng_idx = 0; - -static StaticSemaphore_t sha_mutex_buf; -SemaphoreHandle_t g_bl_sec_sha_mutex = NULL; - -static inline void _trng_trigger() -{ - uint32_t TRNGx = SEC_ENG_BASE; - uint32_t val; - - val = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0); - if (BL_IS_REG_BIT_SET(val, SEC_ENG_SE_TRNG_0_BUSY)) { - return; - } - BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_1, trng_buffer[0]); - BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_2, trng_buffer[1]); - val = BL_SET_REG_BIT(val, SEC_ENG_SE_TRNG_0_INT_SET_1T); - val = BL_SET_REG_BIT(val, SEC_ENG_SE_TRNG_0_INT_CLR_1T); - val = BL_SET_REG_BIT(val, SEC_ENG_SE_TRNG_0_EN); - val = BL_SET_REG_BIT(val, SEC_ENG_SE_TRNG_0_TRIG_1T); - - BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0, val); -} - -static inline void wait_trng4feed() -{ - uint32_t TRNGx = SEC_ENG_BASE; - uint32_t val; - - val = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0); - - while (BL_IS_REG_BIT_SET(val, SEC_ENG_SE_TRNG_0_BUSY)) { - /*wait until trng is NOT busy*/ - val = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0); - } - - val = BL_SET_REG_BIT(val, SEC_ENG_SE_TRNG_0_INT_CLR_1T); - val = BL_CLR_REG_BIT(val, SEC_ENG_SE_TRNG_0_TRIG_1T); - BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0, val); - - blog_debug("Feed random number is %08lx\r\n", trng_buffer[0]); - trng_buffer[0] = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_0); - trng_buffer[1] = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_1); - trng_buffer[2] = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_2); - trng_buffer[3] = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_3); - trng_buffer[4] = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_4); - trng_buffer[5] = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_5); - trng_buffer[6] = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_6); - trng_buffer[7] = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_7); -} - -uint32_t bl_sec_get_random_word(void) -{ - trng_idx = (trng_idx & 0x7); - if (0 == trng_idx) { - _trng_trigger(); - } - return trng_buffer[trng_idx++]; -} - -void bl_rand_stream(uint8_t *buf, int len) -{ - // int pos, copysize; - - // pos = 0; - // if (trng_idx) { - // /*reset trng_buffer*/ - // _trng_trigger(); - // wait_trng4feed(); - // trng_idx = 0; - // } - - // while (len > 0) { - // if (trng_idx) { - // /*reset trng_buffer*/ - // _trng_trigger(); - // wait_trng4feed(); - // trng_idx = 0; - // } - // copysize = len > TRNG_SIZE_IN_BYTES ? TRNG_SIZE_IN_BYTES : len; - // memcpy(buf + pos, trng_buffer, copysize); - // pos += copysize; - // len -= copysize; - // trng_idx = TRNG_SIZE_IN_BYTES - 1; - // } - // _trng_trigger(); - // wait_trng4feed(); - // trng_idx = 0; - int i; - - for (i = 0; i < len; i++) { - buf[i] = (uint8_t)bl_rand(); - } -} - -int bl_rand() -{ - // unsigned int val; - // int counter = 0; - - // do { - // val = bl_sec_get_random_word(); - // if ((counter++) > TRNG_LOOP_COUNTER) { - // puts("[BL] [SEC] Failed after loop " xstr(TRNG_LOOP_COUNTER) "\r\n"); - // break; - // } - // } while (0 == val); - // val >>= 1;//leave signe bit alone - return rand(); -} - -void sec_trng_IRQHandler(void) -{ - uint32_t TRNGx = SEC_ENG_BASE; - uint32_t val; - - if (aos_now_ms() < 1000 * 2) { - /*debug when boot*/ - puts("[BL] [SEC] TRNG Handler\r\n"); - } - val = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0); - val = BL_SET_REG_BIT(val, SEC_ENG_SE_TRNG_0_INT_CLR_1T); - val = BL_CLR_REG_BIT(val, SEC_ENG_SE_TRNG_0_TRIG_1T); - BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0, val); - - blog_debug("random number is %08lx\r\n", trng_buffer[0]); - trng_buffer[0] = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_0); - trng_buffer[1] = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_1); - trng_buffer[2] = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_2); - trng_buffer[3] = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_3); - trng_buffer[4] = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_4); - trng_buffer[5] = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_5); - trng_buffer[6] = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_6); - trng_buffer[7] = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_7); -} - -int bl_sec_init(void) -{ - if (g_bl_sec_sha_mutex) { - return 0; - } - g_bl_sec_sha_mutex = xSemaphoreCreateMutexStatic(&sha_mutex_buf); -#if 0 - _trng_trigger(); - wait_trng4feed(); - /*Trigger again*/ - _trng_trigger(); - wait_trng4feed(); - bl_irq_register(SEC_TRNG_IRQn, sec_trng_IRQHandler); - bl_irq_enable(SEC_TRNG_IRQn); -#endif - - return 0; -} - -int bl_exp_mod(uint32_t *src, uint32_t *result, int len, uint32_t *exp, int exp_len, uint32_t *mod, int mod_len) -{ - return 0; -} - -int bl_sec_test(void) -{ - blog_print("------------------TRNG TEST---------------------------------\r\n"); - blog_print("**********TRNG TEST rand[%08x]**************\r\n", bl_rand()); - blog_print("**********TRNG TEST rand[%08x]**************\r\n", bl_rand()); - blog_print("------------------------------------------------------------\r\n"); - - return 0; -} - -void _dump_rsa_data(const uint8_t *data, int size) -{ - int i; - - for (i = 0; i < size; i++) { - switch (i & 0xF) { - case 0x0: - { - blog_print("[%04X]:", i); - blog_print(" %02X", data[i]); - } - break; - case 0xF: - { - blog_print(" %02X", data[i]); - puts("\r\n"); - } - break; - default: - { - blog_print(" %02X", data[i]); - } - } - } -} - -static void RSA_Compare_Data(const uint8_t *expected, const uint8_t *input, uint32_t len) -{ - int i = 0, is_failed = 0; - - for (i = 0; i < len; i++) { - if (input[i] != expected[i]) { - is_failed = 1; - blog_info("%s[%02d], %02x %02x\r\n", - input[i] ==expected[i] ? "S" : "F", - i, - input[i], - expected[i] - ); - } - } - if (is_failed) { - blog_error("====== Failed %lu Bytes======\r\n", len); - } else { - blog_info("====== Success %lu Bytes=====\r\n", len); - } -} - -static void _pka_test_case2(void) -{ - static const uint8_t n[256] = { - 0xd8, 0xa6, 0x4f, 0xea, 0x28, 0xf9, 0xdf, 0x07, 0x04, 0x55, 0xfa, 0xfb, 0x50, 0x5d, 0xbe, 0xb6, - 0x9f, 0x7b, 0x53, 0x96, 0xef, 0x05, 0x5e, 0x0a, 0xf5, 0x2d, 0xe3, 0x67, 0x78, 0x07, 0x6b, 0xf6, - 0xb2, 0x17, 0xac, 0x2e, 0x51, 0x42, 0x84, 0xbb, 0xfe, 0x3e, 0x5f, 0x0c, 0x85, 0xc4, 0x9d, 0xd4, - 0x8b, 0xd5, 0xfa, 0x17, 0x2d, 0xb1, 0x26, 0x81, 0xe7, 0x79, 0x07, 0x45, 0x82, 0x42, 0x22, 0x3d, - 0x0d, 0x97, 0xcf, 0xde, 0xea, 0xb8, 0xba, 0x16, 0x05, 0x8a, 0x5b, 0x0f, 0xec, 0x07, 0x30, 0xa4, - 0xc6, 0xbf, 0xff, 0x20, 0x52, 0x1b, 0x94, 0xad, 0xfa, 0xb7, 0x6e, 0x83, 0x14, 0x48, 0x58, 0x14, - 0x99, 0xe7, 0xa3, 0x9e, 0xc1, 0x08, 0xbd, 0xfe, 0x20, 0x11, 0x56, 0xdb, 0x96, 0x0a, 0xbb, 0x0b, - 0xbc, 0xd4, 0x37, 0x55, 0xf9, 0x9c, 0x6d, 0x5b, 0x87, 0x4e, 0x50, 0x9f, 0x24, 0x0e, 0x3a, 0x1a, - 0x0c, 0x54, 0x67, 0xbd, 0x0f, 0x34, 0x03, 0x5e, 0x45, 0x5b, 0x93, 0x42, 0xbe, 0x71, 0xe6, 0xa7, - 0xf9, 0x49, 0x1a, 0xb3, 0xb2, 0xfb, 0x0e, 0xee, 0x3d, 0xcf, 0x0c, 0x5a, 0xf8, 0xb5, 0x80, 0x42, - 0x7c, 0x0c, 0x75, 0xc5, 0xe1, 0x17, 0x29, 0x39, 0x55, 0x2b, 0xb1, 0xf5, 0x72, 0x06, 0x9e, 0x54, - 0x0b, 0x0e, 0xf2, 0x95, 0xc8, 0x5b, 0x69, 0xaf, 0x5b, 0x81, 0x97, 0xae, 0xb1, 0x6e, 0xc4, 0x6d, - 0x95, 0xd8, 0x22, 0x1e, 0x39, 0xf0, 0x76, 0x54, 0x19, 0x96, 0x03, 0x4c, 0x25, 0x85, 0x2f, 0xe1, - 0x84, 0xd7, 0xc1, 0x62, 0xe1, 0x9e, 0x9f, 0x1f, 0xd4, 0xb8, 0xf0, 0xc2, 0x68, 0x76, 0x7c, 0xcf, - 0x43, 0x3e, 0x60, 0x93, 0xd0, 0x89, 0x65, 0xae, 0x72, 0xcd, 0xd6, 0x00, 0x0d, 0x91, 0x42, 0x90, - 0x98, 0x02, 0xa9, 0xf6, 0x82, 0x1b, 0xb5, 0x22, 0xfd, 0xb6, 0xc2, 0x5c, 0xad, 0x86, 0x81, 0x1d, - }; - static const uint8_t m[256] = { - 0x30, 0x31, 0x36, 0x64, 0x61, 0x34, 0x31, 0x66, 0x34, 0x62, 0x66, 0x35, 0x38, 0x61, 0x36, 0x32, - 0x35, 0x61, 0x61, 0x35, 0x63, 0x33, 0x30, 0x37, 0x62, 0x63, 0x64, 0x31, 0x61, 0x37, 0x35, 0x30, - 0x33, 0x64, 0x62, 0x30, 0x36, 0x63, 0x39, 0x37, 0x62, 0x30, 0x39, 0x31, 0x39, 0x33, 0x38, 0x61, - 0x32, 0x31, 0x62, 0x35, 0x66, 0x36, 0x38, 0x65, 0x33, 0x37, 0x37, 0x61, 0x62, 0x38, 0x39, 0x39, - 0x62, 0x65, 0x66, 0x37, 0x63, 0x61, 0x31, 0x36, 0x35, 0x30, 0x65, 0x38, 0x66, 0x30, 0x38, 0x64, - 0x37, 0x32, 0x38, 0x37, 0x64, 0x64, 0x30, 0x66, 0x36, 0x64, 0x32, 0x61, 0x64, 0x36, 0x34, 0x31, - 0x32, 0x38, 0x38, 0x33, 0x38, 0x63, 0x35, 0x39, 0x35, 0x61, 0x32, 0x64, 0x31, 0x30, 0x65, 0x34, - 0x36, 0x37, 0x61, 0x62, 0x35, 0x34, 0x35, 0x33, 0x63, 0x34, 0x65, 0x63, 0x37, 0x37, 0x30, 0x35, - 0x33, 0x38, 0x61, 0x63, 0x39, 0x66, 0x38, 0x30, 0x36, 0x66, 0x30, 0x38, 0x66, 0x66, 0x33, 0x30, - 0x38, 0x65, 0x36, 0x65, 0x64, 0x62, 0x35, 0x35, 0x34, 0x31, 0x66, 0x39, 0x66, 0x30, 0x34, 0x36, - 0x63, 0x36, 0x37, 0x32, 0x62, 0x31, 0x32, 0x30, 0x37, 0x37, 0x35, 0x35, 0x62, 0x30, 0x35, 0x66, - 0x35, 0x36, 0x64, 0x33, 0x61, 0x36, 0x36, 0x31, 0x37, 0x64, 0x63, 0x37, 0x35, 0x34, 0x64, 0x35, - 0x65, 0x32, 0x30, 0x34, 0x63, 0x31, 0x36, 0x31, 0x36, 0x61, 0x31, 0x33, 0x65, 0x33, 0x62, 0x31, - 0x34, 0x65, 0x38, 0x65, 0x32, 0x39, 0x63, 0x39, 0x35, 0x33, 0x33, 0x38, 0x36, 0x65, 0x65, 0x64, - 0x62, 0x63, 0x30, 0x39, 0x34, 0x30, 0x37, 0x62, 0x39, 0x34, 0x33, 0x34, 0x38, 0x37, 0x37, 0x36, - 0x36, 0x37, 0x63, 0x62, 0x33, 0x30, 0x39, 0x63, 0x36, 0x33, 0x30, 0x34, 0x32, 0x32, 0x36, 0x32, - }; - static const uint8_t e[4] = { - 0x00, 0x01, 0x00, 0x01, - }; - static const uint8_t nprime[256] = { - 0x38, 0x62, 0xc1, 0xf5, 0x55, 0x2d, 0x3d, 0x60, 0x5e, 0x42, 0xe1, 0x65, 0xde, 0xed, 0x35, 0xd5, - 0xc5, 0x85, 0xe4, 0x4e, 0xeb, 0x74, 0xa5, 0x22, 0xb3, 0xed, 0x5f, 0x5b, 0xb1, 0xb9, 0xe9, 0x0a, - 0x7d, 0xa5, 0x74, 0x58, 0xf8, 0xa1, 0xab, 0x17, 0x74, 0xd0, 0x07, 0xa3, 0x7f, 0xd2, 0x9b, 0x50, - 0x2a, 0xed, 0x5e, 0xdc, 0x5a, 0x69, 0xfe, 0x0e, 0xb1, 0xd8, 0x53, 0x35, 0x9b, 0xef, 0x1d, 0x76, - 0x52, 0x9e, 0x87, 0x3c, 0xb0, 0x82, 0x4e, 0x03, 0xdf, 0x75, 0xed, 0x09, 0x9f, 0x3d, 0x37, 0xf6, - 0xe8, 0x0d, 0xc9, 0x2e, 0x81, 0xf2, 0x9d, 0x2e, 0xaa, 0xe6, 0x53, 0x79, 0x6b, 0x99, 0xef, 0x46, - 0x36, 0xd9, 0x2e, 0x9d, 0x15, 0xd1, 0x7f, 0x23, 0x14, 0xb9, 0xeb, 0x33, 0xa7, 0xd4, 0x8e, 0x86, - 0x60, 0xc9, 0xd9, 0x7c, 0xca, 0x54, 0x59, 0x57, 0x94, 0x1e, 0x52, 0x4d, 0xc8, 0x3f, 0x9b, 0x24, - 0x28, 0x25, 0xcb, 0x57, 0xca, 0x8f, 0x16, 0x5a, 0x37, 0xc2, 0xc6, 0xae, 0xc5, 0xe7, 0xc4, 0x2e, - 0xf3, 0x24, 0x1c, 0xb7, 0xe9, 0xf5, 0x92, 0x4e, 0xd4, 0x51, 0x50, 0xff, 0xde, 0x44, 0x3c, 0xae, - 0x72, 0xbd, 0x16, 0x39, 0x63, 0x8a, 0x22, 0x9c, 0x95, 0xda, 0x21, 0xf0, 0x4c, 0x12, 0x36, 0x2d, - 0x00, 0xad, 0xb3, 0x89, 0xb5, 0x09, 0x9e, 0x3d, 0x24, 0x81, 0xfc, 0xef, 0x99, 0x95, 0x22, 0x9d, - 0xb3, 0x94, 0x39, 0x32, 0xdd, 0xc4, 0x2b, 0x2f, 0xb0, 0x13, 0xfe, 0xb5, 0x5e, 0xc7, 0x64, 0x93, - 0x7a, 0xb5, 0x81, 0x93, 0x1f, 0x9f, 0x96, 0x1e, 0x7a, 0x5c, 0x8d, 0xde, 0x8f, 0xae, 0xd9, 0xc8, - 0xdd, 0x35, 0x1e, 0x17, 0x47, 0xb6, 0xab, 0xed, 0xb6, 0x82, 0x22, 0x4c, 0x62, 0xbd, 0x12, 0x4e, - 0x44, 0x5c, 0x48, 0x2b, 0x75, 0x63, 0x1c, 0xde, 0xfa, 0x15, 0x0d, 0xb1, 0x50, 0x31, 0xb6, 0xcb, - }; - static const uint8_t inv_r[256] = { - 0x2f, 0xb7, 0xf5, 0x4a, 0xd2, 0x19, 0xde, 0x24, 0x7c, 0xdb, 0xcd, 0x52, 0x6e, 0xbc, 0x2c, 0x5c, - 0x76, 0x9a, 0x36, 0xc3, 0x87, 0x33, 0xf7, 0xe9, 0x3d, 0x5b, 0x3d, 0xcd, 0x33, 0x7a, 0x3b, 0x4e, - 0x55, 0xf5, 0xd9, 0x42, 0x76, 0x63, 0x28, 0x7a, 0xa8, 0x7c, 0xf7, 0xd1, 0xf6, 0x0d, 0x26, 0xba, - 0xbe, 0x9f, 0x35, 0xf4, 0x86, 0xc5, 0x93, 0x4c, 0xe8, 0x76, 0xda, 0x88, 0xb8, 0xbe, 0xad, 0x25, - 0x6b, 0xe7, 0x44, 0x3b, 0x1c, 0x2c, 0x99, 0x15, 0xee, 0x33, 0x46, 0xc6, 0xe0, 0xb0, 0x39, 0x6d, - 0x20, 0xb2, 0x68, 0xc7, 0x75, 0x41, 0x2c, 0xff, 0xcb, 0x93, 0x1d, 0x40, 0xd2, 0x0e, 0x64, 0xea, - 0x2e, 0x0a, 0x55, 0x9f, 0x04, 0x9d, 0xfd, 0x5e, 0x24, 0xa9, 0x28, 0x5c, 0x2d, 0x1b, 0x29, 0x87, - 0x61, 0x6b, 0x50, 0x6a, 0x31, 0x31, 0x43, 0x12, 0x13, 0xe3, 0x1f, 0x47, 0x8a, 0x11, 0xd2, 0x5b, - 0x26, 0x5e, 0x79, 0x04, 0x0b, 0xa8, 0xb0, 0x36, 0x22, 0xda, 0x3c, 0x5e, 0xb9, 0x09, 0x48, 0xb0, - 0x32, 0x38, 0x25, 0xec, 0xfd, 0x5e, 0xef, 0xff, 0x80, 0x33, 0x9f, 0x94, 0x8c, 0x6e, 0x2a, 0xfb, - 0xbf, 0x65, 0x18, 0x98, 0x7e, 0xff, 0x41, 0xde, 0x00, 0x2f, 0xd2, 0x7d, 0xbf, 0x4c, 0x54, 0x4e, - 0x1c, 0x46, 0xd6, 0xab, 0xf6, 0x07, 0x34, 0x63, 0xe3, 0x0b, 0x81, 0xa0, 0x94, 0x7d, 0xaf, 0x7e, - 0x37, 0xd6, 0xc5, 0xa6, 0x4a, 0x90, 0x6c, 0x44, 0x6a, 0xd9, 0x0f, 0x20, 0xb2, 0xef, 0x22, 0xa0, - 0xdf, 0x38, 0x2d, 0x0b, 0xb3, 0x03, 0xb2, 0xc8, 0xe6, 0x8d, 0x74, 0xbf, 0x45, 0x91, 0xe0, 0x22, - 0x16, 0xbf, 0xc4, 0xda, 0x54, 0x26, 0xaa, 0x65, 0x85, 0x88, 0xc3, 0xfb, 0x9f, 0xfc, 0x14, 0xc4, - 0xff, 0x8b, 0x88, 0x47, 0x5f, 0xb1, 0x55, 0xdf, 0x47, 0x5c, 0xc0, 0x27, 0x39, 0x7b, 0xe8, 0xad, - }; - uint32_t result[64]; - static const uint8_t encrypted[256] = { - 0x9e, 0xf6, 0x6f, 0x46, 0xf5, 0x51, 0x1a, 0xbc, 0xc2, 0x9c, 0x49, 0x02, 0x21, 0x6c, 0x20, 0xae, - 0x49, 0x91, 0xcd, 0xba, 0xb9, 0x4f, 0xaf, 0xfd, 0x8d, 0x9a, 0x27, 0xbc, 0x0b, 0x69, 0x57, 0xc4, - 0xba, 0x18, 0xe1, 0x56, 0x45, 0x55, 0xbb, 0x3f, 0x7b, 0xca, 0x45, 0xb3, 0x9a, 0x0e, 0xd7, 0x64, - 0x6e, 0x71, 0xce, 0xd3, 0x08, 0xc9, 0x4b, 0x97, 0xab, 0x24, 0xe4, 0x6c, 0xe3, 0xc7, 0x52, 0x97, - 0x3c, 0x45, 0x17, 0x3b, 0x17, 0x0a, 0x90, 0x50, 0xed, 0x73, 0x4b, 0x49, 0x07, 0xee, 0x13, 0xaf, - 0x47, 0x1e, 0xd0, 0x24, 0xb1, 0xd2, 0xc8, 0x09, 0x75, 0xf3, 0x14, 0x9c, 0x71, 0x99, 0xe3, 0x94, - 0x5b, 0xf6, 0xef, 0x2e, 0x79, 0xf5, 0x1d, 0xdc, 0xa7, 0xc5, 0xed, 0x0a, 0x3f, 0x1d, 0x43, 0xd0, - 0x19, 0x14, 0x3a, 0xb7, 0x35, 0xc2, 0x3f, 0xa1, 0x9c, 0x00, 0xde, 0xf6, 0x96, 0x55, 0xf8, 0x0c, - 0x79, 0x08, 0x68, 0xf3, 0x84, 0x7c, 0x2e, 0x0c, 0x51, 0xb6, 0x5e, 0x9e, 0xcd, 0x50, 0xcc, 0x5f, - 0x71, 0x99, 0xc1, 0x0d, 0xf0, 0x3c, 0xd0, 0x80, 0x02, 0xf0, 0x8f, 0x12, 0x3e, 0x49, 0xa4, 0x9b, - 0x1f, 0x14, 0x05, 0xf2, 0x7b, 0x41, 0xc1, 0x3e, 0x8a, 0xb2, 0xab, 0x70, 0x28, 0x2f, 0x20, 0x94, - 0x17, 0x65, 0xf3, 0x89, 0x28, 0x6d, 0xcd, 0x0c, 0xea, 0x03, 0x4a, 0x10, 0x9d, 0xf9, 0x2e, 0xf4, - 0x64, 0x79, 0x7a, 0xec, 0x46, 0xb4, 0xdf, 0xce, 0x6a, 0x8e, 0xd8, 0x35, 0x62, 0xb3, 0x04, 0xea, - 0xf9, 0xc4, 0xde, 0xba, 0x2a, 0x5e, 0xbf, 0x59, 0xfa, 0xef, 0x2a, 0x42, 0x18, 0xc9, 0xf5, 0x7a, - 0x73, 0xb8, 0x67, 0x78, 0x97, 0x6d, 0x75, 0x4b, 0xdd, 0xfb, 0x9b, 0xe6, 0x4c, 0x04, 0x9c, 0x61, - 0x5f, 0x9a, 0x12, 0xbf, 0x2e, 0x75, 0x63, 0xdd, 0x50, 0xba, 0x2c, 0xef, 0xb0, 0x9a, 0x65, 0x24, - }; - - Sec_Eng_PKA_Reset(); - Sec_Eng_PKA_BigEndian_Enable(); - - Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_256, 0, (uint32_t*)n, 64, 0); - Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_256, 1, (uint32_t*)nprime, 64, 0); - Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_256, 2, (uint32_t*)m, 64, 0); - Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_256, 3, (uint32_t*)e, 1, 0); - - Sec_Eng_PKA_CREG(SEC_ENG_PKA_REG_SIZE_256, 4, 0, 0); - Sec_Eng_PKA_CREG(SEC_ENG_PKA_REG_SIZE_256, 5, 0, 1); - Sec_Eng_PKA_LMUL2N( - SEC_ENG_PKA_REG_SIZE_512, 2, - SEC_ENG_PKA_REG_SIZE_256, 2, - 2048, - 0 - ); - Sec_Eng_PKA_MREM( - SEC_ENG_PKA_REG_SIZE_256, 2, - SEC_ENG_PKA_REG_SIZE_512, 2, - SEC_ENG_PKA_REG_SIZE_256, 0, - 0 - ); - Sec_Eng_PKA_CREG(SEC_ENG_PKA_REG_SIZE_512, 2, 0, 1); - - Sec_Eng_PKA_MEXP( - SEC_ENG_PKA_REG_SIZE_256, 4, - SEC_ENG_PKA_REG_SIZE_256, 2, - SEC_ENG_PKA_REG_SIZE_256, 3, - SEC_ENG_PKA_REG_SIZE_256, 0, - 1 - ); - Sec_Eng_PKA_Move_Data( - SEC_ENG_PKA_REG_SIZE_256, 2, - SEC_ENG_PKA_REG_SIZE_256, 4, - 1 - ); - Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_256, 1, (uint32_t*)inv_r, 64, 0); - Sec_Eng_PKA_CREG(SEC_ENG_PKA_REG_SIZE_256, 4, 0, 0); - Sec_Eng_PKA_CREG(SEC_ENG_PKA_REG_SIZE_256, 5, 0, 1); - Sec_Eng_PKA_LMUL( - SEC_ENG_PKA_REG_SIZE_512, 2, - SEC_ENG_PKA_REG_SIZE_256, 2, - SEC_ENG_PKA_REG_SIZE_256, 1, - 0 - ); - Sec_Eng_PKA_MREM( - SEC_ENG_PKA_REG_SIZE_256, 2, - SEC_ENG_PKA_REG_SIZE_512, 2, - SEC_ENG_PKA_REG_SIZE_256, 0, - 0 - ); - Sec_Eng_PKA_CREG(SEC_ENG_PKA_REG_SIZE_512, 2, 0, 1); - Sec_Eng_PKA_Read_Data( - SEC_ENG_PKA_REG_SIZE_256, 2, - result, - 64 - ); - _dump_rsa_data((uint8_t*)result, sizeof(result)); - RSA_Compare_Data(encrypted, (uint8_t*)result, sizeof(result)); -} - -static void __attribute__((unused)) dump_xgcd_step(uint32_t result[64]) -{ - puts(" ---- PKA 8:0\r\n"); - Sec_Eng_PKA_Read_Data( - SEC_ENG_PKA_REG_SIZE_256, 0, - result, - 64 - ); - _dump_rsa_data((uint8_t*)result, 256); - - puts(" ---- PKA 8:1\r\n"); - Sec_Eng_PKA_Read_Data( - SEC_ENG_PKA_REG_SIZE_256, 1, - result, - 64 - ); - _dump_rsa_data((uint8_t*)result, 256); - - puts(" ---- PKA 8:2\r\n"); - Sec_Eng_PKA_Read_Data( - SEC_ENG_PKA_REG_SIZE_256, 2, - result, - 64 - ); - _dump_rsa_data((uint8_t*)result, 256); - - puts(" ---- PKA 8:3\r\n"); - Sec_Eng_PKA_Read_Data( - SEC_ENG_PKA_REG_SIZE_256, 3, - result, - 64 - ); - _dump_rsa_data((uint8_t*)result, 256); - - puts(" ---- PKA 8:4\r\n"); - Sec_Eng_PKA_Read_Data( - SEC_ENG_PKA_REG_SIZE_256, 4, - result, - 64 - ); - _dump_rsa_data((uint8_t*)result, 256); - - puts(" ---- PKA 8:5\r\n"); - Sec_Eng_PKA_Read_Data( - SEC_ENG_PKA_REG_SIZE_256, 5, - result, - 64 - ); - _dump_rsa_data((uint8_t*)result, 256); - - puts(" ---- PKA 8:6\r\n"); - Sec_Eng_PKA_Read_Data( - SEC_ENG_PKA_REG_SIZE_256, 6, - result, - 64 - ); - _dump_rsa_data((uint8_t*)result, 256); - - puts(" ---- PKA 8:7\r\n"); - Sec_Eng_PKA_Read_Data( - SEC_ENG_PKA_REG_SIZE_256, 7, - result, - 64 - ); - _dump_rsa_data((uint8_t*)result, 256); -} - - -static void _pka_test_case_xgcd(void) -{ - int count = 0; - static const uint8_t n[256] = { - 0xd8, 0xa6, 0x4f, 0xea, 0x28, 0xf9, 0xdf, 0x07, 0x04, 0x55, 0xfa, 0xfb, 0x50, 0x5d, 0xbe, 0xb6, - 0x9f, 0x7b, 0x53, 0x96, 0xef, 0x05, 0x5e, 0x0a, 0xf5, 0x2d, 0xe3, 0x67, 0x78, 0x07, 0x6b, 0xf6, - 0xb2, 0x17, 0xac, 0x2e, 0x51, 0x42, 0x84, 0xbb, 0xfe, 0x3e, 0x5f, 0x0c, 0x85, 0xc4, 0x9d, 0xd4, - 0x8b, 0xd5, 0xfa, 0x17, 0x2d, 0xb1, 0x26, 0x81, 0xe7, 0x79, 0x07, 0x45, 0x82, 0x42, 0x22, 0x3d, - 0x0d, 0x97, 0xcf, 0xde, 0xea, 0xb8, 0xba, 0x16, 0x05, 0x8a, 0x5b, 0x0f, 0xec, 0x07, 0x30, 0xa4, - 0xc6, 0xbf, 0xff, 0x20, 0x52, 0x1b, 0x94, 0xad, 0xfa, 0xb7, 0x6e, 0x83, 0x14, 0x48, 0x58, 0x14, - 0x99, 0xe7, 0xa3, 0x9e, 0xc1, 0x08, 0xbd, 0xfe, 0x20, 0x11, 0x56, 0xdb, 0x96, 0x0a, 0xbb, 0x0b, - 0xbc, 0xd4, 0x37, 0x55, 0xf9, 0x9c, 0x6d, 0x5b, 0x87, 0x4e, 0x50, 0x9f, 0x24, 0x0e, 0x3a, 0x1a, - 0x0c, 0x54, 0x67, 0xbd, 0x0f, 0x34, 0x03, 0x5e, 0x45, 0x5b, 0x93, 0x42, 0xbe, 0x71, 0xe6, 0xa7, - 0xf9, 0x49, 0x1a, 0xb3, 0xb2, 0xfb, 0x0e, 0xee, 0x3d, 0xcf, 0x0c, 0x5a, 0xf8, 0xb5, 0x80, 0x42, - 0x7c, 0x0c, 0x75, 0xc5, 0xe1, 0x17, 0x29, 0x39, 0x55, 0x2b, 0xb1, 0xf5, 0x72, 0x06, 0x9e, 0x54, - 0x0b, 0x0e, 0xf2, 0x95, 0xc8, 0x5b, 0x69, 0xaf, 0x5b, 0x81, 0x97, 0xae, 0xb1, 0x6e, 0xc4, 0x6d, - 0x95, 0xd8, 0x22, 0x1e, 0x39, 0xf0, 0x76, 0x54, 0x19, 0x96, 0x03, 0x4c, 0x25, 0x85, 0x2f, 0xe1, - 0x84, 0xd7, 0xc1, 0x62, 0xe1, 0x9e, 0x9f, 0x1f, 0xd4, 0xb8, 0xf0, 0xc2, 0x68, 0x76, 0x7c, 0xcf, - 0x43, 0x3e, 0x60, 0x93, 0xd0, 0x89, 0x65, 0xae, 0x72, 0xcd, 0xd6, 0x00, 0x0d, 0x91, 0x42, 0x90, - 0x98, 0x02, 0xa9, 0xf6, 0x82, 0x1b, 0xb5, 0x22, 0xfd, 0xb6, 0xc2, 0x5c, 0xad, 0x86, 0x81, 0x1d, - }; -#if 0 - static const uint8_t nprime[256] = { - 0x38, 0x62, 0xc1, 0xf5, 0x55, 0x2d, 0x3d, 0x60, 0x5e, 0x42, 0xe1, 0x65, 0xde, 0xed, 0x35, 0xd5, - 0xc5, 0x85, 0xe4, 0x4e, 0xeb, 0x74, 0xa5, 0x22, 0xb3, 0xed, 0x5f, 0x5b, 0xb1, 0xb9, 0xe9, 0x0a, - 0x7d, 0xa5, 0x74, 0x58, 0xf8, 0xa1, 0xab, 0x17, 0x74, 0xd0, 0x07, 0xa3, 0x7f, 0xd2, 0x9b, 0x50, - 0x2a, 0xed, 0x5e, 0xdc, 0x5a, 0x69, 0xfe, 0x0e, 0xb1, 0xd8, 0x53, 0x35, 0x9b, 0xef, 0x1d, 0x76, - 0x52, 0x9e, 0x87, 0x3c, 0xb0, 0x82, 0x4e, 0x03, 0xdf, 0x75, 0xed, 0x09, 0x9f, 0x3d, 0x37, 0xf6, - 0xe8, 0x0d, 0xc9, 0x2e, 0x81, 0xf2, 0x9d, 0x2e, 0xaa, 0xe6, 0x53, 0x79, 0x6b, 0x99, 0xef, 0x46, - 0x36, 0xd9, 0x2e, 0x9d, 0x15, 0xd1, 0x7f, 0x23, 0x14, 0xb9, 0xeb, 0x33, 0xa7, 0xd4, 0x8e, 0x86, - 0x60, 0xc9, 0xd9, 0x7c, 0xca, 0x54, 0x59, 0x57, 0x94, 0x1e, 0x52, 0x4d, 0xc8, 0x3f, 0x9b, 0x24, - 0x28, 0x25, 0xcb, 0x57, 0xca, 0x8f, 0x16, 0x5a, 0x37, 0xc2, 0xc6, 0xae, 0xc5, 0xe7, 0xc4, 0x2e, - 0xf3, 0x24, 0x1c, 0xb7, 0xe9, 0xf5, 0x92, 0x4e, 0xd4, 0x51, 0x50, 0xff, 0xde, 0x44, 0x3c, 0xae, - 0x72, 0xbd, 0x16, 0x39, 0x63, 0x8a, 0x22, 0x9c, 0x95, 0xda, 0x21, 0xf0, 0x4c, 0x12, 0x36, 0x2d, - 0x00, 0xad, 0xb3, 0x89, 0xb5, 0x09, 0x9e, 0x3d, 0x24, 0x81, 0xfc, 0xef, 0x99, 0x95, 0x22, 0x9d, - 0xb3, 0x94, 0x39, 0x32, 0xdd, 0xc4, 0x2b, 0x2f, 0xb0, 0x13, 0xfe, 0xb5, 0x5e, 0xc7, 0x64, 0x93, - 0x7a, 0xb5, 0x81, 0x93, 0x1f, 0x9f, 0x96, 0x1e, 0x7a, 0x5c, 0x8d, 0xde, 0x8f, 0xae, 0xd9, 0xc8, - 0xdd, 0x35, 0x1e, 0x17, 0x47, 0xb6, 0xab, 0xed, 0xb6, 0x82, 0x22, 0x4c, 0x62, 0xbd, 0x12, 0x4e, - 0x44, 0x5c, 0x48, 0x2b, 0x75, 0x63, 0x1c, 0xde, 0xfa, 0x15, 0x0d, 0xb1, 0x50, 0x31, 0xb6, 0xcb, - }; - static const uint8_t inv_r[256] = { - 0x2f, 0xb7, 0xf5, 0x4a, 0xd2, 0x19, 0xde, 0x24, 0x7c, 0xdb, 0xcd, 0x52, 0x6e, 0xbc, 0x2c, 0x5c, - 0x76, 0x9a, 0x36, 0xc3, 0x87, 0x33, 0xf7, 0xe9, 0x3d, 0x5b, 0x3d, 0xcd, 0x33, 0x7a, 0x3b, 0x4e, - 0x55, 0xf5, 0xd9, 0x42, 0x76, 0x63, 0x28, 0x7a, 0xa8, 0x7c, 0xf7, 0xd1, 0xf6, 0x0d, 0x26, 0xba, - 0xbe, 0x9f, 0x35, 0xf4, 0x86, 0xc5, 0x93, 0x4c, 0xe8, 0x76, 0xda, 0x88, 0xb8, 0xbe, 0xad, 0x25, - 0x6b, 0xe7, 0x44, 0x3b, 0x1c, 0x2c, 0x99, 0x15, 0xee, 0x33, 0x46, 0xc6, 0xe0, 0xb0, 0x39, 0x6d, - 0x20, 0xb2, 0x68, 0xc7, 0x75, 0x41, 0x2c, 0xff, 0xcb, 0x93, 0x1d, 0x40, 0xd2, 0x0e, 0x64, 0xea, - 0x2e, 0x0a, 0x55, 0x9f, 0x04, 0x9d, 0xfd, 0x5e, 0x24, 0xa9, 0x28, 0x5c, 0x2d, 0x1b, 0x29, 0x87, - 0x61, 0x6b, 0x50, 0x6a, 0x31, 0x31, 0x43, 0x12, 0x13, 0xe3, 0x1f, 0x47, 0x8a, 0x11, 0xd2, 0x5b, - 0x26, 0x5e, 0x79, 0x04, 0x0b, 0xa8, 0xb0, 0x36, 0x22, 0xda, 0x3c, 0x5e, 0xb9, 0x09, 0x48, 0xb0, - 0x32, 0x38, 0x25, 0xec, 0xfd, 0x5e, 0xef, 0xff, 0x80, 0x33, 0x9f, 0x94, 0x8c, 0x6e, 0x2a, 0xfb, - 0xbf, 0x65, 0x18, 0x98, 0x7e, 0xff, 0x41, 0xde, 0x00, 0x2f, 0xd2, 0x7d, 0xbf, 0x4c, 0x54, 0x4e, - 0x1c, 0x46, 0xd6, 0xab, 0xf6, 0x07, 0x34, 0x63, 0xe3, 0x0b, 0x81, 0xa0, 0x94, 0x7d, 0xaf, 0x7e, - 0x37, 0xd6, 0xc5, 0xa6, 0x4a, 0x90, 0x6c, 0x44, 0x6a, 0xd9, 0x0f, 0x20, 0xb2, 0xef, 0x22, 0xa0, - 0xdf, 0x38, 0x2d, 0x0b, 0xb3, 0x03, 0xb2, 0xc8, 0xe6, 0x8d, 0x74, 0xbf, 0x45, 0x91, 0xe0, 0x22, - 0x16, 0xbf, 0xc4, 0xda, 0x54, 0x26, 0xaa, 0x65, 0x85, 0x88, 0xc3, 0xfb, 0x9f, 0xfc, 0x14, 0xc4, - 0xff, 0x8b, 0x88, 0x47, 0x5f, 0xb1, 0x55, 0xdf, 0x47, 0x5c, 0xc0, 0x27, 0x39, 0x7b, 0xe8, 0xad, - }; -#endif - static const uint8_t n_exp[256] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, - }; - static const uint8_t all_zero[256] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - }; - uint32_t result[64]; - uint8_t pka_a_eq_0 = 0; - - - (void) count; - Sec_Eng_PKA_Reset(); - Sec_Eng_PKA_BigEndian_Enable(); - - Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_256, 1, (uint32_t*)n, 64, 0); - Sec_Eng_PKA_CREG(SEC_ENG_PKA_REG_SIZE_256, 2, 0, 0); - Sec_Eng_PKA_CREG(SEC_ENG_PKA_REG_SIZE_256, 3, 0, 1); - Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_256, 0, (uint32_t*)n_exp, 64, 0); - - - Sec_Eng_PKA_LMUL2N( - SEC_ENG_PKA_REG_SIZE_512, 1, - SEC_ENG_PKA_REG_SIZE_256, 0, - 2048, - 0 - ); - Sec_Eng_PKA_LDIV( - SEC_ENG_PKA_REG_SIZE_256, 0, - SEC_ENG_PKA_REG_SIZE_512, 1, - SEC_ENG_PKA_REG_SIZE_256, 1, - 0 - ); - Sec_Eng_PKA_MREM( - SEC_ENG_PKA_REG_SIZE_256, 4, - SEC_ENG_PKA_REG_SIZE_512, 1, - SEC_ENG_PKA_REG_SIZE_256, 1, - 0 - ); - Sec_Eng_PKA_CREG(SEC_ENG_PKA_REG_SIZE_512, 1, 0, 1); - Sec_Eng_PKA_Move_Data( - SEC_ENG_PKA_REG_SIZE_256, 2, - SEC_ENG_PKA_REG_SIZE_256, 1, - 0 - ); - Sec_Eng_PKA_Move_Data( - SEC_ENG_PKA_REG_SIZE_256, 1, - SEC_ENG_PKA_REG_SIZE_256, 4, - 1 - ); - Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_256, 4, (uint32_t*)all_zero, 64, 0); - Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_256, 5, (uint32_t*)n_exp, 64, 0); - Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_256, 6, (uint32_t*)n_exp, 64, 0); - Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_256, 7, (uint32_t*)all_zero, 64, 0); - - Sec_Eng_PKA_LMUL( - SEC_ENG_PKA_REG_SIZE_256, 8, - SEC_ENG_PKA_REG_SIZE_256, 0, - SEC_ENG_PKA_REG_SIZE_256, 5, - 0 - ); - Sec_Eng_PKA_LSUB( - SEC_ENG_PKA_REG_SIZE_256, 8, - SEC_ENG_PKA_REG_SIZE_256, 4, - SEC_ENG_PKA_REG_SIZE_256, 8, - 0 - ); - Sec_Eng_PKA_LMUL( - SEC_ENG_PKA_REG_SIZE_256, 9, - SEC_ENG_PKA_REG_SIZE_256, 0, - SEC_ENG_PKA_REG_SIZE_256, 7, - 0 - ); - Sec_Eng_PKA_LSUB( - SEC_ENG_PKA_REG_SIZE_256, 9, - SEC_ENG_PKA_REG_SIZE_256, 6, - SEC_ENG_PKA_REG_SIZE_256, 9, - 0 - ); - Sec_Eng_PKA_Move_Data( - SEC_ENG_PKA_REG_SIZE_256, 4, - SEC_ENG_PKA_REG_SIZE_256, 5, - 0 - ); - Sec_Eng_PKA_Move_Data( - SEC_ENG_PKA_REG_SIZE_256, 5, - SEC_ENG_PKA_REG_SIZE_256, 8, - 0 - ); - Sec_Eng_PKA_Move_Data( - SEC_ENG_PKA_REG_SIZE_256, 6, - SEC_ENG_PKA_REG_SIZE_256, 7, - 0 - ); - Sec_Eng_PKA_Move_Data( - SEC_ENG_PKA_REG_SIZE_256, 7, - SEC_ENG_PKA_REG_SIZE_256, 9, - 1 - ); - -#if 0 - blog_info("Dumping Step count %d\r\n", count++); - dump_xgcd_step(result); -#endif - while (!pka_a_eq_0) { - Sec_Eng_PKA_LDIV( - SEC_ENG_PKA_REG_SIZE_256, 0, - SEC_ENG_PKA_REG_SIZE_256, 2, - SEC_ENG_PKA_REG_SIZE_256, 1, - 0 - ); - Sec_Eng_PKA_MREM( - SEC_ENG_PKA_REG_SIZE_256, 3, - SEC_ENG_PKA_REG_SIZE_256, 2, - SEC_ENG_PKA_REG_SIZE_256, 1, - 0 - ); - Sec_Eng_PKA_LMUL( - SEC_ENG_PKA_REG_SIZE_256, 8, - SEC_ENG_PKA_REG_SIZE_256, 0, - SEC_ENG_PKA_REG_SIZE_256, 5, - 0 - ); - Sec_Eng_PKA_LSUB( - SEC_ENG_PKA_REG_SIZE_256, 8, - SEC_ENG_PKA_REG_SIZE_256, 4, - SEC_ENG_PKA_REG_SIZE_256, 8, - 0 - ); - Sec_Eng_PKA_LMUL( - SEC_ENG_PKA_REG_SIZE_256, 9, - SEC_ENG_PKA_REG_SIZE_256, 0, - SEC_ENG_PKA_REG_SIZE_256, 7, - 0 - ); - Sec_Eng_PKA_LSUB( - SEC_ENG_PKA_REG_SIZE_256, 9, - SEC_ENG_PKA_REG_SIZE_256, 6, - SEC_ENG_PKA_REG_SIZE_256, 9, - 0 - ); - Sec_Eng_PKA_Move_Data( - SEC_ENG_PKA_REG_SIZE_256, 2, - SEC_ENG_PKA_REG_SIZE_256, 1, - 0 - ); - Sec_Eng_PKA_Move_Data( - SEC_ENG_PKA_REG_SIZE_256, 4, - SEC_ENG_PKA_REG_SIZE_256, 5, - 0 - ); - Sec_Eng_PKA_Move_Data( - SEC_ENG_PKA_REG_SIZE_256, 5, - SEC_ENG_PKA_REG_SIZE_256, 8, - 0 - ); - Sec_Eng_PKA_Move_Data( - SEC_ENG_PKA_REG_SIZE_256, 6, - SEC_ENG_PKA_REG_SIZE_256, 7, - 0 - ); - Sec_Eng_PKA_Move_Data( - SEC_ENG_PKA_REG_SIZE_256, 7, - SEC_ENG_PKA_REG_SIZE_256, 9, - 1 - ); - Sec_Eng_PKA_Move_Data( - SEC_ENG_PKA_REG_SIZE_256, 1, - SEC_ENG_PKA_REG_SIZE_256, 3, - 1 - ); - Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_256, 10, (uint32_t*)n_exp, 64, 0); - Sec_Eng_PKA_LCMP( - &pka_a_eq_0, - SEC_ENG_PKA_REG_SIZE_256, 1, - SEC_ENG_PKA_REG_SIZE_256, 10 - ); -#if 0 - blog_info("Dumping Step count %d\r\n", count++); - dump_xgcd_step(result); -#endif - } - Sec_Eng_PKA_Read_Data( - SEC_ENG_PKA_REG_SIZE_256, 6, - result, - 64 - ); - _dump_rsa_data((uint8_t*)result, sizeof(result)); - //RSA_Compare_Data(encrypted, (uint8_t*)result, sizeof(result)); -} - -int bl_pka_test(void) -{ -#if 0 - bl_irq_register(SEC_PKA_IRQn, bl_sec_pka_IRQHandler); - bl_irq_enable(SEC_PKA_IRQn); -#endif - - _pka_test_case2(); - _pka_test_case_xgcd(); - _pka_test_case2(); - - return 0; -} - -void bl_sec_pka_IRQHandler(void) -{ - puts("--->>> PKA IRQ\r\n"); - SEC_Eng_IntMask(SEC_ENG_INT_PKA, MASK); -} diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_sec.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_sec.h deleted file mode 100644 index 09306bca1e..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_sec.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __BL_SEC_H__ -#define __BL_SEC_H__ -#include -#include -#include - -#include -#include - -/* copied SEC_Eng_SHA256_Ctx from stddrv */ -typedef struct { - uint32_t total[2]; - uint32_t *shaBuf; - uint32_t *shaPadding; - uint8_t shaFeed; -} _bl_sha_SEC_Eng_SHA256_Ctx_t; - -/* copied SEC_ENG_SHA_Type from stddrv, SHA1_RSVD removed */ -typedef enum { - BL_SHA256, - BL_SHA224, - BL_SHA1, -} bl_sha_type_t; - -typedef struct bl_sha_ctx { - _bl_sha_SEC_Eng_SHA256_Ctx_t sha_ctx; - uint32_t tmp[16]; - uint32_t pad[16]; -} bl_sha_ctx_t; - -extern SemaphoreHandle_t g_bl_sec_sha_mutex; - -int bl_sec_init(void); -int bl_sec_test(void); -int bl_pka_test(void); -int bl_sec_aes_init(void); -int bl_sec_aes_enc(uint8_t *key, int keysize, uint8_t *input, uint8_t *output); -int bl_sec_aes_test(void); -uint32_t bl_sec_get_random_word(void); -void bl_rand_stream(uint8_t *buf, int len); -int bl_rand(void); -/*SHA Engine API*/ -int bl_sec_sha_test(void); - -int bl_sha_mutex_take(); -int bl_sha_mutex_give(); -void bl_sha_init(bl_sha_ctx_t *ctx, const bl_sha_type_t type); -int bl_sha_update(bl_sha_ctx_t *ctx, const uint8_t *input, uint32_t len); -int bl_sha_finish(bl_sha_ctx_t *ctx, uint8_t *hash); -int bl_sec_ccm_encrypt_and_tag(const uint8_t *key, unsigned int key_bytelen, size_t length, const unsigned char *iv, size_t iv_len, const unsigned char *add, size_t add_len, - const unsigned char *input, unsigned char *output, unsigned char *tag, size_t tag_len); -int bl_sec_ccm_auth_decrypt(const uint8_t *key, unsigned int key_bytelen, size_t length,const unsigned char *iv, size_t iv_len, const unsigned char *add, - size_t add_len, const unsigned char *input, unsigned char *output, const unsigned char *tag, size_t tag_len); -int bl_sec_aes_ecb_encrypt(const uint8_t *key, unsigned int key_bytelen, size_t length, const unsigned char *input, unsigned char *output); -int bl_sec_aes_ecb_decrypt(const uint8_t *key, unsigned int key_bytelen, size_t length, const unsigned char *input, unsigned char *output); -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_sec_sha.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_sec_sha.c deleted file mode 100644 index 58f3d606a6..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_sec_sha.c +++ /dev/null @@ -1,180 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include - -#include - -#include -#include - -#include "bl_irq.h" -#include "bl_sec.h" - -#include - -typedef struct sha256_link_item { - SEC_Eng_SHA256_Link_Ctx ctx; - SEC_Eng_SHA_Link_Config_Type linkCfg; - uint32_t tmp[16]; - uint32_t pad[16]; -} sha256_link_item_t; - -#define BL_SHA_ID SEC_ENG_SHA_ID0 // this is the only valid value - -int bl_sha_mutex_take() -{ - if (pdPASS != xSemaphoreTake(g_bl_sec_sha_mutex, portMAX_DELAY)) { - blog_error("sha semphr take failed\r\n"); - return -1; - } - return 0; -} - -int bl_sha_mutex_give() -{ - if (pdPASS != xSemaphoreGive(g_bl_sec_sha_mutex)) { - blog_error("sha semphr give failed\\n"); - return -1; - } - return 0; -} - -void bl_sha_init(bl_sha_ctx_t *ctx, const bl_sha_type_t type) -{ - const SEC_ENG_SHA_Type sha_type = (SEC_ENG_SHA_Type)type; // bl_sha_type_t is the same as SEC_ENG_SHA_Type in driver - - Sec_Eng_SHA256_Init((SEC_Eng_SHA256_Ctx *)&ctx->sha_ctx, BL_SHA_ID, sha_type, ctx->tmp, ctx->pad); - Sec_Eng_SHA_Start(BL_SHA_ID); -} - -int bl_sha_update(bl_sha_ctx_t *ctx, const uint8_t *input, uint32_t len) -{ - return Sec_Eng_SHA256_Update((SEC_Eng_SHA256_Ctx *)&ctx->sha_ctx, BL_SHA_ID, input, len); -} - -int bl_sha_finish(bl_sha_ctx_t *ctx, uint8_t *hash) -{ - return Sec_Eng_SHA256_Finish((SEC_Eng_SHA256_Ctx *)&ctx->sha_ctx, BL_SHA_ID, hash); -} - -static const uint8_t shaSrcBuf1[64] = -{ - '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', - '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', - '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', - '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', -}; - -static void SHA_Compare_Data(const uint8_t *expected, const uint8_t *input, uint32_t len) -{ - int i = 0, is_failed = 0; - - for (i = 0; i < len; i++) { - if (input[i] != expected[i]) { - is_failed = 1; - blog_print("%s[%02d], %02x %02x\r\n", - input[i] ==expected[i] ? "S" : "F", - i, - input[i], - expected[i] - ); - } - } - if (is_failed) { - blog_print("====== Failed %lu Bytes======\r\n", len); - } else { - blog_print("====== Success %lu Bytes=====\r\n", len); - } -} - -void sha256_test_case0(void) -{ - SEC_ENG_SHA_ID_Type shaId = SEC_ENG_SHA_ID0; - sha256_link_item_t sha256_link = { - .linkCfg.shaMode = SEC_ENG_SHA256, - .linkCfg.shaHashSel = 0, - .linkCfg.shaIntClr = 0, - .linkCfg.shaIntSet = 1, - .linkCfg.shaMsgLen = 1, - .linkCfg.shaSrcAddr = 0x50020000, - }; - static const uint8_t sha256_test_result[] = - { - 0x31, 0x38, 0xbb, 0x9b, 0xc7, 0x8d, 0xf2, 0x7c, 0x47, 0x3e, 0xcf, 0xd1, 0x41, 0x0f, 0x7b, 0xd4, - 0x5e, 0xba, 0xc1, 0xf5, 0x9c, 0xf3, 0xff, 0x9c, 0xfe, 0x4d, 0xb7, 0x7a, 0xab, 0x7a, 0xed, 0xd3, - }; - - -#define SEC_SHA_IRQn (IRQ_NUM_BASE+14) - - bl_irq_register(SEC_SHA_IRQn, bl_sec_sha_IRQHandler); - bl_irq_enable(SEC_SHA_IRQn); - - Sec_Eng_SHA_Enable_Link(shaId); - Sec_Eng_SHA256_Link_Init(&sha256_link.ctx, shaId, - (uint32_t)&sha256_link.linkCfg, - sha256_link.tmp, - sha256_link.pad - ); - Sec_Eng_SHA256_Link_Update(&sha256_link.ctx, shaId, - shaSrcBuf1, - 64 - ); - //FIXME Request to change driver API - Sec_Eng_SHA256_Link_Finish(&sha256_link.ctx, shaId, (uint8_t*)sha256_link.linkCfg.result); - Sec_Eng_SHA_Disable_Link(shaId); - - SHA_Compare_Data((const uint8_t*)sha256_link.linkCfg.result, sha256_test_result, sizeof(sha256_test_result)); -} - -int bl_sec_sha_test(void) -{ - puts("^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\r\n"); - puts("^^^^^^^^^^^^^^^^^^^^^^^SHA256 TEST CASE^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\r\n"); - sha256_test_case0(); - puts("------------------------------------------------------------------------------------\r\n"); - - return 0; -} -static void _clear_sha_int() -{ - uint32_t SHAx = SEC_ENG_BASE; - uint32_t val; - - val = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - val = BL_SET_REG_BIT(val, SEC_ENG_SE_SHA_0_INT_CLR_1T); - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, val); -} - -void bl_sec_sha_IRQHandler(void) -{ - puts("--->>> SHA IRQ\r\n"); - _clear_sha_int(); -} diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_sys.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_sys.c deleted file mode 100644 index bc86c9c552..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_sys.c +++ /dev/null @@ -1,325 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include - -// #include -#include -#include -#include -#include -//FIXME no BL808/BL606p header file including is Allowed here -#ifdef BL808 -#include -#include -#elif defined(BL606P) -#include -#include -#else -#error "Use CHIP BL808/BL606P for this module" -#endif -#include "bl_sys.h" - -#define MFG_CONFIG_REG (0x4000F100) -#define MFG_CONFIG_VAL ("0mfg") - -#define REASON_WDT (0x77646F67) // watchdog reboot wdog -#define REASON_SOFTWARE (0x736F6674) // software soft -#define REASON_POWEROFF (0x0) // software soft - -#define RST_REASON (*((volatile uint32_t *)0x40010000)) // use 4 Bytes - -static BL_RST_REASON_E s_rst_reason = BL_RST_POWER_OFF; - -static char *RST_REASON_ARRAY[] = { - "BL_RST_POWER_OFF", - "BL_RST_HARDWARE_WATCHDOG", - "BL_RST_FATAL_EXCEPTION", - "BL_RST_SOFTWARE_WATCHDOG", - "BL_RST_SOFTWARE" -}; -extern volatile bool sys_log_all_enable;//XXX in debug.c - -BL_RST_REASON_E bl_sys_rstinfo_get(void) -{ - BL_RST_REASON_E ret = s_rst_reason; - - s_rst_reason = REASON_POWEROFF; - - return ret; -} - -int bl_sys_rstinfo_set(BL_RST_REASON_E val) -{ - if (val == BL_RST_SOFTWARE_WATCHDOG) { - RST_REASON = REASON_WDT; - } else if (val == BL_RST_SOFTWARE) { - RST_REASON = REASON_SOFTWARE; - } - - return 0; -} - -void bl_sys_rstinfo_init(void) -{ - if (RST_REASON == REASON_WDT) { - s_rst_reason = BL_RST_SOFTWARE_WATCHDOG; - } else if (RST_REASON == REASON_SOFTWARE) { - s_rst_reason = BL_RST_SOFTWARE; - } else { - s_rst_reason = BL_RST_POWER_OFF; - } - - bl_sys_rstinfo_set(BL_RST_SOFTWARE_WATCHDOG); -} - -int bl_sys_rstinfo_getsting(char *info) -{ - memcpy(info, (char *)RST_REASON_ARRAY[s_rst_reason], strlen(RST_REASON_ARRAY[s_rst_reason])); - *(info + strlen(RST_REASON_ARRAY[s_rst_reason])) = '\0'; - return 0; -} - -int bl_sys_logall_enable(void) -{ - sys_log_all_enable = true; - return 0; -} - -int bl_sys_logall_disable(void) -{ - sys_log_all_enable = false; - return 0; -} - -void bl_sys_mfg_config(void) -{ -#if 0 - union _reg_t { - uint8_t byte[4]; - uint32_t word; - } mfg = { - .byte = MFG_CONFIG_VAL, - }; - - *(volatile uint32_t*)(MFG_CONFIG_REG) = mfg.word; -#else - puts("WARN: bl_sys_mfg_config is NOT implemented\r\n"); -#endif -} - -int bl_sys_reset_por(void) -{ -#if 0 - bl_sys_rstinfo_set(BL_RST_SOFTWARE); - __disable_irq(); - GLB_SW_POR_Reset(); - while (1) { - /*empty dead loop*/ - } - - return 0; -#else - puts("WARN: bl_sys_rstinfo_set is NOT implemented\r\n"); - __disable_irq(); - GLB_SW_POR_Reset(); - while (1) { - /*empty dead loop*/ - } - - return 0; -#endif -} - -void bl_sys_reset_system(void) -{ - __disable_irq(); - GLB_SW_System_Reset(); - while (1) { - /*empty dead loop*/ - } -} - - -int bl_sys_em_config(void) -{ -#if 0 - extern uint8_t __LD_CONFIG_EM_SEL; - volatile uint32_t em_size; - - em_size = (uint32_t)&__LD_CONFIG_EM_SEL; - - switch (em_size) { - case 0 * 1024: - { - GLB_Set_EM_Sel(GLB_EM_0KB); - } - break; - case 8 * 1024: - { - GLB_Set_EM_Sel(GLB_EM_8KB); - } - break; - case 16 * 1024: - { - GLB_Set_EM_Sel(GLB_EM_16KB); - } - break; - default: - { - /*nothing here*/ - } - } - - return 0; -#else - puts("WARN: bl_sys_em_config is NOT implemented\r\n"); - return 0; -#endif -} - -int bl_sys_early_init(void) -{ -#if 0 - extern BL_Err_Type HBN_Aon_Pad_IeSmt_Cfg(uint8_t padCfg); - HBN_Aon_Pad_IeSmt_Cfg(1); - - extern void freertos_risc_v_trap_handler(void); //freertos_riscv_ram/portable/GCC/RISC-V/portASM.S - write_csr(mtvec, &freertos_risc_v_trap_handler); - - /* reset here for use wtd first then init hwtimer later*/ - GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_TMR); - /*debuger may NOT ready don't print anything*/ - return 0; -#else - puts("WARN: bl_sys_early_init is NOT implemented\r\n"); - return 0; -#endif -} - -int bl_sys_init(void) -{ - bl_sys_em_config(); - bl_sys_rstinfo_get(); - bl_sys_rstinfo_init(); - return 0; -} - -int bl_sys_isxipaddr(uint32_t addr) -{ - //XXX is 0xD000_0000 Address Range is really used - if ( ((addr & 0xFF000000) == 0x58000000) || ((addr & 0xFF000000) == 0x5C000000) || - ((addr & 0xFF000000) == 0xD8000000) || ((addr & 0xFF000000) == 0xDC000000)) { - return 1; - } - return 0; -} - -void bl_enable_cpu0(void) -{ - PDS_Power_On_MM_System(); -} - -void bl_boot_cpu0(uint32_t start_addr) -{ - GLB_Halt_CPU(GLB_CORE_ID_D0); - GLB_Set_CPU_Reset_Address(GLB_CORE_ID_D0, start_addr); - GLB_Release_CPU(GLB_CORE_ID_D0); -} - -void bl_halt_cpu0(void) -{ - GLB_Halt_CPU(GLB_CORE_ID_D0); -} - -void bl_release_cpu0(void) -{ - GLB_Release_CPU(GLB_CORE_ID_D0); -} - -void bl_sys_enabe_jtag(int cpuid) -{ - GLB_GPIO_Cfg_Type gpio_cfg; - - gpio_cfg.drive = 0; - gpio_cfg.smtCtrl = 1; - gpio_cfg.pullType = GPIO_PULL_NONE; - - gpio_cfg.gpioMode = GPIO_MODE_AF; - gpio_cfg.gpioFun = GPIO_FUN_JTAG_D0; - switch (cpuid) { - case 0: - { - } - break; - case 1: - { - puts("Enable CPU1 (D0/C906) on PIN6/PIN7/PIN12/PIN13\r\n"); - gpio_cfg.gpioPin = GLB_GPIO_PIN_6; - GLB_GPIO_Init(&gpio_cfg); - - gpio_cfg.gpioPin = GLB_GPIO_PIN_7; - GLB_GPIO_Init(&gpio_cfg); - - gpio_cfg.gpioPin = GLB_GPIO_PIN_12; - GLB_GPIO_Init(&gpio_cfg); - - gpio_cfg.gpioPin = GLB_GPIO_PIN_13; - GLB_GPIO_Init(&gpio_cfg); - } - break; - default: - { - } - break; - } -} - -static void bl_sys_reduce_mcu2ext(void) -{ - uint32_t tmpVal; - tmpVal = BL_RD_WORD(MCU_MISC_BASE + MCU_MISC_MCU_BUS_CFG1_OFFSET); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MCU_MISC_REG_X_WTHRE_MCU2EXT, 3); - BL_WR_WORD(MCU_MISC_BASE + MCU_MISC_MCU_BUS_CFG1_OFFSET, tmpVal); -} - -void bl_sys_lowlevel_init(void) -{ - bl_sys_reduce_mcu2ext(); - // blog_init(); - bl_irq_init(); - bl_flash_init(); - hal_boot2_init(); - hal_board_cfg(0); -#ifndef NO_BLE_CONFIG - GLB_Set_EM_Sel(GLB_WRAM96KB_EM64KB); -#endif -} - diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_sys.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_sys.h deleted file mode 100644 index 4fc3430a2f..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_sys.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __BL_SYS_H__ -#define __BL_SYS_H__ - -#include - -typedef enum { - BL_RST_POWER_OFF = 0, - BL_RST_HARDWARE_WATCHDOG, - BL_RST_FATAL_EXCEPTION, - BL_RST_SOFTWARE_WATCHDOG, - BL_RST_SOFTWARE, -} BL_RST_REASON_E; - -BL_RST_REASON_E bl_sys_rstinfo_get(void); -int bl_sys_rstinfo_set(BL_RST_REASON_E val); -int bl_sys_rstinfo_getsting(char *info); -void bl_sys_rstinfo_init(void); -int bl_sys_logall_enable(void); -int bl_sys_logall_disable(void); -void bl_sys_mfg_config(void); -int bl_sys_reset_por(void); -void bl_sys_reset_system(void); -int bl_sys_isxipaddr(uint32_t addr); -int bl_sys_early_init(void); -int bl_sys_init(void); -void bl_enable_cpu0(void); -void bl_boot_cpu0(uint32_t start_addr); -void bl_halt_cpu0(void); -void bl_release_cpu0(void); -void bl_sys_enabe_jtag(int cpuid); -void bl_sys_lowlevel_init(void); -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_timer.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_timer.c deleted file mode 100644 index 80012c4c46..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_timer.c +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "bl_timer.h" -#ifdef BL808 -#include -#include -#elif defined(BL606P) -#include -#include -#else -#error "Use CHIP BL808/BL606P for this module" -#endif - -#include -#include - -uint32_t bl_timer_now_us(void) -{ - return xTaskGetTickCount() * 1000000 / configTICK_RATE_HZ; -} - -uint32_t bl_system_core_clock_get(GLB_CORE_ID_Type core) -{ - uint32_t clockVal = 0; - - switch (core) { - case GLB_CORE_ID_M0: - clockVal = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_CLK); - break; - case GLB_CORE_ID_D0: - clockVal = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_DSP_CLK); - break; - case GLB_CORE_ID_LP: - clockVal = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_LP_CLK); - break; - default: - clockVal = 0; - break; - } - clockVal = clockVal ? clockVal : (32 * 1000 * 1000); - - return clockVal; -} - -BL_Err_Type bl_cpu_set_core_mtimer_clk(GLB_CORE_ID_Type core, uint8_t enable, uint16_t div) -{ - uint32_t tmpVal = 0; - uint32_t address = 0; - - CHECK_PARAM((div <= 0x3FF)); - - switch (core) { - case GLB_CORE_ID_M0: - address = MCU_MISC_BASE + MCU_MISC_MCU_E907_RTC_OFFSET; - break; - case GLB_CORE_ID_D0: - address = MM_MISC_BASE + MM_MISC_CPU_RTC_OFFSET; - break; - case GLB_CORE_ID_LP: - address = PDS_BASE + PDS_CPU_CORE_CFG8_OFFSET; - break; - default: - address = MCU_MISC_BASE + MCU_MISC_MCU_E907_RTC_OFFSET; - break; - } - - /* disable rtc first */ - /* MCU RTC_EN is [31] */ - /* DSP RTC_EN is [31] */ - /* LP RTC_EN is [31] */ - tmpVal = BL_RD_WORD(address); - tmpVal = BL_CLR_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_EN); - BL_WR_WORD(address, tmpVal); - - /* set div */ - /* MCU RTC_DIV is [9:0] */ - /* DSP RTC_DIV is [9:0] */ - /* LP RTC_DIV is [9:0] */ - tmpVal = BL_RD_WORD(address); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MCU_MISC_REG_MCU_RTC_DIV, div); - BL_WR_WORD(address, tmpVal); - - /* enable or not */ - /* MCU RTC_EN is [31] */ - /* DSP RTC_EN is [31] */ - /* LP RTC_EN is [31] */ - tmpVal = BL_RD_WORD(address); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_EN); - } - BL_WR_WORD(address, tmpVal); - - return SUCCESS; -} - -void bl_mtimer_c906_clock_init(void) -{ - uint32_t clockVal = 0; - clockVal = bl_system_core_clock_get(GLB_CORE_ID_D0); - - /* Set MTimer clock source 10M */ - bl_cpu_set_core_mtimer_clk(GLB_CORE_ID_D0, 1, (clockVal / 1000 / 1000 / 10) - 1); -} diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_timer.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_timer.h deleted file mode 100644 index 2ea2756d01..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_timer.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __BL_TIMER_H__ -#define __BL_TIMER_H__ -#include -uint32_t bl_timer_now_us(void); -void bl_mtimer_c906_clock_init(void); -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_uart.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_uart.c deleted file mode 100644 index da0b7c2cd2..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_uart.c +++ /dev/null @@ -1,552 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -//FIXME no BL808/BL606p header file including is Allowed here -#ifdef BL808 -#include -#include -#include -#elif defined(BL606P) -#include -#include -#include -#else -#error "Use CHIP BL808/BL606P for this module" -#endif - -#include "bl_uart.h" -#include "bl_irq.h" - -#ifdef BFLB_USE_HAL_DRIVER -void UART0_IRQHandler(void); -void UART1_IRQHandler(void); -void UART2_IRQHandler(void); -void UART3_IRQHandler(void); -#endif - -//TODO Do in std driver -#define UART_NUMBER_SUPPORTED 4 -#define UART_FIFO_TX_CNT (32) -#define FIFO_TX_SIZE_BURST (32) -static const uint32_t uartAddr[4] = {UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE}; - -typedef struct bl_uart_notify { - cb_uart_notify_t rx_cb; - void *rx_cb_arg; - - cb_uart_notify_t tx_cb; - void *tx_cb_arg; -} bl_uart_notify_t; - -static bl_uart_notify_t g_uart_notify_arg[UART_NUMBER_SUPPORTED]; - - -static void uart_init_demo(uint8_t id) -{ - static UART_CFG_Type uartCfg = { - 80*1000*1000, /* UART clock */ - 2000000, /* UART Baudrate */ - UART_DATABITS_8, /* UART data bits length */ - UART_STOPBITS_1, /* UART data stop bits length */ - UART_PARITY_NONE, /* UART no parity */ - DISABLE, /* Disable auto flow control */ - DISABLE, /* Disable rx input de-glitch function */ - DISABLE, /* Disable RTS output SW control mode */ - DISABLE, /* Disable tx output SW control mode */ - DISABLE, /* Disable tx lin mode */ - DISABLE, /* Disable rx lin mode */ - 0, /* Tx break bit count for lin mode */ - UART_LSB_FIRST /* UART each data byte is send out LSB-first */ - }; - - /* Disable all interrupt */ - UART_IntMask(id, UART_INT_ALL,MASK); - - /* Disable uart before config */ - UART_Disable(id, UART_TXRX); - - /* UART init */ - UART_Init(id, &uartCfg); - - /* Enable tx free run mode */ - UART_TxFreeRun(id, ENABLE); - - /* Enable uart */ - UART_Enable(id, UART_TXRX); -} - -static int uart_signal_get(uint8_t pin) -{ - //TODO no magic number is allowed here - if (pin >= 12 && pin <=23) { - return (pin + 6) % 12; - } else if (pin >= 36 && pin <=45) { - return (pin + 6) % 12; - } - return (pin % 12); -} - -static int uart_func_get(uint8_t id, GLB_UART_SIG_FUN_Type uartfunc) -{ - switch (id) { - case 0: - return uartfunc; - case 1: - return (GLB_UART_SIG_FUN_UART1_RTS - GLB_UART_SIG_FUN_UART0_RTS) * 1 + uartfunc; - case 2: - return (GLB_UART_SIG_FUN_UART1_RTS - GLB_UART_SIG_FUN_UART0_RTS) * 1 + uartfunc; - default: - /*empty here*/ - //TODO should assert here? - return uartfunc; - } -} - -static void uart_gpio_demo(uint8_t id, uint8_t tx_pin, uint8_t rx_pin, uint8_t cts_pin, uint8_t rts_pin) -{ - GLB_GPIO_Cfg_Type gpio_cfg; - uint8_t uart_func, uart_sig; - - //FIXME SWAP set is NOT put here - GLB_UART_Sig_Swap_Set(GLB_UART_SIG_SWAP_GRP_GPIO12_GPIO23, 1); - GLB_UART_Sig_Swap_Set(GLB_UART_SIG_SWAP_GRP_GPIO36_GPIO45, 1); - - //common GPIO cfg - gpio_cfg.drive = 0; - gpio_cfg.smtCtrl = 1; - gpio_cfg.gpioMode = GPIO_MODE_AF; - gpio_cfg.pullType = GPIO_PULL_UP; - gpio_cfg.gpioFun = GPIO_FUN_UART; - //cfg for UART Tx - gpio_cfg.gpioPin = GLB_GPIO_PIN_0 + tx_pin; - uart_func = uart_func_get(id, GLB_UART_SIG_FUN_UART0_TXD); - uart_sig = uart_signal_get(gpio_cfg.gpioPin); - GLB_UART_Fun_Sel((GLB_UART_SIG_Type)uart_sig, (GLB_UART_SIG_FUN_Type)uart_func); - GLB_UART_Fun_Sel((GLB_UART_SIG_Type)uart_func, (GLB_UART_SIG_FUN_Type)uart_sig); - GLB_GPIO_Init(&gpio_cfg); - //cfg for UART Rx - gpio_cfg.gpioPin = GLB_GPIO_PIN_0 + rx_pin; - uart_func = uart_func_get(id, GLB_UART_SIG_FUN_UART0_RXD); - uart_sig = uart_signal_get(gpio_cfg.gpioPin); - GLB_UART_Fun_Sel((GLB_UART_SIG_Type)uart_sig, (GLB_UART_SIG_FUN_Type)uart_func); - GLB_UART_Fun_Sel((GLB_UART_SIG_Type)uart_func, (GLB_UART_SIG_FUN_Type)uart_sig); - GLB_GPIO_Init(&gpio_cfg); - - //Enable UART clock - GLB_Set_UART_CLK(1, 0, 0); -} - -int bl_uart_init(uint8_t id, uint8_t tx_pin, uint8_t rx_pin, uint8_t cts_pin, uint8_t rts_pin, uint32_t baudrate) -{ - UART_CFG_Type uart_dbg_cfg = { - // 32 * 1000 * 1000, /*UART clock*/ - 80*1000*1000, /*UART clock from XTAL*/ - 2000000, /* baudrate */ - UART_DATABITS_8, /* data bits */ - UART_STOPBITS_1, /* stop bits */ - UART_PARITY_NONE, /* parity */ - DISABLE, /* Disable auto flow control */ - DISABLE, /* Disable rx input de-glitch function */ - DISABLE, /* Disable RTS output SW control mode */ - DISABLE, /* Disable tx output SW control mode */ - DISABLE, /* Disable tx lin mode */ - DISABLE, /* Disable rx lin mode */ - 0, /* Tx break bit count for lin mode */ - UART_LSB_FIRST, /* UART each data byte is send out LSB-first */ - }; - - UART_FifoCfg_Type fifoCfg = { - 16, /* TX FIFO threshold */ - 16, /* RX FIFO threshold */ - DISABLE, /* Disable tx dma req/ack interface */ - DISABLE /* Disable rx dma req/ack interface */ - }; - - /* init debug uart gpio first */ - uart_gpio_demo(id, tx_pin, rx_pin, cts_pin, rts_pin); - uart_init_demo(id); - - /* disable all interrupt */ - UART_IntMask(id, UART_INT_ALL, MASK); - - /* disable uart before config */ - UART_Disable(id, UART_TXRX); - - /* uart init with default configuration */ - UART_Init(id, &uart_dbg_cfg); - - /* UART fifo configuration */ - UART_FifoConfig(id, &fifoCfg); - - /* Enable tx free run mode */ - UART_TxFreeRun(id, ENABLE); - - /* Set rx time-out value */ - UART_SetRxTimeoutValue(id, 80); - - /* enable uart */ - UART_AutoBaudDetection(id, 0); - UART_Enable(id, UART_TXRX); - - return 0; -} - -/*This function is NOT thread safe*/ -int bl_uart_data_send(uint8_t id, uint8_t data) -{ - -// UART_SendData(id, &data,1); - uint32_t UARTx = uartAddr[id]; - - /* Wait for FIFO */ - while (UART_GetTxFifoCount(id) == 0) { - } - - BL_WR_BYTE(UARTx + UART_FIFO_WDATA_OFFSET, data); - - return 0; -} - -int bl_uart_data_recv(uint8_t id) -{ - int ret; - uint32_t UARTx = uartAddr[id]; - - /* Receive data */ - if (UART_GetRxFifoCount(id) > 0) { - ret = BL_RD_BYTE(UARTx + UART_FIFO_RDATA_OFFSET); - } else { - ret = -1; - } - - return ret; -} - -int bl_uart_int_rx_enable(uint8_t id) -{ - UART_SetRxTimeoutValue((UART_ID_Type)id, 24); - UART_IntMask((UART_ID_Type)id, UART_INT_RX_FIFO_REQ, UNMASK); - UART_IntMask((UART_ID_Type)id, UART_INT_RX_END, UNMASK); - UART_IntMask((UART_ID_Type)id, UART_INT_RTO, UNMASK); - return 0; -} - -int bl_uart_int_rx_disable(uint8_t id) -{ - UART_IntMask((UART_ID_Type)id, UART_INT_RX_FIFO_REQ, MASK); - UART_IntMask((UART_ID_Type)id, UART_INT_RX_END, MASK); - UART_IntMask((UART_ID_Type)id, UART_INT_RTO, MASK); - return 0; -} - -int bl_uart_int_tx_enable(uint8_t id) -{ - UART_IntMask((UART_ID_Type)id, UART_INT_TX_FIFO_REQ, UNMASK); - return 0; -} - -int bl_uart_int_tx_disable(uint8_t id) -{ - UART_IntMask((UART_ID_Type)id, UART_INT_TX_FIFO_REQ, MASK); - return 0; -} - -int bl_uart_flush(uint8_t id) -{ - /* Wait for FIFO */ - while (UART_FIFO_TX_CNT != UART_GetTxFifoCount(id)) { - } - - return 0; -} - -void bl_uart_getdefconfig(uint8_t id, uint8_t *parity) -{ - if (NULL == parity) { - return; - } - - //*baudrate = 115200;/* not support set no baud */ - *parity = (uint8_t)UART_PARITY_NONE; -} - -void bl_uart_setbaud(uint8_t id, uint32_t baud) -{ - //FIXME - puts("uart is NOT implemented\r\n"); - while (1) { - } -} - -int bl_uart_int_enable(uint8_t id) -{ - switch (id) { - case 0: - { - bl_uart_int_rx_enable(0); - // bl_uart_int_tx_enable(0); - bl_irq_register(UART0_IRQn, UART0_IRQHandler); - bl_irq_enable(UART0_IRQn); - } - break; - case 1: - { - bl_uart_int_rx_enable(1); - // bl_uart_int_tx_enable(1); - bl_irq_register(UART1_IRQn, UART1_IRQHandler); - bl_irq_enable(UART1_IRQn); - } - break; - case 2: - { - bl_uart_int_rx_enable(2); - // bl_uart_int_tx_enable(2); - bl_irq_register(UART2_IRQn, UART2_IRQHandler); - bl_irq_enable(UART2_IRQn); - } - break; - case 3: - { - bl_uart_int_rx_enable(3); - // bl_uart_int_tx_enable(3); - bl_irq_register(UART3_IRQn, UART3_IRQHandler); - bl_irq_enable(UART3_IRQn); - } - break; - default: - { - return -1; - } - } - - return 0; -} - -int bl_uart_int_disable(uint8_t id) -{ - switch (id) { - case 0: - { - bl_uart_int_rx_disable(0); - bl_uart_int_tx_disable(0); - bl_irq_unregister(UART0_IRQn, UART0_IRQHandler); - bl_irq_disable(UART0_IRQn); - } - break; - case 1: - { - bl_uart_int_rx_disable(1); - bl_uart_int_tx_disable(1); - bl_irq_unregister(UART1_IRQn, UART1_IRQHandler); - bl_irq_disable(UART1_IRQn); - } - break; - case 2: - { - bl_uart_int_rx_disable(2); - bl_uart_int_tx_disable(2); - bl_irq_unregister(UART2_IRQn, UART2_IRQHandler); - bl_irq_disable(UART2_IRQn); - } - break; - case 3: - { - bl_uart_int_rx_disable(3); - bl_uart_int_tx_disable(3); - bl_irq_unregister(UART3_IRQn, UART3_IRQHandler); - bl_irq_disable(UART3_IRQn); - } - break; - default: - { - return -1; - } - } - - return 0; -} - -int bl_uart_int_rx_notify_register(uint8_t id, cb_uart_notify_t cb, void *arg) -{ - if (!(id < UART_NUMBER_SUPPORTED)) { - /*UART ID overflow*/ - return -1; - } - - g_uart_notify_arg[id].rx_cb = cb; - g_uart_notify_arg[id].rx_cb_arg = arg; - - return 0; -} - -int bl_uart_int_tx_notify_register(uint8_t id, cb_uart_notify_t cb, void *arg) -{ - if (!(id < UART_NUMBER_SUPPORTED)) { - /*UART ID overflow*/ - return -1; - } - - g_uart_notify_arg[id].tx_cb = cb; - g_uart_notify_arg[id].tx_cb_arg = arg; - - return 0; -} - -int bl_uart_int_rx_notify_unregister(uint8_t id, cb_uart_notify_t cb, void *arg) -{ - if (!(id < UART_NUMBER_SUPPORTED)) { - /*UART ID overflow*/ - return -1; - } - g_uart_notify_arg[id].rx_cb = NULL; - g_uart_notify_arg[id].rx_cb_arg = NULL; - - return 0; -} - -int bl_uart_int_tx_notify_unregister(uint8_t id, cb_uart_notify_t cb, void *arg) -{ - if (!(id < UART_NUMBER_SUPPORTED)) { - /*UART ID overflow*/ - return -1; - } - g_uart_notify_arg[id].tx_cb = NULL; - g_uart_notify_arg[id].tx_cb_arg = NULL; - - return 0; -} - -static inline void uart_generic_notify_handler(uint8_t id) -{ - cb_uart_notify_t cb; - void *arg; - uint32_t tmpVal = 0; - uint32_t maskVal = 0; - uint32_t UARTx = uartAddr[id]; - - tmpVal = BL_RD_REG(UARTx,UART_INT_STS); - maskVal = BL_RD_REG(UARTx,UART_INT_MASK); - - /* Length of uart tx data transfer arrived interrupt */ - if(BL_IS_REG_BIT_SET(tmpVal,UART_UTX_END_INT) && !BL_IS_REG_BIT_SET(maskVal,UART_CR_UTX_END_MASK)){ - BL_WR_REG(UARTx,UART_INT_CLEAR,0x1); - } - - /* Length of uart rx data transfer arrived interrupt */ - if(BL_IS_REG_BIT_SET(tmpVal,UART_URX_END_INT) && !BL_IS_REG_BIT_SET(maskVal,UART_CR_URX_END_MASK)){ - BL_WR_REG(UARTx,UART_INT_CLEAR,0x2); - - /*Receive Data ready*/ - cb = g_uart_notify_arg[id].rx_cb; - arg = g_uart_notify_arg[id].rx_cb_arg; - - if (cb) { - /*notify up layer*/ - cb(arg); - } - } - - /* Tx fifo ready interrupt,auto-cleared when data is pushed */ - if(BL_IS_REG_BIT_SET(tmpVal,UART_UTX_FRDY_INT) && !BL_IS_REG_BIT_SET(maskVal,UART_CR_UTX_FRDY_MASK)){ - /* Transmit data request interrupt */ - cb = g_uart_notify_arg[id].tx_cb; - arg = g_uart_notify_arg[id].tx_cb_arg; - - if (cb) { - /*notify up layer*/ - cb(arg); - } - } - - /* Rx fifo ready interrupt,auto-cleared when data is popped */ - if(BL_IS_REG_BIT_SET(tmpVal,UART_URX_FRDY_INT) && !BL_IS_REG_BIT_SET(maskVal,UART_CR_URX_FRDY_MASK)){ - /*Receive Data ready*/ - - cb = g_uart_notify_arg[id].rx_cb; - arg = g_uart_notify_arg[id].rx_cb_arg; - - if (cb) { - /*notify up layer*/ - cb(arg); - } - } - - /* Rx time-out interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal,UART_URX_RTO_INT) && !BL_IS_REG_BIT_SET(maskVal,UART_CR_URX_RTO_MASK)){ - BL_WR_REG(UARTx,UART_INT_CLEAR,0x10); - - /*Receive Data ready*/ - cb = g_uart_notify_arg[id].rx_cb; - arg = g_uart_notify_arg[id].rx_cb_arg; - - if (cb) { - /*notify up layer*/ - cb(arg); - } - } - - /* Rx parity check error interrupt */ - if(BL_IS_REG_BIT_SET(tmpVal,UART_URX_PCE_INT) && !BL_IS_REG_BIT_SET(maskVal,UART_CR_URX_PCE_MASK)){ - BL_WR_REG(UARTx,UART_INT_CLEAR,0x20); - } - - /* Tx fifo overflow/underflow error interrupt */ - if(BL_IS_REG_BIT_SET(tmpVal,UART_UTX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal,UART_CR_UTX_FER_MASK)){ - } - - /* Rx fifo overflow/underflow error interrupt */ - if(BL_IS_REG_BIT_SET(tmpVal,UART_URX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal,UART_CR_URX_FER_MASK)){ - } - - return; -} - -#ifdef BFLB_USE_HAL_DRIVER -void UART0_IRQHandler(void) -{ - uart_generic_notify_handler(0); -} - -void UART1_IRQHandler(void) -{ - uart_generic_notify_handler(1); -} - -void UART2_IRQHandler(void) -{ - uart_generic_notify_handler(2); -} - -void UART3_IRQHandler(void) -{ - uart_generic_notify_handler(3); -} -#endif - diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_uart.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_uart.h deleted file mode 100644 index 909ba99e73..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_uart.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __BL_UART_H__ -#define __BL_UART_H__ -#include -#define BL_UART_BUFFER_SIZE_MIN (128) -#define BL_UART_BUFFER_SIZE_MASK (128 - 1) - -typedef void (*cb_uart_notify_t)(void *arg); -int bl_uart_gpio_init(uint8_t id, uint8_t tx, uint8_t rx, uint8_t rts, uint8_t cts, int baudrate); -int bl_uart_init(uint8_t id, uint8_t tx_pin, uint8_t rx_pin, uint8_t cts_pin, uint8_t rts_pin, uint32_t baudrate); -int bl_uart_simple_init(uint8_t id, uint8_t tx_pin, uint8_t rx_pin, uint8_t cts_pin, uint8_t rts_pin, uint32_t baudrate); -int bl_uart_debug_early_init(uint32_t baudrate); -int bl_uart_early_init(uint8_t id, uint8_t tx_pin, uint32_t baudrate); - -int bl_uart_int_rx_enable(uint8_t id); -int bl_uart_int_rx_disable(uint8_t id); -int bl_uart_int_tx_enable(uint8_t id); -int bl_uart_int_tx_disable(uint8_t id); -int bl_uart_string_send(uint8_t id, char *data); -int bl_uart_flush(uint8_t id); -void bl_uart_getdefconfig(uint8_t id, uint8_t *parity); -//FIXME fix bl_uart_setconfig -//void bl_uart_setconfig(uint8_t id, uint32_t baudrate, UART_Parity_Type parity); -void bl_uart_setbaud(uint8_t id, uint32_t baud); -int bl_uart_data_send(uint8_t id, uint8_t data); -int bl_uart_datas_send(uint8_t id, uint8_t *data, int len); -int bl_uart_data_recv(uint8_t id); -int bl_uart_int_enable(uint8_t id); -int bl_uart_int_disable(uint8_t id); -int bl_uart_int_rx_notify_register(uint8_t id, cb_uart_notify_t cb, void *arg); -int bl_uart_int_tx_notify_register(uint8_t id, cb_uart_notify_t cb, void *arg); -int bl_uart_int_rx_notify_unregister(uint8_t id, cb_uart_notify_t cb, void *arg); -int bl_uart_int_tx_notify_unregister(uint8_t id, cb_uart_notify_t cb, void *arg); -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_usb_cam.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_usb_cam.c deleted file mode 100644 index 8625934d5d..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_usb_cam.c +++ /dev/null @@ -1,322 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include -#include -#include -#include -#include -#include "bl_usb_cam.h" - -#define VIDEO_IN_EP 0x81 - -#ifdef CONFIG_USB_HS -#define MAX_PAYLOAD_SIZE 1024 -#else -#define MAX_PAYLOAD_SIZE 1023 -#endif -#define VIDEO_PACKET_SIZE (unsigned int)(((MAX_PAYLOAD_SIZE / 1)) | (0x00 << 11)) - -#define WIDTH (unsigned int)(800) -#define HEIGHT (unsigned int)(600) - -#define CAM_FPS (30) -#define INTERVAL (unsigned long)(10000000 / CAM_FPS) -#define MIN_BIT_RATE (unsigned long)(WIDTH * HEIGHT * 16 * CAM_FPS) //16 bit -#define MAX_BIT_RATE (unsigned long)(WIDTH * HEIGHT * 16 * CAM_FPS) -#define MAX_FRAME_SIZE (unsigned long)(WIDTH * HEIGHT * 2) - -#define USB_VIDEO_DESC_SIZ (unsigned long)(9 + \ - 8 + \ - 9 + \ - 13 + \ - 18 + \ - 9 + \ - 12 + \ - 9 + \ - 14 + \ - 11 + \ - 38 + \ - 9 + \ - 7) - -#define VC_TERMINAL_SIZ (unsigned int)(13 + 18 + 12 + 9) -#define VS_HEADER_SIZ (unsigned int)(13 + 1 + 11 + 38) - -#define USBD_VID 0xffff -#define USBD_PID 0xffff -#define USBD_MAX_POWER 100 -#define USBD_LANGID_STRING 1033 -#define TASK_MAIN_PRIORITY 20 -#define PER_FRAME_MJPEG 100*1024 -#define USB_MAX_BUFFER 120*1024 -#define MJPEG_DEFAULT_ADDR 0x80400000 //if mjpeg no init mjpeg addr reg default value - -const uint8_t video_descriptor[] = { - USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0001, 0x01), - USB_CONFIG_DESCRIPTOR_INIT(USB_VIDEO_DESC_SIZ, 0x02, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), - VIDEO_VC_DESCRIPTOR_INIT(0x00, 0, 0x0100, VC_TERMINAL_SIZ, 48000000, 0x02), - VIDEO_VS_DESCRIPTOR_INIT(0x01, 0x00, 0x00), - VIDEO_VS_HEADER_DESCRIPTOR_INIT(0x01, VS_HEADER_SIZ, VIDEO_IN_EP, 1, 0x00), - VIDEO_VS_FORMAT_MJPEG_DESCRIPTOR_INIT(0x01, 0x01), - VIDEO_VS_FRAME_MJPEG_DESCRIPTOR_INIT(0x01, WIDTH, HEIGHT, MIN_BIT_RATE, MAX_BIT_RATE, MAX_FRAME_SIZE, INTERVAL, 0x00, DBVAL(INTERVAL), DBVAL(INTERVAL), DBVAL(0)), - VIDEO_VS_DESCRIPTOR_INIT(0x01, 0x01, 0x01), - /* 1.2.2.2 Standard VideoStream Isochronous Video Data Endpoint Descriptor */ - 0x07, /* bLength */ - USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType: ENDPOINT */ - 0x81, /* bEndpointAddress: IN endpoint 2 */ - 0x01, /* bmAttributes: Isochronous transfer type. Asynchronous synchronization type. */ - WBVAL(VIDEO_PACKET_SIZE), /* wMaxPacketSize */ - 0x01, /* bInterval: One frame interval */ - - /////////////////////////////////////// - /// string0 descriptor - /////////////////////////////////////// - USB_LANGID_INIT(USBD_LANGID_STRING), - /////////////////////////////////////// - /// string1 descriptor - /////////////////////////////////////// - 0x12, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'B', 0x00, /* wcChar0 */ - 'o', 0x00, /* wcChar1 */ - 'u', 0x00, /* wcChar2 */ - 'f', 0x00, /* wcChar3 */ - 'f', 0x00, /* wcChar4 */ - 'a', 0x00, /* wcChar5 */ - 'l', 0x00, /* wcChar6 */ - 'o', 0x00, /* wcChar7 */ - /////////////////////////////////////// - /// string2 descriptor - /////////////////////////////////////// - 0x28, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'B', 0x00, /* wcChar0 */ - 'o', 0x00, /* wcChar1 */ - 'u', 0x00, /* wcChar2 */ - 'f', 0x00, /* wcChar3 */ - 'f', 0x00, /* wcChar4 */ - 'a', 0x00, /* wcChar5 */ - 'l', 0x00, /* wcChar6 */ - 'o', 0x00, /* wcChar7 */ - ' ', 0x00, /* wcChar8 */ - 'V', 0x00, /* wcChar9 */ - 'E', 0x00, /* wcChar10 */ - 'D', 0x00, /* wcChar11 */ - 'I', 0x00, /* wcChar12 */ - 'O', 0x00, /* wcChar13 */ - ' ', 0x00, /* wcChar14 */ - 'D', 0x00, /* wcChar15 */ - 'E', 0x00, /* wcChar16 */ - 'M', 0x00, /* wcChar17 */ - 'O', 0x00, /* wcChar18 */ - /////////////////////////////////////// - /// string3 descriptor - /////////////////////////////////////// - 0x16, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - '2', 0x00, /* wcChar0 */ - '0', 0x00, /* wcChar1 */ - '2', 0x00, /* wcChar2 */ - '1', 0x00, /* wcChar3 */ - '0', 0x00, /* wcChar4 */ - '3', 0x00, /* wcChar5 */ - '1', 0x00, /* wcChar6 */ - '0', 0x00, /* wcChar7 */ - '0', 0x00, /* wcChar8 */ - '0', 0x00, /* wcChar9 */ -#ifdef CONFIG_USB_HS - /////////////////////////////////////// - /// device qualifier descriptor - /////////////////////////////////////// - 0x0a, - USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, - 0x00, - 0x02, - 0x00, - 0x00, - 0x00, - 0x40, - 0x01, - 0x00, -#endif - 0x00 -}; - -static usbd_class_t video_class; -static usbd_interface_t video_control_intf; -static usbd_interface_t video_stream_intf; -#if defined NO_PSRAM_HEAP -#define CUSTOMER_SECTION __attribute__((section(".custom_psram_bss"))) -static uint8_t usb_buffer[USB_MAX_BUFFER] CUSTOMER_SECTION; -static uint8_t mjpeg_swap_buffer[PER_FRAME_MJPEG] CUSTOMER_SECTION; -#else -static uint8_t *usb_buffer = NULL; -static uint8_t *mjpeg_swap_buffer = NULL; -#endif -static uint32_t mjpeg_start_addr, mjpeg_buffer_size; -SemaphoreHandle_t usb_cam_semap = NULL; - -void usbd_video_iso_callback(uint8_t ep) -{ - BaseType_t xHigherPriorityTaskWoken = pdFALSE; - if (usb_cam_semap) { - xSemaphoreGiveFromISR(usb_cam_semap, &xHigherPriorityTaskWoken); - portYIELD_FROM_ISR(xHigherPriorityTaskWoken); - } -} - -static usbd_endpoint_t video_in_ep = { - .ep_cb = usbd_video_iso_callback, - .ep_addr = VIDEO_IN_EP -}; - -volatile bool tx_flag = 0; - -void usbd_video_open(uint8_t intf) -{ - tx_flag = 1; - printf("OPEN\r\n"); -} -void usbd_video_close(uint8_t intf) -{ - printf("CLOSE\r\n"); - tx_flag = 0; -} - -static void bl_usb_clock_init(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1); - tmpVal |= (1 << 13); - BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal); - GLB_Set_USB_CLK_From_WIFIPLL(1); -} - -int bl_usb_cam_init(void) -{ - int ret = 0; - - ret = bl_cam_mjpeg_buffer_info_get(&mjpeg_start_addr, &mjpeg_buffer_size); - if (ret != 0) { - printf("mjpeg not init\r\n"); - goto exit; - } - - usb_cam_semap = xSemaphoreCreateBinary(); - if (NULL == usb_cam_semap) { - printf("create usb_cam_semap fail\r\n"); - ret = -1; - goto exit; - } - -#ifndef NO_PSRAM_HEAP - usb_buffer = pvPortMalloc(USB_MAX_BUFFER); - if (NULL == usb_buffer) { - printf("malloc usb_buffer fail!\r\n"); - vSemaphoreDelete(usb_cam_semap); - usb_cam_semap = NULL; - ret = -1; - goto exit; - } - - mjpeg_swap_buffer = pvPortMalloc(PER_FRAME_MJPEG); - if (NULL == mjpeg_swap_buffer) { - printf("malloc mjpeg_swap_buffer fail!\r\n"); - vPortFree(usb_buffer); - usb_buffer = NULL; - vSemaphoreDelete(usb_cam_semap); - usb_cam_semap = NULL; - ret = -1; - goto exit; - } -#endif - bl_usb_clock_init(); - usbd_desc_register(video_descriptor); - usbd_video_add_interface(&video_class, &video_control_intf); - usbd_video_add_interface(&video_class, &video_stream_intf); - usbd_interface_add_endpoint(&video_stream_intf, &video_in_ep); - - usbd_video_probe_and_commit_controls_init(CAM_FPS, MAX_FRAME_SIZE, MAX_PAYLOAD_SIZE); - usbd_initialize(); - - xSemaphoreGive(usb_cam_semap); -exit: - return ret; -} - -int bl_usb_cam_transfer(void) -{ - int ret = 0; - uint8_t *pic, *usb_ptr; - uint32_t len, first_len, second_len, out_len; - - if (tx_flag) { - ret = bl_cam_mjpeg_get(&pic, &len); - if (ret == 0) { - if (((uint32_t)(uintptr_t)pic + len) > (mjpeg_start_addr + mjpeg_buffer_size)) { - /* if mjpeg store edge loop to start*/ - first_len = mjpeg_start_addr + mjpeg_buffer_size - (uint32_t)(uintptr_t)pic; - second_len = len - first_len; - csi_dcache_invalid_range((void *)pic, first_len); - memcpy(mjpeg_swap_buffer, pic, first_len); - csi_dcache_invalid_range((void *)mjpeg_start_addr, second_len); - memcpy(mjpeg_swap_buffer + first_len, (void *)mjpeg_start_addr, second_len); - usb_ptr = mjpeg_swap_buffer; - } else { - /*mjpeg data not cut*/ - usb_ptr = pic; - csi_dcache_invalid_range((void *)usb_ptr, len); - } - - if (NULL == usb_cam_semap) { - ret = -1; - goto exit; - } - if (len > USB_MAX_BUFFER) { - ret = -1; - printf("jpeg frame size is out of %dbytes\r\n", USB_MAX_BUFFER); - goto exit; - } - xSemaphoreTake(usb_cam_semap, portMAX_DELAY); - /*fill mjpeg in usb data struct*/ - usbd_video_mjpeg_payload_fill(usb_ptr, len, usb_buffer, &out_len); - bl_cam_mjpeg_pop(); - - /* send usb data async*/ - usbd_ep_write_async(VIDEO_IN_EP, usb_buffer, out_len); - } - } - -exit: - return ret; -} - diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_usb_cam.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_usb_cam.h deleted file mode 100644 index d03df4ae90..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_usb_cam.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __BL_USB_CAM_H__ -#define __BL_USB_CAM_H__ -#include -int bl_usb_cam_init(void); -int bl_usb_cam_transfer(void); -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_wifi.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_wifi.c deleted file mode 100644 index 1e031ae52a..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_wifi.c +++ /dev/null @@ -1,255 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include -#include - -//FIXME no BL808/BL606p header file including is Allowed here -#ifdef BL808 -#include -#include -#elif defined(BL606P) -#include -#include -#else -#error "Use CHIP BL808/BL606P for this module" -#endif - -#include "bl_wifi.h" -#include "bl_irq.h" - -typedef struct _bl_wifi_env { - uint8_t sta_mac_addr_board[6]; - uint8_t sta_mac_addr_usr[6]; - uint8_t ap_mac_addr_board[6]; - uint8_t ap_mac_addr_usr[6]; - uint8_t country_code; - - bl_wifi_ap_info_t ap_info; - uint8_t ap_info_en; - - bl_wifi_ap_info_t sta_info; - uint8_t sta_info_en; -} bl_wifi_env_t; - -bl_wifi_env_t wifi_env = { - .sta_mac_addr_board = {0x18, 0xb9, 0x05, 0x88, 0x88, 0x88} -}; - - -/****************************************************************************/ /** - * @brief set wifi core clock divider - * - * @param clkDiv: divider - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -/* 0x3B0 : wifi_cfg0 */ -#define GLB_WIFI_CFG0_OFFSET (0x3B0) -#define GLB_WIFI_MAC_CORE_DIV GLB_WIFI_MAC_CORE_DIV -#define GLB_WIFI_MAC_CORE_DIV_POS (0U) -#define GLB_WIFI_MAC_CORE_DIV_LEN (4U) -#define GLB_WIFI_MAC_CORE_DIV_MSK (((1U<hwaddr[0] = 0x18; - netif->hwaddr[1] = 0xB9; - netif->hwaddr[2] = 0x05; - netif->hwaddr[3] = 0x88; - netif->hwaddr[4] = 0x88; - netif->hwaddr[5] = 0x88; - - /* - netif_add(struct netif *netif, struct ip_addr *ipaddr, - * struct ip_addr *netmask, struct ip_addr *gw, - * void *state, err_t (* init)(struct netif *netif), - * err_t (* input)(struct pbuf *p, struct netif *netif)) - * - * Adds your network interface to the netif_list. Allocate a struct - * netif and pass a pointer to this structure as the first argument. - * Give pointers to cleared ip_addr structures when using DHCP, - * or fill them with sane numbers otherwise. The state pointer may be NULL. - * - * The init function pointer must point to a initialization function for - * your ethernet netif interface. The following code illustrates it's use.*/ - - netif_add(netif, &ipaddr, &netmask, &gw, NULL, &bl606a0_wifi_netif_init, &tcpip_input); - netif->name[0] = 's'; - netif->name[1] = 't'; - netif->flags |= NETIF_FLAG_LINK_UP; - netif_set_default(netif); - netif_set_up(netif); - netifapi_dhcp_start(netif); - - return 0; -} -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_wifi.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_wifi.h deleted file mode 100644 index 17c3b4a45d..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_wifi.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __BL_WIFI_H__ -#define __BL_WIFI_H__ -typedef struct bl_wifi_ap_info { - uint8_t ssid[33]; - uint8_t psk[65]; - uint8_t chan; -} bl_wifi_ap_info_t; - - -int bl_wifi_enable_irq(void); -int bl_wifi_clock_enable(void); -int bl_wifi_sta_mac_addr_set(uint8_t mac[6]); -int bl_wifi_ap_mac_addr_set(uint8_t mac[6]); -int bl_wifi_mac_addr_set(uint8_t mac[6]); -int bl_wifi_country_code_set(uint8_t country_code); -int bl_wifi_ap_info_set(uint8_t* ssid, uint8_t ssid_len, - uint8_t* psk, uint8_t psk_len, - uint8_t chan); -int bl_wifi_mac_addr_get(uint8_t mac[6]); -int bl_wifi_ap_info_get(bl_wifi_ap_info_t* ap_info); -int bl_wifi_sta_info_set(uint8_t* ssid, uint8_t ssid_len, uint8_t* psk, uint8_t psk_len, int autoconnect); -int bl_wifi_sta_info_get(bl_wifi_ap_info_t* sta_info); -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/emac_phy.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/emac_phy.c deleted file mode 100644 index 9cbe9791d1..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/emac_phy.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "phy_8720.c" diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/ethernet_phy.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/ethernet_phy.h deleted file mode 100644 index a155e1e0de..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/ethernet_phy.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __ETHERNET_PHY_H__ -#define __ETHERNET_PHY_H__ - -#include "hal_emac.h" - -typedef enum emac_phy_status { - EMAC_PHY_STAT_EEROR, - EMAC_PHY_STAT_LINK_DOWN, - EMAC_PHY_STAT_LINK_INIT, - EMAC_PHY_STAT_LINK_UP, - EMAC_PHY_STAT_100MBITS_FULLDUPLEX, - EMAC_PHY_STAT_100MBITS_HALFDUPLEX, - EMAC_PHY_STAT_10MBITS_FULLDUPLEX, - EMAC_PHY_STAT_10MBITS_HALFDUPLEX, -} emac_phy_status_t; - -emac_phy_status_t ethernet_phy_status_get(); -int emac_phy_init(emac_phy_cfg_t *cfg); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/ethernetif.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/ethernetif.c deleted file mode 100644 index c2135e56f5..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/ethernetif.c +++ /dev/null @@ -1,574 +0,0 @@ -/* - * Copyright (c) 2020 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* Includes ------------------------------------------------------------------*/ -#include "lwip/opt.h" -#include "lwip/timeouts.h" -#include "lwip/netif.h" -#define LWIP_DHCP 0 -#if LWIP_DHCP -#include "lwip/dhcp.h" -#endif -#include "netif/etharp.h" -#include "ethernetif.h" -#include -#include "hal_emac.h" -#include -#include "semphr.h" -#include "bflb_platform.h" -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Network interface name */ -#define IFNAME0 'b' -#define IFNAME1 'l' - -#define ETH_DMA_TRANSMIT_TIMEOUT (20U) - -#define BL702_EMAC 0 -#define EMAC_OUTPUT BL702_EMAC - -#if LWIP_DHCP -#define MAX_DHCP_TRIES 4 -uint32_t DHCPfineTimer = 0; -uint8_t DHCP_state = DHCP_OFF; -#else -/*Static IP ADDRESS: IP_ADDR0.IP_ADDR1.IP_ADDR2.IP_ADDR3 */ -#define IP_ADDR0 (uint8_t)10 -#define IP_ADDR1 (uint8_t)28 -#define IP_ADDR2 (uint8_t)30 -#define IP_ADDR3 (uint8_t)221 - -/*NETMASK*/ -#define NETMASK_ADDR0 (uint8_t)255 -#define NETMASK_ADDR1 (uint8_t)255 -#define NETMASK_ADDR2 (uint8_t)255 -#define NETMASK_ADDR3 (uint8_t)0 - -/*Gateway Address*/ -#define GW_ADDR0 (uint8_t)10 -#define GW_ADDR1 (uint8_t)28 -#define GW_ADDR2 (uint8_t)30 -#define GW_ADDR3 (uint8_t)1 -#endif - -/* Private function prototypes -----------------------------------------------*/ -void pbuf_free_custom(struct pbuf *p); -void ethernetif_input(void *argument); -SemaphoreHandle_t emac_rx_sem = NULL; -static StackType_t emac_rx_stack[256]; -static StaticTask_t emac_rx_handle; -#if LWIP_DHCP -static StackType_t emac_dhcp_stack[256]; -static StaticTask_t emac_dhcp_handle; -#endif -static uint8_t emac_rx_buffer[ETH_RX_BUFFER_SIZE] __attribute__((aligned(16))) = { 0 }; - -LWIP_MEMPOOL_DECLARE(RX_POOL, 10, sizeof(struct pbuf_custom), "Zero-copy RX PBUF pool"); - -/* Private functions ---------------------------------------------------------*/ -/******************************************************************************* - LL Driver Interface ( LwIP stack --> ETH) -*******************************************************************************/ -/** - * @brief In this function, the hardware should be initialized. - * Called from ethernetif_init(). - * - * @param netif the already initialized lwip network interface structure - * for this ethernetif - */ -extern void emac_init_txrx_buffer(void); -extern int emac_phy_init(emac_phy_cfg_t *cfg); - -/* For emac tx and rx,we put here to make controlling it's size easy */ -#define ETH_RXBUFNB 5 -#define ETH_TXBUFNB 5 -#define ATTR_NOCACHE_RAM_SECTION __attribute__((section(".nocache_ram"))) -ATTR_NOCACHE_RAM_SECTION ATTR_EALIGN(4) uint8_t ethRxBuff[ETH_RXBUFNB][ETH_RX_BUFFER_SIZE] ATTR_EALIGN(4) = { 0 }; /* Ethernet Receive Buffers */ -ATTR_NOCACHE_RAM_SECTION ATTR_EALIGN(4) uint8_t ethTxBuff[ETH_TXBUFNB][ETH_TX_BUFFER_SIZE] ATTR_EALIGN(4); /* Ethernet Transmit Buffers */ -void emac_init_txrx_buffer(void) -{ - emac_bd_init((uint8_t *)ethTxBuff, ETH_TXBUFNB, (uint8_t *)ethRxBuff, ETH_RXBUFNB); - -} -void dhcp_thread(void const *argument); -void low_level_init(struct netif *netif) -{ - int ret = 0; - - emac_device_t emac_cfg = { - .mac_addr[0] = 0x18, - .mac_addr[1] = 0xB9, - .mac_addr[2] = 0x05, - .mac_addr[3] = 0x12, - .mac_addr[4] = 0x34, - .mac_addr[5] = 0x56, - }; - - /* set phy cfg */ - emac_phy_cfg_t phy_cfg = { - .auto_negotiation = 1, /*!< Speed and mode auto negotiation */ - .full_duplex = 0, /*!< Duplex mode */ - .speed = 0, /*!< Speed mode */ - .phy_address = 1, /*!< PHY address */ - .phy_id = 0x7c0f0, /*!< PHY OUI, masked */ - .phy_state = PHY_STATE_DOWN, - }; - - /* set MAC hardware address length */ - netif->hwaddr_len = ETH_HWADDR_LEN; - - /* set MAC hardware address */ - netif->hwaddr[0] = emac_cfg.mac_addr[0]; - netif->hwaddr[1] = emac_cfg.mac_addr[1]; - netif->hwaddr[2] = emac_cfg.mac_addr[2]; - netif->hwaddr[3] = emac_cfg.mac_addr[3]; - netif->hwaddr[4] = emac_cfg.mac_addr[4]; - netif->hwaddr[5] = emac_cfg.mac_addr[5]; - - /* maximum transfer unit */ - netif->mtu = 1500; - - /* emac init,configure ethernet peripheral (GPIOs, clocks, MAC, DMA) */ - MSG("emac_init\r\n"); - emac_init(&emac_cfg); - - ret = emac_phy_init(&phy_cfg); - if (PHY_STATE_UP == phy_cfg.phy_state) { - MSG("PHY[%x] @%d ready on %dMbps, %s duplex\n\r", (int)phy_cfg.phy_id, (int)phy_cfg.phy_address, - (int)phy_cfg.speed, - phy_cfg.full_duplex ? "full" : "half"); - } else { - MSG("PHY Init fail\n\r"); - BL_CASE_FAIL; - while (1) - ; - } - emac_init_txrx_buffer(); - emac_start(); - // emac_start_tx(); - - /* device capabilities */ - /* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */ - netif->flags |= NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP; - - /* Initialize the RX POOL */ - LWIP_MEMPOOL_INIT(RX_POOL); - - /* create a binary semaphore used for informing ethernetif of frame reception */ - //vSemaphoreCreateBinary(emac_rx_sem); - emac_rx_sem = xSemaphoreCreateBinary(); - - /* create the task that handles the ETH_MAC */ - MSG("[OS] Starting emac rx task...\r\n"); - xTaskCreateStatic(ethernetif_input, (char *)"emac_rx_task", sizeof(emac_rx_stack) / 4, netif, 16, emac_rx_stack, &emac_rx_handle); -#if LWIP_DHCP - MSG("[OS] Starting emac dhcp task...\r\n"); - xTaskCreateStatic(dhcp_thread, (char *)"emac_dhcp_task", sizeof(emac_dhcp_stack) / 4, netif, 16, emac_dhcp_stack, &emac_dhcp_handle); -#endif - - if (ret == 0) { - MSG("[OS] %s Netif is up\r\n", netif->name); - netif_set_up(netif); - netif_set_link_up(netif); - } -} - -void emac_tx_error_callback_app() -{ - MSG("EMAC tx error callback\r\n"); -} - -void emac_rx_error_callback_app() -{ - MSG("EMAC rx error callback\r\n"); - // MSG("EMAC tx bd num 0x%x\r\n", BL_RD_WORD(0x4000D020)); - // MSG("EMAC rx bd description0 0x%x\r\n", BL_RD_WORD(0x4000D400 + ((5 + 5) * 8))); - // MSG("EMAC rx bd description1 0x%x\r\n", BL_RD_WORD(0x4000D400 + ((5 + 5) * 8) + 0x4)); -} -/** - * @brief This function should do the actual transmission of the packet. The packet is - * contained in the pbuf that is passed to the function. This pbuf - * might be chained. - * - * @param netif the lwip network interface structure for this ethernetif - * @param p the MAC packet to send (e.g. IP packet including MAC addresses and type) - * @return ERR_OK if the packet could be sent - * an err_t value if the packet couldn't be sent - * - * @note Returning ERR_MEM here if a DMA queue of your MAC is full can lead to - * strange results. You might consider waiting for space in the DMA queue - * to become available since the stack doesn't retry to send a packet - * dropped because of memory failure (except for the TCP timers). - */ - -static unsigned char emac_send_buf[1514]; -static err_t low_level_output(struct netif *netif, struct pbuf *p) -{ - err_t errval = ERR_OK; - struct pbuf *q; - - if (!emac_bd_fragment_support()){ - - uint32_t byteslefttocopy = 0; - // uint32_t payloadoffset = 0; - // uint32_t bufferoffset = 0; - uint32_t framelength = 0; - uint32_t flags = (EMAC_NORMAL_PACKET); - - for (q = p; q != NULL; q = q->next) { - // MSG("p->tot_len:%d,q->len:%d, q->next:%d,f:%d\r\n", q->tot_len, q->len, q->next, framelength); - - byteslefttocopy = q->len; - // payloadoffset = 0; - - // check is copy data is larger than emac tx buf - while ((byteslefttocopy + framelength) > ETH_TX_BUFFER_SIZE) { - // copy data to tx buf - MSG("tx buf is too larger!\r\n"); - flags = EMAC_FRAGMENT_PACKET; - // ARCH_MemCpy_Fast(&emac_send_buf[framelength + bufferoffset], q->payload + payloadoffset, (ETH_TX_BUFFER_SIZE - bufferoffset)); - } - ARCH_MemCpy_Fast(&emac_send_buf[framelength], q->payload, byteslefttocopy); - // bufferoffset = bufferoffset + byteslefttocopy; - framelength = framelength + byteslefttocopy; - } - - if (0 != emac_bd_tx_enqueue(flags, framelength, emac_send_buf)) { - MSG("emac_bd_tx_enqueue error!\r\n"); - return ERR_IF; - } - - }else{ - for (q = p; q != NULL; q = q->next) { - //MSG("p->tot_len:%d,q->len:%d, q->next:%d\r\n", q->tot_len, q->len, q->next); - if (q->len == q->tot_len) { - if (0 != emac_bd_tx_enqueue(EMAC_NORMAL_PACKET, q->len, q->payload)) { - MSG("emac_bd_tx_enqueue error!\r\n"); - return ERR_IF; - } - } else if (q->len < q->tot_len) { - if (0 != emac_bd_tx_enqueue(EMAC_FRAGMENT_PACKET, q->len, q->payload)) { - MSG("emac_bd_tx_enqueue error!\r\n"); - return ERR_IF; - } - } else { - MSG("low_level_output error! Wrong packet!\r\n"); - } - } - } - - return errval; -} - -/** - * @brief Should allocate a pbuf and transfer the bytes of the incoming - * packet from the interface into the pbuf. - * - * @param netif the lwip network interface structure for this ethernetif - * @return a pbuf filled with the received packet (including MAC header) - * NULL on memory error - */ -static struct pbuf *low_level_input(struct netif *netif) -{ - uint32_t rx_len = 0; - struct pbuf *p = NULL, *q; - - emac_bd_rx_dequeue(-1, &rx_len, emac_rx_buffer); - - if (rx_len <= 0) { - //MSG("Recv Null Data\r\n"); - return NULL; - } - - //MSG("Recv full Data\r\n"); - - p = pbuf_alloc(PBUF_RAW, rx_len, PBUF_POOL); - - if (p != NULL) { - for (q = p; q != NULL; q = q->next) { - memcpy(q->payload, emac_rx_buffer + rx_len - q->tot_len, q->len); - } - } - - return p; -} - -void emac_rx_done_callback_app(void) -{ - BaseType_t xHigherPriorityTaskWoken; - - /* Is it time for vATask() to run? */ - xHigherPriorityTaskWoken = pdFALSE; - //MSG("emac_rx_done_callback_app\r\n"); - //low_level_input(NULL); - xSemaphoreGiveFromISR(emac_rx_sem, &xHigherPriorityTaskWoken); - /* If xHigherPriorityTaskWoken was set to true you - we should yield. The actual macro used here is - port specific. */ - portYIELD_FROM_ISR(xHigherPriorityTaskWoken); -} -/** - * @brief This function is the ethernetif_input task, it is processed when a packet - * is ready to be read from the interface. It uses the function low_level_input() - * that should handle the actual reception of bytes from the network - * interface. Then the type of the received packet is determined and - * the appropriate input function is called. - * - * @param netif the lwip network interface structure for this ethernetif - */ -void ethernetif_input(void *argument) -{ - struct pbuf *p = NULL; - struct netif *netif = (struct netif *)argument; - - for (;;) { - if (xSemaphoreTake(emac_rx_sem, portMAX_DELAY) == pdTRUE) { - do { - //MSG("ethernetif_input\r\n"); - p = low_level_input(netif); - - if (p != NULL) { - if (netif->input(p, netif) != ERR_OK) { - pbuf_free(p); - } - } - } while (p != NULL); - } - } -} - -/** - * @brief Should be called at the beginning of the program to set up the - * network interface. It calls the function low_level_init() to do the - * actual setup of the hardware. - * - * This function should be passed as a parameter to netif_add(). - * - * @param netif the lwip network interface structure for this ethernetif - * @return ERR_OK if the loopif is initialized - * ERR_MEM if private data couldn't be allocated - * any other err_t on error - */ -err_t ethernetif_init(struct netif *netif) -{ - LWIP_ASSERT("netif != NULL", (netif != NULL)); - -#if LWIP_NETIF_HOSTNAME - /* Initialize interface hostname */ - netif->hostname = "lwip"; -#endif /* LWIP_NETIF_HOSTNAME */ - - netif->name[0] = IFNAME0; - netif->name[1] = IFNAME1; - /* We directly use etharp_output() here to save a function call. - * You can instead declare your own function an call etharp_output() - * from it if you have to do some checks before sending (e.g. if link - * is available...) */ - netif->output = etharp_output; - netif->linkoutput = low_level_output; - - /* initialize the hardware */ - low_level_init(netif); - - return ERR_OK; -} - -/** - * @brief Custom Rx pbuf free callback - * @param pbuf: pbuf to be freed - * @retval None - */ -void pbuf_free_custom(struct pbuf *p) -{ - struct pbuf_custom *custom_pbuf = (struct pbuf_custom *)p; - LWIP_MEMPOOL_FREE(RX_POOL, custom_pbuf); -} - -static void ethernet_set_static_ip(struct netif *netif) -{ - ip_addr_t ipaddr; - ip_addr_t netmask; - ip_addr_t gw; - - IP4_ADDR(&ipaddr, IP_ADDR0, IP_ADDR1, IP_ADDR2, IP_ADDR3); - IP4_ADDR(&netmask, NETMASK_ADDR0, NETMASK_ADDR1, NETMASK_ADDR2, NETMASK_ADDR3); - IP4_ADDR(&gw, GW_ADDR0, GW_ADDR1, GW_ADDR2, GW_ADDR3); - netif_set_addr(netif, ip_2_ip4(&ipaddr), ip_2_ip4(&netmask), ip_2_ip4(&gw)); -} - -/** - * @brief Notify the User about the network interface config status - * @param netif: the network interface - * @retval None - */ -void ethernet_link_status_updated(struct netif *netif) -{ - if (netif_is_link_up(netif)) { -#if LWIP_DHCP - /* Update DHCP state machine */ - DHCP_state = DHCP_START; - MSG("DHCP Start\n"); -#else - /* IP address default setting */ - ethernet_set_static_ip(netif); - uint8_t iptxt[20]; - sprintf((char *)iptxt, "%s", ip4addr_ntoa(netif_ip4_addr(netif))); - MSG("Static IP address: %s\n", iptxt); -#endif - } else { -#if LWIP_DHCP - /* Update DHCP state machine */ - DHCP_state = DHCP_LINK_DOWN; -#else - MSG("The network cable is not connected \n"); -#endif /* LWIP_DHCP */ - } -} - -/** - * @brief - * @retval None - */ -void ethernet_link_check_state(struct netif *netif) -{ - emac_phy_status_t phy_state; - - uint32_t linkchanged = 0; - // uint32_t speed = 0, duplex = 0; - - phy_state = ethernet_phy_status_get(); - - if (netif_is_link_up(netif) && (phy_state <= EMAC_PHY_STAT_LINK_DOWN)) { - MSG("Link Down\n"); - emac_stop(); - netif_set_down(netif); - netif_set_link_down(netif); - } else if (!netif_is_link_up(netif) && (phy_state <= EMAC_PHY_STAT_LINK_DOWN)) { - MSG("Reinit\n"); - emac_phy_init(NULL); - } else if (!netif_is_link_up(netif) && (phy_state > EMAC_PHY_STAT_LINK_UP)) { - // switch (phy_state) { - // case EMAC_PHY_STAT_100MBITS_FULLDUPLEX: - // duplex = 1; - // speed = 100; - // linkchanged = 1; - // break; - - // case EMAC_PHY_STAT_100MBITS_HALFDUPLEX: - // duplex = 0; - // speed = 100; - // linkchanged = 1; - // break; - - // case EMAC_PHY_STAT_10MBITS_FULLDUPLEX: - // duplex = 1; - // speed = 10; - // linkchanged = 1; - // break; - - // case EMAC_PHY_STAT_10MBITS_HALFDUPLEX: - // duplex = 0; - // speed = 10; - // linkchanged = 1; - // break; - - // default: - // break; - // } - - if (linkchanged) { - /* Get MAC Config MAC */ - //HAL_ETH_GetMACConfig(&EthHandle, &MACConf); - //MACConf.DuplexMode = duplex; - //MACConf.Speed = speed; - //HAL_ETH_SetMACConfig(&EthHandle, &MACConf); - //HAL_ETH_Start(&EthHandle); - netif_set_up(netif); - netif_set_link_up(netif); - } - } -} - -#if LWIP_DHCP -/** - * @brief DHCP Process - * @param argument: network interface - * @retval None - */ -void dhcp_thread(void const *argument) -{ - struct netif *netif = (struct netif *)argument; - ip_addr_t ipaddr; - ip_addr_t netmask; - ip_addr_t gw; - struct dhcp *dhcp; - uint8_t iptxt[20]; - - for (;;) { - switch (DHCP_state) { - case DHCP_START: { - ip_addr_set_zero_ip4(&netif->ip_addr); - ip_addr_set_zero_ip4(&netif->netmask); - ip_addr_set_zero_ip4(&netif->gw); - DHCP_state = DHCP_WAIT_ADDRESS; - MSG(" State: Looking for DHCP server ...\n"); - dhcp_start(netif); - } break; - case DHCP_WAIT_ADDRESS: { - if (dhcp_supplied_address(netif)) { - DHCP_state = DHCP_ADDRESS_ASSIGNED; - sprintf((char *)iptxt, "%s", ip4addr_ntoa(netif_ip4_addr(netif))); - MSG("IP address assigned by a DHCP server: %s\n", iptxt); - } else { - dhcp = (struct dhcp *)netif_get_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_DHCP); - - /* DHCP timeout */ - if (dhcp->tries > MAX_DHCP_TRIES) { - DHCP_state = DHCP_TIMEOUT; - - /* Static address used */ - ethernet_set_static_ip(netif); - sprintf((char *)iptxt, "%s", ip4addr_ntoa(netif_ip4_addr(netif))); - MSG("DHCP Timeout !! \n"); - MSG("Static IP address: %s\n", iptxt); - } - } - } break; - case DHCP_LINK_DOWN: { - DHCP_state = DHCP_OFF; - MSG("The network cable is not connected \n"); - } break; - default: - break; - } - vTaskDelay(100); - } -} -#endif /* LWIP_DHCP */ diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/ethernetif.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/ethernetif.h deleted file mode 100644 index 8b21d0b9eb..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/ethernetif.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) 2020 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __ETHERNETIF_H__ -#define __ETHERNETIF_H__ - -#include "lwip/err.h" -#include "lwip/netif.h" -#include "ethernet_phy.h" - -#define DHCP_OFF (uint8_t)0 -#define DHCP_START (uint8_t)1 -#define DHCP_WAIT_ADDRESS (uint8_t)2 -#define DHCP_ADDRESS_ASSIGNED (uint8_t)3 -#define DHCP_TIMEOUT (uint8_t)4 -#define DHCP_LINK_DOWN (uint8_t)5 - -/* Exported types ------------------------------------------------------------*/ -err_t ethernetif_init(struct netif *netif); -void ethernet_link_check_state(struct netif *netif); -void ethernet_link_status_updated(struct netif *netif); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_board.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_board.c deleted file mode 100644 index 5640d84252..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_board.c +++ /dev/null @@ -1,1273 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include -#include -#include -#include -#include - -#include - -#include -BLOG_DECLARE(dts); -#include - -#define USER_UNUSED(a) ((void)(a)) - -#define BL_FDT32_TO_U8(addr, byte_offset) ((uint8_t)fdt32_to_cpu(*(uint32_t *)((uint8_t *)addr + byte_offset))) -#define BL_FDT32_TO_U16(addr, byte_offset) ((uint16_t)fdt32_to_cpu(*(uint32_t *)((uint8_t *)addr + byte_offset))) -#define BL_FDT32_TO_U32(addr, byte_offset) ((uint32_t)fdt32_to_cpu(*(uint32_t *)((uint8_t *)addr + byte_offset))) - -static uint32_t factory_addr = 0; - -//#ifndef FEATURE_WIFI_DISABLE -//#include -//#include - -#ifdef CFG_BLE_ENABLE -#include "ble_lib_api.h" -#endif -static int update_mac_config_get_mac_from_dtb(const void *fdt, int offset1, uint8_t mac_addr[6]) -{ - int lentmp; - const uint8_t *addr_prop = 0; - - /* set sta_mac_addr ap_mac_addr */ - addr_prop = fdt_getprop(fdt, offset1, "sta_mac_addr", &lentmp); - if (6 == lentmp) { - - memcpy(mac_addr, addr_prop, 6); - blog_info("sta_mac_addr :\r\n"); - blog_buf(mac_addr, 6); - - bl_wifi_sta_mac_addr_set(mac_addr); - } else { - blog_error("sta_mac_addr NULL.\r\n"); - return -1; - } - - addr_prop = fdt_getprop(fdt, offset1, "ap_mac_addr", &lentmp); - if (6 == lentmp) { - - memcpy(mac_addr, addr_prop, 6); - blog_info("ap_mac_addr :\r\n"); - blog_buf(mac_addr, 6); - - bl_wifi_ap_mac_addr_set(mac_addr); - } else { - blog_error("ap_mac_addr NULL.\r\n"); - return -1; - } - blog_info("return 0000 \r\n"); - - return 0; -} - -static int update_mac_config_get_mac_from_efuse(uint8_t mac_addr[6]) -{ - uint8_t result_or, result_and; - - bl_efuse_read_mac(mac_addr); - result_or = mac_addr[0] | mac_addr[1] | mac_addr[2] | mac_addr[3] | mac_addr[4] | mac_addr[5]; - result_and = mac_addr[0] & mac_addr[1] & mac_addr[2] & mac_addr[3] & mac_addr[4] & mac_addr[5]; - - if (0 == result_or || 1 == result_and) { - /*all zero or one found in efuse*/ - return -1; - } - return 0; -} - -static int update_mac_config_get_mac_from_factory(uint8_t mac_addr[6]) -{ - uint8_t result_or, result_and; - - if (bl_efuse_read_mac_factory(mac_addr)) { - return -1; - } - result_or = mac_addr[0] | mac_addr[1] | mac_addr[2] | mac_addr[3] | mac_addr[4] | mac_addr[5]; - result_and = mac_addr[0] & mac_addr[1] & mac_addr[2] & mac_addr[3] & mac_addr[4] & mac_addr[5]; - if (0 == result_or || 1 == result_and) { - /*all zero or one found in efuse*/ - return -1; - } - return 0; -} - -/* - * Update MAC address according to order string - * BFM: - * 'B' for EFUSE built-in MAC address - * 'F' for Flash built-in MAC address - * 'M' for manufacutre configured EFUSE built-in MAC address - * */ -#define MAC_ORDER_ADDR_LEN_MAX (3) -static void update_mac_config_with_order(const void *fdt, int offset1, const char *order) -{ - int i, set, len; - uint8_t mac_addr[6]; - static const uint8_t mac_default[] = {0x18, 0xB9, 0x05, 0x88, 0x88, 0x88}; - - set = 0; - len = strlen(order); - for (i = 0; i < MAC_ORDER_ADDR_LEN_MAX && i < len; i++) { - switch (order[i]) { - case 'B': - { - if (0 == update_mac_config_get_mac_from_efuse(mac_addr)) { - set = 1; - blog_info("get MAC from B ready\r\n"); - goto break_scan; - } else { - blog_info("get MAC from B failed\r\n"); - } - } - break; - case 'F': - { - if (0 == update_mac_config_get_mac_from_dtb(fdt, offset1, mac_addr)) { - set = 1; - printf("get MAC from F ready\r\n"); - goto break_scan; - } else { - printf("get MAC from F failed\r\n"); - } - } - break; - case 'M': - { - if (0 == update_mac_config_get_mac_from_factory(mac_addr)) { - set = 1; - blog_info("get MAC from M ready\r\n"); - goto break_scan; - } else { - blog_info("get MAC from M failed\r\n"); - } - } - break; - default: - { - BL_ASSERT(0); - } - } - } -break_scan: - if (0 == set) { - blog_info("Using Default MAC address\r\n"); - memcpy(mac_addr, mac_default, 6); - } - //FIXME maybe we should set a different MAC address - blog_info("Set MAC addrress %02X:%02X:%02X:%02X:%02X:%02X\r\n", - mac_addr[0], - mac_addr[1], - mac_addr[2], - mac_addr[3], - mac_addr[4], - mac_addr[5] - ); - bl_wifi_ap_mac_addr_set(mac_addr); - bl_wifi_sta_mac_addr_set(mac_addr); -} - -static void update_mac_config(const void *fdt, int offset1) -{ - int countindex = 0, lentmp = 0; - const char *result = 0; - char mac_mode[4]; - - countindex = fdt_stringlist_count(fdt, offset1, "mode"); - if (1 == countindex) { - result = fdt_stringlist_get(fdt, offset1, "mode", 0, &lentmp); - blog_info_user(dts, "MAC address mode length %d\r\n", lentmp); - if (lentmp <= MAC_ORDER_ADDR_LEN_MAX) { - memcpy(mac_mode, result, lentmp); - mac_mode[3] = '\0'; - blog_info_user(dts, "MAC address mode is %s\r\n", mac_mode); - update_mac_config_with_order(fdt, offset1, mac_mode); - } - } -} - - -static int update_xtal_config_get_mac_from_factory(uint32_t capcode[5]) -{ - uint8_t capcode_efuse = 0; - - if (bl_efuse_read_capcode(&capcode_efuse)) { - return -1; - } - /*efuse only have one capcode entry, so we fill the left with hardcode*/ - capcode[0] = capcode_efuse; - capcode[1] = capcode_efuse; - capcode[2] = 1; - capcode[3] = 60; - capcode[4] = 60; - - return 0; -} - -static int update_xtal_config_get_mac_from_dtb(const void *fdt, int offset1, uint32_t capcode[5]) -{ - const uint8_t *addr_prop = 0; - int lentmp = 0; - - addr_prop = fdt_getprop(fdt, offset1, "xtal", &lentmp); - - if (5*4 == lentmp) { - blog_info( - "xtal dtb in DEC :%u %u %u %u %u\r\n", - BL_FDT32_TO_U8(addr_prop, 4*0), - BL_FDT32_TO_U8(addr_prop, 4*1), - BL_FDT32_TO_U8(addr_prop, 4*2), - BL_FDT32_TO_U8(addr_prop, 4*3), - BL_FDT32_TO_U8(addr_prop, 4*4) - ); - capcode[0] = BL_FDT32_TO_U8(addr_prop, 4*0); - capcode[1] = BL_FDT32_TO_U8(addr_prop, 4*1); - capcode[2] = BL_FDT32_TO_U8(addr_prop, 4*2); - capcode[3] = BL_FDT32_TO_U8(addr_prop, 4*3); - capcode[4] = BL_FDT32_TO_U8(addr_prop, 4*4); - } else { - blog_error("xtal dtb NULL."); - return -1; - } - return 0; -} - -#define XTAL_ORDER_ADDR_LEN_MAX (2) -static void update_xtal_config_with_order(const void *fdt, int offset1, const char *order) -{ - int i, set, len; - uint32_t capcode[5]; - - set = 0; - len = strlen(order); - for (i = 0; i < XTAL_ORDER_ADDR_LEN_MAX && i < len; i++) { - switch (order[i]) { - case 'F': - { - if (0 == update_xtal_config_get_mac_from_dtb(fdt, offset1, capcode)) { - set = 1; - blog_info("get xtal from F ready\r\n"); - goto break_scan; - } else { - blog_info("get xtal from F failed\r\n"); - } - } - break; - case 'M': - { - if (0 == update_xtal_config_get_mac_from_factory(capcode)) { - set = 1; - blog_info("get xtal from M ready\r\n"); - goto break_scan; - } else { - blog_info("get xtal from M failed\r\n"); - } - } - break; - default: - { - BL_ASSERT(0); - } - } - } -break_scan: - if (0 == set) { - blog_info("Using Default xtal\r\n"); - capcode[0] = 50; - capcode[1] = 50; - capcode[2] = 1; - capcode[3] = 60; - capcode[4] = 60; - } - hal_sys_capcode_update(capcode[0], capcode[1]); -} - -static void update_xtal_config(const void *fdt, int offset1) -{ - int lentmp = 0, countindex; - char xtal_mode[3]; - const char *result = 0; - - countindex = fdt_stringlist_count(fdt, offset1, "xtal_mode"); - if (1 == countindex) { - result = fdt_stringlist_get(fdt, offset1, "xtal_mode", 0, &lentmp); - blog_info("xtal_mode length %d\r\n", lentmp); - if (lentmp <= XTAL_ORDER_ADDR_LEN_MAX) { - memcpy(xtal_mode, result, lentmp); - xtal_mode[sizeof(xtal_mode) - 1] = '\0'; - blog_info("xtal_mode is %s\r\n", xtal_mode); - update_xtal_config_with_order(fdt, offset1, xtal_mode); - } - } -} -#if 0 -static void update_xtal_config_rftv(uint32_t tlv_addr) -{ - int i, set, len; - uint8_t buffer[20] = {0}; - uint32_t capcode[5] = {0}; - char xtal_mode[3] = {0}; - - if (rftlv_get(tlv_addr, RFTLV_API_TYPE_XTAL_MODE, 3, xtal_mode) > 0) { - xtal_mode[sizeof(xtal_mode) - 1] = '\0'; - blog_info("xtal_mode is %s\r\n", xtal_mode); - } - - set = 0; - len = strlen(xtal_mode); - for (i = 0; i < XTAL_ORDER_ADDR_LEN_MAX && i < len; i++) { - switch (xtal_mode[i]) { - case 'F': - { - if (rftlv_get(tlv_addr, RFTLV_API_TYPE_XTAL, sizeof(buffer), buffer) > 0) { - capcode[0] = *(uint32_t *)buffer; - capcode[1] = *(uint32_t *)(buffer + 4); - capcode[2] = *(uint32_t *)(buffer + 8); - capcode[3] = *(uint32_t *)(buffer + 12); - capcode[4] = *(uint32_t *)(buffer + 16); - set = 1; - blog_info("get xtal from F ready %d %d %d %d %d\r\n", - capcode[0], - capcode[1], - capcode[2], - capcode[3], - capcode[4]); - goto break_scan; - } else { - blog_info("get xtal from F failed\r\n"); - } - } - break; - case 'M': - { - if (0 == update_xtal_config_get_mac_from_factory(capcode)) { - set = 1; - blog_info("get xtal from M ready %d %d %d %d %d\r\n", - capcode[0], - capcode[1], - capcode[2], - capcode[3], - capcode[4]); - goto break_scan; - } else { - blog_info("get xtal from M failed\r\n"); - } - } - break; - default: - { - BL_ASSERT(0); - } - } - } -break_scan: - if (0 == set) { - blog_info("Using Default xtal\r\n"); - capcode[0] = 50; - capcode[1] = 50; - capcode[2] = 1; - capcode[3] = 60; - capcode[4] = 60; - } - hal_sys_capcode_update(capcode[0], capcode[1]); -} -#endif -static int update_poweroffset_config_get_mac_from_dtb(const void *fdt, int offset1, int8_t poweroffset[14]) -{ - int lentmp = 0, i; - const uint8_t *addr_prop = 0; - -#define PWR_OFFSET_BASE (10) - addr_prop = fdt_getprop(fdt, offset1, "pwr_offset", &lentmp); - if (14*4 == lentmp) { - for (i = 0; i < 14; i++) { - poweroffset[i] = BL_FDT32_TO_U32(addr_prop, 4*i); - } - blog_info("pwr_offset from dtb:\r\n"); - blog_buf(poweroffset, 14); - for (i = 0; i < 14; i++) { - poweroffset[i] -= PWR_OFFSET_BASE; - poweroffset[i] = poweroffset[i] * 4; - } - blog_info("pwr_offset from dtb (rebase on %d):\r\n", PWR_OFFSET_BASE); - //TODO FIXME log buffer - //blog_buf_int8(poweroffset, 14); - } else { - blog_error("pwr_offset NULL. lentmp = %d\r\n", lentmp); - return -1; - } - return 0; -} - -static void update_poweroffset_config_with_order(const void *fdt, int offset1, const char *order) -{ - int i, set, len, j; - int8_t poweroffset[14], poweroffset_tmp[14]; - - memset(poweroffset, 0, sizeof(poweroffset)); - memset(poweroffset_tmp, 0, sizeof(poweroffset_tmp)); - set = 0; - len = strlen(order); - for (i = 0; i < XTAL_ORDER_ADDR_LEN_MAX && i < len; i++) { - switch (order[i]) { - case 'B': - case 'b': - { - if (0 == bl_efuse_read_pwroft(poweroffset_tmp)) { - set = 1; - blog_info("get pwr offset from B(b) ready\r\n"); - log_buf_int8(poweroffset_tmp, sizeof(poweroffset_tmp)); - if ('B' == order[i]) { - /*non-incremental mode*/ - for (j = 0; j < sizeof(poweroffset); j++) { - poweroffset[j] = poweroffset_tmp[j]; - } - blog_info("Use pwr offset from B only\r\n"); - goto break_scan; - } else { - /*incremental mode*/ - blog_info("Use pwr offset from b in incremental mode\r\n"); - for (j = 0; j < sizeof(poweroffset); j++) { - poweroffset[j] += poweroffset_tmp[j]; - } - } - } else { - blog_info("get pwr offset from B(b) failed\r\n"); - } - } - break; - case 'F': - case 'f': - { - if (0 == update_poweroffset_config_get_mac_from_dtb(fdt, offset1, poweroffset_tmp)) { - set = 1; - blog_info("get pwr offset from F(f) ready\r\n"); - if ('B' == order[i]) { - /*non-incremental mode*/ - for (j = 0; j < sizeof(poweroffset); j++) { - poweroffset[j] = poweroffset_tmp[j]; - } - blog_info("Use pwr offset from F only\r\n"); - goto break_scan; - } else { - /*incremental mode*/ - blog_info("Use pwr offset from f in incremental mode\r\n"); - for (j = 0; j < sizeof(poweroffset); j++) { - poweroffset[j] += poweroffset_tmp[j]; - } - } - goto break_scan; - } else { - blog_info("get pwr offset from F(f) failed\r\n"); - } - } - break; - default: - { - BL_ASSERT(0); - } - } - } -break_scan: - if (0 == set) { - blog_info("Using Default pwr offset\r\n");//all zeros actually - } - log_buf_int8(poweroffset, sizeof(poweroffset)); -#ifdef CFG_BLE_ENABLE - extern void ble_rf_set_pwr_offset_table(int8_t *poweroffset_table); - ble_rf_set_pwr_offset_table(poweroffset); -#endif - //zys phy_powroffset_set(poweroffset); -} - - -#define PWR_OFFSET_ORDER_ADDR_LEN_MAX (2) -static void update_poweroffset_config(const void *fdt, int offset1) -{ - int lentmp = 0, countindex; - char pwr_mode[3]; - const char *result = 0; - - countindex = fdt_stringlist_count(fdt, offset1, "pwr_mode"); - if (1 == countindex) { - result = fdt_stringlist_get(fdt, offset1, "pwr_mode", 0, &lentmp); - blog_info("pwr_mode length %d\r\n", lentmp); - if (lentmp <= PWR_OFFSET_ORDER_ADDR_LEN_MAX) { - memcpy(pwr_mode, result, lentmp); - pwr_mode[sizeof(pwr_mode) - 1] = '\0'; - blog_info("pwr_mode is %s\r\n", pwr_mode); - update_poweroffset_config_with_order(fdt, offset1, pwr_mode); - } - } -} -#if 0 -zys -static void update_poweroffset_config_rftv(uint32_t tlv_addr, const char *pw_mode) -{ - int i, set, len, j; - int8_t poweroffset[14], poweroffset_tmp[14]; - - memset(poweroffset, 0, sizeof(poweroffset)); - memset(poweroffset_tmp, 0, sizeof(poweroffset_tmp)); - set = 0; - len = strlen(pw_mode); - for (i = 0; i < XTAL_ORDER_ADDR_LEN_MAX && i < len; i++) { - switch (pw_mode[i]) { - case 'B': - case 'b': - { - if (0 == bl_efuse_read_pwroft(poweroffset_tmp)) { - set = 1; - blog_info("get pwr offset from B(b) ready\r\n"); - log_buf_int8(poweroffset_tmp, sizeof(poweroffset_tmp)); - if ('B' == pw_mode[i]) { - /*non-incremental mode*/ - for (j = 0; j < sizeof(poweroffset); j++) { - poweroffset[j] = poweroffset_tmp[j]; - } - blog_info("Use pwr offset from B only\r\n"); - goto break_scan; - } else { - /*incremental mode*/ - blog_info("Use pwr offset from b in incremental mode\r\n"); - for (j = 0; j < sizeof(poweroffset); j++) { - poweroffset[j] += poweroffset_tmp[j]; - } - } - } else { - blog_info("get pwr offset from B(b) failed\r\n"); - } - } - break; - case 'F': - case 'f': - { - if (rftlv_get(tlv_addr, RFTLV_TYPE_PWR_OFFSET, sizeof(poweroffset_tmp), poweroffset_tmp) > 0) { - set = 1; - blog_info("get pwr offset from F(f) ready\r\n"); - if ('F' == pw_mode[i]) { - /*non-incremental mode*/ - for (j = 0; j < sizeof(poweroffset); j++) { - poweroffset[j] = (poweroffset_tmp[j] - 10)*4; - } - blog_info("Use pwr offset from F only\r\n"); - goto break_scan; - } else { - /*incremental mode*/ - blog_info("Use pwr offset from f in incremental mode\r\n"); - for (j = 0; j < sizeof(poweroffset); j++) { - poweroffset[j] = (poweroffset_tmp[j] - 10)*4; - } - } - goto break_scan; - } else { - blog_info("get pwr offset from F(f) failed\r\n"); - } - } - break; - default: - { - BL_ASSERT(0); - } - } - } -break_scan: - if (0 == set) { - blog_info("Using Default pwr offset\r\n");//all zeros actually - } - log_buf_int8(poweroffset, sizeof(poweroffset)); -#ifdef CFG_BLE_ENABLE - extern void ble_rf_set_pwr_offset_table(int8_t *poweroffset_table); - ble_rf_set_pwr_offset_table(poweroffset); -#endif - //zys phy_powroffset_set(poweroffset); -} -#endif -static int update_sta_field(const void *fdt, int wifi_offset, const char *name) -{ - int offset1 = 0; /* subnode offset1 */ - int countindex = 0, lentmp = 0; - const char *result = 0; - const uint8_t *addr_prop = 0; - int auto_connect_enable; - - /* set ssid pwd */ - uint8_t ap_ssid[32]; - uint8_t ap_ssid_len = 0; - uint8_t ap_psk[64]; - uint8_t ap_psk_len = 0; - - offset1 = fdt_subnode_offset(fdt, wifi_offset, name); - if (offset1 > 0) { - - countindex = fdt_stringlist_count(fdt, offset1, "ssid"); - if (1 == countindex) { - result = fdt_stringlist_get(fdt, offset1, "ssid", 0, &lentmp); - if ((lentmp > 0) &&(lentmp<32)) {/* !NULL */ - blog_info("[STA] ap_ssid string[%d] = %s, ap_ssid_len = %d\r\n", 0, result, lentmp); - memcpy(ap_ssid, result, lentmp); - ap_ssid[lentmp] = '\0'; - ap_ssid_len = lentmp; - } - } - - countindex = fdt_stringlist_count(fdt, offset1, "pwd"); - if (1 == countindex) { - result = fdt_stringlist_get(fdt, offset1, "pwd", 0, &lentmp); - if ((lentmp > 0) &&(lentmp<32)) {/* !NULL */ - blog_info("[STA] ap_psk string[%d] = %s, ap_psk_len = %d\r\n", 0, result, lentmp); - memcpy(ap_psk, result, lentmp); - ap_psk[lentmp] = '\0'; - ap_psk_len = lentmp; - } - } - addr_prop = fdt_getprop(fdt, offset1, "auto_connect_enable", &lentmp); - if (addr_prop) { - blog_info("auto_connect_enable = %ld\r\n", BL_FDT32_TO_U32(addr_prop, 0)); - - auto_connect_enable = BL_FDT32_TO_U32(addr_prop, 0); - } else { - auto_connect_enable = 0; - } - - bl_wifi_sta_info_set(ap_ssid, ap_ssid_len, ap_psk, ap_psk_len, auto_connect_enable); - } - return offset1; -} - -static int update_ap_field(const void *fdt, int wifi_offset, const char *name) -{ - int offset1 = 0; /* subnode offset1 */ - int countindex = 0, lentmp = 0; - const char *result = 0; - const uint8_t *addr_prop = 0; - - /* set ssid pwd */ - uint8_t ap_ssid[32]; - uint8_t ap_ssid_len = 0; - uint8_t ap_psk[64]; - uint8_t ap_psk_len = 0; - uint8_t ap_channel = 0; - - offset1 = fdt_subnode_offset(fdt, wifi_offset, "ap"); - if (offset1 > 0) - { - countindex = fdt_stringlist_count(fdt, offset1, "ssid"); - if (1 == countindex) { - result = fdt_stringlist_get(fdt, offset1, "ssid", 0, &lentmp); - if ((lentmp > 0) &&(lentmp<32)) {/* !NULL */ - blog_info("ap_ssid string[%d] = %s, ap_ssid_len = %d\r\n", 0, result, lentmp); - memcpy(ap_ssid, result, lentmp); - ap_ssid[lentmp] = '\0'; - ap_ssid_len = lentmp; - } - } - - countindex = fdt_stringlist_count(fdt, offset1, "pwd"); - if (1 == countindex) { - result = fdt_stringlist_get(fdt, offset1, "pwd", 0, &lentmp); - if ((lentmp > 0) &&(lentmp<32)) {/* !NULL */ - blog_info("ap_psk string[%d] = %s, ap_psk_len = %d\r\n", 0, result, lentmp); - memcpy(ap_psk, result, lentmp); - ap_psk[lentmp] = '\0'; - ap_psk_len = lentmp; - } - } - - addr_prop = fdt_getprop(fdt, offset1, "ap_channel", &lentmp); - if (addr_prop) { - blog_info("ap_channel = %ld\r\n", BL_FDT32_TO_U32(addr_prop, 0)); - - ap_channel = BL_FDT32_TO_U32(addr_prop, 0); - } else { - blog_error("ap_channel NULL.\r\n"); - } - - bl_wifi_ap_info_set(ap_ssid, ap_ssid_len, - ap_psk, ap_psk_len, - ap_channel); - } - return offset1; -} - -typedef struct{ - uint16_t Tchannels[5]; - int16_t Tchannel_os[5]; - int16_t Tchannel_os_low[5]; - int16_t Troom_os; - uint8_t en_tcal; - uint8_t linear_or_follow; -} tcal_param_struct; -extern tcal_param_struct* tcal_param; -enum { - E_RF_TCAL_UPDATE_PARAM = 0, -}; -void rf_pri_update_tcal_param(uint8_t operation);//FIXME -#define TCAL_PARA_CHANNELS 5 - -static int update_rf_temp_field(const void *fdt, int wifi_offset, const char *name) -{ - int lentmp, i; - int offset1 = 0; - const uint8_t *addr_prop = 0; - uint32_t tmp[TCAL_PARA_CHANNELS]; - tcal_param_struct tcal_param_tmp; - - offset1 = fdt_subnode_offset(fdt, wifi_offset, name); - if (offset1 > 0) { - addr_prop = fdt_getprop(fdt, offset1, "Troom_os", &lentmp); - if (addr_prop) { - tcal_param_tmp.Troom_os=BL_FDT32_TO_U32(addr_prop, 0)-256; - blog_info_user(dts, "Troom_os = %d, lentmp = %d\r\n", (int)tcal_param_tmp.Troom_os, lentmp); - } else { - blog_info_user(dts, "Troom_os NULL.\r\n"); - return -1; - } - - addr_prop = fdt_getprop(fdt, offset1, "linear_or_follow", &lentmp); - if (addr_prop) { - tcal_param_tmp.linear_or_follow=BL_FDT32_TO_U32(addr_prop, 0); - blog_info_user(dts, "linear_or_follow = %d, lentmp = %d\r\n", (int)tcal_param_tmp.linear_or_follow, lentmp); - } else { - blog_info_user(dts, "linear_or_follow NULL.\r\n"); - return -1; - } - - addr_prop = fdt_getprop(fdt, offset1, "Tchannels", &lentmp); - if (lentmp == TCAL_PARA_CHANNELS*4) { - memcpy(tmp, addr_prop, TCAL_PARA_CHANNELS*4); - blog_info_user(dts, "Tchannels:"); - for (i = 0; i < TCAL_PARA_CHANNELS; i++){ - tcal_param_tmp.Tchannels[i]=fdt32_to_cpu(tmp[i]); - blog_info_user_raw(dts, "%d,", (int)tcal_param_tmp.Tchannels[i]); - } - blog_info_user_raw(dts, "\r\n"); - } else { - blog_info_user(dts, "Tchannels NULL.\r\n"); - return -1; - } - - addr_prop = fdt_getprop(fdt, offset1, "Tchannel_os", &lentmp); - if (lentmp == TCAL_PARA_CHANNELS*4) { - memcpy(tmp, addr_prop, TCAL_PARA_CHANNELS*4); - blog_info_user(dts, "Tchannel_os:"); - for (i = 0; i < TCAL_PARA_CHANNELS; i++){ - tcal_param_tmp.Tchannel_os[i]=fdt32_to_cpu(tmp[i]); - blog_info_user_raw(dts, "%d,", (int)tcal_param_tmp.Tchannel_os[i]); - } - blog_info_user_raw(dts, "\r\b"); - } else { - blog_info_user(dts, "Tchannel_os NULL.\r\n"); - return -1; - } - - addr_prop = fdt_getprop(fdt, offset1, "Tchannel_os_low", &lentmp); - if (lentmp == TCAL_PARA_CHANNELS*4) { - memcpy(tmp, addr_prop, TCAL_PARA_CHANNELS*4); - blog_info_user(dts, "Tchannel_os_low:"); - for (i = 0; i < TCAL_PARA_CHANNELS; i++){ - tcal_param_tmp.Tchannel_os_low[i]=fdt32_to_cpu(tmp[i]); - blog_info_user_raw(dts, "%d,", (int)tcal_param_tmp.Tchannel_os_low[i]); - } - blog_info_user_raw(dts, "\r\n"); - } else { - blog_info_user(dts, "Tchannel_os_low NULL.\r\n"); - return -1; - } - addr_prop = fdt_getprop(fdt, offset1, "en_tcal", &lentmp); - if (addr_prop) { - tcal_param_tmp.en_tcal=BL_FDT32_TO_U32(addr_prop, 0); - blog_info_user(dts, "en_tcal = %u, lentmp = %d\r\n", tcal_param_tmp.en_tcal, lentmp); - } else { - blog_info_user(dts, "en_tcal NULL.\r\n"); - return -1; - } - } - memcpy(tcal_param, &tcal_param_tmp, sizeof(tcal_param_tmp)); - rf_pri_update_tcal_param(E_RF_TCAL_UPDATE_PARAM); - - return 0; -} -#if 0 -static int hal_board_load_rftv_info(uint32_t rftlv_addr) -{ - int i; - uint8_t *p_buffer; - - /* set tx_pwr_tbl */ - int8_t pwr_table[24]; - - int pwr_table_ble = 0; - - if (!rftlv_valid(rftlv_addr)) { - return -2; - } - - p_buffer = pvPortMalloc(80); - if (p_buffer == NULL) { - return -1; - } - - /* set xtal */ - update_xtal_config_rftv(rftlv_addr); - - if (rftlv_get(rftlv_addr, RFTLV_API_TYPE_PWR_TABLE_11B, 80, p_buffer) > 0) { - for (i = 0; i < 4; i++) { - pwr_table[i] = *(int8_t *)(p_buffer + i); - } - blog_info("pwr_table_11b :%u %u %u %u\r\n", - pwr_table[0], - pwr_table[1], - pwr_table[2], - pwr_table[3] - ); - bl_tpc_update_power_rate_11b((int8_t*)pwr_table); - } else { - blog_error("RFTLV_TYPE_PWR_TABLE_11B NULL\r\n"); - } - if (rftlv_get(rftlv_addr, RFTLV_API_TYPE_PWR_TABLE_11G, 80, p_buffer) > 0) { - for (i = 0; i < 8; i++) { - pwr_table[i] = *(int8_t *)(p_buffer + i); - } - blog_info("pwr_table_11g :%u %u %u %u %u %u %u %u\r\n", - pwr_table[0], - pwr_table[1], - pwr_table[2], - pwr_table[3], - pwr_table[4], - pwr_table[5], - pwr_table[6], - pwr_table[7] - ); - bl_tpc_update_power_rate_11g((int8_t*)pwr_table); - } else { - blog_error("RFTLV_TYPE_PWR_TABLE_11G NULL\r\n"); - } - if (rftlv_get(rftlv_addr, RFTLV_API_TYPE_PWR_TABLE_11N, 80, p_buffer) > 0) { - for (i = 0; i < 8; i++) { - pwr_table[i] = *(int8_t *)(p_buffer + i); - } - blog_info("pwr_table_11n :%u %u %u %u %u %u %u %u\r\n", - pwr_table[0], - pwr_table[1], - pwr_table[2], - pwr_table[3], - pwr_table[4], - pwr_table[5], - pwr_table[6], - pwr_table[7] - ); - bl_tpc_update_power_rate_11n((int8_t*)pwr_table); - } else { - blog_error("RFTLV_TYPE_PWR_TABLE_11N NULL\r\n"); - } - - if (rftlv_get(rftlv_addr, RFTLV_API_TYPE_PWR_MODE, 80, p_buffer) > 0) { - p_buffer[2] = '\0'; - update_poweroffset_config_rftv(rftlv_addr, (const char *)p_buffer); - } else { - blog_error("RFTLV_TYPE_PWR_MODE NULL\r\n"); - } - - if (rftlv_get(rftlv_addr, RFTLV_API_TYPE_PWR_TABLE_BLE, 80, p_buffer) > 0) { - pwr_table_ble = *(int8_t *)p_buffer; - blog_info("set pwr_table_ble = %ld in dts\r\n", pwr_table_ble); - } else { - blog_error("RFTLV_TYPE_PWR_TABLE_BLE NULL\r\n"); - } -#ifdef CFG_BLE_ENABLE - ble_controller_set_tx_pwr(pwr_table_ble); -#endif - - vPortFree(p_buffer); - - return 0; -} -#endif -//static int __try_load_rftlv() -//{ -//extern uint32_t _ld_symbol_rftlv_address; -// return hal_board_load_rftv_info((uint32_t)&_ld_symbol_rftlv_address); -//zys} - -static int hal_board_load_fdt_info(const void *dtb) -{ - const void *fdt = (const void *)dtb;/* const */ - - /* set tx_pwr_tbl */ - uint8_t pwr_table[24]; - - uint32_t channel_div_table[15]; - uint16_t channel_cnt_table[14]; - uint16_t lo_fcal_div = 0; - int pwr_table_ble = 0; - - int wifi_offset = 0, bt_offset = 0; /* subnode wifi & bluetooth */ - int offset1 = 0, offset2 = 0; /* subnode offset1 */ - const uint8_t *addr_prop = 0; - - int lentmp = 0; - int i; - - wifi_offset = fdt_subnode_offset(fdt, 0, "wifi"); - if (!(wifi_offset > 0)) { - blog_error("wifi NULL.\r\n"); - } - - offset1 = fdt_subnode_offset(fdt, wifi_offset, "mac"); - if (offset1 > 0) { - update_mac_config(fdt, offset1); - } - - offset1 = fdt_subnode_offset(fdt, wifi_offset, "region"); - if (offset1 > 0) { - /* set country_code */ - addr_prop = fdt_getprop(fdt, offset1, "country_code", &lentmp); - if (4 == lentmp) { - blog_info("country_code : %d\r\n", BL_FDT32_TO_U8(addr_prop, 4*0)); - - bl_wifi_country_code_set(BL_FDT32_TO_U8(addr_prop, 4*0)); - } else { - blog_error("country_code NULL.\r\n"); - } - } - -//zys if (0 == __try_load_rftlv()) { - - /* load rf from tlv successful */ -// goto __exit; -// } - - offset1 = fdt_subnode_offset(fdt, wifi_offset, "brd_rf"); - if (offset1 > 0) - { - - USER_UNUSED(lo_fcal_div); - USER_UNUSED(channel_div_table); - USER_UNUSED(channel_cnt_table); - - /* set xtal */ - //update_xtal_config(fdt, offset1); - - /* set channel_div_table, channel_cnt_table, lo_fcal_div */ - addr_prop = fdt_getprop(fdt, offset1, "channel_div_table", &lentmp); - if (15*4 == lentmp) { - for (i = 0; i < 15; i++) { - channel_div_table[i] = BL_FDT32_TO_U32(addr_prop, 4*i); - } - blog_info("channel_div_table :\r\n"); - blog_buf(channel_div_table, 15*4); - } else { - blog_error("channel_div_table NULL.\r\n"); - } - - addr_prop = fdt_getprop(fdt, offset1, "channel_cnt_table", &lentmp); - if (14*4 == lentmp) { - for (i = 0; i < 14; i++) { - channel_cnt_table[i] = BL_FDT32_TO_U16(addr_prop, 4*i); - } - blog_info("channel_cnt_table :\r\n"); - blog_buf(channel_cnt_table, 14*4); - } else { - blog_error("channel_cnt_table NULL.\r\n"); - } - - addr_prop = fdt_getprop(fdt, offset1, "lo_fcal_div", &lentmp); - if (4 == lentmp) { - lo_fcal_div = BL_FDT32_TO_U16(addr_prop, 4*0); - blog_info("lo_fcal_div : %d\r\n", lo_fcal_div); - } else { - blog_error("lo_fcal_div NULL.\r\n"); - } - - //TODO FIXME POWER - //bl60x_fw_rf_table_set(channel_div_table, channel_cnt_table, lo_fcal_div); - - USER_UNUSED(pwr_table); - addr_prop = fdt_getprop(fdt, offset1, "pwr_table_11b", &lentmp); - if (4*4 == lentmp) { - for (i = 0; i < 4; i++) { - pwr_table[i] = BL_FDT32_TO_U32(addr_prop, 4*i); - } - blog_info("pwr_table_11b :%u %u %u %u\r\n", - pwr_table[0], - pwr_table[1], - pwr_table[2], - pwr_table[3] - ); - //bl_tpc_update_power_rate_11b((int8_t*)pwr_table); - } else { - blog_error("pwr_table_11b NULL. lentmp = %d\r\n", lentmp); - } - - addr_prop = fdt_getprop(fdt, offset1, "pwr_table_11g", &lentmp); - if (8*4 == lentmp) { - for (i = 0; i < 8; i++) { - pwr_table[i] = BL_FDT32_TO_U32(addr_prop, 4*i); - } - blog_info("pwr_table_11g :%u %u %u %u %u %u %u %u\r\n", - pwr_table[0], - pwr_table[1], - pwr_table[2], - pwr_table[3], - pwr_table[4], - pwr_table[5], - pwr_table[6], - pwr_table[7] - ); - //bl_tpc_update_power_rate_11g((int8_t*)pwr_table); - } else { - blog_error("pwr_table_11g NULL. lentmp = %d\r\n", lentmp); - } - - addr_prop = fdt_getprop(fdt, offset1, "pwr_table_11n", &lentmp); - if (8*4 == lentmp) { - for (i = 0; i < 8; i++) { - pwr_table[i] = BL_FDT32_TO_U32(addr_prop, 4*i); - } - blog_info("pwr_table_11n :%u %u %u %u %u %u %u %u\r\n", - pwr_table[0], - pwr_table[1], - pwr_table[2], - pwr_table[3], - pwr_table[4], - pwr_table[5], - pwr_table[6], - pwr_table[7] - ); - //bl_tpc_update_power_rate_11n((int8_t*)pwr_table); - } else { - blog_error("pwr_table_11n NULL. lentmp = %d\r\n", lentmp); - } - //update_poweroffset_config(fdt, offset1); - } - - bt_offset = fdt_subnode_offset(fdt, 0, "bluetooth"); - if (!(bt_offset > 0)) { - blog_error("bt NULL.\r\n"); - } - - offset2 = fdt_subnode_offset(fdt, bt_offset, "brd_rf"); - if (offset2 > 0) { - addr_prop = fdt_getprop(fdt, offset2, "pwr_table_ble", &lentmp); - if (addr_prop) { - pwr_table_ble = (int8_t)BL_FDT32_TO_U32(addr_prop, 0); - } else { - pwr_table_ble = 0; - } - blog_info("set pwr_table_ble = %ld in dts\r\n", pwr_table_ble); -#ifdef CFG_BLE_ENABLE - //ble_controller_set_tx_pwr(pwr_table_ble); -#endif - } - -//__exit: - //offset1 = update_ap_field(fdt, wifi_offset, "ap"); - //offset1 = update_sta_field(fdt, wifi_offset, "sta"); -// offset1 = update_rf_temp_field(fdt, wifi_offset, "rf_temp"); - - return 0; -} -//#endif - -#ifdef CONFIG_USER_DTS_INAPP -/* - { - model = "bl bl602 iot board"; - wifi { - #address-cells = <1>; - #size-cells = <1>; - region { - country_code = <86>; - }; - mac { - mode = "MBF"; - sta_mac_addr = [C8 43 57 82 73 40]; - ap_mac_addr = [C8 43 57 82 73 02]; - }; - ap { - ssid = "bl_test_005"; - pwd = "12345678"; - ap_channel = <11>; - auto_chan_detect = "disable"; - }; - brd_rf { - xtal_mode = "MF"; - xtal = <36 36 0 60 60>; - pwr_mode = "bf"; - pwr_table = <0x4 0x3 0x3 0xBA 0x4 0x3 0x4 0xB0 0x4 0x3 0x5 0xA7 0x3 0x3 0x0 0x9F 0x3 0x3 0x1 0x95 0x3 0x3 0x2 0x8C 0x3 0x3 0x3 0x81 0x3 0x3 0x4 0x77 0x3 0x3 0x5 0x6E 0x2 0x3 0x0 0x65 0x2 0x3 0x1 0x5B 0x2 0x3 0x2 0x52 0x2 0x3 0x3 0x48 0x2 0x3 0x4 0x3E 0x2 0x3 0x5 0x34 0x1 0x3 0x3 0xA>; - pwr_offset = <10 10 10 10 10 10 10 10 10 10 10 10 10 10>; - channel_div_table = <0x1EEC4EC4 0x1EFCB7CB 0x1F0D20D2 0x1F1D89D8 0x1F2DF2DF 0x1F3E5BE5 0x1F4EC4EC 0x1F5F2DF2 0x1F6F96F9 0x1F800000 0x1F906906 0x1FA0D20D 0x1FB13B13 0x1FD89D89 0x201F81F8>; - channel_cnt_table = <0xA78A 0xA7E3 0xA83C 0xA895 0xA8ED 0xA946 0xA99F 0xA9F8 0xAA51 0xAAAA 0xAB03 0xAB5C 0xABB5 0xAC8A>; - lo_fcal_div = <0x56B>; - }; - }; -}; -*/ -const uint8_t factory_dtb[] = {//1126 - 0xd0, 0x0d, 0xfe, 0xed, 0x00, 0x00, 0x04, 0x66, 0x00, 0x00, 0x00, 0x38, - 0x00, 0x00, 0x03, 0x98, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x11, - 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xce, - 0x00, 0x00, 0x03, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x13, - 0x00, 0x00, 0x00, 0x00, 0x62, 0x6c, 0x20, 0x62, 0x6c, 0x36, 0x30, 0x32, - 0x20, 0x69, 0x6f, 0x74, 0x20, 0x62, 0x6f, 0x61, 0x72, 0x64, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x01, 0x77, 0x69, 0x66, 0x69, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x06, - 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, - 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0x00, 0x00, 0x00, 0xa7, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9f, 0x00, 0x00, 0x00, 0x03, - 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x95, - 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x02, - 0x00, 0x00, 0x00, 0x8c, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03, - 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x81, 0x00, 0x00, 0x00, 0x03, - 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x05, - 0x00, 0x00, 0x00, 0x6e, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x03, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x65, 0x00, 0x00, 0x00, 0x02, - 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x5b, - 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x02, - 0x00, 0x00, 0x00, 0x52, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x03, - 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x48, 0x00, 0x00, 0x00, 0x02, - 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0x1f, 0xa0, 0xd2, 0x0d, 0x1f, 0xb1, 0x3b, 0x13, 0x1f, 0xd8, 0x9d, 0x89, - 0x20, 0x1f, 0x81, 0xf8, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x38, - 0x00, 0x00, 0x00, 0xb0, 0x00, 0x00, 0xa7, 0x8a, 0x00, 0x00, 0xa7, 0xe3, - 0x00, 0x00, 0xa8, 0x3c, 0x00, 0x00, 0xa8, 0x95, 0x00, 0x00, 0xa8, 0xed, - 0x00, 0x00, 0xa9, 0x46, 0x00, 0x00, 0xa9, 0x9f, 0x00, 0x00, 0xa9, 0xf8, - 0x00, 0x00, 0xaa, 0x51, 0x00, 0x00, 0xaa, 0xaa, 0x00, 0x00, 0xab, 0x03, - 0x00, 0x00, 0xab, 0x5c, 0x00, 0x00, 0xab, 0xb5, 0x00, 0x00, 0xac, 0x8a, - 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xc2, - 0x00, 0x00, 0x05, 0x6b, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02, - 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x09, 0x6d, 0x6f, 0x64, 0x65, - 0x6c, 0x00, 0x23, 0x61, 0x64, 0x64, 0x72, 0x65, 0x73, 0x73, 0x2d, 0x63, - 0x65, 0x6c, 0x6c, 0x73, 0x00, 0x23, 0x73, 0x69, 0x7a, 0x65, 0x2d, 0x63, - 0x65, 0x6c, 0x6c, 0x73, 0x00, 0x63, 0x6f, 0x75, 0x6e, 0x74, 0x72, 0x79, - 0x5f, 0x63, 0x6f, 0x64, 0x65, 0x00, 0x6d, 0x6f, 0x64, 0x65, 0x00, 0x73, - 0x74, 0x61, 0x5f, 0x6d, 0x61, 0x63, 0x5f, 0x61, 0x64, 0x64, 0x72, 0x00, - 0x61, 0x70, 0x5f, 0x6d, 0x61, 0x63, 0x5f, 0x61, 0x64, 0x64, 0x72, 0x00, - 0x73, 0x73, 0x69, 0x64, 0x00, 0x70, 0x77, 0x64, 0x00, 0x61, 0x70, 0x5f, - 0x63, 0x68, 0x61, 0x6e, 0x6e, 0x65, 0x6c, 0x00, 0x61, 0x75, 0x74, 0x6f, - 0x5f, 0x63, 0x68, 0x61, 0x6e, 0x5f, 0x64, 0x65, 0x74, 0x65, 0x63, 0x74, - 0x00, 0x78, 0x74, 0x61, 0x6c, 0x5f, 0x6d, 0x6f, 0x64, 0x65, 0x00, 0x78, - 0x74, 0x61, 0x6c, 0x00, 0x70, 0x77, 0x72, 0x5f, 0x6d, 0x6f, 0x64, 0x65, - 0x00, 0x70, 0x77, 0x72, 0x5f, 0x74, 0x61, 0x62, 0x6c, 0x65, 0x00, 0x70, - 0x77, 0x72, 0x5f, 0x6f, 0x66, 0x66, 0x73, 0x65, 0x74, 0x00, 0x63, 0x68, - 0x61, 0x6e, 0x6e, 0x65, 0x6c, 0x5f, 0x64, 0x69, 0x76, 0x5f, 0x74, 0x61, - 0x62, 0x6c, 0x65, 0x00, 0x63, 0x68, 0x61, 0x6e, 0x6e, 0x65, 0x6c, 0x5f, - 0x63, 0x6e, 0x74, 0x5f, 0x74, 0x61, 0x62, 0x6c, 0x65, 0x00, 0x6c, 0x6f, - 0x5f, 0x66, 0x63, 0x61, 0x6c, 0x5f, 0x64, 0x69, 0x76, 0x00 -}; - -#endif - -uint32_t hal_board_get_factory_addr(void) -{ - return factory_addr; -} - -int hal_board_cfg(uint8_t board_code) -{ -#ifdef CONFIG_USER_DTS_INAPP - factory_addr = (uint32_t)factory_dtb; -#else - int ret; - uint32_t size; - - USER_UNUSED(ret); - ret = hal_boot2_partition_addr_active("factory", &factory_addr, &size); - blog_info("[MAIN] [BOARD] [FLASH] addr from partition is %08x, ret is %d\r\n", (unsigned int)factory_addr, ret); - if (0 == factory_addr) { - blog_error("[MAIN] [BOARD] [FLASH] Dead loop. Reason: NO valid Param Parition found\r\n"); - while (1) { - } - } - - ret = hal_boot2_partition_bus_addr_active("factory", &factory_addr, &size); - blog_info("[MAIN] [BOARD] [XIP] addr from partition is %08x, ret is %d\r\n", (unsigned int)factory_addr, ret); - if (0 == factory_addr) { - blog_error("[MAIN] [BOARD] [XIP] Dead loop. Reason: NO valid Param Parition found\r\n"); - while (1) { - } - } -#endif - -//#ifndef FEATURE_WIFI_DISABLE - // printf("hal_board_load_fdt_info\n\r"); - hal_board_load_fdt_info((const void *)factory_addr); -//#endif - - return 0; -} diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_board.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_board.h deleted file mode 100644 index b9cc17502b..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_board.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __HAL_BOARD_H__ -#define __HAL_BOARD_H__ -int hal_board_cfg(uint8_t board_code); -uint32_t hal_board_get_factory_addr(void); -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_boot2.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_boot2.c deleted file mode 100644 index 826ce0daf6..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_boot2.c +++ /dev/null @@ -1,314 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include -#include - -#include "bl_boot2.h" -#include "bl_flash.h" -#include "hal_boot2.h" -#include - -#define USER_UNUSED(a) ((void)(a)) - -#define PARTITION_BOOT2_RAM_ADDR_ACTIVE (0x62047e00) -#define PARTITION_MAGIC (0x54504642) -#define PARTITION_FW_PART_NAME "FW" -#define PARTITION_FW_PART_HEADER_SIZE (0x0) -//TODO use header file from project -#define FW_XIP_ADDRESS (0x58000000) - -static struct { - uint8_t partition_active_idx; - uint8_t pad[3]; - PtTable_Stuff_Config table; -} boot2_partition_table;//XXX Dont change the name of varaible, since we refer this boot2_partition_table in linker script - -void hal_boot2_set_ptable_opt(HALpPtTable_Flash_Erase erase, HALpPtTable_Flash_Write write) -{ - PtTable_Set_Flash_Operation((pPtTable_Flash_Erase)erase, (pPtTable_Flash_Write)write); -} - -int hal_boot2_update_ptable(HALPartition_Entry_Config *ptEntry_hal) -{ - int ret; - //FIXME force covert - PtTable_Entry_Config *ptEntry = (PtTable_Entry_Config*)ptEntry_hal; - - ptEntry->activeIndex = !ptEntry->activeIndex; - (ptEntry->age)++; - ret = PtTable_Update_Entry(NULL,!boot2_partition_table.partition_active_idx, &boot2_partition_table.table, ptEntry); - return ret; -} - -static void _dump_partition(void) -{ - int i; - PtTable_Stuff_Config *part = &boot2_partition_table.table; - - USER_UNUSED(i); - USER_UNUSED(part); - - blog_info("======= PtTable_Config @%p=======\r\n", part); - blog_info("magicCode 0x%08X;", (unsigned int)(part->ptTable.magicCode)); - blog_info_raw(" version 0x%04X;", part->ptTable.version); - blog_info_raw(" entryCnt %u;", part->ptTable.entryCnt); - blog_info_raw(" age %lu;", part->ptTable.age); - blog_info_raw(" crc32 0x%08X\r\n", (unsigned int)part->ptTable.crc32); - - blog_info("idx type device activeIndex name Address[0] Address[1] Length[0] Length[1] age\r\n"); - for (i = 0; i < part->ptTable.entryCnt; i++) { - blog_info("[%02d] ", i); - blog_info_raw(" %02u", part->ptEntries[i].type); - blog_info_raw(" %u", part->ptEntries[i].device); - blog_info_raw(" %u", part->ptEntries[i].activeIndex); - blog_info_raw(" %8s", part->ptEntries[i].name); - blog_info_raw(" 0x%08x", (part->ptEntries[i].Address[0])); - blog_info_raw(" 0x%08x", (part->ptEntries[i].Address[1])); - blog_info_raw(" 0x%08x", (part->ptEntries[i].maxLen[0])); - blog_info_raw(" 0x%08x", (part->ptEntries[i].maxLen[1])); - blog_info_raw(" %lu\r\n", (part->ptEntries[i].age)); - } -} - -uint32_t hal_boot2_get_flash_addr(void) -{ - extern uint8_t __boot2_flashCfg_src; - - return (uint32_t)(&__boot2_flashCfg_src + - (sizeof(boot2_partition_table.table.ptEntries[0]) * boot2_partition_table.table.ptTable.entryCnt)); -} - -int hal_boot2_partition_bus_addr(const char *name, uint32_t *addr0, uint32_t *addr1, uint32_t *size0, uint32_t *size1, int *active) -{ - int i; - uint32_t addr0_t, addr1_t; - - if (PARTITION_MAGIC != boot2_partition_table.table.ptTable.magicCode) { - return -EIO; - } - - /*Get Target partition*/ - for (i = 0; i < boot2_partition_table.table.ptTable.entryCnt; i++) { - if (0 == strcmp((char *)&(boot2_partition_table.table.ptEntries[i].name[0]), name)) { - break; - } - } - if (boot2_partition_table.table.ptTable.entryCnt == i) { - return -ENOENT; - } - addr0_t = boot2_partition_table.table.ptEntries[i].Address[0]; - addr1_t = boot2_partition_table.table.ptEntries[i].Address[1]; - *active = boot2_partition_table.table.ptEntries[i].activeIndex; - *size0 = boot2_partition_table.table.ptEntries[i].maxLen[0]; - *size1 = boot2_partition_table.table.ptEntries[i].maxLen[1]; - - /*cal partition address*/ - for (i = 0; i < boot2_partition_table.table.ptTable.entryCnt; i++) { - if (0 == strcmp((char *)&(boot2_partition_table.table.ptEntries[i].name[0]), PARTITION_FW_PART_NAME)) { - break; - } - } - if (boot2_partition_table.table.ptTable.entryCnt == i) { - return -ECANCELED; - } - /*Make sure target partition is after FW partition*/ - if ( (addr0_t && (addr0_t < boot2_partition_table.table.ptEntries[i].Address[0])) || - (addr0_t && (addr0_t < boot2_partition_table.table.ptEntries[i].Address[1])) || - (addr1_t && (addr1_t < boot2_partition_table.table.ptEntries[i].Address[0])) || - (addr1_t && (addr1_t < boot2_partition_table.table.ptEntries[i].Address[1]))) { - return -EINVAL; - } - if ((0 != boot2_partition_table.table.ptEntries[i].activeIndex) && - (1 != boot2_partition_table.table.ptEntries[i].activeIndex)) { - return -EFAULT; - } - *addr0 = addr0_t - boot2_partition_table.table.ptEntries[i].Address[boot2_partition_table.table.ptEntries[i].activeIndex] - PARTITION_FW_PART_HEADER_SIZE + FW_XIP_ADDRESS; - *addr1 = addr1_t - boot2_partition_table.table.ptEntries[i].Address[boot2_partition_table.table.ptEntries[i].activeIndex] - PARTITION_FW_PART_HEADER_SIZE + FW_XIP_ADDRESS; - - return 0; -} - -int hal_boot2_partition_bus_addr_active(const char *name, uint32_t *addr, uint32_t *size) -{ - uint32_t addr0, addr1; - uint32_t size0, size1; - int active, ret; - - if ((ret = hal_boot2_partition_bus_addr(name, &addr0, &addr1, &size0, &size1, &active))) { - return ret; - } - *addr = active ? addr1 : addr0; - *size = active ? size1 : size0; - - return 0; -} - -int hal_boot2_partition_bus_addr_inactive(const char *name, uint32_t *addr, uint32_t *size) -{ - uint32_t addr0, addr1; - uint32_t size0, size1; - int active, ret; - - if ((ret = hal_boot2_partition_bus_addr(name, &addr0, &addr1, &size0, &size1, &active))) { - return ret; - } - *addr = active ? addr0 : addr1; - *size = active ? size0 : size1; - - return 0; -} - -int hal_boot2_partition_addr(const char *name, uint32_t *addr0, uint32_t *addr1, uint32_t *size0, uint32_t *size1, int *active) -{ - int i; - - if (PARTITION_MAGIC != boot2_partition_table.table.ptTable.magicCode) { - return -EIO; - } - - /*Get Target partition*/ - for (i = 0; i < boot2_partition_table.table.ptTable.entryCnt; i++) { - if (0 == strcmp((char *)&(boot2_partition_table.table.ptEntries[i].name[0]), name)) { - break; - } - } - if (boot2_partition_table.table.ptTable.entryCnt == i) { - return -ENOENT; - } - *addr0 = boot2_partition_table.table.ptEntries[i].Address[0]; - *addr1 = boot2_partition_table.table.ptEntries[i].Address[1]; - *size0 = boot2_partition_table.table.ptEntries[i].maxLen[0]; - *size1 = boot2_partition_table.table.ptEntries[i].maxLen[1]; - *active = boot2_partition_table.table.ptEntries[i].activeIndex; - - return 0; -} - -int hal_boot2_partition_addr_active(const char *name, uint32_t *addr, uint32_t *size) -{ - uint32_t addr0, addr1; - uint32_t size0, size1; - int active, ret; - - if ((ret = hal_boot2_partition_addr(name, &addr0, &addr1, &size0, &size1, &active))) { - return ret; - } - *addr = active ? addr1 : addr0; - *size = active ? size1 : size0; - - return 0; -} - -int hal_boot2_partition_addr_inactive(const char *name, uint32_t *addr, uint32_t *size) -{ - uint32_t addr0, addr1; - uint32_t size0, size1; - int active, ret; - - if ((ret = hal_boot2_partition_addr(name, &addr0, &addr1, &size0, &size1, &active))) { - return ret; - } - *addr = active ? addr0 : addr1; - *size = active ? size0 : size1; - - return 0; -} - -uint8_t hal_boot2_get_active_partition(void) -{ - return boot2_partition_table.partition_active_idx; -} - -int hal_boot2_get_active_entries_byname(uint8_t *name, HALPartition_Entry_Config *ptEntry_hal) -{ - PtTable_Entry_Config *ptEntry = (PtTable_Entry_Config*)ptEntry_hal; - if (PtTable_Get_Active_Entries_By_Name(&boot2_partition_table.table, name, ptEntry)) { - return -1; - } - return 0; -} - -int hal_boot2_get_active_entries(int type, HALPartition_Entry_Config *ptEntry_hal) -{ - PtTable_Entry_Config *ptEntry = (PtTable_Entry_Config*)ptEntry_hal; - if (PtTable_Get_Active_Entries(&boot2_partition_table.table, type, ptEntry)) { - return -1; - } - return 0; -} - -int hal_boot2_dump(void) -{ - _dump_partition(); - return 0; -} - -int hal_boot2_init(void) -{ - boot2_partition_table.partition_active_idx = *(uint8_t*)PARTITION_BOOT2_RAM_ADDR_ACTIVE; - - blog_info("[HAL] [BOOT2] Active Partition[%u] consumed %d Bytes\r\n", - boot2_partition_table.partition_active_idx, - sizeof(PtTable_Stuff_Config) - ); - _dump_partition(); - bl_flash_config_update(); - - return 0; -} - -#if 0 -#define PT_OTA_TYPE_NAME "FW" -#define PT_MEDIA_TYPE_NAME "mfg" -void hal_update_mfg_ptable(void) -{ - PtTable_Entry_Config ptEntry_fw; - PtTable_Entry_Config ptEntry_media; - - printf("update mfg table.\r\n"); - printf("====================\r\n"); - if (0 == hal_boot2_get_active_entries_byname((uint8_t *)PT_OTA_TYPE_NAME, (HALPartition_Entry_Config *)(&ptEntry_fw))) { // ota - if (0 == hal_boot2_get_active_entries_byname((uint8_t *)PT_MEDIA_TYPE_NAME, (HALPartition_Entry_Config *)(&ptEntry_media))) { // media - if (ptEntry_fw.Address[1] == ptEntry_media.Address[0]) { - - memset(ptEntry_media.name, 0, sizeof(ptEntry_media.name)); - PtTable_Update_Entry(NULL, !boot2_partition_table.partition_active_idx, &boot2_partition_table.table, &ptEntry_media); - - printf("===== update mfg partition =====\r\n"); - } - } - } - - printf("====================\r\n"); - printf("update mfg table.\r\n"); -} -#endif - diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_boot2.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_boot2.h deleted file mode 100644 index 387257309d..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_boot2.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __HAL_BOOT2_H__ -#define __HAL_BOOT2_H__ -#include - -typedef int (*fptr_Flash_Erase_t)(uint32_t startaddr,uint32_t endaddr); -typedef int (*fptr_Flash_Write_t)(uint32_t addr,uint8_t *data, uint32_t len); -typedef int (*fptr_Flash_Read_t) (uint32_t addr,uint8_t *data, uint32_t len); - -typedef struct { - uint8_t type; /*!< Partition entry type */ - uint8_t device; /*!< Partition entry device */ - uint8_t activeIndex; /*!< Partition entry active index */ - uint8_t name[9]; /*!< Partition entry name */ - uint32_t Address[2]; /*!< Partition entry start address */ - uint32_t maxLen[2]; /*!< Partition entry max length */ - uint32_t len; /*!< Partition entry length */ - uint32_t age; /*!< Partition entry age */ -} HALPartition_Entry_Config; - -/** - * @brief Partition id type definition - */ -typedef enum { - HAL_PT_ENTRY_FW_CPU0, /*!< Partition entry type:CPU0 firmware */ - HAL_PT_ENTRY_FW_CPU1, /*!< Partition entry type:CPU1 firmware */ - HAL_PT_ENTRY_MAX=16, /*!< Partition entry type:Max */ -} HALPtTable_Entry_Type; - -#define BOOT2_PARTITION_TYPE_FW (0) - -/** - * @brief Error type definition - */ -typedef enum -{ - HAL_SUCCESS = 0, - HAL_ERROR = 1, -} HAL_Err_Type; - -typedef HAL_Err_Type (*HALpPtTable_Flash_Erase)(uint32_t startaddr,uint32_t endaddr); -typedef HAL_Err_Type (*HALpPtTable_Flash_Write)(uint32_t addr,uint8_t *data, uint32_t len); -typedef HAL_Err_Type (*HALpPtTable_Flash_Read) (uint32_t addr,uint8_t *data, uint32_t len); - -void hal_boot2_set_ptable_opt(HALpPtTable_Flash_Erase erase, HALpPtTable_Flash_Write write); -int hal_boot2_partition_bus_addr_active(const char *name, uint32_t *addr, uint32_t *size); -int hal_boot2_partition_bus_addr_inactive(const char *name, uint32_t *addr, uint32_t *size); -int hal_boot2_partition_bus_addr(const char *name, uint32_t *addr0, uint32_t *addr1, uint32_t *size0, uint32_t *size1, int *active); -int hal_boot2_partition_addr_active(const char *name, uint32_t *addr, uint32_t *size); -int hal_boot2_partition_addr_inactive(const char *name, uint32_t *addr, uint32_t *size); -int hal_boot2_partition_addr(const char *name, uint32_t *addr0, uint32_t *addr1, uint32_t *size0, uint32_t *size1, int *active); -uint8_t hal_boot2_get_active_partition(void); -int hal_boot2_get_active_entries(int type, HALPartition_Entry_Config *ptEntry); -int hal_boot2_update_ptable(HALPartition_Entry_Config *ptEntry); -int hal_boot2_dump(void); -int hal_boot2_init(void); -void hal_update_mfg_ptable(void); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_common.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_common.h deleted file mode 100644 index d570eea05c..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_common.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __HAL_COMMON__H__ -#define __HAL_COMMON__H__ - -#include "bl808_common.h" - -void cpu_global_irq_enable(void); -void cpu_global_irq_disable(void); -void hal_por_reset(void); -void hal_system_reset(void); -void hal_cpu_reset(void); -void hal_get_chip_id(uint8_t chip_id[8]); -void hal_dcache_clean_all(void); -void hal_dcache_invalid_all(void); -void hal_dcache_clean_invalid_all(void); -void hal_dcache_clean_byaddr(uintptr_t addr, uint32_t len); -void hal_dcache_invalid_byaddr(uintptr_t addr, uint32_t len); -void hal_dcache_clean_invalid_byaddr(uintptr_t addr, uint32_t len); -void *hal_ioalloc(size_t size); -void hal_iofree(void *addr); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_emac.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_emac.c deleted file mode 100644 index 8e528c2ac7..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_emac.c +++ /dev/null @@ -1,666 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "bl808_emac.h" -#include "bl_irq.h" -#include "bl808_glb.h" -#include "hal_emac.h" -#include "bl808_l1c.h" -#if CTX_TYPE -#include -#include -#endif - -#define EMAC_USE_INSIDE_CLOCK (0) -#define TAG "EMAC_BD: " -#define EMAC_USED_ID EMAC0_ID - -static const uint32_t emacAddr[EMAC_ID_MAX] = { EMAC_BASE }; - -#ifdef EMAC_DBG -#define MSG printf -#else -#define MSG(...) ((void)0) -#endif -#define EMAC_DO_FLUSH_DATA 1 - -#if CTX_TYPE -extern TaskHandle_t DequeueTaskHandle; -#endif -static EMAC_Handle_Type ethHandle; -EMAC_Handle_Type *thiz = NULL; - -/** - * @brief - * - */ -static void emac_gpio_init(void) -{ - uint8_t emacPins[] = { GLB_GPIO_PIN_24, GLB_GPIO_PIN_25, GLB_GPIO_PIN_26, - GLB_GPIO_PIN_27, GLB_GPIO_PIN_28, GLB_GPIO_PIN_29, - GLB_GPIO_PIN_30, GLB_GPIO_PIN_31, GLB_GPIO_PIN_32, - GLB_GPIO_PIN_33 }; - - GLB_GPIO_Func_Init(GPIO_FUN_ETHER_MAC, (GLB_GPIO_Type *)emacPins, sizeof(emacPins)); -} - -/** - * @brief - * - * @param bdt - * @return int - */ -static uint32_t emac_bd_get_cur_active(EMAC_BD_TYPE_e bdt) -{ - uint32_t bd = 0; - - EMAC_GetBD(EMAC_USED_ID, &bd); - - if (bdt == EMAC_BD_TYPE_TX) { - bd &= EMAC_TXBDPTR_MSK; - bd >>= EMAC_TXBDPTR_POS; - } - - if (bdt == EMAC_BD_TYPE_RX) { - bd &= EMAC_RXBDPTR_MSK; - bd >>= EMAC_RXBDPTR_POS; - } - - return bd; -} - -/** - * @brief - * - * @param index - * @return int - */ -static int emac_bd_rx_enqueue(uint32_t index) -{ - BL_Err_Type err = SUCCESS; - - thiz->rxIndexEMAC = index; - - return err; -} - -/** - * @brief - * - * @param index - * @return int - */ -static void emac_bd_rx_on_err(uint32_t index) -{ - /* handle error */ - if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(RX_OR)) { - MSG("EMAC RX OR Error at %s:%d\r\n", __func__, __LINE__); - } - - if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(RX_RE)) { - MSG("MAC RX RE Error at %s:%d\r\n", __func__, __LINE__); - } - - if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(RX_DN)) { - MSG("MAC RX DN Error at %s:%d\r\n", __func__, __LINE__); - } - - if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(RX_TL)) { - MSG("MAC RX TL Error at %s:%d\r\n", __func__, __LINE__); - } - - if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(RX_CRC)) { - MSG("MAC RX CRC Error at %s:%d\r\n", __func__, __LINE__); - } - - if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(RX_LC)) { - MSG("MAC RX LC Error at %s:%d\r\n", __func__, __LINE__); - } - - thiz->bd[index].C_S_L &= ~0xff; - /* RX BD is ready for RX */ - thiz->bd[index].C_S_L |= EMAC_BD_FIELD_MSK(RX_E); -} - -/** - * @brief this func will be called in ISR - * - * @param index - * @return int - */ -static int emac_bd_tx_dequeue(uint32_t index) -{ - BL_Err_Type err = SUCCESS; - EMAC_BD_Desc_Type *DMADesc; - - thiz->txIndexEMAC = index; - DMADesc = &thiz->bd[thiz->txIndexEMAC]; - /* release this tx BD to SW (HW will do this) */ - DMADesc->C_S_L &= EMAC_BD_FIELD_UMSK(TX_RD); - - return err; -} - -/** - * @brief - * - * @param index - * @return int - */ -static void emac_bd_tx_on_err(uint32_t index) -{ - /* handle error */ - if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(TX_UR)) { - MSG("%s:%d\r\n", __func__, __LINE__); - } - - if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(TX_RTRY)) { - MSG("%s:%d\r\n", __func__, __LINE__); - } - - if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(TX_RL)) { - MSG("%s:%d\r\n", __func__, __LINE__); - } - - if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(TX_LC)) { - MSG("%s:%d\r\n", __func__, __LINE__); - } - - if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(TX_DF)) { - MSG("%s:%d\r\n", __func__, __LINE__); - } - - if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(TX_CS)) { - MSG("%s:%d\r\n", __func__, __LINE__); - } - - thiz->bd[index].C_S_L &= ~0xff; -} - -/** - * @brief - * - */ -__WEAK void emac_tx_done_callback_app(void) -{ -} - -/** - * @brief - * - */ -static void emac_tx_done_callback(void) -{ -#if CTX_TYPE - BaseType_t xHigherPriorityTaskWoken = pdFALSE; - - xTaskNotifyFromISR(DequeueTaskHandle, 0x01, eSetBits, &xHigherPriorityTaskWoken); - portYIELD_FROM_ISR(xHigherPriorityTaskWoken); -#else - uint32_t index = 0; - index = emac_bd_get_cur_active(EMAC_BD_TYPE_TX); - - emac_bd_tx_dequeue(index); - - emac_tx_done_callback_app(); -#endif -} - -/** - * @brief - * - */ -__WEAK void emac_tx_error_callback_app(void) -{ - puts("Tx error\r\n"); -} - -/** - * @brief - * - */ -static void emac_tx_error_callback(void) -{ - uint32_t index = 0; - - index = emac_bd_get_cur_active(EMAC_BD_TYPE_TX); - emac_bd_tx_on_err(index); - emac_tx_error_callback_app(); -} - -/** - * @brief - * - */ -__WEAK void emac_rx_done_callback_app(void) -{ -} - -/** - * @brief - * - */ -static void emac_rx_done_callback(void) -{ -#if CTX_TYPE - BaseType_t xHigherPriorityTaskWoken = pdFALSE; - - xTaskNotifyFromISR(DequeueTaskHandle, 0x02, eSetBits, &xHigherPriorityTaskWoken); - portYIELD_FROM_ISR(xHigherPriorityTaskWoken); -#else - uint32_t index = 0; - - index = emac_bd_get_cur_active(EMAC_BD_TYPE_RX); - - emac_bd_rx_enqueue(index); - - emac_rx_done_callback_app(); -#endif -} - -/** - * @brief - * - */ -__WEAK void emac_rx_error_callback_app(void) -{ - puts("Rx error\r\n"); -} - -/** - * @brief - * - */ -static void emac_rx_error_callback(void) -{ - uint32_t index; - - index = emac_bd_get_cur_active(EMAC_BD_TYPE_RX); - - emac_bd_rx_on_err(index); - - emac_rx_error_callback_app(); -} - -/** - * @brief - * - */ -__WEAK void emac_rx_busy_callback_app(void) -{ -} - -/** - * @brief - * - */ -static void emac_rx_busy_callback(void) -{ - MSG("EMAC Rx busy at %s:%d\r\n", __func__, __LINE__); - emac_rx_busy_callback_app(); -} - -void emac_irq_process(void) -{ - EMAC_ID_Type emacId = EMAC_USED_ID; - uint32_t tmpVal; - uint32_t EMACx = emacAddr[emacId]; - - tmpVal = BL_RD_REG(EMACx,EMAC_INT_MASK); - - if (SET == EMAC_GetIntStatus(emacId,EMAC_INT_TX_DONE) && !BL_IS_REG_BIT_SET(tmpVal,EMAC_TXB_M)) { - EMAC_ClrIntStatus(emacId,EMAC_INT_TX_DONE); - EMAC_IntMask(emacId, EMAC_INT_TX_DONE, MASK); - emac_tx_done_callback(); - } - - if (SET == EMAC_GetIntStatus(emacId,EMAC_INT_TX_ERROR) && !BL_IS_REG_BIT_SET(tmpVal,EMAC_TXE_M)) { - EMAC_ClrIntStatus(emacId,EMAC_INT_TX_ERROR); - emac_tx_error_callback(); - } - - if (SET == EMAC_GetIntStatus(emacId,EMAC_INT_RX_DONE) && !BL_IS_REG_BIT_SET(tmpVal,EMAC_RXB_M)) { - EMAC_ClrIntStatus(emacId,EMAC_INT_RX_DONE); - EMAC_IntMask(emacId, EMAC_INT_RX_DONE, MASK); - emac_rx_done_callback(); - } - - if (SET == EMAC_GetIntStatus(emacId,EMAC_INT_RX_ERROR) && !BL_IS_REG_BIT_SET(tmpVal,EMAC_RXE_M)) { - EMAC_ClrIntStatus(emacId,EMAC_INT_RX_ERROR); - emac_rx_error_callback(); - } - - if (SET == EMAC_GetIntStatus(emacId,EMAC_INT_RX_BUSY) && !BL_IS_REG_BIT_SET(tmpVal,EMAC_BUSY_M)) { - EMAC_ClrIntStatus(emacId,EMAC_INT_RX_BUSY); - emac_rx_busy_callback(); - } - - if (SET == EMAC_GetIntStatus(emacId,EMAC_INT_TX_CTRL) && !BL_IS_REG_BIT_SET(tmpVal,EMAC_TXC_M)) { - EMAC_ClrIntStatus(emacId,EMAC_INT_TX_CTRL); - } - - if (SET == EMAC_GetIntStatus(emacId,EMAC_INT_RX_CTRL) && !BL_IS_REG_BIT_SET(tmpVal,EMAC_RXC_M)) { - EMAC_ClrIntStatus(emacId,EMAC_INT_RX_CTRL); - } -} - -void EMAC_Interrupt_Init(void) -{ - MSG("EMAC_Interrupt_Init.\r\n"); - bl_irq_register(EMAC_IRQn, emac_irq_process); - bl_irq_enable(EMAC_IRQn); - - EMAC_ClrIntStatus(EMAC_USED_ID,EMAC_INT_ALL); - EMAC_IntMask(EMAC_USED_ID,EMAC_INT_ALL, UNMASK); - MSG("emac_intmask.\r\n"); -} -/** - * @brief - * - * @param emac_cfg - * @return int - */ -int emac_init(emac_device_t *emac_cfg) -{ - EMAC_CFG_Type emacCfg = { - .recvSmallFrame = ENABLE, /*!< Receive small frmae or not */ - .recvHugeFrame = DISABLE, /*!< Receive huge frmae(>64K bytes) or not */ - .padEnable = ENABLE, /*!< Enable padding for frame which is less than MINFL or not */ - .crcEnable = ENABLE, /*!< Enable hardware CRC or not */ - .noPreamble = DISABLE, /*!< Enable preamble or not */ - .recvBroadCast = ENABLE, /*!< Receive broadcast frame or not */ - .interFrameGapCheck = ENABLE, /*!< Check inter frame gap or not */ - .miiNoPreamble = ENABLE, /*!< Enable MII interface preamble or not */ - .miiClkDiv = 49, /*!< MII interface clock divider from bus clock */ - .maxTxRetry = 16, /*!< Maximum tx retry count */ - .interFrameGapValue = 24, /*!< Inter frame gap vaule in clock cycles(default 24)*/ - .minFrameLen = 64, /*!< Minimum frame length */ - .maxFrameLen = ETH_MAX_PACKET_SIZE, /*!< Maximum frame length */ - .collisionValid = 16, /*!< Collision valid value */ - .macAddr[0] = 0x18, /*!< MAC Address */ - .macAddr[1] = 0xB0, - .macAddr[2] = 0x09, - .macAddr[3] = 0x00, - .macAddr[4] = 0x12, - .macAddr[5] = 0x34, - }; - BL_Err_Type err = SUCCESS; - - /* init emac giio */ - emac_gpio_init(); - - memcpy(emacCfg.macAddr, emac_cfg->mac_addr, 6); - GLB_PER_Clock_UnGate(1<<12); -#if EMAC_USE_INSIDE_CLOCK - /* 50MHZ clock is from uhs pll */ - GLB_Set_ETH_REF_O_CLK_Sel(GLB_ETH_REF_CLK_OUT_INSIDE_50M); -#else - GLB_Set_ETH_REF_O_CLK_Sel(GLB_ETH_REF_CLK_OUT_OUTSIDE_50M); -#endif - //GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_EMAC); - GLB_PER_Clock_UnGate(1<<12); - //GLB_Invert_ETH_RX_CLK(0); - //GLB_Invert_ETH_TX_CLK(0); - EMAC_Init(EMAC_USED_ID,&emacCfg); - - EMAC_Interrupt_Init(); - return err; -} - -/** - * @brief - * - * @param eth_tx_buff - * @param tx_buf_count - * @param eth_rx_buff - * @param rx_buf_count - * @return int - */ -int emac_bd_init(uint8_t *eth_tx_buff, uint8_t tx_buf_count, uint8_t *eth_rx_buff, uint8_t rx_buf_count) -{ - BL_Err_Type err = SUCCESS; - thiz = ðHandle; - - /* init the BDs in emac with buffer address */ - err = EMAC_DMADescListInit(EMAC_USED_ID,thiz, (uint8_t *)eth_tx_buff, tx_buf_count, - (uint8_t *)eth_rx_buff, rx_buf_count); - return err; -} - -/** - * @brief - * - * @param none - * @return int - */ -int emac_bd_fragment_support(void){ - return 1; -} - -/** - * @brief - * - * @param flags - * @param len - * @param data_in - * @return int - */ -//uint32_t tmpbuf[400]; -int emac_bd_tx_enqueue(uint32_t flags, uint32_t len, const uint8_t *data_in) -{ - BL_Err_Type err = SUCCESS; - EMAC_BD_Desc_Type *DMADesc; - uint32_t tx_flags=EMAC_TX_COMMON_FLAGS; - DMADesc = &thiz->bd[thiz->txIndexCPU]; - - if (flags&EMAC_FRAGMENT_PACKET) { - /* Fragment packet, clear EOF */ - tx_flags &= EMAC_BD_FIELD_UMSK(TX_EOF); - } - - if (DMADesc->C_S_L & EMAC_BD_FIELD_MSK(TX_RD)) { - /* no free BD, lost sync with DMA TX? */ - err = NORESC; - //MSG(TAG"%s:%d\n", __func__, __LINE__); - } else { - __DSB(); - // MSG("tx q flags:%d,len:%d,data:0x%x\r\n", flags, len, data_in); - if (flags&EMAC_NOCOPY_PACKET) { - DMADesc->Buffer = (uint32_t)data_in; - }else{ - ARCH_MemCpy_Fast((void *)DMADesc->Buffer, data_in, len); - } - - /* following two lines is for cache test since tmpbuf is in cache range */ - //ARCH_MemCpy_Fast(tmpbuf, data_in, len); - //DMADesc->Buffer = (uint32_t)tmpbuf; -#ifdef EMAC_DO_FLUSH_DATA - if(L1C_Is_DCache_Range((uintptr_t)DMADesc->Buffer)){ - L1C_DCache_Clean_By_Addr((uintptr_t)DMADesc->Buffer,len); - } -#endif - DMADesc->C_S_L = tx_flags | (len << BD_TX_LEN_POS); - - /* move to next TX BD */ - if ((++thiz->txIndexCPU) > thiz->txBuffLimit) { - /* the last BD */ - DMADesc->C_S_L |= EMAC_BD_FIELD_MSK(TX_WR); - /* wrap back */ - thiz->txIndexCPU = 0; - } - } - - return err; -} - -/** - * @brief - * - * @param flags - * @param len - * @param data_out - * @return int - */ -int emac_bd_rx_dequeue(uint32_t flags, uint32_t *len, uint8_t *data_out) -{ - BL_Err_Type err = SUCCESS; - EMAC_BD_Desc_Type *DMADesc; - - DMADesc = &thiz->bd[thiz->rxIndexCPU]; - - if (DMADesc->C_S_L & EMAC_BD_FIELD_MSK(RX_E)) { - /* current RX BD is empty */ - err = NORESC; - *len = 0; - } else { - *len = (thiz->bd[thiz->rxIndexCPU].C_S_L & EMAC_BD_FIELD_MSK(RX_LEN)) >> BD_RX_LEN_POS; -#ifdef EMAC_DO_FLUSH_DATA - if(L1C_Is_DCache_Range((uintptr_t)DMADesc->Buffer)){ - L1C_DCache_Invalid_By_Addr((uintptr_t)DMADesc->Buffer, *len); - } -#endif - if (data_out) { - ARCH_MemCpy_Fast(data_out, (const void *)(uintptr_t)DMADesc->Buffer, *len); - } - - /* RX BD can be used for another receive */ - DMADesc->C_S_L |= EMAC_BD_FIELD_MSK(RX_E); - - /* move to next RX BD */ - if ((++thiz->rxIndexCPU) > thiz->rxBuffLimit) { - /* the last BD */ - DMADesc->C_S_L |= EMAC_BD_FIELD_MSK(RX_WR); - /* wrap back */ - thiz->rxIndexCPU = thiz->txBuffLimit + 1; - } - } - - return err; -} - -/** - * @brief - * - * @param phyAddress - * @return int - */ -int emac_phy_set_address(uint16_t phyAddress) -{ - EMAC_Phy_SetAddress(EMAC_USED_ID,phyAddress); - - return 0; -} - -/** - * @brief - * - * @param fullDuplex - * @return int - */ -int emac_phy_config_full_duplex(uint8_t fullDuplex) -{ - EMAC_Phy_Set_Full_Duplex(EMAC_USED_ID,fullDuplex); - - return 0; -} - -/** - * @brief - * - * @param phyReg - * @param regValue - * @return int - */ -int emac_phy_reg_read(uint16_t phyReg, uint16_t *regValue) -{ - if (EMAC_Phy_Read(EMAC_USED_ID,phyReg, regValue) != SUCCESS) { - return -1; - } - - return 0; -} - -/** - * @brief - * - * @param phyReg - * @param regValue - * @return int - */ -int emac_phy_reg_write(uint16_t phyReg, uint16_t regValue) -{ - if (EMAC_Phy_Write(EMAC_USED_ID,phyReg, regValue) != SUCCESS) { - return -1; - } - - return 0; -} - -int emac_stop(void) -{ - return EMAC_Disable(EMAC_USED_ID); -} - -int emac_start(void) -{ - EMAC_Enable(EMAC_USED_ID); - return 0; -} - -int emac_start_tx(void) -{ - return EMAC_Enable_TX(EMAC_USED_ID); -} - -int emac_stop_tx(void) -{ - return EMAC_Disable_TX(EMAC_USED_ID); -} - -int emac_start_rx(void) -{ - return EMAC_Enable_RX(EMAC_USED_ID); -} - -int emac_stop_rx(void) -{ - return EMAC_Disable_RX(EMAC_USED_ID); -} - -int emac_intmask(EMAC_INT_Type intType, BL_Mask_Type intMask) -{ - return EMAC_IntMask(EMAC_USED_ID,intType, intMask); -} - -int emac_get_fram_len(uint16_t *max, uint16_t *min) -{ - return EMAC_GetFramLen(EMAC_USED_ID, max, min); -} - diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_emac.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_emac.h deleted file mode 100644 index a6d91b34b6..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_emac.h +++ /dev/null @@ -1,127 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __HAL_EMAC_H__ -#define __HAL_EMAC_H__ - -#include "hal_common.h" -#include "drv_device.h" -// #include "bl808_config.h" -#include "bl808_emac.h" - -#define CTX_TYPE 1 - -#define MSG(a,...) printf(a,##__VA_ARGS__) -// #define MSG_DBG(a,...) printf(a,##__VA_ARGS__) -// #define MSG_WAR(a,...) printf(a,##__VA_ARGS__) -// #define MSG_ERR(a,...) printf(a,##__VA_ARGS__) -#define BL_CASE_FAIL {MSG(" Case Fail\r\n");while(1){}} -#define BL_CASE_SUCCESS {MSG(" Case Success\r\n");while(1){}} - -typedef struct emac_device { - struct device parent; - uint8_t mac_addr[6]; /*!< mac address */ -} emac_device_t; - -/** - * @brief EMAC PHY configuration type definition - */ -typedef struct -{ - uint8_t auto_negotiation; /*!< Speed and mode auto negotiation */ - uint8_t full_duplex; /*!< Duplex mode */ -#define PHY_STATE_DOWN (0) /* PHY is not usable */ -#define PHY_STATE_READY (1) /* PHY is OK, wait for controller */ -#define PHY_STATE_UP (2) /* Network is ready for TX/RX */ -#define PHY_STATE_RUNNING (3) /* working */ -#define PHY_STATE_NOLINK (4) /* no cable connected */ -#define PHY_STATE_STOPPED (5) /* PHY has been stopped */ -#define PHY_STATE_TESTING (6) /* in test mode */ - uint8_t phy_state; /*!< down,ready,up,running,nolink,halted */ - uint8_t use_irq; /*!< 0: no IRQ used */ - uint16_t speed; /*!< Speed mode */ - uint16_t phy_address; /*!< PHY address */ - uint32_t phy_id; /*!< PHY OUI */ -} emac_phy_cfg_t; - -#define EMAC_NORMAL_PACKET (uint32_t)(0) -#define EMAC_FRAGMENT_PACKET (uint32_t)(0x01) -#define EMAC_NOCOPY_PACKET (uint32_t)(0x02) - -#ifndef ETH_TX_BUFFER_SIZE -#define ETH_TX_BUFFER_SIZE (ETH_MAX_PACKET_SIZE) -#endif - -#ifndef ETH_RX_BUFFER_SIZE -#define ETH_RX_BUFFER_SIZE (ETH_MAX_PACKET_SIZE) -#endif - -#define EMAC_TX_COMMON_FLAGS (EMAC_BD_FIELD_MSK(TX_RD) | \ - EMAC_BD_FIELD_MSK(TX_IRQ) | \ - EMAC_BD_FIELD_MSK(TX_PAD) | \ - EMAC_BD_FIELD_MSK(TX_CRC) | \ - EMAC_BD_FIELD_MSK(TX_EOF)) - -#define EMAC_RX_COMMON_FLAGS (ETH_MAX_PACKET_SIZE << 16) | \ - EMAC_BD_FIELD_MSK(RX_IRQ) ) - -typedef enum _BD_TYPE_ { - EMAC_BD_TYPE_INVLAID, - EMAC_BD_TYPE_TX, - EMAC_BD_TYPE_RX, - EMAC_BD_TYPE_NONE, - EMAC_BD_TYPE_MAX = 0x7FFFFFFF -} EMAC_BD_TYPE_e; - -int emac_init(emac_device_t *emac_cfg); -int emac_bd_init(uint8_t *ethTxBuff, uint8_t txBufCount, uint8_t *ethRxBuff, uint8_t rxBufCount); -int emac_bd_fragment_support(void); -int emac_bd_tx_enqueue(uint32_t flags, uint32_t len, const uint8_t *data_in); -int emac_bd_rx_dequeue(uint32_t flags, uint32_t *len, uint8_t *data_out); -__WEAK void emac_rx_done_callback_app(void); -__WEAK void emac_rx_error_callback_app(void); -__WEAK void emac_rx_busy_callback_app(void); -__WEAK void emac_tx_error_callback_app(void); -__WEAK void emac_tx_done_callback_app(void); -int emac_phy_set_address(uint16_t phyAddress); -int emac_phy_config_full_duplex(uint8_t fullDuplex); -int emac_phy_reg_read(uint16_t phyReg, uint16_t *regValue); -int emac_phy_reg_write(uint16_t phyReg, uint16_t regValue); -int emac_stop(void); -int emac_start(void); -int emac_start_tx(void); -int emac_stop_tx(void); -int emac_start_rx(void); -int emac_stop_rx(void); -int emac_intmask(EMAC_INT_Type intType, BL_Mask_Type intMask); -int emac_get_fram_len(uint16_t *max, uint16_t *min); -BL_Err_Type EMAC_GetFramLen(EMAC_ID_Type emacId, uint16_t * max, uint16_t *min); -BL_Err_Type EMAC_GetBD(EMAC_ID_Type emacId, uint32_t *bd); -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_sdh.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_sdh.c deleted file mode 100644 index dcdc201d35..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_sdh.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include -#include "bl_sdh.h" -#include "hal_sdh.h" - -static sd_card_t gSDCardInfo; -static uint32_t sdio_bus_width = SDH_DATA_BUS_WIDTH_1BIT; - -int32_t hal_sd_init(sd_dev_t *sd) -{ - static uint8_t inited = 0; - - if (inited == 0) { - if (SDH_Init(sdio_bus_width, &gSDCardInfo) == SD_OK) { - inited = 1; - return 0; - } else { - return -1; - } - } - - return 0; -} - -void hal_sd_bus_4bits_enable() -{ - sdio_bus_width = SDH_DATA_BUS_WIDTH_4BITS; -} - -int32_t hal_sd_stat_get(sd_dev_t *sd, hal_sd_stat *stat) -{ - *stat = SD_STAT_TRANSFER; - return 0; -} - -int32_t hal_sd_blks_read(sd_dev_t *sd, uint8_t *data, uint32_t blk_addr, uint32_t blks, uint32_t timeout) -{ - if (SD_OK == SDH_ReadMultiBlocks(data, blk_addr, gSDCardInfo.blockSize, blks)) { - return 0; - } else { - return -1; - } -} - -int32_t hal_sd_blks_write(sd_dev_t *sd, uint8_t *data, uint32_t blk_addr, uint32_t blks, uint32_t timeout) -{ - if (SD_OK == SDH_WriteMultiBlocks(data, blk_addr, gSDCardInfo.blockSize, blks)) { - return 0; - } else { - return -1; - } -} - -int32_t hal_sd_info_get(sd_dev_t *sd, hal_sd_info_t *info) -{ - - info->blk_nums = gSDCardInfo.blockCount; - info->blk_size = gSDCardInfo.blockSize; - - return 0; -} - diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_sdh.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_sdh.h deleted file mode 100644 index 30801aab28..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_sdh.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __HAL_SDH_H__ -#define __HAL_SDH_H__ -void hal_sd_bus_4bits_enable(); -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_sys.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_sys.c deleted file mode 100644 index e0756ae4b9..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_sys.c +++ /dev/null @@ -1,139 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include - -#include "bl_sys.h" -#include "hal_sys.h" - -void hal_reboot() -{ - bl_sys_reset_por(); -} - -void hal_sys_reset() -{ - //bl_sys_reset_system(); -} - -void hal_poweroff() -{ - /*TODO empty now*/ -} - -#if 0 -static uint32_t user_clz(uint32_t priorities) -{ - return __builtin_clz(priorities); -} - -struct romapi_freertos_map* hal_sys_romapi_get(void) -{ - extern uint8_t __global_pointer_head$; - uint32_t *gp_data_start = (uint32_t*)(&__global_pointer_head$); - struct romapi_freertos_map* romapi_freertos; - - puts(" Configuring Version 1.0 ROM API...\r\n"); - - /*clear bss/common section in GP aera*/ - memset(&__global_pointer_head$, 0, 0x498); - romapi_freertos = (struct romapi_freertos_map*) (((uint8_t*)gp_data_start) + 0x45c); - - /* pTrapNetCounter */ - *(gp_data_start + 0) = (uint32_t)((uint8_t*)(gp_data_start) + 0x58); - /* pullNextTime */ - *(gp_data_start + 1) = (uint32_t)((uint8_t*)(gp_data_start) + 0x60); - /* system tick */ - *(gp_data_start + 2) = 32 * 1000 / 1000;//Use 32K - - return romapi_freertos; -} - -void hal_sys_romapi_update(struct romapi_freertos_map *romapi_freertos) -{ - extern void interrupt_entry(uint32_t mcause); - extern void exception_entry(uint32_t mcause, uint32_t mepc, uint32_t mtval); - extern uint8_t __freertos_irq_stack_top; - - romapi_freertos->interrupt_entry_ptr = interrupt_entry; - romapi_freertos->rtos_sprintf = sprintf; - romapi_freertos->rtos_memcpy_ptr = memcpy; - romapi_freertos->rtos_strlen_ptr = strlen; - romapi_freertos->rtos_memset_ptr = memset; - romapi_freertos->exception_entry_ptr = exception_entry; - romapi_freertos->rtos_strcpy_ptr = strcpy; - romapi_freertos->xISRStackTop = &__freertos_irq_stack_top; - romapi_freertos->rtos_clz = user_clz; -} -#endif -void hal_sys_capcode_update(uint8_t capin, uint8_t capout) -{ - //TODO FPGA no capcode -#if 0 - static uint8_t capin_static, capout_static; - - if (255 != capin && 255 != capout) { - RomDriver_AON_Set_Xtal_CapCode(capin, capout); - capin_static = capin; - capout_static = capout; - } else { - RomDriver_AON_Set_Xtal_CapCode(capin_static, capout_static); - } -#endif -} - -uint8_t hal_sys_capcode_get(void) -{ - return 0; - // return AON_Get_Xtal_CapCode(); -} - -void hal_sys_mtimer_div(void) -{ - *(volatile uint32_t *)0x20009014 = 0x80000004; -} -void hal_enable_cpu0(void) -{ - bl_enable_cpu0(); -} - -void hal_boot_cpu0(uint32_t start_addr) -{ - bl_boot_cpu0(start_addr); -} - -void hal_halt_cpu0(void) -{ - bl_halt_cpu0(); -} - -void hal_release_cpu0(void) -{ - bl_release_cpu0(); -} diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_sys.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_sys.h deleted file mode 100644 index b78b98de28..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_sys.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __HAL_SYS_H__ -#define __HAL_SYS_H__ - -#include - -void hal_reboot(); -void hal_sys_reset(); -void hal_poweroff(); - -struct romapi_freertos_map -{ - void *vApplicationIdleHook; - void *interrupt_entry_ptr; - void *vApplicationGetIdleTaskMemory; - void *vApplicationStackOverflowHook; - void *vApplicationGetTimerTaskMemory; - void *rtos_sprintf; - void *vApplicationMallocFailedHook; - void *rtos_memcpy_ptr; - void *vAssertCalled; - void *rtos_strlen_ptr; - void *rtos_memset_ptr; - void *rtos_clz; - void *exception_entry_ptr; - void *rtos_strcpy_ptr; - void *xISRStackTop; -}; -struct romapi_freertos_map* hal_sys_romapi_get(void); -void hal_sys_romapi_update(struct romapi_freertos_map *romapi); - -void hal_sys_capcode_update(uint8_t capin, uint8_t capout); -uint8_t hal_sys_capcode_get(void); -void hal_sys_mtimer_div(void); -void hal_enable_cpu0(void); -void hal_boot_cpu0(uint32_t start_addr); -void hal_halt_cpu0(void); -void hal_release_cpu0(void); -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_uart.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_uart.c deleted file mode 100644 index 220c54b62b..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_uart.c +++ /dev/null @@ -1,284 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include -#include -#include -#include - -#include "bl_uart.h" -#include "hal_uart.h" - -#include - -typedef struct uart_priv_data { - aos_mutex_t mutex; -} uart_priv_data_t; - -static int8_t inited; -static uart_dev_t *dev_uart0 = NULL; -static uart_dev_t *dev_uart1 = NULL; -static uart_dev_t *dev_uart2 = NULL; -static uart_dev_t *dev_uart3 = NULL; - -static int uart_dev_malloc(uart_dev_t **pdev) -{ - if (*pdev) { - blog_error("arg err.\r\n"); - return -1; - } - - *pdev = pvPortMalloc(sizeof(uart_dev_t)); - if (*pdev == 0) { - blog_error("mem err.\r\n"); - return -1; - } - memset(*pdev, 0, sizeof(uart_dev_t)); - - (*pdev)->read_block_flag = UART_READ_CFG_NOBLOCK; - (*pdev)->priv = NULL; - (*pdev)->priv = pvPortMalloc(sizeof(uart_priv_data_t)); - if ((*pdev)->priv == NULL) { - blog_error("mem err.\r\n"); - return -1; - } - memset((*pdev)->priv, 0, sizeof(uart_priv_data_t)); - - return 0; -} - -static void uart_dev_setdef(uart_dev_t **pdev, uint8_t id) -{ - if (*pdev == NULL) { - blog_error("mem err.\r\n"); - return; - } - - (*pdev)->port = id; - (*pdev)->read_block_flag = UART_READ_CFG_NOBLOCK; - - (*pdev)->config.baud_rate = 2000000; - (*pdev)->config.data_width = DATA_WIDTH_8BIT; - (*pdev)->config.parity = NO_PARITY; - (*pdev)->config.stop_bits = STOP_BITS_1; - (*pdev)->config.flow_control = FLOW_CONTROL_DISABLED; - (*pdev)->config.mode = MODE_TX_RX; -} - -static int dev_uart_init(uint8_t id, const char *path, uint32_t rx_buf_size, uint32_t tx_buf_size) -{ - uart_dev_t **pdev = NULL; - int ret; - - if ((id >= 4) || (path == 0)) { - blog_error("arg err.\r\n"); - return -1; - } - - switch (id) { - case 0: - { - pdev = &dev_uart0; - } break; - case 1: - { - pdev = &dev_uart1; - } break; - case 2: - { - pdev = &dev_uart2; - } break; - case 3: - { - pdev = &dev_uart3; - } break; - default: - { - blog_error("err.\r\n"); - return -1; - } break; - } - - if (uart_dev_malloc(pdev) != 0) { - return -1; - } - (*pdev)->rx_buf_size = rx_buf_size; - (*pdev)->tx_buf_size = tx_buf_size; - // (*pdev)->ring_rx_buffer = pvPortMalloc((*pdev)->rx_buf_size); - // (*pdev)->ring_tx_buffer = pvPortMalloc((*pdev)->tx_buf_size); - - // if ((*pdev)->ring_rx_buffe == NULL || (*pdev)->ring_rx_buffe == NULL ) { - // return -1; - // } - - uart_dev_setdef(pdev, id); - ret = aos_register_driver(path, &uart_ops, *pdev); - if (ret != VFS_SUCCESS) { - return ret; - } - - return 0; -} - -int32_t hal_uart_send_trigger(uart_dev_t *uart) -{ - bl_uart_int_tx_enable(uart->port); - return 0; -} - -int32_t hal_uart_send_trigger_off(uart_dev_t *uart) -{ - bl_uart_int_tx_disable(uart->port); - return 0; -} - -int32_t hal_uart_init(uart_dev_t *uart) -{ - uart_priv_data_t *data; - uint8_t parity; - - data = uart->priv; - if (aos_mutex_new(&(data->mutex))) { - /*we should assert here?*/ - return -1; - } - - bl_uart_getdefconfig(uart->port, &parity); - - if (parity == UART_PARITY_NONE) { - uart->config.parity = NO_PARITY; - } else if (parity == UART_PARITY_ODD) { - uart->config.parity = ODD_PARITY; - } else { - uart->config.parity = EVEN_PARITY; - } - - bl_uart_int_enable(uart->port); - - return 0; -} - -int vfs_uart_init_simple_mode(uint8_t id, uint8_t pin_tx, uint8_t pin_rx, int baudrate, const char *path) -{ - //bl_uart_flush(id); - - bl_uart_init(id, pin_tx, pin_rx, 255, 255, baudrate); - - if (dev_uart_init(id, path, 128, 128) != 0) { - blog_error("dev_uart_init err.\r\n"); - } - - return 0; -} - -int vfs_uart_init(uint32_t fdt, uint32_t dtb_uart_offset) -{ - dev_uart_init(0, "/dev/ttyS0", 512, 512); - return 0; -} - -int32_t hal_uart_recv_II(uart_dev_t *uart, void *data, uint32_t expect_size, uint32_t *recv_size, uint32_t timeout) -{ - int ch; - uint32_t counter = 0; - - while (counter < expect_size && (ch = bl_uart_data_recv(uart->port)) >= 0) { - ((uint8_t*)data)[counter] = ch; - counter++; - } - - *recv_size = counter; - return 0; -} - -int32_t hal_uart_send(uart_dev_t *uart, const void *data, uint32_t size, uint32_t timeout) -{ - uint32_t i = 0; - - while (i < size) { - bl_uart_data_send(uart->port, ((uint8_t*)data)[i]); - i++; - } - return 0; -} - -int32_t hal_uart_send_flush(uart_dev_t *uart, uint32_t timeout) -{ - bl_uart_flush(uart->port); - return 0; -} - -void hal_uart_setbaud(uart_dev_t *uart, uint32_t baud) -{ - bl_uart_setbaud(uart->port, baud); -} - -void hal_uart_setconfig(uart_dev_t *uart, uint32_t baud, hal_uart_parity_t parity) -{ - bl_uart_setconfig(uart->port, baud, parity); -} - -int32_t hal_uart_finalize(uart_dev_t *uart) -{ - uart_priv_data_t *data; - - data = uart->priv; - bl_uart_int_disable(uart->port); - aos_mutex_free(&(data->mutex)); - return 0; -} - -/*TODO better glue for ring buffer?*/ -int32_t hal_uart_notify_register(uart_dev_t *uart, hal_uart_int_t type, void (*cb)(void *arg)) -{ - if (type == UART_TX_INT) { - bl_uart_int_tx_notify_register(uart->port, cb, uart); - } else if (type == UART_RX_INT) { - bl_uart_int_rx_notify_register(uart->port, cb, uart); - } else { - return -1; - } - - return 0; -} - -int32_t hal_uart_notify_unregister(uart_dev_t *uart, hal_uart_int_t type, void (*cb)(void *arg)) -{ - if (type == UART_TX_INT) { - bl_uart_int_tx_notify_unregister(uart->port, cb, uart); - } else if (type == UART_RX_INT) { - bl_uart_int_rx_notify_unregister(uart->port, cb, uart); - } else { - return -1; - } - - return 0; -} - diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_uart.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_uart.h deleted file mode 100644 index c30f93f3de..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_uart.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __HAL_UART_H__ -#define __HAL_UART_H__ -int vfs_uart_init(uint32_t fdt, uint32_t dtb_uart_offset); -int vfs_uart_init_simple_mode(uint8_t id, uint8_t pin_tx, uint8_t pin_rx, int baudrate, const char *path); -int hal_uart_data_notify(int number, int dir); -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_usb.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_usb.c deleted file mode 100644 index ad4592651b..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_usb.c +++ /dev/null @@ -1,1285 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "hal_usb.h" -#include "bl808_usb.h" -#include "bl808_glb.h" - -#ifndef CONFIG_USB_VDMA_ENABLE -#define CONFIG_USB_VDMA_ENABLE -#endif - -#ifndef CONFIG_USB_PINGPONG_ENABLE -// #define CONFIG_USB_PINGPONG_ENABLE -#endif - -#ifndef CONFIG_USB_VDMA_OUT_ENABLE -// #define CONFIG_USB_VDMA_OUT_ENABLE -#endif - -#define MIN(a, b) (((a) < (b)) ? (a) : (b)) - -#define USB_DC_LOG_WRN(a, ...) //bflb_platform_printf(a, ##__VA_ARGS__) -#define USB_DC_LOG_DBG(a, ...) -#define USB_DC_LOG_ERR(a, ...) //bflb_platform_printf(a, ##__VA_ARGS__) -#define USB_DC_LOG(a, ...) //bflb_platform_printf(a, ##__VA_ARGS__) - -static uint8_t fifo_ep_map[4] = { 0, 0, 0, 0 }; - -static usb_dc_device_t usb_hs_device __attribute__((section(".RW_OCRAM_NOINIT"))); -static void USBD_IRQHandler(void); - -static uint8_t usb_ep_is_enabled(uint8_t ep) -{ - uint8_t ep_idx = USB_EP_GET_IDX(ep); - - /* Check if ep enabled */ - if ((USB_EP_DIR_IS_OUT(ep)) && - usb_hs_device.out_ep[ep_idx].ep_ena) { - return 1; - } else if ((USB_EP_DIR_IS_IN(ep)) && - usb_hs_device.in_ep[ep_idx].ep_ena) { - return 1; - } - - return 0; -} -#ifndef CONFIG_USB_VDMA_ENABLE -static int usb_dma_write(uint8_t fifo_num, const uint8_t *data, uint32_t len) -{ - uint32_t timeout = 0xffffff; - - USB_DMA_Cfg_Type dma_cfg; - - dma_cfg.dir = USB_DMA_TRANS_DIR_MEM_2_FIFO; - dma_cfg.memAddr = (uint32_t)(uintptr_t)data; - dma_cfg.length = len; - - csi_dcache_clean_range((uint32_t *)data, len); - /* dma config */ - USB_Set_DMA_Config(fifo_num, &dma_cfg); - /* dma start */ - USB_Set_DMA_Start(); - /* dma wait */ - while (1) { - if (USB_Get_Sub_Group_2_IntStatus() & USB_SUB_GROUP_2_ERROR_BIT_MUSK) { - USB_DC_LOG_ERR("dma error\r\n"); - USB_Get_Sub_Group_2_IntClear(USB_SUB_GROUP_2_ERROR_BIT_MUSK); - return -USB_DC_DMA_ERR; - } - if (USB_Get_Sub_Group_2_IntStatus() & USB_SUB_GROUP_2_CMPLT_BIT_MUSK) { - USB_Get_Sub_Group_2_IntClear(USB_SUB_GROUP_2_CMPLT_BIT_MUSK); - break; - } - timeout--; - if (!timeout) { - USB_DC_LOG_ERR("fifo%d wait free timeout\r\n", fifo_num); - return -USB_DC_EP_TIMEOUT_ERR; - } - } - USB_Reset_DMA_Accessing_Fifo(); - return 0; -} - -static int usb_dma_read(uint8_t fifo_num, const uint8_t *data, uint32_t len) -{ - uint32_t timeout = 0xffffff; - - USB_DMA_Cfg_Type dma_cfg; - - dma_cfg.dir = USB_DMA_TRANS_DIR_FIFO_2_MEM; - dma_cfg.memAddr = (uint32_t)(uintptr_t)data; - dma_cfg.length = len; - - /* dma config */ - USB_Set_DMA_Config(fifo_num, &dma_cfg); - /* dma start */ - USB_Set_DMA_Start(); - /* dma wait */ - while (1) { - if (USB_Get_Sub_Group_2_IntStatus() & USB_SUB_GROUP_2_ERROR_BIT_MUSK) { - USB_DC_LOG_ERR("dma error\r\n"); - USB_Get_Sub_Group_2_IntClear(USB_SUB_GROUP_2_ERROR_BIT_MUSK); - return -USB_DC_DMA_ERR; - } - if (USB_Get_Sub_Group_2_IntStatus() & USB_SUB_GROUP_2_CMPLT_BIT_MUSK) { - USB_Get_Sub_Group_2_IntClear(USB_SUB_GROUP_2_CMPLT_BIT_MUSK); - break; - } - timeout--; - if (!timeout) { - USB_DC_LOG_ERR("fifo%d wait free timeout\r\n", fifo_num); - return -USB_DC_EP_TIMEOUT_ERR; - } - } - USB_Reset_DMA_Accessing_Fifo(); - csi_dcache_invalid_range((uint32_t *)data, len); - return 0; -} -#else -static int usb_vdma_write(uint8_t fifo_num, const uint8_t *data, uint32_t len) -{ - uint32_t timeout = 0xffffff; - - USB_VDMA_Cfg_Type vdma_fifo_cfg; - - vdma_fifo_cfg.dir = USB_VDMA_TRANS_DIR_MEM_2_FIFO; - vdma_fifo_cfg.memAddr = (uint32_t)(uintptr_t)data; - vdma_fifo_cfg.length = len; - - csi_dcache_clean_range((void *)data, len); - - USB_Set_VDMA_Config(fifo_num, &vdma_fifo_cfg); - USB_Set_VDMA_Start(fifo_num); - - while (USB_Get_VDMA_Start(fifo_num)) { - timeout--; - if (!timeout) { - USB_DC_LOG_ERR("fifo%d wait free timeout\r\n", fifo_num); - return -USB_DC_EP_TIMEOUT_ERR; - } - } - - return 0; -} - -static int usb_vdma_read(uint8_t fifo_num, const uint8_t *data, uint32_t len) -{ - uint32_t timeout = 0xffffff; - - USB_VDMA_Cfg_Type vdma_fifo_cfg; - - vdma_fifo_cfg.dir = USB_VDMA_TRANS_DIR_FIFO_2_MEM; - vdma_fifo_cfg.memAddr = (uint32_t)(uintptr_t)data; - vdma_fifo_cfg.length = len; - USB_Set_VDMA_Config(fifo_num, &vdma_fifo_cfg); - USB_Set_VDMA_Start(fifo_num); - - while (USB_Get_VDMA_Start(fifo_num)) { - timeout--; - if (!timeout) { - USB_DC_LOG_ERR("fifo%d wait free timeout\r\n", fifo_num); - return -USB_DC_EP_TIMEOUT_ERR; - } - } - - csi_dcache_invalid_range((void *)data, len); - return 0; -} -#endif - -static uint8_t usb_get_transfer_fifo(uint8_t ep_idx) -{ - uint8_t target_fifo_id; - - if (usb_hs_device.out_ep[ep_idx].ep_cfg.ep_mps > 512 || usb_hs_device.in_ep[ep_idx].ep_cfg.ep_mps > 512) { -#ifdef CONFIG_USB_PINGPONG_ENABLE - target_fifo_id = (4 * ep_idx - 3); -#else - target_fifo_id = (2 * ep_idx - 1); -#endif - } else { -#ifdef CONFIG_USB_PINGPONG_ENABLE - target_fifo_id = (2 * ep_idx - 1); -#else - target_fifo_id = ep_idx; -#endif - } - - return target_fifo_id; -} - -/** - * @brief - * - * @param dev - * @param oflag - * @return int - */ -int usb_dc_init(void) -{ - CPU_Interrupt_Disable(USB_IRQn); - - PDS_Turn_On_USB(1); - - /* interrupt config */ - USB_Global_IntEnable(DISABLE); - - /* software reset usb */ - USB_NORMAL_Cfg_Type usbNormalCfg = { -#ifdef CONFIG_USB_HS - .forceFullSpeed = 0, -#else - .forceFullSpeed = 1, -#endif - .chipEn = 1, - .swRst = 1, - .remoteWakeupEn = 0, - .rstTimeOut = 0xFFFF - }; - USB_Set_Normal_Config(&usbNormalCfg); -#ifdef CONFIG_USB_HS - USB_SOF_Mask_Time_HighSpeed(); -#else - USB_SOF_Mask_Time_FullSpeed(); -#endif - USB_Set_Device_Address(0); - USB_Non_Ctrl_Transfer_Disable(); - - USB_Reset_FIFO(USB_FIFO_0); - USB_Reset_FIFO(USB_FIFO_1); - USB_Reset_FIFO(USB_FIFO_2); - USB_Reset_FIFO(USB_FIFO_3); - USB_Clear_CTRL_FIFO(); - - USB_Group_IntMask(USB_GRP_INT_G0, UNMASK); - USB_Group_IntMask(USB_GRP_INT_G1, UNMASK); - USB_Group_IntMask(USB_GRP_INT_G2, UNMASK); - USB_Group_IntMask(USB_GRP_INT_G3, UNMASK); - USB_Group_IntMask(USB_GRP_INT_G4, UNMASK); - - USB_Global_IntMask(USB_GLOBAL_INT_DEV, UNMASK); - USB_Global_IntMask(USB_GLOBAL_INT_OTG, MASK); - USB_Global_IntMask(USB_GLOBAL_INT_HC, MASK); - - USB_Sub_Group_IntMask(USB_INT_DMA_CMPLT | USB_INT_DMA_ERROR | USB_INT_IDLE | USB_INT_RX0BYTE | USB_INT_TX0BYTE); - USB_Sub_Group_IntMask(USB_INT_VDMA_CMPLT_CXF | USB_INT_VDMA_CMPLT_F0 | USB_INT_VDMA_CMPLT_F1 | USB_INT_VDMA_CMPLT_F2 | USB_INT_VDMA_CMPLT_F3 | - USB_INT_VDMA_ERROR_CXF | USB_INT_VDMA_ERROR_F0 | USB_INT_VDMA_ERROR_F1 | USB_INT_VDMA_ERROR_F2 | USB_INT_VDMA_ERROR_F3); - - USB_Sub_Group_IntUnmask(USB_INT_CX_SETUP | USB_INT_CX_IN | USB_INT_CX_OUT | USB_INT_CX_COMFAIL | USB_INT_CX_COMABORT); - USB_Sub_Group_IntUnmask(USB_INT_RESET | USB_INT_SUSPEND | USB_INT_RESUME | USB_INT_RX0BYTE); - - USB_Get_Sub_Group_0_IntClear(USB_SUB_GROUP_0_CX_COMABORT_BIT_MUSK); - USB_Get_Sub_Group_2_IntClear(USB_SUB_GROUP_2_RESET_BIT_MUSK | USB_SUB_GROUP_2_SUSPEND_BIT_MUSK | USB_SUB_GROUP_2_RESUME_BIT_MUSK | - USB_SUB_GROUP_2_TX0BYTE_BIT_MUSK | USB_SUB_GROUP_2_RX0BYTE_BIT_MUSK | - USB_SUB_GROUP_2_CMPLT_BIT_MUSK | USB_SUB_GROUP_2_ERROR_BIT_MUSK); - USB_Get_Sub_Group_3_IntClear(0xffffffff); //VDMA INT - USB_Get_Sub_Group_4_IntClear(USB_SUB_GROUP_4_L1_BIT_MUSK); - /*TODO mask no use rsv int use some drv*/ - BL_WR_WORD(USB_BASE + USB_DEV_MISG0_OFFSET, 1 << 3); - -#ifdef CONFIG_USB_VDMA_ENABLE - USB_Set_VDMA_Enable(); -#endif - - memset(&usb_hs_device, 0, sizeof(usb_hs_device)); - - usb_hs_device.out_ep[0].ep_ena = 1U; - usb_hs_device.in_ep[0].ep_ena = 1U; - usb_hs_device.out_ep[0].ep_cfg.ep_mps = 64; - usb_hs_device.out_ep[0].ep_cfg.ep_type = USBD_EP_TYPE_CTRL; - usb_hs_device.in_ep[0].ep_cfg.ep_mps = 64; - usb_hs_device.in_ep[0].ep_cfg.ep_type = USBD_EP_TYPE_CTRL; - - Interrupt_Handler_Register(USB_IRQn, USBD_IRQHandler); - CPU_Interrupt_Enable(USB_IRQn); - USB_SoftDetach_Disable(); - USB_Global_IntEnable(ENABLE); - - return 0; -} - -/** - * @brief Set USB device address - * - * @param[in] addr Device address - * - * @return 0 on success, negative errno code on fail. - */ -int usbd_set_address(const uint8_t addr) -{ - USB_Set_Device_Address(addr); - return 0; -} - -/** - * @brief configure and enable endpoint - * This function sets endpoint configuration according to one specified in USB - * endpoint descriptor and then enables it for data transfers. - * - * @param dev - * @param ep_cfg ep_cfg Endpoint - * @return int - */ -int usbd_ep_open(const struct usb_dc_ep_cfg *ep_cfg) -{ - uint8_t ep; - USB_FIFO_Cfg_Type fifo_cfg; - - if (!ep_cfg) { - return -1; - } - - ep = ep_cfg->ep_addr; - - uint8_t ep_idx = USB_EP_GET_IDX(ep); - - if (ep_idx > 4) { - return -1; - } - - USB_DC_LOG_DBG("%s ep %x, mps %d, type %d\r\n", __func__, ep, ep_cfg->ep_mps, ep_cfg->ep_type); - - if (ep_idx == 0) { - return 0; - } - - fifo_cfg.enable = 1; - fifo_cfg.fifoType = ep_cfg->ep_type; - fifo_cfg.epID = ep_idx; - - if (USB_EP_DIR_IS_OUT(ep)) { - fifo_cfg.dir = USB_FIFO_DIR_OUT; - usb_hs_device.out_ep[ep_idx].ep_cfg.ep_mps = ep_cfg->ep_mps; - usb_hs_device.out_ep[ep_idx].ep_cfg.ep_type = ep_cfg->ep_type; - usb_hs_device.out_ep[ep_idx].ep_ena = 1U; - - USB_Set_Endpoint_OUT_MaxPacketSize(ep_idx, ep_cfg->ep_mps); - - } else { - fifo_cfg.dir = USB_FIFO_DIR_IN; - usb_hs_device.in_ep[ep_idx].ep_cfg.ep_mps = ep_cfg->ep_mps; - usb_hs_device.in_ep[ep_idx].ep_cfg.ep_type = ep_cfg->ep_type; - usb_hs_device.in_ep[ep_idx].ep_ena = 1U; - - USB_Set_Endpoint_IN_MaxPacketSize(ep_idx, ep_cfg->ep_mps); - } - -#ifndef CONFIG_USB_PINGPONG_ENABLE - fifo_cfg.blockType = USB_FIFO_BLOCK_CNT_SINGLE_BLOCK; - - if (ep_cfg->ep_mps <= 512) { - if (ep_idx > 4) { - return -1; - } - fifo_ep_map[0] = 0x01; - fifo_ep_map[1] = 0x02; - fifo_ep_map[2] = 0x03; - fifo_ep_map[3] = 0x04; - - USB_Set_FIFO_Of_Endpoint_IN(USB_Endpoint_1, USB_FIFO_0); - USB_Set_FIFO_Of_Endpoint_OUT(USB_Endpoint_1, USB_FIFO_0); - USB_Set_FIFO_Of_Endpoint_IN(USB_Endpoint_2, USB_FIFO_1); - USB_Set_FIFO_Of_Endpoint_OUT(USB_Endpoint_2, USB_FIFO_1); - USB_Set_FIFO_Of_Endpoint_IN(USB_Endpoint_3, USB_FIFO_2); - USB_Set_FIFO_Of_Endpoint_OUT(USB_Endpoint_3, USB_FIFO_2); - USB_Set_FIFO_Of_Endpoint_IN(USB_Endpoint_4, USB_FIFO_3); - USB_Set_FIFO_Of_Endpoint_OUT(USB_Endpoint_4, USB_FIFO_3); - - fifo_cfg.blockSize = USB_FIFO_BLOCK_MAX_SIZE_512; - USB_Set_FIFO_Config(ep_idx - 1, &fifo_cfg); - - if (USB_EP_DIR_IS_OUT(ep)) { -#ifdef CONFIG_USB_VDMA_OUT_ENABLE - USB_Sub_Group_IntUnmask(1ULL << (USB_SUB_GRP3_INT_VDMA_CMPLT_F0 + (ep_idx - 1))); -#else - USB_Sub_Group_IntUnmask(1ULL << (USB_SUB_GRP1_INT_F0_OUT + 2 * (ep_idx - 1))); -#endif - } else { - USB_Sub_Group_IntUnmask(1ULL << (USB_SUB_GRP3_INT_VDMA_CMPLT_F0 + (ep_idx - 1))); - } - - if (ep_cfg->ep_type == 0x01) { - uint32_t tmpVal; - tmpVal = BL_RD_WORD(USB_BASE + USB_DEV_INMPS1_OFFSET + 0x04 * (ep_idx - 1)); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_TX_NUM_HBW_IEP1, 0); - BL_WR_WORD(USB_BASE + USB_DEV_INMPS1_OFFSET + 0x04 * (ep_idx - 1), tmpVal); - } - } else { - if (ep_idx > 2) { - return -1; - } - fifo_ep_map[0] = 0x01; - fifo_ep_map[1] = 0x01; - fifo_ep_map[2] = 0x02; - fifo_ep_map[3] = 0x02; - - USB_Set_FIFO_Of_Endpoint_IN(USB_Endpoint_1, USB_FIFO_0); - USB_Set_FIFO_Of_Endpoint_OUT(USB_Endpoint_1, USB_FIFO_0); - USB_Set_FIFO_Of_Endpoint_IN(USB_Endpoint_2, USB_FIFO_2); - USB_Set_FIFO_Of_Endpoint_OUT(USB_Endpoint_2, USB_FIFO_2); - - fifo_cfg.blockSize = USB_FIFO_BLOCK_MAX_SIZE_1024; - USB_Set_FIFO_Config(2 * ep_idx - 2, &fifo_cfg); - fifo_cfg.enable = 0; - USB_Set_FIFO_Config(2 * ep_idx - 1, &fifo_cfg); - - if (USB_EP_DIR_IS_OUT(ep)) { -#ifdef CONFIG_USB_VDMA_OUT_ENABLE - USB_Sub_Group_IntUnmask(1ULL << (USB_SUB_GRP3_INT_VDMA_CMPLT_F0 + 2 * (ep_idx - 1))); -#else - USB_Sub_Group_IntUnmask(1ULL << (USB_SUB_GRP1_INT_F0_OUT + 4 * (ep_idx - 1))); -#endif - } else { - USB_Sub_Group_IntUnmask(1ULL << (USB_SUB_GRP3_INT_VDMA_CMPLT_F0 + 2 * (ep_idx - 1))); - } - - if (ep_cfg->ep_type == 0x01) { - uint32_t tmpVal; - tmpVal = BL_RD_WORD(USB_BASE + USB_DEV_INMPS1_OFFSET + 0x04 * (ep_idx - 1)); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_TX_NUM_HBW_IEP1, 0); - BL_WR_WORD(USB_BASE + USB_DEV_INMPS1_OFFSET + 0x04 * (ep_idx - 1), tmpVal); - } - } -#else - fifo_cfg.blockType = USB_FIFO_BLOCK_CNT_DOUBLE_BLOCKS; - - if (ep_cfg->ep_mps <= 512) { - if (ep_idx > 2) { - return -1; - } - fifo_ep_map[0] = 0x01; - fifo_ep_map[1] = 0x01; - fifo_ep_map[2] = 0x02; - fifo_ep_map[3] = 0x02; - - USB_Set_FIFO_Of_Endpoint_IN(USB_Endpoint_1, USB_FIFO_0); - USB_Set_FIFO_Of_Endpoint_OUT(USB_Endpoint_1, USB_FIFO_0); - USB_Set_FIFO_Of_Endpoint_IN(USB_Endpoint_2, USB_FIFO_2); - USB_Set_FIFO_Of_Endpoint_OUT(USB_Endpoint_2, USB_FIFO_2); - - fifo_cfg.blockSize = USB_FIFO_BLOCK_MAX_SIZE_512; - USB_Set_FIFO_Config(2 * ep_idx - 2, &fifo_cfg); - fifo_cfg.enable = 0; - USB_Set_FIFO_Config(2 * ep_idx - 1, &fifo_cfg); - - if (USB_EP_DIR_IS_OUT(ep)) { -#ifdef CONFIG_USB_VDMA_OUT_ENABLE - USB_Sub_Group_IntUnmask(1ULL << (USB_SUB_GRP3_INT_VDMA_CMPLT_F0 + 2 * (ep_idx - 1))); -#else - USB_Sub_Group_IntUnmask(1ULL << (USB_SUB_GRP1_INT_F0_OUT + 4 * (ep_idx - 1))); -#endif - } else { - USB_Sub_Group_IntUnmask(1ULL << (USB_SUB_GRP3_INT_VDMA_CMPLT_F0 + 2 * (ep_idx - 1))); - } - } else { - if (ep_idx > 1) { - return -1; - } - - fifo_ep_map[0] = 0x01; - fifo_ep_map[1] = 0x01; - fifo_ep_map[2] = 0x01; - fifo_ep_map[3] = 0x01; - - USB_Set_FIFO_Of_Endpoint_IN(USB_Endpoint_1, USB_FIFO_0); - USB_Set_FIFO_Of_Endpoint_OUT(USB_Endpoint_1, USB_FIFO_0); - - fifo_cfg.blockSize = USB_FIFO_BLOCK_MAX_SIZE_1024; - USB_Set_FIFO_Config(2 * ep_idx - 2, &fifo_cfg); - fifo_cfg.enable = 0; - USB_Set_FIFO_Config(2 * ep_idx - 1, &fifo_cfg); - USB_Set_FIFO_Config(2 * ep_idx, &fifo_cfg); - USB_Set_FIFO_Config(2 * ep_idx + 1, &fifo_cfg); - - if (USB_EP_DIR_IS_OUT(ep)) { -#ifdef CONFIG_USB_VDMA_OUT_ENABLE - USB_Sub_Group_IntUnmask(1ULL << (USB_SUB_GRP3_INT_VDMA_CMPLT_F0)); -#else - USB_Sub_Group_IntUnmask(1ULL << (USB_SUB_GRP1_INT_F0_OUT)); -#endif - } else { - USB_Sub_Group_IntUnmask(1ULL << (USB_SUB_GRP3_INT_VDMA_CMPLT_F0)); - } - } -#endif - - USB_Non_Ctrl_Transfer_Enable(); - - return 0; -} - -/** - * @brief Disable the selected endpoint - * - * Function to disable the selected endpoint. Upon success interrupts are - * disabled for the corresponding endpoint and the endpoint is no longer able - * for transmitting/receiving data. - * - * @param[in] ep Endpoint address corresponding to the one - * listed in the device configuration table - * - * @return 0 on success, negative errno code on fail. - */ -int usbd_ep_close(const uint8_t ep) -{ - return 0; -} -/** - * @brief Set stall condition for the selected endpoint - * - * @param[in] ep Endpoint address corresponding to the one - * listed in the device configuration table - * - * @return 0 on success, negative errno code on fail. - */ -int usbd_ep_set_stall(const uint8_t ep) -{ - uint8_t ep_idx = USB_EP_GET_IDX(ep); - - if (USB_EP_DIR_IS_OUT(ep)) { - if (ep_idx == 0) { - USB_Set_CTRL_Endpoint_Stall_Once(); - } else { - USB_Set_Endpoint_OUT_Stall(ep_idx, ENABLE); - usb_hs_device.out_ep[ep_idx].is_stalled = 1U; - } - } else { - if (ep_idx == 0) { - USB_Set_CTRL_Endpoint_Stall_Once(); - } else { - USB_Set_Endpoint_IN_Stall(ep_idx, ENABLE); - usb_hs_device.in_ep[ep_idx].is_stalled = 1U; - } - } - return 0; -} -/** - * @brief Clear stall condition for the selected endpoint - * - * @param[in] ep Endpoint address corresponding to the one - * listed in the device configuration table - * - * @return 0 on success, negative errno code on fail. - */ -int usbd_ep_clear_stall(const uint8_t ep) -{ - uint8_t ep_idx = USB_EP_GET_IDX(ep); - - if (ep_idx) { - if (USB_EP_DIR_IS_OUT(ep)) { - USB_Reset_Endpoint_OUT_Data_Toggle_Sequence(ep_idx); - USB_Set_Endpoint_OUT_Stall(ep_idx, DISABLE); - usb_hs_device.out_ep[ep_idx].is_stalled = 0; - } else { - USB_Reset_Endpoint_IN_Data_Toggle_Sequence(ep_idx); - USB_Set_Endpoint_IN_Stall(ep_idx, DISABLE); - usb_hs_device.in_ep[ep_idx].is_stalled = 0; - } - } - return 0; -} -/** - * @brief Check if the selected endpoint is stalled - * - * @param dev usb device - * @param[in] ep Endpoint address corresponding to the one - * listed in the device configuration table - * @param[out] stalled Endpoint stall status - * - * @return 0 on success, negative errno code on fail. - */ -int usbd_ep_is_stalled(const uint8_t ep, uint8_t *stalled) -{ - uint8_t ep_idx = USB_EP_GET_IDX(ep); - - if (!stalled) { - return -1; - } - *stalled = 0U; - if (ep_idx == 0) - return 0; - - if (USB_EP_DIR_IS_OUT(ep)) { - if (usb_hs_device.out_ep[ep_idx].is_stalled) { - *stalled = 1U; - } - } else { - if (usb_hs_device.in_ep[ep_idx].is_stalled) { - *stalled = 1U; - } - } - - return 0; -} - -/** - * @brief Write data to the specified endpoint - * - * This function is called to write data to the specified endpoint. The - * supplied usbd_endpoint_callback function will be called when data is transmitted - * out. - * - * @param dev - * @param[in] ep Endpoint address corresponding to the one - * listed in the device configuration table - * @param[in] data Pointer to data to write - * @param[in] data_len Length of the data requested to write. This may - * be zero for a zero length status packet. - * @param[out] ret_bytes Bytes scheduled for transmission. This value - * may be NULL if the application expects all - * bytes to be written - * - * @return 0 on success, negative errno code on fail. - */ -int usbd_ep_write(const uint8_t ep, const uint8_t *data, uint32_t data_len, uint32_t *ret_bytes) -{ - uint32_t timeout = 0xffffff; - uint32_t target_fifo_id = 0; - uint8_t mps_over_flag = 0; - uint8_t ep_idx = USB_EP_GET_IDX(ep); - int ret = 0; - /* Check if IN ep */ - if (USB_EP_GET_DIR(ep) != USB_EP_DIR_IN) { - return -USB_DC_EP_DIR_ERR; - } - - /* Check if ep enabled */ - if (!usb_ep_is_enabled(ep)) { - return -USB_DC_EP_EN_ERR; - } - - if (!data && data_len) { - USB_DC_LOG_ERR("data is null\r\n"); - return -USB_DC_ADDR_ERR; - } - - if (ep_idx == 0) { - if (!data_len) { - /* enable ep0 transfer */ - USB_CTRL_Endpoint_Data_Transfer_Done(); - return USB_DC_OK; - } - if (data_len > usb_hs_device.in_ep[ep_idx].ep_cfg.ep_mps) { - /* Check if transfer len is too big */ - data_len = usb_hs_device.in_ep[ep_idx].ep_cfg.ep_mps; - mps_over_flag = 1; - } - -#ifdef CONFIG_USB_VDMA_ENABLE - ret = usb_vdma_write(0, data, data_len); -#else - ret = usb_dma_write(0, data, data_len); -#endif - if (ret < 0) { - return ret; - } - if (!mps_over_flag) { - USB_CTRL_Endpoint_Data_Transfer_Done(); - } - - } else { - if (!data_len) { - /* send zlp */ - USB_Endpoint_Transmit_Zero_Length_Packet(ep_idx); - while (1) { - if (USB_Is_Endpoint_Transfer_Zero_Length_Packet(ep_idx)) { - USB_Clear_Endpoint_Transfer_Zero_Length_Packet_Status(ep_idx); - break; - } - timeout--; - if (!timeout) { - USB_DC_LOG_ERR("ep%d wait free timeout\r\n", ep); - return -USB_DC_EP_TIMEOUT_ERR; - } - } - return USB_DC_OK; - } - - target_fifo_id = usb_get_transfer_fifo(ep_idx); -#ifdef CONFIG_USB_VDMA_ENABLE - ret = usb_vdma_write(target_fifo_id, data, data_len); -#else - ret = usb_dma_write(target_fifo_id, data, data_len); -#endif - if (ret < 0) { - return ret; - } - } - - USB_DC_LOG_DBG("EP%d write %u bytes\r\n", ep_idx, data_len); - - if (ret_bytes) { - *ret_bytes = data_len; - } - - return USB_DC_OK; -} - -/** - * @brief Read data from the specified endpoint - * - * This function is called by the endpoint handler function, after an OUT - * interrupt has been received for that EP. The application must only call this - * function through the supplied usbd_ep_callback function. This function clears - * the ENDPOINT NAK when max_data_len is 0, if all data in the endpoint FIFO has been read, - * so as to accept more data from host. - * - * @param[in] ep Endpoint address corresponding to the one - * listed in the device configuration table - * @param[in] data Pointer to data buffer to write to - * @param[in] max_data_len Max length of data to read - * @param[out] read_bytes Number of bytes read. If data is NULL and - * max_data_len is 0 the number of bytes - * available for read should be returned. - * - * @return 0 on success, negative errno code on fail. - */ -int usbd_ep_read(const uint8_t ep, uint8_t *data, uint32_t data_len, uint32_t *read_bytes) -{ - uint32_t read_len = 0; - uint32_t target_fifo_id = 0; - uint8_t ep_idx = USB_EP_GET_IDX(ep); - int ret = 0; - - /* Check if OUT ep */ - if (USB_EP_GET_DIR(ep) != USB_EP_DIR_OUT) { - USB_DC_LOG_ERR("Wrong endpoint direction\r\n"); - return -USB_DC_EP_DIR_ERR; - } - - /* Check if ep enabled */ - if (!usb_ep_is_enabled(ep)) { - USB_DC_LOG_ERR("Not enabled endpoint\r\n"); - return -USB_DC_EP_EN_ERR; - } - - if (!data && data_len) { - USB_DC_LOG_ERR("data is null\r\n"); - return -USB_DC_ADDR_ERR; - } - - /* Allow to read 0 bytes */ - if (!data_len) { - return USB_DC_OK; - } - - if (ep_idx == 0) { - /*setup handler*/ - if ((data_len == 8) && !read_bytes) { - USB_Get_Setup_Command((uint32_t *)data); - return USB_DC_OK; - } else { - read_len = BL_GET_REG_BITS_VAL(BL_RD_REG(USB_BASE, USB_DEV_CXCFE), USB_CX_FNT); -#if defined(CONFIG_USB_VDMA_ENABLE) - ret = usb_vdma_read(0, data, read_len); -#else - ret = usb_dma_read(0, data, read_len); -#endif - if (ret < 0) { - return ret; - } - } - } else { - target_fifo_id = usb_get_transfer_fifo(ep_idx); - read_len = USB_Get_OUT_FIFO_Count(target_fifo_id - 1); - if (read_len == 0) { - if (read_bytes) { - *read_bytes = 0; - } - return 0; - } -#ifdef CONFIG_USB_VDMA_ENABLE - ret = usb_vdma_read(target_fifo_id, data, read_len); -#else - ret = usb_dma_read(target_fifo_id, data, read_len); -#endif - if (ret < 0) { - return ret; - } - } - if (read_bytes) { - *read_bytes = read_len; - } - USB_DC_LOG_DBG("Read EP%d, req %d, read %d bytes\r\n", ep, data_len, *read_bytes); - - return USB_DC_OK; -} - -int usbd_ep_write_async(const uint8_t ep, const uint8_t *data, uint32_t data_len) -{ - uint32_t target_fifo_id = 0; - uint8_t ep_idx = USB_EP_GET_IDX(ep); - - /* Check if IN ep */ - if (USB_EP_GET_DIR(ep) != USB_EP_DIR_IN) { - return -USB_DC_EP_DIR_ERR; - } - - /* Check if ep enabled */ - if (!usb_ep_is_enabled(ep)) { - return -USB_DC_EP_EN_ERR; - } - - if (!data && data_len) { - USB_DC_LOG_ERR("data is null\r\n"); - return -USB_DC_ADDR_ERR; - } - - target_fifo_id = usb_get_transfer_fifo(ep_idx); - - USB_VDMA_Cfg_Type vdma_fifo_cfg; - - vdma_fifo_cfg.dir = USB_VDMA_TRANS_DIR_MEM_2_FIFO; - vdma_fifo_cfg.memAddr = (uint32_t)(uintptr_t)data; - vdma_fifo_cfg.length = data_len; - - USB_Set_VDMA_Config(target_fifo_id, &vdma_fifo_cfg); - csi_dcache_clean_range((void *)data, data_len); - USB_Set_VDMA_Start(target_fifo_id); - - return 0; -} - -int usbd_ep_read_async(const uint8_t ep, uint8_t *data, uint32_t data_len) -{ - uint32_t target_fifo_id = 0; - uint8_t ep_idx = USB_EP_GET_IDX(ep); - - /* Check if IN ep */ - if (USB_EP_GET_DIR(ep) != USB_EP_DIR_OUT) { - return -USB_DC_EP_DIR_ERR; - } - - /* Check if ep enabled */ - if (!usb_ep_is_enabled(ep)) { - return -USB_DC_EP_EN_ERR; - } - - if (!data && data_len) { - USB_DC_LOG_ERR("data is null\r\n"); - return -USB_DC_ADDR_ERR; - } - - target_fifo_id = usb_get_transfer_fifo(ep_idx); - - USB_VDMA_Cfg_Type vdma_fifo_cfg; - - vdma_fifo_cfg.dir = USB_VDMA_TRANS_DIR_FIFO_2_MEM; - vdma_fifo_cfg.memAddr = (uint32_t)(uintptr_t)data; - vdma_fifo_cfg.length = data_len; - - USB_Set_VDMA_Config(target_fifo_id, &vdma_fifo_cfg); - USB_Set_VDMA_Start(target_fifo_id); - - return 0; -} - -extern void usbd_event_notify_handler(uint8_t event, void *arg); - -static void usb_group0_isr(void) -{ - uint32_t group0intstatus = USB_Get_Sub_Group_0_IntStatus() & ~USB_Get_Sub_Group_0_IntMask(); - - if (group0intstatus & USB_SUB_GROUP_0_CX_COMABORT_BIT_MUSK) { - /* CX_COMABT_INT */ - USB_DC_LOG_ERR("CX COMABT\r\n"); - USB_Get_Sub_Group_0_IntClear(USB_SUB_GROUP_0_CX_COMABORT_BIT_MUSK); - return; - } - if (group0intstatus & USB_SUB_GROUP_0_CX_COMFAIL_BIT_MUSK) { - /* CX_COMFAIL_INT */ - USB_DC_LOG_ERR("CX COMFAIL\r\n"); - return; - } - if (group0intstatus & USB_SUB_GROUP_0_CX_OUT_BIT_MUSK) { - /* CX_OUT_INT */ - usbd_event_notify_handler(USB_DC_EVENT_EP0_OUT_NOTIFY, NULL); - return; - } - if (group0intstatus & USB_SUB_GROUP_0_CX_IN_BIT_MUSK) { - /* CX_IN_INT */ - usbd_event_notify_handler(USB_DC_EVENT_EP0_IN_NOTIFY, NULL); - return; - } - if (group0intstatus & USB_SUB_GROUP_0_CX_SETUP_BIT_MUSK) { - /* CX_SETUP_INT */ - usbd_event_notify_handler(USB_DC_EVENT_SETUP_NOTIFY, NULL); - return; - } -} -static void usb_group1_isr(void) -{ - uint32_t group1intstatus = USB_Get_Sub_Group_1_IntStatus() & ~USB_Get_Sub_Group_1_IntMask(); - - if (group1intstatus & USB_SUB_GROUP_1_F0_OUT_BIT_MUSK) { - /* F0_OUT_INT */ - usbd_event_notify_handler(USB_DC_EVENT_EP_OUT_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[0] & 0x7f)); - } - - if (group1intstatus & USB_SUB_GROUP_1_F1_OUT_BIT_MUSK) { - /* F1_OUT_INT */ - usbd_event_notify_handler(USB_DC_EVENT_EP_OUT_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[1] & 0x7f)); - } - - if (group1intstatus & USB_SUB_GROUP_1_F2_OUT_BIT_MUSK) { - /* F2_OUT_INT */ - usbd_event_notify_handler(USB_DC_EVENT_EP_OUT_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[2] & 0x7f)); - } - - if (group1intstatus & USB_SUB_GROUP_1_F3_OUT_BIT_MUSK) { - /* F3_OUT_INT */ - usbd_event_notify_handler(USB_DC_EVENT_EP_OUT_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[3] & 0x7f)); - } - - if (group1intstatus & USB_SUB_GROUP_1_F0_IN_BIT_MUSK) { - /* F0_IN_INT */ - usbd_event_notify_handler(USB_DC_EVENT_EP_IN_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[0] | 0x80)); - } - - if (group1intstatus & USB_SUB_GROUP_1_F1_IN_BIT_MUSK) { - /* F1_IN_INT */ - usbd_event_notify_handler(USB_DC_EVENT_EP_IN_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[1] | 0x80)); - } - - if (group1intstatus & USB_SUB_GROUP_1_F2_IN_BIT_MUSK) { - /* F2_IN_INT */ - usbd_event_notify_handler(USB_DC_EVENT_EP_IN_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[2] | 0x80)); - } - - if (group1intstatus & USB_SUB_GROUP_1_F3_IN_BIT_MUSK) { - /* F3_IN_INT */ - usbd_event_notify_handler(USB_DC_EVENT_EP_IN_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[3] | 0x80)); - } -} -static void usb_group2_isr(void) -{ - uint32_t group2intstatus = USB_Get_Sub_Group_2_IntStatus() & ~USB_Get_Sub_Group_2_IntMask(); - - if (group2intstatus & USB_SUB_GROUP_2_WAKEUP_BY_VBUS_BIT_MUSK) { - /* Dev_Wakeup_byVBUS */ - return; - } - if (group2intstatus & USB_SUB_GROUP_2_IDLE_BIT_MUSK) { - /* Dev_Idle(HOV) */ - return; - } - if (group2intstatus & USB_SUB_GROUP_2_ERROR_BIT_MUSK) { - /* DMA_ERROR(HOV) */ - USB_Get_Sub_Group_2_IntClear(USB_SUB_GROUP_2_ERROR_BIT_MUSK); - return; - } - if (group2intstatus & USB_SUB_GROUP_2_CMPLT_BIT_MUSK) { - /* DMA_CMPLT(HOV) */ - USB_Get_Sub_Group_2_IntClear(USB_SUB_GROUP_2_CMPLT_BIT_MUSK); - return; - } - if (group2intstatus & USB_SUB_GROUP_2_RX0BYTE_BIT_MUSK) { - /* RX0BYTE_INT */ - USB_Get_Sub_Group_2_IntClear(USB_SUB_GROUP_2_RX0BYTE_BIT_MUSK); - for (uint32_t i = USB_Endpoint_1; i <= USB_Endpoint_8; i++) { - if (USB_Is_Endpoint_Receive_Zero_Length_Packet(i)) - USB_Clear_Endpoint_Receive_Zero_Length_Packet_Status(i); - } - return; - } - if (group2intstatus & USB_SUB_GROUP_2_TX0BYTE_BIT_MUSK) { - /* TX0BYTE_INT */ - USB_Get_Sub_Group_2_IntClear(USB_SUB_GROUP_2_TX0BYTE_BIT_MUSK); - for (uint32_t i = USB_Endpoint_1; i <= USB_Endpoint_8; i++) { - if (USB_Is_Endpoint_Transfer_Zero_Length_Packet(i)) - USB_Clear_Endpoint_Transfer_Zero_Length_Packet_Status(i); - } - return; - } - if (group2intstatus & USB_SUB_GROUP_2_RESUME_BIT_MUSK) { - /* RESM_INT */ - USB_Get_Sub_Group_2_IntClear(USB_SUB_GROUP_2_RESUME_BIT_MUSK); - usbd_event_notify_handler(USB_DC_EVENT_RESUME, NULL); - return; - } - if (group2intstatus & USB_SUB_GROUP_2_SUSPEND_BIT_MUSK) { - /* SUSP_INT */ - USB_Get_Sub_Group_2_IntClear(USB_SUB_GROUP_2_SUSPEND_BIT_MUSK); - usbd_event_notify_handler(USB_DC_EVENT_SUSPEND, NULL); - return; - } - if (group2intstatus & USB_SUB_GROUP_2_RESET_BIT_MUSK) { - /* USBRST_INT */ - USB_Get_Sub_Group_2_IntClear(USB_SUB_GROUP_2_RESET_BIT_MUSK); - USB_Non_Ctrl_Transfer_Disable(); - USB_Reset_FIFO(USB_FIFO_0); - USB_Reset_FIFO(USB_FIFO_1); - USB_Reset_FIFO(USB_FIFO_2); - USB_Reset_FIFO(USB_FIFO_3); - USB_Clear_CTRL_FIFO(); - -#ifdef CONFIG_USB_HS - USB_SOF_Mask_Time_HighSpeed(); -#else - USB_SOF_Mask_Time_FullSpeed(); -#endif - usbd_event_notify_handler(USB_DC_EVENT_RESET, NULL); - return; - } -} -#ifdef CONFIG_USB_VDMA_ENABLE -static void usb_group3_isr(void) -{ - uint32_t group3intstatus = USB_Get_Sub_Group_3_IntStatus() & ~USB_Get_Sub_Group_3_IntMask(); - - if (group3intstatus & USB_SUB_GROUP_3_VDMA_CMPLT_CXF_BIT_MUSK) { - /* VDMA_CMPLT_CXF */ - USB_Get_Sub_Group_3_IntClear(USB_SUB_GROUP_3_VDMA_CMPLT_CXF_BIT_MUSK); - } - - if (group3intstatus & USB_SUB_GROUP_3_VDMA_CMPLT_F0_BIT_MUSK) { - /* VDMA_CMPLT_F0 */ - USB_Get_Sub_Group_3_IntClear(USB_SUB_GROUP_3_VDMA_CMPLT_F0_BIT_MUSK); - if (usb_hs_device.in_ep[fifo_ep_map[0]].ep_ena) { - usbd_event_notify_handler(USB_DC_EVENT_EP_IN_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[0] | 0x80)); - } else if (usb_hs_device.out_ep[fifo_ep_map[0]].ep_ena) { - usbd_event_notify_handler(USB_DC_EVENT_EP_OUT_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[0] & 0x7f)); - } - } - - if (group3intstatus & USB_SUB_GROUP_3_VDMA_CMPLT_F1_BIT_MUSK) { - /* VDMA_CMPLT_F1 */ - USB_Get_Sub_Group_3_IntClear(USB_SUB_GROUP_3_VDMA_CMPLT_F1_BIT_MUSK); - if (usb_hs_device.in_ep[fifo_ep_map[1]].ep_ena) { - usbd_event_notify_handler(USB_DC_EVENT_EP_IN_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[1] | 0x80)); - } else if (usb_hs_device.out_ep[fifo_ep_map[1]].ep_ena) { - usbd_event_notify_handler(USB_DC_EVENT_EP_OUT_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[1] & 0x7f)); - } - } - - if (group3intstatus & USB_SUB_GROUP_3_VDMA_CMPLT_F2_BIT_MUSK) { - /* VDMA_CMPLT_F2 */ - USB_Get_Sub_Group_3_IntClear(USB_SUB_GROUP_3_VDMA_CMPLT_F2_BIT_MUSK); - if (usb_hs_device.in_ep[fifo_ep_map[2]].ep_ena) { - usbd_event_notify_handler(USB_DC_EVENT_EP_IN_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[2] | 0x80)); - } else if (usb_hs_device.out_ep[fifo_ep_map[2]].ep_ena) { - usbd_event_notify_handler(USB_DC_EVENT_EP_OUT_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[2] & 0x7f)); - } - } - - if (group3intstatus & USB_SUB_GROUP_3_VDMA_CMPLT_F3_BIT_MUSK) { - /* VDMA_CMPLT_F3 */ - USB_Get_Sub_Group_3_IntClear(USB_SUB_GROUP_3_VDMA_CMPLT_F3_BIT_MUSK); - if (usb_hs_device.in_ep[fifo_ep_map[3]].ep_ena) { - usbd_event_notify_handler(USB_DC_EVENT_EP_IN_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[3] | 0x80)); - } else if (usb_hs_device.out_ep[fifo_ep_map[3]].ep_ena) { - usbd_event_notify_handler(USB_DC_EVENT_EP_OUT_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[3] & 0x7f)); - } - } - - if (group3intstatus & USB_SUB_GROUP_3_VDMA_ERROR_CXF_BIT_MUSK) { - /* VDMA_ERROR_CXF */ - USB_Get_Sub_Group_3_IntClear(USB_SUB_GROUP_3_VDMA_ERROR_CXF_BIT_MUSK); - } - - if (group3intstatus & USB_SUB_GROUP_3_VDMA_ERROR_F0_BIT_MUSK) { - /* VDMA_ERROR_F0 */ - USB_Get_Sub_Group_3_IntClear(USB_SUB_GROUP_3_VDMA_ERROR_F0_BIT_MUSK); - } - - if (group3intstatus & USB_SUB_GROUP_3_VDMA_ERROR_F1_BIT_MUSK) { - /* VDMA_ERROR_F1 */ - USB_Get_Sub_Group_3_IntClear(USB_SUB_GROUP_3_VDMA_ERROR_F1_BIT_MUSK); - } - - if (group3intstatus & USB_SUB_GROUP_3_VDMA_ERROR_F2_BIT_MUSK) { - /* VDMA_ERROR_F2 */ - USB_Get_Sub_Group_3_IntClear(USB_SUB_GROUP_3_VDMA_ERROR_F2_BIT_MUSK); - } - - if (group3intstatus & USB_SUB_GROUP_3_VDMA_ERROR_F3_BIT_MUSK) { - /* VDMA_ERROR_F3 */ - USB_Get_Sub_Group_3_IntClear(USB_SUB_GROUP_3_VDMA_ERROR_F3_BIT_MUSK); - } -} -#endif -static void usb_group4_isr(void) -{ - uint32_t group4intstatus = USB_Get_Sub_Group_4_IntStatus() & ~USB_Get_Sub_Group_4_IntMask(); - - if (group4intstatus & USB_SUB_GROUP_4_L1_BIT_MUSK) { - /* L1_INT */ - USB_Get_Sub_Group_3_IntClear(USB_SUB_GROUP_4_L1_BIT_MUSK); - return; - } -} - -/** - * @brief - * - */ -void USBD_IRQHandler(void) -{ - if (USB_Global_IntStatus(USB_GLOBAL_INT_DEV)) { - /* group 0 int */ - if (USB_Group_IntStatus(USB_GRP_INT_G0)) { - usb_group0_isr(); - } - /* group 1 int */ - if (USB_Group_IntStatus(USB_GRP_INT_G1)) { - usb_group1_isr(); - } - /* group 2 int */ - if (USB_Group_IntStatus(USB_GRP_INT_G2)) { - usb_group2_isr(); - } -#ifdef CONFIG_USB_VDMA_ENABLE - /* group 3 int */ - if (USB_Group_IntStatus(USB_GRP_INT_G3)) { - usb_group3_isr(); - } -#endif - /* group 4 int */ - if (USB_Group_IntStatus(USB_GRP_INT_G4)) { - usb_group4_isr(); - } - } -} - -#ifdef USB_TEST_MODE -void usbd_set_feature(uint16_t index, uint16_t value) -{ - switch (value) { - case 0: //USB_FEATURE_ENDPOINT_HALT - //implement in usb_dc_ep_set_stall - break; - case 1: //USB_FEATURE_REMOTE_WAKEUP - { - uint32_t tmpVal; - tmpVal = BL_RD_REG(USB_BASE, USB_DEV_CTL); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_CAP_RMWAKUP); - BL_WR_REG(USB_BASE, USB_DEV_CTL, tmpVal); - } break; - case 2: //USB_FEATURE_TEST_MODE - switch (index >> 8) { - case 1: // Test_J - { - uint32_t tmpVal; - tmpVal = BL_RD_REG(USB_BASE, USB_PHY_TST); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_TST_JSTA); - BL_WR_REG(USB_BASE, USB_PHY_TST, tmpVal); - } break; - case 2: // Test_K - { - uint32_t tmpVal; - tmpVal = BL_RD_REG(USB_BASE, USB_PHY_TST); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_TST_KSTA); - BL_WR_REG(USB_BASE, USB_PHY_TST, tmpVal); - } break; - case 3: // TEST_SE0_NAK - { - uint32_t tmpVal; - tmpVal = BL_RD_REG(USB_BASE, USB_PHY_TST); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_TST_SE0NAK); - BL_WR_REG(USB_BASE, USB_PHY_TST, tmpVal); - } break; - case 4: // Test_Packet - { - uint32_t tmpVal; - tmpVal = BL_RD_REG(USB_BASE, USB_PHY_TST); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_TST_PKT); - BL_WR_REG(USB_BASE, USB_PHY_TST, tmpVal); - } break; - case 5: // Test_Force_Enable - { - uint8_t temp[53]; - uint8_t *pp; - uint8_t i; - pp = temp; - - for (i = 0; i < 9; i++) /*JKJKJKJK x 9*/ - *pp++ = 0x00; - - for (i = 0; i < 8; i++) /* 8*AA */ - *pp++ = 0xAA; - - for (i = 0; i < 8; i++) /* 8*EE */ - *pp++ = 0xEE; - - *pp++ = 0xFE; - - for (i = 0; i < 11; i++) /* 11*FF */ - *pp++ = 0xFF; - - *pp++ = 0x7F; - *pp++ = 0xBF; - *pp++ = 0xDF; - *pp++ = 0xEF; - *pp++ = 0xF7; - *pp++ = 0xFB; - *pp++ = 0xFD; - *pp++ = 0xFC; - *pp++ = 0x7E; - *pp++ = 0xBF; - *pp++ = 0xDF; - *pp++ = 0xEF; - *pp++ = 0xF7; - *pp++ = 0xFB; - *pp++ = 0xFD; - *pp++ = 0x7E; - - uint32_t tmpVal; - tmpVal = BL_RD_REG(USB_BASE, USB_DEV_CXCFE); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_TST_PKDONE); - BL_WR_REG(USB_BASE, USB_DEV_CXCFE, tmpVal); - - } break; - - default: - break; - } - break; - case 3: //USB_FEATURE_BHNPENABLE - { - uint32_t tmpVal; - tmpVal = BL_RD_REG(USB_BASE, USB_OTG_CSR); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_B_BUS_REQ); - BL_WR_REG(USB_BASE, USB_OTG_CSR, tmpVal); - - tmpVal = BL_RD_REG(USB_BASE, USB_OTG_CSR); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_B_HNP_EN); - BL_WR_REG(USB_BASE, USB_OTG_CSR, tmpVal); - } break; - case 4: //USB_FEATURE_AHNPSUPPORT - - break; - case 5: //USB_FEATURE_AALTHNPSUPPORT - - break; - - default: - break; - } -} - -void usbd_clear_feature(uint16_t index, uint16_t value) -{ - switch (value) { - case 0: //USB_FEATURE_ENDPOINT_HALT - //implement in usb_dc_ep_clear_stall - break; - case 1: //USB_FEATURE_REMOTE_WAKEUP - { - uint32_t tmpVal; - tmpVal = BL_RD_REG(USB_BASE, USB_DEV_CTL); - tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CAP_RMWAKUP); - BL_WR_REG(USB_BASE, USB_DEV_CTL, tmpVal); - } break; - - default: - break; - } -} -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_usb.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_usb.h deleted file mode 100644 index 86f454312a..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_usb.h +++ /dev/null @@ -1,158 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __HAL_USB__H__ -#define __HAL_USB__H__ - -#include "stdint.h" - -/** - * USB endpoint Transfer Type mask. - */ -#define USBD_EP_TYPE_CTRL 0 -#define USBD_EP_TYPE_ISOC 1 -#define USBD_EP_TYPE_BULK 2 -#define USBD_EP_TYPE_INTR 3 -#define USBD_EP_TYPE_MASK 3 - -/** - * USB endpoint direction and number. - */ -#define USB_EP_DIR_MASK 0x80U -#define USB_EP_DIR_IN 0x80U -#define USB_EP_DIR_OUT 0x00U - -#define USB_EP_OUT_MSK 0x7FU -#define USB_EP_IN_MSK 0x80U - -/** Get endpoint index (number) from endpoint address */ -#define USB_EP_GET_IDX(ep) ((ep) & ~USB_EP_DIR_MASK) -/** Get direction from endpoint address */ -#define USB_EP_GET_DIR(ep) ((ep)&USB_EP_DIR_MASK) -/** Get endpoint address from endpoint index and direction */ -#define USB_EP_GET_ADDR(idx, dir) ((idx) | ((dir)&USB_EP_DIR_MASK)) -/** True if the endpoint is an IN endpoint */ -#define USB_EP_DIR_IS_IN(ep) (USB_EP_GET_DIR(ep) == USB_EP_DIR_IN) -/** True if the endpoint is an OUT endpoint */ -#define USB_EP_DIR_IS_OUT(ep) (USB_EP_GET_DIR(ep) == USB_EP_DIR_OUT) - -#define USB_SET_EP_OUT(ep) (ep & USB_EP_OUT_MSK) -#define USB_SET_EP_IN(ep) (ep | USB_EP_IN_MSK) - -#define USB_OUT_EP_NUM 8 -#define USB_IN_EP_NUM 8 - -enum usb_dc_event_type { - /** USB error reported by the controller */ - USB_DC_EVENT_ERROR, - /** USB reset */ - USB_DC_EVENT_RESET, - /** Start of Frame received */ - USB_DC_EVENT_SOF, - /** USB connection established, hardware enumeration is completed */ - USB_DC_EVENT_CONNECTED, - /** USB configuration done */ - USB_DC_EVENT_CONFIGURED, - /** USB connection suspended by the HOST */ - USB_DC_EVENT_SUSPEND, - /** USB connection lost */ - USB_DC_EVENT_DISCONNECTED, - /** USB connection resumed by the HOST */ - USB_DC_EVENT_RESUME, - - /** USB interface selected */ - USB_DC_EVENT_SET_INTERFACE, - /** USB interface selected */ - USB_DC_EVENT_SET_REMOTE_WAKEUP, - /** USB interface selected */ - USB_DC_EVENT_CLEAR_REMOTE_WAKEUP, - /** Set Feature ENDPOINT_HALT received */ - USB_DC_EVENT_SET_HALT, - /** Clear Feature ENDPOINT_HALT received */ - USB_DC_EVENT_CLEAR_HALT, - /** setup packet received */ - USB_DC_EVENT_SETUP_NOTIFY, - /** ep0 in packet received */ - USB_DC_EVENT_EP0_IN_NOTIFY, - /** ep0 out packet received */ - USB_DC_EVENT_EP0_OUT_NOTIFY, - /** ep in packet except ep0 received */ - USB_DC_EVENT_EP_IN_NOTIFY, - /** ep out packet except ep0 received */ - USB_DC_EVENT_EP_OUT_NOTIFY, - /** Initial USB connection status */ - USB_DC_EVENT_UNKNOWN -}; - -enum usb_error_type { - USB_DC_OK = 0, - USB_DC_EP_DIR_ERR = 1, - USB_DC_EP_EN_ERR = 2, - USB_DC_EP_TIMEOUT_ERR = 3, - USB_DC_ADDR_ERR = 4, - USB_DC_DMA_ERR = 5, - USB_DC_VDMA_ERR = 6, - USB_DC_DATA_NONE = 7, -}; -/** - * @brief USB Endpoint Configuration. - * - * Structure containing the USB endpoint configuration. - */ -struct usb_dc_ep_cfg { - /** The number associated with the EP in the device - * configuration structure - * IN EP = 0x80 | \ - * OUT EP = 0x00 | \ - */ - uint8_t ep_addr; - /** Endpoint Transfer Type. - * May be Bulk, Interrupt, Control or Isochronous - */ - uint8_t ep_type; - /** Endpoint max packet size */ - uint16_t ep_mps; -}; - -/* - * USB endpoint structure. - */ -typedef struct -{ - uint8_t ep_ena; - uint8_t is_stalled; - struct usb_dc_ep_cfg ep_cfg; -} usb_dc_ep_state_t; - -typedef struct usb_dc_device { - usb_dc_ep_state_t in_ep[8]; /*!< IN endpoint parameters */ - usb_dc_ep_state_t out_ep[8]; /*!< OUT endpoint parameters */ -} usb_dc_device_t; - -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_wifi.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_wifi.c deleted file mode 100644 index 1a73c370bf..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_wifi.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include -#include "hal_wifi.h" -#include - - -#define WIFI_STACK_SIZE (1536) -#define TASK_PRIORITY_FW (30) - -#ifndef FEATURE_WIFI_DISABLE -#include -int hal_wifi_start_firmware_task(void) -{ - static StackType_t wifi_fw_stack[WIFI_STACK_SIZE]; - static StaticTask_t wifi_fw_task; - - bl_pm_init(); - xTaskCreateStatic(wifi_main, (char*)"fw", WIFI_STACK_SIZE, NULL, TASK_PRIORITY_FW, wifi_fw_stack, &wifi_fw_task); - - return 0; -} -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_wifi.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_wifi.h deleted file mode 100644 index d3df2cd5a8..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_wifi.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __HAL_WIFI_H__ -#define __HAL_WIFI_H__ -int hal_wifi_start_firmware_task(void); -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hosal_adc.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hosal_adc.c deleted file mode 100644 index 233c50838f..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hosal_adc.c +++ /dev/null @@ -1,527 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -//FIXME no BL808/BL606p header file including is Allowed here -#ifdef BL808 -#include -#include -#include -#include -#elif defined(BL606P) -#include -#include -#include -#include -#else -#error "Use CHIP BL808/BL606P for this module" -#endif - -#include -#include -#include -#include - -#define ADC_CLOCK_FREQ 40000000 -#define ADC_GPIO_NUM 12 -#define ADC_CHANNEL_MAX 12 - -typedef struct adc_ctx { - uint32_t *channel_data; - void *adc_lli; - void *llibuf; - int lli_flag; - uint32_t chan_init_table; - uint32_t data_size; -}hosal_adc_ctx_t; - -static hosal_adc_dev_t *pgdevice; - -void adc_data_update (void *p_arg, uint32_t flag) -{ - hosal_adc_dev_t *adc = (hosal_adc_dev_t *)p_arg; - hosal_adc_ctx_t *pstctx = (hosal_adc_ctx_t *)adc->priv; - - if (pstctx->lli_flag == 0) { - pstctx->channel_data = (uint32_t *)((DMA_LLI_Ctrl_Type *)(pstctx->adc_lli))[0].destDmaAddr; - pstctx->lli_flag = 1; - } else { - pstctx->channel_data = (uint32_t *)((DMA_LLI_Ctrl_Type *)(pstctx->adc_lli))[1].destDmaAddr; - pstctx->lli_flag = 0; - } -} - -static int adc_check_gpio_valid(GLB_GPIO_Type pin) -{ - int i; - - GLB_GPIO_Type gpio_arr[ADC_GPIO_NUM] = - { - GLB_GPIO_PIN_4, GLB_GPIO_PIN_5, GLB_GPIO_PIN_6, - GLB_GPIO_PIN_11, GLB_GPIO_PIN_12, GLB_GPIO_PIN_13, - GLB_GPIO_PIN_16, GLB_GPIO_PIN_17, GLB_GPIO_PIN_18, - GLB_GPIO_PIN_19, GLB_GPIO_PIN_34, GLB_GPIO_PIN_40 - }; - - for (i = 0; i < ADC_GPIO_NUM; i++) { - if (pin == gpio_arr[i]) { - return 0; - } - } - - blog_error("gpio %d can not used as adc\r\n", pin); - - return -1; -} - -static int adc_get_channel_by_gpio(GLB_GPIO_Type pin) -{ - int channel = -1; - - switch (pin) { - case GLB_GPIO_PIN_4: - channel = 2; - break; - case GLB_GPIO_PIN_5: - channel = 1; - break; - case GLB_GPIO_PIN_6: - channel = 4; - break; - case GLB_GPIO_PIN_11: - channel = 3; - break; - case GLB_GPIO_PIN_12: - channel = 6; - break; - case GLB_GPIO_PIN_13: - channel = 7; - break; - case GLB_GPIO_PIN_16: - channel = 8; - break; - case GLB_GPIO_PIN_17: - channel = 0; - break; - case GLB_GPIO_PIN_18: - channel = 9; - break; - case GLB_GPIO_PIN_19: - channel = 10; - break; - case GLB_GPIO_PIN_34: - channel = 11; - break; - case GLB_GPIO_PIN_40: - channel = 5; - break; - - default : - channel = -1; - break; - } - - return channel; -} - -static void adc_freq_init(hosal_adc_sample_mode_t mode, uint32_t freq) -{ - uint32_t div; - uint32_t source_freq; - uint32_t mode_freq; - - if (mode == HOSAL_ADC_ONE_SHOT) { - mode_freq = ADC_CHANNEL_MAX; - } else { - mode_freq = 1; - } - - source_freq = ADC_CLOCK_FREQ / (128 * 24 * mode_freq); - - div = source_freq / freq; - if (((div + 1) * freq - source_freq) < (source_freq - freq * div)) { - div = div + 1; - } - - if (div > 64) { - div = 64; - } - - /*adc clk can not more than 2M*/ - /*when adc work at scan mode, adc clk can not more than 1M*/ - blog_info("ADC freq: %ldHz. ,div:%lu\r\n", (int)(source_freq / div), div); - - /* set clk */ - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_GPIP | GLB_AHB_CLOCK_DMA_0); - GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, div-1); -} - -static void adc_dma_lli_init(DMA_LLI_Ctrl_Type *pstlli, uint32_t *buf, uint32_t data_num) -{ - struct DMA_Control_Reg dma_ctrl_reg={ - .TransferSize=0, - .SBSize=DMA_BURST_SIZE_1, - .dst_min_mode=DISABLE, - .DBSize=DMA_BURST_SIZE_1, - .dst_add_mode=DISABLE, - .SWidth=DMA_TRNS_WIDTH_32BITS, - .DWidth=DMA_TRNS_WIDTH_32BITS, - .fix_cnt=0, - .SI=DMA_MINC_DISABLE, - .DI=DMA_MINC_ENABLE, - .I=1, - }; - dma_ctrl_reg.TransferSize = data_num; - - pstlli[0].srcDmaAddr = GPIP_BASE+GPIP_GPADC_DMA_RDATA_OFFSET; - pstlli[0].destDmaAddr = (uint32_t)&buf[0]; - pstlli[0].nextLLI = (uint32_t)&pstlli[1]; - pstlli[0].dmaCtrl= dma_ctrl_reg; - - pstlli[1].srcDmaAddr = GPIP_BASE+GPIP_GPADC_DMA_RDATA_OFFSET; - pstlli[1].destDmaAddr = (uint32_t)&buf[ADC_CHANNEL_MAX]; - pstlli[1].nextLLI = (uint32_t)&pstlli[0]; - pstlli[1].dmaCtrl= dma_ctrl_reg; -} - -static int adc_dma_init(hosal_adc_dev_t *adc, uint32_t data_num) -{ - DMA_LLI_Ctrl_Type *pstlli; - uint32_t *llibuf; - DMA_LLI_Cfg_Type llicfg = { - .dir = DMA_TRNS_P2M, - .srcPeriph = DMA_REQ_GPADC_RX, - .dstPeriph = DMA_REQ_NONE, - }; - - hosal_adc_ctx_t *pstctx = (hosal_adc_ctx_t *)adc->priv; - - if (data_num < 1) { - blog_error("illegal para. \r\n"); - return -1; - } - - adc->dma_chan = hosal_dma_chan_request(0); - - pstlli = pvPortMalloc(sizeof(DMA_LLI_Ctrl_Type) * 2); - if (NULL == pstlli) { - blog_error("malloc lli failed. \r\n"); - return -1; - } - - llibuf = pvPortMalloc(sizeof(uint32_t) * data_num * 2); - if (NULL == llibuf) { - blog_error("malloc lli buf failed. \r\n"); - return -1; - } - - adc_dma_lli_init(pstlli, llibuf, data_num); - DMA_LLI_Init(DMA0_ID, adc->dma_chan, &llicfg); - DMA_LLI_Update(DMA0_ID, adc->dma_chan, (uint32_t)&(pstlli[0])); - - pstctx->llibuf = llibuf; - pstctx->adc_lli = pstlli; - pstctx->lli_flag = 0; - pstctx->chan_init_table = 0; - pstctx->channel_data = NULL; - pstctx->data_size = data_num; - - hosal_dma_irq_callback_set(adc->dma_chan, adc_data_update, adc); - - return 0; -} - -//mode = 0, for normal adc. freq 20HZ~1302HZ -static void adc_init(hosal_adc_dev_t *adc) -{ - int i, chan; - uint8_t channel_table[ADC_CHANNEL_MAX] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11}; - - hosal_adc_sample_mode_t mode = adc->config.mode; - GLB_GPIO_Type pin = adc->config.pin; - - ADC_CFG_Type adccfg; - ADC_Chan_Type pos_chlist_single[ADC_CHANNEL_MAX]; - ADC_Chan_Type neg_chlist_single[ADC_CHANNEL_MAX]; - ADC_FIFO_Cfg_Type adc_fifo_cfg = { - /*dma request will happend when fifo count up to fifoThreshold.*/ - .fifoThreshold = ADC_FIFO_THRESHOLD_1, - .dmaEn = ENABLE, - }; - - adccfg.v18Sel=ADC_V18_SEL_1P82V; - adccfg.v11Sel=ADC_V11_SEL_1P1V; - adccfg.clkDiv=ADC_CLK_DIV_24; - /* one shot mode */ - if (mode == HOSAL_ADC_ONE_SHOT) { - adccfg.gain1=ADC_PGA_GAIN_NONE; - adccfg.gain2=ADC_PGA_GAIN_NONE; - adccfg.chopMode=ADC_CHOP_MOD_AZ_PGA_ON; - } else { - adccfg.gain1=ADC_PGA_GAIN_1; - adccfg.gain2=ADC_PGA_GAIN_1; - adccfg.chopMode=ADC_CHOP_MOD_AZ_PGA_ON; - } - adccfg.biasSel=ADC_BIAS_SEL_MAIN_BANDGAP; - adccfg.vcm=ADC_PGA_VCM_1V; - adccfg.vref=ADC_VREF_3P2V; - adccfg.inputMode=ADC_INPUT_SINGLE_END; - adccfg.resWidth = ADC_DATA_WIDTH_16_WITH_128_AVERAGE; - adccfg.offsetCalibEn=0; - adccfg.offsetCalibVal=0; - - ADC_Disable(); - ADC_Enable(); - ADC_Reset(); - - ADC_Init(&adccfg); - - if (mode == HOSAL_ADC_ONE_SHOT) { - for (i = 0; i < ADC_CHANNEL_MAX; i++) { - pos_chlist_single[i] = channel_table[i];; - neg_chlist_single[i] = ADC_CHAN_GND; - } - - ADC_Scan_Channel_Config(pos_chlist_single, neg_chlist_single, ADC_CHANNEL_MAX, ENABLE); - } - else { - chan = adc_get_channel_by_gpio(pin); - ADC_Channel_Config(chan, ADC_CHAN_GND, ENABLE); - ADC_Mic_Init(NULL); - } - - ADC_FIFO_Cfg(&adc_fifo_cfg); -} - -static void adc_dma_start(hosal_dma_chan_t chan) -{ - ADC_Start(); - - /* refresh cache */ - L1C_DCache_Clean_Invalid_All(); - hosal_dma_chan_start(chan); -} - -static int adc_parse_data(uint32_t *parr, int data_size, int channel) -{ - int i; - int32_t data; - - for (i = 0; i < data_size; i++) { - if (parr[i] >> 21 == channel) { - data = parr[i] & 0xFFFF; - data = (data * 3200) >> 16; - - return data; - } - } - blog_error("error!\r\n"); - return -1; -} - -int hosal_adc_init(hosal_adc_dev_t *adc) -{ - int res = -1; - int freq; - GLB_GPIO_Type pin; - hosal_adc_ctx_t *pstctx; - - if (NULL == adc) { - blog_error("parameter is error!\r\n"); - return -1; - } - - freq = adc->config.sampling_freq; - pin = (GLB_GPIO_Type)adc->config.pin; - - /* check adc pin*/ - res = adc_check_gpio_valid(pin); - if (res) { - blog_error("pin is error!\r\n"); - return -1; - } - - pstctx = (hosal_adc_ctx_t *)pvPortMalloc(sizeof(hosal_adc_ctx_t)); - if (NULL == pstctx) { - blog_error("not have enough memory!\r\n"); - return -1; - } - - memset(pstctx, 0, sizeof(hosal_adc_ctx_t)); - adc->priv = pstctx; - - if (adc->config.mode == HOSAL_ADC_ONE_SHOT) { - if (freq < 20 || freq > 1250) { - blog_error("illegal freq. for mode0, freq 20HZ ~ 1250HZ \r\n"); - return -1; - } - /* init gpio */ - GLB_GPIO_Func_Init(GPIO_FUN_ANALOG, &pin, 1); - - /* init freq */ - adc_freq_init(adc->config.mode, freq); - adc_init(adc); - adc_dma_init(adc, ADC_CHANNEL_MAX); - adc_dma_start(adc->dma_chan); - } else { - blog_error("not support continue mode!\r\n"); - return -1; - } - - pgdevice = adc; - - return 0; -} - -int hosal_adc_add_channel(hosal_adc_dev_t *adc, uint32_t channel) -{ - hosal_adc_ctx_t *pstctx = (hosal_adc_ctx_t *)adc->priv; - - if (NULL == adc) { - blog_error("parameter is error!\r\n"); - return -1; - } - - if (channel > 11) { - blog_error("channel is error!"); - return -1; - } - pstctx->chan_init_table |= 1 << channel; - - return 0; -} - -int hosal_adc_remove_channel(hosal_adc_dev_t *adc, uint32_t channel) -{ - hosal_adc_ctx_t *pstctx = (hosal_adc_ctx_t *)adc->priv; - - if (NULL == adc) { - blog_error("parameter is error!\r\n"); - return -1; - } - - if (channel > 11) { - blog_error("channel is error!\r\n"); - return -1; - } - - pstctx->chan_init_table &= ~(1 << channel); - - return 0; -} - -hosal_adc_dev_t *hosal_adc_device_get(void) -{ - if (NULL == pgdevice) { - blog_error("please init adc first!\r\n"); - return NULL; - } - - return pgdevice; -} - -int hosal_adc_value_get(hosal_adc_dev_t *adc, uint32_t channel, uint32_t timeout) -{ - int val = -1; - hosal_adc_ctx_t *pstctx = (hosal_adc_ctx_t *)adc->priv; - - if (NULL == adc) { - blog_error("parameter is error!\r\n"); - return -1; - } - - if (channel > 11) { - blog_error("channel is error!\r\n"); - return -1; - } - - if (((1 << channel) & pstctx->chan_init_table) == 0) { - blog_error("channel = %d not init as adc \r\n", channel); - return -1; - } - - if (pstctx->channel_data == NULL) { - blog_error("adc sampling not finish. \r\n"); - return -1; - } - - /* refresh cache */ - L1C_DCache_Invalid_By_Addr(pstctx->channel_data, sizeof(uint32_t)*ADC_CHANNEL_MAX); - while ((val = adc_parse_data(pstctx->channel_data, ADC_CHANNEL_MAX, channel)) == -1) { - if (timeout-- == 0) { - return -1; - } - vTaskDelay(1); - } - - return val; -} - -int hosal_adc_tsen_value_get(hosal_adc_dev_t *adc) -{ - blog_error("not support now!\r\n"); - return -1; -} - -int hosal_adc_sample_cb_reg(hosal_adc_dev_t *adc, hosal_adc_cb_t cb) -{ - blog_error("not support now!\r\n"); - return -1; -} - -int hosal_adc_start(hosal_adc_dev_t *adc, void *data, uint32_t size) -{ - blog_error("not support now!\r\n"); - return -1; -} - -int hosal_adc_stop(hosal_adc_dev_t *adc) -{ - return 0; -} - -int hosal_adc_finalize(hosal_adc_dev_t *adc) -{ - hosal_adc_ctx_t *pstctx = (hosal_adc_ctx_t *)adc->priv; - - if (NULL == adc) { - blog_error("parm error!\r\n"); - return -1; - } - - vPortFree(pstctx->llibuf); - vPortFree(pstctx->adc_lli); - vPortFree(pstctx); - ADC_Stop(); - hosal_dma_chan_stop(adc->dma_chan); - hosal_dma_chan_release(adc->dma_chan); - - return 0; -} - diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hosal_dma.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hosal_dma.c deleted file mode 100644 index 984b03e1ac..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hosal_dma.c +++ /dev/null @@ -1,314 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -//FIXME no BL808/BL606p header file including is Allowed here -#ifdef BL808 -#include -#include -#elif defined(BL606P) -#include -#else -#error "Use CHIP BL808/BL606P for this module" -#endif - -#include -#include -#include - -static hosal_dma_dev_t *gp_hosal_dma_dev = NULL; - -static void __dma_irq_process(void *p_arg) -{ - int ch; - uint32_t intclr; - uint32_t tmpval; - uint32_t interr_val; - int tc_flag, interr_flag; - /* Get DMA register */ - uint32_t DMAChs = DMA0_BASE; - hosal_dma_dev_t *dma_dev = (hosal_dma_dev_t *)gp_hosal_dma_dev; - hosal_dma_irq_t pfn; - void *parg; - - if (!dma_dev) - return; - - tmpval = BL_RD_REG(DMAChs, DMA_INTTCSTATUS); - interr_val = BL_RD_REG(DMAChs, DMA_INTERRORSTATUS); - - for (ch = 0; ch < dma_dev->max_chans; ch++) { - tc_flag = BL_GET_REG_BITS_VAL(tmpval, DMA_INTTCSTATUS) & (1 << ch); - interr_flag = BL_GET_REG_BITS_VAL(interr_val, DMA_INTERRORSTATUS) & (1 << ch); - - if((tc_flag != 0) || (interr_flag != 0)) { - if (tc_flag != 0) { - /* tc int, clear interrupt */ - tmpval = BL_RD_REG(DMAChs, DMA_INTTCCLEAR); - intclr = BL_GET_REG_BITS_VAL(tmpval, DMA_INTTCCLEAR); - intclr |= (1 << ch); - tmpval = BL_SET_REG_BITS_VAL(tmpval, DMA_INTTCCLEAR, intclr); - BL_WR_REG(DMAChs, DMA_INTTCCLEAR, tmpval); - - pfn = gp_hosal_dma_dev->used_chan[ch].callback; - parg = gp_hosal_dma_dev->used_chan[ch].p_arg; - if (pfn) { - pfn(parg, HOSAL_DMA_INT_TRANS_COMPLETE); - } - } - - if (interr_flag != 0) { - /* int error, clear interrupt */ - tmpval = BL_RD_REG(DMAChs, DMA_INTERRCLR); - intclr = BL_GET_REG_BITS_VAL(tmpval, DMA_INTERRCLR); - intclr |= (1 << ch); - tmpval = BL_SET_REG_BITS_VAL(tmpval, DMA_INTERRCLR, intclr); - BL_WR_REG(DMAChs, DMA_INTERRCLR, tmpval); - - pfn = gp_hosal_dma_dev->used_chan[ch].callback; - parg = gp_hosal_dma_dev->used_chan[ch].p_arg; - if (pfn) { - pfn(parg, HOSAL_DMA_INT_TRANS_ERROR); - } - } - } - } -} - -static int __dma_int_clear(int ch) -{ - uint32_t tmpVal; - uint32_t intClr; - /* Get DMA register */ - uint32_t DMAChs = DMA0_BASE; - - tmpVal = BL_RD_REG(DMAChs, DMA_INTTCSTATUS); - if((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCSTATUS) & (1 << ch)) != 0) { - /* Clear interrupt */ - tmpVal = BL_RD_REG(DMAChs, DMA_INTTCCLEAR); - intClr = BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCCLEAR); - intClr |= (1 << ch); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_INTTCCLEAR, intClr); - BL_WR_REG(DMAChs, DMA_INTTCCLEAR, tmpVal); - } - - tmpVal = BL_RD_REG(DMAChs, DMA_INTERRORSTATUS); - if((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRORSTATUS) & (1 << ch)) != 0) { - /*Clear interrupt */ - tmpVal = BL_RD_REG(DMAChs, DMA_INTERRCLR); - intClr = BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRCLR); - intClr |= (1 << ch); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_INTERRCLR, intClr); - BL_WR_REG(DMAChs, DMA_INTERRCLR, tmpVal); - } - - return 0; -} - -/** - * @brief Initialises a DMA interface - * - * @return 0 : on success, EIO : if an error occurred with any step - */ -int hosal_dma_init(void) -{ - int i; - if (gp_hosal_dma_dev) { - return 0; - } - - gp_hosal_dma_dev = calloc(sizeof(hosal_dma_dev_t), 1); - if (gp_hosal_dma_dev == NULL) { - blog_error("no memory !!!\r\n"); - return -1; - } - - gp_hosal_dma_dev->max_chans = DMA_CH_MAX; - gp_hosal_dma_dev->used_chan = calloc(sizeof(struct hosal_dma_chan) * DMA_CH_MAX, 1); - if (gp_hosal_dma_dev->used_chan == NULL) { - blog_error("no memory !!!\r\n"); - free(gp_hosal_dma_dev); - gp_hosal_dma_dev = NULL; - return -1; - } - DMA_Enable(DMA0_ID); - for (i = 0; i < gp_hosal_dma_dev->max_chans; i++) { - DMA_Channel_Disable(DMA0_ID, i); - DMA_IntMask(DMA0_ID, i, DMA_INT_ALL, MASK); - } - bl_irq_register(DMA0_ALL_IRQn, __dma_irq_process); - bl_irq_enable(DMA0_ALL_IRQn); - return 0; -} - -/** - * @brief Request a DMA channel - * - * @return < 0 : an error occurred with any step, otherwise is DMA channel number - */ -hosal_dma_chan_t hosal_dma_chan_request(int flag) -{ - int i; - - (void)flag; - - if (!gp_hosal_dma_dev) { - blog_error("please hosal_dma_init !\r\n"); - return -1; - } - - for (i = 0; i < gp_hosal_dma_dev->max_chans; i++) { - if (!gp_hosal_dma_dev->used_chan[i].used) { - gp_hosal_dma_dev->used_chan[i].used = 1; - return i; - } - } - return -1; -} - -/** - * @brief Release a DMA channel - * - * @param[in] chan DMA channel number - * - * @return 0 : on success, EIO : if an error occurred with any step - */ -int hosal_dma_chan_release(hosal_dma_chan_t chan) -{ - if (!gp_hosal_dma_dev) { - blog_error("please hosal_dma_init !\r\n"); - return -1; - } - - if (chan > gp_hosal_dma_dev->max_chans) { - return -1; - } - - hosal_dma_chan_stop(chan); - gp_hosal_dma_dev->used_chan[chan].used = 0; - gp_hosal_dma_dev->used_chan[chan].callback = NULL; - DMA_IntMask(DMA0_ID, chan, DMA_INT_TCOMPLETED, MASK); - DMA_IntMask(DMA0_ID, chan, DMA_INT_ERR, MASK); - return 0; -} - -/** - * @brief DMA channel start - * - * @param[in] chan DMA channel number - * - * @return 0 : on success, EIO : if an error occurred with any step - */ -int hosal_dma_chan_start(hosal_dma_chan_t chan) -{ - if (!gp_hosal_dma_dev) { - blog_error("please hosal_dma_init !\r\n"); - return -1; - } - - if (chan > gp_hosal_dma_dev->max_chans) { - return -1; - } - - DMA_Channel_Enable(DMA0_ID, chan); - return 0; -} - -/** - * @brief DMA channel stop - * - * @param[in] chan DMA channel number - * - * @return 0 : on success, EIO : if an error occurred with any step - */ -int hosal_dma_chan_stop(hosal_dma_chan_t chan) -{ - if (!gp_hosal_dma_dev) { - blog_error("please hosal_dma_init !\r\n"); - return -1; - } - - if (chan > gp_hosal_dma_dev->max_chans) { - return -1; - } - - __dma_int_clear(chan); - DMA_Channel_Disable(DMA0_ID, chan); - return 0; -} - -/** - * @brief DMA irq callback set - * - * @param[in] chan : DMA channel number - * @param[in] pfn : callback function - * @param[in] arg : callback function parameter - * - * @return 0 : on success, EIO : if an error occurred with any step - */ -int hosal_dma_irq_callback_set(hosal_dma_chan_t chan, hosal_dma_irq_t pfn, void *p_arg) -{ - if (!gp_hosal_dma_dev) { - blog_error("please hosal_dma_init !\r\n"); - return -1; - } - - if (chan > gp_hosal_dma_dev->max_chans) { - return -1; - } - - gp_hosal_dma_dev->used_chan[chan].callback = pfn; - gp_hosal_dma_dev->used_chan[chan].p_arg = p_arg; - DMA_IntMask(DMA0_ID, chan, DMA_INT_TCOMPLETED, UNMASK); - DMA_IntMask(DMA0_ID, chan, DMA_INT_ERR, UNMASK); - return 0; -} - -/** - * @brief Deinitialises a DMA interface - * - * @param[in] DMA the interface which should be deinitialised - * - * @return 0 : on success, EIO : if an error occurred with any step - */ -int hosal_dma_finalize(void) -{ - if (!gp_hosal_dma_dev) { - blog_error("please hosal_dma_init !\r\n"); - return -1; - } - - DMA_Disable(DMA0_ID); - bl_irq_disable(DMA0_ALL_IRQn); - - free(gp_hosal_dma_dev); - gp_hosal_dma_dev = NULL; - return 0; -} - diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hosal_pwm.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hosal_pwm.c deleted file mode 100644 index b0330d8e38..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hosal_pwm.c +++ /dev/null @@ -1,267 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -//FIXME no BL808/BL606p header file including is Allowed here -#ifdef BL808 -#include -#include -#elif defined(BL606P) -#include -#include -#else -#error "Use CHIP BL808/BL606P for this module" -#endif - -#include "hosal_pwm.h" -#include "blog.h" - - -#define PWM_CHANNAL_MAX 4 -#define PWM_XCLK_CLK 40000000 -#define PWM_DUTY_MAX 10000 - - -/** - * Initialises a PWM pin - * - * - * @param[in] pwm the PWM device - * - * @return 0 : on success, EIO : if an error occurred with any step - */ -int hosal_pwm_init(hosal_pwm_dev_t *pwm) -{ - GLB_GPIO_Cfg_Type gpioCfg = { - .gpioPin = 0, - .gpioFun = GPIO_FUN_PWM0, //GPIO_FUN_PWM1 - .gpioMode = GPIO_MODE_OUTPUT, - .pullType = GPIO_PULL_DOWN, - .drive = 0, - .smtCtrl = 1, - }; - - PWMx_CFG_Type pwmxCfg = { - .clk = PWM_CLK_XCLK, - .stopMode = PWM_STOP_GRACEFUL, - .clkDiv = 1, - .period = 0, - .intPulseCnt = 0, - .extPol = PWM_BREAK_Polarity_HIGH, - .stpRept = DISABLE, - .adcSrc = PWM_TRIGADC_SOURCE_NONE, - }; - - PWM_CHx_CFG_Type chxCfg = { - .modP = PWM_MODE_ENABLE, - .modN = PWM_MODE_ENABLE, - .polP = PWM_POL_ACTIVE_HIGH, - .polN = PWM_POL_ACTIVE_HIGH, - .idlP = PWM_IDLE_STATE_INACTIVE, - .idlN = PWM_IDLE_STATE_INACTIVE, - .brkP = PWM_BREAK_STATE_INACTIVE, - .brkN = PWM_BREAK_STATE_INACTIVE, - .thresholdL = 0, - .thresholdH = 0, - .dtg = 0, - }; - - if (NULL == pwm || (pwm->port != PWM0_ID && pwm->port != PWM1_ID)) { - blog_error("arg error.\r\n"); - return -1; - } - - gpioCfg.gpioPin = pwm->config.pin; - if (pwm->port == PWM0_ID) - gpioCfg.gpioFun = GPIO_FUN_PWM0; - else if (pwm->port == PWM1_ID) - gpioCfg.gpioFun = GPIO_FUN_PWM1; - GLB_GPIO_Init(&gpioCfg); - - PWMx_Disable(pwm->port); - pwmxCfg.period = PWM_XCLK_CLK/pwm->config.freq; - PWMx_Init(pwm->port, &pwmxCfg); - chxCfg.thresholdL = 0; - chxCfg.thresholdH = (PWM_XCLK_CLK/pwm->config.freq)*pwm->config.duty_cycle/PWM_DUTY_MAX; - PWM_Channelx_Init(pwm->port, pwm->config.pin%PWM_CHANNAL_MAX, &chxCfg); - PWM_Channelx_Pwm_Mode_Set(pwm->port, pwm->config.pin%PWM_CHANNAL_MAX, PWM_MODE_DISABLE, PWM_MODE_DISABLE); - PWMx_Enable(pwm->port); - return 0; -} - -/** - * Starts Pulse-Width Modulation signal output on a PWM pin - * - * @param[in] pwm the PWM device - * - * @return 0 : on success, EIO : if an error occurred with any step - */ -int hosal_pwm_start(hosal_pwm_dev_t *pwm) -{ - if (NULL == pwm || (pwm->port != PWM0_ID && pwm->port != PWM1_ID)) { - blog_error("arg error.\r\n"); - return -1; - } - - PWM_Channelx_Pwm_Mode_Set(pwm->port, pwm->config.pin%PWM_CHANNAL_MAX, PWM_MODE_ENABLE, PWM_MODE_ENABLE); - return 0; -} - -/** - * Stops output on a PWM pin - * - * @param[in] pwm the PWM device, para set duty and freq - * - * @return 0 : on success, EIO : if an error occurred with any step - */ -int hosal_pwm_para_chg(hosal_pwm_dev_t *pwm, hosal_pwm_config_t para) -{ - PWM_CHx_CFG_Type chxCfg = { - .modP = PWM_MODE_ENABLE, - .modN = PWM_MODE_ENABLE, - .polP = PWM_POL_ACTIVE_HIGH, - .polN = PWM_POL_ACTIVE_HIGH, - .idlP = PWM_IDLE_STATE_INACTIVE, - .idlN = PWM_IDLE_STATE_INACTIVE, - .brkP = PWM_BREAK_STATE_INACTIVE, - .brkN = PWM_BREAK_STATE_INACTIVE, - .thresholdL = 0, - .thresholdH = 0, - .dtg = 0, - }; - - if (NULL == pwm || (pwm->port != PWM0_ID && pwm->port != PWM1_ID)) { - blog_error("arg error.\r\n"); - return -1; - } - - chxCfg.thresholdL = 0; - chxCfg.thresholdH = (PWM_XCLK_CLK/para.freq)*para.duty_cycle/PWM_DUTY_MAX; - PWM_Channelx_Init(pwm->port, pwm->config.pin%PWM_CHANNAL_MAX, &chxCfg); - return 0; -} - -/** - * set pwm freq - * - *@param[in] id pwm channel - *@param[in] freq pwm freq - * - *@return 0 : on success -1 : fail - */ -int hosal_pwm_freq_set(hosal_pwm_dev_t *pwm, uint32_t freq) -{ - return -1; -} - -int hosal_pwm_freq_get(hosal_pwm_dev_t *pwm, uint32_t *p_freq) -{ - if (NULL == pwm || (pwm->port != PWM0_ID && pwm->port != PWM1_ID)) { - blog_error("arg error.\r\n"); - return -1; - } - - *p_freq = pwm->config.freq; - return 0; -} - -int hosal_pwm_duty_set(hosal_pwm_dev_t *pwm, uint32_t duty) -{ - PWM_CHx_CFG_Type chxCfg = { - .modP = PWM_MODE_ENABLE, - .modN = PWM_MODE_ENABLE, - .polP = PWM_POL_ACTIVE_HIGH, - .polN = PWM_POL_ACTIVE_HIGH, - .idlP = PWM_IDLE_STATE_INACTIVE, - .idlN = PWM_IDLE_STATE_INACTIVE, - .brkP = PWM_BREAK_STATE_INACTIVE, - .brkN = PWM_BREAK_STATE_INACTIVE, - .thresholdL = 0, - .thresholdH = 0, - .dtg = 0, - }; - - if (NULL == pwm || (pwm->port != PWM0_ID && pwm->port != PWM1_ID)) { - blog_error("arg error.\r\n"); - return -1; - } - - chxCfg.thresholdL = 0; - chxCfg.thresholdH = (PWM_XCLK_CLK/pwm->config.freq)*duty/PWM_DUTY_MAX; - PWM_Channelx_Init(pwm->port, pwm->config.pin%PWM_CHANNAL_MAX, &chxCfg); - return 0; -} - -int hosal_pwm_duty_get(hosal_pwm_dev_t *pwm, uint32_t *p_duty) -{ - if (NULL == pwm || (pwm->port != PWM0_ID && pwm->port != PWM1_ID)) { - blog_error("arg error.\r\n"); - return -1; - } - - *p_duty = pwm->config.duty_cycle; - return 0; -} -/** - * Stops output on a PWM pin - * - * @param[in] pwm the PWM device - * - * @return 0 : on success, EIO : if an error occurred with any step - */ -int hosal_pwm_stop(hosal_pwm_dev_t *pwm) -{ - if (NULL == pwm || (pwm->port != PWM0_ID && pwm->port != PWM1_ID)) { - blog_error("arg error.\r\n"); - return -1; - } - - PWM_Channelx_Pwm_Mode_Set(pwm->port, pwm->config.pin%PWM_CHANNAL_MAX, PWM_MODE_DISABLE, PWM_MODE_DISABLE); - return 0; -} - -/** - * De-initialises an PWM interface, Turns off an PWM hardware interface - * - * @param[in] pwm the interface which should be de-initialised - * - * @return 0 : on success, EIO : if an error occurred with any step - */ -int hosal_pwm_finalize(hosal_pwm_dev_t *pwm) -{ - if (NULL == pwm || (pwm->port != PWM0_ID && pwm->port != PWM1_ID)) { - blog_error("arg error.\r\n"); - return -1; - } - - PWMx_Disable(pwm->port); - return 0; -} - - diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hosal_spi.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hosal_spi.c deleted file mode 100644 index 798e914b7c..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hosal_spi.c +++ /dev/null @@ -1,275 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -//FIXME no BL808/BL606p header file including is Allowed here -#ifdef BL808 -#include -#include -#elif defined(BL606P) -#include -#include -#else -#error "Use CHIP BL808/BL606P for this module" -#endif - -#include "bl808_glb_gpio.h" -#include "hosal_spi.h" -#include "blog.h" - -static void spi_basic_init(hosal_spi_dev_t *arg) -{ - hosal_spi_dev_t *hw_arg = arg; - SPI_CFG_Type spicfg; - SPI_FifoCfg_Type fifocfg; - SPI_ID_Type spi_id; - - spi_id = hw_arg->port; - - /* clock config */ - SPI_SetClock(spi_id, hw_arg->config.freq); - - /* spi config */ - spicfg.deglitchEnable = DISABLE; - spicfg.slavePin = SPI_SLAVE_PIN_4; - spicfg.continuousEnable = ENABLE; - spicfg.byteSequence = SPI_BYTE_INVERSE_BYTE0_FIRST; - spicfg.bitSequence = SPI_BIT_INVERSE_MSB_FIRST; - if (hw_arg->config.polar_phase == 0) { - spicfg.clkPhaseInv = SPI_CLK_PHASE_INVERSE_0; - spicfg.clkPolarity = SPI_CLK_POLARITY_LOW; - } else if (hw_arg->config.polar_phase == 1) { - spicfg.clkPhaseInv = SPI_CLK_PHASE_INVERSE_1; - spicfg.clkPolarity = SPI_CLK_POLARITY_LOW; - } else if (hw_arg->config.polar_phase == 2) { - spicfg.clkPhaseInv = SPI_CLK_PHASE_INVERSE_0; - spicfg.clkPolarity = SPI_CLK_POLARITY_HIGH; - } else if (hw_arg->config.polar_phase == 3) { - spicfg.clkPhaseInv = SPI_CLK_PHASE_INVERSE_1; - spicfg.clkPolarity = SPI_CLK_POLARITY_HIGH; - } else { - blog_error("node support polar_phase \r\n"); - } - spicfg.frameSize = SPI_FRAME_SIZE_8; - SPI_Init(spi_id, &spicfg); - - if (hw_arg->config.mode == 0) { - SPI_Disable(spi_id, SPI_WORK_MODE_MASTER); - } else { - SPI_Disable(spi_id, SPI_WORK_MODE_SLAVE); - } - SPI_IntMask(spi_id, SPI_INT_ALL, MASK); - - /* fifo */ - fifocfg.txFifoThreshold = 1; - fifocfg.rxFifoThreshold = 1; - if (hw_arg->config.dma_enable) { - fifocfg.txFifoDmaEnable = ENABLE; - fifocfg.rxFifoDmaEnable = ENABLE; - SPI_FifoConfig(spi_id,&fifocfg); - } else { - fifocfg.txFifoDmaEnable = DISABLE; - fifocfg.rxFifoDmaEnable = DISABLE; - SPI_FifoConfig(spi_id,&fifocfg); - blog_info("spi no dma mode\r\n"); - } -} - -static int hosal_spi_trans(hosal_spi_dev_t *spi, uint8_t *tx_data, uint8_t *rx_data, uint32_t length, uint32_t timeout) -{ - int ret = -1; - - /* Clear tx and rx fifo */ - SPI_ClrTxFifo(spi->port); - SPI_ClrRxFifo(spi->port); - - if (spi->config.mode == 0) { - SPI_Enable(spi->port, SPI_WORK_MODE_MASTER); - } else { - SPI_Enable(spi->port, SPI_WORK_MODE_SLAVE); - } - - if (tx_data && rx_data) - ret = SPI_SendRecvData(spi->port, tx_data, rx_data, length, SPI_TIMEOUT_DISABLE); - else if (tx_data) - ret = SPI_SendData(spi->port, tx_data, length, SPI_TIMEOUT_DISABLE); - else if (rx_data) - ret = SPI_ReceiveData(spi->port, rx_data, length, SPI_TIMEOUT_DISABLE); - - if (spi->config.mode == 0) { - SPI_Disable(spi->port, SPI_WORK_MODE_MASTER); - } else { - SPI_Disable(spi->port, SPI_WORK_MODE_SLAVE); - } - return ret; -} - -static void hosal_spi_gpio_init(hosal_spi_dev_t *arg) -{ - if (!arg) { - blog_error("arg err.\r\n"); - return; - } - - GLB_GPIO_Type gpiopins[3]; - gpiopins[0] = arg->config.pin_clk; - gpiopins[1] = arg->config.pin_mosi; - gpiopins[2] = arg->config.pin_miso; - GLB_GPIO_Func_Init(GPIO_FUN_SPI0, gpiopins, sizeof(gpiopins)/sizeof(gpiopins[0])); - - if (arg->config.mode == 0) { - if(arg->port == SPI0_ID) { - GLB_Set_MCU_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_MASTER); - } else { - GLB_Set_DSP_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_MASTER); - } - } else { - if(arg->port == SPI0_ID) { - GLB_Set_MCU_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_SLAVE); - } else { - GLB_Set_DSP_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_SLAVE); - } - } - - return; -} - -int hosal_spi_init(hosal_spi_dev_t *spi) -{ - hosal_spi_dev_t *dev = spi; - if (NULL == spi ) { - blog_error("arg err.\r\n"); - } - - hosal_spi_gpio_init(dev); - spi_basic_init(dev); - if (dev->config.dma_enable) { - blog_error("unsupport.\r\n"); - return -1; - } - return 0; -} - -int hosal_spi_set_cs(uint8_t pin, uint8_t value) -{ - GLB_GPIO_Cfg_Type cfg; - cfg.gpioPin = pin; - cfg.gpioFun = GPIO_FUN_GPIO; - cfg.gpioMode = GPIO_MODE_OUTPUT; - cfg.pullType = GPIO_PULL_UP; - cfg.drive = 0; - cfg.smtCtrl = 1; - - if (GLB_GPIO_Get_Fun(pin) != GPIO_FUN_GPIO) - GLB_GPIO_Init(&cfg); - GLB_GPIO_Write(pin, value); - return 0; -} - -int hosal_spi_irq_callback_set(hosal_spi_dev_t *spi, hosal_spi_irq_t pfn, void *p_arg) -{ - if (NULL == spi ) { - blog_error("not init.\r\n"); - return -1; - } - - spi->cb = pfn; - spi->p_arg = p_arg; - return 0; -} - -int hosal_spi_finalize(hosal_spi_dev_t *spi) -{ - if (NULL == spi ) { - blog_error("not init.\r\n"); - return -1; - } - - if (spi->config.dma_enable) { - blog_error("unsupport.\r\n"); - return -1; - } - SPI_DeInit(spi->port); - return 0; -} - -int hosal_spi_send(hosal_spi_dev_t *spi, const uint8_t *data, uint32_t size, uint32_t timeout) -{ - int ret; - - if (NULL == spi || data == NULL) { - blog_error("not init.\r\n"); - return -1; - } - - if (spi->config.dma_enable) { - blog_error("unsupport.\r\n"); - ret = -1; - } else { - ret = hosal_spi_trans(spi, (uint8_t *)data, NULL, size, timeout); - } - return ret; -} - -int hosal_spi_recv(hosal_spi_dev_t *spi, uint8_t *data, uint16_t size, uint32_t timeout) -{ - int ret; - - if (NULL == spi || data == NULL) { - blog_error("not init.\r\n"); - return -1; - } - - if (spi->config.dma_enable) { - blog_error("unsupport.\r\n"); - ret = -1; - } else { - ret = hosal_spi_trans(spi, NULL, data, size, timeout); - } - return ret; -} - -int hosal_spi_send_recv(hosal_spi_dev_t *spi, uint8_t *tx_data, uint8_t *rx_data, uint16_t size, uint32_t timeout) -{ - int ret; - - if (NULL == spi || tx_data == NULL || rx_data == NULL) { - blog_error("not init.\r\n"); - return -1; - } - - if (spi->config.dma_enable) { - blog_error("unsupport.\r\n"); - ret = -1; - } else { - ret = hosal_spi_trans(spi, tx_data, rx_data, size, timeout); - } - return ret; -} - diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hosal_uart.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hosal_uart.c deleted file mode 100644 index 52a61f072a..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hosal_uart.c +++ /dev/null @@ -1,557 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -//FIXME no BL808/BL606p header file including is Allowed here -#ifdef BL808 -#include -#include -#elif defined(BL606P) -#include -#include -#else -#error "Use CHIP BL808/BL606P for this module" -#endif - - -#include "bl_uart.h" -#include "bl_irq.h" -#include "hosal_uart.h" -#include "blog.h" - -// static const uint32_t g_uart_addr[2] = {UART0_BASE, UART1_BASE}; - -static void gpio_init(uint8_t id, uint8_t tx_pin, uint8_t rx_pin, uint8_t cts_pin, uint8_t rts_pin) -{ - GLB_GPIO_Cfg_Type cfg; - GLB_UART_SIG_FUN_Type tx_sigfun, rx_sigfun; - - cfg.drive = 1; - cfg.smtCtrl = 1; - cfg.gpioFun = 7; - - cfg.gpioPin = rx_pin; - cfg.gpioMode = GPIO_MODE_AF; - cfg.pullType = GPIO_PULL_UP; - GLB_GPIO_Init(&cfg); - - cfg.gpioPin = tx_pin; - cfg.gpioMode = GPIO_MODE_AF; - cfg.pullType = GPIO_PULL_UP; - GLB_GPIO_Init(&cfg); - - /* select uart gpio function */ - if (id == 0) { - tx_sigfun = GLB_UART_SIG_FUN_UART0_TXD; - rx_sigfun = GLB_UART_SIG_FUN_UART0_RXD; - } else { - tx_sigfun = GLB_UART_SIG_FUN_UART1_TXD; - rx_sigfun = GLB_UART_SIG_FUN_UART1_RXD; - } - - // clk - //GLB_Set_UART_CLK(1, HBN_UART_CLK_160M, 0); - - GLB_UART_Fun_Sel(tx_pin%12, tx_sigfun); - GLB_UART_Fun_Sel(rx_pin%12, rx_sigfun); -} - -static void __uart_rx_irq(void *p_arg) -{ - hosal_uart_dev_t *uart = (hosal_uart_dev_t *)p_arg; - if (uart->rx_cb) { - uart->rx_cb(uart->p_rxarg); - } -} - -static void __uart_tx_irq(void *p_arg) -{ - hosal_uart_dev_t *uart = (hosal_uart_dev_t *)p_arg; - if (uart->tx_cb) { - uart->tx_cb(uart->p_txarg); - } -} -#if 0 -static void __uart_rx_dma_irq(void *p_arg, uint32_t flag) -{ - hosal_uart_dev_t *uart = (hosal_uart_dev_t *)p_arg; - - if (flag != HOSAL_DMA_INT_TRANS_COMPLETE) { - blog_error("DMA RX TRANS ERROR\r\n"); - } - - if (uart->rxdma_cb) { - uart->rxdma_cb(uart->p_rxdma_arg); - } -} - -static void __uart_tx_dma_irq(void *p_arg, uint32_t flag) -{ - hosal_uart_dev_t *uart = (hosal_uart_dev_t *)p_arg; - - if (flag != HOSAL_DMA_INT_TRANS_COMPLETE) { - blog_error("DMA TX TRANS ERROR\r\n"); - } - - if (uart->txdma_cb) { - uart->txdma_cb(uart->p_txdma_arg); - } -} - -static int __uart_dma_txcfg(hosal_uart_dev_t *uart, hosal_uart_dma_cfg_t *dma_cfg) -{ - if (dma_cfg->dma_buf == NULL || dma_cfg->dma_buf_size == 0) { - return -1; - } - DMA_Channel_Cfg_Type txchCfg = { - (uint32_t)dma_cfg->dma_buf, - g_uart_addr[uart->port] + UART_FIFO_WDATA_OFFSET, - dma_cfg->dma_buf_size, - DMA_TRNS_M2P, - DMA_CH0, - DMA_TRNS_WIDTH_8BITS, - DMA_TRNS_WIDTH_8BITS, - DMA_BURST_SIZE_4, - DMA_BURST_SIZE_4, - DMA_MINC_ENABLE, - DMA_PINC_DISABLE, - DMA_REQ_NONE, - DMA_REQ_UART0_TX, - }; - UART_FifoCfg_Type fifoCfg = - { - .txFifoDmaThreshold = 0x10, - .rxFifoDmaThreshold = 0x10, - .txFifoDmaEnable = ENABLE, - .rxFifoDmaEnable = DISABLE, - }; - - if (uart->dma_tx_chan >= 0) { - DMA_Channel_Update_SrcMemcfg(uart->dma_tx_chan, - (uint32_t)dma_cfg->dma_buf, dma_cfg->dma_buf_size); - return 0; - } - - uart->dma_tx_chan = hosal_dma_chan_request(0); - if (uart->dma_tx_chan < 0) { - blog_error("dma_tx_chan request failed !\r\n"); - return -1; - } - - hosal_dma_chan_stop(uart->dma_tx_chan); - - /* FIFO Config*/ - fifoCfg.rxFifoDmaEnable = (uart->dma_rx_chan < 0) ? DISABLE : ENABLE; - UART_FifoConfig(uart->port, &fifoCfg); - - txchCfg.ch = uart->dma_tx_chan; - txchCfg.dstPeriph = (uart->port == 0) ? DMA_REQ_UART0_TX : DMA_REQ_UART1_TX; - DMA_Channel_Init(&txchCfg); - hosal_dma_irq_callback_set(uart->dma_tx_chan, __uart_tx_dma_irq, (void *)uart); - - return 0; -} - -static int __uart_dma_rxcfg(hosal_uart_dev_t *uart, hosal_uart_dma_cfg_t *dma_cfg) -{ - if (dma_cfg->dma_buf == NULL || dma_cfg->dma_buf_size == 0) { - return -1; - } - - DMA_Channel_Cfg_Type rxchCfg = { - g_uart_addr[uart->port] + UART_FIFO_RDATA_OFFSET, - (uint32_t)dma_cfg->dma_buf, - dma_cfg->dma_buf_size, - DMA_TRNS_P2M, - DMA_CH0, - DMA_TRNS_WIDTH_8BITS, - DMA_TRNS_WIDTH_8BITS, - DMA_BURST_SIZE_16, - DMA_BURST_SIZE_16, - DMA_PINC_DISABLE, - DMA_MINC_ENABLE, - DMA_REQ_UART0_RX, - DMA_REQ_NONE, - }; - UART_FifoCfg_Type fifoCfg = - { - .txFifoDmaThreshold = 0x10, - .rxFifoDmaThreshold = 0x10, - .txFifoDmaEnable = DISABLE, - .rxFifoDmaEnable = ENABLE, - }; - - if (uart->dma_rx_chan >= 0) { - DMA_Channel_Update_DstMemcfg(uart->dma_rx_chan, - (uint32_t)dma_cfg->dma_buf, dma_cfg->dma_buf_size); - return 0; - } - - uart->dma_rx_chan = hosal_dma_chan_request(0); - if (uart->dma_rx_chan < 0) { - blog_error("dma_rx_chan request failed !\r\n"); - return -1; - } - - hosal_dma_chan_stop(uart->dma_rx_chan); - - /* FIFO Config*/ - fifoCfg.txFifoDmaEnable = (uart->dma_tx_chan < 0) ? DISABLE : ENABLE; - UART_FifoConfig(uart->port, &fifoCfg); - - rxchCfg.ch = uart->dma_rx_chan; - rxchCfg.srcPeriph = (uart->port == 0) ? DMA_REQ_UART0_RX : DMA_REQ_UART1_RX; - - DMA_Channel_Init(&rxchCfg); - hosal_dma_irq_callback_set(uart->dma_rx_chan, __uart_rx_dma_irq, (void *)uart); - - return 0; -} -#endif -static void __uart_config_set(hosal_uart_dev_t *uart, const hosal_uart_config_t *cfg) -{ - const uint8_t uart_div = 3; - uint8_t id = uart->port; - -#if 0 - UART_CFG_Type uartCfg = - { - 80*1000*1000, /* UART clock */ - 2000000, /* UART Baudrate */ - UART_DATABITS_8, /* UART data bits length */ - UART_STOPBITS_1, /* UART data stop bits length */ - UART_PARITY_NONE, /* UART no parity */ - DISABLE, /* Disable auto flow control */ - DISABLE, /* Disable rx input de-glitch function */ - DISABLE, /* Disable RTS output SW control mode */ - UART_LSB_FIRST /* UART each data byte is send out LSB-first */ - }; - - uartCfg.baudRate = cfg->baud_rate; - uartCfg.dataBits = (UART_DataBits_Type)cfg->data_width; - uartCfg.parity = (UART_Parity_Type)cfg->parity; - - if (cfg->flow_control == HOSAL_FLOW_CONTROL_CTS) { - uartCfg.ctsFlowControl = 1; - uartCfg.rtsSoftwareControl = 0; - } else if (cfg->flow_control == HOSAL_FLOW_CONTROL_RTS) { - uartCfg.ctsFlowControl = 0; - uartCfg.rtsSoftwareControl = 1; - } else if (cfg->flow_control == HOSAL_FLOW_CONTROL_CTS_RTS) { - uartCfg.ctsFlowControl = 1; - uartCfg.rtsSoftwareControl = 1; - } else { - uartCfg.ctsFlowControl = 0; - uartCfg.rtsSoftwareControl = 0; - } - - //uartCfg.uartClk = (160 * 1000 * 1000) / (uart_div + 1); - - /* Disable uart before config */ - UART_Disable(id, UART_TXRX); - - /* UART init */ - UART_Init(id, &uartCfg); -#endif - if (cfg->mode == HOSAL_UART_MODE_INT) { - bl_uart_int_tx_notify_register(uart->port, __uart_tx_irq, uart); - bl_uart_int_rx_notify_register(uart->port, __uart_rx_irq, uart); - bl_uart_int_enable(uart->port); - bl_uart_int_tx_disable(uart->port); - } else { - bl_uart_int_disable(uart->port); - } - - /* Enable uart */ - UART_Enable(id, UART_TXRX); -} - -int hosal_uart_init(hosal_uart_dev_t *uart) -{ - static uint8_t uart_clk_init = 0; - const uint8_t uart_div = 3; - hosal_uart_config_t *cfg = &uart->config; - uint8_t id; - - UART_CFG_Type uartCfg = - { - 80*1000*1000, /* UART clock */ - 2000000, /* UART Baudrate */ - UART_DATABITS_8, /* UART data bits length */ - UART_STOPBITS_1, /* UART data stop bits length */ - UART_PARITY_NONE, /* UART no parity */ - DISABLE, /* Disable auto flow control */ - DISABLE, /* Disable rx input de-glitch function */ - DISABLE, /* Disable RTS output SW control mode */ - UART_LSB_FIRST /* UART each data byte is send out LSB-first */ - }; - UART_FifoCfg_Type fifoCfg = - { - .txFifoDmaThreshold = 0x10, - .rxFifoDmaThreshold = 0x10, - .txFifoDmaEnable = DISABLE, - .rxFifoDmaEnable = DISABLE, - }; - - /* enable clk */ - -#if 0 - if (0 == uart_clk_init) { - GLB_Set_UART_CLK(1, HBN_UART_CLK_160M, uart_div); - uart_clk_init = 1; - } -#endif - - uart->dma_rx_chan = -1; - uart->dma_tx_chan = -1; - id = cfg->uart_id; - uart->port = cfg->uart_id; - - /* gpio init */ - //gpio_init(id, cfg->tx_pin, cfg->rx_pin, cfg->cts_pin, cfg->rts_pin); - - uartCfg.baudRate = cfg->baud_rate; - uartCfg.dataBits = (UART_DataBits_Type)cfg->data_width; - uartCfg.parity = (UART_Parity_Type)cfg->parity; - - if (cfg->flow_control == HOSAL_FLOW_CONTROL_CTS) { - uartCfg.ctsFlowControl = 1; - uartCfg.rtsSoftwareControl = 0; - } else if (cfg->flow_control == HOSAL_FLOW_CONTROL_RTS) { - uartCfg.ctsFlowControl = 0; - uartCfg.rtsSoftwareControl = 1; - } else if (cfg->flow_control == HOSAL_FLOW_CONTROL_CTS_RTS) { - uartCfg.ctsFlowControl = 1; - uartCfg.rtsSoftwareControl = 1; - } else { - uartCfg.ctsFlowControl = 0; - uartCfg.rtsSoftwareControl = 0; - } - - //uartCfg.uartClk = (40 * 1000 * 1000) / (uart_div + 1); - - /* Disable all interrupt */ - UART_IntMask(id, UART_INT_ALL, MASK); - - /* Disable uart before config */ - UART_Disable(id, UART_TXRX); - - if (UART_GetRxBusBusyStatus(id) == SET) { - UART_DeInit(id); - } - - /* UART init */ - UART_Init(id, &uartCfg); - - /* Enable tx free run mode */ - UART_TxFreeRun(id, ENABLE); - - /* FIFO Config*/ - UART_FifoConfig(id, &fifoCfg); - - if (cfg->mode == HOSAL_UART_MODE_INT) { - bl_uart_int_tx_notify_register(uart->port, __uart_tx_irq, uart); - bl_uart_int_rx_notify_register(uart->port, __uart_rx_irq, uart); - bl_uart_int_enable(uart->port); - bl_uart_int_tx_disable(uart->port); - } else { - bl_uart_int_disable(uart->port); - } - - /* Enable uart */ - UART_Enable(id, UART_TXRX); - return 0; -} - -int hosal_uart_receive(hosal_uart_dev_t *uart, void *data, uint32_t expect_size) -{ - int ch; - uint32_t counter = 0; - - while (counter < expect_size) { - if ((ch = bl_uart_data_recv(uart->port)) < 0) { - break; - } - ((uint8_t*)data)[counter] = ch; - counter++; - } - return counter; -} - -int hosal_uart_send(hosal_uart_dev_t *uart, const void *data, uint32_t size) -{ - uint32_t i = 0; - - while (i < size) { - bl_uart_data_send(uart->port, ((uint8_t*)data)[i]); - i++; - } - return i; -} - -int hosal_uart_ioctl(hosal_uart_dev_t *uart, int ctl, void *p_arg) -{ -#if 0 - hosal_uart_dma_cfg_t *dma_cfg; -#endif - - switch (ctl) { - case HOSAL_UART_BAUD_SET: - uart->config.baud_rate = (uint32_t)p_arg; - __uart_config_set(uart, &uart->config); - break; - case HOSAL_UART_BAUD_GET: - if (p_arg) { - *(uint32_t *)p_arg = uart->config.baud_rate; - } - break; - case HOSAL_UART_DATA_WIDTH_SET: - uart->config.data_width = (hosal_uart_data_width_t)p_arg; - __uart_config_set(uart, &uart->config); - break; - case HOSAL_UART_DATA_WIDTH_GET: - if (p_arg) { - *(hosal_uart_data_width_t *)p_arg = uart->config.data_width; - } - break; - case HOSAL_UART_STOP_BITS_SET: - uart->config.stop_bits = (hosal_uart_stop_bits_t)p_arg; - __uart_config_set(uart, &uart->config); - break; - case HOSAL_UART_STOP_BITS_GET: - if (p_arg) { - *(hosal_uart_stop_bits_t *)p_arg = uart->config.stop_bits; - } - break; - case HOSAL_UART_FLOWMODE_SET: - uart->config.flow_control = (hosal_uart_flow_control_t)p_arg; - __uart_config_set(uart, &uart->config); - break; - case HOSAL_UART_FLOWSTAT_GET: - if (p_arg) { - *(hosal_uart_flow_control_t *)p_arg = uart->config.flow_control; - } - break; - case HOSAL_UART_PARITY_SET: - uart->config.parity = (hosal_uart_parity_t)p_arg; - __uart_config_set(uart, &uart->config); - break; - case HOSAL_UART_PARITY_GET: - if (p_arg) { - *(hosal_uart_parity_t *)p_arg = uart->config.parity; - } - break; - case HOSAL_UART_MODE_SET: - uart->config.mode = (hosal_uart_mode_t)p_arg; - __uart_config_set(uart, &uart->config); - break; - case HOSAL_UART_MODE_GET: - if (p_arg) { - *(hosal_uart_mode_t *)p_arg = uart->config.mode; - } - break; - case HOSAL_UART_FREE_TXFIFO_GET: - if (p_arg) { - *(uint32_t *)p_arg = UART_GetTxFifoCount(uart->port); - } - break; - case HOSAL_UART_FREE_RXFIFO_GET: - if (p_arg) { - *(uint32_t *)p_arg = UART_GetRxFifoCount(uart->port); - } - break; - case HOSAL_UART_FLUSH: - bl_uart_flush(uart->port); - break; - case HOSAL_UART_TX_TRIGGER_ON: - bl_uart_int_tx_enable(uart->port); - break; - case HOSAL_UART_TX_TRIGGER_OFF: - bl_uart_int_tx_disable(uart->port); - break; -#if 0 - case HOSAL_UART_DMA_TX_START: - dma_cfg = (hosal_uart_dma_cfg_t *)p_arg; - if (__uart_dma_txcfg(uart, dma_cfg) != 0) { - return -1; - } - hosal_dma_chan_start(uart->dma_tx_chan); - break; - case HOSAL_UART_DMA_RX_START: - dma_cfg = (hosal_uart_dma_cfg_t *)p_arg; - if (__uart_dma_rxcfg(uart, dma_cfg) != 0) { - return -1; - } - hosal_dma_chan_start(uart->dma_rx_chan); - break; -#endif - default : - return -1; - } - return 0; -} - -int hosal_uart_callback_set(hosal_uart_dev_t *uart, - int callback_type, - hosal_uart_callback_t pfn_callback, - void *arg) -{ - if (callback_type == HOSAL_UART_TX_CALLBACK) { - uart->tx_cb = pfn_callback; - uart->p_txarg = arg; - } else if (callback_type == HOSAL_UART_RX_CALLBACK) { - uart->rx_cb = pfn_callback; - uart->p_rxarg = arg; - } -#if 0 - else if (callback_type == HOSAL_UART_TX_DMA_CALLBACK) { - uart->txdma_cb = pfn_callback; - uart->p_txdma_arg = arg; - } else if (callback_type == HOSAL_UART_RX_DMA_CALLBACK) { - uart->rxdma_cb = pfn_callback; - uart->p_rxdma_arg = arg; - } -#endif - return 0; -} - -int hosal_uart_finalize(hosal_uart_dev_t *uart) -{ - bl_uart_int_disable(uart->port); - UART_Disable(uart->port, UART_TXRX); -#if 0 - if (uart->dma_rx_chan > 0) { - hosal_dma_chan_release(uart->dma_rx_chan); - } - if (uart->dma_tx_chan > 0) { - hosal_dma_chan_release(uart->dma_tx_chan); - } -#endif - return 0; -} diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/phy_8720.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/phy_8720.c deleted file mode 100644 index c8cd6e0b5f..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/phy_8720.c +++ /dev/null @@ -1,419 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include "hal_emac.h" -#include "ethernet_phy.h" - -/* LAN8720 PHY Address*/ -#define EMAC_PHY_ADDRESS 0x00U -#define PHY_LINK_TO ((uint32_t)0x00000FFFU) -#define PHY_AUTONEGO_COMPLETED_TO ((uint32_t)0x00000FFFU) -/* Section 3: Common PHY Registers */ -#define PHY_BCR ((uint16_t)0x00U) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x01U) /*!< Transceiver Basic Status Register */ -#define PHY_BSR_100BASETXFULL (1 << 14) -#define PHY_BSR_100BASETXHALF (1 << 13) -#define PHY_BSR_10BASETXFULL (1 << 12) -#define PHY_BSR_10BASETXHALF (1 << 11) -#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ - -#define PHY_PHYID1 ((uint16_t)0x02U) /*!< PHY ID 1 */ -#define PHY_PHYID2 ((uint16_t)0x03U) /*!< PHY ID 2 */ -#define PHY_ADVERTISE ((uint16_t)0x04U) /*!< Auto-negotiation advertisement */ -#define PHY_ADVERTISE_100BASETXFULL (1 << 8) -#define PHY_ADVERTISE_100BASETXHALF (1 << 7) -#define PHY_ADVERTISE_10BASETXFULL (1 << 6) -#define PHY_ADVERTISE_10BASETXHALF (1 << 5) -#define PHY_ADVERTISE_8023 (1 << 0) -#define PHY_LPA ((uint16_t)0x05U) /*!< Auto-negotiation link partner base page ability */ -#define PHY_EXPANSION ((uint16_t)0x06U) /*!< Auto-negotiation expansion */ -/* Section 4: Extended PHY Registers */ -#define PHY_CTRL_STATUS ((uint16_t)17U) /*!< PHY MODE CONTROL/STATUS REGISTER Offset */ -#define PHY_CTRL_STATUS_EDPWRDOWN (1 << 13) /*!< EDPWRDOWN */ -#define PHY_CTRL_STATUS_ENERGYON (1 << 1) /*!< ENERGYON */ - -#define PHY_SPECIAL_MODES ((uint16_t)18U) /*!< PHY SPECIAL MODES REGISTER Offset */ -#define PHY_SPECIAL_MODES_MODE (7 << 5) /*!< Transceiver mode of operation */ -#define PHY_SPECIAL_MODES_MODE_PWRDOWN (6 << 5) /*!< All capable. Auto-negotiation enabled */ -#define PHY_SPECIAL_MODES_MODE_ALL (7 << 5) /*!< All capable. Auto-negotiation enabled */ -#define PHY_SPECIAL_MODES_PHYAD (0x1F << 0) /*!< PHY Address */ - -#define PHY_SR ((uint16_t)0x1FU) /*!< PHY special control/ status register Offset */ -#define PHY_SR_SPEED_OFFSET (2) -#define PHY_SR_SPEED_MASK (0x7 << PHY_SR_SPEED_OFFSET) -#define PHY_SR_SPEED_10BASETXHALF (0x1 << PHY_SR_SPEED_OFFSET) -#define PHY_SR_SPEED_10BASETXFULL (0x5 << PHY_SR_SPEED_OFFSET) -#define PHY_SR_SPEED_100BASETXHALF (0x2 << PHY_SR_SPEED_OFFSET) -#define PHY_SR_SPEED_100BASETXFULL (0x6 << PHY_SR_SPEED_OFFSET) -#define PHY_SR_SPEED_MODE_COMPARE(status, mode) (!!(mode == (status & PHY_SR_SPEED_MASK))) -#define PHY_SPEED_STATUS ((uint16_t)0x0004U) /*!< PHY Speed mask */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0010U) /*!< PHY Duplex mask */ -#define PHY_ISFR ((uint16_t)0x1DU) /*!< PHY Interrupt Source Flag register Offset */ -#define PHY_ISFR_INT4 ((uint16_t)0x0010U) /*!< PHY Link down inturrupt */ - -static emac_phy_cfg_t *phy_8720_cfg = NULL; - -int phy_8720_reset(void) -{ - int timeout = 1000; - uint16_t regval = PHY_RESET; - - /* pull the PHY from power down mode if it is in */ - if (0 != emac_phy_reg_read(PHY_SPECIAL_MODES, ®val)) { - return -1; - } - - if (PHY_SPECIAL_MODES_MODE_PWRDOWN == (regval & PHY_SPECIAL_MODES_MODE)) { - if (emac_phy_reg_write(PHY_SPECIAL_MODES, regval | PHY_SPECIAL_MODES_MODE_ALL) != 0) { - return -1; - } - } - - /* disable energy detect powerdown mode for cable detect, this increase the power by 220mW */ - if (0 != emac_phy_reg_read(PHY_CTRL_STATUS, ®val)) { - return -1; - } - - if (emac_phy_reg_write(PHY_CTRL_STATUS, regval & (~PHY_CTRL_STATUS_EDPWRDOWN)) != 0) { - return -1; - } - - /* do sw reset */ - if (emac_phy_reg_write(PHY_BCR, PHY_RESET) != 0) { - return -1; - } - - for (; timeout; timeout--) { - if (0 != emac_phy_reg_read(PHY_BCR, ®val)) { - return -1; - } - - if (!(regval & PHY_RESET)) { - return 0; - } - - arch_delay_ms(1); - } - - return -1; -} - -int phy_8720_auto_negotiate(emac_phy_cfg_t *cfg) -{ - uint16_t regval = 0; - uint16_t phyid1 = 0, phyid2 = 0; - uint16_t advertise = 0; - uint16_t lpa = 0; - uint32_t timeout = 100; //10s,in 100ms - - if (0 != emac_phy_reg_read(PHY_PHYID1, &phyid1)) { - // MSG("read emac phy id 1 error\r\n"); - return -1; - } - - if (0 != emac_phy_reg_read(PHY_PHYID2, &phyid2)) { - MSG("read emac phy id 2 error\r\n"); - return -1; - } - MSG("emac phy id 1 =%08x\r\n",(unsigned int )phyid1); - MSG("emac phy id 2 =%08x\r\n",(unsigned int )phyid2); - if (cfg->phy_id != (((phyid1 << 16) | phyid2) & 0x000FFFF0)) { - /* ID error */ - return -1; - } else { - cfg->phy_id = (phyid1 << 16) | phyid2; - } - - if (0 != emac_phy_reg_read(PHY_BCR, ®val)) { - return -1; - } - - regval &= ~PHY_AUTONEGOTIATION; - regval &= ~(PHY_LOOPBACK | PHY_POWERDOWN); - regval |= PHY_ISOLATE; - - if (emac_phy_reg_write(PHY_BCR, regval) != 0) { - return -1; - } - - /* set advertisement mode */ - advertise = PHY_ADVERTISE_100BASETXFULL | PHY_ADVERTISE_100BASETXHALF | - PHY_ADVERTISE_10BASETXFULL | PHY_ADVERTISE_10BASETXHALF | - PHY_ADVERTISE_8023; - - if (emac_phy_reg_write(PHY_ADVERTISE, advertise) != 0) { - return -1; - } - - arch_delay_ms(16); - - if (0 != emac_phy_reg_read(PHY_BCR, ®val)) { - return -1; - } - - arch_delay_ms(16); - regval |= (PHY_FULLDUPLEX_100M | PHY_AUTONEGOTIATION); - - if (emac_phy_reg_write(PHY_BCR, regval) != 0) { - return -1; - } - - arch_delay_ms(16); - regval |= PHY_RESTART_AUTONEGOTIATION; - regval &= ~PHY_ISOLATE; - - if (emac_phy_reg_write(PHY_BCR, regval) != 0) { - return -1; - } - - arch_delay_ms(100); - - while (1) { - if (0 != emac_phy_reg_read(PHY_BSR, ®val)) { - return -1; - } - - if (regval & PHY_AUTONEGO_COMPLETE) { - /* complete */ - break; - } - - if (!(--timeout)) { - return -1; - } - - arch_delay_ms(100); - } - - arch_delay_ms(100); - - if (0 != emac_phy_reg_read(PHY_LPA, &lpa)) { - return -1; - } - - if (((advertise & lpa) & PHY_ADVERTISE_100BASETXFULL) != 0) { - /* 100BaseTX and Full Duplex */ - cfg->full_duplex = 1; - cfg->speed = 100; - cfg->phy_state = PHY_STATE_READY; - } else if (((advertise & lpa) & PHY_ADVERTISE_10BASETXFULL) != 0) { - /* 10BaseT and Full Duplex */ - cfg->full_duplex = 1; - cfg->speed = 10; - cfg->phy_state = PHY_STATE_READY; - } else if (((advertise & lpa) & PHY_ADVERTISE_100BASETXHALF) != 0) { - /* 100BaseTX and half Duplex */ - cfg->full_duplex = 0; - cfg->speed = 100; - cfg->phy_state = PHY_STATE_READY; - } else if (((advertise & lpa) & PHY_ADVERTISE_10BASETXHALF) != 0) { - /* 10BaseT and half Duplex */ - cfg->full_duplex = 0; - cfg->speed = 10; - cfg->phy_state = PHY_STATE_READY; - } - - return 0; -} - -int phy_8720_link_up(emac_phy_cfg_t *cfg) -{ - uint16_t phy_bsr = 0; - uint16_t phy_sr = 0; - - arch_delay_ms(16); - - if (0 != emac_phy_reg_read(PHY_BSR, &phy_bsr)) { - return -1; - } - - arch_delay_ms(16); - - if (!(PHY_LINKED_STATUS & phy_bsr)) { - return ERROR; - } - - arch_delay_ms(16); - - if (0 != emac_phy_reg_read(PHY_SR, &phy_sr)) { - return -1; - } - - if ((phy_bsr & PHY_BSR_100BASETXFULL) && PHY_SR_SPEED_MODE_COMPARE(phy_sr, PHY_SR_SPEED_100BASETXFULL)) { - /* 100BaseTX and Full Duplex */ - cfg->full_duplex = 1; - cfg->speed = 100; - cfg->phy_state = PHY_STATE_UP; - } else if ((phy_bsr & PHY_BSR_10BASETXFULL) && PHY_SR_SPEED_MODE_COMPARE(phy_sr, PHY_SR_SPEED_10BASETXFULL)) { - /* 10BaseT and Full Duplex */ - cfg->full_duplex = 1; - cfg->speed = 10; - cfg->phy_state = PHY_STATE_UP; - } else if ((phy_bsr & PHY_BSR_100BASETXHALF) && PHY_SR_SPEED_MODE_COMPARE(phy_sr, PHY_SR_SPEED_100BASETXHALF)) { - /* 100BaseTX and half Duplex */ - cfg->full_duplex = 0; - cfg->speed = 100; - cfg->phy_state = PHY_STATE_UP; - } else if ((phy_bsr & PHY_BSR_10BASETXHALF) && PHY_SR_SPEED_MODE_COMPARE(phy_sr, PHY_SR_SPEED_10BASETXHALF)) { - /* 10BaseT and half Duplex */ - cfg->full_duplex = 0; - cfg->speed = 10; - cfg->phy_state = PHY_STATE_UP; - } else { - /* 10BaseT and half Duplex */ - cfg->full_duplex = -1; - cfg->speed = -1; - cfg->phy_state = PHY_STATE_DOWN; - return -1; - } - - return 0; -} - -/****************************************************************************** - * @brief Use energy detector for cable plug in/out detect. - * - * @param cfg: EMAC PHY configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -int phy_8720_poll_cable_status(emac_phy_cfg_t *cfg) -{ - uint16_t phy_regval = 0; - - CHECK_PARAM(NULL != phy_8720_cfg); - - if (0 != emac_phy_reg_read(PHY_CTRL_STATUS, &phy_regval)) { - return -1; - } - - phy_8720_cfg->phy_state = (PHY_CTRL_STATUS_ENERGYON & phy_regval) ? - PHY_STATE_UP : - PHY_STATE_DOWN; - - return !!(PHY_CTRL_STATUS_ENERGYON & phy_regval); -} - -/****************************************************************************/ /** - * @brief Initialize EMAC PHY module - * - * @param cfg: EMAC PHY configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -int emac_phy_init(emac_phy_cfg_t *cfg) -{ - uint16_t phyReg; - - CHECK_PARAM(NULL != cfg); - - phy_8720_cfg = cfg; - - emac_phy_set_address(cfg->phy_address); - - if (0 != phy_8720_reset()) { - return -1; - } - - if (cfg->auto_negotiation) { - /* - uint32_t cnt=0; - do{ - if(emac_phy_reg_read(PHY_BSR, &phyReg) != SUCCESS){ - return ERROR; - } - cnt++; - if(cnt>PHY_LINK_TO){ - return ERROR; - } - }while((phyReg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS); - */ - if (0 != phy_8720_auto_negotiate(cfg)) { - return -1; - } - } else { - if (emac_phy_reg_read(PHY_BCR, &phyReg) != 0) { - return -1; - } - - phyReg &= (~PHY_FULLDUPLEX_100M); - - if (cfg->speed == 10) { - if (cfg->full_duplex == 1) { - phyReg |= PHY_FULLDUPLEX_10M; - } else { - phyReg |= PHY_HALFDUPLEX_10M; - } - } else { - if (cfg->full_duplex == 1) { - phyReg |= PHY_FULLDUPLEX_100M; - } else { - phyReg |= PHY_HALFDUPLEX_100M; - } - } - - if ((emac_phy_reg_write(PHY_BCR, phyReg)) != 0) { - return -1; - } - } - - emac_phy_config_full_duplex(cfg->full_duplex); - - return phy_8720_link_up(cfg); -} - -emac_phy_status_t ethernet_phy_status_get() -{ - CHECK_PARAM(NULL != phy_8720_cfg); - - if ((100 == phy_8720_cfg->speed) && - (phy_8720_cfg->full_duplex) && - (PHY_STATE_UP == phy_8720_cfg->phy_state)) { - return EMAC_PHY_STAT_100MBITS_FULLDUPLEX; - } else if (PHY_STATE_UP == phy_8720_cfg->phy_state) { - return EMAC_PHY_STAT_LINK_UP; - } else { - return EMAC_PHY_STAT_LINK_DOWN; - } -} diff --git a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_adc.h b/bsp/bl808/m0/libraries/platform/hosal/include/hosal_adc.h deleted file mode 100644 index 66fbecf04a..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_adc.h +++ /dev/null @@ -1,238 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __HOSAL_ADC_H_ -#define __HOSAL_ADC_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include "hosal_dma.h" - -/** @addtogroup hosal_adc ADC - * HOSAL ADC API - * - * @{ - */ - -#define HOSAL_WAIT_FOREVER 0xFFFFFFFFU /**< @brief Define the wait forever timeout macro */ - -/** - * @brief ADC interrupt events - */ -typedef enum __ADC_INT_EVENTS__{ - HOSAL_ADC_INT_OV, /**< @brief Overrun error */ - HOSAL_ADC_INT_EOS, /**< @brief End of sample */ - HOSAL_ADC_INT_DMA_TRH, /**< @brief DMA transceive half */ - HOSAL_ADC_INT_DMA_TRC, /**< @brief DMA transceive complete */ - HOSAL_ADC_INT_DMA_TRE, /**< @briefDMA transceive error */ -} hosal_adc_event_t; - -/** - * @brief ADC data type - */ -typedef struct { - uint32_t size; /**< @brief sampled data size */ - void *data; /**< @brief sampled data, aligned with resolution (until the next power of two) */ -} hosal_adc_data_t; - -/** - * @brief ADC MODE type - */ -typedef enum { - HOSAL_ADC_ONE_SHOT, /**< @brief Single time sampling */ - HOSAL_ADC_CONTINUE /**< @brief Continuous sampling */ -} hosal_adc_sample_mode_t; - -/** - * @brief Define ADC config args - */ -typedef struct { - uint32_t sampling_freq; /**< @brief sampling frequency in Hz */ - uint32_t pin; /**< @brief adc pin */ - hosal_adc_sample_mode_t mode; /**< @brief adc sampling mode */ - uint8_t sample_resolution; /**< @brief adc sampling resolution */ -} hosal_adc_config_t; - -/** - * @brief ADC interrupt function - * - *@param[in] parg Set the custom parameters specified - * - */ -typedef void (*hosal_adc_irq_t)(void *parg); - -/** - * @brief Define ADC dev hosal handle - */ -typedef struct { - uint8_t port; /**< @brief adc port */ - hosal_adc_config_t config; /**< @brief adc config */ - hosal_dma_chan_t dma_chan; /**< @brief adc dma channel */ - hosal_adc_irq_t cb; /**< @brief adc callback */ - void *p_arg; /**< @brief p_arg data */ - void *priv; /**< @brief priv data */ -} hosal_adc_dev_t; - -/** - * @brief ADC interrupt callback - * - * @param[in] parg Set the custom parameters specified when the callback function is set - * - */ -typedef void (*hosal_adc_cb_t)(hosal_adc_event_t event, void *data, uint32_t size); - -/** - * @brief Initialises an ADC interface, Prepares an ADC hardware interface for sampling - * - * @param[in] adc the interface which should be initialised - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_adc_init(hosal_adc_dev_t *adc); - -/** - * @brief Add a channel to an ADC interface - * - * @param[in] adc the interface which should be sampled - * @param[in] channel adc channel - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_adc_add_channel(hosal_adc_dev_t *adc, uint32_t channel); - -/** - * @brief Remove a channel to an ADC interface - * - * @param[in] adc the interface which should be sampled - * @param[in] channel adc channel - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_adc_remove_channel(hosal_adc_dev_t *adc, uint32_t channel); - -/** - * @brief Takes adc device handle from an ADC interface - * - * @return - * - other get adc device success - * - NULL if an error occurred with any step - */ -hosal_adc_dev_t *hosal_adc_device_get(void); - -/** - * @brief Takes a single sample from an ADC interface - * - * @param[in] adc the interface which should be sampled - * @param[in] channel adc channel - * @param[in] timeout ms timeout - * - * @return - * - other get adc data success - * - -1 if an error occurred with any step - */ -int hosal_adc_value_get(hosal_adc_dev_t *adc, uint32_t channel, uint32_t timeout); - -/** - * @brief Takes a tsen sample from an ADC interface - * - * @param[in] adc the interface which should be sampled - * - * @return - * - other get adc data success - * - -1 if an error occurred with any step - */ -int hosal_adc_tsen_value_get(hosal_adc_dev_t *adc); - -/** - * @brief ADC sampling cb register - * - * @param [in] adc the ADC interface - * @param [in] cb Non-zero pointer is the sample callback handler - * NULL pointer for send unregister operation - * adc in cb must be the same pointer with adc pointer passed to hosal_adc_sample_cb_reg - * driver must notify upper layer by calling cb if ADC data is ready in HW or memory(DMA) - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_adc_sample_cb_reg(hosal_adc_dev_t *adc, hosal_adc_cb_t cb); - -/** - * @brief ADC sampling start - * - * @param[in] adc the ADC interface - * @param[in] data adc data buffer - * @param[in] size data buffer size aligned with resolution (until the next power of two) - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_adc_start(hosal_adc_dev_t *adc, void *data, uint32_t size); - -/** - * @brief ADC sampling stop - * - * @param[in] adc the ADC interface - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_adc_stop(hosal_adc_dev_t *adc); - -/** - * @brief De-initialises an ADC interface, Turns off an ADC hardware interface - * - * @param[in] adc the interface which should be de-initialised - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_adc_finalize(hosal_adc_dev_t *adc); - -#ifdef __cplusplus -} -#endif - -#endif /* __HOSAL_ADC_H_ */ - -/* end of file */ diff --git a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_dac.h b/bsp/bl808/m0/libraries/platform/hosal/include/hosal_dac.h deleted file mode 100644 index e5e9e6213e..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_dac.h +++ /dev/null @@ -1,187 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __HOSAL_DAC_H_ -#define __HOSAL_DAC_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include "hosal_dma.h" - -/** @addtogroup hosal_dac DAC - * HOSAL DAC API - * - * @{ - */ - -/** - * @brief hosal dac callback - * - * @param[in] arg Set the custom parameters specified when the callback function is set - * - */ -typedef void (*hosal_dac_cb_t)(void *arg); - -/** - * @brief This struct define dac config args - */ -typedef struct { - uint8_t dma_enable; /**< @brief 1: use dma, 0: no dma */ - uint32_t pin; /**< @brief dac pin */ - uint32_t freq; /**< @brief dac freq */ -} hosal_dac_config_t; - -/** - * @brief This struct define dac device type - */ -typedef struct { - uint8_t port; /**< @brief dac id */ - hosal_dac_config_t config; /**< @brief dac config */ - hosal_dac_cb_t cb; /**< @brief dma callback */ - hosal_dma_chan_t dma_chan; /**< @brief dac dma channel */ - void *arg; /**< @brief arg data */ - void *priv; /**< @brief priv data */ -} hosal_dac_dev_t; - -/** - * @brief Initialises an dac interface - * - * @param[in] dac the interface which should be initialised - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_dac_init(hosal_dac_dev_t *dac); - -/** - * @brief De-initialises an dac interface, Turns off an dac hardware interface - * - * @param[in] dac the interface which should be de-initialised - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_dac_finalize(hosal_dac_dev_t *dac); - -/** - * @brief Start output dac （no DMA mode） - * - * @param[in] dac the interface which should be started - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_dac_start(hosal_dac_dev_t *dac); - -/** - * @brief Stop output dac - * - * @param[in] dac the interface which should be stopped - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_dac_stop(hosal_dac_dev_t *dac); - -/** - * @brief Output a value to an dac interface - * - * @param[in] dac the interface to set value - * - * @param[in] data the value to output, output unit: μV - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_dac_set_value(hosal_dac_dev_t *dac, uint32_t data); - -/** - * @brief Returns the last data output value of the selected dac channel - * - * @param[in] dac the interface to get value - * - * @return dac output value, output unit: μV - */ -int hosal_dac_get_value(hosal_dac_dev_t *dac); - -/** - * @brief DAC cb register - * - * @param [in] dac the DAC interface - * @param [in] callback callback handler - * @param [in] arg callback arg - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_dac_dma_cb_reg(hosal_dac_dev_t *dac, hosal_dac_cb_t callback, void *arg); - -/** - * @brief DAC use DMA mode - * - * @param[in] adc the DAC interface - * @param[in] data dac data buffer - * @param[in] size data buffer size - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_dac_dma_start(hosal_dac_dev_t *dac, uint32_t *data, uint32_t size); - -/** - * @brief Stop output dac - * - * @param[in] dac the interface which should be stopped - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_dac_dma_stop(hosal_dac_dev_t *dac); - -#ifdef __cplusplus -} -#endif - -#endif /* __HOSAL_DAC_H_ */ - -/* end of file */ - - diff --git a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_dma.h b/bsp/bl808/m0/libraries/platform/hosal/include/hosal_dma.h deleted file mode 100644 index 277154b3e1..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_dma.h +++ /dev/null @@ -1,152 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __HOSAL_DMA_H__ -#define __HOSAL_DMA_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @addtogroup hosal_dma DMA - * HOSAL DMA API - * - * @{ - */ - -#include -#include - -/** - * @brief DMA irq callback function flag - */ -#define HOSAL_DMA_INT_TRANS_COMPLETE 0 -#define HOSAL_DMA_INT_TRANS_ERROR 1 - -/** - * @brief DMA irq callback function - */ -typedef void (*hosal_dma_irq_t)(void *p_arg, uint32_t flag); - -/** - * @brief DMA channel describe - */ -struct hosal_dma_chan { - uint8_t used; - hosal_dma_irq_t callback; - void *p_arg; -}; - -/** - * @brief DMA device type - */ -typedef struct hosal_dma_dev { - int max_chans; - struct hosal_dma_chan *used_chan; - void *priv; -} hosal_dma_dev_t; - -/** - * @brief DMA channel - */ -typedef int hosal_dma_chan_t; - -/** - * @brief Initialises a DMA interface - * - * @return 0 : on success, EIO : if an error occurred with any step - */ -int hosal_dma_init(void); - -/** - * @brief Request a DMA channel - * - * @param[in] flag : DMA CHAN REQUEST FLAG - * - * @return < 0 : an error occurred with any step, otherwise is DMA channel number - */ -hosal_dma_chan_t hosal_dma_chan_request(int flag); - -/** - * @brief Release a DMA channel - * - * @param[in] chan DMA channel number - * - * @return 0 : on success, EIO : if an error occurred with any step - */ -int hosal_dma_chan_release(hosal_dma_chan_t chan); - -/** - * @brief DMA channel trans start - * - * @param[in] chan DMA channel number - * - * @return 0 : on success, EIO : if an error occurred with any step - */ -int hosal_dma_chan_start(hosal_dma_chan_t chan); - -/** - * @brief DMA channel trans stop - * - * @param[in] chan DMA channel number - * - * @return 0 : on success, EIO : if an error occurred with any step - */ -int hosal_dma_chan_stop(hosal_dma_chan_t chan); - -/** - * @brief DMA irq callback set - * - * @param[in] chan : DMA channel number - * @param[in] pfn : callback function - * @param[in] arg : callback function parameter - * - * @return 0 : on success, EIO : if an error occurred with any step - */ -int hosal_dma_irq_callback_set(hosal_dma_chan_t chan, hosal_dma_irq_t pfn, void *p_arg); - -/** - * @brief Deinitialises a DMA interface - * - * @param[in] DMA the interface which should be deinitialised - * - * @return 0 : on success, EIO : if an error occurred with any step - */ -int hosal_dma_finalize(void); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* __HOSAL_DMA_H__ */ - -/* end of file */ diff --git a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_efuse.h b/bsp/bl808/m0/libraries/platform/hosal/include/hosal_efuse.h deleted file mode 100644 index 863e67c260..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_efuse.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __HOSAL_EFUSE_H__ -#define __HOSAL_EFUSE_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Read data from efuse - * - * @param[in] addr efuse address - * @param[in] data store data - * @param[in] len data length - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_efuse_read(uint32_t addr, uint32_t *data, uint32_t len); - -/** - * @brief Write data to efuse - * - * @param[in] addr efuse address - * @param[in] data store data - * @param[in] len data length - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_efuse_write(uint32_t addr, uint32_t *data, uint32_t len); - -#ifdef __cplusplus -} -#endif - -#endif /* __HOSAL_EFUSE_H__ */ - -/* end of file */ diff --git a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_flash.h b/bsp/bl808/m0/libraries/platform/hosal/include/hosal_flash.h deleted file mode 100644 index 2de9049123..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_flash.h +++ /dev/null @@ -1,229 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __HOSAL_FLASH_H__ -#define __HOSAL_FLASH_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @addtogroup hosal_flash FLASH - * HOSAL FLASH API - * - * @{ - */ - -#include - -#define HOSAL_FLASH_FLAG_ADDR_0 0 /**< @brief Open flash prtition address 0 in prtition table */ - -#define HOSAL_FLASH_FLAG_ADDR_1 (1 << 0) /**< @brief Open flash prtition address 1 in prtition table */ - -/** - * Open the partition table and use the bus physical address of flash. - * (If it is not set, the offset address set in the partition table is used by default.) - */ -#define HOSAL_FLASH_FLAG_BUSADDR (1 << 1) - -/** - * @brief Hal flash partition device - */ -typedef struct hosal_flash_dev { - void *flash_dev; /**< @brief flash device */ -} hosal_flash_dev_t; - -/** - * @brief Hal flash partition manage struct - */ -typedef struct { - const char *partition_description; /**< @brief name */ - uint32_t partition_start_addr; /**< @brief start addr */ - uint32_t partition_length; /**< @brief length */ - uint32_t partition_options; /**< @brief options */ -} hosal_logic_partition_t; - -/** - * @brief Open a flash partition device - * - * @param[in] name flash partition name - * @param[in] flags flash flags - * - HOSAL_FLASH_FLAG_ADDR_0 - * - HOSAL_FLASH_FLAG_ADDR_1 - * - HOSAL_FLASH_FLAG_BUSADDR - * - * @return - * - NULL flash open error - * - otherwise is flash partition device - */ -hosal_flash_dev_t *hosal_flash_open(const char *name, unsigned int flags); - -/** - * @brief Get the information of the specified flash area - * - * @param[in] p_dev The target flash logical partition device - * @param[out] partition The buffer to store partition info - * - * @return - * - 0 On success - * - otherwise is error - */ -int hosal_flash_info_get(hosal_flash_dev_t *p_dev, hosal_logic_partition_t *partition); - -/** - * @brief Erase an area on a Flash logical partition - * - * @note Erase on an address will erase all data on a sector that the - * address is belonged to, this function does not save data that - * beyond the address area but in the affected sector, the data - * will be lost. - * - * @param[in] p_dev The target flash logical partition which should be erased - * @param[in] off_set Start address of the erased flash area - * @param[in] size Size of the erased flash area - * - * @return - * - 0 On success - * - otherwise is error - */ -int hosal_flash_erase(hosal_flash_dev_t *p_dev, uint32_t off_set, uint32_t size); - -/** - * @brief Write data to an area on a flash logical partition without erase - * - * @param[in] p_dev The target flash logical partition which should be read which should be written - * @param[in/out] off_set Point to the start address that the data is written to, and - * point to the last unwritten address after this function is - * returned, so you can call this function serval times without - * update this start address. - * @param[in] in_buf point to the data buffer that will be written to flash - * @param[in] in_buf_size The size of the buffer - * - * @return - * - 0 On success - * - otherwise is error - */ -int hosal_flash_write(hosal_flash_dev_t *p_dev, uint32_t *off_set, - const void *in_buf, uint32_t in_buf_size); - -/** - * @brief Write data to an area on a flash logical partition with erase first - * - * @param[in] p_dev The target flash logical partition which should be read which should be written - * @param[in/out] off_set Point to the start address that the data is written to, and - * point to the last unwritten address after this function is - * returned, so you can call this function serval times without - * update this start address. - * @param[in] in_buf point to the data buffer that will be written to flash - * @param[in] in_buf_size The length of the buffer - * - * @return - * - 0 On success - * - otherwise is error - */ -int hosal_flash_erase_write(hosal_flash_dev_t *p_dev, uint32_t *off_set, - const void *in_buf, uint32_t in_buf_size); - -/** - * @brief Read data from an area on a Flash to data buffer in RAM - * - * @param[in] p_dev The target flash logical partition which should be read - * @param[in/out] off_set Point to the start address that the data is read, and - * point to the last unread address after this function is - * returned, so you can call this function serval times without - * update this start address. - * @param[in] out_buf Point to the data buffer that stores the data read from flash - * @param[in] out_buf_size The length of the buffer - * - * @return - * - 0 On success - * - otherwise is error - */ -int hosal_flash_read(hosal_flash_dev_t *p_dev, uint32_t *off_set, - void *out_buf, uint32_t out_buf_size); - -/** - * @brief Close a flash partition device - * - * @param[in] p_dev flash partition device - * - * @return - * - 0 On success - * - otherwise is error - */ -int hosal_flash_close(hosal_flash_dev_t *p_dev); - -/** - * @brief Read data from a row address on a Flash to data buffer in RAM - * - * @param[in] buffer Point to the data buffer that stores the data read from flash - * @param[in] address Address on flash to read from - * @param[in] length Length (in bytes) of data to read - * - * @return - * - 0 On success - * - otherwise is error - */ -int hosal_flash_raw_read(void *buffer, uint32_t address, uint32_t length); - -/** - * @brief Write data to a row address on a Flash - * - * @param[in] buffer Point to the data buffer that will be written to flash - * @param[in] address Address on flash to write to - * @param[in] length Length (in bytes) of data to write - * - * @return - * - 0 On success - * - otherwise is error - */ -int hosal_flash_raw_write(void *buffer, uint32_t address, uint32_t length); - -/** - * @brief Erase a region of the flash - * - * @param[in] start_addr Address to start erasing flash. - * @param[in] length Length of region to erase. - * - * @return - * - 0 On success - * - otherwise is error - */ -int hosal_flash_raw_erase(uint32_t start_addr, uint32_t length); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* __HOSAL_FLASH_H__ */ - -/* end of file */ diff --git a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_gpio.h b/bsp/bl808/m0/libraries/platform/hosal/include/hosal_gpio.h deleted file mode 100644 index c2f8f42a52..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_gpio.h +++ /dev/null @@ -1,186 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __HOSAL_GPIO_H_ -#define __HOSAL_GPIO_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/** @addtogroup hosal_gpio GPIO - * HOSAL GPIO API - * - * @{ - */ - -/** - * @brief gpio config struct - */ -typedef enum { - ANALOG_MODE, /**< @brief Used as a function pin, input and output analog */ - INPUT_PULL_UP, /**< @brief Input with an internal pull-up resistor - use with devices that actively drive the signal low - e.g. button connected to ground */ - INPUT_PULL_DOWN, /**< @brief Input with an internal pull-down resistor - use with devices that actively drive the signal high - e.g. button connected to a power rail */ - INPUT_HIGH_IMPEDANCE, /**< @brief Input - must always be driven, either actively or by an external pullup resistor */ - OUTPUT_PUSH_PULL, /**< @brief Output actively driven high and actively driven low - must not be connected to other active outputs - e.g. LED output */ - OUTPUT_OPEN_DRAIN_NO_PULL, /**< @brief Output actively driven low but is high-impedance when set high - can be connected to other open-drain/open-collector outputs. Needs an external pull-up resistor */ - OUTPUT_OPEN_DRAIN_PULL_UP, /**< @brief Output actively driven low and is pulled high with an internal resistor when set high - can be connected to other open-drain/open-collector outputs. */ - OUTPUT_OPEN_DRAIN_AF, /**< @brief Alternate Function Open Drain Mode. */ - OUTPUT_PUSH_PULL_AF, /**< @brief Alternate Function Push Pull Mode. */ -} hosal_gpio_config_t; - -/** - * @brief GPIO interrupt trigger - */ -typedef enum { - HOSAL_IRQ_TRIG_NEG_PULSE, /**< @brief GPIO negedge pulse trigger interrupt */ - HOSAL_IRQ_TRIG_POS_PULSE, /**< @brief GPIO posedge pulse trigger interrupt */ - HOSAL_IRQ_TRIG_NEG_LEVEL, /**< @brief GPIO negedge level trigger interrupt (32k 3T)*/ - HOSAL_IRQ_TRIG_POS_LEVEL, /**< @brief GPIO posedge level trigger interrupt (32k 3T)*/ -} hosal_gpio_irq_trigger_t; - -/** - * @brief GPIO interrupt callback handler - * - *@param[in] parg ：Set the custom parameters specified - */ -typedef void (*hosal_gpio_irq_handler_t)(void *arg); - -/** - * @brief hosal gpio ctx, use for multi gpio irq - */ -typedef struct hosal_gpio_ctx { - struct hosal_gpio_ctx *next; - hosal_gpio_irq_handler_t handle; - void *arg; - uint8_t pin; - uint8_t intCtrlMod; - uint8_t intTrigMod; -}hosal_gpio_ctx_t; - -/** - * @brief GPIO dev struct - */ -typedef struct { - uint8_t port; /**< @brief gpio port */ - hosal_gpio_config_t config; /**< @brief gpio config */ - void *priv; /**< @brief priv data */ -} hosal_gpio_dev_t; - -/** - * @brief Initialises a GPIO pin - * - * @note Prepares a GPIO pin for use. - * - * @param[in] gpio the gpio pin which should be initialised - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_gpio_init(hosal_gpio_dev_t *gpio); - -/** - * @brief Set GPIO output high or low - * - * @note Using this function on a gpio pin which is set to input mode is undefined. - * - * @param[in] gpio the gpio pin which should be set - * @param[in] value 0 : output low | >0 : output high - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_gpio_output_set(hosal_gpio_dev_t *gpio, uint8_t value); - -/** - * @brief Get the state of an input GPIO pin. Using this function on a - * gpio pin which is set to output mode will return an undefined value. - * - * @param[in] gpio the gpio pin which should be read - * @param[out] value gpio value - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_gpio_input_get(hosal_gpio_dev_t *gpio, uint8_t *value); - -/** - * @brief Enables an interrupt trigger for an input GPIO pin. - * Using this function on a gpio pin which is set to - * output mode is undefined. - * - * @param[in] gpio the gpio pin which will provide the interrupt trigger - * @param[in] trigger the type of trigger (rising/falling edge or both) - * @param[in] handler a function pointer to the interrupt handler - * @param[in] arg an argument that will be passed to the interrupt handler - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_gpio_irq_set(hosal_gpio_dev_t *gpio, hosal_gpio_irq_trigger_t trigger_type, hosal_gpio_irq_handler_t handler, void *arg); - -/** - * @brief Clear an interrupt status for an input GPIO pin. - * Using this function on a gpio pin which has generated a interrupt. - * - * @param[in] gpio the gpio pin which provided the interrupt trigger - * @param[in] mask 0 : mask | 1 : umask - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_gpio_irq_mask(hosal_gpio_dev_t *gpio, uint8_t mask); - -/** - * @brief Set a GPIO pin in default state. - * - * @param[in] gpio the gpio pin which should be deinitialised - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_gpio_finalize(hosal_gpio_dev_t *gpio); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* HAL_GPIO_H */ - diff --git a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_i2c.h b/bsp/bl808/m0/libraries/platform/hosal/include/hosal_i2c.h deleted file mode 100644 index c3b1de8bec..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_i2c.h +++ /dev/null @@ -1,212 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __HOSAL_I2C_H_ -#define __HOSAL_I2C_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @addtogroup hosal_i2c I2C - * HOSAL I2C API - * - * @{ - */ - -#include - -#define HOSAL_WAIT_FOREVER 0xFFFFFFFFU /**< @brief i2c wait time */ - -#define HOSAL_I2C_MODE_MASTER 1 /**< @brief i2c communication is master mode */ -#define HOSAL_I2C_MODE_SLAVE 2 /**< @brief i2c communication is slave mode */ - -#define HOSAL_I2C_MEM_ADDR_SIZE_8BIT 1 /**< @brief i2c memory address size 8bit */ -#define HOSAL_I2C_MEM_ADDR_SIZE_16BIT 2 /**< @brief i2c memory address size 16bit */ -#define HOSAL_I2C_MEM_ADDR_SIZE_24BIT 3 /**< @brief i2c memory address size 24bit */ -#define HOSAL_I2C_MEM_ADDR_SIZE_32BIT 4 /**< @brief i2c memory address size 32bit */ - -#define HOSAL_I2C_ADDRESS_WIDTH_7BIT 0 /**< @brief 7 bit mode */ -#define HOSAL_I2C_ADDRESS_WIDTH_10BIT 1 /**< @brief 10 bit mode */ - -/** - * @brief I2C configuration - */ -typedef struct { - uint32_t address_width; /**< @brief Addressing mode: 7 bit or 10 bit */ - uint32_t freq; /**< @brief CLK freq */ - uint8_t scl; /**< @brief i2c clk pin */ - uint8_t sda; /**< @brief i2c data pin */ - uint8_t mode; /**< @brief master or slave mode */ -} hosal_i2c_config_t; - -/** - * @brief I2C device type - */ -typedef struct { - uint8_t port; /**< @brief i2c port */ - hosal_i2c_config_t config; /**< @brief i2c config */ - void *priv; /**< @brief priv data */ -} hosal_i2c_dev_t; - -/** - * @brief Initialises an I2C interface - * - * @param[in] i2c the device for which the i2c port should be initialised - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_i2c_init(hosal_i2c_dev_t *i2c); - -/** - * @brief I2c master send - * - * @param[in] i2c the i2c device - * @param[in] dev_addr device address - * @param[in] data i2c send data - * @param[in] size i2c send data size - * @param[in] timeout timeout in milisecond, set this value to HAL_WAIT_FOREVER - * if you want to wait forever - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_i2c_master_send(hosal_i2c_dev_t *i2c, uint16_t dev_addr, const uint8_t *data, - uint16_t size, uint32_t timeout); - -/** - * @brief I2c master recv - * - * @param[in] i2c the i2c device - * @param[in] dev_addr device address - * @param[out] data i2c receive data - * @param[in] size i2c receive data size - * @param[in] timeout timeout in milisecond, set this value to HAL_WAIT_FOREVER - * if you want to wait forever - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_i2c_master_recv(hosal_i2c_dev_t *i2c, uint16_t dev_addr, uint8_t *data, - uint16_t size, uint32_t timeout); -/** - * @brief I2c slave send - * - * @param[in] i2c the i2c device - * @param[in] data i2c slave send data - * @param[in] size i2c slave send data size - * @param[in] timeout timeout in milisecond, set this value to HAL_WAIT_FOREVER - * if you want to wait forever - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_i2c_slave_send(hosal_i2c_dev_t *i2c, const uint8_t *data, uint16_t size, uint32_t timeout); - -/** - * @brief I2c slave receive - * - * @param[in] i2c tthe i2c device - * @param[out] data i2c slave receive data - * @param[in] size i2c slave receive data size - * @param[in] timeout timeout in milisecond, set this value to HAL_WAIT_FOREVER - * if you want to wait forever - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_i2c_slave_recv(hosal_i2c_dev_t *i2c, uint8_t *data, uint16_t size, uint32_t timeout); - -/** - * @brief I2c mem write - * - * @param[in] i2c the i2c device - * @param[in] dev_addr device address - * @param[in] mem_addr mem address - * @param[in] mem_addr_size mem address - * @param[in] data i2c master send data - * @param[in] size i2c master send data size - * @param[in] timeout timeout in milisecond, set this value to HAL_WAIT_FOREVER - * if you want to wait forever - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_i2c_mem_write(hosal_i2c_dev_t *i2c, uint16_t dev_addr, uint32_t mem_addr, - uint16_t mem_addr_size, const uint8_t *data, uint16_t size, - uint32_t timeout); - -/** - * @brief I2c master mem read - * - * @param[in] i2c the i2c device - * @param[in] dev_addr device address - * @param[in] mem_addr mem address - * @param[in] mem_addr_size mem address - * @param[out] data i2c master send data - * @param[in] size i2c master send data size - * @param[in] timeout timeout in milisecond, set this value to HAL_WAIT_FOREVER - * if you want to wait forever - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_i2c_mem_read(hosal_i2c_dev_t *i2c, uint16_t dev_addr, uint32_t mem_addr, - uint16_t mem_addr_size, uint8_t *data, uint16_t size, - uint32_t timeout); - -/** - * @brief Deinitialises an I2C device - * - * @param[in] i2c the i2c device - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_i2c_finalize(hosal_i2c_dev_t *i2c); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* __HOSAL_I2C_H_ */ - -/* end of file */ diff --git a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_pwm.h b/bsp/bl808/m0/libraries/platform/hosal/include/hosal_pwm.h deleted file mode 100644 index f40a699561..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_pwm.h +++ /dev/null @@ -1,175 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __HOSAL_PWM_H__ -#define __HOSAL_PWM_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @addtogroup hosal_pwm PWM - * HOSAL PWM API - * - * @{ - */ - -#include -/** - * @brief pwm config struct - * - */ -typedef struct { - uint8_t pin; /**< pwm pin */ - uint32_t duty_cycle; /**< the pwm duty_cycle 0 ~ 10000(0 ~ 100%)*/ - uint32_t freq; /**< the pwm freq,range is between 0 and 40M */ -} hosal_pwm_config_t; - -/** - * @brief pwm dev struct - * - */ -typedef struct { - uint8_t port; /**< pwm port */ - hosal_pwm_config_t config; /**< pwm config */ - void *priv; /**< priv data */ -} hosal_pwm_dev_t; - -/** - * @brief Initialises a PWM pin - * - * @param[in] pwm the PWM device - * - * @return - * - 0 : success - * - other: fail - */ -int hosal_pwm_init(hosal_pwm_dev_t *pwm); - -/** - * @brief Starts Pulse-Width Modulation signal output on a PWM pin - * - * @param[in] pwm the PWM device - * - * @return - * - 0 : success - * - other : fail - */ -int hosal_pwm_start(hosal_pwm_dev_t *pwm); - -/** - * @brief Stops output on a PWM pin - * - * @param[in] pwm the PWM device - * - * @return - * - 0 : success - * - other: fail - */ -int hosal_pwm_stop(hosal_pwm_dev_t *pwm); - -/** - * @change the para of pwm - * - * @param[in] pwm the PWM device - * @param[in] para the para of pwm - * - * @return - * - 0 : success - * - other: fail - */ -int hosal_pwm_para_chg(hosal_pwm_dev_t *pwm, hosal_pwm_config_t para); - -/** - * @brief update PWM frequency - * - * @param[in] pwm the PWM device - * @param[in] freq the PWM frequency (0~40M under limited duty) - * - * @return - * - 0 : success - * - other: fail - */ -int hosal_pwm_freq_set(hosal_pwm_dev_t *pwm, uint32_t freq); - -/** - * @brief get PWM frequency - * - * @param[in] pwm the PWM device - * @param[out] p_freq the pointer to memory frequency - * - * @return - * - 0 : success - * - other: fail - */ -int hosal_pwm_freq_get(hosal_pwm_dev_t *pwm, uint32_t *p_freq); - -/** - * @brief set PWM duty - * - * @param[in] pwm the PWM device - * @param[in] duty the PWM duty (original duty * 100) - * - * @return - * - 0 : success - * - other: fail - */ -int hosal_pwm_duty_set(hosal_pwm_dev_t *pwm, uint32_t duty); - -/** - * @brief get PWM duty - * - * @param[in] pwm the PWM device - * @param[out] p_duty the pointer to memory duty(original duty * 100) - * - * @return - * - 0 : success - * - other: fail - */ -int hosal_pwm_duty_get(hosal_pwm_dev_t *pwm, uint32_t *p_duty); - -/** - * @brief De-initialises an PWM interface, Turns off an PWM hardware interface - * - * @param[in] pwm the interface which should be de-initialised - * - * @return - * - 0 : success - * - other: fail - */ -int hosal_pwm_finalize(hosal_pwm_dev_t *pwm); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* HAL_PWM_H */ - diff --git a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_rng.h b/bsp/bl808/m0/libraries/platform/hosal/include/hosal_rng.h deleted file mode 100644 index 733d1d397c..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_rng.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef HAL_RNG_H -#define HAL_RNG_H - -#ifdef __cplusplus -extern "C" { -#endif - -/** @addtogroup hosal_rng RNG - * HOSAL RNG API - * - * @{ - */ - -#include - -/** - * @brief init rng - * - * @return - * - 0 : success - * - other: fail - */ -int hosal_rng_init(void); - -/** - * @brief Fill in a memory buffer with random data - * - * @param[out] buf Point to a valid memory buffer, this function will fill - * in this memory with random numbers after executed - * @param[in] bytes Length of the memory buffer (bytes) - * - * @return - * - 0 : success - * - other: fail - */ -int hosal_random_num_read(void *buf, uint32_t bytes); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* HAL_RNG_H */ - diff --git a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_rtc.h b/bsp/bl808/m0/libraries/platform/hosal/include/hosal_rtc.h deleted file mode 100644 index dc0a3082e7..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_rtc.h +++ /dev/null @@ -1,146 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __HAL_RTC_H__ -#define __HAL_RTC_H__ - -/** @addtogroup hal_rtc RTC - * rtc hal API. - * - * @{ - */ - -#include - -#define HOSAL_RTC_FORMAT_DEC 1 /**< RTC DEC format */ -#define HOSAL_RTC_FORMAT_BCD 2 /**< RTC BCD format */ - -/** - * @brief rtc config struct - */ -typedef struct { - uint8_t format; /**< time formart DEC or BCD */ -} hosal_rtc_config_t; - -/** - * @brief rtc dev struct - */ -typedef struct { - uint8_t port; /**< rtc port */ - hosal_rtc_config_t config; /**< rtc config */ - void *priv; /**< priv data */ -} hosal_rtc_dev_t; - -/** - * @brief RTC time struct - */ -typedef struct { - uint8_t sec; /**< DEC format:value range from 0 to 59, BCD format:value range from 0x00 to 0x59 */ - uint8_t min; /**< DEC format:value range from 0 to 59, BCD format:value range from 0x00 to 0x59 */ - uint8_t hr; /**< DEC format:value range from 0 to 23, BCD format:value range from 0x00 to 0x23 */ - uint8_t date; /**< DEC format:value range from 1 to 31, BCD format:value range from 0x01 to 0x31 */ - uint8_t month; /**< DEC format:value range from 1 to 12, BCD format:value range from 0x01 to 0x12 */ - uint16_t year; /**< DEC format:value range from 0 to 9999, BCD format:value range from 0x0000 to 0x9999 */ -} hosal_rtc_time_t; - -/** - * @brief This function will initialize the on board CPU real time clock - * - * - * @param[in] rtc rtc device - * - * @return - * - 0 : success - * - other : fail - */ -int hosal_rtc_init(hosal_rtc_dev_t *rtc); - -/** - * @brief This function will set MCU RTC time to a new value. - * - * @param[in] rtc rtc device - * @param[in] time pointer to a time structure - * - * @return - * - 0 : success - * - other : fail - */ -int hosal_rtc_set_time(hosal_rtc_dev_t *rtc, const hosal_rtc_time_t *time); - -/** - * @brief This function will return the value of time read from the on board CPU real time clock. - * - * @param[in] rtc rtc device - * @param[out] time pointer to a time structure - * - * @return - * - 0 : success - * - other : fail - */ -int hosal_rtc_get_time(hosal_rtc_dev_t *rtc, hosal_rtc_time_t *time); - -/** - * @brief This function will set MCU RTC time to a new value. - * - * @param[in] rtc rtc device - * @param[in] time_stamp new time value - * - * @return - * - 0 : success - * - other : fail - */ -int hosal_rtc_set_count(hosal_rtc_dev_t *rtc, uint64_t *time_stamp); - -/** - * @brief This function will return the value of time read from the on board CPU real time clock. - * - * @param[in] rtc rtc device - * @param[in] time_stamp new time value - * - * @return - * - 0 : success - * - other : fail - */ -int hosal_rtc_get_count(hosal_rtc_dev_t *rtc, uint64_t *time_stamp); - -/** - * @brief De-initialises an RTC interface, Turns off an RTC hardware interface - * - * @param[in] RTC the interface which should be de-initialised - * - * @return - * - 0 : success - * - other : fail - */ -int hosal_rtc_finalize(hosal_rtc_dev_t *rtc); - -/** @} */ - -#endif /* HAL_RTC_H */ - diff --git a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_spi.h b/bsp/bl808/m0/libraries/platform/hosal/include/hosal_spi.h deleted file mode 100644 index ec259046f0..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_spi.h +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef HAL_SPI_H -#define HAL_SPI_H - -#ifdef __cplusplus -extern "C" { -#endif - -/** @addtogroup hosal_spi SPI - * HOSAL SPI API - * - * @{ - */ - -#include -#include -#include - -#define HOSAL_SPI_MODE_MASTER 0 /**< spi communication is master mode */ -#define HOSAL_SPI_MODE_SLAVE 1 /**< spi communication is slave mode */ -#define HOSAL_WAIT_FOREVER 0xFFFFFFFFU /**< DMA transmission timeout */ - -typedef void (*hosal_spi_irq_t)(void *parg); /**< spi irq callback function */ - -/** - * @brief Define spi config args - */ -typedef struct { - uint8_t mode; /**< spi communication mode */ - uint8_t dma_enable; /**< enable dma tansmission or not */ - uint8_t polar_phase; /**< spi polar and phase */ - uint32_t freq; /**< communication frequency Hz */ - uint8_t pin_clk; /**< spi clk pin */ - uint8_t pin_mosi; /**< spi mosi pin */ - uint8_t pin_miso; /**< spi miso pin */ -} hosal_spi_config_t; - -/** - * @brief Define spi dev handle - */ -typedef struct { - uint8_t port; /**< spi port */ - hosal_spi_config_t config; /**< spi config */ - hosal_spi_irq_t cb; /**< spi interrupt callback */ - void *p_arg; /**< arg pass to callback */ - void *priv; /**< priv data */ -} hosal_spi_dev_t; - -/** - * @brief Initialises the SPI interface for a given SPI device - * - * @param[in] spi the spi device - * - * @return - * - 0 : on success - * - other : error - */ -int hosal_spi_init(hosal_spi_dev_t *spi); - -/** - * @brief Spi send - * - * @param[in] spi the spi device - * @param[in] data spi send data - * @param[in] size spi send data size - * @param[in] timeout timeout in milisecond, set this value to HAL_WAIT_FOREVER - * if you want to wait forever - * - * @return - * - 0 : on success - * - other : error - */ -int hosal_spi_send(hosal_spi_dev_t *spi, const uint8_t *data, uint32_t size, uint32_t timeout); - -/** - * @brief Spi recv - * - * @param[in] spi the spi device - * @param[out] data spi recv data - * @param[in] size spi recv data size - * @param[in] timeout timeout in milisecond, set this value to HAL_WAIT_FOREVER - * if you want to wait forever - * - * @return - * - 0 : success - * - other : error - */ -int hosal_spi_recv(hosal_spi_dev_t *spi, uint8_t *data, uint16_t size, uint32_t timeout); - -/** - * @brief spi send data and recv - * - * @param[in] spi the spi device - * @param[in] tx_data spi send data - * @param[out] rx_data spi recv data - * @param[in] size spi data to be sent and recived - * @param[in] timeout timeout in milisecond, set this value to HAL_WAIT_FOREVER - * if you want to wait forever - * - * @return - * - 0 : success - * - other : error - */ -int hosal_spi_send_recv(hosal_spi_dev_t *spi, uint8_t *tx_data, uint8_t *rx_data, uint16_t size, uint32_t timeout); - -/* - * @brief set spi irq callback - * - * @param spi the spi device - * @param pfn callback function - * @param p_arg callback function parameter - * - * @return - * - 0 : success - * - othe : error - */ -int hosal_spi_irq_callback_set(hosal_spi_dev_t *spi, hosal_spi_irq_t pfn, void *p_arg); - -/** - * @brief spi software set cs pin high/low only for master device - * - * @param[in] pin cs pin - * @param[in] value 0 or 1 - * - * @return - * - 0 : success - * - other : error - */ -int hosal_spi_set_cs(uint8_t pin, uint8_t value); - -/** - * @brief De-initialises a SPI interface - * - * - * @param[in] spi the SPI device to be de-initialised - * - * @return - * - 0 : success - * - other : error - */ -int hosal_spi_finalize(hosal_spi_dev_t *spi); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* HAL_SPI_H */ - diff --git a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_timer.h b/bsp/bl808/m0/libraries/platform/hosal/include/hosal_timer.h deleted file mode 100644 index 20a1a9b66e..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_timer.h +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef HOSAL_TIMER_H -#define HOSAL_TIMER_H - -#ifdef __cplusplus -extern "C" { -#endif - -/** @addtogroup hal_timer TIMER - * timer hal API. - * - * @{ - */ - -#include - -#define TIMER_RELOAD_PERIODIC 1 /**< timer reload automatic */ -#define TIMER_RELOAD_ONCE 2 /**< timer reload once and need to reload manually */ - -typedef void (*hosal_timer_cb_t)(void *arg); /**< Define timer handle function type */ - -/** - * Define timer config args - */ -typedef struct { - uint32_t period; /**< timer period, us */ - uint8_t reload_mode; /**< auto reload or not */ - hosal_timer_cb_t cb; /**< timer handle when expired */ - void *arg; /**< timer handle args */ -} hosal_timer_config_t; - -/** - * Define timer dev handle - */ -typedef struct { - int8_t port; /**< timer port */ - hosal_timer_config_t config; /**< timer config */ - void *priv; /**< priv data */ -} hosal_timer_dev_t; - -/** - * init a hardware timer - * - * @param[in] tim timer device - * - * @return - * - 0 : success - * - other :error - */ -int hosal_timer_init(hosal_timer_dev_t *tim); - -/** - * start a hardware timer - * - * @param[in] tim timer device - * - * @return - * - 0 : success - * - other : error - */ -int hosal_timer_start(hosal_timer_dev_t *tim); - -/** - * stop a hardware timer - * - * @param[in] tim timer device - * - * @return none - */ -void hosal_timer_stop(hosal_timer_dev_t *tim); - -/** - * De-initialises an TIMER interface, Turns off an TIMER hardware interface - * - * @param[in] tim timer device - * - * @return - * - 0 : success - * - other : error - */ -int hosal_timer_finalize(hosal_timer_dev_t *tim); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* HAL_TIMER_H */ - diff --git a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_uart.h b/bsp/bl808/m0/libraries/platform/hosal/include/hosal_uart.h deleted file mode 100644 index 0698406b89..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_uart.h +++ /dev/null @@ -1,356 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __HOSAL_UART_H__ -#define __HOSAL_UART_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @addtogroup hosal_uart UART - * HOSAL UART API - * - * @{ - */ - -#include -#include -#include "hosal_dma.h" - -#define HOSAL_UART_AUTOBAUD_0X55 1 /**< @brief UART auto baudrate detection using codeword 0x55 */ -#define HOSAL_UART_AUTOBAUD_STARTBIT 2 /**< @brief UART auto baudrate detection using start bit */ - -#define HOSAL_UART_TX_CALLBACK 1 /**< @brief UART tx idle interrupt callback */ -#define HOSAL_UART_RX_CALLBACK 2 /**< @brief UART rx complete callback */ -#define HOSAL_UART_TX_DMA_CALLBACK 3 /**< @brief UART tx DMA trans complete callback */ -#define HOSAL_UART_RX_DMA_CALLBACK 4 /**< @brief UART rx DMA trans complete callback */ - -#define HOSAL_UART_BAUD_SET 1 /**< @brief UART baud set */ -#define HOSAL_UART_BAUD_GET 2 /**< @brief UART baud get */ -#define HOSAL_UART_DATA_WIDTH_SET 3 /**< @brief UART data width set */ -#define HOSAL_UART_DATA_WIDTH_GET 4 /**< @brief UART data width get */ -#define HOSAL_UART_STOP_BITS_SET 5 /**< @brief UART stop bits set */ -#define HOSAL_UART_STOP_BITS_GET 6 /**< @brief UART stop bits get */ -#define HOSAL_UART_FLOWMODE_SET 7 /**< @brief UART flow mode set */ -#define HOSAL_UART_FLOWSTAT_GET 8 /**< @brief UART flow state get */ -#define HOSAL_UART_PARITY_SET 9 /**< @brief UART flow mode set */ -#define HOSAL_UART_PARITY_GET 10 /**< @brief UART flow state get */ -#define HOSAL_UART_MODE_SET 11 /**< @brief UART mode set */ -#define HOSAL_UART_MODE_GET 12 /**< @brief UART mode get */ -#define HOSAL_UART_FREE_TXFIFO_GET 13 /**< @brief UART free tx fifo get */ -#define HOSAL_UART_FREE_RXFIFO_GET 14 /**< @brief UART free rx fifo get */ -#define HOSAL_UART_FLUSH 15 /**< @brief Wait for the send to complete */ -#define HOSAL_UART_TX_TRIGGER_ON 16 /**< @brief UART TX trigger on */ -#define HOSAL_UART_TX_TRIGGER_OFF 17 /**< @brief UART TX trigger off */ -#define HOSAL_UART_DMA_TX_START 18 /**< @brief UART DMA TX start trans */ -#define HOSAL_UART_DMA_RX_START 19 /**< @brief UART DMA RX start trans */ - -/** - * @brief hosal uart callback - * - * @param[in] p_arg Set the custom parameters specified when the callback function is set - * - * @return - * - 0 : on success - * - EIO : if an error occurred with any step - */ -typedef int (*hosal_uart_callback_t)(void *p_arg); - -/** - * @brief UART data width - */ -typedef enum { - HOSAL_DATA_WIDTH_5BIT, - HOSAL_DATA_WIDTH_6BIT, - HOSAL_DATA_WIDTH_7BIT, - HOSAL_DATA_WIDTH_8BIT, - HOSAL_DATA_WIDTH_9BIT -} hosal_uart_data_width_t; - -/** - * @brief UART stop bits - */ -typedef enum { - HOSAL_STOP_BITS_1 = 1, - HOSAL_STOP_BITS_2 = 3 -} hosal_uart_stop_bits_t; - -/** - * @brief UART flow control - */ -typedef enum { - HOSAL_FLOW_CONTROL_DISABLED, - HOSAL_FLOW_CONTROL_RTS, - HOSAL_FLOW_CONTROL_CTS, - HOSAL_FLOW_CONTROL_CTS_RTS -} hosal_uart_flow_control_t; - -/** - * @brief UART parity - */ -typedef enum { - HOSAL_NO_PARITY, - HOSAL_ODD_PARITY, - HOSAL_EVEN_PARITY -} hosal_uart_parity_t; - -/** - * @brief UART mode - */ -typedef enum { - HOSAL_UART_MODE_POLL, /**< @brief UART poll mode (default mode) */ - HOSAL_UART_MODE_INT_TX, /**< @brief UART TX int mode */ - HOSAL_UART_MODE_INT_RX, /**< @brief UART RX int mode */ - HOSAL_UART_MODE_INT, /**< @brief UART TX and RX int mode */ -} hosal_uart_mode_t; - -/** - * @brief UART DMA configuration - */ -typedef struct { - /** - * @brief UART DMA trans buffer - * When the transmission is TX, the address is the src address - * When the transmission is RX, the address is the dest address - */ - uint8_t *dma_buf; - - uint32_t dma_buf_size; /**< @brief UART DMA trans buffer size */ -} hosal_uart_dma_cfg_t; - -/** - * @brief UART configuration - */ -typedef struct { - uint8_t uart_id; /**< @brief UART id */ - uint8_t tx_pin; /**< @brief UART tx pin */ - uint8_t rx_pin; /**< @brief UART rx pin */ - uint8_t cts_pin; /**< @brief UART cts pin */ - uint8_t rts_pin; /**< @brief UART rts pin */ - uint32_t baud_rate; /**< @brief UART baud rate */ - hosal_uart_data_width_t data_width; /**< @brief UART data width */ - hosal_uart_parity_t parity; /**< @brief UART parity bit */ - hosal_uart_stop_bits_t stop_bits; /**< @brief UART stop btis */ - hosal_uart_flow_control_t flow_control; /**< @brief UART flow control */ - hosal_uart_mode_t mode; /**< @brief UART int or pull mode */ -} hosal_uart_config_t; - -/** - * @brief UART device type - */ -typedef struct { - uint8_t port; /**< @brief UART port */ - hosal_uart_config_t config; /**< @brief UART config */ - hosal_uart_callback_t tx_cb; /**< @brief UART tx callback */ - void *p_txarg; /**< @brief UART tx callback arg */ - hosal_uart_callback_t rx_cb; /**< @brief UART rx callback */ - void *p_rxarg; /**< @brief UART rx callback arg */ - hosal_uart_callback_t txdma_cb; /**< @brief UART tx dma callback */ - void *p_txdma_arg; /**< @brief UART tx dma callback arg */ - hosal_uart_callback_t rxdma_cb; /**< @brief UART rx dma callback */ - void *p_rxdma_arg; /**< @brief UART rx dma callback arg */ - hosal_dma_chan_t dma_tx_chan; /**< @brief UART dma tx channel */ - hosal_dma_chan_t dma_rx_chan; /**< @brief UART dma rx channel */ - void *priv; /**< @brief UART private data */ -} hosal_uart_dev_t; - -/** - * @brief define a UART default config - * - * @param[in] cfg config define - * @param[in] id uart id - * @param[in] tx uart tx pin - * @param[in] rx uart rx pin - * @param[in] baud uart baud - * - */ -#define HOSAL_UART_CFG_DECL(cfg, id, tx, rx, baud) \ - hosal_uart_config_t cfg = { \ - .uart_id = id, \ - .tx_pin = tx, \ - .rx_pin = rx, \ - .cts_pin = 255, \ - .rts_pin = 255, \ - .baud_rate = baud, \ - .data_width = HOSAL_DATA_WIDTH_8BIT, \ - .parity = HOSAL_NO_PARITY, \ - .stop_bits = HOSAL_STOP_BITS_1, \ - .mode = HOSAL_UART_MODE_POLL, \ - }; - -/** - * @brief define a UART device - * - * @param[in] dev uart device - * @param[in] id uart id - * @param[in] tx uart tx pin - * @param[in] rx uart rx pin - * @param[in] baud uart baud - */ -#define HOSAL_UART_DEV_DECL(dev, id, tx, rx, baud) \ - hosal_uart_dev_t dev = { \ - .config = { \ - .uart_id = id, \ - .tx_pin = tx, \ - .rx_pin = rx, \ - .cts_pin = 255, \ - .rts_pin = 255, \ - .baud_rate = baud, \ - .data_width = HOSAL_DATA_WIDTH_8BIT, \ - .parity = HOSAL_NO_PARITY, \ - .stop_bits = HOSAL_STOP_BITS_1, \ - .mode = HOSAL_UART_MODE_POLL, \ - }, \ - }; -/** - * @brief Get auto baudrate on a UART interface - * - * @param[in] uart the UART interface - * @param[in] mode auto baudrate detection mode(codeword 0x55 or start bit) - * - * @return - * - = 0 on success - * - EIO if an error occurred with any step - */ -int hosal_uart_abr_get(hosal_uart_dev_t *uart, uint8_t mode); - -/** - * @brief Initialises a UART interface - * - * @param[in] uart the interface which should be initialised - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_uart_init(hosal_uart_dev_t *uart); - -/** - * @brief Poll transmit data on a UART interface - * - * @param[in] uart the UART interface - * @param[in] txbuf pointer to the start of data - * @param[in] size number of bytes to transmit - * - * @return - * - > 0 on success - * - EIO if an error occurred with any step - */ -int hosal_uart_send(hosal_uart_dev_t *uart, const void *txbuf, uint32_t size); - -/** - * @brief Poll receive data on a UART interface - * - * @param[in] uart the UART interface - * @param[out] rxbuf pointer to the buffer which will store incoming data - * @param[in] expect_size expect number of bytes to receive - * - * @return - * - > 0 number of bytes to receive - * - EIO if an error occurred with any step - */ -int hosal_uart_receive(hosal_uart_dev_t *uart, void *data, uint32_t expect_size); - -/** - * @brief hal uart ioctl - * - * @param[in] uart the UART interface - * @param[in] ctl Control request - * - HOSAL_UART_BAUD_SET : baud set, p_arg is baud - * - HOSAL_UART_BAUD_GET : baud get, p_arg is baud's pointer - * - HOSAL_UART_DATA_WIDTH_SET : set data width，p_arg is hosal_uart_data_width_t - * - HOSAL_UART_DATA_WIDTH_GET : get data width，p_arg is hosal_uart_data_width_t's pointer - * - HOSAL_UART_STOP_BITS_SET : set stop bits, p_arg is hosal_uart_stop_bits_t - * - HOSAL_UART_STOP_BITS_GET : get stop bits, p_arg is hosal_uart_stop_bits_t's pointer - * - HOSAL_UART_PARITY_SET : set parity, p_arg is hosal_uart_parity_t - * - HOSAL_UART_PARITY_GET : get parity, p_arg is hosal_uart_parity_t's pointer - * - HOSAL_UART_MODE_SET : UART mode set, p_arg is hosal_uart_mode_t - * - HOSAL_UART_MODE_GET : UART mode get, p_arg is hosal_uart_mode_t's pointer - * - HOSAL_UART_FLOWMODE_SET : UART flow mode set, p_arg is hosal_uart_flow_control_t - * - HOSAL_UART_FLOWSTAT_GET : UART flow state get, p_arg is hosal_uart_flow_control_t's pointer - * - HOSAL_UART_FREE_TXFIFO_GET : get uart free tx fifo size (bytes) - * - HOSAL_UART_FREE_RXFIFO_GET : get uart free rx fifo size (bytes) - * - HOSAL_UART_FLUSH : Wait for the send to complete - * - HOSAL_UART_TX_TRIGGER_ON : UART TX trigger on - * - HOSAL_UART_TX_TRIGGER_OFF : UART TX trigger off - * - HOSAL_UART_DMA_CONFIG : p_arg is hosal_uart_dma_cfg_t's pointer - * - HOSAL_UART_DMA_TX_START : UART DMA TX start trans p_arg is hosal_uart_dma_cfg_t's pointer - * - HOSAL_UART_DMA_RX_START : UART DMA RX start trans p_arg is hosal_uart_dma_cfg_t's pointer - * - * @param[in,out] p_arg parameter - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_uart_ioctl (hosal_uart_dev_t *uart, int ctl, void *p_arg); - -/** - * @brief hal uart callback set - * - * @param[in] uart the UART interface - * @param[in] callback_type callback type - * - HOSAL_UART_TX_CALLBACK - * - HOSAL_UART_RX_CALLBACK - * - HOSAL_UART_TX_DMA_CALLBACK - * - HOSAL_UART_RX_DMA_CALLBACK - * @param[in] pfn_callback callback function - * @param[in] arg callback function parameter - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_uart_callback_set (hosal_uart_dev_t *uart, - int callback_type, - hosal_uart_callback_t pfn_callback, - void *arg); - -/** - * @brief Deinitialises a UART interface - * - * @param[in] uart the interface which should be deinitialised - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_uart_finalize(hosal_uart_dev_t *uart); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* __HOSAL_UART_H__ */ - -/* end of file */ diff --git a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_wdg.h b/bsp/bl808/m0/libraries/platform/hosal/include/hosal_wdg.h deleted file mode 100644 index 853c321420..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_wdg.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef HAL_WDG_H -#define HAL_WDG_H - -#ifdef __cplusplus -extern "C" { -#endif - -/** @addtogroup hosal_wdg WATCHDOG - * HOSAL WATCHDOG API - * - * @{ - */ - -#include - -/** - * @brief wdg config struct - * - */ -typedef struct { - uint32_t timeout; /*!< Watchdag timeout in ms*/ -} hosal_wdg_config_t; - -/** - * @brief wdg dev struct - * - */ -typedef struct { - uint8_t port; /**< wdg port */ - hosal_wdg_config_t config; /**< wdg config */ - void *priv; /**< priv data */ -} hosal_wdg_dev_t; - -/** - * @brief This function will initialize the on board CPU hardware watch dog - * - * @param[in] wdg the watch dog device - * - * @return - * - 0 : success - * - other: fail - */ -int hosal_wdg_init(hosal_wdg_dev_t *wdg); - -/** - * @brief Reload watchdog counter. - * - * @param[in] wdg the watch dog device - */ -void hosal_wdg_reload(hosal_wdg_dev_t *wdg); - -/** - * @brief This function performs any platform-specific cleanup needed for hardware watch dog. - * - * @param[in] wdg the watch dog device - * - * @return - * - 0 : success - * - other: fail - */ -int hosal_wdg_finalize(hosal_wdg_dev_t *wdg); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* HAL_WDG_H */ - diff --git a/bsp/bl808/m0/libraries/platform/hosal/platform_hal/platform_hal_device.cpp b/bsp/bl808/m0/libraries/platform/hosal/platform_hal/platform_hal_device.cpp deleted file mode 100644 index e36e2b459d..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/platform_hal/platform_hal_device.cpp +++ /dev/null @@ -1,251 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include - -extern "C" void* operator new(size_t size) -{ - /* printf("[C++] new %d\r\n", size); */ - return pvPortMalloc(size); -} - -extern "C" void* operator new[](size_t size) -{ - /* printf("[C++] new[] %d\r\n", size); */ - return pvPortMalloc(size); -} - -extern "C" void operator delete(void* ptr) { - /* printf("[C++] delete %p\r\n", ptr); */ - vPortFree(ptr); -} - -extern "C" void operator delete[](void* ptr) { - /* printf("[C++] delete[] %p\r\n", ptr); */ - vPortFree(ptr); -} - -BLLinkedItem::BLLinkedItem() -{ - this->next = NULL; -} - -BLLinkedItem* BLLinkedItem::attach(class BLLinkedItem &item) -{ - /*assert when next is NOT NULL*/ - if (this->next) { - printf("[ERR] next is NOT NULL. %p -->> %p\r\n", this->next, &item); - return NULL; - } else if (this == &item) { - printf("[ERR] linked to self. %p -->> %p\r\n", this, &item); - return NULL; - } - this->next = &item; - return this; -} - -BLLinkedItem* BLLinkedItem::detach() -{ - BLLinkedItem *tmp; - - tmp = this->next; - this->next = NULL; - - return tmp; -} - -BLLinkedList::BLLinkedList() -{ - this->head = NULL; - this->tail = NULL; -} - -BLLinkedList* BLLinkedList::push(class BLLinkedItem &item) -{ - printf("[BLLinkedList] push %p\r\n", &item); - - if (NULL == this->head) { - printf("new push\r\n"); - this->head = &item; - this->tail = &item; - return this; - } - /*tail should NOT be NULL, assert here if tail is NULL?*/ - printf("continue push\r\n"); - if (NULL == this->tail->attach(item)) { - return NULL; - } - this->tail = &item; - - return this; -} - -BLLinkedItem* BLLinkedList::pop() -{ - BLLinkedItem *item; - - if (NULL == this->head) { - printf("NULL HEAD\r\n"); - return NULL; - } - item = this->head; - this->head = item->detach(); - - printf("[POP] POP %p\r\n", item); - - return item; -} - -BLAesRequest::BLAesRequest() -{ - memset(this->key, 0, sizeof(this->key)); - memset(this->iv, 0, sizeof(this->iv)); - this->src = NULL; - this->dst = NULL; - this->len = 0; - this->first_use = 0; -} - -BLAesRequest::BLAesRequest(uint8_t *key, uint8_t *iv, uint8_t *src, uint8_t *dst, int len) -{ - memcpy(this->key, key, sizeof(this->key)); - if (iv) { - memcpy(this->iv, iv, sizeof(this->iv)); - } - this->src = src; - this->dst = dst; - this->len = len; - this->first_use = 0; -} - -int BLAesRequest::done_pre(int use_encryption) -{ - this->task_handle = xTaskGetCurrentTaskHandle(); - this->done = 0; - this->is_encryption = use_encryption; - - return 0; -} - -int BLAesRequest::done_wait() -{ - while (0 == this->done) { - ulTaskNotifyTake(pdTRUE, portMAX_DELAY); - } - return 0; -} - -int BLAesRequest::done_set() -{ - this->done = 1; - xTaskNotifyGive(this->task_handle); - - return 0; -} - -int BLAesRequest::done_set_auto() -{ - this->done = 1; - //TODO - printf("[C++] [%s] ongoing...\r\n", __PRETTY_FUNCTION__); - - return 0; -} - -int BLAesRequest::done_set_FromISR() -{ - BaseType_t xHigherPriorityTaskWoken; - - this->done = 1; - vTaskNotifyGiveFromISR(this->task_handle, &xHigherPriorityTaskWoken); - portYIELD_FROM_ISR(xHigherPriorityTaskWoken); - - return 0; -} - -int BLAesEngine::encryption(BLAesRequest &req) -{ - printf("%s %p...\r\n", __PRETTY_FUNCTION__, &req); - - /*request prepare*/ - req.done_pre(1); - /*push to queue and trigger if necessary*/ - if (NULL == this->push(req)) { - return -1; - } - this->encryption_trigger(); - /*request wait*/ - req.done_wait(); - - return 0; -} - -void BLAesEngine::encryption_trigger() -{ - /*Trigger SOFTIRQ if necessary*/ - return; -} - -void BLAesEngine::decryption_trigger() -{ - /*Trigger SOFTIRQ if necessary*/ - return; -} - -int BLAesEngine::decryption(BLAesRequest &req) -{ - printf("%s %p...\r\n", __PRETTY_FUNCTION__, &req); - - /*request prepare*/ - req.done_pre(0); - /*push to queue and trigger if necessary*/ - if (NULL == this->push(req)) { - return -1; - } - this->decryption_trigger(); - /*request wait*/ - req.done_wait(); - - return 0; -} - -static class BLAesEngine *aes_engine; -extern "C" int platform_hal_device_init(void) -{ - class BLAesRequest *aes_request = new BLAesRequest[6]; - aes_engine = new BLAesEngine(); - - (void)aes_request; -#if 0 - aes_engine->encryption(aes_request[0]); -#endif - - return 0; -} diff --git a/bsp/bl808/m0/libraries/platform/hosal/platform_hal/platform_hal_device.h b/bsp/bl808/m0/libraries/platform/hosal/platform_hal/platform_hal_device.h deleted file mode 100644 index c884e3a080..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/platform_hal/platform_hal_device.h +++ /dev/null @@ -1,109 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __PLATFORM_HAL_DEVICE_H__ -#define __PLATFORM_HAL_DEVICE_H__ -#include -#include - -#ifdef __cplusplus -extern "C" -{ -#endif -int platform_hal_device_init(void); - -/*TMP solution for getting API from c scope*/ -int printf(const char *fmt, ...); -void *memcpy(void *dst, const void *src, size_t n); -void *memset(void *s, int c, size_t n); - -#ifdef __cplusplus -} // extern "C" -#endif - -#ifdef __cplusplus -#include - -class BLLinkedItem { -private: - class BLLinkedItem *next; -public: - BLLinkedItem(); - class BLLinkedItem* attach(class BLLinkedItem &item); - class BLLinkedItem* detach(); -}; - -class BLAesRequest : public BLLinkedItem { -public: - uint32_t key[4]; - uint32_t iv[4]; - uint8_t *src; - uint8_t *dst; - size_t len; - int first_use; - - int is_encryption;//0 for encryption, 1 for decryption - /*section for task control*/ - TaskHandle_t task_handle; - int done; -public: - BLAesRequest(); - BLAesRequest(uint8_t *key, uint8_t *iv, uint8_t *src, uint8_t *dst, int len); - int done_pre(int use_encryption); - int done_wait(); - int done_set(); - int done_set_auto(); - int done_set_FromISR(); -}; - -class BLLinkedList { -protected: - class BLLinkedItem *head; - class BLLinkedItem *tail; -public: - BLLinkedList(); - class BLLinkedList* push(class BLLinkedItem &item); - class BLLinkedItem* pop(); - class BLLinkedList* dump(); -}; - -class BLAesEngine : public BLLinkedList { -private: - class BLLinkedList head; - - void encryption_trigger(); - void decryption_trigger(); -public: - int encryption(BLAesRequest &req); - int decryption(BLAesRequest &req); -}; - -#endif - -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/sec_common/bl_sec_aes.c b/bsp/bl808/m0/libraries/platform/hosal/sec_common/bl_sec_aes.c deleted file mode 100644 index 36d508123b..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/sec_common/bl_sec_aes.c +++ /dev/null @@ -1,231 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include "bl_sec_hw_common.h" -#include - -#define AES_ID SEC_ENG_AES_ID0 - -int bl_sec_aes_init() -{ -#ifdef BL616 - Sec_Eng_Group0_Request_AES_Access(); -#endif - Sec_Eng_AES_Enable_BE(AES_ID); - return 0; -} - -int bl_aes_acquire_hw() -{ - taskENTER_CRITICAL(); - return 0; -} - -int bl_aes_release_hw() -{ - taskEXIT_CRITICAL(); - return 0; -} - -int bl_aes_init(bl_sec_aes_t *aes) -{ - if (!aes) { - return -1; - } -#ifdef BL616 - if (bl_sec_is_cache_addr(aes)) { - L1C_DCache_Clean_Invalid_By_Addr((uintptr_t)aes, sizeof(*aes)); - aes = bl_sec_get_no_cache_addr(aes); - } -#endif - memset(aes, 0, sizeof(*aes)); - aes->link_cfg.aesIntClr = 1; - aes->link_cfg.aesBlockMode = SEC_ENG_AES_ECB; - - return 0; -} - -int bl_aes_set_key(bl_sec_aes_t *aes, bl_sec_aes_op_t op, const uint8_t *key, size_t key_len) -{ - if (!(aes && key && (key_len == 16 || key_len == 24 || key_len == 32))) { - return -1; - } - (void)op; - -#ifdef BL616 - aes = bl_sec_get_no_cache_addr(aes); -#endif - - aes->link_cfg.aesDecKeySel = SEC_ENG_AES_USE_NEW; - SEC_ENG_AES_Key_Type key_type; - if (key_len == 16) { - key_type = SEC_ENG_AES_KEY_128BITS; - } else if (key_len == 24) { - key_type = SEC_ENG_AES_KEY_192BITS; - } else { - key_type = SEC_ENG_AES_KEY_256BITS; - } - aes->link_cfg.aesMode = key_type; - memcpy(&aes->link_cfg.aesKey0, key, key_len); - - return 0; -} - -int bl_aes_transform(bl_sec_aes_t *aes, bl_sec_aes_op_t op, const uint8_t *input, uint8_t *output) -{ - const uint16_t n_blk = 1; - if (!(aes && input && output)) { - return -1; - } - -#ifdef BL616 - aes = bl_sec_get_no_cache_addr(aes); - if (bl_sec_is_cache_addr(input)) { - L1C_DCache_Clean_Invalid_By_Addr((uintptr_t)input, 16); - } - if (bl_sec_is_cache_addr(output) && input != output) { - L1C_DCache_Clean_Invalid_By_Addr((uintptr_t)output, 16); - } -#endif - aes->link_cfg.aesMsgLen = n_blk; - if (op == BL_AES_ENCRYPT) { - aes->link_cfg.aesDecEn = SEC_ENG_AES_ENCRYPTION; - } else { - aes->link_cfg.aesDecEn = SEC_ENG_AES_DECRYPTION; - } - - Sec_Eng_AES_Enable_Link(AES_ID); - Sec_Eng_AES_Link_Work(AES_ID, (uint32_t)&aes->link_cfg, input, n_blk << 4, output); - Sec_Eng_AES_Disable_Link(AES_ID); - - return 0; -} - - -/* - * Test cases - */ -#include -#include - -bool tc_aes_ecb() -{ - const void *plaintext = "Bouffalo Lab Ltd"; - const void *keys[3] = { - "0123456789ABCDEF", - "0123456789ABCDEF01234567", - "0123456789ABCDEF0123456789ABCDEF", - }; - const uint8_t ciphertext[][16] = { - {0x36, 0x6B, 0xE1, 0x1E, 0xB7, 0x89, 0x31, 0x23, 0xBD, 0x7A, 0x27, 0xAE, 0x46, 0xC4, 0x28, 0x7D}, - {0xBD, 0x1A, 0x22, 0xD1, 0x76, 0xC5, 0x8B, 0x53, 0x83, 0xE7, 0xB7, 0x26, 0xD6, 0x33, 0x2B, 0x61}, - {0xCC, 0xB7, 0x21, 0xB9, 0x7B, 0x18, 0x43, 0xA0, 0x5B, 0xA9, 0x2C, 0x55, 0xF1, 0x4D, 0x24, 0xF0}, - }; - const uint8_t keylen[3] = {16, 24, 32}; - - uint8_t output[16]; - - while (1) { - bl_sec_aes_t *aes = malloc(sizeof(*aes)); - void *buf = malloc(16); - - if (!aes || !buf) { - printf("Over\r\n"); - return true; - } - - printf("Test addr %p\r\n", aes); - for (int i = 0; i < 3; ++i) { - // 3 key lengths - for (int j = 0; j < 2; ++j) { - // 2 data sources - for (int k = 0; k < 2; ++k) { - // encrypt/decrypt - bl_sec_aes_op_t op = BL_AES_ENCRYPT; - if (k == 1) { - op = BL_AES_DECRYPT; - } - void *input = NULL; - if (j == 0) { - // input from flash - if (k == 0) { - input = (void *)plaintext; - } else { - input = (void *)ciphertext[i]; - } - } else { - // input from ram - input = buf; - if (k == 0) { - memcpy(input, plaintext, 16); - } else { - memcpy(input, ciphertext[i], 16); - } - } - - memset(output, 0, sizeof(output)); - bl_aes_init(aes); - bl_aes_set_key(aes, op, keys[i], keylen[i]); - bl_aes_transform(aes, op, input, output); - const void *exp_result = ciphertext[i]; - if (k == 1) { - exp_result = plaintext; - } - if (memcmp(output, exp_result, 16)) { - printf("AES-ECB (%d,%d,%d) failed\r\n", i, j, k); - return false; - } - } - } - } - } - return true; -} - -#define MD(tc) {tc, #tc} -static struct { - bool (*tc_fun)(void); - const char *desc; -} tc[] = { - MD(tc_aes_ecb), -}; - -int bl_sec_aes_mem_test(void) -{ - for (int i = 0; i < sizeof(tc) / sizeof(tc[0]); ++i) { - printf("Running test case %s\r\n", tc[i].desc); - if (tc[i].tc_fun()) { - printf("\t\tPassed\r\n"); - } else { - printf("\t\tFailed\r\n"); - } - } - return 0; -} diff --git a/bsp/bl808/m0/libraries/platform/hosal/sec_common/bl_sec_aes.h b/bsp/bl808/m0/libraries/platform/hosal/sec_common/bl_sec_aes.h deleted file mode 100644 index c6ccbb51b0..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/sec_common/bl_sec_aes.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#pragma once - - -// copied struct from 616. Should be compatible with all chips -typedef struct -{ - uint32_t : 3; /*!< [2:0]Reserved */ - uint32_t aesMode : 2; /*!< [4:3]128-bit/256-bit/192-bit/128-bit-double key mode select */ - uint32_t aesDecEn : 1; /*!< [5]Encode or decode */ - uint32_t aesDecKeySel : 1; /*!< [6]Use new key or use same key as last one */ - uint32_t aesHwKeyEn : 1; /*!< [7]Enable or disable using hardware hey */ - uint32_t : 1; /*!< [8]Reserved */ - uint32_t aesIntClr : 1; /*!< [9]Clear interrupt */ - uint32_t aesIntSet : 1; /*!< [10]Set interrupt */ - uint32_t : 1; /*!< [11]Reserved */ - uint32_t aesBlockMode : 2; /*!< [13:12]ECB/CTR/CBC mode select */ - uint32_t aesIVSel : 1; /*!< [14]Use new iv or use same iv as last one */ - uint32_t aesXTS : 1; /*!< [15]XTS mode select */ - uint32_t aesMsgLen : 16; /*!< [31:16]Number of 128-bit block */ - uint32_t aesSrcAddr; /*!< Message source address */ - uint32_t aesDstAddr; /*!< Message destination address */ - uint32_t aesIV0; /*!< Big endian initial vector(MSB) */ - uint32_t aesIV1; /*!< Big endian initial vector */ - uint32_t aesIV2; /*!< Big endian initial vector */ - uint32_t aesIV3; /*!< Big endian initial vector(LSB)(CTR mode:counter initial value) */ - uint32_t aesKey0; /*!< Big endian aes key(aes-128/256 key MSB) */ - uint32_t aesKey1; /*!< Big endian aes key */ - uint32_t aesKey2; /*!< Big endian aes key */ - uint32_t aesKey3; /*!< Big endian aes key(aes-128 key LSB) */ - uint32_t aesKey4; /*!< Big endian aes key */ - uint32_t aesKey5; /*!< Big endian aes key */ - uint32_t aesKey6; /*!< Big endian aes key */ - uint32_t aesKey7; /*!< Big endian aes key(aes-256 key LSB) */ -} __attribute__((aligned(4))) bl_SEC_Eng_AES_Link_Config_Type; - -typedef enum { - BL_AES_ENCRYPT, - BL_AES_DECRYPT, -} bl_sec_aes_op_t; - -typedef struct { - bl_SEC_Eng_AES_Link_Config_Type link_cfg; -} bl_sec_aes_t; - -int bl_sec_aes_init(); -int bl_aes_acquire_hw(); -int bl_aes_release_hw(); -int bl_aes_init(bl_sec_aes_t *aes); -int bl_aes_set_key(bl_sec_aes_t *aes, bl_sec_aes_op_t op, const uint8_t *key, size_t key_len); -int bl_aes_transform(bl_sec_aes_t *aes, bl_sec_aes_op_t op, const uint8_t *input, uint8_t *output); diff --git a/bsp/bl808/m0/libraries/platform/hosal/sec_common/bl_sec_common.c b/bsp/bl808/m0/libraries/platform/hosal/sec_common/bl_sec_common.c deleted file mode 100644 index 62c6ace600..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/sec_common/bl_sec_common.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "bl_sec_hw_common.h" - -#ifdef BL616 -bool bl_sec_is_cache_addr(const void *addr) -{ - uintptr_t a = (uintptr_t)addr; - - if ((a & 0xFFFF0000UL) >= 0x62FC0000UL) { - return true; - } - return false; -} - -void *bl_sec_get_no_cache_addr(const void *addr) -{ - uintptr_t a = (uintptr_t)addr; - - if (!bl_sec_is_cache_addr(addr)) { - return (void *)addr; - } - - // OCRAM - if ((a & 0xF0000000UL) == 0x60000000UL) { - return (void *)((a & ~0xF0000000UL) | 0x20000000UL); - } - // pSRAM - if ((a & 0xF0000000UL) == 0xA0000000UL) { - return (void *)((a & ~0xF0000000UL) | 0x10000000UL); - } - - return NULL; -} -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/sec_common/bl_sec_common.h b/bsp/bl808/m0/libraries/platform/hosal/sec_common/bl_sec_common.h deleted file mode 100644 index f7089cd9dc..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/sec_common/bl_sec_common.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#pragma once - -#include - -typedef enum { - BL_SHA1, - BL_SHA224, - BL_SHA256, - BL_MD5, - BL_SHA384, - BL_SHA512, -} bl_sha_type_t; - -/* - * SHA1/SHA224/SHA256 - */ -/* copied SEC_Eng_SHA256_Ctx from stddrv */ -typedef struct { - uint32_t total[2]; - uint32_t *shaBuf; - uint32_t *shaPadding; - uint32_t linkAddr; -} bl_SEC_Eng_SHA256_Link_Ctx; - -// used for both SHA1/SHA224/SHA256 and SHA512 -typedef struct { - uint32_t shaCfgWord; - uint32_t shaSrcAddr; /*!< Message source address */ - uint32_t result[16]; /*!< Result of SHA */ -} __attribute__ ((aligned(4))) bl_SEC_Eng_SHA_Link_Config_Type; - -typedef struct bl_sha_ctx { - bl_sha_type_t type; - bl_SEC_Eng_SHA256_Link_Ctx ctx; - bl_SEC_Eng_SHA_Link_Config_Type link_cfg; - uint32_t tmp[16]; - uint32_t pad[16]; -} bl_sha_ctx_t; - - -/* - * SHA384/512 - */ -// copied SEC_Eng_SHA512_Link_Ctx from stddrv */ -typedef struct -{ - uint64_t total[2]; /*!< Number of bytes processed */ - uint64_t *shaBuf; /*!< Data not processed but in this temp buffer */ - uint64_t *shaPadding; /*!< Padding data */ - uint32_t linkAddr; /*!< Link configure address */ -} bl_SEC_Eng_SHA512_Link_Ctx; - -typedef struct bl_sha512_ctx { - bl_sha_type_t type; - bl_SEC_Eng_SHA512_Link_Ctx ctx; - bl_SEC_Eng_SHA_Link_Config_Type link_cfg; - uint64_t tmp[16]; - uint64_t pad[16]; -} bl_sha512_ctx_t; diff --git a/bsp/bl808/m0/libraries/platform/hosal/sec_common/bl_sec_hw_common.h b/bsp/bl808/m0/libraries/platform/hosal/sec_common/bl_sec_hw_common.h deleted file mode 100644 index 0d2e1d9fc6..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/sec_common/bl_sec_hw_common.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#pragma once - -#include - -#ifdef BL602 -#include -#include -#elif defined BL616 -#include -#include -#define SHA512_CAPABLE -#elif defined BL702 -#include -#include -#elif defined BL702L -#include -#include -#elif defined BL808 -#include -#include -#define SHA512_CAPABLE -#define MD5_CAPABLE -#else -#warn "Chip not ported" -#endif - -bool bl_sec_is_cache_addr(const void *addr); -void *bl_sec_get_no_cache_addr(const void *addr); diff --git a/bsp/bl808/m0/libraries/platform/hosal/sec_common/bl_sec_pka.c b/bsp/bl808/m0/libraries/platform/hosal/sec_common/bl_sec_pka.c deleted file mode 100644 index 79defc9983..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/sec_common/bl_sec_pka.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include - -#include -#include "bl_sec_hw_common.h" - -static StaticSemaphore_t pka_mutex_buf; -static SemaphoreHandle_t pka_mutex = NULL; - -int bl_sec_pka_init(void) -{ -#if defined(BL616) || defined BL808 - GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_MCU_MUXPLL_160M); -#elif defined(BL702L) - GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_SRC_HCLK); -#else - GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_HCLK); -#endif - - pka_mutex = xSemaphoreCreateMutexStatic(&pka_mutex_buf); - if (pka_mutex) { - return 0; - } else { - return -1; - } -} - -int bl_sec_pka_mutex_take(void) -{ - if (pdPASS != xSemaphoreTake(pka_mutex, portMAX_DELAY)) { - return -1; - } - return 0; -} - -int bl_sec_pka_mutex_give(void) -{ - if (pdPASS != xSemaphoreGive(pka_mutex)) { - return -1; - } - return 0; -} diff --git a/bsp/bl808/m0/libraries/platform/hosal/sec_common/bl_sec_pka.h b/bsp/bl808/m0/libraries/platform/hosal/sec_common/bl_sec_pka.h deleted file mode 100644 index a97f2165c2..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/sec_common/bl_sec_pka.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef BL_SEC_PKA_H_V3QMVSBY -#define BL_SEC_PKA_H_V3QMVSBY - -int bl_sec_pka_init(void); -int bl_sec_pka_mutex_take(void); -int bl_sec_pka_mutex_give(void); - -#endif /* end of include guard: BL_SEC_PKA_H_V3QMVSBY */ diff --git a/bsp/bl808/m0/libraries/platform/hosal/sec_common/bl_sec_sha.c b/bsp/bl808/m0/libraries/platform/hosal/sec_common/bl_sec_sha.c deleted file mode 100644 index d6dc1bea8a..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/sec_common/bl_sec_sha.c +++ /dev/null @@ -1,465 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include -#include - -#include -#include - -#include -#include -#include "bl_sec_common.h" -#include "bl_sec_hw_common.h" - -#include - -#define BL_SHA_ID SEC_ENG_SHA_ID0 // this is the only valid value - -#ifdef BL602 -static bl_SEC_Eng_SHA_Link_Config_Type working_link_cfg __attribute__((section(".wifi_ram"))); -#elif defined BL616 -// Nothing -#else -#error "No support for this chip" -#endif - -int bl_sec_sha_init() -{ -#ifdef BL616 - Sec_Eng_Group0_Request_SHA_Access(); -#endif - Sec_Eng_SHA_Enable_Link(BL_SHA_ID); - - return 0; -} - -int bl_sha_mutex_take() -{ - taskENTER_CRITICAL(); - return 0; -} - -int bl_sha_mutex_give() -{ - taskEXIT_CRITICAL(); - return 0; -} - -#ifdef BL602 -static bool is_tcm_addr(void *addr) -{ - uintptr_t addr_masked = (uintptr_t)addr & 0x0FFFFFFFUL; - - // Checking upper boundary ought to be enough - #define BL602_END_OF_DTCM 0x02020000UL - if (addr_masked < BL602_END_OF_DTCM) { - return true; - } - return false; -} -#endif - -static int bl_to_drv_type(bl_sha_type_t type) -{ - const uint8_t map[] = { - [BL_SHA1] = SEC_ENG_SHA1, - [BL_SHA224] = SEC_ENG_SHA224, - [BL_SHA256] = SEC_ENG_SHA256, -#ifdef MD5_CAPABLE - [BL_MD5] = SEC_ENG_MD5, -#endif -#ifdef SHA512_CAPABLE - [BL_SHA384] = SEC_ENG_SHA384, - [BL_SHA512] = SEC_ENG_SHA512, -#endif - }; - if (type < sizeof(map)) { - return map[type]; - } - return -1; -} - - -/* - * SHA1/SHA224/SHA256 - */ -int bl_sha_init(bl_sha_ctx_t *ctx, const bl_sha_type_t type) -{ - if (!(type == BL_SHA1 || type == BL_SHA224 || type == BL_SHA256)) { - return -1; - } - const SEC_ENG_SHA_Type sha_type = (SEC_ENG_SHA_Type)bl_to_drv_type(type); - -#ifdef BL616 - if (bl_sec_is_cache_addr(ctx)) { - L1C_DCache_Clean_Invalid_By_Addr((uintptr_t)ctx, sizeof(*ctx)); - ctx = bl_sec_get_no_cache_addr(ctx); - } -#endif - memset(ctx, 0, sizeof(*ctx)); - ctx->type = type; - SEC_Eng_SHA_Link_Config_Type *lc = (SEC_Eng_SHA_Link_Config_Type *)&ctx->link_cfg; - lc->shaMode = sha_type; - lc->shaIntSet = 1; - lc->shaIntClr = 1; - bl_SEC_Eng_SHA_Link_Config_Type *link_cfg = &ctx->link_cfg; -#ifdef BL602 - if (is_tcm_addr(ctx)) { - link_cfg = &working_link_cfg; - } -#endif - Sec_Eng_SHA256_Link_Init((SEC_Eng_SHA256_Link_Ctx *)&ctx->ctx, BL_SHA_ID, (uint32_t)link_cfg, ctx->tmp, ctx->pad); - return 0; -} - -int bl_sha_clone(bl_sha_ctx_t *dst, const bl_sha_ctx_t *src) -{ - if (!(dst && src)) { - return -1; - } - -#ifdef BL616 - if (bl_sec_is_cache_addr(dst)) { - L1C_DCache_Clean_Invalid_By_Addr((uintptr_t)dst, sizeof(*dst)); - } - if (bl_sec_is_cache_addr(src)) { - L1C_DCache_Clean_Invalid_By_Addr((uintptr_t)src, sizeof(*src)); - } - dst = bl_sec_get_no_cache_addr(dst); - src = bl_sec_get_no_cache_addr(src); -#endif - *dst = *src; - dst->ctx.shaBuf = dst->tmp; - dst->ctx.shaPadding = dst->pad; - dst->ctx.linkAddr = (uint32_t)&dst->link_cfg; -#ifdef BL602 - if (is_tcm_addr(dst)) { - dst->ctx.linkAddr = (uint32_t)&working_link_cfg; - } -#endif - return 0; -} - -int bl_sha_update(bl_sha_ctx_t *ctx, const uint8_t *input, uint32_t len) -{ -#ifdef BL602 - if (is_tcm_addr(ctx)) { - ARCH_MemCpy_Fast(&working_link_cfg, &ctx->link_cfg, sizeof(working_link_cfg)); - } -#elif defined BL616 - ctx = bl_sec_get_no_cache_addr(ctx); - if (bl_sec_is_cache_addr(input)) { - L1C_DCache_Clean_Invalid_By_Addr((uintptr_t)input, len); - } -#endif - Sec_Eng_SHA256_Link_Update((SEC_Eng_SHA256_Link_Ctx *)&ctx->ctx, BL_SHA_ID, input, len); -#ifdef BL602 - if (is_tcm_addr(ctx)) { - ARCH_MemCpy_Fast(&ctx->link_cfg, &working_link_cfg, sizeof(working_link_cfg)); - } -#endif - return 0; -} - -int bl_sha_finish(bl_sha_ctx_t *ctx, uint8_t *hash) -{ -#ifdef BL602 - if (is_tcm_addr(ctx)) { - ARCH_MemCpy_Fast(&working_link_cfg, &ctx->link_cfg, sizeof(working_link_cfg)); - } -#elif defined BL616 - ctx = bl_sec_get_no_cache_addr(ctx); -#endif - Sec_Eng_SHA256_Link_Finish((SEC_Eng_SHA256_Link_Ctx *)&ctx->ctx, BL_SHA_ID, hash); - return 0; -} - - -/* - * SHA384/SHA512 - */ -#ifdef SHA512_CAPABLE -int bl_sha512_init(bl_sha512_ctx_t *ctx, const bl_sha_type_t type) -{ - if (!(type == BL_SHA384 || type == BL_SHA512)) { - return -1; - } - const SEC_ENG_SHA_Type sha_type = (SEC_ENG_SHA_Type)bl_to_drv_type(type); - -#ifdef BL616 - if (bl_sec_is_cache_addr(ctx)) { - L1C_DCache_Clean_Invalid_By_Addr((uintptr_t)ctx, sizeof(*ctx)); - ctx = bl_sec_get_no_cache_addr(ctx); - } -#endif - memset(ctx, 0, sizeof(*ctx)); - ctx->type = type; - SEC_Eng_SHA_Link_Config_Type *lc = (SEC_Eng_SHA_Link_Config_Type *)&ctx->link_cfg; - lc->shaMode = sha_type; - lc->shaIntSet = 1; - lc->shaIntClr = 1; - bl_SEC_Eng_SHA_Link_Config_Type *link_cfg = &ctx->link_cfg; - Sec_Eng_SHA512_Link_Init((SEC_Eng_SHA512_Link_Ctx *)&ctx->ctx, BL_SHA_ID, (uint32_t)link_cfg, ctx->tmp, ctx->pad); - return 0; -} - -int bl_sha512_clone(bl_sha512_ctx_t *dst, const bl_sha512_ctx_t *src) -{ - if (!(dst && src)) { - return -1; - } - -#ifdef BL616 - if (bl_sec_is_cache_addr(dst)) { - L1C_DCache_Clean_Invalid_By_Addr((uintptr_t)dst, sizeof(*dst)); - } - if (bl_sec_is_cache_addr(src)) { - L1C_DCache_Clean_Invalid_By_Addr((uintptr_t)src, sizeof(*src)); - } - dst = bl_sec_get_no_cache_addr(dst); - src = bl_sec_get_no_cache_addr(src); -#endif - *dst = *src; - dst->ctx.shaBuf = dst->tmp; - dst->ctx.shaPadding = dst->pad; - dst->ctx.linkAddr = (uint32_t)&dst->link_cfg; - return 0; -} - -int bl_sha512_update(bl_sha512_ctx_t *ctx, const uint8_t *input, uint32_t len) -{ -#ifdef BL616 - ctx = bl_sec_get_no_cache_addr(ctx); - if (bl_sec_is_cache_addr(input)) { - L1C_DCache_Clean_Invalid_By_Addr((uintptr_t)input, len); - } -#endif - Sec_Eng_SHA512_Link_Update((SEC_Eng_SHA512_Link_Ctx *)&ctx->ctx, BL_SHA_ID, input, len); - return 0; -} - -int bl_sha512_finish(bl_sha512_ctx_t *ctx, uint8_t *hash) -{ -#ifdef BL616 - ctx = bl_sec_get_no_cache_addr(ctx); -#endif - Sec_Eng_SHA512_Link_Finish((SEC_Eng_SHA512_Link_Ctx *)&ctx->ctx, BL_SHA_ID, hash); - return 0; -} -#endif // SHA512_CAPABLE - - -/* - * Test cases - */ -#include - -static const char tc_hash_input[] = "The quick brown fox jumps over the lazy dog"; -bool tc_sha1() -{ - int i; - const bl_sha_type_t types[] = {BL_SHA1, BL_SHA224, BL_SHA256}; - uint8_t result[32]; - const uint8_t expected_results[][32] = { - {0x2f, 0xd4, 0xe1, 0xc6, 0x7a, 0x2d, 0x28, 0xfc, 0xed, 0x84, 0x9e, 0xe1, 0xbb, 0x76, 0xe7, 0x39, 0x1b, 0x93, 0xeb, 0x12, }, - {0x73, 0x0e, 0x10, 0x9b, 0xd7, 0xa8, 0xa3, 0x2b, 0x1c, 0xb9, 0xd9, 0xa0, 0x9a, 0xa2, 0x32, 0x5d, 0x24, 0x30, 0x58, 0x7d, 0xdb, 0xc0, 0xc3, 0x8b, 0xad, 0x91, 0x15, 0x25, }, - {0xd7, 0xa8, 0xfb, 0xb3, 0x07, 0xd7, 0x80, 0x94, 0x69, 0xca, 0x9a, 0xbc, 0xb0, 0x08, 0x2e, 0x4f, 0x8d, 0x56, 0x51, 0xe4, 0x6d, 0x3c, 0xdb, 0x76, 0x2d, 0x02, 0xd0, 0xbf, 0x37, 0xc9, 0xe5, 0x92, }, - }; - - const uint8_t z_2047_expected[][32] = { - {0xe3, 0x59, 0x9e, 0xf5, 0x8f, 0x6c, 0x1b, 0x77, 0x66, 0xf0, 0x45, 0x31, 0xb5, 0x01, 0xec, 0x24, 0x97, 0xb2, 0xa8, 0x2e, }, - {0xe6, 0xdb, 0x06, 0x25, 0xba, 0xb0, 0x0a, 0x65, 0xeb, 0x25, 0xeb, 0xcb, 0xe6, 0xd5, 0xc3, 0xb6, 0x6b, 0x04, 0xad, 0x12, 0xc8, 0x91, 0x25, 0xa3, 0x4e, 0x10, 0xfe, 0x6c, }, - {0xa6, 0xb4, 0xc4, 0x6a, 0xa0, 0xaa, 0xce, 0x53, 0x8f, 0x48, 0x4c, 0x2c, 0x7d, 0x3c, 0x96, 0x4b, 0x2c, 0x10, 0xb1, 0x95, 0x9b, 0xe4, 0xf9, 0xc6, 0x57, 0xa2, 0x7b, 0x37, 0xb6, 0xe7, 0x00, 0xe5, }, - }; - - while (1) { - uint8_t *in_buf; - bl_sha_ctx_t *ctx; - - for (int i = 0; i < 1; ++i) { - in_buf = malloc(2047); - ctx = malloc(sizeof(*ctx)); - if (!in_buf || !ctx) { - printf("Over!\r\n"); - while (1) { - } - } - } - printf("Test addr %p\r\n", ctx); - for (int j = 0; j < 1 * 1000; ++j) { - for (i = 0; i < sizeof(types) / sizeof(types[0]); ++i) { - size_t len = sizeof(tc_hash_input) - 1; - memcpy(in_buf, tc_hash_input, len); - bl_sha_init(ctx, types[i]); - bl_sha_update(ctx, in_buf, len); - memset(result, 0, sizeof(result)); - bl_sha_finish(ctx, result); - if (memcmp(result, expected_results[i], 32) != 0) { - printf("SHA1 #%d failed\r\n", i); - return false; - } - - // input from flash - bl_sha_init(ctx, types[i]); - bl_sha_update(ctx, (void *)tc_hash_input, len); - memset(result, 0, sizeof(result)); - bl_sha_finish(ctx, result); - if (memcmp(result, expected_results[i], 32) != 0) { - printf("SHA1 input from flash #%d failed\r\n", i); - return false; - } - - // 2047 Zs - size_t left = 2047; - memset(in_buf, 'Z', 2047); - bl_sha_init(ctx, types[i]); - while (left > 0) { - size_t l = (bl_rand() & 0xFFU) + 1; - if (l > left) { - l = left; - } - bl_sha_update(ctx, in_buf + (2047 - left), l); - left -= l; - } - memset(result, 0, sizeof(result)); - bl_sha_finish(ctx, result); - if (memcmp(result, z_2047_expected[i], 32) != 0) { - printf("SHA 2047-Z #%d failed\r\n", i); - return false; - } - } - } - } - return true; -} - -#ifdef SHA512_CAPABLE -bool tc_sha512() -{ - int i; - const bl_sha_type_t types[] = { - BL_SHA384, BL_SHA512, - }; - uint8_t result[64]; - const uint8_t expected_results[][64] = { - {0xca, 0x73, 0x7f, 0x10, 0x14, 0xa4, 0x8f, 0x4c, 0x0b, 0x6d, 0xd4, 0x3c, 0xb1, 0x77, 0xb0, 0xaf, 0xd9, 0xe5, 0x16, 0x93, 0x67, 0x54, 0x4c, 0x49, 0x40, 0x11, 0xe3, 0x31, 0x7d, 0xbf, 0x9a, 0x50, 0x9c, 0xb1, 0xe5, 0xdc, 0x1e, 0x85, 0xa9, 0x41, 0xbb, 0xee, 0x3d, 0x7f, 0x2a, 0xfb, 0xc9, 0xb1, }, - {0x07, 0xe5, 0x47, 0xd9, 0x58, 0x6f, 0x6a, 0x73, 0xf7, 0x3f, 0xba, 0xc0, 0x43, 0x5e, 0xd7, 0x69, 0x51, 0x21, 0x8f, 0xb7, 0xd0, 0xc8, 0xd7, 0x88, 0xa3, 0x09, 0xd7, 0x85, 0x43, 0x6b, 0xbb, 0x64, 0x2e, 0x93, 0xa2, 0x52, 0xa9, 0x54, 0xf2, 0x39, 0x12, 0x54, 0x7d, 0x1e, 0x8a, 0x3b, 0x5e, 0xd6, 0xe1, 0xbf, 0xd7, 0x09, 0x78, 0x21, 0x23, 0x3f, 0xa0, 0x53, 0x8f, 0x3d, 0xb8, 0x54, 0xfe, 0xe6, }, - }; - - const uint8_t z_2047_expected[][64] = { - {0x34, 0x1e, 0x3b, 0xd8, 0xf2, 0x3e, 0xc0, 0x3a, 0x26, 0x8a, 0x1d, 0x16, 0xc3, 0xe9, 0xf8, 0x0c, 0xeb, 0x5a, 0xd0, 0xe5, 0xf9, 0x79, 0x88, 0xa6, 0x2d, 0x39, 0x0b, 0x0e, 0x18, 0xb3, 0x1c, 0x42, 0x2c, 0xa0, 0x93, 0x72, 0x5a, 0x05, 0x94, 0x11, 0x3e, 0x65, 0x36, 0x16, 0x36, 0xcf, 0xe3, 0x24, }, - {0x62, 0x8e, 0x01, 0x46, 0x09, 0x53, 0x24, 0x5e, 0x40, 0x84, 0xe9, 0x06, 0x5b, 0x04, 0x7a, 0x92, 0xf5, 0xf6, 0x72, 0x7f, 0xfb, 0x93, 0x96, 0x35, 0x92, 0xed, 0xc9, 0x3b, 0xea, 0x62, 0x01, 0xf5, 0x66, 0x43, 0xf4, 0x9e, 0x70, 0xdf, 0x3c, 0x2a, 0x25, 0x19, 0xa6, 0xbc, 0x98, 0x36, 0xfe, 0x85, 0x05, 0xd1, 0x99, 0x76, 0x6d, 0x02, 0x35, 0xc5, 0x64, 0xbb, 0x16, 0x1f, 0x9b, 0x60, 0x99, 0x07, }, - }; - while (1) { - uint8_t *in_buf; - bl_sha512_ctx_t *ctx; - - for (int i = 0; i < 1; ++i) { - in_buf = malloc(2047); - ctx = malloc(sizeof(*ctx)); - if (!in_buf || !ctx) { - printf("Over!\r\n"); - while (1) { - } - } - } - printf("Test addr %p\r\n", ctx); - for (int j = 0; j < 1 * 1000; ++j) { - for (i = 0; i < sizeof(types) / sizeof(types[0]); ++i) { - size_t len = sizeof(tc_hash_input) - 1; - memcpy(in_buf, tc_hash_input, len); - bl_sha512_init(ctx, types[i]); - bl_sha512_update(ctx, in_buf, len); - memset(result, 0, sizeof(result)); - bl_sha512_finish(ctx, result); - if (memcmp(result, expected_results[i], 64) != 0) { - printf("SHA512 #%d failed\r\n", i); - return false; - } - - // input from flash - bl_sha512_init(ctx, types[i]); - bl_sha512_update(ctx, (void *)tc_hash_input, len); - memset(result, 0, sizeof(result)); - bl_sha512_finish(ctx, result); - if (memcmp(result, expected_results[i], 64) != 0) { - printf("SHA512 input from flash #%d failed\r\n", i); - return false; - } - - // 2047 Zs - size_t left = 2047; - memset(in_buf, 'Z', 2047); - bl_sha512_init(ctx, types[i]); - while (left > 0) { - size_t l = (bl_rand() & 0xFFU) + 1; - if (l > left) { - l = left; - } - bl_sha512_update(ctx, in_buf + (2047 - left), l); - left -= l; - } - memset(result, 0, sizeof(result)); - bl_sha512_finish(ctx, result); - if (memcmp(result, z_2047_expected[i], 64) != 0) { - printf("SHA 2047-Z #%d failed\r\n", i); - return false; - } - } - } - } - return true; -} -#endif - -#define MD(tc) {tc, #tc} -static struct { - bool (*tc_fun)(void); - const char *desc; -} tc[] = { - MD(tc_sha1), -#ifdef SHA512_CAPABLE - MD(tc_sha512), -#endif -}; - -int bl_sec_sha_test(void) -{ - for (int i = 0; i < sizeof(tc) / sizeof(tc[0]); ++i) { - printf("Running test case %s\r\n", tc[i].desc); - if (tc[i].tc_fun()) { - printf("\t\tPassed\r\n"); - } else { - printf("\t\tFailed\r\n"); - } - } - return 0; -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bflb_bsp_driver_glue.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bflb_bsp_driver_glue.h deleted file mode 100644 index 614b7a351b..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bflb_bsp_driver_glue.h +++ /dev/null @@ -1,53 +0,0 @@ -/** - * ***************************************************************************** - * @file bflb_bsp_driver_glue.h - * @version 0.1 - * @date 2020-07-08 - * @brief - * ***************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * ***************************************************************************** - */ -#ifndef __bBFLB_BSP_DRIVER_GLUE_H__ -#define __bBFLB_BSP_DRIVER_GLUE_H__ - - -#include - -#include "bl808_common.h" -#include "bl808_sec_eng.h" -#include "bl808_glb.h" -#include "bl808_dma.h" -#include "bl808_usb.h" -#include "bl808_sdh.h" -#include "bl808_xip_sflash.h" - -#define CPU_FLASH_XIP_BASE BL606P_FLASH_XIP_BASE -#define CPU_FLASH_XIP_END BL606P_FLASH_XIP_END - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bflb_stub.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bflb_stub.c deleted file mode 100644 index 2448d3c28b..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bflb_stub.c +++ /dev/null @@ -1,160 +0,0 @@ -/** - * ***************************************************************************** - * @file bflb_stub.c - * @version 0.1 - * @date 2020-07-08 - * @brief - * ***************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * ***************************************************************************** - */ -#include "bflb_stub.h" -#include "bflb_bsp_driver_glue.h" - - -void BFLB_Delay_Ms(uint32_t tim){ - ARCH_Delay_MS(tim); -} - -void BFLB_Delay_Us(uint32_t tim){ - ARCH_Delay_US(tim); -} - -int BFLB_BSP_Get_Random(uint8_t *data,uint32_t len) -{ - uint8_t tmpBuf[32]; - uint32_t readLen=0; - uint32_t i=0,cnt=0; - - while(readLensizeof(tmpBuf)){ - cnt=sizeof(tmpBuf); - } - for(i=0;i4){ - break; - } - }while(tmpValLow>tmpValLow1||tmpValHigh>tmpValHigh1); - - tmp=(SystemCoreClockGet()/(GLB_Get_BCLK_Div()+1)); - tmp=(tmp>>3)/1000; - - if(tmpValHigh1==0){ - return(uint64_t)(tmpValLow1/tmp); - }else{ - return (((uint64_t)tmpValHigh1<<32)+tmpValLow1)/tmp; - } -} - -void BFLB_BSP_Start_Time() -{ - *(volatile uint64_t*) (CLIC_CTRL_ADDR + CLIC_MTIME) = 0; -} - -void BFLB_BSP_Stop_Time() -{ - -} - -void BFLB_BSP_Set_Alarm_Time(uint64_t time) -{ - uint32_t tmp; - - tmp=(SystemCoreClockGet()/(GLB_Get_BCLK_Div()+1)); - tmp=(tmp>>3)/1000; - - time = time*tmp; - - *(volatile uint64_t*) (CLIC_CTRL_ADDR + CLIC_MTIMECMP) = (*(volatile uint64_t*) (CLIC_CTRL_ADDR + CLIC_MTIME) + time) ; - CPU_Interrupt_Enable(MTIME_IRQn); -} - -void BFLB_BSP_Set_Alarm_CallBack(void( *interruptFun )( void ) ) -{ - Interrupt_Handler_Register(MTIME_IRQn,interruptFun); -} - -void BFLB_BSP_Deinit_Time() -{ - CPU_Interrupt_Disable(MTIME_IRQn); - BFLB_BSP_Stop_Time(); -} - -void BFLB_BSP_Delay_Ms(uint32_t time) -{ - uint64_t cnt=0; - uint32_t clock=SystemCoreClockGet(); - uint64_t startTime=BFLB_BSP_Get_Time_Ms(); - - while(BFLB_BSP_Get_Time_Ms()-startTime(time*(clock>>(10+5)))*2){ - break; - } - } -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bflb_stub.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bflb_stub.h deleted file mode 100644 index 70aacb2cf2..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bflb_stub.h +++ /dev/null @@ -1,54 +0,0 @@ -/** - * ***************************************************************************** - * @file bflb_stub.h - * @version 0.1 - * @date 2020-07-08 - * @brief - * ***************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * ***************************************************************************** - */ -#ifndef __BFLB_STUB__ -#define __BFLB_STUB__ - -#include "stdint.h" - -void BFLB_Delay_Ms(uint32_t tim); -void BFLB_Delay_Us(uint32_t tim); -int BFLB_BSP_Get_Random(uint8_t *data,uint32_t len); -void BFLB_BSP_Init_Time(void); -void BFLB_BSP_Clear_Time(void); -uint64_t BFLB_BSP_Get_Time_Ms(void); -void BFLB_BSP_Start_Time(void); -void BFLB_BSP_Stop_Time(void); -void BFLB_BSP_Set_Alarm_CallBack(void( *interruptFun )( void )); -void BFLB_BSP_Set_Alarm_Time(uint64_t time); -void BFLB_BSP_Deinit_Time(void); -void BFLB_BSP_Delay_Ms(uint32_t time); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/.gitignore b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/.gitignore deleted file mode 100644 index 03ec4f3e29..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/.gitignore +++ /dev/null @@ -1,3 +0,0 @@ -.vscode/* -.settings - diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/blsp_boot2_iap_flash.ld b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/blsp_boot2_iap_flash.ld deleted file mode 100644 index 8778f84825..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/blsp_boot2_iap_flash.ld +++ /dev/null @@ -1,264 +0,0 @@ -/**************************************************************************************** -* @file flash.ld -* -* @brief This file is the link script file (gnuarm or armgcc). -* -* Copyright (C) BouffaloLab 2021 -* -**************************************************************************************** -*/ - -/* configure the CPU type */ -OUTPUT_ARCH( "riscv" ) -/* link with the standard c library */ -INPUT(-lc) -/* link with the standard GCC library */ -INPUT(-lgcc) -/* configure the entry point */ -ENTRY(Reset_Handler) - -StackSize = 0x0400; /* 1KB */ -HeapMinSize = 0x1000; /* 4KB */ -/* ToDo */ -PROVIDE(__boot2_pass_param_addr = 0x62057C00);/* 0x42030000+159*1024 */ -MEMORY -{ - xip_memory (rx) : ORIGIN = 0x58000000, LENGTH = 48K - itcm_memory (rx) : ORIGIN = 0x62020000, LENGTH = 48K - dtcm_memory (rx) : ORIGIN = 0x6202C000, LENGTH = 4K - nocache_ram_memory (!rx) : ORIGIN = 0x2202D000, LENGTH = 84K - ram_memory (!rx) : ORIGIN = 0x62042000, LENGTH = 16K -} - -SECTIONS -{ - - .text : - { - . = ALIGN(4); - __text_code_start__ = .; - KEEP(*startup*.*o(*.text*)) - KEEP (*(SORT_NONE(_start))) - KEEP (*(SORT_NONE(Reset_Handler))) - - *(.text) - *(.text.*) - - /* section information for shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - - /* section information for usb desc */ - . = ALIGN(4); - _usb_desc_start = .; - KEEP(*(usb_desc)) - . = ALIGN(4); - _usb_desc_end = .; - - /*put .rodata**/ - *(EXCLUDE_FILE( *bl808_glb*.o* \ - *bl808_glb_gpio*.o* \ - *bl808_pds*.o* \ - *bl808_aon*.o* \ - *bl808_hbn*.o* \ - *bl808_l1c*.o* \ - *bl808_common*.o* \ - *bl808_clock*.o* \ - *bl808_ef_ctrl*.o* \ - *bl808_sf_cfg*.o* \ - *bl808_sf_ctrl*.o* \ - *bl808_sflash*.o* \ - *bl808_xip_sflash*.o* \ - *bl808_romapi_patch*.o* ) .rodata*) - - *(.srodata) - *(.srodata.*) - - . = ALIGN(4); - __text_code_end__ = .; - } > xip_memory - - . = ALIGN(4); - __itcm_load_addr = .; - - .itcm_region : AT (__itcm_load_addr) - { - . = ALIGN(4); - __tcm_code_start__ = .; - - *(.tcm_code.*) - *(.tcm_const.*) - *(.sclock_rlt_code.*) - *(.sclock_rlt_const.*) - - *bl808_glb*.o*(.rodata*) - *bl808_glb_gpio*.o*(.rodata*) - *bl808_pds*.o*(.rodata*) - *bl808_aon*.o*(.rodata*) - *bl808_hbn*.o*(.rodata*) - *bl808_l1c*.o*(.rodata*) - *bl808_common*.o*(.rodata*) - *bl808_clock*.o*(.rodata*) - *bl808_ef_ctrl*.o*(.rodata*) - *bl808_sf_cfg*.o*(.rodata*) - *bl808_sf_ctrl*.o*(.rodata*) - *bl808_sflash*.o*(.rodata*) - *bl808_xip_sflash*.o*(.rodata*) - *bl808_romapi_patch*.o*(.rodata*) - - . = ALIGN(4); - __tcm_code_end__ = .; - } > itcm_memory - - __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region); - - .dtcm_region : AT (__dtcm_load_addr) - { - . = ALIGN(4); - __tcm_data_start__ = .; - - *(.tcm_data) - /* *finger_print.o(.data*) */ - - . = ALIGN(4); - __tcm_data_end__ = .; - } > dtcm_memory - - /*************************************************************************/ - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (NOLOAD): - { - . = ALIGN(0x4); - . = . + StackSize; - . = ALIGN(0x4); - } > dtcm_memory - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory); - PROVIDE( __freertos_irq_stack_top = __StackTop); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack") - /*************************************************************************/ - /*__nocache_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);*/ - - .nocache_ram_region (NOLOAD) : - { - . = ALIGN(4); - __nocache_ram_data_start__ = .; - - *(.nocache_ram) - - . = ALIGN(4); - __nocache_ram_data_end__ = .; - } > nocache_ram_memory - - __system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region); - - .system_ram_data_region (NOLOAD) : - { - . = ALIGN(4); - __system_ram_data_start__ = .; - - *(.system_ram) - - . = ALIGN(4); - __system_ram_data_end__ = .; - } > ram_memory - - .system_ram_noinit_data_region (NOLOAD) : - { - . = ALIGN(4); - *(.system_ram_noinit) - - . = ALIGN(4); - } > ram_memory - - __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region); - - /* Data section */ - RAM_DATA : AT (__ram_load_addr) - { - . = ALIGN(4); - __ram_data_start__ = .; - - PROVIDE( __global_pointer$ = . + 0x800 ); - - *(.data) - *(.data.*) - *(.sdata) - *(.sdata.*) - *(.sdata2) - *(.sdata2.*) - - . = ALIGN(4); - __ram_data_end__ = .; - } > ram_memory - - __etext_final = (__ram_load_addr + SIZEOF (RAM_DATA)); - ASSERT(__etext_final <= ORIGIN(xip_memory) + LENGTH(xip_memory), "code memory overflow") - - .bl_bss : AT (__bss_start__) - { - . = ALIGN(4); - __bss_start__ = .; - - *(.bss*) - *(.sbss*) - *(COMMON) - - . = ALIGN(4); - __bss_end__ = .; - } > ram_memory - - .noinit_data (NOLOAD) : - { - . = ALIGN(4); - __noinit_data_start__ = .; - - *(.noinit_data*) - - . = ALIGN(4); - __noinit_data_end__ = .; - } > ram_memory - - .nocache_noinit_ram_region (NOLOAD) : - { - . = ALIGN(4); - __nocache_ram_data_start__ = .; - - *(.nocache_noinit_ram) - - . = ALIGN(4); - __nocache_ram_data_end__ = .; - } > nocache_ram_memory - - .heap (NOLOAD): - { - . = ALIGN(4); - __HeapBase = .; - - /*__end__ = .;*/ - /*end = __end__;*/ - KEEP(*(.heap*)) - - . = ALIGN(4); - __HeapLimit = .; - } > ram_memory - - __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory); - ASSERT(__HeapLimit - __HeapBase >= HeapMinSize, "heap region overflow") - -} - diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/cpu_flags.cmake b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/cpu_flags.cmake deleted file mode 100644 index e30769db22..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/cpu_flags.cmake +++ /dev/null @@ -1,3 +0,0 @@ -include(${CMAKE_SOURCE_DIR}/drivers/${CHIP}_driver/startup/${CPU_ID}/cpu_flags.cmake) - -SET(BOOT2_LINKER_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/blsp_boot2_iap_flash.ld) \ No newline at end of file diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/default_config/adc_config.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/default_config/adc_config.h deleted file mode 100644 index 68c0ffbca4..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/default_config/adc_config.h +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef _ADC_CONFIG_H -#define _ADC_CONFIG_H - -#define ADC_DATA_WIDIH_12 (0) - -#define ADC_V18_SELECT (2) /*!< ADC 1.8V select */ -#define ADC_V11_SELECT (1) /*!< ADC 1.1V select */ - -#define ADC_PGA_VCM (0) /*!< ADC VCM value */ -#define ADC_PGA_GAIN1 (0) /*!< PGA gain 1 */ -#define ADC_PGA_GAIN2 (0) /*!< PGA gain 2 */ -#define ADC_CHOP_MODE (2) /*!< ADC chop mode select */ -#define ADC_BIAS_SELECT (0) /*!< ADC current form main bandgap or aon bandgap */ -#define ADC_OFFSET_CALIB_EN (0) /*!< Offset calibration enable */ -#define ADC_OFFSER_CALIB_VAL (0) /*!< Offset calibration value */ - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/default_config/dac_config.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/default_config/dac_config.h deleted file mode 100644 index c611675bde..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/default_config/dac_config.h +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef _DAC_CONFIG_H -#define _DAC_CONFIG_H - -/* | vref source | rng | output range | - * | Internal | 0 | 0.2~1V | - * | Internal | 1/2 | 0.224~1.425V | - * | Internal | 3 | 0.2~1.8V | - * | Extern | 0 | 0.1Vref~0.5Vref | - * | Extern | 1/2 | 0.1125Vref~0.7125Vref | - * | Extern | 3 | 0.1Vref~0.9Vref | - */ -#define DAC_REF_RNG_DEFAULT_SELECT (0x3) /*!< ADC 1.8V select */ - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/default_config/i2s_config.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/default_config/i2s_config.h deleted file mode 100644 index eeaf9f8784..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/default_config/i2s_config.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef _I2S_CONFIG_H -#define _I2S_CONFIG_H - -#define I2S_ADUIO_PLL_DEFAULT AUDIO_PLL_12288000_HZ -#define I2S_DATA_ENDIAN I2S_DATA_ENDIAN_MSB -#define I2S_MONO_CHANNEL I2S_RX_MONO_MODE_LEFT_CHANNEL -#define I2S_LR_EXCHANGE DISABLE /*The position of L/R channel data within each entry is exchanged if enabled*/ -#define I2S_FS_INVERT DISABLE -#define I2S_BCLK_INVERT DISABLE - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/default_config/uart_config.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/default_config/uart_config.h deleted file mode 100644 index 96aa97821b..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/default_config/uart_config.h +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef _UART_CONFIG_H -#define _UART_CONFIG_H - -#define UART_CLOCK_SOURCE_96M_ENABLE (1) -#define UART_CTS_FLOWCONTROL_ENABLE (0) -#define UART_RTS_FLOWCONTROL_ENABLE (0) -#define UART_RX_DEGLITCH_ENABLE (0) -#define UART_MSB_FIRST_ENABLE (0) -#define UART_TX_SWCONTROL_ENABLE (0) -#define UART_TX_LINMODE_ENABLE (0) -#define UART_RX_LINMODE_ENABLE (0) -#define UART_TX_BREAKBIT_CNT (0) - -#define UART_FIFO_MAX_LEN 32 -#define UART_DEFAULT_RTO_TIMEOUT 100 - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_adc.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_adc.h deleted file mode 100644 index f956db98f2..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_adc.h +++ /dev/null @@ -1,176 +0,0 @@ -/** - * @file hal_adc.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __HAL_ADC__H__ -#define __HAL_ADC__H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "hal_common.h" -#include "drv_device.h" -#include "bl808_config.h" - -#define DEVICE_CTRL_ADC_CHANNEL_START 0x10 -#define DEVICE_CTRL_ADC_CHANNEL_STOP 0x11 -#define DEVICE_CTRL_ADC_CHANNEL_CONFIG 0x12 -#define DEVICE_CTRL_ADC_VBAT_ON 0x13 -#define DEVICE_CTRL_ADC_VBAT_OFF 0x14 -#define DEVICE_CTRL_ADC_TSEN_ON 0x15 -#define DEVICE_CTRL_ADC_TSEN_OFF 0x16 - -enum adc_index_type { -#ifdef BSP_USING_ADC0 - ADC0_INDEX, -#endif - ADC_MAX_INDEX -}; - -#define adc_channel_start(dev) device_control(dev, DEVICE_CTRL_ADC_CHANNEL_START, NULL) -#define adc_channel_stop(dev) device_control(dev, DEVICE_CTRL_ADC_CHANNEL_STOP, NULL) -#define adc_channel_config(dev, list) device_control(dev, DEVICE_CTRL_ADC_CHANNEL_CONFIG, list) - -typedef enum { - ADC_CHANNEL0, /* ADC channel 0 */ - ADC_CHANNEL1, /* ADC channel 1 */ - ADC_CHANNEL2, /* ADC channel 2 */ - ADC_CHANNEL3, /* ADC channel 3 */ - ADC_CHANNEL4, /* ADC channel 4 */ - ADC_CHANNEL5, /* ADC channel 5 */ - ADC_CHANNEL6, /* ADC channel 6 */ - ADC_CHANNEL7, /* ADC channel 7 */ - ADC_CHANNEL8, /* ADC channel 8 */ - ADC_CHANNEL9, /* ADC channel 9 */ - ADC_CHANNEL10, /* ADC channel 10 */ - ADC_CHANNEL11, /* ADC channel 11 */ - ADC_CHANNEL_DAC_OUTA, /* DACA, ADC channel 12 */ - ADC_CHANNEL_DAC_OUTB, /* DACB, ADC channel 13 */ - ADC_CHANNEL_TSEN_P, /* TSenp, ADC channel 14 */ - ADC_CHANNEL_TSEN_N, /* TSenn, ADC channel 15 */ - ADC_CHANNEL_VREF, /* Vref, ADC channel 16 */ - ADC_CHANNEL_DCTEST, /* DCTest, ADC channel 17 */ - ADC_CHANNEL_VABT_HALF, /* VBAT/2, ADC channel 18 */ - ADC_CHANNEL_SENP3, /* SenVP3, ADC channel 19 */ - ADC_CHANNEL_SENP2, /* SenVP2, ADC channel 20 */ - ADC_CHANNEL_SENP1, /* SenVP1, ADC channel 21 */ - ADC_CHANNEL_SENP0, /* SenVP0, ADC channel 22 */ - ADC_CHANNEL_GND, /* GND, ADC channel 23 */ -} adc_channel_t; - -typedef enum { - ADC_CLOCK_DIV_1, /*!< ADC clock:on 32M clock is 32M */ - ADC_CLOCK_DIV_4, /*!< ADC clock:on 32M clock is 8M */ - ADC_CLOCK_DIV_8, /*!< ADC clock:on 32M clock is 4M */ - ADC_CLOCK_DIV_12, /*!< ADC clock:on 32M clock is 2.666M */ - ADC_CLOCK_DIV_16, /*!< ADC clock:on 32M clock is 2M */ - ADC_CLOCK_DIV_20, /*!< ADC clock:on 32M clock is 1.6M */ - ADC_CLOCK_DIV_24, /*!< ADC clock:on 32M clock is 1.333M */ - ADC_CLOCK_DIV_32, /*!< ADC clock:on 32M clock is 1M */ -} adc_clk_div_t; - -typedef enum { - ADC_VREF_3V2 = 0, /* ADC select 3.2V as reference voltage */ - ADC_VREF_2V = 1, /* ADC select 2V as reference voltage */ -} adc_vref_t; - -/** - * @brief ADC data width type definition - */ -typedef enum { - ADC_DATA_WIDTH_12B, /*!< ADC 12 bits */ - ADC_DATA_WIDTH_14B_WITH_16_AVERAGE, /*!< ADC 14 bits,and the value is average of 16 converts */ - ADC_DATA_WIDTH_14B_WITH_64_AVERAGE, /*!< ADC 14 bits,and the value is average of 64 converts */ - ADC_DATA_WIDTH_16B_WITH_128_AVERAGE, /*!< ADC 16 bits,and the value is average of 128 converts */ - ADC_DATA_WIDTH_16B_WITH_256_AVERAGE, /*!< ADC 16 bits,and the value is average of 256 converts */ -} adc_data_width_t; - -/** - * @brief ADC FIFO threshold type definition - */ -typedef enum { - ADC_FIFO_THRESHOLD_1BYTE, /*!< ADC FIFO threshold is 1 */ - ADC_FIFO_THRESHOLD_4BYTE, /*!< ADC FIFO threshold is 4 */ - ADC_FIFO_THRESHOLD_8BYTE, /*!< ADC FIFO threshold is 8 */ - ADC_FIFO_THRESHOLD_16BYTE, /*!< ADC FIFO threshold is 16 */ -} adc_fifo_threshold_t; - -/** - * @brief ADC PGA gain type definition - */ -typedef enum { - ADC_GAIN_NONE, /*!< No PGA gain */ - ADC_GAIN_1, /*!< PGA gain 1 */ - ADC_GAIN_2, /*!< PGA gain 2 */ - ADC_GAIN_4, /*!< PGA gain 4 */ - ADC_GAIN_8, /*!< PGA gain 8 */ - ADC_GAIN_16, /*!< PGA gain 16 */ - ADC_GAIN_32, /*!< PGA gain 32 */ -} adc_pga_gain_t; - -enum adc_event_type { - ADC_EVENT_UNDERRUN, - ADC_EVENT_OVERRUN, - ADC_EVENT_FIFO, - ADC_EVENT_UNKNOWN -}; - -enum adc_it_type { - ADC_UNDERRUN_IT = 1 << 2, - ADC_OVERRUN_IT = 1 << 3, - ADC_FIFO_IT = 1 << 5, -}; - -typedef struct { - uint8_t *pos_channel; - uint8_t *neg_channel; - uint8_t num; -} adc_channel_cfg_t; - -typedef struct { - int8_t posChan; /*!< Positive channel */ - int8_t negChan; /*!< Negative channel */ - uint16_t value; /*!< ADC value */ - float volt; /*!< ADC voltage result */ -} adc_channel_val_t; - -typedef struct adc_device { - struct device parent; - adc_clk_div_t clk_div; /* CLK is not more than 2Mhz */ - adc_vref_t vref; /* ADC voltage reference*/ - bool continuous_conv_mode; /** conversion mode: shot conversion mode or continuous conversion mode. */ - bool differential_mode; /** Channel type: single-ended or differential. */ - adc_data_width_t data_width; - adc_fifo_threshold_t fifo_threshold; - adc_pga_gain_t gain; -} adc_device_t; - -#define ADC_DEV(dev) ((adc_device_t *)dev) - -int adc_register(enum adc_index_type index, const char *name); -int adc_trim_tsen(uint16_t *tsen_offset); -float adc_get_tsen(uint16_t tsen_offset); - -#ifdef __cplusplus -} -#endif -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_audio.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_audio.h deleted file mode 100644 index 2131b47661..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_audio.h +++ /dev/null @@ -1,261 +0,0 @@ -/** - * @file hal_audio.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ - -#ifndef __HAL_AUDIO__ -#define __HAL_AUDIO__ - -#include "audio_reg.h" -#include "bl808_audio.h" -#include "bl808_dma.h" -#include "drv_device.h" - -/** @addtogroup BL808_Middleware_Driver - * @{ - */ - -/** @addtogroup AUDIO_Middleware - * @{ - */ - -/** @defgroup AUDIO_Middleware_Public_Types - * @{ - */ - -/** - * @brief Audio Flow Type - */ -typedef enum { - AUDIO_PLAY = 0, /*!< Audio Play selction */ - AUDIO_RECORDING, /*!< Audio Recording selction */ -} Audio_Flow_Type; - -/** - * @brief Audio Channel Sel - */ -typedef enum { - LEFT_CHANNEL = 1, /*!< select mono mode left only */ - RIGHT_CHANNEL, /*!< select mono mode right only */ - STEREO_CHANNEL, /*!< select stereo */ -} Audio_Channel_Type; - -/** - * @brief Audio mixer option - */ -typedef enum { - MIX_WITH_ADC_LEFT = 1, /*!< mix With ADC Left */ - MIX_WITH_ADC_RIGHT, /*!< mix With ADC Right */ -} Audio_Mixer_Cfg_Type; - -/** - * @brief Audio Play/recording bit width - */ -typedef enum { - AUDIO_BIT_WIDTH_16, /*!< 16 bit */ - AUDIO_BIT_WIDTH_24, /*!< 24 bit */ - AUDIO_BIT_WIDTH_32, /*!< 32 bit */ -} Audio_BitWidth_Type; - -/** - * @brief Audio Input Interface - */ -typedef enum { - AUDIO_INPUT_PDM_DMIC, /*!< audio input source is Dmic */ - AUDIO_INPUT_ANG_AMIC, /*!< audio input source is Amic */ -} Audio_RecordingInterface_Type; - -/** - * @brief Audio_PlayCfg_Type - */ -typedef struct { - DMA_ID_Type audioDmaId; /*!< audio dma id */ - DMA_Chan_Type audioDmaChannelId; /*!< audio dma channel id */ - uint32_t playSampleRate; /*!< audio play sample rate */ - Audio_BitWidth_Type playBitWidth; /*!< audio play bit width */ - Audio_Channel_Type channel; /*!< audio play channel number */ - uint16_t audioInitVolume; /*!< initial audio volume */ - void (*pingpongBufferCarryDoneCallback)(uint8_t pp_index); /*!< audio dma carry pingpong buffer done callback function pointer */ - void (*volumeSetDoneCallback)(uint8_t dac_index); /*!< When the volume is adjusted this function pointer will be run */ - BL_Fun_Type audioMixerEn; /*!< enable mixer or not */ - Audio_Mixer_Cfg_Type dacLeftMixWith; /*!< select dac left channel mix with adc right or left */ - Audio_Mixer_Cfg_Type dacRightMixWith; /*!< select dac right channel mix with adc right or left */ -} Audio_PlayCfg_Type; - -/** - * @brief Audio_RecordingCfg_Type - */ -typedef struct { - DMA_ID_Type audioDmaId; /*!< audio dma id */ - DMA_Chan_Type audioDmaChannelId; /*!< audio dma channel id */ - uint32_t recordingSampleRate; /*!< audio Recording sample rate */ - Audio_RecordingInterface_Type recordinginterface; /*!< audio Recording input interface */ - Audio_BitWidth_Type recordingBitWidth; /*!< audio Recording bit width */ - Audio_Channel_Type channel; /*!< audio Recording channel number */ - uint16_t audioInitVolume; /*!< initial audio Recording volume */ - void (*pingpongBufferCarryDoneCallback)(uint8_t pp_index); /*!< audio dma carry pingpong buffer done callback function pointer */ - void (*volumeSetDoneCallback)(uint8_t adc_index); /*!< When the volume is adjusted this function pointer will be run */ -} Audio_RecordingCfg_Type; - -/*@} end of group AUDIO_Middleware_Public_Types */ - -/** @defgroup AUDIO_Middleware_Public_Constants - * @{ - */ - -/** @defgroup AUDIO_FLOW_TYPE - * @{ - */ -#define IS_AUDIO_FLOW_TYPE(type) (((type) == AUDIO_PLAY) || \ - ((type) == AUDIO_RECORDING)) - -/** @defgroup AUDIO_CHANNEL_TYPE - * @{ - */ -#define IS_AUDIO_CHANNEL_TYPE(type) (((type) == LEFT_CHANNEL) || \ - ((type) == RIGHT_CHANNEL) || \ - ((type) == STEREO_CHANNEL)) - -/** @defgroup AUDIO_MIXER_CFG_TYPE - * @{ - */ -#define IS_AUDIO_MIXER_CFG_TYPE(type) (((type) == MIX_WITH_ADC_LEFT) || \ - ((type) == MIX_WITH_ADC_RIGHT)) - -/** @defgroup AUDIO_BITWIDTH_TYPE - * @{ - */ -#define IS_AUDIO_BITWIDTH_TYPE(type) (((type) == AUDIO_BIT_WIDTH_16) || \ - ((type) == AUDIO_BIT_WIDTH_24) || \ - ((type) == AUDIO_BIT_WIDTH_32)) - -/** @defgroup AUDIO_RECORDINGINTERFACE_TYPE - * @{ - */ -#define IS_AUDIO_RECORDINGINTERFACE_TYPE(type) (((type) == AUDIO_INPUT_PDM_DMIC) || \ - ((type) == AUDIO_INPUT_ANG_AMIC)) - -/*@} end of group AUDIO_Middleware_Public_Constants */ - -/** @defgroup AUDIO_Middleware_Public_Macros - * @{ - */ -#define AUDIO_PLAY_PINGPONG_BUFFER_SIZE (2 * 1024) -#define AUDIO_RECORDING_PINGPONG_BUFFER_SIZE (2 * 1024) -#define AUDIO_TX_FIFO_ADDR AUDIO_BASE + 0x94 -#define AUDIO_RX_FIFO_ADDR AUDIO_BASE + 0x88 -#define AUDIO_DEFAULT_TX_DRQ_THR 8 -#define AUDIO_DEFAULT_RX_DRQ_THR 8 -/* audio play configuration */ -#define AUDIO_PLAY_DEFAULT_DMA_ID DMA0_ID -#define AUDIO_PLAY_DEFAULT_DMA_CHANNEL DMA_CH0 -#define AUDIO_PLAY_DEFAULT_SAMPLE 48 * 1000 -#define AUDIO_PLAY_DEFAULT_BIT_WIDTH AUDIO_BIT_WIDTH_16 -#define AUDIO_PLAY_DEFAULT_INITIAL_VOLUME 0xffad -#define AUDIO_PLAY_DEFAULT_CHANNEL_NUM STEREO_CHANNEL -#define AUDIO_PLAY_DEFAULT_MIXER_EN DISABLE -#define AUDIO_PLAY_DEFAULT_LEFT_MIX_WITH MIX_WITH_ADC_LEFT -#define AUDIO_PLAY_DEFAULT_RIGHT_MIX_WITH MIX_WITH_ADC_RIGHT -/*audio recording configuration */ -#define AUDIO_RECORDING_DEFAULT_DMA_ID DMA0_ID -#define AUDIO_RECORDING_DEFAULT_DMA_CHANNEL DMA_CH1 -#define AUDIO_RECORDING_DEFAULT_SAMPLE 16 * 1000 -#define AUDIO_RECORDING_DEFAULT_BIT_WIDTH AUDIO_BIT_WIDTH_16 -#define AUDIO_RECORDING_DEFAULT_INITIAL_VOLUME 60 -/* if user want to select more adc channel option , -* you can write such as -* ADC1_DATA_CHANNEL_FIFO_EN | ADC3_DATA_CHANNEL_FIFO_EN | -* middleware default set is (ADC1_DATA_CHANNEL_FIFO_EN | ADC2_DATA_CHANNEL_FIFO_EN) equel to STEREO_CHANNEL -**/ -#define AUDIO_RECORDING_DEFAULT_CHANNEL_NUM STEREO_CHANNEL -#define AUDIO_RECORDING_DEFAULT_INTERFACE AUDIO_INPUT_PDM_DMIC - -/*@} end of group AUDIO_Middleware_Public_Macros */ - -/** @defgroup AUDIO_Middleware_Public_Functions - * @{ - */ -/* Audio Play Profile API */ -BL_Err_Type Audio_PlayDeInit(void); -BL_Err_Type Audio_PlayInit(Audio_PlayCfg_Type *cfg); -BL_Err_Type Audio_PlayParameterInit(Audio_PlayCfg_Type *cfg); -BL_Err_Type Audio_PlaySetVolume(Audio_Channel_Type channel, int16_t volume); -int16_t Audio_PlayGetVolume(Audio_Channel_Type channel); -BL_Err_Type Audio_PlayStart(Audio_PlayCfg_Type *cfg); -BL_Err_Type Audio_PlayStop(Audio_PlayCfg_Type *cfg); -/* Audio Recording API */ -BL_Err_Type Audio_RecordingDeInit(void); -BL_Err_Type Audio_RecordingInit(Audio_RecordingCfg_Type *cfg); -BL_Err_Type Audio_RecordingParameterInit(Audio_RecordingCfg_Type *cfg); -BL_Err_Type Audio_RecordingSetVolume(Audio_Channel_Type channel, int16_t volume); -int16_t Audio_RecordingGetVolume(Audio_Channel_Type channel); -BL_Err_Type Audio_RecordingStart(Audio_RecordingCfg_Type *cfg); -BL_Err_Type Audio_RecordingStop(Audio_RecordingCfg_Type *cfg); -/* Audio AEC API */ -BL_Err_Type Audio_AecInit(BL_Fun_Type sw, Audio_Channel_Type channel, - Audio_AEC_Atten_Mode aecDrop, Audio_PlayCfg_Type *playCfg, Audio_RecordingCfg_Type *recordingCfg); -uint32_t Audio_GetPingpongBufferAddr(Audio_Flow_Type flowType); -uint32_t Audio_GetPingBufferAddr(Audio_Flow_Type flowType); -uint32_t Audio_GetPongBufferAddr(Audio_Flow_Type flowType); -uint32_t Audio_GetPingpongBufferLength(Audio_Flow_Type flowType); -void Audio_FlushPingpongBuffer(Audio_Flow_Type flowType); - -//--adapt - -#define DEVICE_CTRL_UART_GET_TX_FIFO 0x10 -#define DEVICE_CTRL_UART_GET_RX_FIFO 0x11 - -enum audio_index_type { -#ifdef BSP_USING_AUDIO - AUDIO0_INDEX, -#endif - AUDIO_MAX_INDEX -}; - -typedef struct audio_device { - struct device parent; - uint32_t sampleRate; - Audio_BitWidth_Type bitWidth; - Audio_Channel_Type channel; - uint16_t audioInitVolume; - void (*pingpongBufferCarryDoneCallback)(uint8_t pp_index); - void (*volumeSetDoneCallback)(uint8_t dac_index); - void *tx_dma; - void *rx_dma; -} audio_device_t; - -#define AUDIO_DEV(dev) ((audio_device_t *)dev) - -#define DEVICE_CTRL_PLAY_VOLUME 0x0E -#define DEVICE_CTRL_RECORDING_VOLUME 0x0F - -#define DEVICE_CTRL_RECORDING_START 0x10 -#define DEVICE_CTRL_RECORDING_STOP 0x11 -#define DEVICE_CTRL_PLAY_START 0x12 -#define DEVICE_CTRL_PLAY_STOP 0x13 - -#define DEVICE_CTRL_GET_PLAY_PING_BUF 0x14 -#define DEVICE_CTRL_GET_PLAY_PONG_BUF 0x15 -#define DEVICE_CTRL_GET_RECORD_PING_BUF 0x16 -#define DEVICE_CTRL_GET_RECORD_PONG_BUF 0x17 - -int audio_register(enum audio_index_type index, const char *name); -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_boot2.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_boot2.h deleted file mode 100644 index 0de6107507..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_boot2.h +++ /dev/null @@ -1,323 +0,0 @@ -/** - * ***************************************************************************** - * @file hal_boot2_custom.h - * @version 0.1 - * @date 2021-07-17 - * @brief - * ***************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * ***************************************************************************** - */ -#ifndef __HAL_BOOT2_H__ -#define __HAL_BOOT2_H__ - -#include "hal_common.h" -#include "bl808_sflash.h" -#include "bl808_glb.h" - -#define HAL_PLL_CFG_MAGICCODE "PCFG" - -#define HAL_BOOT2_PK_HASH_SIZE 256 / 8 -#define HAL_BOOT2_IMG_HASH_SIZE 256 / 8 -#define HAL_BOOT2_ECC_KEYXSIZE 256 / 8 -#define HAL_BOOT2_ECC_KEYYSIZE 256 / 8 -#define HAL_BOOT2_SIGN_MAXSIZE (2048 / 8) -#define HAL_BOOT2_DEADBEEF_VAL 0xdeadbeef -#define HAL_BOOT2_CPU0_MAGIC "BFNP" -#define HAL_BOOT2_CPU1_MAGIC "BFAP" -#define HAL_BOOT2_CP_FLAG 0x02 -#define HAL_BOOT2_MP_FLAG 0x01 -#define HAL_BOOT2_SP_FLAG 0x00 - -#define HAL_BOOT2_SUPPORT_DECOMPRESS 1 /* 1 support decompress, 0 not support */ -#define HAL_BOOT2_SUPPORT_USB_IAP 0 /* 1 support IAP, 0 not support */ -#define HAL_BOOT2_SUPPORT_EFLASH_LOADER_RAM 0 /* 1 support eflash loader ram, 0 not support */ -#define HAL_BOOT2_SUPPORT_EFLASH_LOADER_FLASH 0 /* 1 support eflash loader flash, 0 not support */ -#define HAL_BOOT2_SUPPORT_SIGN_ENCRYPT 1 /* 1 support sign and encrypt, 0 not support */ - -#define HAL_BOOT2_CPU_GROUP_MAX 1 -#define HAL_BOOT2_CPU_MAX 3 -#define HAL_BOOT2_RAM_IMG_COUNT_MAX 5 - -#define HAL_BOOT2_FW_IMG_OFFSET_AFTER_HEADER 4 * 1024 -#define HAL_BOOT2_MFG_START_REQUEST_OFFSET 8 * 1024 - -#define HAL_BOOT2_PSRAM_INFO_MASK (0xff0000) -#define HAL_BOOT2_PSRAM_INFO_POS (16) - -struct __attribute__((packed, aligned(4))) boot_efuse_sw_cfg0_t { - uint32_t bootrom_protect : 1; /* ef_sw_usage_0 bit [0] */ - uint32_t uart_log_disable : 1; /* ef_sw_usage_0 bit [1] */ - uint32_t boot_pin_cfg : 1; /* ef_sw_usage_0 bit [2] */ - //uint32_t dbg_pin_cfg : 1; /* ef_sw_usage_0 bit [3] */ - uint32_t uart_download_cfg : 1; /* ef_sw_usage_0 bit [3] */ - - uint32_t mediaboot_disable : 1; /* ef_sw_usage_0 bit [4] */ - uint32_t uartboot_disable : 1; /* ef_sw_usage_0 bit [5] */ - uint32_t usbboot_enable : 1; /* ef_sw_usage_0 bit [6] */ - uint32_t uart_log_reopen : 1; /* ef_sw_usage_1 bit [7] */ - - uint32_t sign_cfg : 1; /* ef_sw_usage_0 bit [8] */ - uint32_t dcache_disable : 1; /* ef_sw_usage_0 bit [9] */ - uint32_t jtag_cfg : 2; /* ef_sw_usage_0 bit [11:10] */ - - uint32_t fix_key_sel : 1; /* ef_sw_usage_0 bit [12] */ - - uint32_t sdh_en : 1; /* ef_sw_usage_1 bit [13] */ - uint32_t sf_pin_cfg : 5; /* ef_sw_usage_0 bit [18:14] */ - uint32_t boot_level_revert : 1; /* ef_sw_usage_0 bit [19] */ - - uint32_t boot_pin_dly : 2; /* ef_sw_usage_0 bit [21:20] */ - uint32_t ldo_trim_enable : 1; /* ef_sw_usage_0 bit [22] */ - uint32_t trim_enable : 1; /* ef_sw_usage_0 bit [23] */ - - uint32_t no_hd_boot_en : 1; /* ef_sw_usage_0 bit [24] */ - uint32_t flash_power_delay : 2; /* ef_sw_usage_0 bit [26:25] */ - uint32_t tz_boot : 1; /* ef_sw_usage_0 bit [27] */ - - uint32_t encrypted_tz_boot : 1; /* ef_sw_usage_0 bit [28] */ - uint32_t hbn_check_sign : 1; /* ef_sw_usage_0 bit [29] */ - uint32_t keep_dbg_port_closed : 1; /* ef_sw_usage_0 bit [30] */ - uint32_t hbn_jump_disable : 1; /* ef_sw_usage_0 bit [31] */ -}; - -struct __attribute__((packed, aligned(4))) boot_efuse_sw_cfg1_t { - uint32_t xtal_type : 3; /* ef_sw_usage_1 bit [2:0] */ - uint32_t wifipll_pu : 1; /* ef_sw_usage_1 bit [3] */ - - uint32_t aupll_pu : 1; /* ef_sw_usage_1 bit [4] */ - uint32_t cpupll_pu : 1; /* ef_sw_usage_1 bit [5] */ - uint32_t mipipll_pu : 1; /* ef_sw_usage_1 bit [6] */ - uint32_t uhspll_pu : 1; /* ef_sw_usage_1 bit [7] */ - - uint32_t mcu_clk : 3; /* ef_sw_usage_1 bit [10:8] */ - uint32_t mcu_clk_div : 1; /* ef_sw_usage_1 bit [11] */ - - uint32_t mcu_pbclk_div : 2; /* ef_sw_usage_1 bit [13:12] */ - uint32_t lp_div : 1; /* ef_sw_usage_1 bit [14] */ - uint32_t dsp_clk : 2; /* ef_sw_usage_1 bit [16:15] */ - uint32_t dsp_clk_div : 1; /* ef_sw_usage_1 bit [17] */ - uint32_t dsp_pbclk : 2; /* ef_sw_usage_1 bit [19:18] */ - - uint32_t emi_clk : 2; /* ef_sw_usage_1 bit [21:20] */ - uint32_t emi_clk_div : 1; /* ef_sw_usage_1 bit [22] */ - uint32_t flash_clk_type : 3; /* ef_sw_usage_1 bit [25:23] */ - uint32_t flash_clk_div : 1; /* ef_sw_usage_1 bit [26] */ - uint32_t ldo18flash_bypass_cfg : 1; /* ef_sw_usage_1 bit [27] */ - uint32_t bootlog_pin_cfg : 1; /* ef_sw_usage_1 bit [28] */ - - uint32_t abt_offset : 1; /* ef_sw_usage_1 bit [29] */ - uint32_t boot_pull_cfg : 1; /* ef_sw_usage_1 bit [30] */ - uint32_t usb_if_int_disable : 1; /* ef_sw_usage_1 bit [31] */ -}; - -typedef struct -{ - uint8_t encrypted[HAL_BOOT2_CPU_GROUP_MAX]; - uint8_t sign[HAL_BOOT2_CPU_GROUP_MAX]; - uint8_t hbn_check_sign; - uint8_t rsvd[3]; - uint8_t chip_id[8]; - uint8_t pk_hash_cpu0[HAL_BOOT2_PK_HASH_SIZE]; - uint8_t pk_hash_cpu1[HAL_BOOT2_PK_HASH_SIZE]; - uint8_t uart_download_cfg; - uint8_t sf_pin_cfg; - uint8_t keep_dbg_port_closed; - uint8_t boot_pin_cfg; - uint32_t dev_info; -} boot2_efuse_hw_config; - -struct __attribute__((packed, aligned(4))) hal_flash_config { - uint32_t magicCode; /*'FCFG'*/ - SPI_Flash_Cfg_Type cfg; - uint32_t crc32; -}; - -struct __attribute__((packed, aligned(4))) hal_sys_clk_config { - uint8_t xtal_type; - uint8_t mcu_clk; - uint8_t mcu_clk_div; - uint8_t mcu_bclk_div; - - uint8_t mcu_pbclk_div; - uint8_t lp_div; - uint8_t dsp_clk; - uint8_t dsp_clk_div; - - uint8_t dsp_bclk_div; - uint8_t dsp_pbclk; - uint8_t dsp_pbclk_div; - uint8_t emi_clk; - - uint8_t emi_clk_div; - uint8_t flash_clk_type; - uint8_t flash_clk_div; - uint8_t wifipll_pu; - - uint8_t aupll_pu; - uint8_t cpupll_pu; - uint8_t mipipll_pu; - uint8_t uhspll_pu; -}; - -typedef struct { - uint32_t magiccode; - struct hal_sys_clk_config cfg; - uint32_t crc32; -} hal_pll_config; - -struct __attribute__((packed, aligned(4))) hal_basic_cfg_t { - uint32_t sign_type : 2; /* [1: 0] for sign */ - uint32_t encrypt_type : 2; /* [3: 2] for encrypt */ - uint32_t key_sel : 2; /* [5: 4] key slot */ - uint32_t xts_mode : 1; /* [6] for xts mode */ - uint32_t aes_region_lock : 1; /* [7] rsvd */ - uint32_t no_segment : 1; /* [8] no segment info */ - uint32_t boot2_enable : 1; /* [9] boot2 enable */ - uint32_t boot2_rollback : 1; /* [10] boot2 rollback */ - uint32_t cpu_master_id : 4; /* [14: 11] master id */ - uint32_t notload_in_bootrom : 1; /* [15] notload in bootrom */ - uint32_t crc_ignore : 1; /* [16] ignore crc */ - uint32_t hash_ignore : 1; /* [17] hash ignore */ - uint32_t power_on_mm : 1; /* [18] power on mm */ - uint32_t em_sel : 3; /* [21: 19] em_sel */ - uint32_t cmds_en : 1; /* [22] command spliter enable */ - uint32_t cmds_wrap_mode : 2; /* [24: 23] cmds wrap mode */ - uint32_t cmds_wrap_len : 4; /* [28: 25] cmds wrap len */ - uint32_t icache_invalid : 1; /* [29] icache invalid */ - uint32_t dcache_invalid : 1; /* [30] dcache invalid */ - uint32_t fpga_halt_release : 1; /* [31] FPGA halt release function */ - - uint32_t group_image_offset; /* flash controller offset */ - uint32_t aes_region_len; /* aes region length */ - - uint32_t img_len_cnt; /* image length or segment count */ - uint32_t hash[8]; /* hash of the image */ -}; - -struct __attribute__((packed, aligned(4))) hal_cpu_cfg_t { - uint8_t config_enable; /* coinfig this cpu */ - uint8_t halt_cpu; /* halt this cpu */ - uint8_t cache_enable : 1; /* cache setting */ - uint8_t cache_wa : 1; /* cache setting */ - uint8_t cache_wb : 1; /* cache setting */ - uint8_t cache_wt : 1; /* cache setting */ - uint8_t cache_way_dis : 4; /* cache setting */ - uint8_t rsvd; - - uint32_t cache_range_h; /* cache range high */ - uint32_t cache_range_l; /* cache range low */ - - uint32_t image_address_offset; /* image address on flash */ /*image_address_offset*/ - uint32_t boot_entry; /* entry point of the m0 image */ - uint32_t msp_val; /* msp value */ -}; - -struct __attribute__((packed, aligned(4))) hal_patch_cfg_t { - uint32_t addr; - uint32_t value; -}; - -struct __attribute__((packed, aligned(4))) hal_bootheader_t { - uint32_t magiccode; - uint32_t rivison; - - struct hal_flash_config flashCfg; - hal_pll_config clkCfg; - - struct hal_basic_cfg_t basic_cfg; - - struct hal_cpu_cfg_t cpu_cfg[HAL_BOOT2_CPU_MAX]; - - uint32_t boot2_pt_table_0; /* address of partition table 0 */ - uint32_t boot2_pt_table_1; /* address of partition table 1 */ - - uint32_t flashCfgTableAddr; /* address of flashcfg table list */ - uint32_t flashCfgTableLen; /* flashcfg table list len */ - - struct hal_patch_cfg_t patch_on_read[4]; /* do patch when read flash */ - struct hal_patch_cfg_t patch_on_jump[4]; /* do patch when jump */ - - uint32_t rsvd[5]; - - uint32_t crc32; -}; - -typedef struct -{ - uint8_t img_valid; - uint8_t pk_src; - uint8_t rsvd[2]; - - struct hal_basic_cfg_t basic_cfg; - - struct hal_cpu_cfg_t cpu_cfg[HAL_BOOT2_CPU_MAX]; - - uint8_t aes_iv[16 + 4]; //iv in boot header - - uint8_t eckye_x[HAL_BOOT2_ECC_KEYXSIZE]; //ec key in boot header - uint8_t eckey_y[HAL_BOOT2_ECC_KEYYSIZE]; //ec key in boot header - uint8_t eckey_x2[HAL_BOOT2_ECC_KEYXSIZE]; //ec key in boot header - uint8_t eckey_y2[HAL_BOOT2_ECC_KEYYSIZE]; //ec key in boot header - - uint8_t signature[HAL_BOOT2_SIGN_MAXSIZE]; //signature in boot header - uint8_t signature2[HAL_BOOT2_SIGN_MAXSIZE]; //signature in boot header - -} boot2_image_config; - -extern boot2_efuse_hw_config g_efuse_cfg; -extern uint8_t g_ps_mode; -extern uint32_t g_user_hash_ignored; -extern struct device *dev_check_hash; - -void hal_boot2_init_clock(void); -uint32_t hal_boot2_custom(void *custom_param); -void hal_boot2_reset_sec_eng(void); -void hal_boot2_sw_system_reset(void); -void hal_boot2_set_psmode_status(uint32_t flag); -uint32_t hal_boot2_get_psmode_status(void); -uint32_t hal_boot2_get_user_fw(void); -void hal_boot2_clr_user_fw(void); -void hal_boot2_get_efuse_cfg(boot2_efuse_hw_config *efuse_cfg); -int32_t hal_boot2_get_clk_cfg(hal_pll_config *cfg); -void hal_boot2_sboot_finish(void); -void hal_boot2_uart_gpio_init(void); -void hal_boot2_debug_uart_gpio_init(void); -void hal_boot2_debug_uart_gpio_deinit(void); -int32_t hal_boot_parse_bootheader(boot2_image_config *boot_img_cfg, uint8_t *data); -void hal_boot2_clean_cache(void); -BL_Err_Type hal_boot2_set_cache(uint8_t cont_read, boot2_image_config *boot_img_cfg); -void hal_boot2_get_ram_img_cnt(char *img_name[], uint32_t *ram_img_cnt); -void hal_boot2_get_img_info(uint8_t *data, uint32_t *image_offset, uint32_t *img_len, uint8_t **hash); -void hal_boot2_release_cpu(uint32_t core, uint32_t boot_addr); -uint32_t hal_boot2_get_xip_addr(uint32_t flash_addr); -uint32_t hal_boot2_get_grp_count(void); -uint32_t hal_boot2_get_cpu_count(void); -uint32_t hal_boot2_get_feature_flag(void); -uint32_t hal_boot2_get_bootheader_offset(void); -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_clock.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_clock.h deleted file mode 100644 index cb4698a215..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_clock.h +++ /dev/null @@ -1,72 +0,0 @@ -/** - * @file hal_clock.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __HAL_CLOCK__H__ -#define __HAL_CLOCK__H__ - -#include "hal_common.h" - -/*XTAL_TYPE*/ -#define XTAL_NONE 0 -#define EXTERNAL_XTAL_24M 1 -#define EXTERNAL_XTAL_32M 2 -#define EXTERNAL_XTAL_38P4M 3 -#define EXTERNAL_XTAL_40M 4 -#define EXTERNAL_XTAL_26M 5 -#define INTERNAL_RC_32M 6 - -/*CLOCK_32K_XTAL*/ -#define EXTERNAL_XTAL_32K 0 -#define INTERNAL_RC_32K 1 - -#define ROOT_CLOCK_SOURCE_32K_CLK 0 -#define ROOT_CLOCK_SOURCE_XCLK 1 -#define ROOT_CLOCK_SOURCE_WIFIPLL_32M 2 -#define ROOT_CLOCK_SOURCE_WIFIPLL_48M 3 -#define ROOT_CLOCK_SOURCE_WIFIPLL_80M 4 -#define ROOT_CLOCK_SOURCE_WIFIPLL_96M 5 -#define ROOT_CLOCK_SOURCE_WIFIPLL_160M 6 -#define ROOT_CLOCK_SOURCE_WIFIPLL_240M 7 -#define ROOT_CLOCK_SOURCE_WIFIPLL_320M 8 -#define ROOT_CLOCK_SOURCE_CPUPLL_80M 9 -#define ROOT_CLOCK_SOURCE_CPUPLL_100M 10 -#define ROOT_CLOCK_SOURCE_CPUPLL_160M 11 -#define ROOT_CLOCK_SOURCE_CPUPLL_200M 12 -#define ROOT_CLOCK_SOURCE_CPUPLL_400M 13 -#define ROOT_CLOCK_SOURCE_AUPLL_DIV1 14 -#define ROOT_CLOCK_SOURCE_AUPLL_DIV2 15 -#define ROOT_CLOCK_SOURCE_AUPLL_DIV2P5 16 -#define ROOT_CLOCK_SOURCE_AUPLL_DIV5 17 -#define ROOT_CLOCK_SOURCE_AUPLL_DIV6 18 -#define ROOT_CLOCK_SOURCE_AUPLL_CLK 19 - -#define BSP_CLOCK_SOURCE_FCLK 20 -#define BSP_CLOCK_SOURCE_BCLK 21 - -#define BSP_CLOCK_SOURCE_MUXPLL_80M ROOT_CLOCK_SOURCE_WIFIPLL_80M -#define BSP_CLOCK_SOURCE_MUXPLL_160M ROOT_CLOCK_SOURCE_WIFIPLL_160M - -void system_clock_init(void); -void peripheral_clock_init(void); -void system_mtimer_clock_init(void); -void system_mtimer_clock_reinit(void); -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_common.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_common.h deleted file mode 100644 index 4fa4f5667d..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_common.h +++ /dev/null @@ -1,49 +0,0 @@ -/** - * @file hal_common.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __HAL_COMMON__H__ -#define __HAL_COMMON__H__ - -#include "bl808_common.h" - -typedef enum { - HAL_REBOOT_AS_BOOTPIN, /*!< reboot as bootpin level */ - HAL_REBOOT_FROM_INTERFACE, /*!< reboot from interface, download mode */ - HAL_REBOOT_FROM_MEDIA, /*!< reboot from media, running mode */ - HAL_REBOOT_MAX /*!< reboot max value */ -} hal_reboot_cfg_t; - -void cpu_global_irq_enable(void); -void cpu_global_irq_disable(void); -void hal_por_reset(void); -void hal_system_reset(void); -void hal_cpu_reset(void); -void hal_reboot_config(hal_reboot_cfg_t rbot); -void hal_get_chip_id(uint8_t chip_id[8]); -void hal_dcache_clean_all(void); -void hal_dcache_invalid_all(void); -void hal_dcache_clean_invalid_all(void); -void hal_dcache_clean_byaddr(uintptr_t addr, uint32_t len); -void hal_dcache_invalidate_byaddr(uintptr_t addr, uint32_t len); -void hal_dcache_clean_invalidate_byaddr(uintptr_t addr, uint32_t len); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_dac.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_dac.h deleted file mode 100644 index 9a6a152451..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_dac.h +++ /dev/null @@ -1,72 +0,0 @@ -/** - * @file hal_dac.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __HAL_DAC__H__ -#define __HAL_DAC__H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "hal_common.h" -#include "drv_device.h" -#include "bl808_config.h" - -enum dac_index_type { -#ifdef BSP_USING_DAC0 - DAC0_INDEX, -#endif - DAC_MAX_INDEX -}; - -#define DAC_CHANNEL_0 (1 << 0) -#define DAC_CHANNEL_1 (1 << 1) -#define DAC_CHANNEL_ALL (DAC_CHANNEL_0 | DAC_CHANNEL_1) - -/* default a_rng and b_rng is 0x03*/ -/*output Voltage = (1.8V-0.2V) * digital_val/1024 + 0.2V */ -#define DAC_VREF_INTERNAL 0 /*0.2V~1.8V*/ -/*output Voltage = (0.9vref-0.1vref) * digital_val/1024 + 0.1vref */ -#define DAC_VREF_EXTERNAL 1 /*0.1vref~0.9vref,using gpio7 for GPIO_FUN_ADC*/ - -enum dac_sample_frequence { - DAC_SAMPLE_FREQ_8KHZ, - DAC_SAMPLE_FREQ_16KHZ, - DAC_SAMPLE_FREQ_44P1KHZ, - DAC_SAMPLE_FREQ_500KHZ, -}; - -typedef struct dac_device { - struct device parent; - enum dac_sample_frequence sample_freq; - uint8_t channels; - uint8_t vref; - void *tx_dma; -} dac_device_t; - -#define DAC_DEV(dev) ((adc_device_t *)dev) - -int dac_register(enum dac_index_type index, const char *name); -#ifdef __cplusplus -} -#endif -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_dma.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_dma.h deleted file mode 100644 index 6af2c755f4..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_dma.h +++ /dev/null @@ -1,262 +0,0 @@ -/** - * @file hal_dma.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __HAL_DMA__H__ -#define __HAL_DMA__H__ - -#include "hal_common.h" -#include "drv_device.h" -#include "bl808_config.h" - -#define DEVICE_CTRL_DMA_CHANNEL_GET_STATUS 0x10 -#define DEVICE_CTRL_DMA_CHANNEL_START 0x11 -#define DEVICE_CTRL_DMA_CHANNEL_STOP 0x12 -#define DEVICE_CTRL_DMA_CHANNEL_UPDATE 0x13 -#define DEVICE_CTRL_DMA_CONFIG_SI 0x14 -#define DEVICE_CTRL_DMA_CONFIG_DI 0x15 - -enum dma_index_type { -#ifdef BSP_USING_DMA0_CH0 - DMA0_CH0_INDEX, -#endif -#ifdef BSP_USING_DMA0_CH1 - DMA0_CH1_INDEX, -#endif -#ifdef BSP_USING_DMA0_CH2 - DMA0_CH2_INDEX, -#endif -#ifdef BSP_USING_DMA0_CH3 - DMA0_CH3_INDEX, -#endif -#ifdef BSP_USING_DMA0_CH4 - DMA0_CH4_INDEX, -#endif -#ifdef BSP_USING_DMA0_CH5 - DMA0_CH5_INDEX, -#endif -#ifdef BSP_USING_DMA0_CH6 - DMA0_CH6_INDEX, -#endif -#ifdef BSP_USING_DMA0_CH7 - DMA0_CH7_INDEX, -#endif -#ifdef BSP_USING_DMA1_CH0 - DMA1_CH0_INDEX, -#endif -#ifdef BSP_USING_DMA1_CH1 - DMA1_CH1_INDEX, -#endif -#ifdef BSP_USING_DMA1_CH2 - DMA1_CH2_INDEX, -#endif -#ifdef BSP_USING_DMA1_CH3 - DMA1_CH3_INDEX, -#endif -#ifdef BSP_USING_DMA1_CH4 - DMA1_CH4_INDEX, -#endif -#ifdef BSP_USING_DMA1_CH5 - DMA1_CH5_INDEX, -#endif -#ifdef BSP_USING_DMA1_CH6 - DMA1_CH6_INDEX, -#endif -#ifdef BSP_USING_DMA1_CH7 - DMA1_CH7_INDEX, -#endif -#ifdef BSP_USING_DMA2_CH0 - DMA2_CH0_INDEX, -#endif -#ifdef BSP_USING_DMA2_CH1 - DMA2_CH1_INDEX, -#endif -#ifdef BSP_USING_DMA2_CH2 - DMA2_CH2_INDEX, -#endif -#ifdef BSP_USING_DMA2_CH3 - DMA2_CH3_INDEX, -#endif -#ifdef BSP_USING_DMA2_CH4 - DMA2_CH4_INDEX, -#endif -#ifdef BSP_USING_DMA2_CH5 - DMA2_CH5_INDEX, -#endif -#ifdef BSP_USING_DMA2_CH6 - DMA2_CH6_INDEX, -#endif -#ifdef BSP_USING_DMA2_CH7 - DMA2_CH7_INDEX, -#endif - DMA_MAX_INDEX -}; - -#define dma_channel_start(dev) device_control(dev, DEVICE_CTRL_DMA_CHANNEL_START, NULL) -#define dma_channel_stop(dev) device_control(dev, DEVICE_CTRL_DMA_CHANNEL_STOP, NULL) -#define dma_channel_update(dev, list) device_control(dev, DEVICE_CTRL_DMA_CHANNEL_UPDATE, list) -#define dma_channel_check_busy(dev) device_control(dev, DEVICE_CTRL_DMA_CHANNEL_GET_STATUS, NULL) - -#define DMA_LLI_ONCE_MODE 0 -#define DMA_LLI_CYCLE_MODE 1 - -#define DMA_ADDR_INCREMENT_DISABLE 0 /*!< Addr increment mode disable */ -#define DMA_ADDR_INCREMENT_ENABLE 1 /*!< Addr increment mode enable */ - -#define DMA_TRANSFER_WIDTH_8BIT 0 -#define DMA_TRANSFER_WIDTH_16BIT 1 -#define DMA_TRANSFER_WIDTH_32BIT 2 - -#define DMA_BURST_INCR1 0 -#define DMA_BURST_INCR4 1 -#define DMA_BURST_INCR8 2 -#define DMA_BURST_INCR16 3 - -#define DMA_ADDR_UART0_TDR (0x2000A000 + 0x88) -#define DMA_ADDR_UART0_RDR (0x2000A000 + 0x8C) -#define DMA_ADDR_UART1_TDR (0x2000A100 + 0x88) -#define DMA_ADDR_UART1_RDR (0x2000A100 + 0x8C) -#define DMA_ADDR_UART2_TDR (0x2000AA00 + 0x88) -#define DMA_ADDR_UART2_RDR (0x2000AA00 + 0x8C) -#define DMA_ADDR_UART3_TDR (0x30002000 + 0x88) -#define DMA_ADDR_UART3_RDR (0x30002000 + 0x8C) -#define DMA_ADDR_UART4_TDR (0x3000E000 + 0x88) -#define DMA_ADDR_UART4_RDR (0x3000E000 + 0x8C) -#define DMA_ADDR_I2C0_TDR (0x2000a300 + 0x88) -#define DMA_ADDR_I2C0_RDR (0x2000a300 + 0x8C) -#define DMA_ADDR_I2C1_TDR (0x2000a900 + 0x88) -#define DMA_ADDR_I2C1_RDR (0x2000a900 + 0x8C) -#define DMA_ADDR_I2C2_TDR (0x30003000 + 0x88) -#define DMA_ADDR_I2C2_RDR (0x30003000 + 0x8C) -#define DMA_ADDR_I2C3_TDR (0x30004000 + 0x88) -#define DMA_ADDR_I2C3_RDR (0x30004000 + 0x8C) -#define DMA_ADDR_SPI0_TDR (0x2000a200 + 0x88) -#define DMA_ADDR_SPI0_RDR (0x2000a200 + 0x8C) -#define DMA_ADDR_SPI1_TDR (0x30008000 + 0x88) -#define DMA_ADDR_SPI1_RDR (0x30008000 + 0x8C) -#define DMA_ADDR_I2S_TDR (0x2000AB00 + 0x88) -#define DMA_ADDR_I2S_RDR (0x2000AB00 + 0x8C) -#define DMA_ADDR_AUDIO_TDR (0x20055000 + 0x94) -#define DMA_ADDR_AUDIO_RDR (0x20055000 + 0x88) -#define DMA_ADDR_ADC_RDR (0x20002000 + 0x04) -#define DMA_ADDR_DAC_TDR (0x20002000 + 0x48) -#define DMA_ADDR_DSI_RDR (0x3001a100 + 0x6C) -#define DMA_ADDR_DSI_TDR (0x3001a100 + 0x68) -#define DMA_ADDR_DBI_TDR (0x3001b000 + 0x88) - -#define DMA_REQUEST_NONE 0x00000000 /*!< DMA request peripheral:None */ -#define DMA_REQUEST_UART0_RX 0x00000000 /*!< DMA request peripheral:UART0 RX, DMA0 and DMA1 support */ -#define DMA_REQUEST_UART0_TX 0x00000001 /*!< DMA request peripheral:UART0 TX, DMA0 and DMA1 support */ -#define DMA_REQUEST_UART1_RX 0x00000002 /*!< DMA request peripheral:UART1 RX, DMA0 and DMA1 support */ -#define DMA_REQUEST_UART1_TX 0x00000003 /*!< DMA request peripheral:UART1 TX, DMA0 and DMA1 support */ -#define DMA_REQUEST_UART2_RX 0x00000004 /*!< DMA request peripheral:UART2 RX, DMA0 and DMA1 support */ -#define DMA_REQUEST_UART2_TX 0x00000005 /*!< DMA request peripheral:UART2 TX, DMA0 and DMA1 support */ -#define DMA_REQUEST_I2C0_RX 0x00000006 /*!< DMA request peripheral:I2C0 RX, DMA0 and DMA1 support */ -#define DMA_REQUEST_I2C0_TX 0x00000007 /*!< DMA request peripheral:I2C0 TX, DMA0 and DMA1 support */ -#define DMA_REQUEST_SPI0_RX 0x0000000A /*!< DMA request peripheral:SPI0 RX, DMA0 and DMA1 support */ -#define DMA_REQUEST_SPI0_TX 0x0000000B /*!< DMA request peripheral:SPI1 RX, DMA0 and DMA1 support */ -#define DMA_REQUEST_AUDIO_RX 0x0000000C /*!< DMA request peripheral:SPI1 RX, DMA0 and DMA1 support */ -#define DMA_REQUEST_AUDIO_TX 0x0000000D /*!< DMA request peripheral:SPI1 RX, DMA0 and DMA1 support */ -#define DMA_REQUEST_I2C1_RX 0x0000000E /*!< DMA request peripheral:I2C1 RX, DMA0 and DMA1 support */ -#define DMA_REQUEST_I2C1_TX 0x0000000F /*!< DMA request peripheral:I2C1 TX, DMA0 and DMA1 support */ -#define DMA_REQUEST_I2S_RX 0x00000010 /*!< DMA request peripheral:I2S RX, DMA0 and DMA1 support */ -#define DMA_REQUEST_I2S_TX 0x00000011 /*!< DMA request peripheral:I2S TX, DMA0 and DMA1 support */ -#define DMA_REQUEST_PDM_RX 0x00000012 /*!< DMA request peripheral:PDM RX, DMA0 and DMA1 support */ -#define DMA_REQUEST_ADC0 0x00000016 /*!< DMA request peripheral:GPADC RX, DMA0 and DMA1 support */ -#define DMA_REQUEST_DAC0 0x00000017 /*!< DMA request peripheral:GPADC TX, DMA0 and DMA1 support */ - -#define DMA_REQUEST_UART3_RX 0x0000000 /*!< DMA request peripheral:UART3 RX, only DMA2 support */ -#define DMA_REQUEST_UART3_TX 0x0000001 /*!< DMA request peripheral:UART3 TX, only DMA2 support */ -#define DMA_REQUEST_SPI1_RX 0x0000002 /*!< DMA request peripheral:SPI1 RX, only DMA2 support */ -#define DMA_REQUEST_SPI1_TX 0x0000003 /*!< DMA request peripheral:SPI1 TX, only DMA2 support */ -#define DMA_REQUEST_UART4_RX 0x0000004 /*!< DMA request peripheral:UART4 RX, only DMA2 support */ -#define DMA_REQUEST_UART4_TX 0x0000005 /*!< DMA request peripheral:UART4 TX, only DMA2 support */ -#define DMA_REQUEST_I2C2_RX 0x0000006 /*!< DMA request peripheral:I2C2 RX, only DMA2 support */ -#define DMA_REQUEST_I2C2_TX 0x0000007 /*!< DMA request peripheral:I2C2 TX, only DMA2 support */ -#define DMA_REQUEST_I2C3_RX 0x0000008 /*!< DMA request peripheral:I2C3 RX, only DMA2 support */ -#define DMA_REQUEST_I2C3_TX 0x0000009 /*!< DMA request peripheral:I2C3 TX, only DMA2 support */ -#define DMA_REQUEST_DSI_RX 0x000000A /*!< DMA request peripheral:DSI RX, only DMA2 support */ -#define DMA_REQUEST_DSI_TX 0x000000B /*!< DMA request peripheral:DSI TX, only DMA2 support */ -#define DMA_REQUEST_DBI_TX 0x0000016 /*!< DMA request peripheral:DBI TX, only DMA2 support */ - -/** - * @brief DMA transfer direction type definition - */ -typedef enum { - DMA_MEMORY_TO_MEMORY = 0, /*!< DMA transfer type:memory to memory */ - DMA_MEMORY_TO_PERIPH, /*!< DMA transfer type:memory to peripheral */ - DMA_PERIPH_TO_MEMORY, /*!< DMA transfer type:peripheral to memory */ - DMA_PERIPH_TO_PERIPH, /*!< DMA transfer type:peripheral to peripheral */ -} dma_transfer_dir_type; - -typedef union { - struct - { - uint32_t TransferSize : 12; /* [11: 0], r/w, 0x0 */ - uint32_t SBSize : 2; /* [13:12], r/w, 0x1 */ - uint32_t dst_min_mode : 1; /* [ 14], r/w, 0x0 */ - uint32_t DBSize : 2; /* [16:15], r/w, 0x1 */ - uint32_t dst_add_mode : 1; /* [ 17], r/w, 0x0 */ - uint32_t SWidth : 2; /* [19:18], r/w, 0x2 */ - uint32_t reserved_20 : 1; /* [ 20], rsvd, 0x0 */ - uint32_t DWidth : 2; /* [22:21], r/w, 0x2 */ - uint32_t fix_cnt : 2; /* [24:23], r/w, 0x0 */ - uint32_t SLargerD : 1; /* [ 25], r/w, 0x0 */ - uint32_t SI : 1; /* [ 26], r/w, 0x1 */ - uint32_t DI : 1; /* [ 27], r/w, 0x1 */ - uint32_t Prot : 3; /* [30:28], r/w, 0x0 */ - uint32_t I : 1; /* [ 31], r/w, 0x0 */ - } bits; - uint32_t WORD; -} dma_control_data_t; - -typedef struct -{ - uint32_t src_addr; - uint32_t dst_addr; - uint32_t nextlli; - dma_control_data_t cfg; -} dma_lli_ctrl_t; - -typedef struct dma_device { - struct device parent; - uint8_t id; - uint8_t ch; - uint8_t transfer_mode; - uint8_t direction; - uint32_t src_req; - uint32_t dst_req; - uint8_t src_addr_inc; - uint8_t dst_addr_inc; - uint8_t src_burst_size; - uint8_t dst_burst_size; - uint8_t src_width; - uint8_t dst_width; - dma_lli_ctrl_t *lli_cfg;/* private param*/ -} dma_device_t; - -#define DMA_DEV(dev) ((dma_device_t *)dev) - -int dma_register(enum dma_index_type index, const char *name); -int dma_allocate_register(const char *name); -int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_t transfer_size); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_dsi.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_dsi.h deleted file mode 100644 index 0b196b8986..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_dsi.h +++ /dev/null @@ -1,574 +0,0 @@ -/** - * @file hal_dsi.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __HAL_DSI__H__ -#define __HAL_DSI__H__ - -#include "hal_common.h" -#include "drv_device.h" -#include "bl808_config.h" - -#define DSI_DEV_NAME_SIZE 20 -#define u8 uint8_t -#define u16 uint16_t -#define u32 uint32_t -#define __be16 uint16_t -/* VESA Display Stream Compression DSC 1.2 constants */ -#define DSC_NUM_BUF_RANGES 15 - -enum mipi_dsi_index_type { - DSI0_INDEX, - DSI_MAX_INDEX -}; - -struct mipi_dsi_host; -struct mipi_dsi_device; -struct drm_dsc_picture_parameter_set; - -/** - * struct drm_dsc_picture_parameter_set - Represents 128 bytes of - * Picture Parameter Set - * - * The VESA DSC standard defines picture parameter set (PPS) which display - * stream compression encoders must communicate to decoders. - * The PPS is encapsulated in 128 bytes (PPS 0 through PPS 127). The fields in - * this structure are as per Table 4.1 in Vesa DSC specification v1.1/v1.2. - * The PPS fields that span over more than a byte should be stored in Big Endian - * format. - */ -struct drm_dsc_picture_parameter_set { - /** - * @dsc_version: - * PPS0[3:0] - dsc_version_minor: Contains Minor version of DSC - * PPS0[7:4] - dsc_version_major: Contains major version of DSC - */ - u8 dsc_version; - /** - * @pps_identifier: - * PPS1[7:0] - Application specific identifier that can be - * used to differentiate between different PPS tables. - */ - u8 pps_identifier; - /** - * @pps_reserved: - * PPS2[7:0]- RESERVED Byte - */ - u8 pps_reserved; - /** - * @pps_3: - * PPS3[3:0] - linebuf_depth: Contains linebuffer bit depth used to - * generate the bitstream. (0x0 - 16 bits for DSC 1.2, 0x8 - 8 bits, - * 0xA - 10 bits, 0xB - 11 bits, 0xC - 12 bits, 0xD - 13 bits, - * 0xE - 14 bits for DSC1.2, 0xF - 14 bits for DSC 1.2. - * PPS3[7:4] - bits_per_component: Bits per component for the original - * pixels of the encoded picture. - * 0x0 = 16bpc (allowed only when dsc_version_minor = 0x2) - * 0x8 = 8bpc, 0xA = 10bpc, 0xC = 12bpc, 0xE = 14bpc (also - * allowed only when dsc_minor_version = 0x2) - */ - u8 pps_3; - /** - * @pps_4: - * PPS4[1:0] -These are the most significant 2 bits of - * compressed BPP bits_per_pixel[9:0] syntax element. - * PPS4[2] - vbr_enable: 0 = VBR disabled, 1 = VBR enabled - * PPS4[3] - simple_422: Indicates if decoder drops samples to - * reconstruct the 4:2:2 picture. - * PPS4[4] - Convert_rgb: Indicates if DSC color space conversion is - * active. - * PPS4[5] - blobk_pred_enable: Indicates if BP is used to code any - * groups in picture - * PPS4[7:6] - Reseved bits - */ - u8 pps_4; - /** - * @bits_per_pixel_low: - * PPS5[7:0] - This indicates the lower significant 8 bits of - * the compressed BPP bits_per_pixel[9:0] element. - */ - u8 bits_per_pixel_low; - /** - * @pic_height: - * PPS6[7:0], PPS7[7:0] -pic_height: Specifies the number of pixel rows - * within the raster. - */ - __be16 pic_height; - /** - * @pic_width: - * PPS8[7:0], PPS9[7:0] - pic_width: Number of pixel columns within - * the raster. - */ - __be16 pic_width; - /** - * @slice_height: - * PPS10[7:0], PPS11[7:0] - Slice height in units of pixels. - */ - __be16 slice_height; - /** - * @slice_width: - * PPS12[7:0], PPS13[7:0] - Slice width in terms of pixels. - */ - __be16 slice_width; - /** - * @chunk_size: - * PPS14[7:0], PPS15[7:0] - Size in units of bytes of the chunks - * that are used for slice multiplexing. - */ - __be16 chunk_size; - /** - * @initial_xmit_delay_high: - * PPS16[1:0] - Most Significant two bits of initial transmission delay. - * It specifies the number of pixel times that the encoder waits before - * transmitting data from its rate buffer. - * PPS16[7:2] - Reserved - */ - u8 initial_xmit_delay_high; - /** - * @initial_xmit_delay_low: - * PPS17[7:0] - Least significant 8 bits of initial transmission delay. - */ - u8 initial_xmit_delay_low; - /** - * @initial_dec_delay: - * - * PPS18[7:0], PPS19[7:0] - Initial decoding delay which is the number - * of pixel times that the decoder accumulates data in its rate buffer - * before starting to decode and output pixels. - */ - __be16 initial_dec_delay; - /** - * @pps20_reserved: - * - * PPS20[7:0] - Reserved - */ - u8 pps20_reserved; - /** - * @initial_scale_value: - * PPS21[5:0] - Initial rcXformScale factor used at beginning - * of a slice. - * PPS21[7:6] - Reserved - */ - u8 initial_scale_value; - /** - * @scale_increment_interval: - * PPS22[7:0], PPS23[7:0] - Number of group times between incrementing - * the rcXformScale factor at end of a slice. - */ - __be16 scale_increment_interval; - /** - * @scale_decrement_interval_high: - * PPS24[3:0] - Higher 4 bits indicating number of group times between - * decrementing the rcXformScale factor at beginning of a slice. - * PPS24[7:4] - Reserved - */ - u8 scale_decrement_interval_high; - /** - * @scale_decrement_interval_low: - * PPS25[7:0] - Lower 8 bits of scale decrement interval - */ - u8 scale_decrement_interval_low; - /** - * @pps26_reserved: - * PPS26[7:0] - */ - u8 pps26_reserved; - /** - * @first_line_bpg_offset: - * PPS27[4:0] - Number of additional bits that are allocated - * for each group on first line of a slice. - * PPS27[7:5] - Reserved - */ - u8 first_line_bpg_offset; - /** - * @nfl_bpg_offset: - * PPS28[7:0], PPS29[7:0] - Number of bits including frac bits - * deallocated for each group for groups after the first line of slice. - */ - __be16 nfl_bpg_offset; - /** - * @slice_bpg_offset: - * PPS30, PPS31[7:0] - Number of bits that are deallocated for each - * group to enforce the slice constraint. - */ - __be16 slice_bpg_offset; - /** - * @initial_offset: - * PPS32,33[7:0] - Initial value for rcXformOffset - */ - __be16 initial_offset; - /** - * @final_offset: - * PPS34,35[7:0] - Maximum end-of-slice value for rcXformOffset - */ - __be16 final_offset; - /** - * @flatness_min_qp: - * PPS36[4:0] - Minimum QP at which flatness is signaled and - * flatness QP adjustment is made. - * PPS36[7:5] - Reserved - */ - u8 flatness_min_qp; - /** - * @flatness_max_qp: - * PPS37[4:0] - Max QP at which flatness is signalled and - * the flatness adjustment is made. - * PPS37[7:5] - Reserved - */ - u8 flatness_max_qp; - /** - * @rc_model_size: - * PPS38,39[7:0] - Number of bits within RC Model. - */ - __be16 rc_model_size; - /** - * @rc_edge_factor: - * PPS40[3:0] - Ratio of current activity vs, previous - * activity to determine presence of edge. - * PPS40[7:4] - Reserved - */ - u8 rc_edge_factor; - /** - * @rc_quant_incr_limit0: - * PPS41[4:0] - QP threshold used in short term RC - * PPS41[7:5] - Reserved - */ - u8 rc_quant_incr_limit0; - /** - * @rc_quant_incr_limit1: - * PPS42[4:0] - QP threshold used in short term RC - * PPS42[7:5] - Reserved - */ - u8 rc_quant_incr_limit1; - /** - * @rc_tgt_offset: - * PPS43[3:0] - Lower end of the variability range around the target - * bits per group that is allowed by short term RC. - * PPS43[7:4]- Upper end of the variability range around the target - * bits per group that i allowed by short term rc. - */ - u8 rc_tgt_offset; - /** - * @rc_buf_thresh: - * PPS44[7:0] - PPS57[7:0] - Specifies the thresholds in RC model for - * the 15 ranges defined by 14 thresholds. - */ - u8 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1]; - /** - * @rc_range_parameters: - * PPS58[7:0] - PPS87[7:0] - * Parameters that correspond to each of the 15 ranges. - */ - __be16 rc_range_parameters[DSC_NUM_BUF_RANGES]; - /** - * @native_422_420: - * PPS88[0] - 0 = Native 4:2:2 not used - * 1 = Native 4:2:2 used - * PPS88[1] - 0 = Native 4:2:0 not use - * 1 = Native 4:2:0 used - * PPS88[7:2] - Reserved 6 bits - */ - u8 native_422_420; - /** - * @second_line_bpg_offset: - * PPS89[4:0] - Additional bits/group budget for the - * second line of a slice in Native 4:2:0 mode. - * Set to 0 if DSC minor version is 1 or native420 is 0. - * PPS89[7:5] - Reserved - */ - u8 second_line_bpg_offset; - /** - * @nsl_bpg_offset: - * PPS90[7:0], PPS91[7:0] - Number of bits that are deallocated - * for each group that is not in the second line of a slice. - */ - __be16 nsl_bpg_offset; - /** - * @second_line_offset_adj: - * PPS92[7:0], PPS93[7:0] - Used as offset adjustment for the second - * line in Native 4:2:0 mode. - */ - __be16 second_line_offset_adj; - /** - * @pps_long_94_reserved: - * PPS 94, 95, 96, 97 - Reserved - */ - u32 pps_long_94_reserved; - /** - * @pps_long_98_reserved: - * PPS 98, 99, 100, 101 - Reserved - */ - u32 pps_long_98_reserved; - /** - * @pps_long_102_reserved: - * PPS 102, 103, 104, 105 - Reserved - */ - u32 pps_long_102_reserved; - /** - * @pps_long_106_reserved: - * PPS 106, 107, 108, 109 - reserved - */ - u32 pps_long_106_reserved; - /** - * @pps_long_110_reserved: - * PPS 110, 111, 112, 113 - reserved - */ - u32 pps_long_110_reserved; - /** - * @pps_long_114_reserved: - * PPS 114 - 117 - reserved - */ - u32 pps_long_114_reserved; - /** - * @pps_long_118_reserved: - * PPS 118 - 121 - reserved - */ - u32 pps_long_118_reserved; - /** - * @pps_long_122_reserved: - * PPS 122- 125 - reserved - */ - u32 pps_long_122_reserved; - /** - * @pps_short_126_reserved: - * PPS 126, 127 - reserved - */ - __be16 pps_short_126_reserved; -} __attribute__((packed)); - -/* request ACK from peripheral */ -#define MIPI_DSI_MSG_REQ_ACK BIT(0) -/* use Low Power Mode to transmit message */ -#define MIPI_DSI_MSG_USE_LPM BIT(1) - -/** - * struct mipi_dsi_msg - read/write DSI buffer - * @channel: virtual channel id - * @type: payload data type - * @flags: flags controlling this message transmission - * @tx_len: length of @tx_buf - * @tx_buf: data to be written - * @rx_len: length of @rx_buf - * @rx_buf: data to be read, or NULL - */ -struct mipi_dsi_msg { - u8 channel; - u8 type; - u16 flags; - - size_t tx_len; - const void *tx_buf; - - size_t rx_len; - void *rx_buf; -}; - -bool mipi_dsi_packet_format_is_short(u8 type); -bool mipi_dsi_packet_format_is_long(u8 type); - -/** - * struct mipi_dsi_packet - represents a MIPI DSI packet in protocol format - * @size: size (in bytes) of the packet - * @header: the four bytes that make up the header (Data ID, Word Count or - * Packet Data, and ECC) - * @payload_length: number of bytes in the payload - * @payload: a pointer to a buffer containing the payload, if any - */ -struct mipi_dsi_packet { - size_t size; - u8 header[4]; - size_t payload_length; - const u8 *payload; -}; - -int mipi_dsi_create_packet(struct mipi_dsi_packet *packet, - const struct mipi_dsi_msg *msg); -/** - * struct mipi_dsi_host_ops - DSI bus operations - * @attach: attach DSI device to DSI host - * @detach: detach DSI device from DSI host - * @transfer: transmit a DSI packet - * - * DSI packets transmitted by .transfer() are passed in as mipi_dsi_msg - * structures. This structure contains information about the type of packet - * being transmitted as well as the transmit and receive buffers. When an - * error is encountered during transmission, this function will return a - * negative error code. On success it shall return the number of bytes - * transmitted for write packets or the number of bytes received for read - * packets. - * - * Note that typically DSI packet transmission is atomic, so the .transfer() - * function will seldomly return anything other than the number of bytes - * contained in the transmit buffer on success. - */ -struct mipi_dsi_host_ops { - int (*attach)(struct mipi_dsi_host *host, - const struct mipi_dsi_device *dsi); - int (*detach)(struct mipi_dsi_host *host, - const struct mipi_dsi_device *dsi); - size_t (*transfer)(struct mipi_dsi_host *host, - const struct mipi_dsi_msg *msg); -}; - -/** - * struct mipi_dsi_host - DSI host device - * @dev: driver model device node for this DSI host - * @ops: DSI host operations - * @list: list management - */ -struct mipi_dsi_host { - //struct device *dev; - const struct mipi_dsi_host_ops *ops; - //struct list_head list; -}; - -/* DSI mode flags */ - -/* video mode */ -#define MIPI_DSI_MODE_VIDEO BIT(0) -/* video burst mode */ -#define MIPI_DSI_MODE_VIDEO_BURST BIT(1) -/* video pulse mode */ -#define MIPI_DSI_MODE_VIDEO_SYNC_PULSE BIT(2) -/* enable auto vertical count mode */ -#define MIPI_DSI_MODE_VIDEO_AUTO_VERT BIT(3) -/* enable hsync-end packets in vsync-pulse and v-porch area */ -#define MIPI_DSI_MODE_VIDEO_HSE BIT(4) -/* disable hfront-porch area */ -#define MIPI_DSI_MODE_VIDEO_HFP BIT(5) -/* disable hback-porch area */ -#define MIPI_DSI_MODE_VIDEO_HBP BIT(6) -/* disable hsync-active area */ -#define MIPI_DSI_MODE_VIDEO_HSA BIT(7) -/* flush display FIFO on vsync pulse */ -#define MIPI_DSI_MODE_VSYNC_FLUSH BIT(8) -/* disable EoT packets in HS mode */ -#define MIPI_DSI_MODE_EOT_PACKET BIT(9) -/* device supports non-continuous clock behavior (DSI spec 5.6.1) */ -#define MIPI_DSI_CLOCK_NON_CONTINUOUS BIT(10) -/* transmit data in low power */ -#define MIPI_DSI_MODE_LPM BIT(11) - -enum mipi_dsi_pixel_format { - MIPI_DSI_DATA_FMT_YUV422 = 0x2C, /*!< DSI data format:YUV 422 8bits */ - MIPI_DSI_DATA_FMT_RGB565 = 0x0E, /*!< DSI data format:RGB565 */ - MIPI_DSI_DATA_FMT_RGB666 = 0x2E, /*!< DSI data format:RGB666 */ - MIPI_DSI_DATA_FMT_RGB888 = 0x3E, /*!< DSI data format:RGB888 */ -}; - -/** - * struct mipi_dsi_device_info - template for creating a mipi_dsi_device - * @type: DSI peripheral chip type - * @channel: DSI virtual channel assigned to peripheral - * @node: pointer to OF device node or NULL - * - * This is populated and passed to mipi_dsi_device_new to create a new - * DSI device - */ -struct mipi_dsi_device_info { - char type[DSI_DEV_NAME_SIZE]; - u32 channel; - struct device_node *node; -}; - -/** - * struct mipi_dsi_device - DSI peripheral device - * @host: DSI host for this peripheral - * @dev: driver model device node for this peripheral - * @name: DSI peripheral chip type - * @channel: virtual channel assigned to the peripheral - * @format: pixel format for video mode - * @lanes: number of active data lanes - * @mode_flags: DSI operation mode related flags - * @hs_rate: maximum lane frequency for high speed mode in hertz, this should - * be set to the real limits of the hardware, zero is only accepted for - * legacy drivers - * @lp_rate: maximum lane frequency for low power mode in hertz, this should - * be set to the real limits of the hardware, zero is only accepted for - * legacy drivers - */ -typedef struct mipi_dsi_device { - struct device dev; - struct mipi_dsi_host *host; - - char name[DSI_DEV_NAME_SIZE]; - unsigned int channel; - unsigned int lanes; - enum mipi_dsi_pixel_format format; - unsigned long mode_flags; - unsigned long hs_rate; - unsigned long lp_rate; -} mipi_dsi_device_t; - -/** - * enum mipi_dsi_dcs_tear_mode - Tearing Effect Output Line mode - * @MIPI_DSI_DCS_TEAR_MODE_VBLANK: the TE output line consists of V-Blanking - * information only - * @MIPI_DSI_DCS_TEAR_MODE_VHBLANK : the TE output line consists of both - * V-Blanking and H-Blanking information - */ -enum mipi_dsi_dcs_tear_mode { - MIPI_DSI_DCS_TEAR_MODE_VBLANK, - MIPI_DSI_DCS_TEAR_MODE_VHBLANK, -}; - -int mipi_dsi_controller_init(const struct mipi_dsi_device *dsi); -int mipi_dsi_shutdown_peripheral(const struct mipi_dsi_device *dsi); -int mipi_dsi_turn_on_peripheral(const struct mipi_dsi_device *dsi); -int mipi_dsi_set_maximum_return_packet_size(const struct mipi_dsi_device *dsi, - u16 value); -int mipi_dsi_compression_mode(const struct mipi_dsi_device *dsi, bool enable); -int mipi_dsi_picture_parameter_set(const struct mipi_dsi_device *dsi, - const struct drm_dsc_picture_parameter_set *pps); - -int mipi_dsi_generic_write(const struct mipi_dsi_device *dsi, const void *payload, - size_t size); -int mipi_dsi_generic_read(const struct mipi_dsi_device *dsi, const void *params, - size_t num_params, void *data, size_t size); -int mipi_dsi_dcs_write_buffer(const struct mipi_dsi_device *dsi, - const void *data, size_t len); -int mipi_dsi_dcs_write(const struct mipi_dsi_device *dsi, u8 cmd, - const void *data, size_t len); -int mipi_dsi_dcs_read(const struct mipi_dsi_device *dsi, u8 cmd, void *data, - size_t len); -int mipi_dsi_dcs_nop(const struct mipi_dsi_device *dsi); -int mipi_dsi_dcs_soft_reset(const struct mipi_dsi_device *dsi); -int mipi_dsi_dcs_get_power_mode(const struct mipi_dsi_device *dsi, u8 *mode); -int mipi_dsi_dcs_get_pixel_format(const struct mipi_dsi_device *dsi, u8 *format); -int mipi_dsi_dcs_enter_sleep_mode(const struct mipi_dsi_device *dsi); -int mipi_dsi_dcs_exit_sleep_mode(const struct mipi_dsi_device *dsi); -int mipi_dsi_dcs_set_display_off(const struct mipi_dsi_device *dsi); -int mipi_dsi_dcs_set_display_on(const struct mipi_dsi_device *dsi); -int mipi_dsi_dcs_set_column_address(const struct mipi_dsi_device *dsi, u16 start, - u16 end); -int mipi_dsi_dcs_set_page_address(const struct mipi_dsi_device *dsi, u16 start, - u16 end); -int mipi_dsi_dcs_set_tear_off(const struct mipi_dsi_device *dsi); -int mipi_dsi_dcs_set_tear_on(const struct mipi_dsi_device *dsi, - enum mipi_dsi_dcs_tear_mode mode); -int mipi_dsi_dcs_set_pixel_format(const struct mipi_dsi_device *dsi, u8 format); -int mipi_dsi_dcs_set_tear_scanline(const struct mipi_dsi_device *dsi, u16 scanline); -int mipi_dsi_dcs_set_display_brightness(const struct mipi_dsi_device *dsi, - u16 brightness); -int mipi_dsi_dcs_get_display_brightness(const struct mipi_dsi_device *dsi, - u16 *brightness); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_emac.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_emac.h deleted file mode 100644 index 0af6f8a69a..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_emac.h +++ /dev/null @@ -1,107 +0,0 @@ -/** - * @file hal_emac.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ - -#ifndef __HAL_EMAC_H__ -#define __HAL_EMAC_H__ - -#include "hal_common.h" -#include "drv_device.h" -#include "bl808_config.h" -#include "bl808_emac.h" - -typedef struct emac_device { - struct device parent; - uint8_t mac_addr[6]; /*!< mac address */ -} emac_device_t; - -/** - * @brief EMAC PHY configuration type definition - */ -typedef struct -{ - uint8_t auto_negotiation; /*!< Speed and mode auto negotiation */ - uint8_t full_duplex; /*!< Duplex mode */ -#define PHY_STATE_DOWN (0) /* PHY is not usable */ -#define PHY_STATE_READY (1) /* PHY is OK, wait for controller */ -#define PHY_STATE_UP (2) /* Network is ready for TX/RX */ -#define PHY_STATE_RUNNING (3) /* working */ -#define PHY_STATE_NOLINK (4) /* no cable connected */ -#define PHY_STATE_STOPPED (5) /* PHY has been stopped */ -#define PHY_STATE_TESTING (6) /* in test mode */ - uint8_t phy_state; /*!< down,ready,up,running,nolink,halted */ - uint8_t use_irq; /*!< 0: no IRQ used */ - uint16_t speed; /*!< Speed mode */ - uint16_t phy_address; /*!< PHY address */ - uint32_t phy_id; /*!< PHY OUI */ -} emac_phy_cfg_t; - -#define EMAC_NORMAL_PACKET (uint32_t)(0) -#define EMAC_FRAGMENT_PACKET (uint32_t)(0x01) -#define EMAC_NOCOPY_PACKET (uint32_t)(0x02) - -#ifndef ETH_TX_BUFFER_SIZE -#define ETH_TX_BUFFER_SIZE (ETH_MAX_PACKET_SIZE) -#endif - -#ifndef ETH_RX_BUFFER_SIZE -#define ETH_RX_BUFFER_SIZE (ETH_MAX_PACKET_SIZE) -#endif - -#define EMAC_TX_COMMON_FLAGS (EMAC_BD_FIELD_MSK(TX_RD) | \ - EMAC_BD_FIELD_MSK(TX_IRQ) | \ - EMAC_BD_FIELD_MSK(TX_PAD) | \ - EMAC_BD_FIELD_MSK(TX_CRC) | \ - EMAC_BD_FIELD_MSK(TX_EOF)) - -#define EMAC_RX_COMMON_FLAGS (ETH_MAX_PACKET_SIZE << 16) | \ - EMAC_BD_FIELD_MSK(RX_IRQ) ) - -typedef enum _BD_TYPE_ { - EMAC_BD_TYPE_INVLAID, - EMAC_BD_TYPE_TX, - EMAC_BD_TYPE_RX, - EMAC_BD_TYPE_NONE, - EMAC_BD_TYPE_MAX = 0x7FFFFFFF -} EMAC_BD_TYPE_e; - -int emac_init(emac_device_t *emac_cfg); -int emac_bd_init(uint8_t *ethTxBuff, uint8_t txBufCount, uint8_t *ethRxBuff, uint8_t rxBufCount); -int emac_bd_fragment_support(void); -int emac_bd_tx_enqueue(uint32_t flags, uint32_t len, const uint8_t *data_in); -int emac_bd_rx_dequeue(uint32_t flags, uint32_t *len, uint8_t *data_out); -__WEAK void emac_rx_done_callback_app(void); -__WEAK void emac_rx_error_callback_app(void); -__WEAK void emac_rx_busy_callback_app(void); -__WEAK void emac_tx_error_callback_app(void); -__WEAK void emac_tx_done_callback_app(void); -int emac_phy_set_address(uint16_t phyAddress); -int emac_phy_config_full_duplex(uint8_t fullDuplex); -int emac_phy_reg_read(uint16_t phyReg, uint16_t *regValue); -int emac_phy_reg_write(uint16_t phyReg, uint16_t regValue); -int emac_stop(void); -int emac_start(void); -int emac_start_tx(void); -int emac_stop_tx(void); -int emac_start_rx(void); -int emac_stop_rx(void); -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_flash.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_flash.h deleted file mode 100644 index be350dd694..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_flash.h +++ /dev/null @@ -1,42 +0,0 @@ -/** - * @file hal_flash.h - * @brief - * - * Copyright 2019-2030 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __HAL_FLASH__H__ -#define __HAL_FLASH__H__ - -#include "hal_common.h" -#include "bl808_sflash.h" - -#define FLASH_NOT_DETECT 0x10 -#define BL_FLASH_XIP_BASE 0//BL808_FLASH_XIP_BASE - -uint32_t flash_get_jedecid(void); -BL_Err_Type flash_init(void); -BL_Err_Type flash_read_jedec_id(uint8_t *data); -BL_Err_Type flash_read_via_xip(uint32_t addr, uint8_t *data, uint32_t len); -BL_Err_Type flash_read(uint32_t addr, uint8_t *data, uint32_t len); -BL_Err_Type flash_write(uint32_t addr, uint8_t *data, uint32_t len); -BL_Err_Type flash_erase(uint32_t startaddr, uint32_t len); -BL_Err_Type flash_set_cache(uint8_t cont_read, uint8_t cache_enable, uint8_t cache_way_disable, uint32_t flash_offset); -BL_Err_Type flash_get_cfg(uint8_t **cfg_addr, uint32_t *len); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_gpio.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_gpio.h deleted file mode 100644 index e7459f3ca3..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_gpio.h +++ /dev/null @@ -1,103 +0,0 @@ -/** - * @file hal_gpio.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __HAL_GPIO__H__ -#define __HAL_GPIO__H__ - -#include "hal_common.h" -#include "drv_device.h" -#include "bl808_config.h" - -enum gpio_pin_type { - GPIO_PIN_0 = 0, - GPIO_PIN_1, - GPIO_PIN_2, - GPIO_PIN_3, - GPIO_PIN_4, - GPIO_PIN_5, - GPIO_PIN_6, - GPIO_PIN_7, - GPIO_PIN_8, - GPIO_PIN_9, - GPIO_PIN_10, - GPIO_PIN_11, - GPIO_PIN_12, - GPIO_PIN_13, - GPIO_PIN_14, - GPIO_PIN_15, - GPIO_PIN_16, - GPIO_PIN_17, - GPIO_PIN_18, - GPIO_PIN_19, - GPIO_PIN_20, - GPIO_PIN_21, - GPIO_PIN_22, - GPIO_PIN_23, - GPIO_PIN_24, - GPIO_PIN_25, - GPIO_PIN_26, - GPIO_PIN_27, - GPIO_PIN_28, - GPIO_PIN_29, - GPIO_PIN_30, - GPIO_PIN_31, - GPIO_PIN_32, - GPIO_PIN_33, - GPIO_PIN_34, - GPIO_PIN_35, - GPIO_PIN_36, - GPIO_PIN_37, - GPIO_PIN_38, - GPIO_PIN_39, - GPIO_PIN_40, - GPIO_PIN_41, - GPIO_PIN_42, - GPIO_PIN_43, - GPIO_PIN_44, - GPIO_PIN_45, - GPIO_PIN_MAX, -}; - -#define GPIO_OUTPUT_MODE 0 -#define GPIO_OUTPUT_PP_MODE 1 -#define GPIO_OUTPUT_PD_MODE 2 -#define GPIO_INPUT_MODE 3 -#define GPIO_INPUT_PP_MODE 4 -#define GPIO_INPUT_PD_MODE 5 -#define GPIO_ASYNC_RISING_TRIGER_INT_MODE 6 -#define GPIO_ASYNC_FALLING_TRIGER_INT_MODE 7 -#define GPIO_ASYNC_HIGH_LEVEL_INT_MODE 8 -#define GPIO_ASYNC_LOW_LEVEL_INT_MODE 9 -#define GPIO_SYNC_RISING_TRIGER_INT_MODE 10 -#define GPIO_SYNC_FALLING_TRIGER_INT_MODE 11 -#define GPIO_SYNC_RISING_FALLING_TRIGER_INT_MODE 12 -#define GPIO_SYNC_HIGH_LEVEL_INT_MODE 13 -#define GPIO_SYNC_LOW_LEVEL_INT_MODE 14 -#define GPIO_HZ_MODE 15 - -void gpio_set_mode(uint32_t pin, uint32_t mode); -void gpio_write(uint32_t pin, uint32_t value); -void gpio_toggle(uint32_t pin); -int gpio_read(uint32_t pin); -void gpio_attach_irq(uint32_t pin, void (*cbfun)(uint32_t pin)); -void gpio_irq_enable(uint32_t pin, uint8_t enabled); -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_i2c.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_i2c.h deleted file mode 100644 index 028ef6888a..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_i2c.h +++ /dev/null @@ -1,77 +0,0 @@ -/** - * @file hal_i2c.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __HAL_I2C__H__ -#define __HAL_I2C__H__ - -#include "hal_common.h" -#include "drv_device.h" -#include "bl808_config.h" - -enum i2c_index_type { -#ifdef BSP_USING_I2C0 - I2C0_INDEX, -#endif -#ifdef BSP_USING_I2C1 - I2C1_INDEX, -#endif -#ifdef BSP_USING_I2C2 - I2C2_INDEX, -#endif -#ifdef BSP_USING_I2C3 - I2C3_INDEX, -#endif - I2C_MAX_INDEX -}; - -#define I2C_WR 0x0000 -#define I2C_RD 0x0001 -#define I2C_RW_MASK 0x0001 - -#define SUB_ADDR_0BYTE 0x0010 -#define SUB_ADDR_1BYTE 0x0020 -#define SUB_ADDR_2BYTE 0x0040 - -#define I2C_HW_MODE 0 -#define I2C_SW_MODE 1 - -typedef struct i2c_msg { - uint8_t slaveaddr; - uint32_t subaddr; - uint16_t flags; - uint16_t len; - uint8_t *buf; -} i2c_msg_t; - -typedef struct i2c_device { - struct device parent; - uint8_t id; - uint8_t mode; - uint32_t phase; -} i2c_device_t; - -#define I2C_DEV(dev) ((i2c_device_t *)dev) - -int i2c_register(enum i2c_index_type index, const char *name); -int i2c_transfer(struct device *dev, i2c_msg_t msgs[], uint32_t num); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_i2s.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_i2s.h deleted file mode 100644 index ec9ee66434..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_i2s.h +++ /dev/null @@ -1,117 +0,0 @@ -/** - * @file hal_i2s.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __HAL_I2S__H__ -#define __HAL_I2S__H__ - -#include "hal_common.h" -#include "drv_device.h" -#include "bl808_config.h" - -#define I2S_GET_TX_FIFO_CMD 0x10 -#define I2S_GET_RX_FIFO_CMD 0x11 -#define DEVICE_CTRL_I2S_ATTACH_TX_DMA 0x12 -#define DEVICE_CTRL_I2S_ATTACH_RX_DMA 0x13 - -enum i2s_index_type { -#ifdef BSP_USING_I2S0 - I2S0_INDEX, -#endif - I2S_MAX_INDEX -}; - -#define I2S_DEFAULT_RTO_TIMEOUT 15 - -/*! - * @brief I2S mode type settings - * - * This enumeration defines the I2S mode type - */ -typedef enum { - I2S_MODE_STD, /*!< I2S STD Mode */ - I2S_MODE_LEFT, /*!< Left-Justified Mode */ - I2S_MODE_RIGHT, /*!< Right-Justified Mode */ - I2S_MODE_DSP_A, /*!< DSP/PCM Mode A*/ - I2S_MODE_DSP_B, /*!< DSP/PCM Mode B*/ -} interface_mode_t; - -/*! - * @brief I2S frame size settings - * - * This enumeration defines the frame size type - */ -typedef enum { - I2S_FRAME_LEN_8 = 1, /*!< I2S frame size 8 bits */ - I2S_FRAME_LEN_16 = 2, /*!< I2S frame size 16 bits */ - I2S_FRAME_LEN_24 = 3, /*!< I2S frame size 24 bits */ - I2S_FRAME_LEN_32 = 4, /*!< I2S frame size 32 bits */ -} i2s_frame_size_t; - -/*! - * @brief I2S data size settings - * - * This enumeration defines the data size type - */ -typedef enum { - I2S_DATA_LEN_8 = 1, /*!< I2S data size 8 bits */ - I2S_DATA_LEN_16 = 2, /*!< I2S data size 16 bits */ - I2S_DATA_LEN_24 = 3, /*!< I2S data size 24 bits */ - I2S_DATA_LEN_32 = 4, /*!< I2S data size 32 bits */ -} i2s_data_size_t; - -/*! - * @brief I2S frame channel settings - * - * This enumeration defines the frame channel mode type - */ -typedef enum { - I2S_FS_CHANNELS_NUM_MONO = 1, /*!< I2S frame is for 1 channels */ - I2S_FS_CHANNELS_NUM_2 = 2, /*!< I2S frame is for 2 channels */ - I2S_FS_CHANNELS_NUM_3 = 3, /*!< I2S frame is for 3 channels, DSP mode only, frame_size must equal data_size*/ - I2S_FS_CHANNELS_NUM_4 = 4, /*!< I2S frame is for 4 channels, DSP mode only, frame_size must equal data_size*/ -} i2s_channel_num_t; - -typedef enum { - I2S_MODE_MASTER = 0, /*!< I2S as master */ - I2S_MODE_SLAVE, /*!< I2S as slave */ -} i2s_mode_t; - -typedef struct i2s_device { - struct device parent; - uint8_t id; - - i2s_mode_t iis_mode; - interface_mode_t interface_mode; - uint32_t sampl_freq_hz; /*!< I2S sample data frequency in Hz */ - i2s_channel_num_t channel_num; - i2s_frame_size_t frame_size; - i2s_data_size_t data_size; - uint8_t fifo_threshold; /*!< I2S receive and transmit threshold*/ - void *tx_dma; - void *rx_dma; -} i2s_device_t; - -#define I2S_DEV(dev) ((i2s_device_t *)dev) - -int i2s_register(enum i2s_index_type index, const char *name); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_mtimer.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_mtimer.h deleted file mode 100644 index 07baccff02..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_mtimer.h +++ /dev/null @@ -1,43 +0,0 @@ -/** - * @file hal_mtimer.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __HAL_MTIMER__H__ -#define __HAL_MTIMER__H__ - -#include "stdint.h" - -#ifdef __cplusplus -extern "C" { -#endif - -void mtimer_init(void); -void mtimer_set_alarm_time(uint64_t ticks, void (*interruptfun)(void)); -uint64_t mtimer_get_time_ms(); -uint64_t mtimer_get_time_us(); -void mtimer_delay_ms(uint32_t time); -void mtimer_delay_us(uint32_t time); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_pm.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_pm.h deleted file mode 100644 index 1fa174b148..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_pm.h +++ /dev/null @@ -1,92 +0,0 @@ -/** - * @file hal_pm.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __HAL_PM__H__ -#define __HAL_PM__H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "hal_common.h" -enum pm_pds_sleep_level { - PM_PDS_LEVEL_1 = 1, - PM_PDS_LEVEL_2 = 2, - PM_PDS_LEVEL_3 = 3, - PM_PDS_LEVEL_7 = 7, -}; - -enum pm_hbn_sleep_level { - PM_HBN_LEVEL_0, - PM_HBN_LEVEL_1, - PM_HBN_LEVEL_2, -}; - -/** - * @brief HBN BOR threshold type definition - */ -typedef enum { - HBN_BOR_THRES_2P05V = 0, /*!< BOR threshold 2.05V */ - HBN_BOR_THRES_2P10V, /*!< BOR threshold 2.10V */ - HBN_BOR_THRES_2P15V, /*!< BOR threshold 2.15V */ - HBN_BOR_THRES_2P20V, /*!< BOR threshold 2.20V */ - HBN_BOR_THRES_2P25V, /*!< BOR threshold 2.25V */ - HBN_BOR_THRES_2P30V, /*!< BOR threshold 2.30V */ - HBN_BOR_THRES_2P35V, /*!< BOR threshold 2.35V */ - HBN_BOR_THRES_2P40V, /*!< BOR threshold 2.40V */ -} HBN_BOR_THRES_Type; - -/** - * @brief HBN BOR mode type definition - */ -typedef enum { - HBN_BOR_MODE_POR_INDEPENDENT, /*!< POR is independent of BOR */ - HBN_BOR_MODE_POR_RELEVANT, /*!< POR is relevant to BOR */ -} HBN_BOR_MODE_Type; - -enum pm_event_type { - PM_HBN_WAKEUP_EVENT_NONE, - PM_HBN_GPIO9_WAKEUP_EVENT, - PM_HBN_GPIO10_WAKEUP_EVENT, - PM_HBN_GPIO11_WAKEUP_EVENT, - PM_HBN_GPIO12_WAKEUP_EVENT, - PM_HBN_GPIO13_WAKEUP_EVENT, - PM_HBN_GPIO14_WAKEUP_EVENT, - PM_HBN_GPIO15_WAKEUP_EVENT, - PM_HBN_GPIO40_WAKEUP_EVENT, - PM_HBN_GPIO41_WAKEUP_EVENT, - PM_HBN_RTC_WAKEUP_EVENT, - PM_HBN_BOD_WAKEUP_EVENT, - PM_HBN_ACOMP0_WAKEUP_EVENT, - PM_HBN_ACOMP1_WAKEUP_EVENT, -}; - -void pm_pds_mask_all_wakeup_src(void); -void pm_pds_mode_enter(enum pm_pds_sleep_level pds_level, uint32_t sleep_time); -void pm_hbn_out0_irq_register(void); -void pm_hbn_out1_irq_register(void); -void HBN_OUT0_IRQ(void); -void HBN_OUT1_IRQ(void); -void pm_irq_callback(enum pm_event_type event); -void pm_pds_irq_register(void); -void PDS_WAKEUP_IRQ(void); -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_pwm.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_pwm.h deleted file mode 100644 index 10326175fb..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_pwm.h +++ /dev/null @@ -1,117 +0,0 @@ -/** - * @file hal_pwm.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __HAL_PWM__H__ -#define __HAL_PWM__H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "hal_common.h" -#include "drv_device.h" -#include "bl808_config.h" - -#define DEVICE_CTRL_PWM_CHANNEL_CONFIG 0x10 -#define DEVICE_CTRL_PWM_BREAK_CONFIG 0x11 -#define DEVICE_CTRL_PWM_FREQUENCE_CONFIG 0x12 -#define DEVICE_CTRL_PWM_DUTYCYCLE_CONFIG 0x13 -#define DEVICE_CTRL_PWM_PULSE_CONFIG 0x14 - -enum pwm_index_type { -#ifdef BSP_USING_PWM0 - PWM0_INDEX, -#endif -#ifdef BSP_USING_PWM1 - PWM1_INDEX, -#endif - PWM_MAX_INDEX -}; - -#define PWM_CHANNEL_0 (1 << 0) -#define PWM_CHANNEL_1 (1 << 1) -#define PWM_CHANNEL_2 (1 << 2) -#define PWM_CHANNEL_3 (1 << 3) - -#define PWM_SINGLE_OUTPUT_MODE 0 -#define PWM_CONTINUE_OUTPUT_MODE 1 - -#define PWM_CLK_SOURCE_XCLK 0 -#define PWM_CLK_SOURCE_BCLK 1 -#define PWM_CLK_SOURCE_32K 2 - -enum pwm_event_type { - PWM_EVENT_PERIOD_END, - PWM_EVENT_PULSE, - PWM_EVENT_BREAK, -}; - -typedef struct -{ - uint8_t ch; - uint8_t chp_enable; - uint8_t chn_enable; - uint8_t chp_polarity; - uint8_t chn_polarity; - uint8_t chp_idlestate; - uint8_t chn_idlestate; - uint16_t threshold_low; - uint16_t threshold_high; -} pwm_channel_common_t; - -typedef struct -{ - uint8_t ch; - uint16_t threshold_low; - uint16_t threshold_high; -} pwm_channel_dutycycle_t; - -typedef struct -{ - uint8_t ch; - uint8_t chp_breakstate; - uint8_t chn_breakstate; - uint8_t deadtime; -} pwm_channel_break_t; - -typedef struct pwm_device { - struct device parent; - uint8_t id; - uint8_t clk_source; - uint8_t clk_div; - uint8_t output_mode; - uint16_t period; - uint16_t pulse; - uint8_t extern_break_polarity; - uint8_t extern_break_enable; - uint8_t internal_break_enable; - uint8_t adc_trig_source; -} pwm_device_t; - -#define PWM_DEV(dev) ((pwm_device_t *)dev) - -int pwm_register(enum pwm_index_type index, const char *name); - -#ifdef __cplusplus -} -#endif -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_rtc.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_rtc.h deleted file mode 100644 index d432ad6017..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_rtc.h +++ /dev/null @@ -1,38 +0,0 @@ -/** - * @file hal_rtc.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __HAL_RTC__H__ -#define __HAL_RTC__H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "hal_common.h" - -void rtc_init(uint64_t sleep_time); -void rtc_set_timestamp(uint64_t time_stamp); -uint64_t rtc_get_timestamp(void); -#ifdef __cplusplus -} -#endif -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_sec_aes.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_sec_aes.h deleted file mode 100644 index edeab53e15..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_sec_aes.h +++ /dev/null @@ -1,57 +0,0 @@ -/** - * @file hal_sec_aes.h - * @brief - * - * Copyright 2019-2030 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __HAL_SEC_AES__H__ -#define __HAL_SEC_AES__H__ - -#include "hal_common.h" - -typedef enum { - SEC_AES_CBC, - SEC_AES_CTR, - SEC_AES_XTS, - SEC_AES_ECB -} sec_aes_type; - -typedef enum { - SEC_AES_KEY_128, - SEC_AES_KEY_256, - SEC_AES_KEY_192 -} sec_aes_key_type; - -typedef struct sec_aes_handle_t { - sec_aes_type aes_type; - sec_aes_key_type key_type; -} sec_aes_handle_t; - -typedef enum { - SEC_AES_DIR_ENCRYPT, - SEC_AES_DIR_DECRYPT -} sec_aes_dir_type; - -int sec_aes_init(sec_aes_handle_t *handle, sec_aes_type aes_tye, sec_aes_key_type key_type); -int sec_aes_setkey(sec_aes_handle_t *handle, const uint8_t *key, uint8_t key_len, const uint8_t *nonce, uint8_t dir); -int sec_aes_encrypt(sec_aes_handle_t *handle, const uint8_t *in, uint32_t len, size_t offset, uint8_t *out); -int sec_aes_decrypt(sec_aes_handle_t *handle, const uint8_t *in, uint32_t len, size_t offset, uint8_t *out); -int sec_aes_deinit(sec_aes_handle_t *handle); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_sec_dsa.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_sec_dsa.h deleted file mode 100644 index 246c695c54..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_sec_dsa.h +++ /dev/null @@ -1,57 +0,0 @@ -/** - * @file hal_sec_dsa.h - * @brief - * - * Copyright 2019-2030 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __HAL_SEC_DSA__H__ -#define __HAL_SEC_DSA__H__ - -#include "hal_common.h" - -typedef struct sec_dsa_crt_cfg_tag { - uint32_t *dP; - uint32_t *dQ; - uint32_t *qInv; - uint32_t *p; - uint32_t *invR_p; - uint32_t *primeN_p; - uint32_t *q; - uint32_t *invR_q; - uint32_t *primeN_q; -} sec_dsa_crt_cfg_t; - -typedef struct -{ - uint32_t size; - uint32_t crtSize; - uint32_t *n; - uint32_t *e; - uint32_t *d; - sec_dsa_crt_cfg_t crtCfg; -} sec_dsa_handle_t; - -int sec_dsa_init(sec_dsa_handle_t *handle, uint32_t size); -int sec_dsa_mexp_binary(uint32_t size, const uint32_t *a, const uint32_t *b, const uint32_t *c, uint32_t *r); -int sec_dsa_mexp_mont(uint32_t size, uint32_t *a, uint32_t *b, uint32_t *c, uint32_t *invR_c, uint32_t *primeN_c, uint32_t *r); -int sec_dsa_decrypt_crt(uint32_t size, uint32_t *c, sec_dsa_crt_cfg_t *crtCfg, uint32_t *d, uint32_t *r); -int sec_dsa_sign(sec_dsa_handle_t *handle, const uint32_t *hash, uint32_t hashLenInWord, uint32_t *s); -int sec_dsa_verify(sec_dsa_handle_t *handle, const uint32_t *hash, uint32_t hashLenInWord, const uint32_t *s); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_sec_ecdsa.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_sec_ecdsa.h deleted file mode 100644 index 8c117ef5e8..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_sec_ecdsa.h +++ /dev/null @@ -1,62 +0,0 @@ -/** - * @file hal_sec_ecdsa.h - * @brief - * - * Copyright 2019-2030 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __HAL_SEC_ECDSA__H__ -#define __HAL_SEC_ECDSA__H__ - -#include "hal_common.h" - -typedef enum { - ECP_SECP256R1 = 0, - ECP_SECP256K1 = 1, - ECP_TYPE_MAX = 2, -} sec_ecp_type; - -typedef struct -{ - sec_ecp_type ecpId; - uint32_t *privateKey; - uint32_t *publicKeyx; - uint32_t *publicKeyy; -} sec_ecdsa_handle_t; - -typedef struct -{ - sec_ecp_type ecpId; -} sec_ecdh_handle_t; - -int sec_ecdsa_init(sec_ecdsa_handle_t *handle, sec_ecp_type id); -int sec_ecdsa_deinit(sec_ecdsa_handle_t *handle); -int sec_ecdsa_sign(sec_ecdsa_handle_t *handle, const uint32_t *random_k, const uint32_t *hash, uint32_t hashLenInWord, uint32_t *r, uint32_t *s); -int sec_ecdsa_verify(sec_ecdsa_handle_t *handle, const uint32_t *hash, uint32_t hashLen, const uint32_t *r, const uint32_t *s); -int sec_ecdsa_get_private_key(sec_ecdsa_handle_t *handle, uint32_t *private_key); -int sec_ecdsa_get_public_key(sec_ecdsa_handle_t *handle, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy); - -int sec_ecdh_init(sec_ecdh_handle_t *handle, sec_ecp_type id); -int sec_ecdh_deinit(sec_ecdh_handle_t *handle); -int sec_ecdh_get_encrypt_key(sec_ecdh_handle_t *handle, const uint32_t *pkX, const uint32_t *pkY, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy); -int sec_ecdh_get_public_key(sec_ecdh_handle_t *handle, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy); -int sec_ecc_get_random_value(uint32_t *randomData, uint32_t *maxRef, uint32_t size); - -#define SEC_CODEPATH_STATE_SIGN 0x48672386 - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_sec_hash.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_sec_hash.h deleted file mode 100644 index 08d7d55480..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_sec_hash.h +++ /dev/null @@ -1,64 +0,0 @@ -/** - * @file hal_sec_hash.h - * @brief - * - * Copyright 2019-2030 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __HAL_SEC_HASH__H__ -#define __HAL_SEC_HASH__H__ - -#include "drv_device.h" -#include "hal_common.h" - -enum sec_hash_index_type { - SEC_HASH0_INDEX, - SEC_HASH_MAX_INDEX -}; - -enum sec_hash_type { - SEC_HASH_SHA1, - SEC_HASH_SHA224, - SEC_HASH_SHA256, - SEC_HASH_SHA384, - SEC_HASH_SHA512, - SEC_HASH_UNKNOWN -}; - -typedef struct sec_hash_device { - struct device parent; - uint32_t shaBuf[64 / 4]; /*!< Data not processed but in this temp buffer */ - uint32_t shaPadding[64 / 4]; /*!< Padding data */ - uint8_t type; /*!< Sha has feed data */ -} sec_hash_device_t; - -typedef struct -{ - uint32_t shaBuf[64 / 4]; /*!< Data not processed but in this temp buffer */ - uint32_t shaPadding[64 / 4]; /*!< Padding data */ - uint8_t type; /*!< Sha has feed data */ -} sec_hash_handle_t; - -int sec_hash_init(sec_hash_handle_t *handle, uint8_t type); -int sec_hash_deinit(sec_hash_handle_t *handle); -int sec_hash_update(sec_hash_handle_t *handle, const void *buffer, uint32_t size); -int sec_hash_finish(sec_hash_handle_t *handle, void *buffer); -int sec_hash_sha256_register(enum sec_hash_index_type index, const char *name); -int sec_hash_sha224_register(enum sec_hash_index_type index, const char *name); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_spi.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_spi.h deleted file mode 100644 index 105c9190db..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_spi.h +++ /dev/null @@ -1,129 +0,0 @@ -/** - * @file hal_spi.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __HAL_SPI__H__ -#define __HAL_SPI__H__ - -#include "hal_common.h" -#include "drv_device.h" -#include "bl808_config.h" - -#define SPI_FIFO_LEN 32 - -#define DEVICE_CTRL_SPI_CONFIG_CLOCK 0x10 - -#define DEVICE_CTRL_SPI_GET_TX_FIFO 0x11 -#define DEVICE_CTRL_SPI_GET_RX_FIFO 0x12 -#define DEVICE_CTRL_SPI_CLEAR_TX_FIFO 0x13 -#define DEVICE_CTRL_SPI_CLEAR_RX_FIFO 0x14 - -#define DEVICE_CTRL_SPI_GET_BUS_BUSY_STATUS 0x15 -#define DEVICE_CTRL_SPI_SET_FRAME_SIZE 0x16 - -enum spi_index_type { -#ifdef BSP_USING_SPI0 - SPI0_INDEX, -#endif -#ifdef BSP_USING_SPI1 - SPI1_INDEX, -#endif - SPI_MAX_INDEX -}; - -/** @defgroup SPI_Direction SPI Direction Mode (Only when the datasize==SPI_DATASIZE_32BIT) - * @{ - */ -typedef enum { - SPI_LSB_BYTE0_DIRECTION_FIRST = 0, - SPI_LSB_BYTE3_DIRECTION_FIRST, - SPI_MSB_BYTE0_DIRECTION_FIRST, - SPI_MSB_BYTE3_DIRECTION_FIRST, -}spi_byte_order_type; - -/** @defgroup SPI_Data_Size SPI Data Size - * @{ - */ -typedef enum { - SPI_DATASIZE_8BIT = 0, - SPI_DATASIZE_16BIT, - SPI_DATASIZE_24BIT, - SPI_DATASIZE_32BIT, -}spi_data_size_type; - -/** @defgroup SPI_Clock_Polarity SPI Clock Polarity - * @{ - */ -typedef enum { - SPI_POLARITY_LOW = 0, - SPI_POLARITY_HIGH, -}spi_polarity_type; - -/** @defgroup SPI_Clock_Phase SPI Clock Phase - * @{ - */ - typedef enum { - SPI_PHASE_1EDGE = 0, - SPI_PHASE_2EDGE, -}spi_phase_type; - -/** @defgroup - * @{ - */ -typedef enum { - SPI_SLVAE_MODE = 0, - SPI_MASTER_MODE, -}spi_mode_type; - -typedef enum { - SPI_TRANSFER_TYPE_8BIT = 0, - SPI_TRANSFER_TYPE_16BIT, - SPI_TRANSFER_TPYE_24BIT, - SPI_TRANSFER_TYPE_32BIT, -}spi_transfer_size_type; - -typedef enum{ - SPI_EVENT_TX_FIFO =0, - SPI_EVENT_RX_FIFO, - SPI_EVENT_UNKNOWN, -}spi_event_type; - -typedef struct spi_device { - struct device parent; - uint8_t id; - uint32_t clk; - spi_mode_type mode; - spi_byte_order_type direction; - spi_polarity_type clk_polaraity; - spi_phase_type clk_phase; - spi_data_size_type datasize; - uint8_t fifo_threshold; - uint8_t pin_swap_enable; /*swap mosi and miso*/ - uint8_t delitch_cnt; - void *tx_dma; - void *rx_dma; -} spi_device_t; - -#define SPI_DEV(dev) ((spi_device_t *)dev) - -int spi_register(enum spi_index_type index, const char *name); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_spi_flash.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_spi_flash.h deleted file mode 100644 index d43ccc4199..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_spi_flash.h +++ /dev/null @@ -1,35 +0,0 @@ -/** - * @file hal_spi_flash.h - * @brief - * - * Copyright 2019-2030 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __HAL_SPI_FLASH__H__ -#define __HAL_SPI_FLASH__H__ - -#include "hal_common.h" - -void spi_flash_set_gpio(uint8_t clk, uint8_t cs, uint8_t mosi, uint8_t miso); -BL_Err_Type spi_flash_init(void); -BL_Err_Type spi_flash_read_jedec_id(uint8_t *data); -BL_Err_Type spi_flash_read(uint32_t addr, uint8_t *data, uint32_t len); -BL_Err_Type spi_flash_write(uint32_t addr, uint8_t *data, uint32_t len); -BL_Err_Type spi_flash_erase(uint32_t startaddr, uint32_t len); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_timer.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_timer.h deleted file mode 100644 index 2a8a52b36d..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_timer.h +++ /dev/null @@ -1,94 +0,0 @@ -/** - * @file hal_timer.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __HAL_TIMER__H__ -#define __HAL_TIMER__H__ - -#include "hal_common.h" -#include "drv_device.h" -#include "bl808_config.h" - -#define DEVICE_CTRL_TIMER_CH_START 0x80 -#define DEVICE_CTRL_TIMER_CH_STOP 0x81 - -enum timer_index_type { -#ifdef BSP_USING_TIMER_CH0 - TIMER_CH0_INDEX, -#endif -#ifdef BSP_USING_TIMER_CH1 - TIMER_CH1_INDEX, -#endif - TIMER_MAX_INDEX -}; - -enum timer_event_type { - TIMER_EVENT_COMP0, - TIMER_EVENT_COMP1, - TIMER_EVENT_COMP2, - TIMER_EVENT_UNKNOWN -}; - -enum timer_it_type { - TIMER_COMP0_IT = 1 << 0, - TIMER_COMP1_IT = 1 << 1, - TIMER_COMP2_IT = 1 << 2, - TIMER_ALL_IT = 1 << 3 -}; -typedef enum { - TIMER_CLK_FCLK, - TIMER_CLK_32K, - TIMER_CLK_1K, - TIMER_CLK_XTAL, -} timer_clk_src_t; - -typedef enum { - TIMER_PL_TRIG_NONE, - TIMER_PL_TRIG_COMP0, - TIMER_PL_TRIG_COMP1, - TIMER_PL_TRIG_COMP2, -} timer_pl_trig_t; - -typedef enum { - TIMER_CNT_PRELOAD, - TIMER_CNT_FREERUN, -} timer_cnt_mode; - -typedef struct -{ - uint32_t timeout_val; - uint32_t comp_it; -} timer_user_cfg_t; - -typedef struct timer_device { - struct device parent; - uint8_t id; - uint8_t ch; - uint8_t clk_div; - timer_cnt_mode cnt_mode; - timer_pl_trig_t pl_trig_src; -} timer_device_t; - -#define TIMER_DEV(dev) ((timer_device_t *)dev) - -int timer_register(enum timer_index_type index, const char *name); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_uart.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_uart.h deleted file mode 100644 index 2555e746f7..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_uart.h +++ /dev/null @@ -1,131 +0,0 @@ -/** - * @file hal_uart.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __HAL_UART__H__ -#define __HAL_UART__H__ - -#include "hal_common.h" -#include "drv_device.h" -#include "bl808_config.h" - -#define UART_FIFO_LEN 32 - -#define DEVICE_CTRL_UART_GET_TX_FIFO 0x10 -#define DEVICE_CTRL_UART_GET_RX_FIFO 0x11 - -enum uart_index_type { -#ifdef BSP_USING_UART0 - UART0_INDEX, -#endif -#ifdef BSP_USING_UART1 - UART1_INDEX, -#endif -#ifdef BSP_USING_UART2 - UART2_INDEX, -#endif -#ifdef BSP_USING_UART3 - UART3_INDEX, -#endif - UART_MAX_INDEX -}; - -/*! - * @brief UART data length settings - * - * This enumeration defines the UART data lengths. - */ -typedef enum { - UART_DATA_LEN_5 = 0, /*!< Data length is 5 bits */ - UART_DATA_LEN_6 = 1, /*!< Data length is 6 bits */ - UART_DATA_LEN_7 = 2, /*!< Data length is 7 bits */ - UART_DATA_LEN_8 = 3 /*!< Data length is 8 bits */ -} uart_databits_t; - -/*! - * @brief UART stop bit settings - * - * This enumeration defines the UART stop bits. - */ -typedef enum { - UART_STOP_ZERO_D_FIVE = 0, /*!< 0.5 stop bit */ - UART_STOP_ONE = 1, /*!< 1 stop bit */ - UART_STOP_ONE_D_FIVE = 2, /*!< 1.5 stop bit */ - UART_STOP_TWO = 3 /*!< 2 stop bits */ -} uart_stopbits_t; - -/*! - * @brief UART parity type settings - * - * This enumeration defines the UART parity types. - */ -typedef enum { - UART_PAR_NONE = 0, /*!< No parity */ - UART_PAR_ODD = 1, /*!< Parity bit is odd */ - UART_PAR_EVEN = 2, /*!< Parity bit is even */ -} uart_parity_t; - -enum uart_event_type { - UART_EVENT_TX_END, - UART_EVENT_TX_FIFO, - UART_EVENT_RX_END, - UART_EVENT_RX_FIFO, - UART_EVENT_RTO, - UART_EVENT_UNKNOWN -}; - -enum uart_it_type { - UART_TX_END_IT = 1 << 0, - UART_RX_END_IT = 1 << 1, - UART_TX_FIFO_IT = 1 << 2, - UART_RX_FIFO_IT = 1 << 3, - UART_RTO_IT = 1 << 4, - UART_PCE_IT = 1 << 5, - UART_TX_FER_IT = 1 << 6, - UART_RX_FER_IT = 1 << 7, - UART_ALL_IT = 1 << 8 -}; - -typedef struct -{ - uint32_t baudrate; - uart_databits_t databits; - uart_stopbits_t stopbits; - uart_parity_t parity; -} uart_param_cfg_t; - -typedef struct uart_device { - struct device parent; - uint8_t id; - uint32_t baudrate; - uart_databits_t databits; - uart_stopbits_t stopbits; - uart_parity_t parity; - uint8_t fifo_threshold; - void *tx_dma; - void *rx_dma; -} uart_device_t; - -#define UART_DEV(dev) ((uart_device_t *)dev) - -int uart_register(enum uart_index_type index, const char *name); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_usb.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_usb.h deleted file mode 100644 index 29d617c4af..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_usb.h +++ /dev/null @@ -1,151 +0,0 @@ -/** - * @file hal_usb.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __HAL_USB__H__ -#define __HAL_USB__H__ - -#include "stdint.h" - -/** - * USB endpoint Transfer Type mask. - */ -#define USBD_EP_TYPE_CTRL 0 -#define USBD_EP_TYPE_ISOC 1 -#define USBD_EP_TYPE_BULK 2 -#define USBD_EP_TYPE_INTR 3 -#define USBD_EP_TYPE_MASK 3 - -/** - * USB endpoint direction and number. - */ -#define USB_EP_DIR_MASK 0x80U -#define USB_EP_DIR_IN 0x80U -#define USB_EP_DIR_OUT 0x00U - -#define USB_EP_OUT_MSK 0x7FU -#define USB_EP_IN_MSK 0x80U - -/** Get endpoint index (number) from endpoint address */ -#define USB_EP_GET_IDX(ep) ((ep) & ~USB_EP_DIR_MASK) -/** Get direction from endpoint address */ -#define USB_EP_GET_DIR(ep) ((ep)&USB_EP_DIR_MASK) -/** Get endpoint address from endpoint index and direction */ -#define USB_EP_GET_ADDR(idx, dir) ((idx) | ((dir)&USB_EP_DIR_MASK)) -/** True if the endpoint is an IN endpoint */ -#define USB_EP_DIR_IS_IN(ep) (USB_EP_GET_DIR(ep) == USB_EP_DIR_IN) -/** True if the endpoint is an OUT endpoint */ -#define USB_EP_DIR_IS_OUT(ep) (USB_EP_GET_DIR(ep) == USB_EP_DIR_OUT) - -#define USB_SET_EP_OUT(ep) (ep & USB_EP_OUT_MSK) -#define USB_SET_EP_IN(ep) (ep | USB_EP_IN_MSK) - -#define USB_OUT_EP_NUM 8 -#define USB_IN_EP_NUM 8 - -enum usb_dc_event_type { - /** USB error reported by the controller */ - USB_DC_EVENT_ERROR, - /** USB reset */ - USB_DC_EVENT_RESET, - /** Start of Frame received */ - USB_DC_EVENT_SOF, - /** USB connection established, hardware enumeration is completed */ - USB_DC_EVENT_CONNECTED, - /** USB configuration done */ - USB_DC_EVENT_CONFIGURED, - /** USB connection suspended by the HOST */ - USB_DC_EVENT_SUSPEND, - /** USB connection lost */ - USB_DC_EVENT_DISCONNECTED, - /** USB connection resumed by the HOST */ - USB_DC_EVENT_RESUME, - - /** USB interface selected */ - USB_DC_EVENT_SET_INTERFACE, - /** USB interface selected */ - USB_DC_EVENT_SET_REMOTE_WAKEUP, - /** USB interface selected */ - USB_DC_EVENT_CLEAR_REMOTE_WAKEUP, - /** Set Feature ENDPOINT_HALT received */ - USB_DC_EVENT_SET_HALT, - /** Clear Feature ENDPOINT_HALT received */ - USB_DC_EVENT_CLEAR_HALT, - /** setup packet received */ - USB_DC_EVENT_SETUP_NOTIFY, - /** ep0 in packet received */ - USB_DC_EVENT_EP0_IN_NOTIFY, - /** ep0 out packet received */ - USB_DC_EVENT_EP0_OUT_NOTIFY, - /** ep in packet except ep0 received */ - USB_DC_EVENT_EP_IN_NOTIFY, - /** ep out packet except ep0 received */ - USB_DC_EVENT_EP_OUT_NOTIFY, - /** Initial USB connection status */ - USB_DC_EVENT_UNKNOWN -}; - -enum usb_error_type { - USB_DC_OK = 0, - USB_DC_EP_DIR_ERR = 1, - USB_DC_EP_EN_ERR = 2, - USB_DC_EP_TIMEOUT_ERR = 3, - USB_DC_ADDR_ERR = 4, - USB_DC_DMA_ERR = 5, - USB_DC_VDMA_ERR = 6, - USB_DC_DATA_NONE = 7, -}; -/** - * @brief USB Endpoint Configuration. - * - * Structure containing the USB endpoint configuration. - */ -struct usb_dc_ep_cfg { - /** The number associated with the EP in the device - * configuration structure - * IN EP = 0x80 | \ - * OUT EP = 0x00 | \ - */ - uint8_t ep_addr; - /** Endpoint Transfer Type. - * May be Bulk, Interrupt, Control or Isochronous - */ - uint8_t ep_type; - /** Endpoint max packet size */ - uint16_t ep_mps; -}; - -/* - * USB endpoint structure. - */ -typedef struct -{ - uint8_t ep_ena; - uint8_t is_stalled; - struct usb_dc_ep_cfg ep_cfg; -} usb_dc_ep_state_t; - -typedef struct usb_dc_device { - usb_dc_ep_state_t in_ep[8]; /*!< IN endpoint parameters */ - usb_dc_ep_state_t out_ep[8]; /*!< OUT endpoint parameters */ -} usb_dc_device_t; - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/mipi_display.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/mipi_display.h deleted file mode 100644 index a63d840161..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/mipi_display.h +++ /dev/null @@ -1,187 +0,0 @@ -#ifndef MIPI_DISPLAY_H -#define MIPI_DISPLAY_H - -/** - * struct drm_panel - DRM panel object - */ -struct drm_panel { - /** - * @dev: - * - * Parent device of the panel. - */ - struct device *dev; - - /** - * @backlight: - * - * Backlight device, used to turn on backlight after the call - * to enable(), and to turn off backlight before the call to - * disable(). - * backlight is set by drm_panel_of_backlight() and drivers - * shall not assign it. - */ - struct backlight_device *backlight; - - /** - * @funcs: - * - * Operations that can be performed on the panel. - */ - const struct drm_panel_funcs *funcs; - - /** - * @connector_type: - * - * Type of the panel as a DRM_MODE_CONNECTOR_* value. This is used to - * initialise the drm_connector corresponding to the panel with the - * correct connector type. - */ - int connector_type; - - /** - * @list: - * - * Panel entry in registry. - */ - //struct list_head list; -}; - -/* MIPI DSI Processor-to-Peripheral transaction types */ -enum { - MIPI_DSI_V_SYNC_START = 0x01, - MIPI_DSI_V_SYNC_END = 0x11, - MIPI_DSI_H_SYNC_START = 0x21, - MIPI_DSI_H_SYNC_END = 0x31, - - MIPI_DSI_COMPRESSION_MODE = 0x07, - MIPI_DSI_END_OF_TRANSMISSION = 0x08, - - MIPI_DSI_COLOR_MODE_OFF = 0x02, - MIPI_DSI_COLOR_MODE_ON = 0x12, - MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22, - MIPI_DSI_TURN_ON_PERIPHERAL = 0x32, - - MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM = 0x03, - MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM = 0x13, - MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM = 0x23, - - MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM = 0x04, - MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM = 0x14, - MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM = 0x24, - - MIPI_DSI_DCS_SHORT_WRITE = 0x05, - MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15, - - MIPI_DSI_DCS_READ = 0x06, - MIPI_DSI_EXECUTE_QUEUE = 0x16, - - MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37, - - MIPI_DSI_NULL_PACKET = 0x09, - MIPI_DSI_BLANKING_PACKET = 0x19, - MIPI_DSI_GENERIC_LONG_WRITE = 0x29, - MIPI_DSI_DCS_LONG_WRITE = 0x39, - - MIPI_DSI_PICTURE_PARAMETER_SET = 0x0a, - MIPI_DSI_COMPRESSED_PIXEL_STREAM = 0x0b, - - MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c, - MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c, - MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c, - - MIPI_DSI_PACKED_PIXEL_STREAM_30 = 0x0d, - MIPI_DSI_PACKED_PIXEL_STREAM_36 = 0x1d, - MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12 = 0x3d, - - MIPI_DSI_PACKED_PIXEL_STREAM_16 = 0x0e, - MIPI_DSI_PACKED_PIXEL_STREAM_18 = 0x1e, - MIPI_DSI_PIXEL_STREAM_3BYTE_18 = 0x2e, - MIPI_DSI_PACKED_PIXEL_STREAM_24 = 0x3e, -}; - -/* MIPI DSI Peripheral-to-Processor transaction types */ -enum { - MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT = 0x02, - MIPI_DSI_RX_END_OF_TRANSMISSION = 0x08, - MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE = 0x11, - MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE = 0x12, - MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE = 0x1a, - MIPI_DSI_RX_DCS_LONG_READ_RESPONSE = 0x1c, - MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE = 0x21, - MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE = 0x22, -}; - -/* MIPI DCS commands */ -enum { - MIPI_DCS_NOP = 0x00, - MIPI_DCS_SOFT_RESET = 0x01, - MIPI_DCS_GET_COMPRESSION_MODE = 0x03, - MIPI_DCS_GET_DISPLAY_ID = 0x04, - MIPI_DCS_GET_ERROR_COUNT_ON_DSI = 0x05, - MIPI_DCS_GET_RED_CHANNEL = 0x06, - MIPI_DCS_GET_GREEN_CHANNEL = 0x07, - MIPI_DCS_GET_BLUE_CHANNEL = 0x08, - MIPI_DCS_GET_DISPLAY_STATUS = 0x09, - MIPI_DCS_GET_POWER_MODE = 0x0A, - MIPI_DCS_GET_ADDRESS_MODE = 0x0B, - MIPI_DCS_GET_PIXEL_FORMAT = 0x0C, - MIPI_DCS_GET_DISPLAY_MODE = 0x0D, - MIPI_DCS_GET_SIGNAL_MODE = 0x0E, - MIPI_DCS_GET_DIAGNOSTIC_RESULT = 0x0F, - MIPI_DCS_ENTER_SLEEP_MODE = 0x10, - MIPI_DCS_EXIT_SLEEP_MODE = 0x11, - MIPI_DCS_ENTER_PARTIAL_MODE = 0x12, - MIPI_DCS_ENTER_NORMAL_MODE = 0x13, - MIPI_DCS_GET_IMAGE_CHECKSUM_RGB = 0x14, - MIPI_DCS_GET_IMAGE_CHECKSUM_CT = 0x15, - MIPI_DCS_EXIT_INVERT_MODE = 0x20, - MIPI_DCS_ENTER_INVERT_MODE = 0x21, - MIPI_DCS_SET_GAMMA_CURVE = 0x26, - MIPI_DCS_SET_DISPLAY_OFF = 0x28, - MIPI_DCS_SET_DISPLAY_ON = 0x29, - MIPI_DCS_SET_COLUMN_ADDRESS = 0x2A, - MIPI_DCS_SET_PAGE_ADDRESS = 0x2B, - MIPI_DCS_WRITE_MEMORY_START = 0x2C, - MIPI_DCS_WRITE_LUT = 0x2D, - MIPI_DCS_READ_MEMORY_START = 0x2E, - MIPI_DCS_SET_PARTIAL_ROWS = 0x30, /* MIPI DCS 1.02 - MIPI_DCS_SET_PARTIAL_AREA before that */ - MIPI_DCS_SET_PARTIAL_COLUMNS = 0x31, - MIPI_DCS_SET_SCROLL_AREA = 0x33, - MIPI_DCS_SET_TEAR_OFF = 0x34, - MIPI_DCS_SET_TEAR_ON = 0x35, - MIPI_DCS_SET_ADDRESS_MODE = 0x36, - MIPI_DCS_SET_SCROLL_START = 0x37, - MIPI_DCS_EXIT_IDLE_MODE = 0x38, - MIPI_DCS_ENTER_IDLE_MODE = 0x39, - MIPI_DCS_SET_PIXEL_FORMAT = 0x3A, - MIPI_DCS_WRITE_MEMORY_CONTINUE = 0x3C, - MIPI_DCS_SET_3D_CONTROL = 0x3D, - MIPI_DCS_READ_MEMORY_CONTINUE = 0x3E, - MIPI_DCS_GET_3D_CONTROL = 0x3F, - MIPI_DCS_SET_VSYNC_TIMING = 0x40, - MIPI_DCS_SET_TEAR_SCANLINE = 0x44, - MIPI_DCS_GET_SCANLINE = 0x45, - MIPI_DCS_SET_DISPLAY_BRIGHTNESS = 0x51, /* MIPI DCS 1.3 */ - MIPI_DCS_GET_DISPLAY_BRIGHTNESS = 0x52, /* MIPI DCS 1.3 */ - MIPI_DCS_WRITE_CONTROL_DISPLAY = 0x53, /* MIPI DCS 1.3 */ - MIPI_DCS_GET_CONTROL_DISPLAY = 0x54, /* MIPI DCS 1.3 */ - MIPI_DCS_WRITE_POWER_SAVE = 0x55, /* MIPI DCS 1.3 */ - MIPI_DCS_GET_POWER_SAVE = 0x56, /* MIPI DCS 1.3 */ - MIPI_DCS_SET_CABC_MIN_BRIGHTNESS = 0x5E, /* MIPI DCS 1.3 */ - MIPI_DCS_GET_CABC_MIN_BRIGHTNESS = 0x5F, /* MIPI DCS 1.3 */ - MIPI_DCS_READ_DDB_START = 0xA1, - MIPI_DCS_READ_PPS_START = 0xA2, - MIPI_DCS_READ_DDB_CONTINUE = 0xA8, - MIPI_DCS_READ_PPS_CONTINUE = 0xA9, -}; - -/* MIPI DCS pixel formats */ -#define MIPI_DCS_PIXEL_FMT_24BIT 7 -#define MIPI_DCS_PIXEL_FMT_18BIT 6 -#define MIPI_DCS_PIXEL_FMT_16BIT 5 -#define MIPI_DCS_PIXEL_FMT_12BIT 3 -#define MIPI_DCS_PIXEL_FMT_8BIT 2 -#define MIPI_DCS_PIXEL_FMT_3BIT 1 - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_adc.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_adc.c deleted file mode 100644 index 3a21ad8dd6..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_adc.c +++ /dev/null @@ -1,383 +0,0 @@ -/** - * @file hal_adc.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#include "hal_adc.h" -#include "hal_clock.h" -#include "bl808_glb.h" -#include "bl808_dma.h" -#include "bl808_adc.h" -#include "adc_config.h" - -#ifdef BSP_USING_ADC0 -static void ADC_IRQ(void); -#endif - -static adc_device_t adcx_device[ADC_MAX_INDEX] = { -#ifdef BSP_USING_ADC0 - ADC0_CONFIG, -#endif -}; - -/** - * @brief Check whether Channel Corresponding IO is configed success by Board System - * - * @param pos_list pos channel list - * @param neg_list negative channel list - * @param channelNum channel number - */ -uint8_t adc_check_channel_status(uint8_t *pos_list, uint8_t *neg_list, uint16_t channelNum) -{ - return SUCCESS; -} -/** - * @brief - * - * @param dev - * @param oflag - * @return int - */ -int adc_open(struct device *dev, uint16_t oflag) -{ - adc_device_t *adc_device = (adc_device_t *)dev; - ADC_CFG_Type adc_cfg = { 0 }; - ADC_FIFO_Cfg_Type adc_fifo_cfg = { 0 }; - - CPU_Interrupt_Disable(GPADC_DMA_IRQn); - - ADC_IntMask(ADC_INT_ALL, MASK); - - adc_cfg.clkDiv = adc_device->clk_div; - - adc_cfg.vref = adc_device->vref; - adc_cfg.resWidth = adc_device->data_width; - adc_cfg.inputMode = adc_device->differential_mode; - - adc_cfg.v18Sel = ADC_V18_SELECT; - adc_cfg.v11Sel = ADC_V11_SELECT; - adc_cfg.gain1 = ADC_PGA_GAIN1; - adc_cfg.gain2 = ADC_PGA_GAIN2; - adc_cfg.chopMode = ADC_CHOP_MODE; - adc_cfg.biasSel = ADC_BIAS_SELECT; - adc_cfg.vcm = ADC_PGA_VCM; - adc_cfg.offsetCalibEn = ADC_OFFSET_CALIB_EN; - adc_cfg.offsetCalibVal = ADC_OFFSER_CALIB_VAL; - - adc_fifo_cfg.dmaEn = DISABLE; - adc_fifo_cfg.fifoThreshold = adc_device->fifo_threshold; - - if (oflag & DEVICE_OFLAG_STREAM_TX) { - } - - if ((oflag & DEVICE_OFLAG_INT_TX) || (oflag & DEVICE_OFLAG_INT_RX)) { -#ifdef BSP_USING_ADC0 - Interrupt_Handler_Register(GPADC_DMA_IRQn, ADC_IRQ); -#endif - } - - if (oflag & DEVICE_OFLAG_DMA_TX) { - } - - if (oflag & DEVICE_OFLAG_DMA_RX) { - adc_fifo_cfg.dmaEn = ENABLE; - } - - ADC_Disable(); - ADC_Enable(); - - ADC_Reset(); - - ADC_Init(&adc_cfg); - - ADC_FIFO_Cfg(&adc_fifo_cfg); - - return 0; -} -/** - * @brief - * - * @param dev - * @return int - */ -int adc_close(struct device *dev) -{ - uint32_t tmpVal; - - ADC_IntMask(ADC_INT_ALL, MASK); - - /* disable convert start */ - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_CONV_START); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); - - /*disable adc */ - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_GLOBAL_EN); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); - - /*disable vbat */ - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_VBAT_EN); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); - - ADC_Reset(); - return 0; -} - -/** - * @brief - * - * @param dev - * @param cmd - * @param args - * @return int - */ -int adc_control(struct device *dev, int cmd, void *args) -{ - adc_device_t *adc_device = (adc_device_t *)dev; - adc_channel_cfg_t *adc_channel_cfg = (adc_channel_cfg_t *)args; - uint8_t rlt = 0; - - switch (cmd) { - case DEVICE_CTRL_SET_INT: { - uint32_t offset = __builtin_ctz((uint32_t)(uintptr_t)args); - while ((2 <= offset) && (offset < 6)) { - if ((uint32_t)(uintptr_t)args & (1 << offset)) { - ADC_IntMask(offset, UNMASK); - } - offset++; - } - CPU_Interrupt_Enable(GPADC_DMA_IRQn); - - break; - } - - case DEVICE_CTRL_CLR_INT: { - uint32_t offset = __builtin_ctz((uint32_t)(uintptr_t)args); - while ((2 <= offset) && (offset < 6)) { - if ((uint32_t)(uintptr_t)args & (1 << offset)) { - ADC_IntMask(offset, UNMASK); - } - offset++; - } - CPU_Interrupt_Disable(GPADC_DMA_IRQn); - - break; - } - - case DEVICE_CTRL_GET_INT: - break; - - case DEVICE_CTRL_CONFIG: - break; - - case DEVICE_CTRL_ADC_CHANNEL_CONFIG: - for (uint32_t i = 0; i < adc_channel_cfg->num; i++) { - if ((adc_channel_cfg->pos_channel[i] == ADC_CHAN5) || (adc_channel_cfg->neg_channel[i] == ADC_CHAN5)) { - HBN_Set_IO4041_As_Xtal_32K_IO(DISABLE); - } - } - if (adc_channel_cfg->num == 1) { - ADC_Channel_Config((ADC_Chan_Type)adc_channel_cfg->pos_channel[0], (ADC_Chan_Type)adc_channel_cfg->neg_channel[0], adc_device->continuous_conv_mode); - rlt = adc_check_channel_status((uint8_t *)adc_channel_cfg->pos_channel, (uint8_t *)adc_channel_cfg->neg_channel, 1); - } else { - ADC_Scan_Channel_Config((ADC_Chan_Type *)adc_channel_cfg->pos_channel, (ADC_Chan_Type *)adc_channel_cfg->neg_channel, adc_channel_cfg->num, adc_device->continuous_conv_mode); - rlt = adc_check_channel_status((uint8_t *)adc_channel_cfg->pos_channel, (uint8_t *)adc_channel_cfg->neg_channel, adc_channel_cfg->num); - } - - break; - - case DEVICE_CTRL_ADC_CHANNEL_START: { - uint32_t regCmd; - - /* disable convert start */ - regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - regCmd = BL_CLR_REG_BIT(regCmd, AON_GPADC_CONV_START); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd); - - arch_delay_us(100); - - /* enable convert start */ - regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - regCmd = BL_SET_REG_BIT(regCmd, AON_GPADC_CONV_START); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd); - } break; - - case DEVICE_CTRL_ADC_CHANNEL_STOP: { - uint32_t tmpVal; - - /* disable convert start */ - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_CONV_START); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); - break; - } - - case DEVICE_CTRL_ADC_VBAT_ON: { - uint32_t tmpVal; - - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_VBAT_EN); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); - break; - } - - case DEVICE_CTRL_ADC_VBAT_OFF: { - uint32_t tmpVal; - - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_VBAT_EN); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); - break; - } - - case DEVICE_CTRL_ADC_TSEN_ON: - ADC_Tsen_Init(ADC_TSEN_MOD_INTERNAL_DIODE); - break; - - default: - break; - } - - return rlt; -} -// int adc_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size) -// { - -// return 0; -// } -/** - * @brief - * - * @param dev - * @param pos - * @param buffer - * @param size - * @return int - */ -int adc_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size) -{ - uint32_t adc_fifo_val[32]; - - if (dev->oflag & DEVICE_OFLAG_STREAM_RX) { - if (size > 32) - return -1; - while (ADC_Get_FIFO_Count() < size) { - } - - for (uint32_t i = 0; i < size; i++) { - adc_fifo_val[i] = ADC_Read_FIFO(); - } - adc_channel_val_t *adc_parse_val = (adc_channel_val_t *)buffer; - ADC_Parse_Result(adc_fifo_val, size, (ADC_Result_Type *)adc_parse_val); - return size; - } - - return 0; -} - -int adc_trim_tsen(uint16_t *tsen_offset) -{ - return ADC_Trim_TSEN(tsen_offset); -} - -float adc_get_tsen(uint16_t tsen_offset) -{ - return TSEN_Get_Temp(tsen_offset); -} - -/** - * @brief - * - * @param index - * @param name - * @return int - */ -int adc_register(enum adc_index_type index, const char *name) -{ - struct device *dev; - - if (ADC_MAX_INDEX == 0) { - return -DEVICE_EINVAL; - } - - dev = &(adcx_device[index].parent); - - dev->open = adc_open; - dev->close = adc_close; - dev->control = adc_control; - dev->write = NULL; - dev->read = adc_read; - - dev->type = DEVICE_CLASS_ADC; - dev->handle = NULL; - - return device_register(dev, name); -} - -/** - * @brief - * - * @param handle - */ -void adc_isr(adc_device_t *handle) -{ - if (!handle->parent.callback) - return; - - if (ADC_GetIntStatus(ADC_INT_POS_SATURATION) == SET && ADC_IntGetMask(ADC_INT_POS_SATURATION) == UNMASK) { - //handle->parent.callback(&handle->parent, NULL, 0, ADC_EVEN_INT_POS_SATURATION); - ADC_IntClr(ADC_INT_POS_SATURATION); - } - - if (ADC_GetIntStatus(ADC_INT_NEG_SATURATION) == SET && ADC_IntGetMask(ADC_INT_NEG_SATURATION) == UNMASK) { - //handle->parent.callback(&handle->parent, NULL, 0, ADC_EVEN_INT_NEG_SATURATION); - ADC_IntClr(ADC_INT_NEG_SATURATION); - } - - if (ADC_GetIntStatus(ADC_INT_FIFO_UNDERRUN) == SET && ADC_IntGetMask(ADC_INT_FIFO_UNDERRUN) == UNMASK) { - handle->parent.callback(&handle->parent, NULL, 0, ADC_EVENT_UNDERRUN); - ADC_IntClr(ADC_INT_FIFO_UNDERRUN); - } - - if (ADC_GetIntStatus(ADC_INT_FIFO_OVERRUN) == SET && ADC_IntGetMask(ADC_INT_FIFO_OVERRUN) == UNMASK) { - handle->parent.callback(&handle->parent, NULL, 0, ADC_EVENT_OVERRUN); - ADC_IntClr(ADC_INT_FIFO_OVERRUN); - } - - if (ADC_GetIntStatus(ADC_INT_ADC_READY) == SET && ADC_IntGetMask(ADC_INT_ADC_READY) == UNMASK) { - uint32_t adc_count = ADC_Get_FIFO_Count(); - uint32_t adc_fifo_val[32]; - adc_channel_val_t adc_parse_val[32]; - for (uint32_t i = 0; i < adc_count; i++) { - adc_fifo_val[i] = ADC_Read_FIFO(); - } - ADC_Parse_Result(adc_fifo_val, adc_count, (ADC_Result_Type *)adc_parse_val); - handle->parent.callback(&handle->parent, (void *)adc_parse_val, adc_count, ADC_INT_ADC_READY); - ADC_IntClr(ADC_INT_ADC_READY); - } -} -#ifdef BSP_USING_ADC0 -void ADC_IRQ(void) -{ - adc_isr(&adcx_device[ADC0_INDEX]); -} -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_boot2.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_boot2.c deleted file mode 100644 index 41b67976eb..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_boot2.c +++ /dev/null @@ -1,602 +0,0 @@ -#include "hal_boot2.h" -#include "hal_flash.h" -#include "bl808_ef_ctrl.h" -#include "bl808_ef_cfg.h" -#include "bl808_hbn.h" -#include "bl808_glb.h" -#include "bl808_xip_sflash.h" -#include "bl808_tzc_sec.h" -#include "hal_gpio.h" -#include "hal_sec_hash.h" -#include "bl808_sec_eng.h" -#include "softcrc.h" -#include "bl808_psram_uhs.h" -#include "bl808_romapi_patch.h" - -extern sec_hash_handle_t hash_handle; - -/** - * @brief boot2 init system clock - * - * @param None - * @return None - */ -void hal_boot2_init_clock(void) -{ - extern void system_mtimer_clock_init(void); - extern void peripheral_clock_init(void); - - system_mtimer_clock_init(); - peripheral_clock_init(); -} - -/** - * @brief boot2 custom - * - * @param custom_param - * @return uint32_t - */ -uint32_t hal_boot2_custom(void *custom_param) -{ - if (((g_efuse_cfg.dev_info & HAL_BOOT2_PSRAM_INFO_MASK) >> HAL_BOOT2_PSRAM_INFO_POS) != 0) { - GLB_Config_UHS_PLL(GLB_XTAL_40M, uhsPllCfg_2000M); - Psram_UHS_x16_Init(2000); - Tzc_Sec_PSRAMA_Access_Release(); - - /* Flush i-cache in case branch prediction logic is wrong when - psram is not inited by hal_boot2_custom but cpu has already prefetch psram */ - __ISB(); - } - return 0; -} - -/** - * @brief get efuse Boot2 config - * - * @param g_efuse_cfg - * @param - * @param - * @return None - */ -void hal_boot2_get_efuse_cfg(boot2_efuse_hw_config *efuse_cfg) -{ - uint32_t timeout_cnt = 0; - uint32_t i = 0; - struct boot_efuse_sw_cfg0_t sw_cfg0; - - /* #define EF_CTRL_LOAD_BEFORE_READ_R0 in ef_ctrl to speed up */ - EF_Ctrl_Load_Efuse_R0(); - EF_Ctrl_Load_Efuse_R1(); - - while (EF_Ctrl_AutoLoad_Done() != SET && timeout_cnt < 80) { - arch_delay_us(1); - timeout_cnt++; - } - - /* get hw cfg (signature and aes type) */ - EF_Ctrl_Read_Secure_Boot((EF_Ctrl_SF_AES_Type *)efuse_cfg->encrypted); - - for (i = 0; i < HAL_BOOT2_CPU_GROUP_MAX; i++) { - if (efuse_cfg->encrypted[i] == EF_CTRL_SF_AES_192) { - efuse_cfg->encrypted[i] = SF_CTRL_AES_192BITS + 1; - } else if (efuse_cfg->encrypted[i] == EF_CTRL_SF_AES_256) { - efuse_cfg->encrypted[i] = SF_CTRL_AES_256BITS + 1; - } - } - - /* get sw uasge 0 */ - EF_Ctrl_Read_Sw_Usage(0, (uint32_t *)&sw_cfg0); - /* get sw uasge 1 */ - //EF_Ctrl_Read_Sw_Usage(1, &sw_cfg1); - - for (i = 0; i < HAL_BOOT2_CPU_GROUP_MAX; i++) { - efuse_cfg->sign[i] = ((struct boot_efuse_sw_cfg0_t)sw_cfg0).sign_cfg; - } - for (i = 1; i < HAL_BOOT2_CPU_GROUP_MAX; i++) { - efuse_cfg->encrypted[i] = EF_CTRL_SF_AES_NONE; - } - - efuse_cfg->hbn_check_sign = (uint8_t)(sw_cfg0.hbn_check_sign); - efuse_cfg->sf_pin_cfg = (uint8_t)(sw_cfg0.sf_pin_cfg); - efuse_cfg->uart_download_cfg = (uint8_t)(sw_cfg0.uart_download_cfg); - efuse_cfg->keep_dbg_port_closed = (uint8_t)(sw_cfg0.keep_dbg_port_closed); - efuse_cfg->boot_pin_cfg = (uint8_t)(sw_cfg0.boot_pin_cfg); - - /* get device info */ - EF_Ctrl_Get_Chip_Info((Efuse_Chip_Info_Type *)&efuse_cfg->dev_info); - - /* get chip id */ - EF_Ctrl_Read_Chip_ID(efuse_cfg->chip_id); - - /* get public key hash */ - EF_Ctrl_Read_AES_Key(0, (uint32_t *)efuse_cfg->pk_hash_cpu0, HAL_BOOT2_PK_HASH_SIZE / 4); - EF_Ctrl_Read_AES_Key(8, (uint32_t *)efuse_cfg->pk_hash_cpu1, HAL_BOOT2_PK_HASH_SIZE / 4); -} -/** - * @brief reset sec eng clock - * - * @return - */ -void hal_boot2_reset_sec_eng(void) -{ - GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_SEC_ENG); - Sec_Eng_Group0_Request_SHA_Access(); - Sec_Eng_Group0_Request_AES_Access(); - Sec_Eng_Group0_Request_Trng_Access(); - Sec_Eng_Trng_Enable(); - GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_MCU_MUXPLL_160M); -} - -/** - * @brief system soft reset - * - * @return - */ -void hal_boot2_sw_system_reset(void) -{ - GLB_SW_System_Reset(); -} - -/** - * @brief - * - * @param flag - * @param - * @param - * @return - */ -void hal_boot2_set_psmode_status(uint32_t flag) -{ - HBN_Set_Status_Flag(flag); -} - -/** - * @brief - * - * @param - * @param - * @param - * @return flag - */ -uint32_t hal_boot2_get_psmode_status(void) -{ - return HBN_Get_Status_Flag(); -} - -/** - * @brief - * - * @param - * @param - * @param - * @return user define flag - */ -uint32_t hal_boot2_get_user_fw(void) -{ - return BL_RD_WORD(HBN_BASE + HBN_RSV0_OFFSET); -} - -/** - * @brief clr user define flag - * - * @param - * @param - * @param - * @return - */ -void hal_boot2_clr_user_fw(void) -{ - uint32_t *p = (uint32_t *)(HBN_BASE + HBN_RSV0_OFFSET); - *p = 0; -} - -/** - * @brief hal_boot2_sboot_finish - * - * @return - */ -void ATTR_TCM_SECTION hal_boot2_sboot_finish(void) -{ - // uint32_t tmpVal; - // if (!g_efuse_cfg.keep_dbg_port_closed) { - // /* only after this, JTAG is really open */ - // tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_TZSRG_CTRL); - // tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_SBOOT_DONE, 0xf); - // BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_TZSRG_CTRL, tmpVal); - // } -} - -void bflb_boot2_pds_hbn_pad_pn(void) -{ - /* clear pds/hbn ctrl pad pull type */ - PDS_Set_Flash_Pad_Pull_None_Fast((SF_Ctrl_Pin_Select)g_efuse_cfg.sf_pin_cfg); - HBN_AON_PAD_CFG_Type aonPadCfg = { - .ctrlEn = ENABLE, - .inputEn = ENABLE, - .outputEn = ENABLE, - .pullCfg = HBN_GPIO_PAD_PULL_NONE, - }; - HBN_Aon_Pad_Cfg(ENABLE, HBN_AON_PAD_GPIO14, &aonPadCfg); - HBN_Aon_Pad_Cfg(ENABLE, HBN_AON_PAD_GPIO15, &aonPadCfg); -} - -/** - * @brief hal_boot2_pll_init - * - * @return - */ -void hal_boot2_uart_gpio_init(void) -{ - GLB_GPIO_Cfg_Type cfg; - - cfg.pullType = GPIO_PULL_UP; - cfg.drive = 0; - cfg.smtCtrl = 1; - - /* ToDo: will crash */ - //bflb_boot2_pds_hbn_pad_pn(); - - cfg.gpioPin = GLB_GPIO_PIN_15; - cfg.gpioFun = GPIO_FUN_UART; - cfg.gpioMode = GPIO_MODE_INPUT; - GLB_GPIO_Init(&cfg); - - //GLB_UART_Sig_Swap_Set(GLB_UART_SIG_SWAP_GRP_GPIO12_GPIO23, 0); - GLB_UART_Fun_Sel(GLB_UART_SIG_3, GLB_UART_SIG_FUN_UART0_RXD); - GLB_UART_Fun_Sel((GLB_UART_SIG_Type)GLB_UART_SIG_FUN_UART0_RXD, (GLB_UART_SIG_FUN_Type)GLB_UART_SIG_3); - - cfg.gpioPin = GLB_GPIO_PIN_14; - cfg.gpioFun = GPIO_FUN_UART; - cfg.gpioMode = GPIO_MODE_OUTPUT; - GLB_GPIO_Init(&cfg); - - //GLB_UART_Sig_Swap_Set(GLB_UART_SIG_SWAP_GRP_GPIO12_GPIO23, 0); - - GLB_UART_Fun_Sel(GLB_UART_SIG_2, GLB_UART_SIG_FUN_UART0_TXD); - GLB_UART_Fun_Sel((GLB_UART_SIG_Type)GLB_UART_SIG_FUN_UART0_TXD, (GLB_UART_SIG_FUN_Type)GLB_UART_SIG_2); -} - -/** - * @brief hal_boot2_pll_init - * - * @return - */ -void hal_boot2_debug_uart_gpio_init(void) -{ - GLB_GPIO_Cfg_Type cfg; - - cfg.pullType = GPIO_PULL_NONE; - cfg.drive = 0; - cfg.smtCtrl = 1; - - /* OTP_BOOTLOG_PIN_CFG() */ - /* 0 -> GPIO39 -> qfn68 */ - /* 1 -> GPIO8 -> qfn88 */ - if (0 == g_efuse_cfg.boot_pin_cfg) { - cfg.gpioPin = GLB_GPIO_PIN_39; - cfg.gpioFun = GPIO_FUN_UART; - cfg.gpioMode = GPIO_MODE_OUTPUT; - GLB_GPIO_Init(&cfg); - - GLB_UART_Sig_Swap_Set(GLB_UART_SIG_SWAP_GRP_GPIO36_GPIO45, 1); - GLB_UART_Fun_Sel(GLB_UART_SIG_9, GLB_UART_SIG_FUN_UART1_TXD); - GLB_UART_Fun_Sel((GLB_UART_SIG_Type)GLB_UART_SIG_FUN_UART1_TXD, (GLB_UART_SIG_FUN_Type)GLB_UART_SIG_9); - - } else { - cfg.gpioPin = GLB_GPIO_PIN_8; - cfg.gpioFun = GPIO_FUN_UART; - cfg.gpioMode = GPIO_MODE_OUTPUT; - GLB_GPIO_Init(&cfg); - - GLB_UART_Sig_Swap_Set(GLB_UART_SIG_SWAP_GRP_GPIO0_GPIO11, 0); - GLB_UART_Fun_Sel(GLB_UART_SIG_8, GLB_UART_SIG_FUN_UART1_TXD); - GLB_UART_Fun_Sel((GLB_UART_SIG_Type)GLB_UART_SIG_FUN_UART1_TXD, (GLB_UART_SIG_FUN_Type)GLB_UART_SIG_8); - } -} - -/** - * @brief hal_boot2_debug_usb_port_init - * - * @return - */ -#if HAL_BOOT2_SUPPORT_USB_IAP -void hal_boot2_debug_usb_port_init(void) -{ -} -#endif - -/** - * @brief hal_boot2_debug_uart_gpio_deinit - * - * @return - */ -void hal_boot2_debug_uart_gpio_deinit(void) -{ -} - -/****************************************************************************/ /** - * @brief Check bootheader crc - * - * @param data: bootheader data pointer - * - * @return boot_error_code type - * -*******************************************************************************/ -static uint32_t hal_boot_check_bootheader(struct hal_bootheader_t *header) -{ - uint32_t crc_pass = 0; - uint32_t crc; - - if (header->basic_cfg.crc_ignore == 1 && header->crc32 == HAL_BOOT2_DEADBEEF_VAL) { - //MSG("Crc ignored\r\n"); - crc_pass = 1; - } else { - crc = BFLB_Soft_CRC32((uint8_t *)header, sizeof(struct hal_bootheader_t) - sizeof(header->crc32)); - - if (header->crc32 == crc) { - crc_pass = 1; - } - } - return crc_pass; -} - -/****************************************************************************/ /** - * @brief Check if the input public key is the same as burned in the efuse - * - * @param g_boot_img_cfg: Boot image config pointer - * @param data: Image data pointer - * - * @return boot_error_code type - * -*******************************************************************************/ -int32_t hal_boot_parse_bootheader(boot2_image_config *boot_img_cfg, uint8_t *data) -{ - struct hal_bootheader_t *header = (struct hal_bootheader_t *)data; - uint32_t crc_pass = 0; - uint32_t i = 0; - uint32_t *phash = (uint32_t *)header->basic_cfg.hash; - - crc_pass = hal_boot_check_bootheader(header); - - if (!crc_pass) { - //MSG_ERR("bootheader crc error\r\n"); - //blsp_dump_data((uint8_t *)&crc, 4); - return 0x0204; - } - - if (header->basic_cfg.notload_in_bootrom) { - return 0x0202; - } - - /* Get which CPU's img it is*/ - for (i = 0; i < HAL_BOOT2_CPU_MAX; i++) { - if (0 == memcmp((void *)&header->magiccode, HAL_BOOT2_CPU0_MAGIC, - sizeof(header->magiccode))) { - break; - } else if (0 == memcmp((void *)&header->magiccode, HAL_BOOT2_CPU1_MAGIC, - sizeof(header->magiccode))) { - break; - } - } - - if (i == HAL_BOOT2_CPU_MAX) { - /* No cpu img magic match */ - //MSG_ERR("Magic code error\r\n"); - return 0x0203; - } - - if (boot_img_cfg == NULL) { - return 0; - } - - boot_img_cfg->pk_src = i; - boot_img_cfg->img_valid = 0; - - arch_memcpy_fast(&boot_img_cfg->basic_cfg, &header->basic_cfg, - sizeof(header->basic_cfg)); - - /* Check encrypt and sign match*/ - if (g_efuse_cfg.encrypted[i] != boot_img_cfg->basic_cfg.encrypt_type) { - if (boot_img_cfg->basic_cfg.xts_mode == 0) { - //("Encrypt not fit\r\n"); - return 0x0205; - } - } - - if (g_efuse_cfg.sign[i] != boot_img_cfg->basic_cfg.sign_type) { - //MSG_ERR("sign not fit\r\n"); - boot_img_cfg->basic_cfg.sign_type = g_efuse_cfg.sign[i]; - return 0x0206; - } - - if (g_ps_mode == 1 && (!g_efuse_cfg.hbn_check_sign)) { - /* In HBN Mode, if user select to ignore hash and sign*/ - boot_img_cfg->basic_cfg.hash_ignore = 1; - } else if ((boot_img_cfg->basic_cfg.hash_ignore == 1 && *phash != HAL_BOOT2_DEADBEEF_VAL) || - g_efuse_cfg.sign[i] != 0) { - /* If signed or user not really want to ignore, hash can't be ignored*/ - boot_img_cfg->basic_cfg.hash_ignore = 0; - } - - if (g_user_hash_ignored) { - boot_img_cfg->basic_cfg.hash_ignore = 1; - } - - if (boot_img_cfg->basic_cfg.img_len_cnt == 0) { - return 0x0207; - } - - arch_memcpy_fast(&boot_img_cfg->cpu_cfg, &header->cpu_cfg, - sizeof(header->cpu_cfg)); - return 0; -} - -void ATTR_TCM_SECTION hal_boot2_clean_cache(void) -{ - L1C_DCache_Clean_Invalid_All(); - L1C_ICache_Invalid_All(); -} - -BL_Err_Type ATTR_TCM_SECTION hal_boot2_set_cache(uint8_t cont_read, boot2_image_config *boot_img_cfg) -{ - flash_set_cache(cont_read, boot_img_cfg->cpu_cfg[0].cache_enable, - boot_img_cfg->cpu_cfg[0].cache_way_dis, - boot_img_cfg->basic_cfg.group_image_offset); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get the ram image name and count - * - * @param img_name: ram image name in partition - * @param ram_img_cnt: ram image count that support boot from flash - * - * @return None - * -*******************************************************************************/ -void hal_boot2_get_ram_img_cnt(char *img_name[], uint32_t *ram_img_cnt) -{ - *ram_img_cnt = 5; - img_name[0] = "Imgload"; - img_name[1] = "SBI"; - img_name[2] = "Kernel"; - img_name[3] = "Rootfs"; - img_name[4] = "DTB"; -} - -/****************************************************************************/ /** - * @brief get the ram image info - * - * @param data: bootheader information - * @param image_offset: ram image offset in flash(from of bootheader) - * @param img_len: ram image length - * @param hash: pointer to hash pointer - * - * @return None - * -*******************************************************************************/ -void hal_boot2_get_img_info(uint8_t *data, uint32_t *image_offset, uint32_t *img_len, uint8_t **hash) -{ - struct hal_bootheader_t *header = (struct hal_bootheader_t *)data; - uint32_t crc_pass = 0; - *img_len = 0; - uint8_t *phash = *hash; - uint8_t hash_ignore = 1; - - crc_pass = hal_boot_check_bootheader(header); - - if (!crc_pass) { - return; - } - if (0 != memcmp((void *)&header->magiccode, HAL_BOOT2_CPU0_MAGIC, sizeof(header->magiccode)) && - 0 != memcmp((void *)&header->magiccode, HAL_BOOT2_CPU1_MAGIC, sizeof(header->magiccode))) { - return; - } - - /* for ram image, it always download in iot tab, so - it share the same group with core 0 but use different image offset and - boot entry */ - *image_offset = 4096 * 1; //bootheader->basic_cfg.group_image_offset; - *img_len = header->basic_cfg.img_len_cnt; - - if (g_ps_mode == 1 && (!g_efuse_cfg.hbn_check_sign)) { - /* In HBN Mode, if user select to ignore hash and sign*/ - hash_ignore = 1; - } else if ((header->basic_cfg.hash_ignore == 1 && header->basic_cfg.hash[0] != HAL_BOOT2_DEADBEEF_VAL) || - g_efuse_cfg.sign[0] != 0) { - /* If signed or user not really want to ignore, hash can't be ignored*/ - hash_ignore = 0; - } - - if (hash_ignore == 1) { - *hash = NULL; - } else { - memcpy(phash, header->basic_cfg.hash, sizeof(header->basic_cfg.hash)); - } -} - -/****************************************************************************/ /** - * @brief release other cpu to boot up - * - * @param core: core number - * @param boot_addr: boot address - * - * @return None - * -*******************************************************************************/ -void ATTR_TCM_SECTION hal_boot2_release_cpu(uint32_t core, uint32_t boot_addr) -{ - GLB_Set_CPU_Reset_Address(core, boot_addr); - GLB_Release_CPU(core); -} - -/****************************************************************************/ /** - * @brief get xip address according to flash addr - * - * @param flash_addr: flash address - * - * @return XIP Address - * -*******************************************************************************/ -uint32_t hal_boot2_get_xip_addr(uint32_t flash_addr) -{ - uint32_t img_offset = SF_Ctrl_Get_Flash_Image_Offset(0, SF_CTRL_FLASH_BANK0); - if (flash_addr >= img_offset) { - return BL808_FLASH_XIP_BASE + (flash_addr - img_offset); - } else { - return 0; - } -} - -/****************************************************************************/ /** - * @brief get if multi-group - * - * @param None - * - * @return 1 for multi-group 0 for not - * -*******************************************************************************/ -uint32_t hal_boot2_get_grp_count(void) -{ - return 2; -} - -/****************************************************************************/ /** - * @brief get cpu count - * - * @param None - * - * @return 1 for multi-group 0 for not - * -*******************************************************************************/ -uint32_t hal_boot2_get_cpu_count(void) -{ - return 3; -} - -/****************************************************************************/ /** - * @brief get cpu count - * - * @param None - * - * @return 1 for multi-group 0 for not - * -*******************************************************************************/ -uint32_t ATTR_TCM_SECTION hal_boot2_get_feature_flag(void) -{ - return HAL_BOOT2_MP_FLAG; -} - -/****************************************************************************/ /** - * @brief get boot header offset - * - * @param None - * - * @return bootheader offset - * -*******************************************************************************/ -uint32_t hal_boot2_get_bootheader_offset(void) -{ - return 0x0; -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_clock.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_clock.c deleted file mode 100644 index e5faf33475..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_clock.c +++ /dev/null @@ -1,305 +0,0 @@ -/** - * @file hal_clock.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ - -#include "bl808_glb.h" -#include "hal_clock.h" - -static void peripheral_clock_gate_all() -{ - uint32_t tmpVal; - tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1); - tmpVal &= (~(1 << 2)); //gpip - tmpVal &= (~(1 << 3)); //sec_dbg - tmpVal &= (~(1 << 4)); //sec_eng - tmpVal &= (~(1 << 5)); //sec_eng - tmpVal &= (~(1 << 12)); //dma - tmpVal &= (~(1 << 13)); //usb - tmpVal &= (~(1 << 16)); //uart0 - tmpVal &= (~(1 << 17)); //uart1 - tmpVal &= (~(1 << 18)); //spi - tmpVal &= (~(1 << 19)); //i2c - tmpVal &= (~(1 << 20)); //pwm - tmpVal &= (~(1 << 21)); //timer - tmpVal &= (~(1 << 22)); //ir - tmpVal &= (~(1 << 23)); //cks - tmpVal &= (~(1 << 25)); //i2c1 - tmpVal &= (~(1 << 26)); //uart2 - tmpVal &= (~(1 << 27)); //i2s - BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG2); - tmpVal &= (~(1 << 4)); //wifi - tmpVal &= (~(1 << 8)); //bt/ble - tmpVal &= (~(1 << 9)); //m154 - tmpVal &= (~(1 << 10)); //bt/ble - tmpVal &= (~(1 << 11)); //m154 - tmpVal &= (~(1 << 19)); //emac - //tmpVal &= (~(1 << 21)); //audio - tmpVal &= (~(1 << 22)); //sdh - BL_WR_REG(GLB_BASE, GLB_CGEN_CFG2, tmpVal); -} - -void system_clock_init(void) -{ - GLB_Power_On_XTAL_And_PLL_CLK(XTAL_TYPE, GLB_PLL_WIFIPLL | - GLB_PLL_CPUPLL | - GLB_PLL_UHSPLL | - GLB_PLL_MIPIPLL); - -#if BSP_ROOT_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK -#if XTAL_TYPE == INTERNAL_RC_32M - GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_RC32M); -#else - GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_XTAL); -#endif -#elif BSP_ROOT_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_WIFIPLL_240M - GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_WIFIPLL_240M); -#elif BSP_ROOT_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_WIFIPLL_320M - GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_WIFIPLL_320M); -#else -#error "do not support current root clock source" -#endif - GLB_Set_MCU_System_CLK_Div(BSP_HCLK_DIV, BSP_BCLK_DIV, BSP_LPCLK_DIV); -#if BSP_CLOCK_SOURCE_MUXPLL_160M == ROOT_CLOCK_SOURCE_WIFIPLL_160M - GLB_Set_MCU_Muxpll_160M_Sel(0); -#elif BSP_CLOCK_SOURCE_MUXPLL_160M == ROOT_CLOCK_SOURCE_CPUPLL_160M - GLB_Set_MCU_Muxpll_160M_Sel(1); -#elif BSP_CLOCK_SOURCE_MUXPLL_160M == ROOT_CLOCK_SOURCE_AUPLL_DIV2 - GLB_Set_MCU_Muxpll_160M_Sel(2); -#elif BSP_CLOCK_SOURCE_MUXPLL_160M == ROOT_CLOCK_SOURCE_AUPLL_DIV2P5 - GLB_Set_MCU_Muxpll_160M_Sel(3); -#else -#error "do not support current muxpll 160m clock source" -#endif - -#if BSP_CLOCK_SOURCE_MUXPLL_80M == ROOT_CLOCK_SOURCE_WIFIPLL_80M - GLB_Set_MCU_Muxpll_80M_Sel(0); -#elif BSP_CLOCK_SOURCE_MUXPLL_80M == ROOT_CLOCK_SOURCE_CPUPLL_80M - GLB_Set_MCU_Muxpll_80M_Sel(1); -#elif BSP_CLOCK_SOURCE_MUXPLL_80M == ROOT_CLOCK_SOURCE_AUPLL_DIV5 - GLB_Set_MCU_Muxpll_80M_Sel(2); -#elif BSP_CLOCK_SOURCE_MUXPLL_80M == ROOT_CLOCK_SOURCE_AUPLL_DIV6 - GLB_Set_MCU_Muxpll_80M_Sel(3); -#else -#error "do not support current muxpll 80m clock source" -#endif - - GLB_Set_DSP_System_CLK(GLB_DSP_SYS_CLK_CPUPLL_400M); - - CPU_Set_MTimer_CLK(ENABLE, CPU_Get_MTimer_Source_Clock() / 1000 / 1000 - 1); -} - -void peripheral_clock_init(void) -{ - uint32_t tmpVal; - - peripheral_clock_gate_all(); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1); -#if defined(BSP_USING_UART0) || defined(BSP_USING_UART1) || defined(BSP_USING_UART2) -#if defined(BSP_USING_UART0) - tmpVal |= (1 << 16); -#endif -#if defined(BSP_USING_UART1) - tmpVal |= (1 << 17); -#endif -#if defined(BSP_USING_UART2) - tmpVal |= (1 << 26); -#endif - -#if BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK - GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_XCLK, BSP_UART_CLOCK_DIV); -#elif BSP_UART_CLOCK_SOURCE == BSP_CLOCK_SOURCE_BCLK - GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_MCU_PBCLK, BSP_UART_CLOCK_DIV); -#elif BSP_UART_CLOCK_SOURCE == BSP_CLOCK_SOURCE_MUXPLL_160M - GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_160M, BSP_UART_CLOCK_DIV); -#else -#error "do not support current uart clock source" -#endif -#endif - -#if defined(BSP_USING_UART3) -#if BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK - GLB_Set_DSP_UART0_CLK(ENABLE, GLB_DSP_UART_CLK_DSP_XCLK, BSP_UART_CLOCK_DIV); -#elif BSP_UART_CLOCK_SOURCE == BSP_CLOCK_SOURCE_BCLK - GLB_Set_DSP_UART0_CLK(ENABLE, GLB_DSP_UART_CLK_DSP_PBCLK, BSP_UART_CLOCK_DIV); -#elif BSP_UART_CLOCK_SOURCE == BSP_CLOCK_SOURCE_MUXPLL_160M - GLB_Set_DSP_UART0_CLK(ENABLE, GLB_DSP_UART_CLK_MUXPLL_160M, BSP_UART_CLOCK_DIV); -#else -#error "do not support current uart clock source" -#endif -#endif - -#if defined(BSP_USING_I2C0) || defined(BSP_USING_I2C1) -#if defined(BSP_USING_I2C0) - tmpVal |= (1 << 19); -#elif defined(BSP_USING_I2C1) - tmpVal |= (1 << 25); -#endif - -#if BSP_I2C_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK - GLB_Set_I2C_CLK(ENABLE, GLB_I2C_CLK_XCLK, BSP_I2C_CLOCK_DIV); -#elif BSP_I2C_CLOCK_SOURCE == BSP_CLOCK_SOURCE_BCLK - GLB_Set_I2C_CLK(ENABLE, GLB_I2C_CLK_BCLK, BSP_I2C_CLOCK_DIV); -#else -#error "do not support current i2c clock source" -#endif -#endif - -#if defined(BSP_USING_I2C2) -#if BSP_I2C_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK - GLB_Set_DSP_I2C0_CLK(ENABLE, GLB_I2C_CLK_XCLK, BSP_I2C_CLOCK_DIV); -#elif BSP_I2C_CLOCK_SOURCE == BSP_CLOCK_SOURCE_BCLK - GLB_Set_DSP_I2C0_CLK(ENABLE, GLB_I2C_CLK_BCLK, BSP_I2C_CLOCK_DIV); -#else -#error "do not support current i2c clock source" -#endif -#endif - -#if defined(BSP_USING_I2C3) -#if BSP_I2C_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK - GLB_Set_DSP_I2C1_CLK(ENABLE, GLB_I2C_CLK_XCLK, BSP_I2C_CLOCK_DIV); -#elif BSP_I2C_CLOCK_SOURCE == BSP_CLOCK_SOURCE_BCLK - GLB_Set_DSP_I2C1_CLK(ENABLE, GLB_I2C_CLK_BCLK, BSP_I2C_CLOCK_DIV); -#else -#error "do not support current i2c clock source" -#endif -#endif - -#if defined(BSP_USING_SPI0) - tmpVal |= (1 << 18); -#if BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK - GLB_Set_SPI_CLK(ENABLE, GLB_SPI_CLK_XCLK, BSP_SPI_CLOCK_DIV); -#elif BSP_UART_CLOCK_SOURCE == BSP_CLOCK_SOURCE_MUXPLL_160M - GLB_Set_SPI_CLK(ENABLE, GLB_SPI_CLK_MCU_MUXPLL_160M, BSP_SPI_CLOCK_DIV); -#else -#error "do not support current spi clock source" -#endif -#endif - -#if defined(BSP_USING_SPI1) -#if BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK - GLB_Set_DSP_SPI_CLK(ENABLE, GLB_DSP_SPI_CLK_DSP_XCLK, BSP_SPI_CLOCK_DIV); -#elif BSP_UART_CLOCK_SOURCE == BSP_CLOCK_SOURCE_MUXPLL_160M - GLB_Set_DSP_SPI_CLK(ENABLE, GLB_DSP_SPI_CLK_DSP_MUXPLL_160M, BSP_SPI_CLOCK_DIV); -#else -#error "do not support current spi clock source" -#endif -#endif - -#if defined(BSP_USING_ADC0) - tmpVal |= (1 << 2); -#if BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL_CLK - GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_AUPLL, BSP_ADC_CLOCK_DIV); -#elif BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK - GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, BSP_ADC_CLOCK_DIV); -#else -#error "do not support current adc clock source" -#endif -#endif - -#if defined(BSP_USING_DAC0) - tmpVal |= (1 << 2); -#if BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_WIFIPLL_32M - //GLB_Set_DAC_CLK(ENABLE, GLB_DAC_CLK_32M, BSP_DAC_CLOCK_DIV); -#elif BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK - //GLB_Set_DAC_CLK(ENABLE, GLB_DAC_CLK_XCLK, BSP_DAC_CLOCK_DIV); -#else -#error "do not support current dac clock source" -#endif -#endif - -#if defined(BSP_USING_USB) - tmpVal |= (1 << 13); - GLB_Set_USB_CLK_From_WIFIPLL(1); -#endif -#if defined(BSP_USING_SDH) - uint32_t tmp_val; - tmp_val = BL_RD_REG(PDS_BASE, PDS_CTL5); - uint32_t tmp_val2 = BL_GET_REG_BITS_VAL(tmp_val, PDS_CR_PDS_GPIO_KEEP_EN); - tmp_val2 &= ~(1 << 0); - tmp_val = BL_SET_REG_BITS_VAL(tmp_val, PDS_CR_PDS_GPIO_KEEP_EN, tmp_val2); - BL_WR_REG(PDS_BASE, PDS_CTL5, tmp_val); - - GLB_Set_SDH_CLK(1, GLB_SDH_CLK_WIFIPLL_96M, 0); - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_SDH); - GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_SDH); -#endif - tmpVal |= (1 << 12); //enable dma - BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal); - - GLB_Set_DSP_DSP2_CLK(1, GLB_DSP_DSP2_CLK_CPUPLL_400M, 0); -} - -uint32_t system_clock_get(enum system_clock_type type) -{ - switch (type) { - case SYSTEM_CLOCK_ROOT_CLOCK: - return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_ROOT_CLK); - - case SYSTEM_CLOCK_FCLK: - return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_CLK); - - case SYSTEM_CLOCK_BCLK: - return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_BCLK); - - case SYSTEM_CLOCK_XCLK: - return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_XCLK); - - case SYSTEM_CLOCK_DSP_CLK: - return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_DSP_CLK); - - case SYSTEM_CLOCK_DSP_BCLK: - return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_DSP_BCLK); - - case SYSTEM_CLOCK_DSP_PBCLK: - return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_DSP_PBCLK); - - case SYSTEM_CLOCK_LP_CLK: - return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_LP_CLK); - - case SYSTEM_CLOCK_32K_CLK: - return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_F32K); - - default: - break; - } - return 0; -} - -uint32_t peripheral_clock_get(enum peripheral_clock_type type) -{ - return 0; -} - -void system_mtimer_clock_init(void) -{ - CPU_Reset_MTimer(); - /* set mtimer clock 1M */ - CPU_Set_MTimer_CLK(ENABLE, CPU_Get_MTimer_Source_Clock() / 1000000); -} - -void system_mtimer_clock_reinit(void) -{ - /* ToDo */ -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_common.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_common.c deleted file mode 100644 index 2085fa0287..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_common.c +++ /dev/null @@ -1,141 +0,0 @@ -/** - * @file hal_common.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#include "hal_common.h" -#include "bl808_l1c.h" -#include "bl808_glb.h" -#include "bl808_hbn.h" - -volatile uint32_t nesting = 0; - -void ATTR_TCM_SECTION cpu_global_irq_enable(void) -{ - nesting--; - if (nesting == 0) { - __enable_irq(); - } -} - -void ATTR_TCM_SECTION cpu_global_irq_disable(void) -{ - __disable_irq(); - nesting++; -} - -void hal_por_reset(void) -{ - GLB_SW_POR_Reset(); -} - -void hal_system_reset(void) -{ - GLB_SW_System_Reset(); -} - -void hal_cpu_reset(void) -{ - GLB_SW_CPU_Reset(); -} - -void hal_reboot_config(hal_reboot_cfg_t rbot) -{ - switch(rbot){ - case HAL_REBOOT_AS_BOOTPIN: - HBN_Set_Hand_Off_Config(0); - break; - case HAL_REBOOT_FROM_INTERFACE: - HBN_Set_Hand_Off_Config(1); - break; - case HAL_REBOOT_FROM_MEDIA: - HBN_Set_Hand_Off_Config(2); - break; - default : - HBN_Set_Hand_Off_Config(0); - break; - } -} - -void ATTR_TCM_SECTION hal_dcache_clean_all(void) -{ - L1C_DCache_Clean_All(); -} - -void ATTR_TCM_SECTION hal_dcache_invalid_all(void) -{ - L1C_DCache_Invalid_All(); -} - -void ATTR_TCM_SECTION hal_dcache_clean_invalid_all(void) -{ - L1C_DCache_Clean_Invalid_All(); -} - -void ATTR_TCM_SECTION hal_dcache_clean_byaddr(uintptr_t addr, uint32_t len) -{ - int64_t op_size = len + (uint64_t)addr % 32; - uint64_t op_addr = (uint64_t)addr & CACHE_INV_ADDR_Msk; - int64_t linesize = 32; - - __DSB(); - - while (op_size > 0) { - __DCACHE_CPA(op_addr); - op_addr += linesize; - op_size -= linesize; - } - - __DSB(); -} - -void ATTR_TCM_SECTION hal_dcache_invalidate_byaddr(uintptr_t addr, uint32_t len) -{ - int64_t op_size = len + (uint64_t)addr % 32; - uint64_t op_addr = (uint64_t)addr; - int64_t linesize = 32; - - __DSB(); - - while (op_size > 0) { - __DCACHE_IPA(op_addr); - op_addr += linesize; - op_size -= linesize; - } - - __DSB(); -} - -void ATTR_TCM_SECTION hal_dcache_clean_invalidate_byaddr(uintptr_t addr, uint32_t len) -{ - int64_t op_size = len + (uint64_t)addr % 32; - uint64_t op_addr = (uint64_t)addr; - int64_t linesize = 32; - - __DSB(); - - while (op_size > 0) { - __DCACHE_CIPA(op_addr); - op_addr += linesize; - op_size -= linesize; - } - - __DSB(); -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_dac.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_dac.c deleted file mode 100644 index 1f97804753..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_dac.c +++ /dev/null @@ -1,324 +0,0 @@ -/** - * @file hal_dac.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#include "hal_dac.h" -#include "hal_dma.h" -#include "bl808_dac.h" -#include "bl808_glb.h" -#include "dac_config.h" - -static dac_device_t dacx_device[] = { -#ifdef BSP_USING_DAC0 - DAC_CONFIG, -#endif -}; - -static uint8_t dac_channel_enable_check = 0; -/** - * @brief - * - * @param dev - * @param oflag - * @return int - */ -int dac_open(struct device *dev, uint16_t oflag) -{ - dac_device_t *dac_device = (dac_device_t *)dev; - uint8_t dac_div = 0; - uint32_t tmpVal; - - uint32_t dac_clk = Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_DAC); - - if ((GLB_GPIO_Get_Fun(GLB_GPIO_PIN_11) == GPIO_FUN_ANALOG) && (dac_device->channels & DAC_CHANNEL_0)) { - dac_channel_enable_check |= DAC_CHANNEL_0; - } - if ((GLB_GPIO_Get_Fun(GLB_GPIO_PIN_17) == GPIO_FUN_ANALOG) && (dac_device->channels & DAC_CHANNEL_1)) { - dac_channel_enable_check |= DAC_CHANNEL_1; - } - - if (dac_channel_enable_check == 0) { - return -1; - } - - switch (dac_device->sample_freq) { - case DAC_SAMPLE_FREQ_500KHZ: - dac_div = dac_clk / 500000; - break; - - case DAC_SAMPLE_FREQ_8KHZ: - dac_div = dac_clk / 8000; - break; - - case DAC_SAMPLE_FREQ_16KHZ: - dac_div = dac_clk / 16000; - break; - - case DAC_SAMPLE_FREQ_44P1KHZ: - dac_div = dac_clk / 441000; - break; - - default: - break; - } - - if (dac_div == 1) { - dac_div = DAC_CLK_DIV_1; - } else if (dac_div == 16) { - dac_div = DAC_CLK_DIV_16; - } else if (dac_div == 32) { - dac_div = DAC_CLK_DIV_32; - } else if (dac_div == 64) { - dac_div = DAC_CLK_DIV_64; - } else - return -2; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DAC_CFG0); - /*dac vref select*/ - if (dac_device->vref == DAC_VREF_EXTERNAL) { - if (GLB_GPIO_Get_Fun(GLB_GPIO_PIN_7) != GPIO_FUN_ANALOG) - return -1; - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDAC_REF_SEL); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPDAC_REF_SEL); - } - BL_WR_REG(GLB_BASE, GLB_DAC_CFG0, tmpVal); - - /*dac reset*/ - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPDACA_RSTN_ANA); - BL_WR_REG(GLB_BASE, GLB_DAC_CFG0, tmpVal); - __NOP(); - __NOP(); - __NOP(); - __NOP(); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPDACB_RSTN_ANA); - BL_WR_REG(GLB_BASE, GLB_DAC_CFG0, tmpVal); - __NOP(); - __NOP(); - __NOP(); - __NOP(); - - /* dac clear reset */ - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDACA_RSTN_ANA); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDACB_RSTN_ANA); - BL_WR_REG(GLB_BASE, GLB_DAC_CFG0, tmpVal); - - /* Set DAC div */ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_MODE, dac_div); - BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); - - /* select source */ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_CH_A_SEL, GPIP_DAC_ChanA_SRC_REG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_CH_B_SEL, GPIP_DAC_ChanB_SRC_REG); - BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); - - /* GPIP enable or disable channel */ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPDAC_EN); - BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); - - /* GLB enable or disable channel */ - if (dac_channel_enable_check & DAC_CHANNEL_0) { - /* a channel */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_DAC_CFG1); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDAC_IOA_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDAC_A_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_A_RNG, DAC_REF_RNG_DEFAULT_SELECT); - tmpVal = BL_WR_REG(GLB_BASE, GLB_DAC_CFG1, tmpVal); - } - if (dac_channel_enable_check & DAC_CHANNEL_1) { - /* b channel */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_DAC_CFG2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_B_RNG, DAC_REF_RNG_DEFAULT_SELECT); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDAC_IOB_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDAC_B_EN); - tmpVal = BL_WR_REG(GLB_BASE, GLB_DAC_CFG2, tmpVal); - } - - /* GPIP disable DMA */ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPDAC_DMA_TX_EN); - BL_WR_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG, tmpVal); - - if (oflag & DEVICE_OFLAG_DMA_TX) { - /* GPIP select source */ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_CH_A_SEL, GPIP_DAC_ChanA_SRC_DMA); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_CH_B_SEL, GPIP_DAC_ChanB_SRC_DMA); - BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); - - /* GPIP enable DMA */ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG); - if (dac_channel_enable_check == 2) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_DMA_FORMAT, GPIP_DAC_DMA_FORMAT_1); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_DMA_FORMAT, GPIP_DAC_DMA_FORMAT_0); - } - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPDAC_DMA_TX_EN); - BL_WR_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG, tmpVal); - } - - return 0; -} -/** - * @brief - * - * @param dev - * @return int - */ -int dac_close(struct device *dev) -{ - GLB_GPIP_DAC_ChanA_Cfg_Type chCfg = { 0 }; - GLB_GPIP_DAC_Cfg_Type dacCfg = { 0 }; - GLB_GPIP_DAC_Init(&dacCfg); - GLB_GPIP_DAC_Set_ChanA_Config(&chCfg); - GLB_GPIP_DAC_Set_ChanB_Config((GLB_GPIP_DAC_ChanB_Cfg_Type *)&chCfg); - GPIP_Set_DAC_DMA_TX_Disable(); - return 0; -} -/** - * @brief - * - * @param dev - * @param cmd - * @param args - * @return int - */ -int dac_control(struct device *dev, int cmd, void *args) -{ - dac_device_t *dac_device = (dac_device_t *)dev; - - switch (cmd) { - case DEVICE_CTRL_SET_INT: - - break; - - case DEVICE_CTRL_CLR_INT: - - break; - - case DEVICE_CTRL_GET_INT: - - break; - - case DEVICE_CTRL_CONFIG: - - break; - - case DEVICE_CTRL_RESUME: - - break; - - case DEVICE_CTRL_SUSPEND: - - break; - - case DEVICE_CTRL_ATTACH_TX_DMA: - dac_device->tx_dma = (struct device *)args; - break; - - default: - break; - } - - return 0; -} -/** - * @brief - * - * @param dev - * @param pos - * @param buffer - * @param size - * @return int - */ -int dac_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size) -{ - int ret = 0; - enum dac_sample_frequence channel = (enum dac_sample_frequence)pos; - dac_device_t *dac_device = (dac_device_t *)dev; - uint32_t i = 0; - - if (dev->oflag & DEVICE_OFLAG_DMA_TX) { - struct device *dma_ch = (struct device *)dac_device->tx_dma; - - if (!dma_ch) { - return -1; - } - - ret = dma_reload(dma_ch, (uint32_t)(uintptr_t)buffer, (uint32_t)DMA_ADDR_DAC_TDR, size); - dma_channel_start(dma_ch); - return ret; - } else if (dev->oflag & DEVICE_OFLAG_STREAM_TX) { - if (channel & DAC_CHANNEL_ALL) { - for (i = 0; i < size; i++) { - GLB_DAC_Set_ChanA_Value(*((uint16_t *)buffer + i)); - GLB_DAC_Set_ChanB_Value(*((uint16_t *)buffer + i)); - } - } else if (channel & DAC_CHANNEL_0) { - for (i = 0; i < size; i++) { - GLB_DAC_Set_ChanA_Value(*((uint16_t *)buffer + i)); - } - } else if (channel & DAC_CHANNEL_1) { - for (i = 0; i < size; i++) { - GLB_DAC_Set_ChanB_Value(*((uint16_t *)buffer + i)); - } - } else { - return -1; - } - return 0; - } - - return -1; -} - -/** - * @brief - * - * @param index - * @param name - * @return int - */ -int dac_register(enum dac_index_type index, const char *name) -{ - struct device *dev; - - if (DAC_MAX_INDEX == 0) { - return -DEVICE_EINVAL; - } - - dev = &(dacx_device[index].parent); - - dev->open = dac_open; - dev->close = dac_close; - dev->control = dac_control; - dev->write = dac_write; - dev->read = NULL; - - dev->type = DEVICE_CLASS_DAC; - dev->handle = NULL; - - device_register(dev, name); - - return 0; -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_dma.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_dma.c deleted file mode 100644 index 962226cc0f..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_dma.c +++ /dev/null @@ -1,562 +0,0 @@ -/** - * ***************************************************************************** - * @file hal_dma.c - * @version 0.1 - * @date 2021-03-01 - * @brief - * ***************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * ***************************************************************************** - */ -#include "hal_dma.h" -#include "bl808_dma.h" - -#define DMA_CHANNEL_BASE(id_base, ch) ((id_base) + DMA_CHANNEL_OFFSET + (ch)*0x100) - -__UNUSED__ static const uint32_t dma_channel_base[][8] = { - { - DMA_CHANNEL_BASE(DMA0_BASE, 0), - DMA_CHANNEL_BASE(DMA0_BASE, 1), - DMA_CHANNEL_BASE(DMA0_BASE, 2), - DMA_CHANNEL_BASE(DMA0_BASE, 3), - DMA_CHANNEL_BASE(DMA0_BASE, 4), - DMA_CHANNEL_BASE(DMA0_BASE, 5), - DMA_CHANNEL_BASE(DMA0_BASE, 6), - DMA_CHANNEL_BASE(DMA0_BASE, 7), - }, - { - DMA_CHANNEL_BASE(DMA1_BASE, 0), - DMA_CHANNEL_BASE(DMA1_BASE, 1), - DMA_CHANNEL_BASE(DMA1_BASE, 2), - DMA_CHANNEL_BASE(DMA1_BASE, 3), - DMA_CHANNEL_BASE(DMA1_BASE, 4), - DMA_CHANNEL_BASE(DMA1_BASE, 5), - DMA_CHANNEL_BASE(DMA1_BASE, 6), - DMA_CHANNEL_BASE(DMA1_BASE, 7), - }, - { - DMA_CHANNEL_BASE(DMA2_BASE, 0), - DMA_CHANNEL_BASE(DMA2_BASE, 1), - DMA_CHANNEL_BASE(DMA2_BASE, 2), - DMA_CHANNEL_BASE(DMA2_BASE, 3), - DMA_CHANNEL_BASE(DMA2_BASE, 4), - DMA_CHANNEL_BASE(DMA2_BASE, 5), - DMA_CHANNEL_BASE(DMA2_BASE, 6), - DMA_CHANNEL_BASE(DMA2_BASE, 7), - } - -}; - -void DMA0_IRQ(void); -void DMA1_IRQ(void); -void (*p_dma2_chn_irq[])(void); - -dma_device_t dmax_device[DMA_MAX_INDEX] = { -#ifdef BSP_USING_DMA0_CH0 - DMA0_CH0_CONFIG, -#endif -#ifdef BSP_USING_DMA0_CH1 - DMA0_CH1_CONFIG, -#endif -#ifdef BSP_USING_DMA0_CH2 - DMA0_CH2_CONFIG, -#endif -#ifdef BSP_USING_DMA0_CH3 - DMA0_CH3_CONFIG, -#endif -#ifdef BSP_USING_DMA0_CH4 - DMA0_CH4_CONFIG, -#endif -#ifdef BSP_USING_DMA0_CH5 - DMA0_CH5_CONFIG, -#endif -#ifdef BSP_USING_DMA0_CH6 - DMA0_CH6_CONFIG, -#endif -#ifdef BSP_USING_DMA0_CH7 - DMA0_CH7_CONFIG, -#endif -#ifdef BSP_USING_DMA1_CH0 - DMA1_CH0_CONFIG, -#endif -#ifdef BSP_USING_DMA1_CH1 - DMA1_CH1_CONFIG, -#endif -#ifdef BSP_USING_DMA1_CH2 - DMA1_CH2_CONFIG, -#endif -#ifdef BSP_USING_DMA1_CH3 - DMA1_CH3_CONFIG, -#endif -#ifdef BSP_USING_DMA1_CH4 - DMA1_CH4_CONFIG, -#endif -#ifdef BSP_USING_DMA1_CH5 - DMA1_CH5_CONFIG, -#endif -#ifdef BSP_USING_DMA1_CH6 - DMA1_CH6_CONFIG, -#endif -#ifdef BSP_USING_DMA1_CH7 - DMA1_CH7_CONFIG, -#endif -#ifdef BSP_USING_DMA2_CH0 - DMA2_CH0_CONFIG, -#endif -#ifdef BSP_USING_DMA2_CH1 - DMA2_CH1_CONFIG, -#endif -#ifdef BSP_USING_DMA2_CH2 - DMA2_CH2_CONFIG, -#endif -#ifdef BSP_USING_DMA2_CH3 - DMA2_CH3_CONFIG, -#endif -#ifdef BSP_USING_DMA2_CH4 - DMA2_CH4_CONFIG, -#endif -#ifdef BSP_USING_DMA2_CH5 - DMA2_CH5_CONFIG, -#endif -#ifdef BSP_USING_DMA2_CH6 - DMA2_CH6_CONFIG, -#endif -#ifdef BSP_USING_DMA2_CH7 - DMA2_CH7_CONFIG, -#endif -}; -/** - * @brief - * - * @param dev - * @param oflag - * @return int - */ -int dma_open(struct device *dev, uint16_t oflag) -{ -#ifdef BSP_USING_DMA - dma_device_t *dma_device = (dma_device_t *)dev; - DMA_Channel_Cfg_Type chCfg = { 0 }; - - /* Disable all interrupt */ - DMA_IntMask(dma_device->id, dma_device->ch, DMA_INT_ALL, MASK); - - /* disable cpu dma interrupt*/ - switch (dma_device->id) - { - case 0: - CPU_Interrupt_Disable(DMA0_ALL_IRQn); - break; - case 1: - CPU_Interrupt_Disable(DMA1_ALL_IRQn); - break; - case 2: - CPU_Interrupt_Disable(DMA2_INT0_IRQn + dma_device->ch); - break; - - default: - return 1; - } - - DMA_Disable(dma_device->id); - - DMA_Channel_Disable(dma_device->id, dma_device->ch); - - chCfg.ch = dma_device->ch; - chCfg.dir = dma_device->direction; - chCfg.srcPeriph = dma_device->src_req; - chCfg.dstPeriph = dma_device->dst_req; - chCfg.srcAddrInc = dma_device->src_addr_inc; - chCfg.destAddrInc = dma_device->dst_addr_inc; - chCfg.srcBurstSize = dma_device->src_burst_size; - chCfg.dstBurstSize = dma_device->dst_burst_size; - chCfg.srcTransfWidth = dma_device->src_width; - chCfg.dstTransfWidth = dma_device->dst_width; - DMA_Channel_Init(dma_device->id, &chCfg); - - DMA_Enable(dma_device->id); - if (dma_device->id == 0) { - Interrupt_Handler_Register(DMA0_ALL_IRQn, DMA0_IRQ); - /* Enable dma interrupt*/ - CPU_Interrupt_Enable(DMA0_ALL_IRQn); - } else if (dma_device->id == 1) { - Interrupt_Handler_Register(DMA1_ALL_IRQn, DMA1_IRQ); - /* Enable dma interrupt*/ - CPU_Interrupt_Enable(DMA1_ALL_IRQn); - } else if(dma_device->id == 2) { - Interrupt_Handler_Register(DMA2_INT0_IRQn + dma_device->ch, p_dma2_chn_irq[dma_device->ch]); - /* Enable dma interrupt*/ - CPU_Interrupt_Enable(DMA2_INT0_IRQn + dma_device->ch); - } -#endif - return 0; -} -/** - * @brief - * - * @param dev - * @param cmd - * @param args - * @return int - */ -int dma_control(struct device *dev, int cmd, void *args) -{ -#ifdef BSP_USING_DMA - dma_device_t *dma_device = (dma_device_t *)dev; - - switch (cmd) { - case DEVICE_CTRL_SET_INT: - DMA_IntMask(dma_device->id, dma_device->ch, DMA_INT_TCOMPLETED, UNMASK); - DMA_IntMask(dma_device->id, dma_device->ch, DMA_INT_ERR, UNMASK); - break; - - case DEVICE_CTRL_CLR_INT: - /* Dma interrupt configuration */ - DMA_IntMask(dma_device->id, dma_device->ch, DMA_INT_TCOMPLETED, MASK); - DMA_IntMask(dma_device->id, dma_device->ch, DMA_INT_ERR, MASK); - break; - - case DEVICE_CTRL_GET_INT: - break; - - case DEVICE_CTRL_CONFIG: - break; - - case DEVICE_CTRL_DMA_CHANNEL_UPDATE: - DMA_LLI_Update(dma_device->id, dma_device->ch, (uint32_t)(uintptr_t)args); - break; - - case DEVICE_CTRL_DMA_CHANNEL_GET_STATUS: - return DMA_Channel_Is_Busy(dma_device->id, dma_device->ch); - - case DEVICE_CTRL_DMA_CHANNEL_START: - DMA_Channel_Enable(dma_device->id, dma_device->ch); - break; - - case DEVICE_CTRL_DMA_CHANNEL_STOP: - DMA_Channel_Disable(dma_device->id, dma_device->ch); - break; - case DEVICE_CTRL_DMA_CONFIG_SI: { - uint32_t tmpVal = BL_RD_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_CONTROL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SI, ((uint32_t)(uintptr_t)args) & 0x01); - BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_CONTROL, tmpVal); - - } break; - case DEVICE_CTRL_DMA_CONFIG_DI: { - uint32_t tmpVal = BL_RD_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_CONTROL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DI, ((uint32_t)(uintptr_t)args) & 0x01); - BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_CONTROL, tmpVal); - - } break; - default: - break; - } -#endif - return 0; -} -/** - * @brief - * - * @param dev - * @return int - */ -int dma_close(struct device *dev) -{ -#ifdef BSP_USING_DMA - dma_device_t *dma_device = (dma_device_t *)dev; - DMA_Channel_Cfg_Type chCfg = { 0 }; - chCfg.ch = dma_device->ch; - - DMA_Channel_Disable(dma_device->id, dma_device->ch); - DMA_Channel_Init(dma_device->id, &chCfg); -#endif - return 0; -} - -int dma_register(enum dma_index_type index, const char *name) -{ -#ifdef BSP_USING_DMA - struct device *dev; - - if (DMA_MAX_INDEX == 0) { - return -DEVICE_EINVAL; - } - - dev = &(dmax_device[index].parent); - - dev->open = dma_open; - dev->close = dma_close; - dev->control = dma_control; - // dev->write = dma_write; - // dev->read = dma_read; - - dev->type = DEVICE_CLASS_DMA; - dev->handle = NULL; - - return device_register(dev, name); -#else - return 0; -#endif -} -/** - * @brief - * - * @param dev - * @param src_addr - * @param dst_addr - * @param transfer_size - * @return int - */ -int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_t transfer_size) -{ -#ifdef BSP_USING_DMA - uint32_t malloc_count; - uint32_t remain_len; - uint32_t actual_transfer_len = 0; - uint32_t actual_transfer_offset = 0; - dma_control_data_t dma_ctrl_cfg; - - dma_device_t *dma_device = (dma_device_t *)dev; - - DMA_Channel_Disable(dma_device->id, dma_device->ch); - - if (transfer_size == 0) { - return 0; - } - - switch (dma_device->src_width) { - case DMA_TRANSFER_WIDTH_8BIT: - actual_transfer_offset = 4064; - actual_transfer_len = transfer_size; - break; - case DMA_TRANSFER_WIDTH_16BIT: - if (transfer_size % 2) { - return -1; - } - actual_transfer_offset = 4064 << 1; - actual_transfer_len = transfer_size >> 1; - break; - case DMA_TRANSFER_WIDTH_32BIT: - if (transfer_size % 4) { - return -1; - } - actual_transfer_offset = 4064 << 2; - actual_transfer_len = transfer_size >> 2; - break; - - default: - return -3; - break; - } - - dma_ctrl_cfg = (dma_control_data_t)(BL_RD_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_CONTROL)); - - malloc_count = actual_transfer_len / 4064 + 1; - remain_len = actual_transfer_len % 4064; - - /* The maximum transfer capacity of the last node is 4095 */ - if(malloc_count > 1 && remain_len < (4095 - 4064)){ - malloc_count --; - remain_len += 4064; - } - - dma_device->lli_cfg = (dma_lli_ctrl_t *)realloc(dma_device->lli_cfg, sizeof(dma_lli_ctrl_t) * malloc_count); - - if (dma_device->lli_cfg) { - dma_ctrl_cfg.bits.TransferSize = 4064; - dma_ctrl_cfg.bits.I = 0; - /*transfer_size will be integer multiple of 4064*n or 4064*2*n or 4064*4*n,(n>0) */ - for (uint32_t i = 0; i < malloc_count; i++) { - dma_device->lli_cfg[i].src_addr = src_addr; - dma_device->lli_cfg[i].dst_addr = dst_addr; - dma_device->lli_cfg[i].nextlli = 0; - - if (dma_ctrl_cfg.bits.SI) { - src_addr += actual_transfer_offset; - } - - if (dma_ctrl_cfg.bits.DI) { - dst_addr += actual_transfer_offset; - } - - if (i == malloc_count - 1) { - dma_ctrl_cfg.bits.TransferSize = remain_len; - dma_ctrl_cfg.bits.I = 1; - - if (dma_device->transfer_mode == DMA_LLI_CYCLE_MODE) { - dma_device->lli_cfg[i].nextlli = (uint32_t)(uintptr_t)&dma_device->lli_cfg[0]; - } - } - - if (i) { - dma_device->lli_cfg[i - 1].nextlli = (uint32_t)(uintptr_t)&dma_device->lli_cfg[i]; - } - - dma_device->lli_cfg[i].cfg = dma_ctrl_cfg; - } - /* clean cache, DMA does not pass through the cache */ - csi_dcache_clean_range((void*)(dma_device->lli_cfg), sizeof(dma_lli_ctrl_t) * malloc_count); - - BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_SRCADDR, dma_device->lli_cfg[0].src_addr); - BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_DSTADDR, dma_device->lli_cfg[0].dst_addr); - BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_LLI, dma_device->lli_cfg[0].nextlli); - BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_CONTROL, dma_device->lli_cfg[0].cfg.WORD); - } else { - return -2; - } -#endif - return 0; -} - -/** - * @brief - * - * @param handle - */ -void dma_channel_isr(dma_device_t *handle) -{ -#ifdef BSP_USING_DMA - uint32_t tmpVal; - uint32_t intClr; - const uint32_t dmaAddr[] = { DMA0_BASE, DMA1_BASE, DMA2_BASE }; - - /* Get DMA register */ - uint32_t DMAChs = dmaAddr[handle->id]; - - if (!handle->parent.callback) { - return; - } - - tmpVal = BL_RD_REG(DMAChs, DMA_INTTCSTATUS); - if ((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCSTATUS) & (1 << handle->ch)) != 0) { - /* Clear interrupt */ - tmpVal = BL_RD_REG(DMAChs, DMA_INTTCCLEAR); - intClr = BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCCLEAR); - intClr |= (1 << handle->ch); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_INTTCCLEAR, intClr); - BL_WR_REG(DMAChs, DMA_INTTCCLEAR, tmpVal); - handle->parent.callback(&handle->parent, NULL, 0, DMA_INT_TCOMPLETED); - } - - tmpVal = BL_RD_REG(DMAChs, DMA_INTERRORSTATUS); - if ((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRORSTATUS) & (1 << handle->ch)) != 0) { - /*Clear interrupt */ - tmpVal = BL_RD_REG(DMAChs, DMA_INTERRCLR); - intClr = BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRCLR); - intClr |= (1 << handle->ch); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_INTERRCLR, intClr); - BL_WR_REG(DMAChs, DMA_INTERRCLR, tmpVal); - handle->parent.callback(&handle->parent, NULL, 0, DMA_INT_ERR); - } -#endif -} - -/** - * @brief - * - */ -void DMA0_IRQ(void) -{ - for (uint8_t i = 0; i < DMA_MAX_INDEX; i++) { - if (dmax_device[i].id == 0) { - dma_channel_isr(&dmax_device[i]); - } - } -} - -/** - * @brief - * - */ -void DMA1_IRQ(void) -{ - for (uint8_t i = 0; i < DMA_MAX_INDEX; i++) { - if (dmax_device[i].id == 1) { - dma_channel_isr(&dmax_device[i]); - } - } -} - -/** - * @brief - * - */ -void dma2_common_irq(uint8_t ch) -{ - for (uint8_t i = 0; i < DMA_MAX_INDEX; i++) { - if (dmax_device[i].id == 2 && dmax_device[i].ch == ch) { - dma_channel_isr(&dmax_device[i]); - } - } -} - -/** - * @brief - * - */ -void DMA2_CH0_IRQ(void) -{ - dma2_common_irq(0); -} - -void DMA2_CH1_IRQ(void) -{ - dma2_common_irq(1); -} - -void DMA2_CH2_IRQ(void) -{ - dma2_common_irq(2); -} - -void DMA2_CH3_IRQ(void) -{ - dma2_common_irq(3); -} - -void DMA2_CH4_IRQ(void) -{ - dma2_common_irq(4); -} - -void DMA2_CH5_IRQ(void) -{ - dma2_common_irq(5); -} - -void DMA2_CH6_IRQ(void) -{ - dma2_common_irq(6); -} - -void DMA2_CH7_IRQ(void) -{ - dma2_common_irq(7); -} - -void (*p_dma2_chn_irq[])(void) = {DMA2_CH0_IRQ, DMA2_CH1_IRQ, DMA2_CH2_IRQ, DMA2_CH3_IRQ, DMA2_CH4_IRQ, DMA2_CH5_IRQ, DMA2_CH6_IRQ, DMA2_CH7_IRQ}; diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_dsi.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_dsi.c deleted file mode 100644 index e87a5224d9..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_dsi.c +++ /dev/null @@ -1,932 +0,0 @@ -/** - * @file hal_dsi.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#include "hal_dsi.h" -#include "hal_clock.h" -#include "mipi_display.h" -#include "bl808_dsi.h" - -#define ENOSYS 123 -#define EINVAL 124 -#define ENOMEM 125 -#define ENODATA 126 - -/** - * mipi_dsi_packet_format_is_short - check if a packet is of the short format - * @type: MIPI DSI data type of the packet - * - * Return: true if the packet for the given data type is a short packet, false - * otherwise. - */ -bool mipi_dsi_packet_format_is_short(u8 type) -{ - switch (type) { - case MIPI_DSI_V_SYNC_START: - case MIPI_DSI_V_SYNC_END: - case MIPI_DSI_H_SYNC_START: - case MIPI_DSI_H_SYNC_END: - case MIPI_DSI_COMPRESSION_MODE: - case MIPI_DSI_END_OF_TRANSMISSION: - case MIPI_DSI_COLOR_MODE_OFF: - case MIPI_DSI_COLOR_MODE_ON: - case MIPI_DSI_SHUTDOWN_PERIPHERAL: - case MIPI_DSI_TURN_ON_PERIPHERAL: - case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM: - case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM: - case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM: - case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM: - case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM: - case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM: - case MIPI_DSI_DCS_SHORT_WRITE: - case MIPI_DSI_DCS_SHORT_WRITE_PARAM: - case MIPI_DSI_DCS_READ: - case MIPI_DSI_EXECUTE_QUEUE: - case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE: - return true; - } - - return false; -} - -/** - * mipi_dsi_packet_format_is_long - check if a packet is of the long format - * @type: MIPI DSI data type of the packet - * - * Return: true if the packet for the given data type is a long packet, false - * otherwise. - */ -bool mipi_dsi_packet_format_is_long(u8 type) -{ - switch (type) { - case MIPI_DSI_NULL_PACKET: - case MIPI_DSI_BLANKING_PACKET: - case MIPI_DSI_GENERIC_LONG_WRITE: - case MIPI_DSI_DCS_LONG_WRITE: - case MIPI_DSI_PICTURE_PARAMETER_SET: - case MIPI_DSI_COMPRESSED_PIXEL_STREAM: - case MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20: - case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24: - case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16: - case MIPI_DSI_PACKED_PIXEL_STREAM_30: - case MIPI_DSI_PACKED_PIXEL_STREAM_36: - case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12: - case MIPI_DSI_PACKED_PIXEL_STREAM_16: - case MIPI_DSI_PACKED_PIXEL_STREAM_18: - case MIPI_DSI_PIXEL_STREAM_3BYTE_18: - case MIPI_DSI_PACKED_PIXEL_STREAM_24: - return true; - } - - return false; -} - -/** - * mipi_dsi_controller_init() - Init DSI controller - * @dsi: DSI peripheral device - * - * Return: 0 on success or a negative error code on failure. - */ -int mipi_dsi_controller_init(const struct mipi_dsi_device *dsi) -{ - DSI_CFG_Type dsiCfg = { - .virtualChan = 0, /*!< DSI virtual channels */ - .laneNum = DSI_LANE_NUMBER_4, /*!< DSI lane numbers */ - .laneOrder = DSI_LANE_ORDER_3210, /*!< DSI lane order */ - .dataType = DSI_DATA_RGB888, /*!< DSI data type */ - .syncType = DSI_HS_SYNC_EVENT_MODE, /*!< HS sync event mode */ - .vsa = 10, /*!< HS vertical sync active width */ - .vfp = 10, /*!< HS vertical front porch width */ - }; - DSI_DPhy_CFG_Type dphyCfg = { - .time_clk_exit = 5, - .time_clk_trail = 3, - .time_clk_zero = 15, - .time_data_exit = 5, - .time_data_prepare = 2, - .time_data_trail = 3, - .time_data_zero = 15, - .time_lpx = 3, - .time_req_ready = 1, - .time_ta_get = 15, - .time_ta_go = 12, - .time_wakeup = 40001, - }; - DSI_Lane_Type usedLanes = DSI_LANE_CLOCK; - - dsiCfg.virtualChan = dsi->channel; - if (dsi->lanes == 1) { - dsiCfg.laneNum = DSI_LANE_NUMBER_1; - } else if(dsi->lanes == 2) { - dsiCfg.laneNum = DSI_LANE_NUMBER_2; - } else { - dsiCfg.laneNum = DSI_LANE_NUMBER_4; - } - dsiCfg.dataType = dsi->format; - - if (dsiCfg.laneNum == DSI_LANE_NUMBER_1) { - usedLanes |= DSI_LANE_DATA0; - } else if (dsiCfg.laneNum == DSI_LANE_NUMBER_2) { - usedLanes |= DSI_LANE_DATA0; - usedLanes |= DSI_LANE_DATA1; - } else if (dsiCfg.laneNum == DSI_LANE_NUMBER_4) { - usedLanes |= DSI_LANE_DATA0; - usedLanes |= DSI_LANE_DATA1; - usedLanes |= DSI_LANE_DATA2; - usedLanes |= DSI_LANE_DATA3; - } - - DSI_Init(DSI0_ID, &dsiCfg); - DSI_PHY_Reset(DSI0_ID); - DSI_PHY_Config(DSI0_ID, &dphyCfg); - DSI_PHY_Enable_Lanes(DSI0_ID, usedLanes); - return 0; -} - -static int mipi_dsi_device_transfer(const struct mipi_dsi_device *dsi, - struct mipi_dsi_msg *msg) -{ - DSI_LPDT_MSG_Type drvMsg = { - .dataType = msg->type, - .flag = msg->flags, /* MIPI_DSI_MSG_REQ_ACK or MIPI_DSI_MSG_USE_LPM*/ - .virtualChan = msg->channel, - .tx_buf = msg->tx_buf, - .tx_len = msg->tx_len, - .rx_buf = msg->rx_buf, - .rx_len = 0, - }; -#if 0 - const struct mipi_dsi_host_ops *ops = dsi->host->ops; - - if(!ops || !ops->transfer) - { - return -ENOSYS; - } - - if(dsi->mode_flags & MIPI_DSI_MODE_LPM) - { - msg->flags |= MIPI_DSI_MSG_USE_LPM; - } - - return ops->transfer(dsi->host, msg); -#endif - - if (mipi_dsi_packet_format_is_short(msg->type)) { - /* short packet */ - if (dsi->mode_flags & MIPI_DSI_MODE_LPM) { - /* use LPDT mode tx */ - if (SUCCESS != DSI_LPDT_Send_Short_Packet(DSI0_ID, &drvMsg)) { - return 0; - } - } else { - return 0; - } - } else { - /* long packet */ - if (dsi->mode_flags & MIPI_DSI_MODE_LPM) { - /* use LPDT mode tx */ - if (SUCCESS != DSI_LPDT_Send_Long_Packet(DSI0_ID, &drvMsg)) { - return 0; - } - } else { - return 0; - } - } - - /* get response */ - if (msg->flags & MIPI_DSI_MSG_REQ_ACK) { - if (dsi->mode_flags & MIPI_DSI_MODE_LPM) { - if (SUCCESS == DSI_LPDT_Recv_Packet(DSI0_ID, &drvMsg)) { - msg->rx_len = drvMsg.rx_len; - return msg->rx_len; - } else { - return 0; - } - } else { - return 0; - } - } - - return msg->tx_len; -} - -/** - * mipi_dsi_create_packet - create a packet from a message according to the - * DSI protocol - * @packet: pointer to a DSI packet structure - * @msg: message to translate into a packet - * - * Return: 0 on success or a negative error code on failure. - */ -int mipi_dsi_create_packet(struct mipi_dsi_packet *packet, - const struct mipi_dsi_msg *msg) -{ - if (!packet || !msg) { - return -EINVAL; - } - - /* do some minimum sanity checking */ - if (!mipi_dsi_packet_format_is_short(msg->type) && - !mipi_dsi_packet_format_is_long(msg->type)) { - return -EINVAL; - } - - if (msg->channel > 3) { - return -EINVAL; - } - - memset(packet, 0, sizeof(*packet)); - packet->header[0] = ((msg->channel & 0x3) << 6) | (msg->type & 0x3f); - - /* TODO: compute ECC if hardware support is not available */ - - /* - * Long write packets contain the word count in header bytes 1 and 2. - * The payload follows the header and is word count bytes long. - * - * Short write packets encode up to two parameters in header bytes 1 - * and 2. - */ - if (mipi_dsi_packet_format_is_long(msg->type)) { - packet->header[1] = (msg->tx_len >> 0) & 0xff; - packet->header[2] = (msg->tx_len >> 8) & 0xff; - - packet->payload_length = msg->tx_len; - packet->payload = msg->tx_buf; - } else { - const u8 *tx = msg->tx_buf; - - packet->header[1] = (msg->tx_len > 0) ? tx[0] : 0; - packet->header[2] = (msg->tx_len > 1) ? tx[1] : 0; - } - - packet->size = sizeof(packet->header) + packet->payload_length; - - return 0; -} - -/** - * mipi_dsi_shutdown_peripheral() - sends a Shutdown Peripheral command - * @dsi: DSI peripheral device - * - * Return: 0 on success or a negative error code on failure. - */ -int mipi_dsi_shutdown_peripheral(const struct mipi_dsi_device *dsi) -{ - struct mipi_dsi_msg msg = { - .channel = dsi->channel, - .type = MIPI_DSI_SHUTDOWN_PERIPHERAL, - .tx_buf = (u8[2]){ 0, 0 }, - .tx_len = 2, - }; - int ret = mipi_dsi_device_transfer(dsi, &msg); - - return (ret < 0) ? ret : 0; -} - -/* - * mipi_dsi_set_maximum_return_packet_size() - specify the maximum size of the - * the payload in a long packet transmitted from the peripheral back to the - * host processor - * @dsi: DSI peripheral device - * @value: the maximum size of the payload - * - * Return: 0 on success or a negative error code on failure. - */ -int mipi_dsi_set_maximum_return_packet_size(const struct mipi_dsi_device *dsi, - u16 value) -{ - u8 tx[2] = { value & 0xff, value >> 8 }; - struct mipi_dsi_msg msg = { - .channel = dsi->channel, - .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, - .tx_len = sizeof(tx), - .tx_buf = tx, - }; - int ret = mipi_dsi_device_transfer(dsi, &msg); - - return (ret < 0) ? ret : 0; -} - -/** - * mipi_dsi_compression_mode() - enable/disable DSC on the peripheral - * @dsi: DSI peripheral device - * @enable: Whether to enable or disable the DSC - * - * Enable or disable Display Stream Compression on the peripheral using the - * default Picture Parameter Set and VESA DSC 1.1 algorithm. - * - * Return: 0 on success or a negative error code on failure. - */ -int mipi_dsi_compression_mode(const struct mipi_dsi_device *dsi, bool enable) -{ - /* Note: Needs updating for non-default PPS or algorithm */ - u8 tx[2] = { enable << 0, 0 }; - struct mipi_dsi_msg msg = { - .channel = dsi->channel, - .type = MIPI_DSI_COMPRESSION_MODE, - .tx_len = sizeof(tx), - .tx_buf = tx, - }; - int ret = mipi_dsi_device_transfer(dsi, &msg); - - return (ret < 0) ? ret : 0; -} - -/** - * mipi_dsi_picture_parameter_set() - transmit the DSC PPS to the peripheral - * @dsi: DSI peripheral device - * @pps: VESA DSC 1.1 Picture Parameter Set - * - * Transmit the VESA DSC 1.1 Picture Parameter Set to the peripheral. - * - * Return: 0 on success or a negative error code on failure. - */ -int mipi_dsi_picture_parameter_set(const struct mipi_dsi_device *dsi, - const struct drm_dsc_picture_parameter_set *pps) -{ - struct mipi_dsi_msg msg = { - .channel = dsi->channel, - .type = MIPI_DSI_PICTURE_PARAMETER_SET, - .tx_len = sizeof(*pps), - .tx_buf = pps, - }; - int ret = mipi_dsi_device_transfer(dsi, &msg); - - return (ret < 0) ? ret : 0; -} - -/** - * mipi_dsi_generic_write() - transmit data using a generic write packet - * @dsi: DSI peripheral device - * @payload: buffer containing the payload - * @size: size of payload buffer - * - * This function will automatically choose the right data type depending on - * the payload length. - * - * Return: The number of bytes transmitted on success or a negative error code - * on failure. - */ -int mipi_dsi_generic_write(const struct mipi_dsi_device *dsi, const void *payload, - size_t size) -{ - struct mipi_dsi_msg msg = { - .channel = dsi->channel, - .tx_buf = payload, - .tx_len = size - }; - - switch (size) { - case 0: - msg.type = MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM; - break; - - case 1: - msg.type = MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM; - break; - - case 2: - msg.type = MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM; - break; - - default: - msg.type = MIPI_DSI_GENERIC_LONG_WRITE; - break; - } - - return mipi_dsi_device_transfer(dsi, &msg); -} - -/** - * mipi_dsi_generic_read() - receive data using a generic read packet - * @dsi: DSI peripheral device - * @params: buffer containing the request parameters - * @num_params: number of request parameters - * @data: buffer in which to return the received data - * @size: size of receive buffer - * - * This function will automatically choose the right data type depending on - * the number of parameters passed in. - * - * Return: The number of bytes successfully read or a negative error code on - * failure. - */ -int mipi_dsi_generic_read(const struct mipi_dsi_device *dsi, const void *params, - size_t num_params, void *data, size_t size) -{ - struct mipi_dsi_msg msg = { - .channel = dsi->channel, - .tx_len = num_params, - .tx_buf = params, - .rx_len = size, - .rx_buf = data - }; - - switch (num_params) { - case 0: - msg.type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM; - break; - - case 1: - msg.type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM; - break; - - case 2: - msg.type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM; - break; - - default: - return -EINVAL; - } - - return mipi_dsi_device_transfer(dsi, &msg); -} - -/** - * mipi_dsi_dcs_write_buffer() - transmit a DCS command with payload - * @dsi: DSI peripheral device - * @data: buffer containing data to be transmitted - * @len: size of transmission buffer - * - * This function will automatically choose the right data type depending on - * the command payload length. - * - * Return: The number of bytes successfully transmitted or a negative error - * code on failure. - */ -int mipi_dsi_dcs_write_buffer(const struct mipi_dsi_device *dsi, - const void *data, size_t len) -{ - struct mipi_dsi_msg msg = { - .channel = dsi->channel, - .tx_buf = data, - .tx_len = len - }; - - switch (len) { - case 0: - return -EINVAL; - - case 1: - msg.type = MIPI_DSI_DCS_SHORT_WRITE; - break; - - case 2: - msg.type = MIPI_DSI_DCS_SHORT_WRITE_PARAM; - break; - - default: - msg.type = MIPI_DSI_DCS_LONG_WRITE; - break; - } - - return mipi_dsi_device_transfer(dsi, &msg); -} - -/** - * mipi_dsi_dcs_write() - send DCS write command - * @dsi: DSI peripheral device - * @cmd: DCS command - * @data: buffer containing the command payload - * @len: command payload length - * - * This function will automatically choose the right data type depending on - * the command payload length. - * - * Return: The number of bytes successfully transmitted or a negative error - * code on failure. - */ -int mipi_dsi_dcs_write(const struct mipi_dsi_device *dsi, u8 cmd, - const void *data, size_t len) -{ - int err; - size_t size; - u8 stack_tx[64]; - u8 *tx; - - size = 1 + len; - - if (len > sizeof(stack_tx) - 1) { - return -ENOMEM; - } else { - tx = stack_tx; - } - - /* concatenate the DCS command byte and the payload */ - tx[0] = cmd; - - if (data) { - memcpy(&tx[1], data, len); - } - - err = mipi_dsi_dcs_write_buffer(dsi, tx, size); - - return err; -} - -/** - * mipi_dsi_dcs_read() - send DCS read request command - * @dsi: DSI peripheral device - * @cmd: DCS command - * @data: buffer in which to receive data - * @len: size of receive buffer - * - * Return: The number of bytes read or a negative error code on failure. - */ -int mipi_dsi_dcs_read(const struct mipi_dsi_device *dsi, u8 cmd, void *data, - size_t len) -{ - u8 wData[2] = {0}; - struct mipi_dsi_msg msg = { - .channel = dsi->channel, - .type = MIPI_DSI_DCS_READ, - .flags = MIPI_DSI_MSG_REQ_ACK, - .tx_buf = wData, - .tx_len = 1, - .rx_buf = data, - .rx_len = len - }; - - wData[0] = cmd; - - return mipi_dsi_device_transfer(dsi, &msg); -} - -/** - * mipi_dsi_dcs_nop() - send DCS nop packet - * @dsi: DSI peripheral device - * - * Return: 0 on success or a negative error code on failure. - */ -int mipi_dsi_dcs_nop(const struct mipi_dsi_device *dsi) -{ - int err; - - err = mipi_dsi_dcs_write(dsi, MIPI_DCS_NOP, NULL, 0); - - if (err < 0) { - return err; - } - - return 0; -} - -/** - * mipi_dsi_dcs_soft_reset() - perform a software reset of the display module - * @dsi: DSI peripheral device - * - * Return: 0 on success or a negative error code on failure. - */ -int mipi_dsi_dcs_soft_reset(const struct mipi_dsi_device *dsi) -{ - int err; - - err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SOFT_RESET, NULL, 0); - - if (err < 0) { - return err; - } - - return 0; -} - -/** - * mipi_dsi_dcs_get_power_mode() - query the display module's current power - * mode - * @dsi: DSI peripheral device - * @mode: return location for the current power mode - * - * Return: 0 on success or a negative error code on failure. - */ -int mipi_dsi_dcs_get_power_mode(const struct mipi_dsi_device *dsi, u8 *mode) -{ - int err; - - err = mipi_dsi_dcs_read(dsi, MIPI_DCS_GET_POWER_MODE, mode, - sizeof(*mode)); - - if (err <= 0) { - if (err == 0) { - err = -ENODATA; - } - - return err; - } - - return 0; -} - -/** - * mipi_dsi_dcs_get_pixel_format() - gets the pixel format for the RGB image - * data used by the interface - * @dsi: DSI peripheral device - * @format: return location for the pixel format - * - * Return: 0 on success or a negative error code on failure. - */ -int mipi_dsi_dcs_get_pixel_format(const struct mipi_dsi_device *dsi, u8 *format) -{ - int err; - - err = mipi_dsi_dcs_read(dsi, MIPI_DCS_GET_PIXEL_FORMAT, format, - sizeof(*format)); - - if (err <= 0) { - if (err == 0) { - err = -ENODATA; - } - - return err; - } - - return 0; -} - -/** - * mipi_dsi_dcs_enter_sleep_mode() - disable all unnecessary blocks inside the - * display module except interface communication - * @dsi: DSI peripheral device - * - * Return: 0 on success or a negative error code on failure. - */ -int mipi_dsi_dcs_enter_sleep_mode(const struct mipi_dsi_device *dsi) -{ - int err; - - err = mipi_dsi_dcs_write(dsi, MIPI_DCS_ENTER_SLEEP_MODE, NULL, 0); - - if (err < 0) { - return err; - } - - return 0; -} - -/** - * mipi_dsi_dcs_exit_sleep_mode() - enable all blocks inside the display - * module - * @dsi: DSI peripheral device - * - * Return: 0 on success or a negative error code on failure. - */ -int mipi_dsi_dcs_exit_sleep_mode(const struct mipi_dsi_device *dsi) -{ - int err; - - err = mipi_dsi_dcs_write(dsi, MIPI_DCS_EXIT_SLEEP_MODE, NULL, 0); - - if (err < 0) { - return err; - } - - return 0; -} - -/** - * mipi_dsi_dcs_set_display_off() - stop displaying the image data on the - * display device - * @dsi: DSI peripheral device - * - * Return: 0 on success or a negative error code on failure. - */ -int mipi_dsi_dcs_set_display_off(const struct mipi_dsi_device *dsi) -{ - int err; - - err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_DISPLAY_OFF, NULL, 0); - - if (err < 0) { - return err; - } - - return 0; -} - -/** - * mipi_dsi_dcs_set_display_on() - start displaying the image data on the - * display device - * @dsi: DSI peripheral device - * - * Return: 0 on success or a negative error code on failure - */ -int mipi_dsi_dcs_set_display_on(const struct mipi_dsi_device *dsi) -{ - int err; - - err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_DISPLAY_ON, NULL, 0); - - if (err < 0) { - return err; - } - - return 0; -} - -/** - * mipi_dsi_dcs_set_column_address() - define the column extent of the frame - * memory accessed by the host processor - * @dsi: DSI peripheral device - * @start: first column of frame memory - * @end: last column of frame memory - * - * Return: 0 on success or a negative error code on failure. - */ -int mipi_dsi_dcs_set_column_address(const struct mipi_dsi_device *dsi, u16 start, - u16 end) -{ - u8 payload[4] = { start >> 8, start & 0xff, end >> 8, end & 0xff }; - int err; - - err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_COLUMN_ADDRESS, payload, - sizeof(payload)); - - if (err < 0) { - return err; - } - - return 0; -} - -/** - * mipi_dsi_dcs_set_page_address() - define the page extent of the frame - * memory accessed by the host processor - * @dsi: DSI peripheral device - * @start: first page of frame memory - * @end: last page of frame memory - * - * Return: 0 on success or a negative error code on failure. - */ -int mipi_dsi_dcs_set_page_address(const struct mipi_dsi_device *dsi, u16 start, - u16 end) -{ - u8 payload[4] = { start >> 8, start & 0xff, end >> 8, end & 0xff }; - int err; - - err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_PAGE_ADDRESS, payload, - sizeof(payload)); - - if (err < 0) { - return err; - } - - return 0; -} - -/** - * mipi_dsi_dcs_set_tear_off() - turn off the display module's Tearing Effect - * output signal on the TE signal line - * @dsi: DSI peripheral device - * - * Return: 0 on success or a negative error code on failure - */ -int mipi_dsi_dcs_set_tear_off(const struct mipi_dsi_device *dsi) -{ - int err; - - err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_TEAR_OFF, NULL, 0); - - if (err < 0) { - return err; - } - - return 0; -} - -/** - * mipi_dsi_dcs_set_tear_on() - turn on the display module's Tearing Effect - * output signal on the TE signal line. - * @dsi: DSI peripheral device - * @mode: the Tearing Effect Output Line mode - * - * Return: 0 on success or a negative error code on failure - */ -int mipi_dsi_dcs_set_tear_on(const struct mipi_dsi_device *dsi, - enum mipi_dsi_dcs_tear_mode mode) -{ - u8 value = mode; - int err; - - err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_TEAR_ON, &value, - sizeof(value)); - - if (err < 0) { - return err; - } - - return 0; -} - -/** - * mipi_dsi_dcs_set_pixel_format() - sets the pixel format for the RGB image - * data used by the interface - * @dsi: DSI peripheral device - * @format: pixel format - * - * Return: 0 on success or a negative error code on failure. - */ -int mipi_dsi_dcs_set_pixel_format(const struct mipi_dsi_device *dsi, u8 format) -{ - int err; - - err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_PIXEL_FORMAT, &format, - sizeof(format)); - - if (err < 0) { - return err; - } - - return 0; -} - -/** - * mipi_dsi_dcs_set_tear_scanline() - set the scanline to use as trigger for - * the Tearing Effect output signal of the display module - * @dsi: DSI peripheral device - * @scanline: scanline to use as trigger - * - * Return: 0 on success or a negative error code on failure - */ -int mipi_dsi_dcs_set_tear_scanline(const struct mipi_dsi_device *dsi, u16 scanline) -{ - u8 payload[2] = { scanline >> 8, scanline & 0xff }; - int err; - - err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_TEAR_SCANLINE, payload, - sizeof(payload)); - - if (err < 0) { - return err; - } - - return 0; -} - -/** - * mipi_dsi_dcs_set_display_brightness() - sets the brightness value of the - * display - * @dsi: DSI peripheral device - * @brightness: brightness value - * - * Return: 0 on success or a negative error code on failure. - */ -int mipi_dsi_dcs_set_display_brightness(const struct mipi_dsi_device *dsi, - u16 brightness) -{ - u8 payload[2] = { brightness & 0xff, brightness >> 8 }; - int err; - - err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_DISPLAY_BRIGHTNESS, - payload, sizeof(payload)); - - if (err < 0) { - return err; - } - - return 0; -} - -/** - * mipi_dsi_dcs_get_display_brightness() - gets the current brightness value - * of the display - * @dsi: DSI peripheral device - * @brightness: brightness value - * - * Return: 0 on success or a negative error code on failure. - */ -int mipi_dsi_dcs_get_display_brightness(const struct mipi_dsi_device *dsi, - u16 *brightness) -{ - int err; - - err = mipi_dsi_dcs_read(dsi, MIPI_DCS_GET_DISPLAY_BRIGHTNESS, - brightness, sizeof(*brightness)); - - if (err <= 0) { - if (err == 0) { - err = -ENODATA; - } - - return err; - } - - return 0; -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_emac.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_emac.c deleted file mode 100644 index 1ddb0aec41..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_emac.c +++ /dev/null @@ -1,584 +0,0 @@ -/** - * @file hal_emac.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ - -#include "bl808_emac.h" -#include "bl808_glb.h" -#include "hal_emac.h" - -#define EMAC_USE_INSIDE_CLOCK (0) -#define TAG "EMAC_BD: " -#define EMAC_USED_ID EMAC0_ID - -//#define EMAC_DBG -#ifdef EMAC_DBG -#define MSG printf -#else -#define MSG(...) ((void)0) -#endif -#define EMAC_DO_FLUSH_DATA 1 - -static EMAC_Handle_Type ethHandle; -static EMAC_Handle_Type *thiz = NULL; - -/** - * @brief - * - */ -static void emac_gpio_init(void) -{ - uint8_t emacPins[] = { GLB_GPIO_PIN_24, GLB_GPIO_PIN_25, GLB_GPIO_PIN_26, - GLB_GPIO_PIN_27, GLB_GPIO_PIN_28, GLB_GPIO_PIN_29, - GLB_GPIO_PIN_30, GLB_GPIO_PIN_31, GLB_GPIO_PIN_32, - GLB_GPIO_PIN_33 }; - - GLB_GPIO_Func_Init(GPIO_FUN_ETHER_MAC, (GLB_GPIO_Type *)emacPins, sizeof(emacPins)); -} - -/** - * @brief - * - * @param bdt - * @return int - */ -static uint32_t emac_bd_get_cur_active(EMAC_BD_TYPE_e bdt) -{ - uint32_t bd = 0; - - bd = BL_RD_REG(EMAC_BASE, EMAC_TX_BD_NUM); - - if (bdt == EMAC_BD_TYPE_TX) { - bd &= EMAC_TXBDPTR_MSK; - bd >>= EMAC_TXBDPTR_POS; - } - - if (bdt == EMAC_BD_TYPE_RX) { - bd &= EMAC_RXBDPTR_MSK; - bd >>= EMAC_RXBDPTR_POS; - } - - return bd; -} - -/** - * @brief - * - * @param index - * @return int - */ -static int emac_bd_rx_enqueue(uint32_t index) -{ - BL_Err_Type err = SUCCESS; - - thiz->rxIndexEMAC = index; - - return err; -} - -/** - * @brief - * - * @param index - * @return int - */ -static void emac_bd_rx_on_err(uint32_t index) -{ - /* handle error */ - if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(RX_OR)) { - MSG("EMAC RX OR Error at %s:%d\r\n", __func__, __LINE__); - } - - if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(RX_RE)) { - MSG("MAC RX RE Error at %s:%d\r\n", __func__, __LINE__); - } - - if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(RX_DN)) { - MSG("MAC RX DN Error at %s:%d\r\n", __func__, __LINE__); - } - - if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(RX_TL)) { - MSG("MAC RX TL Error at %s:%d\r\n", __func__, __LINE__); - } - - if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(RX_CRC)) { - MSG("MAC RX CRC Error at %s:%d\r\n", __func__, __LINE__); - } - - if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(RX_LC)) { - MSG("MAC RX LC Error at %s:%d\r\n", __func__, __LINE__); - } - - thiz->bd[index].C_S_L &= ~0xff; - /* RX BD is ready for RX */ - thiz->bd[index].C_S_L |= EMAC_BD_FIELD_MSK(RX_E); -} - -/** - * @brief this func will be called in ISR - * - * @param index - * @return int - */ -static int emac_bd_tx_dequeue(uint32_t index) -{ - BL_Err_Type err = SUCCESS; - EMAC_BD_Desc_Type *DMADesc; - - thiz->txIndexEMAC = index; - DMADesc = &thiz->bd[thiz->txIndexEMAC]; - /* release this tx BD to SW (HW will do this) */ - DMADesc->C_S_L &= EMAC_BD_FIELD_UMSK(TX_RD); - - return err; -} - -/** - * @brief - * - * @param index - * @return int - */ -static void emac_bd_tx_on_err(uint32_t index) -{ - /* handle error */ - if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(TX_UR)) { - MSG("%s:%d\r\n", __func__, __LINE__); - } - - if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(TX_RTRY)) { - MSG("%s:%d\r\n", __func__, __LINE__); - } - - if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(TX_RL)) { - MSG("%s:%d\r\n", __func__, __LINE__); - } - - if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(TX_LC)) { - MSG("%s:%d\r\n", __func__, __LINE__); - } - - if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(TX_DF)) { - MSG("%s:%d\r\n", __func__, __LINE__); - } - - if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(TX_CS)) { - MSG("%s:%d\r\n", __func__, __LINE__); - } - - thiz->bd[index].C_S_L &= ~0xff; -} - -/** - * @brief - * - */ -__WEAK void emac_tx_done_callback_app(void) -{ -} - -/** - * @brief - * - */ -static void emac_tx_done_callback(void) -{ - uint32_t index = 0; - index = emac_bd_get_cur_active(EMAC_BD_TYPE_TX); - - emac_bd_tx_dequeue(index); - - emac_tx_done_callback_app(); -} - -/** - * @brief - * - */ -__WEAK void emac_tx_error_callback_app(void) -{ -} - -/** - * @brief - * - */ -static void emac_tx_error_callback(void) -{ - uint32_t index = 0; - - index = emac_bd_get_cur_active(EMAC_BD_TYPE_TX); - - emac_bd_tx_on_err(index); -} - -/** - * @brief - * - */ -__WEAK void emac_rx_done_callback_app(void) -{ -} - -/** - * @brief - * - */ -static void emac_rx_done_callback(void) -{ - uint32_t index = 0; - - index = emac_bd_get_cur_active(EMAC_BD_TYPE_RX); - - emac_bd_rx_enqueue(index); - - emac_rx_done_callback_app(); -} - -/** - * @brief - * - */ -__WEAK void emac_rx_error_callback_app(void) -{ -} - -/** - * @brief - * - */ -static void emac_rx_error_callback(void) -{ - uint32_t index; - - index = emac_bd_get_cur_active(EMAC_BD_TYPE_RX); - - emac_bd_rx_on_err(index); - - emac_rx_error_callback_app(); -} - -/** - * @brief - * - */ -__WEAK void emac_rx_busy_callback_app(void) -{ -} - -/** - * @brief - * - */ -static void emac_rx_busy_callback(void) -{ - MSG("EMAC Rx busy at %s:%d\r\n", __func__, __LINE__); - emac_rx_busy_callback_app(); -} - -/** - * @brief - * - * @param emac_cfg - * @return int - */ -int emac_init(emac_device_t *emac_cfg) -{ - EMAC_CFG_Type emacCfg = { - .recvSmallFrame = ENABLE, /*!< Receive small frmae or not */ - .recvHugeFrame = DISABLE, /*!< Receive huge frmae(>64K bytes) or not */ - .padEnable = ENABLE, /*!< Enable padding for frame which is less than MINFL or not */ - .crcEnable = ENABLE, /*!< Enable hardware CRC or not */ - .noPreamble = DISABLE, /*!< Enable preamble or not */ - .recvBroadCast = ENABLE, /*!< Receive broadcast frame or not */ - .interFrameGapCheck = ENABLE, /*!< Check inter frame gap or not */ - .miiNoPreamble = ENABLE, /*!< Enable MII interface preamble or not */ - .miiClkDiv = 49, /*!< MII interface clock divider from bus clock */ - .maxTxRetry = 16, /*!< Maximum tx retry count */ - .interFrameGapValue = 24, /*!< Inter frame gap vaule in clock cycles(default 24)*/ - .minFrameLen = 64, /*!< Minimum frame length */ - .maxFrameLen = ETH_MAX_PACKET_SIZE, /*!< Maximum frame length */ - .collisionValid = 16, /*!< Collision valid value */ - .macAddr[0] = 0x18, /*!< MAC Address */ - .macAddr[1] = 0xB0, - .macAddr[2] = 0x09, - .macAddr[3] = 0x00, - .macAddr[4] = 0x12, - .macAddr[5] = 0x34, - }; - BL_Err_Type err = SUCCESS; - - /* init emac giio */ - emac_gpio_init(); - - memcpy(emacCfg.macAddr, emac_cfg->mac_addr, 6); - GLB_PER_Clock_UnGate(1<<12); -#if EMAC_USE_INSIDE_CLOCK - /* 50MHZ clock is from uhs pll */ - /* Pls make sure uhs pll UHSPLL_EVEN_DIV_EN is 1 */ - GLB_Set_ETH_REF_O_CLK_Sel(GLB_ETH_REF_CLK_OUT_INSIDE_50M); - GLB_Invert_ETH_REF_O_CLK(0); -#else - GLB_Set_ETH_REF_O_CLK_Sel(GLB_ETH_REF_CLK_OUT_OUTSIDE_50M); -#endif - //GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_EMAC); - GLB_PER_Clock_UnGate(1<<12); - //GLB_Invert_ETH_RX_CLK(0); - //GLB_Invert_ETH_TX_CLK(0); - EMAC_Init(EMAC_USED_ID,&emacCfg); - - EMAC_Int_Callback_Install(EMAC_USED_ID, EMAC_INT_TX_DONE_IDX, emac_tx_done_callback); - EMAC_Int_Callback_Install(EMAC_USED_ID, EMAC_INT_TX_ERROR_IDX, emac_tx_error_callback); - - EMAC_Int_Callback_Install(EMAC_USED_ID, EMAC_INT_RX_DONE_IDX, emac_rx_done_callback); - EMAC_Int_Callback_Install(EMAC_USED_ID, EMAC_INT_RX_ERROR_IDX, emac_rx_error_callback); - - EMAC_Int_Callback_Install(EMAC_USED_ID, EMAC_INT_RX_BUSY_IDX, emac_rx_busy_callback); - - CPU_Interrupt_Enable(EMAC_IRQn); - - EMAC_ClrIntStatus(EMAC_USED_ID,EMAC_INT_ALL); - EMAC_IntMask(EMAC_USED_ID,EMAC_INT_ALL, UNMASK); - - //EMAC_Enable(); - - return err; -} - -/** - * @brief - * - * @param eth_tx_buff - * @param tx_buf_count - * @param eth_rx_buff - * @param rx_buf_count - * @return int - */ -int emac_bd_init(uint8_t *eth_tx_buff, uint8_t tx_buf_count, uint8_t *eth_rx_buff, uint8_t rx_buf_count) -{ - BL_Err_Type err = SUCCESS; - thiz = ðHandle; - - /* init the BDs in emac with buffer address */ - err = EMAC_DMADescListInit(EMAC_USED_ID,thiz, (uint8_t *)eth_tx_buff, tx_buf_count, - (uint8_t *)eth_rx_buff, rx_buf_count); - return err; -} - -/** - * @brief - * - * @param none - * @return int - */ -int emac_bd_fragment_support(void){ - return 1; -} - -/** - * @brief - * - * @param flags - * @param len - * @param data_in - * @return int - */ -//uint32_t tmpbuf[400]; -int emac_bd_tx_enqueue(uint32_t flags, uint32_t len, const uint8_t *data_in) -{ - BL_Err_Type err = SUCCESS; - EMAC_BD_Desc_Type *DMADesc; - uint32_t tx_flags=EMAC_TX_COMMON_FLAGS; - DMADesc = &thiz->bd[thiz->txIndexCPU]; - - if (flags&EMAC_FRAGMENT_PACKET) { - /* Fragment packet, clear EOF */ - tx_flags &= EMAC_BD_FIELD_UMSK(TX_EOF); - } - - if (DMADesc->C_S_L & EMAC_BD_FIELD_MSK(TX_RD)) { - /* no free BD, lost sync with DMA TX? */ - err = NORESC; - //MSG(TAG"%s:%d\n", __func__, __LINE__); - } else { - __DSB(); - // MSG("tx q flags:%d,len:%d,data:0x%x\r\n", flags, len, data_in); - if (flags&EMAC_NOCOPY_PACKET) { - DMADesc->Buffer = (uint32_t)(uintptr_t)data_in; - }else{ - ARCH_MemCpy_Fast((void *)(uintptr_t)(DMADesc->Buffer), data_in, len); - } - - /* following two lines is for cache test since tmpbuf is in cache range */ - //ARCH_MemCpy_Fast(tmpbuf, data_in, len); - //DMADesc->Buffer = (uint32_t)tmpbuf; -#ifdef EMAC_DO_FLUSH_DATA - if(L1C_Is_DCache_Range((uintptr_t)DMADesc->Buffer)){ - L1C_DCache_Clean_By_Addr((uintptr_t)DMADesc->Buffer,len); - } -#endif - DMADesc->C_S_L = tx_flags | (len << BD_TX_LEN_POS); - - /* move to next TX BD */ - if ((++thiz->txIndexCPU) > thiz->txBuffLimit) { - /* the last BD */ - DMADesc->C_S_L |= EMAC_BD_FIELD_MSK(TX_WR); - /* wrap back */ - thiz->txIndexCPU = 0; - } - } - - return err; -} - -/** - * @brief - * - * @param flags - * @param len - * @param data_out - * @return int - */ -int emac_bd_rx_dequeue(uint32_t flags, uint32_t *len, uint8_t *data_out) -{ - BL_Err_Type err = SUCCESS; - EMAC_BD_Desc_Type *DMADesc; - - DMADesc = &thiz->bd[thiz->rxIndexCPU]; - - if (DMADesc->C_S_L & EMAC_BD_FIELD_MSK(RX_E)) { - /* current RX BD is empty */ - err = NORESC; - *len = 0; - } else { - *len = (thiz->bd[thiz->rxIndexCPU].C_S_L & EMAC_BD_FIELD_MSK(RX_LEN)) >> BD_RX_LEN_POS; -#ifdef EMAC_DO_FLUSH_DATA - if(L1C_Is_DCache_Range((uintptr_t)DMADesc->Buffer)){ - L1C_DCache_Invalid_By_Addr((uintptr_t)DMADesc->Buffer, *len); - } -#endif - if (data_out) { - ARCH_MemCpy_Fast(data_out, (const void *)(uintptr_t)DMADesc->Buffer, *len); - } - - /* RX BD can be used for another receive */ - DMADesc->C_S_L |= EMAC_BD_FIELD_MSK(RX_E); - - /* move to next RX BD */ - if ((++thiz->rxIndexCPU) > thiz->rxBuffLimit) { - /* the last BD */ - DMADesc->C_S_L |= EMAC_BD_FIELD_MSK(RX_WR); - /* wrap back */ - thiz->rxIndexCPU = thiz->txBuffLimit + 1; - } - } - - return err; -} - -/** - * @brief - * - * @param phyAddress - * @return int - */ -int emac_phy_set_address(uint16_t phyAddress) -{ - EMAC_Phy_SetAddress(EMAC_USED_ID,phyAddress); - - return 0; -} - -/** - * @brief - * - * @param fullDuplex - * @return int - */ -int emac_phy_config_full_duplex(uint8_t fullDuplex) -{ - EMAC_Phy_Set_Full_Duplex(EMAC_USED_ID,fullDuplex); - - return 0; -} - -/** - * @brief - * - * @param phyReg - * @param regValue - * @return int - */ -int emac_phy_reg_read(uint16_t phyReg, uint16_t *regValue) -{ - if (EMAC_Phy_Read(EMAC_USED_ID,phyReg, regValue) != SUCCESS) { - return -1; - } - - return 0; -} - -/** - * @brief - * - * @param phyReg - * @param regValue - * @return int - */ -int emac_phy_reg_write(uint16_t phyReg, uint16_t regValue) -{ - if (EMAC_Phy_Write(EMAC_USED_ID,phyReg, regValue) != SUCCESS) { - return -1; - } - - return 0; -} - -int emac_stop(void) -{ - return EMAC_Disable(EMAC_USED_ID); -} - -int emac_start(void) -{ - EMAC_Enable(EMAC_USED_ID); - return 0; -} - -int emac_start_tx(void) -{ - return EMAC_Enable_TX(EMAC_USED_ID); -} - -int emac_stop_tx(void) -{ - return EMAC_Disable_TX(EMAC_USED_ID); -} - -int emac_start_rx(void) -{ - return EMAC_Enable_RX(EMAC_USED_ID); -} - -int emac_stop_rx(void) -{ - return EMAC_Disable_RX(EMAC_USED_ID); -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_flash.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_flash.c deleted file mode 100644 index 64bdff924c..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_flash.c +++ /dev/null @@ -1,352 +0,0 @@ -/** - * @file hal_flash.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#include "bl808_glb.h" -#include "bl808_xip_sflash.h" -#include "bl808_sf_cfg.h" -#include "bl808_romapi_patch.h" -#include "hal_flash.h" - -static uint32_t g_jedec_id = 0; -static SPI_Flash_Cfg_Type g_flash_cfg; - -/** - * @brief flash_get_jedecid - * - * @return BL_Err_Type - */ -uint32_t flash_get_jedecid(void) -{ - uint32_t jid = 0; - - jid = ((g_jedec_id&0xff)<<16) + (g_jedec_id&0xff00) + ((g_jedec_id&0xff0000)>>16); - return jid; -} - -/** - * @brief flash_get_cfg - * - * @return BL_Err_Type - */ -BL_Err_Type flash_get_cfg(uint8_t **cfg_addr, uint32_t *len) -{ - *cfg_addr = (uint8_t *)&g_flash_cfg; - *len = sizeof(SPI_Flash_Cfg_Type); - - return SUCCESS; -} - -/** - * @brief flash_get_clock_delay - * - * @return BL_Err_Type - */ -static BL_Err_Type flash_get_clock_delay(SPI_Flash_Cfg_Type *cfg) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); - /* bit0-3 for clk delay */ - if (BL_IS_REG_BIT_SET(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN)) { - cfg->clkDelay = BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_N)+1; - } else { - cfg->clkDelay = 0; - } - cfg->clkInvert = 0; - /* bit0 for clk invert */ - cfg->clkInvert |= ((BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CLK_OUT_INV_SEL)&1)<<0); - /* bit1 for rx clk invert */ - cfg->clkInvert |= ((BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CLK_SF_RX_INV_SEL)&1)<<1); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_1); - /* bit4-6 for do delay */ - cfg->clkDelay |= ((BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_0_DO_DLY_SEL)&7)<<4); - /* bit2-4 for di delay */ - cfg->clkInvert |= ((BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_0_DI_DLY_SEL)&7)<<2); - /* bit5-7 for oe delay */ - cfg->clkInvert |= ((BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_0_OE_DLY_SEL)&7)<<5); - - return SUCCESS; -} - -/** - * @brief flash_set_qspi_enable - * - * @return BL_Err_Type - */ -static BL_Err_Type ATTR_TCM_SECTION flash_set_qspi_enable(SPI_Flash_Cfg_Type *p_flash_cfg) -{ - if ((p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QO_MODE || (p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QIO_MODE) { - SFlash_Qspi_Enable(p_flash_cfg); - } - - return SUCCESS; -} - -/** - * @brief flash_set_l1c_wrap - * - * @return BL_Err_Type - */ -static BL_Err_Type ATTR_TCM_SECTION flash_set_l1c_wrap(SPI_Flash_Cfg_Type *p_flash_cfg) -{ - if (((p_flash_cfg->ioMode >> 4) & 0x01) == 1) { - L1C_Set_Wrap(DISABLE); - } else { - L1C_Set_Wrap(ENABLE); - if ((p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QO_MODE || (p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QIO_MODE) { - SFlash_SetBurstWrap(p_flash_cfg); - } - } - - return SUCCESS; -} - -/** - * @brief flash_config_init - * - * @return BL_Err_Type - */ -static BL_Err_Type ATTR_TCM_SECTION flash_config_init(SPI_Flash_Cfg_Type *p_flash_cfg, uint8_t *jedec_id) -{ - BL_Err_Type ret = ERROR; - uint8_t isAesEnable = 0; - uint32_t jid = 0; - uint32_t offset = 0; - - cpu_global_irq_disable(); - XIP_SFlash_Opt_Enter(&isAesEnable); - XIP_SFlash_State_Save(p_flash_cfg, &offset, 0, 0); - SFlash_GetJedecId(p_flash_cfg, (uint8_t *)&jid); - arch_memcpy(jedec_id, (uint8_t *)&jid, 3); - jid &= 0xFFFFFF; - g_jedec_id = jid; - ret = SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(jid, p_flash_cfg, 0, 0); - if (ret == SUCCESS) { - p_flash_cfg->mid = (jid & 0xff); - } - - /* Set flash controler from p_flash_cfg */ - flash_set_qspi_enable(p_flash_cfg); - flash_set_l1c_wrap(p_flash_cfg); - XIP_SFlash_State_Restore(p_flash_cfg, offset, 0, 0); - XIP_SFlash_Opt_Exit(isAesEnable); - cpu_global_irq_enable(); - - return ret; -} - -/** - * @brief multi flash adapter - * - * @return BL_Err_Type - */ -BL_Err_Type ATTR_TCM_SECTION flash_init(void) -{ - BL_Err_Type ret = ERROR; - uint32_t jedec_id = 0; - - jedec_id = GLB_Get_Flash_Id_Value(); - if (jedec_id != 0) { - ret = SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(jedec_id, &g_flash_cfg, 0, 0); - if (ret == SUCCESS) { - g_jedec_id = jedec_id; - flash_get_clock_delay(&g_flash_cfg); - return SUCCESS; - } - } - - cpu_global_irq_disable(); - L1C_ICache_Invalid_All(); - SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(0, &g_flash_cfg, 0, 0); - L1C_ICache_Invalid_All(); - cpu_global_irq_enable(); - if (g_flash_cfg.mid != 0xff) { - flash_get_clock_delay(&g_flash_cfg); - return SUCCESS; - } - - ret = flash_config_init(&g_flash_cfg, (uint8_t *)&jedec_id); -#ifdef HAL_FLASH_MSG - MSG("flash ID = %08x\r\n", jedec_id); - bflb_platform_dump((uint8_t *)&g_flash_cfg, sizeof(g_flash_cfg)); - if (ret != SUCCESS) { - MSG("flash config init fail!\r\n"); - } -#endif - flash_get_clock_delay(&g_flash_cfg); - GLB_Set_Flash_Id_Value(g_jedec_id); - - return ret; -} - -/** - * @brief read jedec id - * - * @param data - * @return BL_Err_Type - */ -BL_Err_Type ATTR_TCM_SECTION flash_read_jedec_id(uint8_t *data) -{ - uint32_t jid = 0; - - cpu_global_irq_disable(); - XIP_SFlash_GetJedecId_Need_Lock(&g_flash_cfg, (uint8_t *)&jid, 0, 0); - cpu_global_irq_enable(); - jid &= 0xFFFFFF; - arch_memcpy(data, (void *)&jid, 4); - - return SUCCESS; -} - -/** - * @brief read flash data via xip - * - * @param flash xip addr or flash absolute addr - * @param data - * @param len - * @return BL_Err_Type - */ -BL_Err_Type ATTR_TCM_SECTION flash_read_via_xip(uint32_t addr, uint8_t *data, uint32_t len) -{ - addr = addr & (BL808_FLASH_XIP_END-BL808_FLASH_XIP_BASE-1); - - cpu_global_irq_disable(); - L1C_ICache_Invalid_All(); - XIP_SFlash_Read_Via_Cache_Need_Lock(addr, data, len, 0, 0); - L1C_ICache_Invalid_All(); - cpu_global_irq_enable(); - - return SUCCESS; -} - -/** - * @brief read flash data via sbus - * - * @param flash absolute addr - * @param data - * @param len - * @return BL_Err_Type - */ -BL_Err_Type ATTR_TCM_SECTION flash_read(uint32_t addr, uint8_t *data, uint32_t len) -{ - BL_Err_Type stat; - - if (addr >= BL808_FLASH_XIP_END-BL808_FLASH_XIP_BASE) { - return ERROR; - } - - cpu_global_irq_disable(); - stat = XIP_SFlash_Read_Need_Lock(&g_flash_cfg, addr, data, len, 0, 0); - cpu_global_irq_enable(); - - return stat; -} - -/** - * @brief write flash data via sbus - * - * @param flash absolute addr - * @param data - * @param len - * @return BL_Err_Type - */ -BL_Err_Type ATTR_TCM_SECTION flash_write(uint32_t addr, uint8_t *data, uint32_t len) -{ - BL_Err_Type stat; - - if (addr >= BL808_FLASH_XIP_END-BL808_FLASH_XIP_BASE) { - return ERROR; - } - - cpu_global_irq_disable(); - stat = XIP_SFlash_Write_Need_Lock(&g_flash_cfg, addr, data, len, 0, 0); - cpu_global_irq_enable(); - - return stat; -} - -/** - * @brief erase flash via sbus - * - * @param flash absolute startaddr - * @param flash absolute endaddr - * @return BL_Err_Type - */ -BL_Err_Type ATTR_TCM_SECTION flash_erase(uint32_t startaddr, uint32_t len) -{ - BL_Err_Type stat; - - if (startaddr >= BL808_FLASH_XIP_END-BL808_FLASH_XIP_BASE) { - return ERROR; - } - - cpu_global_irq_disable(); - stat = XIP_SFlash_Erase_Need_Lock(&g_flash_cfg, startaddr, len, 0, 0); - cpu_global_irq_enable(); - - return stat; -} - -/** - * @brief set flash cache - * - * @param cont_read - * @param cache_enable - * @param cache_way_disable - * @param flash_offset - * @return BL_Err_Type - */ -BL_Err_Type ATTR_TCM_SECTION flash_set_cache(uint8_t cont_read, uint8_t cache_enable, uint8_t cache_way_disable, uint32_t flash_offset) -{ - uint8_t isAesEnable = 0; - uint32_t tmp[1]; - BL_Err_Type stat; - - SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB); - - XIP_SFlash_Opt_Enter(&isAesEnable); - /* To make it simple, exit cont read anyway */ - SFlash_Reset_Continue_Read(&g_flash_cfg); - - if (g_flash_cfg.cReadSupport == 0) { - cont_read = 0; - } - - if (cont_read == 1) { - stat = SFlash_Read(&g_flash_cfg, g_flash_cfg.ioMode & 0xf, 1, 0x00000000, (uint8_t *)tmp, sizeof(tmp)); - - if (SUCCESS != stat) { - XIP_SFlash_Opt_Exit(isAesEnable); - return ERROR; - } - } - - /* TODO: Set default value */ - - SF_Ctrl_Set_Flash_Image_Offset(flash_offset, 0, 0); - SFlash_IDbus_Read_Enable(&g_flash_cfg, g_flash_cfg.ioMode & 0xf, cont_read, SF_CTRL_FLASH_BANK0); - - XIP_SFlash_Opt_Exit(isAesEnable); - - return SUCCESS; -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_gpio.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_gpio.c deleted file mode 100644 index 3a0d01171e..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_gpio.c +++ /dev/null @@ -1,227 +0,0 @@ -/** - * @file hal_gpio.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#include "bl808_glb.h" -#include "bl808_gpio.h" -#include "hal_gpio.h" - -static void GPIO_IRQ(void); - -struct gpio_int_cfg_private { - slist_t list; - uint32_t pin; - void (*cbfun)(uint32_t pin); -}; - -static slist_t gpio_int_head = SLIST_OBJECT_INIT(gpio_int_head); - -/** - * @brief - * - * @param pin - * @param mode - */ -void gpio_set_mode(uint32_t pin, uint32_t mode) -{ - GLB_GPIO_Cfg_Type gpio_cfg; - - gpio_cfg.gpioFun = GPIO_FUN_GPIO; - gpio_cfg.gpioPin = pin; - gpio_cfg.drive = 0; - gpio_cfg.smtCtrl = 1; - gpio_cfg.outputMode = 0; - - switch (mode) { - case GPIO_OUTPUT_MODE: - gpio_cfg.gpioMode = GPIO_MODE_OUTPUT; - gpio_cfg.pullType = GPIO_PULL_NONE; - break; - - case GPIO_OUTPUT_PP_MODE: - gpio_cfg.gpioMode = GPIO_MODE_OUTPUT; - gpio_cfg.pullType = GPIO_PULL_UP; - break; - - case GPIO_OUTPUT_PD_MODE: - gpio_cfg.gpioMode = GPIO_MODE_OUTPUT; - gpio_cfg.pullType = GPIO_PULL_DOWN; - break; - - case GPIO_INPUT_MODE: - gpio_cfg.gpioMode = GPIO_MODE_INPUT; - gpio_cfg.pullType = GPIO_PULL_NONE; - break; - - case GPIO_INPUT_PP_MODE: - gpio_cfg.gpioMode = GPIO_MODE_INPUT; - gpio_cfg.pullType = GPIO_PULL_UP; - break; - - case GPIO_INPUT_PD_MODE: - gpio_cfg.gpioMode = GPIO_MODE_INPUT; - gpio_cfg.pullType = GPIO_PULL_DOWN; - break; - case GPIO_HZ_MODE: - GLB_GPIO_Set_HZ(pin); - default: - CPU_Interrupt_Disable(GPIO_INT0_IRQn); - GLB_GPIO_IntMask(pin, MASK); - - GLB_GPIO_INT_Cfg_Type intCfg; - - intCfg.gpioPin = pin; - intCfg.intMask = MASK; - - gpio_cfg.gpioMode = GPIO_MODE_INPUT; - - if (mode == GPIO_ASYNC_RISING_TRIGER_INT_MODE) { - gpio_cfg.pullType = GPIO_PULL_DOWN; - intCfg.trig = GLB_GPIO_INT_TRIG_ASYNC_RISING_EDGE; - } else if (mode == GPIO_ASYNC_FALLING_TRIGER_INT_MODE) { - gpio_cfg.pullType = GPIO_PULL_UP; - intCfg.trig = GLB_GPIO_INT_TRIG_ASYNC_FALLING_EDGE; - } else if (mode == GPIO_ASYNC_HIGH_LEVEL_INT_MODE) { - gpio_cfg.pullType = GPIO_PULL_DOWN; - intCfg.trig = GLB_GPIO_INT_TRIG_ASYNC_HIGH_LEVEL; - } else if (mode == GPIO_ASYNC_LOW_LEVEL_INT_MODE) { - gpio_cfg.pullType = GPIO_PULL_UP; - intCfg.trig = GLB_GPIO_INT_TRIG_ASYNC_LOW_LEVEL; - } else if (mode == GPIO_SYNC_RISING_TRIGER_INT_MODE) { - gpio_cfg.pullType = GPIO_PULL_DOWN; - intCfg.trig = GLB_GPIO_INT_TRIG_SYNC_RISING_EDGE; - } else if (mode == GPIO_SYNC_FALLING_TRIGER_INT_MODE) { - gpio_cfg.pullType = GPIO_PULL_UP; - intCfg.trig = GLB_GPIO_INT_TRIG_SYNC_FALLING_EDGE; - } else if (mode == GPIO_SYNC_FALLING_TRIGER_INT_MODE) { - gpio_cfg.pullType = GPIO_PULL_NONE; - intCfg.trig = GLB_GPIO_INT_TRIG_SYNC_FALLING_RISING_EDGE; - } else if (mode == GPIO_SYNC_HIGH_LEVEL_INT_MODE) { - gpio_cfg.pullType = GPIO_PULL_DOWN; - intCfg.trig = GLB_GPIO_INT_TRIG_SYNC_HIGH_LEVEL; - } else if (mode == GPIO_SYNC_LOW_LEVEL_INT_MODE) { - gpio_cfg.pullType = GPIO_PULL_UP; - intCfg.trig = GLB_GPIO_INT_TRIG_SYNC_LOW_LEVEL; - } - - GLB_GPIO_Int_Init(&intCfg); - break; - } - - GLB_GPIO_Init(&gpio_cfg); -} -/** - * @brief - * - * @param pin - * @param value - */ -void gpio_write(uint32_t pin, uint32_t value) -{ - GLB_GPIO_Write(pin, value); -} -/** - * @brief - * - * @param pin - */ -void gpio_toggle(uint32_t pin) -{ - uint32_t gpioCfgAddress; - uint32_t tmpVal; - - gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (pin << 2); - tmpVal = BL_RD_WORD(gpioCfgAddress); - - if (BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_O)) { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_O); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_O); - } - - BL_WR_WORD(gpioCfgAddress, tmpVal); -} -/** - * @brief - * - * @param pin - * @return int - */ -int gpio_read(uint32_t pin) -{ - return GLB_GPIO_Read(pin); -} -/** - * @brief - * - * @param pin - * @param cbFun - */ -void gpio_attach_irq(uint32_t pin, void (*cbfun)(uint32_t pin)) -{ - struct gpio_int_cfg_private *int_cfg = malloc(sizeof(struct gpio_int_cfg_private)); - int_cfg->cbfun = cbfun; - int_cfg->pin = pin; - slist_add_tail(&gpio_int_head, &int_cfg->list); - CPU_Interrupt_Disable(GPIO_INT0_IRQn); - Interrupt_Handler_Register(GPIO_INT0_IRQn, GPIO_IRQ); - CPU_Interrupt_Enable(GPIO_INT0_IRQn); -} -/** - * @brief - * - * @param pin - * @param enabled - */ -void gpio_irq_enable(uint32_t pin, uint8_t enabled) -{ - if (enabled) { - GLB_GPIO_IntMask(pin, UNMASK); - } else { - GLB_GPIO_IntMask(pin, MASK); - } -} - -static void GPIO_IRQ(void) -{ - slist_t *i; - uint32_t timeOut = 0; -#define GLB_GPIO_INT0_CLEAR_TIMEOUT (32) - slist_for_each(i, &gpio_int_head) - { - struct gpio_int_cfg_private *int_cfg = slist_entry(i, struct gpio_int_cfg_private, list); - - if (SET == GLB_Get_GPIO_IntStatus(int_cfg->pin)) { - int_cfg->cbfun(int_cfg->pin); - GLB_Clr_GPIO_IntStatus(int_cfg->pin); - /* timeout check */ - timeOut = GLB_GPIO_INT0_CLEAR_TIMEOUT; - - do { - timeOut--; - } while ((SET == GLB_Get_GPIO_IntStatus(int_cfg->pin)) && timeOut); - - if (!timeOut) { - //MSG("WARNING: Clear GPIO interrupt status fail.\r\n"); - } - } - } -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_i2c.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_i2c.c deleted file mode 100644 index 574acf64f9..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_i2c.c +++ /dev/null @@ -1,131 +0,0 @@ -/** - * @file hal_i2c.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#include "hal_i2c.h" -#include "hal_gpio.h" -#include "bl808_i2c.h" -#include "bl808_glb.h" - -static i2c_device_t i2cx_device[I2C_MAX_INDEX] = { -#ifdef BSP_USING_I2C0 - I2C0_CONFIG, -#endif -#ifdef BSP_USING_I2C1 - I2C1_CONFIG, -#endif -#ifdef BSP_USING_I2C2 - I2C2_CONFIG, -#endif -#ifdef BSP_USING_I2C3 - I2C3_CONFIG, -#endif -}; -/** - * @brief - * - * @param dev - * @param oflag - * @return int - */ -int i2c_open(struct device *dev, uint16_t oflag) -{ - i2c_device_t *i2c_device = (i2c_device_t *)dev; - - if (i2c_device->mode == I2C_HW_MODE) { - I2C_SetPrd(i2c_device->id, i2c_device->phase); - } - - return 0; -} - -/** - * @brief - * - * @param index - * @param name - * @param flag - * @return int - */ -int i2c_register(enum i2c_index_type index, const char *name) -{ - struct device *dev; - - if (I2C_MAX_INDEX == 0) { - return -DEVICE_EINVAL; - } - - dev = &(i2cx_device[index].parent); - - dev->open = i2c_open; - dev->close = NULL; - dev->control = NULL; - dev->write = NULL; - dev->read = NULL; - - dev->type = DEVICE_CLASS_I2C; - dev->handle = NULL; - - return device_register(dev, name); -} -/** - * @brief - * - * @param dev - * @param msgs - * @param num - * @return uint32_t - */ -int i2c_transfer(struct device *dev, i2c_msg_t msgs[], uint32_t num) -{ - i2c_msg_t *msg; - I2C_Transfer_Cfg i2cCfg = { 0 }; - - i2c_device_t *i2c_device = (i2c_device_t *)dev; - - if (i2c_device->mode == I2C_HW_MODE) { - for (uint32_t i = 0; i < num; i++) { - msg = &msgs[i]; - i2cCfg.slaveAddr = msg->slaveaddr; - i2cCfg.stopEveryByte = DISABLE; - i2cCfg.subAddr = msg->subaddr; - i2cCfg.dataSize = msg->len; - i2cCfg.data = msg->buf; - - if (msg->flags & SUB_ADDR_0BYTE) { - i2cCfg.subAddrSize = 0; - } else if (msg->flags & SUB_ADDR_1BYTE) { - i2cCfg.subAddrSize = 1; - } else if (msg->flags & SUB_ADDR_2BYTE) { - i2cCfg.subAddrSize = 2; - } - - if ((msg->flags & I2C_RW_MASK) == I2C_WR) { - return I2C_MasterSendBlocking(i2c_device->id, &i2cCfg); - } else if ((msg->flags & I2C_RW_MASK) == I2C_RD) { - return I2C_MasterReceiveBlocking(i2c_device->id, &i2cCfg); - } - } - } else { - } - - return 0; -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_i2s.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_i2s.c deleted file mode 100644 index 549fc1363d..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_i2s.c +++ /dev/null @@ -1,352 +0,0 @@ -/** - * @file hal_i2s.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#include "hal_i2s.h" -#include "hal_clock.h" -#include "hal_dma.h" -#include "bl808_i2s.h" -#include "bl808_glb.h" -#include "i2s_config.h" - -static i2s_device_t i2sx_device[I2S_MAX_INDEX] = { -#ifdef BSP_USING_I2S0 - I2S0_CONFIG, -#endif -}; - -int i2s_open(struct device *dev, uint16_t oflag) -{ - i2s_device_t *i2s_device = (i2s_device_t *)dev; - I2S_CFG_Type i2sCfg = { 0 }; - I2S_FifoCfg_Type fifoCfg = { 0 }; - - /* todo unify clock configuretion */ - // GLB_Power_On_XTAL_And_PLL_CLK(GLB_XTAL_40M, GLB_PLL_AUPLL); - if (i2s_device->sampl_freq_hz == 44100) { - GLB_Config_AUDIO_PLL(GLB_XTAL_40M, audioPllCfg_451P584M); - } - - i2sCfg.audioFreqHz = 24576000; - - i2sCfg.sampleFreqHz = i2s_device->sampl_freq_hz; - - /*!< default I2S msb first */ - i2sCfg.endianType = I2S_DATA_ENDIAN; - - /* Config the I2S type */ - switch (i2s_device->interface_mode) { - case I2S_MODE_STD: - i2sCfg.modeType = I2S_MODE_I2S_LEFT; - i2sCfg.fsMode = I2S_FS_MODE_EVEN; - i2sCfg.dataOffset = 1; - break; - - case I2S_MODE_LEFT: - i2sCfg.modeType = I2S_MODE_I2S_LEFT; - i2sCfg.fsMode = I2S_FS_MODE_EVEN; - i2sCfg.dataOffset = 0; - break; - - case I2S_MODE_RIGHT: - i2sCfg.modeType = I2S_MODE_I2S_RIGHT; - i2sCfg.fsMode = I2S_FS_MODE_EVEN; - i2sCfg.dataOffset = 0; - break; - - case I2S_MODE_DSP_A: - i2sCfg.modeType = I2S_MODE_I2S_DSP; - i2sCfg.fsMode = I2S_FS_MODE_1T; - i2sCfg.dataOffset = 1; - break; - - case I2S_MODE_DSP_B: - i2sCfg.modeType = I2S_MODE_I2S_DSP; - i2sCfg.fsMode = I2S_FS_MODE_1T; - i2sCfg.dataOffset = 0; - break; - - default: - return ERROR; - break; - } - - /* Config the frame/data Size */ - switch (i2s_device->frame_size) { - case I2S_FRAME_LEN_8: - i2sCfg.frameSize = I2S_SIZE_FRAME_8; - break; - - case I2S_FRAME_LEN_16: - i2sCfg.frameSize = I2S_SIZE_FRAME_16; - break; - - case I2S_FRAME_LEN_24: - i2sCfg.frameSize = I2S_SIZE_FRAME_24; - break; - - case I2S_FRAME_LEN_32: - i2sCfg.frameSize = I2S_SIZE_FRAME_32; - break; - - default: - return ERROR; - break; - } - - switch (i2s_device->data_size) { - case I2S_DATA_LEN_8: - i2sCfg.dataSize = I2S_SIZE_DATA_8; - break; - - case I2S_DATA_LEN_16: - i2sCfg.dataSize = I2S_SIZE_DATA_16; - break; - - case I2S_DATA_LEN_24: - i2sCfg.dataSize = I2S_SIZE_DATA_24; - break; - - case I2S_DATA_LEN_32: - i2sCfg.dataSize = I2S_SIZE_DATA_32; - break; - - default: - return ERROR; - break; - } - - fifoCfg.lRMerge = DISABLE; - fifoCfg.frameDataExchange = DISABLE; - - /* Config the Channel number */ - switch (i2s_device->channel_num) { - case I2S_FS_CHANNELS_NUM_MONO: - i2sCfg.monoMode = ENABLE; - i2sCfg.fsChannel = I2S_FS_CHANNELS_2; - i2sCfg.monoModeChannel = I2S_MONO_CHANNEL; - break; - - case I2S_FS_CHANNELS_NUM_2: - i2sCfg.monoMode = DISABLE; - i2sCfg.fsChannel = I2S_FS_CHANNELS_2; - - if (i2s_device->data_size == I2S_DATA_LEN_8 || i2s_device->data_size == I2S_DATA_LEN_16) { - fifoCfg.lRMerge = ENABLE; - fifoCfg.frameDataExchange = I2S_LR_EXCHANGE; - } - - break; - - case I2S_FS_CHANNELS_NUM_3: - if ((i2s_device->interface_mode != I2S_MODE_DSP_A) && (i2s_device->interface_mode != I2S_MODE_DSP_B)) { - return ERROR; - } - - i2sCfg.monoMode = DISABLE; - i2sCfg.fsChannel = I2S_FS_CHANNELS_3; - break; - - case I2S_FS_CHANNELS_NUM_4: - if ((i2s_device->interface_mode != I2S_MODE_DSP_A) && (i2s_device->interface_mode != I2S_MODE_DSP_B)) { - return ERROR; - } - - i2sCfg.monoMode = DISABLE; - i2sCfg.fsChannel = I2S_FS_CHANNELS_4; - - default: - return ERROR; - break; - } - - /* Config the bclk/fs invert */ - i2sCfg.bclkInvert = I2S_BCLK_INVERT; - i2sCfg.fsInvert = I2S_FS_INVERT; - - if (oflag & DEVICE_OFLAG_INT_TX) { - } - - if (oflag & DEVICE_OFLAG_INT_RX) { - } - - fifoCfg.txfifoDmaEnable = (oflag & DEVICE_OFLAG_DMA_TX) ? ENABLE : DISABLE; - fifoCfg.rxfifoDmaEnable = (oflag & DEVICE_OFLAG_DMA_RX) ? ENABLE : DISABLE; - fifoCfg.txFifoLevel = i2s_device->fifo_threshold; - fifoCfg.rxFifoLevel = i2s_device->fifo_threshold; - - /* I2S Init */ - I2S_Disable(i2s_device->id); - I2S_Init(i2s_device->id, &i2sCfg); - I2S_FifoConfig(i2s_device->id, &fifoCfg); - - if (i2s_device->iis_mode == I2S_MODE_MASTER) - I2S_Enable(i2s_device->id, I2S_ROLE_MASTER); - else if (i2s_device->iis_mode == I2S_MODE_SLAVE) - I2S_Enable(i2s_device->id, I2S_ROLE_SLAVE); - return 0; -} - -int i2s_close(struct device *dev) -{ - i2s_device_t *i2s_device = (i2s_device_t *)dev; - I2S_Disable(i2s_device->id); - return 0; -} - -int i2s_control(struct device *dev, int cmd, void *args) -{ - i2s_device_t *i2s_device = (i2s_device_t *)dev; - - switch (cmd) { - case DEVICE_CTRL_SET_INT: - break; - - case DEVICE_CTRL_CLR_INT: - - break; - - case DEVICE_CTRL_GET_INT: - - break; - - case DEVICE_CTRL_RESUME: - - break; - - case DEVICE_CTRL_SUSPEND: - - break; - - case DEVICE_CTRL_CONFIG: - - break; - - case DEVICE_CTRL_ATTACH_TX_DMA: - i2s_device->tx_dma = (struct device *)args; - break; - - case DEVICE_CTRL_ATTACH_RX_DMA: - i2s_device->rx_dma = (struct device *)args; - break; - - case DEVICE_CTRL_GET_CONFIG: - switch ((uint32_t)(size_t)args) { - case I2S_GET_TX_FIFO_CMD: - return I2S_GetTxFIFO_AvlCnt(i2s_device->id); - - case I2S_GET_RX_FIFO_CMD: - return I2S_GetRxFIFO_AvlCnt(i2s_device->id); - - default: - break; - } - - break; - default: - return ERROR; - break; - } - - return SUCCESS; -} - -int i2s_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size) -{ - i2s_device_t *i2s_device = (i2s_device_t *)dev; - - if (dev->oflag & DEVICE_OFLAG_DMA_TX) { - struct device *dma_ch = (struct device *)i2s_device->tx_dma; - - if (!dma_ch) { - return -1; - } - - if (i2s_device->id == 0) { - dma_reload(dma_ch, (uint32_t)(uintptr_t)buffer, (uint32_t)DMA_ADDR_I2S_TDR, size); - dma_channel_start(dma_ch); - } else if (i2s_device->id == 1) { - dma_reload(dma_ch, (uint32_t)(uintptr_t)buffer, (uint32_t)DMA_ADDR_I2S_TDR, size); - dma_channel_start(dma_ch); - } - - return 0; - } else { - return 0; - } -} - -int i2s_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size) -{ - i2s_device_t *i2s_device = (i2s_device_t *)dev; - - if (dev->oflag & DEVICE_OFLAG_DMA_RX) { - struct device *dma_ch = (struct device *)i2s_device->rx_dma; - - if (!dma_ch) { - return -1; - } - - if (i2s_device->id == 0) { - dma_reload(dma_ch, (uint32_t)DMA_ADDR_I2S_RDR, (uint32_t)(uintptr_t)buffer, size); - dma_channel_start(dma_ch); - } else if (i2s_device->id == 1) { - dma_reload(dma_ch, (uint32_t)DMA_ADDR_I2S_RDR, (uint32_t)(uintptr_t)buffer, size); - dma_channel_start(dma_ch); - } - - return 0; - } else { - return 0; - } -} - -int i2s_register(enum i2s_index_type index, const char *name) -{ - struct device *dev; - - if (I2S_MAX_INDEX == 0) { - return -DEVICE_EINVAL; - } - - dev = &(i2sx_device[index].parent); - - dev->open = i2s_open; - dev->close = i2s_close; - dev->control = i2s_control; - dev->write = i2s_write; - dev->read = i2s_read; - - dev->type = DEVICE_CLASS_I2S; - dev->handle = NULL; - - return device_register(dev, name); -} - -void i2s_isr(i2s_device_t *handle) -{ - return; -} - -void I2S_IRQ(void) -{ - i2s_isr(&i2sx_device[0]); -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_mtimer.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_mtimer.c deleted file mode 100644 index 34880dd2b8..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_mtimer.c +++ /dev/null @@ -1,139 +0,0 @@ -/** - * @file hal_mtimer.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#include "hal_mtimer.h" -#include "bl808_glb.h" - -static void (*systick_callback)(void); -static uint64_t current_set_ticks = 0; - -static void Systick_Handler(void) -{ - csi_coret_config(current_set_ticks, MTIME_IRQn); - systick_callback(); -} - -/** - * @brief - * - */ -void mtimer_init(void) -{ - uint32_t clkSrc = CPU_Get_MTimer_Source_Clock(); - - CPU_Interrupt_Disable(MTIME_IRQn); - - if (clkSrc > 1 * 1000 * 1000) { - /* Set MTimer clock source 1M */ - CPU_Set_MTimer_CLK(1, clkSrc / 1000 / 1000 - 1); - } else { - /* Set MTimer clock source 1k */ - CPU_Set_MTimer_CLK(1, clkSrc / 1000 - 1); - } - - /* never reset mtimer */ - //CPU_Reset_MTimer(); -} - -/** - * @brief - * - */ -void mtimer_deinit() -{ - CPU_Interrupt_Disable(MTIME_IRQn); -} -/** - * @brief - * - * @param time - * @param interruptFun - */ -void mtimer_set_alarm_time(uint64_t ticks, void (*interruptfun)(void)) -{ - current_set_ticks = ticks; - systick_callback = interruptfun; - - csi_coret_config_use(ticks, MTIME_IRQn); - CPU_Interrupt_Disable(MTIME_IRQn); - Interrupt_Handler_Register(MTIME_IRQn, Systick_Handler); - CPU_Interrupt_Enable(MTIME_IRQn); -} -/** - * @brief - * - */ -void mtimer_start() -{ -} -/** - * @brief - * - */ -void mtimer_stop() -{ -} -/** - * @brief - * - */ -void mtimer_clear_time() -{ - CPU_Reset_MTimer(); -} - -/** - * @brief - * - * @return uint64_t - */ -uint64_t mtimer_get_time_ms() -{ - return CPU_Get_MTimer_MS(); -} -/** - * @brief - * - * @return uint64_t - */ -uint64_t mtimer_get_time_us() -{ - return CPU_Get_MTimer_US(); -} -/** - * @brief - * - * @param time - */ -void mtimer_delay_ms(uint32_t time) -{ - CPU_MTimer_Delay_MS(time); -} -/** - * @brief - * - * @param time - */ -void mtimer_delay_us(uint32_t time) -{ - CPU_MTimer_Delay_US(time); -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_pm.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_pm.c deleted file mode 100644 index 28bcc3b754..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_pm.c +++ /dev/null @@ -1,855 +0,0 @@ -/** - * @file hal_pm.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#include "hal_pm.h" -#include "bl808.h" -#include "bl808_hbn.h" -#include "bl808_pds.h" -#include "hal_flash.h" -#include "hal_rtc.h" - -#define PM_PDS_GPIO_KEEP_EN 0 -#define PM_HBN_GPIO_KEEP_EN 0 -#define PM_PDS_FLASH_POWER_OFF 1 -#define PM_PDS_DLL_POWER_OFF 1 -#define PM_PDS_PLL_POWER_OFF 1 -#define PM_PDS_RF_POWER_OFF 1 -#define PM_PDS_LDO_LEVEL_DEFAULT HBN_LDO_LEVEL_1P10V -#define PM_PDS_DCDC_LEVEL_DEFAULT AON_DCDC_LEVEL_1P100V -#define PM_HBN_LDO_LEVEL_DEFAULT HBN_LDO_LEVEL_0P90V - -/* Cache Way Disable, will get from l1c register */ -uint8_t cacheWayDisable = 0; - -/* PSRAM IO Configuration, will get from glb register */ -uint32_t psramIoCfg = 0; - -/* Flash offset value, will get from sf_ctrl register */ -uint32_t flash_offset = 0; - -SPI_Flash_Cfg_Type *flash_cfg; - -static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel1 = { - .pdsCtl = { - .pdsStart = 1, - .sleepForever = 0, - .xtalForceOff = 0, - .saveWiFiState = 0, - .dcdc11Off = 0, - .bgSysOff = 0, - .ctrlGpioIePuPd = 0, - .dcdc18Off = 1, - .clkOff = 1, - .memStby = 1, - .glbRstProtect = 0, - .isolation = 1, - .waitXtalRdy = 0, - .pdsPwrOff = 1, - .xtalOff = 1, - .socEnbForceOn = 0, - .pdsRstSocEn = 0, - .pdsRC32mOn = 0, - .pdsDcdc11VselEn = 1, - .usbpllOff = 0, - .aupllOff = 1, - .cpupllOff = 1, - .wifipllOff = 1, - .pdsDcdc11Vsel = 0x08, - .pdsCtlRfSel = 3, - .pdsUseTbttSlp = 0, - .pdsGpioIsoMod = 0, - }, - .pdsCtl2 = { - .forceDspPwrOff = 0, - .forceUsbPwrOff = 0, - .forceDspIso = 0, - .forceUsbIso = 0, - .forceMcuPdsRst = 0, - .forceDspPdsRst = 0, - .forceWbPdsRst = 0, - .forceUsbPdsRst = 0, - .forceMcuMemStby = 0, - .forceDspMemStby = 0, - .forceWbMemStby = 0, - .forceUsbMemStby = 0, - .forceMcuGateClk = 0, - .forceDspGateClk = 0, - .forceWbGateClk = 0, - .forceUsbGateClk = 0, - }, - .pdsCtl3 = { - .forceMiscPwrOff = 0, - .forceMiscIsoEn = 0, - .forceMiscPdsRst = 0, - .forceMiscMemStby = 0, - .forceMiscGateClk = 0, - .DspIsoEn = 1, - .UsbIsoEn = 0, - .MiscIsoEn = 0, - }, - .pdsCtl4 = { - .mcuRst = 0, - .mcuMemStby = 0, - .mcuGateClk = 0, - .dspPwrOff = 1, - .dspRst = 1, - .dspMemStby = 1, - .dspGateClk = 1, - .WbRst = 0, - .WbMemStby = 0, - .WbGateClk = 0, - .usbPwrOff = 0, - .usbRst = 0, - .usbMemStby = 0, - .usbGateClk = 0, - .MiscPwrOff = 0, - .MiscRst = 0, - .MiscMemStby = 0, - .MiscGateClk = 0, - }, - .pdsCtl5 = { - .McuWfiMask = 0, - .DspWfiMask = 1, - .LpWfiMask = 1, - .ctrlUsb33 = 1, - .pdLdo18io = 1, - .gpioKeepEn = 7, - } -}; - -static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel2 = { - .pdsCtl = { - .pdsStart = 1, - .sleepForever = 0, - .xtalForceOff = 0, - .saveWiFiState = 0, - .dcdc11Off = 0, - .bgSysOff = 0, - .ctrlGpioIePuPd = 0, - .dcdc18Off = 1, - .clkOff = 1, - .memStby = 1, - .glbRstProtect = 0, - .isolation = 1, - .waitXtalRdy = 0, - .pdsPwrOff = 1, - .xtalOff = 1, - .socEnbForceOn = 0, - .pdsRstSocEn = 0, - .pdsRC32mOn = 0, - .pdsDcdc11VselEn = 1, - .usbpllOff = 1, - .aupllOff = 1, - .cpupllOff = 1, - .wifipllOff = 1, - .pdsDcdc11Vsel = 0x08, - .pdsCtlRfSel = 3, - .pdsUseTbttSlp = 0, - .pdsGpioIsoMod = 0, - }, - .pdsCtl2 = { - .forceDspPwrOff = 0, - .forceUsbPwrOff = 0, - .forceDspIso = 0, - .forceUsbIso = 0, - .forceMcuPdsRst = 0, - .forceDspPdsRst = 0, - .forceWbPdsRst = 0, - .forceUsbPdsRst = 0, - .forceMcuMemStby = 0, - .forceDspMemStby = 0, - .forceWbMemStby = 0, - .forceUsbMemStby = 0, - .forceMcuGateClk = 0, - .forceDspGateClk = 0, - .forceWbGateClk = 0, - .forceUsbGateClk = 0, - }, - .pdsCtl3 = { - .forceMiscPwrOff = 0, - .forceMiscIsoEn = 0, - .forceMiscPdsRst = 0, - .forceMiscMemStby = 0, - .forceMiscGateClk = 0, - .DspIsoEn = 0, - .UsbIsoEn = 1, - .MiscIsoEn = 0, - }, - .pdsCtl4 = { - .mcuRst = 0, - .mcuMemStby = 0, - .mcuGateClk = 0, - .dspPwrOff = 0, - .dspRst = 0, - .dspMemStby = 0, - .dspGateClk = 0, - .WbRst = 0, - .WbMemStby = 0, - .WbGateClk = 0, - .usbPwrOff = 1, - .usbRst = 1, - .usbMemStby = 1, - .usbGateClk = 1, - .MiscPwrOff = 0, - .MiscRst = 0, - .MiscMemStby = 0, - .MiscGateClk = 0, - }, - .pdsCtl5 = { - .McuWfiMask = 0, - .DspWfiMask = 1, - .LpWfiMask = 1, - .ctrlUsb33 = 1, - .pdLdo18io = 1, - .gpioKeepEn = 7, - } -}; - -static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel3 = { - .pdsCtl = { - .pdsStart = 1, - .sleepForever = 0, - .xtalForceOff = 0, - .saveWiFiState = 0, - .dcdc11Off = 0, - .bgSysOff = 0, - .ctrlGpioIePuPd = 0, - .dcdc18Off = 1, - .clkOff = 1, - .memStby = 1, - .glbRstProtect = 0, - .isolation = 1, - .waitXtalRdy = 0, - .pdsPwrOff = 1, - .xtalOff = 1, - .socEnbForceOn = 0, - .pdsRstSocEn = 0, - .pdsRC32mOn = 0, - .pdsDcdc11VselEn = 1, - .usbpllOff = 1, - .aupllOff = 1, - .cpupllOff = 1, - .wifipllOff = 1, - .pdsDcdc11Vsel = 0x08, - .pdsCtlRfSel = 3, - .pdsUseTbttSlp = 0, - .pdsGpioIsoMod = 0, - }, - .pdsCtl2 = { - .forceDspPwrOff = 0, - .forceUsbPwrOff = 0, - .forceDspIso = 0, - .forceUsbIso = 0, - .forceMcuPdsRst = 0, - .forceDspPdsRst = 0, - .forceWbPdsRst = 0, - .forceUsbPdsRst = 0, - .forceMcuMemStby = 0, - .forceDspMemStby = 0, - .forceWbMemStby = 0, - .forceUsbMemStby = 0, - .forceMcuGateClk = 0, - .forceDspGateClk = 0, - .forceWbGateClk = 0, - .forceUsbGateClk = 0, - }, - .pdsCtl3 = { - .forceMiscPwrOff = 0, - .forceMiscIsoEn = 0, - .forceMiscPdsRst = 0, - .forceMiscMemStby = 0, - .forceMiscGateClk = 0, - .DspIsoEn = 1, - .UsbIsoEn = 1, - .MiscIsoEn = 0, - }, - .pdsCtl4 = { - .mcuRst = 0, - .mcuMemStby = 0, - .mcuGateClk = 0, - .dspPwrOff = 1, - .dspRst = 1, - .dspMemStby = 1, - .dspGateClk = 1, - .WbRst = 0, - .WbMemStby = 0, - .WbGateClk = 0, - .usbPwrOff = 1, - .usbRst = 1, - .usbMemStby = 1, - .usbGateClk = 1, - .MiscPwrOff = 0, - .MiscRst = 0, - .MiscMemStby = 0, - .MiscGateClk = 0, - }, - .pdsCtl5 = { - .McuWfiMask = 0, - .DspWfiMask = 1, - .LpWfiMask = 1, - .ctrlUsb33 = 1, - .pdLdo18io = 1, - .gpioKeepEn = 7, - } -}; - -static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel7 = { - .pdsCtl = { - .pdsStart = 1, - .sleepForever = 0, - .xtalForceOff = 1, - .saveWiFiState = 0, - .dcdc11Off = 1, - .bgSysOff = 1, - .ctrlGpioIePuPd = 0, - .dcdc18Off = 1, - .clkOff = 1, - .memStby = 1, - .glbRstProtect = 0, - .isolation = 1, - .waitXtalRdy = 0, - .pdsPwrOff = 1, - .xtalOff = 1, - .socEnbForceOn = 0, - .pdsRstSocEn = 0, - .pdsRC32mOn = 0, - .pdsDcdc11VselEn = 0, - .usbpllOff = 1, - .aupllOff = 1, - .cpupllOff = 1, - .wifipllOff = 1, - .pdsDcdc11Vsel = 0, - .pdsCtlRfSel = 1, - .pdsUseTbttSlp = 0, - .pdsGpioIsoMod = 1, - }, - .pdsCtl2 = { - .forceDspPwrOff = 0, - .forceUsbPwrOff = 0, - .forceDspIso = 0, - .forceUsbIso = 0, - .forceMcuPdsRst = 0, - .forceDspPdsRst = 0, - .forceWbPdsRst = 0, - .forceUsbPdsRst = 0, - .forceMcuMemStby = 0, - .forceDspMemStby = 0, - .forceWbMemStby = 0, - .forceUsbMemStby = 0, - .forceMcuGateClk = 0, - .forceDspGateClk = 0, - .forceWbGateClk = 0, - .forceUsbGateClk = 0, - }, - .pdsCtl3 = { - .forceMiscPwrOff = 0, - .forceMiscIsoEn = 0, - .forceMiscPdsRst = 0, - .forceMiscMemStby = 0, - .forceMiscGateClk = 0, - .DspIsoEn = 1, - .UsbIsoEn = 1, - .MiscIsoEn = 1, - }, - .pdsCtl4 = { - .mcuRst = 1, - .mcuMemStby = 1, - .mcuGateClk = 1, - .dspPwrOff = 1, - .dspRst = 1, - .dspMemStby = 1, - .dspGateClk = 1, - .WbRst = 1, - .WbMemStby = 1, - .WbGateClk = 1, - .usbPwrOff = 1, - .usbRst = 1, - .usbMemStby = 1, - .usbGateClk = 1, - .MiscPwrOff = 1, - .MiscRst = 1, - .MiscMemStby = 1, - .MiscGateClk = 1, - }, - .pdsCtl5 = { - .McuWfiMask = 0, - .DspWfiMask = 1, - .LpWfiMask = 1, - .ctrlUsb33 = 1, - .pdLdo18io = 1, - .gpioKeepEn = 0, - } -}; - -static void pm_hbn_rtc_rst_disable(void) -{ - HBN_RTC_MISC_Type rtcMiscCfg; - - HBN_Get_RTC_Misc_Cfg(&rtcMiscCfg); - rtcMiscCfg.rtcRstEnRtc = 0; - HBN_Set_RTC_Misc_Cfg(&rtcMiscCfg); -} - -/****************************************************************************** - * @brief set power down sleep VDDCORE gpio interrupt mask - * - * @param None - * - * @return SUCCESS or ERROR - * - *******************************************************************************/ -static BL_Err_Type pm_clr_pds_gpio_int(void) -{ - uint32_t tmpVal = 0; - tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT); - // PDS_GPIO_INT_SET_1_GPIO0_GPIO7: - tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_SET1_INT_CLR); - // PDS_GPIO_INT_SET_2_GPIO8_16_GPIO22: - tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_SET2_INT_CLR); - // PDS_GPIO_INT_SET_3_GPIO23_GPIO30: - tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_SET3_INT_CLR); - // PDS_GPIO_INT_SET_4_GPIO31_GPIO38: - tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_SET4_INT_CLR); - - BL_WR_REG(PDS_BASE, PDS_GPIO_INT, tmpVal); - return SUCCESS; -} - -void pm_pds_mask_all_wakeup_src(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); - tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_WAKEUP_SRC_EN); - BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); -} - -static void pm_pds_intc_clr(void) -{ - pm_clr_pds_gpio_int(); - PDS_IntClear(); -} - -/** - * @brief power management in pds(power down sleep) mode - * - * cpu's behavior after wakeup depend on psd level,see flow table if cpu off , - * cpu will reset after wakeup - * - * PD_AON_RTC PD_AON PD_AON_HBNCORE PD_CORE PD_CORE_MISC PD_USB PD_DSP - * PDS0 ON ON ON ON ON ON ON - * PDS1 ON ON ON ON ON ON OFF - * PDS2 ON ON ON ON ON OFF ON - * PDS3 ON ON ON ON ON OFF OFF - * PDS7 ON ON ON ON OFF OFF OFF - */ -void ATTR_TCM_SECTION pm_pds_mode_enter(enum pm_pds_sleep_level pds_level, - uint32_t sleep_time) -{ - PDS_DEFAULT_LV_CFG_Type *pPdsCfg = NULL; - uint32_t tmpVal; - uint32_t flash_cfg_len; - uint32_t pds_ram1; - uint32_t pds_ram2; - - /* To make it simple and safe*/ - cpu_global_irq_disable(); - - pm_hbn_rtc_rst_disable(); - - flash_get_cfg((uint8_t **)&flash_cfg, &flash_cfg_len); - - HBN_Set_Ldo11_All_Vout(PM_PDS_LDO_LEVEL_DEFAULT); - AON_Set_DCDC11_Top_Vout(PM_PDS_DCDC_LEVEL_DEFAULT); - /************************ PDS INT SET ***********************/ - // PDS_WAKEUP_IRQHandler_Install(); - BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0xffffffff); - BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0); - - tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); - - if (sleep_time) { - tmpVal |= (1 << 10); // unmask pds sleep time wakeup - } - - BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); - - /* clear all interrupt status */ - pm_pds_intc_clr(); - - /* enable PDS interrupt to wakeup CPU (PDS1:CPU not powerdown, CPU __WFI)*/ - pm_pds_irq_register(); - /***********************************************************/ - - switch (pds_level) { - case PM_PDS_LEVEL_1: - pPdsCfg = &pdsCfgLevel1; - break; - case PM_PDS_LEVEL_2: - pPdsCfg = &pdsCfgLevel2; - break; - case PM_PDS_LEVEL_3: - pPdsCfg = &pdsCfgLevel3; - break; - case PM_PDS_LEVEL_7: - pPdsCfg = &pdsCfgLevel7; - break; - default: - return; - } - -#if PM_PDS_FLASH_POWER_OFF - uint32_t sw_cfg0 = 0; - SF_Ctrl_Pin_Select sf_pin_select = 0; - - /* get sw uasge 0 */ - EF_Ctrl_Read_Sw_Usage(0, (uint32_t *)&sw_cfg0); - sf_pin_select = (tmpVal >> 14) & 0x3f; - flash_get_cfg((uint8_t **)&flash_cfg, &flash_cfg_len); - - HBN_Power_Down_Flash(flash_cfg); - - /* LDO_FLASH Pull down */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_LDO18FLASH); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_PU_LDO18FLASH); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_LDO18FLASH_PULLDOWN); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_LDO18FLASH_PULLDOWN_SEL); - BL_WR_REG(GLB_BASE, GLB_LDO18FLASH, tmpVal); - - /* Turn Off Flash PAD IE */ - /* GPIO46~51 */ - for (int i = 0; i < 6; i++) { - BL_WR_WORD(GLB_BASE + GLB_GPIO_CFG46_OFFSET + i * 4, 0); - } - - /* Turn Off PSRAM PAD IE */ - /* GPIO52~63 */ - for (int i = 0; i < 12; i++) { - BL_WR_WORD(GLB_BASE + GLB_GPIO_CFG52_OFFSET + i * 4, 0); - } -#endif - -#if PM_PDS_GPIO_KEEP_EN - pPdsCfg->pdsCtl.pdsGpioIsoMod = 1; - pPdsCfg->pdsCtl5.gpioKeepEn = 7; -#endif - -#if PM_PDS_PLL_POWER_OFF - /*************************** Clock Config **************************/ - GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_RC32M); // MCU CLK SELECT RC32M - GLB_Set_DSP_System_CLK(GLB_DSP_SYS_CLK_RC32M); - - GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_CPUPLL); - GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_WIFIPLL); - GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_AUPLL); - - /* Power Down Mipi PLL */ - GLB_Power_Off_MU_PLL(GLB_MU_PLL_MIPIPLL); - /* Power Down UHS(PSRAM) PLL */ - GLB_Power_Off_MU_PLL(GLB_MU_PLL_UHSPLL); - - // GLB_Set_SF_CLK(1, GLB_SFLASH_CLK_BCLK, 0); - tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL); - tmpVal |= (0x3 << 9); - BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal); - /**************************************************************/ -#endif - -#if PM_PDS_RF_POWER_OFF == 0 - pPdsCfg->pdsCtl.pdsCtlRfSel = 0; -#endif - - if (0xFFFFFFFF != BL_RD_REG(PDS_BASE, PDS_GPIO_PD_SET)) { - pPdsCfg->pdsCtl.ctrlGpioIePuPd = 1; - } - - /* LDO12_UHS Pull down */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_LDO12UHS); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_PU_LDO12UHS); - BL_WR_REG(GLB_BASE, GLB_LDO12UHS, tmpVal); - - /* LDO15_CIS Pull down */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_LDO15CIS); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_PU_LDO15CIS); - BL_WR_REG(GLB_BASE, GLB_LDO15CIS, tmpVal); - - /* DCDC18 Pull down When disable */ - tmpVal = BL_RD_REG(AON_BASE, AON_DCDC18_TOP_1); - tmpVal = BL_SET_REG_BIT(tmpVal, AON_DCDC18_PULLDOWN_AON); - BL_WR_REG(AON_BASE, AON_DCDC18_TOP_1, tmpVal); - - /* LDO28_CIS Pull down */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_LDO28CIS); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_PU_LDO28CIS); - BL_WR_REG(GLB_BASE, GLB_LDO28CIS, tmpVal); - - pds_ram1 = BL_RD_REG(PDS_BASE, PDS_RAM1); - pds_ram2 = BL_RD_REG(PDS_BASE, PDS_RAM2); - - /* PD_CORE's SRAM Clock Gating During PDS Mode */ - pds_ram1 |= (1 << 31); - - if (pds_level == PM_PDS_LEVEL_7) { - pds_ram1 &= ~(0xf < 4); // ocram retention - pds_ram1 |= 0xf; // ocram sleep - pds_ram2 &= ~(0x3ff < 9); // wram retention - pds_ram2 |= (0x380 < 9); // wram retention - pds_ram2 &= ~0x3ff; - pds_ram2 |= 0x7f; // wram sleep - } - - PDS_Default_Level_Config(pPdsCfg, (PDS_CTRL_RAM1_Type *)&pds_ram1, - (PDS_CTRL_RAM2_Type *)&pds_ram2, sleep_time); - - __WFI(); - - /****************************** Wakeup Flow *******************************/ - HBN_Set_Ldo11_All_Vout(HBN_LDO_LEVEL_1P10V); - AON_Set_DCDC11_Top_Vout(AON_DCDC_LEVEL_1P100V); - - /* LDO28_CIS Pull On */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_LDO28CIS); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_PU_LDO28CIS); - BL_WR_REG(GLB_BASE, GLB_LDO28CIS, tmpVal); - - /* DCDC18 Pull On*/ - tmpVal = BL_RD_REG(AON_BASE, AON_DCDC18_TOP_1); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_DCDC18_PULLDOWN_AON); - BL_WR_REG(AON_BASE, AON_DCDC18_TOP_1, tmpVal); - - /* LDO15_CIS Pull On */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_LDO15CIS); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_PU_LDO15CIS); - BL_WR_REG(GLB_BASE, GLB_LDO15CIS, tmpVal); - - /* LDO12_UHS Pull On */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_LDO12UHS); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_PU_LDO12UHS); - BL_WR_REG(GLB_BASE, GLB_LDO12UHS, tmpVal); - -#if PM_PDS_PLL_POWER_OFF - GLB_Power_On_XTAL_And_PLL_CLK(GLB_XTAL_40M, GLB_PLL_WIFIPLL); - GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_WIFIPLL_320M); - GLB_Set_DSP_System_CLK(GLB_DSP_SYS_CLK_CPUPLL_400M); -#endif - -#if PM_PDS_FLASH_POWER_OFF - if (pds_level <= PM_PDS_LEVEL_3) { - /* Init flash gpio */ - SF_Cfg_Init_Ext_Flash_Gpio(0); - SF_Cfg_Init_Flash_Gpio(sf_pin_select, 1); - SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB); - SFlash_Restore_From_Powerdown(flash_cfg, 0, SF_CTRL_FLASH_BANK0); - } -#endif - - cpu_global_irq_enable(); -} - -/** - * @brief - * - * power management in hbn(hibernation) mode - * cpu will reset after wakeup - * - * HBN_LEVEL PD_AON_RTC PD_AON PD_AON_HBNCORE PD_CORE&PD_CORE_MISC&PD_USB&PD_MM - * HBN0 ON ON ON OFF - * HBN1 ON ON OFF OFF - * HBN2 ON OFF OFF OFF - * - * @param hbn_level - */ -void ATTR_TCM_SECTION pm_hbn_mode_enter(enum pm_hbn_sleep_level hbn_level, - uint8_t sleep_time) -{ - uint32_t tmpVal; - - /* To make it simple and safe*/ - cpu_global_irq_disable(); - - CPU_Interrupt_Pending_Clear(HBN_OUT0_IRQn); - CPU_Interrupt_Pending_Clear(HBN_OUT1_IRQn); - - BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0xffffffff); - BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0); - - if (sleep_time) { - rtc_init(sleep_time); // sleep time,unit is second - } - - if (hbn_level >= PM_HBN_LEVEL_2) { - HBN_PD_RC32K_In_Poff(); - } - -#if PM_PDS_FLASH_POWER_OFF - HBN_Power_Down_Flash(NULL); -#endif - -#if PM_HBN_GPIO_KEEP_EN - tmpVal = BL_RD_REG(HBN_BASE, HBN_PAD_CTRL_0); - tmpVal = BL_SET_REG_BIT(tmpVal, HBN_REG_AON_GPIO_ISO_MODE); - tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_REG_EN_AON_CTRL_GPIO); - BL_WR_REG(HBN_BASE, HBN_PAD_CTRL_0, tmpVal); -#endif - - /* Select RC32M */ - // GLB_Set_System_CLK(GLB_DLL_XTAL_NONE, GLB_SYS_CLK_RC32M); - GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_RC32M); - /* power off pll */ - GLB_Power_Off_MU_PLL(GLB_MU_PLL_MIPIPLL); - GLB_Power_Off_MU_PLL(GLB_MU_PLL_UHSPLL); - /* power off xtal */ - AON_Power_Off_XTAL(); - - /* HBN mode LDO level */ - tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_LDO11_AON_VOUT_SEL, - PM_HBN_LDO_LEVEL_DEFAULT); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_LDO11_RT_VOUT_SEL, - PM_HBN_LDO_LEVEL_DEFAULT); - BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); - - /* Set HBN flag */ - BL_WR_REG(HBN_BASE, HBN_RSV0, HBN_STATUS_ENTER_FLAG); - - tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); - - /* Set HBN level, (HBN_PWRDN_HBN_RAM not use) */ - if (hbn_level < PM_HBN_LEVEL_1) { - tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE); - } - - /* Set power on option:0 for por reset twice for robust 1 for reset only - * once*/ - tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWR_ON_OPTION); - BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); - - /* Enable HBN mode */ - tmpVal = BL_SET_REG_BIT(tmpVal, HBN_MODE); - BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); - - while (1) { - arch_delay_ms(100); - GLB_SW_POR_Reset(); - } -} - -void pm_hbn_out0_irq_register(void) -{ - Interrupt_Handler_Register(HBN_OUT0_IRQn, HBN_OUT0_IRQ); - CPU_Interrupt_Enable(HBN_OUT0_IRQn); -} - -void pm_hbn_out1_irq_register(void) -{ - Interrupt_Handler_Register(HBN_OUT1_IRQn, HBN_OUT1_IRQ); - CPU_Interrupt_Enable(HBN_OUT1_IRQn); -} - -void HBN_OUT0_IRQ(void) -{ - if (SET == HBN_Get_INT_State(HBN_INT_GPIO9)) { - HBN_Clear_IRQ(HBN_INT_GPIO9); - pm_irq_callback(PM_HBN_GPIO9_WAKEUP_EVENT); - } else if (SET == HBN_Get_INT_State(HBN_INT_GPIO10)) { - HBN_Clear_IRQ(HBN_INT_GPIO10); - pm_irq_callback(PM_HBN_GPIO10_WAKEUP_EVENT); - } else if (SET == HBN_Get_INT_State(HBN_INT_GPIO11)) { - HBN_Clear_IRQ(HBN_INT_GPIO11); - pm_irq_callback(PM_HBN_GPIO11_WAKEUP_EVENT); - } else if (SET == HBN_Get_INT_State(HBN_INT_GPIO12)) { - HBN_Clear_IRQ(HBN_INT_GPIO12); - pm_irq_callback(PM_HBN_GPIO12_WAKEUP_EVENT); - } else if (SET == HBN_Get_INT_State(HBN_INT_GPIO13)) { - HBN_Clear_IRQ(HBN_INT_GPIO13); - pm_irq_callback(PM_HBN_GPIO13_WAKEUP_EVENT); - } else if (SET == HBN_Get_INT_State(HBN_INT_GPIO14)) { - HBN_Clear_IRQ(HBN_INT_GPIO14); - pm_irq_callback(PM_HBN_GPIO14_WAKEUP_EVENT); - } else if (SET == HBN_Get_INT_State(HBN_INT_GPIO15)) { - HBN_Clear_IRQ(HBN_INT_GPIO15); - pm_irq_callback(PM_HBN_GPIO15_WAKEUP_EVENT); - } else if (SET == HBN_Get_INT_State(HBN_INT_GPIO40)) { - HBN_Clear_IRQ(HBN_INT_GPIO40); - pm_irq_callback(PM_HBN_GPIO40_WAKEUP_EVENT); - } else if (SET == HBN_Get_INT_State(HBN_INT_GPIO41)) { - HBN_Clear_IRQ(HBN_INT_GPIO41); - pm_irq_callback(PM_HBN_GPIO41_WAKEUP_EVENT); - } else { - HBN_Clear_IRQ(HBN_INT_RTC); - HBN_Clear_RTC_INT(); - pm_irq_callback(PM_HBN_RTC_WAKEUP_EVENT); - } -} - -void ATTR_TCM_SECTION HBN_OUT1_IRQ(void) -{ - /* PIR */ - if (SET == HBN_Get_INT_State(HBN_INT_PIR)) { - HBN_Clear_IRQ(HBN_INT_PIR); - } - /* BOR */ - else if (SET == HBN_Get_INT_State(HBN_INT_BOD)) { - HBN_Clear_IRQ(HBN_INT_BOD); - pm_irq_callback(PM_HBN_BOD_WAKEUP_EVENT); - } - /* ACOMP0 */ - else if (SET == HBN_Get_INT_State(HBN_INT_ACOMP0)) { - HBN_Clear_IRQ(HBN_INT_ACOMP0); - pm_irq_callback(PM_HBN_ACOMP0_WAKEUP_EVENT); - } - /* ACOMP1 */ - else if (SET == HBN_Get_INT_State(HBN_INT_ACOMP1)) { - HBN_Clear_IRQ(HBN_INT_ACOMP1); - pm_irq_callback(PM_HBN_ACOMP1_WAKEUP_EVENT); - } -} - -__WEAK void pm_irq_callback(enum pm_event_type event) -{ -} - -void pm_pds_irq_register(void) -{ - Interrupt_Handler_Register(PDS_WAKEUP_IRQn, PDS_WAKEUP_IRQ); - CPU_Interrupt_Enable(PDS_WAKEUP_IRQn); -} - -void ATTR_TCM_SECTION PDS_WAKEUP_IRQ(void) -{ - /* WAKE INT */ - if (SET == PDS_Get_IntStatus(PDS_INT_WAKEUP)) { - } - /* RF DONE */ - else if (SET == PDS_Get_IntStatus(PDS_INT_RF_DONE)) { - } - /* WIFI_TBTT_SLEEP */ - else if (SET == PDS_Get_IntStatus(PDS_INT_WIFI_TBTT_SLEEP)) { - } - /* WIFI_TBTT_WAKEUP */ - else if (SET == PDS_Get_IntStatus(PDS_INT_WIFI_TBTT_WAKEUP)) { - } - - PDS_IntClear(); -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_pwm.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_pwm.c deleted file mode 100644 index 65c2513db4..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_pwm.c +++ /dev/null @@ -1,205 +0,0 @@ -/** - * @file hal_pwm.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#include "hal_pwm.h" -#include "hal_clock.h" -#include "bl808_pwm.h" - -static pwm_device_t pwmx_device[PWM_MAX_INDEX] = { -#ifdef BSP_USING_PWM0 - PWM0_CONFIG, -#endif -#ifdef BSP_USING_PWM1 - PWM1_CONFIG, -#endif -}; - -static void PWM_IRQ(void); - -int pwm_open(struct device *dev, uint16_t oflag) -{ - pwm_device_t *pwm_device = (pwm_device_t *)dev; - PWMx_CFG_Type pwmxCfg = { 0 }; - - CPU_Interrupt_Disable(PWM_IRQn); - PWMx_Disable(pwm_device->id); - PWM_SW_Break_Disable(pwm_device->id); - PWM_Int_Mask(pwm_device->id, PWM_INT_ALL, MASK); - - pwmxCfg.clk = pwm_device->clk_source; - pwmxCfg.clkDiv = pwm_device->clk_div; - pwmxCfg.stopMode = PWM_STOP_GRACEFUL; - pwmxCfg.stpRept = pwm_device->output_mode; - pwmxCfg.extPol = pwm_device->extern_break_polarity; - pwmxCfg.adcSrc = pwm_device->adc_trig_source; - pwmxCfg.intPulseCnt = pwm_device->pulse; - PWMx_Init(pwm_device->id, &pwmxCfg); - - if (pwm_device->extern_break_enable) { - PWM_EXT_Break_Enable(pwm_device->id); - } else { - PWM_EXT_Break_Disable(pwm_device->id); - } - - if (pwm_device->internal_break_enable) { - PWM_SW_Break_Enable(pwm_device->id); - } else { - PWM_SW_Break_Disable(pwm_device->id); - } - - Interrupt_Handler_Register(PWM_IRQn, PWM_IRQ); - CPU_Interrupt_Enable(PWM_IRQn); - - return 0; -} -int pwm_close(struct device *dev) -{ - pwm_device_t *pwm_device = (pwm_device_t *)dev; - PWM_CHx_CFG_Type chxCfg = { 0 }; - - CPU_Interrupt_Disable(PWM_IRQn); - PWMx_Disable(pwm_device->id); - PWM_Int_Mask(pwm_device->id, PWM_INT_ALL, MASK); - - for (uint8_t i = 0; i < PWM_CHx_MAX; i++) { - PWM_Channelx_Init(pwm_device->id, i, &chxCfg); - } - PWM_SW_Break_Disable(pwm_device->id); - PWM_EXT_Break_Disable(pwm_device->id); - - return 0; -} - -int pwm_control(struct device *dev, int cmd, void *args) -{ - pwm_device_t *pwm_device = (pwm_device_t *)dev; - - switch (cmd) { - case DEVICE_CTRL_SET_INT: - break; - case DEVICE_CTRL_CLR_INT: - break; - case DEVICE_CTRL_CONFIG: - break; - case DEVICE_CTRL_PWM_CHANNEL_CONFIG: { - pwm_channel_common_t *config = (pwm_channel_common_t *)args; - - PWM_Channelx_Pwm_Mode_Set(pwm_device->id, config->ch, config->chp_enable, config->chn_enable); - PWM_Channelx_Polarity_Set(pwm_device->id, config->ch, config->chp_polarity, config->chn_polarity); - PWM_Channelx_Idle_State_Set(pwm_device->id, config->ch, config->chp_idlestate, config->chn_idlestate); - PWM_Channelx_Threshold_Set(pwm_device->id, config->ch, config->threshold_low, config->threshold_high); - - } break; - - case DEVICE_CTRL_RESUME: - PWMx_Enable(pwm_device->id); - break; - - case DEVICE_CTRL_SUSPEND: - PWMx_Disable(pwm_device->id); - break; - - case DEVICE_CTRL_PWM_FREQUENCE_CONFIG: - PWMx_Period_Set(pwm_device->id, (uint32_t)(uintptr_t)args); - break; - - case DEVICE_CTRL_PWM_DUTYCYCLE_CONFIG: { - pwm_channel_dutycycle_t *config = (pwm_channel_dutycycle_t *)args; - PWM_Channelx_Threshold_Set(pwm_device->id, config->ch, config->threshold_low, config->threshold_high); - } - - break; - - case DEVICE_CTRL_PWM_PULSE_CONFIG: { - uint32_t tmpVal; - uint32_t PWMx = PWM_BASE + PWM_CHANNEL_OFFSET + (pwm_device->id) * 0x40; - tmpVal = BL_RD_REG(PWMx, PWM_PERIOD); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_INT_PERIOD_CNT, (uint32_t)(uintptr_t)args); - BL_WR_REG(PWMx, PWM_PERIOD, tmpVal); - } break; - case DEVICE_CTRL_PWM_BREAK_CONFIG: { - pwm_channel_break_t *config = (pwm_channel_break_t *)args; - PWM_Channelx_Break_State_Set(pwm_device->id, config->ch, config->chp_breakstate, config->chn_breakstate); - PWM_Channelx_Dtg_Set(pwm_device->id, config->ch, config->deadtime); - } - - break; - default: - break; - } - - return 0; -} - -int pwm_register(enum pwm_index_type index, const char *name) -{ - struct device *dev; - - if (PWM_MAX_INDEX == 0) { - return -DEVICE_EINVAL; - } - - dev = &(pwmx_device[index].parent); - - dev->open = pwm_open; - dev->close = pwm_close; - dev->control = pwm_control; - dev->write = NULL; - dev->read = NULL; - - dev->type = DEVICE_CLASS_PWM; - dev->handle = NULL; - - return device_register(dev, name); -} - -static void pwm_isr(pwm_device_t *handle) -{ - uint32_t tmpVal = 0; - uint32_t maskVal = 0; - uint32_t PWMx; - uint16_t intIndex; - - if (!handle->parent.callback) { - return; - } - - /* Get PWMx start register address */ - PWMx = PWM_BASE + PWM_CHANNEL_OFFSET + (handle->id) * 0x40; - - tmpVal = BL_RD_REG(PWMx, PWM_INT_STS); - maskVal = BL_RD_REG(PWMx, PWM_INT_MASK); - - for (intIndex = 0; intIndex < PWM_INT_ALL; intIndex++) { - if (((1 << intIndex) & tmpVal) && (((1 << intIndex) & maskVal) == 0)) { - BL_WR_REG(PWMx, PWM_INT_CLEAR, 1 << intIndex); - handle->parent.callback(&handle->parent, NULL, 0, 1 << intIndex); - } - } -} - -static void PWM_IRQ(void) -{ - for (int8_t i = 0; i < PWM_MAX_INDEX; i++) { - pwm_isr(&pwmx_device[i]); - } -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_rtc.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_rtc.c deleted file mode 100644 index 7210eaa341..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_rtc.c +++ /dev/null @@ -1,102 +0,0 @@ -/** - * @file hal_rtc.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#include "hal_rtc.h" -#include "bl808_hbn.h" -static uint64_t current_timestamp = 0; - -/** - * @brief rtc init withc sleep time - * - * @param sleep_time - */ -void rtc_init(uint64_t sleep_time) -{ - uint32_t tmpVal; - uint32_t comp_l, comp_h; - - /* Clear & Disable RTC counter */ - tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); - /* Clear RTC control bit0 */ - BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal & 0xfffffff0); - - /* Get current RTC timer */ - /* Tigger RTC val read */ - tmpVal = BL_RD_REG(HBN_BASE, HBN_RTC_TIME_H); - tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RTC_TIME_LATCH); - BL_WR_REG(HBN_BASE, HBN_RTC_TIME_H, tmpVal); - tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RTC_TIME_LATCH); - BL_WR_REG(HBN_BASE, HBN_RTC_TIME_H, tmpVal); - - /* Read RTC val */ - comp_l = BL_RD_REG(HBN_BASE, HBN_RTC_TIME_L); - comp_h = (BL_RD_REG(HBN_BASE, HBN_RTC_TIME_H) & 0xff); - - /* calculate RTC Comp time */ - comp_l += (uint32_t)((sleep_time * 32768) & 0xFFFFFFFF); - comp_h += (uint32_t)(((sleep_time * 32768) >> 32) & 0xFFFFFFFF); - - /* Set RTC Comp time */ - BL_WR_REG(HBN_BASE, HBN_TIME_L, comp_l); - BL_WR_REG(HBN_BASE, HBN_TIME_H, comp_h & 0xff); - - tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); - /* Set interrupt delay option */ - tmpVal = - BL_SET_REG_BITS_VAL(tmpVal, HBN_RTC_DLY_OPTION, HBN_RTC_INT_DELAY_0T); - /* Set RTC compare mode */ - tmpVal |= (HBN_RTC_COMP_BIT0_39 << 1); - BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); - - /* Enable RTC Counter */ - tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); - /* Set RTC control bit0 */ - BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal | 0x01); -} - -void rtc_set_timestamp(uint64_t time_stamp) -{ - current_timestamp = time_stamp; -} -/** - * @bref Get rtc value - * - */ -uint64_t rtc_get_timestamp(void) -{ - uint32_t tmpVal; - uint64_t time_l; - uint64_t time_h; - - /* Tigger RTC val read */ - tmpVal = BL_RD_REG(HBN_BASE, HBN_RTC_TIME_H); - tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RTC_TIME_LATCH); - BL_WR_REG(HBN_BASE, HBN_RTC_TIME_H, tmpVal); - tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RTC_TIME_LATCH); - BL_WR_REG(HBN_BASE, HBN_RTC_TIME_H, tmpVal); - - /* Read RTC val */ - time_l = BL_RD_REG(HBN_BASE, HBN_RTC_TIME_L); - time_h = (BL_RD_REG(HBN_BASE, HBN_RTC_TIME_H) & 0xff); - - return (((time_h << 32 | time_l) >> 15) + current_timestamp); -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_sec_aes.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_sec_aes.c deleted file mode 100644 index ee7a5ae838..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_sec_aes.c +++ /dev/null @@ -1,125 +0,0 @@ -/** - * @file hal_sec_aes.c - * @brief - * - * Copyright 2019-2030 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#include "hal_sec_aes.h" -#include "bl808_sec_eng.h" - -static SEC_Eng_AES_Ctx aesCtx; - -int sec_aes_init(sec_aes_handle_t *handle, sec_aes_type aes_tye, sec_aes_key_type key_type) -{ - handle->aes_type = aes_tye; - handle->key_type = key_type; - - return 0; -} - -static SEC_ENG_AES_Key_Type sec_aes_get_key_type(sec_aes_handle_t *handle) -{ - SEC_ENG_AES_Key_Type type = 0; - - switch (handle->key_type) { - case SEC_AES_KEY_128: - type = SEC_ENG_AES_KEY_128BITS; - break; - - case SEC_AES_KEY_256: - type = SEC_ENG_AES_KEY_256BITS; - break; - - case SEC_AES_KEY_192: - type = SEC_ENG_AES_KEY_192BITS; - break; - - default: - return SEC_ENG_AES_KEY_128BITS; - } - - return type; -} - -int sec_aes_setkey(sec_aes_handle_t *handle, const uint8_t *key, uint8_t key_len, const uint8_t *nonce, uint8_t dir) -{ - SEC_ENG_AES_Key_Type type = sec_aes_get_key_type(handle); - - switch (handle->aes_type) { - case SEC_AES_CBC: - Sec_Eng_AES_Enable_BE(SEC_ENG_AES_ID0); - Sec_Eng_AES_Init(&aesCtx, SEC_ENG_AES_ID0, SEC_ENG_AES_CBC, type, - SEC_AES_DIR_ENCRYPT == dir ? SEC_ENG_AES_ENCRYPTION : SEC_ENG_AES_DECRYPTION); - break; - - case SEC_AES_CTR: - Sec_Eng_AES_Enable_BE(SEC_ENG_AES_ID0); - Sec_Eng_AES_Init(&aesCtx, SEC_ENG_AES_ID0, SEC_ENG_AES_CTR, type, - SEC_AES_DIR_ENCRYPT == dir ? SEC_ENG_AES_ENCRYPTION : SEC_ENG_AES_DECRYPTION); - break; - - case SEC_AES_XTS: - Sec_Eng_AES_Enable_BE(SEC_ENG_AES_ID0); - Sec_Eng_AES_Init(&aesCtx, SEC_ENG_AES_ID0, SEC_ENG_AES_XTS, type, - SEC_AES_DIR_ENCRYPT == dir ? SEC_ENG_AES_ENCRYPTION : SEC_ENG_AES_DECRYPTION); - break; - - case SEC_AES_ECB: - break; - - default: - return -1; - } - - /* if key len is 0, means key is from efuse and *key value is key_sel value */ - if (key_len == 0) { - Sec_Eng_AES_Set_Key_IV_BE(SEC_ENG_AES_ID0, SEC_ENG_AES_KEY_HW, key, nonce); - } else { - Sec_Eng_AES_Set_Key_IV_BE(SEC_ENG_AES_ID0, SEC_ENG_AES_KEY_SW, key, nonce); - } - - return 0; -} - -int sec_aes_encrypt(sec_aes_handle_t *handle, const uint8_t *in, uint32_t len, size_t offset, uint8_t *out) -{ - if (SUCCESS != Sec_Eng_AES_Crypt(&aesCtx, SEC_ENG_AES_ID0, in, len, out)) { - return -1; - } - - return 0; -} - -int sec_aes_decrypt(sec_aes_handle_t *handle, const uint8_t *in, uint32_t len, size_t offset, uint8_t *out) -{ - if (SUCCESS != Sec_Eng_AES_Crypt(&aesCtx, SEC_ENG_AES_ID0, in, len, out)) { - return -1; - } - - return 0; -} - -int sec_aes_deinit(sec_aes_handle_t *handle) -{ - Sec_Eng_AES_Finish(SEC_ENG_AES_ID0); - - memset(handle, 0, sizeof(sec_aes_handle_t)); - - return 0; -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_sec_dsa.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_sec_dsa.c deleted file mode 100644 index 72901dbecc..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_sec_dsa.c +++ /dev/null @@ -1,389 +0,0 @@ -/** - * @file hal_sec_dsa.c - * @brief - * - * Copyright 2019-2030 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#include "hal_sec_dsa.h" -#include "bl808_sec_eng.h" - -//#define DSA_DBG 1 -//#define DSA_DBG_DETAIL 1 -void bflb_platform_dump(uint8_t *data, uint32_t len); - -#if (defined(DSA_DBG) || defined(DSA_DBG_DETAIL)) -uint32_t pka_tmp[64] = { 0 }; -#endif - -/* -n=p*q; -F(n)=(p-1)*(q-1) -e*d%F(n)=1[e is public key and d is private key] -dP=d%(p-1) -dQ=d%(q-1) -m1=c^(dP)%p -m2=c^(dQ)%q -h=qInv*(m1-m2)%p -m=m2+h*q -m=c^d -*/ -static SEC_ENG_PKA_REG_SIZE_Type sec_dsa_get_reg_size(uint32_t size) -{ - switch (size) { - case 64: - return SEC_ENG_PKA_REG_SIZE_8; - - case 128: - return SEC_ENG_PKA_REG_SIZE_16; - - case 256: - return SEC_ENG_PKA_REG_SIZE_32; - - case 512: - return SEC_ENG_PKA_REG_SIZE_64; - - case 768: - return SEC_ENG_PKA_REG_SIZE_96; - - case 1024: - return SEC_ENG_PKA_REG_SIZE_128; - - case 1536: - return SEC_ENG_PKA_REG_SIZE_192; - - case 2048: - return SEC_ENG_PKA_REG_SIZE_256; - - case 3072: - return SEC_ENG_PKA_REG_SIZE_384; - - case 4096: - return SEC_ENG_PKA_REG_SIZE_512; - - default: - return SEC_ENG_PKA_REG_SIZE_32; - } - - return SEC_ENG_PKA_REG_SIZE_32; -} - -/* c code: -number = 1 -base = a -while b: - if b & 1: - number = number * base % c - b >>= 1 - base = base * base % c -return number -*/ -int sec_dsa_mexp_binary(uint32_t size, const uint32_t *a, const uint32_t *b, const uint32_t *c, uint32_t *r) -{ - uint32_t i, j, k; - uint32_t tmp; - uint32_t isOne = 0; - uint8_t *p = (uint8_t *)b; - SEC_ENG_PKA_REG_SIZE_Type nregType = sec_dsa_get_reg_size(size); - SEC_ENG_PKA_REG_SIZE_Type lregType = sec_dsa_get_reg_size(size * 2); - uint32_t dataSize = (size >> 3) >> 2; -#if 1 - uint8_t oneBuf[128] ALIGN4 = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 }; -#endif - /* 0:c - * 4:a - * 5:number - * 6&7:temp - */ - - /* base = a */ - Sec_Eng_PKA_Write_Data(nregType, 4, (uint32_t *)a, dataSize, 0); - - /* number = 1 */ - Sec_Eng_PKA_Write_Data(nregType, 5, (uint32_t *)oneBuf, sizeof(oneBuf) / 4, 0); - //Sec_Eng_PKA_Write_Immediate(nregType,5,0x01,1); -#ifdef DSA_DBG - Sec_Eng_PKA_Read_Data(nregType, 5, (uint32_t *)pka_tmp, dataSize); - MSG("number:\r\n"); - bflb_platform_dump(pka_tmp, dataSize * 4); -#endif - - Sec_Eng_PKA_Write_Data(nregType, 0, (uint32_t *)c, dataSize, 0); - - Sec_Eng_PKA_CREG(nregType, 6, dataSize, 1); - Sec_Eng_PKA_CREG(nregType, 7, dataSize, 1); -#ifdef DSA_DBG - Sec_Eng_PKA_Read_Data(nregType, 4, (uint32_t *)pka_tmp, dataSize); - MSG("base:\r\n"); - bflb_platform_dump(pka_tmp, dataSize * 4); -#endif - /* Remove zeros bytes*/ - k = 0; - - while (p[k] == 0 && k < (size >> 3)) { - k++; - } - - i = (size >> 3) - 1; - - for (; i >= k; i--) { - tmp = p[i]; - j = 0; - - for (j = 0; j < 8; j++) { - isOne = tmp & (1 << j); - - if (isOne) { - /* number = number * base % c */ - Sec_Eng_PKA_LMUL(lregType, 3, nregType, 5, nregType, 4, 0); - Sec_Eng_PKA_MREM(nregType, 5, lregType, 3, nregType, 0, 1); -#ifdef DSA_DBG - Sec_Eng_PKA_Read_Data(nregType, 5, (uint32_t *)pka_tmp, dataSize); - MSG("number:\r\n"); - bflb_platform_dump(pka_tmp, dataSize /*dataSize*4*/); -#endif - } - - /* base = base * base % c */ - Sec_Eng_PKA_LSQR(lregType, 3, nregType, 4, 0); - Sec_Eng_PKA_MREM(nregType, 4, lregType, 3, nregType, 0, 1); -#ifdef DSA_DBG - Sec_Eng_PKA_Read_Data(nregType, 4, (uint32_t *)pka_tmp, dataSize); - MSG("base:\r\n"); - bflb_platform_dump(pka_tmp, dataSize /*dataSize*4*/); -#endif - } - } - - Sec_Eng_PKA_Read_Data(nregType, 5, (uint32_t *)r, dataSize); -#ifdef DSA_DBG - MSG("r:\r\n"); - bflb_platform_dump(r, dataSize * 4); -#endif - return 0; -} - -/*r=a^b%c*/ -int sec_dsa_mexp_mont(uint32_t size, uint32_t *a, uint32_t *b, uint32_t *c, uint32_t *invR_c, uint32_t *primeN_c, uint32_t *r) -{ - SEC_ENG_PKA_REG_SIZE_Type nregType = sec_dsa_get_reg_size(size); - SEC_ENG_PKA_REG_SIZE_Type lregType = sec_dsa_get_reg_size(size * 2); - uint32_t dataSize = (size >> 3) >> 2; - - /* 0:c - * 1:NPrime_c - * 2:invR_c - * 4:a(mont domain) - * 5:b - * 6:a^b%c(mont domain) - * 7:a^b%c(gf domain) - * 10&11:2^size for GF2Mont*/ - Sec_Eng_PKA_Write_Data(nregType, 0, (uint32_t *)c, dataSize, 0); - Sec_Eng_PKA_Write_Data(nregType, 1, (uint32_t *)primeN_c, dataSize, 1); - Sec_Eng_PKA_Write_Data(nregType, 2, (uint32_t *)invR_c, dataSize, 1); - - /* change a into mont domain*/ - Sec_Eng_PKA_Write_Data(nregType, 4, (uint32_t *)a, dataSize, 0); - Sec_Eng_PKA_CREG(nregType, 10, dataSize, 1); - Sec_Eng_PKA_CREG(nregType, 11, dataSize, 1); - Sec_Eng_PKA_GF2Mont(nregType, 4, nregType, 4, size, lregType, 5, nregType, 0); -#ifdef DSA_DBG - Sec_Eng_PKA_Read_Data(nregType, 4, (uint32_t *)pka_tmp, dataSize); - MSG("GF2Mont Result of a:\r\n"); - bflb_platform_dump(pka_tmp, dataSize /*dataSize*4*/); -#endif - - Sec_Eng_PKA_Write_Data(nregType, 5, (uint32_t *)b, dataSize, 0); - /* a^b%c*/ - Sec_Eng_PKA_MEXP(nregType, 6, nregType, 4, nregType, 5, nregType, 0, 1); - - /* change result into gf domain*/ - Sec_Eng_PKA_CREG(nregType, 10, dataSize, 1); - Sec_Eng_PKA_CREG(nregType, 11, dataSize, 1); - /*index 2 is invertR*/ - Sec_Eng_PKA_Mont2GF(nregType, 7, nregType, 6, nregType, 2, lregType, 5, nregType, 0); - Sec_Eng_PKA_Read_Data(nregType, 7, (uint32_t *)r, dataSize); -#ifdef DSA_DBG - MSG("r:\r\n"); - bflb_platform_dump(r, dataSize /*dataSize*4*/); -#endif - return 0; -} - -/** - * dP=d%(p-1) - * dQ=d%(q-1) - * qInv=qp^(1-1):qInv*q%p=1 - * invR_p*r%p=1(r is 1024/2048/256) - * invR_q*r%q=1(r is 1024/2048/256) - */ -int sec_dsa_decrypt_crt(uint32_t size, uint32_t *c, sec_dsa_crt_cfg_t *crtCfg, uint32_t *d, uint32_t *r) -{ - /* - * m1 = pow(c, dP, p) - * m2 = pow(c, dQ, q) - * h = (qInv * (m1 - m2)) % p - * m = m2 + h * q - * */ - SEC_ENG_PKA_REG_SIZE_Type nregType = sec_dsa_get_reg_size(size); - SEC_ENG_PKA_REG_SIZE_Type lregType = sec_dsa_get_reg_size(size * 2); - uint32_t dataSize = (size >> 3) >> 2; -#if 0 - uint8_t m1[64] = {0x11, 0xdd, 0x19, 0x7e, 0x69, 0x1a, 0x40, 0x0a, 0x28, 0xfc, 0x3b, 0x31, 0x47, 0xa2, 0x6c, 0x14, - 0x4e, 0xf6, 0xb0, 0xe6, 0xcd, 0x89, 0x0b, 0x4f, 0x02, 0xe4, 0x86, 0xe2, 0xe5, 0xbe, 0xe1, 0xaf, - 0x91, 0xd1, 0x7b, 0x59, 0x8d, 0xdc, 0xb3, 0x57, 0x18, 0xcb, 0x80, 0x05, 0x1c, 0xb5, 0xa4, 0x07, - 0xde, 0x31, 0x94, 0xa4, 0x2f, 0x45, 0xc7, 0x95, 0x75, 0x0f, 0x91, 0xf0, 0x37, 0x91, 0x85, 0xa5 - }; - uint8_t m2[64] = {0x63, 0x89, 0xa3, 0xbb, 0x64, 0x63, 0x87, 0x4f, 0x38, 0xbd, 0x9e, 0x0e, 0x93, 0x29, 0x58, 0xee, - 0xf8, 0xe2, 0x20, 0x2d, 0xe5, 0x38, 0x0a, 0x7f, 0x18, 0x38, 0x2f, 0xa3, 0xf5, 0x48, 0xf8, 0xfd, - 0xe5, 0x78, 0x4a, 0x10, 0x62, 0x01, 0x09, 0x29, 0xe3, 0xe3, 0x9f, 0xad, 0x9b, 0xbe, 0x20, 0xd2, - 0x68, 0x90, 0x57, 0x97, 0xfc, 0x78, 0xd5, 0xdb, 0x07, 0x5b, 0xfe, 0x21, 0x0a, 0x2d, 0x7f, 0xc1 - }; -#else - uint32_t m1[32]; - uint32_t m2[32]; -#endif - /* - * 4:m1 - * 5:m2 - * 6:qInv - * 7:p - * 8:q - * 9:h - * 10&11:qInv*(m1-m2) - */ - sec_dsa_mexp_mont(size, c, crtCfg->dP, crtCfg->p, crtCfg->invR_p, crtCfg->primeN_p, m1); - sec_dsa_mexp_mont(size, c, crtCfg->dQ, crtCfg->q, crtCfg->invR_q, crtCfg->primeN_q, m2); - - Sec_Eng_PKA_Write_Data(nregType, 4, (uint32_t *)m1, dataSize, 0); - Sec_Eng_PKA_Write_Data(nregType, 5, (uint32_t *)m2, dataSize, 0); - Sec_Eng_PKA_Write_Data(nregType, 6, (uint32_t *)crtCfg->qInv, dataSize, 0); - Sec_Eng_PKA_Write_Data(nregType, 7, (uint32_t *)crtCfg->p, dataSize, 0); - Sec_Eng_PKA_Write_Data(nregType, 8, (uint32_t *)crtCfg->q, dataSize, 0); - - /*(m1 - m2)%p*/ - Sec_Eng_PKA_MSUB(nregType, 4, nregType, 4, nregType, 5, nregType, 7, 1); -#ifdef DSA_DBG - Sec_Eng_PKA_Read_Data(nregType, 4, (uint32_t *)pka_tmp, dataSize); - MSG("m1 - m2:\r\n"); - bflb_platform_dump(pka_tmp, dataSize /*dataSize*4*/); -#endif - /* (qInv * (m1 - m2)) % p*/ - Sec_Eng_PKA_CREG(nregType, 10, dataSize, 1); - Sec_Eng_PKA_CREG(nregType, 11, dataSize, 1); - Sec_Eng_PKA_LMUL(lregType, 5, nregType, 6, nregType, 4, 1); -#ifdef DSA_DBG - Sec_Eng_PKA_Read_Data(lregType, 5, (uint32_t *)pka_tmp, dataSize * 2); - MSG("qInv * (m1 - m2):\r\n"); - bflb_platform_dump(pka_tmp, dataSize /*dataSize*4*2*/); -#endif - Sec_Eng_PKA_MREM(nregType, 9, lregType, 5, nregType, 7, 1); -#ifdef DSA_DBG - Sec_Eng_PKA_Read_Data(nregType, 9, (uint32_t *)pka_tmp, dataSize); - MSG("h:\r\n"); - bflb_platform_dump(pka_tmp, dataSize * 4); -#endif - - /* h*q */ - Sec_Eng_PKA_CREG(nregType, 10, dataSize, 1); - Sec_Eng_PKA_CREG(nregType, 11, dataSize, 1); - Sec_Eng_PKA_LMUL(lregType, 5, nregType, 9, nregType, 8, 1); -#ifdef DSA_DBG - Sec_Eng_PKA_Read_Data(lregType, 5, (uint32_t *)pka_tmp, dataSize * 2); - MSG("h*q:\r\n"); - bflb_platform_dump(pka_tmp, dataSize /*dataSize*4*2*/); -#endif - /* m2 + h*q*/ - Sec_Eng_PKA_LADD(lregType, 5, lregType, 5, nregType, 5, 1); - - Sec_Eng_PKA_Read_Data(lregType, 5, (uint32_t *)r, dataSize * 2); -#ifdef DSA_DBG - MSG("r:\r\n"); - bflb_platform_dump(r, dataSize * 4 * 2); -#endif - return 0; -} - -int sec_dsa_init(sec_dsa_handle_t *handle, uint32_t size) -{ - Sec_Eng_PKA_Reset(); - Sec_Eng_PKA_BigEndian_Enable(); - - memset(handle, 0, sizeof(sec_dsa_handle_t)); - handle->size = size; - handle->crtSize = (size >> 1); - - return 0; -} - -int sec_dsa_sign(sec_dsa_handle_t *handle, const uint32_t *hash, uint32_t hashLenInWord, uint32_t *s) -{ - uint32_t dsa_tmp[64] = { 0 }; - - Sec_Eng_PKA_Reset(); - Sec_Eng_PKA_BigEndian_Enable(); - - memcpy(dsa_tmp + ((handle->crtSize >> 3) >> 2) - hashLenInWord, hash, hashLenInWord * 4); - - if (0 == sec_dsa_decrypt_crt(handle->crtSize, dsa_tmp, &handle->crtCfg, handle->d, s)) { - return 0; - } else { - return -1; - } -} - -/** - */ -int sec_dsa_verify(sec_dsa_handle_t *handle, const uint32_t *hash, uint32_t hashLenInWord, const uint32_t *s) -{ - uint32_t dsa_tmp[64]; - uint8_t i = 0; - uint8_t resultOffset = 0; - - Sec_Eng_PKA_Reset(); - Sec_Eng_PKA_BigEndian_Enable(); - - if (0 == sec_dsa_mexp_binary(handle->size, s, handle->e, handle->n, dsa_tmp)) { - resultOffset = (handle->size >> 5) - hashLenInWord; - - for (i = 0; i < hashLenInWord; i++) { - if (dsa_tmp[resultOffset + i] != hash[i]) { - return -1; - } - } - - return 0; - } else { - return -1; - } -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_sec_ecdsa.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_sec_ecdsa.c deleted file mode 100644 index 0a1592e2a5..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_sec_ecdsa.c +++ /dev/null @@ -1,1458 +0,0 @@ -#include "hal_sec_ecdsa.h" -#include "bl808_sec_eng.h" - -#define ECP_SECP256R1_REG_TYPE SEC_ENG_PKA_REG_SIZE_32 -#define ECP_SECP256R1_N_REG_INDEX 0 -#define ECP_SECP256R1_NPRIME_N_REG_INDEX 1 -#define ECP_SECP256R1_INVR_N_REG_INDEX 2 -#define ECP_SECP256R1_NPRIME_P_REG_INDEX 3 -#define ECP_SECP256R1_INVR_P_REG_INDEX 4 -#define ECP_SECP256R1_SIZE 32 -/* Used in verify */ -#define ECP_SECP256R1_S_REG_INDEX 5 -#define ECP_SECP256R1_BAR_S_REG_INDEX 6 -#define ECP_SECP256R1_HASH_REG_INDEX 6 //use ECP_SECP256R1_BAR_S_REG_INDEX since it's temp -#define ECP_SECP256R1_U1_REG_INDEX 7 -#define ECP_SECP256R1_LT_REG_TYPE SEC_ENG_PKA_REG_SIZE_64 -#define ECP_SECP256R1_LT_REG_INDEX 7 -#define ECP_SECP256R1_SLT_REG_TYPE SEC_ENG_PKA_REG_SIZE_128 -#define ECP_SECP256R1_SLT_REG_INDEX 3 - -//#define ECDSA_DBG 1 -//#define ECDSA_DBG_DETAIL 1 - -#define secp256r1 -#define secp256k1 -#define SEC_ECC_POINT_MUL_PARAM_CFG(G) sec_ecc_point_mul_cfg( \ - (uint32_t *)G##P, \ - (uint32_t *)G##PrimeN_P, \ - (uint32_t *)G##_1, \ - (uint32_t *)G##_BAR2, \ - (uint32_t *)G##_BAR3, \ - (uint32_t *)G##_BAR4, \ - (uint32_t *)G##_BAR8, \ - (uint32_t *)G##_1P1, \ - (uint32_t *)G##_1M1) - -#define SEC_ECC_BASIC_PARAM_CFG(G) sec_ecc_basic_parameter_cfg( \ - (uint32_t *)G##N, \ - (uint32_t *)G##PrimeN_N, \ - (uint32_t *)G##InvR_N) - -void bflb_platform_dump(uint8_t *data, uint32_t len); - -#if (defined(ECDSA_DBG) || defined(ECDSA_DBG_DETAIL)) -uint32_t pka_tmp[32] = { 0 }; -#endif -/********************************************** secp256r1 *******************************************/ -const uint8_t secp256r1P[32] ALIGN4 = { - 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff -}; -const uint8_t secp256r1B[32] ALIGN4 = { - 0x5a, 0xc6, 0x35, 0xd8, 0xaa, 0x3a, 0x93, 0xe7, 0xb3, 0xeb, 0xbd, 0x55, 0x76, 0x98, 0x86, 0xbc, - 0x65, 0x1d, 0x06, 0xb0, 0xcc, 0x53, 0xb0, 0xf6, 0x3b, 0xce, 0x3c, 0x3e, 0x27, 0xd2, 0x60, 0x4b -}; -const uint8_t secp256r1Gx[32] ALIGN4 = { - 0x6b, 0x17, 0xd1, 0xf2, 0xe1, 0x2c, 0x42, 0x47, 0xf8, 0xbc, 0xe6, 0xe5, 0x63, 0xa4, 0x40, 0xf2, - 0x77, 0x03, 0x7d, 0x81, 0x2d, 0xeb, 0x33, 0xa0, 0xf4, 0xa1, 0x39, 0x45, 0xd8, 0x98, 0xc2, 0x96 -}; -const uint8_t secp256r1Gy[32] ALIGN4 = { - 0x4f, 0xe3, 0x42, 0xe2, 0xfe, 0x1a, 0x7f, 0x9b, 0x8e, 0xe7, 0xeb, 0x4a, 0x7c, 0x0f, 0x9e, 0x16, - 0x2b, 0xce, 0x33, 0x57, 0x6b, 0x31, 0x5e, 0xce, 0xcb, 0xb6, 0x40, 0x68, 0x37, 0xbf, 0x51, 0xf5 -}; -const uint8_t secp256r1N[32] ALIGN4 = { - 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xbc, 0xe6, 0xfa, 0xad, 0xa7, 0x17, 0x9e, 0x84, 0xf3, 0xb9, 0xca, 0xc2, 0xfc, 0x63, 0x25, 0x51 -}; -const uint8_t secp256r1PrimeN_N[32] ALIGN4 = { - 0x60, 0xd0, 0x66, 0x33, 0xa9, 0xd6, 0x28, 0x1c, 0x50, 0xfe, 0x77, 0xec, 0xc5, 0x88, 0xc6, 0xf6, - 0x48, 0xc9, 0x44, 0x08, 0x7d, 0x74, 0xd2, 0xe4, 0xcc, 0xd1, 0xc8, 0xaa, 0xee, 0x00, 0xbc, 0x4f -}; -const uint8_t secp256r1InvR_N[32] ALIGN4 = { - 0x60, 0xd0, 0x66, 0x33, 0x49, 0x05, 0xc1, 0xe9, 0x07, 0xf8, 0xb6, 0x04, 0x1e, 0x60, 0x77, 0x25, - 0xba, 0xde, 0xf3, 0xe2, 0x43, 0x56, 0x6f, 0xaf, 0xce, 0x1b, 0xc8, 0xf7, 0x9c, 0x19, 0x7c, 0x79 -}; -const uint8_t secp256r1PrimeN_P[32] ALIGN4 = { - 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 -}; -const uint8_t secp256r1InvR_P[32] ALIGN4 = { - 0xff, 0xff, 0xff, 0xfe, 0x00, 0x00, 0x00, 0x03, 0xff, 0xff, 0xff, 0xfd, 0x00, 0x00, 0x00, 0x02, - 0x00, 0x00, 0x00, 0x01, 0xff, 0xff, 0xff, 0xfe, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00 -}; -const uint8_t secp256r1_1[32] ALIGN4 = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 -}; -const uint8_t secp256r1_BAR2[32] ALIGN4 = { - 0x00, 0x00, 0x00, 0x01, 0xff, 0xff, 0xff, 0xfd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02 -}; -const uint8_t secp256r1_BAR3[32] ALIGN4 = { - 0x00, 0x00, 0x00, 0x02, 0xff, 0xff, 0xff, 0xfc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xfd, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03 -}; -const uint8_t secp256r1_BAR4[32] ALIGN4 = { - 0x00, 0x00, 0x00, 0x03, 0xff, 0xff, 0xff, 0xfb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04 -}; -const uint8_t secp256r1_BAR8[32] ALIGN4 = { - 0x00, 0x00, 0x00, 0x07, 0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08 -}; -const uint8_t secp256r1_1P1[32] ALIGN4 = { - 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02 -}; -const uint8_t secp256r1_1M1[32] ALIGN4 = { - 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -}; -const uint8_t secp256r1_Zerox[32] ALIGN4 = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -}; -const uint8_t secp256r1_Zeroy[32] ALIGN4 = { - 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 -}; -const uint8_t secp256r1_Gx[32] ALIGN4 = { - 0x18, 0x90, 0x5f, 0x76, 0xa5, 0x37, 0x55, 0xc6, 0x79, 0xfb, 0x73, 0x2b, 0x77, 0x62, 0x25, 0x10, - 0x75, 0xba, 0x95, 0xfc, 0x5f, 0xed, 0xb6, 0x01, 0x79, 0xe7, 0x30, 0xd4, 0x18, 0xa9, 0x14, 0x3c -}; -const uint8_t secp256r1_Gy[32] ALIGN4 = { - 0x85, 0x71, 0xff, 0x18, 0x25, 0x88, 0x5d, 0x85, 0xd2, 0xe8, 0x86, 0x88, 0xdd, 0x21, 0xf3, 0x25, - 0x8b, 0x4a, 0xb8, 0xe4, 0xba, 0x19, 0xe4, 0x5c, 0xdd, 0xf2, 0x53, 0x57, 0xce, 0x95, 0x56, 0x0a -}; - -/********************************************** secp256k1 *******************************************/ -const uint8_t secp256k1P[32] ALIGN4 = { - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFC, 0x2F -}; -const uint8_t secp256k1B[32] ALIGN4 = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07 -}; -const uint8_t secp256k1Gx[32] ALIGN4 = { - 0x79, 0xBE, 0x66, 0x7E, 0xF9, 0xDC, 0xBB, 0xAC, 0x55, 0xA0, 0x62, 0x95, 0xCE, 0x87, 0x0B, 0x07, - 0x02, 0x9B, 0xFC, 0xDB, 0x2D, 0xCE, 0x28, 0xD9, 0x59, 0xF2, 0x81, 0x5B, 0x16, 0xF8, 0x17, 0x98 -}; -const uint8_t secp256k1Gy[32] ALIGN4 = { - 0x4f, 0xe3, 0x42, 0xe2, 0xfe, 0x1a, 0x7f, 0x9b, 0x8e, 0xe7, 0xeb, 0x4a, 0x7c, 0x0f, 0x9e, 0x16, - 0x2b, 0xce, 0x33, 0x57, 0x6b, 0x31, 0x5e, 0xce, 0xcb, 0xb6, 0x40, 0x68, 0x37, 0xbf, 0x51, 0xf5 -}; -const uint8_t secp256k1N[32] ALIGN4 = { - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, - 0xBA, 0xAE, 0xDC, 0xE6, 0xAF, 0x48, 0xA0, 0x3B, 0xBF, 0xD2, 0x5E, 0x8C, 0xD0, 0x36, 0x41, 0x41 -}; -const uint8_t secp256k1PrimeN_N[32] ALIGN4 = { - 0xd9, 0xe8, 0x89, 0xd, 0x64, 0x94, 0xef, 0x93, 0x89, 0x7f, 0x30, 0xc1, 0x27, 0xcf, 0xab, 0x5e, - 0x50, 0xa5, 0x1a, 0xc8, 0x34, 0xb9, 0xec, 0x24, 0x4b, 0xd, 0xff, 0x66, 0x55, 0x88, 0xb1, 0x3f -}; -const uint8_t secp256k1InvR_N[32] ALIGN4 = { - 0xd9, 0xe8, 0x89, 0xd, 0x64, 0x94, 0xef, 0x93, 0x89, 0x7f, 0x30, 0xc1, 0x27, 0xcf, 0xab, 0x5d, - 0x3b, 0xbb, 0xd4, 0x56, 0x7f, 0xa5, 0xc, 0x3c, 0x80, 0xfd, 0x22, 0x93, 0x80, 0x97, 0xc0, 0x16 -}; -const uint8_t secp256k1PrimeN_P[32] ALIGN4 = { - 0xc9, 0xbd, 0x19, 0x5, 0x15, 0x53, 0x83, 0x99, 0x9c, 0x46, 0xc2, 0xc2, 0x95, 0xf2, 0xb7, 0x61, - 0xbc, 0xb2, 0x23, 0xfe, 0xdc, 0x24, 0xa0, 0x59, 0xd8, 0x38, 0x9, 0x1d, 0xd2, 0x25, 0x35, 0x31 -}; -const uint8_t secp256k1InvR_P[32] ALIGN4 = { - 0xc9, 0xbd, 0x19, 0x5, 0x15, 0x53, 0x83, 0x99, 0x9c, 0x46, 0xc2, 0xc2, 0x95, 0xf2, 0xb7, 0x61, - 0xbc, 0xb2, 0x23, 0xfe, 0xdc, 0x24, 0xa0, 0x59, 0xd8, 0x38, 0x9, 0x1d, 0x8, 0x68, 0x19, 0x2a -}; -const uint8_t secp256k1_1[32] ALIGN4 = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 -}; -const uint8_t secp256k1_BAR2[32] ALIGN4 = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x07, 0xa2 -}; -const uint8_t secp256k1_BAR3[32] ALIGN4 = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x0b, 0x73 -}; -const uint8_t secp256k1_BAR4[32] ALIGN4 = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x0f, 0x44 -}; -const uint8_t secp256k1_BAR8[32] ALIGN4 = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x1e, 0x88 -}; -const uint8_t secp256k1_1P1[32] ALIGN4 = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x03, 0xd2 -}; -const uint8_t secp256k1_1M1[32] ALIGN4 = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x03, 0xd0 -}; -const uint8_t secp256k1_Zerox[32] ALIGN4 = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -}; -const uint8_t secp256k1_Zeroy[32] ALIGN4 = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x03, 0xd1 -}; -const uint8_t secp256k1_Gx[32] ALIGN4 = { - 0x99, 0x81, 0xe6, 0x43, 0xe9, 0x08, 0x9f, 0x48, 0x97, 0x9f, 0x48, 0xc0, 0x33, 0xfd, 0x12, 0x9c, - 0x23, 0x1e, 0x29, 0x53, 0x29, 0xbc, 0x66, 0xdb, 0xd7, 0x36, 0x2e, 0x5a, 0x48, 0x7e, 0x20, 0x97 -}; -const uint8_t secp256k1_Gy[32] ALIGN4 = { - 0xcf, 0x3f, 0x85, 0x1f, 0xd4, 0xa5, 0x82, 0xd6, 0x70, 0xb6, 0xb5, 0x9a, 0xac, 0x19, 0xc1, 0x36, - 0x8d, 0xfc, 0x5d, 0x5d, 0x1f, 0x1d, 0xc6, 0x4d, 0xb1, 0x5e, 0xa6, 0xd2, 0xd3, 0xdb, 0xab, 0xe2 -}; - -static BL_Err_Type sec_ecc_basic_parameter_cfg(uint32_t *n, uint32_t *prime_n, uint32_t *invr_n) -{ - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, (uint32_t *)n, ECP_SECP256R1_SIZE / 4, 0); - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_NPRIME_N_REG_INDEX, (uint32_t *)prime_n, ECP_SECP256R1_SIZE / 4, 0); - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_INVR_N_REG_INDEX, (uint32_t *)invr_n, ECP_SECP256R1_SIZE / 4, 0); - return SUCCESS; -} -static BL_Err_Type sec_ecc_basic_parameter_init(uint8_t id) -{ - if (id >= ECP_TYPE_MAX) { - return ERROR; - } - - if (id == ECP_SECP256R1) { - SEC_ECC_BASIC_PARAM_CFG(secp256r1); - } else if (id == ECP_SECP256K1) { - SEC_ECC_BASIC_PARAM_CFG(secp256k1); - } - - return SUCCESS; -} - -static BL_Err_Type sec_ecc_point_mul_cfg(uint32_t *p, uint32_t *primeN_p, uint32_t *ori_1, uint32_t *bar2, - uint32_t *bar3, uint32_t *bar4, uint32_t *bar8, uint32_t *bar1p1, uint32_t *bar1m1) -{ - Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 0, (uint32_t *)p, ECP_SECP256R1_SIZE / 4, 0); - Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 1, (uint32_t *)primeN_p, ECP_SECP256R1_SIZE / 4, 0); - Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 8, (uint32_t *)ori_1, ECP_SECP256R1_SIZE / 4, 0); - Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 9, (uint32_t *)bar2, ECP_SECP256R1_SIZE / 4, 0); - Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 10, (uint32_t *)bar3, ECP_SECP256R1_SIZE / 4, 0); - Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 11, (uint32_t *)bar4, ECP_SECP256R1_SIZE / 4, 0); - Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 12, (uint32_t *)bar8, ECP_SECP256R1_SIZE / 4, 0); - Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 19, (uint32_t *)bar1p1, ECP_SECP256R1_SIZE / 4, 0); - Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 20, (uint32_t *)bar1m1, ECP_SECP256R1_SIZE / 4, 0); - - return SUCCESS; -} - -static int sec_ecc_point_mul_init(uint8_t id) -{ - if (id >= ECP_TYPE_MAX) { - return ERROR; - } - - if (id == ECP_SECP256R1) { - SEC_ECC_POINT_MUL_PARAM_CFG(secp256r1); - } else if (id == ECP_SECP256K1) { - SEC_ECC_POINT_MUL_PARAM_CFG(secp256k1); - } - - return SUCCESS; -} - -static void sec_ecdsa_point_add_inf_check(uint8_t *pka_p1_eq_inf, uint8_t *pka_p2_eq_inf) -{ - uint8_t res[4]; - - /* index 2:BAR_Zero_x - * index 3:BAR_Zero_y - * index 4:BAR_Zero_z - * index 5:BAR_G_x - * index 6:BAR_G_y - * index 7:BAR_G_z - * index 8:1 - * index 9:2 - * index 10:3 - * index 11:4 - * index 12:8 - * index 19:1P1 - * index 20:1m1*/ - - //cout = 1 if X1 = 0 - Sec_Eng_PKA_LCMP(res, 3, 2, 3, 8); //s0 < s1 => cout = 1 - //cout = 1 if Y1 < Bar_1p1 - Sec_Eng_PKA_LCMP(res + 1, 3, 3, 3, 19); - //cout=1 if Y1 > Bar_1m1 - Sec_Eng_PKA_LCMP(res + 2, 3, 20, 3, 3); - //cout =1 if Z1 = 0 - Sec_Eng_PKA_LCMP(res + 3, 3, 4, 3, 8); - *pka_p1_eq_inf = res[0] & res[1] & res[2] & res[3]; - - //cout = 1 if X2 = 0 - Sec_Eng_PKA_LCMP(res, 3, 5, 3, 8); - // cout = 1 if Y2 < Bar_1p1 - Sec_Eng_PKA_LCMP(res + 1, 3, 6, 3, 19); - //cout = 1 if Y2 > Bar_1m1 - Sec_Eng_PKA_LCMP(res + 2, 3, 20, 3, 6); - //cout = 1 if Z2 = 0 - Sec_Eng_PKA_LCMP(res + 3, 3, 7, 3, 8); - *pka_p2_eq_inf = res[0] & res[1] & res[2] & res[3]; -} - -static void sec_ecdsa_copy_x2_to_x1(uint8_t id) -{ - //X2->X1 - Sec_Eng_PKA_Move_Data(3, 2, 3, 5, 0); - //Y2->Y1 - Sec_Eng_PKA_Move_Data(3, 3, 3, 6, 0); - //Z2->Z1 - Sec_Eng_PKA_Move_Data(3, 4, 3, 7, 1); //Caution!!! wait movdat ready to execute next command -} - -static void sec_ecdsa_point_add(uint8_t id) -{ - /* index 2:BAR_Zero_x - * index 3:BAR_Zero_y - * index 4:BAR_Zero_z - * index 5:BAR_G_x - * index 6:BAR_G_y - * index 7:BAR_G_z - * index 8:1 - * index 9:2 - * index 10:3 - * index 11:4 - * index 12:8 - * index 19:1P1 - * index 20:1m1*/ - - //U1 = Y2*Z1 - //PKA_MMUL(0,3,13,3, 6,3, 4,3,0);//d_reg_type,d_reg_idx,s0_reg_type,s0_reg_idx,s1_reg_type,s1_reg_idx,s2_reg_type,s2_reg_idx - Sec_Eng_PKA_MMUL(3, 13, 3, 6, 3, 4, 3, 0, 0); - - //U2 = Y1*Z2 - //PKA_MMUL(0,3,14,3, 3,3, 7,3,0); - Sec_Eng_PKA_MMUL(3, 14, 3, 3, 3, 7, 3, 0, 0); - - //V1 = X2*Z1 - //PKA_MMUL(0,3,15,3, 5,3, 4,3,0); - Sec_Eng_PKA_MMUL(3, 15, 3, 5, 3, 4, 3, 0, 0); - - //V2 = X1*Z2 - //PKA_MMUL(0,3,16,3, 2,3, 7,3,0); - Sec_Eng_PKA_MMUL(3, 16, 3, 2, 3, 7, 3, 0, 0); - - //U = U1-U2 - //PKA_MSUB(0,3,13,3,13,3,14,3,0); - Sec_Eng_PKA_MSUB(3, 13, 3, 13, 3, 14, 3, 0, 0); - - //V = V1-V2 - //PKA_MSUB(0,3,15,3,15,3,16,3,0); - Sec_Eng_PKA_MSUB(3, 15, 3, 15, 3, 16, 3, 0, 0); - - //W = Z1*Z2 - //PKA_MMUL(0,3, 2,3, 4,3, 7,3,0); - Sec_Eng_PKA_MMUL(3, 2, 3, 4, 3, 7, 3, 0, 0); - - //V^2 - //PKA_MMUL(0,3, 3,3,15,3,15,3,0); - Sec_Eng_PKA_MMUL(3, 3, 3, 15, 3, 15, 3, 0, 0); - - //V^3 - //PKA_MMUL(0,3, 4,3, 3,3,15,3,0); - Sec_Eng_PKA_MMUL(3, 4, 3, 3, 3, 15, 3, 0, 0); - - //U^2 - //PKA_MMUL(0,3,17,3,13,3,13,3,0); - Sec_Eng_PKA_MMUL(3, 17, 3, 13, 3, 13, 3, 0, 0); - - //U^2*W - //PKA_MMUL(0,3,17,3,17,3, 2,3,0); - Sec_Eng_PKA_MMUL(3, 17, 3, 17, 3, 2, 3, 0, 0); - - //U^2*W-V^3 - //PKA_MSUB(0,3,17,3,17,3, 4,3,0); - Sec_Eng_PKA_MSUB(3, 17, 3, 17, 3, 4, 3, 0, 0); - - //2*V^2 - //PKA_MMUL(0,3,18,3, 9,3, 3,3,0); - Sec_Eng_PKA_MMUL(3, 18, 3, 9, 3, 3, 3, 0, 0); - - //2*V^2*V2 - //PKA_MMUL(0,3,18,3,18,3,16,3,0); - Sec_Eng_PKA_MMUL(3, 18, 3, 18, 3, 16, 3, 0, 0); - - //A = U^2*W-V^3-2*V^2*V2 - //PKA_MSUB(0,3,18,3,17,3,18,3,0); - Sec_Eng_PKA_MSUB(3, 18, 3, 17, 3, 18, 3, 0, 0); - - //V^2*V2 - //PKA_MMUL(0,3, 3,3, 3,3,16,3,0); - Sec_Eng_PKA_MMUL(3, 3, 3, 3, 3, 16, 3, 0, 0); - - //V^3*U2 - //PKA_MMUL(0,3,14,3, 4,3,14,3,0); - Sec_Eng_PKA_MMUL(3, 14, 3, 4, 3, 14, 3, 0, 0); - - //Z3 = V^3*W - //PKA_MMUL(0,3, 4,3, 4,3, 2,3,0); - Sec_Eng_PKA_MMUL(3, 4, 3, 4, 3, 2, 3, 0, 0); - - //X3 = V*A - //PKA_MMUL(0,3, 2,3,15,3,18,3,0); - Sec_Eng_PKA_MMUL(3, 2, 3, 15, 3, 18, 3, 0, 0); - - //V^2*V2-A - //PKA_MSUB(0,3, 3,3, 3,3,18,3,0); - Sec_Eng_PKA_MSUB(3, 3, 3, 3, 3, 18, 3, 0, 0); - - //U*(V^2*V2-A) - //PKA_MMUL(0,3, 3,3,13,3, 3,3,0); - Sec_Eng_PKA_MMUL(3, 3, 3, 13, 3, 3, 3, 0, 0); - - //Y3 = U*(V^2*V2-A)-V^3*U2 - //PKA_MSUB(1,3, 3,3, 3,3,14,3,0); - Sec_Eng_PKA_MSUB(3, 3, 3, 3, 3, 14, 3, 0, 1); -} -/** - * @brief calculate secp256r1's W - * - * @note index 13:W = 3X^2-3Z^2 - */ -static void sec_ecdsa_cal_secp256r1_w(void) -{ - //X1^2 - //PKA_MMUL(0,3,13,3, 5,3, 5,3,0);//d_reg_type,d_reg_idx,s0_reg_type,s0_reg_idx,s1_reg_type,s1_reg_idx,s2_reg_type,s2_reg_idx - Sec_Eng_PKA_MMUL(3, 13, 3, 5, 3, 5, 3, 0, 0); - - //Z1^2 - //PKA_MMUL(0,3,14,3, 7,3, 7,3,0); - Sec_Eng_PKA_MMUL(3, 14, 3, 7, 3, 7, 3, 0, 0); - - //X1^2-Z1^2 - //PKA_MSUB(0,3,13,3,13,3,14,3,0); - Sec_Eng_PKA_MSUB(3, 13, 3, 13, 3, 14, 3, 0, 0); - - //W = 3*(X1^2-Z1^2) - //PKA_MMUL(0,3,13,3,10,3,13,3,0); - Sec_Eng_PKA_MMUL(3, 13, 3, 10, 3, 13, 3, 0, 0); -} - -/** - * @brief calculate secp256k1's W - * - * @note index 13:W = 3X^2 - */ -static void sec_ecdsa_cal_secp256k1_w(void) -{ - //X1^2 - Sec_Eng_PKA_MMUL(3, 13, 3, 5, 3, 5, 3, 0, 0); - - //W = 3* (X1^2) - Sec_Eng_PKA_MMUL(3, 13, 3, 10, 3, 13, 3, 0, 0); -} - -static BL_Err_Type sec_ecdsa_point_double(sec_ecp_type id) -{ - /* index 2:BAR_Zero_x - * index 3:BAR_Zero_y - * index 4:BAR_Zero_z - * index 5:BAR_G_x - * index 6:BAR_G_y - * index 7:BAR_G_z - * index 8:1 - * index 9:2 - * index 10:3 - * index 11:4 - * index 12:8 - * index 19:1P1 - * index 20:1m1*/ - - if (id >= ECP_TYPE_MAX) { - return ERROR; - } - - if (id == ECP_SECP256R1) { - sec_ecdsa_cal_secp256r1_w(); - } else if (id == ECP_SECP256K1) { - sec_ecdsa_cal_secp256k1_w(); - } - - //S = Y1*Z1 - //PKA_MMUL(0,3,14,3, 6,3, 7,3,0); - Sec_Eng_PKA_MMUL(3, 14, 3, 6, 3, 7, 3, 0, 0); - - //X1*Y1 - //PKA_MMUL(0,3,15,3, 5,3, 6,3,0); - Sec_Eng_PKA_MMUL(3, 15, 3, 5, 3, 6, 3, 0, 0); - - //W^2 - //PKA_MMUL(0,3, 7,3,13,3,13,3,0); - Sec_Eng_PKA_MMUL(3, 7, 3, 13, 3, 13, 3, 0, 0); - - //B = X1*Y1*S - //PKA_MMUL(0,3,15,3,15,3,14,3,0); - Sec_Eng_PKA_MMUL(3, 15, 3, 15, 3, 14, 3, 0, 0); - - //8*B - //PKA_MMUL(0,3, 5,3,12,3,15,3,0); - Sec_Eng_PKA_MMUL(3, 5, 3, 12, 3, 15, 3, 0, 0); - - //H = W^2-8*B - //PKA_MSUB(0,3, 7,3, 7,3, 5,3,0); - Sec_Eng_PKA_MSUB(3, 7, 3, 7, 3, 5, 3, 0, 0); - - //2*H - //PKA_MMUL(0,3, 5,3, 9,3, 7,3,0); - Sec_Eng_PKA_MMUL(3, 5, 3, 9, 3, 7, 3, 0, 0); - - //X2 = 2*H*S - //PKA_MMUL(0,3, 5,3, 5,3,14,3,0); - Sec_Eng_PKA_MMUL(3, 5, 3, 5, 3, 14, 3, 0, 0); - - //4*B - //PKA_MMUL(0,3,15,3,11,3,15,3,0); - Sec_Eng_PKA_MMUL(3, 15, 3, 11, 3, 15, 3, 0, 0); - - //S^2 - //PKA_MMUL(0,3,16,3,14,3,14,3,0); - Sec_Eng_PKA_MMUL(3, 16, 3, 14, 3, 14, 3, 0, 0); - - //4*B-H - //PKA_MSUB(0,3,15,3,15,3, 7,3,0); - Sec_Eng_PKA_MSUB(3, 15, 3, 15, 3, 7, 3, 0, 0); - - //Y1^2 - //PKA_MMUL(0,3, 6,3, 6,3, 6,3,0); - Sec_Eng_PKA_MMUL(3, 6, 3, 6, 3, 6, 3, 0, 0); - - //W*(4*B-H) - //PKA_MMUL(0,3,15,3,15,3,13,3,0); - Sec_Eng_PKA_MMUL(3, 15, 3, 15, 3, 13, 3, 0, 0); - - //8*Y1^2 - //PKA_MMUL(0,3, 6,3,12,3, 6,3,0); - Sec_Eng_PKA_MMUL(3, 6, 3, 12, 3, 6, 3, 0, 0); - - //8*Y1^2*S^2 - //PKA_MMUL(0,3, 6,3, 6,3,16,3,0); - Sec_Eng_PKA_MMUL(3, 6, 3, 6, 3, 16, 3, 0, 0); - - //Y2 = W*(4*B-H)-8*Y1^2*S^2 - //PKA_MSUB(0,3, 6,3,15,3, 6,3,0); - Sec_Eng_PKA_MSUB(3, 6, 3, 15, 3, 6, 3, 0, 0); - - //S^3 - //PKA_MMUL(0,3, 7,3,14,3,16,3,0); - Sec_Eng_PKA_MMUL(3, 7, 3, 14, 3, 16, 3, 0, 0); - - //Z2 = 8*S^3 - //PKA_MMUL(1,3, 7,3,12,3, 7,3,0); - Sec_Eng_PKA_MMUL(3, 7, 3, 12, 3, 7, 3, 0, 1); - - return SUCCESS; -} -#ifdef ECDSA_DBG_DETAIL -static void sec_ecdsa_dump_temp_result() -{ - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); - MSG("2=\r\n"); - bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); - MSG("3=\r\n"); - bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 4, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); - MSG("4=\r\n"); - bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); - - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); - MSG("5=\r\n"); - bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); - MSG("6=\r\n"); - bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 7, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); - MSG("7=\r\n"); - bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); -} -#endif -static int sec_ecdsa_verify_point_mul(uint8_t id, const uint32_t *m) -{ - uint32_t i, j, k; - uint32_t tmp; - uint32_t isOne = 0; - uint8_t *p = (uint8_t *)m; - uint8_t pka_p1_eq_inf, pka_p2_eq_inf; - - /* Remove zeros bytes*/ - k = 0; - - while (p[k] == 0 && k < 31) { - k++; - } - - i = 31; - - for (; i >= k; i--) { - tmp = p[i]; - j = 0; - - for (j = 0; j < 8; j++) { - isOne = tmp & (1 << j); - - if (isOne) { - sec_ecdsa_point_add_inf_check(&pka_p1_eq_inf, &pka_p2_eq_inf); - - if (pka_p1_eq_inf == 1 && pka_p2_eq_inf == 0) { - //sum = X2 - sec_ecdsa_copy_x2_to_x1(id); -#ifdef ECDSA_DBG_DETAIL - MSG("sum = X2\r\n"); - sec_ecdsa_dump_temp_result(); -#endif - } else if (pka_p1_eq_inf == 0 && pka_p2_eq_inf == 1) { - //sum = X1 - //MSG("sum = X1\r\n"); - } else if (pka_p1_eq_inf == 0 && pka_p2_eq_inf == 0) { - //sum = X1 + X2 - sec_ecdsa_point_add(id); -#ifdef ECDSA_DBG_DETAIL - MSG("sum = X1+X2\r\n"); - sec_ecdsa_dump_temp_result(); -#endif - } else { - //MSG("Error! infinite point + infinite point\r\n"); - return -1; - } - } - - sec_ecdsa_point_double(id); -#ifdef ECDSA_DBG_DETAIL - sec_ecdsa_dump_temp_result(); -#endif - } - - if (i == 0) { - break; - } - } - - return 0; -} - -/*cal d*G if pkX(pky)==NULL - * cal d(bG) if pkX(pky)!=NULL */ -static int32_t sec_ecdh_get_scalar_point(uint8_t id, const uint32_t *pkX, const uint32_t *pkY, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy) -{ -#ifdef ECDSA_DBG - uint32_t pk_z[8]; -#endif - - if (id >= ECP_TYPE_MAX) { - return ERROR; - } - - /* Pointer check */ - if (private_key == NULL) { - return -1; - } - - Sec_Eng_PKA_Reset(); - Sec_Eng_PKA_BigEndian_Enable(); - - sec_ecc_basic_parameter_init(id); - - //Clear D[7] - //PKA_CREG(1,4, 7,0); - Sec_Eng_PKA_CREG(ECP_SECP256R1_LT_REG_TYPE, 7, ECP_SECP256R1_SIZE / 4, 1); - - sec_ecc_point_mul_init(id); - - if (id == ECP_SECP256R1) { - //X1 - //PKA_CTREG(3, 2,8,bar_Zero_x); - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)secp256r1_Zerox, ECP_SECP256R1_SIZE / 4, 0); - //Y1 - //PKA_CTREG(3, 3,8,bar_Zero_y); - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)secp256r1_Zeroy, ECP_SECP256R1_SIZE / 4, 0); - } else if (id == ECP_SECP256K1) { - //X1 - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)secp256k1_Zerox, ECP_SECP256R1_SIZE / 4, 0); - //Y1 - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)secp256k1_Zeroy, ECP_SECP256R1_SIZE / 4, 0); - } - //Z1 - //PKA_CTREG(3, 4,8,bar_Zero_z); - //PKA_MOVDAT(1,3, 4,3, 2); - Sec_Eng_PKA_Move_Data(3, 4, 3, 2, 1); - - if (pkX == NULL) { - if (id == ECP_SECP256R1) { - //X2 - //PKA_CTREG(3, 5,8,bar_G_x); - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)secp256r1_Gx, ECP_SECP256R1_SIZE / 4, 0); - //Y2 - //PKA_CTREG(3, 6,8,bar_G_y); - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256r1_Gy, ECP_SECP256R1_SIZE / 4, 0); - } else if (id == ECP_SECP256K1) { - //X2 - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)secp256k1_Gx, ECP_SECP256R1_SIZE / 4, 0); - //Y2 - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256k1_Gy, ECP_SECP256R1_SIZE / 4, 0); - } - } else { - /* chaneg peer's public key to mont domain*/ - //PUB_x - //PKA_CTREG(3, 5,8,PUB_x); - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)pkX, ECP_SECP256R1_SIZE / 4, 0); - //bar_pub_x - //PKA_GF2MONT(3, 5,3, 5); - /* Change s to Mont domain,remember to clear temp register and index 0 is P256*/ - /* Clear register for ECP_SECP256R1_LT_REG_INDEX*/ - Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1); - Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1); - Sec_Eng_PKA_GF2Mont(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 5, 256, - ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); -#ifdef ECDSA_DBG - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); - MSG("PK.x in Mont:\r\n"); - bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); -#endif - - //PUB_y - //PKA_CTREG(3, 6,8,PUB_y); - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)pkY, ECP_SECP256R1_SIZE / 4, 0); - //bar_pub_y - //PKA_GF2MONT(3, 6,3, 6); - Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1); - Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1); - Sec_Eng_PKA_GF2Mont(ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_REG_TYPE, 6, 256, - ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); -#ifdef ECDSA_DBG - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); - MSG("PK.y in Mont:\r\n"); - bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); -#endif - } - - //Z2 - //PKA_CTREG(3, 7,8,bar_G_z); - //PKA_MOVDAT(1,3, 7,3, 3); - Sec_Eng_PKA_Move_Data(3, 7, 3, 3, 1); - /* Clear temp register since it's used in point-mul*/ - Sec_Eng_PKA_CREG(ECP_SECP256R1_LT_REG_TYPE, 7, ECP_SECP256R1_SIZE / 4, 1); - - sec_ecdsa_verify_point_mul(id, private_key); - //get bar_u1_x - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)pRx, ECP_SECP256R1_SIZE / 4); -#ifdef ECDSA_DBG - MSG("bar_u1_x\r\n"); - bflb_platform_dump(pRx, ECP_SECP256R1_SIZE); -#endif - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)pRy, ECP_SECP256R1_SIZE / 4); -#ifdef ECDSA_DBG - MSG("bar_u1_y\r\n"); - bflb_platform_dump(pRy, ECP_SECP256R1_SIZE); -#endif -#ifdef ECDSA_DBG - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 4, (uint32_t *)pk_z, ECP_SECP256R1_SIZE / 4); - MSG("bar_u1_z\r\n"); - bflb_platform_dump(pk_z, ECP_SECP256R1_SIZE); -#endif - - //get R.x - //R.z ^ -1 - Sec_Eng_PKA_MINV(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 4, ECP_SECP256R1_REG_TYPE, 0, 1); - if (id == ECP_SECP256R1) { - //inv_r - //PKA_CTREG(3, 6,8,inv_r); - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256r1InvR_P, ECP_SECP256R1_SIZE / 4, 0); - } else if (id == ECP_SECP256K1) { - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256k1InvR_P, ECP_SECP256R1_SIZE / 4, 0); - } - //R.z ^ -1 - Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1); - Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1); - //PKA_MONT2GF(3, 5,3, 5,3, 6); - Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 6, - ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); - - //R.x (Montgomery to GF) - //PKA_MONT2GF(3, 6,3, 2,3, 6); - Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_REG_TYPE, 2, ECP_SECP256R1_REG_TYPE, 6, - ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); - - //R.x (GF to Affine domain) - //PKA_MONT2GF(3, 2,3, 5,3, 6); - Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 2, ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 6, - ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)pRx, ECP_SECP256R1_SIZE / 4); -#ifdef ECDSA_DBG - MSG("R.x=\r\n"); - bflb_platform_dump(pRx, ECP_SECP256R1_SIZE); -#endif - if (id == ECP_SECP256R1) { - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, (uint32_t *)secp256r1N, ECP_SECP256R1_SIZE / 4, 0); - } else if (id == ECP_SECP256K1) { - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, (uint32_t *)secp256k1N, ECP_SECP256R1_SIZE / 4, 0); - } - - Sec_Eng_PKA_MREM(ECP_SECP256R1_REG_TYPE, 2, ECP_SECP256R1_REG_TYPE, 2, - ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, 1); - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)pRx, ECP_SECP256R1_SIZE / 4); -#ifdef ECDSA_DBG - MSG("R.x%n=\r\n"); - bflb_platform_dump(pRx, ECP_SECP256R1_SIZE); -#endif - if (id == ECP_SECP256R1) { - /*after %n,re write p*/ - Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 0, (uint32_t *)secp256r1P, ECP_SECP256R1_SIZE / 4, 0); - } else if (id == ECP_SECP256K1) { - Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 0, (uint32_t *)secp256k1P, ECP_SECP256R1_SIZE / 4, 0); - } - - //get R.y - //R.z ^ -1 - Sec_Eng_PKA_MINV(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 4, ECP_SECP256R1_REG_TYPE, 0, 1); - //inv_r - //PKA_CTREG(3, 6,8,inv_r); - if (id == ECP_SECP256R1) { - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256r1InvR_P, ECP_SECP256R1_SIZE / 4, 0); - } else if (id == ECP_SECP256K1) { - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256k1InvR_P, ECP_SECP256R1_SIZE / 4, 0); - } - //R.z ^ -1 - Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1); - Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1); - //PKA_MONT2GF(3, 5,3, 5,3, 6); - Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 6, - ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); - //R.x (Montgomery to GF) - //PKA_MONT2GF(3, 6,3, 2,3, 6); - Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_REG_TYPE, 3, ECP_SECP256R1_REG_TYPE, 6, - ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); - - //R.x (GF to Affine domain) - //PKA_MONT2GF(3, 2,3, 5,3, 6); - Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 3, ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 6, - ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)pRy, ECP_SECP256R1_SIZE / 4); -#ifdef ECDSA_DBG - MSG("R.y=\r\n"); - bflb_platform_dump(pRy, ECP_SECP256R1_SIZE); -#endif - if (id == ECP_SECP256R1) { - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, (uint32_t *)secp256r1N, ECP_SECP256R1_SIZE / 4, 0); - } else if (id == ECP_SECP256K1) { - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, (uint32_t *)secp256k1N, ECP_SECP256R1_SIZE / 4, 0); - } - Sec_Eng_PKA_MREM(ECP_SECP256R1_REG_TYPE, 3, ECP_SECP256R1_REG_TYPE, 3, - ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, 1); - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)pRy, ECP_SECP256R1_SIZE / 4); -#ifdef ECDSA_DBG - MSG("R.y%n=\r\n"); - bflb_platform_dump(pRy, ECP_SECP256R1_SIZE); -#endif - return 0; -} - -static int32_t sec_ecc_is_zero(uint8_t *a, uint32_t len) -{ - uint32_t i = 0; - - for (i = 0; i < len; i++) { - if (a[i] != 0) { - return 0; - } - } - - return 1; -} - -static int32_t sec_ecc_cmp(uint8_t *a, uint8_t *b, uint32_t len) -{ - uint32_t i = 0, j = 0; - - for (i = 0; i < len; i++) { - if (a[i] != 0) { - break; - } - } - - for (j = 0; j < len; j++) { - if (b[j] != 0) { - break; - } - } - - if (i == len && j == len) { - return (0); - } - - if (i > j) { - return (-1); - } - - if (j > i) { - return (1); - } - - for (; i < len; i++) { - if (a[i] > b[i]) { - return (1); - } - - if (a[i] < b[i]) { - return (-1); - } - } - - return 0; -} - -int sec_ecdsa_init(sec_ecdsa_handle_t *handle, sec_ecp_type id) -{ - Sec_Eng_PKA_Reset(); - Sec_Eng_PKA_BigEndian_Enable(); - Sec_Eng_Trng_Enable(); - - handle->ecpId = id; - - return 0; -} - -int sec_ecdsa_deinit(sec_ecdsa_handle_t *handle) -{ - Sec_Eng_PKA_Reset(); - - return 0; -} - -__WEAK void sec_ecdsa_verify_suss_callback(uint32_t state, uint8_t is_en) -{ - -} - -int sec_ecdsa_verify(sec_ecdsa_handle_t *handle, const uint32_t *hash, uint32_t hashLenInWord, const uint32_t *r, const uint32_t *s) -{ - uint32_t bar_u1_x[8]; - uint32_t bar_u1_y[8]; - uint32_t bar_u1_z[8]; - uint32_t bar_u2_x[8]; - uint32_t bar_u2_y[8]; - uint32_t bar_u2_z[8]; - uint32_t pka_u1[8] = { 0 }; - uint32_t pka_u2[8] = { 0 }; - uint32_t i = 0; - - /* Pointer check */ - if (hash == NULL || handle->publicKeyx == NULL || handle->publicKeyy == NULL || r == NULL || s == NULL) { - return -1; - } - - Sec_Eng_PKA_Reset(); - Sec_Eng_PKA_BigEndian_Enable(); - - /*Step 0: make sure r and s are in range 1..n-1*/ - - /* r and s should not be 0*/ - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, (uint32_t *)r, ECP_SECP256R1_SIZE / 4, 0); - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 8, (uint32_t *)secp256r1_1, ECP_SECP256R1_SIZE / 4, 0); - //cout = 1 if r = 0 - Sec_Eng_PKA_LCMP((uint8_t *)&i, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, 8); //s0 < s1 => cout = 1 - - if (i == 1) { - return -1; - } - - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, (uint32_t *)s, ECP_SECP256R1_SIZE / 4, 0); - //cout = 1 if r = 0 - Sec_Eng_PKA_LCMP((uint8_t *)&i, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, 8); //s0 < s1 => cout = 1 - - if (i == 1) { - return -1; - } - - sec_ecc_basic_parameter_init(handle->ecpId); - - /* r and s should not be 0*/ - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, (uint32_t *)r, ECP_SECP256R1_SIZE / 4, 0); - //cout = 1 if r < N - Sec_Eng_PKA_LCMP((uint8_t *)&i, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX); - - if (i != 1) { - return -1; - } - - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, (uint32_t *)s, ECP_SECP256R1_SIZE / 4, 0); - //cout = 1 if r < N - Sec_Eng_PKA_LCMP((uint8_t *)&i, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX); - - if (i != 1) { - return -1; - } - - /* u1 = e / s mod n, u2 = r / s mod n - * R = u1 G + u2 Q*/ - - /* Step1: Get S^-1*/ - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, (uint32_t *)s, ECP_SECP256R1_SIZE / 4, 0); - /* Change s to Mont domain */ - /* Clear register for ECP_SECP256R1_LT_REG_INDEX*/ - Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1); - Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1); - Sec_Eng_PKA_GF2Mont(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, 256, - ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX); -#ifdef ECDSA_DBG - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); - MSG("GF2Mont Result of s:\r\n"); - bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); -#endif - - /* Get S^-1 in Mont domain */ - Sec_Eng_PKA_MINV(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_BAR_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, - ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, 1); -#ifdef ECDSA_DBG - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_BAR_S_REG_INDEX, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); - MSG("s^-1 in Mont:\r\n"); - bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); -#endif - - /* Change S^-1 into GF domain,now ECP_SECP256R1_S_REG_INDEX store s^-1*/ - /* Clear register for ECP_SECP256R1_LT_REG_INDEX*/ - Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_BAR_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_INVR_N_REG_INDEX, - ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX); -#ifdef ECDSA_DBG - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); - MSG("S^-1:\r\n"); - bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); -#endif - - /* Step2: Get u1*/ - //u1=hash(e)*s^-1; - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_HASH_REG_INDEX, (uint32_t *)hash, ECP_SECP256R1_SIZE / 4, 0); - Sec_Eng_PKA_LMUL(ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_HASH_REG_INDEX, - ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, 0); - Sec_Eng_PKA_MREM(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_U1_REG_INDEX, ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, - ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, 1); - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_U1_REG_INDEX, (uint32_t *)pka_u1, ECP_SECP256R1_SIZE / 4); -#ifdef ECDSA_DBG - MSG("u1:\r\n"); - bflb_platform_dump(pka_u1, ECP_SECP256R1_SIZE); -#endif - - /* Step3: Get u2*/ - //u2=r*s^-1; - // use hash and u1 temp register - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_HASH_REG_INDEX, (uint32_t *)r, ECP_SECP256R1_SIZE / 4, 0); - Sec_Eng_PKA_LMUL(ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_HASH_REG_INDEX, - ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, 0); - Sec_Eng_PKA_MREM(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_U1_REG_INDEX, ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, - ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, 1); - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_U1_REG_INDEX, (uint32_t *)pka_u2, ECP_SECP256R1_SIZE / 4); -#ifdef ECDSA_DBG - MSG("u2:\r\n"); - bflb_platform_dump(pka_u2, ECP_SECP256R1_SIZE); -#endif - - /* Step4: Get u1*G*/ - - //Clear D[7] - //PKA_CREG(1,4, 7,0); - Sec_Eng_PKA_CREG(ECP_SECP256R1_LT_REG_TYPE, 7, ECP_SECP256R1_SIZE / 4, 1); - - sec_ecc_point_mul_init(handle->ecpId); - - //X1 - //PKA_CTREG(3, 2,8,bar_Zero_x); - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)secp256r1_Zerox, ECP_SECP256R1_SIZE / 4, 0); - //Y1 - //PKA_CTREG(3, 3,8,bar_Zero_y); - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)secp256r1_Zeroy, ECP_SECP256R1_SIZE / 4, 0); - //Z1 - //PKA_CTREG(3, 4,8,bar_Zero_z); - //PKA_MOVDAT(1,3, 4,3, 2); - Sec_Eng_PKA_Move_Data(3, 4, 3, 2, 1); - - //X2 - //PKA_CTREG(3, 5,8,bar_G_x); - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)secp256r1_Gx, ECP_SECP256R1_SIZE / 4, 0); - //Y2 - //PKA_CTREG(3, 6,8,bar_G_y); - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256r1_Gy, ECP_SECP256R1_SIZE / 4, 0); - //Z2 - //PKA_CTREG(3, 7,8,bar_G_z); - //PKA_MOVDAT(1,3, 7,3, 3); - Sec_Eng_PKA_Move_Data(3, 7, 3, 3, 1); - - sec_ecdsa_verify_point_mul(handle->ecpId, pka_u1); - //get bar_u1_x - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)bar_u1_x, ECP_SECP256R1_SIZE / 4); -#ifdef ECDSA_DBG - MSG("bar_u1_x\r\n"); - bflb_platform_dump(bar_u1_x, ECP_SECP256R1_SIZE); -#endif - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)bar_u1_y, ECP_SECP256R1_SIZE / 4); -#ifdef ECDSA_DBG - MSG("bar_u1_y\r\n"); - bflb_platform_dump(bar_u1_y, ECP_SECP256R1_SIZE); -#endif - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 4, (uint32_t *)bar_u1_z, ECP_SECP256R1_SIZE / 4); -#ifdef ECDSA_DBG - MSG("bar_u1_z\r\n"); - bflb_platform_dump(bar_u1_z, ECP_SECP256R1_SIZE); -#endif - - /* Step4: Get u2*Q*/ - //X1 - //PKA_CTREG(3, 2,8,bar_Zero_x); - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)secp256r1_Zerox, ECP_SECP256R1_SIZE / 4, 0); - //Y1 - //PKA_CTREG(3, 3,8,bar_Zero_y); - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)secp256r1_Zeroy, ECP_SECP256R1_SIZE / 4, 0); - //Z1 - //PKA_CTREG(3, 4,8,bar_Zero_z); - //PKA_MOVDAT(1,3, 4,3, 2); - Sec_Eng_PKA_Move_Data(3, 4, 3, 2, 1); - - //PUB_x - //PKA_CTREG(3, 5,8,PUB_x); - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)handle->publicKeyx, ECP_SECP256R1_SIZE / 4, 0); - //bar_pub_x - //PKA_GF2MONT(3, 5,3, 5); - /* Change s to Mont domain,remember to clear temp register and index 0 is P256*/ - /* Clear register for ECP_SECP256R1_LT_REG_INDEX*/ - Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1); - Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1); - Sec_Eng_PKA_GF2Mont(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 5, 256, - ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); -#ifdef ECDSA_DBG - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); - MSG("PK.x in Mont:\r\n"); - bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); -#endif - - //PUB_y - //PKA_CTREG(3, 6,8,PUB_y); - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)handle->publicKeyy, ECP_SECP256R1_SIZE / 4, 0); - //bar_pub_y - //PKA_GF2MONT(3, 6,3, 6); - Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1); - Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1); - Sec_Eng_PKA_GF2Mont(ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_REG_TYPE, 6, 256, - ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); -#ifdef ECDSA_DBG - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); - MSG("PK.y in Mont:\r\n"); - bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); -#endif - - //bar_pub_z - //PKA_CTREG(3, 7,8,PUB_z); - //PKA_MOVDAT(1,3, 7,3, 3); - Sec_Eng_PKA_Move_Data(3, 7, 3, 3, 1); - - /* Clear temp register since it's used in point-mul*/ - Sec_Eng_PKA_CREG(ECP_SECP256R1_LT_REG_TYPE, 7, ECP_SECP256R1_SIZE / 4, 1); - - sec_ecdsa_verify_point_mul(handle->ecpId, pka_u2); - //get bar_u1_x - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)bar_u2_x, ECP_SECP256R1_SIZE / 4); -#ifdef ECDSA_DBG - MSG("bar_u2_x\r\n"); - bflb_platform_dump(bar_u2_x, ECP_SECP256R1_SIZE); -#endif - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)bar_u2_y, ECP_SECP256R1_SIZE / 4); -#ifdef ECDSA_DBG - MSG("bar_u2_y\r\n"); - bflb_platform_dump(bar_u2_y, ECP_SECP256R1_SIZE); -#endif - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 4, (uint32_t *)bar_u2_z, ECP_SECP256R1_SIZE / 4); -#ifdef ECDSA_DBG - MSG("bar_u2_z\r\n"); - bflb_platform_dump(bar_u2_z, ECP_SECP256R1_SIZE); -#endif - - /* Step5: Get u1*G+u2*Q*/ - //move bar_u2_x - //PKA_MOVDAT(0,3, 5,3, 2); - Sec_Eng_PKA_Move_Data(3, 5, 3, 2, 0); - //move bar_u2_y - //PKA_MOVDAT(0,3, 6,3, 3); - Sec_Eng_PKA_Move_Data(3, 6, 3, 3, 0); - //move bar_u2_z - //PKA_MOVDAT(1,3, 7,3, 4); - Sec_Eng_PKA_Move_Data(3, 7, 3, 4, 1); - - //bar_u1_x - //PKA_CTREG(3, 2,8,bar_u1_x); - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)bar_u1_x, ECP_SECP256R1_SIZE / 4, 0); - //bar_u1_y - //PKA_CTREG(3, 3,8,bar_u1_y); - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)bar_u1_y, ECP_SECP256R1_SIZE / 4, 0); - //bar_u1_z - //PKA_CTREG(3, 4,8,bar_u1_z); - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 4, (uint32_t *)bar_u1_z, ECP_SECP256R1_SIZE / 4, 0); - - //R = u1 * G + u2 * PUB - //PKA_POINT_ADDITION(); - sec_ecdsa_point_add(handle->ecpId); - - /* Step6 Get R.x(R=u1G+u2P)*/ - //R.z ^ -1 - //PKA_MINV(0,3, 5,3, 4,3, 0); - Sec_Eng_PKA_MINV(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 4, ECP_SECP256R1_REG_TYPE, 0, 1); - //inv_r - //PKA_CTREG(3, 6,8,inv_r); - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256r1InvR_P, ECP_SECP256R1_SIZE / 4, 0); - //R.z ^ -1 - Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1); - Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1); - //PKA_MONT2GF(3, 5,3, 5,3, 6); - Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 6, - ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); - - //R.x (Montgomery to GF) - //PKA_MONT2GF(3, 6,3, 2,3, 6); - Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_REG_TYPE, 2, ECP_SECP256R1_REG_TYPE, 6, - ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); - - //R.x (GF to Affine domain) - //PKA_MONT2GF(3, 2,3, 5,3, 6); - Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 2, ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 6, - ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)bar_u2_x, ECP_SECP256R1_SIZE / 4); -#ifdef ECDSA_DBG - MSG("R.x=\r\n"); - bflb_platform_dump(bar_u2_x, ECP_SECP256R1_SIZE); -#endif - - /* Step7 check R.x=r*/ - /* Check Result */ - for (i = 0; i < 8; i++) { - if (bar_u2_x[i] != r[i]) { - return -1; - } - } - -#ifdef ECDSA_DBG - MSG("Verify success\r\n"); -#endif - - sec_ecdsa_verify_suss_callback(SEC_CODEPATH_STATE_SIGN, 1); - - return 0; -} - -int sec_ecdsa_sign(sec_ecdsa_handle_t *handle, const uint32_t *random_k, const uint32_t *hash, uint32_t hashLenInWord, uint32_t *r, uint32_t *s) -{ - uint32_t k[8]; - uint32_t Rx[8]; - uint32_t Ry[8]; - uint32_t KInvert[8]; - uint32_t maxTry1 = 100; - - /* Pointer check */ - if (handle->privateKey == NULL || hash == NULL || r == NULL || s == NULL) { - return -1; - } - - Sec_Eng_PKA_Reset(); - Sec_Eng_PKA_BigEndian_Enable(); - Sec_Eng_Trng_Enable(); - - while (maxTry1--) { - /* step 1 ,get random k*/ - if (random_k == NULL) { - if (sec_ecc_get_random_value(k, (uint32_t *)secp256r1N, 32) < 0) { - return -1; - } - } else { - memcpy(k, random_k, 32); - } - -#ifdef ECDSA_DBG - MSG("Random k:\r\n"); - bflb_platform_dump(k, ECP_SECP256R1_SIZE); -#endif - - /*step 2, calc R=kG*/ - if (sec_ecdsa_get_public_key(handle, k, Rx, Ry) < 0) { - return -1; - } - - if (sec_ecc_is_zero((uint8_t *)Rx, 32)) { - continue; - } - - memcpy(r, Rx, 32); -#ifdef ECDSA_DBG - MSG("r:\r\n"); - bflb_platform_dump(r, ECP_SECP256R1_SIZE); -#endif - sec_ecc_basic_parameter_init(handle->ecpId); - /* step 3,get k^-1*/ - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)k, ECP_SECP256R1_SIZE / 4, 0); - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, (uint32_t *)secp256r1N, ECP_SECP256R1_SIZE / 4, 0); - /* Change k to Mont domain */ - /* Clear register for ECP_SECP256R1_LT_REG_INDEX*/ - Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1); - Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1); - Sec_Eng_PKA_GF2Mont(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 5, 256, - ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX); -#ifdef ECDSA_DBG - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); - MSG("GF2Mont Result of k:\r\n"); - bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); -#endif - - /* Get k^-1 in Mont domain */ - Sec_Eng_PKA_MINV(ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_REG_TYPE, 5, - ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, 1); -#ifdef ECDSA_DBG - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)KInvert, ECP_SECP256R1_SIZE / 4); - MSG("k^-1 in Mont:\r\n"); - bflb_platform_dump(KInvert, ECP_SECP256R1_SIZE); -#endif - - /* Change k^-1 into GF domain,now ECP_SECP256R1_S_REG_INDEX store k^-1*/ - /* Clear register for ECP_SECP256R1_LT_REG_INDEX*/ - Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_INVR_N_REG_INDEX, - ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX); - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)KInvert, ECP_SECP256R1_SIZE / 4); -#ifdef ECDSA_DBG - MSG("k^-1:\r\n"); - bflb_platform_dump(KInvert, ECP_SECP256R1_SIZE); -#endif - - /* Step 4,r*d ((e + r * d) / k) */ - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 4, (uint32_t *)handle->privateKey, ECP_SECP256R1_SIZE / 4, 0); - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)r, ECP_SECP256R1_SIZE / 4, 0); - Sec_Eng_PKA_LMUL(ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 4, - ECP_SECP256R1_REG_TYPE, 5, 1); -#ifdef ECDSA_DBG - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 2); - MSG("r*d:\r\n"); - bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE * 2); -#endif - - /* Step 5,e+r*d ((e + r * d) / k) */ - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)hash, ECP_SECP256R1_SIZE / 4, 0); - Sec_Eng_PKA_LADD(ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, - ECP_SECP256R1_REG_TYPE, 5, 1); -#ifdef ECDSA_DBG - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 2); - MSG("e+r*d:\r\n"); - bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE * 2); -#endif - - /* Step 6,(e+r*d)*k^-1 ((e + r * d) / k) */ - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)KInvert, ECP_SECP256R1_SIZE / 4, 0); - Sec_Eng_PKA_LMUL(ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, - ECP_SECP256R1_REG_TYPE, 5, 1); -#ifdef ECDSA_DBG - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 2); - MSG("(e+r*d)*k^-1:\r\n"); - bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE * 2); -#endif - /*N write only this time,add following operation will not change this register*/ - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, (uint32_t *)secp256r1N, ECP_SECP256R1_SIZE / 4, 0); - Sec_Eng_PKA_MREM(ECP_SECP256R1_REG_TYPE, 4, ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, - ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, 1); - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 4, (uint32_t *)s, ECP_SECP256R1_SIZE / 4); -#ifdef ECDSA_DBG - MSG("s:\r\n"); - bflb_platform_dump(s, ECP_SECP256R1_SIZE); -#endif - - /* Check s zero*/ - if (sec_ecc_is_zero((uint8_t *)s, 32)) { - continue; - } - - return 0; - } - - return -1; -} - -int sec_ecdsa_get_private_key(sec_ecdsa_handle_t *handle, uint32_t *private_key) -{ - if (sec_ecc_get_random_value(private_key, (uint32_t *)secp256r1N, 32) < 0) { - return -1; - } - - return 0; -} - -int sec_ecdsa_get_public_key(sec_ecdsa_handle_t *handle, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy) -{ - return sec_ecdh_get_scalar_point(handle->ecpId, NULL, NULL, private_key, pRx, pRy); -} - -int sec_ecc_get_random_value(uint32_t *randomData, uint32_t *maxRef, uint32_t size) -{ - uint32_t maxTry = 100; - int32_t ret = 0; - - while (maxTry--) { - ret = Sec_Eng_Trng_Get_Random((uint8_t *)randomData, size); - - if (ret < 0) { - return -1; - } - - if (maxRef != NULL) { - if (sec_ecc_cmp((uint8_t *)maxRef, (uint8_t *)randomData, size) > 0) { - return 0; - } - } else { - return 0; - } - } - - return -1; -} - -int sec_eng_trng_enable(void) -{ - return Sec_Eng_Trng_Enable(); -} - -void sec_eng_trng_disable(void) -{ - Sec_Eng_Trng_Disable(); -} - -int sec_eng_trng_read(uint8_t data[32]) -{ - return Sec_Eng_Trng_Read(data); -} - -int sec_ecdh_init(sec_ecdh_handle_t *handle, sec_ecp_type id) -{ - Sec_Eng_PKA_Reset(); - Sec_Eng_PKA_BigEndian_Enable(); - Sec_Eng_Trng_Enable(); - - handle->ecpId = id; - - return 0; -} - -int sec_ecdh_deinit(sec_ecdh_handle_t *handle) -{ - Sec_Eng_PKA_Reset(); - - return 0; -} - -int sec_ecdh_get_encrypt_key(sec_ecdh_handle_t *handle, const uint32_t *pkX, const uint32_t *pkY, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy) -{ - return sec_ecdh_get_scalar_point(handle->ecpId, pkX, pkY, private_key, pRx, pRy); -} - -int sec_ecdh_get_public_key(sec_ecdh_handle_t *handle, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy) -{ - return sec_ecdh_get_scalar_point(handle->ecpId, NULL, NULL, private_key, pRx, pRy); -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_sec_hash.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_sec_hash.c deleted file mode 100644 index d34121dd95..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_sec_hash.c +++ /dev/null @@ -1,387 +0,0 @@ -/** - * @file hal_sec_hash.c - * @brief - * - * Copyright 2019-2030 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#include "hal_sec_hash.h" -#include "bl808_sec_eng.h" - -void SEC_SHA_IRQHandler(void); - -static sec_hash_device_t sec_hashx_device[SEC_HASH_MAX_INDEX] = { - 0 -}; - -static SEC_Eng_SHA256_Ctx shaCtx; - -static SEC_Eng_SHA256_Ctx sha256Ctx; - -/** - * @brief - * - * @param dev - * @param oflag - * @return int - */ -int sec_hash_open(struct device *dev, uint16_t oflag) -{ - sec_hash_device_t *sec_hash_device = (sec_hash_device_t *)dev; - int ret = 0; - - switch (sec_hash_device->type) { - case SEC_HASH_SHA1: - ret = -1; - break; - - case SEC_HASH_SHA224: - Sec_Eng_SHA256_Init(&shaCtx, SEC_ENG_SHA_ID0, SEC_ENG_SHA224, sec_hash_device->shaBuf, sec_hash_device->shaPadding); - Sec_Eng_SHA_Start(SEC_ENG_SHA_ID0); - break; - - case SEC_HASH_SHA256: - Sec_Eng_SHA256_Init(&shaCtx, SEC_ENG_SHA_ID0, SEC_ENG_SHA256, sec_hash_device->shaBuf, sec_hash_device->shaPadding); - Sec_Eng_SHA_Start(SEC_ENG_SHA_ID0); - break; - - case SEC_HASH_SHA384: - case SEC_HASH_SHA512: - ret = -1; - break; - - default: - ret = -1; - break; - } - - return ret; -} -/** - * @brief - * - * @param dev - * @return int - */ -int sec_hash_close(struct device *dev) -{ - //sec_hash_device_t *sec_hash_device = (sec_hash_device_t *)dev; - //memset(sec_hash_device, 0, sizeof(sec_hash_device_t)); //will cause crash - return 0; -} -/** - * @brief - * - * @param dev - * @param cmd - * @param args - * @return int - */ -int sec_hash_control(struct device *dev, int cmd, void *args) -{ - return 0; -} - -/** - * @brief - * - * @param dev - * @param pos - * @param buffer - * @param size - * @return int - */ -int sec_hash_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size) -{ - sec_hash_device_t *sec_hash_device = (sec_hash_device_t *)dev; - int ret = 0; - - switch (sec_hash_device->type) { - case SEC_HASH_SHA1: - ret = -1; - break; - - case SEC_HASH_SHA224: - Sec_Eng_SHA256_Update(&shaCtx, SEC_ENG_SHA_ID0, (uint8_t *)buffer, size); - break; - - case SEC_HASH_SHA256: - Sec_Eng_SHA256_Update(&shaCtx, SEC_ENG_SHA_ID0, (uint8_t *)buffer, size); - break; - - case SEC_HASH_SHA384: - case SEC_HASH_SHA512: - ret = -1; - break; - - default: - ret = -1; - break; - } - - return ret; -} - -/** - * @brief - * - * @param dev - * @param pos - * @param buffer - * @param size - * @return int - */ -int sec_hash_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size) -{ - sec_hash_device_t *sec_hash_device = (sec_hash_device_t *)dev; - int ret = 0; - - switch (sec_hash_device->type) { - case SEC_HASH_SHA1: - ret = -1; - break; - - case SEC_HASH_SHA224: - Sec_Eng_SHA256_Finish(&shaCtx, SEC_ENG_SHA_ID0, (uint8_t *)buffer); - ret = 28; - break; - - case SEC_HASH_SHA256: - Sec_Eng_SHA256_Finish(&shaCtx, SEC_ENG_SHA_ID0, (uint8_t *)buffer); - ret = 32; - break; - - case SEC_HASH_SHA384: - case SEC_HASH_SHA512: - ret = -1; - break; - - default: - ret = -1; - break; - } - - return ret; -} - -/** - * @brief - * - * @param handle - * @param type - * @return int - */ -int sec_hash_init(sec_hash_handle_t *handle, uint8_t type) -{ - int ret = 0; - - switch (type) { - case SEC_HASH_SHA1: - ret = -1; - break; - - case SEC_HASH_SHA224: - handle->type = type; - Sec_Eng_SHA256_Init(&sha256Ctx, SEC_ENG_SHA_ID0, SEC_ENG_SHA224, handle->shaBuf, handle->shaPadding); - Sec_Eng_SHA_Start(SEC_ENG_SHA_ID0); - break; - - case SEC_HASH_SHA256: - handle->type = type; - Sec_Eng_SHA256_Init(&sha256Ctx, SEC_ENG_SHA_ID0, SEC_ENG_SHA256, handle->shaBuf, handle->shaPadding); - Sec_Eng_SHA_Start(SEC_ENG_SHA_ID0); - break; - - case SEC_HASH_SHA384: - case SEC_HASH_SHA512: - ret = -1; - break; - - default: - ret = -1; - break; - } - - return ret; -} -/** - * @brief - * - * @param handle - * @return int - */ -int sec_hash_deinit(sec_hash_handle_t *handle) -{ - memset(handle->shaBuf, 0, sizeof(handle->shaBuf)); - memset(handle->shaPadding, 0, sizeof(handle->shaPadding)); - - return 0; -} - -/** - * @brief - * - * @param handle - * @param buffer - * @param size - * @return int - */ -int sec_hash_update(sec_hash_handle_t *handle, const void *buffer, uint32_t size) -{ - int ret = 0; - - switch (handle->type) { - case SEC_HASH_SHA1: - ret = -1; - break; - - case SEC_HASH_SHA224: - Sec_Eng_SHA256_Update(&sha256Ctx, SEC_ENG_SHA_ID0, (uint8_t *)buffer, size); - break; - - case SEC_HASH_SHA256: - Sec_Eng_SHA256_Update(&sha256Ctx, SEC_ENG_SHA_ID0, (uint8_t *)buffer, size); - break; - - case SEC_HASH_SHA384: - case SEC_HASH_SHA512: - ret = -1; - break; - - default: - ret = -1; - break; - } - - return ret; -} - -/** - * @brief - * - * @param handle - * @param buffer - * @return int - */ -int sec_hash_finish(sec_hash_handle_t *handle, void *buffer) -{ - int ret = 0; - - switch (handle->type) { - case SEC_HASH_SHA1: - ret = -1; - break; - - case SEC_HASH_SHA224: - Sec_Eng_SHA256_Finish(&sha256Ctx, SEC_ENG_SHA_ID0, (uint8_t *)buffer); - ret = 28; - break; - - case SEC_HASH_SHA256: - Sec_Eng_SHA256_Finish(&sha256Ctx, SEC_ENG_SHA_ID0, (uint8_t *)buffer); - ret = 32; - break; - - case SEC_HASH_SHA384: - case SEC_HASH_SHA512: - ret = -1; - break; - - default: - ret = -1; - break; - } - - return ret; -} - -/** - * @brief - * - * @param index - * @param type - * @param name - * @param flag - * @return int - */ -static int sec_hash_sha_register(enum sec_hash_index_type index, enum sec_hash_type type, const char *name) -{ - struct device *dev; - - if (SEC_HASH_MAX_INDEX == 0) { - return -DEVICE_EINVAL; - } - - dev = &(sec_hashx_device[index].parent); - sec_hashx_device[index].type = type; - - dev->open = sec_hash_open; - dev->close = sec_hash_close; - dev->control = sec_hash_control; - dev->write = sec_hash_write; - dev->read = sec_hash_read; - - dev->type = DEVICE_CLASS_SEC_HASH; - dev->handle = NULL; - - return device_register(dev, name); -} - -/** - * @brief - * - * @param index - * @param name - * @param flag - * @return int - */ -int sec_hash_sha256_register(enum sec_hash_index_type index, const char *name) -{ - return sec_hash_sha_register(index, SEC_HASH_SHA256, name); -} - -/** - * @brief - * - * @param index - * @param name - * @param flag - * @return int - */ -int sec_hash_sha224_register(enum sec_hash_index_type index, const char *name) -{ - return sec_hash_sha_register(index, SEC_HASH_SHA224, name); -} - -/** - * @brief - * - * @param handle - */ -void sec_hash_isr(void) -{ -} - -/** - * @brief - * - */ -void SEC_SHA_IRQ(void) -{ - sec_hash_isr(); -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_spi.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_spi.c deleted file mode 100644 index 8538d9706c..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_spi.c +++ /dev/null @@ -1,494 +0,0 @@ -/** - * @file hal_spi.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#include "hal_spi.h" -#include "hal_dma.h" -#include "bl808_glb.h" -#include "bl808_spi.h" - -#ifdef BSP_USING_SPI0 -static void SPI0_IRQ_Function(void); -#endif -#ifdef BSP_USING_SPI1 -static void SPI1_IRQ_Function(void); -#endif - -static spi_device_t spix_device[SPI_MAX_INDEX] = { -#ifdef BSP_USING_SPI0 - SPI0_CONFIG, -#endif -#ifdef BSP_USING_SPI1 - SPI1_CONFIG, -#endif -}; - -// static uint8_t SPI_IRQ_NumList[SPI_ID_MAX] = {SPI0_IRQn, SPI1_IRQn}; -extern const uint32_t spiAddr[]; - -/** - * @brief - * - * @param dev - * @param oflag - * @return int - */ -int spi_open(struct device *dev, uint16_t oflag) -{ - spi_device_t *spi_device = (spi_device_t *)dev; - SPI_CFG_Type spiCfg = { 0 }; - SPI_FifoCfg_Type fifoCfg = { 0 }; - SPI_ClockCfg_Type clockCfg; - uint32_t spi_clk; - - /* reset SPI (close SPI)*/ - SPI_DeInit(spi_device->id); - - switch (spi_device->id) - { - case 0: - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_SPI); - GLB_Set_SPI_CLK(ENABLE, GLB_SPI_CLK_MCU_MUXPLL_160M, 0); - CPU_Interrupt_Disable(SPI0_IRQn); - GLB_Swap_MCU_SPI_0_MOSI_With_MISO(spi_device->pin_swap_enable); - GLB_Set_MCU_SPI_0_ACT_MOD_Sel(spi_device->mode); - break; - case 1: - GLB_Set_DSP_SPI_CLK(ENABLE, GLB_DSP_SPI_CLK_DSP_MUXPLL_160M, 0); - CPU_Interrupt_Disable(SPI1_IRQn); - GLB_Swap_DSP_SPI_0_MOSI_With_MISO(spi_device->pin_swap_enable); - GLB_Set_DSP_SPI_0_ACT_MOD_Sel(spi_device->mode); - break; - default: - break; - } - - /* get spi peripheral clock */ - spi_clk = Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_SPI0 + spi_device->id); - - /* Out of maximum clock */ - if((spi_clk >> 1) < spi_device->clk ){ - return -1; - } - uint8_t div = spi_clk / spi_device->clk; - - clockCfg.dataPhase0Len = (div >> 1); - clockCfg.dataPhase1Len = (div >> 1); - clockCfg.startLen = (div >> 1); - clockCfg.stopLen = (div >> 1); - clockCfg.intervalLen = (div >> 1); - - if(div % 2){ - /* When Phase0 and Phase1 are not equal, increase the high level time */ - if((uint8_t)spi_device->clk_polaraity == (uint8_t)spi_device->clk_phase){ - clockCfg.dataPhase0Len += 1; - }else{ - clockCfg.dataPhase1Len += 1; - } - } - - SPI_ClockConfig(spi_device->id, &clockCfg); - - /* Continuous transmission is enabled by default */ - spiCfg.continuousEnable = 1; - - if (spi_device->direction == SPI_LSB_BYTE0_DIRECTION_FIRST) { - spiCfg.bitSequence = SPI_BIT_INVERSE_LSB_FIRST; - spiCfg.byteSequence = SPI_BYTE_INVERSE_BYTE0_FIRST; - } else if (spi_device->direction == SPI_LSB_BYTE3_DIRECTION_FIRST) { - spiCfg.bitSequence = SPI_BIT_INVERSE_LSB_FIRST; - spiCfg.byteSequence = SPI_BYTE_INVERSE_BYTE3_FIRST; - } else if (spi_device->direction == SPI_MSB_BYTE0_DIRECTION_FIRST) { - spiCfg.bitSequence = SPI_BIT_INVERSE_MSB_FIRST; - spiCfg.byteSequence = SPI_BYTE_INVERSE_BYTE0_FIRST; - } else if (spi_device->direction == SPI_MSB_BYTE3_DIRECTION_FIRST) { - spiCfg.bitSequence = SPI_BIT_INVERSE_MSB_FIRST; - spiCfg.byteSequence = SPI_BYTE_INVERSE_BYTE3_FIRST; - } - - spiCfg.clkPolarity = spi_device->clk_polaraity; - spiCfg.clkPhaseInv = spi_device->clk_phase; - spiCfg.frameSize = spi_device->datasize; - - if (spi_device->delitch_cnt) { - spiCfg.deglitchEnable = 1; - SPI_SetDeglitchCount(spi_device->id, spi_device->delitch_cnt - 1); - }else{ - spiCfg.deglitchEnable = 0; - } - - /* SPI config */ - SPI_Init(spi_device->id, &spiCfg); - - if(fifoCfg.txFifoThreshold){ - fifoCfg.txFifoThreshold = spi_device->fifo_threshold - 1; - fifoCfg.rxFifoThreshold = spi_device->fifo_threshold - 1; - }else{ - fifoCfg.txFifoThreshold = spi_device->fifo_threshold; - fifoCfg.rxFifoThreshold = spi_device->fifo_threshold; - } - fifoCfg.txFifoDmaEnable = DISABLE; - fifoCfg.rxFifoDmaEnable = DISABLE; - - if (oflag & DEVICE_OFLAG_INT_TX || oflag & DEVICE_OFLAG_INT_RX) { -#ifdef BSP_USING_SPI0 - if(spi_device->id == 0){ - Interrupt_Handler_Register(SPI0_IRQn, SPI0_IRQ_Function); - } -#endif -#ifdef BSP_USING_SPI1 - if(spi_device->id == 1){ - Interrupt_Handler_Register(SPI1_IRQn, SPI1_IRQ_Function); - } -#endif - } - - if (oflag & DEVICE_OFLAG_DMA_TX) { - fifoCfg.txFifoDmaEnable = ENABLE; - } - - if (oflag & DEVICE_OFLAG_DMA_RX) { - fifoCfg.rxFifoDmaEnable = ENABLE; - } - - SPI_FifoConfig(spi_device->id, &fifoCfg); - /* Enable spi master mode */ - SPI_Enable(spi_device->id, spi_device->mode); - - return 0; -} -/** - * @brief - * - * @param dev - * @return int - */ -int spi_close(struct device *dev) -{ - spi_device_t *spi_device = (spi_device_t *)dev; - - SPI_DeInit(spi_device->id); - - return 0; -} -/** - * @brief - * - * @param dev - * @param cmd - * @param args - * @return int - */ -int spi_control(struct device *dev, int cmd, void *args) -{ - spi_device_t *spi_device = (spi_device_t *)dev; - - switch (cmd) { - case DEVICE_CTRL_SET_INT /* constant-expression */: - - break; - - case DEVICE_CTRL_CLR_INT /* constant-expression */: - /* code */ - break; - - case DEVICE_CTRL_GET_INT /* constant-expression */: - /* code */ - break; - - case DEVICE_CTRL_RESUME: - /* code */ - SPI_Enable(spi_device->id, spi_device->mode); - break; - - case DEVICE_CTRL_SUSPEND: - SPI_Disable(spi_device->id, spi_device->mode); - break; - - case DEVICE_CTRL_ATTACH_TX_DMA: - spi_device->tx_dma = (struct device *)args; - break; - - case DEVICE_CTRL_ATTACH_RX_DMA: - spi_device->rx_dma = (struct device *)args; - break; - - case DEVICE_CTRL_SPI_CONFIG_CLOCK: - SPI_SetClock(spi_device->id, (uint32_t)(uintptr_t)args); - break; - - case DEVICE_CTRL_TX_DMA_SUSPEND: { - uint32_t tmpVal = BL_RD_REG(spiAddr[spi_device->id], SPI_FIFO_CONFIG_0); - tmpVal = BL_CLR_REG_BIT(tmpVal, SPI_DMA_TX_EN); - BL_WR_REG(spiAddr[spi_device->id], SPI_FIFO_CONFIG_0, tmpVal); - dev->oflag &= ~DEVICE_OFLAG_DMA_TX; - break; - } - - case DEVICE_CTRL_RX_DMA_SUSPEND: { - uint32_t tmpVal = BL_RD_REG(spiAddr[spi_device->id], SPI_FIFO_CONFIG_0); - tmpVal = BL_CLR_REG_BIT(tmpVal, SPI_DMA_RX_EN); - BL_WR_REG(spiAddr[spi_device->id], SPI_FIFO_CONFIG_0, tmpVal); - dev->oflag &= ~DEVICE_OFLAG_DMA_RX; - break; - } - - case DEVICE_CTRL_TX_DMA_RESUME: { - uint32_t tmpVal = BL_RD_REG(spiAddr[spi_device->id], SPI_FIFO_CONFIG_0); - tmpVal = BL_SET_REG_BIT(tmpVal, SPI_DMA_TX_EN); - BL_WR_REG(spiAddr[spi_device->id], SPI_FIFO_CONFIG_0, tmpVal); - dev->oflag |= DEVICE_OFLAG_DMA_TX; - break; - } - - case DEVICE_CTRL_RX_DMA_RESUME: { - uint32_t tmpVal = BL_RD_REG(spiAddr[spi_device->id], SPI_FIFO_CONFIG_0); - tmpVal = BL_SET_REG_BIT(tmpVal, SPI_DMA_RX_EN); - BL_WR_REG(spiAddr[spi_device->id], SPI_FIFO_CONFIG_0, tmpVal); - dev->oflag |= DEVICE_OFLAG_DMA_RX; - break; - } - case DEVICE_CTRL_SPI_GET_TX_FIFO : - return SPI_GetTxFifoCount(spi_device->id); - - case DEVICE_CTRL_SPI_GET_RX_FIFO : - return SPI_GetRxFifoCount(spi_device->id); - - case DEVICE_CTRL_SPI_CLEAR_TX_FIFO : - return SPI_ClrTxFifo(spi_device->id); - - case DEVICE_CTRL_SPI_CLEAR_RX_FIFO : - return SPI_ClrRxFifo(spi_device->id); - - case DEVICE_CTRL_SPI_GET_BUS_BUSY_STATUS : - return SPI_GetBusyStatus(spi_device->id); - - case DEVICE_CTRL_SPI_SET_FRAME_SIZE: - SPI_SetFrameSize(spi_device->id, (uint32_t)(uintptr_t)args); - spi_device->datasize = (uint32_t)(uintptr_t)args; - break; - default: - break; - } - - return 0; -} -/** - * @brief - * - * @param dev - * @param pos - * @param buffer - * @param size - * @return int - */ -int spi_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size) -{ - int ret = 0; - spi_device_t *spi_device = (spi_device_t *)dev; - - if (dev->oflag & DEVICE_OFLAG_DMA_TX) { - struct device *dma_ch = (struct device *)spi_device->tx_dma; - if (!dma_ch) { - return -1; - } - /* Set valid width for each fifo entry */ - if(spi_device->datasize != DMA_DEV(dma_ch)->dst_width){ - switch (DMA_DEV(dma_ch)->dst_width) { - case DMA_TRANSFER_WIDTH_8BIT: - SPI_SetFrameSize(spi_device->id, SPI_FRAME_SIZE_8); - break; - case DMA_TRANSFER_WIDTH_16BIT: - SPI_SetFrameSize(spi_device->id, SPI_FRAME_SIZE_16); - break; - - case DMA_TRANSFER_WIDTH_32BIT: - SPI_SetFrameSize(spi_device->id, SPI_FRAME_SIZE_32); - break; - default: - break; - } - spi_device->datasize = DMA_DEV(dma_ch)->dst_width; - } - - if(spi_device->id == 0){ - ret = dma_reload(dma_ch, (uint32_t)(uintptr_t)buffer, (uint32_t)DMA_ADDR_SPI0_TDR, size); - }else if(spi_device->id == 1){ - ret = dma_reload(dma_ch, (uint32_t)(uintptr_t)buffer, (uint32_t)DMA_ADDR_SPI1_TDR, size); - } - dma_channel_start(dma_ch); - - return ret; - - } else if (dev->oflag & DEVICE_OFLAG_INT_TX) { - return -2; - } else { - SPI_ClrRxFifo(spi_device->id); - ret = SPI_SendData(spi_device->id, (void *)buffer, size, SPI_TIMEOUT_DISABLE); - return 0; - } -} -/** - * @brief - * - * @param dev - * @param pos - * @param buffer - * @param size - * @return int - */ -int spi_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size) -{ - int ret = 0; - spi_device_t *spi_device = (spi_device_t *)dev; - - if (dev->oflag & DEVICE_OFLAG_DMA_RX) { - struct device *dma_ch = (struct device *)spi_device->rx_dma; - if (!dma_ch) { - return -1; - } - - /* Set valid width for each fifo entry */ - uint32_t tmpVal = BL_RD_REG(spiAddr[spi_device->id], SPI_CONFIG); - switch (DMA_DEV(dma_ch)->dst_width) { - case DMA_TRANSFER_WIDTH_8BIT: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 0); - break; - case DMA_TRANSFER_WIDTH_16BIT: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 1); - break; - - case DMA_TRANSFER_WIDTH_32BIT: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 3); - break; - default: - break; - } - BL_WR_REG(spiAddr[spi_device->id], SPI_CONFIG,tmpVal); - - if(spi_device->id == 0){ - ret = dma_reload(dma_ch, (uint32_t)DMA_ADDR_SPI0_RDR, (uint32_t)(uintptr_t)buffer, size); - }else if(spi_device->id == 1){ - ret = dma_reload(dma_ch, (uint32_t)DMA_ADDR_SPI1_RDR, (uint32_t)(uintptr_t)buffer, size); - } - dma_channel_start(dma_ch); - return ret; - - } else if (dev->oflag & DEVICE_OFLAG_INT_TX) { - return -2; - } else { - ret = SPI_ReceiveData(spi_device->id, buffer, size, SPI_TIMEOUT_DISABLE); - return 0; - } -} -/** - * @brief - * - * @param index - * @param name - * @param flag - * @return int - */ -int spi_register(enum spi_index_type index, const char *name) -{ - struct device *dev; - - if (SPI_MAX_INDEX == 0) { - return -DEVICE_EINVAL; - } - - dev = &(spix_device[index].parent); - - dev->open = spi_open; - dev->close = spi_close; - dev->control = spi_control; - dev->write = spi_write; - dev->read = spi_read; - - dev->type = DEVICE_CLASS_SPI; - dev->handle = NULL; - - return device_register(dev, name); -} - -/** - * @brief - * - * @param handle - */ -void spi_isr(spi_device_t *handle) -{ - uint32_t tmpVal; - uint32_t spix_base = spiAddr[handle->id]; - - tmpVal = BL_RD_REG(spix_base, SPI_INT_STS); - - if (!handle->parent.callback) { - return; - } - - /* Transfer end interrupt,shared by both master and slave mode */ - if (BL_IS_REG_BIT_SET(tmpVal, SPI_END_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_END_MASK)) { - BL_WR_REG(spix_base, SPI_INT_STS, BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_END_CLR)); - handle->parent.callback(&handle->parent, NULL, 0, SPI_INT_END); - } - - /* TX fifo ready interrupt(fifo count > fifo threshold) */ - if (BL_IS_REG_BIT_SET(tmpVal, SPI_TXF_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_TXF_MASK)) { - handle->parent.callback(&handle->parent, NULL, 0, SPI_INT_TX_FIFO_REQ); - } - - /* RX fifo ready interrupt(fifo count > fifo threshold) */ - if (BL_IS_REG_BIT_SET(tmpVal, SPI_RXF_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_RXF_MASK)) { - handle->parent.callback(&handle->parent, NULL, 0, SPI_INT_RX_FIFO_REQ); - } - - /* Slave mode transfer time-out interrupt,triggered when bus is idle for the given value */ - if (BL_IS_REG_BIT_SET(tmpVal, SPI_STO_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_STO_MASK)) { - BL_WR_REG(spix_base, SPI_INT_STS, BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_STO_CLR)); - handle->parent.callback(&handle->parent, NULL, 0, SPI_INT_SLAVE_TIMEOUT); - } - - /* Slave mode tx underrun error interrupt,trigged when tx is not ready during transfer */ - if (BL_IS_REG_BIT_SET(tmpVal, SPI_TXU_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_TXU_MASK)) { - BL_WR_REG(spix_base, SPI_INT_STS, BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_TXU_CLR)); - handle->parent.callback(&handle->parent, NULL, 0, SPI_INT_SLAVE_UNDERRUN); - } - - /* TX/RX fifo overflow/underflow interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, SPI_FER_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_FER_MASK)) { - handle->parent.callback(&handle->parent, NULL, 0, SPI_INT_FIFO_ERROR); - } -} - -#ifdef BSP_USING_SPI0 -void SPI0_IRQ_Function() -{ - spi_isr(&spix_device[SPI0_INDEX]); -} -#endif - -#ifdef BSP_USING_SPI1 -void SPI1_IRQ_Function() -{ - spi_isr(&spix_device[SPI1_INDEX]); -} -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_spi_flash.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_spi_flash.c deleted file mode 100644 index 4f190ae27e..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_spi_flash.c +++ /dev/null @@ -1,589 +0,0 @@ -/** - * @file spi_hal_flash.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#include "bl808_common.h" -#include "bl808_glb.h" -#include "bl808_gpio.h" -#include "bl808_spi.h" -#include "hal_spi_flash.h" - - -#define SPI_USE_ID SPI0_ID -#define SPI_PAD_ACT GLB_SPI_PAD_ACT_AS_MASTER -#define SPI_USE_IRQ SPI0_IRQn -#define SPI_FLASH_BLK32K_SIZE (32 * 1024) -#define SPI_FLASH_BLK64K_SIZE (64 * 1024) -#define SPI_FLASH_DELAY_L (arch_delay_ms(1)) -#define SPI_FLASH_DELAY_H (arch_delay_ms(2)) - -static uint8_t spi_flash_cs_gpio = GLB_GPIO_PIN_4; -static uint8_t spi_flash_clk_gpio = GLB_GPIO_PIN_3; -static uint8_t spi_flash_mosi_gpio = GLB_GPIO_PIN_2; -static uint8_t spi_flash_miso_gpio = GLB_GPIO_PIN_1; - - -/** - * @brief SPI interrupt callback - * - * @return None - */ -static void SPI_Int_Callback(void) -{ - -} - -/** - * @brief spi flash pull cs gpio low - * - * @return None - */ -static __inline void spi_flash_pull_cs_low(void) -{ - GLB_GPIO_Write(spi_flash_cs_gpio, 0); -} - -/** - * @brief spi flash pull cs gpio high - * - * @return None - */ -static __inline void spi_flash_pull_cs_high(void) -{ - GLB_GPIO_Write(spi_flash_cs_gpio, 1); -} - -/** - * @brief spi flash gpio init - * - * @return None - */ -static void spi_flash_gpio_init(void) -{ - GLB_GPIO_Type gpioPins[3] = {spi_flash_clk_gpio, spi_flash_mosi_gpio, spi_flash_miso_gpio}; - GLB_GPIO_Cfg_Type gpioCfg = { - /* CS */ - .gpioPin=spi_flash_cs_gpio, - .gpioFun=11, - .gpioMode=GPIO_MODE_OUTPUT, - .pullType=GPIO_PULL_NONE, - .drive=3, - .smtCtrl=1 - }; - - GLB_GPIO_Func_Init(GPIO_FUN_SPI0, (GLB_GPIO_Type *)gpioPins, sizeof(gpioPins)/sizeof(gpioPins[0])); - GLB_GPIO_Init(&gpioCfg); - spi_flash_pull_cs_high(); - - if(SPI0_ID == SPI_USE_ID){ - GLB_Set_MCU_SPI_0_ACT_MOD_Sel(SPI_PAD_ACT); - }else{ - GLB_Set_DSP_SPI_0_ACT_MOD_Sel(SPI_PAD_ACT); - } -} - -/** - * @brief write enable - * - * @return None - */ -static void spi_flash_write_enable(void) -{ - uint8_t cmd[256] = {0}; - - SPI_SetFrameSize(SPI_USE_ID, SPI_FRAME_SIZE_8); - spi_flash_pull_cs_low(); - cmd[0] = 0x06; - SPI_SendData(SPI_USE_ID,cmd,1,SPI_TIMEOUT_ENABLE); - spi_flash_pull_cs_high(); -} - -/** - * @brief wait not busy - * - * @return None - */ -static void spi_flash_wait_notbusy(void) -{ - uint32_t wdata[1] = {0x05}; - uint32_t rdata[1] = {0}; - - while(1){ - spi_flash_pull_cs_low(); - SPI_SetFrameSize(SPI_USE_ID, SPI_FRAME_SIZE_24); - SPI_SendRecvData(SPI_USE_ID, wdata, rdata, 1, SPI_TIMEOUT_ENABLE); - spi_flash_pull_cs_high(); - - if(((uint8_t *)rdata)[1]&0x1){ - continue; - }else{ - break; - } - } -} - -/****************************************************************************//** - * @brief wait WEL 0 - * - * @param None - * - * @return None - * -*******************************************************************************/ -/** - * @brief wait WEL 0 - * - * @return None - */ -static void spi_flash_wait_wel_0(void) -{ - uint32_t wdata[1] = {0x05}; - uint32_t rdata[1] = {0}; - - while(1){ - spi_flash_pull_cs_low(); - SPI_SetFrameSize(SPI_USE_ID, SPI_FRAME_SIZE_24); - SPI_SendRecvData(SPI_USE_ID, wdata, rdata, 1, SPI_TIMEOUT_ENABLE); - spi_flash_pull_cs_high(); - - if(((uint8_t *)rdata)[1]&(1<<1)){ - continue; - }else{ - break; - } - } -} - -/** - * @brief wait WEL 1 - * - * @return None - */ -static void spi_flash_wait_wel_1(void) -{ - uint32_t wdata[1] = {0x05}; - uint32_t rdata[1] = {0}; - - while(1){ - spi_flash_pull_cs_low(); - SPI_SetFrameSize(SPI_USE_ID, SPI_FRAME_SIZE_24); - SPI_SendRecvData(SPI_USE_ID, wdata, rdata, 1, SPI_TIMEOUT_ENABLE); - spi_flash_pull_cs_high(); - - if(((uint8_t *)rdata)[1]&(1<<1)){ - break; - }else{ - continue; - } - } -} - -/** - * @brief spi flash sector erase - * - * @param sector number - * @return BL_Err_Type - */ -static BL_Err_Type spi_flash_sector_erase(uint32_t secNum) -{ - BL_Err_Type stat = SUCCESS; - uint32_t wdata[1] = {0}; - - spi_flash_wait_notbusy(); - spi_flash_write_enable(); - - spi_flash_pull_cs_low(); - ((uint8_t *)wdata)[0] = 0x20; - ((uint8_t *)wdata)[1] = ((secNum*4*1024)>>16)&0xFF; - ((uint8_t *)wdata)[2] = ((secNum*4*1024)>>8)&0xFF; - ((uint8_t *)wdata)[3] = ((secNum*4*1024)>>0)&0xFF; - - SPI_SetFrameSize(SPI_USE_ID, SPI_FRAME_SIZE_32); - stat = SPI_SendData(SPI_USE_ID, wdata, 1, SPI_TIMEOUT_ENABLE); - spi_flash_pull_cs_high(); - - spi_flash_wait_notbusy(); - spi_flash_wait_wel_0(); - - return stat; -} - -/** - * @brief spi flash block 32k erase - * - * @param block number - * @return BL_Err_Type - */ -static BL_Err_Type spi_flash_blk32_erase(uint32_t blkNum) -{ - BL_Err_Type stat = SUCCESS; - uint32_t wdata[1] = {0}; - - spi_flash_wait_notbusy(); - spi_flash_write_enable(); - - spi_flash_pull_cs_low(); - ((uint8_t *)wdata)[0] = 0x52; - ((uint8_t *)wdata)[1] = ((blkNum*SPI_FLASH_BLK32K_SIZE)>>16)&0xFF; - ((uint8_t *)wdata)[2] = ((blkNum*SPI_FLASH_BLK32K_SIZE)>>8)&0xFF; - ((uint8_t *)wdata)[3] = ((blkNum*SPI_FLASH_BLK32K_SIZE)>>0)&0xFF; - - SPI_SetFrameSize(SPI_USE_ID, SPI_FRAME_SIZE_32); - stat = SPI_SendData(SPI_USE_ID, wdata, 1, SPI_TIMEOUT_ENABLE); - spi_flash_pull_cs_high(); - - spi_flash_wait_notbusy(); - spi_flash_wait_wel_0(); - - return stat; -} - -/** - * @brief spi flash block 64k erase - * - * @param block number - * @return BL_Err_Type - */ -static BL_Err_Type spi_flash_blk64_erase(uint32_t blkNum) -{ - BL_Err_Type stat = SUCCESS; - uint32_t wdata[1] = {0}; - - spi_flash_wait_notbusy(); - spi_flash_write_enable(); - - spi_flash_pull_cs_low(); - ((uint8_t *)wdata)[0] = 0xd8; - ((uint8_t *)wdata)[1] = ((blkNum*SPI_FLASH_BLK64K_SIZE)>>16)&0xFF; - ((uint8_t *)wdata)[2] = ((blkNum*SPI_FLASH_BLK64K_SIZE)>>8)&0xFF; - ((uint8_t *)wdata)[3] = ((blkNum*SPI_FLASH_BLK64K_SIZE)>>0)&0xFF; - - SPI_SetFrameSize(SPI_USE_ID, SPI_FRAME_SIZE_32); - stat = SPI_SendData(SPI_USE_ID, wdata, 1, SPI_TIMEOUT_ENABLE); - spi_flash_pull_cs_high(); - - spi_flash_wait_notbusy(); - spi_flash_wait_wel_0(); - - return stat; -} - -/** - * @brief spi flash page write - * - * @param flashAddr: flash address - * @param wBuff: write buff - * @param wLen: write length - * @return BL_Err_Type - */ -static BL_Err_Type spi_flash_page_write(uint32_t flashAddr, uint8_t *wBuff, uint32_t wLen) -{ - uint32_t i; - uint8_t cmd[260] = {0}; - - if ((!wLen) || (wLen>256)) { - SPI_FLASH_DELAY_H; - return ERROR; - } - if (flashAddr & 0xFF) { - SPI_FLASH_DELAY_H; - } - - spi_flash_wait_notbusy(); - spi_flash_write_enable(); - spi_flash_wait_wel_1(); - - spi_flash_pull_cs_low(); - cmd[0] = 0x02; - cmd[1] = (flashAddr>>16)&0xFF; - cmd[2] = (flashAddr>>8)&0xFF; - cmd[3] = (flashAddr>>0)&0xFF; - for (i=0; i256)) { - SPI_FLASH_DELAY_L; - return ERROR; - } - if (flashAddr & 0xFF) { - SPI_FLASH_DELAY_H; - } - - spi_flash_wait_notbusy(); - - spi_flash_pull_cs_low(); - cmd[0] = 0x03; - cmd[1] = (flashAddr>>16)&0xFF; - cmd[2] = (flashAddr>>8)&0xFF; - cmd[3] = (flashAddr>>0)&0xFF; - for (i=4; i<260; i++) { - cmd[i] = 0; - } - SPI_SetFrameSize(SPI_USE_ID, SPI_FRAME_SIZE_8); - stat = SPI_SendRecvData(SPI_USE_ID, cmd, resp, rLen+4, SPI_TIMEOUT_DISABLE); - spi_flash_pull_cs_high(); - if(stat != SUCCESS){ - return stat; - } - - arch_memcpy(rBuff, resp+4, rLen); - - return SUCCESS; -} - - -/** - * @brief spi flash select gpio - * - * @param clk: clk gpio - * @param cs: cs gpio - * @param mosi: mosi gpio - * @param miso: miso gpio - * @return None - */ -void spi_flash_set_gpio(uint8_t clk, uint8_t cs, uint8_t mosi, uint8_t miso) -{ - spi_flash_cs_gpio = cs; - spi_flash_clk_gpio = clk; - spi_flash_mosi_gpio = mosi; - spi_flash_miso_gpio = miso; -} - -/** - * @brief spi flash init - * - * @return BL_Err_Type - */ -BL_Err_Type spi_flash_init(void) -{ - SPI_CFG_Type spiCfg = { - DISABLE, /* Disable de-glitch function */ - SPI_SLAVE_PIN_4, /* SPI 4-pin mode(CS is enabled) */ - ENABLE, /* Disable master continuous transfer mode */ - SPI_BYTE_INVERSE_BYTE0_FIRST, /* The byte 0 is sent first in SPI transfer */ - SPI_BIT_INVERSE_MSB_FIRST, /* MSB is sent first in SPI transfer */ - SPI_CLK_PHASE_INVERSE_0, /* SPI clock phase */ - SPI_CLK_POLARITY_LOW, /* SPI clock plarity */ - SPI_FRAME_SIZE_32 /* SPI frame size 8-bit(also the valid width for each fifo entry) */ - }; - - SPI_ClockCfg_Type clockCfg = { - 1, /* Length of start condition */ - 1, /* Length of stop condition */ - 1, /* Length of data phase 0,affecting clock */ - 1, /* Length of data phase 1,affecting clock */ - 1 /* Length of interval between frame */ - }; - - /* gpio and pad init */ - spi_flash_gpio_init(); - - /* GLB SPI clock config */ - GLB_Set_DSP_SPI_CLK(ENABLE, GLB_DSP_SPI_CLK_DSP_MUXPLL_160M, 0); - - /* SPI interrupt config */ - SPI_Int_Callback_Install(SPI_USE_ID, SPI_INT_END, SPI_Int_Callback); - SPI_IntMask(SPI_USE_ID, SPI_INT_ALL, MASK); - SPI_IntMask(SPI_USE_ID, SPI_INT_END, UNMASK); - CPU_Interrupt_Enable(SPI_USE_IRQ); - System_NVIC_SetPriority(SPI_USE_IRQ, 4, 1); - - /* SPI config */ - SPI_Init(SPI_USE_ID, &spiCfg); - - /* Set SPI clock */ - SPI_ClockConfig(SPI_USE_ID, &clockCfg); - - /* Enable spi master mode */ - SPI_Enable(SPI_USE_ID, SPI_WORK_MODE_MASTER); - - return SUCCESS; -} - -/** - * @brief spi flash read jedec id - * - * @param jedecid - * @return BL_Err_Type - */ -BL_Err_Type spi_flash_read_jedec_id(uint8_t *data) -{ - uint32_t wdata[1] = {0x9f}; - uint32_t rdata[1] = {0}; - BL_Err_Type stat = SUCCESS; - - SPI_SetFrameSize(SPI_USE_ID, SPI_FRAME_SIZE_32); - spi_flash_pull_cs_low(); - stat = SPI_SendRecvData(SPI_USE_ID, wdata, rdata, 1, SPI_TIMEOUT_ENABLE); - if(stat != SUCCESS) { - return stat; - } - spi_flash_pull_cs_high(); - if((0xFF==((uint8_t *)rdata)[1]) && (0xFF==((uint8_t *)rdata)[2]) && (0xFF==((uint8_t *)rdata)[3])) { - return ERROR; - } - - rdata[0] = (rdata[0]>>8); - arch_memcpy((uint8_t *)data, (uint8_t *)&rdata[0], 3); - - return stat; -} - -/** - * @brief spi flash read data - * - * @param addr - * @param data - * @param len - * @return BL_Err_Type - */ -BL_Err_Type spi_flash_read(uint32_t addr, uint8_t *data, uint32_t len) -{ - BL_Err_Type stat = SUCCESS; - uint32_t i; - uint32_t curLen; - - for (i = 0; i < len;) { - curLen = len - i; - if (curLen >= 256) { - curLen = 256; - } - - stat = spi_flash_page_read(addr, data, curLen); - if (stat != SUCCESS) { - return stat; - } - spi_flash_wait_notbusy(); - - /* Adjust address and programmed length */ - addr += curLen; - i += curLen; - data += curLen; - } - - return SUCCESS; -} - -/** - * @brief spi flash write data - * - * @param addr - * @param data - * @param len - * @return BL_Err_Type - */ -BL_Err_Type spi_flash_write(uint32_t addr, uint8_t *data, uint32_t len) -{ - BL_Err_Type stat = SUCCESS; - uint32_t i; - uint32_t curLen; - - for (i = 0; i < len;) { - /* Get current programmed length within page size */ - curLen = 256 - addr % 256; - - if (curLen > len - i) { - curLen = len - i; - } - - stat = spi_flash_page_write(addr, data, curLen); - if (stat != SUCCESS) { - return stat; - } - spi_flash_wait_notbusy(); - - /* Adjust address and programmed length */ - addr += curLen; - i += curLen; - data += curLen; - } - - return SUCCESS; -} - -/** - * @brief spi flash erase - * - * @param startaddr - * @param erase len - * @return BL_Err_Type - */ -BL_Err_Type spi_flash_erase(uint32_t startaddr, uint32_t len) -{ - uint32_t eraseLen = 0; - uint32_t endaddr = startaddr + len - 1; - BL_Err_Type stat = SUCCESS; - - if (startaddr > endaddr) { - return ERROR; - } - - while (startaddr <= endaddr) { - len = endaddr - startaddr + 1; - - if ((startaddr & (SPI_FLASH_BLK64K_SIZE - 1)) == 0 && - len > (SPI_FLASH_BLK64K_SIZE - 4 * 1024)) { - /* 64K margin address,and length > 64K-sector size, erase one first */ - stat = spi_flash_blk64_erase(startaddr / SPI_FLASH_BLK64K_SIZE); - eraseLen = SPI_FLASH_BLK64K_SIZE; - } else if ((startaddr & (SPI_FLASH_BLK32K_SIZE - 1)) == 0 && - len > (SPI_FLASH_BLK32K_SIZE - 4 * 1024)) { - /* 32K margin address,and length > 32K-sector size, erase one first */ - stat = spi_flash_blk32_erase(startaddr / SPI_FLASH_BLK32K_SIZE); - eraseLen = SPI_FLASH_BLK32K_SIZE; - } else { - /* Sector erase */ - startaddr = ((startaddr) & (~(4 - 1))); - stat = spi_flash_sector_erase(startaddr / 4 / 1024); - eraseLen = 4 * 1024; - } - - startaddr += eraseLen; - - if (stat != SUCCESS) { - return ERROR; - } - } - - return SUCCESS; -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_uart.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_uart.c deleted file mode 100644 index ef0dd2562d..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_uart.c +++ /dev/null @@ -1,528 +0,0 @@ -/** - * @file hal_uart.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#include "hal_uart.h" -#include "hal_dma.h" -#include "bl808_uart.h" -#include "bl808_glb.h" -#include "uart_config.h" - -#ifdef BSP_USING_UART0 -void UART0_IRQ(void); -#endif -#ifdef BSP_USING_UART1 -void UART1_IRQ(void); -#endif -#ifdef BSP_USING_UART2 -void UART2_IRQ(void); -#endif -#ifdef BSP_USING_UART3 -void UART3_IRQ(void); -#endif - -uart_device_t uartx_device[UART_MAX_INDEX] = { -#ifdef BSP_USING_UART0 - UART0_CONFIG, -#endif -#ifdef BSP_USING_UART1 - UART1_CONFIG, -#endif -#ifdef BSP_USING_UART2 - UART2_CONFIG, -#endif -#ifdef BSP_USING_UART3 - UART3_CONFIG, -#endif -}; - -static const uint32_t uartAddr[] = { UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE }; - -/** - * @brief - * - * @param dev - * @param oflag - * @return int - */ -int uart_open(struct device *dev, uint16_t oflag) -{ - uart_device_t *uart_device = (uart_device_t *)dev; - UART_FifoCfg_Type fifoCfg = { 0 }; - UART_CFG_Type uart_cfg = { 0 }; - uint32_t uart_clk; - - /* disable all interrupt */ - UART_IntMask(uart_device->id, UART_INT_ALL, MASK); - /* disable uart before config */ - UART_Disable(uart_device->id, UART_TXRX); - - uart_clk = Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_UART0 + uart_device->id); - - uart_cfg.baudRate = uart_device->baudrate; - uart_cfg.dataBits = uart_device->databits; - uart_cfg.stopBits = uart_device->stopbits; - uart_cfg.parity = uart_device->parity; - uart_cfg.uartClk = uart_clk; - uart_cfg.ctsFlowControl = UART_CTS_FLOWCONTROL_ENABLE; - uart_cfg.rtsSoftwareControl = UART_RTS_FLOWCONTROL_ENABLE; - uart_cfg.byteBitInverse = UART_MSB_FIRST_ENABLE; - uart_cfg.txSoftwareControl = UART_TX_SWCONTROL_ENABLE; - uart_cfg.txLinMode = UART_TX_LINMODE_ENABLE; - uart_cfg.rxLinMode = UART_RX_LINMODE_ENABLE; - uart_cfg.txBreakBitCnt = UART_TX_BREAKBIT_CNT; - - /* uart init with default configuration */ - UART_Init(uart_device->id, &uart_cfg); - - /* Enable tx free run mode */ - UART_TxFreeRun(uart_device->id, ENABLE); - - /* Set rx time-out value */ - UART_SetRxTimeoutValue(uart_device->id, UART_DEFAULT_RTO_TIMEOUT); - - fifoCfg.txFifoDmaThreshold = uart_device->fifo_threshold; - fifoCfg.txFifoDmaEnable = DISABLE; - fifoCfg.rxFifoDmaThreshold = uart_device->fifo_threshold; - fifoCfg.rxFifoDmaEnable = DISABLE; - - if (oflag & DEVICE_OFLAG_STREAM_TX) { - } - - if ((oflag & DEVICE_OFLAG_INT_TX) || (oflag & DEVICE_OFLAG_INT_RX)) { -#ifdef BSP_USING_UART0 - if (uart_device->id == UART0_ID) { - Interrupt_Handler_Register(UART0_IRQn, UART0_IRQ); - } -#endif -#ifdef BSP_USING_UART1 - if (uart_device->id == UART1_ID) { - Interrupt_Handler_Register(UART1_IRQn, UART1_IRQ); - } -#endif -#ifdef BSP_USING_UART2 - if (uart_device->id == UART2_ID) { - Interrupt_Handler_Register(UART2_IRQn, UART2_IRQ); - } -#endif -#ifdef BSP_USING_UART3 - if (uart_device->id == UART0_MM_ID) { - Interrupt_Handler_Register(UART3_IRQn, UART3_IRQ); - } -#endif - } - - if (oflag & DEVICE_OFLAG_DMA_TX) { - fifoCfg.txFifoDmaEnable = ENABLE; - } - - if (oflag & DEVICE_OFLAG_DMA_RX) { - fifoCfg.rxFifoDmaEnable = ENABLE; - } - - UART_FifoConfig(uart_device->id, &fifoCfg); - - UART_TxFifoClear(uart_device->id); - UART_RxFifoClear(uart_device->id); - - /* enable uart */ - UART_Enable(uart_device->id, UART_TXRX); - return 0; -} -/** - * @brief - * - * @param dev - * @return int - */ -int uart_close(struct device *dev) -{ - uart_device_t *uart_device = (uart_device_t *)dev; - - UART_Disable(uart_device->id, UART_TXRX); - return 0; -} -/** - * @brief - * - * @param dev - * @param cmd - * @param args - * @return int - */ -int uart_control(struct device *dev, int cmd, void *args) -{ - uart_device_t *uart_device = (uart_device_t *)dev; - - switch (cmd) { - case DEVICE_CTRL_SET_INT: { - int offset = __builtin_ctz((uint32_t)(uintptr_t)args); - - while (offset < 9) { - if ((uint32_t)(uintptr_t)args & (1 << offset)) { - UART_IntMask(uart_device->id, offset, UNMASK); - } - - offset++; - } - - if (uart_device->id == UART0_ID) { - CPU_Interrupt_Enable(UART0_IRQn); - } else if (uart_device->id == UART1_ID) { - CPU_Interrupt_Enable(UART1_IRQn); - } else if (uart_device->id == UART2_ID) { - CPU_Interrupt_Enable(UART2_IRQn); - } else if (uart_device->id == UART0_MM_ID) { - CPU_Interrupt_Enable(UART3_IRQn); - } - - break; - } - - case DEVICE_CTRL_CLR_INT: { - int offset = __builtin_ctz((uint32_t)(uintptr_t)args); - - while (offset < 9) { - if ((uint32_t)(uintptr_t)args & (1 << offset)) { - UART_IntMask(uart_device->id, offset, MASK); - } - - offset++; - } - - if (uart_device->id == UART0_ID) { - CPU_Interrupt_Disable(UART0_IRQn); - } else if (uart_device->id == UART1_ID) { - CPU_Interrupt_Disable(UART1_IRQn); - } else if (uart_device->id == UART2_ID) { - CPU_Interrupt_Disable(UART2_IRQn); - } else if (uart_device->id == UART0_MM_ID) { - CPU_Interrupt_Disable(UART3_IRQn); - } - - break; - } - - case DEVICE_CTRL_GET_INT: - break; - - case DEVICE_CTRL_CONFIG: { - uart_param_cfg_t *cfg = (uart_param_cfg_t *)args; - UART_CFG_Type uart_cfg = { 0 }; - - /* Disable uart before config */ - UART_Disable(uart_device->id, UART_TXRX); - uint32_t uart_clk = Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_UART0); - - uart_cfg.uartClk = uart_clk; - uart_cfg.baudRate = cfg->baudrate; - uart_cfg.stopBits = cfg->stopbits; - uart_cfg.parity = cfg->parity; - uart_cfg.dataBits = cfg->databits; - uart_cfg.ctsFlowControl = UART_CTS_FLOWCONTROL_ENABLE; - uart_cfg.rtsSoftwareControl = UART_RTS_FLOWCONTROL_ENABLE; - uart_cfg.byteBitInverse = UART_MSB_FIRST_ENABLE; - uart_cfg.txSoftwareControl = UART_TX_SWCONTROL_ENABLE; - uart_cfg.txLinMode = UART_TX_LINMODE_ENABLE; - uart_cfg.rxLinMode = UART_RX_LINMODE_ENABLE; - uart_cfg.txBreakBitCnt = UART_TX_BREAKBIT_CNT; - UART_Init(uart_device->id, &uart_cfg); - - UART_TxFifoClear(uart_device->id); - UART_RxFifoClear(uart_device->id); - - /* Enable uart */ - UART_Enable(uart_device->id, UART_TXRX); - break; - } - - case DEVICE_CTRL_GET_CONFIG: - break; - - case DEVICE_CTRL_ATTACH_TX_DMA: - uart_device->tx_dma = (struct device *)args; - break; - - case DEVICE_CTRL_ATTACH_RX_DMA: - uart_device->rx_dma = (struct device *)args; - break; - - case DEVICE_CTRL_TX_DMA_SUSPEND: { - uint32_t tmpVal = BL_RD_REG(uartAddr[uart_device->id], UART_FIFO_CONFIG_0); - tmpVal = BL_CLR_REG_BIT(tmpVal, UART_DMA_TX_EN); - BL_WR_REG(uartAddr[uart_device->id], UART_FIFO_CONFIG_0, tmpVal); - dev->oflag &= ~DEVICE_OFLAG_DMA_TX; - break; - } - - case DEVICE_CTRL_RX_DMA_SUSPEND: { - uint32_t tmpVal = BL_RD_REG(uartAddr[uart_device->id], UART_FIFO_CONFIG_0); - tmpVal = BL_CLR_REG_BIT(tmpVal, UART_DMA_RX_EN); - BL_WR_REG(uartAddr[uart_device->id], UART_FIFO_CONFIG_0, tmpVal); - dev->oflag &= ~DEVICE_OFLAG_DMA_RX; - break; - } - - case DEVICE_CTRL_TX_DMA_RESUME: { - uint32_t tmpVal = BL_RD_REG(uartAddr[uart_device->id], UART_FIFO_CONFIG_0); - tmpVal = BL_SET_REG_BIT(tmpVal, UART_DMA_TX_EN); - BL_WR_REG(uartAddr[uart_device->id], UART_FIFO_CONFIG_0, tmpVal); - dev->oflag |= DEVICE_OFLAG_DMA_TX; - break; - } - - case DEVICE_CTRL_RX_DMA_RESUME: { - uint32_t tmpVal = BL_RD_REG(uartAddr[uart_device->id], UART_FIFO_CONFIG_0); - tmpVal = BL_SET_REG_BIT(tmpVal, UART_DMA_RX_EN); - BL_WR_REG(uartAddr[uart_device->id], UART_FIFO_CONFIG_0, tmpVal); - dev->oflag |= DEVICE_OFLAG_DMA_RX; - break; - } - - case DEVICE_CTRL_UART_GET_TX_FIFO: - return UART_GetTxFifoCount(uart_device->id); - - case DEVICE_CTRL_UART_GET_RX_FIFO: - return UART_GetRxFifoCount(uart_device->id); - - default: - break; - } - - return 0; -} -/** - * @brief - * - * @param dev - * @param pos - * @param buffer - * @param size - * @return int - */ -int uart_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size) -{ - int ret = 0; - uart_device_t *uart_device = (uart_device_t *)dev; - if (dev->oflag & DEVICE_OFLAG_DMA_TX) { - struct device *dma_ch = (struct device *)uart_device->tx_dma; - if (!dma_ch) - return -1; - - if (uart_device->id == 0) { - ret = dma_reload(dma_ch, (uint32_t)(uintptr_t)buffer, (uint32_t)DMA_ADDR_UART0_TDR, size); - dma_channel_start(dma_ch); - } else if (uart_device->id == 1) { - ret = dma_reload(dma_ch, (uint32_t)(uintptr_t)buffer, (uint32_t)DMA_ADDR_UART1_TDR, size); - dma_channel_start(dma_ch); - } else if (uart_device->id == 2) { - ret = dma_reload(dma_ch, (uint32_t)(uintptr_t)buffer, (uint32_t)DMA_ADDR_UART2_TDR, size); - dma_channel_start(dma_ch); - } else if (uart_device->id == 3) { - ret = dma_reload(dma_ch, (uint32_t)(uintptr_t)buffer, (uint32_t)DMA_ADDR_UART3_TDR, size); - dma_channel_start(dma_ch); - } - return ret; - } else if (dev->oflag & DEVICE_OFLAG_INT_TX) { - return -2; - } else - return UART_SendData(uart_device->id, (uint8_t *)buffer, size); -} -/** - * @brief - * - * @param dev - * @param pos - * @param buffer - * @param size - * @return int - */ -int uart_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size) -{ - int ret = -1; - uart_device_t *uart_device = (uart_device_t *)dev; - if (dev->oflag & DEVICE_OFLAG_DMA_RX) { - struct device *dma_ch = (struct device *)uart_device->rx_dma; - if (!dma_ch) - return -1; - - if (uart_device->id == 0) { - ret = dma_reload(dma_ch, (uint32_t)DMA_ADDR_UART0_RDR, (uint32_t)(uintptr_t)buffer, size); - dma_channel_start(dma_ch); - } else if (uart_device->id == 1) { - ret = dma_reload(dma_ch, (uint32_t)DMA_ADDR_UART1_RDR, (uint32_t)(uintptr_t)buffer, size); - dma_channel_start(dma_ch); - } else if (uart_device->id == 2) { - ret = dma_reload(dma_ch, (uint32_t)DMA_ADDR_UART2_RDR, (uint32_t)(uintptr_t)buffer, size); - dma_channel_start(dma_ch); - } else if (uart_device->id == 3) { - ret = dma_reload(dma_ch, (uint32_t)DMA_ADDR_UART3_RDR, (uint32_t)(uintptr_t)buffer, size); - dma_channel_start(dma_ch); - } - return ret; - } else if (dev->oflag & DEVICE_OFLAG_INT_RX) { - return -2; - } else { - return UART_ReceiveData(uart_device->id, (uint8_t *)buffer, size); - } -} -/** - * @brief - * - * @param index - * @param name - * @param flag - * @return int - */ -int uart_register(enum uart_index_type index, const char *name) -{ - struct device *dev; - - if (UART_MAX_INDEX == 0) { - return -DEVICE_EINVAL; - } - - dev = &(uartx_device[index].parent); - - dev->open = uart_open; - dev->close = uart_close; - dev->control = uart_control; - dev->write = uart_write; - dev->read = uart_read; - - dev->type = DEVICE_CLASS_UART; - dev->handle = NULL; - - return device_register(dev, name); -} -/** - * @brief - * - * @param handle - */ -void uart_isr(uart_device_t *handle) -{ - uint32_t tmpVal = 0; - uint32_t maskVal = 0; - uint32_t UARTx = uartAddr[handle->id]; - - tmpVal = BL_RD_REG(UARTx, UART_INT_STS); - maskVal = BL_RD_REG(UARTx, UART_INT_MASK); - - if (!handle->parent.callback) { - return; - } - - /* Length of uart tx data transfer arrived interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_END_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_END_MASK)) { - BL_WR_REG(UARTx, UART_INT_CLEAR, 0x1); - handle->parent.callback(&handle->parent, NULL, 0, UART_EVENT_TX_END); - } - - /* Length of uart rx data transfer arrived interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_END_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_END_MASK)) { - BL_WR_REG(UARTx, UART_INT_CLEAR, 0x2); - handle->parent.callback(&handle->parent, NULL, 0, UART_EVENT_RX_END); - } - - /* Tx fifo ready interrupt,auto-cleared when data is pushed */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_FRDY_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_FRDY_MASK)) { - handle->parent.callback(&handle->parent, NULL, 0, UART_EVENT_TX_FIFO); - } - - /* Rx fifo ready interrupt,auto-cleared when data is popped */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_FRDY_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_FRDY_MASK)) { - uint8_t buffer[UART_FIFO_MAX_LEN]; - uint8_t len = UART_ReceiveData(handle->id, buffer, UART_FIFO_MAX_LEN); - - if (len) { - handle->parent.callback(&handle->parent, &buffer[0], len, UART_EVENT_RX_FIFO); - } - } - - /* Rx time-out interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_RTO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_RTO_MASK)) { - BL_WR_REG(UARTx, UART_INT_CLEAR, 0x10); - uint8_t buffer[UART_FIFO_MAX_LEN]; - uint8_t len = UART_ReceiveData(handle->id, buffer, UART_FIFO_MAX_LEN); - - if (len) { - handle->parent.callback(&handle->parent, &buffer[0], len, UART_EVENT_RTO); - } - } - - /* Rx parity check error interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_PCE_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_PCE_MASK)) { - BL_WR_REG(UARTx, UART_INT_CLEAR, 0x20); - handle->parent.callback(&handle->parent, NULL, 0, UART_PCE_IT); - } - - /* Tx fifo overflow/underflow error interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_FER_MASK)) { - handle->parent.callback(&handle->parent, NULL, 0, UART_TX_FER_IT); - } - - /* Rx fifo overflow/underflow error interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_FER_MASK)) { - handle->parent.callback(&handle->parent, NULL, 0, UART_RX_FER_IT); - } -} - -#ifdef BSP_USING_UART0 -/** - * @brief - * - */ -void UART0_IRQ(void) -{ - uart_isr(&uartx_device[UART0_INDEX]); -} -#endif -#ifdef BSP_USING_UART1 -/** - * @brief - * - */ -void UART1_IRQ(void) -{ - uart_isr(&uartx_device[UART1_INDEX]); -} -#endif -#ifdef BSP_USING_UART2 -/** - * @brief - * - */ -void UART2_IRQ(void) -{ - uart_isr(&uartx_device[UART2_INDEX]); -} -#endif -#ifdef BSP_USING_UART3 -/** - * @brief - * - */ -void UART3_IRQ(void) -{ - uart_isr(&uartx_device[UART3_INDEX]); -} -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_usb.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_usb.c deleted file mode 100644 index d0080bcf08..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_usb.c +++ /dev/null @@ -1,1291 +0,0 @@ -/** - * @file hal_usb.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#include "hal_usb.h" -#include "bl808_usb.h" -#include "bl808_glb.h" - -#ifndef CONFIG_USB_VDMA_ENABLE -#define CONFIG_USB_VDMA_ENABLE -#endif - -#ifndef CONFIG_USB_PINGPONG_ENABLE -// #define CONFIG_USB_PINGPONG_ENABLE -#endif - -#ifndef CONFIG_USB_VDMA_OUT_ENABLE -// #define CONFIG_USB_VDMA_OUT_ENABLE -#endif - -#define MIN(a, b) (((a) < (b)) ? (a) : (b)) - -#define USB_DC_LOG_WRN(a, ...) //printf(a, ##__VA_ARGS__) -#define USB_DC_LOG_DBG(a, ...) -#define USB_DC_LOG_ERR(a, ...) //printf(a, ##__VA_ARGS__) -#define USB_DC_LOG(a, ...) //printf(a, ##__VA_ARGS__) - -static uint8_t fifo_ep_map[4] = { 0, 0, 0, 0 }; - -static usb_dc_device_t usb_hs_device __attribute__((section(".RW_OCRAM_NOINIT"))); -static void USBD_IRQHandler(void); - -static uint8_t usb_ep_is_enabled(uint8_t ep) -{ - uint8_t ep_idx = USB_EP_GET_IDX(ep); - - /* Check if ep enabled */ - if ((USB_EP_DIR_IS_OUT(ep)) && - usb_hs_device.out_ep[ep_idx].ep_ena) { - return 1; - } else if ((USB_EP_DIR_IS_IN(ep)) && - usb_hs_device.in_ep[ep_idx].ep_ena) { - return 1; - } - - return 0; -} -#ifndef CONFIG_USB_VDMA_ENABLE -static int usb_dma_write(uint8_t fifo_num, const uint8_t *data, uint32_t len) -{ - uint32_t timeout = 0xffffff; - - USB_DMA_Cfg_Type dma_cfg; - - dma_cfg.dir = USB_DMA_TRANS_DIR_MEM_2_FIFO; - dma_cfg.memAddr = (uint32_t)(uintptr_t)data; - dma_cfg.length = len; - - csi_dcache_clean_range((uint32_t *)data, len); - /* dma config */ - USB_Set_DMA_Config(fifo_num, &dma_cfg); - /* dma start */ - USB_Set_DMA_Start(); - /* dma wait */ - while (1) { - if (USB_Get_Sub_Group_2_IntStatus() & USB_SUB_GROUP_2_ERROR_BIT_MUSK) { - USB_DC_LOG_ERR("dma error\r\n"); - USB_Get_Sub_Group_2_IntClear(USB_SUB_GROUP_2_ERROR_BIT_MUSK); - return -USB_DC_DMA_ERR; - } - if (USB_Get_Sub_Group_2_IntStatus() & USB_SUB_GROUP_2_CMPLT_BIT_MUSK) { - USB_Get_Sub_Group_2_IntClear(USB_SUB_GROUP_2_CMPLT_BIT_MUSK); - break; - } - timeout--; - if (!timeout) { - USB_DC_LOG_ERR("fifo%d wait free timeout\r\n", fifo_num); - return -USB_DC_EP_TIMEOUT_ERR; - } - } - USB_Reset_DMA_Accessing_Fifo(); - return 0; -} - -static int usb_dma_read(uint8_t fifo_num, const uint8_t *data, uint32_t len) -{ - uint32_t timeout = 0xffffff; - - USB_DMA_Cfg_Type dma_cfg; - - dma_cfg.dir = USB_DMA_TRANS_DIR_FIFO_2_MEM; - dma_cfg.memAddr = (uint32_t)(uintptr_t)data; - dma_cfg.length = len; - - /* dma config */ - USB_Set_DMA_Config(fifo_num, &dma_cfg); - /* dma start */ - USB_Set_DMA_Start(); - /* dma wait */ - while (1) { - if (USB_Get_Sub_Group_2_IntStatus() & USB_SUB_GROUP_2_ERROR_BIT_MUSK) { - USB_DC_LOG_ERR("dma error\r\n"); - USB_Get_Sub_Group_2_IntClear(USB_SUB_GROUP_2_ERROR_BIT_MUSK); - return -USB_DC_DMA_ERR; - } - if (USB_Get_Sub_Group_2_IntStatus() & USB_SUB_GROUP_2_CMPLT_BIT_MUSK) { - USB_Get_Sub_Group_2_IntClear(USB_SUB_GROUP_2_CMPLT_BIT_MUSK); - break; - } - timeout--; - if (!timeout) { - USB_DC_LOG_ERR("fifo%d wait free timeout\r\n", fifo_num); - return -USB_DC_EP_TIMEOUT_ERR; - } - } - USB_Reset_DMA_Accessing_Fifo(); - csi_dcache_invalid_range((uint32_t *)data, len); - return 0; -} -#else -static int usb_vdma_write(uint8_t fifo_num, const uint8_t *data, uint32_t len) -{ - uint32_t timeout = 0xffffff; - - USB_VDMA_Cfg_Type vdma_fifo_cfg; - - vdma_fifo_cfg.dir = USB_VDMA_TRANS_DIR_MEM_2_FIFO; - vdma_fifo_cfg.memAddr = (uint32_t)(uintptr_t)data; - vdma_fifo_cfg.length = len; - - csi_dcache_clean_range((uint32_t *)data, len); - - USB_Set_VDMA_Config(fifo_num, &vdma_fifo_cfg); - USB_Set_VDMA_Start(fifo_num); - - while (USB_Get_VDMA_Start(fifo_num)) { - timeout--; - if (!timeout) { - USB_DC_LOG_ERR("fifo%d wait free timeout\r\n", fifo_num); - return -USB_DC_EP_TIMEOUT_ERR; - } - } - - return 0; -} - -static int usb_vdma_read(uint8_t fifo_num, const uint8_t *data, uint32_t len) -{ - uint32_t timeout = 0xffffff; - - USB_VDMA_Cfg_Type vdma_fifo_cfg; - - vdma_fifo_cfg.dir = USB_VDMA_TRANS_DIR_FIFO_2_MEM; - vdma_fifo_cfg.memAddr = (uint32_t)(uintptr_t)data; - vdma_fifo_cfg.length = len; - USB_Set_VDMA_Config(fifo_num, &vdma_fifo_cfg); - USB_Set_VDMA_Start(fifo_num); - - while (USB_Get_VDMA_Start(fifo_num)) { - timeout--; - if (!timeout) { - USB_DC_LOG_ERR("fifo%d wait free timeout\r\n", fifo_num); - return -USB_DC_EP_TIMEOUT_ERR; - } - } - - csi_dcache_invalid_range((uint32_t *)data, len); - return 0; -} -#endif - -static uint8_t usb_get_transfer_fifo(uint8_t ep_idx) -{ - uint8_t target_fifo_id; - - if (usb_hs_device.out_ep[ep_idx].ep_cfg.ep_mps > 512 || usb_hs_device.in_ep[ep_idx].ep_cfg.ep_mps > 512) { -#ifdef CONFIG_USB_PINGPONG_ENABLE - target_fifo_id = (4 * ep_idx - 3); -#else - target_fifo_id = (2 * ep_idx - 1); -#endif - } else { -#ifdef CONFIG_USB_PINGPONG_ENABLE - target_fifo_id = (2 * ep_idx - 1); -#else - target_fifo_id = ep_idx; -#endif - } - - return target_fifo_id; -} - -/** - * @brief - * - * @param dev - * @param oflag - * @return int - */ -int usb_dc_init(void) -{ - CPU_Interrupt_Disable(USB_IRQn); - - PDS_Turn_On_USB(1); - - /* interrupt config */ - USB_Global_IntEnable(DISABLE); - - /* software reset usb */ - USB_NORMAL_Cfg_Type usbNormalCfg = { -#ifdef CONFIG_USB_HS - .forceFullSpeed = 0, -#else - .forceFullSpeed = 1, -#endif - .chipEn = 1, - .swRst = 1, - .remoteWakeupEn = 0, - .rstTimeOut = 0xFFFF - }; - USB_Set_Normal_Config(&usbNormalCfg); -#ifdef CONFIG_USB_HS - USB_SOF_Mask_Time_HighSpeed(); -#else - USB_SOF_Mask_Time_FullSpeed(); -#endif - USB_Set_Device_Address(0); - USB_Non_Ctrl_Transfer_Disable(); - - USB_Reset_FIFO(USB_FIFO_0); - USB_Reset_FIFO(USB_FIFO_1); - USB_Reset_FIFO(USB_FIFO_2); - USB_Reset_FIFO(USB_FIFO_3); - USB_Clear_CTRL_FIFO(); - - USB_Group_IntMask(USB_GRP_INT_G0, UNMASK); - USB_Group_IntMask(USB_GRP_INT_G1, UNMASK); - USB_Group_IntMask(USB_GRP_INT_G2, UNMASK); - USB_Group_IntMask(USB_GRP_INT_G3, UNMASK); - USB_Group_IntMask(USB_GRP_INT_G4, UNMASK); - - USB_Global_IntMask(USB_GLOBAL_INT_DEV, UNMASK); - USB_Global_IntMask(USB_GLOBAL_INT_OTG, MASK); - USB_Global_IntMask(USB_GLOBAL_INT_HC, MASK); - - USB_Sub_Group_IntMask(USB_INT_DMA_CMPLT | USB_INT_DMA_ERROR | USB_INT_IDLE | USB_INT_RX0BYTE | USB_INT_TX0BYTE); - USB_Sub_Group_IntMask(USB_INT_VDMA_CMPLT_CXF | USB_INT_VDMA_CMPLT_F0 | USB_INT_VDMA_CMPLT_F1 | USB_INT_VDMA_CMPLT_F2 | USB_INT_VDMA_CMPLT_F3 | - USB_INT_VDMA_ERROR_CXF | USB_INT_VDMA_ERROR_F0 | USB_INT_VDMA_ERROR_F1 | USB_INT_VDMA_ERROR_F2 | USB_INT_VDMA_ERROR_F3); - - USB_Sub_Group_IntUnmask(USB_INT_CX_SETUP | USB_INT_CX_IN | USB_INT_CX_OUT | USB_INT_CX_COMFAIL | USB_INT_CX_COMABORT); - USB_Sub_Group_IntUnmask(USB_INT_RESET | USB_INT_SUSPEND | USB_INT_RESUME | USB_INT_RX0BYTE); - - USB_Get_Sub_Group_0_IntClear(USB_SUB_GROUP_0_CX_COMABORT_BIT_MUSK); - USB_Get_Sub_Group_2_IntClear(USB_SUB_GROUP_2_RESET_BIT_MUSK | USB_SUB_GROUP_2_SUSPEND_BIT_MUSK | USB_SUB_GROUP_2_RESUME_BIT_MUSK | - USB_SUB_GROUP_2_TX0BYTE_BIT_MUSK | USB_SUB_GROUP_2_RX0BYTE_BIT_MUSK | - USB_SUB_GROUP_2_CMPLT_BIT_MUSK | USB_SUB_GROUP_2_ERROR_BIT_MUSK); - USB_Get_Sub_Group_3_IntClear(0xffffffff); //VDMA INT - USB_Get_Sub_Group_4_IntClear(USB_SUB_GROUP_4_L1_BIT_MUSK); - - /* modify ep1 ~ ep8 fifo map ,default is fifo3 */ - for (uint8_t i = USB_Endpoint_1; i <= USB_Endpoint_8; i++) { - USB_Set_FIFO_Of_Endpoint_IN(i, 15); - USB_Set_FIFO_Of_Endpoint_OUT(i, 15); - } - -#ifdef CONFIG_USB_VDMA_ENABLE - USB_Set_VDMA_Enable(); -#endif - - memset(&usb_hs_device, 0, sizeof(usb_hs_device)); - - usb_hs_device.out_ep[0].ep_ena = 1U; - usb_hs_device.in_ep[0].ep_ena = 1U; - usb_hs_device.out_ep[0].ep_cfg.ep_mps = 64; - usb_hs_device.out_ep[0].ep_cfg.ep_type = USBD_EP_TYPE_CTRL; - usb_hs_device.in_ep[0].ep_cfg.ep_mps = 64; - usb_hs_device.in_ep[0].ep_cfg.ep_type = USBD_EP_TYPE_CTRL; - - Interrupt_Handler_Register(USB_IRQn, USBD_IRQHandler); - CPU_Interrupt_Enable(USB_IRQn); - USB_SoftDetach_Disable(); - USB_Global_IntEnable(ENABLE); - - return 0; -} - -/** - * @brief Set USB device address - * - * @param[in] addr Device address - * - * @return 0 on success, negative errno code on fail. - */ -int usbd_set_address(const uint8_t addr) -{ - USB_Set_Device_Address(addr); - return 0; -} - -/** - * @brief configure and enable endpoint - * This function sets endpoint configuration according to one specified in USB - * endpoint descriptor and then enables it for data transfers. - * - * @param dev - * @param ep_cfg ep_cfg Endpoint - * @return int - */ -int usbd_ep_open(const struct usb_dc_ep_cfg *ep_cfg) -{ - uint8_t ep; - USB_FIFO_Cfg_Type fifo_cfg; - - if (!ep_cfg) { - return -1; - } - - ep = ep_cfg->ep_addr; - - uint8_t ep_idx = USB_EP_GET_IDX(ep); - - if (ep_idx > 4) { - return -1; - } - - USB_DC_LOG_DBG("%s ep %x, mps %d, type %d\r\n", __func__, ep, ep_cfg->ep_mps, ep_cfg->ep_type); - - if (ep_idx == 0) { - return 0; - } - - fifo_cfg.enable = 1; - fifo_cfg.fifoType = ep_cfg->ep_type; - fifo_cfg.epID = ep_idx; - - if (USB_EP_DIR_IS_OUT(ep)) { - fifo_cfg.dir = USB_FIFO_DIR_OUT; - usb_hs_device.out_ep[ep_idx].ep_cfg.ep_mps = ep_cfg->ep_mps; - usb_hs_device.out_ep[ep_idx].ep_cfg.ep_type = ep_cfg->ep_type; - usb_hs_device.out_ep[ep_idx].ep_ena = 1U; - - USB_Set_Endpoint_OUT_MaxPacketSize(ep_idx, ep_cfg->ep_mps); - - } else { - fifo_cfg.dir = USB_FIFO_DIR_IN; - usb_hs_device.in_ep[ep_idx].ep_cfg.ep_mps = ep_cfg->ep_mps; - usb_hs_device.in_ep[ep_idx].ep_cfg.ep_type = ep_cfg->ep_type; - usb_hs_device.in_ep[ep_idx].ep_ena = 1U; - - USB_Set_Endpoint_IN_MaxPacketSize(ep_idx, ep_cfg->ep_mps); - } - -#ifndef CONFIG_USB_PINGPONG_ENABLE - fifo_cfg.blockType = USB_FIFO_BLOCK_CNT_SINGLE_BLOCK; - - if (ep_cfg->ep_mps <= 512) { - if (ep_idx > 4) { - return -1; - } - fifo_ep_map[0] = 0x01; - fifo_ep_map[1] = 0x02; - fifo_ep_map[2] = 0x03; - fifo_ep_map[3] = 0x04; - - USB_Set_FIFO_Of_Endpoint_IN(USB_Endpoint_1, USB_FIFO_0); - USB_Set_FIFO_Of_Endpoint_OUT(USB_Endpoint_1, USB_FIFO_0); - USB_Set_FIFO_Of_Endpoint_IN(USB_Endpoint_2, USB_FIFO_1); - USB_Set_FIFO_Of_Endpoint_OUT(USB_Endpoint_2, USB_FIFO_1); - USB_Set_FIFO_Of_Endpoint_IN(USB_Endpoint_3, USB_FIFO_2); - USB_Set_FIFO_Of_Endpoint_OUT(USB_Endpoint_3, USB_FIFO_2); - USB_Set_FIFO_Of_Endpoint_IN(USB_Endpoint_4, USB_FIFO_3); - USB_Set_FIFO_Of_Endpoint_OUT(USB_Endpoint_4, USB_FIFO_3); - - fifo_cfg.blockSize = USB_FIFO_BLOCK_MAX_SIZE_512; - USB_Set_FIFO_Config(ep_idx - 1, &fifo_cfg); - - if (USB_EP_DIR_IS_OUT(ep)) { -#ifdef CONFIG_USB_VDMA_OUT_ENABLE - USB_Sub_Group_IntUnmask(1ULL << (USB_SUB_GRP3_INT_VDMA_CMPLT_F0 + (ep_idx - 1))); -#else - USB_Sub_Group_IntUnmask(1ULL << (USB_SUB_GRP1_INT_F0_OUT + 2 * (ep_idx - 1))); -#endif - } else { - USB_Sub_Group_IntUnmask(1ULL << (USB_SUB_GRP3_INT_VDMA_CMPLT_F0 + (ep_idx - 1))); - } - - if (ep_cfg->ep_type == 0x01) { - uint32_t tmpVal; - tmpVal = BL_RD_WORD(USB_BASE + USB_DEV_INMPS1_OFFSET + 0x04 * (ep_idx - 1)); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_TX_NUM_HBW_IEP1, 0); - BL_WR_WORD(USB_BASE + USB_DEV_INMPS1_OFFSET + 0x04 * (ep_idx - 1), tmpVal); - } - } else { - if (ep_idx > 2) { - return -1; - } - fifo_ep_map[0] = 0x01; - fifo_ep_map[1] = 0x01; - fifo_ep_map[2] = 0x02; - fifo_ep_map[3] = 0x02; - - USB_Set_FIFO_Of_Endpoint_IN(USB_Endpoint_1, USB_FIFO_0); - USB_Set_FIFO_Of_Endpoint_OUT(USB_Endpoint_1, USB_FIFO_0); - USB_Set_FIFO_Of_Endpoint_IN(USB_Endpoint_2, USB_FIFO_2); - USB_Set_FIFO_Of_Endpoint_OUT(USB_Endpoint_2, USB_FIFO_2); - - fifo_cfg.blockSize = USB_FIFO_BLOCK_MAX_SIZE_1024; - USB_Set_FIFO_Config(2 * ep_idx - 2, &fifo_cfg); - fifo_cfg.enable = 0; - USB_Set_FIFO_Config(2 * ep_idx - 1, &fifo_cfg); - - if (USB_EP_DIR_IS_OUT(ep)) { -#ifdef CONFIG_USB_VDMA_OUT_ENABLE - USB_Sub_Group_IntUnmask(1ULL << (USB_SUB_GRP3_INT_VDMA_CMPLT_F0 + 2 * (ep_idx - 1))); -#else - USB_Sub_Group_IntUnmask(1ULL << (USB_SUB_GRP1_INT_F0_OUT + 4 * (ep_idx - 1))); -#endif - } else { - USB_Sub_Group_IntUnmask(1ULL << (USB_SUB_GRP3_INT_VDMA_CMPLT_F0 + 2 * (ep_idx - 1))); - } - - if (ep_cfg->ep_type == 0x01) { - uint32_t tmpVal; - tmpVal = BL_RD_WORD(USB_BASE + USB_DEV_INMPS1_OFFSET + 0x04 * (ep_idx - 1)); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_TX_NUM_HBW_IEP1, 0); - BL_WR_WORD(USB_BASE + USB_DEV_INMPS1_OFFSET + 0x04 * (ep_idx - 1), tmpVal); - } - } -#else - fifo_cfg.blockType = USB_FIFO_BLOCK_CNT_DOUBLE_BLOCKS; - - if (ep_cfg->ep_mps <= 512) { - if (ep_idx > 2) { - return -1; - } - fifo_ep_map[0] = 0x01; - fifo_ep_map[1] = 0x01; - fifo_ep_map[2] = 0x02; - fifo_ep_map[3] = 0x02; - - USB_Set_FIFO_Of_Endpoint_IN(USB_Endpoint_1, USB_FIFO_0); - USB_Set_FIFO_Of_Endpoint_OUT(USB_Endpoint_1, USB_FIFO_0); - USB_Set_FIFO_Of_Endpoint_IN(USB_Endpoint_2, USB_FIFO_2); - USB_Set_FIFO_Of_Endpoint_OUT(USB_Endpoint_2, USB_FIFO_2); - - fifo_cfg.blockSize = USB_FIFO_BLOCK_MAX_SIZE_512; - USB_Set_FIFO_Config(2 * ep_idx - 2, &fifo_cfg); - fifo_cfg.enable = 0; - USB_Set_FIFO_Config(2 * ep_idx - 1, &fifo_cfg); - - if (USB_EP_DIR_IS_OUT(ep)) { -#ifdef CONFIG_USB_VDMA_OUT_ENABLE - USB_Sub_Group_IntUnmask(1ULL << (USB_SUB_GRP3_INT_VDMA_CMPLT_F0 + 2 * (ep_idx - 1))); -#else - USB_Sub_Group_IntUnmask(1ULL << (USB_SUB_GRP1_INT_F0_OUT + 4 * (ep_idx - 1))); -#endif - } else { - USB_Sub_Group_IntUnmask(1ULL << (USB_SUB_GRP3_INT_VDMA_CMPLT_F0 + 2 * (ep_idx - 1))); - } - } else { - if (ep_idx > 1) { - return -1; - } - - fifo_ep_map[0] = 0x01; - fifo_ep_map[1] = 0x01; - fifo_ep_map[2] = 0x01; - fifo_ep_map[3] = 0x01; - - USB_Set_FIFO_Of_Endpoint_IN(USB_Endpoint_1, USB_FIFO_0); - USB_Set_FIFO_Of_Endpoint_OUT(USB_Endpoint_1, USB_FIFO_0); - - fifo_cfg.blockSize = USB_FIFO_BLOCK_MAX_SIZE_1024; - USB_Set_FIFO_Config(2 * ep_idx - 2, &fifo_cfg); - fifo_cfg.enable = 0; - USB_Set_FIFO_Config(2 * ep_idx - 1, &fifo_cfg); - USB_Set_FIFO_Config(2 * ep_idx, &fifo_cfg); - USB_Set_FIFO_Config(2 * ep_idx + 1, &fifo_cfg); - - if (USB_EP_DIR_IS_OUT(ep)) { -#ifdef CONFIG_USB_VDMA_OUT_ENABLE - USB_Sub_Group_IntUnmask(1ULL << (USB_SUB_GRP3_INT_VDMA_CMPLT_F0)); -#else - USB_Sub_Group_IntUnmask(1ULL << (USB_SUB_GRP1_INT_F0_OUT)); -#endif - } else { - USB_Sub_Group_IntUnmask(1ULL << (USB_SUB_GRP3_INT_VDMA_CMPLT_F0)); - } - } -#endif - - USB_Non_Ctrl_Transfer_Enable(); - - return 0; -} - -/** - * @brief Disable the selected endpoint - * - * Function to disable the selected endpoint. Upon success interrupts are - * disabled for the corresponding endpoint and the endpoint is no longer able - * for transmitting/receiving data. - * - * @param[in] ep Endpoint address corresponding to the one - * listed in the device configuration table - * - * @return 0 on success, negative errno code on fail. - */ -int usbd_ep_close(const uint8_t ep) -{ - return 0; -} -/** - * @brief Set stall condition for the selected endpoint - * - * @param[in] ep Endpoint address corresponding to the one - * listed in the device configuration table - * - * @return 0 on success, negative errno code on fail. - */ -int usbd_ep_set_stall(const uint8_t ep) -{ - uint8_t ep_idx = USB_EP_GET_IDX(ep); - - if (USB_EP_DIR_IS_OUT(ep)) { - if (ep_idx == 0) { - USB_Set_CTRL_Endpoint_Stall_Once(); - } else { - USB_Set_Endpoint_OUT_Stall(ep_idx, ENABLE); - usb_hs_device.out_ep[ep_idx].is_stalled = 1U; - } - } else { - if (ep_idx == 0) { - USB_Set_CTRL_Endpoint_Stall_Once(); - } else { - USB_Set_Endpoint_IN_Stall(ep_idx, ENABLE); - usb_hs_device.in_ep[ep_idx].is_stalled = 1U; - } - } - return 0; -} -/** - * @brief Clear stall condition for the selected endpoint - * - * @param[in] ep Endpoint address corresponding to the one - * listed in the device configuration table - * - * @return 0 on success, negative errno code on fail. - */ -int usbd_ep_clear_stall(const uint8_t ep) -{ - uint8_t ep_idx = USB_EP_GET_IDX(ep); - - if (ep_idx) { - if (USB_EP_DIR_IS_OUT(ep)) { - USB_Reset_Endpoint_OUT_Data_Toggle_Sequence(ep_idx); - USB_Set_Endpoint_OUT_Stall(ep_idx, DISABLE); - usb_hs_device.out_ep[ep_idx].is_stalled = 0; - } else { - USB_Reset_Endpoint_IN_Data_Toggle_Sequence(ep_idx); - USB_Set_Endpoint_IN_Stall(ep_idx, DISABLE); - usb_hs_device.in_ep[ep_idx].is_stalled = 0; - } - } - return 0; -} -/** - * @brief Check if the selected endpoint is stalled - * - * @param dev usb device - * @param[in] ep Endpoint address corresponding to the one - * listed in the device configuration table - * @param[out] stalled Endpoint stall status - * - * @return 0 on success, negative errno code on fail. - */ -int usbd_ep_is_stalled(const uint8_t ep, uint8_t *stalled) -{ - uint8_t ep_idx = USB_EP_GET_IDX(ep); - - if (!stalled) { - return -1; - } - *stalled = 0U; - if (ep_idx == 0) - return 0; - - if (USB_EP_DIR_IS_OUT(ep)) { - if (usb_hs_device.out_ep[ep_idx].is_stalled) { - *stalled = 1U; - } - } else { - if (usb_hs_device.in_ep[ep_idx].is_stalled) { - *stalled = 1U; - } - } - - return 0; -} - -/** - * @brief Write data to the specified endpoint - * - * This function is called to write data to the specified endpoint. The - * supplied usbd_endpoint_callback function will be called when data is transmitted - * out. - * - * @param dev - * @param[in] ep Endpoint address corresponding to the one - * listed in the device configuration table - * @param[in] data Pointer to data to write - * @param[in] data_len Length of the data requested to write. This may - * be zero for a zero length status packet. - * @param[out] ret_bytes Bytes scheduled for transmission. This value - * may be NULL if the application expects all - * bytes to be written - * - * @return 0 on success, negative errno code on fail. - */ -int usbd_ep_write(const uint8_t ep, const uint8_t *data, uint32_t data_len, uint32_t *ret_bytes) -{ - uint32_t timeout = 0xffffff; - uint32_t target_fifo_id = 0; - uint8_t mps_over_flag = 0; - uint8_t ep_idx = USB_EP_GET_IDX(ep); - int ret = 0; - /* Check if IN ep */ - if (USB_EP_GET_DIR(ep) != USB_EP_DIR_IN) { - return -USB_DC_EP_DIR_ERR; - } - - /* Check if ep enabled */ - if (!usb_ep_is_enabled(ep)) { - return -USB_DC_EP_EN_ERR; - } - - if (!data && data_len) { - USB_DC_LOG_ERR("data is null\r\n"); - return -USB_DC_ADDR_ERR; - } - - if (ep_idx == 0) { - if (!data_len) { - /* enable ep0 transfer */ - USB_CTRL_Endpoint_Data_Transfer_Done(); - return USB_DC_OK; - } - if (data_len > usb_hs_device.in_ep[ep_idx].ep_cfg.ep_mps) { - /* Check if transfer len is too big */ - data_len = usb_hs_device.in_ep[ep_idx].ep_cfg.ep_mps; - mps_over_flag = 1; - } - -#ifdef CONFIG_USB_VDMA_ENABLE - ret = usb_vdma_write(0, data, data_len); -#else - ret = usb_dma_write(0, data, data_len); -#endif - if (ret < 0) { - return ret; - } - if (!mps_over_flag) { - USB_CTRL_Endpoint_Data_Transfer_Done(); - } - - } else { - if (!data_len) { - /* send zlp */ - USB_Endpoint_Transmit_Zero_Length_Packet(ep_idx); - while (1) { - if (USB_Is_Endpoint_Transfer_Zero_Length_Packet(ep_idx)) { - USB_Clear_Endpoint_Transfer_Zero_Length_Packet_Status(ep_idx); - break; - } - timeout--; - if (!timeout) { - USB_DC_LOG_ERR("ep%d wait free timeout\r\n", ep); - return -USB_DC_EP_TIMEOUT_ERR; - } - } - return USB_DC_OK; - } - - target_fifo_id = usb_get_transfer_fifo(ep_idx); -#ifdef CONFIG_USB_VDMA_ENABLE - ret = usb_vdma_write(target_fifo_id, data, data_len); -#else - ret = usb_dma_write(target_fifo_id, data, data_len); -#endif - if (ret < 0) { - return ret; - } - } - - USB_DC_LOG_DBG("EP%d write %u bytes\r\n", ep_idx, data_len); - - if (ret_bytes) { - *ret_bytes = data_len; - } - - return USB_DC_OK; -} - -/** - * @brief Read data from the specified endpoint - * - * This function is called by the endpoint handler function, after an OUT - * interrupt has been received for that EP. The application must only call this - * function through the supplied usbd_ep_callback function. This function clears - * the ENDPOINT NAK when max_data_len is 0, if all data in the endpoint FIFO has been read, - * so as to accept more data from host. - * - * @param[in] ep Endpoint address corresponding to the one - * listed in the device configuration table - * @param[in] data Pointer to data buffer to write to - * @param[in] max_data_len Max length of data to read - * @param[out] read_bytes Number of bytes read. If data is NULL and - * max_data_len is 0 the number of bytes - * available for read should be returned. - * - * @return 0 on success, negative errno code on fail. - */ -int usbd_ep_read(const uint8_t ep, uint8_t *data, uint32_t data_len, uint32_t *read_bytes) -{ - uint32_t read_len = 0; - uint32_t target_fifo_id = 0; - uint8_t ep_idx = USB_EP_GET_IDX(ep); - int ret = 0; - - /* Check if OUT ep */ - if (USB_EP_GET_DIR(ep) != USB_EP_DIR_OUT) { - USB_DC_LOG_ERR("Wrong endpoint direction\r\n"); - return -USB_DC_EP_DIR_ERR; - } - - /* Check if ep enabled */ - if (!usb_ep_is_enabled(ep)) { - USB_DC_LOG_ERR("Not enabled endpoint\r\n"); - return -USB_DC_EP_EN_ERR; - } - - if (!data && data_len) { - USB_DC_LOG_ERR("data is null\r\n"); - return -USB_DC_ADDR_ERR; - } - - /* Allow to read 0 bytes */ - if (!data_len) { - // if (ep_idx) { - // target_fifo_id = usb_get_transfer_fifo(ep_idx); - // uint32_t tmp = BL_RD_WORD(USB_BASE + USB_DEV_MISG1_OFFSET); - // tmp &= ~(1 << (2 * (target_fifo_id - 1))); - // BL_WR_WORD(USB_BASE + USB_DEV_MISG1_OFFSET, tmp); - // } - return USB_DC_OK; - } - - if (ep_idx == 0) { - /*setup handler*/ - if ((data_len == 8) && !read_bytes) { - USB_Get_Setup_Command((uint32_t *)data); - return USB_DC_OK; - } else { - read_len = BL_GET_REG_BITS_VAL(BL_RD_REG(USB_BASE, USB_DEV_CXCFE), USB_CX_FNT); -#if defined(CONFIG_USB_VDMA_ENABLE) - ret = usb_vdma_read(0, data, read_len); -#else - ret = usb_dma_read(0, data, read_len); -#endif - if (ret < 0) { - return ret; - } - } - } else { - target_fifo_id = usb_get_transfer_fifo(ep_idx); - read_len = USB_Get_OUT_FIFO_Count(target_fifo_id - 1); - if (read_len == 0) { - if (read_bytes) { - *read_bytes = 0; - } - return 0; - } -#ifdef CONFIG_USB_VDMA_ENABLE - ret = usb_vdma_read(target_fifo_id, data, read_len); -#else - ret = usb_dma_read(target_fifo_id, data, read_len); -#endif - if (ret < 0) { - return ret; - } - } - if (read_bytes) { - *read_bytes = read_len; - } - USB_DC_LOG_DBG("Read EP%d, req %d, read %d bytes\r\n", ep, data_len, *read_bytes); - - return USB_DC_OK; -} - -int usbd_ep_write_async(const uint8_t ep, const uint8_t *data, uint32_t data_len) -{ - uint32_t target_fifo_id = 0; - uint8_t ep_idx = USB_EP_GET_IDX(ep); - - /* Check if IN ep */ - if (USB_EP_GET_DIR(ep) != USB_EP_DIR_IN) { - return -USB_DC_EP_DIR_ERR; - } - - /* Check if ep enabled */ - if (!usb_ep_is_enabled(ep)) { - return -USB_DC_EP_EN_ERR; - } - - if (!data && data_len) { - USB_DC_LOG_ERR("data is null\r\n"); - return -USB_DC_ADDR_ERR; - } - - target_fifo_id = usb_get_transfer_fifo(ep_idx); - - USB_VDMA_Cfg_Type vdma_fifo_cfg; - - vdma_fifo_cfg.dir = USB_VDMA_TRANS_DIR_MEM_2_FIFO; - vdma_fifo_cfg.memAddr = (uint32_t)(uintptr_t)data; - vdma_fifo_cfg.length = data_len; - - USB_Set_VDMA_Config(target_fifo_id, &vdma_fifo_cfg); - USB_Set_VDMA_Start(target_fifo_id); - - return 0; -} - -int usbd_ep_read_async(const uint8_t ep, uint8_t *data, uint32_t data_len) -{ - uint32_t target_fifo_id = 0; - uint8_t ep_idx = USB_EP_GET_IDX(ep); - - /* Check if IN ep */ - if (USB_EP_GET_DIR(ep) != USB_EP_DIR_OUT) { - return -USB_DC_EP_DIR_ERR; - } - - /* Check if ep enabled */ - if (!usb_ep_is_enabled(ep)) { - return -USB_DC_EP_EN_ERR; - } - - if (!data && data_len) { - USB_DC_LOG_ERR("data is null\r\n"); - return -USB_DC_ADDR_ERR; - } - - target_fifo_id = usb_get_transfer_fifo(ep_idx); - - USB_VDMA_Cfg_Type vdma_fifo_cfg; - - vdma_fifo_cfg.dir = USB_VDMA_TRANS_DIR_FIFO_2_MEM; - vdma_fifo_cfg.memAddr = (uint32_t)(uintptr_t)data; - vdma_fifo_cfg.length = data_len; - - USB_Set_VDMA_Config(target_fifo_id, &vdma_fifo_cfg); - USB_Set_VDMA_Start(target_fifo_id); - - return 0; -} - -extern void usbd_event_notify_handler(uint8_t event, void *arg); - -static void usb_group0_isr(void) -{ - uint32_t group0intstatus = USB_Get_Sub_Group_0_IntStatus() & ~USB_Get_Sub_Group_0_IntMask(); - - if (group0intstatus & USB_SUB_GROUP_0_CX_COMABORT_BIT_MUSK) { - /* CX_COMABT_INT */ - USB_DC_LOG_ERR("CX COMABT\r\n"); - USB_Get_Sub_Group_0_IntClear(USB_SUB_GROUP_0_CX_COMABORT_BIT_MUSK); - return; - } - if (group0intstatus & USB_SUB_GROUP_0_CX_COMFAIL_BIT_MUSK) { - /* CX_COMFAIL_INT */ - USB_DC_LOG_ERR("CX COMFAIL\r\n"); - return; - } - if (group0intstatus & USB_SUB_GROUP_0_CX_OUT_BIT_MUSK) { - /* CX_OUT_INT */ - usbd_event_notify_handler(USB_DC_EVENT_EP0_OUT_NOTIFY, NULL); - return; - } - if (group0intstatus & USB_SUB_GROUP_0_CX_IN_BIT_MUSK) { - /* CX_IN_INT */ - usbd_event_notify_handler(USB_DC_EVENT_EP0_IN_NOTIFY, NULL); - return; - } - if (group0intstatus & USB_SUB_GROUP_0_CX_SETUP_BIT_MUSK) { - /* CX_SETUP_INT */ - usbd_event_notify_handler(USB_DC_EVENT_SETUP_NOTIFY, NULL); - return; - } -} -static void usb_group1_isr(void) -{ - uint32_t group1intstatus = USB_Get_Sub_Group_1_IntStatus() & ~USB_Get_Sub_Group_1_IntMask(); - - if (group1intstatus & USB_SUB_GROUP_1_F0_OUT_BIT_MUSK) { - /* F0_OUT_INT */ - //BL_WR_WORD(USB_BASE + USB_DEV_MISG1_OFFSET, BL_RD_WORD(USB_BASE + USB_DEV_MISG1_OFFSET) | (1 << 0)); - usbd_event_notify_handler(USB_DC_EVENT_EP_OUT_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[0] & 0x7f)); - } - - if (group1intstatus & USB_SUB_GROUP_1_F1_OUT_BIT_MUSK) { - /* F1_OUT_INT */ - //BL_WR_WORD(USB_BASE + USB_DEV_MISG1_OFFSET, BL_RD_WORD(USB_BASE + USB_DEV_MISG1_OFFSET) | (1 << 2)); - usbd_event_notify_handler(USB_DC_EVENT_EP_OUT_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[1] & 0x7f)); - } - - if (group1intstatus & USB_SUB_GROUP_1_F2_OUT_BIT_MUSK) { - /* F2_OUT_INT */ - //BL_WR_WORD(USB_BASE + USB_DEV_MISG1_OFFSET, BL_RD_WORD(USB_BASE + USB_DEV_MISG1_OFFSET) | (1 << 4)); - usbd_event_notify_handler(USB_DC_EVENT_EP_OUT_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[2] & 0x7f)); - } - - if (group1intstatus & USB_SUB_GROUP_1_F3_OUT_BIT_MUSK) { - /* F3_OUT_INT */ - //BL_WR_WORD(USB_BASE + USB_DEV_MISG1_OFFSET, BL_RD_WORD(USB_BASE + USB_DEV_MISG1_OFFSET) | (1 << 6)); - usbd_event_notify_handler(USB_DC_EVENT_EP_OUT_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[3] & 0x7f)); - } - - if (group1intstatus & USB_SUB_GROUP_1_F0_IN_BIT_MUSK) { - /* F0_IN_INT */ - usbd_event_notify_handler(USB_DC_EVENT_EP_IN_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[0] | 0x80)); - } - - if (group1intstatus & USB_SUB_GROUP_1_F1_IN_BIT_MUSK) { - /* F1_IN_INT */ - usbd_event_notify_handler(USB_DC_EVENT_EP_IN_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[1] | 0x80)); - } - - if (group1intstatus & USB_SUB_GROUP_1_F2_IN_BIT_MUSK) { - /* F2_IN_INT */ - usbd_event_notify_handler(USB_DC_EVENT_EP_IN_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[2] | 0x80)); - } - - if (group1intstatus & USB_SUB_GROUP_1_F3_IN_BIT_MUSK) { - /* F3_IN_INT */ - usbd_event_notify_handler(USB_DC_EVENT_EP_IN_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[3] | 0x80)); - } -} -static void usb_group2_isr(void) -{ - uint32_t group2intstatus = USB_Get_Sub_Group_2_IntStatus() & ~USB_Get_Sub_Group_2_IntMask(); - - if (group2intstatus & USB_SUB_GROUP_2_WAKEUP_BY_VBUS_BIT_MUSK) { - /* Dev_Wakeup_byVBUS */ - return; - } - if (group2intstatus & USB_SUB_GROUP_2_IDLE_BIT_MUSK) { - /* Dev_Idle(HOV) */ - return; - } - if (group2intstatus & USB_SUB_GROUP_2_ERROR_BIT_MUSK) { - /* DMA_ERROR(HOV) */ - USB_Get_Sub_Group_2_IntClear(USB_SUB_GROUP_2_ERROR_BIT_MUSK); - return; - } - if (group2intstatus & USB_SUB_GROUP_2_CMPLT_BIT_MUSK) { - /* DMA_CMPLT(HOV) */ - USB_Get_Sub_Group_2_IntClear(USB_SUB_GROUP_2_CMPLT_BIT_MUSK); - return; - } - if (group2intstatus & USB_SUB_GROUP_2_RX0BYTE_BIT_MUSK) { - /* RX0BYTE_INT */ - USB_Get_Sub_Group_2_IntClear(USB_SUB_GROUP_2_RX0BYTE_BIT_MUSK); - for (uint32_t i = USB_Endpoint_1; i <= USB_Endpoint_8; i++) { - if (USB_Is_Endpoint_Receive_Zero_Length_Packet(i)) - USB_Clear_Endpoint_Receive_Zero_Length_Packet_Status(i); - } - return; - } - if (group2intstatus & USB_SUB_GROUP_2_TX0BYTE_BIT_MUSK) { - /* TX0BYTE_INT */ - USB_Get_Sub_Group_2_IntClear(USB_SUB_GROUP_2_TX0BYTE_BIT_MUSK); - for (uint32_t i = USB_Endpoint_1; i <= USB_Endpoint_8; i++) { - if (USB_Is_Endpoint_Transfer_Zero_Length_Packet(i)) - USB_Clear_Endpoint_Transfer_Zero_Length_Packet_Status(i); - } - return; - } - if (group2intstatus & USB_SUB_GROUP_2_RESUME_BIT_MUSK) { - /* RESM_INT */ - USB_Get_Sub_Group_2_IntClear(USB_SUB_GROUP_2_RESUME_BIT_MUSK); - usbd_event_notify_handler(USB_DC_EVENT_RESUME, NULL); - return; - } - if (group2intstatus & USB_SUB_GROUP_2_SUSPEND_BIT_MUSK) { - /* SUSP_INT */ - USB_Get_Sub_Group_2_IntClear(USB_SUB_GROUP_2_SUSPEND_BIT_MUSK); - usbd_event_notify_handler(USB_DC_EVENT_SUSPEND, NULL); - return; - } - if (group2intstatus & USB_SUB_GROUP_2_RESET_BIT_MUSK) { - /* USBRST_INT */ - USB_Get_Sub_Group_2_IntClear(USB_SUB_GROUP_2_RESET_BIT_MUSK); - USB_Non_Ctrl_Transfer_Disable(); - USB_Reset_FIFO(USB_FIFO_0); - USB_Reset_FIFO(USB_FIFO_1); - USB_Reset_FIFO(USB_FIFO_2); - USB_Reset_FIFO(USB_FIFO_3); - USB_Clear_CTRL_FIFO(); - -#ifdef CONFIG_USB_HS - USB_SOF_Mask_Time_HighSpeed(); -#else - USB_SOF_Mask_Time_FullSpeed(); -#endif - usbd_event_notify_handler(USB_DC_EVENT_RESET, NULL); - return; - } -} -#ifdef CONFIG_USB_VDMA_ENABLE -static void usb_group3_isr(void) -{ - uint32_t group3intstatus = USB_Get_Sub_Group_3_IntStatus() & ~USB_Get_Sub_Group_3_IntMask(); - - if (group3intstatus & USB_SUB_GROUP_3_VDMA_CMPLT_CXF_BIT_MUSK) { - /* VDMA_CMPLT_CXF */ - USB_Get_Sub_Group_3_IntClear(USB_SUB_GROUP_3_VDMA_CMPLT_CXF_BIT_MUSK); - } - - if (group3intstatus & USB_SUB_GROUP_3_VDMA_CMPLT_F0_BIT_MUSK) { - /* VDMA_CMPLT_F0 */ - USB_Get_Sub_Group_3_IntClear(USB_SUB_GROUP_3_VDMA_CMPLT_F0_BIT_MUSK); - if (usb_hs_device.in_ep[fifo_ep_map[0]].ep_ena) { - usbd_event_notify_handler(USB_DC_EVENT_EP_IN_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[0] | 0x80)); - } else if (usb_hs_device.out_ep[fifo_ep_map[0]].ep_ena) { - usbd_event_notify_handler(USB_DC_EVENT_EP_OUT_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[0] & 0x7f)); - } - } - - if (group3intstatus & USB_SUB_GROUP_3_VDMA_CMPLT_F1_BIT_MUSK) { - /* VDMA_CMPLT_F1 */ - USB_Get_Sub_Group_3_IntClear(USB_SUB_GROUP_3_VDMA_CMPLT_F1_BIT_MUSK); - if (usb_hs_device.in_ep[fifo_ep_map[1]].ep_ena) { - usbd_event_notify_handler(USB_DC_EVENT_EP_IN_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[1] | 0x80)); - } else if (usb_hs_device.out_ep[fifo_ep_map[1]].ep_ena) { - usbd_event_notify_handler(USB_DC_EVENT_EP_OUT_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[1] & 0x7f)); - } - } - - if (group3intstatus & USB_SUB_GROUP_3_VDMA_CMPLT_F2_BIT_MUSK) { - /* VDMA_CMPLT_F2 */ - USB_Get_Sub_Group_3_IntClear(USB_SUB_GROUP_3_VDMA_CMPLT_F2_BIT_MUSK); - if (usb_hs_device.in_ep[fifo_ep_map[2]].ep_ena) { - usbd_event_notify_handler(USB_DC_EVENT_EP_IN_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[2] | 0x80)); - } else if (usb_hs_device.out_ep[fifo_ep_map[2]].ep_ena) { - usbd_event_notify_handler(USB_DC_EVENT_EP_OUT_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[2] & 0x7f)); - } - } - - if (group3intstatus & USB_SUB_GROUP_3_VDMA_CMPLT_F3_BIT_MUSK) { - /* VDMA_CMPLT_F3 */ - USB_Get_Sub_Group_3_IntClear(USB_SUB_GROUP_3_VDMA_CMPLT_F3_BIT_MUSK); - if (usb_hs_device.in_ep[fifo_ep_map[3]].ep_ena) { - usbd_event_notify_handler(USB_DC_EVENT_EP_IN_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[3] | 0x80)); - } else if (usb_hs_device.out_ep[fifo_ep_map[3]].ep_ena) { - usbd_event_notify_handler(USB_DC_EVENT_EP_OUT_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[3] & 0x7f)); - } - } - - if (group3intstatus & USB_SUB_GROUP_3_VDMA_ERROR_CXF_BIT_MUSK) { - /* VDMA_ERROR_CXF */ - USB_Get_Sub_Group_3_IntClear(USB_SUB_GROUP_3_VDMA_ERROR_CXF_BIT_MUSK); - } - - if (group3intstatus & USB_SUB_GROUP_3_VDMA_ERROR_F0_BIT_MUSK) { - /* VDMA_ERROR_F0 */ - USB_Get_Sub_Group_3_IntClear(USB_SUB_GROUP_3_VDMA_ERROR_F0_BIT_MUSK); - } - - if (group3intstatus & USB_SUB_GROUP_3_VDMA_ERROR_F1_BIT_MUSK) { - /* VDMA_ERROR_F1 */ - USB_Get_Sub_Group_3_IntClear(USB_SUB_GROUP_3_VDMA_ERROR_F1_BIT_MUSK); - } - - if (group3intstatus & USB_SUB_GROUP_3_VDMA_ERROR_F2_BIT_MUSK) { - /* VDMA_ERROR_F2 */ - USB_Get_Sub_Group_3_IntClear(USB_SUB_GROUP_3_VDMA_ERROR_F2_BIT_MUSK); - } - - if (group3intstatus & USB_SUB_GROUP_3_VDMA_ERROR_F3_BIT_MUSK) { - /* VDMA_ERROR_F3 */ - USB_Get_Sub_Group_3_IntClear(USB_SUB_GROUP_3_VDMA_ERROR_F3_BIT_MUSK); - } -} -#endif -static void usb_group4_isr(void) -{ - uint32_t group4intstatus = USB_Get_Sub_Group_4_IntStatus() & ~USB_Get_Sub_Group_4_IntMask(); - - if (group4intstatus & USB_SUB_GROUP_4_L1_BIT_MUSK) { - /* L1_INT */ - USB_Get_Sub_Group_3_IntClear(USB_SUB_GROUP_4_L1_BIT_MUSK); - return; - } -} - -/** - * @brief - * - */ -void USBD_IRQHandler(void) -{ - if (USB_Global_IntStatus(USB_GLOBAL_INT_DEV)) { - /* group 0 int */ - if (USB_Group_IntStatus(USB_GRP_INT_G0)) { - usb_group0_isr(); - } - /* group 1 int */ - if (USB_Group_IntStatus(USB_GRP_INT_G1)) { - usb_group1_isr(); - } - /* group 2 int */ - if (USB_Group_IntStatus(USB_GRP_INT_G2)) { - usb_group2_isr(); - } -#ifdef CONFIG_USB_VDMA_ENABLE - /* group 3 int */ - if (USB_Group_IntStatus(USB_GRP_INT_G3)) { - usb_group3_isr(); - } -#endif - /* group 4 int */ - if (USB_Group_IntStatus(USB_GRP_INT_G4)) { - usb_group4_isr(); - } - } -} - -#ifdef USB_TEST_MODE -void usbd_set_feature(uint16_t index, uint16_t value) -{ - switch (value) { - case 0: //USB_FEATURE_ENDPOINT_HALT - //implement in usb_dc_ep_set_stall - break; - case 1: //USB_FEATURE_REMOTE_WAKEUP - { - uint32_t tmpVal; - tmpVal = BL_RD_REG(USB_BASE, USB_DEV_CTL); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_CAP_RMWAKUP); - BL_WR_REG(USB_BASE, USB_DEV_CTL, tmpVal); - } break; - case 2: //USB_FEATURE_TEST_MODE - switch (index >> 8) { - case 1: // Test_J - { - uint32_t tmpVal; - tmpVal = BL_RD_REG(USB_BASE, USB_PHY_TST); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_TST_JSTA); - BL_WR_REG(USB_BASE, USB_PHY_TST, tmpVal); - } break; - case 2: // Test_K - { - uint32_t tmpVal; - tmpVal = BL_RD_REG(USB_BASE, USB_PHY_TST); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_TST_KSTA); - BL_WR_REG(USB_BASE, USB_PHY_TST, tmpVal); - } break; - case 3: // TEST_SE0_NAK - { - uint32_t tmpVal; - tmpVal = BL_RD_REG(USB_BASE, USB_PHY_TST); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_TST_SE0NAK); - BL_WR_REG(USB_BASE, USB_PHY_TST, tmpVal); - } break; - case 4: // Test_Packet - { - uint32_t tmpVal; - tmpVal = BL_RD_REG(USB_BASE, USB_PHY_TST); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_TST_PKT); - BL_WR_REG(USB_BASE, USB_PHY_TST, tmpVal); - } break; - case 5: // Test_Force_Enable - { - uint8_t temp[53]; - uint8_t *pp; - uint8_t i; - pp = temp; - - for (i = 0; i < 9; i++) /*JKJKJKJK x 9*/ - *pp++ = 0x00; - - for (i = 0; i < 8; i++) /* 8*AA */ - *pp++ = 0xAA; - - for (i = 0; i < 8; i++) /* 8*EE */ - *pp++ = 0xEE; - - *pp++ = 0xFE; - - for (i = 0; i < 11; i++) /* 11*FF */ - *pp++ = 0xFF; - - *pp++ = 0x7F; - *pp++ = 0xBF; - *pp++ = 0xDF; - *pp++ = 0xEF; - *pp++ = 0xF7; - *pp++ = 0xFB; - *pp++ = 0xFD; - *pp++ = 0xFC; - *pp++ = 0x7E; - *pp++ = 0xBF; - *pp++ = 0xDF; - *pp++ = 0xEF; - *pp++ = 0xF7; - *pp++ = 0xFB; - *pp++ = 0xFD; - *pp++ = 0x7E; - - uint32_t tmpVal; - tmpVal = BL_RD_REG(USB_BASE, USB_DEV_CXCFE); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_TST_PKDONE); - BL_WR_REG(USB_BASE, USB_DEV_CXCFE, tmpVal); - - } break; - - default: - break; - } - break; - case 3: //USB_FEATURE_BHNPENABLE - { - uint32_t tmpVal; - tmpVal = BL_RD_REG(USB_BASE, USB_OTG_CSR); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_B_BUS_REQ); - BL_WR_REG(USB_BASE, USB_OTG_CSR, tmpVal); - - tmpVal = BL_RD_REG(USB_BASE, USB_OTG_CSR); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_B_HNP_EN); - BL_WR_REG(USB_BASE, USB_OTG_CSR, tmpVal); - } break; - case 4: //USB_FEATURE_AHNPSUPPORT - - break; - case 5: //USB_FEATURE_AALTHNPSUPPORT - - break; - - default: - break; - } -} - -void usbd_clear_feature(uint16_t index, uint16_t value) -{ - switch (value) { - case 0: //USB_FEATURE_ENDPOINT_HALT - //implement in usb_dc_ep_clear_stall - break; - case 1: //USB_FEATURE_REMOTE_WAKEUP - { - uint32_t tmpVal; - tmpVal = BL_RD_REG(USB_BASE, USB_DEV_CTL); - tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CAP_RMWAKUP); - BL_WR_REG(USB_BASE, USB_DEV_CTL, tmpVal); - } break; - - default: - break; - } -} -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/audio_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/audio_reg.h deleted file mode 100644 index e51ca2aef3..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/audio_reg.h +++ /dev/null @@ -1,6651 +0,0 @@ -/** - ****************************************************************************** - * @file audio_reg.h - * @version V1.0 - * @date 2021-07-19 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __AUDIO_REG_H__ -#define __AUDIO_REG_H__ - -#include "bl808.h" - -/* 0x0 : aud_top */ -#define AUDIO_AUD_TOP_OFFSET (0x0) -#define AUDIO_CKG_EN AUDIO_CKG_EN -#define AUDIO_CKG_EN_POS (0U) -#define AUDIO_CKG_EN_LEN (1U) -#define AUDIO_CKG_EN_MSK (((1U << AUDIO_CKG_EN_LEN) - 1) << AUDIO_CKG_EN_POS) -#define AUDIO_CKG_EN_UMSK (~(((1U << AUDIO_CKG_EN_LEN) - 1) << AUDIO_CKG_EN_POS)) -#define AUDIO_DAC_ITF_INV_SEL AUDIO_DAC_ITF_INV_SEL -#define AUDIO_DAC_ITF_INV_SEL_POS (1U) -#define AUDIO_DAC_ITF_INV_SEL_LEN (1U) -#define AUDIO_DAC_ITF_INV_SEL_MSK (((1U << AUDIO_DAC_ITF_INV_SEL_LEN) - 1) << AUDIO_DAC_ITF_INV_SEL_POS) -#define AUDIO_DAC_ITF_INV_SEL_UMSK (~(((1U << AUDIO_DAC_ITF_INV_SEL_LEN) - 1) << AUDIO_DAC_ITF_INV_SEL_POS)) -#define AUDIO_ADC_ITF_INV_SEL AUDIO_ADC_ITF_INV_SEL -#define AUDIO_ADC_ITF_INV_SEL_POS (2U) -#define AUDIO_ADC_ITF_INV_SEL_LEN (1U) -#define AUDIO_ADC_ITF_INV_SEL_MSK (((1U << AUDIO_ADC_ITF_INV_SEL_LEN) - 1) << AUDIO_ADC_ITF_INV_SEL_POS) -#define AUDIO_ADC_ITF_INV_SEL_UMSK (~(((1U << AUDIO_ADC_ITF_INV_SEL_LEN) - 1) << AUDIO_ADC_ITF_INV_SEL_POS)) -#define AUDIO_PDM_ITF_INV_SEL AUDIO_PDM_ITF_INV_SEL -#define AUDIO_PDM_ITF_INV_SEL_POS (3U) -#define AUDIO_PDM_ITF_INV_SEL_LEN (1U) -#define AUDIO_PDM_ITF_INV_SEL_MSK (((1U << AUDIO_PDM_ITF_INV_SEL_LEN) - 1) << AUDIO_PDM_ITF_INV_SEL_POS) -#define AUDIO_PDM_ITF_INV_SEL_UMSK (~(((1U << AUDIO_PDM_ITF_INV_SEL_LEN) - 1) << AUDIO_PDM_ITF_INV_SEL_POS)) -#define AUDIO_DAC_RATE AUDIO_DAC_RATE -#define AUDIO_DAC_RATE_POS (24U) -#define AUDIO_DAC_RATE_LEN (3U) -#define AUDIO_DAC_RATE_MSK (((1U << AUDIO_DAC_RATE_LEN) - 1) << AUDIO_DAC_RATE_POS) -#define AUDIO_DAC_RATE_UMSK (~(((1U << AUDIO_DAC_RATE_LEN) - 1) << AUDIO_DAC_RATE_POS)) -#define AUDIO_ADC_RATE AUDIO_ADC_RATE -#define AUDIO_ADC_RATE_POS (28U) -#define AUDIO_ADC_RATE_LEN (3U) -#define AUDIO_ADC_RATE_MSK (((1U << AUDIO_ADC_RATE_LEN) - 1) << AUDIO_ADC_RATE_POS) -#define AUDIO_ADC_RATE_UMSK (~(((1U << AUDIO_ADC_RATE_LEN) - 1) << AUDIO_ADC_RATE_POS)) - -/* 0x4 : aud_itf */ -#define AUDIO_AUD_ITF_OFFSET (0x4) -#define AUDIO_ADC_0_EN AUDIO_ADC_0_EN -#define AUDIO_ADC_0_EN_POS (0U) -#define AUDIO_ADC_0_EN_LEN (1U) -#define AUDIO_ADC_0_EN_MSK (((1U << AUDIO_ADC_0_EN_LEN) - 1) << AUDIO_ADC_0_EN_POS) -#define AUDIO_ADC_0_EN_UMSK (~(((1U << AUDIO_ADC_0_EN_LEN) - 1) << AUDIO_ADC_0_EN_POS)) -#define AUDIO_ADC_1_EN AUDIO_ADC_1_EN -#define AUDIO_ADC_1_EN_POS (1U) -#define AUDIO_ADC_1_EN_LEN (1U) -#define AUDIO_ADC_1_EN_MSK (((1U << AUDIO_ADC_1_EN_LEN) - 1) << AUDIO_ADC_1_EN_POS) -#define AUDIO_ADC_1_EN_UMSK (~(((1U << AUDIO_ADC_1_EN_LEN) - 1) << AUDIO_ADC_1_EN_POS)) -#define AUDIO_ADC_2_EN AUDIO_ADC_2_EN -#define AUDIO_ADC_2_EN_POS (2U) -#define AUDIO_ADC_2_EN_LEN (1U) -#define AUDIO_ADC_2_EN_MSK (((1U << AUDIO_ADC_2_EN_LEN) - 1) << AUDIO_ADC_2_EN_POS) -#define AUDIO_ADC_2_EN_UMSK (~(((1U << AUDIO_ADC_2_EN_LEN) - 1) << AUDIO_ADC_2_EN_POS)) -#define AUDIO_DAC_0_EN AUDIO_DAC_0_EN -#define AUDIO_DAC_0_EN_POS (3U) -#define AUDIO_DAC_0_EN_LEN (1U) -#define AUDIO_DAC_0_EN_MSK (((1U << AUDIO_DAC_0_EN_LEN) - 1) << AUDIO_DAC_0_EN_POS) -#define AUDIO_DAC_0_EN_UMSK (~(((1U << AUDIO_DAC_0_EN_LEN) - 1) << AUDIO_DAC_0_EN_POS)) -#define AUDIO_DAC_1_EN AUDIO_DAC_1_EN -#define AUDIO_DAC_1_EN_POS (4U) -#define AUDIO_DAC_1_EN_LEN (1U) -#define AUDIO_DAC_1_EN_MSK (((1U << AUDIO_DAC_1_EN_LEN) - 1) << AUDIO_DAC_1_EN_POS) -#define AUDIO_DAC_1_EN_UMSK (~(((1U << AUDIO_DAC_1_EN_LEN) - 1) << AUDIO_DAC_1_EN_POS)) -#define AUDIO_AEC_0_EN AUDIO_AEC_0_EN -#define AUDIO_AEC_0_EN_POS (5U) -#define AUDIO_AEC_0_EN_LEN (1U) -#define AUDIO_AEC_0_EN_MSK (((1U << AUDIO_AEC_0_EN_LEN) - 1) << AUDIO_AEC_0_EN_POS) -#define AUDIO_AEC_0_EN_UMSK (~(((1U << AUDIO_AEC_0_EN_LEN) - 1) << AUDIO_AEC_0_EN_POS)) -#define AUDIO_AEC_1_EN AUDIO_AEC_1_EN -#define AUDIO_AEC_1_EN_POS (6U) -#define AUDIO_AEC_1_EN_LEN (1U) -#define AUDIO_AEC_1_EN_MSK (((1U << AUDIO_AEC_1_EN_LEN) - 1) << AUDIO_AEC_1_EN_POS) -#define AUDIO_AEC_1_EN_UMSK (~(((1U << AUDIO_AEC_1_EN_LEN) - 1) << AUDIO_AEC_1_EN_POS)) -#define AUDIO_AUD_RX0_SEL AUDIO_AUD_RX0_SEL -#define AUDIO_AUD_RX0_SEL_POS (13U) -#define AUDIO_AUD_RX0_SEL_LEN (3U) -#define AUDIO_AUD_RX0_SEL_MSK (((1U << AUDIO_AUD_RX0_SEL_LEN) - 1) << AUDIO_AUD_RX0_SEL_POS) -#define AUDIO_AUD_RX0_SEL_UMSK (~(((1U << AUDIO_AUD_RX0_SEL_LEN) - 1) << AUDIO_AUD_RX0_SEL_POS)) -#define AUDIO_AUD_RX1_SEL AUDIO_AUD_RX1_SEL -#define AUDIO_AUD_RX1_SEL_POS (16U) -#define AUDIO_AUD_RX1_SEL_LEN (3U) -#define AUDIO_AUD_RX1_SEL_MSK (((1U << AUDIO_AUD_RX1_SEL_LEN) - 1) << AUDIO_AUD_RX1_SEL_POS) -#define AUDIO_AUD_RX1_SEL_UMSK (~(((1U << AUDIO_AUD_RX1_SEL_LEN) - 1) << AUDIO_AUD_RX1_SEL_POS)) -#define AUDIO_AUD_RX2_SEL AUDIO_AUD_RX2_SEL -#define AUDIO_AUD_RX2_SEL_POS (19U) -#define AUDIO_AUD_RX2_SEL_LEN (3U) -#define AUDIO_AUD_RX2_SEL_MSK (((1U << AUDIO_AUD_RX2_SEL_LEN) - 1) << AUDIO_AUD_RX2_SEL_POS) -#define AUDIO_AUD_RX2_SEL_UMSK (~(((1U << AUDIO_AUD_RX2_SEL_LEN) - 1) << AUDIO_AUD_RX2_SEL_POS)) -#define AUDIO_AUD_RX3_SEL AUDIO_AUD_RX3_SEL -#define AUDIO_AUD_RX3_SEL_POS (22U) -#define AUDIO_AUD_RX3_SEL_LEN (3U) -#define AUDIO_AUD_RX3_SEL_MSK (((1U << AUDIO_AUD_RX3_SEL_LEN) - 1) << AUDIO_AUD_RX3_SEL_POS) -#define AUDIO_AUD_RX3_SEL_UMSK (~(((1U << AUDIO_AUD_RX3_SEL_LEN) - 1) << AUDIO_AUD_RX3_SEL_POS)) -#define AUDIO_AUD_RX4_SEL AUDIO_AUD_RX4_SEL -#define AUDIO_AUD_RX4_SEL_POS (25U) -#define AUDIO_AUD_RX4_SEL_LEN (3U) -#define AUDIO_AUD_RX4_SEL_MSK (((1U << AUDIO_AUD_RX4_SEL_LEN) - 1) << AUDIO_AUD_RX4_SEL_POS) -#define AUDIO_AUD_RX4_SEL_UMSK (~(((1U << AUDIO_AUD_RX4_SEL_LEN) - 1) << AUDIO_AUD_RX4_SEL_POS)) -#define AUDIO_AUD_TX0_SEL AUDIO_AUD_TX0_SEL -#define AUDIO_AUD_TX0_SEL_POS (28U) -#define AUDIO_AUD_TX0_SEL_LEN (1U) -#define AUDIO_AUD_TX0_SEL_MSK (((1U << AUDIO_AUD_TX0_SEL_LEN) - 1) << AUDIO_AUD_TX0_SEL_POS) -#define AUDIO_AUD_TX0_SEL_UMSK (~(((1U << AUDIO_AUD_TX0_SEL_LEN) - 1) << AUDIO_AUD_TX0_SEL_POS)) -#define AUDIO_AUD_TX1_SEL AUDIO_AUD_TX1_SEL -#define AUDIO_AUD_TX1_SEL_POS (29U) -#define AUDIO_AUD_TX1_SEL_LEN (1U) -#define AUDIO_AUD_TX1_SEL_MSK (((1U << AUDIO_AUD_TX1_SEL_LEN) - 1) << AUDIO_AUD_TX1_SEL_POS) -#define AUDIO_AUD_TX1_SEL_UMSK (~(((1U << AUDIO_AUD_TX1_SEL_LEN) - 1) << AUDIO_AUD_TX1_SEL_POS)) -#define AUDIO_ADC_ITF_EN AUDIO_ADC_ITF_EN -#define AUDIO_ADC_ITF_EN_POS (30U) -#define AUDIO_ADC_ITF_EN_LEN (1U) -#define AUDIO_ADC_ITF_EN_MSK (((1U << AUDIO_ADC_ITF_EN_LEN) - 1) << AUDIO_ADC_ITF_EN_POS) -#define AUDIO_ADC_ITF_EN_UMSK (~(((1U << AUDIO_ADC_ITF_EN_LEN) - 1) << AUDIO_ADC_ITF_EN_POS)) -#define AUDIO_DAC_ITF_EN AUDIO_DAC_ITF_EN -#define AUDIO_DAC_ITF_EN_POS (31U) -#define AUDIO_DAC_ITF_EN_LEN (1U) -#define AUDIO_DAC_ITF_EN_MSK (((1U << AUDIO_DAC_ITF_EN_LEN) - 1) << AUDIO_DAC_ITF_EN_POS) -#define AUDIO_DAC_ITF_EN_UMSK (~(((1U << AUDIO_DAC_ITF_EN_LEN) - 1) << AUDIO_DAC_ITF_EN_POS)) - -/* 0x8 : adc_0 */ -#define AUDIO_ADC_0_OFFSET (0x8) -#define AUDIO_ADC_0_FIR_MODE AUDIO_ADC_0_FIR_MODE -#define AUDIO_ADC_0_FIR_MODE_POS (0U) -#define AUDIO_ADC_0_FIR_MODE_LEN (1U) -#define AUDIO_ADC_0_FIR_MODE_MSK (((1U << AUDIO_ADC_0_FIR_MODE_LEN) - 1) << AUDIO_ADC_0_FIR_MODE_POS) -#define AUDIO_ADC_0_FIR_MODE_UMSK (~(((1U << AUDIO_ADC_0_FIR_MODE_LEN) - 1) << AUDIO_ADC_0_FIR_MODE_POS)) -#define AUDIO_ADC_1_FIR_MODE AUDIO_ADC_1_FIR_MODE -#define AUDIO_ADC_1_FIR_MODE_POS (1U) -#define AUDIO_ADC_1_FIR_MODE_LEN (1U) -#define AUDIO_ADC_1_FIR_MODE_MSK (((1U << AUDIO_ADC_1_FIR_MODE_LEN) - 1) << AUDIO_ADC_1_FIR_MODE_POS) -#define AUDIO_ADC_1_FIR_MODE_UMSK (~(((1U << AUDIO_ADC_1_FIR_MODE_LEN) - 1) << AUDIO_ADC_1_FIR_MODE_POS)) -#define AUDIO_ADC_2_FIR_MODE AUDIO_ADC_2_FIR_MODE -#define AUDIO_ADC_2_FIR_MODE_POS (2U) -#define AUDIO_ADC_2_FIR_MODE_LEN (1U) -#define AUDIO_ADC_2_FIR_MODE_MSK (((1U << AUDIO_ADC_2_FIR_MODE_LEN) - 1) << AUDIO_ADC_2_FIR_MODE_POS) -#define AUDIO_ADC_2_FIR_MODE_UMSK (~(((1U << AUDIO_ADC_2_FIR_MODE_LEN) - 1) << AUDIO_ADC_2_FIR_MODE_POS)) -#define AUDIO_ADC_0_SCAL AUDIO_ADC_0_SCAL -#define AUDIO_ADC_0_SCAL_POS (3U) -#define AUDIO_ADC_0_SCAL_LEN (6U) -#define AUDIO_ADC_0_SCAL_MSK (((1U << AUDIO_ADC_0_SCAL_LEN) - 1) << AUDIO_ADC_0_SCAL_POS) -#define AUDIO_ADC_0_SCAL_UMSK (~(((1U << AUDIO_ADC_0_SCAL_LEN) - 1) << AUDIO_ADC_0_SCAL_POS)) -#define AUDIO_ADC_1_SCAL AUDIO_ADC_1_SCAL -#define AUDIO_ADC_1_SCAL_POS (9U) -#define AUDIO_ADC_1_SCAL_LEN (6U) -#define AUDIO_ADC_1_SCAL_MSK (((1U << AUDIO_ADC_1_SCAL_LEN) - 1) << AUDIO_ADC_1_SCAL_POS) -#define AUDIO_ADC_1_SCAL_UMSK (~(((1U << AUDIO_ADC_1_SCAL_LEN) - 1) << AUDIO_ADC_1_SCAL_POS)) -#define AUDIO_ADC_2_SCAL AUDIO_ADC_2_SCAL -#define AUDIO_ADC_2_SCAL_POS (15U) -#define AUDIO_ADC_2_SCAL_LEN (6U) -#define AUDIO_ADC_2_SCAL_MSK (((1U << AUDIO_ADC_2_SCAL_LEN) - 1) << AUDIO_ADC_2_SCAL_POS) -#define AUDIO_ADC_2_SCAL_UMSK (~(((1U << AUDIO_ADC_2_SCAL_LEN) - 1) << AUDIO_ADC_2_SCAL_POS)) -#define AUDIO_ADC_DITHER_DATA AUDIO_ADC_DITHER_DATA -#define AUDIO_ADC_DITHER_DATA_POS (29U) -#define AUDIO_ADC_DITHER_DATA_LEN (1U) -#define AUDIO_ADC_DITHER_DATA_MSK (((1U << AUDIO_ADC_DITHER_DATA_LEN) - 1) << AUDIO_ADC_DITHER_DATA_POS) -#define AUDIO_ADC_DITHER_DATA_UMSK (~(((1U << AUDIO_ADC_DITHER_DATA_LEN) - 1) << AUDIO_ADC_DITHER_DATA_POS)) -#define AUDIO_ADC_LFSR_MODE AUDIO_ADC_LFSR_MODE -#define AUDIO_ADC_LFSR_MODE_POS (30U) -#define AUDIO_ADC_LFSR_MODE_LEN (2U) -#define AUDIO_ADC_LFSR_MODE_MSK (((1U << AUDIO_ADC_LFSR_MODE_LEN) - 1) << AUDIO_ADC_LFSR_MODE_POS) -#define AUDIO_ADC_LFSR_MODE_UMSK (~(((1U << AUDIO_ADC_LFSR_MODE_LEN) - 1) << AUDIO_ADC_LFSR_MODE_POS)) - -/* 0xC : adc_1 */ -#define AUDIO_ADC_1_OFFSET (0xC) -#define AUDIO_ADC_0_K1 AUDIO_ADC_0_K1 -#define AUDIO_ADC_0_K1_POS (0U) -#define AUDIO_ADC_0_K1_LEN (4U) -#define AUDIO_ADC_0_K1_MSK (((1U << AUDIO_ADC_0_K1_LEN) - 1) << AUDIO_ADC_0_K1_POS) -#define AUDIO_ADC_0_K1_UMSK (~(((1U << AUDIO_ADC_0_K1_LEN) - 1) << AUDIO_ADC_0_K1_POS)) -#define AUDIO_ADC_0_K1_EN AUDIO_ADC_0_K1_EN -#define AUDIO_ADC_0_K1_EN_POS (4U) -#define AUDIO_ADC_0_K1_EN_LEN (1U) -#define AUDIO_ADC_0_K1_EN_MSK (((1U << AUDIO_ADC_0_K1_EN_LEN) - 1) << AUDIO_ADC_0_K1_EN_POS) -#define AUDIO_ADC_0_K1_EN_UMSK (~(((1U << AUDIO_ADC_0_K1_EN_LEN) - 1) << AUDIO_ADC_0_K1_EN_POS)) -#define AUDIO_ADC_0_K2 AUDIO_ADC_0_K2 -#define AUDIO_ADC_0_K2_POS (5U) -#define AUDIO_ADC_0_K2_LEN (4U) -#define AUDIO_ADC_0_K2_MSK (((1U << AUDIO_ADC_0_K2_LEN) - 1) << AUDIO_ADC_0_K2_POS) -#define AUDIO_ADC_0_K2_UMSK (~(((1U << AUDIO_ADC_0_K2_LEN) - 1) << AUDIO_ADC_0_K2_POS)) -#define AUDIO_ADC_0_K2_EN AUDIO_ADC_0_K2_EN -#define AUDIO_ADC_0_K2_EN_POS (9U) -#define AUDIO_ADC_0_K2_EN_LEN (1U) -#define AUDIO_ADC_0_K2_EN_MSK (((1U << AUDIO_ADC_0_K2_EN_LEN) - 1) << AUDIO_ADC_0_K2_EN_POS) -#define AUDIO_ADC_0_K2_EN_UMSK (~(((1U << AUDIO_ADC_0_K2_EN_LEN) - 1) << AUDIO_ADC_0_K2_EN_POS)) -#define AUDIO_ADC_1_K1 AUDIO_ADC_1_K1 -#define AUDIO_ADC_1_K1_POS (10U) -#define AUDIO_ADC_1_K1_LEN (4U) -#define AUDIO_ADC_1_K1_MSK (((1U << AUDIO_ADC_1_K1_LEN) - 1) << AUDIO_ADC_1_K1_POS) -#define AUDIO_ADC_1_K1_UMSK (~(((1U << AUDIO_ADC_1_K1_LEN) - 1) << AUDIO_ADC_1_K1_POS)) -#define AUDIO_ADC_1_K1_EN AUDIO_ADC_1_K1_EN -#define AUDIO_ADC_1_K1_EN_POS (14U) -#define AUDIO_ADC_1_K1_EN_LEN (1U) -#define AUDIO_ADC_1_K1_EN_MSK (((1U << AUDIO_ADC_1_K1_EN_LEN) - 1) << AUDIO_ADC_1_K1_EN_POS) -#define AUDIO_ADC_1_K1_EN_UMSK (~(((1U << AUDIO_ADC_1_K1_EN_LEN) - 1) << AUDIO_ADC_1_K1_EN_POS)) -#define AUDIO_ADC_1_K2 AUDIO_ADC_1_K2 -#define AUDIO_ADC_1_K2_POS (15U) -#define AUDIO_ADC_1_K2_LEN (4U) -#define AUDIO_ADC_1_K2_MSK (((1U << AUDIO_ADC_1_K2_LEN) - 1) << AUDIO_ADC_1_K2_POS) -#define AUDIO_ADC_1_K2_UMSK (~(((1U << AUDIO_ADC_1_K2_LEN) - 1) << AUDIO_ADC_1_K2_POS)) -#define AUDIO_ADC_1_K2_EN AUDIO_ADC_1_K2_EN -#define AUDIO_ADC_1_K2_EN_POS (19U) -#define AUDIO_ADC_1_K2_EN_LEN (1U) -#define AUDIO_ADC_1_K2_EN_MSK (((1U << AUDIO_ADC_1_K2_EN_LEN) - 1) << AUDIO_ADC_1_K2_EN_POS) -#define AUDIO_ADC_1_K2_EN_UMSK (~(((1U << AUDIO_ADC_1_K2_EN_LEN) - 1) << AUDIO_ADC_1_K2_EN_POS)) -#define AUDIO_ADC_2_K1 AUDIO_ADC_2_K1 -#define AUDIO_ADC_2_K1_POS (20U) -#define AUDIO_ADC_2_K1_LEN (4U) -#define AUDIO_ADC_2_K1_MSK (((1U << AUDIO_ADC_2_K1_LEN) - 1) << AUDIO_ADC_2_K1_POS) -#define AUDIO_ADC_2_K1_UMSK (~(((1U << AUDIO_ADC_2_K1_LEN) - 1) << AUDIO_ADC_2_K1_POS)) -#define AUDIO_ADC_2_K1_EN AUDIO_ADC_2_K1_EN -#define AUDIO_ADC_2_K1_EN_POS (24U) -#define AUDIO_ADC_2_K1_EN_LEN (1U) -#define AUDIO_ADC_2_K1_EN_MSK (((1U << AUDIO_ADC_2_K1_EN_LEN) - 1) << AUDIO_ADC_2_K1_EN_POS) -#define AUDIO_ADC_2_K1_EN_UMSK (~(((1U << AUDIO_ADC_2_K1_EN_LEN) - 1) << AUDIO_ADC_2_K1_EN_POS)) -#define AUDIO_ADC_2_K2 AUDIO_ADC_2_K2 -#define AUDIO_ADC_2_K2_POS (25U) -#define AUDIO_ADC_2_K2_LEN (4U) -#define AUDIO_ADC_2_K2_MSK (((1U << AUDIO_ADC_2_K2_LEN) - 1) << AUDIO_ADC_2_K2_POS) -#define AUDIO_ADC_2_K2_UMSK (~(((1U << AUDIO_ADC_2_K2_LEN) - 1) << AUDIO_ADC_2_K2_POS)) -#define AUDIO_ADC_2_K2_EN AUDIO_ADC_2_K2_EN -#define AUDIO_ADC_2_K2_EN_POS (29U) -#define AUDIO_ADC_2_K2_EN_LEN (1U) -#define AUDIO_ADC_2_K2_EN_MSK (((1U << AUDIO_ADC_2_K2_EN_LEN) - 1) << AUDIO_ADC_2_K2_EN_POS) -#define AUDIO_ADC_2_K2_EN_UMSK (~(((1U << AUDIO_ADC_2_K2_EN_LEN) - 1) << AUDIO_ADC_2_K2_EN_POS)) - -/* 0x10 : dac_0 */ -#define AUDIO_DAC_0_OFFSET (0x10) -#define AUDIO_ADC_PDM_H AUDIO_ADC_PDM_H -#define AUDIO_ADC_PDM_H_POS (0U) -#define AUDIO_ADC_PDM_H_LEN (6U) -#define AUDIO_ADC_PDM_H_MSK (((1U << AUDIO_ADC_PDM_H_LEN) - 1) << AUDIO_ADC_PDM_H_POS) -#define AUDIO_ADC_PDM_H_UMSK (~(((1U << AUDIO_ADC_PDM_H_LEN) - 1) << AUDIO_ADC_PDM_H_POS)) -#define AUDIO_ADC_PDM_L AUDIO_ADC_PDM_L -#define AUDIO_ADC_PDM_L_POS (6U) -#define AUDIO_ADC_PDM_L_LEN (6U) -#define AUDIO_ADC_PDM_L_MSK (((1U << AUDIO_ADC_PDM_L_LEN) - 1) << AUDIO_ADC_PDM_L_POS) -#define AUDIO_ADC_PDM_L_UMSK (~(((1U << AUDIO_ADC_PDM_L_LEN) - 1) << AUDIO_ADC_PDM_L_POS)) -#define AUDIO_ADC_0_SRC AUDIO_ADC_0_SRC -#define AUDIO_ADC_0_SRC_POS (12U) -#define AUDIO_ADC_0_SRC_LEN (1U) -#define AUDIO_ADC_0_SRC_MSK (((1U << AUDIO_ADC_0_SRC_LEN) - 1) << AUDIO_ADC_0_SRC_POS) -#define AUDIO_ADC_0_SRC_UMSK (~(((1U << AUDIO_ADC_0_SRC_LEN) - 1) << AUDIO_ADC_0_SRC_POS)) -#define AUDIO_ADC_0_PDM_LVL_SWAP AUDIO_ADC_0_PDM_LVL_SWAP -#define AUDIO_ADC_0_PDM_LVL_SWAP_POS (13U) -#define AUDIO_ADC_0_PDM_LVL_SWAP_LEN (1U) -#define AUDIO_ADC_0_PDM_LVL_SWAP_MSK (((1U << AUDIO_ADC_0_PDM_LVL_SWAP_LEN) - 1) << AUDIO_ADC_0_PDM_LVL_SWAP_POS) -#define AUDIO_ADC_0_PDM_LVL_SWAP_UMSK (~(((1U << AUDIO_ADC_0_PDM_LVL_SWAP_LEN) - 1) << AUDIO_ADC_0_PDM_LVL_SWAP_POS)) -#define AUDIO_ADC_0_MASH_BIT_SWAP AUDIO_ADC_0_MASH_BIT_SWAP -#define AUDIO_ADC_0_MASH_BIT_SWAP_POS (14U) -#define AUDIO_ADC_0_MASH_BIT_SWAP_LEN (1U) -#define AUDIO_ADC_0_MASH_BIT_SWAP_MSK (((1U << AUDIO_ADC_0_MASH_BIT_SWAP_LEN) - 1) << AUDIO_ADC_0_MASH_BIT_SWAP_POS) -#define AUDIO_ADC_0_MASH_BIT_SWAP_UMSK (~(((1U << AUDIO_ADC_0_MASH_BIT_SWAP_LEN) - 1) << AUDIO_ADC_0_MASH_BIT_SWAP_POS)) -#define AUDIO_ADC_1_SRC AUDIO_ADC_1_SRC -#define AUDIO_ADC_1_SRC_POS (15U) -#define AUDIO_ADC_1_SRC_LEN (1U) -#define AUDIO_ADC_1_SRC_MSK (((1U << AUDIO_ADC_1_SRC_LEN) - 1) << AUDIO_ADC_1_SRC_POS) -#define AUDIO_ADC_1_SRC_UMSK (~(((1U << AUDIO_ADC_1_SRC_LEN) - 1) << AUDIO_ADC_1_SRC_POS)) -#define AUDIO_ADC_1_PDM_LVL_SWAP AUDIO_ADC_1_PDM_LVL_SWAP -#define AUDIO_ADC_1_PDM_LVL_SWAP_POS (16U) -#define AUDIO_ADC_1_PDM_LVL_SWAP_LEN (1U) -#define AUDIO_ADC_1_PDM_LVL_SWAP_MSK (((1U << AUDIO_ADC_1_PDM_LVL_SWAP_LEN) - 1) << AUDIO_ADC_1_PDM_LVL_SWAP_POS) -#define AUDIO_ADC_1_PDM_LVL_SWAP_UMSK (~(((1U << AUDIO_ADC_1_PDM_LVL_SWAP_LEN) - 1) << AUDIO_ADC_1_PDM_LVL_SWAP_POS)) -#define AUDIO_ADC_1_MASH_BIT_SWAP AUDIO_ADC_1_MASH_BIT_SWAP -#define AUDIO_ADC_1_MASH_BIT_SWAP_POS (17U) -#define AUDIO_ADC_1_MASH_BIT_SWAP_LEN (1U) -#define AUDIO_ADC_1_MASH_BIT_SWAP_MSK (((1U << AUDIO_ADC_1_MASH_BIT_SWAP_LEN) - 1) << AUDIO_ADC_1_MASH_BIT_SWAP_POS) -#define AUDIO_ADC_1_MASH_BIT_SWAP_UMSK (~(((1U << AUDIO_ADC_1_MASH_BIT_SWAP_LEN) - 1) << AUDIO_ADC_1_MASH_BIT_SWAP_POS)) -#define AUDIO_ADC_2_SRC AUDIO_ADC_2_SRC -#define AUDIO_ADC_2_SRC_POS (18U) -#define AUDIO_ADC_2_SRC_LEN (1U) -#define AUDIO_ADC_2_SRC_MSK (((1U << AUDIO_ADC_2_SRC_LEN) - 1) << AUDIO_ADC_2_SRC_POS) -#define AUDIO_ADC_2_SRC_UMSK (~(((1U << AUDIO_ADC_2_SRC_LEN) - 1) << AUDIO_ADC_2_SRC_POS)) -#define AUDIO_ADC_2_PDM_LVL_SWAP AUDIO_ADC_2_PDM_LVL_SWAP -#define AUDIO_ADC_2_PDM_LVL_SWAP_POS (19U) -#define AUDIO_ADC_2_PDM_LVL_SWAP_LEN (1U) -#define AUDIO_ADC_2_PDM_LVL_SWAP_MSK (((1U << AUDIO_ADC_2_PDM_LVL_SWAP_LEN) - 1) << AUDIO_ADC_2_PDM_LVL_SWAP_POS) -#define AUDIO_ADC_2_PDM_LVL_SWAP_UMSK (~(((1U << AUDIO_ADC_2_PDM_LVL_SWAP_LEN) - 1) << AUDIO_ADC_2_PDM_LVL_SWAP_POS)) -#define AUDIO_ADC_2_MASH_BIT_SWAP AUDIO_ADC_2_MASH_BIT_SWAP -#define AUDIO_ADC_2_MASH_BIT_SWAP_POS (20U) -#define AUDIO_ADC_2_MASH_BIT_SWAP_LEN (1U) -#define AUDIO_ADC_2_MASH_BIT_SWAP_MSK (((1U << AUDIO_ADC_2_MASH_BIT_SWAP_LEN) - 1) << AUDIO_ADC_2_MASH_BIT_SWAP_POS) -#define AUDIO_ADC_2_MASH_BIT_SWAP_UMSK (~(((1U << AUDIO_ADC_2_MASH_BIT_SWAP_LEN) - 1) << AUDIO_ADC_2_MASH_BIT_SWAP_POS)) -#define AUDIO_MIX_0_SEL AUDIO_MIX_0_SEL -#define AUDIO_MIX_0_SEL_POS (21U) -#define AUDIO_MIX_0_SEL_LEN (2U) -#define AUDIO_MIX_0_SEL_MSK (((1U << AUDIO_MIX_0_SEL_LEN) - 1) << AUDIO_MIX_0_SEL_POS) -#define AUDIO_MIX_0_SEL_UMSK (~(((1U << AUDIO_MIX_0_SEL_LEN) - 1) << AUDIO_MIX_0_SEL_POS)) -#define AUDIO_MIX_0_MODE AUDIO_MIX_0_MODE -#define AUDIO_MIX_0_MODE_POS (23U) -#define AUDIO_MIX_0_MODE_LEN (2U) -#define AUDIO_MIX_0_MODE_MSK (((1U << AUDIO_MIX_0_MODE_LEN) - 1) << AUDIO_MIX_0_MODE_POS) -#define AUDIO_MIX_0_MODE_UMSK (~(((1U << AUDIO_MIX_0_MODE_LEN) - 1) << AUDIO_MIX_0_MODE_POS)) -#define AUDIO_MIX_0_ATT_MODE1 AUDIO_MIX_0_ATT_MODE1 -#define AUDIO_MIX_0_ATT_MODE1_POS (25U) -#define AUDIO_MIX_0_ATT_MODE1_LEN (3U) -#define AUDIO_MIX_0_ATT_MODE1_MSK (((1U << AUDIO_MIX_0_ATT_MODE1_LEN) - 1) << AUDIO_MIX_0_ATT_MODE1_POS) -#define AUDIO_MIX_0_ATT_MODE1_UMSK (~(((1U << AUDIO_MIX_0_ATT_MODE1_LEN) - 1) << AUDIO_MIX_0_ATT_MODE1_POS)) -#define AUDIO_MIX_0_ATT_MODE2 AUDIO_MIX_0_ATT_MODE2 -#define AUDIO_MIX_0_ATT_MODE2_POS (28U) -#define AUDIO_MIX_0_ATT_MODE2_LEN (3U) -#define AUDIO_MIX_0_ATT_MODE2_MSK (((1U << AUDIO_MIX_0_ATT_MODE2_LEN) - 1) << AUDIO_MIX_0_ATT_MODE2_POS) -#define AUDIO_MIX_0_ATT_MODE2_UMSK (~(((1U << AUDIO_MIX_0_ATT_MODE2_LEN) - 1) << AUDIO_MIX_0_ATT_MODE2_POS)) - -/* 0x14 : dac_1 */ -#define AUDIO_DAC_1_OFFSET (0x14) -#define AUDIO_DAC_DEM_BYPASS AUDIO_DAC_DEM_BYPASS -#define AUDIO_DAC_DEM_BYPASS_POS (0U) -#define AUDIO_DAC_DEM_BYPASS_LEN (1U) -#define AUDIO_DAC_DEM_BYPASS_MSK (((1U << AUDIO_DAC_DEM_BYPASS_LEN) - 1) << AUDIO_DAC_DEM_BYPASS_POS) -#define AUDIO_DAC_DEM_BYPASS_UMSK (~(((1U << AUDIO_DAC_DEM_BYPASS_LEN) - 1) << AUDIO_DAC_DEM_BYPASS_POS)) -#define AUDIO_DAC_DEM_OUT_SWAP AUDIO_DAC_DEM_OUT_SWAP -#define AUDIO_DAC_DEM_OUT_SWAP_POS (1U) -#define AUDIO_DAC_DEM_OUT_SWAP_LEN (1U) -#define AUDIO_DAC_DEM_OUT_SWAP_MSK (((1U << AUDIO_DAC_DEM_OUT_SWAP_LEN) - 1) << AUDIO_DAC_DEM_OUT_SWAP_POS) -#define AUDIO_DAC_DEM_OUT_SWAP_UMSK (~(((1U << AUDIO_DAC_DEM_OUT_SWAP_LEN) - 1) << AUDIO_DAC_DEM_OUT_SWAP_POS)) -#define AUDIO_DAC_DSM_ORDER AUDIO_DAC_DSM_ORDER -#define AUDIO_DAC_DSM_ORDER_POS (5U) -#define AUDIO_DAC_DSM_ORDER_LEN (1U) -#define AUDIO_DAC_DSM_ORDER_MSK (((1U << AUDIO_DAC_DSM_ORDER_LEN) - 1) << AUDIO_DAC_DSM_ORDER_POS) -#define AUDIO_DAC_DSM_ORDER_UMSK (~(((1U << AUDIO_DAC_DSM_ORDER_LEN) - 1) << AUDIO_DAC_DSM_ORDER_POS)) -#define AUDIO_DAC_DSM_SCALING_FACTOR AUDIO_DAC_DSM_SCALING_FACTOR -#define AUDIO_DAC_DSM_SCALING_FACTOR_POS (6U) -#define AUDIO_DAC_DSM_SCALING_FACTOR_LEN (4U) -#define AUDIO_DAC_DSM_SCALING_FACTOR_MSK (((1U << AUDIO_DAC_DSM_SCALING_FACTOR_LEN) - 1) << AUDIO_DAC_DSM_SCALING_FACTOR_POS) -#define AUDIO_DAC_DSM_SCALING_FACTOR_UMSK (~(((1U << AUDIO_DAC_DSM_SCALING_FACTOR_LEN) - 1) << AUDIO_DAC_DSM_SCALING_FACTOR_POS)) -#define AUDIO_DAC_DSM_SCALING_EN AUDIO_DAC_DSM_SCALING_EN -#define AUDIO_DAC_DSM_SCALING_EN_POS (10U) -#define AUDIO_DAC_DSM_SCALING_EN_LEN (1U) -#define AUDIO_DAC_DSM_SCALING_EN_MSK (((1U << AUDIO_DAC_DSM_SCALING_EN_LEN) - 1) << AUDIO_DAC_DSM_SCALING_EN_POS) -#define AUDIO_DAC_DSM_SCALING_EN_UMSK (~(((1U << AUDIO_DAC_DSM_SCALING_EN_LEN) - 1) << AUDIO_DAC_DSM_SCALING_EN_POS)) -#define AUDIO_DAC_DSM_DITHER_AMP AUDIO_DAC_DSM_DITHER_AMP -#define AUDIO_DAC_DSM_DITHER_AMP_POS (11U) -#define AUDIO_DAC_DSM_DITHER_AMP_LEN (3U) -#define AUDIO_DAC_DSM_DITHER_AMP_MSK (((1U << AUDIO_DAC_DSM_DITHER_AMP_LEN) - 1) << AUDIO_DAC_DSM_DITHER_AMP_POS) -#define AUDIO_DAC_DSM_DITHER_AMP_UMSK (~(((1U << AUDIO_DAC_DSM_DITHER_AMP_LEN) - 1) << AUDIO_DAC_DSM_DITHER_AMP_POS)) -#define AUDIO_DAC_DSM_DITHER_EN AUDIO_DAC_DSM_DITHER_EN -#define AUDIO_DAC_DSM_DITHER_EN_POS (14U) -#define AUDIO_DAC_DSM_DITHER_EN_LEN (1U) -#define AUDIO_DAC_DSM_DITHER_EN_MSK (((1U << AUDIO_DAC_DSM_DITHER_EN_LEN) - 1) << AUDIO_DAC_DSM_DITHER_EN_POS) -#define AUDIO_DAC_DSM_DITHER_EN_UMSK (~(((1U << AUDIO_DAC_DSM_DITHER_EN_LEN) - 1) << AUDIO_DAC_DSM_DITHER_EN_POS)) -#define AUDIO_DAC_DSM_DITHER_PRBS_MODE AUDIO_DAC_DSM_DITHER_PRBS_MODE -#define AUDIO_DAC_DSM_DITHER_PRBS_MODE_POS (15U) -#define AUDIO_DAC_DSM_DITHER_PRBS_MODE_LEN (2U) -#define AUDIO_DAC_DSM_DITHER_PRBS_MODE_MSK (((1U << AUDIO_DAC_DSM_DITHER_PRBS_MODE_LEN) - 1) << AUDIO_DAC_DSM_DITHER_PRBS_MODE_POS) -#define AUDIO_DAC_DSM_DITHER_PRBS_MODE_UMSK (~(((1U << AUDIO_DAC_DSM_DITHER_PRBS_MODE_LEN) - 1) << AUDIO_DAC_DSM_DITHER_PRBS_MODE_POS)) -#define AUDIO_MIX_1_SEL AUDIO_MIX_1_SEL -#define AUDIO_MIX_1_SEL_POS (21U) -#define AUDIO_MIX_1_SEL_LEN (2U) -#define AUDIO_MIX_1_SEL_MSK (((1U << AUDIO_MIX_1_SEL_LEN) - 1) << AUDIO_MIX_1_SEL_POS) -#define AUDIO_MIX_1_SEL_UMSK (~(((1U << AUDIO_MIX_1_SEL_LEN) - 1) << AUDIO_MIX_1_SEL_POS)) -#define AUDIO_MIX_1_MODE AUDIO_MIX_1_MODE -#define AUDIO_MIX_1_MODE_POS (23U) -#define AUDIO_MIX_1_MODE_LEN (2U) -#define AUDIO_MIX_1_MODE_MSK (((1U << AUDIO_MIX_1_MODE_LEN) - 1) << AUDIO_MIX_1_MODE_POS) -#define AUDIO_MIX_1_MODE_UMSK (~(((1U << AUDIO_MIX_1_MODE_LEN) - 1) << AUDIO_MIX_1_MODE_POS)) -#define AUDIO_MIX_1_ATT_MODE1 AUDIO_MIX_1_ATT_MODE1 -#define AUDIO_MIX_1_ATT_MODE1_POS (25U) -#define AUDIO_MIX_1_ATT_MODE1_LEN (3U) -#define AUDIO_MIX_1_ATT_MODE1_MSK (((1U << AUDIO_MIX_1_ATT_MODE1_LEN) - 1) << AUDIO_MIX_1_ATT_MODE1_POS) -#define AUDIO_MIX_1_ATT_MODE1_UMSK (~(((1U << AUDIO_MIX_1_ATT_MODE1_LEN) - 1) << AUDIO_MIX_1_ATT_MODE1_POS)) -#define AUDIO_MIX_1_ATT_MODE2 AUDIO_MIX_1_ATT_MODE2 -#define AUDIO_MIX_1_ATT_MODE2_POS (28U) -#define AUDIO_MIX_1_ATT_MODE2_LEN (3U) -#define AUDIO_MIX_1_ATT_MODE2_MSK (((1U << AUDIO_MIX_1_ATT_MODE2_LEN) - 1) << AUDIO_MIX_1_ATT_MODE2_POS) -#define AUDIO_MIX_1_ATT_MODE2_UMSK (~(((1U << AUDIO_MIX_1_ATT_MODE2_LEN) - 1) << AUDIO_MIX_1_ATT_MODE2_POS)) - -/* 0x18 : aec_0 */ -#define AUDIO_AEC_0_OFFSET (0x18) -#define AUDIO_AEC_0_ATTEN_MODE AUDIO_AEC_0_ATTEN_MODE -#define AUDIO_AEC_0_ATTEN_MODE_POS (5U) -#define AUDIO_AEC_0_ATTEN_MODE_LEN (3U) -#define AUDIO_AEC_0_ATTEN_MODE_MSK (((1U << AUDIO_AEC_0_ATTEN_MODE_LEN) - 1) << AUDIO_AEC_0_ATTEN_MODE_POS) -#define AUDIO_AEC_0_ATTEN_MODE_UMSK (~(((1U << AUDIO_AEC_0_ATTEN_MODE_LEN) - 1) << AUDIO_AEC_0_ATTEN_MODE_POS)) -#define AUDIO_AEC_1_ATTEN_MODE AUDIO_AEC_1_ATTEN_MODE -#define AUDIO_AEC_1_ATTEN_MODE_POS (8U) -#define AUDIO_AEC_1_ATTEN_MODE_LEN (3U) -#define AUDIO_AEC_1_ATTEN_MODE_MSK (((1U << AUDIO_AEC_1_ATTEN_MODE_LEN) - 1) << AUDIO_AEC_1_ATTEN_MODE_POS) -#define AUDIO_AEC_1_ATTEN_MODE_UMSK (~(((1U << AUDIO_AEC_1_ATTEN_MODE_LEN) - 1) << AUDIO_AEC_1_ATTEN_MODE_POS)) -#define AUDIO_AEC_RECORD_VLD_4S_DIV AUDIO_AEC_RECORD_VLD_4S_DIV -#define AUDIO_AEC_RECORD_VLD_4S_DIV_POS (11U) -#define AUDIO_AEC_RECORD_VLD_4S_DIV_LEN (2U) -#define AUDIO_AEC_RECORD_VLD_4S_DIV_MSK (((1U << AUDIO_AEC_RECORD_VLD_4S_DIV_LEN) - 1) << AUDIO_AEC_RECORD_VLD_4S_DIV_POS) -#define AUDIO_AEC_RECORD_VLD_4S_DIV_UMSK (~(((1U << AUDIO_AEC_RECORD_VLD_4S_DIV_LEN) - 1) << AUDIO_AEC_RECORD_VLD_4S_DIV_POS)) -#define AUDIO_AEC_RECORD_VLD_4S_EN AUDIO_AEC_RECORD_VLD_4S_EN -#define AUDIO_AEC_RECORD_VLD_4S_EN_POS (13U) -#define AUDIO_AEC_RECORD_VLD_4S_EN_LEN (1U) -#define AUDIO_AEC_RECORD_VLD_4S_EN_MSK (((1U << AUDIO_AEC_RECORD_VLD_4S_EN_LEN) - 1) << AUDIO_AEC_RECORD_VLD_4S_EN_POS) -#define AUDIO_AEC_RECORD_VLD_4S_EN_UMSK (~(((1U << AUDIO_AEC_RECORD_VLD_4S_EN_LEN) - 1) << AUDIO_AEC_RECORD_VLD_4S_EN_POS)) - -/* 0x1C : pdm_0 */ -#define AUDIO_PDM_0_OFFSET (0x1C) -#define AUDIO_PDM_0_EN AUDIO_PDM_0_EN -#define AUDIO_PDM_0_EN_POS (0U) -#define AUDIO_PDM_0_EN_LEN (1U) -#define AUDIO_PDM_0_EN_MSK (((1U << AUDIO_PDM_0_EN_LEN) - 1) << AUDIO_PDM_0_EN_POS) -#define AUDIO_PDM_0_EN_UMSK (~(((1U << AUDIO_PDM_0_EN_LEN) - 1) << AUDIO_PDM_0_EN_POS)) -#define AUDIO_PDM_1_EN AUDIO_PDM_1_EN -#define AUDIO_PDM_1_EN_POS (1U) -#define AUDIO_PDM_1_EN_LEN (1U) -#define AUDIO_PDM_1_EN_MSK (((1U << AUDIO_PDM_1_EN_LEN) - 1) << AUDIO_PDM_1_EN_POS) -#define AUDIO_PDM_1_EN_UMSK (~(((1U << AUDIO_PDM_1_EN_LEN) - 1) << AUDIO_PDM_1_EN_POS)) -#define AUDIO_PDM_2_EN AUDIO_PDM_2_EN -#define AUDIO_PDM_2_EN_POS (2U) -#define AUDIO_PDM_2_EN_LEN (1U) -#define AUDIO_PDM_2_EN_MSK (((1U << AUDIO_PDM_2_EN_LEN) - 1) << AUDIO_PDM_2_EN_POS) -#define AUDIO_PDM_2_EN_UMSK (~(((1U << AUDIO_PDM_2_EN_LEN) - 1) << AUDIO_PDM_2_EN_POS)) -#define AUDIO_ADC_0_PDM_SEL AUDIO_ADC_0_PDM_SEL -#define AUDIO_ADC_0_PDM_SEL_POS (3U) -#define AUDIO_ADC_0_PDM_SEL_LEN (3U) -#define AUDIO_ADC_0_PDM_SEL_MSK (((1U << AUDIO_ADC_0_PDM_SEL_LEN) - 1) << AUDIO_ADC_0_PDM_SEL_POS) -#define AUDIO_ADC_0_PDM_SEL_UMSK (~(((1U << AUDIO_ADC_0_PDM_SEL_LEN) - 1) << AUDIO_ADC_0_PDM_SEL_POS)) -#define AUDIO_ADC_1_PDM_SEL AUDIO_ADC_1_PDM_SEL -#define AUDIO_ADC_1_PDM_SEL_POS (6U) -#define AUDIO_ADC_1_PDM_SEL_LEN (3U) -#define AUDIO_ADC_1_PDM_SEL_MSK (((1U << AUDIO_ADC_1_PDM_SEL_LEN) - 1) << AUDIO_ADC_1_PDM_SEL_POS) -#define AUDIO_ADC_1_PDM_SEL_UMSK (~(((1U << AUDIO_ADC_1_PDM_SEL_LEN) - 1) << AUDIO_ADC_1_PDM_SEL_POS)) -#define AUDIO_ADC_2_PDM_SEL AUDIO_ADC_2_PDM_SEL -#define AUDIO_ADC_2_PDM_SEL_POS (9U) -#define AUDIO_ADC_2_PDM_SEL_LEN (3U) -#define AUDIO_ADC_2_PDM_SEL_MSK (((1U << AUDIO_ADC_2_PDM_SEL_LEN) - 1) << AUDIO_ADC_2_PDM_SEL_POS) -#define AUDIO_ADC_2_PDM_SEL_UMSK (~(((1U << AUDIO_ADC_2_PDM_SEL_LEN) - 1) << AUDIO_ADC_2_PDM_SEL_POS)) - -/* 0x20 : rsvd0 */ -#define AUDIO_RSVD0_OFFSET (0x20) - -/* 0x24 : dbg_0 */ -#define AUDIO_DBG_0_OFFSET (0x24) -#define AUDIO_AUD_SIN_EN AUDIO_AUD_SIN_EN -#define AUDIO_AUD_SIN_EN_POS (0U) -#define AUDIO_AUD_SIN_EN_LEN (1U) -#define AUDIO_AUD_SIN_EN_MSK (((1U << AUDIO_AUD_SIN_EN_LEN) - 1) << AUDIO_AUD_SIN_EN_POS) -#define AUDIO_AUD_SIN_EN_UMSK (~(((1U << AUDIO_AUD_SIN_EN_LEN) - 1) << AUDIO_AUD_SIN_EN_POS)) -#define AUDIO_AUD_SIN_STEP AUDIO_AUD_SIN_STEP -#define AUDIO_AUD_SIN_STEP_POS (1U) -#define AUDIO_AUD_SIN_STEP_LEN (3U) -#define AUDIO_AUD_SIN_STEP_MSK (((1U << AUDIO_AUD_SIN_STEP_LEN) - 1) << AUDIO_AUD_SIN_STEP_POS) -#define AUDIO_AUD_SIN_STEP_UMSK (~(((1U << AUDIO_AUD_SIN_STEP_LEN) - 1) << AUDIO_AUD_SIN_STEP_POS)) -#define AUDIO_TEST_OUT_SEL AUDIO_TEST_OUT_SEL -#define AUDIO_TEST_OUT_SEL_POS (18U) -#define AUDIO_TEST_OUT_SEL_LEN (2U) -#define AUDIO_TEST_OUT_SEL_MSK (((1U << AUDIO_TEST_OUT_SEL_LEN) - 1) << AUDIO_TEST_OUT_SEL_POS) -#define AUDIO_TEST_OUT_SEL_UMSK (~(((1U << AUDIO_TEST_OUT_SEL_LEN) - 1) << AUDIO_TEST_OUT_SEL_POS)) -#define AUDIO_DAC_TEST_CLKIN_EN AUDIO_DAC_TEST_CLKIN_EN -#define AUDIO_DAC_TEST_CLKIN_EN_POS (20U) -#define AUDIO_DAC_TEST_CLKIN_EN_LEN (1U) -#define AUDIO_DAC_TEST_CLKIN_EN_MSK (((1U << AUDIO_DAC_TEST_CLKIN_EN_LEN) - 1) << AUDIO_DAC_TEST_CLKIN_EN_POS) -#define AUDIO_DAC_TEST_CLKIN_EN_UMSK (~(((1U << AUDIO_DAC_TEST_CLKIN_EN_LEN) - 1) << AUDIO_DAC_TEST_CLKIN_EN_POS)) -#define AUDIO_ADC_TEST_CLKIN_EN AUDIO_ADC_TEST_CLKIN_EN -#define AUDIO_ADC_TEST_CLKIN_EN_POS (21U) -#define AUDIO_ADC_TEST_CLKIN_EN_LEN (1U) -#define AUDIO_ADC_TEST_CLKIN_EN_MSK (((1U << AUDIO_ADC_TEST_CLKIN_EN_LEN) - 1) << AUDIO_ADC_TEST_CLKIN_EN_POS) -#define AUDIO_ADC_TEST_CLKIN_EN_UMSK (~(((1U << AUDIO_ADC_TEST_CLKIN_EN_LEN) - 1) << AUDIO_ADC_TEST_CLKIN_EN_POS)) -#define AUDIO_DAC_TEST_DIN_EN AUDIO_DAC_TEST_DIN_EN -#define AUDIO_DAC_TEST_DIN_EN_POS (22U) -#define AUDIO_DAC_TEST_DIN_EN_LEN (1U) -#define AUDIO_DAC_TEST_DIN_EN_MSK (((1U << AUDIO_DAC_TEST_DIN_EN_LEN) - 1) << AUDIO_DAC_TEST_DIN_EN_POS) -#define AUDIO_DAC_TEST_DIN_EN_UMSK (~(((1U << AUDIO_DAC_TEST_DIN_EN_LEN) - 1) << AUDIO_DAC_TEST_DIN_EN_POS)) -#define AUDIO_ADC_TEST_DIN_EN AUDIO_ADC_TEST_DIN_EN -#define AUDIO_ADC_TEST_DIN_EN_POS (23U) -#define AUDIO_ADC_TEST_DIN_EN_LEN (1U) -#define AUDIO_ADC_TEST_DIN_EN_MSK (((1U << AUDIO_ADC_TEST_DIN_EN_LEN) - 1) << AUDIO_ADC_TEST_DIN_EN_POS) -#define AUDIO_ADC_TEST_DIN_EN_UMSK (~(((1U << AUDIO_ADC_TEST_DIN_EN_LEN) - 1) << AUDIO_ADC_TEST_DIN_EN_POS)) -#define AUDIO_AUD_TEST_READ_SEL AUDIO_AUD_TEST_READ_SEL -#define AUDIO_AUD_TEST_READ_SEL_POS (24U) -#define AUDIO_AUD_TEST_READ_SEL_LEN (6U) -#define AUDIO_AUD_TEST_READ_SEL_MSK (((1U << AUDIO_AUD_TEST_READ_SEL_LEN) - 1) << AUDIO_AUD_TEST_READ_SEL_POS) -#define AUDIO_AUD_TEST_READ_SEL_UMSK (~(((1U << AUDIO_AUD_TEST_READ_SEL_LEN) - 1) << AUDIO_AUD_TEST_READ_SEL_POS)) - -/* 0x28 : dbg_1 */ -#define AUDIO_DBG_1_OFFSET (0x28) -#define AUDIO_AUD_TEST_READ AUDIO_AUD_TEST_READ -#define AUDIO_AUD_TEST_READ_POS (0U) -#define AUDIO_AUD_TEST_READ_LEN (32U) -#define AUDIO_AUD_TEST_READ_MSK (((1U << AUDIO_AUD_TEST_READ_LEN) - 1) << AUDIO_AUD_TEST_READ_POS) -#define AUDIO_AUD_TEST_READ_UMSK (~(((1U << AUDIO_AUD_TEST_READ_LEN) - 1) << AUDIO_AUD_TEST_READ_POS)) - -/* 0x2C : dbg_2 */ -#define AUDIO_DBG_2_OFFSET (0x2C) -#define AUDIO_ADC_FIR_4S_VAL AUDIO_ADC_FIR_4S_VAL -#define AUDIO_ADC_FIR_4S_VAL_POS (0U) -#define AUDIO_ADC_FIR_4S_VAL_LEN (20U) -#define AUDIO_ADC_FIR_4S_VAL_MSK (((1U << AUDIO_ADC_FIR_4S_VAL_LEN) - 1) << AUDIO_ADC_FIR_4S_VAL_POS) -#define AUDIO_ADC_FIR_4S_VAL_UMSK (~(((1U << AUDIO_ADC_FIR_4S_VAL_LEN) - 1) << AUDIO_ADC_FIR_4S_VAL_POS)) -#define AUDIO_ADC_0_FIR_4S_EN AUDIO_ADC_0_FIR_4S_EN -#define AUDIO_ADC_0_FIR_4S_EN_POS (20U) -#define AUDIO_ADC_0_FIR_4S_EN_LEN (1U) -#define AUDIO_ADC_0_FIR_4S_EN_MSK (((1U << AUDIO_ADC_0_FIR_4S_EN_LEN) - 1) << AUDIO_ADC_0_FIR_4S_EN_POS) -#define AUDIO_ADC_0_FIR_4S_EN_UMSK (~(((1U << AUDIO_ADC_0_FIR_4S_EN_LEN) - 1) << AUDIO_ADC_0_FIR_4S_EN_POS)) -#define AUDIO_ADC_1_FIR_4S_EN AUDIO_ADC_1_FIR_4S_EN -#define AUDIO_ADC_1_FIR_4S_EN_POS (21U) -#define AUDIO_ADC_1_FIR_4S_EN_LEN (1U) -#define AUDIO_ADC_1_FIR_4S_EN_MSK (((1U << AUDIO_ADC_1_FIR_4S_EN_LEN) - 1) << AUDIO_ADC_1_FIR_4S_EN_POS) -#define AUDIO_ADC_1_FIR_4S_EN_UMSK (~(((1U << AUDIO_ADC_1_FIR_4S_EN_LEN) - 1) << AUDIO_ADC_1_FIR_4S_EN_POS)) -#define AUDIO_ADC_2_FIR_4S_EN AUDIO_ADC_2_FIR_4S_EN -#define AUDIO_ADC_2_FIR_4S_EN_POS (22U) -#define AUDIO_ADC_2_FIR_4S_EN_LEN (1U) -#define AUDIO_ADC_2_FIR_4S_EN_MSK (((1U << AUDIO_ADC_2_FIR_4S_EN_LEN) - 1) << AUDIO_ADC_2_FIR_4S_EN_POS) -#define AUDIO_ADC_2_FIR_4S_EN_UMSK (~(((1U << AUDIO_ADC_2_FIR_4S_EN_LEN) - 1) << AUDIO_ADC_2_FIR_4S_EN_POS)) -#define AUDIO_ADC_IN_0_TEST_SEL AUDIO_ADC_IN_0_TEST_SEL -#define AUDIO_ADC_IN_0_TEST_SEL_POS (23U) -#define AUDIO_ADC_IN_0_TEST_SEL_LEN (1U) -#define AUDIO_ADC_IN_0_TEST_SEL_MSK (((1U << AUDIO_ADC_IN_0_TEST_SEL_LEN) - 1) << AUDIO_ADC_IN_0_TEST_SEL_POS) -#define AUDIO_ADC_IN_0_TEST_SEL_UMSK (~(((1U << AUDIO_ADC_IN_0_TEST_SEL_LEN) - 1) << AUDIO_ADC_IN_0_TEST_SEL_POS)) -#define AUDIO_ADC_IN_1_TEST_SEL AUDIO_ADC_IN_1_TEST_SEL -#define AUDIO_ADC_IN_1_TEST_SEL_POS (24U) -#define AUDIO_ADC_IN_1_TEST_SEL_LEN (1U) -#define AUDIO_ADC_IN_1_TEST_SEL_MSK (((1U << AUDIO_ADC_IN_1_TEST_SEL_LEN) - 1) << AUDIO_ADC_IN_1_TEST_SEL_POS) -#define AUDIO_ADC_IN_1_TEST_SEL_UMSK (~(((1U << AUDIO_ADC_IN_1_TEST_SEL_LEN) - 1) << AUDIO_ADC_IN_1_TEST_SEL_POS)) -#define AUDIO_ADC_IN_2_TEST_SEL AUDIO_ADC_IN_2_TEST_SEL -#define AUDIO_ADC_IN_2_TEST_SEL_POS (25U) -#define AUDIO_ADC_IN_2_TEST_SEL_LEN (1U) -#define AUDIO_ADC_IN_2_TEST_SEL_MSK (((1U << AUDIO_ADC_IN_2_TEST_SEL_LEN) - 1) << AUDIO_ADC_IN_2_TEST_SEL_POS) -#define AUDIO_ADC_IN_2_TEST_SEL_UMSK (~(((1U << AUDIO_ADC_IN_2_TEST_SEL_LEN) - 1) << AUDIO_ADC_IN_2_TEST_SEL_POS)) - -/* 0x30 : dbg_3 */ -#define AUDIO_DBG_3_OFFSET (0x30) -#define AUDIO_DAC_4S_VAL AUDIO_DAC_4S_VAL -#define AUDIO_DAC_4S_VAL_POS (0U) -#define AUDIO_DAC_4S_VAL_LEN (20U) -#define AUDIO_DAC_4S_VAL_MSK (((1U << AUDIO_DAC_4S_VAL_LEN) - 1) << AUDIO_DAC_4S_VAL_POS) -#define AUDIO_DAC_4S_VAL_UMSK (~(((1U << AUDIO_DAC_4S_VAL_LEN) - 1) << AUDIO_DAC_4S_VAL_POS)) -#define AUDIO_DAC_DWA_0_4S_EN AUDIO_DAC_DWA_0_4S_EN -#define AUDIO_DAC_DWA_0_4S_EN_POS (20U) -#define AUDIO_DAC_DWA_0_4S_EN_LEN (1U) -#define AUDIO_DAC_DWA_0_4S_EN_MSK (((1U << AUDIO_DAC_DWA_0_4S_EN_LEN) - 1) << AUDIO_DAC_DWA_0_4S_EN_POS) -#define AUDIO_DAC_DWA_0_4S_EN_UMSK (~(((1U << AUDIO_DAC_DWA_0_4S_EN_LEN) - 1) << AUDIO_DAC_DWA_0_4S_EN_POS)) -#define AUDIO_DAC_DWA_1_4S_EN AUDIO_DAC_DWA_1_4S_EN -#define AUDIO_DAC_DWA_1_4S_EN_POS (21U) -#define AUDIO_DAC_DWA_1_4S_EN_LEN (1U) -#define AUDIO_DAC_DWA_1_4S_EN_MSK (((1U << AUDIO_DAC_DWA_1_4S_EN_LEN) - 1) << AUDIO_DAC_DWA_1_4S_EN_POS) -#define AUDIO_DAC_DWA_1_4S_EN_UMSK (~(((1U << AUDIO_DAC_DWA_1_4S_EN_LEN) - 1) << AUDIO_DAC_DWA_1_4S_EN_POS)) -#define AUDIO_DAC_IN_0_TEST_SEL AUDIO_DAC_IN_0_TEST_SEL -#define AUDIO_DAC_IN_0_TEST_SEL_POS (22U) -#define AUDIO_DAC_IN_0_TEST_SEL_LEN (1U) -#define AUDIO_DAC_IN_0_TEST_SEL_MSK (((1U << AUDIO_DAC_IN_0_TEST_SEL_LEN) - 1) << AUDIO_DAC_IN_0_TEST_SEL_POS) -#define AUDIO_DAC_IN_0_TEST_SEL_UMSK (~(((1U << AUDIO_DAC_IN_0_TEST_SEL_LEN) - 1) << AUDIO_DAC_IN_0_TEST_SEL_POS)) -#define AUDIO_DAC_IN_1_TEST_SEL AUDIO_DAC_IN_1_TEST_SEL -#define AUDIO_DAC_IN_1_TEST_SEL_POS (23U) -#define AUDIO_DAC_IN_1_TEST_SEL_LEN (1U) -#define AUDIO_DAC_IN_1_TEST_SEL_MSK (((1U << AUDIO_DAC_IN_1_TEST_SEL_LEN) - 1) << AUDIO_DAC_IN_1_TEST_SEL_POS) -#define AUDIO_DAC_IN_1_TEST_SEL_UMSK (~(((1U << AUDIO_DAC_IN_1_TEST_SEL_LEN) - 1) << AUDIO_DAC_IN_1_TEST_SEL_POS)) - -/* 0x34 : dbg_4 */ -#define AUDIO_DBG_4_OFFSET (0x34) -#define AUDIO_ADC_IN_RATIO_4S_VAL AUDIO_ADC_IN_RATIO_4S_VAL -#define AUDIO_ADC_IN_RATIO_4S_VAL_POS (0U) -#define AUDIO_ADC_IN_RATIO_4S_VAL_LEN (1U) -#define AUDIO_ADC_IN_RATIO_4S_VAL_MSK (((1U << AUDIO_ADC_IN_RATIO_4S_VAL_LEN) - 1) << AUDIO_ADC_IN_RATIO_4S_VAL_POS) -#define AUDIO_ADC_IN_RATIO_4S_VAL_UMSK (~(((1U << AUDIO_ADC_IN_RATIO_4S_VAL_LEN) - 1) << AUDIO_ADC_IN_RATIO_4S_VAL_POS)) -#define AUDIO_ADC_IN_CH0_RATIO_4S_VAL AUDIO_ADC_IN_CH0_RATIO_4S_VAL -#define AUDIO_ADC_IN_CH0_RATIO_4S_VAL_POS (1U) -#define AUDIO_ADC_IN_CH0_RATIO_4S_VAL_LEN (1U) -#define AUDIO_ADC_IN_CH0_RATIO_4S_VAL_MSK (((1U << AUDIO_ADC_IN_CH0_RATIO_4S_VAL_LEN) - 1) << AUDIO_ADC_IN_CH0_RATIO_4S_VAL_POS) -#define AUDIO_ADC_IN_CH0_RATIO_4S_VAL_UMSK (~(((1U << AUDIO_ADC_IN_CH0_RATIO_4S_VAL_LEN) - 1) << AUDIO_ADC_IN_CH0_RATIO_4S_VAL_POS)) -#define AUDIO_ADC_IN_CH1_RATIO_4S_VAL AUDIO_ADC_IN_CH1_RATIO_4S_VAL -#define AUDIO_ADC_IN_CH1_RATIO_4S_VAL_POS (2U) -#define AUDIO_ADC_IN_CH1_RATIO_4S_VAL_LEN (1U) -#define AUDIO_ADC_IN_CH1_RATIO_4S_VAL_MSK (((1U << AUDIO_ADC_IN_CH1_RATIO_4S_VAL_LEN) - 1) << AUDIO_ADC_IN_CH1_RATIO_4S_VAL_POS) -#define AUDIO_ADC_IN_CH1_RATIO_4S_VAL_UMSK (~(((1U << AUDIO_ADC_IN_CH1_RATIO_4S_VAL_LEN) - 1) << AUDIO_ADC_IN_CH1_RATIO_4S_VAL_POS)) -#define AUDIO_ADC_IN_CH2_RATIO_4S_VAL AUDIO_ADC_IN_CH2_RATIO_4S_VAL -#define AUDIO_ADC_IN_CH2_RATIO_4S_VAL_POS (3U) -#define AUDIO_ADC_IN_CH2_RATIO_4S_VAL_LEN (1U) -#define AUDIO_ADC_IN_CH2_RATIO_4S_VAL_MSK (((1U << AUDIO_ADC_IN_CH2_RATIO_4S_VAL_LEN) - 1) << AUDIO_ADC_IN_CH2_RATIO_4S_VAL_POS) -#define AUDIO_ADC_IN_CH2_RATIO_4S_VAL_UMSK (~(((1U << AUDIO_ADC_IN_CH2_RATIO_4S_VAL_LEN) - 1) << AUDIO_ADC_IN_CH2_RATIO_4S_VAL_POS)) -#define AUDIO_PDM_IN_RATIO_4S_VAL AUDIO_PDM_IN_RATIO_4S_VAL -#define AUDIO_PDM_IN_RATIO_4S_VAL_POS (4U) -#define AUDIO_PDM_IN_RATIO_4S_VAL_LEN (1U) -#define AUDIO_PDM_IN_RATIO_4S_VAL_MSK (((1U << AUDIO_PDM_IN_RATIO_4S_VAL_LEN) - 1) << AUDIO_PDM_IN_RATIO_4S_VAL_POS) -#define AUDIO_PDM_IN_RATIO_4S_VAL_UMSK (~(((1U << AUDIO_PDM_IN_RATIO_4S_VAL_LEN) - 1) << AUDIO_PDM_IN_RATIO_4S_VAL_POS)) -#define AUDIO_PDM_IN_RATIO_4S AUDIO_PDM_IN_RATIO_4S -#define AUDIO_PDM_IN_RATIO_4S_POS (5U) -#define AUDIO_PDM_IN_RATIO_4S_LEN (1U) -#define AUDIO_PDM_IN_RATIO_4S_MSK (((1U << AUDIO_PDM_IN_RATIO_4S_LEN) - 1) << AUDIO_PDM_IN_RATIO_4S_POS) -#define AUDIO_PDM_IN_RATIO_4S_UMSK (~(((1U << AUDIO_PDM_IN_RATIO_4S_LEN) - 1) << AUDIO_PDM_IN_RATIO_4S_POS)) -#define AUDIO_DAC_OUT_RATIO_4S_VAL AUDIO_DAC_OUT_RATIO_4S_VAL -#define AUDIO_DAC_OUT_RATIO_4S_VAL_POS (6U) -#define AUDIO_DAC_OUT_RATIO_4S_VAL_LEN (2U) -#define AUDIO_DAC_OUT_RATIO_4S_VAL_MSK (((1U << AUDIO_DAC_OUT_RATIO_4S_VAL_LEN) - 1) << AUDIO_DAC_OUT_RATIO_4S_VAL_POS) -#define AUDIO_DAC_OUT_RATIO_4S_VAL_UMSK (~(((1U << AUDIO_DAC_OUT_RATIO_4S_VAL_LEN) - 1) << AUDIO_DAC_OUT_RATIO_4S_VAL_POS)) -#define AUDIO_AEC_FS_RATE_4S_VAL AUDIO_AEC_FS_RATE_4S_VAL -#define AUDIO_AEC_FS_RATE_4S_VAL_POS (8U) -#define AUDIO_AEC_FS_RATE_4S_VAL_LEN (3U) -#define AUDIO_AEC_FS_RATE_4S_VAL_MSK (((1U << AUDIO_AEC_FS_RATE_4S_VAL_LEN) - 1) << AUDIO_AEC_FS_RATE_4S_VAL_POS) -#define AUDIO_AEC_FS_RATE_4S_VAL_UMSK (~(((1U << AUDIO_AEC_FS_RATE_4S_VAL_LEN) - 1) << AUDIO_AEC_FS_RATE_4S_VAL_POS)) - -/* 0x80 : rx_fifo_ctrl */ -#define AUDIO_RX_FIFO_CTRL_OFFSET (0x80) -#define AUDIO_RX_FIFO_FLUSH AUDIO_RX_FIFO_FLUSH -#define AUDIO_RX_FIFO_FLUSH_POS (0U) -#define AUDIO_RX_FIFO_FLUSH_LEN (1U) -#define AUDIO_RX_FIFO_FLUSH_MSK (((1U << AUDIO_RX_FIFO_FLUSH_LEN) - 1) << AUDIO_RX_FIFO_FLUSH_POS) -#define AUDIO_RX_FIFO_FLUSH_UMSK (~(((1U << AUDIO_RX_FIFO_FLUSH_LEN) - 1) << AUDIO_RX_FIFO_FLUSH_POS)) -#define AUDIO_RXO_INT_EN AUDIO_RXO_INT_EN -#define AUDIO_RXO_INT_EN_POS (1U) -#define AUDIO_RXO_INT_EN_LEN (1U) -#define AUDIO_RXO_INT_EN_MSK (((1U << AUDIO_RXO_INT_EN_LEN) - 1) << AUDIO_RXO_INT_EN_POS) -#define AUDIO_RXO_INT_EN_UMSK (~(((1U << AUDIO_RXO_INT_EN_LEN) - 1) << AUDIO_RXO_INT_EN_POS)) -#define AUDIO_RXU_INT_EN AUDIO_RXU_INT_EN -#define AUDIO_RXU_INT_EN_POS (2U) -#define AUDIO_RXU_INT_EN_LEN (1U) -#define AUDIO_RXU_INT_EN_MSK (((1U << AUDIO_RXU_INT_EN_LEN) - 1) << AUDIO_RXU_INT_EN_POS) -#define AUDIO_RXU_INT_EN_UMSK (~(((1U << AUDIO_RXU_INT_EN_LEN) - 1) << AUDIO_RXU_INT_EN_POS)) -#define AUDIO_RXA_INT_EN AUDIO_RXA_INT_EN -#define AUDIO_RXA_INT_EN_POS (3U) -#define AUDIO_RXA_INT_EN_LEN (1U) -#define AUDIO_RXA_INT_EN_MSK (((1U << AUDIO_RXA_INT_EN_LEN) - 1) << AUDIO_RXA_INT_EN_POS) -#define AUDIO_RXA_INT_EN_UMSK (~(((1U << AUDIO_RXA_INT_EN_LEN) - 1) << AUDIO_RXA_INT_EN_POS)) -#define AUDIO_RX_DRQ_EN AUDIO_RX_DRQ_EN -#define AUDIO_RX_DRQ_EN_POS (4U) -#define AUDIO_RX_DRQ_EN_LEN (1U) -#define AUDIO_RX_DRQ_EN_MSK (((1U << AUDIO_RX_DRQ_EN_LEN) - 1) << AUDIO_RX_DRQ_EN_POS) -#define AUDIO_RX_DRQ_EN_UMSK (~(((1U << AUDIO_RX_DRQ_EN_LEN) - 1) << AUDIO_RX_DRQ_EN_POS)) -#define AUDIO_RX_DATA_RES AUDIO_RX_DATA_RES -#define AUDIO_RX_DATA_RES_POS (5U) -#define AUDIO_RX_DATA_RES_LEN (1U) -#define AUDIO_RX_DATA_RES_MSK (((1U << AUDIO_RX_DATA_RES_LEN) - 1) << AUDIO_RX_DATA_RES_POS) -#define AUDIO_RX_DATA_RES_UMSK (~(((1U << AUDIO_RX_DATA_RES_LEN) - 1) << AUDIO_RX_DATA_RES_POS)) -#define AUDIO_RX_CH_EN AUDIO_RX_CH_EN -#define AUDIO_RX_CH_EN_POS (8U) -#define AUDIO_RX_CH_EN_LEN (5U) -#define AUDIO_RX_CH_EN_MSK (((1U << AUDIO_RX_CH_EN_LEN) - 1) << AUDIO_RX_CH_EN_POS) -#define AUDIO_RX_CH_EN_UMSK (~(((1U << AUDIO_RX_CH_EN_LEN) - 1) << AUDIO_RX_CH_EN_POS)) -#define AUDIO_RX_DRQ_CNT AUDIO_RX_DRQ_CNT -#define AUDIO_RX_DRQ_CNT_POS (14U) -#define AUDIO_RX_DRQ_CNT_LEN (2U) -#define AUDIO_RX_DRQ_CNT_MSK (((1U << AUDIO_RX_DRQ_CNT_LEN) - 1) << AUDIO_RX_DRQ_CNT_POS) -#define AUDIO_RX_DRQ_CNT_UMSK (~(((1U << AUDIO_RX_DRQ_CNT_LEN) - 1) << AUDIO_RX_DRQ_CNT_POS)) -#define AUDIO_RX_TRG_LEVEL AUDIO_RX_TRG_LEVEL -#define AUDIO_RX_TRG_LEVEL_POS (16U) -#define AUDIO_RX_TRG_LEVEL_LEN (7U) -#define AUDIO_RX_TRG_LEVEL_MSK (((1U << AUDIO_RX_TRG_LEVEL_LEN) - 1) << AUDIO_RX_TRG_LEVEL_POS) -#define AUDIO_RX_TRG_LEVEL_UMSK (~(((1U << AUDIO_RX_TRG_LEVEL_LEN) - 1) << AUDIO_RX_TRG_LEVEL_POS)) -#define AUDIO_RX_DATA_MODE AUDIO_RX_DATA_MODE -#define AUDIO_RX_DATA_MODE_POS (24U) -#define AUDIO_RX_DATA_MODE_LEN (2U) -#define AUDIO_RX_DATA_MODE_MSK (((1U << AUDIO_RX_DATA_MODE_LEN) - 1) << AUDIO_RX_DATA_MODE_POS) -#define AUDIO_RX_DATA_MODE_UMSK (~(((1U << AUDIO_RX_DATA_MODE_LEN) - 1) << AUDIO_RX_DATA_MODE_POS)) - -/* 0x84 : rx_fifo_status */ -#define AUDIO_RX_FIFO_STATUS_OFFSET (0x84) -#define AUDIO_RXO_INT AUDIO_RXO_INT -#define AUDIO_RXO_INT_POS (1U) -#define AUDIO_RXO_INT_LEN (1U) -#define AUDIO_RXO_INT_MSK (((1U << AUDIO_RXO_INT_LEN) - 1) << AUDIO_RXO_INT_POS) -#define AUDIO_RXO_INT_UMSK (~(((1U << AUDIO_RXO_INT_LEN) - 1) << AUDIO_RXO_INT_POS)) -#define AUDIO_RXU_INT AUDIO_RXU_INT -#define AUDIO_RXU_INT_POS (2U) -#define AUDIO_RXU_INT_LEN (1U) -#define AUDIO_RXU_INT_MSK (((1U << AUDIO_RXU_INT_LEN) - 1) << AUDIO_RXU_INT_POS) -#define AUDIO_RXU_INT_UMSK (~(((1U << AUDIO_RXU_INT_LEN) - 1) << AUDIO_RXU_INT_POS)) -#define AUDIO_RXA_INT AUDIO_RXA_INT -#define AUDIO_RXA_INT_POS (4U) -#define AUDIO_RXA_INT_LEN (1U) -#define AUDIO_RXA_INT_MSK (((1U << AUDIO_RXA_INT_LEN) - 1) << AUDIO_RXA_INT_POS) -#define AUDIO_RXA_INT_UMSK (~(((1U << AUDIO_RXA_INT_LEN) - 1) << AUDIO_RXA_INT_POS)) -#define AUDIO_RXA_CNT AUDIO_RXA_CNT -#define AUDIO_RXA_CNT_POS (16U) -#define AUDIO_RXA_CNT_LEN (7U) -#define AUDIO_RXA_CNT_MSK (((1U << AUDIO_RXA_CNT_LEN) - 1) << AUDIO_RXA_CNT_POS) -#define AUDIO_RXA_CNT_UMSK (~(((1U << AUDIO_RXA_CNT_LEN) - 1) << AUDIO_RXA_CNT_POS)) -#define AUDIO_RXA AUDIO_RXA -#define AUDIO_RXA_POS (24U) -#define AUDIO_RXA_LEN (1U) -#define AUDIO_RXA_MSK (((1U << AUDIO_RXA_LEN) - 1) << AUDIO_RXA_POS) -#define AUDIO_RXA_UMSK (~(((1U << AUDIO_RXA_LEN) - 1) << AUDIO_RXA_POS)) - -/* 0x88 : rx_fifo_data */ -#define AUDIO_RX_FIFO_DATA_OFFSET (0x88) -#define AUDIO_RX_DATA AUDIO_RX_DATA -#define AUDIO_RX_DATA_POS (0U) -#define AUDIO_RX_DATA_LEN (32U) -#define AUDIO_RX_DATA_MSK (((1U << AUDIO_RX_DATA_LEN) - 1) << AUDIO_RX_DATA_POS) -#define AUDIO_RX_DATA_UMSK (~(((1U << AUDIO_RX_DATA_LEN) - 1) << AUDIO_RX_DATA_POS)) - -/* 0x8C : tx_fifo_ctrl */ -#define AUDIO_TX_FIFO_CTRL_OFFSET (0x8C) -#define AUDIO_TX_FIFO_FLUSH AUDIO_TX_FIFO_FLUSH -#define AUDIO_TX_FIFO_FLUSH_POS (0U) -#define AUDIO_TX_FIFO_FLUSH_LEN (1U) -#define AUDIO_TX_FIFO_FLUSH_MSK (((1U << AUDIO_TX_FIFO_FLUSH_LEN) - 1) << AUDIO_TX_FIFO_FLUSH_POS) -#define AUDIO_TX_FIFO_FLUSH_UMSK (~(((1U << AUDIO_TX_FIFO_FLUSH_LEN) - 1) << AUDIO_TX_FIFO_FLUSH_POS)) -#define AUDIO_TXO_INT_EN AUDIO_TXO_INT_EN -#define AUDIO_TXO_INT_EN_POS (1U) -#define AUDIO_TXO_INT_EN_LEN (1U) -#define AUDIO_TXO_INT_EN_MSK (((1U << AUDIO_TXO_INT_EN_LEN) - 1) << AUDIO_TXO_INT_EN_POS) -#define AUDIO_TXO_INT_EN_UMSK (~(((1U << AUDIO_TXO_INT_EN_LEN) - 1) << AUDIO_TXO_INT_EN_POS)) -#define AUDIO_TXU_INT_EN AUDIO_TXU_INT_EN -#define AUDIO_TXU_INT_EN_POS (2U) -#define AUDIO_TXU_INT_EN_LEN (1U) -#define AUDIO_TXU_INT_EN_MSK (((1U << AUDIO_TXU_INT_EN_LEN) - 1) << AUDIO_TXU_INT_EN_POS) -#define AUDIO_TXU_INT_EN_UMSK (~(((1U << AUDIO_TXU_INT_EN_LEN) - 1) << AUDIO_TXU_INT_EN_POS)) -#define AUDIO_TXA_INT_EN AUDIO_TXA_INT_EN -#define AUDIO_TXA_INT_EN_POS (3U) -#define AUDIO_TXA_INT_EN_LEN (1U) -#define AUDIO_TXA_INT_EN_MSK (((1U << AUDIO_TXA_INT_EN_LEN) - 1) << AUDIO_TXA_INT_EN_POS) -#define AUDIO_TXA_INT_EN_UMSK (~(((1U << AUDIO_TXA_INT_EN_LEN) - 1) << AUDIO_TXA_INT_EN_POS)) -#define AUDIO_TX_DRQ_EN AUDIO_TX_DRQ_EN -#define AUDIO_TX_DRQ_EN_POS (4U) -#define AUDIO_TX_DRQ_EN_LEN (1U) -#define AUDIO_TX_DRQ_EN_MSK (((1U << AUDIO_TX_DRQ_EN_LEN) - 1) << AUDIO_TX_DRQ_EN_POS) -#define AUDIO_TX_DRQ_EN_UMSK (~(((1U << AUDIO_TX_DRQ_EN_LEN) - 1) << AUDIO_TX_DRQ_EN_POS)) -#define AUDIO_TX_DATA_RES AUDIO_TX_DATA_RES -#define AUDIO_TX_DATA_RES_POS (5U) -#define AUDIO_TX_DATA_RES_LEN (1U) -#define AUDIO_TX_DATA_RES_MSK (((1U << AUDIO_TX_DATA_RES_LEN) - 1) << AUDIO_TX_DATA_RES_POS) -#define AUDIO_TX_DATA_RES_UMSK (~(((1U << AUDIO_TX_DATA_RES_LEN) - 1) << AUDIO_TX_DATA_RES_POS)) -#define AUDIO_TX_CH_EN AUDIO_TX_CH_EN -#define AUDIO_TX_CH_EN_POS (8U) -#define AUDIO_TX_CH_EN_LEN (2U) -#define AUDIO_TX_CH_EN_MSK (((1U << AUDIO_TX_CH_EN_LEN) - 1) << AUDIO_TX_CH_EN_POS) -#define AUDIO_TX_CH_EN_UMSK (~(((1U << AUDIO_TX_CH_EN_LEN) - 1) << AUDIO_TX_CH_EN_POS)) -#define AUDIO_TX_DRQ_CNT AUDIO_TX_DRQ_CNT -#define AUDIO_TX_DRQ_CNT_POS (14U) -#define AUDIO_TX_DRQ_CNT_LEN (2U) -#define AUDIO_TX_DRQ_CNT_MSK (((1U << AUDIO_TX_DRQ_CNT_LEN) - 1) << AUDIO_TX_DRQ_CNT_POS) -#define AUDIO_TX_DRQ_CNT_UMSK (~(((1U << AUDIO_TX_DRQ_CNT_LEN) - 1) << AUDIO_TX_DRQ_CNT_POS)) -#define AUDIO_TX_TRG_LEVEL AUDIO_TX_TRG_LEVEL -#define AUDIO_TX_TRG_LEVEL_POS (16U) -#define AUDIO_TX_TRG_LEVEL_LEN (6U) -#define AUDIO_TX_TRG_LEVEL_MSK (((1U << AUDIO_TX_TRG_LEVEL_LEN) - 1) << AUDIO_TX_TRG_LEVEL_POS) -#define AUDIO_TX_TRG_LEVEL_UMSK (~(((1U << AUDIO_TX_TRG_LEVEL_LEN) - 1) << AUDIO_TX_TRG_LEVEL_POS)) -#define AUDIO_TX_DATA_MODE AUDIO_TX_DATA_MODE -#define AUDIO_TX_DATA_MODE_POS (24U) -#define AUDIO_TX_DATA_MODE_LEN (2U) -#define AUDIO_TX_DATA_MODE_MSK (((1U << AUDIO_TX_DATA_MODE_LEN) - 1) << AUDIO_TX_DATA_MODE_POS) -#define AUDIO_TX_DATA_MODE_UMSK (~(((1U << AUDIO_TX_DATA_MODE_LEN) - 1) << AUDIO_TX_DATA_MODE_POS)) - -/* 0x90 : tx_fifo_status */ -#define AUDIO_TX_FIFO_STATUS_OFFSET (0x90) -#define AUDIO_TXO_INT AUDIO_TXO_INT -#define AUDIO_TXO_INT_POS (1U) -#define AUDIO_TXO_INT_LEN (1U) -#define AUDIO_TXO_INT_MSK (((1U << AUDIO_TXO_INT_LEN) - 1) << AUDIO_TXO_INT_POS) -#define AUDIO_TXO_INT_UMSK (~(((1U << AUDIO_TXO_INT_LEN) - 1) << AUDIO_TXO_INT_POS)) -#define AUDIO_TXU_INT AUDIO_TXU_INT -#define AUDIO_TXU_INT_POS (2U) -#define AUDIO_TXU_INT_LEN (1U) -#define AUDIO_TXU_INT_MSK (((1U << AUDIO_TXU_INT_LEN) - 1) << AUDIO_TXU_INT_POS) -#define AUDIO_TXU_INT_UMSK (~(((1U << AUDIO_TXU_INT_LEN) - 1) << AUDIO_TXU_INT_POS)) -#define AUDIO_TXA_INT AUDIO_TXA_INT -#define AUDIO_TXA_INT_POS (4U) -#define AUDIO_TXA_INT_LEN (1U) -#define AUDIO_TXA_INT_MSK (((1U << AUDIO_TXA_INT_LEN) - 1) << AUDIO_TXA_INT_POS) -#define AUDIO_TXA_INT_UMSK (~(((1U << AUDIO_TXA_INT_LEN) - 1) << AUDIO_TXA_INT_POS)) -#define AUDIO_TXA_CNT AUDIO_TXA_CNT -#define AUDIO_TXA_CNT_POS (16U) -#define AUDIO_TXA_CNT_LEN (6U) -#define AUDIO_TXA_CNT_MSK (((1U << AUDIO_TXA_CNT_LEN) - 1) << AUDIO_TXA_CNT_POS) -#define AUDIO_TXA_CNT_UMSK (~(((1U << AUDIO_TXA_CNT_LEN) - 1) << AUDIO_TXA_CNT_POS)) -#define AUDIO_TXA AUDIO_TXA -#define AUDIO_TXA_POS (24U) -#define AUDIO_TXA_LEN (1U) -#define AUDIO_TXA_MSK (((1U << AUDIO_TXA_LEN) - 1) << AUDIO_TXA_POS) -#define AUDIO_TXA_UMSK (~(((1U << AUDIO_TXA_LEN) - 1) << AUDIO_TXA_POS)) - -/* 0x94 : tx_fifo_data */ -#define AUDIO_TX_FIFO_DATA_OFFSET (0x94) -#define AUDIO_TX_DATA AUDIO_TX_DATA -#define AUDIO_TX_DATA_POS (0U) -#define AUDIO_TX_DATA_LEN (32U) -#define AUDIO_TX_DATA_MSK (((1U << AUDIO_TX_DATA_LEN) - 1) << AUDIO_TX_DATA_POS) -#define AUDIO_TX_DATA_UMSK (~(((1U << AUDIO_TX_DATA_LEN) - 1) << AUDIO_TX_DATA_POS)) - -/* 0x200 : peq_00_b0 */ -#define AUDIO_PEQ_00_B0_OFFSET (0x200) -#define AUDIO_PEQ_00_B0 AUDIO_PEQ_00_B0 -#define AUDIO_PEQ_00_B0_POS (0U) -#define AUDIO_PEQ_00_B0_LEN (20U) -#define AUDIO_PEQ_00_B0_MSK (((1U << AUDIO_PEQ_00_B0_LEN) - 1) << AUDIO_PEQ_00_B0_POS) -#define AUDIO_PEQ_00_B0_UMSK (~(((1U << AUDIO_PEQ_00_B0_LEN) - 1) << AUDIO_PEQ_00_B0_POS)) -#define AUDIO_PEQ_00_BYP AUDIO_PEQ_00_BYP -#define AUDIO_PEQ_00_BYP_POS (20U) -#define AUDIO_PEQ_00_BYP_LEN (1U) -#define AUDIO_PEQ_00_BYP_MSK (((1U << AUDIO_PEQ_00_BYP_LEN) - 1) << AUDIO_PEQ_00_BYP_POS) -#define AUDIO_PEQ_00_BYP_UMSK (~(((1U << AUDIO_PEQ_00_BYP_LEN) - 1) << AUDIO_PEQ_00_BYP_POS)) -#define AUDIO_PEQ_00_QFMT AUDIO_PEQ_00_QFMT -#define AUDIO_PEQ_00_QFMT_POS (21U) -#define AUDIO_PEQ_00_QFMT_LEN (1U) -#define AUDIO_PEQ_00_QFMT_MSK (((1U << AUDIO_PEQ_00_QFMT_LEN) - 1) << AUDIO_PEQ_00_QFMT_POS) -#define AUDIO_PEQ_00_QFMT_UMSK (~(((1U << AUDIO_PEQ_00_QFMT_LEN) - 1) << AUDIO_PEQ_00_QFMT_POS)) - -/* 0x204 : peq_00_b1 */ -#define AUDIO_PEQ_00_B1_OFFSET (0x204) -#define AUDIO_PEQ_00_B1 AUDIO_PEQ_00_B1 -#define AUDIO_PEQ_00_B1_POS (0U) -#define AUDIO_PEQ_00_B1_LEN (20U) -#define AUDIO_PEQ_00_B1_MSK (((1U << AUDIO_PEQ_00_B1_LEN) - 1) << AUDIO_PEQ_00_B1_POS) -#define AUDIO_PEQ_00_B1_UMSK (~(((1U << AUDIO_PEQ_00_B1_LEN) - 1) << AUDIO_PEQ_00_B1_POS)) - -/* 0x208 : peq_00_b2 */ -#define AUDIO_PEQ_00_B2_OFFSET (0x208) -#define AUDIO_PEQ_00_B2 AUDIO_PEQ_00_B2 -#define AUDIO_PEQ_00_B2_POS (0U) -#define AUDIO_PEQ_00_B2_LEN (20U) -#define AUDIO_PEQ_00_B2_MSK (((1U << AUDIO_PEQ_00_B2_LEN) - 1) << AUDIO_PEQ_00_B2_POS) -#define AUDIO_PEQ_00_B2_UMSK (~(((1U << AUDIO_PEQ_00_B2_LEN) - 1) << AUDIO_PEQ_00_B2_POS)) - -/* 0x20C : peq_00_a1 */ -#define AUDIO_PEQ_00_A1_OFFSET (0x20C) -#define AUDIO_PEQ_00_A1 AUDIO_PEQ_00_A1 -#define AUDIO_PEQ_00_A1_POS (0U) -#define AUDIO_PEQ_00_A1_LEN (20U) -#define AUDIO_PEQ_00_A1_MSK (((1U << AUDIO_PEQ_00_A1_LEN) - 1) << AUDIO_PEQ_00_A1_POS) -#define AUDIO_PEQ_00_A1_UMSK (~(((1U << AUDIO_PEQ_00_A1_LEN) - 1) << AUDIO_PEQ_00_A1_POS)) - -/* 0x210 : peq_00_a2 */ -#define AUDIO_PEQ_00_A2_OFFSET (0x210) -#define AUDIO_PEQ_00_A2 AUDIO_PEQ_00_A2 -#define AUDIO_PEQ_00_A2_POS (0U) -#define AUDIO_PEQ_00_A2_LEN (20U) -#define AUDIO_PEQ_00_A2_MSK (((1U << AUDIO_PEQ_00_A2_LEN) - 1) << AUDIO_PEQ_00_A2_POS) -#define AUDIO_PEQ_00_A2_UMSK (~(((1U << AUDIO_PEQ_00_A2_LEN) - 1) << AUDIO_PEQ_00_A2_POS)) - -/* 0x214 : peq_01_b0 */ -#define AUDIO_PEQ_01_B0_OFFSET (0x214) -#define AUDIO_PEQ_01_B0 AUDIO_PEQ_01_B0 -#define AUDIO_PEQ_01_B0_POS (0U) -#define AUDIO_PEQ_01_B0_LEN (20U) -#define AUDIO_PEQ_01_B0_MSK (((1U << AUDIO_PEQ_01_B0_LEN) - 1) << AUDIO_PEQ_01_B0_POS) -#define AUDIO_PEQ_01_B0_UMSK (~(((1U << AUDIO_PEQ_01_B0_LEN) - 1) << AUDIO_PEQ_01_B0_POS)) -#define AUDIO_PEQ_01_BYP AUDIO_PEQ_01_BYP -#define AUDIO_PEQ_01_BYP_POS (20U) -#define AUDIO_PEQ_01_BYP_LEN (1U) -#define AUDIO_PEQ_01_BYP_MSK (((1U << AUDIO_PEQ_01_BYP_LEN) - 1) << AUDIO_PEQ_01_BYP_POS) -#define AUDIO_PEQ_01_BYP_UMSK (~(((1U << AUDIO_PEQ_01_BYP_LEN) - 1) << AUDIO_PEQ_01_BYP_POS)) -#define AUDIO_PEQ_01_QFMT AUDIO_PEQ_01_QFMT -#define AUDIO_PEQ_01_QFMT_POS (21U) -#define AUDIO_PEQ_01_QFMT_LEN (1U) -#define AUDIO_PEQ_01_QFMT_MSK (((1U << AUDIO_PEQ_01_QFMT_LEN) - 1) << AUDIO_PEQ_01_QFMT_POS) -#define AUDIO_PEQ_01_QFMT_UMSK (~(((1U << AUDIO_PEQ_01_QFMT_LEN) - 1) << AUDIO_PEQ_01_QFMT_POS)) - -/* 0x218 : peq_01_b1 */ -#define AUDIO_PEQ_01_B1_OFFSET (0x218) -#define AUDIO_PEQ_01_B1 AUDIO_PEQ_01_B1 -#define AUDIO_PEQ_01_B1_POS (0U) -#define AUDIO_PEQ_01_B1_LEN (20U) -#define AUDIO_PEQ_01_B1_MSK (((1U << AUDIO_PEQ_01_B1_LEN) - 1) << AUDIO_PEQ_01_B1_POS) -#define AUDIO_PEQ_01_B1_UMSK (~(((1U << AUDIO_PEQ_01_B1_LEN) - 1) << AUDIO_PEQ_01_B1_POS)) - -/* 0x21C : peq_01_b2 */ -#define AUDIO_PEQ_01_B2_OFFSET (0x21C) -#define AUDIO_PEQ_01_B2 AUDIO_PEQ_01_B2 -#define AUDIO_PEQ_01_B2_POS (0U) -#define AUDIO_PEQ_01_B2_LEN (20U) -#define AUDIO_PEQ_01_B2_MSK (((1U << AUDIO_PEQ_01_B2_LEN) - 1) << AUDIO_PEQ_01_B2_POS) -#define AUDIO_PEQ_01_B2_UMSK (~(((1U << AUDIO_PEQ_01_B2_LEN) - 1) << AUDIO_PEQ_01_B2_POS)) - -/* 0x220 : peq_01_a1 */ -#define AUDIO_PEQ_01_A1_OFFSET (0x220) -#define AUDIO_PEQ_01_A1 AUDIO_PEQ_01_A1 -#define AUDIO_PEQ_01_A1_POS (0U) -#define AUDIO_PEQ_01_A1_LEN (20U) -#define AUDIO_PEQ_01_A1_MSK (((1U << AUDIO_PEQ_01_A1_LEN) - 1) << AUDIO_PEQ_01_A1_POS) -#define AUDIO_PEQ_01_A1_UMSK (~(((1U << AUDIO_PEQ_01_A1_LEN) - 1) << AUDIO_PEQ_01_A1_POS)) - -/* 0x224 : peq_01_a2 */ -#define AUDIO_PEQ_01_A2_OFFSET (0x224) -#define AUDIO_PEQ_01_A2 AUDIO_PEQ_01_A2 -#define AUDIO_PEQ_01_A2_POS (0U) -#define AUDIO_PEQ_01_A2_LEN (20U) -#define AUDIO_PEQ_01_A2_MSK (((1U << AUDIO_PEQ_01_A2_LEN) - 1) << AUDIO_PEQ_01_A2_POS) -#define AUDIO_PEQ_01_A2_UMSK (~(((1U << AUDIO_PEQ_01_A2_LEN) - 1) << AUDIO_PEQ_01_A2_POS)) - -/* 0x228 : peq_02_b0 */ -#define AUDIO_PEQ_02_B0_OFFSET (0x228) -#define AUDIO_PEQ_02_B0 AUDIO_PEQ_02_B0 -#define AUDIO_PEQ_02_B0_POS (0U) -#define AUDIO_PEQ_02_B0_LEN (20U) -#define AUDIO_PEQ_02_B0_MSK (((1U << AUDIO_PEQ_02_B0_LEN) - 1) << AUDIO_PEQ_02_B0_POS) -#define AUDIO_PEQ_02_B0_UMSK (~(((1U << AUDIO_PEQ_02_B0_LEN) - 1) << AUDIO_PEQ_02_B0_POS)) -#define AUDIO_PEQ_02_BYP AUDIO_PEQ_02_BYP -#define AUDIO_PEQ_02_BYP_POS (20U) -#define AUDIO_PEQ_02_BYP_LEN (1U) -#define AUDIO_PEQ_02_BYP_MSK (((1U << AUDIO_PEQ_02_BYP_LEN) - 1) << AUDIO_PEQ_02_BYP_POS) -#define AUDIO_PEQ_02_BYP_UMSK (~(((1U << AUDIO_PEQ_02_BYP_LEN) - 1) << AUDIO_PEQ_02_BYP_POS)) -#define AUDIO_PEQ_02_QFMT AUDIO_PEQ_02_QFMT -#define AUDIO_PEQ_02_QFMT_POS (21U) -#define AUDIO_PEQ_02_QFMT_LEN (1U) -#define AUDIO_PEQ_02_QFMT_MSK (((1U << AUDIO_PEQ_02_QFMT_LEN) - 1) << AUDIO_PEQ_02_QFMT_POS) -#define AUDIO_PEQ_02_QFMT_UMSK (~(((1U << AUDIO_PEQ_02_QFMT_LEN) - 1) << AUDIO_PEQ_02_QFMT_POS)) - -/* 0x22C : peq_02_b1 */ -#define AUDIO_PEQ_02_B1_OFFSET (0x22C) -#define AUDIO_PEQ_02_B1 AUDIO_PEQ_02_B1 -#define AUDIO_PEQ_02_B1_POS (0U) -#define AUDIO_PEQ_02_B1_LEN (20U) -#define AUDIO_PEQ_02_B1_MSK (((1U << AUDIO_PEQ_02_B1_LEN) - 1) << AUDIO_PEQ_02_B1_POS) -#define AUDIO_PEQ_02_B1_UMSK (~(((1U << AUDIO_PEQ_02_B1_LEN) - 1) << AUDIO_PEQ_02_B1_POS)) - -/* 0x230 : peq_02_b2 */ -#define AUDIO_PEQ_02_B2_OFFSET (0x230) -#define AUDIO_PEQ_02_B2 AUDIO_PEQ_02_B2 -#define AUDIO_PEQ_02_B2_POS (0U) -#define AUDIO_PEQ_02_B2_LEN (20U) -#define AUDIO_PEQ_02_B2_MSK (((1U << AUDIO_PEQ_02_B2_LEN) - 1) << AUDIO_PEQ_02_B2_POS) -#define AUDIO_PEQ_02_B2_UMSK (~(((1U << AUDIO_PEQ_02_B2_LEN) - 1) << AUDIO_PEQ_02_B2_POS)) - -/* 0x234 : peq_02_a1 */ -#define AUDIO_PEQ_02_A1_OFFSET (0x234) -#define AUDIO_PEQ_02_A1 AUDIO_PEQ_02_A1 -#define AUDIO_PEQ_02_A1_POS (0U) -#define AUDIO_PEQ_02_A1_LEN (20U) -#define AUDIO_PEQ_02_A1_MSK (((1U << AUDIO_PEQ_02_A1_LEN) - 1) << AUDIO_PEQ_02_A1_POS) -#define AUDIO_PEQ_02_A1_UMSK (~(((1U << AUDIO_PEQ_02_A1_LEN) - 1) << AUDIO_PEQ_02_A1_POS)) - -/* 0x238 : peq_02_a2 */ -#define AUDIO_PEQ_02_A2_OFFSET (0x238) -#define AUDIO_PEQ_02_A2 AUDIO_PEQ_02_A2 -#define AUDIO_PEQ_02_A2_POS (0U) -#define AUDIO_PEQ_02_A2_LEN (20U) -#define AUDIO_PEQ_02_A2_MSK (((1U << AUDIO_PEQ_02_A2_LEN) - 1) << AUDIO_PEQ_02_A2_POS) -#define AUDIO_PEQ_02_A2_UMSK (~(((1U << AUDIO_PEQ_02_A2_LEN) - 1) << AUDIO_PEQ_02_A2_POS)) - -/* 0x23C : peq_03_b0 */ -#define AUDIO_PEQ_03_B0_OFFSET (0x23C) -#define AUDIO_PEQ_03_B0 AUDIO_PEQ_03_B0 -#define AUDIO_PEQ_03_B0_POS (0U) -#define AUDIO_PEQ_03_B0_LEN (20U) -#define AUDIO_PEQ_03_B0_MSK (((1U << AUDIO_PEQ_03_B0_LEN) - 1) << AUDIO_PEQ_03_B0_POS) -#define AUDIO_PEQ_03_B0_UMSK (~(((1U << AUDIO_PEQ_03_B0_LEN) - 1) << AUDIO_PEQ_03_B0_POS)) -#define AUDIO_PEQ_03_BYP AUDIO_PEQ_03_BYP -#define AUDIO_PEQ_03_BYP_POS (20U) -#define AUDIO_PEQ_03_BYP_LEN (1U) -#define AUDIO_PEQ_03_BYP_MSK (((1U << AUDIO_PEQ_03_BYP_LEN) - 1) << AUDIO_PEQ_03_BYP_POS) -#define AUDIO_PEQ_03_BYP_UMSK (~(((1U << AUDIO_PEQ_03_BYP_LEN) - 1) << AUDIO_PEQ_03_BYP_POS)) -#define AUDIO_PEQ_03_QFMT AUDIO_PEQ_03_QFMT -#define AUDIO_PEQ_03_QFMT_POS (21U) -#define AUDIO_PEQ_03_QFMT_LEN (1U) -#define AUDIO_PEQ_03_QFMT_MSK (((1U << AUDIO_PEQ_03_QFMT_LEN) - 1) << AUDIO_PEQ_03_QFMT_POS) -#define AUDIO_PEQ_03_QFMT_UMSK (~(((1U << AUDIO_PEQ_03_QFMT_LEN) - 1) << AUDIO_PEQ_03_QFMT_POS)) - -/* 0x240 : peq_03_b1 */ -#define AUDIO_PEQ_03_B1_OFFSET (0x240) -#define AUDIO_PEQ_03_B1 AUDIO_PEQ_03_B1 -#define AUDIO_PEQ_03_B1_POS (0U) -#define AUDIO_PEQ_03_B1_LEN (20U) -#define AUDIO_PEQ_03_B1_MSK (((1U << AUDIO_PEQ_03_B1_LEN) - 1) << AUDIO_PEQ_03_B1_POS) -#define AUDIO_PEQ_03_B1_UMSK (~(((1U << AUDIO_PEQ_03_B1_LEN) - 1) << AUDIO_PEQ_03_B1_POS)) - -/* 0x244 : peq_03_b2 */ -#define AUDIO_PEQ_03_B2_OFFSET (0x244) -#define AUDIO_PEQ_03_B2 AUDIO_PEQ_03_B2 -#define AUDIO_PEQ_03_B2_POS (0U) -#define AUDIO_PEQ_03_B2_LEN (20U) -#define AUDIO_PEQ_03_B2_MSK (((1U << AUDIO_PEQ_03_B2_LEN) - 1) << AUDIO_PEQ_03_B2_POS) -#define AUDIO_PEQ_03_B2_UMSK (~(((1U << AUDIO_PEQ_03_B2_LEN) - 1) << AUDIO_PEQ_03_B2_POS)) - -/* 0x248 : peq_03_a1 */ -#define AUDIO_PEQ_03_A1_OFFSET (0x248) -#define AUDIO_PEQ_03_A1 AUDIO_PEQ_03_A1 -#define AUDIO_PEQ_03_A1_POS (0U) -#define AUDIO_PEQ_03_A1_LEN (20U) -#define AUDIO_PEQ_03_A1_MSK (((1U << AUDIO_PEQ_03_A1_LEN) - 1) << AUDIO_PEQ_03_A1_POS) -#define AUDIO_PEQ_03_A1_UMSK (~(((1U << AUDIO_PEQ_03_A1_LEN) - 1) << AUDIO_PEQ_03_A1_POS)) - -/* 0x24C : peq_03_a2 */ -#define AUDIO_PEQ_03_A2_OFFSET (0x24C) -#define AUDIO_PEQ_03_A2 AUDIO_PEQ_03_A2 -#define AUDIO_PEQ_03_A2_POS (0U) -#define AUDIO_PEQ_03_A2_LEN (20U) -#define AUDIO_PEQ_03_A2_MSK (((1U << AUDIO_PEQ_03_A2_LEN) - 1) << AUDIO_PEQ_03_A2_POS) -#define AUDIO_PEQ_03_A2_UMSK (~(((1U << AUDIO_PEQ_03_A2_LEN) - 1) << AUDIO_PEQ_03_A2_POS)) - -/* 0x250 : peq_04_b0 */ -#define AUDIO_PEQ_04_B0_OFFSET (0x250) -#define AUDIO_PEQ_04_B0 AUDIO_PEQ_04_B0 -#define AUDIO_PEQ_04_B0_POS (0U) -#define AUDIO_PEQ_04_B0_LEN (20U) -#define AUDIO_PEQ_04_B0_MSK (((1U << AUDIO_PEQ_04_B0_LEN) - 1) << AUDIO_PEQ_04_B0_POS) -#define AUDIO_PEQ_04_B0_UMSK (~(((1U << AUDIO_PEQ_04_B0_LEN) - 1) << AUDIO_PEQ_04_B0_POS)) -#define AUDIO_PEQ_04_BYP AUDIO_PEQ_04_BYP -#define AUDIO_PEQ_04_BYP_POS (20U) -#define AUDIO_PEQ_04_BYP_LEN (1U) -#define AUDIO_PEQ_04_BYP_MSK (((1U << AUDIO_PEQ_04_BYP_LEN) - 1) << AUDIO_PEQ_04_BYP_POS) -#define AUDIO_PEQ_04_BYP_UMSK (~(((1U << AUDIO_PEQ_04_BYP_LEN) - 1) << AUDIO_PEQ_04_BYP_POS)) -#define AUDIO_PEQ_04_QFMT AUDIO_PEQ_04_QFMT -#define AUDIO_PEQ_04_QFMT_POS (21U) -#define AUDIO_PEQ_04_QFMT_LEN (1U) -#define AUDIO_PEQ_04_QFMT_MSK (((1U << AUDIO_PEQ_04_QFMT_LEN) - 1) << AUDIO_PEQ_04_QFMT_POS) -#define AUDIO_PEQ_04_QFMT_UMSK (~(((1U << AUDIO_PEQ_04_QFMT_LEN) - 1) << AUDIO_PEQ_04_QFMT_POS)) - -/* 0x254 : peq_04_b1 */ -#define AUDIO_PEQ_04_B1_OFFSET (0x254) -#define AUDIO_PEQ_04_B1 AUDIO_PEQ_04_B1 -#define AUDIO_PEQ_04_B1_POS (0U) -#define AUDIO_PEQ_04_B1_LEN (20U) -#define AUDIO_PEQ_04_B1_MSK (((1U << AUDIO_PEQ_04_B1_LEN) - 1) << AUDIO_PEQ_04_B1_POS) -#define AUDIO_PEQ_04_B1_UMSK (~(((1U << AUDIO_PEQ_04_B1_LEN) - 1) << AUDIO_PEQ_04_B1_POS)) - -/* 0x258 : peq_04_b2 */ -#define AUDIO_PEQ_04_B2_OFFSET (0x258) -#define AUDIO_PEQ_04_B2 AUDIO_PEQ_04_B2 -#define AUDIO_PEQ_04_B2_POS (0U) -#define AUDIO_PEQ_04_B2_LEN (20U) -#define AUDIO_PEQ_04_B2_MSK (((1U << AUDIO_PEQ_04_B2_LEN) - 1) << AUDIO_PEQ_04_B2_POS) -#define AUDIO_PEQ_04_B2_UMSK (~(((1U << AUDIO_PEQ_04_B2_LEN) - 1) << AUDIO_PEQ_04_B2_POS)) - -/* 0x25C : peq_04_a1 */ -#define AUDIO_PEQ_04_A1_OFFSET (0x25C) -#define AUDIO_PEQ_04_A1 AUDIO_PEQ_04_A1 -#define AUDIO_PEQ_04_A1_POS (0U) -#define AUDIO_PEQ_04_A1_LEN (20U) -#define AUDIO_PEQ_04_A1_MSK (((1U << AUDIO_PEQ_04_A1_LEN) - 1) << AUDIO_PEQ_04_A1_POS) -#define AUDIO_PEQ_04_A1_UMSK (~(((1U << AUDIO_PEQ_04_A1_LEN) - 1) << AUDIO_PEQ_04_A1_POS)) - -/* 0x260 : peq_04_a2 */ -#define AUDIO_PEQ_04_A2_OFFSET (0x260) -#define AUDIO_PEQ_04_A2 AUDIO_PEQ_04_A2 -#define AUDIO_PEQ_04_A2_POS (0U) -#define AUDIO_PEQ_04_A2_LEN (20U) -#define AUDIO_PEQ_04_A2_MSK (((1U << AUDIO_PEQ_04_A2_LEN) - 1) << AUDIO_PEQ_04_A2_POS) -#define AUDIO_PEQ_04_A2_UMSK (~(((1U << AUDIO_PEQ_04_A2_LEN) - 1) << AUDIO_PEQ_04_A2_POS)) - -/* 0x264 : peq_05_b0 */ -#define AUDIO_PEQ_05_B0_OFFSET (0x264) -#define AUDIO_PEQ_05_B0 AUDIO_PEQ_05_B0 -#define AUDIO_PEQ_05_B0_POS (0U) -#define AUDIO_PEQ_05_B0_LEN (20U) -#define AUDIO_PEQ_05_B0_MSK (((1U << AUDIO_PEQ_05_B0_LEN) - 1) << AUDIO_PEQ_05_B0_POS) -#define AUDIO_PEQ_05_B0_UMSK (~(((1U << AUDIO_PEQ_05_B0_LEN) - 1) << AUDIO_PEQ_05_B0_POS)) -#define AUDIO_PEQ_05_BYP AUDIO_PEQ_05_BYP -#define AUDIO_PEQ_05_BYP_POS (20U) -#define AUDIO_PEQ_05_BYP_LEN (1U) -#define AUDIO_PEQ_05_BYP_MSK (((1U << AUDIO_PEQ_05_BYP_LEN) - 1) << AUDIO_PEQ_05_BYP_POS) -#define AUDIO_PEQ_05_BYP_UMSK (~(((1U << AUDIO_PEQ_05_BYP_LEN) - 1) << AUDIO_PEQ_05_BYP_POS)) -#define AUDIO_PEQ_05_QFMT AUDIO_PEQ_05_QFMT -#define AUDIO_PEQ_05_QFMT_POS (21U) -#define AUDIO_PEQ_05_QFMT_LEN (1U) -#define AUDIO_PEQ_05_QFMT_MSK (((1U << AUDIO_PEQ_05_QFMT_LEN) - 1) << AUDIO_PEQ_05_QFMT_POS) -#define AUDIO_PEQ_05_QFMT_UMSK (~(((1U << AUDIO_PEQ_05_QFMT_LEN) - 1) << AUDIO_PEQ_05_QFMT_POS)) - -/* 0x268 : peq_05_b1 */ -#define AUDIO_PEQ_05_B1_OFFSET (0x268) -#define AUDIO_PEQ_05_B1 AUDIO_PEQ_05_B1 -#define AUDIO_PEQ_05_B1_POS (0U) -#define AUDIO_PEQ_05_B1_LEN (20U) -#define AUDIO_PEQ_05_B1_MSK (((1U << AUDIO_PEQ_05_B1_LEN) - 1) << AUDIO_PEQ_05_B1_POS) -#define AUDIO_PEQ_05_B1_UMSK (~(((1U << AUDIO_PEQ_05_B1_LEN) - 1) << AUDIO_PEQ_05_B1_POS)) - -/* 0x26C : peq_05_b2 */ -#define AUDIO_PEQ_05_B2_OFFSET (0x26C) -#define AUDIO_PEQ_05_B2 AUDIO_PEQ_05_B2 -#define AUDIO_PEQ_05_B2_POS (0U) -#define AUDIO_PEQ_05_B2_LEN (20U) -#define AUDIO_PEQ_05_B2_MSK (((1U << AUDIO_PEQ_05_B2_LEN) - 1) << AUDIO_PEQ_05_B2_POS) -#define AUDIO_PEQ_05_B2_UMSK (~(((1U << AUDIO_PEQ_05_B2_LEN) - 1) << AUDIO_PEQ_05_B2_POS)) - -/* 0x270 : peq_05_a1 */ -#define AUDIO_PEQ_05_A1_OFFSET (0x270) -#define AUDIO_PEQ_05_A1 AUDIO_PEQ_05_A1 -#define AUDIO_PEQ_05_A1_POS (0U) -#define AUDIO_PEQ_05_A1_LEN (20U) -#define AUDIO_PEQ_05_A1_MSK (((1U << AUDIO_PEQ_05_A1_LEN) - 1) << AUDIO_PEQ_05_A1_POS) -#define AUDIO_PEQ_05_A1_UMSK (~(((1U << AUDIO_PEQ_05_A1_LEN) - 1) << AUDIO_PEQ_05_A1_POS)) - -/* 0x274 : peq_05_a2 */ -#define AUDIO_PEQ_05_A2_OFFSET (0x274) -#define AUDIO_PEQ_05_A2 AUDIO_PEQ_05_A2 -#define AUDIO_PEQ_05_A2_POS (0U) -#define AUDIO_PEQ_05_A2_LEN (20U) -#define AUDIO_PEQ_05_A2_MSK (((1U << AUDIO_PEQ_05_A2_LEN) - 1) << AUDIO_PEQ_05_A2_POS) -#define AUDIO_PEQ_05_A2_UMSK (~(((1U << AUDIO_PEQ_05_A2_LEN) - 1) << AUDIO_PEQ_05_A2_POS)) - -/* 0x278 : peq_06_b0 */ -#define AUDIO_PEQ_06_B0_OFFSET (0x278) -#define AUDIO_PEQ_06_B0 AUDIO_PEQ_06_B0 -#define AUDIO_PEQ_06_B0_POS (0U) -#define AUDIO_PEQ_06_B0_LEN (20U) -#define AUDIO_PEQ_06_B0_MSK (((1U << AUDIO_PEQ_06_B0_LEN) - 1) << AUDIO_PEQ_06_B0_POS) -#define AUDIO_PEQ_06_B0_UMSK (~(((1U << AUDIO_PEQ_06_B0_LEN) - 1) << AUDIO_PEQ_06_B0_POS)) -#define AUDIO_PEQ_06_BYP AUDIO_PEQ_06_BYP -#define AUDIO_PEQ_06_BYP_POS (20U) -#define AUDIO_PEQ_06_BYP_LEN (1U) -#define AUDIO_PEQ_06_BYP_MSK (((1U << AUDIO_PEQ_06_BYP_LEN) - 1) << AUDIO_PEQ_06_BYP_POS) -#define AUDIO_PEQ_06_BYP_UMSK (~(((1U << AUDIO_PEQ_06_BYP_LEN) - 1) << AUDIO_PEQ_06_BYP_POS)) -#define AUDIO_PEQ_06_QFMT AUDIO_PEQ_06_QFMT -#define AUDIO_PEQ_06_QFMT_POS (21U) -#define AUDIO_PEQ_06_QFMT_LEN (1U) -#define AUDIO_PEQ_06_QFMT_MSK (((1U << AUDIO_PEQ_06_QFMT_LEN) - 1) << AUDIO_PEQ_06_QFMT_POS) -#define AUDIO_PEQ_06_QFMT_UMSK (~(((1U << AUDIO_PEQ_06_QFMT_LEN) - 1) << AUDIO_PEQ_06_QFMT_POS)) - -/* 0x27C : peq_06_b1 */ -#define AUDIO_PEQ_06_B1_OFFSET (0x27C) -#define AUDIO_PEQ_06_B1 AUDIO_PEQ_06_B1 -#define AUDIO_PEQ_06_B1_POS (0U) -#define AUDIO_PEQ_06_B1_LEN (20U) -#define AUDIO_PEQ_06_B1_MSK (((1U << AUDIO_PEQ_06_B1_LEN) - 1) << AUDIO_PEQ_06_B1_POS) -#define AUDIO_PEQ_06_B1_UMSK (~(((1U << AUDIO_PEQ_06_B1_LEN) - 1) << AUDIO_PEQ_06_B1_POS)) - -/* 0x280 : peq_06_b2 */ -#define AUDIO_PEQ_06_B2_OFFSET (0x280) -#define AUDIO_PEQ_06_B2 AUDIO_PEQ_06_B2 -#define AUDIO_PEQ_06_B2_POS (0U) -#define AUDIO_PEQ_06_B2_LEN (20U) -#define AUDIO_PEQ_06_B2_MSK (((1U << AUDIO_PEQ_06_B2_LEN) - 1) << AUDIO_PEQ_06_B2_POS) -#define AUDIO_PEQ_06_B2_UMSK (~(((1U << AUDIO_PEQ_06_B2_LEN) - 1) << AUDIO_PEQ_06_B2_POS)) - -/* 0x284 : peq_06_a1 */ -#define AUDIO_PEQ_06_A1_OFFSET (0x284) -#define AUDIO_PEQ_06_A1 AUDIO_PEQ_06_A1 -#define AUDIO_PEQ_06_A1_POS (0U) -#define AUDIO_PEQ_06_A1_LEN (20U) -#define AUDIO_PEQ_06_A1_MSK (((1U << AUDIO_PEQ_06_A1_LEN) - 1) << AUDIO_PEQ_06_A1_POS) -#define AUDIO_PEQ_06_A1_UMSK (~(((1U << AUDIO_PEQ_06_A1_LEN) - 1) << AUDIO_PEQ_06_A1_POS)) - -/* 0x288 : peq_06_a2 */ -#define AUDIO_PEQ_06_A2_OFFSET (0x288) -#define AUDIO_PEQ_06_A2 AUDIO_PEQ_06_A2 -#define AUDIO_PEQ_06_A2_POS (0U) -#define AUDIO_PEQ_06_A2_LEN (20U) -#define AUDIO_PEQ_06_A2_MSK (((1U << AUDIO_PEQ_06_A2_LEN) - 1) << AUDIO_PEQ_06_A2_POS) -#define AUDIO_PEQ_06_A2_UMSK (~(((1U << AUDIO_PEQ_06_A2_LEN) - 1) << AUDIO_PEQ_06_A2_POS)) - -/* 0x28C : peq_07_b0 */ -#define AUDIO_PEQ_07_B0_OFFSET (0x28C) -#define AUDIO_PEQ_07_B0 AUDIO_PEQ_07_B0 -#define AUDIO_PEQ_07_B0_POS (0U) -#define AUDIO_PEQ_07_B0_LEN (20U) -#define AUDIO_PEQ_07_B0_MSK (((1U << AUDIO_PEQ_07_B0_LEN) - 1) << AUDIO_PEQ_07_B0_POS) -#define AUDIO_PEQ_07_B0_UMSK (~(((1U << AUDIO_PEQ_07_B0_LEN) - 1) << AUDIO_PEQ_07_B0_POS)) -#define AUDIO_PEQ_07_BYP AUDIO_PEQ_07_BYP -#define AUDIO_PEQ_07_BYP_POS (20U) -#define AUDIO_PEQ_07_BYP_LEN (1U) -#define AUDIO_PEQ_07_BYP_MSK (((1U << AUDIO_PEQ_07_BYP_LEN) - 1) << AUDIO_PEQ_07_BYP_POS) -#define AUDIO_PEQ_07_BYP_UMSK (~(((1U << AUDIO_PEQ_07_BYP_LEN) - 1) << AUDIO_PEQ_07_BYP_POS)) -#define AUDIO_PEQ_07_QFMT AUDIO_PEQ_07_QFMT -#define AUDIO_PEQ_07_QFMT_POS (21U) -#define AUDIO_PEQ_07_QFMT_LEN (1U) -#define AUDIO_PEQ_07_QFMT_MSK (((1U << AUDIO_PEQ_07_QFMT_LEN) - 1) << AUDIO_PEQ_07_QFMT_POS) -#define AUDIO_PEQ_07_QFMT_UMSK (~(((1U << AUDIO_PEQ_07_QFMT_LEN) - 1) << AUDIO_PEQ_07_QFMT_POS)) - -/* 0x290 : peq_07_b1 */ -#define AUDIO_PEQ_07_B1_OFFSET (0x290) -#define AUDIO_PEQ_07_B1 AUDIO_PEQ_07_B1 -#define AUDIO_PEQ_07_B1_POS (0U) -#define AUDIO_PEQ_07_B1_LEN (20U) -#define AUDIO_PEQ_07_B1_MSK (((1U << AUDIO_PEQ_07_B1_LEN) - 1) << AUDIO_PEQ_07_B1_POS) -#define AUDIO_PEQ_07_B1_UMSK (~(((1U << AUDIO_PEQ_07_B1_LEN) - 1) << AUDIO_PEQ_07_B1_POS)) - -/* 0x294 : peq_07_b2 */ -#define AUDIO_PEQ_07_B2_OFFSET (0x294) -#define AUDIO_PEQ_07_B2 AUDIO_PEQ_07_B2 -#define AUDIO_PEQ_07_B2_POS (0U) -#define AUDIO_PEQ_07_B2_LEN (20U) -#define AUDIO_PEQ_07_B2_MSK (((1U << AUDIO_PEQ_07_B2_LEN) - 1) << AUDIO_PEQ_07_B2_POS) -#define AUDIO_PEQ_07_B2_UMSK (~(((1U << AUDIO_PEQ_07_B2_LEN) - 1) << AUDIO_PEQ_07_B2_POS)) - -/* 0x298 : peq_07_a1 */ -#define AUDIO_PEQ_07_A1_OFFSET (0x298) -#define AUDIO_PEQ_07_A1 AUDIO_PEQ_07_A1 -#define AUDIO_PEQ_07_A1_POS (0U) -#define AUDIO_PEQ_07_A1_LEN (20U) -#define AUDIO_PEQ_07_A1_MSK (((1U << AUDIO_PEQ_07_A1_LEN) - 1) << AUDIO_PEQ_07_A1_POS) -#define AUDIO_PEQ_07_A1_UMSK (~(((1U << AUDIO_PEQ_07_A1_LEN) - 1) << AUDIO_PEQ_07_A1_POS)) - -/* 0x29C : peq_07_a2 */ -#define AUDIO_PEQ_07_A2_OFFSET (0x29C) -#define AUDIO_PEQ_07_A2 AUDIO_PEQ_07_A2 -#define AUDIO_PEQ_07_A2_POS (0U) -#define AUDIO_PEQ_07_A2_LEN (20U) -#define AUDIO_PEQ_07_A2_MSK (((1U << AUDIO_PEQ_07_A2_LEN) - 1) << AUDIO_PEQ_07_A2_POS) -#define AUDIO_PEQ_07_A2_UMSK (~(((1U << AUDIO_PEQ_07_A2_LEN) - 1) << AUDIO_PEQ_07_A2_POS)) - -/* 0x2A0 : peq_08_b0 */ -#define AUDIO_PEQ_08_B0_OFFSET (0x2A0) -#define AUDIO_PEQ_08_B0 AUDIO_PEQ_08_B0 -#define AUDIO_PEQ_08_B0_POS (0U) -#define AUDIO_PEQ_08_B0_LEN (20U) -#define AUDIO_PEQ_08_B0_MSK (((1U << AUDIO_PEQ_08_B0_LEN) - 1) << AUDIO_PEQ_08_B0_POS) -#define AUDIO_PEQ_08_B0_UMSK (~(((1U << AUDIO_PEQ_08_B0_LEN) - 1) << AUDIO_PEQ_08_B0_POS)) -#define AUDIO_PEQ_08_BYP AUDIO_PEQ_08_BYP -#define AUDIO_PEQ_08_BYP_POS (20U) -#define AUDIO_PEQ_08_BYP_LEN (1U) -#define AUDIO_PEQ_08_BYP_MSK (((1U << AUDIO_PEQ_08_BYP_LEN) - 1) << AUDIO_PEQ_08_BYP_POS) -#define AUDIO_PEQ_08_BYP_UMSK (~(((1U << AUDIO_PEQ_08_BYP_LEN) - 1) << AUDIO_PEQ_08_BYP_POS)) -#define AUDIO_PEQ_08_QFMT AUDIO_PEQ_08_QFMT -#define AUDIO_PEQ_08_QFMT_POS (21U) -#define AUDIO_PEQ_08_QFMT_LEN (1U) -#define AUDIO_PEQ_08_QFMT_MSK (((1U << AUDIO_PEQ_08_QFMT_LEN) - 1) << AUDIO_PEQ_08_QFMT_POS) -#define AUDIO_PEQ_08_QFMT_UMSK (~(((1U << AUDIO_PEQ_08_QFMT_LEN) - 1) << AUDIO_PEQ_08_QFMT_POS)) - -/* 0x2A4 : peq_08_b1 */ -#define AUDIO_PEQ_08_B1_OFFSET (0x2A4) -#define AUDIO_PEQ_08_B1 AUDIO_PEQ_08_B1 -#define AUDIO_PEQ_08_B1_POS (0U) -#define AUDIO_PEQ_08_B1_LEN (20U) -#define AUDIO_PEQ_08_B1_MSK (((1U << AUDIO_PEQ_08_B1_LEN) - 1) << AUDIO_PEQ_08_B1_POS) -#define AUDIO_PEQ_08_B1_UMSK (~(((1U << AUDIO_PEQ_08_B1_LEN) - 1) << AUDIO_PEQ_08_B1_POS)) - -/* 0x2A8 : peq_08_b2 */ -#define AUDIO_PEQ_08_B2_OFFSET (0x2A8) -#define AUDIO_PEQ_08_B2 AUDIO_PEQ_08_B2 -#define AUDIO_PEQ_08_B2_POS (0U) -#define AUDIO_PEQ_08_B2_LEN (20U) -#define AUDIO_PEQ_08_B2_MSK (((1U << AUDIO_PEQ_08_B2_LEN) - 1) << AUDIO_PEQ_08_B2_POS) -#define AUDIO_PEQ_08_B2_UMSK (~(((1U << AUDIO_PEQ_08_B2_LEN) - 1) << AUDIO_PEQ_08_B2_POS)) - -/* 0x2AC : peq_08_a1 */ -#define AUDIO_PEQ_08_A1_OFFSET (0x2AC) -#define AUDIO_PEQ_08_A1 AUDIO_PEQ_08_A1 -#define AUDIO_PEQ_08_A1_POS (0U) -#define AUDIO_PEQ_08_A1_LEN (20U) -#define AUDIO_PEQ_08_A1_MSK (((1U << AUDIO_PEQ_08_A1_LEN) - 1) << AUDIO_PEQ_08_A1_POS) -#define AUDIO_PEQ_08_A1_UMSK (~(((1U << AUDIO_PEQ_08_A1_LEN) - 1) << AUDIO_PEQ_08_A1_POS)) - -/* 0x2B0 : peq_08_a2 */ -#define AUDIO_PEQ_08_A2_OFFSET (0x2B0) -#define AUDIO_PEQ_08_A2 AUDIO_PEQ_08_A2 -#define AUDIO_PEQ_08_A2_POS (0U) -#define AUDIO_PEQ_08_A2_LEN (20U) -#define AUDIO_PEQ_08_A2_MSK (((1U << AUDIO_PEQ_08_A2_LEN) - 1) << AUDIO_PEQ_08_A2_POS) -#define AUDIO_PEQ_08_A2_UMSK (~(((1U << AUDIO_PEQ_08_A2_LEN) - 1) << AUDIO_PEQ_08_A2_POS)) - -/* 0x2B4 : peq_09_b0 */ -#define AUDIO_PEQ_09_B0_OFFSET (0x2B4) -#define AUDIO_PEQ_09_B0 AUDIO_PEQ_09_B0 -#define AUDIO_PEQ_09_B0_POS (0U) -#define AUDIO_PEQ_09_B0_LEN (20U) -#define AUDIO_PEQ_09_B0_MSK (((1U << AUDIO_PEQ_09_B0_LEN) - 1) << AUDIO_PEQ_09_B0_POS) -#define AUDIO_PEQ_09_B0_UMSK (~(((1U << AUDIO_PEQ_09_B0_LEN) - 1) << AUDIO_PEQ_09_B0_POS)) -#define AUDIO_PEQ_09_BYP AUDIO_PEQ_09_BYP -#define AUDIO_PEQ_09_BYP_POS (20U) -#define AUDIO_PEQ_09_BYP_LEN (1U) -#define AUDIO_PEQ_09_BYP_MSK (((1U << AUDIO_PEQ_09_BYP_LEN) - 1) << AUDIO_PEQ_09_BYP_POS) -#define AUDIO_PEQ_09_BYP_UMSK (~(((1U << AUDIO_PEQ_09_BYP_LEN) - 1) << AUDIO_PEQ_09_BYP_POS)) -#define AUDIO_PEQ_09_QFMT AUDIO_PEQ_09_QFMT -#define AUDIO_PEQ_09_QFMT_POS (21U) -#define AUDIO_PEQ_09_QFMT_LEN (1U) -#define AUDIO_PEQ_09_QFMT_MSK (((1U << AUDIO_PEQ_09_QFMT_LEN) - 1) << AUDIO_PEQ_09_QFMT_POS) -#define AUDIO_PEQ_09_QFMT_UMSK (~(((1U << AUDIO_PEQ_09_QFMT_LEN) - 1) << AUDIO_PEQ_09_QFMT_POS)) - -/* 0x2B8 : peq_09_b1 */ -#define AUDIO_PEQ_09_B1_OFFSET (0x2B8) -#define AUDIO_PEQ_09_B1 AUDIO_PEQ_09_B1 -#define AUDIO_PEQ_09_B1_POS (0U) -#define AUDIO_PEQ_09_B1_LEN (20U) -#define AUDIO_PEQ_09_B1_MSK (((1U << AUDIO_PEQ_09_B1_LEN) - 1) << AUDIO_PEQ_09_B1_POS) -#define AUDIO_PEQ_09_B1_UMSK (~(((1U << AUDIO_PEQ_09_B1_LEN) - 1) << AUDIO_PEQ_09_B1_POS)) - -/* 0x2BC : peq_09_b2 */ -#define AUDIO_PEQ_09_B2_OFFSET (0x2BC) -#define AUDIO_PEQ_09_B2 AUDIO_PEQ_09_B2 -#define AUDIO_PEQ_09_B2_POS (0U) -#define AUDIO_PEQ_09_B2_LEN (20U) -#define AUDIO_PEQ_09_B2_MSK (((1U << AUDIO_PEQ_09_B2_LEN) - 1) << AUDIO_PEQ_09_B2_POS) -#define AUDIO_PEQ_09_B2_UMSK (~(((1U << AUDIO_PEQ_09_B2_LEN) - 1) << AUDIO_PEQ_09_B2_POS)) - -/* 0x2C0 : peq_09_a1 */ -#define AUDIO_PEQ_09_A1_OFFSET (0x2C0) -#define AUDIO_PEQ_09_A1 AUDIO_PEQ_09_A1 -#define AUDIO_PEQ_09_A1_POS (0U) -#define AUDIO_PEQ_09_A1_LEN (20U) -#define AUDIO_PEQ_09_A1_MSK (((1U << AUDIO_PEQ_09_A1_LEN) - 1) << AUDIO_PEQ_09_A1_POS) -#define AUDIO_PEQ_09_A1_UMSK (~(((1U << AUDIO_PEQ_09_A1_LEN) - 1) << AUDIO_PEQ_09_A1_POS)) - -/* 0x2C4 : peq_09_a2 */ -#define AUDIO_PEQ_09_A2_OFFSET (0x2C4) -#define AUDIO_PEQ_09_A2 AUDIO_PEQ_09_A2 -#define AUDIO_PEQ_09_A2_POS (0U) -#define AUDIO_PEQ_09_A2_LEN (20U) -#define AUDIO_PEQ_09_A2_MSK (((1U << AUDIO_PEQ_09_A2_LEN) - 1) << AUDIO_PEQ_09_A2_POS) -#define AUDIO_PEQ_09_A2_UMSK (~(((1U << AUDIO_PEQ_09_A2_LEN) - 1) << AUDIO_PEQ_09_A2_POS)) - -/* 0x2C8 : peq_10_b0 */ -#define AUDIO_PEQ_10_B0_OFFSET (0x2C8) -#define AUDIO_PEQ_10_B0 AUDIO_PEQ_10_B0 -#define AUDIO_PEQ_10_B0_POS (0U) -#define AUDIO_PEQ_10_B0_LEN (20U) -#define AUDIO_PEQ_10_B0_MSK (((1U << AUDIO_PEQ_10_B0_LEN) - 1) << AUDIO_PEQ_10_B0_POS) -#define AUDIO_PEQ_10_B0_UMSK (~(((1U << AUDIO_PEQ_10_B0_LEN) - 1) << AUDIO_PEQ_10_B0_POS)) -#define AUDIO_PEQ_10_BYP AUDIO_PEQ_10_BYP -#define AUDIO_PEQ_10_BYP_POS (20U) -#define AUDIO_PEQ_10_BYP_LEN (1U) -#define AUDIO_PEQ_10_BYP_MSK (((1U << AUDIO_PEQ_10_BYP_LEN) - 1) << AUDIO_PEQ_10_BYP_POS) -#define AUDIO_PEQ_10_BYP_UMSK (~(((1U << AUDIO_PEQ_10_BYP_LEN) - 1) << AUDIO_PEQ_10_BYP_POS)) -#define AUDIO_PEQ_10_QFMT AUDIO_PEQ_10_QFMT -#define AUDIO_PEQ_10_QFMT_POS (21U) -#define AUDIO_PEQ_10_QFMT_LEN (1U) -#define AUDIO_PEQ_10_QFMT_MSK (((1U << AUDIO_PEQ_10_QFMT_LEN) - 1) << AUDIO_PEQ_10_QFMT_POS) -#define AUDIO_PEQ_10_QFMT_UMSK (~(((1U << AUDIO_PEQ_10_QFMT_LEN) - 1) << AUDIO_PEQ_10_QFMT_POS)) - -/* 0x2CC : peq_10_b1 */ -#define AUDIO_PEQ_10_B1_OFFSET (0x2CC) -#define AUDIO_PEQ_10_B1 AUDIO_PEQ_10_B1 -#define AUDIO_PEQ_10_B1_POS (0U) -#define AUDIO_PEQ_10_B1_LEN (20U) -#define AUDIO_PEQ_10_B1_MSK (((1U << AUDIO_PEQ_10_B1_LEN) - 1) << AUDIO_PEQ_10_B1_POS) -#define AUDIO_PEQ_10_B1_UMSK (~(((1U << AUDIO_PEQ_10_B1_LEN) - 1) << AUDIO_PEQ_10_B1_POS)) - -/* 0x2D0 : peq_10_b2 */ -#define AUDIO_PEQ_10_B2_OFFSET (0x2D0) -#define AUDIO_PEQ_10_B2 AUDIO_PEQ_10_B2 -#define AUDIO_PEQ_10_B2_POS (0U) -#define AUDIO_PEQ_10_B2_LEN (20U) -#define AUDIO_PEQ_10_B2_MSK (((1U << AUDIO_PEQ_10_B2_LEN) - 1) << AUDIO_PEQ_10_B2_POS) -#define AUDIO_PEQ_10_B2_UMSK (~(((1U << AUDIO_PEQ_10_B2_LEN) - 1) << AUDIO_PEQ_10_B2_POS)) - -/* 0x2D4 : peq_10_a1 */ -#define AUDIO_PEQ_10_A1_OFFSET (0x2D4) -#define AUDIO_PEQ_10_A1 AUDIO_PEQ_10_A1 -#define AUDIO_PEQ_10_A1_POS (0U) -#define AUDIO_PEQ_10_A1_LEN (20U) -#define AUDIO_PEQ_10_A1_MSK (((1U << AUDIO_PEQ_10_A1_LEN) - 1) << AUDIO_PEQ_10_A1_POS) -#define AUDIO_PEQ_10_A1_UMSK (~(((1U << AUDIO_PEQ_10_A1_LEN) - 1) << AUDIO_PEQ_10_A1_POS)) - -/* 0x2D8 : peq_10_a2 */ -#define AUDIO_PEQ_10_A2_OFFSET (0x2D8) -#define AUDIO_PEQ_10_A2 AUDIO_PEQ_10_A2 -#define AUDIO_PEQ_10_A2_POS (0U) -#define AUDIO_PEQ_10_A2_LEN (20U) -#define AUDIO_PEQ_10_A2_MSK (((1U << AUDIO_PEQ_10_A2_LEN) - 1) << AUDIO_PEQ_10_A2_POS) -#define AUDIO_PEQ_10_A2_UMSK (~(((1U << AUDIO_PEQ_10_A2_LEN) - 1) << AUDIO_PEQ_10_A2_POS)) - -/* 0x2DC : peq_11_b0 */ -#define AUDIO_PEQ_11_B0_OFFSET (0x2DC) -#define AUDIO_PEQ_11_B0 AUDIO_PEQ_11_B0 -#define AUDIO_PEQ_11_B0_POS (0U) -#define AUDIO_PEQ_11_B0_LEN (20U) -#define AUDIO_PEQ_11_B0_MSK (((1U << AUDIO_PEQ_11_B0_LEN) - 1) << AUDIO_PEQ_11_B0_POS) -#define AUDIO_PEQ_11_B0_UMSK (~(((1U << AUDIO_PEQ_11_B0_LEN) - 1) << AUDIO_PEQ_11_B0_POS)) -#define AUDIO_PEQ_11_BYP AUDIO_PEQ_11_BYP -#define AUDIO_PEQ_11_BYP_POS (20U) -#define AUDIO_PEQ_11_BYP_LEN (1U) -#define AUDIO_PEQ_11_BYP_MSK (((1U << AUDIO_PEQ_11_BYP_LEN) - 1) << AUDIO_PEQ_11_BYP_POS) -#define AUDIO_PEQ_11_BYP_UMSK (~(((1U << AUDIO_PEQ_11_BYP_LEN) - 1) << AUDIO_PEQ_11_BYP_POS)) -#define AUDIO_PEQ_11_QFMT AUDIO_PEQ_11_QFMT -#define AUDIO_PEQ_11_QFMT_POS (21U) -#define AUDIO_PEQ_11_QFMT_LEN (1U) -#define AUDIO_PEQ_11_QFMT_MSK (((1U << AUDIO_PEQ_11_QFMT_LEN) - 1) << AUDIO_PEQ_11_QFMT_POS) -#define AUDIO_PEQ_11_QFMT_UMSK (~(((1U << AUDIO_PEQ_11_QFMT_LEN) - 1) << AUDIO_PEQ_11_QFMT_POS)) - -/* 0x2E0 : peq_11_b1 */ -#define AUDIO_PEQ_11_B1_OFFSET (0x2E0) -#define AUDIO_PEQ_11_B1 AUDIO_PEQ_11_B1 -#define AUDIO_PEQ_11_B1_POS (0U) -#define AUDIO_PEQ_11_B1_LEN (20U) -#define AUDIO_PEQ_11_B1_MSK (((1U << AUDIO_PEQ_11_B1_LEN) - 1) << AUDIO_PEQ_11_B1_POS) -#define AUDIO_PEQ_11_B1_UMSK (~(((1U << AUDIO_PEQ_11_B1_LEN) - 1) << AUDIO_PEQ_11_B1_POS)) - -/* 0x2E4 : peq_11_b2 */ -#define AUDIO_PEQ_11_B2_OFFSET (0x2E4) -#define AUDIO_PEQ_11_B2 AUDIO_PEQ_11_B2 -#define AUDIO_PEQ_11_B2_POS (0U) -#define AUDIO_PEQ_11_B2_LEN (20U) -#define AUDIO_PEQ_11_B2_MSK (((1U << AUDIO_PEQ_11_B2_LEN) - 1) << AUDIO_PEQ_11_B2_POS) -#define AUDIO_PEQ_11_B2_UMSK (~(((1U << AUDIO_PEQ_11_B2_LEN) - 1) << AUDIO_PEQ_11_B2_POS)) - -/* 0x2E8 : peq_11_a1 */ -#define AUDIO_PEQ_11_A1_OFFSET (0x2E8) -#define AUDIO_PEQ_11_A1 AUDIO_PEQ_11_A1 -#define AUDIO_PEQ_11_A1_POS (0U) -#define AUDIO_PEQ_11_A1_LEN (20U) -#define AUDIO_PEQ_11_A1_MSK (((1U << AUDIO_PEQ_11_A1_LEN) - 1) << AUDIO_PEQ_11_A1_POS) -#define AUDIO_PEQ_11_A1_UMSK (~(((1U << AUDIO_PEQ_11_A1_LEN) - 1) << AUDIO_PEQ_11_A1_POS)) - -/* 0x2EC : peq_11_a2 */ -#define AUDIO_PEQ_11_A2_OFFSET (0x2EC) -#define AUDIO_PEQ_11_A2 AUDIO_PEQ_11_A2 -#define AUDIO_PEQ_11_A2_POS (0U) -#define AUDIO_PEQ_11_A2_LEN (20U) -#define AUDIO_PEQ_11_A2_MSK (((1U << AUDIO_PEQ_11_A2_LEN) - 1) << AUDIO_PEQ_11_A2_POS) -#define AUDIO_PEQ_11_A2_UMSK (~(((1U << AUDIO_PEQ_11_A2_LEN) - 1) << AUDIO_PEQ_11_A2_POS)) - -/* 0x2F0 : peq_12_b0 */ -#define AUDIO_PEQ_12_B0_OFFSET (0x2F0) -#define AUDIO_PEQ_12_B0 AUDIO_PEQ_12_B0 -#define AUDIO_PEQ_12_B0_POS (0U) -#define AUDIO_PEQ_12_B0_LEN (20U) -#define AUDIO_PEQ_12_B0_MSK (((1U << AUDIO_PEQ_12_B0_LEN) - 1) << AUDIO_PEQ_12_B0_POS) -#define AUDIO_PEQ_12_B0_UMSK (~(((1U << AUDIO_PEQ_12_B0_LEN) - 1) << AUDIO_PEQ_12_B0_POS)) -#define AUDIO_PEQ_12_BYP AUDIO_PEQ_12_BYP -#define AUDIO_PEQ_12_BYP_POS (20U) -#define AUDIO_PEQ_12_BYP_LEN (1U) -#define AUDIO_PEQ_12_BYP_MSK (((1U << AUDIO_PEQ_12_BYP_LEN) - 1) << AUDIO_PEQ_12_BYP_POS) -#define AUDIO_PEQ_12_BYP_UMSK (~(((1U << AUDIO_PEQ_12_BYP_LEN) - 1) << AUDIO_PEQ_12_BYP_POS)) -#define AUDIO_PEQ_12_QFMT AUDIO_PEQ_12_QFMT -#define AUDIO_PEQ_12_QFMT_POS (21U) -#define AUDIO_PEQ_12_QFMT_LEN (1U) -#define AUDIO_PEQ_12_QFMT_MSK (((1U << AUDIO_PEQ_12_QFMT_LEN) - 1) << AUDIO_PEQ_12_QFMT_POS) -#define AUDIO_PEQ_12_QFMT_UMSK (~(((1U << AUDIO_PEQ_12_QFMT_LEN) - 1) << AUDIO_PEQ_12_QFMT_POS)) - -/* 0x2F4 : peq_12_b1 */ -#define AUDIO_PEQ_12_B1_OFFSET (0x2F4) -#define AUDIO_PEQ_12_B1 AUDIO_PEQ_12_B1 -#define AUDIO_PEQ_12_B1_POS (0U) -#define AUDIO_PEQ_12_B1_LEN (20U) -#define AUDIO_PEQ_12_B1_MSK (((1U << AUDIO_PEQ_12_B1_LEN) - 1) << AUDIO_PEQ_12_B1_POS) -#define AUDIO_PEQ_12_B1_UMSK (~(((1U << AUDIO_PEQ_12_B1_LEN) - 1) << AUDIO_PEQ_12_B1_POS)) - -/* 0x2F8 : peq_12_b2 */ -#define AUDIO_PEQ_12_B2_OFFSET (0x2F8) -#define AUDIO_PEQ_12_B2 AUDIO_PEQ_12_B2 -#define AUDIO_PEQ_12_B2_POS (0U) -#define AUDIO_PEQ_12_B2_LEN (20U) -#define AUDIO_PEQ_12_B2_MSK (((1U << AUDIO_PEQ_12_B2_LEN) - 1) << AUDIO_PEQ_12_B2_POS) -#define AUDIO_PEQ_12_B2_UMSK (~(((1U << AUDIO_PEQ_12_B2_LEN) - 1) << AUDIO_PEQ_12_B2_POS)) - -/* 0x2FC : peq_12_a1 */ -#define AUDIO_PEQ_12_A1_OFFSET (0x2FC) -#define AUDIO_PEQ_12_A1 AUDIO_PEQ_12_A1 -#define AUDIO_PEQ_12_A1_POS (0U) -#define AUDIO_PEQ_12_A1_LEN (20U) -#define AUDIO_PEQ_12_A1_MSK (((1U << AUDIO_PEQ_12_A1_LEN) - 1) << AUDIO_PEQ_12_A1_POS) -#define AUDIO_PEQ_12_A1_UMSK (~(((1U << AUDIO_PEQ_12_A1_LEN) - 1) << AUDIO_PEQ_12_A1_POS)) - -/* 0x300 : peq_12_a2 */ -#define AUDIO_PEQ_12_A2_OFFSET (0x300) -#define AUDIO_PEQ_12_A2 AUDIO_PEQ_12_A2 -#define AUDIO_PEQ_12_A2_POS (0U) -#define AUDIO_PEQ_12_A2_LEN (20U) -#define AUDIO_PEQ_12_A2_MSK (((1U << AUDIO_PEQ_12_A2_LEN) - 1) << AUDIO_PEQ_12_A2_POS) -#define AUDIO_PEQ_12_A2_UMSK (~(((1U << AUDIO_PEQ_12_A2_LEN) - 1) << AUDIO_PEQ_12_A2_POS)) - -/* 0x304 : peq_13_b0 */ -#define AUDIO_PEQ_13_B0_OFFSET (0x304) -#define AUDIO_PEQ_13_B0 AUDIO_PEQ_13_B0 -#define AUDIO_PEQ_13_B0_POS (0U) -#define AUDIO_PEQ_13_B0_LEN (20U) -#define AUDIO_PEQ_13_B0_MSK (((1U << AUDIO_PEQ_13_B0_LEN) - 1) << AUDIO_PEQ_13_B0_POS) -#define AUDIO_PEQ_13_B0_UMSK (~(((1U << AUDIO_PEQ_13_B0_LEN) - 1) << AUDIO_PEQ_13_B0_POS)) -#define AUDIO_PEQ_13_BYP AUDIO_PEQ_13_BYP -#define AUDIO_PEQ_13_BYP_POS (20U) -#define AUDIO_PEQ_13_BYP_LEN (1U) -#define AUDIO_PEQ_13_BYP_MSK (((1U << AUDIO_PEQ_13_BYP_LEN) - 1) << AUDIO_PEQ_13_BYP_POS) -#define AUDIO_PEQ_13_BYP_UMSK (~(((1U << AUDIO_PEQ_13_BYP_LEN) - 1) << AUDIO_PEQ_13_BYP_POS)) -#define AUDIO_PEQ_13_QFMT AUDIO_PEQ_13_QFMT -#define AUDIO_PEQ_13_QFMT_POS (21U) -#define AUDIO_PEQ_13_QFMT_LEN (1U) -#define AUDIO_PEQ_13_QFMT_MSK (((1U << AUDIO_PEQ_13_QFMT_LEN) - 1) << AUDIO_PEQ_13_QFMT_POS) -#define AUDIO_PEQ_13_QFMT_UMSK (~(((1U << AUDIO_PEQ_13_QFMT_LEN) - 1) << AUDIO_PEQ_13_QFMT_POS)) - -/* 0x308 : peq_13_b1 */ -#define AUDIO_PEQ_13_B1_OFFSET (0x308) -#define AUDIO_PEQ_13_B1 AUDIO_PEQ_13_B1 -#define AUDIO_PEQ_13_B1_POS (0U) -#define AUDIO_PEQ_13_B1_LEN (20U) -#define AUDIO_PEQ_13_B1_MSK (((1U << AUDIO_PEQ_13_B1_LEN) - 1) << AUDIO_PEQ_13_B1_POS) -#define AUDIO_PEQ_13_B1_UMSK (~(((1U << AUDIO_PEQ_13_B1_LEN) - 1) << AUDIO_PEQ_13_B1_POS)) - -/* 0x30C : peq_13_b2 */ -#define AUDIO_PEQ_13_B2_OFFSET (0x30C) -#define AUDIO_PEQ_13_B2 AUDIO_PEQ_13_B2 -#define AUDIO_PEQ_13_B2_POS (0U) -#define AUDIO_PEQ_13_B2_LEN (20U) -#define AUDIO_PEQ_13_B2_MSK (((1U << AUDIO_PEQ_13_B2_LEN) - 1) << AUDIO_PEQ_13_B2_POS) -#define AUDIO_PEQ_13_B2_UMSK (~(((1U << AUDIO_PEQ_13_B2_LEN) - 1) << AUDIO_PEQ_13_B2_POS)) - -/* 0x310 : peq_13_a1 */ -#define AUDIO_PEQ_13_A1_OFFSET (0x310) -#define AUDIO_PEQ_13_A1 AUDIO_PEQ_13_A1 -#define AUDIO_PEQ_13_A1_POS (0U) -#define AUDIO_PEQ_13_A1_LEN (20U) -#define AUDIO_PEQ_13_A1_MSK (((1U << AUDIO_PEQ_13_A1_LEN) - 1) << AUDIO_PEQ_13_A1_POS) -#define AUDIO_PEQ_13_A1_UMSK (~(((1U << AUDIO_PEQ_13_A1_LEN) - 1) << AUDIO_PEQ_13_A1_POS)) - -/* 0x314 : peq_13_a2 */ -#define AUDIO_PEQ_13_A2_OFFSET (0x314) -#define AUDIO_PEQ_13_A2 AUDIO_PEQ_13_A2 -#define AUDIO_PEQ_13_A2_POS (0U) -#define AUDIO_PEQ_13_A2_LEN (20U) -#define AUDIO_PEQ_13_A2_MSK (((1U << AUDIO_PEQ_13_A2_LEN) - 1) << AUDIO_PEQ_13_A2_POS) -#define AUDIO_PEQ_13_A2_UMSK (~(((1U << AUDIO_PEQ_13_A2_LEN) - 1) << AUDIO_PEQ_13_A2_POS)) - -/* 0x318 : peq_14_b0 */ -#define AUDIO_PEQ_14_B0_OFFSET (0x318) -#define AUDIO_PEQ_14_B0 AUDIO_PEQ_14_B0 -#define AUDIO_PEQ_14_B0_POS (0U) -#define AUDIO_PEQ_14_B0_LEN (20U) -#define AUDIO_PEQ_14_B0_MSK (((1U << AUDIO_PEQ_14_B0_LEN) - 1) << AUDIO_PEQ_14_B0_POS) -#define AUDIO_PEQ_14_B0_UMSK (~(((1U << AUDIO_PEQ_14_B0_LEN) - 1) << AUDIO_PEQ_14_B0_POS)) -#define AUDIO_PEQ_14_BYP AUDIO_PEQ_14_BYP -#define AUDIO_PEQ_14_BYP_POS (20U) -#define AUDIO_PEQ_14_BYP_LEN (1U) -#define AUDIO_PEQ_14_BYP_MSK (((1U << AUDIO_PEQ_14_BYP_LEN) - 1) << AUDIO_PEQ_14_BYP_POS) -#define AUDIO_PEQ_14_BYP_UMSK (~(((1U << AUDIO_PEQ_14_BYP_LEN) - 1) << AUDIO_PEQ_14_BYP_POS)) -#define AUDIO_PEQ_14_QFMT AUDIO_PEQ_14_QFMT -#define AUDIO_PEQ_14_QFMT_POS (21U) -#define AUDIO_PEQ_14_QFMT_LEN (1U) -#define AUDIO_PEQ_14_QFMT_MSK (((1U << AUDIO_PEQ_14_QFMT_LEN) - 1) << AUDIO_PEQ_14_QFMT_POS) -#define AUDIO_PEQ_14_QFMT_UMSK (~(((1U << AUDIO_PEQ_14_QFMT_LEN) - 1) << AUDIO_PEQ_14_QFMT_POS)) - -/* 0x31C : peq_14_b1 */ -#define AUDIO_PEQ_14_B1_OFFSET (0x31C) -#define AUDIO_PEQ_14_B1 AUDIO_PEQ_14_B1 -#define AUDIO_PEQ_14_B1_POS (0U) -#define AUDIO_PEQ_14_B1_LEN (20U) -#define AUDIO_PEQ_14_B1_MSK (((1U << AUDIO_PEQ_14_B1_LEN) - 1) << AUDIO_PEQ_14_B1_POS) -#define AUDIO_PEQ_14_B1_UMSK (~(((1U << AUDIO_PEQ_14_B1_LEN) - 1) << AUDIO_PEQ_14_B1_POS)) - -/* 0x320 : peq_14_b2 */ -#define AUDIO_PEQ_14_B2_OFFSET (0x320) -#define AUDIO_PEQ_14_B2 AUDIO_PEQ_14_B2 -#define AUDIO_PEQ_14_B2_POS (0U) -#define AUDIO_PEQ_14_B2_LEN (20U) -#define AUDIO_PEQ_14_B2_MSK (((1U << AUDIO_PEQ_14_B2_LEN) - 1) << AUDIO_PEQ_14_B2_POS) -#define AUDIO_PEQ_14_B2_UMSK (~(((1U << AUDIO_PEQ_14_B2_LEN) - 1) << AUDIO_PEQ_14_B2_POS)) - -/* 0x324 : peq_14_a1 */ -#define AUDIO_PEQ_14_A1_OFFSET (0x324) -#define AUDIO_PEQ_14_A1 AUDIO_PEQ_14_A1 -#define AUDIO_PEQ_14_A1_POS (0U) -#define AUDIO_PEQ_14_A1_LEN (20U) -#define AUDIO_PEQ_14_A1_MSK (((1U << AUDIO_PEQ_14_A1_LEN) - 1) << AUDIO_PEQ_14_A1_POS) -#define AUDIO_PEQ_14_A1_UMSK (~(((1U << AUDIO_PEQ_14_A1_LEN) - 1) << AUDIO_PEQ_14_A1_POS)) - -/* 0x328 : peq_14_a2 */ -#define AUDIO_PEQ_14_A2_OFFSET (0x328) -#define AUDIO_PEQ_14_A2 AUDIO_PEQ_14_A2 -#define AUDIO_PEQ_14_A2_POS (0U) -#define AUDIO_PEQ_14_A2_LEN (20U) -#define AUDIO_PEQ_14_A2_MSK (((1U << AUDIO_PEQ_14_A2_LEN) - 1) << AUDIO_PEQ_14_A2_POS) -#define AUDIO_PEQ_14_A2_UMSK (~(((1U << AUDIO_PEQ_14_A2_LEN) - 1) << AUDIO_PEQ_14_A2_POS)) - -/* 0x32C : peq_15_b0 */ -#define AUDIO_PEQ_15_B0_OFFSET (0x32C) -#define AUDIO_PEQ_15_B0 AUDIO_PEQ_15_B0 -#define AUDIO_PEQ_15_B0_POS (0U) -#define AUDIO_PEQ_15_B0_LEN (20U) -#define AUDIO_PEQ_15_B0_MSK (((1U << AUDIO_PEQ_15_B0_LEN) - 1) << AUDIO_PEQ_15_B0_POS) -#define AUDIO_PEQ_15_B0_UMSK (~(((1U << AUDIO_PEQ_15_B0_LEN) - 1) << AUDIO_PEQ_15_B0_POS)) -#define AUDIO_PEQ_15_BYP AUDIO_PEQ_15_BYP -#define AUDIO_PEQ_15_BYP_POS (20U) -#define AUDIO_PEQ_15_BYP_LEN (1U) -#define AUDIO_PEQ_15_BYP_MSK (((1U << AUDIO_PEQ_15_BYP_LEN) - 1) << AUDIO_PEQ_15_BYP_POS) -#define AUDIO_PEQ_15_BYP_UMSK (~(((1U << AUDIO_PEQ_15_BYP_LEN) - 1) << AUDIO_PEQ_15_BYP_POS)) -#define AUDIO_PEQ_15_QFMT AUDIO_PEQ_15_QFMT -#define AUDIO_PEQ_15_QFMT_POS (21U) -#define AUDIO_PEQ_15_QFMT_LEN (1U) -#define AUDIO_PEQ_15_QFMT_MSK (((1U << AUDIO_PEQ_15_QFMT_LEN) - 1) << AUDIO_PEQ_15_QFMT_POS) -#define AUDIO_PEQ_15_QFMT_UMSK (~(((1U << AUDIO_PEQ_15_QFMT_LEN) - 1) << AUDIO_PEQ_15_QFMT_POS)) - -/* 0x330 : peq_15_b1 */ -#define AUDIO_PEQ_15_B1_OFFSET (0x330) -#define AUDIO_PEQ_15_B1 AUDIO_PEQ_15_B1 -#define AUDIO_PEQ_15_B1_POS (0U) -#define AUDIO_PEQ_15_B1_LEN (20U) -#define AUDIO_PEQ_15_B1_MSK (((1U << AUDIO_PEQ_15_B1_LEN) - 1) << AUDIO_PEQ_15_B1_POS) -#define AUDIO_PEQ_15_B1_UMSK (~(((1U << AUDIO_PEQ_15_B1_LEN) - 1) << AUDIO_PEQ_15_B1_POS)) - -/* 0x334 : peq_15_b2 */ -#define AUDIO_PEQ_15_B2_OFFSET (0x334) -#define AUDIO_PEQ_15_B2 AUDIO_PEQ_15_B2 -#define AUDIO_PEQ_15_B2_POS (0U) -#define AUDIO_PEQ_15_B2_LEN (20U) -#define AUDIO_PEQ_15_B2_MSK (((1U << AUDIO_PEQ_15_B2_LEN) - 1) << AUDIO_PEQ_15_B2_POS) -#define AUDIO_PEQ_15_B2_UMSK (~(((1U << AUDIO_PEQ_15_B2_LEN) - 1) << AUDIO_PEQ_15_B2_POS)) - -/* 0x338 : peq_15_a1 */ -#define AUDIO_PEQ_15_A1_OFFSET (0x338) -#define AUDIO_PEQ_15_A1 AUDIO_PEQ_15_A1 -#define AUDIO_PEQ_15_A1_POS (0U) -#define AUDIO_PEQ_15_A1_LEN (20U) -#define AUDIO_PEQ_15_A1_MSK (((1U << AUDIO_PEQ_15_A1_LEN) - 1) << AUDIO_PEQ_15_A1_POS) -#define AUDIO_PEQ_15_A1_UMSK (~(((1U << AUDIO_PEQ_15_A1_LEN) - 1) << AUDIO_PEQ_15_A1_POS)) - -/* 0x33C : peq_15_a2 */ -#define AUDIO_PEQ_15_A2_OFFSET (0x33C) -#define AUDIO_PEQ_15_A2 AUDIO_PEQ_15_A2 -#define AUDIO_PEQ_15_A2_POS (0U) -#define AUDIO_PEQ_15_A2_LEN (20U) -#define AUDIO_PEQ_15_A2_MSK (((1U << AUDIO_PEQ_15_A2_LEN) - 1) << AUDIO_PEQ_15_A2_POS) -#define AUDIO_PEQ_15_A2_UMSK (~(((1U << AUDIO_PEQ_15_A2_LEN) - 1) << AUDIO_PEQ_15_A2_POS)) - -/* 0x340 : peq_16_b0 */ -#define AUDIO_PEQ_16_B0_OFFSET (0x340) -#define AUDIO_PEQ_16_B0 AUDIO_PEQ_16_B0 -#define AUDIO_PEQ_16_B0_POS (0U) -#define AUDIO_PEQ_16_B0_LEN (20U) -#define AUDIO_PEQ_16_B0_MSK (((1U << AUDIO_PEQ_16_B0_LEN) - 1) << AUDIO_PEQ_16_B0_POS) -#define AUDIO_PEQ_16_B0_UMSK (~(((1U << AUDIO_PEQ_16_B0_LEN) - 1) << AUDIO_PEQ_16_B0_POS)) -#define AUDIO_PEQ_16_BYP AUDIO_PEQ_16_BYP -#define AUDIO_PEQ_16_BYP_POS (20U) -#define AUDIO_PEQ_16_BYP_LEN (1U) -#define AUDIO_PEQ_16_BYP_MSK (((1U << AUDIO_PEQ_16_BYP_LEN) - 1) << AUDIO_PEQ_16_BYP_POS) -#define AUDIO_PEQ_16_BYP_UMSK (~(((1U << AUDIO_PEQ_16_BYP_LEN) - 1) << AUDIO_PEQ_16_BYP_POS)) -#define AUDIO_PEQ_16_QFMT AUDIO_PEQ_16_QFMT -#define AUDIO_PEQ_16_QFMT_POS (21U) -#define AUDIO_PEQ_16_QFMT_LEN (1U) -#define AUDIO_PEQ_16_QFMT_MSK (((1U << AUDIO_PEQ_16_QFMT_LEN) - 1) << AUDIO_PEQ_16_QFMT_POS) -#define AUDIO_PEQ_16_QFMT_UMSK (~(((1U << AUDIO_PEQ_16_QFMT_LEN) - 1) << AUDIO_PEQ_16_QFMT_POS)) - -/* 0x344 : peq_16_b1 */ -#define AUDIO_PEQ_16_B1_OFFSET (0x344) -#define AUDIO_PEQ_16_B1 AUDIO_PEQ_16_B1 -#define AUDIO_PEQ_16_B1_POS (0U) -#define AUDIO_PEQ_16_B1_LEN (20U) -#define AUDIO_PEQ_16_B1_MSK (((1U << AUDIO_PEQ_16_B1_LEN) - 1) << AUDIO_PEQ_16_B1_POS) -#define AUDIO_PEQ_16_B1_UMSK (~(((1U << AUDIO_PEQ_16_B1_LEN) - 1) << AUDIO_PEQ_16_B1_POS)) - -/* 0x348 : peq_16_b2 */ -#define AUDIO_PEQ_16_B2_OFFSET (0x348) -#define AUDIO_PEQ_16_B2 AUDIO_PEQ_16_B2 -#define AUDIO_PEQ_16_B2_POS (0U) -#define AUDIO_PEQ_16_B2_LEN (20U) -#define AUDIO_PEQ_16_B2_MSK (((1U << AUDIO_PEQ_16_B2_LEN) - 1) << AUDIO_PEQ_16_B2_POS) -#define AUDIO_PEQ_16_B2_UMSK (~(((1U << AUDIO_PEQ_16_B2_LEN) - 1) << AUDIO_PEQ_16_B2_POS)) - -/* 0x34C : peq_16_a1 */ -#define AUDIO_PEQ_16_A1_OFFSET (0x34C) -#define AUDIO_PEQ_16_A1 AUDIO_PEQ_16_A1 -#define AUDIO_PEQ_16_A1_POS (0U) -#define AUDIO_PEQ_16_A1_LEN (20U) -#define AUDIO_PEQ_16_A1_MSK (((1U << AUDIO_PEQ_16_A1_LEN) - 1) << AUDIO_PEQ_16_A1_POS) -#define AUDIO_PEQ_16_A1_UMSK (~(((1U << AUDIO_PEQ_16_A1_LEN) - 1) << AUDIO_PEQ_16_A1_POS)) - -/* 0x350 : peq_16_a2 */ -#define AUDIO_PEQ_16_A2_OFFSET (0x350) -#define AUDIO_PEQ_16_A2 AUDIO_PEQ_16_A2 -#define AUDIO_PEQ_16_A2_POS (0U) -#define AUDIO_PEQ_16_A2_LEN (20U) -#define AUDIO_PEQ_16_A2_MSK (((1U << AUDIO_PEQ_16_A2_LEN) - 1) << AUDIO_PEQ_16_A2_POS) -#define AUDIO_PEQ_16_A2_UMSK (~(((1U << AUDIO_PEQ_16_A2_LEN) - 1) << AUDIO_PEQ_16_A2_POS)) - -/* 0x354 : peq_17_b0 */ -#define AUDIO_PEQ_17_B0_OFFSET (0x354) -#define AUDIO_PEQ_17_B0 AUDIO_PEQ_17_B0 -#define AUDIO_PEQ_17_B0_POS (0U) -#define AUDIO_PEQ_17_B0_LEN (20U) -#define AUDIO_PEQ_17_B0_MSK (((1U << AUDIO_PEQ_17_B0_LEN) - 1) << AUDIO_PEQ_17_B0_POS) -#define AUDIO_PEQ_17_B0_UMSK (~(((1U << AUDIO_PEQ_17_B0_LEN) - 1) << AUDIO_PEQ_17_B0_POS)) -#define AUDIO_PEQ_17_BYP AUDIO_PEQ_17_BYP -#define AUDIO_PEQ_17_BYP_POS (20U) -#define AUDIO_PEQ_17_BYP_LEN (1U) -#define AUDIO_PEQ_17_BYP_MSK (((1U << AUDIO_PEQ_17_BYP_LEN) - 1) << AUDIO_PEQ_17_BYP_POS) -#define AUDIO_PEQ_17_BYP_UMSK (~(((1U << AUDIO_PEQ_17_BYP_LEN) - 1) << AUDIO_PEQ_17_BYP_POS)) -#define AUDIO_PEQ_17_QFMT AUDIO_PEQ_17_QFMT -#define AUDIO_PEQ_17_QFMT_POS (21U) -#define AUDIO_PEQ_17_QFMT_LEN (1U) -#define AUDIO_PEQ_17_QFMT_MSK (((1U << AUDIO_PEQ_17_QFMT_LEN) - 1) << AUDIO_PEQ_17_QFMT_POS) -#define AUDIO_PEQ_17_QFMT_UMSK (~(((1U << AUDIO_PEQ_17_QFMT_LEN) - 1) << AUDIO_PEQ_17_QFMT_POS)) - -/* 0x358 : peq_17_b1 */ -#define AUDIO_PEQ_17_B1_OFFSET (0x358) -#define AUDIO_PEQ_17_B1 AUDIO_PEQ_17_B1 -#define AUDIO_PEQ_17_B1_POS (0U) -#define AUDIO_PEQ_17_B1_LEN (20U) -#define AUDIO_PEQ_17_B1_MSK (((1U << AUDIO_PEQ_17_B1_LEN) - 1) << AUDIO_PEQ_17_B1_POS) -#define AUDIO_PEQ_17_B1_UMSK (~(((1U << AUDIO_PEQ_17_B1_LEN) - 1) << AUDIO_PEQ_17_B1_POS)) - -/* 0x35C : peq_17_b2 */ -#define AUDIO_PEQ_17_B2_OFFSET (0x35C) -#define AUDIO_PEQ_17_B2 AUDIO_PEQ_17_B2 -#define AUDIO_PEQ_17_B2_POS (0U) -#define AUDIO_PEQ_17_B2_LEN (20U) -#define AUDIO_PEQ_17_B2_MSK (((1U << AUDIO_PEQ_17_B2_LEN) - 1) << AUDIO_PEQ_17_B2_POS) -#define AUDIO_PEQ_17_B2_UMSK (~(((1U << AUDIO_PEQ_17_B2_LEN) - 1) << AUDIO_PEQ_17_B2_POS)) - -/* 0x360 : peq_17_a1 */ -#define AUDIO_PEQ_17_A1_OFFSET (0x360) -#define AUDIO_PEQ_17_A1 AUDIO_PEQ_17_A1 -#define AUDIO_PEQ_17_A1_POS (0U) -#define AUDIO_PEQ_17_A1_LEN (20U) -#define AUDIO_PEQ_17_A1_MSK (((1U << AUDIO_PEQ_17_A1_LEN) - 1) << AUDIO_PEQ_17_A1_POS) -#define AUDIO_PEQ_17_A1_UMSK (~(((1U << AUDIO_PEQ_17_A1_LEN) - 1) << AUDIO_PEQ_17_A1_POS)) - -/* 0x364 : peq_17_a2 */ -#define AUDIO_PEQ_17_A2_OFFSET (0x364) -#define AUDIO_PEQ_17_A2 AUDIO_PEQ_17_A2 -#define AUDIO_PEQ_17_A2_POS (0U) -#define AUDIO_PEQ_17_A2_LEN (20U) -#define AUDIO_PEQ_17_A2_MSK (((1U << AUDIO_PEQ_17_A2_LEN) - 1) << AUDIO_PEQ_17_A2_POS) -#define AUDIO_PEQ_17_A2_UMSK (~(((1U << AUDIO_PEQ_17_A2_LEN) - 1) << AUDIO_PEQ_17_A2_POS)) - -/* 0x368 : peq_18_b0 */ -#define AUDIO_PEQ_18_B0_OFFSET (0x368) -#define AUDIO_PEQ_18_B0 AUDIO_PEQ_18_B0 -#define AUDIO_PEQ_18_B0_POS (0U) -#define AUDIO_PEQ_18_B0_LEN (20U) -#define AUDIO_PEQ_18_B0_MSK (((1U << AUDIO_PEQ_18_B0_LEN) - 1) << AUDIO_PEQ_18_B0_POS) -#define AUDIO_PEQ_18_B0_UMSK (~(((1U << AUDIO_PEQ_18_B0_LEN) - 1) << AUDIO_PEQ_18_B0_POS)) -#define AUDIO_PEQ_18_BYP AUDIO_PEQ_18_BYP -#define AUDIO_PEQ_18_BYP_POS (20U) -#define AUDIO_PEQ_18_BYP_LEN (1U) -#define AUDIO_PEQ_18_BYP_MSK (((1U << AUDIO_PEQ_18_BYP_LEN) - 1) << AUDIO_PEQ_18_BYP_POS) -#define AUDIO_PEQ_18_BYP_UMSK (~(((1U << AUDIO_PEQ_18_BYP_LEN) - 1) << AUDIO_PEQ_18_BYP_POS)) -#define AUDIO_PEQ_18_QFMT AUDIO_PEQ_18_QFMT -#define AUDIO_PEQ_18_QFMT_POS (21U) -#define AUDIO_PEQ_18_QFMT_LEN (1U) -#define AUDIO_PEQ_18_QFMT_MSK (((1U << AUDIO_PEQ_18_QFMT_LEN) - 1) << AUDIO_PEQ_18_QFMT_POS) -#define AUDIO_PEQ_18_QFMT_UMSK (~(((1U << AUDIO_PEQ_18_QFMT_LEN) - 1) << AUDIO_PEQ_18_QFMT_POS)) - -/* 0x36C : peq_18_b1 */ -#define AUDIO_PEQ_18_B1_OFFSET (0x36C) -#define AUDIO_PEQ_18_B1 AUDIO_PEQ_18_B1 -#define AUDIO_PEQ_18_B1_POS (0U) -#define AUDIO_PEQ_18_B1_LEN (20U) -#define AUDIO_PEQ_18_B1_MSK (((1U << AUDIO_PEQ_18_B1_LEN) - 1) << AUDIO_PEQ_18_B1_POS) -#define AUDIO_PEQ_18_B1_UMSK (~(((1U << AUDIO_PEQ_18_B1_LEN) - 1) << AUDIO_PEQ_18_B1_POS)) - -/* 0x370 : peq_18_b2 */ -#define AUDIO_PEQ_18_B2_OFFSET (0x370) -#define AUDIO_PEQ_18_B2 AUDIO_PEQ_18_B2 -#define AUDIO_PEQ_18_B2_POS (0U) -#define AUDIO_PEQ_18_B2_LEN (20U) -#define AUDIO_PEQ_18_B2_MSK (((1U << AUDIO_PEQ_18_B2_LEN) - 1) << AUDIO_PEQ_18_B2_POS) -#define AUDIO_PEQ_18_B2_UMSK (~(((1U << AUDIO_PEQ_18_B2_LEN) - 1) << AUDIO_PEQ_18_B2_POS)) - -/* 0x374 : peq_18_a1 */ -#define AUDIO_PEQ_18_A1_OFFSET (0x374) -#define AUDIO_PEQ_18_A1 AUDIO_PEQ_18_A1 -#define AUDIO_PEQ_18_A1_POS (0U) -#define AUDIO_PEQ_18_A1_LEN (20U) -#define AUDIO_PEQ_18_A1_MSK (((1U << AUDIO_PEQ_18_A1_LEN) - 1) << AUDIO_PEQ_18_A1_POS) -#define AUDIO_PEQ_18_A1_UMSK (~(((1U << AUDIO_PEQ_18_A1_LEN) - 1) << AUDIO_PEQ_18_A1_POS)) - -/* 0x378 : peq_18_a2 */ -#define AUDIO_PEQ_18_A2_OFFSET (0x378) -#define AUDIO_PEQ_18_A2 AUDIO_PEQ_18_A2 -#define AUDIO_PEQ_18_A2_POS (0U) -#define AUDIO_PEQ_18_A2_LEN (20U) -#define AUDIO_PEQ_18_A2_MSK (((1U << AUDIO_PEQ_18_A2_LEN) - 1) << AUDIO_PEQ_18_A2_POS) -#define AUDIO_PEQ_18_A2_UMSK (~(((1U << AUDIO_PEQ_18_A2_LEN) - 1) << AUDIO_PEQ_18_A2_POS)) - -/* 0x37C : peq_19_b0 */ -#define AUDIO_PEQ_19_B0_OFFSET (0x37C) -#define AUDIO_PEQ_19_B0 AUDIO_PEQ_19_B0 -#define AUDIO_PEQ_19_B0_POS (0U) -#define AUDIO_PEQ_19_B0_LEN (20U) -#define AUDIO_PEQ_19_B0_MSK (((1U << AUDIO_PEQ_19_B0_LEN) - 1) << AUDIO_PEQ_19_B0_POS) -#define AUDIO_PEQ_19_B0_UMSK (~(((1U << AUDIO_PEQ_19_B0_LEN) - 1) << AUDIO_PEQ_19_B0_POS)) -#define AUDIO_PEQ_19_BYP AUDIO_PEQ_19_BYP -#define AUDIO_PEQ_19_BYP_POS (20U) -#define AUDIO_PEQ_19_BYP_LEN (1U) -#define AUDIO_PEQ_19_BYP_MSK (((1U << AUDIO_PEQ_19_BYP_LEN) - 1) << AUDIO_PEQ_19_BYP_POS) -#define AUDIO_PEQ_19_BYP_UMSK (~(((1U << AUDIO_PEQ_19_BYP_LEN) - 1) << AUDIO_PEQ_19_BYP_POS)) -#define AUDIO_PEQ_19_QFMT AUDIO_PEQ_19_QFMT -#define AUDIO_PEQ_19_QFMT_POS (21U) -#define AUDIO_PEQ_19_QFMT_LEN (1U) -#define AUDIO_PEQ_19_QFMT_MSK (((1U << AUDIO_PEQ_19_QFMT_LEN) - 1) << AUDIO_PEQ_19_QFMT_POS) -#define AUDIO_PEQ_19_QFMT_UMSK (~(((1U << AUDIO_PEQ_19_QFMT_LEN) - 1) << AUDIO_PEQ_19_QFMT_POS)) - -/* 0x380 : peq_19_b1 */ -#define AUDIO_PEQ_19_B1_OFFSET (0x380) -#define AUDIO_PEQ_19_B1 AUDIO_PEQ_19_B1 -#define AUDIO_PEQ_19_B1_POS (0U) -#define AUDIO_PEQ_19_B1_LEN (20U) -#define AUDIO_PEQ_19_B1_MSK (((1U << AUDIO_PEQ_19_B1_LEN) - 1) << AUDIO_PEQ_19_B1_POS) -#define AUDIO_PEQ_19_B1_UMSK (~(((1U << AUDIO_PEQ_19_B1_LEN) - 1) << AUDIO_PEQ_19_B1_POS)) - -/* 0x384 : peq_19_b2 */ -#define AUDIO_PEQ_19_B2_OFFSET (0x384) -#define AUDIO_PEQ_19_B2 AUDIO_PEQ_19_B2 -#define AUDIO_PEQ_19_B2_POS (0U) -#define AUDIO_PEQ_19_B2_LEN (20U) -#define AUDIO_PEQ_19_B2_MSK (((1U << AUDIO_PEQ_19_B2_LEN) - 1) << AUDIO_PEQ_19_B2_POS) -#define AUDIO_PEQ_19_B2_UMSK (~(((1U << AUDIO_PEQ_19_B2_LEN) - 1) << AUDIO_PEQ_19_B2_POS)) - -/* 0x388 : peq_19_a1 */ -#define AUDIO_PEQ_19_A1_OFFSET (0x388) -#define AUDIO_PEQ_19_A1 AUDIO_PEQ_19_A1 -#define AUDIO_PEQ_19_A1_POS (0U) -#define AUDIO_PEQ_19_A1_LEN (20U) -#define AUDIO_PEQ_19_A1_MSK (((1U << AUDIO_PEQ_19_A1_LEN) - 1) << AUDIO_PEQ_19_A1_POS) -#define AUDIO_PEQ_19_A1_UMSK (~(((1U << AUDIO_PEQ_19_A1_LEN) - 1) << AUDIO_PEQ_19_A1_POS)) - -/* 0x38C : peq_19_a2 */ -#define AUDIO_PEQ_19_A2_OFFSET (0x38C) -#define AUDIO_PEQ_19_A2 AUDIO_PEQ_19_A2 -#define AUDIO_PEQ_19_A2_POS (0U) -#define AUDIO_PEQ_19_A2_LEN (20U) -#define AUDIO_PEQ_19_A2_MSK (((1U << AUDIO_PEQ_19_A2_LEN) - 1) << AUDIO_PEQ_19_A2_POS) -#define AUDIO_PEQ_19_A2_UMSK (~(((1U << AUDIO_PEQ_19_A2_LEN) - 1) << AUDIO_PEQ_19_A2_POS)) - -/* 0x390 : peq_20_b0 */ -#define AUDIO_PEQ_20_B0_OFFSET (0x390) -#define AUDIO_PEQ_20_B0 AUDIO_PEQ_20_B0 -#define AUDIO_PEQ_20_B0_POS (0U) -#define AUDIO_PEQ_20_B0_LEN (20U) -#define AUDIO_PEQ_20_B0_MSK (((1U << AUDIO_PEQ_20_B0_LEN) - 1) << AUDIO_PEQ_20_B0_POS) -#define AUDIO_PEQ_20_B0_UMSK (~(((1U << AUDIO_PEQ_20_B0_LEN) - 1) << AUDIO_PEQ_20_B0_POS)) -#define AUDIO_PEQ_20_BYP AUDIO_PEQ_20_BYP -#define AUDIO_PEQ_20_BYP_POS (20U) -#define AUDIO_PEQ_20_BYP_LEN (1U) -#define AUDIO_PEQ_20_BYP_MSK (((1U << AUDIO_PEQ_20_BYP_LEN) - 1) << AUDIO_PEQ_20_BYP_POS) -#define AUDIO_PEQ_20_BYP_UMSK (~(((1U << AUDIO_PEQ_20_BYP_LEN) - 1) << AUDIO_PEQ_20_BYP_POS)) -#define AUDIO_PEQ_20_QFMT AUDIO_PEQ_20_QFMT -#define AUDIO_PEQ_20_QFMT_POS (21U) -#define AUDIO_PEQ_20_QFMT_LEN (1U) -#define AUDIO_PEQ_20_QFMT_MSK (((1U << AUDIO_PEQ_20_QFMT_LEN) - 1) << AUDIO_PEQ_20_QFMT_POS) -#define AUDIO_PEQ_20_QFMT_UMSK (~(((1U << AUDIO_PEQ_20_QFMT_LEN) - 1) << AUDIO_PEQ_20_QFMT_POS)) -#define AUDIO_ADC_PEQ_IN_SEL AUDIO_ADC_PEQ_IN_SEL -#define AUDIO_ADC_PEQ_IN_SEL_POS (30U) -#define AUDIO_ADC_PEQ_IN_SEL_LEN (2U) -#define AUDIO_ADC_PEQ_IN_SEL_MSK (((1U << AUDIO_ADC_PEQ_IN_SEL_LEN) - 1) << AUDIO_ADC_PEQ_IN_SEL_POS) -#define AUDIO_ADC_PEQ_IN_SEL_UMSK (~(((1U << AUDIO_ADC_PEQ_IN_SEL_LEN) - 1) << AUDIO_ADC_PEQ_IN_SEL_POS)) - -/* 0x394 : peq_20_b1 */ -#define AUDIO_PEQ_20_B1_OFFSET (0x394) -#define AUDIO_PEQ_20_B1 AUDIO_PEQ_20_B1 -#define AUDIO_PEQ_20_B1_POS (0U) -#define AUDIO_PEQ_20_B1_LEN (20U) -#define AUDIO_PEQ_20_B1_MSK (((1U << AUDIO_PEQ_20_B1_LEN) - 1) << AUDIO_PEQ_20_B1_POS) -#define AUDIO_PEQ_20_B1_UMSK (~(((1U << AUDIO_PEQ_20_B1_LEN) - 1) << AUDIO_PEQ_20_B1_POS)) - -/* 0x398 : peq_20_b2 */ -#define AUDIO_PEQ_20_B2_OFFSET (0x398) -#define AUDIO_PEQ_20_B2 AUDIO_PEQ_20_B2 -#define AUDIO_PEQ_20_B2_POS (0U) -#define AUDIO_PEQ_20_B2_LEN (20U) -#define AUDIO_PEQ_20_B2_MSK (((1U << AUDIO_PEQ_20_B2_LEN) - 1) << AUDIO_PEQ_20_B2_POS) -#define AUDIO_PEQ_20_B2_UMSK (~(((1U << AUDIO_PEQ_20_B2_LEN) - 1) << AUDIO_PEQ_20_B2_POS)) - -/* 0x39C : peq_20_a1 */ -#define AUDIO_PEQ_20_A1_OFFSET (0x39C) -#define AUDIO_PEQ_20_A1 AUDIO_PEQ_20_A1 -#define AUDIO_PEQ_20_A1_POS (0U) -#define AUDIO_PEQ_20_A1_LEN (20U) -#define AUDIO_PEQ_20_A1_MSK (((1U << AUDIO_PEQ_20_A1_LEN) - 1) << AUDIO_PEQ_20_A1_POS) -#define AUDIO_PEQ_20_A1_UMSK (~(((1U << AUDIO_PEQ_20_A1_LEN) - 1) << AUDIO_PEQ_20_A1_POS)) - -/* 0x3A0 : peq_20_a2 */ -#define AUDIO_PEQ_20_A2_OFFSET (0x3A0) -#define AUDIO_PEQ_20_A2 AUDIO_PEQ_20_A2 -#define AUDIO_PEQ_20_A2_POS (0U) -#define AUDIO_PEQ_20_A2_LEN (20U) -#define AUDIO_PEQ_20_A2_MSK (((1U << AUDIO_PEQ_20_A2_LEN) - 1) << AUDIO_PEQ_20_A2_POS) -#define AUDIO_PEQ_20_A2_UMSK (~(((1U << AUDIO_PEQ_20_A2_LEN) - 1) << AUDIO_PEQ_20_A2_POS)) - -/* 0x3A4 : peq_21_b0 */ -#define AUDIO_PEQ_21_B0_OFFSET (0x3A4) -#define AUDIO_PEQ_21_B0 AUDIO_PEQ_21_B0 -#define AUDIO_PEQ_21_B0_POS (0U) -#define AUDIO_PEQ_21_B0_LEN (20U) -#define AUDIO_PEQ_21_B0_MSK (((1U << AUDIO_PEQ_21_B0_LEN) - 1) << AUDIO_PEQ_21_B0_POS) -#define AUDIO_PEQ_21_B0_UMSK (~(((1U << AUDIO_PEQ_21_B0_LEN) - 1) << AUDIO_PEQ_21_B0_POS)) -#define AUDIO_PEQ_21_BYP AUDIO_PEQ_21_BYP -#define AUDIO_PEQ_21_BYP_POS (20U) -#define AUDIO_PEQ_21_BYP_LEN (1U) -#define AUDIO_PEQ_21_BYP_MSK (((1U << AUDIO_PEQ_21_BYP_LEN) - 1) << AUDIO_PEQ_21_BYP_POS) -#define AUDIO_PEQ_21_BYP_UMSK (~(((1U << AUDIO_PEQ_21_BYP_LEN) - 1) << AUDIO_PEQ_21_BYP_POS)) -#define AUDIO_PEQ_21_QFMT AUDIO_PEQ_21_QFMT -#define AUDIO_PEQ_21_QFMT_POS (21U) -#define AUDIO_PEQ_21_QFMT_LEN (1U) -#define AUDIO_PEQ_21_QFMT_MSK (((1U << AUDIO_PEQ_21_QFMT_LEN) - 1) << AUDIO_PEQ_21_QFMT_POS) -#define AUDIO_PEQ_21_QFMT_UMSK (~(((1U << AUDIO_PEQ_21_QFMT_LEN) - 1) << AUDIO_PEQ_21_QFMT_POS)) - -/* 0x3A8 : peq_21_b1 */ -#define AUDIO_PEQ_21_B1_OFFSET (0x3A8) -#define AUDIO_PEQ_21_B1 AUDIO_PEQ_21_B1 -#define AUDIO_PEQ_21_B1_POS (0U) -#define AUDIO_PEQ_21_B1_LEN (20U) -#define AUDIO_PEQ_21_B1_MSK (((1U << AUDIO_PEQ_21_B1_LEN) - 1) << AUDIO_PEQ_21_B1_POS) -#define AUDIO_PEQ_21_B1_UMSK (~(((1U << AUDIO_PEQ_21_B1_LEN) - 1) << AUDIO_PEQ_21_B1_POS)) - -/* 0x3AC : peq_21_b2 */ -#define AUDIO_PEQ_21_B2_OFFSET (0x3AC) -#define AUDIO_PEQ_21_B2 AUDIO_PEQ_21_B2 -#define AUDIO_PEQ_21_B2_POS (0U) -#define AUDIO_PEQ_21_B2_LEN (20U) -#define AUDIO_PEQ_21_B2_MSK (((1U << AUDIO_PEQ_21_B2_LEN) - 1) << AUDIO_PEQ_21_B2_POS) -#define AUDIO_PEQ_21_B2_UMSK (~(((1U << AUDIO_PEQ_21_B2_LEN) - 1) << AUDIO_PEQ_21_B2_POS)) - -/* 0x3B0 : peq_21_a1 */ -#define AUDIO_PEQ_21_A1_OFFSET (0x3B0) -#define AUDIO_PEQ_21_A1 AUDIO_PEQ_21_A1 -#define AUDIO_PEQ_21_A1_POS (0U) -#define AUDIO_PEQ_21_A1_LEN (20U) -#define AUDIO_PEQ_21_A1_MSK (((1U << AUDIO_PEQ_21_A1_LEN) - 1) << AUDIO_PEQ_21_A1_POS) -#define AUDIO_PEQ_21_A1_UMSK (~(((1U << AUDIO_PEQ_21_A1_LEN) - 1) << AUDIO_PEQ_21_A1_POS)) - -/* 0x3B4 : peq_21_a2 */ -#define AUDIO_PEQ_21_A2_OFFSET (0x3B4) -#define AUDIO_PEQ_21_A2 AUDIO_PEQ_21_A2 -#define AUDIO_PEQ_21_A2_POS (0U) -#define AUDIO_PEQ_21_A2_LEN (20U) -#define AUDIO_PEQ_21_A2_MSK (((1U << AUDIO_PEQ_21_A2_LEN) - 1) << AUDIO_PEQ_21_A2_POS) -#define AUDIO_PEQ_21_A2_UMSK (~(((1U << AUDIO_PEQ_21_A2_LEN) - 1) << AUDIO_PEQ_21_A2_POS)) - -/* 0x3B8 : peq_22_b0 */ -#define AUDIO_PEQ_22_B0_OFFSET (0x3B8) -#define AUDIO_PEQ_22_B0 AUDIO_PEQ_22_B0 -#define AUDIO_PEQ_22_B0_POS (0U) -#define AUDIO_PEQ_22_B0_LEN (20U) -#define AUDIO_PEQ_22_B0_MSK (((1U << AUDIO_PEQ_22_B0_LEN) - 1) << AUDIO_PEQ_22_B0_POS) -#define AUDIO_PEQ_22_B0_UMSK (~(((1U << AUDIO_PEQ_22_B0_LEN) - 1) << AUDIO_PEQ_22_B0_POS)) -#define AUDIO_PEQ_22_BYP AUDIO_PEQ_22_BYP -#define AUDIO_PEQ_22_BYP_POS (20U) -#define AUDIO_PEQ_22_BYP_LEN (1U) -#define AUDIO_PEQ_22_BYP_MSK (((1U << AUDIO_PEQ_22_BYP_LEN) - 1) << AUDIO_PEQ_22_BYP_POS) -#define AUDIO_PEQ_22_BYP_UMSK (~(((1U << AUDIO_PEQ_22_BYP_LEN) - 1) << AUDIO_PEQ_22_BYP_POS)) -#define AUDIO_PEQ_22_QFMT AUDIO_PEQ_22_QFMT -#define AUDIO_PEQ_22_QFMT_POS (21U) -#define AUDIO_PEQ_22_QFMT_LEN (1U) -#define AUDIO_PEQ_22_QFMT_MSK (((1U << AUDIO_PEQ_22_QFMT_LEN) - 1) << AUDIO_PEQ_22_QFMT_POS) -#define AUDIO_PEQ_22_QFMT_UMSK (~(((1U << AUDIO_PEQ_22_QFMT_LEN) - 1) << AUDIO_PEQ_22_QFMT_POS)) - -/* 0x3BC : peq_22_b1 */ -#define AUDIO_PEQ_22_B1_OFFSET (0x3BC) -#define AUDIO_PEQ_22_B1 AUDIO_PEQ_22_B1 -#define AUDIO_PEQ_22_B1_POS (0U) -#define AUDIO_PEQ_22_B1_LEN (20U) -#define AUDIO_PEQ_22_B1_MSK (((1U << AUDIO_PEQ_22_B1_LEN) - 1) << AUDIO_PEQ_22_B1_POS) -#define AUDIO_PEQ_22_B1_UMSK (~(((1U << AUDIO_PEQ_22_B1_LEN) - 1) << AUDIO_PEQ_22_B1_POS)) - -/* 0x3C0 : peq_22_b2 */ -#define AUDIO_PEQ_22_B2_OFFSET (0x3C0) -#define AUDIO_PEQ_22_B2 AUDIO_PEQ_22_B2 -#define AUDIO_PEQ_22_B2_POS (0U) -#define AUDIO_PEQ_22_B2_LEN (20U) -#define AUDIO_PEQ_22_B2_MSK (((1U << AUDIO_PEQ_22_B2_LEN) - 1) << AUDIO_PEQ_22_B2_POS) -#define AUDIO_PEQ_22_B2_UMSK (~(((1U << AUDIO_PEQ_22_B2_LEN) - 1) << AUDIO_PEQ_22_B2_POS)) - -/* 0x3C4 : peq_22_a1 */ -#define AUDIO_PEQ_22_A1_OFFSET (0x3C4) -#define AUDIO_PEQ_22_A1 AUDIO_PEQ_22_A1 -#define AUDIO_PEQ_22_A1_POS (0U) -#define AUDIO_PEQ_22_A1_LEN (20U) -#define AUDIO_PEQ_22_A1_MSK (((1U << AUDIO_PEQ_22_A1_LEN) - 1) << AUDIO_PEQ_22_A1_POS) -#define AUDIO_PEQ_22_A1_UMSK (~(((1U << AUDIO_PEQ_22_A1_LEN) - 1) << AUDIO_PEQ_22_A1_POS)) - -/* 0x3C8 : peq_22_a2 */ -#define AUDIO_PEQ_22_A2_OFFSET (0x3C8) -#define AUDIO_PEQ_22_A2 AUDIO_PEQ_22_A2 -#define AUDIO_PEQ_22_A2_POS (0U) -#define AUDIO_PEQ_22_A2_LEN (20U) -#define AUDIO_PEQ_22_A2_MSK (((1U << AUDIO_PEQ_22_A2_LEN) - 1) << AUDIO_PEQ_22_A2_POS) -#define AUDIO_PEQ_22_A2_UMSK (~(((1U << AUDIO_PEQ_22_A2_LEN) - 1) << AUDIO_PEQ_22_A2_POS)) - -/* 0x3CC : peq_23_b0 */ -#define AUDIO_PEQ_23_B0_OFFSET (0x3CC) -#define AUDIO_PEQ_23_B0 AUDIO_PEQ_23_B0 -#define AUDIO_PEQ_23_B0_POS (0U) -#define AUDIO_PEQ_23_B0_LEN (20U) -#define AUDIO_PEQ_23_B0_MSK (((1U << AUDIO_PEQ_23_B0_LEN) - 1) << AUDIO_PEQ_23_B0_POS) -#define AUDIO_PEQ_23_B0_UMSK (~(((1U << AUDIO_PEQ_23_B0_LEN) - 1) << AUDIO_PEQ_23_B0_POS)) -#define AUDIO_PEQ_23_BYP AUDIO_PEQ_23_BYP -#define AUDIO_PEQ_23_BYP_POS (20U) -#define AUDIO_PEQ_23_BYP_LEN (1U) -#define AUDIO_PEQ_23_BYP_MSK (((1U << AUDIO_PEQ_23_BYP_LEN) - 1) << AUDIO_PEQ_23_BYP_POS) -#define AUDIO_PEQ_23_BYP_UMSK (~(((1U << AUDIO_PEQ_23_BYP_LEN) - 1) << AUDIO_PEQ_23_BYP_POS)) -#define AUDIO_PEQ_23_QFMT AUDIO_PEQ_23_QFMT -#define AUDIO_PEQ_23_QFMT_POS (21U) -#define AUDIO_PEQ_23_QFMT_LEN (1U) -#define AUDIO_PEQ_23_QFMT_MSK (((1U << AUDIO_PEQ_23_QFMT_LEN) - 1) << AUDIO_PEQ_23_QFMT_POS) -#define AUDIO_PEQ_23_QFMT_UMSK (~(((1U << AUDIO_PEQ_23_QFMT_LEN) - 1) << AUDIO_PEQ_23_QFMT_POS)) - -/* 0x3D0 : peq_23_b1 */ -#define AUDIO_PEQ_23_B1_OFFSET (0x3D0) -#define AUDIO_PEQ_23_B1 AUDIO_PEQ_23_B1 -#define AUDIO_PEQ_23_B1_POS (0U) -#define AUDIO_PEQ_23_B1_LEN (20U) -#define AUDIO_PEQ_23_B1_MSK (((1U << AUDIO_PEQ_23_B1_LEN) - 1) << AUDIO_PEQ_23_B1_POS) -#define AUDIO_PEQ_23_B1_UMSK (~(((1U << AUDIO_PEQ_23_B1_LEN) - 1) << AUDIO_PEQ_23_B1_POS)) - -/* 0x3D4 : peq_23_b2 */ -#define AUDIO_PEQ_23_B2_OFFSET (0x3D4) -#define AUDIO_PEQ_23_B2 AUDIO_PEQ_23_B2 -#define AUDIO_PEQ_23_B2_POS (0U) -#define AUDIO_PEQ_23_B2_LEN (20U) -#define AUDIO_PEQ_23_B2_MSK (((1U << AUDIO_PEQ_23_B2_LEN) - 1) << AUDIO_PEQ_23_B2_POS) -#define AUDIO_PEQ_23_B2_UMSK (~(((1U << AUDIO_PEQ_23_B2_LEN) - 1) << AUDIO_PEQ_23_B2_POS)) - -/* 0x3D8 : peq_23_a1 */ -#define AUDIO_PEQ_23_A1_OFFSET (0x3D8) -#define AUDIO_PEQ_23_A1 AUDIO_PEQ_23_A1 -#define AUDIO_PEQ_23_A1_POS (0U) -#define AUDIO_PEQ_23_A1_LEN (20U) -#define AUDIO_PEQ_23_A1_MSK (((1U << AUDIO_PEQ_23_A1_LEN) - 1) << AUDIO_PEQ_23_A1_POS) -#define AUDIO_PEQ_23_A1_UMSK (~(((1U << AUDIO_PEQ_23_A1_LEN) - 1) << AUDIO_PEQ_23_A1_POS)) - -/* 0x3DC : peq_23_a2 */ -#define AUDIO_PEQ_23_A2_OFFSET (0x3DC) -#define AUDIO_PEQ_23_A2 AUDIO_PEQ_23_A2 -#define AUDIO_PEQ_23_A2_POS (0U) -#define AUDIO_PEQ_23_A2_LEN (20U) -#define AUDIO_PEQ_23_A2_MSK (((1U << AUDIO_PEQ_23_A2_LEN) - 1) << AUDIO_PEQ_23_A2_POS) -#define AUDIO_PEQ_23_A2_UMSK (~(((1U << AUDIO_PEQ_23_A2_LEN) - 1) << AUDIO_PEQ_23_A2_POS)) - -/* 0x3E0 : peq_24_b0 */ -#define AUDIO_PEQ_24_B0_OFFSET (0x3E0) -#define AUDIO_PEQ_24_B0 AUDIO_PEQ_24_B0 -#define AUDIO_PEQ_24_B0_POS (0U) -#define AUDIO_PEQ_24_B0_LEN (20U) -#define AUDIO_PEQ_24_B0_MSK (((1U << AUDIO_PEQ_24_B0_LEN) - 1) << AUDIO_PEQ_24_B0_POS) -#define AUDIO_PEQ_24_B0_UMSK (~(((1U << AUDIO_PEQ_24_B0_LEN) - 1) << AUDIO_PEQ_24_B0_POS)) -#define AUDIO_PEQ_24_BYP AUDIO_PEQ_24_BYP -#define AUDIO_PEQ_24_BYP_POS (20U) -#define AUDIO_PEQ_24_BYP_LEN (1U) -#define AUDIO_PEQ_24_BYP_MSK (((1U << AUDIO_PEQ_24_BYP_LEN) - 1) << AUDIO_PEQ_24_BYP_POS) -#define AUDIO_PEQ_24_BYP_UMSK (~(((1U << AUDIO_PEQ_24_BYP_LEN) - 1) << AUDIO_PEQ_24_BYP_POS)) -#define AUDIO_PEQ_24_QFMT AUDIO_PEQ_24_QFMT -#define AUDIO_PEQ_24_QFMT_POS (21U) -#define AUDIO_PEQ_24_QFMT_LEN (1U) -#define AUDIO_PEQ_24_QFMT_MSK (((1U << AUDIO_PEQ_24_QFMT_LEN) - 1) << AUDIO_PEQ_24_QFMT_POS) -#define AUDIO_PEQ_24_QFMT_UMSK (~(((1U << AUDIO_PEQ_24_QFMT_LEN) - 1) << AUDIO_PEQ_24_QFMT_POS)) - -/* 0x3E4 : peq_24_b1 */ -#define AUDIO_PEQ_24_B1_OFFSET (0x3E4) -#define AUDIO_PEQ_24_B1 AUDIO_PEQ_24_B1 -#define AUDIO_PEQ_24_B1_POS (0U) -#define AUDIO_PEQ_24_B1_LEN (20U) -#define AUDIO_PEQ_24_B1_MSK (((1U << AUDIO_PEQ_24_B1_LEN) - 1) << AUDIO_PEQ_24_B1_POS) -#define AUDIO_PEQ_24_B1_UMSK (~(((1U << AUDIO_PEQ_24_B1_LEN) - 1) << AUDIO_PEQ_24_B1_POS)) - -/* 0x3E8 : peq_24_b2 */ -#define AUDIO_PEQ_24_B2_OFFSET (0x3E8) -#define AUDIO_PEQ_24_B2 AUDIO_PEQ_24_B2 -#define AUDIO_PEQ_24_B2_POS (0U) -#define AUDIO_PEQ_24_B2_LEN (20U) -#define AUDIO_PEQ_24_B2_MSK (((1U << AUDIO_PEQ_24_B2_LEN) - 1) << AUDIO_PEQ_24_B2_POS) -#define AUDIO_PEQ_24_B2_UMSK (~(((1U << AUDIO_PEQ_24_B2_LEN) - 1) << AUDIO_PEQ_24_B2_POS)) - -/* 0x3EC : peq_24_a1 */ -#define AUDIO_PEQ_24_A1_OFFSET (0x3EC) -#define AUDIO_PEQ_24_A1 AUDIO_PEQ_24_A1 -#define AUDIO_PEQ_24_A1_POS (0U) -#define AUDIO_PEQ_24_A1_LEN (20U) -#define AUDIO_PEQ_24_A1_MSK (((1U << AUDIO_PEQ_24_A1_LEN) - 1) << AUDIO_PEQ_24_A1_POS) -#define AUDIO_PEQ_24_A1_UMSK (~(((1U << AUDIO_PEQ_24_A1_LEN) - 1) << AUDIO_PEQ_24_A1_POS)) - -/* 0x3F0 : peq_24_a2 */ -#define AUDIO_PEQ_24_A2_OFFSET (0x3F0) -#define AUDIO_PEQ_24_A2 AUDIO_PEQ_24_A2 -#define AUDIO_PEQ_24_A2_POS (0U) -#define AUDIO_PEQ_24_A2_LEN (20U) -#define AUDIO_PEQ_24_A2_MSK (((1U << AUDIO_PEQ_24_A2_LEN) - 1) << AUDIO_PEQ_24_A2_POS) -#define AUDIO_PEQ_24_A2_UMSK (~(((1U << AUDIO_PEQ_24_A2_LEN) - 1) << AUDIO_PEQ_24_A2_POS)) - -/* 0x400 : adc_h */ -#define AUDIO_ADC_H_OFFSET (0x400) -#define AUDIO_ADC_H_CTRL_RMP_RATE AUDIO_ADC_H_CTRL_RMP_RATE -#define AUDIO_ADC_H_CTRL_RMP_RATE_POS (2U) -#define AUDIO_ADC_H_CTRL_RMP_RATE_LEN (4U) -#define AUDIO_ADC_H_CTRL_RMP_RATE_MSK (((1U << AUDIO_ADC_H_CTRL_RMP_RATE_LEN) - 1) << AUDIO_ADC_H_CTRL_RMP_RATE_POS) -#define AUDIO_ADC_H_CTRL_RMP_RATE_UMSK (~(((1U << AUDIO_ADC_H_CTRL_RMP_RATE_LEN) - 1) << AUDIO_ADC_H_CTRL_RMP_RATE_POS)) -#define AUDIO_ADC_H_CTRL_ZCD_RATE AUDIO_ADC_H_CTRL_ZCD_RATE -#define AUDIO_ADC_H_CTRL_ZCD_RATE_POS (6U) -#define AUDIO_ADC_H_CTRL_ZCD_RATE_LEN (4U) -#define AUDIO_ADC_H_CTRL_ZCD_RATE_MSK (((1U << AUDIO_ADC_H_CTRL_ZCD_RATE_LEN) - 1) << AUDIO_ADC_H_CTRL_ZCD_RATE_POS) -#define AUDIO_ADC_H_CTRL_ZCD_RATE_UMSK (~(((1U << AUDIO_ADC_H_CTRL_ZCD_RATE_LEN) - 1) << AUDIO_ADC_H_CTRL_ZCD_RATE_POS)) -#define AUDIO_ADC_H_CTRL_MODE AUDIO_ADC_H_CTRL_MODE -#define AUDIO_ADC_H_CTRL_MODE_POS (10U) -#define AUDIO_ADC_H_CTRL_MODE_LEN (2U) -#define AUDIO_ADC_H_CTRL_MODE_MSK (((1U << AUDIO_ADC_H_CTRL_MODE_LEN) - 1) << AUDIO_ADC_H_CTRL_MODE_POS) -#define AUDIO_ADC_H_CTRL_MODE_UMSK (~(((1U << AUDIO_ADC_H_CTRL_MODE_LEN) - 1) << AUDIO_ADC_H_CTRL_MODE_POS)) -#define AUDIO_ADC_H_VOLUME_UPDATE AUDIO_ADC_H_VOLUME_UPDATE -#define AUDIO_ADC_H_VOLUME_UPDATE_POS (12U) -#define AUDIO_ADC_H_VOLUME_UPDATE_LEN (1U) -#define AUDIO_ADC_H_VOLUME_UPDATE_MSK (((1U << AUDIO_ADC_H_VOLUME_UPDATE_LEN) - 1) << AUDIO_ADC_H_VOLUME_UPDATE_POS) -#define AUDIO_ADC_H_VOLUME_UPDATE_UMSK (~(((1U << AUDIO_ADC_H_VOLUME_UPDATE_LEN) - 1) << AUDIO_ADC_H_VOLUME_UPDATE_POS)) -#define AUDIO_ADC_H_VOLUME AUDIO_ADC_H_VOLUME -#define AUDIO_ADC_H_VOLUME_POS (13U) -#define AUDIO_ADC_H_VOLUME_LEN (9U) -#define AUDIO_ADC_H_VOLUME_MSK (((1U << AUDIO_ADC_H_VOLUME_LEN) - 1) << AUDIO_ADC_H_VOLUME_POS) -#define AUDIO_ADC_H_VOLUME_UMSK (~(((1U << AUDIO_ADC_H_VOLUME_LEN) - 1) << AUDIO_ADC_H_VOLUME_POS)) -#define AUDIO_ADC_H_MUTE_RMPUP_RATE AUDIO_ADC_H_MUTE_RMPUP_RATE -#define AUDIO_ADC_H_MUTE_RMPUP_RATE_POS (22U) -#define AUDIO_ADC_H_MUTE_RMPUP_RATE_LEN (4U) -#define AUDIO_ADC_H_MUTE_RMPUP_RATE_MSK (((1U << AUDIO_ADC_H_MUTE_RMPUP_RATE_LEN) - 1) << AUDIO_ADC_H_MUTE_RMPUP_RATE_POS) -#define AUDIO_ADC_H_MUTE_RMPUP_RATE_UMSK (~(((1U << AUDIO_ADC_H_MUTE_RMPUP_RATE_LEN) - 1) << AUDIO_ADC_H_MUTE_RMPUP_RATE_POS)) -#define AUDIO_ADC_H_MUTE_RMPDN_RATE AUDIO_ADC_H_MUTE_RMPDN_RATE -#define AUDIO_ADC_H_MUTE_RMPDN_RATE_POS (26U) -#define AUDIO_ADC_H_MUTE_RMPDN_RATE_LEN (4U) -#define AUDIO_ADC_H_MUTE_RMPDN_RATE_MSK (((1U << AUDIO_ADC_H_MUTE_RMPDN_RATE_LEN) - 1) << AUDIO_ADC_H_MUTE_RMPDN_RATE_POS) -#define AUDIO_ADC_H_MUTE_RMPDN_RATE_UMSK (~(((1U << AUDIO_ADC_H_MUTE_RMPDN_RATE_LEN) - 1) << AUDIO_ADC_H_MUTE_RMPDN_RATE_POS)) -#define AUDIO_ADC_H_MUTE_SOFTMODE AUDIO_ADC_H_MUTE_SOFTMODE -#define AUDIO_ADC_H_MUTE_SOFTMODE_POS (30U) -#define AUDIO_ADC_H_MUTE_SOFTMODE_LEN (1U) -#define AUDIO_ADC_H_MUTE_SOFTMODE_MSK (((1U << AUDIO_ADC_H_MUTE_SOFTMODE_LEN) - 1) << AUDIO_ADC_H_MUTE_SOFTMODE_POS) -#define AUDIO_ADC_H_MUTE_SOFTMODE_UMSK (~(((1U << AUDIO_ADC_H_MUTE_SOFTMODE_LEN) - 1) << AUDIO_ADC_H_MUTE_SOFTMODE_POS)) -#define AUDIO_ADC_H_MUTE AUDIO_ADC_H_MUTE -#define AUDIO_ADC_H_MUTE_POS (31U) -#define AUDIO_ADC_H_MUTE_LEN (1U) -#define AUDIO_ADC_H_MUTE_MSK (((1U << AUDIO_ADC_H_MUTE_LEN) - 1) << AUDIO_ADC_H_MUTE_POS) -#define AUDIO_ADC_H_MUTE_UMSK (~(((1U << AUDIO_ADC_H_MUTE_LEN) - 1) << AUDIO_ADC_H_MUTE_POS)) - -/* 0x404 : adc_h_misc */ -#define AUDIO_ADC_H_MISC_OFFSET (0x404) -#define AUDIO_ADC_H_CTRL_ZCD_TIMEOUT AUDIO_ADC_H_CTRL_ZCD_TIMEOUT -#define AUDIO_ADC_H_CTRL_ZCD_TIMEOUT_POS (28U) -#define AUDIO_ADC_H_CTRL_ZCD_TIMEOUT_LEN (4U) -#define AUDIO_ADC_H_CTRL_ZCD_TIMEOUT_MSK (((1U << AUDIO_ADC_H_CTRL_ZCD_TIMEOUT_LEN) - 1) << AUDIO_ADC_H_CTRL_ZCD_TIMEOUT_POS) -#define AUDIO_ADC_H_CTRL_ZCD_TIMEOUT_UMSK (~(((1U << AUDIO_ADC_H_CTRL_ZCD_TIMEOUT_LEN) - 1) << AUDIO_ADC_H_CTRL_ZCD_TIMEOUT_POS)) - -/* 0x408 : adc_s0 */ -#define AUDIO_ADC_S0_OFFSET (0x408) -#define AUDIO_ADC_S0_CTRL_RMP_RATE AUDIO_ADC_S0_CTRL_RMP_RATE -#define AUDIO_ADC_S0_CTRL_RMP_RATE_POS (2U) -#define AUDIO_ADC_S0_CTRL_RMP_RATE_LEN (4U) -#define AUDIO_ADC_S0_CTRL_RMP_RATE_MSK (((1U << AUDIO_ADC_S0_CTRL_RMP_RATE_LEN) - 1) << AUDIO_ADC_S0_CTRL_RMP_RATE_POS) -#define AUDIO_ADC_S0_CTRL_RMP_RATE_UMSK (~(((1U << AUDIO_ADC_S0_CTRL_RMP_RATE_LEN) - 1) << AUDIO_ADC_S0_CTRL_RMP_RATE_POS)) -#define AUDIO_ADC_S0_CTRL_ZCD_RATE AUDIO_ADC_S0_CTRL_ZCD_RATE -#define AUDIO_ADC_S0_CTRL_ZCD_RATE_POS (6U) -#define AUDIO_ADC_S0_CTRL_ZCD_RATE_LEN (4U) -#define AUDIO_ADC_S0_CTRL_ZCD_RATE_MSK (((1U << AUDIO_ADC_S0_CTRL_ZCD_RATE_LEN) - 1) << AUDIO_ADC_S0_CTRL_ZCD_RATE_POS) -#define AUDIO_ADC_S0_CTRL_ZCD_RATE_UMSK (~(((1U << AUDIO_ADC_S0_CTRL_ZCD_RATE_LEN) - 1) << AUDIO_ADC_S0_CTRL_ZCD_RATE_POS)) -#define AUDIO_ADC_S0_CTRL_MODE AUDIO_ADC_S0_CTRL_MODE -#define AUDIO_ADC_S0_CTRL_MODE_POS (10U) -#define AUDIO_ADC_S0_CTRL_MODE_LEN (2U) -#define AUDIO_ADC_S0_CTRL_MODE_MSK (((1U << AUDIO_ADC_S0_CTRL_MODE_LEN) - 1) << AUDIO_ADC_S0_CTRL_MODE_POS) -#define AUDIO_ADC_S0_CTRL_MODE_UMSK (~(((1U << AUDIO_ADC_S0_CTRL_MODE_LEN) - 1) << AUDIO_ADC_S0_CTRL_MODE_POS)) -#define AUDIO_ADC_S0_VOLUME_UPDATE AUDIO_ADC_S0_VOLUME_UPDATE -#define AUDIO_ADC_S0_VOLUME_UPDATE_POS (12U) -#define AUDIO_ADC_S0_VOLUME_UPDATE_LEN (1U) -#define AUDIO_ADC_S0_VOLUME_UPDATE_MSK (((1U << AUDIO_ADC_S0_VOLUME_UPDATE_LEN) - 1) << AUDIO_ADC_S0_VOLUME_UPDATE_POS) -#define AUDIO_ADC_S0_VOLUME_UPDATE_UMSK (~(((1U << AUDIO_ADC_S0_VOLUME_UPDATE_LEN) - 1) << AUDIO_ADC_S0_VOLUME_UPDATE_POS)) -#define AUDIO_ADC_S0_VOLUME AUDIO_ADC_S0_VOLUME -#define AUDIO_ADC_S0_VOLUME_POS (13U) -#define AUDIO_ADC_S0_VOLUME_LEN (9U) -#define AUDIO_ADC_S0_VOLUME_MSK (((1U << AUDIO_ADC_S0_VOLUME_LEN) - 1) << AUDIO_ADC_S0_VOLUME_POS) -#define AUDIO_ADC_S0_VOLUME_UMSK (~(((1U << AUDIO_ADC_S0_VOLUME_LEN) - 1) << AUDIO_ADC_S0_VOLUME_POS)) -#define AUDIO_ADC_S0_MUTE_RMPUP_RATE AUDIO_ADC_S0_MUTE_RMPUP_RATE -#define AUDIO_ADC_S0_MUTE_RMPUP_RATE_POS (22U) -#define AUDIO_ADC_S0_MUTE_RMPUP_RATE_LEN (4U) -#define AUDIO_ADC_S0_MUTE_RMPUP_RATE_MSK (((1U << AUDIO_ADC_S0_MUTE_RMPUP_RATE_LEN) - 1) << AUDIO_ADC_S0_MUTE_RMPUP_RATE_POS) -#define AUDIO_ADC_S0_MUTE_RMPUP_RATE_UMSK (~(((1U << AUDIO_ADC_S0_MUTE_RMPUP_RATE_LEN) - 1) << AUDIO_ADC_S0_MUTE_RMPUP_RATE_POS)) -#define AUDIO_ADC_S0_MUTE_RMPDN_RATE AUDIO_ADC_S0_MUTE_RMPDN_RATE -#define AUDIO_ADC_S0_MUTE_RMPDN_RATE_POS (26U) -#define AUDIO_ADC_S0_MUTE_RMPDN_RATE_LEN (4U) -#define AUDIO_ADC_S0_MUTE_RMPDN_RATE_MSK (((1U << AUDIO_ADC_S0_MUTE_RMPDN_RATE_LEN) - 1) << AUDIO_ADC_S0_MUTE_RMPDN_RATE_POS) -#define AUDIO_ADC_S0_MUTE_RMPDN_RATE_UMSK (~(((1U << AUDIO_ADC_S0_MUTE_RMPDN_RATE_LEN) - 1) << AUDIO_ADC_S0_MUTE_RMPDN_RATE_POS)) -#define AUDIO_ADC_S0_MUTE_SOFTMODE AUDIO_ADC_S0_MUTE_SOFTMODE -#define AUDIO_ADC_S0_MUTE_SOFTMODE_POS (30U) -#define AUDIO_ADC_S0_MUTE_SOFTMODE_LEN (1U) -#define AUDIO_ADC_S0_MUTE_SOFTMODE_MSK (((1U << AUDIO_ADC_S0_MUTE_SOFTMODE_LEN) - 1) << AUDIO_ADC_S0_MUTE_SOFTMODE_POS) -#define AUDIO_ADC_S0_MUTE_SOFTMODE_UMSK (~(((1U << AUDIO_ADC_S0_MUTE_SOFTMODE_LEN) - 1) << AUDIO_ADC_S0_MUTE_SOFTMODE_POS)) -#define AUDIO_ADC_S0_MUTE AUDIO_ADC_S0_MUTE -#define AUDIO_ADC_S0_MUTE_POS (31U) -#define AUDIO_ADC_S0_MUTE_LEN (1U) -#define AUDIO_ADC_S0_MUTE_MSK (((1U << AUDIO_ADC_S0_MUTE_LEN) - 1) << AUDIO_ADC_S0_MUTE_POS) -#define AUDIO_ADC_S0_MUTE_UMSK (~(((1U << AUDIO_ADC_S0_MUTE_LEN) - 1) << AUDIO_ADC_S0_MUTE_POS)) - -/* 0x40C : adc_s0_misc */ -#define AUDIO_ADC_S0_MISC_OFFSET (0x40C) -#define AUDIO_ADC_S012_VOLUME_UPDATE AUDIO_ADC_S012_VOLUME_UPDATE -#define AUDIO_ADC_S012_VOLUME_UPDATE_POS (0U) -#define AUDIO_ADC_S012_VOLUME_UPDATE_LEN (1U) -#define AUDIO_ADC_S012_VOLUME_UPDATE_MSK (((1U << AUDIO_ADC_S012_VOLUME_UPDATE_LEN) - 1) << AUDIO_ADC_S012_VOLUME_UPDATE_POS) -#define AUDIO_ADC_S012_VOLUME_UPDATE_UMSK (~(((1U << AUDIO_ADC_S012_VOLUME_UPDATE_LEN) - 1) << AUDIO_ADC_S012_VOLUME_UPDATE_POS)) -#define AUDIO_ADC_S012_MUTE AUDIO_ADC_S012_MUTE -#define AUDIO_ADC_S012_MUTE_POS (1U) -#define AUDIO_ADC_S012_MUTE_LEN (1U) -#define AUDIO_ADC_S012_MUTE_MSK (((1U << AUDIO_ADC_S012_MUTE_LEN) - 1) << AUDIO_ADC_S012_MUTE_POS) -#define AUDIO_ADC_S012_MUTE_UMSK (~(((1U << AUDIO_ADC_S012_MUTE_LEN) - 1) << AUDIO_ADC_S012_MUTE_POS)) -#define AUDIO_ADC_S0_CTRL_ZCD_TIMEOUT AUDIO_ADC_S0_CTRL_ZCD_TIMEOUT -#define AUDIO_ADC_S0_CTRL_ZCD_TIMEOUT_POS (28U) -#define AUDIO_ADC_S0_CTRL_ZCD_TIMEOUT_LEN (4U) -#define AUDIO_ADC_S0_CTRL_ZCD_TIMEOUT_MSK (((1U << AUDIO_ADC_S0_CTRL_ZCD_TIMEOUT_LEN) - 1) << AUDIO_ADC_S0_CTRL_ZCD_TIMEOUT_POS) -#define AUDIO_ADC_S0_CTRL_ZCD_TIMEOUT_UMSK (~(((1U << AUDIO_ADC_S0_CTRL_ZCD_TIMEOUT_LEN) - 1) << AUDIO_ADC_S0_CTRL_ZCD_TIMEOUT_POS)) - -/* 0x410 : adc_s1 */ -#define AUDIO_ADC_S1_OFFSET (0x410) -#define AUDIO_ADC_S1_CTRL_RMP_RATE AUDIO_ADC_S1_CTRL_RMP_RATE -#define AUDIO_ADC_S1_CTRL_RMP_RATE_POS (2U) -#define AUDIO_ADC_S1_CTRL_RMP_RATE_LEN (4U) -#define AUDIO_ADC_S1_CTRL_RMP_RATE_MSK (((1U << AUDIO_ADC_S1_CTRL_RMP_RATE_LEN) - 1) << AUDIO_ADC_S1_CTRL_RMP_RATE_POS) -#define AUDIO_ADC_S1_CTRL_RMP_RATE_UMSK (~(((1U << AUDIO_ADC_S1_CTRL_RMP_RATE_LEN) - 1) << AUDIO_ADC_S1_CTRL_RMP_RATE_POS)) -#define AUDIO_ADC_S1_CTRL_ZCD_RATE AUDIO_ADC_S1_CTRL_ZCD_RATE -#define AUDIO_ADC_S1_CTRL_ZCD_RATE_POS (6U) -#define AUDIO_ADC_S1_CTRL_ZCD_RATE_LEN (4U) -#define AUDIO_ADC_S1_CTRL_ZCD_RATE_MSK (((1U << AUDIO_ADC_S1_CTRL_ZCD_RATE_LEN) - 1) << AUDIO_ADC_S1_CTRL_ZCD_RATE_POS) -#define AUDIO_ADC_S1_CTRL_ZCD_RATE_UMSK (~(((1U << AUDIO_ADC_S1_CTRL_ZCD_RATE_LEN) - 1) << AUDIO_ADC_S1_CTRL_ZCD_RATE_POS)) -#define AUDIO_ADC_S1_CTRL_MODE AUDIO_ADC_S1_CTRL_MODE -#define AUDIO_ADC_S1_CTRL_MODE_POS (10U) -#define AUDIO_ADC_S1_CTRL_MODE_LEN (2U) -#define AUDIO_ADC_S1_CTRL_MODE_MSK (((1U << AUDIO_ADC_S1_CTRL_MODE_LEN) - 1) << AUDIO_ADC_S1_CTRL_MODE_POS) -#define AUDIO_ADC_S1_CTRL_MODE_UMSK (~(((1U << AUDIO_ADC_S1_CTRL_MODE_LEN) - 1) << AUDIO_ADC_S1_CTRL_MODE_POS)) -#define AUDIO_ADC_S1_VOLUME_UPDATE AUDIO_ADC_S1_VOLUME_UPDATE -#define AUDIO_ADC_S1_VOLUME_UPDATE_POS (12U) -#define AUDIO_ADC_S1_VOLUME_UPDATE_LEN (1U) -#define AUDIO_ADC_S1_VOLUME_UPDATE_MSK (((1U << AUDIO_ADC_S1_VOLUME_UPDATE_LEN) - 1) << AUDIO_ADC_S1_VOLUME_UPDATE_POS) -#define AUDIO_ADC_S1_VOLUME_UPDATE_UMSK (~(((1U << AUDIO_ADC_S1_VOLUME_UPDATE_LEN) - 1) << AUDIO_ADC_S1_VOLUME_UPDATE_POS)) -#define AUDIO_ADC_S1_VOLUME AUDIO_ADC_S1_VOLUME -#define AUDIO_ADC_S1_VOLUME_POS (13U) -#define AUDIO_ADC_S1_VOLUME_LEN (9U) -#define AUDIO_ADC_S1_VOLUME_MSK (((1U << AUDIO_ADC_S1_VOLUME_LEN) - 1) << AUDIO_ADC_S1_VOLUME_POS) -#define AUDIO_ADC_S1_VOLUME_UMSK (~(((1U << AUDIO_ADC_S1_VOLUME_LEN) - 1) << AUDIO_ADC_S1_VOLUME_POS)) -#define AUDIO_ADC_S1_MUTE_RMPUP_RATE AUDIO_ADC_S1_MUTE_RMPUP_RATE -#define AUDIO_ADC_S1_MUTE_RMPUP_RATE_POS (22U) -#define AUDIO_ADC_S1_MUTE_RMPUP_RATE_LEN (4U) -#define AUDIO_ADC_S1_MUTE_RMPUP_RATE_MSK (((1U << AUDIO_ADC_S1_MUTE_RMPUP_RATE_LEN) - 1) << AUDIO_ADC_S1_MUTE_RMPUP_RATE_POS) -#define AUDIO_ADC_S1_MUTE_RMPUP_RATE_UMSK (~(((1U << AUDIO_ADC_S1_MUTE_RMPUP_RATE_LEN) - 1) << AUDIO_ADC_S1_MUTE_RMPUP_RATE_POS)) -#define AUDIO_ADC_S1_MUTE_RMPDN_RATE AUDIO_ADC_S1_MUTE_RMPDN_RATE -#define AUDIO_ADC_S1_MUTE_RMPDN_RATE_POS (26U) -#define AUDIO_ADC_S1_MUTE_RMPDN_RATE_LEN (4U) -#define AUDIO_ADC_S1_MUTE_RMPDN_RATE_MSK (((1U << AUDIO_ADC_S1_MUTE_RMPDN_RATE_LEN) - 1) << AUDIO_ADC_S1_MUTE_RMPDN_RATE_POS) -#define AUDIO_ADC_S1_MUTE_RMPDN_RATE_UMSK (~(((1U << AUDIO_ADC_S1_MUTE_RMPDN_RATE_LEN) - 1) << AUDIO_ADC_S1_MUTE_RMPDN_RATE_POS)) -#define AUDIO_ADC_S1_MUTE_SOFTMODE AUDIO_ADC_S1_MUTE_SOFTMODE -#define AUDIO_ADC_S1_MUTE_SOFTMODE_POS (30U) -#define AUDIO_ADC_S1_MUTE_SOFTMODE_LEN (1U) -#define AUDIO_ADC_S1_MUTE_SOFTMODE_MSK (((1U << AUDIO_ADC_S1_MUTE_SOFTMODE_LEN) - 1) << AUDIO_ADC_S1_MUTE_SOFTMODE_POS) -#define AUDIO_ADC_S1_MUTE_SOFTMODE_UMSK (~(((1U << AUDIO_ADC_S1_MUTE_SOFTMODE_LEN) - 1) << AUDIO_ADC_S1_MUTE_SOFTMODE_POS)) -#define AUDIO_ADC_S1_MUTE AUDIO_ADC_S1_MUTE -#define AUDIO_ADC_S1_MUTE_POS (31U) -#define AUDIO_ADC_S1_MUTE_LEN (1U) -#define AUDIO_ADC_S1_MUTE_MSK (((1U << AUDIO_ADC_S1_MUTE_LEN) - 1) << AUDIO_ADC_S1_MUTE_POS) -#define AUDIO_ADC_S1_MUTE_UMSK (~(((1U << AUDIO_ADC_S1_MUTE_LEN) - 1) << AUDIO_ADC_S1_MUTE_POS)) - -/* 0x414 : adc_s1_misc */ -#define AUDIO_ADC_S1_MISC_OFFSET (0x414) -#define AUDIO_ADC_S1_CTRL_ZCD_TIMEOUT AUDIO_ADC_S1_CTRL_ZCD_TIMEOUT -#define AUDIO_ADC_S1_CTRL_ZCD_TIMEOUT_POS (28U) -#define AUDIO_ADC_S1_CTRL_ZCD_TIMEOUT_LEN (4U) -#define AUDIO_ADC_S1_CTRL_ZCD_TIMEOUT_MSK (((1U << AUDIO_ADC_S1_CTRL_ZCD_TIMEOUT_LEN) - 1) << AUDIO_ADC_S1_CTRL_ZCD_TIMEOUT_POS) -#define AUDIO_ADC_S1_CTRL_ZCD_TIMEOUT_UMSK (~(((1U << AUDIO_ADC_S1_CTRL_ZCD_TIMEOUT_LEN) - 1) << AUDIO_ADC_S1_CTRL_ZCD_TIMEOUT_POS)) - -/* 0x418 : adc_s2 */ -#define AUDIO_ADC_S2_OFFSET (0x418) -#define AUDIO_ADC_S2_CTRL_RMP_RATE AUDIO_ADC_S2_CTRL_RMP_RATE -#define AUDIO_ADC_S2_CTRL_RMP_RATE_POS (2U) -#define AUDIO_ADC_S2_CTRL_RMP_RATE_LEN (4U) -#define AUDIO_ADC_S2_CTRL_RMP_RATE_MSK (((1U << AUDIO_ADC_S2_CTRL_RMP_RATE_LEN) - 1) << AUDIO_ADC_S2_CTRL_RMP_RATE_POS) -#define AUDIO_ADC_S2_CTRL_RMP_RATE_UMSK (~(((1U << AUDIO_ADC_S2_CTRL_RMP_RATE_LEN) - 1) << AUDIO_ADC_S2_CTRL_RMP_RATE_POS)) -#define AUDIO_ADC_S2_CTRL_ZCD_RATE AUDIO_ADC_S2_CTRL_ZCD_RATE -#define AUDIO_ADC_S2_CTRL_ZCD_RATE_POS (6U) -#define AUDIO_ADC_S2_CTRL_ZCD_RATE_LEN (4U) -#define AUDIO_ADC_S2_CTRL_ZCD_RATE_MSK (((1U << AUDIO_ADC_S2_CTRL_ZCD_RATE_LEN) - 1) << AUDIO_ADC_S2_CTRL_ZCD_RATE_POS) -#define AUDIO_ADC_S2_CTRL_ZCD_RATE_UMSK (~(((1U << AUDIO_ADC_S2_CTRL_ZCD_RATE_LEN) - 1) << AUDIO_ADC_S2_CTRL_ZCD_RATE_POS)) -#define AUDIO_ADC_S2_CTRL_MODE AUDIO_ADC_S2_CTRL_MODE -#define AUDIO_ADC_S2_CTRL_MODE_POS (10U) -#define AUDIO_ADC_S2_CTRL_MODE_LEN (2U) -#define AUDIO_ADC_S2_CTRL_MODE_MSK (((1U << AUDIO_ADC_S2_CTRL_MODE_LEN) - 1) << AUDIO_ADC_S2_CTRL_MODE_POS) -#define AUDIO_ADC_S2_CTRL_MODE_UMSK (~(((1U << AUDIO_ADC_S2_CTRL_MODE_LEN) - 1) << AUDIO_ADC_S2_CTRL_MODE_POS)) -#define AUDIO_ADC_S2_VOLUME_UPDATE AUDIO_ADC_S2_VOLUME_UPDATE -#define AUDIO_ADC_S2_VOLUME_UPDATE_POS (12U) -#define AUDIO_ADC_S2_VOLUME_UPDATE_LEN (1U) -#define AUDIO_ADC_S2_VOLUME_UPDATE_MSK (((1U << AUDIO_ADC_S2_VOLUME_UPDATE_LEN) - 1) << AUDIO_ADC_S2_VOLUME_UPDATE_POS) -#define AUDIO_ADC_S2_VOLUME_UPDATE_UMSK (~(((1U << AUDIO_ADC_S2_VOLUME_UPDATE_LEN) - 1) << AUDIO_ADC_S2_VOLUME_UPDATE_POS)) -#define AUDIO_ADC_S2_VOLUME AUDIO_ADC_S2_VOLUME -#define AUDIO_ADC_S2_VOLUME_POS (13U) -#define AUDIO_ADC_S2_VOLUME_LEN (9U) -#define AUDIO_ADC_S2_VOLUME_MSK (((1U << AUDIO_ADC_S2_VOLUME_LEN) - 1) << AUDIO_ADC_S2_VOLUME_POS) -#define AUDIO_ADC_S2_VOLUME_UMSK (~(((1U << AUDIO_ADC_S2_VOLUME_LEN) - 1) << AUDIO_ADC_S2_VOLUME_POS)) -#define AUDIO_ADC_S2_MUTE_RMPUP_RATE AUDIO_ADC_S2_MUTE_RMPUP_RATE -#define AUDIO_ADC_S2_MUTE_RMPUP_RATE_POS (22U) -#define AUDIO_ADC_S2_MUTE_RMPUP_RATE_LEN (4U) -#define AUDIO_ADC_S2_MUTE_RMPUP_RATE_MSK (((1U << AUDIO_ADC_S2_MUTE_RMPUP_RATE_LEN) - 1) << AUDIO_ADC_S2_MUTE_RMPUP_RATE_POS) -#define AUDIO_ADC_S2_MUTE_RMPUP_RATE_UMSK (~(((1U << AUDIO_ADC_S2_MUTE_RMPUP_RATE_LEN) - 1) << AUDIO_ADC_S2_MUTE_RMPUP_RATE_POS)) -#define AUDIO_ADC_S2_MUTE_RMPDN_RATE AUDIO_ADC_S2_MUTE_RMPDN_RATE -#define AUDIO_ADC_S2_MUTE_RMPDN_RATE_POS (26U) -#define AUDIO_ADC_S2_MUTE_RMPDN_RATE_LEN (4U) -#define AUDIO_ADC_S2_MUTE_RMPDN_RATE_MSK (((1U << AUDIO_ADC_S2_MUTE_RMPDN_RATE_LEN) - 1) << AUDIO_ADC_S2_MUTE_RMPDN_RATE_POS) -#define AUDIO_ADC_S2_MUTE_RMPDN_RATE_UMSK (~(((1U << AUDIO_ADC_S2_MUTE_RMPDN_RATE_LEN) - 1) << AUDIO_ADC_S2_MUTE_RMPDN_RATE_POS)) -#define AUDIO_ADC_S2_MUTE_SOFTMODE AUDIO_ADC_S2_MUTE_SOFTMODE -#define AUDIO_ADC_S2_MUTE_SOFTMODE_POS (30U) -#define AUDIO_ADC_S2_MUTE_SOFTMODE_LEN (1U) -#define AUDIO_ADC_S2_MUTE_SOFTMODE_MSK (((1U << AUDIO_ADC_S2_MUTE_SOFTMODE_LEN) - 1) << AUDIO_ADC_S2_MUTE_SOFTMODE_POS) -#define AUDIO_ADC_S2_MUTE_SOFTMODE_UMSK (~(((1U << AUDIO_ADC_S2_MUTE_SOFTMODE_LEN) - 1) << AUDIO_ADC_S2_MUTE_SOFTMODE_POS)) -#define AUDIO_ADC_S2_MUTE AUDIO_ADC_S2_MUTE -#define AUDIO_ADC_S2_MUTE_POS (31U) -#define AUDIO_ADC_S2_MUTE_LEN (1U) -#define AUDIO_ADC_S2_MUTE_MSK (((1U << AUDIO_ADC_S2_MUTE_LEN) - 1) << AUDIO_ADC_S2_MUTE_POS) -#define AUDIO_ADC_S2_MUTE_UMSK (~(((1U << AUDIO_ADC_S2_MUTE_LEN) - 1) << AUDIO_ADC_S2_MUTE_POS)) - -/* 0x41C : adc_s2_misc */ -#define AUDIO_ADC_S2_MISC_OFFSET (0x41C) -#define AUDIO_ADC_S2_CTRL_ZCD_TIMEOUT AUDIO_ADC_S2_CTRL_ZCD_TIMEOUT -#define AUDIO_ADC_S2_CTRL_ZCD_TIMEOUT_POS (28U) -#define AUDIO_ADC_S2_CTRL_ZCD_TIMEOUT_LEN (4U) -#define AUDIO_ADC_S2_CTRL_ZCD_TIMEOUT_MSK (((1U << AUDIO_ADC_S2_CTRL_ZCD_TIMEOUT_LEN) - 1) << AUDIO_ADC_S2_CTRL_ZCD_TIMEOUT_POS) -#define AUDIO_ADC_S2_CTRL_ZCD_TIMEOUT_UMSK (~(((1U << AUDIO_ADC_S2_CTRL_ZCD_TIMEOUT_LEN) - 1) << AUDIO_ADC_S2_CTRL_ZCD_TIMEOUT_POS)) - -/* 0x420 : adc_agc_0 */ -#define AUDIO_ADC_AGC_0_OFFSET (0x420) -#define AUDIO_ADC_AGC_EN AUDIO_ADC_AGC_EN -#define AUDIO_ADC_AGC_EN_POS (0U) -#define AUDIO_ADC_AGC_EN_LEN (1U) -#define AUDIO_ADC_AGC_EN_MSK (((1U << AUDIO_ADC_AGC_EN_LEN) - 1) << AUDIO_ADC_AGC_EN_POS) -#define AUDIO_ADC_AGC_EN_UMSK (~(((1U << AUDIO_ADC_AGC_EN_LEN) - 1) << AUDIO_ADC_AGC_EN_POS)) -#define AUDIO_AGC_MIN_GAIN_QDB AUDIO_AGC_MIN_GAIN_QDB -#define AUDIO_AGC_MIN_GAIN_QDB_POS (3U) -#define AUDIO_AGC_MIN_GAIN_QDB_LEN (9U) -#define AUDIO_AGC_MIN_GAIN_QDB_MSK (((1U << AUDIO_AGC_MIN_GAIN_QDB_LEN) - 1) << AUDIO_AGC_MIN_GAIN_QDB_POS) -#define AUDIO_AGC_MIN_GAIN_QDB_UMSK (~(((1U << AUDIO_AGC_MIN_GAIN_QDB_LEN) - 1) << AUDIO_AGC_MIN_GAIN_QDB_POS)) -#define AUDIO_AGC_MAX_GAIN_QDB AUDIO_AGC_MAX_GAIN_QDB -#define AUDIO_AGC_MAX_GAIN_QDB_POS (12U) -#define AUDIO_AGC_MAX_GAIN_QDB_LEN (9U) -#define AUDIO_AGC_MAX_GAIN_QDB_MSK (((1U << AUDIO_AGC_MAX_GAIN_QDB_LEN) - 1) << AUDIO_AGC_MAX_GAIN_QDB_POS) -#define AUDIO_AGC_MAX_GAIN_QDB_UMSK (~(((1U << AUDIO_AGC_MAX_GAIN_QDB_LEN) - 1) << AUDIO_AGC_MAX_GAIN_QDB_POS)) -#define AUDIO_AGC_FORCE_GAIN_IND AUDIO_AGC_FORCE_GAIN_IND -#define AUDIO_AGC_FORCE_GAIN_IND_POS (21U) -#define AUDIO_AGC_FORCE_GAIN_IND_LEN (10U) -#define AUDIO_AGC_FORCE_GAIN_IND_MSK (((1U << AUDIO_AGC_FORCE_GAIN_IND_LEN) - 1) << AUDIO_AGC_FORCE_GAIN_IND_POS) -#define AUDIO_AGC_FORCE_GAIN_IND_UMSK (~(((1U << AUDIO_AGC_FORCE_GAIN_IND_LEN) - 1) << AUDIO_AGC_FORCE_GAIN_IND_POS)) -#define AUDIO_AGC_FORCE_GAIN_EN AUDIO_AGC_FORCE_GAIN_EN -#define AUDIO_AGC_FORCE_GAIN_EN_POS (31U) -#define AUDIO_AGC_FORCE_GAIN_EN_LEN (1U) -#define AUDIO_AGC_FORCE_GAIN_EN_MSK (((1U << AUDIO_AGC_FORCE_GAIN_EN_LEN) - 1) << AUDIO_AGC_FORCE_GAIN_EN_POS) -#define AUDIO_AGC_FORCE_GAIN_EN_UMSK (~(((1U << AUDIO_AGC_FORCE_GAIN_EN_LEN) - 1) << AUDIO_AGC_FORCE_GAIN_EN_POS)) - -/* 0x424 : adc_agc_1 */ -#define AUDIO_ADC_AGC_1_OFFSET (0x424) -#define AUDIO_ADC0_PGA_HW_CTRL AUDIO_ADC0_PGA_HW_CTRL -#define AUDIO_ADC0_PGA_HW_CTRL_POS (0U) -#define AUDIO_ADC0_PGA_HW_CTRL_LEN (1U) -#define AUDIO_ADC0_PGA_HW_CTRL_MSK (((1U << AUDIO_ADC0_PGA_HW_CTRL_LEN) - 1) << AUDIO_ADC0_PGA_HW_CTRL_POS) -#define AUDIO_ADC0_PGA_HW_CTRL_UMSK (~(((1U << AUDIO_ADC0_PGA_HW_CTRL_LEN) - 1) << AUDIO_ADC0_PGA_HW_CTRL_POS)) -#define AUDIO_ADC1_PGA_HW_CTRL AUDIO_ADC1_PGA_HW_CTRL -#define AUDIO_ADC1_PGA_HW_CTRL_POS (1U) -#define AUDIO_ADC1_PGA_HW_CTRL_LEN (1U) -#define AUDIO_ADC1_PGA_HW_CTRL_MSK (((1U << AUDIO_ADC1_PGA_HW_CTRL_LEN) - 1) << AUDIO_ADC1_PGA_HW_CTRL_POS) -#define AUDIO_ADC1_PGA_HW_CTRL_UMSK (~(((1U << AUDIO_ADC1_PGA_HW_CTRL_LEN) - 1) << AUDIO_ADC1_PGA_HW_CTRL_POS)) -#define AUDIO_ADC2_PGA_HW_CTRL AUDIO_ADC2_PGA_HW_CTRL -#define AUDIO_ADC2_PGA_HW_CTRL_POS (2U) -#define AUDIO_ADC2_PGA_HW_CTRL_LEN (1U) -#define AUDIO_ADC2_PGA_HW_CTRL_MSK (((1U << AUDIO_ADC2_PGA_HW_CTRL_LEN) - 1) << AUDIO_ADC2_PGA_HW_CTRL_POS) -#define AUDIO_ADC2_PGA_HW_CTRL_UMSK (~(((1U << AUDIO_ADC2_PGA_HW_CTRL_LEN) - 1) << AUDIO_ADC2_PGA_HW_CTRL_POS)) -#define AUDIO_AGC_ATTACK_TIME_MS AUDIO_AGC_ATTACK_TIME_MS -#define AUDIO_AGC_ATTACK_TIME_MS_POS (4U) -#define AUDIO_AGC_ATTACK_TIME_MS_LEN (4U) -#define AUDIO_AGC_ATTACK_TIME_MS_MSK (((1U << AUDIO_AGC_ATTACK_TIME_MS_LEN) - 1) << AUDIO_AGC_ATTACK_TIME_MS_POS) -#define AUDIO_AGC_ATTACK_TIME_MS_UMSK (~(((1U << AUDIO_AGC_ATTACK_TIME_MS_LEN) - 1) << AUDIO_AGC_ATTACK_TIME_MS_POS)) -#define AUDIO_AGC_DECAY_TIME_MS AUDIO_AGC_DECAY_TIME_MS -#define AUDIO_AGC_DECAY_TIME_MS_POS (8U) -#define AUDIO_AGC_DECAY_TIME_MS_LEN (4U) -#define AUDIO_AGC_DECAY_TIME_MS_MSK (((1U << AUDIO_AGC_DECAY_TIME_MS_LEN) - 1) << AUDIO_AGC_DECAY_TIME_MS_POS) -#define AUDIO_AGC_DECAY_TIME_MS_UMSK (~(((1U << AUDIO_AGC_DECAY_TIME_MS_LEN) - 1) << AUDIO_AGC_DECAY_TIME_MS_POS)) -#define AUDIO_AGC_HOLD_TIME_MS AUDIO_AGC_HOLD_TIME_MS -#define AUDIO_AGC_HOLD_TIME_MS_POS (12U) -#define AUDIO_AGC_HOLD_TIME_MS_LEN (4U) -#define AUDIO_AGC_HOLD_TIME_MS_MSK (((1U << AUDIO_AGC_HOLD_TIME_MS_LEN) - 1) << AUDIO_AGC_HOLD_TIME_MS_POS) -#define AUDIO_AGC_HOLD_TIME_MS_UMSK (~(((1U << AUDIO_AGC_HOLD_TIME_MS_LEN) - 1) << AUDIO_AGC_HOLD_TIME_MS_POS)) -#define AUDIO_AGC_LEVEL_HYST_DECAY AUDIO_AGC_LEVEL_HYST_DECAY -#define AUDIO_AGC_LEVEL_HYST_DECAY_POS (16U) -#define AUDIO_AGC_LEVEL_HYST_DECAY_LEN (5U) -#define AUDIO_AGC_LEVEL_HYST_DECAY_MSK (((1U << AUDIO_AGC_LEVEL_HYST_DECAY_LEN) - 1) << AUDIO_AGC_LEVEL_HYST_DECAY_POS) -#define AUDIO_AGC_LEVEL_HYST_DECAY_UMSK (~(((1U << AUDIO_AGC_LEVEL_HYST_DECAY_LEN) - 1) << AUDIO_AGC_LEVEL_HYST_DECAY_POS)) -#define AUDIO_AGC_LEVEL_HYST_ATTACK AUDIO_AGC_LEVEL_HYST_ATTACK -#define AUDIO_AGC_LEVEL_HYST_ATTACK_POS (21U) -#define AUDIO_AGC_LEVEL_HYST_ATTACK_LEN (5U) -#define AUDIO_AGC_LEVEL_HYST_ATTACK_MSK (((1U << AUDIO_AGC_LEVEL_HYST_ATTACK_LEN) - 1) << AUDIO_AGC_LEVEL_HYST_ATTACK_POS) -#define AUDIO_AGC_LEVEL_HYST_ATTACK_UMSK (~(((1U << AUDIO_AGC_LEVEL_HYST_ATTACK_LEN) - 1) << AUDIO_AGC_LEVEL_HYST_ATTACK_POS)) -#define AUDIO_AGC_LEVEL_TARGET AUDIO_AGC_LEVEL_TARGET -#define AUDIO_AGC_LEVEL_TARGET_POS (26U) -#define AUDIO_AGC_LEVEL_TARGET_LEN (6U) -#define AUDIO_AGC_LEVEL_TARGET_MSK (((1U << AUDIO_AGC_LEVEL_TARGET_LEN) - 1) << AUDIO_AGC_LEVEL_TARGET_POS) -#define AUDIO_AGC_LEVEL_TARGET_UMSK (~(((1U << AUDIO_AGC_LEVEL_TARGET_LEN) - 1) << AUDIO_AGC_LEVEL_TARGET_POS)) - -/* 0x428 : adc_agc_2 */ -#define AUDIO_ADC_AGC_2_OFFSET (0x428) -#define AUDIO_AGC_NOISE_ENTER_TIME_MS AUDIO_AGC_NOISE_ENTER_TIME_MS -#define AUDIO_AGC_NOISE_ENTER_TIME_MS_POS (0U) -#define AUDIO_AGC_NOISE_ENTER_TIME_MS_LEN (7U) -#define AUDIO_AGC_NOISE_ENTER_TIME_MS_MSK (((1U << AUDIO_AGC_NOISE_ENTER_TIME_MS_LEN) - 1) << AUDIO_AGC_NOISE_ENTER_TIME_MS_POS) -#define AUDIO_AGC_NOISE_ENTER_TIME_MS_UMSK (~(((1U << AUDIO_AGC_NOISE_ENTER_TIME_MS_LEN) - 1) << AUDIO_AGC_NOISE_ENTER_TIME_MS_POS)) -#define AUDIO_AGC_SILENCE_GAIN_WAIT_MS AUDIO_AGC_SILENCE_GAIN_WAIT_MS -#define AUDIO_AGC_SILENCE_GAIN_WAIT_MS_POS (7U) -#define AUDIO_AGC_SILENCE_GAIN_WAIT_MS_LEN (4U) -#define AUDIO_AGC_SILENCE_GAIN_WAIT_MS_MSK (((1U << AUDIO_AGC_SILENCE_GAIN_WAIT_MS_LEN) - 1) << AUDIO_AGC_SILENCE_GAIN_WAIT_MS_POS) -#define AUDIO_AGC_SILENCE_GAIN_WAIT_MS_UMSK (~(((1U << AUDIO_AGC_SILENCE_GAIN_WAIT_MS_LEN) - 1) << AUDIO_AGC_SILENCE_GAIN_WAIT_MS_POS)) -#define AUDIO_AGC_SILENCE_GAIN_QDB AUDIO_AGC_SILENCE_GAIN_QDB -#define AUDIO_AGC_SILENCE_GAIN_QDB_POS (11U) -#define AUDIO_AGC_SILENCE_GAIN_QDB_LEN (10U) -#define AUDIO_AGC_SILENCE_GAIN_QDB_MSK (((1U << AUDIO_AGC_SILENCE_GAIN_QDB_LEN) - 1) << AUDIO_AGC_SILENCE_GAIN_QDB_POS) -#define AUDIO_AGC_SILENCE_GAIN_QDB_UMSK (~(((1U << AUDIO_AGC_SILENCE_GAIN_QDB_LEN) - 1) << AUDIO_AGC_SILENCE_GAIN_QDB_POS)) -#define AUDIO_AGC_NOISE_GATE_HYST AUDIO_AGC_NOISE_GATE_HYST -#define AUDIO_AGC_NOISE_GATE_HYST_POS (21U) -#define AUDIO_AGC_NOISE_GATE_HYST_LEN (3U) -#define AUDIO_AGC_NOISE_GATE_HYST_MSK (((1U << AUDIO_AGC_NOISE_GATE_HYST_LEN) - 1) << AUDIO_AGC_NOISE_GATE_HYST_POS) -#define AUDIO_AGC_NOISE_GATE_HYST_UMSK (~(((1U << AUDIO_AGC_NOISE_GATE_HYST_LEN) - 1) << AUDIO_AGC_NOISE_GATE_HYST_POS)) -#define AUDIO_AGC_NOISE_GATE_TH AUDIO_AGC_NOISE_GATE_TH -#define AUDIO_AGC_NOISE_GATE_TH_POS (24U) -#define AUDIO_AGC_NOISE_GATE_TH_LEN (8U) -#define AUDIO_AGC_NOISE_GATE_TH_MSK (((1U << AUDIO_AGC_NOISE_GATE_TH_LEN) - 1) << AUDIO_AGC_NOISE_GATE_TH_POS) -#define AUDIO_AGC_NOISE_GATE_TH_UMSK (~(((1U << AUDIO_AGC_NOISE_GATE_TH_LEN) - 1) << AUDIO_AGC_NOISE_GATE_TH_POS)) - -/* 0x42C : adc_agc_3 */ -#define AUDIO_ADC_AGC_3_OFFSET (0x42C) -#define AUDIO_AGC_PGA_CTRL_EN AUDIO_AGC_PGA_CTRL_EN -#define AUDIO_AGC_PGA_CTRL_EN_POS (2U) -#define AUDIO_AGC_PGA_CTRL_EN_LEN (1U) -#define AUDIO_AGC_PGA_CTRL_EN_MSK (((1U << AUDIO_AGC_PGA_CTRL_EN_LEN) - 1) << AUDIO_AGC_PGA_CTRL_EN_POS) -#define AUDIO_AGC_PGA_CTRL_EN_UMSK (~(((1U << AUDIO_AGC_PGA_CTRL_EN_LEN) - 1) << AUDIO_AGC_PGA_CTRL_EN_POS)) -#define AUDIO_AGC_AVERAGE_TIME AUDIO_AGC_AVERAGE_TIME -#define AUDIO_AGC_AVERAGE_TIME_POS (3U) -#define AUDIO_AGC_AVERAGE_TIME_LEN (5U) -#define AUDIO_AGC_AVERAGE_TIME_MSK (((1U << AUDIO_AGC_AVERAGE_TIME_LEN) - 1) << AUDIO_AGC_AVERAGE_TIME_POS) -#define AUDIO_AGC_AVERAGE_TIME_UMSK (~(((1U << AUDIO_AGC_AVERAGE_TIME_LEN) - 1) << AUDIO_AGC_AVERAGE_TIME_POS)) -#define AUDIO_AGC_RELEASE_TIME AUDIO_AGC_RELEASE_TIME -#define AUDIO_AGC_RELEASE_TIME_POS (8U) -#define AUDIO_AGC_RELEASE_TIME_LEN (5U) -#define AUDIO_AGC_RELEASE_TIME_MSK (((1U << AUDIO_AGC_RELEASE_TIME_LEN) - 1) << AUDIO_AGC_RELEASE_TIME_POS) -#define AUDIO_AGC_RELEASE_TIME_UMSK (~(((1U << AUDIO_AGC_RELEASE_TIME_LEN) - 1) << AUDIO_AGC_RELEASE_TIME_POS)) -#define AUDIO_AGC_ATTACK_TIME AUDIO_AGC_ATTACK_TIME -#define AUDIO_AGC_ATTACK_TIME_POS (13U) -#define AUDIO_AGC_ATTACK_TIME_LEN (5U) -#define AUDIO_AGC_ATTACK_TIME_MSK (((1U << AUDIO_AGC_ATTACK_TIME_LEN) - 1) << AUDIO_AGC_ATTACK_TIME_POS) -#define AUDIO_AGC_ATTACK_TIME_UMSK (~(((1U << AUDIO_AGC_ATTACK_TIME_LEN) - 1) << AUDIO_AGC_ATTACK_TIME_POS)) -#define AUDIO_AGC_DETECT_MODE AUDIO_AGC_DETECT_MODE -#define AUDIO_AGC_DETECT_MODE_POS (18U) -#define AUDIO_AGC_DETECT_MODE_LEN (1U) -#define AUDIO_AGC_DETECT_MODE_MSK (((1U << AUDIO_AGC_DETECT_MODE_LEN) - 1) << AUDIO_AGC_DETECT_MODE_POS) -#define AUDIO_AGC_DETECT_MODE_UMSK (~(((1U << AUDIO_AGC_DETECT_MODE_LEN) - 1) << AUDIO_AGC_DETECT_MODE_POS)) -#define AUDIO_AGC_SRC_SELECT AUDIO_AGC_SRC_SELECT -#define AUDIO_AGC_SRC_SELECT_POS (19U) -#define AUDIO_AGC_SRC_SELECT_LEN (2U) -#define AUDIO_AGC_SRC_SELECT_MSK (((1U << AUDIO_AGC_SRC_SELECT_LEN) - 1) << AUDIO_AGC_SRC_SELECT_POS) -#define AUDIO_AGC_SRC_SELECT_UMSK (~(((1U << AUDIO_AGC_SRC_SELECT_LEN) - 1) << AUDIO_AGC_SRC_SELECT_POS)) -#define AUDIO_AGC_DBV_SETTLE_TIME AUDIO_AGC_DBV_SETTLE_TIME -#define AUDIO_AGC_DBV_SETTLE_TIME_POS (21U) -#define AUDIO_AGC_DBV_SETTLE_TIME_LEN (4U) -#define AUDIO_AGC_DBV_SETTLE_TIME_MSK (((1U << AUDIO_AGC_DBV_SETTLE_TIME_LEN) - 1) << AUDIO_AGC_DBV_SETTLE_TIME_POS) -#define AUDIO_AGC_DBV_SETTLE_TIME_UMSK (~(((1U << AUDIO_AGC_DBV_SETTLE_TIME_LEN) - 1) << AUDIO_AGC_DBV_SETTLE_TIME_POS)) -#define AUDIO_AGC_NOISE_EXIT_TIME_MS AUDIO_AGC_NOISE_EXIT_TIME_MS -#define AUDIO_AGC_NOISE_EXIT_TIME_MS_POS (25U) -#define AUDIO_AGC_NOISE_EXIT_TIME_MS_LEN (7U) -#define AUDIO_AGC_NOISE_EXIT_TIME_MS_MSK (((1U << AUDIO_AGC_NOISE_EXIT_TIME_MS_LEN) - 1) << AUDIO_AGC_NOISE_EXIT_TIME_MS_POS) -#define AUDIO_AGC_NOISE_EXIT_TIME_MS_UMSK (~(((1U << AUDIO_AGC_NOISE_EXIT_TIME_MS_LEN) - 1) << AUDIO_AGC_NOISE_EXIT_TIME_MS_POS)) - -/* 0x430 : audio_status */ -#define AUDIO_STATUS_OFFSET (0x430) -#define AUDIO_ADC_H0_BUSY AUDIO_ADC_H0_BUSY -#define AUDIO_ADC_H0_BUSY_POS (0U) -#define AUDIO_ADC_H0_BUSY_LEN (1U) -#define AUDIO_ADC_H0_BUSY_MSK (((1U << AUDIO_ADC_H0_BUSY_LEN) - 1) << AUDIO_ADC_H0_BUSY_POS) -#define AUDIO_ADC_H0_BUSY_UMSK (~(((1U << AUDIO_ADC_H0_BUSY_LEN) - 1) << AUDIO_ADC_H0_BUSY_POS)) -#define AUDIO_ADC_H0_MUTE_DONE AUDIO_ADC_H0_MUTE_DONE -#define AUDIO_ADC_H0_MUTE_DONE_POS (1U) -#define AUDIO_ADC_H0_MUTE_DONE_LEN (1U) -#define AUDIO_ADC_H0_MUTE_DONE_MSK (((1U << AUDIO_ADC_H0_MUTE_DONE_LEN) - 1) << AUDIO_ADC_H0_MUTE_DONE_POS) -#define AUDIO_ADC_H0_MUTE_DONE_UMSK (~(((1U << AUDIO_ADC_H0_MUTE_DONE_LEN) - 1) << AUDIO_ADC_H0_MUTE_DONE_POS)) -#define AUDIO_ADC_H1_BUSY AUDIO_ADC_H1_BUSY -#define AUDIO_ADC_H1_BUSY_POS (2U) -#define AUDIO_ADC_H1_BUSY_LEN (1U) -#define AUDIO_ADC_H1_BUSY_MSK (((1U << AUDIO_ADC_H1_BUSY_LEN) - 1) << AUDIO_ADC_H1_BUSY_POS) -#define AUDIO_ADC_H1_BUSY_UMSK (~(((1U << AUDIO_ADC_H1_BUSY_LEN) - 1) << AUDIO_ADC_H1_BUSY_POS)) -#define AUDIO_ADC_H1_MUTE_DONE AUDIO_ADC_H1_MUTE_DONE -#define AUDIO_ADC_H1_MUTE_DONE_POS (3U) -#define AUDIO_ADC_H1_MUTE_DONE_LEN (1U) -#define AUDIO_ADC_H1_MUTE_DONE_MSK (((1U << AUDIO_ADC_H1_MUTE_DONE_LEN) - 1) << AUDIO_ADC_H1_MUTE_DONE_POS) -#define AUDIO_ADC_H1_MUTE_DONE_UMSK (~(((1U << AUDIO_ADC_H1_MUTE_DONE_LEN) - 1) << AUDIO_ADC_H1_MUTE_DONE_POS)) -#define AUDIO_ADC_H2_BUSY AUDIO_ADC_H2_BUSY -#define AUDIO_ADC_H2_BUSY_POS (4U) -#define AUDIO_ADC_H2_BUSY_LEN (1U) -#define AUDIO_ADC_H2_BUSY_MSK (((1U << AUDIO_ADC_H2_BUSY_LEN) - 1) << AUDIO_ADC_H2_BUSY_POS) -#define AUDIO_ADC_H2_BUSY_UMSK (~(((1U << AUDIO_ADC_H2_BUSY_LEN) - 1) << AUDIO_ADC_H2_BUSY_POS)) -#define AUDIO_ADC_H2_MUTE_DONE AUDIO_ADC_H2_MUTE_DONE -#define AUDIO_ADC_H2_MUTE_DONE_POS (5U) -#define AUDIO_ADC_H2_MUTE_DONE_LEN (1U) -#define AUDIO_ADC_H2_MUTE_DONE_MSK (((1U << AUDIO_ADC_H2_MUTE_DONE_LEN) - 1) << AUDIO_ADC_H2_MUTE_DONE_POS) -#define AUDIO_ADC_H2_MUTE_DONE_UMSK (~(((1U << AUDIO_ADC_H2_MUTE_DONE_LEN) - 1) << AUDIO_ADC_H2_MUTE_DONE_POS)) -#define AUDIO_ADC_S0_INT AUDIO_ADC_S0_INT -#define AUDIO_ADC_S0_INT_POS (6U) -#define AUDIO_ADC_S0_INT_LEN (1U) -#define AUDIO_ADC_S0_INT_MSK (((1U << AUDIO_ADC_S0_INT_LEN) - 1) << AUDIO_ADC_S0_INT_POS) -#define AUDIO_ADC_S0_INT_UMSK (~(((1U << AUDIO_ADC_S0_INT_LEN) - 1) << AUDIO_ADC_S0_INT_POS)) -#define AUDIO_ADC_S0_INT_CLR AUDIO_ADC_S0_INT_CLR -#define AUDIO_ADC_S0_INT_CLR_POS (7U) -#define AUDIO_ADC_S0_INT_CLR_LEN (1U) -#define AUDIO_ADC_S0_INT_CLR_MSK (((1U << AUDIO_ADC_S0_INT_CLR_LEN) - 1) << AUDIO_ADC_S0_INT_CLR_POS) -#define AUDIO_ADC_S0_INT_CLR_UMSK (~(((1U << AUDIO_ADC_S0_INT_CLR_LEN) - 1) << AUDIO_ADC_S0_INT_CLR_POS)) -#define AUDIO_ADC_S1_INT AUDIO_ADC_S1_INT -#define AUDIO_ADC_S1_INT_POS (8U) -#define AUDIO_ADC_S1_INT_LEN (1U) -#define AUDIO_ADC_S1_INT_MSK (((1U << AUDIO_ADC_S1_INT_LEN) - 1) << AUDIO_ADC_S1_INT_POS) -#define AUDIO_ADC_S1_INT_UMSK (~(((1U << AUDIO_ADC_S1_INT_LEN) - 1) << AUDIO_ADC_S1_INT_POS)) -#define AUDIO_ADC_S1_INT_CLR AUDIO_ADC_S1_INT_CLR -#define AUDIO_ADC_S1_INT_CLR_POS (9U) -#define AUDIO_ADC_S1_INT_CLR_LEN (1U) -#define AUDIO_ADC_S1_INT_CLR_MSK (((1U << AUDIO_ADC_S1_INT_CLR_LEN) - 1) << AUDIO_ADC_S1_INT_CLR_POS) -#define AUDIO_ADC_S1_INT_CLR_UMSK (~(((1U << AUDIO_ADC_S1_INT_CLR_LEN) - 1) << AUDIO_ADC_S1_INT_CLR_POS)) -#define AUDIO_ADC_S2_INT AUDIO_ADC_S2_INT -#define AUDIO_ADC_S2_INT_POS (10U) -#define AUDIO_ADC_S2_INT_LEN (1U) -#define AUDIO_ADC_S2_INT_MSK (((1U << AUDIO_ADC_S2_INT_LEN) - 1) << AUDIO_ADC_S2_INT_POS) -#define AUDIO_ADC_S2_INT_UMSK (~(((1U << AUDIO_ADC_S2_INT_LEN) - 1) << AUDIO_ADC_S2_INT_POS)) -#define AUDIO_ADC_S2_INT_CLR AUDIO_ADC_S2_INT_CLR -#define AUDIO_ADC_S2_INT_CLR_POS (11U) -#define AUDIO_ADC_S2_INT_CLR_LEN (1U) -#define AUDIO_ADC_S2_INT_CLR_MSK (((1U << AUDIO_ADC_S2_INT_CLR_LEN) - 1) << AUDIO_ADC_S2_INT_CLR_POS) -#define AUDIO_ADC_S2_INT_CLR_UMSK (~(((1U << AUDIO_ADC_S2_INT_CLR_LEN) - 1) << AUDIO_ADC_S2_INT_CLR_POS)) -#define AUDIO_DAC_H0_BUSY AUDIO_DAC_H0_BUSY -#define AUDIO_DAC_H0_BUSY_POS (12U) -#define AUDIO_DAC_H0_BUSY_LEN (1U) -#define AUDIO_DAC_H0_BUSY_MSK (((1U << AUDIO_DAC_H0_BUSY_LEN) - 1) << AUDIO_DAC_H0_BUSY_POS) -#define AUDIO_DAC_H0_BUSY_UMSK (~(((1U << AUDIO_DAC_H0_BUSY_LEN) - 1) << AUDIO_DAC_H0_BUSY_POS)) -#define AUDIO_DAC_H0_MUTE_DONE AUDIO_DAC_H0_MUTE_DONE -#define AUDIO_DAC_H0_MUTE_DONE_POS (13U) -#define AUDIO_DAC_H0_MUTE_DONE_LEN (1U) -#define AUDIO_DAC_H0_MUTE_DONE_MSK (((1U << AUDIO_DAC_H0_MUTE_DONE_LEN) - 1) << AUDIO_DAC_H0_MUTE_DONE_POS) -#define AUDIO_DAC_H0_MUTE_DONE_UMSK (~(((1U << AUDIO_DAC_H0_MUTE_DONE_LEN) - 1) << AUDIO_DAC_H0_MUTE_DONE_POS)) -#define AUDIO_DAC_H1_BUSY AUDIO_DAC_H1_BUSY -#define AUDIO_DAC_H1_BUSY_POS (14U) -#define AUDIO_DAC_H1_BUSY_LEN (1U) -#define AUDIO_DAC_H1_BUSY_MSK (((1U << AUDIO_DAC_H1_BUSY_LEN) - 1) << AUDIO_DAC_H1_BUSY_POS) -#define AUDIO_DAC_H1_BUSY_UMSK (~(((1U << AUDIO_DAC_H1_BUSY_LEN) - 1) << AUDIO_DAC_H1_BUSY_POS)) -#define AUDIO_DAC_H1_MUTE_DONE AUDIO_DAC_H1_MUTE_DONE -#define AUDIO_DAC_H1_MUTE_DONE_POS (15U) -#define AUDIO_DAC_H1_MUTE_DONE_LEN (1U) -#define AUDIO_DAC_H1_MUTE_DONE_MSK (((1U << AUDIO_DAC_H1_MUTE_DONE_LEN) - 1) << AUDIO_DAC_H1_MUTE_DONE_POS) -#define AUDIO_DAC_H1_MUTE_DONE_UMSK (~(((1U << AUDIO_DAC_H1_MUTE_DONE_LEN) - 1) << AUDIO_DAC_H1_MUTE_DONE_POS)) -#define AUDIO_DAC_S0_INT AUDIO_DAC_S0_INT -#define AUDIO_DAC_S0_INT_POS (16U) -#define AUDIO_DAC_S0_INT_LEN (1U) -#define AUDIO_DAC_S0_INT_MSK (((1U << AUDIO_DAC_S0_INT_LEN) - 1) << AUDIO_DAC_S0_INT_POS) -#define AUDIO_DAC_S0_INT_UMSK (~(((1U << AUDIO_DAC_S0_INT_LEN) - 1) << AUDIO_DAC_S0_INT_POS)) -#define AUDIO_DAC_S0_INT_CLR AUDIO_DAC_S0_INT_CLR -#define AUDIO_DAC_S0_INT_CLR_POS (17U) -#define AUDIO_DAC_S0_INT_CLR_LEN (1U) -#define AUDIO_DAC_S0_INT_CLR_MSK (((1U << AUDIO_DAC_S0_INT_CLR_LEN) - 1) << AUDIO_DAC_S0_INT_CLR_POS) -#define AUDIO_DAC_S0_INT_CLR_UMSK (~(((1U << AUDIO_DAC_S0_INT_CLR_LEN) - 1) << AUDIO_DAC_S0_INT_CLR_POS)) -#define AUDIO_DAC_S1_INT AUDIO_DAC_S1_INT -#define AUDIO_DAC_S1_INT_POS (18U) -#define AUDIO_DAC_S1_INT_LEN (1U) -#define AUDIO_DAC_S1_INT_MSK (((1U << AUDIO_DAC_S1_INT_LEN) - 1) << AUDIO_DAC_S1_INT_POS) -#define AUDIO_DAC_S1_INT_UMSK (~(((1U << AUDIO_DAC_S1_INT_LEN) - 1) << AUDIO_DAC_S1_INT_POS)) -#define AUDIO_DAC_S1_INT_CLR AUDIO_DAC_S1_INT_CLR -#define AUDIO_DAC_S1_INT_CLR_POS (19U) -#define AUDIO_DAC_S1_INT_CLR_LEN (1U) -#define AUDIO_DAC_S1_INT_CLR_MSK (((1U << AUDIO_DAC_S1_INT_CLR_LEN) - 1) << AUDIO_DAC_S1_INT_CLR_POS) -#define AUDIO_DAC_S1_INT_CLR_UMSK (~(((1U << AUDIO_DAC_S1_INT_CLR_LEN) - 1) << AUDIO_DAC_S1_INT_CLR_POS)) -#define AUDIO_NGT_AMUTE AUDIO_NGT_AMUTE -#define AUDIO_NGT_AMUTE_POS (20U) -#define AUDIO_NGT_AMUTE_LEN (1U) -#define AUDIO_NGT_AMUTE_MSK (((1U << AUDIO_NGT_AMUTE_LEN) - 1) << AUDIO_NGT_AMUTE_POS) -#define AUDIO_NGT_AMUTE_UMSK (~(((1U << AUDIO_NGT_AMUTE_LEN) - 1) << AUDIO_NGT_AMUTE_POS)) -#define AUDIO_NGT_DMUTE AUDIO_NGT_DMUTE -#define AUDIO_NGT_DMUTE_POS (21U) -#define AUDIO_NGT_DMUTE_LEN (1U) -#define AUDIO_NGT_DMUTE_MSK (((1U << AUDIO_NGT_DMUTE_LEN) - 1) << AUDIO_NGT_DMUTE_POS) -#define AUDIO_NGT_DMUTE_UMSK (~(((1U << AUDIO_NGT_DMUTE_LEN) - 1) << AUDIO_NGT_DMUTE_POS)) -#define AUDIO_NGT_DMUTE_DONE AUDIO_NGT_DMUTE_DONE -#define AUDIO_NGT_DMUTE_DONE_POS (22U) -#define AUDIO_NGT_DMUTE_DONE_LEN (1U) -#define AUDIO_NGT_DMUTE_DONE_MSK (((1U << AUDIO_NGT_DMUTE_DONE_LEN) - 1) << AUDIO_NGT_DMUTE_DONE_POS) -#define AUDIO_NGT_DMUTE_DONE_UMSK (~(((1U << AUDIO_NGT_DMUTE_DONE_LEN) - 1) << AUDIO_NGT_DMUTE_DONE_POS)) -#define AUDIO_ZD_AMUTE AUDIO_ZD_AMUTE -#define AUDIO_ZD_AMUTE_POS (23U) -#define AUDIO_ZD_AMUTE_LEN (1U) -#define AUDIO_ZD_AMUTE_MSK (((1U << AUDIO_ZD_AMUTE_LEN) - 1) << AUDIO_ZD_AMUTE_POS) -#define AUDIO_ZD_AMUTE_UMSK (~(((1U << AUDIO_ZD_AMUTE_LEN) - 1) << AUDIO_ZD_AMUTE_POS)) -#define AUDIO_INT_ALL AUDIO_INT_ALL -#define AUDIO_INT_ALL_POS (24U) -#define AUDIO_INT_ALL_LEN (1U) -#define AUDIO_INT_ALL_MSK (((1U << AUDIO_INT_ALL_LEN) - 1) << AUDIO_INT_ALL_POS) -#define AUDIO_INT_ALL_UMSK (~(((1U << AUDIO_INT_ALL_LEN) - 1) << AUDIO_INT_ALL_POS)) -#define AUDIO_VAD_INT AUDIO_VAD_INT -#define AUDIO_VAD_INT_POS (25U) -#define AUDIO_VAD_INT_LEN (1U) -#define AUDIO_VAD_INT_MSK (((1U << AUDIO_VAD_INT_LEN) - 1) << AUDIO_VAD_INT_POS) -#define AUDIO_VAD_INT_UMSK (~(((1U << AUDIO_VAD_INT_LEN) - 1) << AUDIO_VAD_INT_POS)) -#define AUDIO_VAD_INT_CLR AUDIO_VAD_INT_CLR -#define AUDIO_VAD_INT_CLR_POS (26U) -#define AUDIO_VAD_INT_CLR_LEN (1U) -#define AUDIO_VAD_INT_CLR_MSK (((1U << AUDIO_VAD_INT_CLR_LEN) - 1) << AUDIO_VAD_INT_CLR_POS) -#define AUDIO_VAD_INT_CLR_UMSK (~(((1U << AUDIO_VAD_INT_CLR_LEN) - 1) << AUDIO_VAD_INT_CLR_POS)) -#define AUDIO_VAD_INT_SET AUDIO_VAD_INT_SET -#define AUDIO_VAD_INT_SET_POS (27U) -#define AUDIO_VAD_INT_SET_LEN (1U) -#define AUDIO_VAD_INT_SET_MSK (((1U << AUDIO_VAD_INT_SET_LEN) - 1) << AUDIO_VAD_INT_SET_POS) -#define AUDIO_VAD_INT_SET_UMSK (~(((1U << AUDIO_VAD_INT_SET_LEN) - 1) << AUDIO_VAD_INT_SET_POS)) - -/* 0x434 : dac_s0 */ -#define AUDIO_DAC_S0_OFFSET (0x434) -#define AUDIO_DAC_S0_CTRL_RMP_RATE AUDIO_DAC_S0_CTRL_RMP_RATE -#define AUDIO_DAC_S0_CTRL_RMP_RATE_POS (2U) -#define AUDIO_DAC_S0_CTRL_RMP_RATE_LEN (4U) -#define AUDIO_DAC_S0_CTRL_RMP_RATE_MSK (((1U << AUDIO_DAC_S0_CTRL_RMP_RATE_LEN) - 1) << AUDIO_DAC_S0_CTRL_RMP_RATE_POS) -#define AUDIO_DAC_S0_CTRL_RMP_RATE_UMSK (~(((1U << AUDIO_DAC_S0_CTRL_RMP_RATE_LEN) - 1) << AUDIO_DAC_S0_CTRL_RMP_RATE_POS)) -#define AUDIO_DAC_S0_CTRL_ZCD_RATE AUDIO_DAC_S0_CTRL_ZCD_RATE -#define AUDIO_DAC_S0_CTRL_ZCD_RATE_POS (6U) -#define AUDIO_DAC_S0_CTRL_ZCD_RATE_LEN (4U) -#define AUDIO_DAC_S0_CTRL_ZCD_RATE_MSK (((1U << AUDIO_DAC_S0_CTRL_ZCD_RATE_LEN) - 1) << AUDIO_DAC_S0_CTRL_ZCD_RATE_POS) -#define AUDIO_DAC_S0_CTRL_ZCD_RATE_UMSK (~(((1U << AUDIO_DAC_S0_CTRL_ZCD_RATE_LEN) - 1) << AUDIO_DAC_S0_CTRL_ZCD_RATE_POS)) -#define AUDIO_DAC_S0_CTRL_MODE AUDIO_DAC_S0_CTRL_MODE -#define AUDIO_DAC_S0_CTRL_MODE_POS (10U) -#define AUDIO_DAC_S0_CTRL_MODE_LEN (2U) -#define AUDIO_DAC_S0_CTRL_MODE_MSK (((1U << AUDIO_DAC_S0_CTRL_MODE_LEN) - 1) << AUDIO_DAC_S0_CTRL_MODE_POS) -#define AUDIO_DAC_S0_CTRL_MODE_UMSK (~(((1U << AUDIO_DAC_S0_CTRL_MODE_LEN) - 1) << AUDIO_DAC_S0_CTRL_MODE_POS)) -#define AUDIO_DAC_S0_VOLUME_UPDATE AUDIO_DAC_S0_VOLUME_UPDATE -#define AUDIO_DAC_S0_VOLUME_UPDATE_POS (12U) -#define AUDIO_DAC_S0_VOLUME_UPDATE_LEN (1U) -#define AUDIO_DAC_S0_VOLUME_UPDATE_MSK (((1U << AUDIO_DAC_S0_VOLUME_UPDATE_LEN) - 1) << AUDIO_DAC_S0_VOLUME_UPDATE_POS) -#define AUDIO_DAC_S0_VOLUME_UPDATE_UMSK (~(((1U << AUDIO_DAC_S0_VOLUME_UPDATE_LEN) - 1) << AUDIO_DAC_S0_VOLUME_UPDATE_POS)) -#define AUDIO_DAC_S0_VOLUME AUDIO_DAC_S0_VOLUME -#define AUDIO_DAC_S0_VOLUME_POS (13U) -#define AUDIO_DAC_S0_VOLUME_LEN (9U) -#define AUDIO_DAC_S0_VOLUME_MSK (((1U << AUDIO_DAC_S0_VOLUME_LEN) - 1) << AUDIO_DAC_S0_VOLUME_POS) -#define AUDIO_DAC_S0_VOLUME_UMSK (~(((1U << AUDIO_DAC_S0_VOLUME_LEN) - 1) << AUDIO_DAC_S0_VOLUME_POS)) -#define AUDIO_DAC_S0_MUTE_RMPUP_RATE AUDIO_DAC_S0_MUTE_RMPUP_RATE -#define AUDIO_DAC_S0_MUTE_RMPUP_RATE_POS (22U) -#define AUDIO_DAC_S0_MUTE_RMPUP_RATE_LEN (4U) -#define AUDIO_DAC_S0_MUTE_RMPUP_RATE_MSK (((1U << AUDIO_DAC_S0_MUTE_RMPUP_RATE_LEN) - 1) << AUDIO_DAC_S0_MUTE_RMPUP_RATE_POS) -#define AUDIO_DAC_S0_MUTE_RMPUP_RATE_UMSK (~(((1U << AUDIO_DAC_S0_MUTE_RMPUP_RATE_LEN) - 1) << AUDIO_DAC_S0_MUTE_RMPUP_RATE_POS)) -#define AUDIO_DAC_S0_MUTE_RMPDN_RATE AUDIO_DAC_S0_MUTE_RMPDN_RATE -#define AUDIO_DAC_S0_MUTE_RMPDN_RATE_POS (26U) -#define AUDIO_DAC_S0_MUTE_RMPDN_RATE_LEN (4U) -#define AUDIO_DAC_S0_MUTE_RMPDN_RATE_MSK (((1U << AUDIO_DAC_S0_MUTE_RMPDN_RATE_LEN) - 1) << AUDIO_DAC_S0_MUTE_RMPDN_RATE_POS) -#define AUDIO_DAC_S0_MUTE_RMPDN_RATE_UMSK (~(((1U << AUDIO_DAC_S0_MUTE_RMPDN_RATE_LEN) - 1) << AUDIO_DAC_S0_MUTE_RMPDN_RATE_POS)) -#define AUDIO_DAC_S0_MUTE_SOFTMODE AUDIO_DAC_S0_MUTE_SOFTMODE -#define AUDIO_DAC_S0_MUTE_SOFTMODE_POS (30U) -#define AUDIO_DAC_S0_MUTE_SOFTMODE_LEN (1U) -#define AUDIO_DAC_S0_MUTE_SOFTMODE_MSK (((1U << AUDIO_DAC_S0_MUTE_SOFTMODE_LEN) - 1) << AUDIO_DAC_S0_MUTE_SOFTMODE_POS) -#define AUDIO_DAC_S0_MUTE_SOFTMODE_UMSK (~(((1U << AUDIO_DAC_S0_MUTE_SOFTMODE_LEN) - 1) << AUDIO_DAC_S0_MUTE_SOFTMODE_POS)) -#define AUDIO_DAC_S0_MUTE AUDIO_DAC_S0_MUTE -#define AUDIO_DAC_S0_MUTE_POS (31U) -#define AUDIO_DAC_S0_MUTE_LEN (1U) -#define AUDIO_DAC_S0_MUTE_MSK (((1U << AUDIO_DAC_S0_MUTE_LEN) - 1) << AUDIO_DAC_S0_MUTE_POS) -#define AUDIO_DAC_S0_MUTE_UMSK (~(((1U << AUDIO_DAC_S0_MUTE_LEN) - 1) << AUDIO_DAC_S0_MUTE_POS)) - -/* 0x438 : dac_s0_misc */ -#define AUDIO_DAC_S0_MISC_OFFSET (0x438) -#define AUDIO_DAC_S01_VOLUME_UPDATE AUDIO_DAC_S01_VOLUME_UPDATE -#define AUDIO_DAC_S01_VOLUME_UPDATE_POS (0U) -#define AUDIO_DAC_S01_VOLUME_UPDATE_LEN (1U) -#define AUDIO_DAC_S01_VOLUME_UPDATE_MSK (((1U << AUDIO_DAC_S01_VOLUME_UPDATE_LEN) - 1) << AUDIO_DAC_S01_VOLUME_UPDATE_POS) -#define AUDIO_DAC_S01_VOLUME_UPDATE_UMSK (~(((1U << AUDIO_DAC_S01_VOLUME_UPDATE_LEN) - 1) << AUDIO_DAC_S01_VOLUME_UPDATE_POS)) -#define AUDIO_DAC_S01_MUTE AUDIO_DAC_S01_MUTE -#define AUDIO_DAC_S01_MUTE_POS (1U) -#define AUDIO_DAC_S01_MUTE_LEN (1U) -#define AUDIO_DAC_S01_MUTE_MSK (((1U << AUDIO_DAC_S01_MUTE_LEN) - 1) << AUDIO_DAC_S01_MUTE_POS) -#define AUDIO_DAC_S01_MUTE_UMSK (~(((1U << AUDIO_DAC_S01_MUTE_LEN) - 1) << AUDIO_DAC_S01_MUTE_POS)) -#define AUDIO_DAC_S0_CTRL_ZCD_TIMEOUT AUDIO_DAC_S0_CTRL_ZCD_TIMEOUT -#define AUDIO_DAC_S0_CTRL_ZCD_TIMEOUT_POS (28U) -#define AUDIO_DAC_S0_CTRL_ZCD_TIMEOUT_LEN (4U) -#define AUDIO_DAC_S0_CTRL_ZCD_TIMEOUT_MSK (((1U << AUDIO_DAC_S0_CTRL_ZCD_TIMEOUT_LEN) - 1) << AUDIO_DAC_S0_CTRL_ZCD_TIMEOUT_POS) -#define AUDIO_DAC_S0_CTRL_ZCD_TIMEOUT_UMSK (~(((1U << AUDIO_DAC_S0_CTRL_ZCD_TIMEOUT_LEN) - 1) << AUDIO_DAC_S0_CTRL_ZCD_TIMEOUT_POS)) - -/* 0x43C : dac_s1 */ -#define AUDIO_DAC_S1_OFFSET (0x43C) -#define AUDIO_DAC_S1_CTRL_RMP_RATE AUDIO_DAC_S1_CTRL_RMP_RATE -#define AUDIO_DAC_S1_CTRL_RMP_RATE_POS (2U) -#define AUDIO_DAC_S1_CTRL_RMP_RATE_LEN (4U) -#define AUDIO_DAC_S1_CTRL_RMP_RATE_MSK (((1U << AUDIO_DAC_S1_CTRL_RMP_RATE_LEN) - 1) << AUDIO_DAC_S1_CTRL_RMP_RATE_POS) -#define AUDIO_DAC_S1_CTRL_RMP_RATE_UMSK (~(((1U << AUDIO_DAC_S1_CTRL_RMP_RATE_LEN) - 1) << AUDIO_DAC_S1_CTRL_RMP_RATE_POS)) -#define AUDIO_DAC_S1_CTRL_ZCD_RATE AUDIO_DAC_S1_CTRL_ZCD_RATE -#define AUDIO_DAC_S1_CTRL_ZCD_RATE_POS (6U) -#define AUDIO_DAC_S1_CTRL_ZCD_RATE_LEN (4U) -#define AUDIO_DAC_S1_CTRL_ZCD_RATE_MSK (((1U << AUDIO_DAC_S1_CTRL_ZCD_RATE_LEN) - 1) << AUDIO_DAC_S1_CTRL_ZCD_RATE_POS) -#define AUDIO_DAC_S1_CTRL_ZCD_RATE_UMSK (~(((1U << AUDIO_DAC_S1_CTRL_ZCD_RATE_LEN) - 1) << AUDIO_DAC_S1_CTRL_ZCD_RATE_POS)) -#define AUDIO_DAC_S1_CTRL_MODE AUDIO_DAC_S1_CTRL_MODE -#define AUDIO_DAC_S1_CTRL_MODE_POS (10U) -#define AUDIO_DAC_S1_CTRL_MODE_LEN (2U) -#define AUDIO_DAC_S1_CTRL_MODE_MSK (((1U << AUDIO_DAC_S1_CTRL_MODE_LEN) - 1) << AUDIO_DAC_S1_CTRL_MODE_POS) -#define AUDIO_DAC_S1_CTRL_MODE_UMSK (~(((1U << AUDIO_DAC_S1_CTRL_MODE_LEN) - 1) << AUDIO_DAC_S1_CTRL_MODE_POS)) -#define AUDIO_DAC_S1_VOLUME_UPDATE AUDIO_DAC_S1_VOLUME_UPDATE -#define AUDIO_DAC_S1_VOLUME_UPDATE_POS (12U) -#define AUDIO_DAC_S1_VOLUME_UPDATE_LEN (1U) -#define AUDIO_DAC_S1_VOLUME_UPDATE_MSK (((1U << AUDIO_DAC_S1_VOLUME_UPDATE_LEN) - 1) << AUDIO_DAC_S1_VOLUME_UPDATE_POS) -#define AUDIO_DAC_S1_VOLUME_UPDATE_UMSK (~(((1U << AUDIO_DAC_S1_VOLUME_UPDATE_LEN) - 1) << AUDIO_DAC_S1_VOLUME_UPDATE_POS)) -#define AUDIO_DAC_S1_VOLUME AUDIO_DAC_S1_VOLUME -#define AUDIO_DAC_S1_VOLUME_POS (13U) -#define AUDIO_DAC_S1_VOLUME_LEN (9U) -#define AUDIO_DAC_S1_VOLUME_MSK (((1U << AUDIO_DAC_S1_VOLUME_LEN) - 1) << AUDIO_DAC_S1_VOLUME_POS) -#define AUDIO_DAC_S1_VOLUME_UMSK (~(((1U << AUDIO_DAC_S1_VOLUME_LEN) - 1) << AUDIO_DAC_S1_VOLUME_POS)) -#define AUDIO_DAC_S1_MUTE_RMPUP_RATE AUDIO_DAC_S1_MUTE_RMPUP_RATE -#define AUDIO_DAC_S1_MUTE_RMPUP_RATE_POS (22U) -#define AUDIO_DAC_S1_MUTE_RMPUP_RATE_LEN (4U) -#define AUDIO_DAC_S1_MUTE_RMPUP_RATE_MSK (((1U << AUDIO_DAC_S1_MUTE_RMPUP_RATE_LEN) - 1) << AUDIO_DAC_S1_MUTE_RMPUP_RATE_POS) -#define AUDIO_DAC_S1_MUTE_RMPUP_RATE_UMSK (~(((1U << AUDIO_DAC_S1_MUTE_RMPUP_RATE_LEN) - 1) << AUDIO_DAC_S1_MUTE_RMPUP_RATE_POS)) -#define AUDIO_DAC_S1_MUTE_RMPDN_RATE AUDIO_DAC_S1_MUTE_RMPDN_RATE -#define AUDIO_DAC_S1_MUTE_RMPDN_RATE_POS (26U) -#define AUDIO_DAC_S1_MUTE_RMPDN_RATE_LEN (4U) -#define AUDIO_DAC_S1_MUTE_RMPDN_RATE_MSK (((1U << AUDIO_DAC_S1_MUTE_RMPDN_RATE_LEN) - 1) << AUDIO_DAC_S1_MUTE_RMPDN_RATE_POS) -#define AUDIO_DAC_S1_MUTE_RMPDN_RATE_UMSK (~(((1U << AUDIO_DAC_S1_MUTE_RMPDN_RATE_LEN) - 1) << AUDIO_DAC_S1_MUTE_RMPDN_RATE_POS)) -#define AUDIO_DAC_S1_MUTE_SOFTMODE AUDIO_DAC_S1_MUTE_SOFTMODE -#define AUDIO_DAC_S1_MUTE_SOFTMODE_POS (30U) -#define AUDIO_DAC_S1_MUTE_SOFTMODE_LEN (1U) -#define AUDIO_DAC_S1_MUTE_SOFTMODE_MSK (((1U << AUDIO_DAC_S1_MUTE_SOFTMODE_LEN) - 1) << AUDIO_DAC_S1_MUTE_SOFTMODE_POS) -#define AUDIO_DAC_S1_MUTE_SOFTMODE_UMSK (~(((1U << AUDIO_DAC_S1_MUTE_SOFTMODE_LEN) - 1) << AUDIO_DAC_S1_MUTE_SOFTMODE_POS)) -#define AUDIO_DAC_S1_MUTE AUDIO_DAC_S1_MUTE -#define AUDIO_DAC_S1_MUTE_POS (31U) -#define AUDIO_DAC_S1_MUTE_LEN (1U) -#define AUDIO_DAC_S1_MUTE_MSK (((1U << AUDIO_DAC_S1_MUTE_LEN) - 1) << AUDIO_DAC_S1_MUTE_POS) -#define AUDIO_DAC_S1_MUTE_UMSK (~(((1U << AUDIO_DAC_S1_MUTE_LEN) - 1) << AUDIO_DAC_S1_MUTE_POS)) - -/* 0x440 : dac_s1_misc */ -#define AUDIO_DAC_S1_MISC_OFFSET (0x440) -#define AUDIO_DAC_S1_CTRL_ZCD_TIMEOUT AUDIO_DAC_S1_CTRL_ZCD_TIMEOUT -#define AUDIO_DAC_S1_CTRL_ZCD_TIMEOUT_POS (28U) -#define AUDIO_DAC_S1_CTRL_ZCD_TIMEOUT_LEN (4U) -#define AUDIO_DAC_S1_CTRL_ZCD_TIMEOUT_MSK (((1U << AUDIO_DAC_S1_CTRL_ZCD_TIMEOUT_LEN) - 1) << AUDIO_DAC_S1_CTRL_ZCD_TIMEOUT_POS) -#define AUDIO_DAC_S1_CTRL_ZCD_TIMEOUT_UMSK (~(((1U << AUDIO_DAC_S1_CTRL_ZCD_TIMEOUT_LEN) - 1) << AUDIO_DAC_S1_CTRL_ZCD_TIMEOUT_POS)) - -/* 0x444 : dac_drc_0 */ -#define AUDIO_DAC_DRC_0_OFFSET (0x444) -#define AUDIO_DRC_NGT_DOWNSAMPLE_EN AUDIO_DRC_NGT_DOWNSAMPLE_EN -#define AUDIO_DRC_NGT_DOWNSAMPLE_EN_POS (8U) -#define AUDIO_DRC_NGT_DOWNSAMPLE_EN_LEN (1U) -#define AUDIO_DRC_NGT_DOWNSAMPLE_EN_MSK (((1U << AUDIO_DRC_NGT_DOWNSAMPLE_EN_LEN) - 1) << AUDIO_DRC_NGT_DOWNSAMPLE_EN_POS) -#define AUDIO_DRC_NGT_DOWNSAMPLE_EN_UMSK (~(((1U << AUDIO_DRC_NGT_DOWNSAMPLE_EN_LEN) - 1) << AUDIO_DRC_NGT_DOWNSAMPLE_EN_POS)) -#define AUDIO_DRC_RLS_TIME AUDIO_DRC_RLS_TIME -#define AUDIO_DRC_RLS_TIME_POS (9U) -#define AUDIO_DRC_RLS_TIME_LEN (5U) -#define AUDIO_DRC_RLS_TIME_MSK (((1U << AUDIO_DRC_RLS_TIME_LEN) - 1) << AUDIO_DRC_RLS_TIME_POS) -#define AUDIO_DRC_RLS_TIME_UMSK (~(((1U << AUDIO_DRC_RLS_TIME_LEN) - 1) << AUDIO_DRC_RLS_TIME_POS)) -#define AUDIO_DRC_ATT_TIME AUDIO_DRC_ATT_TIME -#define AUDIO_DRC_ATT_TIME_POS (14U) -#define AUDIO_DRC_ATT_TIME_LEN (5U) -#define AUDIO_DRC_ATT_TIME_MSK (((1U << AUDIO_DRC_ATT_TIME_LEN) - 1) << AUDIO_DRC_ATT_TIME_POS) -#define AUDIO_DRC_ATT_TIME_UMSK (~(((1U << AUDIO_DRC_ATT_TIME_LEN) - 1) << AUDIO_DRC_ATT_TIME_POS)) -#define AUDIO_DRC_AVG_TIME AUDIO_DRC_AVG_TIME -#define AUDIO_DRC_AVG_TIME_POS (19U) -#define AUDIO_DRC_AVG_TIME_LEN (5U) -#define AUDIO_DRC_AVG_TIME_MSK (((1U << AUDIO_DRC_AVG_TIME_LEN) - 1) << AUDIO_DRC_AVG_TIME_POS) -#define AUDIO_DRC_AVG_TIME_UMSK (~(((1U << AUDIO_DRC_AVG_TIME_LEN) - 1) << AUDIO_DRC_AVG_TIME_POS)) -#define AUDIO_DRC_AVG_EN AUDIO_DRC_AVG_EN -#define AUDIO_DRC_AVG_EN_POS (24U) -#define AUDIO_DRC_AVG_EN_LEN (1U) -#define AUDIO_DRC_AVG_EN_MSK (((1U << AUDIO_DRC_AVG_EN_LEN) - 1) << AUDIO_DRC_AVG_EN_POS) -#define AUDIO_DRC_AVG_EN_UMSK (~(((1U << AUDIO_DRC_AVG_EN_LEN) - 1) << AUDIO_DRC_AVG_EN_POS)) -#define AUDIO_DRC_AVG_SEL AUDIO_DRC_AVG_SEL -#define AUDIO_DRC_AVG_SEL_POS (25U) -#define AUDIO_DRC_AVG_SEL_LEN (2U) -#define AUDIO_DRC_AVG_SEL_MSK (((1U << AUDIO_DRC_AVG_SEL_LEN) - 1) << AUDIO_DRC_AVG_SEL_POS) -#define AUDIO_DRC_AVG_SEL_UMSK (~(((1U << AUDIO_DRC_AVG_SEL_LEN) - 1) << AUDIO_DRC_AVG_SEL_POS)) -#define AUDIO_DRC_PEAK_SEL AUDIO_DRC_PEAK_SEL -#define AUDIO_DRC_PEAK_SEL_POS (27U) -#define AUDIO_DRC_PEAK_SEL_LEN (2U) -#define AUDIO_DRC_PEAK_SEL_MSK (((1U << AUDIO_DRC_PEAK_SEL_LEN) - 1) << AUDIO_DRC_PEAK_SEL_POS) -#define AUDIO_DRC_PEAK_SEL_UMSK (~(((1U << AUDIO_DRC_PEAK_SEL_LEN) - 1) << AUDIO_DRC_PEAK_SEL_POS)) -#define AUDIO_DRC_RAW_SEL AUDIO_DRC_RAW_SEL -#define AUDIO_DRC_RAW_SEL_POS (29U) -#define AUDIO_DRC_RAW_SEL_LEN (2U) -#define AUDIO_DRC_RAW_SEL_MSK (((1U << AUDIO_DRC_RAW_SEL_LEN) - 1) << AUDIO_DRC_RAW_SEL_POS) -#define AUDIO_DRC_RAW_SEL_UMSK (~(((1U << AUDIO_DRC_RAW_SEL_LEN) - 1) << AUDIO_DRC_RAW_SEL_POS)) -#define AUDIO_DRC_EN AUDIO_DRC_EN -#define AUDIO_DRC_EN_POS (31U) -#define AUDIO_DRC_EN_LEN (1U) -#define AUDIO_DRC_EN_MSK (((1U << AUDIO_DRC_EN_LEN) - 1) << AUDIO_DRC_EN_POS) -#define AUDIO_DRC_EN_UMSK (~(((1U << AUDIO_DRC_EN_LEN) - 1) << AUDIO_DRC_EN_POS)) - -/* 0x448 : dac_drc_1 */ -#define AUDIO_DAC_DRC_1_OFFSET (0x448) -#define AUDIO_DRC_RELEASE_TIME AUDIO_DRC_RELEASE_TIME -#define AUDIO_DRC_RELEASE_TIME_POS (0U) -#define AUDIO_DRC_RELEASE_TIME_LEN (4U) -#define AUDIO_DRC_RELEASE_TIME_MSK (((1U << AUDIO_DRC_RELEASE_TIME_LEN) - 1) << AUDIO_DRC_RELEASE_TIME_POS) -#define AUDIO_DRC_RELEASE_TIME_UMSK (~(((1U << AUDIO_DRC_RELEASE_TIME_LEN) - 1) << AUDIO_DRC_RELEASE_TIME_POS)) -#define AUDIO_DRC_ATTACK_TIME AUDIO_DRC_ATTACK_TIME -#define AUDIO_DRC_ATTACK_TIME_POS (4U) -#define AUDIO_DRC_ATTACK_TIME_LEN (4U) -#define AUDIO_DRC_ATTACK_TIME_MSK (((1U << AUDIO_DRC_ATTACK_TIME_LEN) - 1) << AUDIO_DRC_ATTACK_TIME_POS) -#define AUDIO_DRC_ATTACK_TIME_UMSK (~(((1U << AUDIO_DRC_ATTACK_TIME_LEN) - 1) << AUDIO_DRC_ATTACK_TIME_POS)) -#define AUDIO_DRC_MAKEUP_GAIN AUDIO_DRC_MAKEUP_GAIN -#define AUDIO_DRC_MAKEUP_GAIN_POS (8U) -#define AUDIO_DRC_MAKEUP_GAIN_LEN (4U) -#define AUDIO_DRC_MAKEUP_GAIN_MSK (((1U << AUDIO_DRC_MAKEUP_GAIN_LEN) - 1) << AUDIO_DRC_MAKEUP_GAIN_POS) -#define AUDIO_DRC_MAKEUP_GAIN_UMSK (~(((1U << AUDIO_DRC_MAKEUP_GAIN_LEN) - 1) << AUDIO_DRC_MAKEUP_GAIN_POS)) -#define AUDIO_DRC_SLOPE_MODE_E AUDIO_DRC_SLOPE_MODE_E -#define AUDIO_DRC_SLOPE_MODE_E_POS (12U) -#define AUDIO_DRC_SLOPE_MODE_E_LEN (2U) -#define AUDIO_DRC_SLOPE_MODE_E_MSK (((1U << AUDIO_DRC_SLOPE_MODE_E_LEN) - 1) << AUDIO_DRC_SLOPE_MODE_E_POS) -#define AUDIO_DRC_SLOPE_MODE_E_UMSK (~(((1U << AUDIO_DRC_SLOPE_MODE_E_LEN) - 1) << AUDIO_DRC_SLOPE_MODE_E_POS)) -#define AUDIO_DRC_SLOPE_MODE_C AUDIO_DRC_SLOPE_MODE_C -#define AUDIO_DRC_SLOPE_MODE_C_POS (14U) -#define AUDIO_DRC_SLOPE_MODE_C_LEN (2U) -#define AUDIO_DRC_SLOPE_MODE_C_MSK (((1U << AUDIO_DRC_SLOPE_MODE_C_LEN) - 1) << AUDIO_DRC_SLOPE_MODE_C_POS) -#define AUDIO_DRC_SLOPE_MODE_C_UMSK (~(((1U << AUDIO_DRC_SLOPE_MODE_C_LEN) - 1) << AUDIO_DRC_SLOPE_MODE_C_POS)) -#define AUDIO_DRC_THRESHOLD_E AUDIO_DRC_THRESHOLD_E -#define AUDIO_DRC_THRESHOLD_E_POS (16U) -#define AUDIO_DRC_THRESHOLD_E_LEN (6U) -#define AUDIO_DRC_THRESHOLD_E_MSK (((1U << AUDIO_DRC_THRESHOLD_E_LEN) - 1) << AUDIO_DRC_THRESHOLD_E_POS) -#define AUDIO_DRC_THRESHOLD_E_UMSK (~(((1U << AUDIO_DRC_THRESHOLD_E_LEN) - 1) << AUDIO_DRC_THRESHOLD_E_POS)) -#define AUDIO_DRC_THRESHOLD_C AUDIO_DRC_THRESHOLD_C -#define AUDIO_DRC_THRESHOLD_C_POS (22U) -#define AUDIO_DRC_THRESHOLD_C_LEN (5U) -#define AUDIO_DRC_THRESHOLD_C_MSK (((1U << AUDIO_DRC_THRESHOLD_C_LEN) - 1) << AUDIO_DRC_THRESHOLD_C_POS) -#define AUDIO_DRC_THRESHOLD_C_UMSK (~(((1U << AUDIO_DRC_THRESHOLD_C_LEN) - 1) << AUDIO_DRC_THRESHOLD_C_POS)) -#define AUDIO_DRC_THRESHOLD_L AUDIO_DRC_THRESHOLD_L -#define AUDIO_DRC_THRESHOLD_L_POS (27U) -#define AUDIO_DRC_THRESHOLD_L_LEN (5U) -#define AUDIO_DRC_THRESHOLD_L_MSK (((1U << AUDIO_DRC_THRESHOLD_L_LEN) - 1) << AUDIO_DRC_THRESHOLD_L_POS) -#define AUDIO_DRC_THRESHOLD_L_UMSK (~(((1U << AUDIO_DRC_THRESHOLD_L_LEN) - 1) << AUDIO_DRC_THRESHOLD_L_POS)) - -/* 0x44C : dac_ngt_0 */ -#define AUDIO_DAC_NGT_0_OFFSET (0x44C) -#define AUDIO_NGT_AMUTE_ON AUDIO_NGT_AMUTE_ON -#define AUDIO_NGT_AMUTE_ON_POS (2U) -#define AUDIO_NGT_AMUTE_ON_LEN (1U) -#define AUDIO_NGT_AMUTE_ON_MSK (((1U << AUDIO_NGT_AMUTE_ON_LEN) - 1) << AUDIO_NGT_AMUTE_ON_POS) -#define AUDIO_NGT_AMUTE_ON_UMSK (~(((1U << AUDIO_NGT_AMUTE_ON_LEN) - 1) << AUDIO_NGT_AMUTE_ON_POS)) -#define AUDIO_NGT_DMUTE_ON AUDIO_NGT_DMUTE_ON -#define AUDIO_NGT_DMUTE_ON_POS (3U) -#define AUDIO_NGT_DMUTE_ON_LEN (1U) -#define AUDIO_NGT_DMUTE_ON_MSK (((1U << AUDIO_NGT_DMUTE_ON_LEN) - 1) << AUDIO_NGT_DMUTE_ON_POS) -#define AUDIO_NGT_DMUTE_ON_UMSK (~(((1U << AUDIO_NGT_DMUTE_ON_LEN) - 1) << AUDIO_NGT_DMUTE_ON_POS)) -#define AUDIO_NGT_SIGNAL_HOLD_TIME_K AUDIO_NGT_SIGNAL_HOLD_TIME_K -#define AUDIO_NGT_SIGNAL_HOLD_TIME_K_POS (4U) -#define AUDIO_NGT_SIGNAL_HOLD_TIME_K_LEN (4U) -#define AUDIO_NGT_SIGNAL_HOLD_TIME_K_MSK (((1U << AUDIO_NGT_SIGNAL_HOLD_TIME_K_LEN) - 1) << AUDIO_NGT_SIGNAL_HOLD_TIME_K_POS) -#define AUDIO_NGT_SIGNAL_HOLD_TIME_K_UMSK (~(((1U << AUDIO_NGT_SIGNAL_HOLD_TIME_K_LEN) - 1) << AUDIO_NGT_SIGNAL_HOLD_TIME_K_POS)) -#define AUDIO_NGT_SIGNAL_HOLD_EN AUDIO_NGT_SIGNAL_HOLD_EN -#define AUDIO_NGT_SIGNAL_HOLD_EN_POS (8U) -#define AUDIO_NGT_SIGNAL_HOLD_EN_LEN (1U) -#define AUDIO_NGT_SIGNAL_HOLD_EN_MSK (((1U << AUDIO_NGT_SIGNAL_HOLD_EN_LEN) - 1) << AUDIO_NGT_SIGNAL_HOLD_EN_POS) -#define AUDIO_NGT_SIGNAL_HOLD_EN_UMSK (~(((1U << AUDIO_NGT_SIGNAL_HOLD_EN_LEN) - 1) << AUDIO_NGT_SIGNAL_HOLD_EN_POS)) -#define AUDIO_NGT_NOISE_HOLD_TIME_K AUDIO_NGT_NOISE_HOLD_TIME_K -#define AUDIO_NGT_NOISE_HOLD_TIME_K_POS (9U) -#define AUDIO_NGT_NOISE_HOLD_TIME_K_LEN (4U) -#define AUDIO_NGT_NOISE_HOLD_TIME_K_MSK (((1U << AUDIO_NGT_NOISE_HOLD_TIME_K_LEN) - 1) << AUDIO_NGT_NOISE_HOLD_TIME_K_POS) -#define AUDIO_NGT_NOISE_HOLD_TIME_K_UMSK (~(((1U << AUDIO_NGT_NOISE_HOLD_TIME_K_LEN) - 1) << AUDIO_NGT_NOISE_HOLD_TIME_K_POS)) -#define AUDIO_NGT_NOISE_HOLD_EN AUDIO_NGT_NOISE_HOLD_EN -#define AUDIO_NGT_NOISE_HOLD_EN_POS (13U) -#define AUDIO_NGT_NOISE_HOLD_EN_LEN (1U) -#define AUDIO_NGT_NOISE_HOLD_EN_MSK (((1U << AUDIO_NGT_NOISE_HOLD_EN_LEN) - 1) << AUDIO_NGT_NOISE_HOLD_EN_POS) -#define AUDIO_NGT_NOISE_HOLD_EN_UMSK (~(((1U << AUDIO_NGT_NOISE_HOLD_EN_LEN) - 1) << AUDIO_NGT_NOISE_HOLD_EN_POS)) -#define AUDIO_NGT_HYSTERESIS AUDIO_NGT_HYSTERESIS -#define AUDIO_NGT_HYSTERESIS_POS (14U) -#define AUDIO_NGT_HYSTERESIS_LEN (2U) -#define AUDIO_NGT_HYSTERESIS_MSK (((1U << AUDIO_NGT_HYSTERESIS_LEN) - 1) << AUDIO_NGT_HYSTERESIS_POS) -#define AUDIO_NGT_HYSTERESIS_UMSK (~(((1U << AUDIO_NGT_HYSTERESIS_LEN) - 1) << AUDIO_NGT_HYSTERESIS_POS)) -#define AUDIO_NGT_THRESHOLD AUDIO_NGT_THRESHOLD -#define AUDIO_NGT_THRESHOLD_POS (16U) -#define AUDIO_NGT_THRESHOLD_LEN (8U) -#define AUDIO_NGT_THRESHOLD_MSK (((1U << AUDIO_NGT_THRESHOLD_LEN) - 1) << AUDIO_NGT_THRESHOLD_POS) -#define AUDIO_NGT_THRESHOLD_UMSK (~(((1U << AUDIO_NGT_THRESHOLD_LEN) - 1) << AUDIO_NGT_THRESHOLD_POS)) -#define AUDIO_NGT_AVG_TIME AUDIO_NGT_AVG_TIME -#define AUDIO_NGT_AVG_TIME_POS (24U) -#define AUDIO_NGT_AVG_TIME_LEN (5U) -#define AUDIO_NGT_AVG_TIME_MSK (((1U << AUDIO_NGT_AVG_TIME_LEN) - 1) << AUDIO_NGT_AVG_TIME_POS) -#define AUDIO_NGT_AVG_TIME_UMSK (~(((1U << AUDIO_NGT_AVG_TIME_LEN) - 1) << AUDIO_NGT_AVG_TIME_POS)) -#define AUDIO_NGT_SRC_SEL AUDIO_NGT_SRC_SEL -#define AUDIO_NGT_SRC_SEL_POS (29U) -#define AUDIO_NGT_SRC_SEL_LEN (2U) -#define AUDIO_NGT_SRC_SEL_MSK (((1U << AUDIO_NGT_SRC_SEL_LEN) - 1) << AUDIO_NGT_SRC_SEL_POS) -#define AUDIO_NGT_SRC_SEL_UMSK (~(((1U << AUDIO_NGT_SRC_SEL_LEN) - 1) << AUDIO_NGT_SRC_SEL_POS)) -#define AUDIO_NGT_EN AUDIO_NGT_EN -#define AUDIO_NGT_EN_POS (31U) -#define AUDIO_NGT_EN_LEN (1U) -#define AUDIO_NGT_EN_MSK (((1U << AUDIO_NGT_EN_LEN) - 1) << AUDIO_NGT_EN_POS) -#define AUDIO_NGT_EN_UMSK (~(((1U << AUDIO_NGT_EN_LEN) - 1) << AUDIO_NGT_EN_POS)) - -/* 0x450 : dac_zd_0 */ -#define AUDIO_DAC_ZD_0_OFFSET (0x450) -#define AUDIO_ZD_TIME AUDIO_ZD_TIME -#define AUDIO_ZD_TIME_POS (0U) -#define AUDIO_ZD_TIME_LEN (15U) -#define AUDIO_ZD_TIME_MSK (((1U << AUDIO_ZD_TIME_LEN) - 1) << AUDIO_ZD_TIME_POS) -#define AUDIO_ZD_TIME_UMSK (~(((1U << AUDIO_ZD_TIME_LEN) - 1) << AUDIO_ZD_TIME_POS)) -#define AUDIO_ZD_EN AUDIO_ZD_EN -#define AUDIO_ZD_EN_POS (16U) -#define AUDIO_ZD_EN_LEN (2U) -#define AUDIO_ZD_EN_MSK (((1U << AUDIO_ZD_EN_LEN) - 1) << AUDIO_ZD_EN_POS) -#define AUDIO_ZD_EN_UMSK (~(((1U << AUDIO_ZD_EN_LEN) - 1) << AUDIO_ZD_EN_POS)) -#define AUDIO_DAC_MUTE_HW_CTRL AUDIO_DAC_MUTE_HW_CTRL -#define AUDIO_DAC_MUTE_HW_CTRL_POS (30U) -#define AUDIO_DAC_MUTE_HW_CTRL_LEN (1U) -#define AUDIO_DAC_MUTE_HW_CTRL_MSK (((1U << AUDIO_DAC_MUTE_HW_CTRL_LEN) - 1) << AUDIO_DAC_MUTE_HW_CTRL_POS) -#define AUDIO_DAC_MUTE_HW_CTRL_UMSK (~(((1U << AUDIO_DAC_MUTE_HW_CTRL_LEN) - 1) << AUDIO_DAC_MUTE_HW_CTRL_POS)) -#define AUDIO_DAC_MUTE AUDIO_DAC_MUTE -#define AUDIO_DAC_MUTE_POS (31U) -#define AUDIO_DAC_MUTE_LEN (1U) -#define AUDIO_DAC_MUTE_MSK (((1U << AUDIO_DAC_MUTE_LEN) - 1) << AUDIO_DAC_MUTE_POS) -#define AUDIO_DAC_MUTE_UMSK (~(((1U << AUDIO_DAC_MUTE_LEN) - 1) << AUDIO_DAC_MUTE_POS)) - -/* 0x600 : vad_ctrl_0 */ -#define AUDIO_VAD_CTRL_0_OFFSET (0x600) -#define AUDIO_VAD_NTH_MINLMT_EN AUDIO_VAD_NTH_MINLMT_EN -#define AUDIO_VAD_NTH_MINLMT_EN_POS (0U) -#define AUDIO_VAD_NTH_MINLMT_EN_LEN (1U) -#define AUDIO_VAD_NTH_MINLMT_EN_MSK (((1U << AUDIO_VAD_NTH_MINLMT_EN_LEN) - 1) << AUDIO_VAD_NTH_MINLMT_EN_POS) -#define AUDIO_VAD_NTH_MINLMT_EN_UMSK (~(((1U << AUDIO_VAD_NTH_MINLMT_EN_LEN) - 1) << AUDIO_VAD_NTH_MINLMT_EN_POS)) -#define AUDIO_VAD_NTH_MAXLMT_EN AUDIO_VAD_NTH_MAXLMT_EN -#define AUDIO_VAD_NTH_MAXLMT_EN_POS (1U) -#define AUDIO_VAD_NTH_MAXLMT_EN_LEN (1U) -#define AUDIO_VAD_NTH_MAXLMT_EN_MSK (((1U << AUDIO_VAD_NTH_MAXLMT_EN_LEN) - 1) << AUDIO_VAD_NTH_MAXLMT_EN_POS) -#define AUDIO_VAD_NTH_MAXLMT_EN_UMSK (~(((1U << AUDIO_VAD_NTH_MAXLMT_EN_LEN) - 1) << AUDIO_VAD_NTH_MAXLMT_EN_POS)) -#define AUDIO_VAD_NBUF_MONIT_EN AUDIO_VAD_NBUF_MONIT_EN -#define AUDIO_VAD_NBUF_MONIT_EN_POS (2U) -#define AUDIO_VAD_NBUF_MONIT_EN_LEN (1U) -#define AUDIO_VAD_NBUF_MONIT_EN_MSK (((1U << AUDIO_VAD_NBUF_MONIT_EN_LEN) - 1) << AUDIO_VAD_NBUF_MONIT_EN_POS) -#define AUDIO_VAD_NBUF_MONIT_EN_UMSK (~(((1U << AUDIO_VAD_NBUF_MONIT_EN_LEN) - 1) << AUDIO_VAD_NBUF_MONIT_EN_POS)) -#define AUDIO_VAD_NBUF_MONIT_CTRL AUDIO_VAD_NBUF_MONIT_CTRL -#define AUDIO_VAD_NBUF_MONIT_CTRL_POS (4U) -#define AUDIO_VAD_NBUF_MONIT_CTRL_LEN (2U) -#define AUDIO_VAD_NBUF_MONIT_CTRL_MSK (((1U << AUDIO_VAD_NBUF_MONIT_CTRL_LEN) - 1) << AUDIO_VAD_NBUF_MONIT_CTRL_POS) -#define AUDIO_VAD_NBUF_MONIT_CTRL_UMSK (~(((1U << AUDIO_VAD_NBUF_MONIT_CTRL_LEN) - 1) << AUDIO_VAD_NBUF_MONIT_CTRL_POS)) -#define AUDIO_VAD_NBUF_LEN_CTRL AUDIO_VAD_NBUF_LEN_CTRL -#define AUDIO_VAD_NBUF_LEN_CTRL_POS (8U) -#define AUDIO_VAD_NBUF_LEN_CTRL_LEN (3U) -#define AUDIO_VAD_NBUF_LEN_CTRL_MSK (((1U << AUDIO_VAD_NBUF_LEN_CTRL_LEN) - 1) << AUDIO_VAD_NBUF_LEN_CTRL_POS) -#define AUDIO_VAD_NBUF_LEN_CTRL_UMSK (~(((1U << AUDIO_VAD_NBUF_LEN_CTRL_LEN) - 1) << AUDIO_VAD_NBUF_LEN_CTRL_POS)) -#define AUDIO_VAD_OUT_SEL AUDIO_VAD_OUT_SEL -#define AUDIO_VAD_OUT_SEL_POS (12U) -#define AUDIO_VAD_OUT_SEL_LEN (2U) -#define AUDIO_VAD_OUT_SEL_MSK (((1U << AUDIO_VAD_OUT_SEL_LEN) - 1) << AUDIO_VAD_OUT_SEL_POS) -#define AUDIO_VAD_OUT_SEL_UMSK (~(((1U << AUDIO_VAD_OUT_SEL_LEN) - 1) << AUDIO_VAD_OUT_SEL_POS)) -#define AUDIO_VAD_FRAMETIME_CTRL AUDIO_VAD_FRAMETIME_CTRL -#define AUDIO_VAD_FRAMETIME_CTRL_POS (14U) -#define AUDIO_VAD_FRAMETIME_CTRL_LEN (2U) -#define AUDIO_VAD_FRAMETIME_CTRL_MSK (((1U << AUDIO_VAD_FRAMETIME_CTRL_LEN) - 1) << AUDIO_VAD_FRAMETIME_CTRL_POS) -#define AUDIO_VAD_FRAMETIME_CTRL_UMSK (~(((1U << AUDIO_VAD_FRAMETIME_CTRL_LEN) - 1) << AUDIO_VAD_FRAMETIME_CTRL_POS)) -#define AUDIO_VAD_FRAMESHIFT_CTRL AUDIO_VAD_FRAMESHIFT_CTRL -#define AUDIO_VAD_FRAMESHIFT_CTRL_POS (16U) -#define AUDIO_VAD_FRAMESHIFT_CTRL_LEN (3U) -#define AUDIO_VAD_FRAMESHIFT_CTRL_MSK (((1U << AUDIO_VAD_FRAMESHIFT_CTRL_LEN) - 1) << AUDIO_VAD_FRAMESHIFT_CTRL_POS) -#define AUDIO_VAD_FRAMESHIFT_CTRL_UMSK (~(((1U << AUDIO_VAD_FRAMESHIFT_CTRL_LEN) - 1) << AUDIO_VAD_FRAMESHIFT_CTRL_POS)) -#define AUDIO_VAD_OUT AUDIO_VAD_OUT -#define AUDIO_VAD_OUT_POS (19U) -#define AUDIO_VAD_OUT_LEN (1U) -#define AUDIO_VAD_OUT_MSK (((1U << AUDIO_VAD_OUT_LEN) - 1) << AUDIO_VAD_OUT_POS) -#define AUDIO_VAD_OUT_UMSK (~(((1U << AUDIO_VAD_OUT_LEN) - 1) << AUDIO_VAD_OUT_POS)) -#define AUDIO_VAD_IN_SEL AUDIO_VAD_IN_SEL -#define AUDIO_VAD_IN_SEL_POS (20U) -#define AUDIO_VAD_IN_SEL_LEN (3U) -#define AUDIO_VAD_IN_SEL_MSK (((1U << AUDIO_VAD_IN_SEL_LEN) - 1) << AUDIO_VAD_IN_SEL_POS) -#define AUDIO_VAD_IN_SEL_UMSK (~(((1U << AUDIO_VAD_IN_SEL_LEN) - 1) << AUDIO_VAD_IN_SEL_POS)) -#define AUDIO_VAD_EN AUDIO_VAD_EN -#define AUDIO_VAD_EN_POS (23U) -#define AUDIO_VAD_EN_LEN (1U) -#define AUDIO_VAD_EN_MSK (((1U << AUDIO_VAD_EN_LEN) - 1) << AUDIO_VAD_EN_POS) -#define AUDIO_VAD_EN_UMSK (~(((1U << AUDIO_VAD_EN_LEN) - 1) << AUDIO_VAD_EN_POS)) - -/* 0x604 : vad_ctrl_1 */ -#define AUDIO_VAD_CTRL_1_OFFSET (0x604) -#define AUDIO_VAD_NTH_SCALE AUDIO_VAD_NTH_SCALE -#define AUDIO_VAD_NTH_SCALE_POS (0U) -#define AUDIO_VAD_NTH_SCALE_LEN (8U) -#define AUDIO_VAD_NTH_SCALE_MSK (((1U << AUDIO_VAD_NTH_SCALE_LEN) - 1) << AUDIO_VAD_NTH_SCALE_POS) -#define AUDIO_VAD_NTH_SCALE_UMSK (~(((1U << AUDIO_VAD_NTH_SCALE_LEN) - 1) << AUDIO_VAD_NTH_SCALE_POS)) -#define AUDIO_VAD_NTH_BIAS AUDIO_VAD_NTH_BIAS -#define AUDIO_VAD_NTH_BIAS_POS (8U) -#define AUDIO_VAD_NTH_BIAS_LEN (16U) -#define AUDIO_VAD_NTH_BIAS_MSK (((1U << AUDIO_VAD_NTH_BIAS_LEN) - 1) << AUDIO_VAD_NTH_BIAS_POS) -#define AUDIO_VAD_NTH_BIAS_UMSK (~(((1U << AUDIO_VAD_NTH_BIAS_LEN) - 1) << AUDIO_VAD_NTH_BIAS_POS)) -#define AUDIO_VAD_NBUF_DISCARD AUDIO_VAD_NBUF_DISCARD -#define AUDIO_VAD_NBUF_DISCARD_POS (24U) -#define AUDIO_VAD_NBUF_DISCARD_LEN (8U) -#define AUDIO_VAD_NBUF_DISCARD_MSK (((1U << AUDIO_VAD_NBUF_DISCARD_LEN) - 1) << AUDIO_VAD_NBUF_DISCARD_POS) -#define AUDIO_VAD_NBUF_DISCARD_UMSK (~(((1U << AUDIO_VAD_NBUF_DISCARD_LEN) - 1) << AUDIO_VAD_NBUF_DISCARD_POS)) - -/* 0x608 : vad_ctrl_2 */ -#define AUDIO_VAD_CTRL_2_OFFSET (0x608) -#define AUDIO_VAD_NTH_MINLMT AUDIO_VAD_NTH_MINLMT -#define AUDIO_VAD_NTH_MINLMT_POS (0U) -#define AUDIO_VAD_NTH_MINLMT_LEN (16U) -#define AUDIO_VAD_NTH_MINLMT_MSK (((1U << AUDIO_VAD_NTH_MINLMT_LEN) - 1) << AUDIO_VAD_NTH_MINLMT_POS) -#define AUDIO_VAD_NTH_MINLMT_UMSK (~(((1U << AUDIO_VAD_NTH_MINLMT_LEN) - 1) << AUDIO_VAD_NTH_MINLMT_POS)) -#define AUDIO_VAD_NTH_MAXLMT AUDIO_VAD_NTH_MAXLMT -#define AUDIO_VAD_NTH_MAXLMT_POS (16U) -#define AUDIO_VAD_NTH_MAXLMT_LEN (16U) -#define AUDIO_VAD_NTH_MAXLMT_MSK (((1U << AUDIO_VAD_NTH_MAXLMT_LEN) - 1) << AUDIO_VAD_NTH_MAXLMT_POS) -#define AUDIO_VAD_NTH_MAXLMT_UMSK (~(((1U << AUDIO_VAD_NTH_MAXLMT_LEN) - 1) << AUDIO_VAD_NTH_MAXLMT_POS)) - -/* 0x60C : vad_ctrl_3 */ -#define AUDIO_VAD_CTRL_3_OFFSET (0x60C) -#define AUDIO_VAD_SMOOTH_FALL AUDIO_VAD_SMOOTH_FALL -#define AUDIO_VAD_SMOOTH_FALL_POS (0U) -#define AUDIO_VAD_SMOOTH_FALL_LEN (8U) -#define AUDIO_VAD_SMOOTH_FALL_MSK (((1U << AUDIO_VAD_SMOOTH_FALL_LEN) - 1) << AUDIO_VAD_SMOOTH_FALL_POS) -#define AUDIO_VAD_SMOOTH_FALL_UMSK (~(((1U << AUDIO_VAD_SMOOTH_FALL_LEN) - 1) << AUDIO_VAD_SMOOTH_FALL_POS)) -#define AUDIO_VAD_SMOOTH_RISE AUDIO_VAD_SMOOTH_RISE -#define AUDIO_VAD_SMOOTH_RISE_POS (8U) -#define AUDIO_VAD_SMOOTH_RISE_LEN (8U) -#define AUDIO_VAD_SMOOTH_RISE_MSK (((1U << AUDIO_VAD_SMOOTH_RISE_LEN) - 1) << AUDIO_VAD_SMOOTH_RISE_POS) -#define AUDIO_VAD_SMOOTH_RISE_UMSK (~(((1U << AUDIO_VAD_SMOOTH_RISE_LEN) - 1) << AUDIO_VAD_SMOOTH_RISE_POS)) - -/* 0x610 : vad_ctrl_4 */ -#define AUDIO_VAD_CTRL_4_OFFSET (0x610) -#define AUDIO_VAD_EK AUDIO_VAD_EK -#define AUDIO_VAD_EK_POS (0U) -#define AUDIO_VAD_EK_LEN (24U) -#define AUDIO_VAD_EK_MSK (((1U << AUDIO_VAD_EK_LEN) - 1) << AUDIO_VAD_EK_POS) -#define AUDIO_VAD_EK_UMSK (~(((1U << AUDIO_VAD_EK_LEN) - 1) << AUDIO_VAD_EK_POS)) - -/* 0x614 : vad_ctrl_5 */ -#define AUDIO_VAD_CTRL_5_OFFSET (0x614) -#define AUDIO_VAD_NOISE_TH AUDIO_VAD_NOISE_TH -#define AUDIO_VAD_NOISE_TH_POS (0U) -#define AUDIO_VAD_NOISE_TH_LEN (24U) -#define AUDIO_VAD_NOISE_TH_MSK (((1U << AUDIO_VAD_NOISE_TH_LEN) - 1) << AUDIO_VAD_NOISE_TH_POS) -#define AUDIO_VAD_NOISE_TH_UMSK (~(((1U << AUDIO_VAD_NOISE_TH_LEN) - 1) << AUDIO_VAD_NOISE_TH_POS)) - -/* 0x700 : codec_power1 */ -#define AUDIO_CODEC_POWER1_OFFSET (0x700) -#define AUDIO_MICBIAS_PU AUDIO_MICBIAS_PU -#define AUDIO_MICBIAS_PU_POS (0U) -#define AUDIO_MICBIAS_PU_LEN (1U) -#define AUDIO_MICBIAS_PU_MSK (((1U << AUDIO_MICBIAS_PU_LEN) - 1) << AUDIO_MICBIAS_PU_POS) -#define AUDIO_MICBIAS_PU_UMSK (~(((1U << AUDIO_MICBIAS_PU_LEN) - 1) << AUDIO_MICBIAS_PU_POS)) -#define AUDIO_MICBIAS_CHOP_EN AUDIO_MICBIAS_CHOP_EN -#define AUDIO_MICBIAS_CHOP_EN_POS (1U) -#define AUDIO_MICBIAS_CHOP_EN_LEN (1U) -#define AUDIO_MICBIAS_CHOP_EN_MSK (((1U << AUDIO_MICBIAS_CHOP_EN_LEN) - 1) << AUDIO_MICBIAS_CHOP_EN_POS) -#define AUDIO_MICBIAS_CHOP_EN_UMSK (~(((1U << AUDIO_MICBIAS_CHOP_EN_LEN) - 1) << AUDIO_MICBIAS_CHOP_EN_POS)) -#define AUDIO_MICBIAS_CLK_CHOP_SEL AUDIO_MICBIAS_CLK_CHOP_SEL -#define AUDIO_MICBIAS_CLK_CHOP_SEL_POS (2U) -#define AUDIO_MICBIAS_CLK_CHOP_SEL_LEN (2U) -#define AUDIO_MICBIAS_CLK_CHOP_SEL_MSK (((1U << AUDIO_MICBIAS_CLK_CHOP_SEL_LEN) - 1) << AUDIO_MICBIAS_CLK_CHOP_SEL_POS) -#define AUDIO_MICBIAS_CLK_CHOP_SEL_UMSK (~(((1U << AUDIO_MICBIAS_CLK_CHOP_SEL_LEN) - 1) << AUDIO_MICBIAS_CLK_CHOP_SEL_POS)) -#define AUDIO_MICBIAS_VSEL AUDIO_MICBIAS_VSEL -#define AUDIO_MICBIAS_VSEL_POS (4U) -#define AUDIO_MICBIAS_VSEL_LEN (2U) -#define AUDIO_MICBIAS_VSEL_MSK (((1U << AUDIO_MICBIAS_VSEL_LEN) - 1) << AUDIO_MICBIAS_VSEL_POS) -#define AUDIO_MICBIAS_VSEL_UMSK (~(((1U << AUDIO_MICBIAS_VSEL_LEN) - 1) << AUDIO_MICBIAS_VSEL_POS)) -#define AUDIO_PADC_IBIAS_SOURCE AUDIO_PADC_IBIAS_SOURCE -#define AUDIO_PADC_IBIAS_SOURCE_POS (6U) -#define AUDIO_PADC_IBIAS_SOURCE_LEN (1U) -#define AUDIO_PADC_IBIAS_SOURCE_MSK (((1U << AUDIO_PADC_IBIAS_SOURCE_LEN) - 1) << AUDIO_PADC_IBIAS_SOURCE_POS) -#define AUDIO_PADC_IBIAS_SOURCE_UMSK (~(((1U << AUDIO_PADC_IBIAS_SOURCE_LEN) - 1) << AUDIO_PADC_IBIAS_SOURCE_POS)) -#define AUDIO_PADC_POWER_TEN AUDIO_PADC_POWER_TEN -#define AUDIO_PADC_POWER_TEN_POS (7U) -#define AUDIO_PADC_POWER_TEN_LEN (1U) -#define AUDIO_PADC_POWER_TEN_MSK (((1U << AUDIO_PADC_POWER_TEN_LEN) - 1) << AUDIO_PADC_POWER_TEN_POS) -#define AUDIO_PADC_POWER_TEN_UMSK (~(((1U << AUDIO_PADC_POWER_TEN_LEN) - 1) << AUDIO_PADC_POWER_TEN_POS)) -#define AUDIO_PADC_POWER_TMUX AUDIO_PADC_POWER_TMUX -#define AUDIO_PADC_POWER_TMUX_POS (8U) -#define AUDIO_PADC_POWER_TMUX_LEN (3U) -#define AUDIO_PADC_POWER_TMUX_MSK (((1U << AUDIO_PADC_POWER_TMUX_LEN) - 1) << AUDIO_PADC_POWER_TMUX_POS) -#define AUDIO_PADC_POWER_TMUX_UMSK (~(((1U << AUDIO_PADC_POWER_TMUX_LEN) - 1) << AUDIO_PADC_POWER_TMUX_POS)) -#define AUDIO_CODEC_VRDA_EN AUDIO_CODEC_VRDA_EN -#define AUDIO_CODEC_VRDA_EN_POS (12U) -#define AUDIO_CODEC_VRDA_EN_LEN (1U) -#define AUDIO_CODEC_VRDA_EN_MSK (((1U << AUDIO_CODEC_VRDA_EN_LEN) - 1) << AUDIO_CODEC_VRDA_EN_POS) -#define AUDIO_CODEC_VRDA_EN_UMSK (~(((1U << AUDIO_CODEC_VRDA_EN_LEN) - 1) << AUDIO_CODEC_VRDA_EN_POS)) -#define AUDIO_CODEC_ICTRL_VCM AUDIO_CODEC_ICTRL_VCM -#define AUDIO_CODEC_ICTRL_VCM_POS (13U) -#define AUDIO_CODEC_ICTRL_VCM_LEN (2U) -#define AUDIO_CODEC_ICTRL_VCM_MSK (((1U << AUDIO_CODEC_ICTRL_VCM_LEN) - 1) << AUDIO_CODEC_ICTRL_VCM_POS) -#define AUDIO_CODEC_ICTRL_VCM_UMSK (~(((1U << AUDIO_CODEC_ICTRL_VCM_LEN) - 1) << AUDIO_CODEC_ICTRL_VCM_POS)) -#define AUDIO_CODEC_IBIAS_CTRL AUDIO_CODEC_IBIAS_CTRL -#define AUDIO_CODEC_IBIAS_CTRL_POS (16U) -#define AUDIO_CODEC_IBIAS_CTRL_LEN (3U) -#define AUDIO_CODEC_IBIAS_CTRL_MSK (((1U << AUDIO_CODEC_IBIAS_CTRL_LEN) - 1) << AUDIO_CODEC_IBIAS_CTRL_POS) -#define AUDIO_CODEC_IBIAS_CTRL_UMSK (~(((1U << AUDIO_CODEC_IBIAS_CTRL_LEN) - 1) << AUDIO_CODEC_IBIAS_CTRL_POS)) - -/* 0x704 : codec_power2 */ -#define AUDIO_CODEC_POWER2_OFFSET (0x704) -#define AUDIO_HPBG_CHOP_SEL AUDIO_HPBG_CHOP_SEL -#define AUDIO_HPBG_CHOP_SEL_POS (0U) -#define AUDIO_HPBG_CHOP_SEL_LEN (3U) -#define AUDIO_HPBG_CHOP_SEL_MSK (((1U << AUDIO_HPBG_CHOP_SEL_LEN) - 1) << AUDIO_HPBG_CHOP_SEL_POS) -#define AUDIO_HPBG_CHOP_SEL_UMSK (~(((1U << AUDIO_HPBG_CHOP_SEL_LEN) - 1) << AUDIO_HPBG_CHOP_SEL_POS)) -#define AUDIO_HPBG_CHOP_EN AUDIO_HPBG_CHOP_EN -#define AUDIO_HPBG_CHOP_EN_POS (3U) -#define AUDIO_HPBG_CHOP_EN_LEN (1U) -#define AUDIO_HPBG_CHOP_EN_MSK (((1U << AUDIO_HPBG_CHOP_EN_LEN) - 1) << AUDIO_HPBG_CHOP_EN_POS) -#define AUDIO_HPBG_CHOP_EN_UMSK (~(((1U << AUDIO_HPBG_CHOP_EN_LEN) - 1) << AUDIO_HPBG_CHOP_EN_POS)) -#define AUDIO_HPBG_PU AUDIO_HPBG_PU -#define AUDIO_HPBG_PU_POS (4U) -#define AUDIO_HPBG_PU_LEN (1U) -#define AUDIO_HPBG_PU_MSK (((1U << AUDIO_HPBG_PU_LEN) - 1) << AUDIO_HPBG_PU_POS) -#define AUDIO_HPBG_PU_UMSK (~(((1U << AUDIO_HPBG_PU_LEN) - 1) << AUDIO_HPBG_PU_POS)) -#define AUDIO_HPBG_FILT_RSEL AUDIO_HPBG_FILT_RSEL -#define AUDIO_HPBG_FILT_RSEL_POS (5U) -#define AUDIO_HPBG_FILT_RSEL_LEN (2U) -#define AUDIO_HPBG_FILT_RSEL_MSK (((1U << AUDIO_HPBG_FILT_RSEL_LEN) - 1) << AUDIO_HPBG_FILT_RSEL_POS) -#define AUDIO_HPBG_FILT_RSEL_UMSK (~(((1U << AUDIO_HPBG_FILT_RSEL_LEN) - 1) << AUDIO_HPBG_FILT_RSEL_POS)) -#define AUDIO_HPBG_BYPASS AUDIO_HPBG_BYPASS -#define AUDIO_HPBG_BYPASS_POS (7U) -#define AUDIO_HPBG_BYPASS_LEN (1U) -#define AUDIO_HPBG_BYPASS_MSK (((1U << AUDIO_HPBG_BYPASS_LEN) - 1) << AUDIO_HPBG_BYPASS_POS) -#define AUDIO_HPBG_BYPASS_UMSK (~(((1U << AUDIO_HPBG_BYPASS_LEN) - 1) << AUDIO_HPBG_BYPASS_POS)) -#define AUDIO_HPBG_ADJUST_FINE AUDIO_HPBG_ADJUST_FINE -#define AUDIO_HPBG_ADJUST_FINE_POS (8U) -#define AUDIO_HPBG_ADJUST_FINE_LEN (4U) -#define AUDIO_HPBG_ADJUST_FINE_MSK (((1U << AUDIO_HPBG_ADJUST_FINE_LEN) - 1) << AUDIO_HPBG_ADJUST_FINE_POS) -#define AUDIO_HPBG_ADJUST_FINE_UMSK (~(((1U << AUDIO_HPBG_ADJUST_FINE_LEN) - 1) << AUDIO_HPBG_ADJUST_FINE_POS)) -#define AUDIO_HPBG_ADJUST_COARSE AUDIO_HPBG_ADJUST_COARSE -#define AUDIO_HPBG_ADJUST_COARSE_POS (12U) -#define AUDIO_HPBG_ADJUST_COARSE_LEN (4U) -#define AUDIO_HPBG_ADJUST_COARSE_MSK (((1U << AUDIO_HPBG_ADJUST_COARSE_LEN) - 1) << AUDIO_HPBG_ADJUST_COARSE_POS) -#define AUDIO_HPBG_ADJUST_COARSE_UMSK (~(((1U << AUDIO_HPBG_ADJUST_COARSE_LEN) - 1) << AUDIO_HPBG_ADJUST_COARSE_POS)) -#define AUDIO_HPBG_COMPST_EN AUDIO_HPBG_COMPST_EN -#define AUDIO_HPBG_COMPST_EN_POS (16U) -#define AUDIO_HPBG_COMPST_EN_LEN (1U) -#define AUDIO_HPBG_COMPST_EN_MSK (((1U << AUDIO_HPBG_COMPST_EN_LEN) - 1) << AUDIO_HPBG_COMPST_EN_POS) -#define AUDIO_HPBG_COMPST_EN_UMSK (~(((1U << AUDIO_HPBG_COMPST_EN_LEN) - 1) << AUDIO_HPBG_COMPST_EN_POS)) -#define AUDIO_LDO25_SSTART_EN AUDIO_LDO25_SSTART_EN -#define AUDIO_LDO25_SSTART_EN_POS (17U) -#define AUDIO_LDO25_SSTART_EN_LEN (1U) -#define AUDIO_LDO25_SSTART_EN_MSK (((1U << AUDIO_LDO25_SSTART_EN_LEN) - 1) << AUDIO_LDO25_SSTART_EN_POS) -#define AUDIO_LDO25_SSTART_EN_UMSK (~(((1U << AUDIO_LDO25_SSTART_EN_LEN) - 1) << AUDIO_LDO25_SSTART_EN_POS)) -#define AUDIO_LDO25_SSTART_DELAY AUDIO_LDO25_SSTART_DELAY -#define AUDIO_LDO25_SSTART_DELAY_POS (18U) -#define AUDIO_LDO25_SSTART_DELAY_LEN (2U) -#define AUDIO_LDO25_SSTART_DELAY_MSK (((1U << AUDIO_LDO25_SSTART_DELAY_LEN) - 1) << AUDIO_LDO25_SSTART_DELAY_POS) -#define AUDIO_LDO25_SSTART_DELAY_UMSK (~(((1U << AUDIO_LDO25_SSTART_DELAY_LEN) - 1) << AUDIO_LDO25_SSTART_DELAY_POS)) -#define AUDIO_LDO25_PULLDOWN_SEL AUDIO_LDO25_PULLDOWN_SEL -#define AUDIO_LDO25_PULLDOWN_SEL_POS (20U) -#define AUDIO_LDO25_PULLDOWN_SEL_LEN (1U) -#define AUDIO_LDO25_PULLDOWN_SEL_MSK (((1U << AUDIO_LDO25_PULLDOWN_SEL_LEN) - 1) << AUDIO_LDO25_PULLDOWN_SEL_POS) -#define AUDIO_LDO25_PULLDOWN_SEL_UMSK (~(((1U << AUDIO_LDO25_PULLDOWN_SEL_LEN) - 1) << AUDIO_LDO25_PULLDOWN_SEL_POS)) -#define AUDIO_LDO25_PULLDOWN AUDIO_LDO25_PULLDOWN -#define AUDIO_LDO25_PULLDOWN_POS (21U) -#define AUDIO_LDO25_PULLDOWN_LEN (1U) -#define AUDIO_LDO25_PULLDOWN_MSK (((1U << AUDIO_LDO25_PULLDOWN_LEN) - 1) << AUDIO_LDO25_PULLDOWN_POS) -#define AUDIO_LDO25_PULLDOWN_UMSK (~(((1U << AUDIO_LDO25_PULLDOWN_LEN) - 1) << AUDIO_LDO25_PULLDOWN_POS)) -#define AUDIO_LDO25_PU AUDIO_LDO25_PU -#define AUDIO_LDO25_PU_POS (22U) -#define AUDIO_LDO25_PU_LEN (1U) -#define AUDIO_LDO25_PU_MSK (((1U << AUDIO_LDO25_PU_LEN) - 1) << AUDIO_LDO25_PU_POS) -#define AUDIO_LDO25_PU_UMSK (~(((1U << AUDIO_LDO25_PU_LEN) - 1) << AUDIO_LDO25_PU_POS)) -#define AUDIO_LDO25_CHOP_SEL AUDIO_LDO25_CHOP_SEL -#define AUDIO_LDO25_CHOP_SEL_POS (24U) -#define AUDIO_LDO25_CHOP_SEL_LEN (3U) -#define AUDIO_LDO25_CHOP_SEL_MSK (((1U << AUDIO_LDO25_CHOP_SEL_LEN) - 1) << AUDIO_LDO25_CHOP_SEL_POS) -#define AUDIO_LDO25_CHOP_SEL_UMSK (~(((1U << AUDIO_LDO25_CHOP_SEL_LEN) - 1) << AUDIO_LDO25_CHOP_SEL_POS)) -#define AUDIO_LDO25_CHOP_EN AUDIO_LDO25_CHOP_EN -#define AUDIO_LDO25_CHOP_EN_POS (27U) -#define AUDIO_LDO25_CHOP_EN_LEN (1U) -#define AUDIO_LDO25_CHOP_EN_MSK (((1U << AUDIO_LDO25_CHOP_EN_LEN) - 1) << AUDIO_LDO25_CHOP_EN_POS) -#define AUDIO_LDO25_CHOP_EN_UMSK (~(((1U << AUDIO_LDO25_CHOP_EN_LEN) - 1) << AUDIO_LDO25_CHOP_EN_POS)) -#define AUDIO_LDO25_CC_SEL AUDIO_LDO25_CC_SEL -#define AUDIO_LDO25_CC_SEL_POS (28U) -#define AUDIO_LDO25_CC_SEL_LEN (3U) -#define AUDIO_LDO25_CC_SEL_MSK (((1U << AUDIO_LDO25_CC_SEL_LEN) - 1) << AUDIO_LDO25_CC_SEL_POS) -#define AUDIO_LDO25_CC_SEL_UMSK (~(((1U << AUDIO_LDO25_CC_SEL_LEN) - 1) << AUDIO_LDO25_CC_SEL_POS)) - -/* 0x708 : codec_dac */ -#define AUDIO_CODEC_DAC_OFFSET (0x708) -#define AUDIO_DACR_LINEOUT_GAIN AUDIO_DACR_LINEOUT_GAIN -#define AUDIO_DACR_LINEOUT_GAIN_POS (0U) -#define AUDIO_DACR_LINEOUT_GAIN_LEN (3U) -#define AUDIO_DACR_LINEOUT_GAIN_MSK (((1U << AUDIO_DACR_LINEOUT_GAIN_LEN) - 1) << AUDIO_DACR_LINEOUT_GAIN_POS) -#define AUDIO_DACR_LINEOUT_GAIN_UMSK (~(((1U << AUDIO_DACR_LINEOUT_GAIN_LEN) - 1) << AUDIO_DACR_LINEOUT_GAIN_POS)) -#define AUDIO_DACR_EN_LINEOUT AUDIO_DACR_EN_LINEOUT -#define AUDIO_DACR_EN_LINEOUT_POS (3U) -#define AUDIO_DACR_EN_LINEOUT_LEN (1U) -#define AUDIO_DACR_EN_LINEOUT_MSK (((1U << AUDIO_DACR_EN_LINEOUT_LEN) - 1) << AUDIO_DACR_EN_LINEOUT_POS) -#define AUDIO_DACR_EN_LINEOUT_UMSK (~(((1U << AUDIO_DACR_EN_LINEOUT_LEN) - 1) << AUDIO_DACR_EN_LINEOUT_POS)) -#define AUDIO_DACR_EN_DAC AUDIO_DACR_EN_DAC -#define AUDIO_DACR_EN_DAC_POS (4U) -#define AUDIO_DACR_EN_DAC_LEN (1U) -#define AUDIO_DACR_EN_DAC_MSK (((1U << AUDIO_DACR_EN_DAC_LEN) - 1) << AUDIO_DACR_EN_DAC_POS) -#define AUDIO_DACR_EN_DAC_UMSK (~(((1U << AUDIO_DACR_EN_DAC_LEN) - 1) << AUDIO_DACR_EN_DAC_POS)) -#define AUDIO_DACR_LINEOUT_MODE AUDIO_DACR_LINEOUT_MODE -#define AUDIO_DACR_LINEOUT_MODE_POS (6U) -#define AUDIO_DACR_LINEOUT_MODE_LEN (1U) -#define AUDIO_DACR_LINEOUT_MODE_MSK (((1U << AUDIO_DACR_LINEOUT_MODE_LEN) - 1) << AUDIO_DACR_LINEOUT_MODE_POS) -#define AUDIO_DACR_LINEOUT_MODE_UMSK (~(((1U << AUDIO_DACR_LINEOUT_MODE_LEN) - 1) << AUDIO_DACR_LINEOUT_MODE_POS)) -#define AUDIO_DACR_ICTRL_LINEOUT AUDIO_DACR_ICTRL_LINEOUT -#define AUDIO_DACR_ICTRL_LINEOUT_POS (8U) -#define AUDIO_DACR_ICTRL_LINEOUT_LEN (2U) -#define AUDIO_DACR_ICTRL_LINEOUT_MSK (((1U << AUDIO_DACR_ICTRL_LINEOUT_LEN) - 1) << AUDIO_DACR_ICTRL_LINEOUT_POS) -#define AUDIO_DACR_ICTRL_LINEOUT_UMSK (~(((1U << AUDIO_DACR_ICTRL_LINEOUT_LEN) - 1) << AUDIO_DACR_ICTRL_LINEOUT_POS)) -#define AUDIO_DACR_SDAC_LINEOUT AUDIO_DACR_SDAC_LINEOUT -#define AUDIO_DACR_SDAC_LINEOUT_POS (10U) -#define AUDIO_DACR_SDAC_LINEOUT_LEN (1U) -#define AUDIO_DACR_SDAC_LINEOUT_MSK (((1U << AUDIO_DACR_SDAC_LINEOUT_LEN) - 1) << AUDIO_DACR_SDAC_LINEOUT_POS) -#define AUDIO_DACR_SDAC_LINEOUT_UMSK (~(((1U << AUDIO_DACR_SDAC_LINEOUT_LEN) - 1) << AUDIO_DACR_SDAC_LINEOUT_POS)) -#define AUDIO_DACR_SDEBUG_LINEOUT AUDIO_DACR_SDEBUG_LINEOUT -#define AUDIO_DACR_SDEBUG_LINEOUT_POS (11U) -#define AUDIO_DACR_SDEBUG_LINEOUT_LEN (1U) -#define AUDIO_DACR_SDEBUG_LINEOUT_MSK (((1U << AUDIO_DACR_SDEBUG_LINEOUT_LEN) - 1) << AUDIO_DACR_SDEBUG_LINEOUT_POS) -#define AUDIO_DACR_SDEBUG_LINEOUT_UMSK (~(((1U << AUDIO_DACR_SDEBUG_LINEOUT_LEN) - 1) << AUDIO_DACR_SDEBUG_LINEOUT_POS)) -#define AUDIO_DACR_ICTRL_DAC AUDIO_DACR_ICTRL_DAC -#define AUDIO_DACR_ICTRL_DAC_POS (12U) -#define AUDIO_DACR_ICTRL_DAC_LEN (2U) -#define AUDIO_DACR_ICTRL_DAC_MSK (((1U << AUDIO_DACR_ICTRL_DAC_LEN) - 1) << AUDIO_DACR_ICTRL_DAC_POS) -#define AUDIO_DACR_ICTRL_DAC_UMSK (~(((1U << AUDIO_DACR_ICTRL_DAC_LEN) - 1) << AUDIO_DACR_ICTRL_DAC_POS)) -#define AUDIO_DACR_CKB_EN AUDIO_DACR_CKB_EN -#define AUDIO_DACR_CKB_EN_POS (14U) -#define AUDIO_DACR_CKB_EN_LEN (1U) -#define AUDIO_DACR_CKB_EN_MSK (((1U << AUDIO_DACR_CKB_EN_LEN) - 1) << AUDIO_DACR_CKB_EN_POS) -#define AUDIO_DACR_CKB_EN_UMSK (~(((1U << AUDIO_DACR_CKB_EN_LEN) - 1) << AUDIO_DACR_CKB_EN_POS)) -#define AUDIO_DACL_LINEOUT_GAIN AUDIO_DACL_LINEOUT_GAIN -#define AUDIO_DACL_LINEOUT_GAIN_POS (16U) -#define AUDIO_DACL_LINEOUT_GAIN_LEN (3U) -#define AUDIO_DACL_LINEOUT_GAIN_MSK (((1U << AUDIO_DACL_LINEOUT_GAIN_LEN) - 1) << AUDIO_DACL_LINEOUT_GAIN_POS) -#define AUDIO_DACL_LINEOUT_GAIN_UMSK (~(((1U << AUDIO_DACL_LINEOUT_GAIN_LEN) - 1) << AUDIO_DACL_LINEOUT_GAIN_POS)) -#define AUDIO_DACL_EN_LINEOUT AUDIO_DACL_EN_LINEOUT -#define AUDIO_DACL_EN_LINEOUT_POS (19U) -#define AUDIO_DACL_EN_LINEOUT_LEN (1U) -#define AUDIO_DACL_EN_LINEOUT_MSK (((1U << AUDIO_DACL_EN_LINEOUT_LEN) - 1) << AUDIO_DACL_EN_LINEOUT_POS) -#define AUDIO_DACL_EN_LINEOUT_UMSK (~(((1U << AUDIO_DACL_EN_LINEOUT_LEN) - 1) << AUDIO_DACL_EN_LINEOUT_POS)) -#define AUDIO_DACL_EN_DAC AUDIO_DACL_EN_DAC -#define AUDIO_DACL_EN_DAC_POS (20U) -#define AUDIO_DACL_EN_DAC_LEN (1U) -#define AUDIO_DACL_EN_DAC_MSK (((1U << AUDIO_DACL_EN_DAC_LEN) - 1) << AUDIO_DACL_EN_DAC_POS) -#define AUDIO_DACL_EN_DAC_UMSK (~(((1U << AUDIO_DACL_EN_DAC_LEN) - 1) << AUDIO_DACL_EN_DAC_POS)) -#define AUDIO_DACL_LINEOUT_MODE AUDIO_DACL_LINEOUT_MODE -#define AUDIO_DACL_LINEOUT_MODE_POS (22U) -#define AUDIO_DACL_LINEOUT_MODE_LEN (1U) -#define AUDIO_DACL_LINEOUT_MODE_MSK (((1U << AUDIO_DACL_LINEOUT_MODE_LEN) - 1) << AUDIO_DACL_LINEOUT_MODE_POS) -#define AUDIO_DACL_LINEOUT_MODE_UMSK (~(((1U << AUDIO_DACL_LINEOUT_MODE_LEN) - 1) << AUDIO_DACL_LINEOUT_MODE_POS)) -#define AUDIO_DACL_ICTRL_LINEOUT AUDIO_DACL_ICTRL_LINEOUT -#define AUDIO_DACL_ICTRL_LINEOUT_POS (24U) -#define AUDIO_DACL_ICTRL_LINEOUT_LEN (2U) -#define AUDIO_DACL_ICTRL_LINEOUT_MSK (((1U << AUDIO_DACL_ICTRL_LINEOUT_LEN) - 1) << AUDIO_DACL_ICTRL_LINEOUT_POS) -#define AUDIO_DACL_ICTRL_LINEOUT_UMSK (~(((1U << AUDIO_DACL_ICTRL_LINEOUT_LEN) - 1) << AUDIO_DACL_ICTRL_LINEOUT_POS)) -#define AUDIO_DACL_SDAC_LINEOUT AUDIO_DACL_SDAC_LINEOUT -#define AUDIO_DACL_SDAC_LINEOUT_POS (26U) -#define AUDIO_DACL_SDAC_LINEOUT_LEN (1U) -#define AUDIO_DACL_SDAC_LINEOUT_MSK (((1U << AUDIO_DACL_SDAC_LINEOUT_LEN) - 1) << AUDIO_DACL_SDAC_LINEOUT_POS) -#define AUDIO_DACL_SDAC_LINEOUT_UMSK (~(((1U << AUDIO_DACL_SDAC_LINEOUT_LEN) - 1) << AUDIO_DACL_SDAC_LINEOUT_POS)) -#define AUDIO_DACL_SDEBUG_LINEOUT AUDIO_DACL_SDEBUG_LINEOUT -#define AUDIO_DACL_SDEBUG_LINEOUT_POS (27U) -#define AUDIO_DACL_SDEBUG_LINEOUT_LEN (1U) -#define AUDIO_DACL_SDEBUG_LINEOUT_MSK (((1U << AUDIO_DACL_SDEBUG_LINEOUT_LEN) - 1) << AUDIO_DACL_SDEBUG_LINEOUT_POS) -#define AUDIO_DACL_SDEBUG_LINEOUT_UMSK (~(((1U << AUDIO_DACL_SDEBUG_LINEOUT_LEN) - 1) << AUDIO_DACL_SDEBUG_LINEOUT_POS)) -#define AUDIO_DACL_ICTRL_DAC AUDIO_DACL_ICTRL_DAC -#define AUDIO_DACL_ICTRL_DAC_POS (28U) -#define AUDIO_DACL_ICTRL_DAC_LEN (2U) -#define AUDIO_DACL_ICTRL_DAC_MSK (((1U << AUDIO_DACL_ICTRL_DAC_LEN) - 1) << AUDIO_DACL_ICTRL_DAC_POS) -#define AUDIO_DACL_ICTRL_DAC_UMSK (~(((1U << AUDIO_DACL_ICTRL_DAC_LEN) - 1) << AUDIO_DACL_ICTRL_DAC_POS)) -#define AUDIO_DACL_CKB_EN AUDIO_DACL_CKB_EN -#define AUDIO_DACL_CKB_EN_POS (30U) -#define AUDIO_DACL_CKB_EN_LEN (1U) -#define AUDIO_DACL_CKB_EN_MSK (((1U << AUDIO_DACL_CKB_EN_LEN) - 1) << AUDIO_DACL_CKB_EN_POS) -#define AUDIO_DACL_CKB_EN_UMSK (~(((1U << AUDIO_DACL_CKB_EN_LEN) - 1) << AUDIO_DACL_CKB_EN_POS)) -#define AUDIO_DAC_RG_LO_VREF_RAMP_DCL_BUSY AUDIO_DAC_RG_LO_VREF_RAMP_DCL_BUSY -#define AUDIO_DAC_RG_LO_VREF_RAMP_DCL_BUSY_POS (31U) -#define AUDIO_DAC_RG_LO_VREF_RAMP_DCL_BUSY_LEN (1U) -#define AUDIO_DAC_RG_LO_VREF_RAMP_DCL_BUSY_MSK (((1U << AUDIO_DAC_RG_LO_VREF_RAMP_DCL_BUSY_LEN) - 1) << AUDIO_DAC_RG_LO_VREF_RAMP_DCL_BUSY_POS) -#define AUDIO_DAC_RG_LO_VREF_RAMP_DCL_BUSY_UMSK (~(((1U << AUDIO_DAC_RG_LO_VREF_RAMP_DCL_BUSY_LEN) - 1) << AUDIO_DAC_RG_LO_VREF_RAMP_DCL_BUSY_POS)) - -/* 0x70C : codec_dac_ramp */ -#define AUDIO_CODEC_DAC_RAMP_OFFSET (0x70C) -#define AUDIO_DAC_RG_LO_VREF_RAMP_DCL_EN AUDIO_DAC_RG_LO_VREF_RAMP_DCL_EN -#define AUDIO_DAC_RG_LO_VREF_RAMP_DCL_EN_POS (0U) -#define AUDIO_DAC_RG_LO_VREF_RAMP_DCL_EN_LEN (1U) -#define AUDIO_DAC_RG_LO_VREF_RAMP_DCL_EN_MSK (((1U << AUDIO_DAC_RG_LO_VREF_RAMP_DCL_EN_LEN) - 1) << AUDIO_DAC_RG_LO_VREF_RAMP_DCL_EN_POS) -#define AUDIO_DAC_RG_LO_VREF_RAMP_DCL_EN_UMSK (~(((1U << AUDIO_DAC_RG_LO_VREF_RAMP_DCL_EN_LEN) - 1) << AUDIO_DAC_RG_LO_VREF_RAMP_DCL_EN_POS)) -#define AUDIO_DAC_RG_LINEOUT_VO_PULLDOWN AUDIO_DAC_RG_LINEOUT_VO_PULLDOWN -#define AUDIO_DAC_RG_LINEOUT_VO_PULLDOWN_POS (1U) -#define AUDIO_DAC_RG_LINEOUT_VO_PULLDOWN_LEN (1U) -#define AUDIO_DAC_RG_LINEOUT_VO_PULLDOWN_MSK (((1U << AUDIO_DAC_RG_LINEOUT_VO_PULLDOWN_LEN) - 1) << AUDIO_DAC_RG_LINEOUT_VO_PULLDOWN_POS) -#define AUDIO_DAC_RG_LINEOUT_VO_PULLDOWN_UMSK (~(((1U << AUDIO_DAC_RG_LINEOUT_VO_PULLDOWN_LEN) - 1) << AUDIO_DAC_RG_LINEOUT_VO_PULLDOWN_POS)) -#define AUDIO_DAC_RG_PU_VREF_RAMP AUDIO_DAC_RG_PU_VREF_RAMP -#define AUDIO_DAC_RG_PU_VREF_RAMP_POS (2U) -#define AUDIO_DAC_RG_PU_VREF_RAMP_LEN (1U) -#define AUDIO_DAC_RG_PU_VREF_RAMP_MSK (((1U << AUDIO_DAC_RG_PU_VREF_RAMP_LEN) - 1) << AUDIO_DAC_RG_PU_VREF_RAMP_POS) -#define AUDIO_DAC_RG_PU_VREF_RAMP_UMSK (~(((1U << AUDIO_DAC_RG_PU_VREF_RAMP_LEN) - 1) << AUDIO_DAC_RG_PU_VREF_RAMP_POS)) -#define AUDIO_DAC_RG_PU_LINEOUT AUDIO_DAC_RG_PU_LINEOUT -#define AUDIO_DAC_RG_PU_LINEOUT_POS (3U) -#define AUDIO_DAC_RG_PU_LINEOUT_LEN (1U) -#define AUDIO_DAC_RG_PU_LINEOUT_MSK (((1U << AUDIO_DAC_RG_PU_LINEOUT_LEN) - 1) << AUDIO_DAC_RG_PU_LINEOUT_POS) -#define AUDIO_DAC_RG_PU_LINEOUT_UMSK (~(((1U << AUDIO_DAC_RG_PU_LINEOUT_LEN) - 1) << AUDIO_DAC_RG_PU_LINEOUT_POS)) -#define AUDIO_DAC_RG_VREF_RAMP_STEP_T AUDIO_DAC_RG_VREF_RAMP_STEP_T -#define AUDIO_DAC_RG_VREF_RAMP_STEP_T_POS (4U) -#define AUDIO_DAC_RG_VREF_RAMP_STEP_T_LEN (3U) -#define AUDIO_DAC_RG_VREF_RAMP_STEP_T_MSK (((1U << AUDIO_DAC_RG_VREF_RAMP_STEP_T_LEN) - 1) << AUDIO_DAC_RG_VREF_RAMP_STEP_T_POS) -#define AUDIO_DAC_RG_VREF_RAMP_STEP_T_UMSK (~(((1U << AUDIO_DAC_RG_VREF_RAMP_STEP_T_LEN) - 1) << AUDIO_DAC_RG_VREF_RAMP_STEP_T_POS)) -#define AUDIO_DAC_RG_SW_VREF AUDIO_DAC_RG_SW_VREF -#define AUDIO_DAC_RG_SW_VREF_POS (7U) -#define AUDIO_DAC_RG_SW_VREF_LEN (1U) -#define AUDIO_DAC_RG_SW_VREF_MSK (((1U << AUDIO_DAC_RG_SW_VREF_LEN) - 1) << AUDIO_DAC_RG_SW_VREF_POS) -#define AUDIO_DAC_RG_SW_VREF_UMSK (~(((1U << AUDIO_DAC_RG_SW_VREF_LEN) - 1) << AUDIO_DAC_RG_SW_VREF_POS)) -#define AUDIO_DAC_RG_VREF_RAMP_DELAY AUDIO_DAC_RG_VREF_RAMP_DELAY -#define AUDIO_DAC_RG_VREF_RAMP_DELAY_POS (8U) -#define AUDIO_DAC_RG_VREF_RAMP_DELAY_LEN (2U) -#define AUDIO_DAC_RG_VREF_RAMP_DELAY_MSK (((1U << AUDIO_DAC_RG_VREF_RAMP_DELAY_LEN) - 1) << AUDIO_DAC_RG_VREF_RAMP_DELAY_POS) -#define AUDIO_DAC_RG_VREF_RAMP_DELAY_UMSK (~(((1U << AUDIO_DAC_RG_VREF_RAMP_DELAY_LEN) - 1) << AUDIO_DAC_RG_VREF_RAMP_DELAY_POS)) -#define AUDIO_DAC_RG_LO_VREF_RAMP_DVLD AUDIO_DAC_RG_LO_VREF_RAMP_DVLD -#define AUDIO_DAC_RG_LO_VREF_RAMP_DVLD_POS (10U) -#define AUDIO_DAC_RG_LO_VREF_RAMP_DVLD_LEN (1U) -#define AUDIO_DAC_RG_LO_VREF_RAMP_DVLD_MSK (((1U << AUDIO_DAC_RG_LO_VREF_RAMP_DVLD_LEN) - 1) << AUDIO_DAC_RG_LO_VREF_RAMP_DVLD_POS) -#define AUDIO_DAC_RG_LO_VREF_RAMP_DVLD_UMSK (~(((1U << AUDIO_DAC_RG_LO_VREF_RAMP_DVLD_LEN) - 1) << AUDIO_DAC_RG_LO_VREF_RAMP_DVLD_POS)) -#define AUDIO_DAC_AUTOMUTE_EN AUDIO_DAC_AUTOMUTE_EN -#define AUDIO_DAC_AUTOMUTE_EN_POS (11U) -#define AUDIO_DAC_AUTOMUTE_EN_LEN (1U) -#define AUDIO_DAC_AUTOMUTE_EN_MSK (((1U << AUDIO_DAC_AUTOMUTE_EN_LEN) - 1) << AUDIO_DAC_AUTOMUTE_EN_POS) -#define AUDIO_DAC_AUTOMUTE_EN_UMSK (~(((1U << AUDIO_DAC_AUTOMUTE_EN_LEN) - 1) << AUDIO_DAC_AUTOMUTE_EN_POS)) -#define AUDIO_DG_DAC_MUTE AUDIO_DG_DAC_MUTE -#define AUDIO_DG_DAC_MUTE_POS (12U) -#define AUDIO_DG_DAC_MUTE_LEN (1U) -#define AUDIO_DG_DAC_MUTE_MSK (((1U << AUDIO_DG_DAC_MUTE_LEN) - 1) << AUDIO_DG_DAC_MUTE_POS) -#define AUDIO_DG_DAC_MUTE_UMSK (~(((1U << AUDIO_DG_DAC_MUTE_LEN) - 1) << AUDIO_DG_DAC_MUTE_POS)) -#define AUDIO_DG_VO_PULLDOWN AUDIO_DG_VO_PULLDOWN -#define AUDIO_DG_VO_PULLDOWN_POS (13U) -#define AUDIO_DG_VO_PULLDOWN_LEN (1U) -#define AUDIO_DG_VO_PULLDOWN_MSK (((1U << AUDIO_DG_VO_PULLDOWN_LEN) - 1) << AUDIO_DG_VO_PULLDOWN_POS) -#define AUDIO_DG_VO_PULLDOWN_UMSK (~(((1U << AUDIO_DG_VO_PULLDOWN_LEN) - 1) << AUDIO_DG_VO_PULLDOWN_POS)) -#define AUDIO_DG_PU_VREF_RAMP AUDIO_DG_PU_VREF_RAMP -#define AUDIO_DG_PU_VREF_RAMP_POS (14U) -#define AUDIO_DG_PU_VREF_RAMP_LEN (1U) -#define AUDIO_DG_PU_VREF_RAMP_MSK (((1U << AUDIO_DG_PU_VREF_RAMP_LEN) - 1) << AUDIO_DG_PU_VREF_RAMP_POS) -#define AUDIO_DG_PU_VREF_RAMP_UMSK (~(((1U << AUDIO_DG_PU_VREF_RAMP_LEN) - 1) << AUDIO_DG_PU_VREF_RAMP_POS)) -#define AUDIO_DG_VREF_RAMP_STEP AUDIO_DG_VREF_RAMP_STEP -#define AUDIO_DG_VREF_RAMP_STEP_POS (15U) -#define AUDIO_DG_VREF_RAMP_STEP_LEN (12U) -#define AUDIO_DG_VREF_RAMP_STEP_MSK (((1U << AUDIO_DG_VREF_RAMP_STEP_LEN) - 1) << AUDIO_DG_VREF_RAMP_STEP_POS) -#define AUDIO_DG_VREF_RAMP_STEP_UMSK (~(((1U << AUDIO_DG_VREF_RAMP_STEP_LEN) - 1) << AUDIO_DG_VREF_RAMP_STEP_POS)) -#define AUDIO_DG_SW_VREF AUDIO_DG_SW_VREF -#define AUDIO_DG_SW_VREF_POS (27U) -#define AUDIO_DG_SW_VREF_LEN (1U) -#define AUDIO_DG_SW_VREF_MSK (((1U << AUDIO_DG_SW_VREF_LEN) - 1) << AUDIO_DG_SW_VREF_POS) -#define AUDIO_DG_SW_VREF_UMSK (~(((1U << AUDIO_DG_SW_VREF_LEN) - 1) << AUDIO_DG_SW_VREF_POS)) -#define AUDIO_DG_DACR_EN_LINEOUT AUDIO_DG_DACR_EN_LINEOUT -#define AUDIO_DG_DACR_EN_LINEOUT_POS (28U) -#define AUDIO_DG_DACR_EN_LINEOUT_LEN (1U) -#define AUDIO_DG_DACR_EN_LINEOUT_MSK (((1U << AUDIO_DG_DACR_EN_LINEOUT_LEN) - 1) << AUDIO_DG_DACR_EN_LINEOUT_POS) -#define AUDIO_DG_DACR_EN_LINEOUT_UMSK (~(((1U << AUDIO_DG_DACR_EN_LINEOUT_LEN) - 1) << AUDIO_DG_DACR_EN_LINEOUT_POS)) -#define AUDIO_DG_DACL_EN_LINEOUT AUDIO_DG_DACL_EN_LINEOUT -#define AUDIO_DG_DACL_EN_LINEOUT_POS (29U) -#define AUDIO_DG_DACL_EN_LINEOUT_LEN (1U) -#define AUDIO_DG_DACL_EN_LINEOUT_MSK (((1U << AUDIO_DG_DACL_EN_LINEOUT_LEN) - 1) << AUDIO_DG_DACL_EN_LINEOUT_POS) -#define AUDIO_DG_DACL_EN_LINEOUT_UMSK (~(((1U << AUDIO_DG_DACL_EN_LINEOUT_LEN) - 1) << AUDIO_DG_DACL_EN_LINEOUT_POS)) -#define AUDIO_DAC_RG_VREF_RAMP_DCL_MODE AUDIO_DAC_RG_VREF_RAMP_DCL_MODE -#define AUDIO_DAC_RG_VREF_RAMP_DCL_MODE_POS (30U) -#define AUDIO_DAC_RG_VREF_RAMP_DCL_MODE_LEN (2U) -#define AUDIO_DAC_RG_VREF_RAMP_DCL_MODE_MSK (((1U << AUDIO_DAC_RG_VREF_RAMP_DCL_MODE_LEN) - 1) << AUDIO_DAC_RG_VREF_RAMP_DCL_MODE_POS) -#define AUDIO_DAC_RG_VREF_RAMP_DCL_MODE_UMSK (~(((1U << AUDIO_DAC_RG_VREF_RAMP_DCL_MODE_LEN) - 1) << AUDIO_DAC_RG_VREF_RAMP_DCL_MODE_POS)) - -/* 0x710 : codec_adc0 */ -#define AUDIO_CODEC_ADC0_OFFSET (0x710) -#define AUDIO_ADC0_SDM_LP AUDIO_ADC0_SDM_LP -#define AUDIO_ADC0_SDM_LP_POS (0U) -#define AUDIO_ADC0_SDM_LP_LEN (1U) -#define AUDIO_ADC0_SDM_LP_MSK (((1U << AUDIO_ADC0_SDM_LP_LEN) - 1) << AUDIO_ADC0_SDM_LP_POS) -#define AUDIO_ADC0_SDM_LP_UMSK (~(((1U << AUDIO_ADC0_SDM_LP_LEN) - 1) << AUDIO_ADC0_SDM_LP_POS)) -#define AUDIO_ADC0_CKB_EN AUDIO_ADC0_CKB_EN -#define AUDIO_ADC0_CKB_EN_POS (1U) -#define AUDIO_ADC0_CKB_EN_LEN (1U) -#define AUDIO_ADC0_CKB_EN_MSK (((1U << AUDIO_ADC0_CKB_EN_LEN) - 1) << AUDIO_ADC0_CKB_EN_POS) -#define AUDIO_ADC0_CKB_EN_UMSK (~(((1U << AUDIO_ADC0_CKB_EN_LEN) - 1) << AUDIO_ADC0_CKB_EN_POS)) -#define AUDIO_ADC0_REG_RESEV AUDIO_ADC0_REG_RESEV -#define AUDIO_ADC0_REG_RESEV_POS (2U) -#define AUDIO_ADC0_REG_RESEV_LEN (1U) -#define AUDIO_ADC0_REG_RESEV_MSK (((1U << AUDIO_ADC0_REG_RESEV_LEN) - 1) << AUDIO_ADC0_REG_RESEV_POS) -#define AUDIO_ADC0_REG_RESEV_UMSK (~(((1U << AUDIO_ADC0_REG_RESEV_LEN) - 1) << AUDIO_ADC0_REG_RESEV_POS)) -#define AUDIO_ADC0_PGA_RCM_SEL AUDIO_ADC0_PGA_RCM_SEL -#define AUDIO_ADC0_PGA_RCM_SEL_POS (4U) -#define AUDIO_ADC0_PGA_RCM_SEL_LEN (2U) -#define AUDIO_ADC0_PGA_RCM_SEL_MSK (((1U << AUDIO_ADC0_PGA_RCM_SEL_LEN) - 1) << AUDIO_ADC0_PGA_RCM_SEL_POS) -#define AUDIO_ADC0_PGA_RCM_SEL_UMSK (~(((1U << AUDIO_ADC0_PGA_RCM_SEL_LEN) - 1) << AUDIO_ADC0_PGA_RCM_SEL_POS)) -#define AUDIO_ADC0_PGA_GAIN AUDIO_ADC0_PGA_GAIN -#define AUDIO_ADC0_PGA_GAIN_POS (8U) -#define AUDIO_ADC0_PGA_GAIN_LEN (4U) -#define AUDIO_ADC0_PGA_GAIN_MSK (((1U << AUDIO_ADC0_PGA_GAIN_LEN) - 1) << AUDIO_ADC0_PGA_GAIN_POS) -#define AUDIO_ADC0_PGA_GAIN_UMSK (~(((1U << AUDIO_ADC0_PGA_GAIN_LEN) - 1) << AUDIO_ADC0_PGA_GAIN_POS)) -#define AUDIO_ADC0_ICTRL_MIC AUDIO_ADC0_ICTRL_MIC -#define AUDIO_ADC0_ICTRL_MIC_POS (12U) -#define AUDIO_ADC0_ICTRL_MIC_LEN (2U) -#define AUDIO_ADC0_ICTRL_MIC_MSK (((1U << AUDIO_ADC0_ICTRL_MIC_LEN) - 1) << AUDIO_ADC0_ICTRL_MIC_POS) -#define AUDIO_ADC0_ICTRL_MIC_UMSK (~(((1U << AUDIO_ADC0_ICTRL_MIC_LEN) - 1) << AUDIO_ADC0_ICTRL_MIC_POS)) -#define AUDIO_ADC0_ICTRL_ADC2 AUDIO_ADC0_ICTRL_ADC2 -#define AUDIO_ADC0_ICTRL_ADC2_POS (14U) -#define AUDIO_ADC0_ICTRL_ADC2_LEN (2U) -#define AUDIO_ADC0_ICTRL_ADC2_MSK (((1U << AUDIO_ADC0_ICTRL_ADC2_LEN) - 1) << AUDIO_ADC0_ICTRL_ADC2_POS) -#define AUDIO_ADC0_ICTRL_ADC2_UMSK (~(((1U << AUDIO_ADC0_ICTRL_ADC2_LEN) - 1) << AUDIO_ADC0_ICTRL_ADC2_POS)) -#define AUDIO_ADC0_ICTRL_ADC1 AUDIO_ADC0_ICTRL_ADC1 -#define AUDIO_ADC0_ICTRL_ADC1_POS (16U) -#define AUDIO_ADC0_ICTRL_ADC1_LEN (2U) -#define AUDIO_ADC0_ICTRL_ADC1_MSK (((1U << AUDIO_ADC0_ICTRL_ADC1_LEN) - 1) << AUDIO_ADC0_ICTRL_ADC1_POS) -#define AUDIO_ADC0_ICTRL_ADC1_UMSK (~(((1U << AUDIO_ADC0_ICTRL_ADC1_LEN) - 1) << AUDIO_ADC0_ICTRL_ADC1_POS)) -#define AUDIO_ADC0_ICTRL_AAF AUDIO_ADC0_ICTRL_AAF -#define AUDIO_ADC0_ICTRL_AAF_POS (18U) -#define AUDIO_ADC0_ICTRL_AAF_LEN (2U) -#define AUDIO_ADC0_ICTRL_AAF_MSK (((1U << AUDIO_ADC0_ICTRL_AAF_LEN) - 1) << AUDIO_ADC0_ICTRL_AAF_POS) -#define AUDIO_ADC0_ICTRL_AAF_UMSK (~(((1U << AUDIO_ADC0_ICTRL_AAF_LEN) - 1) << AUDIO_ADC0_ICTRL_AAF_POS)) -#define AUDIO_ADC0_EN_SDM AUDIO_ADC0_EN_SDM -#define AUDIO_ADC0_EN_SDM_POS (20U) -#define AUDIO_ADC0_EN_SDM_LEN (1U) -#define AUDIO_ADC0_EN_SDM_MSK (((1U << AUDIO_ADC0_EN_SDM_LEN) - 1) << AUDIO_ADC0_EN_SDM_POS) -#define AUDIO_ADC0_EN_SDM_UMSK (~(((1U << AUDIO_ADC0_EN_SDM_LEN) - 1) << AUDIO_ADC0_EN_SDM_POS)) -#define AUDIO_ADC0_EN_PGA AUDIO_ADC0_EN_PGA -#define AUDIO_ADC0_EN_PGA_POS (21U) -#define AUDIO_ADC0_EN_PGA_LEN (1U) -#define AUDIO_ADC0_EN_PGA_MSK (((1U << AUDIO_ADC0_EN_PGA_LEN) - 1) << AUDIO_ADC0_EN_PGA_POS) -#define AUDIO_ADC0_EN_PGA_UMSK (~(((1U << AUDIO_ADC0_EN_PGA_LEN) - 1) << AUDIO_ADC0_EN_PGA_POS)) -#define AUDIO_ADC_DITHER_SEL AUDIO_ADC_DITHER_SEL -#define AUDIO_ADC_DITHER_SEL_POS (22U) -#define AUDIO_ADC_DITHER_SEL_LEN (2U) -#define AUDIO_ADC_DITHER_SEL_MSK (((1U << AUDIO_ADC_DITHER_SEL_LEN) - 1) << AUDIO_ADC_DITHER_SEL_POS) -#define AUDIO_ADC_DITHER_SEL_UMSK (~(((1U << AUDIO_ADC_DITHER_SEL_LEN) - 1) << AUDIO_ADC_DITHER_SEL_POS)) - -/* 0x714 : codec_adc1 */ -#define AUDIO_CODEC_ADC1_OFFSET (0x714) -#define AUDIO_ADC1_SDM_LP AUDIO_ADC1_SDM_LP -#define AUDIO_ADC1_SDM_LP_POS (0U) -#define AUDIO_ADC1_SDM_LP_LEN (1U) -#define AUDIO_ADC1_SDM_LP_MSK (((1U << AUDIO_ADC1_SDM_LP_LEN) - 1) << AUDIO_ADC1_SDM_LP_POS) -#define AUDIO_ADC1_SDM_LP_UMSK (~(((1U << AUDIO_ADC1_SDM_LP_LEN) - 1) << AUDIO_ADC1_SDM_LP_POS)) -#define AUDIO_ADC1_CKB_EN AUDIO_ADC1_CKB_EN -#define AUDIO_ADC1_CKB_EN_POS (1U) -#define AUDIO_ADC1_CKB_EN_LEN (1U) -#define AUDIO_ADC1_CKB_EN_MSK (((1U << AUDIO_ADC1_CKB_EN_LEN) - 1) << AUDIO_ADC1_CKB_EN_POS) -#define AUDIO_ADC1_CKB_EN_UMSK (~(((1U << AUDIO_ADC1_CKB_EN_LEN) - 1) << AUDIO_ADC1_CKB_EN_POS)) -#define AUDIO_ADC1_REG_RESEV AUDIO_ADC1_REG_RESEV -#define AUDIO_ADC1_REG_RESEV_POS (2U) -#define AUDIO_ADC1_REG_RESEV_LEN (1U) -#define AUDIO_ADC1_REG_RESEV_MSK (((1U << AUDIO_ADC1_REG_RESEV_LEN) - 1) << AUDIO_ADC1_REG_RESEV_POS) -#define AUDIO_ADC1_REG_RESEV_UMSK (~(((1U << AUDIO_ADC1_REG_RESEV_LEN) - 1) << AUDIO_ADC1_REG_RESEV_POS)) -#define AUDIO_ADC1_PGA_RCM_SEL AUDIO_ADC1_PGA_RCM_SEL -#define AUDIO_ADC1_PGA_RCM_SEL_POS (4U) -#define AUDIO_ADC1_PGA_RCM_SEL_LEN (2U) -#define AUDIO_ADC1_PGA_RCM_SEL_MSK (((1U << AUDIO_ADC1_PGA_RCM_SEL_LEN) - 1) << AUDIO_ADC1_PGA_RCM_SEL_POS) -#define AUDIO_ADC1_PGA_RCM_SEL_UMSK (~(((1U << AUDIO_ADC1_PGA_RCM_SEL_LEN) - 1) << AUDIO_ADC1_PGA_RCM_SEL_POS)) -#define AUDIO_ADC1_PGA_GAIN AUDIO_ADC1_PGA_GAIN -#define AUDIO_ADC1_PGA_GAIN_POS (8U) -#define AUDIO_ADC1_PGA_GAIN_LEN (4U) -#define AUDIO_ADC1_PGA_GAIN_MSK (((1U << AUDIO_ADC1_PGA_GAIN_LEN) - 1) << AUDIO_ADC1_PGA_GAIN_POS) -#define AUDIO_ADC1_PGA_GAIN_UMSK (~(((1U << AUDIO_ADC1_PGA_GAIN_LEN) - 1) << AUDIO_ADC1_PGA_GAIN_POS)) -#define AUDIO_ADC1_ICTRL_MIC AUDIO_ADC1_ICTRL_MIC -#define AUDIO_ADC1_ICTRL_MIC_POS (12U) -#define AUDIO_ADC1_ICTRL_MIC_LEN (2U) -#define AUDIO_ADC1_ICTRL_MIC_MSK (((1U << AUDIO_ADC1_ICTRL_MIC_LEN) - 1) << AUDIO_ADC1_ICTRL_MIC_POS) -#define AUDIO_ADC1_ICTRL_MIC_UMSK (~(((1U << AUDIO_ADC1_ICTRL_MIC_LEN) - 1) << AUDIO_ADC1_ICTRL_MIC_POS)) -#define AUDIO_ADC1_ICTRL_ADC2 AUDIO_ADC1_ICTRL_ADC2 -#define AUDIO_ADC1_ICTRL_ADC2_POS (14U) -#define AUDIO_ADC1_ICTRL_ADC2_LEN (2U) -#define AUDIO_ADC1_ICTRL_ADC2_MSK (((1U << AUDIO_ADC1_ICTRL_ADC2_LEN) - 1) << AUDIO_ADC1_ICTRL_ADC2_POS) -#define AUDIO_ADC1_ICTRL_ADC2_UMSK (~(((1U << AUDIO_ADC1_ICTRL_ADC2_LEN) - 1) << AUDIO_ADC1_ICTRL_ADC2_POS)) -#define AUDIO_ADC1_ICTRL_ADC1 AUDIO_ADC1_ICTRL_ADC1 -#define AUDIO_ADC1_ICTRL_ADC1_POS (16U) -#define AUDIO_ADC1_ICTRL_ADC1_LEN (2U) -#define AUDIO_ADC1_ICTRL_ADC1_MSK (((1U << AUDIO_ADC1_ICTRL_ADC1_LEN) - 1) << AUDIO_ADC1_ICTRL_ADC1_POS) -#define AUDIO_ADC1_ICTRL_ADC1_UMSK (~(((1U << AUDIO_ADC1_ICTRL_ADC1_LEN) - 1) << AUDIO_ADC1_ICTRL_ADC1_POS)) -#define AUDIO_ADC1_ICTRL_AAF AUDIO_ADC1_ICTRL_AAF -#define AUDIO_ADC1_ICTRL_AAF_POS (18U) -#define AUDIO_ADC1_ICTRL_AAF_LEN (2U) -#define AUDIO_ADC1_ICTRL_AAF_MSK (((1U << AUDIO_ADC1_ICTRL_AAF_LEN) - 1) << AUDIO_ADC1_ICTRL_AAF_POS) -#define AUDIO_ADC1_ICTRL_AAF_UMSK (~(((1U << AUDIO_ADC1_ICTRL_AAF_LEN) - 1) << AUDIO_ADC1_ICTRL_AAF_POS)) -#define AUDIO_ADC1_EN_SDM AUDIO_ADC1_EN_SDM -#define AUDIO_ADC1_EN_SDM_POS (20U) -#define AUDIO_ADC1_EN_SDM_LEN (1U) -#define AUDIO_ADC1_EN_SDM_MSK (((1U << AUDIO_ADC1_EN_SDM_LEN) - 1) << AUDIO_ADC1_EN_SDM_POS) -#define AUDIO_ADC1_EN_SDM_UMSK (~(((1U << AUDIO_ADC1_EN_SDM_LEN) - 1) << AUDIO_ADC1_EN_SDM_POS)) -#define AUDIO_ADC1_EN_PGA AUDIO_ADC1_EN_PGA -#define AUDIO_ADC1_EN_PGA_POS (21U) -#define AUDIO_ADC1_EN_PGA_LEN (1U) -#define AUDIO_ADC1_EN_PGA_MSK (((1U << AUDIO_ADC1_EN_PGA_LEN) - 1) << AUDIO_ADC1_EN_PGA_POS) -#define AUDIO_ADC1_EN_PGA_UMSK (~(((1U << AUDIO_ADC1_EN_PGA_LEN) - 1) << AUDIO_ADC1_EN_PGA_POS)) - -/* 0x718 : codec_adc2 */ -#define AUDIO_CODEC_ADC2_OFFSET (0x718) -#define AUDIO_ADC2_SDM_LP AUDIO_ADC2_SDM_LP -#define AUDIO_ADC2_SDM_LP_POS (0U) -#define AUDIO_ADC2_SDM_LP_LEN (1U) -#define AUDIO_ADC2_SDM_LP_MSK (((1U << AUDIO_ADC2_SDM_LP_LEN) - 1) << AUDIO_ADC2_SDM_LP_POS) -#define AUDIO_ADC2_SDM_LP_UMSK (~(((1U << AUDIO_ADC2_SDM_LP_LEN) - 1) << AUDIO_ADC2_SDM_LP_POS)) -#define AUDIO_ADC2_CKB_EN AUDIO_ADC2_CKB_EN -#define AUDIO_ADC2_CKB_EN_POS (1U) -#define AUDIO_ADC2_CKB_EN_LEN (1U) -#define AUDIO_ADC2_CKB_EN_MSK (((1U << AUDIO_ADC2_CKB_EN_LEN) - 1) << AUDIO_ADC2_CKB_EN_POS) -#define AUDIO_ADC2_CKB_EN_UMSK (~(((1U << AUDIO_ADC2_CKB_EN_LEN) - 1) << AUDIO_ADC2_CKB_EN_POS)) -#define AUDIO_ADC2_REG_RESEV AUDIO_ADC2_REG_RESEV -#define AUDIO_ADC2_REG_RESEV_POS (2U) -#define AUDIO_ADC2_REG_RESEV_LEN (1U) -#define AUDIO_ADC2_REG_RESEV_MSK (((1U << AUDIO_ADC2_REG_RESEV_LEN) - 1) << AUDIO_ADC2_REG_RESEV_POS) -#define AUDIO_ADC2_REG_RESEV_UMSK (~(((1U << AUDIO_ADC2_REG_RESEV_LEN) - 1) << AUDIO_ADC2_REG_RESEV_POS)) -#define AUDIO_ADC2_PGA_RCM_SEL AUDIO_ADC2_PGA_RCM_SEL -#define AUDIO_ADC2_PGA_RCM_SEL_POS (4U) -#define AUDIO_ADC2_PGA_RCM_SEL_LEN (2U) -#define AUDIO_ADC2_PGA_RCM_SEL_MSK (((1U << AUDIO_ADC2_PGA_RCM_SEL_LEN) - 1) << AUDIO_ADC2_PGA_RCM_SEL_POS) -#define AUDIO_ADC2_PGA_RCM_SEL_UMSK (~(((1U << AUDIO_ADC2_PGA_RCM_SEL_LEN) - 1) << AUDIO_ADC2_PGA_RCM_SEL_POS)) -#define AUDIO_ADC2_PGA_GAIN AUDIO_ADC2_PGA_GAIN -#define AUDIO_ADC2_PGA_GAIN_POS (8U) -#define AUDIO_ADC2_PGA_GAIN_LEN (4U) -#define AUDIO_ADC2_PGA_GAIN_MSK (((1U << AUDIO_ADC2_PGA_GAIN_LEN) - 1) << AUDIO_ADC2_PGA_GAIN_POS) -#define AUDIO_ADC2_PGA_GAIN_UMSK (~(((1U << AUDIO_ADC2_PGA_GAIN_LEN) - 1) << AUDIO_ADC2_PGA_GAIN_POS)) -#define AUDIO_ADC2_ICTRL_MIC AUDIO_ADC2_ICTRL_MIC -#define AUDIO_ADC2_ICTRL_MIC_POS (12U) -#define AUDIO_ADC2_ICTRL_MIC_LEN (2U) -#define AUDIO_ADC2_ICTRL_MIC_MSK (((1U << AUDIO_ADC2_ICTRL_MIC_LEN) - 1) << AUDIO_ADC2_ICTRL_MIC_POS) -#define AUDIO_ADC2_ICTRL_MIC_UMSK (~(((1U << AUDIO_ADC2_ICTRL_MIC_LEN) - 1) << AUDIO_ADC2_ICTRL_MIC_POS)) -#define AUDIO_ADC2_ICTRL_ADC2 AUDIO_ADC2_ICTRL_ADC2 -#define AUDIO_ADC2_ICTRL_ADC2_POS (14U) -#define AUDIO_ADC2_ICTRL_ADC2_LEN (2U) -#define AUDIO_ADC2_ICTRL_ADC2_MSK (((1U << AUDIO_ADC2_ICTRL_ADC2_LEN) - 1) << AUDIO_ADC2_ICTRL_ADC2_POS) -#define AUDIO_ADC2_ICTRL_ADC2_UMSK (~(((1U << AUDIO_ADC2_ICTRL_ADC2_LEN) - 1) << AUDIO_ADC2_ICTRL_ADC2_POS)) -#define AUDIO_ADC2_ICTRL_ADC1 AUDIO_ADC2_ICTRL_ADC1 -#define AUDIO_ADC2_ICTRL_ADC1_POS (16U) -#define AUDIO_ADC2_ICTRL_ADC1_LEN (2U) -#define AUDIO_ADC2_ICTRL_ADC1_MSK (((1U << AUDIO_ADC2_ICTRL_ADC1_LEN) - 1) << AUDIO_ADC2_ICTRL_ADC1_POS) -#define AUDIO_ADC2_ICTRL_ADC1_UMSK (~(((1U << AUDIO_ADC2_ICTRL_ADC1_LEN) - 1) << AUDIO_ADC2_ICTRL_ADC1_POS)) -#define AUDIO_ADC2_ICTRL_AAF AUDIO_ADC2_ICTRL_AAF -#define AUDIO_ADC2_ICTRL_AAF_POS (18U) -#define AUDIO_ADC2_ICTRL_AAF_LEN (2U) -#define AUDIO_ADC2_ICTRL_AAF_MSK (((1U << AUDIO_ADC2_ICTRL_AAF_LEN) - 1) << AUDIO_ADC2_ICTRL_AAF_POS) -#define AUDIO_ADC2_ICTRL_AAF_UMSK (~(((1U << AUDIO_ADC2_ICTRL_AAF_LEN) - 1) << AUDIO_ADC2_ICTRL_AAF_POS)) -#define AUDIO_ADC2_EN_SDM AUDIO_ADC2_EN_SDM -#define AUDIO_ADC2_EN_SDM_POS (20U) -#define AUDIO_ADC2_EN_SDM_LEN (1U) -#define AUDIO_ADC2_EN_SDM_MSK (((1U << AUDIO_ADC2_EN_SDM_LEN) - 1) << AUDIO_ADC2_EN_SDM_POS) -#define AUDIO_ADC2_EN_SDM_UMSK (~(((1U << AUDIO_ADC2_EN_SDM_LEN) - 1) << AUDIO_ADC2_EN_SDM_POS)) -#define AUDIO_ADC2_EN_PGA AUDIO_ADC2_EN_PGA -#define AUDIO_ADC2_EN_PGA_POS (21U) -#define AUDIO_ADC2_EN_PGA_LEN (1U) -#define AUDIO_ADC2_EN_PGA_MSK (((1U << AUDIO_ADC2_EN_PGA_LEN) - 1) << AUDIO_ADC2_EN_PGA_POS) -#define AUDIO_ADC2_EN_PGA_UMSK (~(((1U << AUDIO_ADC2_EN_PGA_LEN) - 1) << AUDIO_ADC2_EN_PGA_POS)) - -/* 0x800 : padc_ana_cfg1 */ -#define AUDIO_PADC_ANA_CFG1_OFFSET (0x800) -#define AUDIO_PADC_PGA_CHOP_CKSEL AUDIO_PADC_PGA_CHOP_CKSEL -#define AUDIO_PADC_PGA_CHOP_CKSEL_POS (0U) -#define AUDIO_PADC_PGA_CHOP_CKSEL_LEN (1U) -#define AUDIO_PADC_PGA_CHOP_CKSEL_MSK (((1U << AUDIO_PADC_PGA_CHOP_CKSEL_LEN) - 1) << AUDIO_PADC_PGA_CHOP_CKSEL_POS) -#define AUDIO_PADC_PGA_CHOP_CKSEL_UMSK (~(((1U << AUDIO_PADC_PGA_CHOP_CKSEL_LEN) - 1) << AUDIO_PADC_PGA_CHOP_CKSEL_POS)) -#define AUDIO_PADC_PGA_CHOP_FREQ AUDIO_PADC_PGA_CHOP_FREQ -#define AUDIO_PADC_PGA_CHOP_FREQ_POS (1U) -#define AUDIO_PADC_PGA_CHOP_FREQ_LEN (3U) -#define AUDIO_PADC_PGA_CHOP_FREQ_MSK (((1U << AUDIO_PADC_PGA_CHOP_FREQ_LEN) - 1) << AUDIO_PADC_PGA_CHOP_FREQ_POS) -#define AUDIO_PADC_PGA_CHOP_FREQ_UMSK (~(((1U << AUDIO_PADC_PGA_CHOP_FREQ_LEN) - 1) << AUDIO_PADC_PGA_CHOP_FREQ_POS)) -#define AUDIO_PADC_PGA_CHOP_EN AUDIO_PADC_PGA_CHOP_EN -#define AUDIO_PADC_PGA_CHOP_EN_POS (4U) -#define AUDIO_PADC_PGA_CHOP_EN_LEN (1U) -#define AUDIO_PADC_PGA_CHOP_EN_MSK (((1U << AUDIO_PADC_PGA_CHOP_EN_LEN) - 1) << AUDIO_PADC_PGA_CHOP_EN_POS) -#define AUDIO_PADC_PGA_CHOP_EN_UMSK (~(((1U << AUDIO_PADC_PGA_CHOP_EN_LEN) - 1) << AUDIO_PADC_PGA_CHOP_EN_POS)) -#define AUDIO_PADC_PGA_NOISCTRL AUDIO_PADC_PGA_NOISCTRL -#define AUDIO_PADC_PGA_NOISCTRL_POS (5U) -#define AUDIO_PADC_PGA_NOISCTRL_LEN (2U) -#define AUDIO_PADC_PGA_NOISCTRL_MSK (((1U << AUDIO_PADC_PGA_NOISCTRL_LEN) - 1) << AUDIO_PADC_PGA_NOISCTRL_POS) -#define AUDIO_PADC_PGA_NOISCTRL_UMSK (~(((1U << AUDIO_PADC_PGA_NOISCTRL_LEN) - 1) << AUDIO_PADC_PGA_NOISCTRL_POS)) -#define AUDIO_PADC_ICTRL_PGA_BUF AUDIO_PADC_ICTRL_PGA_BUF -#define AUDIO_PADC_ICTRL_PGA_BUF_POS (7U) -#define AUDIO_PADC_ICTRL_PGA_BUF_LEN (2U) -#define AUDIO_PADC_ICTRL_PGA_BUF_MSK (((1U << AUDIO_PADC_ICTRL_PGA_BUF_LEN) - 1) << AUDIO_PADC_ICTRL_PGA_BUF_POS) -#define AUDIO_PADC_ICTRL_PGA_BUF_UMSK (~(((1U << AUDIO_PADC_ICTRL_PGA_BUF_LEN) - 1) << AUDIO_PADC_ICTRL_PGA_BUF_POS)) -#define AUDIO_PADC_ICTRL_PGA_IA AUDIO_PADC_ICTRL_PGA_IA -#define AUDIO_PADC_ICTRL_PGA_IA_POS (9U) -#define AUDIO_PADC_ICTRL_PGA_IA_LEN (2U) -#define AUDIO_PADC_ICTRL_PGA_IA_MSK (((1U << AUDIO_PADC_ICTRL_PGA_IA_LEN) - 1) << AUDIO_PADC_ICTRL_PGA_IA_POS) -#define AUDIO_PADC_ICTRL_PGA_IA_UMSK (~(((1U << AUDIO_PADC_ICTRL_PGA_IA_LEN) - 1) << AUDIO_PADC_ICTRL_PGA_IA_POS)) -#define AUDIO_PADC_PGA_FORCE AUDIO_PADC_PGA_FORCE -#define AUDIO_PADC_PGA_FORCE_POS (11U) -#define AUDIO_PADC_PGA_FORCE_LEN (1U) -#define AUDIO_PADC_PGA_FORCE_MSK (((1U << AUDIO_PADC_PGA_FORCE_LEN) - 1) << AUDIO_PADC_PGA_FORCE_POS) -#define AUDIO_PADC_PGA_FORCE_UMSK (~(((1U << AUDIO_PADC_PGA_FORCE_LEN) - 1) << AUDIO_PADC_PGA_FORCE_POS)) -#define AUDIO_PADC_PGA_AUTOBPS_BUF AUDIO_PADC_PGA_AUTOBPS_BUF -#define AUDIO_PADC_PGA_AUTOBPS_BUF_POS (12U) -#define AUDIO_PADC_PGA_AUTOBPS_BUF_LEN (1U) -#define AUDIO_PADC_PGA_AUTOBPS_BUF_MSK (((1U << AUDIO_PADC_PGA_AUTOBPS_BUF_LEN) - 1) << AUDIO_PADC_PGA_AUTOBPS_BUF_POS) -#define AUDIO_PADC_PGA_AUTOBPS_BUF_UMSK (~(((1U << AUDIO_PADC_PGA_AUTOBPS_BUF_LEN) - 1) << AUDIO_PADC_PGA_AUTOBPS_BUF_POS)) -#define AUDIO_PADC_PGA_AUTOBPS_IA AUDIO_PADC_PGA_AUTOBPS_IA -#define AUDIO_PADC_PGA_AUTOBPS_IA_POS (13U) -#define AUDIO_PADC_PGA_AUTOBPS_IA_LEN (1U) -#define AUDIO_PADC_PGA_AUTOBPS_IA_MSK (((1U << AUDIO_PADC_PGA_AUTOBPS_IA_LEN) - 1) << AUDIO_PADC_PGA_AUTOBPS_IA_POS) -#define AUDIO_PADC_PGA_AUTOBPS_IA_UMSK (~(((1U << AUDIO_PADC_PGA_AUTOBPS_IA_LEN) - 1) << AUDIO_PADC_PGA_AUTOBPS_IA_POS)) -#define AUDIO_PADC_PGA_MODE AUDIO_PADC_PGA_MODE -#define AUDIO_PADC_PGA_MODE_POS (14U) -#define AUDIO_PADC_PGA_MODE_LEN (2U) -#define AUDIO_PADC_PGA_MODE_MSK (((1U << AUDIO_PADC_PGA_MODE_LEN) - 1) << AUDIO_PADC_PGA_MODE_POS) -#define AUDIO_PADC_PGA_MODE_UMSK (~(((1U << AUDIO_PADC_PGA_MODE_LEN) - 1) << AUDIO_PADC_PGA_MODE_POS)) -#define AUDIO_PADC_AFEVCM_ROUT AUDIO_PADC_AFEVCM_ROUT -#define AUDIO_PADC_AFEVCM_ROUT_POS (16U) -#define AUDIO_PADC_AFEVCM_ROUT_LEN (2U) -#define AUDIO_PADC_AFEVCM_ROUT_MSK (((1U << AUDIO_PADC_AFEVCM_ROUT_LEN) - 1) << AUDIO_PADC_AFEVCM_ROUT_POS) -#define AUDIO_PADC_AFEVCM_ROUT_UMSK (~(((1U << AUDIO_PADC_AFEVCM_ROUT_LEN) - 1) << AUDIO_PADC_AFEVCM_ROUT_POS)) -#define AUDIO_PADC_AFEVCM_SEL AUDIO_PADC_AFEVCM_SEL -#define AUDIO_PADC_AFEVCM_SEL_POS (18U) -#define AUDIO_PADC_AFEVCM_SEL_LEN (1U) -#define AUDIO_PADC_AFEVCM_SEL_MSK (((1U << AUDIO_PADC_AFEVCM_SEL_LEN) - 1) << AUDIO_PADC_AFEVCM_SEL_POS) -#define AUDIO_PADC_AFEVCM_SEL_UMSK (~(((1U << AUDIO_PADC_AFEVCM_SEL_LEN) - 1) << AUDIO_PADC_AFEVCM_SEL_POS)) -#define AUDIO_PADC_CKB_EN AUDIO_PADC_CKB_EN -#define AUDIO_PADC_CKB_EN_POS (19U) -#define AUDIO_PADC_CKB_EN_LEN (1U) -#define AUDIO_PADC_CKB_EN_MSK (((1U << AUDIO_PADC_CKB_EN_LEN) - 1) << AUDIO_PADC_CKB_EN_POS) -#define AUDIO_PADC_CKB_EN_UMSK (~(((1U << AUDIO_PADC_CKB_EN_LEN) - 1) << AUDIO_PADC_CKB_EN_POS)) -#define AUDIO_PADC_SEL_EDGE AUDIO_PADC_SEL_EDGE -#define AUDIO_PADC_SEL_EDGE_POS (20U) -#define AUDIO_PADC_SEL_EDGE_LEN (1U) -#define AUDIO_PADC_SEL_EDGE_MSK (((1U << AUDIO_PADC_SEL_EDGE_LEN) - 1) << AUDIO_PADC_SEL_EDGE_POS) -#define AUDIO_PADC_SEL_EDGE_UMSK (~(((1U << AUDIO_PADC_SEL_EDGE_LEN) - 1) << AUDIO_PADC_SEL_EDGE_POS)) - -/* 0x804 : padc_ana_cfg2 */ -#define AUDIO_PADC_ANA_CFG2_OFFSET (0x804) -#define AUDIO_PADC_SDM_CHOP_PHAS AUDIO_PADC_SDM_CHOP_PHAS -#define AUDIO_PADC_SDM_CHOP_PHAS_POS (0U) -#define AUDIO_PADC_SDM_CHOP_PHAS_LEN (1U) -#define AUDIO_PADC_SDM_CHOP_PHAS_MSK (((1U << AUDIO_PADC_SDM_CHOP_PHAS_LEN) - 1) << AUDIO_PADC_SDM_CHOP_PHAS_POS) -#define AUDIO_PADC_SDM_CHOP_PHAS_UMSK (~(((1U << AUDIO_PADC_SDM_CHOP_PHAS_LEN) - 1) << AUDIO_PADC_SDM_CHOP_PHAS_POS)) -#define AUDIO_PADC_SDM_CHOP_FREQ AUDIO_PADC_SDM_CHOP_FREQ -#define AUDIO_PADC_SDM_CHOP_FREQ_POS (1U) -#define AUDIO_PADC_SDM_CHOP_FREQ_LEN (3U) -#define AUDIO_PADC_SDM_CHOP_FREQ_MSK (((1U << AUDIO_PADC_SDM_CHOP_FREQ_LEN) - 1) << AUDIO_PADC_SDM_CHOP_FREQ_POS) -#define AUDIO_PADC_SDM_CHOP_FREQ_UMSK (~(((1U << AUDIO_PADC_SDM_CHOP_FREQ_LEN) - 1) << AUDIO_PADC_SDM_CHOP_FREQ_POS)) -#define AUDIO_PADC_SDM_CHOP_EN AUDIO_PADC_SDM_CHOP_EN -#define AUDIO_PADC_SDM_CHOP_EN_POS (4U) -#define AUDIO_PADC_SDM_CHOP_EN_LEN (1U) -#define AUDIO_PADC_SDM_CHOP_EN_MSK (((1U << AUDIO_PADC_SDM_CHOP_EN_LEN) - 1) << AUDIO_PADC_SDM_CHOP_EN_POS) -#define AUDIO_PADC_SDM_CHOP_EN_UMSK (~(((1U << AUDIO_PADC_SDM_CHOP_EN_LEN) - 1) << AUDIO_PADC_SDM_CHOP_EN_POS)) -#define AUDIO_PADC_DITHER_ORDER AUDIO_PADC_DITHER_ORDER -#define AUDIO_PADC_DITHER_ORDER_POS (5U) -#define AUDIO_PADC_DITHER_ORDER_LEN (1U) -#define AUDIO_PADC_DITHER_ORDER_MSK (((1U << AUDIO_PADC_DITHER_ORDER_LEN) - 1) << AUDIO_PADC_DITHER_ORDER_POS) -#define AUDIO_PADC_DITHER_ORDER_UMSK (~(((1U << AUDIO_PADC_DITHER_ORDER_LEN) - 1) << AUDIO_PADC_DITHER_ORDER_POS)) -#define AUDIO_PADC_DITHER_SEL AUDIO_PADC_DITHER_SEL -#define AUDIO_PADC_DITHER_SEL_POS (6U) -#define AUDIO_PADC_DITHER_SEL_LEN (2U) -#define AUDIO_PADC_DITHER_SEL_MSK (((1U << AUDIO_PADC_DITHER_SEL_LEN) - 1) << AUDIO_PADC_DITHER_SEL_POS) -#define AUDIO_PADC_DITHER_SEL_UMSK (~(((1U << AUDIO_PADC_DITHER_SEL_LEN) - 1) << AUDIO_PADC_DITHER_SEL_POS)) -#define AUDIO_PADC_QUAN_GAIN AUDIO_PADC_QUAN_GAIN -#define AUDIO_PADC_QUAN_GAIN_POS (8U) -#define AUDIO_PADC_QUAN_GAIN_LEN (2U) -#define AUDIO_PADC_QUAN_GAIN_MSK (((1U << AUDIO_PADC_QUAN_GAIN_LEN) - 1) << AUDIO_PADC_QUAN_GAIN_POS) -#define AUDIO_PADC_QUAN_GAIN_UMSK (~(((1U << AUDIO_PADC_QUAN_GAIN_LEN) - 1) << AUDIO_PADC_QUAN_GAIN_POS)) -#define AUDIO_PADC_DEM_EN AUDIO_PADC_DEM_EN -#define AUDIO_PADC_DEM_EN_POS (10U) -#define AUDIO_PADC_DEM_EN_LEN (1U) -#define AUDIO_PADC_DEM_EN_MSK (((1U << AUDIO_PADC_DEM_EN_LEN) - 1) << AUDIO_PADC_DEM_EN_POS) -#define AUDIO_PADC_DEM_EN_UMSK (~(((1U << AUDIO_PADC_DEM_EN_LEN) - 1) << AUDIO_PADC_DEM_EN_POS)) -#define AUDIO_PADC_NCTRL_ADC2 AUDIO_PADC_NCTRL_ADC2 -#define AUDIO_PADC_NCTRL_ADC2_POS (11U) -#define AUDIO_PADC_NCTRL_ADC2_LEN (1U) -#define AUDIO_PADC_NCTRL_ADC2_MSK (((1U << AUDIO_PADC_NCTRL_ADC2_LEN) - 1) << AUDIO_PADC_NCTRL_ADC2_POS) -#define AUDIO_PADC_NCTRL_ADC2_UMSK (~(((1U << AUDIO_PADC_NCTRL_ADC2_LEN) - 1) << AUDIO_PADC_NCTRL_ADC2_POS)) -#define AUDIO_PADC_NCTRL_ADC1 AUDIO_PADC_NCTRL_ADC1 -#define AUDIO_PADC_NCTRL_ADC1_POS (13U) -#define AUDIO_PADC_NCTRL_ADC1_LEN (2U) -#define AUDIO_PADC_NCTRL_ADC1_MSK (((1U << AUDIO_PADC_NCTRL_ADC1_LEN) - 1) << AUDIO_PADC_NCTRL_ADC1_POS) -#define AUDIO_PADC_NCTRL_ADC1_UMSK (~(((1U << AUDIO_PADC_NCTRL_ADC1_LEN) - 1) << AUDIO_PADC_NCTRL_ADC1_POS)) -#define AUDIO_PADC_ICTRL_ADC AUDIO_PADC_ICTRL_ADC -#define AUDIO_PADC_ICTRL_ADC_POS (15U) -#define AUDIO_PADC_ICTRL_ADC_LEN (2U) -#define AUDIO_PADC_ICTRL_ADC_MSK (((1U << AUDIO_PADC_ICTRL_ADC_LEN) - 1) << AUDIO_PADC_ICTRL_ADC_POS) -#define AUDIO_PADC_ICTRL_ADC_UMSK (~(((1U << AUDIO_PADC_ICTRL_ADC_LEN) - 1) << AUDIO_PADC_ICTRL_ADC_POS)) -#define AUDIO_PADC_RESERVED AUDIO_PADC_RESERVED -#define AUDIO_PADC_RESERVED_POS (17U) -#define AUDIO_PADC_RESERVED_LEN (4U) -#define AUDIO_PADC_RESERVED_MSK (((1U << AUDIO_PADC_RESERVED_LEN) - 1) << AUDIO_PADC_RESERVED_POS) -#define AUDIO_PADC_RESERVED_UMSK (~(((1U << AUDIO_PADC_RESERVED_LEN) - 1) << AUDIO_PADC_RESERVED_POS)) - -/* 0x808 : padc_ana_cmd */ -#define AUDIO_PADC_ANA_CMD_OFFSET (0x808) -#define AUDIO_PADC_SELF_TEST_EN AUDIO_PADC_SELF_TEST_EN -#define AUDIO_PADC_SELF_TEST_EN_POS (2U) -#define AUDIO_PADC_SELF_TEST_EN_LEN (1U) -#define AUDIO_PADC_SELF_TEST_EN_MSK (((1U << AUDIO_PADC_SELF_TEST_EN_LEN) - 1) << AUDIO_PADC_SELF_TEST_EN_POS) -#define AUDIO_PADC_SELF_TEST_EN_UMSK (~(((1U << AUDIO_PADC_SELF_TEST_EN_LEN) - 1) << AUDIO_PADC_SELF_TEST_EN_POS)) -#define AUDIO_PADC_SDM_LP_EN AUDIO_PADC_SDM_LP_EN -#define AUDIO_PADC_SDM_LP_EN_POS (3U) -#define AUDIO_PADC_SDM_LP_EN_LEN (1U) -#define AUDIO_PADC_SDM_LP_EN_MSK (((1U << AUDIO_PADC_SDM_LP_EN_LEN) - 1) << AUDIO_PADC_SDM_LP_EN_POS) -#define AUDIO_PADC_SDM_LP_EN_UMSK (~(((1U << AUDIO_PADC_SDM_LP_EN_LEN) - 1) << AUDIO_PADC_SDM_LP_EN_POS)) -#define AUDIO_PADC_PGA_LP_EN AUDIO_PADC_PGA_LP_EN -#define AUDIO_PADC_PGA_LP_EN_POS (4U) -#define AUDIO_PADC_PGA_LP_EN_LEN (1U) -#define AUDIO_PADC_PGA_LP_EN_MSK (((1U << AUDIO_PADC_PGA_LP_EN_LEN) - 1) << AUDIO_PADC_PGA_LP_EN_POS) -#define AUDIO_PADC_PGA_LP_EN_UMSK (~(((1U << AUDIO_PADC_PGA_LP_EN_LEN) - 1) << AUDIO_PADC_PGA_LP_EN_POS)) -#define AUDIO_PADC_DIAG_GSW AUDIO_PADC_DIAG_GSW -#define AUDIO_PADC_DIAG_GSW_POS (5U) -#define AUDIO_PADC_DIAG_GSW_LEN (2U) -#define AUDIO_PADC_DIAG_GSW_MSK (((1U << AUDIO_PADC_DIAG_GSW_LEN) - 1) << AUDIO_PADC_DIAG_GSW_POS) -#define AUDIO_PADC_DIAG_GSW_UMSK (~(((1U << AUDIO_PADC_DIAG_GSW_LEN) - 1) << AUDIO_PADC_DIAG_GSW_POS)) -#define AUDIO_PADC_DIAG_PSW AUDIO_PADC_DIAG_PSW -#define AUDIO_PADC_DIAG_PSW_POS (7U) -#define AUDIO_PADC_DIAG_PSW_LEN (2U) -#define AUDIO_PADC_DIAG_PSW_MSK (((1U << AUDIO_PADC_DIAG_PSW_LEN) - 1) << AUDIO_PADC_DIAG_PSW_POS) -#define AUDIO_PADC_DIAG_PSW_UMSK (~(((1U << AUDIO_PADC_DIAG_PSW_LEN) - 1) << AUDIO_PADC_DIAG_PSW_POS)) -#define AUDIO_PADC_ICTRL_DIAG AUDIO_PADC_ICTRL_DIAG -#define AUDIO_PADC_ICTRL_DIAG_POS (9U) -#define AUDIO_PADC_ICTRL_DIAG_LEN (2U) -#define AUDIO_PADC_ICTRL_DIAG_MSK (((1U << AUDIO_PADC_ICTRL_DIAG_LEN) - 1) << AUDIO_PADC_ICTRL_DIAG_POS) -#define AUDIO_PADC_ICTRL_DIAG_UMSK (~(((1U << AUDIO_PADC_ICTRL_DIAG_LEN) - 1) << AUDIO_PADC_ICTRL_DIAG_POS)) -#define AUDIO_PADC_PGA_GAIN AUDIO_PADC_PGA_GAIN -#define AUDIO_PADC_PGA_GAIN_POS (11U) -#define AUDIO_PADC_PGA_GAIN_LEN (3U) -#define AUDIO_PADC_PGA_GAIN_MSK (((1U << AUDIO_PADC_PGA_GAIN_LEN) - 1) << AUDIO_PADC_PGA_GAIN_POS) -#define AUDIO_PADC_PGA_GAIN_UMSK (~(((1U << AUDIO_PADC_PGA_GAIN_LEN) - 1) << AUDIO_PADC_PGA_GAIN_POS)) -#define AUDIO_PADC_INV_SIG AUDIO_PADC_INV_SIG -#define AUDIO_PADC_INV_SIG_POS (14U) -#define AUDIO_PADC_INV_SIG_LEN (1U) -#define AUDIO_PADC_INV_SIG_MSK (((1U << AUDIO_PADC_INV_SIG_LEN) - 1) << AUDIO_PADC_INV_SIG_POS) -#define AUDIO_PADC_INV_SIG_UMSK (~(((1U << AUDIO_PADC_INV_SIG_LEN) - 1) << AUDIO_PADC_INV_SIG_POS)) -#define AUDIO_PADC_SINGLE_MODE AUDIO_PADC_SINGLE_MODE -#define AUDIO_PADC_SINGLE_MODE_POS (15U) -#define AUDIO_PADC_SINGLE_MODE_LEN (2U) -#define AUDIO_PADC_SINGLE_MODE_MSK (((1U << AUDIO_PADC_SINGLE_MODE_LEN) - 1) << AUDIO_PADC_SINGLE_MODE_POS) -#define AUDIO_PADC_SINGLE_MODE_UMSK (~(((1U << AUDIO_PADC_SINGLE_MODE_LEN) - 1) << AUDIO_PADC_SINGLE_MODE_POS)) -#define AUDIO_PADC_SINGLE_CFG AUDIO_PADC_SINGLE_CFG -#define AUDIO_PADC_SINGLE_CFG_POS (17U) -#define AUDIO_PADC_SINGLE_CFG_LEN (4U) -#define AUDIO_PADC_SINGLE_CFG_MSK (((1U << AUDIO_PADC_SINGLE_CFG_LEN) - 1) << AUDIO_PADC_SINGLE_CFG_POS) -#define AUDIO_PADC_SINGLE_CFG_UMSK (~(((1U << AUDIO_PADC_SINGLE_CFG_LEN) - 1) << AUDIO_PADC_SINGLE_CFG_POS)) -#define AUDIO_PADC_CHANNEL_SEL AUDIO_PADC_CHANNEL_SEL -#define AUDIO_PADC_CHANNEL_SEL_POS (21U) -#define AUDIO_PADC_CHANNEL_SEL_LEN (2U) -#define AUDIO_PADC_CHANNEL_SEL_MSK (((1U << AUDIO_PADC_CHANNEL_SEL_LEN) - 1) << AUDIO_PADC_CHANNEL_SEL_POS) -#define AUDIO_PADC_CHANNEL_SEL_UMSK (~(((1U << AUDIO_PADC_CHANNEL_SEL_LEN) - 1) << AUDIO_PADC_CHANNEL_SEL_POS)) -#define AUDIO_PADC_CHANNEL_EN AUDIO_PADC_CHANNEL_EN -#define AUDIO_PADC_CHANNEL_EN_POS (23U) -#define AUDIO_PADC_CHANNEL_EN_LEN (1U) -#define AUDIO_PADC_CHANNEL_EN_MSK (((1U << AUDIO_PADC_CHANNEL_EN_LEN) - 1) << AUDIO_PADC_CHANNEL_EN_POS) -#define AUDIO_PADC_CHANNEL_EN_UMSK (~(((1U << AUDIO_PADC_CHANNEL_EN_LEN) - 1) << AUDIO_PADC_CHANNEL_EN_POS)) -#define AUDIO_PADC_CONV_DELAY AUDIO_PADC_CONV_DELAY -#define AUDIO_PADC_CONV_DELAY_POS (24U) -#define AUDIO_PADC_CONV_DELAY_LEN (4U) -#define AUDIO_PADC_CONV_DELAY_MSK (((1U << AUDIO_PADC_CONV_DELAY_LEN) - 1) << AUDIO_PADC_CONV_DELAY_POS) -#define AUDIO_PADC_CONV_DELAY_UMSK (~(((1U << AUDIO_PADC_CONV_DELAY_LEN) - 1) << AUDIO_PADC_CONV_DELAY_POS)) -#define AUDIO_PADC_CONV AUDIO_PADC_CONV -#define AUDIO_PADC_CONV_POS (28U) -#define AUDIO_PADC_CONV_LEN (1U) -#define AUDIO_PADC_CONV_MSK (((1U << AUDIO_PADC_CONV_LEN) - 1) << AUDIO_PADC_CONV_POS) -#define AUDIO_PADC_CONV_UMSK (~(((1U << AUDIO_PADC_CONV_LEN) - 1) << AUDIO_PADC_CONV_POS)) -#define AUDIO_PADC_EN_CALDAC AUDIO_PADC_EN_CALDAC -#define AUDIO_PADC_EN_CALDAC_POS (29U) -#define AUDIO_PADC_EN_CALDAC_LEN (1U) -#define AUDIO_PADC_EN_CALDAC_MSK (((1U << AUDIO_PADC_EN_CALDAC_LEN) - 1) << AUDIO_PADC_EN_CALDAC_POS) -#define AUDIO_PADC_EN_CALDAC_UMSK (~(((1U << AUDIO_PADC_EN_CALDAC_LEN) - 1) << AUDIO_PADC_EN_CALDAC_POS)) -#define AUDIO_PADC_SDM_PU AUDIO_PADC_SDM_PU -#define AUDIO_PADC_SDM_PU_POS (30U) -#define AUDIO_PADC_SDM_PU_LEN (1U) -#define AUDIO_PADC_SDM_PU_MSK (((1U << AUDIO_PADC_SDM_PU_LEN) - 1) << AUDIO_PADC_SDM_PU_POS) -#define AUDIO_PADC_SDM_PU_UMSK (~(((1U << AUDIO_PADC_SDM_PU_LEN) - 1) << AUDIO_PADC_SDM_PU_POS)) -#define AUDIO_PADC_PGA_PU AUDIO_PADC_PGA_PU -#define AUDIO_PADC_PGA_PU_POS (31U) -#define AUDIO_PADC_PGA_PU_LEN (1U) -#define AUDIO_PADC_PGA_PU_MSK (((1U << AUDIO_PADC_PGA_PU_LEN) - 1) << AUDIO_PADC_PGA_PU_POS) -#define AUDIO_PADC_PGA_PU_UMSK (~(((1U << AUDIO_PADC_PGA_PU_LEN) - 1) << AUDIO_PADC_PGA_PU_POS)) - -/* 0x80C : padc_out_cfg */ -#define AUDIO_PADC_OUT_CFG_OFFSET (0x80C) -#define AUDIO_PADC_VALID_4S_VAL AUDIO_PADC_VALID_4S_VAL -#define AUDIO_PADC_VALID_4S_VAL_POS (21U) -#define AUDIO_PADC_VALID_4S_VAL_LEN (1U) -#define AUDIO_PADC_VALID_4S_VAL_MSK (((1U << AUDIO_PADC_VALID_4S_VAL_LEN) - 1) << AUDIO_PADC_VALID_4S_VAL_POS) -#define AUDIO_PADC_VALID_4S_VAL_UMSK (~(((1U << AUDIO_PADC_VALID_4S_VAL_LEN) - 1) << AUDIO_PADC_VALID_4S_VAL_POS)) -#define AUDIO_PADC_VALID_4S_EN AUDIO_PADC_VALID_4S_EN -#define AUDIO_PADC_VALID_4S_EN_POS (22U) -#define AUDIO_PADC_VALID_4S_EN_LEN (1U) -#define AUDIO_PADC_VALID_4S_EN_MSK (((1U << AUDIO_PADC_VALID_4S_EN_LEN) - 1) << AUDIO_PADC_VALID_4S_EN_POS) -#define AUDIO_PADC_VALID_4S_EN_UMSK (~(((1U << AUDIO_PADC_VALID_4S_EN_LEN) - 1) << AUDIO_PADC_VALID_4S_EN_POS)) -#define AUDIO_PADC_GLOBAL_CHOP_EN AUDIO_PADC_GLOBAL_CHOP_EN -#define AUDIO_PADC_GLOBAL_CHOP_EN_POS (23U) -#define AUDIO_PADC_GLOBAL_CHOP_EN_LEN (1U) -#define AUDIO_PADC_GLOBAL_CHOP_EN_MSK (((1U << AUDIO_PADC_GLOBAL_CHOP_EN_LEN) - 1) << AUDIO_PADC_GLOBAL_CHOP_EN_POS) -#define AUDIO_PADC_GLOBAL_CHOP_EN_UMSK (~(((1U << AUDIO_PADC_GLOBAL_CHOP_EN_LEN) - 1) << AUDIO_PADC_GLOBAL_CHOP_EN_POS)) -#define AUDIO_PADC_FILTER_TYPE AUDIO_PADC_FILTER_TYPE -#define AUDIO_PADC_FILTER_TYPE_POS (24U) -#define AUDIO_PADC_FILTER_TYPE_LEN (1U) -#define AUDIO_PADC_FILTER_TYPE_MSK (((1U << AUDIO_PADC_FILTER_TYPE_LEN) - 1) << AUDIO_PADC_FILTER_TYPE_POS) -#define AUDIO_PADC_FILTER_TYPE_UMSK (~(((1U << AUDIO_PADC_FILTER_TYPE_LEN) - 1) << AUDIO_PADC_FILTER_TYPE_POS)) -#define AUDIO_PADC_ODR AUDIO_PADC_ODR -#define AUDIO_PADC_ODR_POS (25U) -#define AUDIO_PADC_ODR_LEN (4U) -#define AUDIO_PADC_ODR_MSK (((1U << AUDIO_PADC_ODR_LEN) - 1) << AUDIO_PADC_ODR_POS) -#define AUDIO_PADC_ODR_UMSK (~(((1U << AUDIO_PADC_ODR_LEN) - 1) << AUDIO_PADC_ODR_POS)) - -/* 0x810 : padc_calib_cmd */ -#define AUDIO_PADC_CALIB_CMD_OFFSET (0x810) -#define AUDIO_PADC_CALIB_AVERAGE AUDIO_PADC_CALIB_AVERAGE -#define AUDIO_PADC_CALIB_AVERAGE_POS (16U) -#define AUDIO_PADC_CALIB_AVERAGE_LEN (3U) -#define AUDIO_PADC_CALIB_AVERAGE_MSK (((1U << AUDIO_PADC_CALIB_AVERAGE_LEN) - 1) << AUDIO_PADC_CALIB_AVERAGE_POS) -#define AUDIO_PADC_CALIB_AVERAGE_UMSK (~(((1U << AUDIO_PADC_CALIB_AVERAGE_LEN) - 1) << AUDIO_PADC_CALIB_AVERAGE_POS)) -#define AUDIO_PADC_CALIB_DISCARD AUDIO_PADC_CALIB_DISCARD -#define AUDIO_PADC_CALIB_DISCARD_POS (19U) -#define AUDIO_PADC_CALIB_DISCARD_LEN (3U) -#define AUDIO_PADC_CALIB_DISCARD_MSK (((1U << AUDIO_PADC_CALIB_DISCARD_LEN) - 1) << AUDIO_PADC_CALIB_DISCARD_POS) -#define AUDIO_PADC_CALIB_DISCARD_UMSK (~(((1U << AUDIO_PADC_CALIB_DISCARD_LEN) - 1) << AUDIO_PADC_CALIB_DISCARD_POS)) -#define AUDIO_PADC_CALIB_RUN AUDIO_PADC_CALIB_RUN -#define AUDIO_PADC_CALIB_RUN_POS (22U) -#define AUDIO_PADC_CALIB_RUN_LEN (1U) -#define AUDIO_PADC_CALIB_RUN_MSK (((1U << AUDIO_PADC_CALIB_RUN_LEN) - 1) << AUDIO_PADC_CALIB_RUN_POS) -#define AUDIO_PADC_CALIB_RUN_UMSK (~(((1U << AUDIO_PADC_CALIB_RUN_LEN) - 1) << AUDIO_PADC_CALIB_RUN_POS)) -#define AUDIO_PADC_CALIB_LVL AUDIO_PADC_CALIB_LVL -#define AUDIO_PADC_CALIB_LVL_POS (23U) -#define AUDIO_PADC_CALIB_LVL_LEN (2U) -#define AUDIO_PADC_CALIB_LVL_MSK (((1U << AUDIO_PADC_CALIB_LVL_LEN) - 1) << AUDIO_PADC_CALIB_LVL_POS) -#define AUDIO_PADC_CALIB_LVL_UMSK (~(((1U << AUDIO_PADC_CALIB_LVL_LEN) - 1) << AUDIO_PADC_CALIB_LVL_POS)) -#define AUDIO_PADC_CALIB_GAIN AUDIO_PADC_CALIB_GAIN -#define AUDIO_PADC_CALIB_GAIN_POS (25U) -#define AUDIO_PADC_CALIB_GAIN_LEN (3U) -#define AUDIO_PADC_CALIB_GAIN_MSK (((1U << AUDIO_PADC_CALIB_GAIN_LEN) - 1) << AUDIO_PADC_CALIB_GAIN_POS) -#define AUDIO_PADC_CALIB_GAIN_UMSK (~(((1U << AUDIO_PADC_CALIB_GAIN_LEN) - 1) << AUDIO_PADC_CALIB_GAIN_POS)) -#define AUDIO_PADC_CALIB_MODE AUDIO_PADC_CALIB_MODE -#define AUDIO_PADC_CALIB_MODE_POS (28U) -#define AUDIO_PADC_CALIB_MODE_LEN (2U) -#define AUDIO_PADC_CALIB_MODE_MSK (((1U << AUDIO_PADC_CALIB_MODE_LEN) - 1) << AUDIO_PADC_CALIB_MODE_POS) -#define AUDIO_PADC_CALIB_MODE_UMSK (~(((1U << AUDIO_PADC_CALIB_MODE_LEN) - 1) << AUDIO_PADC_CALIB_MODE_POS)) -#define AUDIO_PADC_CALIB_START AUDIO_PADC_CALIB_START -#define AUDIO_PADC_CALIB_START_POS (30U) -#define AUDIO_PADC_CALIB_START_LEN (1U) -#define AUDIO_PADC_CALIB_START_MSK (((1U << AUDIO_PADC_CALIB_START_LEN) - 1) << AUDIO_PADC_CALIB_START_POS) -#define AUDIO_PADC_CALIB_START_UMSK (~(((1U << AUDIO_PADC_CALIB_START_LEN) - 1) << AUDIO_PADC_CALIB_START_POS)) -#define AUDIO_PADC_CALIB_METHOD AUDIO_PADC_CALIB_METHOD -#define AUDIO_PADC_CALIB_METHOD_POS (31U) -#define AUDIO_PADC_CALIB_METHOD_LEN (1U) -#define AUDIO_PADC_CALIB_METHOD_MSK (((1U << AUDIO_PADC_CALIB_METHOD_LEN) - 1) << AUDIO_PADC_CALIB_METHOD_POS) -#define AUDIO_PADC_CALIB_METHOD_UMSK (~(((1U << AUDIO_PADC_CALIB_METHOD_LEN) - 1) << AUDIO_PADC_CALIB_METHOD_POS)) - -/* 0x814 : padc_status */ -#define AUDIO_PADC_STATUS_OFFSET (0x814) -#define AUDIO_PADC_SOFT_RST AUDIO_PADC_SOFT_RST -#define AUDIO_PADC_SOFT_RST_POS (2U) -#define AUDIO_PADC_SOFT_RST_LEN (1U) -#define AUDIO_PADC_SOFT_RST_MSK (((1U << AUDIO_PADC_SOFT_RST_LEN) - 1) << AUDIO_PADC_SOFT_RST_POS) -#define AUDIO_PADC_SOFT_RST_UMSK (~(((1U << AUDIO_PADC_SOFT_RST_LEN) - 1) << AUDIO_PADC_SOFT_RST_POS)) -#define AUDIO_PADC_FILTER_RDY AUDIO_PADC_FILTER_RDY -#define AUDIO_PADC_FILTER_RDY_POS (3U) -#define AUDIO_PADC_FILTER_RDY_LEN (1U) -#define AUDIO_PADC_FILTER_RDY_MSK (((1U << AUDIO_PADC_FILTER_RDY_LEN) - 1) << AUDIO_PADC_FILTER_RDY_POS) -#define AUDIO_PADC_FILTER_RDY_UMSK (~(((1U << AUDIO_PADC_FILTER_RDY_LEN) - 1) << AUDIO_PADC_FILTER_RDY_POS)) -#define AUDIO_PADC_CALIB_ST AUDIO_PADC_CALIB_ST -#define AUDIO_PADC_CALIB_ST_POS (24U) -#define AUDIO_PADC_CALIB_ST_LEN (3U) -#define AUDIO_PADC_CALIB_ST_MSK (((1U << AUDIO_PADC_CALIB_ST_LEN) - 1) << AUDIO_PADC_CALIB_ST_POS) -#define AUDIO_PADC_CALIB_ST_UMSK (~(((1U << AUDIO_PADC_CALIB_ST_LEN) - 1) << AUDIO_PADC_CALIB_ST_POS)) -#define AUDIO_PADC_CALIB_BUSY AUDIO_PADC_CALIB_BUSY -#define AUDIO_PADC_CALIB_BUSY_POS (27U) -#define AUDIO_PADC_CALIB_BUSY_LEN (1U) -#define AUDIO_PADC_CALIB_BUSY_MSK (((1U << AUDIO_PADC_CALIB_BUSY_LEN) - 1) << AUDIO_PADC_CALIB_BUSY_POS) -#define AUDIO_PADC_CALIB_BUSY_UMSK (~(((1U << AUDIO_PADC_CALIB_BUSY_LEN) - 1) << AUDIO_PADC_CALIB_BUSY_POS)) -#define AUDIO_PADC_INT AUDIO_PADC_INT -#define AUDIO_PADC_INT_POS (28U) -#define AUDIO_PADC_INT_LEN (1U) -#define AUDIO_PADC_INT_MSK (((1U << AUDIO_PADC_INT_LEN) - 1) << AUDIO_PADC_INT_POS) -#define AUDIO_PADC_INT_UMSK (~(((1U << AUDIO_PADC_INT_LEN) - 1) << AUDIO_PADC_INT_POS)) -#define AUDIO_PADC_INT_CLR AUDIO_PADC_INT_CLR -#define AUDIO_PADC_INT_CLR_POS (29U) -#define AUDIO_PADC_INT_CLR_LEN (1U) -#define AUDIO_PADC_INT_CLR_MSK (((1U << AUDIO_PADC_INT_CLR_LEN) - 1) << AUDIO_PADC_INT_CLR_POS) -#define AUDIO_PADC_INT_CLR_UMSK (~(((1U << AUDIO_PADC_INT_CLR_LEN) - 1) << AUDIO_PADC_INT_CLR_POS)) -#define AUDIO_PADC_INT_SET AUDIO_PADC_INT_SET -#define AUDIO_PADC_INT_SET_POS (30U) -#define AUDIO_PADC_INT_SET_LEN (1U) -#define AUDIO_PADC_INT_SET_MSK (((1U << AUDIO_PADC_INT_SET_LEN) - 1) << AUDIO_PADC_INT_SET_POS) -#define AUDIO_PADC_INT_SET_UMSK (~(((1U << AUDIO_PADC_INT_SET_LEN) - 1) << AUDIO_PADC_INT_SET_POS)) - -/* 0x818 : padc_data */ -#define AUDIO_PADC_DATA_OFFSET (0x818) -#define AUDIO_PADC_RAW_DATA AUDIO_PADC_RAW_DATA -#define AUDIO_PADC_RAW_DATA_POS (0U) -#define AUDIO_PADC_RAW_DATA_LEN (24U) -#define AUDIO_PADC_RAW_DATA_MSK (((1U << AUDIO_PADC_RAW_DATA_LEN) - 1) << AUDIO_PADC_RAW_DATA_POS) -#define AUDIO_PADC_RAW_DATA_UMSK (~(((1U << AUDIO_PADC_RAW_DATA_LEN) - 1) << AUDIO_PADC_RAW_DATA_POS)) - -/* 0x81C : padc_calib_cfg1 */ -#define AUDIO_PADC_CALIB_CFG1_OFFSET (0x81C) -#define AUDIO_PADC_OEC AUDIO_PADC_OEC -#define AUDIO_PADC_OEC_POS (0U) -#define AUDIO_PADC_OEC_LEN (24U) -#define AUDIO_PADC_OEC_MSK (((1U << AUDIO_PADC_OEC_LEN) - 1) << AUDIO_PADC_OEC_POS) -#define AUDIO_PADC_OEC_UMSK (~(((1U << AUDIO_PADC_OEC_LEN) - 1) << AUDIO_PADC_OEC_POS)) - -/* 0x820 : padc_calib_cfg2 */ -#define AUDIO_PADC_CALIB_CFG2_OFFSET (0x820) -#define AUDIO_PADC_GEC AUDIO_PADC_GEC -#define AUDIO_PADC_GEC_POS (0U) -#define AUDIO_PADC_GEC_LEN (24U) -#define AUDIO_PADC_GEC_MSK (((1U << AUDIO_PADC_GEC_LEN) - 1) << AUDIO_PADC_GEC_POS) -#define AUDIO_PADC_GEC_UMSK (~(((1U << AUDIO_PADC_GEC_LEN) - 1) << AUDIO_PADC_GEC_POS)) - -/* 0x824 : padc_calib_cfg3 */ -#define AUDIO_PADC_CALIB_CFG3_OFFSET (0x824) - -/* 0x828 : padc_calib_cfg4 */ -#define AUDIO_PADC_CALIB_CFG4_OFFSET (0x828) - -/* 0x82C : padc_calib_cfg5 */ -#define AUDIO_PADC_CALIB_CFG5_OFFSET (0x82C) -#define AUDIO_PADC_GAINCAL_REF AUDIO_PADC_GAINCAL_REF -#define AUDIO_PADC_GAINCAL_REF_POS (0U) -#define AUDIO_PADC_GAINCAL_REF_LEN (24U) -#define AUDIO_PADC_GAINCAL_REF_MSK (((1U << AUDIO_PADC_GAINCAL_REF_LEN) - 1) << AUDIO_PADC_GAINCAL_REF_POS) -#define AUDIO_PADC_GAINCAL_REF_UMSK (~(((1U << AUDIO_PADC_GAINCAL_REF_LEN) - 1) << AUDIO_PADC_GAINCAL_REF_POS)) - -/* 0x830 : padc_calib_cfg6 */ -#define AUDIO_PADC_CALIB_CFG6_OFFSET (0x830) - -/* 0x834 : padc_calib_cfg7 */ -#define AUDIO_PADC_CALIB_CFG7_OFFSET (0x834) - -/* 0x838 : padc_oec_w1p */ -#define AUDIO_PADC_OEC_W1P_OFFSET (0x838) -#define AUDIO_PADC_WR_OEC AUDIO_PADC_WR_OEC -#define AUDIO_PADC_WR_OEC_POS (0U) -#define AUDIO_PADC_WR_OEC_LEN (24U) -#define AUDIO_PADC_WR_OEC_MSK (((1U << AUDIO_PADC_WR_OEC_LEN) - 1) << AUDIO_PADC_WR_OEC_POS) -#define AUDIO_PADC_WR_OEC_UMSK (~(((1U << AUDIO_PADC_WR_OEC_LEN) - 1) << AUDIO_PADC_WR_OEC_POS)) -#define AUDIO_PADC_OEC_W1P_G0 AUDIO_PADC_OEC_W1P_G0 -#define AUDIO_PADC_OEC_W1P_G0_POS (24U) -#define AUDIO_PADC_OEC_W1P_G0_LEN (1U) -#define AUDIO_PADC_OEC_W1P_G0_MSK (((1U << AUDIO_PADC_OEC_W1P_G0_LEN) - 1) << AUDIO_PADC_OEC_W1P_G0_POS) -#define AUDIO_PADC_OEC_W1P_G0_UMSK (~(((1U << AUDIO_PADC_OEC_W1P_G0_LEN) - 1) << AUDIO_PADC_OEC_W1P_G0_POS)) -#define AUDIO_PADC_OEC_W1P_G1 AUDIO_PADC_OEC_W1P_G1 -#define AUDIO_PADC_OEC_W1P_G1_POS (25U) -#define AUDIO_PADC_OEC_W1P_G1_LEN (1U) -#define AUDIO_PADC_OEC_W1P_G1_MSK (((1U << AUDIO_PADC_OEC_W1P_G1_LEN) - 1) << AUDIO_PADC_OEC_W1P_G1_POS) -#define AUDIO_PADC_OEC_W1P_G1_UMSK (~(((1U << AUDIO_PADC_OEC_W1P_G1_LEN) - 1) << AUDIO_PADC_OEC_W1P_G1_POS)) -#define AUDIO_PADC_OEC_W1P_G2 AUDIO_PADC_OEC_W1P_G2 -#define AUDIO_PADC_OEC_W1P_G2_POS (26U) -#define AUDIO_PADC_OEC_W1P_G2_LEN (1U) -#define AUDIO_PADC_OEC_W1P_G2_MSK (((1U << AUDIO_PADC_OEC_W1P_G2_LEN) - 1) << AUDIO_PADC_OEC_W1P_G2_POS) -#define AUDIO_PADC_OEC_W1P_G2_UMSK (~(((1U << AUDIO_PADC_OEC_W1P_G2_LEN) - 1) << AUDIO_PADC_OEC_W1P_G2_POS)) -#define AUDIO_PADC_OEC_W1P_G3 AUDIO_PADC_OEC_W1P_G3 -#define AUDIO_PADC_OEC_W1P_G3_POS (27U) -#define AUDIO_PADC_OEC_W1P_G3_LEN (1U) -#define AUDIO_PADC_OEC_W1P_G3_MSK (((1U << AUDIO_PADC_OEC_W1P_G3_LEN) - 1) << AUDIO_PADC_OEC_W1P_G3_POS) -#define AUDIO_PADC_OEC_W1P_G3_UMSK (~(((1U << AUDIO_PADC_OEC_W1P_G3_LEN) - 1) << AUDIO_PADC_OEC_W1P_G3_POS)) -#define AUDIO_PADC_OEC_W1P_G4 AUDIO_PADC_OEC_W1P_G4 -#define AUDIO_PADC_OEC_W1P_G4_POS (28U) -#define AUDIO_PADC_OEC_W1P_G4_LEN (1U) -#define AUDIO_PADC_OEC_W1P_G4_MSK (((1U << AUDIO_PADC_OEC_W1P_G4_LEN) - 1) << AUDIO_PADC_OEC_W1P_G4_POS) -#define AUDIO_PADC_OEC_W1P_G4_UMSK (~(((1U << AUDIO_PADC_OEC_W1P_G4_LEN) - 1) << AUDIO_PADC_OEC_W1P_G4_POS)) -#define AUDIO_PADC_OEC_W1P_G5 AUDIO_PADC_OEC_W1P_G5 -#define AUDIO_PADC_OEC_W1P_G5_POS (29U) -#define AUDIO_PADC_OEC_W1P_G5_LEN (1U) -#define AUDIO_PADC_OEC_W1P_G5_MSK (((1U << AUDIO_PADC_OEC_W1P_G5_LEN) - 1) << AUDIO_PADC_OEC_W1P_G5_POS) -#define AUDIO_PADC_OEC_W1P_G5_UMSK (~(((1U << AUDIO_PADC_OEC_W1P_G5_LEN) - 1) << AUDIO_PADC_OEC_W1P_G5_POS)) -#define AUDIO_PADC_OEC_W1P_G6 AUDIO_PADC_OEC_W1P_G6 -#define AUDIO_PADC_OEC_W1P_G6_POS (30U) -#define AUDIO_PADC_OEC_W1P_G6_LEN (1U) -#define AUDIO_PADC_OEC_W1P_G6_MSK (((1U << AUDIO_PADC_OEC_W1P_G6_LEN) - 1) << AUDIO_PADC_OEC_W1P_G6_POS) -#define AUDIO_PADC_OEC_W1P_G6_UMSK (~(((1U << AUDIO_PADC_OEC_W1P_G6_LEN) - 1) << AUDIO_PADC_OEC_W1P_G6_POS)) -#define AUDIO_PADC_OEC_W1P_G7 AUDIO_PADC_OEC_W1P_G7 -#define AUDIO_PADC_OEC_W1P_G7_POS (31U) -#define AUDIO_PADC_OEC_W1P_G7_LEN (1U) -#define AUDIO_PADC_OEC_W1P_G7_MSK (((1U << AUDIO_PADC_OEC_W1P_G7_LEN) - 1) << AUDIO_PADC_OEC_W1P_G7_POS) -#define AUDIO_PADC_OEC_W1P_G7_UMSK (~(((1U << AUDIO_PADC_OEC_W1P_G7_LEN) - 1) << AUDIO_PADC_OEC_W1P_G7_POS)) - -/* 0x83C : padc_gec_w1p */ -#define AUDIO_PADC_GEC_W1P_OFFSET (0x83C) -#define AUDIO_PADC_WR_GEC AUDIO_PADC_WR_GEC -#define AUDIO_PADC_WR_GEC_POS (0U) -#define AUDIO_PADC_WR_GEC_LEN (24U) -#define AUDIO_PADC_WR_GEC_MSK (((1U << AUDIO_PADC_WR_GEC_LEN) - 1) << AUDIO_PADC_WR_GEC_POS) -#define AUDIO_PADC_WR_GEC_UMSK (~(((1U << AUDIO_PADC_WR_GEC_LEN) - 1) << AUDIO_PADC_WR_GEC_POS)) -#define AUDIO_PADC_GEC_W1P_G0 AUDIO_PADC_GEC_W1P_G0 -#define AUDIO_PADC_GEC_W1P_G0_POS (24U) -#define AUDIO_PADC_GEC_W1P_G0_LEN (1U) -#define AUDIO_PADC_GEC_W1P_G0_MSK (((1U << AUDIO_PADC_GEC_W1P_G0_LEN) - 1) << AUDIO_PADC_GEC_W1P_G0_POS) -#define AUDIO_PADC_GEC_W1P_G0_UMSK (~(((1U << AUDIO_PADC_GEC_W1P_G0_LEN) - 1) << AUDIO_PADC_GEC_W1P_G0_POS)) -#define AUDIO_PADC_GEC_W1P_G1 AUDIO_PADC_GEC_W1P_G1 -#define AUDIO_PADC_GEC_W1P_G1_POS (25U) -#define AUDIO_PADC_GEC_W1P_G1_LEN (1U) -#define AUDIO_PADC_GEC_W1P_G1_MSK (((1U << AUDIO_PADC_GEC_W1P_G1_LEN) - 1) << AUDIO_PADC_GEC_W1P_G1_POS) -#define AUDIO_PADC_GEC_W1P_G1_UMSK (~(((1U << AUDIO_PADC_GEC_W1P_G1_LEN) - 1) << AUDIO_PADC_GEC_W1P_G1_POS)) -#define AUDIO_PADC_GEC_W1P_G2 AUDIO_PADC_GEC_W1P_G2 -#define AUDIO_PADC_GEC_W1P_G2_POS (26U) -#define AUDIO_PADC_GEC_W1P_G2_LEN (1U) -#define AUDIO_PADC_GEC_W1P_G2_MSK (((1U << AUDIO_PADC_GEC_W1P_G2_LEN) - 1) << AUDIO_PADC_GEC_W1P_G2_POS) -#define AUDIO_PADC_GEC_W1P_G2_UMSK (~(((1U << AUDIO_PADC_GEC_W1P_G2_LEN) - 1) << AUDIO_PADC_GEC_W1P_G2_POS)) -#define AUDIO_PADC_GEC_W1P_G3 AUDIO_PADC_GEC_W1P_G3 -#define AUDIO_PADC_GEC_W1P_G3_POS (27U) -#define AUDIO_PADC_GEC_W1P_G3_LEN (1U) -#define AUDIO_PADC_GEC_W1P_G3_MSK (((1U << AUDIO_PADC_GEC_W1P_G3_LEN) - 1) << AUDIO_PADC_GEC_W1P_G3_POS) -#define AUDIO_PADC_GEC_W1P_G3_UMSK (~(((1U << AUDIO_PADC_GEC_W1P_G3_LEN) - 1) << AUDIO_PADC_GEC_W1P_G3_POS)) -#define AUDIO_PADC_GEC_W1P_G4 AUDIO_PADC_GEC_W1P_G4 -#define AUDIO_PADC_GEC_W1P_G4_POS (28U) -#define AUDIO_PADC_GEC_W1P_G4_LEN (1U) -#define AUDIO_PADC_GEC_W1P_G4_MSK (((1U << AUDIO_PADC_GEC_W1P_G4_LEN) - 1) << AUDIO_PADC_GEC_W1P_G4_POS) -#define AUDIO_PADC_GEC_W1P_G4_UMSK (~(((1U << AUDIO_PADC_GEC_W1P_G4_LEN) - 1) << AUDIO_PADC_GEC_W1P_G4_POS)) -#define AUDIO_PADC_GEC_W1P_G5 AUDIO_PADC_GEC_W1P_G5 -#define AUDIO_PADC_GEC_W1P_G5_POS (29U) -#define AUDIO_PADC_GEC_W1P_G5_LEN (1U) -#define AUDIO_PADC_GEC_W1P_G5_MSK (((1U << AUDIO_PADC_GEC_W1P_G5_LEN) - 1) << AUDIO_PADC_GEC_W1P_G5_POS) -#define AUDIO_PADC_GEC_W1P_G5_UMSK (~(((1U << AUDIO_PADC_GEC_W1P_G5_LEN) - 1) << AUDIO_PADC_GEC_W1P_G5_POS)) -#define AUDIO_PADC_GEC_W1P_G6 AUDIO_PADC_GEC_W1P_G6 -#define AUDIO_PADC_GEC_W1P_G6_POS (30U) -#define AUDIO_PADC_GEC_W1P_G6_LEN (1U) -#define AUDIO_PADC_GEC_W1P_G6_MSK (((1U << AUDIO_PADC_GEC_W1P_G6_LEN) - 1) << AUDIO_PADC_GEC_W1P_G6_POS) -#define AUDIO_PADC_GEC_W1P_G6_UMSK (~(((1U << AUDIO_PADC_GEC_W1P_G6_LEN) - 1) << AUDIO_PADC_GEC_W1P_G6_POS)) -#define AUDIO_PADC_GEC_W1P_G7 AUDIO_PADC_GEC_W1P_G7 -#define AUDIO_PADC_GEC_W1P_G7_POS (31U) -#define AUDIO_PADC_GEC_W1P_G7_LEN (1U) -#define AUDIO_PADC_GEC_W1P_G7_MSK (((1U << AUDIO_PADC_GEC_W1P_G7_LEN) - 1) << AUDIO_PADC_GEC_W1P_G7_POS) -#define AUDIO_PADC_GEC_W1P_G7_UMSK (~(((1U << AUDIO_PADC_GEC_W1P_G7_LEN) - 1) << AUDIO_PADC_GEC_W1P_G7_POS)) - -/* 0x840 : padc_oec_cfg0 */ -#define AUDIO_PADC_OEC_CFG0_OFFSET (0x840) -#define AUDIO_PADC_OEC_G0 AUDIO_PADC_OEC_G0 -#define AUDIO_PADC_OEC_G0_POS (0U) -#define AUDIO_PADC_OEC_G0_LEN (24U) -#define AUDIO_PADC_OEC_G0_MSK (((1U << AUDIO_PADC_OEC_G0_LEN) - 1) << AUDIO_PADC_OEC_G0_POS) -#define AUDIO_PADC_OEC_G0_UMSK (~(((1U << AUDIO_PADC_OEC_G0_LEN) - 1) << AUDIO_PADC_OEC_G0_POS)) - -/* 0x844 : padc_oec_cfg1 */ -#define AUDIO_PADC_OEC_CFG1_OFFSET (0x844) -#define AUDIO_PADC_OEC_G1 AUDIO_PADC_OEC_G1 -#define AUDIO_PADC_OEC_G1_POS (0U) -#define AUDIO_PADC_OEC_G1_LEN (24U) -#define AUDIO_PADC_OEC_G1_MSK (((1U << AUDIO_PADC_OEC_G1_LEN) - 1) << AUDIO_PADC_OEC_G1_POS) -#define AUDIO_PADC_OEC_G1_UMSK (~(((1U << AUDIO_PADC_OEC_G1_LEN) - 1) << AUDIO_PADC_OEC_G1_POS)) - -/* 0x848 : padc_oec_cfg2 */ -#define AUDIO_PADC_OEC_CFG2_OFFSET (0x848) -#define AUDIO_PADC_OEC_G2 AUDIO_PADC_OEC_G2 -#define AUDIO_PADC_OEC_G2_POS (0U) -#define AUDIO_PADC_OEC_G2_LEN (24U) -#define AUDIO_PADC_OEC_G2_MSK (((1U << AUDIO_PADC_OEC_G2_LEN) - 1) << AUDIO_PADC_OEC_G2_POS) -#define AUDIO_PADC_OEC_G2_UMSK (~(((1U << AUDIO_PADC_OEC_G2_LEN) - 1) << AUDIO_PADC_OEC_G2_POS)) - -/* 0x84C : padc_oec_cfg3 */ -#define AUDIO_PADC_OEC_CFG3_OFFSET (0x84C) -#define AUDIO_PADC_OEC_G3 AUDIO_PADC_OEC_G3 -#define AUDIO_PADC_OEC_G3_POS (0U) -#define AUDIO_PADC_OEC_G3_LEN (24U) -#define AUDIO_PADC_OEC_G3_MSK (((1U << AUDIO_PADC_OEC_G3_LEN) - 1) << AUDIO_PADC_OEC_G3_POS) -#define AUDIO_PADC_OEC_G3_UMSK (~(((1U << AUDIO_PADC_OEC_G3_LEN) - 1) << AUDIO_PADC_OEC_G3_POS)) - -/* 0x850 : padc_oec_cfg4 */ -#define AUDIO_PADC_OEC_CFG4_OFFSET (0x850) -#define AUDIO_PADC_OEC_G4 AUDIO_PADC_OEC_G4 -#define AUDIO_PADC_OEC_G4_POS (0U) -#define AUDIO_PADC_OEC_G4_LEN (24U) -#define AUDIO_PADC_OEC_G4_MSK (((1U << AUDIO_PADC_OEC_G4_LEN) - 1) << AUDIO_PADC_OEC_G4_POS) -#define AUDIO_PADC_OEC_G4_UMSK (~(((1U << AUDIO_PADC_OEC_G4_LEN) - 1) << AUDIO_PADC_OEC_G4_POS)) - -/* 0x854 : padc_oec_cfg5 */ -#define AUDIO_PADC_OEC_CFG5_OFFSET (0x854) -#define AUDIO_PADC_OEC_G5 AUDIO_PADC_OEC_G5 -#define AUDIO_PADC_OEC_G5_POS (0U) -#define AUDIO_PADC_OEC_G5_LEN (24U) -#define AUDIO_PADC_OEC_G5_MSK (((1U << AUDIO_PADC_OEC_G5_LEN) - 1) << AUDIO_PADC_OEC_G5_POS) -#define AUDIO_PADC_OEC_G5_UMSK (~(((1U << AUDIO_PADC_OEC_G5_LEN) - 1) << AUDIO_PADC_OEC_G5_POS)) - -/* 0x858 : padc_oec_cfg6 */ -#define AUDIO_PADC_OEC_CFG6_OFFSET (0x858) -#define AUDIO_PADC_OEC_G6 AUDIO_PADC_OEC_G6 -#define AUDIO_PADC_OEC_G6_POS (0U) -#define AUDIO_PADC_OEC_G6_LEN (24U) -#define AUDIO_PADC_OEC_G6_MSK (((1U << AUDIO_PADC_OEC_G6_LEN) - 1) << AUDIO_PADC_OEC_G6_POS) -#define AUDIO_PADC_OEC_G6_UMSK (~(((1U << AUDIO_PADC_OEC_G6_LEN) - 1) << AUDIO_PADC_OEC_G6_POS)) - -/* 0x85C : padc_oec_cfg7 */ -#define AUDIO_PADC_OEC_CFG7_OFFSET (0x85C) -#define AUDIO_PADC_OEC_G7 AUDIO_PADC_OEC_G7 -#define AUDIO_PADC_OEC_G7_POS (0U) -#define AUDIO_PADC_OEC_G7_LEN (24U) -#define AUDIO_PADC_OEC_G7_MSK (((1U << AUDIO_PADC_OEC_G7_LEN) - 1) << AUDIO_PADC_OEC_G7_POS) -#define AUDIO_PADC_OEC_G7_UMSK (~(((1U << AUDIO_PADC_OEC_G7_LEN) - 1) << AUDIO_PADC_OEC_G7_POS)) - -/* 0x860 : padc_gec_cfg0 */ -#define AUDIO_PADC_GEC_CFG0_OFFSET (0x860) -#define AUDIO_PADC_GEC_G0 AUDIO_PADC_GEC_G0 -#define AUDIO_PADC_GEC_G0_POS (0U) -#define AUDIO_PADC_GEC_G0_LEN (24U) -#define AUDIO_PADC_GEC_G0_MSK (((1U << AUDIO_PADC_GEC_G0_LEN) - 1) << AUDIO_PADC_GEC_G0_POS) -#define AUDIO_PADC_GEC_G0_UMSK (~(((1U << AUDIO_PADC_GEC_G0_LEN) - 1) << AUDIO_PADC_GEC_G0_POS)) - -/* 0x864 : padc_gec_cfg1 */ -#define AUDIO_PADC_GEC_CFG1_OFFSET (0x864) -#define AUDIO_PADC_GEC_G1 AUDIO_PADC_GEC_G1 -#define AUDIO_PADC_GEC_G1_POS (0U) -#define AUDIO_PADC_GEC_G1_LEN (24U) -#define AUDIO_PADC_GEC_G1_MSK (((1U << AUDIO_PADC_GEC_G1_LEN) - 1) << AUDIO_PADC_GEC_G1_POS) -#define AUDIO_PADC_GEC_G1_UMSK (~(((1U << AUDIO_PADC_GEC_G1_LEN) - 1) << AUDIO_PADC_GEC_G1_POS)) - -/* 0x868 : padc_gec_cfg2 */ -#define AUDIO_PADC_GEC_CFG2_OFFSET (0x868) -#define AUDIO_PADC_GEC_G2 AUDIO_PADC_GEC_G2 -#define AUDIO_PADC_GEC_G2_POS (0U) -#define AUDIO_PADC_GEC_G2_LEN (24U) -#define AUDIO_PADC_GEC_G2_MSK (((1U << AUDIO_PADC_GEC_G2_LEN) - 1) << AUDIO_PADC_GEC_G2_POS) -#define AUDIO_PADC_GEC_G2_UMSK (~(((1U << AUDIO_PADC_GEC_G2_LEN) - 1) << AUDIO_PADC_GEC_G2_POS)) - -/* 0x86C : padc_gec_cfg3 */ -#define AUDIO_PADC_GEC_CFG3_OFFSET (0x86C) -#define AUDIO_PADC_GEC_G3 AUDIO_PADC_GEC_G3 -#define AUDIO_PADC_GEC_G3_POS (0U) -#define AUDIO_PADC_GEC_G3_LEN (24U) -#define AUDIO_PADC_GEC_G3_MSK (((1U << AUDIO_PADC_GEC_G3_LEN) - 1) << AUDIO_PADC_GEC_G3_POS) -#define AUDIO_PADC_GEC_G3_UMSK (~(((1U << AUDIO_PADC_GEC_G3_LEN) - 1) << AUDIO_PADC_GEC_G3_POS)) - -/* 0x870 : padc_gec_cfg4 */ -#define AUDIO_PADC_GEC_CFG4_OFFSET (0x870) -#define AUDIO_PADC_GEC_G4 AUDIO_PADC_GEC_G4 -#define AUDIO_PADC_GEC_G4_POS (0U) -#define AUDIO_PADC_GEC_G4_LEN (24U) -#define AUDIO_PADC_GEC_G4_MSK (((1U << AUDIO_PADC_GEC_G4_LEN) - 1) << AUDIO_PADC_GEC_G4_POS) -#define AUDIO_PADC_GEC_G4_UMSK (~(((1U << AUDIO_PADC_GEC_G4_LEN) - 1) << AUDIO_PADC_GEC_G4_POS)) - -/* 0x874 : padc_gec_cfg5 */ -#define AUDIO_PADC_GEC_CFG5_OFFSET (0x874) -#define AUDIO_PADC_GEC_G5 AUDIO_PADC_GEC_G5 -#define AUDIO_PADC_GEC_G5_POS (0U) -#define AUDIO_PADC_GEC_G5_LEN (24U) -#define AUDIO_PADC_GEC_G5_MSK (((1U << AUDIO_PADC_GEC_G5_LEN) - 1) << AUDIO_PADC_GEC_G5_POS) -#define AUDIO_PADC_GEC_G5_UMSK (~(((1U << AUDIO_PADC_GEC_G5_LEN) - 1) << AUDIO_PADC_GEC_G5_POS)) - -/* 0x878 : padc_gec_cfg6 */ -#define AUDIO_PADC_GEC_CFG6_OFFSET (0x878) -#define AUDIO_PADC_GEC_G6 AUDIO_PADC_GEC_G6 -#define AUDIO_PADC_GEC_G6_POS (0U) -#define AUDIO_PADC_GEC_G6_LEN (24U) -#define AUDIO_PADC_GEC_G6_MSK (((1U << AUDIO_PADC_GEC_G6_LEN) - 1) << AUDIO_PADC_GEC_G6_POS) -#define AUDIO_PADC_GEC_G6_UMSK (~(((1U << AUDIO_PADC_GEC_G6_LEN) - 1) << AUDIO_PADC_GEC_G6_POS)) - -/* 0x87C : padc_gec_cfg7 */ -#define AUDIO_PADC_GEC_CFG7_OFFSET (0x87C) -#define AUDIO_PADC_GEC_G7 AUDIO_PADC_GEC_G7 -#define AUDIO_PADC_GEC_G7_POS (0U) -#define AUDIO_PADC_GEC_G7_LEN (24U) -#define AUDIO_PADC_GEC_G7_MSK (((1U << AUDIO_PADC_GEC_G7_LEN) - 1) << AUDIO_PADC_GEC_G7_POS) -#define AUDIO_PADC_GEC_G7_UMSK (~(((1U << AUDIO_PADC_GEC_G7_LEN) - 1) << AUDIO_PADC_GEC_G7_POS)) - -/* 0x900 : padc_rx_fifo_ctrl */ -#define AUDIO_PADC_RX_FIFO_CTRL_OFFSET (0x900) -#define AUDIO_PADC_RX_FIFO_FLUSH AUDIO_PADC_RX_FIFO_FLUSH -#define AUDIO_PADC_RX_FIFO_FLUSH_POS (0U) -#define AUDIO_PADC_RX_FIFO_FLUSH_LEN (1U) -#define AUDIO_PADC_RX_FIFO_FLUSH_MSK (((1U << AUDIO_PADC_RX_FIFO_FLUSH_LEN) - 1) << AUDIO_PADC_RX_FIFO_FLUSH_POS) -#define AUDIO_PADC_RX_FIFO_FLUSH_UMSK (~(((1U << AUDIO_PADC_RX_FIFO_FLUSH_LEN) - 1) << AUDIO_PADC_RX_FIFO_FLUSH_POS)) -#define AUDIO_PADC_RXO_INT_EN AUDIO_PADC_RXO_INT_EN -#define AUDIO_PADC_RXO_INT_EN_POS (1U) -#define AUDIO_PADC_RXO_INT_EN_LEN (1U) -#define AUDIO_PADC_RXO_INT_EN_MSK (((1U << AUDIO_PADC_RXO_INT_EN_LEN) - 1) << AUDIO_PADC_RXO_INT_EN_POS) -#define AUDIO_PADC_RXO_INT_EN_UMSK (~(((1U << AUDIO_PADC_RXO_INT_EN_LEN) - 1) << AUDIO_PADC_RXO_INT_EN_POS)) -#define AUDIO_PADC_RXU_INT_EN AUDIO_PADC_RXU_INT_EN -#define AUDIO_PADC_RXU_INT_EN_POS (2U) -#define AUDIO_PADC_RXU_INT_EN_LEN (1U) -#define AUDIO_PADC_RXU_INT_EN_MSK (((1U << AUDIO_PADC_RXU_INT_EN_LEN) - 1) << AUDIO_PADC_RXU_INT_EN_POS) -#define AUDIO_PADC_RXU_INT_EN_UMSK (~(((1U << AUDIO_PADC_RXU_INT_EN_LEN) - 1) << AUDIO_PADC_RXU_INT_EN_POS)) -#define AUDIO_PADC_RXA_INT_EN AUDIO_PADC_RXA_INT_EN -#define AUDIO_PADC_RXA_INT_EN_POS (3U) -#define AUDIO_PADC_RXA_INT_EN_LEN (1U) -#define AUDIO_PADC_RXA_INT_EN_MSK (((1U << AUDIO_PADC_RXA_INT_EN_LEN) - 1) << AUDIO_PADC_RXA_INT_EN_POS) -#define AUDIO_PADC_RXA_INT_EN_UMSK (~(((1U << AUDIO_PADC_RXA_INT_EN_LEN) - 1) << AUDIO_PADC_RXA_INT_EN_POS)) -#define AUDIO_PADC_RX_DRQ_EN AUDIO_PADC_RX_DRQ_EN -#define AUDIO_PADC_RX_DRQ_EN_POS (4U) -#define AUDIO_PADC_RX_DRQ_EN_LEN (1U) -#define AUDIO_PADC_RX_DRQ_EN_MSK (((1U << AUDIO_PADC_RX_DRQ_EN_LEN) - 1) << AUDIO_PADC_RX_DRQ_EN_POS) -#define AUDIO_PADC_RX_DRQ_EN_UMSK (~(((1U << AUDIO_PADC_RX_DRQ_EN_LEN) - 1) << AUDIO_PADC_RX_DRQ_EN_POS)) -#define AUDIO_PADC_RX_DATA_RES AUDIO_PADC_RX_DATA_RES -#define AUDIO_PADC_RX_DATA_RES_POS (5U) -#define AUDIO_PADC_RX_DATA_RES_LEN (1U) -#define AUDIO_PADC_RX_DATA_RES_MSK (((1U << AUDIO_PADC_RX_DATA_RES_LEN) - 1) << AUDIO_PADC_RX_DATA_RES_POS) -#define AUDIO_PADC_RX_DATA_RES_UMSK (~(((1U << AUDIO_PADC_RX_DATA_RES_LEN) - 1) << AUDIO_PADC_RX_DATA_RES_POS)) -#define AUDIO_PADC_RX_CH_EN AUDIO_PADC_RX_CH_EN -#define AUDIO_PADC_RX_CH_EN_POS (8U) -#define AUDIO_PADC_RX_CH_EN_LEN (1U) -#define AUDIO_PADC_RX_CH_EN_MSK (((1U << AUDIO_PADC_RX_CH_EN_LEN) - 1) << AUDIO_PADC_RX_CH_EN_POS) -#define AUDIO_PADC_RX_CH_EN_UMSK (~(((1U << AUDIO_PADC_RX_CH_EN_LEN) - 1) << AUDIO_PADC_RX_CH_EN_POS)) -#define AUDIO_PADC_RX_DRQ_CNT AUDIO_PADC_RX_DRQ_CNT -#define AUDIO_PADC_RX_DRQ_CNT_POS (14U) -#define AUDIO_PADC_RX_DRQ_CNT_LEN (2U) -#define AUDIO_PADC_RX_DRQ_CNT_MSK (((1U << AUDIO_PADC_RX_DRQ_CNT_LEN) - 1) << AUDIO_PADC_RX_DRQ_CNT_POS) -#define AUDIO_PADC_RX_DRQ_CNT_UMSK (~(((1U << AUDIO_PADC_RX_DRQ_CNT_LEN) - 1) << AUDIO_PADC_RX_DRQ_CNT_POS)) -#define AUDIO_PADC_RX_TRG_LEVEL AUDIO_PADC_RX_TRG_LEVEL -#define AUDIO_PADC_RX_TRG_LEVEL_POS (16U) -#define AUDIO_PADC_RX_TRG_LEVEL_LEN (4U) -#define AUDIO_PADC_RX_TRG_LEVEL_MSK (((1U << AUDIO_PADC_RX_TRG_LEVEL_LEN) - 1) << AUDIO_PADC_RX_TRG_LEVEL_POS) -#define AUDIO_PADC_RX_TRG_LEVEL_UMSK (~(((1U << AUDIO_PADC_RX_TRG_LEVEL_LEN) - 1) << AUDIO_PADC_RX_TRG_LEVEL_POS)) -#define AUDIO_PADC_RX_DATA_MODE AUDIO_PADC_RX_DATA_MODE -#define AUDIO_PADC_RX_DATA_MODE_POS (24U) -#define AUDIO_PADC_RX_DATA_MODE_LEN (2U) -#define AUDIO_PADC_RX_DATA_MODE_MSK (((1U << AUDIO_PADC_RX_DATA_MODE_LEN) - 1) << AUDIO_PADC_RX_DATA_MODE_POS) -#define AUDIO_PADC_RX_DATA_MODE_UMSK (~(((1U << AUDIO_PADC_RX_DATA_MODE_LEN) - 1) << AUDIO_PADC_RX_DATA_MODE_POS)) - -/* 0x904 : padc_rx_fifo_status */ -#define AUDIO_PADC_RX_FIFO_STATUS_OFFSET (0x904) -#define AUDIO_PADC_RXO_INT AUDIO_PADC_RXO_INT -#define AUDIO_PADC_RXO_INT_POS (1U) -#define AUDIO_PADC_RXO_INT_LEN (1U) -#define AUDIO_PADC_RXO_INT_MSK (((1U << AUDIO_PADC_RXO_INT_LEN) - 1) << AUDIO_PADC_RXO_INT_POS) -#define AUDIO_PADC_RXO_INT_UMSK (~(((1U << AUDIO_PADC_RXO_INT_LEN) - 1) << AUDIO_PADC_RXO_INT_POS)) -#define AUDIO_PADC_RXU_INT AUDIO_PADC_RXU_INT -#define AUDIO_PADC_RXU_INT_POS (2U) -#define AUDIO_PADC_RXU_INT_LEN (1U) -#define AUDIO_PADC_RXU_INT_MSK (((1U << AUDIO_PADC_RXU_INT_LEN) - 1) << AUDIO_PADC_RXU_INT_POS) -#define AUDIO_PADC_RXU_INT_UMSK (~(((1U << AUDIO_PADC_RXU_INT_LEN) - 1) << AUDIO_PADC_RXU_INT_POS)) -#define AUDIO_PADC_RXA_INT AUDIO_PADC_RXA_INT -#define AUDIO_PADC_RXA_INT_POS (4U) -#define AUDIO_PADC_RXA_INT_LEN (1U) -#define AUDIO_PADC_RXA_INT_MSK (((1U << AUDIO_PADC_RXA_INT_LEN) - 1) << AUDIO_PADC_RXA_INT_POS) -#define AUDIO_PADC_RXA_INT_UMSK (~(((1U << AUDIO_PADC_RXA_INT_LEN) - 1) << AUDIO_PADC_RXA_INT_POS)) -#define AUDIO_PADC_RXA_CNT AUDIO_PADC_RXA_CNT -#define AUDIO_PADC_RXA_CNT_POS (16U) -#define AUDIO_PADC_RXA_CNT_LEN (4U) -#define AUDIO_PADC_RXA_CNT_MSK (((1U << AUDIO_PADC_RXA_CNT_LEN) - 1) << AUDIO_PADC_RXA_CNT_POS) -#define AUDIO_PADC_RXA_CNT_UMSK (~(((1U << AUDIO_PADC_RXA_CNT_LEN) - 1) << AUDIO_PADC_RXA_CNT_POS)) -#define AUDIO_PADC_RXA AUDIO_PADC_RXA -#define AUDIO_PADC_RXA_POS (24U) -#define AUDIO_PADC_RXA_LEN (1U) -#define AUDIO_PADC_RXA_MSK (((1U << AUDIO_PADC_RXA_LEN) - 1) << AUDIO_PADC_RXA_POS) -#define AUDIO_PADC_RXA_UMSK (~(((1U << AUDIO_PADC_RXA_LEN) - 1) << AUDIO_PADC_RXA_POS)) - -/* 0x908 : padc_rx_fifo_data */ -#define AUDIO_PADC_RX_FIFO_DATA_OFFSET (0x908) -#define AUDIO_PADC_RX_DATA AUDIO_PADC_RX_DATA -#define AUDIO_PADC_RX_DATA_POS (0U) -#define AUDIO_PADC_RX_DATA_LEN (32U) -#define AUDIO_PADC_RX_DATA_MSK (((1U << AUDIO_PADC_RX_DATA_LEN) - 1) << AUDIO_PADC_RX_DATA_POS) -#define AUDIO_PADC_RX_DATA_UMSK (~(((1U << AUDIO_PADC_RX_DATA_LEN) - 1) << AUDIO_PADC_RX_DATA_POS)) - -struct audio_reg { - /* 0x0 : aud_top */ - union { - struct { - uint32_t audio_ckg_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t dac_itf_inv_sel : 1; /* [ 1], r/w, 0x1 */ - uint32_t adc_itf_inv_sel : 1; /* [ 2], r/w, 0x0 */ - uint32_t pdm_itf_inv_sel : 1; /* [ 3], r/w, 0x0 */ - uint32_t reserved_4_23 : 20; /* [23: 4], rsvd, 0x0 */ - uint32_t dac_rate : 3; /* [26:24], r/w, 0x4 */ - uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */ - uint32_t adc_rate : 3; /* [30:28], r/w, 0x1 */ - uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } aud_top; - - /* 0x4 : aud_itf */ - union { - struct { - uint32_t adc_0_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t adc_1_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t adc_2_en : 1; /* [ 2], r/w, 0x0 */ - uint32_t dac_0_en : 1; /* [ 3], r/w, 0x0 */ - uint32_t dac_1_en : 1; /* [ 4], r/w, 0x0 */ - uint32_t aec_0_en : 1; /* [ 5], r/w, 0x0 */ - uint32_t aec_1_en : 1; /* [ 6], r/w, 0x0 */ - uint32_t reserved_7_12 : 6; /* [12: 7], rsvd, 0x0 */ - uint32_t aud_rx0_sel : 3; /* [15:13], r/w, 0x0 */ - uint32_t aud_rx1_sel : 3; /* [18:16], r/w, 0x1 */ - uint32_t aud_rx2_sel : 3; /* [21:19], r/w, 0x2 */ - uint32_t aud_rx3_sel : 3; /* [24:22], r/w, 0x3 */ - uint32_t aud_rx4_sel : 3; /* [27:25], r/w, 0x4 */ - uint32_t aud_tx0_sel : 1; /* [ 28], r/w, 0x0 */ - uint32_t aud_tx1_sel : 1; /* [ 29], r/w, 0x1 */ - uint32_t adc_itf_en : 1; /* [ 30], r/w, 0x0 */ - uint32_t dac_itf_en : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } aud_itf; - - /* 0x8 : adc_0 */ - union { - struct { - uint32_t adc_0_fir_mode : 1; /* [ 0], r/w, 0x0 */ - uint32_t adc_1_fir_mode : 1; /* [ 1], r/w, 0x0 */ - uint32_t adc_2_fir_mode : 1; /* [ 2], r/w, 0x0 */ - uint32_t adc_0_scal : 6; /* [ 8: 3], r/w, 0x20 */ - uint32_t adc_1_scal : 6; /* [14: 9], r/w, 0x20 */ - uint32_t adc_2_scal : 6; /* [20:15], r/w, 0x20 */ - uint32_t reserved_21_28 : 8; /* [28:21], rsvd, 0x0 */ - uint32_t adc_dither_data : 1; /* [ 29], r, 0x1 */ - uint32_t adc_lfsr_mode : 2; /* [31:30], r/w, 0x0 */ - } BF; - uint32_t WORD; - } adc_0; - - /* 0xC : adc_1 */ - union { - struct { - uint32_t adc_0_k1 : 4; /* [ 3: 0], r/w, 0x8 */ - uint32_t adc_0_k1_en : 1; /* [ 4], r/w, 0x1 */ - uint32_t adc_0_k2 : 4; /* [ 8: 5], r/w, 0xd */ - uint32_t adc_0_k2_en : 1; /* [ 9], r/w, 0x0 */ - uint32_t adc_1_k1 : 4; /* [13:10], r/w, 0x8 */ - uint32_t adc_1_k1_en : 1; /* [ 14], r/w, 0x1 */ - uint32_t adc_1_k2 : 4; /* [18:15], r/w, 0xd */ - uint32_t adc_1_k2_en : 1; /* [ 19], r/w, 0x0 */ - uint32_t adc_2_k1 : 4; /* [23:20], r/w, 0x8 */ - uint32_t adc_2_k1_en : 1; /* [ 24], r/w, 0x1 */ - uint32_t adc_2_k2 : 4; /* [28:25], r/w, 0xd */ - uint32_t adc_2_k2_en : 1; /* [ 29], r/w, 0x0 */ - uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } adc_1; - - /* 0x10 : dac_0 */ - union { - struct { - uint32_t adc_pdm_h : 6; /* [ 5: 0], r/w, 0x1 */ - uint32_t adc_pdm_l : 6; /* [11: 6], r/w, 0x3f */ - uint32_t adc_0_src : 1; /* [ 12], r/w, 0x0 */ - uint32_t adc_0_pdm_lvl_swap : 1; /* [ 13], r/w, 0x0 */ - uint32_t adc_0_mash_bit_swap : 1; /* [ 14], r/w, 0x0 */ - uint32_t adc_1_src : 1; /* [ 15], r/w, 0x0 */ - uint32_t adc_1_pdm_lvl_swap : 1; /* [ 16], r/w, 0x0 */ - uint32_t adc_1_mash_bit_swap : 1; /* [ 17], r/w, 0x0 */ - uint32_t adc_2_src : 1; /* [ 18], r/w, 0x0 */ - uint32_t adc_2_pdm_lvl_swap : 1; /* [ 19], r/w, 0x0 */ - uint32_t adc_2_mash_bit_swap : 1; /* [ 20], r/w, 0x0 */ - uint32_t mix_0_sel : 2; /* [22:21], r/w, 0x0 */ - uint32_t mix_0_mode : 2; /* [24:23], r/w, 0x0 */ - uint32_t mix_0_att_mode1 : 3; /* [27:25], r/w, 0x0 */ - uint32_t mix_0_att_mode2 : 3; /* [30:28], r/w, 0x0 */ - uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dac_0; - - /* 0x14 : dac_1 */ - union { - struct { - uint32_t dac_dem_bypass : 1; /* [ 0], r/w, 0x0 */ - uint32_t dac_dem_out_swap : 1; /* [ 1], r/w, 0x0 */ - uint32_t reserved_2_4 : 3; /* [ 4: 2], rsvd, 0x0 */ - uint32_t dac_dsm_order : 1; /* [ 5], r/w, 0x0 */ - uint32_t dac_dsm_scaling_factor : 4; /* [ 9: 6], r/w, 0xf */ - uint32_t dac_dsm_scaling_en : 1; /* [ 10], r/w, 0x1 */ - uint32_t dac_dsm_dither_amp : 3; /* [13:11], r/w, 0x0 */ - uint32_t dac_dsm_dither_en : 1; /* [ 14], r/w, 0x1 */ - uint32_t dac_dsm_dither_prbs_mode : 2; /* [16:15], r/w, 0x0 */ - uint32_t reserved_17_20 : 4; /* [20:17], rsvd, 0x0 */ - uint32_t mix_1_sel : 2; /* [22:21], r/w, 0x0 */ - uint32_t mix_1_mode : 2; /* [24:23], r/w, 0x0 */ - uint32_t mix_1_att_mode1 : 3; /* [27:25], r/w, 0x0 */ - uint32_t mix_1_att_mode2 : 3; /* [30:28], r/w, 0x0 */ - uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dac_1; - - /* 0x18 : aec_0 */ - union { - struct { - uint32_t reserved_0_4 : 5; /* [ 4: 0], rsvd, 0x0 */ - uint32_t aec_0_atten_mode : 3; /* [ 7: 5], r/w, 0x0 */ - uint32_t aec_1_atten_mode : 3; /* [10: 8], r/w, 0x0 */ - uint32_t aec_record_vld_4s_div : 2; /* [12:11], r/w, 0x0 */ - uint32_t aec_record_vld_4s_en : 1; /* [ 13], r/w, 0x0 */ - uint32_t reserved_14_31 : 18; /* [31:14], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } aec_0; - - /* 0x1C : pdm_0 */ - union { - struct { - uint32_t pdm_0_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t pdm_1_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t pdm_2_en : 1; /* [ 2], r/w, 0x0 */ - uint32_t adc_0_pdm_sel : 3; /* [ 5: 3], r/w, 0x0 */ - uint32_t adc_1_pdm_sel : 3; /* [ 8: 6], r/w, 0x1 */ - uint32_t adc_2_pdm_sel : 3; /* [11: 9], r/w, 0x2 */ - uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } pdm_0; - - /* 0x20 : rsvd0 */ - union { - struct { - uint32_t rsvd0 : 32; /* [31: 0], r/w, 0xffff */ - } BF; - uint32_t WORD; - } rsvd0; - - /* 0x24 : dbg_0 */ - union { - struct { - uint32_t aud_sin_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t aud_sin_step : 3; /* [ 3: 1], r/w, 0x2 */ - uint32_t reserved_4_17 : 14; /* [17: 4], rsvd, 0x0 */ - uint32_t audio_test_out_sel : 2; /* [19:18], r/w, 0x0 */ - uint32_t dac_test_clkin_en : 1; /* [ 20], r/w, 0x0 */ - uint32_t adc_test_clkin_en : 1; /* [ 21], r/w, 0x0 */ - uint32_t dac_test_din_en : 1; /* [ 22], r/w, 0x0 */ - uint32_t adc_test_din_en : 1; /* [ 23], r/w, 0x0 */ - uint32_t aud_test_read_sel : 6; /* [29:24], r/w, 0x0 */ - uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dbg_0; - - /* 0x28 : dbg_1 */ - union { - struct { - uint32_t aud_test_read : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } dbg_1; - - /* 0x2C : dbg_2 */ - union { - struct { - uint32_t adc_fir_4s_val : 20; /* [19: 0], r/w, 0x0 */ - uint32_t adc_0_fir_4s_en : 1; /* [ 20], r/w, 0x0 */ - uint32_t adc_1_fir_4s_en : 1; /* [ 21], r/w, 0x0 */ - uint32_t adc_2_fir_4s_en : 1; /* [ 22], r/w, 0x0 */ - uint32_t adc_in_0_test_sel : 1; /* [ 23], r/w, 0x0 */ - uint32_t adc_in_1_test_sel : 1; /* [ 24], r/w, 0x0 */ - uint32_t adc_in_2_test_sel : 1; /* [ 25], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dbg_2; - - /* 0x30 : dbg_3 */ - union { - struct { - uint32_t dac_4s_val : 20; /* [19: 0], r/w, 0x0 */ - uint32_t dac_dwa_0_4s_en : 1; /* [ 20], r/w, 0x0 */ - uint32_t dac_dwa_1_4s_en : 1; /* [ 21], r/w, 0x0 */ - uint32_t dac_in_0_test_sel : 1; /* [ 22], r/w, 0x0 */ - uint32_t dac_in_1_test_sel : 1; /* [ 23], r/w, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dbg_3; - - /* 0x34 : dbg_4 */ - union { - struct { - uint32_t adc_in_ratio_4s_val : 1; /* [ 0], r/w, 0x0 */ - uint32_t adc_in_ch0_ratio_4s_val : 1; /* [ 1], r/w, 0x0 */ - uint32_t adc_in_ch1_ratio_4s_val : 1; /* [ 2], r/w, 0x0 */ - uint32_t adc_in_ch2_ratio_4s_val : 1; /* [ 3], r/w, 0x0 */ - uint32_t pdm_in_ratio_4s_val : 1; /* [ 4], r/w, 0x0 */ - uint32_t pdm_in_ratio_4s : 1; /* [ 5], r/w, 0x0 */ - uint32_t dac_out_ratio_4s_val : 2; /* [ 7: 6], r/w, 0x0 */ - uint32_t aec_fs_rate_4s_val : 3; /* [10: 8], r/w, 0x0 */ - uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dbg_4; - - /* 0x38 reserved */ - uint8_t RESERVED0x38[72]; - - /* 0x80 : rx_fifo_ctrl */ - union { - struct { - uint32_t rx_fifo_flush : 1; /* [ 0], w1p, 0x0 */ - uint32_t rxo_int_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t rxu_int_en : 1; /* [ 2], r/w, 0x0 */ - uint32_t rxa_int_en : 1; /* [ 3], r/w, 0x0 */ - uint32_t rx_drq_en : 1; /* [ 4], r/w, 0x0 */ - uint32_t rx_data_res : 1; /* [ 5], r/w, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t rx_ch_en : 5; /* [12: 8], r/w, 0x0 */ - uint32_t reserved_13 : 1; /* [ 13], rsvd, 0x0 */ - uint32_t rx_drq_cnt : 2; /* [15:14], r/w, 0x0 */ - uint32_t rx_trg_level : 7; /* [22:16], r/w, 0x27 */ - uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */ - uint32_t rx_data_mode : 2; /* [25:24], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } rx_fifo_ctrl; - - /* 0x84 : rx_fifo_status */ - union { - struct { - uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */ - uint32_t rxo_int : 1; /* [ 1], r, 0x0 */ - uint32_t rxu_int : 1; /* [ 2], r, 0x0 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t rxa_int : 1; /* [ 4], r, 0x0 */ - uint32_t reserved_5_15 : 11; /* [15: 5], rsvd, 0x0 */ - uint32_t rxa_cnt : 7; /* [22:16], r, 0x0 */ - uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */ - uint32_t rxa : 1; /* [ 24], r, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } rx_fifo_status; - - /* 0x88 : rx_fifo_data */ - union { - struct { - uint32_t rx_data : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } rx_fifo_data; - - /* 0x8C : tx_fifo_ctrl */ - union { - struct { - uint32_t tx_fifo_flush : 1; /* [ 0], w1p, 0x0 */ - uint32_t txo_int_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t txu_int_en : 1; /* [ 2], r/w, 0x0 */ - uint32_t txa_int_en : 1; /* [ 3], r/w, 0x0 */ - uint32_t tx_drq_en : 1; /* [ 4], r/w, 0x0 */ - uint32_t tx_data_res : 1; /* [ 5], r/w, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t tx_ch_en : 2; /* [ 9: 8], r/w, 0x0 */ - uint32_t reserved_10_13 : 4; /* [13:10], rsvd, 0x0 */ - uint32_t tx_drq_cnt : 2; /* [15:14], r/w, 0x0 */ - uint32_t tx_trg_level : 6; /* [21:16], r/w, 0xf */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t tx_data_mode : 2; /* [25:24], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } tx_fifo_ctrl; - - /* 0x90 : tx_fifo_status */ - union { - struct { - uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */ - uint32_t txo_int : 1; /* [ 1], r, 0x0 */ - uint32_t txu_int : 1; /* [ 2], r, 0x0 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t txa_int : 1; /* [ 4], r, 0x0 */ - uint32_t reserved_5_15 : 11; /* [15: 5], rsvd, 0x0 */ - uint32_t txa_cnt : 6; /* [21:16], r, 0x20 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t txa : 1; /* [ 24], r, 0x1 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } tx_fifo_status; - - /* 0x94 : tx_fifo_data */ - union { - struct { - uint32_t tx_data : 32; /* [31: 0], w, 0x0 */ - } BF; - uint32_t WORD; - } tx_fifo_data; - - /* 0x98 reserved */ - uint8_t RESERVED0x98[360]; - - /* 0x200 : peq_00_b0 */ - union { - struct { - uint32_t peq_00_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_00_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_00_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_00_b0; - - /* 0x204 : peq_00_b1 */ - union { - struct { - uint32_t peq_00_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_00_b1; - - /* 0x208 : peq_00_b2 */ - union { - struct { - uint32_t peq_00_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_00_b2; - - /* 0x20C : peq_00_a1 */ - union { - struct { - uint32_t peq_00_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_00_a1; - - /* 0x210 : peq_00_a2 */ - union { - struct { - uint32_t peq_00_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_00_a2; - - /* 0x214 : peq_01_b0 */ - union { - struct { - uint32_t peq_01_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_01_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_01_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_01_b0; - - /* 0x218 : peq_01_b1 */ - union { - struct { - uint32_t peq_01_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_01_b1; - - /* 0x21C : peq_01_b2 */ - union { - struct { - uint32_t peq_01_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_01_b2; - - /* 0x220 : peq_01_a1 */ - union { - struct { - uint32_t peq_01_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_01_a1; - - /* 0x224 : peq_01_a2 */ - union { - struct { - uint32_t peq_01_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_01_a2; - - /* 0x228 : peq_02_b0 */ - union { - struct { - uint32_t peq_02_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_02_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_02_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_02_b0; - - /* 0x22C : peq_02_b1 */ - union { - struct { - uint32_t peq_02_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_02_b1; - - /* 0x230 : peq_02_b2 */ - union { - struct { - uint32_t peq_02_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_02_b2; - - /* 0x234 : peq_02_a1 */ - union { - struct { - uint32_t peq_02_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_02_a1; - - /* 0x238 : peq_02_a2 */ - union { - struct { - uint32_t peq_02_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_02_a2; - - /* 0x23C : peq_03_b0 */ - union { - struct { - uint32_t peq_03_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_03_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_03_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_03_b0; - - /* 0x240 : peq_03_b1 */ - union { - struct { - uint32_t peq_03_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_03_b1; - - /* 0x244 : peq_03_b2 */ - union { - struct { - uint32_t peq_03_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_03_b2; - - /* 0x248 : peq_03_a1 */ - union { - struct { - uint32_t peq_03_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_03_a1; - - /* 0x24C : peq_03_a2 */ - union { - struct { - uint32_t peq_03_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_03_a2; - - /* 0x250 : peq_04_b0 */ - union { - struct { - uint32_t peq_04_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_04_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_04_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_04_b0; - - /* 0x254 : peq_04_b1 */ - union { - struct { - uint32_t peq_04_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_04_b1; - - /* 0x258 : peq_04_b2 */ - union { - struct { - uint32_t peq_04_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_04_b2; - - /* 0x25C : peq_04_a1 */ - union { - struct { - uint32_t peq_04_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_04_a1; - - /* 0x260 : peq_04_a2 */ - union { - struct { - uint32_t peq_04_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_04_a2; - - /* 0x264 : peq_05_b0 */ - union { - struct { - uint32_t peq_05_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_05_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_05_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_05_b0; - - /* 0x268 : peq_05_b1 */ - union { - struct { - uint32_t peq_05_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_05_b1; - - /* 0x26C : peq_05_b2 */ - union { - struct { - uint32_t peq_05_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_05_b2; - - /* 0x270 : peq_05_a1 */ - union { - struct { - uint32_t peq_05_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_05_a1; - - /* 0x274 : peq_05_a2 */ - union { - struct { - uint32_t peq_05_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_05_a2; - - /* 0x278 : peq_06_b0 */ - union { - struct { - uint32_t peq_06_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_06_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_06_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_06_b0; - - /* 0x27C : peq_06_b1 */ - union { - struct { - uint32_t peq_06_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_06_b1; - - /* 0x280 : peq_06_b2 */ - union { - struct { - uint32_t peq_06_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_06_b2; - - /* 0x284 : peq_06_a1 */ - union { - struct { - uint32_t peq_06_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_06_a1; - - /* 0x288 : peq_06_a2 */ - union { - struct { - uint32_t peq_06_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_06_a2; - - /* 0x28C : peq_07_b0 */ - union { - struct { - uint32_t peq_07_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_07_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_07_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_07_b0; - - /* 0x290 : peq_07_b1 */ - union { - struct { - uint32_t peq_07_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_07_b1; - - /* 0x294 : peq_07_b2 */ - union { - struct { - uint32_t peq_07_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_07_b2; - - /* 0x298 : peq_07_a1 */ - union { - struct { - uint32_t peq_07_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_07_a1; - - /* 0x29C : peq_07_a2 */ - union { - struct { - uint32_t peq_07_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_07_a2; - - /* 0x2A0 : peq_08_b0 */ - union { - struct { - uint32_t peq_08_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_08_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_08_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_08_b0; - - /* 0x2A4 : peq_08_b1 */ - union { - struct { - uint32_t peq_08_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_08_b1; - - /* 0x2A8 : peq_08_b2 */ - union { - struct { - uint32_t peq_08_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_08_b2; - - /* 0x2AC : peq_08_a1 */ - union { - struct { - uint32_t peq_08_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_08_a1; - - /* 0x2B0 : peq_08_a2 */ - union { - struct { - uint32_t peq_08_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_08_a2; - - /* 0x2B4 : peq_09_b0 */ - union { - struct { - uint32_t peq_09_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_09_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_09_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_09_b0; - - /* 0x2B8 : peq_09_b1 */ - union { - struct { - uint32_t peq_09_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_09_b1; - - /* 0x2BC : peq_09_b2 */ - union { - struct { - uint32_t peq_09_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_09_b2; - - /* 0x2C0 : peq_09_a1 */ - union { - struct { - uint32_t peq_09_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_09_a1; - - /* 0x2C4 : peq_09_a2 */ - union { - struct { - uint32_t peq_09_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_09_a2; - - /* 0x2C8 : peq_10_b0 */ - union { - struct { - uint32_t peq_10_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_10_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_10_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_10_b0; - - /* 0x2CC : peq_10_b1 */ - union { - struct { - uint32_t peq_10_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_10_b1; - - /* 0x2D0 : peq_10_b2 */ - union { - struct { - uint32_t peq_10_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_10_b2; - - /* 0x2D4 : peq_10_a1 */ - union { - struct { - uint32_t peq_10_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_10_a1; - - /* 0x2D8 : peq_10_a2 */ - union { - struct { - uint32_t peq_10_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_10_a2; - - /* 0x2DC : peq_11_b0 */ - union { - struct { - uint32_t peq_11_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_11_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_11_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_11_b0; - - /* 0x2E0 : peq_11_b1 */ - union { - struct { - uint32_t peq_11_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_11_b1; - - /* 0x2E4 : peq_11_b2 */ - union { - struct { - uint32_t peq_11_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_11_b2; - - /* 0x2E8 : peq_11_a1 */ - union { - struct { - uint32_t peq_11_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_11_a1; - - /* 0x2EC : peq_11_a2 */ - union { - struct { - uint32_t peq_11_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_11_a2; - - /* 0x2F0 : peq_12_b0 */ - union { - struct { - uint32_t peq_12_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_12_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_12_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_12_b0; - - /* 0x2F4 : peq_12_b1 */ - union { - struct { - uint32_t peq_12_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_12_b1; - - /* 0x2F8 : peq_12_b2 */ - union { - struct { - uint32_t peq_12_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_12_b2; - - /* 0x2FC : peq_12_a1 */ - union { - struct { - uint32_t peq_12_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_12_a1; - - /* 0x300 : peq_12_a2 */ - union { - struct { - uint32_t peq_12_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_12_a2; - - /* 0x304 : peq_13_b0 */ - union { - struct { - uint32_t peq_13_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_13_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_13_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_13_b0; - - /* 0x308 : peq_13_b1 */ - union { - struct { - uint32_t peq_13_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_13_b1; - - /* 0x30C : peq_13_b2 */ - union { - struct { - uint32_t peq_13_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_13_b2; - - /* 0x310 : peq_13_a1 */ - union { - struct { - uint32_t peq_13_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_13_a1; - - /* 0x314 : peq_13_a2 */ - union { - struct { - uint32_t peq_13_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_13_a2; - - /* 0x318 : peq_14_b0 */ - union { - struct { - uint32_t peq_14_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_14_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_14_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_14_b0; - - /* 0x31C : peq_14_b1 */ - union { - struct { - uint32_t peq_14_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_14_b1; - - /* 0x320 : peq_14_b2 */ - union { - struct { - uint32_t peq_14_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_14_b2; - - /* 0x324 : peq_14_a1 */ - union { - struct { - uint32_t peq_14_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_14_a1; - - /* 0x328 : peq_14_a2 */ - union { - struct { - uint32_t peq_14_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_14_a2; - - /* 0x32C : peq_15_b0 */ - union { - struct { - uint32_t peq_15_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_15_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_15_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_15_b0; - - /* 0x330 : peq_15_b1 */ - union { - struct { - uint32_t peq_15_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_15_b1; - - /* 0x334 : peq_15_b2 */ - union { - struct { - uint32_t peq_15_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_15_b2; - - /* 0x338 : peq_15_a1 */ - union { - struct { - uint32_t peq_15_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_15_a1; - - /* 0x33C : peq_15_a2 */ - union { - struct { - uint32_t peq_15_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_15_a2; - - /* 0x340 : peq_16_b0 */ - union { - struct { - uint32_t peq_16_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_16_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_16_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_16_b0; - - /* 0x344 : peq_16_b1 */ - union { - struct { - uint32_t peq_16_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_16_b1; - - /* 0x348 : peq_16_b2 */ - union { - struct { - uint32_t peq_16_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_16_b2; - - /* 0x34C : peq_16_a1 */ - union { - struct { - uint32_t peq_16_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_16_a1; - - /* 0x350 : peq_16_a2 */ - union { - struct { - uint32_t peq_16_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_16_a2; - - /* 0x354 : peq_17_b0 */ - union { - struct { - uint32_t peq_17_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_17_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_17_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_17_b0; - - /* 0x358 : peq_17_b1 */ - union { - struct { - uint32_t peq_17_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_17_b1; - - /* 0x35C : peq_17_b2 */ - union { - struct { - uint32_t peq_17_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_17_b2; - - /* 0x360 : peq_17_a1 */ - union { - struct { - uint32_t peq_17_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_17_a1; - - /* 0x364 : peq_17_a2 */ - union { - struct { - uint32_t peq_17_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_17_a2; - - /* 0x368 : peq_18_b0 */ - union { - struct { - uint32_t peq_18_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_18_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_18_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_18_b0; - - /* 0x36C : peq_18_b1 */ - union { - struct { - uint32_t peq_18_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_18_b1; - - /* 0x370 : peq_18_b2 */ - union { - struct { - uint32_t peq_18_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_18_b2; - - /* 0x374 : peq_18_a1 */ - union { - struct { - uint32_t peq_18_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_18_a1; - - /* 0x378 : peq_18_a2 */ - union { - struct { - uint32_t peq_18_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_18_a2; - - /* 0x37C : peq_19_b0 */ - union { - struct { - uint32_t peq_19_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_19_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_19_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_19_b0; - - /* 0x380 : peq_19_b1 */ - union { - struct { - uint32_t peq_19_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_19_b1; - - /* 0x384 : peq_19_b2 */ - union { - struct { - uint32_t peq_19_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_19_b2; - - /* 0x388 : peq_19_a1 */ - union { - struct { - uint32_t peq_19_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_19_a1; - - /* 0x38C : peq_19_a2 */ - union { - struct { - uint32_t peq_19_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_19_a2; - - /* 0x390 : peq_20_b0 */ - union { - struct { - uint32_t peq_20_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_20_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_20_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_29 : 8; /* [29:22], rsvd, 0x0 */ - uint32_t adc_peq_in_sel : 2; /* [31:30], r/w, 0x3 */ - } BF; - uint32_t WORD; - } peq_20_b0; - - /* 0x394 : peq_20_b1 */ - union { - struct { - uint32_t peq_20_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_20_b1; - - /* 0x398 : peq_20_b2 */ - union { - struct { - uint32_t peq_20_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_20_b2; - - /* 0x39C : peq_20_a1 */ - union { - struct { - uint32_t peq_20_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_20_a1; - - /* 0x3A0 : peq_20_a2 */ - union { - struct { - uint32_t peq_20_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_20_a2; - - /* 0x3A4 : peq_21_b0 */ - union { - struct { - uint32_t peq_21_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_21_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_21_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_21_b0; - - /* 0x3A8 : peq_21_b1 */ - union { - struct { - uint32_t peq_21_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_21_b1; - - /* 0x3AC : peq_21_b2 */ - union { - struct { - uint32_t peq_21_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_21_b2; - - /* 0x3B0 : peq_21_a1 */ - union { - struct { - uint32_t peq_21_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_21_a1; - - /* 0x3B4 : peq_21_a2 */ - union { - struct { - uint32_t peq_21_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_21_a2; - - /* 0x3B8 : peq_22_b0 */ - union { - struct { - uint32_t peq_22_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_22_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_22_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_22_b0; - - /* 0x3BC : peq_22_b1 */ - union { - struct { - uint32_t peq_22_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_22_b1; - - /* 0x3C0 : peq_22_b2 */ - union { - struct { - uint32_t peq_22_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_22_b2; - - /* 0x3C4 : peq_22_a1 */ - union { - struct { - uint32_t peq_22_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_22_a1; - - /* 0x3C8 : peq_22_a2 */ - union { - struct { - uint32_t peq_22_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_22_a2; - - /* 0x3CC : peq_23_b0 */ - union { - struct { - uint32_t peq_23_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_23_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_23_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_23_b0; - - /* 0x3D0 : peq_23_b1 */ - union { - struct { - uint32_t peq_23_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_23_b1; - - /* 0x3D4 : peq_23_b2 */ - union { - struct { - uint32_t peq_23_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_23_b2; - - /* 0x3D8 : peq_23_a1 */ - union { - struct { - uint32_t peq_23_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_23_a1; - - /* 0x3DC : peq_23_a2 */ - union { - struct { - uint32_t peq_23_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_23_a2; - - /* 0x3E0 : peq_24_b0 */ - union { - struct { - uint32_t peq_24_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_24_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_24_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_24_b0; - - /* 0x3E4 : peq_24_b1 */ - union { - struct { - uint32_t peq_24_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_24_b1; - - /* 0x3E8 : peq_24_b2 */ - union { - struct { - uint32_t peq_24_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_24_b2; - - /* 0x3EC : peq_24_a1 */ - union { - struct { - uint32_t peq_24_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_24_a1; - - /* 0x3F0 : peq_24_a2 */ - union { - struct { - uint32_t peq_24_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_24_a2; - - /* 0x3f4 reserved */ - uint8_t RESERVED0x3f4[12]; - - /* 0x400 : adc_h */ - union { - struct { - uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */ - uint32_t adc_h_ctrl_rmp_rate : 4; /* [ 5: 2], r/w, 0x1 */ - uint32_t adc_h_ctrl_zcd_rate : 4; /* [ 9: 6], r/w, 0x2 */ - uint32_t adc_h_ctrl_mode : 2; /* [11:10], r/w, 0x0 */ - uint32_t adc_h_volume_update : 1; /* [ 12], r/w, 0x0 */ - uint32_t adc_h_volume : 9; /* [21:13], r, 0x0 */ - uint32_t adc_h_mute_rmpup_rate : 4; /* [25:22], r/w, 0x1 */ - uint32_t adc_h_mute_rmpdn_rate : 4; /* [29:26], r/w, 0x1 */ - uint32_t adc_h_mute_softmode : 1; /* [ 30], r/w, 0x0 */ - uint32_t adc_h_mute : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } adc_h; - - /* 0x404 : adc_h_misc */ - union { - struct { - uint32_t reserved_0_27 : 28; /* [27: 0], rsvd, 0x0 */ - uint32_t adc_h_ctrl_zcd_timeout : 4; /* [31:28], r/w, 0x4 */ - } BF; - uint32_t WORD; - } adc_h_misc; - - /* 0x408 : adc_s0 */ - union { - struct { - uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */ - uint32_t adc_s0_ctrl_rmp_rate : 4; /* [ 5: 2], r/w, 0x1 */ - uint32_t adc_s0_ctrl_zcd_rate : 4; /* [ 9: 6], r/w, 0x2 */ - uint32_t adc_s0_ctrl_mode : 2; /* [11:10], r/w, 0x2 */ - uint32_t adc_s0_volume_update : 1; /* [ 12], r/w, 0x0 */ - uint32_t adc_s0_volume : 9; /* [21:13], r/w, 0x0 */ - uint32_t adc_s0_mute_rmpup_rate : 4; /* [25:22], r/w, 0x1 */ - uint32_t adc_s0_mute_rmpdn_rate : 4; /* [29:26], r/w, 0x1 */ - uint32_t adc_s0_mute_softmode : 1; /* [ 30], r/w, 0x0 */ - uint32_t adc_s0_mute : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } adc_s0; - - /* 0x40C : adc_s0_misc */ - union { - struct { - uint32_t adc_s012_volume_update : 1; /* [ 0], r/w, 0x1 */ - uint32_t adc_s012_mute : 1; /* [ 1], r/w, 0x1 */ - uint32_t reserved_2_27 : 26; /* [27: 2], rsvd, 0x0 */ - uint32_t adc_s0_ctrl_zcd_timeout : 4; /* [31:28], r/w, 0x4 */ - } BF; - uint32_t WORD; - } adc_s0_misc; - - /* 0x410 : adc_s1 */ - union { - struct { - uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */ - uint32_t adc_s1_ctrl_rmp_rate : 4; /* [ 5: 2], r/w, 0x1 */ - uint32_t adc_s1_ctrl_zcd_rate : 4; /* [ 9: 6], r/w, 0x2 */ - uint32_t adc_s1_ctrl_mode : 2; /* [11:10], r/w, 0x2 */ - uint32_t adc_s1_volume_update : 1; /* [ 12], r/w, 0x0 */ - uint32_t adc_s1_volume : 9; /* [21:13], r/w, 0x0 */ - uint32_t adc_s1_mute_rmpup_rate : 4; /* [25:22], r/w, 0x1 */ - uint32_t adc_s1_mute_rmpdn_rate : 4; /* [29:26], r/w, 0x1 */ - uint32_t adc_s1_mute_softmode : 1; /* [ 30], r/w, 0x0 */ - uint32_t adc_s1_mute : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } adc_s1; - - /* 0x414 : adc_s1_misc */ - union { - struct { - uint32_t reserved_0_27 : 28; /* [27: 0], rsvd, 0x0 */ - uint32_t adc_s1_ctrl_zcd_timeout : 4; /* [31:28], r/w, 0x4 */ - } BF; - uint32_t WORD; - } adc_s1_misc; - - /* 0x418 : adc_s2 */ - union { - struct { - uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */ - uint32_t adc_s2_ctrl_rmp_rate : 4; /* [ 5: 2], r/w, 0x1 */ - uint32_t adc_s2_ctrl_zcd_rate : 4; /* [ 9: 6], r/w, 0x2 */ - uint32_t adc_s2_ctrl_mode : 2; /* [11:10], r/w, 0x2 */ - uint32_t adc_s2_volume_update : 1; /* [ 12], r/w, 0x0 */ - uint32_t adc_s2_volume : 9; /* [21:13], r/w, 0x0 */ - uint32_t adc_s2_mute_rmpup_rate : 4; /* [25:22], r/w, 0x1 */ - uint32_t adc_s2_mute_rmpdn_rate : 4; /* [29:26], r/w, 0x1 */ - uint32_t adc_s2_mute_softmode : 1; /* [ 30], r/w, 0x0 */ - uint32_t adc_s2_mute : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } adc_s2; - - /* 0x41C : adc_s2_misc */ - union { - struct { - uint32_t reserved_0_27 : 28; /* [27: 0], rsvd, 0x0 */ - uint32_t adc_s2_ctrl_zcd_timeout : 4; /* [31:28], r/w, 0x4 */ - } BF; - uint32_t WORD; - } adc_s2_misc; - - /* 0x420 : adc_agc_0 */ - union { - struct { - uint32_t adc_agc_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_2 : 2; /* [ 2: 1], rsvd, 0x0 */ - uint32_t agc_min_gain_qdb : 9; /* [11: 3], r/w, 0x1a0 */ - uint32_t agc_max_gain_qdb : 9; /* [20:12], r/w, 0x18 */ - uint32_t agc_force_gain_ind : 10; /* [30:21], r/w, 0x0 */ - uint32_t agc_force_gain_en : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } adc_agc_0; - - /* 0x424 : adc_agc_1 */ - union { - struct { - uint32_t adc0_pga_hw_ctrl : 1; /* [ 0], r/w, 0x0 */ - uint32_t adc1_pga_hw_ctrl : 1; /* [ 1], r/w, 0x0 */ - uint32_t adc2_pga_hw_ctrl : 1; /* [ 2], r/w, 0x0 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t agc_attack_time_ms : 4; /* [ 7: 4], r/w, 0x1 */ - uint32_t agc_decay_time_ms : 4; /* [11: 8], r/w, 0x5 */ - uint32_t agc_hold_time_ms : 4; /* [15:12], r/w, 0x6 */ - uint32_t agc_level_hyst_decay : 5; /* [20:16], r/w, 0x4 */ - uint32_t agc_level_hyst_attack : 5; /* [25:21], r/w, 0x4 */ - uint32_t agc_level_target : 6; /* [31:26], r/w, 0x34 */ - } BF; - uint32_t WORD; - } adc_agc_1; - - /* 0x428 : adc_agc_2 */ - union { - struct { - uint32_t agc_noise_enter_time_ms : 7; /* [ 6: 0], r/w, 0x32 */ - uint32_t agc_silence_gain_wait_ms : 4; /* [10: 7], r/w, 0x0 */ - uint32_t agc_silence_gain_qdb : 10; /* [20:11], r/w, 0x0 */ - uint32_t agc_noise_gate_hyst : 3; /* [23:21], r/w, 0x2 */ - uint32_t agc_noise_gate_th : 8; /* [31:24], r/w, 0xba */ - } BF; - uint32_t WORD; - } adc_agc_2; - - /* 0x42C : adc_agc_3 */ - union { - struct { - uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */ - uint32_t agc_pga_ctrl_en : 1; /* [ 2], r/w, 0x0 */ - uint32_t agc_average_time : 5; /* [ 7: 3], r/w, 0x4 */ - uint32_t agc_release_time : 5; /* [12: 8], r/w, 0x10 */ - uint32_t agc_attack_time : 5; /* [17:13], r/w, 0x6 */ - uint32_t agc_detect_mode : 1; /* [ 18], r/w, 0x0 */ - uint32_t agc_src_select : 2; /* [20:19], r/w, 0x3 */ - uint32_t agc_dbv_settle_time : 4; /* [24:21], r/w, 0x5 */ - uint32_t agc_noise_exit_time_ms : 7; /* [31:25], r/w, 0x1 */ - } BF; - uint32_t WORD; - } adc_agc_3; - - /* 0x430 : audio_status */ - union { - struct { - uint32_t adc_h0_busy : 1; /* [ 0], r, 0x0 */ - uint32_t adc_h0_mute_done : 1; /* [ 1], r, 0x1 */ - uint32_t adc_h1_busy : 1; /* [ 2], r, 0x0 */ - uint32_t adc_h1_mute_done : 1; /* [ 3], r, 0x1 */ - uint32_t adc_h2_busy : 1; /* [ 4], r, 0x0 */ - uint32_t adc_h2_mute_done : 1; /* [ 5], r, 0x1 */ - uint32_t adc_s0_int : 1; /* [ 6], r, 0x0 */ - uint32_t adc_s0_int_clr : 1; /* [ 7], r/w, 0x0 */ - uint32_t adc_s1_int : 1; /* [ 8], r, 0x0 */ - uint32_t adc_s1_int_clr : 1; /* [ 9], r/w, 0x0 */ - uint32_t adc_s2_int : 1; /* [ 10], r, 0x0 */ - uint32_t adc_s2_int_clr : 1; /* [ 11], r/w, 0x0 */ - uint32_t dac_h0_busy : 1; /* [ 12], r, 0x0 */ - uint32_t dac_h0_mute_done : 1; /* [ 13], r, 0x1 */ - uint32_t dac_h1_busy : 1; /* [ 14], r, 0x0 */ - uint32_t dac_h1_mute_done : 1; /* [ 15], r, 0x1 */ - uint32_t dac_s0_int : 1; /* [ 16], r, 0x0 */ - uint32_t dac_s0_int_clr : 1; /* [ 17], r/w, 0x0 */ - uint32_t dac_s1_int : 1; /* [ 18], r, 0x0 */ - uint32_t dac_s1_int_clr : 1; /* [ 19], r/w, 0x0 */ - uint32_t ngt_amute : 1; /* [ 20], r, 0x0 */ - uint32_t ngt_dmute : 1; /* [ 21], r, 0x0 */ - uint32_t ngt_dmute_done : 1; /* [ 22], r, 0x1 */ - uint32_t zd_amute : 1; /* [ 23], r, 0x0 */ - uint32_t audio_int_all : 1; /* [ 24], r, 0x0 */ - uint32_t vad_int : 1; /* [ 25], r, 0x0 */ - uint32_t vad_int_clr : 1; /* [ 26], r/w, 0x0 */ - uint32_t vad_int_set : 1; /* [ 27], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } audio_status; - - /* 0x434 : dac_s0 */ - union { - struct { - uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */ - uint32_t dac_s0_ctrl_rmp_rate : 4; /* [ 5: 2], r/w, 0x6 */ - uint32_t dac_s0_ctrl_zcd_rate : 4; /* [ 9: 6], r/w, 0x2 */ - uint32_t dac_s0_ctrl_mode : 2; /* [11:10], r/w, 0x2 */ - uint32_t dac_s0_volume_update : 1; /* [ 12], r/w, 0x0 */ - uint32_t dac_s0_volume : 9; /* [21:13], r/w, 0x0 */ - uint32_t dac_s0_mute_rmpup_rate : 4; /* [25:22], r/w, 0x0 */ - uint32_t dac_s0_mute_rmpdn_rate : 4; /* [29:26], r/w, 0x6 */ - uint32_t dac_s0_mute_softmode : 1; /* [ 30], r/w, 0x1 */ - uint32_t dac_s0_mute : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dac_s0; - - /* 0x438 : dac_s0_misc */ - union { - struct { - uint32_t dac_s01_volume_update : 1; /* [ 0], r/w, 0x1 */ - uint32_t dac_s01_mute : 1; /* [ 1], r/w, 0x1 */ - uint32_t reserved_2_27 : 26; /* [27: 2], rsvd, 0x0 */ - uint32_t dac_s0_ctrl_zcd_timeout : 4; /* [31:28], r/w, 0x4 */ - } BF; - uint32_t WORD; - } dac_s0_misc; - - /* 0x43C : dac_s1 */ - union { - struct { - uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */ - uint32_t dac_s1_ctrl_rmp_rate : 4; /* [ 5: 2], r/w, 0x6 */ - uint32_t dac_s1_ctrl_zcd_rate : 4; /* [ 9: 6], r/w, 0x2 */ - uint32_t dac_s1_ctrl_mode : 2; /* [11:10], r/w, 0x2 */ - uint32_t dac_s1_volume_update : 1; /* [ 12], r/w, 0x0 */ - uint32_t dac_s1_volume : 9; /* [21:13], r/w, 0x0 */ - uint32_t dac_s1_mute_rmpup_rate : 4; /* [25:22], r/w, 0x0 */ - uint32_t dac_s1_mute_rmpdn_rate : 4; /* [29:26], r/w, 0x6 */ - uint32_t dac_s1_mute_softmode : 1; /* [ 30], r/w, 0x1 */ - uint32_t dac_s1_mute : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dac_s1; - - /* 0x440 : dac_s1_misc */ - union { - struct { - uint32_t reserved_0_27 : 28; /* [27: 0], rsvd, 0x0 */ - uint32_t dac_s1_ctrl_zcd_timeout : 4; /* [31:28], r/w, 0x4 */ - } BF; - uint32_t WORD; - } dac_s1_misc; - - /* 0x444 : dac_drc_0 */ - union { - struct { - uint32_t reserved_0_7 : 8; /* [ 7: 0], rsvd, 0x0 */ - uint32_t drc_ngt_downsample_en : 1; /* [ 8], r/w, 0x0 */ - uint32_t drc_rls_time : 5; /* [13: 9], r/w, 0x4 */ - uint32_t drc_att_time : 5; /* [18:14], r/w, 0xa */ - uint32_t drc_avg_time : 5; /* [23:19], r/w, 0x8 */ - uint32_t drc_avg_en : 1; /* [ 24], r/w, 0x1 */ - uint32_t drc_avg_sel : 2; /* [26:25], r/w, 0x3 */ - uint32_t drc_peak_sel : 2; /* [28:27], r/w, 0x3 */ - uint32_t drc_raw_sel : 2; /* [30:29], r/w, 0x3 */ - uint32_t drc_en : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dac_drc_0; - - /* 0x448 : dac_drc_1 */ - union { - struct { - uint32_t drc_release_time : 4; /* [ 3: 0], r/w, 0x1 */ - uint32_t drc_attack_time : 4; /* [ 7: 4], r/w, 0x1 */ - uint32_t drc_makeup_gain : 4; /* [11: 8], r/w, 0x0 */ - uint32_t drc_slope_mode_e : 2; /* [13:12], r/w, 0x1 */ - uint32_t drc_slope_mode_c : 2; /* [15:14], r/w, 0x1 */ - uint32_t drc_threshold_e : 6; /* [21:16], r/w, 0x24 */ - uint32_t drc_threshold_c : 5; /* [26:22], r/w, 0x10 */ - uint32_t drc_threshold_l : 5; /* [31:27], r/w, 0x8 */ - } BF; - uint32_t WORD; - } dac_drc_1; - - /* 0x44C : dac_ngt_0 */ - union { - struct { - uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */ - uint32_t ngt_amute_on : 1; /* [ 2], r/w, 0x0 */ - uint32_t ngt_dmute_on : 1; /* [ 3], r/w, 0x0 */ - uint32_t ngt_signal_hold_time_k : 4; /* [ 7: 4], r/w, 0x2 */ - uint32_t ngt_signal_hold_en : 1; /* [ 8], r/w, 0x1 */ - uint32_t ngt_noise_hold_time_k : 4; /* [12: 9], r/w, 0x8 */ - uint32_t ngt_noise_hold_en : 1; /* [ 13], r/w, 0x1 */ - uint32_t ngt_hysteresis : 2; /* [15:14], r/w, 0x2 */ - uint32_t ngt_threshold : 8; /* [23:16], r/w, 0xb5 */ - uint32_t ngt_avg_time : 5; /* [28:24], r/w, 0x2 */ - uint32_t ngt_src_sel : 2; /* [30:29], r/w, 0x3 */ - uint32_t ngt_en : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dac_ngt_0; - - /* 0x450 : dac_zd_0 */ - union { - struct { - uint32_t zd_time : 15; /* [14: 0], r/w, 0x200 */ - uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */ - uint32_t zd_en : 2; /* [17:16], r/w, 0x0 */ - uint32_t reserved_18_29 : 12; /* [29:18], rsvd, 0x0 */ - uint32_t dac_mute_hw_ctrl : 1; /* [ 30], r/w, 0x1 */ - uint32_t dac_mute : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dac_zd_0; - - /* 0x454 reserved */ - uint8_t RESERVED0x454[428]; - - /* 0x600 : vad_ctrl_0 */ - union { - struct { - uint32_t vad_nth_minlmt_en : 1; /* [ 0], r/w, 0x1 */ - uint32_t vad_nth_maxlmt_en : 1; /* [ 1], r/w, 0x1 */ - uint32_t vad_nbuf_monit_en : 1; /* [ 2], r/w, 0x1 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t vad_nbuf_monit_ctrl : 2; /* [ 5: 4], r/w, 0x1 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t vad_nbuf_len_ctrl : 3; /* [10: 8], r/w, 0x2 */ - uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */ - uint32_t vad_out_sel : 2; /* [13:12], r/w, 0x1 */ - uint32_t vad_frametime_ctrl : 2; /* [15:14], r/w, 0x1 */ - uint32_t vad_frameshift_ctrl : 3; /* [18:16], r/w, 0x0 */ - uint32_t vad_out : 1; /* [ 19], r, 0x0 */ - uint32_t vad_in_sel : 3; /* [22:20], r/w, 0x0 */ - uint32_t vad_en : 1; /* [ 23], r/w, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } vad_ctrl_0; - - /* 0x604 : vad_ctrl_1 */ - union { - struct { - uint32_t vad_nth_scale : 8; /* [ 7: 0], r/w, 0x33 */ - uint32_t vad_nth_bias : 16; /* [23: 8], r/w, 0x33 */ - uint32_t vad_nbuf_discard : 8; /* [31:24], r/w, 0x10 */ - } BF; - uint32_t WORD; - } vad_ctrl_1; - - /* 0x608 : vad_ctrl_2 */ - union { - struct { - uint32_t vad_nth_minlmt : 16; /* [15: 0], r/w, 0x66 */ - uint32_t vad_nth_maxlmt : 16; /* [31:16], r/w, 0x1400 */ - } BF; - uint32_t WORD; - } vad_ctrl_2; - - /* 0x60C : vad_ctrl_3 */ - union { - struct { - uint32_t vad_smooth_fall : 8; /* [ 7: 0], r/w, 0x80 */ - uint32_t vad_smooth_rise : 8; /* [15: 8], r/w, 0x10 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } vad_ctrl_3; - - /* 0x610 : vad_ctrl_4 */ - union { - struct { - uint32_t vad_ek : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } vad_ctrl_4; - - /* 0x614 : vad_ctrl_5 */ - union { - struct { - uint32_t vad_noise_th : 24; /* [23: 0], r, 0x6600 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } vad_ctrl_5; - - /* 0x618 reserved */ - uint8_t RESERVED0x618[232]; - - /* 0x700 : codec_power1 */ - union { - struct { - uint32_t micbias_pu : 1; /* [ 0], r/w, 0x0 */ - uint32_t micbias_chop_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t micbias_clk_chop_sel : 2; /* [ 3: 2], r/w, 0x2 */ - uint32_t micbias_vsel : 2; /* [ 5: 4], r/w, 0x2 */ - uint32_t padc_ibias_source : 1; /* [ 6], r/w, 0x0 */ - uint32_t padc_power_ten : 1; /* [ 7], r/w, 0x0 */ - uint32_t padc_power_tmux : 3; /* [10: 8], r/w, 0x0 */ - uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */ - uint32_t codec_vrda_en : 1; /* [ 12], r/w, 0x0 */ - uint32_t codec_ictrl_vcm : 2; /* [14:13], r/w, 0x2 */ - uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */ - uint32_t codec_ibias_ctrl : 3; /* [18:16], r/w, 0x4 */ - uint32_t reserved_19_31 : 13; /* [31:19], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } codec_power1; - - /* 0x704 : codec_power2 */ - union { - struct { - uint32_t hpbg_chop_sel : 3; /* [ 2: 0], r/w, 0x0 */ - uint32_t hpbg_chop_en : 1; /* [ 3], r/w, 0x0 */ - uint32_t hpbg_pu : 1; /* [ 4], r/w, 0x1 */ - uint32_t hpbg_filt_rsel : 2; /* [ 6: 5], r/w, 0x1 */ - uint32_t hpbg_bypass : 1; /* [ 7], r/w, 0x0 */ - uint32_t hpbg_adjust_fine : 4; /* [11: 8], r/w, 0x1 */ - uint32_t hpbg_adjust_coarse : 4; /* [15:12], r/w, 0x1 */ - uint32_t hpbg_compst_en : 1; /* [ 16], r/w, 0x1 */ - uint32_t ldo25_sstart_en : 1; /* [ 17], r/w, 0x1 */ - uint32_t ldo25_sstart_delay : 2; /* [19:18], r/w, 0x1 */ - uint32_t ldo25_pulldown_sel : 1; /* [ 20], r/w, 0x0 */ - uint32_t ldo25_pulldown : 1; /* [ 21], r/w, 0x0 */ - uint32_t ldo25_pu : 1; /* [ 22], r/w, 0x1 */ - uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */ - uint32_t ldo25_chop_sel : 3; /* [26:24], r/w, 0x1 */ - uint32_t ldo25_chop_en : 1; /* [ 27], r/w, 0x0 */ - uint32_t ldo25_cc_sel : 3; /* [30:28], r/w, 0x0 */ - uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } codec_power2; - - /* 0x708 : codec_dac */ - union { - struct { - uint32_t dacr_lineout_gain : 3; /* [ 2: 0], r/w, 0x0 */ - uint32_t dacr_en_lineout : 1; /* [ 3], r/w, 0x0 */ - uint32_t dacr_en_dac : 1; /* [ 4], r/w, 0x0 */ - uint32_t reserved_5 : 1; /* [ 5], rsvd, 0x0 */ - uint32_t dacr_lineout_mode : 1; /* [ 6], r/w, 0x0 */ - uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ - uint32_t dacr_ictrl_lineout : 2; /* [ 9: 8], r/w, 0x2 */ - uint32_t dacr_sdac_lineout : 1; /* [ 10], r/w, 0x0 */ - uint32_t dacr_sdebug_lineout : 1; /* [ 11], r/w, 0x0 */ - uint32_t dacr_ictrl_dac : 2; /* [13:12], r/w, 0x1 */ - uint32_t dacr_ckb_en : 1; /* [ 14], r/w, 0x0 */ - uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */ - uint32_t dacl_lineout_gain : 3; /* [18:16], r/w, 0x0 */ - uint32_t dacl_en_lineout : 1; /* [ 19], r/w, 0x0 */ - uint32_t dacl_en_dac : 1; /* [ 20], r/w, 0x0 */ - uint32_t reserved_21 : 1; /* [ 21], rsvd, 0x0 */ - uint32_t dacl_lineout_mode : 1; /* [ 22], r/w, 0x0 */ - uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */ - uint32_t dacl_ictrl_lineout : 2; /* [25:24], r/w, 0x2 */ - uint32_t dacl_sdac_lineout : 1; /* [ 26], r/w, 0x0 */ - uint32_t dacl_sdebug_lineout : 1; /* [ 27], r/w, 0x0 */ - uint32_t dacl_ictrl_dac : 2; /* [29:28], r/w, 0x1 */ - uint32_t dacl_ckb_en : 1; /* [ 30], r/w, 0x0 */ - uint32_t dac_rg_lo_vref_ramp_dcl_busy : 1; /* [ 31], r, 0x0 */ - } BF; - uint32_t WORD; - } codec_dac; - - /* 0x70C : codec_dac_ramp */ - union { - struct { - uint32_t dac_rg_lo_vref_ramp_dcl_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t dac_rg_lineout_vo_pulldown : 1; /* [ 1], r/w, 0x0 */ - uint32_t dac_rg_pu_vref_ramp : 1; /* [ 2], r/w, 0x0 */ - uint32_t dac_rg_pu_lineout : 1; /* [ 3], r/w, 0x0 */ - uint32_t dac_rg_vref_ramp_step_t : 3; /* [ 6: 4], r/w, 0x0 */ - uint32_t dac_rg_sw_vref : 1; /* [ 7], r/w, 0x0 */ - uint32_t dac_rg_vref_ramp_delay : 2; /* [ 9: 8], r/w, 0x1 */ - uint32_t dac_rg_lo_vref_ramp_dvld : 1; /* [ 10], r, 0x0 */ - uint32_t dac_automute_en : 1; /* [ 11], r/w, 0x0 */ - uint32_t dg_dac_mute : 1; /* [ 12], r, 0x0 */ - uint32_t dg_vo_pulldown : 1; /* [ 13], r, 0x0 */ - uint32_t dg_pu_vref_ramp : 1; /* [ 14], r, 0x0 */ - uint32_t dg_vref_ramp_step : 12; /* [26:15], r, 0x0 */ - uint32_t dg_sw_vref : 1; /* [ 27], r, 0x0 */ - uint32_t dg_dacr_en_lineout : 1; /* [ 28], r, 0x0 */ - uint32_t dg_dacl_en_lineout : 1; /* [ 29], r, 0x0 */ - uint32_t dac_rg_vref_ramp_dcl_mode : 2; /* [31:30], r/w, 0x0 */ - } BF; - uint32_t WORD; - } codec_dac_ramp; - - /* 0x710 : codec_adc0 */ - union { - struct { - uint32_t adc0_sdm_lp : 1; /* [ 0], r/w, 0x0 */ - uint32_t adc0_ckb_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t adc0_reg_resev : 1; /* [ 2], r/w, 0x0 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t adc0_pga_rcm_sel : 2; /* [ 5: 4], r/w, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t adc0_pga_gain : 4; /* [11: 8], r/w, 0x0 */ - uint32_t adc0_ictrl_mic : 2; /* [13:12], r/w, 0x2 */ - uint32_t adc0_ictrl_adc2 : 2; /* [15:14], r/w, 0x2 */ - uint32_t adc0_ictrl_adc1 : 2; /* [17:16], r/w, 0x2 */ - uint32_t adc0_ictrl_aaf : 2; /* [19:18], r/w, 0x2 */ - uint32_t adc0_en_sdm : 1; /* [ 20], r/w, 0x0 */ - uint32_t adc0_en_pga : 1; /* [ 21], r/w, 0x0 */ - uint32_t adc_dither_sel : 2; /* [23:22], r/w, 0x2 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } codec_adc0; - - /* 0x714 : codec_adc1 */ - union { - struct { - uint32_t adc1_sdm_lp : 1; /* [ 0], r/w, 0x0 */ - uint32_t adc1_ckb_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t adc1_reg_resev : 1; /* [ 2], r/w, 0x0 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t adc1_pga_rcm_sel : 2; /* [ 5: 4], r/w, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t adc1_pga_gain : 4; /* [11: 8], r/w, 0x0 */ - uint32_t adc1_ictrl_mic : 2; /* [13:12], r/w, 0x2 */ - uint32_t adc1_ictrl_adc2 : 2; /* [15:14], r/w, 0x2 */ - uint32_t adc1_ictrl_adc1 : 2; /* [17:16], r/w, 0x2 */ - uint32_t adc1_ictrl_aaf : 2; /* [19:18], r/w, 0x2 */ - uint32_t adc1_en_sdm : 1; /* [ 20], r/w, 0x0 */ - uint32_t adc1_en_pga : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } codec_adc1; - - /* 0x718 : codec_adc2 */ - union { - struct { - uint32_t adc2_sdm_lp : 1; /* [ 0], r/w, 0x0 */ - uint32_t adc2_ckb_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t adc2_reg_resev : 1; /* [ 2], r/w, 0x0 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t adc2_pga_rcm_sel : 2; /* [ 5: 4], r/w, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t adc2_pga_gain : 4; /* [11: 8], r/w, 0x0 */ - uint32_t adc2_ictrl_mic : 2; /* [13:12], r/w, 0x2 */ - uint32_t adc2_ictrl_adc2 : 2; /* [15:14], r/w, 0x2 */ - uint32_t adc2_ictrl_adc1 : 2; /* [17:16], r/w, 0x2 */ - uint32_t adc2_ictrl_aaf : 2; /* [19:18], r/w, 0x2 */ - uint32_t adc2_en_sdm : 1; /* [ 20], r/w, 0x0 */ - uint32_t adc2_en_pga : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } codec_adc2; - - /* 0x71c reserved */ - uint8_t RESERVED0x71c[228]; - - /* 0x800 : padc_ana_cfg1 */ - union { - struct { - uint32_t padc_pga_chop_cksel : 1; /* [ 0], r/w, 0x1 */ - uint32_t padc_pga_chop_freq : 3; /* [ 3: 1], r/w, 0x4 */ - uint32_t padc_pga_chop_en : 1; /* [ 4], r/w, 0x1 */ - uint32_t padc_pga_noisctrl : 2; /* [ 6: 5], r/w, 0x3 */ - uint32_t padc_ictrl_pga_buf : 2; /* [ 8: 7], r/w, 0x1 */ - uint32_t padc_ictrl_pga_ia : 2; /* [10: 9], r/w, 0x1 */ - uint32_t padc_pga_force : 1; /* [ 11], r/w, 0x0 */ - uint32_t padc_pga_autobps_buf : 1; /* [ 12], r/w, 0x0 */ - uint32_t padc_pga_autobps_ia : 1; /* [ 13], r/w, 0x0 */ - uint32_t padc_pga_mode : 2; /* [15:14], r/w, 0x2 */ - uint32_t padc_afevcm_rout : 2; /* [17:16], r/w, 0x0 */ - uint32_t padc_afevcm_sel : 1; /* [ 18], r/w, 0x0 */ - uint32_t padc_ckb_en : 1; /* [ 19], r/w, 0x0 */ - uint32_t padc_sel_edge : 1; /* [ 20], r/w, 0x0 */ - uint32_t reserved_21_31 : 11; /* [31:21], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_ana_cfg1; - - /* 0x804 : padc_ana_cfg2 */ - union { - struct { - uint32_t padc_sdm_chop_phas : 1; /* [ 0], r/w, 0x1 */ - uint32_t padc_sdm_chop_freq : 3; /* [ 3: 1], r/w, 0x4 */ - uint32_t padc_sdm_chop_en : 1; /* [ 4], r/w, 0x1 */ - uint32_t padc_dither_order : 1; /* [ 5], r/w, 0x0 */ - uint32_t padc_dither_sel : 2; /* [ 7: 6], r/w, 0x0 */ - uint32_t padc_quan_gain : 2; /* [ 9: 8], r/w, 0x1 */ - uint32_t padc_dem_en : 1; /* [ 10], r/w, 0x1 */ - uint32_t padc_nctrl_adc2 : 1; /* [ 11], r/w, 0x0 */ - uint32_t reserved_12 : 1; /* [ 12], rsvd, 0x0 */ - uint32_t padc_nctrl_adc1 : 2; /* [14:13], r/w, 0x0 */ - uint32_t padc_ictrl_adc : 2; /* [16:15], r/w, 0x1 */ - uint32_t padc_reserved : 4; /* [20:17], r/w, 0x0 */ - uint32_t reserved_21_31 : 11; /* [31:21], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_ana_cfg2; - - /* 0x808 : padc_ana_cmd */ - union { - struct { - uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */ - uint32_t padc_self_test_en : 1; /* [ 2], r/w, 0x0 */ - uint32_t padc_sdm_lp_en : 1; /* [ 3], r/w, 0x0 */ - uint32_t padc_pga_lp_en : 1; /* [ 4], r/w, 0x0 */ - uint32_t padc_diag_gsw : 2; /* [ 6: 5], r/w, 0x0 */ - uint32_t padc_diag_psw : 2; /* [ 8: 7], r/w, 0x0 */ - uint32_t padc_ictrl_diag : 2; /* [10: 9], r/w, 0x0 */ - uint32_t padc_pga_gain : 3; /* [13:11], r/w, 0x0 */ - uint32_t padc_inv_sig : 1; /* [ 14], r/w, 0x0 */ - uint32_t padc_single_mode : 2; /* [16:15], r/w, 0x0 */ - uint32_t padc_single_cfg : 4; /* [20:17], r/w, 0x0 */ - uint32_t padc_channel_sel : 2; /* [22:21], r/w, 0x0 */ - uint32_t padc_channel_en : 1; /* [ 23], r/w, 0x0 */ - uint32_t padc_conv_delay : 4; /* [27:24], r/w, 0x3 */ - uint32_t padc_conv : 1; /* [ 28], r/w, 0x0 */ - uint32_t padc_en_caldac : 1; /* [ 29], r/w, 0x0 */ - uint32_t padc_sdm_pu : 1; /* [ 30], r/w, 0x0 */ - uint32_t padc_pga_pu : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } padc_ana_cmd; - - /* 0x80C : padc_out_cfg */ - union { - struct { - uint32_t reserved_0_20 : 21; /* [20: 0], rsvd, 0x0 */ - uint32_t padc_valid_4s_val : 1; /* [ 21], r/w, 0x0 */ - uint32_t padc_valid_4s_en : 1; /* [ 22], r/w, 0x0 */ - uint32_t padc_global_chop_en : 1; /* [ 23], r/w, 0x0 */ - uint32_t padc_filter_type : 1; /* [ 24], r/w, 0x0 */ - uint32_t padc_odr : 4; /* [28:25], r/w, 0x3 */ - uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_out_cfg; - - /* 0x810 : padc_calib_cmd */ - union { - struct { - uint32_t reserved_0_15 : 16; /* [15: 0], rsvd, 0x0 */ - uint32_t padc_calib_average : 3; /* [18:16], r/w, 0x4 */ - uint32_t padc_calib_discard : 3; /* [21:19], r/w, 0x4 */ - uint32_t padc_calib_run : 1; /* [ 22], r/w, 0x0 */ - uint32_t padc_calib_lvl : 2; /* [24:23], r/w, 0x2 */ - uint32_t padc_calib_gain : 3; /* [27:25], r/w, 0x0 */ - uint32_t padc_calib_mode : 2; /* [29:28], r/w, 0x0 */ - uint32_t padc_calib_start : 1; /* [ 30], w1p, 0x0 */ - uint32_t padc_calib_method : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } padc_calib_cmd; - - /* 0x814 : padc_status */ - union { - struct { - uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */ - uint32_t padc_soft_rst : 1; /* [ 2], r/w, 0x0 */ - uint32_t padc_filter_rdy : 1; /* [ 3], r, 0x0 */ - uint32_t reserved_4_23 : 20; /* [23: 4], rsvd, 0x0 */ - uint32_t padc_calib_st : 3; /* [26:24], r, 0x0 */ - uint32_t padc_calib_busy : 1; /* [ 27], r, 0x0 */ - uint32_t padc_int : 1; /* [ 28], r, 0x0 */ - uint32_t padc_int_clr : 1; /* [ 29], r/w, 0x0 */ - uint32_t padc_int_set : 1; /* [ 30], r/w, 0x0 */ - uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_status; - - /* 0x818 : padc_data */ - union { - struct { - uint32_t padc_raw_data : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_data; - - /* 0x81C : padc_calib_cfg1 */ - union { - struct { - uint32_t padc_oec : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_calib_cfg1; - - /* 0x820 : padc_calib_cfg2 */ - union { - struct { - uint32_t padc_gec : 24; /* [23: 0], r, 0x800000 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_calib_cfg2; - - /* 0x824 : padc_calib_cfg3 */ - union { - struct { - uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_calib_cfg3; - - /* 0x828 : padc_calib_cfg4 */ - union { - struct { - uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_calib_cfg4; - - /* 0x82C : padc_calib_cfg5 */ - union { - struct { - uint32_t padc_gaincal_ref : 24; /* [23: 0], r/w, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_calib_cfg5; - - /* 0x830 : padc_calib_cfg6 */ - union { - struct { - uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_calib_cfg6; - - /* 0x834 : padc_calib_cfg7 */ - union { - struct { - uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_calib_cfg7; - - /* 0x838 : padc_oec_w1p */ - union { - struct { - uint32_t padc_wr_oec : 24; /* [23: 0], r/w, 0x0 */ - uint32_t padc_oec_w1p_g0 : 1; /* [ 24], w1p, 0x0 */ - uint32_t padc_oec_w1p_g1 : 1; /* [ 25], w1p, 0x0 */ - uint32_t padc_oec_w1p_g2 : 1; /* [ 26], w1p, 0x0 */ - uint32_t padc_oec_w1p_g3 : 1; /* [ 27], w1p, 0x0 */ - uint32_t padc_oec_w1p_g4 : 1; /* [ 28], w1p, 0x0 */ - uint32_t padc_oec_w1p_g5 : 1; /* [ 29], w1p, 0x0 */ - uint32_t padc_oec_w1p_g6 : 1; /* [ 30], w1p, 0x0 */ - uint32_t padc_oec_w1p_g7 : 1; /* [ 31], w1p, 0x0 */ - } BF; - uint32_t WORD; - } padc_oec_w1p; - - /* 0x83C : padc_gec_w1p */ - union { - struct { - uint32_t padc_wr_gec : 24; /* [23: 0], r/w, 0x0 */ - uint32_t padc_gec_w1p_g0 : 1; /* [ 24], w1p, 0x0 */ - uint32_t padc_gec_w1p_g1 : 1; /* [ 25], w1p, 0x0 */ - uint32_t padc_gec_w1p_g2 : 1; /* [ 26], w1p, 0x0 */ - uint32_t padc_gec_w1p_g3 : 1; /* [ 27], w1p, 0x0 */ - uint32_t padc_gec_w1p_g4 : 1; /* [ 28], w1p, 0x0 */ - uint32_t padc_gec_w1p_g5 : 1; /* [ 29], w1p, 0x0 */ - uint32_t padc_gec_w1p_g6 : 1; /* [ 30], w1p, 0x0 */ - uint32_t padc_gec_w1p_g7 : 1; /* [ 31], w1p, 0x0 */ - } BF; - uint32_t WORD; - } padc_gec_w1p; - - /* 0x840 : padc_oec_cfg0 */ - union { - struct { - uint32_t padc_oec_g0 : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_oec_cfg0; - - /* 0x844 : padc_oec_cfg1 */ - union { - struct { - uint32_t padc_oec_g1 : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_oec_cfg1; - - /* 0x848 : padc_oec_cfg2 */ - union { - struct { - uint32_t padc_oec_g2 : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_oec_cfg2; - - /* 0x84C : padc_oec_cfg3 */ - union { - struct { - uint32_t padc_oec_g3 : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_oec_cfg3; - - /* 0x850 : padc_oec_cfg4 */ - union { - struct { - uint32_t padc_oec_g4 : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_oec_cfg4; - - /* 0x854 : padc_oec_cfg5 */ - union { - struct { - uint32_t padc_oec_g5 : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_oec_cfg5; - - /* 0x858 : padc_oec_cfg6 */ - union { - struct { - uint32_t padc_oec_g6 : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_oec_cfg6; - - /* 0x85C : padc_oec_cfg7 */ - union { - struct { - uint32_t padc_oec_g7 : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_oec_cfg7; - - /* 0x860 : padc_gec_cfg0 */ - union { - struct { - uint32_t padc_gec_g0 : 24; /* [23: 0], r, 0x800000 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_gec_cfg0; - - /* 0x864 : padc_gec_cfg1 */ - union { - struct { - uint32_t padc_gec_g1 : 24; /* [23: 0], r, 0x800000 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_gec_cfg1; - - /* 0x868 : padc_gec_cfg2 */ - union { - struct { - uint32_t padc_gec_g2 : 24; /* [23: 0], r, 0x800000 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_gec_cfg2; - - /* 0x86C : padc_gec_cfg3 */ - union { - struct { - uint32_t padc_gec_g3 : 24; /* [23: 0], r, 0x800000 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_gec_cfg3; - - /* 0x870 : padc_gec_cfg4 */ - union { - struct { - uint32_t padc_gec_g4 : 24; /* [23: 0], r, 0x800000 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_gec_cfg4; - - /* 0x874 : padc_gec_cfg5 */ - union { - struct { - uint32_t padc_gec_g5 : 24; /* [23: 0], r, 0x800000 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_gec_cfg5; - - /* 0x878 : padc_gec_cfg6 */ - union { - struct { - uint32_t padc_gec_g6 : 24; /* [23: 0], r, 0x800000 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_gec_cfg6; - - /* 0x87C : padc_gec_cfg7 */ - union { - struct { - uint32_t padc_gec_g7 : 24; /* [23: 0], r, 0x800000 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_gec_cfg7; - - /* 0x880 reserved */ - uint8_t RESERVED0x880[128]; - - /* 0x900 : padc_rx_fifo_ctrl */ - union { - struct { - uint32_t padc_rx_fifo_flush : 1; /* [ 0], w1p, 0x0 */ - uint32_t padc_rxo_int_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t padc_rxu_int_en : 1; /* [ 2], r/w, 0x0 */ - uint32_t padc_rxa_int_en : 1; /* [ 3], r/w, 0x0 */ - uint32_t padc_rx_drq_en : 1; /* [ 4], r/w, 0x0 */ - uint32_t padc_rx_data_res : 1; /* [ 5], r/w, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t padc_rx_ch_en : 1; /* [ 8], r/w, 0x0 */ - uint32_t reserved_9_13 : 5; /* [13: 9], rsvd, 0x0 */ - uint32_t padc_rx_drq_cnt : 2; /* [15:14], r/w, 0x0 */ - uint32_t padc_rx_trg_level : 4; /* [19:16], r/w, 0x3 */ - uint32_t reserved_20_23 : 4; /* [23:20], rsvd, 0x0 */ - uint32_t padc_rx_data_mode : 2; /* [25:24], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_rx_fifo_ctrl; - - /* 0x904 : padc_rx_fifo_status */ - union { - struct { - uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */ - uint32_t padc_rxo_int : 1; /* [ 1], r, 0x0 */ - uint32_t padc_rxu_int : 1; /* [ 2], r, 0x0 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t padc_rxa_int : 1; /* [ 4], r, 0x0 */ - uint32_t reserved_5_15 : 11; /* [15: 5], rsvd, 0x0 */ - uint32_t padc_rxa_cnt : 4; /* [19:16], r, 0x0 */ - uint32_t reserved_20_23 : 4; /* [23:20], rsvd, 0x0 */ - uint32_t padc_rxa : 1; /* [ 24], r, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_rx_fifo_status; - - /* 0x908 : padc_rx_fifo_data */ - union { - struct { - uint32_t padc_rx_data : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } padc_rx_fifo_data; -}; - -typedef volatile struct audio_reg audio_reg_t; - -#endif /* __AUDIO_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/cam_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/cam_reg.h deleted file mode 100644 index 1a7c5372eb..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/cam_reg.h +++ /dev/null @@ -1,689 +0,0 @@ -/** - ****************************************************************************** - * @file cam_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __CAM_REG_H__ -#define __CAM_REG_H__ - -#include "bl808.h" - -/* 0x0 : dvp2axi_configue */ -#define CAM_DVP2AXI_CONFIGUE_OFFSET (0x0) -#define CAM_REG_DVP_ENABLE CAM_REG_DVP_ENABLE -#define CAM_REG_DVP_ENABLE_POS (0U) -#define CAM_REG_DVP_ENABLE_LEN (1U) -#define CAM_REG_DVP_ENABLE_MSK (((1U << CAM_REG_DVP_ENABLE_LEN) - 1) << CAM_REG_DVP_ENABLE_POS) -#define CAM_REG_DVP_ENABLE_UMSK (~(((1U << CAM_REG_DVP_ENABLE_LEN) - 1) << CAM_REG_DVP_ENABLE_POS)) -#define CAM_REG_SW_MODE CAM_REG_SW_MODE -#define CAM_REG_SW_MODE_POS (1U) -#define CAM_REG_SW_MODE_LEN (1U) -#define CAM_REG_SW_MODE_MSK (((1U << CAM_REG_SW_MODE_LEN) - 1) << CAM_REG_SW_MODE_POS) -#define CAM_REG_SW_MODE_UMSK (~(((1U << CAM_REG_SW_MODE_LEN) - 1) << CAM_REG_SW_MODE_POS)) -#define CAM_REG_FRAM_VLD_POL CAM_REG_FRAM_VLD_POL -#define CAM_REG_FRAM_VLD_POL_POS (2U) -#define CAM_REG_FRAM_VLD_POL_LEN (1U) -#define CAM_REG_FRAM_VLD_POL_MSK (((1U << CAM_REG_FRAM_VLD_POL_LEN) - 1) << CAM_REG_FRAM_VLD_POL_POS) -#define CAM_REG_FRAM_VLD_POL_UMSK (~(((1U << CAM_REG_FRAM_VLD_POL_LEN) - 1) << CAM_REG_FRAM_VLD_POL_POS)) -#define CAM_REG_LINE_VLD_POL CAM_REG_LINE_VLD_POL -#define CAM_REG_LINE_VLD_POL_POS (3U) -#define CAM_REG_LINE_VLD_POL_LEN (1U) -#define CAM_REG_LINE_VLD_POL_MSK (((1U << CAM_REG_LINE_VLD_POL_LEN) - 1) << CAM_REG_LINE_VLD_POL_POS) -#define CAM_REG_LINE_VLD_POL_UMSK (~(((1U << CAM_REG_LINE_VLD_POL_LEN) - 1) << CAM_REG_LINE_VLD_POL_POS)) -#define CAM_REG_XLEN CAM_REG_XLEN -#define CAM_REG_XLEN_POS (4U) -#define CAM_REG_XLEN_LEN (3U) -#define CAM_REG_XLEN_MSK (((1U << CAM_REG_XLEN_LEN) - 1) << CAM_REG_XLEN_POS) -#define CAM_REG_XLEN_UMSK (~(((1U << CAM_REG_XLEN_LEN) - 1) << CAM_REG_XLEN_POS)) -#define CAM_REG_DVP_MODE CAM_REG_DVP_MODE -#define CAM_REG_DVP_MODE_POS (8U) -#define CAM_REG_DVP_MODE_LEN (3U) -#define CAM_REG_DVP_MODE_MSK (((1U << CAM_REG_DVP_MODE_LEN) - 1) << CAM_REG_DVP_MODE_POS) -#define CAM_REG_DVP_MODE_UMSK (~(((1U << CAM_REG_DVP_MODE_LEN) - 1) << CAM_REG_DVP_MODE_POS)) -#define CAM_REG_HW_MODE_FWRAP CAM_REG_HW_MODE_FWRAP -#define CAM_REG_HW_MODE_FWRAP_POS (11U) -#define CAM_REG_HW_MODE_FWRAP_LEN (1U) -#define CAM_REG_HW_MODE_FWRAP_MSK (((1U << CAM_REG_HW_MODE_FWRAP_LEN) - 1) << CAM_REG_HW_MODE_FWRAP_POS) -#define CAM_REG_HW_MODE_FWRAP_UMSK (~(((1U << CAM_REG_HW_MODE_FWRAP_LEN) - 1) << CAM_REG_HW_MODE_FWRAP_POS)) -#define CAM_REG_DROP_EN CAM_REG_DROP_EN -#define CAM_REG_DROP_EN_POS (12U) -#define CAM_REG_DROP_EN_LEN (1U) -#define CAM_REG_DROP_EN_MSK (((1U << CAM_REG_DROP_EN_LEN) - 1) << CAM_REG_DROP_EN_POS) -#define CAM_REG_DROP_EN_UMSK (~(((1U << CAM_REG_DROP_EN_LEN) - 1) << CAM_REG_DROP_EN_POS)) -#define CAM_REG_DROP_EVEN CAM_REG_DROP_EVEN -#define CAM_REG_DROP_EVEN_POS (13U) -#define CAM_REG_DROP_EVEN_LEN (1U) -#define CAM_REG_DROP_EVEN_MSK (((1U << CAM_REG_DROP_EVEN_LEN) - 1) << CAM_REG_DROP_EVEN_POS) -#define CAM_REG_DROP_EVEN_UMSK (~(((1U << CAM_REG_DROP_EVEN_LEN) - 1) << CAM_REG_DROP_EVEN_POS)) -#define CAM_REG_QOS_SW_MODE CAM_REG_QOS_SW_MODE -#define CAM_REG_QOS_SW_MODE_POS (14U) -#define CAM_REG_QOS_SW_MODE_LEN (1U) -#define CAM_REG_QOS_SW_MODE_MSK (((1U << CAM_REG_QOS_SW_MODE_LEN) - 1) << CAM_REG_QOS_SW_MODE_POS) -#define CAM_REG_QOS_SW_MODE_UMSK (~(((1U << CAM_REG_QOS_SW_MODE_LEN) - 1) << CAM_REG_QOS_SW_MODE_POS)) -#define CAM_REG_QOS_SW CAM_REG_QOS_SW -#define CAM_REG_QOS_SW_POS (15U) -#define CAM_REG_QOS_SW_LEN (1U) -#define CAM_REG_QOS_SW_MSK (((1U << CAM_REG_QOS_SW_LEN) - 1) << CAM_REG_QOS_SW_POS) -#define CAM_REG_QOS_SW_UMSK (~(((1U << CAM_REG_QOS_SW_LEN) - 1) << CAM_REG_QOS_SW_POS)) -#define CAM_REG_DVP_DATA_MODE CAM_REG_DVP_DATA_MODE -#define CAM_REG_DVP_DATA_MODE_POS (16U) -#define CAM_REG_DVP_DATA_MODE_LEN (3U) -#define CAM_REG_DVP_DATA_MODE_MSK (((1U << CAM_REG_DVP_DATA_MODE_LEN) - 1) << CAM_REG_DVP_DATA_MODE_POS) -#define CAM_REG_DVP_DATA_MODE_UMSK (~(((1U << CAM_REG_DVP_DATA_MODE_LEN) - 1) << CAM_REG_DVP_DATA_MODE_POS)) -#define CAM_REG_DVP_DATA_BSEL CAM_REG_DVP_DATA_BSEL -#define CAM_REG_DVP_DATA_BSEL_POS (19U) -#define CAM_REG_DVP_DATA_BSEL_LEN (1U) -#define CAM_REG_DVP_DATA_BSEL_MSK (((1U << CAM_REG_DVP_DATA_BSEL_LEN) - 1) << CAM_REG_DVP_DATA_BSEL_POS) -#define CAM_REG_DVP_DATA_BSEL_UMSK (~(((1U << CAM_REG_DVP_DATA_BSEL_LEN) - 1) << CAM_REG_DVP_DATA_BSEL_POS)) -#define CAM_REG_DVP_PIX_CLK_CG CAM_REG_DVP_PIX_CLK_CG -#define CAM_REG_DVP_PIX_CLK_CG_POS (20U) -#define CAM_REG_DVP_PIX_CLK_CG_LEN (1U) -#define CAM_REG_DVP_PIX_CLK_CG_MSK (((1U << CAM_REG_DVP_PIX_CLK_CG_LEN) - 1) << CAM_REG_DVP_PIX_CLK_CG_POS) -#define CAM_REG_DVP_PIX_CLK_CG_UMSK (~(((1U << CAM_REG_DVP_PIX_CLK_CG_LEN) - 1) << CAM_REG_DVP_PIX_CLK_CG_POS)) -#define CAM_REG_V_SUBSAMPLE_EN CAM_REG_V_SUBSAMPLE_EN -#define CAM_REG_V_SUBSAMPLE_EN_POS (22U) -#define CAM_REG_V_SUBSAMPLE_EN_LEN (1U) -#define CAM_REG_V_SUBSAMPLE_EN_MSK (((1U << CAM_REG_V_SUBSAMPLE_EN_LEN) - 1) << CAM_REG_V_SUBSAMPLE_EN_POS) -#define CAM_REG_V_SUBSAMPLE_EN_UMSK (~(((1U << CAM_REG_V_SUBSAMPLE_EN_LEN) - 1) << CAM_REG_V_SUBSAMPLE_EN_POS)) -#define CAM_REG_V_SUBSAMPLE_POL CAM_REG_V_SUBSAMPLE_POL -#define CAM_REG_V_SUBSAMPLE_POL_POS (23U) -#define CAM_REG_V_SUBSAMPLE_POL_LEN (1U) -#define CAM_REG_V_SUBSAMPLE_POL_MSK (((1U << CAM_REG_V_SUBSAMPLE_POL_LEN) - 1) << CAM_REG_V_SUBSAMPLE_POL_POS) -#define CAM_REG_V_SUBSAMPLE_POL_UMSK (~(((1U << CAM_REG_V_SUBSAMPLE_POL_LEN) - 1) << CAM_REG_V_SUBSAMPLE_POL_POS)) -#define CAM_REG_DVP_WAIT_CYCLE CAM_REG_DVP_WAIT_CYCLE -#define CAM_REG_DVP_WAIT_CYCLE_POS (24U) -#define CAM_REG_DVP_WAIT_CYCLE_LEN (8U) -#define CAM_REG_DVP_WAIT_CYCLE_MSK (((1U << CAM_REG_DVP_WAIT_CYCLE_LEN) - 1) << CAM_REG_DVP_WAIT_CYCLE_POS) -#define CAM_REG_DVP_WAIT_CYCLE_UMSK (~(((1U << CAM_REG_DVP_WAIT_CYCLE_LEN) - 1) << CAM_REG_DVP_WAIT_CYCLE_POS)) - -/* 0x4 : dvp2axi_addr_start */ -#define CAM_DVP2AXI_ADDR_START_OFFSET (0x4) -#define CAM_REG_ADDR_START CAM_REG_ADDR_START -#define CAM_REG_ADDR_START_POS (0U) -#define CAM_REG_ADDR_START_LEN (32U) -#define CAM_REG_ADDR_START_MSK (((1U << CAM_REG_ADDR_START_LEN) - 1) << CAM_REG_ADDR_START_POS) -#define CAM_REG_ADDR_START_UMSK (~(((1U << CAM_REG_ADDR_START_LEN) - 1) << CAM_REG_ADDR_START_POS)) - -/* 0x8 : dvp2axi_mem_bcnt */ -#define CAM_DVP2AXI_MEM_BCNT_OFFSET (0x8) -#define CAM_REG_MEM_BURST_CNT CAM_REG_MEM_BURST_CNT -#define CAM_REG_MEM_BURST_CNT_POS (0U) -#define CAM_REG_MEM_BURST_CNT_LEN (32U) -#define CAM_REG_MEM_BURST_CNT_MSK (((1U << CAM_REG_MEM_BURST_CNT_LEN) - 1) << CAM_REG_MEM_BURST_CNT_POS) -#define CAM_REG_MEM_BURST_CNT_UMSK (~(((1U << CAM_REG_MEM_BURST_CNT_LEN) - 1) << CAM_REG_MEM_BURST_CNT_POS)) - -/* 0xC : dvp_status_and_error */ -#define CAM_DVP_STATUS_AND_ERROR_OFFSET (0xC) -#define CAM_REG_FRAME_CNT_TRGR_INT CAM_REG_FRAME_CNT_TRGR_INT -#define CAM_REG_FRAME_CNT_TRGR_INT_POS (0U) -#define CAM_REG_FRAME_CNT_TRGR_INT_LEN (5U) -#define CAM_REG_FRAME_CNT_TRGR_INT_MSK (((1U << CAM_REG_FRAME_CNT_TRGR_INT_LEN) - 1) << CAM_REG_FRAME_CNT_TRGR_INT_POS) -#define CAM_REG_FRAME_CNT_TRGR_INT_UMSK (~(((1U << CAM_REG_FRAME_CNT_TRGR_INT_LEN) - 1) << CAM_REG_FRAME_CNT_TRGR_INT_POS)) -#define CAM_REG_INT_HCNT_EN CAM_REG_INT_HCNT_EN -#define CAM_REG_INT_HCNT_EN_POS (6U) -#define CAM_REG_INT_HCNT_EN_LEN (1U) -#define CAM_REG_INT_HCNT_EN_MSK (((1U << CAM_REG_INT_HCNT_EN_LEN) - 1) << CAM_REG_INT_HCNT_EN_POS) -#define CAM_REG_INT_HCNT_EN_UMSK (~(((1U << CAM_REG_INT_HCNT_EN_LEN) - 1) << CAM_REG_INT_HCNT_EN_POS)) -#define CAM_REG_INT_VCNT_EN CAM_REG_INT_VCNT_EN -#define CAM_REG_INT_VCNT_EN_POS (7U) -#define CAM_REG_INT_VCNT_EN_LEN (1U) -#define CAM_REG_INT_VCNT_EN_MSK (((1U << CAM_REG_INT_VCNT_EN_LEN) - 1) << CAM_REG_INT_VCNT_EN_POS) -#define CAM_REG_INT_VCNT_EN_UMSK (~(((1U << CAM_REG_INT_VCNT_EN_LEN) - 1) << CAM_REG_INT_VCNT_EN_POS)) -#define CAM_REG_INT_NORMAL_EN CAM_REG_INT_NORMAL_EN -#define CAM_REG_INT_NORMAL_EN_POS (8U) -#define CAM_REG_INT_NORMAL_EN_LEN (1U) -#define CAM_REG_INT_NORMAL_EN_MSK (((1U << CAM_REG_INT_NORMAL_EN_LEN) - 1) << CAM_REG_INT_NORMAL_EN_POS) -#define CAM_REG_INT_NORMAL_EN_UMSK (~(((1U << CAM_REG_INT_NORMAL_EN_LEN) - 1) << CAM_REG_INT_NORMAL_EN_POS)) -#define CAM_REG_INT_MEM_EN CAM_REG_INT_MEM_EN -#define CAM_REG_INT_MEM_EN_POS (9U) -#define CAM_REG_INT_MEM_EN_LEN (1U) -#define CAM_REG_INT_MEM_EN_MSK (((1U << CAM_REG_INT_MEM_EN_LEN) - 1) << CAM_REG_INT_MEM_EN_POS) -#define CAM_REG_INT_MEM_EN_UMSK (~(((1U << CAM_REG_INT_MEM_EN_LEN) - 1) << CAM_REG_INT_MEM_EN_POS)) -#define CAM_REG_INT_FRAME_EN CAM_REG_INT_FRAME_EN -#define CAM_REG_INT_FRAME_EN_POS (10U) -#define CAM_REG_INT_FRAME_EN_LEN (1U) -#define CAM_REG_INT_FRAME_EN_MSK (((1U << CAM_REG_INT_FRAME_EN_LEN) - 1) << CAM_REG_INT_FRAME_EN_POS) -#define CAM_REG_INT_FRAME_EN_UMSK (~(((1U << CAM_REG_INT_FRAME_EN_LEN) - 1) << CAM_REG_INT_FRAME_EN_POS)) -#define CAM_REG_INT_FIFO_EN CAM_REG_INT_FIFO_EN -#define CAM_REG_INT_FIFO_EN_POS (11U) -#define CAM_REG_INT_FIFO_EN_LEN (1U) -#define CAM_REG_INT_FIFO_EN_MSK (((1U << CAM_REG_INT_FIFO_EN_LEN) - 1) << CAM_REG_INT_FIFO_EN_POS) -#define CAM_REG_INT_FIFO_EN_UMSK (~(((1U << CAM_REG_INT_FIFO_EN_LEN) - 1) << CAM_REG_INT_FIFO_EN_POS)) -#define CAM_STS_NORMAL_INT CAM_STS_NORMAL_INT -#define CAM_STS_NORMAL_INT_POS (12U) -#define CAM_STS_NORMAL_INT_LEN (1U) -#define CAM_STS_NORMAL_INT_MSK (((1U << CAM_STS_NORMAL_INT_LEN) - 1) << CAM_STS_NORMAL_INT_POS) -#define CAM_STS_NORMAL_INT_UMSK (~(((1U << CAM_STS_NORMAL_INT_LEN) - 1) << CAM_STS_NORMAL_INT_POS)) -#define CAM_STS_MEM_INT CAM_STS_MEM_INT -#define CAM_STS_MEM_INT_POS (13U) -#define CAM_STS_MEM_INT_LEN (1U) -#define CAM_STS_MEM_INT_MSK (((1U << CAM_STS_MEM_INT_LEN) - 1) << CAM_STS_MEM_INT_POS) -#define CAM_STS_MEM_INT_UMSK (~(((1U << CAM_STS_MEM_INT_LEN) - 1) << CAM_STS_MEM_INT_POS)) -#define CAM_STS_FRAME_INT CAM_STS_FRAME_INT -#define CAM_STS_FRAME_INT_POS (14U) -#define CAM_STS_FRAME_INT_LEN (1U) -#define CAM_STS_FRAME_INT_MSK (((1U << CAM_STS_FRAME_INT_LEN) - 1) << CAM_STS_FRAME_INT_POS) -#define CAM_STS_FRAME_INT_UMSK (~(((1U << CAM_STS_FRAME_INT_LEN) - 1) << CAM_STS_FRAME_INT_POS)) -#define CAM_STS_FIFO_INT CAM_STS_FIFO_INT -#define CAM_STS_FIFO_INT_POS (15U) -#define CAM_STS_FIFO_INT_LEN (1U) -#define CAM_STS_FIFO_INT_MSK (((1U << CAM_STS_FIFO_INT_LEN) - 1) << CAM_STS_FIFO_INT_POS) -#define CAM_STS_FIFO_INT_UMSK (~(((1U << CAM_STS_FIFO_INT_LEN) - 1) << CAM_STS_FIFO_INT_POS)) -#define CAM_FRAME_VALID_CNT CAM_FRAME_VALID_CNT -#define CAM_FRAME_VALID_CNT_POS (16U) -#define CAM_FRAME_VALID_CNT_LEN (5U) -#define CAM_FRAME_VALID_CNT_MSK (((1U << CAM_FRAME_VALID_CNT_LEN) - 1) << CAM_FRAME_VALID_CNT_POS) -#define CAM_FRAME_VALID_CNT_UMSK (~(((1U << CAM_FRAME_VALID_CNT_LEN) - 1) << CAM_FRAME_VALID_CNT_POS)) -#define CAM_STS_HCNT_INT CAM_STS_HCNT_INT -#define CAM_STS_HCNT_INT_POS (21U) -#define CAM_STS_HCNT_INT_LEN (1U) -#define CAM_STS_HCNT_INT_MSK (((1U << CAM_STS_HCNT_INT_LEN) - 1) << CAM_STS_HCNT_INT_POS) -#define CAM_STS_HCNT_INT_UMSK (~(((1U << CAM_STS_HCNT_INT_LEN) - 1) << CAM_STS_HCNT_INT_POS)) -#define CAM_STS_VCNT_INT CAM_STS_VCNT_INT -#define CAM_STS_VCNT_INT_POS (22U) -#define CAM_STS_VCNT_INT_LEN (1U) -#define CAM_STS_VCNT_INT_MSK (((1U << CAM_STS_VCNT_INT_LEN) - 1) << CAM_STS_VCNT_INT_POS) -#define CAM_STS_VCNT_INT_UMSK (~(((1U << CAM_STS_VCNT_INT_LEN) - 1) << CAM_STS_VCNT_INT_POS)) -#define CAM_ST_BUS_IDLE CAM_ST_BUS_IDLE -#define CAM_ST_BUS_IDLE_POS (24U) -#define CAM_ST_BUS_IDLE_LEN (1U) -#define CAM_ST_BUS_IDLE_MSK (((1U << CAM_ST_BUS_IDLE_LEN) - 1) << CAM_ST_BUS_IDLE_POS) -#define CAM_ST_BUS_IDLE_UMSK (~(((1U << CAM_ST_BUS_IDLE_LEN) - 1) << CAM_ST_BUS_IDLE_POS)) -#define CAM_ST_BUS_FUNC CAM_ST_BUS_FUNC -#define CAM_ST_BUS_FUNC_POS (25U) -#define CAM_ST_BUS_FUNC_LEN (1U) -#define CAM_ST_BUS_FUNC_MSK (((1U << CAM_ST_BUS_FUNC_LEN) - 1) << CAM_ST_BUS_FUNC_POS) -#define CAM_ST_BUS_FUNC_UMSK (~(((1U << CAM_ST_BUS_FUNC_LEN) - 1) << CAM_ST_BUS_FUNC_POS)) -#define CAM_ST_BUS_WAIT CAM_ST_BUS_WAIT -#define CAM_ST_BUS_WAIT_POS (26U) -#define CAM_ST_BUS_WAIT_LEN (1U) -#define CAM_ST_BUS_WAIT_MSK (((1U << CAM_ST_BUS_WAIT_LEN) - 1) << CAM_ST_BUS_WAIT_POS) -#define CAM_ST_BUS_WAIT_UMSK (~(((1U << CAM_ST_BUS_WAIT_LEN) - 1) << CAM_ST_BUS_WAIT_POS)) -#define CAM_ST_BUS_FLSH CAM_ST_BUS_FLSH -#define CAM_ST_BUS_FLSH_POS (27U) -#define CAM_ST_BUS_FLSH_LEN (1U) -#define CAM_ST_BUS_FLSH_MSK (((1U << CAM_ST_BUS_FLSH_LEN) - 1) << CAM_ST_BUS_FLSH_POS) -#define CAM_ST_BUS_FLSH_UMSK (~(((1U << CAM_ST_BUS_FLSH_LEN) - 1) << CAM_ST_BUS_FLSH_POS)) -#define CAM_AXI_IDLE CAM_AXI_IDLE -#define CAM_AXI_IDLE_POS (28U) -#define CAM_AXI_IDLE_LEN (1U) -#define CAM_AXI_IDLE_MSK (((1U << CAM_AXI_IDLE_LEN) - 1) << CAM_AXI_IDLE_POS) -#define CAM_AXI_IDLE_UMSK (~(((1U << CAM_AXI_IDLE_LEN) - 1) << CAM_AXI_IDLE_POS)) -#define CAM_ST_DVP_IDLE CAM_ST_DVP_IDLE -#define CAM_ST_DVP_IDLE_POS (29U) -#define CAM_ST_DVP_IDLE_LEN (1U) -#define CAM_ST_DVP_IDLE_MSK (((1U << CAM_ST_DVP_IDLE_LEN) - 1) << CAM_ST_DVP_IDLE_POS) -#define CAM_ST_DVP_IDLE_UMSK (~(((1U << CAM_ST_DVP_IDLE_LEN) - 1) << CAM_ST_DVP_IDLE_POS)) - -/* 0x10 : dvp2axi_frame_bcnt */ -#define CAM_DVP2AXI_FRAME_BCNT_OFFSET (0x10) -#define CAM_REG_FRAME_BYTE_CNT CAM_REG_FRAME_BYTE_CNT -#define CAM_REG_FRAME_BYTE_CNT_POS (0U) -#define CAM_REG_FRAME_BYTE_CNT_LEN (32U) -#define CAM_REG_FRAME_BYTE_CNT_MSK (((1U << CAM_REG_FRAME_BYTE_CNT_LEN) - 1) << CAM_REG_FRAME_BYTE_CNT_POS) -#define CAM_REG_FRAME_BYTE_CNT_UMSK (~(((1U << CAM_REG_FRAME_BYTE_CNT_LEN) - 1) << CAM_REG_FRAME_BYTE_CNT_POS)) - -/* 0x14 : dvp_frame_fifo_pop */ -#define CAM_DVP_FRAME_FIFO_POP_OFFSET (0x14) -#define CAM_RFIFO_POP CAM_RFIFO_POP -#define CAM_RFIFO_POP_POS (0U) -#define CAM_RFIFO_POP_LEN (1U) -#define CAM_RFIFO_POP_MSK (((1U << CAM_RFIFO_POP_LEN) - 1) << CAM_RFIFO_POP_POS) -#define CAM_RFIFO_POP_UMSK (~(((1U << CAM_RFIFO_POP_LEN) - 1) << CAM_RFIFO_POP_POS)) -#define CAM_REG_INT_NORMAL_CLR CAM_REG_INT_NORMAL_CLR -#define CAM_REG_INT_NORMAL_CLR_POS (4U) -#define CAM_REG_INT_NORMAL_CLR_LEN (1U) -#define CAM_REG_INT_NORMAL_CLR_MSK (((1U << CAM_REG_INT_NORMAL_CLR_LEN) - 1) << CAM_REG_INT_NORMAL_CLR_POS) -#define CAM_REG_INT_NORMAL_CLR_UMSK (~(((1U << CAM_REG_INT_NORMAL_CLR_LEN) - 1) << CAM_REG_INT_NORMAL_CLR_POS)) -#define CAM_REG_INT_MEM_CLR CAM_REG_INT_MEM_CLR -#define CAM_REG_INT_MEM_CLR_POS (5U) -#define CAM_REG_INT_MEM_CLR_LEN (1U) -#define CAM_REG_INT_MEM_CLR_MSK (((1U << CAM_REG_INT_MEM_CLR_LEN) - 1) << CAM_REG_INT_MEM_CLR_POS) -#define CAM_REG_INT_MEM_CLR_UMSK (~(((1U << CAM_REG_INT_MEM_CLR_LEN) - 1) << CAM_REG_INT_MEM_CLR_POS)) -#define CAM_REG_INT_FRAME_CLR CAM_REG_INT_FRAME_CLR -#define CAM_REG_INT_FRAME_CLR_POS (6U) -#define CAM_REG_INT_FRAME_CLR_LEN (1U) -#define CAM_REG_INT_FRAME_CLR_MSK (((1U << CAM_REG_INT_FRAME_CLR_LEN) - 1) << CAM_REG_INT_FRAME_CLR_POS) -#define CAM_REG_INT_FRAME_CLR_UMSK (~(((1U << CAM_REG_INT_FRAME_CLR_LEN) - 1) << CAM_REG_INT_FRAME_CLR_POS)) -#define CAM_REG_INT_FIFO_CLR CAM_REG_INT_FIFO_CLR -#define CAM_REG_INT_FIFO_CLR_POS (7U) -#define CAM_REG_INT_FIFO_CLR_LEN (1U) -#define CAM_REG_INT_FIFO_CLR_MSK (((1U << CAM_REG_INT_FIFO_CLR_LEN) - 1) << CAM_REG_INT_FIFO_CLR_POS) -#define CAM_REG_INT_FIFO_CLR_UMSK (~(((1U << CAM_REG_INT_FIFO_CLR_LEN) - 1) << CAM_REG_INT_FIFO_CLR_POS)) -#define CAM_REG_INT_HCNT_CLR CAM_REG_INT_HCNT_CLR -#define CAM_REG_INT_HCNT_CLR_POS (8U) -#define CAM_REG_INT_HCNT_CLR_LEN (1U) -#define CAM_REG_INT_HCNT_CLR_MSK (((1U << CAM_REG_INT_HCNT_CLR_LEN) - 1) << CAM_REG_INT_HCNT_CLR_POS) -#define CAM_REG_INT_HCNT_CLR_UMSK (~(((1U << CAM_REG_INT_HCNT_CLR_LEN) - 1) << CAM_REG_INT_HCNT_CLR_POS)) -#define CAM_REG_INT_VCNT_CLR CAM_REG_INT_VCNT_CLR -#define CAM_REG_INT_VCNT_CLR_POS (9U) -#define CAM_REG_INT_VCNT_CLR_LEN (1U) -#define CAM_REG_INT_VCNT_CLR_MSK (((1U << CAM_REG_INT_VCNT_CLR_LEN) - 1) << CAM_REG_INT_VCNT_CLR_POS) -#define CAM_REG_INT_VCNT_CLR_UMSK (~(((1U << CAM_REG_INT_VCNT_CLR_LEN) - 1) << CAM_REG_INT_VCNT_CLR_POS)) - -/* 0x18 : dvp2axi_frame_vld */ -#define CAM_DVP2AXI_FRAME_VLD_OFFSET (0x18) -#define CAM_REG_FRAME_N_VLD CAM_REG_FRAME_N_VLD -#define CAM_REG_FRAME_N_VLD_POS (0U) -#define CAM_REG_FRAME_N_VLD_LEN (32U) -#define CAM_REG_FRAME_N_VLD_MSK (((1U << CAM_REG_FRAME_N_VLD_LEN) - 1) << CAM_REG_FRAME_N_VLD_POS) -#define CAM_REG_FRAME_N_VLD_UMSK (~(((1U << CAM_REG_FRAME_N_VLD_LEN) - 1) << CAM_REG_FRAME_N_VLD_POS)) - -/* 0x1C : dvp2axi_frame_period */ -#define CAM_DVP2AXI_FRAME_PERIOD_OFFSET (0x1C) -#define CAM_REG_FRAME_PERIOD CAM_REG_FRAME_PERIOD -#define CAM_REG_FRAME_PERIOD_POS (0U) -#define CAM_REG_FRAME_PERIOD_LEN (5U) -#define CAM_REG_FRAME_PERIOD_MSK (((1U << CAM_REG_FRAME_PERIOD_LEN) - 1) << CAM_REG_FRAME_PERIOD_POS) -#define CAM_REG_FRAME_PERIOD_UMSK (~(((1U << CAM_REG_FRAME_PERIOD_LEN) - 1) << CAM_REG_FRAME_PERIOD_POS)) - -/* 0x20 : dvp2axi_misc */ -#define CAM_DVP2AXI_MISC_OFFSET (0x20) -#define CAM_REG_ALPHA CAM_REG_ALPHA -#define CAM_REG_ALPHA_POS (0U) -#define CAM_REG_ALPHA_LEN (8U) -#define CAM_REG_ALPHA_MSK (((1U << CAM_REG_ALPHA_LEN) - 1) << CAM_REG_ALPHA_POS) -#define CAM_REG_ALPHA_UMSK (~(((1U << CAM_REG_ALPHA_LEN) - 1) << CAM_REG_ALPHA_POS)) -#define CAM_REG_FORMAT_565 CAM_REG_FORMAT_565 -#define CAM_REG_FORMAT_565_POS (8U) -#define CAM_REG_FORMAT_565_LEN (3U) -#define CAM_REG_FORMAT_565_MSK (((1U << CAM_REG_FORMAT_565_LEN) - 1) << CAM_REG_FORMAT_565_POS) -#define CAM_REG_FORMAT_565_UMSK (~(((1U << CAM_REG_FORMAT_565_LEN) - 1) << CAM_REG_FORMAT_565_POS)) - -/* 0x30 : dvp2axi_hsync_crop */ -#define CAM_DVP2AXI_HSYNC_CROP_OFFSET (0x30) -#define CAM_REG_HSYNC_ACT_END CAM_REG_HSYNC_ACT_END -#define CAM_REG_HSYNC_ACT_END_POS (0U) -#define CAM_REG_HSYNC_ACT_END_LEN (16U) -#define CAM_REG_HSYNC_ACT_END_MSK (((1U << CAM_REG_HSYNC_ACT_END_LEN) - 1) << CAM_REG_HSYNC_ACT_END_POS) -#define CAM_REG_HSYNC_ACT_END_UMSK (~(((1U << CAM_REG_HSYNC_ACT_END_LEN) - 1) << CAM_REG_HSYNC_ACT_END_POS)) -#define CAM_REG_HSYNC_ACT_START CAM_REG_HSYNC_ACT_START -#define CAM_REG_HSYNC_ACT_START_POS (16U) -#define CAM_REG_HSYNC_ACT_START_LEN (16U) -#define CAM_REG_HSYNC_ACT_START_MSK (((1U << CAM_REG_HSYNC_ACT_START_LEN) - 1) << CAM_REG_HSYNC_ACT_START_POS) -#define CAM_REG_HSYNC_ACT_START_UMSK (~(((1U << CAM_REG_HSYNC_ACT_START_LEN) - 1) << CAM_REG_HSYNC_ACT_START_POS)) - -/* 0x34 : dvp2axi_vsync_crop */ -#define CAM_DVP2AXI_VSYNC_CROP_OFFSET (0x34) -#define CAM_REG_VSYNC_ACT_END CAM_REG_VSYNC_ACT_END -#define CAM_REG_VSYNC_ACT_END_POS (0U) -#define CAM_REG_VSYNC_ACT_END_LEN (16U) -#define CAM_REG_VSYNC_ACT_END_MSK (((1U << CAM_REG_VSYNC_ACT_END_LEN) - 1) << CAM_REG_VSYNC_ACT_END_POS) -#define CAM_REG_VSYNC_ACT_END_UMSK (~(((1U << CAM_REG_VSYNC_ACT_END_LEN) - 1) << CAM_REG_VSYNC_ACT_END_POS)) -#define CAM_REG_VSYNC_ACT_START CAM_REG_VSYNC_ACT_START -#define CAM_REG_VSYNC_ACT_START_POS (16U) -#define CAM_REG_VSYNC_ACT_START_LEN (16U) -#define CAM_REG_VSYNC_ACT_START_MSK (((1U << CAM_REG_VSYNC_ACT_START_LEN) - 1) << CAM_REG_VSYNC_ACT_START_POS) -#define CAM_REG_VSYNC_ACT_START_UMSK (~(((1U << CAM_REG_VSYNC_ACT_START_LEN) - 1) << CAM_REG_VSYNC_ACT_START_POS)) - -/* 0x38 : dvp2axi_fram_exm */ -#define CAM_DVP2AXI_FRAM_EXM_OFFSET (0x38) -#define CAM_REG_TOTAL_HCNT CAM_REG_TOTAL_HCNT -#define CAM_REG_TOTAL_HCNT_POS (0U) -#define CAM_REG_TOTAL_HCNT_LEN (16U) -#define CAM_REG_TOTAL_HCNT_MSK (((1U << CAM_REG_TOTAL_HCNT_LEN) - 1) << CAM_REG_TOTAL_HCNT_POS) -#define CAM_REG_TOTAL_HCNT_UMSK (~(((1U << CAM_REG_TOTAL_HCNT_LEN) - 1) << CAM_REG_TOTAL_HCNT_POS)) -#define CAM_REG_TOTAL_VCNT CAM_REG_TOTAL_VCNT -#define CAM_REG_TOTAL_VCNT_POS (16U) -#define CAM_REG_TOTAL_VCNT_LEN (16U) -#define CAM_REG_TOTAL_VCNT_MSK (((1U << CAM_REG_TOTAL_VCNT_LEN) - 1) << CAM_REG_TOTAL_VCNT_POS) -#define CAM_REG_TOTAL_VCNT_UMSK (~(((1U << CAM_REG_TOTAL_VCNT_LEN) - 1) << CAM_REG_TOTAL_VCNT_POS)) - -/* 0x40 : frame_start_addr0 */ -#define CAM_FRAME_START_ADDR0_OFFSET (0x40) -#define CAM_FRAME_START_ADDR_0 CAM_FRAME_START_ADDR_0 -#define CAM_FRAME_START_ADDR_0_POS (0U) -#define CAM_FRAME_START_ADDR_0_LEN (32U) -#define CAM_FRAME_START_ADDR_0_MSK (((1U << CAM_FRAME_START_ADDR_0_LEN) - 1) << CAM_FRAME_START_ADDR_0_POS) -#define CAM_FRAME_START_ADDR_0_UMSK (~(((1U << CAM_FRAME_START_ADDR_0_LEN) - 1) << CAM_FRAME_START_ADDR_0_POS)) - -/* 0x48 : frame_start_addr1 */ -#define CAM_FRAME_START_ADDR1_OFFSET (0x48) -#define CAM_FRAME_START_ADDR_1 CAM_FRAME_START_ADDR_1 -#define CAM_FRAME_START_ADDR_1_POS (0U) -#define CAM_FRAME_START_ADDR_1_LEN (32U) -#define CAM_FRAME_START_ADDR_1_MSK (((1U << CAM_FRAME_START_ADDR_1_LEN) - 1) << CAM_FRAME_START_ADDR_1_POS) -#define CAM_FRAME_START_ADDR_1_UMSK (~(((1U << CAM_FRAME_START_ADDR_1_LEN) - 1) << CAM_FRAME_START_ADDR_1_POS)) - -/* 0x50 : frame_start_addr2 */ -#define CAM_FRAME_START_ADDR2_OFFSET (0x50) -#define CAM_FRAME_START_ADDR_2 CAM_FRAME_START_ADDR_2 -#define CAM_FRAME_START_ADDR_2_POS (0U) -#define CAM_FRAME_START_ADDR_2_LEN (32U) -#define CAM_FRAME_START_ADDR_2_MSK (((1U << CAM_FRAME_START_ADDR_2_LEN) - 1) << CAM_FRAME_START_ADDR_2_POS) -#define CAM_FRAME_START_ADDR_2_UMSK (~(((1U << CAM_FRAME_START_ADDR_2_LEN) - 1) << CAM_FRAME_START_ADDR_2_POS)) - -/* 0x58 : frame_start_addr3 */ -#define CAM_FRAME_START_ADDR3_OFFSET (0x58) -#define CAM_FRAME_START_ADDR_3 CAM_FRAME_START_ADDR_3 -#define CAM_FRAME_START_ADDR_3_POS (0U) -#define CAM_FRAME_START_ADDR_3_LEN (32U) -#define CAM_FRAME_START_ADDR_3_MSK (((1U << CAM_FRAME_START_ADDR_3_LEN) - 1) << CAM_FRAME_START_ADDR_3_POS) -#define CAM_FRAME_START_ADDR_3_UMSK (~(((1U << CAM_FRAME_START_ADDR_3_LEN) - 1) << CAM_FRAME_START_ADDR_3_POS)) - -/* 0x60 : frame_id_sts01 */ -#define CAM_FRAME_ID_STS01_OFFSET (0x60) -#define CAM_FRAME_ID_0 CAM_FRAME_ID_0 -#define CAM_FRAME_ID_0_POS (0U) -#define CAM_FRAME_ID_0_LEN (16U) -#define CAM_FRAME_ID_0_MSK (((1U << CAM_FRAME_ID_0_LEN) - 1) << CAM_FRAME_ID_0_POS) -#define CAM_FRAME_ID_0_UMSK (~(((1U << CAM_FRAME_ID_0_LEN) - 1) << CAM_FRAME_ID_0_POS)) -#define CAM_FRAME_ID_1 CAM_FRAME_ID_1 -#define CAM_FRAME_ID_1_POS (16U) -#define CAM_FRAME_ID_1_LEN (16U) -#define CAM_FRAME_ID_1_MSK (((1U << CAM_FRAME_ID_1_LEN) - 1) << CAM_FRAME_ID_1_POS) -#define CAM_FRAME_ID_1_UMSK (~(((1U << CAM_FRAME_ID_1_LEN) - 1) << CAM_FRAME_ID_1_POS)) - -/* 0x64 : frame_id_sts23 */ -#define CAM_FRAME_ID_STS23_OFFSET (0x64) -#define CAM_FRAME_ID_2 CAM_FRAME_ID_2 -#define CAM_FRAME_ID_2_POS (0U) -#define CAM_FRAME_ID_2_LEN (16U) -#define CAM_FRAME_ID_2_MSK (((1U << CAM_FRAME_ID_2_LEN) - 1) << CAM_FRAME_ID_2_POS) -#define CAM_FRAME_ID_2_UMSK (~(((1U << CAM_FRAME_ID_2_LEN) - 1) << CAM_FRAME_ID_2_POS)) -#define CAM_FRAME_ID_3 CAM_FRAME_ID_3 -#define CAM_FRAME_ID_3_POS (16U) -#define CAM_FRAME_ID_3_LEN (16U) -#define CAM_FRAME_ID_3_MSK (((1U << CAM_FRAME_ID_3_LEN) - 1) << CAM_FRAME_ID_3_POS) -#define CAM_FRAME_ID_3_UMSK (~(((1U << CAM_FRAME_ID_3_LEN) - 1) << CAM_FRAME_ID_3_POS)) - -/* 0xF0 : dvp_debug */ -#define CAM_DVP_DEBUG_OFFSET (0xF0) -#define CAM_REG_DVP_DBG_EN CAM_REG_DVP_DBG_EN -#define CAM_REG_DVP_DBG_EN_POS (0U) -#define CAM_REG_DVP_DBG_EN_LEN (1U) -#define CAM_REG_DVP_DBG_EN_MSK (((1U << CAM_REG_DVP_DBG_EN_LEN) - 1) << CAM_REG_DVP_DBG_EN_POS) -#define CAM_REG_DVP_DBG_EN_UMSK (~(((1U << CAM_REG_DVP_DBG_EN_LEN) - 1) << CAM_REG_DVP_DBG_EN_POS)) -#define CAM_REG_DVP_DBG_SEL CAM_REG_DVP_DBG_SEL -#define CAM_REG_DVP_DBG_SEL_POS (1U) -#define CAM_REG_DVP_DBG_SEL_LEN (3U) -#define CAM_REG_DVP_DBG_SEL_MSK (((1U << CAM_REG_DVP_DBG_SEL_LEN) - 1) << CAM_REG_DVP_DBG_SEL_POS) -#define CAM_REG_DVP_DBG_SEL_UMSK (~(((1U << CAM_REG_DVP_DBG_SEL_LEN) - 1) << CAM_REG_DVP_DBG_SEL_POS)) -#define CAM_REG_ID_LATCH_LINE CAM_REG_ID_LATCH_LINE -#define CAM_REG_ID_LATCH_LINE_POS (8U) -#define CAM_REG_ID_LATCH_LINE_LEN (4U) -#define CAM_REG_ID_LATCH_LINE_MSK (((1U << CAM_REG_ID_LATCH_LINE_LEN) - 1) << CAM_REG_ID_LATCH_LINE_POS) -#define CAM_REG_ID_LATCH_LINE_UMSK (~(((1U << CAM_REG_ID_LATCH_LINE_LEN) - 1) << CAM_REG_ID_LATCH_LINE_POS)) - -/* 0xFC : dvp_dummy_reg */ -#define CAM_DVP_DUMMY_REG_OFFSET (0xFC) - -struct cam_reg { - /* 0x0 : dvp2axi_configue */ - union { - struct { - uint32_t reg_dvp_enable : 1; /* [ 0], r/w, 0x0 */ - uint32_t reg_sw_mode : 1; /* [ 1], r/w, 0x0 */ - uint32_t reg_fram_vld_pol : 1; /* [ 2], r/w, 0x1 */ - uint32_t reg_line_vld_pol : 1; /* [ 3], r/w, 0x1 */ - uint32_t reg_xlen : 3; /* [ 6: 4], r/w, 0x3 */ - uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ - uint32_t reg_dvp_mode : 3; /* [10: 8], r/w, 0x0 */ - uint32_t reg_hw_mode_fwrap : 1; /* [ 11], r/w, 0x1 */ - uint32_t reg_drop_en : 1; /* [ 12], r/w, 0x0 */ - uint32_t reg_drop_even : 1; /* [ 13], r/w, 0x0 */ - uint32_t reg_qos_sw_mode : 1; /* [ 14], r/w, 0x0 */ - uint32_t reg_qos_sw : 1; /* [ 15], r/w, 0x0 */ - uint32_t reg_dvp_data_mode : 3; /* [18:16], r/w, 0x0 */ - uint32_t reg_dvp_data_bsel : 1; /* [ 19], r/w, 0x0 */ - uint32_t reg_dvp_pix_clk_cg : 1; /* [ 20], r/w, 0x0 */ - uint32_t reserved_21 : 1; /* [ 21], rsvd, 0x0 */ - uint32_t reg_v_subsample_en : 1; /* [ 22], r/w, 0x0 */ - uint32_t reg_v_subsample_pol : 1; /* [ 23], r/w, 0x0 */ - uint32_t reg_dvp_wait_cycle : 8; /* [31:24], r/w, 0x40 */ - } BF; - uint32_t WORD; - } dvp2axi_configue; - - /* 0x4 : dvp2axi_addr_start */ - union { - struct { - uint32_t reg_addr_start : 32; /* [31: 0], r/w, 0x80000000 */ - } BF; - uint32_t WORD; - } dvp2axi_addr_start; - - /* 0x8 : dvp2axi_mem_bcnt */ - union { - struct { - uint32_t reg_mem_burst_cnt : 32; /* [31: 0], r/w, 0xc000 */ - } BF; - uint32_t WORD; - } dvp2axi_mem_bcnt; - - /* 0xC : dvp_status_and_error */ - union { - struct { - uint32_t reg_frame_cnt_trgr_int : 5; /* [ 4: 0], r/w, 0x0 */ - uint32_t reserved_5 : 1; /* [ 5], rsvd, 0x0 */ - uint32_t reg_int_hcnt_en : 1; /* [ 6], r/w, 0x0 */ - uint32_t reg_int_vcnt_en : 1; /* [ 7], r/w, 0x0 */ - uint32_t reg_int_normal_en : 1; /* [ 8], r/w, 0x0 */ - uint32_t reg_int_mem_en : 1; /* [ 9], r/w, 0x0 */ - uint32_t reg_int_frame_en : 1; /* [ 10], r/w, 0x0 */ - uint32_t reg_int_fifo_en : 1; /* [ 11], r/w, 0x1 */ - uint32_t sts_normal_int : 1; /* [ 12], r, 0x0 */ - uint32_t sts_mem_int : 1; /* [ 13], r, 0x0 */ - uint32_t sts_frame_int : 1; /* [ 14], r, 0x0 */ - uint32_t sts_fifo_int : 1; /* [ 15], r, 0x0 */ - uint32_t frame_valid_cnt : 5; /* [20:16], r, 0x0 */ - uint32_t sts_hcnt_int : 1; /* [ 21], r, 0x0 */ - uint32_t sts_vcnt_int : 1; /* [ 22], r, 0x0 */ - uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */ - uint32_t st_bus_idle : 1; /* [ 24], r, 0x1 */ - uint32_t st_bus_func : 1; /* [ 25], r, 0x0 */ - uint32_t st_bus_wait : 1; /* [ 26], r, 0x0 */ - uint32_t st_bus_flsh : 1; /* [ 27], r, 0x0 */ - uint32_t axi_idle : 1; /* [ 28], r, 0x1 */ - uint32_t st_dvp_idle : 1; /* [ 29], r, 0x1 */ - uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dvp_status_and_error; - - /* 0x10 : dvp2axi_frame_bcnt */ - union { - struct { - uint32_t reg_frame_byte_cnt : 32; /* [31: 0], r/w, 0x7e90 */ - } BF; - uint32_t WORD; - } dvp2axi_frame_bcnt; - - /* 0x14 : dvp_frame_fifo_pop */ - union { - struct { - uint32_t rfifo_pop : 1; /* [ 0], w1p, 0x0 */ - uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ - uint32_t reg_int_normal_clr : 1; /* [ 4], w1p, 0x0 */ - uint32_t reg_int_mem_clr : 1; /* [ 5], w1p, 0x0 */ - uint32_t reg_int_frame_clr : 1; /* [ 6], w1p, 0x0 */ - uint32_t reg_int_fifo_clr : 1; /* [ 7], w1p, 0x0 */ - uint32_t reg_int_hcnt_clr : 1; /* [ 8], w1p, 0x0 */ - uint32_t reg_int_vcnt_clr : 1; /* [ 9], w1p, 0x0 */ - uint32_t reserved_10_31 : 22; /* [31:10], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dvp_frame_fifo_pop; - - /* 0x18 : dvp2axi_frame_vld */ - union { - struct { - uint32_t reg_frame_n_vld : 32; /* [31: 0], r/w, 0xffffffff */ - } BF; - uint32_t WORD; - } dvp2axi_frame_vld; - - /* 0x1C : dvp2axi_frame_period */ - union { - struct { - uint32_t reg_frame_period : 5; /* [ 4: 0], r/w, 0x0 */ - uint32_t reserved_5_31 : 27; /* [31: 5], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dvp2axi_frame_period; - - /* 0x20 : dvp2axi_misc */ - union { - struct { - uint32_t reg_alpha : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_format_565 : 3; /* [10: 8], r/w, 0x0 */ - uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dvp2axi_misc; - - /* 0x24 reserved */ - uint8_t RESERVED0x24[12]; - - /* 0x30 : dvp2axi_hsync_crop */ - union { - struct { - uint32_t reg_hsync_act_end : 16; /* [15: 0], r/w, 0xffff */ - uint32_t reg_hsync_act_start : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dvp2axi_hsync_crop; - - /* 0x34 : dvp2axi_vsync_crop */ - union { - struct { - uint32_t reg_vsync_act_end : 16; /* [15: 0], r/w, 0xffff */ - uint32_t reg_vsync_act_start : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dvp2axi_vsync_crop; - - /* 0x38 : dvp2axi_fram_exm */ - union { - struct { - uint32_t reg_total_hcnt : 16; /* [15: 0], r/w, 0x0 */ - uint32_t reg_total_vcnt : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dvp2axi_fram_exm; - - /* 0x3c reserved */ - uint8_t RESERVED0x3c[4]; - - /* 0x40 : frame_start_addr0 */ - union { - struct { - uint32_t frame_start_addr_0 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } frame_start_addr0; - - /* 0x44 reserved */ - uint8_t RESERVED0x44[4]; - - /* 0x48 : frame_start_addr1 */ - union { - struct { - uint32_t frame_start_addr_1 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } frame_start_addr1; - - /* 0x4c reserved */ - uint8_t RESERVED0x4c[4]; - - /* 0x50 : frame_start_addr2 */ - union { - struct { - uint32_t frame_start_addr_2 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } frame_start_addr2; - - /* 0x54 reserved */ - uint8_t RESERVED0x54[4]; - - /* 0x58 : frame_start_addr3 */ - union { - struct { - uint32_t frame_start_addr_3 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } frame_start_addr3; - - /* 0x5c reserved */ - uint8_t RESERVED0x5c[4]; - - /* 0x60 : frame_id_sts01 */ - union { - struct { - uint32_t frame_id_0 : 16; /* [15: 0], r, 0x0 */ - uint32_t frame_id_1 : 16; /* [31:16], r, 0x0 */ - } BF; - uint32_t WORD; - } frame_id_sts01; - - /* 0x64 : frame_id_sts23 */ - union { - struct { - uint32_t frame_id_2 : 16; /* [15: 0], r, 0x0 */ - uint32_t frame_id_3 : 16; /* [31:16], r, 0x0 */ - } BF; - uint32_t WORD; - } frame_id_sts23; - - /* 0x68 reserved */ - uint8_t RESERVED0x68[136]; - - /* 0xF0 : dvp_debug */ - union { - struct { - uint32_t reg_dvp_dbg_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t reg_dvp_dbg_sel : 3; /* [ 3: 1], r/w, 0x0 */ - uint32_t reserved_4_7 : 4; /* [ 7: 4], rsvd, 0x0 */ - uint32_t reg_id_latch_line : 4; /* [11: 8], r/w, 0x5 */ - uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dvp_debug; - - /* 0xf4 reserved */ - uint8_t RESERVED0xf4[8]; - - /* 0xFC : dvp_dummy_reg */ - union { - struct { - uint32_t RESERVED_31_0 : 32; /* [31: 0], rsvd, 0xf0f0f0f0 */ - } BF; - uint32_t WORD; - } dvp_dummy_reg; -}; - -typedef volatile struct cam_reg cam_reg_t; - -#endif /* __CAM_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/can_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/can_reg.h deleted file mode 100644 index 11516e591c..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/can_reg.h +++ /dev/null @@ -1,807 +0,0 @@ -/** - ****************************************************************************** - * @file can_reg.h - * @version V1.0 - * @date 2020-12-29 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __CAN_REG_H__ -#define __CAN_REG_H__ - -#include "bl808.h" - -/* 0x0 : op mode:rw reset mode:rw */ -#define CAN_MODE_OFFSET (0x0) -#define CAN_RESET_REQUEST CAN_RESET_REQUEST -#define CAN_RESET_REQUEST_POS (0U) -#define CAN_RESET_REQUEST_LEN (1U) -#define CAN_RESET_REQUEST_MSK (((1U << CAN_RESET_REQUEST_LEN) - 1) << CAN_RESET_REQUEST_POS) -#define CAN_RESET_REQUEST_UMSK (~(((1U << CAN_RESET_REQUEST_LEN) - 1) << CAN_RESET_REQUEST_POS)) -#define CAN_LISTEN_ONLY CAN_LISTEN_ONLY -#define CAN_LISTEN_ONLY_POS (1U) -#define CAN_LISTEN_ONLY_LEN (1U) -#define CAN_LISTEN_ONLY_MSK (((1U << CAN_LISTEN_ONLY_LEN) - 1) << CAN_LISTEN_ONLY_POS) -#define CAN_LISTEN_ONLY_UMSK (~(((1U << CAN_LISTEN_ONLY_LEN) - 1) << CAN_LISTEN_ONLY_POS)) -#define CAN_SELT_TEST CAN_SELT_TEST -#define CAN_SELT_TEST_POS (2U) -#define CAN_SELT_TEST_LEN (1U) -#define CAN_SELT_TEST_MSK (((1U << CAN_SELT_TEST_LEN) - 1) << CAN_SELT_TEST_POS) -#define CAN_SELT_TEST_UMSK (~(((1U << CAN_SELT_TEST_LEN) - 1) << CAN_SELT_TEST_POS)) -#define CAN_ACCEPTANCE_FILTER CAN_ACCEPTANCE_FILTER -#define CAN_ACCEPTANCE_FILTER_POS (3U) -#define CAN_ACCEPTANCE_FILTER_LEN (1U) -#define CAN_ACCEPTANCE_FILTER_MSK (((1U << CAN_ACCEPTANCE_FILTER_LEN) - 1) << CAN_ACCEPTANCE_FILTER_POS) -#define CAN_ACCEPTANCE_FILTER_UMSK (~(((1U << CAN_ACCEPTANCE_FILTER_LEN) - 1) << CAN_ACCEPTANCE_FILTER_POS)) - -/* 0x4 : op mode:w r -> 8'h00 -reset mode:w r -> 8'h00 */ -#define CAN_COMMAND_OFFSET (0x4) -#define CAN_TRANSMIT_REQUEST CAN_TRANSMIT_REQUEST -#define CAN_TRANSMIT_REQUEST_POS (0U) -#define CAN_TRANSMIT_REQUEST_LEN (1U) -#define CAN_TRANSMIT_REQUEST_MSK (((1U << CAN_TRANSMIT_REQUEST_LEN) - 1) << CAN_TRANSMIT_REQUEST_POS) -#define CAN_TRANSMIT_REQUEST_UMSK (~(((1U << CAN_TRANSMIT_REQUEST_LEN) - 1) << CAN_TRANSMIT_REQUEST_POS)) -#define CAN_ABORT_TRANSMISSION CAN_ABORT_TRANSMISSION -#define CAN_ABORT_TRANSMISSION_POS (1U) -#define CAN_ABORT_TRANSMISSION_LEN (1U) -#define CAN_ABORT_TRANSMISSION_MSK (((1U << CAN_ABORT_TRANSMISSION_LEN) - 1) << CAN_ABORT_TRANSMISSION_POS) -#define CAN_ABORT_TRANSMISSION_UMSK (~(((1U << CAN_ABORT_TRANSMISSION_LEN) - 1) << CAN_ABORT_TRANSMISSION_POS)) -#define CAN_RELEASE_RECEIVE_BUFFER CAN_RELEASE_RECEIVE_BUFFER -#define CAN_RELEASE_RECEIVE_BUFFER_POS (2U) -#define CAN_RELEASE_RECEIVE_BUFFER_LEN (1U) -#define CAN_RELEASE_RECEIVE_BUFFER_MSK (((1U << CAN_RELEASE_RECEIVE_BUFFER_LEN) - 1) << CAN_RELEASE_RECEIVE_BUFFER_POS) -#define CAN_RELEASE_RECEIVE_BUFFER_UMSK (~(((1U << CAN_RELEASE_RECEIVE_BUFFER_LEN) - 1) << CAN_RELEASE_RECEIVE_BUFFER_POS)) -#define CAN_CLEAR_DATA_OVERRUN CAN_CLEAR_DATA_OVERRUN -#define CAN_CLEAR_DATA_OVERRUN_POS (3U) -#define CAN_CLEAR_DATA_OVERRUN_LEN (1U) -#define CAN_CLEAR_DATA_OVERRUN_MSK (((1U << CAN_CLEAR_DATA_OVERRUN_LEN) - 1) << CAN_CLEAR_DATA_OVERRUN_POS) -#define CAN_CLEAR_DATA_OVERRUN_UMSK (~(((1U << CAN_CLEAR_DATA_OVERRUN_LEN) - 1) << CAN_CLEAR_DATA_OVERRUN_POS)) -#define CAN_SELF_REQUEST CAN_SELF_REQUEST -#define CAN_SELF_REQUEST_POS (4U) -#define CAN_SELF_REQUEST_LEN (1U) -#define CAN_SELF_REQUEST_MSK (((1U << CAN_SELF_REQUEST_LEN) - 1) << CAN_SELF_REQUEST_POS) -#define CAN_SELF_REQUEST_UMSK (~(((1U << CAN_SELF_REQUEST_LEN) - 1) << CAN_SELF_REQUEST_POS)) - -/* 0x8 : op mode:r reset mode:r */ -#define CAN_STATUS_OFFSET (0x8) -#define CAN_RECEIVE_BUFFER_STS CAN_RECEIVE_BUFFER_STS -#define CAN_RECEIVE_BUFFER_STS_POS (0U) -#define CAN_RECEIVE_BUFFER_STS_LEN (1U) -#define CAN_RECEIVE_BUFFER_STS_MSK (((1U << CAN_RECEIVE_BUFFER_STS_LEN) - 1) << CAN_RECEIVE_BUFFER_STS_POS) -#define CAN_RECEIVE_BUFFER_STS_UMSK (~(((1U << CAN_RECEIVE_BUFFER_STS_LEN) - 1) << CAN_RECEIVE_BUFFER_STS_POS)) -#define CAN_DATA_OVERRUN_STS CAN_DATA_OVERRUN_STS -#define CAN_DATA_OVERRUN_STS_POS (1U) -#define CAN_DATA_OVERRUN_STS_LEN (1U) -#define CAN_DATA_OVERRUN_STS_MSK (((1U << CAN_DATA_OVERRUN_STS_LEN) - 1) << CAN_DATA_OVERRUN_STS_POS) -#define CAN_DATA_OVERRUN_STS_UMSK (~(((1U << CAN_DATA_OVERRUN_STS_LEN) - 1) << CAN_DATA_OVERRUN_STS_POS)) -#define CAN_TRANSMIT_BUFFER_STS CAN_TRANSMIT_BUFFER_STS -#define CAN_TRANSMIT_BUFFER_STS_POS (2U) -#define CAN_TRANSMIT_BUFFER_STS_LEN (1U) -#define CAN_TRANSMIT_BUFFER_STS_MSK (((1U << CAN_TRANSMIT_BUFFER_STS_LEN) - 1) << CAN_TRANSMIT_BUFFER_STS_POS) -#define CAN_TRANSMIT_BUFFER_STS_UMSK (~(((1U << CAN_TRANSMIT_BUFFER_STS_LEN) - 1) << CAN_TRANSMIT_BUFFER_STS_POS)) -#define CAN_TRANSMIT_COMPLETE_STS CAN_TRANSMIT_COMPLETE_STS -#define CAN_TRANSMIT_COMPLETE_STS_POS (3U) -#define CAN_TRANSMIT_COMPLETE_STS_LEN (1U) -#define CAN_TRANSMIT_COMPLETE_STS_MSK (((1U << CAN_TRANSMIT_COMPLETE_STS_LEN) - 1) << CAN_TRANSMIT_COMPLETE_STS_POS) -#define CAN_TRANSMIT_COMPLETE_STS_UMSK (~(((1U << CAN_TRANSMIT_COMPLETE_STS_LEN) - 1) << CAN_TRANSMIT_COMPLETE_STS_POS)) -#define CAN_RECEIVE_STS CAN_RECEIVE_STS -#define CAN_RECEIVE_STS_POS (4U) -#define CAN_RECEIVE_STS_LEN (1U) -#define CAN_RECEIVE_STS_MSK (((1U << CAN_RECEIVE_STS_LEN) - 1) << CAN_RECEIVE_STS_POS) -#define CAN_RECEIVE_STS_UMSK (~(((1U << CAN_RECEIVE_STS_LEN) - 1) << CAN_RECEIVE_STS_POS)) -#define CAN_TRANSMIT_STS CAN_TRANSMIT_STS -#define CAN_TRANSMIT_STS_POS (5U) -#define CAN_TRANSMIT_STS_LEN (1U) -#define CAN_TRANSMIT_STS_MSK (((1U << CAN_TRANSMIT_STS_LEN) - 1) << CAN_TRANSMIT_STS_POS) -#define CAN_TRANSMIT_STS_UMSK (~(((1U << CAN_TRANSMIT_STS_LEN) - 1) << CAN_TRANSMIT_STS_POS)) -#define CAN_ERROR_STS CAN_ERROR_STS -#define CAN_ERROR_STS_POS (6U) -#define CAN_ERROR_STS_LEN (1U) -#define CAN_ERROR_STS_MSK (((1U << CAN_ERROR_STS_LEN) - 1) << CAN_ERROR_STS_POS) -#define CAN_ERROR_STS_UMSK (~(((1U << CAN_ERROR_STS_LEN) - 1) << CAN_ERROR_STS_POS)) -#define CAN_BUS_STS CAN_BUS_STS -#define CAN_BUS_STS_POS (7U) -#define CAN_BUS_STS_LEN (1U) -#define CAN_BUS_STS_MSK (((1U << CAN_BUS_STS_LEN) - 1) << CAN_BUS_STS_POS) -#define CAN_BUS_STS_UMSK (~(((1U << CAN_BUS_STS_LEN) - 1) << CAN_BUS_STS_POS)) - -/* 0xc : op mode:r reset mode:r when be read,all bits are reseted and can_int disappear */ -#define CAN_INTERRUPT_OFFSET (0xc) -#define CAN_RECEIVE_INT CAN_RECEIVE_INT -#define CAN_RECEIVE_INT_POS (0U) -#define CAN_RECEIVE_INT_LEN (1U) -#define CAN_RECEIVE_INT_MSK (((1U << CAN_RECEIVE_INT_LEN) - 1) << CAN_RECEIVE_INT_POS) -#define CAN_RECEIVE_INT_UMSK (~(((1U << CAN_RECEIVE_INT_LEN) - 1) << CAN_RECEIVE_INT_POS)) -#define CAN_TRANSMIT_INT CAN_TRANSMIT_INT -#define CAN_TRANSMIT_INT_POS (1U) -#define CAN_TRANSMIT_INT_LEN (1U) -#define CAN_TRANSMIT_INT_MSK (((1U << CAN_TRANSMIT_INT_LEN) - 1) << CAN_TRANSMIT_INT_POS) -#define CAN_TRANSMIT_INT_UMSK (~(((1U << CAN_TRANSMIT_INT_LEN) - 1) << CAN_TRANSMIT_INT_POS)) -#define CAN_ERROR_INT CAN_ERROR_INT -#define CAN_ERROR_INT_POS (2U) -#define CAN_ERROR_INT_LEN (1U) -#define CAN_ERROR_INT_MSK (((1U << CAN_ERROR_INT_LEN) - 1) << CAN_ERROR_INT_POS) -#define CAN_ERROR_INT_UMSK (~(((1U << CAN_ERROR_INT_LEN) - 1) << CAN_ERROR_INT_POS)) -#define CAN_DATA_OVERRUN_INT CAN_DATA_OVERRUN_INT -#define CAN_DATA_OVERRUN_INT_POS (3U) -#define CAN_DATA_OVERRUN_INT_LEN (1U) -#define CAN_DATA_OVERRUN_INT_MSK (((1U << CAN_DATA_OVERRUN_INT_LEN) - 1) << CAN_DATA_OVERRUN_INT_POS) -#define CAN_DATA_OVERRUN_INT_UMSK (~(((1U << CAN_DATA_OVERRUN_INT_LEN) - 1) << CAN_DATA_OVERRUN_INT_POS)) -#define CAN_ERROR_PASSIVE_INT CAN_ERROR_PASSIVE_INT -#define CAN_ERROR_PASSIVE_INT_POS (5U) -#define CAN_ERROR_PASSIVE_INT_LEN (1U) -#define CAN_ERROR_PASSIVE_INT_MSK (((1U << CAN_ERROR_PASSIVE_INT_LEN) - 1) << CAN_ERROR_PASSIVE_INT_POS) -#define CAN_ERROR_PASSIVE_INT_UMSK (~(((1U << CAN_ERROR_PASSIVE_INT_LEN) - 1) << CAN_ERROR_PASSIVE_INT_POS)) -#define CAN_ARB_LOST_INT CAN_ARB_LOST_INT -#define CAN_ARB_LOST_INT_POS (6U) -#define CAN_ARB_LOST_INT_LEN (1U) -#define CAN_ARB_LOST_INT_MSK (((1U << CAN_ARB_LOST_INT_LEN) - 1) << CAN_ARB_LOST_INT_POS) -#define CAN_ARB_LOST_INT_UMSK (~(((1U << CAN_ARB_LOST_INT_LEN) - 1) << CAN_ARB_LOST_INT_POS)) -#define CAN_BUS_ERROR_INT CAN_BUS_ERROR_INT -#define CAN_BUS_ERROR_INT_POS (7U) -#define CAN_BUS_ERROR_INT_LEN (1U) -#define CAN_BUS_ERROR_INT_MSK (((1U << CAN_BUS_ERROR_INT_LEN) - 1) << CAN_BUS_ERROR_INT_POS) -#define CAN_BUS_ERROR_INT_UMSK (~(((1U << CAN_BUS_ERROR_INT_LEN) - 1) << CAN_BUS_ERROR_INT_POS)) - -/* 0x10 : op mode:rw reset mode:rw when be read,all bits are reseted and can_int disappear */ -#define CAN_INTERRUPT_ENABLE_OFFSET (0x10) -#define CAN_RECEIVE_INT_EN CAN_RECEIVE_INT_EN -#define CAN_RECEIVE_INT_EN_POS (0U) -#define CAN_RECEIVE_INT_EN_LEN (1U) -#define CAN_RECEIVE_INT_EN_MSK (((1U << CAN_RECEIVE_INT_EN_LEN) - 1) << CAN_RECEIVE_INT_EN_POS) -#define CAN_RECEIVE_INT_EN_UMSK (~(((1U << CAN_RECEIVE_INT_EN_LEN) - 1) << CAN_RECEIVE_INT_EN_POS)) -#define CAN_TRANSMIT_INT_EN CAN_TRANSMIT_INT_EN -#define CAN_TRANSMIT_INT_EN_POS (1U) -#define CAN_TRANSMIT_INT_EN_LEN (1U) -#define CAN_TRANSMIT_INT_EN_MSK (((1U << CAN_TRANSMIT_INT_EN_LEN) - 1) << CAN_TRANSMIT_INT_EN_POS) -#define CAN_TRANSMIT_INT_EN_UMSK (~(((1U << CAN_TRANSMIT_INT_EN_LEN) - 1) << CAN_TRANSMIT_INT_EN_POS)) -#define CAN_ERROR_INT_EN CAN_ERROR_INT_EN -#define CAN_ERROR_INT_EN_POS (2U) -#define CAN_ERROR_INT_EN_LEN (1U) -#define CAN_ERROR_INT_EN_MSK (((1U << CAN_ERROR_INT_EN_LEN) - 1) << CAN_ERROR_INT_EN_POS) -#define CAN_ERROR_INT_EN_UMSK (~(((1U << CAN_ERROR_INT_EN_LEN) - 1) << CAN_ERROR_INT_EN_POS)) -#define CAN_DATA_OVERRUN_INT_EN CAN_DATA_OVERRUN_INT_EN -#define CAN_DATA_OVERRUN_INT_EN_POS (3U) -#define CAN_DATA_OVERRUN_INT_EN_LEN (1U) -#define CAN_DATA_OVERRUN_INT_EN_MSK (((1U << CAN_DATA_OVERRUN_INT_EN_LEN) - 1) << CAN_DATA_OVERRUN_INT_EN_POS) -#define CAN_DATA_OVERRUN_INT_EN_UMSK (~(((1U << CAN_DATA_OVERRUN_INT_EN_LEN) - 1) << CAN_DATA_OVERRUN_INT_EN_POS)) -#define CAN_ERROR_PASSIVE_INT_EN CAN_ERROR_PASSIVE_INT_EN -#define CAN_ERROR_PASSIVE_INT_EN_POS (5U) -#define CAN_ERROR_PASSIVE_INT_EN_LEN (1U) -#define CAN_ERROR_PASSIVE_INT_EN_MSK (((1U << CAN_ERROR_PASSIVE_INT_EN_LEN) - 1) << CAN_ERROR_PASSIVE_INT_EN_POS) -#define CAN_ERROR_PASSIVE_INT_EN_UMSK (~(((1U << CAN_ERROR_PASSIVE_INT_EN_LEN) - 1) << CAN_ERROR_PASSIVE_INT_EN_POS)) -#define CAN_ARB_LOST_INT_EN CAN_ARB_LOST_INT_EN -#define CAN_ARB_LOST_INT_EN_POS (6U) -#define CAN_ARB_LOST_INT_EN_LEN (1U) -#define CAN_ARB_LOST_INT_EN_MSK (((1U << CAN_ARB_LOST_INT_EN_LEN) - 1) << CAN_ARB_LOST_INT_EN_POS) -#define CAN_ARB_LOST_INT_EN_UMSK (~(((1U << CAN_ARB_LOST_INT_EN_LEN) - 1) << CAN_ARB_LOST_INT_EN_POS)) -#define CAN_BUS_ERROR_INT_EN CAN_BUS_ERROR_INT_EN -#define CAN_BUS_ERROR_INT_EN_POS (7U) -#define CAN_BUS_ERROR_INT_EN_LEN (1U) -#define CAN_BUS_ERROR_INT_EN_MSK (((1U << CAN_BUS_ERROR_INT_EN_LEN) - 1) << CAN_BUS_ERROR_INT_EN_POS) -#define CAN_BUS_ERROR_INT_EN_UMSK (~(((1U << CAN_BUS_ERROR_INT_EN_LEN) - 1) << CAN_BUS_ERROR_INT_EN_POS)) - -/* 0x18 : op mode:r reset mode:rw */ -#define CAN_BUS_TIMING_0_OFFSET (0x18) -#define CAN_BAUD_RATE_PRESCALER CAN_BAUD_RATE_PRESCALER -#define CAN_BAUD_RATE_PRESCALER_POS (0U) -#define CAN_BAUD_RATE_PRESCALER_LEN (6U) -#define CAN_BAUD_RATE_PRESCALER_MSK (((1U << CAN_BAUD_RATE_PRESCALER_LEN) - 1) << CAN_BAUD_RATE_PRESCALER_POS) -#define CAN_BAUD_RATE_PRESCALER_UMSK (~(((1U << CAN_BAUD_RATE_PRESCALER_LEN) - 1) << CAN_BAUD_RATE_PRESCALER_POS)) -#define CAN_SYNC_JUMP_WIDTH CAN_SYNC_JUMP_WIDTH -#define CAN_SYNC_JUMP_WIDTH_POS (6U) -#define CAN_SYNC_JUMP_WIDTH_LEN (2U) -#define CAN_SYNC_JUMP_WIDTH_MSK (((1U << CAN_SYNC_JUMP_WIDTH_LEN) - 1) << CAN_SYNC_JUMP_WIDTH_POS) -#define CAN_SYNC_JUMP_WIDTH_UMSK (~(((1U << CAN_SYNC_JUMP_WIDTH_LEN) - 1) << CAN_SYNC_JUMP_WIDTH_POS)) - -/* 0x1c : op mode:r reset mode:rw */ -#define CAN_BUS_TIMING_1_OFFSET (0x1c) -#define CAN_TIME_SEGMENT_1 CAN_TIME_SEGMENT_1 -#define CAN_TIME_SEGMENT_1_POS (0U) -#define CAN_TIME_SEGMENT_1_LEN (4U) -#define CAN_TIME_SEGMENT_1_MSK (((1U << CAN_TIME_SEGMENT_1_LEN) - 1) << CAN_TIME_SEGMENT_1_POS) -#define CAN_TIME_SEGMENT_1_UMSK (~(((1U << CAN_TIME_SEGMENT_1_LEN) - 1) << CAN_TIME_SEGMENT_1_POS)) -#define CAN_TIME_SEGMENT_2 CAN_TIME_SEGMENT_2 -#define CAN_TIME_SEGMENT_2_POS (4U) -#define CAN_TIME_SEGMENT_2_LEN (3U) -#define CAN_TIME_SEGMENT_2_MSK (((1U << CAN_TIME_SEGMENT_2_LEN) - 1) << CAN_TIME_SEGMENT_2_POS) -#define CAN_TIME_SEGMENT_2_UMSK (~(((1U << CAN_TIME_SEGMENT_2_LEN) - 1) << CAN_TIME_SEGMENT_2_POS)) -#define CAN_SAMPLING CAN_SAMPLING -#define CAN_SAMPLING_POS (7U) -#define CAN_SAMPLING_LEN (1U) -#define CAN_SAMPLING_MSK (((1U << CAN_SAMPLING_LEN) - 1) << CAN_SAMPLING_POS) -#define CAN_SAMPLING_UMSK (~(((1U << CAN_SAMPLING_LEN) - 1) << CAN_SAMPLING_POS)) - -/* 0x2c : op mode:r reset mode:r */ -#define CAN_ARB_LOST_CAPTURE_OFFSET (0x2c) -#define CAN_ALC4_0 CAN_ALC4_0 -#define CAN_ALC4_0_POS (0U) -#define CAN_ALC4_0_LEN (5U) -#define CAN_ALC4_0_MSK (((1U << CAN_ALC4_0_LEN) - 1) << CAN_ALC4_0_POS) -#define CAN_ALC4_0_UMSK (~(((1U << CAN_ALC4_0_LEN) - 1) << CAN_ALC4_0_POS)) - -/* 0x30 : op mode:r reset mode:r */ -#define CAN_ERROR_CODE_CAPTURE_OFFSET (0x30) -#define CAN_SEGMENT4_0 CAN_SEGMENT4_0 -#define CAN_SEGMENT4_0_POS (0U) -#define CAN_SEGMENT4_0_LEN (5U) -#define CAN_SEGMENT4_0_MSK (((1U << CAN_SEGMENT4_0_LEN) - 1) << CAN_SEGMENT4_0_POS) -#define CAN_SEGMENT4_0_UMSK (~(((1U << CAN_SEGMENT4_0_LEN) - 1) << CAN_SEGMENT4_0_POS)) -#define CAN_DIR CAN_DIR -#define CAN_DIR_POS (5U) -#define CAN_DIR_LEN (1U) -#define CAN_DIR_MSK (((1U << CAN_DIR_LEN) - 1) << CAN_DIR_POS) -#define CAN_DIR_UMSK (~(((1U << CAN_DIR_LEN) - 1) << CAN_DIR_POS)) -#define CAN_ERR_CODE CAN_ERR_CODE -#define CAN_ERR_CODE_POS (6U) -#define CAN_ERR_CODE_LEN (2U) -#define CAN_ERR_CODE_MSK (((1U << CAN_ERR_CODE_LEN) - 1) << CAN_ERR_CODE_POS) -#define CAN_ERR_CODE_UMSK (~(((1U << CAN_ERR_CODE_LEN) - 1) << CAN_ERR_CODE_POS)) - -/* 0x34 : op mode:r reset mode:rw */ -#define CAN_ERROR_WARNING_LIMIT_OFFSET (0x34) -#define CAN_ERR_WARNING_LIMIT CAN_ERR_WARNING_LIMIT -#define CAN_ERR_WARNING_LIMIT_POS (0U) -#define CAN_ERR_WARNING_LIMIT_LEN (8U) -#define CAN_ERR_WARNING_LIMIT_MSK (((1U << CAN_ERR_WARNING_LIMIT_LEN) - 1) << CAN_ERR_WARNING_LIMIT_POS) -#define CAN_ERR_WARNING_LIMIT_UMSK (~(((1U << CAN_ERR_WARNING_LIMIT_LEN) - 1) << CAN_ERR_WARNING_LIMIT_POS)) - -/* 0x38 : op mode:r reset mode:rw */ -#define CAN_RX_ERR_COUNT_OFFSET (0x38) -#define CAN_RX_ERR_CNT CAN_RX_ERR_CNT -#define CAN_RX_ERR_CNT_POS (0U) -#define CAN_RX_ERR_CNT_LEN (8U) -#define CAN_RX_ERR_CNT_MSK (((1U << CAN_RX_ERR_CNT_LEN) - 1) << CAN_RX_ERR_CNT_POS) -#define CAN_RX_ERR_CNT_UMSK (~(((1U << CAN_RX_ERR_CNT_LEN) - 1) << CAN_RX_ERR_CNT_POS)) - -/* 0x3c : op mode:r reset mode:rw */ -#define CAN_TX_ERR_COUNT_OFFSET (0x3c) -#define CAN_TX_ERR_CNT CAN_TX_ERR_CNT -#define CAN_TX_ERR_CNT_POS (0U) -#define CAN_TX_ERR_CNT_LEN (8U) -#define CAN_TX_ERR_CNT_MSK (((1U << CAN_TX_ERR_CNT_LEN) - 1) << CAN_TX_ERR_CNT_POS) -#define CAN_TX_ERR_CNT_UMSK (~(((1U << CAN_TX_ERR_CNT_LEN) - 1) << CAN_TX_ERR_CNT_POS)) - -/* 0x40 : op mode: w -> tx_frm_info - r -> rx_frm_info -reset mode:rw -> acceptance_code0 */ -#define CAN_TXRX_FRM_INFO_OR_ACCEPTANCE_CODE0_OFFSET (0x40) -#define CAN_TXRX_FRM_INFO_OR_ACCEPTANCE_CODE0 CAN_TXRX_FRM_INFO_OR_ACCEPTANCE_CODE0 -#define CAN_TXRX_FRM_INFO_OR_ACCEPTANCE_CODE0_POS (0U) -#define CAN_TXRX_FRM_INFO_OR_ACCEPTANCE_CODE0_LEN (8U) -#define CAN_TXRX_FRM_INFO_OR_ACCEPTANCE_CODE0_MSK (((1U << CAN_TXRX_FRM_INFO_OR_ACCEPTANCE_CODE0_LEN) - 1) << CAN_TXRX_FRM_INFO_OR_ACCEPTANCE_CODE0_POS) -#define CAN_TXRX_FRM_INFO_OR_ACCEPTANCE_CODE0_UMSK (~(((1U << CAN_TXRX_FRM_INFO_OR_ACCEPTANCE_CODE0_LEN) - 1) << CAN_TXRX_FRM_INFO_OR_ACCEPTANCE_CODE0_POS)) - -/* 0x44 : op mode:w -> tx_id1 - r -> rx_id1 -reset mode:rw -> acceptance_code1 */ -#define CAN_TXRX_ID1_OR_ACCEPTANCE_CODE1_OFFSET (0x44) -#define CAN_TXRX_ID1_OR_ACCEPTANCE_CODE1 CAN_TXRX_ID1_OR_ACCEPTANCE_CODE1 -#define CAN_TXRX_ID1_OR_ACCEPTANCE_CODE1_POS (0U) -#define CAN_TXRX_ID1_OR_ACCEPTANCE_CODE1_LEN (8U) -#define CAN_TXRX_ID1_OR_ACCEPTANCE_CODE1_MSK (((1U << CAN_TXRX_ID1_OR_ACCEPTANCE_CODE1_LEN) - 1) << CAN_TXRX_ID1_OR_ACCEPTANCE_CODE1_POS) -#define CAN_TXRX_ID1_OR_ACCEPTANCE_CODE1_UMSK (~(((1U << CAN_TXRX_ID1_OR_ACCEPTANCE_CODE1_LEN) - 1) << CAN_TXRX_ID1_OR_ACCEPTANCE_CODE1_POS)) - -/* 0x48 : op mode:w -> tx_id2 - r -> rx_id2 - reset mode:rw -> acceptance_code2 */ -#define CAN_TXRX_ID2_OR_ACCEPTANCE_CODE2_OFFSET (0x48) -#define CAN_TXRX_ID2_OR_ACCEPTANCE_CODE2 CAN_TXRX_ID2_OR_ACCEPTANCE_CODE2 -#define CAN_TXRX_ID2_OR_ACCEPTANCE_CODE2_POS (0U) -#define CAN_TXRX_ID2_OR_ACCEPTANCE_CODE2_LEN (8U) -#define CAN_TXRX_ID2_OR_ACCEPTANCE_CODE2_MSK (((1U << CAN_TXRX_ID2_OR_ACCEPTANCE_CODE2_LEN) - 1) << CAN_TXRX_ID2_OR_ACCEPTANCE_CODE2_POS) -#define CAN_TXRX_ID2_OR_ACCEPTANCE_CODE2_UMSK (~(((1U << CAN_TXRX_ID2_OR_ACCEPTANCE_CODE2_LEN) - 1) << CAN_TXRX_ID2_OR_ACCEPTANCE_CODE2_POS)) - -/* 0x74 : op mode:r reset mode:r */ -#define CAN_RX_MESSAGE_COUNT_OFFSET (0x74) -#define CAN_RX_MESSAGE_CNT CAN_RX_MESSAGE_CNT -#define CAN_RX_MESSAGE_CNT_POS (0U) -#define CAN_RX_MESSAGE_CNT_LEN (5U) -#define CAN_RX_MESSAGE_CNT_MSK (((1U << CAN_RX_MESSAGE_CNT_LEN) - 1) << CAN_RX_MESSAGE_CNT_POS) -#define CAN_RX_MESSAGE_CNT_UMSK (~(((1U << CAN_RX_MESSAGE_CNT_LEN) - 1) << CAN_RX_MESSAGE_CNT_POS)) - -/* 0x7c : op mode:rw reset mode:rw can_mode and cbp can be write in reset mode only */ -#define CAN_CLOCK_DIVIDER_OFFSET (0x7c) -#define CAN_CD CAN_CD -#define CAN_CD_POS (0U) -#define CAN_CD_LEN (3U) -#define CAN_CD_MSK (((1U << CAN_CD_LEN) - 1) << CAN_CD_POS) -#define CAN_CD_UMSK (~(((1U << CAN_CD_LEN) - 1) << CAN_CD_POS)) -#define CAN_CLOCKOFF CAN_CLOCKOFF -#define CAN_CLOCKOFF_POS (3U) -#define CAN_CLOCKOFF_LEN (1U) -#define CAN_CLOCKOFF_MSK (((1U << CAN_CLOCKOFF_LEN) - 1) << CAN_CLOCKOFF_POS) -#define CAN_CLOCKOFF_UMSK (~(((1U << CAN_CLOCKOFF_LEN) - 1) << CAN_CLOCKOFF_POS)) -#define CAN_READONLY CAN_READONLY -#define CAN_READONLY_POS (4U) -#define CAN_READONLY_LEN (1U) -#define CAN_READONLY_MSK (((1U << CAN_READONLY_LEN) - 1) << CAN_READONLY_POS) -#define CAN_READONLY_UMSK (~(((1U << CAN_READONLY_LEN) - 1) << CAN_READONLY_POS)) -#define CAN_RXINTEN CAN_RXINTEN -#define CAN_RXINTEN_POS (5U) -#define CAN_RXINTEN_LEN (1U) -#define CAN_RXINTEN_MSK (((1U << CAN_RXINTEN_LEN) - 1) << CAN_RXINTEN_POS) -#define CAN_RXINTEN_UMSK (~(((1U << CAN_RXINTEN_LEN) - 1) << CAN_RXINTEN_POS)) -#define CAN_CBP CAN_CBP -#define CAN_CBP_POS (6U) -#define CAN_CBP_LEN (1U) -#define CAN_CBP_MSK (((1U << CAN_CBP_LEN) - 1) << CAN_CBP_POS) -#define CAN_CBP_UMSK (~(((1U << CAN_CBP_LEN) - 1) << CAN_CBP_POS)) -#define CAN_MODE CAN_MODE -#define CAN_MODE_POS (7U) -#define CAN_MODE_LEN (1U) -#define CAN_MODE_MSK (((1U << CAN_MODE_LEN) - 1) << CAN_MODE_POS) -#define CAN_MODE_UMSK (~(((1U << CAN_MODE_LEN) - 1) << CAN_MODE_POS)) - -/* 0x40 : Frame information */ -#define CAN_INFORMATION_OFFSET (0x40) -#define CAN_INF_DLC CAN_INF_DLC -#define CAN_INF_DLC_POS (0U) -#define CAN_INF_DLC_LEN (4U) -#define CAN_INF_DLC_MSK (((1U << CAN_INF_DLC_LEN) - 1) << CAN_INF_DLC_POS) -#define CAN_INF_DLC_UMSK (~(((1U << CAN_INF_DLC_LEN) - 1) << CAN_INF_DLC_POS)) -#define CAN_INF_RTR CAN_INF_RTR -#define CAN_INF_RTR_POS (6U) -#define CAN_INF_RTR_LEN (1U) -#define CAN_INF_RTR_MSK (((1U << CAN_INF_RTR_LEN) - 1) << CAN_INF_RTR_POS) -#define CAN_INF_RTR_UMSK (~(((1U << CAN_INF_RTR_LEN) - 1) << CAN_INF_RTR_POS)) -#define CAN_INF_FF CAN_INF_FF -#define CAN_INF_FF_POS (7U) -#define CAN_INF_FF_LEN (1U) -#define CAN_INF_FF_MSK (((1U << CAN_INF_FF_LEN) - 1) << CAN_INF_FF_POS) -#define CAN_INF_FF_UMSK (~(((1U << CAN_INF_FF_LEN) - 1) << CAN_INF_FF_POS)) - -/* 0x44 : Identifier 1, ID28~21 */ -#define CAN_IDENTIFIER_1_OFFSET (0x44) - -/* 0x48 : Identifier 2, ID20~13, SFF Only use ID20~18 */ -#define CAN_IDENTIFIER_2_OFFSET (0x48) - -/* 0x4C : Identifier 3, ID12~5, only for EFF */ -#define CAN_IDENTIFIER_3_OFFSET (0x4C) - -/* 0x50 : Identifier 4, ID4~0, only for EFF */ -#define CAN_IDENTIFIER_4_OFFSET (0x50) - -/* 0x4C : Standard Format Data 1 buffer */ -#define CAN_SFF_DATA_1_OFFSET (0x4C) - -/* 0x50 : Standard Format Data 2 buffer */ -#define CAN_SFF_DATA_2_OFFSET (0x50) - -/* 0x54 : Standard Format Data 3 buffer */ -#define CAN_SFF_DATA_3_OFFSET (0x54) - -/* 0x58 : Standard Format Data 4 buffer */ -#define CAN_SFF_DATA_4_OFFSET (0x58) - -/* 0x5C : Standard Format Data 5 buffer */ -#define CAN_SFF_DATA_5_OFFSET (0x5C) - -/* 0x60 : Standard Format Data 6 buffer */ -#define CAN_SFF_DATA_6_OFFSET (0x60) - -/* 0x64 : Standard Format Data 7 buffer */ -#define CAN_SFF_DATA_7_OFFSET (0x64) - -/* 0x68 : Standard Format Data 8 buffer */ -#define CAN_SFF_DATA_8_OFFSET (0x68) - -/* 0x54 : Extended Format Data 1 buffer */ -#define CAN_EFF_DATA_1_OFFSET (0x54) - -/* 0x58 : Extended Format Data 2 buffer */ -#define CAN_EFF_DATA_2_OFFSET (0x58) - -/* 0x5C : Extended Format Data 3 buffer */ -#define CAN_EFF_DATA_3_OFFSET (0x5C) - -/* 0x60 : Extended Format Data 4 buffer */ -#define CAN_EFF_DATA_4_OFFSET (0x60) - -/* 0x64 : Extended Format Data 5 buffer */ -#define CAN_EFF_DATA_5_OFFSET (0x64) - -/* 0x68 : Extended Format Data 6 buffer */ -#define CAN_EFF_DATA_6_OFFSET (0x68) - -/* 0x6C : Extended Format Data 7 buffer */ -#define CAN_EFF_DATA_7_OFFSET (0x6C) - -/* 0x70 : Extended Format Data 8 buffer */ -#define CAN_EFF_DATA_8_OFFSET (0x70) - -/* 0x70 : Extended Format Data 8 buffer */ -#define CAN_EFF_DATA_8_OFFSET (0x70) - -/* 0x40 : Filter Acceptance 0 */ -#define CAN_FILTER_ACCEPTANCE_0_OFFSET (0x40) - -/* 0x44 : Filter Acceptance 1 */ -#define CAN_FILTER_ACCEPTANCE_1_OFFSET (0x44) - -/* 0x48 : Filter Acceptance 2 */ -#define CAN_FILTER_ACCEPTANCE_2_OFFSET (0x48) - -/* 0x4C : Filter Acceptance 3 */ -#define CAN_FILTER_ACCEPTANCE_3_OFFSET (0x4C) - -/* 0x50 : Filter Mask 0 */ -#define CAN_FILTER_Mask_0_OFFSET (0x50) - -/* 0x54 : Filter Mask 1 */ -#define CAN_FILTER_Mask_1_OFFSET (0x54) - -/* 0x58 : Filter Mask 2 */ -#define CAN_FILTER_Mask_2_OFFSET (0x58) - -/* 0x5C : Filter Mask 3 */ -#define CAN_FILTER_Mask_3_OFFSET (0x5C) - -/* 0x4C : Extended Format, Tx information 5, ID4~0 */ -#define CAN_IDENTIFIER_4_OFFSET (0x50) - -struct can_reg { - /* 0x0 : op mode:rw reset mode:rw */ - union { - struct { - uint32_t reset_request : 1; /* [ 0], w1c, 0x0 */ - uint32_t listen_only : 1; /* [ 1], w1c, 0x0 */ - uint32_t selt_test : 1; /* [ 2], w1c, 0x0 */ - uint32_t acceptance_filter : 1; /* [ 3], w1c, 0x0 */ - uint32_t rsvd_7_4 : 4; /* [ 7: 4], rsvd, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mode; - - /* 0x4 : op mode:w r -> 8'h00 -reset mode:w r -> 8'h00 */ - union { - struct { - uint32_t transmit_request : 1; /* [ 0], w1c, 0x0 */ - uint32_t abort_transmission : 1; /* [ 1], w1c, 0x0 */ - uint32_t release_receive_buffer : 1; /* [ 2], w1c, 0x0 */ - uint32_t clear_data_overrun : 1; /* [ 3], w1c, 0x0 */ - uint32_t self_request : 1; /* [ 4], w1c, 0x0 */ - uint32_t rsvd_7_5 : 3; /* [ 7: 5], rsvd, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } command; - - /* 0x8 : op mode:r reset mode:r */ - union { - struct { - uint32_t receive_buffer_sts : 1; /* [ 0], r, 0x0 */ - uint32_t data_overrun_sts : 1; /* [ 1], r, 0x0 */ - uint32_t transmit_buffer_sts : 1; /* [ 2], r, 0x0 */ - uint32_t transmit_complete_sts : 1; /* [ 3], r, 0x0 */ - uint32_t receive_sts : 1; /* [ 4], r, 0x0 */ - uint32_t transmit_sts : 1; /* [ 5], r, 0x0 */ - uint32_t error_sts : 1; /* [ 6], r, 0x0 */ - uint32_t bus_sts : 1; /* [ 7], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } status; - - /* 0xc : op mode:r reset mode:r when be read,all bits are reseted and can_int disappear */ - union { - struct { - uint32_t receive_int : 1; /* [ 0], r, 0x0 */ - uint32_t transmit_int : 1; /* [ 1], r, 0x0 */ - uint32_t error_int : 1; /* [ 2], r, 0x0 */ - uint32_t data_overrun_int : 1; /* [ 3], r, 0x0 */ - uint32_t rsvd_4 : 1; /* [ 4], rsvd, 0x0 */ - uint32_t error_passive_int : 1; /* [ 5], r, 0x0 */ - uint32_t arb_lost_int : 1; /* [ 6], r, 0x0 */ - uint32_t bus_error_int : 1; /* [ 7], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } interrupt; - - /* 0x10 : op mode:rw reset mode:rw when be read,all bits are reseted and can_int disappear */ - union { - struct { - uint32_t receive_int_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t transmit_int_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t error_int_en : 1; /* [ 2], r/w, 0x0 */ - uint32_t data_overrun_int_en : 1; /* [ 3], r/w, 0x0 */ - uint32_t rsvd_4 : 1; /* [ 4], rsvd, 0x0 */ - uint32_t error_passive_int_en : 1; /* [ 5], r/w, 0x0 */ - uint32_t arb_lost_int_en : 1; /* [ 6], r/w, 0x0 */ - uint32_t bus_error_int_en : 1; /* [ 7], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } interrupt_enable; - - /* 0x14 reserved */ - uint8_t RESERVED0x14[4]; - - /* 0x18 : op mode:r reset mode:rw */ - union { - struct { - uint32_t baud_rate_prescaler_0 : 1; /* [ 0], r/w, 0x0 */ - uint32_t baud_rate_prescaler_1 : 1; /* [ 1], r/w, 0x0 */ - uint32_t baud_rate_prescaler_2 : 1; /* [ 2], r/w, 0x0 */ - uint32_t baud_rate_prescaler_3 : 1; /* [ 3], r/w, 0x0 */ - uint32_t baud_rate_prescaler_4 : 1; /* [ 4], r/w, 0x0 */ - uint32_t baud_rate_prescaler_5 : 1; /* [ 5], r/w, 0x0 */ - uint32_t sync_jump_width_0 : 1; /* [ 6], r/w, 0x0 */ - uint32_t sync_jump_width_1 : 1; /* [ 7], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } bus_timing_0; - - /* 0x1c : op mode:r reset mode:rw */ - union { - struct { - uint32_t time_segment_1_0 : 1; /* [ 0], r/w, 0x0 */ - uint32_t time_segment_1_1 : 1; /* [ 1], r/w, 0x0 */ - uint32_t time_segment_1_2 : 1; /* [ 2], r/w, 0x0 */ - uint32_t time_segment_1_3 : 1; /* [ 3], r/w, 0x0 */ - uint32_t time_segment_2_0 : 1; /* [ 4], r/w, 0x0 */ - uint32_t time_segment_2_1 : 1; /* [ 5], r/w, 0x0 */ - uint32_t time_segment_2_2 : 1; /* [ 6], r/w, 0x0 */ - uint32_t sampling : 1; /* [ 7], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } bus_timing_1; - - /* 0x20 reserved */ - uint8_t RESERVED0x20[12]; - - /* 0x2c : op mode:r reset mode:r */ - union { - struct { - uint32_t ALC4_0 : 5; /* [ 4: 0], r, 0x0 */ - uint32_t rsvd_7_5 : 3; /* [ 7: 5], rsvd, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } arb_lost_capture; - - /* 0x30 : op mode:r reset mode:r */ - union { - struct { - uint32_t segment4_0 : 5; /* [ 4: 0], r, 0x0 */ - uint32_t dir : 1; /* [ 5], r, 0x0 */ - uint32_t err_code : 2; /* [ 7: 6], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } error_code_capture; - - /* 0x34 : op mode:r reset mode:rw */ - union { - struct { - uint32_t err_warning_limit : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } error_warning_limit; - - /* 0x38 : op mode:r reset mode:rw */ - union { - struct { - uint32_t rx_err_cnt : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } rx_err_count; - - /* 0x3c : op mode:r reset mode:rw */ - union { - struct { - uint32_t tx_err_cnt : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } tx_err_count; - - /* 0x40 : op mode: w -> tx_frm_info - r -> rx_frm_info -reset mode:rw -> acceptance_code0 */ - union { - struct { - uint32_t txrx_frm_info_or_acceptance_code0 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_frm_info_or_acceptance_code0; - - /* 0x44 : op mode:w -> tx_id1 - r -> rx_id1 -reset mode:rw -> acceptance_code1 */ - union { - struct { - uint32_t txrx_id1_or_acceptance_code1 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_id1_or_acceptance_code1; - - /* 0x48 : op mode:w -> tx_id2 - r -> rx_id2 - reset mode:rw -> acceptance_code2 */ - union { - struct { - uint32_t txrx_id2_or_acceptance_code2 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_id2_or_acceptance_code2; - - /* 0x4c : op mode:w -> tx_data1_s or tx_id3 - r -> rx_data1_s or rx_id3 - reset mode:rw -> acceptance_code3 */ - union { - struct { - uint32_t txrx_data1_s_or_txrx_id3_e_or_acceptance_code3 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_data1_s_or_txrx_id3_e_or_acceptance_code3; - - /* 0x50 : op mode:w -> tx_data2_s or tx_id4 - r -> rx_data2_s or rx_id4 -reset mode:rw -> acceptance_mask0 */ - union { - struct { - uint32_t txrx_data2_s_or_txrx_id4_e_or_acceptance_mask0 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_data2_s_or_txrx_id4_e_or_acceptance_mask0; - - /* 0x54 : op mode:w -> tx_data3_s or tx_data1_e - r -> rx_data3_s or rx_data1_e -reset mode:rw -> acceptance_mask1 */ - union { - struct { - uint32_t txrx_data3_s_or_txrx_data1_e_or_acceptance_mask1 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_data3_s_or_txrx_data1_e_or_acceptance_mask1; - - /* 0x58 : op mode:w -> tx_data4_s or tx_data2_e - r -> rx_data4_s or rx_data2_e -reset mode:rw -> acceptance_mask2 */ - union { - struct { - uint32_t txrx_data4_s_or_txrx_data2_e_or_acceptance_mask2 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_data4_s_or_txrx_data2_e_or_acceptance_mask2; - - /* 0x5c : op mode:w -> tx_data5_s or tx_data3_e - r -> rx_data5_s or rx_data3_e -reset mode:rw -> acceptance_mask3 */ - union { - struct { - uint32_t txrx_data5_s_or_txrx_data3_e_or_acceptance_mask3 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_data5_s_or_txrx_data3_e_or_acceptance_mask3; - - /* 0x60 : op mode:w -> tx_data6_s or tx_data4_e - r -> rx_data6_s or rx_data4_e -reset mode:r -> 8'H00 */ - union { - struct { - uint32_t txrx_data6_s_or_txrx_data4_e : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_data6_s_or_txrx_data4_e; - - /* 0x64 : op mode:w -> tx_data7_s or tx_data5_e - r -> rx_data7_s or rx_data5_e -reset mode:r -> 8'H00 */ - union { - struct { - uint32_t txrx_data7_s_or_txrx_data5_e : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_data7_s_or_txrx_data5_e; - - /* 0x68 : op mode:w -> tx_data8_s or tx_data6_e - r -> rx_data8_s or rx_data6_e -reset mode:r -> 8'H00 */ - union { - struct { - uint32_t txrx_data8_s_or_txrx_data6_e : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_data8_s_or_txrx_data6_e; - - /* 0x6c : op mode:w -> tx_data7_e - r -> rx_data7_e -reset mode:r -> 8'H00 */ - union { - struct { - uint32_t txrx_data7_e : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_data7_e; - - /* 0x70 : op mode:w -> tx_data8_e - r -> rx_data8_e -reset mode:r -> 8'H00 */ - union { - struct { - uint32_t txrx_data8_e : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_data8_e; - - /* 0x74 : op mode:r reset mode:r */ - union { - struct { - uint32_t rx_message_cnt : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } rx_message_count; - - /* 0x78 reserved */ - uint8_t RESERVED0x78[4]; - - /* 0x7c : op mode:rw reset mode:rw can_mode and cbp can be write in reset mode only */ - union { - struct { - uint32_t cd : 3; /* [ 2: 0], r/w, 0x0 */ - uint32_t clockoff : 1; /* [ 3], r/w, 0x0 */ - uint32_t readonly : 1; /* [ 4], r, 0x0 */ - uint32_t rxinten : 1; /* [ 5], r/w, 0x0 */ - uint32_t cbp : 1; /* [ 6], r/w, 0x0 */ - uint32_t can_mode : 1; /* [ 7], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } clock_divider; -}; - -typedef volatile struct can_reg can_reg_t; - -#endif /* __CAN_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/cnn_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/cnn_reg.h deleted file mode 100644 index 1f4c662611..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/cnn_reg.h +++ /dev/null @@ -1,241 +0,0 @@ -/** - ****************************************************************************** - * @file cnn_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __CNN_REG_H__ -#define __CNN_REG_H__ - -#include "bl808.h" - -/* 0x00 : bl_cnn_cfg */ -#define CNN_BL_CNN_CFG_OFFSET (0x00) -#define CNN_REG_INT_CLR CNN_REG_INT_CLR -#define CNN_REG_INT_CLR_POS (24U) -#define CNN_REG_INT_CLR_LEN (1U) -#define CNN_REG_INT_CLR_MSK (((1U << CNN_REG_INT_CLR_LEN) - 1) << CNN_REG_INT_CLR_POS) -#define CNN_REG_INT_CLR_UMSK (~(((1U << CNN_REG_INT_CLR_LEN) - 1) << CNN_REG_INT_CLR_POS)) -#define CNN_INT CNN_INT -#define CNN_INT_POS (25U) -#define CNN_INT_LEN (1U) -#define CNN_INT_MSK (((1U << CNN_INT_LEN) - 1) << CNN_INT_POS) -#define CNN_INT_UMSK (~(((1U << CNN_INT_LEN) - 1) << CNN_INT_POS)) -#define CNN_REG_BUS_RST CNN_REG_BUS_RST -#define CNN_REG_BUS_RST_POS (27U) -#define CNN_REG_BUS_RST_LEN (1U) -#define CNN_REG_BUS_RST_MSK (((1U << CNN_REG_BUS_RST_LEN) - 1) << CNN_REG_BUS_RST_POS) -#define CNN_REG_BUS_RST_UMSK (~(((1U << CNN_REG_BUS_RST_LEN) - 1) << CNN_REG_BUS_RST_POS)) -#define CNN_AXI_IDLE CNN_AXI_IDLE -#define CNN_AXI_IDLE_POS (31U) -#define CNN_AXI_IDLE_LEN (1U) -#define CNN_AXI_IDLE_MSK (((1U << CNN_AXI_IDLE_LEN) - 1) << CNN_AXI_IDLE_POS) -#define CNN_AXI_IDLE_UMSK (~(((1U << CNN_AXI_IDLE_LEN) - 1) << CNN_AXI_IDLE_POS)) - -/* 0x04 : bl_cnn_weig_addr */ -#define CNN_BL_CNN_WEIG_ADDR_OFFSET (0x04) -#define CNN_WEIG_ADDR_BASE CNN_WEIG_ADDR_BASE -#define CNN_WEIG_ADDR_BASE_POS (0U) -#define CNN_WEIG_ADDR_BASE_LEN (32U) -#define CNN_WEIG_ADDR_BASE_MSK (((1U << CNN_WEIG_ADDR_BASE_LEN) - 1) << CNN_WEIG_ADDR_BASE_POS) -#define CNN_WEIG_ADDR_BASE_UMSK (~(((1U << CNN_WEIG_ADDR_BASE_LEN) - 1) << CNN_WEIG_ADDR_BASE_POS)) - -/* 0x08 : bl_cnn_img_addr */ -#define CNN_BL_CNN_IMG_ADDR_OFFSET (0x08) -#define CNN_IMG_ADDR_BASE CNN_IMG_ADDR_BASE -#define CNN_IMG_ADDR_BASE_POS (0U) -#define CNN_IMG_ADDR_BASE_LEN (32U) -#define CNN_IMG_ADDR_BASE_MSK (((1U << CNN_IMG_ADDR_BASE_LEN) - 1) << CNN_IMG_ADDR_BASE_POS) -#define CNN_IMG_ADDR_BASE_UMSK (~(((1U << CNN_IMG_ADDR_BASE_LEN) - 1) << CNN_IMG_ADDR_BASE_POS)) - -/* 0x0C : bl_cnn_bias_addr */ -#define CNN_BL_CNN_BIAS_ADDR_OFFSET (0x0C) -#define CNN_BIAS_ADDR_BASE CNN_BIAS_ADDR_BASE -#define CNN_BIAS_ADDR_BASE_POS (0U) -#define CNN_BIAS_ADDR_BASE_LEN (32U) -#define CNN_BIAS_ADDR_BASE_MSK (((1U << CNN_BIAS_ADDR_BASE_LEN) - 1) << CNN_BIAS_ADDR_BASE_POS) -#define CNN_BIAS_ADDR_BASE_UMSK (~(((1U << CNN_BIAS_ADDR_BASE_LEN) - 1) << CNN_BIAS_ADDR_BASE_POS)) - -/* 0x10 : bl_cnn_inst_addr */ -#define CNN_BL_CNN_INST_ADDR_OFFSET (0x10) -#define CNN_INST_ADDR_BASE CNN_INST_ADDR_BASE -#define CNN_INST_ADDR_BASE_POS (0U) -#define CNN_INST_ADDR_BASE_LEN (32U) -#define CNN_INST_ADDR_BASE_MSK (((1U << CNN_INST_ADDR_BASE_LEN) - 1) << CNN_INST_ADDR_BASE_POS) -#define CNN_INST_ADDR_BASE_UMSK (~(((1U << CNN_INST_ADDR_BASE_LEN) - 1) << CNN_INST_ADDR_BASE_POS)) - -/* 0x14 : bl_cnn_out_addr */ -#define CNN_BL_CNN_OUT_ADDR_OFFSET (0x14) -#define CNN_OUT_ADDR_BASE CNN_OUT_ADDR_BASE -#define CNN_OUT_ADDR_BASE_POS (0U) -#define CNN_OUT_ADDR_BASE_LEN (32U) -#define CNN_OUT_ADDR_BASE_MSK (((1U << CNN_OUT_ADDR_BASE_LEN) - 1) << CNN_OUT_ADDR_BASE_POS) -#define CNN_OUT_ADDR_BASE_UMSK (~(((1U << CNN_OUT_ADDR_BASE_LEN) - 1) << CNN_OUT_ADDR_BASE_POS)) - -/* 0x18 : bl_cnn_num1 */ -#define CNN_BL_CNN_NUM1_OFFSET (0x18) -#define CNN_WEIG_NUM CNN_WEIG_NUM -#define CNN_WEIG_NUM_POS (0U) -#define CNN_WEIG_NUM_LEN (16U) -#define CNN_WEIG_NUM_MSK (((1U << CNN_WEIG_NUM_LEN) - 1) << CNN_WEIG_NUM_POS) -#define CNN_WEIG_NUM_UMSK (~(((1U << CNN_WEIG_NUM_LEN) - 1) << CNN_WEIG_NUM_POS)) -#define CNN_IMG_NUM CNN_IMG_NUM -#define CNN_IMG_NUM_POS (16U) -#define CNN_IMG_NUM_LEN (16U) -#define CNN_IMG_NUM_MSK (((1U << CNN_IMG_NUM_LEN) - 1) << CNN_IMG_NUM_POS) -#define CNN_IMG_NUM_UMSK (~(((1U << CNN_IMG_NUM_LEN) - 1) << CNN_IMG_NUM_POS)) - -/* 0x1C : bl_cnn_num2 */ -#define CNN_BL_CNN_NUM2_OFFSET (0x1C) -#define CNN_BIAS_NUM CNN_BIAS_NUM -#define CNN_BIAS_NUM_POS (0U) -#define CNN_BIAS_NUM_LEN (16U) -#define CNN_BIAS_NUM_MSK (((1U << CNN_BIAS_NUM_LEN) - 1) << CNN_BIAS_NUM_POS) -#define CNN_BIAS_NUM_UMSK (~(((1U << CNN_BIAS_NUM_LEN) - 1) << CNN_BIAS_NUM_POS)) -#define CNN_OUT_NUM CNN_OUT_NUM -#define CNN_OUT_NUM_POS (16U) -#define CNN_OUT_NUM_LEN (16U) -#define CNN_OUT_NUM_MSK (((1U << CNN_OUT_NUM_LEN) - 1) << CNN_OUT_NUM_POS) -#define CNN_OUT_NUM_UMSK (~(((1U << CNN_OUT_NUM_LEN) - 1) << CNN_OUT_NUM_POS)) - -/* 0x20 : bl_cnn_num3 */ -#define CNN_BL_CNN_NUM3_OFFSET (0x20) -#define CNN_INST_NUM CNN_INST_NUM -#define CNN_INST_NUM_POS (0U) -#define CNN_INST_NUM_LEN (16U) -#define CNN_INST_NUM_MSK (((1U << CNN_INST_NUM_LEN) - 1) << CNN_INST_NUM_POS) -#define CNN_INST_NUM_UMSK (~(((1U << CNN_INST_NUM_LEN) - 1) << CNN_INST_NUM_POS)) -#define CNN_START CNN_START -#define CNN_START_POS (16U) -#define CNN_START_LEN (1U) -#define CNN_START_MSK (((1U << CNN_START_LEN) - 1) << CNN_START_POS) -#define CNN_START_UMSK (~(((1U << CNN_START_LEN) - 1) << CNN_START_POS)) -#define CNN_RST CNN_RST -#define CNN_RST_POS (17U) -#define CNN_RST_LEN (1U) -#define CNN_RST_MSK (((1U << CNN_RST_LEN) - 1) << CNN_RST_POS) -#define CNN_RST_UMSK (~(((1U << CNN_RST_LEN) - 1) << CNN_RST_POS)) -#define CNN_INPUT_CHANNEL CNN_INPUT_CHANNEL -#define CNN_INPUT_CHANNEL_POS (18U) -#define CNN_INPUT_CHANNEL_LEN (2U) -#define CNN_INPUT_CHANNEL_MSK (((1U << CNN_INPUT_CHANNEL_LEN) - 1) << CNN_INPUT_CHANNEL_POS) -#define CNN_INPUT_CHANNEL_UMSK (~(((1U << CNN_INPUT_CHANNEL_LEN) - 1) << CNN_INPUT_CHANNEL_POS)) - -struct cnn_reg { - /* 0x00 : bl_cnn_cfg */ - union { - struct { - uint32_t reserved_0_23 : 24; /* [23: 0], rsvd, 0x0 */ - uint32_t reg_int_clr : 1; /* [ 24], w1p, 0x0 */ - uint32_t cnn_int : 1; /* [ 25], r, 0x0 */ - uint32_t reserved_26 : 1; /* [ 26], rsvd, 0x0 */ - uint32_t reg_bus_rst : 1; /* [ 27], w1p, 0x0 */ - uint32_t reserved_28_30 : 3; /* [30:28], rsvd, 0x0 */ - uint32_t axi_idle : 1; /* [ 31], r, 0x0 */ - } BF; - uint32_t WORD; - } bl_cnn_cfg; - - /* 0x04 : bl_cnn_weig_addr */ - union { - struct { - uint32_t WEIG_addr_base : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } bl_cnn_weig_addr; - - /* 0x08 : bl_cnn_img_addr */ - union { - struct { - uint32_t IMG_addr_base : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } bl_cnn_img_addr; - - /* 0x0C : bl_cnn_bias_addr */ - union { - struct { - uint32_t BIAS_addr_base : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } bl_cnn_bias_addr; - - /* 0x10 : bl_cnn_inst_addr */ - union { - struct { - uint32_t INST_addr_base : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } bl_cnn_inst_addr; - - /* 0x14 : bl_cnn_out_addr */ - union { - struct { - uint32_t OUT_addr_base : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } bl_cnn_out_addr; - - /* 0x18 : bl_cnn_num1 */ - union { - struct { - uint32_t WEIG_num : 16; /* [15: 0], r/w, 0x0 */ - uint32_t IMG_num : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } bl_cnn_num1; - - /* 0x1C : bl_cnn_num2 */ - union { - struct { - uint32_t BIAS_num : 16; /* [15: 0], r/w, 0x0 */ - uint32_t OUT_num : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } bl_cnn_num2; - - /* 0x20 : bl_cnn_num3 */ - union { - struct { - uint32_t INST_num : 16; /* [15: 0], r/w, 0x0 */ - uint32_t CNN_start : 1; /* [ 16], r/w, 0x0 */ - uint32_t CNN_rst : 1; /* [ 17], r/w, 0x0 */ - uint32_t input_channel : 2; /* [19:18], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } bl_cnn_num3; -}; - -typedef volatile struct cnn_reg cnn_reg_t; - -#endif /* __CNN_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/csi_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/csi_reg.h deleted file mode 100644 index 52df1ae765..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/csi_reg.h +++ /dev/null @@ -1,528 +0,0 @@ -/** - ****************************************************************************** - * @file csi_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __CSI_REG_H__ -#define __CSI_REG_H__ - -#include "bl808.h" - -/* 0x0 : mipi_config */ -#define CSI_MIPI_CONFIG_OFFSET (0x0) -#define CSI_CR_CSI_EN CSI_CR_CSI_EN -#define CSI_CR_CSI_EN_POS (0U) -#define CSI_CR_CSI_EN_LEN (1U) -#define CSI_CR_CSI_EN_MSK (((1U << CSI_CR_CSI_EN_LEN) - 1) << CSI_CR_CSI_EN_POS) -#define CSI_CR_CSI_EN_UMSK (~(((1U << CSI_CR_CSI_EN_LEN) - 1) << CSI_CR_CSI_EN_POS)) -#define CSI_CR_LANE_NUM CSI_CR_LANE_NUM -#define CSI_CR_LANE_NUM_POS (1U) -#define CSI_CR_LANE_NUM_LEN (1U) -#define CSI_CR_LANE_NUM_MSK (((1U << CSI_CR_LANE_NUM_LEN) - 1) << CSI_CR_LANE_NUM_POS) -#define CSI_CR_LANE_NUM_UMSK (~(((1U << CSI_CR_LANE_NUM_LEN) - 1) << CSI_CR_LANE_NUM_POS)) -#define CSI_CR_LANE_INV CSI_CR_LANE_INV -#define CSI_CR_LANE_INV_POS (3U) -#define CSI_CR_LANE_INV_LEN (1U) -#define CSI_CR_LANE_INV_MSK (((1U << CSI_CR_LANE_INV_LEN) - 1) << CSI_CR_LANE_INV_POS) -#define CSI_CR_LANE_INV_UMSK (~(((1U << CSI_CR_LANE_INV_LEN) - 1) << CSI_CR_LANE_INV_POS)) -#define CSI_CR_DATA_BIT_INV CSI_CR_DATA_BIT_INV -#define CSI_CR_DATA_BIT_INV_POS (4U) -#define CSI_CR_DATA_BIT_INV_LEN (1U) -#define CSI_CR_DATA_BIT_INV_MSK (((1U << CSI_CR_DATA_BIT_INV_LEN) - 1) << CSI_CR_DATA_BIT_INV_POS) -#define CSI_CR_DATA_BIT_INV_UMSK (~(((1U << CSI_CR_DATA_BIT_INV_LEN) - 1) << CSI_CR_DATA_BIT_INV_POS)) -#define CSI_CR_SYNC_SP_EN CSI_CR_SYNC_SP_EN -#define CSI_CR_SYNC_SP_EN_POS (5U) -#define CSI_CR_SYNC_SP_EN_LEN (1U) -#define CSI_CR_SYNC_SP_EN_MSK (((1U << CSI_CR_SYNC_SP_EN_LEN) - 1) << CSI_CR_SYNC_SP_EN_POS) -#define CSI_CR_SYNC_SP_EN_UMSK (~(((1U << CSI_CR_SYNC_SP_EN_LEN) - 1) << CSI_CR_SYNC_SP_EN_POS)) -#define CSI_CR_UNPACK_EN CSI_CR_UNPACK_EN -#define CSI_CR_UNPACK_EN_POS (6U) -#define CSI_CR_UNPACK_EN_LEN (1U) -#define CSI_CR_UNPACK_EN_MSK (((1U << CSI_CR_UNPACK_EN_LEN) - 1) << CSI_CR_UNPACK_EN_POS) -#define CSI_CR_UNPACK_EN_UMSK (~(((1U << CSI_CR_UNPACK_EN_LEN) - 1) << CSI_CR_UNPACK_EN_POS)) -#define CSI_CR_VC_DVP0 CSI_CR_VC_DVP0 -#define CSI_CR_VC_DVP0_POS (12U) -#define CSI_CR_VC_DVP0_LEN (2U) -#define CSI_CR_VC_DVP0_MSK (((1U << CSI_CR_VC_DVP0_LEN) - 1) << CSI_CR_VC_DVP0_POS) -#define CSI_CR_VC_DVP0_UMSK (~(((1U << CSI_CR_VC_DVP0_LEN) - 1) << CSI_CR_VC_DVP0_POS)) -#define CSI_CR_VC_DVP1 CSI_CR_VC_DVP1 -#define CSI_CR_VC_DVP1_POS (14U) -#define CSI_CR_VC_DVP1_LEN (2U) -#define CSI_CR_VC_DVP1_MSK (((1U << CSI_CR_VC_DVP1_LEN) - 1) << CSI_CR_VC_DVP1_POS) -#define CSI_CR_VC_DVP1_UMSK (~(((1U << CSI_CR_VC_DVP1_LEN) - 1) << CSI_CR_VC_DVP1_POS)) - -/* 0x10 : csi_int_status */ -#define CSI_INT_STATUS_OFFSET (0x10) -#define CSI_INT_STATUS CSI_INT_STATUS -#define CSI_INT_STATUS_POS (0U) -#define CSI_INT_STATUS_LEN (6U) -#define CSI_INT_STATUS_MSK (((1U << CSI_INT_STATUS_LEN) - 1) << CSI_INT_STATUS_POS) -#define CSI_INT_STATUS_UMSK (~(((1U << CSI_INT_STATUS_LEN) - 1) << CSI_INT_STATUS_POS)) - -/* 0x14 : csi_int_mask */ -#define CSI_INT_MASK_OFFSET (0x14) -#define CSI_INT_MASK CSI_INT_MASK -#define CSI_INT_MASK_POS (0U) -#define CSI_INT_MASK_LEN (6U) -#define CSI_INT_MASK_MSK (((1U << CSI_INT_MASK_LEN) - 1) << CSI_INT_MASK_POS) -#define CSI_INT_MASK_UMSK (~(((1U << CSI_INT_MASK_LEN) - 1) << CSI_INT_MASK_POS)) - -/* 0x18 : csi_int_clear */ -#define CSI_INT_CLEAR_OFFSET (0x18) -#define CSI_INT_CLEAR CSI_INT_CLEAR -#define CSI_INT_CLEAR_POS (0U) -#define CSI_INT_CLEAR_LEN (6U) -#define CSI_INT_CLEAR_MSK (((1U << CSI_INT_CLEAR_LEN) - 1) << CSI_INT_CLEAR_POS) -#define CSI_INT_CLEAR_UMSK (~(((1U << CSI_INT_CLEAR_LEN) - 1) << CSI_INT_CLEAR_POS)) - -/* 0x1C : csi_int_enable */ -#define CSI_INT_ENABLE_OFFSET (0x1C) -#define CSI_INT_ENABLE CSI_INT_ENABLE -#define CSI_INT_ENABLE_POS (0U) -#define CSI_INT_ENABLE_LEN (6U) -#define CSI_INT_ENABLE_MSK (((1U << CSI_INT_ENABLE_LEN) - 1) << CSI_INT_ENABLE_POS) -#define CSI_INT_ENABLE_UMSK (~(((1U << CSI_INT_ENABLE_LEN) - 1) << CSI_INT_ENABLE_POS)) - -/* 0x20 : gnr_buf_status */ -#define CSI_GNR_BUF_STATUS_OFFSET (0x20) -#define CSI_ST_GNR_FIFO_CNT CSI_ST_GNR_FIFO_CNT -#define CSI_ST_GNR_FIFO_CNT_POS (0U) -#define CSI_ST_GNR_FIFO_CNT_LEN (4U) -#define CSI_ST_GNR_FIFO_CNT_MSK (((1U << CSI_ST_GNR_FIFO_CNT_LEN) - 1) << CSI_ST_GNR_FIFO_CNT_POS) -#define CSI_ST_GNR_FIFO_CNT_UMSK (~(((1U << CSI_ST_GNR_FIFO_CNT_LEN) - 1) << CSI_ST_GNR_FIFO_CNT_POS)) - -/* 0x24 : gnr_buf_rdata */ -#define CSI_GNR_BUF_RDATA_OFFSET (0x24) -#define CSI_GNR_BUF_RDATA CSI_GNR_BUF_RDATA -#define CSI_GNR_BUF_RDATA_POS (0U) -#define CSI_GNR_BUF_RDATA_LEN (32U) -#define CSI_GNR_BUF_RDATA_MSK (((1U << CSI_GNR_BUF_RDATA_LEN) - 1) << CSI_GNR_BUF_RDATA_POS) -#define CSI_GNR_BUF_RDATA_UMSK (~(((1U << CSI_GNR_BUF_RDATA_LEN) - 1) << CSI_GNR_BUF_RDATA_POS)) - -/* 0x80 : dphy_config_0 */ -#define CSI_DPHY_CONFIG_0_OFFSET (0x80) -#define CSI_DL0_ENABLE CSI_DL0_ENABLE -#define CSI_DL0_ENABLE_POS (0U) -#define CSI_DL0_ENABLE_LEN (1U) -#define CSI_DL0_ENABLE_MSK (((1U << CSI_DL0_ENABLE_LEN) - 1) << CSI_DL0_ENABLE_POS) -#define CSI_DL0_ENABLE_UMSK (~(((1U << CSI_DL0_ENABLE_LEN) - 1) << CSI_DL0_ENABLE_POS)) -#define CSI_DL1_ENABLE CSI_DL1_ENABLE -#define CSI_DL1_ENABLE_POS (1U) -#define CSI_DL1_ENABLE_LEN (1U) -#define CSI_DL1_ENABLE_MSK (((1U << CSI_DL1_ENABLE_LEN) - 1) << CSI_DL1_ENABLE_POS) -#define CSI_DL1_ENABLE_UMSK (~(((1U << CSI_DL1_ENABLE_LEN) - 1) << CSI_DL1_ENABLE_POS)) -#define CSI_CL_ENABLE CSI_CL_ENABLE -#define CSI_CL_ENABLE_POS (2U) -#define CSI_CL_ENABLE_LEN (1U) -#define CSI_CL_ENABLE_MSK (((1U << CSI_CL_ENABLE_LEN) - 1) << CSI_CL_ENABLE_POS) -#define CSI_CL_ENABLE_UMSK (~(((1U << CSI_CL_ENABLE_LEN) - 1) << CSI_CL_ENABLE_POS)) -#define CSI_DL0_STOPSTATE CSI_DL0_STOPSTATE -#define CSI_DL0_STOPSTATE_POS (4U) -#define CSI_DL0_STOPSTATE_LEN (1U) -#define CSI_DL0_STOPSTATE_MSK (((1U << CSI_DL0_STOPSTATE_LEN) - 1) << CSI_DL0_STOPSTATE_POS) -#define CSI_DL0_STOPSTATE_UMSK (~(((1U << CSI_DL0_STOPSTATE_LEN) - 1) << CSI_DL0_STOPSTATE_POS)) -#define CSI_DL1_STOPSTATE CSI_DL1_STOPSTATE -#define CSI_DL1_STOPSTATE_POS (5U) -#define CSI_DL1_STOPSTATE_LEN (1U) -#define CSI_DL1_STOPSTATE_MSK (((1U << CSI_DL1_STOPSTATE_LEN) - 1) << CSI_DL1_STOPSTATE_POS) -#define CSI_DL1_STOPSTATE_UMSK (~(((1U << CSI_DL1_STOPSTATE_LEN) - 1) << CSI_DL1_STOPSTATE_POS)) -#define CSI_CL_STOPSTATE CSI_CL_STOPSTATE -#define CSI_CL_STOPSTATE_POS (6U) -#define CSI_CL_STOPSTATE_LEN (1U) -#define CSI_CL_STOPSTATE_MSK (((1U << CSI_CL_STOPSTATE_LEN) - 1) << CSI_CL_STOPSTATE_POS) -#define CSI_CL_STOPSTATE_UMSK (~(((1U << CSI_CL_STOPSTATE_LEN) - 1) << CSI_CL_STOPSTATE_POS)) -#define CSI_DL0_ULPSACTIVENOT CSI_DL0_ULPSACTIVENOT -#define CSI_DL0_ULPSACTIVENOT_POS (8U) -#define CSI_DL0_ULPSACTIVENOT_LEN (1U) -#define CSI_DL0_ULPSACTIVENOT_MSK (((1U << CSI_DL0_ULPSACTIVENOT_LEN) - 1) << CSI_DL0_ULPSACTIVENOT_POS) -#define CSI_DL0_ULPSACTIVENOT_UMSK (~(((1U << CSI_DL0_ULPSACTIVENOT_LEN) - 1) << CSI_DL0_ULPSACTIVENOT_POS)) -#define CSI_DL1_ULPSACTIVENOT CSI_DL1_ULPSACTIVENOT -#define CSI_DL1_ULPSACTIVENOT_POS (9U) -#define CSI_DL1_ULPSACTIVENOT_LEN (1U) -#define CSI_DL1_ULPSACTIVENOT_MSK (((1U << CSI_DL1_ULPSACTIVENOT_LEN) - 1) << CSI_DL1_ULPSACTIVENOT_POS) -#define CSI_DL1_ULPSACTIVENOT_UMSK (~(((1U << CSI_DL1_ULPSACTIVENOT_LEN) - 1) << CSI_DL1_ULPSACTIVENOT_POS)) -#define CSI_CL_ULPSACTIVENOT CSI_CL_ULPSACTIVENOT -#define CSI_CL_ULPSACTIVENOT_POS (10U) -#define CSI_CL_ULPSACTIVENOT_LEN (1U) -#define CSI_CL_ULPSACTIVENOT_MSK (((1U << CSI_CL_ULPSACTIVENOT_LEN) - 1) << CSI_CL_ULPSACTIVENOT_POS) -#define CSI_CL_ULPSACTIVENOT_UMSK (~(((1U << CSI_CL_ULPSACTIVENOT_LEN) - 1) << CSI_CL_ULPSACTIVENOT_POS)) -#define CSI_DL0_FORCERXMODE CSI_DL0_FORCERXMODE -#define CSI_DL0_FORCERXMODE_POS (12U) -#define CSI_DL0_FORCERXMODE_LEN (1U) -#define CSI_DL0_FORCERXMODE_MSK (((1U << CSI_DL0_FORCERXMODE_LEN) - 1) << CSI_DL0_FORCERXMODE_POS) -#define CSI_DL0_FORCERXMODE_UMSK (~(((1U << CSI_DL0_FORCERXMODE_LEN) - 1) << CSI_DL0_FORCERXMODE_POS)) -#define CSI_DL1_FORCERXMODE CSI_DL1_FORCERXMODE -#define CSI_DL1_FORCERXMODE_POS (13U) -#define CSI_DL1_FORCERXMODE_LEN (1U) -#define CSI_DL1_FORCERXMODE_MSK (((1U << CSI_DL1_FORCERXMODE_LEN) - 1) << CSI_DL1_FORCERXMODE_POS) -#define CSI_DL1_FORCERXMODE_UMSK (~(((1U << CSI_DL1_FORCERXMODE_LEN) - 1) << CSI_DL1_FORCERXMODE_POS)) -#define CSI_CL_RXCLKACTIVEHS CSI_CL_RXCLKACTIVEHS -#define CSI_CL_RXCLKACTIVEHS_POS (14U) -#define CSI_CL_RXCLKACTIVEHS_LEN (1U) -#define CSI_CL_RXCLKACTIVEHS_MSK (((1U << CSI_CL_RXCLKACTIVEHS_LEN) - 1) << CSI_CL_RXCLKACTIVEHS_POS) -#define CSI_CL_RXCLKACTIVEHS_UMSK (~(((1U << CSI_CL_RXCLKACTIVEHS_LEN) - 1) << CSI_CL_RXCLKACTIVEHS_POS)) -#define CSI_CL_RXULPSCLKNOT CSI_CL_RXULPSCLKNOT -#define CSI_CL_RXULPSCLKNOT_POS (15U) -#define CSI_CL_RXULPSCLKNOT_LEN (1U) -#define CSI_CL_RXULPSCLKNOT_MSK (((1U << CSI_CL_RXULPSCLKNOT_LEN) - 1) << CSI_CL_RXULPSCLKNOT_POS) -#define CSI_CL_RXULPSCLKNOT_UMSK (~(((1U << CSI_CL_RXULPSCLKNOT_LEN) - 1) << CSI_CL_RXULPSCLKNOT_POS)) -#define CSI_RESET_N CSI_RESET_N -#define CSI_RESET_N_POS (31U) -#define CSI_RESET_N_LEN (1U) -#define CSI_RESET_N_MSK (((1U << CSI_RESET_N_LEN) - 1) << CSI_RESET_N_POS) -#define CSI_RESET_N_UMSK (~(((1U << CSI_RESET_N_LEN) - 1) << CSI_RESET_N_POS)) - -/* 0x84 : dphy_config_1 */ -#define CSI_DPHY_CONFIG_1_OFFSET (0x84) -#define CSI_REG_TIME_CK_SETTLE CSI_REG_TIME_CK_SETTLE -#define CSI_REG_TIME_CK_SETTLE_POS (0U) -#define CSI_REG_TIME_CK_SETTLE_LEN (8U) -#define CSI_REG_TIME_CK_SETTLE_MSK (((1U << CSI_REG_TIME_CK_SETTLE_LEN) - 1) << CSI_REG_TIME_CK_SETTLE_POS) -#define CSI_REG_TIME_CK_SETTLE_UMSK (~(((1U << CSI_REG_TIME_CK_SETTLE_LEN) - 1) << CSI_REG_TIME_CK_SETTLE_POS)) -#define CSI_REG_TIME_CK_TERM_EN CSI_REG_TIME_CK_TERM_EN -#define CSI_REG_TIME_CK_TERM_EN_POS (8U) -#define CSI_REG_TIME_CK_TERM_EN_LEN (8U) -#define CSI_REG_TIME_CK_TERM_EN_MSK (((1U << CSI_REG_TIME_CK_TERM_EN_LEN) - 1) << CSI_REG_TIME_CK_TERM_EN_POS) -#define CSI_REG_TIME_CK_TERM_EN_UMSK (~(((1U << CSI_REG_TIME_CK_TERM_EN_LEN) - 1) << CSI_REG_TIME_CK_TERM_EN_POS)) -#define CSI_REG_TIME_HS_SETTLE CSI_REG_TIME_HS_SETTLE -#define CSI_REG_TIME_HS_SETTLE_POS (16U) -#define CSI_REG_TIME_HS_SETTLE_LEN (8U) -#define CSI_REG_TIME_HS_SETTLE_MSK (((1U << CSI_REG_TIME_HS_SETTLE_LEN) - 1) << CSI_REG_TIME_HS_SETTLE_POS) -#define CSI_REG_TIME_HS_SETTLE_UMSK (~(((1U << CSI_REG_TIME_HS_SETTLE_LEN) - 1) << CSI_REG_TIME_HS_SETTLE_POS)) -#define CSI_REG_TIME_HS_TERM_EN CSI_REG_TIME_HS_TERM_EN -#define CSI_REG_TIME_HS_TERM_EN_POS (24U) -#define CSI_REG_TIME_HS_TERM_EN_LEN (8U) -#define CSI_REG_TIME_HS_TERM_EN_MSK (((1U << CSI_REG_TIME_HS_TERM_EN_LEN) - 1) << CSI_REG_TIME_HS_TERM_EN_POS) -#define CSI_REG_TIME_HS_TERM_EN_UMSK (~(((1U << CSI_REG_TIME_HS_TERM_EN_LEN) - 1) << CSI_REG_TIME_HS_TERM_EN_POS)) - -/* 0x88 : dphy_config_2 */ -#define CSI_DPHY_CONFIG_2_OFFSET (0x88) -#define CSI_REG_ANA_LPRXEN_CLK CSI_REG_ANA_LPRXEN_CLK -#define CSI_REG_ANA_LPRXEN_CLK_POS (0U) -#define CSI_REG_ANA_LPRXEN_CLK_LEN (1U) -#define CSI_REG_ANA_LPRXEN_CLK_MSK (((1U << CSI_REG_ANA_LPRXEN_CLK_LEN) - 1) << CSI_REG_ANA_LPRXEN_CLK_POS) -#define CSI_REG_ANA_LPRXEN_CLK_UMSK (~(((1U << CSI_REG_ANA_LPRXEN_CLK_LEN) - 1) << CSI_REG_ANA_LPRXEN_CLK_POS)) -#define CSI_REG_ANA_HSRXEN_CLK CSI_REG_ANA_HSRXEN_CLK -#define CSI_REG_ANA_HSRXEN_CLK_POS (1U) -#define CSI_REG_ANA_HSRXEN_CLK_LEN (1U) -#define CSI_REG_ANA_HSRXEN_CLK_MSK (((1U << CSI_REG_ANA_HSRXEN_CLK_LEN) - 1) << CSI_REG_ANA_HSRXEN_CLK_POS) -#define CSI_REG_ANA_HSRXEN_CLK_UMSK (~(((1U << CSI_REG_ANA_HSRXEN_CLK_LEN) - 1) << CSI_REG_ANA_HSRXEN_CLK_POS)) -#define CSI_REG_ANA_HSRX_STOP_STATE CSI_REG_ANA_HSRX_STOP_STATE -#define CSI_REG_ANA_HSRX_STOP_STATE_POS (2U) -#define CSI_REG_ANA_HSRX_STOP_STATE_LEN (2U) -#define CSI_REG_ANA_HSRX_STOP_STATE_MSK (((1U << CSI_REG_ANA_HSRX_STOP_STATE_LEN) - 1) << CSI_REG_ANA_HSRX_STOP_STATE_POS) -#define CSI_REG_ANA_HSRX_STOP_STATE_UMSK (~(((1U << CSI_REG_ANA_HSRX_STOP_STATE_LEN) - 1) << CSI_REG_ANA_HSRX_STOP_STATE_POS)) -#define CSI_REG_ANA_HSRX_SYNC_EN CSI_REG_ANA_HSRX_SYNC_EN -#define CSI_REG_ANA_HSRX_SYNC_EN_POS (4U) -#define CSI_REG_ANA_HSRX_SYNC_EN_LEN (2U) -#define CSI_REG_ANA_HSRX_SYNC_EN_MSK (((1U << CSI_REG_ANA_HSRX_SYNC_EN_LEN) - 1) << CSI_REG_ANA_HSRX_SYNC_EN_POS) -#define CSI_REG_ANA_HSRX_SYNC_EN_UMSK (~(((1U << CSI_REG_ANA_HSRX_SYNC_EN_LEN) - 1) << CSI_REG_ANA_HSRX_SYNC_EN_POS)) -#define CSI_REG_ANA_LPRXEN CSI_REG_ANA_LPRXEN -#define CSI_REG_ANA_LPRXEN_POS (6U) -#define CSI_REG_ANA_LPRXEN_LEN (2U) -#define CSI_REG_ANA_LPRXEN_MSK (((1U << CSI_REG_ANA_LPRXEN_LEN) - 1) << CSI_REG_ANA_LPRXEN_POS) -#define CSI_REG_ANA_LPRXEN_UMSK (~(((1U << CSI_REG_ANA_LPRXEN_LEN) - 1) << CSI_REG_ANA_LPRXEN_POS)) -#define CSI_REG_ANA_HSRXEN CSI_REG_ANA_HSRXEN -#define CSI_REG_ANA_HSRXEN_POS (8U) -#define CSI_REG_ANA_HSRXEN_LEN (2U) -#define CSI_REG_ANA_HSRXEN_MSK (((1U << CSI_REG_ANA_HSRXEN_LEN) - 1) << CSI_REG_ANA_HSRXEN_POS) -#define CSI_REG_ANA_HSRXEN_UMSK (~(((1U << CSI_REG_ANA_HSRXEN_LEN) - 1) << CSI_REG_ANA_HSRXEN_POS)) -#define CSI_REG_ANA_TERM_EN CSI_REG_ANA_TERM_EN -#define CSI_REG_ANA_TERM_EN_POS (10U) -#define CSI_REG_ANA_TERM_EN_LEN (5U) -#define CSI_REG_ANA_TERM_EN_MSK (((1U << CSI_REG_ANA_TERM_EN_LEN) - 1) << CSI_REG_ANA_TERM_EN_POS) -#define CSI_REG_ANA_TERM_EN_UMSK (~(((1U << CSI_REG_ANA_TERM_EN_LEN) - 1) << CSI_REG_ANA_TERM_EN_POS)) -#define CSI_REG_ANA_TEST_EN CSI_REG_ANA_TEST_EN -#define CSI_REG_ANA_TEST_EN_POS (15U) -#define CSI_REG_ANA_TEST_EN_LEN (1U) -#define CSI_REG_ANA_TEST_EN_MSK (((1U << CSI_REG_ANA_TEST_EN_LEN) - 1) << CSI_REG_ANA_TEST_EN_POS) -#define CSI_REG_ANA_TEST_EN_UMSK (~(((1U << CSI_REG_ANA_TEST_EN_LEN) - 1) << CSI_REG_ANA_TEST_EN_POS)) -#define CSI_REG_PT_LOCK_COUNTER CSI_REG_PT_LOCK_COUNTER -#define CSI_REG_PT_LOCK_COUNTER_POS (16U) -#define CSI_REG_PT_LOCK_COUNTER_LEN (4U) -#define CSI_REG_PT_LOCK_COUNTER_MSK (((1U << CSI_REG_PT_LOCK_COUNTER_LEN) - 1) << CSI_REG_PT_LOCK_COUNTER_POS) -#define CSI_REG_PT_LOCK_COUNTER_UMSK (~(((1U << CSI_REG_PT_LOCK_COUNTER_LEN) - 1) << CSI_REG_PT_LOCK_COUNTER_POS)) -#define CSI_REG_PT_PRBS_OR_JITT CSI_REG_PT_PRBS_OR_JITT -#define CSI_REG_PT_PRBS_OR_JITT_POS (20U) -#define CSI_REG_PT_PRBS_OR_JITT_LEN (1U) -#define CSI_REG_PT_PRBS_OR_JITT_MSK (((1U << CSI_REG_PT_PRBS_OR_JITT_LEN) - 1) << CSI_REG_PT_PRBS_OR_JITT_POS) -#define CSI_REG_PT_PRBS_OR_JITT_UMSK (~(((1U << CSI_REG_PT_PRBS_OR_JITT_LEN) - 1) << CSI_REG_PT_PRBS_OR_JITT_POS)) -#define CSI_REG_PT_LP_MODE CSI_REG_PT_LP_MODE -#define CSI_REG_PT_LP_MODE_POS (21U) -#define CSI_REG_PT_LP_MODE_LEN (1U) -#define CSI_REG_PT_LP_MODE_MSK (((1U << CSI_REG_PT_LP_MODE_LEN) - 1) << CSI_REG_PT_LP_MODE_POS) -#define CSI_REG_PT_LP_MODE_UMSK (~(((1U << CSI_REG_PT_LP_MODE_LEN) - 1) << CSI_REG_PT_LP_MODE_POS)) -#define CSI_REG_PT_EN CSI_REG_PT_EN -#define CSI_REG_PT_EN_POS (22U) -#define CSI_REG_PT_EN_LEN (1U) -#define CSI_REG_PT_EN_MSK (((1U << CSI_REG_PT_EN_LEN) - 1) << CSI_REG_PT_EN_POS) -#define CSI_REG_PT_EN_UMSK (~(((1U << CSI_REG_PT_EN_LEN) - 1) << CSI_REG_PT_EN_POS)) -#define CSI_REG_PT_LOCK CSI_REG_PT_LOCK -#define CSI_REG_PT_LOCK_POS (23U) -#define CSI_REG_PT_LOCK_LEN (1U) -#define CSI_REG_PT_LOCK_MSK (((1U << CSI_REG_PT_LOCK_LEN) - 1) << CSI_REG_PT_LOCK_POS) -#define CSI_REG_PT_LOCK_UMSK (~(((1U << CSI_REG_PT_LOCK_LEN) - 1) << CSI_REG_PT_LOCK_POS)) -#define CSI_REG_PT_PASS CSI_REG_PT_PASS -#define CSI_REG_PT_PASS_POS (24U) -#define CSI_REG_PT_PASS_LEN (1U) -#define CSI_REG_PT_PASS_MSK (((1U << CSI_REG_PT_PASS_LEN) - 1) << CSI_REG_PT_PASS_POS) -#define CSI_REG_PT_PASS_UMSK (~(((1U << CSI_REG_PT_PASS_LEN) - 1) << CSI_REG_PT_PASS_POS)) - -/* 0x8C : dphy_config_3 */ -#define CSI_DPHY_CONFIG_3_OFFSET (0x8C) -#define CSI_REG_CSI_ANA_1 CSI_REG_CSI_ANA_1 -#define CSI_REG_CSI_ANA_1_POS (0U) -#define CSI_REG_CSI_ANA_1_LEN (16U) -#define CSI_REG_CSI_ANA_1_MSK (((1U << CSI_REG_CSI_ANA_1_LEN) - 1) << CSI_REG_CSI_ANA_1_POS) -#define CSI_REG_CSI_ANA_1_UMSK (~(((1U << CSI_REG_CSI_ANA_1_LEN) - 1) << CSI_REG_CSI_ANA_1_POS)) -#define CSI_REG_CSI_ANA_0 CSI_REG_CSI_ANA_0 -#define CSI_REG_CSI_ANA_0_POS (16U) -#define CSI_REG_CSI_ANA_0_LEN (16U) -#define CSI_REG_CSI_ANA_0_MSK (((1U << CSI_REG_CSI_ANA_0_LEN) - 1) << CSI_REG_CSI_ANA_0_POS) -#define CSI_REG_CSI_ANA_0_UMSK (~(((1U << CSI_REG_CSI_ANA_0_LEN) - 1) << CSI_REG_CSI_ANA_0_POS)) - -/* 0x90 : dphy_config_4 */ -#define CSI_DPHY_CONFIG_4_OFFSET (0x90) -#define CSI_REG_CSI_DC_TP_OUT_EN CSI_REG_CSI_DC_TP_OUT_EN -#define CSI_REG_CSI_DC_TP_OUT_EN_POS (0U) -#define CSI_REG_CSI_DC_TP_OUT_EN_LEN (1U) -#define CSI_REG_CSI_DC_TP_OUT_EN_MSK (((1U << CSI_REG_CSI_DC_TP_OUT_EN_LEN) - 1) << CSI_REG_CSI_DC_TP_OUT_EN_POS) -#define CSI_REG_CSI_DC_TP_OUT_EN_UMSK (~(((1U << CSI_REG_CSI_DC_TP_OUT_EN_LEN) - 1) << CSI_REG_CSI_DC_TP_OUT_EN_POS)) -#define CSI_REG_CSI_PW_AVDD1815 CSI_REG_CSI_PW_AVDD1815 -#define CSI_REG_CSI_PW_AVDD1815_POS (4U) -#define CSI_REG_CSI_PW_AVDD1815_LEN (1U) -#define CSI_REG_CSI_PW_AVDD1815_MSK (((1U << CSI_REG_CSI_PW_AVDD1815_LEN) - 1) << CSI_REG_CSI_PW_AVDD1815_POS) -#define CSI_REG_CSI_PW_AVDD1815_UMSK (~(((1U << CSI_REG_CSI_PW_AVDD1815_LEN) - 1) << CSI_REG_CSI_PW_AVDD1815_POS)) - -/* 0x94 : dphy_config_5 */ -#define CSI_DPHY_CONFIG_5_OFFSET (0x94) -#define CSI_REG_CSI_BYTE_CLK_INV CSI_REG_CSI_BYTE_CLK_INV -#define CSI_REG_CSI_BYTE_CLK_INV_POS (0U) -#define CSI_REG_CSI_BYTE_CLK_INV_LEN (1U) -#define CSI_REG_CSI_BYTE_CLK_INV_MSK (((1U << CSI_REG_CSI_BYTE_CLK_INV_LEN) - 1) << CSI_REG_CSI_BYTE_CLK_INV_POS) -#define CSI_REG_CSI_BYTE_CLK_INV_UMSK (~(((1U << CSI_REG_CSI_BYTE_CLK_INV_LEN) - 1) << CSI_REG_CSI_BYTE_CLK_INV_POS)) -#define CSI_REG_CSI_DDR_CLK_INV CSI_REG_CSI_DDR_CLK_INV -#define CSI_REG_CSI_DDR_CLK_INV_POS (1U) -#define CSI_REG_CSI_DDR_CLK_INV_LEN (1U) -#define CSI_REG_CSI_DDR_CLK_INV_MSK (((1U << CSI_REG_CSI_DDR_CLK_INV_LEN) - 1) << CSI_REG_CSI_DDR_CLK_INV_POS) -#define CSI_REG_CSI_DDR_CLK_INV_UMSK (~(((1U << CSI_REG_CSI_DDR_CLK_INV_LEN) - 1) << CSI_REG_CSI_DDR_CLK_INV_POS)) - -/* 0xFC : dummy_reg */ -#define CSI_DUMMY_REG_OFFSET (0xFC) -#define CSI_DUMMY_REG CSI_DUMMY_REG -#define CSI_DUMMY_REG_POS (0U) -#define CSI_DUMMY_REG_LEN (32U) -#define CSI_DUMMY_REG_MSK (((1U << CSI_DUMMY_REG_LEN) - 1) << CSI_DUMMY_REG_POS) -#define CSI_DUMMY_REG_UMSK (~(((1U << CSI_DUMMY_REG_LEN) - 1) << CSI_DUMMY_REG_POS)) - -struct csi_reg { - /* 0x0 : mipi_config */ - union { - struct { - uint32_t cr_csi_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t cr_lane_num : 1; /* [ 1], r/w, 0x1 */ - uint32_t rsvd_2 : 1; /* [ 2], rsvd, 0x0 */ - uint32_t cr_lane_inv : 1; /* [ 3], r/w, 0x0 */ - uint32_t cr_data_bit_inv : 1; /* [ 4], r/w, 0x0 */ - uint32_t cr_sync_sp_en : 1; /* [ 5], r/w, 0x0 */ - uint32_t cr_unpack_en : 1; /* [ 6], r/w, 0x1 */ - uint32_t reserved_7_11 : 5; /* [11: 7], rsvd, 0x0 */ - uint32_t cr_vc_dvp0 : 2; /* [13:12], r/w, 0x0 */ - uint32_t cr_vc_dvp1 : 2; /* [15:14], r/w, 0x1 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mipi_config; - - /* 0x4 reserved */ - uint8_t RESERVED0x4[12]; - - /* 0x10 : csi_int_status */ - union { - struct { - uint32_t csi_int_status : 6; /* [ 5: 0], r, 0x0 */ - uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } csi_int_status; - - /* 0x14 : csi_int_mask */ - union { - struct { - uint32_t csi_int_mask : 6; /* [ 5: 0], r/w, 0x3f */ - uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } csi_int_mask; - - /* 0x18 : csi_int_clear */ - union { - struct { - uint32_t csi_int_clear : 6; /* [ 5: 0], w1p, 0x0 */ - uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } csi_int_clear; - - /* 0x1C : csi_int_enable */ - union { - struct { - uint32_t csi_int_enable : 6; /* [ 5: 0], r/w, 0x3f */ - uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } csi_int_enable; - - /* 0x20 : gnr_buf_status */ - union { - struct { - uint32_t st_gnr_fifo_cnt : 4; /* [ 3: 0], r, 0x0 */ - uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } gnr_buf_status; - - /* 0x24 : gnr_buf_rdata */ - union { - struct { - uint32_t gnr_buf_rdata : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } gnr_buf_rdata; - - /* 0x28 reserved */ - uint8_t RESERVED0x28[88]; - - /* 0x80 : dphy_config_0 */ - union { - struct { - uint32_t dl0_enable : 1; /* [ 0], r/w, 0x0 */ - uint32_t dl1_enable : 1; /* [ 1], r/w, 0x0 */ - uint32_t cl_enable : 1; /* [ 2], r/w, 0x0 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t dl0_stopstate : 1; /* [ 4], r, 0x1 */ - uint32_t dl1_stopstate : 1; /* [ 5], r, 0x1 */ - uint32_t cl_stopstate : 1; /* [ 6], r, 0x1 */ - uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ - uint32_t dl0_ulpsactivenot : 1; /* [ 8], r, 0x1 */ - uint32_t dl1_ulpsactivenot : 1; /* [ 9], r, 0x1 */ - uint32_t cl_ulpsactivenot : 1; /* [ 10], r, 0x1 */ - uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */ - uint32_t dl0_forcerxmode : 1; /* [ 12], r/w, 0x0 */ - uint32_t dl1_forcerxmode : 1; /* [ 13], r/w, 0x0 */ - uint32_t cl_rxclkactivehs : 1; /* [ 14], r, 0x0 */ - uint32_t cl_rxulpsclknot : 1; /* [ 15], r, 0x1 */ - uint32_t reserved_16_30 : 15; /* [30:16], rsvd, 0x0 */ - uint32_t csi_reset_n : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dphy_config_0; - - /* 0x84 : dphy_config_1 */ - union { - struct { - uint32_t reg_time_ck_settle : 8; /* [ 7: 0], r/w, 0xa */ - uint32_t reg_time_ck_term_en : 8; /* [15: 8], r/w, 0x1 */ - uint32_t reg_time_hs_settle : 8; /* [23:16], r/w, 0x2f */ - uint32_t reg_time_hs_term_en : 8; /* [31:24], r/w, 0xf */ - } BF; - uint32_t WORD; - } dphy_config_1; - - /* 0x88 : dphy_config_2 */ - union { - struct { - uint32_t reg_ana_lprxen_clk : 1; /* [ 0], r/w, 0x0 */ - uint32_t reg_ana_hsrxen_clk : 1; /* [ 1], r/w, 0x0 */ - uint32_t reg_ana_hsrx_stop_state : 2; /* [ 3: 2], r/w, 0x0 */ - uint32_t reg_ana_hsrx_sync_en : 2; /* [ 5: 4], r/w, 0x0 */ - uint32_t reg_ana_lprxen : 2; /* [ 7: 6], r/w, 0x0 */ - uint32_t reg_ana_hsrxen : 2; /* [ 9: 8], r/w, 0x0 */ - uint32_t reg_ana_term_en : 5; /* [14:10], r/w, 0x0 */ - uint32_t reg_ana_test_en : 1; /* [ 15], r/w, 0x0 */ - uint32_t reg_pt_lock_counter : 4; /* [19:16], r/w, 0x0 */ - uint32_t reg_pt_prbs_or_jitt : 1; /* [ 20], r/w, 0x0 */ - uint32_t reg_pt_lp_mode : 1; /* [ 21], r/w, 0x0 */ - uint32_t reg_pt_en : 1; /* [ 22], r/w, 0x0 */ - uint32_t reg_pt_lock : 1; /* [ 23], r, 0x0 */ - uint32_t reg_pt_pass : 1; /* [ 24], r, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dphy_config_2; - - /* 0x8C : dphy_config_3 */ - union { - struct { - uint32_t reg_csi_ana_1 : 16; /* [15: 0], r/w, 0x0 */ - uint32_t reg_csi_ana_0 : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dphy_config_3; - - /* 0x90 : dphy_config_4 */ - union { - struct { - uint32_t reg_csi_dc_tp_out_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ - uint32_t reg_csi_pw_avdd1815 : 1; /* [ 4], r/w, 0x0 */ - uint32_t reserved_5_31 : 27; /* [31: 5], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dphy_config_4; - - /* 0x94 : dphy_config_5 */ - union { - struct { - uint32_t reg_csi_byte_clk_inv : 1; /* [ 0], r/w, 0x0 */ - uint32_t reg_csi_ddr_clk_inv : 1; /* [ 1], r/w, 0x0 */ - uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dphy_config_5; - - /* 0x98 reserved */ - uint8_t RESERVED0x98[100]; - - /* 0xFC : dummy_reg */ - union { - struct { - uint32_t dummy_reg : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dummy_reg; -}; - -typedef volatile struct csi_reg csi_reg_t; - -#endif /* __CSI_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dbi_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dbi_reg.h deleted file mode 100644 index cf982e4c80..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dbi_reg.h +++ /dev/null @@ -1,423 +0,0 @@ -/** - ****************************************************************************** - * @file dbi_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __DBI_REG_H__ -#define __DBI_REG_H__ - -#include "bl808.h" - -/* 0x0 : dbi_config */ -#define DBI_CONFIG_OFFSET (0x0) -#define DBI_CR_DBI_EN DBI_CR_DBI_EN -#define DBI_CR_DBI_EN_POS (0U) -#define DBI_CR_DBI_EN_LEN (1U) -#define DBI_CR_DBI_EN_MSK (((1U << DBI_CR_DBI_EN_LEN) - 1) << DBI_CR_DBI_EN_POS) -#define DBI_CR_DBI_EN_UMSK (~(((1U << DBI_CR_DBI_EN_LEN) - 1) << DBI_CR_DBI_EN_POS)) -#define DBI_CR_DBI_SEL DBI_CR_DBI_SEL -#define DBI_CR_DBI_SEL_POS (1U) -#define DBI_CR_DBI_SEL_LEN (1U) -#define DBI_CR_DBI_SEL_MSK (((1U << DBI_CR_DBI_SEL_LEN) - 1) << DBI_CR_DBI_SEL_POS) -#define DBI_CR_DBI_SEL_UMSK (~(((1U << DBI_CR_DBI_SEL_LEN) - 1) << DBI_CR_DBI_SEL_POS)) -#define DBI_CR_DBI_CMD_EN DBI_CR_DBI_CMD_EN -#define DBI_CR_DBI_CMD_EN_POS (2U) -#define DBI_CR_DBI_CMD_EN_LEN (1U) -#define DBI_CR_DBI_CMD_EN_MSK (((1U << DBI_CR_DBI_CMD_EN_LEN) - 1) << DBI_CR_DBI_CMD_EN_POS) -#define DBI_CR_DBI_CMD_EN_UMSK (~(((1U << DBI_CR_DBI_CMD_EN_LEN) - 1) << DBI_CR_DBI_CMD_EN_POS)) -#define DBI_CR_DBI_DAT_EN DBI_CR_DBI_DAT_EN -#define DBI_CR_DBI_DAT_EN_POS (3U) -#define DBI_CR_DBI_DAT_EN_LEN (1U) -#define DBI_CR_DBI_DAT_EN_MSK (((1U << DBI_CR_DBI_DAT_EN_LEN) - 1) << DBI_CR_DBI_DAT_EN_POS) -#define DBI_CR_DBI_DAT_EN_UMSK (~(((1U << DBI_CR_DBI_DAT_EN_LEN) - 1) << DBI_CR_DBI_DAT_EN_POS)) -#define DBI_CR_DBI_DAT_WR DBI_CR_DBI_DAT_WR -#define DBI_CR_DBI_DAT_WR_POS (4U) -#define DBI_CR_DBI_DAT_WR_LEN (1U) -#define DBI_CR_DBI_DAT_WR_MSK (((1U << DBI_CR_DBI_DAT_WR_LEN) - 1) << DBI_CR_DBI_DAT_WR_POS) -#define DBI_CR_DBI_DAT_WR_UMSK (~(((1U << DBI_CR_DBI_DAT_WR_LEN) - 1) << DBI_CR_DBI_DAT_WR_POS)) -#define DBI_CR_DBI_DAT_TP DBI_CR_DBI_DAT_TP -#define DBI_CR_DBI_DAT_TP_POS (5U) -#define DBI_CR_DBI_DAT_TP_LEN (1U) -#define DBI_CR_DBI_DAT_TP_MSK (((1U << DBI_CR_DBI_DAT_TP_LEN) - 1) << DBI_CR_DBI_DAT_TP_POS) -#define DBI_CR_DBI_DAT_TP_UMSK (~(((1U << DBI_CR_DBI_DAT_TP_LEN) - 1) << DBI_CR_DBI_DAT_TP_POS)) -#define DBI_CR_DBI_DAT_BC DBI_CR_DBI_DAT_BC -#define DBI_CR_DBI_DAT_BC_POS (6U) -#define DBI_CR_DBI_DAT_BC_LEN (2U) -#define DBI_CR_DBI_DAT_BC_MSK (((1U << DBI_CR_DBI_DAT_BC_LEN) - 1) << DBI_CR_DBI_DAT_BC_POS) -#define DBI_CR_DBI_DAT_BC_UMSK (~(((1U << DBI_CR_DBI_DAT_BC_LEN) - 1) << DBI_CR_DBI_DAT_BC_POS)) -#define DBI_CR_DBI_CMD DBI_CR_DBI_CMD -#define DBI_CR_DBI_CMD_POS (8U) -#define DBI_CR_DBI_CMD_LEN (8U) -#define DBI_CR_DBI_CMD_MSK (((1U << DBI_CR_DBI_CMD_LEN) - 1) << DBI_CR_DBI_CMD_POS) -#define DBI_CR_DBI_CMD_UMSK (~(((1U << DBI_CR_DBI_CMD_LEN) - 1) << DBI_CR_DBI_CMD_POS)) -#define DBI_CR_DBI_SCL_POL DBI_CR_DBI_SCL_POL -#define DBI_CR_DBI_SCL_POL_POS (16U) -#define DBI_CR_DBI_SCL_POL_LEN (1U) -#define DBI_CR_DBI_SCL_POL_MSK (((1U << DBI_CR_DBI_SCL_POL_LEN) - 1) << DBI_CR_DBI_SCL_POL_POS) -#define DBI_CR_DBI_SCL_POL_UMSK (~(((1U << DBI_CR_DBI_SCL_POL_LEN) - 1) << DBI_CR_DBI_SCL_POL_POS)) -#define DBI_CR_DBI_SCL_PH DBI_CR_DBI_SCL_PH -#define DBI_CR_DBI_SCL_PH_POS (17U) -#define DBI_CR_DBI_SCL_PH_LEN (1U) -#define DBI_CR_DBI_SCL_PH_MSK (((1U << DBI_CR_DBI_SCL_PH_LEN) - 1) << DBI_CR_DBI_SCL_PH_POS) -#define DBI_CR_DBI_SCL_PH_UMSK (~(((1U << DBI_CR_DBI_SCL_PH_LEN) - 1) << DBI_CR_DBI_SCL_PH_POS)) -#define DBI_CR_DBI_CONT_EN DBI_CR_DBI_CONT_EN -#define DBI_CR_DBI_CONT_EN_POS (18U) -#define DBI_CR_DBI_CONT_EN_LEN (1U) -#define DBI_CR_DBI_CONT_EN_MSK (((1U << DBI_CR_DBI_CONT_EN_LEN) - 1) << DBI_CR_DBI_CONT_EN_POS) -#define DBI_CR_DBI_CONT_EN_UMSK (~(((1U << DBI_CR_DBI_CONT_EN_LEN) - 1) << DBI_CR_DBI_CONT_EN_POS)) -#define DBI_CR_DBI_DMY_EN DBI_CR_DBI_DMY_EN -#define DBI_CR_DBI_DMY_EN_POS (19U) -#define DBI_CR_DBI_DMY_EN_LEN (1U) -#define DBI_CR_DBI_DMY_EN_MSK (((1U << DBI_CR_DBI_DMY_EN_LEN) - 1) << DBI_CR_DBI_DMY_EN_POS) -#define DBI_CR_DBI_DMY_EN_UMSK (~(((1U << DBI_CR_DBI_DMY_EN_LEN) - 1) << DBI_CR_DBI_DMY_EN_POS)) -#define DBI_CR_DBI_DMY_CNT DBI_CR_DBI_DMY_CNT -#define DBI_CR_DBI_DMY_CNT_POS (20U) -#define DBI_CR_DBI_DMY_CNT_LEN (4U) -#define DBI_CR_DBI_DMY_CNT_MSK (((1U << DBI_CR_DBI_DMY_CNT_LEN) - 1) << DBI_CR_DBI_DMY_CNT_POS) -#define DBI_CR_DBI_DMY_CNT_UMSK (~(((1U << DBI_CR_DBI_DMY_CNT_LEN) - 1) << DBI_CR_DBI_DMY_CNT_POS)) -#define DBI_CR_DBI_TC_3W_MODE DBI_CR_DBI_TC_3W_MODE -#define DBI_CR_DBI_TC_3W_MODE_POS (27U) -#define DBI_CR_DBI_TC_3W_MODE_LEN (1U) -#define DBI_CR_DBI_TC_3W_MODE_MSK (((1U << DBI_CR_DBI_TC_3W_MODE_LEN) - 1) << DBI_CR_DBI_TC_3W_MODE_POS) -#define DBI_CR_DBI_TC_3W_MODE_UMSK (~(((1U << DBI_CR_DBI_TC_3W_MODE_LEN) - 1) << DBI_CR_DBI_TC_3W_MODE_POS)) -#define DBI_CR_DBI_TC_DEG_EN DBI_CR_DBI_TC_DEG_EN -#define DBI_CR_DBI_TC_DEG_EN_POS (28U) -#define DBI_CR_DBI_TC_DEG_EN_LEN (1U) -#define DBI_CR_DBI_TC_DEG_EN_MSK (((1U << DBI_CR_DBI_TC_DEG_EN_LEN) - 1) << DBI_CR_DBI_TC_DEG_EN_POS) -#define DBI_CR_DBI_TC_DEG_EN_UMSK (~(((1U << DBI_CR_DBI_TC_DEG_EN_LEN) - 1) << DBI_CR_DBI_TC_DEG_EN_POS)) -#define DBI_CR_DBI_TC_DEG_CNT DBI_CR_DBI_TC_DEG_CNT -#define DBI_CR_DBI_TC_DEG_CNT_POS (29U) -#define DBI_CR_DBI_TC_DEG_CNT_LEN (3U) -#define DBI_CR_DBI_TC_DEG_CNT_MSK (((1U << DBI_CR_DBI_TC_DEG_CNT_LEN) - 1) << DBI_CR_DBI_TC_DEG_CNT_POS) -#define DBI_CR_DBI_TC_DEG_CNT_UMSK (~(((1U << DBI_CR_DBI_TC_DEG_CNT_LEN) - 1) << DBI_CR_DBI_TC_DEG_CNT_POS)) - -/* 0x4 : dbi_int_sts */ -#define DBI_INT_STS_OFFSET (0x4) -#define DBI_END_INT DBI_END_INT -#define DBI_END_INT_POS (0U) -#define DBI_END_INT_LEN (1U) -#define DBI_END_INT_MSK (((1U << DBI_END_INT_LEN) - 1) << DBI_END_INT_POS) -#define DBI_END_INT_UMSK (~(((1U << DBI_END_INT_LEN) - 1) << DBI_END_INT_POS)) -#define DBI_TXF_INT DBI_TXF_INT -#define DBI_TXF_INT_POS (1U) -#define DBI_TXF_INT_LEN (1U) -#define DBI_TXF_INT_MSK (((1U << DBI_TXF_INT_LEN) - 1) << DBI_TXF_INT_POS) -#define DBI_TXF_INT_UMSK (~(((1U << DBI_TXF_INT_LEN) - 1) << DBI_TXF_INT_POS)) -#define DBI_FER_INT DBI_FER_INT -#define DBI_FER_INT_POS (2U) -#define DBI_FER_INT_LEN (1U) -#define DBI_FER_INT_MSK (((1U << DBI_FER_INT_LEN) - 1) << DBI_FER_INT_POS) -#define DBI_FER_INT_UMSK (~(((1U << DBI_FER_INT_LEN) - 1) << DBI_FER_INT_POS)) -#define DBI_CR_DBI_END_MASK DBI_CR_DBI_END_MASK -#define DBI_CR_DBI_END_MASK_POS (8U) -#define DBI_CR_DBI_END_MASK_LEN (1U) -#define DBI_CR_DBI_END_MASK_MSK (((1U << DBI_CR_DBI_END_MASK_LEN) - 1) << DBI_CR_DBI_END_MASK_POS) -#define DBI_CR_DBI_END_MASK_UMSK (~(((1U << DBI_CR_DBI_END_MASK_LEN) - 1) << DBI_CR_DBI_END_MASK_POS)) -#define DBI_CR_DBI_TXF_MASK DBI_CR_DBI_TXF_MASK -#define DBI_CR_DBI_TXF_MASK_POS (9U) -#define DBI_CR_DBI_TXF_MASK_LEN (1U) -#define DBI_CR_DBI_TXF_MASK_MSK (((1U << DBI_CR_DBI_TXF_MASK_LEN) - 1) << DBI_CR_DBI_TXF_MASK_POS) -#define DBI_CR_DBI_TXF_MASK_UMSK (~(((1U << DBI_CR_DBI_TXF_MASK_LEN) - 1) << DBI_CR_DBI_TXF_MASK_POS)) -#define DBI_CR_DBI_FER_MASK DBI_CR_DBI_FER_MASK -#define DBI_CR_DBI_FER_MASK_POS (10U) -#define DBI_CR_DBI_FER_MASK_LEN (1U) -#define DBI_CR_DBI_FER_MASK_MSK (((1U << DBI_CR_DBI_FER_MASK_LEN) - 1) << DBI_CR_DBI_FER_MASK_POS) -#define DBI_CR_DBI_FER_MASK_UMSK (~(((1U << DBI_CR_DBI_FER_MASK_LEN) - 1) << DBI_CR_DBI_FER_MASK_POS)) -#define DBI_CR_DBI_END_CLR DBI_CR_DBI_END_CLR -#define DBI_CR_DBI_END_CLR_POS (16U) -#define DBI_CR_DBI_END_CLR_LEN (1U) -#define DBI_CR_DBI_END_CLR_MSK (((1U << DBI_CR_DBI_END_CLR_LEN) - 1) << DBI_CR_DBI_END_CLR_POS) -#define DBI_CR_DBI_END_CLR_UMSK (~(((1U << DBI_CR_DBI_END_CLR_LEN) - 1) << DBI_CR_DBI_END_CLR_POS)) -#define DBI_CR_DBI_END_EN DBI_CR_DBI_END_EN -#define DBI_CR_DBI_END_EN_POS (24U) -#define DBI_CR_DBI_END_EN_LEN (1U) -#define DBI_CR_DBI_END_EN_MSK (((1U << DBI_CR_DBI_END_EN_LEN) - 1) << DBI_CR_DBI_END_EN_POS) -#define DBI_CR_DBI_END_EN_UMSK (~(((1U << DBI_CR_DBI_END_EN_LEN) - 1) << DBI_CR_DBI_END_EN_POS)) -#define DBI_CR_DBI_TXF_EN DBI_CR_DBI_TXF_EN -#define DBI_CR_DBI_TXF_EN_POS (25U) -#define DBI_CR_DBI_TXF_EN_LEN (1U) -#define DBI_CR_DBI_TXF_EN_MSK (((1U << DBI_CR_DBI_TXF_EN_LEN) - 1) << DBI_CR_DBI_TXF_EN_POS) -#define DBI_CR_DBI_TXF_EN_UMSK (~(((1U << DBI_CR_DBI_TXF_EN_LEN) - 1) << DBI_CR_DBI_TXF_EN_POS)) -#define DBI_CR_DBI_FER_EN DBI_CR_DBI_FER_EN -#define DBI_CR_DBI_FER_EN_POS (26U) -#define DBI_CR_DBI_FER_EN_LEN (1U) -#define DBI_CR_DBI_FER_EN_MSK (((1U << DBI_CR_DBI_FER_EN_LEN) - 1) << DBI_CR_DBI_FER_EN_POS) -#define DBI_CR_DBI_FER_EN_UMSK (~(((1U << DBI_CR_DBI_FER_EN_LEN) - 1) << DBI_CR_DBI_FER_EN_POS)) - -/* 0x8 : dbi_bus_busy */ -#define DBI_BUS_BUSY_OFFSET (0x8) -#define DBI_STS_DBI_BUS_BUSY DBI_STS_DBI_BUS_BUSY -#define DBI_STS_DBI_BUS_BUSY_POS (0U) -#define DBI_STS_DBI_BUS_BUSY_LEN (1U) -#define DBI_STS_DBI_BUS_BUSY_MSK (((1U << DBI_STS_DBI_BUS_BUSY_LEN) - 1) << DBI_STS_DBI_BUS_BUSY_POS) -#define DBI_STS_DBI_BUS_BUSY_UMSK (~(((1U << DBI_STS_DBI_BUS_BUSY_LEN) - 1) << DBI_STS_DBI_BUS_BUSY_POS)) - -/* 0xC : dbi_pix_cnt */ -#define DBI_PIX_CNT_OFFSET (0xC) -#define DBI_CR_DBI_PIX_CNT DBI_CR_DBI_PIX_CNT -#define DBI_CR_DBI_PIX_CNT_POS (0U) -#define DBI_CR_DBI_PIX_CNT_LEN (24U) -#define DBI_CR_DBI_PIX_CNT_MSK (((1U << DBI_CR_DBI_PIX_CNT_LEN) - 1) << DBI_CR_DBI_PIX_CNT_POS) -#define DBI_CR_DBI_PIX_CNT_UMSK (~(((1U << DBI_CR_DBI_PIX_CNT_LEN) - 1) << DBI_CR_DBI_PIX_CNT_POS)) -#define DBI_CR_DBI_PIX_FORMAT DBI_CR_DBI_PIX_FORMAT -#define DBI_CR_DBI_PIX_FORMAT_POS (31U) -#define DBI_CR_DBI_PIX_FORMAT_LEN (1U) -#define DBI_CR_DBI_PIX_FORMAT_MSK (((1U << DBI_CR_DBI_PIX_FORMAT_LEN) - 1) << DBI_CR_DBI_PIX_FORMAT_POS) -#define DBI_CR_DBI_PIX_FORMAT_UMSK (~(((1U << DBI_CR_DBI_PIX_FORMAT_LEN) - 1) << DBI_CR_DBI_PIX_FORMAT_POS)) - -/* 0x10 : dbi_prd */ -#define DBI_PRD_OFFSET (0x10) -#define DBI_CR_DBI_PRD_S DBI_CR_DBI_PRD_S -#define DBI_CR_DBI_PRD_S_POS (0U) -#define DBI_CR_DBI_PRD_S_LEN (8U) -#define DBI_CR_DBI_PRD_S_MSK (((1U << DBI_CR_DBI_PRD_S_LEN) - 1) << DBI_CR_DBI_PRD_S_POS) -#define DBI_CR_DBI_PRD_S_UMSK (~(((1U << DBI_CR_DBI_PRD_S_LEN) - 1) << DBI_CR_DBI_PRD_S_POS)) -#define DBI_CR_DBI_PRD_I DBI_CR_DBI_PRD_I -#define DBI_CR_DBI_PRD_I_POS (8U) -#define DBI_CR_DBI_PRD_I_LEN (8U) -#define DBI_CR_DBI_PRD_I_MSK (((1U << DBI_CR_DBI_PRD_I_LEN) - 1) << DBI_CR_DBI_PRD_I_POS) -#define DBI_CR_DBI_PRD_I_UMSK (~(((1U << DBI_CR_DBI_PRD_I_LEN) - 1) << DBI_CR_DBI_PRD_I_POS)) -#define DBI_CR_DBI_PRD_D_PH_0 DBI_CR_DBI_PRD_D_PH_0 -#define DBI_CR_DBI_PRD_D_PH_0_POS (16U) -#define DBI_CR_DBI_PRD_D_PH_0_LEN (8U) -#define DBI_CR_DBI_PRD_D_PH_0_MSK (((1U << DBI_CR_DBI_PRD_D_PH_0_LEN) - 1) << DBI_CR_DBI_PRD_D_PH_0_POS) -#define DBI_CR_DBI_PRD_D_PH_0_UMSK (~(((1U << DBI_CR_DBI_PRD_D_PH_0_LEN) - 1) << DBI_CR_DBI_PRD_D_PH_0_POS)) -#define DBI_CR_DBI_PRD_D_PH_1 DBI_CR_DBI_PRD_D_PH_1 -#define DBI_CR_DBI_PRD_D_PH_1_POS (24U) -#define DBI_CR_DBI_PRD_D_PH_1_LEN (8U) -#define DBI_CR_DBI_PRD_D_PH_1_MSK (((1U << DBI_CR_DBI_PRD_D_PH_1_LEN) - 1) << DBI_CR_DBI_PRD_D_PH_1_POS) -#define DBI_CR_DBI_PRD_D_PH_1_UMSK (~(((1U << DBI_CR_DBI_PRD_D_PH_1_LEN) - 1) << DBI_CR_DBI_PRD_D_PH_1_POS)) - -/* 0x18 : dbi_wdata */ -#define DBI_WDATA_OFFSET (0x18) -#define DBI_CR_DBI_WDATA DBI_CR_DBI_WDATA -#define DBI_CR_DBI_WDATA_POS (0U) -#define DBI_CR_DBI_WDATA_LEN (32U) -#define DBI_CR_DBI_WDATA_MSK (((1U << DBI_CR_DBI_WDATA_LEN) - 1) << DBI_CR_DBI_WDATA_POS) -#define DBI_CR_DBI_WDATA_UMSK (~(((1U << DBI_CR_DBI_WDATA_LEN) - 1) << DBI_CR_DBI_WDATA_POS)) - -/* 0x1C : dbi_rdata */ -#define DBI_RDATA_OFFSET (0x1C) -#define DBI_STS_DBI_RDATA DBI_STS_DBI_RDATA -#define DBI_STS_DBI_RDATA_POS (0U) -#define DBI_STS_DBI_RDATA_LEN (32U) -#define DBI_STS_DBI_RDATA_MSK (((1U << DBI_STS_DBI_RDATA_LEN) - 1) << DBI_STS_DBI_RDATA_POS) -#define DBI_STS_DBI_RDATA_UMSK (~(((1U << DBI_STS_DBI_RDATA_LEN) - 1) << DBI_STS_DBI_RDATA_POS)) - -/* 0x80 : dbi_fifo_config_0 */ -#define DBI_FIFO_CONFIG_0_OFFSET (0x80) -#define DBI_DMA_TX_EN DBI_DMA_TX_EN -#define DBI_DMA_TX_EN_POS (0U) -#define DBI_DMA_TX_EN_LEN (1U) -#define DBI_DMA_TX_EN_MSK (((1U << DBI_DMA_TX_EN_LEN) - 1) << DBI_DMA_TX_EN_POS) -#define DBI_DMA_TX_EN_UMSK (~(((1U << DBI_DMA_TX_EN_LEN) - 1) << DBI_DMA_TX_EN_POS)) -#define DBI_TX_FIFO_CLR DBI_TX_FIFO_CLR -#define DBI_TX_FIFO_CLR_POS (2U) -#define DBI_TX_FIFO_CLR_LEN (1U) -#define DBI_TX_FIFO_CLR_MSK (((1U << DBI_TX_FIFO_CLR_LEN) - 1) << DBI_TX_FIFO_CLR_POS) -#define DBI_TX_FIFO_CLR_UMSK (~(((1U << DBI_TX_FIFO_CLR_LEN) - 1) << DBI_TX_FIFO_CLR_POS)) -#define DBI_TX_FIFO_OVERFLOW DBI_TX_FIFO_OVERFLOW -#define DBI_TX_FIFO_OVERFLOW_POS (4U) -#define DBI_TX_FIFO_OVERFLOW_LEN (1U) -#define DBI_TX_FIFO_OVERFLOW_MSK (((1U << DBI_TX_FIFO_OVERFLOW_LEN) - 1) << DBI_TX_FIFO_OVERFLOW_POS) -#define DBI_TX_FIFO_OVERFLOW_UMSK (~(((1U << DBI_TX_FIFO_OVERFLOW_LEN) - 1) << DBI_TX_FIFO_OVERFLOW_POS)) -#define DBI_TX_FIFO_UNDERFLOW DBI_TX_FIFO_UNDERFLOW -#define DBI_TX_FIFO_UNDERFLOW_POS (5U) -#define DBI_TX_FIFO_UNDERFLOW_LEN (1U) -#define DBI_TX_FIFO_UNDERFLOW_MSK (((1U << DBI_TX_FIFO_UNDERFLOW_LEN) - 1) << DBI_TX_FIFO_UNDERFLOW_POS) -#define DBI_TX_FIFO_UNDERFLOW_UMSK (~(((1U << DBI_TX_FIFO_UNDERFLOW_LEN) - 1) << DBI_TX_FIFO_UNDERFLOW_POS)) -#define DBI_FIFO_FORMAT DBI_FIFO_FORMAT -#define DBI_FIFO_FORMAT_POS (29U) -#define DBI_FIFO_FORMAT_LEN (3U) -#define DBI_FIFO_FORMAT_MSK (((1U << DBI_FIFO_FORMAT_LEN) - 1) << DBI_FIFO_FORMAT_POS) -#define DBI_FIFO_FORMAT_UMSK (~(((1U << DBI_FIFO_FORMAT_LEN) - 1) << DBI_FIFO_FORMAT_POS)) - -/* 0x84 : dbi_fifo_config_1 */ -#define DBI_FIFO_CONFIG_1_OFFSET (0x84) -#define DBI_TX_FIFO_CNT DBI_TX_FIFO_CNT -#define DBI_TX_FIFO_CNT_POS (0U) -#define DBI_TX_FIFO_CNT_LEN (4U) -#define DBI_TX_FIFO_CNT_MSK (((1U << DBI_TX_FIFO_CNT_LEN) - 1) << DBI_TX_FIFO_CNT_POS) -#define DBI_TX_FIFO_CNT_UMSK (~(((1U << DBI_TX_FIFO_CNT_LEN) - 1) << DBI_TX_FIFO_CNT_POS)) -#define DBI_TX_FIFO_TH DBI_TX_FIFO_TH -#define DBI_TX_FIFO_TH_POS (16U) -#define DBI_TX_FIFO_TH_LEN (3U) -#define DBI_TX_FIFO_TH_MSK (((1U << DBI_TX_FIFO_TH_LEN) - 1) << DBI_TX_FIFO_TH_POS) -#define DBI_TX_FIFO_TH_UMSK (~(((1U << DBI_TX_FIFO_TH_LEN) - 1) << DBI_TX_FIFO_TH_POS)) - -/* 0x88 : dbi_fifo_wdata */ -#define DBI_FIFO_WDATA_OFFSET (0x88) -#define DBI_FIFO_WDATA DBI_FIFO_WDATA -#define DBI_FIFO_WDATA_POS (0U) -#define DBI_FIFO_WDATA_LEN (32U) -#define DBI_FIFO_WDATA_MSK (((1U << DBI_FIFO_WDATA_LEN) - 1) << DBI_FIFO_WDATA_POS) -#define DBI_FIFO_WDATA_UMSK (~(((1U << DBI_FIFO_WDATA_LEN) - 1) << DBI_FIFO_WDATA_POS)) - -struct dbi_reg { - /* 0x0 : dbi_config */ - union { - struct { - uint32_t cr_dbi_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t cr_dbi_sel : 1; /* [ 1], r/w, 0x0 */ - uint32_t cr_dbi_cmd_en : 1; /* [ 2], r/w, 0x1 */ - uint32_t cr_dbi_dat_en : 1; /* [ 3], r/w, 0x1 */ - uint32_t cr_dbi_dat_wr : 1; /* [ 4], r/w, 0x1 */ - uint32_t cr_dbi_dat_tp : 1; /* [ 5], r/w, 0x0 */ - uint32_t cr_dbi_dat_bc : 2; /* [ 7: 6], r/w, 0x0 */ - uint32_t cr_dbi_cmd : 8; /* [15: 8], r/w, 0x2c */ - uint32_t cr_dbi_scl_pol : 1; /* [ 16], r/w, 0x1 */ - uint32_t cr_dbi_scl_ph : 1; /* [ 17], r/w, 0x0 */ - uint32_t cr_dbi_cont_en : 1; /* [ 18], r/w, 0x1 */ - uint32_t cr_dbi_dmy_en : 1; /* [ 19], r/w, 0x0 */ - uint32_t cr_dbi_dmy_cnt : 4; /* [23:20], r/w, 0x0 */ - uint32_t rsvd_26_24 : 3; /* [26:24], rsvd, 0x0 */ - uint32_t cr_dbi_tc_3w_mode : 1; /* [ 27], r/w, 0x0 */ - uint32_t cr_dbi_tc_deg_en : 1; /* [ 28], r/w, 0x0 */ - uint32_t cr_dbi_tc_deg_cnt : 3; /* [31:29], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dbi_config; - - /* 0x4 : dbi_int_sts */ - union { - struct { - uint32_t dbi_end_int : 1; /* [ 0], r, 0x0 */ - uint32_t dbi_txf_int : 1; /* [ 1], r, 0x1 */ - uint32_t dbi_fer_int : 1; /* [ 2], r, 0x0 */ - uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */ - uint32_t cr_dbi_end_mask : 1; /* [ 8], r/w, 0x1 */ - uint32_t cr_dbi_txf_mask : 1; /* [ 9], r/w, 0x1 */ - uint32_t cr_dbi_fer_mask : 1; /* [ 10], r/w, 0x1 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t cr_dbi_end_clr : 1; /* [ 16], w1c, 0x0 */ - uint32_t rsvd_17 : 1; /* [ 17], rsvd, 0x0 */ - uint32_t rsvd_18 : 1; /* [ 18], rsvd, 0x0 */ - uint32_t reserved_19_23 : 5; /* [23:19], rsvd, 0x0 */ - uint32_t cr_dbi_end_en : 1; /* [ 24], r/w, 0x1 */ - uint32_t cr_dbi_txf_en : 1; /* [ 25], r/w, 0x1 */ - uint32_t cr_dbi_fer_en : 1; /* [ 26], r/w, 0x1 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dbi_int_sts; - - /* 0x8 : dbi_bus_busy */ - union { - struct { - uint32_t sts_dbi_bus_busy : 1; /* [ 0], r, 0x0 */ - uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dbi_bus_busy; - - /* 0xC : dbi_pix_cnt */ - union { - struct { - uint32_t cr_dbi_pix_cnt : 24; /* [23: 0], r/w, 0x0 */ - uint32_t reserved_24_30 : 7; /* [30:24], rsvd, 0x0 */ - uint32_t cr_dbi_pix_format : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dbi_pix_cnt; - - /* 0x10 : dbi_prd */ - union { - struct { - uint32_t cr_dbi_prd_s : 8; /* [ 7: 0], r/w, 0xf */ - uint32_t cr_dbi_prd_i : 8; /* [15: 8], r/w, 0xf */ - uint32_t cr_dbi_prd_d_ph_0 : 8; /* [23:16], r/w, 0xf */ - uint32_t cr_dbi_prd_d_ph_1 : 8; /* [31:24], r/w, 0xf */ - } BF; - uint32_t WORD; - } dbi_prd; - - /* 0x14 reserved */ - uint8_t RESERVED0x14[4]; - - /* 0x18 : dbi_wdata */ - union { - struct { - uint32_t cr_dbi_wdata : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dbi_wdata; - - /* 0x1C : dbi_rdata */ - union { - struct { - uint32_t sts_dbi_rdata : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } dbi_rdata; - - /* 0x20 reserved */ - uint8_t RESERVED0x20[96]; - - /* 0x80 : dbi_fifo_config_0 */ - union { - struct { - uint32_t dbi_dma_tx_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1 : 1; /* [ 1], rsvd, 0x0 */ - uint32_t tx_fifo_clr : 1; /* [ 2], w1c, 0x0 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t tx_fifo_overflow : 1; /* [ 4], r, 0x0 */ - uint32_t tx_fifo_underflow : 1; /* [ 5], r, 0x0 */ - uint32_t reserved_6_28 : 23; /* [28: 6], rsvd, 0x0 */ - uint32_t fifo_format : 3; /* [31:29], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dbi_fifo_config_0; - - /* 0x84 : dbi_fifo_config_1 */ - union { - struct { - uint32_t tx_fifo_cnt : 4; /* [ 3: 0], r, 0x8 */ - uint32_t reserved_4_15 : 12; /* [15: 4], rsvd, 0x0 */ - uint32_t tx_fifo_th : 3; /* [18:16], r/w, 0x0 */ - uint32_t reserved_19_31 : 13; /* [31:19], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dbi_fifo_config_1; - - /* 0x88 : dbi_fifo_wdata */ - union { - struct { - uint32_t dbi_fifo_wdata : 32; /* [31: 0], w, x */ - } BF; - uint32_t WORD; - } dbi_fifo_wdata; -}; - -typedef volatile struct dbi_reg dbi_reg_t; - -#endif /* __DBI_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dma2d_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dma2d_reg.h deleted file mode 100644 index ff2e90c3dd..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dma2d_reg.h +++ /dev/null @@ -1,574 +0,0 @@ -/** - ****************************************************************************** - * @file dma2d_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __DMA2D_REG_H__ -#define __DMA2D_REG_H__ - -#include "bl808.h" - -/* 0x0 : DMA_IntStatus */ -#define DMA2D_DMA_INTSTATUS_OFFSET (0x0) -#define DMA2D_INTSTATUS DMA2D_INTSTATUS -#define DMA2D_INTSTATUS_POS (0U) -#define DMA2D_INTSTATUS_LEN (8U) -#define DMA2D_INTSTATUS_MSK (((1U << DMA2D_INTSTATUS_LEN) - 1) << DMA2D_INTSTATUS_POS) -#define DMA2D_INTSTATUS_UMSK (~(((1U << DMA2D_INTSTATUS_LEN) - 1) << DMA2D_INTSTATUS_POS)) - -/* 0x4 : DMA_IntTCStatus */ -#define DMA2D_DMA_INTTCSTATUS_OFFSET (0x4) -#define DMA2D_INTTCSTATUS DMA2D_INTTCSTATUS -#define DMA2D_INTTCSTATUS_POS (0U) -#define DMA2D_INTTCSTATUS_LEN (8U) -#define DMA2D_INTTCSTATUS_MSK (((1U << DMA2D_INTTCSTATUS_LEN) - 1) << DMA2D_INTTCSTATUS_POS) -#define DMA2D_INTTCSTATUS_UMSK (~(((1U << DMA2D_INTTCSTATUS_LEN) - 1) << DMA2D_INTTCSTATUS_POS)) - -/* 0x8 : DMA_IntTCClear */ -#define DMA2D_DMA_INTTCCLEAR_OFFSET (0x8) -#define DMA2D_INTTCCLEAR DMA2D_INTTCCLEAR -#define DMA2D_INTTCCLEAR_POS (0U) -#define DMA2D_INTTCCLEAR_LEN (8U) -#define DMA2D_INTTCCLEAR_MSK (((1U << DMA2D_INTTCCLEAR_LEN) - 1) << DMA2D_INTTCCLEAR_POS) -#define DMA2D_INTTCCLEAR_UMSK (~(((1U << DMA2D_INTTCCLEAR_LEN) - 1) << DMA2D_INTTCCLEAR_POS)) - -/* 0xC : DMA_EnbldChns */ -#define DMA2D_DMA_ENBLDCHNS_OFFSET (0xC) -#define DMA2D_ENABLEDCHANNELS DMA2D_ENABLEDCHANNELS -#define DMA2D_ENABLEDCHANNELS_POS (0U) -#define DMA2D_ENABLEDCHANNELS_LEN (8U) -#define DMA2D_ENABLEDCHANNELS_MSK (((1U << DMA2D_ENABLEDCHANNELS_LEN) - 1) << DMA2D_ENABLEDCHANNELS_POS) -#define DMA2D_ENABLEDCHANNELS_UMSK (~(((1U << DMA2D_ENABLEDCHANNELS_LEN) - 1) << DMA2D_ENABLEDCHANNELS_POS)) - -/* 0x10 : DMA_Config */ -#define DMA2D_DMA_CONFIG_OFFSET (0x10) -#define DMA2D_E DMA2D_E -#define DMA2D_E_POS (0U) -#define DMA2D_E_LEN (1U) -#define DMA2D_E_MSK (((1U << DMA2D_E_LEN) - 1) << DMA2D_E_POS) -#define DMA2D_E_UMSK (~(((1U << DMA2D_E_LEN) - 1) << DMA2D_E_POS)) -#define DMA2D_CHCLKCG DMA2D_CHCLKCG -#define DMA2D_CHCLKCG_POS (16U) -#define DMA2D_CHCLKCG_LEN (8U) -#define DMA2D_CHCLKCG_MSK (((1U << DMA2D_CHCLKCG_LEN) - 1) << DMA2D_CHCLKCG_POS) -#define DMA2D_CHCLKCG_UMSK (~(((1U << DMA2D_CHCLKCG_LEN) - 1) << DMA2D_CHCLKCG_POS)) - -/* 0x14 : DMA_Sync */ -#define DMA2D_DMA_SYNC_OFFSET (0x14) -#define DMA2D_DMA_SYNC DMA2D_DMA_SYNC -#define DMA2D_DMA_SYNC_POS (0U) -#define DMA2D_DMA_SYNC_LEN (32U) -#define DMA2D_DMA_SYNC_MSK (((1U << DMA2D_DMA_SYNC_LEN) - 1) << DMA2D_DMA_SYNC_POS) -#define DMA2D_DMA_SYNC_UMSK (~(((1U << DMA2D_DMA_SYNC_LEN) - 1) << DMA2D_DMA_SYNC_POS)) - -/* 0x18 : DMA_SoftBReq */ -#define DMA2D_DMA_SOFTBREQ_OFFSET (0x18) -#define DMA2D_SOFTBREQ DMA2D_SOFTBREQ -#define DMA2D_SOFTBREQ_POS (0U) -#define DMA2D_SOFTBREQ_LEN (32U) -#define DMA2D_SOFTBREQ_MSK (((1U << DMA2D_SOFTBREQ_LEN) - 1) << DMA2D_SOFTBREQ_POS) -#define DMA2D_SOFTBREQ_UMSK (~(((1U << DMA2D_SOFTBREQ_LEN) - 1) << DMA2D_SOFTBREQ_POS)) - -/* 0x1C : DMA_SoftLBReq */ -#define DMA2D_DMA_SOFTLBREQ_OFFSET (0x1C) -#define DMA2D_SOFTLBREQ DMA2D_SOFTLBREQ -#define DMA2D_SOFTLBREQ_POS (0U) -#define DMA2D_SOFTLBREQ_LEN (32U) -#define DMA2D_SOFTLBREQ_MSK (((1U << DMA2D_SOFTLBREQ_LEN) - 1) << DMA2D_SOFTLBREQ_POS) -#define DMA2D_SOFTLBREQ_UMSK (~(((1U << DMA2D_SOFTLBREQ_LEN) - 1) << DMA2D_SOFTLBREQ_POS)) - -/* 0x20 : DMA_SoftSReq */ -#define DMA2D_DMA_SOFTSREQ_OFFSET (0x20) -#define DMA2D_SOFTSREQ DMA2D_SOFTSREQ -#define DMA2D_SOFTSREQ_POS (0U) -#define DMA2D_SOFTSREQ_LEN (32U) -#define DMA2D_SOFTSREQ_MSK (((1U << DMA2D_SOFTSREQ_LEN) - 1) << DMA2D_SOFTSREQ_POS) -#define DMA2D_SOFTSREQ_UMSK (~(((1U << DMA2D_SOFTSREQ_LEN) - 1) << DMA2D_SOFTSREQ_POS)) - -/* 0x24 : DMA_SoftLSReq */ -#define DMA2D_DMA_SOFTLSREQ_OFFSET (0x24) -#define DMA2D_SOFTLSREQ DMA2D_SOFTLSREQ -#define DMA2D_SOFTLSREQ_POS (0U) -#define DMA2D_SOFTLSREQ_LEN (32U) -#define DMA2D_SOFTLSREQ_MSK (((1U << DMA2D_SOFTLSREQ_LEN) - 1) << DMA2D_SOFTLSREQ_POS) -#define DMA2D_SOFTLSREQ_UMSK (~(((1U << DMA2D_SOFTLSREQ_LEN) - 1) << DMA2D_SOFTLSREQ_POS)) - -/* 0x100 : DMA2D_C0SrcAddr */ -#define DMA2D_C0SRCADDR_OFFSET (0x100) -#define DMA2D_SRCADDR DMA2D_SRCADDR -#define DMA2D_SRCADDR_POS (0U) -#define DMA2D_SRCADDR_LEN (32U) -#define DMA2D_SRCADDR_MSK (((1U << DMA2D_SRCADDR_LEN) - 1) << DMA2D_SRCADDR_POS) -#define DMA2D_SRCADDR_UMSK (~(((1U << DMA2D_SRCADDR_LEN) - 1) << DMA2D_SRCADDR_POS)) - -/* 0x104 : DMA2D_C0DstAddr */ -#define DMA2D_C0DSTADDR_OFFSET (0x104) -#define DMA2D_DSTADDR DMA2D_DSTADDR -#define DMA2D_DSTADDR_POS (0U) -#define DMA2D_DSTADDR_LEN (32U) -#define DMA2D_DSTADDR_MSK (((1U << DMA2D_DSTADDR_LEN) - 1) << DMA2D_DSTADDR_POS) -#define DMA2D_DSTADDR_UMSK (~(((1U << DMA2D_DSTADDR_LEN) - 1) << DMA2D_DSTADDR_POS)) - -/* 0x108 : DMA2D_C0LLI */ -#define DMA2D_C0LLI_OFFSET (0x108) -#define DMA2D_LLI_EN DMA2D_LLI_EN -#define DMA2D_LLI_EN_POS (0U) -#define DMA2D_LLI_EN_LEN (1U) -#define DMA2D_LLI_EN_MSK (((1U << DMA2D_LLI_EN_LEN) - 1) << DMA2D_LLI_EN_POS) -#define DMA2D_LLI_EN_UMSK (~(((1U << DMA2D_LLI_EN_LEN) - 1) << DMA2D_LLI_EN_POS)) -#define DMA2D_LLI_ADDR DMA2D_LLI_ADDR -#define DMA2D_LLI_ADDR_POS (2U) -#define DMA2D_LLI_ADDR_LEN (30U) -#define DMA2D_LLI_ADDR_MSK (((1U << DMA2D_LLI_ADDR_LEN) - 1) << DMA2D_LLI_ADDR_POS) -#define DMA2D_LLI_ADDR_UMSK (~(((1U << DMA2D_LLI_ADDR_LEN) - 1) << DMA2D_LLI_ADDR_POS)) - -/* 0x10C : DMA2D_C0_BUS */ -#define DMA2D_C0_BUS_OFFSET (0x10C) -#define DMA2D_TRANSFERSIZE DMA2D_TRANSFERSIZE -#define DMA2D_TRANSFERSIZE_POS (0U) -#define DMA2D_TRANSFERSIZE_LEN (12U) -#define DMA2D_TRANSFERSIZE_MSK (((1U << DMA2D_TRANSFERSIZE_LEN) - 1) << DMA2D_TRANSFERSIZE_POS) -#define DMA2D_TRANSFERSIZE_UMSK (~(((1U << DMA2D_TRANSFERSIZE_LEN) - 1) << DMA2D_TRANSFERSIZE_POS)) -#define DMA2D_SRC_BURST DMA2D_SRC_BURST -#define DMA2D_SRC_BURST_POS (12U) -#define DMA2D_SRC_BURST_LEN (2U) -#define DMA2D_SRC_BURST_MSK (((1U << DMA2D_SRC_BURST_LEN) - 1) << DMA2D_SRC_BURST_POS) -#define DMA2D_SRC_BURST_UMSK (~(((1U << DMA2D_SRC_BURST_LEN) - 1) << DMA2D_SRC_BURST_POS)) -#define DMA2D_DST_BURST DMA2D_DST_BURST -#define DMA2D_DST_BURST_POS (15U) -#define DMA2D_DST_BURST_LEN (2U) -#define DMA2D_DST_BURST_MSK (((1U << DMA2D_DST_BURST_LEN) - 1) << DMA2D_DST_BURST_POS) -#define DMA2D_DST_BURST_UMSK (~(((1U << DMA2D_DST_BURST_LEN) - 1) << DMA2D_DST_BURST_POS)) -#define DMA2D_SRC_SIZE DMA2D_SRC_SIZE -#define DMA2D_SRC_SIZE_POS (18U) -#define DMA2D_SRC_SIZE_LEN (2U) -#define DMA2D_SRC_SIZE_MSK (((1U << DMA2D_SRC_SIZE_LEN) - 1) << DMA2D_SRC_SIZE_POS) -#define DMA2D_SRC_SIZE_UMSK (~(((1U << DMA2D_SRC_SIZE_LEN) - 1) << DMA2D_SRC_SIZE_POS)) -#define DMA2D_DST_SIZE DMA2D_DST_SIZE -#define DMA2D_DST_SIZE_POS (21U) -#define DMA2D_DST_SIZE_LEN (2U) -#define DMA2D_DST_SIZE_MSK (((1U << DMA2D_DST_SIZE_LEN) - 1) << DMA2D_DST_SIZE_POS) -#define DMA2D_DST_SIZE_UMSK (~(((1U << DMA2D_DST_SIZE_LEN) - 1) << DMA2D_DST_SIZE_POS)) -#define DMA2D_SI DMA2D_SI -#define DMA2D_SI_POS (26U) -#define DMA2D_SI_LEN (1U) -#define DMA2D_SI_MSK (((1U << DMA2D_SI_LEN) - 1) << DMA2D_SI_POS) -#define DMA2D_SI_UMSK (~(((1U << DMA2D_SI_LEN) - 1) << DMA2D_SI_POS)) -#define DMA2D_DI DMA2D_DI -#define DMA2D_DI_POS (27U) -#define DMA2D_DI_LEN (1U) -#define DMA2D_DI_MSK (((1U << DMA2D_DI_LEN) - 1) << DMA2D_DI_POS) -#define DMA2D_DI_UMSK (~(((1U << DMA2D_DI_LEN) - 1) << DMA2D_DI_POS)) -#define DMA2D_PROT DMA2D_PROT -#define DMA2D_PROT_POS (28U) -#define DMA2D_PROT_LEN (3U) -#define DMA2D_PROT_MSK (((1U << DMA2D_PROT_LEN) - 1) << DMA2D_PROT_POS) -#define DMA2D_PROT_UMSK (~(((1U << DMA2D_PROT_LEN) - 1) << DMA2D_PROT_POS)) -#define DMA2D_I DMA2D_I -#define DMA2D_I_POS (31U) -#define DMA2D_I_LEN (1U) -#define DMA2D_I_MSK (((1U << DMA2D_I_LEN) - 1) << DMA2D_I_POS) -#define DMA2D_I_UMSK (~(((1U << DMA2D_I_LEN) - 1) << DMA2D_I_POS)) - -/* 0x110 : DMA2D_C0_SRC_CNT */ -#define DMA2D_C0_SRC_CNT_OFFSET (0x110) -#define DMA2D_SRC_X_CNT DMA2D_SRC_X_CNT -#define DMA2D_SRC_X_CNT_POS (0U) -#define DMA2D_SRC_X_CNT_LEN (16U) -#define DMA2D_SRC_X_CNT_MSK (((1U << DMA2D_SRC_X_CNT_LEN) - 1) << DMA2D_SRC_X_CNT_POS) -#define DMA2D_SRC_X_CNT_UMSK (~(((1U << DMA2D_SRC_X_CNT_LEN) - 1) << DMA2D_SRC_X_CNT_POS)) -#define DMA2D_SRC_Y_CNT DMA2D_SRC_Y_CNT -#define DMA2D_SRC_Y_CNT_POS (16U) -#define DMA2D_SRC_Y_CNT_LEN (16U) -#define DMA2D_SRC_Y_CNT_MSK (((1U << DMA2D_SRC_Y_CNT_LEN) - 1) << DMA2D_SRC_Y_CNT_POS) -#define DMA2D_SRC_Y_CNT_UMSK (~(((1U << DMA2D_SRC_Y_CNT_LEN) - 1) << DMA2D_SRC_Y_CNT_POS)) - -/* 0x114 : DMA2D_C0_SRC_XIC */ -#define DMA2D_C0_SRC_XIC_OFFSET (0x114) -#define DMA2D_SRC_X_INCR DMA2D_SRC_X_INCR -#define DMA2D_SRC_X_INCR_POS (0U) -#define DMA2D_SRC_X_INCR_LEN (32U) -#define DMA2D_SRC_X_INCR_MSK (((1U << DMA2D_SRC_X_INCR_LEN) - 1) << DMA2D_SRC_X_INCR_POS) -#define DMA2D_SRC_X_INCR_UMSK (~(((1U << DMA2D_SRC_X_INCR_LEN) - 1) << DMA2D_SRC_X_INCR_POS)) - -/* 0x118 : DMA2D_C0_SRC_YIC */ -#define DMA2D_C0_SRC_YIC_OFFSET (0x118) -#define DMA2D_SRC_Y_INCR DMA2D_SRC_Y_INCR -#define DMA2D_SRC_Y_INCR_POS (0U) -#define DMA2D_SRC_Y_INCR_LEN (32U) -#define DMA2D_SRC_Y_INCR_MSK (((1U << DMA2D_SRC_Y_INCR_LEN) - 1) << DMA2D_SRC_Y_INCR_POS) -#define DMA2D_SRC_Y_INCR_UMSK (~(((1U << DMA2D_SRC_Y_INCR_LEN) - 1) << DMA2D_SRC_Y_INCR_POS)) - -/* 0x11C : DMA2D_C0_DST_CNT */ -#define DMA2D_C0_DST_CNT_OFFSET (0x11C) -#define DMA2D_DST_X_CNT DMA2D_DST_X_CNT -#define DMA2D_DST_X_CNT_POS (0U) -#define DMA2D_DST_X_CNT_LEN (16U) -#define DMA2D_DST_X_CNT_MSK (((1U << DMA2D_DST_X_CNT_LEN) - 1) << DMA2D_DST_X_CNT_POS) -#define DMA2D_DST_X_CNT_UMSK (~(((1U << DMA2D_DST_X_CNT_LEN) - 1) << DMA2D_DST_X_CNT_POS)) - -/* 0x120 : DMA2D_C0_DST_XIC */ -#define DMA2D_C0_DST_XIC_OFFSET (0x120) -#define DMA2D_DST_X_INCR DMA2D_DST_X_INCR -#define DMA2D_DST_X_INCR_POS (0U) -#define DMA2D_DST_X_INCR_LEN (32U) -#define DMA2D_DST_X_INCR_MSK (((1U << DMA2D_DST_X_INCR_LEN) - 1) << DMA2D_DST_X_INCR_POS) -#define DMA2D_DST_X_INCR_UMSK (~(((1U << DMA2D_DST_X_INCR_LEN) - 1) << DMA2D_DST_X_INCR_POS)) - -/* 0x124 : DMA2D_C0_DST_YIC */ -#define DMA2D_C0_DST_YIC_OFFSET (0x124) -#define DMA2D_DST_Y_INCR DMA2D_DST_Y_INCR -#define DMA2D_DST_Y_INCR_POS (0U) -#define DMA2D_DST_Y_INCR_LEN (32U) -#define DMA2D_DST_Y_INCR_MSK (((1U << DMA2D_DST_Y_INCR_LEN) - 1) << DMA2D_DST_Y_INCR_POS) -#define DMA2D_DST_Y_INCR_UMSK (~(((1U << DMA2D_DST_Y_INCR_LEN) - 1) << DMA2D_DST_Y_INCR_POS)) - -/* 0x174 : DMA2D_C0_KEY */ -#define DMA2D_C0_KEY_OFFSET (0x174) -#define DMA2D_KEY0 DMA2D_KEY0 -#define DMA2D_KEY0_POS (0U) -#define DMA2D_KEY0_LEN (8U) -#define DMA2D_KEY0_MSK (((1U << DMA2D_KEY0_LEN) - 1) << DMA2D_KEY0_POS) -#define DMA2D_KEY0_UMSK (~(((1U << DMA2D_KEY0_LEN) - 1) << DMA2D_KEY0_POS)) -#define DMA2D_KEY1 DMA2D_KEY1 -#define DMA2D_KEY1_POS (8U) -#define DMA2D_KEY1_LEN (8U) -#define DMA2D_KEY1_MSK (((1U << DMA2D_KEY1_LEN) - 1) << DMA2D_KEY1_POS) -#define DMA2D_KEY1_UMSK (~(((1U << DMA2D_KEY1_LEN) - 1) << DMA2D_KEY1_POS)) -#define DMA2D_KEY2 DMA2D_KEY2 -#define DMA2D_KEY2_POS (16U) -#define DMA2D_KEY2_LEN (8U) -#define DMA2D_KEY2_MSK (((1U << DMA2D_KEY2_LEN) - 1) << DMA2D_KEY2_POS) -#define DMA2D_KEY2_UMSK (~(((1U << DMA2D_KEY2_LEN) - 1) << DMA2D_KEY2_POS)) -#define DMA2D_KEY3 DMA2D_KEY3 -#define DMA2D_KEY3_POS (24U) -#define DMA2D_KEY3_LEN (8U) -#define DMA2D_KEY3_MSK (((1U << DMA2D_KEY3_LEN) - 1) << DMA2D_KEY3_POS) -#define DMA2D_KEY3_UMSK (~(((1U << DMA2D_KEY3_LEN) - 1) << DMA2D_KEY3_POS)) - -/* 0x178 : DMA2D_C0_KEY_EN */ -#define DMA2D_C0_KEY_EN_OFFSET (0x178) -#define DMA2D_KEY_EN DMA2D_KEY_EN -#define DMA2D_KEY_EN_POS (0U) -#define DMA2D_KEY_EN_LEN (1U) -#define DMA2D_KEY_EN_MSK (((1U << DMA2D_KEY_EN_LEN) - 1) << DMA2D_KEY_EN_POS) -#define DMA2D_KEY_EN_UMSK (~(((1U << DMA2D_KEY_EN_LEN) - 1) << DMA2D_KEY_EN_POS)) -#define DMA2D_KEY_MODE DMA2D_KEY_MODE -#define DMA2D_KEY_MODE_POS (1U) -#define DMA2D_KEY_MODE_LEN (2U) -#define DMA2D_KEY_MODE_MSK (((1U << DMA2D_KEY_MODE_LEN) - 1) << DMA2D_KEY_MODE_POS) -#define DMA2D_KEY_MODE_UMSK (~(((1U << DMA2D_KEY_MODE_LEN) - 1) << DMA2D_KEY_MODE_POS)) -#define DMA2D_KEY_STRB DMA2D_KEY_STRB -#define DMA2D_KEY_STRB_POS (4U) -#define DMA2D_KEY_STRB_LEN (4U) -#define DMA2D_KEY_STRB_MSK (((1U << DMA2D_KEY_STRB_LEN) - 1) << DMA2D_KEY_STRB_POS) -#define DMA2D_KEY_STRB_UMSK (~(((1U << DMA2D_KEY_STRB_LEN) - 1) << DMA2D_KEY_STRB_POS)) - -/* 0x17C : DMA2D_C0_CFG */ -#define DMA2D_C0_CFG_OFFSET (0x17C) -#define DMA2D_CH_EN DMA2D_CH_EN -#define DMA2D_CH_EN_POS (0U) -#define DMA2D_CH_EN_LEN (1U) -#define DMA2D_CH_EN_MSK (((1U << DMA2D_CH_EN_LEN) - 1) << DMA2D_CH_EN_POS) -#define DMA2D_CH_EN_UMSK (~(((1U << DMA2D_CH_EN_LEN) - 1) << DMA2D_CH_EN_POS)) -#define DMA2D_SRCPERIPHERAL DMA2D_SRCPERIPHERAL -#define DMA2D_SRCPERIPHERAL_POS (1U) -#define DMA2D_SRCPERIPHERAL_LEN (5U) -#define DMA2D_SRCPERIPHERAL_MSK (((1U << DMA2D_SRCPERIPHERAL_LEN) - 1) << DMA2D_SRCPERIPHERAL_POS) -#define DMA2D_SRCPERIPHERAL_UMSK (~(((1U << DMA2D_SRCPERIPHERAL_LEN) - 1) << DMA2D_SRCPERIPHERAL_POS)) -#define DMA2D_DSTPERIPHERAL DMA2D_DSTPERIPHERAL -#define DMA2D_DSTPERIPHERAL_POS (6U) -#define DMA2D_DSTPERIPHERAL_LEN (5U) -#define DMA2D_DSTPERIPHERAL_MSK (((1U << DMA2D_DSTPERIPHERAL_LEN) - 1) << DMA2D_DSTPERIPHERAL_POS) -#define DMA2D_DSTPERIPHERAL_UMSK (~(((1U << DMA2D_DSTPERIPHERAL_LEN) - 1) << DMA2D_DSTPERIPHERAL_POS)) -#define DMA2D_FLOWCNTRL DMA2D_FLOWCNTRL -#define DMA2D_FLOWCNTRL_POS (11U) -#define DMA2D_FLOWCNTRL_LEN (3U) -#define DMA2D_FLOWCNTRL_MSK (((1U << DMA2D_FLOWCNTRL_LEN) - 1) << DMA2D_FLOWCNTRL_POS) -#define DMA2D_FLOWCNTRL_UMSK (~(((1U << DMA2D_FLOWCNTRL_LEN) - 1) << DMA2D_FLOWCNTRL_POS)) -#define DMA2D_AHB_B2B DMA2D_AHB_B2B -#define DMA2D_AHB_B2B_POS (14U) -#define DMA2D_AHB_B2B_LEN (1U) -#define DMA2D_AHB_B2B_MSK (((1U << DMA2D_AHB_B2B_LEN) - 1) << DMA2D_AHB_B2B_POS) -#define DMA2D_AHB_B2B_UMSK (~(((1U << DMA2D_AHB_B2B_LEN) - 1) << DMA2D_AHB_B2B_POS)) -#define DMA2D_FIFO_EMPTY DMA2D_FIFO_EMPTY -#define DMA2D_FIFO_EMPTY_POS (16U) -#define DMA2D_FIFO_EMPTY_LEN (1U) -#define DMA2D_FIFO_EMPTY_MSK (((1U << DMA2D_FIFO_EMPTY_LEN) - 1) << DMA2D_FIFO_EMPTY_POS) -#define DMA2D_FIFO_EMPTY_UMSK (~(((1U << DMA2D_FIFO_EMPTY_LEN) - 1) << DMA2D_FIFO_EMPTY_POS)) -#define DMA2D_LLICOUNTER DMA2D_LLICOUNTER -#define DMA2D_LLICOUNTER_POS (20U) -#define DMA2D_LLICOUNTER_LEN (10U) -#define DMA2D_LLICOUNTER_MSK (((1U << DMA2D_LLICOUNTER_LEN) - 1) << DMA2D_LLICOUNTER_POS) -#define DMA2D_LLICOUNTER_UMSK (~(((1U << DMA2D_LLICOUNTER_LEN) - 1) << DMA2D_LLICOUNTER_POS)) -#define DMA2D_REG_DMA_2D_EN DMA2D_REG_DMA_2D_EN -#define DMA2D_REG_DMA_2D_EN_POS (31U) -#define DMA2D_REG_DMA_2D_EN_LEN (1U) -#define DMA2D_REG_DMA_2D_EN_MSK (((1U << DMA2D_REG_DMA_2D_EN_LEN) - 1) << DMA2D_REG_DMA_2D_EN_POS) -#define DMA2D_REG_DMA_2D_EN_UMSK (~(((1U << DMA2D_REG_DMA_2D_EN_LEN) - 1) << DMA2D_REG_DMA_2D_EN_POS)) - -struct dma2d_reg { - /* 0x0 : DMA_IntStatus */ - union { - struct { - uint32_t IntStatus : 8; /* [ 7: 0], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_IntStatus; - - /* 0x4 : DMA_IntTCStatus */ - union { - struct { - uint32_t IntTCStatus : 8; /* [ 7: 0], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_IntTCStatus; - - /* 0x8 : DMA_IntTCClear */ - union { - struct { - uint32_t IntTCClear : 8; /* [ 7: 0], w1p, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_IntTCClear; - - /* 0xC : DMA_EnbldChns */ - union { - struct { - uint32_t EnabledChannels : 8; /* [ 7: 0], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_EnbldChns; - - /* 0x10 : DMA_Config */ - union { - struct { - uint32_t E : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_15 : 15; /* [15: 1], rsvd, 0x0 */ - uint32_t ChClkCG : 8; /* [23:16], r/w, 0xff */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_Config; - - /* 0x14 : DMA_Sync */ - union { - struct { - uint32_t DMA_Sync : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_Sync; - - /* 0x18 : DMA_SoftBReq */ - union { - struct { - uint32_t SoftBReq : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_SoftBReq; - - /* 0x1C : DMA_SoftLBReq */ - union { - struct { - uint32_t SoftLBReq : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_SoftLBReq; - - /* 0x20 : DMA_SoftSReq */ - union { - struct { - uint32_t SoftSReq : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_SoftSReq; - - /* 0x24 : DMA_SoftLSReq */ - union { - struct { - uint32_t SoftLSReq : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_SoftLSReq; - - /* 0x28 reserved */ - uint8_t RESERVED0x28[216]; - - /* 0x100 : DMA2D_C0SrcAddr */ - union { - struct { - uint32_t SrcAddr : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA2D_C0SrcAddr; - - /* 0x104 : DMA2D_C0DstAddr */ - union { - struct { - uint32_t DstAddr : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA2D_C0DstAddr; - - /* 0x108 : DMA2D_C0LLI */ - union { - struct { - uint32_t LLI_EN : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1 : 1; /* [ 1], rsvd, 0x0 */ - uint32_t LLI_ADDR : 30; /* [31: 2], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA2D_C0LLI; - - /* 0x10C : DMA2D_C0_BUS */ - union { - struct DMA2D_Control_Reg { - uint32_t TransferSize : 12; /* [11: 0], r/w, 0x0 */ - uint32_t SRC_BURST : 2; /* [13:12], r/w, 0x1 */ - uint32_t reserved_14 : 1; /* [ 14], rsvd, 0x0 */ - uint32_t DST_BURST : 2; /* [16:15], r/w, 0x1 */ - uint32_t reserved_17 : 1; /* [ 17], rsvd, 0x0 */ - uint32_t SRC_SIZE : 2; /* [19:18], r/w, 0x2 */ - uint32_t reserved_20 : 1; /* [ 20], rsvd, 0x0 */ - uint32_t DST_SIZE : 2; /* [22:21], r/w, 0x2 */ - uint32_t reserved_23_25 : 3; /* [25:23], rsvd, 0x0 */ - uint32_t SI : 1; /* [ 26], r/w, 0x1 */ - uint32_t DI : 1; /* [ 27], r/w, 0x1 */ - uint32_t Prot : 3; /* [30:28], r/w, 0x0 */ - uint32_t I : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA2D_C0_BUS; - - /* 0x110 : DMA2D_C0_SRC_CNT */ - union { - struct { - uint32_t SRC_X_CNT : 16; /* [15: 0], r/w, 0x0 */ - uint32_t SRC_Y_CNT : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA2D_C0_SRC_CNT; - - /* 0x114 : DMA2D_C0_SRC_XIC */ - union { - struct { - uint32_t SRC_X_INCR : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA2D_C0_SRC_XIC; - - /* 0x118 : DMA2D_C0_SRC_YIC */ - union { - struct { - uint32_t SRC_Y_INCR : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA2D_C0_SRC_YIC; - - /* 0x11C : DMA2D_C0_DST_CNT */ - union { - struct { - uint32_t DST_X_CNT : 16; /* [15: 0], r/w, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA2D_C0_DST_CNT; - - /* 0x120 : DMA2D_C0_DST_XIC */ - union { - struct { - uint32_t DST_X_INCR : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA2D_C0_DST_XIC; - - /* 0x124 : DMA2D_C0_DST_YIC */ - union { - struct { - uint32_t DST_Y_INCR : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA2D_C0_DST_YIC; - - /* 0x128 reserved */ - uint8_t RESERVED0x128[76]; - - /* 0x174 : DMA2D_C0_KEY */ - union { - struct { - uint32_t KEY0 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t KEY1 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t KEY2 : 8; /* [23:16], r/w, 0x0 */ - uint32_t KEY3 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA2D_C0_KEY; - - /* 0x178 : DMA2D_C0_KEY_EN */ - union { - struct { - uint32_t KEY_EN : 1; /* [ 0], r/w, 0x0 */ - uint32_t KEY_MODE : 2; /* [ 2: 1], r/w, 0x0 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t KEY_STRB : 4; /* [ 7: 4], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA2D_C0_KEY_EN; - - /* 0x17C : DMA2D_C0_CFG */ - union { - struct { - uint32_t CH_EN : 1; /* [ 0], r/w, 0x0 */ - uint32_t SrcPeripheral : 5; /* [ 5: 1], r/w, 0x0 */ - uint32_t DstPeripheral : 5; /* [10: 6], r/w, 0x0 */ - uint32_t FlowCntrl : 3; /* [13:11], r/w, 0x0 */ - uint32_t AHB_B2B : 1; /* [ 14], r/w, 0x0 */ - uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */ - uint32_t FIFO_Empty : 1; /* [ 16], r, 0x0 */ - uint32_t reserved_17_19 : 3; /* [19:17], rsvd, 0x0 */ - uint32_t LLICounter : 10; /* [29:20], r, 0x0 */ - uint32_t reserved_30 : 1; /* [ 30], rsvd, 0x0 */ - uint32_t reg_dma_2d_en : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA2D_C0_CFG; -}; - -typedef volatile struct dma2d_reg dma2d_reg_t; - -#endif /* __DMA2D_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dma_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dma_reg.h deleted file mode 100644 index 9c544259b5..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dma_reg.h +++ /dev/null @@ -1,2084 +0,0 @@ -/** - ****************************************************************************** - * @file dma_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __DMA_REG_H__ -#define __DMA_REG_H__ - -#include "bl808.h" - -/* 0x0 : DMA_IntStatus */ -#define DMA_INTSTATUS_OFFSET (0x0) -#define DMA_INTSTATUS DMA_INTSTATUS -#define DMA_INTSTATUS_POS (0U) -#define DMA_INTSTATUS_LEN (8U) -#define DMA_INTSTATUS_MSK (((1U << DMA_INTSTATUS_LEN) - 1) << DMA_INTSTATUS_POS) -#define DMA_INTSTATUS_UMSK (~(((1U << DMA_INTSTATUS_LEN) - 1) << DMA_INTSTATUS_POS)) - -/* 0x4 : DMA_IntTCStatus */ -#define DMA_INTTCSTATUS_OFFSET (0x4) -#define DMA_INTTCSTATUS DMA_INTTCSTATUS -#define DMA_INTTCSTATUS_POS (0U) -#define DMA_INTTCSTATUS_LEN (8U) -#define DMA_INTTCSTATUS_MSK (((1U << DMA_INTTCSTATUS_LEN) - 1) << DMA_INTTCSTATUS_POS) -#define DMA_INTTCSTATUS_UMSK (~(((1U << DMA_INTTCSTATUS_LEN) - 1) << DMA_INTTCSTATUS_POS)) - -/* 0x8 : DMA_IntTCClear */ -#define DMA_INTTCCLEAR_OFFSET (0x8) -#define DMA_INTTCCLEAR DMA_INTTCCLEAR -#define DMA_INTTCCLEAR_POS (0U) -#define DMA_INTTCCLEAR_LEN (8U) -#define DMA_INTTCCLEAR_MSK (((1U << DMA_INTTCCLEAR_LEN) - 1) << DMA_INTTCCLEAR_POS) -#define DMA_INTTCCLEAR_UMSK (~(((1U << DMA_INTTCCLEAR_LEN) - 1) << DMA_INTTCCLEAR_POS)) - -/* 0xC : DMA_IntErrorStatus */ -#define DMA_INTERRORSTATUS_OFFSET (0xC) -#define DMA_INTERRORSTATUS DMA_INTERRORSTATUS -#define DMA_INTERRORSTATUS_POS (0U) -#define DMA_INTERRORSTATUS_LEN (8U) -#define DMA_INTERRORSTATUS_MSK (((1U << DMA_INTERRORSTATUS_LEN) - 1) << DMA_INTERRORSTATUS_POS) -#define DMA_INTERRORSTATUS_UMSK (~(((1U << DMA_INTERRORSTATUS_LEN) - 1) << DMA_INTERRORSTATUS_POS)) - -/* 0x10 : DMA_IntErrClr */ -#define DMA_INTERRCLR_OFFSET (0x10) -#define DMA_INTERRCLR DMA_INTERRCLR -#define DMA_INTERRCLR_POS (0U) -#define DMA_INTERRCLR_LEN (8U) -#define DMA_INTERRCLR_MSK (((1U << DMA_INTERRCLR_LEN) - 1) << DMA_INTERRCLR_POS) -#define DMA_INTERRCLR_UMSK (~(((1U << DMA_INTERRCLR_LEN) - 1) << DMA_INTERRCLR_POS)) - -/* 0x14 : DMA_RawIntTCStatus */ -#define DMA_RAWINTTCSTATUS_OFFSET (0x14) -#define DMA_RAWINTTCSTATUS DMA_RAWINTTCSTATUS -#define DMA_RAWINTTCSTATUS_POS (0U) -#define DMA_RAWINTTCSTATUS_LEN (8U) -#define DMA_RAWINTTCSTATUS_MSK (((1U << DMA_RAWINTTCSTATUS_LEN) - 1) << DMA_RAWINTTCSTATUS_POS) -#define DMA_RAWINTTCSTATUS_UMSK (~(((1U << DMA_RAWINTTCSTATUS_LEN) - 1) << DMA_RAWINTTCSTATUS_POS)) - -/* 0x18 : DMA_RawIntErrorStatus */ -#define DMA_RAWINTERRORSTATUS_OFFSET (0x18) -#define DMA_RAWINTERRORSTATUS DMA_RAWINTERRORSTATUS -#define DMA_RAWINTERRORSTATUS_POS (0U) -#define DMA_RAWINTERRORSTATUS_LEN (8U) -#define DMA_RAWINTERRORSTATUS_MSK (((1U << DMA_RAWINTERRORSTATUS_LEN) - 1) << DMA_RAWINTERRORSTATUS_POS) -#define DMA_RAWINTERRORSTATUS_UMSK (~(((1U << DMA_RAWINTERRORSTATUS_LEN) - 1) << DMA_RAWINTERRORSTATUS_POS)) - -/* 0x1C : DMA_EnbldChns */ -#define DMA_ENBLDCHNS_OFFSET (0x1C) -#define DMA_ENABLEDCHANNELS DMA_ENABLEDCHANNELS -#define DMA_ENABLEDCHANNELS_POS (0U) -#define DMA_ENABLEDCHANNELS_LEN (8U) -#define DMA_ENABLEDCHANNELS_MSK (((1U << DMA_ENABLEDCHANNELS_LEN) - 1) << DMA_ENABLEDCHANNELS_POS) -#define DMA_ENABLEDCHANNELS_UMSK (~(((1U << DMA_ENABLEDCHANNELS_LEN) - 1) << DMA_ENABLEDCHANNELS_POS)) - -/* 0x20 : DMA_SoftBReq */ -#define DMA_SOFTBREQ_OFFSET (0x20) -#define DMA_SOFTBREQ DMA_SOFTBREQ -#define DMA_SOFTBREQ_POS (0U) -#define DMA_SOFTBREQ_LEN (32U) -#define DMA_SOFTBREQ_MSK (((1U << DMA_SOFTBREQ_LEN) - 1) << DMA_SOFTBREQ_POS) -#define DMA_SOFTBREQ_UMSK (~(((1U << DMA_SOFTBREQ_LEN) - 1) << DMA_SOFTBREQ_POS)) - -/* 0x24 : DMA_SoftSReq */ -#define DMA_SOFTSREQ_OFFSET (0x24) -#define DMA_SOFTSREQ DMA_SOFTSREQ -#define DMA_SOFTSREQ_POS (0U) -#define DMA_SOFTSREQ_LEN (32U) -#define DMA_SOFTSREQ_MSK (((1U << DMA_SOFTSREQ_LEN) - 1) << DMA_SOFTSREQ_POS) -#define DMA_SOFTSREQ_UMSK (~(((1U << DMA_SOFTSREQ_LEN) - 1) << DMA_SOFTSREQ_POS)) - -/* 0x28 : DMA_SoftLBReq */ -#define DMA_SOFTLBREQ_OFFSET (0x28) -#define DMA_SOFTLBREQ DMA_SOFTLBREQ -#define DMA_SOFTLBREQ_POS (0U) -#define DMA_SOFTLBREQ_LEN (32U) -#define DMA_SOFTLBREQ_MSK (((1U << DMA_SOFTLBREQ_LEN) - 1) << DMA_SOFTLBREQ_POS) -#define DMA_SOFTLBREQ_UMSK (~(((1U << DMA_SOFTLBREQ_LEN) - 1) << DMA_SOFTLBREQ_POS)) - -/* 0x2C : DMA_SoftLSReq */ -#define DMA_SOFTLSREQ_OFFSET (0x2C) -#define DMA_SOFTLSREQ DMA_SOFTLSREQ -#define DMA_SOFTLSREQ_POS (0U) -#define DMA_SOFTLSREQ_LEN (32U) -#define DMA_SOFTLSREQ_MSK (((1U << DMA_SOFTLSREQ_LEN) - 1) << DMA_SOFTLSREQ_POS) -#define DMA_SOFTLSREQ_UMSK (~(((1U << DMA_SOFTLSREQ_LEN) - 1) << DMA_SOFTLSREQ_POS)) - -/* 0x30 : DMA_Top_Config */ -#define DMA_TOP_CONFIG_OFFSET (0x30) -#define DMA_E DMA_E -#define DMA_E_POS (0U) -#define DMA_E_LEN (1U) -#define DMA_E_MSK (((1U << DMA_E_LEN) - 1) << DMA_E_POS) -#define DMA_E_UMSK (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS)) -#define DMA_M DMA_M -#define DMA_M_POS (1U) -#define DMA_M_LEN (1U) -#define DMA_M_MSK (((1U << DMA_M_LEN) - 1) << DMA_M_POS) -#define DMA_M_UMSK (~(((1U << DMA_M_LEN) - 1) << DMA_M_POS)) - -/* 0x34 : DMA_Sync */ -#define DMA_SYNC_OFFSET (0x34) -#define DMA_SYNC DMA_SYNC -#define DMA_SYNC_POS (0U) -#define DMA_SYNC_LEN (32U) -#define DMA_SYNC_MSK (((1U << DMA_SYNC_LEN) - 1) << DMA_SYNC_POS) -#define DMA_SYNC_UMSK (~(((1U << DMA_SYNC_LEN) - 1) << DMA_SYNC_POS)) - -/* 0x100 : DMA_C0SrcAddr */ -#define DMA_C0SRCADDR_OFFSET (0x100) -#define DMA_SRCADDR DMA_SRCADDR -#define DMA_SRCADDR_POS (0U) -#define DMA_SRCADDR_LEN (32U) -#define DMA_SRCADDR_MSK (((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS) -#define DMA_SRCADDR_UMSK (~(((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS)) - -/* 0x104 : DMA_C0DstAddr */ -#define DMA_C0DSTADDR_OFFSET (0x104) -#define DMA_DSTADDR DMA_DSTADDR -#define DMA_DSTADDR_POS (0U) -#define DMA_DSTADDR_LEN (32U) -#define DMA_DSTADDR_MSK (((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS) -#define DMA_DSTADDR_UMSK (~(((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS)) - -/* 0x108 : DMA_C0LLI */ -#define DMA_C0LLI_OFFSET (0x108) -#define DMA_LLI DMA_LLI -#define DMA_LLI_POS (0U) -#define DMA_LLI_LEN (32U) -#define DMA_LLI_MSK (((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS) -#define DMA_LLI_UMSK (~(((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS)) - -/* 0x10C : DMA_C0Control */ -#define DMA_C0CONTROL_OFFSET (0x10C) -#define DMA_TRANSFERSIZE DMA_TRANSFERSIZE -#define DMA_TRANSFERSIZE_POS (0U) -#define DMA_TRANSFERSIZE_LEN (12U) -#define DMA_TRANSFERSIZE_MSK (((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS) -#define DMA_TRANSFERSIZE_UMSK (~(((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS)) -#define DMA_SBSIZE DMA_SBSIZE -#define DMA_SBSIZE_POS (12U) -#define DMA_SBSIZE_LEN (2U) -#define DMA_SBSIZE_MSK (((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS) -#define DMA_SBSIZE_UMSK (~(((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS)) -#define DMA_DST_MIN_MODE DMA_DST_MIN_MODE -#define DMA_DST_MIN_MODE_POS (14U) -#define DMA_DST_MIN_MODE_LEN (1U) -#define DMA_DST_MIN_MODE_MSK (((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS) -#define DMA_DST_MIN_MODE_UMSK (~(((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS)) -#define DMA_DBSIZE DMA_DBSIZE -#define DMA_DBSIZE_POS (15U) -#define DMA_DBSIZE_LEN (2U) -#define DMA_DBSIZE_MSK (((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS) -#define DMA_DBSIZE_UMSK (~(((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS)) -#define DMA_DST_ADD_MODE DMA_DST_ADD_MODE -#define DMA_DST_ADD_MODE_POS (17U) -#define DMA_DST_ADD_MODE_LEN (1U) -#define DMA_DST_ADD_MODE_MSK (((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS) -#define DMA_DST_ADD_MODE_UMSK (~(((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS)) -#define DMA_SWIDTH DMA_SWIDTH -#define DMA_SWIDTH_POS (18U) -#define DMA_SWIDTH_LEN (2U) -#define DMA_SWIDTH_MSK (((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS) -#define DMA_SWIDTH_UMSK (~(((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS)) -#define DMA_DWIDTH DMA_DWIDTH -#define DMA_DWIDTH_POS (21U) -#define DMA_DWIDTH_LEN (2U) -#define DMA_DWIDTH_MSK (((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS) -#define DMA_DWIDTH_UMSK (~(((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS)) -#define DMA_FIX_CNT DMA_FIX_CNT -#define DMA_FIX_CNT_POS (23U) -#define DMA_FIX_CNT_LEN (3U) -#define DMA_FIX_CNT_MSK (((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS) -#define DMA_FIX_CNT_UMSK (~(((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS)) -#define DMA_SI DMA_SI -#define DMA_SI_POS (26U) -#define DMA_SI_LEN (1U) -#define DMA_SI_MSK (((1U << DMA_SI_LEN) - 1) << DMA_SI_POS) -#define DMA_SI_UMSK (~(((1U << DMA_SI_LEN) - 1) << DMA_SI_POS)) -#define DMA_DI DMA_DI -#define DMA_DI_POS (27U) -#define DMA_DI_LEN (1U) -#define DMA_DI_MSK (((1U << DMA_DI_LEN) - 1) << DMA_DI_POS) -#define DMA_DI_UMSK (~(((1U << DMA_DI_LEN) - 1) << DMA_DI_POS)) -#define DMA_PROT DMA_PROT -#define DMA_PROT_POS (28U) -#define DMA_PROT_LEN (3U) -#define DMA_PROT_MSK (((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS) -#define DMA_PROT_UMSK (~(((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS)) -#define DMA_I DMA_I -#define DMA_I_POS (31U) -#define DMA_I_LEN (1U) -#define DMA_I_MSK (((1U << DMA_I_LEN) - 1) << DMA_I_POS) -#define DMA_I_UMSK (~(((1U << DMA_I_LEN) - 1) << DMA_I_POS)) - -/* 0x110 : DMA_C0Config */ -#define DMA_C0CONFIG_OFFSET (0x110) -#define DMA_E DMA_E -#define DMA_E_POS (0U) -#define DMA_E_LEN (1U) -#define DMA_E_MSK (((1U << DMA_E_LEN) - 1) << DMA_E_POS) -#define DMA_E_UMSK (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS)) -#define DMA_SRCPERIPHERAL DMA_SRCPERIPHERAL -#define DMA_SRCPERIPHERAL_POS (1U) -#define DMA_SRCPERIPHERAL_LEN (5U) -#define DMA_SRCPERIPHERAL_MSK (((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS) -#define DMA_SRCPERIPHERAL_UMSK (~(((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS)) -#define DMA_DSTPERIPHERAL DMA_DSTPERIPHERAL -#define DMA_DSTPERIPHERAL_POS (6U) -#define DMA_DSTPERIPHERAL_LEN (5U) -#define DMA_DSTPERIPHERAL_MSK (((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS) -#define DMA_DSTPERIPHERAL_UMSK (~(((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS)) -#define DMA_FLOWCNTRL DMA_FLOWCNTRL -#define DMA_FLOWCNTRL_POS (11U) -#define DMA_FLOWCNTRL_LEN (3U) -#define DMA_FLOWCNTRL_MSK (((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS) -#define DMA_FLOWCNTRL_UMSK (~(((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS)) -#define DMA_IE DMA_IE -#define DMA_IE_POS (14U) -#define DMA_IE_LEN (1U) -#define DMA_IE_MSK (((1U << DMA_IE_LEN) - 1) << DMA_IE_POS) -#define DMA_IE_UMSK (~(((1U << DMA_IE_LEN) - 1) << DMA_IE_POS)) -#define DMA_ITC DMA_ITC -#define DMA_ITC_POS (15U) -#define DMA_ITC_LEN (1U) -#define DMA_ITC_MSK (((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS) -#define DMA_ITC_UMSK (~(((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS)) -#define DMA_L DMA_L -#define DMA_L_POS (16U) -#define DMA_L_LEN (1U) -#define DMA_L_MSK (((1U << DMA_L_LEN) - 1) << DMA_L_POS) -#define DMA_L_UMSK (~(((1U << DMA_L_LEN) - 1) << DMA_L_POS)) -#define DMA_A DMA_A -#define DMA_A_POS (17U) -#define DMA_A_LEN (1U) -#define DMA_A_MSK (((1U << DMA_A_LEN) - 1) << DMA_A_POS) -#define DMA_A_UMSK (~(((1U << DMA_A_LEN) - 1) << DMA_A_POS)) -#define DMA_H DMA_H -#define DMA_H_POS (18U) -#define DMA_H_LEN (1U) -#define DMA_H_MSK (((1U << DMA_H_LEN) - 1) << DMA_H_POS) -#define DMA_H_UMSK (~(((1U << DMA_H_LEN) - 1) << DMA_H_POS)) -#define DMA_LLICOUNTER DMA_LLICOUNTER -#define DMA_LLICOUNTER_POS (20U) -#define DMA_LLICOUNTER_LEN (10U) -#define DMA_LLICOUNTER_MSK (((1U << DMA_LLICOUNTER_LEN) - 1) << DMA_LLICOUNTER_POS) -#define DMA_LLICOUNTER_UMSK (~(((1U << DMA_LLICOUNTER_LEN) - 1) << DMA_LLICOUNTER_POS)) - -/* 0x11C : DMA_C0RSVD */ -#define DMA_C0RSVD_OFFSET (0x11C) -#define DMA_DSTREMNSGLE DMA_DSTREMNSGLE -#define DMA_DSTREMNSGLE_POS (3U) -#define DMA_DSTREMNSGLE_LEN (1U) -#define DMA_DSTREMNSGLE_MSK (((1U << DMA_DSTREMNSGLE_LEN) - 1) << DMA_DSTREMNSGLE_POS) -#define DMA_DSTREMNSGLE_UMSK (~(((1U << DMA_DSTREMNSGLE_LEN) - 1) << DMA_DSTREMNSGLE_POS)) -#define DMA_SRCREMNSGLE DMA_SRCREMNSGLE -#define DMA_SRCREMNSGLE_POS (4U) -#define DMA_SRCREMNSGLE_LEN (1U) -#define DMA_SRCREMNSGLE_MSK (((1U << DMA_SRCREMNSGLE_LEN) - 1) << DMA_SRCREMNSGLE_POS) -#define DMA_SRCREMNSGLE_UMSK (~(((1U << DMA_SRCREMNSGLE_LEN) - 1) << DMA_SRCREMNSGLE_POS)) - -/* 0x200 : DMA_C1SrcAddr */ -#define DMA_C1SRCADDR_OFFSET (0x200) -#define DMA_SRCADDR DMA_SRCADDR -#define DMA_SRCADDR_POS (0U) -#define DMA_SRCADDR_LEN (32U) -#define DMA_SRCADDR_MSK (((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS) -#define DMA_SRCADDR_UMSK (~(((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS)) - -/* 0x204 : DMA_C1DstAddr */ -#define DMA_C1DSTADDR_OFFSET (0x204) -#define DMA_DSTADDR DMA_DSTADDR -#define DMA_DSTADDR_POS (0U) -#define DMA_DSTADDR_LEN (32U) -#define DMA_DSTADDR_MSK (((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS) -#define DMA_DSTADDR_UMSK (~(((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS)) - -/* 0x208 : DMA_C1LLI */ -#define DMA_C1LLI_OFFSET (0x208) -#define DMA_LLI DMA_LLI -#define DMA_LLI_POS (0U) -#define DMA_LLI_LEN (32U) -#define DMA_LLI_MSK (((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS) -#define DMA_LLI_UMSK (~(((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS)) - -/* 0x20C : DMA_C1Control */ -#define DMA_C1CONTROL_OFFSET (0x20C) -#define DMA_TRANSFERSIZE DMA_TRANSFERSIZE -#define DMA_TRANSFERSIZE_POS (0U) -#define DMA_TRANSFERSIZE_LEN (12U) -#define DMA_TRANSFERSIZE_MSK (((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS) -#define DMA_TRANSFERSIZE_UMSK (~(((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS)) -#define DMA_SBSIZE DMA_SBSIZE -#define DMA_SBSIZE_POS (12U) -#define DMA_SBSIZE_LEN (2U) -#define DMA_SBSIZE_MSK (((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS) -#define DMA_SBSIZE_UMSK (~(((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS)) -#define DMA_DST_MIN_MODE DMA_DST_MIN_MODE -#define DMA_DST_MIN_MODE_POS (14U) -#define DMA_DST_MIN_MODE_LEN (1U) -#define DMA_DST_MIN_MODE_MSK (((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS) -#define DMA_DST_MIN_MODE_UMSK (~(((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS)) -#define DMA_DBSIZE DMA_DBSIZE -#define DMA_DBSIZE_POS (15U) -#define DMA_DBSIZE_LEN (2U) -#define DMA_DBSIZE_MSK (((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS) -#define DMA_DBSIZE_UMSK (~(((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS)) -#define DMA_DST_ADD_MODE DMA_DST_ADD_MODE -#define DMA_DST_ADD_MODE_POS (17U) -#define DMA_DST_ADD_MODE_LEN (1U) -#define DMA_DST_ADD_MODE_MSK (((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS) -#define DMA_DST_ADD_MODE_UMSK (~(((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS)) -#define DMA_SWIDTH DMA_SWIDTH -#define DMA_SWIDTH_POS (18U) -#define DMA_SWIDTH_LEN (2U) -#define DMA_SWIDTH_MSK (((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS) -#define DMA_SWIDTH_UMSK (~(((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS)) -#define DMA_DWIDTH DMA_DWIDTH -#define DMA_DWIDTH_POS (21U) -#define DMA_DWIDTH_LEN (2U) -#define DMA_DWIDTH_MSK (((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS) -#define DMA_DWIDTH_UMSK (~(((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS)) -#define DMA_FIX_CNT DMA_FIX_CNT -#define DMA_FIX_CNT_POS (23U) -#define DMA_FIX_CNT_LEN (3U) -#define DMA_FIX_CNT_MSK (((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS) -#define DMA_FIX_CNT_UMSK (~(((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS)) -#define DMA_SI DMA_SI -#define DMA_SI_POS (26U) -#define DMA_SI_LEN (1U) -#define DMA_SI_MSK (((1U << DMA_SI_LEN) - 1) << DMA_SI_POS) -#define DMA_SI_UMSK (~(((1U << DMA_SI_LEN) - 1) << DMA_SI_POS)) -#define DMA_DI DMA_DI -#define DMA_DI_POS (27U) -#define DMA_DI_LEN (1U) -#define DMA_DI_MSK (((1U << DMA_DI_LEN) - 1) << DMA_DI_POS) -#define DMA_DI_UMSK (~(((1U << DMA_DI_LEN) - 1) << DMA_DI_POS)) -#define DMA_PROT DMA_PROT -#define DMA_PROT_POS (28U) -#define DMA_PROT_LEN (3U) -#define DMA_PROT_MSK (((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS) -#define DMA_PROT_UMSK (~(((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS)) -#define DMA_I DMA_I -#define DMA_I_POS (31U) -#define DMA_I_LEN (1U) -#define DMA_I_MSK (((1U << DMA_I_LEN) - 1) << DMA_I_POS) -#define DMA_I_UMSK (~(((1U << DMA_I_LEN) - 1) << DMA_I_POS)) - -/* 0x210 : DMA_C1Config */ -#define DMA_C1CONFIG_OFFSET (0x210) -#define DMA_E DMA_E -#define DMA_E_POS (0U) -#define DMA_E_LEN (1U) -#define DMA_E_MSK (((1U << DMA_E_LEN) - 1) << DMA_E_POS) -#define DMA_E_UMSK (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS)) -#define DMA_SRCPERIPHERAL DMA_SRCPERIPHERAL -#define DMA_SRCPERIPHERAL_POS (1U) -#define DMA_SRCPERIPHERAL_LEN (5U) -#define DMA_SRCPERIPHERAL_MSK (((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS) -#define DMA_SRCPERIPHERAL_UMSK (~(((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS)) -#define DMA_DSTPERIPHERAL DMA_DSTPERIPHERAL -#define DMA_DSTPERIPHERAL_POS (6U) -#define DMA_DSTPERIPHERAL_LEN (5U) -#define DMA_DSTPERIPHERAL_MSK (((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS) -#define DMA_DSTPERIPHERAL_UMSK (~(((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS)) -#define DMA_FLOWCNTRL DMA_FLOWCNTRL -#define DMA_FLOWCNTRL_POS (11U) -#define DMA_FLOWCNTRL_LEN (3U) -#define DMA_FLOWCNTRL_MSK (((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS) -#define DMA_FLOWCNTRL_UMSK (~(((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS)) -#define DMA_IE DMA_IE -#define DMA_IE_POS (14U) -#define DMA_IE_LEN (1U) -#define DMA_IE_MSK (((1U << DMA_IE_LEN) - 1) << DMA_IE_POS) -#define DMA_IE_UMSK (~(((1U << DMA_IE_LEN) - 1) << DMA_IE_POS)) -#define DMA_ITC DMA_ITC -#define DMA_ITC_POS (15U) -#define DMA_ITC_LEN (1U) -#define DMA_ITC_MSK (((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS) -#define DMA_ITC_UMSK (~(((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS)) -#define DMA_L DMA_L -#define DMA_L_POS (16U) -#define DMA_L_LEN (1U) -#define DMA_L_MSK (((1U << DMA_L_LEN) - 1) << DMA_L_POS) -#define DMA_L_UMSK (~(((1U << DMA_L_LEN) - 1) << DMA_L_POS)) -#define DMA_A DMA_A -#define DMA_A_POS (17U) -#define DMA_A_LEN (1U) -#define DMA_A_MSK (((1U << DMA_A_LEN) - 1) << DMA_A_POS) -#define DMA_A_UMSK (~(((1U << DMA_A_LEN) - 1) << DMA_A_POS)) -#define DMA_H DMA_H -#define DMA_H_POS (18U) -#define DMA_H_LEN (1U) -#define DMA_H_MSK (((1U << DMA_H_LEN) - 1) << DMA_H_POS) -#define DMA_H_UMSK (~(((1U << DMA_H_LEN) - 1) << DMA_H_POS)) - -/* 0x21C : DMA_C1RSVD */ -#define DMA_C1RSVD_OFFSET (0x21C) -#define DMA_DSTREMNSGLE DMA_DSTREMNSGLE -#define DMA_DSTREMNSGLE_POS (3U) -#define DMA_DSTREMNSGLE_LEN (1U) -#define DMA_DSTREMNSGLE_MSK (((1U << DMA_DSTREMNSGLE_LEN) - 1) << DMA_DSTREMNSGLE_POS) -#define DMA_DSTREMNSGLE_UMSK (~(((1U << DMA_DSTREMNSGLE_LEN) - 1) << DMA_DSTREMNSGLE_POS)) -#define DMA_SRCREMNSGLE DMA_SRCREMNSGLE -#define DMA_SRCREMNSGLE_POS (4U) -#define DMA_SRCREMNSGLE_LEN (1U) -#define DMA_SRCREMNSGLE_MSK (((1U << DMA_SRCREMNSGLE_LEN) - 1) << DMA_SRCREMNSGLE_POS) -#define DMA_SRCREMNSGLE_UMSK (~(((1U << DMA_SRCREMNSGLE_LEN) - 1) << DMA_SRCREMNSGLE_POS)) - -/* 0x300 : DMA_C2SrcAddr */ -#define DMA_C2SRCADDR_OFFSET (0x300) -#define DMA_SRCADDR DMA_SRCADDR -#define DMA_SRCADDR_POS (0U) -#define DMA_SRCADDR_LEN (32U) -#define DMA_SRCADDR_MSK (((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS) -#define DMA_SRCADDR_UMSK (~(((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS)) - -/* 0x304 : DMA_C2DstAddr */ -#define DMA_C2DSTADDR_OFFSET (0x304) -#define DMA_DSTADDR DMA_DSTADDR -#define DMA_DSTADDR_POS (0U) -#define DMA_DSTADDR_LEN (32U) -#define DMA_DSTADDR_MSK (((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS) -#define DMA_DSTADDR_UMSK (~(((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS)) - -/* 0x308 : DMA_C2LLI */ -#define DMA_C2LLI_OFFSET (0x308) -#define DMA_LLI DMA_LLI -#define DMA_LLI_POS (0U) -#define DMA_LLI_LEN (32U) -#define DMA_LLI_MSK (((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS) -#define DMA_LLI_UMSK (~(((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS)) - -/* 0x30C : DMA_C2Control */ -#define DMA_C2CONTROL_OFFSET (0x30C) -#define DMA_TRANSFERSIZE DMA_TRANSFERSIZE -#define DMA_TRANSFERSIZE_POS (0U) -#define DMA_TRANSFERSIZE_LEN (12U) -#define DMA_TRANSFERSIZE_MSK (((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS) -#define DMA_TRANSFERSIZE_UMSK (~(((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS)) -#define DMA_SBSIZE DMA_SBSIZE -#define DMA_SBSIZE_POS (12U) -#define DMA_SBSIZE_LEN (2U) -#define DMA_SBSIZE_MSK (((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS) -#define DMA_SBSIZE_UMSK (~(((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS)) -#define DMA_DST_MIN_MODE DMA_DST_MIN_MODE -#define DMA_DST_MIN_MODE_POS (14U) -#define DMA_DST_MIN_MODE_LEN (1U) -#define DMA_DST_MIN_MODE_MSK (((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS) -#define DMA_DST_MIN_MODE_UMSK (~(((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS)) -#define DMA_DBSIZE DMA_DBSIZE -#define DMA_DBSIZE_POS (15U) -#define DMA_DBSIZE_LEN (2U) -#define DMA_DBSIZE_MSK (((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS) -#define DMA_DBSIZE_UMSK (~(((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS)) -#define DMA_DST_ADD_MODE DMA_DST_ADD_MODE -#define DMA_DST_ADD_MODE_POS (17U) -#define DMA_DST_ADD_MODE_LEN (1U) -#define DMA_DST_ADD_MODE_MSK (((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS) -#define DMA_DST_ADD_MODE_UMSK (~(((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS)) -#define DMA_SWIDTH DMA_SWIDTH -#define DMA_SWIDTH_POS (18U) -#define DMA_SWIDTH_LEN (2U) -#define DMA_SWIDTH_MSK (((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS) -#define DMA_SWIDTH_UMSK (~(((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS)) -#define DMA_DWIDTH DMA_DWIDTH -#define DMA_DWIDTH_POS (21U) -#define DMA_DWIDTH_LEN (2U) -#define DMA_DWIDTH_MSK (((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS) -#define DMA_DWIDTH_UMSK (~(((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS)) -#define DMA_FIX_CNT DMA_FIX_CNT -#define DMA_FIX_CNT_POS (23U) -#define DMA_FIX_CNT_LEN (3U) -#define DMA_FIX_CNT_MSK (((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS) -#define DMA_FIX_CNT_UMSK (~(((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS)) -#define DMA_SI DMA_SI -#define DMA_SI_POS (26U) -#define DMA_SI_LEN (1U) -#define DMA_SI_MSK (((1U << DMA_SI_LEN) - 1) << DMA_SI_POS) -#define DMA_SI_UMSK (~(((1U << DMA_SI_LEN) - 1) << DMA_SI_POS)) -#define DMA_DI DMA_DI -#define DMA_DI_POS (27U) -#define DMA_DI_LEN (1U) -#define DMA_DI_MSK (((1U << DMA_DI_LEN) - 1) << DMA_DI_POS) -#define DMA_DI_UMSK (~(((1U << DMA_DI_LEN) - 1) << DMA_DI_POS)) -#define DMA_PROT DMA_PROT -#define DMA_PROT_POS (28U) -#define DMA_PROT_LEN (3U) -#define DMA_PROT_MSK (((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS) -#define DMA_PROT_UMSK (~(((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS)) -#define DMA_I DMA_I -#define DMA_I_POS (31U) -#define DMA_I_LEN (1U) -#define DMA_I_MSK (((1U << DMA_I_LEN) - 1) << DMA_I_POS) -#define DMA_I_UMSK (~(((1U << DMA_I_LEN) - 1) << DMA_I_POS)) - -/* 0x310 : DMA_C3Config */ -#define DMA_C3CONFIG_OFFSET (0x310) -#define DMA_E DMA_E -#define DMA_E_POS (0U) -#define DMA_E_LEN (1U) -#define DMA_E_MSK (((1U << DMA_E_LEN) - 1) << DMA_E_POS) -#define DMA_E_UMSK (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS)) -#define DMA_SRCPERIPHERAL DMA_SRCPERIPHERAL -#define DMA_SRCPERIPHERAL_POS (1U) -#define DMA_SRCPERIPHERAL_LEN (5U) -#define DMA_SRCPERIPHERAL_MSK (((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS) -#define DMA_SRCPERIPHERAL_UMSK (~(((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS)) -#define DMA_DSTPERIPHERAL DMA_DSTPERIPHERAL -#define DMA_DSTPERIPHERAL_POS (6U) -#define DMA_DSTPERIPHERAL_LEN (5U) -#define DMA_DSTPERIPHERAL_MSK (((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS) -#define DMA_DSTPERIPHERAL_UMSK (~(((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS)) -#define DMA_FLOWCNTRL DMA_FLOWCNTRL -#define DMA_FLOWCNTRL_POS (11U) -#define DMA_FLOWCNTRL_LEN (3U) -#define DMA_FLOWCNTRL_MSK (((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS) -#define DMA_FLOWCNTRL_UMSK (~(((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS)) -#define DMA_IE DMA_IE -#define DMA_IE_POS (14U) -#define DMA_IE_LEN (1U) -#define DMA_IE_MSK (((1U << DMA_IE_LEN) - 1) << DMA_IE_POS) -#define DMA_IE_UMSK (~(((1U << DMA_IE_LEN) - 1) << DMA_IE_POS)) -#define DMA_ITC DMA_ITC -#define DMA_ITC_POS (15U) -#define DMA_ITC_LEN (1U) -#define DMA_ITC_MSK (((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS) -#define DMA_ITC_UMSK (~(((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS)) -#define DMA_L DMA_L -#define DMA_L_POS (16U) -#define DMA_L_LEN (1U) -#define DMA_L_MSK (((1U << DMA_L_LEN) - 1) << DMA_L_POS) -#define DMA_L_UMSK (~(((1U << DMA_L_LEN) - 1) << DMA_L_POS)) -#define DMA_A DMA_A -#define DMA_A_POS (17U) -#define DMA_A_LEN (1U) -#define DMA_A_MSK (((1U << DMA_A_LEN) - 1) << DMA_A_POS) -#define DMA_A_UMSK (~(((1U << DMA_A_LEN) - 1) << DMA_A_POS)) -#define DMA_H DMA_H -#define DMA_H_POS (18U) -#define DMA_H_LEN (1U) -#define DMA_H_MSK (((1U << DMA_H_LEN) - 1) << DMA_H_POS) -#define DMA_H_UMSK (~(((1U << DMA_H_LEN) - 1) << DMA_H_POS)) - -/* 0x31C : DMA_C3RSVD */ -#define DMA_C3RSVD_OFFSET (0x31C) -#define DMA_DSTREMNSGLE DMA_DSTREMNSGLE -#define DMA_DSTREMNSGLE_POS (3U) -#define DMA_DSTREMNSGLE_LEN (1U) -#define DMA_DSTREMNSGLE_MSK (((1U << DMA_DSTREMNSGLE_LEN) - 1) << DMA_DSTREMNSGLE_POS) -#define DMA_DSTREMNSGLE_UMSK (~(((1U << DMA_DSTREMNSGLE_LEN) - 1) << DMA_DSTREMNSGLE_POS)) -#define DMA_SRCREMNSGLE DMA_SRCREMNSGLE -#define DMA_SRCREMNSGLE_POS (4U) -#define DMA_SRCREMNSGLE_LEN (1U) -#define DMA_SRCREMNSGLE_MSK (((1U << DMA_SRCREMNSGLE_LEN) - 1) << DMA_SRCREMNSGLE_POS) -#define DMA_SRCREMNSGLE_UMSK (~(((1U << DMA_SRCREMNSGLE_LEN) - 1) << DMA_SRCREMNSGLE_POS)) - -/* 0x500 : DMA_C4SrcAddr */ -#define DMA_C4SRCADDR_OFFSET (0x500) -#define DMA_SRCADDR DMA_SRCADDR -#define DMA_SRCADDR_POS (0U) -#define DMA_SRCADDR_LEN (32U) -#define DMA_SRCADDR_MSK (((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS) -#define DMA_SRCADDR_UMSK (~(((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS)) - -/* 0x504 : DMA_C4DstAddr */ -#define DMA_C4DSTADDR_OFFSET (0x504) -#define DMA_DSTADDR DMA_DSTADDR -#define DMA_DSTADDR_POS (0U) -#define DMA_DSTADDR_LEN (32U) -#define DMA_DSTADDR_MSK (((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS) -#define DMA_DSTADDR_UMSK (~(((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS)) - -/* 0x508 : DMA_C4LLI */ -#define DMA_C4LLI_OFFSET (0x508) -#define DMA_LLI DMA_LLI -#define DMA_LLI_POS (0U) -#define DMA_LLI_LEN (32U) -#define DMA_LLI_MSK (((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS) -#define DMA_LLI_UMSK (~(((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS)) - -/* 0x50C : DMA_C4Control */ -#define DMA_C4CONTROL_OFFSET (0x50C) -#define DMA_TRANSFERSIZE DMA_TRANSFERSIZE -#define DMA_TRANSFERSIZE_POS (0U) -#define DMA_TRANSFERSIZE_LEN (12U) -#define DMA_TRANSFERSIZE_MSK (((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS) -#define DMA_TRANSFERSIZE_UMSK (~(((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS)) -#define DMA_SBSIZE DMA_SBSIZE -#define DMA_SBSIZE_POS (12U) -#define DMA_SBSIZE_LEN (2U) -#define DMA_SBSIZE_MSK (((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS) -#define DMA_SBSIZE_UMSK (~(((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS)) -#define DMA_DST_MIN_MODE DMA_DST_MIN_MODE -#define DMA_DST_MIN_MODE_POS (14U) -#define DMA_DST_MIN_MODE_LEN (1U) -#define DMA_DST_MIN_MODE_MSK (((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS) -#define DMA_DST_MIN_MODE_UMSK (~(((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS)) -#define DMA_DBSIZE DMA_DBSIZE -#define DMA_DBSIZE_POS (15U) -#define DMA_DBSIZE_LEN (2U) -#define DMA_DBSIZE_MSK (((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS) -#define DMA_DBSIZE_UMSK (~(((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS)) -#define DMA_DST_ADD_MODE DMA_DST_ADD_MODE -#define DMA_DST_ADD_MODE_POS (17U) -#define DMA_DST_ADD_MODE_LEN (1U) -#define DMA_DST_ADD_MODE_MSK (((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS) -#define DMA_DST_ADD_MODE_UMSK (~(((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS)) -#define DMA_SWIDTH DMA_SWIDTH -#define DMA_SWIDTH_POS (18U) -#define DMA_SWIDTH_LEN (2U) -#define DMA_SWIDTH_MSK (((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS) -#define DMA_SWIDTH_UMSK (~(((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS)) -#define DMA_DWIDTH DMA_DWIDTH -#define DMA_DWIDTH_POS (21U) -#define DMA_DWIDTH_LEN (2U) -#define DMA_DWIDTH_MSK (((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS) -#define DMA_DWIDTH_UMSK (~(((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS)) -#define DMA_FIX_CNT DMA_FIX_CNT -#define DMA_FIX_CNT_POS (23U) -#define DMA_FIX_CNT_LEN (3U) -#define DMA_FIX_CNT_MSK (((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS) -#define DMA_FIX_CNT_UMSK (~(((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS)) -#define DMA_SI DMA_SI -#define DMA_SI_POS (26U) -#define DMA_SI_LEN (1U) -#define DMA_SI_MSK (((1U << DMA_SI_LEN) - 1) << DMA_SI_POS) -#define DMA_SI_UMSK (~(((1U << DMA_SI_LEN) - 1) << DMA_SI_POS)) -#define DMA_DI DMA_DI -#define DMA_DI_POS (27U) -#define DMA_DI_LEN (1U) -#define DMA_DI_MSK (((1U << DMA_DI_LEN) - 1) << DMA_DI_POS) -#define DMA_DI_UMSK (~(((1U << DMA_DI_LEN) - 1) << DMA_DI_POS)) -#define DMA_PROT DMA_PROT -#define DMA_PROT_POS (28U) -#define DMA_PROT_LEN (3U) -#define DMA_PROT_MSK (((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS) -#define DMA_PROT_UMSK (~(((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS)) -#define DMA_I DMA_I -#define DMA_I_POS (31U) -#define DMA_I_LEN (1U) -#define DMA_I_MSK (((1U << DMA_I_LEN) - 1) << DMA_I_POS) -#define DMA_I_UMSK (~(((1U << DMA_I_LEN) - 1) << DMA_I_POS)) - -/* 0x510 : DMA_C4Config */ -#define DMA_C4CONFIG_OFFSET (0x510) -#define DMA_E DMA_E -#define DMA_E_POS (0U) -#define DMA_E_LEN (1U) -#define DMA_E_MSK (((1U << DMA_E_LEN) - 1) << DMA_E_POS) -#define DMA_E_UMSK (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS)) -#define DMA_SRCPERIPHERAL DMA_SRCPERIPHERAL -#define DMA_SRCPERIPHERAL_POS (1U) -#define DMA_SRCPERIPHERAL_LEN (5U) -#define DMA_SRCPERIPHERAL_MSK (((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS) -#define DMA_SRCPERIPHERAL_UMSK (~(((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS)) -#define DMA_DSTPERIPHERAL DMA_DSTPERIPHERAL -#define DMA_DSTPERIPHERAL_POS (6U) -#define DMA_DSTPERIPHERAL_LEN (5U) -#define DMA_DSTPERIPHERAL_MSK (((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS) -#define DMA_DSTPERIPHERAL_UMSK (~(((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS)) -#define DMA_FLOWCNTRL DMA_FLOWCNTRL -#define DMA_FLOWCNTRL_POS (11U) -#define DMA_FLOWCNTRL_LEN (3U) -#define DMA_FLOWCNTRL_MSK (((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS) -#define DMA_FLOWCNTRL_UMSK (~(((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS)) -#define DMA_IE DMA_IE -#define DMA_IE_POS (14U) -#define DMA_IE_LEN (1U) -#define DMA_IE_MSK (((1U << DMA_IE_LEN) - 1) << DMA_IE_POS) -#define DMA_IE_UMSK (~(((1U << DMA_IE_LEN) - 1) << DMA_IE_POS)) -#define DMA_ITC DMA_ITC -#define DMA_ITC_POS (15U) -#define DMA_ITC_LEN (1U) -#define DMA_ITC_MSK (((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS) -#define DMA_ITC_UMSK (~(((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS)) -#define DMA_L DMA_L -#define DMA_L_POS (16U) -#define DMA_L_LEN (1U) -#define DMA_L_MSK (((1U << DMA_L_LEN) - 1) << DMA_L_POS) -#define DMA_L_UMSK (~(((1U << DMA_L_LEN) - 1) << DMA_L_POS)) -#define DMA_A DMA_A -#define DMA_A_POS (17U) -#define DMA_A_LEN (1U) -#define DMA_A_MSK (((1U << DMA_A_LEN) - 1) << DMA_A_POS) -#define DMA_A_UMSK (~(((1U << DMA_A_LEN) - 1) << DMA_A_POS)) -#define DMA_H DMA_H -#define DMA_H_POS (18U) -#define DMA_H_LEN (1U) -#define DMA_H_MSK (((1U << DMA_H_LEN) - 1) << DMA_H_POS) -#define DMA_H_UMSK (~(((1U << DMA_H_LEN) - 1) << DMA_H_POS)) - -/* 0x51C : DMA_C4RSVD */ -#define DMA_C4RSVD_OFFSET (0x51C) -#define DMA_DSTREMNSGLE DMA_DSTREMNSGLE -#define DMA_DSTREMNSGLE_POS (3U) -#define DMA_DSTREMNSGLE_LEN (1U) -#define DMA_DSTREMNSGLE_MSK (((1U << DMA_DSTREMNSGLE_LEN) - 1) << DMA_DSTREMNSGLE_POS) -#define DMA_DSTREMNSGLE_UMSK (~(((1U << DMA_DSTREMNSGLE_LEN) - 1) << DMA_DSTREMNSGLE_POS)) -#define DMA_SRCREMNSGLE DMA_SRCREMNSGLE -#define DMA_SRCREMNSGLE_POS (4U) -#define DMA_SRCREMNSGLE_LEN (1U) -#define DMA_SRCREMNSGLE_MSK (((1U << DMA_SRCREMNSGLE_LEN) - 1) << DMA_SRCREMNSGLE_POS) -#define DMA_SRCREMNSGLE_UMSK (~(((1U << DMA_SRCREMNSGLE_LEN) - 1) << DMA_SRCREMNSGLE_POS)) - -/* 0x600 : DMA_C5SrcAddr */ -#define DMA_C5SRCADDR_OFFSET (0x600) -#define DMA_SRCADDR DMA_SRCADDR -#define DMA_SRCADDR_POS (0U) -#define DMA_SRCADDR_LEN (32U) -#define DMA_SRCADDR_MSK (((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS) -#define DMA_SRCADDR_UMSK (~(((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS)) - -/* 0x604 : DMA_C5DstAddr */ -#define DMA_C5DSTADDR_OFFSET (0x604) -#define DMA_DSTADDR DMA_DSTADDR -#define DMA_DSTADDR_POS (0U) -#define DMA_DSTADDR_LEN (32U) -#define DMA_DSTADDR_MSK (((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS) -#define DMA_DSTADDR_UMSK (~(((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS)) - -/* 0x608 : DMA_C5LLI */ -#define DMA_C5LLI_OFFSET (0x608) -#define DMA_LLI DMA_LLI -#define DMA_LLI_POS (0U) -#define DMA_LLI_LEN (32U) -#define DMA_LLI_MSK (((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS) -#define DMA_LLI_UMSK (~(((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS)) - -/* 0x60C : DMA_C5Control */ -#define DMA_C5CONTROL_OFFSET (0x60C) -#define DMA_TRANSFERSIZE DMA_TRANSFERSIZE -#define DMA_TRANSFERSIZE_POS (0U) -#define DMA_TRANSFERSIZE_LEN (12U) -#define DMA_TRANSFERSIZE_MSK (((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS) -#define DMA_TRANSFERSIZE_UMSK (~(((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS)) -#define DMA_SBSIZE DMA_SBSIZE -#define DMA_SBSIZE_POS (12U) -#define DMA_SBSIZE_LEN (2U) -#define DMA_SBSIZE_MSK (((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS) -#define DMA_SBSIZE_UMSK (~(((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS)) -#define DMA_DST_MIN_MODE DMA_DST_MIN_MODE -#define DMA_DST_MIN_MODE_POS (14U) -#define DMA_DST_MIN_MODE_LEN (1U) -#define DMA_DST_MIN_MODE_MSK (((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS) -#define DMA_DST_MIN_MODE_UMSK (~(((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS)) -#define DMA_DBSIZE DMA_DBSIZE -#define DMA_DBSIZE_POS (15U) -#define DMA_DBSIZE_LEN (2U) -#define DMA_DBSIZE_MSK (((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS) -#define DMA_DBSIZE_UMSK (~(((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS)) -#define DMA_DST_ADD_MODE DMA_DST_ADD_MODE -#define DMA_DST_ADD_MODE_POS (17U) -#define DMA_DST_ADD_MODE_LEN (1U) -#define DMA_DST_ADD_MODE_MSK (((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS) -#define DMA_DST_ADD_MODE_UMSK (~(((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS)) -#define DMA_SWIDTH DMA_SWIDTH -#define DMA_SWIDTH_POS (18U) -#define DMA_SWIDTH_LEN (2U) -#define DMA_SWIDTH_MSK (((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS) -#define DMA_SWIDTH_UMSK (~(((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS)) -#define DMA_DWIDTH DMA_DWIDTH -#define DMA_DWIDTH_POS (21U) -#define DMA_DWIDTH_LEN (2U) -#define DMA_DWIDTH_MSK (((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS) -#define DMA_DWIDTH_UMSK (~(((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS)) -#define DMA_FIX_CNT DMA_FIX_CNT -#define DMA_FIX_CNT_POS (23U) -#define DMA_FIX_CNT_LEN (3U) -#define DMA_FIX_CNT_MSK (((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS) -#define DMA_FIX_CNT_UMSK (~(((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS)) -#define DMA_SI DMA_SI -#define DMA_SI_POS (26U) -#define DMA_SI_LEN (1U) -#define DMA_SI_MSK (((1U << DMA_SI_LEN) - 1) << DMA_SI_POS) -#define DMA_SI_UMSK (~(((1U << DMA_SI_LEN) - 1) << DMA_SI_POS)) -#define DMA_DI DMA_DI -#define DMA_DI_POS (27U) -#define DMA_DI_LEN (1U) -#define DMA_DI_MSK (((1U << DMA_DI_LEN) - 1) << DMA_DI_POS) -#define DMA_DI_UMSK (~(((1U << DMA_DI_LEN) - 1) << DMA_DI_POS)) -#define DMA_PROT DMA_PROT -#define DMA_PROT_POS (28U) -#define DMA_PROT_LEN (3U) -#define DMA_PROT_MSK (((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS) -#define DMA_PROT_UMSK (~(((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS)) -#define DMA_I DMA_I -#define DMA_I_POS (31U) -#define DMA_I_LEN (1U) -#define DMA_I_MSK (((1U << DMA_I_LEN) - 1) << DMA_I_POS) -#define DMA_I_UMSK (~(((1U << DMA_I_LEN) - 1) << DMA_I_POS)) - -/* 0x610 : DMA_C5Config */ -#define DMA_C5CONFIG_OFFSET (0x610) -#define DMA_E DMA_E -#define DMA_E_POS (0U) -#define DMA_E_LEN (1U) -#define DMA_E_MSK (((1U << DMA_E_LEN) - 1) << DMA_E_POS) -#define DMA_E_UMSK (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS)) -#define DMA_SRCPERIPHERAL DMA_SRCPERIPHERAL -#define DMA_SRCPERIPHERAL_POS (1U) -#define DMA_SRCPERIPHERAL_LEN (5U) -#define DMA_SRCPERIPHERAL_MSK (((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS) -#define DMA_SRCPERIPHERAL_UMSK (~(((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS)) -#define DMA_DSTPERIPHERAL DMA_DSTPERIPHERAL -#define DMA_DSTPERIPHERAL_POS (6U) -#define DMA_DSTPERIPHERAL_LEN (5U) -#define DMA_DSTPERIPHERAL_MSK (((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS) -#define DMA_DSTPERIPHERAL_UMSK (~(((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS)) -#define DMA_FLOWCNTRL DMA_FLOWCNTRL -#define DMA_FLOWCNTRL_POS (11U) -#define DMA_FLOWCNTRL_LEN (3U) -#define DMA_FLOWCNTRL_MSK (((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS) -#define DMA_FLOWCNTRL_UMSK (~(((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS)) -#define DMA_IE DMA_IE -#define DMA_IE_POS (14U) -#define DMA_IE_LEN (1U) -#define DMA_IE_MSK (((1U << DMA_IE_LEN) - 1) << DMA_IE_POS) -#define DMA_IE_UMSK (~(((1U << DMA_IE_LEN) - 1) << DMA_IE_POS)) -#define DMA_ITC DMA_ITC -#define DMA_ITC_POS (15U) -#define DMA_ITC_LEN (1U) -#define DMA_ITC_MSK (((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS) -#define DMA_ITC_UMSK (~(((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS)) -#define DMA_L DMA_L -#define DMA_L_POS (16U) -#define DMA_L_LEN (1U) -#define DMA_L_MSK (((1U << DMA_L_LEN) - 1) << DMA_L_POS) -#define DMA_L_UMSK (~(((1U << DMA_L_LEN) - 1) << DMA_L_POS)) -#define DMA_A DMA_A -#define DMA_A_POS (17U) -#define DMA_A_LEN (1U) -#define DMA_A_MSK (((1U << DMA_A_LEN) - 1) << DMA_A_POS) -#define DMA_A_UMSK (~(((1U << DMA_A_LEN) - 1) << DMA_A_POS)) -#define DMA_H DMA_H -#define DMA_H_POS (18U) -#define DMA_H_LEN (1U) -#define DMA_H_MSK (((1U << DMA_H_LEN) - 1) << DMA_H_POS) -#define DMA_H_UMSK (~(((1U << DMA_H_LEN) - 1) << DMA_H_POS)) - -/* 0x61C : DMA_C5RSVD */ -#define DMA_C5RSVD_OFFSET (0x61C) -#define DMA_DSTREMNSGLE DMA_DSTREMNSGLE -#define DMA_DSTREMNSGLE_POS (3U) -#define DMA_DSTREMNSGLE_LEN (1U) -#define DMA_DSTREMNSGLE_MSK (((1U << DMA_DSTREMNSGLE_LEN) - 1) << DMA_DSTREMNSGLE_POS) -#define DMA_DSTREMNSGLE_UMSK (~(((1U << DMA_DSTREMNSGLE_LEN) - 1) << DMA_DSTREMNSGLE_POS)) -#define DMA_SRCREMNSGLE DMA_SRCREMNSGLE -#define DMA_SRCREMNSGLE_POS (4U) -#define DMA_SRCREMNSGLE_LEN (1U) -#define DMA_SRCREMNSGLE_MSK (((1U << DMA_SRCREMNSGLE_LEN) - 1) << DMA_SRCREMNSGLE_POS) -#define DMA_SRCREMNSGLE_UMSK (~(((1U << DMA_SRCREMNSGLE_LEN) - 1) << DMA_SRCREMNSGLE_POS)) - -/* 0x700 : DMA_C6SrcAddr */ -#define DMA_C6SRCADDR_OFFSET (0x700) -#define DMA_SRCADDR DMA_SRCADDR -#define DMA_SRCADDR_POS (0U) -#define DMA_SRCADDR_LEN (32U) -#define DMA_SRCADDR_MSK (((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS) -#define DMA_SRCADDR_UMSK (~(((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS)) - -/* 0x704 : DMA_C6DstAddr */ -#define DMA_C6DSTADDR_OFFSET (0x704) -#define DMA_DSTADDR DMA_DSTADDR -#define DMA_DSTADDR_POS (0U) -#define DMA_DSTADDR_LEN (32U) -#define DMA_DSTADDR_MSK (((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS) -#define DMA_DSTADDR_UMSK (~(((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS)) - -/* 0x708 : DMA_C6LLI */ -#define DMA_C6LLI_OFFSET (0x708) -#define DMA_LLI DMA_LLI -#define DMA_LLI_POS (0U) -#define DMA_LLI_LEN (32U) -#define DMA_LLI_MSK (((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS) -#define DMA_LLI_UMSK (~(((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS)) - -/* 0x70C : DMA_C6Control */ -#define DMA_C6CONTROL_OFFSET (0x70C) -#define DMA_TRANSFERSIZE DMA_TRANSFERSIZE -#define DMA_TRANSFERSIZE_POS (0U) -#define DMA_TRANSFERSIZE_LEN (12U) -#define DMA_TRANSFERSIZE_MSK (((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS) -#define DMA_TRANSFERSIZE_UMSK (~(((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS)) -#define DMA_SBSIZE DMA_SBSIZE -#define DMA_SBSIZE_POS (12U) -#define DMA_SBSIZE_LEN (2U) -#define DMA_SBSIZE_MSK (((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS) -#define DMA_SBSIZE_UMSK (~(((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS)) -#define DMA_DST_MIN_MODE DMA_DST_MIN_MODE -#define DMA_DST_MIN_MODE_POS (14U) -#define DMA_DST_MIN_MODE_LEN (1U) -#define DMA_DST_MIN_MODE_MSK (((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS) -#define DMA_DST_MIN_MODE_UMSK (~(((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS)) -#define DMA_DBSIZE DMA_DBSIZE -#define DMA_DBSIZE_POS (15U) -#define DMA_DBSIZE_LEN (2U) -#define DMA_DBSIZE_MSK (((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS) -#define DMA_DBSIZE_UMSK (~(((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS)) -#define DMA_DST_ADD_MODE DMA_DST_ADD_MODE -#define DMA_DST_ADD_MODE_POS (17U) -#define DMA_DST_ADD_MODE_LEN (1U) -#define DMA_DST_ADD_MODE_MSK (((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS) -#define DMA_DST_ADD_MODE_UMSK (~(((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS)) -#define DMA_SWIDTH DMA_SWIDTH -#define DMA_SWIDTH_POS (18U) -#define DMA_SWIDTH_LEN (2U) -#define DMA_SWIDTH_MSK (((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS) -#define DMA_SWIDTH_UMSK (~(((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS)) -#define DMA_DWIDTH DMA_DWIDTH -#define DMA_DWIDTH_POS (21U) -#define DMA_DWIDTH_LEN (2U) -#define DMA_DWIDTH_MSK (((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS) -#define DMA_DWIDTH_UMSK (~(((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS)) -#define DMA_FIX_CNT DMA_FIX_CNT -#define DMA_FIX_CNT_POS (23U) -#define DMA_FIX_CNT_LEN (3U) -#define DMA_FIX_CNT_MSK (((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS) -#define DMA_FIX_CNT_UMSK (~(((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS)) -#define DMA_SI DMA_SI -#define DMA_SI_POS (26U) -#define DMA_SI_LEN (1U) -#define DMA_SI_MSK (((1U << DMA_SI_LEN) - 1) << DMA_SI_POS) -#define DMA_SI_UMSK (~(((1U << DMA_SI_LEN) - 1) << DMA_SI_POS)) -#define DMA_DI DMA_DI -#define DMA_DI_POS (27U) -#define DMA_DI_LEN (1U) -#define DMA_DI_MSK (((1U << DMA_DI_LEN) - 1) << DMA_DI_POS) -#define DMA_DI_UMSK (~(((1U << DMA_DI_LEN) - 1) << DMA_DI_POS)) -#define DMA_PROT DMA_PROT -#define DMA_PROT_POS (28U) -#define DMA_PROT_LEN (3U) -#define DMA_PROT_MSK (((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS) -#define DMA_PROT_UMSK (~(((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS)) -#define DMA_I DMA_I -#define DMA_I_POS (31U) -#define DMA_I_LEN (1U) -#define DMA_I_MSK (((1U << DMA_I_LEN) - 1) << DMA_I_POS) -#define DMA_I_UMSK (~(((1U << DMA_I_LEN) - 1) << DMA_I_POS)) - -/* 0x710 : DMA_C6Config */ -#define DMA_C6CONFIG_OFFSET (0x710) -#define DMA_E DMA_E -#define DMA_E_POS (0U) -#define DMA_E_LEN (1U) -#define DMA_E_MSK (((1U << DMA_E_LEN) - 1) << DMA_E_POS) -#define DMA_E_UMSK (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS)) -#define DMA_SRCPERIPHERAL DMA_SRCPERIPHERAL -#define DMA_SRCPERIPHERAL_POS (1U) -#define DMA_SRCPERIPHERAL_LEN (5U) -#define DMA_SRCPERIPHERAL_MSK (((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS) -#define DMA_SRCPERIPHERAL_UMSK (~(((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS)) -#define DMA_DSTPERIPHERAL DMA_DSTPERIPHERAL -#define DMA_DSTPERIPHERAL_POS (6U) -#define DMA_DSTPERIPHERAL_LEN (5U) -#define DMA_DSTPERIPHERAL_MSK (((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS) -#define DMA_DSTPERIPHERAL_UMSK (~(((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS)) -#define DMA_FLOWCNTRL DMA_FLOWCNTRL -#define DMA_FLOWCNTRL_POS (11U) -#define DMA_FLOWCNTRL_LEN (3U) -#define DMA_FLOWCNTRL_MSK (((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS) -#define DMA_FLOWCNTRL_UMSK (~(((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS)) -#define DMA_IE DMA_IE -#define DMA_IE_POS (14U) -#define DMA_IE_LEN (1U) -#define DMA_IE_MSK (((1U << DMA_IE_LEN) - 1) << DMA_IE_POS) -#define DMA_IE_UMSK (~(((1U << DMA_IE_LEN) - 1) << DMA_IE_POS)) -#define DMA_ITC DMA_ITC -#define DMA_ITC_POS (15U) -#define DMA_ITC_LEN (1U) -#define DMA_ITC_MSK (((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS) -#define DMA_ITC_UMSK (~(((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS)) -#define DMA_L DMA_L -#define DMA_L_POS (16U) -#define DMA_L_LEN (1U) -#define DMA_L_MSK (((1U << DMA_L_LEN) - 1) << DMA_L_POS) -#define DMA_L_UMSK (~(((1U << DMA_L_LEN) - 1) << DMA_L_POS)) -#define DMA_A DMA_A -#define DMA_A_POS (17U) -#define DMA_A_LEN (1U) -#define DMA_A_MSK (((1U << DMA_A_LEN) - 1) << DMA_A_POS) -#define DMA_A_UMSK (~(((1U << DMA_A_LEN) - 1) << DMA_A_POS)) -#define DMA_H DMA_H -#define DMA_H_POS (18U) -#define DMA_H_LEN (1U) -#define DMA_H_MSK (((1U << DMA_H_LEN) - 1) << DMA_H_POS) -#define DMA_H_UMSK (~(((1U << DMA_H_LEN) - 1) << DMA_H_POS)) - -/* 0x71C : DMA_C6RSVD */ -#define DMA_C6RSVD_OFFSET (0x71C) -#define DMA_DSTREMNSGLE DMA_DSTREMNSGLE -#define DMA_DSTREMNSGLE_POS (3U) -#define DMA_DSTREMNSGLE_LEN (1U) -#define DMA_DSTREMNSGLE_MSK (((1U << DMA_DSTREMNSGLE_LEN) - 1) << DMA_DSTREMNSGLE_POS) -#define DMA_DSTREMNSGLE_UMSK (~(((1U << DMA_DSTREMNSGLE_LEN) - 1) << DMA_DSTREMNSGLE_POS)) -#define DMA_SRCREMNSGLE DMA_SRCREMNSGLE -#define DMA_SRCREMNSGLE_POS (4U) -#define DMA_SRCREMNSGLE_LEN (1U) -#define DMA_SRCREMNSGLE_MSK (((1U << DMA_SRCREMNSGLE_LEN) - 1) << DMA_SRCREMNSGLE_POS) -#define DMA_SRCREMNSGLE_UMSK (~(((1U << DMA_SRCREMNSGLE_LEN) - 1) << DMA_SRCREMNSGLE_POS)) - -/* 0x800 : DMA_C7SrcAddr */ -#define DMA_C7SRCADDR_OFFSET (0x800) -#define DMA_SRCADDR DMA_SRCADDR -#define DMA_SRCADDR_POS (0U) -#define DMA_SRCADDR_LEN (32U) -#define DMA_SRCADDR_MSK (((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS) -#define DMA_SRCADDR_UMSK (~(((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS)) - -/* 0x804 : DMA_C7DstAddr */ -#define DMA_C7DSTADDR_OFFSET (0x804) -#define DMA_DSTADDR DMA_DSTADDR -#define DMA_DSTADDR_POS (0U) -#define DMA_DSTADDR_LEN (32U) -#define DMA_DSTADDR_MSK (((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS) -#define DMA_DSTADDR_UMSK (~(((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS)) - -/* 0x808 : DMA_C7LLI */ -#define DMA_C7LLI_OFFSET (0x808) -#define DMA_LLI DMA_LLI -#define DMA_LLI_POS (0U) -#define DMA_LLI_LEN (32U) -#define DMA_LLI_MSK (((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS) -#define DMA_LLI_UMSK (~(((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS)) - -/* 0x80C : DMA_C7Control */ -#define DMA_C7CONTROL_OFFSET (0x80C) -#define DMA_TRANSFERSIZE DMA_TRANSFERSIZE -#define DMA_TRANSFERSIZE_POS (0U) -#define DMA_TRANSFERSIZE_LEN (12U) -#define DMA_TRANSFERSIZE_MSK (((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS) -#define DMA_TRANSFERSIZE_UMSK (~(((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS)) -#define DMA_SBSIZE DMA_SBSIZE -#define DMA_SBSIZE_POS (12U) -#define DMA_SBSIZE_LEN (2U) -#define DMA_SBSIZE_MSK (((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS) -#define DMA_SBSIZE_UMSK (~(((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS)) -#define DMA_DST_MIN_MODE DMA_DST_MIN_MODE -#define DMA_DST_MIN_MODE_POS (14U) -#define DMA_DST_MIN_MODE_LEN (1U) -#define DMA_DST_MIN_MODE_MSK (((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS) -#define DMA_DST_MIN_MODE_UMSK (~(((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS)) -#define DMA_DBSIZE DMA_DBSIZE -#define DMA_DBSIZE_POS (15U) -#define DMA_DBSIZE_LEN (2U) -#define DMA_DBSIZE_MSK (((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS) -#define DMA_DBSIZE_UMSK (~(((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS)) -#define DMA_DST_ADD_MODE DMA_DST_ADD_MODE -#define DMA_DST_ADD_MODE_POS (17U) -#define DMA_DST_ADD_MODE_LEN (1U) -#define DMA_DST_ADD_MODE_MSK (((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS) -#define DMA_DST_ADD_MODE_UMSK (~(((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS)) -#define DMA_SWIDTH DMA_SWIDTH -#define DMA_SWIDTH_POS (18U) -#define DMA_SWIDTH_LEN (2U) -#define DMA_SWIDTH_MSK (((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS) -#define DMA_SWIDTH_UMSK (~(((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS)) -#define DMA_DWIDTH DMA_DWIDTH -#define DMA_DWIDTH_POS (21U) -#define DMA_DWIDTH_LEN (2U) -#define DMA_DWIDTH_MSK (((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS) -#define DMA_DWIDTH_UMSK (~(((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS)) -#define DMA_FIX_CNT DMA_FIX_CNT -#define DMA_FIX_CNT_POS (23U) -#define DMA_FIX_CNT_LEN (3U) -#define DMA_FIX_CNT_MSK (((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS) -#define DMA_FIX_CNT_UMSK (~(((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS)) -#define DMA_SI DMA_SI -#define DMA_SI_POS (26U) -#define DMA_SI_LEN (1U) -#define DMA_SI_MSK (((1U << DMA_SI_LEN) - 1) << DMA_SI_POS) -#define DMA_SI_UMSK (~(((1U << DMA_SI_LEN) - 1) << DMA_SI_POS)) -#define DMA_DI DMA_DI -#define DMA_DI_POS (27U) -#define DMA_DI_LEN (1U) -#define DMA_DI_MSK (((1U << DMA_DI_LEN) - 1) << DMA_DI_POS) -#define DMA_DI_UMSK (~(((1U << DMA_DI_LEN) - 1) << DMA_DI_POS)) -#define DMA_PROT DMA_PROT -#define DMA_PROT_POS (28U) -#define DMA_PROT_LEN (3U) -#define DMA_PROT_MSK (((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS) -#define DMA_PROT_UMSK (~(((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS)) -#define DMA_I DMA_I -#define DMA_I_POS (31U) -#define DMA_I_LEN (1U) -#define DMA_I_MSK (((1U << DMA_I_LEN) - 1) << DMA_I_POS) -#define DMA_I_UMSK (~(((1U << DMA_I_LEN) - 1) << DMA_I_POS)) - -/* 0x810 : DMA_C7Config */ -#define DMA_C7CONFIG_OFFSET (0x810) -#define DMA_E DMA_E -#define DMA_E_POS (0U) -#define DMA_E_LEN (1U) -#define DMA_E_MSK (((1U << DMA_E_LEN) - 1) << DMA_E_POS) -#define DMA_E_UMSK (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS)) -#define DMA_SRCPERIPHERAL DMA_SRCPERIPHERAL -#define DMA_SRCPERIPHERAL_POS (1U) -#define DMA_SRCPERIPHERAL_LEN (5U) -#define DMA_SRCPERIPHERAL_MSK (((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS) -#define DMA_SRCPERIPHERAL_UMSK (~(((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS)) -#define DMA_DSTPERIPHERAL DMA_DSTPERIPHERAL -#define DMA_DSTPERIPHERAL_POS (6U) -#define DMA_DSTPERIPHERAL_LEN (5U) -#define DMA_DSTPERIPHERAL_MSK (((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS) -#define DMA_DSTPERIPHERAL_UMSK (~(((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS)) -#define DMA_FLOWCNTRL DMA_FLOWCNTRL -#define DMA_FLOWCNTRL_POS (11U) -#define DMA_FLOWCNTRL_LEN (3U) -#define DMA_FLOWCNTRL_MSK (((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS) -#define DMA_FLOWCNTRL_UMSK (~(((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS)) -#define DMA_IE DMA_IE -#define DMA_IE_POS (14U) -#define DMA_IE_LEN (1U) -#define DMA_IE_MSK (((1U << DMA_IE_LEN) - 1) << DMA_IE_POS) -#define DMA_IE_UMSK (~(((1U << DMA_IE_LEN) - 1) << DMA_IE_POS)) -#define DMA_ITC DMA_ITC -#define DMA_ITC_POS (15U) -#define DMA_ITC_LEN (1U) -#define DMA_ITC_MSK (((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS) -#define DMA_ITC_UMSK (~(((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS)) -#define DMA_L DMA_L -#define DMA_L_POS (16U) -#define DMA_L_LEN (1U) -#define DMA_L_MSK (((1U << DMA_L_LEN) - 1) << DMA_L_POS) -#define DMA_L_UMSK (~(((1U << DMA_L_LEN) - 1) << DMA_L_POS)) -#define DMA_A DMA_A -#define DMA_A_POS (17U) -#define DMA_A_LEN (1U) -#define DMA_A_MSK (((1U << DMA_A_LEN) - 1) << DMA_A_POS) -#define DMA_A_UMSK (~(((1U << DMA_A_LEN) - 1) << DMA_A_POS)) -#define DMA_H DMA_H -#define DMA_H_POS (18U) -#define DMA_H_LEN (1U) -#define DMA_H_MSK (((1U << DMA_H_LEN) - 1) << DMA_H_POS) -#define DMA_H_UMSK (~(((1U << DMA_H_LEN) - 1) << DMA_H_POS)) - -/* 0x81C : DMA_C7RSVD */ -#define DMA_C7RSVD_OFFSET (0x81C) -#define DMA_DSTREMNSGLE DMA_DSTREMNSGLE -#define DMA_DSTREMNSGLE_POS (3U) -#define DMA_DSTREMNSGLE_LEN (1U) -#define DMA_DSTREMNSGLE_MSK (((1U << DMA_DSTREMNSGLE_LEN) - 1) << DMA_DSTREMNSGLE_POS) -#define DMA_DSTREMNSGLE_UMSK (~(((1U << DMA_DSTREMNSGLE_LEN) - 1) << DMA_DSTREMNSGLE_POS)) -#define DMA_SRCREMNSGLE DMA_SRCREMNSGLE -#define DMA_SRCREMNSGLE_POS (4U) -#define DMA_SRCREMNSGLE_LEN (1U) -#define DMA_SRCREMNSGLE_MSK (((1U << DMA_SRCREMNSGLE_LEN) - 1) << DMA_SRCREMNSGLE_POS) -#define DMA_SRCREMNSGLE_UMSK (~(((1U << DMA_SRCREMNSGLE_LEN) - 1) << DMA_SRCREMNSGLE_POS)) - -struct dma_reg { - /* 0x0 : DMA_IntStatus */ - union { - struct { - uint32_t IntStatus : 8; /* [ 7: 0], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_IntStatus; - - /* 0x4 : DMA_IntTCStatus */ - union { - struct { - uint32_t IntTCStatus : 8; /* [ 7: 0], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_IntTCStatus; - - /* 0x8 : DMA_IntTCClear */ - union { - struct { - uint32_t IntTCClear : 8; /* [ 7: 0], w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_IntTCClear; - - /* 0xC : DMA_IntErrorStatus */ - union { - struct { - uint32_t IntErrorStatus : 8; /* [ 7: 0], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_IntErrorStatus; - - /* 0x10 : DMA_IntErrClr */ - union { - struct { - uint32_t IntErrClr : 8; /* [ 7: 0], w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_IntErrClr; - - /* 0x14 : DMA_RawIntTCStatus */ - union { - struct { - uint32_t RawIntTCStatus : 8; /* [ 7: 0], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_RawIntTCStatus; - - /* 0x18 : DMA_RawIntErrorStatus */ - union { - struct { - uint32_t RawIntErrorStatus : 8; /* [ 7: 0], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_RawIntErrorStatus; - - /* 0x1C : DMA_EnbldChns */ - union { - struct { - uint32_t EnabledChannels : 8; /* [ 7: 0], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_EnbldChns; - - /* 0x20 : DMA_SoftBReq */ - union { - struct { - uint32_t SoftBReq : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_SoftBReq; - - /* 0x24 : DMA_SoftSReq */ - union { - struct { - uint32_t SoftSReq : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_SoftSReq; - - /* 0x28 : DMA_SoftLBReq */ - union { - struct { - uint32_t SoftLBReq : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_SoftLBReq; - - /* 0x2C : DMA_SoftLSReq */ - union { - struct { - uint32_t SoftLSReq : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_SoftLSReq; - - /* 0x30 : DMA_Top_Config */ - union { - struct { - uint32_t E : 1; /* [ 0], r/w, 0x0 */ - uint32_t M : 1; /* [ 1], r/w, 0x0 */ - uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_Top_Config; - - /* 0x34 : DMA_Sync */ - union { - struct { - uint32_t DMA_Sync : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_Sync; - - /* 0x38 reserved */ - uint8_t RESERVED0x38[200]; - - /* 0x100 : DMA_C0SrcAddr */ - union { - struct { - uint32_t SrcAddr : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C0SrcAddr; - - /* 0x104 : DMA_C0DstAddr */ - union { - struct { - uint32_t DstAddr : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C0DstAddr; - - /* 0x108 : DMA_C0LLI */ - union { - struct { - uint32_t LLI : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C0LLI; - - /* 0x10C : DMA_C0Control */ - union { - struct { - uint32_t TransferSize : 12; /* [11: 0], r/w, 0x0 */ - uint32_t SBSize : 2; /* [13:12], r/w, 0x1 */ - uint32_t dst_min_mode : 1; /* [ 14], r/w, 0x0 */ - uint32_t DBSize : 2; /* [16:15], r/w, 0x1 */ - uint32_t dst_add_mode : 1; /* [ 17], r/w, 0x0 */ - uint32_t SWidth : 2; /* [19:18], r/w, 0x2 */ - uint32_t reserved_20 : 1; /* [ 20], rsvd, 0x0 */ - uint32_t DWidth : 2; /* [22:21], r/w, 0x2 */ - uint32_t fix_cnt : 3; /* [25:23], r/w, 0x0 */ - uint32_t SI : 1; /* [ 26], r/w, 0x1 */ - uint32_t DI : 1; /* [ 27], r/w, 0x1 */ - uint32_t Prot : 3; /* [30:28], r/w, 0x0 */ - uint32_t I : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C0Control; - - /* 0x110 : DMA_C0Config */ - union { - struct { - uint32_t E : 1; /* [ 0], r/w, 0x0 */ - uint32_t SrcPeripheral : 5; /* [ 5: 1], r/w, 0x0 */ - uint32_t DstPeripheral : 5; /* [10: 6], r/w, 0x0 */ - uint32_t FlowCntrl : 3; /* [13:11], r/w, 0x0 */ - uint32_t IE : 1; /* [ 14], r/w, 0x0 */ - uint32_t ITC : 1; /* [ 15], r/w, 0x0 */ - uint32_t L : 1; /* [ 16], r/w, 0x0 */ - uint32_t A : 1; /* [ 17], r, 0x0 */ - uint32_t H : 1; /* [ 18], r/w, 0x0 */ - uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */ - uint32_t LLICounter : 10; /* [29:20], r, 0x0 */ - uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C0Config; - - /* 0x114 reserved */ - uint8_t RESERVED0x114[8]; - - /* 0x11C : DMA_C0RSVD */ - union { - struct { - uint32_t reserved_0_2 : 3; /* [ 2: 0], rsvd, 0x0 */ - uint32_t DstRemnSgle : 1; /* [ 3], r/w, 0x0 */ - uint32_t SrcRemnSgle : 1; /* [ 4], r/w, 0x0 */ - uint32_t reserved_5_31 : 27; /* [31: 5], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C0RSVD; - - /* 0x120 reserved */ - uint8_t RESERVED0x120[224]; - - /* 0x200 : DMA_C1SrcAddr */ - union { - struct { - uint32_t SrcAddr : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C1SrcAddr; - - /* 0x204 : DMA_C1DstAddr */ - union { - struct { - uint32_t DstAddr : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C1DstAddr; - - /* 0x208 : DMA_C1LLI */ - union { - struct { - uint32_t LLI : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C1LLI; - - /* 0x20C : DMA_C1Control */ - union { - struct { - uint32_t TransferSize : 12; /* [11: 0], r/w, 0x0 */ - uint32_t SBSize : 2; /* [13:12], r/w, 0x1 */ - uint32_t dst_min_mode : 1; /* [ 14], r/w, 0x0 */ - uint32_t DBSize : 2; /* [16:15], r/w, 0x1 */ - uint32_t dst_add_mode : 1; /* [ 17], r/w, 0x0 */ - uint32_t SWidth : 2; /* [19:18], r/w, 0x2 */ - uint32_t reserved_20 : 1; /* [ 20], rsvd, 0x0 */ - uint32_t DWidth : 2; /* [22:21], r/w, 0x2 */ - uint32_t fix_cnt : 3; /* [25:23], r/w, 0x0 */ - uint32_t SI : 1; /* [ 26], r/w, 0x1 */ - uint32_t DI : 1; /* [ 27], r/w, 0x1 */ - uint32_t Prot : 3; /* [30:28], r/w, 0x0 */ - uint32_t I : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C1Control; - - /* 0x210 : DMA_C1Config */ - union { - struct { - uint32_t E : 1; /* [ 0], r/w, 0x0 */ - uint32_t SrcPeripheral : 5; /* [ 5: 1], r/w, 0x0 */ - uint32_t DstPeripheral : 5; /* [10: 6], r/w, 0x0 */ - uint32_t FlowCntrl : 3; /* [13:11], r/w, 0x0 */ - uint32_t IE : 1; /* [ 14], r/w, 0x0 */ - uint32_t ITC : 1; /* [ 15], r/w, 0x0 */ - uint32_t L : 1; /* [ 16], r/w, 0x0 */ - uint32_t A : 1; /* [ 17], r, 0x0 */ - uint32_t H : 1; /* [ 18], r/w, 0x0 */ - uint32_t reserved_19_31 : 13; /* [31:19], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C1Config; - - /* 0x214 reserved */ - uint8_t RESERVED0x214[8]; - - /* 0x21C : DMA_C1RSVD */ - union { - struct { - uint32_t reserved_0_2 : 3; /* [ 2: 0], rsvd, 0x0 */ - uint32_t DstRemnSgle : 1; /* [ 3], r/w, 0x0 */ - uint32_t SrcRemnSgle : 1; /* [ 4], r/w, 0x0 */ - uint32_t reserved_5_31 : 27; /* [31: 5], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C1RSVD; - - /* 0x220 reserved */ - uint8_t RESERVED0x220[224]; - - /* 0x300 : DMA_C2SrcAddr */ - union { - struct { - uint32_t SrcAddr : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C2SrcAddr; - - /* 0x304 : DMA_C2DstAddr */ - union { - struct { - uint32_t DstAddr : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C2DstAddr; - - /* 0x308 : DMA_C2LLI */ - union { - struct { - uint32_t LLI : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C2LLI; - - /* 0x30C : DMA_C2Control */ - union { - struct { - uint32_t TransferSize : 12; /* [11: 0], r/w, 0x0 */ - uint32_t SBSize : 2; /* [13:12], r/w, 0x1 */ - uint32_t dst_min_mode : 1; /* [ 14], r/w, 0x0 */ - uint32_t DBSize : 2; /* [16:15], r/w, 0x1 */ - uint32_t dst_add_mode : 1; /* [ 17], r/w, 0x0 */ - uint32_t SWidth : 2; /* [19:18], r/w, 0x2 */ - uint32_t reserved_20 : 1; /* [ 20], rsvd, 0x0 */ - uint32_t DWidth : 2; /* [22:21], r/w, 0x2 */ - uint32_t fix_cnt : 3; /* [25:23], r/w, 0x0 */ - uint32_t SI : 1; /* [ 26], r/w, 0x1 */ - uint32_t DI : 1; /* [ 27], r/w, 0x1 */ - uint32_t Prot : 3; /* [30:28], r/w, 0x0 */ - uint32_t I : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C2Control; - - /* 0x310 : DMA_C3Config */ - union { - struct { - uint32_t E : 1; /* [ 0], r/w, 0x0 */ - uint32_t SrcPeripheral : 5; /* [ 5: 1], r/w, 0x0 */ - uint32_t DstPeripheral : 5; /* [10: 6], r/w, 0x0 */ - uint32_t FlowCntrl : 3; /* [13:11], r/w, 0x0 */ - uint32_t IE : 1; /* [ 14], r/w, 0x0 */ - uint32_t ITC : 1; /* [ 15], r/w, 0x0 */ - uint32_t L : 1; /* [ 16], r/w, 0x0 */ - uint32_t A : 1; /* [ 17], r, 0x0 */ - uint32_t H : 1; /* [ 18], r/w, 0x0 */ - uint32_t reserved_19_31 : 13; /* [31:19], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C3Config; - - /* 0x314 reserved */ - uint8_t RESERVED0x314[8]; - - /* 0x31C : DMA_C3RSVD */ - union { - struct { - uint32_t reserved_0_2 : 3; /* [ 2: 0], rsvd, 0x0 */ - uint32_t DstRemnSgle : 1; /* [ 3], r/w, 0x0 */ - uint32_t SrcRemnSgle : 1; /* [ 4], r/w, 0x0 */ - uint32_t reserved_5_31 : 27; /* [31: 5], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C3RSVD; - - /* 0x320 reserved */ - uint8_t RESERVED0x320[480]; - - /* 0x500 : DMA_C4SrcAddr */ - union { - struct { - uint32_t SrcAddr : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C4SrcAddr; - - /* 0x504 : DMA_C4DstAddr */ - union { - struct { - uint32_t DstAddr : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C4DstAddr; - - /* 0x508 : DMA_C4LLI */ - union { - struct { - uint32_t LLI : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C4LLI; - - /* 0x50C : DMA_C4Control */ - union { - struct { - uint32_t TransferSize : 12; /* [11: 0], r/w, 0x0 */ - uint32_t SBSize : 2; /* [13:12], r/w, 0x1 */ - uint32_t dst_min_mode : 1; /* [ 14], r/w, 0x0 */ - uint32_t DBSize : 2; /* [16:15], r/w, 0x1 */ - uint32_t dst_add_mode : 1; /* [ 17], r/w, 0x0 */ - uint32_t SWidth : 2; /* [19:18], r/w, 0x2 */ - uint32_t reserved_20 : 1; /* [ 20], rsvd, 0x0 */ - uint32_t DWidth : 2; /* [22:21], r/w, 0x2 */ - uint32_t fix_cnt : 3; /* [25:23], r/w, 0x0 */ - uint32_t SI : 1; /* [ 26], r/w, 0x1 */ - uint32_t DI : 1; /* [ 27], r/w, 0x1 */ - uint32_t Prot : 3; /* [30:28], r/w, 0x0 */ - uint32_t I : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C4Control; - - /* 0x510 : DMA_C4Config */ - union { - struct { - uint32_t E : 1; /* [ 0], r/w, 0x0 */ - uint32_t SrcPeripheral : 5; /* [ 5: 1], r/w, 0x0 */ - uint32_t DstPeripheral : 5; /* [10: 6], r/w, 0x0 */ - uint32_t FlowCntrl : 3; /* [13:11], r/w, 0x0 */ - uint32_t IE : 1; /* [ 14], r/w, 0x0 */ - uint32_t ITC : 1; /* [ 15], r/w, 0x0 */ - uint32_t L : 1; /* [ 16], r/w, 0x0 */ - uint32_t A : 1; /* [ 17], r, 0x0 */ - uint32_t H : 1; /* [ 18], r/w, 0x0 */ - uint32_t reserved_19_31 : 13; /* [31:19], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C4Config; - - /* 0x514 reserved */ - uint8_t RESERVED0x514[8]; - - /* 0x51C : DMA_C4RSVD */ - union { - struct { - uint32_t reserved_0_2 : 3; /* [ 2: 0], rsvd, 0x0 */ - uint32_t DstRemnSgle : 1; /* [ 3], r/w, 0x0 */ - uint32_t SrcRemnSgle : 1; /* [ 4], r/w, 0x0 */ - uint32_t reserved_5_31 : 27; /* [31: 5], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C4RSVD; - - /* 0x520 reserved */ - uint8_t RESERVED0x520[224]; - - /* 0x600 : DMA_C5SrcAddr */ - union { - struct { - uint32_t SrcAddr : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C5SrcAddr; - - /* 0x604 : DMA_C5DstAddr */ - union { - struct { - uint32_t DstAddr : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C5DstAddr; - - /* 0x608 : DMA_C5LLI */ - union { - struct { - uint32_t LLI : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C5LLI; - - /* 0x60C : DMA_C5Control */ - union { - struct { - uint32_t TransferSize : 12; /* [11: 0], r/w, 0x0 */ - uint32_t SBSize : 2; /* [13:12], r/w, 0x1 */ - uint32_t dst_min_mode : 1; /* [ 14], r/w, 0x0 */ - uint32_t DBSize : 2; /* [16:15], r/w, 0x1 */ - uint32_t dst_add_mode : 1; /* [ 17], r/w, 0x0 */ - uint32_t SWidth : 2; /* [19:18], r/w, 0x2 */ - uint32_t reserved_20 : 1; /* [ 20], rsvd, 0x0 */ - uint32_t DWidth : 2; /* [22:21], r/w, 0x2 */ - uint32_t fix_cnt : 3; /* [25:23], r/w, 0x0 */ - uint32_t SI : 1; /* [ 26], r/w, 0x1 */ - uint32_t DI : 1; /* [ 27], r/w, 0x1 */ - uint32_t Prot : 3; /* [30:28], r/w, 0x0 */ - uint32_t I : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C5Control; - - /* 0x610 : DMA_C5Config */ - union { - struct { - uint32_t E : 1; /* [ 0], r/w, 0x0 */ - uint32_t SrcPeripheral : 5; /* [ 5: 1], r/w, 0x0 */ - uint32_t DstPeripheral : 5; /* [10: 6], r/w, 0x0 */ - uint32_t FlowCntrl : 3; /* [13:11], r/w, 0x0 */ - uint32_t IE : 1; /* [ 14], r/w, 0x0 */ - uint32_t ITC : 1; /* [ 15], r/w, 0x0 */ - uint32_t L : 1; /* [ 16], r/w, 0x0 */ - uint32_t A : 1; /* [ 17], r, 0x0 */ - uint32_t H : 1; /* [ 18], r/w, 0x0 */ - uint32_t reserved_19_31 : 13; /* [31:19], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C5Config; - - /* 0x614 reserved */ - uint8_t RESERVED0x614[8]; - - /* 0x61C : DMA_C5RSVD */ - union { - struct { - uint32_t reserved_0_2 : 3; /* [ 2: 0], rsvd, 0x0 */ - uint32_t DstRemnSgle : 1; /* [ 3], r/w, 0x0 */ - uint32_t SrcRemnSgle : 1; /* [ 4], r/w, 0x0 */ - uint32_t reserved_5_31 : 27; /* [31: 5], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C5RSVD; - - /* 0x620 reserved */ - uint8_t RESERVED0x620[224]; - - /* 0x700 : DMA_C6SrcAddr */ - union { - struct { - uint32_t SrcAddr : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C6SrcAddr; - - /* 0x704 : DMA_C6DstAddr */ - union { - struct { - uint32_t DstAddr : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C6DstAddr; - - /* 0x708 : DMA_C6LLI */ - union { - struct { - uint32_t LLI : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C6LLI; - - /* 0x70C : DMA_C6Control */ - union { - struct { - uint32_t TransferSize : 12; /* [11: 0], r/w, 0x0 */ - uint32_t SBSize : 2; /* [13:12], r/w, 0x1 */ - uint32_t dst_min_mode : 1; /* [ 14], r/w, 0x0 */ - uint32_t DBSize : 2; /* [16:15], r/w, 0x1 */ - uint32_t dst_add_mode : 1; /* [ 17], r/w, 0x0 */ - uint32_t SWidth : 2; /* [19:18], r/w, 0x2 */ - uint32_t reserved_20 : 1; /* [ 20], rsvd, 0x0 */ - uint32_t DWidth : 2; /* [22:21], r/w, 0x2 */ - uint32_t fix_cnt : 3; /* [25:23], r/w, 0x0 */ - uint32_t SI : 1; /* [ 26], r/w, 0x1 */ - uint32_t DI : 1; /* [ 27], r/w, 0x1 */ - uint32_t Prot : 3; /* [30:28], r/w, 0x0 */ - uint32_t I : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C6Control; - - /* 0x710 : DMA_C6Config */ - union { - struct { - uint32_t E : 1; /* [ 0], r/w, 0x0 */ - uint32_t SrcPeripheral : 5; /* [ 5: 1], r/w, 0x0 */ - uint32_t DstPeripheral : 5; /* [10: 6], r/w, 0x0 */ - uint32_t FlowCntrl : 3; /* [13:11], r/w, 0x0 */ - uint32_t IE : 1; /* [ 14], r/w, 0x0 */ - uint32_t ITC : 1; /* [ 15], r/w, 0x0 */ - uint32_t L : 1; /* [ 16], r/w, 0x0 */ - uint32_t A : 1; /* [ 17], r, 0x0 */ - uint32_t H : 1; /* [ 18], r/w, 0x0 */ - uint32_t reserved_19_31 : 13; /* [31:19], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C6Config; - - /* 0x714 reserved */ - uint8_t RESERVED0x714[8]; - - /* 0x71C : DMA_C6RSVD */ - union { - struct { - uint32_t reserved_0_2 : 3; /* [ 2: 0], rsvd, 0x0 */ - uint32_t DstRemnSgle : 1; /* [ 3], r/w, 0x0 */ - uint32_t SrcRemnSgle : 1; /* [ 4], r/w, 0x0 */ - uint32_t reserved_5_31 : 27; /* [31: 5], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C6RSVD; - - /* 0x720 reserved */ - uint8_t RESERVED0x720[224]; - - /* 0x800 : DMA_C7SrcAddr */ - union { - struct { - uint32_t SrcAddr : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C7SrcAddr; - - /* 0x804 : DMA_C7DstAddr */ - union { - struct { - uint32_t DstAddr : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C7DstAddr; - - /* 0x808 : DMA_C7LLI */ - union { - struct { - uint32_t LLI : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C7LLI; - - /* 0x80C : DMA_C7Control */ - union { - struct { - uint32_t TransferSize : 12; /* [11: 0], r/w, 0x0 */ - uint32_t SBSize : 2; /* [13:12], r/w, 0x1 */ - uint32_t dst_min_mode : 1; /* [ 14], r/w, 0x0 */ - uint32_t DBSize : 2; /* [16:15], r/w, 0x1 */ - uint32_t dst_add_mode : 1; /* [ 17], r/w, 0x0 */ - uint32_t SWidth : 2; /* [19:18], r/w, 0x2 */ - uint32_t reserved_20 : 1; /* [ 20], rsvd, 0x0 */ - uint32_t DWidth : 2; /* [22:21], r/w, 0x2 */ - uint32_t fix_cnt : 3; /* [25:23], r/w, 0x0 */ - uint32_t SI : 1; /* [ 26], r/w, 0x1 */ - uint32_t DI : 1; /* [ 27], r/w, 0x1 */ - uint32_t Prot : 3; /* [30:28], r/w, 0x0 */ - uint32_t I : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C7Control; - - /* 0x810 : DMA_C7Config */ - union { - struct { - uint32_t E : 1; /* [ 0], r/w, 0x0 */ - uint32_t SrcPeripheral : 5; /* [ 5: 1], r/w, 0x0 */ - uint32_t DstPeripheral : 5; /* [10: 6], r/w, 0x0 */ - uint32_t FlowCntrl : 3; /* [13:11], r/w, 0x0 */ - uint32_t IE : 1; /* [ 14], r/w, 0x0 */ - uint32_t ITC : 1; /* [ 15], r/w, 0x0 */ - uint32_t L : 1; /* [ 16], r/w, 0x0 */ - uint32_t A : 1; /* [ 17], r, 0x0 */ - uint32_t H : 1; /* [ 18], r/w, 0x0 */ - uint32_t reserved_19_31 : 13; /* [31:19], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C7Config; - - /* 0x814 reserved */ - uint8_t RESERVED0x814[8]; - - /* 0x81C : DMA_C7RSVD */ - union { - struct { - uint32_t reserved_0_2 : 3; /* [ 2: 0], rsvd, 0x0 */ - uint32_t DstRemnSgle : 1; /* [ 3], r/w, 0x0 */ - uint32_t SrcRemnSgle : 1; /* [ 4], r/w, 0x0 */ - uint32_t reserved_5_31 : 27; /* [31: 5], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C7RSVD; -}; - -typedef volatile struct dma_reg dma_reg_t; - -/*Following is reg patch*/ - -/* 0x0 : DMA_SrcAddr */ -#define DMA_SRCADDR_OFFSET (0x0) -#define DMA_SRCADDR DMA_SRCADDR -#define DMA_SRCADDR_POS (0U) -#define DMA_SRCADDR_LEN (32U) -#define DMA_SRCADDR_MSK (((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS) -#define DMA_SRCADDR_UMSK (~(((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS)) - -/* 0x4 : DMA_DstAddr */ -#define DMA_DSTADDR_OFFSET (0x4) -#define DMA_DSTADDR DMA_DSTADDR -#define DMA_DSTADDR_POS (0U) -#define DMA_DSTADDR_LEN (32U) -#define DMA_DSTADDR_MSK (((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS) -#define DMA_DSTADDR_UMSK (~(((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS)) - -/* 0x8 : DMA_LLI */ -#define DMA_LLI_OFFSET (0x8) -#define DMA_LLI DMA_LLI -#define DMA_LLI_POS (0U) -#define DMA_LLI_LEN (32U) -#define DMA_LLI_MSK (((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS) -#define DMA_LLI_UMSK (~(((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS)) - -/* 0xc : DMA_Control */ -#define DMA_CONTROL_OFFSET (0xc) -#define DMA_TRANSFERSIZE DMA_TRANSFERSIZE -#define DMA_TRANSFERSIZE_POS (0U) -#define DMA_TRANSFERSIZE_LEN (12U) -#define DMA_TRANSFERSIZE_MSK (((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS) -#define DMA_TRANSFERSIZE_UMSK (~(((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS)) -#define DMA_SBSIZE DMA_SBSIZE -#define DMA_SBSIZE_POS (12U) -#define DMA_SBSIZE_LEN (2U) -#define DMA_SBSIZE_MSK (((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS) -#define DMA_SBSIZE_UMSK (~(((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS)) -#define DMA_DST_MIN_MODE DMA_DST_MIN_MODE -#define DMA_DST_MIN_MODE_POS (14U) -#define DMA_DST_MIN_MODE_LEN (1U) -#define DMA_DST_MIN_MODE_MSK (((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS) -#define DMA_DST_MIN_MODE_UMSK (~(((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS)) -#define DMA_DBSIZE DMA_DBSIZE -#define DMA_DBSIZE_POS (15U) -#define DMA_DBSIZE_LEN (2U) -#define DMA_DBSIZE_MSK (((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS) -#define DMA_DBSIZE_UMSK (~(((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS)) -#define DMA_DST_ADD_MODE DMA_DST_ADD_MODE -#define DMA_DST_ADD_MODE_POS (17U) -#define DMA_DST_ADD_MODE_LEN (1U) -#define DMA_DST_ADD_MODE_MSK (((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS) -#define DMA_DST_ADD_MODE_UMSK (~(((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS)) -#define DMA_SWIDTH DMA_SWIDTH -#define DMA_SWIDTH_POS (18U) -#define DMA_SWIDTH_LEN (2U) -#define DMA_SWIDTH_MSK (((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS) -#define DMA_SWIDTH_UMSK (~(((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS)) -#define DMA_DWIDTH DMA_DWIDTH -#define DMA_DWIDTH_POS (21U) -#define DMA_DWIDTH_LEN (2U) -#define DMA_DWIDTH_MSK (((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS) -#define DMA_DWIDTH_UMSK (~(((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS)) -#define DMA_FIX_CNT DMA_FIX_CNT -#define DMA_FIX_CNT_POS (23U) -#define DMA_FIX_CNT_LEN (3U) -#define DMA_FIX_CNT_MSK (((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS) -#define DMA_FIX_CNT_UMSK (~(((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS)) -#define DMA_SI DMA_SI -#define DMA_SI_POS (26U) -#define DMA_SI_LEN (1U) -#define DMA_SI_MSK (((1U << DMA_SI_LEN) - 1) << DMA_SI_POS) -#define DMA_SI_UMSK (~(((1U << DMA_SI_LEN) - 1) << DMA_SI_POS)) -#define DMA_DI DMA_DI -#define DMA_DI_POS (27U) -#define DMA_DI_LEN (1U) -#define DMA_DI_MSK (((1U << DMA_DI_LEN) - 1) << DMA_DI_POS) -#define DMA_DI_UMSK (~(((1U << DMA_DI_LEN) - 1) << DMA_DI_POS)) -#define DMA_PROT DMA_PROT -#define DMA_PROT_POS (28U) -#define DMA_PROT_LEN (3U) -#define DMA_PROT_MSK (((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS) -#define DMA_PROT_UMSK (~(((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS)) -#define DMA_I DMA_I -#define DMA_I_POS (31U) -#define DMA_I_LEN (1U) -#define DMA_I_MSK (((1U << DMA_I_LEN) - 1) << DMA_I_POS) -#define DMA_I_UMSK (~(((1U << DMA_I_LEN) - 1) << DMA_I_POS)) - -/* 0x10 : DMA_Config */ -#define DMA_CONFIG_OFFSET (0x10) -#define DMA_E DMA_E -#define DMA_E_POS (0U) -#define DMA_E_LEN (1U) -#define DMA_E_MSK (((1U << DMA_E_LEN) - 1) << DMA_E_POS) -#define DMA_E_UMSK (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS)) -#define DMA_SRCPERIPHERAL DMA_SRCPERIPHERAL -#define DMA_SRCPERIPHERAL_POS (1U) -#define DMA_SRCPERIPHERAL_LEN (5U) -#define DMA_SRCPERIPHERAL_MSK (((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS) -#define DMA_SRCPERIPHERAL_UMSK (~(((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS)) -#define DMA_DSTPERIPHERAL DMA_DSTPERIPHERAL -#define DMA_DSTPERIPHERAL_POS (6U) -#define DMA_DSTPERIPHERAL_LEN (5U) -#define DMA_DSTPERIPHERAL_MSK (((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS) -#define DMA_DSTPERIPHERAL_UMSK (~(((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS)) -#define DMA_FLOWCNTRL DMA_FLOWCNTRL -#define DMA_FLOWCNTRL_POS (11U) -#define DMA_FLOWCNTRL_LEN (3U) -#define DMA_FLOWCNTRL_MSK (((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS) -#define DMA_FLOWCNTRL_UMSK (~(((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS)) -#define DMA_IE DMA_IE -#define DMA_IE_POS (14U) -#define DMA_IE_LEN (1U) -#define DMA_IE_MSK (((1U << DMA_IE_LEN) - 1) << DMA_IE_POS) -#define DMA_IE_UMSK (~(((1U << DMA_IE_LEN) - 1) << DMA_IE_POS)) -#define DMA_ITC DMA_ITC -#define DMA_ITC_POS (15U) -#define DMA_ITC_LEN (1U) -#define DMA_ITC_MSK (((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS) -#define DMA_ITC_UMSK (~(((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS)) -#define DMA_L DMA_L -#define DMA_L_POS (16U) -#define DMA_L_LEN (1U) -#define DMA_L_MSK (((1U << DMA_L_LEN) - 1) << DMA_L_POS) -#define DMA_L_UMSK (~(((1U << DMA_L_LEN) - 1) << DMA_L_POS)) -#define DMA_A DMA_A -#define DMA_A_POS (17U) -#define DMA_A_LEN (1U) -#define DMA_A_MSK (((1U << DMA_A_LEN) - 1) << DMA_A_POS) -#define DMA_A_UMSK (~(((1U << DMA_A_LEN) - 1) << DMA_A_POS)) -#define DMA_H DMA_H -#define DMA_H_POS (18U) -#define DMA_H_LEN (1U) -#define DMA_H_MSK (((1U << DMA_H_LEN) - 1) << DMA_H_POS) -#define DMA_H_UMSK (~(((1U << DMA_H_LEN) - 1) << DMA_H_POS)) -#define DMA_LLICOUNTER DMA_LLICOUNTER -#define DMA_LLICOUNTER_POS (20U) -#define DMA_LLICOUNTER_LEN (10U) -#define DMA_LLICOUNTER_MSK (((1U << DMA_LLICOUNTER_LEN) - 1) << DMA_LLICOUNTER_POS) -#define DMA_LLICOUNTER_UMSK (~(((1U << DMA_LLICOUNTER_LEN) - 1) << DMA_LLICOUNTER_POS)) - -struct dma_channel_reg { - /* 0x0 : DMA_SrcAddr */ - union { - struct { - uint32_t SrcAddr : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_SrcAddr; - - /* 0x4 : DMA_DstAddr */ - union { - struct { - uint32_t DstAddr : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_DstAddr; - - /* 0x8 : DMA_LLI */ - union { - struct { - uint32_t LLI : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_LLI; - - /* 0xc : DMA_Control */ - union { - struct DMA_Control_Reg { - uint32_t TransferSize : 12; /* [11: 0], r/w, 0x0 */ - uint32_t SBSize : 2; /* [13:12], r/w, 0x1 */ - uint32_t dst_min_mode : 1; /* [ 14], r/w, 0x0 */ - uint32_t DBSize : 2; /* [16:15], r/w, 0x1 */ - uint32_t dst_add_mode : 1; /* [ 17], r/w, 0x0 */ - uint32_t SWidth : 2; /* [19:18], r/w, 0x2 */ - uint32_t reserved_20 : 1; /* [ 20], rsvd, 0x0 */ - uint32_t DWidth : 2; /* [22:21], r/w, 0x2 */ - uint32_t fix_cnt : 3; /* [25:23], r/w, 0x0 */ - uint32_t SI : 1; /* [ 26], r/w, 0x1 */ - uint32_t DI : 1; /* [ 27], r/w, 0x1 */ - uint32_t Prot : 3; /* [30:28], r/w, 0x0 */ - uint32_t I : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_Control; - - /* 0x10 : DMA_Config */ - union { - struct { - uint32_t E : 1; /* [ 0], r/w, 0x0 */ - uint32_t SrcPeripheral : 5; /* [ 5: 1], r/w, 0x0 */ - uint32_t DstPeripheral : 5; /* [10: 6], r/w, 0x0 */ - uint32_t FlowCntrl : 3; /* [13:11], r/w, 0x0 */ - uint32_t IE : 1; /* [ 14], r/w, 0x0 */ - uint32_t ITC : 1; /* [ 15], r/w, 0x0 */ - uint32_t L : 1; /* [ 16], r/w, 0x0 */ - uint32_t A : 1; /* [ 17], r, 0x0 */ - uint32_t H : 1; /* [ 18], r/w, 0x0 */ - uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */ - uint32_t LLICounter : 10; /* [29:20], r, 0x0 */ - uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_Config; -}; - -typedef volatile struct dma_channel_reg dma_channel_reg_t; - -#define DMA_CHANNEL_OFFSET 0x100 - -#endif /* __DMA_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsi_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsi_reg.h deleted file mode 100644 index d7154f0ba8..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsi_reg.h +++ /dev/null @@ -1,1231 +0,0 @@ -/** - ****************************************************************************** - * @file dsi_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __DSI_REG_H__ -#define __DSI_REG_H__ - -#include "bl808.h" - -/* 0x0 : dsi_config */ -#define DSI_CONFIG_OFFSET (0x0) -#define DSI_CR_HSTX_EN DSI_CR_HSTX_EN -#define DSI_CR_HSTX_EN_POS (0U) -#define DSI_CR_HSTX_EN_LEN (1U) -#define DSI_CR_HSTX_EN_MSK (((1U << DSI_CR_HSTX_EN_LEN) - 1) << DSI_CR_HSTX_EN_POS) -#define DSI_CR_HSTX_EN_UMSK (~(((1U << DSI_CR_HSTX_EN_LEN) - 1) << DSI_CR_HSTX_EN_POS)) -#define DSI_CR_LANE_NUM DSI_CR_LANE_NUM -#define DSI_CR_LANE_NUM_POS (1U) -#define DSI_CR_LANE_NUM_LEN (2U) -#define DSI_CR_LANE_NUM_MSK (((1U << DSI_CR_LANE_NUM_LEN) - 1) << DSI_CR_LANE_NUM_POS) -#define DSI_CR_LANE_NUM_UMSK (~(((1U << DSI_CR_LANE_NUM_LEN) - 1) << DSI_CR_LANE_NUM_POS)) -#define DSI_CR_HSTX_MODE DSI_CR_HSTX_MODE -#define DSI_CR_HSTX_MODE_POS (4U) -#define DSI_CR_HSTX_MODE_LEN (1U) -#define DSI_CR_HSTX_MODE_MSK (((1U << DSI_CR_HSTX_MODE_LEN) - 1) << DSI_CR_HSTX_MODE_POS) -#define DSI_CR_HSTX_MODE_UMSK (~(((1U << DSI_CR_HSTX_MODE_LEN) - 1) << DSI_CR_HSTX_MODE_POS)) -#define DSI_CR_LSE_PKT_EN DSI_CR_LSE_PKT_EN -#define DSI_CR_LSE_PKT_EN_POS (5U) -#define DSI_CR_LSE_PKT_EN_LEN (1U) -#define DSI_CR_LSE_PKT_EN_MSK (((1U << DSI_CR_LSE_PKT_EN_LEN) - 1) << DSI_CR_LSE_PKT_EN_POS) -#define DSI_CR_LSE_PKT_EN_UMSK (~(((1U << DSI_CR_LSE_PKT_EN_LEN) - 1) << DSI_CR_LSE_PKT_EN_POS)) -#define DSI_CR_LANE_MUX_SEL DSI_CR_LANE_MUX_SEL -#define DSI_CR_LANE_MUX_SEL_POS (6U) -#define DSI_CR_LANE_MUX_SEL_LEN (2U) -#define DSI_CR_LANE_MUX_SEL_MSK (((1U << DSI_CR_LANE_MUX_SEL_LEN) - 1) << DSI_CR_LANE_MUX_SEL_POS) -#define DSI_CR_LANE_MUX_SEL_UMSK (~(((1U << DSI_CR_LANE_MUX_SEL_LEN) - 1) << DSI_CR_LANE_MUX_SEL_POS)) -#define DSI_CR_DT DSI_CR_DT -#define DSI_CR_DT_POS (8U) -#define DSI_CR_DT_LEN (6U) -#define DSI_CR_DT_MSK (((1U << DSI_CR_DT_LEN) - 1) << DSI_CR_DT_POS) -#define DSI_CR_DT_UMSK (~(((1U << DSI_CR_DT_LEN) - 1) << DSI_CR_DT_POS)) -#define DSI_CR_VC DSI_CR_VC -#define DSI_CR_VC_POS (14U) -#define DSI_CR_VC_LEN (2U) -#define DSI_CR_VC_MSK (((1U << DSI_CR_VC_LEN) - 1) << DSI_CR_VC_POS) -#define DSI_CR_VC_UMSK (~(((1U << DSI_CR_VC_LEN) - 1) << DSI_CR_VC_POS)) -#define DSI_CR_HSTX_VFP DSI_CR_HSTX_VFP -#define DSI_CR_HSTX_VFP_POS (16U) -#define DSI_CR_HSTX_VFP_LEN (8U) -#define DSI_CR_HSTX_VFP_MSK (((1U << DSI_CR_HSTX_VFP_LEN) - 1) << DSI_CR_HSTX_VFP_POS) -#define DSI_CR_HSTX_VFP_UMSK (~(((1U << DSI_CR_HSTX_VFP_LEN) - 1) << DSI_CR_HSTX_VFP_POS)) -#define DSI_CR_HSTX_VSA DSI_CR_HSTX_VSA -#define DSI_CR_HSTX_VSA_POS (24U) -#define DSI_CR_HSTX_VSA_LEN (8U) -#define DSI_CR_HSTX_VSA_MSK (((1U << DSI_CR_HSTX_VSA_LEN) - 1) << DSI_CR_HSTX_VSA_POS) -#define DSI_CR_HSTX_VSA_UMSK (~(((1U << DSI_CR_HSTX_VSA_LEN) - 1) << DSI_CR_HSTX_VSA_POS)) - -/* 0x4 : dsi_esc_config */ -#define DSI_ESC_CONFIG_OFFSET (0x4) -#define DSI_CR_ESC_TX_EN DSI_CR_ESC_TX_EN -#define DSI_CR_ESC_TX_EN_POS (0U) -#define DSI_CR_ESC_TX_EN_LEN (1U) -#define DSI_CR_ESC_TX_EN_MSK (((1U << DSI_CR_ESC_TX_EN_LEN) - 1) << DSI_CR_ESC_TX_EN_POS) -#define DSI_CR_ESC_TX_EN_UMSK (~(((1U << DSI_CR_ESC_TX_EN_LEN) - 1) << DSI_CR_ESC_TX_EN_POS)) -#define DSI_CR_ESC_TX_MODE DSI_CR_ESC_TX_MODE -#define DSI_CR_ESC_TX_MODE_POS (1U) -#define DSI_CR_ESC_TX_MODE_LEN (2U) -#define DSI_CR_ESC_TX_MODE_MSK (((1U << DSI_CR_ESC_TX_MODE_LEN) - 1) << DSI_CR_ESC_TX_MODE_POS) -#define DSI_CR_ESC_TX_MODE_UMSK (~(((1U << DSI_CR_ESC_TX_MODE_LEN) - 1) << DSI_CR_ESC_TX_MODE_POS)) -#define DSI_CR_ESC_TX_ULPS_EXIT DSI_CR_ESC_TX_ULPS_EXIT -#define DSI_CR_ESC_TX_ULPS_EXIT_POS (3U) -#define DSI_CR_ESC_TX_ULPS_EXIT_LEN (1U) -#define DSI_CR_ESC_TX_ULPS_EXIT_MSK (((1U << DSI_CR_ESC_TX_ULPS_EXIT_LEN) - 1) << DSI_CR_ESC_TX_ULPS_EXIT_POS) -#define DSI_CR_ESC_TX_ULPS_EXIT_UMSK (~(((1U << DSI_CR_ESC_TX_ULPS_EXIT_LEN) - 1) << DSI_CR_ESC_TX_ULPS_EXIT_POS)) -#define DSI_CR_ESC_TX_TRIG DSI_CR_ESC_TX_TRIG -#define DSI_CR_ESC_TX_TRIG_POS (4U) -#define DSI_CR_ESC_TX_TRIG_LEN (4U) -#define DSI_CR_ESC_TX_TRIG_MSK (((1U << DSI_CR_ESC_TX_TRIG_LEN) - 1) << DSI_CR_ESC_TX_TRIG_POS) -#define DSI_CR_ESC_TX_TRIG_UMSK (~(((1U << DSI_CR_ESC_TX_TRIG_LEN) - 1) << DSI_CR_ESC_TX_TRIG_POS)) -#define DSI_CR_ESC_RX_EN DSI_CR_ESC_RX_EN -#define DSI_CR_ESC_RX_EN_POS (16U) -#define DSI_CR_ESC_RX_EN_LEN (1U) -#define DSI_CR_ESC_RX_EN_MSK (((1U << DSI_CR_ESC_RX_EN_LEN) - 1) << DSI_CR_ESC_RX_EN_POS) -#define DSI_CR_ESC_RX_EN_UMSK (~(((1U << DSI_CR_ESC_RX_EN_LEN) - 1) << DSI_CR_ESC_RX_EN_POS)) -#define DSI_ST_ESC_RX_LEN DSI_ST_ESC_RX_LEN -#define DSI_ST_ESC_RX_LEN_POS (24U) -#define DSI_ST_ESC_RX_LEN_LEN (8U) -#define DSI_ST_ESC_RX_LEN_MSK (((1U << DSI_ST_ESC_RX_LEN_LEN) - 1) << DSI_ST_ESC_RX_LEN_POS) -#define DSI_ST_ESC_RX_LEN_UMSK (~(((1U << DSI_ST_ESC_RX_LEN_LEN) - 1) << DSI_ST_ESC_RX_LEN_POS)) - -/* 0x8 : dsi_lpdt_tx_config */ -#define DSI_LPDT_TX_CONFIG_OFFSET (0x8) -#define DSI_CR_LPDT_PDLEN DSI_CR_LPDT_PDLEN -#define DSI_CR_LPDT_PDLEN_POS (0U) -#define DSI_CR_LPDT_PDLEN_LEN (8U) -#define DSI_CR_LPDT_PDLEN_MSK (((1U << DSI_CR_LPDT_PDLEN_LEN) - 1) << DSI_CR_LPDT_PDLEN_POS) -#define DSI_CR_LPDT_PDLEN_UMSK (~(((1U << DSI_CR_LPDT_PDLEN_LEN) - 1) << DSI_CR_LPDT_PDLEN_POS)) -#define DSI_CR_LPDT_VC DSI_CR_LPDT_VC -#define DSI_CR_LPDT_VC_POS (8U) -#define DSI_CR_LPDT_VC_LEN (2U) -#define DSI_CR_LPDT_VC_MSK (((1U << DSI_CR_LPDT_VC_LEN) - 1) << DSI_CR_LPDT_VC_POS) -#define DSI_CR_LPDT_VC_UMSK (~(((1U << DSI_CR_LPDT_VC_LEN) - 1) << DSI_CR_LPDT_VC_POS)) -#define DSI_CR_LPDT_DI DSI_CR_LPDT_DI -#define DSI_CR_LPDT_DI_POS (10U) -#define DSI_CR_LPDT_DI_LEN (6U) -#define DSI_CR_LPDT_DI_MSK (((1U << DSI_CR_LPDT_DI_LEN) - 1) << DSI_CR_LPDT_DI_POS) -#define DSI_CR_LPDT_DI_UMSK (~(((1U << DSI_CR_LPDT_DI_LEN) - 1) << DSI_CR_LPDT_DI_POS)) -#define DSI_CR_LPDT_WORD0 DSI_CR_LPDT_WORD0 -#define DSI_CR_LPDT_WORD0_POS (16U) -#define DSI_CR_LPDT_WORD0_LEN (8U) -#define DSI_CR_LPDT_WORD0_MSK (((1U << DSI_CR_LPDT_WORD0_LEN) - 1) << DSI_CR_LPDT_WORD0_POS) -#define DSI_CR_LPDT_WORD0_UMSK (~(((1U << DSI_CR_LPDT_WORD0_LEN) - 1) << DSI_CR_LPDT_WORD0_POS)) -#define DSI_CR_LPDT_WORD1 DSI_CR_LPDT_WORD1 -#define DSI_CR_LPDT_WORD1_POS (24U) -#define DSI_CR_LPDT_WORD1_LEN (8U) -#define DSI_CR_LPDT_WORD1_MSK (((1U << DSI_CR_LPDT_WORD1_LEN) - 1) << DSI_CR_LPDT_WORD1_POS) -#define DSI_CR_LPDT_WORD1_UMSK (~(((1U << DSI_CR_LPDT_WORD1_LEN) - 1) << DSI_CR_LPDT_WORD1_POS)) - -/* 0xC : dsi_hstx_config */ -#define DSI_HSTX_CONFIG_OFFSET (0xC) -#define DSI_CR_HSTX_PC DSI_CR_HSTX_PC -#define DSI_CR_HSTX_PC_POS (0U) -#define DSI_CR_HSTX_PC_LEN (11U) -#define DSI_CR_HSTX_PC_MSK (((1U << DSI_CR_HSTX_PC_LEN) - 1) << DSI_CR_HSTX_PC_POS) -#define DSI_CR_HSTX_PC_UMSK (~(((1U << DSI_CR_HSTX_PC_LEN) - 1) << DSI_CR_HSTX_PC_POS)) -#define DSI_CR_HSTX_OUT_TH DSI_CR_HSTX_OUT_TH -#define DSI_CR_HSTX_OUT_TH_POS (16U) -#define DSI_CR_HSTX_OUT_TH_LEN (11U) -#define DSI_CR_HSTX_OUT_TH_MSK (((1U << DSI_CR_HSTX_OUT_TH_LEN) - 1) << DSI_CR_HSTX_OUT_TH_POS) -#define DSI_CR_HSTX_OUT_TH_UMSK (~(((1U << DSI_CR_HSTX_OUT_TH_LEN) - 1) << DSI_CR_HSTX_OUT_TH_POS)) - -/* 0x10 : dsi_int_status */ -#define DSI_INT_STATUS_OFFSET (0x10) -#define DSI_INT_STATUS DSI_INT_STATUS -#define DSI_INT_STATUS_POS (0U) -#define DSI_INT_STATUS_LEN (14U) -#define DSI_INT_STATUS_MSK (((1U << DSI_INT_STATUS_LEN) - 1) << DSI_INT_STATUS_POS) -#define DSI_INT_STATUS_UMSK (~(((1U << DSI_INT_STATUS_LEN) - 1) << DSI_INT_STATUS_POS)) - -/* 0x14 : dsi_int_mask */ -#define DSI_INT_MASK_OFFSET (0x14) -#define DSI_INT_MASK DSI_INT_MASK -#define DSI_INT_MASK_POS (0U) -#define DSI_INT_MASK_LEN (14U) -#define DSI_INT_MASK_MSK (((1U << DSI_INT_MASK_LEN) - 1) << DSI_INT_MASK_POS) -#define DSI_INT_MASK_UMSK (~(((1U << DSI_INT_MASK_LEN) - 1) << DSI_INT_MASK_POS)) - -/* 0x18 : dsi_int_clear */ -#define DSI_INT_CLEAR_OFFSET (0x18) -#define DSI_INT_CLEAR DSI_INT_CLEAR -#define DSI_INT_CLEAR_POS (0U) -#define DSI_INT_CLEAR_LEN (14U) -#define DSI_INT_CLEAR_MSK (((1U << DSI_INT_CLEAR_LEN) - 1) << DSI_INT_CLEAR_POS) -#define DSI_INT_CLEAR_UMSK (~(((1U << DSI_INT_CLEAR_LEN) - 1) << DSI_INT_CLEAR_POS)) - -/* 0x1C : dsi_int_enable */ -#define DSI_INT_ENABLE_OFFSET (0x1C) -#define DSI_INT_ENABLE DSI_INT_ENABLE -#define DSI_INT_ENABLE_POS (0U) -#define DSI_INT_ENABLE_LEN (14U) -#define DSI_INT_ENABLE_MSK (((1U << DSI_INT_ENABLE_LEN) - 1) << DSI_INT_ENABLE_POS) -#define DSI_INT_ENABLE_UMSK (~(((1U << DSI_INT_ENABLE_LEN) - 1) << DSI_INT_ENABLE_POS)) - -/* 0x20 : dsi_frame_num */ -#define DSI_FRAME_NUM_OFFSET (0x20) -#define DSI_CR_FRAME_NUM DSI_CR_FRAME_NUM -#define DSI_CR_FRAME_NUM_POS (0U) -#define DSI_CR_FRAME_NUM_LEN (16U) -#define DSI_CR_FRAME_NUM_MSK (((1U << DSI_CR_FRAME_NUM_LEN) - 1) << DSI_CR_FRAME_NUM_POS) -#define DSI_CR_FRAME_NUM_UMSK (~(((1U << DSI_CR_FRAME_NUM_LEN) - 1) << DSI_CR_FRAME_NUM_POS)) -#define DSI_CR_FRAME_UPD DSI_CR_FRAME_UPD -#define DSI_CR_FRAME_UPD_POS (31U) -#define DSI_CR_FRAME_UPD_LEN (1U) -#define DSI_CR_FRAME_UPD_MSK (((1U << DSI_CR_FRAME_UPD_LEN) - 1) << DSI_CR_FRAME_UPD_POS) -#define DSI_CR_FRAME_UPD_UMSK (~(((1U << DSI_CR_FRAME_UPD_LEN) - 1) << DSI_CR_FRAME_UPD_POS)) - -/* 0x60 : dsi_fifo_config_0 */ -#define DSI_FIFO_CONFIG_0_OFFSET (0x60) -#define DSI_DMA_TX_EN DSI_DMA_TX_EN -#define DSI_DMA_TX_EN_POS (0U) -#define DSI_DMA_TX_EN_LEN (1U) -#define DSI_DMA_TX_EN_MSK (((1U << DSI_DMA_TX_EN_LEN) - 1) << DSI_DMA_TX_EN_POS) -#define DSI_DMA_TX_EN_UMSK (~(((1U << DSI_DMA_TX_EN_LEN) - 1) << DSI_DMA_TX_EN_POS)) -#define DSI_DMA_RX_EN DSI_DMA_RX_EN -#define DSI_DMA_RX_EN_POS (1U) -#define DSI_DMA_RX_EN_LEN (1U) -#define DSI_DMA_RX_EN_MSK (((1U << DSI_DMA_RX_EN_LEN) - 1) << DSI_DMA_RX_EN_POS) -#define DSI_DMA_RX_EN_UMSK (~(((1U << DSI_DMA_RX_EN_LEN) - 1) << DSI_DMA_RX_EN_POS)) -#define DSI_TX_FIFO_CLR DSI_TX_FIFO_CLR -#define DSI_TX_FIFO_CLR_POS (2U) -#define DSI_TX_FIFO_CLR_LEN (1U) -#define DSI_TX_FIFO_CLR_MSK (((1U << DSI_TX_FIFO_CLR_LEN) - 1) << DSI_TX_FIFO_CLR_POS) -#define DSI_TX_FIFO_CLR_UMSK (~(((1U << DSI_TX_FIFO_CLR_LEN) - 1) << DSI_TX_FIFO_CLR_POS)) -#define DSI_RX_FIFO_CLR DSI_RX_FIFO_CLR -#define DSI_RX_FIFO_CLR_POS (3U) -#define DSI_RX_FIFO_CLR_LEN (1U) -#define DSI_RX_FIFO_CLR_MSK (((1U << DSI_RX_FIFO_CLR_LEN) - 1) << DSI_RX_FIFO_CLR_POS) -#define DSI_RX_FIFO_CLR_UMSK (~(((1U << DSI_RX_FIFO_CLR_LEN) - 1) << DSI_RX_FIFO_CLR_POS)) -#define DSI_TX_FIFO_OVERFLOW DSI_TX_FIFO_OVERFLOW -#define DSI_TX_FIFO_OVERFLOW_POS (4U) -#define DSI_TX_FIFO_OVERFLOW_LEN (1U) -#define DSI_TX_FIFO_OVERFLOW_MSK (((1U << DSI_TX_FIFO_OVERFLOW_LEN) - 1) << DSI_TX_FIFO_OVERFLOW_POS) -#define DSI_TX_FIFO_OVERFLOW_UMSK (~(((1U << DSI_TX_FIFO_OVERFLOW_LEN) - 1) << DSI_TX_FIFO_OVERFLOW_POS)) -#define DSI_TX_FIFO_UNDERFLOW DSI_TX_FIFO_UNDERFLOW -#define DSI_TX_FIFO_UNDERFLOW_POS (5U) -#define DSI_TX_FIFO_UNDERFLOW_LEN (1U) -#define DSI_TX_FIFO_UNDERFLOW_MSK (((1U << DSI_TX_FIFO_UNDERFLOW_LEN) - 1) << DSI_TX_FIFO_UNDERFLOW_POS) -#define DSI_TX_FIFO_UNDERFLOW_UMSK (~(((1U << DSI_TX_FIFO_UNDERFLOW_LEN) - 1) << DSI_TX_FIFO_UNDERFLOW_POS)) -#define DSI_RX_FIFO_OVERFLOW DSI_RX_FIFO_OVERFLOW -#define DSI_RX_FIFO_OVERFLOW_POS (6U) -#define DSI_RX_FIFO_OVERFLOW_LEN (1U) -#define DSI_RX_FIFO_OVERFLOW_MSK (((1U << DSI_RX_FIFO_OVERFLOW_LEN) - 1) << DSI_RX_FIFO_OVERFLOW_POS) -#define DSI_RX_FIFO_OVERFLOW_UMSK (~(((1U << DSI_RX_FIFO_OVERFLOW_LEN) - 1) << DSI_RX_FIFO_OVERFLOW_POS)) -#define DSI_RX_FIFO_UNDERFLOW DSI_RX_FIFO_UNDERFLOW -#define DSI_RX_FIFO_UNDERFLOW_POS (7U) -#define DSI_RX_FIFO_UNDERFLOW_LEN (1U) -#define DSI_RX_FIFO_UNDERFLOW_MSK (((1U << DSI_RX_FIFO_UNDERFLOW_LEN) - 1) << DSI_RX_FIFO_UNDERFLOW_POS) -#define DSI_RX_FIFO_UNDERFLOW_UMSK (~(((1U << DSI_RX_FIFO_UNDERFLOW_LEN) - 1) << DSI_RX_FIFO_UNDERFLOW_POS)) - -/* 0x64 : dsi_fifo_config_1 */ -#define DSI_FIFO_CONFIG_1_OFFSET (0x64) -#define DSI_TX_FIFO_CNT DSI_TX_FIFO_CNT -#define DSI_TX_FIFO_CNT_POS (0U) -#define DSI_TX_FIFO_CNT_LEN (3U) -#define DSI_TX_FIFO_CNT_MSK (((1U << DSI_TX_FIFO_CNT_LEN) - 1) << DSI_TX_FIFO_CNT_POS) -#define DSI_TX_FIFO_CNT_UMSK (~(((1U << DSI_TX_FIFO_CNT_LEN) - 1) << DSI_TX_FIFO_CNT_POS)) -#define DSI_RX_FIFO_CNT DSI_RX_FIFO_CNT -#define DSI_RX_FIFO_CNT_POS (8U) -#define DSI_RX_FIFO_CNT_LEN (3U) -#define DSI_RX_FIFO_CNT_MSK (((1U << DSI_RX_FIFO_CNT_LEN) - 1) << DSI_RX_FIFO_CNT_POS) -#define DSI_RX_FIFO_CNT_UMSK (~(((1U << DSI_RX_FIFO_CNT_LEN) - 1) << DSI_RX_FIFO_CNT_POS)) -#define DSI_TX_FIFO_TH DSI_TX_FIFO_TH -#define DSI_TX_FIFO_TH_POS (16U) -#define DSI_TX_FIFO_TH_LEN (2U) -#define DSI_TX_FIFO_TH_MSK (((1U << DSI_TX_FIFO_TH_LEN) - 1) << DSI_TX_FIFO_TH_POS) -#define DSI_TX_FIFO_TH_UMSK (~(((1U << DSI_TX_FIFO_TH_LEN) - 1) << DSI_TX_FIFO_TH_POS)) -#define DSI_RX_FIFO_TH DSI_RX_FIFO_TH -#define DSI_RX_FIFO_TH_POS (24U) -#define DSI_RX_FIFO_TH_LEN (2U) -#define DSI_RX_FIFO_TH_MSK (((1U << DSI_RX_FIFO_TH_LEN) - 1) << DSI_RX_FIFO_TH_POS) -#define DSI_RX_FIFO_TH_UMSK (~(((1U << DSI_RX_FIFO_TH_LEN) - 1) << DSI_RX_FIFO_TH_POS)) - -/* 0x68 : dsi_fifo_wdata */ -#define DSI_FIFO_WDATA_OFFSET (0x68) -#define DSI_FIFO_WDATA DSI_FIFO_WDATA -#define DSI_FIFO_WDATA_POS (0U) -#define DSI_FIFO_WDATA_LEN (32U) -#define DSI_FIFO_WDATA_MSK (((1U << DSI_FIFO_WDATA_LEN) - 1) << DSI_FIFO_WDATA_POS) -#define DSI_FIFO_WDATA_UMSK (~(((1U << DSI_FIFO_WDATA_LEN) - 1) << DSI_FIFO_WDATA_POS)) - -/* 0x6C : dsi_fifo_rdata */ -#define DSI_FIFO_RDATA_OFFSET (0x6C) -#define DSI_FIFO_RDATA DSI_FIFO_RDATA -#define DSI_FIFO_RDATA_POS (0U) -#define DSI_FIFO_RDATA_LEN (32U) -#define DSI_FIFO_RDATA_MSK (((1U << DSI_FIFO_RDATA_LEN) - 1) << DSI_FIFO_RDATA_POS) -#define DSI_FIFO_RDATA_UMSK (~(((1U << DSI_FIFO_RDATA_LEN) - 1) << DSI_FIFO_RDATA_POS)) - -/* 0x80 : dphy_config_0 */ -#define DSI_DPHY_CONFIG_0_OFFSET (0x80) -#define DSI_CL_ENABLE DSI_CL_ENABLE -#define DSI_CL_ENABLE_POS (0U) -#define DSI_CL_ENABLE_LEN (1U) -#define DSI_CL_ENABLE_MSK (((1U << DSI_CL_ENABLE_LEN) - 1) << DSI_CL_ENABLE_POS) -#define DSI_CL_ENABLE_UMSK (~(((1U << DSI_CL_ENABLE_LEN) - 1) << DSI_CL_ENABLE_POS)) -#define DSI_CL_TXREQUESTHS DSI_CL_TXREQUESTHS -#define DSI_CL_TXREQUESTHS_POS (1U) -#define DSI_CL_TXREQUESTHS_LEN (1U) -#define DSI_CL_TXREQUESTHS_MSK (((1U << DSI_CL_TXREQUESTHS_LEN) - 1) << DSI_CL_TXREQUESTHS_POS) -#define DSI_CL_TXREQUESTHS_UMSK (~(((1U << DSI_CL_TXREQUESTHS_LEN) - 1) << DSI_CL_TXREQUESTHS_POS)) -#define DSI_CL_TXULPSCLK DSI_CL_TXULPSCLK -#define DSI_CL_TXULPSCLK_POS (2U) -#define DSI_CL_TXULPSCLK_LEN (1U) -#define DSI_CL_TXULPSCLK_MSK (((1U << DSI_CL_TXULPSCLK_LEN) - 1) << DSI_CL_TXULPSCLK_POS) -#define DSI_CL_TXULPSCLK_UMSK (~(((1U << DSI_CL_TXULPSCLK_LEN) - 1) << DSI_CL_TXULPSCLK_POS)) -#define DSI_CL_TXULPSEXIT DSI_CL_TXULPSEXIT -#define DSI_CL_TXULPSEXIT_POS (3U) -#define DSI_CL_TXULPSEXIT_LEN (1U) -#define DSI_CL_TXULPSEXIT_MSK (((1U << DSI_CL_TXULPSEXIT_LEN) - 1) << DSI_CL_TXULPSEXIT_POS) -#define DSI_CL_TXULPSEXIT_UMSK (~(((1U << DSI_CL_TXULPSEXIT_LEN) - 1) << DSI_CL_TXULPSEXIT_POS)) -#define DSI_CL_STOPSTATE DSI_CL_STOPSTATE -#define DSI_CL_STOPSTATE_POS (4U) -#define DSI_CL_STOPSTATE_LEN (1U) -#define DSI_CL_STOPSTATE_MSK (((1U << DSI_CL_STOPSTATE_LEN) - 1) << DSI_CL_STOPSTATE_POS) -#define DSI_CL_STOPSTATE_UMSK (~(((1U << DSI_CL_STOPSTATE_LEN) - 1) << DSI_CL_STOPSTATE_POS)) -#define DSI_CL_ULPSACTIVENOT DSI_CL_ULPSACTIVENOT -#define DSI_CL_ULPSACTIVENOT_POS (5U) -#define DSI_CL_ULPSACTIVENOT_LEN (1U) -#define DSI_CL_ULPSACTIVENOT_MSK (((1U << DSI_CL_ULPSACTIVENOT_LEN) - 1) << DSI_CL_ULPSACTIVENOT_POS) -#define DSI_CL_ULPSACTIVENOT_UMSK (~(((1U << DSI_CL_ULPSACTIVENOT_LEN) - 1) << DSI_CL_ULPSACTIVENOT_POS)) -#define DSI_DL0_ENABLE DSI_DL0_ENABLE -#define DSI_DL0_ENABLE_POS (8U) -#define DSI_DL0_ENABLE_LEN (1U) -#define DSI_DL0_ENABLE_MSK (((1U << DSI_DL0_ENABLE_LEN) - 1) << DSI_DL0_ENABLE_POS) -#define DSI_DL0_ENABLE_UMSK (~(((1U << DSI_DL0_ENABLE_LEN) - 1) << DSI_DL0_ENABLE_POS)) -#define DSI_DL1_ENABLE DSI_DL1_ENABLE -#define DSI_DL1_ENABLE_POS (9U) -#define DSI_DL1_ENABLE_LEN (1U) -#define DSI_DL1_ENABLE_MSK (((1U << DSI_DL1_ENABLE_LEN) - 1) << DSI_DL1_ENABLE_POS) -#define DSI_DL1_ENABLE_UMSK (~(((1U << DSI_DL1_ENABLE_LEN) - 1) << DSI_DL1_ENABLE_POS)) -#define DSI_DL2_ENABLE DSI_DL2_ENABLE -#define DSI_DL2_ENABLE_POS (10U) -#define DSI_DL2_ENABLE_LEN (1U) -#define DSI_DL2_ENABLE_MSK (((1U << DSI_DL2_ENABLE_LEN) - 1) << DSI_DL2_ENABLE_POS) -#define DSI_DL2_ENABLE_UMSK (~(((1U << DSI_DL2_ENABLE_LEN) - 1) << DSI_DL2_ENABLE_POS)) -#define DSI_DL3_ENABLE DSI_DL3_ENABLE -#define DSI_DL3_ENABLE_POS (11U) -#define DSI_DL3_ENABLE_LEN (1U) -#define DSI_DL3_ENABLE_MSK (((1U << DSI_DL3_ENABLE_LEN) - 1) << DSI_DL3_ENABLE_POS) -#define DSI_DL3_ENABLE_UMSK (~(((1U << DSI_DL3_ENABLE_LEN) - 1) << DSI_DL3_ENABLE_POS)) -#define DSI_DL0_STOPSTATE DSI_DL0_STOPSTATE -#define DSI_DL0_STOPSTATE_POS (12U) -#define DSI_DL0_STOPSTATE_LEN (1U) -#define DSI_DL0_STOPSTATE_MSK (((1U << DSI_DL0_STOPSTATE_LEN) - 1) << DSI_DL0_STOPSTATE_POS) -#define DSI_DL0_STOPSTATE_UMSK (~(((1U << DSI_DL0_STOPSTATE_LEN) - 1) << DSI_DL0_STOPSTATE_POS)) -#define DSI_DL1_STOPSTATE DSI_DL1_STOPSTATE -#define DSI_DL1_STOPSTATE_POS (13U) -#define DSI_DL1_STOPSTATE_LEN (1U) -#define DSI_DL1_STOPSTATE_MSK (((1U << DSI_DL1_STOPSTATE_LEN) - 1) << DSI_DL1_STOPSTATE_POS) -#define DSI_DL1_STOPSTATE_UMSK (~(((1U << DSI_DL1_STOPSTATE_LEN) - 1) << DSI_DL1_STOPSTATE_POS)) -#define DSI_DL2_STOPSTATE DSI_DL2_STOPSTATE -#define DSI_DL2_STOPSTATE_POS (14U) -#define DSI_DL2_STOPSTATE_LEN (1U) -#define DSI_DL2_STOPSTATE_MSK (((1U << DSI_DL2_STOPSTATE_LEN) - 1) << DSI_DL2_STOPSTATE_POS) -#define DSI_DL2_STOPSTATE_UMSK (~(((1U << DSI_DL2_STOPSTATE_LEN) - 1) << DSI_DL2_STOPSTATE_POS)) -#define DSI_DL3_STOPSTATE DSI_DL3_STOPSTATE -#define DSI_DL3_STOPSTATE_POS (15U) -#define DSI_DL3_STOPSTATE_LEN (1U) -#define DSI_DL3_STOPSTATE_MSK (((1U << DSI_DL3_STOPSTATE_LEN) - 1) << DSI_DL3_STOPSTATE_POS) -#define DSI_DL3_STOPSTATE_UMSK (~(((1U << DSI_DL3_STOPSTATE_LEN) - 1) << DSI_DL3_STOPSTATE_POS)) -#define DSI_DL0_ULPSACTIVENOT DSI_DL0_ULPSACTIVENOT -#define DSI_DL0_ULPSACTIVENOT_POS (16U) -#define DSI_DL0_ULPSACTIVENOT_LEN (1U) -#define DSI_DL0_ULPSACTIVENOT_MSK (((1U << DSI_DL0_ULPSACTIVENOT_LEN) - 1) << DSI_DL0_ULPSACTIVENOT_POS) -#define DSI_DL0_ULPSACTIVENOT_UMSK (~(((1U << DSI_DL0_ULPSACTIVENOT_LEN) - 1) << DSI_DL0_ULPSACTIVENOT_POS)) -#define DSI_DL1_ULPSACTIVENOT DSI_DL1_ULPSACTIVENOT -#define DSI_DL1_ULPSACTIVENOT_POS (17U) -#define DSI_DL1_ULPSACTIVENOT_LEN (1U) -#define DSI_DL1_ULPSACTIVENOT_MSK (((1U << DSI_DL1_ULPSACTIVENOT_LEN) - 1) << DSI_DL1_ULPSACTIVENOT_POS) -#define DSI_DL1_ULPSACTIVENOT_UMSK (~(((1U << DSI_DL1_ULPSACTIVENOT_LEN) - 1) << DSI_DL1_ULPSACTIVENOT_POS)) -#define DSI_DL2_ULPSACTIVENOT DSI_DL2_ULPSACTIVENOT -#define DSI_DL2_ULPSACTIVENOT_POS (18U) -#define DSI_DL2_ULPSACTIVENOT_LEN (1U) -#define DSI_DL2_ULPSACTIVENOT_MSK (((1U << DSI_DL2_ULPSACTIVENOT_LEN) - 1) << DSI_DL2_ULPSACTIVENOT_POS) -#define DSI_DL2_ULPSACTIVENOT_UMSK (~(((1U << DSI_DL2_ULPSACTIVENOT_LEN) - 1) << DSI_DL2_ULPSACTIVENOT_POS)) -#define DSI_DL3_ULPSACTIVENOT DSI_DL3_ULPSACTIVENOT -#define DSI_DL3_ULPSACTIVENOT_POS (19U) -#define DSI_DL3_ULPSACTIVENOT_LEN (1U) -#define DSI_DL3_ULPSACTIVENOT_MSK (((1U << DSI_DL3_ULPSACTIVENOT_LEN) - 1) << DSI_DL3_ULPSACTIVENOT_POS) -#define DSI_DL3_ULPSACTIVENOT_UMSK (~(((1U << DSI_DL3_ULPSACTIVENOT_LEN) - 1) << DSI_DL3_ULPSACTIVENOT_POS)) -#define DSI_DL0_FORCERXMODE DSI_DL0_FORCERXMODE -#define DSI_DL0_FORCERXMODE_POS (20U) -#define DSI_DL0_FORCERXMODE_LEN (1U) -#define DSI_DL0_FORCERXMODE_MSK (((1U << DSI_DL0_FORCERXMODE_LEN) - 1) << DSI_DL0_FORCERXMODE_POS) -#define DSI_DL0_FORCERXMODE_UMSK (~(((1U << DSI_DL0_FORCERXMODE_LEN) - 1) << DSI_DL0_FORCERXMODE_POS)) -#define DSI_DL1_FORCERXMODE DSI_DL1_FORCERXMODE -#define DSI_DL1_FORCERXMODE_POS (21U) -#define DSI_DL1_FORCERXMODE_LEN (1U) -#define DSI_DL1_FORCERXMODE_MSK (((1U << DSI_DL1_FORCERXMODE_LEN) - 1) << DSI_DL1_FORCERXMODE_POS) -#define DSI_DL1_FORCERXMODE_UMSK (~(((1U << DSI_DL1_FORCERXMODE_LEN) - 1) << DSI_DL1_FORCERXMODE_POS)) -#define DSI_DL2_FORCERXMODE DSI_DL2_FORCERXMODE -#define DSI_DL2_FORCERXMODE_POS (22U) -#define DSI_DL2_FORCERXMODE_LEN (1U) -#define DSI_DL2_FORCERXMODE_MSK (((1U << DSI_DL2_FORCERXMODE_LEN) - 1) << DSI_DL2_FORCERXMODE_POS) -#define DSI_DL2_FORCERXMODE_UMSK (~(((1U << DSI_DL2_FORCERXMODE_LEN) - 1) << DSI_DL2_FORCERXMODE_POS)) -#define DSI_DL3_FORCERXMODE DSI_DL3_FORCERXMODE -#define DSI_DL3_FORCERXMODE_POS (23U) -#define DSI_DL3_FORCERXMODE_LEN (1U) -#define DSI_DL3_FORCERXMODE_MSK (((1U << DSI_DL3_FORCERXMODE_LEN) - 1) << DSI_DL3_FORCERXMODE_POS) -#define DSI_DL3_FORCERXMODE_UMSK (~(((1U << DSI_DL3_FORCERXMODE_LEN) - 1) << DSI_DL3_FORCERXMODE_POS)) -#define DSI_DL0_FORCETXSTOPMODE DSI_DL0_FORCETXSTOPMODE -#define DSI_DL0_FORCETXSTOPMODE_POS (24U) -#define DSI_DL0_FORCETXSTOPMODE_LEN (1U) -#define DSI_DL0_FORCETXSTOPMODE_MSK (((1U << DSI_DL0_FORCETXSTOPMODE_LEN) - 1) << DSI_DL0_FORCETXSTOPMODE_POS) -#define DSI_DL0_FORCETXSTOPMODE_UMSK (~(((1U << DSI_DL0_FORCETXSTOPMODE_LEN) - 1) << DSI_DL0_FORCETXSTOPMODE_POS)) -#define DSI_DL1_FORCETXSTOPMODE DSI_DL1_FORCETXSTOPMODE -#define DSI_DL1_FORCETXSTOPMODE_POS (25U) -#define DSI_DL1_FORCETXSTOPMODE_LEN (1U) -#define DSI_DL1_FORCETXSTOPMODE_MSK (((1U << DSI_DL1_FORCETXSTOPMODE_LEN) - 1) << DSI_DL1_FORCETXSTOPMODE_POS) -#define DSI_DL1_FORCETXSTOPMODE_UMSK (~(((1U << DSI_DL1_FORCETXSTOPMODE_LEN) - 1) << DSI_DL1_FORCETXSTOPMODE_POS)) -#define DSI_DL2_FORCETXSTOPMODE DSI_DL2_FORCETXSTOPMODE -#define DSI_DL2_FORCETXSTOPMODE_POS (26U) -#define DSI_DL2_FORCETXSTOPMODE_LEN (1U) -#define DSI_DL2_FORCETXSTOPMODE_MSK (((1U << DSI_DL2_FORCETXSTOPMODE_LEN) - 1) << DSI_DL2_FORCETXSTOPMODE_POS) -#define DSI_DL2_FORCETXSTOPMODE_UMSK (~(((1U << DSI_DL2_FORCETXSTOPMODE_LEN) - 1) << DSI_DL2_FORCETXSTOPMODE_POS)) -#define DSI_DL3_FORCETXSTOPMODE DSI_DL3_FORCETXSTOPMODE -#define DSI_DL3_FORCETXSTOPMODE_POS (27U) -#define DSI_DL3_FORCETXSTOPMODE_LEN (1U) -#define DSI_DL3_FORCETXSTOPMODE_MSK (((1U << DSI_DL3_FORCETXSTOPMODE_LEN) - 1) << DSI_DL3_FORCETXSTOPMODE_POS) -#define DSI_DL3_FORCETXSTOPMODE_UMSK (~(((1U << DSI_DL3_FORCETXSTOPMODE_LEN) - 1) << DSI_DL3_FORCETXSTOPMODE_POS)) -#define DSI_DL0_TURNESC DSI_DL0_TURNESC -#define DSI_DL0_TURNESC_POS (30U) -#define DSI_DL0_TURNESC_LEN (1U) -#define DSI_DL0_TURNESC_MSK (((1U << DSI_DL0_TURNESC_LEN) - 1) << DSI_DL0_TURNESC_POS) -#define DSI_DL0_TURNESC_UMSK (~(((1U << DSI_DL0_TURNESC_LEN) - 1) << DSI_DL0_TURNESC_POS)) -#define DSI_RESET_N DSI_RESET_N -#define DSI_RESET_N_POS (31U) -#define DSI_RESET_N_LEN (1U) -#define DSI_RESET_N_MSK (((1U << DSI_RESET_N_LEN) - 1) << DSI_RESET_N_POS) -#define DSI_RESET_N_UMSK (~(((1U << DSI_RESET_N_LEN) - 1) << DSI_RESET_N_POS)) - -/* 0x84 : dphy_config_1 */ -#define DSI_DPHY_CONFIG_1_OFFSET (0x84) -#define DSI_REG_TIME_CK_ZERO DSI_REG_TIME_CK_ZERO -#define DSI_REG_TIME_CK_ZERO_POS (0U) -#define DSI_REG_TIME_CK_ZERO_LEN (8U) -#define DSI_REG_TIME_CK_ZERO_MSK (((1U << DSI_REG_TIME_CK_ZERO_LEN) - 1) << DSI_REG_TIME_CK_ZERO_POS) -#define DSI_REG_TIME_CK_ZERO_UMSK (~(((1U << DSI_REG_TIME_CK_ZERO_LEN) - 1) << DSI_REG_TIME_CK_ZERO_POS)) -#define DSI_REG_TIME_CK_TRAIL DSI_REG_TIME_CK_TRAIL -#define DSI_REG_TIME_CK_TRAIL_POS (8U) -#define DSI_REG_TIME_CK_TRAIL_LEN (8U) -#define DSI_REG_TIME_CK_TRAIL_MSK (((1U << DSI_REG_TIME_CK_TRAIL_LEN) - 1) << DSI_REG_TIME_CK_TRAIL_POS) -#define DSI_REG_TIME_CK_TRAIL_UMSK (~(((1U << DSI_REG_TIME_CK_TRAIL_LEN) - 1) << DSI_REG_TIME_CK_TRAIL_POS)) -#define DSI_REG_TIME_CK_EXIT DSI_REG_TIME_CK_EXIT -#define DSI_REG_TIME_CK_EXIT_POS (16U) -#define DSI_REG_TIME_CK_EXIT_LEN (8U) -#define DSI_REG_TIME_CK_EXIT_MSK (((1U << DSI_REG_TIME_CK_EXIT_LEN) - 1) << DSI_REG_TIME_CK_EXIT_POS) -#define DSI_REG_TIME_CK_EXIT_UMSK (~(((1U << DSI_REG_TIME_CK_EXIT_LEN) - 1) << DSI_REG_TIME_CK_EXIT_POS)) -#define DSI_REG_EN_LPRX_AT_ULPS DSI_REG_EN_LPRX_AT_ULPS -#define DSI_REG_EN_LPRX_AT_ULPS_POS (24U) -#define DSI_REG_EN_LPRX_AT_ULPS_LEN (1U) -#define DSI_REG_EN_LPRX_AT_ULPS_MSK (((1U << DSI_REG_EN_LPRX_AT_ULPS_LEN) - 1) << DSI_REG_EN_LPRX_AT_ULPS_POS) -#define DSI_REG_EN_LPRX_AT_ULPS_UMSK (~(((1U << DSI_REG_EN_LPRX_AT_ULPS_LEN) - 1) << DSI_REG_EN_LPRX_AT_ULPS_POS)) - -/* 0x88 : dphy_config_2 */ -#define DSI_DPHY_CONFIG_2_OFFSET (0x88) -#define DSI_REG_TIME_HS_ZERO DSI_REG_TIME_HS_ZERO -#define DSI_REG_TIME_HS_ZERO_POS (0U) -#define DSI_REG_TIME_HS_ZERO_LEN (8U) -#define DSI_REG_TIME_HS_ZERO_MSK (((1U << DSI_REG_TIME_HS_ZERO_LEN) - 1) << DSI_REG_TIME_HS_ZERO_POS) -#define DSI_REG_TIME_HS_ZERO_UMSK (~(((1U << DSI_REG_TIME_HS_ZERO_LEN) - 1) << DSI_REG_TIME_HS_ZERO_POS)) -#define DSI_REG_TIME_HS_TRAIL DSI_REG_TIME_HS_TRAIL -#define DSI_REG_TIME_HS_TRAIL_POS (8U) -#define DSI_REG_TIME_HS_TRAIL_LEN (8U) -#define DSI_REG_TIME_HS_TRAIL_MSK (((1U << DSI_REG_TIME_HS_TRAIL_LEN) - 1) << DSI_REG_TIME_HS_TRAIL_POS) -#define DSI_REG_TIME_HS_TRAIL_UMSK (~(((1U << DSI_REG_TIME_HS_TRAIL_LEN) - 1) << DSI_REG_TIME_HS_TRAIL_POS)) -#define DSI_REG_TIME_HS_PREP DSI_REG_TIME_HS_PREP -#define DSI_REG_TIME_HS_PREP_POS (16U) -#define DSI_REG_TIME_HS_PREP_LEN (8U) -#define DSI_REG_TIME_HS_PREP_MSK (((1U << DSI_REG_TIME_HS_PREP_LEN) - 1) << DSI_REG_TIME_HS_PREP_POS) -#define DSI_REG_TIME_HS_PREP_UMSK (~(((1U << DSI_REG_TIME_HS_PREP_LEN) - 1) << DSI_REG_TIME_HS_PREP_POS)) -#define DSI_REG_TIME_HS_EXIT DSI_REG_TIME_HS_EXIT -#define DSI_REG_TIME_HS_EXIT_POS (24U) -#define DSI_REG_TIME_HS_EXIT_LEN (8U) -#define DSI_REG_TIME_HS_EXIT_MSK (((1U << DSI_REG_TIME_HS_EXIT_LEN) - 1) << DSI_REG_TIME_HS_EXIT_POS) -#define DSI_REG_TIME_HS_EXIT_UMSK (~(((1U << DSI_REG_TIME_HS_EXIT_LEN) - 1) << DSI_REG_TIME_HS_EXIT_POS)) - -/* 0x8C : dphy_config_3 */ -#define DSI_DPHY_CONFIG_3_OFFSET (0x8C) -#define DSI_REG_TIME_TA_GO DSI_REG_TIME_TA_GO -#define DSI_REG_TIME_TA_GO_POS (0U) -#define DSI_REG_TIME_TA_GO_LEN (8U) -#define DSI_REG_TIME_TA_GO_MSK (((1U << DSI_REG_TIME_TA_GO_LEN) - 1) << DSI_REG_TIME_TA_GO_POS) -#define DSI_REG_TIME_TA_GO_UMSK (~(((1U << DSI_REG_TIME_TA_GO_LEN) - 1) << DSI_REG_TIME_TA_GO_POS)) -#define DSI_REG_TIME_TA_GET DSI_REG_TIME_TA_GET -#define DSI_REG_TIME_TA_GET_POS (8U) -#define DSI_REG_TIME_TA_GET_LEN (8U) -#define DSI_REG_TIME_TA_GET_MSK (((1U << DSI_REG_TIME_TA_GET_LEN) - 1) << DSI_REG_TIME_TA_GET_POS) -#define DSI_REG_TIME_TA_GET_UMSK (~(((1U << DSI_REG_TIME_TA_GET_LEN) - 1) << DSI_REG_TIME_TA_GET_POS)) -#define DSI_REG_TIME_REQRDY DSI_REG_TIME_REQRDY -#define DSI_REG_TIME_REQRDY_POS (16U) -#define DSI_REG_TIME_REQRDY_LEN (8U) -#define DSI_REG_TIME_REQRDY_MSK (((1U << DSI_REG_TIME_REQRDY_LEN) - 1) << DSI_REG_TIME_REQRDY_POS) -#define DSI_REG_TIME_REQRDY_UMSK (~(((1U << DSI_REG_TIME_REQRDY_LEN) - 1) << DSI_REG_TIME_REQRDY_POS)) -#define DSI_REG_TIME_LPX DSI_REG_TIME_LPX -#define DSI_REG_TIME_LPX_POS (24U) -#define DSI_REG_TIME_LPX_LEN (8U) -#define DSI_REG_TIME_LPX_MSK (((1U << DSI_REG_TIME_LPX_LEN) - 1) << DSI_REG_TIME_LPX_POS) -#define DSI_REG_TIME_LPX_UMSK (~(((1U << DSI_REG_TIME_LPX_LEN) - 1) << DSI_REG_TIME_LPX_POS)) - -/* 0x90 : dphy_config_4 */ -#define DSI_DPHY_CONFIG_4_OFFSET (0x90) -#define DSI_REG_TIME_WAKEUP DSI_REG_TIME_WAKEUP -#define DSI_REG_TIME_WAKEUP_POS (0U) -#define DSI_REG_TIME_WAKEUP_LEN (16U) -#define DSI_REG_TIME_WAKEUP_MSK (((1U << DSI_REG_TIME_WAKEUP_LEN) - 1) << DSI_REG_TIME_WAKEUP_POS) -#define DSI_REG_TIME_WAKEUP_UMSK (~(((1U << DSI_REG_TIME_WAKEUP_LEN) - 1) << DSI_REG_TIME_WAKEUP_POS)) - -/* 0x94 : dphy_config_5 */ -#define DSI_DPHY_CONFIG_5_OFFSET (0x94) -#define DSI_REG_TRIG3_CODE DSI_REG_TRIG3_CODE -#define DSI_REG_TRIG3_CODE_POS (0U) -#define DSI_REG_TRIG3_CODE_LEN (8U) -#define DSI_REG_TRIG3_CODE_MSK (((1U << DSI_REG_TRIG3_CODE_LEN) - 1) << DSI_REG_TRIG3_CODE_POS) -#define DSI_REG_TRIG3_CODE_UMSK (~(((1U << DSI_REG_TRIG3_CODE_LEN) - 1) << DSI_REG_TRIG3_CODE_POS)) -#define DSI_REG_TRIG2_CODE DSI_REG_TRIG2_CODE -#define DSI_REG_TRIG2_CODE_POS (8U) -#define DSI_REG_TRIG2_CODE_LEN (8U) -#define DSI_REG_TRIG2_CODE_MSK (((1U << DSI_REG_TRIG2_CODE_LEN) - 1) << DSI_REG_TRIG2_CODE_POS) -#define DSI_REG_TRIG2_CODE_UMSK (~(((1U << DSI_REG_TRIG2_CODE_LEN) - 1) << DSI_REG_TRIG2_CODE_POS)) -#define DSI_REG_TRIG1_CODE DSI_REG_TRIG1_CODE -#define DSI_REG_TRIG1_CODE_POS (16U) -#define DSI_REG_TRIG1_CODE_LEN (8U) -#define DSI_REG_TRIG1_CODE_MSK (((1U << DSI_REG_TRIG1_CODE_LEN) - 1) << DSI_REG_TRIG1_CODE_POS) -#define DSI_REG_TRIG1_CODE_UMSK (~(((1U << DSI_REG_TRIG1_CODE_LEN) - 1) << DSI_REG_TRIG1_CODE_POS)) -#define DSI_REG_TRIG0_CODE DSI_REG_TRIG0_CODE -#define DSI_REG_TRIG0_CODE_POS (24U) -#define DSI_REG_TRIG0_CODE_LEN (8U) -#define DSI_REG_TRIG0_CODE_MSK (((1U << DSI_REG_TRIG0_CODE_LEN) - 1) << DSI_REG_TRIG0_CODE_POS) -#define DSI_REG_TRIG0_CODE_UMSK (~(((1U << DSI_REG_TRIG0_CODE_LEN) - 1) << DSI_REG_TRIG0_CODE_POS)) - -/* 0x98 : dphy_config_6 */ -#define DSI_DPHY_CONFIG_6_OFFSET (0x98) -#define DSI_REG_ULPS_CODE DSI_REG_ULPS_CODE -#define DSI_REG_ULPS_CODE_POS (0U) -#define DSI_REG_ULPS_CODE_LEN (8U) -#define DSI_REG_ULPS_CODE_MSK (((1U << DSI_REG_ULPS_CODE_LEN) - 1) << DSI_REG_ULPS_CODE_POS) -#define DSI_REG_ULPS_CODE_UMSK (~(((1U << DSI_REG_ULPS_CODE_LEN) - 1) << DSI_REG_ULPS_CODE_POS)) -#define DSI_REG_LPDT_CODE DSI_REG_LPDT_CODE -#define DSI_REG_LPDT_CODE_POS (8U) -#define DSI_REG_LPDT_CODE_LEN (8U) -#define DSI_REG_LPDT_CODE_MSK (((1U << DSI_REG_LPDT_CODE_LEN) - 1) << DSI_REG_LPDT_CODE_POS) -#define DSI_REG_LPDT_CODE_UMSK (~(((1U << DSI_REG_LPDT_CODE_LEN) - 1) << DSI_REG_LPDT_CODE_POS)) - -/* 0x9C : dphy_config_7 */ -#define DSI_DPHY_CONFIG_7_OFFSET (0x9C) -#define DSI_REG_ANA_TEST_EN DSI_REG_ANA_TEST_EN -#define DSI_REG_ANA_TEST_EN_POS (0U) -#define DSI_REG_ANA_TEST_EN_LEN (1U) -#define DSI_REG_ANA_TEST_EN_MSK (((1U << DSI_REG_ANA_TEST_EN_LEN) - 1) << DSI_REG_ANA_TEST_EN_POS) -#define DSI_REG_ANA_TEST_EN_UMSK (~(((1U << DSI_REG_ANA_TEST_EN_LEN) - 1) << DSI_REG_ANA_TEST_EN_POS)) -#define DSI_REG_PT_EN DSI_REG_PT_EN -#define DSI_REG_PT_EN_POS (1U) -#define DSI_REG_PT_EN_LEN (1U) -#define DSI_REG_PT_EN_MSK (((1U << DSI_REG_PT_EN_LEN) - 1) << DSI_REG_PT_EN_POS) -#define DSI_REG_PT_EN_UMSK (~(((1U << DSI_REG_PT_EN_LEN) - 1) << DSI_REG_PT_EN_POS)) -#define DSI_REG_PT_LP_MODE DSI_REG_PT_LP_MODE -#define DSI_REG_PT_LP_MODE_POS (2U) -#define DSI_REG_PT_LP_MODE_LEN (1U) -#define DSI_REG_PT_LP_MODE_MSK (((1U << DSI_REG_PT_LP_MODE_LEN) - 1) << DSI_REG_PT_LP_MODE_POS) -#define DSI_REG_PT_LP_MODE_UMSK (~(((1U << DSI_REG_PT_LP_MODE_LEN) - 1) << DSI_REG_PT_LP_MODE_POS)) -#define DSI_REG_PT_PRBS_OR_JITT DSI_REG_PT_PRBS_OR_JITT -#define DSI_REG_PT_PRBS_OR_JITT_POS (3U) -#define DSI_REG_PT_PRBS_OR_JITT_LEN (1U) -#define DSI_REG_PT_PRBS_OR_JITT_MSK (((1U << DSI_REG_PT_PRBS_OR_JITT_LEN) - 1) << DSI_REG_PT_PRBS_OR_JITT_POS) -#define DSI_REG_PT_PRBS_OR_JITT_UMSK (~(((1U << DSI_REG_PT_PRBS_OR_JITT_LEN) - 1) << DSI_REG_PT_PRBS_OR_JITT_POS)) -#define DSI_REG_FORCE_HIZ_LP DSI_REG_FORCE_HIZ_LP -#define DSI_REG_FORCE_HIZ_LP_POS (4U) -#define DSI_REG_FORCE_HIZ_LP_LEN (4U) -#define DSI_REG_FORCE_HIZ_LP_MSK (((1U << DSI_REG_FORCE_HIZ_LP_LEN) - 1) << DSI_REG_FORCE_HIZ_LP_POS) -#define DSI_REG_FORCE_HIZ_LP_UMSK (~(((1U << DSI_REG_FORCE_HIZ_LP_LEN) - 1) << DSI_REG_FORCE_HIZ_LP_POS)) -#define DSI_REG_FORCE_HIZ_HS DSI_REG_FORCE_HIZ_HS -#define DSI_REG_FORCE_HIZ_HS_POS (8U) -#define DSI_REG_FORCE_HIZ_HS_LEN (4U) -#define DSI_REG_FORCE_HIZ_HS_MSK (((1U << DSI_REG_FORCE_HIZ_HS_LEN) - 1) << DSI_REG_FORCE_HIZ_HS_POS) -#define DSI_REG_FORCE_HIZ_HS_UMSK (~(((1U << DSI_REG_FORCE_HIZ_HS_LEN) - 1) << DSI_REG_FORCE_HIZ_HS_POS)) -#define DSI_REG_FORCE_CLK_HIZ_LP DSI_REG_FORCE_CLK_HIZ_LP -#define DSI_REG_FORCE_CLK_HIZ_LP_POS (12U) -#define DSI_REG_FORCE_CLK_HIZ_LP_LEN (1U) -#define DSI_REG_FORCE_CLK_HIZ_LP_MSK (((1U << DSI_REG_FORCE_CLK_HIZ_LP_LEN) - 1) << DSI_REG_FORCE_CLK_HIZ_LP_POS) -#define DSI_REG_FORCE_CLK_HIZ_LP_UMSK (~(((1U << DSI_REG_FORCE_CLK_HIZ_LP_LEN) - 1) << DSI_REG_FORCE_CLK_HIZ_LP_POS)) -#define DSI_REG_FORCE_CLK_HIZ_HS DSI_REG_FORCE_CLK_HIZ_HS -#define DSI_REG_FORCE_CLK_HIZ_HS_POS (13U) -#define DSI_REG_FORCE_CLK_HIZ_HS_LEN (1U) -#define DSI_REG_FORCE_CLK_HIZ_HS_MSK (((1U << DSI_REG_FORCE_CLK_HIZ_HS_LEN) - 1) << DSI_REG_FORCE_CLK_HIZ_HS_POS) -#define DSI_REG_FORCE_CLK_HIZ_HS_UMSK (~(((1U << DSI_REG_FORCE_CLK_HIZ_HS_LEN) - 1) << DSI_REG_FORCE_CLK_HIZ_HS_POS)) -#define DSI_REG_ANA_LP_TXEN_CLKLANE_ESC DSI_REG_ANA_LP_TXEN_CLKLANE_ESC -#define DSI_REG_ANA_LP_TXEN_CLKLANE_ESC_POS (14U) -#define DSI_REG_ANA_LP_TXEN_CLKLANE_ESC_LEN (1U) -#define DSI_REG_ANA_LP_TXEN_CLKLANE_ESC_MSK (((1U << DSI_REG_ANA_LP_TXEN_CLKLANE_ESC_LEN) - 1) << DSI_REG_ANA_LP_TXEN_CLKLANE_ESC_POS) -#define DSI_REG_ANA_LP_TXEN_CLKLANE_ESC_UMSK (~(((1U << DSI_REG_ANA_LP_TXEN_CLKLANE_ESC_LEN) - 1) << DSI_REG_ANA_LP_TXEN_CLKLANE_ESC_POS)) -#define DSI_REG_ANA_LP_DPTXDATA_CLKLANE_ESC DSI_REG_ANA_LP_DPTXDATA_CLKLANE_ESC -#define DSI_REG_ANA_LP_DPTXDATA_CLKLANE_ESC_POS (15U) -#define DSI_REG_ANA_LP_DPTXDATA_CLKLANE_ESC_LEN (1U) -#define DSI_REG_ANA_LP_DPTXDATA_CLKLANE_ESC_MSK (((1U << DSI_REG_ANA_LP_DPTXDATA_CLKLANE_ESC_LEN) - 1) << DSI_REG_ANA_LP_DPTXDATA_CLKLANE_ESC_POS) -#define DSI_REG_ANA_LP_DPTXDATA_CLKLANE_ESC_UMSK (~(((1U << DSI_REG_ANA_LP_DPTXDATA_CLKLANE_ESC_LEN) - 1) << DSI_REG_ANA_LP_DPTXDATA_CLKLANE_ESC_POS)) -#define DSI_REG_ANA_LP_DNTXDATA_CLKLANE_ESC DSI_REG_ANA_LP_DNTXDATA_CLKLANE_ESC -#define DSI_REG_ANA_LP_DNTXDATA_CLKLANE_ESC_POS (16U) -#define DSI_REG_ANA_LP_DNTXDATA_CLKLANE_ESC_LEN (1U) -#define DSI_REG_ANA_LP_DNTXDATA_CLKLANE_ESC_MSK (((1U << DSI_REG_ANA_LP_DNTXDATA_CLKLANE_ESC_LEN) - 1) << DSI_REG_ANA_LP_DNTXDATA_CLKLANE_ESC_POS) -#define DSI_REG_ANA_LP_DNTXDATA_CLKLANE_ESC_UMSK (~(((1U << DSI_REG_ANA_LP_DNTXDATA_CLKLANE_ESC_LEN) - 1) << DSI_REG_ANA_LP_DNTXDATA_CLKLANE_ESC_POS)) -#define DSI_REG_ANA_HS_TXEN_CLKLANE_ESC DSI_REG_ANA_HS_TXEN_CLKLANE_ESC -#define DSI_REG_ANA_HS_TXEN_CLKLANE_ESC_POS (17U) -#define DSI_REG_ANA_HS_TXEN_CLKLANE_ESC_LEN (1U) -#define DSI_REG_ANA_HS_TXEN_CLKLANE_ESC_MSK (((1U << DSI_REG_ANA_HS_TXEN_CLKLANE_ESC_LEN) - 1) << DSI_REG_ANA_HS_TXEN_CLKLANE_ESC_POS) -#define DSI_REG_ANA_HS_TXEN_CLKLANE_ESC_UMSK (~(((1U << DSI_REG_ANA_HS_TXEN_CLKLANE_ESC_LEN) - 1) << DSI_REG_ANA_HS_TXEN_CLKLANE_ESC_POS)) -#define DSI_REG_ANA_CLK_EN_ESC DSI_REG_ANA_CLK_EN_ESC -#define DSI_REG_ANA_CLK_EN_ESC_POS (18U) -#define DSI_REG_ANA_CLK_EN_ESC_LEN (1U) -#define DSI_REG_ANA_CLK_EN_ESC_MSK (((1U << DSI_REG_ANA_CLK_EN_ESC_LEN) - 1) << DSI_REG_ANA_CLK_EN_ESC_POS) -#define DSI_REG_ANA_CLK_EN_ESC_UMSK (~(((1U << DSI_REG_ANA_CLK_EN_ESC_LEN) - 1) << DSI_REG_ANA_CLK_EN_ESC_POS)) -#define DSI_REG_ANA_BYTE_REV DSI_REG_ANA_BYTE_REV -#define DSI_REG_ANA_BYTE_REV_POS (19U) -#define DSI_REG_ANA_BYTE_REV_LEN (1U) -#define DSI_REG_ANA_BYTE_REV_MSK (((1U << DSI_REG_ANA_BYTE_REV_LEN) - 1) << DSI_REG_ANA_BYTE_REV_POS) -#define DSI_REG_ANA_BYTE_REV_UMSK (~(((1U << DSI_REG_ANA_BYTE_REV_LEN) - 1) << DSI_REG_ANA_BYTE_REV_POS)) - -/* 0xA0 : dphy_config_8 */ -#define DSI_DPHY_CONFIG_8_OFFSET (0xA0) -#define DSI_REG_ANA_LPTXP_DATA DSI_REG_ANA_LPTXP_DATA -#define DSI_REG_ANA_LPTXP_DATA_POS (0U) -#define DSI_REG_ANA_LPTXP_DATA_LEN (4U) -#define DSI_REG_ANA_LPTXP_DATA_MSK (((1U << DSI_REG_ANA_LPTXP_DATA_LEN) - 1) << DSI_REG_ANA_LPTXP_DATA_POS) -#define DSI_REG_ANA_LPTXP_DATA_UMSK (~(((1U << DSI_REG_ANA_LPTXP_DATA_LEN) - 1) << DSI_REG_ANA_LPTXP_DATA_POS)) -#define DSI_REG_ANA_LPTXN_DATA DSI_REG_ANA_LPTXN_DATA -#define DSI_REG_ANA_LPTXN_DATA_POS (4U) -#define DSI_REG_ANA_LPTXN_DATA_LEN (4U) -#define DSI_REG_ANA_LPTXN_DATA_MSK (((1U << DSI_REG_ANA_LPTXN_DATA_LEN) - 1) << DSI_REG_ANA_LPTXN_DATA_POS) -#define DSI_REG_ANA_LPTXN_DATA_UMSK (~(((1U << DSI_REG_ANA_LPTXN_DATA_LEN) - 1) << DSI_REG_ANA_LPTXN_DATA_POS)) -#define DSI_REG_ANA_LPTXEN DSI_REG_ANA_LPTXEN -#define DSI_REG_ANA_LPTXEN_POS (8U) -#define DSI_REG_ANA_LPTXEN_LEN (4U) -#define DSI_REG_ANA_LPTXEN_MSK (((1U << DSI_REG_ANA_LPTXEN_LEN) - 1) << DSI_REG_ANA_LPTXEN_POS) -#define DSI_REG_ANA_LPTXEN_UMSK (~(((1U << DSI_REG_ANA_LPTXEN_LEN) - 1) << DSI_REG_ANA_LPTXEN_POS)) -#define DSI_REG_ANA_LPRXEN DSI_REG_ANA_LPRXEN -#define DSI_REG_ANA_LPRXEN_POS (12U) -#define DSI_REG_ANA_LPRXEN_LEN (4U) -#define DSI_REG_ANA_LPRXEN_MSK (((1U << DSI_REG_ANA_LPRXEN_LEN) - 1) << DSI_REG_ANA_LPRXEN_POS) -#define DSI_REG_ANA_LPRXEN_UMSK (~(((1U << DSI_REG_ANA_LPRXEN_LEN) - 1) << DSI_REG_ANA_LPRXEN_POS)) -#define DSI_REG_ANA_HSTXEN DSI_REG_ANA_HSTXEN -#define DSI_REG_ANA_HSTXEN_POS (16U) -#define DSI_REG_ANA_HSTXEN_LEN (4U) -#define DSI_REG_ANA_HSTXEN_MSK (((1U << DSI_REG_ANA_HSTXEN_LEN) - 1) << DSI_REG_ANA_HSTXEN_POS) -#define DSI_REG_ANA_HSTXEN_UMSK (~(((1U << DSI_REG_ANA_HSTXEN_LEN) - 1) << DSI_REG_ANA_HSTXEN_POS)) -#define DSI_REG_ANA_HS_TRAIL_BYTE DSI_REG_ANA_HS_TRAIL_BYTE -#define DSI_REG_ANA_HS_TRAIL_BYTE_POS (20U) -#define DSI_REG_ANA_HS_TRAIL_BYTE_LEN (4U) -#define DSI_REG_ANA_HS_TRAIL_BYTE_MSK (((1U << DSI_REG_ANA_HS_TRAIL_BYTE_LEN) - 1) << DSI_REG_ANA_HS_TRAIL_BYTE_POS) -#define DSI_REG_ANA_HS_TRAIL_BYTE_UMSK (~(((1U << DSI_REG_ANA_HS_TRAIL_BYTE_LEN) - 1) << DSI_REG_ANA_HS_TRAIL_BYTE_POS)) -#define DSI_REG_ANA_HS_SYNC_LD_BYTE DSI_REG_ANA_HS_SYNC_LD_BYTE -#define DSI_REG_ANA_HS_SYNC_LD_BYTE_POS (24U) -#define DSI_REG_ANA_HS_SYNC_LD_BYTE_LEN (4U) -#define DSI_REG_ANA_HS_SYNC_LD_BYTE_MSK (((1U << DSI_REG_ANA_HS_SYNC_LD_BYTE_LEN) - 1) << DSI_REG_ANA_HS_SYNC_LD_BYTE_POS) -#define DSI_REG_ANA_HS_SYNC_LD_BYTE_UMSK (~(((1U << DSI_REG_ANA_HS_SYNC_LD_BYTE_LEN) - 1) << DSI_REG_ANA_HS_SYNC_LD_BYTE_POS)) -#define DSI_REG_ANA_HS_P2S_SEL_BYTE DSI_REG_ANA_HS_P2S_SEL_BYTE -#define DSI_REG_ANA_HS_P2S_SEL_BYTE_POS (28U) -#define DSI_REG_ANA_HS_P2S_SEL_BYTE_LEN (4U) -#define DSI_REG_ANA_HS_P2S_SEL_BYTE_MSK (((1U << DSI_REG_ANA_HS_P2S_SEL_BYTE_LEN) - 1) << DSI_REG_ANA_HS_P2S_SEL_BYTE_POS) -#define DSI_REG_ANA_HS_P2S_SEL_BYTE_UMSK (~(((1U << DSI_REG_ANA_HS_P2S_SEL_BYTE_LEN) - 1) << DSI_REG_ANA_HS_P2S_SEL_BYTE_POS)) - -/* 0xA4 : dphy_config_9 */ -#define DSI_DPHY_CONFIG_9_OFFSET (0xA4) -#define DSI_REG_ANA_HS_DATA_OUT_BYTE DSI_REG_ANA_HS_DATA_OUT_BYTE -#define DSI_REG_ANA_HS_DATA_OUT_BYTE_POS (0U) -#define DSI_REG_ANA_HS_DATA_OUT_BYTE_LEN (32U) -#define DSI_REG_ANA_HS_DATA_OUT_BYTE_MSK (((1U << DSI_REG_ANA_HS_DATA_OUT_BYTE_LEN) - 1) << DSI_REG_ANA_HS_DATA_OUT_BYTE_POS) -#define DSI_REG_ANA_HS_DATA_OUT_BYTE_UMSK (~(((1U << DSI_REG_ANA_HS_DATA_OUT_BYTE_LEN) - 1) << DSI_REG_ANA_HS_DATA_OUT_BYTE_POS)) - -/* 0xA8 : dphy_config_10 */ -#define DSI_DPHY_CONFIG_10_OFFSET (0xA8) -#define DSI_REG_TESTBUS_SEL_LO DSI_REG_TESTBUS_SEL_LO -#define DSI_REG_TESTBUS_SEL_LO_POS (0U) -#define DSI_REG_TESTBUS_SEL_LO_LEN (4U) -#define DSI_REG_TESTBUS_SEL_LO_MSK (((1U << DSI_REG_TESTBUS_SEL_LO_LEN) - 1) << DSI_REG_TESTBUS_SEL_LO_POS) -#define DSI_REG_TESTBUS_SEL_LO_UMSK (~(((1U << DSI_REG_TESTBUS_SEL_LO_LEN) - 1) << DSI_REG_TESTBUS_SEL_LO_POS)) -#define DSI_REG_TESTBUS_SEL_HI DSI_REG_TESTBUS_SEL_HI -#define DSI_REG_TESTBUS_SEL_HI_POS (4U) -#define DSI_REG_TESTBUS_SEL_HI_LEN (4U) -#define DSI_REG_TESTBUS_SEL_HI_MSK (((1U << DSI_REG_TESTBUS_SEL_HI_LEN) - 1) << DSI_REG_TESTBUS_SEL_HI_POS) -#define DSI_REG_TESTBUS_SEL_HI_UMSK (~(((1U << DSI_REG_TESTBUS_SEL_HI_LEN) - 1) << DSI_REG_TESTBUS_SEL_HI_POS)) -#define DSI_REG_TESTBUS_HI8BSEL_8BMODE DSI_REG_TESTBUS_HI8BSEL_8BMODE -#define DSI_REG_TESTBUS_HI8BSEL_8BMODE_POS (8U) -#define DSI_REG_TESTBUS_HI8BSEL_8BMODE_LEN (1U) -#define DSI_REG_TESTBUS_HI8BSEL_8BMODE_MSK (((1U << DSI_REG_TESTBUS_HI8BSEL_8BMODE_LEN) - 1) << DSI_REG_TESTBUS_HI8BSEL_8BMODE_POS) -#define DSI_REG_TESTBUS_HI8BSEL_8BMODE_UMSK (~(((1U << DSI_REG_TESTBUS_HI8BSEL_8BMODE_LEN) - 1) << DSI_REG_TESTBUS_HI8BSEL_8BMODE_POS)) -#define DSI_REG_IMP_PU_CODE DSI_REG_IMP_PU_CODE -#define DSI_REG_IMP_PU_CODE_POS (9U) -#define DSI_REG_IMP_PU_CODE_LEN (5U) -#define DSI_REG_IMP_PU_CODE_MSK (((1U << DSI_REG_IMP_PU_CODE_LEN) - 1) << DSI_REG_IMP_PU_CODE_POS) -#define DSI_REG_IMP_PU_CODE_UMSK (~(((1U << DSI_REG_IMP_PU_CODE_LEN) - 1) << DSI_REG_IMP_PU_CODE_POS)) -#define DSI_REG_IMP_PD_CODE DSI_REG_IMP_PD_CODE -#define DSI_REG_IMP_PD_CODE_POS (14U) -#define DSI_REG_IMP_PD_CODE_LEN (5U) -#define DSI_REG_IMP_PD_CODE_MSK (((1U << DSI_REG_IMP_PD_CODE_LEN) - 1) << DSI_REG_IMP_PD_CODE_POS) -#define DSI_REG_IMP_PD_CODE_UMSK (~(((1U << DSI_REG_IMP_PD_CODE_LEN) - 1) << DSI_REG_IMP_PD_CODE_POS)) -#define DSI_REG_DPHY_VREG400MV_TRIM DSI_REG_DPHY_VREG400MV_TRIM -#define DSI_REG_DPHY_VREG400MV_TRIM_POS (19U) -#define DSI_REG_DPHY_VREG400MV_TRIM_LEN (3U) -#define DSI_REG_DPHY_VREG400MV_TRIM_MSK (((1U << DSI_REG_DPHY_VREG400MV_TRIM_LEN) - 1) << DSI_REG_DPHY_VREG400MV_TRIM_POS) -#define DSI_REG_DPHY_VREG400MV_TRIM_UMSK (~(((1U << DSI_REG_DPHY_VREG400MV_TRIM_LEN) - 1) << DSI_REG_DPHY_VREG400MV_TRIM_POS)) -#define DSI_REG_DPHY_BG_VREF_EN DSI_REG_DPHY_BG_VREF_EN -#define DSI_REG_DPHY_BG_VREF_EN_POS (22U) -#define DSI_REG_DPHY_BG_VREF_EN_LEN (1U) -#define DSI_REG_DPHY_BG_VREF_EN_MSK (((1U << DSI_REG_DPHY_BG_VREF_EN_LEN) - 1) << DSI_REG_DPHY_BG_VREF_EN_POS) -#define DSI_REG_DPHY_BG_VREF_EN_UMSK (~(((1U << DSI_REG_DPHY_BG_VREF_EN_LEN) - 1) << DSI_REG_DPHY_BG_VREF_EN_POS)) -#define DSI_REG_ANA_BG_VREF_EN DSI_REG_ANA_BG_VREF_EN -#define DSI_REG_ANA_BG_VREF_EN_POS (23U) -#define DSI_REG_ANA_BG_VREF_EN_LEN (1U) -#define DSI_REG_ANA_BG_VREF_EN_MSK (((1U << DSI_REG_ANA_BG_VREF_EN_LEN) - 1) << DSI_REG_ANA_BG_VREF_EN_POS) -#define DSI_REG_ANA_BG_VREF_EN_UMSK (~(((1U << DSI_REG_ANA_BG_VREF_EN_LEN) - 1) << DSI_REG_ANA_BG_VREF_EN_POS)) -#define DSI_REG_ANA_VREG400MV_TRIM DSI_REG_ANA_VREG400MV_TRIM -#define DSI_REG_ANA_VREG400MV_TRIM_POS (24U) -#define DSI_REG_ANA_VREG400MV_TRIM_LEN (3U) -#define DSI_REG_ANA_VREG400MV_TRIM_MSK (((1U << DSI_REG_ANA_VREG400MV_TRIM_LEN) - 1) << DSI_REG_ANA_VREG400MV_TRIM_POS) -#define DSI_REG_ANA_VREG400MV_TRIM_UMSK (~(((1U << DSI_REG_ANA_VREG400MV_TRIM_LEN) - 1) << DSI_REG_ANA_VREG400MV_TRIM_POS)) -#define DSI_REG_ANA_VREF_EN DSI_REG_ANA_VREF_EN -#define DSI_REG_ANA_VREF_EN_POS (27U) -#define DSI_REG_ANA_VREF_EN_LEN (1U) -#define DSI_REG_ANA_VREF_EN_MSK (((1U << DSI_REG_ANA_VREF_EN_LEN) - 1) << DSI_REG_ANA_VREF_EN_POS) -#define DSI_REG_ANA_VREF_EN_UMSK (~(((1U << DSI_REG_ANA_VREF_EN_LEN) - 1) << DSI_REG_ANA_VREF_EN_POS)) - -/* 0xAC : dphy_config_11 */ -#define DSI_DPHY_CONFIG_11_OFFSET (0xAC) -#define DSI_REG_DSI_ANA_0 DSI_REG_DSI_ANA_0 -#define DSI_REG_DSI_ANA_0_POS (0U) -#define DSI_REG_DSI_ANA_0_LEN (16U) -#define DSI_REG_DSI_ANA_0_MSK (((1U << DSI_REG_DSI_ANA_0_LEN) - 1) << DSI_REG_DSI_ANA_0_POS) -#define DSI_REG_DSI_ANA_0_UMSK (~(((1U << DSI_REG_DSI_ANA_0_LEN) - 1) << DSI_REG_DSI_ANA_0_POS)) -#define DSI_REG_DSI_ANA_1 DSI_REG_DSI_ANA_1 -#define DSI_REG_DSI_ANA_1_POS (16U) -#define DSI_REG_DSI_ANA_1_LEN (16U) -#define DSI_REG_DSI_ANA_1_MSK (((1U << DSI_REG_DSI_ANA_1_LEN) - 1) << DSI_REG_DSI_ANA_1_POS) -#define DSI_REG_DSI_ANA_1_UMSK (~(((1U << DSI_REG_DSI_ANA_1_LEN) - 1) << DSI_REG_DSI_ANA_1_POS)) - -/* 0xB0 : dphy_config_12 */ -#define DSI_DPHY_CONFIG_12_OFFSET (0xB0) -#define DSI_REG_DSI_ANA_2 DSI_REG_DSI_ANA_2 -#define DSI_REG_DSI_ANA_2_POS (0U) -#define DSI_REG_DSI_ANA_2_LEN (16U) -#define DSI_REG_DSI_ANA_2_MSK (((1U << DSI_REG_DSI_ANA_2_LEN) - 1) << DSI_REG_DSI_ANA_2_POS) -#define DSI_REG_DSI_ANA_2_UMSK (~(((1U << DSI_REG_DSI_ANA_2_LEN) - 1) << DSI_REG_DSI_ANA_2_POS)) - -/* 0xB4 : dphy_config_13 */ -#define DSI_DPHY_CONFIG_13_OFFSET (0xB4) -#define DSI_REG_RD_DIG_TEST_BUS DSI_REG_RD_DIG_TEST_BUS -#define DSI_REG_RD_DIG_TEST_BUS_POS (0U) -#define DSI_REG_RD_DIG_TEST_BUS_LEN (16U) -#define DSI_REG_RD_DIG_TEST_BUS_MSK (((1U << DSI_REG_RD_DIG_TEST_BUS_LEN) - 1) << DSI_REG_RD_DIG_TEST_BUS_POS) -#define DSI_REG_RD_DIG_TEST_BUS_UMSK (~(((1U << DSI_REG_RD_DIG_TEST_BUS_LEN) - 1) << DSI_REG_RD_DIG_TEST_BUS_POS)) - -/* 0xB8 : dphy_config_14 */ -#define DSI_DPHY_CONFIG_14_OFFSET (0xB8) -#define DSI_REG_PT_FREE_REP_PAT DSI_REG_PT_FREE_REP_PAT -#define DSI_REG_PT_FREE_REP_PAT_POS (0U) -#define DSI_REG_PT_FREE_REP_PAT_LEN (32U) -#define DSI_REG_PT_FREE_REP_PAT_MSK (((1U << DSI_REG_PT_FREE_REP_PAT_LEN) - 1) << DSI_REG_PT_FREE_REP_PAT_POS) -#define DSI_REG_PT_FREE_REP_PAT_UMSK (~(((1U << DSI_REG_PT_FREE_REP_PAT_LEN) - 1) << DSI_REG_PT_FREE_REP_PAT_POS)) - -/* 0xBC : dphy_config_15 */ -#define DSI_DPHY_CONFIG_15_OFFSET (0xBC) -#define DSI_REG_DSI_DC_TP_OUT_EN DSI_REG_DSI_DC_TP_OUT_EN -#define DSI_REG_DSI_DC_TP_OUT_EN_POS (0U) -#define DSI_REG_DSI_DC_TP_OUT_EN_LEN (1U) -#define DSI_REG_DSI_DC_TP_OUT_EN_MSK (((1U << DSI_REG_DSI_DC_TP_OUT_EN_LEN) - 1) << DSI_REG_DSI_DC_TP_OUT_EN_POS) -#define DSI_REG_DSI_DC_TP_OUT_EN_UMSK (~(((1U << DSI_REG_DSI_DC_TP_OUT_EN_LEN) - 1) << DSI_REG_DSI_DC_TP_OUT_EN_POS)) -#define DSI_REG_DSI_PW_AVDD1815 DSI_REG_DSI_PW_AVDD1815 -#define DSI_REG_DSI_PW_AVDD1815_POS (4U) -#define DSI_REG_DSI_PW_AVDD1815_LEN (1U) -#define DSI_REG_DSI_PW_AVDD1815_MSK (((1U << DSI_REG_DSI_PW_AVDD1815_LEN) - 1) << DSI_REG_DSI_PW_AVDD1815_POS) -#define DSI_REG_DSI_PW_AVDD1815_UMSK (~(((1U << DSI_REG_DSI_PW_AVDD1815_LEN) - 1) << DSI_REG_DSI_PW_AVDD1815_POS)) -#define DSI_REG_DPHY_PU_LDO11 DSI_REG_DPHY_PU_LDO11 -#define DSI_REG_DPHY_PU_LDO11_POS (8U) -#define DSI_REG_DPHY_PU_LDO11_LEN (1U) -#define DSI_REG_DPHY_PU_LDO11_MSK (((1U << DSI_REG_DPHY_PU_LDO11_LEN) - 1) << DSI_REG_DPHY_PU_LDO11_POS) -#define DSI_REG_DPHY_PU_LDO11_UMSK (~(((1U << DSI_REG_DPHY_PU_LDO11_LEN) - 1) << DSI_REG_DPHY_PU_LDO11_POS)) -#define DSI_REG_DPHY_SHORT_LDO11 DSI_REG_DPHY_SHORT_LDO11 -#define DSI_REG_DPHY_SHORT_LDO11_POS (12U) -#define DSI_REG_DPHY_SHORT_LDO11_LEN (1U) -#define DSI_REG_DPHY_SHORT_LDO11_MSK (((1U << DSI_REG_DPHY_SHORT_LDO11_LEN) - 1) << DSI_REG_DPHY_SHORT_LDO11_POS) -#define DSI_REG_DPHY_SHORT_LDO11_UMSK (~(((1U << DSI_REG_DPHY_SHORT_LDO11_LEN) - 1) << DSI_REG_DPHY_SHORT_LDO11_POS)) -#define DSI_REG_DPHY_LDO11_RFB_SW DSI_REG_DPHY_LDO11_RFB_SW -#define DSI_REG_DPHY_LDO11_RFB_SW_POS (16U) -#define DSI_REG_DPHY_LDO11_RFB_SW_LEN (3U) -#define DSI_REG_DPHY_LDO11_RFB_SW_MSK (((1U << DSI_REG_DPHY_LDO11_RFB_SW_LEN) - 1) << DSI_REG_DPHY_LDO11_RFB_SW_POS) -#define DSI_REG_DPHY_LDO11_RFB_SW_UMSK (~(((1U << DSI_REG_DPHY_LDO11_RFB_SW_LEN) - 1) << DSI_REG_DPHY_LDO11_RFB_SW_POS)) -#define DSI_REG_TEN_DSI_LDO DSI_REG_TEN_DSI_LDO -#define DSI_REG_TEN_DSI_LDO_POS (20U) -#define DSI_REG_TEN_DSI_LDO_LEN (1U) -#define DSI_REG_TEN_DSI_LDO_MSK (((1U << DSI_REG_TEN_DSI_LDO_LEN) - 1) << DSI_REG_TEN_DSI_LDO_POS) -#define DSI_REG_TEN_DSI_LDO_UMSK (~(((1U << DSI_REG_TEN_DSI_LDO_LEN) - 1) << DSI_REG_TEN_DSI_LDO_POS)) -#define DSI_REG_MIPI_LDO_FAST DSI_REG_MIPI_LDO_FAST -#define DSI_REG_MIPI_LDO_FAST_POS (24U) -#define DSI_REG_MIPI_LDO_FAST_LEN (1U) -#define DSI_REG_MIPI_LDO_FAST_MSK (((1U << DSI_REG_MIPI_LDO_FAST_LEN) - 1) << DSI_REG_MIPI_LDO_FAST_POS) -#define DSI_REG_MIPI_LDO_FAST_UMSK (~(((1U << DSI_REG_MIPI_LDO_FAST_LEN) - 1) << DSI_REG_MIPI_LDO_FAST_POS)) -#define DSI_REG_DSI_RST_N_PRE DSI_REG_DSI_RST_N_PRE -#define DSI_REG_DSI_RST_N_PRE_POS (28U) -#define DSI_REG_DSI_RST_N_PRE_LEN (1U) -#define DSI_REG_DSI_RST_N_PRE_MSK (((1U << DSI_REG_DSI_RST_N_PRE_LEN) - 1) << DSI_REG_DSI_RST_N_PRE_POS) -#define DSI_REG_DSI_RST_N_PRE_UMSK (~(((1U << DSI_REG_DSI_RST_N_PRE_LEN) - 1) << DSI_REG_DSI_RST_N_PRE_POS)) -#define DSI_REG_CSI_RST_N_PRE DSI_REG_CSI_RST_N_PRE -#define DSI_REG_CSI_RST_N_PRE_POS (29U) -#define DSI_REG_CSI_RST_N_PRE_LEN (1U) -#define DSI_REG_CSI_RST_N_PRE_MSK (((1U << DSI_REG_CSI_RST_N_PRE_LEN) - 1) << DSI_REG_CSI_RST_N_PRE_POS) -#define DSI_REG_CSI_RST_N_PRE_UMSK (~(((1U << DSI_REG_CSI_RST_N_PRE_LEN) - 1) << DSI_REG_CSI_RST_N_PRE_POS)) - -/* 0xC0 : dphy_config_16 */ -#define DSI_DPHY_CONFIG_16_OFFSET (0xC0) -#define DSI_REG_DSI_BYTE_CLK_INV DSI_REG_DSI_BYTE_CLK_INV -#define DSI_REG_DSI_BYTE_CLK_INV_POS (0U) -#define DSI_REG_DSI_BYTE_CLK_INV_LEN (1U) -#define DSI_REG_DSI_BYTE_CLK_INV_MSK (((1U << DSI_REG_DSI_BYTE_CLK_INV_LEN) - 1) << DSI_REG_DSI_BYTE_CLK_INV_POS) -#define DSI_REG_DSI_BYTE_CLK_INV_UMSK (~(((1U << DSI_REG_DSI_BYTE_CLK_INV_LEN) - 1) << DSI_REG_DSI_BYTE_CLK_INV_POS)) -#define DSI_REG_DSI_LPRX_CLK_INV DSI_REG_DSI_LPRX_CLK_INV -#define DSI_REG_DSI_LPRX_CLK_INV_POS (1U) -#define DSI_REG_DSI_LPRX_CLK_INV_LEN (1U) -#define DSI_REG_DSI_LPRX_CLK_INV_MSK (((1U << DSI_REG_DSI_LPRX_CLK_INV_LEN) - 1) << DSI_REG_DSI_LPRX_CLK_INV_POS) -#define DSI_REG_DSI_LPRX_CLK_INV_UMSK (~(((1U << DSI_REG_DSI_LPRX_CLK_INV_LEN) - 1) << DSI_REG_DSI_LPRX_CLK_INV_POS)) - -/* 0xFC : dummy_reg */ -#define DSI_DUMMY_REG_OFFSET (0xFC) -#define DSI_DUMMY_REG DSI_DUMMY_REG -#define DSI_DUMMY_REG_POS (0U) -#define DSI_DUMMY_REG_LEN (32U) -#define DSI_DUMMY_REG_MSK (((1U << DSI_DUMMY_REG_LEN) - 1) << DSI_DUMMY_REG_POS) -#define DSI_DUMMY_REG_UMSK (~(((1U << DSI_DUMMY_REG_LEN) - 1) << DSI_DUMMY_REG_POS)) - -struct dsi_reg { - /* 0x0 : dsi_config */ - union { - struct { - uint32_t cr_hstx_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t cr_lane_num : 2; /* [ 2: 1], r/w, 0x0 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t cr_hstx_mode : 1; /* [ 4], r/w, 0x1 */ - uint32_t cr_lse_pkt_en : 1; /* [ 5], r/w, 0x0 */ - uint32_t cr_lane_mux_sel : 2; /* [ 7: 6], r/w, 0x0 */ - uint32_t cr_dt : 6; /* [13: 8], r/w, 0x3e */ - uint32_t cr_vc : 2; /* [15:14], r/w, 0x0 */ - uint32_t cr_hstx_vfp : 8; /* [23:16], r/w, 0x2 */ - uint32_t cr_hstx_vsa : 8; /* [31:24], r/w, 0x2 */ - } BF; - uint32_t WORD; - } dsi_config; - - /* 0x4 : dsi_esc_config */ - union { - struct { - uint32_t cr_esc_tx_en : 1; /* [ 0], w1p, 0x0 */ - uint32_t cr_esc_tx_mode : 2; /* [ 2: 1], r/w, 0x0 */ - uint32_t cr_esc_tx_ulps_exit : 1; /* [ 3], w1p, 0x0 */ - uint32_t cr_esc_tx_trig : 4; /* [ 7: 4], r/w, 0x0 */ - uint32_t reserved_8_15 : 8; /* [15: 8], rsvd, 0x0 */ - uint32_t cr_esc_rx_en : 1; /* [ 16], r/w, 0x0 */ - uint32_t reserved_17_23 : 7; /* [23:17], rsvd, 0x0 */ - uint32_t st_esc_rx_len : 8; /* [31:24], r, 0x0 */ - } BF; - uint32_t WORD; - } dsi_esc_config; - - /* 0x8 : dsi_lpdt_tx_config */ - union { - struct { - uint32_t cr_lpdt_pdlen : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t cr_lpdt_vc : 2; /* [ 9: 8], r/w, 0x0 */ - uint32_t cr_lpdt_di : 6; /* [15:10], r/w, 0x0 */ - uint32_t cr_lpdt_word0 : 8; /* [23:16], r/w, 0x0 */ - uint32_t cr_lpdt_word1 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dsi_lpdt_tx_config; - - /* 0xC : dsi_hstx_config */ - union { - struct { - uint32_t cr_hstx_pc : 11; /* [10: 0], r/w, 0x500 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t cr_hstx_out_th : 11; /* [26:16], r/w, 0x348 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dsi_hstx_config; - - /* 0x10 : dsi_int_status */ - union { - struct { - uint32_t dsi_int_status : 14; /* [13: 0], r, 0x0 */ - uint32_t reserved_14_31 : 18; /* [31:14], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dsi_int_status; - - /* 0x14 : dsi_int_mask */ - union { - struct { - uint32_t dsi_int_mask : 14; /* [13: 0], r/w, 0x3fff */ - uint32_t reserved_14_31 : 18; /* [31:14], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dsi_int_mask; - - /* 0x18 : dsi_int_clear */ - union { - struct { - uint32_t dsi_int_clear : 14; /* [13: 0], w1p, 0x0 */ - uint32_t reserved_14_31 : 18; /* [31:14], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dsi_int_clear; - - /* 0x1C : dsi_int_enable */ - union { - struct { - uint32_t dsi_int_enable : 14; /* [13: 0], r/w, 0x3fff */ - uint32_t reserved_14_31 : 18; /* [31:14], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dsi_int_enable; - - /* 0x20 : dsi_frame_num */ - union { - struct { - uint32_t cr_frame_num : 16; /* [15: 0], r/w, 0x0 */ - uint32_t reserved_16_30 : 15; /* [30:16], rsvd, 0x0 */ - uint32_t cr_frame_upd : 1; /* [ 31], w1p, 0x0 */ - } BF; - uint32_t WORD; - } dsi_frame_num; - - /* 0x24 reserved */ - uint8_t RESERVED0x24[60]; - - /* 0x60 : dsi_fifo_config_0 */ - union { - struct { - uint32_t dsi_dma_tx_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t dsi_dma_rx_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t tx_fifo_clr : 1; /* [ 2], w1p, 0x0 */ - uint32_t rx_fifo_clr : 1; /* [ 3], w1p, 0x0 */ - uint32_t tx_fifo_overflow : 1; /* [ 4], r, 0x0 */ - uint32_t tx_fifo_underflow : 1; /* [ 5], r, 0x0 */ - uint32_t rx_fifo_overflow : 1; /* [ 6], r, 0x0 */ - uint32_t rx_fifo_underflow : 1; /* [ 7], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dsi_fifo_config_0; - - /* 0x64 : dsi_fifo_config_1 */ - union { - struct { - uint32_t tx_fifo_cnt : 3; /* [ 2: 0], r, 0x4 */ - uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */ - uint32_t rx_fifo_cnt : 3; /* [10: 8], r, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t tx_fifo_th : 2; /* [17:16], r/w, 0x0 */ - uint32_t reserved_18_23 : 6; /* [23:18], rsvd, 0x0 */ - uint32_t rx_fifo_th : 2; /* [25:24], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dsi_fifo_config_1; - - /* 0x68 : dsi_fifo_wdata */ - union { - struct { - uint32_t dsi_fifo_wdata : 32; /* [31: 0], w, x */ - } BF; - uint32_t WORD; - } dsi_fifo_wdata; - - /* 0x6C : dsi_fifo_rdata */ - union { - struct { - uint32_t dsi_fifo_rdata : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } dsi_fifo_rdata; - - /* 0x70 reserved */ - uint8_t RESERVED0x70[16]; - - /* 0x80 : dphy_config_0 */ - union { - struct { - uint32_t cl_enable : 1; /* [ 0], r/w, 0x0 */ - uint32_t cl_txrequesths : 1; /* [ 1], r/w, 0x0 */ - uint32_t cl_txulpsclk : 1; /* [ 2], r/w, 0x0 */ - uint32_t cl_txulpsexit : 1; /* [ 3], w1p, 0x0 */ - uint32_t cl_stopstate : 1; /* [ 4], r, 0x1 */ - uint32_t cl_ulpsactivenot : 1; /* [ 5], r, 0x1 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t dl0_enable : 1; /* [ 8], r/w, 0x0 */ - uint32_t dl1_enable : 1; /* [ 9], r/w, 0x0 */ - uint32_t dl2_enable : 1; /* [ 10], r/w, 0x0 */ - uint32_t dl3_enable : 1; /* [ 11], r/w, 0x0 */ - uint32_t dl0_stopstate : 1; /* [ 12], r, 0x1 */ - uint32_t dl1_stopstate : 1; /* [ 13], r, 0x1 */ - uint32_t dl2_stopstate : 1; /* [ 14], r, 0x1 */ - uint32_t dl3_stopstate : 1; /* [ 15], r, 0x1 */ - uint32_t dl0_ulpsactivenot : 1; /* [ 16], r, 0x1 */ - uint32_t dl1_ulpsactivenot : 1; /* [ 17], r, 0x1 */ - uint32_t dl2_ulpsactivenot : 1; /* [ 18], r, 0x1 */ - uint32_t dl3_ulpsactivenot : 1; /* [ 19], r, 0x1 */ - uint32_t dl0_forcerxmode : 1; /* [ 20], r/w, 0x0 */ - uint32_t dl1_forcerxmode : 1; /* [ 21], r/w, 0x0 */ - uint32_t dl2_forcerxmode : 1; /* [ 22], r/w, 0x0 */ - uint32_t dl3_forcerxmode : 1; /* [ 23], r/w, 0x0 */ - uint32_t dl0_forcetxstopmode : 1; /* [ 24], r/w, 0x0 */ - uint32_t dl1_forcetxstopmode : 1; /* [ 25], r/w, 0x0 */ - uint32_t dl2_forcetxstopmode : 1; /* [ 26], r/w, 0x0 */ - uint32_t dl3_forcetxstopmode : 1; /* [ 27], r/w, 0x0 */ - uint32_t reserved_28_29 : 2; /* [29:28], rsvd, 0x0 */ - uint32_t dl0_turnesc : 1; /* [ 30], w1p, 0x0 */ - uint32_t dsi_reset_n : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dphy_config_0; - - /* 0x84 : dphy_config_1 */ - union { - struct { - uint32_t reg_time_ck_zero : 8; /* [ 7: 0], r/w, 0xf */ - uint32_t reg_time_ck_trail : 8; /* [15: 8], r/w, 0x3 */ - uint32_t reg_time_ck_exit : 8; /* [23:16], r/w, 0x5 */ - uint32_t reg_en_lprx_at_ulps : 1; /* [ 24], r/w, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dphy_config_1; - - /* 0x88 : dphy_config_2 */ - union { - struct { - uint32_t reg_time_hs_zero : 8; /* [ 7: 0], r/w, 0x5 */ - uint32_t reg_time_hs_trail : 8; /* [15: 8], r/w, 0x3 */ - uint32_t reg_time_hs_prep : 8; /* [23:16], r/w, 0x2 */ - uint32_t reg_time_hs_exit : 8; /* [31:24], r/w, 0x5 */ - } BF; - uint32_t WORD; - } dphy_config_2; - - /* 0x8C : dphy_config_3 */ - union { - struct { - uint32_t reg_time_ta_go : 8; /* [ 7: 0], r/w, 0xc */ - uint32_t reg_time_ta_get : 8; /* [15: 8], r/w, 0xf */ - uint32_t reg_time_reqrdy : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_time_lpx : 8; /* [31:24], r/w, 0x3 */ - } BF; - uint32_t WORD; - } dphy_config_3; - - /* 0x90 : dphy_config_4 */ - union { - struct { - uint32_t reg_time_wakeup : 16; /* [15: 0], r/w, 0x9c41 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dphy_config_4; - - /* 0x94 : dphy_config_5 */ - union { - struct { - uint32_t reg_trig3_code : 8; /* [ 7: 0], r/w, 0x5 */ - uint32_t reg_trig2_code : 8; /* [15: 8], r/w, 0x84 */ - uint32_t reg_trig1_code : 8; /* [23:16], r/w, 0xba */ - uint32_t reg_trig0_code : 8; /* [31:24], r/w, 0x46 */ - } BF; - uint32_t WORD; - } dphy_config_5; - - /* 0x98 : dphy_config_6 */ - union { - struct { - uint32_t reg_ulps_code : 8; /* [ 7: 0], r/w, 0x78 */ - uint32_t reg_lpdt_code : 8; /* [15: 8], r/w, 0x87 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dphy_config_6; - - /* 0x9C : dphy_config_7 */ - union { - struct { - uint32_t reg_ana_test_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t reg_pt_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t reg_pt_lp_mode : 1; /* [ 2], r/w, 0x0 */ - uint32_t reg_pt_prbs_or_jitt : 1; /* [ 3], r/w, 0x0 */ - uint32_t reg_force_hiz_lp : 4; /* [ 7: 4], r/w, 0x0 */ - uint32_t reg_force_hiz_hs : 4; /* [11: 8], r/w, 0x0 */ - uint32_t reg_force_clk_hiz_lp : 1; /* [ 12], r/w, 0x0 */ - uint32_t reg_force_clk_hiz_hs : 1; /* [ 13], r/w, 0x0 */ - uint32_t reg_ana_lp_txen_clklane_esc : 1; /* [ 14], r/w, 0x0 */ - uint32_t reg_ana_lp_dptxdata_clklane_esc : 1; /* [ 15], r/w, 0x0 */ - uint32_t reg_ana_lp_dntxdata_clklane_esc : 1; /* [ 16], r/w, 0x0 */ - uint32_t reg_ana_hs_txen_clklane_esc : 1; /* [ 17], r/w, 0x0 */ - uint32_t reg_ana_clk_en_esc : 1; /* [ 18], r/w, 0x0 */ - uint32_t reg_ana_byte_rev : 1; /* [ 19], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dphy_config_7; - - /* 0xA0 : dphy_config_8 */ - union { - struct { - uint32_t reg_ana_lptxp_data : 4; /* [ 3: 0], r/w, 0x0 */ - uint32_t reg_ana_lptxn_data : 4; /* [ 7: 4], r/w, 0x0 */ - uint32_t reg_ana_lptxen : 4; /* [11: 8], r/w, 0x0 */ - uint32_t reg_ana_lprxen : 4; /* [15:12], r/w, 0x0 */ - uint32_t reg_ana_hstxen : 4; /* [19:16], r/w, 0x0 */ - uint32_t reg_ana_hs_trail_byte : 4; /* [23:20], r/w, 0x0 */ - uint32_t reg_ana_hs_sync_ld_byte : 4; /* [27:24], r/w, 0x0 */ - uint32_t reg_ana_hs_p2s_sel_byte : 4; /* [31:28], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dphy_config_8; - - /* 0xA4 : dphy_config_9 */ - union { - struct { - uint32_t reg_ana_hs_data_out_byte : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dphy_config_9; - - /* 0xA8 : dphy_config_10 */ - union { - struct { - uint32_t reg_testbus_sel_lo : 4; /* [ 3: 0], r/w, 0x0 */ - uint32_t reg_testbus_sel_hi : 4; /* [ 7: 4], r/w, 0x0 */ - uint32_t reg_testbus_hi8bsel_8bmode : 1; /* [ 8], r/w, 0x0 */ - uint32_t reg_imp_pu_code : 5; /* [13: 9], r/w, 0x8 */ - uint32_t reg_imp_pd_code : 5; /* [18:14], r/w, 0x9 */ - uint32_t reg_dphy_vreg400mv_trim : 3; /* [21:19], r/w, 0x0 */ - uint32_t reg_dphy_bg_vref_en : 1; /* [ 22], r/w, 0x0 */ - uint32_t reg_ana_bg_vref_en : 1; /* [ 23], r/w, 0x0 */ - uint32_t reg_ana_vreg400mv_trim : 3; /* [26:24], r/w, 0x0 */ - uint32_t reg_ana_vref_en : 1; /* [ 27], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dphy_config_10; - - /* 0xAC : dphy_config_11 */ - union { - struct { - uint32_t reg_dsi_ana_0 : 16; /* [15: 0], r/w, 0xc14 */ - uint32_t reg_dsi_ana_1 : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dphy_config_11; - - /* 0xB0 : dphy_config_12 */ - union { - struct { - uint32_t reg_dsi_ana_2 : 16; /* [15: 0], r/w, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dphy_config_12; - - /* 0xB4 : dphy_config_13 */ - union { - struct { - uint32_t reg_rd_dig_test_bus : 16; /* [15: 0], r, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dphy_config_13; - - /* 0xB8 : dphy_config_14 */ - union { - struct { - uint32_t reg_pt_free_rep_pat : 32; /* [31: 0], r/w, 0x87654321 */ - } BF; - uint32_t WORD; - } dphy_config_14; - - /* 0xBC : dphy_config_15 */ - union { - struct { - uint32_t reg_dsi_dc_tp_out_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ - uint32_t reg_dsi_pw_avdd1815 : 1; /* [ 4], r/w, 0x0 */ - uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ - uint32_t reg_dphy_pu_ldo11 : 1; /* [ 8], r/w, 0x1 */ - uint32_t reserved_9_11 : 3; /* [11: 9], rsvd, 0x0 */ - uint32_t reg_dphy_short_ldo11 : 1; /* [ 12], r/w, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t reg_dphy_ldo11_rfb_sw : 3; /* [18:16], r/w, 0x4 */ - uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */ - uint32_t reg_ten_dsi_ldo : 1; /* [ 20], r/w, 0x0 */ - uint32_t reserved_21_23 : 3; /* [23:21], rsvd, 0x0 */ - uint32_t reg_mipi_ldo_fast : 1; /* [ 24], r/w, 0x0 */ - uint32_t reserved_25_27 : 3; /* [27:25], rsvd, 0x0 */ - uint32_t reg_dsi_rst_n_pre : 1; /* [ 28], r/w, 0x0 */ - uint32_t reg_csi_rst_n_pre : 1; /* [ 29], r/w, 0x0 */ - uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dphy_config_15; - - /* 0xC0 : dphy_config_16 */ - union { - struct { - uint32_t reg_dsi_byte_clk_inv : 1; /* [ 0], r/w, 0x0 */ - uint32_t reg_dsi_lprx_clk_inv : 1; /* [ 1], r/w, 0x0 */ - uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dphy_config_16; - - /* 0xc4 reserved */ - uint8_t RESERVED0xc4[56]; - - /* 0xFC : dummy_reg */ - union { - struct { - uint32_t dummy_reg : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dummy_reg; -}; - -typedef volatile struct dsi_reg dsi_reg_t; - -#endif /* __DSI_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_auto_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_auto_reg.h deleted file mode 100644 index 9602494e27..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_auto_reg.h +++ /dev/null @@ -1,201 +0,0 @@ -/** - ****************************************************************************** - * @file dsp2_auto_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __DSP2_AUTO_REG_H__ -#define __DSP2_AUTO_REG_H__ - -#include "bl808.h" - -/* 0x444 : afwas */ -#define DSP2_AUTO_AFWAS_OFFSET (0x444) -#define DSP2_AUTO_AFWASX_W DSP2_AUTO_AFWASX_W -#define DSP2_AUTO_AFWASX_W_POS (16U) -#define DSP2_AUTO_AFWASX_W_LEN (8U) -#define DSP2_AUTO_AFWASX_W_MSK (((1U << DSP2_AUTO_AFWASX_W_LEN) - 1) << DSP2_AUTO_AFWASX_W_POS) -#define DSP2_AUTO_AFWASX_W_UMSK (~(((1U << DSP2_AUTO_AFWASX_W_LEN) - 1) << DSP2_AUTO_AFWASX_W_POS)) -#define DSP2_AUTO_AFWASY_W DSP2_AUTO_AFWASY_W -#define DSP2_AUTO_AFWASY_W_POS (24U) -#define DSP2_AUTO_AFWASY_W_LEN (8U) -#define DSP2_AUTO_AFWASY_W_MSK (((1U << DSP2_AUTO_AFWASY_W_LEN) - 1) << DSP2_AUTO_AFWASY_W_POS) -#define DSP2_AUTO_AFWASY_W_UMSK (~(((1U << DSP2_AUTO_AFWASY_W_LEN) - 1) << DSP2_AUTO_AFWASY_W_POS)) - -/* 0x448 : afwae_afwbs */ -#define DSP2_AUTO_AFWAE_AFWBS_OFFSET (0x448) -#define DSP2_AUTO_AFWAEX_W DSP2_AUTO_AFWAEX_W -#define DSP2_AUTO_AFWAEX_W_POS (0U) -#define DSP2_AUTO_AFWAEX_W_LEN (8U) -#define DSP2_AUTO_AFWAEX_W_MSK (((1U << DSP2_AUTO_AFWAEX_W_LEN) - 1) << DSP2_AUTO_AFWAEX_W_POS) -#define DSP2_AUTO_AFWAEX_W_UMSK (~(((1U << DSP2_AUTO_AFWAEX_W_LEN) - 1) << DSP2_AUTO_AFWAEX_W_POS)) -#define DSP2_AUTO_AFWAEY_W DSP2_AUTO_AFWAEY_W -#define DSP2_AUTO_AFWAEY_W_POS (8U) -#define DSP2_AUTO_AFWAEY_W_LEN (8U) -#define DSP2_AUTO_AFWAEY_W_MSK (((1U << DSP2_AUTO_AFWAEY_W_LEN) - 1) << DSP2_AUTO_AFWAEY_W_POS) -#define DSP2_AUTO_AFWAEY_W_UMSK (~(((1U << DSP2_AUTO_AFWAEY_W_LEN) - 1) << DSP2_AUTO_AFWAEY_W_POS)) -#define DSP2_AUTO_AFWBSX_W DSP2_AUTO_AFWBSX_W -#define DSP2_AUTO_AFWBSX_W_POS (16U) -#define DSP2_AUTO_AFWBSX_W_LEN (8U) -#define DSP2_AUTO_AFWBSX_W_MSK (((1U << DSP2_AUTO_AFWBSX_W_LEN) - 1) << DSP2_AUTO_AFWBSX_W_POS) -#define DSP2_AUTO_AFWBSX_W_UMSK (~(((1U << DSP2_AUTO_AFWBSX_W_LEN) - 1) << DSP2_AUTO_AFWBSX_W_POS)) -#define DSP2_AUTO_AFWBSY_W DSP2_AUTO_AFWBSY_W -#define DSP2_AUTO_AFWBSY_W_POS (24U) -#define DSP2_AUTO_AFWBSY_W_LEN (8U) -#define DSP2_AUTO_AFWBSY_W_MSK (((1U << DSP2_AUTO_AFWBSY_W_LEN) - 1) << DSP2_AUTO_AFWBSY_W_POS) -#define DSP2_AUTO_AFWBSY_W_UMSK (~(((1U << DSP2_AUTO_AFWBSY_W_LEN) - 1) << DSP2_AUTO_AFWBSY_W_POS)) - -/* 0x44C : afbae_afmisc */ -#define DSP2_AUTO_AFBAE_AFMISC_OFFSET (0x44C) -#define DSP2_AUTO_AFWBEX_W DSP2_AUTO_AFWBEX_W -#define DSP2_AUTO_AFWBEX_W_POS (0U) -#define DSP2_AUTO_AFWBEX_W_LEN (8U) -#define DSP2_AUTO_AFWBEX_W_MSK (((1U << DSP2_AUTO_AFWBEX_W_LEN) - 1) << DSP2_AUTO_AFWBEX_W_POS) -#define DSP2_AUTO_AFWBEX_W_UMSK (~(((1U << DSP2_AUTO_AFWBEX_W_LEN) - 1) << DSP2_AUTO_AFWBEX_W_POS)) -#define DSP2_AUTO_AFWBEY_W DSP2_AUTO_AFWBEY_W -#define DSP2_AUTO_AFWBEY_W_POS (8U) -#define DSP2_AUTO_AFWBEY_W_LEN (8U) -#define DSP2_AUTO_AFWBEY_W_MSK (((1U << DSP2_AUTO_AFWBEY_W_LEN) - 1) << DSP2_AUTO_AFWBEY_W_POS) -#define DSP2_AUTO_AFWBEY_W_UMSK (~(((1U << DSP2_AUTO_AFWBEY_W_LEN) - 1) << DSP2_AUTO_AFWBEY_W_POS)) -#define DSP2_AUTO_FCORE2_W DSP2_AUTO_FCORE2_W -#define DSP2_AUTO_FCORE2_W_POS (16U) -#define DSP2_AUTO_FCORE2_W_LEN (4U) -#define DSP2_AUTO_FCORE2_W_MSK (((1U << DSP2_AUTO_FCORE2_W_LEN) - 1) << DSP2_AUTO_FCORE2_W_POS) -#define DSP2_AUTO_FCORE2_W_UMSK (~(((1U << DSP2_AUTO_FCORE2_W_LEN) - 1) << DSP2_AUTO_FCORE2_W_POS)) -#define DSP2_AUTO_FCORE1_W DSP2_AUTO_FCORE1_W -#define DSP2_AUTO_FCORE1_W_POS (20U) -#define DSP2_AUTO_FCORE1_W_LEN (4U) -#define DSP2_AUTO_FCORE1_W_MSK (((1U << DSP2_AUTO_FCORE1_W_LEN) - 1) << DSP2_AUTO_FCORE1_W_POS) -#define DSP2_AUTO_FCORE1_W_UMSK (~(((1U << DSP2_AUTO_FCORE1_W_LEN) - 1) << DSP2_AUTO_FCORE1_W_POS)) -#define DSP2_AUTO_AFGAMMA_W DSP2_AUTO_AFGAMMA_W -#define DSP2_AUTO_AFGAMMA_W_POS (24U) -#define DSP2_AUTO_AFGAMMA_W_LEN (3U) -#define DSP2_AUTO_AFGAMMA_W_MSK (((1U << DSP2_AUTO_AFGAMMA_W_LEN) - 1) << DSP2_AUTO_AFGAMMA_W_POS) -#define DSP2_AUTO_AFGAMMA_W_UMSK (~(((1U << DSP2_AUTO_AFGAMMA_W_LEN) - 1) << DSP2_AUTO_AFGAMMA_W_POS)) -#define DSP2_AUTO_SUM_SHIFT_B_W DSP2_AUTO_SUM_SHIFT_B_W -#define DSP2_AUTO_SUM_SHIFT_B_W_POS (27U) -#define DSP2_AUTO_SUM_SHIFT_B_W_LEN (3U) -#define DSP2_AUTO_SUM_SHIFT_B_W_MSK (((1U << DSP2_AUTO_SUM_SHIFT_B_W_LEN) - 1) << DSP2_AUTO_SUM_SHIFT_B_W_POS) -#define DSP2_AUTO_SUM_SHIFT_B_W_UMSK (~(((1U << DSP2_AUTO_SUM_SHIFT_B_W_LEN) - 1) << DSP2_AUTO_SUM_SHIFT_B_W_POS)) -#define DSP2_AUTO_SUM_SHIFT_A_W DSP2_AUTO_SUM_SHIFT_A_W -#define DSP2_AUTO_SUM_SHIFT_A_W_POS (30U) -#define DSP2_AUTO_SUM_SHIFT_A_W_LEN (2U) -#define DSP2_AUTO_SUM_SHIFT_A_W_MSK (((1U << DSP2_AUTO_SUM_SHIFT_A_W_LEN) - 1) << DSP2_AUTO_SUM_SHIFT_A_W_POS) -#define DSP2_AUTO_SUM_SHIFT_A_W_UMSK (~(((1U << DSP2_AUTO_SUM_SHIFT_A_W_LEN) - 1) << DSP2_AUTO_SUM_SHIFT_A_W_POS)) - -/* 0x450 : afwah */ -#define DSP2_AUTO_AFWAH_OFFSET (0x450) -#define DSP2_AUTO_AFWAH1_R DSP2_AUTO_AFWAH1_R -#define DSP2_AUTO_AFWAH1_R_POS (0U) -#define DSP2_AUTO_AFWAH1_R_LEN (16U) -#define DSP2_AUTO_AFWAH1_R_MSK (((1U << DSP2_AUTO_AFWAH1_R_LEN) - 1) << DSP2_AUTO_AFWAH1_R_POS) -#define DSP2_AUTO_AFWAH1_R_UMSK (~(((1U << DSP2_AUTO_AFWAH1_R_LEN) - 1) << DSP2_AUTO_AFWAH1_R_POS)) -#define DSP2_AUTO_AFWAH2_R DSP2_AUTO_AFWAH2_R -#define DSP2_AUTO_AFWAH2_R_POS (16U) -#define DSP2_AUTO_AFWAH2_R_LEN (16U) -#define DSP2_AUTO_AFWAH2_R_MSK (((1U << DSP2_AUTO_AFWAH2_R_LEN) - 1) << DSP2_AUTO_AFWAH2_R_POS) -#define DSP2_AUTO_AFWAH2_R_UMSK (~(((1U << DSP2_AUTO_AFWAH2_R_LEN) - 1) << DSP2_AUTO_AFWAH2_R_POS)) - -/* 0x454 : afwbh */ -#define DSP2_AUTO_AFWBH_OFFSET (0x454) -#define DSP2_AUTO_AFWBH1_R DSP2_AUTO_AFWBH1_R -#define DSP2_AUTO_AFWBH1_R_POS (0U) -#define DSP2_AUTO_AFWBH1_R_LEN (16U) -#define DSP2_AUTO_AFWBH1_R_MSK (((1U << DSP2_AUTO_AFWBH1_R_LEN) - 1) << DSP2_AUTO_AFWBH1_R_POS) -#define DSP2_AUTO_AFWBH1_R_UMSK (~(((1U << DSP2_AUTO_AFWBH1_R_LEN) - 1) << DSP2_AUTO_AFWBH1_R_POS)) -#define DSP2_AUTO_AFWBH2_R DSP2_AUTO_AFWBH2_R -#define DSP2_AUTO_AFWBH2_R_POS (16U) -#define DSP2_AUTO_AFWBH2_R_LEN (16U) -#define DSP2_AUTO_AFWBH2_R_MSK (((1U << DSP2_AUTO_AFWBH2_R_LEN) - 1) << DSP2_AUTO_AFWBH2_R_POS) -#define DSP2_AUTO_AFWBH2_R_UMSK (~(((1U << DSP2_AUTO_AFWBH2_R_LEN) - 1) << DSP2_AUTO_AFWBH2_R_POS)) - -struct dsp2_auto_reg { - /* 0x0 reserved */ - uint8_t RESERVED0x0[1092]; - - /* 0x444 : afwas */ - union { - struct { - uint32_t reserved_0_15 : 16; /* [15: 0], rsvd, 0x0 */ - uint32_t afwasx_w : 8; /* [23:16], r/w, 0x0 */ - uint32_t afwasy_w : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } afwas; - - /* 0x448 : afwae_afwbs */ - union { - struct { - uint32_t afwaex_w : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t afwaey_w : 8; /* [15: 8], r/w, 0x0 */ - uint32_t afwbsx_w : 8; /* [23:16], r/w, 0x0 */ - uint32_t afwbsy_w : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } afwae_afwbs; - - /* 0x44C : afbae_afmisc */ - union { - struct { - uint32_t afwbex_w : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t afwbey_w : 8; /* [15: 8], r/w, 0x0 */ - uint32_t fcore2_w : 4; /* [19:16], r/w, 0x0 */ - uint32_t fcore1_w : 4; /* [23:20], r/w, 0x0 */ - uint32_t AFGamma_w : 3; /* [26:24], r/w, 0x0 */ - uint32_t sum_shift_b_w : 3; /* [29:27], r/w, 0x0 */ - uint32_t sum_shift_a_w : 2; /* [31:30], r/w, 0x0 */ - } BF; - uint32_t WORD; - } afbae_afmisc; - - /* 0x450 : afwah */ - union { - struct { - uint32_t afwah1_r : 16; /* [15: 0], r, 0x0 */ - uint32_t afwah2_r : 16; /* [31:16], r, 0x0 */ - } BF; - uint32_t WORD; - } afwah; - - /* 0x454 : afwbh */ - union { - struct { - uint32_t afwbh1_r : 16; /* [15: 0], r, 0x0 */ - uint32_t afwbh2_r : 16; /* [31:16], r, 0x0 */ - } BF; - uint32_t WORD; - } afwbh; -}; - -typedef volatile struct dsp2_auto_reg dsp2_auto_reg_t; - -#endif /* __DSP2_AUTO_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_axi_ctrl_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_axi_ctrl_reg.h deleted file mode 100644 index 8d4e6b4e64..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_axi_ctrl_reg.h +++ /dev/null @@ -1,336 +0,0 @@ -/** - ****************************************************************************** - * @file dsp2_axi_ctrl_reg.h - * @version V1.0 - * @date 2021-07-19 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __DSP2_AXI_CTRL_REG_H__ -#define __DSP2_AXI_CTRL_REG_H__ - -#include "bl808.h" - -/* 0x0 : nr_control */ -#define DSP2_AXI_CTRL_NR_CONTROL_OFFSET (0x0) -#define DSP2_AXI_CTRL_REG_ENABLE DSP2_AXI_CTRL_REG_ENABLE -#define DSP2_AXI_CTRL_REG_ENABLE_POS (0U) -#define DSP2_AXI_CTRL_REG_ENABLE_LEN (1U) -#define DSP2_AXI_CTRL_REG_ENABLE_MSK (((1U << DSP2_AXI_CTRL_REG_ENABLE_LEN) - 1) << DSP2_AXI_CTRL_REG_ENABLE_POS) -#define DSP2_AXI_CTRL_REG_ENABLE_UMSK (~(((1U << DSP2_AXI_CTRL_REG_ENABLE_LEN) - 1) << DSP2_AXI_CTRL_REG_ENABLE_POS)) -#define DSP2_AXI_CTRL_REG_DRAIN_CLR DSP2_AXI_CTRL_REG_DRAIN_CLR -#define DSP2_AXI_CTRL_REG_DRAIN_CLR_POS (1U) -#define DSP2_AXI_CTRL_REG_DRAIN_CLR_LEN (1U) -#define DSP2_AXI_CTRL_REG_DRAIN_CLR_MSK (((1U << DSP2_AXI_CTRL_REG_DRAIN_CLR_LEN) - 1) << DSP2_AXI_CTRL_REG_DRAIN_CLR_POS) -#define DSP2_AXI_CTRL_REG_DRAIN_CLR_UMSK (~(((1U << DSP2_AXI_CTRL_REG_DRAIN_CLR_LEN) - 1) << DSP2_AXI_CTRL_REG_DRAIN_CLR_POS)) -#define DSP2_AXI_CTRL_REG_OVERFLOW_CLR DSP2_AXI_CTRL_REG_OVERFLOW_CLR -#define DSP2_AXI_CTRL_REG_OVERFLOW_CLR_POS (2U) -#define DSP2_AXI_CTRL_REG_OVERFLOW_CLR_LEN (1U) -#define DSP2_AXI_CTRL_REG_OVERFLOW_CLR_MSK (((1U << DSP2_AXI_CTRL_REG_OVERFLOW_CLR_LEN) - 1) << DSP2_AXI_CTRL_REG_OVERFLOW_CLR_POS) -#define DSP2_AXI_CTRL_REG_OVERFLOW_CLR_UMSK (~(((1U << DSP2_AXI_CTRL_REG_OVERFLOW_CLR_LEN) - 1) << DSP2_AXI_CTRL_REG_OVERFLOW_CLR_POS)) -#define DSP2_AXI_CTRL_REG_XLEN DSP2_AXI_CTRL_REG_XLEN -#define DSP2_AXI_CTRL_REG_XLEN_POS (4U) -#define DSP2_AXI_CTRL_REG_XLEN_LEN (3U) -#define DSP2_AXI_CTRL_REG_XLEN_MSK (((1U << DSP2_AXI_CTRL_REG_XLEN_LEN) - 1) << DSP2_AXI_CTRL_REG_XLEN_POS) -#define DSP2_AXI_CTRL_REG_XLEN_UMSK (~(((1U << DSP2_AXI_CTRL_REG_XLEN_LEN) - 1) << DSP2_AXI_CTRL_REG_XLEN_POS)) -#define DSP2_AXI_CTRL_REG_QOS_SW_MODE DSP2_AXI_CTRL_REG_QOS_SW_MODE -#define DSP2_AXI_CTRL_REG_QOS_SW_MODE_POS (8U) -#define DSP2_AXI_CTRL_REG_QOS_SW_MODE_LEN (1U) -#define DSP2_AXI_CTRL_REG_QOS_SW_MODE_MSK (((1U << DSP2_AXI_CTRL_REG_QOS_SW_MODE_LEN) - 1) << DSP2_AXI_CTRL_REG_QOS_SW_MODE_POS) -#define DSP2_AXI_CTRL_REG_QOS_SW_MODE_UMSK (~(((1U << DSP2_AXI_CTRL_REG_QOS_SW_MODE_LEN) - 1) << DSP2_AXI_CTRL_REG_QOS_SW_MODE_POS)) -#define DSP2_AXI_CTRL_REG_QOS_SW DSP2_AXI_CTRL_REG_QOS_SW -#define DSP2_AXI_CTRL_REG_QOS_SW_POS (9U) -#define DSP2_AXI_CTRL_REG_QOS_SW_LEN (1U) -#define DSP2_AXI_CTRL_REG_QOS_SW_MSK (((1U << DSP2_AXI_CTRL_REG_QOS_SW_LEN) - 1) << DSP2_AXI_CTRL_REG_QOS_SW_POS) -#define DSP2_AXI_CTRL_REG_QOS_SW_UMSK (~(((1U << DSP2_AXI_CTRL_REG_QOS_SW_LEN) - 1) << DSP2_AXI_CTRL_REG_QOS_SW_POS)) - -/* 0x4 : nr_haddr_start_address */ -#define DSP2_AXI_CTRL_NR_HADDR_START_ADDRESS_OFFSET (0x4) -#define DSP2_AXI_CTRL_REG_ADDR_START DSP2_AXI_CTRL_REG_ADDR_START -#define DSP2_AXI_CTRL_REG_ADDR_START_POS (0U) -#define DSP2_AXI_CTRL_REG_ADDR_START_LEN (32U) -#define DSP2_AXI_CTRL_REG_ADDR_START_MSK (((1U << DSP2_AXI_CTRL_REG_ADDR_START_LEN) - 1) << DSP2_AXI_CTRL_REG_ADDR_START_POS) -#define DSP2_AXI_CTRL_REG_ADDR_START_UMSK (~(((1U << DSP2_AXI_CTRL_REG_ADDR_START_LEN) - 1) << DSP2_AXI_CTRL_REG_ADDR_START_POS)) - -/* 0x8 : nr_memory_burst_count */ -#define DSP2_AXI_CTRL_NR_MEMORY_BURST_COUNT_OFFSET (0x8) -#define DSP2_AXI_CTRL_REG_BURST_CNT DSP2_AXI_CTRL_REG_BURST_CNT -#define DSP2_AXI_CTRL_REG_BURST_CNT_POS (0U) -#define DSP2_AXI_CTRL_REG_BURST_CNT_LEN (32U) -#define DSP2_AXI_CTRL_REG_BURST_CNT_MSK (((1U << DSP2_AXI_CTRL_REG_BURST_CNT_LEN) - 1) << DSP2_AXI_CTRL_REG_BURST_CNT_POS) -#define DSP2_AXI_CTRL_REG_BURST_CNT_UMSK (~(((1U << DSP2_AXI_CTRL_REG_BURST_CNT_LEN) - 1) << DSP2_AXI_CTRL_REG_BURST_CNT_POS)) - -/* 0xC : nr_hsync_control */ -#define DSP2_AXI_CTRL_NR_HSYNC_CONTROL_OFFSET (0xC) -#define DSP2_AXI_CTRL_REG_HSYNC_ACT_END DSP2_AXI_CTRL_REG_HSYNC_ACT_END -#define DSP2_AXI_CTRL_REG_HSYNC_ACT_END_POS (0U) -#define DSP2_AXI_CTRL_REG_HSYNC_ACT_END_LEN (16U) -#define DSP2_AXI_CTRL_REG_HSYNC_ACT_END_MSK (((1U << DSP2_AXI_CTRL_REG_HSYNC_ACT_END_LEN) - 1) << DSP2_AXI_CTRL_REG_HSYNC_ACT_END_POS) -#define DSP2_AXI_CTRL_REG_HSYNC_ACT_END_UMSK (~(((1U << DSP2_AXI_CTRL_REG_HSYNC_ACT_END_LEN) - 1) << DSP2_AXI_CTRL_REG_HSYNC_ACT_END_POS)) -#define DSP2_AXI_CTRL_REG_HSYNC_ACT_START DSP2_AXI_CTRL_REG_HSYNC_ACT_START -#define DSP2_AXI_CTRL_REG_HSYNC_ACT_START_POS (16U) -#define DSP2_AXI_CTRL_REG_HSYNC_ACT_START_LEN (16U) -#define DSP2_AXI_CTRL_REG_HSYNC_ACT_START_MSK (((1U << DSP2_AXI_CTRL_REG_HSYNC_ACT_START_LEN) - 1) << DSP2_AXI_CTRL_REG_HSYNC_ACT_START_POS) -#define DSP2_AXI_CTRL_REG_HSYNC_ACT_START_UMSK (~(((1U << DSP2_AXI_CTRL_REG_HSYNC_ACT_START_LEN) - 1) << DSP2_AXI_CTRL_REG_HSYNC_ACT_START_POS)) - -/* 0x10 : nr_vsync_control */ -#define DSP2_AXI_CTRL_NR_VSYNC_CONTROL_OFFSET (0x10) -#define DSP2_AXI_CTRL_REG_VSYNC_ACT_END DSP2_AXI_CTRL_REG_VSYNC_ACT_END -#define DSP2_AXI_CTRL_REG_VSYNC_ACT_END_POS (0U) -#define DSP2_AXI_CTRL_REG_VSYNC_ACT_END_LEN (16U) -#define DSP2_AXI_CTRL_REG_VSYNC_ACT_END_MSK (((1U << DSP2_AXI_CTRL_REG_VSYNC_ACT_END_LEN) - 1) << DSP2_AXI_CTRL_REG_VSYNC_ACT_END_POS) -#define DSP2_AXI_CTRL_REG_VSYNC_ACT_END_UMSK (~(((1U << DSP2_AXI_CTRL_REG_VSYNC_ACT_END_LEN) - 1) << DSP2_AXI_CTRL_REG_VSYNC_ACT_END_POS)) -#define DSP2_AXI_CTRL_REG_VSYNC_ACT_START DSP2_AXI_CTRL_REG_VSYNC_ACT_START -#define DSP2_AXI_CTRL_REG_VSYNC_ACT_START_POS (16U) -#define DSP2_AXI_CTRL_REG_VSYNC_ACT_START_LEN (16U) -#define DSP2_AXI_CTRL_REG_VSYNC_ACT_START_MSK (((1U << DSP2_AXI_CTRL_REG_VSYNC_ACT_START_LEN) - 1) << DSP2_AXI_CTRL_REG_VSYNC_ACT_START_POS) -#define DSP2_AXI_CTRL_REG_VSYNC_ACT_START_UMSK (~(((1U << DSP2_AXI_CTRL_REG_VSYNC_ACT_START_LEN) - 1) << DSP2_AXI_CTRL_REG_VSYNC_ACT_START_POS)) - -/* 0x14 : nr_status */ -#define DSP2_AXI_CTRL_NR_STATUS_OFFSET (0x14) -#define DSP2_AXI_CTRL_STATUS_R_DRAIN DSP2_AXI_CTRL_STATUS_R_DRAIN -#define DSP2_AXI_CTRL_STATUS_R_DRAIN_POS (4U) -#define DSP2_AXI_CTRL_STATUS_R_DRAIN_LEN (1U) -#define DSP2_AXI_CTRL_STATUS_R_DRAIN_MSK (((1U << DSP2_AXI_CTRL_STATUS_R_DRAIN_LEN) - 1) << DSP2_AXI_CTRL_STATUS_R_DRAIN_POS) -#define DSP2_AXI_CTRL_STATUS_R_DRAIN_UMSK (~(((1U << DSP2_AXI_CTRL_STATUS_R_DRAIN_LEN) - 1) << DSP2_AXI_CTRL_STATUS_R_DRAIN_POS)) -#define DSP2_AXI_CTRL_STATUS_W_OVERFLOW DSP2_AXI_CTRL_STATUS_W_OVERFLOW -#define DSP2_AXI_CTRL_STATUS_W_OVERFLOW_POS (5U) -#define DSP2_AXI_CTRL_STATUS_W_OVERFLOW_LEN (1U) -#define DSP2_AXI_CTRL_STATUS_W_OVERFLOW_MSK (((1U << DSP2_AXI_CTRL_STATUS_W_OVERFLOW_LEN) - 1) << DSP2_AXI_CTRL_STATUS_W_OVERFLOW_POS) -#define DSP2_AXI_CTRL_STATUS_W_OVERFLOW_UMSK (~(((1U << DSP2_AXI_CTRL_STATUS_W_OVERFLOW_LEN) - 1) << DSP2_AXI_CTRL_STATUS_W_OVERFLOW_POS)) -#define DSP2_AXI_CTRL_STATE_W_DVP_IDLE DSP2_AXI_CTRL_STATE_W_DVP_IDLE -#define DSP2_AXI_CTRL_STATE_W_DVP_IDLE_POS (8U) -#define DSP2_AXI_CTRL_STATE_W_DVP_IDLE_LEN (1U) -#define DSP2_AXI_CTRL_STATE_W_DVP_IDLE_MSK (((1U << DSP2_AXI_CTRL_STATE_W_DVP_IDLE_LEN) - 1) << DSP2_AXI_CTRL_STATE_W_DVP_IDLE_POS) -#define DSP2_AXI_CTRL_STATE_W_DVP_IDLE_UMSK (~(((1U << DSP2_AXI_CTRL_STATE_W_DVP_IDLE_LEN) - 1) << DSP2_AXI_CTRL_STATE_W_DVP_IDLE_POS)) -#define DSP2_AXI_CTRL_STATE_W_DVP_WTST DSP2_AXI_CTRL_STATE_W_DVP_WTST -#define DSP2_AXI_CTRL_STATE_W_DVP_WTST_POS (9U) -#define DSP2_AXI_CTRL_STATE_W_DVP_WTST_LEN (1U) -#define DSP2_AXI_CTRL_STATE_W_DVP_WTST_MSK (((1U << DSP2_AXI_CTRL_STATE_W_DVP_WTST_LEN) - 1) << DSP2_AXI_CTRL_STATE_W_DVP_WTST_POS) -#define DSP2_AXI_CTRL_STATE_W_DVP_WTST_UMSK (~(((1U << DSP2_AXI_CTRL_STATE_W_DVP_WTST_LEN) - 1) << DSP2_AXI_CTRL_STATE_W_DVP_WTST_POS)) -#define DSP2_AXI_CTRL_STATE_W_DVP_FUNC DSP2_AXI_CTRL_STATE_W_DVP_FUNC -#define DSP2_AXI_CTRL_STATE_W_DVP_FUNC_POS (10U) -#define DSP2_AXI_CTRL_STATE_W_DVP_FUNC_LEN (1U) -#define DSP2_AXI_CTRL_STATE_W_DVP_FUNC_MSK (((1U << DSP2_AXI_CTRL_STATE_W_DVP_FUNC_LEN) - 1) << DSP2_AXI_CTRL_STATE_W_DVP_FUNC_POS) -#define DSP2_AXI_CTRL_STATE_W_DVP_FUNC_UMSK (~(((1U << DSP2_AXI_CTRL_STATE_W_DVP_FUNC_LEN) - 1) << DSP2_AXI_CTRL_STATE_W_DVP_FUNC_POS)) -#define DSP2_AXI_CTRL_STATE_W_DVP_FEND DSP2_AXI_CTRL_STATE_W_DVP_FEND -#define DSP2_AXI_CTRL_STATE_W_DVP_FEND_POS (11U) -#define DSP2_AXI_CTRL_STATE_W_DVP_FEND_LEN (1U) -#define DSP2_AXI_CTRL_STATE_W_DVP_FEND_MSK (((1U << DSP2_AXI_CTRL_STATE_W_DVP_FEND_LEN) - 1) << DSP2_AXI_CTRL_STATE_W_DVP_FEND_POS) -#define DSP2_AXI_CTRL_STATE_W_DVP_FEND_UMSK (~(((1U << DSP2_AXI_CTRL_STATE_W_DVP_FEND_LEN) - 1) << DSP2_AXI_CTRL_STATE_W_DVP_FEND_POS)) -#define DSP2_AXI_CTRL_STATE_W_DVP_FLSH DSP2_AXI_CTRL_STATE_W_DVP_FLSH -#define DSP2_AXI_CTRL_STATE_W_DVP_FLSH_POS (12U) -#define DSP2_AXI_CTRL_STATE_W_DVP_FLSH_LEN (1U) -#define DSP2_AXI_CTRL_STATE_W_DVP_FLSH_MSK (((1U << DSP2_AXI_CTRL_STATE_W_DVP_FLSH_LEN) - 1) << DSP2_AXI_CTRL_STATE_W_DVP_FLSH_POS) -#define DSP2_AXI_CTRL_STATE_W_DVP_FLSH_UMSK (~(((1U << DSP2_AXI_CTRL_STATE_W_DVP_FLSH_LEN) - 1) << DSP2_AXI_CTRL_STATE_W_DVP_FLSH_POS)) -#define DSP2_AXI_CTRL_STATE_W_BUS_IDLE DSP2_AXI_CTRL_STATE_W_BUS_IDLE -#define DSP2_AXI_CTRL_STATE_W_BUS_IDLE_POS (13U) -#define DSP2_AXI_CTRL_STATE_W_BUS_IDLE_LEN (1U) -#define DSP2_AXI_CTRL_STATE_W_BUS_IDLE_MSK (((1U << DSP2_AXI_CTRL_STATE_W_BUS_IDLE_LEN) - 1) << DSP2_AXI_CTRL_STATE_W_BUS_IDLE_POS) -#define DSP2_AXI_CTRL_STATE_W_BUS_IDLE_UMSK (~(((1U << DSP2_AXI_CTRL_STATE_W_BUS_IDLE_LEN) - 1) << DSP2_AXI_CTRL_STATE_W_BUS_IDLE_POS)) -#define DSP2_AXI_CTRL_STATE_W_BUS_FUNC DSP2_AXI_CTRL_STATE_W_BUS_FUNC -#define DSP2_AXI_CTRL_STATE_W_BUS_FUNC_POS (14U) -#define DSP2_AXI_CTRL_STATE_W_BUS_FUNC_LEN (1U) -#define DSP2_AXI_CTRL_STATE_W_BUS_FUNC_MSK (((1U << DSP2_AXI_CTRL_STATE_W_BUS_FUNC_LEN) - 1) << DSP2_AXI_CTRL_STATE_W_BUS_FUNC_POS) -#define DSP2_AXI_CTRL_STATE_W_BUS_FUNC_UMSK (~(((1U << DSP2_AXI_CTRL_STATE_W_BUS_FUNC_LEN) - 1) << DSP2_AXI_CTRL_STATE_W_BUS_FUNC_POS)) -#define DSP2_AXI_CTRL_STATE_W_BUS_FEND DSP2_AXI_CTRL_STATE_W_BUS_FEND -#define DSP2_AXI_CTRL_STATE_W_BUS_FEND_POS (15U) -#define DSP2_AXI_CTRL_STATE_W_BUS_FEND_LEN (1U) -#define DSP2_AXI_CTRL_STATE_W_BUS_FEND_MSK (((1U << DSP2_AXI_CTRL_STATE_W_BUS_FEND_LEN) - 1) << DSP2_AXI_CTRL_STATE_W_BUS_FEND_POS) -#define DSP2_AXI_CTRL_STATE_W_BUS_FEND_UMSK (~(((1U << DSP2_AXI_CTRL_STATE_W_BUS_FEND_LEN) - 1) << DSP2_AXI_CTRL_STATE_W_BUS_FEND_POS)) -#define DSP2_AXI_CTRL_STATE_W_BUS_FLSH DSP2_AXI_CTRL_STATE_W_BUS_FLSH -#define DSP2_AXI_CTRL_STATE_W_BUS_FLSH_POS (16U) -#define DSP2_AXI_CTRL_STATE_W_BUS_FLSH_LEN (1U) -#define DSP2_AXI_CTRL_STATE_W_BUS_FLSH_MSK (((1U << DSP2_AXI_CTRL_STATE_W_BUS_FLSH_LEN) - 1) << DSP2_AXI_CTRL_STATE_W_BUS_FLSH_POS) -#define DSP2_AXI_CTRL_STATE_W_BUS_FLSH_UMSK (~(((1U << DSP2_AXI_CTRL_STATE_W_BUS_FLSH_LEN) - 1) << DSP2_AXI_CTRL_STATE_W_BUS_FLSH_POS)) -#define DSP2_AXI_CTRL_STATE_R_DVP_IDLE DSP2_AXI_CTRL_STATE_R_DVP_IDLE -#define DSP2_AXI_CTRL_STATE_R_DVP_IDLE_POS (17U) -#define DSP2_AXI_CTRL_STATE_R_DVP_IDLE_LEN (1U) -#define DSP2_AXI_CTRL_STATE_R_DVP_IDLE_MSK (((1U << DSP2_AXI_CTRL_STATE_R_DVP_IDLE_LEN) - 1) << DSP2_AXI_CTRL_STATE_R_DVP_IDLE_POS) -#define DSP2_AXI_CTRL_STATE_R_DVP_IDLE_UMSK (~(((1U << DSP2_AXI_CTRL_STATE_R_DVP_IDLE_LEN) - 1) << DSP2_AXI_CTRL_STATE_R_DVP_IDLE_POS)) -#define DSP2_AXI_CTRL_STATE_R_DVP_WTST DSP2_AXI_CTRL_STATE_R_DVP_WTST -#define DSP2_AXI_CTRL_STATE_R_DVP_WTST_POS (18U) -#define DSP2_AXI_CTRL_STATE_R_DVP_WTST_LEN (1U) -#define DSP2_AXI_CTRL_STATE_R_DVP_WTST_MSK (((1U << DSP2_AXI_CTRL_STATE_R_DVP_WTST_LEN) - 1) << DSP2_AXI_CTRL_STATE_R_DVP_WTST_POS) -#define DSP2_AXI_CTRL_STATE_R_DVP_WTST_UMSK (~(((1U << DSP2_AXI_CTRL_STATE_R_DVP_WTST_LEN) - 1) << DSP2_AXI_CTRL_STATE_R_DVP_WTST_POS)) -#define DSP2_AXI_CTRL_STATE_R_DVP_FUNC DSP2_AXI_CTRL_STATE_R_DVP_FUNC -#define DSP2_AXI_CTRL_STATE_R_DVP_FUNC_POS (19U) -#define DSP2_AXI_CTRL_STATE_R_DVP_FUNC_LEN (1U) -#define DSP2_AXI_CTRL_STATE_R_DVP_FUNC_MSK (((1U << DSP2_AXI_CTRL_STATE_R_DVP_FUNC_LEN) - 1) << DSP2_AXI_CTRL_STATE_R_DVP_FUNC_POS) -#define DSP2_AXI_CTRL_STATE_R_DVP_FUNC_UMSK (~(((1U << DSP2_AXI_CTRL_STATE_R_DVP_FUNC_LEN) - 1) << DSP2_AXI_CTRL_STATE_R_DVP_FUNC_POS)) -#define DSP2_AXI_CTRL_STATE_R_DVP_FEND DSP2_AXI_CTRL_STATE_R_DVP_FEND -#define DSP2_AXI_CTRL_STATE_R_DVP_FEND_POS (20U) -#define DSP2_AXI_CTRL_STATE_R_DVP_FEND_LEN (1U) -#define DSP2_AXI_CTRL_STATE_R_DVP_FEND_MSK (((1U << DSP2_AXI_CTRL_STATE_R_DVP_FEND_LEN) - 1) << DSP2_AXI_CTRL_STATE_R_DVP_FEND_POS) -#define DSP2_AXI_CTRL_STATE_R_DVP_FEND_UMSK (~(((1U << DSP2_AXI_CTRL_STATE_R_DVP_FEND_LEN) - 1) << DSP2_AXI_CTRL_STATE_R_DVP_FEND_POS)) -#define DSP2_AXI_CTRL_STATE_R_DVP_FLSH DSP2_AXI_CTRL_STATE_R_DVP_FLSH -#define DSP2_AXI_CTRL_STATE_R_DVP_FLSH_POS (21U) -#define DSP2_AXI_CTRL_STATE_R_DVP_FLSH_LEN (1U) -#define DSP2_AXI_CTRL_STATE_R_DVP_FLSH_MSK (((1U << DSP2_AXI_CTRL_STATE_R_DVP_FLSH_LEN) - 1) << DSP2_AXI_CTRL_STATE_R_DVP_FLSH_POS) -#define DSP2_AXI_CTRL_STATE_R_DVP_FLSH_UMSK (~(((1U << DSP2_AXI_CTRL_STATE_R_DVP_FLSH_LEN) - 1) << DSP2_AXI_CTRL_STATE_R_DVP_FLSH_POS)) -#define DSP2_AXI_CTRL_STATE_R_BUS_IDLE DSP2_AXI_CTRL_STATE_R_BUS_IDLE -#define DSP2_AXI_CTRL_STATE_R_BUS_IDLE_POS (22U) -#define DSP2_AXI_CTRL_STATE_R_BUS_IDLE_LEN (1U) -#define DSP2_AXI_CTRL_STATE_R_BUS_IDLE_MSK (((1U << DSP2_AXI_CTRL_STATE_R_BUS_IDLE_LEN) - 1) << DSP2_AXI_CTRL_STATE_R_BUS_IDLE_POS) -#define DSP2_AXI_CTRL_STATE_R_BUS_IDLE_UMSK (~(((1U << DSP2_AXI_CTRL_STATE_R_BUS_IDLE_LEN) - 1) << DSP2_AXI_CTRL_STATE_R_BUS_IDLE_POS)) -#define DSP2_AXI_CTRL_STATE_R_BUS_FUNC DSP2_AXI_CTRL_STATE_R_BUS_FUNC -#define DSP2_AXI_CTRL_STATE_R_BUS_FUNC_POS (23U) -#define DSP2_AXI_CTRL_STATE_R_BUS_FUNC_LEN (1U) -#define DSP2_AXI_CTRL_STATE_R_BUS_FUNC_MSK (((1U << DSP2_AXI_CTRL_STATE_R_BUS_FUNC_LEN) - 1) << DSP2_AXI_CTRL_STATE_R_BUS_FUNC_POS) -#define DSP2_AXI_CTRL_STATE_R_BUS_FUNC_UMSK (~(((1U << DSP2_AXI_CTRL_STATE_R_BUS_FUNC_LEN) - 1) << DSP2_AXI_CTRL_STATE_R_BUS_FUNC_POS)) -#define DSP2_AXI_CTRL_STATE_R_BUS_FEND DSP2_AXI_CTRL_STATE_R_BUS_FEND -#define DSP2_AXI_CTRL_STATE_R_BUS_FEND_POS (24U) -#define DSP2_AXI_CTRL_STATE_R_BUS_FEND_LEN (1U) -#define DSP2_AXI_CTRL_STATE_R_BUS_FEND_MSK (((1U << DSP2_AXI_CTRL_STATE_R_BUS_FEND_LEN) - 1) << DSP2_AXI_CTRL_STATE_R_BUS_FEND_POS) -#define DSP2_AXI_CTRL_STATE_R_BUS_FEND_UMSK (~(((1U << DSP2_AXI_CTRL_STATE_R_BUS_FEND_LEN) - 1) << DSP2_AXI_CTRL_STATE_R_BUS_FEND_POS)) -#define DSP2_AXI_CTRL_STATE_R_BUS_FLSH DSP2_AXI_CTRL_STATE_R_BUS_FLSH -#define DSP2_AXI_CTRL_STATE_R_BUS_FLSH_POS (25U) -#define DSP2_AXI_CTRL_STATE_R_BUS_FLSH_LEN (1U) -#define DSP2_AXI_CTRL_STATE_R_BUS_FLSH_MSK (((1U << DSP2_AXI_CTRL_STATE_R_BUS_FLSH_LEN) - 1) << DSP2_AXI_CTRL_STATE_R_BUS_FLSH_POS) -#define DSP2_AXI_CTRL_STATE_R_BUS_FLSH_UMSK (~(((1U << DSP2_AXI_CTRL_STATE_R_BUS_FLSH_LEN) - 1) << DSP2_AXI_CTRL_STATE_R_BUS_FLSH_POS)) -#define DSP2_AXI_CTRL_AXI_R_IDLE DSP2_AXI_CTRL_AXI_R_IDLE -#define DSP2_AXI_CTRL_AXI_R_IDLE_POS (26U) -#define DSP2_AXI_CTRL_AXI_R_IDLE_LEN (1U) -#define DSP2_AXI_CTRL_AXI_R_IDLE_MSK (((1U << DSP2_AXI_CTRL_AXI_R_IDLE_LEN) - 1) << DSP2_AXI_CTRL_AXI_R_IDLE_POS) -#define DSP2_AXI_CTRL_AXI_R_IDLE_UMSK (~(((1U << DSP2_AXI_CTRL_AXI_R_IDLE_LEN) - 1) << DSP2_AXI_CTRL_AXI_R_IDLE_POS)) -#define DSP2_AXI_CTRL_AXI_W_IDLE DSP2_AXI_CTRL_AXI_W_IDLE -#define DSP2_AXI_CTRL_AXI_W_IDLE_POS (27U) -#define DSP2_AXI_CTRL_AXI_W_IDLE_LEN (1U) -#define DSP2_AXI_CTRL_AXI_W_IDLE_MSK (((1U << DSP2_AXI_CTRL_AXI_W_IDLE_LEN) - 1) << DSP2_AXI_CTRL_AXI_W_IDLE_POS) -#define DSP2_AXI_CTRL_AXI_W_IDLE_UMSK (~(((1U << DSP2_AXI_CTRL_AXI_W_IDLE_LEN) - 1) << DSP2_AXI_CTRL_AXI_W_IDLE_POS)) - -/* 0xFC : nr_RSVD */ -#define DSP2_AXI_CTRL_NR_RSVD_OFFSET (0xFC) - -struct dsp2_axi_ctrl_reg { - /* 0x0 : nr_control */ - union { - struct - { - uint32_t reg_enable : 1; /* [ 0], r/w, 0x0 */ - uint32_t reg_drain_clr : 1; /* [ 1], w1p, 0x0 */ - uint32_t reg_overflow_clr : 1; /* [ 2], w1p, 0x0 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t reg_xlen : 3; /* [ 6: 4], r/w, 0x3 */ - uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ - uint32_t reg_qos_sw_mode : 1; /* [ 8], r/w, 0x0 */ - uint32_t reg_qos_sw : 1; /* [ 9], r/w, 0x0 */ - uint32_t reserved_10_31 : 22; /* [31:10], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } nr_control; - - /* 0x4 : nr_haddr_start_address */ - union { - struct - { - uint32_t reg_addr_start : 32; /* [31: 0], r/w, 0x70000000 */ - } BF; - uint32_t WORD; - } nr_haddr_start_address; - - /* 0x8 : nr_memory_burst_count */ - union { - struct - { - uint32_t reg_burst_cnt : 32; /* [31: 0], r/w, 0x80 */ - } BF; - uint32_t WORD; - } nr_memory_burst_count; - - /* 0xC : nr_hsync_control */ - union { - struct - { - uint32_t reg_hsync_act_end : 16; /* [15: 0], r/w, 0xffff */ - uint32_t reg_hsync_act_start : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } nr_hsync_control; - - /* 0x10 : nr_vsync_control */ - union { - struct - { - uint32_t reg_vsync_act_end : 16; /* [15: 0], r/w, 0xffff */ - uint32_t reg_vsync_act_start : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } nr_vsync_control; - - /* 0x14 : nr_status */ - union { - struct - { - uint32_t reserved_0_3 : 4; /* [ 3: 0], rsvd, 0x0 */ - uint32_t status_r_drain : 1; /* [ 4], r, 0x0 */ - uint32_t status_w_overflow : 1; /* [ 5], r, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t state_w_dvp_idle : 1; /* [ 8], r, 0x1 */ - uint32_t state_w_dvp_wtst : 1; /* [ 9], r, 0x0 */ - uint32_t state_w_dvp_func : 1; /* [ 10], r, 0x0 */ - uint32_t state_w_dvp_fend : 1; /* [ 11], r, 0x0 */ - uint32_t state_w_dvp_flsh : 1; /* [ 12], r, 0x0 */ - uint32_t state_w_bus_idle : 1; /* [ 13], r, 0x1 */ - uint32_t state_w_bus_func : 1; /* [ 14], r, 0x0 */ - uint32_t state_w_bus_fend : 1; /* [ 15], r, 0x0 */ - uint32_t state_w_bus_flsh : 1; /* [ 16], r, 0x0 */ - uint32_t state_r_dvp_idle : 1; /* [ 17], r, 0x1 */ - uint32_t state_r_dvp_wtst : 1; /* [ 18], r, 0x0 */ - uint32_t state_r_dvp_func : 1; /* [ 19], r, 0x0 */ - uint32_t state_r_dvp_fend : 1; /* [ 20], r, 0x0 */ - uint32_t state_r_dvp_flsh : 1; /* [ 21], r, 0x0 */ - uint32_t state_r_bus_idle : 1; /* [ 22], r, 0x1 */ - uint32_t state_r_bus_func : 1; /* [ 23], r, 0x0 */ - uint32_t state_r_bus_fend : 1; /* [ 24], r, 0x0 */ - uint32_t state_r_bus_flsh : 1; /* [ 25], r, 0x0 */ - uint32_t axi_r_idle : 1; /* [ 26], r, 0x0 */ - uint32_t axi_w_idle : 1; /* [ 27], r, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } nr_status; - - /* 0x18 reserved */ - uint8_t RESERVED0x18[228]; - - /* 0xFC : nr_RSVD */ - union { - struct - { - uint32_t RESERVED_31_0 : 32; /* [31: 0], rsvd, 0xffff0000 */ - } BF; - uint32_t WORD; - } nr_RSVD; -}; - -typedef volatile struct dsp2_axi_ctrl_reg dsp2_axi_ctrl_reg_t; - -#endif /* __DSP2_AXI_CTRL_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_back_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_back_reg.h deleted file mode 100644 index 5fbbbaf25e..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_back_reg.h +++ /dev/null @@ -1,574 +0,0 @@ -/** - ****************************************************************************** - * @file dsp2_back_reg.h - * @version V1.0 - * @date 2021-02-05 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __DSP2_BACK_REG_H__ -#define __DSP2_BACK_REG_H__ - -#include "bl808.h" - -/* 0x314 : ccr_coef_A */ -#define DSP2_BACK_CCR_COEF_A_OFFSET (0x314) -#define DSP2_BACK_A11_PRE DSP2_BACK_A11_PRE -#define DSP2_BACK_A11_PRE_POS (16U) -#define DSP2_BACK_A11_PRE_LEN (12U) -#define DSP2_BACK_A11_PRE_MSK (((1U << DSP2_BACK_A11_PRE_LEN) - 1) << DSP2_BACK_A11_PRE_POS) -#define DSP2_BACK_A11_PRE_UMSK (~(((1U << DSP2_BACK_A11_PRE_LEN) - 1) << DSP2_BACK_A11_PRE_POS)) - -/* 0x318 : ccr_coef_B */ -#define DSP2_BACK_CCR_COEF_B_OFFSET (0x318) -#define DSP2_BACK_A12_PRE DSP2_BACK_A12_PRE -#define DSP2_BACK_A12_PRE_POS (0U) -#define DSP2_BACK_A12_PRE_LEN (12U) -#define DSP2_BACK_A12_PRE_MSK (((1U << DSP2_BACK_A12_PRE_LEN) - 1) << DSP2_BACK_A12_PRE_POS) -#define DSP2_BACK_A12_PRE_UMSK (~(((1U << DSP2_BACK_A12_PRE_LEN) - 1) << DSP2_BACK_A12_PRE_POS)) -#define DSP2_BACK_A13_PRE DSP2_BACK_A13_PRE -#define DSP2_BACK_A13_PRE_POS (16U) -#define DSP2_BACK_A13_PRE_LEN (12U) -#define DSP2_BACK_A13_PRE_MSK (((1U << DSP2_BACK_A13_PRE_LEN) - 1) << DSP2_BACK_A13_PRE_POS) -#define DSP2_BACK_A13_PRE_UMSK (~(((1U << DSP2_BACK_A13_PRE_LEN) - 1) << DSP2_BACK_A13_PRE_POS)) - -/* 0x31C : ccr_coef_C */ -#define DSP2_BACK_CCR_COEF_C_OFFSET (0x31C) -#define DSP2_BACK_A21_PRE DSP2_BACK_A21_PRE -#define DSP2_BACK_A21_PRE_POS (0U) -#define DSP2_BACK_A21_PRE_LEN (12U) -#define DSP2_BACK_A21_PRE_MSK (((1U << DSP2_BACK_A21_PRE_LEN) - 1) << DSP2_BACK_A21_PRE_POS) -#define DSP2_BACK_A21_PRE_UMSK (~(((1U << DSP2_BACK_A21_PRE_LEN) - 1) << DSP2_BACK_A21_PRE_POS)) -#define DSP2_BACK_A22_PRE DSP2_BACK_A22_PRE -#define DSP2_BACK_A22_PRE_POS (16U) -#define DSP2_BACK_A22_PRE_LEN (12U) -#define DSP2_BACK_A22_PRE_MSK (((1U << DSP2_BACK_A22_PRE_LEN) - 1) << DSP2_BACK_A22_PRE_POS) -#define DSP2_BACK_A22_PRE_UMSK (~(((1U << DSP2_BACK_A22_PRE_LEN) - 1) << DSP2_BACK_A22_PRE_POS)) - -/* 0x320 : ccr_coef_D */ -#define DSP2_BACK_CCR_COEF_D_OFFSET (0x320) -#define DSP2_BACK_A23_PRE DSP2_BACK_A23_PRE -#define DSP2_BACK_A23_PRE_POS (0U) -#define DSP2_BACK_A23_PRE_LEN (12U) -#define DSP2_BACK_A23_PRE_MSK (((1U << DSP2_BACK_A23_PRE_LEN) - 1) << DSP2_BACK_A23_PRE_POS) -#define DSP2_BACK_A23_PRE_UMSK (~(((1U << DSP2_BACK_A23_PRE_LEN) - 1) << DSP2_BACK_A23_PRE_POS)) -#define DSP2_BACK_A31_PRE DSP2_BACK_A31_PRE -#define DSP2_BACK_A31_PRE_POS (16U) -#define DSP2_BACK_A31_PRE_LEN (12U) -#define DSP2_BACK_A31_PRE_MSK (((1U << DSP2_BACK_A31_PRE_LEN) - 1) << DSP2_BACK_A31_PRE_POS) -#define DSP2_BACK_A31_PRE_UMSK (~(((1U << DSP2_BACK_A31_PRE_LEN) - 1) << DSP2_BACK_A31_PRE_POS)) - -/* 0x324 : ccr_coef_E */ -#define DSP2_BACK_CCR_COEF_E_OFFSET (0x324) -#define DSP2_BACK_A32_PRE DSP2_BACK_A32_PRE -#define DSP2_BACK_A32_PRE_POS (0U) -#define DSP2_BACK_A32_PRE_LEN (12U) -#define DSP2_BACK_A32_PRE_MSK (((1U << DSP2_BACK_A32_PRE_LEN) - 1) << DSP2_BACK_A32_PRE_POS) -#define DSP2_BACK_A32_PRE_UMSK (~(((1U << DSP2_BACK_A32_PRE_LEN) - 1) << DSP2_BACK_A32_PRE_POS)) -#define DSP2_BACK_A33_PRE DSP2_BACK_A33_PRE -#define DSP2_BACK_A33_PRE_POS (16U) -#define DSP2_BACK_A33_PRE_LEN (12U) -#define DSP2_BACK_A33_PRE_MSK (((1U << DSP2_BACK_A33_PRE_LEN) - 1) << DSP2_BACK_A33_PRE_POS) -#define DSP2_BACK_A33_PRE_UMSK (~(((1U << DSP2_BACK_A33_PRE_LEN) - 1) << DSP2_BACK_A33_PRE_POS)) - -/* 0x328 : gamma_A */ -#define DSP2_BACK_GAMMA_A_OFFSET (0x328) -#define DSP2_BACK_GAMMA_ON_PRE DSP2_BACK_GAMMA_ON_PRE -#define DSP2_BACK_GAMMA_ON_PRE_POS (0U) -#define DSP2_BACK_GAMMA_ON_PRE_LEN (1U) -#define DSP2_BACK_GAMMA_ON_PRE_MSK (((1U << DSP2_BACK_GAMMA_ON_PRE_LEN) - 1) << DSP2_BACK_GAMMA_ON_PRE_POS) -#define DSP2_BACK_GAMMA_ON_PRE_UMSK (~(((1U << DSP2_BACK_GAMMA_ON_PRE_LEN) - 1) << DSP2_BACK_GAMMA_ON_PRE_POS)) -#define DSP2_BACK_GAMMA_EB_PRE DSP2_BACK_GAMMA_EB_PRE -#define DSP2_BACK_GAMMA_EB_PRE_POS (1U) -#define DSP2_BACK_GAMMA_EB_PRE_LEN (1U) -#define DSP2_BACK_GAMMA_EB_PRE_MSK (((1U << DSP2_BACK_GAMMA_EB_PRE_LEN) - 1) << DSP2_BACK_GAMMA_EB_PRE_POS) -#define DSP2_BACK_GAMMA_EB_PRE_UMSK (~(((1U << DSP2_BACK_GAMMA_EB_PRE_LEN) - 1) << DSP2_BACK_GAMMA_EB_PRE_POS)) -#define DSP2_BACK_B0_PRE DSP2_BACK_B0_PRE -#define DSP2_BACK_B0_PRE_POS (8U) -#define DSP2_BACK_B0_PRE_LEN (8U) -#define DSP2_BACK_B0_PRE_MSK (((1U << DSP2_BACK_B0_PRE_LEN) - 1) << DSP2_BACK_B0_PRE_POS) -#define DSP2_BACK_B0_PRE_UMSK (~(((1U << DSP2_BACK_B0_PRE_LEN) - 1) << DSP2_BACK_B0_PRE_POS)) -#define DSP2_BACK_B1_PRE DSP2_BACK_B1_PRE -#define DSP2_BACK_B1_PRE_POS (16U) -#define DSP2_BACK_B1_PRE_LEN (8U) -#define DSP2_BACK_B1_PRE_MSK (((1U << DSP2_BACK_B1_PRE_LEN) - 1) << DSP2_BACK_B1_PRE_POS) -#define DSP2_BACK_B1_PRE_UMSK (~(((1U << DSP2_BACK_B1_PRE_LEN) - 1) << DSP2_BACK_B1_PRE_POS)) -#define DSP2_BACK_B2_PRE DSP2_BACK_B2_PRE -#define DSP2_BACK_B2_PRE_POS (24U) -#define DSP2_BACK_B2_PRE_LEN (8U) -#define DSP2_BACK_B2_PRE_MSK (((1U << DSP2_BACK_B2_PRE_LEN) - 1) << DSP2_BACK_B2_PRE_POS) -#define DSP2_BACK_B2_PRE_UMSK (~(((1U << DSP2_BACK_B2_PRE_LEN) - 1) << DSP2_BACK_B2_PRE_POS)) - -/* 0x32C : gamma_B */ -#define DSP2_BACK_GAMMA_B_OFFSET (0x32C) -#define DSP2_BACK_B3_PRE DSP2_BACK_B3_PRE -#define DSP2_BACK_B3_PRE_POS (0U) -#define DSP2_BACK_B3_PRE_LEN (8U) -#define DSP2_BACK_B3_PRE_MSK (((1U << DSP2_BACK_B3_PRE_LEN) - 1) << DSP2_BACK_B3_PRE_POS) -#define DSP2_BACK_B3_PRE_UMSK (~(((1U << DSP2_BACK_B3_PRE_LEN) - 1) << DSP2_BACK_B3_PRE_POS)) -#define DSP2_BACK_B4_PRE DSP2_BACK_B4_PRE -#define DSP2_BACK_B4_PRE_POS (8U) -#define DSP2_BACK_B4_PRE_LEN (8U) -#define DSP2_BACK_B4_PRE_MSK (((1U << DSP2_BACK_B4_PRE_LEN) - 1) << DSP2_BACK_B4_PRE_POS) -#define DSP2_BACK_B4_PRE_UMSK (~(((1U << DSP2_BACK_B4_PRE_LEN) - 1) << DSP2_BACK_B4_PRE_POS)) -#define DSP2_BACK_B5_PRE DSP2_BACK_B5_PRE -#define DSP2_BACK_B5_PRE_POS (16U) -#define DSP2_BACK_B5_PRE_LEN (8U) -#define DSP2_BACK_B5_PRE_MSK (((1U << DSP2_BACK_B5_PRE_LEN) - 1) << DSP2_BACK_B5_PRE_POS) -#define DSP2_BACK_B5_PRE_UMSK (~(((1U << DSP2_BACK_B5_PRE_LEN) - 1) << DSP2_BACK_B5_PRE_POS)) -#define DSP2_BACK_B6_PRE DSP2_BACK_B6_PRE -#define DSP2_BACK_B6_PRE_POS (24U) -#define DSP2_BACK_B6_PRE_LEN (8U) -#define DSP2_BACK_B6_PRE_MSK (((1U << DSP2_BACK_B6_PRE_LEN) - 1) << DSP2_BACK_B6_PRE_POS) -#define DSP2_BACK_B6_PRE_UMSK (~(((1U << DSP2_BACK_B6_PRE_LEN) - 1) << DSP2_BACK_B6_PRE_POS)) - -/* 0x330 : gamma_C */ -#define DSP2_BACK_GAMMA_C_OFFSET (0x330) -#define DSP2_BACK_B7_PRE DSP2_BACK_B7_PRE -#define DSP2_BACK_B7_PRE_POS (0U) -#define DSP2_BACK_B7_PRE_LEN (8U) -#define DSP2_BACK_B7_PRE_MSK (((1U << DSP2_BACK_B7_PRE_LEN) - 1) << DSP2_BACK_B7_PRE_POS) -#define DSP2_BACK_B7_PRE_UMSK (~(((1U << DSP2_BACK_B7_PRE_LEN) - 1) << DSP2_BACK_B7_PRE_POS)) -#define DSP2_BACK_B8_PRE DSP2_BACK_B8_PRE -#define DSP2_BACK_B8_PRE_POS (8U) -#define DSP2_BACK_B8_PRE_LEN (8U) -#define DSP2_BACK_B8_PRE_MSK (((1U << DSP2_BACK_B8_PRE_LEN) - 1) << DSP2_BACK_B8_PRE_POS) -#define DSP2_BACK_B8_PRE_UMSK (~(((1U << DSP2_BACK_B8_PRE_LEN) - 1) << DSP2_BACK_B8_PRE_POS)) -#define DSP2_BACK_B9_PRE DSP2_BACK_B9_PRE -#define DSP2_BACK_B9_PRE_POS (16U) -#define DSP2_BACK_B9_PRE_LEN (8U) -#define DSP2_BACK_B9_PRE_MSK (((1U << DSP2_BACK_B9_PRE_LEN) - 1) << DSP2_BACK_B9_PRE_POS) -#define DSP2_BACK_B9_PRE_UMSK (~(((1U << DSP2_BACK_B9_PRE_LEN) - 1) << DSP2_BACK_B9_PRE_POS)) -#define DSP2_BACK_B10_PRE DSP2_BACK_B10_PRE -#define DSP2_BACK_B10_PRE_POS (24U) -#define DSP2_BACK_B10_PRE_LEN (8U) -#define DSP2_BACK_B10_PRE_MSK (((1U << DSP2_BACK_B10_PRE_LEN) - 1) << DSP2_BACK_B10_PRE_POS) -#define DSP2_BACK_B10_PRE_UMSK (~(((1U << DSP2_BACK_B10_PRE_LEN) - 1) << DSP2_BACK_B10_PRE_POS)) - -/* 0x334 : gamma_D */ -#define DSP2_BACK_GAMMA_D_OFFSET (0x334) -#define DSP2_BACK_B11_PRE DSP2_BACK_B11_PRE -#define DSP2_BACK_B11_PRE_POS (0U) -#define DSP2_BACK_B11_PRE_LEN (8U) -#define DSP2_BACK_B11_PRE_MSK (((1U << DSP2_BACK_B11_PRE_LEN) - 1) << DSP2_BACK_B11_PRE_POS) -#define DSP2_BACK_B11_PRE_UMSK (~(((1U << DSP2_BACK_B11_PRE_LEN) - 1) << DSP2_BACK_B11_PRE_POS)) -#define DSP2_BACK_B12_PRE DSP2_BACK_B12_PRE -#define DSP2_BACK_B12_PRE_POS (8U) -#define DSP2_BACK_B12_PRE_LEN (8U) -#define DSP2_BACK_B12_PRE_MSK (((1U << DSP2_BACK_B12_PRE_LEN) - 1) << DSP2_BACK_B12_PRE_POS) -#define DSP2_BACK_B12_PRE_UMSK (~(((1U << DSP2_BACK_B12_PRE_LEN) - 1) << DSP2_BACK_B12_PRE_POS)) -#define DSP2_BACK_B13_PRE DSP2_BACK_B13_PRE -#define DSP2_BACK_B13_PRE_POS (16U) -#define DSP2_BACK_B13_PRE_LEN (8U) -#define DSP2_BACK_B13_PRE_MSK (((1U << DSP2_BACK_B13_PRE_LEN) - 1) << DSP2_BACK_B13_PRE_POS) -#define DSP2_BACK_B13_PRE_UMSK (~(((1U << DSP2_BACK_B13_PRE_LEN) - 1) << DSP2_BACK_B13_PRE_POS)) -#define DSP2_BACK_B14_PRE DSP2_BACK_B14_PRE -#define DSP2_BACK_B14_PRE_POS (24U) -#define DSP2_BACK_B14_PRE_LEN (8U) -#define DSP2_BACK_B14_PRE_MSK (((1U << DSP2_BACK_B14_PRE_LEN) - 1) << DSP2_BACK_B14_PRE_POS) -#define DSP2_BACK_B14_PRE_UMSK (~(((1U << DSP2_BACK_B14_PRE_LEN) - 1) << DSP2_BACK_B14_PRE_POS)) - -/* 0x338 : gamma_E */ -#define DSP2_BACK_GAMMA_E_OFFSET (0x338) -#define DSP2_BACK_B15_PRE DSP2_BACK_B15_PRE -#define DSP2_BACK_B15_PRE_POS (0U) -#define DSP2_BACK_B15_PRE_LEN (8U) -#define DSP2_BACK_B15_PRE_MSK (((1U << DSP2_BACK_B15_PRE_LEN) - 1) << DSP2_BACK_B15_PRE_POS) -#define DSP2_BACK_B15_PRE_UMSK (~(((1U << DSP2_BACK_B15_PRE_LEN) - 1) << DSP2_BACK_B15_PRE_POS)) -#define DSP2_BACK_B16_PRE DSP2_BACK_B16_PRE -#define DSP2_BACK_B16_PRE_POS (8U) -#define DSP2_BACK_B16_PRE_LEN (8U) -#define DSP2_BACK_B16_PRE_MSK (((1U << DSP2_BACK_B16_PRE_LEN) - 1) << DSP2_BACK_B16_PRE_POS) -#define DSP2_BACK_B16_PRE_UMSK (~(((1U << DSP2_BACK_B16_PRE_LEN) - 1) << DSP2_BACK_B16_PRE_POS)) -#define DSP2_BACK_B17_PRE DSP2_BACK_B17_PRE -#define DSP2_BACK_B17_PRE_POS (16U) -#define DSP2_BACK_B17_PRE_LEN (8U) -#define DSP2_BACK_B17_PRE_MSK (((1U << DSP2_BACK_B17_PRE_LEN) - 1) << DSP2_BACK_B17_PRE_POS) -#define DSP2_BACK_B17_PRE_UMSK (~(((1U << DSP2_BACK_B17_PRE_LEN) - 1) << DSP2_BACK_B17_PRE_POS)) -#define DSP2_BACK_B18_PRE DSP2_BACK_B18_PRE -#define DSP2_BACK_B18_PRE_POS (24U) -#define DSP2_BACK_B18_PRE_LEN (8U) -#define DSP2_BACK_B18_PRE_MSK (((1U << DSP2_BACK_B18_PRE_LEN) - 1) << DSP2_BACK_B18_PRE_POS) -#define DSP2_BACK_B18_PRE_UMSK (~(((1U << DSP2_BACK_B18_PRE_LEN) - 1) << DSP2_BACK_B18_PRE_POS)) - -/* 0x33C : conv_mode */ -#define DSP2_BACK_CONV_MODE_OFFSET (0x33C) -#define DSP2_BACK_CONV_MODE_W DSP2_BACK_CONV_MODE_W -#define DSP2_BACK_CONV_MODE_W_POS (0U) -#define DSP2_BACK_CONV_MODE_W_LEN (1U) -#define DSP2_BACK_CONV_MODE_W_MSK (((1U << DSP2_BACK_CONV_MODE_W_LEN) - 1) << DSP2_BACK_CONV_MODE_W_POS) -#define DSP2_BACK_CONV_MODE_W_UMSK (~(((1U << DSP2_BACK_CONV_MODE_W_LEN) - 1) << DSP2_BACK_CONV_MODE_W_POS)) - -/* 0x348 : edge_enhance */ -#define DSP2_BACK_EDGE_ENHANCE_OFFSET (0x348) -#define DSP2_BACK_ENHANCE_LEVEL_W DSP2_BACK_ENHANCE_LEVEL_W -#define DSP2_BACK_ENHANCE_LEVEL_W_POS (0U) -#define DSP2_BACK_ENHANCE_LEVEL_W_LEN (7U) -#define DSP2_BACK_ENHANCE_LEVEL_W_MSK (((1U << DSP2_BACK_ENHANCE_LEVEL_W_LEN) - 1) << DSP2_BACK_ENHANCE_LEVEL_W_POS) -#define DSP2_BACK_ENHANCE_LEVEL_W_UMSK (~(((1U << DSP2_BACK_ENHANCE_LEVEL_W_LEN) - 1) << DSP2_BACK_ENHANCE_LEVEL_W_POS)) -#define DSP2_BACK_EDGE_LIMIT_W DSP2_BACK_EDGE_LIMIT_W -#define DSP2_BACK_EDGE_LIMIT_W_POS (8U) -#define DSP2_BACK_EDGE_LIMIT_W_LEN (8U) -#define DSP2_BACK_EDGE_LIMIT_W_MSK (((1U << DSP2_BACK_EDGE_LIMIT_W_LEN) - 1) << DSP2_BACK_EDGE_LIMIT_W_POS) -#define DSP2_BACK_EDGE_LIMIT_W_UMSK (~(((1U << DSP2_BACK_EDGE_LIMIT_W_LEN) - 1) << DSP2_BACK_EDGE_LIMIT_W_POS)) -#define DSP2_BACK_HPF_RATE_W DSP2_BACK_HPF_RATE_W -#define DSP2_BACK_HPF_RATE_W_POS (16U) -#define DSP2_BACK_HPF_RATE_W_LEN (4U) -#define DSP2_BACK_HPF_RATE_W_MSK (((1U << DSP2_BACK_HPF_RATE_W_LEN) - 1) << DSP2_BACK_HPF_RATE_W_POS) -#define DSP2_BACK_HPF_RATE_W_UMSK (~(((1U << DSP2_BACK_HPF_RATE_W_LEN) - 1) << DSP2_BACK_HPF_RATE_W_POS)) -#define DSP2_BACK_NOISE_THRESHOLD_PRE DSP2_BACK_NOISE_THRESHOLD_PRE -#define DSP2_BACK_NOISE_THRESHOLD_PRE_POS (24U) -#define DSP2_BACK_NOISE_THRESHOLD_PRE_LEN (7U) -#define DSP2_BACK_NOISE_THRESHOLD_PRE_MSK (((1U << DSP2_BACK_NOISE_THRESHOLD_PRE_LEN) - 1) << DSP2_BACK_NOISE_THRESHOLD_PRE_POS) -#define DSP2_BACK_NOISE_THRESHOLD_PRE_UMSK (~(((1U << DSP2_BACK_NOISE_THRESHOLD_PRE_LEN) - 1) << DSP2_BACK_NOISE_THRESHOLD_PRE_POS)) - -/* 0x34C : YUVC_A */ -#define DSP2_BACK_YUVC_A_OFFSET (0x34C) -#define DSP2_BACK_YBRIGHTNESS_W DSP2_BACK_YBRIGHTNESS_W -#define DSP2_BACK_YBRIGHTNESS_W_POS (0U) -#define DSP2_BACK_YBRIGHTNESS_W_LEN (8U) -#define DSP2_BACK_YBRIGHTNESS_W_MSK (((1U << DSP2_BACK_YBRIGHTNESS_W_LEN) - 1) << DSP2_BACK_YBRIGHTNESS_W_POS) -#define DSP2_BACK_YBRIGHTNESS_W_UMSK (~(((1U << DSP2_BACK_YBRIGHTNESS_W_LEN) - 1) << DSP2_BACK_YBRIGHTNESS_W_POS)) -#define DSP2_BACK_YCONTRAST_W DSP2_BACK_YCONTRAST_W -#define DSP2_BACK_YCONTRAST_W_POS (8U) -#define DSP2_BACK_YCONTRAST_W_LEN (8U) -#define DSP2_BACK_YCONTRAST_W_MSK (((1U << DSP2_BACK_YCONTRAST_W_LEN) - 1) << DSP2_BACK_YCONTRAST_W_POS) -#define DSP2_BACK_YCONTRAST_W_UMSK (~(((1U << DSP2_BACK_YCONTRAST_W_LEN) - 1) << DSP2_BACK_YCONTRAST_W_POS)) -#define DSP2_BACK_CBSATURATION_PRE DSP2_BACK_CBSATURATION_PRE -#define DSP2_BACK_CBSATURATION_PRE_POS (16U) -#define DSP2_BACK_CBSATURATION_PRE_LEN (8U) -#define DSP2_BACK_CBSATURATION_PRE_MSK (((1U << DSP2_BACK_CBSATURATION_PRE_LEN) - 1) << DSP2_BACK_CBSATURATION_PRE_POS) -#define DSP2_BACK_CBSATURATION_PRE_UMSK (~(((1U << DSP2_BACK_CBSATURATION_PRE_LEN) - 1) << DSP2_BACK_CBSATURATION_PRE_POS)) -#define DSP2_BACK_CRSATURATION_PRE DSP2_BACK_CRSATURATION_PRE -#define DSP2_BACK_CRSATURATION_PRE_POS (24U) -#define DSP2_BACK_CRSATURATION_PRE_LEN (8U) -#define DSP2_BACK_CRSATURATION_PRE_MSK (((1U << DSP2_BACK_CRSATURATION_PRE_LEN) - 1) << DSP2_BACK_CRSATURATION_PRE_POS) -#define DSP2_BACK_CRSATURATION_PRE_UMSK (~(((1U << DSP2_BACK_CRSATURATION_PRE_LEN) - 1) << DSP2_BACK_CRSATURATION_PRE_POS)) - -/* 0x350 : YUVC_B */ -#define DSP2_BACK_YUVC_B_OFFSET (0x350) -#define DSP2_BACK_SPECIALMODE_W DSP2_BACK_SPECIALMODE_W -#define DSP2_BACK_SPECIALMODE_W_POS (0U) -#define DSP2_BACK_SPECIALMODE_W_LEN (3U) -#define DSP2_BACK_SPECIALMODE_W_MSK (((1U << DSP2_BACK_SPECIALMODE_W_LEN) - 1) << DSP2_BACK_SPECIALMODE_W_POS) -#define DSP2_BACK_SPECIALMODE_W_UMSK (~(((1U << DSP2_BACK_SPECIALMODE_W_LEN) - 1) << DSP2_BACK_SPECIALMODE_W_POS)) -#define DSP2_BACK_C444TO422FILTERINGMODE_W DSP2_BACK_C444TO422FILTERINGMODE_W -#define DSP2_BACK_C444TO422FILTERINGMODE_W_POS (4U) -#define DSP2_BACK_C444TO422FILTERINGMODE_W_LEN (1U) -#define DSP2_BACK_C444TO422FILTERINGMODE_W_MSK (((1U << DSP2_BACK_C444TO422FILTERINGMODE_W_LEN) - 1) << DSP2_BACK_C444TO422FILTERINGMODE_W_POS) -#define DSP2_BACK_C444TO422FILTERINGMODE_W_UMSK (~(((1U << DSP2_BACK_C444TO422FILTERINGMODE_W_LEN) - 1) << DSP2_BACK_C444TO422FILTERINGMODE_W_POS)) -#define DSP2_BACK_SEPIACB_W DSP2_BACK_SEPIACB_W -#define DSP2_BACK_SEPIACB_W_POS (8U) -#define DSP2_BACK_SEPIACB_W_LEN (8U) -#define DSP2_BACK_SEPIACB_W_MSK (((1U << DSP2_BACK_SEPIACB_W_LEN) - 1) << DSP2_BACK_SEPIACB_W_POS) -#define DSP2_BACK_SEPIACB_W_UMSK (~(((1U << DSP2_BACK_SEPIACB_W_LEN) - 1) << DSP2_BACK_SEPIACB_W_POS)) -#define DSP2_BACK_SEPIACR_W DSP2_BACK_SEPIACR_W -#define DSP2_BACK_SEPIACR_W_POS (16U) -#define DSP2_BACK_SEPIACR_W_LEN (8U) -#define DSP2_BACK_SEPIACR_W_MSK (((1U << DSP2_BACK_SEPIACR_W_LEN) - 1) << DSP2_BACK_SEPIACR_W_POS) -#define DSP2_BACK_SEPIACR_W_UMSK (~(((1U << DSP2_BACK_SEPIACR_W_LEN) - 1) << DSP2_BACK_SEPIACR_W_POS)) -#define DSP2_BACK_SOLARTHRED_W DSP2_BACK_SOLARTHRED_W -#define DSP2_BACK_SOLARTHRED_W_POS (24U) -#define DSP2_BACK_SOLARTHRED_W_LEN (8U) -#define DSP2_BACK_SOLARTHRED_W_MSK (((1U << DSP2_BACK_SOLARTHRED_W_LEN) - 1) << DSP2_BACK_SOLARTHRED_W_POS) -#define DSP2_BACK_SOLARTHRED_W_UMSK (~(((1U << DSP2_BACK_SOLARTHRED_W_LEN) - 1) << DSP2_BACK_SOLARTHRED_W_POS)) - -/* 0x354 : DNR_A */ -#define DSP2_BACK_DNR_A_OFFSET (0x354) -#define DSP2_BACK_NOISE_LEVEL_PRE DSP2_BACK_NOISE_LEVEL_PRE -#define DSP2_BACK_NOISE_LEVEL_PRE_POS (0U) -#define DSP2_BACK_NOISE_LEVEL_PRE_LEN (6U) -#define DSP2_BACK_NOISE_LEVEL_PRE_MSK (((1U << DSP2_BACK_NOISE_LEVEL_PRE_LEN) - 1) << DSP2_BACK_NOISE_LEVEL_PRE_POS) -#define DSP2_BACK_NOISE_LEVEL_PRE_UMSK (~(((1U << DSP2_BACK_NOISE_LEVEL_PRE_LEN) - 1) << DSP2_BACK_NOISE_LEVEL_PRE_POS)) -#define DSP2_BACK_NR_HSIZE_PRE DSP2_BACK_NR_HSIZE_PRE -#define DSP2_BACK_NR_HSIZE_PRE_POS (8U) -#define DSP2_BACK_NR_HSIZE_PRE_LEN (16U) -#define DSP2_BACK_NR_HSIZE_PRE_MSK (((1U << DSP2_BACK_NR_HSIZE_PRE_LEN) - 1) << DSP2_BACK_NR_HSIZE_PRE_POS) -#define DSP2_BACK_NR_HSIZE_PRE_UMSK (~(((1U << DSP2_BACK_NR_HSIZE_PRE_LEN) - 1) << DSP2_BACK_NR_HSIZE_PRE_POS)) -#define DSP2_BACK_FILT_STRENGTH_2D_PRE DSP2_BACK_FILT_STRENGTH_2D_PRE -#define DSP2_BACK_FILT_STRENGTH_2D_PRE_POS (24U) -#define DSP2_BACK_FILT_STRENGTH_2D_PRE_LEN (4U) -#define DSP2_BACK_FILT_STRENGTH_2D_PRE_MSK (((1U << DSP2_BACK_FILT_STRENGTH_2D_PRE_LEN) - 1) << DSP2_BACK_FILT_STRENGTH_2D_PRE_POS) -#define DSP2_BACK_FILT_STRENGTH_2D_PRE_UMSK (~(((1U << DSP2_BACK_FILT_STRENGTH_2D_PRE_LEN) - 1) << DSP2_BACK_FILT_STRENGTH_2D_PRE_POS)) -#define DSP2_BACK_FILT_STRENGTH_3D_PRE DSP2_BACK_FILT_STRENGTH_3D_PRE -#define DSP2_BACK_FILT_STRENGTH_3D_PRE_POS (28U) -#define DSP2_BACK_FILT_STRENGTH_3D_PRE_LEN (4U) -#define DSP2_BACK_FILT_STRENGTH_3D_PRE_MSK (((1U << DSP2_BACK_FILT_STRENGTH_3D_PRE_LEN) - 1) << DSP2_BACK_FILT_STRENGTH_3D_PRE_POS) -#define DSP2_BACK_FILT_STRENGTH_3D_PRE_UMSK (~(((1U << DSP2_BACK_FILT_STRENGTH_3D_PRE_LEN) - 1) << DSP2_BACK_FILT_STRENGTH_3D_PRE_POS)) - -/* 0x358 : DNR_B */ -#define DSP2_BACK_DNR_B_OFFSET (0x358) -#define DSP2_BACK_DELAYNUM3DNR_W DSP2_BACK_DELAYNUM3DNR_W -#define DSP2_BACK_DELAYNUM3DNR_W_POS (0U) -#define DSP2_BACK_DELAYNUM3DNR_W_LEN (3U) -#define DSP2_BACK_DELAYNUM3DNR_W_MSK (((1U << DSP2_BACK_DELAYNUM3DNR_W_LEN) - 1) << DSP2_BACK_DELAYNUM3DNR_W_POS) -#define DSP2_BACK_DELAYNUM3DNR_W_UMSK (~(((1U << DSP2_BACK_DELAYNUM3DNR_W_LEN) - 1) << DSP2_BACK_DELAYNUM3DNR_W_POS)) -#define DSP2_BACK_CBCR_SELECT_W DSP2_BACK_CBCR_SELECT_W -#define DSP2_BACK_CBCR_SELECT_W_POS (8U) -#define DSP2_BACK_CBCR_SELECT_W_LEN (1U) -#define DSP2_BACK_CBCR_SELECT_W_MSK (((1U << DSP2_BACK_CBCR_SELECT_W_LEN) - 1) << DSP2_BACK_CBCR_SELECT_W_POS) -#define DSP2_BACK_CBCR_SELECT_W_UMSK (~(((1U << DSP2_BACK_CBCR_SELECT_W_LEN) - 1) << DSP2_BACK_CBCR_SELECT_W_POS)) -#define DSP2_BACK_OUT_FORMAT_W DSP2_BACK_OUT_FORMAT_W -#define DSP2_BACK_OUT_FORMAT_W_POS (9U) -#define DSP2_BACK_OUT_FORMAT_W_LEN (2U) -#define DSP2_BACK_OUT_FORMAT_W_MSK (((1U << DSP2_BACK_OUT_FORMAT_W_LEN) - 1) << DSP2_BACK_OUT_FORMAT_W_POS) -#define DSP2_BACK_OUT_FORMAT_W_UMSK (~(((1U << DSP2_BACK_OUT_FORMAT_W_LEN) - 1) << DSP2_BACK_OUT_FORMAT_W_POS)) - -/* 0x3FF : DVI_HDMI_MODE */ -#define DSP2_BACK_DVI_HDMI_MODE_OFFSET (0x3FF) -#define DSP2_BACK_DVI_HDMI_MODE_W DSP2_BACK_DVI_HDMI_MODE_W -#define DSP2_BACK_DVI_HDMI_MODE_W_POS (0U) -#define DSP2_BACK_DVI_HDMI_MODE_W_LEN (1U) -#define DSP2_BACK_DVI_HDMI_MODE_W_MSK (((1U << DSP2_BACK_DVI_HDMI_MODE_W_LEN) - 1) << DSP2_BACK_DVI_HDMI_MODE_W_POS) -#define DSP2_BACK_DVI_HDMI_MODE_W_UMSK (~(((1U << DSP2_BACK_DVI_HDMI_MODE_W_LEN) - 1) << DSP2_BACK_DVI_HDMI_MODE_W_POS)) - -struct dsp2_back_reg { - /* 0x0 reserved */ - uint8_t RESERVED0x0[788]; - - /* 0x314 : ccr_coef_A */ - union { - struct - { - uint32_t reserved_0_15 : 16; /* [15: 0], rsvd, 0x0 */ - uint32_t a11_pre : 12; /* [27:16], r/w, 0x200 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } ccr_coef_A; - - /* 0x318 : ccr_coef_B */ - union { - struct - { - uint32_t a12_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t a13_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } ccr_coef_B; - - /* 0x31C : ccr_coef_C */ - union { - struct - { - uint32_t a21_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t a22_pre : 12; /* [27:16], r/w, 0x200 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } ccr_coef_C; - - /* 0x320 : ccr_coef_D */ - union { - struct - { - uint32_t a23_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t a31_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } ccr_coef_D; - - /* 0x324 : ccr_coef_E */ - union { - struct - { - uint32_t a32_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t a33_pre : 12; /* [27:16], r/w, 0x200 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } ccr_coef_E; - - /* 0x328 : gamma_A */ - union { - struct - { - uint32_t gamma_on_pre : 1; /* [ 0], r/w, 0x0 */ - uint32_t gamma_eb_pre : 1; /* [ 1], r/w, 0x0 */ - uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ - uint32_t b0_pre : 8; /* [15: 8], r/w, 0x0 */ - uint32_t b1_pre : 8; /* [23:16], r/w, 0x4 */ - uint32_t b2_pre : 8; /* [31:24], r/w, 0x8 */ - } BF; - uint32_t WORD; - } gamma_A; - - /* 0x32C : gamma_B */ - union { - struct - { - uint32_t b3_pre : 8; /* [ 7: 0], r/w, 0x10 */ - uint32_t b4_pre : 8; /* [15: 8], r/w, 0x20 */ - uint32_t b5_pre : 8; /* [23:16], r/w, 0x30 */ - uint32_t b6_pre : 8; /* [31:24], r/w, 0x40 */ - } BF; - uint32_t WORD; - } gamma_B; - - /* 0x330 : gamma_C */ - union { - struct - { - uint32_t b7_pre : 8; /* [ 7: 0], r/w, 0x50 */ - uint32_t b8_pre : 8; /* [15: 8], r/w, 0x60 */ - uint32_t b9_pre : 8; /* [23:16], r/w, 0x70 */ - uint32_t b10_pre : 8; /* [31:24], r/w, 0x80 */ - } BF; - uint32_t WORD; - } gamma_C; - - /* 0x334 : gamma_D */ - union { - struct - { - uint32_t b11_pre : 8; /* [ 7: 0], r/w, 0x90 */ - uint32_t b12_pre : 8; /* [15: 8], r/w, 0xa0 */ - uint32_t b13_pre : 8; /* [23:16], r/w, 0xb0 */ - uint32_t b14_pre : 8; /* [31:24], r/w, 0xc0 */ - } BF; - uint32_t WORD; - } gamma_D; - - /* 0x338 : gamma_E */ - union { - struct - { - uint32_t b15_pre : 8; /* [ 7: 0], r/w, 0xd0 */ - uint32_t b16_pre : 8; /* [15: 8], r/w, 0xe0 */ - uint32_t b17_pre : 8; /* [23:16], r/w, 0xf0 */ - uint32_t b18_pre : 8; /* [31:24], r/w, 0xff */ - } BF; - uint32_t WORD; - } gamma_E; - - /* 0x33C : conv_mode */ - union { - struct - { - uint32_t conv_mode_w : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } conv_mode; - - /* 0x340 reserved */ - uint8_t RESERVED0x340[8]; - - /* 0x348 : edge_enhance */ - union { - struct - { - uint32_t enhance_level_w : 7; /* [ 6: 0], r/w, 0x69 */ - uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ - uint32_t edge_limit_w : 8; /* [15: 8], r/w, 0x30 */ - uint32_t HPF_rate_w : 4; /* [19:16], r/w, 0x4 */ - uint32_t reserved_20_23 : 4; /* [23:20], rsvd, 0x0 */ - uint32_t noise_threshold_pre : 7; /* [30:24], r/w, 0x0 */ - uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } edge_enhance; - - /* 0x34C : YUVC_A */ - union { - struct - { - uint32_t YBrightness_w : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t YContrast_w : 8; /* [15: 8], r/w, 0x0 */ - uint32_t CbSaturation_pre : 8; /* [23:16], r/w, 0x80 */ - uint32_t CrSaturation_pre : 8; /* [31:24], r/w, 0x80 */ - } BF; - uint32_t WORD; - } YUVC_A; - - /* 0x350 : YUVC_B */ - union { - struct - { - uint32_t SpecialMode_w : 3; /* [ 2: 0], r/w, 0x0 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t C444to422Filteringmode_w : 1; /* [ 4], r/w, 0x0 */ - uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ - uint32_t SepiaCb_w : 8; /* [15: 8], r/w, 0x73 */ - uint32_t SepiaCr_w : 8; /* [23:16], r/w, 0x89 */ - uint32_t SolarThred_w : 8; /* [31:24], r/w, 0x80 */ - } BF; - uint32_t WORD; - } YUVC_B; - - /* 0x354 : DNR_A */ - union { - struct - { - uint32_t noise_level_pre : 6; /* [ 5: 0], r/w, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t nr_hsize_pre : 16; /* [23: 8], r/w, 0x788 */ - uint32_t Filt_Strength_2D_pre : 4; /* [27:24], r/w, 0x6 */ - uint32_t Filt_Strength_3D_pre : 4; /* [31:28], r/w, 0x5 */ - } BF; - uint32_t WORD; - } DNR_A; - - /* 0x358 : DNR_B */ - union { - struct - { - uint32_t DelayNum3DNR_w : 3; /* [ 2: 0], r/w, 0x4 */ - uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */ - uint32_t CbCr_select_w : 1; /* [ 8], r/w, 0x1 */ - uint32_t out_format_w : 2; /* [10: 9], r/w, 0x1 */ - uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DNR_B; - - /* 0x35c reserved */ - uint8_t RESERVED0x35c[163]; - - /* 0x3FF : DVI_HDMI_MODE */ - union { - struct - { - uint32_t DVI_HDMI_MODE_w : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DVI_HDMI_MODE; -}; - -typedef volatile struct dsp2_back_reg dsp2_back_reg_t; - -#endif /* __DSP2_BACK_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_blae_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_blae_reg.h deleted file mode 100644 index f347e0fed3..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_blae_reg.h +++ /dev/null @@ -1,95 +0,0 @@ -/** - ****************************************************************************** - * @file dsp2_blae_reg.h - * @version V1.2 - * @date 2019-03-28 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2018 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __DSP2_BLAE_REG_H__ -#define __DSP2_BLAE_REG_H__ - -#include "bl808.h" - -/* 0x500 : blae_read_grid_addr */ -#define DSP2_BLAE_BLAE_READ_GRID_ADDR_OFFSET (0x500) -#define DSP2_BLAE_BLAE_READ_GRID_ADDR DSP2_BLAE_BLAE_READ_GRID_ADDR -#define DSP2_BLAE_BLAE_READ_GRID_ADDR_POS (0U) -#define DSP2_BLAE_BLAE_READ_GRID_ADDR_LEN (9U) -#define DSP2_BLAE_BLAE_READ_GRID_ADDR_MSK (((1U << DSP2_BLAE_BLAE_READ_GRID_ADDR_LEN) - 1) << DSP2_BLAE_BLAE_READ_GRID_ADDR_POS) -#define DSP2_BLAE_BLAE_READ_GRID_ADDR_UMSK (~(((1U << DSP2_BLAE_BLAE_READ_GRID_ADDR_LEN) - 1) << DSP2_BLAE_BLAE_READ_GRID_ADDR_POS)) -#define DSP2_BLAE_BLAE_BUF_IDX DSP2_BLAE_BLAE_BUF_IDX -#define DSP2_BLAE_BLAE_BUF_IDX_POS (16U) -#define DSP2_BLAE_BLAE_BUF_IDX_LEN (1U) -#define DSP2_BLAE_BLAE_BUF_IDX_MSK (((1U << DSP2_BLAE_BLAE_BUF_IDX_LEN) - 1) << DSP2_BLAE_BLAE_BUF_IDX_POS) -#define DSP2_BLAE_BLAE_BUF_IDX_UMSK (~(((1U << DSP2_BLAE_BLAE_BUF_IDX_LEN) - 1) << DSP2_BLAE_BLAE_BUF_IDX_POS)) -#define DSP2_BLAE_BLAE_W_CNT DSP2_BLAE_BLAE_W_CNT -#define DSP2_BLAE_BLAE_W_CNT_POS (20U) -#define DSP2_BLAE_BLAE_W_CNT_LEN (5U) -#define DSP2_BLAE_BLAE_W_CNT_MSK (((1U << DSP2_BLAE_BLAE_W_CNT_LEN) - 1) << DSP2_BLAE_BLAE_W_CNT_POS) -#define DSP2_BLAE_BLAE_W_CNT_UMSK (~(((1U << DSP2_BLAE_BLAE_W_CNT_LEN) - 1) << DSP2_BLAE_BLAE_W_CNT_POS)) - -/* 0x504 : blae_grid_data */ -#define DSP2_BLAE_BLAE_GRID_DATA_OFFSET (0x504) -#define DSP2_BLAE_BLAE_GRID_DATA DSP2_BLAE_BLAE_GRID_DATA -#define DSP2_BLAE_BLAE_GRID_DATA_POS (0U) -#define DSP2_BLAE_BLAE_GRID_DATA_LEN (32U) -#define DSP2_BLAE_BLAE_GRID_DATA_MSK (((1U << DSP2_BLAE_BLAE_GRID_DATA_LEN) - 1) << DSP2_BLAE_BLAE_GRID_DATA_POS) -#define DSP2_BLAE_BLAE_GRID_DATA_UMSK (~(((1U << DSP2_BLAE_BLAE_GRID_DATA_LEN) - 1) << DSP2_BLAE_BLAE_GRID_DATA_POS)) - -struct dsp2_blae_reg { - /* 0x0 reserved */ - uint8_t RESERVED0x0[1280]; - - /* 0x500 : blae_read_grid_addr */ - union { - struct { - uint32_t blae_read_grid_addr : 9; /* [ 8: 0], r/w, 0x0 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t blae_buf_idx : 1; /* [ 16], r, 0x0 */ - uint32_t reserved_17_19 : 3; /* [19:17], rsvd, 0x0 */ - uint32_t blae_w_cnt : 5; /* [24:20], r, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } blae_read_grid_addr; - - /* 0x504 : blae_grid_data */ - union { - struct { - uint32_t blae_grid_data : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } blae_grid_data; -}; - -typedef volatile struct dsp2_blae_reg dsp2_blae_reg_t; - -#endif /* __DSP2_BLAE_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_blawb_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_blawb_reg.h deleted file mode 100644 index 0ab82e1902..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_blawb_reg.h +++ /dev/null @@ -1,95 +0,0 @@ -/** - ****************************************************************************** - * @file dsp2_blawb_reg.h - * @version V1.2 - * @date 2019-04-25 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2018 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __DSP2_BLAWB_REG_H__ -#define __DSP2_BLAWB_REG_H__ - -#include "bl808.h" - -/* 0x600 : blawb_read_grid_addr */ -#define DSP2_BLAWB_BLAWB_READ_GRID_ADDR_OFFSET (0x600) -#define DSP2_BLAWB_BLAWB_READ_GRID_ADDR DSP2_BLAWB_BLAWB_READ_GRID_ADDR -#define DSP2_BLAWB_BLAWB_READ_GRID_ADDR_POS (0U) -#define DSP2_BLAWB_BLAWB_READ_GRID_ADDR_LEN (12U) -#define DSP2_BLAWB_BLAWB_READ_GRID_ADDR_MSK (((1U << DSP2_BLAWB_BLAWB_READ_GRID_ADDR_LEN) - 1) << DSP2_BLAWB_BLAWB_READ_GRID_ADDR_POS) -#define DSP2_BLAWB_BLAWB_READ_GRID_ADDR_UMSK (~(((1U << DSP2_BLAWB_BLAWB_READ_GRID_ADDR_LEN) - 1) << DSP2_BLAWB_BLAWB_READ_GRID_ADDR_POS)) -#define DSP2_BLAWB_BLAWB_BUF_IDX DSP2_BLAWB_BLAWB_BUF_IDX -#define DSP2_BLAWB_BLAWB_BUF_IDX_POS (16U) -#define DSP2_BLAWB_BLAWB_BUF_IDX_LEN (1U) -#define DSP2_BLAWB_BLAWB_BUF_IDX_MSK (((1U << DSP2_BLAWB_BLAWB_BUF_IDX_LEN) - 1) << DSP2_BLAWB_BLAWB_BUF_IDX_POS) -#define DSP2_BLAWB_BLAWB_BUF_IDX_UMSK (~(((1U << DSP2_BLAWB_BLAWB_BUF_IDX_LEN) - 1) << DSP2_BLAWB_BLAWB_BUF_IDX_POS)) -#define DSP2_BLAWB_BLAWB_W_CNT DSP2_BLAWB_BLAWB_W_CNT -#define DSP2_BLAWB_BLAWB_W_CNT_POS (20U) -#define DSP2_BLAWB_BLAWB_W_CNT_LEN (5U) -#define DSP2_BLAWB_BLAWB_W_CNT_MSK (((1U << DSP2_BLAWB_BLAWB_W_CNT_LEN) - 1) << DSP2_BLAWB_BLAWB_W_CNT_POS) -#define DSP2_BLAWB_BLAWB_W_CNT_UMSK (~(((1U << DSP2_BLAWB_BLAWB_W_CNT_LEN) - 1) << DSP2_BLAWB_BLAWB_W_CNT_POS)) - -/* 0x604 : blawb_grid_data */ -#define DSP2_BLAWB_BLAWB_GRID_DATA_OFFSET (0x604) -#define DSP2_BLAWB_BLAWB_GRID_DATA DSP2_BLAWB_BLAWB_GRID_DATA -#define DSP2_BLAWB_BLAWB_GRID_DATA_POS (0U) -#define DSP2_BLAWB_BLAWB_GRID_DATA_LEN (32U) -#define DSP2_BLAWB_BLAWB_GRID_DATA_MSK (((1U << DSP2_BLAWB_BLAWB_GRID_DATA_LEN) - 1) << DSP2_BLAWB_BLAWB_GRID_DATA_POS) -#define DSP2_BLAWB_BLAWB_GRID_DATA_UMSK (~(((1U << DSP2_BLAWB_BLAWB_GRID_DATA_LEN) - 1) << DSP2_BLAWB_BLAWB_GRID_DATA_POS)) - -struct dsp2_blawb_reg { - /* 0x0 reserved */ - uint8_t RESERVED0x0[1536]; - - /* 0x600 : blawb_read_grid_addr */ - union { - struct { - uint32_t blawb_read_grid_addr : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t blawb_buf_idx : 1; /* [ 16], r, 0x0 */ - uint32_t reserved_17_19 : 3; /* [19:17], rsvd, 0x0 */ - uint32_t blawb_w_cnt : 5; /* [24:20], r, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } blawb_read_grid_addr; - - /* 0x604 : blawb_grid_data */ - union { - struct { - uint32_t blawb_grid_data : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } blawb_grid_data; -}; - -typedef volatile struct dsp2_blawb_reg dsp2_blawb_reg_t; - -#endif /* __DSP2_BLAWB_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_blback_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_blback_reg.h deleted file mode 100644 index 09e0f3dc07..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_blback_reg.h +++ /dev/null @@ -1,8061 +0,0 @@ -/** - ****************************************************************************** - * @file dsp2_blback_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __DSP2_BLBACK_REG_H__ -#define __DSP2_BLBACK_REG_H__ - -#include "bl808.h" - -/* 0x314 : ccr_coef_A */ -#define DSP2_BLBACK_CCR_COEF_A_OFFSET (0x314) -#define DSP2_BLBACK_A11_PRE DSP2_BLBACK_A11_PRE -#define DSP2_BLBACK_A11_PRE_POS (16U) -#define DSP2_BLBACK_A11_PRE_LEN (12U) -#define DSP2_BLBACK_A11_PRE_MSK (((1U << DSP2_BLBACK_A11_PRE_LEN) - 1) << DSP2_BLBACK_A11_PRE_POS) -#define DSP2_BLBACK_A11_PRE_UMSK (~(((1U << DSP2_BLBACK_A11_PRE_LEN) - 1) << DSP2_BLBACK_A11_PRE_POS)) - -/* 0x318 : ccr_coef_B */ -#define DSP2_BLBACK_CCR_COEF_B_OFFSET (0x318) -#define DSP2_BLBACK_A12_PRE DSP2_BLBACK_A12_PRE -#define DSP2_BLBACK_A12_PRE_POS (0U) -#define DSP2_BLBACK_A12_PRE_LEN (12U) -#define DSP2_BLBACK_A12_PRE_MSK (((1U << DSP2_BLBACK_A12_PRE_LEN) - 1) << DSP2_BLBACK_A12_PRE_POS) -#define DSP2_BLBACK_A12_PRE_UMSK (~(((1U << DSP2_BLBACK_A12_PRE_LEN) - 1) << DSP2_BLBACK_A12_PRE_POS)) -#define DSP2_BLBACK_A13_PRE DSP2_BLBACK_A13_PRE -#define DSP2_BLBACK_A13_PRE_POS (16U) -#define DSP2_BLBACK_A13_PRE_LEN (12U) -#define DSP2_BLBACK_A13_PRE_MSK (((1U << DSP2_BLBACK_A13_PRE_LEN) - 1) << DSP2_BLBACK_A13_PRE_POS) -#define DSP2_BLBACK_A13_PRE_UMSK (~(((1U << DSP2_BLBACK_A13_PRE_LEN) - 1) << DSP2_BLBACK_A13_PRE_POS)) - -/* 0x31C : ccr_coef_C */ -#define DSP2_BLBACK_CCR_COEF_C_OFFSET (0x31C) -#define DSP2_BLBACK_A21_PRE DSP2_BLBACK_A21_PRE -#define DSP2_BLBACK_A21_PRE_POS (0U) -#define DSP2_BLBACK_A21_PRE_LEN (12U) -#define DSP2_BLBACK_A21_PRE_MSK (((1U << DSP2_BLBACK_A21_PRE_LEN) - 1) << DSP2_BLBACK_A21_PRE_POS) -#define DSP2_BLBACK_A21_PRE_UMSK (~(((1U << DSP2_BLBACK_A21_PRE_LEN) - 1) << DSP2_BLBACK_A21_PRE_POS)) -#define DSP2_BLBACK_A22_PRE DSP2_BLBACK_A22_PRE -#define DSP2_BLBACK_A22_PRE_POS (16U) -#define DSP2_BLBACK_A22_PRE_LEN (12U) -#define DSP2_BLBACK_A22_PRE_MSK (((1U << DSP2_BLBACK_A22_PRE_LEN) - 1) << DSP2_BLBACK_A22_PRE_POS) -#define DSP2_BLBACK_A22_PRE_UMSK (~(((1U << DSP2_BLBACK_A22_PRE_LEN) - 1) << DSP2_BLBACK_A22_PRE_POS)) - -/* 0x320 : ccr_coef_D */ -#define DSP2_BLBACK_CCR_COEF_D_OFFSET (0x320) -#define DSP2_BLBACK_A23_PRE DSP2_BLBACK_A23_PRE -#define DSP2_BLBACK_A23_PRE_POS (0U) -#define DSP2_BLBACK_A23_PRE_LEN (12U) -#define DSP2_BLBACK_A23_PRE_MSK (((1U << DSP2_BLBACK_A23_PRE_LEN) - 1) << DSP2_BLBACK_A23_PRE_POS) -#define DSP2_BLBACK_A23_PRE_UMSK (~(((1U << DSP2_BLBACK_A23_PRE_LEN) - 1) << DSP2_BLBACK_A23_PRE_POS)) -#define DSP2_BLBACK_A31_PRE DSP2_BLBACK_A31_PRE -#define DSP2_BLBACK_A31_PRE_POS (16U) -#define DSP2_BLBACK_A31_PRE_LEN (12U) -#define DSP2_BLBACK_A31_PRE_MSK (((1U << DSP2_BLBACK_A31_PRE_LEN) - 1) << DSP2_BLBACK_A31_PRE_POS) -#define DSP2_BLBACK_A31_PRE_UMSK (~(((1U << DSP2_BLBACK_A31_PRE_LEN) - 1) << DSP2_BLBACK_A31_PRE_POS)) - -/* 0x324 : ccr_coef_E */ -#define DSP2_BLBACK_CCR_COEF_E_OFFSET (0x324) -#define DSP2_BLBACK_A32_PRE DSP2_BLBACK_A32_PRE -#define DSP2_BLBACK_A32_PRE_POS (0U) -#define DSP2_BLBACK_A32_PRE_LEN (12U) -#define DSP2_BLBACK_A32_PRE_MSK (((1U << DSP2_BLBACK_A32_PRE_LEN) - 1) << DSP2_BLBACK_A32_PRE_POS) -#define DSP2_BLBACK_A32_PRE_UMSK (~(((1U << DSP2_BLBACK_A32_PRE_LEN) - 1) << DSP2_BLBACK_A32_PRE_POS)) -#define DSP2_BLBACK_A33_PRE DSP2_BLBACK_A33_PRE -#define DSP2_BLBACK_A33_PRE_POS (16U) -#define DSP2_BLBACK_A33_PRE_LEN (12U) -#define DSP2_BLBACK_A33_PRE_MSK (((1U << DSP2_BLBACK_A33_PRE_LEN) - 1) << DSP2_BLBACK_A33_PRE_POS) -#define DSP2_BLBACK_A33_PRE_UMSK (~(((1U << DSP2_BLBACK_A33_PRE_LEN) - 1) << DSP2_BLBACK_A33_PRE_POS)) - -/* 0x328 : gamma_A */ -#define DSP2_BLBACK_GAMMA_A_OFFSET (0x328) -#define DSP2_BLBACK_GAMMA_ON_PRE DSP2_BLBACK_GAMMA_ON_PRE -#define DSP2_BLBACK_GAMMA_ON_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_ON_PRE_LEN (1U) -#define DSP2_BLBACK_GAMMA_ON_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_ON_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_ON_PRE_POS) -#define DSP2_BLBACK_GAMMA_ON_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_ON_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_ON_PRE_POS)) -#define DSP2_BLBACK_GAMMA_EB_PRE DSP2_BLBACK_GAMMA_EB_PRE -#define DSP2_BLBACK_GAMMA_EB_PRE_POS (1U) -#define DSP2_BLBACK_GAMMA_EB_PRE_LEN (1U) -#define DSP2_BLBACK_GAMMA_EB_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_EB_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_EB_PRE_POS) -#define DSP2_BLBACK_GAMMA_EB_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_EB_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_EB_PRE_POS)) -#define DSP2_BLBACK_BL_GAMMA_EN_PRE DSP2_BLBACK_BL_GAMMA_EN_PRE -#define DSP2_BLBACK_BL_GAMMA_EN_PRE_POS (4U) -#define DSP2_BLBACK_BL_GAMMA_EN_PRE_LEN (1U) -#define DSP2_BLBACK_BL_GAMMA_EN_PRE_MSK (((1U << DSP2_BLBACK_BL_GAMMA_EN_PRE_LEN) - 1) << DSP2_BLBACK_BL_GAMMA_EN_PRE_POS) -#define DSP2_BLBACK_BL_GAMMA_EN_PRE_UMSK (~(((1U << DSP2_BLBACK_BL_GAMMA_EN_PRE_LEN) - 1) << DSP2_BLBACK_BL_GAMMA_EN_PRE_POS)) - -/* 0x33C : conv_mode */ -#define DSP2_BLBACK_CONV_MODE_OFFSET (0x33C) -#define DSP2_BLBACK_CONV_MODE_W DSP2_BLBACK_CONV_MODE_W -#define DSP2_BLBACK_CONV_MODE_W_POS (0U) -#define DSP2_BLBACK_CONV_MODE_W_LEN (1U) -#define DSP2_BLBACK_CONV_MODE_W_MSK (((1U << DSP2_BLBACK_CONV_MODE_W_LEN) - 1) << DSP2_BLBACK_CONV_MODE_W_POS) -#define DSP2_BLBACK_CONV_MODE_W_UMSK (~(((1U << DSP2_BLBACK_CONV_MODE_W_LEN) - 1) << DSP2_BLBACK_CONV_MODE_W_POS)) - -/* 0x34C : YUVC_A */ -#define DSP2_BLBACK_YUVC_A_OFFSET (0x34C) -#define DSP2_BLBACK_YBRIGHTNESS_W DSP2_BLBACK_YBRIGHTNESS_W -#define DSP2_BLBACK_YBRIGHTNESS_W_POS (0U) -#define DSP2_BLBACK_YBRIGHTNESS_W_LEN (8U) -#define DSP2_BLBACK_YBRIGHTNESS_W_MSK (((1U << DSP2_BLBACK_YBRIGHTNESS_W_LEN) - 1) << DSP2_BLBACK_YBRIGHTNESS_W_POS) -#define DSP2_BLBACK_YBRIGHTNESS_W_UMSK (~(((1U << DSP2_BLBACK_YBRIGHTNESS_W_LEN) - 1) << DSP2_BLBACK_YBRIGHTNESS_W_POS)) -#define DSP2_BLBACK_YCONTRAST_W DSP2_BLBACK_YCONTRAST_W -#define DSP2_BLBACK_YCONTRAST_W_POS (8U) -#define DSP2_BLBACK_YCONTRAST_W_LEN (8U) -#define DSP2_BLBACK_YCONTRAST_W_MSK (((1U << DSP2_BLBACK_YCONTRAST_W_LEN) - 1) << DSP2_BLBACK_YCONTRAST_W_POS) -#define DSP2_BLBACK_YCONTRAST_W_UMSK (~(((1U << DSP2_BLBACK_YCONTRAST_W_LEN) - 1) << DSP2_BLBACK_YCONTRAST_W_POS)) -#define DSP2_BLBACK_CBSATURATION_PRE DSP2_BLBACK_CBSATURATION_PRE -#define DSP2_BLBACK_CBSATURATION_PRE_POS (16U) -#define DSP2_BLBACK_CBSATURATION_PRE_LEN (8U) -#define DSP2_BLBACK_CBSATURATION_PRE_MSK (((1U << DSP2_BLBACK_CBSATURATION_PRE_LEN) - 1) << DSP2_BLBACK_CBSATURATION_PRE_POS) -#define DSP2_BLBACK_CBSATURATION_PRE_UMSK (~(((1U << DSP2_BLBACK_CBSATURATION_PRE_LEN) - 1) << DSP2_BLBACK_CBSATURATION_PRE_POS)) -#define DSP2_BLBACK_CRSATURATION_PRE DSP2_BLBACK_CRSATURATION_PRE -#define DSP2_BLBACK_CRSATURATION_PRE_POS (24U) -#define DSP2_BLBACK_CRSATURATION_PRE_LEN (8U) -#define DSP2_BLBACK_CRSATURATION_PRE_MSK (((1U << DSP2_BLBACK_CRSATURATION_PRE_LEN) - 1) << DSP2_BLBACK_CRSATURATION_PRE_POS) -#define DSP2_BLBACK_CRSATURATION_PRE_UMSK (~(((1U << DSP2_BLBACK_CRSATURATION_PRE_LEN) - 1) << DSP2_BLBACK_CRSATURATION_PRE_POS)) - -/* 0x350 : YUVC_B */ -#define DSP2_BLBACK_YUVC_B_OFFSET (0x350) -#define DSP2_BLBACK_SPECIALMODE_W DSP2_BLBACK_SPECIALMODE_W -#define DSP2_BLBACK_SPECIALMODE_W_POS (0U) -#define DSP2_BLBACK_SPECIALMODE_W_LEN (3U) -#define DSP2_BLBACK_SPECIALMODE_W_MSK (((1U << DSP2_BLBACK_SPECIALMODE_W_LEN) - 1) << DSP2_BLBACK_SPECIALMODE_W_POS) -#define DSP2_BLBACK_SPECIALMODE_W_UMSK (~(((1U << DSP2_BLBACK_SPECIALMODE_W_LEN) - 1) << DSP2_BLBACK_SPECIALMODE_W_POS)) -#define DSP2_BLBACK_C444TO422FILTERINGMODE_W DSP2_BLBACK_C444TO422FILTERINGMODE_W -#define DSP2_BLBACK_C444TO422FILTERINGMODE_W_POS (4U) -#define DSP2_BLBACK_C444TO422FILTERINGMODE_W_LEN (1U) -#define DSP2_BLBACK_C444TO422FILTERINGMODE_W_MSK (((1U << DSP2_BLBACK_C444TO422FILTERINGMODE_W_LEN) - 1) << DSP2_BLBACK_C444TO422FILTERINGMODE_W_POS) -#define DSP2_BLBACK_C444TO422FILTERINGMODE_W_UMSK (~(((1U << DSP2_BLBACK_C444TO422FILTERINGMODE_W_LEN) - 1) << DSP2_BLBACK_C444TO422FILTERINGMODE_W_POS)) -#define DSP2_BLBACK_SEPIACB_W DSP2_BLBACK_SEPIACB_W -#define DSP2_BLBACK_SEPIACB_W_POS (8U) -#define DSP2_BLBACK_SEPIACB_W_LEN (8U) -#define DSP2_BLBACK_SEPIACB_W_MSK (((1U << DSP2_BLBACK_SEPIACB_W_LEN) - 1) << DSP2_BLBACK_SEPIACB_W_POS) -#define DSP2_BLBACK_SEPIACB_W_UMSK (~(((1U << DSP2_BLBACK_SEPIACB_W_LEN) - 1) << DSP2_BLBACK_SEPIACB_W_POS)) -#define DSP2_BLBACK_SEPIACR_W DSP2_BLBACK_SEPIACR_W -#define DSP2_BLBACK_SEPIACR_W_POS (16U) -#define DSP2_BLBACK_SEPIACR_W_LEN (8U) -#define DSP2_BLBACK_SEPIACR_W_MSK (((1U << DSP2_BLBACK_SEPIACR_W_LEN) - 1) << DSP2_BLBACK_SEPIACR_W_POS) -#define DSP2_BLBACK_SEPIACR_W_UMSK (~(((1U << DSP2_BLBACK_SEPIACR_W_LEN) - 1) << DSP2_BLBACK_SEPIACR_W_POS)) -#define DSP2_BLBACK_SOLARTHRED_W DSP2_BLBACK_SOLARTHRED_W -#define DSP2_BLBACK_SOLARTHRED_W_POS (24U) -#define DSP2_BLBACK_SOLARTHRED_W_LEN (8U) -#define DSP2_BLBACK_SOLARTHRED_W_MSK (((1U << DSP2_BLBACK_SOLARTHRED_W_LEN) - 1) << DSP2_BLBACK_SOLARTHRED_W_POS) -#define DSP2_BLBACK_SOLARTHRED_W_UMSK (~(((1U << DSP2_BLBACK_SOLARTHRED_W_LEN) - 1) << DSP2_BLBACK_SOLARTHRED_W_POS)) - -/* 0x354 : DNR_A */ -#define DSP2_BLBACK_DNR_A_OFFSET (0x354) -#define DSP2_BLBACK_NOISE_LEVEL_PRE DSP2_BLBACK_NOISE_LEVEL_PRE -#define DSP2_BLBACK_NOISE_LEVEL_PRE_POS (0U) -#define DSP2_BLBACK_NOISE_LEVEL_PRE_LEN (6U) -#define DSP2_BLBACK_NOISE_LEVEL_PRE_MSK (((1U << DSP2_BLBACK_NOISE_LEVEL_PRE_LEN) - 1) << DSP2_BLBACK_NOISE_LEVEL_PRE_POS) -#define DSP2_BLBACK_NOISE_LEVEL_PRE_UMSK (~(((1U << DSP2_BLBACK_NOISE_LEVEL_PRE_LEN) - 1) << DSP2_BLBACK_NOISE_LEVEL_PRE_POS)) -#define DSP2_BLBACK_NR_HSIZE_PRE DSP2_BLBACK_NR_HSIZE_PRE -#define DSP2_BLBACK_NR_HSIZE_PRE_POS (8U) -#define DSP2_BLBACK_NR_HSIZE_PRE_LEN (16U) -#define DSP2_BLBACK_NR_HSIZE_PRE_MSK (((1U << DSP2_BLBACK_NR_HSIZE_PRE_LEN) - 1) << DSP2_BLBACK_NR_HSIZE_PRE_POS) -#define DSP2_BLBACK_NR_HSIZE_PRE_UMSK (~(((1U << DSP2_BLBACK_NR_HSIZE_PRE_LEN) - 1) << DSP2_BLBACK_NR_HSIZE_PRE_POS)) -#define DSP2_BLBACK_FILT_STRENGTH_2D_PRE DSP2_BLBACK_FILT_STRENGTH_2D_PRE -#define DSP2_BLBACK_FILT_STRENGTH_2D_PRE_POS (24U) -#define DSP2_BLBACK_FILT_STRENGTH_2D_PRE_LEN (4U) -#define DSP2_BLBACK_FILT_STRENGTH_2D_PRE_MSK (((1U << DSP2_BLBACK_FILT_STRENGTH_2D_PRE_LEN) - 1) << DSP2_BLBACK_FILT_STRENGTH_2D_PRE_POS) -#define DSP2_BLBACK_FILT_STRENGTH_2D_PRE_UMSK (~(((1U << DSP2_BLBACK_FILT_STRENGTH_2D_PRE_LEN) - 1) << DSP2_BLBACK_FILT_STRENGTH_2D_PRE_POS)) -#define DSP2_BLBACK_FILT_STRENGTH_3D_PRE DSP2_BLBACK_FILT_STRENGTH_3D_PRE -#define DSP2_BLBACK_FILT_STRENGTH_3D_PRE_POS (28U) -#define DSP2_BLBACK_FILT_STRENGTH_3D_PRE_LEN (4U) -#define DSP2_BLBACK_FILT_STRENGTH_3D_PRE_MSK (((1U << DSP2_BLBACK_FILT_STRENGTH_3D_PRE_LEN) - 1) << DSP2_BLBACK_FILT_STRENGTH_3D_PRE_POS) -#define DSP2_BLBACK_FILT_STRENGTH_3D_PRE_UMSK (~(((1U << DSP2_BLBACK_FILT_STRENGTH_3D_PRE_LEN) - 1) << DSP2_BLBACK_FILT_STRENGTH_3D_PRE_POS)) - -/* 0x358 : DNR_B */ -#define DSP2_BLBACK_DNR_B_OFFSET (0x358) -#define DSP2_BLBACK_CBCR_SELECT_W DSP2_BLBACK_CBCR_SELECT_W -#define DSP2_BLBACK_CBCR_SELECT_W_POS (8U) -#define DSP2_BLBACK_CBCR_SELECT_W_LEN (1U) -#define DSP2_BLBACK_CBCR_SELECT_W_MSK (((1U << DSP2_BLBACK_CBCR_SELECT_W_LEN) - 1) << DSP2_BLBACK_CBCR_SELECT_W_POS) -#define DSP2_BLBACK_CBCR_SELECT_W_UMSK (~(((1U << DSP2_BLBACK_CBCR_SELECT_W_LEN) - 1) << DSP2_BLBACK_CBCR_SELECT_W_POS)) -#define DSP2_BLBACK_OUT_FORMAT_W DSP2_BLBACK_OUT_FORMAT_W -#define DSP2_BLBACK_OUT_FORMAT_W_POS (9U) -#define DSP2_BLBACK_OUT_FORMAT_W_LEN (2U) -#define DSP2_BLBACK_OUT_FORMAT_W_MSK (((1U << DSP2_BLBACK_OUT_FORMAT_W_LEN) - 1) << DSP2_BLBACK_OUT_FORMAT_W_POS) -#define DSP2_BLBACK_OUT_FORMAT_W_UMSK (~(((1U << DSP2_BLBACK_OUT_FORMAT_W_LEN) - 1) << DSP2_BLBACK_OUT_FORMAT_W_POS)) - -/* 0x360 : BLEE_0 */ -#define DSP2_BLBACK_BLEE_0_OFFSET (0x360) -#define DSP2_BLBACK_EE_EB_PRE DSP2_BLBACK_EE_EB_PRE -#define DSP2_BLBACK_EE_EB_PRE_POS (0U) -#define DSP2_BLBACK_EE_EB_PRE_LEN (1U) -#define DSP2_BLBACK_EE_EB_PRE_MSK (((1U << DSP2_BLBACK_EE_EB_PRE_LEN) - 1) << DSP2_BLBACK_EE_EB_PRE_POS) -#define DSP2_BLBACK_EE_EB_PRE_UMSK (~(((1U << DSP2_BLBACK_EE_EB_PRE_LEN) - 1) << DSP2_BLBACK_EE_EB_PRE_POS)) -#define DSP2_BLBACK_OVRSHT_EB_PRE DSP2_BLBACK_OVRSHT_EB_PRE -#define DSP2_BLBACK_OVRSHT_EB_PRE_POS (1U) -#define DSP2_BLBACK_OVRSHT_EB_PRE_LEN (1U) -#define DSP2_BLBACK_OVRSHT_EB_PRE_MSK (((1U << DSP2_BLBACK_OVRSHT_EB_PRE_LEN) - 1) << DSP2_BLBACK_OVRSHT_EB_PRE_POS) -#define DSP2_BLBACK_OVRSHT_EB_PRE_UMSK (~(((1U << DSP2_BLBACK_OVRSHT_EB_PRE_LEN) - 1) << DSP2_BLBACK_OVRSHT_EB_PRE_POS)) -#define DSP2_BLBACK_TXT_THR_PRE DSP2_BLBACK_TXT_THR_PRE -#define DSP2_BLBACK_TXT_THR_PRE_POS (16U) -#define DSP2_BLBACK_TXT_THR_PRE_LEN (9U) -#define DSP2_BLBACK_TXT_THR_PRE_MSK (((1U << DSP2_BLBACK_TXT_THR_PRE_LEN) - 1) << DSP2_BLBACK_TXT_THR_PRE_POS) -#define DSP2_BLBACK_TXT_THR_PRE_UMSK (~(((1U << DSP2_BLBACK_TXT_THR_PRE_LEN) - 1) << DSP2_BLBACK_TXT_THR_PRE_POS)) - -/* 0x364 : BLEE_1 */ -#define DSP2_BLBACK_BLEE_1_OFFSET (0x364) -#define DSP2_BLBACK_THRESH1_PRE DSP2_BLBACK_THRESH1_PRE -#define DSP2_BLBACK_THRESH1_PRE_POS (0U) -#define DSP2_BLBACK_THRESH1_PRE_LEN (7U) -#define DSP2_BLBACK_THRESH1_PRE_MSK (((1U << DSP2_BLBACK_THRESH1_PRE_LEN) - 1) << DSP2_BLBACK_THRESH1_PRE_POS) -#define DSP2_BLBACK_THRESH1_PRE_UMSK (~(((1U << DSP2_BLBACK_THRESH1_PRE_LEN) - 1) << DSP2_BLBACK_THRESH1_PRE_POS)) -#define DSP2_BLBACK_THRESH2_PRE DSP2_BLBACK_THRESH2_PRE -#define DSP2_BLBACK_THRESH2_PRE_POS (8U) -#define DSP2_BLBACK_THRESH2_PRE_LEN (7U) -#define DSP2_BLBACK_THRESH2_PRE_MSK (((1U << DSP2_BLBACK_THRESH2_PRE_LEN) - 1) << DSP2_BLBACK_THRESH2_PRE_POS) -#define DSP2_BLBACK_THRESH2_PRE_UMSK (~(((1U << DSP2_BLBACK_THRESH2_PRE_LEN) - 1) << DSP2_BLBACK_THRESH2_PRE_POS)) -#define DSP2_BLBACK_FLAT_THR_PRE DSP2_BLBACK_FLAT_THR_PRE -#define DSP2_BLBACK_FLAT_THR_PRE_POS (16U) -#define DSP2_BLBACK_FLAT_THR_PRE_LEN (8U) -#define DSP2_BLBACK_FLAT_THR_PRE_MSK (((1U << DSP2_BLBACK_FLAT_THR_PRE_LEN) - 1) << DSP2_BLBACK_FLAT_THR_PRE_POS) -#define DSP2_BLBACK_FLAT_THR_PRE_UMSK (~(((1U << DSP2_BLBACK_FLAT_THR_PRE_LEN) - 1) << DSP2_BLBACK_FLAT_THR_PRE_POS)) - -/* 0x368 : BLEE_2 */ -#define DSP2_BLBACK_BLEE_2_OFFSET (0x368) -#define DSP2_BLBACK_OVRSHT_POS_PRE DSP2_BLBACK_OVRSHT_POS_PRE -#define DSP2_BLBACK_OVRSHT_POS_PRE_POS (0U) -#define DSP2_BLBACK_OVRSHT_POS_PRE_LEN (7U) -#define DSP2_BLBACK_OVRSHT_POS_PRE_MSK (((1U << DSP2_BLBACK_OVRSHT_POS_PRE_LEN) - 1) << DSP2_BLBACK_OVRSHT_POS_PRE_POS) -#define DSP2_BLBACK_OVRSHT_POS_PRE_UMSK (~(((1U << DSP2_BLBACK_OVRSHT_POS_PRE_LEN) - 1) << DSP2_BLBACK_OVRSHT_POS_PRE_POS)) -#define DSP2_BLBACK_OVRSHT_NEG_PRE DSP2_BLBACK_OVRSHT_NEG_PRE -#define DSP2_BLBACK_OVRSHT_NEG_PRE_POS (8U) -#define DSP2_BLBACK_OVRSHT_NEG_PRE_LEN (7U) -#define DSP2_BLBACK_OVRSHT_NEG_PRE_MSK (((1U << DSP2_BLBACK_OVRSHT_NEG_PRE_LEN) - 1) << DSP2_BLBACK_OVRSHT_NEG_PRE_POS) -#define DSP2_BLBACK_OVRSHT_NEG_PRE_UMSK (~(((1U << DSP2_BLBACK_OVRSHT_NEG_PRE_LEN) - 1) << DSP2_BLBACK_OVRSHT_NEG_PRE_POS)) -#define DSP2_BLBACK_POSEE_STR_PRE DSP2_BLBACK_POSEE_STR_PRE -#define DSP2_BLBACK_POSEE_STR_PRE_POS (16U) -#define DSP2_BLBACK_POSEE_STR_PRE_LEN (7U) -#define DSP2_BLBACK_POSEE_STR_PRE_MSK (((1U << DSP2_BLBACK_POSEE_STR_PRE_LEN) - 1) << DSP2_BLBACK_POSEE_STR_PRE_POS) -#define DSP2_BLBACK_POSEE_STR_PRE_UMSK (~(((1U << DSP2_BLBACK_POSEE_STR_PRE_LEN) - 1) << DSP2_BLBACK_POSEE_STR_PRE_POS)) -#define DSP2_BLBACK_NEGEE_STR_PRE DSP2_BLBACK_NEGEE_STR_PRE -#define DSP2_BLBACK_NEGEE_STR_PRE_POS (24U) -#define DSP2_BLBACK_NEGEE_STR_PRE_LEN (7U) -#define DSP2_BLBACK_NEGEE_STR_PRE_MSK (((1U << DSP2_BLBACK_NEGEE_STR_PRE_LEN) - 1) << DSP2_BLBACK_NEGEE_STR_PRE_POS) -#define DSP2_BLBACK_NEGEE_STR_PRE_UMSK (~(((1U << DSP2_BLBACK_NEGEE_STR_PRE_LEN) - 1) << DSP2_BLBACK_NEGEE_STR_PRE_POS)) - -/* 0x36C : BLEE_3 */ -#define DSP2_BLBACK_BLEE_3_OFFSET (0x36C) -#define DSP2_BLBACK_EDGE_THR_PRE DSP2_BLBACK_EDGE_THR_PRE -#define DSP2_BLBACK_EDGE_THR_PRE_POS (0U) -#define DSP2_BLBACK_EDGE_THR_PRE_LEN (16U) -#define DSP2_BLBACK_EDGE_THR_PRE_MSK (((1U << DSP2_BLBACK_EDGE_THR_PRE_LEN) - 1) << DSP2_BLBACK_EDGE_THR_PRE_POS) -#define DSP2_BLBACK_EDGE_THR_PRE_UMSK (~(((1U << DSP2_BLBACK_EDGE_THR_PRE_LEN) - 1) << DSP2_BLBACK_EDGE_THR_PRE_POS)) -#define DSP2_BLBACK_NR_STR_PRE DSP2_BLBACK_NR_STR_PRE -#define DSP2_BLBACK_NR_STR_PRE_POS (16U) -#define DSP2_BLBACK_NR_STR_PRE_LEN (8U) -#define DSP2_BLBACK_NR_STR_PRE_MSK (((1U << DSP2_BLBACK_NR_STR_PRE_LEN) - 1) << DSP2_BLBACK_NR_STR_PRE_POS) -#define DSP2_BLBACK_NR_STR_PRE_UMSK (~(((1U << DSP2_BLBACK_NR_STR_PRE_LEN) - 1) << DSP2_BLBACK_NR_STR_PRE_POS)) - -/* 0x370 : BLEE_4 */ -#define DSP2_BLBACK_BLEE_4_OFFSET (0x370) -#define DSP2_BLBACK_LUMA_WGT0_PRE DSP2_BLBACK_LUMA_WGT0_PRE -#define DSP2_BLBACK_LUMA_WGT0_PRE_POS (0U) -#define DSP2_BLBACK_LUMA_WGT0_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT0_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT0_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT0_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT0_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT0_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT0_PRE_POS)) -#define DSP2_BLBACK_LUMA_WGT1_PRE DSP2_BLBACK_LUMA_WGT1_PRE -#define DSP2_BLBACK_LUMA_WGT1_PRE_POS (16U) -#define DSP2_BLBACK_LUMA_WGT1_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT1_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT1_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT1_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT1_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT1_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT1_PRE_POS)) - -/* 0x374 : BLEE_5 */ -#define DSP2_BLBACK_BLEE_5_OFFSET (0x374) -#define DSP2_BLBACK_LUMA_WGT2_PRE DSP2_BLBACK_LUMA_WGT2_PRE -#define DSP2_BLBACK_LUMA_WGT2_PRE_POS (0U) -#define DSP2_BLBACK_LUMA_WGT2_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT2_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT2_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT2_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT2_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT2_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT2_PRE_POS)) -#define DSP2_BLBACK_LUMA_WGT3_PRE DSP2_BLBACK_LUMA_WGT3_PRE -#define DSP2_BLBACK_LUMA_WGT3_PRE_POS (16U) -#define DSP2_BLBACK_LUMA_WGT3_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT3_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT3_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT3_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT3_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT3_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT3_PRE_POS)) - -/* 0x378 : BLEE_6 */ -#define DSP2_BLBACK_BLEE_6_OFFSET (0x378) -#define DSP2_BLBACK_LUMA_WGT4_PRE DSP2_BLBACK_LUMA_WGT4_PRE -#define DSP2_BLBACK_LUMA_WGT4_PRE_POS (0U) -#define DSP2_BLBACK_LUMA_WGT4_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT4_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT4_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT4_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT4_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT4_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT4_PRE_POS)) -#define DSP2_BLBACK_LUMA_WGT5_PRE DSP2_BLBACK_LUMA_WGT5_PRE -#define DSP2_BLBACK_LUMA_WGT5_PRE_POS (16U) -#define DSP2_BLBACK_LUMA_WGT5_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT5_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT5_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT5_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT5_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT5_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT5_PRE_POS)) - -/* 0x37C : BLEE_7 */ -#define DSP2_BLBACK_BLEE_7_OFFSET (0x37C) -#define DSP2_BLBACK_LUMA_WGT6_PRE DSP2_BLBACK_LUMA_WGT6_PRE -#define DSP2_BLBACK_LUMA_WGT6_PRE_POS (0U) -#define DSP2_BLBACK_LUMA_WGT6_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT6_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT6_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT6_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT6_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT6_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT6_PRE_POS)) -#define DSP2_BLBACK_LUMA_WGT7_PRE DSP2_BLBACK_LUMA_WGT7_PRE -#define DSP2_BLBACK_LUMA_WGT7_PRE_POS (16U) -#define DSP2_BLBACK_LUMA_WGT7_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT7_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT7_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT7_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT7_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT7_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT7_PRE_POS)) - -/* 0x380 : BLEE_8 */ -#define DSP2_BLBACK_BLEE_8_OFFSET (0x380) -#define DSP2_BLBACK_LUMA_WGT8_PRE DSP2_BLBACK_LUMA_WGT8_PRE -#define DSP2_BLBACK_LUMA_WGT8_PRE_POS (0U) -#define DSP2_BLBACK_LUMA_WGT8_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT8_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT8_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT8_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT8_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT8_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT8_PRE_POS)) -#define DSP2_BLBACK_LUMA_WGT9_PRE DSP2_BLBACK_LUMA_WGT9_PRE -#define DSP2_BLBACK_LUMA_WGT9_PRE_POS (16U) -#define DSP2_BLBACK_LUMA_WGT9_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT9_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT9_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT9_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT9_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT9_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT9_PRE_POS)) - -/* 0x384 : BLEE_9 */ -#define DSP2_BLBACK_BLEE_9_OFFSET (0x384) -#define DSP2_BLBACK_LUMA_WGT10_PRE DSP2_BLBACK_LUMA_WGT10_PRE -#define DSP2_BLBACK_LUMA_WGT10_PRE_POS (0U) -#define DSP2_BLBACK_LUMA_WGT10_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT10_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT10_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT10_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT10_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT10_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT10_PRE_POS)) -#define DSP2_BLBACK_LUMA_WGT11_PRE DSP2_BLBACK_LUMA_WGT11_PRE -#define DSP2_BLBACK_LUMA_WGT11_PRE_POS (16U) -#define DSP2_BLBACK_LUMA_WGT11_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT11_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT11_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT11_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT11_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT11_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT11_PRE_POS)) - -/* 0x388 : BLEE_A */ -#define DSP2_BLBACK_BLEE_A_OFFSET (0x388) -#define DSP2_BLBACK_LUMA_WGT12_PRE DSP2_BLBACK_LUMA_WGT12_PRE -#define DSP2_BLBACK_LUMA_WGT12_PRE_POS (0U) -#define DSP2_BLBACK_LUMA_WGT12_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT12_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT12_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT12_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT12_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT12_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT12_PRE_POS)) -#define DSP2_BLBACK_LUMA_WGT13_PRE DSP2_BLBACK_LUMA_WGT13_PRE -#define DSP2_BLBACK_LUMA_WGT13_PRE_POS (16U) -#define DSP2_BLBACK_LUMA_WGT13_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT13_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT13_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT13_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT13_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT13_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT13_PRE_POS)) - -/* 0x38C : BLEE_B */ -#define DSP2_BLBACK_BLEE_B_OFFSET (0x38C) -#define DSP2_BLBACK_LUMA_WGT14_PRE DSP2_BLBACK_LUMA_WGT14_PRE -#define DSP2_BLBACK_LUMA_WGT14_PRE_POS (0U) -#define DSP2_BLBACK_LUMA_WGT14_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT14_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT14_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT14_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT14_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT14_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT14_PRE_POS)) -#define DSP2_BLBACK_LUMA_WGT15_PRE DSP2_BLBACK_LUMA_WGT15_PRE -#define DSP2_BLBACK_LUMA_WGT15_PRE_POS (16U) -#define DSP2_BLBACK_LUMA_WGT15_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT15_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT15_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT15_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT15_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT15_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT15_PRE_POS)) - -/* 0x390 : BLEE_C */ -#define DSP2_BLBACK_BLEE_C_OFFSET (0x390) -#define DSP2_BLBACK_LUMA_WGT16_PRE DSP2_BLBACK_LUMA_WGT16_PRE -#define DSP2_BLBACK_LUMA_WGT16_PRE_POS (0U) -#define DSP2_BLBACK_LUMA_WGT16_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT16_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT16_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT16_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT16_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT16_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT16_PRE_POS)) -#define DSP2_BLBACK_LUMA_WGT17_PRE DSP2_BLBACK_LUMA_WGT17_PRE -#define DSP2_BLBACK_LUMA_WGT17_PRE_POS (16U) -#define DSP2_BLBACK_LUMA_WGT17_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT17_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT17_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT17_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT17_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT17_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT17_PRE_POS)) - -/* 0x394 : BLEE_D */ -#define DSP2_BLBACK_BLEE_D_OFFSET (0x394) -#define DSP2_BLBACK_LUMA_WGT18_PRE DSP2_BLBACK_LUMA_WGT18_PRE -#define DSP2_BLBACK_LUMA_WGT18_PRE_POS (0U) -#define DSP2_BLBACK_LUMA_WGT18_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT18_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT18_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT18_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT18_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT18_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT18_PRE_POS)) -#define DSP2_BLBACK_LUMA_WGT19_PRE DSP2_BLBACK_LUMA_WGT19_PRE -#define DSP2_BLBACK_LUMA_WGT19_PRE_POS (16U) -#define DSP2_BLBACK_LUMA_WGT19_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT19_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT19_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT19_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT19_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT19_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT19_PRE_POS)) - -/* 0x398 : BLEE_E */ -#define DSP2_BLBACK_BLEE_E_OFFSET (0x398) -#define DSP2_BLBACK_LUMA_WGT20_PRE DSP2_BLBACK_LUMA_WGT20_PRE -#define DSP2_BLBACK_LUMA_WGT20_PRE_POS (0U) -#define DSP2_BLBACK_LUMA_WGT20_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT20_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT20_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT20_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT20_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT20_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT20_PRE_POS)) -#define DSP2_BLBACK_LUMA_WGT21_PRE DSP2_BLBACK_LUMA_WGT21_PRE -#define DSP2_BLBACK_LUMA_WGT21_PRE_POS (16U) -#define DSP2_BLBACK_LUMA_WGT21_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT21_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT21_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT21_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT21_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT21_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT21_PRE_POS)) - -/* 0x39C : BLEE_F */ -#define DSP2_BLBACK_BLEE_F_OFFSET (0x39C) -#define DSP2_BLBACK_LUMA_WGT22_PRE DSP2_BLBACK_LUMA_WGT22_PRE -#define DSP2_BLBACK_LUMA_WGT22_PRE_POS (0U) -#define DSP2_BLBACK_LUMA_WGT22_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT22_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT22_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT22_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT22_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT22_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT22_PRE_POS)) -#define DSP2_BLBACK_LUMA_WGT23_PRE DSP2_BLBACK_LUMA_WGT23_PRE -#define DSP2_BLBACK_LUMA_WGT23_PRE_POS (16U) -#define DSP2_BLBACK_LUMA_WGT23_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT23_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT23_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT23_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT23_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT23_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT23_PRE_POS)) - -/* 0x3A0 : BLEE_10 */ -#define DSP2_BLBACK_BLEE_10_OFFSET (0x3A0) -#define DSP2_BLBACK_LUMA_WGT24_PRE DSP2_BLBACK_LUMA_WGT24_PRE -#define DSP2_BLBACK_LUMA_WGT24_PRE_POS (0U) -#define DSP2_BLBACK_LUMA_WGT24_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT24_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT24_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT24_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT24_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT24_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT24_PRE_POS)) -#define DSP2_BLBACK_LUMA_WGT25_PRE DSP2_BLBACK_LUMA_WGT25_PRE -#define DSP2_BLBACK_LUMA_WGT25_PRE_POS (16U) -#define DSP2_BLBACK_LUMA_WGT25_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT25_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT25_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT25_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT25_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT25_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT25_PRE_POS)) - -/* 0x3A4 : BLEE_11 */ -#define DSP2_BLBACK_BLEE_11_OFFSET (0x3A4) -#define DSP2_BLBACK_LUMA_WGT26_PRE DSP2_BLBACK_LUMA_WGT26_PRE -#define DSP2_BLBACK_LUMA_WGT26_PRE_POS (0U) -#define DSP2_BLBACK_LUMA_WGT26_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT26_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT26_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT26_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT26_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT26_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT26_PRE_POS)) -#define DSP2_BLBACK_LUMA_WGT27_PRE DSP2_BLBACK_LUMA_WGT27_PRE -#define DSP2_BLBACK_LUMA_WGT27_PRE_POS (16U) -#define DSP2_BLBACK_LUMA_WGT27_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT27_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT27_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT27_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT27_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT27_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT27_PRE_POS)) - -/* 0x3A8 : BLEE_12 */ -#define DSP2_BLBACK_BLEE_12_OFFSET (0x3A8) -#define DSP2_BLBACK_LUMA_WGT28_PRE DSP2_BLBACK_LUMA_WGT28_PRE -#define DSP2_BLBACK_LUMA_WGT28_PRE_POS (0U) -#define DSP2_BLBACK_LUMA_WGT28_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT28_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT28_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT28_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT28_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT28_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT28_PRE_POS)) -#define DSP2_BLBACK_LUMA_WGT29_PRE DSP2_BLBACK_LUMA_WGT29_PRE -#define DSP2_BLBACK_LUMA_WGT29_PRE_POS (16U) -#define DSP2_BLBACK_LUMA_WGT29_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT29_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT29_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT29_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT29_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT29_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT29_PRE_POS)) - -/* 0x3AC : BLEE_13 */ -#define DSP2_BLBACK_BLEE_13_OFFSET (0x3AC) -#define DSP2_BLBACK_LUMA_WGT30_PRE DSP2_BLBACK_LUMA_WGT30_PRE -#define DSP2_BLBACK_LUMA_WGT30_PRE_POS (0U) -#define DSP2_BLBACK_LUMA_WGT30_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT30_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT30_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT30_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT30_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT30_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT30_PRE_POS)) -#define DSP2_BLBACK_LUMA_WGT31_PRE DSP2_BLBACK_LUMA_WGT31_PRE -#define DSP2_BLBACK_LUMA_WGT31_PRE_POS (16U) -#define DSP2_BLBACK_LUMA_WGT31_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT31_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT31_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT31_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT31_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT31_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT31_PRE_POS)) - -/* 0x3B0 : CS1 */ -#define DSP2_BLBACK_CS1_OFFSET (0x3B0) -#define DSP2_BLBACK_CS1_GREY_TH_PRE DSP2_BLBACK_CS1_GREY_TH_PRE -#define DSP2_BLBACK_CS1_GREY_TH_PRE_POS (0U) -#define DSP2_BLBACK_CS1_GREY_TH_PRE_LEN (4U) -#define DSP2_BLBACK_CS1_GREY_TH_PRE_MSK (((1U << DSP2_BLBACK_CS1_GREY_TH_PRE_LEN) - 1) << DSP2_BLBACK_CS1_GREY_TH_PRE_POS) -#define DSP2_BLBACK_CS1_GREY_TH_PRE_UMSK (~(((1U << DSP2_BLBACK_CS1_GREY_TH_PRE_LEN) - 1) << DSP2_BLBACK_CS1_GREY_TH_PRE_POS)) -#define DSP2_BLBACK_CS1_ENABLE_PRE DSP2_BLBACK_CS1_ENABLE_PRE -#define DSP2_BLBACK_CS1_ENABLE_PRE_POS (4U) -#define DSP2_BLBACK_CS1_ENABLE_PRE_LEN (1U) -#define DSP2_BLBACK_CS1_ENABLE_PRE_MSK (((1U << DSP2_BLBACK_CS1_ENABLE_PRE_LEN) - 1) << DSP2_BLBACK_CS1_ENABLE_PRE_POS) -#define DSP2_BLBACK_CS1_ENABLE_PRE_UMSK (~(((1U << DSP2_BLBACK_CS1_ENABLE_PRE_LEN) - 1) << DSP2_BLBACK_CS1_ENABLE_PRE_POS)) -#define DSP2_BLBACK_CS1_WEIGHT_PRE DSP2_BLBACK_CS1_WEIGHT_PRE -#define DSP2_BLBACK_CS1_WEIGHT_PRE_POS (8U) -#define DSP2_BLBACK_CS1_WEIGHT_PRE_LEN (5U) -#define DSP2_BLBACK_CS1_WEIGHT_PRE_MSK (((1U << DSP2_BLBACK_CS1_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_CS1_WEIGHT_PRE_POS) -#define DSP2_BLBACK_CS1_WEIGHT_PRE_UMSK (~(((1U << DSP2_BLBACK_CS1_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_CS1_WEIGHT_PRE_POS)) -#define DSP2_BLBACK_CS1_GAIN_PRE DSP2_BLBACK_CS1_GAIN_PRE -#define DSP2_BLBACK_CS1_GAIN_PRE_POS (16U) -#define DSP2_BLBACK_CS1_GAIN_PRE_LEN (9U) -#define DSP2_BLBACK_CS1_GAIN_PRE_MSK (((1U << DSP2_BLBACK_CS1_GAIN_PRE_LEN) - 1) << DSP2_BLBACK_CS1_GAIN_PRE_POS) -#define DSP2_BLBACK_CS1_GAIN_PRE_UMSK (~(((1U << DSP2_BLBACK_CS1_GAIN_PRE_LEN) - 1) << DSP2_BLBACK_CS1_GAIN_PRE_POS)) - -/* 0x3B4 : CS2 */ -#define DSP2_BLBACK_CS2_OFFSET (0x3B4) -#define DSP2_BLBACK_CS2_GREY_TH_PRE DSP2_BLBACK_CS2_GREY_TH_PRE -#define DSP2_BLBACK_CS2_GREY_TH_PRE_POS (0U) -#define DSP2_BLBACK_CS2_GREY_TH_PRE_LEN (4U) -#define DSP2_BLBACK_CS2_GREY_TH_PRE_MSK (((1U << DSP2_BLBACK_CS2_GREY_TH_PRE_LEN) - 1) << DSP2_BLBACK_CS2_GREY_TH_PRE_POS) -#define DSP2_BLBACK_CS2_GREY_TH_PRE_UMSK (~(((1U << DSP2_BLBACK_CS2_GREY_TH_PRE_LEN) - 1) << DSP2_BLBACK_CS2_GREY_TH_PRE_POS)) -#define DSP2_BLBACK_CS2_ENABLE_PRE DSP2_BLBACK_CS2_ENABLE_PRE -#define DSP2_BLBACK_CS2_ENABLE_PRE_POS (4U) -#define DSP2_BLBACK_CS2_ENABLE_PRE_LEN (1U) -#define DSP2_BLBACK_CS2_ENABLE_PRE_MSK (((1U << DSP2_BLBACK_CS2_ENABLE_PRE_LEN) - 1) << DSP2_BLBACK_CS2_ENABLE_PRE_POS) -#define DSP2_BLBACK_CS2_ENABLE_PRE_UMSK (~(((1U << DSP2_BLBACK_CS2_ENABLE_PRE_LEN) - 1) << DSP2_BLBACK_CS2_ENABLE_PRE_POS)) -#define DSP2_BLBACK_CS2_WEIGHT_PRE DSP2_BLBACK_CS2_WEIGHT_PRE -#define DSP2_BLBACK_CS2_WEIGHT_PRE_POS (8U) -#define DSP2_BLBACK_CS2_WEIGHT_PRE_LEN (5U) -#define DSP2_BLBACK_CS2_WEIGHT_PRE_MSK (((1U << DSP2_BLBACK_CS2_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_CS2_WEIGHT_PRE_POS) -#define DSP2_BLBACK_CS2_WEIGHT_PRE_UMSK (~(((1U << DSP2_BLBACK_CS2_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_CS2_WEIGHT_PRE_POS)) -#define DSP2_BLBACK_CS2_GAIN_PRE DSP2_BLBACK_CS2_GAIN_PRE -#define DSP2_BLBACK_CS2_GAIN_PRE_POS (16U) -#define DSP2_BLBACK_CS2_GAIN_PRE_LEN (9U) -#define DSP2_BLBACK_CS2_GAIN_PRE_MSK (((1U << DSP2_BLBACK_CS2_GAIN_PRE_LEN) - 1) << DSP2_BLBACK_CS2_GAIN_PRE_POS) -#define DSP2_BLBACK_CS2_GAIN_PRE_UMSK (~(((1U << DSP2_BLBACK_CS2_GAIN_PRE_LEN) - 1) << DSP2_BLBACK_CS2_GAIN_PRE_POS)) - -/* 0x3FC : DUMMY_CTRL */ -#define DSP2_BLBACK_DUMMY_CTRL_OFFSET (0x3FC) -#define DSP2_BLBACK_REG_BL444TO422_EN_W DSP2_BLBACK_REG_BL444TO422_EN_W -#define DSP2_BLBACK_REG_BL444TO422_EN_W_POS (0U) -#define DSP2_BLBACK_REG_BL444TO422_EN_W_LEN (1U) -#define DSP2_BLBACK_REG_BL444TO422_EN_W_MSK (((1U << DSP2_BLBACK_REG_BL444TO422_EN_W_LEN) - 1) << DSP2_BLBACK_REG_BL444TO422_EN_W_POS) -#define DSP2_BLBACK_REG_BL444TO422_EN_W_UMSK (~(((1U << DSP2_BLBACK_REG_BL444TO422_EN_W_LEN) - 1) << DSP2_BLBACK_REG_BL444TO422_EN_W_POS)) - -/* 0x900 : WDR_0 */ -#define DSP2_BLBACK_WDR_0_OFFSET (0x900) -#define DSP2_BLBACK_WDR_EN_PRE DSP2_BLBACK_WDR_EN_PRE -#define DSP2_BLBACK_WDR_EN_PRE_POS (0U) -#define DSP2_BLBACK_WDR_EN_PRE_LEN (1U) -#define DSP2_BLBACK_WDR_EN_PRE_MSK (((1U << DSP2_BLBACK_WDR_EN_PRE_LEN) - 1) << DSP2_BLBACK_WDR_EN_PRE_POS) -#define DSP2_BLBACK_WDR_EN_PRE_UMSK (~(((1U << DSP2_BLBACK_WDR_EN_PRE_LEN) - 1) << DSP2_BLBACK_WDR_EN_PRE_POS)) -#define DSP2_BLBACK_BLWDR_BUF_IDX_R DSP2_BLBACK_BLWDR_BUF_IDX_R -#define DSP2_BLBACK_BLWDR_BUF_IDX_R_POS (1U) -#define DSP2_BLBACK_BLWDR_BUF_IDX_R_LEN (1U) -#define DSP2_BLBACK_BLWDR_BUF_IDX_R_MSK (((1U << DSP2_BLBACK_BLWDR_BUF_IDX_R_LEN) - 1) << DSP2_BLBACK_BLWDR_BUF_IDX_R_POS) -#define DSP2_BLBACK_BLWDR_BUF_IDX_R_UMSK (~(((1U << DSP2_BLBACK_BLWDR_BUF_IDX_R_LEN) - 1) << DSP2_BLBACK_BLWDR_BUF_IDX_R_POS)) -#define DSP2_BLBACK_BLWDR_W_CNT_R DSP2_BLBACK_BLWDR_W_CNT_R -#define DSP2_BLBACK_BLWDR_W_CNT_R_POS (4U) -#define DSP2_BLBACK_BLWDR_W_CNT_R_LEN (5U) -#define DSP2_BLBACK_BLWDR_W_CNT_R_MSK (((1U << DSP2_BLBACK_BLWDR_W_CNT_R_LEN) - 1) << DSP2_BLBACK_BLWDR_W_CNT_R_POS) -#define DSP2_BLBACK_BLWDR_W_CNT_R_UMSK (~(((1U << DSP2_BLBACK_BLWDR_W_CNT_R_LEN) - 1) << DSP2_BLBACK_BLWDR_W_CNT_R_POS)) -#define DSP2_BLBACK_WDR_CS_GAIN_PRE DSP2_BLBACK_WDR_CS_GAIN_PRE -#define DSP2_BLBACK_WDR_CS_GAIN_PRE_POS (16U) -#define DSP2_BLBACK_WDR_CS_GAIN_PRE_LEN (13U) -#define DSP2_BLBACK_WDR_CS_GAIN_PRE_MSK (((1U << DSP2_BLBACK_WDR_CS_GAIN_PRE_LEN) - 1) << DSP2_BLBACK_WDR_CS_GAIN_PRE_POS) -#define DSP2_BLBACK_WDR_CS_GAIN_PRE_UMSK (~(((1U << DSP2_BLBACK_WDR_CS_GAIN_PRE_LEN) - 1) << DSP2_BLBACK_WDR_CS_GAIN_PRE_POS)) - -/* 0x904 : WDR_CS_0 */ -#define DSP2_BLBACK_WDR_CS_0_OFFSET (0x904) -#define DSP2_BLBACK_WDR_CS_EN_PRE DSP2_BLBACK_WDR_CS_EN_PRE -#define DSP2_BLBACK_WDR_CS_EN_PRE_POS (0U) -#define DSP2_BLBACK_WDR_CS_EN_PRE_LEN (1U) -#define DSP2_BLBACK_WDR_CS_EN_PRE_MSK (((1U << DSP2_BLBACK_WDR_CS_EN_PRE_LEN) - 1) << DSP2_BLBACK_WDR_CS_EN_PRE_POS) -#define DSP2_BLBACK_WDR_CS_EN_PRE_UMSK (~(((1U << DSP2_BLBACK_WDR_CS_EN_PRE_LEN) - 1) << DSP2_BLBACK_WDR_CS_EN_PRE_POS)) -#define DSP2_BLBACK_WDR_CS_WEIGHT_PRE DSP2_BLBACK_WDR_CS_WEIGHT_PRE -#define DSP2_BLBACK_WDR_CS_WEIGHT_PRE_POS (8U) -#define DSP2_BLBACK_WDR_CS_WEIGHT_PRE_LEN (5U) -#define DSP2_BLBACK_WDR_CS_WEIGHT_PRE_MSK (((1U << DSP2_BLBACK_WDR_CS_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_WDR_CS_WEIGHT_PRE_POS) -#define DSP2_BLBACK_WDR_CS_WEIGHT_PRE_UMSK (~(((1U << DSP2_BLBACK_WDR_CS_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_WDR_CS_WEIGHT_PRE_POS)) -#define DSP2_BLBACK_WDR_CS_GREY_TH_PRE DSP2_BLBACK_WDR_CS_GREY_TH_PRE -#define DSP2_BLBACK_WDR_CS_GREY_TH_PRE_POS (16U) -#define DSP2_BLBACK_WDR_CS_GREY_TH_PRE_LEN (8U) -#define DSP2_BLBACK_WDR_CS_GREY_TH_PRE_MSK (((1U << DSP2_BLBACK_WDR_CS_GREY_TH_PRE_LEN) - 1) << DSP2_BLBACK_WDR_CS_GREY_TH_PRE_POS) -#define DSP2_BLBACK_WDR_CS_GREY_TH_PRE_UMSK (~(((1U << DSP2_BLBACK_WDR_CS_GREY_TH_PRE_LEN) - 1) << DSP2_BLBACK_WDR_CS_GREY_TH_PRE_POS)) - -/* 0x908 : WDR_HIST_1 */ -#define DSP2_BLBACK_WDR_HIST_1_OFFSET (0x908) -#define DSP2_BLBACK_HIST_ROI0_EN_PRE DSP2_BLBACK_HIST_ROI0_EN_PRE -#define DSP2_BLBACK_HIST_ROI0_EN_PRE_POS (0U) -#define DSP2_BLBACK_HIST_ROI0_EN_PRE_LEN (1U) -#define DSP2_BLBACK_HIST_ROI0_EN_PRE_MSK (((1U << DSP2_BLBACK_HIST_ROI0_EN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI0_EN_PRE_POS) -#define DSP2_BLBACK_HIST_ROI0_EN_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_ROI0_EN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI0_EN_PRE_POS)) -#define DSP2_BLBACK_HIST_ROI0_WEIGHT_PRE DSP2_BLBACK_HIST_ROI0_WEIGHT_PRE -#define DSP2_BLBACK_HIST_ROI0_WEIGHT_PRE_POS (8U) -#define DSP2_BLBACK_HIST_ROI0_WEIGHT_PRE_LEN (4U) -#define DSP2_BLBACK_HIST_ROI0_WEIGHT_PRE_MSK (((1U << DSP2_BLBACK_HIST_ROI0_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI0_WEIGHT_PRE_POS) -#define DSP2_BLBACK_HIST_ROI0_WEIGHT_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_ROI0_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI0_WEIGHT_PRE_POS)) -#define DSP2_BLBACK_HIST_ROI1_EN_PRE DSP2_BLBACK_HIST_ROI1_EN_PRE -#define DSP2_BLBACK_HIST_ROI1_EN_PRE_POS (16U) -#define DSP2_BLBACK_HIST_ROI1_EN_PRE_LEN (1U) -#define DSP2_BLBACK_HIST_ROI1_EN_PRE_MSK (((1U << DSP2_BLBACK_HIST_ROI1_EN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI1_EN_PRE_POS) -#define DSP2_BLBACK_HIST_ROI1_EN_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_ROI1_EN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI1_EN_PRE_POS)) -#define DSP2_BLBACK_HIST_ROI1_WEIGHT_PRE DSP2_BLBACK_HIST_ROI1_WEIGHT_PRE -#define DSP2_BLBACK_HIST_ROI1_WEIGHT_PRE_POS (24U) -#define DSP2_BLBACK_HIST_ROI1_WEIGHT_PRE_LEN (4U) -#define DSP2_BLBACK_HIST_ROI1_WEIGHT_PRE_MSK (((1U << DSP2_BLBACK_HIST_ROI1_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI1_WEIGHT_PRE_POS) -#define DSP2_BLBACK_HIST_ROI1_WEIGHT_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_ROI1_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI1_WEIGHT_PRE_POS)) - -/* 0x90C : WDR_HIST_2 */ -#define DSP2_BLBACK_WDR_HIST_2_OFFSET (0x90C) -#define DSP2_BLBACK_HIST_ROI2_EN_PRE DSP2_BLBACK_HIST_ROI2_EN_PRE -#define DSP2_BLBACK_HIST_ROI2_EN_PRE_POS (0U) -#define DSP2_BLBACK_HIST_ROI2_EN_PRE_LEN (1U) -#define DSP2_BLBACK_HIST_ROI2_EN_PRE_MSK (((1U << DSP2_BLBACK_HIST_ROI2_EN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI2_EN_PRE_POS) -#define DSP2_BLBACK_HIST_ROI2_EN_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_ROI2_EN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI2_EN_PRE_POS)) -#define DSP2_BLBACK_HIST_ROI2_WEIGHT_PRE DSP2_BLBACK_HIST_ROI2_WEIGHT_PRE -#define DSP2_BLBACK_HIST_ROI2_WEIGHT_PRE_POS (8U) -#define DSP2_BLBACK_HIST_ROI2_WEIGHT_PRE_LEN (4U) -#define DSP2_BLBACK_HIST_ROI2_WEIGHT_PRE_MSK (((1U << DSP2_BLBACK_HIST_ROI2_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI2_WEIGHT_PRE_POS) -#define DSP2_BLBACK_HIST_ROI2_WEIGHT_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_ROI2_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI2_WEIGHT_PRE_POS)) -#define DSP2_BLBACK_HIST_ROI3_EN_PRE DSP2_BLBACK_HIST_ROI3_EN_PRE -#define DSP2_BLBACK_HIST_ROI3_EN_PRE_POS (16U) -#define DSP2_BLBACK_HIST_ROI3_EN_PRE_LEN (1U) -#define DSP2_BLBACK_HIST_ROI3_EN_PRE_MSK (((1U << DSP2_BLBACK_HIST_ROI3_EN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI3_EN_PRE_POS) -#define DSP2_BLBACK_HIST_ROI3_EN_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_ROI3_EN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI3_EN_PRE_POS)) -#define DSP2_BLBACK_HIST_ROI3_WEIGHT_PRE DSP2_BLBACK_HIST_ROI3_WEIGHT_PRE -#define DSP2_BLBACK_HIST_ROI3_WEIGHT_PRE_POS (24U) -#define DSP2_BLBACK_HIST_ROI3_WEIGHT_PRE_LEN (4U) -#define DSP2_BLBACK_HIST_ROI3_WEIGHT_PRE_MSK (((1U << DSP2_BLBACK_HIST_ROI3_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI3_WEIGHT_PRE_POS) -#define DSP2_BLBACK_HIST_ROI3_WEIGHT_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_ROI3_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI3_WEIGHT_PRE_POS)) - -/* 0x910 : WDR_HIST_3 */ -#define DSP2_BLBACK_WDR_HIST_3_OFFSET (0x910) -#define DSP2_BLBACK_HIST_ROI4_EN_PRE DSP2_BLBACK_HIST_ROI4_EN_PRE -#define DSP2_BLBACK_HIST_ROI4_EN_PRE_POS (0U) -#define DSP2_BLBACK_HIST_ROI4_EN_PRE_LEN (1U) -#define DSP2_BLBACK_HIST_ROI4_EN_PRE_MSK (((1U << DSP2_BLBACK_HIST_ROI4_EN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI4_EN_PRE_POS) -#define DSP2_BLBACK_HIST_ROI4_EN_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_ROI4_EN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI4_EN_PRE_POS)) -#define DSP2_BLBACK_HIST_ROI4_WEIGHT_PRE DSP2_BLBACK_HIST_ROI4_WEIGHT_PRE -#define DSP2_BLBACK_HIST_ROI4_WEIGHT_PRE_POS (8U) -#define DSP2_BLBACK_HIST_ROI4_WEIGHT_PRE_LEN (4U) -#define DSP2_BLBACK_HIST_ROI4_WEIGHT_PRE_MSK (((1U << DSP2_BLBACK_HIST_ROI4_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI4_WEIGHT_PRE_POS) -#define DSP2_BLBACK_HIST_ROI4_WEIGHT_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_ROI4_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI4_WEIGHT_PRE_POS)) -#define DSP2_BLBACK_HIST_ROI5_EN_PRE DSP2_BLBACK_HIST_ROI5_EN_PRE -#define DSP2_BLBACK_HIST_ROI5_EN_PRE_POS (16U) -#define DSP2_BLBACK_HIST_ROI5_EN_PRE_LEN (1U) -#define DSP2_BLBACK_HIST_ROI5_EN_PRE_MSK (((1U << DSP2_BLBACK_HIST_ROI5_EN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI5_EN_PRE_POS) -#define DSP2_BLBACK_HIST_ROI5_EN_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_ROI5_EN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI5_EN_PRE_POS)) -#define DSP2_BLBACK_HIST_ROI5_WEIGHT_PRE DSP2_BLBACK_HIST_ROI5_WEIGHT_PRE -#define DSP2_BLBACK_HIST_ROI5_WEIGHT_PRE_POS (24U) -#define DSP2_BLBACK_HIST_ROI5_WEIGHT_PRE_LEN (4U) -#define DSP2_BLBACK_HIST_ROI5_WEIGHT_PRE_MSK (((1U << DSP2_BLBACK_HIST_ROI5_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI5_WEIGHT_PRE_POS) -#define DSP2_BLBACK_HIST_ROI5_WEIGHT_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_ROI5_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI5_WEIGHT_PRE_POS)) - -/* 0x914 : WDR_HIST_4 */ -#define DSP2_BLBACK_WDR_HIST_4_OFFSET (0x914) -#define DSP2_BLBACK_HIST_ROI6_EN_PRE DSP2_BLBACK_HIST_ROI6_EN_PRE -#define DSP2_BLBACK_HIST_ROI6_EN_PRE_POS (0U) -#define DSP2_BLBACK_HIST_ROI6_EN_PRE_LEN (1U) -#define DSP2_BLBACK_HIST_ROI6_EN_PRE_MSK (((1U << DSP2_BLBACK_HIST_ROI6_EN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI6_EN_PRE_POS) -#define DSP2_BLBACK_HIST_ROI6_EN_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_ROI6_EN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI6_EN_PRE_POS)) -#define DSP2_BLBACK_HIST_ROI6_WEIGHT_PRE DSP2_BLBACK_HIST_ROI6_WEIGHT_PRE -#define DSP2_BLBACK_HIST_ROI6_WEIGHT_PRE_POS (8U) -#define DSP2_BLBACK_HIST_ROI6_WEIGHT_PRE_LEN (4U) -#define DSP2_BLBACK_HIST_ROI6_WEIGHT_PRE_MSK (((1U << DSP2_BLBACK_HIST_ROI6_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI6_WEIGHT_PRE_POS) -#define DSP2_BLBACK_HIST_ROI6_WEIGHT_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_ROI6_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI6_WEIGHT_PRE_POS)) -#define DSP2_BLBACK_HIST_ROI7_EN_PRE DSP2_BLBACK_HIST_ROI7_EN_PRE -#define DSP2_BLBACK_HIST_ROI7_EN_PRE_POS (16U) -#define DSP2_BLBACK_HIST_ROI7_EN_PRE_LEN (1U) -#define DSP2_BLBACK_HIST_ROI7_EN_PRE_MSK (((1U << DSP2_BLBACK_HIST_ROI7_EN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI7_EN_PRE_POS) -#define DSP2_BLBACK_HIST_ROI7_EN_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_ROI7_EN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI7_EN_PRE_POS)) -#define DSP2_BLBACK_HIST_ROI7_WEIGHT_PRE DSP2_BLBACK_HIST_ROI7_WEIGHT_PRE -#define DSP2_BLBACK_HIST_ROI7_WEIGHT_PRE_POS (24U) -#define DSP2_BLBACK_HIST_ROI7_WEIGHT_PRE_LEN (4U) -#define DSP2_BLBACK_HIST_ROI7_WEIGHT_PRE_MSK (((1U << DSP2_BLBACK_HIST_ROI7_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI7_WEIGHT_PRE_POS) -#define DSP2_BLBACK_HIST_ROI7_WEIGHT_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_ROI7_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI7_WEIGHT_PRE_POS)) - -/* 0x918 : WDR_HIST_5 */ -#define DSP2_BLBACK_WDR_HIST_5_OFFSET (0x918) -#define DSP2_BLBACK_HIST_X0_MAX_PRE DSP2_BLBACK_HIST_X0_MAX_PRE -#define DSP2_BLBACK_HIST_X0_MAX_PRE_POS (0U) -#define DSP2_BLBACK_HIST_X0_MAX_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_X0_MAX_PRE_MSK (((1U << DSP2_BLBACK_HIST_X0_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X0_MAX_PRE_POS) -#define DSP2_BLBACK_HIST_X0_MAX_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_X0_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X0_MAX_PRE_POS)) -#define DSP2_BLBACK_HIST_X0_MIN_PRE DSP2_BLBACK_HIST_X0_MIN_PRE -#define DSP2_BLBACK_HIST_X0_MIN_PRE_POS (16U) -#define DSP2_BLBACK_HIST_X0_MIN_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_X0_MIN_PRE_MSK (((1U << DSP2_BLBACK_HIST_X0_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X0_MIN_PRE_POS) -#define DSP2_BLBACK_HIST_X0_MIN_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_X0_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X0_MIN_PRE_POS)) - -/* 0x91C : WDR_HIST_6 */ -#define DSP2_BLBACK_WDR_HIST_6_OFFSET (0x91C) -#define DSP2_BLBACK_HIST_Y0_MAX_PRE DSP2_BLBACK_HIST_Y0_MAX_PRE -#define DSP2_BLBACK_HIST_Y0_MAX_PRE_POS (0U) -#define DSP2_BLBACK_HIST_Y0_MAX_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_Y0_MAX_PRE_MSK (((1U << DSP2_BLBACK_HIST_Y0_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y0_MAX_PRE_POS) -#define DSP2_BLBACK_HIST_Y0_MAX_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_Y0_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y0_MAX_PRE_POS)) -#define DSP2_BLBACK_HIST_Y0_MIN_PRE DSP2_BLBACK_HIST_Y0_MIN_PRE -#define DSP2_BLBACK_HIST_Y0_MIN_PRE_POS (16U) -#define DSP2_BLBACK_HIST_Y0_MIN_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_Y0_MIN_PRE_MSK (((1U << DSP2_BLBACK_HIST_Y0_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y0_MIN_PRE_POS) -#define DSP2_BLBACK_HIST_Y0_MIN_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_Y0_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y0_MIN_PRE_POS)) - -/* 0x920 : WDR_HIST_7 */ -#define DSP2_BLBACK_WDR_HIST_7_OFFSET (0x920) -#define DSP2_BLBACK_HIST_X1_MAX_PRE DSP2_BLBACK_HIST_X1_MAX_PRE -#define DSP2_BLBACK_HIST_X1_MAX_PRE_POS (0U) -#define DSP2_BLBACK_HIST_X1_MAX_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_X1_MAX_PRE_MSK (((1U << DSP2_BLBACK_HIST_X1_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X1_MAX_PRE_POS) -#define DSP2_BLBACK_HIST_X1_MAX_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_X1_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X1_MAX_PRE_POS)) -#define DSP2_BLBACK_HIST_X1_MIN_PRE DSP2_BLBACK_HIST_X1_MIN_PRE -#define DSP2_BLBACK_HIST_X1_MIN_PRE_POS (16U) -#define DSP2_BLBACK_HIST_X1_MIN_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_X1_MIN_PRE_MSK (((1U << DSP2_BLBACK_HIST_X1_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X1_MIN_PRE_POS) -#define DSP2_BLBACK_HIST_X1_MIN_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_X1_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X1_MIN_PRE_POS)) - -/* 0x924 : WDR_HIST_8 */ -#define DSP2_BLBACK_WDR_HIST_8_OFFSET (0x924) -#define DSP2_BLBACK_HIST_Y1_MAX_PRE DSP2_BLBACK_HIST_Y1_MAX_PRE -#define DSP2_BLBACK_HIST_Y1_MAX_PRE_POS (0U) -#define DSP2_BLBACK_HIST_Y1_MAX_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_Y1_MAX_PRE_MSK (((1U << DSP2_BLBACK_HIST_Y1_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y1_MAX_PRE_POS) -#define DSP2_BLBACK_HIST_Y1_MAX_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_Y1_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y1_MAX_PRE_POS)) -#define DSP2_BLBACK_HIST_Y1_MIN_PRE DSP2_BLBACK_HIST_Y1_MIN_PRE -#define DSP2_BLBACK_HIST_Y1_MIN_PRE_POS (16U) -#define DSP2_BLBACK_HIST_Y1_MIN_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_Y1_MIN_PRE_MSK (((1U << DSP2_BLBACK_HIST_Y1_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y1_MIN_PRE_POS) -#define DSP2_BLBACK_HIST_Y1_MIN_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_Y1_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y1_MIN_PRE_POS)) - -/* 0x928 : WDR_HIST_9 */ -#define DSP2_BLBACK_WDR_HIST_9_OFFSET (0x928) -#define DSP2_BLBACK_HIST_X2_MAX_PRE DSP2_BLBACK_HIST_X2_MAX_PRE -#define DSP2_BLBACK_HIST_X2_MAX_PRE_POS (0U) -#define DSP2_BLBACK_HIST_X2_MAX_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_X2_MAX_PRE_MSK (((1U << DSP2_BLBACK_HIST_X2_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X2_MAX_PRE_POS) -#define DSP2_BLBACK_HIST_X2_MAX_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_X2_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X2_MAX_PRE_POS)) -#define DSP2_BLBACK_HIST_X2_MIN_PRE DSP2_BLBACK_HIST_X2_MIN_PRE -#define DSP2_BLBACK_HIST_X2_MIN_PRE_POS (16U) -#define DSP2_BLBACK_HIST_X2_MIN_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_X2_MIN_PRE_MSK (((1U << DSP2_BLBACK_HIST_X2_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X2_MIN_PRE_POS) -#define DSP2_BLBACK_HIST_X2_MIN_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_X2_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X2_MIN_PRE_POS)) - -/* 0x92C : WDR_HIST_10 */ -#define DSP2_BLBACK_WDR_HIST_10_OFFSET (0x92C) -#define DSP2_BLBACK_HIST_Y2_MAX_PRE DSP2_BLBACK_HIST_Y2_MAX_PRE -#define DSP2_BLBACK_HIST_Y2_MAX_PRE_POS (0U) -#define DSP2_BLBACK_HIST_Y2_MAX_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_Y2_MAX_PRE_MSK (((1U << DSP2_BLBACK_HIST_Y2_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y2_MAX_PRE_POS) -#define DSP2_BLBACK_HIST_Y2_MAX_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_Y2_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y2_MAX_PRE_POS)) -#define DSP2_BLBACK_HIST_Y2_MIN_PRE DSP2_BLBACK_HIST_Y2_MIN_PRE -#define DSP2_BLBACK_HIST_Y2_MIN_PRE_POS (16U) -#define DSP2_BLBACK_HIST_Y2_MIN_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_Y2_MIN_PRE_MSK (((1U << DSP2_BLBACK_HIST_Y2_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y2_MIN_PRE_POS) -#define DSP2_BLBACK_HIST_Y2_MIN_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_Y2_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y2_MIN_PRE_POS)) - -/* 0x930 : WDR_HIST_11 */ -#define DSP2_BLBACK_WDR_HIST_11_OFFSET (0x930) -#define DSP2_BLBACK_HIST_X3_MAX_PRE DSP2_BLBACK_HIST_X3_MAX_PRE -#define DSP2_BLBACK_HIST_X3_MAX_PRE_POS (0U) -#define DSP2_BLBACK_HIST_X3_MAX_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_X3_MAX_PRE_MSK (((1U << DSP2_BLBACK_HIST_X3_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X3_MAX_PRE_POS) -#define DSP2_BLBACK_HIST_X3_MAX_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_X3_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X3_MAX_PRE_POS)) -#define DSP2_BLBACK_HIST_X3_MIN_PRE DSP2_BLBACK_HIST_X3_MIN_PRE -#define DSP2_BLBACK_HIST_X3_MIN_PRE_POS (16U) -#define DSP2_BLBACK_HIST_X3_MIN_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_X3_MIN_PRE_MSK (((1U << DSP2_BLBACK_HIST_X3_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X3_MIN_PRE_POS) -#define DSP2_BLBACK_HIST_X3_MIN_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_X3_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X3_MIN_PRE_POS)) - -/* 0x934 : WDR_HIST_12 */ -#define DSP2_BLBACK_WDR_HIST_12_OFFSET (0x934) -#define DSP2_BLBACK_HIST_Y3_MAX_PRE DSP2_BLBACK_HIST_Y3_MAX_PRE -#define DSP2_BLBACK_HIST_Y3_MAX_PRE_POS (0U) -#define DSP2_BLBACK_HIST_Y3_MAX_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_Y3_MAX_PRE_MSK (((1U << DSP2_BLBACK_HIST_Y3_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y3_MAX_PRE_POS) -#define DSP2_BLBACK_HIST_Y3_MAX_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_Y3_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y3_MAX_PRE_POS)) -#define DSP2_BLBACK_HIST_Y3_MIN_PRE DSP2_BLBACK_HIST_Y3_MIN_PRE -#define DSP2_BLBACK_HIST_Y3_MIN_PRE_POS (16U) -#define DSP2_BLBACK_HIST_Y3_MIN_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_Y3_MIN_PRE_MSK (((1U << DSP2_BLBACK_HIST_Y3_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y3_MIN_PRE_POS) -#define DSP2_BLBACK_HIST_Y3_MIN_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_Y3_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y3_MIN_PRE_POS)) - -/* 0x938 : WDR_HIST_13 */ -#define DSP2_BLBACK_WDR_HIST_13_OFFSET (0x938) -#define DSP2_BLBACK_HIST_X4_MAX_PRE DSP2_BLBACK_HIST_X4_MAX_PRE -#define DSP2_BLBACK_HIST_X4_MAX_PRE_POS (0U) -#define DSP2_BLBACK_HIST_X4_MAX_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_X4_MAX_PRE_MSK (((1U << DSP2_BLBACK_HIST_X4_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X4_MAX_PRE_POS) -#define DSP2_BLBACK_HIST_X4_MAX_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_X4_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X4_MAX_PRE_POS)) -#define DSP2_BLBACK_HIST_X4_MIN_PRE DSP2_BLBACK_HIST_X4_MIN_PRE -#define DSP2_BLBACK_HIST_X4_MIN_PRE_POS (16U) -#define DSP2_BLBACK_HIST_X4_MIN_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_X4_MIN_PRE_MSK (((1U << DSP2_BLBACK_HIST_X4_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X4_MIN_PRE_POS) -#define DSP2_BLBACK_HIST_X4_MIN_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_X4_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X4_MIN_PRE_POS)) - -/* 0x93C : WDR_HIST_14 */ -#define DSP2_BLBACK_WDR_HIST_14_OFFSET (0x93C) -#define DSP2_BLBACK_HIST_Y4_MAX_PRE DSP2_BLBACK_HIST_Y4_MAX_PRE -#define DSP2_BLBACK_HIST_Y4_MAX_PRE_POS (0U) -#define DSP2_BLBACK_HIST_Y4_MAX_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_Y4_MAX_PRE_MSK (((1U << DSP2_BLBACK_HIST_Y4_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y4_MAX_PRE_POS) -#define DSP2_BLBACK_HIST_Y4_MAX_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_Y4_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y4_MAX_PRE_POS)) -#define DSP2_BLBACK_HIST_Y4_MIN_PRE DSP2_BLBACK_HIST_Y4_MIN_PRE -#define DSP2_BLBACK_HIST_Y4_MIN_PRE_POS (16U) -#define DSP2_BLBACK_HIST_Y4_MIN_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_Y4_MIN_PRE_MSK (((1U << DSP2_BLBACK_HIST_Y4_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y4_MIN_PRE_POS) -#define DSP2_BLBACK_HIST_Y4_MIN_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_Y4_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y4_MIN_PRE_POS)) - -/* 0x940 : WDR_HIST_15 */ -#define DSP2_BLBACK_WDR_HIST_15_OFFSET (0x940) -#define DSP2_BLBACK_HIST_X5_MAX_PRE DSP2_BLBACK_HIST_X5_MAX_PRE -#define DSP2_BLBACK_HIST_X5_MAX_PRE_POS (0U) -#define DSP2_BLBACK_HIST_X5_MAX_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_X5_MAX_PRE_MSK (((1U << DSP2_BLBACK_HIST_X5_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X5_MAX_PRE_POS) -#define DSP2_BLBACK_HIST_X5_MAX_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_X5_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X5_MAX_PRE_POS)) -#define DSP2_BLBACK_HIST_X5_MIN_PRE DSP2_BLBACK_HIST_X5_MIN_PRE -#define DSP2_BLBACK_HIST_X5_MIN_PRE_POS (16U) -#define DSP2_BLBACK_HIST_X5_MIN_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_X5_MIN_PRE_MSK (((1U << DSP2_BLBACK_HIST_X5_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X5_MIN_PRE_POS) -#define DSP2_BLBACK_HIST_X5_MIN_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_X5_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X5_MIN_PRE_POS)) - -/* 0x944 : WDR_HIST_16 */ -#define DSP2_BLBACK_WDR_HIST_16_OFFSET (0x944) -#define DSP2_BLBACK_HIST_Y5_MAX_PRE DSP2_BLBACK_HIST_Y5_MAX_PRE -#define DSP2_BLBACK_HIST_Y5_MAX_PRE_POS (0U) -#define DSP2_BLBACK_HIST_Y5_MAX_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_Y5_MAX_PRE_MSK (((1U << DSP2_BLBACK_HIST_Y5_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y5_MAX_PRE_POS) -#define DSP2_BLBACK_HIST_Y5_MAX_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_Y5_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y5_MAX_PRE_POS)) -#define DSP2_BLBACK_HIST_Y5_MIN_PRE DSP2_BLBACK_HIST_Y5_MIN_PRE -#define DSP2_BLBACK_HIST_Y5_MIN_PRE_POS (16U) -#define DSP2_BLBACK_HIST_Y5_MIN_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_Y5_MIN_PRE_MSK (((1U << DSP2_BLBACK_HIST_Y5_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y5_MIN_PRE_POS) -#define DSP2_BLBACK_HIST_Y5_MIN_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_Y5_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y5_MIN_PRE_POS)) - -/* 0x948 : WDR_HIST_17 */ -#define DSP2_BLBACK_WDR_HIST_17_OFFSET (0x948) -#define DSP2_BLBACK_HIST_X6_MAX_PRE DSP2_BLBACK_HIST_X6_MAX_PRE -#define DSP2_BLBACK_HIST_X6_MAX_PRE_POS (0U) -#define DSP2_BLBACK_HIST_X6_MAX_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_X6_MAX_PRE_MSK (((1U << DSP2_BLBACK_HIST_X6_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X6_MAX_PRE_POS) -#define DSP2_BLBACK_HIST_X6_MAX_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_X6_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X6_MAX_PRE_POS)) -#define DSP2_BLBACK_HIST_X6_MIN_PRE DSP2_BLBACK_HIST_X6_MIN_PRE -#define DSP2_BLBACK_HIST_X6_MIN_PRE_POS (16U) -#define DSP2_BLBACK_HIST_X6_MIN_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_X6_MIN_PRE_MSK (((1U << DSP2_BLBACK_HIST_X6_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X6_MIN_PRE_POS) -#define DSP2_BLBACK_HIST_X6_MIN_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_X6_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X6_MIN_PRE_POS)) - -/* 0x94C : WDR_HIST_18 */ -#define DSP2_BLBACK_WDR_HIST_18_OFFSET (0x94C) -#define DSP2_BLBACK_HIST_Y6_MAX_PRE DSP2_BLBACK_HIST_Y6_MAX_PRE -#define DSP2_BLBACK_HIST_Y6_MAX_PRE_POS (0U) -#define DSP2_BLBACK_HIST_Y6_MAX_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_Y6_MAX_PRE_MSK (((1U << DSP2_BLBACK_HIST_Y6_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y6_MAX_PRE_POS) -#define DSP2_BLBACK_HIST_Y6_MAX_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_Y6_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y6_MAX_PRE_POS)) -#define DSP2_BLBACK_HIST_Y6_MIN_PRE DSP2_BLBACK_HIST_Y6_MIN_PRE -#define DSP2_BLBACK_HIST_Y6_MIN_PRE_POS (16U) -#define DSP2_BLBACK_HIST_Y6_MIN_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_Y6_MIN_PRE_MSK (((1U << DSP2_BLBACK_HIST_Y6_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y6_MIN_PRE_POS) -#define DSP2_BLBACK_HIST_Y6_MIN_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_Y6_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y6_MIN_PRE_POS)) - -/* 0x950 : WDR_HIST_19 */ -#define DSP2_BLBACK_WDR_HIST_19_OFFSET (0x950) -#define DSP2_BLBACK_HIST_X7_MAX_PRE DSP2_BLBACK_HIST_X7_MAX_PRE -#define DSP2_BLBACK_HIST_X7_MAX_PRE_POS (0U) -#define DSP2_BLBACK_HIST_X7_MAX_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_X7_MAX_PRE_MSK (((1U << DSP2_BLBACK_HIST_X7_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X7_MAX_PRE_POS) -#define DSP2_BLBACK_HIST_X7_MAX_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_X7_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X7_MAX_PRE_POS)) -#define DSP2_BLBACK_HIST_X7_MIN_PRE DSP2_BLBACK_HIST_X7_MIN_PRE -#define DSP2_BLBACK_HIST_X7_MIN_PRE_POS (16U) -#define DSP2_BLBACK_HIST_X7_MIN_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_X7_MIN_PRE_MSK (((1U << DSP2_BLBACK_HIST_X7_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X7_MIN_PRE_POS) -#define DSP2_BLBACK_HIST_X7_MIN_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_X7_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X7_MIN_PRE_POS)) - -/* 0x954 : WDR_HIST_20 */ -#define DSP2_BLBACK_WDR_HIST_20_OFFSET (0x954) -#define DSP2_BLBACK_HIST_Y7_MAX_PRE DSP2_BLBACK_HIST_Y7_MAX_PRE -#define DSP2_BLBACK_HIST_Y7_MAX_PRE_POS (0U) -#define DSP2_BLBACK_HIST_Y7_MAX_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_Y7_MAX_PRE_MSK (((1U << DSP2_BLBACK_HIST_Y7_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y7_MAX_PRE_POS) -#define DSP2_BLBACK_HIST_Y7_MAX_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_Y7_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y7_MAX_PRE_POS)) -#define DSP2_BLBACK_HIST_Y7_MIN_PRE DSP2_BLBACK_HIST_Y7_MIN_PRE -#define DSP2_BLBACK_HIST_Y7_MIN_PRE_POS (16U) -#define DSP2_BLBACK_HIST_Y7_MIN_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_Y7_MIN_PRE_MSK (((1U << DSP2_BLBACK_HIST_Y7_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y7_MIN_PRE_POS) -#define DSP2_BLBACK_HIST_Y7_MIN_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_Y7_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y7_MIN_PRE_POS)) - -/* 0x958 : REG_HIST0_64 */ -#define DSP2_BLBACK_REG_HIST0_64_OFFSET (0x958) -#define DSP2_BLBACK_HIST0_64_R DSP2_BLBACK_HIST0_64_R -#define DSP2_BLBACK_HIST0_64_R_POS (0U) -#define DSP2_BLBACK_HIST0_64_R_LEN (24U) -#define DSP2_BLBACK_HIST0_64_R_MSK (((1U << DSP2_BLBACK_HIST0_64_R_LEN) - 1) << DSP2_BLBACK_HIST0_64_R_POS) -#define DSP2_BLBACK_HIST0_64_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_64_R_LEN) - 1) << DSP2_BLBACK_HIST0_64_R_POS)) - -/* 0x95C : REG_HIST1_64 */ -#define DSP2_BLBACK_REG_HIST1_64_OFFSET (0x95C) -#define DSP2_BLBACK_HIST1_64_R DSP2_BLBACK_HIST1_64_R -#define DSP2_BLBACK_HIST1_64_R_POS (0U) -#define DSP2_BLBACK_HIST1_64_R_LEN (24U) -#define DSP2_BLBACK_HIST1_64_R_MSK (((1U << DSP2_BLBACK_HIST1_64_R_LEN) - 1) << DSP2_BLBACK_HIST1_64_R_POS) -#define DSP2_BLBACK_HIST1_64_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_64_R_LEN) - 1) << DSP2_BLBACK_HIST1_64_R_POS)) - -/* 0xA00 : REG_HIST0_0 */ -#define DSP2_BLBACK_REG_HIST0_0_OFFSET (0xA00) -#define DSP2_BLBACK_HIST0_0_R DSP2_BLBACK_HIST0_0_R -#define DSP2_BLBACK_HIST0_0_R_POS (0U) -#define DSP2_BLBACK_HIST0_0_R_LEN (24U) -#define DSP2_BLBACK_HIST0_0_R_MSK (((1U << DSP2_BLBACK_HIST0_0_R_LEN) - 1) << DSP2_BLBACK_HIST0_0_R_POS) -#define DSP2_BLBACK_HIST0_0_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_0_R_LEN) - 1) << DSP2_BLBACK_HIST0_0_R_POS)) - -/* 0xA04 : REG_HIST0_1 */ -#define DSP2_BLBACK_REG_HIST0_1_OFFSET (0xA04) -#define DSP2_BLBACK_HIST0_1_R DSP2_BLBACK_HIST0_1_R -#define DSP2_BLBACK_HIST0_1_R_POS (0U) -#define DSP2_BLBACK_HIST0_1_R_LEN (24U) -#define DSP2_BLBACK_HIST0_1_R_MSK (((1U << DSP2_BLBACK_HIST0_1_R_LEN) - 1) << DSP2_BLBACK_HIST0_1_R_POS) -#define DSP2_BLBACK_HIST0_1_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_1_R_LEN) - 1) << DSP2_BLBACK_HIST0_1_R_POS)) - -/* 0xA08 : REG_HIST0_2 */ -#define DSP2_BLBACK_REG_HIST0_2_OFFSET (0xA08) -#define DSP2_BLBACK_HIST0_2_R DSP2_BLBACK_HIST0_2_R -#define DSP2_BLBACK_HIST0_2_R_POS (0U) -#define DSP2_BLBACK_HIST0_2_R_LEN (24U) -#define DSP2_BLBACK_HIST0_2_R_MSK (((1U << DSP2_BLBACK_HIST0_2_R_LEN) - 1) << DSP2_BLBACK_HIST0_2_R_POS) -#define DSP2_BLBACK_HIST0_2_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_2_R_LEN) - 1) << DSP2_BLBACK_HIST0_2_R_POS)) - -/* 0xA0C : REG_HIST0_3 */ -#define DSP2_BLBACK_REG_HIST0_3_OFFSET (0xA0C) -#define DSP2_BLBACK_HIST0_3_R DSP2_BLBACK_HIST0_3_R -#define DSP2_BLBACK_HIST0_3_R_POS (0U) -#define DSP2_BLBACK_HIST0_3_R_LEN (24U) -#define DSP2_BLBACK_HIST0_3_R_MSK (((1U << DSP2_BLBACK_HIST0_3_R_LEN) - 1) << DSP2_BLBACK_HIST0_3_R_POS) -#define DSP2_BLBACK_HIST0_3_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_3_R_LEN) - 1) << DSP2_BLBACK_HIST0_3_R_POS)) - -/* 0xA10 : REG_HIST0_4 */ -#define DSP2_BLBACK_REG_HIST0_4_OFFSET (0xA10) -#define DSP2_BLBACK_HIST0_4_R DSP2_BLBACK_HIST0_4_R -#define DSP2_BLBACK_HIST0_4_R_POS (0U) -#define DSP2_BLBACK_HIST0_4_R_LEN (24U) -#define DSP2_BLBACK_HIST0_4_R_MSK (((1U << DSP2_BLBACK_HIST0_4_R_LEN) - 1) << DSP2_BLBACK_HIST0_4_R_POS) -#define DSP2_BLBACK_HIST0_4_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_4_R_LEN) - 1) << DSP2_BLBACK_HIST0_4_R_POS)) - -/* 0xA14 : REG_HIST0_5 */ -#define DSP2_BLBACK_REG_HIST0_5_OFFSET (0xA14) -#define DSP2_BLBACK_HIST0_5_R DSP2_BLBACK_HIST0_5_R -#define DSP2_BLBACK_HIST0_5_R_POS (0U) -#define DSP2_BLBACK_HIST0_5_R_LEN (24U) -#define DSP2_BLBACK_HIST0_5_R_MSK (((1U << DSP2_BLBACK_HIST0_5_R_LEN) - 1) << DSP2_BLBACK_HIST0_5_R_POS) -#define DSP2_BLBACK_HIST0_5_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_5_R_LEN) - 1) << DSP2_BLBACK_HIST0_5_R_POS)) - -/* 0xA18 : REG_HIST0_6 */ -#define DSP2_BLBACK_REG_HIST0_6_OFFSET (0xA18) -#define DSP2_BLBACK_HIST0_6_R DSP2_BLBACK_HIST0_6_R -#define DSP2_BLBACK_HIST0_6_R_POS (0U) -#define DSP2_BLBACK_HIST0_6_R_LEN (24U) -#define DSP2_BLBACK_HIST0_6_R_MSK (((1U << DSP2_BLBACK_HIST0_6_R_LEN) - 1) << DSP2_BLBACK_HIST0_6_R_POS) -#define DSP2_BLBACK_HIST0_6_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_6_R_LEN) - 1) << DSP2_BLBACK_HIST0_6_R_POS)) - -/* 0xA1C : REG_HIST0_7 */ -#define DSP2_BLBACK_REG_HIST0_7_OFFSET (0xA1C) -#define DSP2_BLBACK_HIST0_7_R DSP2_BLBACK_HIST0_7_R -#define DSP2_BLBACK_HIST0_7_R_POS (0U) -#define DSP2_BLBACK_HIST0_7_R_LEN (24U) -#define DSP2_BLBACK_HIST0_7_R_MSK (((1U << DSP2_BLBACK_HIST0_7_R_LEN) - 1) << DSP2_BLBACK_HIST0_7_R_POS) -#define DSP2_BLBACK_HIST0_7_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_7_R_LEN) - 1) << DSP2_BLBACK_HIST0_7_R_POS)) - -/* 0xA20 : REG_HIST0_8 */ -#define DSP2_BLBACK_REG_HIST0_8_OFFSET (0xA20) -#define DSP2_BLBACK_HIST0_8_R DSP2_BLBACK_HIST0_8_R -#define DSP2_BLBACK_HIST0_8_R_POS (0U) -#define DSP2_BLBACK_HIST0_8_R_LEN (24U) -#define DSP2_BLBACK_HIST0_8_R_MSK (((1U << DSP2_BLBACK_HIST0_8_R_LEN) - 1) << DSP2_BLBACK_HIST0_8_R_POS) -#define DSP2_BLBACK_HIST0_8_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_8_R_LEN) - 1) << DSP2_BLBACK_HIST0_8_R_POS)) - -/* 0xA24 : REG_HIST0_9 */ -#define DSP2_BLBACK_REG_HIST0_9_OFFSET (0xA24) -#define DSP2_BLBACK_HIST0_9_R DSP2_BLBACK_HIST0_9_R -#define DSP2_BLBACK_HIST0_9_R_POS (0U) -#define DSP2_BLBACK_HIST0_9_R_LEN (24U) -#define DSP2_BLBACK_HIST0_9_R_MSK (((1U << DSP2_BLBACK_HIST0_9_R_LEN) - 1) << DSP2_BLBACK_HIST0_9_R_POS) -#define DSP2_BLBACK_HIST0_9_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_9_R_LEN) - 1) << DSP2_BLBACK_HIST0_9_R_POS)) - -/* 0xA28 : REG_HIST0_10 */ -#define DSP2_BLBACK_REG_HIST0_10_OFFSET (0xA28) -#define DSP2_BLBACK_HIST0_10_R DSP2_BLBACK_HIST0_10_R -#define DSP2_BLBACK_HIST0_10_R_POS (0U) -#define DSP2_BLBACK_HIST0_10_R_LEN (24U) -#define DSP2_BLBACK_HIST0_10_R_MSK (((1U << DSP2_BLBACK_HIST0_10_R_LEN) - 1) << DSP2_BLBACK_HIST0_10_R_POS) -#define DSP2_BLBACK_HIST0_10_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_10_R_LEN) - 1) << DSP2_BLBACK_HIST0_10_R_POS)) - -/* 0xA2C : REG_HIST0_11 */ -#define DSP2_BLBACK_REG_HIST0_11_OFFSET (0xA2C) -#define DSP2_BLBACK_HIST0_11_R DSP2_BLBACK_HIST0_11_R -#define DSP2_BLBACK_HIST0_11_R_POS (0U) -#define DSP2_BLBACK_HIST0_11_R_LEN (24U) -#define DSP2_BLBACK_HIST0_11_R_MSK (((1U << DSP2_BLBACK_HIST0_11_R_LEN) - 1) << DSP2_BLBACK_HIST0_11_R_POS) -#define DSP2_BLBACK_HIST0_11_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_11_R_LEN) - 1) << DSP2_BLBACK_HIST0_11_R_POS)) - -/* 0xA30 : REG_HIST0_12 */ -#define DSP2_BLBACK_REG_HIST0_12_OFFSET (0xA30) -#define DSP2_BLBACK_HIST0_12_R DSP2_BLBACK_HIST0_12_R -#define DSP2_BLBACK_HIST0_12_R_POS (0U) -#define DSP2_BLBACK_HIST0_12_R_LEN (24U) -#define DSP2_BLBACK_HIST0_12_R_MSK (((1U << DSP2_BLBACK_HIST0_12_R_LEN) - 1) << DSP2_BLBACK_HIST0_12_R_POS) -#define DSP2_BLBACK_HIST0_12_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_12_R_LEN) - 1) << DSP2_BLBACK_HIST0_12_R_POS)) - -/* 0xA34 : REG_HIST0_13 */ -#define DSP2_BLBACK_REG_HIST0_13_OFFSET (0xA34) -#define DSP2_BLBACK_HIST0_13_R DSP2_BLBACK_HIST0_13_R -#define DSP2_BLBACK_HIST0_13_R_POS (0U) -#define DSP2_BLBACK_HIST0_13_R_LEN (24U) -#define DSP2_BLBACK_HIST0_13_R_MSK (((1U << DSP2_BLBACK_HIST0_13_R_LEN) - 1) << DSP2_BLBACK_HIST0_13_R_POS) -#define DSP2_BLBACK_HIST0_13_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_13_R_LEN) - 1) << DSP2_BLBACK_HIST0_13_R_POS)) - -/* 0xA38 : REG_HIST0_14 */ -#define DSP2_BLBACK_REG_HIST0_14_OFFSET (0xA38) -#define DSP2_BLBACK_HIST0_14_R DSP2_BLBACK_HIST0_14_R -#define DSP2_BLBACK_HIST0_14_R_POS (0U) -#define DSP2_BLBACK_HIST0_14_R_LEN (24U) -#define DSP2_BLBACK_HIST0_14_R_MSK (((1U << DSP2_BLBACK_HIST0_14_R_LEN) - 1) << DSP2_BLBACK_HIST0_14_R_POS) -#define DSP2_BLBACK_HIST0_14_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_14_R_LEN) - 1) << DSP2_BLBACK_HIST0_14_R_POS)) - -/* 0xA3C : REG_HIST0_15 */ -#define DSP2_BLBACK_REG_HIST0_15_OFFSET (0xA3C) -#define DSP2_BLBACK_HIST0_15_R DSP2_BLBACK_HIST0_15_R -#define DSP2_BLBACK_HIST0_15_R_POS (0U) -#define DSP2_BLBACK_HIST0_15_R_LEN (24U) -#define DSP2_BLBACK_HIST0_15_R_MSK (((1U << DSP2_BLBACK_HIST0_15_R_LEN) - 1) << DSP2_BLBACK_HIST0_15_R_POS) -#define DSP2_BLBACK_HIST0_15_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_15_R_LEN) - 1) << DSP2_BLBACK_HIST0_15_R_POS)) - -/* 0xA40 : REG_HIST0_16 */ -#define DSP2_BLBACK_REG_HIST0_16_OFFSET (0xA40) -#define DSP2_BLBACK_HIST0_16_R DSP2_BLBACK_HIST0_16_R -#define DSP2_BLBACK_HIST0_16_R_POS (0U) -#define DSP2_BLBACK_HIST0_16_R_LEN (24U) -#define DSP2_BLBACK_HIST0_16_R_MSK (((1U << DSP2_BLBACK_HIST0_16_R_LEN) - 1) << DSP2_BLBACK_HIST0_16_R_POS) -#define DSP2_BLBACK_HIST0_16_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_16_R_LEN) - 1) << DSP2_BLBACK_HIST0_16_R_POS)) - -/* 0xA44 : REG_HIST0_17 */ -#define DSP2_BLBACK_REG_HIST0_17_OFFSET (0xA44) -#define DSP2_BLBACK_HIST0_17_R DSP2_BLBACK_HIST0_17_R -#define DSP2_BLBACK_HIST0_17_R_POS (0U) -#define DSP2_BLBACK_HIST0_17_R_LEN (24U) -#define DSP2_BLBACK_HIST0_17_R_MSK (((1U << DSP2_BLBACK_HIST0_17_R_LEN) - 1) << DSP2_BLBACK_HIST0_17_R_POS) -#define DSP2_BLBACK_HIST0_17_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_17_R_LEN) - 1) << DSP2_BLBACK_HIST0_17_R_POS)) - -/* 0xA48 : REG_HIST0_18 */ -#define DSP2_BLBACK_REG_HIST0_18_OFFSET (0xA48) -#define DSP2_BLBACK_HIST0_18_R DSP2_BLBACK_HIST0_18_R -#define DSP2_BLBACK_HIST0_18_R_POS (0U) -#define DSP2_BLBACK_HIST0_18_R_LEN (24U) -#define DSP2_BLBACK_HIST0_18_R_MSK (((1U << DSP2_BLBACK_HIST0_18_R_LEN) - 1) << DSP2_BLBACK_HIST0_18_R_POS) -#define DSP2_BLBACK_HIST0_18_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_18_R_LEN) - 1) << DSP2_BLBACK_HIST0_18_R_POS)) - -/* 0xA4C : REG_HIST0_19 */ -#define DSP2_BLBACK_REG_HIST0_19_OFFSET (0xA4C) -#define DSP2_BLBACK_HIST0_19_R DSP2_BLBACK_HIST0_19_R -#define DSP2_BLBACK_HIST0_19_R_POS (0U) -#define DSP2_BLBACK_HIST0_19_R_LEN (24U) -#define DSP2_BLBACK_HIST0_19_R_MSK (((1U << DSP2_BLBACK_HIST0_19_R_LEN) - 1) << DSP2_BLBACK_HIST0_19_R_POS) -#define DSP2_BLBACK_HIST0_19_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_19_R_LEN) - 1) << DSP2_BLBACK_HIST0_19_R_POS)) - -/* 0xA50 : REG_HIST0_20 */ -#define DSP2_BLBACK_REG_HIST0_20_OFFSET (0xA50) -#define DSP2_BLBACK_HIST0_20_R DSP2_BLBACK_HIST0_20_R -#define DSP2_BLBACK_HIST0_20_R_POS (0U) -#define DSP2_BLBACK_HIST0_20_R_LEN (24U) -#define DSP2_BLBACK_HIST0_20_R_MSK (((1U << DSP2_BLBACK_HIST0_20_R_LEN) - 1) << DSP2_BLBACK_HIST0_20_R_POS) -#define DSP2_BLBACK_HIST0_20_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_20_R_LEN) - 1) << DSP2_BLBACK_HIST0_20_R_POS)) - -/* 0xA54 : REG_HIST0_21 */ -#define DSP2_BLBACK_REG_HIST0_21_OFFSET (0xA54) -#define DSP2_BLBACK_HIST0_21_R DSP2_BLBACK_HIST0_21_R -#define DSP2_BLBACK_HIST0_21_R_POS (0U) -#define DSP2_BLBACK_HIST0_21_R_LEN (24U) -#define DSP2_BLBACK_HIST0_21_R_MSK (((1U << DSP2_BLBACK_HIST0_21_R_LEN) - 1) << DSP2_BLBACK_HIST0_21_R_POS) -#define DSP2_BLBACK_HIST0_21_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_21_R_LEN) - 1) << DSP2_BLBACK_HIST0_21_R_POS)) - -/* 0xA58 : REG_HIST0_22 */ -#define DSP2_BLBACK_REG_HIST0_22_OFFSET (0xA58) -#define DSP2_BLBACK_HIST0_22_R DSP2_BLBACK_HIST0_22_R -#define DSP2_BLBACK_HIST0_22_R_POS (0U) -#define DSP2_BLBACK_HIST0_22_R_LEN (24U) -#define DSP2_BLBACK_HIST0_22_R_MSK (((1U << DSP2_BLBACK_HIST0_22_R_LEN) - 1) << DSP2_BLBACK_HIST0_22_R_POS) -#define DSP2_BLBACK_HIST0_22_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_22_R_LEN) - 1) << DSP2_BLBACK_HIST0_22_R_POS)) - -/* 0xA5C : REG_HIST0_23 */ -#define DSP2_BLBACK_REG_HIST0_23_OFFSET (0xA5C) -#define DSP2_BLBACK_HIST0_23_R DSP2_BLBACK_HIST0_23_R -#define DSP2_BLBACK_HIST0_23_R_POS (0U) -#define DSP2_BLBACK_HIST0_23_R_LEN (24U) -#define DSP2_BLBACK_HIST0_23_R_MSK (((1U << DSP2_BLBACK_HIST0_23_R_LEN) - 1) << DSP2_BLBACK_HIST0_23_R_POS) -#define DSP2_BLBACK_HIST0_23_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_23_R_LEN) - 1) << DSP2_BLBACK_HIST0_23_R_POS)) - -/* 0xA60 : REG_HIST0_24 */ -#define DSP2_BLBACK_REG_HIST0_24_OFFSET (0xA60) -#define DSP2_BLBACK_HIST0_24_R DSP2_BLBACK_HIST0_24_R -#define DSP2_BLBACK_HIST0_24_R_POS (0U) -#define DSP2_BLBACK_HIST0_24_R_LEN (24U) -#define DSP2_BLBACK_HIST0_24_R_MSK (((1U << DSP2_BLBACK_HIST0_24_R_LEN) - 1) << DSP2_BLBACK_HIST0_24_R_POS) -#define DSP2_BLBACK_HIST0_24_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_24_R_LEN) - 1) << DSP2_BLBACK_HIST0_24_R_POS)) - -/* 0xA64 : REG_HIST0_25 */ -#define DSP2_BLBACK_REG_HIST0_25_OFFSET (0xA64) -#define DSP2_BLBACK_HIST0_25_R DSP2_BLBACK_HIST0_25_R -#define DSP2_BLBACK_HIST0_25_R_POS (0U) -#define DSP2_BLBACK_HIST0_25_R_LEN (24U) -#define DSP2_BLBACK_HIST0_25_R_MSK (((1U << DSP2_BLBACK_HIST0_25_R_LEN) - 1) << DSP2_BLBACK_HIST0_25_R_POS) -#define DSP2_BLBACK_HIST0_25_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_25_R_LEN) - 1) << DSP2_BLBACK_HIST0_25_R_POS)) - -/* 0xA68 : REG_HIST0_26 */ -#define DSP2_BLBACK_REG_HIST0_26_OFFSET (0xA68) -#define DSP2_BLBACK_HIST0_26_R DSP2_BLBACK_HIST0_26_R -#define DSP2_BLBACK_HIST0_26_R_POS (0U) -#define DSP2_BLBACK_HIST0_26_R_LEN (24U) -#define DSP2_BLBACK_HIST0_26_R_MSK (((1U << DSP2_BLBACK_HIST0_26_R_LEN) - 1) << DSP2_BLBACK_HIST0_26_R_POS) -#define DSP2_BLBACK_HIST0_26_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_26_R_LEN) - 1) << DSP2_BLBACK_HIST0_26_R_POS)) - -/* 0xA6C : REG_HIST0_27 */ -#define DSP2_BLBACK_REG_HIST0_27_OFFSET (0xA6C) -#define DSP2_BLBACK_HIST0_27_R DSP2_BLBACK_HIST0_27_R -#define DSP2_BLBACK_HIST0_27_R_POS (0U) -#define DSP2_BLBACK_HIST0_27_R_LEN (24U) -#define DSP2_BLBACK_HIST0_27_R_MSK (((1U << DSP2_BLBACK_HIST0_27_R_LEN) - 1) << DSP2_BLBACK_HIST0_27_R_POS) -#define DSP2_BLBACK_HIST0_27_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_27_R_LEN) - 1) << DSP2_BLBACK_HIST0_27_R_POS)) - -/* 0xA70 : REG_HIST0_28 */ -#define DSP2_BLBACK_REG_HIST0_28_OFFSET (0xA70) -#define DSP2_BLBACK_HIST0_28_R DSP2_BLBACK_HIST0_28_R -#define DSP2_BLBACK_HIST0_28_R_POS (0U) -#define DSP2_BLBACK_HIST0_28_R_LEN (24U) -#define DSP2_BLBACK_HIST0_28_R_MSK (((1U << DSP2_BLBACK_HIST0_28_R_LEN) - 1) << DSP2_BLBACK_HIST0_28_R_POS) -#define DSP2_BLBACK_HIST0_28_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_28_R_LEN) - 1) << DSP2_BLBACK_HIST0_28_R_POS)) - -/* 0xA74 : REG_HIST0_29 */ -#define DSP2_BLBACK_REG_HIST0_29_OFFSET (0xA74) -#define DSP2_BLBACK_HIST0_29_R DSP2_BLBACK_HIST0_29_R -#define DSP2_BLBACK_HIST0_29_R_POS (0U) -#define DSP2_BLBACK_HIST0_29_R_LEN (24U) -#define DSP2_BLBACK_HIST0_29_R_MSK (((1U << DSP2_BLBACK_HIST0_29_R_LEN) - 1) << DSP2_BLBACK_HIST0_29_R_POS) -#define DSP2_BLBACK_HIST0_29_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_29_R_LEN) - 1) << DSP2_BLBACK_HIST0_29_R_POS)) - -/* 0xA78 : REG_HIST0_30 */ -#define DSP2_BLBACK_REG_HIST0_30_OFFSET (0xA78) -#define DSP2_BLBACK_HIST0_30_R DSP2_BLBACK_HIST0_30_R -#define DSP2_BLBACK_HIST0_30_R_POS (0U) -#define DSP2_BLBACK_HIST0_30_R_LEN (24U) -#define DSP2_BLBACK_HIST0_30_R_MSK (((1U << DSP2_BLBACK_HIST0_30_R_LEN) - 1) << DSP2_BLBACK_HIST0_30_R_POS) -#define DSP2_BLBACK_HIST0_30_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_30_R_LEN) - 1) << DSP2_BLBACK_HIST0_30_R_POS)) - -/* 0xA7C : REG_HIST0_31 */ -#define DSP2_BLBACK_REG_HIST0_31_OFFSET (0xA7C) -#define DSP2_BLBACK_HIST0_31_R DSP2_BLBACK_HIST0_31_R -#define DSP2_BLBACK_HIST0_31_R_POS (0U) -#define DSP2_BLBACK_HIST0_31_R_LEN (24U) -#define DSP2_BLBACK_HIST0_31_R_MSK (((1U << DSP2_BLBACK_HIST0_31_R_LEN) - 1) << DSP2_BLBACK_HIST0_31_R_POS) -#define DSP2_BLBACK_HIST0_31_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_31_R_LEN) - 1) << DSP2_BLBACK_HIST0_31_R_POS)) - -/* 0xA80 : REG_HIST0_32 */ -#define DSP2_BLBACK_REG_HIST0_32_OFFSET (0xA80) -#define DSP2_BLBACK_HIST0_32_R DSP2_BLBACK_HIST0_32_R -#define DSP2_BLBACK_HIST0_32_R_POS (0U) -#define DSP2_BLBACK_HIST0_32_R_LEN (24U) -#define DSP2_BLBACK_HIST0_32_R_MSK (((1U << DSP2_BLBACK_HIST0_32_R_LEN) - 1) << DSP2_BLBACK_HIST0_32_R_POS) -#define DSP2_BLBACK_HIST0_32_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_32_R_LEN) - 1) << DSP2_BLBACK_HIST0_32_R_POS)) - -/* 0xA84 : REG_HIST0_33 */ -#define DSP2_BLBACK_REG_HIST0_33_OFFSET (0xA84) -#define DSP2_BLBACK_HIST0_33_R DSP2_BLBACK_HIST0_33_R -#define DSP2_BLBACK_HIST0_33_R_POS (0U) -#define DSP2_BLBACK_HIST0_33_R_LEN (24U) -#define DSP2_BLBACK_HIST0_33_R_MSK (((1U << DSP2_BLBACK_HIST0_33_R_LEN) - 1) << DSP2_BLBACK_HIST0_33_R_POS) -#define DSP2_BLBACK_HIST0_33_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_33_R_LEN) - 1) << DSP2_BLBACK_HIST0_33_R_POS)) - -/* 0xA88 : REG_HIST0_34 */ -#define DSP2_BLBACK_REG_HIST0_34_OFFSET (0xA88) -#define DSP2_BLBACK_HIST0_34_R DSP2_BLBACK_HIST0_34_R -#define DSP2_BLBACK_HIST0_34_R_POS (0U) -#define DSP2_BLBACK_HIST0_34_R_LEN (24U) -#define DSP2_BLBACK_HIST0_34_R_MSK (((1U << DSP2_BLBACK_HIST0_34_R_LEN) - 1) << DSP2_BLBACK_HIST0_34_R_POS) -#define DSP2_BLBACK_HIST0_34_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_34_R_LEN) - 1) << DSP2_BLBACK_HIST0_34_R_POS)) - -/* 0xA8C : REG_HIST0_35 */ -#define DSP2_BLBACK_REG_HIST0_35_OFFSET (0xA8C) -#define DSP2_BLBACK_HIST0_35_R DSP2_BLBACK_HIST0_35_R -#define DSP2_BLBACK_HIST0_35_R_POS (0U) -#define DSP2_BLBACK_HIST0_35_R_LEN (24U) -#define DSP2_BLBACK_HIST0_35_R_MSK (((1U << DSP2_BLBACK_HIST0_35_R_LEN) - 1) << DSP2_BLBACK_HIST0_35_R_POS) -#define DSP2_BLBACK_HIST0_35_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_35_R_LEN) - 1) << DSP2_BLBACK_HIST0_35_R_POS)) - -/* 0xA90 : REG_HIST0_36 */ -#define DSP2_BLBACK_REG_HIST0_36_OFFSET (0xA90) -#define DSP2_BLBACK_HIST0_36_R DSP2_BLBACK_HIST0_36_R -#define DSP2_BLBACK_HIST0_36_R_POS (0U) -#define DSP2_BLBACK_HIST0_36_R_LEN (24U) -#define DSP2_BLBACK_HIST0_36_R_MSK (((1U << DSP2_BLBACK_HIST0_36_R_LEN) - 1) << DSP2_BLBACK_HIST0_36_R_POS) -#define DSP2_BLBACK_HIST0_36_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_36_R_LEN) - 1) << DSP2_BLBACK_HIST0_36_R_POS)) - -/* 0xA94 : REG_HIST0_37 */ -#define DSP2_BLBACK_REG_HIST0_37_OFFSET (0xA94) -#define DSP2_BLBACK_HIST0_37_R DSP2_BLBACK_HIST0_37_R -#define DSP2_BLBACK_HIST0_37_R_POS (0U) -#define DSP2_BLBACK_HIST0_37_R_LEN (24U) -#define DSP2_BLBACK_HIST0_37_R_MSK (((1U << DSP2_BLBACK_HIST0_37_R_LEN) - 1) << DSP2_BLBACK_HIST0_37_R_POS) -#define DSP2_BLBACK_HIST0_37_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_37_R_LEN) - 1) << DSP2_BLBACK_HIST0_37_R_POS)) - -/* 0xA98 : REG_HIST0_38 */ -#define DSP2_BLBACK_REG_HIST0_38_OFFSET (0xA98) -#define DSP2_BLBACK_HIST0_38_R DSP2_BLBACK_HIST0_38_R -#define DSP2_BLBACK_HIST0_38_R_POS (0U) -#define DSP2_BLBACK_HIST0_38_R_LEN (24U) -#define DSP2_BLBACK_HIST0_38_R_MSK (((1U << DSP2_BLBACK_HIST0_38_R_LEN) - 1) << DSP2_BLBACK_HIST0_38_R_POS) -#define DSP2_BLBACK_HIST0_38_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_38_R_LEN) - 1) << DSP2_BLBACK_HIST0_38_R_POS)) - -/* 0xA9C : REG_HIST0_39 */ -#define DSP2_BLBACK_REG_HIST0_39_OFFSET (0xA9C) -#define DSP2_BLBACK_HIST0_39_R DSP2_BLBACK_HIST0_39_R -#define DSP2_BLBACK_HIST0_39_R_POS (0U) -#define DSP2_BLBACK_HIST0_39_R_LEN (24U) -#define DSP2_BLBACK_HIST0_39_R_MSK (((1U << DSP2_BLBACK_HIST0_39_R_LEN) - 1) << DSP2_BLBACK_HIST0_39_R_POS) -#define DSP2_BLBACK_HIST0_39_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_39_R_LEN) - 1) << DSP2_BLBACK_HIST0_39_R_POS)) - -/* 0xAA0 : REG_HIST0_40 */ -#define DSP2_BLBACK_REG_HIST0_40_OFFSET (0xAA0) -#define DSP2_BLBACK_HIST0_40_R DSP2_BLBACK_HIST0_40_R -#define DSP2_BLBACK_HIST0_40_R_POS (0U) -#define DSP2_BLBACK_HIST0_40_R_LEN (24U) -#define DSP2_BLBACK_HIST0_40_R_MSK (((1U << DSP2_BLBACK_HIST0_40_R_LEN) - 1) << DSP2_BLBACK_HIST0_40_R_POS) -#define DSP2_BLBACK_HIST0_40_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_40_R_LEN) - 1) << DSP2_BLBACK_HIST0_40_R_POS)) - -/* 0xAA4 : REG_HIST0_41 */ -#define DSP2_BLBACK_REG_HIST0_41_OFFSET (0xAA4) -#define DSP2_BLBACK_HIST0_41_R DSP2_BLBACK_HIST0_41_R -#define DSP2_BLBACK_HIST0_41_R_POS (0U) -#define DSP2_BLBACK_HIST0_41_R_LEN (24U) -#define DSP2_BLBACK_HIST0_41_R_MSK (((1U << DSP2_BLBACK_HIST0_41_R_LEN) - 1) << DSP2_BLBACK_HIST0_41_R_POS) -#define DSP2_BLBACK_HIST0_41_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_41_R_LEN) - 1) << DSP2_BLBACK_HIST0_41_R_POS)) - -/* 0xAA8 : REG_HIST0_42 */ -#define DSP2_BLBACK_REG_HIST0_42_OFFSET (0xAA8) -#define DSP2_BLBACK_HIST0_42_R DSP2_BLBACK_HIST0_42_R -#define DSP2_BLBACK_HIST0_42_R_POS (0U) -#define DSP2_BLBACK_HIST0_42_R_LEN (24U) -#define DSP2_BLBACK_HIST0_42_R_MSK (((1U << DSP2_BLBACK_HIST0_42_R_LEN) - 1) << DSP2_BLBACK_HIST0_42_R_POS) -#define DSP2_BLBACK_HIST0_42_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_42_R_LEN) - 1) << DSP2_BLBACK_HIST0_42_R_POS)) - -/* 0xAAC : REG_HIST0_43 */ -#define DSP2_BLBACK_REG_HIST0_43_OFFSET (0xAAC) -#define DSP2_BLBACK_HIST0_43_R DSP2_BLBACK_HIST0_43_R -#define DSP2_BLBACK_HIST0_43_R_POS (0U) -#define DSP2_BLBACK_HIST0_43_R_LEN (24U) -#define DSP2_BLBACK_HIST0_43_R_MSK (((1U << DSP2_BLBACK_HIST0_43_R_LEN) - 1) << DSP2_BLBACK_HIST0_43_R_POS) -#define DSP2_BLBACK_HIST0_43_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_43_R_LEN) - 1) << DSP2_BLBACK_HIST0_43_R_POS)) - -/* 0xAB0 : REG_HIST0_44 */ -#define DSP2_BLBACK_REG_HIST0_44_OFFSET (0xAB0) -#define DSP2_BLBACK_HIST0_44_R DSP2_BLBACK_HIST0_44_R -#define DSP2_BLBACK_HIST0_44_R_POS (0U) -#define DSP2_BLBACK_HIST0_44_R_LEN (24U) -#define DSP2_BLBACK_HIST0_44_R_MSK (((1U << DSP2_BLBACK_HIST0_44_R_LEN) - 1) << DSP2_BLBACK_HIST0_44_R_POS) -#define DSP2_BLBACK_HIST0_44_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_44_R_LEN) - 1) << DSP2_BLBACK_HIST0_44_R_POS)) - -/* 0xAB4 : REG_HIST0_45 */ -#define DSP2_BLBACK_REG_HIST0_45_OFFSET (0xAB4) -#define DSP2_BLBACK_HIST0_45_R DSP2_BLBACK_HIST0_45_R -#define DSP2_BLBACK_HIST0_45_R_POS (0U) -#define DSP2_BLBACK_HIST0_45_R_LEN (24U) -#define DSP2_BLBACK_HIST0_45_R_MSK (((1U << DSP2_BLBACK_HIST0_45_R_LEN) - 1) << DSP2_BLBACK_HIST0_45_R_POS) -#define DSP2_BLBACK_HIST0_45_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_45_R_LEN) - 1) << DSP2_BLBACK_HIST0_45_R_POS)) - -/* 0xAB8 : REG_HIST0_46 */ -#define DSP2_BLBACK_REG_HIST0_46_OFFSET (0xAB8) -#define DSP2_BLBACK_HIST0_46_R DSP2_BLBACK_HIST0_46_R -#define DSP2_BLBACK_HIST0_46_R_POS (0U) -#define DSP2_BLBACK_HIST0_46_R_LEN (24U) -#define DSP2_BLBACK_HIST0_46_R_MSK (((1U << DSP2_BLBACK_HIST0_46_R_LEN) - 1) << DSP2_BLBACK_HIST0_46_R_POS) -#define DSP2_BLBACK_HIST0_46_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_46_R_LEN) - 1) << DSP2_BLBACK_HIST0_46_R_POS)) - -/* 0xABC : REG_HIST0_47 */ -#define DSP2_BLBACK_REG_HIST0_47_OFFSET (0xABC) -#define DSP2_BLBACK_HIST0_47_R DSP2_BLBACK_HIST0_47_R -#define DSP2_BLBACK_HIST0_47_R_POS (0U) -#define DSP2_BLBACK_HIST0_47_R_LEN (24U) -#define DSP2_BLBACK_HIST0_47_R_MSK (((1U << DSP2_BLBACK_HIST0_47_R_LEN) - 1) << DSP2_BLBACK_HIST0_47_R_POS) -#define DSP2_BLBACK_HIST0_47_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_47_R_LEN) - 1) << DSP2_BLBACK_HIST0_47_R_POS)) - -/* 0xAC0 : REG_HIST0_48 */ -#define DSP2_BLBACK_REG_HIST0_48_OFFSET (0xAC0) -#define DSP2_BLBACK_HIST0_48_R DSP2_BLBACK_HIST0_48_R -#define DSP2_BLBACK_HIST0_48_R_POS (0U) -#define DSP2_BLBACK_HIST0_48_R_LEN (24U) -#define DSP2_BLBACK_HIST0_48_R_MSK (((1U << DSP2_BLBACK_HIST0_48_R_LEN) - 1) << DSP2_BLBACK_HIST0_48_R_POS) -#define DSP2_BLBACK_HIST0_48_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_48_R_LEN) - 1) << DSP2_BLBACK_HIST0_48_R_POS)) - -/* 0xAC4 : REG_HIST0_49 */ -#define DSP2_BLBACK_REG_HIST0_49_OFFSET (0xAC4) -#define DSP2_BLBACK_HIST0_49_R DSP2_BLBACK_HIST0_49_R -#define DSP2_BLBACK_HIST0_49_R_POS (0U) -#define DSP2_BLBACK_HIST0_49_R_LEN (24U) -#define DSP2_BLBACK_HIST0_49_R_MSK (((1U << DSP2_BLBACK_HIST0_49_R_LEN) - 1) << DSP2_BLBACK_HIST0_49_R_POS) -#define DSP2_BLBACK_HIST0_49_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_49_R_LEN) - 1) << DSP2_BLBACK_HIST0_49_R_POS)) - -/* 0xAC8 : REG_HIST0_50 */ -#define DSP2_BLBACK_REG_HIST0_50_OFFSET (0xAC8) -#define DSP2_BLBACK_HIST0_50_R DSP2_BLBACK_HIST0_50_R -#define DSP2_BLBACK_HIST0_50_R_POS (0U) -#define DSP2_BLBACK_HIST0_50_R_LEN (24U) -#define DSP2_BLBACK_HIST0_50_R_MSK (((1U << DSP2_BLBACK_HIST0_50_R_LEN) - 1) << DSP2_BLBACK_HIST0_50_R_POS) -#define DSP2_BLBACK_HIST0_50_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_50_R_LEN) - 1) << DSP2_BLBACK_HIST0_50_R_POS)) - -/* 0xACC : REG_HIST0_51 */ -#define DSP2_BLBACK_REG_HIST0_51_OFFSET (0xACC) -#define DSP2_BLBACK_HIST0_51_R DSP2_BLBACK_HIST0_51_R -#define DSP2_BLBACK_HIST0_51_R_POS (0U) -#define DSP2_BLBACK_HIST0_51_R_LEN (24U) -#define DSP2_BLBACK_HIST0_51_R_MSK (((1U << DSP2_BLBACK_HIST0_51_R_LEN) - 1) << DSP2_BLBACK_HIST0_51_R_POS) -#define DSP2_BLBACK_HIST0_51_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_51_R_LEN) - 1) << DSP2_BLBACK_HIST0_51_R_POS)) - -/* 0xAD0 : REG_HIST0_52 */ -#define DSP2_BLBACK_REG_HIST0_52_OFFSET (0xAD0) -#define DSP2_BLBACK_HIST0_52_R DSP2_BLBACK_HIST0_52_R -#define DSP2_BLBACK_HIST0_52_R_POS (0U) -#define DSP2_BLBACK_HIST0_52_R_LEN (24U) -#define DSP2_BLBACK_HIST0_52_R_MSK (((1U << DSP2_BLBACK_HIST0_52_R_LEN) - 1) << DSP2_BLBACK_HIST0_52_R_POS) -#define DSP2_BLBACK_HIST0_52_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_52_R_LEN) - 1) << DSP2_BLBACK_HIST0_52_R_POS)) - -/* 0xAD4 : REG_HIST0_53 */ -#define DSP2_BLBACK_REG_HIST0_53_OFFSET (0xAD4) -#define DSP2_BLBACK_HIST0_53_R DSP2_BLBACK_HIST0_53_R -#define DSP2_BLBACK_HIST0_53_R_POS (0U) -#define DSP2_BLBACK_HIST0_53_R_LEN (24U) -#define DSP2_BLBACK_HIST0_53_R_MSK (((1U << DSP2_BLBACK_HIST0_53_R_LEN) - 1) << DSP2_BLBACK_HIST0_53_R_POS) -#define DSP2_BLBACK_HIST0_53_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_53_R_LEN) - 1) << DSP2_BLBACK_HIST0_53_R_POS)) - -/* 0xAD8 : REG_HIST0_54 */ -#define DSP2_BLBACK_REG_HIST0_54_OFFSET (0xAD8) -#define DSP2_BLBACK_HIST0_54_R DSP2_BLBACK_HIST0_54_R -#define DSP2_BLBACK_HIST0_54_R_POS (0U) -#define DSP2_BLBACK_HIST0_54_R_LEN (24U) -#define DSP2_BLBACK_HIST0_54_R_MSK (((1U << DSP2_BLBACK_HIST0_54_R_LEN) - 1) << DSP2_BLBACK_HIST0_54_R_POS) -#define DSP2_BLBACK_HIST0_54_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_54_R_LEN) - 1) << DSP2_BLBACK_HIST0_54_R_POS)) - -/* 0xADC : REG_HIST0_55 */ -#define DSP2_BLBACK_REG_HIST0_55_OFFSET (0xADC) -#define DSP2_BLBACK_HIST0_55_R DSP2_BLBACK_HIST0_55_R -#define DSP2_BLBACK_HIST0_55_R_POS (0U) -#define DSP2_BLBACK_HIST0_55_R_LEN (24U) -#define DSP2_BLBACK_HIST0_55_R_MSK (((1U << DSP2_BLBACK_HIST0_55_R_LEN) - 1) << DSP2_BLBACK_HIST0_55_R_POS) -#define DSP2_BLBACK_HIST0_55_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_55_R_LEN) - 1) << DSP2_BLBACK_HIST0_55_R_POS)) - -/* 0xAE0 : REG_HIST0_56 */ -#define DSP2_BLBACK_REG_HIST0_56_OFFSET (0xAE0) -#define DSP2_BLBACK_HIST0_56_R DSP2_BLBACK_HIST0_56_R -#define DSP2_BLBACK_HIST0_56_R_POS (0U) -#define DSP2_BLBACK_HIST0_56_R_LEN (24U) -#define DSP2_BLBACK_HIST0_56_R_MSK (((1U << DSP2_BLBACK_HIST0_56_R_LEN) - 1) << DSP2_BLBACK_HIST0_56_R_POS) -#define DSP2_BLBACK_HIST0_56_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_56_R_LEN) - 1) << DSP2_BLBACK_HIST0_56_R_POS)) - -/* 0xAE4 : REG_HIST0_57 */ -#define DSP2_BLBACK_REG_HIST0_57_OFFSET (0xAE4) -#define DSP2_BLBACK_HIST0_57_R DSP2_BLBACK_HIST0_57_R -#define DSP2_BLBACK_HIST0_57_R_POS (0U) -#define DSP2_BLBACK_HIST0_57_R_LEN (24U) -#define DSP2_BLBACK_HIST0_57_R_MSK (((1U << DSP2_BLBACK_HIST0_57_R_LEN) - 1) << DSP2_BLBACK_HIST0_57_R_POS) -#define DSP2_BLBACK_HIST0_57_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_57_R_LEN) - 1) << DSP2_BLBACK_HIST0_57_R_POS)) - -/* 0xAE8 : REG_HIST0_58 */ -#define DSP2_BLBACK_REG_HIST0_58_OFFSET (0xAE8) -#define DSP2_BLBACK_HIST0_58_R DSP2_BLBACK_HIST0_58_R -#define DSP2_BLBACK_HIST0_58_R_POS (0U) -#define DSP2_BLBACK_HIST0_58_R_LEN (24U) -#define DSP2_BLBACK_HIST0_58_R_MSK (((1U << DSP2_BLBACK_HIST0_58_R_LEN) - 1) << DSP2_BLBACK_HIST0_58_R_POS) -#define DSP2_BLBACK_HIST0_58_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_58_R_LEN) - 1) << DSP2_BLBACK_HIST0_58_R_POS)) - -/* 0xAEC : REG_HIST0_59 */ -#define DSP2_BLBACK_REG_HIST0_59_OFFSET (0xAEC) -#define DSP2_BLBACK_HIST0_59_R DSP2_BLBACK_HIST0_59_R -#define DSP2_BLBACK_HIST0_59_R_POS (0U) -#define DSP2_BLBACK_HIST0_59_R_LEN (24U) -#define DSP2_BLBACK_HIST0_59_R_MSK (((1U << DSP2_BLBACK_HIST0_59_R_LEN) - 1) << DSP2_BLBACK_HIST0_59_R_POS) -#define DSP2_BLBACK_HIST0_59_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_59_R_LEN) - 1) << DSP2_BLBACK_HIST0_59_R_POS)) - -/* 0xAF0 : REG_HIST0_60 */ -#define DSP2_BLBACK_REG_HIST0_60_OFFSET (0xAF0) -#define DSP2_BLBACK_HIST0_60_R DSP2_BLBACK_HIST0_60_R -#define DSP2_BLBACK_HIST0_60_R_POS (0U) -#define DSP2_BLBACK_HIST0_60_R_LEN (24U) -#define DSP2_BLBACK_HIST0_60_R_MSK (((1U << DSP2_BLBACK_HIST0_60_R_LEN) - 1) << DSP2_BLBACK_HIST0_60_R_POS) -#define DSP2_BLBACK_HIST0_60_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_60_R_LEN) - 1) << DSP2_BLBACK_HIST0_60_R_POS)) - -/* 0xAF4 : REG_HIST0_61 */ -#define DSP2_BLBACK_REG_HIST0_61_OFFSET (0xAF4) -#define DSP2_BLBACK_HIST0_61_R DSP2_BLBACK_HIST0_61_R -#define DSP2_BLBACK_HIST0_61_R_POS (0U) -#define DSP2_BLBACK_HIST0_61_R_LEN (24U) -#define DSP2_BLBACK_HIST0_61_R_MSK (((1U << DSP2_BLBACK_HIST0_61_R_LEN) - 1) << DSP2_BLBACK_HIST0_61_R_POS) -#define DSP2_BLBACK_HIST0_61_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_61_R_LEN) - 1) << DSP2_BLBACK_HIST0_61_R_POS)) - -/* 0xAF8 : REG_HIST0_62 */ -#define DSP2_BLBACK_REG_HIST0_62_OFFSET (0xAF8) -#define DSP2_BLBACK_HIST0_62_R DSP2_BLBACK_HIST0_62_R -#define DSP2_BLBACK_HIST0_62_R_POS (0U) -#define DSP2_BLBACK_HIST0_62_R_LEN (24U) -#define DSP2_BLBACK_HIST0_62_R_MSK (((1U << DSP2_BLBACK_HIST0_62_R_LEN) - 1) << DSP2_BLBACK_HIST0_62_R_POS) -#define DSP2_BLBACK_HIST0_62_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_62_R_LEN) - 1) << DSP2_BLBACK_HIST0_62_R_POS)) - -/* 0xAFC : REG_HIST0_63 */ -#define DSP2_BLBACK_REG_HIST0_63_OFFSET (0xAFC) -#define DSP2_BLBACK_HIST0_63_R DSP2_BLBACK_HIST0_63_R -#define DSP2_BLBACK_HIST0_63_R_POS (0U) -#define DSP2_BLBACK_HIST0_63_R_LEN (24U) -#define DSP2_BLBACK_HIST0_63_R_MSK (((1U << DSP2_BLBACK_HIST0_63_R_LEN) - 1) << DSP2_BLBACK_HIST0_63_R_POS) -#define DSP2_BLBACK_HIST0_63_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_63_R_LEN) - 1) << DSP2_BLBACK_HIST0_63_R_POS)) - -/* 0xB00 : REG_HIST1_0 */ -#define DSP2_BLBACK_REG_HIST1_0_OFFSET (0xB00) -#define DSP2_BLBACK_HIST1_0_R DSP2_BLBACK_HIST1_0_R -#define DSP2_BLBACK_HIST1_0_R_POS (0U) -#define DSP2_BLBACK_HIST1_0_R_LEN (24U) -#define DSP2_BLBACK_HIST1_0_R_MSK (((1U << DSP2_BLBACK_HIST1_0_R_LEN) - 1) << DSP2_BLBACK_HIST1_0_R_POS) -#define DSP2_BLBACK_HIST1_0_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_0_R_LEN) - 1) << DSP2_BLBACK_HIST1_0_R_POS)) - -/* 0xB04 : REG_HIST1_1 */ -#define DSP2_BLBACK_REG_HIST1_1_OFFSET (0xB04) -#define DSP2_BLBACK_HIST1_1_R DSP2_BLBACK_HIST1_1_R -#define DSP2_BLBACK_HIST1_1_R_POS (0U) -#define DSP2_BLBACK_HIST1_1_R_LEN (24U) -#define DSP2_BLBACK_HIST1_1_R_MSK (((1U << DSP2_BLBACK_HIST1_1_R_LEN) - 1) << DSP2_BLBACK_HIST1_1_R_POS) -#define DSP2_BLBACK_HIST1_1_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_1_R_LEN) - 1) << DSP2_BLBACK_HIST1_1_R_POS)) - -/* 0xB08 : REG_HIST1_2 */ -#define DSP2_BLBACK_REG_HIST1_2_OFFSET (0xB08) -#define DSP2_BLBACK_HIST1_2_R DSP2_BLBACK_HIST1_2_R -#define DSP2_BLBACK_HIST1_2_R_POS (0U) -#define DSP2_BLBACK_HIST1_2_R_LEN (24U) -#define DSP2_BLBACK_HIST1_2_R_MSK (((1U << DSP2_BLBACK_HIST1_2_R_LEN) - 1) << DSP2_BLBACK_HIST1_2_R_POS) -#define DSP2_BLBACK_HIST1_2_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_2_R_LEN) - 1) << DSP2_BLBACK_HIST1_2_R_POS)) - -/* 0xB0C : REG_HIST1_3 */ -#define DSP2_BLBACK_REG_HIST1_3_OFFSET (0xB0C) -#define DSP2_BLBACK_HIST1_3_R DSP2_BLBACK_HIST1_3_R -#define DSP2_BLBACK_HIST1_3_R_POS (0U) -#define DSP2_BLBACK_HIST1_3_R_LEN (24U) -#define DSP2_BLBACK_HIST1_3_R_MSK (((1U << DSP2_BLBACK_HIST1_3_R_LEN) - 1) << DSP2_BLBACK_HIST1_3_R_POS) -#define DSP2_BLBACK_HIST1_3_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_3_R_LEN) - 1) << DSP2_BLBACK_HIST1_3_R_POS)) - -/* 0xB10 : REG_HIST1_4 */ -#define DSP2_BLBACK_REG_HIST1_4_OFFSET (0xB10) -#define DSP2_BLBACK_HIST1_4_R DSP2_BLBACK_HIST1_4_R -#define DSP2_BLBACK_HIST1_4_R_POS (0U) -#define DSP2_BLBACK_HIST1_4_R_LEN (24U) -#define DSP2_BLBACK_HIST1_4_R_MSK (((1U << DSP2_BLBACK_HIST1_4_R_LEN) - 1) << DSP2_BLBACK_HIST1_4_R_POS) -#define DSP2_BLBACK_HIST1_4_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_4_R_LEN) - 1) << DSP2_BLBACK_HIST1_4_R_POS)) - -/* 0xB14 : REG_HIST1_5 */ -#define DSP2_BLBACK_REG_HIST1_5_OFFSET (0xB14) -#define DSP2_BLBACK_HIST1_5_R DSP2_BLBACK_HIST1_5_R -#define DSP2_BLBACK_HIST1_5_R_POS (0U) -#define DSP2_BLBACK_HIST1_5_R_LEN (24U) -#define DSP2_BLBACK_HIST1_5_R_MSK (((1U << DSP2_BLBACK_HIST1_5_R_LEN) - 1) << DSP2_BLBACK_HIST1_5_R_POS) -#define DSP2_BLBACK_HIST1_5_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_5_R_LEN) - 1) << DSP2_BLBACK_HIST1_5_R_POS)) - -/* 0xB18 : REG_HIST1_6 */ -#define DSP2_BLBACK_REG_HIST1_6_OFFSET (0xB18) -#define DSP2_BLBACK_HIST1_6_R DSP2_BLBACK_HIST1_6_R -#define DSP2_BLBACK_HIST1_6_R_POS (0U) -#define DSP2_BLBACK_HIST1_6_R_LEN (24U) -#define DSP2_BLBACK_HIST1_6_R_MSK (((1U << DSP2_BLBACK_HIST1_6_R_LEN) - 1) << DSP2_BLBACK_HIST1_6_R_POS) -#define DSP2_BLBACK_HIST1_6_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_6_R_LEN) - 1) << DSP2_BLBACK_HIST1_6_R_POS)) - -/* 0xB1C : REG_HIST1_7 */ -#define DSP2_BLBACK_REG_HIST1_7_OFFSET (0xB1C) -#define DSP2_BLBACK_HIST1_7_R DSP2_BLBACK_HIST1_7_R -#define DSP2_BLBACK_HIST1_7_R_POS (0U) -#define DSP2_BLBACK_HIST1_7_R_LEN (24U) -#define DSP2_BLBACK_HIST1_7_R_MSK (((1U << DSP2_BLBACK_HIST1_7_R_LEN) - 1) << DSP2_BLBACK_HIST1_7_R_POS) -#define DSP2_BLBACK_HIST1_7_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_7_R_LEN) - 1) << DSP2_BLBACK_HIST1_7_R_POS)) - -/* 0xB20 : REG_HIST1_8 */ -#define DSP2_BLBACK_REG_HIST1_8_OFFSET (0xB20) -#define DSP2_BLBACK_HIST1_8_R DSP2_BLBACK_HIST1_8_R -#define DSP2_BLBACK_HIST1_8_R_POS (0U) -#define DSP2_BLBACK_HIST1_8_R_LEN (24U) -#define DSP2_BLBACK_HIST1_8_R_MSK (((1U << DSP2_BLBACK_HIST1_8_R_LEN) - 1) << DSP2_BLBACK_HIST1_8_R_POS) -#define DSP2_BLBACK_HIST1_8_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_8_R_LEN) - 1) << DSP2_BLBACK_HIST1_8_R_POS)) - -/* 0xB24 : REG_HIST1_9 */ -#define DSP2_BLBACK_REG_HIST1_9_OFFSET (0xB24) -#define DSP2_BLBACK_HIST1_9_R DSP2_BLBACK_HIST1_9_R -#define DSP2_BLBACK_HIST1_9_R_POS (0U) -#define DSP2_BLBACK_HIST1_9_R_LEN (24U) -#define DSP2_BLBACK_HIST1_9_R_MSK (((1U << DSP2_BLBACK_HIST1_9_R_LEN) - 1) << DSP2_BLBACK_HIST1_9_R_POS) -#define DSP2_BLBACK_HIST1_9_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_9_R_LEN) - 1) << DSP2_BLBACK_HIST1_9_R_POS)) - -/* 0xB28 : REG_HIST1_10 */ -#define DSP2_BLBACK_REG_HIST1_10_OFFSET (0xB28) -#define DSP2_BLBACK_HIST1_10_R DSP2_BLBACK_HIST1_10_R -#define DSP2_BLBACK_HIST1_10_R_POS (0U) -#define DSP2_BLBACK_HIST1_10_R_LEN (24U) -#define DSP2_BLBACK_HIST1_10_R_MSK (((1U << DSP2_BLBACK_HIST1_10_R_LEN) - 1) << DSP2_BLBACK_HIST1_10_R_POS) -#define DSP2_BLBACK_HIST1_10_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_10_R_LEN) - 1) << DSP2_BLBACK_HIST1_10_R_POS)) - -/* 0xB2C : REG_HIST1_11 */ -#define DSP2_BLBACK_REG_HIST1_11_OFFSET (0xB2C) -#define DSP2_BLBACK_HIST1_11_R DSP2_BLBACK_HIST1_11_R -#define DSP2_BLBACK_HIST1_11_R_POS (0U) -#define DSP2_BLBACK_HIST1_11_R_LEN (24U) -#define DSP2_BLBACK_HIST1_11_R_MSK (((1U << DSP2_BLBACK_HIST1_11_R_LEN) - 1) << DSP2_BLBACK_HIST1_11_R_POS) -#define DSP2_BLBACK_HIST1_11_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_11_R_LEN) - 1) << DSP2_BLBACK_HIST1_11_R_POS)) - -/* 0xB30 : REG_HIST1_12 */ -#define DSP2_BLBACK_REG_HIST1_12_OFFSET (0xB30) -#define DSP2_BLBACK_HIST1_12_R DSP2_BLBACK_HIST1_12_R -#define DSP2_BLBACK_HIST1_12_R_POS (0U) -#define DSP2_BLBACK_HIST1_12_R_LEN (24U) -#define DSP2_BLBACK_HIST1_12_R_MSK (((1U << DSP2_BLBACK_HIST1_12_R_LEN) - 1) << DSP2_BLBACK_HIST1_12_R_POS) -#define DSP2_BLBACK_HIST1_12_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_12_R_LEN) - 1) << DSP2_BLBACK_HIST1_12_R_POS)) - -/* 0xB34 : REG_HIST1_13 */ -#define DSP2_BLBACK_REG_HIST1_13_OFFSET (0xB34) -#define DSP2_BLBACK_HIST1_13_R DSP2_BLBACK_HIST1_13_R -#define DSP2_BLBACK_HIST1_13_R_POS (0U) -#define DSP2_BLBACK_HIST1_13_R_LEN (24U) -#define DSP2_BLBACK_HIST1_13_R_MSK (((1U << DSP2_BLBACK_HIST1_13_R_LEN) - 1) << DSP2_BLBACK_HIST1_13_R_POS) -#define DSP2_BLBACK_HIST1_13_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_13_R_LEN) - 1) << DSP2_BLBACK_HIST1_13_R_POS)) - -/* 0xB38 : REG_HIST1_14 */ -#define DSP2_BLBACK_REG_HIST1_14_OFFSET (0xB38) -#define DSP2_BLBACK_HIST1_14_R DSP2_BLBACK_HIST1_14_R -#define DSP2_BLBACK_HIST1_14_R_POS (0U) -#define DSP2_BLBACK_HIST1_14_R_LEN (24U) -#define DSP2_BLBACK_HIST1_14_R_MSK (((1U << DSP2_BLBACK_HIST1_14_R_LEN) - 1) << DSP2_BLBACK_HIST1_14_R_POS) -#define DSP2_BLBACK_HIST1_14_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_14_R_LEN) - 1) << DSP2_BLBACK_HIST1_14_R_POS)) - -/* 0xB3C : REG_HIST1_15 */ -#define DSP2_BLBACK_REG_HIST1_15_OFFSET (0xB3C) -#define DSP2_BLBACK_HIST1_15_R DSP2_BLBACK_HIST1_15_R -#define DSP2_BLBACK_HIST1_15_R_POS (0U) -#define DSP2_BLBACK_HIST1_15_R_LEN (24U) -#define DSP2_BLBACK_HIST1_15_R_MSK (((1U << DSP2_BLBACK_HIST1_15_R_LEN) - 1) << DSP2_BLBACK_HIST1_15_R_POS) -#define DSP2_BLBACK_HIST1_15_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_15_R_LEN) - 1) << DSP2_BLBACK_HIST1_15_R_POS)) - -/* 0xB40 : REG_HIST1_16 */ -#define DSP2_BLBACK_REG_HIST1_16_OFFSET (0xB40) -#define DSP2_BLBACK_HIST1_16_R DSP2_BLBACK_HIST1_16_R -#define DSP2_BLBACK_HIST1_16_R_POS (0U) -#define DSP2_BLBACK_HIST1_16_R_LEN (24U) -#define DSP2_BLBACK_HIST1_16_R_MSK (((1U << DSP2_BLBACK_HIST1_16_R_LEN) - 1) << DSP2_BLBACK_HIST1_16_R_POS) -#define DSP2_BLBACK_HIST1_16_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_16_R_LEN) - 1) << DSP2_BLBACK_HIST1_16_R_POS)) - -/* 0xB44 : REG_HIST1_17 */ -#define DSP2_BLBACK_REG_HIST1_17_OFFSET (0xB44) -#define DSP2_BLBACK_HIST1_17_R DSP2_BLBACK_HIST1_17_R -#define DSP2_BLBACK_HIST1_17_R_POS (0U) -#define DSP2_BLBACK_HIST1_17_R_LEN (24U) -#define DSP2_BLBACK_HIST1_17_R_MSK (((1U << DSP2_BLBACK_HIST1_17_R_LEN) - 1) << DSP2_BLBACK_HIST1_17_R_POS) -#define DSP2_BLBACK_HIST1_17_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_17_R_LEN) - 1) << DSP2_BLBACK_HIST1_17_R_POS)) - -/* 0xB48 : REG_HIST1_18 */ -#define DSP2_BLBACK_REG_HIST1_18_OFFSET (0xB48) -#define DSP2_BLBACK_HIST1_18_R DSP2_BLBACK_HIST1_18_R -#define DSP2_BLBACK_HIST1_18_R_POS (0U) -#define DSP2_BLBACK_HIST1_18_R_LEN (24U) -#define DSP2_BLBACK_HIST1_18_R_MSK (((1U << DSP2_BLBACK_HIST1_18_R_LEN) - 1) << DSP2_BLBACK_HIST1_18_R_POS) -#define DSP2_BLBACK_HIST1_18_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_18_R_LEN) - 1) << DSP2_BLBACK_HIST1_18_R_POS)) - -/* 0xB4C : REG_HIST1_19 */ -#define DSP2_BLBACK_REG_HIST1_19_OFFSET (0xB4C) -#define DSP2_BLBACK_HIST1_19_R DSP2_BLBACK_HIST1_19_R -#define DSP2_BLBACK_HIST1_19_R_POS (0U) -#define DSP2_BLBACK_HIST1_19_R_LEN (24U) -#define DSP2_BLBACK_HIST1_19_R_MSK (((1U << DSP2_BLBACK_HIST1_19_R_LEN) - 1) << DSP2_BLBACK_HIST1_19_R_POS) -#define DSP2_BLBACK_HIST1_19_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_19_R_LEN) - 1) << DSP2_BLBACK_HIST1_19_R_POS)) - -/* 0xB50 : REG_HIST1_20 */ -#define DSP2_BLBACK_REG_HIST1_20_OFFSET (0xB50) -#define DSP2_BLBACK_HIST1_20_R DSP2_BLBACK_HIST1_20_R -#define DSP2_BLBACK_HIST1_20_R_POS (0U) -#define DSP2_BLBACK_HIST1_20_R_LEN (24U) -#define DSP2_BLBACK_HIST1_20_R_MSK (((1U << DSP2_BLBACK_HIST1_20_R_LEN) - 1) << DSP2_BLBACK_HIST1_20_R_POS) -#define DSP2_BLBACK_HIST1_20_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_20_R_LEN) - 1) << DSP2_BLBACK_HIST1_20_R_POS)) - -/* 0xB54 : REG_HIST1_21 */ -#define DSP2_BLBACK_REG_HIST1_21_OFFSET (0xB54) -#define DSP2_BLBACK_HIST1_21_R DSP2_BLBACK_HIST1_21_R -#define DSP2_BLBACK_HIST1_21_R_POS (0U) -#define DSP2_BLBACK_HIST1_21_R_LEN (24U) -#define DSP2_BLBACK_HIST1_21_R_MSK (((1U << DSP2_BLBACK_HIST1_21_R_LEN) - 1) << DSP2_BLBACK_HIST1_21_R_POS) -#define DSP2_BLBACK_HIST1_21_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_21_R_LEN) - 1) << DSP2_BLBACK_HIST1_21_R_POS)) - -/* 0xB58 : REG_HIST1_22 */ -#define DSP2_BLBACK_REG_HIST1_22_OFFSET (0xB58) -#define DSP2_BLBACK_HIST1_22_R DSP2_BLBACK_HIST1_22_R -#define DSP2_BLBACK_HIST1_22_R_POS (0U) -#define DSP2_BLBACK_HIST1_22_R_LEN (24U) -#define DSP2_BLBACK_HIST1_22_R_MSK (((1U << DSP2_BLBACK_HIST1_22_R_LEN) - 1) << DSP2_BLBACK_HIST1_22_R_POS) -#define DSP2_BLBACK_HIST1_22_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_22_R_LEN) - 1) << DSP2_BLBACK_HIST1_22_R_POS)) - -/* 0xB5C : REG_HIST1_23 */ -#define DSP2_BLBACK_REG_HIST1_23_OFFSET (0xB5C) -#define DSP2_BLBACK_HIST1_23_R DSP2_BLBACK_HIST1_23_R -#define DSP2_BLBACK_HIST1_23_R_POS (0U) -#define DSP2_BLBACK_HIST1_23_R_LEN (24U) -#define DSP2_BLBACK_HIST1_23_R_MSK (((1U << DSP2_BLBACK_HIST1_23_R_LEN) - 1) << DSP2_BLBACK_HIST1_23_R_POS) -#define DSP2_BLBACK_HIST1_23_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_23_R_LEN) - 1) << DSP2_BLBACK_HIST1_23_R_POS)) - -/* 0xB60 : REG_HIST1_24 */ -#define DSP2_BLBACK_REG_HIST1_24_OFFSET (0xB60) -#define DSP2_BLBACK_HIST1_24_R DSP2_BLBACK_HIST1_24_R -#define DSP2_BLBACK_HIST1_24_R_POS (0U) -#define DSP2_BLBACK_HIST1_24_R_LEN (24U) -#define DSP2_BLBACK_HIST1_24_R_MSK (((1U << DSP2_BLBACK_HIST1_24_R_LEN) - 1) << DSP2_BLBACK_HIST1_24_R_POS) -#define DSP2_BLBACK_HIST1_24_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_24_R_LEN) - 1) << DSP2_BLBACK_HIST1_24_R_POS)) - -/* 0xB64 : REG_HIST1_25 */ -#define DSP2_BLBACK_REG_HIST1_25_OFFSET (0xB64) -#define DSP2_BLBACK_HIST1_25_R DSP2_BLBACK_HIST1_25_R -#define DSP2_BLBACK_HIST1_25_R_POS (0U) -#define DSP2_BLBACK_HIST1_25_R_LEN (24U) -#define DSP2_BLBACK_HIST1_25_R_MSK (((1U << DSP2_BLBACK_HIST1_25_R_LEN) - 1) << DSP2_BLBACK_HIST1_25_R_POS) -#define DSP2_BLBACK_HIST1_25_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_25_R_LEN) - 1) << DSP2_BLBACK_HIST1_25_R_POS)) - -/* 0xB68 : REG_HIST1_26 */ -#define DSP2_BLBACK_REG_HIST1_26_OFFSET (0xB68) -#define DSP2_BLBACK_HIST1_26_R DSP2_BLBACK_HIST1_26_R -#define DSP2_BLBACK_HIST1_26_R_POS (0U) -#define DSP2_BLBACK_HIST1_26_R_LEN (24U) -#define DSP2_BLBACK_HIST1_26_R_MSK (((1U << DSP2_BLBACK_HIST1_26_R_LEN) - 1) << DSP2_BLBACK_HIST1_26_R_POS) -#define DSP2_BLBACK_HIST1_26_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_26_R_LEN) - 1) << DSP2_BLBACK_HIST1_26_R_POS)) - -/* 0xB6C : REG_HIST1_27 */ -#define DSP2_BLBACK_REG_HIST1_27_OFFSET (0xB6C) -#define DSP2_BLBACK_HIST1_27_R DSP2_BLBACK_HIST1_27_R -#define DSP2_BLBACK_HIST1_27_R_POS (0U) -#define DSP2_BLBACK_HIST1_27_R_LEN (24U) -#define DSP2_BLBACK_HIST1_27_R_MSK (((1U << DSP2_BLBACK_HIST1_27_R_LEN) - 1) << DSP2_BLBACK_HIST1_27_R_POS) -#define DSP2_BLBACK_HIST1_27_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_27_R_LEN) - 1) << DSP2_BLBACK_HIST1_27_R_POS)) - -/* 0xB70 : REG_HIST1_28 */ -#define DSP2_BLBACK_REG_HIST1_28_OFFSET (0xB70) -#define DSP2_BLBACK_HIST1_28_R DSP2_BLBACK_HIST1_28_R -#define DSP2_BLBACK_HIST1_28_R_POS (0U) -#define DSP2_BLBACK_HIST1_28_R_LEN (24U) -#define DSP2_BLBACK_HIST1_28_R_MSK (((1U << DSP2_BLBACK_HIST1_28_R_LEN) - 1) << DSP2_BLBACK_HIST1_28_R_POS) -#define DSP2_BLBACK_HIST1_28_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_28_R_LEN) - 1) << DSP2_BLBACK_HIST1_28_R_POS)) - -/* 0xB74 : REG_HIST1_29 */ -#define DSP2_BLBACK_REG_HIST1_29_OFFSET (0xB74) -#define DSP2_BLBACK_HIST1_29_R DSP2_BLBACK_HIST1_29_R -#define DSP2_BLBACK_HIST1_29_R_POS (0U) -#define DSP2_BLBACK_HIST1_29_R_LEN (24U) -#define DSP2_BLBACK_HIST1_29_R_MSK (((1U << DSP2_BLBACK_HIST1_29_R_LEN) - 1) << DSP2_BLBACK_HIST1_29_R_POS) -#define DSP2_BLBACK_HIST1_29_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_29_R_LEN) - 1) << DSP2_BLBACK_HIST1_29_R_POS)) - -/* 0xB78 : REG_HIST1_30 */ -#define DSP2_BLBACK_REG_HIST1_30_OFFSET (0xB78) -#define DSP2_BLBACK_HIST1_30_R DSP2_BLBACK_HIST1_30_R -#define DSP2_BLBACK_HIST1_30_R_POS (0U) -#define DSP2_BLBACK_HIST1_30_R_LEN (24U) -#define DSP2_BLBACK_HIST1_30_R_MSK (((1U << DSP2_BLBACK_HIST1_30_R_LEN) - 1) << DSP2_BLBACK_HIST1_30_R_POS) -#define DSP2_BLBACK_HIST1_30_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_30_R_LEN) - 1) << DSP2_BLBACK_HIST1_30_R_POS)) - -/* 0xB7C : REG_HIST1_31 */ -#define DSP2_BLBACK_REG_HIST1_31_OFFSET (0xB7C) -#define DSP2_BLBACK_HIST1_31_R DSP2_BLBACK_HIST1_31_R -#define DSP2_BLBACK_HIST1_31_R_POS (0U) -#define DSP2_BLBACK_HIST1_31_R_LEN (24U) -#define DSP2_BLBACK_HIST1_31_R_MSK (((1U << DSP2_BLBACK_HIST1_31_R_LEN) - 1) << DSP2_BLBACK_HIST1_31_R_POS) -#define DSP2_BLBACK_HIST1_31_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_31_R_LEN) - 1) << DSP2_BLBACK_HIST1_31_R_POS)) - -/* 0xB80 : REG_HIST1_32 */ -#define DSP2_BLBACK_REG_HIST1_32_OFFSET (0xB80) -#define DSP2_BLBACK_HIST1_32_R DSP2_BLBACK_HIST1_32_R -#define DSP2_BLBACK_HIST1_32_R_POS (0U) -#define DSP2_BLBACK_HIST1_32_R_LEN (24U) -#define DSP2_BLBACK_HIST1_32_R_MSK (((1U << DSP2_BLBACK_HIST1_32_R_LEN) - 1) << DSP2_BLBACK_HIST1_32_R_POS) -#define DSP2_BLBACK_HIST1_32_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_32_R_LEN) - 1) << DSP2_BLBACK_HIST1_32_R_POS)) - -/* 0xB84 : REG_HIST1_33 */ -#define DSP2_BLBACK_REG_HIST1_33_OFFSET (0xB84) -#define DSP2_BLBACK_HIST1_33_R DSP2_BLBACK_HIST1_33_R -#define DSP2_BLBACK_HIST1_33_R_POS (0U) -#define DSP2_BLBACK_HIST1_33_R_LEN (24U) -#define DSP2_BLBACK_HIST1_33_R_MSK (((1U << DSP2_BLBACK_HIST1_33_R_LEN) - 1) << DSP2_BLBACK_HIST1_33_R_POS) -#define DSP2_BLBACK_HIST1_33_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_33_R_LEN) - 1) << DSP2_BLBACK_HIST1_33_R_POS)) - -/* 0xB88 : REG_HIST1_34 */ -#define DSP2_BLBACK_REG_HIST1_34_OFFSET (0xB88) -#define DSP2_BLBACK_HIST1_34_R DSP2_BLBACK_HIST1_34_R -#define DSP2_BLBACK_HIST1_34_R_POS (0U) -#define DSP2_BLBACK_HIST1_34_R_LEN (24U) -#define DSP2_BLBACK_HIST1_34_R_MSK (((1U << DSP2_BLBACK_HIST1_34_R_LEN) - 1) << DSP2_BLBACK_HIST1_34_R_POS) -#define DSP2_BLBACK_HIST1_34_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_34_R_LEN) - 1) << DSP2_BLBACK_HIST1_34_R_POS)) - -/* 0xB8C : REG_HIST1_35 */ -#define DSP2_BLBACK_REG_HIST1_35_OFFSET (0xB8C) -#define DSP2_BLBACK_HIST1_35_R DSP2_BLBACK_HIST1_35_R -#define DSP2_BLBACK_HIST1_35_R_POS (0U) -#define DSP2_BLBACK_HIST1_35_R_LEN (24U) -#define DSP2_BLBACK_HIST1_35_R_MSK (((1U << DSP2_BLBACK_HIST1_35_R_LEN) - 1) << DSP2_BLBACK_HIST1_35_R_POS) -#define DSP2_BLBACK_HIST1_35_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_35_R_LEN) - 1) << DSP2_BLBACK_HIST1_35_R_POS)) - -/* 0xB90 : REG_HIST1_36 */ -#define DSP2_BLBACK_REG_HIST1_36_OFFSET (0xB90) -#define DSP2_BLBACK_HIST1_36_R DSP2_BLBACK_HIST1_36_R -#define DSP2_BLBACK_HIST1_36_R_POS (0U) -#define DSP2_BLBACK_HIST1_36_R_LEN (24U) -#define DSP2_BLBACK_HIST1_36_R_MSK (((1U << DSP2_BLBACK_HIST1_36_R_LEN) - 1) << DSP2_BLBACK_HIST1_36_R_POS) -#define DSP2_BLBACK_HIST1_36_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_36_R_LEN) - 1) << DSP2_BLBACK_HIST1_36_R_POS)) - -/* 0xB94 : REG_HIST1_37 */ -#define DSP2_BLBACK_REG_HIST1_37_OFFSET (0xB94) -#define DSP2_BLBACK_HIST1_37_R DSP2_BLBACK_HIST1_37_R -#define DSP2_BLBACK_HIST1_37_R_POS (0U) -#define DSP2_BLBACK_HIST1_37_R_LEN (24U) -#define DSP2_BLBACK_HIST1_37_R_MSK (((1U << DSP2_BLBACK_HIST1_37_R_LEN) - 1) << DSP2_BLBACK_HIST1_37_R_POS) -#define DSP2_BLBACK_HIST1_37_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_37_R_LEN) - 1) << DSP2_BLBACK_HIST1_37_R_POS)) - -/* 0xB98 : REG_HIST1_38 */ -#define DSP2_BLBACK_REG_HIST1_38_OFFSET (0xB98) -#define DSP2_BLBACK_HIST1_38_R DSP2_BLBACK_HIST1_38_R -#define DSP2_BLBACK_HIST1_38_R_POS (0U) -#define DSP2_BLBACK_HIST1_38_R_LEN (24U) -#define DSP2_BLBACK_HIST1_38_R_MSK (((1U << DSP2_BLBACK_HIST1_38_R_LEN) - 1) << DSP2_BLBACK_HIST1_38_R_POS) -#define DSP2_BLBACK_HIST1_38_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_38_R_LEN) - 1) << DSP2_BLBACK_HIST1_38_R_POS)) - -/* 0xB9C : REG_HIST1_39 */ -#define DSP2_BLBACK_REG_HIST1_39_OFFSET (0xB9C) -#define DSP2_BLBACK_HIST1_39_R DSP2_BLBACK_HIST1_39_R -#define DSP2_BLBACK_HIST1_39_R_POS (0U) -#define DSP2_BLBACK_HIST1_39_R_LEN (24U) -#define DSP2_BLBACK_HIST1_39_R_MSK (((1U << DSP2_BLBACK_HIST1_39_R_LEN) - 1) << DSP2_BLBACK_HIST1_39_R_POS) -#define DSP2_BLBACK_HIST1_39_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_39_R_LEN) - 1) << DSP2_BLBACK_HIST1_39_R_POS)) - -/* 0xBA0 : REG_HIST1_40 */ -#define DSP2_BLBACK_REG_HIST1_40_OFFSET (0xBA0) -#define DSP2_BLBACK_HIST1_40_R DSP2_BLBACK_HIST1_40_R -#define DSP2_BLBACK_HIST1_40_R_POS (0U) -#define DSP2_BLBACK_HIST1_40_R_LEN (24U) -#define DSP2_BLBACK_HIST1_40_R_MSK (((1U << DSP2_BLBACK_HIST1_40_R_LEN) - 1) << DSP2_BLBACK_HIST1_40_R_POS) -#define DSP2_BLBACK_HIST1_40_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_40_R_LEN) - 1) << DSP2_BLBACK_HIST1_40_R_POS)) - -/* 0xBA4 : REG_HIST1_41 */ -#define DSP2_BLBACK_REG_HIST1_41_OFFSET (0xBA4) -#define DSP2_BLBACK_HIST1_41_R DSP2_BLBACK_HIST1_41_R -#define DSP2_BLBACK_HIST1_41_R_POS (0U) -#define DSP2_BLBACK_HIST1_41_R_LEN (24U) -#define DSP2_BLBACK_HIST1_41_R_MSK (((1U << DSP2_BLBACK_HIST1_41_R_LEN) - 1) << DSP2_BLBACK_HIST1_41_R_POS) -#define DSP2_BLBACK_HIST1_41_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_41_R_LEN) - 1) << DSP2_BLBACK_HIST1_41_R_POS)) - -/* 0xBA8 : REG_HIST1_42 */ -#define DSP2_BLBACK_REG_HIST1_42_OFFSET (0xBA8) -#define DSP2_BLBACK_HIST1_42_R DSP2_BLBACK_HIST1_42_R -#define DSP2_BLBACK_HIST1_42_R_POS (0U) -#define DSP2_BLBACK_HIST1_42_R_LEN (24U) -#define DSP2_BLBACK_HIST1_42_R_MSK (((1U << DSP2_BLBACK_HIST1_42_R_LEN) - 1) << DSP2_BLBACK_HIST1_42_R_POS) -#define DSP2_BLBACK_HIST1_42_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_42_R_LEN) - 1) << DSP2_BLBACK_HIST1_42_R_POS)) - -/* 0xBAC : REG_HIST1_43 */ -#define DSP2_BLBACK_REG_HIST1_43_OFFSET (0xBAC) -#define DSP2_BLBACK_HIST1_43_R DSP2_BLBACK_HIST1_43_R -#define DSP2_BLBACK_HIST1_43_R_POS (0U) -#define DSP2_BLBACK_HIST1_43_R_LEN (24U) -#define DSP2_BLBACK_HIST1_43_R_MSK (((1U << DSP2_BLBACK_HIST1_43_R_LEN) - 1) << DSP2_BLBACK_HIST1_43_R_POS) -#define DSP2_BLBACK_HIST1_43_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_43_R_LEN) - 1) << DSP2_BLBACK_HIST1_43_R_POS)) - -/* 0xBB0 : REG_HIST1_44 */ -#define DSP2_BLBACK_REG_HIST1_44_OFFSET (0xBB0) -#define DSP2_BLBACK_HIST1_44_R DSP2_BLBACK_HIST1_44_R -#define DSP2_BLBACK_HIST1_44_R_POS (0U) -#define DSP2_BLBACK_HIST1_44_R_LEN (24U) -#define DSP2_BLBACK_HIST1_44_R_MSK (((1U << DSP2_BLBACK_HIST1_44_R_LEN) - 1) << DSP2_BLBACK_HIST1_44_R_POS) -#define DSP2_BLBACK_HIST1_44_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_44_R_LEN) - 1) << DSP2_BLBACK_HIST1_44_R_POS)) - -/* 0xBB4 : REG_HIST1_45 */ -#define DSP2_BLBACK_REG_HIST1_45_OFFSET (0xBB4) -#define DSP2_BLBACK_HIST1_45_R DSP2_BLBACK_HIST1_45_R -#define DSP2_BLBACK_HIST1_45_R_POS (0U) -#define DSP2_BLBACK_HIST1_45_R_LEN (24U) -#define DSP2_BLBACK_HIST1_45_R_MSK (((1U << DSP2_BLBACK_HIST1_45_R_LEN) - 1) << DSP2_BLBACK_HIST1_45_R_POS) -#define DSP2_BLBACK_HIST1_45_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_45_R_LEN) - 1) << DSP2_BLBACK_HIST1_45_R_POS)) - -/* 0xBB8 : REG_HIST1_46 */ -#define DSP2_BLBACK_REG_HIST1_46_OFFSET (0xBB8) -#define DSP2_BLBACK_HIST1_46_R DSP2_BLBACK_HIST1_46_R -#define DSP2_BLBACK_HIST1_46_R_POS (0U) -#define DSP2_BLBACK_HIST1_46_R_LEN (24U) -#define DSP2_BLBACK_HIST1_46_R_MSK (((1U << DSP2_BLBACK_HIST1_46_R_LEN) - 1) << DSP2_BLBACK_HIST1_46_R_POS) -#define DSP2_BLBACK_HIST1_46_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_46_R_LEN) - 1) << DSP2_BLBACK_HIST1_46_R_POS)) - -/* 0xBBC : REG_HIST1_47 */ -#define DSP2_BLBACK_REG_HIST1_47_OFFSET (0xBBC) -#define DSP2_BLBACK_HIST1_47_R DSP2_BLBACK_HIST1_47_R -#define DSP2_BLBACK_HIST1_47_R_POS (0U) -#define DSP2_BLBACK_HIST1_47_R_LEN (24U) -#define DSP2_BLBACK_HIST1_47_R_MSK (((1U << DSP2_BLBACK_HIST1_47_R_LEN) - 1) << DSP2_BLBACK_HIST1_47_R_POS) -#define DSP2_BLBACK_HIST1_47_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_47_R_LEN) - 1) << DSP2_BLBACK_HIST1_47_R_POS)) - -/* 0xBC0 : REG_HIST1_48 */ -#define DSP2_BLBACK_REG_HIST1_48_OFFSET (0xBC0) -#define DSP2_BLBACK_HIST1_48_R DSP2_BLBACK_HIST1_48_R -#define DSP2_BLBACK_HIST1_48_R_POS (0U) -#define DSP2_BLBACK_HIST1_48_R_LEN (24U) -#define DSP2_BLBACK_HIST1_48_R_MSK (((1U << DSP2_BLBACK_HIST1_48_R_LEN) - 1) << DSP2_BLBACK_HIST1_48_R_POS) -#define DSP2_BLBACK_HIST1_48_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_48_R_LEN) - 1) << DSP2_BLBACK_HIST1_48_R_POS)) - -/* 0xBC4 : REG_HIST1_49 */ -#define DSP2_BLBACK_REG_HIST1_49_OFFSET (0xBC4) -#define DSP2_BLBACK_HIST1_49_R DSP2_BLBACK_HIST1_49_R -#define DSP2_BLBACK_HIST1_49_R_POS (0U) -#define DSP2_BLBACK_HIST1_49_R_LEN (24U) -#define DSP2_BLBACK_HIST1_49_R_MSK (((1U << DSP2_BLBACK_HIST1_49_R_LEN) - 1) << DSP2_BLBACK_HIST1_49_R_POS) -#define DSP2_BLBACK_HIST1_49_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_49_R_LEN) - 1) << DSP2_BLBACK_HIST1_49_R_POS)) - -/* 0xBC8 : REG_HIST1_50 */ -#define DSP2_BLBACK_REG_HIST1_50_OFFSET (0xBC8) -#define DSP2_BLBACK_HIST1_50_R DSP2_BLBACK_HIST1_50_R -#define DSP2_BLBACK_HIST1_50_R_POS (0U) -#define DSP2_BLBACK_HIST1_50_R_LEN (24U) -#define DSP2_BLBACK_HIST1_50_R_MSK (((1U << DSP2_BLBACK_HIST1_50_R_LEN) - 1) << DSP2_BLBACK_HIST1_50_R_POS) -#define DSP2_BLBACK_HIST1_50_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_50_R_LEN) - 1) << DSP2_BLBACK_HIST1_50_R_POS)) - -/* 0xBCC : REG_HIST1_51 */ -#define DSP2_BLBACK_REG_HIST1_51_OFFSET (0xBCC) -#define DSP2_BLBACK_HIST1_51_R DSP2_BLBACK_HIST1_51_R -#define DSP2_BLBACK_HIST1_51_R_POS (0U) -#define DSP2_BLBACK_HIST1_51_R_LEN (24U) -#define DSP2_BLBACK_HIST1_51_R_MSK (((1U << DSP2_BLBACK_HIST1_51_R_LEN) - 1) << DSP2_BLBACK_HIST1_51_R_POS) -#define DSP2_BLBACK_HIST1_51_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_51_R_LEN) - 1) << DSP2_BLBACK_HIST1_51_R_POS)) - -/* 0xBD0 : REG_HIST1_52 */ -#define DSP2_BLBACK_REG_HIST1_52_OFFSET (0xBD0) -#define DSP2_BLBACK_HIST1_52_R DSP2_BLBACK_HIST1_52_R -#define DSP2_BLBACK_HIST1_52_R_POS (0U) -#define DSP2_BLBACK_HIST1_52_R_LEN (24U) -#define DSP2_BLBACK_HIST1_52_R_MSK (((1U << DSP2_BLBACK_HIST1_52_R_LEN) - 1) << DSP2_BLBACK_HIST1_52_R_POS) -#define DSP2_BLBACK_HIST1_52_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_52_R_LEN) - 1) << DSP2_BLBACK_HIST1_52_R_POS)) - -/* 0xBD4 : REG_HIST1_53 */ -#define DSP2_BLBACK_REG_HIST1_53_OFFSET (0xBD4) -#define DSP2_BLBACK_HIST1_53_R DSP2_BLBACK_HIST1_53_R -#define DSP2_BLBACK_HIST1_53_R_POS (0U) -#define DSP2_BLBACK_HIST1_53_R_LEN (24U) -#define DSP2_BLBACK_HIST1_53_R_MSK (((1U << DSP2_BLBACK_HIST1_53_R_LEN) - 1) << DSP2_BLBACK_HIST1_53_R_POS) -#define DSP2_BLBACK_HIST1_53_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_53_R_LEN) - 1) << DSP2_BLBACK_HIST1_53_R_POS)) - -/* 0xBD8 : REG_HIST1_54 */ -#define DSP2_BLBACK_REG_HIST1_54_OFFSET (0xBD8) -#define DSP2_BLBACK_HIST1_54_R DSP2_BLBACK_HIST1_54_R -#define DSP2_BLBACK_HIST1_54_R_POS (0U) -#define DSP2_BLBACK_HIST1_54_R_LEN (24U) -#define DSP2_BLBACK_HIST1_54_R_MSK (((1U << DSP2_BLBACK_HIST1_54_R_LEN) - 1) << DSP2_BLBACK_HIST1_54_R_POS) -#define DSP2_BLBACK_HIST1_54_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_54_R_LEN) - 1) << DSP2_BLBACK_HIST1_54_R_POS)) - -/* 0xBDC : REG_HIST1_55 */ -#define DSP2_BLBACK_REG_HIST1_55_OFFSET (0xBDC) -#define DSP2_BLBACK_HIST1_55_R DSP2_BLBACK_HIST1_55_R -#define DSP2_BLBACK_HIST1_55_R_POS (0U) -#define DSP2_BLBACK_HIST1_55_R_LEN (24U) -#define DSP2_BLBACK_HIST1_55_R_MSK (((1U << DSP2_BLBACK_HIST1_55_R_LEN) - 1) << DSP2_BLBACK_HIST1_55_R_POS) -#define DSP2_BLBACK_HIST1_55_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_55_R_LEN) - 1) << DSP2_BLBACK_HIST1_55_R_POS)) - -/* 0xBE0 : REG_HIST1_56 */ -#define DSP2_BLBACK_REG_HIST1_56_OFFSET (0xBE0) -#define DSP2_BLBACK_HIST1_56_R DSP2_BLBACK_HIST1_56_R -#define DSP2_BLBACK_HIST1_56_R_POS (0U) -#define DSP2_BLBACK_HIST1_56_R_LEN (24U) -#define DSP2_BLBACK_HIST1_56_R_MSK (((1U << DSP2_BLBACK_HIST1_56_R_LEN) - 1) << DSP2_BLBACK_HIST1_56_R_POS) -#define DSP2_BLBACK_HIST1_56_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_56_R_LEN) - 1) << DSP2_BLBACK_HIST1_56_R_POS)) - -/* 0xBE4 : REG_HIST1_57 */ -#define DSP2_BLBACK_REG_HIST1_57_OFFSET (0xBE4) -#define DSP2_BLBACK_HIST1_57_R DSP2_BLBACK_HIST1_57_R -#define DSP2_BLBACK_HIST1_57_R_POS (0U) -#define DSP2_BLBACK_HIST1_57_R_LEN (24U) -#define DSP2_BLBACK_HIST1_57_R_MSK (((1U << DSP2_BLBACK_HIST1_57_R_LEN) - 1) << DSP2_BLBACK_HIST1_57_R_POS) -#define DSP2_BLBACK_HIST1_57_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_57_R_LEN) - 1) << DSP2_BLBACK_HIST1_57_R_POS)) - -/* 0xBE8 : REG_HIST1_58 */ -#define DSP2_BLBACK_REG_HIST1_58_OFFSET (0xBE8) -#define DSP2_BLBACK_HIST1_58_R DSP2_BLBACK_HIST1_58_R -#define DSP2_BLBACK_HIST1_58_R_POS (0U) -#define DSP2_BLBACK_HIST1_58_R_LEN (24U) -#define DSP2_BLBACK_HIST1_58_R_MSK (((1U << DSP2_BLBACK_HIST1_58_R_LEN) - 1) << DSP2_BLBACK_HIST1_58_R_POS) -#define DSP2_BLBACK_HIST1_58_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_58_R_LEN) - 1) << DSP2_BLBACK_HIST1_58_R_POS)) - -/* 0xBEC : REG_HIST1_59 */ -#define DSP2_BLBACK_REG_HIST1_59_OFFSET (0xBEC) -#define DSP2_BLBACK_HIST1_59_R DSP2_BLBACK_HIST1_59_R -#define DSP2_BLBACK_HIST1_59_R_POS (0U) -#define DSP2_BLBACK_HIST1_59_R_LEN (24U) -#define DSP2_BLBACK_HIST1_59_R_MSK (((1U << DSP2_BLBACK_HIST1_59_R_LEN) - 1) << DSP2_BLBACK_HIST1_59_R_POS) -#define DSP2_BLBACK_HIST1_59_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_59_R_LEN) - 1) << DSP2_BLBACK_HIST1_59_R_POS)) - -/* 0xBF0 : REG_HIST1_60 */ -#define DSP2_BLBACK_REG_HIST1_60_OFFSET (0xBF0) -#define DSP2_BLBACK_HIST1_60_R DSP2_BLBACK_HIST1_60_R -#define DSP2_BLBACK_HIST1_60_R_POS (0U) -#define DSP2_BLBACK_HIST1_60_R_LEN (24U) -#define DSP2_BLBACK_HIST1_60_R_MSK (((1U << DSP2_BLBACK_HIST1_60_R_LEN) - 1) << DSP2_BLBACK_HIST1_60_R_POS) -#define DSP2_BLBACK_HIST1_60_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_60_R_LEN) - 1) << DSP2_BLBACK_HIST1_60_R_POS)) - -/* 0xBF4 : REG_HIST1_61 */ -#define DSP2_BLBACK_REG_HIST1_61_OFFSET (0xBF4) -#define DSP2_BLBACK_HIST1_61_R DSP2_BLBACK_HIST1_61_R -#define DSP2_BLBACK_HIST1_61_R_POS (0U) -#define DSP2_BLBACK_HIST1_61_R_LEN (24U) -#define DSP2_BLBACK_HIST1_61_R_MSK (((1U << DSP2_BLBACK_HIST1_61_R_LEN) - 1) << DSP2_BLBACK_HIST1_61_R_POS) -#define DSP2_BLBACK_HIST1_61_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_61_R_LEN) - 1) << DSP2_BLBACK_HIST1_61_R_POS)) - -/* 0xBF8 : REG_HIST1_62 */ -#define DSP2_BLBACK_REG_HIST1_62_OFFSET (0xBF8) -#define DSP2_BLBACK_HIST1_62_R DSP2_BLBACK_HIST1_62_R -#define DSP2_BLBACK_HIST1_62_R_POS (0U) -#define DSP2_BLBACK_HIST1_62_R_LEN (24U) -#define DSP2_BLBACK_HIST1_62_R_MSK (((1U << DSP2_BLBACK_HIST1_62_R_LEN) - 1) << DSP2_BLBACK_HIST1_62_R_POS) -#define DSP2_BLBACK_HIST1_62_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_62_R_LEN) - 1) << DSP2_BLBACK_HIST1_62_R_POS)) - -/* 0xBFC : REG_HIST1_63 */ -#define DSP2_BLBACK_REG_HIST1_63_OFFSET (0xBFC) -#define DSP2_BLBACK_HIST1_63_R DSP2_BLBACK_HIST1_63_R -#define DSP2_BLBACK_HIST1_63_R_POS (0U) -#define DSP2_BLBACK_HIST1_63_R_LEN (24U) -#define DSP2_BLBACK_HIST1_63_R_MSK (((1U << DSP2_BLBACK_HIST1_63_R_LEN) - 1) << DSP2_BLBACK_HIST1_63_R_POS) -#define DSP2_BLBACK_HIST1_63_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_63_R_LEN) - 1) << DSP2_BLBACK_HIST1_63_R_POS)) - -/* 0xC00 : WDR_CURVE_1 */ -#define DSP2_BLBACK_WDR_CURVE_1_OFFSET (0xC00) -#define DSP2_BLBACK_CURVE_0_PRE DSP2_BLBACK_CURVE_0_PRE -#define DSP2_BLBACK_CURVE_0_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_0_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_0_PRE_MSK (((1U << DSP2_BLBACK_CURVE_0_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_0_PRE_POS) -#define DSP2_BLBACK_CURVE_0_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_0_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_0_PRE_POS)) -#define DSP2_BLBACK_CURVE_1_PRE DSP2_BLBACK_CURVE_1_PRE -#define DSP2_BLBACK_CURVE_1_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_1_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_1_PRE_MSK (((1U << DSP2_BLBACK_CURVE_1_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_1_PRE_POS) -#define DSP2_BLBACK_CURVE_1_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_1_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_1_PRE_POS)) - -/* 0xC04 : WDR_CURVE_2 */ -#define DSP2_BLBACK_WDR_CURVE_2_OFFSET (0xC04) -#define DSP2_BLBACK_CURVE_2_PRE DSP2_BLBACK_CURVE_2_PRE -#define DSP2_BLBACK_CURVE_2_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_2_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_2_PRE_MSK (((1U << DSP2_BLBACK_CURVE_2_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_2_PRE_POS) -#define DSP2_BLBACK_CURVE_2_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_2_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_2_PRE_POS)) -#define DSP2_BLBACK_CURVE_3_PRE DSP2_BLBACK_CURVE_3_PRE -#define DSP2_BLBACK_CURVE_3_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_3_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_3_PRE_MSK (((1U << DSP2_BLBACK_CURVE_3_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_3_PRE_POS) -#define DSP2_BLBACK_CURVE_3_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_3_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_3_PRE_POS)) - -/* 0xC08 : WDR_CURVE_3 */ -#define DSP2_BLBACK_WDR_CURVE_3_OFFSET (0xC08) -#define DSP2_BLBACK_CURVE_4_PRE DSP2_BLBACK_CURVE_4_PRE -#define DSP2_BLBACK_CURVE_4_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_4_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_4_PRE_MSK (((1U << DSP2_BLBACK_CURVE_4_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_4_PRE_POS) -#define DSP2_BLBACK_CURVE_4_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_4_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_4_PRE_POS)) -#define DSP2_BLBACK_CURVE_5_PRE DSP2_BLBACK_CURVE_5_PRE -#define DSP2_BLBACK_CURVE_5_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_5_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_5_PRE_MSK (((1U << DSP2_BLBACK_CURVE_5_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_5_PRE_POS) -#define DSP2_BLBACK_CURVE_5_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_5_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_5_PRE_POS)) - -/* 0xC0C : WDR_CURVE_4 */ -#define DSP2_BLBACK_WDR_CURVE_4_OFFSET (0xC0C) -#define DSP2_BLBACK_CURVE_6_PRE DSP2_BLBACK_CURVE_6_PRE -#define DSP2_BLBACK_CURVE_6_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_6_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_6_PRE_MSK (((1U << DSP2_BLBACK_CURVE_6_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_6_PRE_POS) -#define DSP2_BLBACK_CURVE_6_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_6_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_6_PRE_POS)) -#define DSP2_BLBACK_CURVE_7_PRE DSP2_BLBACK_CURVE_7_PRE -#define DSP2_BLBACK_CURVE_7_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_7_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_7_PRE_MSK (((1U << DSP2_BLBACK_CURVE_7_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_7_PRE_POS) -#define DSP2_BLBACK_CURVE_7_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_7_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_7_PRE_POS)) - -/* 0xC10 : WDR_CURVE_5 */ -#define DSP2_BLBACK_WDR_CURVE_5_OFFSET (0xC10) -#define DSP2_BLBACK_CURVE_8_PRE DSP2_BLBACK_CURVE_8_PRE -#define DSP2_BLBACK_CURVE_8_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_8_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_8_PRE_MSK (((1U << DSP2_BLBACK_CURVE_8_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_8_PRE_POS) -#define DSP2_BLBACK_CURVE_8_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_8_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_8_PRE_POS)) -#define DSP2_BLBACK_CURVE_9_PRE DSP2_BLBACK_CURVE_9_PRE -#define DSP2_BLBACK_CURVE_9_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_9_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_9_PRE_MSK (((1U << DSP2_BLBACK_CURVE_9_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_9_PRE_POS) -#define DSP2_BLBACK_CURVE_9_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_9_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_9_PRE_POS)) - -/* 0xC14 : WDR_CURVE_6 */ -#define DSP2_BLBACK_WDR_CURVE_6_OFFSET (0xC14) -#define DSP2_BLBACK_CURVE_10_PRE DSP2_BLBACK_CURVE_10_PRE -#define DSP2_BLBACK_CURVE_10_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_10_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_10_PRE_MSK (((1U << DSP2_BLBACK_CURVE_10_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_10_PRE_POS) -#define DSP2_BLBACK_CURVE_10_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_10_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_10_PRE_POS)) -#define DSP2_BLBACK_CURVE_11_PRE DSP2_BLBACK_CURVE_11_PRE -#define DSP2_BLBACK_CURVE_11_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_11_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_11_PRE_MSK (((1U << DSP2_BLBACK_CURVE_11_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_11_PRE_POS) -#define DSP2_BLBACK_CURVE_11_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_11_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_11_PRE_POS)) - -/* 0xC18 : WDR_CURVE_7 */ -#define DSP2_BLBACK_WDR_CURVE_7_OFFSET (0xC18) -#define DSP2_BLBACK_CURVE_12_PRE DSP2_BLBACK_CURVE_12_PRE -#define DSP2_BLBACK_CURVE_12_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_12_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_12_PRE_MSK (((1U << DSP2_BLBACK_CURVE_12_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_12_PRE_POS) -#define DSP2_BLBACK_CURVE_12_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_12_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_12_PRE_POS)) -#define DSP2_BLBACK_CURVE_13_PRE DSP2_BLBACK_CURVE_13_PRE -#define DSP2_BLBACK_CURVE_13_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_13_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_13_PRE_MSK (((1U << DSP2_BLBACK_CURVE_13_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_13_PRE_POS) -#define DSP2_BLBACK_CURVE_13_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_13_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_13_PRE_POS)) - -/* 0xC1C : WDR_CURVE_8 */ -#define DSP2_BLBACK_WDR_CURVE_8_OFFSET (0xC1C) -#define DSP2_BLBACK_CURVE_14_PRE DSP2_BLBACK_CURVE_14_PRE -#define DSP2_BLBACK_CURVE_14_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_14_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_14_PRE_MSK (((1U << DSP2_BLBACK_CURVE_14_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_14_PRE_POS) -#define DSP2_BLBACK_CURVE_14_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_14_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_14_PRE_POS)) -#define DSP2_BLBACK_CURVE_15_PRE DSP2_BLBACK_CURVE_15_PRE -#define DSP2_BLBACK_CURVE_15_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_15_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_15_PRE_MSK (((1U << DSP2_BLBACK_CURVE_15_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_15_PRE_POS) -#define DSP2_BLBACK_CURVE_15_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_15_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_15_PRE_POS)) - -/* 0xC20 : WDR_CURVE_9 */ -#define DSP2_BLBACK_WDR_CURVE_9_OFFSET (0xC20) -#define DSP2_BLBACK_CURVE_16_PRE DSP2_BLBACK_CURVE_16_PRE -#define DSP2_BLBACK_CURVE_16_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_16_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_16_PRE_MSK (((1U << DSP2_BLBACK_CURVE_16_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_16_PRE_POS) -#define DSP2_BLBACK_CURVE_16_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_16_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_16_PRE_POS)) -#define DSP2_BLBACK_CURVE_17_PRE DSP2_BLBACK_CURVE_17_PRE -#define DSP2_BLBACK_CURVE_17_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_17_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_17_PRE_MSK (((1U << DSP2_BLBACK_CURVE_17_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_17_PRE_POS) -#define DSP2_BLBACK_CURVE_17_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_17_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_17_PRE_POS)) - -/* 0xC24 : WDR_CURVE_10 */ -#define DSP2_BLBACK_WDR_CURVE_10_OFFSET (0xC24) -#define DSP2_BLBACK_CURVE_18_PRE DSP2_BLBACK_CURVE_18_PRE -#define DSP2_BLBACK_CURVE_18_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_18_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_18_PRE_MSK (((1U << DSP2_BLBACK_CURVE_18_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_18_PRE_POS) -#define DSP2_BLBACK_CURVE_18_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_18_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_18_PRE_POS)) -#define DSP2_BLBACK_CURVE_19_PRE DSP2_BLBACK_CURVE_19_PRE -#define DSP2_BLBACK_CURVE_19_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_19_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_19_PRE_MSK (((1U << DSP2_BLBACK_CURVE_19_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_19_PRE_POS) -#define DSP2_BLBACK_CURVE_19_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_19_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_19_PRE_POS)) - -/* 0xC28 : WDR_CURVE_11 */ -#define DSP2_BLBACK_WDR_CURVE_11_OFFSET (0xC28) -#define DSP2_BLBACK_CURVE_20_PRE DSP2_BLBACK_CURVE_20_PRE -#define DSP2_BLBACK_CURVE_20_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_20_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_20_PRE_MSK (((1U << DSP2_BLBACK_CURVE_20_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_20_PRE_POS) -#define DSP2_BLBACK_CURVE_20_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_20_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_20_PRE_POS)) -#define DSP2_BLBACK_CURVE_21_PRE DSP2_BLBACK_CURVE_21_PRE -#define DSP2_BLBACK_CURVE_21_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_21_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_21_PRE_MSK (((1U << DSP2_BLBACK_CURVE_21_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_21_PRE_POS) -#define DSP2_BLBACK_CURVE_21_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_21_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_21_PRE_POS)) - -/* 0xC2C : WDR_CURVE_12 */ -#define DSP2_BLBACK_WDR_CURVE_12_OFFSET (0xC2C) -#define DSP2_BLBACK_CURVE_22_PRE DSP2_BLBACK_CURVE_22_PRE -#define DSP2_BLBACK_CURVE_22_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_22_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_22_PRE_MSK (((1U << DSP2_BLBACK_CURVE_22_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_22_PRE_POS) -#define DSP2_BLBACK_CURVE_22_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_22_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_22_PRE_POS)) -#define DSP2_BLBACK_CURVE_23_PRE DSP2_BLBACK_CURVE_23_PRE -#define DSP2_BLBACK_CURVE_23_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_23_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_23_PRE_MSK (((1U << DSP2_BLBACK_CURVE_23_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_23_PRE_POS) -#define DSP2_BLBACK_CURVE_23_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_23_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_23_PRE_POS)) - -/* 0xC30 : WDR_CURVE_13 */ -#define DSP2_BLBACK_WDR_CURVE_13_OFFSET (0xC30) -#define DSP2_BLBACK_CURVE_24_PRE DSP2_BLBACK_CURVE_24_PRE -#define DSP2_BLBACK_CURVE_24_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_24_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_24_PRE_MSK (((1U << DSP2_BLBACK_CURVE_24_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_24_PRE_POS) -#define DSP2_BLBACK_CURVE_24_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_24_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_24_PRE_POS)) -#define DSP2_BLBACK_CURVE_25_PRE DSP2_BLBACK_CURVE_25_PRE -#define DSP2_BLBACK_CURVE_25_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_25_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_25_PRE_MSK (((1U << DSP2_BLBACK_CURVE_25_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_25_PRE_POS) -#define DSP2_BLBACK_CURVE_25_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_25_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_25_PRE_POS)) - -/* 0xC34 : WDR_CURVE_14 */ -#define DSP2_BLBACK_WDR_CURVE_14_OFFSET (0xC34) -#define DSP2_BLBACK_CURVE_26_PRE DSP2_BLBACK_CURVE_26_PRE -#define DSP2_BLBACK_CURVE_26_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_26_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_26_PRE_MSK (((1U << DSP2_BLBACK_CURVE_26_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_26_PRE_POS) -#define DSP2_BLBACK_CURVE_26_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_26_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_26_PRE_POS)) -#define DSP2_BLBACK_CURVE_27_PRE DSP2_BLBACK_CURVE_27_PRE -#define DSP2_BLBACK_CURVE_27_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_27_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_27_PRE_MSK (((1U << DSP2_BLBACK_CURVE_27_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_27_PRE_POS) -#define DSP2_BLBACK_CURVE_27_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_27_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_27_PRE_POS)) - -/* 0xC38 : WDR_CURVE_15 */ -#define DSP2_BLBACK_WDR_CURVE_15_OFFSET (0xC38) -#define DSP2_BLBACK_CURVE_28_PRE DSP2_BLBACK_CURVE_28_PRE -#define DSP2_BLBACK_CURVE_28_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_28_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_28_PRE_MSK (((1U << DSP2_BLBACK_CURVE_28_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_28_PRE_POS) -#define DSP2_BLBACK_CURVE_28_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_28_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_28_PRE_POS)) -#define DSP2_BLBACK_CURVE_29_PRE DSP2_BLBACK_CURVE_29_PRE -#define DSP2_BLBACK_CURVE_29_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_29_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_29_PRE_MSK (((1U << DSP2_BLBACK_CURVE_29_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_29_PRE_POS) -#define DSP2_BLBACK_CURVE_29_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_29_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_29_PRE_POS)) - -/* 0xC3C : WDR_CURVE_16 */ -#define DSP2_BLBACK_WDR_CURVE_16_OFFSET (0xC3C) -#define DSP2_BLBACK_CURVE_30_PRE DSP2_BLBACK_CURVE_30_PRE -#define DSP2_BLBACK_CURVE_30_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_30_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_30_PRE_MSK (((1U << DSP2_BLBACK_CURVE_30_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_30_PRE_POS) -#define DSP2_BLBACK_CURVE_30_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_30_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_30_PRE_POS)) -#define DSP2_BLBACK_CURVE_31_PRE DSP2_BLBACK_CURVE_31_PRE -#define DSP2_BLBACK_CURVE_31_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_31_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_31_PRE_MSK (((1U << DSP2_BLBACK_CURVE_31_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_31_PRE_POS) -#define DSP2_BLBACK_CURVE_31_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_31_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_31_PRE_POS)) - -/* 0xC40 : WDR_CURVE_17 */ -#define DSP2_BLBACK_WDR_CURVE_17_OFFSET (0xC40) -#define DSP2_BLBACK_CURVE_32_PRE DSP2_BLBACK_CURVE_32_PRE -#define DSP2_BLBACK_CURVE_32_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_32_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_32_PRE_MSK (((1U << DSP2_BLBACK_CURVE_32_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_32_PRE_POS) -#define DSP2_BLBACK_CURVE_32_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_32_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_32_PRE_POS)) -#define DSP2_BLBACK_CURVE_33_PRE DSP2_BLBACK_CURVE_33_PRE -#define DSP2_BLBACK_CURVE_33_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_33_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_33_PRE_MSK (((1U << DSP2_BLBACK_CURVE_33_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_33_PRE_POS) -#define DSP2_BLBACK_CURVE_33_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_33_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_33_PRE_POS)) - -/* 0xC44 : WDR_CURVE_18 */ -#define DSP2_BLBACK_WDR_CURVE_18_OFFSET (0xC44) -#define DSP2_BLBACK_CURVE_34_PRE DSP2_BLBACK_CURVE_34_PRE -#define DSP2_BLBACK_CURVE_34_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_34_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_34_PRE_MSK (((1U << DSP2_BLBACK_CURVE_34_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_34_PRE_POS) -#define DSP2_BLBACK_CURVE_34_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_34_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_34_PRE_POS)) -#define DSP2_BLBACK_CURVE_35_PRE DSP2_BLBACK_CURVE_35_PRE -#define DSP2_BLBACK_CURVE_35_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_35_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_35_PRE_MSK (((1U << DSP2_BLBACK_CURVE_35_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_35_PRE_POS) -#define DSP2_BLBACK_CURVE_35_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_35_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_35_PRE_POS)) - -/* 0xC48 : WDR_CURVE_19 */ -#define DSP2_BLBACK_WDR_CURVE_19_OFFSET (0xC48) -#define DSP2_BLBACK_CURVE_36_PRE DSP2_BLBACK_CURVE_36_PRE -#define DSP2_BLBACK_CURVE_36_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_36_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_36_PRE_MSK (((1U << DSP2_BLBACK_CURVE_36_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_36_PRE_POS) -#define DSP2_BLBACK_CURVE_36_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_36_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_36_PRE_POS)) -#define DSP2_BLBACK_CURVE_37_PRE DSP2_BLBACK_CURVE_37_PRE -#define DSP2_BLBACK_CURVE_37_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_37_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_37_PRE_MSK (((1U << DSP2_BLBACK_CURVE_37_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_37_PRE_POS) -#define DSP2_BLBACK_CURVE_37_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_37_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_37_PRE_POS)) - -/* 0xC4C : WDR_CURVE_20 */ -#define DSP2_BLBACK_WDR_CURVE_20_OFFSET (0xC4C) -#define DSP2_BLBACK_CURVE_38_PRE DSP2_BLBACK_CURVE_38_PRE -#define DSP2_BLBACK_CURVE_38_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_38_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_38_PRE_MSK (((1U << DSP2_BLBACK_CURVE_38_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_38_PRE_POS) -#define DSP2_BLBACK_CURVE_38_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_38_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_38_PRE_POS)) -#define DSP2_BLBACK_CURVE_39_PRE DSP2_BLBACK_CURVE_39_PRE -#define DSP2_BLBACK_CURVE_39_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_39_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_39_PRE_MSK (((1U << DSP2_BLBACK_CURVE_39_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_39_PRE_POS) -#define DSP2_BLBACK_CURVE_39_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_39_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_39_PRE_POS)) - -/* 0xC50 : WDR_CURVE_21 */ -#define DSP2_BLBACK_WDR_CURVE_21_OFFSET (0xC50) -#define DSP2_BLBACK_CURVE_40_PRE DSP2_BLBACK_CURVE_40_PRE -#define DSP2_BLBACK_CURVE_40_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_40_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_40_PRE_MSK (((1U << DSP2_BLBACK_CURVE_40_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_40_PRE_POS) -#define DSP2_BLBACK_CURVE_40_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_40_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_40_PRE_POS)) -#define DSP2_BLBACK_CURVE_41_PRE DSP2_BLBACK_CURVE_41_PRE -#define DSP2_BLBACK_CURVE_41_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_41_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_41_PRE_MSK (((1U << DSP2_BLBACK_CURVE_41_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_41_PRE_POS) -#define DSP2_BLBACK_CURVE_41_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_41_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_41_PRE_POS)) - -/* 0xC54 : WDR_CURVE_22 */ -#define DSP2_BLBACK_WDR_CURVE_22_OFFSET (0xC54) -#define DSP2_BLBACK_CURVE_42_PRE DSP2_BLBACK_CURVE_42_PRE -#define DSP2_BLBACK_CURVE_42_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_42_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_42_PRE_MSK (((1U << DSP2_BLBACK_CURVE_42_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_42_PRE_POS) -#define DSP2_BLBACK_CURVE_42_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_42_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_42_PRE_POS)) -#define DSP2_BLBACK_CURVE_43_PRE DSP2_BLBACK_CURVE_43_PRE -#define DSP2_BLBACK_CURVE_43_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_43_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_43_PRE_MSK (((1U << DSP2_BLBACK_CURVE_43_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_43_PRE_POS) -#define DSP2_BLBACK_CURVE_43_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_43_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_43_PRE_POS)) - -/* 0xC58 : WDR_CURVE_23 */ -#define DSP2_BLBACK_WDR_CURVE_23_OFFSET (0xC58) -#define DSP2_BLBACK_CURVE_44_PRE DSP2_BLBACK_CURVE_44_PRE -#define DSP2_BLBACK_CURVE_44_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_44_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_44_PRE_MSK (((1U << DSP2_BLBACK_CURVE_44_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_44_PRE_POS) -#define DSP2_BLBACK_CURVE_44_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_44_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_44_PRE_POS)) -#define DSP2_BLBACK_CURVE_45_PRE DSP2_BLBACK_CURVE_45_PRE -#define DSP2_BLBACK_CURVE_45_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_45_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_45_PRE_MSK (((1U << DSP2_BLBACK_CURVE_45_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_45_PRE_POS) -#define DSP2_BLBACK_CURVE_45_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_45_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_45_PRE_POS)) - -/* 0xC5C : WDR_CURVE_24 */ -#define DSP2_BLBACK_WDR_CURVE_24_OFFSET (0xC5C) -#define DSP2_BLBACK_CURVE_46_PRE DSP2_BLBACK_CURVE_46_PRE -#define DSP2_BLBACK_CURVE_46_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_46_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_46_PRE_MSK (((1U << DSP2_BLBACK_CURVE_46_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_46_PRE_POS) -#define DSP2_BLBACK_CURVE_46_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_46_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_46_PRE_POS)) -#define DSP2_BLBACK_CURVE_47_PRE DSP2_BLBACK_CURVE_47_PRE -#define DSP2_BLBACK_CURVE_47_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_47_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_47_PRE_MSK (((1U << DSP2_BLBACK_CURVE_47_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_47_PRE_POS) -#define DSP2_BLBACK_CURVE_47_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_47_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_47_PRE_POS)) - -/* 0xC60 : WDR_CURVE_25 */ -#define DSP2_BLBACK_WDR_CURVE_25_OFFSET (0xC60) -#define DSP2_BLBACK_CURVE_48_PRE DSP2_BLBACK_CURVE_48_PRE -#define DSP2_BLBACK_CURVE_48_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_48_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_48_PRE_MSK (((1U << DSP2_BLBACK_CURVE_48_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_48_PRE_POS) -#define DSP2_BLBACK_CURVE_48_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_48_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_48_PRE_POS)) -#define DSP2_BLBACK_CURVE_49_PRE DSP2_BLBACK_CURVE_49_PRE -#define DSP2_BLBACK_CURVE_49_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_49_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_49_PRE_MSK (((1U << DSP2_BLBACK_CURVE_49_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_49_PRE_POS) -#define DSP2_BLBACK_CURVE_49_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_49_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_49_PRE_POS)) - -/* 0xC64 : WDR_CURVE_26 */ -#define DSP2_BLBACK_WDR_CURVE_26_OFFSET (0xC64) -#define DSP2_BLBACK_CURVE_50_PRE DSP2_BLBACK_CURVE_50_PRE -#define DSP2_BLBACK_CURVE_50_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_50_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_50_PRE_MSK (((1U << DSP2_BLBACK_CURVE_50_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_50_PRE_POS) -#define DSP2_BLBACK_CURVE_50_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_50_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_50_PRE_POS)) -#define DSP2_BLBACK_CURVE_51_PRE DSP2_BLBACK_CURVE_51_PRE -#define DSP2_BLBACK_CURVE_51_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_51_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_51_PRE_MSK (((1U << DSP2_BLBACK_CURVE_51_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_51_PRE_POS) -#define DSP2_BLBACK_CURVE_51_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_51_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_51_PRE_POS)) - -/* 0xC68 : WDR_CURVE_27 */ -#define DSP2_BLBACK_WDR_CURVE_27_OFFSET (0xC68) -#define DSP2_BLBACK_CURVE_52_PRE DSP2_BLBACK_CURVE_52_PRE -#define DSP2_BLBACK_CURVE_52_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_52_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_52_PRE_MSK (((1U << DSP2_BLBACK_CURVE_52_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_52_PRE_POS) -#define DSP2_BLBACK_CURVE_52_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_52_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_52_PRE_POS)) -#define DSP2_BLBACK_CURVE_53_PRE DSP2_BLBACK_CURVE_53_PRE -#define DSP2_BLBACK_CURVE_53_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_53_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_53_PRE_MSK (((1U << DSP2_BLBACK_CURVE_53_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_53_PRE_POS) -#define DSP2_BLBACK_CURVE_53_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_53_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_53_PRE_POS)) - -/* 0xC6C : WDR_CURVE_28 */ -#define DSP2_BLBACK_WDR_CURVE_28_OFFSET (0xC6C) -#define DSP2_BLBACK_CURVE_54_PRE DSP2_BLBACK_CURVE_54_PRE -#define DSP2_BLBACK_CURVE_54_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_54_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_54_PRE_MSK (((1U << DSP2_BLBACK_CURVE_54_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_54_PRE_POS) -#define DSP2_BLBACK_CURVE_54_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_54_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_54_PRE_POS)) -#define DSP2_BLBACK_CURVE_55_PRE DSP2_BLBACK_CURVE_55_PRE -#define DSP2_BLBACK_CURVE_55_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_55_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_55_PRE_MSK (((1U << DSP2_BLBACK_CURVE_55_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_55_PRE_POS) -#define DSP2_BLBACK_CURVE_55_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_55_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_55_PRE_POS)) - -/* 0xC70 : WDR_CURVE_29 */ -#define DSP2_BLBACK_WDR_CURVE_29_OFFSET (0xC70) -#define DSP2_BLBACK_CURVE_56_PRE DSP2_BLBACK_CURVE_56_PRE -#define DSP2_BLBACK_CURVE_56_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_56_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_56_PRE_MSK (((1U << DSP2_BLBACK_CURVE_56_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_56_PRE_POS) -#define DSP2_BLBACK_CURVE_56_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_56_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_56_PRE_POS)) -#define DSP2_BLBACK_CURVE_57_PRE DSP2_BLBACK_CURVE_57_PRE -#define DSP2_BLBACK_CURVE_57_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_57_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_57_PRE_MSK (((1U << DSP2_BLBACK_CURVE_57_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_57_PRE_POS) -#define DSP2_BLBACK_CURVE_57_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_57_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_57_PRE_POS)) - -/* 0xC74 : WDR_CURVE_30 */ -#define DSP2_BLBACK_WDR_CURVE_30_OFFSET (0xC74) -#define DSP2_BLBACK_CURVE_58_PRE DSP2_BLBACK_CURVE_58_PRE -#define DSP2_BLBACK_CURVE_58_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_58_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_58_PRE_MSK (((1U << DSP2_BLBACK_CURVE_58_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_58_PRE_POS) -#define DSP2_BLBACK_CURVE_58_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_58_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_58_PRE_POS)) -#define DSP2_BLBACK_CURVE_59_PRE DSP2_BLBACK_CURVE_59_PRE -#define DSP2_BLBACK_CURVE_59_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_59_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_59_PRE_MSK (((1U << DSP2_BLBACK_CURVE_59_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_59_PRE_POS) -#define DSP2_BLBACK_CURVE_59_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_59_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_59_PRE_POS)) - -/* 0xC78 : WDR_CURVE_31 */ -#define DSP2_BLBACK_WDR_CURVE_31_OFFSET (0xC78) -#define DSP2_BLBACK_CURVE_60_PRE DSP2_BLBACK_CURVE_60_PRE -#define DSP2_BLBACK_CURVE_60_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_60_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_60_PRE_MSK (((1U << DSP2_BLBACK_CURVE_60_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_60_PRE_POS) -#define DSP2_BLBACK_CURVE_60_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_60_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_60_PRE_POS)) -#define DSP2_BLBACK_CURVE_61_PRE DSP2_BLBACK_CURVE_61_PRE -#define DSP2_BLBACK_CURVE_61_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_61_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_61_PRE_MSK (((1U << DSP2_BLBACK_CURVE_61_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_61_PRE_POS) -#define DSP2_BLBACK_CURVE_61_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_61_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_61_PRE_POS)) - -/* 0xC7C : WDR_CURVE_32 */ -#define DSP2_BLBACK_WDR_CURVE_32_OFFSET (0xC7C) -#define DSP2_BLBACK_CURVE_62_PRE DSP2_BLBACK_CURVE_62_PRE -#define DSP2_BLBACK_CURVE_62_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_62_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_62_PRE_MSK (((1U << DSP2_BLBACK_CURVE_62_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_62_PRE_POS) -#define DSP2_BLBACK_CURVE_62_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_62_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_62_PRE_POS)) -#define DSP2_BLBACK_CURVE_63_PRE DSP2_BLBACK_CURVE_63_PRE -#define DSP2_BLBACK_CURVE_63_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_63_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_63_PRE_MSK (((1U << DSP2_BLBACK_CURVE_63_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_63_PRE_POS) -#define DSP2_BLBACK_CURVE_63_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_63_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_63_PRE_POS)) - -/* 0xC80 : WDR_CURVE_33 */ -#define DSP2_BLBACK_WDR_CURVE_33_OFFSET (0xC80) -#define DSP2_BLBACK_CURVE_EN_PRE DSP2_BLBACK_CURVE_EN_PRE -#define DSP2_BLBACK_CURVE_EN_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_EN_PRE_LEN (1U) -#define DSP2_BLBACK_CURVE_EN_PRE_MSK (((1U << DSP2_BLBACK_CURVE_EN_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_EN_PRE_POS) -#define DSP2_BLBACK_CURVE_EN_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_EN_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_EN_PRE_POS)) -#define DSP2_BLBACK_CURVE_WEIGHT_PRE DSP2_BLBACK_CURVE_WEIGHT_PRE -#define DSP2_BLBACK_CURVE_WEIGHT_PRE_POS (8U) -#define DSP2_BLBACK_CURVE_WEIGHT_PRE_LEN (5U) -#define DSP2_BLBACK_CURVE_WEIGHT_PRE_MSK (((1U << DSP2_BLBACK_CURVE_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_WEIGHT_PRE_POS) -#define DSP2_BLBACK_CURVE_WEIGHT_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_WEIGHT_PRE_POS)) - -/* 0xC84 : WDR_ENH_1 */ -#define DSP2_BLBACK_WDR_ENH_1_OFFSET (0xC84) -#define DSP2_BLBACK_ENH_EN_PRE DSP2_BLBACK_ENH_EN_PRE -#define DSP2_BLBACK_ENH_EN_PRE_POS (0U) -#define DSP2_BLBACK_ENH_EN_PRE_LEN (1U) -#define DSP2_BLBACK_ENH_EN_PRE_MSK (((1U << DSP2_BLBACK_ENH_EN_PRE_LEN) - 1) << DSP2_BLBACK_ENH_EN_PRE_POS) -#define DSP2_BLBACK_ENH_EN_PRE_UMSK (~(((1U << DSP2_BLBACK_ENH_EN_PRE_LEN) - 1) << DSP2_BLBACK_ENH_EN_PRE_POS)) -#define DSP2_BLBACK_ENH_WEIGHT_PRE DSP2_BLBACK_ENH_WEIGHT_PRE -#define DSP2_BLBACK_ENH_WEIGHT_PRE_POS (8U) -#define DSP2_BLBACK_ENH_WEIGHT_PRE_LEN (5U) -#define DSP2_BLBACK_ENH_WEIGHT_PRE_MSK (((1U << DSP2_BLBACK_ENH_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_ENH_WEIGHT_PRE_POS) -#define DSP2_BLBACK_ENH_WEIGHT_PRE_UMSK (~(((1U << DSP2_BLBACK_ENH_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_ENH_WEIGHT_PRE_POS)) -#define DSP2_BLBACK_ENH_Y_OFFSET_PRE DSP2_BLBACK_ENH_Y_OFFSET_PRE -#define DSP2_BLBACK_ENH_Y_OFFSET_PRE_POS (16U) -#define DSP2_BLBACK_ENH_Y_OFFSET_PRE_LEN (12U) -#define DSP2_BLBACK_ENH_Y_OFFSET_PRE_MSK (((1U << DSP2_BLBACK_ENH_Y_OFFSET_PRE_LEN) - 1) << DSP2_BLBACK_ENH_Y_OFFSET_PRE_POS) -#define DSP2_BLBACK_ENH_Y_OFFSET_PRE_UMSK (~(((1U << DSP2_BLBACK_ENH_Y_OFFSET_PRE_LEN) - 1) << DSP2_BLBACK_ENH_Y_OFFSET_PRE_POS)) - -/* 0xC88 : WDR_ENH_2 */ -#define DSP2_BLBACK_WDR_ENH_2_OFFSET (0xC88) -#define DSP2_BLBACK_ENH_C_GAIN_PRE DSP2_BLBACK_ENH_C_GAIN_PRE -#define DSP2_BLBACK_ENH_C_GAIN_PRE_POS (0U) -#define DSP2_BLBACK_ENH_C_GAIN_PRE_LEN (15U) -#define DSP2_BLBACK_ENH_C_GAIN_PRE_MSK (((1U << DSP2_BLBACK_ENH_C_GAIN_PRE_LEN) - 1) << DSP2_BLBACK_ENH_C_GAIN_PRE_POS) -#define DSP2_BLBACK_ENH_C_GAIN_PRE_UMSK (~(((1U << DSP2_BLBACK_ENH_C_GAIN_PRE_LEN) - 1) << DSP2_BLBACK_ENH_C_GAIN_PRE_POS)) -#define DSP2_BLBACK_ENH_Y_GAIN_PRE DSP2_BLBACK_ENH_Y_GAIN_PRE -#define DSP2_BLBACK_ENH_Y_GAIN_PRE_POS (16U) -#define DSP2_BLBACK_ENH_Y_GAIN_PRE_LEN (15U) -#define DSP2_BLBACK_ENH_Y_GAIN_PRE_MSK (((1U << DSP2_BLBACK_ENH_Y_GAIN_PRE_LEN) - 1) << DSP2_BLBACK_ENH_Y_GAIN_PRE_POS) -#define DSP2_BLBACK_ENH_Y_GAIN_PRE_UMSK (~(((1U << DSP2_BLBACK_ENH_Y_GAIN_PRE_LEN) - 1) << DSP2_BLBACK_ENH_Y_GAIN_PRE_POS)) - -/* 0xD00 : BL_GAMMA_TABLE_1 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_1_OFFSET (0xD00) -#define DSP2_BLBACK_GAMMA_TABLE0_PRE DSP2_BLBACK_GAMMA_TABLE0_PRE -#define DSP2_BLBACK_GAMMA_TABLE0_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE0_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE0_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE0_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE0_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE0_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE0_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE0_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE1_PRE DSP2_BLBACK_GAMMA_TABLE1_PRE -#define DSP2_BLBACK_GAMMA_TABLE1_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE1_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE1_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE1_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE1_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE1_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE1_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE1_PRE_POS)) - -/* 0xD04 : BL_GAMMA_TABLE_2 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_2_OFFSET (0xD04) -#define DSP2_BLBACK_GAMMA_TABLE2_PRE DSP2_BLBACK_GAMMA_TABLE2_PRE -#define DSP2_BLBACK_GAMMA_TABLE2_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE2_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE2_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE2_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE2_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE2_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE2_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE2_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE3_PRE DSP2_BLBACK_GAMMA_TABLE3_PRE -#define DSP2_BLBACK_GAMMA_TABLE3_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE3_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE3_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE3_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE3_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE3_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE3_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE3_PRE_POS)) - -/* 0xD08 : BL_GAMMA_TABLE_3 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_3_OFFSET (0xD08) -#define DSP2_BLBACK_GAMMA_TABLE4_PRE DSP2_BLBACK_GAMMA_TABLE4_PRE -#define DSP2_BLBACK_GAMMA_TABLE4_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE4_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE4_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE4_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE4_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE4_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE4_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE4_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE5_PRE DSP2_BLBACK_GAMMA_TABLE5_PRE -#define DSP2_BLBACK_GAMMA_TABLE5_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE5_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE5_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE5_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE5_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE5_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE5_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE5_PRE_POS)) - -/* 0xD0C : BL_GAMMA_TABLE_4 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_4_OFFSET (0xD0C) -#define DSP2_BLBACK_GAMMA_TABLE6_PRE DSP2_BLBACK_GAMMA_TABLE6_PRE -#define DSP2_BLBACK_GAMMA_TABLE6_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE6_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE6_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE6_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE6_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE6_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE6_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE6_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE7_PRE DSP2_BLBACK_GAMMA_TABLE7_PRE -#define DSP2_BLBACK_GAMMA_TABLE7_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE7_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE7_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE7_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE7_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE7_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE7_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE7_PRE_POS)) - -/* 0xD10 : BL_GAMMA_TABLE_5 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_5_OFFSET (0xD10) -#define DSP2_BLBACK_GAMMA_TABLE8_PRE DSP2_BLBACK_GAMMA_TABLE8_PRE -#define DSP2_BLBACK_GAMMA_TABLE8_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE8_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE8_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE8_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE8_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE8_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE8_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE8_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE9_PRE DSP2_BLBACK_GAMMA_TABLE9_PRE -#define DSP2_BLBACK_GAMMA_TABLE9_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE9_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE9_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE9_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE9_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE9_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE9_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE9_PRE_POS)) - -/* 0xD14 : BL_GAMMA_TABLE_6 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_6_OFFSET (0xD14) -#define DSP2_BLBACK_GAMMA_TABLE10_PRE DSP2_BLBACK_GAMMA_TABLE10_PRE -#define DSP2_BLBACK_GAMMA_TABLE10_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE10_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE10_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE10_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE10_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE10_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE10_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE10_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE11_PRE DSP2_BLBACK_GAMMA_TABLE11_PRE -#define DSP2_BLBACK_GAMMA_TABLE11_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE11_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE11_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE11_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE11_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE11_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE11_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE11_PRE_POS)) - -/* 0xD18 : BL_GAMMA_TABLE_7 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_7_OFFSET (0xD18) -#define DSP2_BLBACK_GAMMA_TABLE12_PRE DSP2_BLBACK_GAMMA_TABLE12_PRE -#define DSP2_BLBACK_GAMMA_TABLE12_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE12_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE12_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE12_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE12_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE12_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE12_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE12_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE13_PRE DSP2_BLBACK_GAMMA_TABLE13_PRE -#define DSP2_BLBACK_GAMMA_TABLE13_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE13_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE13_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE13_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE13_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE13_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE13_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE13_PRE_POS)) - -/* 0xD1C : BL_GAMMA_TABLE_8 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_8_OFFSET (0xD1C) -#define DSP2_BLBACK_GAMMA_TABLE14_PRE DSP2_BLBACK_GAMMA_TABLE14_PRE -#define DSP2_BLBACK_GAMMA_TABLE14_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE14_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE14_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE14_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE14_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE14_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE14_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE14_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE15_PRE DSP2_BLBACK_GAMMA_TABLE15_PRE -#define DSP2_BLBACK_GAMMA_TABLE15_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE15_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE15_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE15_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE15_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE15_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE15_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE15_PRE_POS)) - -/* 0xD20 : BL_GAMMA_TABLE_9 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_9_OFFSET (0xD20) -#define DSP2_BLBACK_GAMMA_TABLE16_PRE DSP2_BLBACK_GAMMA_TABLE16_PRE -#define DSP2_BLBACK_GAMMA_TABLE16_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE16_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE16_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE16_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE16_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE16_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE16_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE16_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE17_PRE DSP2_BLBACK_GAMMA_TABLE17_PRE -#define DSP2_BLBACK_GAMMA_TABLE17_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE17_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE17_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE17_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE17_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE17_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE17_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE17_PRE_POS)) - -/* 0xD24 : BL_GAMMA_TABLE_10 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_10_OFFSET (0xD24) -#define DSP2_BLBACK_GAMMA_TABLE18_PRE DSP2_BLBACK_GAMMA_TABLE18_PRE -#define DSP2_BLBACK_GAMMA_TABLE18_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE18_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE18_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE18_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE18_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE18_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE18_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE18_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE19_PRE DSP2_BLBACK_GAMMA_TABLE19_PRE -#define DSP2_BLBACK_GAMMA_TABLE19_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE19_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE19_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE19_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE19_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE19_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE19_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE19_PRE_POS)) - -/* 0xD28 : BL_GAMMA_TABLE_11 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_11_OFFSET (0xD28) -#define DSP2_BLBACK_GAMMA_TABLE20_PRE DSP2_BLBACK_GAMMA_TABLE20_PRE -#define DSP2_BLBACK_GAMMA_TABLE20_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE20_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE20_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE20_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE20_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE20_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE20_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE20_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE21_PRE DSP2_BLBACK_GAMMA_TABLE21_PRE -#define DSP2_BLBACK_GAMMA_TABLE21_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE21_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE21_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE21_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE21_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE21_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE21_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE21_PRE_POS)) - -/* 0xD2C : BL_GAMMA_TABLE_12 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_12_OFFSET (0xD2C) -#define DSP2_BLBACK_GAMMA_TABLE22_PRE DSP2_BLBACK_GAMMA_TABLE22_PRE -#define DSP2_BLBACK_GAMMA_TABLE22_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE22_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE22_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE22_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE22_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE22_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE22_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE22_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE23_PRE DSP2_BLBACK_GAMMA_TABLE23_PRE -#define DSP2_BLBACK_GAMMA_TABLE23_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE23_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE23_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE23_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE23_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE23_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE23_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE23_PRE_POS)) - -/* 0xD30 : BL_GAMMA_TABLE_13 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_13_OFFSET (0xD30) -#define DSP2_BLBACK_GAMMA_TABLE24_PRE DSP2_BLBACK_GAMMA_TABLE24_PRE -#define DSP2_BLBACK_GAMMA_TABLE24_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE24_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE24_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE24_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE24_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE24_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE24_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE24_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE25_PRE DSP2_BLBACK_GAMMA_TABLE25_PRE -#define DSP2_BLBACK_GAMMA_TABLE25_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE25_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE25_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE25_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE25_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE25_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE25_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE25_PRE_POS)) - -/* 0xD34 : BL_GAMMA_TABLE_14 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_14_OFFSET (0xD34) -#define DSP2_BLBACK_GAMMA_TABLE26_PRE DSP2_BLBACK_GAMMA_TABLE26_PRE -#define DSP2_BLBACK_GAMMA_TABLE26_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE26_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE26_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE26_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE26_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE26_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE26_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE26_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE27_PRE DSP2_BLBACK_GAMMA_TABLE27_PRE -#define DSP2_BLBACK_GAMMA_TABLE27_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE27_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE27_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE27_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE27_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE27_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE27_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE27_PRE_POS)) - -/* 0xD38 : BL_GAMMA_TABLE_15 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_15_OFFSET (0xD38) -#define DSP2_BLBACK_GAMMA_TABLE28_PRE DSP2_BLBACK_GAMMA_TABLE28_PRE -#define DSP2_BLBACK_GAMMA_TABLE28_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE28_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE28_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE28_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE28_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE28_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE28_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE28_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE29_PRE DSP2_BLBACK_GAMMA_TABLE29_PRE -#define DSP2_BLBACK_GAMMA_TABLE29_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE29_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE29_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE29_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE29_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE29_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE29_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE29_PRE_POS)) - -/* 0xD3C : BL_GAMMA_TABLE_16 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_16_OFFSET (0xD3C) -#define DSP2_BLBACK_GAMMA_TABLE30_PRE DSP2_BLBACK_GAMMA_TABLE30_PRE -#define DSP2_BLBACK_GAMMA_TABLE30_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE30_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE30_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE30_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE30_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE30_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE30_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE30_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE31_PRE DSP2_BLBACK_GAMMA_TABLE31_PRE -#define DSP2_BLBACK_GAMMA_TABLE31_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE31_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE31_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE31_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE31_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE31_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE31_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE31_PRE_POS)) - -/* 0xD40 : BL_GAMMA_TABLE_17 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_17_OFFSET (0xD40) -#define DSP2_BLBACK_GAMMA_TABLE32_PRE DSP2_BLBACK_GAMMA_TABLE32_PRE -#define DSP2_BLBACK_GAMMA_TABLE32_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE32_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE32_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE32_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE32_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE32_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE32_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE32_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE33_PRE DSP2_BLBACK_GAMMA_TABLE33_PRE -#define DSP2_BLBACK_GAMMA_TABLE33_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE33_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE33_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE33_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE33_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE33_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE33_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE33_PRE_POS)) - -/* 0xD44 : BL_GAMMA_TABLE_18 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_18_OFFSET (0xD44) -#define DSP2_BLBACK_GAMMA_TABLE34_PRE DSP2_BLBACK_GAMMA_TABLE34_PRE -#define DSP2_BLBACK_GAMMA_TABLE34_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE34_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE34_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE34_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE34_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE34_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE34_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE34_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE35_PRE DSP2_BLBACK_GAMMA_TABLE35_PRE -#define DSP2_BLBACK_GAMMA_TABLE35_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE35_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE35_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE35_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE35_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE35_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE35_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE35_PRE_POS)) - -/* 0xD48 : BL_GAMMA_TABLE_19 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_19_OFFSET (0xD48) -#define DSP2_BLBACK_GAMMA_TABLE36_PRE DSP2_BLBACK_GAMMA_TABLE36_PRE -#define DSP2_BLBACK_GAMMA_TABLE36_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE36_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE36_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE36_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE36_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE36_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE36_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE36_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE37_PRE DSP2_BLBACK_GAMMA_TABLE37_PRE -#define DSP2_BLBACK_GAMMA_TABLE37_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE37_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE37_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE37_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE37_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE37_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE37_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE37_PRE_POS)) - -/* 0xD4C : BL_GAMMA_TABLE_20 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_20_OFFSET (0xD4C) -#define DSP2_BLBACK_GAMMA_TABLE38_PRE DSP2_BLBACK_GAMMA_TABLE38_PRE -#define DSP2_BLBACK_GAMMA_TABLE38_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE38_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE38_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE38_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE38_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE38_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE38_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE38_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE39_PRE DSP2_BLBACK_GAMMA_TABLE39_PRE -#define DSP2_BLBACK_GAMMA_TABLE39_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE39_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE39_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE39_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE39_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE39_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE39_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE39_PRE_POS)) - -/* 0xD50 : BL_GAMMA_TABLE_21 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_21_OFFSET (0xD50) -#define DSP2_BLBACK_GAMMA_TABLE40_PRE DSP2_BLBACK_GAMMA_TABLE40_PRE -#define DSP2_BLBACK_GAMMA_TABLE40_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE40_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE40_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE40_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE40_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE40_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE40_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE40_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE41_PRE DSP2_BLBACK_GAMMA_TABLE41_PRE -#define DSP2_BLBACK_GAMMA_TABLE41_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE41_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE41_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE41_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE41_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE41_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE41_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE41_PRE_POS)) - -/* 0xD54 : BL_GAMMA_TABLE_22 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_22_OFFSET (0xD54) -#define DSP2_BLBACK_GAMMA_TABLE42_PRE DSP2_BLBACK_GAMMA_TABLE42_PRE -#define DSP2_BLBACK_GAMMA_TABLE42_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE42_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE42_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE42_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE42_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE42_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE42_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE42_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE43_PRE DSP2_BLBACK_GAMMA_TABLE43_PRE -#define DSP2_BLBACK_GAMMA_TABLE43_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE43_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE43_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE43_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE43_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE43_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE43_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE43_PRE_POS)) - -/* 0xD58 : BL_GAMMA_TABLE_23 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_23_OFFSET (0xD58) -#define DSP2_BLBACK_GAMMA_TABLE44_PRE DSP2_BLBACK_GAMMA_TABLE44_PRE -#define DSP2_BLBACK_GAMMA_TABLE44_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE44_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE44_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE44_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE44_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE44_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE44_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE44_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE45_PRE DSP2_BLBACK_GAMMA_TABLE45_PRE -#define DSP2_BLBACK_GAMMA_TABLE45_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE45_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE45_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE45_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE45_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE45_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE45_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE45_PRE_POS)) - -/* 0xD5C : BL_GAMMA_TABLE_24 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_24_OFFSET (0xD5C) -#define DSP2_BLBACK_GAMMA_TABLE46_PRE DSP2_BLBACK_GAMMA_TABLE46_PRE -#define DSP2_BLBACK_GAMMA_TABLE46_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE46_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE46_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE46_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE46_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE46_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE46_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE46_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE47_PRE DSP2_BLBACK_GAMMA_TABLE47_PRE -#define DSP2_BLBACK_GAMMA_TABLE47_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE47_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE47_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE47_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE47_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE47_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE47_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE47_PRE_POS)) - -/* 0xD60 : BL_GAMMA_TABLE_25 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_25_OFFSET (0xD60) -#define DSP2_BLBACK_GAMMA_TABLE48_PRE DSP2_BLBACK_GAMMA_TABLE48_PRE -#define DSP2_BLBACK_GAMMA_TABLE48_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE48_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE48_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE48_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE48_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE48_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE48_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE48_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE49_PRE DSP2_BLBACK_GAMMA_TABLE49_PRE -#define DSP2_BLBACK_GAMMA_TABLE49_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE49_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE49_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE49_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE49_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE49_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE49_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE49_PRE_POS)) - -/* 0xD64 : BL_GAMMA_TABLE_26 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_26_OFFSET (0xD64) -#define DSP2_BLBACK_GAMMA_TABLE50_PRE DSP2_BLBACK_GAMMA_TABLE50_PRE -#define DSP2_BLBACK_GAMMA_TABLE50_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE50_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE50_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE50_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE50_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE50_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE50_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE50_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE51_PRE DSP2_BLBACK_GAMMA_TABLE51_PRE -#define DSP2_BLBACK_GAMMA_TABLE51_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE51_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE51_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE51_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE51_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE51_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE51_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE51_PRE_POS)) - -/* 0xD68 : BL_GAMMA_TABLE_27 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_27_OFFSET (0xD68) -#define DSP2_BLBACK_GAMMA_TABLE52_PRE DSP2_BLBACK_GAMMA_TABLE52_PRE -#define DSP2_BLBACK_GAMMA_TABLE52_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE52_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE52_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE52_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE52_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE52_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE52_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE52_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE53_PRE DSP2_BLBACK_GAMMA_TABLE53_PRE -#define DSP2_BLBACK_GAMMA_TABLE53_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE53_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE53_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE53_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE53_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE53_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE53_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE53_PRE_POS)) - -/* 0xD6C : BL_GAMMA_TABLE_28 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_28_OFFSET (0xD6C) -#define DSP2_BLBACK_GAMMA_TABLE54_PRE DSP2_BLBACK_GAMMA_TABLE54_PRE -#define DSP2_BLBACK_GAMMA_TABLE54_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE54_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE54_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE54_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE54_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE54_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE54_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE54_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE55_PRE DSP2_BLBACK_GAMMA_TABLE55_PRE -#define DSP2_BLBACK_GAMMA_TABLE55_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE55_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE55_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE55_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE55_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE55_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE55_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE55_PRE_POS)) - -/* 0xD70 : BL_GAMMA_TABLE_29 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_29_OFFSET (0xD70) -#define DSP2_BLBACK_GAMMA_TABLE56_PRE DSP2_BLBACK_GAMMA_TABLE56_PRE -#define DSP2_BLBACK_GAMMA_TABLE56_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE56_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE56_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE56_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE56_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE56_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE56_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE56_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE57_PRE DSP2_BLBACK_GAMMA_TABLE57_PRE -#define DSP2_BLBACK_GAMMA_TABLE57_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE57_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE57_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE57_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE57_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE57_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE57_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE57_PRE_POS)) - -/* 0xD74 : BL_GAMMA_TABLE_30 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_30_OFFSET (0xD74) -#define DSP2_BLBACK_GAMMA_TABLE58_PRE DSP2_BLBACK_GAMMA_TABLE58_PRE -#define DSP2_BLBACK_GAMMA_TABLE58_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE58_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE58_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE58_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE58_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE58_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE58_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE58_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE59_PRE DSP2_BLBACK_GAMMA_TABLE59_PRE -#define DSP2_BLBACK_GAMMA_TABLE59_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE59_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE59_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE59_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE59_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE59_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE59_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE59_PRE_POS)) - -/* 0xD78 : BL_GAMMA_TABLE_31 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_31_OFFSET (0xD78) -#define DSP2_BLBACK_GAMMA_TABLE60_PRE DSP2_BLBACK_GAMMA_TABLE60_PRE -#define DSP2_BLBACK_GAMMA_TABLE60_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE60_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE60_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE60_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE60_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE60_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE60_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE60_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE61_PRE DSP2_BLBACK_GAMMA_TABLE61_PRE -#define DSP2_BLBACK_GAMMA_TABLE61_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE61_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE61_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE61_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE61_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE61_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE61_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE61_PRE_POS)) - -/* 0xD7C : BL_GAMMA_TABLE_32 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_32_OFFSET (0xD7C) -#define DSP2_BLBACK_GAMMA_TABLE62_PRE DSP2_BLBACK_GAMMA_TABLE62_PRE -#define DSP2_BLBACK_GAMMA_TABLE62_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE62_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE62_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE62_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE62_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE62_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE62_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE62_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE63_PRE DSP2_BLBACK_GAMMA_TABLE63_PRE -#define DSP2_BLBACK_GAMMA_TABLE63_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE63_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE63_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE63_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE63_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE63_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE63_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE63_PRE_POS)) - -/* 0xD80 : BL_GAMMA_TABLE_33 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_33_OFFSET (0xD80) -#define DSP2_BLBACK_GAMMA_TABLE64_PRE DSP2_BLBACK_GAMMA_TABLE64_PRE -#define DSP2_BLBACK_GAMMA_TABLE64_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE64_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE64_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE64_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE64_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE64_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE64_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE64_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE65_PRE DSP2_BLBACK_GAMMA_TABLE65_PRE -#define DSP2_BLBACK_GAMMA_TABLE65_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE65_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE65_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE65_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE65_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE65_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE65_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE65_PRE_POS)) - -/* 0xD84 : BL_GAMMA_TABLE_34 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_34_OFFSET (0xD84) -#define DSP2_BLBACK_GAMMA_TABLE66_PRE DSP2_BLBACK_GAMMA_TABLE66_PRE -#define DSP2_BLBACK_GAMMA_TABLE66_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE66_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE66_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE66_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE66_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE66_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE66_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE66_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE67_PRE DSP2_BLBACK_GAMMA_TABLE67_PRE -#define DSP2_BLBACK_GAMMA_TABLE67_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE67_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE67_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE67_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE67_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE67_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE67_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE67_PRE_POS)) - -/* 0xD88 : BL_GAMMA_TABLE_35 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_35_OFFSET (0xD88) -#define DSP2_BLBACK_GAMMA_TABLE68_PRE DSP2_BLBACK_GAMMA_TABLE68_PRE -#define DSP2_BLBACK_GAMMA_TABLE68_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE68_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE68_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE68_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE68_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE68_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE68_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE68_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE69_PRE DSP2_BLBACK_GAMMA_TABLE69_PRE -#define DSP2_BLBACK_GAMMA_TABLE69_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE69_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE69_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE69_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE69_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE69_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE69_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE69_PRE_POS)) - -/* 0xD8C : BL_GAMMA_TABLE_36 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_36_OFFSET (0xD8C) -#define DSP2_BLBACK_GAMMA_TABLE70_PRE DSP2_BLBACK_GAMMA_TABLE70_PRE -#define DSP2_BLBACK_GAMMA_TABLE70_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE70_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE70_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE70_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE70_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE70_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE70_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE70_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE71_PRE DSP2_BLBACK_GAMMA_TABLE71_PRE -#define DSP2_BLBACK_GAMMA_TABLE71_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE71_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE71_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE71_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE71_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE71_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE71_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE71_PRE_POS)) - -/* 0xD90 : BL_GAMMA_TABLE_37 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_37_OFFSET (0xD90) -#define DSP2_BLBACK_GAMMA_TABLE72_PRE DSP2_BLBACK_GAMMA_TABLE72_PRE -#define DSP2_BLBACK_GAMMA_TABLE72_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE72_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE72_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE72_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE72_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE72_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE72_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE72_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE73_PRE DSP2_BLBACK_GAMMA_TABLE73_PRE -#define DSP2_BLBACK_GAMMA_TABLE73_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE73_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE73_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE73_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE73_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE73_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE73_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE73_PRE_POS)) - -/* 0xD94 : BL_GAMMA_TABLE_38 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_38_OFFSET (0xD94) -#define DSP2_BLBACK_GAMMA_TABLE74_PRE DSP2_BLBACK_GAMMA_TABLE74_PRE -#define DSP2_BLBACK_GAMMA_TABLE74_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE74_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE74_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE74_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE74_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE74_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE74_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE74_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE75_PRE DSP2_BLBACK_GAMMA_TABLE75_PRE -#define DSP2_BLBACK_GAMMA_TABLE75_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE75_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE75_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE75_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE75_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE75_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE75_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE75_PRE_POS)) - -/* 0xD98 : BL_GAMMA_TABLE_39 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_39_OFFSET (0xD98) -#define DSP2_BLBACK_GAMMA_TABLE76_PRE DSP2_BLBACK_GAMMA_TABLE76_PRE -#define DSP2_BLBACK_GAMMA_TABLE76_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE76_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE76_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE76_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE76_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE76_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE76_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE76_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE77_PRE DSP2_BLBACK_GAMMA_TABLE77_PRE -#define DSP2_BLBACK_GAMMA_TABLE77_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE77_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE77_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE77_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE77_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE77_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE77_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE77_PRE_POS)) - -/* 0xD9C : BL_GAMMA_TABLE_40 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_40_OFFSET (0xD9C) -#define DSP2_BLBACK_GAMMA_TABLE78_PRE DSP2_BLBACK_GAMMA_TABLE78_PRE -#define DSP2_BLBACK_GAMMA_TABLE78_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE78_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE78_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE78_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE78_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE78_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE78_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE78_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE79_PRE DSP2_BLBACK_GAMMA_TABLE79_PRE -#define DSP2_BLBACK_GAMMA_TABLE79_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE79_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE79_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE79_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE79_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE79_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE79_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE79_PRE_POS)) - -/* 0xDA0 : BL_GAMMA_TABLE_41 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_41_OFFSET (0xDA0) -#define DSP2_BLBACK_GAMMA_TABLE80_PRE DSP2_BLBACK_GAMMA_TABLE80_PRE -#define DSP2_BLBACK_GAMMA_TABLE80_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE80_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE80_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE80_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE80_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE80_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE80_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE80_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE81_PRE DSP2_BLBACK_GAMMA_TABLE81_PRE -#define DSP2_BLBACK_GAMMA_TABLE81_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE81_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE81_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE81_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE81_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE81_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE81_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE81_PRE_POS)) - -/* 0xDA4 : BL_GAMMA_TABLE_42 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_42_OFFSET (0xDA4) -#define DSP2_BLBACK_GAMMA_TABLE82_PRE DSP2_BLBACK_GAMMA_TABLE82_PRE -#define DSP2_BLBACK_GAMMA_TABLE82_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE82_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE82_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE82_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE82_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE82_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE82_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE82_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE83_PRE DSP2_BLBACK_GAMMA_TABLE83_PRE -#define DSP2_BLBACK_GAMMA_TABLE83_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE83_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE83_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE83_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE83_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE83_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE83_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE83_PRE_POS)) - -/* 0xDA8 : BL_GAMMA_TABLE_43 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_43_OFFSET (0xDA8) -#define DSP2_BLBACK_GAMMA_TABLE84_PRE DSP2_BLBACK_GAMMA_TABLE84_PRE -#define DSP2_BLBACK_GAMMA_TABLE84_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE84_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE84_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE84_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE84_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE84_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE84_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE84_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE85_PRE DSP2_BLBACK_GAMMA_TABLE85_PRE -#define DSP2_BLBACK_GAMMA_TABLE85_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE85_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE85_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE85_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE85_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE85_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE85_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE85_PRE_POS)) - -/* 0xDAC : BL_GAMMA_TABLE_44 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_44_OFFSET (0xDAC) -#define DSP2_BLBACK_GAMMA_TABLE86_PRE DSP2_BLBACK_GAMMA_TABLE86_PRE -#define DSP2_BLBACK_GAMMA_TABLE86_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE86_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE86_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE86_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE86_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE86_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE86_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE86_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE87_PRE DSP2_BLBACK_GAMMA_TABLE87_PRE -#define DSP2_BLBACK_GAMMA_TABLE87_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE87_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE87_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE87_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE87_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE87_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE87_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE87_PRE_POS)) - -/* 0xDB0 : BL_GAMMA_TABLE_45 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_45_OFFSET (0xDB0) -#define DSP2_BLBACK_GAMMA_TABLE88_PRE DSP2_BLBACK_GAMMA_TABLE88_PRE -#define DSP2_BLBACK_GAMMA_TABLE88_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE88_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE88_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE88_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE88_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE88_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE88_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE88_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE89_PRE DSP2_BLBACK_GAMMA_TABLE89_PRE -#define DSP2_BLBACK_GAMMA_TABLE89_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE89_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE89_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE89_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE89_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE89_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE89_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE89_PRE_POS)) - -/* 0xDB4 : BL_GAMMA_TABLE_46 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_46_OFFSET (0xDB4) -#define DSP2_BLBACK_GAMMA_TABLE90_PRE DSP2_BLBACK_GAMMA_TABLE90_PRE -#define DSP2_BLBACK_GAMMA_TABLE90_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE90_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE90_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE90_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE90_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE90_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE90_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE90_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE91_PRE DSP2_BLBACK_GAMMA_TABLE91_PRE -#define DSP2_BLBACK_GAMMA_TABLE91_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE91_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE91_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE91_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE91_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE91_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE91_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE91_PRE_POS)) - -/* 0xDB8 : BL_GAMMA_TABLE_47 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_47_OFFSET (0xDB8) -#define DSP2_BLBACK_GAMMA_TABLE92_PRE DSP2_BLBACK_GAMMA_TABLE92_PRE -#define DSP2_BLBACK_GAMMA_TABLE92_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE92_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE92_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE92_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE92_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE92_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE92_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE92_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE93_PRE DSP2_BLBACK_GAMMA_TABLE93_PRE -#define DSP2_BLBACK_GAMMA_TABLE93_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE93_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE93_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE93_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE93_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE93_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE93_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE93_PRE_POS)) - -/* 0xDBC : BL_GAMMA_TABLE_48 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_48_OFFSET (0xDBC) -#define DSP2_BLBACK_GAMMA_TABLE94_PRE DSP2_BLBACK_GAMMA_TABLE94_PRE -#define DSP2_BLBACK_GAMMA_TABLE94_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE94_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE94_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE94_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE94_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE94_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE94_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE94_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE95_PRE DSP2_BLBACK_GAMMA_TABLE95_PRE -#define DSP2_BLBACK_GAMMA_TABLE95_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE95_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE95_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE95_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE95_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE95_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE95_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE95_PRE_POS)) - -/* 0xDC0 : BL_GAMMA_TABLE_49 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_49_OFFSET (0xDC0) -#define DSP2_BLBACK_GAMMA_TABLE96_PRE DSP2_BLBACK_GAMMA_TABLE96_PRE -#define DSP2_BLBACK_GAMMA_TABLE96_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE96_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE96_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE96_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE96_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE96_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE96_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE96_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE97_PRE DSP2_BLBACK_GAMMA_TABLE97_PRE -#define DSP2_BLBACK_GAMMA_TABLE97_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE97_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE97_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE97_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE97_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE97_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE97_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE97_PRE_POS)) - -/* 0xDC4 : BL_GAMMA_TABLE_50 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_50_OFFSET (0xDC4) -#define DSP2_BLBACK_GAMMA_TABLE98_PRE DSP2_BLBACK_GAMMA_TABLE98_PRE -#define DSP2_BLBACK_GAMMA_TABLE98_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE98_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE98_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE98_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE98_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE98_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE98_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE98_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE99_PRE DSP2_BLBACK_GAMMA_TABLE99_PRE -#define DSP2_BLBACK_GAMMA_TABLE99_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE99_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE99_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE99_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE99_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE99_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE99_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE99_PRE_POS)) - -/* 0xDC8 : BL_GAMMA_TABLE_51 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_51_OFFSET (0xDC8) -#define DSP2_BLBACK_GAMMA_TABLE100_PRE DSP2_BLBACK_GAMMA_TABLE100_PRE -#define DSP2_BLBACK_GAMMA_TABLE100_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE100_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE100_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE100_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE100_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE100_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE100_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE100_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE101_PRE DSP2_BLBACK_GAMMA_TABLE101_PRE -#define DSP2_BLBACK_GAMMA_TABLE101_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE101_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE101_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE101_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE101_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE101_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE101_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE101_PRE_POS)) - -/* 0xDCC : BL_GAMMA_TABLE_52 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_52_OFFSET (0xDCC) -#define DSP2_BLBACK_GAMMA_TABLE102_PRE DSP2_BLBACK_GAMMA_TABLE102_PRE -#define DSP2_BLBACK_GAMMA_TABLE102_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE102_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE102_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE102_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE102_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE102_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE102_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE102_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE103_PRE DSP2_BLBACK_GAMMA_TABLE103_PRE -#define DSP2_BLBACK_GAMMA_TABLE103_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE103_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE103_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE103_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE103_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE103_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE103_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE103_PRE_POS)) - -/* 0xDD0 : BL_GAMMA_TABLE_53 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_53_OFFSET (0xDD0) -#define DSP2_BLBACK_GAMMA_TABLE104_PRE DSP2_BLBACK_GAMMA_TABLE104_PRE -#define DSP2_BLBACK_GAMMA_TABLE104_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE104_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE104_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE104_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE104_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE104_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE104_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE104_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE105_PRE DSP2_BLBACK_GAMMA_TABLE105_PRE -#define DSP2_BLBACK_GAMMA_TABLE105_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE105_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE105_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE105_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE105_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE105_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE105_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE105_PRE_POS)) - -/* 0xDD4 : BL_GAMMA_TABLE_54 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_54_OFFSET (0xDD4) -#define DSP2_BLBACK_GAMMA_TABLE106_PRE DSP2_BLBACK_GAMMA_TABLE106_PRE -#define DSP2_BLBACK_GAMMA_TABLE106_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE106_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE106_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE106_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE106_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE106_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE106_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE106_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE107_PRE DSP2_BLBACK_GAMMA_TABLE107_PRE -#define DSP2_BLBACK_GAMMA_TABLE107_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE107_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE107_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE107_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE107_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE107_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE107_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE107_PRE_POS)) - -/* 0xDD8 : BL_GAMMA_TABLE_55 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_55_OFFSET (0xDD8) -#define DSP2_BLBACK_GAMMA_TABLE108_PRE DSP2_BLBACK_GAMMA_TABLE108_PRE -#define DSP2_BLBACK_GAMMA_TABLE108_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE108_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE108_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE108_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE108_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE108_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE108_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE108_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE109_PRE DSP2_BLBACK_GAMMA_TABLE109_PRE -#define DSP2_BLBACK_GAMMA_TABLE109_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE109_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE109_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE109_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE109_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE109_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE109_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE109_PRE_POS)) - -/* 0xDDC : BL_GAMMA_TABLE_56 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_56_OFFSET (0xDDC) -#define DSP2_BLBACK_GAMMA_TABLE110_PRE DSP2_BLBACK_GAMMA_TABLE110_PRE -#define DSP2_BLBACK_GAMMA_TABLE110_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE110_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE110_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE110_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE110_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE110_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE110_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE110_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE111_PRE DSP2_BLBACK_GAMMA_TABLE111_PRE -#define DSP2_BLBACK_GAMMA_TABLE111_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE111_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE111_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE111_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE111_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE111_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE111_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE111_PRE_POS)) - -/* 0xDE0 : BL_GAMMA_TABLE_57 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_57_OFFSET (0xDE0) -#define DSP2_BLBACK_GAMMA_TABLE112_PRE DSP2_BLBACK_GAMMA_TABLE112_PRE -#define DSP2_BLBACK_GAMMA_TABLE112_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE112_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE112_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE112_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE112_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE112_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE112_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE112_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE113_PRE DSP2_BLBACK_GAMMA_TABLE113_PRE -#define DSP2_BLBACK_GAMMA_TABLE113_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE113_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE113_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE113_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE113_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE113_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE113_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE113_PRE_POS)) - -/* 0xDE4 : BL_GAMMA_TABLE_58 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_58_OFFSET (0xDE4) -#define DSP2_BLBACK_GAMMA_TABLE114_PRE DSP2_BLBACK_GAMMA_TABLE114_PRE -#define DSP2_BLBACK_GAMMA_TABLE114_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE114_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE114_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE114_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE114_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE114_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE114_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE114_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE115_PRE DSP2_BLBACK_GAMMA_TABLE115_PRE -#define DSP2_BLBACK_GAMMA_TABLE115_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE115_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE115_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE115_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE115_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE115_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE115_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE115_PRE_POS)) - -/* 0xDE8 : BL_GAMMA_TABLE_59 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_59_OFFSET (0xDE8) -#define DSP2_BLBACK_GAMMA_TABLE116_PRE DSP2_BLBACK_GAMMA_TABLE116_PRE -#define DSP2_BLBACK_GAMMA_TABLE116_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE116_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE116_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE116_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE116_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE116_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE116_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE116_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE117_PRE DSP2_BLBACK_GAMMA_TABLE117_PRE -#define DSP2_BLBACK_GAMMA_TABLE117_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE117_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE117_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE117_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE117_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE117_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE117_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE117_PRE_POS)) - -/* 0xDEC : BL_GAMMA_TABLE_60 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_60_OFFSET (0xDEC) -#define DSP2_BLBACK_GAMMA_TABLE118_PRE DSP2_BLBACK_GAMMA_TABLE118_PRE -#define DSP2_BLBACK_GAMMA_TABLE118_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE118_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE118_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE118_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE118_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE118_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE118_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE118_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE119_PRE DSP2_BLBACK_GAMMA_TABLE119_PRE -#define DSP2_BLBACK_GAMMA_TABLE119_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE119_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE119_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE119_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE119_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE119_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE119_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE119_PRE_POS)) - -/* 0xDF0 : BL_GAMMA_TABLE_61 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_61_OFFSET (0xDF0) -#define DSP2_BLBACK_GAMMA_TABLE120_PRE DSP2_BLBACK_GAMMA_TABLE120_PRE -#define DSP2_BLBACK_GAMMA_TABLE120_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE120_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE120_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE120_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE120_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE120_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE120_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE120_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE121_PRE DSP2_BLBACK_GAMMA_TABLE121_PRE -#define DSP2_BLBACK_GAMMA_TABLE121_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE121_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE121_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE121_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE121_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE121_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE121_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE121_PRE_POS)) - -/* 0xDF4 : BL_GAMMA_TABLE_62 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_62_OFFSET (0xDF4) -#define DSP2_BLBACK_GAMMA_TABLE122_PRE DSP2_BLBACK_GAMMA_TABLE122_PRE -#define DSP2_BLBACK_GAMMA_TABLE122_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE122_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE122_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE122_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE122_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE122_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE122_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE122_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE123_PRE DSP2_BLBACK_GAMMA_TABLE123_PRE -#define DSP2_BLBACK_GAMMA_TABLE123_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE123_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE123_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE123_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE123_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE123_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE123_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE123_PRE_POS)) - -/* 0xDF8 : BL_GAMMA_TABLE_63 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_63_OFFSET (0xDF8) -#define DSP2_BLBACK_GAMMA_TABLE124_PRE DSP2_BLBACK_GAMMA_TABLE124_PRE -#define DSP2_BLBACK_GAMMA_TABLE124_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE124_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE124_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE124_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE124_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE124_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE124_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE124_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE125_PRE DSP2_BLBACK_GAMMA_TABLE125_PRE -#define DSP2_BLBACK_GAMMA_TABLE125_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE125_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE125_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE125_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE125_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE125_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE125_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE125_PRE_POS)) - -/* 0xDFC : BL_GAMMA_TABLE_64 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_64_OFFSET (0xDFC) -#define DSP2_BLBACK_GAMMA_TABLE126_PRE DSP2_BLBACK_GAMMA_TABLE126_PRE -#define DSP2_BLBACK_GAMMA_TABLE126_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE126_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE126_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE126_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE126_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE126_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE126_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE126_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE127_PRE DSP2_BLBACK_GAMMA_TABLE127_PRE -#define DSP2_BLBACK_GAMMA_TABLE127_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE127_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE127_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE127_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE127_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE127_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE127_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE127_PRE_POS)) - -/* 0xE00 : BL_GAMMA_TABLE_65 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_65_OFFSET (0xE00) -#define DSP2_BLBACK_GAMMA_TABLE128_PRE DSP2_BLBACK_GAMMA_TABLE128_PRE -#define DSP2_BLBACK_GAMMA_TABLE128_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE128_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE128_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE128_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE128_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE128_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE128_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE128_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE129_PRE DSP2_BLBACK_GAMMA_TABLE129_PRE -#define DSP2_BLBACK_GAMMA_TABLE129_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE129_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE129_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE129_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE129_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE129_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE129_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE129_PRE_POS)) - -/* 0xE04 : BL_GAMMA_TABLE_66 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_66_OFFSET (0xE04) -#define DSP2_BLBACK_GAMMA_TABLE130_PRE DSP2_BLBACK_GAMMA_TABLE130_PRE -#define DSP2_BLBACK_GAMMA_TABLE130_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE130_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE130_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE130_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE130_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE130_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE130_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE130_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE131_PRE DSP2_BLBACK_GAMMA_TABLE131_PRE -#define DSP2_BLBACK_GAMMA_TABLE131_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE131_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE131_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE131_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE131_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE131_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE131_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE131_PRE_POS)) - -/* 0xE08 : BL_GAMMA_TABLE_67 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_67_OFFSET (0xE08) -#define DSP2_BLBACK_GAMMA_TABLE132_PRE DSP2_BLBACK_GAMMA_TABLE132_PRE -#define DSP2_BLBACK_GAMMA_TABLE132_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE132_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE132_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE132_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE132_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE132_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE132_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE132_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE133_PRE DSP2_BLBACK_GAMMA_TABLE133_PRE -#define DSP2_BLBACK_GAMMA_TABLE133_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE133_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE133_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE133_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE133_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE133_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE133_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE133_PRE_POS)) - -/* 0xE0C : BL_GAMMA_TABLE_68 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_68_OFFSET (0xE0C) -#define DSP2_BLBACK_GAMMA_TABLE134_PRE DSP2_BLBACK_GAMMA_TABLE134_PRE -#define DSP2_BLBACK_GAMMA_TABLE134_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE134_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE134_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE134_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE134_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE134_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE134_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE134_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE135_PRE DSP2_BLBACK_GAMMA_TABLE135_PRE -#define DSP2_BLBACK_GAMMA_TABLE135_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE135_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE135_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE135_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE135_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE135_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE135_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE135_PRE_POS)) - -/* 0xE10 : BL_GAMMA_TABLE_69 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_69_OFFSET (0xE10) -#define DSP2_BLBACK_GAMMA_TABLE136_PRE DSP2_BLBACK_GAMMA_TABLE136_PRE -#define DSP2_BLBACK_GAMMA_TABLE136_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE136_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE136_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE136_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE136_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE136_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE136_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE136_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE137_PRE DSP2_BLBACK_GAMMA_TABLE137_PRE -#define DSP2_BLBACK_GAMMA_TABLE137_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE137_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE137_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE137_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE137_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE137_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE137_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE137_PRE_POS)) - -/* 0xE14 : BL_GAMMA_TABLE_70 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_70_OFFSET (0xE14) -#define DSP2_BLBACK_GAMMA_TABLE138_PRE DSP2_BLBACK_GAMMA_TABLE138_PRE -#define DSP2_BLBACK_GAMMA_TABLE138_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE138_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE138_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE138_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE138_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE138_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE138_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE138_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE139_PRE DSP2_BLBACK_GAMMA_TABLE139_PRE -#define DSP2_BLBACK_GAMMA_TABLE139_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE139_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE139_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE139_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE139_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE139_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE139_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE139_PRE_POS)) - -/* 0xE18 : BL_GAMMA_TABLE_71 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_71_OFFSET (0xE18) -#define DSP2_BLBACK_GAMMA_TABLE140_PRE DSP2_BLBACK_GAMMA_TABLE140_PRE -#define DSP2_BLBACK_GAMMA_TABLE140_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE140_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE140_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE140_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE140_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE140_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE140_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE140_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE141_PRE DSP2_BLBACK_GAMMA_TABLE141_PRE -#define DSP2_BLBACK_GAMMA_TABLE141_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE141_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE141_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE141_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE141_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE141_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE141_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE141_PRE_POS)) - -/* 0xE1C : BL_GAMMA_TABLE_72 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_72_OFFSET (0xE1C) -#define DSP2_BLBACK_GAMMA_TABLE142_PRE DSP2_BLBACK_GAMMA_TABLE142_PRE -#define DSP2_BLBACK_GAMMA_TABLE142_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE142_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE142_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE142_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE142_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE142_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE142_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE142_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE143_PRE DSP2_BLBACK_GAMMA_TABLE143_PRE -#define DSP2_BLBACK_GAMMA_TABLE143_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE143_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE143_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE143_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE143_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE143_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE143_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE143_PRE_POS)) - -/* 0xE20 : BL_GAMMA_TABLE_73 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_73_OFFSET (0xE20) -#define DSP2_BLBACK_GAMMA_TABLE144_PRE DSP2_BLBACK_GAMMA_TABLE144_PRE -#define DSP2_BLBACK_GAMMA_TABLE144_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE144_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE144_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE144_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE144_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE144_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE144_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE144_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE145_PRE DSP2_BLBACK_GAMMA_TABLE145_PRE -#define DSP2_BLBACK_GAMMA_TABLE145_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE145_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE145_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE145_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE145_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE145_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE145_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE145_PRE_POS)) - -/* 0xE24 : BL_GAMMA_TABLE_74 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_74_OFFSET (0xE24) -#define DSP2_BLBACK_GAMMA_TABLE146_PRE DSP2_BLBACK_GAMMA_TABLE146_PRE -#define DSP2_BLBACK_GAMMA_TABLE146_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE146_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE146_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE146_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE146_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE146_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE146_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE146_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE147_PRE DSP2_BLBACK_GAMMA_TABLE147_PRE -#define DSP2_BLBACK_GAMMA_TABLE147_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE147_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE147_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE147_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE147_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE147_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE147_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE147_PRE_POS)) - -/* 0xE28 : BL_GAMMA_TABLE_75 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_75_OFFSET (0xE28) -#define DSP2_BLBACK_GAMMA_TABLE148_PRE DSP2_BLBACK_GAMMA_TABLE148_PRE -#define DSP2_BLBACK_GAMMA_TABLE148_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE148_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE148_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE148_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE148_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE148_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE148_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE148_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE149_PRE DSP2_BLBACK_GAMMA_TABLE149_PRE -#define DSP2_BLBACK_GAMMA_TABLE149_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE149_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE149_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE149_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE149_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE149_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE149_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE149_PRE_POS)) - -/* 0xE2C : BL_GAMMA_TABLE_76 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_76_OFFSET (0xE2C) -#define DSP2_BLBACK_GAMMA_TABLE150_PRE DSP2_BLBACK_GAMMA_TABLE150_PRE -#define DSP2_BLBACK_GAMMA_TABLE150_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE150_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE150_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE150_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE150_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE150_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE150_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE150_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE151_PRE DSP2_BLBACK_GAMMA_TABLE151_PRE -#define DSP2_BLBACK_GAMMA_TABLE151_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE151_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE151_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE151_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE151_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE151_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE151_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE151_PRE_POS)) - -/* 0xE30 : BL_GAMMA_TABLE_77 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_77_OFFSET (0xE30) -#define DSP2_BLBACK_GAMMA_TABLE152_PRE DSP2_BLBACK_GAMMA_TABLE152_PRE -#define DSP2_BLBACK_GAMMA_TABLE152_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE152_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE152_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE152_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE152_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE152_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE152_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE152_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE153_PRE DSP2_BLBACK_GAMMA_TABLE153_PRE -#define DSP2_BLBACK_GAMMA_TABLE153_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE153_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE153_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE153_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE153_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE153_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE153_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE153_PRE_POS)) - -/* 0xE34 : BL_GAMMA_TABLE_78 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_78_OFFSET (0xE34) -#define DSP2_BLBACK_GAMMA_TABLE154_PRE DSP2_BLBACK_GAMMA_TABLE154_PRE -#define DSP2_BLBACK_GAMMA_TABLE154_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE154_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE154_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE154_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE154_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE154_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE154_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE154_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE155_PRE DSP2_BLBACK_GAMMA_TABLE155_PRE -#define DSP2_BLBACK_GAMMA_TABLE155_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE155_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE155_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE155_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE155_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE155_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE155_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE155_PRE_POS)) - -/* 0xE38 : BL_GAMMA_TABLE_79 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_79_OFFSET (0xE38) -#define DSP2_BLBACK_GAMMA_TABLE156_PRE DSP2_BLBACK_GAMMA_TABLE156_PRE -#define DSP2_BLBACK_GAMMA_TABLE156_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE156_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE156_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE156_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE156_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE156_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE156_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE156_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE157_PRE DSP2_BLBACK_GAMMA_TABLE157_PRE -#define DSP2_BLBACK_GAMMA_TABLE157_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE157_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE157_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE157_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE157_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE157_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE157_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE157_PRE_POS)) - -/* 0xE3C : BL_GAMMA_TABLE_80 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_80_OFFSET (0xE3C) -#define DSP2_BLBACK_GAMMA_TABLE158_PRE DSP2_BLBACK_GAMMA_TABLE158_PRE -#define DSP2_BLBACK_GAMMA_TABLE158_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE158_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE158_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE158_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE158_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE158_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE158_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE158_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE159_PRE DSP2_BLBACK_GAMMA_TABLE159_PRE -#define DSP2_BLBACK_GAMMA_TABLE159_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE159_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE159_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE159_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE159_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE159_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE159_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE159_PRE_POS)) - -/* 0xE40 : BL_GAMMA_TABLE_81 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_81_OFFSET (0xE40) -#define DSP2_BLBACK_GAMMA_TABLE160_PRE DSP2_BLBACK_GAMMA_TABLE160_PRE -#define DSP2_BLBACK_GAMMA_TABLE160_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE160_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE160_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE160_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE160_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE160_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE160_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE160_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE161_PRE DSP2_BLBACK_GAMMA_TABLE161_PRE -#define DSP2_BLBACK_GAMMA_TABLE161_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE161_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE161_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE161_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE161_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE161_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE161_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE161_PRE_POS)) - -/* 0xE44 : BL_GAMMA_TABLE_82 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_82_OFFSET (0xE44) -#define DSP2_BLBACK_GAMMA_TABLE162_PRE DSP2_BLBACK_GAMMA_TABLE162_PRE -#define DSP2_BLBACK_GAMMA_TABLE162_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE162_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE162_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE162_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE162_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE162_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE162_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE162_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE163_PRE DSP2_BLBACK_GAMMA_TABLE163_PRE -#define DSP2_BLBACK_GAMMA_TABLE163_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE163_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE163_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE163_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE163_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE163_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE163_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE163_PRE_POS)) - -/* 0xE48 : BL_GAMMA_TABLE_83 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_83_OFFSET (0xE48) -#define DSP2_BLBACK_GAMMA_TABLE164_PRE DSP2_BLBACK_GAMMA_TABLE164_PRE -#define DSP2_BLBACK_GAMMA_TABLE164_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE164_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE164_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE164_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE164_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE164_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE164_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE164_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE165_PRE DSP2_BLBACK_GAMMA_TABLE165_PRE -#define DSP2_BLBACK_GAMMA_TABLE165_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE165_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE165_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE165_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE165_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE165_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE165_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE165_PRE_POS)) - -/* 0xE4C : BL_GAMMA_TABLE_84 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_84_OFFSET (0xE4C) -#define DSP2_BLBACK_GAMMA_TABLE166_PRE DSP2_BLBACK_GAMMA_TABLE166_PRE -#define DSP2_BLBACK_GAMMA_TABLE166_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE166_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE166_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE166_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE166_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE166_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE166_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE166_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE167_PRE DSP2_BLBACK_GAMMA_TABLE167_PRE -#define DSP2_BLBACK_GAMMA_TABLE167_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE167_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE167_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE167_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE167_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE167_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE167_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE167_PRE_POS)) - -/* 0xE50 : BL_GAMMA_TABLE_85 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_85_OFFSET (0xE50) -#define DSP2_BLBACK_GAMMA_TABLE168_PRE DSP2_BLBACK_GAMMA_TABLE168_PRE -#define DSP2_BLBACK_GAMMA_TABLE168_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE168_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE168_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE168_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE168_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE168_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE168_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE168_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE169_PRE DSP2_BLBACK_GAMMA_TABLE169_PRE -#define DSP2_BLBACK_GAMMA_TABLE169_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE169_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE169_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE169_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE169_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE169_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE169_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE169_PRE_POS)) - -/* 0xE54 : BL_GAMMA_TABLE_86 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_86_OFFSET (0xE54) -#define DSP2_BLBACK_GAMMA_TABLE170_PRE DSP2_BLBACK_GAMMA_TABLE170_PRE -#define DSP2_BLBACK_GAMMA_TABLE170_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE170_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE170_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE170_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE170_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE170_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE170_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE170_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE171_PRE DSP2_BLBACK_GAMMA_TABLE171_PRE -#define DSP2_BLBACK_GAMMA_TABLE171_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE171_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE171_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE171_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE171_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE171_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE171_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE171_PRE_POS)) - -/* 0xE58 : BL_GAMMA_TABLE_87 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_87_OFFSET (0xE58) -#define DSP2_BLBACK_GAMMA_TABLE172_PRE DSP2_BLBACK_GAMMA_TABLE172_PRE -#define DSP2_BLBACK_GAMMA_TABLE172_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE172_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE172_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE172_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE172_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE172_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE172_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE172_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE173_PRE DSP2_BLBACK_GAMMA_TABLE173_PRE -#define DSP2_BLBACK_GAMMA_TABLE173_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE173_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE173_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE173_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE173_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE173_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE173_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE173_PRE_POS)) - -/* 0xE5C : BL_GAMMA_TABLE_88 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_88_OFFSET (0xE5C) -#define DSP2_BLBACK_GAMMA_TABLE174_PRE DSP2_BLBACK_GAMMA_TABLE174_PRE -#define DSP2_BLBACK_GAMMA_TABLE174_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE174_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE174_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE174_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE174_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE174_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE174_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE174_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE175_PRE DSP2_BLBACK_GAMMA_TABLE175_PRE -#define DSP2_BLBACK_GAMMA_TABLE175_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE175_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE175_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE175_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE175_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE175_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE175_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE175_PRE_POS)) - -/* 0xE60 : BL_GAMMA_TABLE_89 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_89_OFFSET (0xE60) -#define DSP2_BLBACK_GAMMA_TABLE176_PRE DSP2_BLBACK_GAMMA_TABLE176_PRE -#define DSP2_BLBACK_GAMMA_TABLE176_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE176_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE176_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE176_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE176_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE176_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE176_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE176_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE177_PRE DSP2_BLBACK_GAMMA_TABLE177_PRE -#define DSP2_BLBACK_GAMMA_TABLE177_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE177_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE177_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE177_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE177_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE177_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE177_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE177_PRE_POS)) - -/* 0xE64 : BL_GAMMA_TABLE_90 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_90_OFFSET (0xE64) -#define DSP2_BLBACK_GAMMA_TABLE178_PRE DSP2_BLBACK_GAMMA_TABLE178_PRE -#define DSP2_BLBACK_GAMMA_TABLE178_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE178_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE178_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE178_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE178_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE178_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE178_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE178_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE179_PRE DSP2_BLBACK_GAMMA_TABLE179_PRE -#define DSP2_BLBACK_GAMMA_TABLE179_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE179_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE179_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE179_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE179_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE179_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE179_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE179_PRE_POS)) - -/* 0xE68 : BL_GAMMA_TABLE_91 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_91_OFFSET (0xE68) -#define DSP2_BLBACK_GAMMA_TABLE180_PRE DSP2_BLBACK_GAMMA_TABLE180_PRE -#define DSP2_BLBACK_GAMMA_TABLE180_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE180_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE180_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE180_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE180_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE180_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE180_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE180_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE181_PRE DSP2_BLBACK_GAMMA_TABLE181_PRE -#define DSP2_BLBACK_GAMMA_TABLE181_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE181_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE181_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE181_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE181_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE181_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE181_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE181_PRE_POS)) - -/* 0xE6C : BL_GAMMA_TABLE_92 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_92_OFFSET (0xE6C) -#define DSP2_BLBACK_GAMMA_TABLE182_PRE DSP2_BLBACK_GAMMA_TABLE182_PRE -#define DSP2_BLBACK_GAMMA_TABLE182_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE182_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE182_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE182_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE182_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE182_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE182_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE182_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE183_PRE DSP2_BLBACK_GAMMA_TABLE183_PRE -#define DSP2_BLBACK_GAMMA_TABLE183_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE183_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE183_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE183_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE183_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE183_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE183_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE183_PRE_POS)) - -/* 0xE70 : BL_GAMMA_TABLE_93 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_93_OFFSET (0xE70) -#define DSP2_BLBACK_GAMMA_TABLE184_PRE DSP2_BLBACK_GAMMA_TABLE184_PRE -#define DSP2_BLBACK_GAMMA_TABLE184_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE184_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE184_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE184_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE184_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE184_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE184_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE184_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE185_PRE DSP2_BLBACK_GAMMA_TABLE185_PRE -#define DSP2_BLBACK_GAMMA_TABLE185_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE185_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE185_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE185_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE185_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE185_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE185_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE185_PRE_POS)) - -/* 0xE74 : BL_GAMMA_TABLE_94 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_94_OFFSET (0xE74) -#define DSP2_BLBACK_GAMMA_TABLE186_PRE DSP2_BLBACK_GAMMA_TABLE186_PRE -#define DSP2_BLBACK_GAMMA_TABLE186_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE186_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE186_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE186_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE186_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE186_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE186_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE186_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE187_PRE DSP2_BLBACK_GAMMA_TABLE187_PRE -#define DSP2_BLBACK_GAMMA_TABLE187_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE187_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE187_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE187_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE187_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE187_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE187_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE187_PRE_POS)) - -/* 0xE78 : BL_GAMMA_TABLE_95 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_95_OFFSET (0xE78) -#define DSP2_BLBACK_GAMMA_TABLE188_PRE DSP2_BLBACK_GAMMA_TABLE188_PRE -#define DSP2_BLBACK_GAMMA_TABLE188_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE188_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE188_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE188_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE188_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE188_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE188_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE188_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE189_PRE DSP2_BLBACK_GAMMA_TABLE189_PRE -#define DSP2_BLBACK_GAMMA_TABLE189_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE189_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE189_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE189_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE189_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE189_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE189_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE189_PRE_POS)) - -/* 0xE7C : BL_GAMMA_TABLE_96 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_96_OFFSET (0xE7C) -#define DSP2_BLBACK_GAMMA_TABLE190_PRE DSP2_BLBACK_GAMMA_TABLE190_PRE -#define DSP2_BLBACK_GAMMA_TABLE190_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE190_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE190_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE190_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE190_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE190_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE190_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE190_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE191_PRE DSP2_BLBACK_GAMMA_TABLE191_PRE -#define DSP2_BLBACK_GAMMA_TABLE191_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE191_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE191_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE191_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE191_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE191_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE191_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE191_PRE_POS)) - -/* 0xE80 : BL_GAMMA_TABLE_97 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_97_OFFSET (0xE80) -#define DSP2_BLBACK_GAMMA_TABLE192_PRE DSP2_BLBACK_GAMMA_TABLE192_PRE -#define DSP2_BLBACK_GAMMA_TABLE192_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE192_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE192_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE192_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE192_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE192_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE192_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE192_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE193_PRE DSP2_BLBACK_GAMMA_TABLE193_PRE -#define DSP2_BLBACK_GAMMA_TABLE193_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE193_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE193_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE193_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE193_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE193_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE193_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE193_PRE_POS)) - -/* 0xE84 : BL_GAMMA_TABLE_98 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_98_OFFSET (0xE84) -#define DSP2_BLBACK_GAMMA_TABLE194_PRE DSP2_BLBACK_GAMMA_TABLE194_PRE -#define DSP2_BLBACK_GAMMA_TABLE194_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE194_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE194_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE194_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE194_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE194_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE194_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE194_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE195_PRE DSP2_BLBACK_GAMMA_TABLE195_PRE -#define DSP2_BLBACK_GAMMA_TABLE195_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE195_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE195_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE195_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE195_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE195_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE195_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE195_PRE_POS)) - -/* 0xE88 : BL_GAMMA_TABLE_99 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_99_OFFSET (0xE88) -#define DSP2_BLBACK_GAMMA_TABLE196_PRE DSP2_BLBACK_GAMMA_TABLE196_PRE -#define DSP2_BLBACK_GAMMA_TABLE196_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE196_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE196_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE196_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE196_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE196_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE196_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE196_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE197_PRE DSP2_BLBACK_GAMMA_TABLE197_PRE -#define DSP2_BLBACK_GAMMA_TABLE197_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE197_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE197_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE197_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE197_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE197_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE197_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE197_PRE_POS)) - -/* 0xE8C : BL_GAMMA_TABLE_100 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_100_OFFSET (0xE8C) -#define DSP2_BLBACK_GAMMA_TABLE198_PRE DSP2_BLBACK_GAMMA_TABLE198_PRE -#define DSP2_BLBACK_GAMMA_TABLE198_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE198_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE198_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE198_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE198_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE198_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE198_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE198_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE199_PRE DSP2_BLBACK_GAMMA_TABLE199_PRE -#define DSP2_BLBACK_GAMMA_TABLE199_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE199_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE199_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE199_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE199_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE199_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE199_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE199_PRE_POS)) - -/* 0xE90 : BL_GAMMA_TABLE_101 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_101_OFFSET (0xE90) -#define DSP2_BLBACK_GAMMA_TABLE200_PRE DSP2_BLBACK_GAMMA_TABLE200_PRE -#define DSP2_BLBACK_GAMMA_TABLE200_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE200_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE200_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE200_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE200_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE200_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE200_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE200_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE201_PRE DSP2_BLBACK_GAMMA_TABLE201_PRE -#define DSP2_BLBACK_GAMMA_TABLE201_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE201_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE201_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE201_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE201_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE201_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE201_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE201_PRE_POS)) - -/* 0xE94 : BL_GAMMA_TABLE_102 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_102_OFFSET (0xE94) -#define DSP2_BLBACK_GAMMA_TABLE202_PRE DSP2_BLBACK_GAMMA_TABLE202_PRE -#define DSP2_BLBACK_GAMMA_TABLE202_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE202_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE202_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE202_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE202_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE202_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE202_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE202_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE203_PRE DSP2_BLBACK_GAMMA_TABLE203_PRE -#define DSP2_BLBACK_GAMMA_TABLE203_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE203_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE203_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE203_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE203_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE203_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE203_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE203_PRE_POS)) - -/* 0xE98 : BL_GAMMA_TABLE_103 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_103_OFFSET (0xE98) -#define DSP2_BLBACK_GAMMA_TABLE204_PRE DSP2_BLBACK_GAMMA_TABLE204_PRE -#define DSP2_BLBACK_GAMMA_TABLE204_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE204_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE204_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE204_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE204_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE204_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE204_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE204_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE205_PRE DSP2_BLBACK_GAMMA_TABLE205_PRE -#define DSP2_BLBACK_GAMMA_TABLE205_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE205_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE205_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE205_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE205_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE205_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE205_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE205_PRE_POS)) - -/* 0xE9C : BL_GAMMA_TABLE_104 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_104_OFFSET (0xE9C) -#define DSP2_BLBACK_GAMMA_TABLE206_PRE DSP2_BLBACK_GAMMA_TABLE206_PRE -#define DSP2_BLBACK_GAMMA_TABLE206_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE206_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE206_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE206_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE206_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE206_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE206_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE206_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE207_PRE DSP2_BLBACK_GAMMA_TABLE207_PRE -#define DSP2_BLBACK_GAMMA_TABLE207_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE207_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE207_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE207_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE207_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE207_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE207_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE207_PRE_POS)) - -/* 0xEA0 : BL_GAMMA_TABLE_105 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_105_OFFSET (0xEA0) -#define DSP2_BLBACK_GAMMA_TABLE208_PRE DSP2_BLBACK_GAMMA_TABLE208_PRE -#define DSP2_BLBACK_GAMMA_TABLE208_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE208_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE208_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE208_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE208_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE208_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE208_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE208_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE209_PRE DSP2_BLBACK_GAMMA_TABLE209_PRE -#define DSP2_BLBACK_GAMMA_TABLE209_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE209_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE209_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE209_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE209_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE209_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE209_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE209_PRE_POS)) - -/* 0xEA4 : BL_GAMMA_TABLE_106 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_106_OFFSET (0xEA4) -#define DSP2_BLBACK_GAMMA_TABLE210_PRE DSP2_BLBACK_GAMMA_TABLE210_PRE -#define DSP2_BLBACK_GAMMA_TABLE210_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE210_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE210_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE210_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE210_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE210_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE210_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE210_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE211_PRE DSP2_BLBACK_GAMMA_TABLE211_PRE -#define DSP2_BLBACK_GAMMA_TABLE211_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE211_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE211_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE211_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE211_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE211_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE211_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE211_PRE_POS)) - -/* 0xEA8 : BL_GAMMA_TABLE_107 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_107_OFFSET (0xEA8) -#define DSP2_BLBACK_GAMMA_TABLE212_PRE DSP2_BLBACK_GAMMA_TABLE212_PRE -#define DSP2_BLBACK_GAMMA_TABLE212_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE212_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE212_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE212_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE212_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE212_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE212_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE212_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE213_PRE DSP2_BLBACK_GAMMA_TABLE213_PRE -#define DSP2_BLBACK_GAMMA_TABLE213_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE213_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE213_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE213_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE213_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE213_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE213_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE213_PRE_POS)) - -/* 0xEAC : BL_GAMMA_TABLE_108 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_108_OFFSET (0xEAC) -#define DSP2_BLBACK_GAMMA_TABLE214_PRE DSP2_BLBACK_GAMMA_TABLE214_PRE -#define DSP2_BLBACK_GAMMA_TABLE214_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE214_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE214_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE214_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE214_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE214_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE214_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE214_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE215_PRE DSP2_BLBACK_GAMMA_TABLE215_PRE -#define DSP2_BLBACK_GAMMA_TABLE215_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE215_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE215_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE215_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE215_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE215_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE215_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE215_PRE_POS)) - -/* 0xEB0 : BL_GAMMA_TABLE_109 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_109_OFFSET (0xEB0) -#define DSP2_BLBACK_GAMMA_TABLE216_PRE DSP2_BLBACK_GAMMA_TABLE216_PRE -#define DSP2_BLBACK_GAMMA_TABLE216_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE216_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE216_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE216_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE216_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE216_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE216_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE216_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE217_PRE DSP2_BLBACK_GAMMA_TABLE217_PRE -#define DSP2_BLBACK_GAMMA_TABLE217_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE217_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE217_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE217_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE217_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE217_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE217_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE217_PRE_POS)) - -/* 0xEB4 : BL_GAMMA_TABLE_110 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_110_OFFSET (0xEB4) -#define DSP2_BLBACK_GAMMA_TABLE218_PRE DSP2_BLBACK_GAMMA_TABLE218_PRE -#define DSP2_BLBACK_GAMMA_TABLE218_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE218_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE218_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE218_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE218_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE218_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE218_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE218_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE219_PRE DSP2_BLBACK_GAMMA_TABLE219_PRE -#define DSP2_BLBACK_GAMMA_TABLE219_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE219_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE219_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE219_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE219_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE219_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE219_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE219_PRE_POS)) - -/* 0xEB8 : BL_GAMMA_TABLE_111 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_111_OFFSET (0xEB8) -#define DSP2_BLBACK_GAMMA_TABLE220_PRE DSP2_BLBACK_GAMMA_TABLE220_PRE -#define DSP2_BLBACK_GAMMA_TABLE220_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE220_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE220_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE220_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE220_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE220_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE220_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE220_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE221_PRE DSP2_BLBACK_GAMMA_TABLE221_PRE -#define DSP2_BLBACK_GAMMA_TABLE221_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE221_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE221_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE221_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE221_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE221_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE221_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE221_PRE_POS)) - -/* 0xEBC : BL_GAMMA_TABLE_112 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_112_OFFSET (0xEBC) -#define DSP2_BLBACK_GAMMA_TABLE222_PRE DSP2_BLBACK_GAMMA_TABLE222_PRE -#define DSP2_BLBACK_GAMMA_TABLE222_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE222_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE222_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE222_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE222_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE222_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE222_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE222_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE223_PRE DSP2_BLBACK_GAMMA_TABLE223_PRE -#define DSP2_BLBACK_GAMMA_TABLE223_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE223_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE223_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE223_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE223_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE223_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE223_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE223_PRE_POS)) - -/* 0xEC0 : BL_GAMMA_TABLE_113 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_113_OFFSET (0xEC0) -#define DSP2_BLBACK_GAMMA_TABLE224_PRE DSP2_BLBACK_GAMMA_TABLE224_PRE -#define DSP2_BLBACK_GAMMA_TABLE224_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE224_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE224_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE224_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE224_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE224_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE224_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE224_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE225_PRE DSP2_BLBACK_GAMMA_TABLE225_PRE -#define DSP2_BLBACK_GAMMA_TABLE225_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE225_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE225_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE225_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE225_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE225_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE225_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE225_PRE_POS)) - -/* 0xEC4 : BL_GAMMA_TABLE_114 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_114_OFFSET (0xEC4) -#define DSP2_BLBACK_GAMMA_TABLE226_PRE DSP2_BLBACK_GAMMA_TABLE226_PRE -#define DSP2_BLBACK_GAMMA_TABLE226_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE226_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE226_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE226_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE226_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE226_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE226_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE226_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE227_PRE DSP2_BLBACK_GAMMA_TABLE227_PRE -#define DSP2_BLBACK_GAMMA_TABLE227_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE227_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE227_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE227_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE227_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE227_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE227_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE227_PRE_POS)) - -/* 0xEC8 : BL_GAMMA_TABLE_115 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_115_OFFSET (0xEC8) -#define DSP2_BLBACK_GAMMA_TABLE228_PRE DSP2_BLBACK_GAMMA_TABLE228_PRE -#define DSP2_BLBACK_GAMMA_TABLE228_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE228_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE228_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE228_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE228_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE228_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE228_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE228_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE229_PRE DSP2_BLBACK_GAMMA_TABLE229_PRE -#define DSP2_BLBACK_GAMMA_TABLE229_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE229_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE229_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE229_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE229_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE229_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE229_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE229_PRE_POS)) - -/* 0xECC : BL_GAMMA_TABLE_116 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_116_OFFSET (0xECC) -#define DSP2_BLBACK_GAMMA_TABLE230_PRE DSP2_BLBACK_GAMMA_TABLE230_PRE -#define DSP2_BLBACK_GAMMA_TABLE230_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE230_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE230_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE230_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE230_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE230_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE230_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE230_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE231_PRE DSP2_BLBACK_GAMMA_TABLE231_PRE -#define DSP2_BLBACK_GAMMA_TABLE231_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE231_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE231_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE231_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE231_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE231_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE231_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE231_PRE_POS)) - -/* 0xED0 : BL_GAMMA_TABLE_117 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_117_OFFSET (0xED0) -#define DSP2_BLBACK_GAMMA_TABLE232_PRE DSP2_BLBACK_GAMMA_TABLE232_PRE -#define DSP2_BLBACK_GAMMA_TABLE232_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE232_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE232_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE232_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE232_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE232_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE232_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE232_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE233_PRE DSP2_BLBACK_GAMMA_TABLE233_PRE -#define DSP2_BLBACK_GAMMA_TABLE233_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE233_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE233_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE233_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE233_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE233_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE233_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE233_PRE_POS)) - -/* 0xED4 : BL_GAMMA_TABLE_118 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_118_OFFSET (0xED4) -#define DSP2_BLBACK_GAMMA_TABLE234_PRE DSP2_BLBACK_GAMMA_TABLE234_PRE -#define DSP2_BLBACK_GAMMA_TABLE234_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE234_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE234_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE234_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE234_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE234_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE234_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE234_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE235_PRE DSP2_BLBACK_GAMMA_TABLE235_PRE -#define DSP2_BLBACK_GAMMA_TABLE235_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE235_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE235_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE235_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE235_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE235_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE235_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE235_PRE_POS)) - -/* 0xED8 : BL_GAMMA_TABLE_119 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_119_OFFSET (0xED8) -#define DSP2_BLBACK_GAMMA_TABLE236_PRE DSP2_BLBACK_GAMMA_TABLE236_PRE -#define DSP2_BLBACK_GAMMA_TABLE236_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE236_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE236_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE236_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE236_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE236_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE236_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE236_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE237_PRE DSP2_BLBACK_GAMMA_TABLE237_PRE -#define DSP2_BLBACK_GAMMA_TABLE237_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE237_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE237_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE237_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE237_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE237_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE237_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE237_PRE_POS)) - -/* 0xEDC : BL_GAMMA_TABLE_120 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_120_OFFSET (0xEDC) -#define DSP2_BLBACK_GAMMA_TABLE238_PRE DSP2_BLBACK_GAMMA_TABLE238_PRE -#define DSP2_BLBACK_GAMMA_TABLE238_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE238_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE238_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE238_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE238_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE238_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE238_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE238_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE239_PRE DSP2_BLBACK_GAMMA_TABLE239_PRE -#define DSP2_BLBACK_GAMMA_TABLE239_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE239_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE239_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE239_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE239_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE239_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE239_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE239_PRE_POS)) - -/* 0xEE0 : BL_GAMMA_TABLE_121 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_121_OFFSET (0xEE0) -#define DSP2_BLBACK_GAMMA_TABLE240_PRE DSP2_BLBACK_GAMMA_TABLE240_PRE -#define DSP2_BLBACK_GAMMA_TABLE240_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE240_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE240_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE240_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE240_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE240_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE240_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE240_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE241_PRE DSP2_BLBACK_GAMMA_TABLE241_PRE -#define DSP2_BLBACK_GAMMA_TABLE241_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE241_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE241_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE241_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE241_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE241_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE241_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE241_PRE_POS)) - -/* 0xEE4 : BL_GAMMA_TABLE_122 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_122_OFFSET (0xEE4) -#define DSP2_BLBACK_GAMMA_TABLE242_PRE DSP2_BLBACK_GAMMA_TABLE242_PRE -#define DSP2_BLBACK_GAMMA_TABLE242_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE242_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE242_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE242_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE242_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE242_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE242_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE242_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE243_PRE DSP2_BLBACK_GAMMA_TABLE243_PRE -#define DSP2_BLBACK_GAMMA_TABLE243_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE243_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE243_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE243_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE243_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE243_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE243_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE243_PRE_POS)) - -/* 0xEE8 : BL_GAMMA_TABLE_123 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_123_OFFSET (0xEE8) -#define DSP2_BLBACK_GAMMA_TABLE244_PRE DSP2_BLBACK_GAMMA_TABLE244_PRE -#define DSP2_BLBACK_GAMMA_TABLE244_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE244_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE244_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE244_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE244_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE244_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE244_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE244_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE245_PRE DSP2_BLBACK_GAMMA_TABLE245_PRE -#define DSP2_BLBACK_GAMMA_TABLE245_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE245_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE245_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE245_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE245_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE245_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE245_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE245_PRE_POS)) - -/* 0xEEC : BL_GAMMA_TABLE_124 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_124_OFFSET (0xEEC) -#define DSP2_BLBACK_GAMMA_TABLE246_PRE DSP2_BLBACK_GAMMA_TABLE246_PRE -#define DSP2_BLBACK_GAMMA_TABLE246_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE246_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE246_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE246_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE246_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE246_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE246_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE246_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE247_PRE DSP2_BLBACK_GAMMA_TABLE247_PRE -#define DSP2_BLBACK_GAMMA_TABLE247_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE247_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE247_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE247_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE247_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE247_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE247_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE247_PRE_POS)) - -/* 0xEF0 : BL_GAMMA_TABLE_125 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_125_OFFSET (0xEF0) -#define DSP2_BLBACK_GAMMA_TABLE248_PRE DSP2_BLBACK_GAMMA_TABLE248_PRE -#define DSP2_BLBACK_GAMMA_TABLE248_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE248_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE248_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE248_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE248_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE248_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE248_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE248_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE249_PRE DSP2_BLBACK_GAMMA_TABLE249_PRE -#define DSP2_BLBACK_GAMMA_TABLE249_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE249_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE249_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE249_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE249_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE249_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE249_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE249_PRE_POS)) - -/* 0xEF4 : BL_GAMMA_TABLE_126 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_126_OFFSET (0xEF4) -#define DSP2_BLBACK_GAMMA_TABLE250_PRE DSP2_BLBACK_GAMMA_TABLE250_PRE -#define DSP2_BLBACK_GAMMA_TABLE250_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE250_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE250_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE250_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE250_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE250_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE250_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE250_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE251_PRE DSP2_BLBACK_GAMMA_TABLE251_PRE -#define DSP2_BLBACK_GAMMA_TABLE251_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE251_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE251_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE251_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE251_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE251_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE251_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE251_PRE_POS)) - -/* 0xEF8 : BL_GAMMA_TABLE_127 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_127_OFFSET (0xEF8) -#define DSP2_BLBACK_GAMMA_TABLE252_PRE DSP2_BLBACK_GAMMA_TABLE252_PRE -#define DSP2_BLBACK_GAMMA_TABLE252_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE252_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE252_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE252_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE252_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE252_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE252_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE252_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE253_PRE DSP2_BLBACK_GAMMA_TABLE253_PRE -#define DSP2_BLBACK_GAMMA_TABLE253_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE253_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE253_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE253_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE253_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE253_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE253_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE253_PRE_POS)) - -/* 0xEFC : BL_GAMMA_TABLE_128 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_128_OFFSET (0xEFC) -#define DSP2_BLBACK_GAMMA_TABLE254_PRE DSP2_BLBACK_GAMMA_TABLE254_PRE -#define DSP2_BLBACK_GAMMA_TABLE254_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE254_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE254_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE254_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE254_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE254_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE254_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE254_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE255_PRE DSP2_BLBACK_GAMMA_TABLE255_PRE -#define DSP2_BLBACK_GAMMA_TABLE255_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE255_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE255_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE255_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE255_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE255_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE255_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE255_PRE_POS)) - -/* 0xF00 : CC_OFFSET_0 */ -#define DSP2_BLBACK_CC_OFFSET_0_OFFSET (0xF00) -#define DSP2_BLBACK_CC_PRE_OFFSET0_PRE DSP2_BLBACK_CC_PRE_OFFSET0_PRE -#define DSP2_BLBACK_CC_PRE_OFFSET0_PRE_POS (0U) -#define DSP2_BLBACK_CC_PRE_OFFSET0_PRE_LEN (13U) -#define DSP2_BLBACK_CC_PRE_OFFSET0_PRE_MSK (((1U << DSP2_BLBACK_CC_PRE_OFFSET0_PRE_LEN) - 1) << DSP2_BLBACK_CC_PRE_OFFSET0_PRE_POS) -#define DSP2_BLBACK_CC_PRE_OFFSET0_PRE_UMSK (~(((1U << DSP2_BLBACK_CC_PRE_OFFSET0_PRE_LEN) - 1) << DSP2_BLBACK_CC_PRE_OFFSET0_PRE_POS)) -#define DSP2_BLBACK_CC_PRE_OFFSET1_PRE DSP2_BLBACK_CC_PRE_OFFSET1_PRE -#define DSP2_BLBACK_CC_PRE_OFFSET1_PRE_POS (16U) -#define DSP2_BLBACK_CC_PRE_OFFSET1_PRE_LEN (13U) -#define DSP2_BLBACK_CC_PRE_OFFSET1_PRE_MSK (((1U << DSP2_BLBACK_CC_PRE_OFFSET1_PRE_LEN) - 1) << DSP2_BLBACK_CC_PRE_OFFSET1_PRE_POS) -#define DSP2_BLBACK_CC_PRE_OFFSET1_PRE_UMSK (~(((1U << DSP2_BLBACK_CC_PRE_OFFSET1_PRE_LEN) - 1) << DSP2_BLBACK_CC_PRE_OFFSET1_PRE_POS)) -#define DSP2_BLBACK_CC_ENABLE_PRE DSP2_BLBACK_CC_ENABLE_PRE -#define DSP2_BLBACK_CC_ENABLE_PRE_POS (31U) -#define DSP2_BLBACK_CC_ENABLE_PRE_LEN (1U) -#define DSP2_BLBACK_CC_ENABLE_PRE_MSK (((1U << DSP2_BLBACK_CC_ENABLE_PRE_LEN) - 1) << DSP2_BLBACK_CC_ENABLE_PRE_POS) -#define DSP2_BLBACK_CC_ENABLE_PRE_UMSK (~(((1U << DSP2_BLBACK_CC_ENABLE_PRE_LEN) - 1) << DSP2_BLBACK_CC_ENABLE_PRE_POS)) - -/* 0xF04 : CC_OFFSET_1 */ -#define DSP2_BLBACK_CC_OFFSET_1_OFFSET (0xF04) -#define DSP2_BLBACK_CC_PRE_OFFSET2_PRE DSP2_BLBACK_CC_PRE_OFFSET2_PRE -#define DSP2_BLBACK_CC_PRE_OFFSET2_PRE_POS (0U) -#define DSP2_BLBACK_CC_PRE_OFFSET2_PRE_LEN (13U) -#define DSP2_BLBACK_CC_PRE_OFFSET2_PRE_MSK (((1U << DSP2_BLBACK_CC_PRE_OFFSET2_PRE_LEN) - 1) << DSP2_BLBACK_CC_PRE_OFFSET2_PRE_POS) -#define DSP2_BLBACK_CC_PRE_OFFSET2_PRE_UMSK (~(((1U << DSP2_BLBACK_CC_PRE_OFFSET2_PRE_LEN) - 1) << DSP2_BLBACK_CC_PRE_OFFSET2_PRE_POS)) -#define DSP2_BLBACK_CC_POST_OFFSET2_PRE DSP2_BLBACK_CC_POST_OFFSET2_PRE -#define DSP2_BLBACK_CC_POST_OFFSET2_PRE_POS (16U) -#define DSP2_BLBACK_CC_POST_OFFSET2_PRE_LEN (13U) -#define DSP2_BLBACK_CC_POST_OFFSET2_PRE_MSK (((1U << DSP2_BLBACK_CC_POST_OFFSET2_PRE_LEN) - 1) << DSP2_BLBACK_CC_POST_OFFSET2_PRE_POS) -#define DSP2_BLBACK_CC_POST_OFFSET2_PRE_UMSK (~(((1U << DSP2_BLBACK_CC_POST_OFFSET2_PRE_LEN) - 1) << DSP2_BLBACK_CC_POST_OFFSET2_PRE_POS)) - -/* 0xF08 : CC_OFFSET_2 */ -#define DSP2_BLBACK_CC_OFFSET_2_OFFSET (0xF08) -#define DSP2_BLBACK_CC_POST_OFFSET0_PRE DSP2_BLBACK_CC_POST_OFFSET0_PRE -#define DSP2_BLBACK_CC_POST_OFFSET0_PRE_POS (0U) -#define DSP2_BLBACK_CC_POST_OFFSET0_PRE_LEN (13U) -#define DSP2_BLBACK_CC_POST_OFFSET0_PRE_MSK (((1U << DSP2_BLBACK_CC_POST_OFFSET0_PRE_LEN) - 1) << DSP2_BLBACK_CC_POST_OFFSET0_PRE_POS) -#define DSP2_BLBACK_CC_POST_OFFSET0_PRE_UMSK (~(((1U << DSP2_BLBACK_CC_POST_OFFSET0_PRE_LEN) - 1) << DSP2_BLBACK_CC_POST_OFFSET0_PRE_POS)) -#define DSP2_BLBACK_CC_POST_OFFSET1_PRE DSP2_BLBACK_CC_POST_OFFSET1_PRE -#define DSP2_BLBACK_CC_POST_OFFSET1_PRE_POS (16U) -#define DSP2_BLBACK_CC_POST_OFFSET1_PRE_LEN (13U) -#define DSP2_BLBACK_CC_POST_OFFSET1_PRE_MSK (((1U << DSP2_BLBACK_CC_POST_OFFSET1_PRE_LEN) - 1) << DSP2_BLBACK_CC_POST_OFFSET1_PRE_POS) -#define DSP2_BLBACK_CC_POST_OFFSET1_PRE_UMSK (~(((1U << DSP2_BLBACK_CC_POST_OFFSET1_PRE_LEN) - 1) << DSP2_BLBACK_CC_POST_OFFSET1_PRE_POS)) - -/* 0xF0C : CC_MATRIX_0 */ -#define DSP2_BLBACK_CC_MATRIX_0_OFFSET (0xF0C) -#define DSP2_BLBACK_CC_MATRIX00_PRE DSP2_BLBACK_CC_MATRIX00_PRE -#define DSP2_BLBACK_CC_MATRIX00_PRE_POS (0U) -#define DSP2_BLBACK_CC_MATRIX00_PRE_LEN (12U) -#define DSP2_BLBACK_CC_MATRIX00_PRE_MSK (((1U << DSP2_BLBACK_CC_MATRIX00_PRE_LEN) - 1) << DSP2_BLBACK_CC_MATRIX00_PRE_POS) -#define DSP2_BLBACK_CC_MATRIX00_PRE_UMSK (~(((1U << DSP2_BLBACK_CC_MATRIX00_PRE_LEN) - 1) << DSP2_BLBACK_CC_MATRIX00_PRE_POS)) -#define DSP2_BLBACK_CC_MATRIX01_PRE DSP2_BLBACK_CC_MATRIX01_PRE -#define DSP2_BLBACK_CC_MATRIX01_PRE_POS (16U) -#define DSP2_BLBACK_CC_MATRIX01_PRE_LEN (12U) -#define DSP2_BLBACK_CC_MATRIX01_PRE_MSK (((1U << DSP2_BLBACK_CC_MATRIX01_PRE_LEN) - 1) << DSP2_BLBACK_CC_MATRIX01_PRE_POS) -#define DSP2_BLBACK_CC_MATRIX01_PRE_UMSK (~(((1U << DSP2_BLBACK_CC_MATRIX01_PRE_LEN) - 1) << DSP2_BLBACK_CC_MATRIX01_PRE_POS)) - -/* 0xF10 : CC_MATRIX_1 */ -#define DSP2_BLBACK_CC_MATRIX_1_OFFSET (0xF10) -#define DSP2_BLBACK_CC_MATRIX10_PRE DSP2_BLBACK_CC_MATRIX10_PRE -#define DSP2_BLBACK_CC_MATRIX10_PRE_POS (0U) -#define DSP2_BLBACK_CC_MATRIX10_PRE_LEN (12U) -#define DSP2_BLBACK_CC_MATRIX10_PRE_MSK (((1U << DSP2_BLBACK_CC_MATRIX10_PRE_LEN) - 1) << DSP2_BLBACK_CC_MATRIX10_PRE_POS) -#define DSP2_BLBACK_CC_MATRIX10_PRE_UMSK (~(((1U << DSP2_BLBACK_CC_MATRIX10_PRE_LEN) - 1) << DSP2_BLBACK_CC_MATRIX10_PRE_POS)) -#define DSP2_BLBACK_CC_MATRIX02_PRE DSP2_BLBACK_CC_MATRIX02_PRE -#define DSP2_BLBACK_CC_MATRIX02_PRE_POS (16U) -#define DSP2_BLBACK_CC_MATRIX02_PRE_LEN (12U) -#define DSP2_BLBACK_CC_MATRIX02_PRE_MSK (((1U << DSP2_BLBACK_CC_MATRIX02_PRE_LEN) - 1) << DSP2_BLBACK_CC_MATRIX02_PRE_POS) -#define DSP2_BLBACK_CC_MATRIX02_PRE_UMSK (~(((1U << DSP2_BLBACK_CC_MATRIX02_PRE_LEN) - 1) << DSP2_BLBACK_CC_MATRIX02_PRE_POS)) - -/* 0xF14 : CC_MATRIX_2 */ -#define DSP2_BLBACK_CC_MATRIX_2_OFFSET (0xF14) -#define DSP2_BLBACK_CC_MATRIX11_PRE DSP2_BLBACK_CC_MATRIX11_PRE -#define DSP2_BLBACK_CC_MATRIX11_PRE_POS (0U) -#define DSP2_BLBACK_CC_MATRIX11_PRE_LEN (12U) -#define DSP2_BLBACK_CC_MATRIX11_PRE_MSK (((1U << DSP2_BLBACK_CC_MATRIX11_PRE_LEN) - 1) << DSP2_BLBACK_CC_MATRIX11_PRE_POS) -#define DSP2_BLBACK_CC_MATRIX11_PRE_UMSK (~(((1U << DSP2_BLBACK_CC_MATRIX11_PRE_LEN) - 1) << DSP2_BLBACK_CC_MATRIX11_PRE_POS)) -#define DSP2_BLBACK_CC_MATRIX12_PRE DSP2_BLBACK_CC_MATRIX12_PRE -#define DSP2_BLBACK_CC_MATRIX12_PRE_POS (16U) -#define DSP2_BLBACK_CC_MATRIX12_PRE_LEN (12U) -#define DSP2_BLBACK_CC_MATRIX12_PRE_MSK (((1U << DSP2_BLBACK_CC_MATRIX12_PRE_LEN) - 1) << DSP2_BLBACK_CC_MATRIX12_PRE_POS) -#define DSP2_BLBACK_CC_MATRIX12_PRE_UMSK (~(((1U << DSP2_BLBACK_CC_MATRIX12_PRE_LEN) - 1) << DSP2_BLBACK_CC_MATRIX12_PRE_POS)) - -/* 0xF18 : CC_MATRIX_3 */ -#define DSP2_BLBACK_CC_MATRIX_3_OFFSET (0xF18) -#define DSP2_BLBACK_CC_MATRIX20_PRE DSP2_BLBACK_CC_MATRIX20_PRE -#define DSP2_BLBACK_CC_MATRIX20_PRE_POS (0U) -#define DSP2_BLBACK_CC_MATRIX20_PRE_LEN (12U) -#define DSP2_BLBACK_CC_MATRIX20_PRE_MSK (((1U << DSP2_BLBACK_CC_MATRIX20_PRE_LEN) - 1) << DSP2_BLBACK_CC_MATRIX20_PRE_POS) -#define DSP2_BLBACK_CC_MATRIX20_PRE_UMSK (~(((1U << DSP2_BLBACK_CC_MATRIX20_PRE_LEN) - 1) << DSP2_BLBACK_CC_MATRIX20_PRE_POS)) -#define DSP2_BLBACK_CC_MATRIX21_PRE DSP2_BLBACK_CC_MATRIX21_PRE -#define DSP2_BLBACK_CC_MATRIX21_PRE_POS (16U) -#define DSP2_BLBACK_CC_MATRIX21_PRE_LEN (12U) -#define DSP2_BLBACK_CC_MATRIX21_PRE_MSK (((1U << DSP2_BLBACK_CC_MATRIX21_PRE_LEN) - 1) << DSP2_BLBACK_CC_MATRIX21_PRE_POS) -#define DSP2_BLBACK_CC_MATRIX21_PRE_UMSK (~(((1U << DSP2_BLBACK_CC_MATRIX21_PRE_LEN) - 1) << DSP2_BLBACK_CC_MATRIX21_PRE_POS)) - -/* 0xF1C : CC_CE_MATRIX */ -#define DSP2_BLBACK_CC_CE_MATRIX_OFFSET (0xF1C) -#define DSP2_BLBACK_CC_MATRIX22_PRE DSP2_BLBACK_CC_MATRIX22_PRE -#define DSP2_BLBACK_CC_MATRIX22_PRE_POS (0U) -#define DSP2_BLBACK_CC_MATRIX22_PRE_LEN (12U) -#define DSP2_BLBACK_CC_MATRIX22_PRE_MSK (((1U << DSP2_BLBACK_CC_MATRIX22_PRE_LEN) - 1) << DSP2_BLBACK_CC_MATRIX22_PRE_POS) -#define DSP2_BLBACK_CC_MATRIX22_PRE_UMSK (~(((1U << DSP2_BLBACK_CC_MATRIX22_PRE_LEN) - 1) << DSP2_BLBACK_CC_MATRIX22_PRE_POS)) -#define DSP2_BLBACK_CE_MATRIX02_PRE DSP2_BLBACK_CE_MATRIX02_PRE -#define DSP2_BLBACK_CE_MATRIX02_PRE_POS (16U) -#define DSP2_BLBACK_CE_MATRIX02_PRE_LEN (12U) -#define DSP2_BLBACK_CE_MATRIX02_PRE_MSK (((1U << DSP2_BLBACK_CE_MATRIX02_PRE_LEN) - 1) << DSP2_BLBACK_CE_MATRIX02_PRE_POS) -#define DSP2_BLBACK_CE_MATRIX02_PRE_UMSK (~(((1U << DSP2_BLBACK_CE_MATRIX02_PRE_LEN) - 1) << DSP2_BLBACK_CE_MATRIX02_PRE_POS)) - -/* 0xF20 : CE_MATRIX_0 */ -#define DSP2_BLBACK_CE_MATRIX_0_OFFSET (0xF20) -#define DSP2_BLBACK_CE_MATRIX00_PRE DSP2_BLBACK_CE_MATRIX00_PRE -#define DSP2_BLBACK_CE_MATRIX00_PRE_POS (0U) -#define DSP2_BLBACK_CE_MATRIX00_PRE_LEN (12U) -#define DSP2_BLBACK_CE_MATRIX00_PRE_MSK (((1U << DSP2_BLBACK_CE_MATRIX00_PRE_LEN) - 1) << DSP2_BLBACK_CE_MATRIX00_PRE_POS) -#define DSP2_BLBACK_CE_MATRIX00_PRE_UMSK (~(((1U << DSP2_BLBACK_CE_MATRIX00_PRE_LEN) - 1) << DSP2_BLBACK_CE_MATRIX00_PRE_POS)) -#define DSP2_BLBACK_CE_MATRIX01_PRE DSP2_BLBACK_CE_MATRIX01_PRE -#define DSP2_BLBACK_CE_MATRIX01_PRE_POS (16U) -#define DSP2_BLBACK_CE_MATRIX01_PRE_LEN (12U) -#define DSP2_BLBACK_CE_MATRIX01_PRE_MSK (((1U << DSP2_BLBACK_CE_MATRIX01_PRE_LEN) - 1) << DSP2_BLBACK_CE_MATRIX01_PRE_POS) -#define DSP2_BLBACK_CE_MATRIX01_PRE_UMSK (~(((1U << DSP2_BLBACK_CE_MATRIX01_PRE_LEN) - 1) << DSP2_BLBACK_CE_MATRIX01_PRE_POS)) - -/* 0xF24 : CE_MATRIX_1 */ -#define DSP2_BLBACK_CE_MATRIX_1_OFFSET (0xF24) -#define DSP2_BLBACK_CE_MATRIX10_PRE DSP2_BLBACK_CE_MATRIX10_PRE -#define DSP2_BLBACK_CE_MATRIX10_PRE_POS (0U) -#define DSP2_BLBACK_CE_MATRIX10_PRE_LEN (12U) -#define DSP2_BLBACK_CE_MATRIX10_PRE_MSK (((1U << DSP2_BLBACK_CE_MATRIX10_PRE_LEN) - 1) << DSP2_BLBACK_CE_MATRIX10_PRE_POS) -#define DSP2_BLBACK_CE_MATRIX10_PRE_UMSK (~(((1U << DSP2_BLBACK_CE_MATRIX10_PRE_LEN) - 1) << DSP2_BLBACK_CE_MATRIX10_PRE_POS)) -#define DSP2_BLBACK_CE_MATRIX11_PRE DSP2_BLBACK_CE_MATRIX11_PRE -#define DSP2_BLBACK_CE_MATRIX11_PRE_POS (16U) -#define DSP2_BLBACK_CE_MATRIX11_PRE_LEN (12U) -#define DSP2_BLBACK_CE_MATRIX11_PRE_MSK (((1U << DSP2_BLBACK_CE_MATRIX11_PRE_LEN) - 1) << DSP2_BLBACK_CE_MATRIX11_PRE_POS) -#define DSP2_BLBACK_CE_MATRIX11_PRE_UMSK (~(((1U << DSP2_BLBACK_CE_MATRIX11_PRE_LEN) - 1) << DSP2_BLBACK_CE_MATRIX11_PRE_POS)) - -/* 0xF28 : CE_MATRIX_2 */ -#define DSP2_BLBACK_CE_MATRIX_2_OFFSET (0xF28) -#define DSP2_BLBACK_CE_MATRIX20_PRE DSP2_BLBACK_CE_MATRIX20_PRE -#define DSP2_BLBACK_CE_MATRIX20_PRE_POS (0U) -#define DSP2_BLBACK_CE_MATRIX20_PRE_LEN (12U) -#define DSP2_BLBACK_CE_MATRIX20_PRE_MSK (((1U << DSP2_BLBACK_CE_MATRIX20_PRE_LEN) - 1) << DSP2_BLBACK_CE_MATRIX20_PRE_POS) -#define DSP2_BLBACK_CE_MATRIX20_PRE_UMSK (~(((1U << DSP2_BLBACK_CE_MATRIX20_PRE_LEN) - 1) << DSP2_BLBACK_CE_MATRIX20_PRE_POS)) -#define DSP2_BLBACK_CE_MATRIX12_PRE DSP2_BLBACK_CE_MATRIX12_PRE -#define DSP2_BLBACK_CE_MATRIX12_PRE_POS (16U) -#define DSP2_BLBACK_CE_MATRIX12_PRE_LEN (12U) -#define DSP2_BLBACK_CE_MATRIX12_PRE_MSK (((1U << DSP2_BLBACK_CE_MATRIX12_PRE_LEN) - 1) << DSP2_BLBACK_CE_MATRIX12_PRE_POS) -#define DSP2_BLBACK_CE_MATRIX12_PRE_UMSK (~(((1U << DSP2_BLBACK_CE_MATRIX12_PRE_LEN) - 1) << DSP2_BLBACK_CE_MATRIX12_PRE_POS)) - -/* 0xF2C : CE_MATRIX_3 */ -#define DSP2_BLBACK_CE_MATRIX_3_OFFSET (0xF2C) -#define DSP2_BLBACK_CE_MATRIX21_PRE DSP2_BLBACK_CE_MATRIX21_PRE -#define DSP2_BLBACK_CE_MATRIX21_PRE_POS (0U) -#define DSP2_BLBACK_CE_MATRIX21_PRE_LEN (12U) -#define DSP2_BLBACK_CE_MATRIX21_PRE_MSK (((1U << DSP2_BLBACK_CE_MATRIX21_PRE_LEN) - 1) << DSP2_BLBACK_CE_MATRIX21_PRE_POS) -#define DSP2_BLBACK_CE_MATRIX21_PRE_UMSK (~(((1U << DSP2_BLBACK_CE_MATRIX21_PRE_LEN) - 1) << DSP2_BLBACK_CE_MATRIX21_PRE_POS)) -#define DSP2_BLBACK_CE_MATRIX22_PRE DSP2_BLBACK_CE_MATRIX22_PRE -#define DSP2_BLBACK_CE_MATRIX22_PRE_POS (16U) -#define DSP2_BLBACK_CE_MATRIX22_PRE_LEN (12U) -#define DSP2_BLBACK_CE_MATRIX22_PRE_MSK (((1U << DSP2_BLBACK_CE_MATRIX22_PRE_LEN) - 1) << DSP2_BLBACK_CE_MATRIX22_PRE_POS) -#define DSP2_BLBACK_CE_MATRIX22_PRE_UMSK (~(((1U << DSP2_BLBACK_CE_MATRIX22_PRE_LEN) - 1) << DSP2_BLBACK_CE_MATRIX22_PRE_POS)) - -/* 0xF30 : CE_OFFSET_0 */ -#define DSP2_BLBACK_CE_OFFSET_0_OFFSET (0xF30) -#define DSP2_BLBACK_CE_PRE_OFFSET0_PRE DSP2_BLBACK_CE_PRE_OFFSET0_PRE -#define DSP2_BLBACK_CE_PRE_OFFSET0_PRE_POS (0U) -#define DSP2_BLBACK_CE_PRE_OFFSET0_PRE_LEN (13U) -#define DSP2_BLBACK_CE_PRE_OFFSET0_PRE_MSK (((1U << DSP2_BLBACK_CE_PRE_OFFSET0_PRE_LEN) - 1) << DSP2_BLBACK_CE_PRE_OFFSET0_PRE_POS) -#define DSP2_BLBACK_CE_PRE_OFFSET0_PRE_UMSK (~(((1U << DSP2_BLBACK_CE_PRE_OFFSET0_PRE_LEN) - 1) << DSP2_BLBACK_CE_PRE_OFFSET0_PRE_POS)) -#define DSP2_BLBACK_CE_PRE_OFFSET1_PRE DSP2_BLBACK_CE_PRE_OFFSET1_PRE -#define DSP2_BLBACK_CE_PRE_OFFSET1_PRE_POS (16U) -#define DSP2_BLBACK_CE_PRE_OFFSET1_PRE_LEN (13U) -#define DSP2_BLBACK_CE_PRE_OFFSET1_PRE_MSK (((1U << DSP2_BLBACK_CE_PRE_OFFSET1_PRE_LEN) - 1) << DSP2_BLBACK_CE_PRE_OFFSET1_PRE_POS) -#define DSP2_BLBACK_CE_PRE_OFFSET1_PRE_UMSK (~(((1U << DSP2_BLBACK_CE_PRE_OFFSET1_PRE_LEN) - 1) << DSP2_BLBACK_CE_PRE_OFFSET1_PRE_POS)) - -/* 0xF34 : CE_OFFSET_1 */ -#define DSP2_BLBACK_CE_OFFSET_1_OFFSET (0xF34) -#define DSP2_BLBACK_CE_PRE_OFFSET2_PRE DSP2_BLBACK_CE_PRE_OFFSET2_PRE -#define DSP2_BLBACK_CE_PRE_OFFSET2_PRE_POS (0U) -#define DSP2_BLBACK_CE_PRE_OFFSET2_PRE_LEN (13U) -#define DSP2_BLBACK_CE_PRE_OFFSET2_PRE_MSK (((1U << DSP2_BLBACK_CE_PRE_OFFSET2_PRE_LEN) - 1) << DSP2_BLBACK_CE_PRE_OFFSET2_PRE_POS) -#define DSP2_BLBACK_CE_PRE_OFFSET2_PRE_UMSK (~(((1U << DSP2_BLBACK_CE_PRE_OFFSET2_PRE_LEN) - 1) << DSP2_BLBACK_CE_PRE_OFFSET2_PRE_POS)) -#define DSP2_BLBACK_CE_POST_OFFSET2_PRE DSP2_BLBACK_CE_POST_OFFSET2_PRE -#define DSP2_BLBACK_CE_POST_OFFSET2_PRE_POS (16U) -#define DSP2_BLBACK_CE_POST_OFFSET2_PRE_LEN (13U) -#define DSP2_BLBACK_CE_POST_OFFSET2_PRE_MSK (((1U << DSP2_BLBACK_CE_POST_OFFSET2_PRE_LEN) - 1) << DSP2_BLBACK_CE_POST_OFFSET2_PRE_POS) -#define DSP2_BLBACK_CE_POST_OFFSET2_PRE_UMSK (~(((1U << DSP2_BLBACK_CE_POST_OFFSET2_PRE_LEN) - 1) << DSP2_BLBACK_CE_POST_OFFSET2_PRE_POS)) - -/* 0xF38 : CE_OFFSET_2 */ -#define DSP2_BLBACK_CE_OFFSET_2_OFFSET (0xF38) -#define DSP2_BLBACK_CE_POST_OFFSET0_PRE DSP2_BLBACK_CE_POST_OFFSET0_PRE -#define DSP2_BLBACK_CE_POST_OFFSET0_PRE_POS (0U) -#define DSP2_BLBACK_CE_POST_OFFSET0_PRE_LEN (13U) -#define DSP2_BLBACK_CE_POST_OFFSET0_PRE_MSK (((1U << DSP2_BLBACK_CE_POST_OFFSET0_PRE_LEN) - 1) << DSP2_BLBACK_CE_POST_OFFSET0_PRE_POS) -#define DSP2_BLBACK_CE_POST_OFFSET0_PRE_UMSK (~(((1U << DSP2_BLBACK_CE_POST_OFFSET0_PRE_LEN) - 1) << DSP2_BLBACK_CE_POST_OFFSET0_PRE_POS)) -#define DSP2_BLBACK_CE_POST_OFFSET1_PRE DSP2_BLBACK_CE_POST_OFFSET1_PRE -#define DSP2_BLBACK_CE_POST_OFFSET1_PRE_POS (16U) -#define DSP2_BLBACK_CE_POST_OFFSET1_PRE_LEN (13U) -#define DSP2_BLBACK_CE_POST_OFFSET1_PRE_MSK (((1U << DSP2_BLBACK_CE_POST_OFFSET1_PRE_LEN) - 1) << DSP2_BLBACK_CE_POST_OFFSET1_PRE_POS) -#define DSP2_BLBACK_CE_POST_OFFSET1_PRE_UMSK (~(((1U << DSP2_BLBACK_CE_POST_OFFSET1_PRE_LEN) - 1) << DSP2_BLBACK_CE_POST_OFFSET1_PRE_POS)) - -struct dsp2_blback_reg { - /* 0x0 reserved */ - uint8_t RESERVED0x0[788]; - - /* 0x314 : ccr_coef_A */ - union { - struct { - uint32_t reserved_0_15 : 16; /* [15: 0], rsvd, 0x0 */ - uint32_t a11_pre : 12; /* [27:16], r/w, 0x200 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } ccr_coef_A; - - /* 0x318 : ccr_coef_B */ - union { - struct { - uint32_t a12_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t a13_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } ccr_coef_B; - - /* 0x31C : ccr_coef_C */ - union { - struct { - uint32_t a21_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t a22_pre : 12; /* [27:16], r/w, 0x200 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } ccr_coef_C; - - /* 0x320 : ccr_coef_D */ - union { - struct { - uint32_t a23_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t a31_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } ccr_coef_D; - - /* 0x324 : ccr_coef_E */ - union { - struct { - uint32_t a32_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t a33_pre : 12; /* [27:16], r/w, 0x200 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } ccr_coef_E; - - /* 0x328 : gamma_A */ - union { - struct { - uint32_t gamma_on_pre : 1; /* [ 0], r/w, 0x0 */ - uint32_t gamma_eb_pre : 1; /* [ 1], r/w, 0x0 */ - uint32_t reserved_2_3 : 2; /* [ 3: 2], rsvd, 0x0 */ - uint32_t bl_gamma_en_pre : 1; /* [ 4], r/w, 0x0 */ - uint32_t reserved_5_31 : 27; /* [31: 5], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } gamma_A; - - /* 0x32c reserved */ - uint8_t RESERVED0x32c[16]; - - /* 0x33C : conv_mode */ - union { - struct { - uint32_t conv_mode_w : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } conv_mode; - - /* 0x340 reserved */ - uint8_t RESERVED0x340[12]; - - /* 0x34C : YUVC_A */ - union { - struct { - uint32_t YBrightness_w : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t YContrast_w : 8; /* [15: 8], r/w, 0x0 */ - uint32_t CbSaturation_pre : 8; /* [23:16], r/w, 0x80 */ - uint32_t CrSaturation_pre : 8; /* [31:24], r/w, 0x80 */ - } BF; - uint32_t WORD; - } YUVC_A; - - /* 0x350 : YUVC_B */ - union { - struct { - uint32_t SpecialMode_w : 3; /* [ 2: 0], r/w, 0x0 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t C444to422Filteringmode_w : 1; /* [ 4], r/w, 0x0 */ - uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ - uint32_t SepiaCb_w : 8; /* [15: 8], r/w, 0x73 */ - uint32_t SepiaCr_w : 8; /* [23:16], r/w, 0x89 */ - uint32_t SolarThred_w : 8; /* [31:24], r/w, 0x80 */ - } BF; - uint32_t WORD; - } YUVC_B; - - /* 0x354 : DNR_A */ - union { - struct { - uint32_t noise_level_pre : 6; /* [ 5: 0], r/w, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t nr_hsize_pre : 16; /* [23: 8], r/w, 0x788 */ - uint32_t Filt_Strength_2D_pre : 4; /* [27:24], r/w, 0x6 */ - uint32_t Filt_Strength_3D_pre : 4; /* [31:28], r/w, 0x5 */ - } BF; - uint32_t WORD; - } DNR_A; - - /* 0x358 : DNR_B */ - union { - struct { - uint32_t reserved_0_7 : 8; /* [ 7: 0], rsvd, 0x0 */ - uint32_t CbCr_select_w : 1; /* [ 8], r/w, 0x1 */ - uint32_t out_format_w : 2; /* [10: 9], r/w, 0x1 */ - uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DNR_B; - - /* 0x35c reserved */ - uint8_t RESERVED0x35c[4]; - - /* 0x360 : BLEE_0 */ - union { - struct { - uint32_t ee_eb_pre : 1; /* [ 0], r/w, 0x0 */ - uint32_t ovrsht_eb_pre : 1; /* [ 1], r/w, 0x0 */ - uint32_t reserved_2_15 : 14; /* [15: 2], rsvd, 0x0 */ - uint32_t txt_thr_pre : 9; /* [24:16], r/w, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BLEE_0; - - /* 0x364 : BLEE_1 */ - union { - struct { - uint32_t thresh1_pre : 7; /* [ 6: 0], r/w, 0x0 */ - uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ - uint32_t thresh2_pre : 7; /* [14: 8], r/w, 0x0 */ - uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */ - uint32_t flat_thr_pre : 8; /* [23:16], r/w, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BLEE_1; - - /* 0x368 : BLEE_2 */ - union { - struct { - uint32_t ovrsht_pos_pre : 7; /* [ 6: 0], r/w, 0x0 */ - uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ - uint32_t ovrsht_neg_pre : 7; /* [14: 8], r/w, 0x0 */ - uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */ - uint32_t posee_str_pre : 7; /* [22:16], r/w, 0x0 */ - uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */ - uint32_t negee_str_pre : 7; /* [30:24], r/w, 0x0 */ - uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BLEE_2; - - /* 0x36C : BLEE_3 */ - union { - struct { - uint32_t edge_thr_pre : 16; /* [15: 0], r/w, 0x0 */ - uint32_t nr_str_pre : 8; /* [23:16], r/w, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BLEE_3; - - /* 0x370 : BLEE_4 */ - union { - struct { - uint32_t luma_wgt0_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t luma_wgt1_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BLEE_4; - - /* 0x374 : BLEE_5 */ - union { - struct { - uint32_t luma_wgt2_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t luma_wgt3_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BLEE_5; - - /* 0x378 : BLEE_6 */ - union { - struct { - uint32_t luma_wgt4_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t luma_wgt5_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BLEE_6; - - /* 0x37C : BLEE_7 */ - union { - struct { - uint32_t luma_wgt6_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t luma_wgt7_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BLEE_7; - - /* 0x380 : BLEE_8 */ - union { - struct { - uint32_t luma_wgt8_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t luma_wgt9_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BLEE_8; - - /* 0x384 : BLEE_9 */ - union { - struct { - uint32_t luma_wgt10_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t luma_wgt11_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BLEE_9; - - /* 0x388 : BLEE_A */ - union { - struct { - uint32_t luma_wgt12_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t luma_wgt13_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BLEE_A; - - /* 0x38C : BLEE_B */ - union { - struct { - uint32_t luma_wgt14_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t luma_wgt15_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BLEE_B; - - /* 0x390 : BLEE_C */ - union { - struct { - uint32_t luma_wgt16_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t luma_wgt17_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BLEE_C; - - /* 0x394 : BLEE_D */ - union { - struct { - uint32_t luma_wgt18_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t luma_wgt19_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BLEE_D; - - /* 0x398 : BLEE_E */ - union { - struct { - uint32_t luma_wgt20_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t luma_wgt21_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BLEE_E; - - /* 0x39C : BLEE_F */ - union { - struct { - uint32_t luma_wgt22_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t luma_wgt23_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BLEE_F; - - /* 0x3A0 : BLEE_10 */ - union { - struct { - uint32_t luma_wgt24_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t luma_wgt25_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BLEE_10; - - /* 0x3A4 : BLEE_11 */ - union { - struct { - uint32_t luma_wgt26_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t luma_wgt27_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BLEE_11; - - /* 0x3A8 : BLEE_12 */ - union { - struct { - uint32_t luma_wgt28_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t luma_wgt29_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BLEE_12; - - /* 0x3AC : BLEE_13 */ - union { - struct { - uint32_t luma_wgt30_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t luma_wgt31_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BLEE_13; - - /* 0x3B0 : CS1 */ - union { - struct { - uint32_t cs1_grey_th_pre : 4; /* [ 3: 0], r/w, 0x0 */ - uint32_t cs1_enable_pre : 1; /* [ 4], r/w, 0x0 */ - uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ - uint32_t cs1_weight_pre : 5; /* [12: 8], r/w, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t cs1_gain_pre : 9; /* [24:16], r/w, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } CS1; - - /* 0x3B4 : CS2 */ - union { - struct { - uint32_t cs2_grey_th_pre : 4; /* [ 3: 0], r/w, 0x0 */ - uint32_t cs2_enable_pre : 1; /* [ 4], r/w, 0x0 */ - uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ - uint32_t cs2_weight_pre : 5; /* [12: 8], r/w, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t cs2_gain_pre : 9; /* [24:16], r/w, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } CS2; - - /* 0x3b8 reserved */ - uint8_t RESERVED0x3b8[68]; - - /* 0x3FC : DUMMY_CTRL */ - union { - struct { - uint32_t reg_bl444to422_en_w : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DUMMY_CTRL; - - /* 0x400 reserved */ - uint8_t RESERVED0x400[1280]; - - /* 0x900 : WDR_0 */ - union { - struct { - uint32_t wdr_en_pre : 1; /* [ 0], r/w, 0x0 */ - uint32_t blwdr_buf_idx_r : 1; /* [ 1], r, 0x0 */ - uint32_t reserved_2_3 : 2; /* [ 3: 2], rsvd, 0x0 */ - uint32_t blwdr_w_cnt_r : 5; /* [ 8: 4], r, 0x0 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t wdr_cs_gain_pre : 13; /* [28:16], r/w, 0x0 */ - uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_0; - - /* 0x904 : WDR_CS_0 */ - union { - struct { - uint32_t wdr_cs_en_pre : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_7 : 7; /* [ 7: 1], rsvd, 0x0 */ - uint32_t wdr_cs_weight_pre : 5; /* [12: 8], r/w, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t wdr_cs_grey_th_pre : 8; /* [23:16], r/w, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CS_0; - - /* 0x908 : WDR_HIST_1 */ - union { - struct { - uint32_t hist_roi0_en_pre : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_7 : 7; /* [ 7: 1], rsvd, 0x0 */ - uint32_t hist_roi0_weight_pre : 4; /* [11: 8], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t hist_roi1_en_pre : 1; /* [ 16], r/w, 0x0 */ - uint32_t reserved_17_23 : 7; /* [23:17], rsvd, 0x0 */ - uint32_t hist_roi1_weight_pre : 4; /* [27:24], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_HIST_1; - - /* 0x90C : WDR_HIST_2 */ - union { - struct { - uint32_t hist_roi2_en_pre : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_7 : 7; /* [ 7: 1], rsvd, 0x0 */ - uint32_t hist_roi2_weight_pre : 4; /* [11: 8], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t hist_roi3_en_pre : 1; /* [ 16], r/w, 0x0 */ - uint32_t reserved_17_23 : 7; /* [23:17], rsvd, 0x0 */ - uint32_t hist_roi3_weight_pre : 4; /* [27:24], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_HIST_2; - - /* 0x910 : WDR_HIST_3 */ - union { - struct { - uint32_t hist_roi4_en_pre : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_7 : 7; /* [ 7: 1], rsvd, 0x0 */ - uint32_t hist_roi4_weight_pre : 4; /* [11: 8], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t hist_roi5_en_pre : 1; /* [ 16], r/w, 0x0 */ - uint32_t reserved_17_23 : 7; /* [23:17], rsvd, 0x0 */ - uint32_t hist_roi5_weight_pre : 4; /* [27:24], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_HIST_3; - - /* 0x914 : WDR_HIST_4 */ - union { - struct { - uint32_t hist_roi6_en_pre : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_7 : 7; /* [ 7: 1], rsvd, 0x0 */ - uint32_t hist_roi6_weight_pre : 4; /* [11: 8], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t hist_roi7_en_pre : 1; /* [ 16], r/w, 0x0 */ - uint32_t reserved_17_23 : 7; /* [23:17], rsvd, 0x0 */ - uint32_t hist_roi7_weight_pre : 4; /* [27:24], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_HIST_4; - - /* 0x918 : WDR_HIST_5 */ - union { - struct { - uint32_t hist_x0_max_pre : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t hist_x0_min_pre : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_HIST_5; - - /* 0x91C : WDR_HIST_6 */ - union { - struct { - uint32_t hist_y0_max_pre : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t hist_y0_min_pre : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_HIST_6; - - /* 0x920 : WDR_HIST_7 */ - union { - struct { - uint32_t hist_x1_max_pre : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t hist_x1_min_pre : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_HIST_7; - - /* 0x924 : WDR_HIST_8 */ - union { - struct { - uint32_t hist_y1_max_pre : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t hist_y1_min_pre : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_HIST_8; - - /* 0x928 : WDR_HIST_9 */ - union { - struct { - uint32_t hist_x2_max_pre : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t hist_x2_min_pre : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_HIST_9; - - /* 0x92C : WDR_HIST_10 */ - union { - struct { - uint32_t hist_y2_max_pre : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t hist_y2_min_pre : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_HIST_10; - - /* 0x930 : WDR_HIST_11 */ - union { - struct { - uint32_t hist_x3_max_pre : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t hist_x3_min_pre : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_HIST_11; - - /* 0x934 : WDR_HIST_12 */ - union { - struct { - uint32_t hist_y3_max_pre : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t hist_y3_min_pre : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_HIST_12; - - /* 0x938 : WDR_HIST_13 */ - union { - struct { - uint32_t hist_x4_max_pre : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t hist_x4_min_pre : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_HIST_13; - - /* 0x93C : WDR_HIST_14 */ - union { - struct { - uint32_t hist_y4_max_pre : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t hist_y4_min_pre : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_HIST_14; - - /* 0x940 : WDR_HIST_15 */ - union { - struct { - uint32_t hist_x5_max_pre : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t hist_x5_min_pre : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_HIST_15; - - /* 0x944 : WDR_HIST_16 */ - union { - struct { - uint32_t hist_y5_max_pre : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t hist_y5_min_pre : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_HIST_16; - - /* 0x948 : WDR_HIST_17 */ - union { - struct { - uint32_t hist_x6_max_pre : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t hist_x6_min_pre : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_HIST_17; - - /* 0x94C : WDR_HIST_18 */ - union { - struct { - uint32_t hist_y6_max_pre : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t hist_y6_min_pre : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_HIST_18; - - /* 0x950 : WDR_HIST_19 */ - union { - struct { - uint32_t hist_x7_max_pre : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t hist_x7_min_pre : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_HIST_19; - - /* 0x954 : WDR_HIST_20 */ - union { - struct { - uint32_t hist_y7_max_pre : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t hist_y7_min_pre : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_HIST_20; - - /* 0x958 : REG_HIST0_64 */ - union { - struct { - uint32_t hist0_64_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_64; - - /* 0x95C : REG_HIST1_64 */ - union { - struct { - uint32_t hist1_64_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_64; - - /* 0x960 reserved */ - uint8_t RESERVED0x960[160]; - - /* 0xA00 : REG_HIST0_0 */ - union { - struct { - uint32_t hist0_0_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_0; - - /* 0xA04 : REG_HIST0_1 */ - union { - struct { - uint32_t hist0_1_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_1; - - /* 0xA08 : REG_HIST0_2 */ - union { - struct { - uint32_t hist0_2_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_2; - - /* 0xA0C : REG_HIST0_3 */ - union { - struct { - uint32_t hist0_3_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_3; - - /* 0xA10 : REG_HIST0_4 */ - union { - struct { - uint32_t hist0_4_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_4; - - /* 0xA14 : REG_HIST0_5 */ - union { - struct { - uint32_t hist0_5_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_5; - - /* 0xA18 : REG_HIST0_6 */ - union { - struct { - uint32_t hist0_6_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_6; - - /* 0xA1C : REG_HIST0_7 */ - union { - struct { - uint32_t hist0_7_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_7; - - /* 0xA20 : REG_HIST0_8 */ - union { - struct { - uint32_t hist0_8_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_8; - - /* 0xA24 : REG_HIST0_9 */ - union { - struct { - uint32_t hist0_9_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_9; - - /* 0xA28 : REG_HIST0_10 */ - union { - struct { - uint32_t hist0_10_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_10; - - /* 0xA2C : REG_HIST0_11 */ - union { - struct { - uint32_t hist0_11_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_11; - - /* 0xA30 : REG_HIST0_12 */ - union { - struct { - uint32_t hist0_12_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_12; - - /* 0xA34 : REG_HIST0_13 */ - union { - struct { - uint32_t hist0_13_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_13; - - /* 0xA38 : REG_HIST0_14 */ - union { - struct { - uint32_t hist0_14_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_14; - - /* 0xA3C : REG_HIST0_15 */ - union { - struct { - uint32_t hist0_15_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_15; - - /* 0xA40 : REG_HIST0_16 */ - union { - struct { - uint32_t hist0_16_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_16; - - /* 0xA44 : REG_HIST0_17 */ - union { - struct { - uint32_t hist0_17_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_17; - - /* 0xA48 : REG_HIST0_18 */ - union { - struct { - uint32_t hist0_18_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_18; - - /* 0xA4C : REG_HIST0_19 */ - union { - struct { - uint32_t hist0_19_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_19; - - /* 0xA50 : REG_HIST0_20 */ - union { - struct { - uint32_t hist0_20_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_20; - - /* 0xA54 : REG_HIST0_21 */ - union { - struct { - uint32_t hist0_21_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_21; - - /* 0xA58 : REG_HIST0_22 */ - union { - struct { - uint32_t hist0_22_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_22; - - /* 0xA5C : REG_HIST0_23 */ - union { - struct { - uint32_t hist0_23_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_23; - - /* 0xA60 : REG_HIST0_24 */ - union { - struct { - uint32_t hist0_24_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_24; - - /* 0xA64 : REG_HIST0_25 */ - union { - struct { - uint32_t hist0_25_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_25; - - /* 0xA68 : REG_HIST0_26 */ - union { - struct { - uint32_t hist0_26_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_26; - - /* 0xA6C : REG_HIST0_27 */ - union { - struct { - uint32_t hist0_27_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_27; - - /* 0xA70 : REG_HIST0_28 */ - union { - struct { - uint32_t hist0_28_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_28; - - /* 0xA74 : REG_HIST0_29 */ - union { - struct { - uint32_t hist0_29_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_29; - - /* 0xA78 : REG_HIST0_30 */ - union { - struct { - uint32_t hist0_30_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_30; - - /* 0xA7C : REG_HIST0_31 */ - union { - struct { - uint32_t hist0_31_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_31; - - /* 0xA80 : REG_HIST0_32 */ - union { - struct { - uint32_t hist0_32_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_32; - - /* 0xA84 : REG_HIST0_33 */ - union { - struct { - uint32_t hist0_33_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_33; - - /* 0xA88 : REG_HIST0_34 */ - union { - struct { - uint32_t hist0_34_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_34; - - /* 0xA8C : REG_HIST0_35 */ - union { - struct { - uint32_t hist0_35_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_35; - - /* 0xA90 : REG_HIST0_36 */ - union { - struct { - uint32_t hist0_36_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_36; - - /* 0xA94 : REG_HIST0_37 */ - union { - struct { - uint32_t hist0_37_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_37; - - /* 0xA98 : REG_HIST0_38 */ - union { - struct { - uint32_t hist0_38_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_38; - - /* 0xA9C : REG_HIST0_39 */ - union { - struct { - uint32_t hist0_39_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_39; - - /* 0xAA0 : REG_HIST0_40 */ - union { - struct { - uint32_t hist0_40_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_40; - - /* 0xAA4 : REG_HIST0_41 */ - union { - struct { - uint32_t hist0_41_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_41; - - /* 0xAA8 : REG_HIST0_42 */ - union { - struct { - uint32_t hist0_42_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_42; - - /* 0xAAC : REG_HIST0_43 */ - union { - struct { - uint32_t hist0_43_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_43; - - /* 0xAB0 : REG_HIST0_44 */ - union { - struct { - uint32_t hist0_44_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_44; - - /* 0xAB4 : REG_HIST0_45 */ - union { - struct { - uint32_t hist0_45_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_45; - - /* 0xAB8 : REG_HIST0_46 */ - union { - struct { - uint32_t hist0_46_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_46; - - /* 0xABC : REG_HIST0_47 */ - union { - struct { - uint32_t hist0_47_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_47; - - /* 0xAC0 : REG_HIST0_48 */ - union { - struct { - uint32_t hist0_48_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_48; - - /* 0xAC4 : REG_HIST0_49 */ - union { - struct { - uint32_t hist0_49_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_49; - - /* 0xAC8 : REG_HIST0_50 */ - union { - struct { - uint32_t hist0_50_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_50; - - /* 0xACC : REG_HIST0_51 */ - union { - struct { - uint32_t hist0_51_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_51; - - /* 0xAD0 : REG_HIST0_52 */ - union { - struct { - uint32_t hist0_52_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_52; - - /* 0xAD4 : REG_HIST0_53 */ - union { - struct { - uint32_t hist0_53_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_53; - - /* 0xAD8 : REG_HIST0_54 */ - union { - struct { - uint32_t hist0_54_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_54; - - /* 0xADC : REG_HIST0_55 */ - union { - struct { - uint32_t hist0_55_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_55; - - /* 0xAE0 : REG_HIST0_56 */ - union { - struct { - uint32_t hist0_56_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_56; - - /* 0xAE4 : REG_HIST0_57 */ - union { - struct { - uint32_t hist0_57_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_57; - - /* 0xAE8 : REG_HIST0_58 */ - union { - struct { - uint32_t hist0_58_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_58; - - /* 0xAEC : REG_HIST0_59 */ - union { - struct { - uint32_t hist0_59_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_59; - - /* 0xAF0 : REG_HIST0_60 */ - union { - struct { - uint32_t hist0_60_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_60; - - /* 0xAF4 : REG_HIST0_61 */ - union { - struct { - uint32_t hist0_61_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_61; - - /* 0xAF8 : REG_HIST0_62 */ - union { - struct { - uint32_t hist0_62_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_62; - - /* 0xAFC : REG_HIST0_63 */ - union { - struct { - uint32_t hist0_63_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_63; - - /* 0xB00 : REG_HIST1_0 */ - union { - struct { - uint32_t hist1_0_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_0; - - /* 0xB04 : REG_HIST1_1 */ - union { - struct { - uint32_t hist1_1_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_1; - - /* 0xB08 : REG_HIST1_2 */ - union { - struct { - uint32_t hist1_2_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_2; - - /* 0xB0C : REG_HIST1_3 */ - union { - struct { - uint32_t hist1_3_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_3; - - /* 0xB10 : REG_HIST1_4 */ - union { - struct { - uint32_t hist1_4_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_4; - - /* 0xB14 : REG_HIST1_5 */ - union { - struct { - uint32_t hist1_5_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_5; - - /* 0xB18 : REG_HIST1_6 */ - union { - struct { - uint32_t hist1_6_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_6; - - /* 0xB1C : REG_HIST1_7 */ - union { - struct { - uint32_t hist1_7_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_7; - - /* 0xB20 : REG_HIST1_8 */ - union { - struct { - uint32_t hist1_8_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_8; - - /* 0xB24 : REG_HIST1_9 */ - union { - struct { - uint32_t hist1_9_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_9; - - /* 0xB28 : REG_HIST1_10 */ - union { - struct { - uint32_t hist1_10_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_10; - - /* 0xB2C : REG_HIST1_11 */ - union { - struct { - uint32_t hist1_11_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_11; - - /* 0xB30 : REG_HIST1_12 */ - union { - struct { - uint32_t hist1_12_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_12; - - /* 0xB34 : REG_HIST1_13 */ - union { - struct { - uint32_t hist1_13_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_13; - - /* 0xB38 : REG_HIST1_14 */ - union { - struct { - uint32_t hist1_14_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_14; - - /* 0xB3C : REG_HIST1_15 */ - union { - struct { - uint32_t hist1_15_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_15; - - /* 0xB40 : REG_HIST1_16 */ - union { - struct { - uint32_t hist1_16_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_16; - - /* 0xB44 : REG_HIST1_17 */ - union { - struct { - uint32_t hist1_17_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_17; - - /* 0xB48 : REG_HIST1_18 */ - union { - struct { - uint32_t hist1_18_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_18; - - /* 0xB4C : REG_HIST1_19 */ - union { - struct { - uint32_t hist1_19_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_19; - - /* 0xB50 : REG_HIST1_20 */ - union { - struct { - uint32_t hist1_20_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_20; - - /* 0xB54 : REG_HIST1_21 */ - union { - struct { - uint32_t hist1_21_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_21; - - /* 0xB58 : REG_HIST1_22 */ - union { - struct { - uint32_t hist1_22_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_22; - - /* 0xB5C : REG_HIST1_23 */ - union { - struct { - uint32_t hist1_23_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_23; - - /* 0xB60 : REG_HIST1_24 */ - union { - struct { - uint32_t hist1_24_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_24; - - /* 0xB64 : REG_HIST1_25 */ - union { - struct { - uint32_t hist1_25_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_25; - - /* 0xB68 : REG_HIST1_26 */ - union { - struct { - uint32_t hist1_26_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_26; - - /* 0xB6C : REG_HIST1_27 */ - union { - struct { - uint32_t hist1_27_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_27; - - /* 0xB70 : REG_HIST1_28 */ - union { - struct { - uint32_t hist1_28_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_28; - - /* 0xB74 : REG_HIST1_29 */ - union { - struct { - uint32_t hist1_29_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_29; - - /* 0xB78 : REG_HIST1_30 */ - union { - struct { - uint32_t hist1_30_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_30; - - /* 0xB7C : REG_HIST1_31 */ - union { - struct { - uint32_t hist1_31_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_31; - - /* 0xB80 : REG_HIST1_32 */ - union { - struct { - uint32_t hist1_32_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_32; - - /* 0xB84 : REG_HIST1_33 */ - union { - struct { - uint32_t hist1_33_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_33; - - /* 0xB88 : REG_HIST1_34 */ - union { - struct { - uint32_t hist1_34_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_34; - - /* 0xB8C : REG_HIST1_35 */ - union { - struct { - uint32_t hist1_35_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_35; - - /* 0xB90 : REG_HIST1_36 */ - union { - struct { - uint32_t hist1_36_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_36; - - /* 0xB94 : REG_HIST1_37 */ - union { - struct { - uint32_t hist1_37_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_37; - - /* 0xB98 : REG_HIST1_38 */ - union { - struct { - uint32_t hist1_38_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_38; - - /* 0xB9C : REG_HIST1_39 */ - union { - struct { - uint32_t hist1_39_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_39; - - /* 0xBA0 : REG_HIST1_40 */ - union { - struct { - uint32_t hist1_40_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_40; - - /* 0xBA4 : REG_HIST1_41 */ - union { - struct { - uint32_t hist1_41_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_41; - - /* 0xBA8 : REG_HIST1_42 */ - union { - struct { - uint32_t hist1_42_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_42; - - /* 0xBAC : REG_HIST1_43 */ - union { - struct { - uint32_t hist1_43_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_43; - - /* 0xBB0 : REG_HIST1_44 */ - union { - struct { - uint32_t hist1_44_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_44; - - /* 0xBB4 : REG_HIST1_45 */ - union { - struct { - uint32_t hist1_45_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_45; - - /* 0xBB8 : REG_HIST1_46 */ - union { - struct { - uint32_t hist1_46_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_46; - - /* 0xBBC : REG_HIST1_47 */ - union { - struct { - uint32_t hist1_47_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_47; - - /* 0xBC0 : REG_HIST1_48 */ - union { - struct { - uint32_t hist1_48_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_48; - - /* 0xBC4 : REG_HIST1_49 */ - union { - struct { - uint32_t hist1_49_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_49; - - /* 0xBC8 : REG_HIST1_50 */ - union { - struct { - uint32_t hist1_50_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_50; - - /* 0xBCC : REG_HIST1_51 */ - union { - struct { - uint32_t hist1_51_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_51; - - /* 0xBD0 : REG_HIST1_52 */ - union { - struct { - uint32_t hist1_52_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_52; - - /* 0xBD4 : REG_HIST1_53 */ - union { - struct { - uint32_t hist1_53_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_53; - - /* 0xBD8 : REG_HIST1_54 */ - union { - struct { - uint32_t hist1_54_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_54; - - /* 0xBDC : REG_HIST1_55 */ - union { - struct { - uint32_t hist1_55_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_55; - - /* 0xBE0 : REG_HIST1_56 */ - union { - struct { - uint32_t hist1_56_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_56; - - /* 0xBE4 : REG_HIST1_57 */ - union { - struct { - uint32_t hist1_57_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_57; - - /* 0xBE8 : REG_HIST1_58 */ - union { - struct { - uint32_t hist1_58_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_58; - - /* 0xBEC : REG_HIST1_59 */ - union { - struct { - uint32_t hist1_59_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_59; - - /* 0xBF0 : REG_HIST1_60 */ - union { - struct { - uint32_t hist1_60_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_60; - - /* 0xBF4 : REG_HIST1_61 */ - union { - struct { - uint32_t hist1_61_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_61; - - /* 0xBF8 : REG_HIST1_62 */ - union { - struct { - uint32_t hist1_62_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_62; - - /* 0xBFC : REG_HIST1_63 */ - union { - struct { - uint32_t hist1_63_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_63; - - /* 0xC00 : WDR_CURVE_1 */ - union { - struct { - uint32_t curve_0_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_1_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_1; - - /* 0xC04 : WDR_CURVE_2 */ - union { - struct { - uint32_t curve_2_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_3_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_2; - - /* 0xC08 : WDR_CURVE_3 */ - union { - struct { - uint32_t curve_4_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_5_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_3; - - /* 0xC0C : WDR_CURVE_4 */ - union { - struct { - uint32_t curve_6_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_7_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_4; - - /* 0xC10 : WDR_CURVE_5 */ - union { - struct { - uint32_t curve_8_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_9_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_5; - - /* 0xC14 : WDR_CURVE_6 */ - union { - struct { - uint32_t curve_10_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_11_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_6; - - /* 0xC18 : WDR_CURVE_7 */ - union { - struct { - uint32_t curve_12_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_13_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_7; - - /* 0xC1C : WDR_CURVE_8 */ - union { - struct { - uint32_t curve_14_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_15_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_8; - - /* 0xC20 : WDR_CURVE_9 */ - union { - struct { - uint32_t curve_16_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_17_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_9; - - /* 0xC24 : WDR_CURVE_10 */ - union { - struct { - uint32_t curve_18_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_19_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_10; - - /* 0xC28 : WDR_CURVE_11 */ - union { - struct { - uint32_t curve_20_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_21_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_11; - - /* 0xC2C : WDR_CURVE_12 */ - union { - struct { - uint32_t curve_22_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_23_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_12; - - /* 0xC30 : WDR_CURVE_13 */ - union { - struct { - uint32_t curve_24_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_25_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_13; - - /* 0xC34 : WDR_CURVE_14 */ - union { - struct { - uint32_t curve_26_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_27_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_14; - - /* 0xC38 : WDR_CURVE_15 */ - union { - struct { - uint32_t curve_28_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_29_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_15; - - /* 0xC3C : WDR_CURVE_16 */ - union { - struct { - uint32_t curve_30_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_31_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_16; - - /* 0xC40 : WDR_CURVE_17 */ - union { - struct { - uint32_t curve_32_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_33_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_17; - - /* 0xC44 : WDR_CURVE_18 */ - union { - struct { - uint32_t curve_34_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_35_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_18; - - /* 0xC48 : WDR_CURVE_19 */ - union { - struct { - uint32_t curve_36_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_37_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_19; - - /* 0xC4C : WDR_CURVE_20 */ - union { - struct { - uint32_t curve_38_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_39_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_20; - - /* 0xC50 : WDR_CURVE_21 */ - union { - struct { - uint32_t curve_40_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_41_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_21; - - /* 0xC54 : WDR_CURVE_22 */ - union { - struct { - uint32_t curve_42_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_43_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_22; - - /* 0xC58 : WDR_CURVE_23 */ - union { - struct { - uint32_t curve_44_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_45_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_23; - - /* 0xC5C : WDR_CURVE_24 */ - union { - struct { - uint32_t curve_46_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_47_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_24; - - /* 0xC60 : WDR_CURVE_25 */ - union { - struct { - uint32_t curve_48_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_49_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_25; - - /* 0xC64 : WDR_CURVE_26 */ - union { - struct { - uint32_t curve_50_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_51_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_26; - - /* 0xC68 : WDR_CURVE_27 */ - union { - struct { - uint32_t curve_52_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_53_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_27; - - /* 0xC6C : WDR_CURVE_28 */ - union { - struct { - uint32_t curve_54_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_55_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_28; - - /* 0xC70 : WDR_CURVE_29 */ - union { - struct { - uint32_t curve_56_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_57_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_29; - - /* 0xC74 : WDR_CURVE_30 */ - union { - struct { - uint32_t curve_58_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_59_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_30; - - /* 0xC78 : WDR_CURVE_31 */ - union { - struct { - uint32_t curve_60_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_61_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_31; - - /* 0xC7C : WDR_CURVE_32 */ - union { - struct { - uint32_t curve_62_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_63_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_32; - - /* 0xC80 : WDR_CURVE_33 */ - union { - struct { - uint32_t curve_en_pre : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_7 : 7; /* [ 7: 1], rsvd, 0x0 */ - uint32_t curve_weight_pre : 5; /* [12: 8], r/w, 0x0 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_33; - - /* 0xC84 : WDR_ENH_1 */ - union { - struct { - uint32_t enh_en_pre : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_7 : 7; /* [ 7: 1], rsvd, 0x0 */ - uint32_t enh_weight_pre : 5; /* [12: 8], r/w, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t enh_y_offset_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_ENH_1; - - /* 0xC88 : WDR_ENH_2 */ - union { - struct { - uint32_t enh_c_gain_pre : 15; /* [14: 0], r/w, 0x0 */ - uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */ - uint32_t enh_y_gain_pre : 15; /* [30:16], r/w, 0x0 */ - uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_ENH_2; - - /* 0xc8c reserved */ - uint8_t RESERVED0xc8c[116]; - - /* 0xD00 : BL_GAMMA_TABLE_1 */ - union { - struct { - uint32_t gamma_table0_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table1_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_1; - - /* 0xD04 : BL_GAMMA_TABLE_2 */ - union { - struct { - uint32_t gamma_table2_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table3_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_2; - - /* 0xD08 : BL_GAMMA_TABLE_3 */ - union { - struct { - uint32_t gamma_table4_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table5_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_3; - - /* 0xD0C : BL_GAMMA_TABLE_4 */ - union { - struct { - uint32_t gamma_table6_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table7_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_4; - - /* 0xD10 : BL_GAMMA_TABLE_5 */ - union { - struct { - uint32_t gamma_table8_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table9_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_5; - - /* 0xD14 : BL_GAMMA_TABLE_6 */ - union { - struct { - uint32_t gamma_table10_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table11_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_6; - - /* 0xD18 : BL_GAMMA_TABLE_7 */ - union { - struct { - uint32_t gamma_table12_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table13_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_7; - - /* 0xD1C : BL_GAMMA_TABLE_8 */ - union { - struct { - uint32_t gamma_table14_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table15_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_8; - - /* 0xD20 : BL_GAMMA_TABLE_9 */ - union { - struct { - uint32_t gamma_table16_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table17_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_9; - - /* 0xD24 : BL_GAMMA_TABLE_10 */ - union { - struct { - uint32_t gamma_table18_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table19_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_10; - - /* 0xD28 : BL_GAMMA_TABLE_11 */ - union { - struct { - uint32_t gamma_table20_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table21_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_11; - - /* 0xD2C : BL_GAMMA_TABLE_12 */ - union { - struct { - uint32_t gamma_table22_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table23_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_12; - - /* 0xD30 : BL_GAMMA_TABLE_13 */ - union { - struct { - uint32_t gamma_table24_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table25_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_13; - - /* 0xD34 : BL_GAMMA_TABLE_14 */ - union { - struct { - uint32_t gamma_table26_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table27_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_14; - - /* 0xD38 : BL_GAMMA_TABLE_15 */ - union { - struct { - uint32_t gamma_table28_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table29_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_15; - - /* 0xD3C : BL_GAMMA_TABLE_16 */ - union { - struct { - uint32_t gamma_table30_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table31_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_16; - - /* 0xD40 : BL_GAMMA_TABLE_17 */ - union { - struct { - uint32_t gamma_table32_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table33_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_17; - - /* 0xD44 : BL_GAMMA_TABLE_18 */ - union { - struct { - uint32_t gamma_table34_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table35_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_18; - - /* 0xD48 : BL_GAMMA_TABLE_19 */ - union { - struct { - uint32_t gamma_table36_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table37_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_19; - - /* 0xD4C : BL_GAMMA_TABLE_20 */ - union { - struct { - uint32_t gamma_table38_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table39_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_20; - - /* 0xD50 : BL_GAMMA_TABLE_21 */ - union { - struct { - uint32_t gamma_table40_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table41_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_21; - - /* 0xD54 : BL_GAMMA_TABLE_22 */ - union { - struct { - uint32_t gamma_table42_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table43_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_22; - - /* 0xD58 : BL_GAMMA_TABLE_23 */ - union { - struct { - uint32_t gamma_table44_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table45_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_23; - - /* 0xD5C : BL_GAMMA_TABLE_24 */ - union { - struct { - uint32_t gamma_table46_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table47_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_24; - - /* 0xD60 : BL_GAMMA_TABLE_25 */ - union { - struct { - uint32_t gamma_table48_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table49_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_25; - - /* 0xD64 : BL_GAMMA_TABLE_26 */ - union { - struct { - uint32_t gamma_table50_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table51_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_26; - - /* 0xD68 : BL_GAMMA_TABLE_27 */ - union { - struct { - uint32_t gamma_table52_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table53_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_27; - - /* 0xD6C : BL_GAMMA_TABLE_28 */ - union { - struct { - uint32_t gamma_table54_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table55_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_28; - - /* 0xD70 : BL_GAMMA_TABLE_29 */ - union { - struct { - uint32_t gamma_table56_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table57_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_29; - - /* 0xD74 : BL_GAMMA_TABLE_30 */ - union { - struct { - uint32_t gamma_table58_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table59_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_30; - - /* 0xD78 : BL_GAMMA_TABLE_31 */ - union { - struct { - uint32_t gamma_table60_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table61_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_31; - - /* 0xD7C : BL_GAMMA_TABLE_32 */ - union { - struct { - uint32_t gamma_table62_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table63_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_32; - - /* 0xD80 : BL_GAMMA_TABLE_33 */ - union { - struct { - uint32_t gamma_table64_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table65_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_33; - - /* 0xD84 : BL_GAMMA_TABLE_34 */ - union { - struct { - uint32_t gamma_table66_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table67_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_34; - - /* 0xD88 : BL_GAMMA_TABLE_35 */ - union { - struct { - uint32_t gamma_table68_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table69_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_35; - - /* 0xD8C : BL_GAMMA_TABLE_36 */ - union { - struct { - uint32_t gamma_table70_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table71_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_36; - - /* 0xD90 : BL_GAMMA_TABLE_37 */ - union { - struct { - uint32_t gamma_table72_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table73_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_37; - - /* 0xD94 : BL_GAMMA_TABLE_38 */ - union { - struct { - uint32_t gamma_table74_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table75_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_38; - - /* 0xD98 : BL_GAMMA_TABLE_39 */ - union { - struct { - uint32_t gamma_table76_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table77_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_39; - - /* 0xD9C : BL_GAMMA_TABLE_40 */ - union { - struct { - uint32_t gamma_table78_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table79_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_40; - - /* 0xDA0 : BL_GAMMA_TABLE_41 */ - union { - struct { - uint32_t gamma_table80_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table81_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_41; - - /* 0xDA4 : BL_GAMMA_TABLE_42 */ - union { - struct { - uint32_t gamma_table82_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table83_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_42; - - /* 0xDA8 : BL_GAMMA_TABLE_43 */ - union { - struct { - uint32_t gamma_table84_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table85_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_43; - - /* 0xDAC : BL_GAMMA_TABLE_44 */ - union { - struct { - uint32_t gamma_table86_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table87_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_44; - - /* 0xDB0 : BL_GAMMA_TABLE_45 */ - union { - struct { - uint32_t gamma_table88_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table89_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_45; - - /* 0xDB4 : BL_GAMMA_TABLE_46 */ - union { - struct { - uint32_t gamma_table90_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table91_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_46; - - /* 0xDB8 : BL_GAMMA_TABLE_47 */ - union { - struct { - uint32_t gamma_table92_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table93_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_47; - - /* 0xDBC : BL_GAMMA_TABLE_48 */ - union { - struct { - uint32_t gamma_table94_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table95_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_48; - - /* 0xDC0 : BL_GAMMA_TABLE_49 */ - union { - struct { - uint32_t gamma_table96_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table97_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_49; - - /* 0xDC4 : BL_GAMMA_TABLE_50 */ - union { - struct { - uint32_t gamma_table98_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table99_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_50; - - /* 0xDC8 : BL_GAMMA_TABLE_51 */ - union { - struct { - uint32_t gamma_table100_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table101_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_51; - - /* 0xDCC : BL_GAMMA_TABLE_52 */ - union { - struct { - uint32_t gamma_table102_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table103_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_52; - - /* 0xDD0 : BL_GAMMA_TABLE_53 */ - union { - struct { - uint32_t gamma_table104_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table105_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_53; - - /* 0xDD4 : BL_GAMMA_TABLE_54 */ - union { - struct { - uint32_t gamma_table106_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table107_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_54; - - /* 0xDD8 : BL_GAMMA_TABLE_55 */ - union { - struct { - uint32_t gamma_table108_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table109_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_55; - - /* 0xDDC : BL_GAMMA_TABLE_56 */ - union { - struct { - uint32_t gamma_table110_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table111_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_56; - - /* 0xDE0 : BL_GAMMA_TABLE_57 */ - union { - struct { - uint32_t gamma_table112_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table113_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_57; - - /* 0xDE4 : BL_GAMMA_TABLE_58 */ - union { - struct { - uint32_t gamma_table114_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table115_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_58; - - /* 0xDE8 : BL_GAMMA_TABLE_59 */ - union { - struct { - uint32_t gamma_table116_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table117_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_59; - - /* 0xDEC : BL_GAMMA_TABLE_60 */ - union { - struct { - uint32_t gamma_table118_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table119_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_60; - - /* 0xDF0 : BL_GAMMA_TABLE_61 */ - union { - struct { - uint32_t gamma_table120_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table121_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_61; - - /* 0xDF4 : BL_GAMMA_TABLE_62 */ - union { - struct { - uint32_t gamma_table122_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table123_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_62; - - /* 0xDF8 : BL_GAMMA_TABLE_63 */ - union { - struct { - uint32_t gamma_table124_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table125_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_63; - - /* 0xDFC : BL_GAMMA_TABLE_64 */ - union { - struct { - uint32_t gamma_table126_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table127_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_64; - - /* 0xE00 : BL_GAMMA_TABLE_65 */ - union { - struct { - uint32_t gamma_table128_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table129_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_65; - - /* 0xE04 : BL_GAMMA_TABLE_66 */ - union { - struct { - uint32_t gamma_table130_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table131_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_66; - - /* 0xE08 : BL_GAMMA_TABLE_67 */ - union { - struct { - uint32_t gamma_table132_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table133_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_67; - - /* 0xE0C : BL_GAMMA_TABLE_68 */ - union { - struct { - uint32_t gamma_table134_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table135_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_68; - - /* 0xE10 : BL_GAMMA_TABLE_69 */ - union { - struct { - uint32_t gamma_table136_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table137_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_69; - - /* 0xE14 : BL_GAMMA_TABLE_70 */ - union { - struct { - uint32_t gamma_table138_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table139_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_70; - - /* 0xE18 : BL_GAMMA_TABLE_71 */ - union { - struct { - uint32_t gamma_table140_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table141_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_71; - - /* 0xE1C : BL_GAMMA_TABLE_72 */ - union { - struct { - uint32_t gamma_table142_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table143_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_72; - - /* 0xE20 : BL_GAMMA_TABLE_73 */ - union { - struct { - uint32_t gamma_table144_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table145_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_73; - - /* 0xE24 : BL_GAMMA_TABLE_74 */ - union { - struct { - uint32_t gamma_table146_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table147_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_74; - - /* 0xE28 : BL_GAMMA_TABLE_75 */ - union { - struct { - uint32_t gamma_table148_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table149_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_75; - - /* 0xE2C : BL_GAMMA_TABLE_76 */ - union { - struct { - uint32_t gamma_table150_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table151_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_76; - - /* 0xE30 : BL_GAMMA_TABLE_77 */ - union { - struct { - uint32_t gamma_table152_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table153_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_77; - - /* 0xE34 : BL_GAMMA_TABLE_78 */ - union { - struct { - uint32_t gamma_table154_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table155_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_78; - - /* 0xE38 : BL_GAMMA_TABLE_79 */ - union { - struct { - uint32_t gamma_table156_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table157_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_79; - - /* 0xE3C : BL_GAMMA_TABLE_80 */ - union { - struct { - uint32_t gamma_table158_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table159_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_80; - - /* 0xE40 : BL_GAMMA_TABLE_81 */ - union { - struct { - uint32_t gamma_table160_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table161_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_81; - - /* 0xE44 : BL_GAMMA_TABLE_82 */ - union { - struct { - uint32_t gamma_table162_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table163_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_82; - - /* 0xE48 : BL_GAMMA_TABLE_83 */ - union { - struct { - uint32_t gamma_table164_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table165_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_83; - - /* 0xE4C : BL_GAMMA_TABLE_84 */ - union { - struct { - uint32_t gamma_table166_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table167_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_84; - - /* 0xE50 : BL_GAMMA_TABLE_85 */ - union { - struct { - uint32_t gamma_table168_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table169_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_85; - - /* 0xE54 : BL_GAMMA_TABLE_86 */ - union { - struct { - uint32_t gamma_table170_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table171_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_86; - - /* 0xE58 : BL_GAMMA_TABLE_87 */ - union { - struct { - uint32_t gamma_table172_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table173_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_87; - - /* 0xE5C : BL_GAMMA_TABLE_88 */ - union { - struct { - uint32_t gamma_table174_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table175_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_88; - - /* 0xE60 : BL_GAMMA_TABLE_89 */ - union { - struct { - uint32_t gamma_table176_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table177_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_89; - - /* 0xE64 : BL_GAMMA_TABLE_90 */ - union { - struct { - uint32_t gamma_table178_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table179_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_90; - - /* 0xE68 : BL_GAMMA_TABLE_91 */ - union { - struct { - uint32_t gamma_table180_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table181_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_91; - - /* 0xE6C : BL_GAMMA_TABLE_92 */ - union { - struct { - uint32_t gamma_table182_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table183_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_92; - - /* 0xE70 : BL_GAMMA_TABLE_93 */ - union { - struct { - uint32_t gamma_table184_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table185_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_93; - - /* 0xE74 : BL_GAMMA_TABLE_94 */ - union { - struct { - uint32_t gamma_table186_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table187_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_94; - - /* 0xE78 : BL_GAMMA_TABLE_95 */ - union { - struct { - uint32_t gamma_table188_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table189_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_95; - - /* 0xE7C : BL_GAMMA_TABLE_96 */ - union { - struct { - uint32_t gamma_table190_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table191_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_96; - - /* 0xE80 : BL_GAMMA_TABLE_97 */ - union { - struct { - uint32_t gamma_table192_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table193_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_97; - - /* 0xE84 : BL_GAMMA_TABLE_98 */ - union { - struct { - uint32_t gamma_table194_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table195_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_98; - - /* 0xE88 : BL_GAMMA_TABLE_99 */ - union { - struct { - uint32_t gamma_table196_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table197_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_99; - - /* 0xE8C : BL_GAMMA_TABLE_100 */ - union { - struct { - uint32_t gamma_table198_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table199_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_100; - - /* 0xE90 : BL_GAMMA_TABLE_101 */ - union { - struct { - uint32_t gamma_table200_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table201_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_101; - - /* 0xE94 : BL_GAMMA_TABLE_102 */ - union { - struct { - uint32_t gamma_table202_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table203_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_102; - - /* 0xE98 : BL_GAMMA_TABLE_103 */ - union { - struct { - uint32_t gamma_table204_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table205_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_103; - - /* 0xE9C : BL_GAMMA_TABLE_104 */ - union { - struct { - uint32_t gamma_table206_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table207_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_104; - - /* 0xEA0 : BL_GAMMA_TABLE_105 */ - union { - struct { - uint32_t gamma_table208_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table209_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_105; - - /* 0xEA4 : BL_GAMMA_TABLE_106 */ - union { - struct { - uint32_t gamma_table210_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table211_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_106; - - /* 0xEA8 : BL_GAMMA_TABLE_107 */ - union { - struct { - uint32_t gamma_table212_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table213_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_107; - - /* 0xEAC : BL_GAMMA_TABLE_108 */ - union { - struct { - uint32_t gamma_table214_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table215_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_108; - - /* 0xEB0 : BL_GAMMA_TABLE_109 */ - union { - struct { - uint32_t gamma_table216_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table217_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_109; - - /* 0xEB4 : BL_GAMMA_TABLE_110 */ - union { - struct { - uint32_t gamma_table218_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table219_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_110; - - /* 0xEB8 : BL_GAMMA_TABLE_111 */ - union { - struct { - uint32_t gamma_table220_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table221_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_111; - - /* 0xEBC : BL_GAMMA_TABLE_112 */ - union { - struct { - uint32_t gamma_table222_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table223_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_112; - - /* 0xEC0 : BL_GAMMA_TABLE_113 */ - union { - struct { - uint32_t gamma_table224_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table225_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_113; - - /* 0xEC4 : BL_GAMMA_TABLE_114 */ - union { - struct { - uint32_t gamma_table226_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table227_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_114; - - /* 0xEC8 : BL_GAMMA_TABLE_115 */ - union { - struct { - uint32_t gamma_table228_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table229_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_115; - - /* 0xECC : BL_GAMMA_TABLE_116 */ - union { - struct { - uint32_t gamma_table230_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table231_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_116; - - /* 0xED0 : BL_GAMMA_TABLE_117 */ - union { - struct { - uint32_t gamma_table232_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table233_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_117; - - /* 0xED4 : BL_GAMMA_TABLE_118 */ - union { - struct { - uint32_t gamma_table234_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table235_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_118; - - /* 0xED8 : BL_GAMMA_TABLE_119 */ - union { - struct { - uint32_t gamma_table236_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table237_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_119; - - /* 0xEDC : BL_GAMMA_TABLE_120 */ - union { - struct { - uint32_t gamma_table238_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table239_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_120; - - /* 0xEE0 : BL_GAMMA_TABLE_121 */ - union { - struct { - uint32_t gamma_table240_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table241_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_121; - - /* 0xEE4 : BL_GAMMA_TABLE_122 */ - union { - struct { - uint32_t gamma_table242_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table243_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_122; - - /* 0xEE8 : BL_GAMMA_TABLE_123 */ - union { - struct { - uint32_t gamma_table244_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table245_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_123; - - /* 0xEEC : BL_GAMMA_TABLE_124 */ - union { - struct { - uint32_t gamma_table246_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table247_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_124; - - /* 0xEF0 : BL_GAMMA_TABLE_125 */ - union { - struct { - uint32_t gamma_table248_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table249_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_125; - - /* 0xEF4 : BL_GAMMA_TABLE_126 */ - union { - struct { - uint32_t gamma_table250_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table251_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_126; - - /* 0xEF8 : BL_GAMMA_TABLE_127 */ - union { - struct { - uint32_t gamma_table252_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table253_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_127; - - /* 0xEFC : BL_GAMMA_TABLE_128 */ - union { - struct { - uint32_t gamma_table254_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table255_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_128; - - /* 0xF00 : CC_OFFSET_0 */ - union { - struct { - uint32_t cc_pre_offset0_pre : 13; /* [12: 0], r/w, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t cc_pre_offset1_pre : 13; /* [28:16], r/w, 0x0 */ - uint32_t reserved_29_30 : 2; /* [30:29], rsvd, 0x0 */ - uint32_t cc_enable_pre : 1; /* [ 31], r/w, 0x1 */ - } BF; - uint32_t WORD; - } CC_OFFSET_0; - - /* 0xF04 : CC_OFFSET_1 */ - union { - struct { - uint32_t cc_pre_offset2_pre : 13; /* [12: 0], r/w, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t cc_post_offset2_pre : 13; /* [28:16], r/w, 0x0 */ - uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } CC_OFFSET_1; - - /* 0xF08 : CC_OFFSET_2 */ - union { - struct { - uint32_t cc_post_offset0_pre : 13; /* [12: 0], r/w, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t cc_post_offset1_pre : 13; /* [28:16], r/w, 0x0 */ - uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } CC_OFFSET_2; - - /* 0xF0C : CC_MATRIX_0 */ - union { - struct { - uint32_t cc_matrix00_pre : 12; /* [11: 0], r/w, 0x200 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t cc_matrix01_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } CC_MATRIX_0; - - /* 0xF10 : CC_MATRIX_1 */ - union { - struct { - uint32_t cc_matrix10_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t cc_matrix02_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } CC_MATRIX_1; - - /* 0xF14 : CC_MATRIX_2 */ - union { - struct { - uint32_t cc_matrix11_pre : 12; /* [11: 0], r/w, 0x200 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t cc_matrix12_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } CC_MATRIX_2; - - /* 0xF18 : CC_MATRIX_3 */ - union { - struct { - uint32_t cc_matrix20_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t cc_matrix21_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } CC_MATRIX_3; - - /* 0xF1C : CC_CE_MATRIX */ - union { - struct { - uint32_t cc_matrix22_pre : 12; /* [11: 0], r/w, 0x200 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t ce_matrix02_pre : 12; /* [27:16], r/w, 0x3a */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } CC_CE_MATRIX; - - /* 0xF20 : CE_MATRIX_0 */ - union { - struct { - uint32_t ce_matrix00_pre : 12; /* [11: 0], r/w, 0x99 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t ce_matrix01_pre : 12; /* [27:16], r/w, 0x12d */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } CE_MATRIX_0; - - /* 0xF24 : CE_MATRIX_1 */ - union { - struct { - uint32_t ce_matrix10_pre : 12; /* [11: 0], r/w, 0xfa9 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t ce_matrix11_pre : 12; /* [27:16], r/w, 0xf57 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } CE_MATRIX_1; - - /* 0xF28 : CE_MATRIX_2 */ - union { - struct { - uint32_t ce_matrix20_pre : 12; /* [11: 0], r/w, 0x100 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t ce_matrix12_pre : 12; /* [27:16], r/w, 0x100 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } CE_MATRIX_2; - - /* 0xF2C : CE_MATRIX_3 */ - union { - struct { - uint32_t ce_matrix21_pre : 12; /* [11: 0], r/w, 0xf29 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t ce_matrix22_pre : 12; /* [27:16], r/w, 0xfd7 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } CE_MATRIX_3; - - /* 0xF30 : CE_OFFSET_0 */ - union { - struct { - uint32_t ce_pre_offset0_pre : 13; /* [12: 0], r/w, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t ce_pre_offset1_pre : 13; /* [28:16], r/w, 0x0 */ - uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } CE_OFFSET_0; - - /* 0xF34 : CE_OFFSET_1 */ - union { - struct { - uint32_t ce_pre_offset2_pre : 13; /* [12: 0], r/w, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t ce_post_offset2_pre : 13; /* [28:16], r/w, 0x800 */ - uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } CE_OFFSET_1; - - /* 0xF38 : CE_OFFSET_2 */ - union { - struct { - uint32_t ce_post_offset0_pre : 13; /* [12: 0], r/w, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t ce_post_offset1_pre : 13; /* [28:16], r/w, 0x800 */ - uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } CE_OFFSET_2; -}; - -typedef volatile struct dsp2_blback_reg dsp2_blback_reg_t; - -#endif /* __DSP2_BLBACK_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_front_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_front_reg.h deleted file mode 100644 index f3f6383110..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_front_reg.h +++ /dev/null @@ -1,346 +0,0 @@ -/** - ****************************************************************************** - * @file dsp2_front_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __DSP2_FRONT_REG_H__ -#define __DSP2_FRONT_REG_H__ - -#include "bl808.h" - -/* 0x110 : pattern_mode */ -#define DSP2_FRONT_PATTERN_MODE_OFFSET (0x110) -#define DSP2_FRONT_PATTERN_MODE_W DSP2_FRONT_PATTERN_MODE_W -#define DSP2_FRONT_PATTERN_MODE_W_POS (0U) -#define DSP2_FRONT_PATTERN_MODE_W_LEN (3U) -#define DSP2_FRONT_PATTERN_MODE_W_MSK (((1U << DSP2_FRONT_PATTERN_MODE_W_LEN) - 1) << DSP2_FRONT_PATTERN_MODE_W_POS) -#define DSP2_FRONT_PATTERN_MODE_W_UMSK (~(((1U << DSP2_FRONT_PATTERN_MODE_W_LEN) - 1) << DSP2_FRONT_PATTERN_MODE_W_POS)) -#define DSP2_FRONT_PID_INV_RGB_PRE DSP2_FRONT_PID_INV_RGB_PRE -#define DSP2_FRONT_PID_INV_RGB_PRE_POS (8U) -#define DSP2_FRONT_PID_INV_RGB_PRE_LEN (1U) -#define DSP2_FRONT_PID_INV_RGB_PRE_MSK (((1U << DSP2_FRONT_PID_INV_RGB_PRE_LEN) - 1) << DSP2_FRONT_PID_INV_RGB_PRE_POS) -#define DSP2_FRONT_PID_INV_RGB_PRE_UMSK (~(((1U << DSP2_FRONT_PID_INV_RGB_PRE_LEN) - 1) << DSP2_FRONT_PID_INV_RGB_PRE_POS)) -#define DSP2_FRONT_LID_INV_RGB_PRE DSP2_FRONT_LID_INV_RGB_PRE -#define DSP2_FRONT_LID_INV_RGB_PRE_POS (9U) -#define DSP2_FRONT_LID_INV_RGB_PRE_LEN (1U) -#define DSP2_FRONT_LID_INV_RGB_PRE_MSK (((1U << DSP2_FRONT_LID_INV_RGB_PRE_LEN) - 1) << DSP2_FRONT_LID_INV_RGB_PRE_POS) -#define DSP2_FRONT_LID_INV_RGB_PRE_UMSK (~(((1U << DSP2_FRONT_LID_INV_RGB_PRE_LEN) - 1) << DSP2_FRONT_LID_INV_RGB_PRE_POS)) -#define DSP2_FRONT_REG_BL_LPID_SEL_W DSP2_FRONT_REG_BL_LPID_SEL_W -#define DSP2_FRONT_REG_BL_LPID_SEL_W_POS (10U) -#define DSP2_FRONT_REG_BL_LPID_SEL_W_LEN (1U) -#define DSP2_FRONT_REG_BL_LPID_SEL_W_MSK (((1U << DSP2_FRONT_REG_BL_LPID_SEL_W_LEN) - 1) << DSP2_FRONT_REG_BL_LPID_SEL_W_POS) -#define DSP2_FRONT_REG_BL_LPID_SEL_W_UMSK (~(((1U << DSP2_FRONT_REG_BL_LPID_SEL_W_LEN) - 1) << DSP2_FRONT_REG_BL_LPID_SEL_W_POS)) -#define DSP2_FRONT_ACT_HSIZE_W DSP2_FRONT_ACT_HSIZE_W -#define DSP2_FRONT_ACT_HSIZE_W_POS (16U) -#define DSP2_FRONT_ACT_HSIZE_W_LEN (16U) -#define DSP2_FRONT_ACT_HSIZE_W_MSK (((1U << DSP2_FRONT_ACT_HSIZE_W_LEN) - 1) << DSP2_FRONT_ACT_HSIZE_W_POS) -#define DSP2_FRONT_ACT_HSIZE_W_UMSK (~(((1U << DSP2_FRONT_ACT_HSIZE_W_LEN) - 1) << DSP2_FRONT_ACT_HSIZE_W_POS)) - -/* 0x114 : clamp_R_Gr */ -#define DSP2_FRONT_CLAMP_R_GR_OFFSET (0x114) -#define DSP2_FRONT_CLP_R_PRE DSP2_FRONT_CLP_R_PRE -#define DSP2_FRONT_CLP_R_PRE_POS (0U) -#define DSP2_FRONT_CLP_R_PRE_LEN (16U) -#define DSP2_FRONT_CLP_R_PRE_MSK (((1U << DSP2_FRONT_CLP_R_PRE_LEN) - 1) << DSP2_FRONT_CLP_R_PRE_POS) -#define DSP2_FRONT_CLP_R_PRE_UMSK (~(((1U << DSP2_FRONT_CLP_R_PRE_LEN) - 1) << DSP2_FRONT_CLP_R_PRE_POS)) -#define DSP2_FRONT_CLP_GR_PRE DSP2_FRONT_CLP_GR_PRE -#define DSP2_FRONT_CLP_GR_PRE_POS (16U) -#define DSP2_FRONT_CLP_GR_PRE_LEN (16U) -#define DSP2_FRONT_CLP_GR_PRE_MSK (((1U << DSP2_FRONT_CLP_GR_PRE_LEN) - 1) << DSP2_FRONT_CLP_GR_PRE_POS) -#define DSP2_FRONT_CLP_GR_PRE_UMSK (~(((1U << DSP2_FRONT_CLP_GR_PRE_LEN) - 1) << DSP2_FRONT_CLP_GR_PRE_POS)) - -/* 0x118 : clamp_B_Gb */ -#define DSP2_FRONT_CLAMP_B_GB_OFFSET (0x118) -#define DSP2_FRONT_CLP_GB_PRE DSP2_FRONT_CLP_GB_PRE -#define DSP2_FRONT_CLP_GB_PRE_POS (0U) -#define DSP2_FRONT_CLP_GB_PRE_LEN (16U) -#define DSP2_FRONT_CLP_GB_PRE_MSK (((1U << DSP2_FRONT_CLP_GB_PRE_LEN) - 1) << DSP2_FRONT_CLP_GB_PRE_POS) -#define DSP2_FRONT_CLP_GB_PRE_UMSK (~(((1U << DSP2_FRONT_CLP_GB_PRE_LEN) - 1) << DSP2_FRONT_CLP_GB_PRE_POS)) -#define DSP2_FRONT_CLP_B_PRE DSP2_FRONT_CLP_B_PRE -#define DSP2_FRONT_CLP_B_PRE_POS (16U) -#define DSP2_FRONT_CLP_B_PRE_LEN (16U) -#define DSP2_FRONT_CLP_B_PRE_MSK (((1U << DSP2_FRONT_CLP_B_PRE_LEN) - 1) << DSP2_FRONT_CLP_B_PRE_POS) -#define DSP2_FRONT_CLP_B_PRE_UMSK (~(((1U << DSP2_FRONT_CLP_B_PRE_LEN) - 1) << DSP2_FRONT_CLP_B_PRE_POS)) - -/* 0x130 : ob_win */ -#define DSP2_FRONT_OB_WIN_OFFSET (0x130) -#define DSP2_FRONT_OB_WIN_STARTX_W DSP2_FRONT_OB_WIN_STARTX_W -#define DSP2_FRONT_OB_WIN_STARTX_W_POS (0U) -#define DSP2_FRONT_OB_WIN_STARTX_W_LEN (16U) -#define DSP2_FRONT_OB_WIN_STARTX_W_MSK (((1U << DSP2_FRONT_OB_WIN_STARTX_W_LEN) - 1) << DSP2_FRONT_OB_WIN_STARTX_W_POS) -#define DSP2_FRONT_OB_WIN_STARTX_W_UMSK (~(((1U << DSP2_FRONT_OB_WIN_STARTX_W_LEN) - 1) << DSP2_FRONT_OB_WIN_STARTX_W_POS)) -#define DSP2_FRONT_OB_WIN_STARTY_W DSP2_FRONT_OB_WIN_STARTY_W -#define DSP2_FRONT_OB_WIN_STARTY_W_POS (16U) -#define DSP2_FRONT_OB_WIN_STARTY_W_LEN (16U) -#define DSP2_FRONT_OB_WIN_STARTY_W_MSK (((1U << DSP2_FRONT_OB_WIN_STARTY_W_LEN) - 1) << DSP2_FRONT_OB_WIN_STARTY_W_POS) -#define DSP2_FRONT_OB_WIN_STARTY_W_UMSK (~(((1U << DSP2_FRONT_OB_WIN_STARTY_W_LEN) - 1) << DSP2_FRONT_OB_WIN_STARTY_W_POS)) - -/* 0x134 : black_columns_bit */ -#define DSP2_FRONT_BLACK_COLUMNS_BIT_OFFSET (0x134) -#define DSP2_FRONT_BLACK_ROWS_BIT_W DSP2_FRONT_BLACK_ROWS_BIT_W -#define DSP2_FRONT_BLACK_ROWS_BIT_W_POS (0U) -#define DSP2_FRONT_BLACK_ROWS_BIT_W_LEN (4U) -#define DSP2_FRONT_BLACK_ROWS_BIT_W_MSK (((1U << DSP2_FRONT_BLACK_ROWS_BIT_W_LEN) - 1) << DSP2_FRONT_BLACK_ROWS_BIT_W_POS) -#define DSP2_FRONT_BLACK_ROWS_BIT_W_UMSK (~(((1U << DSP2_FRONT_BLACK_ROWS_BIT_W_LEN) - 1) << DSP2_FRONT_BLACK_ROWS_BIT_W_POS)) -#define DSP2_FRONT_BLACK_COLUMNS_BIT_W DSP2_FRONT_BLACK_COLUMNS_BIT_W -#define DSP2_FRONT_BLACK_COLUMNS_BIT_W_POS (4U) -#define DSP2_FRONT_BLACK_COLUMNS_BIT_W_LEN (4U) -#define DSP2_FRONT_BLACK_COLUMNS_BIT_W_MSK (((1U << DSP2_FRONT_BLACK_COLUMNS_BIT_W_LEN) - 1) << DSP2_FRONT_BLACK_COLUMNS_BIT_W_POS) -#define DSP2_FRONT_BLACK_COLUMNS_BIT_W_UMSK (~(((1U << DSP2_FRONT_BLACK_COLUMNS_BIT_W_LEN) - 1) << DSP2_FRONT_BLACK_COLUMNS_BIT_W_POS)) - -/* 0x138 : Ob_R_Gr */ -#define DSP2_FRONT_OB_R_GR_OFFSET (0x138) -#define DSP2_FRONT_OB_R_R DSP2_FRONT_OB_R_R -#define DSP2_FRONT_OB_R_R_POS (0U) -#define DSP2_FRONT_OB_R_R_LEN (16U) -#define DSP2_FRONT_OB_R_R_MSK (((1U << DSP2_FRONT_OB_R_R_LEN) - 1) << DSP2_FRONT_OB_R_R_POS) -#define DSP2_FRONT_OB_R_R_UMSK (~(((1U << DSP2_FRONT_OB_R_R_LEN) - 1) << DSP2_FRONT_OB_R_R_POS)) -#define DSP2_FRONT_OB_GR_R DSP2_FRONT_OB_GR_R -#define DSP2_FRONT_OB_GR_R_POS (16U) -#define DSP2_FRONT_OB_GR_R_LEN (16U) -#define DSP2_FRONT_OB_GR_R_MSK (((1U << DSP2_FRONT_OB_GR_R_LEN) - 1) << DSP2_FRONT_OB_GR_R_POS) -#define DSP2_FRONT_OB_GR_R_UMSK (~(((1U << DSP2_FRONT_OB_GR_R_LEN) - 1) << DSP2_FRONT_OB_GR_R_POS)) - -/* 0x13C : Ob_B_Gb */ -#define DSP2_FRONT_OB_B_GB_OFFSET (0x13C) -#define DSP2_FRONT_OB_GB_R DSP2_FRONT_OB_GB_R -#define DSP2_FRONT_OB_GB_R_POS (0U) -#define DSP2_FRONT_OB_GB_R_LEN (16U) -#define DSP2_FRONT_OB_GB_R_MSK (((1U << DSP2_FRONT_OB_GB_R_LEN) - 1) << DSP2_FRONT_OB_GB_R_POS) -#define DSP2_FRONT_OB_GB_R_UMSK (~(((1U << DSP2_FRONT_OB_GB_R_LEN) - 1) << DSP2_FRONT_OB_GB_R_POS)) -#define DSP2_FRONT_OB_B_R DSP2_FRONT_OB_B_R -#define DSP2_FRONT_OB_B_R_POS (16U) -#define DSP2_FRONT_OB_B_R_LEN (16U) -#define DSP2_FRONT_OB_B_R_MSK (((1U << DSP2_FRONT_OB_B_R_LEN) - 1) << DSP2_FRONT_OB_B_R_POS) -#define DSP2_FRONT_OB_B_R_UMSK (~(((1U << DSP2_FRONT_OB_B_R_LEN) - 1) << DSP2_FRONT_OB_B_R_POS)) - -/* 0x150 : gain_R_G */ -#define DSP2_FRONT_GAIN_R_G_OFFSET (0x150) -#define DSP2_FRONT_RGAIN1_PRE DSP2_FRONT_RGAIN1_PRE -#define DSP2_FRONT_RGAIN1_PRE_POS (0U) -#define DSP2_FRONT_RGAIN1_PRE_LEN (11U) -#define DSP2_FRONT_RGAIN1_PRE_MSK (((1U << DSP2_FRONT_RGAIN1_PRE_LEN) - 1) << DSP2_FRONT_RGAIN1_PRE_POS) -#define DSP2_FRONT_RGAIN1_PRE_UMSK (~(((1U << DSP2_FRONT_RGAIN1_PRE_LEN) - 1) << DSP2_FRONT_RGAIN1_PRE_POS)) -#define DSP2_FRONT_GGAIN1_PRE DSP2_FRONT_GGAIN1_PRE -#define DSP2_FRONT_GGAIN1_PRE_POS (16U) -#define DSP2_FRONT_GGAIN1_PRE_LEN (11U) -#define DSP2_FRONT_GGAIN1_PRE_MSK (((1U << DSP2_FRONT_GGAIN1_PRE_LEN) - 1) << DSP2_FRONT_GGAIN1_PRE_POS) -#define DSP2_FRONT_GGAIN1_PRE_UMSK (~(((1U << DSP2_FRONT_GGAIN1_PRE_LEN) - 1) << DSP2_FRONT_GGAIN1_PRE_POS)) - -/* 0x154 : gain_B */ -#define DSP2_FRONT_GAIN_B_OFFSET (0x154) -#define DSP2_FRONT_BGAIN1_PRE DSP2_FRONT_BGAIN1_PRE -#define DSP2_FRONT_BGAIN1_PRE_POS (0U) -#define DSP2_FRONT_BGAIN1_PRE_LEN (11U) -#define DSP2_FRONT_BGAIN1_PRE_MSK (((1U << DSP2_FRONT_BGAIN1_PRE_LEN) - 1) << DSP2_FRONT_BGAIN1_PRE_POS) -#define DSP2_FRONT_BGAIN1_PRE_UMSK (~(((1U << DSP2_FRONT_BGAIN1_PRE_LEN) - 1) << DSP2_FRONT_BGAIN1_PRE_POS)) - -/* 0x1D0 : clp_rgr_gain */ -#define DSP2_FRONT_CLP_RGR_GAIN_OFFSET (0x1D0) -#define DSP2_FRONT_CLP_GR_GAIN_PRE DSP2_FRONT_CLP_GR_GAIN_PRE -#define DSP2_FRONT_CLP_GR_GAIN_PRE_POS (0U) -#define DSP2_FRONT_CLP_GR_GAIN_PRE_LEN (15U) -#define DSP2_FRONT_CLP_GR_GAIN_PRE_MSK (((1U << DSP2_FRONT_CLP_GR_GAIN_PRE_LEN) - 1) << DSP2_FRONT_CLP_GR_GAIN_PRE_POS) -#define DSP2_FRONT_CLP_GR_GAIN_PRE_UMSK (~(((1U << DSP2_FRONT_CLP_GR_GAIN_PRE_LEN) - 1) << DSP2_FRONT_CLP_GR_GAIN_PRE_POS)) -#define DSP2_FRONT_CLP_R_GAIN_PRE DSP2_FRONT_CLP_R_GAIN_PRE -#define DSP2_FRONT_CLP_R_GAIN_PRE_POS (16U) -#define DSP2_FRONT_CLP_R_GAIN_PRE_LEN (15U) -#define DSP2_FRONT_CLP_R_GAIN_PRE_MSK (((1U << DSP2_FRONT_CLP_R_GAIN_PRE_LEN) - 1) << DSP2_FRONT_CLP_R_GAIN_PRE_POS) -#define DSP2_FRONT_CLP_R_GAIN_PRE_UMSK (~(((1U << DSP2_FRONT_CLP_R_GAIN_PRE_LEN) - 1) << DSP2_FRONT_CLP_R_GAIN_PRE_POS)) -#define DSP2_FRONT_CLP_GAIN_EN_PRE DSP2_FRONT_CLP_GAIN_EN_PRE -#define DSP2_FRONT_CLP_GAIN_EN_PRE_POS (31U) -#define DSP2_FRONT_CLP_GAIN_EN_PRE_LEN (1U) -#define DSP2_FRONT_CLP_GAIN_EN_PRE_MSK (((1U << DSP2_FRONT_CLP_GAIN_EN_PRE_LEN) - 1) << DSP2_FRONT_CLP_GAIN_EN_PRE_POS) -#define DSP2_FRONT_CLP_GAIN_EN_PRE_UMSK (~(((1U << DSP2_FRONT_CLP_GAIN_EN_PRE_LEN) - 1) << DSP2_FRONT_CLP_GAIN_EN_PRE_POS)) - -/* 0x1D4 : clp_bgb_gain */ -#define DSP2_FRONT_CLP_BGB_GAIN_OFFSET (0x1D4) -#define DSP2_FRONT_CLP_GB_GAIN_PRE DSP2_FRONT_CLP_GB_GAIN_PRE -#define DSP2_FRONT_CLP_GB_GAIN_PRE_POS (0U) -#define DSP2_FRONT_CLP_GB_GAIN_PRE_LEN (15U) -#define DSP2_FRONT_CLP_GB_GAIN_PRE_MSK (((1U << DSP2_FRONT_CLP_GB_GAIN_PRE_LEN) - 1) << DSP2_FRONT_CLP_GB_GAIN_PRE_POS) -#define DSP2_FRONT_CLP_GB_GAIN_PRE_UMSK (~(((1U << DSP2_FRONT_CLP_GB_GAIN_PRE_LEN) - 1) << DSP2_FRONT_CLP_GB_GAIN_PRE_POS)) -#define DSP2_FRONT_CLP_B_GAIN_PRE DSP2_FRONT_CLP_B_GAIN_PRE -#define DSP2_FRONT_CLP_B_GAIN_PRE_POS (16U) -#define DSP2_FRONT_CLP_B_GAIN_PRE_LEN (15U) -#define DSP2_FRONT_CLP_B_GAIN_PRE_MSK (((1U << DSP2_FRONT_CLP_B_GAIN_PRE_LEN) - 1) << DSP2_FRONT_CLP_B_GAIN_PRE_POS) -#define DSP2_FRONT_CLP_B_GAIN_PRE_UMSK (~(((1U << DSP2_FRONT_CLP_B_GAIN_PRE_LEN) - 1) << DSP2_FRONT_CLP_B_GAIN_PRE_POS)) - -/* 0x1F0 : Image_select */ -#define DSP2_FRONT_IMAGE_SELECT_OFFSET (0x1F0) -#define DSP2_FRONT_IMAGE_SELECT_PRE DSP2_FRONT_IMAGE_SELECT_PRE -#define DSP2_FRONT_IMAGE_SELECT_PRE_POS (0U) -#define DSP2_FRONT_IMAGE_SELECT_PRE_LEN (2U) -#define DSP2_FRONT_IMAGE_SELECT_PRE_MSK (((1U << DSP2_FRONT_IMAGE_SELECT_PRE_LEN) - 1) << DSP2_FRONT_IMAGE_SELECT_PRE_POS) -#define DSP2_FRONT_IMAGE_SELECT_PRE_UMSK (~(((1U << DSP2_FRONT_IMAGE_SELECT_PRE_LEN) - 1) << DSP2_FRONT_IMAGE_SELECT_PRE_POS)) - -struct dsp2_front_reg { - /* 0x0 reserved */ - uint8_t RESERVED0x0[272]; - - /* 0x110 : pattern_mode */ - union { - struct { - uint32_t pattern_mode_w : 3; /* [ 2: 0], r/w, 0x0 */ - uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */ - uint32_t pid_inv_rgb_pre : 1; /* [ 8], r/w, 0x0 */ - uint32_t lid_inv_rgb_pre : 1; /* [ 9], r/w, 0x0 */ - uint32_t reg_bl_lpid_sel_w : 1; /* [ 10], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t act_hsize_w : 16; /* [31:16], r/w, 0x788 */ - } BF; - uint32_t WORD; - } pattern_mode; - - /* 0x114 : clamp_R_Gr */ - union { - struct { - uint32_t clp_R_pre : 16; /* [15: 0], r/w, 0x0 */ - uint32_t clp_Gr_pre : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } clamp_R_Gr; - - /* 0x118 : clamp_B_Gb */ - union { - struct { - uint32_t clp_Gb_pre : 16; /* [15: 0], r/w, 0x0 */ - uint32_t clp_B_pre : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } clamp_B_Gb; - - /* 0x11c reserved */ - uint8_t RESERVED0x11c[20]; - - /* 0x130 : ob_win */ - union { - struct { - uint32_t ob_win_startx_w : 16; /* [15: 0], r/w, 0x0 */ - uint32_t ob_win_starty_w : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ob_win; - - /* 0x134 : black_columns_bit */ - union { - struct { - uint32_t black_rows_bit_w : 4; /* [ 3: 0], r/w, 0x2 */ - uint32_t black_columns_bit_w : 4; /* [ 7: 4], r/w, 0x8 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } black_columns_bit; - - /* 0x138 : Ob_R_Gr */ - union { - struct { - uint32_t Ob_R_r : 16; /* [15: 0], r, 0x0 */ - uint32_t Ob_Gr_r : 16; /* [31:16], r, 0x0 */ - } BF; - uint32_t WORD; - } Ob_R_Gr; - - /* 0x13C : Ob_B_Gb */ - union { - struct { - uint32_t Ob_Gb_r : 16; /* [15: 0], r, 0x0 */ - uint32_t Ob_B_r : 16; /* [31:16], r, 0x0 */ - } BF; - uint32_t WORD; - } Ob_B_Gb; - - /* 0x140 reserved */ - uint8_t RESERVED0x140[16]; - - /* 0x150 : gain_R_G */ - union { - struct { - uint32_t rgain1_pre : 11; /* [10: 0], r/w, 0x80 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t ggain1_pre : 11; /* [26:16], r/w, 0x80 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } gain_R_G; - - /* 0x154 : gain_B */ - union { - struct { - uint32_t bgain1_pre : 11; /* [10: 0], r/w, 0x80 */ - uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } gain_B; - - /* 0x158 reserved */ - uint8_t RESERVED0x158[120]; - - /* 0x1D0 : clp_rgr_gain */ - union { - struct { - uint32_t clp_gr_gain_pre : 15; /* [14: 0], r/w, 0x1000 */ - uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */ - uint32_t clp_r_gain_pre : 15; /* [30:16], r/w, 0x1000 */ - uint32_t clp_gain_en_pre : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } clp_rgr_gain; - - /* 0x1D4 : clp_bgb_gain */ - union { - struct { - uint32_t clp_gb_gain_pre : 15; /* [14: 0], r/w, 0x1000 */ - uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */ - uint32_t clp_b_gain_pre : 15; /* [30:16], r/w, 0x1000 */ - uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } clp_bgb_gain; - - /* 0x1d8 reserved */ - uint8_t RESERVED0x1d8[24]; - - /* 0x1F0 : Image_select */ - union { - struct { - uint32_t Image_Select_pre : 2; /* [ 1: 0], r/w, 0x0 */ - uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } Image_select; -}; - -typedef volatile struct dsp2_front_reg dsp2_front_reg_t; - -#endif /* __DSP2_FRONT_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_gamma_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_gamma_reg.h deleted file mode 100644 index 6b0ffa8ec5..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_gamma_reg.h +++ /dev/null @@ -1,2288 +0,0 @@ -/** - ****************************************************************************** - * @file dsp2_gamma_reg.h - * @version V1.0 - * @date 2021-02-05 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __DSP2_GAMMA_REG_H__ -#define __DSP2_GAMMA_REG_H__ - -#include "bl808.h" - -/* 0x700 : GAMMA_CRUVE_1 */ -#define DSP2_GAMMA_GAMMA_CRUVE_1_OFFSET (0x700) -#define DSP2_GAMMA_C0_PRE DSP2_GAMMA_C0_PRE -#define DSP2_GAMMA_C0_PRE_POS (0U) -#define DSP2_GAMMA_C0_PRE_LEN (8U) -#define DSP2_GAMMA_C0_PRE_MSK (((1U << DSP2_GAMMA_C0_PRE_LEN) - 1) << DSP2_GAMMA_C0_PRE_POS) -#define DSP2_GAMMA_C0_PRE_UMSK (~(((1U << DSP2_GAMMA_C0_PRE_LEN) - 1) << DSP2_GAMMA_C0_PRE_POS)) -#define DSP2_GAMMA_C1_PRE DSP2_GAMMA_C1_PRE -#define DSP2_GAMMA_C1_PRE_POS (8U) -#define DSP2_GAMMA_C1_PRE_LEN (8U) -#define DSP2_GAMMA_C1_PRE_MSK (((1U << DSP2_GAMMA_C1_PRE_LEN) - 1) << DSP2_GAMMA_C1_PRE_POS) -#define DSP2_GAMMA_C1_PRE_UMSK (~(((1U << DSP2_GAMMA_C1_PRE_LEN) - 1) << DSP2_GAMMA_C1_PRE_POS)) -#define DSP2_GAMMA_C2_PRE DSP2_GAMMA_C2_PRE -#define DSP2_GAMMA_C2_PRE_POS (16U) -#define DSP2_GAMMA_C2_PRE_LEN (8U) -#define DSP2_GAMMA_C2_PRE_MSK (((1U << DSP2_GAMMA_C2_PRE_LEN) - 1) << DSP2_GAMMA_C2_PRE_POS) -#define DSP2_GAMMA_C2_PRE_UMSK (~(((1U << DSP2_GAMMA_C2_PRE_LEN) - 1) << DSP2_GAMMA_C2_PRE_POS)) -#define DSP2_GAMMA_C3_PRE DSP2_GAMMA_C3_PRE -#define DSP2_GAMMA_C3_PRE_POS (24U) -#define DSP2_GAMMA_C3_PRE_LEN (8U) -#define DSP2_GAMMA_C3_PRE_MSK (((1U << DSP2_GAMMA_C3_PRE_LEN) - 1) << DSP2_GAMMA_C3_PRE_POS) -#define DSP2_GAMMA_C3_PRE_UMSK (~(((1U << DSP2_GAMMA_C3_PRE_LEN) - 1) << DSP2_GAMMA_C3_PRE_POS)) - -/* 0x704 : GAMMA_CRUVE_2 */ -#define DSP2_GAMMA_GAMMA_CRUVE_2_OFFSET (0x704) -#define DSP2_GAMMA_C4_PRE DSP2_GAMMA_C4_PRE -#define DSP2_GAMMA_C4_PRE_POS (0U) -#define DSP2_GAMMA_C4_PRE_LEN (8U) -#define DSP2_GAMMA_C4_PRE_MSK (((1U << DSP2_GAMMA_C4_PRE_LEN) - 1) << DSP2_GAMMA_C4_PRE_POS) -#define DSP2_GAMMA_C4_PRE_UMSK (~(((1U << DSP2_GAMMA_C4_PRE_LEN) - 1) << DSP2_GAMMA_C4_PRE_POS)) -#define DSP2_GAMMA_C5_PRE DSP2_GAMMA_C5_PRE -#define DSP2_GAMMA_C5_PRE_POS (8U) -#define DSP2_GAMMA_C5_PRE_LEN (8U) -#define DSP2_GAMMA_C5_PRE_MSK (((1U << DSP2_GAMMA_C5_PRE_LEN) - 1) << DSP2_GAMMA_C5_PRE_POS) -#define DSP2_GAMMA_C5_PRE_UMSK (~(((1U << DSP2_GAMMA_C5_PRE_LEN) - 1) << DSP2_GAMMA_C5_PRE_POS)) -#define DSP2_GAMMA_C6_PRE DSP2_GAMMA_C6_PRE -#define DSP2_GAMMA_C6_PRE_POS (16U) -#define DSP2_GAMMA_C6_PRE_LEN (8U) -#define DSP2_GAMMA_C6_PRE_MSK (((1U << DSP2_GAMMA_C6_PRE_LEN) - 1) << DSP2_GAMMA_C6_PRE_POS) -#define DSP2_GAMMA_C6_PRE_UMSK (~(((1U << DSP2_GAMMA_C6_PRE_LEN) - 1) << DSP2_GAMMA_C6_PRE_POS)) -#define DSP2_GAMMA_C7_PRE DSP2_GAMMA_C7_PRE -#define DSP2_GAMMA_C7_PRE_POS (24U) -#define DSP2_GAMMA_C7_PRE_LEN (8U) -#define DSP2_GAMMA_C7_PRE_MSK (((1U << DSP2_GAMMA_C7_PRE_LEN) - 1) << DSP2_GAMMA_C7_PRE_POS) -#define DSP2_GAMMA_C7_PRE_UMSK (~(((1U << DSP2_GAMMA_C7_PRE_LEN) - 1) << DSP2_GAMMA_C7_PRE_POS)) - -/* 0x708 : GAMMA_CRUVE_3 */ -#define DSP2_GAMMA_GAMMA_CRUVE_3_OFFSET (0x708) -#define DSP2_GAMMA_C8_PRE DSP2_GAMMA_C8_PRE -#define DSP2_GAMMA_C8_PRE_POS (0U) -#define DSP2_GAMMA_C8_PRE_LEN (8U) -#define DSP2_GAMMA_C8_PRE_MSK (((1U << DSP2_GAMMA_C8_PRE_LEN) - 1) << DSP2_GAMMA_C8_PRE_POS) -#define DSP2_GAMMA_C8_PRE_UMSK (~(((1U << DSP2_GAMMA_C8_PRE_LEN) - 1) << DSP2_GAMMA_C8_PRE_POS)) -#define DSP2_GAMMA_C9_PRE DSP2_GAMMA_C9_PRE -#define DSP2_GAMMA_C9_PRE_POS (8U) -#define DSP2_GAMMA_C9_PRE_LEN (8U) -#define DSP2_GAMMA_C9_PRE_MSK (((1U << DSP2_GAMMA_C9_PRE_LEN) - 1) << DSP2_GAMMA_C9_PRE_POS) -#define DSP2_GAMMA_C9_PRE_UMSK (~(((1U << DSP2_GAMMA_C9_PRE_LEN) - 1) << DSP2_GAMMA_C9_PRE_POS)) -#define DSP2_GAMMA_C10_PRE DSP2_GAMMA_C10_PRE -#define DSP2_GAMMA_C10_PRE_POS (16U) -#define DSP2_GAMMA_C10_PRE_LEN (8U) -#define DSP2_GAMMA_C10_PRE_MSK (((1U << DSP2_GAMMA_C10_PRE_LEN) - 1) << DSP2_GAMMA_C10_PRE_POS) -#define DSP2_GAMMA_C10_PRE_UMSK (~(((1U << DSP2_GAMMA_C10_PRE_LEN) - 1) << DSP2_GAMMA_C10_PRE_POS)) -#define DSP2_GAMMA_C11_PRE DSP2_GAMMA_C11_PRE -#define DSP2_GAMMA_C11_PRE_POS (24U) -#define DSP2_GAMMA_C11_PRE_LEN (8U) -#define DSP2_GAMMA_C11_PRE_MSK (((1U << DSP2_GAMMA_C11_PRE_LEN) - 1) << DSP2_GAMMA_C11_PRE_POS) -#define DSP2_GAMMA_C11_PRE_UMSK (~(((1U << DSP2_GAMMA_C11_PRE_LEN) - 1) << DSP2_GAMMA_C11_PRE_POS)) - -/* 0x70C : GAMMA_CRUVE_4 */ -#define DSP2_GAMMA_GAMMA_CRUVE_4_OFFSET (0x70C) -#define DSP2_GAMMA_C12_PRE DSP2_GAMMA_C12_PRE -#define DSP2_GAMMA_C12_PRE_POS (0U) -#define DSP2_GAMMA_C12_PRE_LEN (8U) -#define DSP2_GAMMA_C12_PRE_MSK (((1U << DSP2_GAMMA_C12_PRE_LEN) - 1) << DSP2_GAMMA_C12_PRE_POS) -#define DSP2_GAMMA_C12_PRE_UMSK (~(((1U << DSP2_GAMMA_C12_PRE_LEN) - 1) << DSP2_GAMMA_C12_PRE_POS)) -#define DSP2_GAMMA_C13_PRE DSP2_GAMMA_C13_PRE -#define DSP2_GAMMA_C13_PRE_POS (8U) -#define DSP2_GAMMA_C13_PRE_LEN (8U) -#define DSP2_GAMMA_C13_PRE_MSK (((1U << DSP2_GAMMA_C13_PRE_LEN) - 1) << DSP2_GAMMA_C13_PRE_POS) -#define DSP2_GAMMA_C13_PRE_UMSK (~(((1U << DSP2_GAMMA_C13_PRE_LEN) - 1) << DSP2_GAMMA_C13_PRE_POS)) -#define DSP2_GAMMA_C14_PRE DSP2_GAMMA_C14_PRE -#define DSP2_GAMMA_C14_PRE_POS (16U) -#define DSP2_GAMMA_C14_PRE_LEN (8U) -#define DSP2_GAMMA_C14_PRE_MSK (((1U << DSP2_GAMMA_C14_PRE_LEN) - 1) << DSP2_GAMMA_C14_PRE_POS) -#define DSP2_GAMMA_C14_PRE_UMSK (~(((1U << DSP2_GAMMA_C14_PRE_LEN) - 1) << DSP2_GAMMA_C14_PRE_POS)) -#define DSP2_GAMMA_C15_PRE DSP2_GAMMA_C15_PRE -#define DSP2_GAMMA_C15_PRE_POS (24U) -#define DSP2_GAMMA_C15_PRE_LEN (8U) -#define DSP2_GAMMA_C15_PRE_MSK (((1U << DSP2_GAMMA_C15_PRE_LEN) - 1) << DSP2_GAMMA_C15_PRE_POS) -#define DSP2_GAMMA_C15_PRE_UMSK (~(((1U << DSP2_GAMMA_C15_PRE_LEN) - 1) << DSP2_GAMMA_C15_PRE_POS)) - -/* 0x710 : GAMMA_CRUVE_5 */ -#define DSP2_GAMMA_GAMMA_CRUVE_5_OFFSET (0x710) -#define DSP2_GAMMA_C16_PRE DSP2_GAMMA_C16_PRE -#define DSP2_GAMMA_C16_PRE_POS (0U) -#define DSP2_GAMMA_C16_PRE_LEN (8U) -#define DSP2_GAMMA_C16_PRE_MSK (((1U << DSP2_GAMMA_C16_PRE_LEN) - 1) << DSP2_GAMMA_C16_PRE_POS) -#define DSP2_GAMMA_C16_PRE_UMSK (~(((1U << DSP2_GAMMA_C16_PRE_LEN) - 1) << DSP2_GAMMA_C16_PRE_POS)) -#define DSP2_GAMMA_C17_PRE DSP2_GAMMA_C17_PRE -#define DSP2_GAMMA_C17_PRE_POS (8U) -#define DSP2_GAMMA_C17_PRE_LEN (8U) -#define DSP2_GAMMA_C17_PRE_MSK (((1U << DSP2_GAMMA_C17_PRE_LEN) - 1) << DSP2_GAMMA_C17_PRE_POS) -#define DSP2_GAMMA_C17_PRE_UMSK (~(((1U << DSP2_GAMMA_C17_PRE_LEN) - 1) << DSP2_GAMMA_C17_PRE_POS)) -#define DSP2_GAMMA_C18_PRE DSP2_GAMMA_C18_PRE -#define DSP2_GAMMA_C18_PRE_POS (16U) -#define DSP2_GAMMA_C18_PRE_LEN (8U) -#define DSP2_GAMMA_C18_PRE_MSK (((1U << DSP2_GAMMA_C18_PRE_LEN) - 1) << DSP2_GAMMA_C18_PRE_POS) -#define DSP2_GAMMA_C18_PRE_UMSK (~(((1U << DSP2_GAMMA_C18_PRE_LEN) - 1) << DSP2_GAMMA_C18_PRE_POS)) -#define DSP2_GAMMA_C19_PRE DSP2_GAMMA_C19_PRE -#define DSP2_GAMMA_C19_PRE_POS (24U) -#define DSP2_GAMMA_C19_PRE_LEN (8U) -#define DSP2_GAMMA_C19_PRE_MSK (((1U << DSP2_GAMMA_C19_PRE_LEN) - 1) << DSP2_GAMMA_C19_PRE_POS) -#define DSP2_GAMMA_C19_PRE_UMSK (~(((1U << DSP2_GAMMA_C19_PRE_LEN) - 1) << DSP2_GAMMA_C19_PRE_POS)) - -/* 0x714 : GAMMA_CRUVE_6 */ -#define DSP2_GAMMA_GAMMA_CRUVE_6_OFFSET (0x714) -#define DSP2_GAMMA_C20_PRE DSP2_GAMMA_C20_PRE -#define DSP2_GAMMA_C20_PRE_POS (0U) -#define DSP2_GAMMA_C20_PRE_LEN (8U) -#define DSP2_GAMMA_C20_PRE_MSK (((1U << DSP2_GAMMA_C20_PRE_LEN) - 1) << DSP2_GAMMA_C20_PRE_POS) -#define DSP2_GAMMA_C20_PRE_UMSK (~(((1U << DSP2_GAMMA_C20_PRE_LEN) - 1) << DSP2_GAMMA_C20_PRE_POS)) -#define DSP2_GAMMA_C21_PRE DSP2_GAMMA_C21_PRE -#define DSP2_GAMMA_C21_PRE_POS (8U) -#define DSP2_GAMMA_C21_PRE_LEN (8U) -#define DSP2_GAMMA_C21_PRE_MSK (((1U << DSP2_GAMMA_C21_PRE_LEN) - 1) << DSP2_GAMMA_C21_PRE_POS) -#define DSP2_GAMMA_C21_PRE_UMSK (~(((1U << DSP2_GAMMA_C21_PRE_LEN) - 1) << DSP2_GAMMA_C21_PRE_POS)) -#define DSP2_GAMMA_C22_PRE DSP2_GAMMA_C22_PRE -#define DSP2_GAMMA_C22_PRE_POS (16U) -#define DSP2_GAMMA_C22_PRE_LEN (8U) -#define DSP2_GAMMA_C22_PRE_MSK (((1U << DSP2_GAMMA_C22_PRE_LEN) - 1) << DSP2_GAMMA_C22_PRE_POS) -#define DSP2_GAMMA_C22_PRE_UMSK (~(((1U << DSP2_GAMMA_C22_PRE_LEN) - 1) << DSP2_GAMMA_C22_PRE_POS)) -#define DSP2_GAMMA_C23_PRE DSP2_GAMMA_C23_PRE -#define DSP2_GAMMA_C23_PRE_POS (24U) -#define DSP2_GAMMA_C23_PRE_LEN (8U) -#define DSP2_GAMMA_C23_PRE_MSK (((1U << DSP2_GAMMA_C23_PRE_LEN) - 1) << DSP2_GAMMA_C23_PRE_POS) -#define DSP2_GAMMA_C23_PRE_UMSK (~(((1U << DSP2_GAMMA_C23_PRE_LEN) - 1) << DSP2_GAMMA_C23_PRE_POS)) - -/* 0x718 : GAMMA_CRUVE_7 */ -#define DSP2_GAMMA_GAMMA_CRUVE_7_OFFSET (0x718) -#define DSP2_GAMMA_C24_PRE DSP2_GAMMA_C24_PRE -#define DSP2_GAMMA_C24_PRE_POS (0U) -#define DSP2_GAMMA_C24_PRE_LEN (8U) -#define DSP2_GAMMA_C24_PRE_MSK (((1U << DSP2_GAMMA_C24_PRE_LEN) - 1) << DSP2_GAMMA_C24_PRE_POS) -#define DSP2_GAMMA_C24_PRE_UMSK (~(((1U << DSP2_GAMMA_C24_PRE_LEN) - 1) << DSP2_GAMMA_C24_PRE_POS)) -#define DSP2_GAMMA_C25_PRE DSP2_GAMMA_C25_PRE -#define DSP2_GAMMA_C25_PRE_POS (8U) -#define DSP2_GAMMA_C25_PRE_LEN (8U) -#define DSP2_GAMMA_C25_PRE_MSK (((1U << DSP2_GAMMA_C25_PRE_LEN) - 1) << DSP2_GAMMA_C25_PRE_POS) -#define DSP2_GAMMA_C25_PRE_UMSK (~(((1U << DSP2_GAMMA_C25_PRE_LEN) - 1) << DSP2_GAMMA_C25_PRE_POS)) -#define DSP2_GAMMA_C26_PRE DSP2_GAMMA_C26_PRE -#define DSP2_GAMMA_C26_PRE_POS (16U) -#define DSP2_GAMMA_C26_PRE_LEN (8U) -#define DSP2_GAMMA_C26_PRE_MSK (((1U << DSP2_GAMMA_C26_PRE_LEN) - 1) << DSP2_GAMMA_C26_PRE_POS) -#define DSP2_GAMMA_C26_PRE_UMSK (~(((1U << DSP2_GAMMA_C26_PRE_LEN) - 1) << DSP2_GAMMA_C26_PRE_POS)) -#define DSP2_GAMMA_C27_PRE DSP2_GAMMA_C27_PRE -#define DSP2_GAMMA_C27_PRE_POS (24U) -#define DSP2_GAMMA_C27_PRE_LEN (8U) -#define DSP2_GAMMA_C27_PRE_MSK (((1U << DSP2_GAMMA_C27_PRE_LEN) - 1) << DSP2_GAMMA_C27_PRE_POS) -#define DSP2_GAMMA_C27_PRE_UMSK (~(((1U << DSP2_GAMMA_C27_PRE_LEN) - 1) << DSP2_GAMMA_C27_PRE_POS)) - -/* 0x71C : GAMMA_CRUVE_8 */ -#define DSP2_GAMMA_GAMMA_CRUVE_8_OFFSET (0x71C) -#define DSP2_GAMMA_C28_PRE DSP2_GAMMA_C28_PRE -#define DSP2_GAMMA_C28_PRE_POS (0U) -#define DSP2_GAMMA_C28_PRE_LEN (8U) -#define DSP2_GAMMA_C28_PRE_MSK (((1U << DSP2_GAMMA_C28_PRE_LEN) - 1) << DSP2_GAMMA_C28_PRE_POS) -#define DSP2_GAMMA_C28_PRE_UMSK (~(((1U << DSP2_GAMMA_C28_PRE_LEN) - 1) << DSP2_GAMMA_C28_PRE_POS)) -#define DSP2_GAMMA_C29_PRE DSP2_GAMMA_C29_PRE -#define DSP2_GAMMA_C29_PRE_POS (8U) -#define DSP2_GAMMA_C29_PRE_LEN (8U) -#define DSP2_GAMMA_C29_PRE_MSK (((1U << DSP2_GAMMA_C29_PRE_LEN) - 1) << DSP2_GAMMA_C29_PRE_POS) -#define DSP2_GAMMA_C29_PRE_UMSK (~(((1U << DSP2_GAMMA_C29_PRE_LEN) - 1) << DSP2_GAMMA_C29_PRE_POS)) -#define DSP2_GAMMA_C30_PRE DSP2_GAMMA_C30_PRE -#define DSP2_GAMMA_C30_PRE_POS (16U) -#define DSP2_GAMMA_C30_PRE_LEN (8U) -#define DSP2_GAMMA_C30_PRE_MSK (((1U << DSP2_GAMMA_C30_PRE_LEN) - 1) << DSP2_GAMMA_C30_PRE_POS) -#define DSP2_GAMMA_C30_PRE_UMSK (~(((1U << DSP2_GAMMA_C30_PRE_LEN) - 1) << DSP2_GAMMA_C30_PRE_POS)) -#define DSP2_GAMMA_C31_PRE DSP2_GAMMA_C31_PRE -#define DSP2_GAMMA_C31_PRE_POS (24U) -#define DSP2_GAMMA_C31_PRE_LEN (8U) -#define DSP2_GAMMA_C31_PRE_MSK (((1U << DSP2_GAMMA_C31_PRE_LEN) - 1) << DSP2_GAMMA_C31_PRE_POS) -#define DSP2_GAMMA_C31_PRE_UMSK (~(((1U << DSP2_GAMMA_C31_PRE_LEN) - 1) << DSP2_GAMMA_C31_PRE_POS)) - -/* 0x720 : GAMMA_CRUVE_9 */ -#define DSP2_GAMMA_GAMMA_CRUVE_9_OFFSET (0x720) -#define DSP2_GAMMA_C32_PRE DSP2_GAMMA_C32_PRE -#define DSP2_GAMMA_C32_PRE_POS (0U) -#define DSP2_GAMMA_C32_PRE_LEN (8U) -#define DSP2_GAMMA_C32_PRE_MSK (((1U << DSP2_GAMMA_C32_PRE_LEN) - 1) << DSP2_GAMMA_C32_PRE_POS) -#define DSP2_GAMMA_C32_PRE_UMSK (~(((1U << DSP2_GAMMA_C32_PRE_LEN) - 1) << DSP2_GAMMA_C32_PRE_POS)) -#define DSP2_GAMMA_C33_PRE DSP2_GAMMA_C33_PRE -#define DSP2_GAMMA_C33_PRE_POS (8U) -#define DSP2_GAMMA_C33_PRE_LEN (8U) -#define DSP2_GAMMA_C33_PRE_MSK (((1U << DSP2_GAMMA_C33_PRE_LEN) - 1) << DSP2_GAMMA_C33_PRE_POS) -#define DSP2_GAMMA_C33_PRE_UMSK (~(((1U << DSP2_GAMMA_C33_PRE_LEN) - 1) << DSP2_GAMMA_C33_PRE_POS)) -#define DSP2_GAMMA_C34_PRE DSP2_GAMMA_C34_PRE -#define DSP2_GAMMA_C34_PRE_POS (16U) -#define DSP2_GAMMA_C34_PRE_LEN (8U) -#define DSP2_GAMMA_C34_PRE_MSK (((1U << DSP2_GAMMA_C34_PRE_LEN) - 1) << DSP2_GAMMA_C34_PRE_POS) -#define DSP2_GAMMA_C34_PRE_UMSK (~(((1U << DSP2_GAMMA_C34_PRE_LEN) - 1) << DSP2_GAMMA_C34_PRE_POS)) -#define DSP2_GAMMA_C35_PRE DSP2_GAMMA_C35_PRE -#define DSP2_GAMMA_C35_PRE_POS (24U) -#define DSP2_GAMMA_C35_PRE_LEN (8U) -#define DSP2_GAMMA_C35_PRE_MSK (((1U << DSP2_GAMMA_C35_PRE_LEN) - 1) << DSP2_GAMMA_C35_PRE_POS) -#define DSP2_GAMMA_C35_PRE_UMSK (~(((1U << DSP2_GAMMA_C35_PRE_LEN) - 1) << DSP2_GAMMA_C35_PRE_POS)) - -/* 0x724 : GAMMA_CRUVE_10 */ -#define DSP2_GAMMA_GAMMA_CRUVE_10_OFFSET (0x724) -#define DSP2_GAMMA_C36_PRE DSP2_GAMMA_C36_PRE -#define DSP2_GAMMA_C36_PRE_POS (0U) -#define DSP2_GAMMA_C36_PRE_LEN (8U) -#define DSP2_GAMMA_C36_PRE_MSK (((1U << DSP2_GAMMA_C36_PRE_LEN) - 1) << DSP2_GAMMA_C36_PRE_POS) -#define DSP2_GAMMA_C36_PRE_UMSK (~(((1U << DSP2_GAMMA_C36_PRE_LEN) - 1) << DSP2_GAMMA_C36_PRE_POS)) -#define DSP2_GAMMA_C37_PRE DSP2_GAMMA_C37_PRE -#define DSP2_GAMMA_C37_PRE_POS (8U) -#define DSP2_GAMMA_C37_PRE_LEN (8U) -#define DSP2_GAMMA_C37_PRE_MSK (((1U << DSP2_GAMMA_C37_PRE_LEN) - 1) << DSP2_GAMMA_C37_PRE_POS) -#define DSP2_GAMMA_C37_PRE_UMSK (~(((1U << DSP2_GAMMA_C37_PRE_LEN) - 1) << DSP2_GAMMA_C37_PRE_POS)) -#define DSP2_GAMMA_C38_PRE DSP2_GAMMA_C38_PRE -#define DSP2_GAMMA_C38_PRE_POS (16U) -#define DSP2_GAMMA_C38_PRE_LEN (8U) -#define DSP2_GAMMA_C38_PRE_MSK (((1U << DSP2_GAMMA_C38_PRE_LEN) - 1) << DSP2_GAMMA_C38_PRE_POS) -#define DSP2_GAMMA_C38_PRE_UMSK (~(((1U << DSP2_GAMMA_C38_PRE_LEN) - 1) << DSP2_GAMMA_C38_PRE_POS)) -#define DSP2_GAMMA_C39_PRE DSP2_GAMMA_C39_PRE -#define DSP2_GAMMA_C39_PRE_POS (24U) -#define DSP2_GAMMA_C39_PRE_LEN (8U) -#define DSP2_GAMMA_C39_PRE_MSK (((1U << DSP2_GAMMA_C39_PRE_LEN) - 1) << DSP2_GAMMA_C39_PRE_POS) -#define DSP2_GAMMA_C39_PRE_UMSK (~(((1U << DSP2_GAMMA_C39_PRE_LEN) - 1) << DSP2_GAMMA_C39_PRE_POS)) - -/* 0x728 : GAMMA_CRUVE_11 */ -#define DSP2_GAMMA_GAMMA_CRUVE_11_OFFSET (0x728) -#define DSP2_GAMMA_C40_PRE DSP2_GAMMA_C40_PRE -#define DSP2_GAMMA_C40_PRE_POS (0U) -#define DSP2_GAMMA_C40_PRE_LEN (8U) -#define DSP2_GAMMA_C40_PRE_MSK (((1U << DSP2_GAMMA_C40_PRE_LEN) - 1) << DSP2_GAMMA_C40_PRE_POS) -#define DSP2_GAMMA_C40_PRE_UMSK (~(((1U << DSP2_GAMMA_C40_PRE_LEN) - 1) << DSP2_GAMMA_C40_PRE_POS)) -#define DSP2_GAMMA_C41_PRE DSP2_GAMMA_C41_PRE -#define DSP2_GAMMA_C41_PRE_POS (8U) -#define DSP2_GAMMA_C41_PRE_LEN (8U) -#define DSP2_GAMMA_C41_PRE_MSK (((1U << DSP2_GAMMA_C41_PRE_LEN) - 1) << DSP2_GAMMA_C41_PRE_POS) -#define DSP2_GAMMA_C41_PRE_UMSK (~(((1U << DSP2_GAMMA_C41_PRE_LEN) - 1) << DSP2_GAMMA_C41_PRE_POS)) -#define DSP2_GAMMA_C42_PRE DSP2_GAMMA_C42_PRE -#define DSP2_GAMMA_C42_PRE_POS (16U) -#define DSP2_GAMMA_C42_PRE_LEN (8U) -#define DSP2_GAMMA_C42_PRE_MSK (((1U << DSP2_GAMMA_C42_PRE_LEN) - 1) << DSP2_GAMMA_C42_PRE_POS) -#define DSP2_GAMMA_C42_PRE_UMSK (~(((1U << DSP2_GAMMA_C42_PRE_LEN) - 1) << DSP2_GAMMA_C42_PRE_POS)) -#define DSP2_GAMMA_C43_PRE DSP2_GAMMA_C43_PRE -#define DSP2_GAMMA_C43_PRE_POS (24U) -#define DSP2_GAMMA_C43_PRE_LEN (8U) -#define DSP2_GAMMA_C43_PRE_MSK (((1U << DSP2_GAMMA_C43_PRE_LEN) - 1) << DSP2_GAMMA_C43_PRE_POS) -#define DSP2_GAMMA_C43_PRE_UMSK (~(((1U << DSP2_GAMMA_C43_PRE_LEN) - 1) << DSP2_GAMMA_C43_PRE_POS)) - -/* 0x72C : GAMMA_CRUVE_12 */ -#define DSP2_GAMMA_GAMMA_CRUVE_12_OFFSET (0x72C) -#define DSP2_GAMMA_C44_PRE DSP2_GAMMA_C44_PRE -#define DSP2_GAMMA_C44_PRE_POS (0U) -#define DSP2_GAMMA_C44_PRE_LEN (8U) -#define DSP2_GAMMA_C44_PRE_MSK (((1U << DSP2_GAMMA_C44_PRE_LEN) - 1) << DSP2_GAMMA_C44_PRE_POS) -#define DSP2_GAMMA_C44_PRE_UMSK (~(((1U << DSP2_GAMMA_C44_PRE_LEN) - 1) << DSP2_GAMMA_C44_PRE_POS)) -#define DSP2_GAMMA_C45_PRE DSP2_GAMMA_C45_PRE -#define DSP2_GAMMA_C45_PRE_POS (8U) -#define DSP2_GAMMA_C45_PRE_LEN (8U) -#define DSP2_GAMMA_C45_PRE_MSK (((1U << DSP2_GAMMA_C45_PRE_LEN) - 1) << DSP2_GAMMA_C45_PRE_POS) -#define DSP2_GAMMA_C45_PRE_UMSK (~(((1U << DSP2_GAMMA_C45_PRE_LEN) - 1) << DSP2_GAMMA_C45_PRE_POS)) -#define DSP2_GAMMA_C46_PRE DSP2_GAMMA_C46_PRE -#define DSP2_GAMMA_C46_PRE_POS (16U) -#define DSP2_GAMMA_C46_PRE_LEN (8U) -#define DSP2_GAMMA_C46_PRE_MSK (((1U << DSP2_GAMMA_C46_PRE_LEN) - 1) << DSP2_GAMMA_C46_PRE_POS) -#define DSP2_GAMMA_C46_PRE_UMSK (~(((1U << DSP2_GAMMA_C46_PRE_LEN) - 1) << DSP2_GAMMA_C46_PRE_POS)) -#define DSP2_GAMMA_C47_PRE DSP2_GAMMA_C47_PRE -#define DSP2_GAMMA_C47_PRE_POS (24U) -#define DSP2_GAMMA_C47_PRE_LEN (8U) -#define DSP2_GAMMA_C47_PRE_MSK (((1U << DSP2_GAMMA_C47_PRE_LEN) - 1) << DSP2_GAMMA_C47_PRE_POS) -#define DSP2_GAMMA_C47_PRE_UMSK (~(((1U << DSP2_GAMMA_C47_PRE_LEN) - 1) << DSP2_GAMMA_C47_PRE_POS)) - -/* 0x730 : GAMMA_CRUVE_13 */ -#define DSP2_GAMMA_GAMMA_CRUVE_13_OFFSET (0x730) -#define DSP2_GAMMA_C48_PRE DSP2_GAMMA_C48_PRE -#define DSP2_GAMMA_C48_PRE_POS (0U) -#define DSP2_GAMMA_C48_PRE_LEN (8U) -#define DSP2_GAMMA_C48_PRE_MSK (((1U << DSP2_GAMMA_C48_PRE_LEN) - 1) << DSP2_GAMMA_C48_PRE_POS) -#define DSP2_GAMMA_C48_PRE_UMSK (~(((1U << DSP2_GAMMA_C48_PRE_LEN) - 1) << DSP2_GAMMA_C48_PRE_POS)) -#define DSP2_GAMMA_C49_PRE DSP2_GAMMA_C49_PRE -#define DSP2_GAMMA_C49_PRE_POS (8U) -#define DSP2_GAMMA_C49_PRE_LEN (8U) -#define DSP2_GAMMA_C49_PRE_MSK (((1U << DSP2_GAMMA_C49_PRE_LEN) - 1) << DSP2_GAMMA_C49_PRE_POS) -#define DSP2_GAMMA_C49_PRE_UMSK (~(((1U << DSP2_GAMMA_C49_PRE_LEN) - 1) << DSP2_GAMMA_C49_PRE_POS)) -#define DSP2_GAMMA_C50_PRE DSP2_GAMMA_C50_PRE -#define DSP2_GAMMA_C50_PRE_POS (16U) -#define DSP2_GAMMA_C50_PRE_LEN (8U) -#define DSP2_GAMMA_C50_PRE_MSK (((1U << DSP2_GAMMA_C50_PRE_LEN) - 1) << DSP2_GAMMA_C50_PRE_POS) -#define DSP2_GAMMA_C50_PRE_UMSK (~(((1U << DSP2_GAMMA_C50_PRE_LEN) - 1) << DSP2_GAMMA_C50_PRE_POS)) -#define DSP2_GAMMA_C51_PRE DSP2_GAMMA_C51_PRE -#define DSP2_GAMMA_C51_PRE_POS (24U) -#define DSP2_GAMMA_C51_PRE_LEN (8U) -#define DSP2_GAMMA_C51_PRE_MSK (((1U << DSP2_GAMMA_C51_PRE_LEN) - 1) << DSP2_GAMMA_C51_PRE_POS) -#define DSP2_GAMMA_C51_PRE_UMSK (~(((1U << DSP2_GAMMA_C51_PRE_LEN) - 1) << DSP2_GAMMA_C51_PRE_POS)) - -/* 0x734 : GAMMA_CRUVE_14 */ -#define DSP2_GAMMA_GAMMA_CRUVE_14_OFFSET (0x734) -#define DSP2_GAMMA_C52_PRE DSP2_GAMMA_C52_PRE -#define DSP2_GAMMA_C52_PRE_POS (0U) -#define DSP2_GAMMA_C52_PRE_LEN (8U) -#define DSP2_GAMMA_C52_PRE_MSK (((1U << DSP2_GAMMA_C52_PRE_LEN) - 1) << DSP2_GAMMA_C52_PRE_POS) -#define DSP2_GAMMA_C52_PRE_UMSK (~(((1U << DSP2_GAMMA_C52_PRE_LEN) - 1) << DSP2_GAMMA_C52_PRE_POS)) -#define DSP2_GAMMA_C53_PRE DSP2_GAMMA_C53_PRE -#define DSP2_GAMMA_C53_PRE_POS (8U) -#define DSP2_GAMMA_C53_PRE_LEN (8U) -#define DSP2_GAMMA_C53_PRE_MSK (((1U << DSP2_GAMMA_C53_PRE_LEN) - 1) << DSP2_GAMMA_C53_PRE_POS) -#define DSP2_GAMMA_C53_PRE_UMSK (~(((1U << DSP2_GAMMA_C53_PRE_LEN) - 1) << DSP2_GAMMA_C53_PRE_POS)) -#define DSP2_GAMMA_C54_PRE DSP2_GAMMA_C54_PRE -#define DSP2_GAMMA_C54_PRE_POS (16U) -#define DSP2_GAMMA_C54_PRE_LEN (8U) -#define DSP2_GAMMA_C54_PRE_MSK (((1U << DSP2_GAMMA_C54_PRE_LEN) - 1) << DSP2_GAMMA_C54_PRE_POS) -#define DSP2_GAMMA_C54_PRE_UMSK (~(((1U << DSP2_GAMMA_C54_PRE_LEN) - 1) << DSP2_GAMMA_C54_PRE_POS)) -#define DSP2_GAMMA_C55_PRE DSP2_GAMMA_C55_PRE -#define DSP2_GAMMA_C55_PRE_POS (24U) -#define DSP2_GAMMA_C55_PRE_LEN (8U) -#define DSP2_GAMMA_C55_PRE_MSK (((1U << DSP2_GAMMA_C55_PRE_LEN) - 1) << DSP2_GAMMA_C55_PRE_POS) -#define DSP2_GAMMA_C55_PRE_UMSK (~(((1U << DSP2_GAMMA_C55_PRE_LEN) - 1) << DSP2_GAMMA_C55_PRE_POS)) - -/* 0x738 : GAMMA_CRUVE_15 */ -#define DSP2_GAMMA_GAMMA_CRUVE_15_OFFSET (0x738) -#define DSP2_GAMMA_C56_PRE DSP2_GAMMA_C56_PRE -#define DSP2_GAMMA_C56_PRE_POS (0U) -#define DSP2_GAMMA_C56_PRE_LEN (8U) -#define DSP2_GAMMA_C56_PRE_MSK (((1U << DSP2_GAMMA_C56_PRE_LEN) - 1) << DSP2_GAMMA_C56_PRE_POS) -#define DSP2_GAMMA_C56_PRE_UMSK (~(((1U << DSP2_GAMMA_C56_PRE_LEN) - 1) << DSP2_GAMMA_C56_PRE_POS)) -#define DSP2_GAMMA_C57_PRE DSP2_GAMMA_C57_PRE -#define DSP2_GAMMA_C57_PRE_POS (8U) -#define DSP2_GAMMA_C57_PRE_LEN (8U) -#define DSP2_GAMMA_C57_PRE_MSK (((1U << DSP2_GAMMA_C57_PRE_LEN) - 1) << DSP2_GAMMA_C57_PRE_POS) -#define DSP2_GAMMA_C57_PRE_UMSK (~(((1U << DSP2_GAMMA_C57_PRE_LEN) - 1) << DSP2_GAMMA_C57_PRE_POS)) -#define DSP2_GAMMA_C58_PRE DSP2_GAMMA_C58_PRE -#define DSP2_GAMMA_C58_PRE_POS (16U) -#define DSP2_GAMMA_C58_PRE_LEN (8U) -#define DSP2_GAMMA_C58_PRE_MSK (((1U << DSP2_GAMMA_C58_PRE_LEN) - 1) << DSP2_GAMMA_C58_PRE_POS) -#define DSP2_GAMMA_C58_PRE_UMSK (~(((1U << DSP2_GAMMA_C58_PRE_LEN) - 1) << DSP2_GAMMA_C58_PRE_POS)) -#define DSP2_GAMMA_C59_PRE DSP2_GAMMA_C59_PRE -#define DSP2_GAMMA_C59_PRE_POS (24U) -#define DSP2_GAMMA_C59_PRE_LEN (8U) -#define DSP2_GAMMA_C59_PRE_MSK (((1U << DSP2_GAMMA_C59_PRE_LEN) - 1) << DSP2_GAMMA_C59_PRE_POS) -#define DSP2_GAMMA_C59_PRE_UMSK (~(((1U << DSP2_GAMMA_C59_PRE_LEN) - 1) << DSP2_GAMMA_C59_PRE_POS)) - -/* 0x73C : GAMMA_CRUVE_16 */ -#define DSP2_GAMMA_GAMMA_CRUVE_16_OFFSET (0x73C) -#define DSP2_GAMMA_C60_PRE DSP2_GAMMA_C60_PRE -#define DSP2_GAMMA_C60_PRE_POS (0U) -#define DSP2_GAMMA_C60_PRE_LEN (8U) -#define DSP2_GAMMA_C60_PRE_MSK (((1U << DSP2_GAMMA_C60_PRE_LEN) - 1) << DSP2_GAMMA_C60_PRE_POS) -#define DSP2_GAMMA_C60_PRE_UMSK (~(((1U << DSP2_GAMMA_C60_PRE_LEN) - 1) << DSP2_GAMMA_C60_PRE_POS)) -#define DSP2_GAMMA_C61_PRE DSP2_GAMMA_C61_PRE -#define DSP2_GAMMA_C61_PRE_POS (8U) -#define DSP2_GAMMA_C61_PRE_LEN (8U) -#define DSP2_GAMMA_C61_PRE_MSK (((1U << DSP2_GAMMA_C61_PRE_LEN) - 1) << DSP2_GAMMA_C61_PRE_POS) -#define DSP2_GAMMA_C61_PRE_UMSK (~(((1U << DSP2_GAMMA_C61_PRE_LEN) - 1) << DSP2_GAMMA_C61_PRE_POS)) -#define DSP2_GAMMA_C62_PRE DSP2_GAMMA_C62_PRE -#define DSP2_GAMMA_C62_PRE_POS (16U) -#define DSP2_GAMMA_C62_PRE_LEN (8U) -#define DSP2_GAMMA_C62_PRE_MSK (((1U << DSP2_GAMMA_C62_PRE_LEN) - 1) << DSP2_GAMMA_C62_PRE_POS) -#define DSP2_GAMMA_C62_PRE_UMSK (~(((1U << DSP2_GAMMA_C62_PRE_LEN) - 1) << DSP2_GAMMA_C62_PRE_POS)) -#define DSP2_GAMMA_C63_PRE DSP2_GAMMA_C63_PRE -#define DSP2_GAMMA_C63_PRE_POS (24U) -#define DSP2_GAMMA_C63_PRE_LEN (8U) -#define DSP2_GAMMA_C63_PRE_MSK (((1U << DSP2_GAMMA_C63_PRE_LEN) - 1) << DSP2_GAMMA_C63_PRE_POS) -#define DSP2_GAMMA_C63_PRE_UMSK (~(((1U << DSP2_GAMMA_C63_PRE_LEN) - 1) << DSP2_GAMMA_C63_PRE_POS)) - -/* 0x740 : GAMMA_CRUVE_17 */ -#define DSP2_GAMMA_GAMMA_CRUVE_17_OFFSET (0x740) -#define DSP2_GAMMA_C64_PRE DSP2_GAMMA_C64_PRE -#define DSP2_GAMMA_C64_PRE_POS (0U) -#define DSP2_GAMMA_C64_PRE_LEN (8U) -#define DSP2_GAMMA_C64_PRE_MSK (((1U << DSP2_GAMMA_C64_PRE_LEN) - 1) << DSP2_GAMMA_C64_PRE_POS) -#define DSP2_GAMMA_C64_PRE_UMSK (~(((1U << DSP2_GAMMA_C64_PRE_LEN) - 1) << DSP2_GAMMA_C64_PRE_POS)) -#define DSP2_GAMMA_C65_PRE DSP2_GAMMA_C65_PRE -#define DSP2_GAMMA_C65_PRE_POS (8U) -#define DSP2_GAMMA_C65_PRE_LEN (8U) -#define DSP2_GAMMA_C65_PRE_MSK (((1U << DSP2_GAMMA_C65_PRE_LEN) - 1) << DSP2_GAMMA_C65_PRE_POS) -#define DSP2_GAMMA_C65_PRE_UMSK (~(((1U << DSP2_GAMMA_C65_PRE_LEN) - 1) << DSP2_GAMMA_C65_PRE_POS)) -#define DSP2_GAMMA_C66_PRE DSP2_GAMMA_C66_PRE -#define DSP2_GAMMA_C66_PRE_POS (16U) -#define DSP2_GAMMA_C66_PRE_LEN (8U) -#define DSP2_GAMMA_C66_PRE_MSK (((1U << DSP2_GAMMA_C66_PRE_LEN) - 1) << DSP2_GAMMA_C66_PRE_POS) -#define DSP2_GAMMA_C66_PRE_UMSK (~(((1U << DSP2_GAMMA_C66_PRE_LEN) - 1) << DSP2_GAMMA_C66_PRE_POS)) -#define DSP2_GAMMA_C67_PRE DSP2_GAMMA_C67_PRE -#define DSP2_GAMMA_C67_PRE_POS (24U) -#define DSP2_GAMMA_C67_PRE_LEN (8U) -#define DSP2_GAMMA_C67_PRE_MSK (((1U << DSP2_GAMMA_C67_PRE_LEN) - 1) << DSP2_GAMMA_C67_PRE_POS) -#define DSP2_GAMMA_C67_PRE_UMSK (~(((1U << DSP2_GAMMA_C67_PRE_LEN) - 1) << DSP2_GAMMA_C67_PRE_POS)) - -/* 0x744 : GAMMA_CRUVE_18 */ -#define DSP2_GAMMA_GAMMA_CRUVE_18_OFFSET (0x744) -#define DSP2_GAMMA_C68_PRE DSP2_GAMMA_C68_PRE -#define DSP2_GAMMA_C68_PRE_POS (0U) -#define DSP2_GAMMA_C68_PRE_LEN (8U) -#define DSP2_GAMMA_C68_PRE_MSK (((1U << DSP2_GAMMA_C68_PRE_LEN) - 1) << DSP2_GAMMA_C68_PRE_POS) -#define DSP2_GAMMA_C68_PRE_UMSK (~(((1U << DSP2_GAMMA_C68_PRE_LEN) - 1) << DSP2_GAMMA_C68_PRE_POS)) -#define DSP2_GAMMA_C69_PRE DSP2_GAMMA_C69_PRE -#define DSP2_GAMMA_C69_PRE_POS (8U) -#define DSP2_GAMMA_C69_PRE_LEN (8U) -#define DSP2_GAMMA_C69_PRE_MSK (((1U << DSP2_GAMMA_C69_PRE_LEN) - 1) << DSP2_GAMMA_C69_PRE_POS) -#define DSP2_GAMMA_C69_PRE_UMSK (~(((1U << DSP2_GAMMA_C69_PRE_LEN) - 1) << DSP2_GAMMA_C69_PRE_POS)) -#define DSP2_GAMMA_C70_PRE DSP2_GAMMA_C70_PRE -#define DSP2_GAMMA_C70_PRE_POS (16U) -#define DSP2_GAMMA_C70_PRE_LEN (8U) -#define DSP2_GAMMA_C70_PRE_MSK (((1U << DSP2_GAMMA_C70_PRE_LEN) - 1) << DSP2_GAMMA_C70_PRE_POS) -#define DSP2_GAMMA_C70_PRE_UMSK (~(((1U << DSP2_GAMMA_C70_PRE_LEN) - 1) << DSP2_GAMMA_C70_PRE_POS)) -#define DSP2_GAMMA_C71_PRE DSP2_GAMMA_C71_PRE -#define DSP2_GAMMA_C71_PRE_POS (24U) -#define DSP2_GAMMA_C71_PRE_LEN (8U) -#define DSP2_GAMMA_C71_PRE_MSK (((1U << DSP2_GAMMA_C71_PRE_LEN) - 1) << DSP2_GAMMA_C71_PRE_POS) -#define DSP2_GAMMA_C71_PRE_UMSK (~(((1U << DSP2_GAMMA_C71_PRE_LEN) - 1) << DSP2_GAMMA_C71_PRE_POS)) - -/* 0x748 : GAMMA_CRUVE_19 */ -#define DSP2_GAMMA_GAMMA_CRUVE_19_OFFSET (0x748) -#define DSP2_GAMMA_C72_PRE DSP2_GAMMA_C72_PRE -#define DSP2_GAMMA_C72_PRE_POS (0U) -#define DSP2_GAMMA_C72_PRE_LEN (8U) -#define DSP2_GAMMA_C72_PRE_MSK (((1U << DSP2_GAMMA_C72_PRE_LEN) - 1) << DSP2_GAMMA_C72_PRE_POS) -#define DSP2_GAMMA_C72_PRE_UMSK (~(((1U << DSP2_GAMMA_C72_PRE_LEN) - 1) << DSP2_GAMMA_C72_PRE_POS)) -#define DSP2_GAMMA_C73_PRE DSP2_GAMMA_C73_PRE -#define DSP2_GAMMA_C73_PRE_POS (8U) -#define DSP2_GAMMA_C73_PRE_LEN (8U) -#define DSP2_GAMMA_C73_PRE_MSK (((1U << DSP2_GAMMA_C73_PRE_LEN) - 1) << DSP2_GAMMA_C73_PRE_POS) -#define DSP2_GAMMA_C73_PRE_UMSK (~(((1U << DSP2_GAMMA_C73_PRE_LEN) - 1) << DSP2_GAMMA_C73_PRE_POS)) -#define DSP2_GAMMA_C74_PRE DSP2_GAMMA_C74_PRE -#define DSP2_GAMMA_C74_PRE_POS (16U) -#define DSP2_GAMMA_C74_PRE_LEN (8U) -#define DSP2_GAMMA_C74_PRE_MSK (((1U << DSP2_GAMMA_C74_PRE_LEN) - 1) << DSP2_GAMMA_C74_PRE_POS) -#define DSP2_GAMMA_C74_PRE_UMSK (~(((1U << DSP2_GAMMA_C74_PRE_LEN) - 1) << DSP2_GAMMA_C74_PRE_POS)) -#define DSP2_GAMMA_C75_PRE DSP2_GAMMA_C75_PRE -#define DSP2_GAMMA_C75_PRE_POS (24U) -#define DSP2_GAMMA_C75_PRE_LEN (8U) -#define DSP2_GAMMA_C75_PRE_MSK (((1U << DSP2_GAMMA_C75_PRE_LEN) - 1) << DSP2_GAMMA_C75_PRE_POS) -#define DSP2_GAMMA_C75_PRE_UMSK (~(((1U << DSP2_GAMMA_C75_PRE_LEN) - 1) << DSP2_GAMMA_C75_PRE_POS)) - -/* 0x74C : GAMMA_CRUVE_20 */ -#define DSP2_GAMMA_GAMMA_CRUVE_20_OFFSET (0x74C) -#define DSP2_GAMMA_C76_PRE DSP2_GAMMA_C76_PRE -#define DSP2_GAMMA_C76_PRE_POS (0U) -#define DSP2_GAMMA_C76_PRE_LEN (8U) -#define DSP2_GAMMA_C76_PRE_MSK (((1U << DSP2_GAMMA_C76_PRE_LEN) - 1) << DSP2_GAMMA_C76_PRE_POS) -#define DSP2_GAMMA_C76_PRE_UMSK (~(((1U << DSP2_GAMMA_C76_PRE_LEN) - 1) << DSP2_GAMMA_C76_PRE_POS)) -#define DSP2_GAMMA_C77_PRE DSP2_GAMMA_C77_PRE -#define DSP2_GAMMA_C77_PRE_POS (8U) -#define DSP2_GAMMA_C77_PRE_LEN (8U) -#define DSP2_GAMMA_C77_PRE_MSK (((1U << DSP2_GAMMA_C77_PRE_LEN) - 1) << DSP2_GAMMA_C77_PRE_POS) -#define DSP2_GAMMA_C77_PRE_UMSK (~(((1U << DSP2_GAMMA_C77_PRE_LEN) - 1) << DSP2_GAMMA_C77_PRE_POS)) -#define DSP2_GAMMA_C78_PRE DSP2_GAMMA_C78_PRE -#define DSP2_GAMMA_C78_PRE_POS (16U) -#define DSP2_GAMMA_C78_PRE_LEN (8U) -#define DSP2_GAMMA_C78_PRE_MSK (((1U << DSP2_GAMMA_C78_PRE_LEN) - 1) << DSP2_GAMMA_C78_PRE_POS) -#define DSP2_GAMMA_C78_PRE_UMSK (~(((1U << DSP2_GAMMA_C78_PRE_LEN) - 1) << DSP2_GAMMA_C78_PRE_POS)) -#define DSP2_GAMMA_C79_PRE DSP2_GAMMA_C79_PRE -#define DSP2_GAMMA_C79_PRE_POS (24U) -#define DSP2_GAMMA_C79_PRE_LEN (8U) -#define DSP2_GAMMA_C79_PRE_MSK (((1U << DSP2_GAMMA_C79_PRE_LEN) - 1) << DSP2_GAMMA_C79_PRE_POS) -#define DSP2_GAMMA_C79_PRE_UMSK (~(((1U << DSP2_GAMMA_C79_PRE_LEN) - 1) << DSP2_GAMMA_C79_PRE_POS)) - -/* 0x750 : GAMMA_CRUVE_21 */ -#define DSP2_GAMMA_GAMMA_CRUVE_21_OFFSET (0x750) -#define DSP2_GAMMA_C80_PRE DSP2_GAMMA_C80_PRE -#define DSP2_GAMMA_C80_PRE_POS (0U) -#define DSP2_GAMMA_C80_PRE_LEN (8U) -#define DSP2_GAMMA_C80_PRE_MSK (((1U << DSP2_GAMMA_C80_PRE_LEN) - 1) << DSP2_GAMMA_C80_PRE_POS) -#define DSP2_GAMMA_C80_PRE_UMSK (~(((1U << DSP2_GAMMA_C80_PRE_LEN) - 1) << DSP2_GAMMA_C80_PRE_POS)) -#define DSP2_GAMMA_C81_PRE DSP2_GAMMA_C81_PRE -#define DSP2_GAMMA_C81_PRE_POS (8U) -#define DSP2_GAMMA_C81_PRE_LEN (8U) -#define DSP2_GAMMA_C81_PRE_MSK (((1U << DSP2_GAMMA_C81_PRE_LEN) - 1) << DSP2_GAMMA_C81_PRE_POS) -#define DSP2_GAMMA_C81_PRE_UMSK (~(((1U << DSP2_GAMMA_C81_PRE_LEN) - 1) << DSP2_GAMMA_C81_PRE_POS)) -#define DSP2_GAMMA_C82_PRE DSP2_GAMMA_C82_PRE -#define DSP2_GAMMA_C82_PRE_POS (16U) -#define DSP2_GAMMA_C82_PRE_LEN (8U) -#define DSP2_GAMMA_C82_PRE_MSK (((1U << DSP2_GAMMA_C82_PRE_LEN) - 1) << DSP2_GAMMA_C82_PRE_POS) -#define DSP2_GAMMA_C82_PRE_UMSK (~(((1U << DSP2_GAMMA_C82_PRE_LEN) - 1) << DSP2_GAMMA_C82_PRE_POS)) -#define DSP2_GAMMA_C83_PRE DSP2_GAMMA_C83_PRE -#define DSP2_GAMMA_C83_PRE_POS (24U) -#define DSP2_GAMMA_C83_PRE_LEN (8U) -#define DSP2_GAMMA_C83_PRE_MSK (((1U << DSP2_GAMMA_C83_PRE_LEN) - 1) << DSP2_GAMMA_C83_PRE_POS) -#define DSP2_GAMMA_C83_PRE_UMSK (~(((1U << DSP2_GAMMA_C83_PRE_LEN) - 1) << DSP2_GAMMA_C83_PRE_POS)) - -/* 0x754 : GAMMA_CRUVE_22 */ -#define DSP2_GAMMA_GAMMA_CRUVE_22_OFFSET (0x754) -#define DSP2_GAMMA_C84_PRE DSP2_GAMMA_C84_PRE -#define DSP2_GAMMA_C84_PRE_POS (0U) -#define DSP2_GAMMA_C84_PRE_LEN (8U) -#define DSP2_GAMMA_C84_PRE_MSK (((1U << DSP2_GAMMA_C84_PRE_LEN) - 1) << DSP2_GAMMA_C84_PRE_POS) -#define DSP2_GAMMA_C84_PRE_UMSK (~(((1U << DSP2_GAMMA_C84_PRE_LEN) - 1) << DSP2_GAMMA_C84_PRE_POS)) -#define DSP2_GAMMA_C85_PRE DSP2_GAMMA_C85_PRE -#define DSP2_GAMMA_C85_PRE_POS (8U) -#define DSP2_GAMMA_C85_PRE_LEN (8U) -#define DSP2_GAMMA_C85_PRE_MSK (((1U << DSP2_GAMMA_C85_PRE_LEN) - 1) << DSP2_GAMMA_C85_PRE_POS) -#define DSP2_GAMMA_C85_PRE_UMSK (~(((1U << DSP2_GAMMA_C85_PRE_LEN) - 1) << DSP2_GAMMA_C85_PRE_POS)) -#define DSP2_GAMMA_C86_PRE DSP2_GAMMA_C86_PRE -#define DSP2_GAMMA_C86_PRE_POS (16U) -#define DSP2_GAMMA_C86_PRE_LEN (8U) -#define DSP2_GAMMA_C86_PRE_MSK (((1U << DSP2_GAMMA_C86_PRE_LEN) - 1) << DSP2_GAMMA_C86_PRE_POS) -#define DSP2_GAMMA_C86_PRE_UMSK (~(((1U << DSP2_GAMMA_C86_PRE_LEN) - 1) << DSP2_GAMMA_C86_PRE_POS)) -#define DSP2_GAMMA_C87_PRE DSP2_GAMMA_C87_PRE -#define DSP2_GAMMA_C87_PRE_POS (24U) -#define DSP2_GAMMA_C87_PRE_LEN (8U) -#define DSP2_GAMMA_C87_PRE_MSK (((1U << DSP2_GAMMA_C87_PRE_LEN) - 1) << DSP2_GAMMA_C87_PRE_POS) -#define DSP2_GAMMA_C87_PRE_UMSK (~(((1U << DSP2_GAMMA_C87_PRE_LEN) - 1) << DSP2_GAMMA_C87_PRE_POS)) - -/* 0x758 : GAMMA_CRUVE_23 */ -#define DSP2_GAMMA_GAMMA_CRUVE_23_OFFSET (0x758) -#define DSP2_GAMMA_C88_PRE DSP2_GAMMA_C88_PRE -#define DSP2_GAMMA_C88_PRE_POS (0U) -#define DSP2_GAMMA_C88_PRE_LEN (8U) -#define DSP2_GAMMA_C88_PRE_MSK (((1U << DSP2_GAMMA_C88_PRE_LEN) - 1) << DSP2_GAMMA_C88_PRE_POS) -#define DSP2_GAMMA_C88_PRE_UMSK (~(((1U << DSP2_GAMMA_C88_PRE_LEN) - 1) << DSP2_GAMMA_C88_PRE_POS)) -#define DSP2_GAMMA_C89_PRE DSP2_GAMMA_C89_PRE -#define DSP2_GAMMA_C89_PRE_POS (8U) -#define DSP2_GAMMA_C89_PRE_LEN (8U) -#define DSP2_GAMMA_C89_PRE_MSK (((1U << DSP2_GAMMA_C89_PRE_LEN) - 1) << DSP2_GAMMA_C89_PRE_POS) -#define DSP2_GAMMA_C89_PRE_UMSK (~(((1U << DSP2_GAMMA_C89_PRE_LEN) - 1) << DSP2_GAMMA_C89_PRE_POS)) -#define DSP2_GAMMA_C90_PRE DSP2_GAMMA_C90_PRE -#define DSP2_GAMMA_C90_PRE_POS (16U) -#define DSP2_GAMMA_C90_PRE_LEN (8U) -#define DSP2_GAMMA_C90_PRE_MSK (((1U << DSP2_GAMMA_C90_PRE_LEN) - 1) << DSP2_GAMMA_C90_PRE_POS) -#define DSP2_GAMMA_C90_PRE_UMSK (~(((1U << DSP2_GAMMA_C90_PRE_LEN) - 1) << DSP2_GAMMA_C90_PRE_POS)) -#define DSP2_GAMMA_C91_PRE DSP2_GAMMA_C91_PRE -#define DSP2_GAMMA_C91_PRE_POS (24U) -#define DSP2_GAMMA_C91_PRE_LEN (8U) -#define DSP2_GAMMA_C91_PRE_MSK (((1U << DSP2_GAMMA_C91_PRE_LEN) - 1) << DSP2_GAMMA_C91_PRE_POS) -#define DSP2_GAMMA_C91_PRE_UMSK (~(((1U << DSP2_GAMMA_C91_PRE_LEN) - 1) << DSP2_GAMMA_C91_PRE_POS)) - -/* 0x75C : GAMMA_CRUVE_24 */ -#define DSP2_GAMMA_GAMMA_CRUVE_24_OFFSET (0x75C) -#define DSP2_GAMMA_C92_PRE DSP2_GAMMA_C92_PRE -#define DSP2_GAMMA_C92_PRE_POS (0U) -#define DSP2_GAMMA_C92_PRE_LEN (8U) -#define DSP2_GAMMA_C92_PRE_MSK (((1U << DSP2_GAMMA_C92_PRE_LEN) - 1) << DSP2_GAMMA_C92_PRE_POS) -#define DSP2_GAMMA_C92_PRE_UMSK (~(((1U << DSP2_GAMMA_C92_PRE_LEN) - 1) << DSP2_GAMMA_C92_PRE_POS)) -#define DSP2_GAMMA_C93_PRE DSP2_GAMMA_C93_PRE -#define DSP2_GAMMA_C93_PRE_POS (8U) -#define DSP2_GAMMA_C93_PRE_LEN (8U) -#define DSP2_GAMMA_C93_PRE_MSK (((1U << DSP2_GAMMA_C93_PRE_LEN) - 1) << DSP2_GAMMA_C93_PRE_POS) -#define DSP2_GAMMA_C93_PRE_UMSK (~(((1U << DSP2_GAMMA_C93_PRE_LEN) - 1) << DSP2_GAMMA_C93_PRE_POS)) -#define DSP2_GAMMA_C94_PRE DSP2_GAMMA_C94_PRE -#define DSP2_GAMMA_C94_PRE_POS (16U) -#define DSP2_GAMMA_C94_PRE_LEN (8U) -#define DSP2_GAMMA_C94_PRE_MSK (((1U << DSP2_GAMMA_C94_PRE_LEN) - 1) << DSP2_GAMMA_C94_PRE_POS) -#define DSP2_GAMMA_C94_PRE_UMSK (~(((1U << DSP2_GAMMA_C94_PRE_LEN) - 1) << DSP2_GAMMA_C94_PRE_POS)) -#define DSP2_GAMMA_C95_PRE DSP2_GAMMA_C95_PRE -#define DSP2_GAMMA_C95_PRE_POS (24U) -#define DSP2_GAMMA_C95_PRE_LEN (8U) -#define DSP2_GAMMA_C95_PRE_MSK (((1U << DSP2_GAMMA_C95_PRE_LEN) - 1) << DSP2_GAMMA_C95_PRE_POS) -#define DSP2_GAMMA_C95_PRE_UMSK (~(((1U << DSP2_GAMMA_C95_PRE_LEN) - 1) << DSP2_GAMMA_C95_PRE_POS)) - -/* 0x760 : GAMMA_CRUVE_25 */ -#define DSP2_GAMMA_GAMMA_CRUVE_25_OFFSET (0x760) -#define DSP2_GAMMA_C96_PRE DSP2_GAMMA_C96_PRE -#define DSP2_GAMMA_C96_PRE_POS (0U) -#define DSP2_GAMMA_C96_PRE_LEN (8U) -#define DSP2_GAMMA_C96_PRE_MSK (((1U << DSP2_GAMMA_C96_PRE_LEN) - 1) << DSP2_GAMMA_C96_PRE_POS) -#define DSP2_GAMMA_C96_PRE_UMSK (~(((1U << DSP2_GAMMA_C96_PRE_LEN) - 1) << DSP2_GAMMA_C96_PRE_POS)) -#define DSP2_GAMMA_C97_PRE DSP2_GAMMA_C97_PRE -#define DSP2_GAMMA_C97_PRE_POS (8U) -#define DSP2_GAMMA_C97_PRE_LEN (8U) -#define DSP2_GAMMA_C97_PRE_MSK (((1U << DSP2_GAMMA_C97_PRE_LEN) - 1) << DSP2_GAMMA_C97_PRE_POS) -#define DSP2_GAMMA_C97_PRE_UMSK (~(((1U << DSP2_GAMMA_C97_PRE_LEN) - 1) << DSP2_GAMMA_C97_PRE_POS)) -#define DSP2_GAMMA_C98_PRE DSP2_GAMMA_C98_PRE -#define DSP2_GAMMA_C98_PRE_POS (16U) -#define DSP2_GAMMA_C98_PRE_LEN (8U) -#define DSP2_GAMMA_C98_PRE_MSK (((1U << DSP2_GAMMA_C98_PRE_LEN) - 1) << DSP2_GAMMA_C98_PRE_POS) -#define DSP2_GAMMA_C98_PRE_UMSK (~(((1U << DSP2_GAMMA_C98_PRE_LEN) - 1) << DSP2_GAMMA_C98_PRE_POS)) -#define DSP2_GAMMA_C99_PRE DSP2_GAMMA_C99_PRE -#define DSP2_GAMMA_C99_PRE_POS (24U) -#define DSP2_GAMMA_C99_PRE_LEN (8U) -#define DSP2_GAMMA_C99_PRE_MSK (((1U << DSP2_GAMMA_C99_PRE_LEN) - 1) << DSP2_GAMMA_C99_PRE_POS) -#define DSP2_GAMMA_C99_PRE_UMSK (~(((1U << DSP2_GAMMA_C99_PRE_LEN) - 1) << DSP2_GAMMA_C99_PRE_POS)) - -/* 0x764 : GAMMA_CRUVE_26 */ -#define DSP2_GAMMA_GAMMA_CRUVE_26_OFFSET (0x764) -#define DSP2_GAMMA_C100_PRE DSP2_GAMMA_C100_PRE -#define DSP2_GAMMA_C100_PRE_POS (0U) -#define DSP2_GAMMA_C100_PRE_LEN (8U) -#define DSP2_GAMMA_C100_PRE_MSK (((1U << DSP2_GAMMA_C100_PRE_LEN) - 1) << DSP2_GAMMA_C100_PRE_POS) -#define DSP2_GAMMA_C100_PRE_UMSK (~(((1U << DSP2_GAMMA_C100_PRE_LEN) - 1) << DSP2_GAMMA_C100_PRE_POS)) -#define DSP2_GAMMA_C101_PRE DSP2_GAMMA_C101_PRE -#define DSP2_GAMMA_C101_PRE_POS (8U) -#define DSP2_GAMMA_C101_PRE_LEN (8U) -#define DSP2_GAMMA_C101_PRE_MSK (((1U << DSP2_GAMMA_C101_PRE_LEN) - 1) << DSP2_GAMMA_C101_PRE_POS) -#define DSP2_GAMMA_C101_PRE_UMSK (~(((1U << DSP2_GAMMA_C101_PRE_LEN) - 1) << DSP2_GAMMA_C101_PRE_POS)) -#define DSP2_GAMMA_C102_PRE DSP2_GAMMA_C102_PRE -#define DSP2_GAMMA_C102_PRE_POS (16U) -#define DSP2_GAMMA_C102_PRE_LEN (8U) -#define DSP2_GAMMA_C102_PRE_MSK (((1U << DSP2_GAMMA_C102_PRE_LEN) - 1) << DSP2_GAMMA_C102_PRE_POS) -#define DSP2_GAMMA_C102_PRE_UMSK (~(((1U << DSP2_GAMMA_C102_PRE_LEN) - 1) << DSP2_GAMMA_C102_PRE_POS)) -#define DSP2_GAMMA_C103_PRE DSP2_GAMMA_C103_PRE -#define DSP2_GAMMA_C103_PRE_POS (24U) -#define DSP2_GAMMA_C103_PRE_LEN (8U) -#define DSP2_GAMMA_C103_PRE_MSK (((1U << DSP2_GAMMA_C103_PRE_LEN) - 1) << DSP2_GAMMA_C103_PRE_POS) -#define DSP2_GAMMA_C103_PRE_UMSK (~(((1U << DSP2_GAMMA_C103_PRE_LEN) - 1) << DSP2_GAMMA_C103_PRE_POS)) - -/* 0x768 : GAMMA_CRUVE_27 */ -#define DSP2_GAMMA_GAMMA_CRUVE_27_OFFSET (0x768) -#define DSP2_GAMMA_C104_PRE DSP2_GAMMA_C104_PRE -#define DSP2_GAMMA_C104_PRE_POS (0U) -#define DSP2_GAMMA_C104_PRE_LEN (8U) -#define DSP2_GAMMA_C104_PRE_MSK (((1U << DSP2_GAMMA_C104_PRE_LEN) - 1) << DSP2_GAMMA_C104_PRE_POS) -#define DSP2_GAMMA_C104_PRE_UMSK (~(((1U << DSP2_GAMMA_C104_PRE_LEN) - 1) << DSP2_GAMMA_C104_PRE_POS)) -#define DSP2_GAMMA_C105_PRE DSP2_GAMMA_C105_PRE -#define DSP2_GAMMA_C105_PRE_POS (8U) -#define DSP2_GAMMA_C105_PRE_LEN (8U) -#define DSP2_GAMMA_C105_PRE_MSK (((1U << DSP2_GAMMA_C105_PRE_LEN) - 1) << DSP2_GAMMA_C105_PRE_POS) -#define DSP2_GAMMA_C105_PRE_UMSK (~(((1U << DSP2_GAMMA_C105_PRE_LEN) - 1) << DSP2_GAMMA_C105_PRE_POS)) -#define DSP2_GAMMA_C106_PRE DSP2_GAMMA_C106_PRE -#define DSP2_GAMMA_C106_PRE_POS (16U) -#define DSP2_GAMMA_C106_PRE_LEN (8U) -#define DSP2_GAMMA_C106_PRE_MSK (((1U << DSP2_GAMMA_C106_PRE_LEN) - 1) << DSP2_GAMMA_C106_PRE_POS) -#define DSP2_GAMMA_C106_PRE_UMSK (~(((1U << DSP2_GAMMA_C106_PRE_LEN) - 1) << DSP2_GAMMA_C106_PRE_POS)) -#define DSP2_GAMMA_C107_PRE DSP2_GAMMA_C107_PRE -#define DSP2_GAMMA_C107_PRE_POS (24U) -#define DSP2_GAMMA_C107_PRE_LEN (8U) -#define DSP2_GAMMA_C107_PRE_MSK (((1U << DSP2_GAMMA_C107_PRE_LEN) - 1) << DSP2_GAMMA_C107_PRE_POS) -#define DSP2_GAMMA_C107_PRE_UMSK (~(((1U << DSP2_GAMMA_C107_PRE_LEN) - 1) << DSP2_GAMMA_C107_PRE_POS)) - -/* 0x76C : GAMMA_CRUVE_28 */ -#define DSP2_GAMMA_GAMMA_CRUVE_28_OFFSET (0x76C) -#define DSP2_GAMMA_C108_PRE DSP2_GAMMA_C108_PRE -#define DSP2_GAMMA_C108_PRE_POS (0U) -#define DSP2_GAMMA_C108_PRE_LEN (8U) -#define DSP2_GAMMA_C108_PRE_MSK (((1U << DSP2_GAMMA_C108_PRE_LEN) - 1) << DSP2_GAMMA_C108_PRE_POS) -#define DSP2_GAMMA_C108_PRE_UMSK (~(((1U << DSP2_GAMMA_C108_PRE_LEN) - 1) << DSP2_GAMMA_C108_PRE_POS)) -#define DSP2_GAMMA_C109_PRE DSP2_GAMMA_C109_PRE -#define DSP2_GAMMA_C109_PRE_POS (8U) -#define DSP2_GAMMA_C109_PRE_LEN (8U) -#define DSP2_GAMMA_C109_PRE_MSK (((1U << DSP2_GAMMA_C109_PRE_LEN) - 1) << DSP2_GAMMA_C109_PRE_POS) -#define DSP2_GAMMA_C109_PRE_UMSK (~(((1U << DSP2_GAMMA_C109_PRE_LEN) - 1) << DSP2_GAMMA_C109_PRE_POS)) -#define DSP2_GAMMA_C110_PRE DSP2_GAMMA_C110_PRE -#define DSP2_GAMMA_C110_PRE_POS (16U) -#define DSP2_GAMMA_C110_PRE_LEN (8U) -#define DSP2_GAMMA_C110_PRE_MSK (((1U << DSP2_GAMMA_C110_PRE_LEN) - 1) << DSP2_GAMMA_C110_PRE_POS) -#define DSP2_GAMMA_C110_PRE_UMSK (~(((1U << DSP2_GAMMA_C110_PRE_LEN) - 1) << DSP2_GAMMA_C110_PRE_POS)) -#define DSP2_GAMMA_C111_PRE DSP2_GAMMA_C111_PRE -#define DSP2_GAMMA_C111_PRE_POS (24U) -#define DSP2_GAMMA_C111_PRE_LEN (8U) -#define DSP2_GAMMA_C111_PRE_MSK (((1U << DSP2_GAMMA_C111_PRE_LEN) - 1) << DSP2_GAMMA_C111_PRE_POS) -#define DSP2_GAMMA_C111_PRE_UMSK (~(((1U << DSP2_GAMMA_C111_PRE_LEN) - 1) << DSP2_GAMMA_C111_PRE_POS)) - -/* 0x770 : GAMMA_CRUVE_29 */ -#define DSP2_GAMMA_GAMMA_CRUVE_29_OFFSET (0x770) -#define DSP2_GAMMA_C112_PRE DSP2_GAMMA_C112_PRE -#define DSP2_GAMMA_C112_PRE_POS (0U) -#define DSP2_GAMMA_C112_PRE_LEN (8U) -#define DSP2_GAMMA_C112_PRE_MSK (((1U << DSP2_GAMMA_C112_PRE_LEN) - 1) << DSP2_GAMMA_C112_PRE_POS) -#define DSP2_GAMMA_C112_PRE_UMSK (~(((1U << DSP2_GAMMA_C112_PRE_LEN) - 1) << DSP2_GAMMA_C112_PRE_POS)) -#define DSP2_GAMMA_C113_PRE DSP2_GAMMA_C113_PRE -#define DSP2_GAMMA_C113_PRE_POS (8U) -#define DSP2_GAMMA_C113_PRE_LEN (8U) -#define DSP2_GAMMA_C113_PRE_MSK (((1U << DSP2_GAMMA_C113_PRE_LEN) - 1) << DSP2_GAMMA_C113_PRE_POS) -#define DSP2_GAMMA_C113_PRE_UMSK (~(((1U << DSP2_GAMMA_C113_PRE_LEN) - 1) << DSP2_GAMMA_C113_PRE_POS)) -#define DSP2_GAMMA_C114_PRE DSP2_GAMMA_C114_PRE -#define DSP2_GAMMA_C114_PRE_POS (16U) -#define DSP2_GAMMA_C114_PRE_LEN (8U) -#define DSP2_GAMMA_C114_PRE_MSK (((1U << DSP2_GAMMA_C114_PRE_LEN) - 1) << DSP2_GAMMA_C114_PRE_POS) -#define DSP2_GAMMA_C114_PRE_UMSK (~(((1U << DSP2_GAMMA_C114_PRE_LEN) - 1) << DSP2_GAMMA_C114_PRE_POS)) -#define DSP2_GAMMA_C115_PRE DSP2_GAMMA_C115_PRE -#define DSP2_GAMMA_C115_PRE_POS (24U) -#define DSP2_GAMMA_C115_PRE_LEN (8U) -#define DSP2_GAMMA_C115_PRE_MSK (((1U << DSP2_GAMMA_C115_PRE_LEN) - 1) << DSP2_GAMMA_C115_PRE_POS) -#define DSP2_GAMMA_C115_PRE_UMSK (~(((1U << DSP2_GAMMA_C115_PRE_LEN) - 1) << DSP2_GAMMA_C115_PRE_POS)) - -/* 0x774 : GAMMA_CRUVE_30 */ -#define DSP2_GAMMA_GAMMA_CRUVE_30_OFFSET (0x774) -#define DSP2_GAMMA_C116_PRE DSP2_GAMMA_C116_PRE -#define DSP2_GAMMA_C116_PRE_POS (0U) -#define DSP2_GAMMA_C116_PRE_LEN (8U) -#define DSP2_GAMMA_C116_PRE_MSK (((1U << DSP2_GAMMA_C116_PRE_LEN) - 1) << DSP2_GAMMA_C116_PRE_POS) -#define DSP2_GAMMA_C116_PRE_UMSK (~(((1U << DSP2_GAMMA_C116_PRE_LEN) - 1) << DSP2_GAMMA_C116_PRE_POS)) -#define DSP2_GAMMA_C117_PRE DSP2_GAMMA_C117_PRE -#define DSP2_GAMMA_C117_PRE_POS (8U) -#define DSP2_GAMMA_C117_PRE_LEN (8U) -#define DSP2_GAMMA_C117_PRE_MSK (((1U << DSP2_GAMMA_C117_PRE_LEN) - 1) << DSP2_GAMMA_C117_PRE_POS) -#define DSP2_GAMMA_C117_PRE_UMSK (~(((1U << DSP2_GAMMA_C117_PRE_LEN) - 1) << DSP2_GAMMA_C117_PRE_POS)) -#define DSP2_GAMMA_C118_PRE DSP2_GAMMA_C118_PRE -#define DSP2_GAMMA_C118_PRE_POS (16U) -#define DSP2_GAMMA_C118_PRE_LEN (8U) -#define DSP2_GAMMA_C118_PRE_MSK (((1U << DSP2_GAMMA_C118_PRE_LEN) - 1) << DSP2_GAMMA_C118_PRE_POS) -#define DSP2_GAMMA_C118_PRE_UMSK (~(((1U << DSP2_GAMMA_C118_PRE_LEN) - 1) << DSP2_GAMMA_C118_PRE_POS)) -#define DSP2_GAMMA_C119_PRE DSP2_GAMMA_C119_PRE -#define DSP2_GAMMA_C119_PRE_POS (24U) -#define DSP2_GAMMA_C119_PRE_LEN (8U) -#define DSP2_GAMMA_C119_PRE_MSK (((1U << DSP2_GAMMA_C119_PRE_LEN) - 1) << DSP2_GAMMA_C119_PRE_POS) -#define DSP2_GAMMA_C119_PRE_UMSK (~(((1U << DSP2_GAMMA_C119_PRE_LEN) - 1) << DSP2_GAMMA_C119_PRE_POS)) - -/* 0x778 : GAMMA_CRUVE_31 */ -#define DSP2_GAMMA_GAMMA_CRUVE_31_OFFSET (0x778) -#define DSP2_GAMMA_C120_PRE DSP2_GAMMA_C120_PRE -#define DSP2_GAMMA_C120_PRE_POS (0U) -#define DSP2_GAMMA_C120_PRE_LEN (8U) -#define DSP2_GAMMA_C120_PRE_MSK (((1U << DSP2_GAMMA_C120_PRE_LEN) - 1) << DSP2_GAMMA_C120_PRE_POS) -#define DSP2_GAMMA_C120_PRE_UMSK (~(((1U << DSP2_GAMMA_C120_PRE_LEN) - 1) << DSP2_GAMMA_C120_PRE_POS)) -#define DSP2_GAMMA_C121_PRE DSP2_GAMMA_C121_PRE -#define DSP2_GAMMA_C121_PRE_POS (8U) -#define DSP2_GAMMA_C121_PRE_LEN (8U) -#define DSP2_GAMMA_C121_PRE_MSK (((1U << DSP2_GAMMA_C121_PRE_LEN) - 1) << DSP2_GAMMA_C121_PRE_POS) -#define DSP2_GAMMA_C121_PRE_UMSK (~(((1U << DSP2_GAMMA_C121_PRE_LEN) - 1) << DSP2_GAMMA_C121_PRE_POS)) -#define DSP2_GAMMA_C122_PRE DSP2_GAMMA_C122_PRE -#define DSP2_GAMMA_C122_PRE_POS (16U) -#define DSP2_GAMMA_C122_PRE_LEN (8U) -#define DSP2_GAMMA_C122_PRE_MSK (((1U << DSP2_GAMMA_C122_PRE_LEN) - 1) << DSP2_GAMMA_C122_PRE_POS) -#define DSP2_GAMMA_C122_PRE_UMSK (~(((1U << DSP2_GAMMA_C122_PRE_LEN) - 1) << DSP2_GAMMA_C122_PRE_POS)) -#define DSP2_GAMMA_C123_PRE DSP2_GAMMA_C123_PRE -#define DSP2_GAMMA_C123_PRE_POS (24U) -#define DSP2_GAMMA_C123_PRE_LEN (8U) -#define DSP2_GAMMA_C123_PRE_MSK (((1U << DSP2_GAMMA_C123_PRE_LEN) - 1) << DSP2_GAMMA_C123_PRE_POS) -#define DSP2_GAMMA_C123_PRE_UMSK (~(((1U << DSP2_GAMMA_C123_PRE_LEN) - 1) << DSP2_GAMMA_C123_PRE_POS)) - -/* 0x77C : GAMMA_CRUVE_32 */ -#define DSP2_GAMMA_GAMMA_CRUVE_32_OFFSET (0x77C) -#define DSP2_GAMMA_C124_PRE DSP2_GAMMA_C124_PRE -#define DSP2_GAMMA_C124_PRE_POS (0U) -#define DSP2_GAMMA_C124_PRE_LEN (8U) -#define DSP2_GAMMA_C124_PRE_MSK (((1U << DSP2_GAMMA_C124_PRE_LEN) - 1) << DSP2_GAMMA_C124_PRE_POS) -#define DSP2_GAMMA_C124_PRE_UMSK (~(((1U << DSP2_GAMMA_C124_PRE_LEN) - 1) << DSP2_GAMMA_C124_PRE_POS)) -#define DSP2_GAMMA_C125_PRE DSP2_GAMMA_C125_PRE -#define DSP2_GAMMA_C125_PRE_POS (8U) -#define DSP2_GAMMA_C125_PRE_LEN (8U) -#define DSP2_GAMMA_C125_PRE_MSK (((1U << DSP2_GAMMA_C125_PRE_LEN) - 1) << DSP2_GAMMA_C125_PRE_POS) -#define DSP2_GAMMA_C125_PRE_UMSK (~(((1U << DSP2_GAMMA_C125_PRE_LEN) - 1) << DSP2_GAMMA_C125_PRE_POS)) -#define DSP2_GAMMA_C126_PRE DSP2_GAMMA_C126_PRE -#define DSP2_GAMMA_C126_PRE_POS (16U) -#define DSP2_GAMMA_C126_PRE_LEN (8U) -#define DSP2_GAMMA_C126_PRE_MSK (((1U << DSP2_GAMMA_C126_PRE_LEN) - 1) << DSP2_GAMMA_C126_PRE_POS) -#define DSP2_GAMMA_C126_PRE_UMSK (~(((1U << DSP2_GAMMA_C126_PRE_LEN) - 1) << DSP2_GAMMA_C126_PRE_POS)) -#define DSP2_GAMMA_C127_PRE DSP2_GAMMA_C127_PRE -#define DSP2_GAMMA_C127_PRE_POS (24U) -#define DSP2_GAMMA_C127_PRE_LEN (8U) -#define DSP2_GAMMA_C127_PRE_MSK (((1U << DSP2_GAMMA_C127_PRE_LEN) - 1) << DSP2_GAMMA_C127_PRE_POS) -#define DSP2_GAMMA_C127_PRE_UMSK (~(((1U << DSP2_GAMMA_C127_PRE_LEN) - 1) << DSP2_GAMMA_C127_PRE_POS)) - -/* 0x780 : GAMMA_CRUVE_33 */ -#define DSP2_GAMMA_GAMMA_CRUVE_33_OFFSET (0x780) -#define DSP2_GAMMA_C128_PRE DSP2_GAMMA_C128_PRE -#define DSP2_GAMMA_C128_PRE_POS (0U) -#define DSP2_GAMMA_C128_PRE_LEN (8U) -#define DSP2_GAMMA_C128_PRE_MSK (((1U << DSP2_GAMMA_C128_PRE_LEN) - 1) << DSP2_GAMMA_C128_PRE_POS) -#define DSP2_GAMMA_C128_PRE_UMSK (~(((1U << DSP2_GAMMA_C128_PRE_LEN) - 1) << DSP2_GAMMA_C128_PRE_POS)) -#define DSP2_GAMMA_C129_PRE DSP2_GAMMA_C129_PRE -#define DSP2_GAMMA_C129_PRE_POS (8U) -#define DSP2_GAMMA_C129_PRE_LEN (8U) -#define DSP2_GAMMA_C129_PRE_MSK (((1U << DSP2_GAMMA_C129_PRE_LEN) - 1) << DSP2_GAMMA_C129_PRE_POS) -#define DSP2_GAMMA_C129_PRE_UMSK (~(((1U << DSP2_GAMMA_C129_PRE_LEN) - 1) << DSP2_GAMMA_C129_PRE_POS)) -#define DSP2_GAMMA_C130_PRE DSP2_GAMMA_C130_PRE -#define DSP2_GAMMA_C130_PRE_POS (16U) -#define DSP2_GAMMA_C130_PRE_LEN (8U) -#define DSP2_GAMMA_C130_PRE_MSK (((1U << DSP2_GAMMA_C130_PRE_LEN) - 1) << DSP2_GAMMA_C130_PRE_POS) -#define DSP2_GAMMA_C130_PRE_UMSK (~(((1U << DSP2_GAMMA_C130_PRE_LEN) - 1) << DSP2_GAMMA_C130_PRE_POS)) -#define DSP2_GAMMA_C131_PRE DSP2_GAMMA_C131_PRE -#define DSP2_GAMMA_C131_PRE_POS (24U) -#define DSP2_GAMMA_C131_PRE_LEN (8U) -#define DSP2_GAMMA_C131_PRE_MSK (((1U << DSP2_GAMMA_C131_PRE_LEN) - 1) << DSP2_GAMMA_C131_PRE_POS) -#define DSP2_GAMMA_C131_PRE_UMSK (~(((1U << DSP2_GAMMA_C131_PRE_LEN) - 1) << DSP2_GAMMA_C131_PRE_POS)) - -/* 0x784 : GAMMA_CRUVE_34 */ -#define DSP2_GAMMA_GAMMA_CRUVE_34_OFFSET (0x784) -#define DSP2_GAMMA_C132_PRE DSP2_GAMMA_C132_PRE -#define DSP2_GAMMA_C132_PRE_POS (0U) -#define DSP2_GAMMA_C132_PRE_LEN (8U) -#define DSP2_GAMMA_C132_PRE_MSK (((1U << DSP2_GAMMA_C132_PRE_LEN) - 1) << DSP2_GAMMA_C132_PRE_POS) -#define DSP2_GAMMA_C132_PRE_UMSK (~(((1U << DSP2_GAMMA_C132_PRE_LEN) - 1) << DSP2_GAMMA_C132_PRE_POS)) -#define DSP2_GAMMA_C133_PRE DSP2_GAMMA_C133_PRE -#define DSP2_GAMMA_C133_PRE_POS (8U) -#define DSP2_GAMMA_C133_PRE_LEN (8U) -#define DSP2_GAMMA_C133_PRE_MSK (((1U << DSP2_GAMMA_C133_PRE_LEN) - 1) << DSP2_GAMMA_C133_PRE_POS) -#define DSP2_GAMMA_C133_PRE_UMSK (~(((1U << DSP2_GAMMA_C133_PRE_LEN) - 1) << DSP2_GAMMA_C133_PRE_POS)) -#define DSP2_GAMMA_C134_PRE DSP2_GAMMA_C134_PRE -#define DSP2_GAMMA_C134_PRE_POS (16U) -#define DSP2_GAMMA_C134_PRE_LEN (8U) -#define DSP2_GAMMA_C134_PRE_MSK (((1U << DSP2_GAMMA_C134_PRE_LEN) - 1) << DSP2_GAMMA_C134_PRE_POS) -#define DSP2_GAMMA_C134_PRE_UMSK (~(((1U << DSP2_GAMMA_C134_PRE_LEN) - 1) << DSP2_GAMMA_C134_PRE_POS)) -#define DSP2_GAMMA_C135_PRE DSP2_GAMMA_C135_PRE -#define DSP2_GAMMA_C135_PRE_POS (24U) -#define DSP2_GAMMA_C135_PRE_LEN (8U) -#define DSP2_GAMMA_C135_PRE_MSK (((1U << DSP2_GAMMA_C135_PRE_LEN) - 1) << DSP2_GAMMA_C135_PRE_POS) -#define DSP2_GAMMA_C135_PRE_UMSK (~(((1U << DSP2_GAMMA_C135_PRE_LEN) - 1) << DSP2_GAMMA_C135_PRE_POS)) - -/* 0x788 : GAMMA_CRUVE_35 */ -#define DSP2_GAMMA_GAMMA_CRUVE_35_OFFSET (0x788) -#define DSP2_GAMMA_C136_PRE DSP2_GAMMA_C136_PRE -#define DSP2_GAMMA_C136_PRE_POS (0U) -#define DSP2_GAMMA_C136_PRE_LEN (8U) -#define DSP2_GAMMA_C136_PRE_MSK (((1U << DSP2_GAMMA_C136_PRE_LEN) - 1) << DSP2_GAMMA_C136_PRE_POS) -#define DSP2_GAMMA_C136_PRE_UMSK (~(((1U << DSP2_GAMMA_C136_PRE_LEN) - 1) << DSP2_GAMMA_C136_PRE_POS)) -#define DSP2_GAMMA_C137_PRE DSP2_GAMMA_C137_PRE -#define DSP2_GAMMA_C137_PRE_POS (8U) -#define DSP2_GAMMA_C137_PRE_LEN (8U) -#define DSP2_GAMMA_C137_PRE_MSK (((1U << DSP2_GAMMA_C137_PRE_LEN) - 1) << DSP2_GAMMA_C137_PRE_POS) -#define DSP2_GAMMA_C137_PRE_UMSK (~(((1U << DSP2_GAMMA_C137_PRE_LEN) - 1) << DSP2_GAMMA_C137_PRE_POS)) -#define DSP2_GAMMA_C138_PRE DSP2_GAMMA_C138_PRE -#define DSP2_GAMMA_C138_PRE_POS (16U) -#define DSP2_GAMMA_C138_PRE_LEN (8U) -#define DSP2_GAMMA_C138_PRE_MSK (((1U << DSP2_GAMMA_C138_PRE_LEN) - 1) << DSP2_GAMMA_C138_PRE_POS) -#define DSP2_GAMMA_C138_PRE_UMSK (~(((1U << DSP2_GAMMA_C138_PRE_LEN) - 1) << DSP2_GAMMA_C138_PRE_POS)) -#define DSP2_GAMMA_C139_PRE DSP2_GAMMA_C139_PRE -#define DSP2_GAMMA_C139_PRE_POS (24U) -#define DSP2_GAMMA_C139_PRE_LEN (8U) -#define DSP2_GAMMA_C139_PRE_MSK (((1U << DSP2_GAMMA_C139_PRE_LEN) - 1) << DSP2_GAMMA_C139_PRE_POS) -#define DSP2_GAMMA_C139_PRE_UMSK (~(((1U << DSP2_GAMMA_C139_PRE_LEN) - 1) << DSP2_GAMMA_C139_PRE_POS)) - -/* 0x78C : GAMMA_CRUVE_36 */ -#define DSP2_GAMMA_GAMMA_CRUVE_36_OFFSET (0x78C) -#define DSP2_GAMMA_C140_PRE DSP2_GAMMA_C140_PRE -#define DSP2_GAMMA_C140_PRE_POS (0U) -#define DSP2_GAMMA_C140_PRE_LEN (8U) -#define DSP2_GAMMA_C140_PRE_MSK (((1U << DSP2_GAMMA_C140_PRE_LEN) - 1) << DSP2_GAMMA_C140_PRE_POS) -#define DSP2_GAMMA_C140_PRE_UMSK (~(((1U << DSP2_GAMMA_C140_PRE_LEN) - 1) << DSP2_GAMMA_C140_PRE_POS)) -#define DSP2_GAMMA_C141_PRE DSP2_GAMMA_C141_PRE -#define DSP2_GAMMA_C141_PRE_POS (8U) -#define DSP2_GAMMA_C141_PRE_LEN (8U) -#define DSP2_GAMMA_C141_PRE_MSK (((1U << DSP2_GAMMA_C141_PRE_LEN) - 1) << DSP2_GAMMA_C141_PRE_POS) -#define DSP2_GAMMA_C141_PRE_UMSK (~(((1U << DSP2_GAMMA_C141_PRE_LEN) - 1) << DSP2_GAMMA_C141_PRE_POS)) -#define DSP2_GAMMA_C142_PRE DSP2_GAMMA_C142_PRE -#define DSP2_GAMMA_C142_PRE_POS (16U) -#define DSP2_GAMMA_C142_PRE_LEN (8U) -#define DSP2_GAMMA_C142_PRE_MSK (((1U << DSP2_GAMMA_C142_PRE_LEN) - 1) << DSP2_GAMMA_C142_PRE_POS) -#define DSP2_GAMMA_C142_PRE_UMSK (~(((1U << DSP2_GAMMA_C142_PRE_LEN) - 1) << DSP2_GAMMA_C142_PRE_POS)) -#define DSP2_GAMMA_C143_PRE DSP2_GAMMA_C143_PRE -#define DSP2_GAMMA_C143_PRE_POS (24U) -#define DSP2_GAMMA_C143_PRE_LEN (8U) -#define DSP2_GAMMA_C143_PRE_MSK (((1U << DSP2_GAMMA_C143_PRE_LEN) - 1) << DSP2_GAMMA_C143_PRE_POS) -#define DSP2_GAMMA_C143_PRE_UMSK (~(((1U << DSP2_GAMMA_C143_PRE_LEN) - 1) << DSP2_GAMMA_C143_PRE_POS)) - -/* 0x790 : GAMMA_CRUVE_37 */ -#define DSP2_GAMMA_GAMMA_CRUVE_37_OFFSET (0x790) -#define DSP2_GAMMA_C144_PRE DSP2_GAMMA_C144_PRE -#define DSP2_GAMMA_C144_PRE_POS (0U) -#define DSP2_GAMMA_C144_PRE_LEN (8U) -#define DSP2_GAMMA_C144_PRE_MSK (((1U << DSP2_GAMMA_C144_PRE_LEN) - 1) << DSP2_GAMMA_C144_PRE_POS) -#define DSP2_GAMMA_C144_PRE_UMSK (~(((1U << DSP2_GAMMA_C144_PRE_LEN) - 1) << DSP2_GAMMA_C144_PRE_POS)) -#define DSP2_GAMMA_C145_PRE DSP2_GAMMA_C145_PRE -#define DSP2_GAMMA_C145_PRE_POS (8U) -#define DSP2_GAMMA_C145_PRE_LEN (8U) -#define DSP2_GAMMA_C145_PRE_MSK (((1U << DSP2_GAMMA_C145_PRE_LEN) - 1) << DSP2_GAMMA_C145_PRE_POS) -#define DSP2_GAMMA_C145_PRE_UMSK (~(((1U << DSP2_GAMMA_C145_PRE_LEN) - 1) << DSP2_GAMMA_C145_PRE_POS)) -#define DSP2_GAMMA_C146_PRE DSP2_GAMMA_C146_PRE -#define DSP2_GAMMA_C146_PRE_POS (16U) -#define DSP2_GAMMA_C146_PRE_LEN (8U) -#define DSP2_GAMMA_C146_PRE_MSK (((1U << DSP2_GAMMA_C146_PRE_LEN) - 1) << DSP2_GAMMA_C146_PRE_POS) -#define DSP2_GAMMA_C146_PRE_UMSK (~(((1U << DSP2_GAMMA_C146_PRE_LEN) - 1) << DSP2_GAMMA_C146_PRE_POS)) -#define DSP2_GAMMA_C147_PRE DSP2_GAMMA_C147_PRE -#define DSP2_GAMMA_C147_PRE_POS (24U) -#define DSP2_GAMMA_C147_PRE_LEN (8U) -#define DSP2_GAMMA_C147_PRE_MSK (((1U << DSP2_GAMMA_C147_PRE_LEN) - 1) << DSP2_GAMMA_C147_PRE_POS) -#define DSP2_GAMMA_C147_PRE_UMSK (~(((1U << DSP2_GAMMA_C147_PRE_LEN) - 1) << DSP2_GAMMA_C147_PRE_POS)) - -/* 0x794 : GAMMA_CRUVE_38 */ -#define DSP2_GAMMA_GAMMA_CRUVE_38_OFFSET (0x794) -#define DSP2_GAMMA_C148_PRE DSP2_GAMMA_C148_PRE -#define DSP2_GAMMA_C148_PRE_POS (0U) -#define DSP2_GAMMA_C148_PRE_LEN (8U) -#define DSP2_GAMMA_C148_PRE_MSK (((1U << DSP2_GAMMA_C148_PRE_LEN) - 1) << DSP2_GAMMA_C148_PRE_POS) -#define DSP2_GAMMA_C148_PRE_UMSK (~(((1U << DSP2_GAMMA_C148_PRE_LEN) - 1) << DSP2_GAMMA_C148_PRE_POS)) -#define DSP2_GAMMA_C149_PRE DSP2_GAMMA_C149_PRE -#define DSP2_GAMMA_C149_PRE_POS (8U) -#define DSP2_GAMMA_C149_PRE_LEN (8U) -#define DSP2_GAMMA_C149_PRE_MSK (((1U << DSP2_GAMMA_C149_PRE_LEN) - 1) << DSP2_GAMMA_C149_PRE_POS) -#define DSP2_GAMMA_C149_PRE_UMSK (~(((1U << DSP2_GAMMA_C149_PRE_LEN) - 1) << DSP2_GAMMA_C149_PRE_POS)) -#define DSP2_GAMMA_C150_PRE DSP2_GAMMA_C150_PRE -#define DSP2_GAMMA_C150_PRE_POS (16U) -#define DSP2_GAMMA_C150_PRE_LEN (8U) -#define DSP2_GAMMA_C150_PRE_MSK (((1U << DSP2_GAMMA_C150_PRE_LEN) - 1) << DSP2_GAMMA_C150_PRE_POS) -#define DSP2_GAMMA_C150_PRE_UMSK (~(((1U << DSP2_GAMMA_C150_PRE_LEN) - 1) << DSP2_GAMMA_C150_PRE_POS)) -#define DSP2_GAMMA_C151_PRE DSP2_GAMMA_C151_PRE -#define DSP2_GAMMA_C151_PRE_POS (24U) -#define DSP2_GAMMA_C151_PRE_LEN (8U) -#define DSP2_GAMMA_C151_PRE_MSK (((1U << DSP2_GAMMA_C151_PRE_LEN) - 1) << DSP2_GAMMA_C151_PRE_POS) -#define DSP2_GAMMA_C151_PRE_UMSK (~(((1U << DSP2_GAMMA_C151_PRE_LEN) - 1) << DSP2_GAMMA_C151_PRE_POS)) - -/* 0x798 : GAMMA_CRUVE_39 */ -#define DSP2_GAMMA_GAMMA_CRUVE_39_OFFSET (0x798) -#define DSP2_GAMMA_C152_PRE DSP2_GAMMA_C152_PRE -#define DSP2_GAMMA_C152_PRE_POS (0U) -#define DSP2_GAMMA_C152_PRE_LEN (8U) -#define DSP2_GAMMA_C152_PRE_MSK (((1U << DSP2_GAMMA_C152_PRE_LEN) - 1) << DSP2_GAMMA_C152_PRE_POS) -#define DSP2_GAMMA_C152_PRE_UMSK (~(((1U << DSP2_GAMMA_C152_PRE_LEN) - 1) << DSP2_GAMMA_C152_PRE_POS)) -#define DSP2_GAMMA_C153_PRE DSP2_GAMMA_C153_PRE -#define DSP2_GAMMA_C153_PRE_POS (8U) -#define DSP2_GAMMA_C153_PRE_LEN (8U) -#define DSP2_GAMMA_C153_PRE_MSK (((1U << DSP2_GAMMA_C153_PRE_LEN) - 1) << DSP2_GAMMA_C153_PRE_POS) -#define DSP2_GAMMA_C153_PRE_UMSK (~(((1U << DSP2_GAMMA_C153_PRE_LEN) - 1) << DSP2_GAMMA_C153_PRE_POS)) -#define DSP2_GAMMA_C154_PRE DSP2_GAMMA_C154_PRE -#define DSP2_GAMMA_C154_PRE_POS (16U) -#define DSP2_GAMMA_C154_PRE_LEN (8U) -#define DSP2_GAMMA_C154_PRE_MSK (((1U << DSP2_GAMMA_C154_PRE_LEN) - 1) << DSP2_GAMMA_C154_PRE_POS) -#define DSP2_GAMMA_C154_PRE_UMSK (~(((1U << DSP2_GAMMA_C154_PRE_LEN) - 1) << DSP2_GAMMA_C154_PRE_POS)) -#define DSP2_GAMMA_C155_PRE DSP2_GAMMA_C155_PRE -#define DSP2_GAMMA_C155_PRE_POS (24U) -#define DSP2_GAMMA_C155_PRE_LEN (8U) -#define DSP2_GAMMA_C155_PRE_MSK (((1U << DSP2_GAMMA_C155_PRE_LEN) - 1) << DSP2_GAMMA_C155_PRE_POS) -#define DSP2_GAMMA_C155_PRE_UMSK (~(((1U << DSP2_GAMMA_C155_PRE_LEN) - 1) << DSP2_GAMMA_C155_PRE_POS)) - -/* 0x79C : GAMMA_CRUVE_40 */ -#define DSP2_GAMMA_GAMMA_CRUVE_40_OFFSET (0x79C) -#define DSP2_GAMMA_C156_PRE DSP2_GAMMA_C156_PRE -#define DSP2_GAMMA_C156_PRE_POS (0U) -#define DSP2_GAMMA_C156_PRE_LEN (8U) -#define DSP2_GAMMA_C156_PRE_MSK (((1U << DSP2_GAMMA_C156_PRE_LEN) - 1) << DSP2_GAMMA_C156_PRE_POS) -#define DSP2_GAMMA_C156_PRE_UMSK (~(((1U << DSP2_GAMMA_C156_PRE_LEN) - 1) << DSP2_GAMMA_C156_PRE_POS)) -#define DSP2_GAMMA_C157_PRE DSP2_GAMMA_C157_PRE -#define DSP2_GAMMA_C157_PRE_POS (8U) -#define DSP2_GAMMA_C157_PRE_LEN (8U) -#define DSP2_GAMMA_C157_PRE_MSK (((1U << DSP2_GAMMA_C157_PRE_LEN) - 1) << DSP2_GAMMA_C157_PRE_POS) -#define DSP2_GAMMA_C157_PRE_UMSK (~(((1U << DSP2_GAMMA_C157_PRE_LEN) - 1) << DSP2_GAMMA_C157_PRE_POS)) -#define DSP2_GAMMA_C158_PRE DSP2_GAMMA_C158_PRE -#define DSP2_GAMMA_C158_PRE_POS (16U) -#define DSP2_GAMMA_C158_PRE_LEN (8U) -#define DSP2_GAMMA_C158_PRE_MSK (((1U << DSP2_GAMMA_C158_PRE_LEN) - 1) << DSP2_GAMMA_C158_PRE_POS) -#define DSP2_GAMMA_C158_PRE_UMSK (~(((1U << DSP2_GAMMA_C158_PRE_LEN) - 1) << DSP2_GAMMA_C158_PRE_POS)) -#define DSP2_GAMMA_C159_PRE DSP2_GAMMA_C159_PRE -#define DSP2_GAMMA_C159_PRE_POS (24U) -#define DSP2_GAMMA_C159_PRE_LEN (8U) -#define DSP2_GAMMA_C159_PRE_MSK (((1U << DSP2_GAMMA_C159_PRE_LEN) - 1) << DSP2_GAMMA_C159_PRE_POS) -#define DSP2_GAMMA_C159_PRE_UMSK (~(((1U << DSP2_GAMMA_C159_PRE_LEN) - 1) << DSP2_GAMMA_C159_PRE_POS)) - -/* 0x7A0 : GAMMA_CRUVE_41 */ -#define DSP2_GAMMA_GAMMA_CRUVE_41_OFFSET (0x7A0) -#define DSP2_GAMMA_C160_PRE DSP2_GAMMA_C160_PRE -#define DSP2_GAMMA_C160_PRE_POS (0U) -#define DSP2_GAMMA_C160_PRE_LEN (8U) -#define DSP2_GAMMA_C160_PRE_MSK (((1U << DSP2_GAMMA_C160_PRE_LEN) - 1) << DSP2_GAMMA_C160_PRE_POS) -#define DSP2_GAMMA_C160_PRE_UMSK (~(((1U << DSP2_GAMMA_C160_PRE_LEN) - 1) << DSP2_GAMMA_C160_PRE_POS)) -#define DSP2_GAMMA_C161_PRE DSP2_GAMMA_C161_PRE -#define DSP2_GAMMA_C161_PRE_POS (8U) -#define DSP2_GAMMA_C161_PRE_LEN (8U) -#define DSP2_GAMMA_C161_PRE_MSK (((1U << DSP2_GAMMA_C161_PRE_LEN) - 1) << DSP2_GAMMA_C161_PRE_POS) -#define DSP2_GAMMA_C161_PRE_UMSK (~(((1U << DSP2_GAMMA_C161_PRE_LEN) - 1) << DSP2_GAMMA_C161_PRE_POS)) -#define DSP2_GAMMA_C162_PRE DSP2_GAMMA_C162_PRE -#define DSP2_GAMMA_C162_PRE_POS (16U) -#define DSP2_GAMMA_C162_PRE_LEN (8U) -#define DSP2_GAMMA_C162_PRE_MSK (((1U << DSP2_GAMMA_C162_PRE_LEN) - 1) << DSP2_GAMMA_C162_PRE_POS) -#define DSP2_GAMMA_C162_PRE_UMSK (~(((1U << DSP2_GAMMA_C162_PRE_LEN) - 1) << DSP2_GAMMA_C162_PRE_POS)) -#define DSP2_GAMMA_C163_PRE DSP2_GAMMA_C163_PRE -#define DSP2_GAMMA_C163_PRE_POS (24U) -#define DSP2_GAMMA_C163_PRE_LEN (8U) -#define DSP2_GAMMA_C163_PRE_MSK (((1U << DSP2_GAMMA_C163_PRE_LEN) - 1) << DSP2_GAMMA_C163_PRE_POS) -#define DSP2_GAMMA_C163_PRE_UMSK (~(((1U << DSP2_GAMMA_C163_PRE_LEN) - 1) << DSP2_GAMMA_C163_PRE_POS)) - -/* 0x7A4 : GAMMA_CRUVE_42 */ -#define DSP2_GAMMA_GAMMA_CRUVE_42_OFFSET (0x7A4) -#define DSP2_GAMMA_C164_PRE DSP2_GAMMA_C164_PRE -#define DSP2_GAMMA_C164_PRE_POS (0U) -#define DSP2_GAMMA_C164_PRE_LEN (8U) -#define DSP2_GAMMA_C164_PRE_MSK (((1U << DSP2_GAMMA_C164_PRE_LEN) - 1) << DSP2_GAMMA_C164_PRE_POS) -#define DSP2_GAMMA_C164_PRE_UMSK (~(((1U << DSP2_GAMMA_C164_PRE_LEN) - 1) << DSP2_GAMMA_C164_PRE_POS)) -#define DSP2_GAMMA_C165_PRE DSP2_GAMMA_C165_PRE -#define DSP2_GAMMA_C165_PRE_POS (8U) -#define DSP2_GAMMA_C165_PRE_LEN (8U) -#define DSP2_GAMMA_C165_PRE_MSK (((1U << DSP2_GAMMA_C165_PRE_LEN) - 1) << DSP2_GAMMA_C165_PRE_POS) -#define DSP2_GAMMA_C165_PRE_UMSK (~(((1U << DSP2_GAMMA_C165_PRE_LEN) - 1) << DSP2_GAMMA_C165_PRE_POS)) -#define DSP2_GAMMA_C166_PRE DSP2_GAMMA_C166_PRE -#define DSP2_GAMMA_C166_PRE_POS (16U) -#define DSP2_GAMMA_C166_PRE_LEN (8U) -#define DSP2_GAMMA_C166_PRE_MSK (((1U << DSP2_GAMMA_C166_PRE_LEN) - 1) << DSP2_GAMMA_C166_PRE_POS) -#define DSP2_GAMMA_C166_PRE_UMSK (~(((1U << DSP2_GAMMA_C166_PRE_LEN) - 1) << DSP2_GAMMA_C166_PRE_POS)) -#define DSP2_GAMMA_C167_PRE DSP2_GAMMA_C167_PRE -#define DSP2_GAMMA_C167_PRE_POS (24U) -#define DSP2_GAMMA_C167_PRE_LEN (8U) -#define DSP2_GAMMA_C167_PRE_MSK (((1U << DSP2_GAMMA_C167_PRE_LEN) - 1) << DSP2_GAMMA_C167_PRE_POS) -#define DSP2_GAMMA_C167_PRE_UMSK (~(((1U << DSP2_GAMMA_C167_PRE_LEN) - 1) << DSP2_GAMMA_C167_PRE_POS)) - -/* 0x7A8 : GAMMA_CRUVE_43 */ -#define DSP2_GAMMA_GAMMA_CRUVE_43_OFFSET (0x7A8) -#define DSP2_GAMMA_C168_PRE DSP2_GAMMA_C168_PRE -#define DSP2_GAMMA_C168_PRE_POS (0U) -#define DSP2_GAMMA_C168_PRE_LEN (8U) -#define DSP2_GAMMA_C168_PRE_MSK (((1U << DSP2_GAMMA_C168_PRE_LEN) - 1) << DSP2_GAMMA_C168_PRE_POS) -#define DSP2_GAMMA_C168_PRE_UMSK (~(((1U << DSP2_GAMMA_C168_PRE_LEN) - 1) << DSP2_GAMMA_C168_PRE_POS)) -#define DSP2_GAMMA_C169_PRE DSP2_GAMMA_C169_PRE -#define DSP2_GAMMA_C169_PRE_POS (8U) -#define DSP2_GAMMA_C169_PRE_LEN (8U) -#define DSP2_GAMMA_C169_PRE_MSK (((1U << DSP2_GAMMA_C169_PRE_LEN) - 1) << DSP2_GAMMA_C169_PRE_POS) -#define DSP2_GAMMA_C169_PRE_UMSK (~(((1U << DSP2_GAMMA_C169_PRE_LEN) - 1) << DSP2_GAMMA_C169_PRE_POS)) -#define DSP2_GAMMA_C170_PRE DSP2_GAMMA_C170_PRE -#define DSP2_GAMMA_C170_PRE_POS (16U) -#define DSP2_GAMMA_C170_PRE_LEN (8U) -#define DSP2_GAMMA_C170_PRE_MSK (((1U << DSP2_GAMMA_C170_PRE_LEN) - 1) << DSP2_GAMMA_C170_PRE_POS) -#define DSP2_GAMMA_C170_PRE_UMSK (~(((1U << DSP2_GAMMA_C170_PRE_LEN) - 1) << DSP2_GAMMA_C170_PRE_POS)) -#define DSP2_GAMMA_C171_PRE DSP2_GAMMA_C171_PRE -#define DSP2_GAMMA_C171_PRE_POS (24U) -#define DSP2_GAMMA_C171_PRE_LEN (8U) -#define DSP2_GAMMA_C171_PRE_MSK (((1U << DSP2_GAMMA_C171_PRE_LEN) - 1) << DSP2_GAMMA_C171_PRE_POS) -#define DSP2_GAMMA_C171_PRE_UMSK (~(((1U << DSP2_GAMMA_C171_PRE_LEN) - 1) << DSP2_GAMMA_C171_PRE_POS)) - -/* 0x7AC : GAMMA_CRUVE_44 */ -#define DSP2_GAMMA_GAMMA_CRUVE_44_OFFSET (0x7AC) -#define DSP2_GAMMA_C172_PRE DSP2_GAMMA_C172_PRE -#define DSP2_GAMMA_C172_PRE_POS (0U) -#define DSP2_GAMMA_C172_PRE_LEN (8U) -#define DSP2_GAMMA_C172_PRE_MSK (((1U << DSP2_GAMMA_C172_PRE_LEN) - 1) << DSP2_GAMMA_C172_PRE_POS) -#define DSP2_GAMMA_C172_PRE_UMSK (~(((1U << DSP2_GAMMA_C172_PRE_LEN) - 1) << DSP2_GAMMA_C172_PRE_POS)) -#define DSP2_GAMMA_C173_PRE DSP2_GAMMA_C173_PRE -#define DSP2_GAMMA_C173_PRE_POS (8U) -#define DSP2_GAMMA_C173_PRE_LEN (8U) -#define DSP2_GAMMA_C173_PRE_MSK (((1U << DSP2_GAMMA_C173_PRE_LEN) - 1) << DSP2_GAMMA_C173_PRE_POS) -#define DSP2_GAMMA_C173_PRE_UMSK (~(((1U << DSP2_GAMMA_C173_PRE_LEN) - 1) << DSP2_GAMMA_C173_PRE_POS)) -#define DSP2_GAMMA_C174_PRE DSP2_GAMMA_C174_PRE -#define DSP2_GAMMA_C174_PRE_POS (16U) -#define DSP2_GAMMA_C174_PRE_LEN (8U) -#define DSP2_GAMMA_C174_PRE_MSK (((1U << DSP2_GAMMA_C174_PRE_LEN) - 1) << DSP2_GAMMA_C174_PRE_POS) -#define DSP2_GAMMA_C174_PRE_UMSK (~(((1U << DSP2_GAMMA_C174_PRE_LEN) - 1) << DSP2_GAMMA_C174_PRE_POS)) -#define DSP2_GAMMA_C175_PRE DSP2_GAMMA_C175_PRE -#define DSP2_GAMMA_C175_PRE_POS (24U) -#define DSP2_GAMMA_C175_PRE_LEN (8U) -#define DSP2_GAMMA_C175_PRE_MSK (((1U << DSP2_GAMMA_C175_PRE_LEN) - 1) << DSP2_GAMMA_C175_PRE_POS) -#define DSP2_GAMMA_C175_PRE_UMSK (~(((1U << DSP2_GAMMA_C175_PRE_LEN) - 1) << DSP2_GAMMA_C175_PRE_POS)) - -/* 0x7B0 : GAMMA_CRUVE_45 */ -#define DSP2_GAMMA_GAMMA_CRUVE_45_OFFSET (0x7B0) -#define DSP2_GAMMA_C176_PRE DSP2_GAMMA_C176_PRE -#define DSP2_GAMMA_C176_PRE_POS (0U) -#define DSP2_GAMMA_C176_PRE_LEN (8U) -#define DSP2_GAMMA_C176_PRE_MSK (((1U << DSP2_GAMMA_C176_PRE_LEN) - 1) << DSP2_GAMMA_C176_PRE_POS) -#define DSP2_GAMMA_C176_PRE_UMSK (~(((1U << DSP2_GAMMA_C176_PRE_LEN) - 1) << DSP2_GAMMA_C176_PRE_POS)) -#define DSP2_GAMMA_C177_PRE DSP2_GAMMA_C177_PRE -#define DSP2_GAMMA_C177_PRE_POS (8U) -#define DSP2_GAMMA_C177_PRE_LEN (8U) -#define DSP2_GAMMA_C177_PRE_MSK (((1U << DSP2_GAMMA_C177_PRE_LEN) - 1) << DSP2_GAMMA_C177_PRE_POS) -#define DSP2_GAMMA_C177_PRE_UMSK (~(((1U << DSP2_GAMMA_C177_PRE_LEN) - 1) << DSP2_GAMMA_C177_PRE_POS)) -#define DSP2_GAMMA_C178_PRE DSP2_GAMMA_C178_PRE -#define DSP2_GAMMA_C178_PRE_POS (16U) -#define DSP2_GAMMA_C178_PRE_LEN (8U) -#define DSP2_GAMMA_C178_PRE_MSK (((1U << DSP2_GAMMA_C178_PRE_LEN) - 1) << DSP2_GAMMA_C178_PRE_POS) -#define DSP2_GAMMA_C178_PRE_UMSK (~(((1U << DSP2_GAMMA_C178_PRE_LEN) - 1) << DSP2_GAMMA_C178_PRE_POS)) -#define DSP2_GAMMA_C179_PRE DSP2_GAMMA_C179_PRE -#define DSP2_GAMMA_C179_PRE_POS (24U) -#define DSP2_GAMMA_C179_PRE_LEN (8U) -#define DSP2_GAMMA_C179_PRE_MSK (((1U << DSP2_GAMMA_C179_PRE_LEN) - 1) << DSP2_GAMMA_C179_PRE_POS) -#define DSP2_GAMMA_C179_PRE_UMSK (~(((1U << DSP2_GAMMA_C179_PRE_LEN) - 1) << DSP2_GAMMA_C179_PRE_POS)) - -/* 0x7B4 : GAMMA_CRUVE_46 */ -#define DSP2_GAMMA_GAMMA_CRUVE_46_OFFSET (0x7B4) -#define DSP2_GAMMA_C180_PRE DSP2_GAMMA_C180_PRE -#define DSP2_GAMMA_C180_PRE_POS (0U) -#define DSP2_GAMMA_C180_PRE_LEN (8U) -#define DSP2_GAMMA_C180_PRE_MSK (((1U << DSP2_GAMMA_C180_PRE_LEN) - 1) << DSP2_GAMMA_C180_PRE_POS) -#define DSP2_GAMMA_C180_PRE_UMSK (~(((1U << DSP2_GAMMA_C180_PRE_LEN) - 1) << DSP2_GAMMA_C180_PRE_POS)) -#define DSP2_GAMMA_C181_PRE DSP2_GAMMA_C181_PRE -#define DSP2_GAMMA_C181_PRE_POS (8U) -#define DSP2_GAMMA_C181_PRE_LEN (8U) -#define DSP2_GAMMA_C181_PRE_MSK (((1U << DSP2_GAMMA_C181_PRE_LEN) - 1) << DSP2_GAMMA_C181_PRE_POS) -#define DSP2_GAMMA_C181_PRE_UMSK (~(((1U << DSP2_GAMMA_C181_PRE_LEN) - 1) << DSP2_GAMMA_C181_PRE_POS)) -#define DSP2_GAMMA_C182_PRE DSP2_GAMMA_C182_PRE -#define DSP2_GAMMA_C182_PRE_POS (16U) -#define DSP2_GAMMA_C182_PRE_LEN (8U) -#define DSP2_GAMMA_C182_PRE_MSK (((1U << DSP2_GAMMA_C182_PRE_LEN) - 1) << DSP2_GAMMA_C182_PRE_POS) -#define DSP2_GAMMA_C182_PRE_UMSK (~(((1U << DSP2_GAMMA_C182_PRE_LEN) - 1) << DSP2_GAMMA_C182_PRE_POS)) -#define DSP2_GAMMA_C183_PRE DSP2_GAMMA_C183_PRE -#define DSP2_GAMMA_C183_PRE_POS (24U) -#define DSP2_GAMMA_C183_PRE_LEN (8U) -#define DSP2_GAMMA_C183_PRE_MSK (((1U << DSP2_GAMMA_C183_PRE_LEN) - 1) << DSP2_GAMMA_C183_PRE_POS) -#define DSP2_GAMMA_C183_PRE_UMSK (~(((1U << DSP2_GAMMA_C183_PRE_LEN) - 1) << DSP2_GAMMA_C183_PRE_POS)) - -/* 0x7B8 : GAMMA_CRUVE_47 */ -#define DSP2_GAMMA_GAMMA_CRUVE_47_OFFSET (0x7B8) -#define DSP2_GAMMA_C184_PRE DSP2_GAMMA_C184_PRE -#define DSP2_GAMMA_C184_PRE_POS (0U) -#define DSP2_GAMMA_C184_PRE_LEN (8U) -#define DSP2_GAMMA_C184_PRE_MSK (((1U << DSP2_GAMMA_C184_PRE_LEN) - 1) << DSP2_GAMMA_C184_PRE_POS) -#define DSP2_GAMMA_C184_PRE_UMSK (~(((1U << DSP2_GAMMA_C184_PRE_LEN) - 1) << DSP2_GAMMA_C184_PRE_POS)) -#define DSP2_GAMMA_C185_PRE DSP2_GAMMA_C185_PRE -#define DSP2_GAMMA_C185_PRE_POS (8U) -#define DSP2_GAMMA_C185_PRE_LEN (8U) -#define DSP2_GAMMA_C185_PRE_MSK (((1U << DSP2_GAMMA_C185_PRE_LEN) - 1) << DSP2_GAMMA_C185_PRE_POS) -#define DSP2_GAMMA_C185_PRE_UMSK (~(((1U << DSP2_GAMMA_C185_PRE_LEN) - 1) << DSP2_GAMMA_C185_PRE_POS)) -#define DSP2_GAMMA_C186_PRE DSP2_GAMMA_C186_PRE -#define DSP2_GAMMA_C186_PRE_POS (16U) -#define DSP2_GAMMA_C186_PRE_LEN (8U) -#define DSP2_GAMMA_C186_PRE_MSK (((1U << DSP2_GAMMA_C186_PRE_LEN) - 1) << DSP2_GAMMA_C186_PRE_POS) -#define DSP2_GAMMA_C186_PRE_UMSK (~(((1U << DSP2_GAMMA_C186_PRE_LEN) - 1) << DSP2_GAMMA_C186_PRE_POS)) -#define DSP2_GAMMA_C187_PRE DSP2_GAMMA_C187_PRE -#define DSP2_GAMMA_C187_PRE_POS (24U) -#define DSP2_GAMMA_C187_PRE_LEN (8U) -#define DSP2_GAMMA_C187_PRE_MSK (((1U << DSP2_GAMMA_C187_PRE_LEN) - 1) << DSP2_GAMMA_C187_PRE_POS) -#define DSP2_GAMMA_C187_PRE_UMSK (~(((1U << DSP2_GAMMA_C187_PRE_LEN) - 1) << DSP2_GAMMA_C187_PRE_POS)) - -/* 0x7BC : GAMMA_CRUVE_48 */ -#define DSP2_GAMMA_GAMMA_CRUVE_48_OFFSET (0x7BC) -#define DSP2_GAMMA_C188_PRE DSP2_GAMMA_C188_PRE -#define DSP2_GAMMA_C188_PRE_POS (0U) -#define DSP2_GAMMA_C188_PRE_LEN (8U) -#define DSP2_GAMMA_C188_PRE_MSK (((1U << DSP2_GAMMA_C188_PRE_LEN) - 1) << DSP2_GAMMA_C188_PRE_POS) -#define DSP2_GAMMA_C188_PRE_UMSK (~(((1U << DSP2_GAMMA_C188_PRE_LEN) - 1) << DSP2_GAMMA_C188_PRE_POS)) -#define DSP2_GAMMA_C189_PRE DSP2_GAMMA_C189_PRE -#define DSP2_GAMMA_C189_PRE_POS (8U) -#define DSP2_GAMMA_C189_PRE_LEN (8U) -#define DSP2_GAMMA_C189_PRE_MSK (((1U << DSP2_GAMMA_C189_PRE_LEN) - 1) << DSP2_GAMMA_C189_PRE_POS) -#define DSP2_GAMMA_C189_PRE_UMSK (~(((1U << DSP2_GAMMA_C189_PRE_LEN) - 1) << DSP2_GAMMA_C189_PRE_POS)) -#define DSP2_GAMMA_C190_PRE DSP2_GAMMA_C190_PRE -#define DSP2_GAMMA_C190_PRE_POS (16U) -#define DSP2_GAMMA_C190_PRE_LEN (8U) -#define DSP2_GAMMA_C190_PRE_MSK (((1U << DSP2_GAMMA_C190_PRE_LEN) - 1) << DSP2_GAMMA_C190_PRE_POS) -#define DSP2_GAMMA_C190_PRE_UMSK (~(((1U << DSP2_GAMMA_C190_PRE_LEN) - 1) << DSP2_GAMMA_C190_PRE_POS)) -#define DSP2_GAMMA_C191_PRE DSP2_GAMMA_C191_PRE -#define DSP2_GAMMA_C191_PRE_POS (24U) -#define DSP2_GAMMA_C191_PRE_LEN (8U) -#define DSP2_GAMMA_C191_PRE_MSK (((1U << DSP2_GAMMA_C191_PRE_LEN) - 1) << DSP2_GAMMA_C191_PRE_POS) -#define DSP2_GAMMA_C191_PRE_UMSK (~(((1U << DSP2_GAMMA_C191_PRE_LEN) - 1) << DSP2_GAMMA_C191_PRE_POS)) - -/* 0x7C0 : GAMMA_CRUVE_49 */ -#define DSP2_GAMMA_GAMMA_CRUVE_49_OFFSET (0x7C0) -#define DSP2_GAMMA_C192_PRE DSP2_GAMMA_C192_PRE -#define DSP2_GAMMA_C192_PRE_POS (0U) -#define DSP2_GAMMA_C192_PRE_LEN (8U) -#define DSP2_GAMMA_C192_PRE_MSK (((1U << DSP2_GAMMA_C192_PRE_LEN) - 1) << DSP2_GAMMA_C192_PRE_POS) -#define DSP2_GAMMA_C192_PRE_UMSK (~(((1U << DSP2_GAMMA_C192_PRE_LEN) - 1) << DSP2_GAMMA_C192_PRE_POS)) -#define DSP2_GAMMA_C193_PRE DSP2_GAMMA_C193_PRE -#define DSP2_GAMMA_C193_PRE_POS (8U) -#define DSP2_GAMMA_C193_PRE_LEN (8U) -#define DSP2_GAMMA_C193_PRE_MSK (((1U << DSP2_GAMMA_C193_PRE_LEN) - 1) << DSP2_GAMMA_C193_PRE_POS) -#define DSP2_GAMMA_C193_PRE_UMSK (~(((1U << DSP2_GAMMA_C193_PRE_LEN) - 1) << DSP2_GAMMA_C193_PRE_POS)) -#define DSP2_GAMMA_C194_PRE DSP2_GAMMA_C194_PRE -#define DSP2_GAMMA_C194_PRE_POS (16U) -#define DSP2_GAMMA_C194_PRE_LEN (8U) -#define DSP2_GAMMA_C194_PRE_MSK (((1U << DSP2_GAMMA_C194_PRE_LEN) - 1) << DSP2_GAMMA_C194_PRE_POS) -#define DSP2_GAMMA_C194_PRE_UMSK (~(((1U << DSP2_GAMMA_C194_PRE_LEN) - 1) << DSP2_GAMMA_C194_PRE_POS)) -#define DSP2_GAMMA_C195_PRE DSP2_GAMMA_C195_PRE -#define DSP2_GAMMA_C195_PRE_POS (24U) -#define DSP2_GAMMA_C195_PRE_LEN (8U) -#define DSP2_GAMMA_C195_PRE_MSK (((1U << DSP2_GAMMA_C195_PRE_LEN) - 1) << DSP2_GAMMA_C195_PRE_POS) -#define DSP2_GAMMA_C195_PRE_UMSK (~(((1U << DSP2_GAMMA_C195_PRE_LEN) - 1) << DSP2_GAMMA_C195_PRE_POS)) - -/* 0x7C4 : GAMMA_CRUVE_50 */ -#define DSP2_GAMMA_GAMMA_CRUVE_50_OFFSET (0x7C4) -#define DSP2_GAMMA_C196_PRE DSP2_GAMMA_C196_PRE -#define DSP2_GAMMA_C196_PRE_POS (0U) -#define DSP2_GAMMA_C196_PRE_LEN (8U) -#define DSP2_GAMMA_C196_PRE_MSK (((1U << DSP2_GAMMA_C196_PRE_LEN) - 1) << DSP2_GAMMA_C196_PRE_POS) -#define DSP2_GAMMA_C196_PRE_UMSK (~(((1U << DSP2_GAMMA_C196_PRE_LEN) - 1) << DSP2_GAMMA_C196_PRE_POS)) -#define DSP2_GAMMA_C197_PRE DSP2_GAMMA_C197_PRE -#define DSP2_GAMMA_C197_PRE_POS (8U) -#define DSP2_GAMMA_C197_PRE_LEN (8U) -#define DSP2_GAMMA_C197_PRE_MSK (((1U << DSP2_GAMMA_C197_PRE_LEN) - 1) << DSP2_GAMMA_C197_PRE_POS) -#define DSP2_GAMMA_C197_PRE_UMSK (~(((1U << DSP2_GAMMA_C197_PRE_LEN) - 1) << DSP2_GAMMA_C197_PRE_POS)) -#define DSP2_GAMMA_C198_PRE DSP2_GAMMA_C198_PRE -#define DSP2_GAMMA_C198_PRE_POS (16U) -#define DSP2_GAMMA_C198_PRE_LEN (8U) -#define DSP2_GAMMA_C198_PRE_MSK (((1U << DSP2_GAMMA_C198_PRE_LEN) - 1) << DSP2_GAMMA_C198_PRE_POS) -#define DSP2_GAMMA_C198_PRE_UMSK (~(((1U << DSP2_GAMMA_C198_PRE_LEN) - 1) << DSP2_GAMMA_C198_PRE_POS)) -#define DSP2_GAMMA_C199_PRE DSP2_GAMMA_C199_PRE -#define DSP2_GAMMA_C199_PRE_POS (24U) -#define DSP2_GAMMA_C199_PRE_LEN (8U) -#define DSP2_GAMMA_C199_PRE_MSK (((1U << DSP2_GAMMA_C199_PRE_LEN) - 1) << DSP2_GAMMA_C199_PRE_POS) -#define DSP2_GAMMA_C199_PRE_UMSK (~(((1U << DSP2_GAMMA_C199_PRE_LEN) - 1) << DSP2_GAMMA_C199_PRE_POS)) - -/* 0x7C8 : GAMMA_CRUVE_51 */ -#define DSP2_GAMMA_GAMMA_CRUVE_51_OFFSET (0x7C8) -#define DSP2_GAMMA_C200_PRE DSP2_GAMMA_C200_PRE -#define DSP2_GAMMA_C200_PRE_POS (0U) -#define DSP2_GAMMA_C200_PRE_LEN (8U) -#define DSP2_GAMMA_C200_PRE_MSK (((1U << DSP2_GAMMA_C200_PRE_LEN) - 1) << DSP2_GAMMA_C200_PRE_POS) -#define DSP2_GAMMA_C200_PRE_UMSK (~(((1U << DSP2_GAMMA_C200_PRE_LEN) - 1) << DSP2_GAMMA_C200_PRE_POS)) -#define DSP2_GAMMA_C201_PRE DSP2_GAMMA_C201_PRE -#define DSP2_GAMMA_C201_PRE_POS (8U) -#define DSP2_GAMMA_C201_PRE_LEN (8U) -#define DSP2_GAMMA_C201_PRE_MSK (((1U << DSP2_GAMMA_C201_PRE_LEN) - 1) << DSP2_GAMMA_C201_PRE_POS) -#define DSP2_GAMMA_C201_PRE_UMSK (~(((1U << DSP2_GAMMA_C201_PRE_LEN) - 1) << DSP2_GAMMA_C201_PRE_POS)) -#define DSP2_GAMMA_C202_PRE DSP2_GAMMA_C202_PRE -#define DSP2_GAMMA_C202_PRE_POS (16U) -#define DSP2_GAMMA_C202_PRE_LEN (8U) -#define DSP2_GAMMA_C202_PRE_MSK (((1U << DSP2_GAMMA_C202_PRE_LEN) - 1) << DSP2_GAMMA_C202_PRE_POS) -#define DSP2_GAMMA_C202_PRE_UMSK (~(((1U << DSP2_GAMMA_C202_PRE_LEN) - 1) << DSP2_GAMMA_C202_PRE_POS)) -#define DSP2_GAMMA_C203_PRE DSP2_GAMMA_C203_PRE -#define DSP2_GAMMA_C203_PRE_POS (24U) -#define DSP2_GAMMA_C203_PRE_LEN (8U) -#define DSP2_GAMMA_C203_PRE_MSK (((1U << DSP2_GAMMA_C203_PRE_LEN) - 1) << DSP2_GAMMA_C203_PRE_POS) -#define DSP2_GAMMA_C203_PRE_UMSK (~(((1U << DSP2_GAMMA_C203_PRE_LEN) - 1) << DSP2_GAMMA_C203_PRE_POS)) - -/* 0x7CC : GAMMA_CRUVE_52 */ -#define DSP2_GAMMA_GAMMA_CRUVE_52_OFFSET (0x7CC) -#define DSP2_GAMMA_C204_PRE DSP2_GAMMA_C204_PRE -#define DSP2_GAMMA_C204_PRE_POS (0U) -#define DSP2_GAMMA_C204_PRE_LEN (8U) -#define DSP2_GAMMA_C204_PRE_MSK (((1U << DSP2_GAMMA_C204_PRE_LEN) - 1) << DSP2_GAMMA_C204_PRE_POS) -#define DSP2_GAMMA_C204_PRE_UMSK (~(((1U << DSP2_GAMMA_C204_PRE_LEN) - 1) << DSP2_GAMMA_C204_PRE_POS)) -#define DSP2_GAMMA_C205_PRE DSP2_GAMMA_C205_PRE -#define DSP2_GAMMA_C205_PRE_POS (8U) -#define DSP2_GAMMA_C205_PRE_LEN (8U) -#define DSP2_GAMMA_C205_PRE_MSK (((1U << DSP2_GAMMA_C205_PRE_LEN) - 1) << DSP2_GAMMA_C205_PRE_POS) -#define DSP2_GAMMA_C205_PRE_UMSK (~(((1U << DSP2_GAMMA_C205_PRE_LEN) - 1) << DSP2_GAMMA_C205_PRE_POS)) -#define DSP2_GAMMA_C206_PRE DSP2_GAMMA_C206_PRE -#define DSP2_GAMMA_C206_PRE_POS (16U) -#define DSP2_GAMMA_C206_PRE_LEN (8U) -#define DSP2_GAMMA_C206_PRE_MSK (((1U << DSP2_GAMMA_C206_PRE_LEN) - 1) << DSP2_GAMMA_C206_PRE_POS) -#define DSP2_GAMMA_C206_PRE_UMSK (~(((1U << DSP2_GAMMA_C206_PRE_LEN) - 1) << DSP2_GAMMA_C206_PRE_POS)) -#define DSP2_GAMMA_C207_PRE DSP2_GAMMA_C207_PRE -#define DSP2_GAMMA_C207_PRE_POS (24U) -#define DSP2_GAMMA_C207_PRE_LEN (8U) -#define DSP2_GAMMA_C207_PRE_MSK (((1U << DSP2_GAMMA_C207_PRE_LEN) - 1) << DSP2_GAMMA_C207_PRE_POS) -#define DSP2_GAMMA_C207_PRE_UMSK (~(((1U << DSP2_GAMMA_C207_PRE_LEN) - 1) << DSP2_GAMMA_C207_PRE_POS)) - -/* 0x7D0 : GAMMA_CRUVE_53 */ -#define DSP2_GAMMA_GAMMA_CRUVE_53_OFFSET (0x7D0) -#define DSP2_GAMMA_C208_PRE DSP2_GAMMA_C208_PRE -#define DSP2_GAMMA_C208_PRE_POS (0U) -#define DSP2_GAMMA_C208_PRE_LEN (8U) -#define DSP2_GAMMA_C208_PRE_MSK (((1U << DSP2_GAMMA_C208_PRE_LEN) - 1) << DSP2_GAMMA_C208_PRE_POS) -#define DSP2_GAMMA_C208_PRE_UMSK (~(((1U << DSP2_GAMMA_C208_PRE_LEN) - 1) << DSP2_GAMMA_C208_PRE_POS)) -#define DSP2_GAMMA_C209_PRE DSP2_GAMMA_C209_PRE -#define DSP2_GAMMA_C209_PRE_POS (8U) -#define DSP2_GAMMA_C209_PRE_LEN (8U) -#define DSP2_GAMMA_C209_PRE_MSK (((1U << DSP2_GAMMA_C209_PRE_LEN) - 1) << DSP2_GAMMA_C209_PRE_POS) -#define DSP2_GAMMA_C209_PRE_UMSK (~(((1U << DSP2_GAMMA_C209_PRE_LEN) - 1) << DSP2_GAMMA_C209_PRE_POS)) -#define DSP2_GAMMA_C210_PRE DSP2_GAMMA_C210_PRE -#define DSP2_GAMMA_C210_PRE_POS (16U) -#define DSP2_GAMMA_C210_PRE_LEN (8U) -#define DSP2_GAMMA_C210_PRE_MSK (((1U << DSP2_GAMMA_C210_PRE_LEN) - 1) << DSP2_GAMMA_C210_PRE_POS) -#define DSP2_GAMMA_C210_PRE_UMSK (~(((1U << DSP2_GAMMA_C210_PRE_LEN) - 1) << DSP2_GAMMA_C210_PRE_POS)) -#define DSP2_GAMMA_C211_PRE DSP2_GAMMA_C211_PRE -#define DSP2_GAMMA_C211_PRE_POS (24U) -#define DSP2_GAMMA_C211_PRE_LEN (8U) -#define DSP2_GAMMA_C211_PRE_MSK (((1U << DSP2_GAMMA_C211_PRE_LEN) - 1) << DSP2_GAMMA_C211_PRE_POS) -#define DSP2_GAMMA_C211_PRE_UMSK (~(((1U << DSP2_GAMMA_C211_PRE_LEN) - 1) << DSP2_GAMMA_C211_PRE_POS)) - -/* 0x7D4 : GAMMA_CRUVE_54 */ -#define DSP2_GAMMA_GAMMA_CRUVE_54_OFFSET (0x7D4) -#define DSP2_GAMMA_C212_PRE DSP2_GAMMA_C212_PRE -#define DSP2_GAMMA_C212_PRE_POS (0U) -#define DSP2_GAMMA_C212_PRE_LEN (8U) -#define DSP2_GAMMA_C212_PRE_MSK (((1U << DSP2_GAMMA_C212_PRE_LEN) - 1) << DSP2_GAMMA_C212_PRE_POS) -#define DSP2_GAMMA_C212_PRE_UMSK (~(((1U << DSP2_GAMMA_C212_PRE_LEN) - 1) << DSP2_GAMMA_C212_PRE_POS)) -#define DSP2_GAMMA_C213_PRE DSP2_GAMMA_C213_PRE -#define DSP2_GAMMA_C213_PRE_POS (8U) -#define DSP2_GAMMA_C213_PRE_LEN (8U) -#define DSP2_GAMMA_C213_PRE_MSK (((1U << DSP2_GAMMA_C213_PRE_LEN) - 1) << DSP2_GAMMA_C213_PRE_POS) -#define DSP2_GAMMA_C213_PRE_UMSK (~(((1U << DSP2_GAMMA_C213_PRE_LEN) - 1) << DSP2_GAMMA_C213_PRE_POS)) -#define DSP2_GAMMA_C214_PRE DSP2_GAMMA_C214_PRE -#define DSP2_GAMMA_C214_PRE_POS (16U) -#define DSP2_GAMMA_C214_PRE_LEN (8U) -#define DSP2_GAMMA_C214_PRE_MSK (((1U << DSP2_GAMMA_C214_PRE_LEN) - 1) << DSP2_GAMMA_C214_PRE_POS) -#define DSP2_GAMMA_C214_PRE_UMSK (~(((1U << DSP2_GAMMA_C214_PRE_LEN) - 1) << DSP2_GAMMA_C214_PRE_POS)) -#define DSP2_GAMMA_C215_PRE DSP2_GAMMA_C215_PRE -#define DSP2_GAMMA_C215_PRE_POS (24U) -#define DSP2_GAMMA_C215_PRE_LEN (8U) -#define DSP2_GAMMA_C215_PRE_MSK (((1U << DSP2_GAMMA_C215_PRE_LEN) - 1) << DSP2_GAMMA_C215_PRE_POS) -#define DSP2_GAMMA_C215_PRE_UMSK (~(((1U << DSP2_GAMMA_C215_PRE_LEN) - 1) << DSP2_GAMMA_C215_PRE_POS)) - -/* 0x7D8 : GAMMA_CRUVE_55 */ -#define DSP2_GAMMA_GAMMA_CRUVE_55_OFFSET (0x7D8) -#define DSP2_GAMMA_C216_PRE DSP2_GAMMA_C216_PRE -#define DSP2_GAMMA_C216_PRE_POS (0U) -#define DSP2_GAMMA_C216_PRE_LEN (8U) -#define DSP2_GAMMA_C216_PRE_MSK (((1U << DSP2_GAMMA_C216_PRE_LEN) - 1) << DSP2_GAMMA_C216_PRE_POS) -#define DSP2_GAMMA_C216_PRE_UMSK (~(((1U << DSP2_GAMMA_C216_PRE_LEN) - 1) << DSP2_GAMMA_C216_PRE_POS)) -#define DSP2_GAMMA_C217_PRE DSP2_GAMMA_C217_PRE -#define DSP2_GAMMA_C217_PRE_POS (8U) -#define DSP2_GAMMA_C217_PRE_LEN (8U) -#define DSP2_GAMMA_C217_PRE_MSK (((1U << DSP2_GAMMA_C217_PRE_LEN) - 1) << DSP2_GAMMA_C217_PRE_POS) -#define DSP2_GAMMA_C217_PRE_UMSK (~(((1U << DSP2_GAMMA_C217_PRE_LEN) - 1) << DSP2_GAMMA_C217_PRE_POS)) -#define DSP2_GAMMA_C218_PRE DSP2_GAMMA_C218_PRE -#define DSP2_GAMMA_C218_PRE_POS (16U) -#define DSP2_GAMMA_C218_PRE_LEN (8U) -#define DSP2_GAMMA_C218_PRE_MSK (((1U << DSP2_GAMMA_C218_PRE_LEN) - 1) << DSP2_GAMMA_C218_PRE_POS) -#define DSP2_GAMMA_C218_PRE_UMSK (~(((1U << DSP2_GAMMA_C218_PRE_LEN) - 1) << DSP2_GAMMA_C218_PRE_POS)) -#define DSP2_GAMMA_C219_PRE DSP2_GAMMA_C219_PRE -#define DSP2_GAMMA_C219_PRE_POS (24U) -#define DSP2_GAMMA_C219_PRE_LEN (8U) -#define DSP2_GAMMA_C219_PRE_MSK (((1U << DSP2_GAMMA_C219_PRE_LEN) - 1) << DSP2_GAMMA_C219_PRE_POS) -#define DSP2_GAMMA_C219_PRE_UMSK (~(((1U << DSP2_GAMMA_C219_PRE_LEN) - 1) << DSP2_GAMMA_C219_PRE_POS)) - -/* 0x7DC : GAMMA_CRUVE_56 */ -#define DSP2_GAMMA_GAMMA_CRUVE_56_OFFSET (0x7DC) -#define DSP2_GAMMA_C220_PRE DSP2_GAMMA_C220_PRE -#define DSP2_GAMMA_C220_PRE_POS (0U) -#define DSP2_GAMMA_C220_PRE_LEN (8U) -#define DSP2_GAMMA_C220_PRE_MSK (((1U << DSP2_GAMMA_C220_PRE_LEN) - 1) << DSP2_GAMMA_C220_PRE_POS) -#define DSP2_GAMMA_C220_PRE_UMSK (~(((1U << DSP2_GAMMA_C220_PRE_LEN) - 1) << DSP2_GAMMA_C220_PRE_POS)) -#define DSP2_GAMMA_C221_PRE DSP2_GAMMA_C221_PRE -#define DSP2_GAMMA_C221_PRE_POS (8U) -#define DSP2_GAMMA_C221_PRE_LEN (8U) -#define DSP2_GAMMA_C221_PRE_MSK (((1U << DSP2_GAMMA_C221_PRE_LEN) - 1) << DSP2_GAMMA_C221_PRE_POS) -#define DSP2_GAMMA_C221_PRE_UMSK (~(((1U << DSP2_GAMMA_C221_PRE_LEN) - 1) << DSP2_GAMMA_C221_PRE_POS)) -#define DSP2_GAMMA_C222_PRE DSP2_GAMMA_C222_PRE -#define DSP2_GAMMA_C222_PRE_POS (16U) -#define DSP2_GAMMA_C222_PRE_LEN (8U) -#define DSP2_GAMMA_C222_PRE_MSK (((1U << DSP2_GAMMA_C222_PRE_LEN) - 1) << DSP2_GAMMA_C222_PRE_POS) -#define DSP2_GAMMA_C222_PRE_UMSK (~(((1U << DSP2_GAMMA_C222_PRE_LEN) - 1) << DSP2_GAMMA_C222_PRE_POS)) -#define DSP2_GAMMA_C223_PRE DSP2_GAMMA_C223_PRE -#define DSP2_GAMMA_C223_PRE_POS (24U) -#define DSP2_GAMMA_C223_PRE_LEN (8U) -#define DSP2_GAMMA_C223_PRE_MSK (((1U << DSP2_GAMMA_C223_PRE_LEN) - 1) << DSP2_GAMMA_C223_PRE_POS) -#define DSP2_GAMMA_C223_PRE_UMSK (~(((1U << DSP2_GAMMA_C223_PRE_LEN) - 1) << DSP2_GAMMA_C223_PRE_POS)) - -/* 0x7E0 : GAMMA_CRUVE_57 */ -#define DSP2_GAMMA_GAMMA_CRUVE_57_OFFSET (0x7E0) -#define DSP2_GAMMA_C224_PRE DSP2_GAMMA_C224_PRE -#define DSP2_GAMMA_C224_PRE_POS (0U) -#define DSP2_GAMMA_C224_PRE_LEN (8U) -#define DSP2_GAMMA_C224_PRE_MSK (((1U << DSP2_GAMMA_C224_PRE_LEN) - 1) << DSP2_GAMMA_C224_PRE_POS) -#define DSP2_GAMMA_C224_PRE_UMSK (~(((1U << DSP2_GAMMA_C224_PRE_LEN) - 1) << DSP2_GAMMA_C224_PRE_POS)) -#define DSP2_GAMMA_C225_PRE DSP2_GAMMA_C225_PRE -#define DSP2_GAMMA_C225_PRE_POS (8U) -#define DSP2_GAMMA_C225_PRE_LEN (8U) -#define DSP2_GAMMA_C225_PRE_MSK (((1U << DSP2_GAMMA_C225_PRE_LEN) - 1) << DSP2_GAMMA_C225_PRE_POS) -#define DSP2_GAMMA_C225_PRE_UMSK (~(((1U << DSP2_GAMMA_C225_PRE_LEN) - 1) << DSP2_GAMMA_C225_PRE_POS)) -#define DSP2_GAMMA_C226_PRE DSP2_GAMMA_C226_PRE -#define DSP2_GAMMA_C226_PRE_POS (16U) -#define DSP2_GAMMA_C226_PRE_LEN (8U) -#define DSP2_GAMMA_C226_PRE_MSK (((1U << DSP2_GAMMA_C226_PRE_LEN) - 1) << DSP2_GAMMA_C226_PRE_POS) -#define DSP2_GAMMA_C226_PRE_UMSK (~(((1U << DSP2_GAMMA_C226_PRE_LEN) - 1) << DSP2_GAMMA_C226_PRE_POS)) -#define DSP2_GAMMA_C227_PRE DSP2_GAMMA_C227_PRE -#define DSP2_GAMMA_C227_PRE_POS (24U) -#define DSP2_GAMMA_C227_PRE_LEN (8U) -#define DSP2_GAMMA_C227_PRE_MSK (((1U << DSP2_GAMMA_C227_PRE_LEN) - 1) << DSP2_GAMMA_C227_PRE_POS) -#define DSP2_GAMMA_C227_PRE_UMSK (~(((1U << DSP2_GAMMA_C227_PRE_LEN) - 1) << DSP2_GAMMA_C227_PRE_POS)) - -/* 0x7E4 : GAMMA_CRUVE_58 */ -#define DSP2_GAMMA_GAMMA_CRUVE_58_OFFSET (0x7E4) -#define DSP2_GAMMA_C228_PRE DSP2_GAMMA_C228_PRE -#define DSP2_GAMMA_C228_PRE_POS (0U) -#define DSP2_GAMMA_C228_PRE_LEN (8U) -#define DSP2_GAMMA_C228_PRE_MSK (((1U << DSP2_GAMMA_C228_PRE_LEN) - 1) << DSP2_GAMMA_C228_PRE_POS) -#define DSP2_GAMMA_C228_PRE_UMSK (~(((1U << DSP2_GAMMA_C228_PRE_LEN) - 1) << DSP2_GAMMA_C228_PRE_POS)) -#define DSP2_GAMMA_C229_PRE DSP2_GAMMA_C229_PRE -#define DSP2_GAMMA_C229_PRE_POS (8U) -#define DSP2_GAMMA_C229_PRE_LEN (8U) -#define DSP2_GAMMA_C229_PRE_MSK (((1U << DSP2_GAMMA_C229_PRE_LEN) - 1) << DSP2_GAMMA_C229_PRE_POS) -#define DSP2_GAMMA_C229_PRE_UMSK (~(((1U << DSP2_GAMMA_C229_PRE_LEN) - 1) << DSP2_GAMMA_C229_PRE_POS)) -#define DSP2_GAMMA_C230_PRE DSP2_GAMMA_C230_PRE -#define DSP2_GAMMA_C230_PRE_POS (16U) -#define DSP2_GAMMA_C230_PRE_LEN (8U) -#define DSP2_GAMMA_C230_PRE_MSK (((1U << DSP2_GAMMA_C230_PRE_LEN) - 1) << DSP2_GAMMA_C230_PRE_POS) -#define DSP2_GAMMA_C230_PRE_UMSK (~(((1U << DSP2_GAMMA_C230_PRE_LEN) - 1) << DSP2_GAMMA_C230_PRE_POS)) -#define DSP2_GAMMA_C231_PRE DSP2_GAMMA_C231_PRE -#define DSP2_GAMMA_C231_PRE_POS (24U) -#define DSP2_GAMMA_C231_PRE_LEN (8U) -#define DSP2_GAMMA_C231_PRE_MSK (((1U << DSP2_GAMMA_C231_PRE_LEN) - 1) << DSP2_GAMMA_C231_PRE_POS) -#define DSP2_GAMMA_C231_PRE_UMSK (~(((1U << DSP2_GAMMA_C231_PRE_LEN) - 1) << DSP2_GAMMA_C231_PRE_POS)) - -/* 0x7E8 : GAMMA_CRUVE_59 */ -#define DSP2_GAMMA_GAMMA_CRUVE_59_OFFSET (0x7E8) -#define DSP2_GAMMA_C232_PRE DSP2_GAMMA_C232_PRE -#define DSP2_GAMMA_C232_PRE_POS (0U) -#define DSP2_GAMMA_C232_PRE_LEN (8U) -#define DSP2_GAMMA_C232_PRE_MSK (((1U << DSP2_GAMMA_C232_PRE_LEN) - 1) << DSP2_GAMMA_C232_PRE_POS) -#define DSP2_GAMMA_C232_PRE_UMSK (~(((1U << DSP2_GAMMA_C232_PRE_LEN) - 1) << DSP2_GAMMA_C232_PRE_POS)) -#define DSP2_GAMMA_C233_PRE DSP2_GAMMA_C233_PRE -#define DSP2_GAMMA_C233_PRE_POS (8U) -#define DSP2_GAMMA_C233_PRE_LEN (8U) -#define DSP2_GAMMA_C233_PRE_MSK (((1U << DSP2_GAMMA_C233_PRE_LEN) - 1) << DSP2_GAMMA_C233_PRE_POS) -#define DSP2_GAMMA_C233_PRE_UMSK (~(((1U << DSP2_GAMMA_C233_PRE_LEN) - 1) << DSP2_GAMMA_C233_PRE_POS)) -#define DSP2_GAMMA_C234_PRE DSP2_GAMMA_C234_PRE -#define DSP2_GAMMA_C234_PRE_POS (16U) -#define DSP2_GAMMA_C234_PRE_LEN (8U) -#define DSP2_GAMMA_C234_PRE_MSK (((1U << DSP2_GAMMA_C234_PRE_LEN) - 1) << DSP2_GAMMA_C234_PRE_POS) -#define DSP2_GAMMA_C234_PRE_UMSK (~(((1U << DSP2_GAMMA_C234_PRE_LEN) - 1) << DSP2_GAMMA_C234_PRE_POS)) -#define DSP2_GAMMA_C235_PRE DSP2_GAMMA_C235_PRE -#define DSP2_GAMMA_C235_PRE_POS (24U) -#define DSP2_GAMMA_C235_PRE_LEN (8U) -#define DSP2_GAMMA_C235_PRE_MSK (((1U << DSP2_GAMMA_C235_PRE_LEN) - 1) << DSP2_GAMMA_C235_PRE_POS) -#define DSP2_GAMMA_C235_PRE_UMSK (~(((1U << DSP2_GAMMA_C235_PRE_LEN) - 1) << DSP2_GAMMA_C235_PRE_POS)) - -/* 0x7EC : GAMMA_CRUVE_60 */ -#define DSP2_GAMMA_GAMMA_CRUVE_60_OFFSET (0x7EC) -#define DSP2_GAMMA_C236_PRE DSP2_GAMMA_C236_PRE -#define DSP2_GAMMA_C236_PRE_POS (0U) -#define DSP2_GAMMA_C236_PRE_LEN (8U) -#define DSP2_GAMMA_C236_PRE_MSK (((1U << DSP2_GAMMA_C236_PRE_LEN) - 1) << DSP2_GAMMA_C236_PRE_POS) -#define DSP2_GAMMA_C236_PRE_UMSK (~(((1U << DSP2_GAMMA_C236_PRE_LEN) - 1) << DSP2_GAMMA_C236_PRE_POS)) -#define DSP2_GAMMA_C237_PRE DSP2_GAMMA_C237_PRE -#define DSP2_GAMMA_C237_PRE_POS (8U) -#define DSP2_GAMMA_C237_PRE_LEN (8U) -#define DSP2_GAMMA_C237_PRE_MSK (((1U << DSP2_GAMMA_C237_PRE_LEN) - 1) << DSP2_GAMMA_C237_PRE_POS) -#define DSP2_GAMMA_C237_PRE_UMSK (~(((1U << DSP2_GAMMA_C237_PRE_LEN) - 1) << DSP2_GAMMA_C237_PRE_POS)) -#define DSP2_GAMMA_C238_PRE DSP2_GAMMA_C238_PRE -#define DSP2_GAMMA_C238_PRE_POS (16U) -#define DSP2_GAMMA_C238_PRE_LEN (8U) -#define DSP2_GAMMA_C238_PRE_MSK (((1U << DSP2_GAMMA_C238_PRE_LEN) - 1) << DSP2_GAMMA_C238_PRE_POS) -#define DSP2_GAMMA_C238_PRE_UMSK (~(((1U << DSP2_GAMMA_C238_PRE_LEN) - 1) << DSP2_GAMMA_C238_PRE_POS)) -#define DSP2_GAMMA_C239_PRE DSP2_GAMMA_C239_PRE -#define DSP2_GAMMA_C239_PRE_POS (24U) -#define DSP2_GAMMA_C239_PRE_LEN (8U) -#define DSP2_GAMMA_C239_PRE_MSK (((1U << DSP2_GAMMA_C239_PRE_LEN) - 1) << DSP2_GAMMA_C239_PRE_POS) -#define DSP2_GAMMA_C239_PRE_UMSK (~(((1U << DSP2_GAMMA_C239_PRE_LEN) - 1) << DSP2_GAMMA_C239_PRE_POS)) - -/* 0x7F0 : GAMMA_CRUVE_61 */ -#define DSP2_GAMMA_GAMMA_CRUVE_61_OFFSET (0x7F0) -#define DSP2_GAMMA_C240_PRE DSP2_GAMMA_C240_PRE -#define DSP2_GAMMA_C240_PRE_POS (0U) -#define DSP2_GAMMA_C240_PRE_LEN (8U) -#define DSP2_GAMMA_C240_PRE_MSK (((1U << DSP2_GAMMA_C240_PRE_LEN) - 1) << DSP2_GAMMA_C240_PRE_POS) -#define DSP2_GAMMA_C240_PRE_UMSK (~(((1U << DSP2_GAMMA_C240_PRE_LEN) - 1) << DSP2_GAMMA_C240_PRE_POS)) -#define DSP2_GAMMA_C241_PRE DSP2_GAMMA_C241_PRE -#define DSP2_GAMMA_C241_PRE_POS (8U) -#define DSP2_GAMMA_C241_PRE_LEN (8U) -#define DSP2_GAMMA_C241_PRE_MSK (((1U << DSP2_GAMMA_C241_PRE_LEN) - 1) << DSP2_GAMMA_C241_PRE_POS) -#define DSP2_GAMMA_C241_PRE_UMSK (~(((1U << DSP2_GAMMA_C241_PRE_LEN) - 1) << DSP2_GAMMA_C241_PRE_POS)) -#define DSP2_GAMMA_C242_PRE DSP2_GAMMA_C242_PRE -#define DSP2_GAMMA_C242_PRE_POS (16U) -#define DSP2_GAMMA_C242_PRE_LEN (8U) -#define DSP2_GAMMA_C242_PRE_MSK (((1U << DSP2_GAMMA_C242_PRE_LEN) - 1) << DSP2_GAMMA_C242_PRE_POS) -#define DSP2_GAMMA_C242_PRE_UMSK (~(((1U << DSP2_GAMMA_C242_PRE_LEN) - 1) << DSP2_GAMMA_C242_PRE_POS)) -#define DSP2_GAMMA_C243_PRE DSP2_GAMMA_C243_PRE -#define DSP2_GAMMA_C243_PRE_POS (24U) -#define DSP2_GAMMA_C243_PRE_LEN (8U) -#define DSP2_GAMMA_C243_PRE_MSK (((1U << DSP2_GAMMA_C243_PRE_LEN) - 1) << DSP2_GAMMA_C243_PRE_POS) -#define DSP2_GAMMA_C243_PRE_UMSK (~(((1U << DSP2_GAMMA_C243_PRE_LEN) - 1) << DSP2_GAMMA_C243_PRE_POS)) - -/* 0x7F4 : GAMMA_CRUVE_62 */ -#define DSP2_GAMMA_GAMMA_CRUVE_62_OFFSET (0x7F4) -#define DSP2_GAMMA_C244_PRE DSP2_GAMMA_C244_PRE -#define DSP2_GAMMA_C244_PRE_POS (0U) -#define DSP2_GAMMA_C244_PRE_LEN (8U) -#define DSP2_GAMMA_C244_PRE_MSK (((1U << DSP2_GAMMA_C244_PRE_LEN) - 1) << DSP2_GAMMA_C244_PRE_POS) -#define DSP2_GAMMA_C244_PRE_UMSK (~(((1U << DSP2_GAMMA_C244_PRE_LEN) - 1) << DSP2_GAMMA_C244_PRE_POS)) -#define DSP2_GAMMA_C245_PRE DSP2_GAMMA_C245_PRE -#define DSP2_GAMMA_C245_PRE_POS (8U) -#define DSP2_GAMMA_C245_PRE_LEN (8U) -#define DSP2_GAMMA_C245_PRE_MSK (((1U << DSP2_GAMMA_C245_PRE_LEN) - 1) << DSP2_GAMMA_C245_PRE_POS) -#define DSP2_GAMMA_C245_PRE_UMSK (~(((1U << DSP2_GAMMA_C245_PRE_LEN) - 1) << DSP2_GAMMA_C245_PRE_POS)) -#define DSP2_GAMMA_C246_PRE DSP2_GAMMA_C246_PRE -#define DSP2_GAMMA_C246_PRE_POS (16U) -#define DSP2_GAMMA_C246_PRE_LEN (8U) -#define DSP2_GAMMA_C246_PRE_MSK (((1U << DSP2_GAMMA_C246_PRE_LEN) - 1) << DSP2_GAMMA_C246_PRE_POS) -#define DSP2_GAMMA_C246_PRE_UMSK (~(((1U << DSP2_GAMMA_C246_PRE_LEN) - 1) << DSP2_GAMMA_C246_PRE_POS)) -#define DSP2_GAMMA_C247_PRE DSP2_GAMMA_C247_PRE -#define DSP2_GAMMA_C247_PRE_POS (24U) -#define DSP2_GAMMA_C247_PRE_LEN (8U) -#define DSP2_GAMMA_C247_PRE_MSK (((1U << DSP2_GAMMA_C247_PRE_LEN) - 1) << DSP2_GAMMA_C247_PRE_POS) -#define DSP2_GAMMA_C247_PRE_UMSK (~(((1U << DSP2_GAMMA_C247_PRE_LEN) - 1) << DSP2_GAMMA_C247_PRE_POS)) - -/* 0x7F8 : GAMMA_CRUVE_63 */ -#define DSP2_GAMMA_GAMMA_CRUVE_63_OFFSET (0x7F8) -#define DSP2_GAMMA_C248_PRE DSP2_GAMMA_C248_PRE -#define DSP2_GAMMA_C248_PRE_POS (0U) -#define DSP2_GAMMA_C248_PRE_LEN (8U) -#define DSP2_GAMMA_C248_PRE_MSK (((1U << DSP2_GAMMA_C248_PRE_LEN) - 1) << DSP2_GAMMA_C248_PRE_POS) -#define DSP2_GAMMA_C248_PRE_UMSK (~(((1U << DSP2_GAMMA_C248_PRE_LEN) - 1) << DSP2_GAMMA_C248_PRE_POS)) -#define DSP2_GAMMA_C249_PRE DSP2_GAMMA_C249_PRE -#define DSP2_GAMMA_C249_PRE_POS (8U) -#define DSP2_GAMMA_C249_PRE_LEN (8U) -#define DSP2_GAMMA_C249_PRE_MSK (((1U << DSP2_GAMMA_C249_PRE_LEN) - 1) << DSP2_GAMMA_C249_PRE_POS) -#define DSP2_GAMMA_C249_PRE_UMSK (~(((1U << DSP2_GAMMA_C249_PRE_LEN) - 1) << DSP2_GAMMA_C249_PRE_POS)) -#define DSP2_GAMMA_C250_PRE DSP2_GAMMA_C250_PRE -#define DSP2_GAMMA_C250_PRE_POS (16U) -#define DSP2_GAMMA_C250_PRE_LEN (8U) -#define DSP2_GAMMA_C250_PRE_MSK (((1U << DSP2_GAMMA_C250_PRE_LEN) - 1) << DSP2_GAMMA_C250_PRE_POS) -#define DSP2_GAMMA_C250_PRE_UMSK (~(((1U << DSP2_GAMMA_C250_PRE_LEN) - 1) << DSP2_GAMMA_C250_PRE_POS)) -#define DSP2_GAMMA_C251_PRE DSP2_GAMMA_C251_PRE -#define DSP2_GAMMA_C251_PRE_POS (24U) -#define DSP2_GAMMA_C251_PRE_LEN (8U) -#define DSP2_GAMMA_C251_PRE_MSK (((1U << DSP2_GAMMA_C251_PRE_LEN) - 1) << DSP2_GAMMA_C251_PRE_POS) -#define DSP2_GAMMA_C251_PRE_UMSK (~(((1U << DSP2_GAMMA_C251_PRE_LEN) - 1) << DSP2_GAMMA_C251_PRE_POS)) - -/* 0x7FC : GAMMA_CRUVE_64 */ -#define DSP2_GAMMA_GAMMA_CRUVE_64_OFFSET (0x7FC) -#define DSP2_GAMMA_C252_PRE DSP2_GAMMA_C252_PRE -#define DSP2_GAMMA_C252_PRE_POS (0U) -#define DSP2_GAMMA_C252_PRE_LEN (8U) -#define DSP2_GAMMA_C252_PRE_MSK (((1U << DSP2_GAMMA_C252_PRE_LEN) - 1) << DSP2_GAMMA_C252_PRE_POS) -#define DSP2_GAMMA_C252_PRE_UMSK (~(((1U << DSP2_GAMMA_C252_PRE_LEN) - 1) << DSP2_GAMMA_C252_PRE_POS)) -#define DSP2_GAMMA_C253_PRE DSP2_GAMMA_C253_PRE -#define DSP2_GAMMA_C253_PRE_POS (8U) -#define DSP2_GAMMA_C253_PRE_LEN (8U) -#define DSP2_GAMMA_C253_PRE_MSK (((1U << DSP2_GAMMA_C253_PRE_LEN) - 1) << DSP2_GAMMA_C253_PRE_POS) -#define DSP2_GAMMA_C253_PRE_UMSK (~(((1U << DSP2_GAMMA_C253_PRE_LEN) - 1) << DSP2_GAMMA_C253_PRE_POS)) -#define DSP2_GAMMA_C254_PRE DSP2_GAMMA_C254_PRE -#define DSP2_GAMMA_C254_PRE_POS (16U) -#define DSP2_GAMMA_C254_PRE_LEN (8U) -#define DSP2_GAMMA_C254_PRE_MSK (((1U << DSP2_GAMMA_C254_PRE_LEN) - 1) << DSP2_GAMMA_C254_PRE_POS) -#define DSP2_GAMMA_C254_PRE_UMSK (~(((1U << DSP2_GAMMA_C254_PRE_LEN) - 1) << DSP2_GAMMA_C254_PRE_POS)) -#define DSP2_GAMMA_C255_PRE DSP2_GAMMA_C255_PRE -#define DSP2_GAMMA_C255_PRE_POS (24U) -#define DSP2_GAMMA_C255_PRE_LEN (8U) -#define DSP2_GAMMA_C255_PRE_MSK (((1U << DSP2_GAMMA_C255_PRE_LEN) - 1) << DSP2_GAMMA_C255_PRE_POS) -#define DSP2_GAMMA_C255_PRE_UMSK (~(((1U << DSP2_GAMMA_C255_PRE_LEN) - 1) << DSP2_GAMMA_C255_PRE_POS)) - -struct dsp2_gamma_reg { - /* 0x0 reserved */ - uint8_t RESERVED0x0[1792]; - - /* 0x700 : GAMMA_CRUVE_1 */ - union { - struct - { - uint32_t c0_pre : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t c1_pre : 8; /* [15: 8], r/w, 0x5 */ - uint32_t c2_pre : 8; /* [23:16], r/w, 0x7 */ - uint32_t c3_pre : 8; /* [31:24], r/w, 0xa */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_1; - - /* 0x704 : GAMMA_CRUVE_2 */ - union { - struct - { - uint32_t c4_pre : 8; /* [ 7: 0], r/w, 0xd */ - uint32_t c5_pre : 8; /* [15: 8], r/w, 0x11 */ - uint32_t c6_pre : 8; /* [23:16], r/w, 0x14 */ - uint32_t c7_pre : 8; /* [31:24], r/w, 0x17 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_2; - - /* 0x708 : GAMMA_CRUVE_3 */ - union { - struct - { - uint32_t c8_pre : 8; /* [ 7: 0], r/w, 0x1a */ - uint32_t c9_pre : 8; /* [15: 8], r/w, 0x1e */ - uint32_t c10_pre : 8; /* [23:16], r/w, 0x21 */ - uint32_t c11_pre : 8; /* [31:24], r/w, 0x24 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_3; - - /* 0x70C : GAMMA_CRUVE_4 */ - union { - struct - { - uint32_t c12_pre : 8; /* [ 7: 0], r/w, 0x27 */ - uint32_t c13_pre : 8; /* [15: 8], r/w, 0x2a */ - uint32_t c14_pre : 8; /* [23:16], r/w, 0x2d */ - uint32_t c15_pre : 8; /* [31:24], r/w, 0x30 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_4; - - /* 0x710 : GAMMA_CRUVE_5 */ - union { - struct - { - uint32_t c16_pre : 8; /* [ 7: 0], r/w, 0x34 */ - uint32_t c17_pre : 8; /* [15: 8], r/w, 0x36 */ - uint32_t c18_pre : 8; /* [23:16], r/w, 0x39 */ - uint32_t c19_pre : 8; /* [31:24], r/w, 0x3c */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_5; - - /* 0x714 : GAMMA_CRUVE_6 */ - union { - struct - { - uint32_t c20_pre : 8; /* [ 7: 0], r/w, 0x3f */ - uint32_t c21_pre : 8; /* [15: 8], r/w, 0x42 */ - uint32_t c22_pre : 8; /* [23:16], r/w, 0x45 */ - uint32_t c23_pre : 8; /* [31:24], r/w, 0x47 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_6; - - /* 0x718 : GAMMA_CRUVE_7 */ - union { - struct - { - uint32_t c24_pre : 8; /* [ 7: 0], r/w, 0x4a */ - uint32_t c25_pre : 8; /* [15: 8], r/w, 0x4d */ - uint32_t c26_pre : 8; /* [23:16], r/w, 0x4f */ - uint32_t c27_pre : 8; /* [31:24], r/w, 0x52 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_7; - - /* 0x71C : GAMMA_CRUVE_8 */ - union { - struct - { - uint32_t c28_pre : 8; /* [ 7: 0], r/w, 0x54 */ - uint32_t c29_pre : 8; /* [15: 8], r/w, 0x57 */ - uint32_t c30_pre : 8; /* [23:16], r/w, 0x59 */ - uint32_t c31_pre : 8; /* [31:24], r/w, 0x5b */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_8; - - /* 0x720 : GAMMA_CRUVE_9 */ - union { - struct - { - uint32_t c32_pre : 8; /* [ 7: 0], r/w, 0x5e */ - uint32_t c33_pre : 8; /* [15: 8], r/w, 0x60 */ - uint32_t c34_pre : 8; /* [23:16], r/w, 0x62 */ - uint32_t c35_pre : 8; /* [31:24], r/w, 0x64 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_9; - - /* 0x724 : GAMMA_CRUVE_10 */ - union { - struct - { - uint32_t c36_pre : 8; /* [ 7: 0], r/w, 0x66 */ - uint32_t c37_pre : 8; /* [15: 8], r/w, 0x68 */ - uint32_t c38_pre : 8; /* [23:16], r/w, 0x6a */ - uint32_t c39_pre : 8; /* [31:24], r/w, 0x6c */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_10; - - /* 0x728 : GAMMA_CRUVE_11 */ - union { - struct - { - uint32_t c40_pre : 8; /* [ 7: 0], r/w, 0x6e */ - uint32_t c41_pre : 8; /* [15: 8], r/w, 0x70 */ - uint32_t c42_pre : 8; /* [23:16], r/w, 0x72 */ - uint32_t c43_pre : 8; /* [31:24], r/w, 0x74 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_11; - - /* 0x72C : GAMMA_CRUVE_12 */ - union { - struct - { - uint32_t c44_pre : 8; /* [ 7: 0], r/w, 0x76 */ - uint32_t c45_pre : 8; /* [15: 8], r/w, 0x78 */ - uint32_t c46_pre : 8; /* [23:16], r/w, 0x7a */ - uint32_t c47_pre : 8; /* [31:24], r/w, 0x7b */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_12; - - /* 0x730 : GAMMA_CRUVE_13 */ - union { - struct - { - uint32_t c48_pre : 8; /* [ 7: 0], r/w, 0x7d */ - uint32_t c49_pre : 8; /* [15: 8], r/w, 0x7f */ - uint32_t c50_pre : 8; /* [23:16], r/w, 0x80 */ - uint32_t c51_pre : 8; /* [31:24], r/w, 0x82 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_13; - - /* 0x734 : GAMMA_CRUVE_14 */ - union { - struct - { - uint32_t c52_pre : 8; /* [ 7: 0], r/w, 0x84 */ - uint32_t c53_pre : 8; /* [15: 8], r/w, 0x85 */ - uint32_t c54_pre : 8; /* [23:16], r/w, 0x87 */ - uint32_t c55_pre : 8; /* [31:24], r/w, 0x88 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_14; - - /* 0x738 : GAMMA_CRUVE_15 */ - union { - struct - { - uint32_t c56_pre : 8; /* [ 7: 0], r/w, 0x8a */ - uint32_t c57_pre : 8; /* [15: 8], r/w, 0x8b */ - uint32_t c58_pre : 8; /* [23:16], r/w, 0x8d */ - uint32_t c59_pre : 8; /* [31:24], r/w, 0x8e */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_15; - - /* 0x73C : GAMMA_CRUVE_16 */ - union { - struct - { - uint32_t c60_pre : 8; /* [ 7: 0], r/w, 0x90 */ - uint32_t c61_pre : 8; /* [15: 8], r/w, 0x91 */ - uint32_t c62_pre : 8; /* [23:16], r/w, 0x92 */ - uint32_t c63_pre : 8; /* [31:24], r/w, 0x94 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_16; - - /* 0x740 : GAMMA_CRUVE_17 */ - union { - struct - { - uint32_t c64_pre : 8; /* [ 7: 0], r/w, 0x95 */ - uint32_t c65_pre : 8; /* [15: 8], r/w, 0x96 */ - uint32_t c66_pre : 8; /* [23:16], r/w, 0x98 */ - uint32_t c67_pre : 8; /* [31:24], r/w, 0x99 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_17; - - /* 0x744 : GAMMA_CRUVE_18 */ - union { - struct - { - uint32_t c68_pre : 8; /* [ 7: 0], r/w, 0x9a */ - uint32_t c69_pre : 8; /* [15: 8], r/w, 0x9c */ - uint32_t c70_pre : 8; /* [23:16], r/w, 0x9d */ - uint32_t c71_pre : 8; /* [31:24], r/w, 0x9e */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_18; - - /* 0x748 : GAMMA_CRUVE_19 */ - union { - struct - { - uint32_t c72_pre : 8; /* [ 7: 0], r/w, 0xa0 */ - uint32_t c73_pre : 8; /* [15: 8], r/w, 0xa1 */ - uint32_t c74_pre : 8; /* [23:16], r/w, 0xa2 */ - uint32_t c75_pre : 8; /* [31:24], r/w, 0xa3 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_19; - - /* 0x74C : GAMMA_CRUVE_20 */ - union { - struct - { - uint32_t c76_pre : 8; /* [ 7: 0], r/w, 0xa5 */ - uint32_t c77_pre : 8; /* [15: 8], r/w, 0xa6 */ - uint32_t c78_pre : 8; /* [23:16], r/w, 0xa7 */ - uint32_t c79_pre : 8; /* [31:24], r/w, 0xa8 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_20; - - /* 0x750 : GAMMA_CRUVE_21 */ - union { - struct - { - uint32_t c80_pre : 8; /* [ 7: 0], r/w, 0xa9 */ - uint32_t c81_pre : 8; /* [15: 8], r/w, 0xab */ - uint32_t c82_pre : 8; /* [23:16], r/w, 0xac */ - uint32_t c83_pre : 8; /* [31:24], r/w, 0xad */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_21; - - /* 0x754 : GAMMA_CRUVE_22 */ - union { - struct - { - uint32_t c84_pre : 8; /* [ 7: 0], r/w, 0xae */ - uint32_t c85_pre : 8; /* [15: 8], r/w, 0xaf */ - uint32_t c86_pre : 8; /* [23:16], r/w, 0xb0 */ - uint32_t c87_pre : 8; /* [31:24], r/w, 0xb1 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_22; - - /* 0x758 : GAMMA_CRUVE_23 */ - union { - struct - { - uint32_t c88_pre : 8; /* [ 7: 0], r/w, 0xb3 */ - uint32_t c89_pre : 8; /* [15: 8], r/w, 0xb4 */ - uint32_t c90_pre : 8; /* [23:16], r/w, 0xb5 */ - uint32_t c91_pre : 8; /* [31:24], r/w, 0xb6 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_23; - - /* 0x75C : GAMMA_CRUVE_24 */ - union { - struct - { - uint32_t c92_pre : 8; /* [ 7: 0], r/w, 0xb7 */ - uint32_t c93_pre : 8; /* [15: 8], r/w, 0xb8 */ - uint32_t c94_pre : 8; /* [23:16], r/w, 0xb9 */ - uint32_t c95_pre : 8; /* [31:24], r/w, 0xba */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_24; - - /* 0x760 : GAMMA_CRUVE_25 */ - union { - struct - { - uint32_t c96_pre : 8; /* [ 7: 0], r/w, 0xbb */ - uint32_t c97_pre : 8; /* [15: 8], r/w, 0xbc */ - uint32_t c98_pre : 8; /* [23:16], r/w, 0xbd */ - uint32_t c99_pre : 8; /* [31:24], r/w, 0xbe */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_25; - - /* 0x764 : GAMMA_CRUVE_26 */ - union { - struct - { - uint32_t c100_pre : 8; /* [ 7: 0], r/w, 0xbf */ - uint32_t c101_pre : 8; /* [15: 8], r/w, 0xc0 */ - uint32_t c102_pre : 8; /* [23:16], r/w, 0xc1 */ - uint32_t c103_pre : 8; /* [31:24], r/w, 0xc2 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_26; - - /* 0x768 : GAMMA_CRUVE_27 */ - union { - struct - { - uint32_t c104_pre : 8; /* [ 7: 0], r/w, 0xc3 */ - uint32_t c105_pre : 8; /* [15: 8], r/w, 0xc4 */ - uint32_t c106_pre : 8; /* [23:16], r/w, 0xc5 */ - uint32_t c107_pre : 8; /* [31:24], r/w, 0xc6 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_27; - - /* 0x76C : GAMMA_CRUVE_28 */ - union { - struct - { - uint32_t c108_pre : 8; /* [ 7: 0], r/w, 0xc7 */ - uint32_t c109_pre : 8; /* [15: 8], r/w, 0xc8 */ - uint32_t c110_pre : 8; /* [23:16], r/w, 0xc8 */ - uint32_t c111_pre : 8; /* [31:24], r/w, 0xc9 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_28; - - /* 0x770 : GAMMA_CRUVE_29 */ - union { - struct - { - uint32_t c112_pre : 8; /* [ 7: 0], r/w, 0xca */ - uint32_t c113_pre : 8; /* [15: 8], r/w, 0xcb */ - uint32_t c114_pre : 8; /* [23:16], r/w, 0xcc */ - uint32_t c115_pre : 8; /* [31:24], r/w, 0xcd */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_29; - - /* 0x774 : GAMMA_CRUVE_30 */ - union { - struct - { - uint32_t c116_pre : 8; /* [ 7: 0], r/w, 0xcd */ - uint32_t c117_pre : 8; /* [15: 8], r/w, 0xce */ - uint32_t c118_pre : 8; /* [23:16], r/w, 0xcf */ - uint32_t c119_pre : 8; /* [31:24], r/w, 0xd0 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_30; - - /* 0x778 : GAMMA_CRUVE_31 */ - union { - struct - { - uint32_t c120_pre : 8; /* [ 7: 0], r/w, 0xd1 */ - uint32_t c121_pre : 8; /* [15: 8], r/w, 0xd1 */ - uint32_t c122_pre : 8; /* [23:16], r/w, 0xd2 */ - uint32_t c123_pre : 8; /* [31:24], r/w, 0xd3 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_31; - - /* 0x77C : GAMMA_CRUVE_32 */ - union { - struct - { - uint32_t c124_pre : 8; /* [ 7: 0], r/w, 0xd4 */ - uint32_t c125_pre : 8; /* [15: 8], r/w, 0xd4 */ - uint32_t c126_pre : 8; /* [23:16], r/w, 0xd5 */ - uint32_t c127_pre : 8; /* [31:24], r/w, 0xd6 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_32; - - /* 0x780 : GAMMA_CRUVE_33 */ - union { - struct - { - uint32_t c128_pre : 8; /* [ 7: 0], r/w, 0xd6 */ - uint32_t c129_pre : 8; /* [15: 8], r/w, 0xd7 */ - uint32_t c130_pre : 8; /* [23:16], r/w, 0xd8 */ - uint32_t c131_pre : 8; /* [31:24], r/w, 0xd8 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_33; - - /* 0x784 : GAMMA_CRUVE_34 */ - union { - struct - { - uint32_t c132_pre : 8; /* [ 7: 0], r/w, 0xd9 */ - uint32_t c133_pre : 8; /* [15: 8], r/w, 0xda */ - uint32_t c134_pre : 8; /* [23:16], r/w, 0xda */ - uint32_t c135_pre : 8; /* [31:24], r/w, 0xdb */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_34; - - /* 0x788 : GAMMA_CRUVE_35 */ - union { - struct - { - uint32_t c136_pre : 8; /* [ 7: 0], r/w, 0xdb */ - uint32_t c137_pre : 8; /* [15: 8], r/w, 0xdc */ - uint32_t c138_pre : 8; /* [23:16], r/w, 0xdd */ - uint32_t c139_pre : 8; /* [31:24], r/w, 0xdd */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_35; - - /* 0x78C : GAMMA_CRUVE_36 */ - union { - struct - { - uint32_t c140_pre : 8; /* [ 7: 0], r/w, 0xde */ - uint32_t c141_pre : 8; /* [15: 8], r/w, 0xde */ - uint32_t c142_pre : 8; /* [23:16], r/w, 0xdf */ - uint32_t c143_pre : 8; /* [31:24], r/w, 0xdf */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_36; - - /* 0x790 : GAMMA_CRUVE_37 */ - union { - struct - { - uint32_t c144_pre : 8; /* [ 7: 0], r/w, 0xe0 */ - uint32_t c145_pre : 8; /* [15: 8], r/w, 0xe1 */ - uint32_t c146_pre : 8; /* [23:16], r/w, 0xe1 */ - uint32_t c147_pre : 8; /* [31:24], r/w, 0xe2 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_37; - - /* 0x794 : GAMMA_CRUVE_38 */ - union { - struct - { - uint32_t c148_pre : 8; /* [ 7: 0], r/w, 0xe2 */ - uint32_t c149_pre : 8; /* [15: 8], r/w, 0xe3 */ - uint32_t c150_pre : 8; /* [23:16], r/w, 0xe3 */ - uint32_t c151_pre : 8; /* [31:24], r/w, 0xe4 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_38; - - /* 0x798 : GAMMA_CRUVE_39 */ - union { - struct - { - uint32_t c152_pre : 8; /* [ 7: 0], r/w, 0xe4 */ - uint32_t c153_pre : 8; /* [15: 8], r/w, 0xe5 */ - uint32_t c154_pre : 8; /* [23:16], r/w, 0xe5 */ - uint32_t c155_pre : 8; /* [31:24], r/w, 0xe5 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_39; - - /* 0x79C : GAMMA_CRUVE_40 */ - union { - struct - { - uint32_t c156_pre : 8; /* [ 7: 0], r/w, 0xe6 */ - uint32_t c157_pre : 8; /* [15: 8], r/w, 0xe6 */ - uint32_t c158_pre : 8; /* [23:16], r/w, 0xe7 */ - uint32_t c159_pre : 8; /* [31:24], r/w, 0xe7 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_40; - - /* 0x7A0 : GAMMA_CRUVE_41 */ - union { - struct - { - uint32_t c160_pre : 8; /* [ 7: 0], r/w, 0xe8 */ - uint32_t c161_pre : 8; /* [15: 8], r/w, 0xe8 */ - uint32_t c162_pre : 8; /* [23:16], r/w, 0xe9 */ - uint32_t c163_pre : 8; /* [31:24], r/w, 0xe9 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_41; - - /* 0x7A4 : GAMMA_CRUVE_42 */ - union { - struct - { - uint32_t c164_pre : 8; /* [ 7: 0], r/w, 0xe9 */ - uint32_t c165_pre : 8; /* [15: 8], r/w, 0xea */ - uint32_t c166_pre : 8; /* [23:16], r/w, 0xea */ - uint32_t c167_pre : 8; /* [31:24], r/w, 0xeb */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_42; - - /* 0x7A8 : GAMMA_CRUVE_43 */ - union { - struct - { - uint32_t c168_pre : 8; /* [ 7: 0], r/w, 0xeb */ - uint32_t c169_pre : 8; /* [15: 8], r/w, 0xeb */ - uint32_t c170_pre : 8; /* [23:16], r/w, 0xec */ - uint32_t c171_pre : 8; /* [31:24], r/w, 0xec */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_43; - - /* 0x7AC : GAMMA_CRUVE_44 */ - union { - struct - { - uint32_t c172_pre : 8; /* [ 7: 0], r/w, 0xec */ - uint32_t c173_pre : 8; /* [15: 8], r/w, 0xed */ - uint32_t c174_pre : 8; /* [23:16], r/w, 0xed */ - uint32_t c175_pre : 8; /* [31:24], r/w, 0xed */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_44; - - /* 0x7B0 : GAMMA_CRUVE_45 */ - union { - struct - { - uint32_t c176_pre : 8; /* [ 7: 0], r/w, 0xee */ - uint32_t c177_pre : 8; /* [15: 8], r/w, 0xee */ - uint32_t c178_pre : 8; /* [23:16], r/w, 0xee */ - uint32_t c179_pre : 8; /* [31:24], r/w, 0xef */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_45; - - /* 0x7B4 : GAMMA_CRUVE_46 */ - union { - struct - { - uint32_t c180_pre : 8; /* [ 7: 0], r/w, 0xef */ - uint32_t c181_pre : 8; /* [15: 8], r/w, 0xef */ - uint32_t c182_pre : 8; /* [23:16], r/w, 0xf0 */ - uint32_t c183_pre : 8; /* [31:24], r/w, 0xf0 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_46; - - /* 0x7B8 : GAMMA_CRUVE_47 */ - union { - struct - { - uint32_t c184_pre : 8; /* [ 7: 0], r/w, 0xf0 */ - uint32_t c185_pre : 8; /* [15: 8], r/w, 0xf1 */ - uint32_t c186_pre : 8; /* [23:16], r/w, 0xf1 */ - uint32_t c187_pre : 8; /* [31:24], r/w, 0xf1 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_47; - - /* 0x7BC : GAMMA_CRUVE_48 */ - union { - struct - { - uint32_t c188_pre : 8; /* [ 7: 0], r/w, 0xf2 */ - uint32_t c189_pre : 8; /* [15: 8], r/w, 0xf2 */ - uint32_t c190_pre : 8; /* [23:16], r/w, 0xf2 */ - uint32_t c191_pre : 8; /* [31:24], r/w, 0xf2 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_48; - - /* 0x7C0 : GAMMA_CRUVE_49 */ - union { - struct - { - uint32_t c192_pre : 8; /* [ 7: 0], r/w, 0xf3 */ - uint32_t c193_pre : 8; /* [15: 8], r/w, 0xf3 */ - uint32_t c194_pre : 8; /* [23:16], r/w, 0xf3 */ - uint32_t c195_pre : 8; /* [31:24], r/w, 0xf3 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_49; - - /* 0x7C4 : GAMMA_CRUVE_50 */ - union { - struct - { - uint32_t c196_pre : 8; /* [ 7: 0], r/w, 0xf4 */ - uint32_t c197_pre : 8; /* [15: 8], r/w, 0xf4 */ - uint32_t c198_pre : 8; /* [23:16], r/w, 0xf4 */ - uint32_t c199_pre : 8; /* [31:24], r/w, 0xf4 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_50; - - /* 0x7C8 : GAMMA_CRUVE_51 */ - union { - struct - { - uint32_t c200_pre : 8; /* [ 7: 0], r/w, 0xf5 */ - uint32_t c201_pre : 8; /* [15: 8], r/w, 0xf5 */ - uint32_t c202_pre : 8; /* [23:16], r/w, 0xf5 */ - uint32_t c203_pre : 8; /* [31:24], r/w, 0xf5 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_51; - - /* 0x7CC : GAMMA_CRUVE_52 */ - union { - struct - { - uint32_t c204_pre : 8; /* [ 7: 0], r/w, 0xf6 */ - uint32_t c205_pre : 8; /* [15: 8], r/w, 0xf6 */ - uint32_t c206_pre : 8; /* [23:16], r/w, 0xf6 */ - uint32_t c207_pre : 8; /* [31:24], r/w, 0xf6 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_52; - - /* 0x7D0 : GAMMA_CRUVE_53 */ - union { - struct - { - uint32_t c208_pre : 8; /* [ 7: 0], r/w, 0xf7 */ - uint32_t c209_pre : 8; /* [15: 8], r/w, 0xf7 */ - uint32_t c210_pre : 8; /* [23:16], r/w, 0xf7 */ - uint32_t c211_pre : 8; /* [31:24], r/w, 0xf7 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_53; - - /* 0x7D4 : GAMMA_CRUVE_54 */ - union { - struct - { - uint32_t c212_pre : 8; /* [ 7: 0], r/w, 0xf7 */ - uint32_t c213_pre : 8; /* [15: 8], r/w, 0xf8 */ - uint32_t c214_pre : 8; /* [23:16], r/w, 0xf8 */ - uint32_t c215_pre : 8; /* [31:24], r/w, 0xf8 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_54; - - /* 0x7D8 : GAMMA_CRUVE_55 */ - union { - struct - { - uint32_t c216_pre : 8; /* [ 7: 0], r/w, 0xf8 */ - uint32_t c217_pre : 8; /* [15: 8], r/w, 0xf8 */ - uint32_t c218_pre : 8; /* [23:16], r/w, 0xf9 */ - uint32_t c219_pre : 8; /* [31:24], r/w, 0xf9 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_55; - - /* 0x7DC : GAMMA_CRUVE_56 */ - union { - struct - { - uint32_t c220_pre : 8; /* [ 7: 0], r/w, 0xf9 */ - uint32_t c221_pre : 8; /* [15: 8], r/w, 0xf9 */ - uint32_t c222_pre : 8; /* [23:16], r/w, 0xf9 */ - uint32_t c223_pre : 8; /* [31:24], r/w, 0xfa */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_56; - - /* 0x7E0 : GAMMA_CRUVE_57 */ - union { - struct - { - uint32_t c224_pre : 8; /* [ 7: 0], r/w, 0xfa */ - uint32_t c225_pre : 8; /* [15: 8], r/w, 0xfa */ - uint32_t c226_pre : 8; /* [23:16], r/w, 0xfa */ - uint32_t c227_pre : 8; /* [31:24], r/w, 0xfa */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_57; - - /* 0x7E4 : GAMMA_CRUVE_58 */ - union { - struct - { - uint32_t c228_pre : 8; /* [ 7: 0], r/w, 0xfb */ - uint32_t c229_pre : 8; /* [15: 8], r/w, 0xfb */ - uint32_t c230_pre : 8; /* [23:16], r/w, 0xfb */ - uint32_t c231_pre : 8; /* [31:24], r/w, 0xfb */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_58; - - /* 0x7E8 : GAMMA_CRUVE_59 */ - union { - struct - { - uint32_t c232_pre : 8; /* [ 7: 0], r/w, 0xfb */ - uint32_t c233_pre : 8; /* [15: 8], r/w, 0xfb */ - uint32_t c234_pre : 8; /* [23:16], r/w, 0xfc */ - uint32_t c235_pre : 8; /* [31:24], r/w, 0xfc */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_59; - - /* 0x7EC : GAMMA_CRUVE_60 */ - union { - struct - { - uint32_t c236_pre : 8; /* [ 7: 0], r/w, 0xfc */ - uint32_t c237_pre : 8; /* [15: 8], r/w, 0xfc */ - uint32_t c238_pre : 8; /* [23:16], r/w, 0xfc */ - uint32_t c239_pre : 8; /* [31:24], r/w, 0xfc */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_60; - - /* 0x7F0 : GAMMA_CRUVE_61 */ - union { - struct - { - uint32_t c240_pre : 8; /* [ 7: 0], r/w, 0xfd */ - uint32_t c241_pre : 8; /* [15: 8], r/w, 0xfd */ - uint32_t c242_pre : 8; /* [23:16], r/w, 0xfd */ - uint32_t c243_pre : 8; /* [31:24], r/w, 0xfd */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_61; - - /* 0x7F4 : GAMMA_CRUVE_62 */ - union { - struct - { - uint32_t c244_pre : 8; /* [ 7: 0], r/w, 0xfd */ - uint32_t c245_pre : 8; /* [15: 8], r/w, 0xfd */ - uint32_t c246_pre : 8; /* [23:16], r/w, 0xfe */ - uint32_t c247_pre : 8; /* [31:24], r/w, 0xfe */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_62; - - /* 0x7F8 : GAMMA_CRUVE_63 */ - union { - struct - { - uint32_t c248_pre : 8; /* [ 7: 0], r/w, 0xfe */ - uint32_t c249_pre : 8; /* [15: 8], r/w, 0xfe */ - uint32_t c250_pre : 8; /* [23:16], r/w, 0xfe */ - uint32_t c251_pre : 8; /* [31:24], r/w, 0xfe */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_63; - - /* 0x7FC : GAMMA_CRUVE_64 */ - union { - struct - { - uint32_t c252_pre : 8; /* [ 7: 0], r/w, 0xff */ - uint32_t c253_pre : 8; /* [15: 8], r/w, 0xff */ - uint32_t c254_pre : 8; /* [23:16], r/w, 0xff */ - uint32_t c255_pre : 8; /* [31:24], r/w, 0xff */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_64; -}; - -typedef volatile struct dsp2_gamma_reg dsp2_gamma_reg_t; - -#endif /* __DSP2_GAMMA_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_middle2_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_middle2_reg.h deleted file mode 100644 index 993d5844b8..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_middle2_reg.h +++ /dev/null @@ -1,1115 +0,0 @@ -/** - ****************************************************************************** - * @file dsp2_middle2_reg.h - * @version V1.0 - * @date 2021-02-05 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __DSP2_MIDDLE2_REG_H__ -#define __DSP2_MIDDLE2_REG_H__ - -#include "bl808.h" - -/* 0x800 : BDM_1 */ -#define DSP2_MIDDLE2_BDM_1_OFFSET (0x800) -#define DSP2_MIDDLE2_BDM_EB_PRE DSP2_MIDDLE2_BDM_EB_PRE -#define DSP2_MIDDLE2_BDM_EB_PRE_POS (0U) -#define DSP2_MIDDLE2_BDM_EB_PRE_LEN (1U) -#define DSP2_MIDDLE2_BDM_EB_PRE_MSK (((1U << DSP2_MIDDLE2_BDM_EB_PRE_LEN) - 1) << DSP2_MIDDLE2_BDM_EB_PRE_POS) -#define DSP2_MIDDLE2_BDM_EB_PRE_UMSK (~(((1U << DSP2_MIDDLE2_BDM_EB_PRE_LEN) - 1) << DSP2_MIDDLE2_BDM_EB_PRE_POS)) -#define DSP2_MIDDLE2_GW_THR_PRE DSP2_MIDDLE2_GW_THR_PRE -#define DSP2_MIDDLE2_GW_THR_PRE_POS (8U) -#define DSP2_MIDDLE2_GW_THR_PRE_LEN (5U) -#define DSP2_MIDDLE2_GW_THR_PRE_MSK (((1U << DSP2_MIDDLE2_GW_THR_PRE_LEN) - 1) << DSP2_MIDDLE2_GW_THR_PRE_POS) -#define DSP2_MIDDLE2_GW_THR_PRE_UMSK (~(((1U << DSP2_MIDDLE2_GW_THR_PRE_LEN) - 1) << DSP2_MIDDLE2_GW_THR_PRE_POS)) -#define DSP2_MIDDLE2_G_SCAL_FACTOR_PRE DSP2_MIDDLE2_G_SCAL_FACTOR_PRE -#define DSP2_MIDDLE2_G_SCAL_FACTOR_PRE_POS (16U) -#define DSP2_MIDDLE2_G_SCAL_FACTOR_PRE_LEN (9U) -#define DSP2_MIDDLE2_G_SCAL_FACTOR_PRE_MSK (((1U << DSP2_MIDDLE2_G_SCAL_FACTOR_PRE_LEN) - 1) << DSP2_MIDDLE2_G_SCAL_FACTOR_PRE_POS) -#define DSP2_MIDDLE2_G_SCAL_FACTOR_PRE_UMSK (~(((1U << DSP2_MIDDLE2_G_SCAL_FACTOR_PRE_LEN) - 1) << DSP2_MIDDLE2_G_SCAL_FACTOR_PRE_POS)) - -/* 0x804 : BDM_2 */ -#define DSP2_MIDDLE2_BDM_2_OFFSET (0x804) -#define DSP2_MIDDLE2_R_SCAL_FACTOR_PRE DSP2_MIDDLE2_R_SCAL_FACTOR_PRE -#define DSP2_MIDDLE2_R_SCAL_FACTOR_PRE_POS (0U) -#define DSP2_MIDDLE2_R_SCAL_FACTOR_PRE_LEN (9U) -#define DSP2_MIDDLE2_R_SCAL_FACTOR_PRE_MSK (((1U << DSP2_MIDDLE2_R_SCAL_FACTOR_PRE_LEN) - 1) << DSP2_MIDDLE2_R_SCAL_FACTOR_PRE_POS) -#define DSP2_MIDDLE2_R_SCAL_FACTOR_PRE_UMSK (~(((1U << DSP2_MIDDLE2_R_SCAL_FACTOR_PRE_LEN) - 1) << DSP2_MIDDLE2_R_SCAL_FACTOR_PRE_POS)) -#define DSP2_MIDDLE2_B_SCAL_FACTOR_PRE DSP2_MIDDLE2_B_SCAL_FACTOR_PRE -#define DSP2_MIDDLE2_B_SCAL_FACTOR_PRE_POS (16U) -#define DSP2_MIDDLE2_B_SCAL_FACTOR_PRE_LEN (9U) -#define DSP2_MIDDLE2_B_SCAL_FACTOR_PRE_MSK (((1U << DSP2_MIDDLE2_B_SCAL_FACTOR_PRE_LEN) - 1) << DSP2_MIDDLE2_B_SCAL_FACTOR_PRE_POS) -#define DSP2_MIDDLE2_B_SCAL_FACTOR_PRE_UMSK (~(((1U << DSP2_MIDDLE2_B_SCAL_FACTOR_PRE_LEN) - 1) << DSP2_MIDDLE2_B_SCAL_FACTOR_PRE_POS)) - -/* 0x808 : BDM_3 */ -#define DSP2_MIDDLE2_BDM_3_OFFSET (0x808) -#define DSP2_MIDDLE2_NR_PROFILE10_PRE DSP2_MIDDLE2_NR_PROFILE10_PRE -#define DSP2_MIDDLE2_NR_PROFILE10_PRE_POS (0U) -#define DSP2_MIDDLE2_NR_PROFILE10_PRE_LEN (12U) -#define DSP2_MIDDLE2_NR_PROFILE10_PRE_MSK (((1U << DSP2_MIDDLE2_NR_PROFILE10_PRE_LEN) - 1) << DSP2_MIDDLE2_NR_PROFILE10_PRE_POS) -#define DSP2_MIDDLE2_NR_PROFILE10_PRE_UMSK (~(((1U << DSP2_MIDDLE2_NR_PROFILE10_PRE_LEN) - 1) << DSP2_MIDDLE2_NR_PROFILE10_PRE_POS)) -#define DSP2_MIDDLE2_NR_PROFILE00_PRE DSP2_MIDDLE2_NR_PROFILE00_PRE -#define DSP2_MIDDLE2_NR_PROFILE00_PRE_POS (16U) -#define DSP2_MIDDLE2_NR_PROFILE00_PRE_LEN (12U) -#define DSP2_MIDDLE2_NR_PROFILE00_PRE_MSK (((1U << DSP2_MIDDLE2_NR_PROFILE00_PRE_LEN) - 1) << DSP2_MIDDLE2_NR_PROFILE00_PRE_POS) -#define DSP2_MIDDLE2_NR_PROFILE00_PRE_UMSK (~(((1U << DSP2_MIDDLE2_NR_PROFILE00_PRE_LEN) - 1) << DSP2_MIDDLE2_NR_PROFILE00_PRE_POS)) - -/* 0x80C : BDM_4 */ -#define DSP2_MIDDLE2_BDM_4_OFFSET (0x80C) -#define DSP2_MIDDLE2_NR_PROFILE30_PRE DSP2_MIDDLE2_NR_PROFILE30_PRE -#define DSP2_MIDDLE2_NR_PROFILE30_PRE_POS (0U) -#define DSP2_MIDDLE2_NR_PROFILE30_PRE_LEN (12U) -#define DSP2_MIDDLE2_NR_PROFILE30_PRE_MSK (((1U << DSP2_MIDDLE2_NR_PROFILE30_PRE_LEN) - 1) << DSP2_MIDDLE2_NR_PROFILE30_PRE_POS) -#define DSP2_MIDDLE2_NR_PROFILE30_PRE_UMSK (~(((1U << DSP2_MIDDLE2_NR_PROFILE30_PRE_LEN) - 1) << DSP2_MIDDLE2_NR_PROFILE30_PRE_POS)) -#define DSP2_MIDDLE2_NR_PROFILE20_PRE DSP2_MIDDLE2_NR_PROFILE20_PRE -#define DSP2_MIDDLE2_NR_PROFILE20_PRE_POS (16U) -#define DSP2_MIDDLE2_NR_PROFILE20_PRE_LEN (12U) -#define DSP2_MIDDLE2_NR_PROFILE20_PRE_MSK (((1U << DSP2_MIDDLE2_NR_PROFILE20_PRE_LEN) - 1) << DSP2_MIDDLE2_NR_PROFILE20_PRE_POS) -#define DSP2_MIDDLE2_NR_PROFILE20_PRE_UMSK (~(((1U << DSP2_MIDDLE2_NR_PROFILE20_PRE_LEN) - 1) << DSP2_MIDDLE2_NR_PROFILE20_PRE_POS)) - -/* 0x810 : BDM_5 */ -#define DSP2_MIDDLE2_BDM_5_OFFSET (0x810) -#define DSP2_MIDDLE2_NR_PROFILE50_PRE DSP2_MIDDLE2_NR_PROFILE50_PRE -#define DSP2_MIDDLE2_NR_PROFILE50_PRE_POS (0U) -#define DSP2_MIDDLE2_NR_PROFILE50_PRE_LEN (12U) -#define DSP2_MIDDLE2_NR_PROFILE50_PRE_MSK (((1U << DSP2_MIDDLE2_NR_PROFILE50_PRE_LEN) - 1) << DSP2_MIDDLE2_NR_PROFILE50_PRE_POS) -#define DSP2_MIDDLE2_NR_PROFILE50_PRE_UMSK (~(((1U << DSP2_MIDDLE2_NR_PROFILE50_PRE_LEN) - 1) << DSP2_MIDDLE2_NR_PROFILE50_PRE_POS)) -#define DSP2_MIDDLE2_NR_PROFILE40_PRE DSP2_MIDDLE2_NR_PROFILE40_PRE -#define DSP2_MIDDLE2_NR_PROFILE40_PRE_POS (16U) -#define DSP2_MIDDLE2_NR_PROFILE40_PRE_LEN (12U) -#define DSP2_MIDDLE2_NR_PROFILE40_PRE_MSK (((1U << DSP2_MIDDLE2_NR_PROFILE40_PRE_LEN) - 1) << DSP2_MIDDLE2_NR_PROFILE40_PRE_POS) -#define DSP2_MIDDLE2_NR_PROFILE40_PRE_UMSK (~(((1U << DSP2_MIDDLE2_NR_PROFILE40_PRE_LEN) - 1) << DSP2_MIDDLE2_NR_PROFILE40_PRE_POS)) - -/* 0x814 : BDM_6 */ -#define DSP2_MIDDLE2_BDM_6_OFFSET (0x814) -#define DSP2_MIDDLE2_NR_PROFILE01_PRE DSP2_MIDDLE2_NR_PROFILE01_PRE -#define DSP2_MIDDLE2_NR_PROFILE01_PRE_POS (0U) -#define DSP2_MIDDLE2_NR_PROFILE01_PRE_LEN (17U) -#define DSP2_MIDDLE2_NR_PROFILE01_PRE_MSK (((1U << DSP2_MIDDLE2_NR_PROFILE01_PRE_LEN) - 1) << DSP2_MIDDLE2_NR_PROFILE01_PRE_POS) -#define DSP2_MIDDLE2_NR_PROFILE01_PRE_UMSK (~(((1U << DSP2_MIDDLE2_NR_PROFILE01_PRE_LEN) - 1) << DSP2_MIDDLE2_NR_PROFILE01_PRE_POS)) - -/* 0x818 : BDM_7 */ -#define DSP2_MIDDLE2_BDM_7_OFFSET (0x818) -#define DSP2_MIDDLE2_NR_PROFILE11_PRE DSP2_MIDDLE2_NR_PROFILE11_PRE -#define DSP2_MIDDLE2_NR_PROFILE11_PRE_POS (0U) -#define DSP2_MIDDLE2_NR_PROFILE11_PRE_LEN (17U) -#define DSP2_MIDDLE2_NR_PROFILE11_PRE_MSK (((1U << DSP2_MIDDLE2_NR_PROFILE11_PRE_LEN) - 1) << DSP2_MIDDLE2_NR_PROFILE11_PRE_POS) -#define DSP2_MIDDLE2_NR_PROFILE11_PRE_UMSK (~(((1U << DSP2_MIDDLE2_NR_PROFILE11_PRE_LEN) - 1) << DSP2_MIDDLE2_NR_PROFILE11_PRE_POS)) - -/* 0x81C : BDM_8 */ -#define DSP2_MIDDLE2_BDM_8_OFFSET (0x81C) -#define DSP2_MIDDLE2_NR_PROFILE21_PRE DSP2_MIDDLE2_NR_PROFILE21_PRE -#define DSP2_MIDDLE2_NR_PROFILE21_PRE_POS (0U) -#define DSP2_MIDDLE2_NR_PROFILE21_PRE_LEN (17U) -#define DSP2_MIDDLE2_NR_PROFILE21_PRE_MSK (((1U << DSP2_MIDDLE2_NR_PROFILE21_PRE_LEN) - 1) << DSP2_MIDDLE2_NR_PROFILE21_PRE_POS) -#define DSP2_MIDDLE2_NR_PROFILE21_PRE_UMSK (~(((1U << DSP2_MIDDLE2_NR_PROFILE21_PRE_LEN) - 1) << DSP2_MIDDLE2_NR_PROFILE21_PRE_POS)) - -/* 0x820 : BDM_9 */ -#define DSP2_MIDDLE2_BDM_9_OFFSET (0x820) -#define DSP2_MIDDLE2_NR_PROFILE31_PRE DSP2_MIDDLE2_NR_PROFILE31_PRE -#define DSP2_MIDDLE2_NR_PROFILE31_PRE_POS (0U) -#define DSP2_MIDDLE2_NR_PROFILE31_PRE_LEN (17U) -#define DSP2_MIDDLE2_NR_PROFILE31_PRE_MSK (((1U << DSP2_MIDDLE2_NR_PROFILE31_PRE_LEN) - 1) << DSP2_MIDDLE2_NR_PROFILE31_PRE_POS) -#define DSP2_MIDDLE2_NR_PROFILE31_PRE_UMSK (~(((1U << DSP2_MIDDLE2_NR_PROFILE31_PRE_LEN) - 1) << DSP2_MIDDLE2_NR_PROFILE31_PRE_POS)) - -/* 0x824 : BDM_10 */ -#define DSP2_MIDDLE2_BDM_10_OFFSET (0x824) -#define DSP2_MIDDLE2_NR_PROFILE41_PRE DSP2_MIDDLE2_NR_PROFILE41_PRE -#define DSP2_MIDDLE2_NR_PROFILE41_PRE_POS (0U) -#define DSP2_MIDDLE2_NR_PROFILE41_PRE_LEN (17U) -#define DSP2_MIDDLE2_NR_PROFILE41_PRE_MSK (((1U << DSP2_MIDDLE2_NR_PROFILE41_PRE_LEN) - 1) << DSP2_MIDDLE2_NR_PROFILE41_PRE_POS) -#define DSP2_MIDDLE2_NR_PROFILE41_PRE_UMSK (~(((1U << DSP2_MIDDLE2_NR_PROFILE41_PRE_LEN) - 1) << DSP2_MIDDLE2_NR_PROFILE41_PRE_POS)) - -/* 0x828 : BDM_11 */ -#define DSP2_MIDDLE2_BDM_11_OFFSET (0x828) -#define DSP2_MIDDLE2_NR_PROFILE51_PRE DSP2_MIDDLE2_NR_PROFILE51_PRE -#define DSP2_MIDDLE2_NR_PROFILE51_PRE_POS (0U) -#define DSP2_MIDDLE2_NR_PROFILE51_PRE_LEN (17U) -#define DSP2_MIDDLE2_NR_PROFILE51_PRE_MSK (((1U << DSP2_MIDDLE2_NR_PROFILE51_PRE_LEN) - 1) << DSP2_MIDDLE2_NR_PROFILE51_PRE_POS) -#define DSP2_MIDDLE2_NR_PROFILE51_PRE_UMSK (~(((1U << DSP2_MIDDLE2_NR_PROFILE51_PRE_LEN) - 1) << DSP2_MIDDLE2_NR_PROFILE51_PRE_POS)) - -/* 0x82C : BDM_12 */ -#define DSP2_MIDDLE2_BDM_12_OFFSET (0x82C) -#define DSP2_MIDDLE2_LUMA_G_W1_PRE DSP2_MIDDLE2_LUMA_G_W1_PRE -#define DSP2_MIDDLE2_LUMA_G_W1_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_G_W1_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W1_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W1_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W1_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W1_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W1_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W1_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_G_W0_PRE DSP2_MIDDLE2_LUMA_G_W0_PRE -#define DSP2_MIDDLE2_LUMA_G_W0_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_G_W0_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W0_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W0_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W0_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W0_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W0_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W0_PRE_POS)) - -/* 0x830 : BDM_13 */ -#define DSP2_MIDDLE2_BDM_13_OFFSET (0x830) -#define DSP2_MIDDLE2_LUMA_G_W3_PRE DSP2_MIDDLE2_LUMA_G_W3_PRE -#define DSP2_MIDDLE2_LUMA_G_W3_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_G_W3_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W3_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W3_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W3_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W3_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W3_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W3_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_G_W2_PRE DSP2_MIDDLE2_LUMA_G_W2_PRE -#define DSP2_MIDDLE2_LUMA_G_W2_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_G_W2_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W2_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W2_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W2_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W2_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W2_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W2_PRE_POS)) - -/* 0x834 : BDM_14 */ -#define DSP2_MIDDLE2_BDM_14_OFFSET (0x834) -#define DSP2_MIDDLE2_LUMA_G_W5_PRE DSP2_MIDDLE2_LUMA_G_W5_PRE -#define DSP2_MIDDLE2_LUMA_G_W5_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_G_W5_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W5_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W5_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W5_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W5_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W5_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W5_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_G_W4_PRE DSP2_MIDDLE2_LUMA_G_W4_PRE -#define DSP2_MIDDLE2_LUMA_G_W4_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_G_W4_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W4_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W4_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W4_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W4_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W4_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W4_PRE_POS)) - -/* 0x838 : BDM_15 */ -#define DSP2_MIDDLE2_BDM_15_OFFSET (0x838) -#define DSP2_MIDDLE2_LUMA_G_W7_PRE DSP2_MIDDLE2_LUMA_G_W7_PRE -#define DSP2_MIDDLE2_LUMA_G_W7_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_G_W7_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W7_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W7_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W7_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W7_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W7_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W7_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_G_W6_PRE DSP2_MIDDLE2_LUMA_G_W6_PRE -#define DSP2_MIDDLE2_LUMA_G_W6_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_G_W6_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W6_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W6_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W6_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W6_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W6_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W6_PRE_POS)) - -/* 0x83C : BDM_16 */ -#define DSP2_MIDDLE2_BDM_16_OFFSET (0x83C) -#define DSP2_MIDDLE2_LUMA_G_W9_PRE DSP2_MIDDLE2_LUMA_G_W9_PRE -#define DSP2_MIDDLE2_LUMA_G_W9_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_G_W9_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W9_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W9_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W9_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W9_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W9_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W9_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_G_W8_PRE DSP2_MIDDLE2_LUMA_G_W8_PRE -#define DSP2_MIDDLE2_LUMA_G_W8_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_G_W8_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W8_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W8_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W8_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W8_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W8_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W8_PRE_POS)) - -/* 0x840 : BDM_17 */ -#define DSP2_MIDDLE2_BDM_17_OFFSET (0x840) -#define DSP2_MIDDLE2_LUMA_G_W11_PRE DSP2_MIDDLE2_LUMA_G_W11_PRE -#define DSP2_MIDDLE2_LUMA_G_W11_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_G_W11_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W11_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W11_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W11_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W11_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W11_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W11_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_G_W10_PRE DSP2_MIDDLE2_LUMA_G_W10_PRE -#define DSP2_MIDDLE2_LUMA_G_W10_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_G_W10_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W10_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W10_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W10_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W10_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W10_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W10_PRE_POS)) - -/* 0x844 : BDM_18 */ -#define DSP2_MIDDLE2_BDM_18_OFFSET (0x844) -#define DSP2_MIDDLE2_LUMA_G_W13_PRE DSP2_MIDDLE2_LUMA_G_W13_PRE -#define DSP2_MIDDLE2_LUMA_G_W13_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_G_W13_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W13_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W13_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W13_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W13_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W13_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W13_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_G_W12_PRE DSP2_MIDDLE2_LUMA_G_W12_PRE -#define DSP2_MIDDLE2_LUMA_G_W12_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_G_W12_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W12_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W12_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W12_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W12_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W12_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W12_PRE_POS)) - -/* 0x848 : BDM_19 */ -#define DSP2_MIDDLE2_BDM_19_OFFSET (0x848) -#define DSP2_MIDDLE2_LUMA_G_W15_PRE DSP2_MIDDLE2_LUMA_G_W15_PRE -#define DSP2_MIDDLE2_LUMA_G_W15_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_G_W15_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W15_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W15_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W15_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W15_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W15_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W15_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_G_W14_PRE DSP2_MIDDLE2_LUMA_G_W14_PRE -#define DSP2_MIDDLE2_LUMA_G_W14_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_G_W14_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W14_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W14_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W14_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W14_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W14_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W14_PRE_POS)) - -/* 0x84C : BDM_20 */ -#define DSP2_MIDDLE2_BDM_20_OFFSET (0x84C) -#define DSP2_MIDDLE2_LUMA_G_W17_PRE DSP2_MIDDLE2_LUMA_G_W17_PRE -#define DSP2_MIDDLE2_LUMA_G_W17_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_G_W17_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W17_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W17_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W17_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W17_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W17_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W17_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_G_W16_PRE DSP2_MIDDLE2_LUMA_G_W16_PRE -#define DSP2_MIDDLE2_LUMA_G_W16_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_G_W16_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W16_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W16_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W16_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W16_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W16_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W16_PRE_POS)) - -/* 0x850 : BDM_21 */ -#define DSP2_MIDDLE2_BDM_21_OFFSET (0x850) -#define DSP2_MIDDLE2_LUMA_G_W19_PRE DSP2_MIDDLE2_LUMA_G_W19_PRE -#define DSP2_MIDDLE2_LUMA_G_W19_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_G_W19_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W19_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W19_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W19_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W19_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W19_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W19_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_G_W18_PRE DSP2_MIDDLE2_LUMA_G_W18_PRE -#define DSP2_MIDDLE2_LUMA_G_W18_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_G_W18_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W18_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W18_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W18_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W18_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W18_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W18_PRE_POS)) - -/* 0x854 : BDM_22 */ -#define DSP2_MIDDLE2_BDM_22_OFFSET (0x854) -#define DSP2_MIDDLE2_LUMA_G_W21_PRE DSP2_MIDDLE2_LUMA_G_W21_PRE -#define DSP2_MIDDLE2_LUMA_G_W21_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_G_W21_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W21_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W21_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W21_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W21_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W21_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W21_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_G_W20_PRE DSP2_MIDDLE2_LUMA_G_W20_PRE -#define DSP2_MIDDLE2_LUMA_G_W20_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_G_W20_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W20_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W20_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W20_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W20_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W20_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W20_PRE_POS)) - -/* 0x858 : BDM_23 */ -#define DSP2_MIDDLE2_BDM_23_OFFSET (0x858) -#define DSP2_MIDDLE2_LUMA_G_W23_PRE DSP2_MIDDLE2_LUMA_G_W23_PRE -#define DSP2_MIDDLE2_LUMA_G_W23_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_G_W23_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W23_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W23_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W23_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W23_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W23_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W23_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_G_W22_PRE DSP2_MIDDLE2_LUMA_G_W22_PRE -#define DSP2_MIDDLE2_LUMA_G_W22_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_G_W22_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W22_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W22_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W22_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W22_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W22_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W22_PRE_POS)) - -/* 0x85C : BDM_24 */ -#define DSP2_MIDDLE2_BDM_24_OFFSET (0x85C) -#define DSP2_MIDDLE2_LUMA_G_W25_PRE DSP2_MIDDLE2_LUMA_G_W25_PRE -#define DSP2_MIDDLE2_LUMA_G_W25_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_G_W25_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W25_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W25_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W25_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W25_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W25_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W25_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_G_W24_PRE DSP2_MIDDLE2_LUMA_G_W24_PRE -#define DSP2_MIDDLE2_LUMA_G_W24_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_G_W24_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W24_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W24_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W24_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W24_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W24_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W24_PRE_POS)) - -/* 0x860 : BDM_25 */ -#define DSP2_MIDDLE2_BDM_25_OFFSET (0x860) -#define DSP2_MIDDLE2_LUMA_G_W27_PRE DSP2_MIDDLE2_LUMA_G_W27_PRE -#define DSP2_MIDDLE2_LUMA_G_W27_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_G_W27_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W27_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W27_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W27_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W27_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W27_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W27_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_G_W26_PRE DSP2_MIDDLE2_LUMA_G_W26_PRE -#define DSP2_MIDDLE2_LUMA_G_W26_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_G_W26_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W26_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W26_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W26_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W26_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W26_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W26_PRE_POS)) - -/* 0x864 : BDM_26 */ -#define DSP2_MIDDLE2_BDM_26_OFFSET (0x864) -#define DSP2_MIDDLE2_LUMA_G_W29_PRE DSP2_MIDDLE2_LUMA_G_W29_PRE -#define DSP2_MIDDLE2_LUMA_G_W29_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_G_W29_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W29_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W29_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W29_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W29_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W29_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W29_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_G_W28_PRE DSP2_MIDDLE2_LUMA_G_W28_PRE -#define DSP2_MIDDLE2_LUMA_G_W28_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_G_W28_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W28_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W28_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W28_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W28_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W28_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W28_PRE_POS)) - -/* 0x868 : BDM_27 */ -#define DSP2_MIDDLE2_BDM_27_OFFSET (0x868) -#define DSP2_MIDDLE2_LUMA_G_W31_PRE DSP2_MIDDLE2_LUMA_G_W31_PRE -#define DSP2_MIDDLE2_LUMA_G_W31_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_G_W31_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W31_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W31_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W31_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W31_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W31_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W31_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_G_W30_PRE DSP2_MIDDLE2_LUMA_G_W30_PRE -#define DSP2_MIDDLE2_LUMA_G_W30_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_G_W30_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W30_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W30_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W30_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W30_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W30_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W30_PRE_POS)) - -/* 0x870 : BDM_28 */ -#define DSP2_MIDDLE2_BDM_28_OFFSET (0x870) -#define DSP2_MIDDLE2_LUMA_BR_W1_PRE DSP2_MIDDLE2_LUMA_BR_W1_PRE -#define DSP2_MIDDLE2_LUMA_BR_W1_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_BR_W1_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W1_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W1_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W1_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W1_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W1_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W1_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_BR_W0_PRE DSP2_MIDDLE2_LUMA_BR_W0_PRE -#define DSP2_MIDDLE2_LUMA_BR_W0_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_BR_W0_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W0_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W0_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W0_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W0_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W0_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W0_PRE_POS)) - -/* 0x874 : BDM_29 */ -#define DSP2_MIDDLE2_BDM_29_OFFSET (0x874) -#define DSP2_MIDDLE2_LUMA_BR_W3_PRE DSP2_MIDDLE2_LUMA_BR_W3_PRE -#define DSP2_MIDDLE2_LUMA_BR_W3_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_BR_W3_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W3_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W3_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W3_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W3_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W3_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W3_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_BR_W2_PRE DSP2_MIDDLE2_LUMA_BR_W2_PRE -#define DSP2_MIDDLE2_LUMA_BR_W2_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_BR_W2_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W2_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W2_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W2_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W2_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W2_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W2_PRE_POS)) - -/* 0x878 : BDM_30 */ -#define DSP2_MIDDLE2_BDM_30_OFFSET (0x878) -#define DSP2_MIDDLE2_LUMA_BR_W5_PRE DSP2_MIDDLE2_LUMA_BR_W5_PRE -#define DSP2_MIDDLE2_LUMA_BR_W5_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_BR_W5_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W5_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W5_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W5_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W5_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W5_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W5_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_BR_W4_PRE DSP2_MIDDLE2_LUMA_BR_W4_PRE -#define DSP2_MIDDLE2_LUMA_BR_W4_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_BR_W4_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W4_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W4_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W4_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W4_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W4_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W4_PRE_POS)) - -/* 0x87C : BDM_31 */ -#define DSP2_MIDDLE2_BDM_31_OFFSET (0x87C) -#define DSP2_MIDDLE2_LUMA_BR_W7_PRE DSP2_MIDDLE2_LUMA_BR_W7_PRE -#define DSP2_MIDDLE2_LUMA_BR_W7_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_BR_W7_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W7_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W7_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W7_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W7_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W7_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W7_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_BR_W6_PRE DSP2_MIDDLE2_LUMA_BR_W6_PRE -#define DSP2_MIDDLE2_LUMA_BR_W6_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_BR_W6_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W6_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W6_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W6_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W6_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W6_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W6_PRE_POS)) - -/* 0x880 : BDM_32 */ -#define DSP2_MIDDLE2_BDM_32_OFFSET (0x880) -#define DSP2_MIDDLE2_LUMA_BR_W9_PRE DSP2_MIDDLE2_LUMA_BR_W9_PRE -#define DSP2_MIDDLE2_LUMA_BR_W9_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_BR_W9_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W9_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W9_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W9_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W9_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W9_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W9_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_BR_W8_PRE DSP2_MIDDLE2_LUMA_BR_W8_PRE -#define DSP2_MIDDLE2_LUMA_BR_W8_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_BR_W8_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W8_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W8_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W8_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W8_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W8_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W8_PRE_POS)) - -/* 0x884 : BDM_33 */ -#define DSP2_MIDDLE2_BDM_33_OFFSET (0x884) -#define DSP2_MIDDLE2_LUMA_BR_W11_PRE DSP2_MIDDLE2_LUMA_BR_W11_PRE -#define DSP2_MIDDLE2_LUMA_BR_W11_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_BR_W11_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W11_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W11_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W11_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W11_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W11_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W11_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_BR_W10_PRE DSP2_MIDDLE2_LUMA_BR_W10_PRE -#define DSP2_MIDDLE2_LUMA_BR_W10_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_BR_W10_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W10_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W10_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W10_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W10_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W10_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W10_PRE_POS)) - -/* 0x888 : BDM_34 */ -#define DSP2_MIDDLE2_BDM_34_OFFSET (0x888) -#define DSP2_MIDDLE2_LUMA_BR_W13_PRE DSP2_MIDDLE2_LUMA_BR_W13_PRE -#define DSP2_MIDDLE2_LUMA_BR_W13_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_BR_W13_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W13_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W13_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W13_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W13_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W13_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W13_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_BR_W12_PRE DSP2_MIDDLE2_LUMA_BR_W12_PRE -#define DSP2_MIDDLE2_LUMA_BR_W12_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_BR_W12_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W12_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W12_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W12_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W12_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W12_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W12_PRE_POS)) - -/* 0x88C : BDM_35 */ -#define DSP2_MIDDLE2_BDM_35_OFFSET (0x88C) -#define DSP2_MIDDLE2_LUMA_BR_W15_PRE DSP2_MIDDLE2_LUMA_BR_W15_PRE -#define DSP2_MIDDLE2_LUMA_BR_W15_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_BR_W15_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W15_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W15_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W15_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W15_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W15_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W15_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_BR_W14_PRE DSP2_MIDDLE2_LUMA_BR_W14_PRE -#define DSP2_MIDDLE2_LUMA_BR_W14_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_BR_W14_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W14_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W14_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W14_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W14_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W14_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W14_PRE_POS)) - -/* 0x890 : BDM_36 */ -#define DSP2_MIDDLE2_BDM_36_OFFSET (0x890) -#define DSP2_MIDDLE2_LUMA_BR_W17_PRE DSP2_MIDDLE2_LUMA_BR_W17_PRE -#define DSP2_MIDDLE2_LUMA_BR_W17_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_BR_W17_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W17_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W17_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W17_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W17_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W17_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W17_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_BR_W16_PRE DSP2_MIDDLE2_LUMA_BR_W16_PRE -#define DSP2_MIDDLE2_LUMA_BR_W16_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_BR_W16_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W16_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W16_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W16_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W16_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W16_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W16_PRE_POS)) - -/* 0x894 : BDM_37 */ -#define DSP2_MIDDLE2_BDM_37_OFFSET (0x894) -#define DSP2_MIDDLE2_LUMA_BR_W19_PRE DSP2_MIDDLE2_LUMA_BR_W19_PRE -#define DSP2_MIDDLE2_LUMA_BR_W19_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_BR_W19_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W19_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W19_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W19_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W19_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W19_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W19_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_BR_W18_PRE DSP2_MIDDLE2_LUMA_BR_W18_PRE -#define DSP2_MIDDLE2_LUMA_BR_W18_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_BR_W18_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W18_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W18_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W18_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W18_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W18_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W18_PRE_POS)) - -/* 0x898 : BDM_38 */ -#define DSP2_MIDDLE2_BDM_38_OFFSET (0x898) -#define DSP2_MIDDLE2_LUMA_BR_W21_PRE DSP2_MIDDLE2_LUMA_BR_W21_PRE -#define DSP2_MIDDLE2_LUMA_BR_W21_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_BR_W21_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W21_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W21_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W21_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W21_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W21_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W21_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_BR_W20_PRE DSP2_MIDDLE2_LUMA_BR_W20_PRE -#define DSP2_MIDDLE2_LUMA_BR_W20_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_BR_W20_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W20_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W20_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W20_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W20_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W20_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W20_PRE_POS)) - -/* 0x89C : BDM_39 */ -#define DSP2_MIDDLE2_BDM_39_OFFSET (0x89C) -#define DSP2_MIDDLE2_LUMA_BR_W23_PRE DSP2_MIDDLE2_LUMA_BR_W23_PRE -#define DSP2_MIDDLE2_LUMA_BR_W23_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_BR_W23_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W23_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W23_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W23_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W23_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W23_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W23_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_BR_W22_PRE DSP2_MIDDLE2_LUMA_BR_W22_PRE -#define DSP2_MIDDLE2_LUMA_BR_W22_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_BR_W22_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W22_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W22_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W22_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W22_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W22_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W22_PRE_POS)) - -/* 0x8A0 : BDM_40 */ -#define DSP2_MIDDLE2_BDM_40_OFFSET (0x8A0) -#define DSP2_MIDDLE2_LUMA_BR_W25_PRE DSP2_MIDDLE2_LUMA_BR_W25_PRE -#define DSP2_MIDDLE2_LUMA_BR_W25_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_BR_W25_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W25_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W25_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W25_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W25_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W25_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W25_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_BR_W24_PRE DSP2_MIDDLE2_LUMA_BR_W24_PRE -#define DSP2_MIDDLE2_LUMA_BR_W24_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_BR_W24_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W24_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W24_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W24_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W24_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W24_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W24_PRE_POS)) - -/* 0x8A4 : BDM_41 */ -#define DSP2_MIDDLE2_BDM_41_OFFSET (0x8A4) -#define DSP2_MIDDLE2_LUMA_BR_W27_PRE DSP2_MIDDLE2_LUMA_BR_W27_PRE -#define DSP2_MIDDLE2_LUMA_BR_W27_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_BR_W27_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W27_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W27_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W27_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W27_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W27_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W27_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_BR_W26_PRE DSP2_MIDDLE2_LUMA_BR_W26_PRE -#define DSP2_MIDDLE2_LUMA_BR_W26_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_BR_W26_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W26_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W26_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W26_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W26_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W26_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W26_PRE_POS)) - -/* 0x8A8 : BDM_42 */ -#define DSP2_MIDDLE2_BDM_42_OFFSET (0x8A8) -#define DSP2_MIDDLE2_LUMA_BR_W29_PRE DSP2_MIDDLE2_LUMA_BR_W29_PRE -#define DSP2_MIDDLE2_LUMA_BR_W29_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_BR_W29_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W29_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W29_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W29_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W29_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W29_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W29_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_BR_W28_PRE DSP2_MIDDLE2_LUMA_BR_W28_PRE -#define DSP2_MIDDLE2_LUMA_BR_W28_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_BR_W28_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W28_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W28_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W28_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W28_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W28_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W28_PRE_POS)) - -/* 0x8AC : BDM_43 */ -#define DSP2_MIDDLE2_BDM_43_OFFSET (0x8AC) -#define DSP2_MIDDLE2_LUMA_BR_W31_PRE DSP2_MIDDLE2_LUMA_BR_W31_PRE -#define DSP2_MIDDLE2_LUMA_BR_W31_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_BR_W31_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W31_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W31_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W31_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W31_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W31_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W31_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_BR_W30_PRE DSP2_MIDDLE2_LUMA_BR_W30_PRE -#define DSP2_MIDDLE2_LUMA_BR_W30_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_BR_W30_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W30_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W30_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W30_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W30_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W30_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W30_PRE_POS)) - -/* 0x8B0 : BDM_44 */ -#define DSP2_MIDDLE2_BDM_44_OFFSET (0x8B0) -#define DSP2_MIDDLE2_G_COREW_PRE DSP2_MIDDLE2_G_COREW_PRE -#define DSP2_MIDDLE2_G_COREW_PRE_POS (0U) -#define DSP2_MIDDLE2_G_COREW_PRE_LEN (8U) -#define DSP2_MIDDLE2_G_COREW_PRE_MSK (((1U << DSP2_MIDDLE2_G_COREW_PRE_LEN) - 1) << DSP2_MIDDLE2_G_COREW_PRE_POS) -#define DSP2_MIDDLE2_G_COREW_PRE_UMSK (~(((1U << DSP2_MIDDLE2_G_COREW_PRE_LEN) - 1) << DSP2_MIDDLE2_G_COREW_PRE_POS)) -#define DSP2_MIDDLE2_BR_COREW_PRE DSP2_MIDDLE2_BR_COREW_PRE -#define DSP2_MIDDLE2_BR_COREW_PRE_POS (8U) -#define DSP2_MIDDLE2_BR_COREW_PRE_LEN (8U) -#define DSP2_MIDDLE2_BR_COREW_PRE_MSK (((1U << DSP2_MIDDLE2_BR_COREW_PRE_LEN) - 1) << DSP2_MIDDLE2_BR_COREW_PRE_POS) -#define DSP2_MIDDLE2_BR_COREW_PRE_UMSK (~(((1U << DSP2_MIDDLE2_BR_COREW_PRE_LEN) - 1) << DSP2_MIDDLE2_BR_COREW_PRE_POS)) - -struct dsp2_middle2_reg { - /* 0x0 reserved */ - uint8_t RESERVED0x0[2048]; - - /* 0x800 : BDM_1 */ - union { - struct - { - uint32_t bdm_eb_pre : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_7 : 7; /* [ 7: 1], rsvd, 0x0 */ - uint32_t gw_thr_pre : 5; /* [12: 8], r/w, 0x5 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t g_scal_factor_pre : 9; /* [24:16], r/w, 0x40 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_1; - - /* 0x804 : BDM_2 */ - union { - struct - { - uint32_t r_scal_factor_pre : 9; /* [ 8: 0], r/w, 0x40 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t b_scal_factor_pre : 9; /* [24:16], r/w, 0x40 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_2; - - /* 0x808 : BDM_3 */ - union { - struct - { - uint32_t nr_profile10_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t nr_profile00_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_3; - - /* 0x80C : BDM_4 */ - union { - struct - { - uint32_t nr_profile30_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t nr_profile20_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_4; - - /* 0x810 : BDM_5 */ - union { - struct - { - uint32_t nr_profile50_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t nr_profile40_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_5; - - /* 0x814 : BDM_6 */ - union { - struct - { - uint32_t nr_profile01_pre : 17; /* [16: 0], r/w, 0x0 */ - uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_6; - - /* 0x818 : BDM_7 */ - union { - struct - { - uint32_t nr_profile11_pre : 17; /* [16: 0], r/w, 0x0 */ - uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_7; - - /* 0x81C : BDM_8 */ - union { - struct - { - uint32_t nr_profile21_pre : 17; /* [16: 0], r/w, 0x0 */ - uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_8; - - /* 0x820 : BDM_9 */ - union { - struct - { - uint32_t nr_profile31_pre : 17; /* [16: 0], r/w, 0x0 */ - uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_9; - - /* 0x824 : BDM_10 */ - union { - struct - { - uint32_t nr_profile41_pre : 17; /* [16: 0], r/w, 0x0 */ - uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_10; - - /* 0x828 : BDM_11 */ - union { - struct - { - uint32_t nr_profile51_pre : 17; /* [16: 0], r/w, 0x0 */ - uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_11; - - /* 0x82C : BDM_12 */ - union { - struct - { - uint32_t luma_g_w1_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_g_w0_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_12; - - /* 0x830 : BDM_13 */ - union { - struct - { - uint32_t luma_g_w3_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_g_w2_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_13; - - /* 0x834 : BDM_14 */ - union { - struct - { - uint32_t luma_g_w5_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_g_w4_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_14; - - /* 0x838 : BDM_15 */ - union { - struct - { - uint32_t luma_g_w7_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_g_w6_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_15; - - /* 0x83C : BDM_16 */ - union { - struct - { - uint32_t luma_g_w9_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_g_w8_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_16; - - /* 0x840 : BDM_17 */ - union { - struct - { - uint32_t luma_g_w11_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_g_w10_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_17; - - /* 0x844 : BDM_18 */ - union { - struct - { - uint32_t luma_g_w13_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_g_w12_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_18; - - /* 0x848 : BDM_19 */ - union { - struct - { - uint32_t luma_g_w15_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_g_w14_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_19; - - /* 0x84C : BDM_20 */ - union { - struct - { - uint32_t luma_g_w17_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_g_w16_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_20; - - /* 0x850 : BDM_21 */ - union { - struct - { - uint32_t luma_g_w19_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_g_w18_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_21; - - /* 0x854 : BDM_22 */ - union { - struct - { - uint32_t luma_g_w21_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_g_w20_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_22; - - /* 0x858 : BDM_23 */ - union { - struct - { - uint32_t luma_g_w23_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_g_w22_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_23; - - /* 0x85C : BDM_24 */ - union { - struct - { - uint32_t luma_g_w25_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_g_w24_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_24; - - /* 0x860 : BDM_25 */ - union { - struct - { - uint32_t luma_g_w27_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_g_w26_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_25; - - /* 0x864 : BDM_26 */ - union { - struct - { - uint32_t luma_g_w29_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_g_w28_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_26; - - /* 0x868 : BDM_27 */ - union { - struct - { - uint32_t luma_g_w31_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_g_w30_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_27; - - /* 0x86c reserved */ - uint8_t RESERVED0x86c[4]; - - /* 0x870 : BDM_28 */ - union { - struct - { - uint32_t luma_br_w1_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_br_w0_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_28; - - /* 0x874 : BDM_29 */ - union { - struct - { - uint32_t luma_br_w3_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_br_w2_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_29; - - /* 0x878 : BDM_30 */ - union { - struct - { - uint32_t luma_br_w5_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_br_w4_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_30; - - /* 0x87C : BDM_31 */ - union { - struct - { - uint32_t luma_br_w7_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_br_w6_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_31; - - /* 0x880 : BDM_32 */ - union { - struct - { - uint32_t luma_br_w9_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_br_w8_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_32; - - /* 0x884 : BDM_33 */ - union { - struct - { - uint32_t luma_br_w11_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_br_w10_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_33; - - /* 0x888 : BDM_34 */ - union { - struct - { - uint32_t luma_br_w13_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_br_w12_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_34; - - /* 0x88C : BDM_35 */ - union { - struct - { - uint32_t luma_br_w15_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_br_w14_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_35; - - /* 0x890 : BDM_36 */ - union { - struct - { - uint32_t luma_br_w17_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_br_w16_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_36; - - /* 0x894 : BDM_37 */ - union { - struct - { - uint32_t luma_br_w19_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_br_w18_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_37; - - /* 0x898 : BDM_38 */ - union { - struct - { - uint32_t luma_br_w21_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_br_w20_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_38; - - /* 0x89C : BDM_39 */ - union { - struct - { - uint32_t luma_br_w23_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_br_w22_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_39; - - /* 0x8A0 : BDM_40 */ - union { - struct - { - uint32_t luma_br_w25_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_br_w24_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_40; - - /* 0x8A4 : BDM_41 */ - union { - struct - { - uint32_t luma_br_w27_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_br_w26_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_41; - - /* 0x8A8 : BDM_42 */ - union { - struct - { - uint32_t luma_br_w29_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_br_w28_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_42; - - /* 0x8AC : BDM_43 */ - union { - struct - { - uint32_t luma_br_w31_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_br_w30_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_43; - - /* 0x8B0 : BDM_44 */ - union { - struct - { - uint32_t g_corew_pre : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t br_corew_pre : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_44; -}; - -typedef volatile struct dsp2_middle2_reg dsp2_middle2_reg_t; - -#endif /* __DSP2_MIDDLE2_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_middle3_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_middle3_reg.h deleted file mode 100644 index 147fee7bb7..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_middle3_reg.h +++ /dev/null @@ -1,928 +0,0 @@ -/** - ****************************************************************************** - * @file dsp2_middle3_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __DSP2_MIDDLE3_REG_H__ -#define __DSP2_MIDDLE3_REG_H__ - -#include "bl808.h" - -/* 0x500 : awb2_sta_xaxis */ -#define DSP2_MIDDLE3_AWB2_STA_XAXIS_OFFSET (0x500) -#define DSP2_MIDDLE3_AWB2_X_MIN_PRE DSP2_MIDDLE3_AWB2_X_MIN_PRE -#define DSP2_MIDDLE3_AWB2_X_MIN_PRE_POS (0U) -#define DSP2_MIDDLE3_AWB2_X_MIN_PRE_LEN (11U) -#define DSP2_MIDDLE3_AWB2_X_MIN_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_X_MIN_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_X_MIN_PRE_POS) -#define DSP2_MIDDLE3_AWB2_X_MIN_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_X_MIN_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_X_MIN_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_X_MAX_PRE DSP2_MIDDLE3_AWB2_X_MAX_PRE -#define DSP2_MIDDLE3_AWB2_X_MAX_PRE_POS (16U) -#define DSP2_MIDDLE3_AWB2_X_MAX_PRE_LEN (11U) -#define DSP2_MIDDLE3_AWB2_X_MAX_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_X_MAX_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_X_MAX_PRE_POS) -#define DSP2_MIDDLE3_AWB2_X_MAX_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_X_MAX_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_X_MAX_PRE_POS)) - -/* 0x504 : awb2_sta_yaxis */ -#define DSP2_MIDDLE3_AWB2_STA_YAXIS_OFFSET (0x504) -#define DSP2_MIDDLE3_AWB2_Y_MIN_PRE DSP2_MIDDLE3_AWB2_Y_MIN_PRE -#define DSP2_MIDDLE3_AWB2_Y_MIN_PRE_POS (0U) -#define DSP2_MIDDLE3_AWB2_Y_MIN_PRE_LEN (11U) -#define DSP2_MIDDLE3_AWB2_Y_MIN_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_Y_MIN_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_Y_MIN_PRE_POS) -#define DSP2_MIDDLE3_AWB2_Y_MIN_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_Y_MIN_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_Y_MIN_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_Y_MAX_PRE DSP2_MIDDLE3_AWB2_Y_MAX_PRE -#define DSP2_MIDDLE3_AWB2_Y_MAX_PRE_POS (16U) -#define DSP2_MIDDLE3_AWB2_Y_MAX_PRE_LEN (11U) -#define DSP2_MIDDLE3_AWB2_Y_MAX_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_Y_MAX_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_Y_MAX_PRE_POS) -#define DSP2_MIDDLE3_AWB2_Y_MAX_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_Y_MAX_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_Y_MAX_PRE_POS)) - -/* 0x508 : awb2_sta_pixel_num */ -#define DSP2_MIDDLE3_AWB2_STA_PIXEL_NUM_OFFSET (0x508) -#define DSP2_MIDDLE3_AWB2_PIXEL_NUM_PRE DSP2_MIDDLE3_AWB2_PIXEL_NUM_PRE -#define DSP2_MIDDLE3_AWB2_PIXEL_NUM_PRE_POS (0U) -#define DSP2_MIDDLE3_AWB2_PIXEL_NUM_PRE_LEN (21U) -#define DSP2_MIDDLE3_AWB2_PIXEL_NUM_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_PIXEL_NUM_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_PIXEL_NUM_PRE_POS) -#define DSP2_MIDDLE3_AWB2_PIXEL_NUM_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_PIXEL_NUM_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_PIXEL_NUM_PRE_POS)) - -/* 0x50C : awb2_sta_gain0 */ -#define DSP2_MIDDLE3_AWB2_STA_GAIN0_OFFSET (0x50C) -#define DSP2_MIDDLE3_AWB2_STAT_GGAIN_PRE DSP2_MIDDLE3_AWB2_STAT_GGAIN_PRE -#define DSP2_MIDDLE3_AWB2_STAT_GGAIN_PRE_POS (0U) -#define DSP2_MIDDLE3_AWB2_STAT_GGAIN_PRE_LEN (16U) -#define DSP2_MIDDLE3_AWB2_STAT_GGAIN_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_STAT_GGAIN_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_STAT_GGAIN_PRE_POS) -#define DSP2_MIDDLE3_AWB2_STAT_GGAIN_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_STAT_GGAIN_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_STAT_GGAIN_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_STAT_RGAIN_PRE DSP2_MIDDLE3_AWB2_STAT_RGAIN_PRE -#define DSP2_MIDDLE3_AWB2_STAT_RGAIN_PRE_POS (16U) -#define DSP2_MIDDLE3_AWB2_STAT_RGAIN_PRE_LEN (16U) -#define DSP2_MIDDLE3_AWB2_STAT_RGAIN_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_STAT_RGAIN_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_STAT_RGAIN_PRE_POS) -#define DSP2_MIDDLE3_AWB2_STAT_RGAIN_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_STAT_RGAIN_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_STAT_RGAIN_PRE_POS)) - -/* 0x510 : awb2_sta_gain1 */ -#define DSP2_MIDDLE3_AWB2_STA_GAIN1_OFFSET (0x510) -#define DSP2_MIDDLE3_AWB2_RGAIN_PRE DSP2_MIDDLE3_AWB2_RGAIN_PRE -#define DSP2_MIDDLE3_AWB2_RGAIN_PRE_POS (0U) -#define DSP2_MIDDLE3_AWB2_RGAIN_PRE_LEN (16U) -#define DSP2_MIDDLE3_AWB2_RGAIN_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_RGAIN_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_RGAIN_PRE_POS) -#define DSP2_MIDDLE3_AWB2_RGAIN_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_RGAIN_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_RGAIN_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_STAT_BGAIN_PRE DSP2_MIDDLE3_AWB2_STAT_BGAIN_PRE -#define DSP2_MIDDLE3_AWB2_STAT_BGAIN_PRE_POS (16U) -#define DSP2_MIDDLE3_AWB2_STAT_BGAIN_PRE_LEN (16U) -#define DSP2_MIDDLE3_AWB2_STAT_BGAIN_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_STAT_BGAIN_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_STAT_BGAIN_PRE_POS) -#define DSP2_MIDDLE3_AWB2_STAT_BGAIN_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_STAT_BGAIN_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_STAT_BGAIN_PRE_POS)) - -/* 0x514 : awb2_sta_gain2 */ -#define DSP2_MIDDLE3_AWB2_STA_GAIN2_OFFSET (0x514) -#define DSP2_MIDDLE3_AWB2_BGAIN_PRE DSP2_MIDDLE3_AWB2_BGAIN_PRE -#define DSP2_MIDDLE3_AWB2_BGAIN_PRE_POS (0U) -#define DSP2_MIDDLE3_AWB2_BGAIN_PRE_LEN (16U) -#define DSP2_MIDDLE3_AWB2_BGAIN_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_BGAIN_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_BGAIN_PRE_POS) -#define DSP2_MIDDLE3_AWB2_BGAIN_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_BGAIN_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_BGAIN_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_GGAIN_PRE DSP2_MIDDLE3_AWB2_GGAIN_PRE -#define DSP2_MIDDLE3_AWB2_GGAIN_PRE_POS (16U) -#define DSP2_MIDDLE3_AWB2_GGAIN_PRE_LEN (16U) -#define DSP2_MIDDLE3_AWB2_GGAIN_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_GGAIN_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_GGAIN_PRE_POS) -#define DSP2_MIDDLE3_AWB2_GGAIN_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_GGAIN_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_GGAIN_PRE_POS)) - -/* 0x518 : awb2_sta_gain3 */ -#define DSP2_MIDDLE3_AWB2_STA_GAIN3_OFFSET (0x518) -#define DSP2_MIDDLE3_AWB2_VGAIN_PRE DSP2_MIDDLE3_AWB2_VGAIN_PRE -#define DSP2_MIDDLE3_AWB2_VGAIN_PRE_POS (0U) -#define DSP2_MIDDLE3_AWB2_VGAIN_PRE_LEN (10U) -#define DSP2_MIDDLE3_AWB2_VGAIN_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_VGAIN_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_VGAIN_PRE_POS) -#define DSP2_MIDDLE3_AWB2_VGAIN_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_VGAIN_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_VGAIN_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_UGAIN_PRE DSP2_MIDDLE3_AWB2_UGAIN_PRE -#define DSP2_MIDDLE3_AWB2_UGAIN_PRE_POS (16U) -#define DSP2_MIDDLE3_AWB2_UGAIN_PRE_LEN (10U) -#define DSP2_MIDDLE3_AWB2_UGAIN_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_UGAIN_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_UGAIN_PRE_POS) -#define DSP2_MIDDLE3_AWB2_UGAIN_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_UGAIN_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_UGAIN_PRE_POS)) - -/* 0x51C : awb2_sta_l0 */ -#define DSP2_MIDDLE3_AWB2_STA_L0_OFFSET (0x51C) -#define DSP2_MIDDLE3_AWB2_YTH1_PRE DSP2_MIDDLE3_AWB2_YTH1_PRE -#define DSP2_MIDDLE3_AWB2_YTH1_PRE_POS (0U) -#define DSP2_MIDDLE3_AWB2_YTH1_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_YTH1_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_YTH1_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YTH1_PRE_POS) -#define DSP2_MIDDLE3_AWB2_YTH1_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_YTH1_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YTH1_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_YTH2_PRE DSP2_MIDDLE3_AWB2_YTH2_PRE -#define DSP2_MIDDLE3_AWB2_YTH2_PRE_POS (8U) -#define DSP2_MIDDLE3_AWB2_YTH2_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_YTH2_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_YTH2_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YTH2_PRE_POS) -#define DSP2_MIDDLE3_AWB2_YTH2_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_YTH2_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YTH2_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_YTH3_PRE DSP2_MIDDLE3_AWB2_YTH3_PRE -#define DSP2_MIDDLE3_AWB2_YTH3_PRE_POS (16U) -#define DSP2_MIDDLE3_AWB2_YTH3_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_YTH3_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_YTH3_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YTH3_PRE_POS) -#define DSP2_MIDDLE3_AWB2_YTH3_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_YTH3_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YTH3_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_YTH4_PRE DSP2_MIDDLE3_AWB2_YTH4_PRE -#define DSP2_MIDDLE3_AWB2_YTH4_PRE_POS (24U) -#define DSP2_MIDDLE3_AWB2_YTH4_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_YTH4_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_YTH4_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YTH4_PRE_POS) -#define DSP2_MIDDLE3_AWB2_YTH4_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_YTH4_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YTH4_PRE_POS)) - -/* 0x520 : awb2_sta_l1 */ -#define DSP2_MIDDLE3_AWB2_STA_L1_OFFSET (0x520) -#define DSP2_MIDDLE3_AWB2_YWEIGHT2_PRE DSP2_MIDDLE3_AWB2_YWEIGHT2_PRE -#define DSP2_MIDDLE3_AWB2_YWEIGHT2_PRE_POS (0U) -#define DSP2_MIDDLE3_AWB2_YWEIGHT2_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_YWEIGHT2_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_YWEIGHT2_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YWEIGHT2_PRE_POS) -#define DSP2_MIDDLE3_AWB2_YWEIGHT2_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_YWEIGHT2_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YWEIGHT2_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_YWEIGHT3_PRE DSP2_MIDDLE3_AWB2_YWEIGHT3_PRE -#define DSP2_MIDDLE3_AWB2_YWEIGHT3_PRE_POS (8U) -#define DSP2_MIDDLE3_AWB2_YWEIGHT3_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_YWEIGHT3_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_YWEIGHT3_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YWEIGHT3_PRE_POS) -#define DSP2_MIDDLE3_AWB2_YWEIGHT3_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_YWEIGHT3_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YWEIGHT3_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_YWEIGHT4_PRE DSP2_MIDDLE3_AWB2_YWEIGHT4_PRE -#define DSP2_MIDDLE3_AWB2_YWEIGHT4_PRE_POS (16U) -#define DSP2_MIDDLE3_AWB2_YWEIGHT4_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_YWEIGHT4_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_YWEIGHT4_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YWEIGHT4_PRE_POS) -#define DSP2_MIDDLE3_AWB2_YWEIGHT4_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_YWEIGHT4_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YWEIGHT4_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_YTH0_PRE DSP2_MIDDLE3_AWB2_YTH0_PRE -#define DSP2_MIDDLE3_AWB2_YTH0_PRE_POS (24U) -#define DSP2_MIDDLE3_AWB2_YTH0_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_YTH0_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_YTH0_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YTH0_PRE_POS) -#define DSP2_MIDDLE3_AWB2_YTH0_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_YTH0_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YTH0_PRE_POS)) - -/* 0x524 : awb2_sta_l2 */ -#define DSP2_MIDDLE3_AWB2_STA_L2_OFFSET (0x524) -#define DSP2_MIDDLE3_AWB2_YSLOPE4_PRE DSP2_MIDDLE3_AWB2_YSLOPE4_PRE -#define DSP2_MIDDLE3_AWB2_YSLOPE4_PRE_POS (0U) -#define DSP2_MIDDLE3_AWB2_YSLOPE4_PRE_LEN (9U) -#define DSP2_MIDDLE3_AWB2_YSLOPE4_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_YSLOPE4_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YSLOPE4_PRE_POS) -#define DSP2_MIDDLE3_AWB2_YSLOPE4_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_YSLOPE4_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YSLOPE4_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_YWEIGHT0_PRE DSP2_MIDDLE3_AWB2_YWEIGHT0_PRE -#define DSP2_MIDDLE3_AWB2_YWEIGHT0_PRE_POS (16U) -#define DSP2_MIDDLE3_AWB2_YWEIGHT0_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_YWEIGHT0_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_YWEIGHT0_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YWEIGHT0_PRE_POS) -#define DSP2_MIDDLE3_AWB2_YWEIGHT0_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_YWEIGHT0_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YWEIGHT0_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_YWEIGHT1_PRE DSP2_MIDDLE3_AWB2_YWEIGHT1_PRE -#define DSP2_MIDDLE3_AWB2_YWEIGHT1_PRE_POS (24U) -#define DSP2_MIDDLE3_AWB2_YWEIGHT1_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_YWEIGHT1_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_YWEIGHT1_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YWEIGHT1_PRE_POS) -#define DSP2_MIDDLE3_AWB2_YWEIGHT1_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_YWEIGHT1_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YWEIGHT1_PRE_POS)) - -/* 0x528 : awb2_sta_l3 */ -#define DSP2_MIDDLE3_AWB2_STA_L3_OFFSET (0x528) -#define DSP2_MIDDLE3_AWB2_YSLOPE2_PRE DSP2_MIDDLE3_AWB2_YSLOPE2_PRE -#define DSP2_MIDDLE3_AWB2_YSLOPE2_PRE_POS (0U) -#define DSP2_MIDDLE3_AWB2_YSLOPE2_PRE_LEN (9U) -#define DSP2_MIDDLE3_AWB2_YSLOPE2_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_YSLOPE2_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YSLOPE2_PRE_POS) -#define DSP2_MIDDLE3_AWB2_YSLOPE2_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_YSLOPE2_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YSLOPE2_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_YSLOPE3_PRE DSP2_MIDDLE3_AWB2_YSLOPE3_PRE -#define DSP2_MIDDLE3_AWB2_YSLOPE3_PRE_POS (16U) -#define DSP2_MIDDLE3_AWB2_YSLOPE3_PRE_LEN (9U) -#define DSP2_MIDDLE3_AWB2_YSLOPE3_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_YSLOPE3_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YSLOPE3_PRE_POS) -#define DSP2_MIDDLE3_AWB2_YSLOPE3_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_YSLOPE3_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YSLOPE3_PRE_POS)) - -/* 0x52C : awb2_sta_l4 */ -#define DSP2_MIDDLE3_AWB2_STA_L4_OFFSET (0x52C) -#define DSP2_MIDDLE3_AWB2_YSLOPE0_PRE DSP2_MIDDLE3_AWB2_YSLOPE0_PRE -#define DSP2_MIDDLE3_AWB2_YSLOPE0_PRE_POS (0U) -#define DSP2_MIDDLE3_AWB2_YSLOPE0_PRE_LEN (9U) -#define DSP2_MIDDLE3_AWB2_YSLOPE0_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_YSLOPE0_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YSLOPE0_PRE_POS) -#define DSP2_MIDDLE3_AWB2_YSLOPE0_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_YSLOPE0_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YSLOPE0_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_YSLOPE1_PRE DSP2_MIDDLE3_AWB2_YSLOPE1_PRE -#define DSP2_MIDDLE3_AWB2_YSLOPE1_PRE_POS (16U) -#define DSP2_MIDDLE3_AWB2_YSLOPE1_PRE_LEN (9U) -#define DSP2_MIDDLE3_AWB2_YSLOPE1_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_YSLOPE1_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YSLOPE1_PRE_POS) -#define DSP2_MIDDLE3_AWB2_YSLOPE1_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_YSLOPE1_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YSLOPE1_PRE_POS)) - -/* 0x530 : awb2_sta_c0 */ -#define DSP2_MIDDLE3_AWB2_STA_C0_OFFSET (0x530) -#define DSP2_MIDDLE3_AWB2_UREG4_PRE DSP2_MIDDLE3_AWB2_UREG4_PRE -#define DSP2_MIDDLE3_AWB2_UREG4_PRE_POS (0U) -#define DSP2_MIDDLE3_AWB2_UREG4_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_UREG4_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_UREG4_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_UREG4_PRE_POS) -#define DSP2_MIDDLE3_AWB2_UREG4_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_UREG4_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_UREG4_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_UREG5_PRE DSP2_MIDDLE3_AWB2_UREG5_PRE -#define DSP2_MIDDLE3_AWB2_UREG5_PRE_POS (8U) -#define DSP2_MIDDLE3_AWB2_UREG5_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_UREG5_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_UREG5_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_UREG5_PRE_POS) -#define DSP2_MIDDLE3_AWB2_UREG5_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_UREG5_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_UREG5_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_UREG6_PRE DSP2_MIDDLE3_AWB2_UREG6_PRE -#define DSP2_MIDDLE3_AWB2_UREG6_PRE_POS (16U) -#define DSP2_MIDDLE3_AWB2_UREG6_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_UREG6_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_UREG6_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_UREG6_PRE_POS) -#define DSP2_MIDDLE3_AWB2_UREG6_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_UREG6_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_UREG6_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_UREG7_PRE DSP2_MIDDLE3_AWB2_UREG7_PRE -#define DSP2_MIDDLE3_AWB2_UREG7_PRE_POS (24U) -#define DSP2_MIDDLE3_AWB2_UREG7_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_UREG7_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_UREG7_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_UREG7_PRE_POS) -#define DSP2_MIDDLE3_AWB2_UREG7_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_UREG7_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_UREG7_PRE_POS)) - -/* 0x534 : awb2_sta_c1 */ -#define DSP2_MIDDLE3_AWB2_STA_C1_OFFSET (0x534) -#define DSP2_MIDDLE3_AWB2_UREG0_PRE DSP2_MIDDLE3_AWB2_UREG0_PRE -#define DSP2_MIDDLE3_AWB2_UREG0_PRE_POS (0U) -#define DSP2_MIDDLE3_AWB2_UREG0_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_UREG0_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_UREG0_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_UREG0_PRE_POS) -#define DSP2_MIDDLE3_AWB2_UREG0_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_UREG0_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_UREG0_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_UREG1_PRE DSP2_MIDDLE3_AWB2_UREG1_PRE -#define DSP2_MIDDLE3_AWB2_UREG1_PRE_POS (8U) -#define DSP2_MIDDLE3_AWB2_UREG1_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_UREG1_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_UREG1_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_UREG1_PRE_POS) -#define DSP2_MIDDLE3_AWB2_UREG1_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_UREG1_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_UREG1_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_UREG2_PRE DSP2_MIDDLE3_AWB2_UREG2_PRE -#define DSP2_MIDDLE3_AWB2_UREG2_PRE_POS (16U) -#define DSP2_MIDDLE3_AWB2_UREG2_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_UREG2_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_UREG2_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_UREG2_PRE_POS) -#define DSP2_MIDDLE3_AWB2_UREG2_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_UREG2_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_UREG2_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_UREG3_PRE DSP2_MIDDLE3_AWB2_UREG3_PRE -#define DSP2_MIDDLE3_AWB2_UREG3_PRE_POS (24U) -#define DSP2_MIDDLE3_AWB2_UREG3_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_UREG3_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_UREG3_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_UREG3_PRE_POS) -#define DSP2_MIDDLE3_AWB2_UREG3_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_UREG3_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_UREG3_PRE_POS)) - -/* 0x538 : awb2_sta_c2 */ -#define DSP2_MIDDLE3_AWB2_STA_C2_OFFSET (0x538) -#define DSP2_MIDDLE3_AWB2_VREG4_PRE DSP2_MIDDLE3_AWB2_VREG4_PRE -#define DSP2_MIDDLE3_AWB2_VREG4_PRE_POS (0U) -#define DSP2_MIDDLE3_AWB2_VREG4_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_VREG4_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_VREG4_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_VREG4_PRE_POS) -#define DSP2_MIDDLE3_AWB2_VREG4_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_VREG4_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_VREG4_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_VREG5_PRE DSP2_MIDDLE3_AWB2_VREG5_PRE -#define DSP2_MIDDLE3_AWB2_VREG5_PRE_POS (8U) -#define DSP2_MIDDLE3_AWB2_VREG5_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_VREG5_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_VREG5_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_VREG5_PRE_POS) -#define DSP2_MIDDLE3_AWB2_VREG5_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_VREG5_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_VREG5_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_VREG6_PRE DSP2_MIDDLE3_AWB2_VREG6_PRE -#define DSP2_MIDDLE3_AWB2_VREG6_PRE_POS (16U) -#define DSP2_MIDDLE3_AWB2_VREG6_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_VREG6_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_VREG6_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_VREG6_PRE_POS) -#define DSP2_MIDDLE3_AWB2_VREG6_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_VREG6_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_VREG6_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_VREG7_PRE DSP2_MIDDLE3_AWB2_VREG7_PRE -#define DSP2_MIDDLE3_AWB2_VREG7_PRE_POS (24U) -#define DSP2_MIDDLE3_AWB2_VREG7_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_VREG7_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_VREG7_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_VREG7_PRE_POS) -#define DSP2_MIDDLE3_AWB2_VREG7_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_VREG7_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_VREG7_PRE_POS)) - -/* 0x53C : awb2_sta_c3 */ -#define DSP2_MIDDLE3_AWB2_STA_C3_OFFSET (0x53C) -#define DSP2_MIDDLE3_AWB2_VREG0_PRE DSP2_MIDDLE3_AWB2_VREG0_PRE -#define DSP2_MIDDLE3_AWB2_VREG0_PRE_POS (0U) -#define DSP2_MIDDLE3_AWB2_VREG0_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_VREG0_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_VREG0_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_VREG0_PRE_POS) -#define DSP2_MIDDLE3_AWB2_VREG0_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_VREG0_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_VREG0_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_VREG1_PRE DSP2_MIDDLE3_AWB2_VREG1_PRE -#define DSP2_MIDDLE3_AWB2_VREG1_PRE_POS (8U) -#define DSP2_MIDDLE3_AWB2_VREG1_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_VREG1_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_VREG1_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_VREG1_PRE_POS) -#define DSP2_MIDDLE3_AWB2_VREG1_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_VREG1_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_VREG1_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_VREG2_PRE DSP2_MIDDLE3_AWB2_VREG2_PRE -#define DSP2_MIDDLE3_AWB2_VREG2_PRE_POS (16U) -#define DSP2_MIDDLE3_AWB2_VREG2_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_VREG2_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_VREG2_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_VREG2_PRE_POS) -#define DSP2_MIDDLE3_AWB2_VREG2_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_VREG2_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_VREG2_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_VREG3_PRE DSP2_MIDDLE3_AWB2_VREG3_PRE -#define DSP2_MIDDLE3_AWB2_VREG3_PRE_POS (24U) -#define DSP2_MIDDLE3_AWB2_VREG3_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_VREG3_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_VREG3_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_VREG3_PRE_POS) -#define DSP2_MIDDLE3_AWB2_VREG3_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_VREG3_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_VREG3_PRE_POS)) - -/* 0x540 : awb2_sta_c4 */ -#define DSP2_MIDDLE3_AWB2_STA_C4_OFFSET (0x540) -#define DSP2_MIDDLE3_AWB2_CTH4_PRE DSP2_MIDDLE3_AWB2_CTH4_PRE -#define DSP2_MIDDLE3_AWB2_CTH4_PRE_POS (0U) -#define DSP2_MIDDLE3_AWB2_CTH4_PRE_LEN (6U) -#define DSP2_MIDDLE3_AWB2_CTH4_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_CTH4_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CTH4_PRE_POS) -#define DSP2_MIDDLE3_AWB2_CTH4_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_CTH4_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CTH4_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_CTH5_PRE DSP2_MIDDLE3_AWB2_CTH5_PRE -#define DSP2_MIDDLE3_AWB2_CTH5_PRE_POS (8U) -#define DSP2_MIDDLE3_AWB2_CTH5_PRE_LEN (6U) -#define DSP2_MIDDLE3_AWB2_CTH5_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_CTH5_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CTH5_PRE_POS) -#define DSP2_MIDDLE3_AWB2_CTH5_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_CTH5_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CTH5_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_CTH6_PRE DSP2_MIDDLE3_AWB2_CTH6_PRE -#define DSP2_MIDDLE3_AWB2_CTH6_PRE_POS (16U) -#define DSP2_MIDDLE3_AWB2_CTH6_PRE_LEN (6U) -#define DSP2_MIDDLE3_AWB2_CTH6_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_CTH6_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CTH6_PRE_POS) -#define DSP2_MIDDLE3_AWB2_CTH6_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_CTH6_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CTH6_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_CTH7_PRE DSP2_MIDDLE3_AWB2_CTH7_PRE -#define DSP2_MIDDLE3_AWB2_CTH7_PRE_POS (24U) -#define DSP2_MIDDLE3_AWB2_CTH7_PRE_LEN (6U) -#define DSP2_MIDDLE3_AWB2_CTH7_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_CTH7_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CTH7_PRE_POS) -#define DSP2_MIDDLE3_AWB2_CTH7_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_CTH7_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CTH7_PRE_POS)) - -/* 0x544 : awb2_sta_c5 */ -#define DSP2_MIDDLE3_AWB2_STA_C5_OFFSET (0x544) -#define DSP2_MIDDLE3_AWB2_CTH0_PRE DSP2_MIDDLE3_AWB2_CTH0_PRE -#define DSP2_MIDDLE3_AWB2_CTH0_PRE_POS (0U) -#define DSP2_MIDDLE3_AWB2_CTH0_PRE_LEN (6U) -#define DSP2_MIDDLE3_AWB2_CTH0_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_CTH0_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CTH0_PRE_POS) -#define DSP2_MIDDLE3_AWB2_CTH0_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_CTH0_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CTH0_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_CTH1_PRE DSP2_MIDDLE3_AWB2_CTH1_PRE -#define DSP2_MIDDLE3_AWB2_CTH1_PRE_POS (8U) -#define DSP2_MIDDLE3_AWB2_CTH1_PRE_LEN (6U) -#define DSP2_MIDDLE3_AWB2_CTH1_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_CTH1_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CTH1_PRE_POS) -#define DSP2_MIDDLE3_AWB2_CTH1_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_CTH1_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CTH1_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_CTH2_PRE DSP2_MIDDLE3_AWB2_CTH2_PRE -#define DSP2_MIDDLE3_AWB2_CTH2_PRE_POS (16U) -#define DSP2_MIDDLE3_AWB2_CTH2_PRE_LEN (6U) -#define DSP2_MIDDLE3_AWB2_CTH2_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_CTH2_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CTH2_PRE_POS) -#define DSP2_MIDDLE3_AWB2_CTH2_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_CTH2_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CTH2_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_CTH3_PRE DSP2_MIDDLE3_AWB2_CTH3_PRE -#define DSP2_MIDDLE3_AWB2_CTH3_PRE_POS (24U) -#define DSP2_MIDDLE3_AWB2_CTH3_PRE_LEN (6U) -#define DSP2_MIDDLE3_AWB2_CTH3_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_CTH3_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CTH3_PRE_POS) -#define DSP2_MIDDLE3_AWB2_CTH3_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_CTH3_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CTH3_PRE_POS)) - -/* 0x548 : awb2_sta_c6 */ -#define DSP2_MIDDLE3_AWB2_STA_C6_OFFSET (0x548) -#define DSP2_MIDDLE3_AWB2_CSLOPE4_PRE DSP2_MIDDLE3_AWB2_CSLOPE4_PRE -#define DSP2_MIDDLE3_AWB2_CSLOPE4_PRE_POS (0U) -#define DSP2_MIDDLE3_AWB2_CSLOPE4_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_CSLOPE4_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_CSLOPE4_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CSLOPE4_PRE_POS) -#define DSP2_MIDDLE3_AWB2_CSLOPE4_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_CSLOPE4_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CSLOPE4_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_CSLOPE5_PRE DSP2_MIDDLE3_AWB2_CSLOPE5_PRE -#define DSP2_MIDDLE3_AWB2_CSLOPE5_PRE_POS (8U) -#define DSP2_MIDDLE3_AWB2_CSLOPE5_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_CSLOPE5_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_CSLOPE5_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CSLOPE5_PRE_POS) -#define DSP2_MIDDLE3_AWB2_CSLOPE5_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_CSLOPE5_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CSLOPE5_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_CSLOPE6_PRE DSP2_MIDDLE3_AWB2_CSLOPE6_PRE -#define DSP2_MIDDLE3_AWB2_CSLOPE6_PRE_POS (16U) -#define DSP2_MIDDLE3_AWB2_CSLOPE6_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_CSLOPE6_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_CSLOPE6_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CSLOPE6_PRE_POS) -#define DSP2_MIDDLE3_AWB2_CSLOPE6_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_CSLOPE6_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CSLOPE6_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_CSLOPE7_PRE DSP2_MIDDLE3_AWB2_CSLOPE7_PRE -#define DSP2_MIDDLE3_AWB2_CSLOPE7_PRE_POS (24U) -#define DSP2_MIDDLE3_AWB2_CSLOPE7_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_CSLOPE7_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_CSLOPE7_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CSLOPE7_PRE_POS) -#define DSP2_MIDDLE3_AWB2_CSLOPE7_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_CSLOPE7_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CSLOPE7_PRE_POS)) - -/* 0x54C : awb2_sta_c7 */ -#define DSP2_MIDDLE3_AWB2_STA_C7_OFFSET (0x54C) -#define DSP2_MIDDLE3_AWB2_CSLOPE0_PRE DSP2_MIDDLE3_AWB2_CSLOPE0_PRE -#define DSP2_MIDDLE3_AWB2_CSLOPE0_PRE_POS (0U) -#define DSP2_MIDDLE3_AWB2_CSLOPE0_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_CSLOPE0_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_CSLOPE0_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CSLOPE0_PRE_POS) -#define DSP2_MIDDLE3_AWB2_CSLOPE0_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_CSLOPE0_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CSLOPE0_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_CSLOPE1_PRE DSP2_MIDDLE3_AWB2_CSLOPE1_PRE -#define DSP2_MIDDLE3_AWB2_CSLOPE1_PRE_POS (8U) -#define DSP2_MIDDLE3_AWB2_CSLOPE1_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_CSLOPE1_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_CSLOPE1_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CSLOPE1_PRE_POS) -#define DSP2_MIDDLE3_AWB2_CSLOPE1_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_CSLOPE1_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CSLOPE1_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_CSLOPE2_PRE DSP2_MIDDLE3_AWB2_CSLOPE2_PRE -#define DSP2_MIDDLE3_AWB2_CSLOPE2_PRE_POS (16U) -#define DSP2_MIDDLE3_AWB2_CSLOPE2_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_CSLOPE2_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_CSLOPE2_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CSLOPE2_PRE_POS) -#define DSP2_MIDDLE3_AWB2_CSLOPE2_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_CSLOPE2_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CSLOPE2_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_CSLOPE3_PRE DSP2_MIDDLE3_AWB2_CSLOPE3_PRE -#define DSP2_MIDDLE3_AWB2_CSLOPE3_PRE_POS (24U) -#define DSP2_MIDDLE3_AWB2_CSLOPE3_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_CSLOPE3_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_CSLOPE3_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CSLOPE3_PRE_POS) -#define DSP2_MIDDLE3_AWB2_CSLOPE3_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_CSLOPE3_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CSLOPE3_PRE_POS)) - -/* 0x550 : awb2_sta_r0 */ -#define DSP2_MIDDLE3_AWB2_STA_R0_OFFSET (0x550) -#define DSP2_MIDDLE3_AWB2_G_AVG0_R DSP2_MIDDLE3_AWB2_G_AVG0_R -#define DSP2_MIDDLE3_AWB2_G_AVG0_R_POS (0U) -#define DSP2_MIDDLE3_AWB2_G_AVG0_R_LEN (12U) -#define DSP2_MIDDLE3_AWB2_G_AVG0_R_MSK (((1U << DSP2_MIDDLE3_AWB2_G_AVG0_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_G_AVG0_R_POS) -#define DSP2_MIDDLE3_AWB2_G_AVG0_R_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_G_AVG0_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_G_AVG0_R_POS)) -#define DSP2_MIDDLE3_AWB2_R_AVG0_R DSP2_MIDDLE3_AWB2_R_AVG0_R -#define DSP2_MIDDLE3_AWB2_R_AVG0_R_POS (16U) -#define DSP2_MIDDLE3_AWB2_R_AVG0_R_LEN (12U) -#define DSP2_MIDDLE3_AWB2_R_AVG0_R_MSK (((1U << DSP2_MIDDLE3_AWB2_R_AVG0_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_R_AVG0_R_POS) -#define DSP2_MIDDLE3_AWB2_R_AVG0_R_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_R_AVG0_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_R_AVG0_R_POS)) - -/* 0x554 : awb2_sta_r1 */ -#define DSP2_MIDDLE3_AWB2_STA_R1_OFFSET (0x554) -#define DSP2_MIDDLE3_AWB2_WHITE_RATIO0_R DSP2_MIDDLE3_AWB2_WHITE_RATIO0_R -#define DSP2_MIDDLE3_AWB2_WHITE_RATIO0_R_POS (0U) -#define DSP2_MIDDLE3_AWB2_WHITE_RATIO0_R_LEN (15U) -#define DSP2_MIDDLE3_AWB2_WHITE_RATIO0_R_MSK (((1U << DSP2_MIDDLE3_AWB2_WHITE_RATIO0_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITE_RATIO0_R_POS) -#define DSP2_MIDDLE3_AWB2_WHITE_RATIO0_R_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_WHITE_RATIO0_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITE_RATIO0_R_POS)) -#define DSP2_MIDDLE3_AWB2_B_AVG0_R DSP2_MIDDLE3_AWB2_B_AVG0_R -#define DSP2_MIDDLE3_AWB2_B_AVG0_R_POS (16U) -#define DSP2_MIDDLE3_AWB2_B_AVG0_R_LEN (12U) -#define DSP2_MIDDLE3_AWB2_B_AVG0_R_MSK (((1U << DSP2_MIDDLE3_AWB2_B_AVG0_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_B_AVG0_R_POS) -#define DSP2_MIDDLE3_AWB2_B_AVG0_R_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_B_AVG0_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_B_AVG0_R_POS)) - -/* 0x558 : awb2_sta_r2 */ -#define DSP2_MIDDLE3_AWB2_STA_R2_OFFSET (0x558) -#define DSP2_MIDDLE3_AWB2_G_AVG1_R DSP2_MIDDLE3_AWB2_G_AVG1_R -#define DSP2_MIDDLE3_AWB2_G_AVG1_R_POS (0U) -#define DSP2_MIDDLE3_AWB2_G_AVG1_R_LEN (12U) -#define DSP2_MIDDLE3_AWB2_G_AVG1_R_MSK (((1U << DSP2_MIDDLE3_AWB2_G_AVG1_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_G_AVG1_R_POS) -#define DSP2_MIDDLE3_AWB2_G_AVG1_R_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_G_AVG1_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_G_AVG1_R_POS)) -#define DSP2_MIDDLE3_AWB2_R_AVG1_R DSP2_MIDDLE3_AWB2_R_AVG1_R -#define DSP2_MIDDLE3_AWB2_R_AVG1_R_POS (16U) -#define DSP2_MIDDLE3_AWB2_R_AVG1_R_LEN (12U) -#define DSP2_MIDDLE3_AWB2_R_AVG1_R_MSK (((1U << DSP2_MIDDLE3_AWB2_R_AVG1_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_R_AVG1_R_POS) -#define DSP2_MIDDLE3_AWB2_R_AVG1_R_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_R_AVG1_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_R_AVG1_R_POS)) - -/* 0x55C : awb2_sta_r3 */ -#define DSP2_MIDDLE3_AWB2_STA_R3_OFFSET (0x55C) -#define DSP2_MIDDLE3_AWB2_WHITE_RATIO1_R DSP2_MIDDLE3_AWB2_WHITE_RATIO1_R -#define DSP2_MIDDLE3_AWB2_WHITE_RATIO1_R_POS (0U) -#define DSP2_MIDDLE3_AWB2_WHITE_RATIO1_R_LEN (15U) -#define DSP2_MIDDLE3_AWB2_WHITE_RATIO1_R_MSK (((1U << DSP2_MIDDLE3_AWB2_WHITE_RATIO1_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITE_RATIO1_R_POS) -#define DSP2_MIDDLE3_AWB2_WHITE_RATIO1_R_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_WHITE_RATIO1_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITE_RATIO1_R_POS)) -#define DSP2_MIDDLE3_AWB2_B_AVG1_R DSP2_MIDDLE3_AWB2_B_AVG1_R -#define DSP2_MIDDLE3_AWB2_B_AVG1_R_POS (16U) -#define DSP2_MIDDLE3_AWB2_B_AVG1_R_LEN (12U) -#define DSP2_MIDDLE3_AWB2_B_AVG1_R_MSK (((1U << DSP2_MIDDLE3_AWB2_B_AVG1_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_B_AVG1_R_POS) -#define DSP2_MIDDLE3_AWB2_B_AVG1_R_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_B_AVG1_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_B_AVG1_R_POS)) - -/* 0x560 : awb2_sta_r4 */ -#define DSP2_MIDDLE3_AWB2_STA_R4_OFFSET (0x560) -#define DSP2_MIDDLE3_AWB2_WHITER_SUMH0_R DSP2_MIDDLE3_AWB2_WHITER_SUMH0_R -#define DSP2_MIDDLE3_AWB2_WHITER_SUMH0_R_POS (0U) -#define DSP2_MIDDLE3_AWB2_WHITER_SUMH0_R_LEN (32U) -#define DSP2_MIDDLE3_AWB2_WHITER_SUMH0_R_MSK (((1U << DSP2_MIDDLE3_AWB2_WHITER_SUMH0_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITER_SUMH0_R_POS) -#define DSP2_MIDDLE3_AWB2_WHITER_SUMH0_R_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_WHITER_SUMH0_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITER_SUMH0_R_POS)) - -/* 0x564 : awb2_sta_r5 */ -#define DSP2_MIDDLE3_AWB2_STA_R5_OFFSET (0x564) -#define DSP2_MIDDLE3_AWB2_WHITER_SUML1_R DSP2_MIDDLE3_AWB2_WHITER_SUML1_R -#define DSP2_MIDDLE3_AWB2_WHITER_SUML1_R_POS (0U) -#define DSP2_MIDDLE3_AWB2_WHITER_SUML1_R_LEN (9U) -#define DSP2_MIDDLE3_AWB2_WHITER_SUML1_R_MSK (((1U << DSP2_MIDDLE3_AWB2_WHITER_SUML1_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITER_SUML1_R_POS) -#define DSP2_MIDDLE3_AWB2_WHITER_SUML1_R_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_WHITER_SUML1_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITER_SUML1_R_POS)) -#define DSP2_MIDDLE3_AWB2_WHITER_SUML0_R DSP2_MIDDLE3_AWB2_WHITER_SUML0_R -#define DSP2_MIDDLE3_AWB2_WHITER_SUML0_R_POS (16U) -#define DSP2_MIDDLE3_AWB2_WHITER_SUML0_R_LEN (9U) -#define DSP2_MIDDLE3_AWB2_WHITER_SUML0_R_MSK (((1U << DSP2_MIDDLE3_AWB2_WHITER_SUML0_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITER_SUML0_R_POS) -#define DSP2_MIDDLE3_AWB2_WHITER_SUML0_R_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_WHITER_SUML0_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITER_SUML0_R_POS)) - -/* 0x568 : awb2_sta_r6 */ -#define DSP2_MIDDLE3_AWB2_STA_R6_OFFSET (0x568) -#define DSP2_MIDDLE3_AWB2_WHITER_SUMH1_R DSP2_MIDDLE3_AWB2_WHITER_SUMH1_R -#define DSP2_MIDDLE3_AWB2_WHITER_SUMH1_R_POS (0U) -#define DSP2_MIDDLE3_AWB2_WHITER_SUMH1_R_LEN (32U) -#define DSP2_MIDDLE3_AWB2_WHITER_SUMH1_R_MSK (((1U << DSP2_MIDDLE3_AWB2_WHITER_SUMH1_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITER_SUMH1_R_POS) -#define DSP2_MIDDLE3_AWB2_WHITER_SUMH1_R_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_WHITER_SUMH1_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITER_SUMH1_R_POS)) - -/* 0x56C : awb2_sta_r7 */ -#define DSP2_MIDDLE3_AWB2_STA_R7_OFFSET (0x56C) -#define DSP2_MIDDLE3_AWB2_WHITEG_SUMH0_R DSP2_MIDDLE3_AWB2_WHITEG_SUMH0_R -#define DSP2_MIDDLE3_AWB2_WHITEG_SUMH0_R_POS (0U) -#define DSP2_MIDDLE3_AWB2_WHITEG_SUMH0_R_LEN (32U) -#define DSP2_MIDDLE3_AWB2_WHITEG_SUMH0_R_MSK (((1U << DSP2_MIDDLE3_AWB2_WHITEG_SUMH0_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITEG_SUMH0_R_POS) -#define DSP2_MIDDLE3_AWB2_WHITEG_SUMH0_R_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_WHITEG_SUMH0_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITEG_SUMH0_R_POS)) - -/* 0x570 : awb2_sta_r8 */ -#define DSP2_MIDDLE3_AWB2_STA_R8_OFFSET (0x570) -#define DSP2_MIDDLE3_AWB2_WHITEG_SUML1_R DSP2_MIDDLE3_AWB2_WHITEG_SUML1_R -#define DSP2_MIDDLE3_AWB2_WHITEG_SUML1_R_POS (0U) -#define DSP2_MIDDLE3_AWB2_WHITEG_SUML1_R_LEN (9U) -#define DSP2_MIDDLE3_AWB2_WHITEG_SUML1_R_MSK (((1U << DSP2_MIDDLE3_AWB2_WHITEG_SUML1_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITEG_SUML1_R_POS) -#define DSP2_MIDDLE3_AWB2_WHITEG_SUML1_R_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_WHITEG_SUML1_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITEG_SUML1_R_POS)) -#define DSP2_MIDDLE3_AWB2_WHITEG_SUML0_R DSP2_MIDDLE3_AWB2_WHITEG_SUML0_R -#define DSP2_MIDDLE3_AWB2_WHITEG_SUML0_R_POS (16U) -#define DSP2_MIDDLE3_AWB2_WHITEG_SUML0_R_LEN (9U) -#define DSP2_MIDDLE3_AWB2_WHITEG_SUML0_R_MSK (((1U << DSP2_MIDDLE3_AWB2_WHITEG_SUML0_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITEG_SUML0_R_POS) -#define DSP2_MIDDLE3_AWB2_WHITEG_SUML0_R_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_WHITEG_SUML0_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITEG_SUML0_R_POS)) - -/* 0x574 : awb2_sta_r9 */ -#define DSP2_MIDDLE3_AWB2_STA_R9_OFFSET (0x574) -#define DSP2_MIDDLE3_AWB2_WHITEG_SUMH1_R DSP2_MIDDLE3_AWB2_WHITEG_SUMH1_R -#define DSP2_MIDDLE3_AWB2_WHITEG_SUMH1_R_POS (0U) -#define DSP2_MIDDLE3_AWB2_WHITEG_SUMH1_R_LEN (32U) -#define DSP2_MIDDLE3_AWB2_WHITEG_SUMH1_R_MSK (((1U << DSP2_MIDDLE3_AWB2_WHITEG_SUMH1_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITEG_SUMH1_R_POS) -#define DSP2_MIDDLE3_AWB2_WHITEG_SUMH1_R_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_WHITEG_SUMH1_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITEG_SUMH1_R_POS)) - -/* 0x578 : awb2_sta_ra */ -#define DSP2_MIDDLE3_AWB2_STA_RA_OFFSET (0x578) -#define DSP2_MIDDLE3_AWB2_WHITEB_SUMH0_R DSP2_MIDDLE3_AWB2_WHITEB_SUMH0_R -#define DSP2_MIDDLE3_AWB2_WHITEB_SUMH0_R_POS (0U) -#define DSP2_MIDDLE3_AWB2_WHITEB_SUMH0_R_LEN (32U) -#define DSP2_MIDDLE3_AWB2_WHITEB_SUMH0_R_MSK (((1U << DSP2_MIDDLE3_AWB2_WHITEB_SUMH0_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITEB_SUMH0_R_POS) -#define DSP2_MIDDLE3_AWB2_WHITEB_SUMH0_R_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_WHITEB_SUMH0_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITEB_SUMH0_R_POS)) - -/* 0x57C : awb2_sta_rb */ -#define DSP2_MIDDLE3_AWB2_STA_RB_OFFSET (0x57C) -#define DSP2_MIDDLE3_AWB2_WHITEB_SUML1_R DSP2_MIDDLE3_AWB2_WHITEB_SUML1_R -#define DSP2_MIDDLE3_AWB2_WHITEB_SUML1_R_POS (0U) -#define DSP2_MIDDLE3_AWB2_WHITEB_SUML1_R_LEN (9U) -#define DSP2_MIDDLE3_AWB2_WHITEB_SUML1_R_MSK (((1U << DSP2_MIDDLE3_AWB2_WHITEB_SUML1_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITEB_SUML1_R_POS) -#define DSP2_MIDDLE3_AWB2_WHITEB_SUML1_R_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_WHITEB_SUML1_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITEB_SUML1_R_POS)) -#define DSP2_MIDDLE3_AWB2_WHITEB_SUML0_R DSP2_MIDDLE3_AWB2_WHITEB_SUML0_R -#define DSP2_MIDDLE3_AWB2_WHITEB_SUML0_R_POS (16U) -#define DSP2_MIDDLE3_AWB2_WHITEB_SUML0_R_LEN (9U) -#define DSP2_MIDDLE3_AWB2_WHITEB_SUML0_R_MSK (((1U << DSP2_MIDDLE3_AWB2_WHITEB_SUML0_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITEB_SUML0_R_POS) -#define DSP2_MIDDLE3_AWB2_WHITEB_SUML0_R_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_WHITEB_SUML0_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITEB_SUML0_R_POS)) - -/* 0x580 : awb2_sta_rc */ -#define DSP2_MIDDLE3_AWB2_STA_RC_OFFSET (0x580) -#define DSP2_MIDDLE3_AWB2_WHITEB_SUMH1_R DSP2_MIDDLE3_AWB2_WHITEB_SUMH1_R -#define DSP2_MIDDLE3_AWB2_WHITEB_SUMH1_R_POS (0U) -#define DSP2_MIDDLE3_AWB2_WHITEB_SUMH1_R_LEN (32U) -#define DSP2_MIDDLE3_AWB2_WHITEB_SUMH1_R_MSK (((1U << DSP2_MIDDLE3_AWB2_WHITEB_SUMH1_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITEB_SUMH1_R_POS) -#define DSP2_MIDDLE3_AWB2_WHITEB_SUMH1_R_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_WHITEB_SUMH1_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITEB_SUMH1_R_POS)) - -/* 0x584 : awb2_sta_int */ -#define DSP2_MIDDLE3_AWB2_STA_INT_OFFSET (0x584) -#define DSP2_MIDDLE3_AWB2_GAIN_EN_PRE DSP2_MIDDLE3_AWB2_GAIN_EN_PRE -#define DSP2_MIDDLE3_AWB2_GAIN_EN_PRE_POS (0U) -#define DSP2_MIDDLE3_AWB2_GAIN_EN_PRE_LEN (1U) -#define DSP2_MIDDLE3_AWB2_GAIN_EN_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_GAIN_EN_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_GAIN_EN_PRE_POS) -#define DSP2_MIDDLE3_AWB2_GAIN_EN_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_GAIN_EN_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_GAIN_EN_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_STAT_EN_PRE DSP2_MIDDLE3_AWB2_STAT_EN_PRE -#define DSP2_MIDDLE3_AWB2_STAT_EN_PRE_POS (1U) -#define DSP2_MIDDLE3_AWB2_STAT_EN_PRE_LEN (1U) -#define DSP2_MIDDLE3_AWB2_STAT_EN_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_STAT_EN_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_STAT_EN_PRE_POS) -#define DSP2_MIDDLE3_AWB2_STAT_EN_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_STAT_EN_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_STAT_EN_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_BUF_IDX_R DSP2_MIDDLE3_AWB2_BUF_IDX_R -#define DSP2_MIDDLE3_AWB2_BUF_IDX_R_POS (2U) -#define DSP2_MIDDLE3_AWB2_BUF_IDX_R_LEN (1U) -#define DSP2_MIDDLE3_AWB2_BUF_IDX_R_MSK (((1U << DSP2_MIDDLE3_AWB2_BUF_IDX_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_BUF_IDX_R_POS) -#define DSP2_MIDDLE3_AWB2_BUF_IDX_R_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_BUF_IDX_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_BUF_IDX_R_POS)) -#define DSP2_MIDDLE3_AWB2_W_CNT_R DSP2_MIDDLE3_AWB2_W_CNT_R -#define DSP2_MIDDLE3_AWB2_W_CNT_R_POS (8U) -#define DSP2_MIDDLE3_AWB2_W_CNT_R_LEN (5U) -#define DSP2_MIDDLE3_AWB2_W_CNT_R_MSK (((1U << DSP2_MIDDLE3_AWB2_W_CNT_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_W_CNT_R_POS) -#define DSP2_MIDDLE3_AWB2_W_CNT_R_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_W_CNT_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_W_CNT_R_POS)) - -struct dsp2_middle3_reg { - /* 0x0 reserved */ - uint8_t RESERVED0x0[1280]; - - /* 0x500 : awb2_sta_xaxis */ - union { - struct { - uint32_t awb2_x_min_pre : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t awb2_x_max_pre : 11; /* [26:16], r/w, 0x77f */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_xaxis; - - /* 0x504 : awb2_sta_yaxis */ - union { - struct { - uint32_t awb2_y_min_pre : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t awb2_y_max_pre : 11; /* [26:16], r/w, 0x437 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_yaxis; - - /* 0x508 : awb2_sta_pixel_num */ - union { - struct { - uint32_t awb2_pixel_num_pre : 21; /* [20: 0], r/w, 0x1fa400 */ - uint32_t reserved_21_31 : 11; /* [31:21], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_pixel_num; - - /* 0x50C : awb2_sta_gain0 */ - union { - struct { - uint32_t awb2_stat_ggain_pre : 16; /* [15: 0], r/w, 0x1000 */ - uint32_t awb2_stat_rgain_pre : 16; /* [31:16], r/w, 0x1000 */ - } BF; - uint32_t WORD; - } awb2_sta_gain0; - - /* 0x510 : awb2_sta_gain1 */ - union { - struct { - uint32_t awb2_rgain_pre : 16; /* [15: 0], r/w, 0x1000 */ - uint32_t awb2_stat_bgain_pre : 16; /* [31:16], r/w, 0x1000 */ - } BF; - uint32_t WORD; - } awb2_sta_gain1; - - /* 0x514 : awb2_sta_gain2 */ - union { - struct { - uint32_t awb2_bgain_pre : 16; /* [15: 0], r/w, 0x1000 */ - uint32_t awb2_ggain_pre : 16; /* [31:16], r/w, 0x1000 */ - } BF; - uint32_t WORD; - } awb2_sta_gain2; - - /* 0x518 : awb2_sta_gain3 */ - union { - struct { - uint32_t awb2_vgain_pre : 10; /* [ 9: 0], r/w, 0x100 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t awb2_ugain_pre : 10; /* [25:16], r/w, 0x100 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_gain3; - - /* 0x51C : awb2_sta_l0 */ - union { - struct { - uint32_t awb2_yth1_pre : 8; /* [ 7: 0], r/w, 0x10 */ - uint32_t awb2_yth2_pre : 8; /* [15: 8], r/w, 0x30 */ - uint32_t awb2_yth3_pre : 8; /* [23:16], r/w, 0xd0 */ - uint32_t awb2_yth4_pre : 8; /* [31:24], r/w, 0xf0 */ - } BF; - uint32_t WORD; - } awb2_sta_l0; - - /* 0x520 : awb2_sta_l1 */ - union { - struct { - uint32_t awb2_yweight2_pre : 8; /* [ 7: 0], r/w, 0xff */ - uint32_t awb2_yweight3_pre : 8; /* [15: 8], r/w, 0xff */ - uint32_t awb2_yweight4_pre : 8; /* [23:16], r/w, 0x0 */ - uint32_t awb2_yth0_pre : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_l1; - - /* 0x524 : awb2_sta_l2 */ - union { - struct { - uint32_t awb2_yslope4_pre : 9; /* [ 8: 0], r/w, 0x0 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t awb2_yweight0_pre : 8; /* [23:16], r/w, 0x0 */ - uint32_t awb2_yweight1_pre : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_l2; - - /* 0x528 : awb2_sta_l3 */ - union { - struct { - uint32_t awb2_yslope2_pre : 9; /* [ 8: 0], r/w, 0x0 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t awb2_yslope3_pre : 9; /* [24:16], r/w, 0x1e0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_l3; - - /* 0x52C : awb2_sta_l4 */ - union { - struct { - uint32_t awb2_yslope0_pre : 9; /* [ 8: 0], r/w, 0x0 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t awb2_yslope1_pre : 9; /* [24:16], r/w, 0x20 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_l4; - - /* 0x530 : awb2_sta_c0 */ - union { - struct { - uint32_t awb2_ureg4_pre : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t awb2_ureg5_pre : 8; /* [15: 8], r/w, 0x0 */ - uint32_t awb2_ureg6_pre : 8; /* [23:16], r/w, 0x0 */ - uint32_t awb2_ureg7_pre : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_c0; - - /* 0x534 : awb2_sta_c1 */ - union { - struct { - uint32_t awb2_ureg0_pre : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t awb2_ureg1_pre : 8; /* [15: 8], r/w, 0x0 */ - uint32_t awb2_ureg2_pre : 8; /* [23:16], r/w, 0x0 */ - uint32_t awb2_ureg3_pre : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_c1; - - /* 0x538 : awb2_sta_c2 */ - union { - struct { - uint32_t awb2_vreg4_pre : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t awb2_vreg5_pre : 8; /* [15: 8], r/w, 0x0 */ - uint32_t awb2_vreg6_pre : 8; /* [23:16], r/w, 0x0 */ - uint32_t awb2_vreg7_pre : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_c2; - - /* 0x53C : awb2_sta_c3 */ - union { - struct { - uint32_t awb2_vreg0_pre : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t awb2_vreg1_pre : 8; /* [15: 8], r/w, 0x0 */ - uint32_t awb2_vreg2_pre : 8; /* [23:16], r/w, 0x0 */ - uint32_t awb2_vreg3_pre : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_c3; - - /* 0x540 : awb2_sta_c4 */ - union { - struct { - uint32_t awb2_cth4_pre : 6; /* [ 5: 0], r/w, 0x10 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t awb2_cth5_pre : 6; /* [13: 8], r/w, 0x10 */ - uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ - uint32_t awb2_cth6_pre : 6; /* [21:16], r/w, 0x10 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t awb2_cth7_pre : 6; /* [29:24], r/w, 0x10 */ - uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_c4; - - /* 0x544 : awb2_sta_c5 */ - union { - struct { - uint32_t awb2_cth0_pre : 6; /* [ 5: 0], r/w, 0x10 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t awb2_cth1_pre : 6; /* [13: 8], r/w, 0x10 */ - uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ - uint32_t awb2_cth2_pre : 6; /* [21:16], r/w, 0x10 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t awb2_cth3_pre : 6; /* [29:24], r/w, 0x10 */ - uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_c5; - - /* 0x548 : awb2_sta_c6 */ - union { - struct { - uint32_t awb2_cslope4_pre : 8; /* [ 7: 0], r/w, 0x40 */ - uint32_t awb2_cslope5_pre : 8; /* [15: 8], r/w, 0x40 */ - uint32_t awb2_cslope6_pre : 8; /* [23:16], r/w, 0x40 */ - uint32_t awb2_cslope7_pre : 8; /* [31:24], r/w, 0x40 */ - } BF; - uint32_t WORD; - } awb2_sta_c6; - - /* 0x54C : awb2_sta_c7 */ - union { - struct { - uint32_t awb2_cslope0_pre : 8; /* [ 7: 0], r/w, 0x40 */ - uint32_t awb2_cslope1_pre : 8; /* [15: 8], r/w, 0x40 */ - uint32_t awb2_cslope2_pre : 8; /* [23:16], r/w, 0x40 */ - uint32_t awb2_cslope3_pre : 8; /* [31:24], r/w, 0x40 */ - } BF; - uint32_t WORD; - } awb2_sta_c7; - - /* 0x550 : awb2_sta_r0 */ - union { - struct { - uint32_t awb2_g_avg0_r : 12; /* [11: 0], r, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t awb2_r_avg0_r : 12; /* [27:16], r, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_r0; - - /* 0x554 : awb2_sta_r1 */ - union { - struct { - uint32_t awb2_white_ratio0_r : 15; /* [14: 0], r, 0x0 */ - uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */ - uint32_t awb2_b_avg0_r : 12; /* [27:16], r, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_r1; - - /* 0x558 : awb2_sta_r2 */ - union { - struct { - uint32_t awb2_g_avg1_r : 12; /* [11: 0], r, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t awb2_r_avg1_r : 12; /* [27:16], r, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_r2; - - /* 0x55C : awb2_sta_r3 */ - union { - struct { - uint32_t awb2_white_ratio1_r : 15; /* [14: 0], r, 0x0 */ - uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */ - uint32_t awb2_b_avg1_r : 12; /* [27:16], r, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_r3; - - /* 0x560 : awb2_sta_r4 */ - union { - struct { - uint32_t awb2_whiter_sumh0_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_r4; - - /* 0x564 : awb2_sta_r5 */ - union { - struct { - uint32_t awb2_whiter_suml1_r : 9; /* [ 8: 0], r, 0x0 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t awb2_whiter_suml0_r : 9; /* [24:16], r, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_r5; - - /* 0x568 : awb2_sta_r6 */ - union { - struct { - uint32_t awb2_whiter_sumh1_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_r6; - - /* 0x56C : awb2_sta_r7 */ - union { - struct { - uint32_t awb2_whiteg_sumh0_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_r7; - - /* 0x570 : awb2_sta_r8 */ - union { - struct { - uint32_t awb2_whiteg_suml1_r : 9; /* [ 8: 0], r, 0x0 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t awb2_whiteg_suml0_r : 9; /* [24:16], r, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_r8; - - /* 0x574 : awb2_sta_r9 */ - union { - struct { - uint32_t awb2_whiteg_sumh1_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_r9; - - /* 0x578 : awb2_sta_ra */ - union { - struct { - uint32_t awb2_whiteb_sumh0_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_ra; - - /* 0x57C : awb2_sta_rb */ - union { - struct { - uint32_t awb2_whiteb_suml1_r : 9; /* [ 8: 0], r, 0x0 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t awb2_whiteb_suml0_r : 9; /* [24:16], r, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_rb; - - /* 0x580 : awb2_sta_rc */ - union { - struct { - uint32_t awb2_whiteb_sumh1_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_rc; - - /* 0x584 : awb2_sta_int */ - union { - struct { - uint32_t awb2_gain_en_pre : 1; /* [ 0], r/w, 0x0 */ - uint32_t awb2_stat_en_pre : 1; /* [ 1], r/w, 0x0 */ - uint32_t awb2_buf_idx_r : 1; /* [ 2], r, 0x0 */ - uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */ - uint32_t awb2_w_cnt_r : 5; /* [12: 8], r, 0x0 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_int; -}; - -typedef volatile struct dsp2_middle3_reg dsp2_middle3_reg_t; - -#endif /* __DSP2_MIDDLE3_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_middle4_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_middle4_reg.h deleted file mode 100644 index 21a7c189b8..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_middle4_reg.h +++ /dev/null @@ -1,167 +0,0 @@ -/** - ****************************************************************************** - * @file dsp2_middle4_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __DSP2_MIDDLE4_REG_H__ -#define __DSP2_MIDDLE4_REG_H__ - -#include "bl808.h" - -/* 0x600 : bnr_config_0 */ -#define DSP2_MIDDLE4_BNR_CONFIG_0_OFFSET (0x600) -#define DSP2_MIDDLE4_BNR_WEIGHT_PRE DSP2_MIDDLE4_BNR_WEIGHT_PRE -#define DSP2_MIDDLE4_BNR_WEIGHT_PRE_POS (0U) -#define DSP2_MIDDLE4_BNR_WEIGHT_PRE_LEN (7U) -#define DSP2_MIDDLE4_BNR_WEIGHT_PRE_MSK (((1U << DSP2_MIDDLE4_BNR_WEIGHT_PRE_LEN) - 1) << DSP2_MIDDLE4_BNR_WEIGHT_PRE_POS) -#define DSP2_MIDDLE4_BNR_WEIGHT_PRE_UMSK (~(((1U << DSP2_MIDDLE4_BNR_WEIGHT_PRE_LEN) - 1) << DSP2_MIDDLE4_BNR_WEIGHT_PRE_POS)) -#define DSP2_MIDDLE4_BNR_EN_PRE DSP2_MIDDLE4_BNR_EN_PRE -#define DSP2_MIDDLE4_BNR_EN_PRE_POS (7U) -#define DSP2_MIDDLE4_BNR_EN_PRE_LEN (1U) -#define DSP2_MIDDLE4_BNR_EN_PRE_MSK (((1U << DSP2_MIDDLE4_BNR_EN_PRE_LEN) - 1) << DSP2_MIDDLE4_BNR_EN_PRE_POS) -#define DSP2_MIDDLE4_BNR_EN_PRE_UMSK (~(((1U << DSP2_MIDDLE4_BNR_EN_PRE_LEN) - 1) << DSP2_MIDDLE4_BNR_EN_PRE_POS)) -#define DSP2_MIDDLE4_LPF_WEIGHT_PRE DSP2_MIDDLE4_LPF_WEIGHT_PRE -#define DSP2_MIDDLE4_LPF_WEIGHT_PRE_POS (8U) -#define DSP2_MIDDLE4_LPF_WEIGHT_PRE_LEN (5U) -#define DSP2_MIDDLE4_LPF_WEIGHT_PRE_MSK (((1U << DSP2_MIDDLE4_LPF_WEIGHT_PRE_LEN) - 1) << DSP2_MIDDLE4_LPF_WEIGHT_PRE_POS) -#define DSP2_MIDDLE4_LPF_WEIGHT_PRE_UMSK (~(((1U << DSP2_MIDDLE4_LPF_WEIGHT_PRE_LEN) - 1) << DSP2_MIDDLE4_LPF_WEIGHT_PRE_POS)) -#define DSP2_MIDDLE4_TH_BASE_B_PRE DSP2_MIDDLE4_TH_BASE_B_PRE -#define DSP2_MIDDLE4_TH_BASE_B_PRE_POS (16U) -#define DSP2_MIDDLE4_TH_BASE_B_PRE_LEN (10U) -#define DSP2_MIDDLE4_TH_BASE_B_PRE_MSK (((1U << DSP2_MIDDLE4_TH_BASE_B_PRE_LEN) - 1) << DSP2_MIDDLE4_TH_BASE_B_PRE_POS) -#define DSP2_MIDDLE4_TH_BASE_B_PRE_UMSK (~(((1U << DSP2_MIDDLE4_TH_BASE_B_PRE_LEN) - 1) << DSP2_MIDDLE4_TH_BASE_B_PRE_POS)) - -/* 0x604 : bnr_config_1 */ -#define DSP2_MIDDLE4_BNR_CONFIG_1_OFFSET (0x604) -#define DSP2_MIDDLE4_TH_BASE_R_PRE DSP2_MIDDLE4_TH_BASE_R_PRE -#define DSP2_MIDDLE4_TH_BASE_R_PRE_POS (0U) -#define DSP2_MIDDLE4_TH_BASE_R_PRE_LEN (10U) -#define DSP2_MIDDLE4_TH_BASE_R_PRE_MSK (((1U << DSP2_MIDDLE4_TH_BASE_R_PRE_LEN) - 1) << DSP2_MIDDLE4_TH_BASE_R_PRE_POS) -#define DSP2_MIDDLE4_TH_BASE_R_PRE_UMSK (~(((1U << DSP2_MIDDLE4_TH_BASE_R_PRE_LEN) - 1) << DSP2_MIDDLE4_TH_BASE_R_PRE_POS)) -#define DSP2_MIDDLE4_TH_BASE_G_PRE DSP2_MIDDLE4_TH_BASE_G_PRE -#define DSP2_MIDDLE4_TH_BASE_G_PRE_POS (16U) -#define DSP2_MIDDLE4_TH_BASE_G_PRE_LEN (10U) -#define DSP2_MIDDLE4_TH_BASE_G_PRE_MSK (((1U << DSP2_MIDDLE4_TH_BASE_G_PRE_LEN) - 1) << DSP2_MIDDLE4_TH_BASE_G_PRE_POS) -#define DSP2_MIDDLE4_TH_BASE_G_PRE_UMSK (~(((1U << DSP2_MIDDLE4_TH_BASE_G_PRE_LEN) - 1) << DSP2_MIDDLE4_TH_BASE_G_PRE_POS)) - -/* 0x608 : bnr_config_2 */ -#define DSP2_MIDDLE4_BNR_CONFIG_2_OFFSET (0x608) -#define DSP2_MIDDLE4_TH_SLOPE_R_PRE DSP2_MIDDLE4_TH_SLOPE_R_PRE -#define DSP2_MIDDLE4_TH_SLOPE_R_PRE_POS (0U) -#define DSP2_MIDDLE4_TH_SLOPE_R_PRE_LEN (8U) -#define DSP2_MIDDLE4_TH_SLOPE_R_PRE_MSK (((1U << DSP2_MIDDLE4_TH_SLOPE_R_PRE_LEN) - 1) << DSP2_MIDDLE4_TH_SLOPE_R_PRE_POS) -#define DSP2_MIDDLE4_TH_SLOPE_R_PRE_UMSK (~(((1U << DSP2_MIDDLE4_TH_SLOPE_R_PRE_LEN) - 1) << DSP2_MIDDLE4_TH_SLOPE_R_PRE_POS)) -#define DSP2_MIDDLE4_TH_SLOPE_G_PRE DSP2_MIDDLE4_TH_SLOPE_G_PRE -#define DSP2_MIDDLE4_TH_SLOPE_G_PRE_POS (8U) -#define DSP2_MIDDLE4_TH_SLOPE_G_PRE_LEN (8U) -#define DSP2_MIDDLE4_TH_SLOPE_G_PRE_MSK (((1U << DSP2_MIDDLE4_TH_SLOPE_G_PRE_LEN) - 1) << DSP2_MIDDLE4_TH_SLOPE_G_PRE_POS) -#define DSP2_MIDDLE4_TH_SLOPE_G_PRE_UMSK (~(((1U << DSP2_MIDDLE4_TH_SLOPE_G_PRE_LEN) - 1) << DSP2_MIDDLE4_TH_SLOPE_G_PRE_POS)) -#define DSP2_MIDDLE4_TH_SLOPE_B_PRE DSP2_MIDDLE4_TH_SLOPE_B_PRE -#define DSP2_MIDDLE4_TH_SLOPE_B_PRE_POS (16U) -#define DSP2_MIDDLE4_TH_SLOPE_B_PRE_LEN (8U) -#define DSP2_MIDDLE4_TH_SLOPE_B_PRE_MSK (((1U << DSP2_MIDDLE4_TH_SLOPE_B_PRE_LEN) - 1) << DSP2_MIDDLE4_TH_SLOPE_B_PRE_POS) -#define DSP2_MIDDLE4_TH_SLOPE_B_PRE_UMSK (~(((1U << DSP2_MIDDLE4_TH_SLOPE_B_PRE_LEN) - 1) << DSP2_MIDDLE4_TH_SLOPE_B_PRE_POS)) -#define DSP2_MIDDLE4_SLOPE_GAIN_PRE DSP2_MIDDLE4_SLOPE_GAIN_PRE -#define DSP2_MIDDLE4_SLOPE_GAIN_PRE_POS (24U) -#define DSP2_MIDDLE4_SLOPE_GAIN_PRE_LEN (6U) -#define DSP2_MIDDLE4_SLOPE_GAIN_PRE_MSK (((1U << DSP2_MIDDLE4_SLOPE_GAIN_PRE_LEN) - 1) << DSP2_MIDDLE4_SLOPE_GAIN_PRE_POS) -#define DSP2_MIDDLE4_SLOPE_GAIN_PRE_UMSK (~(((1U << DSP2_MIDDLE4_SLOPE_GAIN_PRE_LEN) - 1) << DSP2_MIDDLE4_SLOPE_GAIN_PRE_POS)) - -/* 0x60C : bnr_config_3 */ -#define DSP2_MIDDLE4_BNR_CONFIG_3_OFFSET (0x60C) -#define DSP2_MIDDLE4_FB_LEVEL_PRE DSP2_MIDDLE4_FB_LEVEL_PRE -#define DSP2_MIDDLE4_FB_LEVEL_PRE_POS (0U) -#define DSP2_MIDDLE4_FB_LEVEL_PRE_LEN (3U) -#define DSP2_MIDDLE4_FB_LEVEL_PRE_MSK (((1U << DSP2_MIDDLE4_FB_LEVEL_PRE_LEN) - 1) << DSP2_MIDDLE4_FB_LEVEL_PRE_POS) -#define DSP2_MIDDLE4_FB_LEVEL_PRE_UMSK (~(((1U << DSP2_MIDDLE4_FB_LEVEL_PRE_LEN) - 1) << DSP2_MIDDLE4_FB_LEVEL_PRE_POS)) -#define DSP2_MIDDLE4_FB_LPF_WEIGHT_PRE DSP2_MIDDLE4_FB_LPF_WEIGHT_PRE -#define DSP2_MIDDLE4_FB_LPF_WEIGHT_PRE_POS (8U) -#define DSP2_MIDDLE4_FB_LPF_WEIGHT_PRE_LEN (5U) -#define DSP2_MIDDLE4_FB_LPF_WEIGHT_PRE_MSK (((1U << DSP2_MIDDLE4_FB_LPF_WEIGHT_PRE_LEN) - 1) << DSP2_MIDDLE4_FB_LPF_WEIGHT_PRE_POS) -#define DSP2_MIDDLE4_FB_LPF_WEIGHT_PRE_UMSK (~(((1U << DSP2_MIDDLE4_FB_LPF_WEIGHT_PRE_LEN) - 1) << DSP2_MIDDLE4_FB_LPF_WEIGHT_PRE_POS)) - -struct dsp2_middle4_reg { - /* 0x0 reserved */ - uint8_t RESERVED0x0[1536]; - - /* 0x600 : bnr_config_0 */ - union { - struct { - uint32_t bnr_weight_pre : 7; /* [ 6: 0], r/w, 0x0 */ - uint32_t bnr_en_pre : 1; /* [ 7], r/w, 0x0 */ - uint32_t lpf_weight_pre : 5; /* [12: 8], r/w, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t th_base_b_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } bnr_config_0; - - /* 0x604 : bnr_config_1 */ - union { - struct { - uint32_t th_base_r_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t th_base_g_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } bnr_config_1; - - /* 0x608 : bnr_config_2 */ - union { - struct { - uint32_t th_slope_r_pre : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t th_slope_g_pre : 8; /* [15: 8], r/w, 0x0 */ - uint32_t th_slope_b_pre : 8; /* [23:16], r/w, 0x0 */ - uint32_t slope_gain_pre : 6; /* [29:24], r/w, 0x0 */ - uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } bnr_config_2; - - /* 0x60C : bnr_config_3 */ - union { - struct { - uint32_t fb_level_pre : 3; /* [ 2: 0], r/w, 0x0 */ - uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */ - uint32_t fb_lpf_weight_pre : 5; /* [12: 8], r/w, 0x0 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } bnr_config_3; -}; - -typedef volatile struct dsp2_middle4_reg dsp2_middle4_reg_t; - -#endif /* __DSP2_MIDDLE4_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_middle5_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_middle5_reg.h deleted file mode 100644 index df2fc9add1..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_middle5_reg.h +++ /dev/null @@ -1,2589 +0,0 @@ -/** - ****************************************************************************** - * @file dsp2_middle5_reg.h - * @version V1.2 - * @date 2021-07-15 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __DSP2_MIDDLE5_REG_H__ -#define __DSP2_MIDDLE5_REG_H__ - -#include "bl808.h" - -/* 0x000 : awb3_config_0 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_0_OFFSET (0x000) -#define DSP2_MIDDLE5_AWB3_STAT_X_MAX_PRE DSP2_MIDDLE5_AWB3_STAT_X_MAX_PRE -#define DSP2_MIDDLE5_AWB3_STAT_X_MAX_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_STAT_X_MAX_PRE_LEN (11U) -#define DSP2_MIDDLE5_AWB3_STAT_X_MAX_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_STAT_X_MAX_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_STAT_X_MAX_PRE_POS) -#define DSP2_MIDDLE5_AWB3_STAT_X_MAX_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_STAT_X_MAX_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_STAT_X_MAX_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_STAT_X_MIN_PRE DSP2_MIDDLE5_AWB3_STAT_X_MIN_PRE -#define DSP2_MIDDLE5_AWB3_STAT_X_MIN_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_STAT_X_MIN_PRE_LEN (11U) -#define DSP2_MIDDLE5_AWB3_STAT_X_MIN_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_STAT_X_MIN_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_STAT_X_MIN_PRE_POS) -#define DSP2_MIDDLE5_AWB3_STAT_X_MIN_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_STAT_X_MIN_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_STAT_X_MIN_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_STAT_EN_PRE DSP2_MIDDLE5_AWB3_STAT_EN_PRE -#define DSP2_MIDDLE5_AWB3_STAT_EN_PRE_POS (31U) -#define DSP2_MIDDLE5_AWB3_STAT_EN_PRE_LEN (1U) -#define DSP2_MIDDLE5_AWB3_STAT_EN_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_STAT_EN_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_STAT_EN_PRE_POS) -#define DSP2_MIDDLE5_AWB3_STAT_EN_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_STAT_EN_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_STAT_EN_PRE_POS)) - -/* 0x004 : awb3_config_1 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_1_OFFSET (0x004) -#define DSP2_MIDDLE5_AWB3_STAT_Y_MAX_PRE DSP2_MIDDLE5_AWB3_STAT_Y_MAX_PRE -#define DSP2_MIDDLE5_AWB3_STAT_Y_MAX_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_STAT_Y_MAX_PRE_LEN (11U) -#define DSP2_MIDDLE5_AWB3_STAT_Y_MAX_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_STAT_Y_MAX_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_STAT_Y_MAX_PRE_POS) -#define DSP2_MIDDLE5_AWB3_STAT_Y_MAX_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_STAT_Y_MAX_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_STAT_Y_MAX_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_STAT_Y_MIN_PRE DSP2_MIDDLE5_AWB3_STAT_Y_MIN_PRE -#define DSP2_MIDDLE5_AWB3_STAT_Y_MIN_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_STAT_Y_MIN_PRE_LEN (11U) -#define DSP2_MIDDLE5_AWB3_STAT_Y_MIN_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_STAT_Y_MIN_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_STAT_Y_MIN_PRE_POS) -#define DSP2_MIDDLE5_AWB3_STAT_Y_MIN_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_STAT_Y_MIN_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_STAT_Y_MIN_PRE_POS)) - -/* 0x008 : awb3_config_2 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_2_OFFSET (0x008) -#define DSP2_MIDDLE5_AWB3_B_RATIO_OFST_PRE DSP2_MIDDLE5_AWB3_B_RATIO_OFST_PRE -#define DSP2_MIDDLE5_AWB3_B_RATIO_OFST_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_OFST_PRE_LEN (12U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_OFST_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_B_RATIO_OFST_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_OFST_PRE_POS) -#define DSP2_MIDDLE5_AWB3_B_RATIO_OFST_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_B_RATIO_OFST_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_OFST_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_R_RATIO_OFST_PRE DSP2_MIDDLE5_AWB3_R_RATIO_OFST_PRE -#define DSP2_MIDDLE5_AWB3_R_RATIO_OFST_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_OFST_PRE_LEN (12U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_OFST_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_R_RATIO_OFST_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_OFST_PRE_POS) -#define DSP2_MIDDLE5_AWB3_R_RATIO_OFST_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_R_RATIO_OFST_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_OFST_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_G_DIVISOR_PRE DSP2_MIDDLE5_AWB3_G_DIVISOR_PRE -#define DSP2_MIDDLE5_AWB3_G_DIVISOR_PRE_POS (31U) -#define DSP2_MIDDLE5_AWB3_G_DIVISOR_PRE_LEN (1U) -#define DSP2_MIDDLE5_AWB3_G_DIVISOR_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_G_DIVISOR_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_G_DIVISOR_PRE_POS) -#define DSP2_MIDDLE5_AWB3_G_DIVISOR_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_G_DIVISOR_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_G_DIVISOR_PRE_POS)) - -/* 0x00C : awb3_config_3 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_3_OFFSET (0x00C) -#define DSP2_MIDDLE5_AWB3_B_RATIO_MULT_PRE DSP2_MIDDLE5_AWB3_B_RATIO_MULT_PRE -#define DSP2_MIDDLE5_AWB3_B_RATIO_MULT_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_MULT_PRE_LEN (12U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_MULT_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_B_RATIO_MULT_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_MULT_PRE_POS) -#define DSP2_MIDDLE5_AWB3_B_RATIO_MULT_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_B_RATIO_MULT_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_MULT_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_R_RATIO_MULT_PRE DSP2_MIDDLE5_AWB3_R_RATIO_MULT_PRE -#define DSP2_MIDDLE5_AWB3_R_RATIO_MULT_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_MULT_PRE_LEN (12U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_MULT_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_R_RATIO_MULT_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_MULT_PRE_POS) -#define DSP2_MIDDLE5_AWB3_R_RATIO_MULT_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_R_RATIO_MULT_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_MULT_PRE_POS)) - -/* 0x010 : awb3_config_4 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_4_OFFSET (0x010) -#define DSP2_MIDDLE5_AWB3_RATIO_SUM_MAX_PRE DSP2_MIDDLE5_AWB3_RATIO_SUM_MAX_PRE -#define DSP2_MIDDLE5_AWB3_RATIO_SUM_MAX_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_RATIO_SUM_MAX_PRE_LEN (9U) -#define DSP2_MIDDLE5_AWB3_RATIO_SUM_MAX_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_RATIO_SUM_MAX_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_RATIO_SUM_MAX_PRE_POS) -#define DSP2_MIDDLE5_AWB3_RATIO_SUM_MAX_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_RATIO_SUM_MAX_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_RATIO_SUM_MAX_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_RATIO_SUM_MIN_PRE DSP2_MIDDLE5_AWB3_RATIO_SUM_MIN_PRE -#define DSP2_MIDDLE5_AWB3_RATIO_SUM_MIN_PRE_POS (9U) -#define DSP2_MIDDLE5_AWB3_RATIO_SUM_MIN_PRE_LEN (9U) -#define DSP2_MIDDLE5_AWB3_RATIO_SUM_MIN_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_RATIO_SUM_MIN_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_RATIO_SUM_MIN_PRE_POS) -#define DSP2_MIDDLE5_AWB3_RATIO_SUM_MIN_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_RATIO_SUM_MIN_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_RATIO_SUM_MIN_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_GAIN_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_GAIN_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_GAIN_PRE_POS (18U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_GAIN_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_GAIN_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_GAIN_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_GAIN_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_GAIN_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_GAIN_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_GAIN_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_EN_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_EN_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_EN_PRE_POS (26U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_EN_PRE_LEN (1U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_EN_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_EN_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_EN_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_EN_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_EN_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_EN_PRE_POS)) - -/* 0x014 : awb3_config_5 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_5_OFFSET (0x014) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_00_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_00_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_00_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_00_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_00_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_00_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_00_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_00_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_00_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_00_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_01_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_01_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_01_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_01_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_01_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_01_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_01_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_01_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_01_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_01_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_02_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_02_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_02_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_02_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_02_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_02_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_02_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_02_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_02_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_02_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_03_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_03_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_03_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_03_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_03_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_03_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_03_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_03_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_03_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_03_PRE_POS)) - -/* 0x018 : awb3_config_6 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_6_OFFSET (0x018) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_04_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_04_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_04_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_04_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_04_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_04_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_04_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_04_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_04_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_04_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_05_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_05_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_05_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_05_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_05_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_05_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_05_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_05_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_05_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_05_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_06_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_06_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_06_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_06_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_06_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_06_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_06_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_06_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_06_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_06_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_07_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_07_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_07_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_07_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_07_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_07_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_07_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_07_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_07_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_07_PRE_POS)) - -/* 0x01C : awb3_config_7 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_7_OFFSET (0x01C) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_08_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_08_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_08_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_08_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_08_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_08_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_08_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_08_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_08_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_08_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_10_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_10_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_10_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_10_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_10_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_10_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_10_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_10_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_10_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_10_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_11_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_11_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_11_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_11_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_11_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_11_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_11_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_11_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_11_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_11_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_12_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_12_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_12_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_12_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_12_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_12_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_12_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_12_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_12_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_12_PRE_POS)) - -/* 0x020 : awb3_config_8 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_8_OFFSET (0x020) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_13_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_13_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_13_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_13_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_13_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_13_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_13_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_13_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_13_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_13_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_14_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_14_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_14_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_14_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_14_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_14_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_14_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_14_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_14_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_14_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_15_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_15_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_15_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_15_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_15_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_15_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_15_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_15_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_15_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_15_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_16_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_16_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_16_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_16_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_16_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_16_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_16_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_16_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_16_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_16_PRE_POS)) - -/* 0x024 : awb3_config_9 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_9_OFFSET (0x024) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_17_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_17_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_17_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_17_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_17_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_17_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_17_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_17_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_17_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_17_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_18_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_18_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_18_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_18_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_18_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_18_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_18_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_18_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_18_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_18_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_20_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_20_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_20_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_20_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_20_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_20_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_20_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_20_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_20_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_20_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_21_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_21_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_21_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_21_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_21_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_21_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_21_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_21_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_21_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_21_PRE_POS)) - -/* 0x028 : awb3_config_10 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_10_OFFSET (0x028) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_22_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_22_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_22_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_22_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_22_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_22_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_22_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_22_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_22_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_22_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_23_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_23_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_23_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_23_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_23_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_23_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_23_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_23_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_23_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_23_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_24_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_24_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_24_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_24_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_24_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_24_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_24_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_24_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_24_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_24_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_25_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_25_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_25_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_25_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_25_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_25_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_25_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_25_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_25_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_25_PRE_POS)) - -/* 0x02C : awb3_config_11 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_11_OFFSET (0x02C) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_26_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_26_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_26_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_26_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_26_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_26_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_26_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_26_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_26_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_26_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_27_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_27_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_27_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_27_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_27_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_27_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_27_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_27_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_27_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_27_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_28_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_28_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_28_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_28_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_28_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_28_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_28_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_28_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_28_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_28_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_30_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_30_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_30_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_30_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_30_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_30_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_30_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_30_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_30_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_30_PRE_POS)) - -/* 0x030 : awb3_config_12 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_12_OFFSET (0x030) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_31_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_31_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_31_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_31_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_31_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_31_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_31_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_31_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_31_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_31_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_32_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_32_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_32_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_32_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_32_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_32_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_32_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_32_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_32_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_32_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_33_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_33_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_33_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_33_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_33_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_33_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_33_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_33_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_33_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_33_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_34_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_34_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_34_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_34_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_34_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_34_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_34_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_34_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_34_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_34_PRE_POS)) - -/* 0x034 : awb3_config_13 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_13_OFFSET (0x034) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_35_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_35_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_35_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_35_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_35_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_35_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_35_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_35_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_35_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_35_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_36_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_36_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_36_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_36_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_36_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_36_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_36_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_36_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_36_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_36_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_37_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_37_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_37_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_37_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_37_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_37_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_37_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_37_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_37_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_37_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_38_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_38_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_38_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_38_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_38_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_38_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_38_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_38_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_38_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_38_PRE_POS)) - -/* 0x038 : awb3_config_14 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_14_OFFSET (0x038) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_40_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_40_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_40_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_40_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_40_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_40_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_40_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_40_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_40_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_40_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_41_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_41_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_41_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_41_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_41_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_41_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_41_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_41_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_41_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_41_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_42_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_42_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_42_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_42_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_42_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_42_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_42_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_42_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_42_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_42_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_43_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_43_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_43_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_43_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_43_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_43_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_43_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_43_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_43_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_43_PRE_POS)) - -/* 0x03C : awb3_config_15 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_15_OFFSET (0x03C) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_44_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_44_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_44_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_44_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_44_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_44_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_44_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_44_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_44_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_44_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_45_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_45_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_45_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_45_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_45_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_45_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_45_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_45_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_45_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_45_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_46_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_46_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_46_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_46_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_46_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_46_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_46_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_46_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_46_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_46_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_47_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_47_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_47_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_47_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_47_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_47_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_47_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_47_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_47_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_47_PRE_POS)) - -/* 0x040 : awb3_config_16 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_16_OFFSET (0x040) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_48_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_48_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_48_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_48_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_48_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_48_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_48_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_48_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_48_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_48_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_50_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_50_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_50_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_50_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_50_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_50_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_50_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_50_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_50_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_50_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_51_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_51_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_51_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_51_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_51_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_51_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_51_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_51_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_51_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_51_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_52_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_52_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_52_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_52_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_52_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_52_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_52_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_52_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_52_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_52_PRE_POS)) - -/* 0x044 : awb3_config_17 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_17_OFFSET (0x044) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_53_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_53_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_53_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_53_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_53_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_53_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_53_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_53_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_53_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_53_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_54_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_54_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_54_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_54_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_54_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_54_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_54_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_54_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_54_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_54_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_55_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_55_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_55_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_55_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_55_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_55_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_55_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_55_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_55_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_55_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_56_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_56_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_56_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_56_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_56_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_56_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_56_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_56_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_56_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_56_PRE_POS)) - -/* 0x048 : awb3_config_18 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_18_OFFSET (0x048) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_57_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_57_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_57_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_57_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_57_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_57_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_57_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_57_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_57_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_57_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_58_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_58_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_58_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_58_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_58_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_58_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_58_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_58_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_58_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_58_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_60_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_60_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_60_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_60_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_60_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_60_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_60_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_60_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_60_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_60_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_61_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_61_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_61_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_61_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_61_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_61_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_61_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_61_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_61_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_61_PRE_POS)) - -/* 0x04C : awb3_config_19 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_19_OFFSET (0x04C) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_62_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_62_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_62_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_62_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_62_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_62_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_62_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_62_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_62_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_62_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_63_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_63_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_63_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_63_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_63_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_63_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_63_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_63_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_63_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_63_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_64_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_64_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_64_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_64_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_64_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_64_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_64_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_64_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_64_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_64_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_65_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_65_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_65_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_65_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_65_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_65_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_65_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_65_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_65_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_65_PRE_POS)) - -/* 0x050 : awb3_config_20 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_20_OFFSET (0x050) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_66_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_66_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_66_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_66_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_66_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_66_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_66_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_66_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_66_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_66_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_67_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_67_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_67_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_67_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_67_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_67_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_67_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_67_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_67_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_67_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_68_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_68_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_68_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_68_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_68_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_68_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_68_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_68_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_68_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_68_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_70_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_70_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_70_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_70_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_70_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_70_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_70_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_70_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_70_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_70_PRE_POS)) - -/* 0x054 : awb3_config_21 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_21_OFFSET (0x054) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_71_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_71_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_71_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_71_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_71_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_71_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_71_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_71_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_71_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_71_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_72_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_72_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_72_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_72_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_72_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_72_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_72_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_72_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_72_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_72_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_73_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_73_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_73_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_73_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_73_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_73_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_73_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_73_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_73_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_73_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_74_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_74_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_74_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_74_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_74_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_74_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_74_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_74_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_74_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_74_PRE_POS)) - -/* 0x058 : awb3_config_22 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_22_OFFSET (0x058) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_75_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_75_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_75_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_75_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_75_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_75_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_75_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_75_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_75_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_75_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_76_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_76_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_76_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_76_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_76_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_76_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_76_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_76_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_76_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_76_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_77_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_77_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_77_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_77_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_77_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_77_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_77_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_77_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_77_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_77_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_78_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_78_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_78_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_78_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_78_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_78_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_78_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_78_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_78_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_78_PRE_POS)) - -/* 0x05C : awb3_config_23 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_23_OFFSET (0x05C) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_80_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_80_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_80_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_80_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_80_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_80_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_80_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_80_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_80_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_80_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_81_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_81_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_81_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_81_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_81_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_81_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_81_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_81_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_81_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_81_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_82_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_82_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_82_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_82_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_82_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_82_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_82_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_82_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_82_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_82_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_83_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_83_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_83_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_83_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_83_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_83_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_83_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_83_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_83_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_83_PRE_POS)) - -/* 0x060 : awb3_config_24 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_24_OFFSET (0x060) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_84_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_84_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_84_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_84_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_84_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_84_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_84_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_84_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_84_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_84_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_85_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_85_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_85_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_85_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_85_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_85_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_85_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_85_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_85_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_85_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_86_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_86_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_86_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_86_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_86_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_86_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_86_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_86_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_86_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_86_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_87_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_87_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_87_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_87_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_87_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_87_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_87_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_87_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_87_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_87_PRE_POS)) - -/* 0x064 : awb3_config_25 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_25_OFFSET (0x064) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_88_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_88_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_88_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_88_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_88_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_88_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_88_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_88_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_88_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_88_PRE_POS)) - -/* 0x068 : awb3_config_26 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_26_OFFSET (0x068) -#define DSP2_MIDDLE5_AWB3_Y_R_COEFF_PRE DSP2_MIDDLE5_AWB3_Y_R_COEFF_PRE -#define DSP2_MIDDLE5_AWB3_Y_R_COEFF_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_Y_R_COEFF_PRE_LEN (12U) -#define DSP2_MIDDLE5_AWB3_Y_R_COEFF_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_Y_R_COEFF_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_Y_R_COEFF_PRE_POS) -#define DSP2_MIDDLE5_AWB3_Y_R_COEFF_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_Y_R_COEFF_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_Y_R_COEFF_PRE_POS)) - -/* 0x06C : awb3_config_27 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_27_OFFSET (0x06C) -#define DSP2_MIDDLE5_AWB3_Y_G_COEFF_PRE DSP2_MIDDLE5_AWB3_Y_G_COEFF_PRE -#define DSP2_MIDDLE5_AWB3_Y_G_COEFF_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_Y_G_COEFF_PRE_LEN (12U) -#define DSP2_MIDDLE5_AWB3_Y_G_COEFF_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_Y_G_COEFF_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_Y_G_COEFF_PRE_POS) -#define DSP2_MIDDLE5_AWB3_Y_G_COEFF_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_Y_G_COEFF_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_Y_G_COEFF_PRE_POS)) - -/* 0x070 : awb3_config_28 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_28_OFFSET (0x070) -#define DSP2_MIDDLE5_AWB3_Y_B_COEFF_PRE DSP2_MIDDLE5_AWB3_Y_B_COEFF_PRE -#define DSP2_MIDDLE5_AWB3_Y_B_COEFF_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_Y_B_COEFF_PRE_LEN (12U) -#define DSP2_MIDDLE5_AWB3_Y_B_COEFF_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_Y_B_COEFF_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_Y_B_COEFF_PRE_POS) -#define DSP2_MIDDLE5_AWB3_Y_B_COEFF_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_Y_B_COEFF_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_Y_B_COEFF_PRE_POS)) - -/* 0x074 : awb3_config_29 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_29_OFFSET (0x074) -#define DSP2_MIDDLE5_AWB3_WT_Y_GAIN_PRE DSP2_MIDDLE5_AWB3_WT_Y_GAIN_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_GAIN_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_Y_GAIN_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_GAIN_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_GAIN_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_GAIN_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_GAIN_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_GAIN_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_GAIN_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_EN_PRE DSP2_MIDDLE5_AWB3_WT_Y_EN_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_EN_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_EN_PRE_LEN (1U) -#define DSP2_MIDDLE5_AWB3_WT_Y_EN_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_EN_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_EN_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_EN_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_EN_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_EN_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_USE_G_PRE DSP2_MIDDLE5_AWB3_WT_Y_USE_G_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_USE_G_PRE_POS (12U) -#define DSP2_MIDDLE5_AWB3_WT_Y_USE_G_PRE_LEN (1U) -#define DSP2_MIDDLE5_AWB3_WT_Y_USE_G_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_USE_G_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_USE_G_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_USE_G_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_USE_G_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_USE_G_PRE_POS)) - -/* 0x078 : awb3_config_30 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_30_OFFSET (0x078) -#define DSP2_MIDDLE5_AWB3_WT_Y_00_PRE DSP2_MIDDLE5_AWB3_WT_Y_00_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_00_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_Y_00_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_00_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_00_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_00_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_00_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_00_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_00_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_01_PRE DSP2_MIDDLE5_AWB3_WT_Y_01_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_01_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_01_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_01_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_01_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_01_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_01_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_01_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_01_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_02_PRE DSP2_MIDDLE5_AWB3_WT_Y_02_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_02_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_Y_02_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_02_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_02_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_02_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_02_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_02_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_02_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_03_PRE DSP2_MIDDLE5_AWB3_WT_Y_03_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_03_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_Y_03_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_03_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_03_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_03_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_03_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_03_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_03_PRE_POS)) - -/* 0x07C : awb3_config_31 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_31_OFFSET (0x07C) -#define DSP2_MIDDLE5_AWB3_WT_Y_04_PRE DSP2_MIDDLE5_AWB3_WT_Y_04_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_04_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_Y_04_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_04_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_04_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_04_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_04_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_04_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_04_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_05_PRE DSP2_MIDDLE5_AWB3_WT_Y_05_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_05_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_05_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_05_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_05_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_05_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_05_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_05_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_05_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_06_PRE DSP2_MIDDLE5_AWB3_WT_Y_06_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_06_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_Y_06_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_06_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_06_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_06_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_06_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_06_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_06_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_07_PRE DSP2_MIDDLE5_AWB3_WT_Y_07_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_07_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_Y_07_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_07_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_07_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_07_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_07_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_07_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_07_PRE_POS)) - -/* 0x080 : awb3_config_32 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_32_OFFSET (0x080) -#define DSP2_MIDDLE5_AWB3_WT_Y_08_PRE DSP2_MIDDLE5_AWB3_WT_Y_08_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_08_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_Y_08_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_08_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_08_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_08_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_08_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_08_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_08_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_10_PRE DSP2_MIDDLE5_AWB3_WT_Y_10_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_10_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_10_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_10_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_10_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_10_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_10_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_10_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_10_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_11_PRE DSP2_MIDDLE5_AWB3_WT_Y_11_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_11_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_Y_11_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_11_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_11_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_11_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_11_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_11_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_11_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_12_PRE DSP2_MIDDLE5_AWB3_WT_Y_12_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_12_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_Y_12_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_12_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_12_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_12_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_12_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_12_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_12_PRE_POS)) - -/* 0x084 : awb3_config_33 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_33_OFFSET (0x084) -#define DSP2_MIDDLE5_AWB3_WT_Y_13_PRE DSP2_MIDDLE5_AWB3_WT_Y_13_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_13_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_Y_13_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_13_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_13_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_13_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_13_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_13_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_13_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_14_PRE DSP2_MIDDLE5_AWB3_WT_Y_14_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_14_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_14_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_14_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_14_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_14_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_14_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_14_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_14_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_15_PRE DSP2_MIDDLE5_AWB3_WT_Y_15_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_15_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_Y_15_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_15_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_15_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_15_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_15_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_15_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_15_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_16_PRE DSP2_MIDDLE5_AWB3_WT_Y_16_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_16_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_Y_16_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_16_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_16_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_16_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_16_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_16_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_16_PRE_POS)) - -/* 0x088 : awb3_config_34 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_34_OFFSET (0x088) -#define DSP2_MIDDLE5_AWB3_WT_Y_17_PRE DSP2_MIDDLE5_AWB3_WT_Y_17_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_17_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_Y_17_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_17_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_17_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_17_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_17_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_17_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_17_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_18_PRE DSP2_MIDDLE5_AWB3_WT_Y_18_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_18_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_18_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_18_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_18_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_18_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_18_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_18_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_18_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_20_PRE DSP2_MIDDLE5_AWB3_WT_Y_20_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_20_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_Y_20_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_20_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_20_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_20_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_20_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_20_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_20_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_21_PRE DSP2_MIDDLE5_AWB3_WT_Y_21_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_21_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_Y_21_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_21_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_21_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_21_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_21_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_21_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_21_PRE_POS)) - -/* 0x08C : awb3_config_35 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_35_OFFSET (0x08C) -#define DSP2_MIDDLE5_AWB3_WT_Y_22_PRE DSP2_MIDDLE5_AWB3_WT_Y_22_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_22_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_Y_22_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_22_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_22_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_22_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_22_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_22_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_22_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_23_PRE DSP2_MIDDLE5_AWB3_WT_Y_23_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_23_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_23_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_23_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_23_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_23_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_23_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_23_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_23_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_24_PRE DSP2_MIDDLE5_AWB3_WT_Y_24_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_24_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_Y_24_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_24_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_24_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_24_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_24_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_24_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_24_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_25_PRE DSP2_MIDDLE5_AWB3_WT_Y_25_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_25_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_Y_25_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_25_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_25_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_25_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_25_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_25_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_25_PRE_POS)) - -/* 0x090 : awb3_config_36 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_36_OFFSET (0x090) -#define DSP2_MIDDLE5_AWB3_WT_Y_26_PRE DSP2_MIDDLE5_AWB3_WT_Y_26_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_26_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_Y_26_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_26_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_26_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_26_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_26_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_26_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_26_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_27_PRE DSP2_MIDDLE5_AWB3_WT_Y_27_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_27_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_27_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_27_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_27_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_27_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_27_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_27_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_27_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_28_PRE DSP2_MIDDLE5_AWB3_WT_Y_28_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_28_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_Y_28_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_28_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_28_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_28_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_28_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_28_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_28_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_30_PRE DSP2_MIDDLE5_AWB3_WT_Y_30_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_30_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_Y_30_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_30_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_30_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_30_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_30_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_30_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_30_PRE_POS)) - -/* 0x094 : awb3_config_37 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_37_OFFSET (0x094) -#define DSP2_MIDDLE5_AWB3_WT_Y_31_PRE DSP2_MIDDLE5_AWB3_WT_Y_31_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_31_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_Y_31_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_31_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_31_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_31_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_31_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_31_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_31_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_32_PRE DSP2_MIDDLE5_AWB3_WT_Y_32_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_32_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_32_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_32_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_32_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_32_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_32_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_32_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_32_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_33_PRE DSP2_MIDDLE5_AWB3_WT_Y_33_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_33_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_Y_33_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_33_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_33_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_33_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_33_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_33_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_33_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_34_PRE DSP2_MIDDLE5_AWB3_WT_Y_34_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_34_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_Y_34_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_34_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_34_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_34_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_34_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_34_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_34_PRE_POS)) - -/* 0x098 : awb3_config_38 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_38_OFFSET (0x098) -#define DSP2_MIDDLE5_AWB3_WT_Y_35_PRE DSP2_MIDDLE5_AWB3_WT_Y_35_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_35_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_Y_35_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_35_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_35_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_35_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_35_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_35_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_35_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_36_PRE DSP2_MIDDLE5_AWB3_WT_Y_36_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_36_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_36_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_36_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_36_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_36_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_36_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_36_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_36_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_37_PRE DSP2_MIDDLE5_AWB3_WT_Y_37_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_37_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_Y_37_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_37_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_37_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_37_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_37_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_37_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_37_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_38_PRE DSP2_MIDDLE5_AWB3_WT_Y_38_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_38_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_Y_38_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_38_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_38_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_38_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_38_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_38_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_38_PRE_POS)) - -/* 0x09C : awb3_config_39 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_39_OFFSET (0x09C) -#define DSP2_MIDDLE5_AWB3_WT_Y_40_PRE DSP2_MIDDLE5_AWB3_WT_Y_40_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_40_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_Y_40_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_40_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_40_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_40_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_40_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_40_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_40_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_41_PRE DSP2_MIDDLE5_AWB3_WT_Y_41_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_41_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_41_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_41_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_41_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_41_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_41_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_41_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_41_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_42_PRE DSP2_MIDDLE5_AWB3_WT_Y_42_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_42_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_Y_42_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_42_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_42_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_42_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_42_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_42_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_42_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_43_PRE DSP2_MIDDLE5_AWB3_WT_Y_43_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_43_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_Y_43_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_43_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_43_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_43_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_43_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_43_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_43_PRE_POS)) - -/* 0x0A0 : awb3_config_40 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_40_OFFSET (0x0A0) -#define DSP2_MIDDLE5_AWB3_WT_Y_44_PRE DSP2_MIDDLE5_AWB3_WT_Y_44_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_44_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_Y_44_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_44_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_44_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_44_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_44_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_44_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_44_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_45_PRE DSP2_MIDDLE5_AWB3_WT_Y_45_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_45_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_45_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_45_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_45_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_45_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_45_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_45_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_45_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_46_PRE DSP2_MIDDLE5_AWB3_WT_Y_46_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_46_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_Y_46_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_46_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_46_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_46_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_46_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_46_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_46_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_47_PRE DSP2_MIDDLE5_AWB3_WT_Y_47_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_47_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_Y_47_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_47_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_47_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_47_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_47_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_47_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_47_PRE_POS)) - -/* 0x0A4 : awb3_config_41 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_41_OFFSET (0x0A4) -#define DSP2_MIDDLE5_AWB3_WT_Y_48_PRE DSP2_MIDDLE5_AWB3_WT_Y_48_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_48_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_Y_48_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_48_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_48_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_48_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_48_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_48_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_48_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_50_PRE DSP2_MIDDLE5_AWB3_WT_Y_50_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_50_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_50_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_50_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_50_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_50_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_50_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_50_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_50_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_51_PRE DSP2_MIDDLE5_AWB3_WT_Y_51_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_51_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_Y_51_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_51_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_51_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_51_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_51_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_51_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_51_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_52_PRE DSP2_MIDDLE5_AWB3_WT_Y_52_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_52_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_Y_52_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_52_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_52_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_52_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_52_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_52_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_52_PRE_POS)) - -/* 0x0A8 : awb3_config_42 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_42_OFFSET (0x0A8) -#define DSP2_MIDDLE5_AWB3_WT_Y_53_PRE DSP2_MIDDLE5_AWB3_WT_Y_53_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_53_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_Y_53_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_53_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_53_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_53_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_53_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_53_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_53_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_54_PRE DSP2_MIDDLE5_AWB3_WT_Y_54_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_54_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_54_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_54_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_54_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_54_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_54_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_54_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_54_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_55_PRE DSP2_MIDDLE5_AWB3_WT_Y_55_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_55_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_Y_55_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_55_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_55_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_55_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_55_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_55_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_55_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_56_PRE DSP2_MIDDLE5_AWB3_WT_Y_56_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_56_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_Y_56_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_56_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_56_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_56_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_56_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_56_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_56_PRE_POS)) - -/* 0x0AC : awb3_config_43 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_43_OFFSET (0x0AC) -#define DSP2_MIDDLE5_AWB3_WT_Y_57_PRE DSP2_MIDDLE5_AWB3_WT_Y_57_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_57_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_Y_57_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_57_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_57_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_57_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_57_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_57_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_57_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_58_PRE DSP2_MIDDLE5_AWB3_WT_Y_58_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_58_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_58_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_58_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_58_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_58_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_58_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_58_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_58_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_60_PRE DSP2_MIDDLE5_AWB3_WT_Y_60_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_60_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_Y_60_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_60_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_60_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_60_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_60_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_60_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_60_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_61_PRE DSP2_MIDDLE5_AWB3_WT_Y_61_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_61_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_Y_61_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_61_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_61_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_61_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_61_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_61_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_61_PRE_POS)) - -/* 0x0B0 : awb3_config_44 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_44_OFFSET (0x0B0) -#define DSP2_MIDDLE5_AWB3_WT_Y_62_PRE DSP2_MIDDLE5_AWB3_WT_Y_62_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_62_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_Y_62_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_62_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_62_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_62_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_62_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_62_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_62_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_63_PRE DSP2_MIDDLE5_AWB3_WT_Y_63_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_63_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_63_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_63_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_63_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_63_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_63_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_63_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_63_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_64_PRE DSP2_MIDDLE5_AWB3_WT_Y_64_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_64_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_Y_64_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_64_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_64_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_64_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_64_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_64_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_64_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_65_PRE DSP2_MIDDLE5_AWB3_WT_Y_65_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_65_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_Y_65_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_65_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_65_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_65_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_65_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_65_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_65_PRE_POS)) - -/* 0x0B4 : awb3_config_45 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_45_OFFSET (0x0B4) -#define DSP2_MIDDLE5_AWB3_WT_Y_66_PRE DSP2_MIDDLE5_AWB3_WT_Y_66_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_66_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_Y_66_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_66_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_66_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_66_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_66_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_66_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_66_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_67_PRE DSP2_MIDDLE5_AWB3_WT_Y_67_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_67_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_67_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_67_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_67_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_67_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_67_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_67_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_67_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_68_PRE DSP2_MIDDLE5_AWB3_WT_Y_68_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_68_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_Y_68_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_68_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_68_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_68_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_68_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_68_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_68_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_70_PRE DSP2_MIDDLE5_AWB3_WT_Y_70_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_70_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_Y_70_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_70_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_70_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_70_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_70_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_70_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_70_PRE_POS)) - -/* 0x0B8 : awb3_config_46 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_46_OFFSET (0x0B8) -#define DSP2_MIDDLE5_AWB3_WT_Y_71_PRE DSP2_MIDDLE5_AWB3_WT_Y_71_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_71_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_Y_71_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_71_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_71_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_71_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_71_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_71_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_71_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_72_PRE DSP2_MIDDLE5_AWB3_WT_Y_72_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_72_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_72_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_72_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_72_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_72_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_72_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_72_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_72_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_73_PRE DSP2_MIDDLE5_AWB3_WT_Y_73_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_73_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_Y_73_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_73_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_73_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_73_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_73_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_73_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_73_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_74_PRE DSP2_MIDDLE5_AWB3_WT_Y_74_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_74_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_Y_74_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_74_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_74_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_74_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_74_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_74_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_74_PRE_POS)) - -/* 0x0BC : awb3_config_47 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_47_OFFSET (0x0BC) -#define DSP2_MIDDLE5_AWB3_WT_Y_75_PRE DSP2_MIDDLE5_AWB3_WT_Y_75_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_75_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_Y_75_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_75_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_75_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_75_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_75_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_75_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_75_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_76_PRE DSP2_MIDDLE5_AWB3_WT_Y_76_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_76_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_76_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_76_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_76_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_76_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_76_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_76_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_76_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_77_PRE DSP2_MIDDLE5_AWB3_WT_Y_77_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_77_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_Y_77_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_77_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_77_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_77_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_77_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_77_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_77_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_78_PRE DSP2_MIDDLE5_AWB3_WT_Y_78_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_78_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_Y_78_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_78_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_78_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_78_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_78_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_78_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_78_PRE_POS)) - -/* 0x0C0 : awb3_config_48 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_48_OFFSET (0x0C0) -#define DSP2_MIDDLE5_AWB3_WT_Y_80_PRE DSP2_MIDDLE5_AWB3_WT_Y_80_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_80_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_Y_80_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_80_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_80_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_80_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_80_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_80_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_80_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_81_PRE DSP2_MIDDLE5_AWB3_WT_Y_81_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_81_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_81_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_81_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_81_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_81_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_81_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_81_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_81_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_82_PRE DSP2_MIDDLE5_AWB3_WT_Y_82_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_82_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_Y_82_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_82_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_82_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_82_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_82_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_82_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_82_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_83_PRE DSP2_MIDDLE5_AWB3_WT_Y_83_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_83_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_Y_83_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_83_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_83_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_83_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_83_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_83_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_83_PRE_POS)) - -/* 0x0C4 : awb3_config_49 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_49_OFFSET (0x0C4) -#define DSP2_MIDDLE5_AWB3_WT_Y_84_PRE DSP2_MIDDLE5_AWB3_WT_Y_84_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_84_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_Y_84_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_84_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_84_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_84_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_84_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_84_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_84_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_85_PRE DSP2_MIDDLE5_AWB3_WT_Y_85_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_85_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_85_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_85_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_85_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_85_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_85_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_85_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_85_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_86_PRE DSP2_MIDDLE5_AWB3_WT_Y_86_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_86_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_Y_86_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_86_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_86_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_86_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_86_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_86_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_86_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_87_PRE DSP2_MIDDLE5_AWB3_WT_Y_87_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_87_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_Y_87_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_87_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_87_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_87_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_87_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_87_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_87_PRE_POS)) - -/* 0x0C8 : awb3_config_50 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_50_OFFSET (0x0C8) -#define DSP2_MIDDLE5_AWB3_WT_Y_88_PRE DSP2_MIDDLE5_AWB3_WT_Y_88_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_88_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_Y_88_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_88_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_88_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_88_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_88_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_88_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_88_PRE_POS)) - -/* 0x0CC : awb3_config_51 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_51_OFFSET (0x0CC) -#define DSP2_MIDDLE5_AWB3_BIN_MODE_PRE DSP2_MIDDLE5_AWB3_BIN_MODE_PRE -#define DSP2_MIDDLE5_AWB3_BIN_MODE_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_BIN_MODE_PRE_LEN (2U) -#define DSP2_MIDDLE5_AWB3_BIN_MODE_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_BIN_MODE_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_BIN_MODE_PRE_POS) -#define DSP2_MIDDLE5_AWB3_BIN_MODE_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_BIN_MODE_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_BIN_MODE_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_BIN_PIXEL_CLIP_PRE DSP2_MIDDLE5_AWB3_BIN_PIXEL_CLIP_PRE -#define DSP2_MIDDLE5_AWB3_BIN_PIXEL_CLIP_PRE_POS (2U) -#define DSP2_MIDDLE5_AWB3_BIN_PIXEL_CLIP_PRE_LEN (20U) -#define DSP2_MIDDLE5_AWB3_BIN_PIXEL_CLIP_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_BIN_PIXEL_CLIP_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_BIN_PIXEL_CLIP_PRE_POS) -#define DSP2_MIDDLE5_AWB3_BIN_PIXEL_CLIP_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_BIN_PIXEL_CLIP_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_BIN_PIXEL_CLIP_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_BIN_CLIP_EN_PRE DSP2_MIDDLE5_AWB3_BIN_CLIP_EN_PRE -#define DSP2_MIDDLE5_AWB3_BIN_CLIP_EN_PRE_POS (22U) -#define DSP2_MIDDLE5_AWB3_BIN_CLIP_EN_PRE_LEN (1U) -#define DSP2_MIDDLE5_AWB3_BIN_CLIP_EN_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_BIN_CLIP_EN_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_BIN_CLIP_EN_PRE_POS) -#define DSP2_MIDDLE5_AWB3_BIN_CLIP_EN_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_BIN_CLIP_EN_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_BIN_CLIP_EN_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_BIN_RATIO_LEVEL_PRE DSP2_MIDDLE5_AWB3_BIN_RATIO_LEVEL_PRE -#define DSP2_MIDDLE5_AWB3_BIN_RATIO_LEVEL_PRE_POS (23U) -#define DSP2_MIDDLE5_AWB3_BIN_RATIO_LEVEL_PRE_LEN (3U) -#define DSP2_MIDDLE5_AWB3_BIN_RATIO_LEVEL_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_BIN_RATIO_LEVEL_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_BIN_RATIO_LEVEL_PRE_POS) -#define DSP2_MIDDLE5_AWB3_BIN_RATIO_LEVEL_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_BIN_RATIO_LEVEL_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_BIN_RATIO_LEVEL_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_BIN_Y_LEVEL_PRE DSP2_MIDDLE5_AWB3_BIN_Y_LEVEL_PRE -#define DSP2_MIDDLE5_AWB3_BIN_Y_LEVEL_PRE_POS (26U) -#define DSP2_MIDDLE5_AWB3_BIN_Y_LEVEL_PRE_LEN (3U) -#define DSP2_MIDDLE5_AWB3_BIN_Y_LEVEL_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_BIN_Y_LEVEL_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_BIN_Y_LEVEL_PRE_POS) -#define DSP2_MIDDLE5_AWB3_BIN_Y_LEVEL_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_BIN_Y_LEVEL_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_BIN_Y_LEVEL_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_HIST_Y_USE_G_PRE DSP2_MIDDLE5_AWB3_HIST_Y_USE_G_PRE -#define DSP2_MIDDLE5_AWB3_HIST_Y_USE_G_PRE_POS (29U) -#define DSP2_MIDDLE5_AWB3_HIST_Y_USE_G_PRE_LEN (1U) -#define DSP2_MIDDLE5_AWB3_HIST_Y_USE_G_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_HIST_Y_USE_G_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_HIST_Y_USE_G_PRE_POS) -#define DSP2_MIDDLE5_AWB3_HIST_Y_USE_G_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_HIST_Y_USE_G_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_HIST_Y_USE_G_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_COUNT_ZERO_WT_PRE DSP2_MIDDLE5_AWB3_COUNT_ZERO_WT_PRE -#define DSP2_MIDDLE5_AWB3_COUNT_ZERO_WT_PRE_POS (30U) -#define DSP2_MIDDLE5_AWB3_COUNT_ZERO_WT_PRE_LEN (1U) -#define DSP2_MIDDLE5_AWB3_COUNT_ZERO_WT_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_COUNT_ZERO_WT_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_COUNT_ZERO_WT_PRE_POS) -#define DSP2_MIDDLE5_AWB3_COUNT_ZERO_WT_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_COUNT_ZERO_WT_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_COUNT_ZERO_WT_PRE_POS)) - -/* 0x0D0 : awb3_config_52 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_52_OFFSET (0x0D0) -#define DSP2_MIDDLE5_AWB3_INK_GAIN_PRE DSP2_MIDDLE5_AWB3_INK_GAIN_PRE -#define DSP2_MIDDLE5_AWB3_INK_GAIN_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_INK_GAIN_PRE_LEN (4U) -#define DSP2_MIDDLE5_AWB3_INK_GAIN_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_INK_GAIN_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_INK_GAIN_PRE_POS) -#define DSP2_MIDDLE5_AWB3_INK_GAIN_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_INK_GAIN_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_INK_GAIN_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_INK_TYPE_PRE DSP2_MIDDLE5_AWB3_INK_TYPE_PRE -#define DSP2_MIDDLE5_AWB3_INK_TYPE_PRE_POS (4U) -#define DSP2_MIDDLE5_AWB3_INK_TYPE_PRE_LEN (2U) -#define DSP2_MIDDLE5_AWB3_INK_TYPE_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_INK_TYPE_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_INK_TYPE_PRE_POS) -#define DSP2_MIDDLE5_AWB3_INK_TYPE_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_INK_TYPE_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_INK_TYPE_PRE_POS)) - -/* 0x0D4 : awb3_sta_0 */ -#define DSP2_MIDDLE5_AWB3_STA_0_OFFSET (0x0D4) -#define DSP2_MIDDLE5_AWB3_R_SUM0_R DSP2_MIDDLE5_AWB3_R_SUM0_R -#define DSP2_MIDDLE5_AWB3_R_SUM0_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_R_SUM0_R_LEN (32U) -#define DSP2_MIDDLE5_AWB3_R_SUM0_R_MSK (((1U << DSP2_MIDDLE5_AWB3_R_SUM0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_SUM0_R_POS) -#define DSP2_MIDDLE5_AWB3_R_SUM0_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_R_SUM0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_SUM0_R_POS)) - -/* 0x0D8 : awb3_sta_1 */ -#define DSP2_MIDDLE5_AWB3_STA_1_OFFSET (0x0D8) -#define DSP2_MIDDLE5_AWB3_G_SUM0_R DSP2_MIDDLE5_AWB3_G_SUM0_R -#define DSP2_MIDDLE5_AWB3_G_SUM0_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_G_SUM0_R_LEN (32U) -#define DSP2_MIDDLE5_AWB3_G_SUM0_R_MSK (((1U << DSP2_MIDDLE5_AWB3_G_SUM0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_G_SUM0_R_POS) -#define DSP2_MIDDLE5_AWB3_G_SUM0_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_G_SUM0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_G_SUM0_R_POS)) - -/* 0x0DC : awb3_sta_2 */ -#define DSP2_MIDDLE5_AWB3_STA_2_OFFSET (0x0DC) -#define DSP2_MIDDLE5_AWB3_B_SUM0_R DSP2_MIDDLE5_AWB3_B_SUM0_R -#define DSP2_MIDDLE5_AWB3_B_SUM0_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_B_SUM0_R_LEN (32U) -#define DSP2_MIDDLE5_AWB3_B_SUM0_R_MSK (((1U << DSP2_MIDDLE5_AWB3_B_SUM0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_SUM0_R_POS) -#define DSP2_MIDDLE5_AWB3_B_SUM0_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_B_SUM0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_SUM0_R_POS)) - -/* 0x0E0 : awb3_sta_3 */ -#define DSP2_MIDDLE5_AWB3_STA_3_OFFSET (0x0E0) -#define DSP2_MIDDLE5_AWB3_R_SUM_HEX0_R DSP2_MIDDLE5_AWB3_R_SUM_HEX0_R -#define DSP2_MIDDLE5_AWB3_R_SUM_HEX0_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_R_SUM_HEX0_R_LEN (32U) -#define DSP2_MIDDLE5_AWB3_R_SUM_HEX0_R_MSK (((1U << DSP2_MIDDLE5_AWB3_R_SUM_HEX0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_SUM_HEX0_R_POS) -#define DSP2_MIDDLE5_AWB3_R_SUM_HEX0_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_R_SUM_HEX0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_SUM_HEX0_R_POS)) - -/* 0x0E4 : awb3_sta_4 */ -#define DSP2_MIDDLE5_AWB3_STA_4_OFFSET (0x0E4) -#define DSP2_MIDDLE5_AWB3_G_SUM_HEX0_R DSP2_MIDDLE5_AWB3_G_SUM_HEX0_R -#define DSP2_MIDDLE5_AWB3_G_SUM_HEX0_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_G_SUM_HEX0_R_LEN (32U) -#define DSP2_MIDDLE5_AWB3_G_SUM_HEX0_R_MSK (((1U << DSP2_MIDDLE5_AWB3_G_SUM_HEX0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_G_SUM_HEX0_R_POS) -#define DSP2_MIDDLE5_AWB3_G_SUM_HEX0_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_G_SUM_HEX0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_G_SUM_HEX0_R_POS)) - -/* 0x0E8 : awb3_sta_5 */ -#define DSP2_MIDDLE5_AWB3_STA_5_OFFSET (0x0E8) -#define DSP2_MIDDLE5_AWB3_B_SUM_HEX0_R DSP2_MIDDLE5_AWB3_B_SUM_HEX0_R -#define DSP2_MIDDLE5_AWB3_B_SUM_HEX0_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_B_SUM_HEX0_R_LEN (32U) -#define DSP2_MIDDLE5_AWB3_B_SUM_HEX0_R_MSK (((1U << DSP2_MIDDLE5_AWB3_B_SUM_HEX0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_SUM_HEX0_R_POS) -#define DSP2_MIDDLE5_AWB3_B_SUM_HEX0_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_B_SUM_HEX0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_SUM_HEX0_R_POS)) - -/* 0x0EC : awb3_sta_6 */ -#define DSP2_MIDDLE5_AWB3_STA_6_OFFSET (0x0EC) -#define DSP2_MIDDLE5_AWB3_PIXEL_HEX0_R DSP2_MIDDLE5_AWB3_PIXEL_HEX0_R -#define DSP2_MIDDLE5_AWB3_PIXEL_HEX0_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_PIXEL_HEX0_R_LEN (20U) -#define DSP2_MIDDLE5_AWB3_PIXEL_HEX0_R_MSK (((1U << DSP2_MIDDLE5_AWB3_PIXEL_HEX0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_PIXEL_HEX0_R_POS) -#define DSP2_MIDDLE5_AWB3_PIXEL_HEX0_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_PIXEL_HEX0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_PIXEL_HEX0_R_POS)) - -/* 0x0F0 : awb3_sta_7 */ -#define DSP2_MIDDLE5_AWB3_STA_7_OFFSET (0x0F0) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y0U_R DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y0U_R -#define DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y0U_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y0U_R_LEN (8U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y0U_R_MSK (((1U << DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y0U_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y0U_R_POS) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y0U_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y0U_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y0U_R_POS)) - -/* 0x0F4 : awb3_sta_8 */ -#define DSP2_MIDDLE5_AWB3_STA_8_OFFSET (0x0F4) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y0L_R DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y0L_R -#define DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y0L_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y0L_R_LEN (32U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y0L_R_MSK (((1U << DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y0L_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y0L_R_POS) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y0L_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y0L_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y0L_R_POS)) - -/* 0x0F8 : awb3_sta_9 */ -#define DSP2_MIDDLE5_AWB3_STA_9_OFFSET (0x0F8) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y0U_R DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y0U_R -#define DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y0U_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y0U_R_LEN (8U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y0U_R_MSK (((1U << DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y0U_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y0U_R_POS) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y0U_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y0U_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y0U_R_POS)) - -/* 0x0FC : awb3_sta_10 */ -#define DSP2_MIDDLE5_AWB3_STA_10_OFFSET (0x0FC) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y0L_R DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y0L_R -#define DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y0L_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y0L_R_LEN (32U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y0L_R_MSK (((1U << DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y0L_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y0L_R_POS) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y0L_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y0L_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y0L_R_POS)) - -/* 0x100 : awb3_sta_11 */ -#define DSP2_MIDDLE5_AWB3_STA_11_OFFSET (0x100) -#define DSP2_MIDDLE5_AWB3_WT_HEX_Y0_R DSP2_MIDDLE5_AWB3_WT_HEX_Y0_R -#define DSP2_MIDDLE5_AWB3_WT_HEX_Y0_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_HEX_Y0_R_LEN (28U) -#define DSP2_MIDDLE5_AWB3_WT_HEX_Y0_R_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_HEX_Y0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_HEX_Y0_R_POS) -#define DSP2_MIDDLE5_AWB3_WT_HEX_Y0_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_HEX_Y0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_HEX_Y0_R_POS)) - -/* 0x104 : awb3_sta_12 */ -#define DSP2_MIDDLE5_AWB3_STA_12_OFFSET (0x104) -#define DSP2_MIDDLE5_AWB3_PIXEL_HEX_Y0_R DSP2_MIDDLE5_AWB3_PIXEL_HEX_Y0_R -#define DSP2_MIDDLE5_AWB3_PIXEL_HEX_Y0_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_PIXEL_HEX_Y0_R_LEN (20U) -#define DSP2_MIDDLE5_AWB3_PIXEL_HEX_Y0_R_MSK (((1U << DSP2_MIDDLE5_AWB3_PIXEL_HEX_Y0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_PIXEL_HEX_Y0_R_POS) -#define DSP2_MIDDLE5_AWB3_PIXEL_HEX_Y0_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_PIXEL_HEX_Y0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_PIXEL_HEX_Y0_R_POS)) - -/* 0x108 : awb3_sta_13 */ -#define DSP2_MIDDLE5_AWB3_STA_13_OFFSET (0x108) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST0U_R DSP2_MIDDLE5_AWB3_R_RATIO_HIST0U_R -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST0U_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST0U_R_LEN (8U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST0U_R_MSK (((1U << DSP2_MIDDLE5_AWB3_R_RATIO_HIST0U_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_HIST0U_R_POS) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST0U_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_R_RATIO_HIST0U_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_HIST0U_R_POS)) - -/* 0x10C : awb3_sta_14 */ -#define DSP2_MIDDLE5_AWB3_STA_14_OFFSET (0x10C) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST0L_R DSP2_MIDDLE5_AWB3_R_RATIO_HIST0L_R -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST0L_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST0L_R_LEN (32U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST0L_R_MSK (((1U << DSP2_MIDDLE5_AWB3_R_RATIO_HIST0L_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_HIST0L_R_POS) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST0L_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_R_RATIO_HIST0L_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_HIST0L_R_POS)) - -/* 0x110 : awb3_sta_15 */ -#define DSP2_MIDDLE5_AWB3_STA_15_OFFSET (0x110) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST0U_R DSP2_MIDDLE5_AWB3_B_RATIO_HIST0U_R -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST0U_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST0U_R_LEN (8U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST0U_R_MSK (((1U << DSP2_MIDDLE5_AWB3_B_RATIO_HIST0U_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_HIST0U_R_POS) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST0U_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_B_RATIO_HIST0U_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_HIST0U_R_POS)) - -/* 0x114 : awb3_sta_16 */ -#define DSP2_MIDDLE5_AWB3_STA_16_OFFSET (0x114) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST0L_R DSP2_MIDDLE5_AWB3_B_RATIO_HIST0L_R -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST0L_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST0L_R_LEN (32U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST0L_R_MSK (((1U << DSP2_MIDDLE5_AWB3_B_RATIO_HIST0L_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_HIST0L_R_POS) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST0L_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_B_RATIO_HIST0L_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_HIST0L_R_POS)) - -/* 0x118 : awb3_sta_17 */ -#define DSP2_MIDDLE5_AWB3_STA_17_OFFSET (0x118) -#define DSP2_MIDDLE5_AWB3_WT_HIST0_R DSP2_MIDDLE5_AWB3_WT_HIST0_R -#define DSP2_MIDDLE5_AWB3_WT_HIST0_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_HIST0_R_LEN (28U) -#define DSP2_MIDDLE5_AWB3_WT_HIST0_R_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_HIST0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_HIST0_R_POS) -#define DSP2_MIDDLE5_AWB3_WT_HIST0_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_HIST0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_HIST0_R_POS)) - -/* 0x11C : awb3_sta_18 */ -#define DSP2_MIDDLE5_AWB3_STA_18_OFFSET (0x11C) -#define DSP2_MIDDLE5_AWB3_PIXEL_HIST0_R DSP2_MIDDLE5_AWB3_PIXEL_HIST0_R -#define DSP2_MIDDLE5_AWB3_PIXEL_HIST0_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_PIXEL_HIST0_R_LEN (20U) -#define DSP2_MIDDLE5_AWB3_PIXEL_HIST0_R_MSK (((1U << DSP2_MIDDLE5_AWB3_PIXEL_HIST0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_PIXEL_HIST0_R_POS) -#define DSP2_MIDDLE5_AWB3_PIXEL_HIST0_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_PIXEL_HIST0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_PIXEL_HIST0_R_POS)) - -/* 0x120 : awb3_sta_19 */ -#define DSP2_MIDDLE5_AWB3_STA_19_OFFSET (0x120) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP0U_R DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP0U_R -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP0U_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP0U_R_LEN (8U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP0U_R_MSK (((1U << DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP0U_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP0U_R_POS) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP0U_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP0U_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP0U_R_POS)) - -/* 0x124 : awb3_sta_20 */ -#define DSP2_MIDDLE5_AWB3_STA_20_OFFSET (0x124) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP0L_R DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP0L_R -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP0L_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP0L_R_LEN (32U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP0L_R_MSK (((1U << DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP0L_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP0L_R_POS) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP0L_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP0L_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP0L_R_POS)) - -/* 0x128 : awb3_sta_21 */ -#define DSP2_MIDDLE5_AWB3_STA_21_OFFSET (0x128) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP0U_R DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP0U_R -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP0U_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP0U_R_LEN (8U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP0U_R_MSK (((1U << DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP0U_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP0U_R_POS) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP0U_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP0U_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP0U_R_POS)) - -/* 0x12C : awb3_sta_22 */ -#define DSP2_MIDDLE5_AWB3_STA_22_OFFSET (0x12C) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP0L_R DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP0L_R -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP0L_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP0L_R_LEN (32U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP0L_R_MSK (((1U << DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP0L_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP0L_R_POS) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP0L_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP0L_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP0L_R_POS)) - -/* 0x130 : awb3_sta_23 */ -#define DSP2_MIDDLE5_AWB3_STA_23_OFFSET (0x130) -#define DSP2_MIDDLE5_AWB3_WT_HIST_CLIP0_R DSP2_MIDDLE5_AWB3_WT_HIST_CLIP0_R -#define DSP2_MIDDLE5_AWB3_WT_HIST_CLIP0_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_HIST_CLIP0_R_LEN (28U) -#define DSP2_MIDDLE5_AWB3_WT_HIST_CLIP0_R_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_HIST_CLIP0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_HIST_CLIP0_R_POS) -#define DSP2_MIDDLE5_AWB3_WT_HIST_CLIP0_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_HIST_CLIP0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_HIST_CLIP0_R_POS)) - -/* 0x134 : awb3_sta_24 */ -#define DSP2_MIDDLE5_AWB3_STA_24_OFFSET (0x134) -#define DSP2_MIDDLE5_AWB3_PIXEL_HIST_CLIP0_R DSP2_MIDDLE5_AWB3_PIXEL_HIST_CLIP0_R -#define DSP2_MIDDLE5_AWB3_PIXEL_HIST_CLIP0_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_PIXEL_HIST_CLIP0_R_LEN (20U) -#define DSP2_MIDDLE5_AWB3_PIXEL_HIST_CLIP0_R_MSK (((1U << DSP2_MIDDLE5_AWB3_PIXEL_HIST_CLIP0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_PIXEL_HIST_CLIP0_R_POS) -#define DSP2_MIDDLE5_AWB3_PIXEL_HIST_CLIP0_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_PIXEL_HIST_CLIP0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_PIXEL_HIST_CLIP0_R_POS)) - -/* 0x138 : awb3_sta_25 */ -#define DSP2_MIDDLE5_AWB3_STA_25_OFFSET (0x138) -#define DSP2_MIDDLE5_AWB3_R_SUM1_R DSP2_MIDDLE5_AWB3_R_SUM1_R -#define DSP2_MIDDLE5_AWB3_R_SUM1_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_R_SUM1_R_LEN (32U) -#define DSP2_MIDDLE5_AWB3_R_SUM1_R_MSK (((1U << DSP2_MIDDLE5_AWB3_R_SUM1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_SUM1_R_POS) -#define DSP2_MIDDLE5_AWB3_R_SUM1_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_R_SUM1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_SUM1_R_POS)) - -/* 0x13C : awb3_sta_26 */ -#define DSP2_MIDDLE5_AWB3_STA_26_OFFSET (0x13C) -#define DSP2_MIDDLE5_AWB3_G_SUM1_R DSP2_MIDDLE5_AWB3_G_SUM1_R -#define DSP2_MIDDLE5_AWB3_G_SUM1_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_G_SUM1_R_LEN (32U) -#define DSP2_MIDDLE5_AWB3_G_SUM1_R_MSK (((1U << DSP2_MIDDLE5_AWB3_G_SUM1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_G_SUM1_R_POS) -#define DSP2_MIDDLE5_AWB3_G_SUM1_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_G_SUM1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_G_SUM1_R_POS)) - -/* 0x140 : awb3_sta_27 */ -#define DSP2_MIDDLE5_AWB3_STA_27_OFFSET (0x140) -#define DSP2_MIDDLE5_AWB3_B_SUM1_R DSP2_MIDDLE5_AWB3_B_SUM1_R -#define DSP2_MIDDLE5_AWB3_B_SUM1_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_B_SUM1_R_LEN (32U) -#define DSP2_MIDDLE5_AWB3_B_SUM1_R_MSK (((1U << DSP2_MIDDLE5_AWB3_B_SUM1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_SUM1_R_POS) -#define DSP2_MIDDLE5_AWB3_B_SUM1_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_B_SUM1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_SUM1_R_POS)) - -/* 0x144 : awb3_sta_28 */ -#define DSP2_MIDDLE5_AWB3_STA_28_OFFSET (0x144) -#define DSP2_MIDDLE5_AWB3_R_SUM_HEX1_R DSP2_MIDDLE5_AWB3_R_SUM_HEX1_R -#define DSP2_MIDDLE5_AWB3_R_SUM_HEX1_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_R_SUM_HEX1_R_LEN (32U) -#define DSP2_MIDDLE5_AWB3_R_SUM_HEX1_R_MSK (((1U << DSP2_MIDDLE5_AWB3_R_SUM_HEX1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_SUM_HEX1_R_POS) -#define DSP2_MIDDLE5_AWB3_R_SUM_HEX1_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_R_SUM_HEX1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_SUM_HEX1_R_POS)) - -/* 0x148 : awb3_sta_29 */ -#define DSP2_MIDDLE5_AWB3_STA_29_OFFSET (0x148) -#define DSP2_MIDDLE5_AWB3_G_SUM_HEX1_R DSP2_MIDDLE5_AWB3_G_SUM_HEX1_R -#define DSP2_MIDDLE5_AWB3_G_SUM_HEX1_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_G_SUM_HEX1_R_LEN (32U) -#define DSP2_MIDDLE5_AWB3_G_SUM_HEX1_R_MSK (((1U << DSP2_MIDDLE5_AWB3_G_SUM_HEX1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_G_SUM_HEX1_R_POS) -#define DSP2_MIDDLE5_AWB3_G_SUM_HEX1_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_G_SUM_HEX1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_G_SUM_HEX1_R_POS)) - -/* 0x14C : awb3_sta_30 */ -#define DSP2_MIDDLE5_AWB3_STA_30_OFFSET (0x14C) -#define DSP2_MIDDLE5_AWB3_B_SUM_HEX1_R DSP2_MIDDLE5_AWB3_B_SUM_HEX1_R -#define DSP2_MIDDLE5_AWB3_B_SUM_HEX1_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_B_SUM_HEX1_R_LEN (32U) -#define DSP2_MIDDLE5_AWB3_B_SUM_HEX1_R_MSK (((1U << DSP2_MIDDLE5_AWB3_B_SUM_HEX1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_SUM_HEX1_R_POS) -#define DSP2_MIDDLE5_AWB3_B_SUM_HEX1_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_B_SUM_HEX1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_SUM_HEX1_R_POS)) - -/* 0x150 : awb3_sta_31 */ -#define DSP2_MIDDLE5_AWB3_STA_31_OFFSET (0x150) -#define DSP2_MIDDLE5_AWB3_PIXEL_HEX1_R DSP2_MIDDLE5_AWB3_PIXEL_HEX1_R -#define DSP2_MIDDLE5_AWB3_PIXEL_HEX1_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_PIXEL_HEX1_R_LEN (20U) -#define DSP2_MIDDLE5_AWB3_PIXEL_HEX1_R_MSK (((1U << DSP2_MIDDLE5_AWB3_PIXEL_HEX1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_PIXEL_HEX1_R_POS) -#define DSP2_MIDDLE5_AWB3_PIXEL_HEX1_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_PIXEL_HEX1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_PIXEL_HEX1_R_POS)) - -/* 0x154 : awb3_sta_32 */ -#define DSP2_MIDDLE5_AWB3_STA_32_OFFSET (0x154) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y1U_R DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y1U_R -#define DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y1U_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y1U_R_LEN (8U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y1U_R_MSK (((1U << DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y1U_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y1U_R_POS) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y1U_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y1U_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y1U_R_POS)) - -/* 0x158 : awb3_sta_33 */ -#define DSP2_MIDDLE5_AWB3_STA_33_OFFSET (0x158) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y1L_R DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y1L_R -#define DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y1L_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y1L_R_LEN (32U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y1L_R_MSK (((1U << DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y1L_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y1L_R_POS) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y1L_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y1L_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y1L_R_POS)) - -/* 0x15C : awb3_sta_34 */ -#define DSP2_MIDDLE5_AWB3_STA_34_OFFSET (0x15C) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y1U_R DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y1U_R -#define DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y1U_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y1U_R_LEN (8U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y1U_R_MSK (((1U << DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y1U_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y1U_R_POS) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y1U_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y1U_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y1U_R_POS)) - -/* 0x160 : awb3_sta_35 */ -#define DSP2_MIDDLE5_AWB3_STA_35_OFFSET (0x160) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y1L_R DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y1L_R -#define DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y1L_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y1L_R_LEN (32U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y1L_R_MSK (((1U << DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y1L_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y1L_R_POS) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y1L_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y1L_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y1L_R_POS)) - -/* 0x164 : awb3_sta_36 */ -#define DSP2_MIDDLE5_AWB3_STA_36_OFFSET (0x164) -#define DSP2_MIDDLE5_AWB3_WT_HEX_Y1_R DSP2_MIDDLE5_AWB3_WT_HEX_Y1_R -#define DSP2_MIDDLE5_AWB3_WT_HEX_Y1_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_HEX_Y1_R_LEN (28U) -#define DSP2_MIDDLE5_AWB3_WT_HEX_Y1_R_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_HEX_Y1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_HEX_Y1_R_POS) -#define DSP2_MIDDLE5_AWB3_WT_HEX_Y1_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_HEX_Y1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_HEX_Y1_R_POS)) - -/* 0x168 : awb3_sta_37 */ -#define DSP2_MIDDLE5_AWB3_STA_37_OFFSET (0x168) -#define DSP2_MIDDLE5_AWB3_PIXEL_HEX_Y1_R DSP2_MIDDLE5_AWB3_PIXEL_HEX_Y1_R -#define DSP2_MIDDLE5_AWB3_PIXEL_HEX_Y1_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_PIXEL_HEX_Y1_R_LEN (20U) -#define DSP2_MIDDLE5_AWB3_PIXEL_HEX_Y1_R_MSK (((1U << DSP2_MIDDLE5_AWB3_PIXEL_HEX_Y1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_PIXEL_HEX_Y1_R_POS) -#define DSP2_MIDDLE5_AWB3_PIXEL_HEX_Y1_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_PIXEL_HEX_Y1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_PIXEL_HEX_Y1_R_POS)) - -/* 0x16C : awb3_sta_38 */ -#define DSP2_MIDDLE5_AWB3_STA_38_OFFSET (0x16C) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST1U_R DSP2_MIDDLE5_AWB3_R_RATIO_HIST1U_R -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST1U_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST1U_R_LEN (8U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST1U_R_MSK (((1U << DSP2_MIDDLE5_AWB3_R_RATIO_HIST1U_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_HIST1U_R_POS) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST1U_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_R_RATIO_HIST1U_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_HIST1U_R_POS)) - -/* 0x170 : awb3_sta_39 */ -#define DSP2_MIDDLE5_AWB3_STA_39_OFFSET (0x170) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST1L_R DSP2_MIDDLE5_AWB3_R_RATIO_HIST1L_R -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST1L_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST1L_R_LEN (32U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST1L_R_MSK (((1U << DSP2_MIDDLE5_AWB3_R_RATIO_HIST1L_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_HIST1L_R_POS) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST1L_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_R_RATIO_HIST1L_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_HIST1L_R_POS)) - -/* 0x174 : awb3_sta_40 */ -#define DSP2_MIDDLE5_AWB3_STA_40_OFFSET (0x174) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST1U_R DSP2_MIDDLE5_AWB3_B_RATIO_HIST1U_R -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST1U_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST1U_R_LEN (8U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST1U_R_MSK (((1U << DSP2_MIDDLE5_AWB3_B_RATIO_HIST1U_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_HIST1U_R_POS) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST1U_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_B_RATIO_HIST1U_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_HIST1U_R_POS)) - -/* 0x178 : awb3_sta_41 */ -#define DSP2_MIDDLE5_AWB3_STA_41_OFFSET (0x178) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST1L_R DSP2_MIDDLE5_AWB3_B_RATIO_HIST1L_R -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST1L_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST1L_R_LEN (32U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST1L_R_MSK (((1U << DSP2_MIDDLE5_AWB3_B_RATIO_HIST1L_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_HIST1L_R_POS) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST1L_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_B_RATIO_HIST1L_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_HIST1L_R_POS)) - -/* 0x17C : awb3_sta_42 */ -#define DSP2_MIDDLE5_AWB3_STA_42_OFFSET (0x17C) -#define DSP2_MIDDLE5_AWB3_WT_HIST1_R DSP2_MIDDLE5_AWB3_WT_HIST1_R -#define DSP2_MIDDLE5_AWB3_WT_HIST1_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_HIST1_R_LEN (28U) -#define DSP2_MIDDLE5_AWB3_WT_HIST1_R_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_HIST1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_HIST1_R_POS) -#define DSP2_MIDDLE5_AWB3_WT_HIST1_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_HIST1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_HIST1_R_POS)) - -/* 0x180 : awb3_sta_43 */ -#define DSP2_MIDDLE5_AWB3_STA_43_OFFSET (0x180) -#define DSP2_MIDDLE5_AWB3_PIXEL_HIST1_R DSP2_MIDDLE5_AWB3_PIXEL_HIST1_R -#define DSP2_MIDDLE5_AWB3_PIXEL_HIST1_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_PIXEL_HIST1_R_LEN (20U) -#define DSP2_MIDDLE5_AWB3_PIXEL_HIST1_R_MSK (((1U << DSP2_MIDDLE5_AWB3_PIXEL_HIST1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_PIXEL_HIST1_R_POS) -#define DSP2_MIDDLE5_AWB3_PIXEL_HIST1_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_PIXEL_HIST1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_PIXEL_HIST1_R_POS)) - -/* 0x184 : awb3_sta_44 */ -#define DSP2_MIDDLE5_AWB3_STA_44_OFFSET (0x184) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP1U_R DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP1U_R -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP1U_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP1U_R_LEN (8U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP1U_R_MSK (((1U << DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP1U_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP1U_R_POS) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP1U_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP1U_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP1U_R_POS)) - -/* 0x188 : awb3_sta_45 */ -#define DSP2_MIDDLE5_AWB3_STA_45_OFFSET (0x188) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP1L_R DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP1L_R -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP1L_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP1L_R_LEN (32U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP1L_R_MSK (((1U << DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP1L_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP1L_R_POS) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP1L_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP1L_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP1L_R_POS)) - -/* 0x18C : awb3_sta_46 */ -#define DSP2_MIDDLE5_AWB3_STA_46_OFFSET (0x18C) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP1U_R DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP1U_R -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP1U_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP1U_R_LEN (17U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP1U_R_MSK (((1U << DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP1U_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP1U_R_POS) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP1U_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP1U_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP1U_R_POS)) - -/* 0x190 : awb3_sta_47 */ -#define DSP2_MIDDLE5_AWB3_STA_47_OFFSET (0x190) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP1L_R DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP1L_R -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP1L_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP1L_R_LEN (32U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP1L_R_MSK (((1U << DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP1L_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP1L_R_POS) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP1L_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP1L_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP1L_R_POS)) - -/* 0x194 : awb3_sta_48 */ -#define DSP2_MIDDLE5_AWB3_STA_48_OFFSET (0x194) -#define DSP2_MIDDLE5_AWB3_WT_HIST_CLIP1_R DSP2_MIDDLE5_AWB3_WT_HIST_CLIP1_R -#define DSP2_MIDDLE5_AWB3_WT_HIST_CLIP1_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_HIST_CLIP1_R_LEN (28U) -#define DSP2_MIDDLE5_AWB3_WT_HIST_CLIP1_R_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_HIST_CLIP1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_HIST_CLIP1_R_POS) -#define DSP2_MIDDLE5_AWB3_WT_HIST_CLIP1_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_HIST_CLIP1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_HIST_CLIP1_R_POS)) - -/* 0x198 : awb3_sta_49 */ -#define DSP2_MIDDLE5_AWB3_STA_49_OFFSET (0x198) -#define DSP2_MIDDLE5_AWB3_PIXEL_HIST_CLIP1_R DSP2_MIDDLE5_AWB3_PIXEL_HIST_CLIP1_R -#define DSP2_MIDDLE5_AWB3_PIXEL_HIST_CLIP1_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_PIXEL_HIST_CLIP1_R_LEN (20U) -#define DSP2_MIDDLE5_AWB3_PIXEL_HIST_CLIP1_R_MSK (((1U << DSP2_MIDDLE5_AWB3_PIXEL_HIST_CLIP1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_PIXEL_HIST_CLIP1_R_POS) -#define DSP2_MIDDLE5_AWB3_PIXEL_HIST_CLIP1_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_PIXEL_HIST_CLIP1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_PIXEL_HIST_CLIP1_R_POS)) - -/* 0x19C : awb3_status_0 */ -#define DSP2_MIDDLE5_AWB3_STATUS_0_OFFSET (0x19C) -#define DSP2_MIDDLE5_AWB3_W_CNT_R DSP2_MIDDLE5_AWB3_W_CNT_R -#define DSP2_MIDDLE5_AWB3_W_CNT_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_W_CNT_R_LEN (5U) -#define DSP2_MIDDLE5_AWB3_W_CNT_R_MSK (((1U << DSP2_MIDDLE5_AWB3_W_CNT_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_W_CNT_R_POS) -#define DSP2_MIDDLE5_AWB3_W_CNT_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_W_CNT_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_W_CNT_R_POS)) -#define DSP2_MIDDLE5_AWB3_BUF_IDX_R DSP2_MIDDLE5_AWB3_BUF_IDX_R -#define DSP2_MIDDLE5_AWB3_BUF_IDX_R_POS (8U) -#define DSP2_MIDDLE5_AWB3_BUF_IDX_R_LEN (1U) -#define DSP2_MIDDLE5_AWB3_BUF_IDX_R_MSK (((1U << DSP2_MIDDLE5_AWB3_BUF_IDX_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_BUF_IDX_R_POS) -#define DSP2_MIDDLE5_AWB3_BUF_IDX_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_BUF_IDX_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_BUF_IDX_R_POS)) - -struct dsp2_middle5_reg { - /* 0x000 : awb3_config_0 */ - union { - struct { - uint32_t awb3_stat_x_max_pre : 11; /* [10: 0], r/w, 0x77f */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t awb3_stat_x_min_pre : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_30 : 4; /* [30:27], rsvd, 0x0 */ - uint32_t awb3_stat_en_pre : 1; /* [ 31], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_0; - - /* 0x004 : awb3_config_1 */ - union { - struct { - uint32_t awb3_stat_y_max_pre : 11; /* [10: 0], r/w, 0x437 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t awb3_stat_y_min_pre : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_config_1; - - /* 0x008 : awb3_config_2 */ - union { - struct { - uint32_t awb3_b_ratio_ofst_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t awb3_r_ratio_ofst_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_30 : 3; /* [30:28], rsvd, 0x0 */ - uint32_t awb3_g_divisor_pre : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } awb3_config_2; - - /* 0x00C : awb3_config_3 */ - union { - struct { - uint32_t awb3_b_ratio_mult_pre : 12; /* [11: 0], r/w, 0x100 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t awb3_r_ratio_mult_pre : 12; /* [27:16], r/w, 0x100 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_config_3; - - /* 0x010 : awb3_config_4 */ - union { - struct { - uint32_t awb3_ratio_sum_max_pre : 9; /* [ 8: 0], r/w, 0x0 */ - uint32_t awb3_ratio_sum_min_pre : 9; /* [17: 9], r/w, 0x0 */ - uint32_t awb3_wt_ratio_gain_pre : 8; /* [25:18], r/w, 0x0 */ - uint32_t awb3_wt_ratio_en_pre : 1; /* [ 26], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_config_4; - - /* 0x014 : awb3_config_5 */ - union { - struct { - uint32_t awb3_wt_ratio_00_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_ratio_01_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_ratio_02_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_ratio_03_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_5; - - /* 0x018 : awb3_config_6 */ - union { - struct { - uint32_t awb3_wt_ratio_04_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_ratio_05_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_ratio_06_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_ratio_07_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_6; - - /* 0x01C : awb3_config_7 */ - union { - struct { - uint32_t awb3_wt_ratio_08_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_ratio_10_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_ratio_11_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_ratio_12_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_7; - - /* 0x020 : awb3_config_8 */ - union { - struct { - uint32_t awb3_wt_ratio_13_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_ratio_14_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_ratio_15_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_ratio_16_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_8; - - /* 0x024 : awb3_config_9 */ - union { - struct { - uint32_t awb3_wt_ratio_17_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_ratio_18_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_ratio_20_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_ratio_21_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_9; - - /* 0x028 : awb3_config_10 */ - union { - struct { - uint32_t awb3_wt_ratio_22_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_ratio_23_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_ratio_24_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_ratio_25_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_10; - - /* 0x02C : awb3_config_11 */ - union { - struct { - uint32_t awb3_wt_ratio_26_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_ratio_27_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_ratio_28_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_ratio_30_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_11; - - /* 0x030 : awb3_config_12 */ - union { - struct { - uint32_t awb3_wt_ratio_31_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_ratio_32_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_ratio_33_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_ratio_34_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_12; - - /* 0x034 : awb3_config_13 */ - union { - struct { - uint32_t awb3_wt_ratio_35_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_ratio_36_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_ratio_37_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_ratio_38_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_13; - - /* 0x038 : awb3_config_14 */ - union { - struct { - uint32_t awb3_wt_ratio_40_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_ratio_41_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_ratio_42_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_ratio_43_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_14; - - /* 0x03C : awb3_config_15 */ - union { - struct { - uint32_t awb3_wt_ratio_44_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_ratio_45_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_ratio_46_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_ratio_47_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_15; - - /* 0x040 : awb3_config_16 */ - union { - struct { - uint32_t awb3_wt_ratio_48_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_ratio_50_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_ratio_51_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_ratio_52_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_16; - - /* 0x044 : awb3_config_17 */ - union { - struct { - uint32_t awb3_wt_ratio_53_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_ratio_54_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_ratio_55_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_ratio_56_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_17; - - /* 0x048 : awb3_config_18 */ - union { - struct { - uint32_t awb3_wt_ratio_57_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_ratio_58_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_ratio_60_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_ratio_61_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_18; - - /* 0x04C : awb3_config_19 */ - union { - struct { - uint32_t awb3_wt_ratio_62_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_ratio_63_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_ratio_64_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_ratio_65_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_19; - - /* 0x050 : awb3_config_20 */ - union { - struct { - uint32_t awb3_wt_ratio_66_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_ratio_67_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_ratio_68_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_ratio_70_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_20; - - /* 0x054 : awb3_config_21 */ - union { - struct { - uint32_t awb3_wt_ratio_71_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_ratio_72_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_ratio_73_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_ratio_74_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_21; - - /* 0x058 : awb3_config_22 */ - union { - struct { - uint32_t awb3_wt_ratio_75_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_ratio_76_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_ratio_77_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_ratio_78_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_22; - - /* 0x05C : awb3_config_23 */ - union { - struct { - uint32_t awb3_wt_ratio_80_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_ratio_81_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_ratio_82_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_ratio_83_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_23; - - /* 0x060 : awb3_config_24 */ - union { - struct { - uint32_t awb3_wt_ratio_84_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_ratio_85_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_ratio_86_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_ratio_87_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_24; - - /* 0x064 : awb3_config_25 */ - union { - struct { - uint32_t awb3_wt_ratio_88_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_config_25; - - /* 0x068 : awb3_config_26 */ - union { - struct { - uint32_t awb3_y_r_coeff_pre : 12; /* [11: 0], r/w, 0x4d */ - uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_config_26; - - /* 0x06C : awb3_config_27 */ - union { - struct { - uint32_t awb3_y_g_coeff_pre : 12; /* [11: 0], r/w, 0x96 */ - uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_config_27; - - /* 0x070 : awb3_config_28 */ - union { - struct { - uint32_t awb3_y_b_coeff_pre : 12; /* [11: 0], r/w, 0x1d */ - uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_config_28; - - /* 0x074 : awb3_config_29 */ - union { - struct { - uint32_t awb3_wt_y_gain_pre : 8; /* [ 7: 0], r/w, 0x10 */ - uint32_t awb3_wt_y_en_pre : 1; /* [ 8], r/w, 0x1 */ - uint32_t reserved_9_11 : 3; /* [11: 9], rsvd, 0x0 */ - uint32_t awb3_wt_y_use_g_pre : 1; /* [ 12], r/w, 0x0 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_config_29; - - /* 0x078 : awb3_config_30 */ - union { - struct { - uint32_t awb3_wt_y_00_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_y_01_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_y_02_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_y_03_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_30; - - /* 0x07C : awb3_config_31 */ - union { - struct { - uint32_t awb3_wt_y_04_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_y_05_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_y_06_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_y_07_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_31; - - /* 0x080 : awb3_config_32 */ - union { - struct { - uint32_t awb3_wt_y_08_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_y_10_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_y_11_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_y_12_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_32; - - /* 0x084 : awb3_config_33 */ - union { - struct { - uint32_t awb3_wt_y_13_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_y_14_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_y_15_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_y_16_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_33; - - /* 0x088 : awb3_config_34 */ - union { - struct { - uint32_t awb3_wt_y_17_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_y_18_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_y_20_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_y_21_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_34; - - /* 0x08C : awb3_config_35 */ - union { - struct { - uint32_t awb3_wt_y_22_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_y_23_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_y_24_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_y_25_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_35; - - /* 0x090 : awb3_config_36 */ - union { - struct { - uint32_t awb3_wt_y_26_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_y_27_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_y_28_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_y_30_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_36; - - /* 0x094 : awb3_config_37 */ - union { - struct { - uint32_t awb3_wt_y_31_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_y_32_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_y_33_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_y_34_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_37; - - /* 0x098 : awb3_config_38 */ - union { - struct { - uint32_t awb3_wt_y_35_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_y_36_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_y_37_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_y_38_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_38; - - /* 0x09C : awb3_config_39 */ - union { - struct { - uint32_t awb3_wt_y_40_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_y_41_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_y_42_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_y_43_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_39; - - /* 0x0A0 : awb3_config_40 */ - union { - struct { - uint32_t awb3_wt_y_44_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_y_45_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_y_46_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_y_47_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_40; - - /* 0x0A4 : awb3_config_41 */ - union { - struct { - uint32_t awb3_wt_y_48_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_y_50_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_y_51_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_y_52_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_41; - - /* 0x0A8 : awb3_config_42 */ - union { - struct { - uint32_t awb3_wt_y_53_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_y_54_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_y_55_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_y_56_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_42; - - /* 0x0AC : awb3_config_43 */ - union { - struct { - uint32_t awb3_wt_y_57_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_y_58_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_y_60_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_y_61_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_43; - - /* 0x0B0 : awb3_config_44 */ - union { - struct { - uint32_t awb3_wt_y_62_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_y_63_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_y_64_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_y_65_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_44; - - /* 0x0B4 : awb3_config_45 */ - union { - struct { - uint32_t awb3_wt_y_66_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_y_67_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_y_68_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_y_70_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_45; - - /* 0x0B8 : awb3_config_46 */ - union { - struct { - uint32_t awb3_wt_y_71_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_y_72_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_y_73_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_y_74_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_46; - - /* 0x0BC : awb3_config_47 */ - union { - struct { - uint32_t awb3_wt_y_75_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_y_76_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_y_77_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_y_78_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_47; - - /* 0x0C0 : awb3_config_48 */ - union { - struct { - uint32_t awb3_wt_y_80_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_y_81_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_y_82_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_y_83_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_48; - - /* 0x0C4 : awb3_config_49 */ - union { - struct { - uint32_t awb3_wt_y_84_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_y_85_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_y_86_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_y_87_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_49; - - /* 0x0C8 : awb3_config_50 */ - union { - struct { - uint32_t awb3_wt_y_88_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_config_50; - - /* 0x0CC : awb3_config_51 */ - union { - struct { - uint32_t awb3_bin_mode_pre : 2; /* [ 1: 0], r/w, 0x3 */ - uint32_t awb3_bin_pixel_clip_pre : 20; /* [21: 2], r/w, 0xfd200 */ - uint32_t awb3_bin_clip_en_pre : 1; /* [ 22], r/w, 0x0 */ - uint32_t awb3_bin_ratio_level_pre : 3; /* [25:23], r/w, 0x3 */ - uint32_t awb3_bin_y_level_pre : 3; /* [28:26], r/w, 0x3 */ - uint32_t awb3_hist_y_use_g_pre : 1; /* [ 29], r/w, 0x0 */ - uint32_t awb3_count_zero_wt_pre : 1; /* [ 30], r/w, 0x0 */ - uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_config_51; - - /* 0x0D0 : awb3_config_52 */ - union { - struct { - uint32_t awb3_ink_gain_pre : 4; /* [ 3: 0], r/w, 0x1 */ - uint32_t awb3_ink_type_pre : 2; /* [ 5: 4], r/w, 0x0 */ - uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_config_52; - - /* 0x0D4 : awb3_sta_0 */ - union { - struct { - uint32_t awb3_r_sum0_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_0; - - /* 0x0D8 : awb3_sta_1 */ - union { - struct { - uint32_t awb3_g_sum0_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_1; - - /* 0x0DC : awb3_sta_2 */ - union { - struct { - uint32_t awb3_b_sum0_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_2; - - /* 0x0E0 : awb3_sta_3 */ - union { - struct { - uint32_t awb3_r_sum_hex0_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_3; - - /* 0x0E4 : awb3_sta_4 */ - union { - struct { - uint32_t awb3_g_sum_hex0_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_4; - - /* 0x0E8 : awb3_sta_5 */ - union { - struct { - uint32_t awb3_b_sum_hex0_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_5; - - /* 0x0EC : awb3_sta_6 */ - union { - struct { - uint32_t awb3_pixel_hex0_r : 20; /* [19: 0], r, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_6; - - /* 0x0F0 : awb3_sta_7 */ - union { - struct { - uint32_t awb3_r_ratio_hex_y0u_r : 8; /* [ 7: 0], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_7; - - /* 0x0F4 : awb3_sta_8 */ - union { - struct { - uint32_t awb3_r_ratio_hex_y0l_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_8; - - /* 0x0F8 : awb3_sta_9 */ - union { - struct { - uint32_t awb3_b_ratio_hex_y0u_r : 8; /* [ 7: 0], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_9; - - /* 0x0FC : awb3_sta_10 */ - union { - struct { - uint32_t awb3_b_ratio_hex_y0l_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_10; - - /* 0x100 : awb3_sta_11 */ - union { - struct { - uint32_t awb3_wt_hex_y0_r : 28; /* [27: 0], r, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_11; - - /* 0x104 : awb3_sta_12 */ - union { - struct { - uint32_t awb3_pixel_hex_y0_r : 20; /* [19: 0], r, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_12; - - /* 0x108 : awb3_sta_13 */ - union { - struct { - uint32_t awb3_r_ratio_hist0u_r : 8; /* [ 7: 0], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_13; - - /* 0x10C : awb3_sta_14 */ - union { - struct { - uint32_t awb3_r_ratio_hist0l_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_14; - - /* 0x110 : awb3_sta_15 */ - union { - struct { - uint32_t awb3_b_ratio_hist0u_r : 8; /* [ 7: 0], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_15; - - /* 0x114 : awb3_sta_16 */ - union { - struct { - uint32_t awb3_b_ratio_hist0l_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_16; - - /* 0x118 : awb3_sta_17 */ - union { - struct { - uint32_t awb3_wt_hist0_r : 28; /* [27: 0], r, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_17; - - /* 0x11C : awb3_sta_18 */ - union { - struct { - uint32_t awb3_pixel_hist0_r : 20; /* [19: 0], r, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_18; - - /* 0x120 : awb3_sta_19 */ - union { - struct { - uint32_t awb3_r_ratio_hist_clip0u_r : 8; /* [ 7: 0], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_19; - - /* 0x124 : awb3_sta_20 */ - union { - struct { - uint32_t awb3_r_ratio_hist_clip0l_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_20; - - /* 0x128 : awb3_sta_21 */ - union { - struct { - uint32_t awb3_b_ratio_hist_clip0u_r : 8; /* [ 7: 0], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_21; - - /* 0x12C : awb3_sta_22 */ - union { - struct { - uint32_t awb3_b_ratio_hist_clip0l_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_22; - - /* 0x130 : awb3_sta_23 */ - union { - struct { - uint32_t awb3_wt_hist_clip0_r : 28; /* [27: 0], r, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_23; - - /* 0x134 : awb3_sta_24 */ - union { - struct { - uint32_t awb3_pixel_hist_clip0_r : 20; /* [19: 0], r, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_24; - - /* 0x138 : awb3_sta_25 */ - union { - struct { - uint32_t awb3_r_sum1_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_25; - - /* 0x13C : awb3_sta_26 */ - union { - struct { - uint32_t awb3_g_sum1_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_26; - - /* 0x140 : awb3_sta_27 */ - union { - struct { - uint32_t awb3_b_sum1_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_27; - - /* 0x144 : awb3_sta_28 */ - union { - struct { - uint32_t awb3_r_sum_hex1_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_28; - - /* 0x148 : awb3_sta_29 */ - union { - struct { - uint32_t awb3_g_sum_hex1_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_29; - - /* 0x14C : awb3_sta_30 */ - union { - struct { - uint32_t awb3_b_sum_hex1_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_30; - - /* 0x150 : awb3_sta_31 */ - union { - struct { - uint32_t awb3_pixel_hex1_r : 20; /* [19: 0], r, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_31; - - /* 0x154 : awb3_sta_32 */ - union { - struct { - uint32_t awb3_r_ratio_hex_y1u_r : 8; /* [ 7: 0], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_32; - - /* 0x158 : awb3_sta_33 */ - union { - struct { - uint32_t awb3_r_ratio_hex_y1l_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_33; - - /* 0x15C : awb3_sta_34 */ - union { - struct { - uint32_t awb3_b_ratio_hex_y1u_r : 8; /* [ 7: 0], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_34; - - /* 0x160 : awb3_sta_35 */ - union { - struct { - uint32_t awb3_b_ratio_hex_y1l_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_35; - - /* 0x164 : awb3_sta_36 */ - union { - struct { - uint32_t awb3_wt_hex_y1_r : 28; /* [27: 0], r, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_36; - - /* 0x168 : awb3_sta_37 */ - union { - struct { - uint32_t awb3_pixel_hex_y1_r : 20; /* [19: 0], r, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_37; - - /* 0x16C : awb3_sta_38 */ - union { - struct { - uint32_t awb3_r_ratio_hist1u_r : 8; /* [ 7: 0], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_38; - - /* 0x170 : awb3_sta_39 */ - union { - struct { - uint32_t awb3_r_ratio_hist1l_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_39; - - /* 0x174 : awb3_sta_40 */ - union { - struct { - uint32_t awb3_b_ratio_hist1u_r : 8; /* [ 7: 0], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_40; - - /* 0x178 : awb3_sta_41 */ - union { - struct { - uint32_t awb3_b_ratio_hist1l_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_41; - - /* 0x17C : awb3_sta_42 */ - union { - struct { - uint32_t awb3_wt_hist1_r : 28; /* [27: 0], r, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_42; - - /* 0x180 : awb3_sta_43 */ - union { - struct { - uint32_t awb3_pixel_hist1_r : 20; /* [19: 0], r, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_43; - - /* 0x184 : awb3_sta_44 */ - union { - struct { - uint32_t awb3_r_ratio_hist_clip1u_r : 8; /* [ 7: 0], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_44; - - /* 0x188 : awb3_sta_45 */ - union { - struct { - uint32_t awb3_r_ratio_hist_clip1l_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_45; - - /* 0x18C : awb3_sta_46 */ - union { - struct { - uint32_t awb3_b_ratio_hist_clip1u_r : 17; /* [16: 0], r, 0x0 */ - uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_46; - - /* 0x190 : awb3_sta_47 */ - union { - struct { - uint32_t awb3_b_ratio_hist_clip1l_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_47; - - /* 0x194 : awb3_sta_48 */ - union { - struct { - uint32_t awb3_wt_hist_clip1_r : 28; /* [27: 0], r, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_48; - - /* 0x198 : awb3_sta_49 */ - union { - struct { - uint32_t awb3_pixel_hist_clip1_r : 20; /* [19: 0], r, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_49; - - /* 0x19C : awb3_status_0 */ - union { - struct { - uint32_t awb3_w_cnt_r : 5; /* [ 4: 0], r, 0x0 */ - uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ - uint32_t awb3_buf_idx_r : 1; /* [ 8], r, 0x0 */ - uint32_t reserved_9_31 : 23; /* [31: 9], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_status_0; -}; - -typedef volatile struct dsp2_middle5_reg dsp2_middle5_reg_t; - -#endif /* __DSP2_MIDDLE5_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_middle_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_middle_reg.h deleted file mode 100644 index c36d1c464f..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_middle_reg.h +++ /dev/null @@ -1,1278 +0,0 @@ -/** - ****************************************************************************** - * @file dsp2_middle_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __DSP2_MIDDLE_REG_H__ -#define __DSP2_MIDDLE_REG_H__ - -#include "bl808.h" - -/* 0x224 : LSC_setting */ -#define DSP2_MIDDLE_LSC_SETTING_OFFSET (0x224) -#define DSP2_MIDDLE_LSC_ON_W DSP2_MIDDLE_LSC_ON_W -#define DSP2_MIDDLE_LSC_ON_W_POS (8U) -#define DSP2_MIDDLE_LSC_ON_W_LEN (1U) -#define DSP2_MIDDLE_LSC_ON_W_MSK (((1U << DSP2_MIDDLE_LSC_ON_W_LEN) - 1) << DSP2_MIDDLE_LSC_ON_W_POS) -#define DSP2_MIDDLE_LSC_ON_W_UMSK (~(((1U << DSP2_MIDDLE_LSC_ON_W_LEN) - 1) << DSP2_MIDDLE_LSC_ON_W_POS)) -#define DSP2_MIDDLE_X_OFFSET_W DSP2_MIDDLE_X_OFFSET_W -#define DSP2_MIDDLE_X_OFFSET_W_POS (16U) -#define DSP2_MIDDLE_X_OFFSET_W_LEN (8U) -#define DSP2_MIDDLE_X_OFFSET_W_MSK (((1U << DSP2_MIDDLE_X_OFFSET_W_LEN) - 1) << DSP2_MIDDLE_X_OFFSET_W_POS) -#define DSP2_MIDDLE_X_OFFSET_W_UMSK (~(((1U << DSP2_MIDDLE_X_OFFSET_W_LEN) - 1) << DSP2_MIDDLE_X_OFFSET_W_POS)) -#define DSP2_MIDDLE_Y_OFFSET_W DSP2_MIDDLE_Y_OFFSET_W -#define DSP2_MIDDLE_Y_OFFSET_W_POS (24U) -#define DSP2_MIDDLE_Y_OFFSET_W_LEN (8U) -#define DSP2_MIDDLE_Y_OFFSET_W_MSK (((1U << DSP2_MIDDLE_Y_OFFSET_W_LEN) - 1) << DSP2_MIDDLE_Y_OFFSET_W_POS) -#define DSP2_MIDDLE_Y_OFFSET_W_UMSK (~(((1U << DSP2_MIDDLE_Y_OFFSET_W_LEN) - 1) << DSP2_MIDDLE_Y_OFFSET_W_POS)) - -/* 0x228 : LSC_coeff_R_A */ -#define DSP2_MIDDLE_LSC_COEFF_R_A_OFFSET (0x228) -#define DSP2_MIDDLE_R_ACOEFF_W DSP2_MIDDLE_R_ACOEFF_W -#define DSP2_MIDDLE_R_ACOEFF_W_POS (0U) -#define DSP2_MIDDLE_R_ACOEFF_W_LEN (23U) -#define DSP2_MIDDLE_R_ACOEFF_W_MSK (((1U << DSP2_MIDDLE_R_ACOEFF_W_LEN) - 1) << DSP2_MIDDLE_R_ACOEFF_W_POS) -#define DSP2_MIDDLE_R_ACOEFF_W_UMSK (~(((1U << DSP2_MIDDLE_R_ACOEFF_W_LEN) - 1) << DSP2_MIDDLE_R_ACOEFF_W_POS)) - -/* 0x22C : LSC_coeff_R_BE */ -#define DSP2_MIDDLE_LSC_COEFF_R_BE_OFFSET (0x22C) -#define DSP2_MIDDLE_R_BCOEFF_W DSP2_MIDDLE_R_BCOEFF_W -#define DSP2_MIDDLE_R_BCOEFF_W_POS (0U) -#define DSP2_MIDDLE_R_BCOEFF_W_LEN (13U) -#define DSP2_MIDDLE_R_BCOEFF_W_MSK (((1U << DSP2_MIDDLE_R_BCOEFF_W_LEN) - 1) << DSP2_MIDDLE_R_BCOEFF_W_POS) -#define DSP2_MIDDLE_R_BCOEFF_W_UMSK (~(((1U << DSP2_MIDDLE_R_BCOEFF_W_LEN) - 1) << DSP2_MIDDLE_R_BCOEFF_W_POS)) -#define DSP2_MIDDLE_R_ECOEFF_W DSP2_MIDDLE_R_ECOEFF_W -#define DSP2_MIDDLE_R_ECOEFF_W_POS (16U) -#define DSP2_MIDDLE_R_ECOEFF_W_LEN (13U) -#define DSP2_MIDDLE_R_ECOEFF_W_MSK (((1U << DSP2_MIDDLE_R_ECOEFF_W_LEN) - 1) << DSP2_MIDDLE_R_ECOEFF_W_POS) -#define DSP2_MIDDLE_R_ECOEFF_W_UMSK (~(((1U << DSP2_MIDDLE_R_ECOEFF_W_LEN) - 1) << DSP2_MIDDLE_R_ECOEFF_W_POS)) - -/* 0x230 : LSC_coeff_R_CD */ -#define DSP2_MIDDLE_LSC_COEFF_R_CD_OFFSET (0x230) -#define DSP2_MIDDLE_R_DCOEFF_W DSP2_MIDDLE_R_DCOEFF_W -#define DSP2_MIDDLE_R_DCOEFF_W_POS (0U) -#define DSP2_MIDDLE_R_DCOEFF_W_LEN (23U) -#define DSP2_MIDDLE_R_DCOEFF_W_MSK (((1U << DSP2_MIDDLE_R_DCOEFF_W_LEN) - 1) << DSP2_MIDDLE_R_DCOEFF_W_POS) -#define DSP2_MIDDLE_R_DCOEFF_W_UMSK (~(((1U << DSP2_MIDDLE_R_DCOEFF_W_LEN) - 1) << DSP2_MIDDLE_R_DCOEFF_W_POS)) -#define DSP2_MIDDLE_R_CCOEFF_W DSP2_MIDDLE_R_CCOEFF_W -#define DSP2_MIDDLE_R_CCOEFF_W_POS (24U) -#define DSP2_MIDDLE_R_CCOEFF_W_LEN (8U) -#define DSP2_MIDDLE_R_CCOEFF_W_MSK (((1U << DSP2_MIDDLE_R_CCOEFF_W_LEN) - 1) << DSP2_MIDDLE_R_CCOEFF_W_POS) -#define DSP2_MIDDLE_R_CCOEFF_W_UMSK (~(((1U << DSP2_MIDDLE_R_CCOEFF_W_LEN) - 1) << DSP2_MIDDLE_R_CCOEFF_W_POS)) - -/* 0x234 : LSC_coeff_R_G */ -#define DSP2_MIDDLE_LSC_COEFF_R_G_OFFSET (0x234) -#define DSP2_MIDDLE_R_GCOEFF_W DSP2_MIDDLE_R_GCOEFF_W -#define DSP2_MIDDLE_R_GCOEFF_W_POS (0U) -#define DSP2_MIDDLE_R_GCOEFF_W_LEN (23U) -#define DSP2_MIDDLE_R_GCOEFF_W_MSK (((1U << DSP2_MIDDLE_R_GCOEFF_W_LEN) - 1) << DSP2_MIDDLE_R_GCOEFF_W_POS) -#define DSP2_MIDDLE_R_GCOEFF_W_UMSK (~(((1U << DSP2_MIDDLE_R_GCOEFF_W_LEN) - 1) << DSP2_MIDDLE_R_GCOEFF_W_POS)) - -/* 0x238 : LSC_coeff_G_A */ -#define DSP2_MIDDLE_LSC_COEFF_G_A_OFFSET (0x238) -#define DSP2_MIDDLE_G_ACOEFF_W DSP2_MIDDLE_G_ACOEFF_W -#define DSP2_MIDDLE_G_ACOEFF_W_POS (0U) -#define DSP2_MIDDLE_G_ACOEFF_W_LEN (23U) -#define DSP2_MIDDLE_G_ACOEFF_W_MSK (((1U << DSP2_MIDDLE_G_ACOEFF_W_LEN) - 1) << DSP2_MIDDLE_G_ACOEFF_W_POS) -#define DSP2_MIDDLE_G_ACOEFF_W_UMSK (~(((1U << DSP2_MIDDLE_G_ACOEFF_W_LEN) - 1) << DSP2_MIDDLE_G_ACOEFF_W_POS)) - -/* 0x23C : LSC_coeff_G_BE */ -#define DSP2_MIDDLE_LSC_COEFF_G_BE_OFFSET (0x23C) -#define DSP2_MIDDLE_G_BCOEFF_W DSP2_MIDDLE_G_BCOEFF_W -#define DSP2_MIDDLE_G_BCOEFF_W_POS (0U) -#define DSP2_MIDDLE_G_BCOEFF_W_LEN (13U) -#define DSP2_MIDDLE_G_BCOEFF_W_MSK (((1U << DSP2_MIDDLE_G_BCOEFF_W_LEN) - 1) << DSP2_MIDDLE_G_BCOEFF_W_POS) -#define DSP2_MIDDLE_G_BCOEFF_W_UMSK (~(((1U << DSP2_MIDDLE_G_BCOEFF_W_LEN) - 1) << DSP2_MIDDLE_G_BCOEFF_W_POS)) -#define DSP2_MIDDLE_G_ECOEFF_W DSP2_MIDDLE_G_ECOEFF_W -#define DSP2_MIDDLE_G_ECOEFF_W_POS (16U) -#define DSP2_MIDDLE_G_ECOEFF_W_LEN (13U) -#define DSP2_MIDDLE_G_ECOEFF_W_MSK (((1U << DSP2_MIDDLE_G_ECOEFF_W_LEN) - 1) << DSP2_MIDDLE_G_ECOEFF_W_POS) -#define DSP2_MIDDLE_G_ECOEFF_W_UMSK (~(((1U << DSP2_MIDDLE_G_ECOEFF_W_LEN) - 1) << DSP2_MIDDLE_G_ECOEFF_W_POS)) - -/* 0x240 : LSC_coeff_G_CD */ -#define DSP2_MIDDLE_LSC_COEFF_G_CD_OFFSET (0x240) -#define DSP2_MIDDLE_G_DCOEFF_W DSP2_MIDDLE_G_DCOEFF_W -#define DSP2_MIDDLE_G_DCOEFF_W_POS (0U) -#define DSP2_MIDDLE_G_DCOEFF_W_LEN (23U) -#define DSP2_MIDDLE_G_DCOEFF_W_MSK (((1U << DSP2_MIDDLE_G_DCOEFF_W_LEN) - 1) << DSP2_MIDDLE_G_DCOEFF_W_POS) -#define DSP2_MIDDLE_G_DCOEFF_W_UMSK (~(((1U << DSP2_MIDDLE_G_DCOEFF_W_LEN) - 1) << DSP2_MIDDLE_G_DCOEFF_W_POS)) -#define DSP2_MIDDLE_G_CCOEFF_W DSP2_MIDDLE_G_CCOEFF_W -#define DSP2_MIDDLE_G_CCOEFF_W_POS (24U) -#define DSP2_MIDDLE_G_CCOEFF_W_LEN (8U) -#define DSP2_MIDDLE_G_CCOEFF_W_MSK (((1U << DSP2_MIDDLE_G_CCOEFF_W_LEN) - 1) << DSP2_MIDDLE_G_CCOEFF_W_POS) -#define DSP2_MIDDLE_G_CCOEFF_W_UMSK (~(((1U << DSP2_MIDDLE_G_CCOEFF_W_LEN) - 1) << DSP2_MIDDLE_G_CCOEFF_W_POS)) - -/* 0x244 : LSC_coeff_G_G */ -#define DSP2_MIDDLE_LSC_COEFF_G_G_OFFSET (0x244) -#define DSP2_MIDDLE_G_GCOEFF_W DSP2_MIDDLE_G_GCOEFF_W -#define DSP2_MIDDLE_G_GCOEFF_W_POS (0U) -#define DSP2_MIDDLE_G_GCOEFF_W_LEN (23U) -#define DSP2_MIDDLE_G_GCOEFF_W_MSK (((1U << DSP2_MIDDLE_G_GCOEFF_W_LEN) - 1) << DSP2_MIDDLE_G_GCOEFF_W_POS) -#define DSP2_MIDDLE_G_GCOEFF_W_UMSK (~(((1U << DSP2_MIDDLE_G_GCOEFF_W_LEN) - 1) << DSP2_MIDDLE_G_GCOEFF_W_POS)) - -/* 0x248 : LSC_coeff_B_A */ -#define DSP2_MIDDLE_LSC_COEFF_B_A_OFFSET (0x248) -#define DSP2_MIDDLE_B_ACOEFF_W DSP2_MIDDLE_B_ACOEFF_W -#define DSP2_MIDDLE_B_ACOEFF_W_POS (0U) -#define DSP2_MIDDLE_B_ACOEFF_W_LEN (23U) -#define DSP2_MIDDLE_B_ACOEFF_W_MSK (((1U << DSP2_MIDDLE_B_ACOEFF_W_LEN) - 1) << DSP2_MIDDLE_B_ACOEFF_W_POS) -#define DSP2_MIDDLE_B_ACOEFF_W_UMSK (~(((1U << DSP2_MIDDLE_B_ACOEFF_W_LEN) - 1) << DSP2_MIDDLE_B_ACOEFF_W_POS)) - -/* 0x24C : LSC_coeff_B_BE */ -#define DSP2_MIDDLE_LSC_COEFF_B_BE_OFFSET (0x24C) -#define DSP2_MIDDLE_B_BCOEFF_W DSP2_MIDDLE_B_BCOEFF_W -#define DSP2_MIDDLE_B_BCOEFF_W_POS (0U) -#define DSP2_MIDDLE_B_BCOEFF_W_LEN (13U) -#define DSP2_MIDDLE_B_BCOEFF_W_MSK (((1U << DSP2_MIDDLE_B_BCOEFF_W_LEN) - 1) << DSP2_MIDDLE_B_BCOEFF_W_POS) -#define DSP2_MIDDLE_B_BCOEFF_W_UMSK (~(((1U << DSP2_MIDDLE_B_BCOEFF_W_LEN) - 1) << DSP2_MIDDLE_B_BCOEFF_W_POS)) -#define DSP2_MIDDLE_B_ECOEFF_W DSP2_MIDDLE_B_ECOEFF_W -#define DSP2_MIDDLE_B_ECOEFF_W_POS (16U) -#define DSP2_MIDDLE_B_ECOEFF_W_LEN (13U) -#define DSP2_MIDDLE_B_ECOEFF_W_MSK (((1U << DSP2_MIDDLE_B_ECOEFF_W_LEN) - 1) << DSP2_MIDDLE_B_ECOEFF_W_POS) -#define DSP2_MIDDLE_B_ECOEFF_W_UMSK (~(((1U << DSP2_MIDDLE_B_ECOEFF_W_LEN) - 1) << DSP2_MIDDLE_B_ECOEFF_W_POS)) - -/* 0x250 : LSC_coeff_B_CD */ -#define DSP2_MIDDLE_LSC_COEFF_B_CD_OFFSET (0x250) -#define DSP2_MIDDLE_B_DCOEFF_W DSP2_MIDDLE_B_DCOEFF_W -#define DSP2_MIDDLE_B_DCOEFF_W_POS (0U) -#define DSP2_MIDDLE_B_DCOEFF_W_LEN (23U) -#define DSP2_MIDDLE_B_DCOEFF_W_MSK (((1U << DSP2_MIDDLE_B_DCOEFF_W_LEN) - 1) << DSP2_MIDDLE_B_DCOEFF_W_POS) -#define DSP2_MIDDLE_B_DCOEFF_W_UMSK (~(((1U << DSP2_MIDDLE_B_DCOEFF_W_LEN) - 1) << DSP2_MIDDLE_B_DCOEFF_W_POS)) -#define DSP2_MIDDLE_B_CCOEFF_W DSP2_MIDDLE_B_CCOEFF_W -#define DSP2_MIDDLE_B_CCOEFF_W_POS (24U) -#define DSP2_MIDDLE_B_CCOEFF_W_LEN (8U) -#define DSP2_MIDDLE_B_CCOEFF_W_MSK (((1U << DSP2_MIDDLE_B_CCOEFF_W_LEN) - 1) << DSP2_MIDDLE_B_CCOEFF_W_POS) -#define DSP2_MIDDLE_B_CCOEFF_W_UMSK (~(((1U << DSP2_MIDDLE_B_CCOEFF_W_LEN) - 1) << DSP2_MIDDLE_B_CCOEFF_W_POS)) - -/* 0x254 : LSC_coeff_B_G */ -#define DSP2_MIDDLE_LSC_COEFF_B_G_OFFSET (0x254) -#define DSP2_MIDDLE_B_GCOEFF_W DSP2_MIDDLE_B_GCOEFF_W -#define DSP2_MIDDLE_B_GCOEFF_W_POS (0U) -#define DSP2_MIDDLE_B_GCOEFF_W_LEN (23U) -#define DSP2_MIDDLE_B_GCOEFF_W_MSK (((1U << DSP2_MIDDLE_B_GCOEFF_W_LEN) - 1) << DSP2_MIDDLE_B_GCOEFF_W_POS) -#define DSP2_MIDDLE_B_GCOEFF_W_UMSK (~(((1U << DSP2_MIDDLE_B_GCOEFF_W_LEN) - 1) << DSP2_MIDDLE_B_GCOEFF_W_POS)) - -/* 0x258 : MAX_R_G */ -#define DSP2_MIDDLE_MAX_R_G_OFFSET (0x258) -#define DSP2_MIDDLE_MAXR_W DSP2_MIDDLE_MAXR_W -#define DSP2_MIDDLE_MAXR_W_POS (0U) -#define DSP2_MIDDLE_MAXR_W_LEN (16U) -#define DSP2_MIDDLE_MAXR_W_MSK (((1U << DSP2_MIDDLE_MAXR_W_LEN) - 1) << DSP2_MIDDLE_MAXR_W_POS) -#define DSP2_MIDDLE_MAXR_W_UMSK (~(((1U << DSP2_MIDDLE_MAXR_W_LEN) - 1) << DSP2_MIDDLE_MAXR_W_POS)) -#define DSP2_MIDDLE_MAXG_W DSP2_MIDDLE_MAXG_W -#define DSP2_MIDDLE_MAXG_W_POS (16U) -#define DSP2_MIDDLE_MAXG_W_LEN (16U) -#define DSP2_MIDDLE_MAXG_W_MSK (((1U << DSP2_MIDDLE_MAXG_W_LEN) - 1) << DSP2_MIDDLE_MAXG_W_POS) -#define DSP2_MIDDLE_MAXG_W_UMSK (~(((1U << DSP2_MIDDLE_MAXG_W_LEN) - 1) << DSP2_MIDDLE_MAXG_W_POS)) - -/* 0x25C : MAX_B */ -#define DSP2_MIDDLE_MAX_B_OFFSET (0x25C) -#define DSP2_MIDDLE_MAXB_W DSP2_MIDDLE_MAXB_W -#define DSP2_MIDDLE_MAXB_W_POS (0U) -#define DSP2_MIDDLE_MAXB_W_LEN (16U) -#define DSP2_MIDDLE_MAXB_W_MSK (((1U << DSP2_MIDDLE_MAXB_W_LEN) - 1) << DSP2_MIDDLE_MAXB_W_POS) -#define DSP2_MIDDLE_MAXB_W_UMSK (~(((1U << DSP2_MIDDLE_MAXB_W_LEN) - 1) << DSP2_MIDDLE_MAXB_W_POS)) - -/* 0x260 : defect_setting */ -#define DSP2_MIDDLE_DEFECT_SETTING_OFFSET (0x260) -#define DSP2_MIDDLE_DEFECT_CORRECT_MODE_W DSP2_MIDDLE_DEFECT_CORRECT_MODE_W -#define DSP2_MIDDLE_DEFECT_CORRECT_MODE_W_POS (0U) -#define DSP2_MIDDLE_DEFECT_CORRECT_MODE_W_LEN (3U) -#define DSP2_MIDDLE_DEFECT_CORRECT_MODE_W_MSK (((1U << DSP2_MIDDLE_DEFECT_CORRECT_MODE_W_LEN) - 1) << DSP2_MIDDLE_DEFECT_CORRECT_MODE_W_POS) -#define DSP2_MIDDLE_DEFECT_CORRECT_MODE_W_UMSK (~(((1U << DSP2_MIDDLE_DEFECT_CORRECT_MODE_W_LEN) - 1) << DSP2_MIDDLE_DEFECT_CORRECT_MODE_W_POS)) -#define DSP2_MIDDLE_RESOLUTION_ENHANCE1_W DSP2_MIDDLE_RESOLUTION_ENHANCE1_W -#define DSP2_MIDDLE_RESOLUTION_ENHANCE1_W_POS (8U) -#define DSP2_MIDDLE_RESOLUTION_ENHANCE1_W_LEN (1U) -#define DSP2_MIDDLE_RESOLUTION_ENHANCE1_W_MSK (((1U << DSP2_MIDDLE_RESOLUTION_ENHANCE1_W_LEN) - 1) << DSP2_MIDDLE_RESOLUTION_ENHANCE1_W_POS) -#define DSP2_MIDDLE_RESOLUTION_ENHANCE1_W_UMSK (~(((1U << DSP2_MIDDLE_RESOLUTION_ENHANCE1_W_LEN) - 1) << DSP2_MIDDLE_RESOLUTION_ENHANCE1_W_POS)) -#define DSP2_MIDDLE_RESOLUTION_ENHANCE2_W DSP2_MIDDLE_RESOLUTION_ENHANCE2_W -#define DSP2_MIDDLE_RESOLUTION_ENHANCE2_W_POS (9U) -#define DSP2_MIDDLE_RESOLUTION_ENHANCE2_W_LEN (1U) -#define DSP2_MIDDLE_RESOLUTION_ENHANCE2_W_MSK (((1U << DSP2_MIDDLE_RESOLUTION_ENHANCE2_W_LEN) - 1) << DSP2_MIDDLE_RESOLUTION_ENHANCE2_W_POS) -#define DSP2_MIDDLE_RESOLUTION_ENHANCE2_W_UMSK (~(((1U << DSP2_MIDDLE_RESOLUTION_ENHANCE2_W_LEN) - 1) << DSP2_MIDDLE_RESOLUTION_ENHANCE2_W_POS)) -#define DSP2_MIDDLE_RESOLUTION_ENHANCE3_W DSP2_MIDDLE_RESOLUTION_ENHANCE3_W -#define DSP2_MIDDLE_RESOLUTION_ENHANCE3_W_POS (10U) -#define DSP2_MIDDLE_RESOLUTION_ENHANCE3_W_LEN (1U) -#define DSP2_MIDDLE_RESOLUTION_ENHANCE3_W_MSK (((1U << DSP2_MIDDLE_RESOLUTION_ENHANCE3_W_LEN) - 1) << DSP2_MIDDLE_RESOLUTION_ENHANCE3_W_POS) -#define DSP2_MIDDLE_RESOLUTION_ENHANCE3_W_UMSK (~(((1U << DSP2_MIDDLE_RESOLUTION_ENHANCE3_W_LEN) - 1) << DSP2_MIDDLE_RESOLUTION_ENHANCE3_W_POS)) -#define DSP2_MIDDLE_DEFECT_ADDRESS_W DSP2_MIDDLE_DEFECT_ADDRESS_W -#define DSP2_MIDDLE_DEFECT_ADDRESS_W_POS (16U) -#define DSP2_MIDDLE_DEFECT_ADDRESS_W_LEN (8U) -#define DSP2_MIDDLE_DEFECT_ADDRESS_W_MSK (((1U << DSP2_MIDDLE_DEFECT_ADDRESS_W_LEN) - 1) << DSP2_MIDDLE_DEFECT_ADDRESS_W_POS) -#define DSP2_MIDDLE_DEFECT_ADDRESS_W_UMSK (~(((1U << DSP2_MIDDLE_DEFECT_ADDRESS_W_LEN) - 1) << DSP2_MIDDLE_DEFECT_ADDRESS_W_POS)) - -/* 0x264 : defect_position */ -#define DSP2_MIDDLE_DEFECT_POSITION_OFFSET (0x264) -#define DSP2_MIDDLE_X_POSITION_W DSP2_MIDDLE_X_POSITION_W -#define DSP2_MIDDLE_X_POSITION_W_POS (0U) -#define DSP2_MIDDLE_X_POSITION_W_LEN (16U) -#define DSP2_MIDDLE_X_POSITION_W_MSK (((1U << DSP2_MIDDLE_X_POSITION_W_LEN) - 1) << DSP2_MIDDLE_X_POSITION_W_POS) -#define DSP2_MIDDLE_X_POSITION_W_UMSK (~(((1U << DSP2_MIDDLE_X_POSITION_W_LEN) - 1) << DSP2_MIDDLE_X_POSITION_W_POS)) -#define DSP2_MIDDLE_Y_POSITION_W DSP2_MIDDLE_Y_POSITION_W -#define DSP2_MIDDLE_Y_POSITION_W_POS (16U) -#define DSP2_MIDDLE_Y_POSITION_W_LEN (16U) -#define DSP2_MIDDLE_Y_POSITION_W_MSK (((1U << DSP2_MIDDLE_Y_POSITION_W_LEN) - 1) << DSP2_MIDDLE_Y_POSITION_W_POS) -#define DSP2_MIDDLE_Y_POSITION_W_UMSK (~(((1U << DSP2_MIDDLE_Y_POSITION_W_LEN) - 1) << DSP2_MIDDLE_Y_POSITION_W_POS)) - -/* 0x268 : defect_th_A */ -#define DSP2_MIDDLE_DEFECT_TH_A_OFFSET (0x268) -#define DSP2_MIDDLE_DEFECT_TH1_W DSP2_MIDDLE_DEFECT_TH1_W -#define DSP2_MIDDLE_DEFECT_TH1_W_POS (0U) -#define DSP2_MIDDLE_DEFECT_TH1_W_LEN (8U) -#define DSP2_MIDDLE_DEFECT_TH1_W_MSK (((1U << DSP2_MIDDLE_DEFECT_TH1_W_LEN) - 1) << DSP2_MIDDLE_DEFECT_TH1_W_POS) -#define DSP2_MIDDLE_DEFECT_TH1_W_UMSK (~(((1U << DSP2_MIDDLE_DEFECT_TH1_W_LEN) - 1) << DSP2_MIDDLE_DEFECT_TH1_W_POS)) -#define DSP2_MIDDLE_DEFECT_TH2_W DSP2_MIDDLE_DEFECT_TH2_W -#define DSP2_MIDDLE_DEFECT_TH2_W_POS (8U) -#define DSP2_MIDDLE_DEFECT_TH2_W_LEN (8U) -#define DSP2_MIDDLE_DEFECT_TH2_W_MSK (((1U << DSP2_MIDDLE_DEFECT_TH2_W_LEN) - 1) << DSP2_MIDDLE_DEFECT_TH2_W_POS) -#define DSP2_MIDDLE_DEFECT_TH2_W_UMSK (~(((1U << DSP2_MIDDLE_DEFECT_TH2_W_LEN) - 1) << DSP2_MIDDLE_DEFECT_TH2_W_POS)) -#define DSP2_MIDDLE_DEFECT_TH3_W DSP2_MIDDLE_DEFECT_TH3_W -#define DSP2_MIDDLE_DEFECT_TH3_W_POS (16U) -#define DSP2_MIDDLE_DEFECT_TH3_W_LEN (8U) -#define DSP2_MIDDLE_DEFECT_TH3_W_MSK (((1U << DSP2_MIDDLE_DEFECT_TH3_W_LEN) - 1) << DSP2_MIDDLE_DEFECT_TH3_W_POS) -#define DSP2_MIDDLE_DEFECT_TH3_W_UMSK (~(((1U << DSP2_MIDDLE_DEFECT_TH3_W_LEN) - 1) << DSP2_MIDDLE_DEFECT_TH3_W_POS)) -#define DSP2_MIDDLE_DEFECT_TH4_W DSP2_MIDDLE_DEFECT_TH4_W -#define DSP2_MIDDLE_DEFECT_TH4_W_POS (24U) -#define DSP2_MIDDLE_DEFECT_TH4_W_LEN (8U) -#define DSP2_MIDDLE_DEFECT_TH4_W_MSK (((1U << DSP2_MIDDLE_DEFECT_TH4_W_LEN) - 1) << DSP2_MIDDLE_DEFECT_TH4_W_POS) -#define DSP2_MIDDLE_DEFECT_TH4_W_UMSK (~(((1U << DSP2_MIDDLE_DEFECT_TH4_W_LEN) - 1) << DSP2_MIDDLE_DEFECT_TH4_W_POS)) - -/* 0x26C : defect_th_B */ -#define DSP2_MIDDLE_DEFECT_TH_B_OFFSET (0x26C) -#define DSP2_MIDDLE_DEFECT_TH5_W DSP2_MIDDLE_DEFECT_TH5_W -#define DSP2_MIDDLE_DEFECT_TH5_W_POS (0U) -#define DSP2_MIDDLE_DEFECT_TH5_W_LEN (8U) -#define DSP2_MIDDLE_DEFECT_TH5_W_MSK (((1U << DSP2_MIDDLE_DEFECT_TH5_W_LEN) - 1) << DSP2_MIDDLE_DEFECT_TH5_W_POS) -#define DSP2_MIDDLE_DEFECT_TH5_W_UMSK (~(((1U << DSP2_MIDDLE_DEFECT_TH5_W_LEN) - 1) << DSP2_MIDDLE_DEFECT_TH5_W_POS)) - -/* 0x270 : awb_setting */ -#define DSP2_MIDDLE_AWB_SETTING_OFFSET (0x270) -#define DSP2_MIDDLE_AWB_SWITCH_BANK_EN_W DSP2_MIDDLE_AWB_SWITCH_BANK_EN_W -#define DSP2_MIDDLE_AWB_SWITCH_BANK_EN_W_POS (0U) -#define DSP2_MIDDLE_AWB_SWITCH_BANK_EN_W_LEN (1U) -#define DSP2_MIDDLE_AWB_SWITCH_BANK_EN_W_MSK (((1U << DSP2_MIDDLE_AWB_SWITCH_BANK_EN_W_LEN) - 1) << DSP2_MIDDLE_AWB_SWITCH_BANK_EN_W_POS) -#define DSP2_MIDDLE_AWB_SWITCH_BANK_EN_W_UMSK (~(((1U << DSP2_MIDDLE_AWB_SWITCH_BANK_EN_W_LEN) - 1) << DSP2_MIDDLE_AWB_SWITCH_BANK_EN_W_POS)) -#define DSP2_MIDDLE_NEW_AWB_STA_ENABLE_W DSP2_MIDDLE_NEW_AWB_STA_ENABLE_W -#define DSP2_MIDDLE_NEW_AWB_STA_ENABLE_W_POS (1U) -#define DSP2_MIDDLE_NEW_AWB_STA_ENABLE_W_LEN (1U) -#define DSP2_MIDDLE_NEW_AWB_STA_ENABLE_W_MSK (((1U << DSP2_MIDDLE_NEW_AWB_STA_ENABLE_W_LEN) - 1) << DSP2_MIDDLE_NEW_AWB_STA_ENABLE_W_POS) -#define DSP2_MIDDLE_NEW_AWB_STA_ENABLE_W_UMSK (~(((1U << DSP2_MIDDLE_NEW_AWB_STA_ENABLE_W_LEN) - 1) << DSP2_MIDDLE_NEW_AWB_STA_ENABLE_W_POS)) -#define DSP2_MIDDLE_BL_AWB_GAIN_SEL_W DSP2_MIDDLE_BL_AWB_GAIN_SEL_W -#define DSP2_MIDDLE_BL_AWB_GAIN_SEL_W_POS (2U) -#define DSP2_MIDDLE_BL_AWB_GAIN_SEL_W_LEN (1U) -#define DSP2_MIDDLE_BL_AWB_GAIN_SEL_W_MSK (((1U << DSP2_MIDDLE_BL_AWB_GAIN_SEL_W_LEN) - 1) << DSP2_MIDDLE_BL_AWB_GAIN_SEL_W_POS) -#define DSP2_MIDDLE_BL_AWB_GAIN_SEL_W_UMSK (~(((1U << DSP2_MIDDLE_BL_AWB_GAIN_SEL_W_LEN) - 1) << DSP2_MIDDLE_BL_AWB_GAIN_SEL_W_POS)) -#define DSP2_MIDDLE_BL_DIGITAL_GAIN_SEL_W DSP2_MIDDLE_BL_DIGITAL_GAIN_SEL_W -#define DSP2_MIDDLE_BL_DIGITAL_GAIN_SEL_W_POS (3U) -#define DSP2_MIDDLE_BL_DIGITAL_GAIN_SEL_W_LEN (1U) -#define DSP2_MIDDLE_BL_DIGITAL_GAIN_SEL_W_MSK (((1U << DSP2_MIDDLE_BL_DIGITAL_GAIN_SEL_W_LEN) - 1) << DSP2_MIDDLE_BL_DIGITAL_GAIN_SEL_W_POS) -#define DSP2_MIDDLE_BL_DIGITAL_GAIN_SEL_W_UMSK (~(((1U << DSP2_MIDDLE_BL_DIGITAL_GAIN_SEL_W_LEN) - 1) << DSP2_MIDDLE_BL_DIGITAL_GAIN_SEL_W_POS)) -#define DSP2_MIDDLE_GRID_CNT_WITHIN_THRE_R DSP2_MIDDLE_GRID_CNT_WITHIN_THRE_R -#define DSP2_MIDDLE_GRID_CNT_WITHIN_THRE_R_POS (16U) -#define DSP2_MIDDLE_GRID_CNT_WITHIN_THRE_R_LEN (11U) -#define DSP2_MIDDLE_GRID_CNT_WITHIN_THRE_R_MSK (((1U << DSP2_MIDDLE_GRID_CNT_WITHIN_THRE_R_LEN) - 1) << DSP2_MIDDLE_GRID_CNT_WITHIN_THRE_R_POS) -#define DSP2_MIDDLE_GRID_CNT_WITHIN_THRE_R_UMSK (~(((1U << DSP2_MIDDLE_GRID_CNT_WITHIN_THRE_R_LEN) - 1) << DSP2_MIDDLE_GRID_CNT_WITHIN_THRE_R_POS)) - -/* 0x274 : awb_roi_x */ -#define DSP2_MIDDLE_AWB_ROI_X_OFFSET (0x274) -#define DSP2_MIDDLE_AWB_ROI_START_X_W DSP2_MIDDLE_AWB_ROI_START_X_W -#define DSP2_MIDDLE_AWB_ROI_START_X_W_POS (0U) -#define DSP2_MIDDLE_AWB_ROI_START_X_W_LEN (11U) -#define DSP2_MIDDLE_AWB_ROI_START_X_W_MSK (((1U << DSP2_MIDDLE_AWB_ROI_START_X_W_LEN) - 1) << DSP2_MIDDLE_AWB_ROI_START_X_W_POS) -#define DSP2_MIDDLE_AWB_ROI_START_X_W_UMSK (~(((1U << DSP2_MIDDLE_AWB_ROI_START_X_W_LEN) - 1) << DSP2_MIDDLE_AWB_ROI_START_X_W_POS)) -#define DSP2_MIDDLE_AWB_ROI_WIDTH_W DSP2_MIDDLE_AWB_ROI_WIDTH_W -#define DSP2_MIDDLE_AWB_ROI_WIDTH_W_POS (16U) -#define DSP2_MIDDLE_AWB_ROI_WIDTH_W_LEN (11U) -#define DSP2_MIDDLE_AWB_ROI_WIDTH_W_MSK (((1U << DSP2_MIDDLE_AWB_ROI_WIDTH_W_LEN) - 1) << DSP2_MIDDLE_AWB_ROI_WIDTH_W_POS) -#define DSP2_MIDDLE_AWB_ROI_WIDTH_W_UMSK (~(((1U << DSP2_MIDDLE_AWB_ROI_WIDTH_W_LEN) - 1) << DSP2_MIDDLE_AWB_ROI_WIDTH_W_POS)) - -/* 0x278 : awb_roi_y */ -#define DSP2_MIDDLE_AWB_ROI_Y_OFFSET (0x278) -#define DSP2_MIDDLE_AWB_ROI_START_Y_W DSP2_MIDDLE_AWB_ROI_START_Y_W -#define DSP2_MIDDLE_AWB_ROI_START_Y_W_POS (0U) -#define DSP2_MIDDLE_AWB_ROI_START_Y_W_LEN (11U) -#define DSP2_MIDDLE_AWB_ROI_START_Y_W_MSK (((1U << DSP2_MIDDLE_AWB_ROI_START_Y_W_LEN) - 1) << DSP2_MIDDLE_AWB_ROI_START_Y_W_POS) -#define DSP2_MIDDLE_AWB_ROI_START_Y_W_UMSK (~(((1U << DSP2_MIDDLE_AWB_ROI_START_Y_W_LEN) - 1) << DSP2_MIDDLE_AWB_ROI_START_Y_W_POS)) -#define DSP2_MIDDLE_AWB_ROI_HEIGHT_W DSP2_MIDDLE_AWB_ROI_HEIGHT_W -#define DSP2_MIDDLE_AWB_ROI_HEIGHT_W_POS (16U) -#define DSP2_MIDDLE_AWB_ROI_HEIGHT_W_LEN (11U) -#define DSP2_MIDDLE_AWB_ROI_HEIGHT_W_MSK (((1U << DSP2_MIDDLE_AWB_ROI_HEIGHT_W_LEN) - 1) << DSP2_MIDDLE_AWB_ROI_HEIGHT_W_POS) -#define DSP2_MIDDLE_AWB_ROI_HEIGHT_W_UMSK (~(((1U << DSP2_MIDDLE_AWB_ROI_HEIGHT_W_LEN) - 1) << DSP2_MIDDLE_AWB_ROI_HEIGHT_W_POS)) - -/* 0x27C : awb_image_size */ -#define DSP2_MIDDLE_AWB_IMAGE_SIZE_OFFSET (0x27C) -#define DSP2_MIDDLE_AWB_IMAGE_WIDTH_W DSP2_MIDDLE_AWB_IMAGE_WIDTH_W -#define DSP2_MIDDLE_AWB_IMAGE_WIDTH_W_POS (0U) -#define DSP2_MIDDLE_AWB_IMAGE_WIDTH_W_LEN (11U) -#define DSP2_MIDDLE_AWB_IMAGE_WIDTH_W_MSK (((1U << DSP2_MIDDLE_AWB_IMAGE_WIDTH_W_LEN) - 1) << DSP2_MIDDLE_AWB_IMAGE_WIDTH_W_POS) -#define DSP2_MIDDLE_AWB_IMAGE_WIDTH_W_UMSK (~(((1U << DSP2_MIDDLE_AWB_IMAGE_WIDTH_W_LEN) - 1) << DSP2_MIDDLE_AWB_IMAGE_WIDTH_W_POS)) -#define DSP2_MIDDLE_AWB_IMAGE_HEIGHT_W DSP2_MIDDLE_AWB_IMAGE_HEIGHT_W -#define DSP2_MIDDLE_AWB_IMAGE_HEIGHT_W_POS (16U) -#define DSP2_MIDDLE_AWB_IMAGE_HEIGHT_W_LEN (11U) -#define DSP2_MIDDLE_AWB_IMAGE_HEIGHT_W_MSK (((1U << DSP2_MIDDLE_AWB_IMAGE_HEIGHT_W_LEN) - 1) << DSP2_MIDDLE_AWB_IMAGE_HEIGHT_W_POS) -#define DSP2_MIDDLE_AWB_IMAGE_HEIGHT_W_UMSK (~(((1U << DSP2_MIDDLE_AWB_IMAGE_HEIGHT_W_LEN) - 1) << DSP2_MIDDLE_AWB_IMAGE_HEIGHT_W_POS)) - -/* 0x280 : awb_grid_size */ -#define DSP2_MIDDLE_AWB_GRID_SIZE_OFFSET (0x280) -#define DSP2_MIDDLE_AWB_GRID_WIDTH_W DSP2_MIDDLE_AWB_GRID_WIDTH_W -#define DSP2_MIDDLE_AWB_GRID_WIDTH_W_POS (0U) -#define DSP2_MIDDLE_AWB_GRID_WIDTH_W_LEN (8U) -#define DSP2_MIDDLE_AWB_GRID_WIDTH_W_MSK (((1U << DSP2_MIDDLE_AWB_GRID_WIDTH_W_LEN) - 1) << DSP2_MIDDLE_AWB_GRID_WIDTH_W_POS) -#define DSP2_MIDDLE_AWB_GRID_WIDTH_W_UMSK (~(((1U << DSP2_MIDDLE_AWB_GRID_WIDTH_W_LEN) - 1) << DSP2_MIDDLE_AWB_GRID_WIDTH_W_POS)) -#define DSP2_MIDDLE_AWB_GRID_HEIGHT_W DSP2_MIDDLE_AWB_GRID_HEIGHT_W -#define DSP2_MIDDLE_AWB_GRID_HEIGHT_W_POS (8U) -#define DSP2_MIDDLE_AWB_GRID_HEIGHT_W_LEN (8U) -#define DSP2_MIDDLE_AWB_GRID_HEIGHT_W_MSK (((1U << DSP2_MIDDLE_AWB_GRID_HEIGHT_W_LEN) - 1) << DSP2_MIDDLE_AWB_GRID_HEIGHT_W_POS) -#define DSP2_MIDDLE_AWB_GRID_HEIGHT_W_UMSK (~(((1U << DSP2_MIDDLE_AWB_GRID_HEIGHT_W_LEN) - 1) << DSP2_MIDDLE_AWB_GRID_HEIGHT_W_POS)) -#define DSP2_MIDDLE_AWB_GRID_X_MAX_W DSP2_MIDDLE_AWB_GRID_X_MAX_W -#define DSP2_MIDDLE_AWB_GRID_X_MAX_W_POS (16U) -#define DSP2_MIDDLE_AWB_GRID_X_MAX_W_LEN (6U) -#define DSP2_MIDDLE_AWB_GRID_X_MAX_W_MSK (((1U << DSP2_MIDDLE_AWB_GRID_X_MAX_W_LEN) - 1) << DSP2_MIDDLE_AWB_GRID_X_MAX_W_POS) -#define DSP2_MIDDLE_AWB_GRID_X_MAX_W_UMSK (~(((1U << DSP2_MIDDLE_AWB_GRID_X_MAX_W_LEN) - 1) << DSP2_MIDDLE_AWB_GRID_X_MAX_W_POS)) -#define DSP2_MIDDLE_AWB_GRID_Y_MAX_W DSP2_MIDDLE_AWB_GRID_Y_MAX_W -#define DSP2_MIDDLE_AWB_GRID_Y_MAX_W_POS (24U) -#define DSP2_MIDDLE_AWB_GRID_Y_MAX_W_LEN (6U) -#define DSP2_MIDDLE_AWB_GRID_Y_MAX_W_MSK (((1U << DSP2_MIDDLE_AWB_GRID_Y_MAX_W_LEN) - 1) << DSP2_MIDDLE_AWB_GRID_Y_MAX_W_POS) -#define DSP2_MIDDLE_AWB_GRID_Y_MAX_W_UMSK (~(((1U << DSP2_MIDDLE_AWB_GRID_Y_MAX_W_LEN) - 1) << DSP2_MIDDLE_AWB_GRID_Y_MAX_W_POS)) - -/* 0x284 : awb_r_thre */ -#define DSP2_MIDDLE_AWB_R_THRE_OFFSET (0x284) -#define DSP2_MIDDLE_AWB_R_MAX_THR_W DSP2_MIDDLE_AWB_R_MAX_THR_W -#define DSP2_MIDDLE_AWB_R_MAX_THR_W_POS (0U) -#define DSP2_MIDDLE_AWB_R_MAX_THR_W_LEN (12U) -#define DSP2_MIDDLE_AWB_R_MAX_THR_W_MSK (((1U << DSP2_MIDDLE_AWB_R_MAX_THR_W_LEN) - 1) << DSP2_MIDDLE_AWB_R_MAX_THR_W_POS) -#define DSP2_MIDDLE_AWB_R_MAX_THR_W_UMSK (~(((1U << DSP2_MIDDLE_AWB_R_MAX_THR_W_LEN) - 1) << DSP2_MIDDLE_AWB_R_MAX_THR_W_POS)) -#define DSP2_MIDDLE_AWB_R_MIN_THR_W DSP2_MIDDLE_AWB_R_MIN_THR_W -#define DSP2_MIDDLE_AWB_R_MIN_THR_W_POS (16U) -#define DSP2_MIDDLE_AWB_R_MIN_THR_W_LEN (12U) -#define DSP2_MIDDLE_AWB_R_MIN_THR_W_MSK (((1U << DSP2_MIDDLE_AWB_R_MIN_THR_W_LEN) - 1) << DSP2_MIDDLE_AWB_R_MIN_THR_W_POS) -#define DSP2_MIDDLE_AWB_R_MIN_THR_W_UMSK (~(((1U << DSP2_MIDDLE_AWB_R_MIN_THR_W_LEN) - 1) << DSP2_MIDDLE_AWB_R_MIN_THR_W_POS)) - -/* 0x288 : awb_g_thre */ -#define DSP2_MIDDLE_AWB_G_THRE_OFFSET (0x288) -#define DSP2_MIDDLE_AWB_G_MAX_THR_W DSP2_MIDDLE_AWB_G_MAX_THR_W -#define DSP2_MIDDLE_AWB_G_MAX_THR_W_POS (0U) -#define DSP2_MIDDLE_AWB_G_MAX_THR_W_LEN (12U) -#define DSP2_MIDDLE_AWB_G_MAX_THR_W_MSK (((1U << DSP2_MIDDLE_AWB_G_MAX_THR_W_LEN) - 1) << DSP2_MIDDLE_AWB_G_MAX_THR_W_POS) -#define DSP2_MIDDLE_AWB_G_MAX_THR_W_UMSK (~(((1U << DSP2_MIDDLE_AWB_G_MAX_THR_W_LEN) - 1) << DSP2_MIDDLE_AWB_G_MAX_THR_W_POS)) -#define DSP2_MIDDLE_AWB_G_MIN_THR_W DSP2_MIDDLE_AWB_G_MIN_THR_W -#define DSP2_MIDDLE_AWB_G_MIN_THR_W_POS (16U) -#define DSP2_MIDDLE_AWB_G_MIN_THR_W_LEN (12U) -#define DSP2_MIDDLE_AWB_G_MIN_THR_W_MSK (((1U << DSP2_MIDDLE_AWB_G_MIN_THR_W_LEN) - 1) << DSP2_MIDDLE_AWB_G_MIN_THR_W_POS) -#define DSP2_MIDDLE_AWB_G_MIN_THR_W_UMSK (~(((1U << DSP2_MIDDLE_AWB_G_MIN_THR_W_LEN) - 1) << DSP2_MIDDLE_AWB_G_MIN_THR_W_POS)) - -/* 0x28C : awb_b_thre */ -#define DSP2_MIDDLE_AWB_B_THRE_OFFSET (0x28C) -#define DSP2_MIDDLE_AWB_B_MAX_THR_W DSP2_MIDDLE_AWB_B_MAX_THR_W -#define DSP2_MIDDLE_AWB_B_MAX_THR_W_POS (0U) -#define DSP2_MIDDLE_AWB_B_MAX_THR_W_LEN (12U) -#define DSP2_MIDDLE_AWB_B_MAX_THR_W_MSK (((1U << DSP2_MIDDLE_AWB_B_MAX_THR_W_LEN) - 1) << DSP2_MIDDLE_AWB_B_MAX_THR_W_POS) -#define DSP2_MIDDLE_AWB_B_MAX_THR_W_UMSK (~(((1U << DSP2_MIDDLE_AWB_B_MAX_THR_W_LEN) - 1) << DSP2_MIDDLE_AWB_B_MAX_THR_W_POS)) -#define DSP2_MIDDLE_AWB_B_MIN_THR_W DSP2_MIDDLE_AWB_B_MIN_THR_W -#define DSP2_MIDDLE_AWB_B_MIN_THR_W_POS (16U) -#define DSP2_MIDDLE_AWB_B_MIN_THR_W_LEN (12U) -#define DSP2_MIDDLE_AWB_B_MIN_THR_W_MSK (((1U << DSP2_MIDDLE_AWB_B_MIN_THR_W_LEN) - 1) << DSP2_MIDDLE_AWB_B_MIN_THR_W_POS) -#define DSP2_MIDDLE_AWB_B_MIN_THR_W_UMSK (~(((1U << DSP2_MIDDLE_AWB_B_MIN_THR_W_LEN) - 1) << DSP2_MIDDLE_AWB_B_MIN_THR_W_POS)) - -/* 0x290 : awb_rgr_gain */ -#define DSP2_MIDDLE_AWB_RGR_GAIN_OFFSET (0x290) -#define DSP2_MIDDLE_AWB_GR_GAIN_PRE DSP2_MIDDLE_AWB_GR_GAIN_PRE -#define DSP2_MIDDLE_AWB_GR_GAIN_PRE_POS (0U) -#define DSP2_MIDDLE_AWB_GR_GAIN_PRE_LEN (16U) -#define DSP2_MIDDLE_AWB_GR_GAIN_PRE_MSK (((1U << DSP2_MIDDLE_AWB_GR_GAIN_PRE_LEN) - 1) << DSP2_MIDDLE_AWB_GR_GAIN_PRE_POS) -#define DSP2_MIDDLE_AWB_GR_GAIN_PRE_UMSK (~(((1U << DSP2_MIDDLE_AWB_GR_GAIN_PRE_LEN) - 1) << DSP2_MIDDLE_AWB_GR_GAIN_PRE_POS)) -#define DSP2_MIDDLE_AWB_R_GAIN_PRE DSP2_MIDDLE_AWB_R_GAIN_PRE -#define DSP2_MIDDLE_AWB_R_GAIN_PRE_POS (16U) -#define DSP2_MIDDLE_AWB_R_GAIN_PRE_LEN (16U) -#define DSP2_MIDDLE_AWB_R_GAIN_PRE_MSK (((1U << DSP2_MIDDLE_AWB_R_GAIN_PRE_LEN) - 1) << DSP2_MIDDLE_AWB_R_GAIN_PRE_POS) -#define DSP2_MIDDLE_AWB_R_GAIN_PRE_UMSK (~(((1U << DSP2_MIDDLE_AWB_R_GAIN_PRE_LEN) - 1) << DSP2_MIDDLE_AWB_R_GAIN_PRE_POS)) - -/* 0x294 : awb_bgb_gain */ -#define DSP2_MIDDLE_AWB_BGB_GAIN_OFFSET (0x294) -#define DSP2_MIDDLE_AWB_GB_GAIN_PRE DSP2_MIDDLE_AWB_GB_GAIN_PRE -#define DSP2_MIDDLE_AWB_GB_GAIN_PRE_POS (0U) -#define DSP2_MIDDLE_AWB_GB_GAIN_PRE_LEN (16U) -#define DSP2_MIDDLE_AWB_GB_GAIN_PRE_MSK (((1U << DSP2_MIDDLE_AWB_GB_GAIN_PRE_LEN) - 1) << DSP2_MIDDLE_AWB_GB_GAIN_PRE_POS) -#define DSP2_MIDDLE_AWB_GB_GAIN_PRE_UMSK (~(((1U << DSP2_MIDDLE_AWB_GB_GAIN_PRE_LEN) - 1) << DSP2_MIDDLE_AWB_GB_GAIN_PRE_POS)) -#define DSP2_MIDDLE_AWB_B_GAIN_PRE DSP2_MIDDLE_AWB_B_GAIN_PRE -#define DSP2_MIDDLE_AWB_B_GAIN_PRE_POS (16U) -#define DSP2_MIDDLE_AWB_B_GAIN_PRE_LEN (16U) -#define DSP2_MIDDLE_AWB_B_GAIN_PRE_MSK (((1U << DSP2_MIDDLE_AWB_B_GAIN_PRE_LEN) - 1) << DSP2_MIDDLE_AWB_B_GAIN_PRE_POS) -#define DSP2_MIDDLE_AWB_B_GAIN_PRE_UMSK (~(((1U << DSP2_MIDDLE_AWB_B_GAIN_PRE_LEN) - 1) << DSP2_MIDDLE_AWB_B_GAIN_PRE_POS)) - -/* 0x298 : awb_rgr_offset */ -#define DSP2_MIDDLE_AWB_RGR_OFFSET_OFFSET (0x298) -#define DSP2_MIDDLE_AWB_GR_OFFSET_PRE DSP2_MIDDLE_AWB_GR_OFFSET_PRE -#define DSP2_MIDDLE_AWB_GR_OFFSET_PRE_POS (0U) -#define DSP2_MIDDLE_AWB_GR_OFFSET_PRE_LEN (12U) -#define DSP2_MIDDLE_AWB_GR_OFFSET_PRE_MSK (((1U << DSP2_MIDDLE_AWB_GR_OFFSET_PRE_LEN) - 1) << DSP2_MIDDLE_AWB_GR_OFFSET_PRE_POS) -#define DSP2_MIDDLE_AWB_GR_OFFSET_PRE_UMSK (~(((1U << DSP2_MIDDLE_AWB_GR_OFFSET_PRE_LEN) - 1) << DSP2_MIDDLE_AWB_GR_OFFSET_PRE_POS)) -#define DSP2_MIDDLE_AWB_R_OFFSET_PRE DSP2_MIDDLE_AWB_R_OFFSET_PRE -#define DSP2_MIDDLE_AWB_R_OFFSET_PRE_POS (16U) -#define DSP2_MIDDLE_AWB_R_OFFSET_PRE_LEN (12U) -#define DSP2_MIDDLE_AWB_R_OFFSET_PRE_MSK (((1U << DSP2_MIDDLE_AWB_R_OFFSET_PRE_LEN) - 1) << DSP2_MIDDLE_AWB_R_OFFSET_PRE_POS) -#define DSP2_MIDDLE_AWB_R_OFFSET_PRE_UMSK (~(((1U << DSP2_MIDDLE_AWB_R_OFFSET_PRE_LEN) - 1) << DSP2_MIDDLE_AWB_R_OFFSET_PRE_POS)) - -/* 0x29C : awb_bgb_offset */ -#define DSP2_MIDDLE_AWB_BGB_OFFSET_OFFSET (0x29C) -#define DSP2_MIDDLE_AWB_GB_OFFSET_PRE DSP2_MIDDLE_AWB_GB_OFFSET_PRE -#define DSP2_MIDDLE_AWB_GB_OFFSET_PRE_POS (0U) -#define DSP2_MIDDLE_AWB_GB_OFFSET_PRE_LEN (12U) -#define DSP2_MIDDLE_AWB_GB_OFFSET_PRE_MSK (((1U << DSP2_MIDDLE_AWB_GB_OFFSET_PRE_LEN) - 1) << DSP2_MIDDLE_AWB_GB_OFFSET_PRE_POS) -#define DSP2_MIDDLE_AWB_GB_OFFSET_PRE_UMSK (~(((1U << DSP2_MIDDLE_AWB_GB_OFFSET_PRE_LEN) - 1) << DSP2_MIDDLE_AWB_GB_OFFSET_PRE_POS)) -#define DSP2_MIDDLE_AWB_B_OFFSET_PRE DSP2_MIDDLE_AWB_B_OFFSET_PRE -#define DSP2_MIDDLE_AWB_B_OFFSET_PRE_POS (16U) -#define DSP2_MIDDLE_AWB_B_OFFSET_PRE_LEN (12U) -#define DSP2_MIDDLE_AWB_B_OFFSET_PRE_MSK (((1U << DSP2_MIDDLE_AWB_B_OFFSET_PRE_LEN) - 1) << DSP2_MIDDLE_AWB_B_OFFSET_PRE_POS) -#define DSP2_MIDDLE_AWB_B_OFFSET_PRE_UMSK (~(((1U << DSP2_MIDDLE_AWB_B_OFFSET_PRE_LEN) - 1) << DSP2_MIDDLE_AWB_B_OFFSET_PRE_POS)) - -/* 0x2A0 : cfa_int_1 */ -#define DSP2_MIDDLE_CFA_INT_1_OFFSET (0x2A0) -#define DSP2_MIDDLE_REG_CFA_FRINGE_ON_W DSP2_MIDDLE_REG_CFA_FRINGE_ON_W -#define DSP2_MIDDLE_REG_CFA_FRINGE_ON_W_POS (0U) -#define DSP2_MIDDLE_REG_CFA_FRINGE_ON_W_LEN (1U) -#define DSP2_MIDDLE_REG_CFA_FRINGE_ON_W_MSK (((1U << DSP2_MIDDLE_REG_CFA_FRINGE_ON_W_LEN) - 1) << DSP2_MIDDLE_REG_CFA_FRINGE_ON_W_POS) -#define DSP2_MIDDLE_REG_CFA_FRINGE_ON_W_UMSK (~(((1U << DSP2_MIDDLE_REG_CFA_FRINGE_ON_W_LEN) - 1) << DSP2_MIDDLE_REG_CFA_FRINGE_ON_W_POS)) - -/* 0x2A8 : digital_rgr_gain */ -#define DSP2_MIDDLE_DIGITAL_RGR_GAIN_OFFSET (0x2A8) -#define DSP2_MIDDLE_DIGITAL_GR_GAIN_PRE DSP2_MIDDLE_DIGITAL_GR_GAIN_PRE -#define DSP2_MIDDLE_DIGITAL_GR_GAIN_PRE_POS (0U) -#define DSP2_MIDDLE_DIGITAL_GR_GAIN_PRE_LEN (16U) -#define DSP2_MIDDLE_DIGITAL_GR_GAIN_PRE_MSK (((1U << DSP2_MIDDLE_DIGITAL_GR_GAIN_PRE_LEN) - 1) << DSP2_MIDDLE_DIGITAL_GR_GAIN_PRE_POS) -#define DSP2_MIDDLE_DIGITAL_GR_GAIN_PRE_UMSK (~(((1U << DSP2_MIDDLE_DIGITAL_GR_GAIN_PRE_LEN) - 1) << DSP2_MIDDLE_DIGITAL_GR_GAIN_PRE_POS)) -#define DSP2_MIDDLE_DIGITAL_R_GAIN_PRE DSP2_MIDDLE_DIGITAL_R_GAIN_PRE -#define DSP2_MIDDLE_DIGITAL_R_GAIN_PRE_POS (16U) -#define DSP2_MIDDLE_DIGITAL_R_GAIN_PRE_LEN (16U) -#define DSP2_MIDDLE_DIGITAL_R_GAIN_PRE_MSK (((1U << DSP2_MIDDLE_DIGITAL_R_GAIN_PRE_LEN) - 1) << DSP2_MIDDLE_DIGITAL_R_GAIN_PRE_POS) -#define DSP2_MIDDLE_DIGITAL_R_GAIN_PRE_UMSK (~(((1U << DSP2_MIDDLE_DIGITAL_R_GAIN_PRE_LEN) - 1) << DSP2_MIDDLE_DIGITAL_R_GAIN_PRE_POS)) - -/* 0x2AC : digital_bgb_gain */ -#define DSP2_MIDDLE_DIGITAL_BGB_GAIN_OFFSET (0x2AC) -#define DSP2_MIDDLE_DIGITAL_GB_GAIN_PRE DSP2_MIDDLE_DIGITAL_GB_GAIN_PRE -#define DSP2_MIDDLE_DIGITAL_GB_GAIN_PRE_POS (0U) -#define DSP2_MIDDLE_DIGITAL_GB_GAIN_PRE_LEN (16U) -#define DSP2_MIDDLE_DIGITAL_GB_GAIN_PRE_MSK (((1U << DSP2_MIDDLE_DIGITAL_GB_GAIN_PRE_LEN) - 1) << DSP2_MIDDLE_DIGITAL_GB_GAIN_PRE_POS) -#define DSP2_MIDDLE_DIGITAL_GB_GAIN_PRE_UMSK (~(((1U << DSP2_MIDDLE_DIGITAL_GB_GAIN_PRE_LEN) - 1) << DSP2_MIDDLE_DIGITAL_GB_GAIN_PRE_POS)) -#define DSP2_MIDDLE_DIGITAL_B_GAIN_PRE DSP2_MIDDLE_DIGITAL_B_GAIN_PRE -#define DSP2_MIDDLE_DIGITAL_B_GAIN_PRE_POS (16U) -#define DSP2_MIDDLE_DIGITAL_B_GAIN_PRE_LEN (16U) -#define DSP2_MIDDLE_DIGITAL_B_GAIN_PRE_MSK (((1U << DSP2_MIDDLE_DIGITAL_B_GAIN_PRE_LEN) - 1) << DSP2_MIDDLE_DIGITAL_B_GAIN_PRE_POS) -#define DSP2_MIDDLE_DIGITAL_B_GAIN_PRE_UMSK (~(((1U << DSP2_MIDDLE_DIGITAL_B_GAIN_PRE_LEN) - 1) << DSP2_MIDDLE_DIGITAL_B_GAIN_PRE_POS)) - -/* 0x2BC : ae_roi_x */ -#define DSP2_MIDDLE_AE_ROI_X_OFFSET (0x2BC) -#define DSP2_MIDDLE_AE_ROI_START_X_PRE DSP2_MIDDLE_AE_ROI_START_X_PRE -#define DSP2_MIDDLE_AE_ROI_START_X_PRE_POS (0U) -#define DSP2_MIDDLE_AE_ROI_START_X_PRE_LEN (11U) -#define DSP2_MIDDLE_AE_ROI_START_X_PRE_MSK (((1U << DSP2_MIDDLE_AE_ROI_START_X_PRE_LEN) - 1) << DSP2_MIDDLE_AE_ROI_START_X_PRE_POS) -#define DSP2_MIDDLE_AE_ROI_START_X_PRE_UMSK (~(((1U << DSP2_MIDDLE_AE_ROI_START_X_PRE_LEN) - 1) << DSP2_MIDDLE_AE_ROI_START_X_PRE_POS)) -#define DSP2_MIDDLE_AE_ROI_WIDTH_PRE DSP2_MIDDLE_AE_ROI_WIDTH_PRE -#define DSP2_MIDDLE_AE_ROI_WIDTH_PRE_POS (16U) -#define DSP2_MIDDLE_AE_ROI_WIDTH_PRE_LEN (11U) -#define DSP2_MIDDLE_AE_ROI_WIDTH_PRE_MSK (((1U << DSP2_MIDDLE_AE_ROI_WIDTH_PRE_LEN) - 1) << DSP2_MIDDLE_AE_ROI_WIDTH_PRE_POS) -#define DSP2_MIDDLE_AE_ROI_WIDTH_PRE_UMSK (~(((1U << DSP2_MIDDLE_AE_ROI_WIDTH_PRE_LEN) - 1) << DSP2_MIDDLE_AE_ROI_WIDTH_PRE_POS)) - -/* 0x2C0 : ae_roi_y */ -#define DSP2_MIDDLE_AE_ROI_Y_OFFSET (0x2C0) -#define DSP2_MIDDLE_AE_ROI_START_Y_PRE DSP2_MIDDLE_AE_ROI_START_Y_PRE -#define DSP2_MIDDLE_AE_ROI_START_Y_PRE_POS (0U) -#define DSP2_MIDDLE_AE_ROI_START_Y_PRE_LEN (11U) -#define DSP2_MIDDLE_AE_ROI_START_Y_PRE_MSK (((1U << DSP2_MIDDLE_AE_ROI_START_Y_PRE_LEN) - 1) << DSP2_MIDDLE_AE_ROI_START_Y_PRE_POS) -#define DSP2_MIDDLE_AE_ROI_START_Y_PRE_UMSK (~(((1U << DSP2_MIDDLE_AE_ROI_START_Y_PRE_LEN) - 1) << DSP2_MIDDLE_AE_ROI_START_Y_PRE_POS)) -#define DSP2_MIDDLE_AE_ROI_HEIGHT_PRE DSP2_MIDDLE_AE_ROI_HEIGHT_PRE -#define DSP2_MIDDLE_AE_ROI_HEIGHT_PRE_POS (16U) -#define DSP2_MIDDLE_AE_ROI_HEIGHT_PRE_LEN (11U) -#define DSP2_MIDDLE_AE_ROI_HEIGHT_PRE_MSK (((1U << DSP2_MIDDLE_AE_ROI_HEIGHT_PRE_LEN) - 1) << DSP2_MIDDLE_AE_ROI_HEIGHT_PRE_POS) -#define DSP2_MIDDLE_AE_ROI_HEIGHT_PRE_UMSK (~(((1U << DSP2_MIDDLE_AE_ROI_HEIGHT_PRE_LEN) - 1) << DSP2_MIDDLE_AE_ROI_HEIGHT_PRE_POS)) - -/* 0x2C4 : ae_image_size */ -#define DSP2_MIDDLE_AE_IMAGE_SIZE_OFFSET (0x2C4) -#define DSP2_MIDDLE_AE_IMAGE_WIDTH_PRE DSP2_MIDDLE_AE_IMAGE_WIDTH_PRE -#define DSP2_MIDDLE_AE_IMAGE_WIDTH_PRE_POS (0U) -#define DSP2_MIDDLE_AE_IMAGE_WIDTH_PRE_LEN (11U) -#define DSP2_MIDDLE_AE_IMAGE_WIDTH_PRE_MSK (((1U << DSP2_MIDDLE_AE_IMAGE_WIDTH_PRE_LEN) - 1) << DSP2_MIDDLE_AE_IMAGE_WIDTH_PRE_POS) -#define DSP2_MIDDLE_AE_IMAGE_WIDTH_PRE_UMSK (~(((1U << DSP2_MIDDLE_AE_IMAGE_WIDTH_PRE_LEN) - 1) << DSP2_MIDDLE_AE_IMAGE_WIDTH_PRE_POS)) -#define DSP2_MIDDLE_AE_IMAGE_HEIGHT_PRE DSP2_MIDDLE_AE_IMAGE_HEIGHT_PRE -#define DSP2_MIDDLE_AE_IMAGE_HEIGHT_PRE_POS (16U) -#define DSP2_MIDDLE_AE_IMAGE_HEIGHT_PRE_LEN (11U) -#define DSP2_MIDDLE_AE_IMAGE_HEIGHT_PRE_MSK (((1U << DSP2_MIDDLE_AE_IMAGE_HEIGHT_PRE_LEN) - 1) << DSP2_MIDDLE_AE_IMAGE_HEIGHT_PRE_POS) -#define DSP2_MIDDLE_AE_IMAGE_HEIGHT_PRE_UMSK (~(((1U << DSP2_MIDDLE_AE_IMAGE_HEIGHT_PRE_LEN) - 1) << DSP2_MIDDLE_AE_IMAGE_HEIGHT_PRE_POS)) - -/* 0x2C8 : ae_grid_size */ -#define DSP2_MIDDLE_AE_GRID_SIZE_OFFSET (0x2C8) -#define DSP2_MIDDLE_AE_GRID_WIDTH_PRE DSP2_MIDDLE_AE_GRID_WIDTH_PRE -#define DSP2_MIDDLE_AE_GRID_WIDTH_PRE_POS (0U) -#define DSP2_MIDDLE_AE_GRID_WIDTH_PRE_LEN (8U) -#define DSP2_MIDDLE_AE_GRID_WIDTH_PRE_MSK (((1U << DSP2_MIDDLE_AE_GRID_WIDTH_PRE_LEN) - 1) << DSP2_MIDDLE_AE_GRID_WIDTH_PRE_POS) -#define DSP2_MIDDLE_AE_GRID_WIDTH_PRE_UMSK (~(((1U << DSP2_MIDDLE_AE_GRID_WIDTH_PRE_LEN) - 1) << DSP2_MIDDLE_AE_GRID_WIDTH_PRE_POS)) -#define DSP2_MIDDLE_AE_GRID_HEIGHT_PRE DSP2_MIDDLE_AE_GRID_HEIGHT_PRE -#define DSP2_MIDDLE_AE_GRID_HEIGHT_PRE_POS (8U) -#define DSP2_MIDDLE_AE_GRID_HEIGHT_PRE_LEN (8U) -#define DSP2_MIDDLE_AE_GRID_HEIGHT_PRE_MSK (((1U << DSP2_MIDDLE_AE_GRID_HEIGHT_PRE_LEN) - 1) << DSP2_MIDDLE_AE_GRID_HEIGHT_PRE_POS) -#define DSP2_MIDDLE_AE_GRID_HEIGHT_PRE_UMSK (~(((1U << DSP2_MIDDLE_AE_GRID_HEIGHT_PRE_LEN) - 1) << DSP2_MIDDLE_AE_GRID_HEIGHT_PRE_POS)) -#define DSP2_MIDDLE_AE_GRID_Y_MAX_PRE DSP2_MIDDLE_AE_GRID_Y_MAX_PRE -#define DSP2_MIDDLE_AE_GRID_Y_MAX_PRE_POS (16U) -#define DSP2_MIDDLE_AE_GRID_Y_MAX_PRE_LEN (4U) -#define DSP2_MIDDLE_AE_GRID_Y_MAX_PRE_MSK (((1U << DSP2_MIDDLE_AE_GRID_Y_MAX_PRE_LEN) - 1) << DSP2_MIDDLE_AE_GRID_Y_MAX_PRE_POS) -#define DSP2_MIDDLE_AE_GRID_Y_MAX_PRE_UMSK (~(((1U << DSP2_MIDDLE_AE_GRID_Y_MAX_PRE_LEN) - 1) << DSP2_MIDDLE_AE_GRID_Y_MAX_PRE_POS)) -#define DSP2_MIDDLE_AE_GRID_X_MAX_PRE DSP2_MIDDLE_AE_GRID_X_MAX_PRE -#define DSP2_MIDDLE_AE_GRID_X_MAX_PRE_POS (20U) -#define DSP2_MIDDLE_AE_GRID_X_MAX_PRE_LEN (4U) -#define DSP2_MIDDLE_AE_GRID_X_MAX_PRE_MSK (((1U << DSP2_MIDDLE_AE_GRID_X_MAX_PRE_LEN) - 1) << DSP2_MIDDLE_AE_GRID_X_MAX_PRE_POS) -#define DSP2_MIDDLE_AE_GRID_X_MAX_PRE_UMSK (~(((1U << DSP2_MIDDLE_AE_GRID_X_MAX_PRE_LEN) - 1) << DSP2_MIDDLE_AE_GRID_X_MAX_PRE_POS)) -#define DSP2_MIDDLE_NEW_AE_STA_ENABLE_W DSP2_MIDDLE_NEW_AE_STA_ENABLE_W -#define DSP2_MIDDLE_NEW_AE_STA_ENABLE_W_POS (24U) -#define DSP2_MIDDLE_NEW_AE_STA_ENABLE_W_LEN (1U) -#define DSP2_MIDDLE_NEW_AE_STA_ENABLE_W_MSK (((1U << DSP2_MIDDLE_NEW_AE_STA_ENABLE_W_LEN) - 1) << DSP2_MIDDLE_NEW_AE_STA_ENABLE_W_POS) -#define DSP2_MIDDLE_NEW_AE_STA_ENABLE_W_UMSK (~(((1U << DSP2_MIDDLE_NEW_AE_STA_ENABLE_W_LEN) - 1) << DSP2_MIDDLE_NEW_AE_STA_ENABLE_W_POS)) -#define DSP2_MIDDLE_AE_SWITCH_BANK_EN_PRE DSP2_MIDDLE_AE_SWITCH_BANK_EN_PRE -#define DSP2_MIDDLE_AE_SWITCH_BANK_EN_PRE_POS (25U) -#define DSP2_MIDDLE_AE_SWITCH_BANK_EN_PRE_LEN (1U) -#define DSP2_MIDDLE_AE_SWITCH_BANK_EN_PRE_MSK (((1U << DSP2_MIDDLE_AE_SWITCH_BANK_EN_PRE_LEN) - 1) << DSP2_MIDDLE_AE_SWITCH_BANK_EN_PRE_POS) -#define DSP2_MIDDLE_AE_SWITCH_BANK_EN_PRE_UMSK (~(((1U << DSP2_MIDDLE_AE_SWITCH_BANK_EN_PRE_LEN) - 1) << DSP2_MIDDLE_AE_SWITCH_BANK_EN_PRE_POS)) -#define DSP2_MIDDLE_AE_HIST_EN_PRE DSP2_MIDDLE_AE_HIST_EN_PRE -#define DSP2_MIDDLE_AE_HIST_EN_PRE_POS (26U) -#define DSP2_MIDDLE_AE_HIST_EN_PRE_LEN (1U) -#define DSP2_MIDDLE_AE_HIST_EN_PRE_MSK (((1U << DSP2_MIDDLE_AE_HIST_EN_PRE_LEN) - 1) << DSP2_MIDDLE_AE_HIST_EN_PRE_POS) -#define DSP2_MIDDLE_AE_HIST_EN_PRE_UMSK (~(((1U << DSP2_MIDDLE_AE_HIST_EN_PRE_LEN) - 1) << DSP2_MIDDLE_AE_HIST_EN_PRE_POS)) -#define DSP2_MIDDLE_AE_HIST_MODE_PRE DSP2_MIDDLE_AE_HIST_MODE_PRE -#define DSP2_MIDDLE_AE_HIST_MODE_PRE_POS (27U) -#define DSP2_MIDDLE_AE_HIST_MODE_PRE_LEN (1U) -#define DSP2_MIDDLE_AE_HIST_MODE_PRE_MSK (((1U << DSP2_MIDDLE_AE_HIST_MODE_PRE_LEN) - 1) << DSP2_MIDDLE_AE_HIST_MODE_PRE_POS) -#define DSP2_MIDDLE_AE_HIST_MODE_PRE_UMSK (~(((1U << DSP2_MIDDLE_AE_HIST_MODE_PRE_LEN) - 1) << DSP2_MIDDLE_AE_HIST_MODE_PRE_POS)) -#define DSP2_MIDDLE_AE_HIST_ROI_EN_PRE DSP2_MIDDLE_AE_HIST_ROI_EN_PRE -#define DSP2_MIDDLE_AE_HIST_ROI_EN_PRE_POS (28U) -#define DSP2_MIDDLE_AE_HIST_ROI_EN_PRE_LEN (1U) -#define DSP2_MIDDLE_AE_HIST_ROI_EN_PRE_MSK (((1U << DSP2_MIDDLE_AE_HIST_ROI_EN_PRE_LEN) - 1) << DSP2_MIDDLE_AE_HIST_ROI_EN_PRE_POS) -#define DSP2_MIDDLE_AE_HIST_ROI_EN_PRE_UMSK (~(((1U << DSP2_MIDDLE_AE_HIST_ROI_EN_PRE_LEN) - 1) << DSP2_MIDDLE_AE_HIST_ROI_EN_PRE_POS)) - -/* 0x2CC : ae_coeff */ -#define DSP2_MIDDLE_AE_COEFF_OFFSET (0x2CC) -#define DSP2_MIDDLE_AE_YSUM_COEFF_R_PRE DSP2_MIDDLE_AE_YSUM_COEFF_R_PRE -#define DSP2_MIDDLE_AE_YSUM_COEFF_R_PRE_POS (0U) -#define DSP2_MIDDLE_AE_YSUM_COEFF_R_PRE_LEN (8U) -#define DSP2_MIDDLE_AE_YSUM_COEFF_R_PRE_MSK (((1U << DSP2_MIDDLE_AE_YSUM_COEFF_R_PRE_LEN) - 1) << DSP2_MIDDLE_AE_YSUM_COEFF_R_PRE_POS) -#define DSP2_MIDDLE_AE_YSUM_COEFF_R_PRE_UMSK (~(((1U << DSP2_MIDDLE_AE_YSUM_COEFF_R_PRE_LEN) - 1) << DSP2_MIDDLE_AE_YSUM_COEFF_R_PRE_POS)) -#define DSP2_MIDDLE_AE_YSUM_COEFF_G_PRE DSP2_MIDDLE_AE_YSUM_COEFF_G_PRE -#define DSP2_MIDDLE_AE_YSUM_COEFF_G_PRE_POS (8U) -#define DSP2_MIDDLE_AE_YSUM_COEFF_G_PRE_LEN (8U) -#define DSP2_MIDDLE_AE_YSUM_COEFF_G_PRE_MSK (((1U << DSP2_MIDDLE_AE_YSUM_COEFF_G_PRE_LEN) - 1) << DSP2_MIDDLE_AE_YSUM_COEFF_G_PRE_POS) -#define DSP2_MIDDLE_AE_YSUM_COEFF_G_PRE_UMSK (~(((1U << DSP2_MIDDLE_AE_YSUM_COEFF_G_PRE_LEN) - 1) << DSP2_MIDDLE_AE_YSUM_COEFF_G_PRE_POS)) -#define DSP2_MIDDLE_AE_YSUM_COEFF_B_PRE DSP2_MIDDLE_AE_YSUM_COEFF_B_PRE -#define DSP2_MIDDLE_AE_YSUM_COEFF_B_PRE_POS (16U) -#define DSP2_MIDDLE_AE_YSUM_COEFF_B_PRE_LEN (8U) -#define DSP2_MIDDLE_AE_YSUM_COEFF_B_PRE_MSK (((1U << DSP2_MIDDLE_AE_YSUM_COEFF_B_PRE_LEN) - 1) << DSP2_MIDDLE_AE_YSUM_COEFF_B_PRE_POS) -#define DSP2_MIDDLE_AE_YSUM_COEFF_B_PRE_UMSK (~(((1U << DSP2_MIDDLE_AE_YSUM_COEFF_B_PRE_LEN) - 1) << DSP2_MIDDLE_AE_YSUM_COEFF_B_PRE_POS)) - -/* 0x2D0 : ae2_roi_x */ -#define DSP2_MIDDLE_AE2_ROI_X_OFFSET (0x2D0) -#define DSP2_MIDDLE_AE_HIST_X_MAX_PRE DSP2_MIDDLE_AE_HIST_X_MAX_PRE -#define DSP2_MIDDLE_AE_HIST_X_MAX_PRE_POS (0U) -#define DSP2_MIDDLE_AE_HIST_X_MAX_PRE_LEN (11U) -#define DSP2_MIDDLE_AE_HIST_X_MAX_PRE_MSK (((1U << DSP2_MIDDLE_AE_HIST_X_MAX_PRE_LEN) - 1) << DSP2_MIDDLE_AE_HIST_X_MAX_PRE_POS) -#define DSP2_MIDDLE_AE_HIST_X_MAX_PRE_UMSK (~(((1U << DSP2_MIDDLE_AE_HIST_X_MAX_PRE_LEN) - 1) << DSP2_MIDDLE_AE_HIST_X_MAX_PRE_POS)) -#define DSP2_MIDDLE_AE_HIST_X_MIN_PRE DSP2_MIDDLE_AE_HIST_X_MIN_PRE -#define DSP2_MIDDLE_AE_HIST_X_MIN_PRE_POS (16U) -#define DSP2_MIDDLE_AE_HIST_X_MIN_PRE_LEN (11U) -#define DSP2_MIDDLE_AE_HIST_X_MIN_PRE_MSK (((1U << DSP2_MIDDLE_AE_HIST_X_MIN_PRE_LEN) - 1) << DSP2_MIDDLE_AE_HIST_X_MIN_PRE_POS) -#define DSP2_MIDDLE_AE_HIST_X_MIN_PRE_UMSK (~(((1U << DSP2_MIDDLE_AE_HIST_X_MIN_PRE_LEN) - 1) << DSP2_MIDDLE_AE_HIST_X_MIN_PRE_POS)) - -/* 0x2D4 : ae2_roi_y */ -#define DSP2_MIDDLE_AE2_ROI_Y_OFFSET (0x2D4) -#define DSP2_MIDDLE_AE_HIST_Y_MAX_PRE DSP2_MIDDLE_AE_HIST_Y_MAX_PRE -#define DSP2_MIDDLE_AE_HIST_Y_MAX_PRE_POS (0U) -#define DSP2_MIDDLE_AE_HIST_Y_MAX_PRE_LEN (11U) -#define DSP2_MIDDLE_AE_HIST_Y_MAX_PRE_MSK (((1U << DSP2_MIDDLE_AE_HIST_Y_MAX_PRE_LEN) - 1) << DSP2_MIDDLE_AE_HIST_Y_MAX_PRE_POS) -#define DSP2_MIDDLE_AE_HIST_Y_MAX_PRE_UMSK (~(((1U << DSP2_MIDDLE_AE_HIST_Y_MAX_PRE_LEN) - 1) << DSP2_MIDDLE_AE_HIST_Y_MAX_PRE_POS)) -#define DSP2_MIDDLE_AE_HIST_Y_MIN_PRE DSP2_MIDDLE_AE_HIST_Y_MIN_PRE -#define DSP2_MIDDLE_AE_HIST_Y_MIN_PRE_POS (16U) -#define DSP2_MIDDLE_AE_HIST_Y_MIN_PRE_LEN (11U) -#define DSP2_MIDDLE_AE_HIST_Y_MIN_PRE_MSK (((1U << DSP2_MIDDLE_AE_HIST_Y_MIN_PRE_LEN) - 1) << DSP2_MIDDLE_AE_HIST_Y_MIN_PRE_POS) -#define DSP2_MIDDLE_AE_HIST_Y_MIN_PRE_UMSK (~(((1U << DSP2_MIDDLE_AE_HIST_Y_MIN_PRE_LEN) - 1) << DSP2_MIDDLE_AE_HIST_Y_MIN_PRE_POS)) - -/* 0x2E8 : ae_status */ -#define DSP2_MIDDLE_AE_STATUS_OFFSET (0x2E8) -#define DSP2_MIDDLE_AE_HIST_W_CNT_R DSP2_MIDDLE_AE_HIST_W_CNT_R -#define DSP2_MIDDLE_AE_HIST_W_CNT_R_POS (4U) -#define DSP2_MIDDLE_AE_HIST_W_CNT_R_LEN (5U) -#define DSP2_MIDDLE_AE_HIST_W_CNT_R_MSK (((1U << DSP2_MIDDLE_AE_HIST_W_CNT_R_LEN) - 1) << DSP2_MIDDLE_AE_HIST_W_CNT_R_POS) -#define DSP2_MIDDLE_AE_HIST_W_CNT_R_UMSK (~(((1U << DSP2_MIDDLE_AE_HIST_W_CNT_R_LEN) - 1) << DSP2_MIDDLE_AE_HIST_W_CNT_R_POS)) -#define DSP2_MIDDLE_BLAE_BUF_IDX_R DSP2_MIDDLE_BLAE_BUF_IDX_R -#define DSP2_MIDDLE_BLAE_BUF_IDX_R_POS (16U) -#define DSP2_MIDDLE_BLAE_BUF_IDX_R_LEN (1U) -#define DSP2_MIDDLE_BLAE_BUF_IDX_R_MSK (((1U << DSP2_MIDDLE_BLAE_BUF_IDX_R_LEN) - 1) << DSP2_MIDDLE_BLAE_BUF_IDX_R_POS) -#define DSP2_MIDDLE_BLAE_BUF_IDX_R_UMSK (~(((1U << DSP2_MIDDLE_BLAE_BUF_IDX_R_LEN) - 1) << DSP2_MIDDLE_BLAE_BUF_IDX_R_POS)) -#define DSP2_MIDDLE_BLAE_W_CNT_R DSP2_MIDDLE_BLAE_W_CNT_R -#define DSP2_MIDDLE_BLAE_W_CNT_R_POS (20U) -#define DSP2_MIDDLE_BLAE_W_CNT_R_LEN (5U) -#define DSP2_MIDDLE_BLAE_W_CNT_R_MSK (((1U << DSP2_MIDDLE_BLAE_W_CNT_R_LEN) - 1) << DSP2_MIDDLE_BLAE_W_CNT_R_POS) -#define DSP2_MIDDLE_BLAE_W_CNT_R_UMSK (~(((1U << DSP2_MIDDLE_BLAE_W_CNT_R_LEN) - 1) << DSP2_MIDDLE_BLAE_W_CNT_R_POS)) - -/* 0x2EC : ae_sta_dbg */ -#define DSP2_MIDDLE_AE_STA_DBG_OFFSET (0x2EC) -#define DSP2_MIDDLE_AE_GRID_CNT DSP2_MIDDLE_AE_GRID_CNT -#define DSP2_MIDDLE_AE_GRID_CNT_POS (0U) -#define DSP2_MIDDLE_AE_GRID_CNT_LEN (7U) -#define DSP2_MIDDLE_AE_GRID_CNT_MSK (((1U << DSP2_MIDDLE_AE_GRID_CNT_LEN) - 1) << DSP2_MIDDLE_AE_GRID_CNT_POS) -#define DSP2_MIDDLE_AE_GRID_CNT_UMSK (~(((1U << DSP2_MIDDLE_AE_GRID_CNT_LEN) - 1) << DSP2_MIDDLE_AE_GRID_CNT_POS)) -#define DSP2_MIDDLE_AE_STA_DONE DSP2_MIDDLE_AE_STA_DONE -#define DSP2_MIDDLE_AE_STA_DONE_POS (7U) -#define DSP2_MIDDLE_AE_STA_DONE_LEN (1U) -#define DSP2_MIDDLE_AE_STA_DONE_MSK (((1U << DSP2_MIDDLE_AE_STA_DONE_LEN) - 1) << DSP2_MIDDLE_AE_STA_DONE_POS) -#define DSP2_MIDDLE_AE_STA_DONE_UMSK (~(((1U << DSP2_MIDDLE_AE_STA_DONE_LEN) - 1) << DSP2_MIDDLE_AE_STA_DONE_POS)) -#define DSP2_MIDDLE_AE_WRITE_DATA_CNT DSP2_MIDDLE_AE_WRITE_DATA_CNT -#define DSP2_MIDDLE_AE_WRITE_DATA_CNT_POS (8U) -#define DSP2_MIDDLE_AE_WRITE_DATA_CNT_LEN (8U) -#define DSP2_MIDDLE_AE_WRITE_DATA_CNT_MSK (((1U << DSP2_MIDDLE_AE_WRITE_DATA_CNT_LEN) - 1) << DSP2_MIDDLE_AE_WRITE_DATA_CNT_POS) -#define DSP2_MIDDLE_AE_WRITE_DATA_CNT_UMSK (~(((1U << DSP2_MIDDLE_AE_WRITE_DATA_CNT_LEN) - 1) << DSP2_MIDDLE_AE_WRITE_DATA_CNT_POS)) -#define DSP2_MIDDLE_AE_STA_INT_FLAG DSP2_MIDDLE_AE_STA_INT_FLAG -#define DSP2_MIDDLE_AE_STA_INT_FLAG_POS (16U) -#define DSP2_MIDDLE_AE_STA_INT_FLAG_LEN (1U) -#define DSP2_MIDDLE_AE_STA_INT_FLAG_MSK (((1U << DSP2_MIDDLE_AE_STA_INT_FLAG_LEN) - 1) << DSP2_MIDDLE_AE_STA_INT_FLAG_POS) -#define DSP2_MIDDLE_AE_STA_INT_FLAG_UMSK (~(((1U << DSP2_MIDDLE_AE_STA_INT_FLAG_LEN) - 1) << DSP2_MIDDLE_AE_STA_INT_FLAG_POS)) -#define DSP2_MIDDLE_AE_GRID_CNT_MAX DSP2_MIDDLE_AE_GRID_CNT_MAX -#define DSP2_MIDDLE_AE_GRID_CNT_MAX_POS (17U) -#define DSP2_MIDDLE_AE_GRID_CNT_MAX_LEN (7U) -#define DSP2_MIDDLE_AE_GRID_CNT_MAX_MSK (((1U << DSP2_MIDDLE_AE_GRID_CNT_MAX_LEN) - 1) << DSP2_MIDDLE_AE_GRID_CNT_MAX_POS) -#define DSP2_MIDDLE_AE_GRID_CNT_MAX_UMSK (~(((1U << DSP2_MIDDLE_AE_GRID_CNT_MAX_LEN) - 1) << DSP2_MIDDLE_AE_GRID_CNT_MAX_POS)) -#define DSP2_MIDDLE_AE_FIFO_FULL DSP2_MIDDLE_AE_FIFO_FULL -#define DSP2_MIDDLE_AE_FIFO_FULL_POS (24U) -#define DSP2_MIDDLE_AE_FIFO_FULL_LEN (1U) -#define DSP2_MIDDLE_AE_FIFO_FULL_MSK (((1U << DSP2_MIDDLE_AE_FIFO_FULL_LEN) - 1) << DSP2_MIDDLE_AE_FIFO_FULL_POS) -#define DSP2_MIDDLE_AE_FIFO_FULL_UMSK (~(((1U << DSP2_MIDDLE_AE_FIFO_FULL_LEN) - 1) << DSP2_MIDDLE_AE_FIFO_FULL_POS)) -#define DSP2_MIDDLE_AE_CONTROL_STATUS DSP2_MIDDLE_AE_CONTROL_STATUS -#define DSP2_MIDDLE_AE_CONTROL_STATUS_POS (25U) -#define DSP2_MIDDLE_AE_CONTROL_STATUS_LEN (4U) -#define DSP2_MIDDLE_AE_CONTROL_STATUS_MSK (((1U << DSP2_MIDDLE_AE_CONTROL_STATUS_LEN) - 1) << DSP2_MIDDLE_AE_CONTROL_STATUS_POS) -#define DSP2_MIDDLE_AE_CONTROL_STATUS_UMSK (~(((1U << DSP2_MIDDLE_AE_CONTROL_STATUS_LEN) - 1) << DSP2_MIDDLE_AE_CONTROL_STATUS_POS)) -#define DSP2_MIDDLE_AE_OPERATION_DONE DSP2_MIDDLE_AE_OPERATION_DONE -#define DSP2_MIDDLE_AE_OPERATION_DONE_POS (29U) -#define DSP2_MIDDLE_AE_OPERATION_DONE_LEN (1U) -#define DSP2_MIDDLE_AE_OPERATION_DONE_MSK (((1U << DSP2_MIDDLE_AE_OPERATION_DONE_LEN) - 1) << DSP2_MIDDLE_AE_OPERATION_DONE_POS) -#define DSP2_MIDDLE_AE_OPERATION_DONE_UMSK (~(((1U << DSP2_MIDDLE_AE_OPERATION_DONE_LEN) - 1) << DSP2_MIDDLE_AE_OPERATION_DONE_POS)) -#define DSP2_MIDDLE_AE_FIFO_EMPTY DSP2_MIDDLE_AE_FIFO_EMPTY -#define DSP2_MIDDLE_AE_FIFO_EMPTY_POS (30U) -#define DSP2_MIDDLE_AE_FIFO_EMPTY_LEN (1U) -#define DSP2_MIDDLE_AE_FIFO_EMPTY_MSK (((1U << DSP2_MIDDLE_AE_FIFO_EMPTY_LEN) - 1) << DSP2_MIDDLE_AE_FIFO_EMPTY_POS) -#define DSP2_MIDDLE_AE_FIFO_EMPTY_UMSK (~(((1U << DSP2_MIDDLE_AE_FIFO_EMPTY_LEN) - 1) << DSP2_MIDDLE_AE_FIFO_EMPTY_POS)) - -/* 0x2F4 : awb_sta_dbg1 */ -#define DSP2_MIDDLE_AWB_STA_DBG1_OFFSET (0x2F4) -#define DSP2_MIDDLE_AWB_GRID_CNT_MAX DSP2_MIDDLE_AWB_GRID_CNT_MAX -#define DSP2_MIDDLE_AWB_GRID_CNT_MAX_POS (0U) -#define DSP2_MIDDLE_AWB_GRID_CNT_MAX_LEN (11U) -#define DSP2_MIDDLE_AWB_GRID_CNT_MAX_MSK (((1U << DSP2_MIDDLE_AWB_GRID_CNT_MAX_LEN) - 1) << DSP2_MIDDLE_AWB_GRID_CNT_MAX_POS) -#define DSP2_MIDDLE_AWB_GRID_CNT_MAX_UMSK (~(((1U << DSP2_MIDDLE_AWB_GRID_CNT_MAX_LEN) - 1) << DSP2_MIDDLE_AWB_GRID_CNT_MAX_POS)) -#define DSP2_MIDDLE_AWB_FIFO_FULL DSP2_MIDDLE_AWB_FIFO_FULL -#define DSP2_MIDDLE_AWB_FIFO_FULL_POS (12U) -#define DSP2_MIDDLE_AWB_FIFO_FULL_LEN (1U) -#define DSP2_MIDDLE_AWB_FIFO_FULL_MSK (((1U << DSP2_MIDDLE_AWB_FIFO_FULL_LEN) - 1) << DSP2_MIDDLE_AWB_FIFO_FULL_POS) -#define DSP2_MIDDLE_AWB_FIFO_FULL_UMSK (~(((1U << DSP2_MIDDLE_AWB_FIFO_FULL_LEN) - 1) << DSP2_MIDDLE_AWB_FIFO_FULL_POS)) -#define DSP2_MIDDLE_AWB_CONTROL_STATUS DSP2_MIDDLE_AWB_CONTROL_STATUS -#define DSP2_MIDDLE_AWB_CONTROL_STATUS_POS (16U) -#define DSP2_MIDDLE_AWB_CONTROL_STATUS_LEN (4U) -#define DSP2_MIDDLE_AWB_CONTROL_STATUS_MSK (((1U << DSP2_MIDDLE_AWB_CONTROL_STATUS_LEN) - 1) << DSP2_MIDDLE_AWB_CONTROL_STATUS_POS) -#define DSP2_MIDDLE_AWB_CONTROL_STATUS_UMSK (~(((1U << DSP2_MIDDLE_AWB_CONTROL_STATUS_LEN) - 1) << DSP2_MIDDLE_AWB_CONTROL_STATUS_POS)) -#define DSP2_MIDDLE_AWB_OPERATION_DONE DSP2_MIDDLE_AWB_OPERATION_DONE -#define DSP2_MIDDLE_AWB_OPERATION_DONE_POS (20U) -#define DSP2_MIDDLE_AWB_OPERATION_DONE_LEN (1U) -#define DSP2_MIDDLE_AWB_OPERATION_DONE_MSK (((1U << DSP2_MIDDLE_AWB_OPERATION_DONE_LEN) - 1) << DSP2_MIDDLE_AWB_OPERATION_DONE_POS) -#define DSP2_MIDDLE_AWB_OPERATION_DONE_UMSK (~(((1U << DSP2_MIDDLE_AWB_OPERATION_DONE_LEN) - 1) << DSP2_MIDDLE_AWB_OPERATION_DONE_POS)) -#define DSP2_MIDDLE_AWB_FIFO_EMPTY DSP2_MIDDLE_AWB_FIFO_EMPTY -#define DSP2_MIDDLE_AWB_FIFO_EMPTY_POS (21U) -#define DSP2_MIDDLE_AWB_FIFO_EMPTY_LEN (1U) -#define DSP2_MIDDLE_AWB_FIFO_EMPTY_MSK (((1U << DSP2_MIDDLE_AWB_FIFO_EMPTY_LEN) - 1) << DSP2_MIDDLE_AWB_FIFO_EMPTY_POS) -#define DSP2_MIDDLE_AWB_FIFO_EMPTY_UMSK (~(((1U << DSP2_MIDDLE_AWB_FIFO_EMPTY_LEN) - 1) << DSP2_MIDDLE_AWB_FIFO_EMPTY_POS)) -#define DSP2_MIDDLE_BLAWB_W_CNT_R DSP2_MIDDLE_BLAWB_W_CNT_R -#define DSP2_MIDDLE_BLAWB_W_CNT_R_POS (24U) -#define DSP2_MIDDLE_BLAWB_W_CNT_R_LEN (5U) -#define DSP2_MIDDLE_BLAWB_W_CNT_R_MSK (((1U << DSP2_MIDDLE_BLAWB_W_CNT_R_LEN) - 1) << DSP2_MIDDLE_BLAWB_W_CNT_R_POS) -#define DSP2_MIDDLE_BLAWB_W_CNT_R_UMSK (~(((1U << DSP2_MIDDLE_BLAWB_W_CNT_R_LEN) - 1) << DSP2_MIDDLE_BLAWB_W_CNT_R_POS)) -#define DSP2_MIDDLE_BLAWB_BUF_IDX_R DSP2_MIDDLE_BLAWB_BUF_IDX_R -#define DSP2_MIDDLE_BLAWB_BUF_IDX_R_POS (31U) -#define DSP2_MIDDLE_BLAWB_BUF_IDX_R_LEN (1U) -#define DSP2_MIDDLE_BLAWB_BUF_IDX_R_MSK (((1U << DSP2_MIDDLE_BLAWB_BUF_IDX_R_LEN) - 1) << DSP2_MIDDLE_BLAWB_BUF_IDX_R_POS) -#define DSP2_MIDDLE_BLAWB_BUF_IDX_R_UMSK (~(((1U << DSP2_MIDDLE_BLAWB_BUF_IDX_R_LEN) - 1) << DSP2_MIDDLE_BLAWB_BUF_IDX_R_POS)) - -/* 0x2F8 : awb_sta_dbg0 */ -#define DSP2_MIDDLE_AWB_STA_DBG0_OFFSET (0x2F8) -#define DSP2_MIDDLE_AWB_GRID_CNT DSP2_MIDDLE_AWB_GRID_CNT -#define DSP2_MIDDLE_AWB_GRID_CNT_POS (0U) -#define DSP2_MIDDLE_AWB_GRID_CNT_LEN (10U) -#define DSP2_MIDDLE_AWB_GRID_CNT_MSK (((1U << DSP2_MIDDLE_AWB_GRID_CNT_LEN) - 1) << DSP2_MIDDLE_AWB_GRID_CNT_POS) -#define DSP2_MIDDLE_AWB_GRID_CNT_UMSK (~(((1U << DSP2_MIDDLE_AWB_GRID_CNT_LEN) - 1) << DSP2_MIDDLE_AWB_GRID_CNT_POS)) -#define DSP2_MIDDLE_AWB_STA_DONE DSP2_MIDDLE_AWB_STA_DONE -#define DSP2_MIDDLE_AWB_STA_DONE_POS (12U) -#define DSP2_MIDDLE_AWB_STA_DONE_LEN (1U) -#define DSP2_MIDDLE_AWB_STA_DONE_MSK (((1U << DSP2_MIDDLE_AWB_STA_DONE_LEN) - 1) << DSP2_MIDDLE_AWB_STA_DONE_POS) -#define DSP2_MIDDLE_AWB_STA_DONE_UMSK (~(((1U << DSP2_MIDDLE_AWB_STA_DONE_LEN) - 1) << DSP2_MIDDLE_AWB_STA_DONE_POS)) -#define DSP2_MIDDLE_AWB_WRITE_DATA_CNT DSP2_MIDDLE_AWB_WRITE_DATA_CNT -#define DSP2_MIDDLE_AWB_WRITE_DATA_CNT_POS (16U) -#define DSP2_MIDDLE_AWB_WRITE_DATA_CNT_LEN (12U) -#define DSP2_MIDDLE_AWB_WRITE_DATA_CNT_MSK (((1U << DSP2_MIDDLE_AWB_WRITE_DATA_CNT_LEN) - 1) << DSP2_MIDDLE_AWB_WRITE_DATA_CNT_POS) -#define DSP2_MIDDLE_AWB_WRITE_DATA_CNT_UMSK (~(((1U << DSP2_MIDDLE_AWB_WRITE_DATA_CNT_LEN) - 1) << DSP2_MIDDLE_AWB_WRITE_DATA_CNT_POS)) -#define DSP2_MIDDLE_AWB_STA_INT_FLAG DSP2_MIDDLE_AWB_STA_INT_FLAG -#define DSP2_MIDDLE_AWB_STA_INT_FLAG_POS (28U) -#define DSP2_MIDDLE_AWB_STA_INT_FLAG_LEN (1U) -#define DSP2_MIDDLE_AWB_STA_INT_FLAG_MSK (((1U << DSP2_MIDDLE_AWB_STA_INT_FLAG_LEN) - 1) << DSP2_MIDDLE_AWB_STA_INT_FLAG_POS) -#define DSP2_MIDDLE_AWB_STA_INT_FLAG_UMSK (~(((1U << DSP2_MIDDLE_AWB_STA_INT_FLAG_LEN) - 1) << DSP2_MIDDLE_AWB_STA_INT_FLAG_POS)) - -/* 0x2FC : dummy */ -#define DSP2_MIDDLE_DUMMY_OFFSET (0x2FC) - -struct dsp2_middle_reg { - /* 0x0 reserved */ - uint8_t RESERVED0x0[548]; - - /* 0x224 : LSC_setting */ - union { - struct { - uint32_t reserved_0_7 : 8; /* [ 7: 0], rsvd, 0x0 */ - uint32_t Lsc_on_w : 1; /* [ 8], r/w, 0x0 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t X_offset_w : 8; /* [23:16], r/w, 0x4 */ - uint32_t Y_offset_w : 8; /* [31:24], r/w, 0x4 */ - } BF; - uint32_t WORD; - } LSC_setting; - - /* 0x228 : LSC_coeff_R_A */ - union { - struct { - uint32_t R_Acoeff_w : 23; /* [22: 0], r/w, 0x0 */ - uint32_t reserved_23_31 : 9; /* [31:23], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } LSC_coeff_R_A; - - /* 0x22C : LSC_coeff_R_BE */ - union { - struct { - uint32_t R_Bcoeff_w : 13; /* [12: 0], r/w, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t R_Ecoeff_w : 13; /* [28:16], r/w, 0x0 */ - uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } LSC_coeff_R_BE; - - /* 0x230 : LSC_coeff_R_CD */ - union { - struct { - uint32_t R_Dcoeff_w : 23; /* [22: 0], r/w, 0x0 */ - uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */ - uint32_t R_Ccoeff_w : 8; /* [31:24], r/w, 0xff */ - } BF; - uint32_t WORD; - } LSC_coeff_R_CD; - - /* 0x234 : LSC_coeff_R_G */ - union { - struct { - uint32_t R_Gcoeff_w : 23; /* [22: 0], r/w, 0x0 */ - uint32_t reserved_23_31 : 9; /* [31:23], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } LSC_coeff_R_G; - - /* 0x238 : LSC_coeff_G_A */ - union { - struct { - uint32_t G_Acoeff_w : 23; /* [22: 0], r/w, 0x0 */ - uint32_t reserved_23_31 : 9; /* [31:23], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } LSC_coeff_G_A; - - /* 0x23C : LSC_coeff_G_BE */ - union { - struct { - uint32_t G_Bcoeff_w : 13; /* [12: 0], r/w, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t G_Ecoeff_w : 13; /* [28:16], r/w, 0x0 */ - uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } LSC_coeff_G_BE; - - /* 0x240 : LSC_coeff_G_CD */ - union { - struct { - uint32_t G_Dcoeff_w : 23; /* [22: 0], r/w, 0x0 */ - uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */ - uint32_t G_Ccoeff_w : 8; /* [31:24], r/w, 0xff */ - } BF; - uint32_t WORD; - } LSC_coeff_G_CD; - - /* 0x244 : LSC_coeff_G_G */ - union { - struct { - uint32_t G_Gcoeff_w : 23; /* [22: 0], r/w, 0x0 */ - uint32_t reserved_23_31 : 9; /* [31:23], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } LSC_coeff_G_G; - - /* 0x248 : LSC_coeff_B_A */ - union { - struct { - uint32_t B_Acoeff_w : 23; /* [22: 0], r/w, 0x0 */ - uint32_t reserved_23_31 : 9; /* [31:23], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } LSC_coeff_B_A; - - /* 0x24C : LSC_coeff_B_BE */ - union { - struct { - uint32_t B_Bcoeff_w : 13; /* [12: 0], r/w, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t B_Ecoeff_w : 13; /* [28:16], r/w, 0x0 */ - uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } LSC_coeff_B_BE; - - /* 0x250 : LSC_coeff_B_CD */ - union { - struct { - uint32_t B_Dcoeff_w : 23; /* [22: 0], r/w, 0x0 */ - uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */ - uint32_t B_Ccoeff_w : 8; /* [31:24], r/w, 0xff */ - } BF; - uint32_t WORD; - } LSC_coeff_B_CD; - - /* 0x254 : LSC_coeff_B_G */ - union { - struct { - uint32_t B_Gcoeff_w : 23; /* [22: 0], r/w, 0x0 */ - uint32_t reserved_23_31 : 9; /* [31:23], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } LSC_coeff_B_G; - - /* 0x258 : MAX_R_G */ - union { - struct { - uint32_t MAXR_w : 16; /* [15: 0], r/w, 0xff */ - uint32_t MAXG_w : 16; /* [31:16], r/w, 0xff */ - } BF; - uint32_t WORD; - } MAX_R_G; - - /* 0x25C : MAX_B */ - union { - struct { - uint32_t MAXB_w : 16; /* [15: 0], r/w, 0xff */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } MAX_B; - - /* 0x260 : defect_setting */ - union { - struct { - uint32_t defect_correct_mode_w : 3; /* [ 2: 0], r/w, 0x0 */ - uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */ - uint32_t resolution_enhance1_w : 1; /* [ 8], r/w, 0x1 */ - uint32_t resolution_enhance2_w : 1; /* [ 9], r/w, 0x1 */ - uint32_t resolution_enhance3_w : 1; /* [ 10], r/w, 0x1 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t defect_address_w : 8; /* [23:16], r/w, 0x4 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } defect_setting; - - /* 0x264 : defect_position */ - union { - struct { - uint32_t x_position_w : 16; /* [15: 0], r/w, 0x0 */ - uint32_t y_position_w : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } defect_position; - - /* 0x268 : defect_th_A */ - union { - struct { - uint32_t defect_th1_w : 8; /* [ 7: 0], r/w, 0x46 */ - uint32_t defect_th2_w : 8; /* [15: 8], r/w, 0x14 */ - uint32_t defect_th3_w : 8; /* [23:16], r/w, 0x32 */ - uint32_t defect_th4_w : 8; /* [31:24], r/w, 0x32 */ - } BF; - uint32_t WORD; - } defect_th_A; - - /* 0x26C : defect_th_B */ - union { - struct { - uint32_t defect_th5_w : 8; /* [ 7: 0], r/w, 0x14 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } defect_th_B; - - /* 0x270 : awb_setting */ - union { - struct { - uint32_t awb_switch_bank_en_w : 1; /* [ 0], r/w, 0x1 */ - uint32_t new_awb_sta_enable_w : 1; /* [ 1], r/w, 0x0 */ - uint32_t bl_awb_gain_sel_w : 1; /* [ 2], r/w, 0x1 */ - uint32_t bl_digital_gain_sel_w : 1; /* [ 3], r/w, 0x1 */ - uint32_t reserved_4_15 : 12; /* [15: 4], rsvd, 0x0 */ - uint32_t grid_cnt_within_thre_r : 11; /* [26:16], r, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb_setting; - - /* 0x274 : awb_roi_x */ - union { - struct { - uint32_t awb_roi_start_x_w : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t awb_roi_width_w : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb_roi_x; - - /* 0x278 : awb_roi_y */ - union { - struct { - uint32_t awb_roi_start_y_w : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t awb_roi_height_w : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb_roi_y; - - /* 0x27C : awb_image_size */ - union { - struct { - uint32_t awb_image_width_w : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t awb_image_height_w : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb_image_size; - - /* 0x280 : awb_grid_size */ - union { - struct { - uint32_t awb_grid_width_w : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t awb_grid_height_w : 8; /* [15: 8], r/w, 0x0 */ - uint32_t awb_grid_x_max_w : 6; /* [21:16], r/w, 0x0 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t awb_grid_y_max_w : 6; /* [29:24], r/w, 0x0 */ - uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb_grid_size; - - /* 0x284 : awb_r_thre */ - union { - struct { - uint32_t awb_r_max_thr_w : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t awb_r_min_thr_w : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb_r_thre; - - /* 0x288 : awb_g_thre */ - union { - struct { - uint32_t awb_g_max_thr_w : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t awb_g_min_thr_w : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb_g_thre; - - /* 0x28C : awb_b_thre */ - union { - struct { - uint32_t awb_b_max_thr_w : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t awb_b_min_thr_w : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb_b_thre; - - /* 0x290 : awb_rgr_gain */ - union { - struct { - uint32_t awb_gr_gain_pre : 16; /* [15: 0], r/w, 0x1000 */ - uint32_t awb_r_gain_pre : 16; /* [31:16], r/w, 0x1000 */ - } BF; - uint32_t WORD; - } awb_rgr_gain; - - /* 0x294 : awb_bgb_gain */ - union { - struct { - uint32_t awb_gb_gain_pre : 16; /* [15: 0], r/w, 0x1000 */ - uint32_t awb_b_gain_pre : 16; /* [31:16], r/w, 0x1000 */ - } BF; - uint32_t WORD; - } awb_bgb_gain; - - /* 0x298 : awb_rgr_offset */ - union { - struct { - uint32_t awb_gr_offset_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t awb_r_offset_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb_rgr_offset; - - /* 0x29C : awb_bgb_offset */ - union { - struct { - uint32_t awb_gb_offset_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t awb_b_offset_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb_bgb_offset; - - /* 0x2A0 : cfa_int_1 */ - union { - struct { - uint32_t reg_cfa_fringe_on_w : 1; /* [ 0], r/w, 0x1 */ - uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } cfa_int_1; - - /* 0x2a4 reserved */ - uint8_t RESERVED0x2a4[4]; - - /* 0x2A8 : digital_rgr_gain */ - union { - struct { - uint32_t digital_gr_gain_pre : 16; /* [15: 0], r/w, 0x1000 */ - uint32_t digital_r_gain_pre : 16; /* [31:16], r/w, 0x1000 */ - } BF; - uint32_t WORD; - } digital_rgr_gain; - - /* 0x2AC : digital_bgb_gain */ - union { - struct { - uint32_t digital_gb_gain_pre : 16; /* [15: 0], r/w, 0x1000 */ - uint32_t digital_b_gain_pre : 16; /* [31:16], r/w, 0x1000 */ - } BF; - uint32_t WORD; - } digital_bgb_gain; - - /* 0x2b0 reserved */ - uint8_t RESERVED0x2b0[12]; - - /* 0x2BC : ae_roi_x */ - union { - struct { - uint32_t ae_roi_start_x_pre : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t ae_roi_width_pre : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } ae_roi_x; - - /* 0x2C0 : ae_roi_y */ - union { - struct { - uint32_t ae_roi_start_y_pre : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t ae_roi_height_pre : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } ae_roi_y; - - /* 0x2C4 : ae_image_size */ - union { - struct { - uint32_t ae_image_width_pre : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t ae_image_height_pre : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } ae_image_size; - - /* 0x2C8 : ae_grid_size */ - union { - struct { - uint32_t ae_grid_width_pre : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t ae_grid_height_pre : 8; /* [15: 8], r/w, 0x0 */ - uint32_t ae_grid_y_max_pre : 4; /* [19:16], r/w, 0x0 */ - uint32_t ae_grid_x_max_pre : 4; /* [23:20], r/w, 0x0 */ - uint32_t new_ae_sta_enable_w : 1; /* [ 24], r/w, 0x0 */ - uint32_t ae_switch_bank_en_pre : 1; /* [ 25], r/w, 0x1 */ - uint32_t ae_hist_en_pre : 1; /* [ 26], r/w, 0x1 */ - uint32_t ae_hist_mode_pre : 1; /* [ 27], r/w, 0x1 */ - uint32_t ae_hist_roi_en_pre : 1; /* [ 28], r/w, 0x0 */ - uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } ae_grid_size; - - /* 0x2CC : ae_coeff */ - union { - struct { - uint32_t ae_ysum_coeff_r_pre : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t ae_ysum_coeff_g_pre : 8; /* [15: 8], r/w, 0x0 */ - uint32_t ae_ysum_coeff_b_pre : 8; /* [23:16], r/w, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } ae_coeff; - - /* 0x2D0 : ae2_roi_x */ - union { - struct { - uint32_t ae_hist_x_max_pre : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t ae_hist_x_min_pre : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } ae2_roi_x; - - /* 0x2D4 : ae2_roi_y */ - union { - struct { - uint32_t ae_hist_y_max_pre : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t ae_hist_y_min_pre : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } ae2_roi_y; - - /* 0x2d8 reserved */ - uint8_t RESERVED0x2d8[16]; - - /* 0x2E8 : ae_status */ - union { - struct { - uint32_t reserved_0_3 : 4; /* [ 3: 0], rsvd, 0x0 */ - uint32_t ae_hist_w_cnt_r : 5; /* [ 8: 4], r, 0x0 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t blae_buf_idx_r : 1; /* [ 16], r, 0x0 */ - uint32_t reserved_17_19 : 3; /* [19:17], rsvd, 0x0 */ - uint32_t blae_w_cnt_r : 5; /* [24:20], r, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } ae_status; - - /* 0x2EC : ae_sta_dbg */ - union { - struct { - uint32_t ae_grid_cnt : 7; /* [ 6: 0], r, 0x0 */ - uint32_t ae_sta_done : 1; /* [ 7], r, 0x0 */ - uint32_t ae_write_data_cnt : 8; /* [15: 8], r, 0x0 */ - uint32_t ae_sta_int_flag : 1; /* [ 16], r, 0x0 */ - uint32_t ae_grid_cnt_max : 7; /* [23:17], r, 0x0 */ - uint32_t ae_fifo_full : 1; /* [ 24], r, 0x0 */ - uint32_t ae_control_status : 4; /* [28:25], r, 0x0 */ - uint32_t ae_operation_done : 1; /* [ 29], r, 0x0 */ - uint32_t ae_fifo_empty : 1; /* [ 30], r, 0x0 */ - uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } ae_sta_dbg; - - /* 0x2f0 reserved */ - uint8_t RESERVED0x2f0[4]; - - /* 0x2F4 : awb_sta_dbg1 */ - union { - struct { - uint32_t awb_grid_cnt_max : 11; /* [10: 0], r, 0x0 */ - uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */ - uint32_t awb_fifo_full : 1; /* [ 12], r, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t awb_control_status : 4; /* [19:16], r, 0x0 */ - uint32_t awb_operation_done : 1; /* [ 20], r, 0x0 */ - uint32_t awb_fifo_empty : 1; /* [ 21], r, 0x0 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t blawb_w_cnt_r : 5; /* [28:24], r, 0x0 */ - uint32_t reserved_29_30 : 2; /* [30:29], rsvd, 0x0 */ - uint32_t blawb_buf_idx_r : 1; /* [ 31], r, 0x0 */ - } BF; - uint32_t WORD; - } awb_sta_dbg1; - - /* 0x2F8 : awb_sta_dbg0 */ - union { - struct { - uint32_t awb_grid_cnt : 10; /* [ 9: 0], r, 0x0 */ - uint32_t reserved_10_11 : 2; /* [11:10], rsvd, 0x0 */ - uint32_t awb_sta_done : 1; /* [ 12], r, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t awb_write_data_cnt : 12; /* [27:16], r, 0x0 */ - uint32_t awb_sta_int_flag : 1; /* [ 28], r, 0x0 */ - uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb_sta_dbg0; - - /* 0x2FC : dummy */ - union { - struct { - uint32_t Reserved_31_0 : 32; /* [31: 0], r/w, 0xf0f0f0f0 */ - } BF; - uint32_t WORD; - } dummy; -}; - -typedef volatile struct dsp2_middle_reg dsp2_middle_reg_t; - -#endif /* __DSP2_MIDDLE_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_misc_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_misc_reg.h deleted file mode 100644 index f7b5371083..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_misc_reg.h +++ /dev/null @@ -1,4491 +0,0 @@ -/** - ****************************************************************************** - * @file dsp2_misc_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __DSP2_MISC_REG_H__ -#define __DSP2_MISC_REG_H__ - -#include "bl808.h" - -/* 0x0 : config */ -#define DSP2_MISC_CONFIG_OFFSET (0x0) -#define DSP2_MISC_RG_DVPAS_ENABLE DSP2_MISC_RG_DVPAS_ENABLE -#define DSP2_MISC_RG_DVPAS_ENABLE_POS (0U) -#define DSP2_MISC_RG_DVPAS_ENABLE_LEN (1U) -#define DSP2_MISC_RG_DVPAS_ENABLE_MSK (((1U << DSP2_MISC_RG_DVPAS_ENABLE_LEN) - 1) << DSP2_MISC_RG_DVPAS_ENABLE_POS) -#define DSP2_MISC_RG_DVPAS_ENABLE_UMSK (~(((1U << DSP2_MISC_RG_DVPAS_ENABLE_LEN) - 1) << DSP2_MISC_RG_DVPAS_ENABLE_POS)) -#define DSP2_MISC_RG_DVPAS_HS_INV DSP2_MISC_RG_DVPAS_HS_INV -#define DSP2_MISC_RG_DVPAS_HS_INV_POS (1U) -#define DSP2_MISC_RG_DVPAS_HS_INV_LEN (1U) -#define DSP2_MISC_RG_DVPAS_HS_INV_MSK (((1U << DSP2_MISC_RG_DVPAS_HS_INV_LEN) - 1) << DSP2_MISC_RG_DVPAS_HS_INV_POS) -#define DSP2_MISC_RG_DVPAS_HS_INV_UMSK (~(((1U << DSP2_MISC_RG_DVPAS_HS_INV_LEN) - 1) << DSP2_MISC_RG_DVPAS_HS_INV_POS)) -#define DSP2_MISC_RG_DVPAS_VS_INV DSP2_MISC_RG_DVPAS_VS_INV -#define DSP2_MISC_RG_DVPAS_VS_INV_POS (2U) -#define DSP2_MISC_RG_DVPAS_VS_INV_LEN (1U) -#define DSP2_MISC_RG_DVPAS_VS_INV_MSK (((1U << DSP2_MISC_RG_DVPAS_VS_INV_LEN) - 1) << DSP2_MISC_RG_DVPAS_VS_INV_POS) -#define DSP2_MISC_RG_DVPAS_VS_INV_UMSK (~(((1U << DSP2_MISC_RG_DVPAS_VS_INV_LEN) - 1) << DSP2_MISC_RG_DVPAS_VS_INV_POS)) -#define DSP2_MISC_RG_DVPAS_DA_ORDER DSP2_MISC_RG_DVPAS_DA_ORDER -#define DSP2_MISC_RG_DVPAS_DA_ORDER_POS (3U) -#define DSP2_MISC_RG_DVPAS_DA_ORDER_LEN (1U) -#define DSP2_MISC_RG_DVPAS_DA_ORDER_MSK (((1U << DSP2_MISC_RG_DVPAS_DA_ORDER_LEN) - 1) << DSP2_MISC_RG_DVPAS_DA_ORDER_POS) -#define DSP2_MISC_RG_DVPAS_DA_ORDER_UMSK (~(((1U << DSP2_MISC_RG_DVPAS_DA_ORDER_LEN) - 1) << DSP2_MISC_RG_DVPAS_DA_ORDER_POS)) -#define DSP2_MISC_RG_DVPAS_FIFO_TH DSP2_MISC_RG_DVPAS_FIFO_TH -#define DSP2_MISC_RG_DVPAS_FIFO_TH_POS (16U) -#define DSP2_MISC_RG_DVPAS_FIFO_TH_LEN (11U) -#define DSP2_MISC_RG_DVPAS_FIFO_TH_MSK (((1U << DSP2_MISC_RG_DVPAS_FIFO_TH_LEN) - 1) << DSP2_MISC_RG_DVPAS_FIFO_TH_POS) -#define DSP2_MISC_RG_DVPAS_FIFO_TH_UMSK (~(((1U << DSP2_MISC_RG_DVPAS_FIFO_TH_LEN) - 1) << DSP2_MISC_RG_DVPAS_FIFO_TH_POS)) -#define DSP2_MISC_CR_DSP2_DE_AS_HSYNC DSP2_MISC_CR_DSP2_DE_AS_HSYNC -#define DSP2_MISC_CR_DSP2_DE_AS_HSYNC_POS (30U) -#define DSP2_MISC_CR_DSP2_DE_AS_HSYNC_LEN (1U) -#define DSP2_MISC_CR_DSP2_DE_AS_HSYNC_MSK (((1U << DSP2_MISC_CR_DSP2_DE_AS_HSYNC_LEN) - 1) << DSP2_MISC_CR_DSP2_DE_AS_HSYNC_POS) -#define DSP2_MISC_CR_DSP2_DE_AS_HSYNC_UMSK (~(((1U << DSP2_MISC_CR_DSP2_DE_AS_HSYNC_LEN) - 1) << DSP2_MISC_CR_DSP2_DE_AS_HSYNC_POS)) -#define DSP2_MISC_REG_DSP2_PCLK_FORCE_ON DSP2_MISC_REG_DSP2_PCLK_FORCE_ON -#define DSP2_MISC_REG_DSP2_PCLK_FORCE_ON_POS (31U) -#define DSP2_MISC_REG_DSP2_PCLK_FORCE_ON_LEN (1U) -#define DSP2_MISC_REG_DSP2_PCLK_FORCE_ON_MSK (((1U << DSP2_MISC_REG_DSP2_PCLK_FORCE_ON_LEN) - 1) << DSP2_MISC_REG_DSP2_PCLK_FORCE_ON_POS) -#define DSP2_MISC_REG_DSP2_PCLK_FORCE_ON_UMSK (~(((1U << DSP2_MISC_REG_DSP2_PCLK_FORCE_ON_LEN) - 1) << DSP2_MISC_REG_DSP2_PCLK_FORCE_ON_POS)) - -/* 0x4 : pix_data_ctrl */ -#define DSP2_MISC_PIX_DATA_CTRL_OFFSET (0x4) -#define DSP2_MISC_REG_PIX_DATA_CTRL DSP2_MISC_REG_PIX_DATA_CTRL -#define DSP2_MISC_REG_PIX_DATA_CTRL_POS (0U) -#define DSP2_MISC_REG_PIX_DATA_CTRL_LEN (12U) -#define DSP2_MISC_REG_PIX_DATA_CTRL_MSK (((1U << DSP2_MISC_REG_PIX_DATA_CTRL_LEN) - 1) << DSP2_MISC_REG_PIX_DATA_CTRL_POS) -#define DSP2_MISC_REG_PIX_DATA_CTRL_UMSK (~(((1U << DSP2_MISC_REG_PIX_DATA_CTRL_LEN) - 1) << DSP2_MISC_REG_PIX_DATA_CTRL_POS)) -#define DSP2_MISC_REG_PIX_DATA_SHT_BIT DSP2_MISC_REG_PIX_DATA_SHT_BIT -#define DSP2_MISC_REG_PIX_DATA_SHT_BIT_POS (16U) -#define DSP2_MISC_REG_PIX_DATA_SHT_BIT_LEN (4U) -#define DSP2_MISC_REG_PIX_DATA_SHT_BIT_MSK (((1U << DSP2_MISC_REG_PIX_DATA_SHT_BIT_LEN) - 1) << DSP2_MISC_REG_PIX_DATA_SHT_BIT_POS) -#define DSP2_MISC_REG_PIX_DATA_SHT_BIT_UMSK (~(((1U << DSP2_MISC_REG_PIX_DATA_SHT_BIT_LEN) - 1) << DSP2_MISC_REG_PIX_DATA_SHT_BIT_POS)) -#define DSP2_MISC_REG_PIX_DATA_SHT_DIR DSP2_MISC_REG_PIX_DATA_SHT_DIR -#define DSP2_MISC_REG_PIX_DATA_SHT_DIR_POS (20U) -#define DSP2_MISC_REG_PIX_DATA_SHT_DIR_LEN (1U) -#define DSP2_MISC_REG_PIX_DATA_SHT_DIR_MSK (((1U << DSP2_MISC_REG_PIX_DATA_SHT_DIR_LEN) - 1) << DSP2_MISC_REG_PIX_DATA_SHT_DIR_POS) -#define DSP2_MISC_REG_PIX_DATA_SHT_DIR_UMSK (~(((1U << DSP2_MISC_REG_PIX_DATA_SHT_DIR_LEN) - 1) << DSP2_MISC_REG_PIX_DATA_SHT_DIR_POS)) -#define DSP2_MISC_REG_DSP2_DTSRC_SRC DSP2_MISC_REG_DSP2_DTSRC_SRC -#define DSP2_MISC_REG_DSP2_DTSRC_SRC_POS (31U) -#define DSP2_MISC_REG_DSP2_DTSRC_SRC_LEN (1U) -#define DSP2_MISC_REG_DSP2_DTSRC_SRC_MSK (((1U << DSP2_MISC_REG_DSP2_DTSRC_SRC_LEN) - 1) << DSP2_MISC_REG_DSP2_DTSRC_SRC_POS) -#define DSP2_MISC_REG_DSP2_DTSRC_SRC_UMSK (~(((1U << DSP2_MISC_REG_DSP2_DTSRC_SRC_LEN) - 1) << DSP2_MISC_REG_DSP2_DTSRC_SRC_POS)) - -/* 0x8 : dvp2bus_src_sel_1 */ -#define DSP2_MISC_DVP2BUS_SRC_SEL_1_OFFSET (0x8) -#define DSP2_MISC_RG_D2B_DVP_SEL_A DSP2_MISC_RG_D2B_DVP_SEL_A -#define DSP2_MISC_RG_D2B_DVP_SEL_A_POS (0U) -#define DSP2_MISC_RG_D2B_DVP_SEL_A_LEN (6U) -#define DSP2_MISC_RG_D2B_DVP_SEL_A_MSK (((1U << DSP2_MISC_RG_D2B_DVP_SEL_A_LEN) - 1) << DSP2_MISC_RG_D2B_DVP_SEL_A_POS) -#define DSP2_MISC_RG_D2B_DVP_SEL_A_UMSK (~(((1U << DSP2_MISC_RG_D2B_DVP_SEL_A_LEN) - 1) << DSP2_MISC_RG_D2B_DVP_SEL_A_POS)) -#define DSP2_MISC_RG_D2X_ID_SEL_A DSP2_MISC_RG_D2X_ID_SEL_A -#define DSP2_MISC_RG_D2X_ID_SEL_A_POS (7U) -#define DSP2_MISC_RG_D2X_ID_SEL_A_LEN (1U) -#define DSP2_MISC_RG_D2X_ID_SEL_A_MSK (((1U << DSP2_MISC_RG_D2X_ID_SEL_A_LEN) - 1) << DSP2_MISC_RG_D2X_ID_SEL_A_POS) -#define DSP2_MISC_RG_D2X_ID_SEL_A_UMSK (~(((1U << DSP2_MISC_RG_D2X_ID_SEL_A_LEN) - 1) << DSP2_MISC_RG_D2X_ID_SEL_A_POS)) -#define DSP2_MISC_RG_D2B_DVP_SEL_B DSP2_MISC_RG_D2B_DVP_SEL_B -#define DSP2_MISC_RG_D2B_DVP_SEL_B_POS (8U) -#define DSP2_MISC_RG_D2B_DVP_SEL_B_LEN (6U) -#define DSP2_MISC_RG_D2B_DVP_SEL_B_MSK (((1U << DSP2_MISC_RG_D2B_DVP_SEL_B_LEN) - 1) << DSP2_MISC_RG_D2B_DVP_SEL_B_POS) -#define DSP2_MISC_RG_D2B_DVP_SEL_B_UMSK (~(((1U << DSP2_MISC_RG_D2B_DVP_SEL_B_LEN) - 1) << DSP2_MISC_RG_D2B_DVP_SEL_B_POS)) -#define DSP2_MISC_RG_D2X_ID_SEL_B DSP2_MISC_RG_D2X_ID_SEL_B -#define DSP2_MISC_RG_D2X_ID_SEL_B_POS (15U) -#define DSP2_MISC_RG_D2X_ID_SEL_B_LEN (1U) -#define DSP2_MISC_RG_D2X_ID_SEL_B_MSK (((1U << DSP2_MISC_RG_D2X_ID_SEL_B_LEN) - 1) << DSP2_MISC_RG_D2X_ID_SEL_B_POS) -#define DSP2_MISC_RG_D2X_ID_SEL_B_UMSK (~(((1U << DSP2_MISC_RG_D2X_ID_SEL_B_LEN) - 1) << DSP2_MISC_RG_D2X_ID_SEL_B_POS)) -#define DSP2_MISC_RG_D2B_DVP_SEL_C DSP2_MISC_RG_D2B_DVP_SEL_C -#define DSP2_MISC_RG_D2B_DVP_SEL_C_POS (16U) -#define DSP2_MISC_RG_D2B_DVP_SEL_C_LEN (6U) -#define DSP2_MISC_RG_D2B_DVP_SEL_C_MSK (((1U << DSP2_MISC_RG_D2B_DVP_SEL_C_LEN) - 1) << DSP2_MISC_RG_D2B_DVP_SEL_C_POS) -#define DSP2_MISC_RG_D2B_DVP_SEL_C_UMSK (~(((1U << DSP2_MISC_RG_D2B_DVP_SEL_C_LEN) - 1) << DSP2_MISC_RG_D2B_DVP_SEL_C_POS)) -#define DSP2_MISC_RG_D2X_ID_SEL_C DSP2_MISC_RG_D2X_ID_SEL_C -#define DSP2_MISC_RG_D2X_ID_SEL_C_POS (23U) -#define DSP2_MISC_RG_D2X_ID_SEL_C_LEN (1U) -#define DSP2_MISC_RG_D2X_ID_SEL_C_MSK (((1U << DSP2_MISC_RG_D2X_ID_SEL_C_LEN) - 1) << DSP2_MISC_RG_D2X_ID_SEL_C_POS) -#define DSP2_MISC_RG_D2X_ID_SEL_C_UMSK (~(((1U << DSP2_MISC_RG_D2X_ID_SEL_C_LEN) - 1) << DSP2_MISC_RG_D2X_ID_SEL_C_POS)) -#define DSP2_MISC_RG_D2B_DVP_SEL_D DSP2_MISC_RG_D2B_DVP_SEL_D -#define DSP2_MISC_RG_D2B_DVP_SEL_D_POS (24U) -#define DSP2_MISC_RG_D2B_DVP_SEL_D_LEN (6U) -#define DSP2_MISC_RG_D2B_DVP_SEL_D_MSK (((1U << DSP2_MISC_RG_D2B_DVP_SEL_D_LEN) - 1) << DSP2_MISC_RG_D2B_DVP_SEL_D_POS) -#define DSP2_MISC_RG_D2B_DVP_SEL_D_UMSK (~(((1U << DSP2_MISC_RG_D2B_DVP_SEL_D_LEN) - 1) << DSP2_MISC_RG_D2B_DVP_SEL_D_POS)) -#define DSP2_MISC_RG_D2X_ID_SEL_D DSP2_MISC_RG_D2X_ID_SEL_D -#define DSP2_MISC_RG_D2X_ID_SEL_D_POS (31U) -#define DSP2_MISC_RG_D2X_ID_SEL_D_LEN (1U) -#define DSP2_MISC_RG_D2X_ID_SEL_D_MSK (((1U << DSP2_MISC_RG_D2X_ID_SEL_D_LEN) - 1) << DSP2_MISC_RG_D2X_ID_SEL_D_POS) -#define DSP2_MISC_RG_D2X_ID_SEL_D_UMSK (~(((1U << DSP2_MISC_RG_D2X_ID_SEL_D_LEN) - 1) << DSP2_MISC_RG_D2X_ID_SEL_D_POS)) - -/* 0xC : dvp_frame_m_to_n */ -#define DSP2_MISC_DVP_FRAME_M_TO_N_OFFSET (0xC) -#define DSP2_MISC_CR_FRAME_M_TO_N_EN DSP2_MISC_CR_FRAME_M_TO_N_EN -#define DSP2_MISC_CR_FRAME_M_TO_N_EN_POS (0U) -#define DSP2_MISC_CR_FRAME_M_TO_N_EN_LEN (1U) -#define DSP2_MISC_CR_FRAME_M_TO_N_EN_MSK (((1U << DSP2_MISC_CR_FRAME_M_TO_N_EN_LEN) - 1) << DSP2_MISC_CR_FRAME_M_TO_N_EN_POS) -#define DSP2_MISC_CR_FRAME_M_TO_N_EN_UMSK (~(((1U << DSP2_MISC_CR_FRAME_M_TO_N_EN_LEN) - 1) << DSP2_MISC_CR_FRAME_M_TO_N_EN_POS)) -#define DSP2_MISC_CR_FRAME_INTERVAL DSP2_MISC_CR_FRAME_INTERVAL -#define DSP2_MISC_CR_FRAME_INTERVAL_POS (4U) -#define DSP2_MISC_CR_FRAME_INTERVAL_LEN (4U) -#define DSP2_MISC_CR_FRAME_INTERVAL_MSK (((1U << DSP2_MISC_CR_FRAME_INTERVAL_LEN) - 1) << DSP2_MISC_CR_FRAME_INTERVAL_POS) -#define DSP2_MISC_CR_FRAME_INTERVAL_UMSK (~(((1U << DSP2_MISC_CR_FRAME_INTERVAL_LEN) - 1) << DSP2_MISC_CR_FRAME_INTERVAL_POS)) -#define DSP2_MISC_CR_FRAME_CNT_N DSP2_MISC_CR_FRAME_CNT_N -#define DSP2_MISC_CR_FRAME_CNT_N_POS (8U) -#define DSP2_MISC_CR_FRAME_CNT_N_LEN (4U) -#define DSP2_MISC_CR_FRAME_CNT_N_MSK (((1U << DSP2_MISC_CR_FRAME_CNT_N_LEN) - 1) << DSP2_MISC_CR_FRAME_CNT_N_POS) -#define DSP2_MISC_CR_FRAME_CNT_N_UMSK (~(((1U << DSP2_MISC_CR_FRAME_CNT_N_LEN) - 1) << DSP2_MISC_CR_FRAME_CNT_N_POS)) -#define DSP2_MISC_CR_FRAME_CNT_M DSP2_MISC_CR_FRAME_CNT_M -#define DSP2_MISC_CR_FRAME_CNT_M_POS (12U) -#define DSP2_MISC_CR_FRAME_CNT_M_LEN (4U) -#define DSP2_MISC_CR_FRAME_CNT_M_MSK (((1U << DSP2_MISC_CR_FRAME_CNT_M_LEN) - 1) << DSP2_MISC_CR_FRAME_CNT_M_POS) -#define DSP2_MISC_CR_FRAME_CNT_M_UMSK (~(((1U << DSP2_MISC_CR_FRAME_CNT_M_LEN) - 1) << DSP2_MISC_CR_FRAME_CNT_M_POS)) - -/* 0x10 : dsp2_id_bayer */ -#define DSP2_MISC_DSP2_ID_BAYER_OFFSET (0x10) -#define DSP2_MISC_REG_BAYER_IDGEN_RST DSP2_MISC_REG_BAYER_IDGEN_RST -#define DSP2_MISC_REG_BAYER_IDGEN_RST_POS (0U) -#define DSP2_MISC_REG_BAYER_IDGEN_RST_LEN (1U) -#define DSP2_MISC_REG_BAYER_IDGEN_RST_MSK (((1U << DSP2_MISC_REG_BAYER_IDGEN_RST_LEN) - 1) << DSP2_MISC_REG_BAYER_IDGEN_RST_POS) -#define DSP2_MISC_REG_BAYER_IDGEN_RST_UMSK (~(((1U << DSP2_MISC_REG_BAYER_IDGEN_RST_LEN) - 1) << DSP2_MISC_REG_BAYER_IDGEN_RST_POS)) -#define DSP2_MISC_REG_BAYER_IDGEN_EDGE DSP2_MISC_REG_BAYER_IDGEN_EDGE -#define DSP2_MISC_REG_BAYER_IDGEN_EDGE_POS (1U) -#define DSP2_MISC_REG_BAYER_IDGEN_EDGE_LEN (1U) -#define DSP2_MISC_REG_BAYER_IDGEN_EDGE_MSK (((1U << DSP2_MISC_REG_BAYER_IDGEN_EDGE_LEN) - 1) << DSP2_MISC_REG_BAYER_IDGEN_EDGE_POS) -#define DSP2_MISC_REG_BAYER_IDGEN_EDGE_UMSK (~(((1U << DSP2_MISC_REG_BAYER_IDGEN_EDGE_LEN) - 1) << DSP2_MISC_REG_BAYER_IDGEN_EDGE_POS)) -#define DSP2_MISC_REG_BAYER_IDGEN_CNT_INCR DSP2_MISC_REG_BAYER_IDGEN_CNT_INCR -#define DSP2_MISC_REG_BAYER_IDGEN_CNT_INCR_POS (16U) -#define DSP2_MISC_REG_BAYER_IDGEN_CNT_INCR_LEN (16U) -#define DSP2_MISC_REG_BAYER_IDGEN_CNT_INCR_MSK (((1U << DSP2_MISC_REG_BAYER_IDGEN_CNT_INCR_LEN) - 1) << DSP2_MISC_REG_BAYER_IDGEN_CNT_INCR_POS) -#define DSP2_MISC_REG_BAYER_IDGEN_CNT_INCR_UMSK (~(((1U << DSP2_MISC_REG_BAYER_IDGEN_CNT_INCR_LEN) - 1) << DSP2_MISC_REG_BAYER_IDGEN_CNT_INCR_POS)) - -/* 0x14 : dvp2bus_src_sel_2 */ -#define DSP2_MISC_DVP2BUS_SRC_SEL_2_OFFSET (0x14) -#define DSP2_MISC_RG_D2B_DVP_SEL_E DSP2_MISC_RG_D2B_DVP_SEL_E -#define DSP2_MISC_RG_D2B_DVP_SEL_E_POS (0U) -#define DSP2_MISC_RG_D2B_DVP_SEL_E_LEN (6U) -#define DSP2_MISC_RG_D2B_DVP_SEL_E_MSK (((1U << DSP2_MISC_RG_D2B_DVP_SEL_E_LEN) - 1) << DSP2_MISC_RG_D2B_DVP_SEL_E_POS) -#define DSP2_MISC_RG_D2B_DVP_SEL_E_UMSK (~(((1U << DSP2_MISC_RG_D2B_DVP_SEL_E_LEN) - 1) << DSP2_MISC_RG_D2B_DVP_SEL_E_POS)) -#define DSP2_MISC_RG_D2X_ID_SEL_E DSP2_MISC_RG_D2X_ID_SEL_E -#define DSP2_MISC_RG_D2X_ID_SEL_E_POS (7U) -#define DSP2_MISC_RG_D2X_ID_SEL_E_LEN (1U) -#define DSP2_MISC_RG_D2X_ID_SEL_E_MSK (((1U << DSP2_MISC_RG_D2X_ID_SEL_E_LEN) - 1) << DSP2_MISC_RG_D2X_ID_SEL_E_POS) -#define DSP2_MISC_RG_D2X_ID_SEL_E_UMSK (~(((1U << DSP2_MISC_RG_D2X_ID_SEL_E_LEN) - 1) << DSP2_MISC_RG_D2X_ID_SEL_E_POS)) -#define DSP2_MISC_RG_D2B_DVP_SEL_F DSP2_MISC_RG_D2B_DVP_SEL_F -#define DSP2_MISC_RG_D2B_DVP_SEL_F_POS (8U) -#define DSP2_MISC_RG_D2B_DVP_SEL_F_LEN (6U) -#define DSP2_MISC_RG_D2B_DVP_SEL_F_MSK (((1U << DSP2_MISC_RG_D2B_DVP_SEL_F_LEN) - 1) << DSP2_MISC_RG_D2B_DVP_SEL_F_POS) -#define DSP2_MISC_RG_D2B_DVP_SEL_F_UMSK (~(((1U << DSP2_MISC_RG_D2B_DVP_SEL_F_LEN) - 1) << DSP2_MISC_RG_D2B_DVP_SEL_F_POS)) -#define DSP2_MISC_RG_D2X_ID_SEL_F DSP2_MISC_RG_D2X_ID_SEL_F -#define DSP2_MISC_RG_D2X_ID_SEL_F_POS (15U) -#define DSP2_MISC_RG_D2X_ID_SEL_F_LEN (1U) -#define DSP2_MISC_RG_D2X_ID_SEL_F_MSK (((1U << DSP2_MISC_RG_D2X_ID_SEL_F_LEN) - 1) << DSP2_MISC_RG_D2X_ID_SEL_F_POS) -#define DSP2_MISC_RG_D2X_ID_SEL_F_UMSK (~(((1U << DSP2_MISC_RG_D2X_ID_SEL_F_LEN) - 1) << DSP2_MISC_RG_D2X_ID_SEL_F_POS)) -#define DSP2_MISC_RG_D2B_DVP_SEL_G DSP2_MISC_RG_D2B_DVP_SEL_G -#define DSP2_MISC_RG_D2B_DVP_SEL_G_POS (16U) -#define DSP2_MISC_RG_D2B_DVP_SEL_G_LEN (6U) -#define DSP2_MISC_RG_D2B_DVP_SEL_G_MSK (((1U << DSP2_MISC_RG_D2B_DVP_SEL_G_LEN) - 1) << DSP2_MISC_RG_D2B_DVP_SEL_G_POS) -#define DSP2_MISC_RG_D2B_DVP_SEL_G_UMSK (~(((1U << DSP2_MISC_RG_D2B_DVP_SEL_G_LEN) - 1) << DSP2_MISC_RG_D2B_DVP_SEL_G_POS)) -#define DSP2_MISC_RG_D2X_ID_SEL_G DSP2_MISC_RG_D2X_ID_SEL_G -#define DSP2_MISC_RG_D2X_ID_SEL_G_POS (23U) -#define DSP2_MISC_RG_D2X_ID_SEL_G_LEN (1U) -#define DSP2_MISC_RG_D2X_ID_SEL_G_MSK (((1U << DSP2_MISC_RG_D2X_ID_SEL_G_LEN) - 1) << DSP2_MISC_RG_D2X_ID_SEL_G_POS) -#define DSP2_MISC_RG_D2X_ID_SEL_G_UMSK (~(((1U << DSP2_MISC_RG_D2X_ID_SEL_G_LEN) - 1) << DSP2_MISC_RG_D2X_ID_SEL_G_POS)) -#define DSP2_MISC_RG_D2B_DVP_SEL_H DSP2_MISC_RG_D2B_DVP_SEL_H -#define DSP2_MISC_RG_D2B_DVP_SEL_H_POS (24U) -#define DSP2_MISC_RG_D2B_DVP_SEL_H_LEN (6U) -#define DSP2_MISC_RG_D2B_DVP_SEL_H_MSK (((1U << DSP2_MISC_RG_D2B_DVP_SEL_H_LEN) - 1) << DSP2_MISC_RG_D2B_DVP_SEL_H_POS) -#define DSP2_MISC_RG_D2B_DVP_SEL_H_UMSK (~(((1U << DSP2_MISC_RG_D2B_DVP_SEL_H_LEN) - 1) << DSP2_MISC_RG_D2B_DVP_SEL_H_POS)) -#define DSP2_MISC_RG_D2X_ID_SEL_H DSP2_MISC_RG_D2X_ID_SEL_H -#define DSP2_MISC_RG_D2X_ID_SEL_H_POS (31U) -#define DSP2_MISC_RG_D2X_ID_SEL_H_LEN (1U) -#define DSP2_MISC_RG_D2X_ID_SEL_H_MSK (((1U << DSP2_MISC_RG_D2X_ID_SEL_H_LEN) - 1) << DSP2_MISC_RG_D2X_ID_SEL_H_POS) -#define DSP2_MISC_RG_D2X_ID_SEL_H_UMSK (~(((1U << DSP2_MISC_RG_D2X_ID_SEL_H_LEN) - 1) << DSP2_MISC_RG_D2X_ID_SEL_H_POS)) - -/* 0x20 : int_clr */ -#define DSP2_MISC_INT_CLR_OFFSET (0x20) -#define DSP2_MISC_RG_AWB_INT_CLR DSP2_MISC_RG_AWB_INT_CLR -#define DSP2_MISC_RG_AWB_INT_CLR_POS (0U) -#define DSP2_MISC_RG_AWB_INT_CLR_LEN (1U) -#define DSP2_MISC_RG_AWB_INT_CLR_MSK (((1U << DSP2_MISC_RG_AWB_INT_CLR_LEN) - 1) << DSP2_MISC_RG_AWB_INT_CLR_POS) -#define DSP2_MISC_RG_AWB_INT_CLR_UMSK (~(((1U << DSP2_MISC_RG_AWB_INT_CLR_LEN) - 1) << DSP2_MISC_RG_AWB_INT_CLR_POS)) -#define DSP2_MISC_RG_AE_INT_CLR DSP2_MISC_RG_AE_INT_CLR -#define DSP2_MISC_RG_AE_INT_CLR_POS (1U) -#define DSP2_MISC_RG_AE_INT_CLR_LEN (1U) -#define DSP2_MISC_RG_AE_INT_CLR_MSK (((1U << DSP2_MISC_RG_AE_INT_CLR_LEN) - 1) << DSP2_MISC_RG_AE_INT_CLR_POS) -#define DSP2_MISC_RG_AE_INT_CLR_UMSK (~(((1U << DSP2_MISC_RG_AE_INT_CLR_LEN) - 1) << DSP2_MISC_RG_AE_INT_CLR_POS)) -#define DSP2_MISC_RG_WDR_INT_CLR DSP2_MISC_RG_WDR_INT_CLR -#define DSP2_MISC_RG_WDR_INT_CLR_POS (2U) -#define DSP2_MISC_RG_WDR_INT_CLR_LEN (1U) -#define DSP2_MISC_RG_WDR_INT_CLR_MSK (((1U << DSP2_MISC_RG_WDR_INT_CLR_LEN) - 1) << DSP2_MISC_RG_WDR_INT_CLR_POS) -#define DSP2_MISC_RG_WDR_INT_CLR_UMSK (~(((1U << DSP2_MISC_RG_WDR_INT_CLR_LEN) - 1) << DSP2_MISC_RG_WDR_INT_CLR_POS)) -#define DSP2_MISC_RG_AWB2_INT_CLR DSP2_MISC_RG_AWB2_INT_CLR -#define DSP2_MISC_RG_AWB2_INT_CLR_POS (3U) -#define DSP2_MISC_RG_AWB2_INT_CLR_LEN (1U) -#define DSP2_MISC_RG_AWB2_INT_CLR_MSK (((1U << DSP2_MISC_RG_AWB2_INT_CLR_LEN) - 1) << DSP2_MISC_RG_AWB2_INT_CLR_POS) -#define DSP2_MISC_RG_AWB2_INT_CLR_UMSK (~(((1U << DSP2_MISC_RG_AWB2_INT_CLR_LEN) - 1) << DSP2_MISC_RG_AWB2_INT_CLR_POS)) -#define DSP2_MISC_RG_OSD_PB_INT_CLR DSP2_MISC_RG_OSD_PB_INT_CLR -#define DSP2_MISC_RG_OSD_PB_INT_CLR_POS (4U) -#define DSP2_MISC_RG_OSD_PB_INT_CLR_LEN (1U) -#define DSP2_MISC_RG_OSD_PB_INT_CLR_MSK (((1U << DSP2_MISC_RG_OSD_PB_INT_CLR_LEN) - 1) << DSP2_MISC_RG_OSD_PB_INT_CLR_POS) -#define DSP2_MISC_RG_OSD_PB_INT_CLR_UMSK (~(((1U << DSP2_MISC_RG_OSD_PB_INT_CLR_LEN) - 1) << DSP2_MISC_RG_OSD_PB_INT_CLR_POS)) -#define DSP2_MISC_RG_SEOF1_INT_CLR DSP2_MISC_RG_SEOF1_INT_CLR -#define DSP2_MISC_RG_SEOF1_INT_CLR_POS (8U) -#define DSP2_MISC_RG_SEOF1_INT_CLR_LEN (1U) -#define DSP2_MISC_RG_SEOF1_INT_CLR_MSK (((1U << DSP2_MISC_RG_SEOF1_INT_CLR_LEN) - 1) << DSP2_MISC_RG_SEOF1_INT_CLR_POS) -#define DSP2_MISC_RG_SEOF1_INT_CLR_UMSK (~(((1U << DSP2_MISC_RG_SEOF1_INT_CLR_LEN) - 1) << DSP2_MISC_RG_SEOF1_INT_CLR_POS)) -#define DSP2_MISC_RG_SEOF2_INT_CLR DSP2_MISC_RG_SEOF2_INT_CLR -#define DSP2_MISC_RG_SEOF2_INT_CLR_POS (9U) -#define DSP2_MISC_RG_SEOF2_INT_CLR_LEN (1U) -#define DSP2_MISC_RG_SEOF2_INT_CLR_MSK (((1U << DSP2_MISC_RG_SEOF2_INT_CLR_LEN) - 1) << DSP2_MISC_RG_SEOF2_INT_CLR_POS) -#define DSP2_MISC_RG_SEOF2_INT_CLR_UMSK (~(((1U << DSP2_MISC_RG_SEOF2_INT_CLR_LEN) - 1) << DSP2_MISC_RG_SEOF2_INT_CLR_POS)) -#define DSP2_MISC_RG_SEOF3_INT_CLR DSP2_MISC_RG_SEOF3_INT_CLR -#define DSP2_MISC_RG_SEOF3_INT_CLR_POS (10U) -#define DSP2_MISC_RG_SEOF3_INT_CLR_LEN (1U) -#define DSP2_MISC_RG_SEOF3_INT_CLR_MSK (((1U << DSP2_MISC_RG_SEOF3_INT_CLR_LEN) - 1) << DSP2_MISC_RG_SEOF3_INT_CLR_POS) -#define DSP2_MISC_RG_SEOF3_INT_CLR_UMSK (~(((1U << DSP2_MISC_RG_SEOF3_INT_CLR_LEN) - 1) << DSP2_MISC_RG_SEOF3_INT_CLR_POS)) -#define DSP2_MISC_RG_AE_HIST_INT_CLR DSP2_MISC_RG_AE_HIST_INT_CLR -#define DSP2_MISC_RG_AE_HIST_INT_CLR_POS (11U) -#define DSP2_MISC_RG_AE_HIST_INT_CLR_LEN (1U) -#define DSP2_MISC_RG_AE_HIST_INT_CLR_MSK (((1U << DSP2_MISC_RG_AE_HIST_INT_CLR_LEN) - 1) << DSP2_MISC_RG_AE_HIST_INT_CLR_POS) -#define DSP2_MISC_RG_AE_HIST_INT_CLR_UMSK (~(((1U << DSP2_MISC_RG_AE_HIST_INT_CLR_LEN) - 1) << DSP2_MISC_RG_AE_HIST_INT_CLR_POS)) -#define DSP2_MISC_RG_AWB3_INT_CLR DSP2_MISC_RG_AWB3_INT_CLR -#define DSP2_MISC_RG_AWB3_INT_CLR_POS (12U) -#define DSP2_MISC_RG_AWB3_INT_CLR_LEN (1U) -#define DSP2_MISC_RG_AWB3_INT_CLR_MSK (((1U << DSP2_MISC_RG_AWB3_INT_CLR_LEN) - 1) << DSP2_MISC_RG_AWB3_INT_CLR_POS) -#define DSP2_MISC_RG_AWB3_INT_CLR_UMSK (~(((1U << DSP2_MISC_RG_AWB3_INT_CLR_LEN) - 1) << DSP2_MISC_RG_AWB3_INT_CLR_POS)) -#define DSP2_MISC_RG_DP_SEOF0_INT_CLR DSP2_MISC_RG_DP_SEOF0_INT_CLR -#define DSP2_MISC_RG_DP_SEOF0_INT_CLR_POS (13U) -#define DSP2_MISC_RG_DP_SEOF0_INT_CLR_LEN (1U) -#define DSP2_MISC_RG_DP_SEOF0_INT_CLR_MSK (((1U << DSP2_MISC_RG_DP_SEOF0_INT_CLR_LEN) - 1) << DSP2_MISC_RG_DP_SEOF0_INT_CLR_POS) -#define DSP2_MISC_RG_DP_SEOF0_INT_CLR_UMSK (~(((1U << DSP2_MISC_RG_DP_SEOF0_INT_CLR_LEN) - 1) << DSP2_MISC_RG_DP_SEOF0_INT_CLR_POS)) -#define DSP2_MISC_RG_SEOF4_INT_CLR DSP2_MISC_RG_SEOF4_INT_CLR -#define DSP2_MISC_RG_SEOF4_INT_CLR_POS (14U) -#define DSP2_MISC_RG_SEOF4_INT_CLR_LEN (1U) -#define DSP2_MISC_RG_SEOF4_INT_CLR_MSK (((1U << DSP2_MISC_RG_SEOF4_INT_CLR_LEN) - 1) << DSP2_MISC_RG_SEOF4_INT_CLR_POS) -#define DSP2_MISC_RG_SEOF4_INT_CLR_UMSK (~(((1U << DSP2_MISC_RG_SEOF4_INT_CLR_LEN) - 1) << DSP2_MISC_RG_SEOF4_INT_CLR_POS)) - -/* 0x24 : int_ctrl */ -#define DSP2_MISC_INT_CTRL_OFFSET (0x24) -#define DSP2_MISC_RG_AE_INT_MASK DSP2_MISC_RG_AE_INT_MASK -#define DSP2_MISC_RG_AE_INT_MASK_POS (0U) -#define DSP2_MISC_RG_AE_INT_MASK_LEN (1U) -#define DSP2_MISC_RG_AE_INT_MASK_MSK (((1U << DSP2_MISC_RG_AE_INT_MASK_LEN) - 1) << DSP2_MISC_RG_AE_INT_MASK_POS) -#define DSP2_MISC_RG_AE_INT_MASK_UMSK (~(((1U << DSP2_MISC_RG_AE_INT_MASK_LEN) - 1) << DSP2_MISC_RG_AE_INT_MASK_POS)) -#define DSP2_MISC_RG_AWB_INT_MASK DSP2_MISC_RG_AWB_INT_MASK -#define DSP2_MISC_RG_AWB_INT_MASK_POS (1U) -#define DSP2_MISC_RG_AWB_INT_MASK_LEN (1U) -#define DSP2_MISC_RG_AWB_INT_MASK_MSK (((1U << DSP2_MISC_RG_AWB_INT_MASK_LEN) - 1) << DSP2_MISC_RG_AWB_INT_MASK_POS) -#define DSP2_MISC_RG_AWB_INT_MASK_UMSK (~(((1U << DSP2_MISC_RG_AWB_INT_MASK_LEN) - 1) << DSP2_MISC_RG_AWB_INT_MASK_POS)) -#define DSP2_MISC_RG_WDR_INT_MASK DSP2_MISC_RG_WDR_INT_MASK -#define DSP2_MISC_RG_WDR_INT_MASK_POS (2U) -#define DSP2_MISC_RG_WDR_INT_MASK_LEN (1U) -#define DSP2_MISC_RG_WDR_INT_MASK_MSK (((1U << DSP2_MISC_RG_WDR_INT_MASK_LEN) - 1) << DSP2_MISC_RG_WDR_INT_MASK_POS) -#define DSP2_MISC_RG_WDR_INT_MASK_UMSK (~(((1U << DSP2_MISC_RG_WDR_INT_MASK_LEN) - 1) << DSP2_MISC_RG_WDR_INT_MASK_POS)) -#define DSP2_MISC_RG_AWB2_INT_MASK DSP2_MISC_RG_AWB2_INT_MASK -#define DSP2_MISC_RG_AWB2_INT_MASK_POS (3U) -#define DSP2_MISC_RG_AWB2_INT_MASK_LEN (1U) -#define DSP2_MISC_RG_AWB2_INT_MASK_MSK (((1U << DSP2_MISC_RG_AWB2_INT_MASK_LEN) - 1) << DSP2_MISC_RG_AWB2_INT_MASK_POS) -#define DSP2_MISC_RG_AWB2_INT_MASK_UMSK (~(((1U << DSP2_MISC_RG_AWB2_INT_MASK_LEN) - 1) << DSP2_MISC_RG_AWB2_INT_MASK_POS)) -#define DSP2_MISC_RG_OSD_PB_INT_MASK DSP2_MISC_RG_OSD_PB_INT_MASK -#define DSP2_MISC_RG_OSD_PB_INT_MASK_POS (4U) -#define DSP2_MISC_RG_OSD_PB_INT_MASK_LEN (1U) -#define DSP2_MISC_RG_OSD_PB_INT_MASK_MSK (((1U << DSP2_MISC_RG_OSD_PB_INT_MASK_LEN) - 1) << DSP2_MISC_RG_OSD_PB_INT_MASK_POS) -#define DSP2_MISC_RG_OSD_PB_INT_MASK_UMSK (~(((1U << DSP2_MISC_RG_OSD_PB_INT_MASK_LEN) - 1) << DSP2_MISC_RG_OSD_PB_INT_MASK_POS)) -#define DSP2_MISC_RG_SEOF1_INT_MASK DSP2_MISC_RG_SEOF1_INT_MASK -#define DSP2_MISC_RG_SEOF1_INT_MASK_POS (8U) -#define DSP2_MISC_RG_SEOF1_INT_MASK_LEN (1U) -#define DSP2_MISC_RG_SEOF1_INT_MASK_MSK (((1U << DSP2_MISC_RG_SEOF1_INT_MASK_LEN) - 1) << DSP2_MISC_RG_SEOF1_INT_MASK_POS) -#define DSP2_MISC_RG_SEOF1_INT_MASK_UMSK (~(((1U << DSP2_MISC_RG_SEOF1_INT_MASK_LEN) - 1) << DSP2_MISC_RG_SEOF1_INT_MASK_POS)) -#define DSP2_MISC_RG_SEOF1_INT_EDGE DSP2_MISC_RG_SEOF1_INT_EDGE -#define DSP2_MISC_RG_SEOF1_INT_EDGE_POS (9U) -#define DSP2_MISC_RG_SEOF1_INT_EDGE_LEN (1U) -#define DSP2_MISC_RG_SEOF1_INT_EDGE_MSK (((1U << DSP2_MISC_RG_SEOF1_INT_EDGE_LEN) - 1) << DSP2_MISC_RG_SEOF1_INT_EDGE_POS) -#define DSP2_MISC_RG_SEOF1_INT_EDGE_UMSK (~(((1U << DSP2_MISC_RG_SEOF1_INT_EDGE_LEN) - 1) << DSP2_MISC_RG_SEOF1_INT_EDGE_POS)) -#define DSP2_MISC_RG_SEOF1_INT_SRC DSP2_MISC_RG_SEOF1_INT_SRC -#define DSP2_MISC_RG_SEOF1_INT_SRC_POS (10U) -#define DSP2_MISC_RG_SEOF1_INT_SRC_LEN (2U) -#define DSP2_MISC_RG_SEOF1_INT_SRC_MSK (((1U << DSP2_MISC_RG_SEOF1_INT_SRC_LEN) - 1) << DSP2_MISC_RG_SEOF1_INT_SRC_POS) -#define DSP2_MISC_RG_SEOF1_INT_SRC_UMSK (~(((1U << DSP2_MISC_RG_SEOF1_INT_SRC_LEN) - 1) << DSP2_MISC_RG_SEOF1_INT_SRC_POS)) -#define DSP2_MISC_RG_SEOF2_INT_MASK DSP2_MISC_RG_SEOF2_INT_MASK -#define DSP2_MISC_RG_SEOF2_INT_MASK_POS (12U) -#define DSP2_MISC_RG_SEOF2_INT_MASK_LEN (1U) -#define DSP2_MISC_RG_SEOF2_INT_MASK_MSK (((1U << DSP2_MISC_RG_SEOF2_INT_MASK_LEN) - 1) << DSP2_MISC_RG_SEOF2_INT_MASK_POS) -#define DSP2_MISC_RG_SEOF2_INT_MASK_UMSK (~(((1U << DSP2_MISC_RG_SEOF2_INT_MASK_LEN) - 1) << DSP2_MISC_RG_SEOF2_INT_MASK_POS)) -#define DSP2_MISC_RG_SEOF2_INT_EDGE DSP2_MISC_RG_SEOF2_INT_EDGE -#define DSP2_MISC_RG_SEOF2_INT_EDGE_POS (13U) -#define DSP2_MISC_RG_SEOF2_INT_EDGE_LEN (1U) -#define DSP2_MISC_RG_SEOF2_INT_EDGE_MSK (((1U << DSP2_MISC_RG_SEOF2_INT_EDGE_LEN) - 1) << DSP2_MISC_RG_SEOF2_INT_EDGE_POS) -#define DSP2_MISC_RG_SEOF2_INT_EDGE_UMSK (~(((1U << DSP2_MISC_RG_SEOF2_INT_EDGE_LEN) - 1) << DSP2_MISC_RG_SEOF2_INT_EDGE_POS)) -#define DSP2_MISC_RG_SEOF2_INT_SRC DSP2_MISC_RG_SEOF2_INT_SRC -#define DSP2_MISC_RG_SEOF2_INT_SRC_POS (14U) -#define DSP2_MISC_RG_SEOF2_INT_SRC_LEN (2U) -#define DSP2_MISC_RG_SEOF2_INT_SRC_MSK (((1U << DSP2_MISC_RG_SEOF2_INT_SRC_LEN) - 1) << DSP2_MISC_RG_SEOF2_INT_SRC_POS) -#define DSP2_MISC_RG_SEOF2_INT_SRC_UMSK (~(((1U << DSP2_MISC_RG_SEOF2_INT_SRC_LEN) - 1) << DSP2_MISC_RG_SEOF2_INT_SRC_POS)) -#define DSP2_MISC_RG_SEOF3_INT_MASK DSP2_MISC_RG_SEOF3_INT_MASK -#define DSP2_MISC_RG_SEOF3_INT_MASK_POS (16U) -#define DSP2_MISC_RG_SEOF3_INT_MASK_LEN (1U) -#define DSP2_MISC_RG_SEOF3_INT_MASK_MSK (((1U << DSP2_MISC_RG_SEOF3_INT_MASK_LEN) - 1) << DSP2_MISC_RG_SEOF3_INT_MASK_POS) -#define DSP2_MISC_RG_SEOF3_INT_MASK_UMSK (~(((1U << DSP2_MISC_RG_SEOF3_INT_MASK_LEN) - 1) << DSP2_MISC_RG_SEOF3_INT_MASK_POS)) -#define DSP2_MISC_RG_SEOF3_INT_EDGE DSP2_MISC_RG_SEOF3_INT_EDGE -#define DSP2_MISC_RG_SEOF3_INT_EDGE_POS (17U) -#define DSP2_MISC_RG_SEOF3_INT_EDGE_LEN (1U) -#define DSP2_MISC_RG_SEOF3_INT_EDGE_MSK (((1U << DSP2_MISC_RG_SEOF3_INT_EDGE_LEN) - 1) << DSP2_MISC_RG_SEOF3_INT_EDGE_POS) -#define DSP2_MISC_RG_SEOF3_INT_EDGE_UMSK (~(((1U << DSP2_MISC_RG_SEOF3_INT_EDGE_LEN) - 1) << DSP2_MISC_RG_SEOF3_INT_EDGE_POS)) -#define DSP2_MISC_RG_SEOF3_INT_SRC DSP2_MISC_RG_SEOF3_INT_SRC -#define DSP2_MISC_RG_SEOF3_INT_SRC_POS (18U) -#define DSP2_MISC_RG_SEOF3_INT_SRC_LEN (2U) -#define DSP2_MISC_RG_SEOF3_INT_SRC_MSK (((1U << DSP2_MISC_RG_SEOF3_INT_SRC_LEN) - 1) << DSP2_MISC_RG_SEOF3_INT_SRC_POS) -#define DSP2_MISC_RG_SEOF3_INT_SRC_UMSK (~(((1U << DSP2_MISC_RG_SEOF3_INT_SRC_LEN) - 1) << DSP2_MISC_RG_SEOF3_INT_SRC_POS)) -#define DSP2_MISC_RG_AE_HIST_INT_MASK DSP2_MISC_RG_AE_HIST_INT_MASK -#define DSP2_MISC_RG_AE_HIST_INT_MASK_POS (20U) -#define DSP2_MISC_RG_AE_HIST_INT_MASK_LEN (1U) -#define DSP2_MISC_RG_AE_HIST_INT_MASK_MSK (((1U << DSP2_MISC_RG_AE_HIST_INT_MASK_LEN) - 1) << DSP2_MISC_RG_AE_HIST_INT_MASK_POS) -#define DSP2_MISC_RG_AE_HIST_INT_MASK_UMSK (~(((1U << DSP2_MISC_RG_AE_HIST_INT_MASK_LEN) - 1) << DSP2_MISC_RG_AE_HIST_INT_MASK_POS)) -#define DSP2_MISC_RG_AWB3_INT_MASK DSP2_MISC_RG_AWB3_INT_MASK -#define DSP2_MISC_RG_AWB3_INT_MASK_POS (21U) -#define DSP2_MISC_RG_AWB3_INT_MASK_LEN (1U) -#define DSP2_MISC_RG_AWB3_INT_MASK_MSK (((1U << DSP2_MISC_RG_AWB3_INT_MASK_LEN) - 1) << DSP2_MISC_RG_AWB3_INT_MASK_POS) -#define DSP2_MISC_RG_AWB3_INT_MASK_UMSK (~(((1U << DSP2_MISC_RG_AWB3_INT_MASK_LEN) - 1) << DSP2_MISC_RG_AWB3_INT_MASK_POS)) -#define DSP2_MISC_RG_DP_SEOF0_INT_SRC DSP2_MISC_RG_DP_SEOF0_INT_SRC -#define DSP2_MISC_RG_DP_SEOF0_INT_SRC_POS (22U) -#define DSP2_MISC_RG_DP_SEOF0_INT_SRC_LEN (1U) -#define DSP2_MISC_RG_DP_SEOF0_INT_SRC_MSK (((1U << DSP2_MISC_RG_DP_SEOF0_INT_SRC_LEN) - 1) << DSP2_MISC_RG_DP_SEOF0_INT_SRC_POS) -#define DSP2_MISC_RG_DP_SEOF0_INT_SRC_UMSK (~(((1U << DSP2_MISC_RG_DP_SEOF0_INT_SRC_LEN) - 1) << DSP2_MISC_RG_DP_SEOF0_INT_SRC_POS)) -#define DSP2_MISC_RG_DP_SEOF0_INT_EDGE DSP2_MISC_RG_DP_SEOF0_INT_EDGE -#define DSP2_MISC_RG_DP_SEOF0_INT_EDGE_POS (23U) -#define DSP2_MISC_RG_DP_SEOF0_INT_EDGE_LEN (1U) -#define DSP2_MISC_RG_DP_SEOF0_INT_EDGE_MSK (((1U << DSP2_MISC_RG_DP_SEOF0_INT_EDGE_LEN) - 1) << DSP2_MISC_RG_DP_SEOF0_INT_EDGE_POS) -#define DSP2_MISC_RG_DP_SEOF0_INT_EDGE_UMSK (~(((1U << DSP2_MISC_RG_DP_SEOF0_INT_EDGE_LEN) - 1) << DSP2_MISC_RG_DP_SEOF0_INT_EDGE_POS)) -#define DSP2_MISC_RG_DP_SEOF0_INT_MASK DSP2_MISC_RG_DP_SEOF0_INT_MASK -#define DSP2_MISC_RG_DP_SEOF0_INT_MASK_POS (24U) -#define DSP2_MISC_RG_DP_SEOF0_INT_MASK_LEN (1U) -#define DSP2_MISC_RG_DP_SEOF0_INT_MASK_MSK (((1U << DSP2_MISC_RG_DP_SEOF0_INT_MASK_LEN) - 1) << DSP2_MISC_RG_DP_SEOF0_INT_MASK_POS) -#define DSP2_MISC_RG_DP_SEOF0_INT_MASK_UMSK (~(((1U << DSP2_MISC_RG_DP_SEOF0_INT_MASK_LEN) - 1) << DSP2_MISC_RG_DP_SEOF0_INT_MASK_POS)) -#define DSP2_MISC_RG_SEOF4_INT_MASK DSP2_MISC_RG_SEOF4_INT_MASK -#define DSP2_MISC_RG_SEOF4_INT_MASK_POS (28U) -#define DSP2_MISC_RG_SEOF4_INT_MASK_LEN (1U) -#define DSP2_MISC_RG_SEOF4_INT_MASK_MSK (((1U << DSP2_MISC_RG_SEOF4_INT_MASK_LEN) - 1) << DSP2_MISC_RG_SEOF4_INT_MASK_POS) -#define DSP2_MISC_RG_SEOF4_INT_MASK_UMSK (~(((1U << DSP2_MISC_RG_SEOF4_INT_MASK_LEN) - 1) << DSP2_MISC_RG_SEOF4_INT_MASK_POS)) -#define DSP2_MISC_RG_SEOF4_INT_EDGE DSP2_MISC_RG_SEOF4_INT_EDGE -#define DSP2_MISC_RG_SEOF4_INT_EDGE_POS (29U) -#define DSP2_MISC_RG_SEOF4_INT_EDGE_LEN (1U) -#define DSP2_MISC_RG_SEOF4_INT_EDGE_MSK (((1U << DSP2_MISC_RG_SEOF4_INT_EDGE_LEN) - 1) << DSP2_MISC_RG_SEOF4_INT_EDGE_POS) -#define DSP2_MISC_RG_SEOF4_INT_EDGE_UMSK (~(((1U << DSP2_MISC_RG_SEOF4_INT_EDGE_LEN) - 1) << DSP2_MISC_RG_SEOF4_INT_EDGE_POS)) -#define DSP2_MISC_RG_SEOF4_INT_SRC DSP2_MISC_RG_SEOF4_INT_SRC -#define DSP2_MISC_RG_SEOF4_INT_SRC_POS (30U) -#define DSP2_MISC_RG_SEOF4_INT_SRC_LEN (2U) -#define DSP2_MISC_RG_SEOF4_INT_SRC_MSK (((1U << DSP2_MISC_RG_SEOF4_INT_SRC_LEN) - 1) << DSP2_MISC_RG_SEOF4_INT_SRC_POS) -#define DSP2_MISC_RG_SEOF4_INT_SRC_UMSK (~(((1U << DSP2_MISC_RG_SEOF4_INT_SRC_LEN) - 1) << DSP2_MISC_RG_SEOF4_INT_SRC_POS)) - -/* 0x28 : dsp2_id_yuv */ -#define DSP2_MISC_DSP2_ID_YUV_OFFSET (0x28) -#define DSP2_MISC_REG_YUV_IDGEN_RST DSP2_MISC_REG_YUV_IDGEN_RST -#define DSP2_MISC_REG_YUV_IDGEN_RST_POS (0U) -#define DSP2_MISC_REG_YUV_IDGEN_RST_LEN (1U) -#define DSP2_MISC_REG_YUV_IDGEN_RST_MSK (((1U << DSP2_MISC_REG_YUV_IDGEN_RST_LEN) - 1) << DSP2_MISC_REG_YUV_IDGEN_RST_POS) -#define DSP2_MISC_REG_YUV_IDGEN_RST_UMSK (~(((1U << DSP2_MISC_REG_YUV_IDGEN_RST_LEN) - 1) << DSP2_MISC_REG_YUV_IDGEN_RST_POS)) -#define DSP2_MISC_REG_YUV_IDGEN_EDGE DSP2_MISC_REG_YUV_IDGEN_EDGE -#define DSP2_MISC_REG_YUV_IDGEN_EDGE_POS (1U) -#define DSP2_MISC_REG_YUV_IDGEN_EDGE_LEN (1U) -#define DSP2_MISC_REG_YUV_IDGEN_EDGE_MSK (((1U << DSP2_MISC_REG_YUV_IDGEN_EDGE_LEN) - 1) << DSP2_MISC_REG_YUV_IDGEN_EDGE_POS) -#define DSP2_MISC_REG_YUV_IDGEN_EDGE_UMSK (~(((1U << DSP2_MISC_REG_YUV_IDGEN_EDGE_LEN) - 1) << DSP2_MISC_REG_YUV_IDGEN_EDGE_POS)) -#define DSP2_MISC_REG_YUV_IDGEN_CNT_INCR DSP2_MISC_REG_YUV_IDGEN_CNT_INCR -#define DSP2_MISC_REG_YUV_IDGEN_CNT_INCR_POS (16U) -#define DSP2_MISC_REG_YUV_IDGEN_CNT_INCR_LEN (16U) -#define DSP2_MISC_REG_YUV_IDGEN_CNT_INCR_MSK (((1U << DSP2_MISC_REG_YUV_IDGEN_CNT_INCR_LEN) - 1) << DSP2_MISC_REG_YUV_IDGEN_CNT_INCR_POS) -#define DSP2_MISC_REG_YUV_IDGEN_CNT_INCR_UMSK (~(((1U << DSP2_MISC_REG_YUV_IDGEN_CNT_INCR_LEN) - 1) << DSP2_MISC_REG_YUV_IDGEN_CNT_INCR_POS)) - -/* 0x2C : dvp_reshape */ -#define DSP2_MISC_DVP_RESHAPE_OFFSET (0x2C) -#define DSP2_MISC_REG_RSHP_TGL_COUNT DSP2_MISC_REG_RSHP_TGL_COUNT -#define DSP2_MISC_REG_RSHP_TGL_COUNT_POS (0U) -#define DSP2_MISC_REG_RSHP_TGL_COUNT_LEN (5U) -#define DSP2_MISC_REG_RSHP_TGL_COUNT_MSK (((1U << DSP2_MISC_REG_RSHP_TGL_COUNT_LEN) - 1) << DSP2_MISC_REG_RSHP_TGL_COUNT_POS) -#define DSP2_MISC_REG_RSHP_TGL_COUNT_UMSK (~(((1U << DSP2_MISC_REG_RSHP_TGL_COUNT_LEN) - 1) << DSP2_MISC_REG_RSHP_TGL_COUNT_POS)) -#define DSP2_MISC_REG_RSHP_HSYNC_INV DSP2_MISC_REG_RSHP_HSYNC_INV -#define DSP2_MISC_REG_RSHP_HSYNC_INV_POS (5U) -#define DSP2_MISC_REG_RSHP_HSYNC_INV_LEN (1U) -#define DSP2_MISC_REG_RSHP_HSYNC_INV_MSK (((1U << DSP2_MISC_REG_RSHP_HSYNC_INV_LEN) - 1) << DSP2_MISC_REG_RSHP_HSYNC_INV_POS) -#define DSP2_MISC_REG_RSHP_HSYNC_INV_UMSK (~(((1U << DSP2_MISC_REG_RSHP_HSYNC_INV_LEN) - 1) << DSP2_MISC_REG_RSHP_HSYNC_INV_POS)) -#define DSP2_MISC_REG_RSHP_VSYNC_INV DSP2_MISC_REG_RSHP_VSYNC_INV -#define DSP2_MISC_REG_RSHP_VSYNC_INV_POS (6U) -#define DSP2_MISC_REG_RSHP_VSYNC_INV_LEN (1U) -#define DSP2_MISC_REG_RSHP_VSYNC_INV_MSK (((1U << DSP2_MISC_REG_RSHP_VSYNC_INV_LEN) - 1) << DSP2_MISC_REG_RSHP_VSYNC_INV_POS) -#define DSP2_MISC_REG_RSHP_VSYNC_INV_UMSK (~(((1U << DSP2_MISC_REG_RSHP_VSYNC_INV_LEN) - 1) << DSP2_MISC_REG_RSHP_VSYNC_INV_POS)) -#define DSP2_MISC_REG_RSHP_CLR DSP2_MISC_REG_RSHP_CLR -#define DSP2_MISC_REG_RSHP_CLR_POS (7U) -#define DSP2_MISC_REG_RSHP_CLR_LEN (1U) -#define DSP2_MISC_REG_RSHP_CLR_MSK (((1U << DSP2_MISC_REG_RSHP_CLR_LEN) - 1) << DSP2_MISC_REG_RSHP_CLR_POS) -#define DSP2_MISC_REG_RSHP_CLR_UMSK (~(((1U << DSP2_MISC_REG_RSHP_CLR_LEN) - 1) << DSP2_MISC_REG_RSHP_CLR_POS)) -#define DSP2_MISC_REG_RSHP_EN DSP2_MISC_REG_RSHP_EN -#define DSP2_MISC_REG_RSHP_EN_POS (8U) -#define DSP2_MISC_REG_RSHP_EN_LEN (1U) -#define DSP2_MISC_REG_RSHP_EN_MSK (((1U << DSP2_MISC_REG_RSHP_EN_LEN) - 1) << DSP2_MISC_REG_RSHP_EN_POS) -#define DSP2_MISC_REG_RSHP_EN_UMSK (~(((1U << DSP2_MISC_REG_RSHP_EN_LEN) - 1) << DSP2_MISC_REG_RSHP_EN_POS)) - -/* 0x40 : scalerA_i_size */ -#define DSP2_MISC_SCALERA_I_SIZE_OFFSET (0x40) -#define DSP2_MISC_RG_SCALERA_I_W DSP2_MISC_RG_SCALERA_I_W -#define DSP2_MISC_RG_SCALERA_I_W_POS (0U) -#define DSP2_MISC_RG_SCALERA_I_W_LEN (11U) -#define DSP2_MISC_RG_SCALERA_I_W_MSK (((1U << DSP2_MISC_RG_SCALERA_I_W_LEN) - 1) << DSP2_MISC_RG_SCALERA_I_W_POS) -#define DSP2_MISC_RG_SCALERA_I_W_UMSK (~(((1U << DSP2_MISC_RG_SCALERA_I_W_LEN) - 1) << DSP2_MISC_RG_SCALERA_I_W_POS)) -#define DSP2_MISC_RG_SCALERA_I_H DSP2_MISC_RG_SCALERA_I_H -#define DSP2_MISC_RG_SCALERA_I_H_POS (16U) -#define DSP2_MISC_RG_SCALERA_I_H_LEN (11U) -#define DSP2_MISC_RG_SCALERA_I_H_MSK (((1U << DSP2_MISC_RG_SCALERA_I_H_LEN) - 1) << DSP2_MISC_RG_SCALERA_I_H_POS) -#define DSP2_MISC_RG_SCALERA_I_H_UMSK (~(((1U << DSP2_MISC_RG_SCALERA_I_H_LEN) - 1) << DSP2_MISC_RG_SCALERA_I_H_POS)) -#define DSP2_MISC_RG_SCLRA_SW_SH DSP2_MISC_RG_SCLRA_SW_SH -#define DSP2_MISC_RG_SCLRA_SW_SH_POS (27U) -#define DSP2_MISC_RG_SCLRA_SW_SH_LEN (1U) -#define DSP2_MISC_RG_SCLRA_SW_SH_MSK (((1U << DSP2_MISC_RG_SCLRA_SW_SH_LEN) - 1) << DSP2_MISC_RG_SCLRA_SW_SH_POS) -#define DSP2_MISC_RG_SCLRA_SW_SH_UMSK (~(((1U << DSP2_MISC_RG_SCLRA_SW_SH_LEN) - 1) << DSP2_MISC_RG_SCLRA_SW_SH_POS)) -#define DSP2_MISC_RG_SCALERA_BYPASS DSP2_MISC_RG_SCALERA_BYPASS -#define DSP2_MISC_RG_SCALERA_BYPASS_POS (28U) -#define DSP2_MISC_RG_SCALERA_BYPASS_LEN (1U) -#define DSP2_MISC_RG_SCALERA_BYPASS_MSK (((1U << DSP2_MISC_RG_SCALERA_BYPASS_LEN) - 1) << DSP2_MISC_RG_SCALERA_BYPASS_POS) -#define DSP2_MISC_RG_SCALERA_BYPASS_UMSK (~(((1U << DSP2_MISC_RG_SCALERA_BYPASS_LEN) - 1) << DSP2_MISC_RG_SCALERA_BYPASS_POS)) -#define DSP2_MISC_RG_SCALERA_SEL DSP2_MISC_RG_SCALERA_SEL -#define DSP2_MISC_RG_SCALERA_SEL_POS (29U) -#define DSP2_MISC_RG_SCALERA_SEL_LEN (3U) -#define DSP2_MISC_RG_SCALERA_SEL_MSK (((1U << DSP2_MISC_RG_SCALERA_SEL_LEN) - 1) << DSP2_MISC_RG_SCALERA_SEL_POS) -#define DSP2_MISC_RG_SCALERA_SEL_UMSK (~(((1U << DSP2_MISC_RG_SCALERA_SEL_LEN) - 1) << DSP2_MISC_RG_SCALERA_SEL_POS)) - -/* 0x44 : scalerA_o_size */ -#define DSP2_MISC_SCALERA_O_SIZE_OFFSET (0x44) -#define DSP2_MISC_RG_SCALERA_O_W DSP2_MISC_RG_SCALERA_O_W -#define DSP2_MISC_RG_SCALERA_O_W_POS (0U) -#define DSP2_MISC_RG_SCALERA_O_W_LEN (11U) -#define DSP2_MISC_RG_SCALERA_O_W_MSK (((1U << DSP2_MISC_RG_SCALERA_O_W_LEN) - 1) << DSP2_MISC_RG_SCALERA_O_W_POS) -#define DSP2_MISC_RG_SCALERA_O_W_UMSK (~(((1U << DSP2_MISC_RG_SCALERA_O_W_LEN) - 1) << DSP2_MISC_RG_SCALERA_O_W_POS)) -#define DSP2_MISC_RG_SCALERA_O_H DSP2_MISC_RG_SCALERA_O_H -#define DSP2_MISC_RG_SCALERA_O_H_POS (16U) -#define DSP2_MISC_RG_SCALERA_O_H_LEN (11U) -#define DSP2_MISC_RG_SCALERA_O_H_MSK (((1U << DSP2_MISC_RG_SCALERA_O_H_LEN) - 1) << DSP2_MISC_RG_SCALERA_O_H_POS) -#define DSP2_MISC_RG_SCALERA_O_H_UMSK (~(((1U << DSP2_MISC_RG_SCALERA_O_H_LEN) - 1) << DSP2_MISC_RG_SCALERA_O_H_POS)) - -/* 0x48 : scalerB_i_size */ -#define DSP2_MISC_SCALERB_I_SIZE_OFFSET (0x48) -#define DSP2_MISC_RG_SCALERB_I_W DSP2_MISC_RG_SCALERB_I_W -#define DSP2_MISC_RG_SCALERB_I_W_POS (0U) -#define DSP2_MISC_RG_SCALERB_I_W_LEN (11U) -#define DSP2_MISC_RG_SCALERB_I_W_MSK (((1U << DSP2_MISC_RG_SCALERB_I_W_LEN) - 1) << DSP2_MISC_RG_SCALERB_I_W_POS) -#define DSP2_MISC_RG_SCALERB_I_W_UMSK (~(((1U << DSP2_MISC_RG_SCALERB_I_W_LEN) - 1) << DSP2_MISC_RG_SCALERB_I_W_POS)) -#define DSP2_MISC_RG_SCALERB_I_H DSP2_MISC_RG_SCALERB_I_H -#define DSP2_MISC_RG_SCALERB_I_H_POS (16U) -#define DSP2_MISC_RG_SCALERB_I_H_LEN (11U) -#define DSP2_MISC_RG_SCALERB_I_H_MSK (((1U << DSP2_MISC_RG_SCALERB_I_H_LEN) - 1) << DSP2_MISC_RG_SCALERB_I_H_POS) -#define DSP2_MISC_RG_SCALERB_I_H_UMSK (~(((1U << DSP2_MISC_RG_SCALERB_I_H_LEN) - 1) << DSP2_MISC_RG_SCALERB_I_H_POS)) -#define DSP2_MISC_RG_SCLRB_SW_SH DSP2_MISC_RG_SCLRB_SW_SH -#define DSP2_MISC_RG_SCLRB_SW_SH_POS (27U) -#define DSP2_MISC_RG_SCLRB_SW_SH_LEN (1U) -#define DSP2_MISC_RG_SCLRB_SW_SH_MSK (((1U << DSP2_MISC_RG_SCLRB_SW_SH_LEN) - 1) << DSP2_MISC_RG_SCLRB_SW_SH_POS) -#define DSP2_MISC_RG_SCLRB_SW_SH_UMSK (~(((1U << DSP2_MISC_RG_SCLRB_SW_SH_LEN) - 1) << DSP2_MISC_RG_SCLRB_SW_SH_POS)) -#define DSP2_MISC_RG_SCALERB_BYPASS DSP2_MISC_RG_SCALERB_BYPASS -#define DSP2_MISC_RG_SCALERB_BYPASS_POS (28U) -#define DSP2_MISC_RG_SCALERB_BYPASS_LEN (1U) -#define DSP2_MISC_RG_SCALERB_BYPASS_MSK (((1U << DSP2_MISC_RG_SCALERB_BYPASS_LEN) - 1) << DSP2_MISC_RG_SCALERB_BYPASS_POS) -#define DSP2_MISC_RG_SCALERB_BYPASS_UMSK (~(((1U << DSP2_MISC_RG_SCALERB_BYPASS_LEN) - 1) << DSP2_MISC_RG_SCALERB_BYPASS_POS)) -#define DSP2_MISC_RG_SCALERB_SEL DSP2_MISC_RG_SCALERB_SEL -#define DSP2_MISC_RG_SCALERB_SEL_POS (29U) -#define DSP2_MISC_RG_SCALERB_SEL_LEN (3U) -#define DSP2_MISC_RG_SCALERB_SEL_MSK (((1U << DSP2_MISC_RG_SCALERB_SEL_LEN) - 1) << DSP2_MISC_RG_SCALERB_SEL_POS) -#define DSP2_MISC_RG_SCALERB_SEL_UMSK (~(((1U << DSP2_MISC_RG_SCALERB_SEL_LEN) - 1) << DSP2_MISC_RG_SCALERB_SEL_POS)) - -/* 0x4C : scalerB_o_size */ -#define DSP2_MISC_SCALERB_O_SIZE_OFFSET (0x4C) -#define DSP2_MISC_RG_SCALERB_O_W DSP2_MISC_RG_SCALERB_O_W -#define DSP2_MISC_RG_SCALERB_O_W_POS (0U) -#define DSP2_MISC_RG_SCALERB_O_W_LEN (11U) -#define DSP2_MISC_RG_SCALERB_O_W_MSK (((1U << DSP2_MISC_RG_SCALERB_O_W_LEN) - 1) << DSP2_MISC_RG_SCALERB_O_W_POS) -#define DSP2_MISC_RG_SCALERB_O_W_UMSK (~(((1U << DSP2_MISC_RG_SCALERB_O_W_LEN) - 1) << DSP2_MISC_RG_SCALERB_O_W_POS)) -#define DSP2_MISC_RG_SCALERB_O_H DSP2_MISC_RG_SCALERB_O_H -#define DSP2_MISC_RG_SCALERB_O_H_POS (16U) -#define DSP2_MISC_RG_SCALERB_O_H_LEN (11U) -#define DSP2_MISC_RG_SCALERB_O_H_MSK (((1U << DSP2_MISC_RG_SCALERB_O_H_LEN) - 1) << DSP2_MISC_RG_SCALERB_O_H_POS) -#define DSP2_MISC_RG_SCALERB_O_H_UMSK (~(((1U << DSP2_MISC_RG_SCALERB_O_H_LEN) - 1) << DSP2_MISC_RG_SCALERB_O_H_POS)) - -/* 0x50 : scalerC_i_size */ -#define DSP2_MISC_SCALERC_I_SIZE_OFFSET (0x50) -#define DSP2_MISC_RG_SCALERC_I_W DSP2_MISC_RG_SCALERC_I_W -#define DSP2_MISC_RG_SCALERC_I_W_POS (0U) -#define DSP2_MISC_RG_SCALERC_I_W_LEN (11U) -#define DSP2_MISC_RG_SCALERC_I_W_MSK (((1U << DSP2_MISC_RG_SCALERC_I_W_LEN) - 1) << DSP2_MISC_RG_SCALERC_I_W_POS) -#define DSP2_MISC_RG_SCALERC_I_W_UMSK (~(((1U << DSP2_MISC_RG_SCALERC_I_W_LEN) - 1) << DSP2_MISC_RG_SCALERC_I_W_POS)) -#define DSP2_MISC_RG_SCALERC_I_H DSP2_MISC_RG_SCALERC_I_H -#define DSP2_MISC_RG_SCALERC_I_H_POS (16U) -#define DSP2_MISC_RG_SCALERC_I_H_LEN (11U) -#define DSP2_MISC_RG_SCALERC_I_H_MSK (((1U << DSP2_MISC_RG_SCALERC_I_H_LEN) - 1) << DSP2_MISC_RG_SCALERC_I_H_POS) -#define DSP2_MISC_RG_SCALERC_I_H_UMSK (~(((1U << DSP2_MISC_RG_SCALERC_I_H_LEN) - 1) << DSP2_MISC_RG_SCALERC_I_H_POS)) -#define DSP2_MISC_RG_SCLRC_SW_SH DSP2_MISC_RG_SCLRC_SW_SH -#define DSP2_MISC_RG_SCLRC_SW_SH_POS (27U) -#define DSP2_MISC_RG_SCLRC_SW_SH_LEN (1U) -#define DSP2_MISC_RG_SCLRC_SW_SH_MSK (((1U << DSP2_MISC_RG_SCLRC_SW_SH_LEN) - 1) << DSP2_MISC_RG_SCLRC_SW_SH_POS) -#define DSP2_MISC_RG_SCLRC_SW_SH_UMSK (~(((1U << DSP2_MISC_RG_SCLRC_SW_SH_LEN) - 1) << DSP2_MISC_RG_SCLRC_SW_SH_POS)) -#define DSP2_MISC_RG_SCALERC_BYPASS DSP2_MISC_RG_SCALERC_BYPASS -#define DSP2_MISC_RG_SCALERC_BYPASS_POS (28U) -#define DSP2_MISC_RG_SCALERC_BYPASS_LEN (1U) -#define DSP2_MISC_RG_SCALERC_BYPASS_MSK (((1U << DSP2_MISC_RG_SCALERC_BYPASS_LEN) - 1) << DSP2_MISC_RG_SCALERC_BYPASS_POS) -#define DSP2_MISC_RG_SCALERC_BYPASS_UMSK (~(((1U << DSP2_MISC_RG_SCALERC_BYPASS_LEN) - 1) << DSP2_MISC_RG_SCALERC_BYPASS_POS)) -#define DSP2_MISC_RG_SCALERC_SEL DSP2_MISC_RG_SCALERC_SEL -#define DSP2_MISC_RG_SCALERC_SEL_POS (29U) -#define DSP2_MISC_RG_SCALERC_SEL_LEN (3U) -#define DSP2_MISC_RG_SCALERC_SEL_MSK (((1U << DSP2_MISC_RG_SCALERC_SEL_LEN) - 1) << DSP2_MISC_RG_SCALERC_SEL_POS) -#define DSP2_MISC_RG_SCALERC_SEL_UMSK (~(((1U << DSP2_MISC_RG_SCALERC_SEL_LEN) - 1) << DSP2_MISC_RG_SCALERC_SEL_POS)) - -/* 0x54 : scalerC_o_size */ -#define DSP2_MISC_SCALERC_O_SIZE_OFFSET (0x54) -#define DSP2_MISC_RG_SCALERC_O_W DSP2_MISC_RG_SCALERC_O_W -#define DSP2_MISC_RG_SCALERC_O_W_POS (0U) -#define DSP2_MISC_RG_SCALERC_O_W_LEN (11U) -#define DSP2_MISC_RG_SCALERC_O_W_MSK (((1U << DSP2_MISC_RG_SCALERC_O_W_LEN) - 1) << DSP2_MISC_RG_SCALERC_O_W_POS) -#define DSP2_MISC_RG_SCALERC_O_W_UMSK (~(((1U << DSP2_MISC_RG_SCALERC_O_W_LEN) - 1) << DSP2_MISC_RG_SCALERC_O_W_POS)) -#define DSP2_MISC_RG_SCALERC_O_H DSP2_MISC_RG_SCALERC_O_H -#define DSP2_MISC_RG_SCALERC_O_H_POS (16U) -#define DSP2_MISC_RG_SCALERC_O_H_LEN (11U) -#define DSP2_MISC_RG_SCALERC_O_H_MSK (((1U << DSP2_MISC_RG_SCALERC_O_H_LEN) - 1) << DSP2_MISC_RG_SCALERC_O_H_POS) -#define DSP2_MISC_RG_SCALERC_O_H_UMSK (~(((1U << DSP2_MISC_RG_SCALERC_O_H_LEN) - 1) << DSP2_MISC_RG_SCALERC_O_H_POS)) - -/* 0x58 : scalerD_i_size */ -#define DSP2_MISC_SCALERD_I_SIZE_OFFSET (0x58) -#define DSP2_MISC_RG_SCALERD_I_W DSP2_MISC_RG_SCALERD_I_W -#define DSP2_MISC_RG_SCALERD_I_W_POS (0U) -#define DSP2_MISC_RG_SCALERD_I_W_LEN (11U) -#define DSP2_MISC_RG_SCALERD_I_W_MSK (((1U << DSP2_MISC_RG_SCALERD_I_W_LEN) - 1) << DSP2_MISC_RG_SCALERD_I_W_POS) -#define DSP2_MISC_RG_SCALERD_I_W_UMSK (~(((1U << DSP2_MISC_RG_SCALERD_I_W_LEN) - 1) << DSP2_MISC_RG_SCALERD_I_W_POS)) -#define DSP2_MISC_RG_SCALERD_I_H DSP2_MISC_RG_SCALERD_I_H -#define DSP2_MISC_RG_SCALERD_I_H_POS (16U) -#define DSP2_MISC_RG_SCALERD_I_H_LEN (11U) -#define DSP2_MISC_RG_SCALERD_I_H_MSK (((1U << DSP2_MISC_RG_SCALERD_I_H_LEN) - 1) << DSP2_MISC_RG_SCALERD_I_H_POS) -#define DSP2_MISC_RG_SCALERD_I_H_UMSK (~(((1U << DSP2_MISC_RG_SCALERD_I_H_LEN) - 1) << DSP2_MISC_RG_SCALERD_I_H_POS)) -#define DSP2_MISC_RG_SCLRD_SW_SH DSP2_MISC_RG_SCLRD_SW_SH -#define DSP2_MISC_RG_SCLRD_SW_SH_POS (27U) -#define DSP2_MISC_RG_SCLRD_SW_SH_LEN (1U) -#define DSP2_MISC_RG_SCLRD_SW_SH_MSK (((1U << DSP2_MISC_RG_SCLRD_SW_SH_LEN) - 1) << DSP2_MISC_RG_SCLRD_SW_SH_POS) -#define DSP2_MISC_RG_SCLRD_SW_SH_UMSK (~(((1U << DSP2_MISC_RG_SCLRD_SW_SH_LEN) - 1) << DSP2_MISC_RG_SCLRD_SW_SH_POS)) -#define DSP2_MISC_RG_SCALERD_BYPASS DSP2_MISC_RG_SCALERD_BYPASS -#define DSP2_MISC_RG_SCALERD_BYPASS_POS (28U) -#define DSP2_MISC_RG_SCALERD_BYPASS_LEN (1U) -#define DSP2_MISC_RG_SCALERD_BYPASS_MSK (((1U << DSP2_MISC_RG_SCALERD_BYPASS_LEN) - 1) << DSP2_MISC_RG_SCALERD_BYPASS_POS) -#define DSP2_MISC_RG_SCALERD_BYPASS_UMSK (~(((1U << DSP2_MISC_RG_SCALERD_BYPASS_LEN) - 1) << DSP2_MISC_RG_SCALERD_BYPASS_POS)) -#define DSP2_MISC_RG_SCALERD_SEL DSP2_MISC_RG_SCALERD_SEL -#define DSP2_MISC_RG_SCALERD_SEL_POS (29U) -#define DSP2_MISC_RG_SCALERD_SEL_LEN (3U) -#define DSP2_MISC_RG_SCALERD_SEL_MSK (((1U << DSP2_MISC_RG_SCALERD_SEL_LEN) - 1) << DSP2_MISC_RG_SCALERD_SEL_POS) -#define DSP2_MISC_RG_SCALERD_SEL_UMSK (~(((1U << DSP2_MISC_RG_SCALERD_SEL_LEN) - 1) << DSP2_MISC_RG_SCALERD_SEL_POS)) - -/* 0x5C : scalerD_o_size */ -#define DSP2_MISC_SCALERD_O_SIZE_OFFSET (0x5C) -#define DSP2_MISC_RG_SCALERD_O_W DSP2_MISC_RG_SCALERD_O_W -#define DSP2_MISC_RG_SCALERD_O_W_POS (0U) -#define DSP2_MISC_RG_SCALERD_O_W_LEN (11U) -#define DSP2_MISC_RG_SCALERD_O_W_MSK (((1U << DSP2_MISC_RG_SCALERD_O_W_LEN) - 1) << DSP2_MISC_RG_SCALERD_O_W_POS) -#define DSP2_MISC_RG_SCALERD_O_W_UMSK (~(((1U << DSP2_MISC_RG_SCALERD_O_W_LEN) - 1) << DSP2_MISC_RG_SCALERD_O_W_POS)) -#define DSP2_MISC_RG_SCALERD_O_H DSP2_MISC_RG_SCALERD_O_H -#define DSP2_MISC_RG_SCALERD_O_H_POS (16U) -#define DSP2_MISC_RG_SCALERD_O_H_LEN (11U) -#define DSP2_MISC_RG_SCALERD_O_H_MSK (((1U << DSP2_MISC_RG_SCALERD_O_H_LEN) - 1) << DSP2_MISC_RG_SCALERD_O_H_POS) -#define DSP2_MISC_RG_SCALERD_O_H_UMSK (~(((1U << DSP2_MISC_RG_SCALERD_O_H_LEN) - 1) << DSP2_MISC_RG_SCALERD_O_H_POS)) - -/* 0x60 : disp_config */ -#define DSP2_MISC_DISP_CONFIG_OFFSET (0x60) -#define DSP2_MISC_RG_DISP_BT656_EN DSP2_MISC_RG_DISP_BT656_EN -#define DSP2_MISC_RG_DISP_BT656_EN_POS (4U) -#define DSP2_MISC_RG_DISP_BT656_EN_LEN (1U) -#define DSP2_MISC_RG_DISP_BT656_EN_MSK (((1U << DSP2_MISC_RG_DISP_BT656_EN_LEN) - 1) << DSP2_MISC_RG_DISP_BT656_EN_POS) -#define DSP2_MISC_RG_DISP_BT656_EN_UMSK (~(((1U << DSP2_MISC_RG_DISP_BT656_EN_LEN) - 1) << DSP2_MISC_RG_DISP_BT656_EN_POS)) -#define DSP2_MISC_RG_DISP_BT1120_EN DSP2_MISC_RG_DISP_BT1120_EN -#define DSP2_MISC_RG_DISP_BT1120_EN_POS (5U) -#define DSP2_MISC_RG_DISP_BT1120_EN_LEN (1U) -#define DSP2_MISC_RG_DISP_BT1120_EN_MSK (((1U << DSP2_MISC_RG_DISP_BT1120_EN_LEN) - 1) << DSP2_MISC_RG_DISP_BT1120_EN_POS) -#define DSP2_MISC_RG_DISP_BT1120_EN_UMSK (~(((1U << DSP2_MISC_RG_DISP_BT1120_EN_LEN) - 1) << DSP2_MISC_RG_DISP_BT1120_EN_POS)) -#define DSP2_MISC_RG_DISP_DPI_EN DSP2_MISC_RG_DISP_DPI_EN -#define DSP2_MISC_RG_DISP_DPI_EN_POS (6U) -#define DSP2_MISC_RG_DISP_DPI_EN_LEN (1U) -#define DSP2_MISC_RG_DISP_DPI_EN_MSK (((1U << DSP2_MISC_RG_DISP_DPI_EN_LEN) - 1) << DSP2_MISC_RG_DISP_DPI_EN_POS) -#define DSP2_MISC_RG_DISP_DPI_EN_UMSK (~(((1U << DSP2_MISC_RG_DISP_DPI_EN_LEN) - 1) << DSP2_MISC_RG_DISP_DPI_EN_POS)) -#define DSP2_MISC_RG_DISP_HDMI_EN DSP2_MISC_RG_DISP_HDMI_EN -#define DSP2_MISC_RG_DISP_HDMI_EN_POS (7U) -#define DSP2_MISC_RG_DISP_HDMI_EN_LEN (1U) -#define DSP2_MISC_RG_DISP_HDMI_EN_MSK (((1U << DSP2_MISC_RG_DISP_HDMI_EN_LEN) - 1) << DSP2_MISC_RG_DISP_HDMI_EN_POS) -#define DSP2_MISC_RG_DISP_HDMI_EN_UMSK (~(((1U << DSP2_MISC_RG_DISP_HDMI_EN_LEN) - 1) << DSP2_MISC_RG_DISP_HDMI_EN_POS)) -#define DSP2_MISC_RG_DISP_MUX_SEL DSP2_MISC_RG_DISP_MUX_SEL -#define DSP2_MISC_RG_DISP_MUX_SEL_POS (8U) -#define DSP2_MISC_RG_DISP_MUX_SEL_LEN (2U) -#define DSP2_MISC_RG_DISP_MUX_SEL_MSK (((1U << DSP2_MISC_RG_DISP_MUX_SEL_LEN) - 1) << DSP2_MISC_RG_DISP_MUX_SEL_POS) -#define DSP2_MISC_RG_DISP_MUX_SEL_UMSK (~(((1U << DSP2_MISC_RG_DISP_MUX_SEL_LEN) - 1) << DSP2_MISC_RG_DISP_MUX_SEL_POS)) -#define DSP2_MISC_RG_OSDDP_SEL DSP2_MISC_RG_OSDDP_SEL -#define DSP2_MISC_RG_OSDDP_SEL_POS (12U) -#define DSP2_MISC_RG_OSDDP_SEL_LEN (2U) -#define DSP2_MISC_RG_OSDDP_SEL_MSK (((1U << DSP2_MISC_RG_OSDDP_SEL_LEN) - 1) << DSP2_MISC_RG_OSDDP_SEL_POS) -#define DSP2_MISC_RG_OSDDP_SEL_UMSK (~(((1U << DSP2_MISC_RG_OSDDP_SEL_LEN) - 1) << DSP2_MISC_RG_OSDDP_SEL_POS)) -#define DSP2_MISC_RG_DISP_CLKO_INV DSP2_MISC_RG_DISP_CLKO_INV -#define DSP2_MISC_RG_DISP_CLKO_INV_POS (31U) -#define DSP2_MISC_RG_DISP_CLKO_INV_LEN (1U) -#define DSP2_MISC_RG_DISP_CLKO_INV_MSK (((1U << DSP2_MISC_RG_DISP_CLKO_INV_LEN) - 1) << DSP2_MISC_RG_DISP_CLKO_INV_POS) -#define DSP2_MISC_RG_DISP_CLKO_INV_UMSK (~(((1U << DSP2_MISC_RG_DISP_CLKO_INV_LEN) - 1) << DSP2_MISC_RG_DISP_CLKO_INV_POS)) - -/* 0x64 : disp_dpi_config */ -#define DSP2_MISC_DISP_DPI_CONFIG_OFFSET (0x64) -#define DSP2_MISC_RG_DISP_DPI_HS_W DSP2_MISC_RG_DISP_DPI_HS_W -#define DSP2_MISC_RG_DISP_DPI_HS_W_POS (0U) -#define DSP2_MISC_RG_DISP_DPI_HS_W_LEN (8U) -#define DSP2_MISC_RG_DISP_DPI_HS_W_MSK (((1U << DSP2_MISC_RG_DISP_DPI_HS_W_LEN) - 1) << DSP2_MISC_RG_DISP_DPI_HS_W_POS) -#define DSP2_MISC_RG_DISP_DPI_HS_W_UMSK (~(((1U << DSP2_MISC_RG_DISP_DPI_HS_W_LEN) - 1) << DSP2_MISC_RG_DISP_DPI_HS_W_POS)) -#define DSP2_MISC_RG_DISP_DPI_HFP_W DSP2_MISC_RG_DISP_DPI_HFP_W -#define DSP2_MISC_RG_DISP_DPI_HFP_W_POS (8U) -#define DSP2_MISC_RG_DISP_DPI_HFP_W_LEN (8U) -#define DSP2_MISC_RG_DISP_DPI_HFP_W_MSK (((1U << DSP2_MISC_RG_DISP_DPI_HFP_W_LEN) - 1) << DSP2_MISC_RG_DISP_DPI_HFP_W_POS) -#define DSP2_MISC_RG_DISP_DPI_HFP_W_UMSK (~(((1U << DSP2_MISC_RG_DISP_DPI_HFP_W_LEN) - 1) << DSP2_MISC_RG_DISP_DPI_HFP_W_POS)) -#define DSP2_MISC_RG_DISP_DPI_VS_W DSP2_MISC_RG_DISP_DPI_VS_W -#define DSP2_MISC_RG_DISP_DPI_VS_W_POS (16U) -#define DSP2_MISC_RG_DISP_DPI_VS_W_LEN (8U) -#define DSP2_MISC_RG_DISP_DPI_VS_W_MSK (((1U << DSP2_MISC_RG_DISP_DPI_VS_W_LEN) - 1) << DSP2_MISC_RG_DISP_DPI_VS_W_POS) -#define DSP2_MISC_RG_DISP_DPI_VS_W_UMSK (~(((1U << DSP2_MISC_RG_DISP_DPI_VS_W_LEN) - 1) << DSP2_MISC_RG_DISP_DPI_VS_W_POS)) -#define DSP2_MISC_RG_DISP_DPI_VFP_W DSP2_MISC_RG_DISP_DPI_VFP_W -#define DSP2_MISC_RG_DISP_DPI_VFP_W_POS (24U) -#define DSP2_MISC_RG_DISP_DPI_VFP_W_LEN (8U) -#define DSP2_MISC_RG_DISP_DPI_VFP_W_MSK (((1U << DSP2_MISC_RG_DISP_DPI_VFP_W_LEN) - 1) << DSP2_MISC_RG_DISP_DPI_VFP_W_POS) -#define DSP2_MISC_RG_DISP_DPI_VFP_W_UMSK (~(((1U << DSP2_MISC_RG_DISP_DPI_VFP_W_LEN) - 1) << DSP2_MISC_RG_DISP_DPI_VFP_W_POS)) - -/* 0x68 : disp_yuv_rgb_config_0 */ -#define DSP2_MISC_DISP_YUV_RGB_CONFIG_0_OFFSET (0x68) -#define DSP2_MISC_RG_DISP_Y2R_PRE_0 DSP2_MISC_RG_DISP_Y2R_PRE_0 -#define DSP2_MISC_RG_DISP_Y2R_PRE_0_POS (0U) -#define DSP2_MISC_RG_DISP_Y2R_PRE_0_LEN (9U) -#define DSP2_MISC_RG_DISP_Y2R_PRE_0_MSK (((1U << DSP2_MISC_RG_DISP_Y2R_PRE_0_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_PRE_0_POS) -#define DSP2_MISC_RG_DISP_Y2R_PRE_0_UMSK (~(((1U << DSP2_MISC_RG_DISP_Y2R_PRE_0_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_PRE_0_POS)) -#define DSP2_MISC_RG_DISP_Y2R_PRE_1 DSP2_MISC_RG_DISP_Y2R_PRE_1 -#define DSP2_MISC_RG_DISP_Y2R_PRE_1_POS (10U) -#define DSP2_MISC_RG_DISP_Y2R_PRE_1_LEN (9U) -#define DSP2_MISC_RG_DISP_Y2R_PRE_1_MSK (((1U << DSP2_MISC_RG_DISP_Y2R_PRE_1_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_PRE_1_POS) -#define DSP2_MISC_RG_DISP_Y2R_PRE_1_UMSK (~(((1U << DSP2_MISC_RG_DISP_Y2R_PRE_1_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_PRE_1_POS)) -#define DSP2_MISC_RG_DISP_Y2R_PRE_2 DSP2_MISC_RG_DISP_Y2R_PRE_2 -#define DSP2_MISC_RG_DISP_Y2R_PRE_2_POS (20U) -#define DSP2_MISC_RG_DISP_Y2R_PRE_2_LEN (9U) -#define DSP2_MISC_RG_DISP_Y2R_PRE_2_MSK (((1U << DSP2_MISC_RG_DISP_Y2R_PRE_2_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_PRE_2_POS) -#define DSP2_MISC_RG_DISP_Y2R_PRE_2_UMSK (~(((1U << DSP2_MISC_RG_DISP_Y2R_PRE_2_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_PRE_2_POS)) -#define DSP2_MISC_RG_DISP_Y2R_EN DSP2_MISC_RG_DISP_Y2R_EN -#define DSP2_MISC_RG_DISP_Y2R_EN_POS (31U) -#define DSP2_MISC_RG_DISP_Y2R_EN_LEN (1U) -#define DSP2_MISC_RG_DISP_Y2R_EN_MSK (((1U << DSP2_MISC_RG_DISP_Y2R_EN_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_EN_POS) -#define DSP2_MISC_RG_DISP_Y2R_EN_UMSK (~(((1U << DSP2_MISC_RG_DISP_Y2R_EN_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_EN_POS)) - -/* 0x6C : disp_yuv_rgb_config_1 */ -#define DSP2_MISC_DISP_YUV_RGB_CONFIG_1_OFFSET (0x6C) -#define DSP2_MISC_RG_DISP_Y2R_POS_0 DSP2_MISC_RG_DISP_Y2R_POS_0 -#define DSP2_MISC_RG_DISP_Y2R_POS_0_POS (0U) -#define DSP2_MISC_RG_DISP_Y2R_POS_0_LEN (9U) -#define DSP2_MISC_RG_DISP_Y2R_POS_0_MSK (((1U << DSP2_MISC_RG_DISP_Y2R_POS_0_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_POS_0_POS) -#define DSP2_MISC_RG_DISP_Y2R_POS_0_UMSK (~(((1U << DSP2_MISC_RG_DISP_Y2R_POS_0_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_POS_0_POS)) -#define DSP2_MISC_RG_DISP_Y2R_POS_1 DSP2_MISC_RG_DISP_Y2R_POS_1 -#define DSP2_MISC_RG_DISP_Y2R_POS_1_POS (10U) -#define DSP2_MISC_RG_DISP_Y2R_POS_1_LEN (9U) -#define DSP2_MISC_RG_DISP_Y2R_POS_1_MSK (((1U << DSP2_MISC_RG_DISP_Y2R_POS_1_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_POS_1_POS) -#define DSP2_MISC_RG_DISP_Y2R_POS_1_UMSK (~(((1U << DSP2_MISC_RG_DISP_Y2R_POS_1_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_POS_1_POS)) -#define DSP2_MISC_RG_DISP_Y2R_POS_2 DSP2_MISC_RG_DISP_Y2R_POS_2 -#define DSP2_MISC_RG_DISP_Y2R_POS_2_POS (20U) -#define DSP2_MISC_RG_DISP_Y2R_POS_2_LEN (9U) -#define DSP2_MISC_RG_DISP_Y2R_POS_2_MSK (((1U << DSP2_MISC_RG_DISP_Y2R_POS_2_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_POS_2_POS) -#define DSP2_MISC_RG_DISP_Y2R_POS_2_UMSK (~(((1U << DSP2_MISC_RG_DISP_Y2R_POS_2_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_POS_2_POS)) - -/* 0x70 : disp_yuv_rgb_config_2 */ -#define DSP2_MISC_DISP_YUV_RGB_CONFIG_2_OFFSET (0x70) -#define DSP2_MISC_RG_DISP_Y2R_MTX_00 DSP2_MISC_RG_DISP_Y2R_MTX_00 -#define DSP2_MISC_RG_DISP_Y2R_MTX_00_POS (0U) -#define DSP2_MISC_RG_DISP_Y2R_MTX_00_LEN (12U) -#define DSP2_MISC_RG_DISP_Y2R_MTX_00_MSK (((1U << DSP2_MISC_RG_DISP_Y2R_MTX_00_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_MTX_00_POS) -#define DSP2_MISC_RG_DISP_Y2R_MTX_00_UMSK (~(((1U << DSP2_MISC_RG_DISP_Y2R_MTX_00_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_MTX_00_POS)) -#define DSP2_MISC_RG_DISP_Y2R_MTX_01 DSP2_MISC_RG_DISP_Y2R_MTX_01 -#define DSP2_MISC_RG_DISP_Y2R_MTX_01_POS (12U) -#define DSP2_MISC_RG_DISP_Y2R_MTX_01_LEN (12U) -#define DSP2_MISC_RG_DISP_Y2R_MTX_01_MSK (((1U << DSP2_MISC_RG_DISP_Y2R_MTX_01_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_MTX_01_POS) -#define DSP2_MISC_RG_DISP_Y2R_MTX_01_UMSK (~(((1U << DSP2_MISC_RG_DISP_Y2R_MTX_01_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_MTX_01_POS)) -#define DSP2_MISC_RG_DISP_Y2R_MTX_02_L DSP2_MISC_RG_DISP_Y2R_MTX_02_L -#define DSP2_MISC_RG_DISP_Y2R_MTX_02_L_POS (24U) -#define DSP2_MISC_RG_DISP_Y2R_MTX_02_L_LEN (8U) -#define DSP2_MISC_RG_DISP_Y2R_MTX_02_L_MSK (((1U << DSP2_MISC_RG_DISP_Y2R_MTX_02_L_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_MTX_02_L_POS) -#define DSP2_MISC_RG_DISP_Y2R_MTX_02_L_UMSK (~(((1U << DSP2_MISC_RG_DISP_Y2R_MTX_02_L_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_MTX_02_L_POS)) - -/* 0x74 : disp_yuv_rgb_config_3 */ -#define DSP2_MISC_DISP_YUV_RGB_CONFIG_3_OFFSET (0x74) -#define DSP2_MISC_RG_DISP_Y2R_MTX_02_U DSP2_MISC_RG_DISP_Y2R_MTX_02_U -#define DSP2_MISC_RG_DISP_Y2R_MTX_02_U_POS (0U) -#define DSP2_MISC_RG_DISP_Y2R_MTX_02_U_LEN (4U) -#define DSP2_MISC_RG_DISP_Y2R_MTX_02_U_MSK (((1U << DSP2_MISC_RG_DISP_Y2R_MTX_02_U_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_MTX_02_U_POS) -#define DSP2_MISC_RG_DISP_Y2R_MTX_02_U_UMSK (~(((1U << DSP2_MISC_RG_DISP_Y2R_MTX_02_U_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_MTX_02_U_POS)) -#define DSP2_MISC_RG_DISP_Y2R_MTX_10 DSP2_MISC_RG_DISP_Y2R_MTX_10 -#define DSP2_MISC_RG_DISP_Y2R_MTX_10_POS (4U) -#define DSP2_MISC_RG_DISP_Y2R_MTX_10_LEN (12U) -#define DSP2_MISC_RG_DISP_Y2R_MTX_10_MSK (((1U << DSP2_MISC_RG_DISP_Y2R_MTX_10_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_MTX_10_POS) -#define DSP2_MISC_RG_DISP_Y2R_MTX_10_UMSK (~(((1U << DSP2_MISC_RG_DISP_Y2R_MTX_10_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_MTX_10_POS)) -#define DSP2_MISC_RG_DISP_Y2R_MTX_11 DSP2_MISC_RG_DISP_Y2R_MTX_11 -#define DSP2_MISC_RG_DISP_Y2R_MTX_11_POS (16U) -#define DSP2_MISC_RG_DISP_Y2R_MTX_11_LEN (12U) -#define DSP2_MISC_RG_DISP_Y2R_MTX_11_MSK (((1U << DSP2_MISC_RG_DISP_Y2R_MTX_11_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_MTX_11_POS) -#define DSP2_MISC_RG_DISP_Y2R_MTX_11_UMSK (~(((1U << DSP2_MISC_RG_DISP_Y2R_MTX_11_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_MTX_11_POS)) -#define DSP2_MISC_RG_DISP_Y2R_MTX_12_L DSP2_MISC_RG_DISP_Y2R_MTX_12_L -#define DSP2_MISC_RG_DISP_Y2R_MTX_12_L_POS (28U) -#define DSP2_MISC_RG_DISP_Y2R_MTX_12_L_LEN (4U) -#define DSP2_MISC_RG_DISP_Y2R_MTX_12_L_MSK (((1U << DSP2_MISC_RG_DISP_Y2R_MTX_12_L_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_MTX_12_L_POS) -#define DSP2_MISC_RG_DISP_Y2R_MTX_12_L_UMSK (~(((1U << DSP2_MISC_RG_DISP_Y2R_MTX_12_L_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_MTX_12_L_POS)) - -/* 0x78 : disp_yuv_rgb_config_4 */ -#define DSP2_MISC_DISP_YUV_RGB_CONFIG_4_OFFSET (0x78) -#define DSP2_MISC_RG_DISP_Y2R_MTX_12_U DSP2_MISC_RG_DISP_Y2R_MTX_12_U -#define DSP2_MISC_RG_DISP_Y2R_MTX_12_U_POS (0U) -#define DSP2_MISC_RG_DISP_Y2R_MTX_12_U_LEN (8U) -#define DSP2_MISC_RG_DISP_Y2R_MTX_12_U_MSK (((1U << DSP2_MISC_RG_DISP_Y2R_MTX_12_U_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_MTX_12_U_POS) -#define DSP2_MISC_RG_DISP_Y2R_MTX_12_U_UMSK (~(((1U << DSP2_MISC_RG_DISP_Y2R_MTX_12_U_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_MTX_12_U_POS)) -#define DSP2_MISC_RG_DISP_Y2R_MTX_20 DSP2_MISC_RG_DISP_Y2R_MTX_20 -#define DSP2_MISC_RG_DISP_Y2R_MTX_20_POS (8U) -#define DSP2_MISC_RG_DISP_Y2R_MTX_20_LEN (12U) -#define DSP2_MISC_RG_DISP_Y2R_MTX_20_MSK (((1U << DSP2_MISC_RG_DISP_Y2R_MTX_20_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_MTX_20_POS) -#define DSP2_MISC_RG_DISP_Y2R_MTX_20_UMSK (~(((1U << DSP2_MISC_RG_DISP_Y2R_MTX_20_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_MTX_20_POS)) -#define DSP2_MISC_RG_DISP_Y2R_MTX_21 DSP2_MISC_RG_DISP_Y2R_MTX_21 -#define DSP2_MISC_RG_DISP_Y2R_MTX_21_POS (20U) -#define DSP2_MISC_RG_DISP_Y2R_MTX_21_LEN (12U) -#define DSP2_MISC_RG_DISP_Y2R_MTX_21_MSK (((1U << DSP2_MISC_RG_DISP_Y2R_MTX_21_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_MTX_21_POS) -#define DSP2_MISC_RG_DISP_Y2R_MTX_21_UMSK (~(((1U << DSP2_MISC_RG_DISP_Y2R_MTX_21_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_MTX_21_POS)) - -/* 0x7C : disp_yuv_rgb_config_5 */ -#define DSP2_MISC_DISP_YUV_RGB_CONFIG_5_OFFSET (0x7C) -#define DSP2_MISC_RG_DISP_Y2R_MTX_22 DSP2_MISC_RG_DISP_Y2R_MTX_22 -#define DSP2_MISC_RG_DISP_Y2R_MTX_22_POS (0U) -#define DSP2_MISC_RG_DISP_Y2R_MTX_22_LEN (12U) -#define DSP2_MISC_RG_DISP_Y2R_MTX_22_MSK (((1U << DSP2_MISC_RG_DISP_Y2R_MTX_22_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_MTX_22_POS) -#define DSP2_MISC_RG_DISP_Y2R_MTX_22_UMSK (~(((1U << DSP2_MISC_RG_DISP_Y2R_MTX_22_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_MTX_22_POS)) - -/* 0x80 : dsp2_subsys_bus_ctrl */ -#define DSP2_MISC_DSP2_SUBSYS_BUS_CTRL_OFFSET (0x80) -#define DSP2_MISC_RG_DSP2_SUB_PCLK_FORCE_ON DSP2_MISC_RG_DSP2_SUB_PCLK_FORCE_ON -#define DSP2_MISC_RG_DSP2_SUB_PCLK_FORCE_ON_POS (0U) -#define DSP2_MISC_RG_DSP2_SUB_PCLK_FORCE_ON_LEN (16U) -#define DSP2_MISC_RG_DSP2_SUB_PCLK_FORCE_ON_MSK (((1U << DSP2_MISC_RG_DSP2_SUB_PCLK_FORCE_ON_LEN) - 1) << DSP2_MISC_RG_DSP2_SUB_PCLK_FORCE_ON_POS) -#define DSP2_MISC_RG_DSP2_SUB_PCLK_FORCE_ON_UMSK (~(((1U << DSP2_MISC_RG_DSP2_SUB_PCLK_FORCE_ON_LEN) - 1) << DSP2_MISC_RG_DSP2_SUB_PCLK_FORCE_ON_POS)) -#define DSP2_MISC_RG_DSP2_PERI_PCLK_FORCE_ON DSP2_MISC_RG_DSP2_PERI_PCLK_FORCE_ON -#define DSP2_MISC_RG_DSP2_PERI_PCLK_FORCE_ON_POS (16U) -#define DSP2_MISC_RG_DSP2_PERI_PCLK_FORCE_ON_LEN (16U) -#define DSP2_MISC_RG_DSP2_PERI_PCLK_FORCE_ON_MSK (((1U << DSP2_MISC_RG_DSP2_PERI_PCLK_FORCE_ON_LEN) - 1) << DSP2_MISC_RG_DSP2_PERI_PCLK_FORCE_ON_POS) -#define DSP2_MISC_RG_DSP2_PERI_PCLK_FORCE_ON_UMSK (~(((1U << DSP2_MISC_RG_DSP2_PERI_PCLK_FORCE_ON_LEN) - 1) << DSP2_MISC_RG_DSP2_PERI_PCLK_FORCE_ON_POS)) - -/* 0xA0 : osdA_i_ctrl */ -#define DSP2_MISC_OSDA_I_CTRL_OFFSET (0xA0) -#define DSP2_MISC_RG_OSD_PB_SEL DSP2_MISC_RG_OSD_PB_SEL -#define DSP2_MISC_RG_OSD_PB_SEL_POS (0U) -#define DSP2_MISC_RG_OSD_PB_SEL_LEN (1U) -#define DSP2_MISC_RG_OSD_PB_SEL_MSK (((1U << DSP2_MISC_RG_OSD_PB_SEL_LEN) - 1) << DSP2_MISC_RG_OSD_PB_SEL_POS) -#define DSP2_MISC_RG_OSD_PB_SEL_UMSK (~(((1U << DSP2_MISC_RG_OSD_PB_SEL_LEN) - 1) << DSP2_MISC_RG_OSD_PB_SEL_POS)) -#define DSP2_MISC_RG_OSDA_SEL DSP2_MISC_RG_OSDA_SEL -#define DSP2_MISC_RG_OSDA_SEL_POS (29U) -#define DSP2_MISC_RG_OSDA_SEL_LEN (3U) -#define DSP2_MISC_RG_OSDA_SEL_MSK (((1U << DSP2_MISC_RG_OSDA_SEL_LEN) - 1) << DSP2_MISC_RG_OSDA_SEL_POS) -#define DSP2_MISC_RG_OSDA_SEL_UMSK (~(((1U << DSP2_MISC_RG_OSDA_SEL_LEN) - 1) << DSP2_MISC_RG_OSDA_SEL_POS)) - -/* 0xA4 : osdB_i_ctrl */ -#define DSP2_MISC_OSDB_I_CTRL_OFFSET (0xA4) -#define DSP2_MISC_RG_OSDB_SEL DSP2_MISC_RG_OSDB_SEL -#define DSP2_MISC_RG_OSDB_SEL_POS (29U) -#define DSP2_MISC_RG_OSDB_SEL_LEN (3U) -#define DSP2_MISC_RG_OSDB_SEL_MSK (((1U << DSP2_MISC_RG_OSDB_SEL_LEN) - 1) << DSP2_MISC_RG_OSDB_SEL_POS) -#define DSP2_MISC_RG_OSDB_SEL_UMSK (~(((1U << DSP2_MISC_RG_OSDB_SEL_LEN) - 1) << DSP2_MISC_RG_OSDB_SEL_POS)) - -/* 0xA8 : osdC_i_ctrl */ -#define DSP2_MISC_OSDC_I_CTRL_OFFSET (0xA8) -#define DSP2_MISC_RG_OSDC_SEL DSP2_MISC_RG_OSDC_SEL -#define DSP2_MISC_RG_OSDC_SEL_POS (29U) -#define DSP2_MISC_RG_OSDC_SEL_LEN (3U) -#define DSP2_MISC_RG_OSDC_SEL_MSK (((1U << DSP2_MISC_RG_OSDC_SEL_LEN) - 1) << DSP2_MISC_RG_OSDC_SEL_POS) -#define DSP2_MISC_RG_OSDC_SEL_UMSK (~(((1U << DSP2_MISC_RG_OSDC_SEL_LEN) - 1) << DSP2_MISC_RG_OSDC_SEL_POS)) - -/* 0xAC : osdD_i_ctrl */ -#define DSP2_MISC_OSDD_I_CTRL_OFFSET (0xAC) -#define DSP2_MISC_RG_OSDD_SEL DSP2_MISC_RG_OSDD_SEL -#define DSP2_MISC_RG_OSDD_SEL_POS (29U) -#define DSP2_MISC_RG_OSDD_SEL_LEN (3U) -#define DSP2_MISC_RG_OSDD_SEL_MSK (((1U << DSP2_MISC_RG_OSDD_SEL_LEN) - 1) << DSP2_MISC_RG_OSDD_SEL_POS) -#define DSP2_MISC_RG_OSDD_SEL_UMSK (~(((1U << DSP2_MISC_RG_OSDD_SEL_LEN) - 1) << DSP2_MISC_RG_OSDD_SEL_POS)) - -/* 0xC0 : dsp2_subsys_dbg_sel */ -#define DSP2_MISC_DSP2_SUBSYS_DBG_SEL_OFFSET (0xC0) -#define DSP2_MISC_REG_DSP2_SUB_DBG_EN DSP2_MISC_REG_DSP2_SUB_DBG_EN -#define DSP2_MISC_REG_DSP2_SUB_DBG_EN_POS (0U) -#define DSP2_MISC_REG_DSP2_SUB_DBG_EN_LEN (1U) -#define DSP2_MISC_REG_DSP2_SUB_DBG_EN_MSK (((1U << DSP2_MISC_REG_DSP2_SUB_DBG_EN_LEN) - 1) << DSP2_MISC_REG_DSP2_SUB_DBG_EN_POS) -#define DSP2_MISC_REG_DSP2_SUB_DBG_EN_UMSK (~(((1U << DSP2_MISC_REG_DSP2_SUB_DBG_EN_LEN) - 1) << DSP2_MISC_REG_DSP2_SUB_DBG_EN_POS)) -#define DSP2_MISC_REG_DSP2_SUB_DBG_SEL DSP2_MISC_REG_DSP2_SUB_DBG_SEL -#define DSP2_MISC_REG_DSP2_SUB_DBG_SEL_POS (4U) -#define DSP2_MISC_REG_DSP2_SUB_DBG_SEL_LEN (4U) -#define DSP2_MISC_REG_DSP2_SUB_DBG_SEL_MSK (((1U << DSP2_MISC_REG_DSP2_SUB_DBG_SEL_LEN) - 1) << DSP2_MISC_REG_DSP2_SUB_DBG_SEL_POS) -#define DSP2_MISC_REG_DSP2_SUB_DBG_SEL_UMSK (~(((1U << DSP2_MISC_REG_DSP2_SUB_DBG_SEL_LEN) - 1) << DSP2_MISC_REG_DSP2_SUB_DBG_SEL_POS)) - -/* 0xFC : DSP2_MISC_Dummy */ -#define DSP2_MISC_DUMMY_OFFSET (0xFC) -#define DSP2_MISC_DUMMY_REG DSP2_MISC_DUMMY_REG -#define DSP2_MISC_DUMMY_REG_POS (0U) -#define DSP2_MISC_DUMMY_REG_LEN (32U) -#define DSP2_MISC_DUMMY_REG_MSK (((1U << DSP2_MISC_DUMMY_REG_LEN) - 1) << DSP2_MISC_DUMMY_REG_POS) -#define DSP2_MISC_DUMMY_REG_UMSK (~(((1U << DSP2_MISC_DUMMY_REG_LEN) - 1) << DSP2_MISC_DUMMY_REG_POS)) - -/* 0x100 : adjA_ctrl_0 */ -#define DSP2_MISC_ADJA_CTRL_0_OFFSET (0x100) -#define DSP2_MISC_REG_ADJA_ADJ_EB DSP2_MISC_REG_ADJA_ADJ_EB -#define DSP2_MISC_REG_ADJA_ADJ_EB_POS (0U) -#define DSP2_MISC_REG_ADJA_ADJ_EB_LEN (1U) -#define DSP2_MISC_REG_ADJA_ADJ_EB_MSK (((1U << DSP2_MISC_REG_ADJA_ADJ_EB_LEN) - 1) << DSP2_MISC_REG_ADJA_ADJ_EB_POS) -#define DSP2_MISC_REG_ADJA_ADJ_EB_UMSK (~(((1U << DSP2_MISC_REG_ADJA_ADJ_EB_LEN) - 1) << DSP2_MISC_REG_ADJA_ADJ_EB_POS)) -#define DSP2_MISC_REG_ADJA_Y_LUMA DSP2_MISC_REG_ADJA_Y_LUMA -#define DSP2_MISC_REG_ADJA_Y_LUMA_POS (1U) -#define DSP2_MISC_REG_ADJA_Y_LUMA_LEN (9U) -#define DSP2_MISC_REG_ADJA_Y_LUMA_MSK (((1U << DSP2_MISC_REG_ADJA_Y_LUMA_LEN) - 1) << DSP2_MISC_REG_ADJA_Y_LUMA_POS) -#define DSP2_MISC_REG_ADJA_Y_LUMA_UMSK (~(((1U << DSP2_MISC_REG_ADJA_Y_LUMA_LEN) - 1) << DSP2_MISC_REG_ADJA_Y_LUMA_POS)) -#define DSP2_MISC_REG_ADJA_Y_MUL0 DSP2_MISC_REG_ADJA_Y_MUL0 -#define DSP2_MISC_REG_ADJA_Y_MUL0_POS (10U) -#define DSP2_MISC_REG_ADJA_Y_MUL0_LEN (11U) -#define DSP2_MISC_REG_ADJA_Y_MUL0_MSK (((1U << DSP2_MISC_REG_ADJA_Y_MUL0_LEN) - 1) << DSP2_MISC_REG_ADJA_Y_MUL0_POS) -#define DSP2_MISC_REG_ADJA_Y_MUL0_UMSK (~(((1U << DSP2_MISC_REG_ADJA_Y_MUL0_LEN) - 1) << DSP2_MISC_REG_ADJA_Y_MUL0_POS)) -#define DSP2_MISC_REG_ADJA_Y_MUL1 DSP2_MISC_REG_ADJA_Y_MUL1 -#define DSP2_MISC_REG_ADJA_Y_MUL1_POS (21U) -#define DSP2_MISC_REG_ADJA_Y_MUL1_LEN (11U) -#define DSP2_MISC_REG_ADJA_Y_MUL1_MSK (((1U << DSP2_MISC_REG_ADJA_Y_MUL1_LEN) - 1) << DSP2_MISC_REG_ADJA_Y_MUL1_POS) -#define DSP2_MISC_REG_ADJA_Y_MUL1_UMSK (~(((1U << DSP2_MISC_REG_ADJA_Y_MUL1_LEN) - 1) << DSP2_MISC_REG_ADJA_Y_MUL1_POS)) - -/* 0x104 : adjA_ctrl_1 */ -#define DSP2_MISC_ADJA_CTRL_1_OFFSET (0x104) -#define DSP2_MISC_REG_ADJA_Y_MIN DSP2_MISC_REG_ADJA_Y_MIN -#define DSP2_MISC_REG_ADJA_Y_MIN_POS (0U) -#define DSP2_MISC_REG_ADJA_Y_MIN_LEN (8U) -#define DSP2_MISC_REG_ADJA_Y_MIN_MSK (((1U << DSP2_MISC_REG_ADJA_Y_MIN_LEN) - 1) << DSP2_MISC_REG_ADJA_Y_MIN_POS) -#define DSP2_MISC_REG_ADJA_Y_MIN_UMSK (~(((1U << DSP2_MISC_REG_ADJA_Y_MIN_LEN) - 1) << DSP2_MISC_REG_ADJA_Y_MIN_POS)) -#define DSP2_MISC_REG_ADJA_Y_MAX DSP2_MISC_REG_ADJA_Y_MAX -#define DSP2_MISC_REG_ADJA_Y_MAX_POS (8U) -#define DSP2_MISC_REG_ADJA_Y_MAX_LEN (8U) -#define DSP2_MISC_REG_ADJA_Y_MAX_MSK (((1U << DSP2_MISC_REG_ADJA_Y_MAX_LEN) - 1) << DSP2_MISC_REG_ADJA_Y_MAX_POS) -#define DSP2_MISC_REG_ADJA_Y_MAX_UMSK (~(((1U << DSP2_MISC_REG_ADJA_Y_MAX_LEN) - 1) << DSP2_MISC_REG_ADJA_Y_MAX_POS)) -#define DSP2_MISC_REG_ADJA_UV_MIN DSP2_MISC_REG_ADJA_UV_MIN -#define DSP2_MISC_REG_ADJA_UV_MIN_POS (16U) -#define DSP2_MISC_REG_ADJA_UV_MIN_LEN (8U) -#define DSP2_MISC_REG_ADJA_UV_MIN_MSK (((1U << DSP2_MISC_REG_ADJA_UV_MIN_LEN) - 1) << DSP2_MISC_REG_ADJA_UV_MIN_POS) -#define DSP2_MISC_REG_ADJA_UV_MIN_UMSK (~(((1U << DSP2_MISC_REG_ADJA_UV_MIN_LEN) - 1) << DSP2_MISC_REG_ADJA_UV_MIN_POS)) -#define DSP2_MISC_REG_ADJA_UV_MAX DSP2_MISC_REG_ADJA_UV_MAX -#define DSP2_MISC_REG_ADJA_UV_MAX_POS (24U) -#define DSP2_MISC_REG_ADJA_UV_MAX_LEN (8U) -#define DSP2_MISC_REG_ADJA_UV_MAX_MSK (((1U << DSP2_MISC_REG_ADJA_UV_MAX_LEN) - 1) << DSP2_MISC_REG_ADJA_UV_MAX_POS) -#define DSP2_MISC_REG_ADJA_UV_MAX_UMSK (~(((1U << DSP2_MISC_REG_ADJA_UV_MAX_LEN) - 1) << DSP2_MISC_REG_ADJA_UV_MAX_POS)) - -/* 0x108 : adjA_ctrl_2 */ -#define DSP2_MISC_ADJA_CTRL_2_OFFSET (0x108) -#define DSP2_MISC_RG_ADJA_SEL DSP2_MISC_RG_ADJA_SEL -#define DSP2_MISC_RG_ADJA_SEL_POS (0U) -#define DSP2_MISC_RG_ADJA_SEL_LEN (4U) -#define DSP2_MISC_RG_ADJA_SEL_MSK (((1U << DSP2_MISC_RG_ADJA_SEL_LEN) - 1) << DSP2_MISC_RG_ADJA_SEL_POS) -#define DSP2_MISC_RG_ADJA_SEL_UMSK (~(((1U << DSP2_MISC_RG_ADJA_SEL_LEN) - 1) << DSP2_MISC_RG_ADJA_SEL_POS)) -#define DSP2_MISC_REG_ADJA_UV_MUL0 DSP2_MISC_REG_ADJA_UV_MUL0 -#define DSP2_MISC_REG_ADJA_UV_MUL0_POS (10U) -#define DSP2_MISC_REG_ADJA_UV_MUL0_LEN (11U) -#define DSP2_MISC_REG_ADJA_UV_MUL0_MSK (((1U << DSP2_MISC_REG_ADJA_UV_MUL0_LEN) - 1) << DSP2_MISC_REG_ADJA_UV_MUL0_POS) -#define DSP2_MISC_REG_ADJA_UV_MUL0_UMSK (~(((1U << DSP2_MISC_REG_ADJA_UV_MUL0_LEN) - 1) << DSP2_MISC_REG_ADJA_UV_MUL0_POS)) -#define DSP2_MISC_REG_ADJA_UV_MUL1 DSP2_MISC_REG_ADJA_UV_MUL1 -#define DSP2_MISC_REG_ADJA_UV_MUL1_POS (21U) -#define DSP2_MISC_REG_ADJA_UV_MUL1_LEN (11U) -#define DSP2_MISC_REG_ADJA_UV_MUL1_MSK (((1U << DSP2_MISC_REG_ADJA_UV_MUL1_LEN) - 1) << DSP2_MISC_REG_ADJA_UV_MUL1_POS) -#define DSP2_MISC_REG_ADJA_UV_MUL1_UMSK (~(((1U << DSP2_MISC_REG_ADJA_UV_MUL1_LEN) - 1) << DSP2_MISC_REG_ADJA_UV_MUL1_POS)) - -/* 0x110 : adjB_ctrl_0 */ -#define DSP2_MISC_ADJB_CTRL_0_OFFSET (0x110) -#define DSP2_MISC_REG_ADJB_ADJ_EB DSP2_MISC_REG_ADJB_ADJ_EB -#define DSP2_MISC_REG_ADJB_ADJ_EB_POS (0U) -#define DSP2_MISC_REG_ADJB_ADJ_EB_LEN (1U) -#define DSP2_MISC_REG_ADJB_ADJ_EB_MSK (((1U << DSP2_MISC_REG_ADJB_ADJ_EB_LEN) - 1) << DSP2_MISC_REG_ADJB_ADJ_EB_POS) -#define DSP2_MISC_REG_ADJB_ADJ_EB_UMSK (~(((1U << DSP2_MISC_REG_ADJB_ADJ_EB_LEN) - 1) << DSP2_MISC_REG_ADJB_ADJ_EB_POS)) -#define DSP2_MISC_REG_ADJB_Y_LUMA DSP2_MISC_REG_ADJB_Y_LUMA -#define DSP2_MISC_REG_ADJB_Y_LUMA_POS (1U) -#define DSP2_MISC_REG_ADJB_Y_LUMA_LEN (9U) -#define DSP2_MISC_REG_ADJB_Y_LUMA_MSK (((1U << DSP2_MISC_REG_ADJB_Y_LUMA_LEN) - 1) << DSP2_MISC_REG_ADJB_Y_LUMA_POS) -#define DSP2_MISC_REG_ADJB_Y_LUMA_UMSK (~(((1U << DSP2_MISC_REG_ADJB_Y_LUMA_LEN) - 1) << DSP2_MISC_REG_ADJB_Y_LUMA_POS)) -#define DSP2_MISC_REG_ADJB_Y_MUL0 DSP2_MISC_REG_ADJB_Y_MUL0 -#define DSP2_MISC_REG_ADJB_Y_MUL0_POS (10U) -#define DSP2_MISC_REG_ADJB_Y_MUL0_LEN (11U) -#define DSP2_MISC_REG_ADJB_Y_MUL0_MSK (((1U << DSP2_MISC_REG_ADJB_Y_MUL0_LEN) - 1) << DSP2_MISC_REG_ADJB_Y_MUL0_POS) -#define DSP2_MISC_REG_ADJB_Y_MUL0_UMSK (~(((1U << DSP2_MISC_REG_ADJB_Y_MUL0_LEN) - 1) << DSP2_MISC_REG_ADJB_Y_MUL0_POS)) -#define DSP2_MISC_REG_ADJB_Y_MUL1 DSP2_MISC_REG_ADJB_Y_MUL1 -#define DSP2_MISC_REG_ADJB_Y_MUL1_POS (21U) -#define DSP2_MISC_REG_ADJB_Y_MUL1_LEN (11U) -#define DSP2_MISC_REG_ADJB_Y_MUL1_MSK (((1U << DSP2_MISC_REG_ADJB_Y_MUL1_LEN) - 1) << DSP2_MISC_REG_ADJB_Y_MUL1_POS) -#define DSP2_MISC_REG_ADJB_Y_MUL1_UMSK (~(((1U << DSP2_MISC_REG_ADJB_Y_MUL1_LEN) - 1) << DSP2_MISC_REG_ADJB_Y_MUL1_POS)) - -/* 0x114 : adjB_ctrl_1 */ -#define DSP2_MISC_ADJB_CTRL_1_OFFSET (0x114) -#define DSP2_MISC_REG_ADJB_Y_MIN DSP2_MISC_REG_ADJB_Y_MIN -#define DSP2_MISC_REG_ADJB_Y_MIN_POS (0U) -#define DSP2_MISC_REG_ADJB_Y_MIN_LEN (8U) -#define DSP2_MISC_REG_ADJB_Y_MIN_MSK (((1U << DSP2_MISC_REG_ADJB_Y_MIN_LEN) - 1) << DSP2_MISC_REG_ADJB_Y_MIN_POS) -#define DSP2_MISC_REG_ADJB_Y_MIN_UMSK (~(((1U << DSP2_MISC_REG_ADJB_Y_MIN_LEN) - 1) << DSP2_MISC_REG_ADJB_Y_MIN_POS)) -#define DSP2_MISC_REG_ADJB_Y_MAX DSP2_MISC_REG_ADJB_Y_MAX -#define DSP2_MISC_REG_ADJB_Y_MAX_POS (8U) -#define DSP2_MISC_REG_ADJB_Y_MAX_LEN (8U) -#define DSP2_MISC_REG_ADJB_Y_MAX_MSK (((1U << DSP2_MISC_REG_ADJB_Y_MAX_LEN) - 1) << DSP2_MISC_REG_ADJB_Y_MAX_POS) -#define DSP2_MISC_REG_ADJB_Y_MAX_UMSK (~(((1U << DSP2_MISC_REG_ADJB_Y_MAX_LEN) - 1) << DSP2_MISC_REG_ADJB_Y_MAX_POS)) -#define DSP2_MISC_REG_ADJB_UV_MIN DSP2_MISC_REG_ADJB_UV_MIN -#define DSP2_MISC_REG_ADJB_UV_MIN_POS (16U) -#define DSP2_MISC_REG_ADJB_UV_MIN_LEN (8U) -#define DSP2_MISC_REG_ADJB_UV_MIN_MSK (((1U << DSP2_MISC_REG_ADJB_UV_MIN_LEN) - 1) << DSP2_MISC_REG_ADJB_UV_MIN_POS) -#define DSP2_MISC_REG_ADJB_UV_MIN_UMSK (~(((1U << DSP2_MISC_REG_ADJB_UV_MIN_LEN) - 1) << DSP2_MISC_REG_ADJB_UV_MIN_POS)) -#define DSP2_MISC_REG_ADJB_UV_MAX DSP2_MISC_REG_ADJB_UV_MAX -#define DSP2_MISC_REG_ADJB_UV_MAX_POS (24U) -#define DSP2_MISC_REG_ADJB_UV_MAX_LEN (8U) -#define DSP2_MISC_REG_ADJB_UV_MAX_MSK (((1U << DSP2_MISC_REG_ADJB_UV_MAX_LEN) - 1) << DSP2_MISC_REG_ADJB_UV_MAX_POS) -#define DSP2_MISC_REG_ADJB_UV_MAX_UMSK (~(((1U << DSP2_MISC_REG_ADJB_UV_MAX_LEN) - 1) << DSP2_MISC_REG_ADJB_UV_MAX_POS)) - -/* 0x118 : adjB_ctrl_2 */ -#define DSP2_MISC_ADJB_CTRL_2_OFFSET (0x118) -#define DSP2_MISC_RG_ADJB_SEL DSP2_MISC_RG_ADJB_SEL -#define DSP2_MISC_RG_ADJB_SEL_POS (0U) -#define DSP2_MISC_RG_ADJB_SEL_LEN (4U) -#define DSP2_MISC_RG_ADJB_SEL_MSK (((1U << DSP2_MISC_RG_ADJB_SEL_LEN) - 1) << DSP2_MISC_RG_ADJB_SEL_POS) -#define DSP2_MISC_RG_ADJB_SEL_UMSK (~(((1U << DSP2_MISC_RG_ADJB_SEL_LEN) - 1) << DSP2_MISC_RG_ADJB_SEL_POS)) -#define DSP2_MISC_REG_ADJB_UV_MUL0 DSP2_MISC_REG_ADJB_UV_MUL0 -#define DSP2_MISC_REG_ADJB_UV_MUL0_POS (10U) -#define DSP2_MISC_REG_ADJB_UV_MUL0_LEN (11U) -#define DSP2_MISC_REG_ADJB_UV_MUL0_MSK (((1U << DSP2_MISC_REG_ADJB_UV_MUL0_LEN) - 1) << DSP2_MISC_REG_ADJB_UV_MUL0_POS) -#define DSP2_MISC_REG_ADJB_UV_MUL0_UMSK (~(((1U << DSP2_MISC_REG_ADJB_UV_MUL0_LEN) - 1) << DSP2_MISC_REG_ADJB_UV_MUL0_POS)) -#define DSP2_MISC_REG_ADJB_UV_MUL1 DSP2_MISC_REG_ADJB_UV_MUL1 -#define DSP2_MISC_REG_ADJB_UV_MUL1_POS (21U) -#define DSP2_MISC_REG_ADJB_UV_MUL1_LEN (11U) -#define DSP2_MISC_REG_ADJB_UV_MUL1_MSK (((1U << DSP2_MISC_REG_ADJB_UV_MUL1_LEN) - 1) << DSP2_MISC_REG_ADJB_UV_MUL1_POS) -#define DSP2_MISC_REG_ADJB_UV_MUL1_UMSK (~(((1U << DSP2_MISC_REG_ADJB_UV_MUL1_LEN) - 1) << DSP2_MISC_REG_ADJB_UV_MUL1_POS)) - -/* 0x120 : adjC_ctrl_0 */ -#define DSP2_MISC_ADJC_CTRL_0_OFFSET (0x120) -#define DSP2_MISC_REG_ADJC_ADJ_EB DSP2_MISC_REG_ADJC_ADJ_EB -#define DSP2_MISC_REG_ADJC_ADJ_EB_POS (0U) -#define DSP2_MISC_REG_ADJC_ADJ_EB_LEN (1U) -#define DSP2_MISC_REG_ADJC_ADJ_EB_MSK (((1U << DSP2_MISC_REG_ADJC_ADJ_EB_LEN) - 1) << DSP2_MISC_REG_ADJC_ADJ_EB_POS) -#define DSP2_MISC_REG_ADJC_ADJ_EB_UMSK (~(((1U << DSP2_MISC_REG_ADJC_ADJ_EB_LEN) - 1) << DSP2_MISC_REG_ADJC_ADJ_EB_POS)) -#define DSP2_MISC_REG_ADJC_Y_LUMA DSP2_MISC_REG_ADJC_Y_LUMA -#define DSP2_MISC_REG_ADJC_Y_LUMA_POS (1U) -#define DSP2_MISC_REG_ADJC_Y_LUMA_LEN (9U) -#define DSP2_MISC_REG_ADJC_Y_LUMA_MSK (((1U << DSP2_MISC_REG_ADJC_Y_LUMA_LEN) - 1) << DSP2_MISC_REG_ADJC_Y_LUMA_POS) -#define DSP2_MISC_REG_ADJC_Y_LUMA_UMSK (~(((1U << DSP2_MISC_REG_ADJC_Y_LUMA_LEN) - 1) << DSP2_MISC_REG_ADJC_Y_LUMA_POS)) -#define DSP2_MISC_REG_ADJC_Y_MUL0 DSP2_MISC_REG_ADJC_Y_MUL0 -#define DSP2_MISC_REG_ADJC_Y_MUL0_POS (10U) -#define DSP2_MISC_REG_ADJC_Y_MUL0_LEN (11U) -#define DSP2_MISC_REG_ADJC_Y_MUL0_MSK (((1U << DSP2_MISC_REG_ADJC_Y_MUL0_LEN) - 1) << DSP2_MISC_REG_ADJC_Y_MUL0_POS) -#define DSP2_MISC_REG_ADJC_Y_MUL0_UMSK (~(((1U << DSP2_MISC_REG_ADJC_Y_MUL0_LEN) - 1) << DSP2_MISC_REG_ADJC_Y_MUL0_POS)) -#define DSP2_MISC_REG_ADJC_Y_MUL1 DSP2_MISC_REG_ADJC_Y_MUL1 -#define DSP2_MISC_REG_ADJC_Y_MUL1_POS (21U) -#define DSP2_MISC_REG_ADJC_Y_MUL1_LEN (11U) -#define DSP2_MISC_REG_ADJC_Y_MUL1_MSK (((1U << DSP2_MISC_REG_ADJC_Y_MUL1_LEN) - 1) << DSP2_MISC_REG_ADJC_Y_MUL1_POS) -#define DSP2_MISC_REG_ADJC_Y_MUL1_UMSK (~(((1U << DSP2_MISC_REG_ADJC_Y_MUL1_LEN) - 1) << DSP2_MISC_REG_ADJC_Y_MUL1_POS)) - -/* 0x124 : adjC_ctrl_1 */ -#define DSP2_MISC_ADJC_CTRL_1_OFFSET (0x124) -#define DSP2_MISC_REG_ADJC_Y_MIN DSP2_MISC_REG_ADJC_Y_MIN -#define DSP2_MISC_REG_ADJC_Y_MIN_POS (0U) -#define DSP2_MISC_REG_ADJC_Y_MIN_LEN (8U) -#define DSP2_MISC_REG_ADJC_Y_MIN_MSK (((1U << DSP2_MISC_REG_ADJC_Y_MIN_LEN) - 1) << DSP2_MISC_REG_ADJC_Y_MIN_POS) -#define DSP2_MISC_REG_ADJC_Y_MIN_UMSK (~(((1U << DSP2_MISC_REG_ADJC_Y_MIN_LEN) - 1) << DSP2_MISC_REG_ADJC_Y_MIN_POS)) -#define DSP2_MISC_REG_ADJC_Y_MAX DSP2_MISC_REG_ADJC_Y_MAX -#define DSP2_MISC_REG_ADJC_Y_MAX_POS (8U) -#define DSP2_MISC_REG_ADJC_Y_MAX_LEN (8U) -#define DSP2_MISC_REG_ADJC_Y_MAX_MSK (((1U << DSP2_MISC_REG_ADJC_Y_MAX_LEN) - 1) << DSP2_MISC_REG_ADJC_Y_MAX_POS) -#define DSP2_MISC_REG_ADJC_Y_MAX_UMSK (~(((1U << DSP2_MISC_REG_ADJC_Y_MAX_LEN) - 1) << DSP2_MISC_REG_ADJC_Y_MAX_POS)) -#define DSP2_MISC_REG_ADJC_UV_MIN DSP2_MISC_REG_ADJC_UV_MIN -#define DSP2_MISC_REG_ADJC_UV_MIN_POS (16U) -#define DSP2_MISC_REG_ADJC_UV_MIN_LEN (8U) -#define DSP2_MISC_REG_ADJC_UV_MIN_MSK (((1U << DSP2_MISC_REG_ADJC_UV_MIN_LEN) - 1) << DSP2_MISC_REG_ADJC_UV_MIN_POS) -#define DSP2_MISC_REG_ADJC_UV_MIN_UMSK (~(((1U << DSP2_MISC_REG_ADJC_UV_MIN_LEN) - 1) << DSP2_MISC_REG_ADJC_UV_MIN_POS)) -#define DSP2_MISC_REG_ADJC_UV_MAX DSP2_MISC_REG_ADJC_UV_MAX -#define DSP2_MISC_REG_ADJC_UV_MAX_POS (24U) -#define DSP2_MISC_REG_ADJC_UV_MAX_LEN (8U) -#define DSP2_MISC_REG_ADJC_UV_MAX_MSK (((1U << DSP2_MISC_REG_ADJC_UV_MAX_LEN) - 1) << DSP2_MISC_REG_ADJC_UV_MAX_POS) -#define DSP2_MISC_REG_ADJC_UV_MAX_UMSK (~(((1U << DSP2_MISC_REG_ADJC_UV_MAX_LEN) - 1) << DSP2_MISC_REG_ADJC_UV_MAX_POS)) - -/* 0x128 : adjC_ctrl_2 */ -#define DSP2_MISC_ADJC_CTRL_2_OFFSET (0x128) -#define DSP2_MISC_RG_ADJC_SEL DSP2_MISC_RG_ADJC_SEL -#define DSP2_MISC_RG_ADJC_SEL_POS (0U) -#define DSP2_MISC_RG_ADJC_SEL_LEN (4U) -#define DSP2_MISC_RG_ADJC_SEL_MSK (((1U << DSP2_MISC_RG_ADJC_SEL_LEN) - 1) << DSP2_MISC_RG_ADJC_SEL_POS) -#define DSP2_MISC_RG_ADJC_SEL_UMSK (~(((1U << DSP2_MISC_RG_ADJC_SEL_LEN) - 1) << DSP2_MISC_RG_ADJC_SEL_POS)) -#define DSP2_MISC_REG_ADJC_UV_MUL0 DSP2_MISC_REG_ADJC_UV_MUL0 -#define DSP2_MISC_REG_ADJC_UV_MUL0_POS (10U) -#define DSP2_MISC_REG_ADJC_UV_MUL0_LEN (11U) -#define DSP2_MISC_REG_ADJC_UV_MUL0_MSK (((1U << DSP2_MISC_REG_ADJC_UV_MUL0_LEN) - 1) << DSP2_MISC_REG_ADJC_UV_MUL0_POS) -#define DSP2_MISC_REG_ADJC_UV_MUL0_UMSK (~(((1U << DSP2_MISC_REG_ADJC_UV_MUL0_LEN) - 1) << DSP2_MISC_REG_ADJC_UV_MUL0_POS)) -#define DSP2_MISC_REG_ADJC_UV_MUL1 DSP2_MISC_REG_ADJC_UV_MUL1 -#define DSP2_MISC_REG_ADJC_UV_MUL1_POS (21U) -#define DSP2_MISC_REG_ADJC_UV_MUL1_LEN (11U) -#define DSP2_MISC_REG_ADJC_UV_MUL1_MSK (((1U << DSP2_MISC_REG_ADJC_UV_MUL1_LEN) - 1) << DSP2_MISC_REG_ADJC_UV_MUL1_POS) -#define DSP2_MISC_REG_ADJC_UV_MUL1_UMSK (~(((1U << DSP2_MISC_REG_ADJC_UV_MUL1_LEN) - 1) << DSP2_MISC_REG_ADJC_UV_MUL1_POS)) - -/* 0x130 : adjD_ctrl_0 */ -#define DSP2_MISC_ADJD_CTRL_0_OFFSET (0x130) -#define DSP2_MISC_REG_ADJD_ADJ_EB DSP2_MISC_REG_ADJD_ADJ_EB -#define DSP2_MISC_REG_ADJD_ADJ_EB_POS (0U) -#define DSP2_MISC_REG_ADJD_ADJ_EB_LEN (1U) -#define DSP2_MISC_REG_ADJD_ADJ_EB_MSK (((1U << DSP2_MISC_REG_ADJD_ADJ_EB_LEN) - 1) << DSP2_MISC_REG_ADJD_ADJ_EB_POS) -#define DSP2_MISC_REG_ADJD_ADJ_EB_UMSK (~(((1U << DSP2_MISC_REG_ADJD_ADJ_EB_LEN) - 1) << DSP2_MISC_REG_ADJD_ADJ_EB_POS)) -#define DSP2_MISC_REG_ADJD_Y_LUMA DSP2_MISC_REG_ADJD_Y_LUMA -#define DSP2_MISC_REG_ADJD_Y_LUMA_POS (1U) -#define DSP2_MISC_REG_ADJD_Y_LUMA_LEN (9U) -#define DSP2_MISC_REG_ADJD_Y_LUMA_MSK (((1U << DSP2_MISC_REG_ADJD_Y_LUMA_LEN) - 1) << DSP2_MISC_REG_ADJD_Y_LUMA_POS) -#define DSP2_MISC_REG_ADJD_Y_LUMA_UMSK (~(((1U << DSP2_MISC_REG_ADJD_Y_LUMA_LEN) - 1) << DSP2_MISC_REG_ADJD_Y_LUMA_POS)) -#define DSP2_MISC_REG_ADJD_Y_MUL0 DSP2_MISC_REG_ADJD_Y_MUL0 -#define DSP2_MISC_REG_ADJD_Y_MUL0_POS (10U) -#define DSP2_MISC_REG_ADJD_Y_MUL0_LEN (11U) -#define DSP2_MISC_REG_ADJD_Y_MUL0_MSK (((1U << DSP2_MISC_REG_ADJD_Y_MUL0_LEN) - 1) << DSP2_MISC_REG_ADJD_Y_MUL0_POS) -#define DSP2_MISC_REG_ADJD_Y_MUL0_UMSK (~(((1U << DSP2_MISC_REG_ADJD_Y_MUL0_LEN) - 1) << DSP2_MISC_REG_ADJD_Y_MUL0_POS)) -#define DSP2_MISC_REG_ADJD_Y_MUL1 DSP2_MISC_REG_ADJD_Y_MUL1 -#define DSP2_MISC_REG_ADJD_Y_MUL1_POS (21U) -#define DSP2_MISC_REG_ADJD_Y_MUL1_LEN (11U) -#define DSP2_MISC_REG_ADJD_Y_MUL1_MSK (((1U << DSP2_MISC_REG_ADJD_Y_MUL1_LEN) - 1) << DSP2_MISC_REG_ADJD_Y_MUL1_POS) -#define DSP2_MISC_REG_ADJD_Y_MUL1_UMSK (~(((1U << DSP2_MISC_REG_ADJD_Y_MUL1_LEN) - 1) << DSP2_MISC_REG_ADJD_Y_MUL1_POS)) - -/* 0x134 : adjD_ctrl_1 */ -#define DSP2_MISC_ADJD_CTRL_1_OFFSET (0x134) -#define DSP2_MISC_REG_ADJD_Y_MIN DSP2_MISC_REG_ADJD_Y_MIN -#define DSP2_MISC_REG_ADJD_Y_MIN_POS (0U) -#define DSP2_MISC_REG_ADJD_Y_MIN_LEN (8U) -#define DSP2_MISC_REG_ADJD_Y_MIN_MSK (((1U << DSP2_MISC_REG_ADJD_Y_MIN_LEN) - 1) << DSP2_MISC_REG_ADJD_Y_MIN_POS) -#define DSP2_MISC_REG_ADJD_Y_MIN_UMSK (~(((1U << DSP2_MISC_REG_ADJD_Y_MIN_LEN) - 1) << DSP2_MISC_REG_ADJD_Y_MIN_POS)) -#define DSP2_MISC_REG_ADJD_Y_MAX DSP2_MISC_REG_ADJD_Y_MAX -#define DSP2_MISC_REG_ADJD_Y_MAX_POS (8U) -#define DSP2_MISC_REG_ADJD_Y_MAX_LEN (8U) -#define DSP2_MISC_REG_ADJD_Y_MAX_MSK (((1U << DSP2_MISC_REG_ADJD_Y_MAX_LEN) - 1) << DSP2_MISC_REG_ADJD_Y_MAX_POS) -#define DSP2_MISC_REG_ADJD_Y_MAX_UMSK (~(((1U << DSP2_MISC_REG_ADJD_Y_MAX_LEN) - 1) << DSP2_MISC_REG_ADJD_Y_MAX_POS)) -#define DSP2_MISC_REG_ADJD_UV_MIN DSP2_MISC_REG_ADJD_UV_MIN -#define DSP2_MISC_REG_ADJD_UV_MIN_POS (16U) -#define DSP2_MISC_REG_ADJD_UV_MIN_LEN (8U) -#define DSP2_MISC_REG_ADJD_UV_MIN_MSK (((1U << DSP2_MISC_REG_ADJD_UV_MIN_LEN) - 1) << DSP2_MISC_REG_ADJD_UV_MIN_POS) -#define DSP2_MISC_REG_ADJD_UV_MIN_UMSK (~(((1U << DSP2_MISC_REG_ADJD_UV_MIN_LEN) - 1) << DSP2_MISC_REG_ADJD_UV_MIN_POS)) -#define DSP2_MISC_REG_ADJD_UV_MAX DSP2_MISC_REG_ADJD_UV_MAX -#define DSP2_MISC_REG_ADJD_UV_MAX_POS (24U) -#define DSP2_MISC_REG_ADJD_UV_MAX_LEN (8U) -#define DSP2_MISC_REG_ADJD_UV_MAX_MSK (((1U << DSP2_MISC_REG_ADJD_UV_MAX_LEN) - 1) << DSP2_MISC_REG_ADJD_UV_MAX_POS) -#define DSP2_MISC_REG_ADJD_UV_MAX_UMSK (~(((1U << DSP2_MISC_REG_ADJD_UV_MAX_LEN) - 1) << DSP2_MISC_REG_ADJD_UV_MAX_POS)) - -/* 0x138 : adjD_ctrl_2 */ -#define DSP2_MISC_ADJD_CTRL_2_OFFSET (0x138) -#define DSP2_MISC_RG_ADJD_SEL DSP2_MISC_RG_ADJD_SEL -#define DSP2_MISC_RG_ADJD_SEL_POS (0U) -#define DSP2_MISC_RG_ADJD_SEL_LEN (4U) -#define DSP2_MISC_RG_ADJD_SEL_MSK (((1U << DSP2_MISC_RG_ADJD_SEL_LEN) - 1) << DSP2_MISC_RG_ADJD_SEL_POS) -#define DSP2_MISC_RG_ADJD_SEL_UMSK (~(((1U << DSP2_MISC_RG_ADJD_SEL_LEN) - 1) << DSP2_MISC_RG_ADJD_SEL_POS)) -#define DSP2_MISC_REG_ADJD_UV_MUL0 DSP2_MISC_REG_ADJD_UV_MUL0 -#define DSP2_MISC_REG_ADJD_UV_MUL0_POS (10U) -#define DSP2_MISC_REG_ADJD_UV_MUL0_LEN (11U) -#define DSP2_MISC_REG_ADJD_UV_MUL0_MSK (((1U << DSP2_MISC_REG_ADJD_UV_MUL0_LEN) - 1) << DSP2_MISC_REG_ADJD_UV_MUL0_POS) -#define DSP2_MISC_REG_ADJD_UV_MUL0_UMSK (~(((1U << DSP2_MISC_REG_ADJD_UV_MUL0_LEN) - 1) << DSP2_MISC_REG_ADJD_UV_MUL0_POS)) -#define DSP2_MISC_REG_ADJD_UV_MUL1 DSP2_MISC_REG_ADJD_UV_MUL1 -#define DSP2_MISC_REG_ADJD_UV_MUL1_POS (21U) -#define DSP2_MISC_REG_ADJD_UV_MUL1_LEN (11U) -#define DSP2_MISC_REG_ADJD_UV_MUL1_MSK (((1U << DSP2_MISC_REG_ADJD_UV_MUL1_LEN) - 1) << DSP2_MISC_REG_ADJD_UV_MUL1_POS) -#define DSP2_MISC_REG_ADJD_UV_MUL1_UMSK (~(((1U << DSP2_MISC_REG_ADJD_UV_MUL1_LEN) - 1) << DSP2_MISC_REG_ADJD_UV_MUL1_POS)) - -/* 0x160 : y2rA_config_0 */ -#define DSP2_MISC_Y2RA_CONFIG_0_OFFSET (0x160) -#define DSP2_MISC_RG_Y2RA_PRE_0 DSP2_MISC_RG_Y2RA_PRE_0 -#define DSP2_MISC_RG_Y2RA_PRE_0_POS (0U) -#define DSP2_MISC_RG_Y2RA_PRE_0_LEN (9U) -#define DSP2_MISC_RG_Y2RA_PRE_0_MSK (((1U << DSP2_MISC_RG_Y2RA_PRE_0_LEN) - 1) << DSP2_MISC_RG_Y2RA_PRE_0_POS) -#define DSP2_MISC_RG_Y2RA_PRE_0_UMSK (~(((1U << DSP2_MISC_RG_Y2RA_PRE_0_LEN) - 1) << DSP2_MISC_RG_Y2RA_PRE_0_POS)) -#define DSP2_MISC_RG_Y2RA_POS_0 DSP2_MISC_RG_Y2RA_POS_0 -#define DSP2_MISC_RG_Y2RA_POS_0_POS (16U) -#define DSP2_MISC_RG_Y2RA_POS_0_LEN (9U) -#define DSP2_MISC_RG_Y2RA_POS_0_MSK (((1U << DSP2_MISC_RG_Y2RA_POS_0_LEN) - 1) << DSP2_MISC_RG_Y2RA_POS_0_POS) -#define DSP2_MISC_RG_Y2RA_POS_0_UMSK (~(((1U << DSP2_MISC_RG_Y2RA_POS_0_LEN) - 1) << DSP2_MISC_RG_Y2RA_POS_0_POS)) -#define DSP2_MISC_RG_Y2RA_EN DSP2_MISC_RG_Y2RA_EN -#define DSP2_MISC_RG_Y2RA_EN_POS (27U) -#define DSP2_MISC_RG_Y2RA_EN_LEN (1U) -#define DSP2_MISC_RG_Y2RA_EN_MSK (((1U << DSP2_MISC_RG_Y2RA_EN_LEN) - 1) << DSP2_MISC_RG_Y2RA_EN_POS) -#define DSP2_MISC_RG_Y2RA_EN_UMSK (~(((1U << DSP2_MISC_RG_Y2RA_EN_LEN) - 1) << DSP2_MISC_RG_Y2RA_EN_POS)) -#define DSP2_MISC_RG_Y2RA_SEL DSP2_MISC_RG_Y2RA_SEL -#define DSP2_MISC_RG_Y2RA_SEL_POS (28U) -#define DSP2_MISC_RG_Y2RA_SEL_LEN (4U) -#define DSP2_MISC_RG_Y2RA_SEL_MSK (((1U << DSP2_MISC_RG_Y2RA_SEL_LEN) - 1) << DSP2_MISC_RG_Y2RA_SEL_POS) -#define DSP2_MISC_RG_Y2RA_SEL_UMSK (~(((1U << DSP2_MISC_RG_Y2RA_SEL_LEN) - 1) << DSP2_MISC_RG_Y2RA_SEL_POS)) - -/* 0x164 : y2rA_config_1 */ -#define DSP2_MISC_Y2RA_CONFIG_1_OFFSET (0x164) -#define DSP2_MISC_RG_Y2RA_PRE_1 DSP2_MISC_RG_Y2RA_PRE_1 -#define DSP2_MISC_RG_Y2RA_PRE_1_POS (0U) -#define DSP2_MISC_RG_Y2RA_PRE_1_LEN (9U) -#define DSP2_MISC_RG_Y2RA_PRE_1_MSK (((1U << DSP2_MISC_RG_Y2RA_PRE_1_LEN) - 1) << DSP2_MISC_RG_Y2RA_PRE_1_POS) -#define DSP2_MISC_RG_Y2RA_PRE_1_UMSK (~(((1U << DSP2_MISC_RG_Y2RA_PRE_1_LEN) - 1) << DSP2_MISC_RG_Y2RA_PRE_1_POS)) -#define DSP2_MISC_RG_Y2RA_POS_1 DSP2_MISC_RG_Y2RA_POS_1 -#define DSP2_MISC_RG_Y2RA_POS_1_POS (16U) -#define DSP2_MISC_RG_Y2RA_POS_1_LEN (9U) -#define DSP2_MISC_RG_Y2RA_POS_1_MSK (((1U << DSP2_MISC_RG_Y2RA_POS_1_LEN) - 1) << DSP2_MISC_RG_Y2RA_POS_1_POS) -#define DSP2_MISC_RG_Y2RA_POS_1_UMSK (~(((1U << DSP2_MISC_RG_Y2RA_POS_1_LEN) - 1) << DSP2_MISC_RG_Y2RA_POS_1_POS)) - -/* 0x168 : y2rA_config_2 */ -#define DSP2_MISC_Y2RA_CONFIG_2_OFFSET (0x168) -#define DSP2_MISC_RG_Y2RA_PRE_2 DSP2_MISC_RG_Y2RA_PRE_2 -#define DSP2_MISC_RG_Y2RA_PRE_2_POS (0U) -#define DSP2_MISC_RG_Y2RA_PRE_2_LEN (9U) -#define DSP2_MISC_RG_Y2RA_PRE_2_MSK (((1U << DSP2_MISC_RG_Y2RA_PRE_2_LEN) - 1) << DSP2_MISC_RG_Y2RA_PRE_2_POS) -#define DSP2_MISC_RG_Y2RA_PRE_2_UMSK (~(((1U << DSP2_MISC_RG_Y2RA_PRE_2_LEN) - 1) << DSP2_MISC_RG_Y2RA_PRE_2_POS)) -#define DSP2_MISC_RG_Y2RA_POS_2 DSP2_MISC_RG_Y2RA_POS_2 -#define DSP2_MISC_RG_Y2RA_POS_2_POS (16U) -#define DSP2_MISC_RG_Y2RA_POS_2_LEN (9U) -#define DSP2_MISC_RG_Y2RA_POS_2_MSK (((1U << DSP2_MISC_RG_Y2RA_POS_2_LEN) - 1) << DSP2_MISC_RG_Y2RA_POS_2_POS) -#define DSP2_MISC_RG_Y2RA_POS_2_UMSK (~(((1U << DSP2_MISC_RG_Y2RA_POS_2_LEN) - 1) << DSP2_MISC_RG_Y2RA_POS_2_POS)) - -/* 0x16C : y2rA_config_3 */ -#define DSP2_MISC_Y2RA_CONFIG_3_OFFSET (0x16C) -#define DSP2_MISC_RG_Y2RA_MTX_00 DSP2_MISC_RG_Y2RA_MTX_00 -#define DSP2_MISC_RG_Y2RA_MTX_00_POS (0U) -#define DSP2_MISC_RG_Y2RA_MTX_00_LEN (12U) -#define DSP2_MISC_RG_Y2RA_MTX_00_MSK (((1U << DSP2_MISC_RG_Y2RA_MTX_00_LEN) - 1) << DSP2_MISC_RG_Y2RA_MTX_00_POS) -#define DSP2_MISC_RG_Y2RA_MTX_00_UMSK (~(((1U << DSP2_MISC_RG_Y2RA_MTX_00_LEN) - 1) << DSP2_MISC_RG_Y2RA_MTX_00_POS)) -#define DSP2_MISC_RG_Y2RA_MTX_01 DSP2_MISC_RG_Y2RA_MTX_01 -#define DSP2_MISC_RG_Y2RA_MTX_01_POS (16U) -#define DSP2_MISC_RG_Y2RA_MTX_01_LEN (12U) -#define DSP2_MISC_RG_Y2RA_MTX_01_MSK (((1U << DSP2_MISC_RG_Y2RA_MTX_01_LEN) - 1) << DSP2_MISC_RG_Y2RA_MTX_01_POS) -#define DSP2_MISC_RG_Y2RA_MTX_01_UMSK (~(((1U << DSP2_MISC_RG_Y2RA_MTX_01_LEN) - 1) << DSP2_MISC_RG_Y2RA_MTX_01_POS)) - -/* 0x170 : y2rA_config_4 */ -#define DSP2_MISC_Y2RA_CONFIG_4_OFFSET (0x170) -#define DSP2_MISC_RG_Y2RA_MTX_02 DSP2_MISC_RG_Y2RA_MTX_02 -#define DSP2_MISC_RG_Y2RA_MTX_02_POS (0U) -#define DSP2_MISC_RG_Y2RA_MTX_02_LEN (12U) -#define DSP2_MISC_RG_Y2RA_MTX_02_MSK (((1U << DSP2_MISC_RG_Y2RA_MTX_02_LEN) - 1) << DSP2_MISC_RG_Y2RA_MTX_02_POS) -#define DSP2_MISC_RG_Y2RA_MTX_02_UMSK (~(((1U << DSP2_MISC_RG_Y2RA_MTX_02_LEN) - 1) << DSP2_MISC_RG_Y2RA_MTX_02_POS)) -#define DSP2_MISC_RG_Y2RA_MTX_10 DSP2_MISC_RG_Y2RA_MTX_10 -#define DSP2_MISC_RG_Y2RA_MTX_10_POS (16U) -#define DSP2_MISC_RG_Y2RA_MTX_10_LEN (12U) -#define DSP2_MISC_RG_Y2RA_MTX_10_MSK (((1U << DSP2_MISC_RG_Y2RA_MTX_10_LEN) - 1) << DSP2_MISC_RG_Y2RA_MTX_10_POS) -#define DSP2_MISC_RG_Y2RA_MTX_10_UMSK (~(((1U << DSP2_MISC_RG_Y2RA_MTX_10_LEN) - 1) << DSP2_MISC_RG_Y2RA_MTX_10_POS)) - -/* 0x174 : y2rA_config_5 */ -#define DSP2_MISC_Y2RA_CONFIG_5_OFFSET (0x174) -#define DSP2_MISC_RG_Y2RA_MTX_11 DSP2_MISC_RG_Y2RA_MTX_11 -#define DSP2_MISC_RG_Y2RA_MTX_11_POS (0U) -#define DSP2_MISC_RG_Y2RA_MTX_11_LEN (12U) -#define DSP2_MISC_RG_Y2RA_MTX_11_MSK (((1U << DSP2_MISC_RG_Y2RA_MTX_11_LEN) - 1) << DSP2_MISC_RG_Y2RA_MTX_11_POS) -#define DSP2_MISC_RG_Y2RA_MTX_11_UMSK (~(((1U << DSP2_MISC_RG_Y2RA_MTX_11_LEN) - 1) << DSP2_MISC_RG_Y2RA_MTX_11_POS)) -#define DSP2_MISC_RG_Y2RA_MTX_12 DSP2_MISC_RG_Y2RA_MTX_12 -#define DSP2_MISC_RG_Y2RA_MTX_12_POS (16U) -#define DSP2_MISC_RG_Y2RA_MTX_12_LEN (12U) -#define DSP2_MISC_RG_Y2RA_MTX_12_MSK (((1U << DSP2_MISC_RG_Y2RA_MTX_12_LEN) - 1) << DSP2_MISC_RG_Y2RA_MTX_12_POS) -#define DSP2_MISC_RG_Y2RA_MTX_12_UMSK (~(((1U << DSP2_MISC_RG_Y2RA_MTX_12_LEN) - 1) << DSP2_MISC_RG_Y2RA_MTX_12_POS)) - -/* 0x178 : y2rA_config_6 */ -#define DSP2_MISC_Y2RA_CONFIG_6_OFFSET (0x178) -#define DSP2_MISC_RG_Y2RA_MTX_20 DSP2_MISC_RG_Y2RA_MTX_20 -#define DSP2_MISC_RG_Y2RA_MTX_20_POS (0U) -#define DSP2_MISC_RG_Y2RA_MTX_20_LEN (12U) -#define DSP2_MISC_RG_Y2RA_MTX_20_MSK (((1U << DSP2_MISC_RG_Y2RA_MTX_20_LEN) - 1) << DSP2_MISC_RG_Y2RA_MTX_20_POS) -#define DSP2_MISC_RG_Y2RA_MTX_20_UMSK (~(((1U << DSP2_MISC_RG_Y2RA_MTX_20_LEN) - 1) << DSP2_MISC_RG_Y2RA_MTX_20_POS)) -#define DSP2_MISC_RG_Y2RA_MTX_21 DSP2_MISC_RG_Y2RA_MTX_21 -#define DSP2_MISC_RG_Y2RA_MTX_21_POS (16U) -#define DSP2_MISC_RG_Y2RA_MTX_21_LEN (12U) -#define DSP2_MISC_RG_Y2RA_MTX_21_MSK (((1U << DSP2_MISC_RG_Y2RA_MTX_21_LEN) - 1) << DSP2_MISC_RG_Y2RA_MTX_21_POS) -#define DSP2_MISC_RG_Y2RA_MTX_21_UMSK (~(((1U << DSP2_MISC_RG_Y2RA_MTX_21_LEN) - 1) << DSP2_MISC_RG_Y2RA_MTX_21_POS)) - -/* 0x17C : y2rA_config_7 */ -#define DSP2_MISC_Y2RA_CONFIG_7_OFFSET (0x17C) -#define DSP2_MISC_RG_Y2RA_MTX_22 DSP2_MISC_RG_Y2RA_MTX_22 -#define DSP2_MISC_RG_Y2RA_MTX_22_POS (0U) -#define DSP2_MISC_RG_Y2RA_MTX_22_LEN (12U) -#define DSP2_MISC_RG_Y2RA_MTX_22_MSK (((1U << DSP2_MISC_RG_Y2RA_MTX_22_LEN) - 1) << DSP2_MISC_RG_Y2RA_MTX_22_POS) -#define DSP2_MISC_RG_Y2RA_MTX_22_UMSK (~(((1U << DSP2_MISC_RG_Y2RA_MTX_22_LEN) - 1) << DSP2_MISC_RG_Y2RA_MTX_22_POS)) - -/* 0x180 : disp_rgb2yuv_config_0 */ -#define DSP2_MISC_DISP_RGB2YUV_CONFIG_0_OFFSET (0x180) -#define DSP2_MISC_RG_DISP_R2Y_PRE_0 DSP2_MISC_RG_DISP_R2Y_PRE_0 -#define DSP2_MISC_RG_DISP_R2Y_PRE_0_POS (0U) -#define DSP2_MISC_RG_DISP_R2Y_PRE_0_LEN (9U) -#define DSP2_MISC_RG_DISP_R2Y_PRE_0_MSK (((1U << DSP2_MISC_RG_DISP_R2Y_PRE_0_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_PRE_0_POS) -#define DSP2_MISC_RG_DISP_R2Y_PRE_0_UMSK (~(((1U << DSP2_MISC_RG_DISP_R2Y_PRE_0_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_PRE_0_POS)) -#define DSP2_MISC_RG_DISP_R2Y_PRE_1 DSP2_MISC_RG_DISP_R2Y_PRE_1 -#define DSP2_MISC_RG_DISP_R2Y_PRE_1_POS (10U) -#define DSP2_MISC_RG_DISP_R2Y_PRE_1_LEN (9U) -#define DSP2_MISC_RG_DISP_R2Y_PRE_1_MSK (((1U << DSP2_MISC_RG_DISP_R2Y_PRE_1_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_PRE_1_POS) -#define DSP2_MISC_RG_DISP_R2Y_PRE_1_UMSK (~(((1U << DSP2_MISC_RG_DISP_R2Y_PRE_1_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_PRE_1_POS)) -#define DSP2_MISC_RG_DISP_R2Y_PRE_2 DSP2_MISC_RG_DISP_R2Y_PRE_2 -#define DSP2_MISC_RG_DISP_R2Y_PRE_2_POS (20U) -#define DSP2_MISC_RG_DISP_R2Y_PRE_2_LEN (9U) -#define DSP2_MISC_RG_DISP_R2Y_PRE_2_MSK (((1U << DSP2_MISC_RG_DISP_R2Y_PRE_2_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_PRE_2_POS) -#define DSP2_MISC_RG_DISP_R2Y_PRE_2_UMSK (~(((1U << DSP2_MISC_RG_DISP_R2Y_PRE_2_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_PRE_2_POS)) -#define DSP2_MISC_RG_DISP_R2Y_EN DSP2_MISC_RG_DISP_R2Y_EN -#define DSP2_MISC_RG_DISP_R2Y_EN_POS (31U) -#define DSP2_MISC_RG_DISP_R2Y_EN_LEN (1U) -#define DSP2_MISC_RG_DISP_R2Y_EN_MSK (((1U << DSP2_MISC_RG_DISP_R2Y_EN_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_EN_POS) -#define DSP2_MISC_RG_DISP_R2Y_EN_UMSK (~(((1U << DSP2_MISC_RG_DISP_R2Y_EN_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_EN_POS)) - -/* 0x184 : disp_rgb2yuv_config_1 */ -#define DSP2_MISC_DISP_RGB2YUV_CONFIG_1_OFFSET (0x184) -#define DSP2_MISC_RG_DISP_R2Y_POS_0 DSP2_MISC_RG_DISP_R2Y_POS_0 -#define DSP2_MISC_RG_DISP_R2Y_POS_0_POS (0U) -#define DSP2_MISC_RG_DISP_R2Y_POS_0_LEN (9U) -#define DSP2_MISC_RG_DISP_R2Y_POS_0_MSK (((1U << DSP2_MISC_RG_DISP_R2Y_POS_0_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_POS_0_POS) -#define DSP2_MISC_RG_DISP_R2Y_POS_0_UMSK (~(((1U << DSP2_MISC_RG_DISP_R2Y_POS_0_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_POS_0_POS)) -#define DSP2_MISC_RG_DISP_R2Y_POS_1 DSP2_MISC_RG_DISP_R2Y_POS_1 -#define DSP2_MISC_RG_DISP_R2Y_POS_1_POS (10U) -#define DSP2_MISC_RG_DISP_R2Y_POS_1_LEN (9U) -#define DSP2_MISC_RG_DISP_R2Y_POS_1_MSK (((1U << DSP2_MISC_RG_DISP_R2Y_POS_1_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_POS_1_POS) -#define DSP2_MISC_RG_DISP_R2Y_POS_1_UMSK (~(((1U << DSP2_MISC_RG_DISP_R2Y_POS_1_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_POS_1_POS)) -#define DSP2_MISC_RG_DISP_R2Y_POS_2 DSP2_MISC_RG_DISP_R2Y_POS_2 -#define DSP2_MISC_RG_DISP_R2Y_POS_2_POS (20U) -#define DSP2_MISC_RG_DISP_R2Y_POS_2_LEN (9U) -#define DSP2_MISC_RG_DISP_R2Y_POS_2_MSK (((1U << DSP2_MISC_RG_DISP_R2Y_POS_2_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_POS_2_POS) -#define DSP2_MISC_RG_DISP_R2Y_POS_2_UMSK (~(((1U << DSP2_MISC_RG_DISP_R2Y_POS_2_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_POS_2_POS)) - -/* 0x188 : disp_rgb2yuv_config_2 */ -#define DSP2_MISC_DISP_RGB2YUV_CONFIG_2_OFFSET (0x188) -#define DSP2_MISC_RG_DISP_R2Y_MTX_00 DSP2_MISC_RG_DISP_R2Y_MTX_00 -#define DSP2_MISC_RG_DISP_R2Y_MTX_00_POS (0U) -#define DSP2_MISC_RG_DISP_R2Y_MTX_00_LEN (12U) -#define DSP2_MISC_RG_DISP_R2Y_MTX_00_MSK (((1U << DSP2_MISC_RG_DISP_R2Y_MTX_00_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_MTX_00_POS) -#define DSP2_MISC_RG_DISP_R2Y_MTX_00_UMSK (~(((1U << DSP2_MISC_RG_DISP_R2Y_MTX_00_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_MTX_00_POS)) -#define DSP2_MISC_RG_DISP_R2Y_MTX_01 DSP2_MISC_RG_DISP_R2Y_MTX_01 -#define DSP2_MISC_RG_DISP_R2Y_MTX_01_POS (12U) -#define DSP2_MISC_RG_DISP_R2Y_MTX_01_LEN (12U) -#define DSP2_MISC_RG_DISP_R2Y_MTX_01_MSK (((1U << DSP2_MISC_RG_DISP_R2Y_MTX_01_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_MTX_01_POS) -#define DSP2_MISC_RG_DISP_R2Y_MTX_01_UMSK (~(((1U << DSP2_MISC_RG_DISP_R2Y_MTX_01_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_MTX_01_POS)) -#define DSP2_MISC_RG_DISP_R2Y_MTX_02_L DSP2_MISC_RG_DISP_R2Y_MTX_02_L -#define DSP2_MISC_RG_DISP_R2Y_MTX_02_L_POS (24U) -#define DSP2_MISC_RG_DISP_R2Y_MTX_02_L_LEN (8U) -#define DSP2_MISC_RG_DISP_R2Y_MTX_02_L_MSK (((1U << DSP2_MISC_RG_DISP_R2Y_MTX_02_L_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_MTX_02_L_POS) -#define DSP2_MISC_RG_DISP_R2Y_MTX_02_L_UMSK (~(((1U << DSP2_MISC_RG_DISP_R2Y_MTX_02_L_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_MTX_02_L_POS)) - -/* 0x18C : disp_rgb2yuv_config_3 */ -#define DSP2_MISC_DISP_RGB2YUV_CONFIG_3_OFFSET (0x18C) -#define DSP2_MISC_RG_DISP_R2Y_MTX_02_U DSP2_MISC_RG_DISP_R2Y_MTX_02_U -#define DSP2_MISC_RG_DISP_R2Y_MTX_02_U_POS (0U) -#define DSP2_MISC_RG_DISP_R2Y_MTX_02_U_LEN (4U) -#define DSP2_MISC_RG_DISP_R2Y_MTX_02_U_MSK (((1U << DSP2_MISC_RG_DISP_R2Y_MTX_02_U_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_MTX_02_U_POS) -#define DSP2_MISC_RG_DISP_R2Y_MTX_02_U_UMSK (~(((1U << DSP2_MISC_RG_DISP_R2Y_MTX_02_U_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_MTX_02_U_POS)) -#define DSP2_MISC_RG_DISP_R2Y_MTX_10 DSP2_MISC_RG_DISP_R2Y_MTX_10 -#define DSP2_MISC_RG_DISP_R2Y_MTX_10_POS (4U) -#define DSP2_MISC_RG_DISP_R2Y_MTX_10_LEN (12U) -#define DSP2_MISC_RG_DISP_R2Y_MTX_10_MSK (((1U << DSP2_MISC_RG_DISP_R2Y_MTX_10_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_MTX_10_POS) -#define DSP2_MISC_RG_DISP_R2Y_MTX_10_UMSK (~(((1U << DSP2_MISC_RG_DISP_R2Y_MTX_10_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_MTX_10_POS)) -#define DSP2_MISC_RG_DISP_R2Y_MTX_11 DSP2_MISC_RG_DISP_R2Y_MTX_11 -#define DSP2_MISC_RG_DISP_R2Y_MTX_11_POS (16U) -#define DSP2_MISC_RG_DISP_R2Y_MTX_11_LEN (12U) -#define DSP2_MISC_RG_DISP_R2Y_MTX_11_MSK (((1U << DSP2_MISC_RG_DISP_R2Y_MTX_11_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_MTX_11_POS) -#define DSP2_MISC_RG_DISP_R2Y_MTX_11_UMSK (~(((1U << DSP2_MISC_RG_DISP_R2Y_MTX_11_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_MTX_11_POS)) -#define DSP2_MISC_RG_DISP_R2Y_MTX_12_L DSP2_MISC_RG_DISP_R2Y_MTX_12_L -#define DSP2_MISC_RG_DISP_R2Y_MTX_12_L_POS (28U) -#define DSP2_MISC_RG_DISP_R2Y_MTX_12_L_LEN (4U) -#define DSP2_MISC_RG_DISP_R2Y_MTX_12_L_MSK (((1U << DSP2_MISC_RG_DISP_R2Y_MTX_12_L_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_MTX_12_L_POS) -#define DSP2_MISC_RG_DISP_R2Y_MTX_12_L_UMSK (~(((1U << DSP2_MISC_RG_DISP_R2Y_MTX_12_L_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_MTX_12_L_POS)) - -/* 0x190 : disp_rgb2yuv_config_4 */ -#define DSP2_MISC_DISP_RGB2YUV_CONFIG_4_OFFSET (0x190) -#define DSP2_MISC_RG_DISP_R2Y_MTX_12_U DSP2_MISC_RG_DISP_R2Y_MTX_12_U -#define DSP2_MISC_RG_DISP_R2Y_MTX_12_U_POS (0U) -#define DSP2_MISC_RG_DISP_R2Y_MTX_12_U_LEN (8U) -#define DSP2_MISC_RG_DISP_R2Y_MTX_12_U_MSK (((1U << DSP2_MISC_RG_DISP_R2Y_MTX_12_U_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_MTX_12_U_POS) -#define DSP2_MISC_RG_DISP_R2Y_MTX_12_U_UMSK (~(((1U << DSP2_MISC_RG_DISP_R2Y_MTX_12_U_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_MTX_12_U_POS)) -#define DSP2_MISC_RG_DISP_R2Y_MTX_20 DSP2_MISC_RG_DISP_R2Y_MTX_20 -#define DSP2_MISC_RG_DISP_R2Y_MTX_20_POS (8U) -#define DSP2_MISC_RG_DISP_R2Y_MTX_20_LEN (12U) -#define DSP2_MISC_RG_DISP_R2Y_MTX_20_MSK (((1U << DSP2_MISC_RG_DISP_R2Y_MTX_20_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_MTX_20_POS) -#define DSP2_MISC_RG_DISP_R2Y_MTX_20_UMSK (~(((1U << DSP2_MISC_RG_DISP_R2Y_MTX_20_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_MTX_20_POS)) -#define DSP2_MISC_RG_DISP_R2Y_MTX_21 DSP2_MISC_RG_DISP_R2Y_MTX_21 -#define DSP2_MISC_RG_DISP_R2Y_MTX_21_POS (20U) -#define DSP2_MISC_RG_DISP_R2Y_MTX_21_LEN (12U) -#define DSP2_MISC_RG_DISP_R2Y_MTX_21_MSK (((1U << DSP2_MISC_RG_DISP_R2Y_MTX_21_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_MTX_21_POS) -#define DSP2_MISC_RG_DISP_R2Y_MTX_21_UMSK (~(((1U << DSP2_MISC_RG_DISP_R2Y_MTX_21_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_MTX_21_POS)) - -/* 0x194 : disp_rgb2yuv_config_5 */ -#define DSP2_MISC_DISP_RGB2YUV_CONFIG_5_OFFSET (0x194) -#define DSP2_MISC_RG_DISP_R2Y_MTX_22 DSP2_MISC_RG_DISP_R2Y_MTX_22 -#define DSP2_MISC_RG_DISP_R2Y_MTX_22_POS (0U) -#define DSP2_MISC_RG_DISP_R2Y_MTX_22_LEN (12U) -#define DSP2_MISC_RG_DISP_R2Y_MTX_22_MSK (((1U << DSP2_MISC_RG_DISP_R2Y_MTX_22_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_MTX_22_POS) -#define DSP2_MISC_RG_DISP_R2Y_MTX_22_UMSK (~(((1U << DSP2_MISC_RG_DISP_R2Y_MTX_22_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_MTX_22_POS)) - -/* 0x1C0 : cropA_hsync */ -#define DSP2_MISC_CROPA_HSYNC_OFFSET (0x1C0) -#define DSP2_MISC_REG_CROPA_HSYNC_START DSP2_MISC_REG_CROPA_HSYNC_START -#define DSP2_MISC_REG_CROPA_HSYNC_START_POS (0U) -#define DSP2_MISC_REG_CROPA_HSYNC_START_LEN (16U) -#define DSP2_MISC_REG_CROPA_HSYNC_START_MSK (((1U << DSP2_MISC_REG_CROPA_HSYNC_START_LEN) - 1) << DSP2_MISC_REG_CROPA_HSYNC_START_POS) -#define DSP2_MISC_REG_CROPA_HSYNC_START_UMSK (~(((1U << DSP2_MISC_REG_CROPA_HSYNC_START_LEN) - 1) << DSP2_MISC_REG_CROPA_HSYNC_START_POS)) -#define DSP2_MISC_REG_CROPA_HSYNC_END DSP2_MISC_REG_CROPA_HSYNC_END -#define DSP2_MISC_REG_CROPA_HSYNC_END_POS (16U) -#define DSP2_MISC_REG_CROPA_HSYNC_END_LEN (16U) -#define DSP2_MISC_REG_CROPA_HSYNC_END_MSK (((1U << DSP2_MISC_REG_CROPA_HSYNC_END_LEN) - 1) << DSP2_MISC_REG_CROPA_HSYNC_END_POS) -#define DSP2_MISC_REG_CROPA_HSYNC_END_UMSK (~(((1U << DSP2_MISC_REG_CROPA_HSYNC_END_LEN) - 1) << DSP2_MISC_REG_CROPA_HSYNC_END_POS)) - -/* 0x1C4 : cropA_vsync */ -#define DSP2_MISC_CROPA_VSYNC_OFFSET (0x1C4) -#define DSP2_MISC_REG_CROPA_VSYNC_START DSP2_MISC_REG_CROPA_VSYNC_START -#define DSP2_MISC_REG_CROPA_VSYNC_START_POS (0U) -#define DSP2_MISC_REG_CROPA_VSYNC_START_LEN (16U) -#define DSP2_MISC_REG_CROPA_VSYNC_START_MSK (((1U << DSP2_MISC_REG_CROPA_VSYNC_START_LEN) - 1) << DSP2_MISC_REG_CROPA_VSYNC_START_POS) -#define DSP2_MISC_REG_CROPA_VSYNC_START_UMSK (~(((1U << DSP2_MISC_REG_CROPA_VSYNC_START_LEN) - 1) << DSP2_MISC_REG_CROPA_VSYNC_START_POS)) -#define DSP2_MISC_REG_CROPA_VSYNC_END DSP2_MISC_REG_CROPA_VSYNC_END -#define DSP2_MISC_REG_CROPA_VSYNC_END_POS (16U) -#define DSP2_MISC_REG_CROPA_VSYNC_END_LEN (16U) -#define DSP2_MISC_REG_CROPA_VSYNC_END_MSK (((1U << DSP2_MISC_REG_CROPA_VSYNC_END_LEN) - 1) << DSP2_MISC_REG_CROPA_VSYNC_END_POS) -#define DSP2_MISC_REG_CROPA_VSYNC_END_UMSK (~(((1U << DSP2_MISC_REG_CROPA_VSYNC_END_LEN) - 1) << DSP2_MISC_REG_CROPA_VSYNC_END_POS)) - -/* 0x1C8 : cropB_hsync */ -#define DSP2_MISC_CROPB_HSYNC_OFFSET (0x1C8) -#define DSP2_MISC_REG_CROPB_HSYNC_START DSP2_MISC_REG_CROPB_HSYNC_START -#define DSP2_MISC_REG_CROPB_HSYNC_START_POS (0U) -#define DSP2_MISC_REG_CROPB_HSYNC_START_LEN (16U) -#define DSP2_MISC_REG_CROPB_HSYNC_START_MSK (((1U << DSP2_MISC_REG_CROPB_HSYNC_START_LEN) - 1) << DSP2_MISC_REG_CROPB_HSYNC_START_POS) -#define DSP2_MISC_REG_CROPB_HSYNC_START_UMSK (~(((1U << DSP2_MISC_REG_CROPB_HSYNC_START_LEN) - 1) << DSP2_MISC_REG_CROPB_HSYNC_START_POS)) -#define DSP2_MISC_REG_CROPB_HSYNC_END DSP2_MISC_REG_CROPB_HSYNC_END -#define DSP2_MISC_REG_CROPB_HSYNC_END_POS (16U) -#define DSP2_MISC_REG_CROPB_HSYNC_END_LEN (16U) -#define DSP2_MISC_REG_CROPB_HSYNC_END_MSK (((1U << DSP2_MISC_REG_CROPB_HSYNC_END_LEN) - 1) << DSP2_MISC_REG_CROPB_HSYNC_END_POS) -#define DSP2_MISC_REG_CROPB_HSYNC_END_UMSK (~(((1U << DSP2_MISC_REG_CROPB_HSYNC_END_LEN) - 1) << DSP2_MISC_REG_CROPB_HSYNC_END_POS)) - -/* 0x1CC : cropB_vsync */ -#define DSP2_MISC_CROPB_VSYNC_OFFSET (0x1CC) -#define DSP2_MISC_REG_CROPB_VSYNC_START DSP2_MISC_REG_CROPB_VSYNC_START -#define DSP2_MISC_REG_CROPB_VSYNC_START_POS (0U) -#define DSP2_MISC_REG_CROPB_VSYNC_START_LEN (16U) -#define DSP2_MISC_REG_CROPB_VSYNC_START_MSK (((1U << DSP2_MISC_REG_CROPB_VSYNC_START_LEN) - 1) << DSP2_MISC_REG_CROPB_VSYNC_START_POS) -#define DSP2_MISC_REG_CROPB_VSYNC_START_UMSK (~(((1U << DSP2_MISC_REG_CROPB_VSYNC_START_LEN) - 1) << DSP2_MISC_REG_CROPB_VSYNC_START_POS)) -#define DSP2_MISC_REG_CROPB_VSYNC_END DSP2_MISC_REG_CROPB_VSYNC_END -#define DSP2_MISC_REG_CROPB_VSYNC_END_POS (16U) -#define DSP2_MISC_REG_CROPB_VSYNC_END_LEN (16U) -#define DSP2_MISC_REG_CROPB_VSYNC_END_MSK (((1U << DSP2_MISC_REG_CROPB_VSYNC_END_LEN) - 1) << DSP2_MISC_REG_CROPB_VSYNC_END_POS) -#define DSP2_MISC_REG_CROPB_VSYNC_END_UMSK (~(((1U << DSP2_MISC_REG_CROPB_VSYNC_END_LEN) - 1) << DSP2_MISC_REG_CROPB_VSYNC_END_POS)) - -/* 0x1D0 : cropC_hsync */ -#define DSP2_MISC_CROPC_HSYNC_OFFSET (0x1D0) -#define DSP2_MISC_REG_CROPC_HSYNC_START DSP2_MISC_REG_CROPC_HSYNC_START -#define DSP2_MISC_REG_CROPC_HSYNC_START_POS (0U) -#define DSP2_MISC_REG_CROPC_HSYNC_START_LEN (16U) -#define DSP2_MISC_REG_CROPC_HSYNC_START_MSK (((1U << DSP2_MISC_REG_CROPC_HSYNC_START_LEN) - 1) << DSP2_MISC_REG_CROPC_HSYNC_START_POS) -#define DSP2_MISC_REG_CROPC_HSYNC_START_UMSK (~(((1U << DSP2_MISC_REG_CROPC_HSYNC_START_LEN) - 1) << DSP2_MISC_REG_CROPC_HSYNC_START_POS)) -#define DSP2_MISC_REG_CROPC_HSYNC_END DSP2_MISC_REG_CROPC_HSYNC_END -#define DSP2_MISC_REG_CROPC_HSYNC_END_POS (16U) -#define DSP2_MISC_REG_CROPC_HSYNC_END_LEN (16U) -#define DSP2_MISC_REG_CROPC_HSYNC_END_MSK (((1U << DSP2_MISC_REG_CROPC_HSYNC_END_LEN) - 1) << DSP2_MISC_REG_CROPC_HSYNC_END_POS) -#define DSP2_MISC_REG_CROPC_HSYNC_END_UMSK (~(((1U << DSP2_MISC_REG_CROPC_HSYNC_END_LEN) - 1) << DSP2_MISC_REG_CROPC_HSYNC_END_POS)) - -/* 0x1D4 : cropC_vsync */ -#define DSP2_MISC_CROPC_VSYNC_OFFSET (0x1D4) -#define DSP2_MISC_REG_CROPC_VSYNC_START DSP2_MISC_REG_CROPC_VSYNC_START -#define DSP2_MISC_REG_CROPC_VSYNC_START_POS (0U) -#define DSP2_MISC_REG_CROPC_VSYNC_START_LEN (16U) -#define DSP2_MISC_REG_CROPC_VSYNC_START_MSK (((1U << DSP2_MISC_REG_CROPC_VSYNC_START_LEN) - 1) << DSP2_MISC_REG_CROPC_VSYNC_START_POS) -#define DSP2_MISC_REG_CROPC_VSYNC_START_UMSK (~(((1U << DSP2_MISC_REG_CROPC_VSYNC_START_LEN) - 1) << DSP2_MISC_REG_CROPC_VSYNC_START_POS)) -#define DSP2_MISC_REG_CROPC_VSYNC_END DSP2_MISC_REG_CROPC_VSYNC_END -#define DSP2_MISC_REG_CROPC_VSYNC_END_POS (16U) -#define DSP2_MISC_REG_CROPC_VSYNC_END_LEN (16U) -#define DSP2_MISC_REG_CROPC_VSYNC_END_MSK (((1U << DSP2_MISC_REG_CROPC_VSYNC_END_LEN) - 1) << DSP2_MISC_REG_CROPC_VSYNC_END_POS) -#define DSP2_MISC_REG_CROPC_VSYNC_END_UMSK (~(((1U << DSP2_MISC_REG_CROPC_VSYNC_END_LEN) - 1) << DSP2_MISC_REG_CROPC_VSYNC_END_POS)) - -/* 0x1D8 : cropD_hsync */ -#define DSP2_MISC_CROPD_HSYNC_OFFSET (0x1D8) -#define DSP2_MISC_REG_CROPD_HSYNC_START DSP2_MISC_REG_CROPD_HSYNC_START -#define DSP2_MISC_REG_CROPD_HSYNC_START_POS (0U) -#define DSP2_MISC_REG_CROPD_HSYNC_START_LEN (16U) -#define DSP2_MISC_REG_CROPD_HSYNC_START_MSK (((1U << DSP2_MISC_REG_CROPD_HSYNC_START_LEN) - 1) << DSP2_MISC_REG_CROPD_HSYNC_START_POS) -#define DSP2_MISC_REG_CROPD_HSYNC_START_UMSK (~(((1U << DSP2_MISC_REG_CROPD_HSYNC_START_LEN) - 1) << DSP2_MISC_REG_CROPD_HSYNC_START_POS)) -#define DSP2_MISC_REG_CROPD_HSYNC_END DSP2_MISC_REG_CROPD_HSYNC_END -#define DSP2_MISC_REG_CROPD_HSYNC_END_POS (16U) -#define DSP2_MISC_REG_CROPD_HSYNC_END_LEN (16U) -#define DSP2_MISC_REG_CROPD_HSYNC_END_MSK (((1U << DSP2_MISC_REG_CROPD_HSYNC_END_LEN) - 1) << DSP2_MISC_REG_CROPD_HSYNC_END_POS) -#define DSP2_MISC_REG_CROPD_HSYNC_END_UMSK (~(((1U << DSP2_MISC_REG_CROPD_HSYNC_END_LEN) - 1) << DSP2_MISC_REG_CROPD_HSYNC_END_POS)) - -/* 0x1DC : cropD_vsync */ -#define DSP2_MISC_CROPD_VSYNC_OFFSET (0x1DC) -#define DSP2_MISC_REG_CROPD_VSYNC_START DSP2_MISC_REG_CROPD_VSYNC_START -#define DSP2_MISC_REG_CROPD_VSYNC_START_POS (0U) -#define DSP2_MISC_REG_CROPD_VSYNC_START_LEN (16U) -#define DSP2_MISC_REG_CROPD_VSYNC_START_MSK (((1U << DSP2_MISC_REG_CROPD_VSYNC_START_LEN) - 1) << DSP2_MISC_REG_CROPD_VSYNC_START_POS) -#define DSP2_MISC_REG_CROPD_VSYNC_START_UMSK (~(((1U << DSP2_MISC_REG_CROPD_VSYNC_START_LEN) - 1) << DSP2_MISC_REG_CROPD_VSYNC_START_POS)) -#define DSP2_MISC_REG_CROPD_VSYNC_END DSP2_MISC_REG_CROPD_VSYNC_END -#define DSP2_MISC_REG_CROPD_VSYNC_END_POS (16U) -#define DSP2_MISC_REG_CROPD_VSYNC_END_LEN (16U) -#define DSP2_MISC_REG_CROPD_VSYNC_END_MSK (((1U << DSP2_MISC_REG_CROPD_VSYNC_END_LEN) - 1) << DSP2_MISC_REG_CROPD_VSYNC_END_POS) -#define DSP2_MISC_REG_CROPD_VSYNC_END_UMSK (~(((1U << DSP2_MISC_REG_CROPD_VSYNC_END_LEN) - 1) << DSP2_MISC_REG_CROPD_VSYNC_END_POS)) - -/* 0x1E0 : crop_enable */ -#define DSP2_MISC_CROP_ENABLE_OFFSET (0x1E0) -#define DSP2_MISC_REG_CROPA_ENABLE DSP2_MISC_REG_CROPA_ENABLE -#define DSP2_MISC_REG_CROPA_ENABLE_POS (0U) -#define DSP2_MISC_REG_CROPA_ENABLE_LEN (1U) -#define DSP2_MISC_REG_CROPA_ENABLE_MSK (((1U << DSP2_MISC_REG_CROPA_ENABLE_LEN) - 1) << DSP2_MISC_REG_CROPA_ENABLE_POS) -#define DSP2_MISC_REG_CROPA_ENABLE_UMSK (~(((1U << DSP2_MISC_REG_CROPA_ENABLE_LEN) - 1) << DSP2_MISC_REG_CROPA_ENABLE_POS)) -#define DSP2_MISC_REG_CROPB_ENABLE DSP2_MISC_REG_CROPB_ENABLE -#define DSP2_MISC_REG_CROPB_ENABLE_POS (1U) -#define DSP2_MISC_REG_CROPB_ENABLE_LEN (1U) -#define DSP2_MISC_REG_CROPB_ENABLE_MSK (((1U << DSP2_MISC_REG_CROPB_ENABLE_LEN) - 1) << DSP2_MISC_REG_CROPB_ENABLE_POS) -#define DSP2_MISC_REG_CROPB_ENABLE_UMSK (~(((1U << DSP2_MISC_REG_CROPB_ENABLE_LEN) - 1) << DSP2_MISC_REG_CROPB_ENABLE_POS)) -#define DSP2_MISC_REG_CROPC_ENABLE DSP2_MISC_REG_CROPC_ENABLE -#define DSP2_MISC_REG_CROPC_ENABLE_POS (2U) -#define DSP2_MISC_REG_CROPC_ENABLE_LEN (1U) -#define DSP2_MISC_REG_CROPC_ENABLE_MSK (((1U << DSP2_MISC_REG_CROPC_ENABLE_LEN) - 1) << DSP2_MISC_REG_CROPC_ENABLE_POS) -#define DSP2_MISC_REG_CROPC_ENABLE_UMSK (~(((1U << DSP2_MISC_REG_CROPC_ENABLE_LEN) - 1) << DSP2_MISC_REG_CROPC_ENABLE_POS)) -#define DSP2_MISC_REG_CROPD_ENABLE DSP2_MISC_REG_CROPD_ENABLE -#define DSP2_MISC_REG_CROPD_ENABLE_POS (3U) -#define DSP2_MISC_REG_CROPD_ENABLE_LEN (1U) -#define DSP2_MISC_REG_CROPD_ENABLE_MSK (((1U << DSP2_MISC_REG_CROPD_ENABLE_LEN) - 1) << DSP2_MISC_REG_CROPD_ENABLE_POS) -#define DSP2_MISC_REG_CROPD_ENABLE_UMSK (~(((1U << DSP2_MISC_REG_CROPD_ENABLE_LEN) - 1) << DSP2_MISC_REG_CROPD_ENABLE_POS)) - -/* 0x1FC : disp_gma_cfg */ -#define DSP2_MISC_DISP_GMA_CFG_OFFSET (0x1FC) -#define DSP2_MISC_REG_DP_GMA_CH0_EN DSP2_MISC_REG_DP_GMA_CH0_EN -#define DSP2_MISC_REG_DP_GMA_CH0_EN_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CH0_EN_LEN (1U) -#define DSP2_MISC_REG_DP_GMA_CH0_EN_MSK (((1U << DSP2_MISC_REG_DP_GMA_CH0_EN_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CH0_EN_POS) -#define DSP2_MISC_REG_DP_GMA_CH0_EN_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CH0_EN_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CH0_EN_POS)) -#define DSP2_MISC_REG_DP_GMA_CH1_EN DSP2_MISC_REG_DP_GMA_CH1_EN -#define DSP2_MISC_REG_DP_GMA_CH1_EN_POS (1U) -#define DSP2_MISC_REG_DP_GMA_CH1_EN_LEN (1U) -#define DSP2_MISC_REG_DP_GMA_CH1_EN_MSK (((1U << DSP2_MISC_REG_DP_GMA_CH1_EN_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CH1_EN_POS) -#define DSP2_MISC_REG_DP_GMA_CH1_EN_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CH1_EN_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CH1_EN_POS)) -#define DSP2_MISC_REG_DP_GMA_CH2_EN DSP2_MISC_REG_DP_GMA_CH2_EN -#define DSP2_MISC_REG_DP_GMA_CH2_EN_POS (2U) -#define DSP2_MISC_REG_DP_GMA_CH2_EN_LEN (1U) -#define DSP2_MISC_REG_DP_GMA_CH2_EN_MSK (((1U << DSP2_MISC_REG_DP_GMA_CH2_EN_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CH2_EN_POS) -#define DSP2_MISC_REG_DP_GMA_CH2_EN_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CH2_EN_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CH2_EN_POS)) - -/* 0x200 : disp_gma_curve_00 */ -#define DSP2_MISC_DISP_GMA_CURVE_00_OFFSET (0x200) -#define DSP2_MISC_REG_DP_GMA_CURVE_00 DSP2_MISC_REG_DP_GMA_CURVE_00 -#define DSP2_MISC_REG_DP_GMA_CURVE_00_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_00_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_00_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_00_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_00_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_00_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_00_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_00_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_01 DSP2_MISC_REG_DP_GMA_CURVE_01 -#define DSP2_MISC_REG_DP_GMA_CURVE_01_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_01_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_01_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_01_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_01_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_01_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_01_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_01_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_02 DSP2_MISC_REG_DP_GMA_CURVE_02 -#define DSP2_MISC_REG_DP_GMA_CURVE_02_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_02_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_02_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_02_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_02_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_02_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_02_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_02_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_03 DSP2_MISC_REG_DP_GMA_CURVE_03 -#define DSP2_MISC_REG_DP_GMA_CURVE_03_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_03_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_03_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_03_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_03_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_03_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_03_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_03_POS)) - -/* 0x204 : disp_gma_curve_04 */ -#define DSP2_MISC_DISP_GMA_CURVE_04_OFFSET (0x204) -#define DSP2_MISC_REG_DP_GMA_CURVE_04 DSP2_MISC_REG_DP_GMA_CURVE_04 -#define DSP2_MISC_REG_DP_GMA_CURVE_04_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_04_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_04_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_04_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_04_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_04_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_04_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_04_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_05 DSP2_MISC_REG_DP_GMA_CURVE_05 -#define DSP2_MISC_REG_DP_GMA_CURVE_05_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_05_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_05_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_05_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_05_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_05_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_05_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_05_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_06 DSP2_MISC_REG_DP_GMA_CURVE_06 -#define DSP2_MISC_REG_DP_GMA_CURVE_06_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_06_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_06_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_06_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_06_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_06_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_06_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_06_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_07 DSP2_MISC_REG_DP_GMA_CURVE_07 -#define DSP2_MISC_REG_DP_GMA_CURVE_07_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_07_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_07_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_07_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_07_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_07_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_07_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_07_POS)) - -/* 0x208 : disp_gma_curve_08 */ -#define DSP2_MISC_DISP_GMA_CURVE_08_OFFSET (0x208) -#define DSP2_MISC_REG_DP_GMA_CURVE_08 DSP2_MISC_REG_DP_GMA_CURVE_08 -#define DSP2_MISC_REG_DP_GMA_CURVE_08_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_08_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_08_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_08_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_08_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_08_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_08_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_08_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_09 DSP2_MISC_REG_DP_GMA_CURVE_09 -#define DSP2_MISC_REG_DP_GMA_CURVE_09_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_09_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_09_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_09_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_09_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_09_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_09_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_09_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_0A DSP2_MISC_REG_DP_GMA_CURVE_0A -#define DSP2_MISC_REG_DP_GMA_CURVE_0A_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_0A_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_0A_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_0A_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_0A_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_0A_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_0A_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_0A_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_0B DSP2_MISC_REG_DP_GMA_CURVE_0B -#define DSP2_MISC_REG_DP_GMA_CURVE_0B_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_0B_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_0B_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_0B_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_0B_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_0B_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_0B_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_0B_POS)) - -/* 0x20C : disp_gma_curve_0c */ -#define DSP2_MISC_DISP_GMA_CURVE_0C_OFFSET (0x20C) -#define DSP2_MISC_REG_DP_GMA_CURVE_0C DSP2_MISC_REG_DP_GMA_CURVE_0C -#define DSP2_MISC_REG_DP_GMA_CURVE_0C_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_0C_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_0C_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_0C_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_0C_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_0C_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_0C_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_0C_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_0D DSP2_MISC_REG_DP_GMA_CURVE_0D -#define DSP2_MISC_REG_DP_GMA_CURVE_0D_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_0D_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_0D_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_0D_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_0D_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_0D_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_0D_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_0D_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_0E DSP2_MISC_REG_DP_GMA_CURVE_0E -#define DSP2_MISC_REG_DP_GMA_CURVE_0E_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_0E_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_0E_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_0E_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_0E_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_0E_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_0E_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_0E_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_0F DSP2_MISC_REG_DP_GMA_CURVE_0F -#define DSP2_MISC_REG_DP_GMA_CURVE_0F_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_0F_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_0F_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_0F_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_0F_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_0F_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_0F_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_0F_POS)) - -/* 0x210 : disp_gma_curve_10 */ -#define DSP2_MISC_DISP_GMA_CURVE_10_OFFSET (0x210) -#define DSP2_MISC_REG_DP_GMA_CURVE_10 DSP2_MISC_REG_DP_GMA_CURVE_10 -#define DSP2_MISC_REG_DP_GMA_CURVE_10_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_10_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_10_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_10_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_10_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_10_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_10_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_10_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_11 DSP2_MISC_REG_DP_GMA_CURVE_11 -#define DSP2_MISC_REG_DP_GMA_CURVE_11_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_11_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_11_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_11_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_11_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_11_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_11_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_11_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_12 DSP2_MISC_REG_DP_GMA_CURVE_12 -#define DSP2_MISC_REG_DP_GMA_CURVE_12_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_12_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_12_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_12_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_12_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_12_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_12_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_12_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_13 DSP2_MISC_REG_DP_GMA_CURVE_13 -#define DSP2_MISC_REG_DP_GMA_CURVE_13_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_13_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_13_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_13_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_13_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_13_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_13_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_13_POS)) - -/* 0x214 : disp_gma_curve_14 */ -#define DSP2_MISC_DISP_GMA_CURVE_14_OFFSET (0x214) -#define DSP2_MISC_REG_DP_GMA_CURVE_14 DSP2_MISC_REG_DP_GMA_CURVE_14 -#define DSP2_MISC_REG_DP_GMA_CURVE_14_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_14_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_14_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_14_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_14_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_14_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_14_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_14_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_15 DSP2_MISC_REG_DP_GMA_CURVE_15 -#define DSP2_MISC_REG_DP_GMA_CURVE_15_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_15_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_15_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_15_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_15_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_15_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_15_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_15_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_16 DSP2_MISC_REG_DP_GMA_CURVE_16 -#define DSP2_MISC_REG_DP_GMA_CURVE_16_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_16_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_16_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_16_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_16_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_16_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_16_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_16_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_17 DSP2_MISC_REG_DP_GMA_CURVE_17 -#define DSP2_MISC_REG_DP_GMA_CURVE_17_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_17_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_17_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_17_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_17_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_17_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_17_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_17_POS)) - -/* 0x218 : disp_gma_curve_18 */ -#define DSP2_MISC_DISP_GMA_CURVE_18_OFFSET (0x218) -#define DSP2_MISC_REG_DP_GMA_CURVE_18 DSP2_MISC_REG_DP_GMA_CURVE_18 -#define DSP2_MISC_REG_DP_GMA_CURVE_18_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_18_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_18_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_18_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_18_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_18_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_18_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_18_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_19 DSP2_MISC_REG_DP_GMA_CURVE_19 -#define DSP2_MISC_REG_DP_GMA_CURVE_19_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_19_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_19_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_19_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_19_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_19_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_19_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_19_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_1A DSP2_MISC_REG_DP_GMA_CURVE_1A -#define DSP2_MISC_REG_DP_GMA_CURVE_1A_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_1A_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_1A_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_1A_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_1A_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_1A_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_1A_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_1A_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_1B DSP2_MISC_REG_DP_GMA_CURVE_1B -#define DSP2_MISC_REG_DP_GMA_CURVE_1B_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_1B_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_1B_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_1B_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_1B_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_1B_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_1B_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_1B_POS)) - -/* 0x21C : disp_gma_curve_1c */ -#define DSP2_MISC_DISP_GMA_CURVE_1C_OFFSET (0x21C) -#define DSP2_MISC_REG_DP_GMA_CURVE_1C DSP2_MISC_REG_DP_GMA_CURVE_1C -#define DSP2_MISC_REG_DP_GMA_CURVE_1C_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_1C_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_1C_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_1C_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_1C_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_1C_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_1C_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_1C_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_1D DSP2_MISC_REG_DP_GMA_CURVE_1D -#define DSP2_MISC_REG_DP_GMA_CURVE_1D_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_1D_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_1D_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_1D_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_1D_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_1D_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_1D_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_1D_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_1E DSP2_MISC_REG_DP_GMA_CURVE_1E -#define DSP2_MISC_REG_DP_GMA_CURVE_1E_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_1E_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_1E_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_1E_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_1E_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_1E_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_1E_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_1E_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_1F DSP2_MISC_REG_DP_GMA_CURVE_1F -#define DSP2_MISC_REG_DP_GMA_CURVE_1F_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_1F_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_1F_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_1F_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_1F_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_1F_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_1F_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_1F_POS)) - -/* 0x220 : disp_gma_curve_20 */ -#define DSP2_MISC_DISP_GMA_CURVE_20_OFFSET (0x220) -#define DSP2_MISC_REG_DP_GMA_CURVE_20 DSP2_MISC_REG_DP_GMA_CURVE_20 -#define DSP2_MISC_REG_DP_GMA_CURVE_20_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_20_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_20_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_20_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_20_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_20_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_20_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_20_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_21 DSP2_MISC_REG_DP_GMA_CURVE_21 -#define DSP2_MISC_REG_DP_GMA_CURVE_21_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_21_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_21_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_21_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_21_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_21_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_21_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_21_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_22 DSP2_MISC_REG_DP_GMA_CURVE_22 -#define DSP2_MISC_REG_DP_GMA_CURVE_22_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_22_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_22_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_22_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_22_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_22_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_22_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_22_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_23 DSP2_MISC_REG_DP_GMA_CURVE_23 -#define DSP2_MISC_REG_DP_GMA_CURVE_23_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_23_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_23_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_23_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_23_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_23_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_23_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_23_POS)) - -/* 0x224 : disp_gma_curve_24 */ -#define DSP2_MISC_DISP_GMA_CURVE_24_OFFSET (0x224) -#define DSP2_MISC_REG_DP_GMA_CURVE_24 DSP2_MISC_REG_DP_GMA_CURVE_24 -#define DSP2_MISC_REG_DP_GMA_CURVE_24_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_24_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_24_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_24_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_24_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_24_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_24_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_24_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_25 DSP2_MISC_REG_DP_GMA_CURVE_25 -#define DSP2_MISC_REG_DP_GMA_CURVE_25_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_25_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_25_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_25_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_25_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_25_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_25_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_25_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_26 DSP2_MISC_REG_DP_GMA_CURVE_26 -#define DSP2_MISC_REG_DP_GMA_CURVE_26_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_26_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_26_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_26_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_26_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_26_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_26_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_26_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_27 DSP2_MISC_REG_DP_GMA_CURVE_27 -#define DSP2_MISC_REG_DP_GMA_CURVE_27_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_27_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_27_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_27_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_27_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_27_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_27_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_27_POS)) - -/* 0x228 : disp_gma_curve_28 */ -#define DSP2_MISC_DISP_GMA_CURVE_28_OFFSET (0x228) -#define DSP2_MISC_REG_DP_GMA_CURVE_28 DSP2_MISC_REG_DP_GMA_CURVE_28 -#define DSP2_MISC_REG_DP_GMA_CURVE_28_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_28_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_28_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_28_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_28_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_28_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_28_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_28_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_29 DSP2_MISC_REG_DP_GMA_CURVE_29 -#define DSP2_MISC_REG_DP_GMA_CURVE_29_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_29_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_29_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_29_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_29_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_29_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_29_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_29_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_2A DSP2_MISC_REG_DP_GMA_CURVE_2A -#define DSP2_MISC_REG_DP_GMA_CURVE_2A_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_2A_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_2A_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_2A_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_2A_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_2A_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_2A_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_2A_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_2B DSP2_MISC_REG_DP_GMA_CURVE_2B -#define DSP2_MISC_REG_DP_GMA_CURVE_2B_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_2B_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_2B_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_2B_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_2B_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_2B_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_2B_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_2B_POS)) - -/* 0x22C : disp_gma_curve_2c */ -#define DSP2_MISC_DISP_GMA_CURVE_2C_OFFSET (0x22C) -#define DSP2_MISC_REG_DP_GMA_CURVE_2C DSP2_MISC_REG_DP_GMA_CURVE_2C -#define DSP2_MISC_REG_DP_GMA_CURVE_2C_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_2C_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_2C_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_2C_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_2C_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_2C_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_2C_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_2C_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_2D DSP2_MISC_REG_DP_GMA_CURVE_2D -#define DSP2_MISC_REG_DP_GMA_CURVE_2D_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_2D_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_2D_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_2D_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_2D_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_2D_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_2D_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_2D_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_2E DSP2_MISC_REG_DP_GMA_CURVE_2E -#define DSP2_MISC_REG_DP_GMA_CURVE_2E_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_2E_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_2E_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_2E_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_2E_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_2E_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_2E_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_2E_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_2F DSP2_MISC_REG_DP_GMA_CURVE_2F -#define DSP2_MISC_REG_DP_GMA_CURVE_2F_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_2F_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_2F_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_2F_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_2F_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_2F_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_2F_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_2F_POS)) - -/* 0x230 : disp_gma_curve_30 */ -#define DSP2_MISC_DISP_GMA_CURVE_30_OFFSET (0x230) -#define DSP2_MISC_REG_DP_GMA_CURVE_30 DSP2_MISC_REG_DP_GMA_CURVE_30 -#define DSP2_MISC_REG_DP_GMA_CURVE_30_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_30_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_30_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_30_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_30_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_30_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_30_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_30_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_31 DSP2_MISC_REG_DP_GMA_CURVE_31 -#define DSP2_MISC_REG_DP_GMA_CURVE_31_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_31_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_31_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_31_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_31_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_31_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_31_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_31_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_32 DSP2_MISC_REG_DP_GMA_CURVE_32 -#define DSP2_MISC_REG_DP_GMA_CURVE_32_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_32_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_32_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_32_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_32_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_32_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_32_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_32_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_33 DSP2_MISC_REG_DP_GMA_CURVE_33 -#define DSP2_MISC_REG_DP_GMA_CURVE_33_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_33_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_33_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_33_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_33_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_33_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_33_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_33_POS)) - -/* 0x234 : disp_gma_curve_34 */ -#define DSP2_MISC_DISP_GMA_CURVE_34_OFFSET (0x234) -#define DSP2_MISC_REG_DP_GMA_CURVE_34 DSP2_MISC_REG_DP_GMA_CURVE_34 -#define DSP2_MISC_REG_DP_GMA_CURVE_34_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_34_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_34_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_34_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_34_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_34_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_34_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_34_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_35 DSP2_MISC_REG_DP_GMA_CURVE_35 -#define DSP2_MISC_REG_DP_GMA_CURVE_35_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_35_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_35_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_35_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_35_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_35_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_35_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_35_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_36 DSP2_MISC_REG_DP_GMA_CURVE_36 -#define DSP2_MISC_REG_DP_GMA_CURVE_36_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_36_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_36_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_36_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_36_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_36_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_36_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_36_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_37 DSP2_MISC_REG_DP_GMA_CURVE_37 -#define DSP2_MISC_REG_DP_GMA_CURVE_37_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_37_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_37_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_37_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_37_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_37_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_37_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_37_POS)) - -/* 0x238 : disp_gma_curve_38 */ -#define DSP2_MISC_DISP_GMA_CURVE_38_OFFSET (0x238) -#define DSP2_MISC_REG_DP_GMA_CURVE_38 DSP2_MISC_REG_DP_GMA_CURVE_38 -#define DSP2_MISC_REG_DP_GMA_CURVE_38_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_38_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_38_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_38_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_38_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_38_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_38_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_38_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_39 DSP2_MISC_REG_DP_GMA_CURVE_39 -#define DSP2_MISC_REG_DP_GMA_CURVE_39_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_39_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_39_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_39_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_39_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_39_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_39_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_39_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_3A DSP2_MISC_REG_DP_GMA_CURVE_3A -#define DSP2_MISC_REG_DP_GMA_CURVE_3A_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_3A_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_3A_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_3A_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_3A_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_3A_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_3A_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_3A_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_3B DSP2_MISC_REG_DP_GMA_CURVE_3B -#define DSP2_MISC_REG_DP_GMA_CURVE_3B_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_3B_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_3B_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_3B_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_3B_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_3B_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_3B_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_3B_POS)) - -/* 0x23C : disp_gma_curve_3c */ -#define DSP2_MISC_DISP_GMA_CURVE_3C_OFFSET (0x23C) -#define DSP2_MISC_REG_DP_GMA_CURVE_3C DSP2_MISC_REG_DP_GMA_CURVE_3C -#define DSP2_MISC_REG_DP_GMA_CURVE_3C_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_3C_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_3C_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_3C_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_3C_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_3C_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_3C_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_3C_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_3D DSP2_MISC_REG_DP_GMA_CURVE_3D -#define DSP2_MISC_REG_DP_GMA_CURVE_3D_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_3D_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_3D_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_3D_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_3D_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_3D_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_3D_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_3D_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_3E DSP2_MISC_REG_DP_GMA_CURVE_3E -#define DSP2_MISC_REG_DP_GMA_CURVE_3E_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_3E_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_3E_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_3E_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_3E_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_3E_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_3E_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_3E_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_3F DSP2_MISC_REG_DP_GMA_CURVE_3F -#define DSP2_MISC_REG_DP_GMA_CURVE_3F_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_3F_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_3F_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_3F_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_3F_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_3F_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_3F_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_3F_POS)) - -/* 0x240 : disp_gma_curve_40 */ -#define DSP2_MISC_DISP_GMA_CURVE_40_OFFSET (0x240) -#define DSP2_MISC_REG_DP_GMA_CURVE_40 DSP2_MISC_REG_DP_GMA_CURVE_40 -#define DSP2_MISC_REG_DP_GMA_CURVE_40_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_40_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_40_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_40_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_40_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_40_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_40_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_40_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_41 DSP2_MISC_REG_DP_GMA_CURVE_41 -#define DSP2_MISC_REG_DP_GMA_CURVE_41_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_41_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_41_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_41_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_41_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_41_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_41_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_41_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_42 DSP2_MISC_REG_DP_GMA_CURVE_42 -#define DSP2_MISC_REG_DP_GMA_CURVE_42_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_42_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_42_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_42_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_42_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_42_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_42_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_42_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_43 DSP2_MISC_REG_DP_GMA_CURVE_43 -#define DSP2_MISC_REG_DP_GMA_CURVE_43_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_43_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_43_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_43_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_43_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_43_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_43_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_43_POS)) - -/* 0x244 : disp_gma_curve_44 */ -#define DSP2_MISC_DISP_GMA_CURVE_44_OFFSET (0x244) -#define DSP2_MISC_REG_DP_GMA_CURVE_44 DSP2_MISC_REG_DP_GMA_CURVE_44 -#define DSP2_MISC_REG_DP_GMA_CURVE_44_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_44_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_44_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_44_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_44_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_44_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_44_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_44_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_45 DSP2_MISC_REG_DP_GMA_CURVE_45 -#define DSP2_MISC_REG_DP_GMA_CURVE_45_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_45_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_45_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_45_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_45_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_45_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_45_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_45_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_46 DSP2_MISC_REG_DP_GMA_CURVE_46 -#define DSP2_MISC_REG_DP_GMA_CURVE_46_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_46_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_46_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_46_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_46_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_46_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_46_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_46_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_47 DSP2_MISC_REG_DP_GMA_CURVE_47 -#define DSP2_MISC_REG_DP_GMA_CURVE_47_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_47_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_47_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_47_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_47_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_47_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_47_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_47_POS)) - -/* 0x248 : disp_gma_curve_48 */ -#define DSP2_MISC_DISP_GMA_CURVE_48_OFFSET (0x248) -#define DSP2_MISC_REG_DP_GMA_CURVE_48 DSP2_MISC_REG_DP_GMA_CURVE_48 -#define DSP2_MISC_REG_DP_GMA_CURVE_48_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_48_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_48_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_48_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_48_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_48_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_48_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_48_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_49 DSP2_MISC_REG_DP_GMA_CURVE_49 -#define DSP2_MISC_REG_DP_GMA_CURVE_49_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_49_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_49_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_49_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_49_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_49_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_49_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_49_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_4A DSP2_MISC_REG_DP_GMA_CURVE_4A -#define DSP2_MISC_REG_DP_GMA_CURVE_4A_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_4A_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_4A_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_4A_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_4A_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_4A_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_4A_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_4A_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_4B DSP2_MISC_REG_DP_GMA_CURVE_4B -#define DSP2_MISC_REG_DP_GMA_CURVE_4B_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_4B_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_4B_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_4B_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_4B_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_4B_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_4B_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_4B_POS)) - -/* 0x24C : disp_gma_curve_4c */ -#define DSP2_MISC_DISP_GMA_CURVE_4C_OFFSET (0x24C) -#define DSP2_MISC_REG_DP_GMA_CURVE_4C DSP2_MISC_REG_DP_GMA_CURVE_4C -#define DSP2_MISC_REG_DP_GMA_CURVE_4C_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_4C_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_4C_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_4C_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_4C_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_4C_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_4C_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_4C_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_4D DSP2_MISC_REG_DP_GMA_CURVE_4D -#define DSP2_MISC_REG_DP_GMA_CURVE_4D_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_4D_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_4D_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_4D_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_4D_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_4D_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_4D_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_4D_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_4E DSP2_MISC_REG_DP_GMA_CURVE_4E -#define DSP2_MISC_REG_DP_GMA_CURVE_4E_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_4E_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_4E_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_4E_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_4E_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_4E_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_4E_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_4E_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_4F DSP2_MISC_REG_DP_GMA_CURVE_4F -#define DSP2_MISC_REG_DP_GMA_CURVE_4F_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_4F_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_4F_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_4F_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_4F_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_4F_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_4F_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_4F_POS)) - -/* 0x250 : disp_gma_curve_50 */ -#define DSP2_MISC_DISP_GMA_CURVE_50_OFFSET (0x250) -#define DSP2_MISC_REG_DP_GMA_CURVE_50 DSP2_MISC_REG_DP_GMA_CURVE_50 -#define DSP2_MISC_REG_DP_GMA_CURVE_50_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_50_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_50_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_50_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_50_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_50_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_50_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_50_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_51 DSP2_MISC_REG_DP_GMA_CURVE_51 -#define DSP2_MISC_REG_DP_GMA_CURVE_51_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_51_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_51_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_51_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_51_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_51_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_51_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_51_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_52 DSP2_MISC_REG_DP_GMA_CURVE_52 -#define DSP2_MISC_REG_DP_GMA_CURVE_52_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_52_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_52_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_52_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_52_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_52_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_52_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_52_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_53 DSP2_MISC_REG_DP_GMA_CURVE_53 -#define DSP2_MISC_REG_DP_GMA_CURVE_53_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_53_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_53_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_53_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_53_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_53_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_53_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_53_POS)) - -/* 0x254 : disp_gma_curve_54 */ -#define DSP2_MISC_DISP_GMA_CURVE_54_OFFSET (0x254) -#define DSP2_MISC_REG_DP_GMA_CURVE_54 DSP2_MISC_REG_DP_GMA_CURVE_54 -#define DSP2_MISC_REG_DP_GMA_CURVE_54_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_54_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_54_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_54_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_54_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_54_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_54_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_54_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_55 DSP2_MISC_REG_DP_GMA_CURVE_55 -#define DSP2_MISC_REG_DP_GMA_CURVE_55_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_55_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_55_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_55_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_55_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_55_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_55_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_55_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_56 DSP2_MISC_REG_DP_GMA_CURVE_56 -#define DSP2_MISC_REG_DP_GMA_CURVE_56_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_56_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_56_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_56_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_56_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_56_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_56_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_56_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_57 DSP2_MISC_REG_DP_GMA_CURVE_57 -#define DSP2_MISC_REG_DP_GMA_CURVE_57_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_57_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_57_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_57_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_57_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_57_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_57_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_57_POS)) - -/* 0x258 : disp_gma_curve_58 */ -#define DSP2_MISC_DISP_GMA_CURVE_58_OFFSET (0x258) -#define DSP2_MISC_REG_DP_GMA_CURVE_58 DSP2_MISC_REG_DP_GMA_CURVE_58 -#define DSP2_MISC_REG_DP_GMA_CURVE_58_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_58_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_58_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_58_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_58_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_58_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_58_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_58_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_59 DSP2_MISC_REG_DP_GMA_CURVE_59 -#define DSP2_MISC_REG_DP_GMA_CURVE_59_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_59_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_59_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_59_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_59_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_59_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_59_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_59_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_5A DSP2_MISC_REG_DP_GMA_CURVE_5A -#define DSP2_MISC_REG_DP_GMA_CURVE_5A_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_5A_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_5A_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_5A_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_5A_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_5A_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_5A_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_5A_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_5B DSP2_MISC_REG_DP_GMA_CURVE_5B -#define DSP2_MISC_REG_DP_GMA_CURVE_5B_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_5B_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_5B_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_5B_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_5B_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_5B_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_5B_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_5B_POS)) - -/* 0x25C : disp_gma_curve_5c */ -#define DSP2_MISC_DISP_GMA_CURVE_5C_OFFSET (0x25C) -#define DSP2_MISC_REG_DP_GMA_CURVE_5C DSP2_MISC_REG_DP_GMA_CURVE_5C -#define DSP2_MISC_REG_DP_GMA_CURVE_5C_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_5C_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_5C_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_5C_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_5C_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_5C_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_5C_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_5C_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_5D DSP2_MISC_REG_DP_GMA_CURVE_5D -#define DSP2_MISC_REG_DP_GMA_CURVE_5D_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_5D_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_5D_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_5D_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_5D_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_5D_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_5D_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_5D_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_5E DSP2_MISC_REG_DP_GMA_CURVE_5E -#define DSP2_MISC_REG_DP_GMA_CURVE_5E_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_5E_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_5E_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_5E_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_5E_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_5E_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_5E_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_5E_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_5F DSP2_MISC_REG_DP_GMA_CURVE_5F -#define DSP2_MISC_REG_DP_GMA_CURVE_5F_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_5F_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_5F_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_5F_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_5F_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_5F_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_5F_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_5F_POS)) - -/* 0x260 : disp_gma_curve_60 */ -#define DSP2_MISC_DISP_GMA_CURVE_60_OFFSET (0x260) -#define DSP2_MISC_REG_DP_GMA_CURVE_60 DSP2_MISC_REG_DP_GMA_CURVE_60 -#define DSP2_MISC_REG_DP_GMA_CURVE_60_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_60_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_60_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_60_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_60_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_60_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_60_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_60_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_61 DSP2_MISC_REG_DP_GMA_CURVE_61 -#define DSP2_MISC_REG_DP_GMA_CURVE_61_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_61_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_61_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_61_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_61_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_61_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_61_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_61_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_62 DSP2_MISC_REG_DP_GMA_CURVE_62 -#define DSP2_MISC_REG_DP_GMA_CURVE_62_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_62_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_62_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_62_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_62_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_62_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_62_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_62_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_63 DSP2_MISC_REG_DP_GMA_CURVE_63 -#define DSP2_MISC_REG_DP_GMA_CURVE_63_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_63_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_63_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_63_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_63_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_63_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_63_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_63_POS)) - -/* 0x264 : disp_gma_curve_64 */ -#define DSP2_MISC_DISP_GMA_CURVE_64_OFFSET (0x264) -#define DSP2_MISC_REG_DP_GMA_CURVE_64 DSP2_MISC_REG_DP_GMA_CURVE_64 -#define DSP2_MISC_REG_DP_GMA_CURVE_64_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_64_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_64_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_64_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_64_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_64_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_64_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_64_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_65 DSP2_MISC_REG_DP_GMA_CURVE_65 -#define DSP2_MISC_REG_DP_GMA_CURVE_65_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_65_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_65_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_65_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_65_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_65_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_65_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_65_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_66 DSP2_MISC_REG_DP_GMA_CURVE_66 -#define DSP2_MISC_REG_DP_GMA_CURVE_66_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_66_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_66_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_66_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_66_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_66_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_66_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_66_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_67 DSP2_MISC_REG_DP_GMA_CURVE_67 -#define DSP2_MISC_REG_DP_GMA_CURVE_67_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_67_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_67_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_67_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_67_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_67_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_67_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_67_POS)) - -/* 0x268 : disp_gma_curve_68 */ -#define DSP2_MISC_DISP_GMA_CURVE_68_OFFSET (0x268) -#define DSP2_MISC_REG_DP_GMA_CURVE_68 DSP2_MISC_REG_DP_GMA_CURVE_68 -#define DSP2_MISC_REG_DP_GMA_CURVE_68_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_68_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_68_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_68_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_68_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_68_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_68_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_68_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_69 DSP2_MISC_REG_DP_GMA_CURVE_69 -#define DSP2_MISC_REG_DP_GMA_CURVE_69_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_69_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_69_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_69_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_69_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_69_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_69_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_69_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_6A DSP2_MISC_REG_DP_GMA_CURVE_6A -#define DSP2_MISC_REG_DP_GMA_CURVE_6A_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_6A_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_6A_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_6A_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_6A_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_6A_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_6A_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_6A_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_6B DSP2_MISC_REG_DP_GMA_CURVE_6B -#define DSP2_MISC_REG_DP_GMA_CURVE_6B_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_6B_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_6B_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_6B_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_6B_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_6B_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_6B_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_6B_POS)) - -/* 0x26C : disp_gma_curve_6c */ -#define DSP2_MISC_DISP_GMA_CURVE_6C_OFFSET (0x26C) -#define DSP2_MISC_REG_DP_GMA_CURVE_6C DSP2_MISC_REG_DP_GMA_CURVE_6C -#define DSP2_MISC_REG_DP_GMA_CURVE_6C_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_6C_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_6C_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_6C_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_6C_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_6C_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_6C_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_6C_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_6D DSP2_MISC_REG_DP_GMA_CURVE_6D -#define DSP2_MISC_REG_DP_GMA_CURVE_6D_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_6D_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_6D_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_6D_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_6D_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_6D_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_6D_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_6D_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_6E DSP2_MISC_REG_DP_GMA_CURVE_6E -#define DSP2_MISC_REG_DP_GMA_CURVE_6E_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_6E_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_6E_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_6E_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_6E_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_6E_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_6E_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_6E_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_6F DSP2_MISC_REG_DP_GMA_CURVE_6F -#define DSP2_MISC_REG_DP_GMA_CURVE_6F_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_6F_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_6F_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_6F_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_6F_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_6F_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_6F_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_6F_POS)) - -/* 0x270 : disp_gma_curve_70 */ -#define DSP2_MISC_DISP_GMA_CURVE_70_OFFSET (0x270) -#define DSP2_MISC_REG_DP_GMA_CURVE_70 DSP2_MISC_REG_DP_GMA_CURVE_70 -#define DSP2_MISC_REG_DP_GMA_CURVE_70_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_70_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_70_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_70_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_70_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_70_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_70_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_70_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_71 DSP2_MISC_REG_DP_GMA_CURVE_71 -#define DSP2_MISC_REG_DP_GMA_CURVE_71_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_71_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_71_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_71_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_71_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_71_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_71_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_71_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_72 DSP2_MISC_REG_DP_GMA_CURVE_72 -#define DSP2_MISC_REG_DP_GMA_CURVE_72_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_72_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_72_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_72_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_72_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_72_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_72_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_72_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_73 DSP2_MISC_REG_DP_GMA_CURVE_73 -#define DSP2_MISC_REG_DP_GMA_CURVE_73_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_73_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_73_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_73_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_73_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_73_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_73_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_73_POS)) - -/* 0x274 : disp_gma_curve_74 */ -#define DSP2_MISC_DISP_GMA_CURVE_74_OFFSET (0x274) -#define DSP2_MISC_REG_DP_GMA_CURVE_74 DSP2_MISC_REG_DP_GMA_CURVE_74 -#define DSP2_MISC_REG_DP_GMA_CURVE_74_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_74_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_74_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_74_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_74_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_74_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_74_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_74_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_75 DSP2_MISC_REG_DP_GMA_CURVE_75 -#define DSP2_MISC_REG_DP_GMA_CURVE_75_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_75_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_75_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_75_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_75_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_75_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_75_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_75_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_76 DSP2_MISC_REG_DP_GMA_CURVE_76 -#define DSP2_MISC_REG_DP_GMA_CURVE_76_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_76_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_76_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_76_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_76_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_76_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_76_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_76_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_77 DSP2_MISC_REG_DP_GMA_CURVE_77 -#define DSP2_MISC_REG_DP_GMA_CURVE_77_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_77_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_77_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_77_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_77_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_77_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_77_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_77_POS)) - -/* 0x278 : disp_gma_curve_78 */ -#define DSP2_MISC_DISP_GMA_CURVE_78_OFFSET (0x278) -#define DSP2_MISC_REG_DP_GMA_CURVE_78 DSP2_MISC_REG_DP_GMA_CURVE_78 -#define DSP2_MISC_REG_DP_GMA_CURVE_78_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_78_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_78_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_78_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_78_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_78_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_78_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_78_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_79 DSP2_MISC_REG_DP_GMA_CURVE_79 -#define DSP2_MISC_REG_DP_GMA_CURVE_79_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_79_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_79_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_79_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_79_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_79_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_79_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_79_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_7A DSP2_MISC_REG_DP_GMA_CURVE_7A -#define DSP2_MISC_REG_DP_GMA_CURVE_7A_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_7A_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_7A_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_7A_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_7A_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_7A_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_7A_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_7A_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_7B DSP2_MISC_REG_DP_GMA_CURVE_7B -#define DSP2_MISC_REG_DP_GMA_CURVE_7B_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_7B_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_7B_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_7B_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_7B_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_7B_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_7B_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_7B_POS)) - -/* 0x27C : disp_gma_curve_7c */ -#define DSP2_MISC_DISP_GMA_CURVE_7C_OFFSET (0x27C) -#define DSP2_MISC_REG_DP_GMA_CURVE_7C DSP2_MISC_REG_DP_GMA_CURVE_7C -#define DSP2_MISC_REG_DP_GMA_CURVE_7C_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_7C_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_7C_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_7C_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_7C_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_7C_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_7C_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_7C_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_7D DSP2_MISC_REG_DP_GMA_CURVE_7D -#define DSP2_MISC_REG_DP_GMA_CURVE_7D_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_7D_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_7D_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_7D_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_7D_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_7D_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_7D_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_7D_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_7E DSP2_MISC_REG_DP_GMA_CURVE_7E -#define DSP2_MISC_REG_DP_GMA_CURVE_7E_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_7E_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_7E_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_7E_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_7E_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_7E_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_7E_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_7E_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_7F DSP2_MISC_REG_DP_GMA_CURVE_7F -#define DSP2_MISC_REG_DP_GMA_CURVE_7F_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_7F_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_7F_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_7F_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_7F_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_7F_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_7F_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_7F_POS)) - -/* 0x280 : disp_gma_curve_80 */ -#define DSP2_MISC_DISP_GMA_CURVE_80_OFFSET (0x280) -#define DSP2_MISC_REG_DP_GMA_CURVE_80 DSP2_MISC_REG_DP_GMA_CURVE_80 -#define DSP2_MISC_REG_DP_GMA_CURVE_80_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_80_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_80_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_80_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_80_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_80_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_80_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_80_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_81 DSP2_MISC_REG_DP_GMA_CURVE_81 -#define DSP2_MISC_REG_DP_GMA_CURVE_81_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_81_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_81_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_81_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_81_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_81_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_81_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_81_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_82 DSP2_MISC_REG_DP_GMA_CURVE_82 -#define DSP2_MISC_REG_DP_GMA_CURVE_82_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_82_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_82_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_82_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_82_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_82_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_82_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_82_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_83 DSP2_MISC_REG_DP_GMA_CURVE_83 -#define DSP2_MISC_REG_DP_GMA_CURVE_83_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_83_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_83_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_83_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_83_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_83_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_83_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_83_POS)) - -/* 0x284 : disp_gma_curve_84 */ -#define DSP2_MISC_DISP_GMA_CURVE_84_OFFSET (0x284) -#define DSP2_MISC_REG_DP_GMA_CURVE_84 DSP2_MISC_REG_DP_GMA_CURVE_84 -#define DSP2_MISC_REG_DP_GMA_CURVE_84_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_84_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_84_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_84_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_84_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_84_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_84_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_84_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_85 DSP2_MISC_REG_DP_GMA_CURVE_85 -#define DSP2_MISC_REG_DP_GMA_CURVE_85_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_85_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_85_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_85_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_85_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_85_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_85_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_85_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_86 DSP2_MISC_REG_DP_GMA_CURVE_86 -#define DSP2_MISC_REG_DP_GMA_CURVE_86_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_86_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_86_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_86_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_86_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_86_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_86_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_86_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_87 DSP2_MISC_REG_DP_GMA_CURVE_87 -#define DSP2_MISC_REG_DP_GMA_CURVE_87_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_87_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_87_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_87_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_87_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_87_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_87_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_87_POS)) - -/* 0x288 : disp_gma_curve_88 */ -#define DSP2_MISC_DISP_GMA_CURVE_88_OFFSET (0x288) -#define DSP2_MISC_REG_DP_GMA_CURVE_88 DSP2_MISC_REG_DP_GMA_CURVE_88 -#define DSP2_MISC_REG_DP_GMA_CURVE_88_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_88_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_88_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_88_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_88_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_88_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_88_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_88_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_89 DSP2_MISC_REG_DP_GMA_CURVE_89 -#define DSP2_MISC_REG_DP_GMA_CURVE_89_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_89_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_89_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_89_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_89_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_89_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_89_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_89_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_8A DSP2_MISC_REG_DP_GMA_CURVE_8A -#define DSP2_MISC_REG_DP_GMA_CURVE_8A_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_8A_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_8A_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_8A_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_8A_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_8A_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_8A_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_8A_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_8B DSP2_MISC_REG_DP_GMA_CURVE_8B -#define DSP2_MISC_REG_DP_GMA_CURVE_8B_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_8B_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_8B_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_8B_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_8B_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_8B_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_8B_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_8B_POS)) - -/* 0x28C : disp_gma_curve_8c */ -#define DSP2_MISC_DISP_GMA_CURVE_8C_OFFSET (0x28C) -#define DSP2_MISC_REG_DP_GMA_CURVE_8C DSP2_MISC_REG_DP_GMA_CURVE_8C -#define DSP2_MISC_REG_DP_GMA_CURVE_8C_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_8C_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_8C_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_8C_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_8C_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_8C_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_8C_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_8C_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_8D DSP2_MISC_REG_DP_GMA_CURVE_8D -#define DSP2_MISC_REG_DP_GMA_CURVE_8D_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_8D_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_8D_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_8D_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_8D_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_8D_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_8D_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_8D_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_8E DSP2_MISC_REG_DP_GMA_CURVE_8E -#define DSP2_MISC_REG_DP_GMA_CURVE_8E_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_8E_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_8E_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_8E_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_8E_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_8E_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_8E_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_8E_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_8F DSP2_MISC_REG_DP_GMA_CURVE_8F -#define DSP2_MISC_REG_DP_GMA_CURVE_8F_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_8F_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_8F_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_8F_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_8F_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_8F_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_8F_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_8F_POS)) - -/* 0x290 : disp_gma_curve_90 */ -#define DSP2_MISC_DISP_GMA_CURVE_90_OFFSET (0x290) -#define DSP2_MISC_REG_DP_GMA_CURVE_90 DSP2_MISC_REG_DP_GMA_CURVE_90 -#define DSP2_MISC_REG_DP_GMA_CURVE_90_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_90_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_90_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_90_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_90_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_90_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_90_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_90_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_91 DSP2_MISC_REG_DP_GMA_CURVE_91 -#define DSP2_MISC_REG_DP_GMA_CURVE_91_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_91_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_91_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_91_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_91_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_91_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_91_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_91_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_92 DSP2_MISC_REG_DP_GMA_CURVE_92 -#define DSP2_MISC_REG_DP_GMA_CURVE_92_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_92_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_92_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_92_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_92_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_92_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_92_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_92_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_93 DSP2_MISC_REG_DP_GMA_CURVE_93 -#define DSP2_MISC_REG_DP_GMA_CURVE_93_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_93_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_93_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_93_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_93_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_93_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_93_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_93_POS)) - -/* 0x294 : disp_gma_curve_94 */ -#define DSP2_MISC_DISP_GMA_CURVE_94_OFFSET (0x294) -#define DSP2_MISC_REG_DP_GMA_CURVE_94 DSP2_MISC_REG_DP_GMA_CURVE_94 -#define DSP2_MISC_REG_DP_GMA_CURVE_94_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_94_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_94_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_94_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_94_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_94_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_94_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_94_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_95 DSP2_MISC_REG_DP_GMA_CURVE_95 -#define DSP2_MISC_REG_DP_GMA_CURVE_95_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_95_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_95_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_95_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_95_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_95_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_95_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_95_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_96 DSP2_MISC_REG_DP_GMA_CURVE_96 -#define DSP2_MISC_REG_DP_GMA_CURVE_96_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_96_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_96_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_96_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_96_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_96_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_96_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_96_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_97 DSP2_MISC_REG_DP_GMA_CURVE_97 -#define DSP2_MISC_REG_DP_GMA_CURVE_97_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_97_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_97_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_97_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_97_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_97_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_97_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_97_POS)) - -/* 0x298 : disp_gma_curve_98 */ -#define DSP2_MISC_DISP_GMA_CURVE_98_OFFSET (0x298) -#define DSP2_MISC_REG_DP_GMA_CURVE_98 DSP2_MISC_REG_DP_GMA_CURVE_98 -#define DSP2_MISC_REG_DP_GMA_CURVE_98_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_98_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_98_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_98_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_98_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_98_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_98_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_98_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_99 DSP2_MISC_REG_DP_GMA_CURVE_99 -#define DSP2_MISC_REG_DP_GMA_CURVE_99_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_99_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_99_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_99_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_99_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_99_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_99_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_99_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_9A DSP2_MISC_REG_DP_GMA_CURVE_9A -#define DSP2_MISC_REG_DP_GMA_CURVE_9A_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_9A_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_9A_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_9A_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_9A_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_9A_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_9A_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_9A_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_9B DSP2_MISC_REG_DP_GMA_CURVE_9B -#define DSP2_MISC_REG_DP_GMA_CURVE_9B_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_9B_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_9B_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_9B_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_9B_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_9B_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_9B_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_9B_POS)) - -/* 0x29C : disp_gma_curve_9c */ -#define DSP2_MISC_DISP_GMA_CURVE_9C_OFFSET (0x29C) -#define DSP2_MISC_REG_DP_GMA_CURVE_9C DSP2_MISC_REG_DP_GMA_CURVE_9C -#define DSP2_MISC_REG_DP_GMA_CURVE_9C_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_9C_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_9C_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_9C_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_9C_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_9C_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_9C_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_9C_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_9D DSP2_MISC_REG_DP_GMA_CURVE_9D -#define DSP2_MISC_REG_DP_GMA_CURVE_9D_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_9D_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_9D_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_9D_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_9D_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_9D_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_9D_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_9D_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_9E DSP2_MISC_REG_DP_GMA_CURVE_9E -#define DSP2_MISC_REG_DP_GMA_CURVE_9E_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_9E_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_9E_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_9E_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_9E_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_9E_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_9E_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_9E_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_9F DSP2_MISC_REG_DP_GMA_CURVE_9F -#define DSP2_MISC_REG_DP_GMA_CURVE_9F_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_9F_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_9F_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_9F_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_9F_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_9F_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_9F_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_9F_POS)) - -/* 0x2A0 : disp_gma_curve_a0 */ -#define DSP2_MISC_DISP_GMA_CURVE_A0_OFFSET (0x2A0) -#define DSP2_MISC_REG_DP_GMA_CURVE_A0 DSP2_MISC_REG_DP_GMA_CURVE_A0 -#define DSP2_MISC_REG_DP_GMA_CURVE_A0_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_A0_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_A0_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_A0_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_A0_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_A0_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_A0_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_A0_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_A1 DSP2_MISC_REG_DP_GMA_CURVE_A1 -#define DSP2_MISC_REG_DP_GMA_CURVE_A1_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_A1_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_A1_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_A1_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_A1_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_A1_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_A1_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_A1_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_A2 DSP2_MISC_REG_DP_GMA_CURVE_A2 -#define DSP2_MISC_REG_DP_GMA_CURVE_A2_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_A2_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_A2_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_A2_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_A2_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_A2_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_A2_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_A2_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_A3 DSP2_MISC_REG_DP_GMA_CURVE_A3 -#define DSP2_MISC_REG_DP_GMA_CURVE_A3_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_A3_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_A3_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_A3_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_A3_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_A3_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_A3_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_A3_POS)) - -/* 0x2A4 : disp_gma_curve_a4 */ -#define DSP2_MISC_DISP_GMA_CURVE_A4_OFFSET (0x2A4) -#define DSP2_MISC_REG_DP_GMA_CURVE_A4 DSP2_MISC_REG_DP_GMA_CURVE_A4 -#define DSP2_MISC_REG_DP_GMA_CURVE_A4_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_A4_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_A4_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_A4_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_A4_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_A4_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_A4_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_A4_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_A5 DSP2_MISC_REG_DP_GMA_CURVE_A5 -#define DSP2_MISC_REG_DP_GMA_CURVE_A5_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_A5_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_A5_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_A5_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_A5_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_A5_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_A5_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_A5_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_A6 DSP2_MISC_REG_DP_GMA_CURVE_A6 -#define DSP2_MISC_REG_DP_GMA_CURVE_A6_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_A6_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_A6_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_A6_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_A6_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_A6_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_A6_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_A6_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_A7 DSP2_MISC_REG_DP_GMA_CURVE_A7 -#define DSP2_MISC_REG_DP_GMA_CURVE_A7_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_A7_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_A7_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_A7_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_A7_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_A7_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_A7_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_A7_POS)) - -/* 0x2A8 : disp_gma_curve_a8 */ -#define DSP2_MISC_DISP_GMA_CURVE_A8_OFFSET (0x2A8) -#define DSP2_MISC_REG_DP_GMA_CURVE_A8 DSP2_MISC_REG_DP_GMA_CURVE_A8 -#define DSP2_MISC_REG_DP_GMA_CURVE_A8_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_A8_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_A8_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_A8_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_A8_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_A8_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_A8_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_A8_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_A9 DSP2_MISC_REG_DP_GMA_CURVE_A9 -#define DSP2_MISC_REG_DP_GMA_CURVE_A9_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_A9_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_A9_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_A9_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_A9_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_A9_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_A9_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_A9_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_AA DSP2_MISC_REG_DP_GMA_CURVE_AA -#define DSP2_MISC_REG_DP_GMA_CURVE_AA_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_AA_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_AA_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_AA_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_AA_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_AA_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_AA_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_AA_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_AB DSP2_MISC_REG_DP_GMA_CURVE_AB -#define DSP2_MISC_REG_DP_GMA_CURVE_AB_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_AB_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_AB_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_AB_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_AB_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_AB_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_AB_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_AB_POS)) - -/* 0x2AC : disp_gma_curve_ac */ -#define DSP2_MISC_DISP_GMA_CURVE_AC_OFFSET (0x2AC) -#define DSP2_MISC_REG_DP_GMA_CURVE_AC DSP2_MISC_REG_DP_GMA_CURVE_AC -#define DSP2_MISC_REG_DP_GMA_CURVE_AC_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_AC_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_AC_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_AC_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_AC_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_AC_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_AC_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_AC_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_AD DSP2_MISC_REG_DP_GMA_CURVE_AD -#define DSP2_MISC_REG_DP_GMA_CURVE_AD_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_AD_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_AD_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_AD_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_AD_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_AD_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_AD_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_AD_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_AE DSP2_MISC_REG_DP_GMA_CURVE_AE -#define DSP2_MISC_REG_DP_GMA_CURVE_AE_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_AE_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_AE_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_AE_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_AE_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_AE_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_AE_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_AE_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_AF DSP2_MISC_REG_DP_GMA_CURVE_AF -#define DSP2_MISC_REG_DP_GMA_CURVE_AF_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_AF_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_AF_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_AF_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_AF_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_AF_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_AF_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_AF_POS)) - -/* 0x2B0 : disp_gma_curve_b0 */ -#define DSP2_MISC_DISP_GMA_CURVE_B0_OFFSET (0x2B0) -#define DSP2_MISC_REG_DP_GMA_CURVE_B0 DSP2_MISC_REG_DP_GMA_CURVE_B0 -#define DSP2_MISC_REG_DP_GMA_CURVE_B0_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_B0_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_B0_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_B0_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_B0_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_B0_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_B0_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_B0_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_B1 DSP2_MISC_REG_DP_GMA_CURVE_B1 -#define DSP2_MISC_REG_DP_GMA_CURVE_B1_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_B1_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_B1_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_B1_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_B1_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_B1_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_B1_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_B1_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_B2 DSP2_MISC_REG_DP_GMA_CURVE_B2 -#define DSP2_MISC_REG_DP_GMA_CURVE_B2_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_B2_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_B2_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_B2_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_B2_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_B2_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_B2_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_B2_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_B3 DSP2_MISC_REG_DP_GMA_CURVE_B3 -#define DSP2_MISC_REG_DP_GMA_CURVE_B3_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_B3_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_B3_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_B3_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_B3_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_B3_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_B3_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_B3_POS)) - -/* 0x2B4 : disp_gma_curve_b4 */ -#define DSP2_MISC_DISP_GMA_CURVE_B4_OFFSET (0x2B4) -#define DSP2_MISC_REG_DP_GMA_CURVE_B4 DSP2_MISC_REG_DP_GMA_CURVE_B4 -#define DSP2_MISC_REG_DP_GMA_CURVE_B4_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_B4_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_B4_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_B4_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_B4_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_B4_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_B4_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_B4_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_B5 DSP2_MISC_REG_DP_GMA_CURVE_B5 -#define DSP2_MISC_REG_DP_GMA_CURVE_B5_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_B5_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_B5_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_B5_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_B5_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_B5_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_B5_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_B5_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_B6 DSP2_MISC_REG_DP_GMA_CURVE_B6 -#define DSP2_MISC_REG_DP_GMA_CURVE_B6_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_B6_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_B6_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_B6_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_B6_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_B6_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_B6_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_B6_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_B7 DSP2_MISC_REG_DP_GMA_CURVE_B7 -#define DSP2_MISC_REG_DP_GMA_CURVE_B7_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_B7_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_B7_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_B7_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_B7_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_B7_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_B7_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_B7_POS)) - -/* 0x2B8 : disp_gma_curve_b8 */ -#define DSP2_MISC_DISP_GMA_CURVE_B8_OFFSET (0x2B8) -#define DSP2_MISC_REG_DP_GMA_CURVE_B8 DSP2_MISC_REG_DP_GMA_CURVE_B8 -#define DSP2_MISC_REG_DP_GMA_CURVE_B8_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_B8_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_B8_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_B8_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_B8_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_B8_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_B8_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_B8_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_B9 DSP2_MISC_REG_DP_GMA_CURVE_B9 -#define DSP2_MISC_REG_DP_GMA_CURVE_B9_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_B9_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_B9_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_B9_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_B9_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_B9_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_B9_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_B9_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_BA DSP2_MISC_REG_DP_GMA_CURVE_BA -#define DSP2_MISC_REG_DP_GMA_CURVE_BA_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_BA_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_BA_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_BA_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_BA_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_BA_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_BA_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_BA_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_BB DSP2_MISC_REG_DP_GMA_CURVE_BB -#define DSP2_MISC_REG_DP_GMA_CURVE_BB_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_BB_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_BB_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_BB_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_BB_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_BB_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_BB_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_BB_POS)) - -/* 0x2BC : disp_gma_curve_bc */ -#define DSP2_MISC_DISP_GMA_CURVE_BC_OFFSET (0x2BC) -#define DSP2_MISC_REG_DP_GMA_CURVE_BC DSP2_MISC_REG_DP_GMA_CURVE_BC -#define DSP2_MISC_REG_DP_GMA_CURVE_BC_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_BC_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_BC_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_BC_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_BC_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_BC_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_BC_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_BC_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_BD DSP2_MISC_REG_DP_GMA_CURVE_BD -#define DSP2_MISC_REG_DP_GMA_CURVE_BD_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_BD_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_BD_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_BD_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_BD_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_BD_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_BD_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_BD_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_BE DSP2_MISC_REG_DP_GMA_CURVE_BE -#define DSP2_MISC_REG_DP_GMA_CURVE_BE_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_BE_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_BE_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_BE_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_BE_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_BE_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_BE_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_BE_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_BF DSP2_MISC_REG_DP_GMA_CURVE_BF -#define DSP2_MISC_REG_DP_GMA_CURVE_BF_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_BF_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_BF_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_BF_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_BF_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_BF_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_BF_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_BF_POS)) - -/* 0x2C0 : disp_gma_curve_c0 */ -#define DSP2_MISC_DISP_GMA_CURVE_C0_OFFSET (0x2C0) -#define DSP2_MISC_REG_DP_GMA_CURVE_C0 DSP2_MISC_REG_DP_GMA_CURVE_C0 -#define DSP2_MISC_REG_DP_GMA_CURVE_C0_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_C0_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_C0_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_C0_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_C0_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_C0_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_C0_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_C0_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_C1 DSP2_MISC_REG_DP_GMA_CURVE_C1 -#define DSP2_MISC_REG_DP_GMA_CURVE_C1_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_C1_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_C1_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_C1_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_C1_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_C1_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_C1_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_C1_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_C2 DSP2_MISC_REG_DP_GMA_CURVE_C2 -#define DSP2_MISC_REG_DP_GMA_CURVE_C2_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_C2_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_C2_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_C2_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_C2_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_C2_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_C2_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_C2_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_C3 DSP2_MISC_REG_DP_GMA_CURVE_C3 -#define DSP2_MISC_REG_DP_GMA_CURVE_C3_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_C3_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_C3_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_C3_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_C3_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_C3_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_C3_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_C3_POS)) - -/* 0x2C4 : disp_gma_curve_c4 */ -#define DSP2_MISC_DISP_GMA_CURVE_C4_OFFSET (0x2C4) -#define DSP2_MISC_REG_DP_GMA_CURVE_C4 DSP2_MISC_REG_DP_GMA_CURVE_C4 -#define DSP2_MISC_REG_DP_GMA_CURVE_C4_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_C4_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_C4_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_C4_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_C4_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_C4_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_C4_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_C4_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_C5 DSP2_MISC_REG_DP_GMA_CURVE_C5 -#define DSP2_MISC_REG_DP_GMA_CURVE_C5_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_C5_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_C5_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_C5_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_C5_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_C5_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_C5_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_C5_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_C6 DSP2_MISC_REG_DP_GMA_CURVE_C6 -#define DSP2_MISC_REG_DP_GMA_CURVE_C6_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_C6_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_C6_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_C6_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_C6_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_C6_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_C6_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_C6_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_C7 DSP2_MISC_REG_DP_GMA_CURVE_C7 -#define DSP2_MISC_REG_DP_GMA_CURVE_C7_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_C7_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_C7_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_C7_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_C7_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_C7_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_C7_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_C7_POS)) - -/* 0x2C8 : disp_gma_curve_c8 */ -#define DSP2_MISC_DISP_GMA_CURVE_C8_OFFSET (0x2C8) -#define DSP2_MISC_REG_DP_GMA_CURVE_C8 DSP2_MISC_REG_DP_GMA_CURVE_C8 -#define DSP2_MISC_REG_DP_GMA_CURVE_C8_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_C8_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_C8_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_C8_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_C8_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_C8_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_C8_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_C8_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_C9 DSP2_MISC_REG_DP_GMA_CURVE_C9 -#define DSP2_MISC_REG_DP_GMA_CURVE_C9_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_C9_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_C9_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_C9_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_C9_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_C9_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_C9_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_C9_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_CA DSP2_MISC_REG_DP_GMA_CURVE_CA -#define DSP2_MISC_REG_DP_GMA_CURVE_CA_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_CA_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_CA_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_CA_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_CA_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_CA_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_CA_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_CA_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_CB DSP2_MISC_REG_DP_GMA_CURVE_CB -#define DSP2_MISC_REG_DP_GMA_CURVE_CB_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_CB_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_CB_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_CB_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_CB_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_CB_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_CB_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_CB_POS)) - -/* 0x2CC : disp_gma_curve_cc */ -#define DSP2_MISC_DISP_GMA_CURVE_CC_OFFSET (0x2CC) -#define DSP2_MISC_REG_DP_GMA_CURVE_CC DSP2_MISC_REG_DP_GMA_CURVE_CC -#define DSP2_MISC_REG_DP_GMA_CURVE_CC_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_CC_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_CC_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_CC_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_CC_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_CC_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_CC_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_CC_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_CD DSP2_MISC_REG_DP_GMA_CURVE_CD -#define DSP2_MISC_REG_DP_GMA_CURVE_CD_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_CD_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_CD_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_CD_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_CD_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_CD_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_CD_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_CD_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_CE DSP2_MISC_REG_DP_GMA_CURVE_CE -#define DSP2_MISC_REG_DP_GMA_CURVE_CE_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_CE_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_CE_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_CE_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_CE_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_CE_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_CE_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_CE_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_CF DSP2_MISC_REG_DP_GMA_CURVE_CF -#define DSP2_MISC_REG_DP_GMA_CURVE_CF_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_CF_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_CF_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_CF_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_CF_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_CF_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_CF_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_CF_POS)) - -/* 0x2D0 : disp_gma_curve_d0 */ -#define DSP2_MISC_DISP_GMA_CURVE_D0_OFFSET (0x2D0) -#define DSP2_MISC_REG_DP_GMA_CURVE_D0 DSP2_MISC_REG_DP_GMA_CURVE_D0 -#define DSP2_MISC_REG_DP_GMA_CURVE_D0_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_D0_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_D0_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_D0_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_D0_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_D0_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_D0_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_D0_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_D1 DSP2_MISC_REG_DP_GMA_CURVE_D1 -#define DSP2_MISC_REG_DP_GMA_CURVE_D1_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_D1_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_D1_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_D1_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_D1_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_D1_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_D1_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_D1_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_D2 DSP2_MISC_REG_DP_GMA_CURVE_D2 -#define DSP2_MISC_REG_DP_GMA_CURVE_D2_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_D2_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_D2_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_D2_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_D2_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_D2_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_D2_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_D2_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_D3 DSP2_MISC_REG_DP_GMA_CURVE_D3 -#define DSP2_MISC_REG_DP_GMA_CURVE_D3_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_D3_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_D3_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_D3_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_D3_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_D3_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_D3_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_D3_POS)) - -/* 0x2D4 : disp_gma_curve_d4 */ -#define DSP2_MISC_DISP_GMA_CURVE_D4_OFFSET (0x2D4) -#define DSP2_MISC_REG_DP_GMA_CURVE_D4 DSP2_MISC_REG_DP_GMA_CURVE_D4 -#define DSP2_MISC_REG_DP_GMA_CURVE_D4_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_D4_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_D4_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_D4_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_D4_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_D4_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_D4_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_D4_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_D5 DSP2_MISC_REG_DP_GMA_CURVE_D5 -#define DSP2_MISC_REG_DP_GMA_CURVE_D5_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_D5_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_D5_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_D5_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_D5_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_D5_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_D5_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_D5_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_D6 DSP2_MISC_REG_DP_GMA_CURVE_D6 -#define DSP2_MISC_REG_DP_GMA_CURVE_D6_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_D6_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_D6_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_D6_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_D6_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_D6_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_D6_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_D6_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_D7 DSP2_MISC_REG_DP_GMA_CURVE_D7 -#define DSP2_MISC_REG_DP_GMA_CURVE_D7_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_D7_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_D7_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_D7_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_D7_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_D7_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_D7_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_D7_POS)) - -/* 0x2D8 : disp_gma_curve_d8 */ -#define DSP2_MISC_DISP_GMA_CURVE_D8_OFFSET (0x2D8) -#define DSP2_MISC_REG_DP_GMA_CURVE_D8 DSP2_MISC_REG_DP_GMA_CURVE_D8 -#define DSP2_MISC_REG_DP_GMA_CURVE_D8_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_D8_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_D8_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_D8_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_D8_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_D8_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_D8_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_D8_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_D9 DSP2_MISC_REG_DP_GMA_CURVE_D9 -#define DSP2_MISC_REG_DP_GMA_CURVE_D9_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_D9_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_D9_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_D9_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_D9_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_D9_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_D9_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_D9_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_DA DSP2_MISC_REG_DP_GMA_CURVE_DA -#define DSP2_MISC_REG_DP_GMA_CURVE_DA_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_DA_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_DA_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_DA_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_DA_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_DA_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_DA_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_DA_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_DB DSP2_MISC_REG_DP_GMA_CURVE_DB -#define DSP2_MISC_REG_DP_GMA_CURVE_DB_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_DB_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_DB_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_DB_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_DB_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_DB_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_DB_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_DB_POS)) - -/* 0x2DC : disp_gma_curve_dc */ -#define DSP2_MISC_DISP_GMA_CURVE_DC_OFFSET (0x2DC) -#define DSP2_MISC_REG_DP_GMA_CURVE_DC DSP2_MISC_REG_DP_GMA_CURVE_DC -#define DSP2_MISC_REG_DP_GMA_CURVE_DC_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_DC_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_DC_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_DC_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_DC_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_DC_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_DC_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_DC_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_DD DSP2_MISC_REG_DP_GMA_CURVE_DD -#define DSP2_MISC_REG_DP_GMA_CURVE_DD_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_DD_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_DD_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_DD_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_DD_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_DD_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_DD_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_DD_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_DE DSP2_MISC_REG_DP_GMA_CURVE_DE -#define DSP2_MISC_REG_DP_GMA_CURVE_DE_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_DE_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_DE_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_DE_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_DE_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_DE_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_DE_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_DE_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_DF DSP2_MISC_REG_DP_GMA_CURVE_DF -#define DSP2_MISC_REG_DP_GMA_CURVE_DF_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_DF_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_DF_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_DF_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_DF_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_DF_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_DF_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_DF_POS)) - -/* 0x2E0 : disp_gma_curve_e0 */ -#define DSP2_MISC_DISP_GMA_CURVE_E0_OFFSET (0x2E0) -#define DSP2_MISC_REG_DP_GMA_CURVE_E0 DSP2_MISC_REG_DP_GMA_CURVE_E0 -#define DSP2_MISC_REG_DP_GMA_CURVE_E0_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_E0_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_E0_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_E0_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_E0_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_E0_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_E0_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_E0_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_E1 DSP2_MISC_REG_DP_GMA_CURVE_E1 -#define DSP2_MISC_REG_DP_GMA_CURVE_E1_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_E1_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_E1_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_E1_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_E1_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_E1_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_E1_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_E1_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_E2 DSP2_MISC_REG_DP_GMA_CURVE_E2 -#define DSP2_MISC_REG_DP_GMA_CURVE_E2_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_E2_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_E2_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_E2_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_E2_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_E2_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_E2_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_E2_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_E3 DSP2_MISC_REG_DP_GMA_CURVE_E3 -#define DSP2_MISC_REG_DP_GMA_CURVE_E3_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_E3_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_E3_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_E3_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_E3_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_E3_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_E3_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_E3_POS)) - -/* 0x2E4 : disp_gma_curve_e4 */ -#define DSP2_MISC_DISP_GMA_CURVE_E4_OFFSET (0x2E4) -#define DSP2_MISC_REG_DP_GMA_CURVE_E4 DSP2_MISC_REG_DP_GMA_CURVE_E4 -#define DSP2_MISC_REG_DP_GMA_CURVE_E4_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_E4_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_E4_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_E4_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_E4_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_E4_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_E4_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_E4_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_E5 DSP2_MISC_REG_DP_GMA_CURVE_E5 -#define DSP2_MISC_REG_DP_GMA_CURVE_E5_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_E5_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_E5_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_E5_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_E5_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_E5_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_E5_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_E5_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_E6 DSP2_MISC_REG_DP_GMA_CURVE_E6 -#define DSP2_MISC_REG_DP_GMA_CURVE_E6_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_E6_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_E6_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_E6_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_E6_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_E6_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_E6_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_E6_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_E7 DSP2_MISC_REG_DP_GMA_CURVE_E7 -#define DSP2_MISC_REG_DP_GMA_CURVE_E7_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_E7_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_E7_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_E7_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_E7_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_E7_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_E7_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_E7_POS)) - -/* 0x2E8 : disp_gma_curve_e8 */ -#define DSP2_MISC_DISP_GMA_CURVE_E8_OFFSET (0x2E8) -#define DSP2_MISC_REG_DP_GMA_CURVE_E8 DSP2_MISC_REG_DP_GMA_CURVE_E8 -#define DSP2_MISC_REG_DP_GMA_CURVE_E8_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_E8_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_E8_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_E8_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_E8_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_E8_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_E8_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_E8_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_E9 DSP2_MISC_REG_DP_GMA_CURVE_E9 -#define DSP2_MISC_REG_DP_GMA_CURVE_E9_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_E9_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_E9_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_E9_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_E9_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_E9_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_E9_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_E9_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_EA DSP2_MISC_REG_DP_GMA_CURVE_EA -#define DSP2_MISC_REG_DP_GMA_CURVE_EA_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_EA_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_EA_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_EA_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_EA_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_EA_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_EA_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_EA_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_EB DSP2_MISC_REG_DP_GMA_CURVE_EB -#define DSP2_MISC_REG_DP_GMA_CURVE_EB_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_EB_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_EB_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_EB_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_EB_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_EB_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_EB_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_EB_POS)) - -/* 0x2EC : disp_gma_curve_ec */ -#define DSP2_MISC_DISP_GMA_CURVE_EC_OFFSET (0x2EC) -#define DSP2_MISC_REG_DP_GMA_CURVE_EC DSP2_MISC_REG_DP_GMA_CURVE_EC -#define DSP2_MISC_REG_DP_GMA_CURVE_EC_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_EC_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_EC_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_EC_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_EC_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_EC_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_EC_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_EC_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_ED DSP2_MISC_REG_DP_GMA_CURVE_ED -#define DSP2_MISC_REG_DP_GMA_CURVE_ED_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_ED_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_ED_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_ED_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_ED_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_ED_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_ED_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_ED_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_EE DSP2_MISC_REG_DP_GMA_CURVE_EE -#define DSP2_MISC_REG_DP_GMA_CURVE_EE_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_EE_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_EE_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_EE_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_EE_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_EE_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_EE_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_EE_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_EF DSP2_MISC_REG_DP_GMA_CURVE_EF -#define DSP2_MISC_REG_DP_GMA_CURVE_EF_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_EF_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_EF_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_EF_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_EF_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_EF_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_EF_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_EF_POS)) - -/* 0x2F0 : disp_gma_curve_f0 */ -#define DSP2_MISC_DISP_GMA_CURVE_F0_OFFSET (0x2F0) -#define DSP2_MISC_REG_DP_GMA_CURVE_F0 DSP2_MISC_REG_DP_GMA_CURVE_F0 -#define DSP2_MISC_REG_DP_GMA_CURVE_F0_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_F0_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_F0_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_F0_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_F0_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_F0_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_F0_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_F0_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_F1 DSP2_MISC_REG_DP_GMA_CURVE_F1 -#define DSP2_MISC_REG_DP_GMA_CURVE_F1_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_F1_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_F1_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_F1_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_F1_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_F1_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_F1_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_F1_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_F2 DSP2_MISC_REG_DP_GMA_CURVE_F2 -#define DSP2_MISC_REG_DP_GMA_CURVE_F2_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_F2_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_F2_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_F2_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_F2_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_F2_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_F2_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_F2_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_F3 DSP2_MISC_REG_DP_GMA_CURVE_F3 -#define DSP2_MISC_REG_DP_GMA_CURVE_F3_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_F3_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_F3_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_F3_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_F3_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_F3_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_F3_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_F3_POS)) - -/* 0x2F4 : disp_gma_curve_f4 */ -#define DSP2_MISC_DISP_GMA_CURVE_F4_OFFSET (0x2F4) -#define DSP2_MISC_REG_DP_GMA_CURVE_F4 DSP2_MISC_REG_DP_GMA_CURVE_F4 -#define DSP2_MISC_REG_DP_GMA_CURVE_F4_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_F4_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_F4_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_F4_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_F4_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_F4_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_F4_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_F4_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_F5 DSP2_MISC_REG_DP_GMA_CURVE_F5 -#define DSP2_MISC_REG_DP_GMA_CURVE_F5_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_F5_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_F5_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_F5_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_F5_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_F5_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_F5_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_F5_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_F6 DSP2_MISC_REG_DP_GMA_CURVE_F6 -#define DSP2_MISC_REG_DP_GMA_CURVE_F6_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_F6_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_F6_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_F6_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_F6_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_F6_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_F6_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_F6_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_F7 DSP2_MISC_REG_DP_GMA_CURVE_F7 -#define DSP2_MISC_REG_DP_GMA_CURVE_F7_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_F7_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_F7_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_F7_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_F7_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_F7_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_F7_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_F7_POS)) - -/* 0x2F8 : disp_gma_curve_f8 */ -#define DSP2_MISC_DISP_GMA_CURVE_F8_OFFSET (0x2F8) -#define DSP2_MISC_REG_DP_GMA_CURVE_F8 DSP2_MISC_REG_DP_GMA_CURVE_F8 -#define DSP2_MISC_REG_DP_GMA_CURVE_F8_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_F8_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_F8_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_F8_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_F8_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_F8_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_F8_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_F8_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_F9 DSP2_MISC_REG_DP_GMA_CURVE_F9 -#define DSP2_MISC_REG_DP_GMA_CURVE_F9_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_F9_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_F9_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_F9_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_F9_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_F9_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_F9_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_F9_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_FA DSP2_MISC_REG_DP_GMA_CURVE_FA -#define DSP2_MISC_REG_DP_GMA_CURVE_FA_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_FA_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_FA_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_FA_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_FA_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_FA_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_FA_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_FA_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_FB DSP2_MISC_REG_DP_GMA_CURVE_FB -#define DSP2_MISC_REG_DP_GMA_CURVE_FB_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_FB_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_FB_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_FB_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_FB_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_FB_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_FB_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_FB_POS)) - -/* 0x2FC : disp_gma_curve_fc */ -#define DSP2_MISC_DISP_GMA_CURVE_FC_OFFSET (0x2FC) -#define DSP2_MISC_REG_DP_GMA_CURVE_FC DSP2_MISC_REG_DP_GMA_CURVE_FC -#define DSP2_MISC_REG_DP_GMA_CURVE_FC_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_FC_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_FC_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_FC_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_FC_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_FC_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_FC_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_FC_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_FD DSP2_MISC_REG_DP_GMA_CURVE_FD -#define DSP2_MISC_REG_DP_GMA_CURVE_FD_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_FD_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_FD_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_FD_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_FD_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_FD_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_FD_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_FD_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_FE DSP2_MISC_REG_DP_GMA_CURVE_FE -#define DSP2_MISC_REG_DP_GMA_CURVE_FE_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_FE_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_FE_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_FE_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_FE_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_FE_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_FE_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_FE_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_FF DSP2_MISC_REG_DP_GMA_CURVE_FF -#define DSP2_MISC_REG_DP_GMA_CURVE_FF_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_FF_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_FF_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_FF_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_FF_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_FF_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_FF_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_FF_POS)) - -struct dsp2_misc_reg { - /* 0x0 : config */ - union { - struct { - uint32_t rg_dvpas_enable : 1; /* [ 0], r/w, 0x0 */ - uint32_t rg_dvpas_hs_inv : 1; /* [ 1], r/w, 0x0 */ - uint32_t rg_dvpas_vs_inv : 1; /* [ 2], r/w, 0x0 */ - uint32_t rg_dvpas_da_order : 1; /* [ 3], r/w, 0x0 */ - uint32_t reserved_4_15 : 12; /* [15: 4], rsvd, 0x0 */ - uint32_t rg_dvpas_fifo_th : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_29 : 3; /* [29:27], rsvd, 0x0 */ - uint32_t cr_dsp2_de_as_hsync : 1; /* [ 30], r/w, 0x0 */ - uint32_t reg_dsp2_pclk_force_on : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } config; - - /* 0x4 : pix_data_ctrl */ - union { - struct { - uint32_t reg_pix_data_ctrl : 12; /* [11: 0], r/w, 0xfff */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_pix_data_sht_bit : 4; /* [19:16], r/w, 0x0 */ - uint32_t reg_pix_data_sht_dir : 1; /* [ 20], r/w, 0x0 */ - uint32_t reserved_21_30 : 10; /* [30:21], rsvd, 0x0 */ - uint32_t reg_dsp2_dtsrc_src : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } pix_data_ctrl; - - /* 0x8 : dvp2bus_src_sel_1 */ - union { - struct { - uint32_t rg_d2b_dvp_sel_a : 6; /* [ 5: 0], r/w, 0x0 */ - uint32_t reserved_6 : 1; /* [ 6], rsvd, 0x0 */ - uint32_t rg_d2x_id_sel_a : 1; /* [ 7], r/w, 0x0 */ - uint32_t rg_d2b_dvp_sel_b : 6; /* [13: 8], r/w, 0x0 */ - uint32_t reserved_14 : 1; /* [ 14], rsvd, 0x0 */ - uint32_t rg_d2x_id_sel_b : 1; /* [ 15], r/w, 0x0 */ - uint32_t rg_d2b_dvp_sel_c : 6; /* [21:16], r/w, 0x0 */ - uint32_t reserved_22 : 1; /* [ 22], rsvd, 0x0 */ - uint32_t rg_d2x_id_sel_c : 1; /* [ 23], r/w, 0x0 */ - uint32_t rg_d2b_dvp_sel_d : 6; /* [29:24], r/w, 0x0 */ - uint32_t reserved_30 : 1; /* [ 30], rsvd, 0x0 */ - uint32_t rg_d2x_id_sel_d : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dvp2bus_src_sel_1; - - /* 0xC : dvp_frame_m_to_n */ - union { - struct { - uint32_t cr_frame_m_to_n_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ - uint32_t cr_frame_interval : 4; /* [ 7: 4], r/w, 0x0 */ - uint32_t cr_frame_cnt_n : 4; /* [11: 8], r/w, 0x0 */ - uint32_t cr_frame_cnt_m : 4; /* [15:12], r/w, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dvp_frame_m_to_n; - - /* 0x10 : dsp2_id_bayer */ - union { - struct { - uint32_t reg_bayer_idgen_rst : 1; /* [ 0], w1p, 0x0 */ - uint32_t reg_bayer_idgen_edge : 1; /* [ 1], r/w, 0x1 */ - uint32_t reserved_2_15 : 14; /* [15: 2], rsvd, 0x0 */ - uint32_t reg_bayer_idgen_cnt_incr : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dsp2_id_bayer; - - /* 0x14 : dvp2bus_src_sel_2 */ - union { - struct { - uint32_t rg_d2b_dvp_sel_e : 6; /* [ 5: 0], r/w, 0x0 */ - uint32_t reserved_6 : 1; /* [ 6], rsvd, 0x0 */ - uint32_t rg_d2x_id_sel_e : 1; /* [ 7], r/w, 0x0 */ - uint32_t rg_d2b_dvp_sel_f : 6; /* [13: 8], r/w, 0x0 */ - uint32_t reserved_14 : 1; /* [ 14], rsvd, 0x0 */ - uint32_t rg_d2x_id_sel_f : 1; /* [ 15], r/w, 0x0 */ - uint32_t rg_d2b_dvp_sel_g : 6; /* [21:16], r/w, 0x0 */ - uint32_t reserved_22 : 1; /* [ 22], rsvd, 0x0 */ - uint32_t rg_d2x_id_sel_g : 1; /* [ 23], r/w, 0x0 */ - uint32_t rg_d2b_dvp_sel_h : 6; /* [29:24], r/w, 0x0 */ - uint32_t reserved_30 : 1; /* [ 30], rsvd, 0x0 */ - uint32_t rg_d2x_id_sel_h : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dvp2bus_src_sel_2; - - /* 0x18 reserved */ - uint8_t RESERVED0x18[8]; - - /* 0x20 : int_clr */ - union { - struct { - uint32_t rg_awb_int_clr : 1; /* [ 0], w1p, 0x0 */ - uint32_t rg_ae_int_clr : 1; /* [ 1], w1p, 0x0 */ - uint32_t rg_wdr_int_clr : 1; /* [ 2], w1p, 0x0 */ - uint32_t rg_awb2_int_clr : 1; /* [ 3], w1p, 0x0 */ - uint32_t rg_osd_pb_int_clr : 1; /* [ 4], w1p, 0x0 */ - uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ - uint32_t rg_seof1_int_clr : 1; /* [ 8], w1p, 0x0 */ - uint32_t rg_seof2_int_clr : 1; /* [ 9], w1p, 0x0 */ - uint32_t rg_seof3_int_clr : 1; /* [ 10], w1p, 0x0 */ - uint32_t rg_ae_hist_int_clr : 1; /* [ 11], w1p, 0x0 */ - uint32_t rg_awb3_int_clr : 1; /* [ 12], w1p, 0x0 */ - uint32_t rg_dp_seof0_int_clr : 1; /* [ 13], w1p, 0x0 */ - uint32_t rg_seof4_int_clr : 1; /* [ 14], w1p, 0x0 */ - uint32_t reserved_15_31 : 17; /* [31:15], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } int_clr; - - /* 0x24 : int_ctrl */ - union { - struct { - uint32_t rg_ae_int_mask : 1; /* [ 0], r/w, 0x0 */ - uint32_t rg_awb_int_mask : 1; /* [ 1], r/w, 0x0 */ - uint32_t rg_wdr_int_mask : 1; /* [ 2], r/w, 0x0 */ - uint32_t rg_awb2_int_mask : 1; /* [ 3], r/w, 0x0 */ - uint32_t rg_osd_pb_int_mask : 1; /* [ 4], r/w, 0x0 */ - uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ - uint32_t rg_seof1_int_mask : 1; /* [ 8], r/w, 0x0 */ - uint32_t rg_seof1_int_edge : 1; /* [ 9], r/w, 0x0 */ - uint32_t rg_seof1_int_src : 2; /* [11:10], r/w, 0x2 */ - uint32_t rg_seof2_int_mask : 1; /* [ 12], r/w, 0x0 */ - uint32_t rg_seof2_int_edge : 1; /* [ 13], r/w, 0x0 */ - uint32_t rg_seof2_int_src : 2; /* [15:14], r/w, 0x2 */ - uint32_t rg_seof3_int_mask : 1; /* [ 16], r/w, 0x0 */ - uint32_t rg_seof3_int_edge : 1; /* [ 17], r/w, 0x0 */ - uint32_t rg_seof3_int_src : 2; /* [19:18], r/w, 0x2 */ - uint32_t rg_ae_hist_int_mask : 1; /* [ 20], r/w, 0x0 */ - uint32_t rg_awb3_int_mask : 1; /* [ 21], r/w, 0x0 */ - uint32_t rg_dp_seof0_int_src : 1; /* [ 22], r/w, 0x0 */ - uint32_t rg_dp_seof0_int_edge : 1; /* [ 23], r/w, 0x0 */ - uint32_t rg_dp_seof0_int_mask : 1; /* [ 24], r/w, 0x0 */ - uint32_t reserved_25_27 : 3; /* [27:25], rsvd, 0x0 */ - uint32_t rg_seof4_int_mask : 1; /* [ 28], r/w, 0x0 */ - uint32_t rg_seof4_int_edge : 1; /* [ 29], r/w, 0x0 */ - uint32_t rg_seof4_int_src : 2; /* [31:30], r/w, 0x2 */ - } BF; - uint32_t WORD; - } int_ctrl; - - /* 0x28 : dsp2_id_yuv */ - union { - struct { - uint32_t reg_yuv_idgen_rst : 1; /* [ 0], w1p, 0x0 */ - uint32_t reg_yuv_idgen_edge : 1; /* [ 1], r/w, 0x1 */ - uint32_t reserved_2_15 : 14; /* [15: 2], rsvd, 0x0 */ - uint32_t reg_yuv_idgen_cnt_incr : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dsp2_id_yuv; - - /* 0x2C : dvp_reshape */ - union { - struct { - uint32_t reg_rshp_tgl_count : 5; /* [ 4: 0], r/w, 0x0 */ - uint32_t reg_rshp_hsync_inv : 1; /* [ 5], r/w, 0x0 */ - uint32_t reg_rshp_vsync_inv : 1; /* [ 6], r/w, 0x0 */ - uint32_t reg_rshp_clr : 1; /* [ 7], w1p, 0x0 */ - uint32_t reg_rshp_en : 1; /* [ 8], r/w, 0x0 */ - uint32_t reserved_9_31 : 23; /* [31: 9], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dvp_reshape; - - /* 0x30 reserved */ - uint8_t RESERVED0x30[16]; - - /* 0x40 : scalerA_i_size */ - union { - struct { - uint32_t rg_scalerA_i_w : 11; /* [10: 0], r/w, 0x780 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t rg_scalerA_i_h : 11; /* [26:16], r/w, 0x438 */ - uint32_t rg_sclrA_sw_sh : 1; /* [ 27], w1p, 0x0 */ - uint32_t rg_scalerA_bypass : 1; /* [ 28], r/w, 0x1 */ - uint32_t rg_scalerA_sel : 3; /* [31:29], r/w, 0x0 */ - } BF; - uint32_t WORD; - } scalerA_i_size; - - /* 0x44 : scalerA_o_size */ - union { - struct { - uint32_t rg_scalerA_o_w : 11; /* [10: 0], r/w, 0x500 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t rg_scalerA_o_h : 11; /* [26:16], r/w, 0x2d0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } scalerA_o_size; - - /* 0x48 : scalerB_i_size */ - union { - struct { - uint32_t rg_scalerB_i_w : 11; /* [10: 0], r/w, 0x780 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t rg_scalerB_i_h : 11; /* [26:16], r/w, 0x438 */ - uint32_t rg_sclrB_sw_sh : 1; /* [ 27], w1p, 0x0 */ - uint32_t rg_scalerB_bypass : 1; /* [ 28], r/w, 0x1 */ - uint32_t rg_scalerB_sel : 3; /* [31:29], r/w, 0x0 */ - } BF; - uint32_t WORD; - } scalerB_i_size; - - /* 0x4C : scalerB_o_size */ - union { - struct { - uint32_t rg_scalerB_o_w : 11; /* [10: 0], r/w, 0x500 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t rg_scalerB_o_h : 11; /* [26:16], r/w, 0x2d0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } scalerB_o_size; - - /* 0x50 : scalerC_i_size */ - union { - struct { - uint32_t rg_scalerC_i_w : 11; /* [10: 0], r/w, 0x780 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t rg_scalerC_i_h : 11; /* [26:16], r/w, 0x438 */ - uint32_t rg_sclrC_sw_sh : 1; /* [ 27], w1p, 0x0 */ - uint32_t rg_scalerC_bypass : 1; /* [ 28], r/w, 0x1 */ - uint32_t rg_scalerC_sel : 3; /* [31:29], r/w, 0x0 */ - } BF; - uint32_t WORD; - } scalerC_i_size; - - /* 0x54 : scalerC_o_size */ - union { - struct { - uint32_t rg_scalerC_o_w : 11; /* [10: 0], r/w, 0x500 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t rg_scalerC_o_h : 11; /* [26:16], r/w, 0x2d0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } scalerC_o_size; - - /* 0x58 : scalerD_i_size */ - union { - struct { - uint32_t rg_scalerD_i_w : 11; /* [10: 0], r/w, 0x780 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t rg_scalerD_i_h : 11; /* [26:16], r/w, 0x438 */ - uint32_t rg_sclrD_sw_sh : 1; /* [ 27], w1p, 0x0 */ - uint32_t rg_scalerD_bypass : 1; /* [ 28], r/w, 0x1 */ - uint32_t rg_scalerD_sel : 3; /* [31:29], r/w, 0x0 */ - } BF; - uint32_t WORD; - } scalerD_i_size; - - /* 0x5C : scalerD_o_size */ - union { - struct { - uint32_t rg_scalerD_o_w : 11; /* [10: 0], r/w, 0x500 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t rg_scalerD_o_h : 11; /* [26:16], r/w, 0x2d0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } scalerD_o_size; - - /* 0x60 : disp_config */ - union { - struct { - uint32_t reserved_0_3 : 4; /* [ 3: 0], rsvd, 0x0 */ - uint32_t rg_disp_bt656_en : 1; /* [ 4], r/w, 0x0 */ - uint32_t rg_disp_bt1120_en : 1; /* [ 5], r/w, 0x0 */ - uint32_t rg_disp_dpi_en : 1; /* [ 6], r/w, 0x0 */ - uint32_t rg_disp_hdmi_en : 1; /* [ 7], r/w, 0x0 */ - uint32_t rg_disp_mux_sel : 2; /* [ 9: 8], r/w, 0x0 */ - uint32_t reserved_10_11 : 2; /* [11:10], rsvd, 0x0 */ - uint32_t rg_osdDP_sel : 2; /* [13:12], r/w, 0x0 */ - uint32_t reserved_14_30 : 17; /* [30:14], rsvd, 0x0 */ - uint32_t rg_disp_clko_inv : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } disp_config; - - /* 0x64 : disp_dpi_config */ - union { - struct { - uint32_t rg_disp_dpi_hs_w : 8; /* [ 7: 0], r/w, 0x8 */ - uint32_t rg_disp_dpi_hfp_w : 8; /* [15: 8], r/w, 0x10 */ - uint32_t rg_disp_dpi_vs_w : 8; /* [23:16], r/w, 0x2 */ - uint32_t rg_disp_dpi_vfp_w : 8; /* [31:24], r/w, 0x4 */ - } BF; - uint32_t WORD; - } disp_dpi_config; - - /* 0x68 : disp_yuv_rgb_config_0 */ - union { - struct { - uint32_t rg_disp_y2r_pre_0 : 9; /* [ 8: 0], r/w, 0x0 */ - uint32_t reserved_9 : 1; /* [ 9], rsvd, 0x0 */ - uint32_t rg_disp_y2r_pre_1 : 9; /* [18:10], r/w, 0x0 */ - uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */ - uint32_t rg_disp_y2r_pre_2 : 9; /* [28:20], r/w, 0x0 */ - uint32_t reserved_29_30 : 2; /* [30:29], rsvd, 0x0 */ - uint32_t rg_disp_y2r_en : 1; /* [ 31], r/w, 0x1 */ - } BF; - uint32_t WORD; - } disp_yuv_rgb_config_0; - - /* 0x6C : disp_yuv_rgb_config_1 */ - union { - struct { - uint32_t rg_disp_y2r_pos_0 : 9; /* [ 8: 0], r/w, 0x0 */ - uint32_t reserved_9 : 1; /* [ 9], rsvd, 0x0 */ - uint32_t rg_disp_y2r_pos_1 : 9; /* [18:10], r/w, 0x0 */ - uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */ - uint32_t rg_disp_y2r_pos_2 : 9; /* [28:20], r/w, 0x0 */ - uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } disp_yuv_rgb_config_1; - - /* 0x70 : disp_yuv_rgb_config_2 */ - union { - struct { - uint32_t rg_disp_y2r_mtx_00 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t rg_disp_y2r_mtx_01 : 12; /* [23:12], r/w, 0x0 */ - uint32_t rg_disp_y2r_mtx_02_l : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } disp_yuv_rgb_config_2; - - /* 0x74 : disp_yuv_rgb_config_3 */ - union { - struct { - uint32_t rg_disp_y2r_mtx_02_u : 4; /* [ 3: 0], r/w, 0x0 */ - uint32_t rg_disp_y2r_mtx_10 : 12; /* [15: 4], r/w, 0x0 */ - uint32_t rg_disp_y2r_mtx_11 : 12; /* [27:16], r/w, 0x0 */ - uint32_t rg_disp_y2r_mtx_12_l : 4; /* [31:28], r/w, 0x0 */ - } BF; - uint32_t WORD; - } disp_yuv_rgb_config_3; - - /* 0x78 : disp_yuv_rgb_config_4 */ - union { - struct { - uint32_t rg_disp_y2r_mtx_12_u : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t rg_disp_y2r_mtx_20 : 12; /* [19: 8], r/w, 0x0 */ - uint32_t rg_disp_y2r_mtx_21 : 12; /* [31:20], r/w, 0x0 */ - } BF; - uint32_t WORD; - } disp_yuv_rgb_config_4; - - /* 0x7C : disp_yuv_rgb_config_5 */ - union { - struct { - uint32_t rg_disp_y2r_mtx_22 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } disp_yuv_rgb_config_5; - - /* 0x80 : dsp2_subsys_bus_ctrl */ - union { - struct { - uint32_t rg_dsp2_sub_pclk_force_on : 16; /* [15: 0], r/w, 0x0 */ - uint32_t rg_dsp2_peri_pclk_force_on : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dsp2_subsys_bus_ctrl; - - /* 0x84 reserved */ - uint8_t RESERVED0x84[28]; - - /* 0xA0 : osdA_i_ctrl */ - union { - struct { - uint32_t rg_osd_pb_sel : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_28 : 28; /* [28: 1], rsvd, 0x0 */ - uint32_t rg_osdA_sel : 3; /* [31:29], r/w, 0x0 */ - } BF; - uint32_t WORD; - } osdA_i_ctrl; - - /* 0xA4 : osdB_i_ctrl */ - union { - struct { - uint32_t reserved_0_28 : 29; /* [28: 0], rsvd, 0x0 */ - uint32_t rg_osdB_sel : 3; /* [31:29], r/w, 0x0 */ - } BF; - uint32_t WORD; - } osdB_i_ctrl; - - /* 0xA8 : osdC_i_ctrl */ - union { - struct { - uint32_t reserved_0_28 : 29; /* [28: 0], rsvd, 0x0 */ - uint32_t rg_osdC_sel : 3; /* [31:29], r/w, 0x0 */ - } BF; - uint32_t WORD; - } osdC_i_ctrl; - - /* 0xAC : osdD_i_ctrl */ - union { - struct { - uint32_t reserved_0_28 : 29; /* [28: 0], rsvd, 0x0 */ - uint32_t rg_osdD_sel : 3; /* [31:29], r/w, 0x0 */ - } BF; - uint32_t WORD; - } osdD_i_ctrl; - - /* 0xb0 reserved */ - uint8_t RESERVED0xb0[16]; - - /* 0xC0 : dsp2_subsys_dbg_sel */ - union { - struct { - uint32_t reg_dsp2_sub_dbg_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ - uint32_t reg_dsp2_sub_dbg_sel : 4; /* [ 7: 4], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dsp2_subsys_dbg_sel; - - /* 0xc4 reserved */ - uint8_t RESERVED0xc4[56]; - - /* 0xFC : DSP2_MISC_Dummy */ - union { - struct { - uint32_t dummy_reg : 32; /* [31: 0], r/w, 0xffff0000 */ - } BF; - uint32_t WORD; - } DSP2_MISC_Dummy; - - /* 0x100 : adjA_ctrl_0 */ - union { - struct { - uint32_t reg_adjA_adj_eb : 1; /* [ 0], r/w, 0x0 */ - uint32_t reg_adjA_y_luma : 9; /* [ 9: 1], r/w, 0x0 */ - uint32_t reg_adjA_y_mul0 : 11; /* [20:10], r/w, 0x380 */ - uint32_t reg_adjA_y_mul1 : 11; /* [31:21], r/w, 0x35e */ - } BF; - uint32_t WORD; - } adjA_ctrl_0; - - /* 0x104 : adjA_ctrl_1 */ - union { - struct { - uint32_t reg_adjA_y_min : 8; /* [ 7: 0], r/w, 0x10 */ - uint32_t reg_adjA_y_max : 8; /* [15: 8], r/w, 0xeb */ - uint32_t reg_adjA_uv_min : 8; /* [23:16], r/w, 0x10 */ - uint32_t reg_adjA_uv_max : 8; /* [31:24], r/w, 0xf0 */ - } BF; - uint32_t WORD; - } adjA_ctrl_1; - - /* 0x108 : adjA_ctrl_2 */ - union { - struct { - uint32_t rg_adjA_sel : 4; /* [ 3: 0], r/w, 0x0 */ - uint32_t reserved_4_9 : 6; /* [ 9: 4], rsvd, 0x0 */ - uint32_t reg_adjA_uv_mul0 : 11; /* [20:10], r/w, 0x380 */ - uint32_t reg_adjA_uv_mul1 : 11; /* [31:21], r/w, 0x387 */ - } BF; - uint32_t WORD; - } adjA_ctrl_2; - - /* 0x10c reserved */ - uint8_t RESERVED0x10c[4]; - - /* 0x110 : adjB_ctrl_0 */ - union { - struct { - uint32_t reg_adjB_adj_eb : 1; /* [ 0], r/w, 0x0 */ - uint32_t reg_adjB_y_luma : 9; /* [ 9: 1], r/w, 0x0 */ - uint32_t reg_adjB_y_mul0 : 11; /* [20:10], r/w, 0x380 */ - uint32_t reg_adjB_y_mul1 : 11; /* [31:21], r/w, 0x35e */ - } BF; - uint32_t WORD; - } adjB_ctrl_0; - - /* 0x114 : adjB_ctrl_1 */ - union { - struct { - uint32_t reg_adjB_y_min : 8; /* [ 7: 0], r/w, 0x10 */ - uint32_t reg_adjB_y_max : 8; /* [15: 8], r/w, 0xeb */ - uint32_t reg_adjB_uv_min : 8; /* [23:16], r/w, 0x10 */ - uint32_t reg_adjB_uv_max : 8; /* [31:24], r/w, 0xf0 */ - } BF; - uint32_t WORD; - } adjB_ctrl_1; - - /* 0x118 : adjB_ctrl_2 */ - union { - struct { - uint32_t rg_adjB_sel : 4; /* [ 3: 0], r/w, 0x0 */ - uint32_t reserved_4_9 : 6; /* [ 9: 4], rsvd, 0x0 */ - uint32_t reg_adjB_uv_mul0 : 11; /* [20:10], r/w, 0x380 */ - uint32_t reg_adjB_uv_mul1 : 11; /* [31:21], r/w, 0x387 */ - } BF; - uint32_t WORD; - } adjB_ctrl_2; - - /* 0x11c reserved */ - uint8_t RESERVED0x11c[4]; - - /* 0x120 : adjC_ctrl_0 */ - union { - struct { - uint32_t reg_adjC_adj_eb : 1; /* [ 0], r/w, 0x0 */ - uint32_t reg_adjC_y_luma : 9; /* [ 9: 1], r/w, 0x0 */ - uint32_t reg_adjC_y_mul0 : 11; /* [20:10], r/w, 0x380 */ - uint32_t reg_adjC_y_mul1 : 11; /* [31:21], r/w, 0x35e */ - } BF; - uint32_t WORD; - } adjC_ctrl_0; - - /* 0x124 : adjC_ctrl_1 */ - union { - struct { - uint32_t reg_adjC_y_min : 8; /* [ 7: 0], r/w, 0x10 */ - uint32_t reg_adjC_y_max : 8; /* [15: 8], r/w, 0xeb */ - uint32_t reg_adjC_uv_min : 8; /* [23:16], r/w, 0x10 */ - uint32_t reg_adjC_uv_max : 8; /* [31:24], r/w, 0xf0 */ - } BF; - uint32_t WORD; - } adjC_ctrl_1; - - /* 0x128 : adjC_ctrl_2 */ - union { - struct { - uint32_t rg_adjC_sel : 4; /* [ 3: 0], r/w, 0x0 */ - uint32_t reserved_4_9 : 6; /* [ 9: 4], rsvd, 0x0 */ - uint32_t reg_adjC_uv_mul0 : 11; /* [20:10], r/w, 0x380 */ - uint32_t reg_adjC_uv_mul1 : 11; /* [31:21], r/w, 0x387 */ - } BF; - uint32_t WORD; - } adjC_ctrl_2; - - /* 0x12c reserved */ - uint8_t RESERVED0x12c[4]; - - /* 0x130 : adjD_ctrl_0 */ - union { - struct { - uint32_t reg_adjD_adj_eb : 1; /* [ 0], r/w, 0x0 */ - uint32_t reg_adjD_y_luma : 9; /* [ 9: 1], r/w, 0x0 */ - uint32_t reg_adjD_y_mul0 : 11; /* [20:10], r/w, 0x380 */ - uint32_t reg_adjD_y_mul1 : 11; /* [31:21], r/w, 0x35e */ - } BF; - uint32_t WORD; - } adjD_ctrl_0; - - /* 0x134 : adjD_ctrl_1 */ - union { - struct { - uint32_t reg_adjD_y_min : 8; /* [ 7: 0], r/w, 0x10 */ - uint32_t reg_adjD_y_max : 8; /* [15: 8], r/w, 0xeb */ - uint32_t reg_adjD_uv_min : 8; /* [23:16], r/w, 0x10 */ - uint32_t reg_adjD_uv_max : 8; /* [31:24], r/w, 0xf0 */ - } BF; - uint32_t WORD; - } adjD_ctrl_1; - - /* 0x138 : adjD_ctrl_2 */ - union { - struct { - uint32_t rg_adjD_sel : 4; /* [ 3: 0], r/w, 0x0 */ - uint32_t reserved_4_9 : 6; /* [ 9: 4], rsvd, 0x0 */ - uint32_t reg_adjD_uv_mul0 : 11; /* [20:10], r/w, 0x380 */ - uint32_t reg_adjD_uv_mul1 : 11; /* [31:21], r/w, 0x387 */ - } BF; - uint32_t WORD; - } adjD_ctrl_2; - - /* 0x13c reserved */ - uint8_t RESERVED0x13c[36]; - - /* 0x160 : y2rA_config_0 */ - union { - struct { - uint32_t rg_y2rA_pre_0 : 9; /* [ 8: 0], r/w, 0x0 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t rg_y2rA_pos_0 : 9; /* [24:16], r/w, 0x0 */ - uint32_t reserved_25_26 : 2; /* [26:25], rsvd, 0x0 */ - uint32_t rg_y2rA_en : 1; /* [ 27], r/w, 0x0 */ - uint32_t rg_y2rA_sel : 4; /* [31:28], r/w, 0x0 */ - } BF; - uint32_t WORD; - } y2rA_config_0; - - /* 0x164 : y2rA_config_1 */ - union { - struct { - uint32_t rg_y2rA_pre_1 : 9; /* [ 8: 0], r/w, 0x0 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t rg_y2rA_pos_1 : 9; /* [24:16], r/w, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } y2rA_config_1; - - /* 0x168 : y2rA_config_2 */ - union { - struct { - uint32_t rg_y2rA_pre_2 : 9; /* [ 8: 0], r/w, 0x0 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t rg_y2rA_pos_2 : 9; /* [24:16], r/w, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } y2rA_config_2; - - /* 0x16C : y2rA_config_3 */ - union { - struct { - uint32_t rg_y2rA_mtx_00 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t rg_y2rA_mtx_01 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } y2rA_config_3; - - /* 0x170 : y2rA_config_4 */ - union { - struct { - uint32_t rg_y2rA_mtx_02 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t rg_y2rA_mtx_10 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } y2rA_config_4; - - /* 0x174 : y2rA_config_5 */ - union { - struct { - uint32_t rg_y2rA_mtx_11 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t rg_y2rA_mtx_12 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } y2rA_config_5; - - /* 0x178 : y2rA_config_6 */ - union { - struct { - uint32_t rg_y2rA_mtx_20 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t rg_y2rA_mtx_21 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } y2rA_config_6; - - /* 0x17C : y2rA_config_7 */ - union { - struct { - uint32_t rg_y2rA_mtx_22 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } y2rA_config_7; - - /* 0x180 : disp_rgb2yuv_config_0 */ - union { - struct { - uint32_t rg_disp_r2y_pre_0 : 9; /* [ 8: 0], r/w, 0x0 */ - uint32_t reserved_9 : 1; /* [ 9], rsvd, 0x0 */ - uint32_t rg_disp_r2y_pre_1 : 9; /* [18:10], r/w, 0x0 */ - uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */ - uint32_t rg_disp_r2y_pre_2 : 9; /* [28:20], r/w, 0x0 */ - uint32_t reserved_29_30 : 2; /* [30:29], rsvd, 0x0 */ - uint32_t rg_disp_r2y_en : 1; /* [ 31], r/w, 0x1 */ - } BF; - uint32_t WORD; - } disp_rgb2yuv_config_0; - - /* 0x184 : disp_rgb2yuv_config_1 */ - union { - struct { - uint32_t rg_disp_r2y_pos_0 : 9; /* [ 8: 0], r/w, 0x0 */ - uint32_t reserved_9 : 1; /* [ 9], rsvd, 0x0 */ - uint32_t rg_disp_r2y_pos_1 : 9; /* [18:10], r/w, 0x80 */ - uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */ - uint32_t rg_disp_r2y_pos_2 : 9; /* [28:20], r/w, 0x80 */ - uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } disp_rgb2yuv_config_1; - - /* 0x188 : disp_rgb2yuv_config_2 */ - union { - struct { - uint32_t rg_disp_r2y_mtx_00 : 12; /* [11: 0], r/w, 0x99 */ - uint32_t rg_disp_r2y_mtx_01 : 12; /* [23:12], r/w, 0x12d */ - uint32_t rg_disp_r2y_mtx_02_l : 8; /* [31:24], r/w, 0x3a */ - } BF; - uint32_t WORD; - } disp_rgb2yuv_config_2; - - /* 0x18C : disp_rgb2yuv_config_3 */ - union { - struct { - uint32_t rg_disp_r2y_mtx_02_u : 4; /* [ 3: 0], r/w, 0x0 */ - uint32_t rg_disp_r2y_mtx_10 : 12; /* [15: 4], r/w, 0xfa9 */ - uint32_t rg_disp_r2y_mtx_11 : 12; /* [27:16], r/w, 0xf57 */ - uint32_t rg_disp_r2y_mtx_12_l : 4; /* [31:28], r/w, 0x0 */ - } BF; - uint32_t WORD; - } disp_rgb2yuv_config_3; - - /* 0x190 : disp_rgb2yuv_config_4 */ - union { - struct { - uint32_t rg_disp_r2y_mtx_12_u : 8; /* [ 7: 0], r/w, 0x10 */ - uint32_t rg_disp_r2y_mtx_20 : 12; /* [19: 8], r/w, 0x100 */ - uint32_t rg_disp_r2y_mtx_21 : 12; /* [31:20], r/w, 0xf29 */ - } BF; - uint32_t WORD; - } disp_rgb2yuv_config_4; - - /* 0x194 : disp_rgb2yuv_config_5 */ - union { - struct { - uint32_t rg_disp_r2y_mtx_22 : 12; /* [11: 0], r/w, 0xfd7 */ - uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } disp_rgb2yuv_config_5; - - /* 0x198 reserved */ - uint8_t RESERVED0x198[40]; - - /* 0x1C0 : cropA_hsync */ - union { - struct { - uint32_t reg_cropA_hsync_start : 16; /* [15: 0], r/w, 0x0 */ - uint32_t reg_cropA_hsync_end : 16; /* [31:16], r/w, 0xffff */ - } BF; - uint32_t WORD; - } cropA_hsync; - - /* 0x1C4 : cropA_vsync */ - union { - struct { - uint32_t reg_cropA_vsync_start : 16; /* [15: 0], r/w, 0x0 */ - uint32_t reg_cropA_vsync_end : 16; /* [31:16], r/w, 0xffff */ - } BF; - uint32_t WORD; - } cropA_vsync; - - /* 0x1C8 : cropB_hsync */ - union { - struct { - uint32_t reg_cropB_hsync_start : 16; /* [15: 0], r/w, 0x0 */ - uint32_t reg_cropB_hsync_end : 16; /* [31:16], r/w, 0xffff */ - } BF; - uint32_t WORD; - } cropB_hsync; - - /* 0x1CC : cropB_vsync */ - union { - struct { - uint32_t reg_cropB_vsync_start : 16; /* [15: 0], r/w, 0x0 */ - uint32_t reg_cropB_vsync_end : 16; /* [31:16], r/w, 0xffff */ - } BF; - uint32_t WORD; - } cropB_vsync; - - /* 0x1D0 : cropC_hsync */ - union { - struct { - uint32_t reg_cropC_hsync_start : 16; /* [15: 0], r/w, 0x0 */ - uint32_t reg_cropC_hsync_end : 16; /* [31:16], r/w, 0xffff */ - } BF; - uint32_t WORD; - } cropC_hsync; - - /* 0x1D4 : cropC_vsync */ - union { - struct { - uint32_t reg_cropC_vsync_start : 16; /* [15: 0], r/w, 0x0 */ - uint32_t reg_cropC_vsync_end : 16; /* [31:16], r/w, 0xffff */ - } BF; - uint32_t WORD; - } cropC_vsync; - - /* 0x1D8 : cropD_hsync */ - union { - struct { - uint32_t reg_cropD_hsync_start : 16; /* [15: 0], r/w, 0x0 */ - uint32_t reg_cropD_hsync_end : 16; /* [31:16], r/w, 0xffff */ - } BF; - uint32_t WORD; - } cropD_hsync; - - /* 0x1DC : cropD_vsync */ - union { - struct { - uint32_t reg_cropD_vsync_start : 16; /* [15: 0], r/w, 0x0 */ - uint32_t reg_cropD_vsync_end : 16; /* [31:16], r/w, 0xffff */ - } BF; - uint32_t WORD; - } cropD_vsync; - - /* 0x1E0 : crop_enable */ - union { - struct { - uint32_t reg_cropA_enable : 1; /* [ 0], r/w, 0x0 */ - uint32_t reg_cropB_enable : 1; /* [ 1], r/w, 0x0 */ - uint32_t reg_cropC_enable : 1; /* [ 2], r/w, 0x0 */ - uint32_t reg_cropD_enable : 1; /* [ 3], r/w, 0x0 */ - uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } crop_enable; - - /* 0x1e4 reserved */ - uint8_t RESERVED0x1e4[24]; - - /* 0x1FC : disp_gma_cfg */ - union { - struct { - uint32_t reg_dp_gma_ch0_en : 1; /* [ 0], r/w, 0x1 */ - uint32_t reg_dp_gma_ch1_en : 1; /* [ 1], r/w, 0x1 */ - uint32_t reg_dp_gma_ch2_en : 1; /* [ 2], r/w, 0x1 */ - uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } disp_gma_cfg; - - /* 0x200 : disp_gma_curve_00 */ - union { - struct { - uint32_t reg_dp_gma_curve_00 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_dp_gma_curve_01 : 8; /* [15: 8], r/w, 0x1 */ - uint32_t reg_dp_gma_curve_02 : 8; /* [23:16], r/w, 0x2 */ - uint32_t reg_dp_gma_curve_03 : 8; /* [31:24], r/w, 0x3 */ - } BF; - uint32_t WORD; - } disp_gma_curve_00; - - /* 0x204 : disp_gma_curve_04 */ - union { - struct { - uint32_t reg_dp_gma_curve_04 : 8; /* [ 7: 0], r/w, 0x4 */ - uint32_t reg_dp_gma_curve_05 : 8; /* [15: 8], r/w, 0x5 */ - uint32_t reg_dp_gma_curve_06 : 8; /* [23:16], r/w, 0x6 */ - uint32_t reg_dp_gma_curve_07 : 8; /* [31:24], r/w, 0x7 */ - } BF; - uint32_t WORD; - } disp_gma_curve_04; - - /* 0x208 : disp_gma_curve_08 */ - union { - struct { - uint32_t reg_dp_gma_curve_08 : 8; /* [ 7: 0], r/w, 0x8 */ - uint32_t reg_dp_gma_curve_09 : 8; /* [15: 8], r/w, 0x9 */ - uint32_t reg_dp_gma_curve_0a : 8; /* [23:16], r/w, 0xa */ - uint32_t reg_dp_gma_curve_0b : 8; /* [31:24], r/w, 0xb */ - } BF; - uint32_t WORD; - } disp_gma_curve_08; - - /* 0x20C : disp_gma_curve_0c */ - union { - struct { - uint32_t reg_dp_gma_curve_0c : 8; /* [ 7: 0], r/w, 0xc */ - uint32_t reg_dp_gma_curve_0d : 8; /* [15: 8], r/w, 0xd */ - uint32_t reg_dp_gma_curve_0e : 8; /* [23:16], r/w, 0xe */ - uint32_t reg_dp_gma_curve_0f : 8; /* [31:24], r/w, 0xf */ - } BF; - uint32_t WORD; - } disp_gma_curve_0c; - - /* 0x210 : disp_gma_curve_10 */ - union { - struct { - uint32_t reg_dp_gma_curve_10 : 8; /* [ 7: 0], r/w, 0x10 */ - uint32_t reg_dp_gma_curve_11 : 8; /* [15: 8], r/w, 0x11 */ - uint32_t reg_dp_gma_curve_12 : 8; /* [23:16], r/w, 0x12 */ - uint32_t reg_dp_gma_curve_13 : 8; /* [31:24], r/w, 0x13 */ - } BF; - uint32_t WORD; - } disp_gma_curve_10; - - /* 0x214 : disp_gma_curve_14 */ - union { - struct { - uint32_t reg_dp_gma_curve_14 : 8; /* [ 7: 0], r/w, 0x14 */ - uint32_t reg_dp_gma_curve_15 : 8; /* [15: 8], r/w, 0x15 */ - uint32_t reg_dp_gma_curve_16 : 8; /* [23:16], r/w, 0x16 */ - uint32_t reg_dp_gma_curve_17 : 8; /* [31:24], r/w, 0x17 */ - } BF; - uint32_t WORD; - } disp_gma_curve_14; - - /* 0x218 : disp_gma_curve_18 */ - union { - struct { - uint32_t reg_dp_gma_curve_18 : 8; /* [ 7: 0], r/w, 0x18 */ - uint32_t reg_dp_gma_curve_19 : 8; /* [15: 8], r/w, 0x19 */ - uint32_t reg_dp_gma_curve_1a : 8; /* [23:16], r/w, 0x1a */ - uint32_t reg_dp_gma_curve_1b : 8; /* [31:24], r/w, 0x1b */ - } BF; - uint32_t WORD; - } disp_gma_curve_18; - - /* 0x21C : disp_gma_curve_1c */ - union { - struct { - uint32_t reg_dp_gma_curve_1c : 8; /* [ 7: 0], r/w, 0x1c */ - uint32_t reg_dp_gma_curve_1d : 8; /* [15: 8], r/w, 0x1d */ - uint32_t reg_dp_gma_curve_1e : 8; /* [23:16], r/w, 0x1e */ - uint32_t reg_dp_gma_curve_1f : 8; /* [31:24], r/w, 0x1f */ - } BF; - uint32_t WORD; - } disp_gma_curve_1c; - - /* 0x220 : disp_gma_curve_20 */ - union { - struct { - uint32_t reg_dp_gma_curve_20 : 8; /* [ 7: 0], r/w, 0x20 */ - uint32_t reg_dp_gma_curve_21 : 8; /* [15: 8], r/w, 0x21 */ - uint32_t reg_dp_gma_curve_22 : 8; /* [23:16], r/w, 0x22 */ - uint32_t reg_dp_gma_curve_23 : 8; /* [31:24], r/w, 0x23 */ - } BF; - uint32_t WORD; - } disp_gma_curve_20; - - /* 0x224 : disp_gma_curve_24 */ - union { - struct { - uint32_t reg_dp_gma_curve_24 : 8; /* [ 7: 0], r/w, 0x24 */ - uint32_t reg_dp_gma_curve_25 : 8; /* [15: 8], r/w, 0x25 */ - uint32_t reg_dp_gma_curve_26 : 8; /* [23:16], r/w, 0x26 */ - uint32_t reg_dp_gma_curve_27 : 8; /* [31:24], r/w, 0x27 */ - } BF; - uint32_t WORD; - } disp_gma_curve_24; - - /* 0x228 : disp_gma_curve_28 */ - union { - struct { - uint32_t reg_dp_gma_curve_28 : 8; /* [ 7: 0], r/w, 0x28 */ - uint32_t reg_dp_gma_curve_29 : 8; /* [15: 8], r/w, 0x29 */ - uint32_t reg_dp_gma_curve_2a : 8; /* [23:16], r/w, 0x2a */ - uint32_t reg_dp_gma_curve_2b : 8; /* [31:24], r/w, 0x2b */ - } BF; - uint32_t WORD; - } disp_gma_curve_28; - - /* 0x22C : disp_gma_curve_2c */ - union { - struct { - uint32_t reg_dp_gma_curve_2c : 8; /* [ 7: 0], r/w, 0x2c */ - uint32_t reg_dp_gma_curve_2d : 8; /* [15: 8], r/w, 0x2d */ - uint32_t reg_dp_gma_curve_2e : 8; /* [23:16], r/w, 0x2e */ - uint32_t reg_dp_gma_curve_2f : 8; /* [31:24], r/w, 0x2f */ - } BF; - uint32_t WORD; - } disp_gma_curve_2c; - - /* 0x230 : disp_gma_curve_30 */ - union { - struct { - uint32_t reg_dp_gma_curve_30 : 8; /* [ 7: 0], r/w, 0x30 */ - uint32_t reg_dp_gma_curve_31 : 8; /* [15: 8], r/w, 0x31 */ - uint32_t reg_dp_gma_curve_32 : 8; /* [23:16], r/w, 0x32 */ - uint32_t reg_dp_gma_curve_33 : 8; /* [31:24], r/w, 0x33 */ - } BF; - uint32_t WORD; - } disp_gma_curve_30; - - /* 0x234 : disp_gma_curve_34 */ - union { - struct { - uint32_t reg_dp_gma_curve_34 : 8; /* [ 7: 0], r/w, 0x34 */ - uint32_t reg_dp_gma_curve_35 : 8; /* [15: 8], r/w, 0x35 */ - uint32_t reg_dp_gma_curve_36 : 8; /* [23:16], r/w, 0x36 */ - uint32_t reg_dp_gma_curve_37 : 8; /* [31:24], r/w, 0x37 */ - } BF; - uint32_t WORD; - } disp_gma_curve_34; - - /* 0x238 : disp_gma_curve_38 */ - union { - struct { - uint32_t reg_dp_gma_curve_38 : 8; /* [ 7: 0], r/w, 0x38 */ - uint32_t reg_dp_gma_curve_39 : 8; /* [15: 8], r/w, 0x39 */ - uint32_t reg_dp_gma_curve_3a : 8; /* [23:16], r/w, 0x3a */ - uint32_t reg_dp_gma_curve_3b : 8; /* [31:24], r/w, 0x3b */ - } BF; - uint32_t WORD; - } disp_gma_curve_38; - - /* 0x23C : disp_gma_curve_3c */ - union { - struct { - uint32_t reg_dp_gma_curve_3c : 8; /* [ 7: 0], r/w, 0x3c */ - uint32_t reg_dp_gma_curve_3d : 8; /* [15: 8], r/w, 0x3d */ - uint32_t reg_dp_gma_curve_3e : 8; /* [23:16], r/w, 0x3e */ - uint32_t reg_dp_gma_curve_3f : 8; /* [31:24], r/w, 0x3f */ - } BF; - uint32_t WORD; - } disp_gma_curve_3c; - - /* 0x240 : disp_gma_curve_40 */ - union { - struct { - uint32_t reg_dp_gma_curve_40 : 8; /* [ 7: 0], r/w, 0x40 */ - uint32_t reg_dp_gma_curve_41 : 8; /* [15: 8], r/w, 0x41 */ - uint32_t reg_dp_gma_curve_42 : 8; /* [23:16], r/w, 0x42 */ - uint32_t reg_dp_gma_curve_43 : 8; /* [31:24], r/w, 0x43 */ - } BF; - uint32_t WORD; - } disp_gma_curve_40; - - /* 0x244 : disp_gma_curve_44 */ - union { - struct { - uint32_t reg_dp_gma_curve_44 : 8; /* [ 7: 0], r/w, 0x44 */ - uint32_t reg_dp_gma_curve_45 : 8; /* [15: 8], r/w, 0x45 */ - uint32_t reg_dp_gma_curve_46 : 8; /* [23:16], r/w, 0x46 */ - uint32_t reg_dp_gma_curve_47 : 8; /* [31:24], r/w, 0x47 */ - } BF; - uint32_t WORD; - } disp_gma_curve_44; - - /* 0x248 : disp_gma_curve_48 */ - union { - struct { - uint32_t reg_dp_gma_curve_48 : 8; /* [ 7: 0], r/w, 0x48 */ - uint32_t reg_dp_gma_curve_49 : 8; /* [15: 8], r/w, 0x49 */ - uint32_t reg_dp_gma_curve_4a : 8; /* [23:16], r/w, 0x4a */ - uint32_t reg_dp_gma_curve_4b : 8; /* [31:24], r/w, 0x4b */ - } BF; - uint32_t WORD; - } disp_gma_curve_48; - - /* 0x24C : disp_gma_curve_4c */ - union { - struct { - uint32_t reg_dp_gma_curve_4c : 8; /* [ 7: 0], r/w, 0x4c */ - uint32_t reg_dp_gma_curve_4d : 8; /* [15: 8], r/w, 0x4d */ - uint32_t reg_dp_gma_curve_4e : 8; /* [23:16], r/w, 0x4e */ - uint32_t reg_dp_gma_curve_4f : 8; /* [31:24], r/w, 0x4f */ - } BF; - uint32_t WORD; - } disp_gma_curve_4c; - - /* 0x250 : disp_gma_curve_50 */ - union { - struct { - uint32_t reg_dp_gma_curve_50 : 8; /* [ 7: 0], r/w, 0x50 */ - uint32_t reg_dp_gma_curve_51 : 8; /* [15: 8], r/w, 0x51 */ - uint32_t reg_dp_gma_curve_52 : 8; /* [23:16], r/w, 0x52 */ - uint32_t reg_dp_gma_curve_53 : 8; /* [31:24], r/w, 0x53 */ - } BF; - uint32_t WORD; - } disp_gma_curve_50; - - /* 0x254 : disp_gma_curve_54 */ - union { - struct { - uint32_t reg_dp_gma_curve_54 : 8; /* [ 7: 0], r/w, 0x54 */ - uint32_t reg_dp_gma_curve_55 : 8; /* [15: 8], r/w, 0x55 */ - uint32_t reg_dp_gma_curve_56 : 8; /* [23:16], r/w, 0x56 */ - uint32_t reg_dp_gma_curve_57 : 8; /* [31:24], r/w, 0x57 */ - } BF; - uint32_t WORD; - } disp_gma_curve_54; - - /* 0x258 : disp_gma_curve_58 */ - union { - struct { - uint32_t reg_dp_gma_curve_58 : 8; /* [ 7: 0], r/w, 0x58 */ - uint32_t reg_dp_gma_curve_59 : 8; /* [15: 8], r/w, 0x59 */ - uint32_t reg_dp_gma_curve_5a : 8; /* [23:16], r/w, 0x5a */ - uint32_t reg_dp_gma_curve_5b : 8; /* [31:24], r/w, 0x5b */ - } BF; - uint32_t WORD; - } disp_gma_curve_58; - - /* 0x25C : disp_gma_curve_5c */ - union { - struct { - uint32_t reg_dp_gma_curve_5c : 8; /* [ 7: 0], r/w, 0x5c */ - uint32_t reg_dp_gma_curve_5d : 8; /* [15: 8], r/w, 0x5d */ - uint32_t reg_dp_gma_curve_5e : 8; /* [23:16], r/w, 0x5e */ - uint32_t reg_dp_gma_curve_5f : 8; /* [31:24], r/w, 0x5f */ - } BF; - uint32_t WORD; - } disp_gma_curve_5c; - - /* 0x260 : disp_gma_curve_60 */ - union { - struct { - uint32_t reg_dp_gma_curve_60 : 8; /* [ 7: 0], r/w, 0x60 */ - uint32_t reg_dp_gma_curve_61 : 8; /* [15: 8], r/w, 0x61 */ - uint32_t reg_dp_gma_curve_62 : 8; /* [23:16], r/w, 0x62 */ - uint32_t reg_dp_gma_curve_63 : 8; /* [31:24], r/w, 0x63 */ - } BF; - uint32_t WORD; - } disp_gma_curve_60; - - /* 0x264 : disp_gma_curve_64 */ - union { - struct { - uint32_t reg_dp_gma_curve_64 : 8; /* [ 7: 0], r/w, 0x64 */ - uint32_t reg_dp_gma_curve_65 : 8; /* [15: 8], r/w, 0x65 */ - uint32_t reg_dp_gma_curve_66 : 8; /* [23:16], r/w, 0x66 */ - uint32_t reg_dp_gma_curve_67 : 8; /* [31:24], r/w, 0x67 */ - } BF; - uint32_t WORD; - } disp_gma_curve_64; - - /* 0x268 : disp_gma_curve_68 */ - union { - struct { - uint32_t reg_dp_gma_curve_68 : 8; /* [ 7: 0], r/w, 0x68 */ - uint32_t reg_dp_gma_curve_69 : 8; /* [15: 8], r/w, 0x69 */ - uint32_t reg_dp_gma_curve_6a : 8; /* [23:16], r/w, 0x6a */ - uint32_t reg_dp_gma_curve_6b : 8; /* [31:24], r/w, 0x6b */ - } BF; - uint32_t WORD; - } disp_gma_curve_68; - - /* 0x26C : disp_gma_curve_6c */ - union { - struct { - uint32_t reg_dp_gma_curve_6c : 8; /* [ 7: 0], r/w, 0x6c */ - uint32_t reg_dp_gma_curve_6d : 8; /* [15: 8], r/w, 0x6d */ - uint32_t reg_dp_gma_curve_6e : 8; /* [23:16], r/w, 0x6e */ - uint32_t reg_dp_gma_curve_6f : 8; /* [31:24], r/w, 0x6f */ - } BF; - uint32_t WORD; - } disp_gma_curve_6c; - - /* 0x270 : disp_gma_curve_70 */ - union { - struct { - uint32_t reg_dp_gma_curve_70 : 8; /* [ 7: 0], r/w, 0x70 */ - uint32_t reg_dp_gma_curve_71 : 8; /* [15: 8], r/w, 0x71 */ - uint32_t reg_dp_gma_curve_72 : 8; /* [23:16], r/w, 0x72 */ - uint32_t reg_dp_gma_curve_73 : 8; /* [31:24], r/w, 0x73 */ - } BF; - uint32_t WORD; - } disp_gma_curve_70; - - /* 0x274 : disp_gma_curve_74 */ - union { - struct { - uint32_t reg_dp_gma_curve_74 : 8; /* [ 7: 0], r/w, 0x74 */ - uint32_t reg_dp_gma_curve_75 : 8; /* [15: 8], r/w, 0x75 */ - uint32_t reg_dp_gma_curve_76 : 8; /* [23:16], r/w, 0x76 */ - uint32_t reg_dp_gma_curve_77 : 8; /* [31:24], r/w, 0x77 */ - } BF; - uint32_t WORD; - } disp_gma_curve_74; - - /* 0x278 : disp_gma_curve_78 */ - union { - struct { - uint32_t reg_dp_gma_curve_78 : 8; /* [ 7: 0], r/w, 0x78 */ - uint32_t reg_dp_gma_curve_79 : 8; /* [15: 8], r/w, 0x79 */ - uint32_t reg_dp_gma_curve_7a : 8; /* [23:16], r/w, 0x7a */ - uint32_t reg_dp_gma_curve_7b : 8; /* [31:24], r/w, 0x7b */ - } BF; - uint32_t WORD; - } disp_gma_curve_78; - - /* 0x27C : disp_gma_curve_7c */ - union { - struct { - uint32_t reg_dp_gma_curve_7c : 8; /* [ 7: 0], r/w, 0x7c */ - uint32_t reg_dp_gma_curve_7d : 8; /* [15: 8], r/w, 0x7d */ - uint32_t reg_dp_gma_curve_7e : 8; /* [23:16], r/w, 0x7e */ - uint32_t reg_dp_gma_curve_7f : 8; /* [31:24], r/w, 0x7f */ - } BF; - uint32_t WORD; - } disp_gma_curve_7c; - - /* 0x280 : disp_gma_curve_80 */ - union { - struct { - uint32_t reg_dp_gma_curve_80 : 8; /* [ 7: 0], r/w, 0x80 */ - uint32_t reg_dp_gma_curve_81 : 8; /* [15: 8], r/w, 0x81 */ - uint32_t reg_dp_gma_curve_82 : 8; /* [23:16], r/w, 0x82 */ - uint32_t reg_dp_gma_curve_83 : 8; /* [31:24], r/w, 0x83 */ - } BF; - uint32_t WORD; - } disp_gma_curve_80; - - /* 0x284 : disp_gma_curve_84 */ - union { - struct { - uint32_t reg_dp_gma_curve_84 : 8; /* [ 7: 0], r/w, 0x84 */ - uint32_t reg_dp_gma_curve_85 : 8; /* [15: 8], r/w, 0x85 */ - uint32_t reg_dp_gma_curve_86 : 8; /* [23:16], r/w, 0x86 */ - uint32_t reg_dp_gma_curve_87 : 8; /* [31:24], r/w, 0x87 */ - } BF; - uint32_t WORD; - } disp_gma_curve_84; - - /* 0x288 : disp_gma_curve_88 */ - union { - struct { - uint32_t reg_dp_gma_curve_88 : 8; /* [ 7: 0], r/w, 0x88 */ - uint32_t reg_dp_gma_curve_89 : 8; /* [15: 8], r/w, 0x89 */ - uint32_t reg_dp_gma_curve_8a : 8; /* [23:16], r/w, 0x8a */ - uint32_t reg_dp_gma_curve_8b : 8; /* [31:24], r/w, 0x8b */ - } BF; - uint32_t WORD; - } disp_gma_curve_88; - - /* 0x28C : disp_gma_curve_8c */ - union { - struct { - uint32_t reg_dp_gma_curve_8c : 8; /* [ 7: 0], r/w, 0x8c */ - uint32_t reg_dp_gma_curve_8d : 8; /* [15: 8], r/w, 0x8d */ - uint32_t reg_dp_gma_curve_8e : 8; /* [23:16], r/w, 0x8e */ - uint32_t reg_dp_gma_curve_8f : 8; /* [31:24], r/w, 0x8f */ - } BF; - uint32_t WORD; - } disp_gma_curve_8c; - - /* 0x290 : disp_gma_curve_90 */ - union { - struct { - uint32_t reg_dp_gma_curve_90 : 8; /* [ 7: 0], r/w, 0x90 */ - uint32_t reg_dp_gma_curve_91 : 8; /* [15: 8], r/w, 0x91 */ - uint32_t reg_dp_gma_curve_92 : 8; /* [23:16], r/w, 0x92 */ - uint32_t reg_dp_gma_curve_93 : 8; /* [31:24], r/w, 0x93 */ - } BF; - uint32_t WORD; - } disp_gma_curve_90; - - /* 0x294 : disp_gma_curve_94 */ - union { - struct { - uint32_t reg_dp_gma_curve_94 : 8; /* [ 7: 0], r/w, 0x94 */ - uint32_t reg_dp_gma_curve_95 : 8; /* [15: 8], r/w, 0x95 */ - uint32_t reg_dp_gma_curve_96 : 8; /* [23:16], r/w, 0x96 */ - uint32_t reg_dp_gma_curve_97 : 8; /* [31:24], r/w, 0x97 */ - } BF; - uint32_t WORD; - } disp_gma_curve_94; - - /* 0x298 : disp_gma_curve_98 */ - union { - struct { - uint32_t reg_dp_gma_curve_98 : 8; /* [ 7: 0], r/w, 0x98 */ - uint32_t reg_dp_gma_curve_99 : 8; /* [15: 8], r/w, 0x99 */ - uint32_t reg_dp_gma_curve_9a : 8; /* [23:16], r/w, 0x9a */ - uint32_t reg_dp_gma_curve_9b : 8; /* [31:24], r/w, 0x9b */ - } BF; - uint32_t WORD; - } disp_gma_curve_98; - - /* 0x29C : disp_gma_curve_9c */ - union { - struct { - uint32_t reg_dp_gma_curve_9c : 8; /* [ 7: 0], r/w, 0x9c */ - uint32_t reg_dp_gma_curve_9d : 8; /* [15: 8], r/w, 0x9d */ - uint32_t reg_dp_gma_curve_9e : 8; /* [23:16], r/w, 0x9e */ - uint32_t reg_dp_gma_curve_9f : 8; /* [31:24], r/w, 0x9f */ - } BF; - uint32_t WORD; - } disp_gma_curve_9c; - - /* 0x2A0 : disp_gma_curve_a0 */ - union { - struct { - uint32_t reg_dp_gma_curve_a0 : 8; /* [ 7: 0], r/w, 0xa0 */ - uint32_t reg_dp_gma_curve_a1 : 8; /* [15: 8], r/w, 0xa1 */ - uint32_t reg_dp_gma_curve_a2 : 8; /* [23:16], r/w, 0xa2 */ - uint32_t reg_dp_gma_curve_a3 : 8; /* [31:24], r/w, 0xa3 */ - } BF; - uint32_t WORD; - } disp_gma_curve_a0; - - /* 0x2A4 : disp_gma_curve_a4 */ - union { - struct { - uint32_t reg_dp_gma_curve_a4 : 8; /* [ 7: 0], r/w, 0xa4 */ - uint32_t reg_dp_gma_curve_a5 : 8; /* [15: 8], r/w, 0xa5 */ - uint32_t reg_dp_gma_curve_a6 : 8; /* [23:16], r/w, 0xa6 */ - uint32_t reg_dp_gma_curve_a7 : 8; /* [31:24], r/w, 0xa7 */ - } BF; - uint32_t WORD; - } disp_gma_curve_a4; - - /* 0x2A8 : disp_gma_curve_a8 */ - union { - struct { - uint32_t reg_dp_gma_curve_a8 : 8; /* [ 7: 0], r/w, 0xa8 */ - uint32_t reg_dp_gma_curve_a9 : 8; /* [15: 8], r/w, 0xa9 */ - uint32_t reg_dp_gma_curve_aa : 8; /* [23:16], r/w, 0xaa */ - uint32_t reg_dp_gma_curve_ab : 8; /* [31:24], r/w, 0xab */ - } BF; - uint32_t WORD; - } disp_gma_curve_a8; - - /* 0x2AC : disp_gma_curve_ac */ - union { - struct { - uint32_t reg_dp_gma_curve_ac : 8; /* [ 7: 0], r/w, 0xac */ - uint32_t reg_dp_gma_curve_ad : 8; /* [15: 8], r/w, 0xad */ - uint32_t reg_dp_gma_curve_ae : 8; /* [23:16], r/w, 0xae */ - uint32_t reg_dp_gma_curve_af : 8; /* [31:24], r/w, 0xaf */ - } BF; - uint32_t WORD; - } disp_gma_curve_ac; - - /* 0x2B0 : disp_gma_curve_b0 */ - union { - struct { - uint32_t reg_dp_gma_curve_b0 : 8; /* [ 7: 0], r/w, 0xb0 */ - uint32_t reg_dp_gma_curve_b1 : 8; /* [15: 8], r/w, 0xb1 */ - uint32_t reg_dp_gma_curve_b2 : 8; /* [23:16], r/w, 0xb2 */ - uint32_t reg_dp_gma_curve_b3 : 8; /* [31:24], r/w, 0xb3 */ - } BF; - uint32_t WORD; - } disp_gma_curve_b0; - - /* 0x2B4 : disp_gma_curve_b4 */ - union { - struct { - uint32_t reg_dp_gma_curve_b4 : 8; /* [ 7: 0], r/w, 0xb4 */ - uint32_t reg_dp_gma_curve_b5 : 8; /* [15: 8], r/w, 0xb5 */ - uint32_t reg_dp_gma_curve_b6 : 8; /* [23:16], r/w, 0xb6 */ - uint32_t reg_dp_gma_curve_b7 : 8; /* [31:24], r/w, 0xb7 */ - } BF; - uint32_t WORD; - } disp_gma_curve_b4; - - /* 0x2B8 : disp_gma_curve_b8 */ - union { - struct { - uint32_t reg_dp_gma_curve_b8 : 8; /* [ 7: 0], r/w, 0xb8 */ - uint32_t reg_dp_gma_curve_b9 : 8; /* [15: 8], r/w, 0xb9 */ - uint32_t reg_dp_gma_curve_ba : 8; /* [23:16], r/w, 0xba */ - uint32_t reg_dp_gma_curve_bb : 8; /* [31:24], r/w, 0xbb */ - } BF; - uint32_t WORD; - } disp_gma_curve_b8; - - /* 0x2BC : disp_gma_curve_bc */ - union { - struct { - uint32_t reg_dp_gma_curve_bc : 8; /* [ 7: 0], r/w, 0xbc */ - uint32_t reg_dp_gma_curve_bd : 8; /* [15: 8], r/w, 0xbd */ - uint32_t reg_dp_gma_curve_be : 8; /* [23:16], r/w, 0xbe */ - uint32_t reg_dp_gma_curve_bf : 8; /* [31:24], r/w, 0xbf */ - } BF; - uint32_t WORD; - } disp_gma_curve_bc; - - /* 0x2C0 : disp_gma_curve_c0 */ - union { - struct { - uint32_t reg_dp_gma_curve_c0 : 8; /* [ 7: 0], r/w, 0xc0 */ - uint32_t reg_dp_gma_curve_c1 : 8; /* [15: 8], r/w, 0xc1 */ - uint32_t reg_dp_gma_curve_c2 : 8; /* [23:16], r/w, 0xc2 */ - uint32_t reg_dp_gma_curve_c3 : 8; /* [31:24], r/w, 0xc3 */ - } BF; - uint32_t WORD; - } disp_gma_curve_c0; - - /* 0x2C4 : disp_gma_curve_c4 */ - union { - struct { - uint32_t reg_dp_gma_curve_c4 : 8; /* [ 7: 0], r/w, 0xc4 */ - uint32_t reg_dp_gma_curve_c5 : 8; /* [15: 8], r/w, 0xc5 */ - uint32_t reg_dp_gma_curve_c6 : 8; /* [23:16], r/w, 0xc6 */ - uint32_t reg_dp_gma_curve_c7 : 8; /* [31:24], r/w, 0xc7 */ - } BF; - uint32_t WORD; - } disp_gma_curve_c4; - - /* 0x2C8 : disp_gma_curve_c8 */ - union { - struct { - uint32_t reg_dp_gma_curve_c8 : 8; /* [ 7: 0], r/w, 0xc8 */ - uint32_t reg_dp_gma_curve_c9 : 8; /* [15: 8], r/w, 0xc9 */ - uint32_t reg_dp_gma_curve_ca : 8; /* [23:16], r/w, 0xca */ - uint32_t reg_dp_gma_curve_cb : 8; /* [31:24], r/w, 0xcb */ - } BF; - uint32_t WORD; - } disp_gma_curve_c8; - - /* 0x2CC : disp_gma_curve_cc */ - union { - struct { - uint32_t reg_dp_gma_curve_cc : 8; /* [ 7: 0], r/w, 0xcc */ - uint32_t reg_dp_gma_curve_cd : 8; /* [15: 8], r/w, 0xcd */ - uint32_t reg_dp_gma_curve_ce : 8; /* [23:16], r/w, 0xce */ - uint32_t reg_dp_gma_curve_cf : 8; /* [31:24], r/w, 0xcf */ - } BF; - uint32_t WORD; - } disp_gma_curve_cc; - - /* 0x2D0 : disp_gma_curve_d0 */ - union { - struct { - uint32_t reg_dp_gma_curve_d0 : 8; /* [ 7: 0], r/w, 0xd0 */ - uint32_t reg_dp_gma_curve_d1 : 8; /* [15: 8], r/w, 0xd1 */ - uint32_t reg_dp_gma_curve_d2 : 8; /* [23:16], r/w, 0xd2 */ - uint32_t reg_dp_gma_curve_d3 : 8; /* [31:24], r/w, 0xd3 */ - } BF; - uint32_t WORD; - } disp_gma_curve_d0; - - /* 0x2D4 : disp_gma_curve_d4 */ - union { - struct { - uint32_t reg_dp_gma_curve_d4 : 8; /* [ 7: 0], r/w, 0xd4 */ - uint32_t reg_dp_gma_curve_d5 : 8; /* [15: 8], r/w, 0xd5 */ - uint32_t reg_dp_gma_curve_d6 : 8; /* [23:16], r/w, 0xd6 */ - uint32_t reg_dp_gma_curve_d7 : 8; /* [31:24], r/w, 0xd7 */ - } BF; - uint32_t WORD; - } disp_gma_curve_d4; - - /* 0x2D8 : disp_gma_curve_d8 */ - union { - struct { - uint32_t reg_dp_gma_curve_d8 : 8; /* [ 7: 0], r/w, 0xd8 */ - uint32_t reg_dp_gma_curve_d9 : 8; /* [15: 8], r/w, 0xd9 */ - uint32_t reg_dp_gma_curve_da : 8; /* [23:16], r/w, 0xda */ - uint32_t reg_dp_gma_curve_db : 8; /* [31:24], r/w, 0xdb */ - } BF; - uint32_t WORD; - } disp_gma_curve_d8; - - /* 0x2DC : disp_gma_curve_dc */ - union { - struct { - uint32_t reg_dp_gma_curve_dc : 8; /* [ 7: 0], r/w, 0xdc */ - uint32_t reg_dp_gma_curve_dd : 8; /* [15: 8], r/w, 0xdd */ - uint32_t reg_dp_gma_curve_de : 8; /* [23:16], r/w, 0xde */ - uint32_t reg_dp_gma_curve_df : 8; /* [31:24], r/w, 0xdf */ - } BF; - uint32_t WORD; - } disp_gma_curve_dc; - - /* 0x2E0 : disp_gma_curve_e0 */ - union { - struct { - uint32_t reg_dp_gma_curve_e0 : 8; /* [ 7: 0], r/w, 0xe0 */ - uint32_t reg_dp_gma_curve_e1 : 8; /* [15: 8], r/w, 0xe1 */ - uint32_t reg_dp_gma_curve_e2 : 8; /* [23:16], r/w, 0xe2 */ - uint32_t reg_dp_gma_curve_e3 : 8; /* [31:24], r/w, 0xe3 */ - } BF; - uint32_t WORD; - } disp_gma_curve_e0; - - /* 0x2E4 : disp_gma_curve_e4 */ - union { - struct { - uint32_t reg_dp_gma_curve_e4 : 8; /* [ 7: 0], r/w, 0xe4 */ - uint32_t reg_dp_gma_curve_e5 : 8; /* [15: 8], r/w, 0xe5 */ - uint32_t reg_dp_gma_curve_e6 : 8; /* [23:16], r/w, 0xe6 */ - uint32_t reg_dp_gma_curve_e7 : 8; /* [31:24], r/w, 0xe7 */ - } BF; - uint32_t WORD; - } disp_gma_curve_e4; - - /* 0x2E8 : disp_gma_curve_e8 */ - union { - struct { - uint32_t reg_dp_gma_curve_e8 : 8; /* [ 7: 0], r/w, 0xe8 */ - uint32_t reg_dp_gma_curve_e9 : 8; /* [15: 8], r/w, 0xe9 */ - uint32_t reg_dp_gma_curve_ea : 8; /* [23:16], r/w, 0xea */ - uint32_t reg_dp_gma_curve_eb : 8; /* [31:24], r/w, 0xeb */ - } BF; - uint32_t WORD; - } disp_gma_curve_e8; - - /* 0x2EC : disp_gma_curve_ec */ - union { - struct { - uint32_t reg_dp_gma_curve_ec : 8; /* [ 7: 0], r/w, 0xec */ - uint32_t reg_dp_gma_curve_ed : 8; /* [15: 8], r/w, 0xed */ - uint32_t reg_dp_gma_curve_ee : 8; /* [23:16], r/w, 0xee */ - uint32_t reg_dp_gma_curve_ef : 8; /* [31:24], r/w, 0xef */ - } BF; - uint32_t WORD; - } disp_gma_curve_ec; - - /* 0x2F0 : disp_gma_curve_f0 */ - union { - struct { - uint32_t reg_dp_gma_curve_f0 : 8; /* [ 7: 0], r/w, 0xf0 */ - uint32_t reg_dp_gma_curve_f1 : 8; /* [15: 8], r/w, 0xf1 */ - uint32_t reg_dp_gma_curve_f2 : 8; /* [23:16], r/w, 0xf2 */ - uint32_t reg_dp_gma_curve_f3 : 8; /* [31:24], r/w, 0xf3 */ - } BF; - uint32_t WORD; - } disp_gma_curve_f0; - - /* 0x2F4 : disp_gma_curve_f4 */ - union { - struct { - uint32_t reg_dp_gma_curve_f4 : 8; /* [ 7: 0], r/w, 0xf4 */ - uint32_t reg_dp_gma_curve_f5 : 8; /* [15: 8], r/w, 0xf5 */ - uint32_t reg_dp_gma_curve_f6 : 8; /* [23:16], r/w, 0xf6 */ - uint32_t reg_dp_gma_curve_f7 : 8; /* [31:24], r/w, 0xf7 */ - } BF; - uint32_t WORD; - } disp_gma_curve_f4; - - /* 0x2F8 : disp_gma_curve_f8 */ - union { - struct { - uint32_t reg_dp_gma_curve_f8 : 8; /* [ 7: 0], r/w, 0xf8 */ - uint32_t reg_dp_gma_curve_f9 : 8; /* [15: 8], r/w, 0xf9 */ - uint32_t reg_dp_gma_curve_fa : 8; /* [23:16], r/w, 0xfa */ - uint32_t reg_dp_gma_curve_fb : 8; /* [31:24], r/w, 0xfb */ - } BF; - uint32_t WORD; - } disp_gma_curve_f8; - - /* 0x2FC : disp_gma_curve_fc */ - union { - struct { - uint32_t reg_dp_gma_curve_fc : 8; /* [ 7: 0], r/w, 0xfc */ - uint32_t reg_dp_gma_curve_fd : 8; /* [15: 8], r/w, 0xfd */ - uint32_t reg_dp_gma_curve_fe : 8; /* [23:16], r/w, 0xfe */ - uint32_t reg_dp_gma_curve_ff : 8; /* [31:24], r/w, 0xff */ - } BF; - uint32_t WORD; - } disp_gma_curve_fc; -}; - -typedef volatile struct dsp2_misc_reg dsp2_misc_reg_t; - -#endif /* __DSP2_MISC_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_tg_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_tg_reg.h deleted file mode 100644 index 48584252ba..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_tg_reg.h +++ /dev/null @@ -1,423 +0,0 @@ -/** - ****************************************************************************** - * @file dsp2_tg_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __DSP2_TG_REG_H__ -#define __DSP2_TG_REG_H__ - -#include "bl808.h" - -/* 0x00 : ip_info */ -#define DSP2_TG_IP_INFO_OFFSET (0x00) -#define DSP2_TG_IP_ID_R DSP2_TG_IP_ID_R -#define DSP2_TG_IP_ID_R_POS (8U) -#define DSP2_TG_IP_ID_R_LEN (8U) -#define DSP2_TG_IP_ID_R_MSK (((1U << DSP2_TG_IP_ID_R_LEN) - 1) << DSP2_TG_IP_ID_R_POS) -#define DSP2_TG_IP_ID_R_UMSK (~(((1U << DSP2_TG_IP_ID_R_LEN) - 1) << DSP2_TG_IP_ID_R_POS)) -#define DSP2_TG_VERSION_R DSP2_TG_VERSION_R -#define DSP2_TG_VERSION_R_POS (16U) -#define DSP2_TG_VERSION_R_LEN (8U) -#define DSP2_TG_VERSION_R_MSK (((1U << DSP2_TG_VERSION_R_LEN) - 1) << DSP2_TG_VERSION_R_POS) -#define DSP2_TG_VERSION_R_UMSK (~(((1U << DSP2_TG_VERSION_R_LEN) - 1) << DSP2_TG_VERSION_R_POS)) - -/* 0x08 : dvp_mode */ -#define DSP2_TG_DVP_MODE_OFFSET (0x08) -#define DSP2_TG_FHBLK_LINE_ON_W DSP2_TG_FHBLK_LINE_ON_W -#define DSP2_TG_FHBLK_LINE_ON_W_POS (0U) -#define DSP2_TG_FHBLK_LINE_ON_W_LEN (1U) -#define DSP2_TG_FHBLK_LINE_ON_W_MSK (((1U << DSP2_TG_FHBLK_LINE_ON_W_LEN) - 1) << DSP2_TG_FHBLK_LINE_ON_W_POS) -#define DSP2_TG_FHBLK_LINE_ON_W_UMSK (~(((1U << DSP2_TG_FHBLK_LINE_ON_W_LEN) - 1) << DSP2_TG_FHBLK_LINE_ON_W_POS)) -#define DSP2_TG_HBLK_LINE_ON_W DSP2_TG_HBLK_LINE_ON_W -#define DSP2_TG_HBLK_LINE_ON_W_POS (1U) -#define DSP2_TG_HBLK_LINE_ON_W_LEN (1U) -#define DSP2_TG_HBLK_LINE_ON_W_MSK (((1U << DSP2_TG_HBLK_LINE_ON_W_LEN) - 1) << DSP2_TG_HBLK_LINE_ON_W_POS) -#define DSP2_TG_HBLK_LINE_ON_W_UMSK (~(((1U << DSP2_TG_HBLK_LINE_ON_W_LEN) - 1) << DSP2_TG_HBLK_LINE_ON_W_POS)) -#define DSP2_TG_VCNT_RST_MODE_W DSP2_TG_VCNT_RST_MODE_W -#define DSP2_TG_VCNT_RST_MODE_W_POS (16U) -#define DSP2_TG_VCNT_RST_MODE_W_LEN (1U) -#define DSP2_TG_VCNT_RST_MODE_W_MSK (((1U << DSP2_TG_VCNT_RST_MODE_W_LEN) - 1) << DSP2_TG_VCNT_RST_MODE_W_POS) -#define DSP2_TG_VCNT_RST_MODE_W_UMSK (~(((1U << DSP2_TG_VCNT_RST_MODE_W_LEN) - 1) << DSP2_TG_VCNT_RST_MODE_W_POS)) -#define DSP2_TG_HCNT_RST_MODE_W DSP2_TG_HCNT_RST_MODE_W -#define DSP2_TG_HCNT_RST_MODE_W_POS (17U) -#define DSP2_TG_HCNT_RST_MODE_W_LEN (1U) -#define DSP2_TG_HCNT_RST_MODE_W_MSK (((1U << DSP2_TG_HCNT_RST_MODE_W_LEN) - 1) << DSP2_TG_HCNT_RST_MODE_W_POS) -#define DSP2_TG_HCNT_RST_MODE_W_UMSK (~(((1U << DSP2_TG_HCNT_RST_MODE_W_LEN) - 1) << DSP2_TG_HCNT_RST_MODE_W_POS)) -#define DSP2_TG_VSYNC_IN_INV_W DSP2_TG_VSYNC_IN_INV_W -#define DSP2_TG_VSYNC_IN_INV_W_POS (18U) -#define DSP2_TG_VSYNC_IN_INV_W_LEN (1U) -#define DSP2_TG_VSYNC_IN_INV_W_MSK (((1U << DSP2_TG_VSYNC_IN_INV_W_LEN) - 1) << DSP2_TG_VSYNC_IN_INV_W_POS) -#define DSP2_TG_VSYNC_IN_INV_W_UMSK (~(((1U << DSP2_TG_VSYNC_IN_INV_W_LEN) - 1) << DSP2_TG_VSYNC_IN_INV_W_POS)) -#define DSP2_TG_HSYNC_IN_INV_W DSP2_TG_HSYNC_IN_INV_W -#define DSP2_TG_HSYNC_IN_INV_W_POS (19U) -#define DSP2_TG_HSYNC_IN_INV_W_LEN (1U) -#define DSP2_TG_HSYNC_IN_INV_W_MSK (((1U << DSP2_TG_HSYNC_IN_INV_W_LEN) - 1) << DSP2_TG_HSYNC_IN_INV_W_POS) -#define DSP2_TG_HSYNC_IN_INV_W_UMSK (~(((1U << DSP2_TG_HSYNC_IN_INV_W_LEN) - 1) << DSP2_TG_HSYNC_IN_INV_W_POS)) -#define DSP2_TG_SYNC_MODE_W DSP2_TG_SYNC_MODE_W -#define DSP2_TG_SYNC_MODE_W_POS (20U) -#define DSP2_TG_SYNC_MODE_W_LEN (2U) -#define DSP2_TG_SYNC_MODE_W_MSK (((1U << DSP2_TG_SYNC_MODE_W_LEN) - 1) << DSP2_TG_SYNC_MODE_W_POS) -#define DSP2_TG_SYNC_MODE_W_UMSK (~(((1U << DSP2_TG_SYNC_MODE_W_LEN) - 1) << DSP2_TG_SYNC_MODE_W_POS)) -#define DSP2_TG_REG_ACT_VSYNC_RST_EN_W DSP2_TG_REG_ACT_VSYNC_RST_EN_W -#define DSP2_TG_REG_ACT_VSYNC_RST_EN_W_POS (24U) -#define DSP2_TG_REG_ACT_VSYNC_RST_EN_W_LEN (1U) -#define DSP2_TG_REG_ACT_VSYNC_RST_EN_W_MSK (((1U << DSP2_TG_REG_ACT_VSYNC_RST_EN_W_LEN) - 1) << DSP2_TG_REG_ACT_VSYNC_RST_EN_W_POS) -#define DSP2_TG_REG_ACT_VSYNC_RST_EN_W_UMSK (~(((1U << DSP2_TG_REG_ACT_VSYNC_RST_EN_W_LEN) - 1) << DSP2_TG_REG_ACT_VSYNC_RST_EN_W_POS)) - -/* 0x0C : total_pixels */ -#define DSP2_TG_TOTAL_PIXELS_OFFSET (0x0C) -#define DSP2_TG_TOTAL_HPIXELS_W DSP2_TG_TOTAL_HPIXELS_W -#define DSP2_TG_TOTAL_HPIXELS_W_POS (0U) -#define DSP2_TG_TOTAL_HPIXELS_W_LEN (16U) -#define DSP2_TG_TOTAL_HPIXELS_W_MSK (((1U << DSP2_TG_TOTAL_HPIXELS_W_LEN) - 1) << DSP2_TG_TOTAL_HPIXELS_W_POS) -#define DSP2_TG_TOTAL_HPIXELS_W_UMSK (~(((1U << DSP2_TG_TOTAL_HPIXELS_W_LEN) - 1) << DSP2_TG_TOTAL_HPIXELS_W_POS)) -#define DSP2_TG_TOTAL_VLINES_W DSP2_TG_TOTAL_VLINES_W -#define DSP2_TG_TOTAL_VLINES_W_POS (16U) -#define DSP2_TG_TOTAL_VLINES_W_LEN (16U) -#define DSP2_TG_TOTAL_VLINES_W_MSK (((1U << DSP2_TG_TOTAL_VLINES_W_LEN) - 1) << DSP2_TG_TOTAL_VLINES_W_POS) -#define DSP2_TG_TOTAL_VLINES_W_UMSK (~(((1U << DSP2_TG_TOTAL_VLINES_W_LEN) - 1) << DSP2_TG_TOTAL_VLINES_W_POS)) - -/* 0x10 : act_pixels_1 */ -#define DSP2_TG_ACT_PIXELS_1_OFFSET (0x10) -#define DSP2_TG_ACT_START_PIXEL_W DSP2_TG_ACT_START_PIXEL_W -#define DSP2_TG_ACT_START_PIXEL_W_POS (0U) -#define DSP2_TG_ACT_START_PIXEL_W_LEN (16U) -#define DSP2_TG_ACT_START_PIXEL_W_MSK (((1U << DSP2_TG_ACT_START_PIXEL_W_LEN) - 1) << DSP2_TG_ACT_START_PIXEL_W_POS) -#define DSP2_TG_ACT_START_PIXEL_W_UMSK (~(((1U << DSP2_TG_ACT_START_PIXEL_W_LEN) - 1) << DSP2_TG_ACT_START_PIXEL_W_POS)) -#define DSP2_TG_ACT_PIXEL_WIDTH_W DSP2_TG_ACT_PIXEL_WIDTH_W -#define DSP2_TG_ACT_PIXEL_WIDTH_W_POS (16U) -#define DSP2_TG_ACT_PIXEL_WIDTH_W_LEN (16U) -#define DSP2_TG_ACT_PIXEL_WIDTH_W_MSK (((1U << DSP2_TG_ACT_PIXEL_WIDTH_W_LEN) - 1) << DSP2_TG_ACT_PIXEL_WIDTH_W_POS) -#define DSP2_TG_ACT_PIXEL_WIDTH_W_UMSK (~(((1U << DSP2_TG_ACT_PIXEL_WIDTH_W_LEN) - 1) << DSP2_TG_ACT_PIXEL_WIDTH_W_POS)) - -/* 0x14 : act_pixels_2 */ -#define DSP2_TG_ACT_PIXELS_2_OFFSET (0x14) -#define DSP2_TG_ACT_START_LINE_W DSP2_TG_ACT_START_LINE_W -#define DSP2_TG_ACT_START_LINE_W_POS (0U) -#define DSP2_TG_ACT_START_LINE_W_LEN (16U) -#define DSP2_TG_ACT_START_LINE_W_MSK (((1U << DSP2_TG_ACT_START_LINE_W_LEN) - 1) << DSP2_TG_ACT_START_LINE_W_POS) -#define DSP2_TG_ACT_START_LINE_W_UMSK (~(((1U << DSP2_TG_ACT_START_LINE_W_LEN) - 1) << DSP2_TG_ACT_START_LINE_W_POS)) -#define DSP2_TG_ACT_LINE_HEIGHT_W DSP2_TG_ACT_LINE_HEIGHT_W -#define DSP2_TG_ACT_LINE_HEIGHT_W_POS (16U) -#define DSP2_TG_ACT_LINE_HEIGHT_W_LEN (16U) -#define DSP2_TG_ACT_LINE_HEIGHT_W_MSK (((1U << DSP2_TG_ACT_LINE_HEIGHT_W_LEN) - 1) << DSP2_TG_ACT_LINE_HEIGHT_W_POS) -#define DSP2_TG_ACT_LINE_HEIGHT_W_UMSK (~(((1U << DSP2_TG_ACT_LINE_HEIGHT_W_LEN) - 1) << DSP2_TG_ACT_LINE_HEIGHT_W_POS)) - -/* 0x18 : fact_pixels_1 */ -#define DSP2_TG_FACT_PIXELS_1_OFFSET (0x18) -#define DSP2_TG_FACT_START_PIXEL_W DSP2_TG_FACT_START_PIXEL_W -#define DSP2_TG_FACT_START_PIXEL_W_POS (0U) -#define DSP2_TG_FACT_START_PIXEL_W_LEN (16U) -#define DSP2_TG_FACT_START_PIXEL_W_MSK (((1U << DSP2_TG_FACT_START_PIXEL_W_LEN) - 1) << DSP2_TG_FACT_START_PIXEL_W_POS) -#define DSP2_TG_FACT_START_PIXEL_W_UMSK (~(((1U << DSP2_TG_FACT_START_PIXEL_W_LEN) - 1) << DSP2_TG_FACT_START_PIXEL_W_POS)) -#define DSP2_TG_FACT_PIXEL_WIDTH_W DSP2_TG_FACT_PIXEL_WIDTH_W -#define DSP2_TG_FACT_PIXEL_WIDTH_W_POS (16U) -#define DSP2_TG_FACT_PIXEL_WIDTH_W_LEN (16U) -#define DSP2_TG_FACT_PIXEL_WIDTH_W_MSK (((1U << DSP2_TG_FACT_PIXEL_WIDTH_W_LEN) - 1) << DSP2_TG_FACT_PIXEL_WIDTH_W_POS) -#define DSP2_TG_FACT_PIXEL_WIDTH_W_UMSK (~(((1U << DSP2_TG_FACT_PIXEL_WIDTH_W_LEN) - 1) << DSP2_TG_FACT_PIXEL_WIDTH_W_POS)) - -/* 0x1C : fact_pixels_2 */ -#define DSP2_TG_FACT_PIXELS_2_OFFSET (0x1C) -#define DSP2_TG_FACT_START_LINE_W DSP2_TG_FACT_START_LINE_W -#define DSP2_TG_FACT_START_LINE_W_POS (0U) -#define DSP2_TG_FACT_START_LINE_W_LEN (16U) -#define DSP2_TG_FACT_START_LINE_W_MSK (((1U << DSP2_TG_FACT_START_LINE_W_LEN) - 1) << DSP2_TG_FACT_START_LINE_W_POS) -#define DSP2_TG_FACT_START_LINE_W_UMSK (~(((1U << DSP2_TG_FACT_START_LINE_W_LEN) - 1) << DSP2_TG_FACT_START_LINE_W_POS)) -#define DSP2_TG_FACT_LINE_HEIGHT_W DSP2_TG_FACT_LINE_HEIGHT_W -#define DSP2_TG_FACT_LINE_HEIGHT_W_POS (16U) -#define DSP2_TG_FACT_LINE_HEIGHT_W_LEN (16U) -#define DSP2_TG_FACT_LINE_HEIGHT_W_MSK (((1U << DSP2_TG_FACT_LINE_HEIGHT_W_LEN) - 1) << DSP2_TG_FACT_LINE_HEIGHT_W_POS) -#define DSP2_TG_FACT_LINE_HEIGHT_W_UMSK (~(((1U << DSP2_TG_FACT_LINE_HEIGHT_W_LEN) - 1) << DSP2_TG_FACT_LINE_HEIGHT_W_POS)) - -/* 0x20 : hsync_pixel */ -#define DSP2_TG_HSYNC_PIXEL_OFFSET (0x20) -#define DSP2_TG_HSYNC_START_PIXEL_W DSP2_TG_HSYNC_START_PIXEL_W -#define DSP2_TG_HSYNC_START_PIXEL_W_POS (0U) -#define DSP2_TG_HSYNC_START_PIXEL_W_LEN (16U) -#define DSP2_TG_HSYNC_START_PIXEL_W_MSK (((1U << DSP2_TG_HSYNC_START_PIXEL_W_LEN) - 1) << DSP2_TG_HSYNC_START_PIXEL_W_POS) -#define DSP2_TG_HSYNC_START_PIXEL_W_UMSK (~(((1U << DSP2_TG_HSYNC_START_PIXEL_W_LEN) - 1) << DSP2_TG_HSYNC_START_PIXEL_W_POS)) -#define DSP2_TG_HSYNC_PIXEL_WIDTH_W DSP2_TG_HSYNC_PIXEL_WIDTH_W -#define DSP2_TG_HSYNC_PIXEL_WIDTH_W_POS (16U) -#define DSP2_TG_HSYNC_PIXEL_WIDTH_W_LEN (16U) -#define DSP2_TG_HSYNC_PIXEL_WIDTH_W_MSK (((1U << DSP2_TG_HSYNC_PIXEL_WIDTH_W_LEN) - 1) << DSP2_TG_HSYNC_PIXEL_WIDTH_W_POS) -#define DSP2_TG_HSYNC_PIXEL_WIDTH_W_UMSK (~(((1U << DSP2_TG_HSYNC_PIXEL_WIDTH_W_LEN) - 1) << DSP2_TG_HSYNC_PIXEL_WIDTH_W_POS)) - -/* 0x24 : hsync_line */ -#define DSP2_TG_HSYNC_LINE_OFFSET (0x24) -#define DSP2_TG_HSYNC_START_LINE_W DSP2_TG_HSYNC_START_LINE_W -#define DSP2_TG_HSYNC_START_LINE_W_POS (0U) -#define DSP2_TG_HSYNC_START_LINE_W_LEN (16U) -#define DSP2_TG_HSYNC_START_LINE_W_MSK (((1U << DSP2_TG_HSYNC_START_LINE_W_LEN) - 1) << DSP2_TG_HSYNC_START_LINE_W_POS) -#define DSP2_TG_HSYNC_START_LINE_W_UMSK (~(((1U << DSP2_TG_HSYNC_START_LINE_W_LEN) - 1) << DSP2_TG_HSYNC_START_LINE_W_POS)) -#define DSP2_TG_HSYNC_LINE_HEIGHT_W DSP2_TG_HSYNC_LINE_HEIGHT_W -#define DSP2_TG_HSYNC_LINE_HEIGHT_W_POS (16U) -#define DSP2_TG_HSYNC_LINE_HEIGHT_W_LEN (16U) -#define DSP2_TG_HSYNC_LINE_HEIGHT_W_MSK (((1U << DSP2_TG_HSYNC_LINE_HEIGHT_W_LEN) - 1) << DSP2_TG_HSYNC_LINE_HEIGHT_W_POS) -#define DSP2_TG_HSYNC_LINE_HEIGHT_W_UMSK (~(((1U << DSP2_TG_HSYNC_LINE_HEIGHT_W_LEN) - 1) << DSP2_TG_HSYNC_LINE_HEIGHT_W_POS)) - -/* 0x28 : vsync_line */ -#define DSP2_TG_VSYNC_LINE_OFFSET (0x28) -#define DSP2_TG_VSYNC_START_LINE_W DSP2_TG_VSYNC_START_LINE_W -#define DSP2_TG_VSYNC_START_LINE_W_POS (0U) -#define DSP2_TG_VSYNC_START_LINE_W_LEN (16U) -#define DSP2_TG_VSYNC_START_LINE_W_MSK (((1U << DSP2_TG_VSYNC_START_LINE_W_LEN) - 1) << DSP2_TG_VSYNC_START_LINE_W_POS) -#define DSP2_TG_VSYNC_START_LINE_W_UMSK (~(((1U << DSP2_TG_VSYNC_START_LINE_W_LEN) - 1) << DSP2_TG_VSYNC_START_LINE_W_POS)) -#define DSP2_TG_VSYNC_LINE_HEIGHT_W DSP2_TG_VSYNC_LINE_HEIGHT_W -#define DSP2_TG_VSYNC_LINE_HEIGHT_W_POS (16U) -#define DSP2_TG_VSYNC_LINE_HEIGHT_W_LEN (16U) -#define DSP2_TG_VSYNC_LINE_HEIGHT_W_MSK (((1U << DSP2_TG_VSYNC_LINE_HEIGHT_W_LEN) - 1) << DSP2_TG_VSYNC_LINE_HEIGHT_W_POS) -#define DSP2_TG_VSYNC_LINE_HEIGHT_W_UMSK (~(((1U << DSP2_TG_VSYNC_LINE_HEIGHT_W_LEN) - 1) << DSP2_TG_VSYNC_LINE_HEIGHT_W_POS)) - -/* 0x2C : vsync_pixel */ -#define DSP2_TG_VSYNC_PIXEL_OFFSET (0x2C) -#define DSP2_TG_VSYNC_START_PIXEL_W DSP2_TG_VSYNC_START_PIXEL_W -#define DSP2_TG_VSYNC_START_PIXEL_W_POS (0U) -#define DSP2_TG_VSYNC_START_PIXEL_W_LEN (16U) -#define DSP2_TG_VSYNC_START_PIXEL_W_MSK (((1U << DSP2_TG_VSYNC_START_PIXEL_W_LEN) - 1) << DSP2_TG_VSYNC_START_PIXEL_W_POS) -#define DSP2_TG_VSYNC_START_PIXEL_W_UMSK (~(((1U << DSP2_TG_VSYNC_START_PIXEL_W_LEN) - 1) << DSP2_TG_VSYNC_START_PIXEL_W_POS)) -#define DSP2_TG_VSYNC_END_PIXEL_W DSP2_TG_VSYNC_END_PIXEL_W -#define DSP2_TG_VSYNC_END_PIXEL_W_POS (16U) -#define DSP2_TG_VSYNC_END_PIXEL_W_LEN (16U) -#define DSP2_TG_VSYNC_END_PIXEL_W_MSK (((1U << DSP2_TG_VSYNC_END_PIXEL_W_LEN) - 1) << DSP2_TG_VSYNC_END_PIXEL_W_POS) -#define DSP2_TG_VSYNC_END_PIXEL_W_UMSK (~(((1U << DSP2_TG_VSYNC_END_PIXEL_W_LEN) - 1) << DSP2_TG_VSYNC_END_PIXEL_W_POS)) - -/* 0x30 : sync_out_inv */ -#define DSP2_TG_SYNC_OUT_INV_OFFSET (0x30) -#define DSP2_TG_VSYNC_OUT_INV_W DSP2_TG_VSYNC_OUT_INV_W -#define DSP2_TG_VSYNC_OUT_INV_W_POS (10U) -#define DSP2_TG_VSYNC_OUT_INV_W_LEN (1U) -#define DSP2_TG_VSYNC_OUT_INV_W_MSK (((1U << DSP2_TG_VSYNC_OUT_INV_W_LEN) - 1) << DSP2_TG_VSYNC_OUT_INV_W_POS) -#define DSP2_TG_VSYNC_OUT_INV_W_UMSK (~(((1U << DSP2_TG_VSYNC_OUT_INV_W_LEN) - 1) << DSP2_TG_VSYNC_OUT_INV_W_POS)) -#define DSP2_TG_HSYNC_OUT_INV_W DSP2_TG_HSYNC_OUT_INV_W -#define DSP2_TG_HSYNC_OUT_INV_W_POS (11U) -#define DSP2_TG_HSYNC_OUT_INV_W_LEN (1U) -#define DSP2_TG_HSYNC_OUT_INV_W_MSK (((1U << DSP2_TG_HSYNC_OUT_INV_W_LEN) - 1) << DSP2_TG_HSYNC_OUT_INV_W_POS) -#define DSP2_TG_HSYNC_OUT_INV_W_UMSK (~(((1U << DSP2_TG_HSYNC_OUT_INV_W_LEN) - 1) << DSP2_TG_HSYNC_OUT_INV_W_POS)) - -/* 0x34 : hvcount_ctrl */ -#define DSP2_TG_HVCOUNT_CTRL_OFFSET (0x34) -#define DSP2_TG_AUTO_HVSYNC_GEN_W DSP2_TG_AUTO_HVSYNC_GEN_W -#define DSP2_TG_AUTO_HVSYNC_GEN_W_POS (0U) -#define DSP2_TG_AUTO_HVSYNC_GEN_W_LEN (1U) -#define DSP2_TG_AUTO_HVSYNC_GEN_W_MSK (((1U << DSP2_TG_AUTO_HVSYNC_GEN_W_LEN) - 1) << DSP2_TG_AUTO_HVSYNC_GEN_W_POS) -#define DSP2_TG_AUTO_HVSYNC_GEN_W_UMSK (~(((1U << DSP2_TG_AUTO_HVSYNC_GEN_W_LEN) - 1) << DSP2_TG_AUTO_HVSYNC_GEN_W_POS)) -#define DSP2_TG_RSHP_VSYNC_INV_W DSP2_TG_RSHP_VSYNC_INV_W -#define DSP2_TG_RSHP_VSYNC_INV_W_POS (1U) -#define DSP2_TG_RSHP_VSYNC_INV_W_LEN (1U) -#define DSP2_TG_RSHP_VSYNC_INV_W_MSK (((1U << DSP2_TG_RSHP_VSYNC_INV_W_LEN) - 1) << DSP2_TG_RSHP_VSYNC_INV_W_POS) -#define DSP2_TG_RSHP_VSYNC_INV_W_UMSK (~(((1U << DSP2_TG_RSHP_VSYNC_INV_W_LEN) - 1) << DSP2_TG_RSHP_VSYNC_INV_W_POS)) -#define DSP2_TG_RSHP_HSYNC_INV_W DSP2_TG_RSHP_HSYNC_INV_W -#define DSP2_TG_RSHP_HSYNC_INV_W_POS (2U) -#define DSP2_TG_RSHP_HSYNC_INV_W_LEN (1U) -#define DSP2_TG_RSHP_HSYNC_INV_W_MSK (((1U << DSP2_TG_RSHP_HSYNC_INV_W_LEN) - 1) << DSP2_TG_RSHP_HSYNC_INV_W_POS) -#define DSP2_TG_RSHP_HSYNC_INV_W_UMSK (~(((1U << DSP2_TG_RSHP_HSYNC_INV_W_LEN) - 1) << DSP2_TG_RSHP_HSYNC_INV_W_POS)) -#define DSP2_TG_TG_CTRL_START_W DSP2_TG_TG_CTRL_START_W -#define DSP2_TG_TG_CTRL_START_W_POS (3U) -#define DSP2_TG_TG_CTRL_START_W_LEN (1U) -#define DSP2_TG_TG_CTRL_START_W_MSK (((1U << DSP2_TG_TG_CTRL_START_W_LEN) - 1) << DSP2_TG_TG_CTRL_START_W_POS) -#define DSP2_TG_TG_CTRL_START_W_UMSK (~(((1U << DSP2_TG_TG_CTRL_START_W_LEN) - 1) << DSP2_TG_TG_CTRL_START_W_POS)) -#define DSP2_TG_AUTO_OHVSYNC_GEN_W DSP2_TG_AUTO_OHVSYNC_GEN_W -#define DSP2_TG_AUTO_OHVSYNC_GEN_W_POS (4U) -#define DSP2_TG_AUTO_OHVSYNC_GEN_W_LEN (1U) -#define DSP2_TG_AUTO_OHVSYNC_GEN_W_MSK (((1U << DSP2_TG_AUTO_OHVSYNC_GEN_W_LEN) - 1) << DSP2_TG_AUTO_OHVSYNC_GEN_W_POS) -#define DSP2_TG_AUTO_OHVSYNC_GEN_W_UMSK (~(((1U << DSP2_TG_AUTO_OHVSYNC_GEN_W_LEN) - 1) << DSP2_TG_AUTO_OHVSYNC_GEN_W_POS)) -#define DSP2_TG_TG_CTRL_OSTART_W DSP2_TG_TG_CTRL_OSTART_W -#define DSP2_TG_TG_CTRL_OSTART_W_POS (7U) -#define DSP2_TG_TG_CTRL_OSTART_W_LEN (1U) -#define DSP2_TG_TG_CTRL_OSTART_W_MSK (((1U << DSP2_TG_TG_CTRL_OSTART_W_LEN) - 1) << DSP2_TG_TG_CTRL_OSTART_W_POS) -#define DSP2_TG_TG_CTRL_OSTART_W_UMSK (~(((1U << DSP2_TG_TG_CTRL_OSTART_W_LEN) - 1) << DSP2_TG_TG_CTRL_OSTART_W_POS)) - -/* 0xFC : dsp2_apb_ctrl */ -#define DSP2_TG_DSP2_APB_CTRL_OFFSET (0xFC) -#define DSP2_TG_RG_PCLK_FORCE_ON_W DSP2_TG_RG_PCLK_FORCE_ON_W -#define DSP2_TG_RG_PCLK_FORCE_ON_W_POS (0U) -#define DSP2_TG_RG_PCLK_FORCE_ON_W_LEN (16U) -#define DSP2_TG_RG_PCLK_FORCE_ON_W_MSK (((1U << DSP2_TG_RG_PCLK_FORCE_ON_W_LEN) - 1) << DSP2_TG_RG_PCLK_FORCE_ON_W_POS) -#define DSP2_TG_RG_PCLK_FORCE_ON_W_UMSK (~(((1U << DSP2_TG_RG_PCLK_FORCE_ON_W_LEN) - 1) << DSP2_TG_RG_PCLK_FORCE_ON_W_POS)) - -struct dsp2_tg_reg { - /* 0x00 : ip_info */ - union { - struct { - uint32_t reserved_0_7 : 8; /* [ 7: 0], rsvd, 0x0 */ - uint32_t IP_ID_r : 8; /* [15: 8], r, 0x13 */ - uint32_t Version_r : 8; /* [23:16], r, 0x28 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } ip_info; - - /* 0x4 reserved */ - uint8_t RESERVED0x4[4]; - - /* 0x08 : dvp_mode */ - union { - struct { - uint32_t fhblk_line_on_w : 1; /* [ 0], r/w, 0x0 */ - uint32_t hblk_line_on_w : 1; /* [ 1], r/w, 0x0 */ - uint32_t reserved_2_15 : 14; /* [15: 2], rsvd, 0x0 */ - uint32_t vcnt_rst_mode_w : 1; /* [ 16], r/w, 0x1 */ - uint32_t hcnt_rst_mode_w : 1; /* [ 17], r/w, 0x1 */ - uint32_t vsync_in_inv_w : 1; /* [ 18], r/w, 0x0 */ - uint32_t hsync_in_inv_w : 1; /* [ 19], r/w, 0x0 */ - uint32_t sync_mode_w : 2; /* [21:20], r/w, 0x0 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t reg_act_vsync_rst_en_w : 1; /* [ 24], r/w, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dvp_mode; - - /* 0x0C : total_pixels */ - union { - struct { - uint32_t total_hpixels_w : 16; /* [15: 0], r/w, 0xb0c */ - uint32_t total_vlines_w : 16; /* [31:16], r/w, 0x45a */ - } BF; - uint32_t WORD; - } total_pixels; - - /* 0x10 : act_pixels_1 */ - union { - struct { - uint32_t act_start_pixel_w : 16; /* [15: 0], r/w, 0x384 */ - uint32_t act_pixel_width_w : 16; /* [31:16], r/w, 0x5dc */ - } BF; - uint32_t WORD; - } act_pixels_1; - - /* 0x14 : act_pixels_2 */ - union { - struct { - uint32_t act_start_line_w : 16; /* [15: 0], r/w, 0x1a */ - uint32_t act_line_height_w : 16; /* [31:16], r/w, 0x440 */ - } BF; - uint32_t WORD; - } act_pixels_2; - - /* 0x18 : fact_pixels_1 */ - union { - struct { - uint32_t fact_start_pixel_w : 16; /* [15: 0], r/w, 0x43c */ - uint32_t fact_pixel_width_w : 16; /* [31:16], r/w, 0x780 */ - } BF; - uint32_t WORD; - } fact_pixels_1; - - /* 0x1C : fact_pixels_2 */ - union { - struct { - uint32_t fact_start_line_w : 16; /* [15: 0], r/w, 0x438 */ - uint32_t fact_line_height_w : 16; /* [31:16], r/w, 0x26 */ - } BF; - uint32_t WORD; - } fact_pixels_2; - - /* 0x20 : hsync_pixel */ - union { - struct { - uint32_t hsync_start_pixel_w : 16; /* [15: 0], r/w, 0x0 */ - uint32_t hsync_pixel_width_w : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } hsync_pixel; - - /* 0x24 : hsync_line */ - union { - struct { - uint32_t hsync_start_line_w : 16; /* [15: 0], r/w, 0x0 */ - uint32_t hsync_line_height_w : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } hsync_line; - - /* 0x28 : vsync_line */ - union { - struct { - uint32_t vsync_start_line_w : 16; /* [15: 0], r/w, 0x0 */ - uint32_t vsync_line_height_w : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } vsync_line; - - /* 0x2C : vsync_pixel */ - union { - struct { - uint32_t vsync_start_pixel_w : 16; /* [15: 0], r/w, 0x0 */ - uint32_t vsync_end_pixel_w : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } vsync_pixel; - - /* 0x30 : sync_out_inv */ - union { - struct { - uint32_t reserved_0_9 : 10; /* [ 9: 0], rsvd, 0x0 */ - uint32_t vsync_out_inv_w : 1; /* [ 10], r/w, 0x0 */ - uint32_t hsync_out_inv_w : 1; /* [ 11], r/w, 0x0 */ - uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } sync_out_inv; - - /* 0x34 : hvcount_ctrl */ - union { - struct { - uint32_t auto_hvsync_gen_w : 1; /* [ 0], r/w, 0x0 */ - uint32_t rshp_vsync_inv_w : 1; /* [ 1], r/w, 0x0 */ - uint32_t rshp_hsync_inv_w : 1; /* [ 2], r/w, 0x0 */ - uint32_t tg_ctrl_start_w : 1; /* [ 3], w1p, 0x0 */ - uint32_t auto_ohvsync_gen_w : 1; /* [ 4], r/w, 0x0 */ - uint32_t reserved_5_6 : 2; /* [ 6: 5], rsvd, 0x0 */ - uint32_t tg_ctrl_ostart_w : 1; /* [ 7], w1p, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } hvcount_ctrl; - - /* 0x38 reserved */ - uint8_t RESERVED0x38[196]; - - /* 0xFC : dsp2_apb_ctrl */ - union { - struct { - uint32_t rg_pclk_force_on_w : 16; /* [15: 0], r/w, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dsp2_apb_ctrl; -}; - -typedef volatile struct dsp2_tg_reg dsp2_tg_reg_t; - -#endif /* __DSP2_TG_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dtsrc_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dtsrc_reg.h deleted file mode 100644 index 879e0ebbe8..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dtsrc_reg.h +++ /dev/null @@ -1,505 +0,0 @@ -/** - ****************************************************************************** - * @file dtsrc_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __DTSRC_REG_H__ -#define __DTSRC_REG_H__ - -#include "bl808.h" - -/* 0x0 : config */ -#define DTSRC_CONFIG_OFFSET (0x0) -#define DTSRC_CR_ENABLE DTSRC_CR_ENABLE -#define DTSRC_CR_ENABLE_POS (0U) -#define DTSRC_CR_ENABLE_LEN (1U) -#define DTSRC_CR_ENABLE_MSK (((1U << DTSRC_CR_ENABLE_LEN) - 1) << DTSRC_CR_ENABLE_POS) -#define DTSRC_CR_ENABLE_UMSK (~(((1U << DTSRC_CR_ENABLE_LEN) - 1) << DTSRC_CR_ENABLE_POS)) -#define DTSRC_CR_AXI_EN DTSRC_CR_AXI_EN -#define DTSRC_CR_AXI_EN_POS (1U) -#define DTSRC_CR_AXI_EN_LEN (1U) -#define DTSRC_CR_AXI_EN_MSK (((1U << DTSRC_CR_AXI_EN_LEN) - 1) << DTSRC_CR_AXI_EN_POS) -#define DTSRC_CR_AXI_EN_UMSK (~(((1U << DTSRC_CR_AXI_EN_LEN) - 1) << DTSRC_CR_AXI_EN_POS)) -#define DTSRC_CR_MODE_CEA_861 DTSRC_CR_MODE_CEA_861 -#define DTSRC_CR_MODE_CEA_861_POS (2U) -#define DTSRC_CR_MODE_CEA_861_LEN (1U) -#define DTSRC_CR_MODE_CEA_861_MSK (((1U << DTSRC_CR_MODE_CEA_861_LEN) - 1) << DTSRC_CR_MODE_CEA_861_POS) -#define DTSRC_CR_MODE_CEA_861_UMSK (~(((1U << DTSRC_CR_MODE_CEA_861_LEN) - 1) << DTSRC_CR_MODE_CEA_861_POS)) -#define DTSRC_CR_SNSR_EN DTSRC_CR_SNSR_EN -#define DTSRC_CR_SNSR_EN_POS (3U) -#define DTSRC_CR_SNSR_EN_LEN (1U) -#define DTSRC_CR_SNSR_EN_MSK (((1U << DTSRC_CR_SNSR_EN_LEN) - 1) << DTSRC_CR_SNSR_EN_POS) -#define DTSRC_CR_SNSR_EN_UMSK (~(((1U << DTSRC_CR_SNSR_EN_LEN) - 1) << DTSRC_CR_SNSR_EN_POS)) -#define DTSRC_CR_SNSR_HSYNC_INV DTSRC_CR_SNSR_HSYNC_INV -#define DTSRC_CR_SNSR_HSYNC_INV_POS (4U) -#define DTSRC_CR_SNSR_HSYNC_INV_LEN (1U) -#define DTSRC_CR_SNSR_HSYNC_INV_MSK (((1U << DTSRC_CR_SNSR_HSYNC_INV_LEN) - 1) << DTSRC_CR_SNSR_HSYNC_INV_POS) -#define DTSRC_CR_SNSR_HSYNC_INV_UMSK (~(((1U << DTSRC_CR_SNSR_HSYNC_INV_LEN) - 1) << DTSRC_CR_SNSR_HSYNC_INV_POS)) -#define DTSRC_CR_SNSR_VSYNC_INV DTSRC_CR_SNSR_VSYNC_INV -#define DTSRC_CR_SNSR_VSYNC_INV_POS (5U) -#define DTSRC_CR_SNSR_VSYNC_INV_LEN (1U) -#define DTSRC_CR_SNSR_VSYNC_INV_MSK (((1U << DTSRC_CR_SNSR_VSYNC_INV_LEN) - 1) << DTSRC_CR_SNSR_VSYNC_INV_POS) -#define DTSRC_CR_SNSR_VSYNC_INV_UMSK (~(((1U << DTSRC_CR_SNSR_VSYNC_INV_LEN) - 1) << DTSRC_CR_SNSR_VSYNC_INV_POS)) -#define DTSRC_CR_AXI_SWAP_MODE DTSRC_CR_AXI_SWAP_MODE -#define DTSRC_CR_AXI_SWAP_MODE_POS (7U) -#define DTSRC_CR_AXI_SWAP_MODE_LEN (1U) -#define DTSRC_CR_AXI_SWAP_MODE_MSK (((1U << DTSRC_CR_AXI_SWAP_MODE_LEN) - 1) << DTSRC_CR_AXI_SWAP_MODE_POS) -#define DTSRC_CR_AXI_SWAP_MODE_UMSK (~(((1U << DTSRC_CR_AXI_SWAP_MODE_LEN) - 1) << DTSRC_CR_AXI_SWAP_MODE_POS)) -#define DTSRC_CR_AXI_SWAP_IDX_SEL DTSRC_CR_AXI_SWAP_IDX_SEL -#define DTSRC_CR_AXI_SWAP_IDX_SEL_POS (8U) -#define DTSRC_CR_AXI_SWAP_IDX_SEL_LEN (4U) -#define DTSRC_CR_AXI_SWAP_IDX_SEL_MSK (((1U << DTSRC_CR_AXI_SWAP_IDX_SEL_LEN) - 1) << DTSRC_CR_AXI_SWAP_IDX_SEL_POS) -#define DTSRC_CR_AXI_SWAP_IDX_SEL_UMSK (~(((1U << DTSRC_CR_AXI_SWAP_IDX_SEL_LEN) - 1) << DTSRC_CR_AXI_SWAP_IDX_SEL_POS)) -#define DTSRC_CR_AXI_SWAP_IDX_SWM DTSRC_CR_AXI_SWAP_IDX_SWM -#define DTSRC_CR_AXI_SWAP_IDX_SWM_POS (12U) -#define DTSRC_CR_AXI_SWAP_IDX_SWM_LEN (1U) -#define DTSRC_CR_AXI_SWAP_IDX_SWM_MSK (((1U << DTSRC_CR_AXI_SWAP_IDX_SWM_LEN) - 1) << DTSRC_CR_AXI_SWAP_IDX_SWM_POS) -#define DTSRC_CR_AXI_SWAP_IDX_SWM_UMSK (~(((1U << DTSRC_CR_AXI_SWAP_IDX_SWM_LEN) - 1) << DTSRC_CR_AXI_SWAP_IDX_SWM_POS)) -#define DTSRC_CR_AXI_SWAP_IDX_SWV DTSRC_CR_AXI_SWAP_IDX_SWV -#define DTSRC_CR_AXI_SWAP_IDX_SWV_POS (13U) -#define DTSRC_CR_AXI_SWAP_IDX_SWV_LEN (1U) -#define DTSRC_CR_AXI_SWAP_IDX_SWV_MSK (((1U << DTSRC_CR_AXI_SWAP_IDX_SWV_LEN) - 1) << DTSRC_CR_AXI_SWAP_IDX_SWV_POS) -#define DTSRC_CR_AXI_SWAP_IDX_SWV_UMSK (~(((1U << DTSRC_CR_AXI_SWAP_IDX_SWV_LEN) - 1) << DTSRC_CR_AXI_SWAP_IDX_SWV_POS)) -#define DTSRC_CR_AXI_DVP_DATA_MODE DTSRC_CR_AXI_DVP_DATA_MODE -#define DTSRC_CR_AXI_DVP_DATA_MODE_POS (16U) -#define DTSRC_CR_AXI_DVP_DATA_MODE_LEN (3U) -#define DTSRC_CR_AXI_DVP_DATA_MODE_MSK (((1U << DTSRC_CR_AXI_DVP_DATA_MODE_LEN) - 1) << DTSRC_CR_AXI_DVP_DATA_MODE_POS) -#define DTSRC_CR_AXI_DVP_DATA_MODE_UMSK (~(((1U << DTSRC_CR_AXI_DVP_DATA_MODE_LEN) - 1) << DTSRC_CR_AXI_DVP_DATA_MODE_POS)) -#define DTSRC_CR_AXI_B0_SEL DTSRC_CR_AXI_B0_SEL -#define DTSRC_CR_AXI_B0_SEL_POS (20U) -#define DTSRC_CR_AXI_B0_SEL_LEN (2U) -#define DTSRC_CR_AXI_B0_SEL_MSK (((1U << DTSRC_CR_AXI_B0_SEL_LEN) - 1) << DTSRC_CR_AXI_B0_SEL_POS) -#define DTSRC_CR_AXI_B0_SEL_UMSK (~(((1U << DTSRC_CR_AXI_B0_SEL_LEN) - 1) << DTSRC_CR_AXI_B0_SEL_POS)) -#define DTSRC_CR_AXI_B1_SEL DTSRC_CR_AXI_B1_SEL -#define DTSRC_CR_AXI_B1_SEL_POS (22U) -#define DTSRC_CR_AXI_B1_SEL_LEN (2U) -#define DTSRC_CR_AXI_B1_SEL_MSK (((1U << DTSRC_CR_AXI_B1_SEL_LEN) - 1) << DTSRC_CR_AXI_B1_SEL_POS) -#define DTSRC_CR_AXI_B1_SEL_UMSK (~(((1U << DTSRC_CR_AXI_B1_SEL_LEN) - 1) << DTSRC_CR_AXI_B1_SEL_POS)) -#define DTSRC_CR_AXI_B2_SEL DTSRC_CR_AXI_B2_SEL -#define DTSRC_CR_AXI_B2_SEL_POS (24U) -#define DTSRC_CR_AXI_B2_SEL_LEN (2U) -#define DTSRC_CR_AXI_B2_SEL_MSK (((1U << DTSRC_CR_AXI_B2_SEL_LEN) - 1) << DTSRC_CR_AXI_B2_SEL_POS) -#define DTSRC_CR_AXI_B2_SEL_UMSK (~(((1U << DTSRC_CR_AXI_B2_SEL_LEN) - 1) << DTSRC_CR_AXI_B2_SEL_POS)) - -/* 0x4 : frame_size_h */ -#define DTSRC_FRAME_SIZE_H_OFFSET (0x4) -#define DTSRC_CR_TOTAL_H DTSRC_CR_TOTAL_H -#define DTSRC_CR_TOTAL_H_POS (0U) -#define DTSRC_CR_TOTAL_H_LEN (12U) -#define DTSRC_CR_TOTAL_H_MSK (((1U << DTSRC_CR_TOTAL_H_LEN) - 1) << DTSRC_CR_TOTAL_H_POS) -#define DTSRC_CR_TOTAL_H_UMSK (~(((1U << DTSRC_CR_TOTAL_H_LEN) - 1) << DTSRC_CR_TOTAL_H_POS)) -#define DTSRC_CR_BLANK_H DTSRC_CR_BLANK_H -#define DTSRC_CR_BLANK_H_POS (16U) -#define DTSRC_CR_BLANK_H_LEN (12U) -#define DTSRC_CR_BLANK_H_MSK (((1U << DTSRC_CR_BLANK_H_LEN) - 1) << DTSRC_CR_BLANK_H_POS) -#define DTSRC_CR_BLANK_H_UMSK (~(((1U << DTSRC_CR_BLANK_H_LEN) - 1) << DTSRC_CR_BLANK_H_POS)) - -/* 0x8 : frame_size_v */ -#define DTSRC_FRAME_SIZE_V_OFFSET (0x8) -#define DTSRC_CR_TOTAL_V DTSRC_CR_TOTAL_V -#define DTSRC_CR_TOTAL_V_POS (0U) -#define DTSRC_CR_TOTAL_V_LEN (12U) -#define DTSRC_CR_TOTAL_V_MSK (((1U << DTSRC_CR_TOTAL_V_LEN) - 1) << DTSRC_CR_TOTAL_V_POS) -#define DTSRC_CR_TOTAL_V_UMSK (~(((1U << DTSRC_CR_TOTAL_V_LEN) - 1) << DTSRC_CR_TOTAL_V_POS)) -#define DTSRC_CR_BLANK_V DTSRC_CR_BLANK_V -#define DTSRC_CR_BLANK_V_POS (16U) -#define DTSRC_CR_BLANK_V_LEN (12U) -#define DTSRC_CR_BLANK_V_MSK (((1U << DTSRC_CR_BLANK_V_LEN) - 1) << DTSRC_CR_BLANK_V_POS) -#define DTSRC_CR_BLANK_V_UMSK (~(((1U << DTSRC_CR_BLANK_V_LEN) - 1) << DTSRC_CR_BLANK_V_POS)) - -/* 0xC : frame_size_cea_861 */ -#define DTSRC_FRAME_SIZE_CEA_861_OFFSET (0xC) -#define DTSRC_CR_H_DURATION DTSRC_CR_H_DURATION -#define DTSRC_CR_H_DURATION_POS (0U) -#define DTSRC_CR_H_DURATION_LEN (8U) -#define DTSRC_CR_H_DURATION_MSK (((1U << DTSRC_CR_H_DURATION_LEN) - 1) << DTSRC_CR_H_DURATION_POS) -#define DTSRC_CR_H_DURATION_UMSK (~(((1U << DTSRC_CR_H_DURATION_LEN) - 1) << DTSRC_CR_H_DURATION_POS)) -#define DTSRC_CR_H_PLACEMENT DTSRC_CR_H_PLACEMENT -#define DTSRC_CR_H_PLACEMENT_POS (8U) -#define DTSRC_CR_H_PLACEMENT_LEN (8U) -#define DTSRC_CR_H_PLACEMENT_MSK (((1U << DTSRC_CR_H_PLACEMENT_LEN) - 1) << DTSRC_CR_H_PLACEMENT_POS) -#define DTSRC_CR_H_PLACEMENT_UMSK (~(((1U << DTSRC_CR_H_PLACEMENT_LEN) - 1) << DTSRC_CR_H_PLACEMENT_POS)) -#define DTSRC_CR_V_DURATION DTSRC_CR_V_DURATION -#define DTSRC_CR_V_DURATION_POS (16U) -#define DTSRC_CR_V_DURATION_LEN (8U) -#define DTSRC_CR_V_DURATION_MSK (((1U << DTSRC_CR_V_DURATION_LEN) - 1) << DTSRC_CR_V_DURATION_POS) -#define DTSRC_CR_V_DURATION_UMSK (~(((1U << DTSRC_CR_V_DURATION_LEN) - 1) << DTSRC_CR_V_DURATION_POS)) -#define DTSRC_CR_V_PLACEMENT DTSRC_CR_V_PLACEMENT -#define DTSRC_CR_V_PLACEMENT_POS (24U) -#define DTSRC_CR_V_PLACEMENT_LEN (8U) -#define DTSRC_CR_V_PLACEMENT_MSK (((1U << DTSRC_CR_V_PLACEMENT_LEN) - 1) << DTSRC_CR_V_PLACEMENT_POS) -#define DTSRC_CR_V_PLACEMENT_UMSK (~(((1U << DTSRC_CR_V_PLACEMENT_LEN) - 1) << DTSRC_CR_V_PLACEMENT_POS)) - -/* 0x10 : pix_data_range */ -#define DTSRC_PIX_DATA_RANGE_OFFSET (0x10) -#define DTSRC_CR_DATA_MIN DTSRC_CR_DATA_MIN -#define DTSRC_CR_DATA_MIN_POS (0U) -#define DTSRC_CR_DATA_MIN_LEN (16U) -#define DTSRC_CR_DATA_MIN_MSK (((1U << DTSRC_CR_DATA_MIN_LEN) - 1) << DTSRC_CR_DATA_MIN_POS) -#define DTSRC_CR_DATA_MIN_UMSK (~(((1U << DTSRC_CR_DATA_MIN_LEN) - 1) << DTSRC_CR_DATA_MIN_POS)) -#define DTSRC_CR_DATA_MAX DTSRC_CR_DATA_MAX -#define DTSRC_CR_DATA_MAX_POS (16U) -#define DTSRC_CR_DATA_MAX_LEN (16U) -#define DTSRC_CR_DATA_MAX_MSK (((1U << DTSRC_CR_DATA_MAX_LEN) - 1) << DTSRC_CR_DATA_MAX_POS) -#define DTSRC_CR_DATA_MAX_UMSK (~(((1U << DTSRC_CR_DATA_MAX_LEN) - 1) << DTSRC_CR_DATA_MAX_POS)) - -/* 0x14 : pix_data_step */ -#define DTSRC_PIX_DATA_STEP_OFFSET (0x14) -#define DTSRC_CR_DATA_STEP DTSRC_CR_DATA_STEP -#define DTSRC_CR_DATA_STEP_POS (0U) -#define DTSRC_CR_DATA_STEP_LEN (8U) -#define DTSRC_CR_DATA_STEP_MSK (((1U << DTSRC_CR_DATA_STEP_LEN) - 1) << DTSRC_CR_DATA_STEP_POS) -#define DTSRC_CR_DATA_STEP_UMSK (~(((1U << DTSRC_CR_DATA_STEP_LEN) - 1) << DTSRC_CR_DATA_STEP_POS)) - -/* 0x20 : axi2dvp_setting */ -#define DTSRC_AXI2DVP_SETTING_OFFSET (0x20) -#define DTSRC_CR_AXI_XLEN DTSRC_CR_AXI_XLEN -#define DTSRC_CR_AXI_XLEN_POS (0U) -#define DTSRC_CR_AXI_XLEN_LEN (3U) -#define DTSRC_CR_AXI_XLEN_MSK (((1U << DTSRC_CR_AXI_XLEN_LEN) - 1) << DTSRC_CR_AXI_XLEN_POS) -#define DTSRC_CR_AXI_XLEN_UMSK (~(((1U << DTSRC_CR_AXI_XLEN_LEN) - 1) << DTSRC_CR_AXI_XLEN_POS)) -#define DTSRC_CR_AXI_DRAIN_ERR_CLR DTSRC_CR_AXI_DRAIN_ERR_CLR -#define DTSRC_CR_AXI_DRAIN_ERR_CLR_POS (4U) -#define DTSRC_CR_AXI_DRAIN_ERR_CLR_LEN (1U) -#define DTSRC_CR_AXI_DRAIN_ERR_CLR_MSK (((1U << DTSRC_CR_AXI_DRAIN_ERR_CLR_LEN) - 1) << DTSRC_CR_AXI_DRAIN_ERR_CLR_POS) -#define DTSRC_CR_AXI_DRAIN_ERR_CLR_UMSK (~(((1U << DTSRC_CR_AXI_DRAIN_ERR_CLR_LEN) - 1) << DTSRC_CR_AXI_DRAIN_ERR_CLR_POS)) -#define DTSRC_CR_AXI_420_MODE DTSRC_CR_AXI_420_MODE -#define DTSRC_CR_AXI_420_MODE_POS (8U) -#define DTSRC_CR_AXI_420_MODE_LEN (1U) -#define DTSRC_CR_AXI_420_MODE_MSK (((1U << DTSRC_CR_AXI_420_MODE_LEN) - 1) << DTSRC_CR_AXI_420_MODE_POS) -#define DTSRC_CR_AXI_420_MODE_UMSK (~(((1U << DTSRC_CR_AXI_420_MODE_LEN) - 1) << DTSRC_CR_AXI_420_MODE_POS)) -#define DTSRC_CR_AXI_420_UD_SEL DTSRC_CR_AXI_420_UD_SEL -#define DTSRC_CR_AXI_420_UD_SEL_POS (9U) -#define DTSRC_CR_AXI_420_UD_SEL_LEN (1U) -#define DTSRC_CR_AXI_420_UD_SEL_MSK (((1U << DTSRC_CR_AXI_420_UD_SEL_LEN) - 1) << DTSRC_CR_AXI_420_UD_SEL_POS) -#define DTSRC_CR_AXI_420_UD_SEL_UMSK (~(((1U << DTSRC_CR_AXI_420_UD_SEL_LEN) - 1) << DTSRC_CR_AXI_420_UD_SEL_POS)) -#define DTSRC_CR_QOS_SW_MODE DTSRC_CR_QOS_SW_MODE -#define DTSRC_CR_QOS_SW_MODE_POS (10U) -#define DTSRC_CR_QOS_SW_MODE_LEN (1U) -#define DTSRC_CR_QOS_SW_MODE_MSK (((1U << DTSRC_CR_QOS_SW_MODE_LEN) - 1) << DTSRC_CR_QOS_SW_MODE_POS) -#define DTSRC_CR_QOS_SW_MODE_UMSK (~(((1U << DTSRC_CR_QOS_SW_MODE_LEN) - 1) << DTSRC_CR_QOS_SW_MODE_POS)) -#define DTSRC_CR_QOS_SW DTSRC_CR_QOS_SW -#define DTSRC_CR_QOS_SW_POS (11U) -#define DTSRC_CR_QOS_SW_LEN (1U) -#define DTSRC_CR_QOS_SW_MSK (((1U << DTSRC_CR_QOS_SW_LEN) - 1) << DTSRC_CR_QOS_SW_POS) -#define DTSRC_CR_QOS_SW_UMSK (~(((1U << DTSRC_CR_QOS_SW_LEN) - 1) << DTSRC_CR_QOS_SW_POS)) - -/* 0x24 : axi2dvp_start_addr_by */ -#define DTSRC_AXI2DVP_START_ADDR_BY_OFFSET (0x24) -#define DTSRC_CR_AXI_ADDR_START_BY DTSRC_CR_AXI_ADDR_START_BY -#define DTSRC_CR_AXI_ADDR_START_BY_POS (0U) -#define DTSRC_CR_AXI_ADDR_START_BY_LEN (32U) -#define DTSRC_CR_AXI_ADDR_START_BY_MSK (((1U << DTSRC_CR_AXI_ADDR_START_BY_LEN) - 1) << DTSRC_CR_AXI_ADDR_START_BY_POS) -#define DTSRC_CR_AXI_ADDR_START_BY_UMSK (~(((1U << DTSRC_CR_AXI_ADDR_START_BY_LEN) - 1) << DTSRC_CR_AXI_ADDR_START_BY_POS)) - -/* 0x28 : axi2dvp_burst_cnt */ -#define DTSRC_AXI2DVP_BURST_CNT_OFFSET (0x28) -#define DTSRC_CR_AXI_FRAME_BC DTSRC_CR_AXI_FRAME_BC -#define DTSRC_CR_AXI_FRAME_BC_POS (0U) -#define DTSRC_CR_AXI_FRAME_BC_LEN (32U) -#define DTSRC_CR_AXI_FRAME_BC_MSK (((1U << DTSRC_CR_AXI_FRAME_BC_LEN) - 1) << DTSRC_CR_AXI_FRAME_BC_POS) -#define DTSRC_CR_AXI_FRAME_BC_UMSK (~(((1U << DTSRC_CR_AXI_FRAME_BC_LEN) - 1) << DTSRC_CR_AXI_FRAME_BC_POS)) - -/* 0x2C : axi2dvp_status */ -#define DTSRC_AXI2DVP_STATUS_OFFSET (0x2C) -#define DTSRC_ST_AXI_FIFO_CNT_BY DTSRC_ST_AXI_FIFO_CNT_BY -#define DTSRC_ST_AXI_FIFO_CNT_BY_POS (0U) -#define DTSRC_ST_AXI_FIFO_CNT_BY_LEN (7U) -#define DTSRC_ST_AXI_FIFO_CNT_BY_MSK (((1U << DTSRC_ST_AXI_FIFO_CNT_BY_LEN) - 1) << DTSRC_ST_AXI_FIFO_CNT_BY_POS) -#define DTSRC_ST_AXI_FIFO_CNT_BY_UMSK (~(((1U << DTSRC_ST_AXI_FIFO_CNT_BY_LEN) - 1) << DTSRC_ST_AXI_FIFO_CNT_BY_POS)) -#define DTSRC_ST_AXI_DRAIN_ERROR_BY DTSRC_ST_AXI_DRAIN_ERROR_BY -#define DTSRC_ST_AXI_DRAIN_ERROR_BY_POS (7U) -#define DTSRC_ST_AXI_DRAIN_ERROR_BY_LEN (1U) -#define DTSRC_ST_AXI_DRAIN_ERROR_BY_MSK (((1U << DTSRC_ST_AXI_DRAIN_ERROR_BY_LEN) - 1) << DTSRC_ST_AXI_DRAIN_ERROR_BY_POS) -#define DTSRC_ST_AXI_DRAIN_ERROR_BY_UMSK (~(((1U << DTSRC_ST_AXI_DRAIN_ERROR_BY_LEN) - 1) << DTSRC_ST_AXI_DRAIN_ERROR_BY_POS)) -#define DTSRC_ST_AXI_STATE_IDLE_BY DTSRC_ST_AXI_STATE_IDLE_BY -#define DTSRC_ST_AXI_STATE_IDLE_BY_POS (8U) -#define DTSRC_ST_AXI_STATE_IDLE_BY_LEN (1U) -#define DTSRC_ST_AXI_STATE_IDLE_BY_MSK (((1U << DTSRC_ST_AXI_STATE_IDLE_BY_LEN) - 1) << DTSRC_ST_AXI_STATE_IDLE_BY_POS) -#define DTSRC_ST_AXI_STATE_IDLE_BY_UMSK (~(((1U << DTSRC_ST_AXI_STATE_IDLE_BY_LEN) - 1) << DTSRC_ST_AXI_STATE_IDLE_BY_POS)) -#define DTSRC_ST_AXI_STATE_FUNC_BY DTSRC_ST_AXI_STATE_FUNC_BY -#define DTSRC_ST_AXI_STATE_FUNC_BY_POS (9U) -#define DTSRC_ST_AXI_STATE_FUNC_BY_LEN (1U) -#define DTSRC_ST_AXI_STATE_FUNC_BY_MSK (((1U << DTSRC_ST_AXI_STATE_FUNC_BY_LEN) - 1) << DTSRC_ST_AXI_STATE_FUNC_BY_POS) -#define DTSRC_ST_AXI_STATE_FUNC_BY_UMSK (~(((1U << DTSRC_ST_AXI_STATE_FUNC_BY_LEN) - 1) << DTSRC_ST_AXI_STATE_FUNC_BY_POS)) -#define DTSRC_ST_AXI_STATE_FLSH_BY DTSRC_ST_AXI_STATE_FLSH_BY -#define DTSRC_ST_AXI_STATE_FLSH_BY_POS (10U) -#define DTSRC_ST_AXI_STATE_FLSH_BY_LEN (1U) -#define DTSRC_ST_AXI_STATE_FLSH_BY_MSK (((1U << DTSRC_ST_AXI_STATE_FLSH_BY_LEN) - 1) << DTSRC_ST_AXI_STATE_FLSH_BY_POS) -#define DTSRC_ST_AXI_STATE_FLSH_BY_UMSK (~(((1U << DTSRC_ST_AXI_STATE_FLSH_BY_LEN) - 1) << DTSRC_ST_AXI_STATE_FLSH_BY_POS)) -#define DTSRC_ST_AXI_FIFO_CNT_UV DTSRC_ST_AXI_FIFO_CNT_UV -#define DTSRC_ST_AXI_FIFO_CNT_UV_POS (16U) -#define DTSRC_ST_AXI_FIFO_CNT_UV_LEN (7U) -#define DTSRC_ST_AXI_FIFO_CNT_UV_MSK (((1U << DTSRC_ST_AXI_FIFO_CNT_UV_LEN) - 1) << DTSRC_ST_AXI_FIFO_CNT_UV_POS) -#define DTSRC_ST_AXI_FIFO_CNT_UV_UMSK (~(((1U << DTSRC_ST_AXI_FIFO_CNT_UV_LEN) - 1) << DTSRC_ST_AXI_FIFO_CNT_UV_POS)) -#define DTSRC_ST_AXI_DRAIN_ERROR_UV DTSRC_ST_AXI_DRAIN_ERROR_UV -#define DTSRC_ST_AXI_DRAIN_ERROR_UV_POS (23U) -#define DTSRC_ST_AXI_DRAIN_ERROR_UV_LEN (1U) -#define DTSRC_ST_AXI_DRAIN_ERROR_UV_MSK (((1U << DTSRC_ST_AXI_DRAIN_ERROR_UV_LEN) - 1) << DTSRC_ST_AXI_DRAIN_ERROR_UV_POS) -#define DTSRC_ST_AXI_DRAIN_ERROR_UV_UMSK (~(((1U << DTSRC_ST_AXI_DRAIN_ERROR_UV_LEN) - 1) << DTSRC_ST_AXI_DRAIN_ERROR_UV_POS)) -#define DTSRC_ST_AXI_STATE_IDLE_UV DTSRC_ST_AXI_STATE_IDLE_UV -#define DTSRC_ST_AXI_STATE_IDLE_UV_POS (24U) -#define DTSRC_ST_AXI_STATE_IDLE_UV_LEN (1U) -#define DTSRC_ST_AXI_STATE_IDLE_UV_MSK (((1U << DTSRC_ST_AXI_STATE_IDLE_UV_LEN) - 1) << DTSRC_ST_AXI_STATE_IDLE_UV_POS) -#define DTSRC_ST_AXI_STATE_IDLE_UV_UMSK (~(((1U << DTSRC_ST_AXI_STATE_IDLE_UV_LEN) - 1) << DTSRC_ST_AXI_STATE_IDLE_UV_POS)) -#define DTSRC_ST_AXI_STATE_FUNC_UV DTSRC_ST_AXI_STATE_FUNC_UV -#define DTSRC_ST_AXI_STATE_FUNC_UV_POS (25U) -#define DTSRC_ST_AXI_STATE_FUNC_UV_LEN (1U) -#define DTSRC_ST_AXI_STATE_FUNC_UV_MSK (((1U << DTSRC_ST_AXI_STATE_FUNC_UV_LEN) - 1) << DTSRC_ST_AXI_STATE_FUNC_UV_POS) -#define DTSRC_ST_AXI_STATE_FUNC_UV_UMSK (~(((1U << DTSRC_ST_AXI_STATE_FUNC_UV_LEN) - 1) << DTSRC_ST_AXI_STATE_FUNC_UV_POS)) -#define DTSRC_ST_AXI_STATE_FLSH_UV DTSRC_ST_AXI_STATE_FLSH_UV -#define DTSRC_ST_AXI_STATE_FLSH_UV_POS (26U) -#define DTSRC_ST_AXI_STATE_FLSH_UV_LEN (1U) -#define DTSRC_ST_AXI_STATE_FLSH_UV_MSK (((1U << DTSRC_ST_AXI_STATE_FLSH_UV_LEN) - 1) << DTSRC_ST_AXI_STATE_FLSH_UV_POS) -#define DTSRC_ST_AXI_STATE_FLSH_UV_UMSK (~(((1U << DTSRC_ST_AXI_STATE_FLSH_UV_LEN) - 1) << DTSRC_ST_AXI_STATE_FLSH_UV_POS)) - -/* 0x30 : axi2dvp_swap_addr_by */ -#define DTSRC_AXI2DVP_SWAP_ADDR_BY_OFFSET (0x30) -#define DTSRC_CR_AXI_ADDR_SWAP_BY DTSRC_CR_AXI_ADDR_SWAP_BY -#define DTSRC_CR_AXI_ADDR_SWAP_BY_POS (0U) -#define DTSRC_CR_AXI_ADDR_SWAP_BY_LEN (32U) -#define DTSRC_CR_AXI_ADDR_SWAP_BY_MSK (((1U << DTSRC_CR_AXI_ADDR_SWAP_BY_LEN) - 1) << DTSRC_CR_AXI_ADDR_SWAP_BY_POS) -#define DTSRC_CR_AXI_ADDR_SWAP_BY_UMSK (~(((1U << DTSRC_CR_AXI_ADDR_SWAP_BY_LEN) - 1) << DTSRC_CR_AXI_ADDR_SWAP_BY_POS)) - -/* 0x34 : axi2dvp_prefetch */ -#define DTSRC_AXI2DVP_PREFETCH_OFFSET (0x34) -#define DTSRC_CR_PREFETCH_V DTSRC_CR_PREFETCH_V -#define DTSRC_CR_PREFETCH_V_POS (0U) -#define DTSRC_CR_PREFETCH_V_LEN (12U) -#define DTSRC_CR_PREFETCH_V_MSK (((1U << DTSRC_CR_PREFETCH_V_LEN) - 1) << DTSRC_CR_PREFETCH_V_POS) -#define DTSRC_CR_PREFETCH_V_UMSK (~(((1U << DTSRC_CR_PREFETCH_V_LEN) - 1) << DTSRC_CR_PREFETCH_V_POS)) - -/* 0x38 : snsr2dvp_wait_pos */ -#define DTSRC_SNSR2DVP_WAIT_POS_OFFSET (0x38) -#define DTSRC_CR_SNSR_FIFO_TH DTSRC_CR_SNSR_FIFO_TH -#define DTSRC_CR_SNSR_FIFO_TH_POS (0U) -#define DTSRC_CR_SNSR_FIFO_TH_LEN (11U) -#define DTSRC_CR_SNSR_FIFO_TH_MSK (((1U << DTSRC_CR_SNSR_FIFO_TH_LEN) - 1) << DTSRC_CR_SNSR_FIFO_TH_POS) -#define DTSRC_CR_SNSR_FIFO_TH_UMSK (~(((1U << DTSRC_CR_SNSR_FIFO_TH_LEN) - 1) << DTSRC_CR_SNSR_FIFO_TH_POS)) - -/* 0x40 : axi2dvp_start_addr_uv */ -#define DTSRC_AXI2DVP_START_ADDR_UV_OFFSET (0x40) -#define DTSRC_CR_AXI_ADDR_START_UV DTSRC_CR_AXI_ADDR_START_UV -#define DTSRC_CR_AXI_ADDR_START_UV_POS (0U) -#define DTSRC_CR_AXI_ADDR_START_UV_LEN (32U) -#define DTSRC_CR_AXI_ADDR_START_UV_MSK (((1U << DTSRC_CR_AXI_ADDR_START_UV_LEN) - 1) << DTSRC_CR_AXI_ADDR_START_UV_POS) -#define DTSRC_CR_AXI_ADDR_START_UV_UMSK (~(((1U << DTSRC_CR_AXI_ADDR_START_UV_LEN) - 1) << DTSRC_CR_AXI_ADDR_START_UV_POS)) - -/* 0x44 : axi2dvp_swap_addr_uv */ -#define DTSRC_AXI2DVP_SWAP_ADDR_UV_OFFSET (0x44) -#define DTSRC_CR_AXI_ADDR_SWAP_UV DTSRC_CR_AXI_ADDR_SWAP_UV -#define DTSRC_CR_AXI_ADDR_SWAP_UV_POS (0U) -#define DTSRC_CR_AXI_ADDR_SWAP_UV_LEN (32U) -#define DTSRC_CR_AXI_ADDR_SWAP_UV_MSK (((1U << DTSRC_CR_AXI_ADDR_SWAP_UV_LEN) - 1) << DTSRC_CR_AXI_ADDR_SWAP_UV_POS) -#define DTSRC_CR_AXI_ADDR_SWAP_UV_UMSK (~(((1U << DTSRC_CR_AXI_ADDR_SWAP_UV_LEN) - 1) << DTSRC_CR_AXI_ADDR_SWAP_UV_POS)) - -struct dtsrc_reg { - /* 0x0 : config */ - union { - struct { - uint32_t cr_enable : 1; /* [ 0], r/w, 0x0 */ - uint32_t cr_axi_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t cr_mode_cea_861 : 1; /* [ 2], r/w, 0x0 */ - uint32_t cr_snsr_en : 1; /* [ 3], r/w, 0x0 */ - uint32_t cr_snsr_hsync_inv : 1; /* [ 4], r/w, 0x0 */ - uint32_t cr_snsr_vsync_inv : 1; /* [ 5], r/w, 0x0 */ - uint32_t reserved_6 : 1; /* [ 6], rsvd, 0x0 */ - uint32_t cr_axi_swap_mode : 1; /* [ 7], r/w, 0x0 */ - uint32_t cr_axi_swap_idx_sel : 4; /* [11: 8], r/w, 0x0 */ - uint32_t cr_axi_swap_idx_swm : 1; /* [ 12], r/w, 0x0 */ - uint32_t cr_axi_swap_idx_swv : 1; /* [ 13], r/w, 0x0 */ - uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ - uint32_t cr_axi_dvp_data_mode : 3; /* [18:16], r/w, 0x0 */ - uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */ - uint32_t cr_axi_b0_sel : 2; /* [21:20], r/w, 0x0 */ - uint32_t cr_axi_b1_sel : 2; /* [23:22], r/w, 0x1 */ - uint32_t cr_axi_b2_sel : 2; /* [25:24], r/w, 0x2 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } config; - - /* 0x4 : frame_size_h */ - union { - struct { - uint32_t cr_total_h : 12; /* [11: 0], r/w, 0x897 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t cr_blank_h : 12; /* [27:16], r/w, 0x117 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } frame_size_h; - - /* 0x8 : frame_size_v */ - union { - struct { - uint32_t cr_total_v : 12; /* [11: 0], r/w, 0x464 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t cr_blank_v : 12; /* [27:16], r/w, 0x2c */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } frame_size_v; - - /* 0xC : frame_size_cea_861 */ - union { - struct { - uint32_t cr_h_duration : 8; /* [ 7: 0], r/w, 0x83 */ - uint32_t cr_h_placement : 8; /* [15: 8], r/w, 0x57 */ - uint32_t cr_v_duration : 8; /* [23:16], r/w, 0x8 */ - uint32_t cr_v_placement : 8; /* [31:24], r/w, 0x3 */ - } BF; - uint32_t WORD; - } frame_size_cea_861; - - /* 0x10 : pix_data_range */ - union { - struct { - uint32_t cr_data_min : 16; /* [15: 0], r/w, 0x0 */ - uint32_t cr_data_max : 16; /* [31:16], r/w, 0xffff */ - } BF; - uint32_t WORD; - } pix_data_range; - - /* 0x14 : pix_data_step */ - union { - struct { - uint32_t cr_data_step : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } pix_data_step; - - /* 0x18 reserved */ - uint8_t RESERVED0x18[8]; - - /* 0x20 : axi2dvp_setting */ - union { - struct { - uint32_t cr_axi_xlen : 3; /* [ 2: 0], r/w, 0x3 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t cr_axi_drain_err_clr : 1; /* [ 4], w1p, 0x0 */ - uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ - uint32_t cr_axi_420_mode : 1; /* [ 8], r/w, 0x0 */ - uint32_t cr_axi_420_ud_sel : 1; /* [ 9], r/w, 0x0 */ - uint32_t cr_qos_sw_mode : 1; /* [ 10], r/w, 0x0 */ - uint32_t cr_qos_sw : 1; /* [ 11], r/w, 0x0 */ - uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } axi2dvp_setting; - - /* 0x24 : axi2dvp_start_addr_by */ - union { - struct { - uint32_t cr_axi_addr_start_by : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } axi2dvp_start_addr_by; - - /* 0x28 : axi2dvp_burst_cnt */ - union { - struct { - uint32_t cr_axi_frame_bc : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } axi2dvp_burst_cnt; - - /* 0x2C : axi2dvp_status */ - union { - struct { - uint32_t st_axi_fifo_cnt_by : 7; /* [ 6: 0], r, 0x0 */ - uint32_t st_axi_drain_error_by : 1; /* [ 7], r, 0x0 */ - uint32_t st_axi_state_idle_by : 1; /* [ 8], r, 0x0 */ - uint32_t st_axi_state_func_by : 1; /* [ 9], r, 0x0 */ - uint32_t st_axi_state_flsh_by : 1; /* [ 10], r, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t st_axi_fifo_cnt_uv : 7; /* [22:16], r, 0x0 */ - uint32_t st_axi_drain_error_uv : 1; /* [ 23], r, 0x0 */ - uint32_t st_axi_state_idle_uv : 1; /* [ 24], r, 0x0 */ - uint32_t st_axi_state_func_uv : 1; /* [ 25], r, 0x0 */ - uint32_t st_axi_state_flsh_uv : 1; /* [ 26], r, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } axi2dvp_status; - - /* 0x30 : axi2dvp_swap_addr_by */ - union { - struct { - uint32_t cr_axi_addr_swap_by : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } axi2dvp_swap_addr_by; - - /* 0x34 : axi2dvp_prefetch */ - union { - struct { - uint32_t cr_prefetch_v : 12; /* [11: 0], r/w, 0x28 */ - uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } axi2dvp_prefetch; - - /* 0x38 : snsr2dvp_wait_pos */ - union { - struct { - uint32_t cr_snsr_fifo_th : 11; /* [10: 0], r/w, 0x8b */ - uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } snsr2dvp_wait_pos; - - /* 0x3c reserved */ - uint8_t RESERVED0x3c[4]; - - /* 0x40 : axi2dvp_start_addr_uv */ - union { - struct { - uint32_t cr_axi_addr_start_uv : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } axi2dvp_start_addr_uv; - - /* 0x44 : axi2dvp_swap_addr_uv */ - union { - struct { - uint32_t cr_axi_addr_swap_uv : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } axi2dvp_swap_addr_uv; -}; - -typedef volatile struct dtsrc_reg dtsrc_reg_t; - -#endif /* __DTSRC_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/emac_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/emac_reg.h deleted file mode 100644 index afb93d6598..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/emac_reg.h +++ /dev/null @@ -1,583 +0,0 @@ -/** - ****************************************************************************** - * @file emac_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __EMAC_REG_H__ -#define __EMAC_REG_H__ - -#include "bl808.h" - -/* 0x0 : MODE */ -#define EMAC_MODE_OFFSET (0x0) -#define EMAC_RXEN EMAC_RXEN -#define EMAC_RXEN_POS (0U) -#define EMAC_RXEN_LEN (1U) -#define EMAC_RXEN_MSK (((1U << EMAC_RXEN_LEN) - 1) << EMAC_RXEN_POS) -#define EMAC_RXEN_UMSK (~(((1U << EMAC_RXEN_LEN) - 1) << EMAC_RXEN_POS)) -#define EMAC_TXEN EMAC_TXEN -#define EMAC_TXEN_POS (1U) -#define EMAC_TXEN_LEN (1U) -#define EMAC_TXEN_MSK (((1U << EMAC_TXEN_LEN) - 1) << EMAC_TXEN_POS) -#define EMAC_TXEN_UMSK (~(((1U << EMAC_TXEN_LEN) - 1) << EMAC_TXEN_POS)) -#define EMAC_NOPRE EMAC_NOPRE -#define EMAC_NOPRE_POS (2U) -#define EMAC_NOPRE_LEN (1U) -#define EMAC_NOPRE_MSK (((1U << EMAC_NOPRE_LEN) - 1) << EMAC_NOPRE_POS) -#define EMAC_NOPRE_UMSK (~(((1U << EMAC_NOPRE_LEN) - 1) << EMAC_NOPRE_POS)) -#define EMAC_BRO EMAC_BRO -#define EMAC_BRO_POS (3U) -#define EMAC_BRO_LEN (1U) -#define EMAC_BRO_MSK (((1U << EMAC_BRO_LEN) - 1) << EMAC_BRO_POS) -#define EMAC_BRO_UMSK (~(((1U << EMAC_BRO_LEN) - 1) << EMAC_BRO_POS)) -#define EMAC_PRO EMAC_PRO -#define EMAC_PRO_POS (5U) -#define EMAC_PRO_LEN (1U) -#define EMAC_PRO_MSK (((1U << EMAC_PRO_LEN) - 1) << EMAC_PRO_POS) -#define EMAC_PRO_UMSK (~(((1U << EMAC_PRO_LEN) - 1) << EMAC_PRO_POS)) -#define EMAC_IFG EMAC_IFG -#define EMAC_IFG_POS (6U) -#define EMAC_IFG_LEN (1U) -#define EMAC_IFG_MSK (((1U << EMAC_IFG_LEN) - 1) << EMAC_IFG_POS) -#define EMAC_IFG_UMSK (~(((1U << EMAC_IFG_LEN) - 1) << EMAC_IFG_POS)) -#define EMAC_FULLD EMAC_FULLD -#define EMAC_FULLD_POS (10U) -#define EMAC_FULLD_LEN (1U) -#define EMAC_FULLD_MSK (((1U << EMAC_FULLD_LEN) - 1) << EMAC_FULLD_POS) -#define EMAC_FULLD_UMSK (~(((1U << EMAC_FULLD_LEN) - 1) << EMAC_FULLD_POS)) -#define EMAC_CRCEN EMAC_CRCEN -#define EMAC_CRCEN_POS (13U) -#define EMAC_CRCEN_LEN (1U) -#define EMAC_CRCEN_MSK (((1U << EMAC_CRCEN_LEN) - 1) << EMAC_CRCEN_POS) -#define EMAC_CRCEN_UMSK (~(((1U << EMAC_CRCEN_LEN) - 1) << EMAC_CRCEN_POS)) -#define EMAC_HUGEN EMAC_HUGEN -#define EMAC_HUGEN_POS (14U) -#define EMAC_HUGEN_LEN (1U) -#define EMAC_HUGEN_MSK (((1U << EMAC_HUGEN_LEN) - 1) << EMAC_HUGEN_POS) -#define EMAC_HUGEN_UMSK (~(((1U << EMAC_HUGEN_LEN) - 1) << EMAC_HUGEN_POS)) -#define EMAC_PAD EMAC_PAD -#define EMAC_PAD_POS (15U) -#define EMAC_PAD_LEN (1U) -#define EMAC_PAD_MSK (((1U << EMAC_PAD_LEN) - 1) << EMAC_PAD_POS) -#define EMAC_PAD_UMSK (~(((1U << EMAC_PAD_LEN) - 1) << EMAC_PAD_POS)) -#define EMAC_RECSMALL EMAC_RECSMALL -#define EMAC_RECSMALL_POS (16U) -#define EMAC_RECSMALL_LEN (1U) -#define EMAC_RECSMALL_MSK (((1U << EMAC_RECSMALL_LEN) - 1) << EMAC_RECSMALL_POS) -#define EMAC_RECSMALL_UMSK (~(((1U << EMAC_RECSMALL_LEN) - 1) << EMAC_RECSMALL_POS)) -#define EMAC_RMII_EN EMAC_RMII_EN -#define EMAC_RMII_EN_POS (17U) -#define EMAC_RMII_EN_LEN (1U) -#define EMAC_RMII_EN_MSK (((1U << EMAC_RMII_EN_LEN) - 1) << EMAC_RMII_EN_POS) -#define EMAC_RMII_EN_UMSK (~(((1U << EMAC_RMII_EN_LEN) - 1) << EMAC_RMII_EN_POS)) - -/* 0x4 : INT_SOURCE */ -#define EMAC_INT_SOURCE_OFFSET (0x4) -#define EMAC_TXB EMAC_TXB -#define EMAC_TXB_POS (0U) -#define EMAC_TXB_LEN (1U) -#define EMAC_TXB_MSK (((1U << EMAC_TXB_LEN) - 1) << EMAC_TXB_POS) -#define EMAC_TXB_UMSK (~(((1U << EMAC_TXB_LEN) - 1) << EMAC_TXB_POS)) -#define EMAC_TXE EMAC_TXE -#define EMAC_TXE_POS (1U) -#define EMAC_TXE_LEN (1U) -#define EMAC_TXE_MSK (((1U << EMAC_TXE_LEN) - 1) << EMAC_TXE_POS) -#define EMAC_TXE_UMSK (~(((1U << EMAC_TXE_LEN) - 1) << EMAC_TXE_POS)) -#define EMAC_RXB EMAC_RXB -#define EMAC_RXB_POS (2U) -#define EMAC_RXB_LEN (1U) -#define EMAC_RXB_MSK (((1U << EMAC_RXB_LEN) - 1) << EMAC_RXB_POS) -#define EMAC_RXB_UMSK (~(((1U << EMAC_RXB_LEN) - 1) << EMAC_RXB_POS)) -#define EMAC_RXE EMAC_RXE -#define EMAC_RXE_POS (3U) -#define EMAC_RXE_LEN (1U) -#define EMAC_RXE_MSK (((1U << EMAC_RXE_LEN) - 1) << EMAC_RXE_POS) -#define EMAC_RXE_UMSK (~(((1U << EMAC_RXE_LEN) - 1) << EMAC_RXE_POS)) -#define EMAC_BUSY EMAC_BUSY -#define EMAC_BUSY_POS (4U) -#define EMAC_BUSY_LEN (1U) -#define EMAC_BUSY_MSK (((1U << EMAC_BUSY_LEN) - 1) << EMAC_BUSY_POS) -#define EMAC_BUSY_UMSK (~(((1U << EMAC_BUSY_LEN) - 1) << EMAC_BUSY_POS)) -#define EMAC_TXC EMAC_TXC -#define EMAC_TXC_POS (5U) -#define EMAC_TXC_LEN (1U) -#define EMAC_TXC_MSK (((1U << EMAC_TXC_LEN) - 1) << EMAC_TXC_POS) -#define EMAC_TXC_UMSK (~(((1U << EMAC_TXC_LEN) - 1) << EMAC_TXC_POS)) -#define EMAC_RXC EMAC_RXC -#define EMAC_RXC_POS (6U) -#define EMAC_RXC_LEN (1U) -#define EMAC_RXC_MSK (((1U << EMAC_RXC_LEN) - 1) << EMAC_RXC_POS) -#define EMAC_RXC_UMSK (~(((1U << EMAC_RXC_LEN) - 1) << EMAC_RXC_POS)) - -/* 0x8 : INT_MASK */ -#define EMAC_INT_MASK_OFFSET (0x8) -#define EMAC_TXB_M EMAC_TXB_M -#define EMAC_TXB_M_POS (0U) -#define EMAC_TXB_M_LEN (1U) -#define EMAC_TXB_M_MSK (((1U << EMAC_TXB_M_LEN) - 1) << EMAC_TXB_M_POS) -#define EMAC_TXB_M_UMSK (~(((1U << EMAC_TXB_M_LEN) - 1) << EMAC_TXB_M_POS)) -#define EMAC_TXE_M EMAC_TXE_M -#define EMAC_TXE_M_POS (1U) -#define EMAC_TXE_M_LEN (1U) -#define EMAC_TXE_M_MSK (((1U << EMAC_TXE_M_LEN) - 1) << EMAC_TXE_M_POS) -#define EMAC_TXE_M_UMSK (~(((1U << EMAC_TXE_M_LEN) - 1) << EMAC_TXE_M_POS)) -#define EMAC_RXB_M EMAC_RXB_M -#define EMAC_RXB_M_POS (2U) -#define EMAC_RXB_M_LEN (1U) -#define EMAC_RXB_M_MSK (((1U << EMAC_RXB_M_LEN) - 1) << EMAC_RXB_M_POS) -#define EMAC_RXB_M_UMSK (~(((1U << EMAC_RXB_M_LEN) - 1) << EMAC_RXB_M_POS)) -#define EMAC_RXE_M EMAC_RXE_M -#define EMAC_RXE_M_POS (3U) -#define EMAC_RXE_M_LEN (1U) -#define EMAC_RXE_M_MSK (((1U << EMAC_RXE_M_LEN) - 1) << EMAC_RXE_M_POS) -#define EMAC_RXE_M_UMSK (~(((1U << EMAC_RXE_M_LEN) - 1) << EMAC_RXE_M_POS)) -#define EMAC_BUSY_M EMAC_BUSY_M -#define EMAC_BUSY_M_POS (4U) -#define EMAC_BUSY_M_LEN (1U) -#define EMAC_BUSY_M_MSK (((1U << EMAC_BUSY_M_LEN) - 1) << EMAC_BUSY_M_POS) -#define EMAC_BUSY_M_UMSK (~(((1U << EMAC_BUSY_M_LEN) - 1) << EMAC_BUSY_M_POS)) -#define EMAC_TXC_M EMAC_TXC_M -#define EMAC_TXC_M_POS (5U) -#define EMAC_TXC_M_LEN (1U) -#define EMAC_TXC_M_MSK (((1U << EMAC_TXC_M_LEN) - 1) << EMAC_TXC_M_POS) -#define EMAC_TXC_M_UMSK (~(((1U << EMAC_TXC_M_LEN) - 1) << EMAC_TXC_M_POS)) -#define EMAC_RXC_M EMAC_RXC_M -#define EMAC_RXC_M_POS (6U) -#define EMAC_RXC_M_LEN (1U) -#define EMAC_RXC_M_MSK (((1U << EMAC_RXC_M_LEN) - 1) << EMAC_RXC_M_POS) -#define EMAC_RXC_M_UMSK (~(((1U << EMAC_RXC_M_LEN) - 1) << EMAC_RXC_M_POS)) - -/* 0xC : IPGT */ -#define EMAC_IPGT_OFFSET (0xC) -#define EMAC_IPGT EMAC_IPGT -#define EMAC_IPGT_POS (0U) -#define EMAC_IPGT_LEN (7U) -#define EMAC_IPGT_MSK (((1U << EMAC_IPGT_LEN) - 1) << EMAC_IPGT_POS) -#define EMAC_IPGT_UMSK (~(((1U << EMAC_IPGT_LEN) - 1) << EMAC_IPGT_POS)) - -/* 0x18 : PACKETLEN */ -#define EMAC_PACKETLEN_OFFSET (0x18) -#define EMAC_MAXFL EMAC_MAXFL -#define EMAC_MAXFL_POS (0U) -#define EMAC_MAXFL_LEN (16U) -#define EMAC_MAXFL_MSK (((1U << EMAC_MAXFL_LEN) - 1) << EMAC_MAXFL_POS) -#define EMAC_MAXFL_UMSK (~(((1U << EMAC_MAXFL_LEN) - 1) << EMAC_MAXFL_POS)) -#define EMAC_MINFL EMAC_MINFL -#define EMAC_MINFL_POS (16U) -#define EMAC_MINFL_LEN (16U) -#define EMAC_MINFL_MSK (((1U << EMAC_MINFL_LEN) - 1) << EMAC_MINFL_POS) -#define EMAC_MINFL_UMSK (~(((1U << EMAC_MINFL_LEN) - 1) << EMAC_MINFL_POS)) - -/* 0x1C : COLLCONFIG */ -#define EMAC_COLLCONFIG_OFFSET (0x1C) -#define EMAC_COLLVALID EMAC_COLLVALID -#define EMAC_COLLVALID_POS (0U) -#define EMAC_COLLVALID_LEN (6U) -#define EMAC_COLLVALID_MSK (((1U << EMAC_COLLVALID_LEN) - 1) << EMAC_COLLVALID_POS) -#define EMAC_COLLVALID_UMSK (~(((1U << EMAC_COLLVALID_LEN) - 1) << EMAC_COLLVALID_POS)) -#define EMAC_MAXRET EMAC_MAXRET -#define EMAC_MAXRET_POS (16U) -#define EMAC_MAXRET_LEN (4U) -#define EMAC_MAXRET_MSK (((1U << EMAC_MAXRET_LEN) - 1) << EMAC_MAXRET_POS) -#define EMAC_MAXRET_UMSK (~(((1U << EMAC_MAXRET_LEN) - 1) << EMAC_MAXRET_POS)) - -/* 0x20 : TX_BD_NUM */ -#define EMAC_TX_BD_NUM_OFFSET (0x20) -#define EMAC_TXBDNUM EMAC_TXBDNUM -#define EMAC_TXBDNUM_POS (0U) -#define EMAC_TXBDNUM_LEN (8U) -#define EMAC_TXBDNUM_MSK (((1U << EMAC_TXBDNUM_LEN) - 1) << EMAC_TXBDNUM_POS) -#define EMAC_TXBDNUM_UMSK (~(((1U << EMAC_TXBDNUM_LEN) - 1) << EMAC_TXBDNUM_POS)) -#define EMAC_TXBDPTR EMAC_TXBDPTR -#define EMAC_TXBDPTR_POS (16U) -#define EMAC_TXBDPTR_LEN (7U) -#define EMAC_TXBDPTR_MSK (((1U << EMAC_TXBDPTR_LEN) - 1) << EMAC_TXBDPTR_POS) -#define EMAC_TXBDPTR_UMSK (~(((1U << EMAC_TXBDPTR_LEN) - 1) << EMAC_TXBDPTR_POS)) -#define EMAC_RXBDPTR EMAC_RXBDPTR -#define EMAC_RXBDPTR_POS (24U) -#define EMAC_RXBDPTR_LEN (7U) -#define EMAC_RXBDPTR_MSK (((1U << EMAC_RXBDPTR_LEN) - 1) << EMAC_RXBDPTR_POS) -#define EMAC_RXBDPTR_UMSK (~(((1U << EMAC_RXBDPTR_LEN) - 1) << EMAC_RXBDPTR_POS)) - -/* 0x28 : MIIMODE */ -#define EMAC_MIIMODE_OFFSET (0x28) -#define EMAC_CLKDIV EMAC_CLKDIV -#define EMAC_CLKDIV_POS (0U) -#define EMAC_CLKDIV_LEN (8U) -#define EMAC_CLKDIV_MSK (((1U << EMAC_CLKDIV_LEN) - 1) << EMAC_CLKDIV_POS) -#define EMAC_CLKDIV_UMSK (~(((1U << EMAC_CLKDIV_LEN) - 1) << EMAC_CLKDIV_POS)) -#define EMAC_MIINOPRE EMAC_MIINOPRE -#define EMAC_MIINOPRE_POS (8U) -#define EMAC_MIINOPRE_LEN (1U) -#define EMAC_MIINOPRE_MSK (((1U << EMAC_MIINOPRE_LEN) - 1) << EMAC_MIINOPRE_POS) -#define EMAC_MIINOPRE_UMSK (~(((1U << EMAC_MIINOPRE_LEN) - 1) << EMAC_MIINOPRE_POS)) - -/* 0x2C : MIICOMMAND */ -#define EMAC_MIICOMMAND_OFFSET (0x2C) -#define EMAC_SCANSTAT EMAC_SCANSTAT -#define EMAC_SCANSTAT_POS (0U) -#define EMAC_SCANSTAT_LEN (1U) -#define EMAC_SCANSTAT_MSK (((1U << EMAC_SCANSTAT_LEN) - 1) << EMAC_SCANSTAT_POS) -#define EMAC_SCANSTAT_UMSK (~(((1U << EMAC_SCANSTAT_LEN) - 1) << EMAC_SCANSTAT_POS)) -#define EMAC_RSTAT EMAC_RSTAT -#define EMAC_RSTAT_POS (1U) -#define EMAC_RSTAT_LEN (1U) -#define EMAC_RSTAT_MSK (((1U << EMAC_RSTAT_LEN) - 1) << EMAC_RSTAT_POS) -#define EMAC_RSTAT_UMSK (~(((1U << EMAC_RSTAT_LEN) - 1) << EMAC_RSTAT_POS)) -#define EMAC_WCTRLDATA EMAC_WCTRLDATA -#define EMAC_WCTRLDATA_POS (2U) -#define EMAC_WCTRLDATA_LEN (1U) -#define EMAC_WCTRLDATA_MSK (((1U << EMAC_WCTRLDATA_LEN) - 1) << EMAC_WCTRLDATA_POS) -#define EMAC_WCTRLDATA_UMSK (~(((1U << EMAC_WCTRLDATA_LEN) - 1) << EMAC_WCTRLDATA_POS)) - -/* 0x30 : MIIADDRESS */ -#define EMAC_MIIADDRESS_OFFSET (0x30) -#define EMAC_FIAD EMAC_FIAD -#define EMAC_FIAD_POS (0U) -#define EMAC_FIAD_LEN (5U) -#define EMAC_FIAD_MSK (((1U << EMAC_FIAD_LEN) - 1) << EMAC_FIAD_POS) -#define EMAC_FIAD_UMSK (~(((1U << EMAC_FIAD_LEN) - 1) << EMAC_FIAD_POS)) -#define EMAC_RGAD EMAC_RGAD -#define EMAC_RGAD_POS (8U) -#define EMAC_RGAD_LEN (5U) -#define EMAC_RGAD_MSK (((1U << EMAC_RGAD_LEN) - 1) << EMAC_RGAD_POS) -#define EMAC_RGAD_UMSK (~(((1U << EMAC_RGAD_LEN) - 1) << EMAC_RGAD_POS)) - -/* 0x34 : MIITX_DATA */ -#define EMAC_MIITX_DATA_OFFSET (0x34) -#define EMAC_CTRLDATA EMAC_CTRLDATA -#define EMAC_CTRLDATA_POS (0U) -#define EMAC_CTRLDATA_LEN (16U) -#define EMAC_CTRLDATA_MSK (((1U << EMAC_CTRLDATA_LEN) - 1) << EMAC_CTRLDATA_POS) -#define EMAC_CTRLDATA_UMSK (~(((1U << EMAC_CTRLDATA_LEN) - 1) << EMAC_CTRLDATA_POS)) - -/* 0x38 : MIIRX_DATA */ -#define EMAC_MIIRX_DATA_OFFSET (0x38) -#define EMAC_PRSD EMAC_PRSD -#define EMAC_PRSD_POS (0U) -#define EMAC_PRSD_LEN (16U) -#define EMAC_PRSD_MSK (((1U << EMAC_PRSD_LEN) - 1) << EMAC_PRSD_POS) -#define EMAC_PRSD_UMSK (~(((1U << EMAC_PRSD_LEN) - 1) << EMAC_PRSD_POS)) - -/* 0x3C : MIISTATUS */ -#define EMAC_MIISTATUS_OFFSET (0x3C) -#define EMAC_MIIM_LINKFAIL EMAC_MIIM_LINKFAIL -#define EMAC_MIIM_LINKFAIL_POS (0U) -#define EMAC_MIIM_LINKFAIL_LEN (1U) -#define EMAC_MIIM_LINKFAIL_MSK (((1U << EMAC_MIIM_LINKFAIL_LEN) - 1) << EMAC_MIIM_LINKFAIL_POS) -#define EMAC_MIIM_LINKFAIL_UMSK (~(((1U << EMAC_MIIM_LINKFAIL_LEN) - 1) << EMAC_MIIM_LINKFAIL_POS)) -#define EMAC_MIIM_BUSY EMAC_MIIM_BUSY -#define EMAC_MIIM_BUSY_POS (1U) -#define EMAC_MIIM_BUSY_LEN (1U) -#define EMAC_MIIM_BUSY_MSK (((1U << EMAC_MIIM_BUSY_LEN) - 1) << EMAC_MIIM_BUSY_POS) -#define EMAC_MIIM_BUSY_UMSK (~(((1U << EMAC_MIIM_BUSY_LEN) - 1) << EMAC_MIIM_BUSY_POS)) - -/* 0x40 : MAC_ADDR0 */ -#define EMAC_MAC_ADDR0_OFFSET (0x40) -#define EMAC_MAC_B5 EMAC_MAC_B5 -#define EMAC_MAC_B5_POS (0U) -#define EMAC_MAC_B5_LEN (8U) -#define EMAC_MAC_B5_MSK (((1U << EMAC_MAC_B5_LEN) - 1) << EMAC_MAC_B5_POS) -#define EMAC_MAC_B5_UMSK (~(((1U << EMAC_MAC_B5_LEN) - 1) << EMAC_MAC_B5_POS)) -#define EMAC_MAC_B4 EMAC_MAC_B4 -#define EMAC_MAC_B4_POS (8U) -#define EMAC_MAC_B4_LEN (8U) -#define EMAC_MAC_B4_MSK (((1U << EMAC_MAC_B4_LEN) - 1) << EMAC_MAC_B4_POS) -#define EMAC_MAC_B4_UMSK (~(((1U << EMAC_MAC_B4_LEN) - 1) << EMAC_MAC_B4_POS)) -#define EMAC_MAC_B3 EMAC_MAC_B3 -#define EMAC_MAC_B3_POS (16U) -#define EMAC_MAC_B3_LEN (8U) -#define EMAC_MAC_B3_MSK (((1U << EMAC_MAC_B3_LEN) - 1) << EMAC_MAC_B3_POS) -#define EMAC_MAC_B3_UMSK (~(((1U << EMAC_MAC_B3_LEN) - 1) << EMAC_MAC_B3_POS)) -#define EMAC_MAC_B2 EMAC_MAC_B2 -#define EMAC_MAC_B2_POS (24U) -#define EMAC_MAC_B2_LEN (8U) -#define EMAC_MAC_B2_MSK (((1U << EMAC_MAC_B2_LEN) - 1) << EMAC_MAC_B2_POS) -#define EMAC_MAC_B2_UMSK (~(((1U << EMAC_MAC_B2_LEN) - 1) << EMAC_MAC_B2_POS)) - -/* 0x44 : MAC_ADDR1 */ -#define EMAC_MAC_ADDR1_OFFSET (0x44) -#define EMAC_MAC_B1 EMAC_MAC_B1 -#define EMAC_MAC_B1_POS (0U) -#define EMAC_MAC_B1_LEN (8U) -#define EMAC_MAC_B1_MSK (((1U << EMAC_MAC_B1_LEN) - 1) << EMAC_MAC_B1_POS) -#define EMAC_MAC_B1_UMSK (~(((1U << EMAC_MAC_B1_LEN) - 1) << EMAC_MAC_B1_POS)) -#define EMAC_MAC_B0 EMAC_MAC_B0 -#define EMAC_MAC_B0_POS (8U) -#define EMAC_MAC_B0_LEN (8U) -#define EMAC_MAC_B0_MSK (((1U << EMAC_MAC_B0_LEN) - 1) << EMAC_MAC_B0_POS) -#define EMAC_MAC_B0_UMSK (~(((1U << EMAC_MAC_B0_LEN) - 1) << EMAC_MAC_B0_POS)) - -/* 0x48 : HASH0_ADDR */ -#define EMAC_HASH0_ADDR_OFFSET (0x48) -#define EMAC_HASH0 EMAC_HASH0 -#define EMAC_HASH0_POS (0U) -#define EMAC_HASH0_LEN (32U) -#define EMAC_HASH0_MSK (((1U << EMAC_HASH0_LEN) - 1) << EMAC_HASH0_POS) -#define EMAC_HASH0_UMSK (~(((1U << EMAC_HASH0_LEN) - 1) << EMAC_HASH0_POS)) - -/* 0x4C : HASH1_ADDR */ -#define EMAC_HASH1_ADDR_OFFSET (0x4C) -#define EMAC_HASH1 EMAC_HASH1 -#define EMAC_HASH1_POS (0U) -#define EMAC_HASH1_LEN (32U) -#define EMAC_HASH1_MSK (((1U << EMAC_HASH1_LEN) - 1) << EMAC_HASH1_POS) -#define EMAC_HASH1_UMSK (~(((1U << EMAC_HASH1_LEN) - 1) << EMAC_HASH1_POS)) - -/* 0x50 : TXCTRL */ -#define EMAC_TXCTRL_OFFSET (0x50) -#define EMAC_TXPAUSETV EMAC_TXPAUSETV -#define EMAC_TXPAUSETV_POS (0U) -#define EMAC_TXPAUSETV_LEN (16U) -#define EMAC_TXPAUSETV_MSK (((1U << EMAC_TXPAUSETV_LEN) - 1) << EMAC_TXPAUSETV_POS) -#define EMAC_TXPAUSETV_UMSK (~(((1U << EMAC_TXPAUSETV_LEN) - 1) << EMAC_TXPAUSETV_POS)) -#define EMAC_TXPAUSERQ EMAC_TXPAUSERQ -#define EMAC_TXPAUSERQ_POS (16U) -#define EMAC_TXPAUSERQ_LEN (1U) -#define EMAC_TXPAUSERQ_MSK (((1U << EMAC_TXPAUSERQ_LEN) - 1) << EMAC_TXPAUSERQ_POS) -#define EMAC_TXPAUSERQ_UMSK (~(((1U << EMAC_TXPAUSERQ_LEN) - 1) << EMAC_TXPAUSERQ_POS)) - -struct emac_reg { - /* 0x0 : MODE */ - union { - struct { - uint32_t RXEN : 1; /* [ 0], r/w, 0x0 */ - uint32_t TXEN : 1; /* [ 1], r/w, 0x0 */ - uint32_t NOPRE : 1; /* [ 2], r/w, 0x0 */ - uint32_t BRO : 1; /* [ 3], r/w, 0x1 */ - uint32_t rsvd_4 : 1; /* [ 4], rsvd, 0x0 */ - uint32_t PRO : 1; /* [ 5], r/w, 0x0 */ - uint32_t IFG : 1; /* [ 6], r/w, 0x0 */ - uint32_t rsvd_9_7 : 3; /* [ 9: 7], rsvd, 0x0 */ - uint32_t FULLD : 1; /* [ 10], r/w, 0x0 */ - uint32_t rsvd_12_11 : 2; /* [12:11], rsvd, 0x0 */ - uint32_t CRCEN : 1; /* [ 13], r/w, 0x1 */ - uint32_t HUGEN : 1; /* [ 14], r/w, 0x0 */ - uint32_t PAD : 1; /* [ 15], r/w, 0x1 */ - uint32_t RECSMALL : 1; /* [ 16], r/w, 0x0 */ - uint32_t RMII_EN : 1; /* [ 17], r/w, 0x0 */ - uint32_t rsvd_23_18 : 6; /* [23:18], rsvd, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } MODE; - - /* 0x4 : INT_SOURCE */ - union { - struct { - uint32_t TXB : 1; /* [ 0], r/w, 0x0 */ - uint32_t TXE : 1; /* [ 1], r/w, 0x0 */ - uint32_t RXB : 1; /* [ 2], r/w, 0x0 */ - uint32_t RXE : 1; /* [ 3], r/w, 0x0 */ - uint32_t BUSY : 1; /* [ 4], r/w, 0x0 */ - uint32_t TXC : 1; /* [ 5], r/w, 0x0 */ - uint32_t RXC : 1; /* [ 6], r/w, 0x0 */ - uint32_t reserved_7_31 : 25; /* [31: 7], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } INT_SOURCE; - - /* 0x8 : INT_MASK */ - union { - struct { - uint32_t TXB_M : 1; /* [ 0], r/w, 0x1 */ - uint32_t TXE_M : 1; /* [ 1], r/w, 0x1 */ - uint32_t RXB_M : 1; /* [ 2], r/w, 0x1 */ - uint32_t RXE_M : 1; /* [ 3], r/w, 0x1 */ - uint32_t BUSY_M : 1; /* [ 4], r/w, 0x1 */ - uint32_t TXC_M : 1; /* [ 5], r/w, 0x1 */ - uint32_t RXC_M : 1; /* [ 6], r/w, 0x1 */ - uint32_t reserved_7_31 : 25; /* [31: 7], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } INT_MASK; - - /* 0xC : IPGT */ - union { - struct { - uint32_t IPGT : 7; /* [ 6: 0], r/w, 0x18 */ - uint32_t reserved_7_31 : 25; /* [31: 7], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } IPGT; - - /* 0x10 reserved */ - uint8_t RESERVED0x10[8]; - - /* 0x18 : PACKETLEN */ - union { - struct { - uint32_t MAXFL : 16; /* [15: 0], r/w, 0x600 */ - uint32_t MINFL : 16; /* [31:16], r/w, 0x40 */ - } BF; - uint32_t WORD; - } PACKETLEN; - - /* 0x1C : COLLCONFIG */ - union { - struct { - uint32_t COLLVALID : 6; /* [ 5: 0], r/w, 0x3f */ - uint32_t reserved_6_15 : 10; /* [15: 6], rsvd, 0x0 */ - uint32_t MAXRET : 4; /* [19:16], r/w, 0xf */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } COLLCONFIG; - - /* 0x20 : TX_BD_NUM */ - union { - struct { - uint32_t TXBDNUM : 8; /* [ 7: 0], r/w, 0x40 */ - uint32_t reserved_8_15 : 8; /* [15: 8], rsvd, 0x0 */ - uint32_t TXBDPTR : 7; /* [22:16], r, 0x0 */ - uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */ - uint32_t RXBDPTR : 7; /* [30:24], r, 0x0 */ - uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } TX_BD_NUM; - - /* 0x24 reserved */ - uint8_t RESERVED0x24[4]; - - /* 0x28 : MIIMODE */ - union { - struct { - uint32_t CLKDIV : 8; /* [ 7: 0], r/w, 0x64 */ - uint32_t MIINOPRE : 1; /* [ 8], r/w, 0x0 */ - uint32_t reserved_9_31 : 23; /* [31: 9], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } MIIMODE; - - /* 0x2C : MIICOMMAND */ - union { - struct { - uint32_t SCANSTAT : 1; /* [ 0], r/w, 0x0 */ - uint32_t RSTAT : 1; /* [ 1], r/w, 0x0 */ - uint32_t WCTRLDATA : 1; /* [ 2], r/w, 0x0 */ - uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } MIICOMMAND; - - /* 0x30 : MIIADDRESS */ - union { - struct { - uint32_t FIAD : 5; /* [ 4: 0], r/w, 0x0 */ - uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ - uint32_t RGAD : 5; /* [12: 8], r/w, 0x0 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } MIIADDRESS; - - /* 0x34 : MIITX_DATA */ - union { - struct { - uint32_t CTRLDATA : 16; /* [15: 0], r/w, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } MIITX_DATA; - - /* 0x38 : MIIRX_DATA */ - union { - struct { - uint32_t PRSD : 16; /* [15: 0], r, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } MIIRX_DATA; - - /* 0x3C : MIISTATUS */ - union { - struct { - uint32_t MIIM_LINKFAIL : 1; /* [ 0], r, 0x0 */ - uint32_t MIIM_BUSY : 1; /* [ 1], r, 0x0 */ - uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } MIISTATUS; - - /* 0x40 : MAC_ADDR0 */ - union { - struct { - uint32_t MAC_B5 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t MAC_B4 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t MAC_B3 : 8; /* [23:16], r/w, 0x0 */ - uint32_t MAC_B2 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } MAC_ADDR0; - - /* 0x44 : MAC_ADDR1 */ - union { - struct { - uint32_t MAC_B1 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t MAC_B0 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } MAC_ADDR1; - - /* 0x48 : HASH0_ADDR */ - union { - struct { - uint32_t HASH0 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } HASH0_ADDR; - - /* 0x4C : HASH1_ADDR */ - union { - struct { - uint32_t HASH1 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } HASH1_ADDR; - - /* 0x50 : TXCTRL */ - union { - struct { - uint32_t TXPAUSETV : 16; /* [15: 0], r/w, 0x0 */ - uint32_t TXPAUSERQ : 1; /* [ 16], r/w, 0x0 */ - uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } TXCTRL; -}; - -typedef volatile struct emac_reg emac_reg_t; - -#endif /* __EMAC_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/emi_misc_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/emi_misc_reg.h deleted file mode 100644 index acb7637206..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/emi_misc_reg.h +++ /dev/null @@ -1,121 +0,0 @@ -/** - ****************************************************************************** - * @file emi_misc_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __EMI_MISC_REG_H__ -#define __EMI_MISC_REG_H__ - -#include "bl808.h" - -/* 0x00 : emi_bus_ctrl */ -#define EMI_MISC_EMI_BUS_CTRL_OFFSET (0x00) -#define EMI_MISC_RG_EMI_PCLK_FORCE_ON EMI_MISC_RG_EMI_PCLK_FORCE_ON -#define EMI_MISC_RG_EMI_PCLK_FORCE_ON_POS (0U) -#define EMI_MISC_RG_EMI_PCLK_FORCE_ON_LEN (16U) -#define EMI_MISC_RG_EMI_PCLK_FORCE_ON_MSK (((1U << EMI_MISC_RG_EMI_PCLK_FORCE_ON_LEN) - 1) << EMI_MISC_RG_EMI_PCLK_FORCE_ON_POS) -#define EMI_MISC_RG_EMI_PCLK_FORCE_ON_UMSK (~(((1U << EMI_MISC_RG_EMI_PCLK_FORCE_ON_LEN) - 1) << EMI_MISC_RG_EMI_PCLK_FORCE_ON_POS)) - -/* 0x04 : emi_bus_ctrl2 */ -#define EMI_MISC_EMI_BUS_CTRL2_OFFSET (0x04) -#define EMI_MISC_REG_SF_HARB_MODE EMI_MISC_REG_SF_HARB_MODE -#define EMI_MISC_REG_SF_HARB_MODE_POS (0U) -#define EMI_MISC_REG_SF_HARB_MODE_LEN (1U) -#define EMI_MISC_REG_SF_HARB_MODE_MSK (((1U << EMI_MISC_REG_SF_HARB_MODE_LEN) - 1) << EMI_MISC_REG_SF_HARB_MODE_POS) -#define EMI_MISC_REG_SF_HARB_MODE_UMSK (~(((1U << EMI_MISC_REG_SF_HARB_MODE_LEN) - 1) << EMI_MISC_REG_SF_HARB_MODE_POS)) - -/* 0x08 : emi_bus_thre */ -#define EMI_MISC_EMI_BUS_THRE_OFFSET (0x08) -#define EMI_MISC_REG_X_WTHRE_PB EMI_MISC_REG_X_WTHRE_PB -#define EMI_MISC_REG_X_WTHRE_PB_POS (0U) -#define EMI_MISC_REG_X_WTHRE_PB_LEN (2U) -#define EMI_MISC_REG_X_WTHRE_PB_MSK (((1U << EMI_MISC_REG_X_WTHRE_PB_LEN) - 1) << EMI_MISC_REG_X_WTHRE_PB_POS) -#define EMI_MISC_REG_X_WTHRE_PB_UMSK (~(((1U << EMI_MISC_REG_X_WTHRE_PB_LEN) - 1) << EMI_MISC_REG_X_WTHRE_PB_POS)) -#define EMI_MISC_REG_X_WTHRE_PA EMI_MISC_REG_X_WTHRE_PA -#define EMI_MISC_REG_X_WTHRE_PA_POS (2U) -#define EMI_MISC_REG_X_WTHRE_PA_LEN (2U) -#define EMI_MISC_REG_X_WTHRE_PA_MSK (((1U << EMI_MISC_REG_X_WTHRE_PA_LEN) - 1) << EMI_MISC_REG_X_WTHRE_PA_POS) -#define EMI_MISC_REG_X_WTHRE_PA_UMSK (~(((1U << EMI_MISC_REG_X_WTHRE_PA_LEN) - 1) << EMI_MISC_REG_X_WTHRE_PA_POS)) - -/* 0xFC : emi_misc_dummy */ -#define EMI_MISC_DUMMY_OFFSET (0xFC) -#define EMI_MISC_DUMMY_REG EMI_MISC_DUMMY_REG -#define EMI_MISC_DUMMY_REG_POS (0U) -#define EMI_MISC_DUMMY_REG_LEN (32U) -#define EMI_MISC_DUMMY_REG_MSK (((1U << EMI_MISC_DUMMY_REG_LEN) - 1) << EMI_MISC_DUMMY_REG_POS) -#define EMI_MISC_DUMMY_REG_UMSK (~(((1U << EMI_MISC_DUMMY_REG_LEN) - 1) << EMI_MISC_DUMMY_REG_POS)) - -struct emi_misc_reg { - /* 0x00 : emi_bus_ctrl */ - union { - struct { - uint32_t rg_emi_pclk_force_on : 16; /* [15: 0], r/w, 0xffff */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } emi_bus_ctrl; - - /* 0x04 : emi_bus_ctrl2 */ - union { - struct { - uint32_t reg_sf_harb_mode : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } emi_bus_ctrl2; - - /* 0x08 : emi_bus_thre */ - union { - struct { - uint32_t reg_x_wthre_pB : 2; /* [ 1: 0], r/w, 0x0 */ - uint32_t reg_x_wthre_pA : 2; /* [ 3: 2], r/w, 0x0 */ - uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } emi_bus_thre; - - /* 0xc reserved */ - uint8_t RESERVED0xc[240]; - - /* 0xFC : emi_misc_dummy */ - union { - struct { - uint32_t dummy_reg : 32; /* [31: 0], r/w, 0xffff0000 */ - } BF; - uint32_t WORD; - } emi_misc_dummy; -}; - -typedef volatile struct emi_misc_reg emi_misc_reg_t; - -#endif /* __EMI_MISC_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/i2c_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/i2c_reg.h deleted file mode 100644 index 0f498e244f..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/i2c_reg.h +++ /dev/null @@ -1,550 +0,0 @@ -/** - ****************************************************************************** - * @file i2c_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __I2C_REG_H__ -#define __I2C_REG_H__ - -#include "bl808.h" - -/* 0x0 : i2c_config */ -#define I2C_CONFIG_OFFSET (0x0) -#define I2C_CR_I2C_M_EN I2C_CR_I2C_M_EN -#define I2C_CR_I2C_M_EN_POS (0U) -#define I2C_CR_I2C_M_EN_LEN (1U) -#define I2C_CR_I2C_M_EN_MSK (((1U << I2C_CR_I2C_M_EN_LEN) - 1) << I2C_CR_I2C_M_EN_POS) -#define I2C_CR_I2C_M_EN_UMSK (~(((1U << I2C_CR_I2C_M_EN_LEN) - 1) << I2C_CR_I2C_M_EN_POS)) -#define I2C_CR_I2C_PKT_DIR I2C_CR_I2C_PKT_DIR -#define I2C_CR_I2C_PKT_DIR_POS (1U) -#define I2C_CR_I2C_PKT_DIR_LEN (1U) -#define I2C_CR_I2C_PKT_DIR_MSK (((1U << I2C_CR_I2C_PKT_DIR_LEN) - 1) << I2C_CR_I2C_PKT_DIR_POS) -#define I2C_CR_I2C_PKT_DIR_UMSK (~(((1U << I2C_CR_I2C_PKT_DIR_LEN) - 1) << I2C_CR_I2C_PKT_DIR_POS)) -#define I2C_CR_I2C_DEG_EN I2C_CR_I2C_DEG_EN -#define I2C_CR_I2C_DEG_EN_POS (2U) -#define I2C_CR_I2C_DEG_EN_LEN (1U) -#define I2C_CR_I2C_DEG_EN_MSK (((1U << I2C_CR_I2C_DEG_EN_LEN) - 1) << I2C_CR_I2C_DEG_EN_POS) -#define I2C_CR_I2C_DEG_EN_UMSK (~(((1U << I2C_CR_I2C_DEG_EN_LEN) - 1) << I2C_CR_I2C_DEG_EN_POS)) -#define I2C_CR_I2C_SCL_SYNC_EN I2C_CR_I2C_SCL_SYNC_EN -#define I2C_CR_I2C_SCL_SYNC_EN_POS (3U) -#define I2C_CR_I2C_SCL_SYNC_EN_LEN (1U) -#define I2C_CR_I2C_SCL_SYNC_EN_MSK (((1U << I2C_CR_I2C_SCL_SYNC_EN_LEN) - 1) << I2C_CR_I2C_SCL_SYNC_EN_POS) -#define I2C_CR_I2C_SCL_SYNC_EN_UMSK (~(((1U << I2C_CR_I2C_SCL_SYNC_EN_LEN) - 1) << I2C_CR_I2C_SCL_SYNC_EN_POS)) -#define I2C_CR_I2C_SUB_ADDR_EN I2C_CR_I2C_SUB_ADDR_EN -#define I2C_CR_I2C_SUB_ADDR_EN_POS (4U) -#define I2C_CR_I2C_SUB_ADDR_EN_LEN (1U) -#define I2C_CR_I2C_SUB_ADDR_EN_MSK (((1U << I2C_CR_I2C_SUB_ADDR_EN_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_EN_POS) -#define I2C_CR_I2C_SUB_ADDR_EN_UMSK (~(((1U << I2C_CR_I2C_SUB_ADDR_EN_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_EN_POS)) -#define I2C_CR_I2C_SUB_ADDR_BC I2C_CR_I2C_SUB_ADDR_BC -#define I2C_CR_I2C_SUB_ADDR_BC_POS (5U) -#define I2C_CR_I2C_SUB_ADDR_BC_LEN (2U) -#define I2C_CR_I2C_SUB_ADDR_BC_MSK (((1U << I2C_CR_I2C_SUB_ADDR_BC_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_BC_POS) -#define I2C_CR_I2C_SUB_ADDR_BC_UMSK (~(((1U << I2C_CR_I2C_SUB_ADDR_BC_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_BC_POS)) -#define I2C_CR_I2C_10B_ADDR_EN I2C_CR_I2C_10B_ADDR_EN -#define I2C_CR_I2C_10B_ADDR_EN_POS (7U) -#define I2C_CR_I2C_10B_ADDR_EN_LEN (1U) -#define I2C_CR_I2C_10B_ADDR_EN_MSK (((1U << I2C_CR_I2C_10B_ADDR_EN_LEN) - 1) << I2C_CR_I2C_10B_ADDR_EN_POS) -#define I2C_CR_I2C_10B_ADDR_EN_UMSK (~(((1U << I2C_CR_I2C_10B_ADDR_EN_LEN) - 1) << I2C_CR_I2C_10B_ADDR_EN_POS)) -#define I2C_CR_I2C_SLV_ADDR I2C_CR_I2C_SLV_ADDR -#define I2C_CR_I2C_SLV_ADDR_POS (8U) -#define I2C_CR_I2C_SLV_ADDR_LEN (10U) -#define I2C_CR_I2C_SLV_ADDR_MSK (((1U << I2C_CR_I2C_SLV_ADDR_LEN) - 1) << I2C_CR_I2C_SLV_ADDR_POS) -#define I2C_CR_I2C_SLV_ADDR_UMSK (~(((1U << I2C_CR_I2C_SLV_ADDR_LEN) - 1) << I2C_CR_I2C_SLV_ADDR_POS)) -#define I2C_CR_I2C_PKT_LEN I2C_CR_I2C_PKT_LEN -#define I2C_CR_I2C_PKT_LEN_POS (20U) -#define I2C_CR_I2C_PKT_LEN_LEN (8U) -#define I2C_CR_I2C_PKT_LEN_MSK (((1U << I2C_CR_I2C_PKT_LEN_LEN) - 1) << I2C_CR_I2C_PKT_LEN_POS) -#define I2C_CR_I2C_PKT_LEN_UMSK (~(((1U << I2C_CR_I2C_PKT_LEN_LEN) - 1) << I2C_CR_I2C_PKT_LEN_POS)) -#define I2C_CR_I2C_DEG_CNT I2C_CR_I2C_DEG_CNT -#define I2C_CR_I2C_DEG_CNT_POS (28U) -#define I2C_CR_I2C_DEG_CNT_LEN (4U) -#define I2C_CR_I2C_DEG_CNT_MSK (((1U << I2C_CR_I2C_DEG_CNT_LEN) - 1) << I2C_CR_I2C_DEG_CNT_POS) -#define I2C_CR_I2C_DEG_CNT_UMSK (~(((1U << I2C_CR_I2C_DEG_CNT_LEN) - 1) << I2C_CR_I2C_DEG_CNT_POS)) - -/* 0x4 : i2c_int_sts */ -#define I2C_INT_STS_OFFSET (0x4) -#define I2C_END_INT I2C_END_INT -#define I2C_END_INT_POS (0U) -#define I2C_END_INT_LEN (1U) -#define I2C_END_INT_MSK (((1U << I2C_END_INT_LEN) - 1) << I2C_END_INT_POS) -#define I2C_END_INT_UMSK (~(((1U << I2C_END_INT_LEN) - 1) << I2C_END_INT_POS)) -#define I2C_TXF_INT I2C_TXF_INT -#define I2C_TXF_INT_POS (1U) -#define I2C_TXF_INT_LEN (1U) -#define I2C_TXF_INT_MSK (((1U << I2C_TXF_INT_LEN) - 1) << I2C_TXF_INT_POS) -#define I2C_TXF_INT_UMSK (~(((1U << I2C_TXF_INT_LEN) - 1) << I2C_TXF_INT_POS)) -#define I2C_RXF_INT I2C_RXF_INT -#define I2C_RXF_INT_POS (2U) -#define I2C_RXF_INT_LEN (1U) -#define I2C_RXF_INT_MSK (((1U << I2C_RXF_INT_LEN) - 1) << I2C_RXF_INT_POS) -#define I2C_RXF_INT_UMSK (~(((1U << I2C_RXF_INT_LEN) - 1) << I2C_RXF_INT_POS)) -#define I2C_NAK_INT I2C_NAK_INT -#define I2C_NAK_INT_POS (3U) -#define I2C_NAK_INT_LEN (1U) -#define I2C_NAK_INT_MSK (((1U << I2C_NAK_INT_LEN) - 1) << I2C_NAK_INT_POS) -#define I2C_NAK_INT_UMSK (~(((1U << I2C_NAK_INT_LEN) - 1) << I2C_NAK_INT_POS)) -#define I2C_ARB_INT I2C_ARB_INT -#define I2C_ARB_INT_POS (4U) -#define I2C_ARB_INT_LEN (1U) -#define I2C_ARB_INT_MSK (((1U << I2C_ARB_INT_LEN) - 1) << I2C_ARB_INT_POS) -#define I2C_ARB_INT_UMSK (~(((1U << I2C_ARB_INT_LEN) - 1) << I2C_ARB_INT_POS)) -#define I2C_FER_INT I2C_FER_INT -#define I2C_FER_INT_POS (5U) -#define I2C_FER_INT_LEN (1U) -#define I2C_FER_INT_MSK (((1U << I2C_FER_INT_LEN) - 1) << I2C_FER_INT_POS) -#define I2C_FER_INT_UMSK (~(((1U << I2C_FER_INT_LEN) - 1) << I2C_FER_INT_POS)) -#define I2C_CR_I2C_END_MASK I2C_CR_I2C_END_MASK -#define I2C_CR_I2C_END_MASK_POS (8U) -#define I2C_CR_I2C_END_MASK_LEN (1U) -#define I2C_CR_I2C_END_MASK_MSK (((1U << I2C_CR_I2C_END_MASK_LEN) - 1) << I2C_CR_I2C_END_MASK_POS) -#define I2C_CR_I2C_END_MASK_UMSK (~(((1U << I2C_CR_I2C_END_MASK_LEN) - 1) << I2C_CR_I2C_END_MASK_POS)) -#define I2C_CR_I2C_TXF_MASK I2C_CR_I2C_TXF_MASK -#define I2C_CR_I2C_TXF_MASK_POS (9U) -#define I2C_CR_I2C_TXF_MASK_LEN (1U) -#define I2C_CR_I2C_TXF_MASK_MSK (((1U << I2C_CR_I2C_TXF_MASK_LEN) - 1) << I2C_CR_I2C_TXF_MASK_POS) -#define I2C_CR_I2C_TXF_MASK_UMSK (~(((1U << I2C_CR_I2C_TXF_MASK_LEN) - 1) << I2C_CR_I2C_TXF_MASK_POS)) -#define I2C_CR_I2C_RXF_MASK I2C_CR_I2C_RXF_MASK -#define I2C_CR_I2C_RXF_MASK_POS (10U) -#define I2C_CR_I2C_RXF_MASK_LEN (1U) -#define I2C_CR_I2C_RXF_MASK_MSK (((1U << I2C_CR_I2C_RXF_MASK_LEN) - 1) << I2C_CR_I2C_RXF_MASK_POS) -#define I2C_CR_I2C_RXF_MASK_UMSK (~(((1U << I2C_CR_I2C_RXF_MASK_LEN) - 1) << I2C_CR_I2C_RXF_MASK_POS)) -#define I2C_CR_I2C_NAK_MASK I2C_CR_I2C_NAK_MASK -#define I2C_CR_I2C_NAK_MASK_POS (11U) -#define I2C_CR_I2C_NAK_MASK_LEN (1U) -#define I2C_CR_I2C_NAK_MASK_MSK (((1U << I2C_CR_I2C_NAK_MASK_LEN) - 1) << I2C_CR_I2C_NAK_MASK_POS) -#define I2C_CR_I2C_NAK_MASK_UMSK (~(((1U << I2C_CR_I2C_NAK_MASK_LEN) - 1) << I2C_CR_I2C_NAK_MASK_POS)) -#define I2C_CR_I2C_ARB_MASK I2C_CR_I2C_ARB_MASK -#define I2C_CR_I2C_ARB_MASK_POS (12U) -#define I2C_CR_I2C_ARB_MASK_LEN (1U) -#define I2C_CR_I2C_ARB_MASK_MSK (((1U << I2C_CR_I2C_ARB_MASK_LEN) - 1) << I2C_CR_I2C_ARB_MASK_POS) -#define I2C_CR_I2C_ARB_MASK_UMSK (~(((1U << I2C_CR_I2C_ARB_MASK_LEN) - 1) << I2C_CR_I2C_ARB_MASK_POS)) -#define I2C_CR_I2C_FER_MASK I2C_CR_I2C_FER_MASK -#define I2C_CR_I2C_FER_MASK_POS (13U) -#define I2C_CR_I2C_FER_MASK_LEN (1U) -#define I2C_CR_I2C_FER_MASK_MSK (((1U << I2C_CR_I2C_FER_MASK_LEN) - 1) << I2C_CR_I2C_FER_MASK_POS) -#define I2C_CR_I2C_FER_MASK_UMSK (~(((1U << I2C_CR_I2C_FER_MASK_LEN) - 1) << I2C_CR_I2C_FER_MASK_POS)) -#define I2C_CR_I2C_END_CLR I2C_CR_I2C_END_CLR -#define I2C_CR_I2C_END_CLR_POS (16U) -#define I2C_CR_I2C_END_CLR_LEN (1U) -#define I2C_CR_I2C_END_CLR_MSK (((1U << I2C_CR_I2C_END_CLR_LEN) - 1) << I2C_CR_I2C_END_CLR_POS) -#define I2C_CR_I2C_END_CLR_UMSK (~(((1U << I2C_CR_I2C_END_CLR_LEN) - 1) << I2C_CR_I2C_END_CLR_POS)) -#define I2C_CR_I2C_NAK_CLR I2C_CR_I2C_NAK_CLR -#define I2C_CR_I2C_NAK_CLR_POS (19U) -#define I2C_CR_I2C_NAK_CLR_LEN (1U) -#define I2C_CR_I2C_NAK_CLR_MSK (((1U << I2C_CR_I2C_NAK_CLR_LEN) - 1) << I2C_CR_I2C_NAK_CLR_POS) -#define I2C_CR_I2C_NAK_CLR_UMSK (~(((1U << I2C_CR_I2C_NAK_CLR_LEN) - 1) << I2C_CR_I2C_NAK_CLR_POS)) -#define I2C_CR_I2C_ARB_CLR I2C_CR_I2C_ARB_CLR -#define I2C_CR_I2C_ARB_CLR_POS (20U) -#define I2C_CR_I2C_ARB_CLR_LEN (1U) -#define I2C_CR_I2C_ARB_CLR_MSK (((1U << I2C_CR_I2C_ARB_CLR_LEN) - 1) << I2C_CR_I2C_ARB_CLR_POS) -#define I2C_CR_I2C_ARB_CLR_UMSK (~(((1U << I2C_CR_I2C_ARB_CLR_LEN) - 1) << I2C_CR_I2C_ARB_CLR_POS)) -#define I2C_CR_I2C_END_EN I2C_CR_I2C_END_EN -#define I2C_CR_I2C_END_EN_POS (24U) -#define I2C_CR_I2C_END_EN_LEN (1U) -#define I2C_CR_I2C_END_EN_MSK (((1U << I2C_CR_I2C_END_EN_LEN) - 1) << I2C_CR_I2C_END_EN_POS) -#define I2C_CR_I2C_END_EN_UMSK (~(((1U << I2C_CR_I2C_END_EN_LEN) - 1) << I2C_CR_I2C_END_EN_POS)) -#define I2C_CR_I2C_TXF_EN I2C_CR_I2C_TXF_EN -#define I2C_CR_I2C_TXF_EN_POS (25U) -#define I2C_CR_I2C_TXF_EN_LEN (1U) -#define I2C_CR_I2C_TXF_EN_MSK (((1U << I2C_CR_I2C_TXF_EN_LEN) - 1) << I2C_CR_I2C_TXF_EN_POS) -#define I2C_CR_I2C_TXF_EN_UMSK (~(((1U << I2C_CR_I2C_TXF_EN_LEN) - 1) << I2C_CR_I2C_TXF_EN_POS)) -#define I2C_CR_I2C_RXF_EN I2C_CR_I2C_RXF_EN -#define I2C_CR_I2C_RXF_EN_POS (26U) -#define I2C_CR_I2C_RXF_EN_LEN (1U) -#define I2C_CR_I2C_RXF_EN_MSK (((1U << I2C_CR_I2C_RXF_EN_LEN) - 1) << I2C_CR_I2C_RXF_EN_POS) -#define I2C_CR_I2C_RXF_EN_UMSK (~(((1U << I2C_CR_I2C_RXF_EN_LEN) - 1) << I2C_CR_I2C_RXF_EN_POS)) -#define I2C_CR_I2C_NAK_EN I2C_CR_I2C_NAK_EN -#define I2C_CR_I2C_NAK_EN_POS (27U) -#define I2C_CR_I2C_NAK_EN_LEN (1U) -#define I2C_CR_I2C_NAK_EN_MSK (((1U << I2C_CR_I2C_NAK_EN_LEN) - 1) << I2C_CR_I2C_NAK_EN_POS) -#define I2C_CR_I2C_NAK_EN_UMSK (~(((1U << I2C_CR_I2C_NAK_EN_LEN) - 1) << I2C_CR_I2C_NAK_EN_POS)) -#define I2C_CR_I2C_ARB_EN I2C_CR_I2C_ARB_EN -#define I2C_CR_I2C_ARB_EN_POS (28U) -#define I2C_CR_I2C_ARB_EN_LEN (1U) -#define I2C_CR_I2C_ARB_EN_MSK (((1U << I2C_CR_I2C_ARB_EN_LEN) - 1) << I2C_CR_I2C_ARB_EN_POS) -#define I2C_CR_I2C_ARB_EN_UMSK (~(((1U << I2C_CR_I2C_ARB_EN_LEN) - 1) << I2C_CR_I2C_ARB_EN_POS)) -#define I2C_CR_I2C_FER_EN I2C_CR_I2C_FER_EN -#define I2C_CR_I2C_FER_EN_POS (29U) -#define I2C_CR_I2C_FER_EN_LEN (1U) -#define I2C_CR_I2C_FER_EN_MSK (((1U << I2C_CR_I2C_FER_EN_LEN) - 1) << I2C_CR_I2C_FER_EN_POS) -#define I2C_CR_I2C_FER_EN_UMSK (~(((1U << I2C_CR_I2C_FER_EN_LEN) - 1) << I2C_CR_I2C_FER_EN_POS)) - -/* 0x8 : i2c_sub_addr */ -#define I2C_SUB_ADDR_OFFSET (0x8) -#define I2C_CR_I2C_SUB_ADDR_B0 I2C_CR_I2C_SUB_ADDR_B0 -#define I2C_CR_I2C_SUB_ADDR_B0_POS (0U) -#define I2C_CR_I2C_SUB_ADDR_B0_LEN (8U) -#define I2C_CR_I2C_SUB_ADDR_B0_MSK (((1U << I2C_CR_I2C_SUB_ADDR_B0_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B0_POS) -#define I2C_CR_I2C_SUB_ADDR_B0_UMSK (~(((1U << I2C_CR_I2C_SUB_ADDR_B0_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B0_POS)) -#define I2C_CR_I2C_SUB_ADDR_B1 I2C_CR_I2C_SUB_ADDR_B1 -#define I2C_CR_I2C_SUB_ADDR_B1_POS (8U) -#define I2C_CR_I2C_SUB_ADDR_B1_LEN (8U) -#define I2C_CR_I2C_SUB_ADDR_B1_MSK (((1U << I2C_CR_I2C_SUB_ADDR_B1_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B1_POS) -#define I2C_CR_I2C_SUB_ADDR_B1_UMSK (~(((1U << I2C_CR_I2C_SUB_ADDR_B1_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B1_POS)) -#define I2C_CR_I2C_SUB_ADDR_B2 I2C_CR_I2C_SUB_ADDR_B2 -#define I2C_CR_I2C_SUB_ADDR_B2_POS (16U) -#define I2C_CR_I2C_SUB_ADDR_B2_LEN (8U) -#define I2C_CR_I2C_SUB_ADDR_B2_MSK (((1U << I2C_CR_I2C_SUB_ADDR_B2_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B2_POS) -#define I2C_CR_I2C_SUB_ADDR_B2_UMSK (~(((1U << I2C_CR_I2C_SUB_ADDR_B2_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B2_POS)) -#define I2C_CR_I2C_SUB_ADDR_B3 I2C_CR_I2C_SUB_ADDR_B3 -#define I2C_CR_I2C_SUB_ADDR_B3_POS (24U) -#define I2C_CR_I2C_SUB_ADDR_B3_LEN (8U) -#define I2C_CR_I2C_SUB_ADDR_B3_MSK (((1U << I2C_CR_I2C_SUB_ADDR_B3_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B3_POS) -#define I2C_CR_I2C_SUB_ADDR_B3_UMSK (~(((1U << I2C_CR_I2C_SUB_ADDR_B3_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B3_POS)) - -/* 0xC : i2c_bus_busy */ -#define I2C_BUS_BUSY_OFFSET (0xC) -#define I2C_STS_I2C_BUS_BUSY I2C_STS_I2C_BUS_BUSY -#define I2C_STS_I2C_BUS_BUSY_POS (0U) -#define I2C_STS_I2C_BUS_BUSY_LEN (1U) -#define I2C_STS_I2C_BUS_BUSY_MSK (((1U << I2C_STS_I2C_BUS_BUSY_LEN) - 1) << I2C_STS_I2C_BUS_BUSY_POS) -#define I2C_STS_I2C_BUS_BUSY_UMSK (~(((1U << I2C_STS_I2C_BUS_BUSY_LEN) - 1) << I2C_STS_I2C_BUS_BUSY_POS)) -#define I2C_CR_I2C_BUS_BUSY_CLR I2C_CR_I2C_BUS_BUSY_CLR -#define I2C_CR_I2C_BUS_BUSY_CLR_POS (1U) -#define I2C_CR_I2C_BUS_BUSY_CLR_LEN (1U) -#define I2C_CR_I2C_BUS_BUSY_CLR_MSK (((1U << I2C_CR_I2C_BUS_BUSY_CLR_LEN) - 1) << I2C_CR_I2C_BUS_BUSY_CLR_POS) -#define I2C_CR_I2C_BUS_BUSY_CLR_UMSK (~(((1U << I2C_CR_I2C_BUS_BUSY_CLR_LEN) - 1) << I2C_CR_I2C_BUS_BUSY_CLR_POS)) - -/* 0x10 : i2c_prd_start */ -#define I2C_PRD_START_OFFSET (0x10) -#define I2C_CR_I2C_PRD_S_PH_0 I2C_CR_I2C_PRD_S_PH_0 -#define I2C_CR_I2C_PRD_S_PH_0_POS (0U) -#define I2C_CR_I2C_PRD_S_PH_0_LEN (8U) -#define I2C_CR_I2C_PRD_S_PH_0_MSK (((1U << I2C_CR_I2C_PRD_S_PH_0_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_0_POS) -#define I2C_CR_I2C_PRD_S_PH_0_UMSK (~(((1U << I2C_CR_I2C_PRD_S_PH_0_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_0_POS)) -#define I2C_CR_I2C_PRD_S_PH_1 I2C_CR_I2C_PRD_S_PH_1 -#define I2C_CR_I2C_PRD_S_PH_1_POS (8U) -#define I2C_CR_I2C_PRD_S_PH_1_LEN (8U) -#define I2C_CR_I2C_PRD_S_PH_1_MSK (((1U << I2C_CR_I2C_PRD_S_PH_1_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_1_POS) -#define I2C_CR_I2C_PRD_S_PH_1_UMSK (~(((1U << I2C_CR_I2C_PRD_S_PH_1_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_1_POS)) -#define I2C_CR_I2C_PRD_S_PH_2 I2C_CR_I2C_PRD_S_PH_2 -#define I2C_CR_I2C_PRD_S_PH_2_POS (16U) -#define I2C_CR_I2C_PRD_S_PH_2_LEN (8U) -#define I2C_CR_I2C_PRD_S_PH_2_MSK (((1U << I2C_CR_I2C_PRD_S_PH_2_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_2_POS) -#define I2C_CR_I2C_PRD_S_PH_2_UMSK (~(((1U << I2C_CR_I2C_PRD_S_PH_2_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_2_POS)) -#define I2C_CR_I2C_PRD_S_PH_3 I2C_CR_I2C_PRD_S_PH_3 -#define I2C_CR_I2C_PRD_S_PH_3_POS (24U) -#define I2C_CR_I2C_PRD_S_PH_3_LEN (8U) -#define I2C_CR_I2C_PRD_S_PH_3_MSK (((1U << I2C_CR_I2C_PRD_S_PH_3_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_3_POS) -#define I2C_CR_I2C_PRD_S_PH_3_UMSK (~(((1U << I2C_CR_I2C_PRD_S_PH_3_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_3_POS)) - -/* 0x14 : i2c_prd_stop */ -#define I2C_PRD_STOP_OFFSET (0x14) -#define I2C_CR_I2C_PRD_P_PH_0 I2C_CR_I2C_PRD_P_PH_0 -#define I2C_CR_I2C_PRD_P_PH_0_POS (0U) -#define I2C_CR_I2C_PRD_P_PH_0_LEN (8U) -#define I2C_CR_I2C_PRD_P_PH_0_MSK (((1U << I2C_CR_I2C_PRD_P_PH_0_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_0_POS) -#define I2C_CR_I2C_PRD_P_PH_0_UMSK (~(((1U << I2C_CR_I2C_PRD_P_PH_0_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_0_POS)) -#define I2C_CR_I2C_PRD_P_PH_1 I2C_CR_I2C_PRD_P_PH_1 -#define I2C_CR_I2C_PRD_P_PH_1_POS (8U) -#define I2C_CR_I2C_PRD_P_PH_1_LEN (8U) -#define I2C_CR_I2C_PRD_P_PH_1_MSK (((1U << I2C_CR_I2C_PRD_P_PH_1_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_1_POS) -#define I2C_CR_I2C_PRD_P_PH_1_UMSK (~(((1U << I2C_CR_I2C_PRD_P_PH_1_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_1_POS)) -#define I2C_CR_I2C_PRD_P_PH_2 I2C_CR_I2C_PRD_P_PH_2 -#define I2C_CR_I2C_PRD_P_PH_2_POS (16U) -#define I2C_CR_I2C_PRD_P_PH_2_LEN (8U) -#define I2C_CR_I2C_PRD_P_PH_2_MSK (((1U << I2C_CR_I2C_PRD_P_PH_2_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_2_POS) -#define I2C_CR_I2C_PRD_P_PH_2_UMSK (~(((1U << I2C_CR_I2C_PRD_P_PH_2_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_2_POS)) -#define I2C_CR_I2C_PRD_P_PH_3 I2C_CR_I2C_PRD_P_PH_3 -#define I2C_CR_I2C_PRD_P_PH_3_POS (24U) -#define I2C_CR_I2C_PRD_P_PH_3_LEN (8U) -#define I2C_CR_I2C_PRD_P_PH_3_MSK (((1U << I2C_CR_I2C_PRD_P_PH_3_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_3_POS) -#define I2C_CR_I2C_PRD_P_PH_3_UMSK (~(((1U << I2C_CR_I2C_PRD_P_PH_3_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_3_POS)) - -/* 0x18 : i2c_prd_data */ -#define I2C_PRD_DATA_OFFSET (0x18) -#define I2C_CR_I2C_PRD_D_PH_0 I2C_CR_I2C_PRD_D_PH_0 -#define I2C_CR_I2C_PRD_D_PH_0_POS (0U) -#define I2C_CR_I2C_PRD_D_PH_0_LEN (8U) -#define I2C_CR_I2C_PRD_D_PH_0_MSK (((1U << I2C_CR_I2C_PRD_D_PH_0_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_0_POS) -#define I2C_CR_I2C_PRD_D_PH_0_UMSK (~(((1U << I2C_CR_I2C_PRD_D_PH_0_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_0_POS)) -#define I2C_CR_I2C_PRD_D_PH_1 I2C_CR_I2C_PRD_D_PH_1 -#define I2C_CR_I2C_PRD_D_PH_1_POS (8U) -#define I2C_CR_I2C_PRD_D_PH_1_LEN (8U) -#define I2C_CR_I2C_PRD_D_PH_1_MSK (((1U << I2C_CR_I2C_PRD_D_PH_1_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_1_POS) -#define I2C_CR_I2C_PRD_D_PH_1_UMSK (~(((1U << I2C_CR_I2C_PRD_D_PH_1_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_1_POS)) -#define I2C_CR_I2C_PRD_D_PH_2 I2C_CR_I2C_PRD_D_PH_2 -#define I2C_CR_I2C_PRD_D_PH_2_POS (16U) -#define I2C_CR_I2C_PRD_D_PH_2_LEN (8U) -#define I2C_CR_I2C_PRD_D_PH_2_MSK (((1U << I2C_CR_I2C_PRD_D_PH_2_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_2_POS) -#define I2C_CR_I2C_PRD_D_PH_2_UMSK (~(((1U << I2C_CR_I2C_PRD_D_PH_2_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_2_POS)) -#define I2C_CR_I2C_PRD_D_PH_3 I2C_CR_I2C_PRD_D_PH_3 -#define I2C_CR_I2C_PRD_D_PH_3_POS (24U) -#define I2C_CR_I2C_PRD_D_PH_3_LEN (8U) -#define I2C_CR_I2C_PRD_D_PH_3_MSK (((1U << I2C_CR_I2C_PRD_D_PH_3_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_3_POS) -#define I2C_CR_I2C_PRD_D_PH_3_UMSK (~(((1U << I2C_CR_I2C_PRD_D_PH_3_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_3_POS)) - -/* 0x80 : i2c_fifo_config_0 */ -#define I2C_FIFO_CONFIG_0_OFFSET (0x80) -#define I2C_DMA_TX_EN I2C_DMA_TX_EN -#define I2C_DMA_TX_EN_POS (0U) -#define I2C_DMA_TX_EN_LEN (1U) -#define I2C_DMA_TX_EN_MSK (((1U << I2C_DMA_TX_EN_LEN) - 1) << I2C_DMA_TX_EN_POS) -#define I2C_DMA_TX_EN_UMSK (~(((1U << I2C_DMA_TX_EN_LEN) - 1) << I2C_DMA_TX_EN_POS)) -#define I2C_DMA_RX_EN I2C_DMA_RX_EN -#define I2C_DMA_RX_EN_POS (1U) -#define I2C_DMA_RX_EN_LEN (1U) -#define I2C_DMA_RX_EN_MSK (((1U << I2C_DMA_RX_EN_LEN) - 1) << I2C_DMA_RX_EN_POS) -#define I2C_DMA_RX_EN_UMSK (~(((1U << I2C_DMA_RX_EN_LEN) - 1) << I2C_DMA_RX_EN_POS)) -#define I2C_TX_FIFO_CLR I2C_TX_FIFO_CLR -#define I2C_TX_FIFO_CLR_POS (2U) -#define I2C_TX_FIFO_CLR_LEN (1U) -#define I2C_TX_FIFO_CLR_MSK (((1U << I2C_TX_FIFO_CLR_LEN) - 1) << I2C_TX_FIFO_CLR_POS) -#define I2C_TX_FIFO_CLR_UMSK (~(((1U << I2C_TX_FIFO_CLR_LEN) - 1) << I2C_TX_FIFO_CLR_POS)) -#define I2C_RX_FIFO_CLR I2C_RX_FIFO_CLR -#define I2C_RX_FIFO_CLR_POS (3U) -#define I2C_RX_FIFO_CLR_LEN (1U) -#define I2C_RX_FIFO_CLR_MSK (((1U << I2C_RX_FIFO_CLR_LEN) - 1) << I2C_RX_FIFO_CLR_POS) -#define I2C_RX_FIFO_CLR_UMSK (~(((1U << I2C_RX_FIFO_CLR_LEN) - 1) << I2C_RX_FIFO_CLR_POS)) -#define I2C_TX_FIFO_OVERFLOW I2C_TX_FIFO_OVERFLOW -#define I2C_TX_FIFO_OVERFLOW_POS (4U) -#define I2C_TX_FIFO_OVERFLOW_LEN (1U) -#define I2C_TX_FIFO_OVERFLOW_MSK (((1U << I2C_TX_FIFO_OVERFLOW_LEN) - 1) << I2C_TX_FIFO_OVERFLOW_POS) -#define I2C_TX_FIFO_OVERFLOW_UMSK (~(((1U << I2C_TX_FIFO_OVERFLOW_LEN) - 1) << I2C_TX_FIFO_OVERFLOW_POS)) -#define I2C_TX_FIFO_UNDERFLOW I2C_TX_FIFO_UNDERFLOW -#define I2C_TX_FIFO_UNDERFLOW_POS (5U) -#define I2C_TX_FIFO_UNDERFLOW_LEN (1U) -#define I2C_TX_FIFO_UNDERFLOW_MSK (((1U << I2C_TX_FIFO_UNDERFLOW_LEN) - 1) << I2C_TX_FIFO_UNDERFLOW_POS) -#define I2C_TX_FIFO_UNDERFLOW_UMSK (~(((1U << I2C_TX_FIFO_UNDERFLOW_LEN) - 1) << I2C_TX_FIFO_UNDERFLOW_POS)) -#define I2C_RX_FIFO_OVERFLOW I2C_RX_FIFO_OVERFLOW -#define I2C_RX_FIFO_OVERFLOW_POS (6U) -#define I2C_RX_FIFO_OVERFLOW_LEN (1U) -#define I2C_RX_FIFO_OVERFLOW_MSK (((1U << I2C_RX_FIFO_OVERFLOW_LEN) - 1) << I2C_RX_FIFO_OVERFLOW_POS) -#define I2C_RX_FIFO_OVERFLOW_UMSK (~(((1U << I2C_RX_FIFO_OVERFLOW_LEN) - 1) << I2C_RX_FIFO_OVERFLOW_POS)) -#define I2C_RX_FIFO_UNDERFLOW I2C_RX_FIFO_UNDERFLOW -#define I2C_RX_FIFO_UNDERFLOW_POS (7U) -#define I2C_RX_FIFO_UNDERFLOW_LEN (1U) -#define I2C_RX_FIFO_UNDERFLOW_MSK (((1U << I2C_RX_FIFO_UNDERFLOW_LEN) - 1) << I2C_RX_FIFO_UNDERFLOW_POS) -#define I2C_RX_FIFO_UNDERFLOW_UMSK (~(((1U << I2C_RX_FIFO_UNDERFLOW_LEN) - 1) << I2C_RX_FIFO_UNDERFLOW_POS)) - -/* 0x84 : i2c_fifo_config_1 */ -#define I2C_FIFO_CONFIG_1_OFFSET (0x84) -#define I2C_TX_FIFO_CNT I2C_TX_FIFO_CNT -#define I2C_TX_FIFO_CNT_POS (0U) -#define I2C_TX_FIFO_CNT_LEN (2U) -#define I2C_TX_FIFO_CNT_MSK (((1U << I2C_TX_FIFO_CNT_LEN) - 1) << I2C_TX_FIFO_CNT_POS) -#define I2C_TX_FIFO_CNT_UMSK (~(((1U << I2C_TX_FIFO_CNT_LEN) - 1) << I2C_TX_FIFO_CNT_POS)) -#define I2C_RX_FIFO_CNT I2C_RX_FIFO_CNT -#define I2C_RX_FIFO_CNT_POS (8U) -#define I2C_RX_FIFO_CNT_LEN (2U) -#define I2C_RX_FIFO_CNT_MSK (((1U << I2C_RX_FIFO_CNT_LEN) - 1) << I2C_RX_FIFO_CNT_POS) -#define I2C_RX_FIFO_CNT_UMSK (~(((1U << I2C_RX_FIFO_CNT_LEN) - 1) << I2C_RX_FIFO_CNT_POS)) -#define I2C_TX_FIFO_TH I2C_TX_FIFO_TH -#define I2C_TX_FIFO_TH_POS (16U) -#define I2C_TX_FIFO_TH_LEN (1U) -#define I2C_TX_FIFO_TH_MSK (((1U << I2C_TX_FIFO_TH_LEN) - 1) << I2C_TX_FIFO_TH_POS) -#define I2C_TX_FIFO_TH_UMSK (~(((1U << I2C_TX_FIFO_TH_LEN) - 1) << I2C_TX_FIFO_TH_POS)) -#define I2C_RX_FIFO_TH I2C_RX_FIFO_TH -#define I2C_RX_FIFO_TH_POS (24U) -#define I2C_RX_FIFO_TH_LEN (1U) -#define I2C_RX_FIFO_TH_MSK (((1U << I2C_RX_FIFO_TH_LEN) - 1) << I2C_RX_FIFO_TH_POS) -#define I2C_RX_FIFO_TH_UMSK (~(((1U << I2C_RX_FIFO_TH_LEN) - 1) << I2C_RX_FIFO_TH_POS)) - -/* 0x88 : i2c_fifo_wdata */ -#define I2C_FIFO_WDATA_OFFSET (0x88) -#define I2C_FIFO_WDATA I2C_FIFO_WDATA -#define I2C_FIFO_WDATA_POS (0U) -#define I2C_FIFO_WDATA_LEN (32U) -#define I2C_FIFO_WDATA_MSK (((1U << I2C_FIFO_WDATA_LEN) - 1) << I2C_FIFO_WDATA_POS) -#define I2C_FIFO_WDATA_UMSK (~(((1U << I2C_FIFO_WDATA_LEN) - 1) << I2C_FIFO_WDATA_POS)) - -/* 0x8C : i2c_fifo_rdata */ -#define I2C_FIFO_RDATA_OFFSET (0x8C) -#define I2C_FIFO_RDATA I2C_FIFO_RDATA -#define I2C_FIFO_RDATA_POS (0U) -#define I2C_FIFO_RDATA_LEN (32U) -#define I2C_FIFO_RDATA_MSK (((1U << I2C_FIFO_RDATA_LEN) - 1) << I2C_FIFO_RDATA_POS) -#define I2C_FIFO_RDATA_UMSK (~(((1U << I2C_FIFO_RDATA_LEN) - 1) << I2C_FIFO_RDATA_POS)) - -struct i2c_reg { - /* 0x0 : i2c_config */ - union { - struct { - uint32_t cr_i2c_m_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t cr_i2c_pkt_dir : 1; /* [ 1], r/w, 0x1 */ - uint32_t cr_i2c_deg_en : 1; /* [ 2], r/w, 0x0 */ - uint32_t cr_i2c_scl_sync_en : 1; /* [ 3], r/w, 0x1 */ - uint32_t cr_i2c_sub_addr_en : 1; /* [ 4], r/w, 0x0 */ - uint32_t cr_i2c_sub_addr_bc : 2; /* [ 6: 5], r/w, 0x0 */ - uint32_t cr_i2c_10b_addr_en : 1; /* [ 7], r/w, 0x0 */ - uint32_t cr_i2c_slv_addr : 10; /* [17: 8], r/w, 0x0 */ - uint32_t reserved_18_19 : 2; /* [19:18], rsvd, 0x0 */ - uint32_t cr_i2c_pkt_len : 8; /* [27:20], r/w, 0x0 */ - uint32_t cr_i2c_deg_cnt : 4; /* [31:28], r/w, 0x0 */ - } BF; - uint32_t WORD; - } i2c_config; - - /* 0x4 : i2c_int_sts */ - union { - struct { - uint32_t i2c_end_int : 1; /* [ 0], r, 0x0 */ - uint32_t i2c_txf_int : 1; /* [ 1], r, 0x1 */ - uint32_t i2c_rxf_int : 1; /* [ 2], r, 0x0 */ - uint32_t i2c_nak_int : 1; /* [ 3], r, 0x0 */ - uint32_t i2c_arb_int : 1; /* [ 4], r, 0x0 */ - uint32_t i2c_fer_int : 1; /* [ 5], r, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t cr_i2c_end_mask : 1; /* [ 8], r/w, 0x1 */ - uint32_t cr_i2c_txf_mask : 1; /* [ 9], r/w, 0x1 */ - uint32_t cr_i2c_rxf_mask : 1; /* [ 10], r/w, 0x1 */ - uint32_t cr_i2c_nak_mask : 1; /* [ 11], r/w, 0x1 */ - uint32_t cr_i2c_arb_mask : 1; /* [ 12], r/w, 0x1 */ - uint32_t cr_i2c_fer_mask : 1; /* [ 13], r/w, 0x1 */ - uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ - uint32_t cr_i2c_end_clr : 1; /* [ 16], w1c, 0x0 */ - uint32_t rsvd_17 : 1; /* [ 17], rsvd, 0x0 */ - uint32_t rsvd_18 : 1; /* [ 18], rsvd, 0x0 */ - uint32_t cr_i2c_nak_clr : 1; /* [ 19], w1c, 0x0 */ - uint32_t cr_i2c_arb_clr : 1; /* [ 20], w1c, 0x0 */ - uint32_t rsvd_21 : 1; /* [ 21], rsvd, 0x0 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t cr_i2c_end_en : 1; /* [ 24], r/w, 0x1 */ - uint32_t cr_i2c_txf_en : 1; /* [ 25], r/w, 0x1 */ - uint32_t cr_i2c_rxf_en : 1; /* [ 26], r/w, 0x1 */ - uint32_t cr_i2c_nak_en : 1; /* [ 27], r/w, 0x1 */ - uint32_t cr_i2c_arb_en : 1; /* [ 28], r/w, 0x1 */ - uint32_t cr_i2c_fer_en : 1; /* [ 29], r/w, 0x1 */ - uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } i2c_int_sts; - - /* 0x8 : i2c_sub_addr */ - union { - struct { - uint32_t cr_i2c_sub_addr_b0 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t cr_i2c_sub_addr_b1 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t cr_i2c_sub_addr_b2 : 8; /* [23:16], r/w, 0x0 */ - uint32_t cr_i2c_sub_addr_b3 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } i2c_sub_addr; - - /* 0xC : i2c_bus_busy */ - union { - struct { - uint32_t sts_i2c_bus_busy : 1; /* [ 0], r, 0x0 */ - uint32_t cr_i2c_bus_busy_clr : 1; /* [ 1], w1c, 0x0 */ - uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } i2c_bus_busy; - - /* 0x10 : i2c_prd_start */ - union { - struct { - uint32_t cr_i2c_prd_s_ph_0 : 8; /* [ 7: 0], r/w, 0xf */ - uint32_t cr_i2c_prd_s_ph_1 : 8; /* [15: 8], r/w, 0xf */ - uint32_t cr_i2c_prd_s_ph_2 : 8; /* [23:16], r/w, 0xf */ - uint32_t cr_i2c_prd_s_ph_3 : 8; /* [31:24], r/w, 0xf */ - } BF; - uint32_t WORD; - } i2c_prd_start; - - /* 0x14 : i2c_prd_stop */ - union { - struct { - uint32_t cr_i2c_prd_p_ph_0 : 8; /* [ 7: 0], r/w, 0xf */ - uint32_t cr_i2c_prd_p_ph_1 : 8; /* [15: 8], r/w, 0xf */ - uint32_t cr_i2c_prd_p_ph_2 : 8; /* [23:16], r/w, 0xf */ - uint32_t cr_i2c_prd_p_ph_3 : 8; /* [31:24], r/w, 0xf */ - } BF; - uint32_t WORD; - } i2c_prd_stop; - - /* 0x18 : i2c_prd_data */ - union { - struct { - uint32_t cr_i2c_prd_d_ph_0 : 8; /* [ 7: 0], r/w, 0xf */ - uint32_t cr_i2c_prd_d_ph_1 : 8; /* [15: 8], r/w, 0xf */ - uint32_t cr_i2c_prd_d_ph_2 : 8; /* [23:16], r/w, 0xf */ - uint32_t cr_i2c_prd_d_ph_3 : 8; /* [31:24], r/w, 0xf */ - } BF; - uint32_t WORD; - } i2c_prd_data; - - /* 0x1c reserved */ - uint8_t RESERVED0x1c[100]; - - /* 0x80 : i2c_fifo_config_0 */ - union { - struct { - uint32_t i2c_dma_tx_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t i2c_dma_rx_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t tx_fifo_clr : 1; /* [ 2], w1c, 0x0 */ - uint32_t rx_fifo_clr : 1; /* [ 3], w1c, 0x0 */ - uint32_t tx_fifo_overflow : 1; /* [ 4], r, 0x0 */ - uint32_t tx_fifo_underflow : 1; /* [ 5], r, 0x0 */ - uint32_t rx_fifo_overflow : 1; /* [ 6], r, 0x0 */ - uint32_t rx_fifo_underflow : 1; /* [ 7], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } i2c_fifo_config_0; - - /* 0x84 : i2c_fifo_config_1 */ - union { - struct { - uint32_t tx_fifo_cnt : 2; /* [ 1: 0], r, 0x2 */ - uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ - uint32_t rx_fifo_cnt : 2; /* [ 9: 8], r, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t tx_fifo_th : 1; /* [ 16], r/w, 0x0 */ - uint32_t reserved_17_23 : 7; /* [23:17], rsvd, 0x0 */ - uint32_t rx_fifo_th : 1; /* [ 24], r/w, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } i2c_fifo_config_1; - - /* 0x88 : i2c_fifo_wdata */ - union { - struct { - uint32_t i2c_fifo_wdata : 32; /* [31: 0], w, x */ - } BF; - uint32_t WORD; - } i2c_fifo_wdata; - - /* 0x8C : i2c_fifo_rdata */ - union { - struct { - uint32_t i2c_fifo_rdata : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } i2c_fifo_rdata; -}; - -typedef volatile struct i2c_reg i2c_reg_t; - -#endif /* __I2C_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/i2s_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/i2s_reg.h deleted file mode 100644 index b4250520d6..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/i2s_reg.h +++ /dev/null @@ -1,441 +0,0 @@ -/** - ****************************************************************************** - * @file i2s_reg.h - * @version V1.0 - * @date 2021-06-22 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __I2S_REG_H__ -#define __I2S_REG_H__ - -#include "bl808.h" - -/* 0x0 : i2s_config */ -#define I2S_CONFIG_OFFSET (0x0) -#define I2S_CR_I2S_M_EN I2S_CR_I2S_M_EN -#define I2S_CR_I2S_M_EN_POS (0U) -#define I2S_CR_I2S_M_EN_LEN (1U) -#define I2S_CR_I2S_M_EN_MSK (((1U << I2S_CR_I2S_M_EN_LEN) - 1) << I2S_CR_I2S_M_EN_POS) -#define I2S_CR_I2S_M_EN_UMSK (~(((1U << I2S_CR_I2S_M_EN_LEN) - 1) << I2S_CR_I2S_M_EN_POS)) -#define I2S_CR_I2S_S_EN I2S_CR_I2S_S_EN -#define I2S_CR_I2S_S_EN_POS (1U) -#define I2S_CR_I2S_S_EN_LEN (1U) -#define I2S_CR_I2S_S_EN_MSK (((1U << I2S_CR_I2S_S_EN_LEN) - 1) << I2S_CR_I2S_S_EN_POS) -#define I2S_CR_I2S_S_EN_UMSK (~(((1U << I2S_CR_I2S_S_EN_LEN) - 1) << I2S_CR_I2S_S_EN_POS)) -#define I2S_CR_I2S_TXD_EN I2S_CR_I2S_TXD_EN -#define I2S_CR_I2S_TXD_EN_POS (2U) -#define I2S_CR_I2S_TXD_EN_LEN (1U) -#define I2S_CR_I2S_TXD_EN_MSK (((1U << I2S_CR_I2S_TXD_EN_LEN) - 1) << I2S_CR_I2S_TXD_EN_POS) -#define I2S_CR_I2S_TXD_EN_UMSK (~(((1U << I2S_CR_I2S_TXD_EN_LEN) - 1) << I2S_CR_I2S_TXD_EN_POS)) -#define I2S_CR_I2S_RXD_EN I2S_CR_I2S_RXD_EN -#define I2S_CR_I2S_RXD_EN_POS (3U) -#define I2S_CR_I2S_RXD_EN_LEN (1U) -#define I2S_CR_I2S_RXD_EN_MSK (((1U << I2S_CR_I2S_RXD_EN_LEN) - 1) << I2S_CR_I2S_RXD_EN_POS) -#define I2S_CR_I2S_RXD_EN_UMSK (~(((1U << I2S_CR_I2S_RXD_EN_LEN) - 1) << I2S_CR_I2S_RXD_EN_POS)) -#define I2S_CR_MONO_MODE I2S_CR_MONO_MODE -#define I2S_CR_MONO_MODE_POS (4U) -#define I2S_CR_MONO_MODE_LEN (1U) -#define I2S_CR_MONO_MODE_MSK (((1U << I2S_CR_MONO_MODE_LEN) - 1) << I2S_CR_MONO_MODE_POS) -#define I2S_CR_MONO_MODE_UMSK (~(((1U << I2S_CR_MONO_MODE_LEN) - 1) << I2S_CR_MONO_MODE_POS)) -#define I2S_CR_MUTE_MODE I2S_CR_MUTE_MODE -#define I2S_CR_MUTE_MODE_POS (5U) -#define I2S_CR_MUTE_MODE_LEN (1U) -#define I2S_CR_MUTE_MODE_MSK (((1U << I2S_CR_MUTE_MODE_LEN) - 1) << I2S_CR_MUTE_MODE_POS) -#define I2S_CR_MUTE_MODE_UMSK (~(((1U << I2S_CR_MUTE_MODE_LEN) - 1) << I2S_CR_MUTE_MODE_POS)) -#define I2S_CR_FS_1T_MODE I2S_CR_FS_1T_MODE -#define I2S_CR_FS_1T_MODE_POS (6U) -#define I2S_CR_FS_1T_MODE_LEN (1U) -#define I2S_CR_FS_1T_MODE_MSK (((1U << I2S_CR_FS_1T_MODE_LEN) - 1) << I2S_CR_FS_1T_MODE_POS) -#define I2S_CR_FS_1T_MODE_UMSK (~(((1U << I2S_CR_FS_1T_MODE_LEN) - 1) << I2S_CR_FS_1T_MODE_POS)) -#define I2S_CR_FS_CH_CNT I2S_CR_FS_CH_CNT -#define I2S_CR_FS_CH_CNT_POS (7U) -#define I2S_CR_FS_CH_CNT_LEN (2U) -#define I2S_CR_FS_CH_CNT_MSK (((1U << I2S_CR_FS_CH_CNT_LEN) - 1) << I2S_CR_FS_CH_CNT_POS) -#define I2S_CR_FS_CH_CNT_UMSK (~(((1U << I2S_CR_FS_CH_CNT_LEN) - 1) << I2S_CR_FS_CH_CNT_POS)) -#define I2S_CR_FRAME_SIZE I2S_CR_FRAME_SIZE -#define I2S_CR_FRAME_SIZE_POS (12U) -#define I2S_CR_FRAME_SIZE_LEN (2U) -#define I2S_CR_FRAME_SIZE_MSK (((1U << I2S_CR_FRAME_SIZE_LEN) - 1) << I2S_CR_FRAME_SIZE_POS) -#define I2S_CR_FRAME_SIZE_UMSK (~(((1U << I2S_CR_FRAME_SIZE_LEN) - 1) << I2S_CR_FRAME_SIZE_POS)) -#define I2S_CR_DATA_SIZE I2S_CR_DATA_SIZE -#define I2S_CR_DATA_SIZE_POS (14U) -#define I2S_CR_DATA_SIZE_LEN (2U) -#define I2S_CR_DATA_SIZE_MSK (((1U << I2S_CR_DATA_SIZE_LEN) - 1) << I2S_CR_DATA_SIZE_POS) -#define I2S_CR_DATA_SIZE_UMSK (~(((1U << I2S_CR_DATA_SIZE_LEN) - 1) << I2S_CR_DATA_SIZE_POS)) -#define I2S_CR_I2S_MODE I2S_CR_I2S_MODE -#define I2S_CR_I2S_MODE_POS (16U) -#define I2S_CR_I2S_MODE_LEN (2U) -#define I2S_CR_I2S_MODE_MSK (((1U << I2S_CR_I2S_MODE_LEN) - 1) << I2S_CR_I2S_MODE_POS) -#define I2S_CR_I2S_MODE_UMSK (~(((1U << I2S_CR_I2S_MODE_LEN) - 1) << I2S_CR_I2S_MODE_POS)) -#define I2S_CR_ENDIAN I2S_CR_ENDIAN -#define I2S_CR_ENDIAN_POS (18U) -#define I2S_CR_ENDIAN_LEN (1U) -#define I2S_CR_ENDIAN_MSK (((1U << I2S_CR_ENDIAN_LEN) - 1) << I2S_CR_ENDIAN_POS) -#define I2S_CR_ENDIAN_UMSK (~(((1U << I2S_CR_ENDIAN_LEN) - 1) << I2S_CR_ENDIAN_POS)) -#define I2S_CR_MONO_RX_CH I2S_CR_MONO_RX_CH -#define I2S_CR_MONO_RX_CH_POS (19U) -#define I2S_CR_MONO_RX_CH_LEN (1U) -#define I2S_CR_MONO_RX_CH_MSK (((1U << I2S_CR_MONO_RX_CH_LEN) - 1) << I2S_CR_MONO_RX_CH_POS) -#define I2S_CR_MONO_RX_CH_UMSK (~(((1U << I2S_CR_MONO_RX_CH_LEN) - 1) << I2S_CR_MONO_RX_CH_POS)) -#define I2S_CR_OFS_CNT I2S_CR_OFS_CNT -#define I2S_CR_OFS_CNT_POS (20U) -#define I2S_CR_OFS_CNT_LEN (5U) -#define I2S_CR_OFS_CNT_MSK (((1U << I2S_CR_OFS_CNT_LEN) - 1) << I2S_CR_OFS_CNT_POS) -#define I2S_CR_OFS_CNT_UMSK (~(((1U << I2S_CR_OFS_CNT_LEN) - 1) << I2S_CR_OFS_CNT_POS)) -#define I2S_CR_OFS_EN I2S_CR_OFS_EN -#define I2S_CR_OFS_EN_POS (25U) -#define I2S_CR_OFS_EN_LEN (1U) -#define I2S_CR_OFS_EN_MSK (((1U << I2S_CR_OFS_EN_LEN) - 1) << I2S_CR_OFS_EN_POS) -#define I2S_CR_OFS_EN_UMSK (~(((1U << I2S_CR_OFS_EN_LEN) - 1) << I2S_CR_OFS_EN_POS)) - -/* 0x4 : i2s_int_sts */ -#define I2S_INT_STS_OFFSET (0x4) -#define I2S_TXF_INT I2S_TXF_INT -#define I2S_TXF_INT_POS (0U) -#define I2S_TXF_INT_LEN (1U) -#define I2S_TXF_INT_MSK (((1U << I2S_TXF_INT_LEN) - 1) << I2S_TXF_INT_POS) -#define I2S_TXF_INT_UMSK (~(((1U << I2S_TXF_INT_LEN) - 1) << I2S_TXF_INT_POS)) -#define I2S_RXF_INT I2S_RXF_INT -#define I2S_RXF_INT_POS (1U) -#define I2S_RXF_INT_LEN (1U) -#define I2S_RXF_INT_MSK (((1U << I2S_RXF_INT_LEN) - 1) << I2S_RXF_INT_POS) -#define I2S_RXF_INT_UMSK (~(((1U << I2S_RXF_INT_LEN) - 1) << I2S_RXF_INT_POS)) -#define I2S_FER_INT I2S_FER_INT -#define I2S_FER_INT_POS (2U) -#define I2S_FER_INT_LEN (1U) -#define I2S_FER_INT_MSK (((1U << I2S_FER_INT_LEN) - 1) << I2S_FER_INT_POS) -#define I2S_FER_INT_UMSK (~(((1U << I2S_FER_INT_LEN) - 1) << I2S_FER_INT_POS)) -#define I2S_CR_I2S_TXF_MASK I2S_CR_I2S_TXF_MASK -#define I2S_CR_I2S_TXF_MASK_POS (8U) -#define I2S_CR_I2S_TXF_MASK_LEN (1U) -#define I2S_CR_I2S_TXF_MASK_MSK (((1U << I2S_CR_I2S_TXF_MASK_LEN) - 1) << I2S_CR_I2S_TXF_MASK_POS) -#define I2S_CR_I2S_TXF_MASK_UMSK (~(((1U << I2S_CR_I2S_TXF_MASK_LEN) - 1) << I2S_CR_I2S_TXF_MASK_POS)) -#define I2S_CR_I2S_RXF_MASK I2S_CR_I2S_RXF_MASK -#define I2S_CR_I2S_RXF_MASK_POS (9U) -#define I2S_CR_I2S_RXF_MASK_LEN (1U) -#define I2S_CR_I2S_RXF_MASK_MSK (((1U << I2S_CR_I2S_RXF_MASK_LEN) - 1) << I2S_CR_I2S_RXF_MASK_POS) -#define I2S_CR_I2S_RXF_MASK_UMSK (~(((1U << I2S_CR_I2S_RXF_MASK_LEN) - 1) << I2S_CR_I2S_RXF_MASK_POS)) -#define I2S_CR_I2S_FER_MASK I2S_CR_I2S_FER_MASK -#define I2S_CR_I2S_FER_MASK_POS (10U) -#define I2S_CR_I2S_FER_MASK_LEN (1U) -#define I2S_CR_I2S_FER_MASK_MSK (((1U << I2S_CR_I2S_FER_MASK_LEN) - 1) << I2S_CR_I2S_FER_MASK_POS) -#define I2S_CR_I2S_FER_MASK_UMSK (~(((1U << I2S_CR_I2S_FER_MASK_LEN) - 1) << I2S_CR_I2S_FER_MASK_POS)) -#define I2S_CR_I2S_TXF_EN I2S_CR_I2S_TXF_EN -#define I2S_CR_I2S_TXF_EN_POS (24U) -#define I2S_CR_I2S_TXF_EN_LEN (1U) -#define I2S_CR_I2S_TXF_EN_MSK (((1U << I2S_CR_I2S_TXF_EN_LEN) - 1) << I2S_CR_I2S_TXF_EN_POS) -#define I2S_CR_I2S_TXF_EN_UMSK (~(((1U << I2S_CR_I2S_TXF_EN_LEN) - 1) << I2S_CR_I2S_TXF_EN_POS)) -#define I2S_CR_I2S_RXF_EN I2S_CR_I2S_RXF_EN -#define I2S_CR_I2S_RXF_EN_POS (25U) -#define I2S_CR_I2S_RXF_EN_LEN (1U) -#define I2S_CR_I2S_RXF_EN_MSK (((1U << I2S_CR_I2S_RXF_EN_LEN) - 1) << I2S_CR_I2S_RXF_EN_POS) -#define I2S_CR_I2S_RXF_EN_UMSK (~(((1U << I2S_CR_I2S_RXF_EN_LEN) - 1) << I2S_CR_I2S_RXF_EN_POS)) -#define I2S_CR_I2S_FER_EN I2S_CR_I2S_FER_EN -#define I2S_CR_I2S_FER_EN_POS (26U) -#define I2S_CR_I2S_FER_EN_LEN (1U) -#define I2S_CR_I2S_FER_EN_MSK (((1U << I2S_CR_I2S_FER_EN_LEN) - 1) << I2S_CR_I2S_FER_EN_POS) -#define I2S_CR_I2S_FER_EN_UMSK (~(((1U << I2S_CR_I2S_FER_EN_LEN) - 1) << I2S_CR_I2S_FER_EN_POS)) - -/* 0x10 : i2s_bclk_config */ -#define I2S_BCLK_CONFIG_OFFSET (0x10) -#define I2S_CR_BCLK_DIV_L I2S_CR_BCLK_DIV_L -#define I2S_CR_BCLK_DIV_L_POS (0U) -#define I2S_CR_BCLK_DIV_L_LEN (12U) -#define I2S_CR_BCLK_DIV_L_MSK (((1U << I2S_CR_BCLK_DIV_L_LEN) - 1) << I2S_CR_BCLK_DIV_L_POS) -#define I2S_CR_BCLK_DIV_L_UMSK (~(((1U << I2S_CR_BCLK_DIV_L_LEN) - 1) << I2S_CR_BCLK_DIV_L_POS)) -#define I2S_CR_BCLK_DIV_H I2S_CR_BCLK_DIV_H -#define I2S_CR_BCLK_DIV_H_POS (16U) -#define I2S_CR_BCLK_DIV_H_LEN (12U) -#define I2S_CR_BCLK_DIV_H_MSK (((1U << I2S_CR_BCLK_DIV_H_LEN) - 1) << I2S_CR_BCLK_DIV_H_POS) -#define I2S_CR_BCLK_DIV_H_UMSK (~(((1U << I2S_CR_BCLK_DIV_H_LEN) - 1) << I2S_CR_BCLK_DIV_H_POS)) - -/* 0x80 : i2s_fifo_config_0 */ -#define I2S_FIFO_CONFIG_0_OFFSET (0x80) -#define I2S_DMA_TX_EN I2S_DMA_TX_EN -#define I2S_DMA_TX_EN_POS (0U) -#define I2S_DMA_TX_EN_LEN (1U) -#define I2S_DMA_TX_EN_MSK (((1U << I2S_DMA_TX_EN_LEN) - 1) << I2S_DMA_TX_EN_POS) -#define I2S_DMA_TX_EN_UMSK (~(((1U << I2S_DMA_TX_EN_LEN) - 1) << I2S_DMA_TX_EN_POS)) -#define I2S_DMA_RX_EN I2S_DMA_RX_EN -#define I2S_DMA_RX_EN_POS (1U) -#define I2S_DMA_RX_EN_LEN (1U) -#define I2S_DMA_RX_EN_MSK (((1U << I2S_DMA_RX_EN_LEN) - 1) << I2S_DMA_RX_EN_POS) -#define I2S_DMA_RX_EN_UMSK (~(((1U << I2S_DMA_RX_EN_LEN) - 1) << I2S_DMA_RX_EN_POS)) -#define I2S_TX_FIFO_CLR I2S_TX_FIFO_CLR -#define I2S_TX_FIFO_CLR_POS (2U) -#define I2S_TX_FIFO_CLR_LEN (1U) -#define I2S_TX_FIFO_CLR_MSK (((1U << I2S_TX_FIFO_CLR_LEN) - 1) << I2S_TX_FIFO_CLR_POS) -#define I2S_TX_FIFO_CLR_UMSK (~(((1U << I2S_TX_FIFO_CLR_LEN) - 1) << I2S_TX_FIFO_CLR_POS)) -#define I2S_RX_FIFO_CLR I2S_RX_FIFO_CLR -#define I2S_RX_FIFO_CLR_POS (3U) -#define I2S_RX_FIFO_CLR_LEN (1U) -#define I2S_RX_FIFO_CLR_MSK (((1U << I2S_RX_FIFO_CLR_LEN) - 1) << I2S_RX_FIFO_CLR_POS) -#define I2S_RX_FIFO_CLR_UMSK (~(((1U << I2S_RX_FIFO_CLR_LEN) - 1) << I2S_RX_FIFO_CLR_POS)) -#define I2S_TX_FIFO_OVERFLOW I2S_TX_FIFO_OVERFLOW -#define I2S_TX_FIFO_OVERFLOW_POS (4U) -#define I2S_TX_FIFO_OVERFLOW_LEN (1U) -#define I2S_TX_FIFO_OVERFLOW_MSK (((1U << I2S_TX_FIFO_OVERFLOW_LEN) - 1) << I2S_TX_FIFO_OVERFLOW_POS) -#define I2S_TX_FIFO_OVERFLOW_UMSK (~(((1U << I2S_TX_FIFO_OVERFLOW_LEN) - 1) << I2S_TX_FIFO_OVERFLOW_POS)) -#define I2S_TX_FIFO_UNDERFLOW I2S_TX_FIFO_UNDERFLOW -#define I2S_TX_FIFO_UNDERFLOW_POS (5U) -#define I2S_TX_FIFO_UNDERFLOW_LEN (1U) -#define I2S_TX_FIFO_UNDERFLOW_MSK (((1U << I2S_TX_FIFO_UNDERFLOW_LEN) - 1) << I2S_TX_FIFO_UNDERFLOW_POS) -#define I2S_TX_FIFO_UNDERFLOW_UMSK (~(((1U << I2S_TX_FIFO_UNDERFLOW_LEN) - 1) << I2S_TX_FIFO_UNDERFLOW_POS)) -#define I2S_RX_FIFO_OVERFLOW I2S_RX_FIFO_OVERFLOW -#define I2S_RX_FIFO_OVERFLOW_POS (6U) -#define I2S_RX_FIFO_OVERFLOW_LEN (1U) -#define I2S_RX_FIFO_OVERFLOW_MSK (((1U << I2S_RX_FIFO_OVERFLOW_LEN) - 1) << I2S_RX_FIFO_OVERFLOW_POS) -#define I2S_RX_FIFO_OVERFLOW_UMSK (~(((1U << I2S_RX_FIFO_OVERFLOW_LEN) - 1) << I2S_RX_FIFO_OVERFLOW_POS)) -#define I2S_RX_FIFO_UNDERFLOW I2S_RX_FIFO_UNDERFLOW -#define I2S_RX_FIFO_UNDERFLOW_POS (7U) -#define I2S_RX_FIFO_UNDERFLOW_LEN (1U) -#define I2S_RX_FIFO_UNDERFLOW_MSK (((1U << I2S_RX_FIFO_UNDERFLOW_LEN) - 1) << I2S_RX_FIFO_UNDERFLOW_POS) -#define I2S_RX_FIFO_UNDERFLOW_UMSK (~(((1U << I2S_RX_FIFO_UNDERFLOW_LEN) - 1) << I2S_RX_FIFO_UNDERFLOW_POS)) -#define I2S_CR_FIFO_LR_MERGE I2S_CR_FIFO_LR_MERGE -#define I2S_CR_FIFO_LR_MERGE_POS (8U) -#define I2S_CR_FIFO_LR_MERGE_LEN (1U) -#define I2S_CR_FIFO_LR_MERGE_MSK (((1U << I2S_CR_FIFO_LR_MERGE_LEN) - 1) << I2S_CR_FIFO_LR_MERGE_POS) -#define I2S_CR_FIFO_LR_MERGE_UMSK (~(((1U << I2S_CR_FIFO_LR_MERGE_LEN) - 1) << I2S_CR_FIFO_LR_MERGE_POS)) -#define I2S_CR_FIFO_LR_EXCHG I2S_CR_FIFO_LR_EXCHG -#define I2S_CR_FIFO_LR_EXCHG_POS (9U) -#define I2S_CR_FIFO_LR_EXCHG_LEN (1U) -#define I2S_CR_FIFO_LR_EXCHG_MSK (((1U << I2S_CR_FIFO_LR_EXCHG_LEN) - 1) << I2S_CR_FIFO_LR_EXCHG_POS) -#define I2S_CR_FIFO_LR_EXCHG_UMSK (~(((1U << I2S_CR_FIFO_LR_EXCHG_LEN) - 1) << I2S_CR_FIFO_LR_EXCHG_POS)) -#define I2S_CR_FIFO_24B_LJ I2S_CR_FIFO_24B_LJ -#define I2S_CR_FIFO_24B_LJ_POS (10U) -#define I2S_CR_FIFO_24B_LJ_LEN (1U) -#define I2S_CR_FIFO_24B_LJ_MSK (((1U << I2S_CR_FIFO_24B_LJ_LEN) - 1) << I2S_CR_FIFO_24B_LJ_POS) -#define I2S_CR_FIFO_24B_LJ_UMSK (~(((1U << I2S_CR_FIFO_24B_LJ_LEN) - 1) << I2S_CR_FIFO_24B_LJ_POS)) - -/* 0x84 : i2s_fifo_config_1 */ -#define I2S_FIFO_CONFIG_1_OFFSET (0x84) -#define I2S_TX_FIFO_CNT I2S_TX_FIFO_CNT -#define I2S_TX_FIFO_CNT_POS (0U) -#define I2S_TX_FIFO_CNT_LEN (5U) -#define I2S_TX_FIFO_CNT_MSK (((1U << I2S_TX_FIFO_CNT_LEN) - 1) << I2S_TX_FIFO_CNT_POS) -#define I2S_TX_FIFO_CNT_UMSK (~(((1U << I2S_TX_FIFO_CNT_LEN) - 1) << I2S_TX_FIFO_CNT_POS)) -#define I2S_RX_FIFO_CNT I2S_RX_FIFO_CNT -#define I2S_RX_FIFO_CNT_POS (8U) -#define I2S_RX_FIFO_CNT_LEN (5U) -#define I2S_RX_FIFO_CNT_MSK (((1U << I2S_RX_FIFO_CNT_LEN) - 1) << I2S_RX_FIFO_CNT_POS) -#define I2S_RX_FIFO_CNT_UMSK (~(((1U << I2S_RX_FIFO_CNT_LEN) - 1) << I2S_RX_FIFO_CNT_POS)) -#define I2S_TX_FIFO_TH I2S_TX_FIFO_TH -#define I2S_TX_FIFO_TH_POS (16U) -#define I2S_TX_FIFO_TH_LEN (4U) -#define I2S_TX_FIFO_TH_MSK (((1U << I2S_TX_FIFO_TH_LEN) - 1) << I2S_TX_FIFO_TH_POS) -#define I2S_TX_FIFO_TH_UMSK (~(((1U << I2S_TX_FIFO_TH_LEN) - 1) << I2S_TX_FIFO_TH_POS)) -#define I2S_RX_FIFO_TH I2S_RX_FIFO_TH -#define I2S_RX_FIFO_TH_POS (24U) -#define I2S_RX_FIFO_TH_LEN (4U) -#define I2S_RX_FIFO_TH_MSK (((1U << I2S_RX_FIFO_TH_LEN) - 1) << I2S_RX_FIFO_TH_POS) -#define I2S_RX_FIFO_TH_UMSK (~(((1U << I2S_RX_FIFO_TH_LEN) - 1) << I2S_RX_FIFO_TH_POS)) - -/* 0x88 : i2s_fifo_wdata */ -#define I2S_FIFO_WDATA_OFFSET (0x88) -#define I2S_FIFO_WDATA I2S_FIFO_WDATA -#define I2S_FIFO_WDATA_POS (0U) -#define I2S_FIFO_WDATA_LEN (32U) -#define I2S_FIFO_WDATA_MSK (((1U << I2S_FIFO_WDATA_LEN) - 1) << I2S_FIFO_WDATA_POS) -#define I2S_FIFO_WDATA_UMSK (~(((1U << I2S_FIFO_WDATA_LEN) - 1) << I2S_FIFO_WDATA_POS)) - -/* 0x8C : i2s_fifo_rdata */ -#define I2S_FIFO_RDATA_OFFSET (0x8C) -#define I2S_FIFO_RDATA I2S_FIFO_RDATA -#define I2S_FIFO_RDATA_POS (0U) -#define I2S_FIFO_RDATA_LEN (32U) -#define I2S_FIFO_RDATA_MSK (((1U << I2S_FIFO_RDATA_LEN) - 1) << I2S_FIFO_RDATA_POS) -#define I2S_FIFO_RDATA_UMSK (~(((1U << I2S_FIFO_RDATA_LEN) - 1) << I2S_FIFO_RDATA_POS)) - -/* 0xFC : i2s_io_config */ -#define I2S_IO_CONFIG_OFFSET (0xFC) -#define I2S_CR_I2S_TXD_INV I2S_CR_I2S_TXD_INV -#define I2S_CR_I2S_TXD_INV_POS (0U) -#define I2S_CR_I2S_TXD_INV_LEN (1U) -#define I2S_CR_I2S_TXD_INV_MSK (((1U << I2S_CR_I2S_TXD_INV_LEN) - 1) << I2S_CR_I2S_TXD_INV_POS) -#define I2S_CR_I2S_TXD_INV_UMSK (~(((1U << I2S_CR_I2S_TXD_INV_LEN) - 1) << I2S_CR_I2S_TXD_INV_POS)) -#define I2S_CR_I2S_RXD_INV I2S_CR_I2S_RXD_INV -#define I2S_CR_I2S_RXD_INV_POS (1U) -#define I2S_CR_I2S_RXD_INV_LEN (1U) -#define I2S_CR_I2S_RXD_INV_MSK (((1U << I2S_CR_I2S_RXD_INV_LEN) - 1) << I2S_CR_I2S_RXD_INV_POS) -#define I2S_CR_I2S_RXD_INV_UMSK (~(((1U << I2S_CR_I2S_RXD_INV_LEN) - 1) << I2S_CR_I2S_RXD_INV_POS)) -#define I2S_CR_I2S_FS_INV I2S_CR_I2S_FS_INV -#define I2S_CR_I2S_FS_INV_POS (2U) -#define I2S_CR_I2S_FS_INV_LEN (1U) -#define I2S_CR_I2S_FS_INV_MSK (((1U << I2S_CR_I2S_FS_INV_LEN) - 1) << I2S_CR_I2S_FS_INV_POS) -#define I2S_CR_I2S_FS_INV_UMSK (~(((1U << I2S_CR_I2S_FS_INV_LEN) - 1) << I2S_CR_I2S_FS_INV_POS)) -#define I2S_CR_I2S_BCLK_INV I2S_CR_I2S_BCLK_INV -#define I2S_CR_I2S_BCLK_INV_POS (3U) -#define I2S_CR_I2S_BCLK_INV_LEN (1U) -#define I2S_CR_I2S_BCLK_INV_MSK (((1U << I2S_CR_I2S_BCLK_INV_LEN) - 1) << I2S_CR_I2S_BCLK_INV_POS) -#define I2S_CR_I2S_BCLK_INV_UMSK (~(((1U << I2S_CR_I2S_BCLK_INV_LEN) - 1) << I2S_CR_I2S_BCLK_INV_POS)) -#define I2S_CR_DEG_CNT I2S_CR_DEG_CNT -#define I2S_CR_DEG_CNT_POS (4U) -#define I2S_CR_DEG_CNT_LEN (3U) -#define I2S_CR_DEG_CNT_MSK (((1U << I2S_CR_DEG_CNT_LEN) - 1) << I2S_CR_DEG_CNT_POS) -#define I2S_CR_DEG_CNT_UMSK (~(((1U << I2S_CR_DEG_CNT_LEN) - 1) << I2S_CR_DEG_CNT_POS)) -#define I2S_CR_DEG_EN I2S_CR_DEG_EN -#define I2S_CR_DEG_EN_POS (7U) -#define I2S_CR_DEG_EN_LEN (1U) -#define I2S_CR_DEG_EN_MSK (((1U << I2S_CR_DEG_EN_LEN) - 1) << I2S_CR_DEG_EN_POS) -#define I2S_CR_DEG_EN_UMSK (~(((1U << I2S_CR_DEG_EN_LEN) - 1) << I2S_CR_DEG_EN_POS)) - -struct i2s_reg { - /* 0x0 : i2s_config */ - union { - struct { - uint32_t cr_i2s_m_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t cr_i2s_s_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t cr_i2s_txd_en : 1; /* [ 2], r/w, 0x0 */ - uint32_t cr_i2s_rxd_en : 1; /* [ 3], r/w, 0x0 */ - uint32_t cr_mono_mode : 1; /* [ 4], r/w, 0x0 */ - uint32_t cr_mute_mode : 1; /* [ 5], r/w, 0x0 */ - uint32_t cr_fs_1t_mode : 1; /* [ 6], r/w, 0x0 */ - uint32_t cr_fs_ch_cnt : 2; /* [ 8: 7], r/w, 0x0 */ - uint32_t reserved_9_11 : 3; /* [11: 9], rsvd, 0x0 */ - uint32_t cr_frame_size : 2; /* [13:12], r/w, 0x1 */ - uint32_t cr_data_size : 2; /* [15:14], r/w, 0x1 */ - uint32_t cr_i2s_mode : 2; /* [17:16], r/w, 0x0 */ - uint32_t cr_endian : 1; /* [ 18], r/w, 0x0 */ - uint32_t cr_mono_rx_ch : 1; /* [ 19], r/w, 0x0 */ - uint32_t cr_ofs_cnt : 5; /* [24:20], r/w, 0x0 */ - uint32_t cr_ofs_en : 1; /* [ 25], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } i2s_config; - - /* 0x4 : i2s_int_sts */ - union { - struct { - uint32_t i2s_txf_int : 1; /* [ 0], r, 0x1 */ - uint32_t i2s_rxf_int : 1; /* [ 1], r, 0x0 */ - uint32_t i2s_fer_int : 1; /* [ 2], r, 0x0 */ - uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */ - uint32_t cr_i2s_txf_mask : 1; /* [ 8], r/w, 0x1 */ - uint32_t cr_i2s_rxf_mask : 1; /* [ 9], r/w, 0x1 */ - uint32_t cr_i2s_fer_mask : 1; /* [ 10], r/w, 0x1 */ - uint32_t reserved_11_23 : 13; /* [23:11], rsvd, 0x0 */ - uint32_t cr_i2s_txf_en : 1; /* [ 24], r/w, 0x1 */ - uint32_t cr_i2s_rxf_en : 1; /* [ 25], r/w, 0x1 */ - uint32_t cr_i2s_fer_en : 1; /* [ 26], r/w, 0x1 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } i2s_int_sts; - - /* 0x8 reserved */ - uint8_t RESERVED0x8[8]; - - /* 0x10 : i2s_bclk_config */ - union { - struct { - uint32_t cr_bclk_div_l : 12; /* [11: 0], r/w, 0x1 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t cr_bclk_div_h : 12; /* [27:16], r/w, 0x1 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } i2s_bclk_config; - - /* 0x14 reserved */ - uint8_t RESERVED0x14[108]; - - /* 0x80 : i2s_fifo_config_0 */ - union { - struct { - uint32_t i2s_dma_tx_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t i2s_dma_rx_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t tx_fifo_clr : 1; /* [ 2], w1c, 0x0 */ - uint32_t rx_fifo_clr : 1; /* [ 3], w1c, 0x0 */ - uint32_t tx_fifo_overflow : 1; /* [ 4], r, 0x0 */ - uint32_t tx_fifo_underflow : 1; /* [ 5], r, 0x0 */ - uint32_t rx_fifo_overflow : 1; /* [ 6], r, 0x0 */ - uint32_t rx_fifo_underflow : 1; /* [ 7], r, 0x0 */ - uint32_t cr_fifo_lr_merge : 1; /* [ 8], r/w, 0x0 */ - uint32_t cr_fifo_lr_exchg : 1; /* [ 9], r/w, 0x0 */ - uint32_t cr_fifo_24b_lj : 1; /* [ 10], r/w, 0x0 */ - uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } i2s_fifo_config_0; - - /* 0x84 : i2s_fifo_config_1 */ - union { - struct { - uint32_t tx_fifo_cnt : 5; /* [ 4: 0], r, 0x10 */ - uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ - uint32_t rx_fifo_cnt : 5; /* [12: 8], r, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t tx_fifo_th : 4; /* [19:16], r/w, 0x0 */ - uint32_t reserved_20_23 : 4; /* [23:20], rsvd, 0x0 */ - uint32_t rx_fifo_th : 4; /* [27:24], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } i2s_fifo_config_1; - - /* 0x88 : i2s_fifo_wdata */ - union { - struct { - uint32_t i2s_fifo_wdata : 32; /* [31: 0], w, x */ - } BF; - uint32_t WORD; - } i2s_fifo_wdata; - - /* 0x8C : i2s_fifo_rdata */ - union { - struct { - uint32_t i2s_fifo_rdata : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } i2s_fifo_rdata; - - /* 0x90 reserved */ - uint8_t RESERVED0x90[108]; - - /* 0xFC : i2s_io_config */ - union { - struct { - uint32_t cr_i2s_txd_inv : 1; /* [ 0], r/w, 0x0 */ - uint32_t cr_i2s_rxd_inv : 1; /* [ 1], r/w, 0x0 */ - uint32_t cr_i2s_fs_inv : 1; /* [ 2], r/w, 0x0 */ - uint32_t cr_i2s_bclk_inv : 1; /* [ 3], r/w, 0x0 */ - uint32_t cr_deg_cnt : 3; /* [ 6: 4], r/w, 0x0 */ - uint32_t cr_deg_en : 1; /* [ 7], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } i2s_io_config; -}; - -typedef volatile struct i2s_reg i2s_reg_t; - -#endif /* __I2S_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/ir_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/ir_reg.h deleted file mode 100644 index 8cffd08359..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/ir_reg.h +++ /dev/null @@ -1,646 +0,0 @@ -/** - ****************************************************************************** - * @file ir_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __IR_REG_H__ -#define __IR_REG_H__ - -#include "bl808.h" - -/* 0x0 : irtx_config */ -#define IRTX_CONFIG_OFFSET (0x0) -#define IR_CR_IRTX_EN IR_CR_IRTX_EN -#define IR_CR_IRTX_EN_POS (0U) -#define IR_CR_IRTX_EN_LEN (1U) -#define IR_CR_IRTX_EN_MSK (((1U << IR_CR_IRTX_EN_LEN) - 1) << IR_CR_IRTX_EN_POS) -#define IR_CR_IRTX_EN_UMSK (~(((1U << IR_CR_IRTX_EN_LEN) - 1) << IR_CR_IRTX_EN_POS)) -#define IR_CR_IRTX_OUT_INV IR_CR_IRTX_OUT_INV -#define IR_CR_IRTX_OUT_INV_POS (1U) -#define IR_CR_IRTX_OUT_INV_LEN (1U) -#define IR_CR_IRTX_OUT_INV_MSK (((1U << IR_CR_IRTX_OUT_INV_LEN) - 1) << IR_CR_IRTX_OUT_INV_POS) -#define IR_CR_IRTX_OUT_INV_UMSK (~(((1U << IR_CR_IRTX_OUT_INV_LEN) - 1) << IR_CR_IRTX_OUT_INV_POS)) -#define IR_CR_IRTX_MOD_EN IR_CR_IRTX_MOD_EN -#define IR_CR_IRTX_MOD_EN_POS (2U) -#define IR_CR_IRTX_MOD_EN_LEN (1U) -#define IR_CR_IRTX_MOD_EN_MSK (((1U << IR_CR_IRTX_MOD_EN_LEN) - 1) << IR_CR_IRTX_MOD_EN_POS) -#define IR_CR_IRTX_MOD_EN_UMSK (~(((1U << IR_CR_IRTX_MOD_EN_LEN) - 1) << IR_CR_IRTX_MOD_EN_POS)) -#define IR_CR_IRTX_SWM_EN IR_CR_IRTX_SWM_EN -#define IR_CR_IRTX_SWM_EN_POS (3U) -#define IR_CR_IRTX_SWM_EN_LEN (1U) -#define IR_CR_IRTX_SWM_EN_MSK (((1U << IR_CR_IRTX_SWM_EN_LEN) - 1) << IR_CR_IRTX_SWM_EN_POS) -#define IR_CR_IRTX_SWM_EN_UMSK (~(((1U << IR_CR_IRTX_SWM_EN_LEN) - 1) << IR_CR_IRTX_SWM_EN_POS)) -#define IR_CR_IRTX_DATA_EN IR_CR_IRTX_DATA_EN -#define IR_CR_IRTX_DATA_EN_POS (4U) -#define IR_CR_IRTX_DATA_EN_LEN (1U) -#define IR_CR_IRTX_DATA_EN_MSK (((1U << IR_CR_IRTX_DATA_EN_LEN) - 1) << IR_CR_IRTX_DATA_EN_POS) -#define IR_CR_IRTX_DATA_EN_UMSK (~(((1U << IR_CR_IRTX_DATA_EN_LEN) - 1) << IR_CR_IRTX_DATA_EN_POS)) -#define IR_CR_IRTX_LOGIC0_HL_INV IR_CR_IRTX_LOGIC0_HL_INV -#define IR_CR_IRTX_LOGIC0_HL_INV_POS (5U) -#define IR_CR_IRTX_LOGIC0_HL_INV_LEN (1U) -#define IR_CR_IRTX_LOGIC0_HL_INV_MSK (((1U << IR_CR_IRTX_LOGIC0_HL_INV_LEN) - 1) << IR_CR_IRTX_LOGIC0_HL_INV_POS) -#define IR_CR_IRTX_LOGIC0_HL_INV_UMSK (~(((1U << IR_CR_IRTX_LOGIC0_HL_INV_LEN) - 1) << IR_CR_IRTX_LOGIC0_HL_INV_POS)) -#define IR_CR_IRTX_LOGIC1_HL_INV IR_CR_IRTX_LOGIC1_HL_INV -#define IR_CR_IRTX_LOGIC1_HL_INV_POS (6U) -#define IR_CR_IRTX_LOGIC1_HL_INV_LEN (1U) -#define IR_CR_IRTX_LOGIC1_HL_INV_MSK (((1U << IR_CR_IRTX_LOGIC1_HL_INV_LEN) - 1) << IR_CR_IRTX_LOGIC1_HL_INV_POS) -#define IR_CR_IRTX_LOGIC1_HL_INV_UMSK (~(((1U << IR_CR_IRTX_LOGIC1_HL_INV_LEN) - 1) << IR_CR_IRTX_LOGIC1_HL_INV_POS)) -#define IR_CR_IRTX_HEAD_EN IR_CR_IRTX_HEAD_EN -#define IR_CR_IRTX_HEAD_EN_POS (8U) -#define IR_CR_IRTX_HEAD_EN_LEN (1U) -#define IR_CR_IRTX_HEAD_EN_MSK (((1U << IR_CR_IRTX_HEAD_EN_LEN) - 1) << IR_CR_IRTX_HEAD_EN_POS) -#define IR_CR_IRTX_HEAD_EN_UMSK (~(((1U << IR_CR_IRTX_HEAD_EN_LEN) - 1) << IR_CR_IRTX_HEAD_EN_POS)) -#define IR_CR_IRTX_HEAD_HL_INV IR_CR_IRTX_HEAD_HL_INV -#define IR_CR_IRTX_HEAD_HL_INV_POS (9U) -#define IR_CR_IRTX_HEAD_HL_INV_LEN (1U) -#define IR_CR_IRTX_HEAD_HL_INV_MSK (((1U << IR_CR_IRTX_HEAD_HL_INV_LEN) - 1) << IR_CR_IRTX_HEAD_HL_INV_POS) -#define IR_CR_IRTX_HEAD_HL_INV_UMSK (~(((1U << IR_CR_IRTX_HEAD_HL_INV_LEN) - 1) << IR_CR_IRTX_HEAD_HL_INV_POS)) -#define IR_CR_IRTX_TAIL_EN IR_CR_IRTX_TAIL_EN -#define IR_CR_IRTX_TAIL_EN_POS (10U) -#define IR_CR_IRTX_TAIL_EN_LEN (1U) -#define IR_CR_IRTX_TAIL_EN_MSK (((1U << IR_CR_IRTX_TAIL_EN_LEN) - 1) << IR_CR_IRTX_TAIL_EN_POS) -#define IR_CR_IRTX_TAIL_EN_UMSK (~(((1U << IR_CR_IRTX_TAIL_EN_LEN) - 1) << IR_CR_IRTX_TAIL_EN_POS)) -#define IR_CR_IRTX_TAIL_HL_INV IR_CR_IRTX_TAIL_HL_INV -#define IR_CR_IRTX_TAIL_HL_INV_POS (11U) -#define IR_CR_IRTX_TAIL_HL_INV_LEN (1U) -#define IR_CR_IRTX_TAIL_HL_INV_MSK (((1U << IR_CR_IRTX_TAIL_HL_INV_LEN) - 1) << IR_CR_IRTX_TAIL_HL_INV_POS) -#define IR_CR_IRTX_TAIL_HL_INV_UMSK (~(((1U << IR_CR_IRTX_TAIL_HL_INV_LEN) - 1) << IR_CR_IRTX_TAIL_HL_INV_POS)) -#define IR_CR_IRTX_FRM_EN IR_CR_IRTX_FRM_EN -#define IR_CR_IRTX_FRM_EN_POS (12U) -#define IR_CR_IRTX_FRM_EN_LEN (1U) -#define IR_CR_IRTX_FRM_EN_MSK (((1U << IR_CR_IRTX_FRM_EN_LEN) - 1) << IR_CR_IRTX_FRM_EN_POS) -#define IR_CR_IRTX_FRM_EN_UMSK (~(((1U << IR_CR_IRTX_FRM_EN_LEN) - 1) << IR_CR_IRTX_FRM_EN_POS)) -#define IR_CR_IRTX_FRM_CONT_EN IR_CR_IRTX_FRM_CONT_EN -#define IR_CR_IRTX_FRM_CONT_EN_POS (13U) -#define IR_CR_IRTX_FRM_CONT_EN_LEN (1U) -#define IR_CR_IRTX_FRM_CONT_EN_MSK (((1U << IR_CR_IRTX_FRM_CONT_EN_LEN) - 1) << IR_CR_IRTX_FRM_CONT_EN_POS) -#define IR_CR_IRTX_FRM_CONT_EN_UMSK (~(((1U << IR_CR_IRTX_FRM_CONT_EN_LEN) - 1) << IR_CR_IRTX_FRM_CONT_EN_POS)) -#define IR_CR_IRTX_FRM_FRAME_SIZE IR_CR_IRTX_FRM_FRAME_SIZE -#define IR_CR_IRTX_FRM_FRAME_SIZE_POS (14U) -#define IR_CR_IRTX_FRM_FRAME_SIZE_LEN (2U) -#define IR_CR_IRTX_FRM_FRAME_SIZE_MSK (((1U << IR_CR_IRTX_FRM_FRAME_SIZE_LEN) - 1) << IR_CR_IRTX_FRM_FRAME_SIZE_POS) -#define IR_CR_IRTX_FRM_FRAME_SIZE_UMSK (~(((1U << IR_CR_IRTX_FRM_FRAME_SIZE_LEN) - 1) << IR_CR_IRTX_FRM_FRAME_SIZE_POS)) -#define IR_CR_IRTX_DATA_NUM IR_CR_IRTX_DATA_NUM -#define IR_CR_IRTX_DATA_NUM_POS (16U) -#define IR_CR_IRTX_DATA_NUM_LEN (7U) -#define IR_CR_IRTX_DATA_NUM_MSK (((1U << IR_CR_IRTX_DATA_NUM_LEN) - 1) << IR_CR_IRTX_DATA_NUM_POS) -#define IR_CR_IRTX_DATA_NUM_UMSK (~(((1U << IR_CR_IRTX_DATA_NUM_LEN) - 1) << IR_CR_IRTX_DATA_NUM_POS)) - -/* 0x4 : irtx_int_sts */ -#define IRTX_INT_STS_OFFSET (0x4) -#define IRTX_END_INT IRTX_END_INT -#define IRTX_END_INT_POS (0U) -#define IRTX_END_INT_LEN (1U) -#define IRTX_END_INT_MSK (((1U << IRTX_END_INT_LEN) - 1) << IRTX_END_INT_POS) -#define IRTX_END_INT_UMSK (~(((1U << IRTX_END_INT_LEN) - 1) << IRTX_END_INT_POS)) -#define IRTX_FRDY_INT IRTX_FRDY_INT -#define IRTX_FRDY_INT_POS (1U) -#define IRTX_FRDY_INT_LEN (1U) -#define IRTX_FRDY_INT_MSK (((1U << IRTX_FRDY_INT_LEN) - 1) << IRTX_FRDY_INT_POS) -#define IRTX_FRDY_INT_UMSK (~(((1U << IRTX_FRDY_INT_LEN) - 1) << IRTX_FRDY_INT_POS)) -#define IRTX_FER_INT IRTX_FER_INT -#define IRTX_FER_INT_POS (2U) -#define IRTX_FER_INT_LEN (1U) -#define IRTX_FER_INT_MSK (((1U << IRTX_FER_INT_LEN) - 1) << IRTX_FER_INT_POS) -#define IRTX_FER_INT_UMSK (~(((1U << IRTX_FER_INT_LEN) - 1) << IRTX_FER_INT_POS)) -#define IR_CR_IRTX_END_MASK IR_CR_IRTX_END_MASK -#define IR_CR_IRTX_END_MASK_POS (8U) -#define IR_CR_IRTX_END_MASK_LEN (1U) -#define IR_CR_IRTX_END_MASK_MSK (((1U << IR_CR_IRTX_END_MASK_LEN) - 1) << IR_CR_IRTX_END_MASK_POS) -#define IR_CR_IRTX_END_MASK_UMSK (~(((1U << IR_CR_IRTX_END_MASK_LEN) - 1) << IR_CR_IRTX_END_MASK_POS)) -#define IR_CR_IRTX_FRDY_MASK IR_CR_IRTX_FRDY_MASK -#define IR_CR_IRTX_FRDY_MASK_POS (9U) -#define IR_CR_IRTX_FRDY_MASK_LEN (1U) -#define IR_CR_IRTX_FRDY_MASK_MSK (((1U << IR_CR_IRTX_FRDY_MASK_LEN) - 1) << IR_CR_IRTX_FRDY_MASK_POS) -#define IR_CR_IRTX_FRDY_MASK_UMSK (~(((1U << IR_CR_IRTX_FRDY_MASK_LEN) - 1) << IR_CR_IRTX_FRDY_MASK_POS)) -#define IR_CR_IRTX_FER_MASK IR_CR_IRTX_FER_MASK -#define IR_CR_IRTX_FER_MASK_POS (10U) -#define IR_CR_IRTX_FER_MASK_LEN (1U) -#define IR_CR_IRTX_FER_MASK_MSK (((1U << IR_CR_IRTX_FER_MASK_LEN) - 1) << IR_CR_IRTX_FER_MASK_POS) -#define IR_CR_IRTX_FER_MASK_UMSK (~(((1U << IR_CR_IRTX_FER_MASK_LEN) - 1) << IR_CR_IRTX_FER_MASK_POS)) -#define IR_CR_IRTX_END_CLR IR_CR_IRTX_END_CLR -#define IR_CR_IRTX_END_CLR_POS (16U) -#define IR_CR_IRTX_END_CLR_LEN (1U) -#define IR_CR_IRTX_END_CLR_MSK (((1U << IR_CR_IRTX_END_CLR_LEN) - 1) << IR_CR_IRTX_END_CLR_POS) -#define IR_CR_IRTX_END_CLR_UMSK (~(((1U << IR_CR_IRTX_END_CLR_LEN) - 1) << IR_CR_IRTX_END_CLR_POS)) -#define IR_CR_IRTX_END_EN IR_CR_IRTX_END_EN -#define IR_CR_IRTX_END_EN_POS (24U) -#define IR_CR_IRTX_END_EN_LEN (1U) -#define IR_CR_IRTX_END_EN_MSK (((1U << IR_CR_IRTX_END_EN_LEN) - 1) << IR_CR_IRTX_END_EN_POS) -#define IR_CR_IRTX_END_EN_UMSK (~(((1U << IR_CR_IRTX_END_EN_LEN) - 1) << IR_CR_IRTX_END_EN_POS)) -#define IR_CR_IRTX_FRDY_EN IR_CR_IRTX_FRDY_EN -#define IR_CR_IRTX_FRDY_EN_POS (25U) -#define IR_CR_IRTX_FRDY_EN_LEN (1U) -#define IR_CR_IRTX_FRDY_EN_MSK (((1U << IR_CR_IRTX_FRDY_EN_LEN) - 1) << IR_CR_IRTX_FRDY_EN_POS) -#define IR_CR_IRTX_FRDY_EN_UMSK (~(((1U << IR_CR_IRTX_FRDY_EN_LEN) - 1) << IR_CR_IRTX_FRDY_EN_POS)) -#define IR_CR_IRTX_FER_EN IR_CR_IRTX_FER_EN -#define IR_CR_IRTX_FER_EN_POS (26U) -#define IR_CR_IRTX_FER_EN_LEN (1U) -#define IR_CR_IRTX_FER_EN_MSK (((1U << IR_CR_IRTX_FER_EN_LEN) - 1) << IR_CR_IRTX_FER_EN_POS) -#define IR_CR_IRTX_FER_EN_UMSK (~(((1U << IR_CR_IRTX_FER_EN_LEN) - 1) << IR_CR_IRTX_FER_EN_POS)) - -/* 0x10 : irtx_pulse_width */ -#define IRTX_PULSE_WIDTH_OFFSET (0x10) -#define IR_CR_IRTX_PW_UNIT IR_CR_IRTX_PW_UNIT -#define IR_CR_IRTX_PW_UNIT_POS (0U) -#define IR_CR_IRTX_PW_UNIT_LEN (12U) -#define IR_CR_IRTX_PW_UNIT_MSK (((1U << IR_CR_IRTX_PW_UNIT_LEN) - 1) << IR_CR_IRTX_PW_UNIT_POS) -#define IR_CR_IRTX_PW_UNIT_UMSK (~(((1U << IR_CR_IRTX_PW_UNIT_LEN) - 1) << IR_CR_IRTX_PW_UNIT_POS)) -#define IR_CR_IRTX_MOD_PH0_W IR_CR_IRTX_MOD_PH0_W -#define IR_CR_IRTX_MOD_PH0_W_POS (16U) -#define IR_CR_IRTX_MOD_PH0_W_LEN (8U) -#define IR_CR_IRTX_MOD_PH0_W_MSK (((1U << IR_CR_IRTX_MOD_PH0_W_LEN) - 1) << IR_CR_IRTX_MOD_PH0_W_POS) -#define IR_CR_IRTX_MOD_PH0_W_UMSK (~(((1U << IR_CR_IRTX_MOD_PH0_W_LEN) - 1) << IR_CR_IRTX_MOD_PH0_W_POS)) -#define IR_CR_IRTX_MOD_PH1_W IR_CR_IRTX_MOD_PH1_W -#define IR_CR_IRTX_MOD_PH1_W_POS (24U) -#define IR_CR_IRTX_MOD_PH1_W_LEN (8U) -#define IR_CR_IRTX_MOD_PH1_W_MSK (((1U << IR_CR_IRTX_MOD_PH1_W_LEN) - 1) << IR_CR_IRTX_MOD_PH1_W_POS) -#define IR_CR_IRTX_MOD_PH1_W_UMSK (~(((1U << IR_CR_IRTX_MOD_PH1_W_LEN) - 1) << IR_CR_IRTX_MOD_PH1_W_POS)) - -/* 0x14 : irtx_pw_0 */ -#define IRTX_PW_0_OFFSET (0x14) -#define IR_CR_IRTX_LOGIC0_PH0_W IR_CR_IRTX_LOGIC0_PH0_W -#define IR_CR_IRTX_LOGIC0_PH0_W_POS (0U) -#define IR_CR_IRTX_LOGIC0_PH0_W_LEN (8U) -#define IR_CR_IRTX_LOGIC0_PH0_W_MSK (((1U << IR_CR_IRTX_LOGIC0_PH0_W_LEN) - 1) << IR_CR_IRTX_LOGIC0_PH0_W_POS) -#define IR_CR_IRTX_LOGIC0_PH0_W_UMSK (~(((1U << IR_CR_IRTX_LOGIC0_PH0_W_LEN) - 1) << IR_CR_IRTX_LOGIC0_PH0_W_POS)) -#define IR_CR_IRTX_LOGIC0_PH1_W IR_CR_IRTX_LOGIC0_PH1_W -#define IR_CR_IRTX_LOGIC0_PH1_W_POS (8U) -#define IR_CR_IRTX_LOGIC0_PH1_W_LEN (8U) -#define IR_CR_IRTX_LOGIC0_PH1_W_MSK (((1U << IR_CR_IRTX_LOGIC0_PH1_W_LEN) - 1) << IR_CR_IRTX_LOGIC0_PH1_W_POS) -#define IR_CR_IRTX_LOGIC0_PH1_W_UMSK (~(((1U << IR_CR_IRTX_LOGIC0_PH1_W_LEN) - 1) << IR_CR_IRTX_LOGIC0_PH1_W_POS)) -#define IR_CR_IRTX_LOGIC1_PH0_W IR_CR_IRTX_LOGIC1_PH0_W -#define IR_CR_IRTX_LOGIC1_PH0_W_POS (16U) -#define IR_CR_IRTX_LOGIC1_PH0_W_LEN (8U) -#define IR_CR_IRTX_LOGIC1_PH0_W_MSK (((1U << IR_CR_IRTX_LOGIC1_PH0_W_LEN) - 1) << IR_CR_IRTX_LOGIC1_PH0_W_POS) -#define IR_CR_IRTX_LOGIC1_PH0_W_UMSK (~(((1U << IR_CR_IRTX_LOGIC1_PH0_W_LEN) - 1) << IR_CR_IRTX_LOGIC1_PH0_W_POS)) -#define IR_CR_IRTX_LOGIC1_PH1_W IR_CR_IRTX_LOGIC1_PH1_W -#define IR_CR_IRTX_LOGIC1_PH1_W_POS (24U) -#define IR_CR_IRTX_LOGIC1_PH1_W_LEN (8U) -#define IR_CR_IRTX_LOGIC1_PH1_W_MSK (((1U << IR_CR_IRTX_LOGIC1_PH1_W_LEN) - 1) << IR_CR_IRTX_LOGIC1_PH1_W_POS) -#define IR_CR_IRTX_LOGIC1_PH1_W_UMSK (~(((1U << IR_CR_IRTX_LOGIC1_PH1_W_LEN) - 1) << IR_CR_IRTX_LOGIC1_PH1_W_POS)) - -/* 0x18 : irtx_pw_1 */ -#define IRTX_PW_1_OFFSET (0x18) -#define IR_CR_IRTX_HEAD_PH0_W IR_CR_IRTX_HEAD_PH0_W -#define IR_CR_IRTX_HEAD_PH0_W_POS (0U) -#define IR_CR_IRTX_HEAD_PH0_W_LEN (8U) -#define IR_CR_IRTX_HEAD_PH0_W_MSK (((1U << IR_CR_IRTX_HEAD_PH0_W_LEN) - 1) << IR_CR_IRTX_HEAD_PH0_W_POS) -#define IR_CR_IRTX_HEAD_PH0_W_UMSK (~(((1U << IR_CR_IRTX_HEAD_PH0_W_LEN) - 1) << IR_CR_IRTX_HEAD_PH0_W_POS)) -#define IR_CR_IRTX_HEAD_PH1_W IR_CR_IRTX_HEAD_PH1_W -#define IR_CR_IRTX_HEAD_PH1_W_POS (8U) -#define IR_CR_IRTX_HEAD_PH1_W_LEN (8U) -#define IR_CR_IRTX_HEAD_PH1_W_MSK (((1U << IR_CR_IRTX_HEAD_PH1_W_LEN) - 1) << IR_CR_IRTX_HEAD_PH1_W_POS) -#define IR_CR_IRTX_HEAD_PH1_W_UMSK (~(((1U << IR_CR_IRTX_HEAD_PH1_W_LEN) - 1) << IR_CR_IRTX_HEAD_PH1_W_POS)) -#define IR_CR_IRTX_TAIL_PH0_W IR_CR_IRTX_TAIL_PH0_W -#define IR_CR_IRTX_TAIL_PH0_W_POS (16U) -#define IR_CR_IRTX_TAIL_PH0_W_LEN (8U) -#define IR_CR_IRTX_TAIL_PH0_W_MSK (((1U << IR_CR_IRTX_TAIL_PH0_W_LEN) - 1) << IR_CR_IRTX_TAIL_PH0_W_POS) -#define IR_CR_IRTX_TAIL_PH0_W_UMSK (~(((1U << IR_CR_IRTX_TAIL_PH0_W_LEN) - 1) << IR_CR_IRTX_TAIL_PH0_W_POS)) -#define IR_CR_IRTX_TAIL_PH1_W IR_CR_IRTX_TAIL_PH1_W -#define IR_CR_IRTX_TAIL_PH1_W_POS (24U) -#define IR_CR_IRTX_TAIL_PH1_W_LEN (8U) -#define IR_CR_IRTX_TAIL_PH1_W_MSK (((1U << IR_CR_IRTX_TAIL_PH1_W_LEN) - 1) << IR_CR_IRTX_TAIL_PH1_W_POS) -#define IR_CR_IRTX_TAIL_PH1_W_UMSK (~(((1U << IR_CR_IRTX_TAIL_PH1_W_LEN) - 1) << IR_CR_IRTX_TAIL_PH1_W_POS)) - -/* 0x40 : irrx_config */ -#define IRRX_CONFIG_OFFSET (0x40) -#define IR_CR_IRRX_EN IR_CR_IRRX_EN -#define IR_CR_IRRX_EN_POS (0U) -#define IR_CR_IRRX_EN_LEN (1U) -#define IR_CR_IRRX_EN_MSK (((1U << IR_CR_IRRX_EN_LEN) - 1) << IR_CR_IRRX_EN_POS) -#define IR_CR_IRRX_EN_UMSK (~(((1U << IR_CR_IRRX_EN_LEN) - 1) << IR_CR_IRRX_EN_POS)) -#define IR_CR_IRRX_IN_INV IR_CR_IRRX_IN_INV -#define IR_CR_IRRX_IN_INV_POS (1U) -#define IR_CR_IRRX_IN_INV_LEN (1U) -#define IR_CR_IRRX_IN_INV_MSK (((1U << IR_CR_IRRX_IN_INV_LEN) - 1) << IR_CR_IRRX_IN_INV_POS) -#define IR_CR_IRRX_IN_INV_UMSK (~(((1U << IR_CR_IRRX_IN_INV_LEN) - 1) << IR_CR_IRRX_IN_INV_POS)) -#define IR_CR_IRRX_MODE IR_CR_IRRX_MODE -#define IR_CR_IRRX_MODE_POS (2U) -#define IR_CR_IRRX_MODE_LEN (2U) -#define IR_CR_IRRX_MODE_MSK (((1U << IR_CR_IRRX_MODE_LEN) - 1) << IR_CR_IRRX_MODE_POS) -#define IR_CR_IRRX_MODE_UMSK (~(((1U << IR_CR_IRRX_MODE_LEN) - 1) << IR_CR_IRRX_MODE_POS)) -#define IR_CR_IRRX_DEG_EN IR_CR_IRRX_DEG_EN -#define IR_CR_IRRX_DEG_EN_POS (4U) -#define IR_CR_IRRX_DEG_EN_LEN (1U) -#define IR_CR_IRRX_DEG_EN_MSK (((1U << IR_CR_IRRX_DEG_EN_LEN) - 1) << IR_CR_IRRX_DEG_EN_POS) -#define IR_CR_IRRX_DEG_EN_UMSK (~(((1U << IR_CR_IRRX_DEG_EN_LEN) - 1) << IR_CR_IRRX_DEG_EN_POS)) -#define IR_CR_IRRX_DEG_CNT IR_CR_IRRX_DEG_CNT -#define IR_CR_IRRX_DEG_CNT_POS (8U) -#define IR_CR_IRRX_DEG_CNT_LEN (4U) -#define IR_CR_IRRX_DEG_CNT_MSK (((1U << IR_CR_IRRX_DEG_CNT_LEN) - 1) << IR_CR_IRRX_DEG_CNT_POS) -#define IR_CR_IRRX_DEG_CNT_UMSK (~(((1U << IR_CR_IRRX_DEG_CNT_LEN) - 1) << IR_CR_IRRX_DEG_CNT_POS)) - -/* 0x44 : irrx_int_sts */ -#define IRRX_INT_STS_OFFSET (0x44) -#define IRRX_END_INT IRRX_END_INT -#define IRRX_END_INT_POS (0U) -#define IRRX_END_INT_LEN (1U) -#define IRRX_END_INT_MSK (((1U << IRRX_END_INT_LEN) - 1) << IRRX_END_INT_POS) -#define IRRX_END_INT_UMSK (~(((1U << IRRX_END_INT_LEN) - 1) << IRRX_END_INT_POS)) -#define IRRX_FRDY_INT IRRX_FRDY_INT -#define IRRX_FRDY_INT_POS (1U) -#define IRRX_FRDY_INT_LEN (1U) -#define IRRX_FRDY_INT_MSK (((1U << IRRX_FRDY_INT_LEN) - 1) << IRRX_FRDY_INT_POS) -#define IRRX_FRDY_INT_UMSK (~(((1U << IRRX_FRDY_INT_LEN) - 1) << IRRX_FRDY_INT_POS)) -#define IRRX_FER_INT IRRX_FER_INT -#define IRRX_FER_INT_POS (2U) -#define IRRX_FER_INT_LEN (1U) -#define IRRX_FER_INT_MSK (((1U << IRRX_FER_INT_LEN) - 1) << IRRX_FER_INT_POS) -#define IRRX_FER_INT_UMSK (~(((1U << IRRX_FER_INT_LEN) - 1) << IRRX_FER_INT_POS)) -#define IR_CR_IRRX_END_MASK IR_CR_IRRX_END_MASK -#define IR_CR_IRRX_END_MASK_POS (8U) -#define IR_CR_IRRX_END_MASK_LEN (1U) -#define IR_CR_IRRX_END_MASK_MSK (((1U << IR_CR_IRRX_END_MASK_LEN) - 1) << IR_CR_IRRX_END_MASK_POS) -#define IR_CR_IRRX_END_MASK_UMSK (~(((1U << IR_CR_IRRX_END_MASK_LEN) - 1) << IR_CR_IRRX_END_MASK_POS)) -#define IR_CR_IRRX_FRDY_MASK IR_CR_IRRX_FRDY_MASK -#define IR_CR_IRRX_FRDY_MASK_POS (9U) -#define IR_CR_IRRX_FRDY_MASK_LEN (1U) -#define IR_CR_IRRX_FRDY_MASK_MSK (((1U << IR_CR_IRRX_FRDY_MASK_LEN) - 1) << IR_CR_IRRX_FRDY_MASK_POS) -#define IR_CR_IRRX_FRDY_MASK_UMSK (~(((1U << IR_CR_IRRX_FRDY_MASK_LEN) - 1) << IR_CR_IRRX_FRDY_MASK_POS)) -#define IR_CR_IRRX_FER_MASK IR_CR_IRRX_FER_MASK -#define IR_CR_IRRX_FER_MASK_POS (10U) -#define IR_CR_IRRX_FER_MASK_LEN (1U) -#define IR_CR_IRRX_FER_MASK_MSK (((1U << IR_CR_IRRX_FER_MASK_LEN) - 1) << IR_CR_IRRX_FER_MASK_POS) -#define IR_CR_IRRX_FER_MASK_UMSK (~(((1U << IR_CR_IRRX_FER_MASK_LEN) - 1) << IR_CR_IRRX_FER_MASK_POS)) -#define IR_CR_IRRX_END_CLR IR_CR_IRRX_END_CLR -#define IR_CR_IRRX_END_CLR_POS (16U) -#define IR_CR_IRRX_END_CLR_LEN (1U) -#define IR_CR_IRRX_END_CLR_MSK (((1U << IR_CR_IRRX_END_CLR_LEN) - 1) << IR_CR_IRRX_END_CLR_POS) -#define IR_CR_IRRX_END_CLR_UMSK (~(((1U << IR_CR_IRRX_END_CLR_LEN) - 1) << IR_CR_IRRX_END_CLR_POS)) -#define IR_CR_IRRX_END_EN IR_CR_IRRX_END_EN -#define IR_CR_IRRX_END_EN_POS (24U) -#define IR_CR_IRRX_END_EN_LEN (1U) -#define IR_CR_IRRX_END_EN_MSK (((1U << IR_CR_IRRX_END_EN_LEN) - 1) << IR_CR_IRRX_END_EN_POS) -#define IR_CR_IRRX_END_EN_UMSK (~(((1U << IR_CR_IRRX_END_EN_LEN) - 1) << IR_CR_IRRX_END_EN_POS)) -#define IR_CR_IRRX_FRDY_EN IR_CR_IRRX_FRDY_EN -#define IR_CR_IRRX_FRDY_EN_POS (25U) -#define IR_CR_IRRX_FRDY_EN_LEN (1U) -#define IR_CR_IRRX_FRDY_EN_MSK (((1U << IR_CR_IRRX_FRDY_EN_LEN) - 1) << IR_CR_IRRX_FRDY_EN_POS) -#define IR_CR_IRRX_FRDY_EN_UMSK (~(((1U << IR_CR_IRRX_FRDY_EN_LEN) - 1) << IR_CR_IRRX_FRDY_EN_POS)) -#define IR_CR_IRRX_FER_EN IR_CR_IRRX_FER_EN -#define IR_CR_IRRX_FER_EN_POS (26U) -#define IR_CR_IRRX_FER_EN_LEN (1U) -#define IR_CR_IRRX_FER_EN_MSK (((1U << IR_CR_IRRX_FER_EN_LEN) - 1) << IR_CR_IRRX_FER_EN_POS) -#define IR_CR_IRRX_FER_EN_UMSK (~(((1U << IR_CR_IRRX_FER_EN_LEN) - 1) << IR_CR_IRRX_FER_EN_POS)) - -/* 0x48 : irrx_pw_config */ -#define IRRX_PW_CONFIG_OFFSET (0x48) -#define IR_CR_IRRX_DATA_TH IR_CR_IRRX_DATA_TH -#define IR_CR_IRRX_DATA_TH_POS (0U) -#define IR_CR_IRRX_DATA_TH_LEN (16U) -#define IR_CR_IRRX_DATA_TH_MSK (((1U << IR_CR_IRRX_DATA_TH_LEN) - 1) << IR_CR_IRRX_DATA_TH_POS) -#define IR_CR_IRRX_DATA_TH_UMSK (~(((1U << IR_CR_IRRX_DATA_TH_LEN) - 1) << IR_CR_IRRX_DATA_TH_POS)) -#define IR_CR_IRRX_END_TH IR_CR_IRRX_END_TH -#define IR_CR_IRRX_END_TH_POS (16U) -#define IR_CR_IRRX_END_TH_LEN (16U) -#define IR_CR_IRRX_END_TH_MSK (((1U << IR_CR_IRRX_END_TH_LEN) - 1) << IR_CR_IRRX_END_TH_POS) -#define IR_CR_IRRX_END_TH_UMSK (~(((1U << IR_CR_IRRX_END_TH_LEN) - 1) << IR_CR_IRRX_END_TH_POS)) - -/* 0x50 : irrx_data_count */ -#define IRRX_DATA_COUNT_OFFSET (0x50) -#define IR_STS_IRRX_DATA_CNT IR_STS_IRRX_DATA_CNT -#define IR_STS_IRRX_DATA_CNT_POS (0U) -#define IR_STS_IRRX_DATA_CNT_LEN (7U) -#define IR_STS_IRRX_DATA_CNT_MSK (((1U << IR_STS_IRRX_DATA_CNT_LEN) - 1) << IR_STS_IRRX_DATA_CNT_POS) -#define IR_STS_IRRX_DATA_CNT_UMSK (~(((1U << IR_STS_IRRX_DATA_CNT_LEN) - 1) << IR_STS_IRRX_DATA_CNT_POS)) - -/* 0x54 : irrx_data_word0 */ -#define IRRX_DATA_WORD0_OFFSET (0x54) -#define IR_STS_IRRX_DATA_WORD0 IR_STS_IRRX_DATA_WORD0 -#define IR_STS_IRRX_DATA_WORD0_POS (0U) -#define IR_STS_IRRX_DATA_WORD0_LEN (32U) -#define IR_STS_IRRX_DATA_WORD0_MSK (((1U << IR_STS_IRRX_DATA_WORD0_LEN) - 1) << IR_STS_IRRX_DATA_WORD0_POS) -#define IR_STS_IRRX_DATA_WORD0_UMSK (~(((1U << IR_STS_IRRX_DATA_WORD0_LEN) - 1) << IR_STS_IRRX_DATA_WORD0_POS)) - -/* 0x58 : irrx_data_word1 */ -#define IRRX_DATA_WORD1_OFFSET (0x58) -#define IR_STS_IRRX_DATA_WORD1 IR_STS_IRRX_DATA_WORD1 -#define IR_STS_IRRX_DATA_WORD1_POS (0U) -#define IR_STS_IRRX_DATA_WORD1_LEN (32U) -#define IR_STS_IRRX_DATA_WORD1_MSK (((1U << IR_STS_IRRX_DATA_WORD1_LEN) - 1) << IR_STS_IRRX_DATA_WORD1_POS) -#define IR_STS_IRRX_DATA_WORD1_UMSK (~(((1U << IR_STS_IRRX_DATA_WORD1_LEN) - 1) << IR_STS_IRRX_DATA_WORD1_POS)) - -/* 0x80 : irtx_fifo_config_0 */ -#define IRTX_FIFO_CONFIG_0_OFFSET (0x80) -#define IRTX_DMA_EN IRTX_DMA_EN -#define IRTX_DMA_EN_POS (0U) -#define IRTX_DMA_EN_LEN (1U) -#define IRTX_DMA_EN_MSK (((1U << IRTX_DMA_EN_LEN) - 1) << IRTX_DMA_EN_POS) -#define IRTX_DMA_EN_UMSK (~(((1U << IRTX_DMA_EN_LEN) - 1) << IRTX_DMA_EN_POS)) -#define IR_TX_FIFO_CLR IR_TX_FIFO_CLR -#define IR_TX_FIFO_CLR_POS (2U) -#define IR_TX_FIFO_CLR_LEN (1U) -#define IR_TX_FIFO_CLR_MSK (((1U << IR_TX_FIFO_CLR_LEN) - 1) << IR_TX_FIFO_CLR_POS) -#define IR_TX_FIFO_CLR_UMSK (~(((1U << IR_TX_FIFO_CLR_LEN) - 1) << IR_TX_FIFO_CLR_POS)) -#define IR_RX_FIFO_CLR IR_RX_FIFO_CLR -#define IR_RX_FIFO_CLR_POS (3U) -#define IR_RX_FIFO_CLR_LEN (1U) -#define IR_RX_FIFO_CLR_MSK (((1U << IR_RX_FIFO_CLR_LEN) - 1) << IR_RX_FIFO_CLR_POS) -#define IR_RX_FIFO_CLR_UMSK (~(((1U << IR_RX_FIFO_CLR_LEN) - 1) << IR_RX_FIFO_CLR_POS)) -#define IR_TX_FIFO_OVERFLOW IR_TX_FIFO_OVERFLOW -#define IR_TX_FIFO_OVERFLOW_POS (4U) -#define IR_TX_FIFO_OVERFLOW_LEN (1U) -#define IR_TX_FIFO_OVERFLOW_MSK (((1U << IR_TX_FIFO_OVERFLOW_LEN) - 1) << IR_TX_FIFO_OVERFLOW_POS) -#define IR_TX_FIFO_OVERFLOW_UMSK (~(((1U << IR_TX_FIFO_OVERFLOW_LEN) - 1) << IR_TX_FIFO_OVERFLOW_POS)) -#define IR_TX_FIFO_UNDERFLOW IR_TX_FIFO_UNDERFLOW -#define IR_TX_FIFO_UNDERFLOW_POS (5U) -#define IR_TX_FIFO_UNDERFLOW_LEN (1U) -#define IR_TX_FIFO_UNDERFLOW_MSK (((1U << IR_TX_FIFO_UNDERFLOW_LEN) - 1) << IR_TX_FIFO_UNDERFLOW_POS) -#define IR_TX_FIFO_UNDERFLOW_UMSK (~(((1U << IR_TX_FIFO_UNDERFLOW_LEN) - 1) << IR_TX_FIFO_UNDERFLOW_POS)) -#define IR_RX_FIFO_OVERFLOW IR_RX_FIFO_OVERFLOW -#define IR_RX_FIFO_OVERFLOW_POS (6U) -#define IR_RX_FIFO_OVERFLOW_LEN (1U) -#define IR_RX_FIFO_OVERFLOW_MSK (((1U << IR_RX_FIFO_OVERFLOW_LEN) - 1) << IR_RX_FIFO_OVERFLOW_POS) -#define IR_RX_FIFO_OVERFLOW_UMSK (~(((1U << IR_RX_FIFO_OVERFLOW_LEN) - 1) << IR_RX_FIFO_OVERFLOW_POS)) -#define IR_RX_FIFO_UNDERFLOW IR_RX_FIFO_UNDERFLOW -#define IR_RX_FIFO_UNDERFLOW_POS (7U) -#define IR_RX_FIFO_UNDERFLOW_LEN (1U) -#define IR_RX_FIFO_UNDERFLOW_MSK (((1U << IR_RX_FIFO_UNDERFLOW_LEN) - 1) << IR_RX_FIFO_UNDERFLOW_POS) -#define IR_RX_FIFO_UNDERFLOW_UMSK (~(((1U << IR_RX_FIFO_UNDERFLOW_LEN) - 1) << IR_RX_FIFO_UNDERFLOW_POS)) - -/* 0x84 : irtx_fifo_config_1 */ -#define IRTX_FIFO_CONFIG_1_OFFSET (0x84) -#define IR_TX_FIFO_CNT IR_TX_FIFO_CNT -#define IR_TX_FIFO_CNT_POS (0U) -#define IR_TX_FIFO_CNT_LEN (3U) -#define IR_TX_FIFO_CNT_MSK (((1U << IR_TX_FIFO_CNT_LEN) - 1) << IR_TX_FIFO_CNT_POS) -#define IR_TX_FIFO_CNT_UMSK (~(((1U << IR_TX_FIFO_CNT_LEN) - 1) << IR_TX_FIFO_CNT_POS)) -#define IR_RX_FIFO_CNT IR_RX_FIFO_CNT -#define IR_RX_FIFO_CNT_POS (8U) -#define IR_RX_FIFO_CNT_LEN (7U) -#define IR_RX_FIFO_CNT_MSK (((1U << IR_RX_FIFO_CNT_LEN) - 1) << IR_RX_FIFO_CNT_POS) -#define IR_RX_FIFO_CNT_UMSK (~(((1U << IR_RX_FIFO_CNT_LEN) - 1) << IR_RX_FIFO_CNT_POS)) -#define IR_TX_FIFO_TH IR_TX_FIFO_TH -#define IR_TX_FIFO_TH_POS (16U) -#define IR_TX_FIFO_TH_LEN (2U) -#define IR_TX_FIFO_TH_MSK (((1U << IR_TX_FIFO_TH_LEN) - 1) << IR_TX_FIFO_TH_POS) -#define IR_TX_FIFO_TH_UMSK (~(((1U << IR_TX_FIFO_TH_LEN) - 1) << IR_TX_FIFO_TH_POS)) -#define IR_RX_FIFO_TH IR_RX_FIFO_TH -#define IR_RX_FIFO_TH_POS (24U) -#define IR_RX_FIFO_TH_LEN (6U) -#define IR_RX_FIFO_TH_MSK (((1U << IR_RX_FIFO_TH_LEN) - 1) << IR_RX_FIFO_TH_POS) -#define IR_RX_FIFO_TH_UMSK (~(((1U << IR_RX_FIFO_TH_LEN) - 1) << IR_RX_FIFO_TH_POS)) - -/* 0x88 : ir_fifo_wdata */ -#define IR_FIFO_WDATA_OFFSET (0x88) -#define IR_TX_FIFO_WDATA IR_TX_FIFO_WDATA -#define IR_TX_FIFO_WDATA_POS (0U) -#define IR_TX_FIFO_WDATA_LEN (32U) -#define IR_TX_FIFO_WDATA_MSK (((1U << IR_TX_FIFO_WDATA_LEN) - 1) << IR_TX_FIFO_WDATA_POS) -#define IR_TX_FIFO_WDATA_UMSK (~(((1U << IR_TX_FIFO_WDATA_LEN) - 1) << IR_TX_FIFO_WDATA_POS)) - -/* 0x8C : ir_fifo_rdata */ -#define IR_FIFO_RDATA_OFFSET (0x8C) -#define IR_RX_FIFO_RDATA IR_RX_FIFO_RDATA -#define IR_RX_FIFO_RDATA_POS (0U) -#define IR_RX_FIFO_RDATA_LEN (16U) -#define IR_RX_FIFO_RDATA_MSK (((1U << IR_RX_FIFO_RDATA_LEN) - 1) << IR_RX_FIFO_RDATA_POS) -#define IR_RX_FIFO_RDATA_UMSK (~(((1U << IR_RX_FIFO_RDATA_LEN) - 1) << IR_RX_FIFO_RDATA_POS)) - -struct ir_reg { - /* 0x0 : irtx_config */ - union { - struct { - uint32_t cr_irtx_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t cr_irtx_out_inv : 1; /* [ 1], r/w, 0x0 */ - uint32_t cr_irtx_mod_en : 1; /* [ 2], r/w, 0x0 */ - uint32_t cr_irtx_swm_en : 1; /* [ 3], r/w, 0x0 */ - uint32_t cr_irtx_data_en : 1; /* [ 4], r/w, 0x1 */ - uint32_t cr_irtx_logic0_hl_inv : 1; /* [ 5], r/w, 0x0 */ - uint32_t cr_irtx_logic1_hl_inv : 1; /* [ 6], r/w, 0x0 */ - uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ - uint32_t cr_irtx_head_en : 1; /* [ 8], r/w, 0x1 */ - uint32_t cr_irtx_head_hl_inv : 1; /* [ 9], r/w, 0x0 */ - uint32_t cr_irtx_tail_en : 1; /* [ 10], r/w, 0x1 */ - uint32_t cr_irtx_tail_hl_inv : 1; /* [ 11], r/w, 0x0 */ - uint32_t cr_irtx_frm_en : 1; /* [ 12], r/w, 0x0 */ - uint32_t cr_irtx_frm_cont_en : 1; /* [ 13], r/w, 0x0 */ - uint32_t cr_irtx_frm_frame_size : 2; /* [15:14], r/w, 0x0 */ - uint32_t cr_irtx_data_num : 7; /* [22:16], r/w, 0x1f */ - uint32_t reserved_23_31 : 9; /* [31:23], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } irtx_config; - - /* 0x4 : irtx_int_sts */ - union { - struct { - uint32_t irtx_end_int : 1; /* [ 0], r, 0x0 */ - uint32_t irtx_frdy_int : 1; /* [ 1], r, 0x1 */ - uint32_t irtx_fer_int : 1; /* [ 2], r, 0x0 */ - uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */ - uint32_t cr_irtx_end_mask : 1; /* [ 8], r/w, 0x1 */ - uint32_t cr_irtx_frdy_mask : 1; /* [ 9], r/w, 0x1 */ - uint32_t cr_irtx_fer_mask : 1; /* [ 10], r/w, 0x1 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t cr_irtx_end_clr : 1; /* [ 16], w1c, 0x0 */ - uint32_t rsvd_17 : 1; /* [ 17], rsvd, 0x0 */ - uint32_t rsvd_18 : 1; /* [ 18], rsvd, 0x0 */ - uint32_t reserved_19_23 : 5; /* [23:19], rsvd, 0x0 */ - uint32_t cr_irtx_end_en : 1; /* [ 24], r/w, 0x1 */ - uint32_t cr_irtx_frdy_en : 1; /* [ 25], r/w, 0x1 */ - uint32_t cr_irtx_fer_en : 1; /* [ 26], r/w, 0x1 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } irtx_int_sts; - - /* 0x8 reserved */ - uint8_t RESERVED0x8[8]; - - /* 0x10 : irtx_pulse_width */ - union { - struct { - uint32_t cr_irtx_pw_unit : 12; /* [11: 0], r/w, 0x464 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t cr_irtx_mod_ph0_w : 8; /* [23:16], r/w, 0x11 */ - uint32_t cr_irtx_mod_ph1_w : 8; /* [31:24], r/w, 0x22 */ - } BF; - uint32_t WORD; - } irtx_pulse_width; - - /* 0x14 : irtx_pw_0 */ - union { - struct { - uint32_t cr_irtx_logic0_ph0_w : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t cr_irtx_logic0_ph1_w : 8; /* [15: 8], r/w, 0x0 */ - uint32_t cr_irtx_logic1_ph0_w : 8; /* [23:16], r/w, 0x0 */ - uint32_t cr_irtx_logic1_ph1_w : 8; /* [31:24], r/w, 0x2 */ - } BF; - uint32_t WORD; - } irtx_pw_0; - - /* 0x18 : irtx_pw_1 */ - union { - struct { - uint32_t cr_irtx_head_ph0_w : 8; /* [ 7: 0], r/w, 0xf */ - uint32_t cr_irtx_head_ph1_w : 8; /* [15: 8], r/w, 0x7 */ - uint32_t cr_irtx_tail_ph0_w : 8; /* [23:16], r/w, 0x0 */ - uint32_t cr_irtx_tail_ph1_w : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } irtx_pw_1; - - /* 0x1c reserved */ - uint8_t RESERVED0x1c[36]; - - /* 0x40 : irrx_config */ - union { - struct { - uint32_t cr_irrx_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t cr_irrx_in_inv : 1; /* [ 1], r/w, 0x1 */ - uint32_t cr_irrx_mode : 2; /* [ 3: 2], r/w, 0x0 */ - uint32_t cr_irrx_deg_en : 1; /* [ 4], r/w, 0x0 */ - uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ - uint32_t cr_irrx_deg_cnt : 4; /* [11: 8], r/w, 0x0 */ - uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } irrx_config; - - /* 0x44 : irrx_int_sts */ - union { - struct { - uint32_t irrx_end_int : 1; /* [ 0], r, 0x0 */ - uint32_t irrx_frdy_int : 1; /* [ 1], r, 0x0 */ - uint32_t irrx_fer_int : 1; /* [ 2], r, 0x0 */ - uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */ - uint32_t cr_irrx_end_mask : 1; /* [ 8], r/w, 0x1 */ - uint32_t cr_irrx_frdy_mask : 1; /* [ 9], r/w, 0x1 */ - uint32_t cr_irrx_fer_mask : 1; /* [ 10], r/w, 0x1 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t cr_irrx_end_clr : 1; /* [ 16], w1c, 0x0 */ - uint32_t rsvd_17 : 1; /* [ 17], rsvd, 0x0 */ - uint32_t rsvd_18 : 1; /* [ 18], rsvd, 0x0 */ - uint32_t reserved_19_23 : 5; /* [23:19], rsvd, 0x0 */ - uint32_t cr_irrx_end_en : 1; /* [ 24], r/w, 0x1 */ - uint32_t cr_irrx_frdy_en : 1; /* [ 25], r/w, 0x1 */ - uint32_t cr_irrx_fer_en : 1; /* [ 26], r/w, 0x1 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } irrx_int_sts; - - /* 0x48 : irrx_pw_config */ - union { - struct { - uint32_t cr_irrx_data_th : 16; /* [15: 0], r/w, 0xd47 */ - uint32_t cr_irrx_end_th : 16; /* [31:16], r/w, 0x2327 */ - } BF; - uint32_t WORD; - } irrx_pw_config; - - /* 0x4c reserved */ - uint8_t RESERVED0x4c[4]; - - /* 0x50 : irrx_data_count */ - union { - struct { - uint32_t sts_irrx_data_cnt : 7; /* [ 6: 0], r, 0x0 */ - uint32_t reserved_7_31 : 25; /* [31: 7], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } irrx_data_count; - - /* 0x54 : irrx_data_word0 */ - union { - struct { - uint32_t sts_irrx_data_word0 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } irrx_data_word0; - - /* 0x58 : irrx_data_word1 */ - union { - struct { - uint32_t sts_irrx_data_word1 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } irrx_data_word1; - - /* 0x5c reserved */ - uint8_t RESERVED0x5c[36]; - - /* 0x80 : irtx_fifo_config_0 */ - union { - struct { - uint32_t irtx_dma_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t rsvd_1 : 1; /* [ 1], rsvd, 0x0 */ - uint32_t tx_fifo_clr : 1; /* [ 2], w1c, 0x0 */ - uint32_t rx_fifo_clr : 1; /* [ 3], w1c, 0x0 */ - uint32_t tx_fifo_overflow : 1; /* [ 4], r, 0x0 */ - uint32_t tx_fifo_underflow : 1; /* [ 5], r, 0x0 */ - uint32_t rx_fifo_overflow : 1; /* [ 6], r, 0x0 */ - uint32_t rx_fifo_underflow : 1; /* [ 7], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } irtx_fifo_config_0; - - /* 0x84 : irtx_fifo_config_1 */ - union { - struct { - uint32_t tx_fifo_cnt : 3; /* [ 2: 0], r, 0x4 */ - uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */ - uint32_t rx_fifo_cnt : 7; /* [14: 8], r, 0x0 */ - uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */ - uint32_t tx_fifo_th : 2; /* [17:16], r/w, 0x0 */ - uint32_t reserved_18_23 : 6; /* [23:18], rsvd, 0x0 */ - uint32_t rx_fifo_th : 6; /* [29:24], r/w, 0x0 */ - uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } irtx_fifo_config_1; - - /* 0x88 : ir_fifo_wdata */ - union { - struct { - uint32_t tx_fifo_wdata : 32; /* [31: 0], w, 0x0 */ - } BF; - uint32_t WORD; - } ir_fifo_wdata; - - /* 0x8C : ir_fifo_rdata */ - union { - struct { - uint32_t rx_fifo_rdata : 16; /* [15: 0], r, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } ir_fifo_rdata; -}; - -typedef volatile struct ir_reg ir_reg_t; - -#endif /* __IR_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/iso11898_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/iso11898_reg.h deleted file mode 100644 index 96b9e9dcf2..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/iso11898_reg.h +++ /dev/null @@ -1,807 +0,0 @@ -/** - ****************************************************************************** - * @file iso11898_reg.h - * @version V1.0 - * @date 2020-12-29 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __ISO11898_REG_H__ -#define __ISO11898_REG_H__ - -#include "bl808.h" - -/* 0x0 : op mode:rw reset mode:rw */ -#define ISO11898_MODE_OFFSET (0x0) -#define ISO11898_RESET_REQUEST ISO11898_RESET_REQUEST -#define ISO11898_RESET_REQUEST_POS (0U) -#define ISO11898_RESET_REQUEST_LEN (1U) -#define ISO11898_RESET_REQUEST_MSK (((1U << ISO11898_RESET_REQUEST_LEN) - 1) << ISO11898_RESET_REQUEST_POS) -#define ISO11898_RESET_REQUEST_UMSK (~(((1U << ISO11898_RESET_REQUEST_LEN) - 1) << ISO11898_RESET_REQUEST_POS)) -#define ISO11898_LISTEN_ONLY ISO11898_LISTEN_ONLY -#define ISO11898_LISTEN_ONLY_POS (1U) -#define ISO11898_LISTEN_ONLY_LEN (1U) -#define ISO11898_LISTEN_ONLY_MSK (((1U << ISO11898_LISTEN_ONLY_LEN) - 1) << ISO11898_LISTEN_ONLY_POS) -#define ISO11898_LISTEN_ONLY_UMSK (~(((1U << ISO11898_LISTEN_ONLY_LEN) - 1) << ISO11898_LISTEN_ONLY_POS)) -#define ISO11898_SELT_TEST ISO11898_SELT_TEST -#define ISO11898_SELT_TEST_POS (2U) -#define ISO11898_SELT_TEST_LEN (1U) -#define ISO11898_SELT_TEST_MSK (((1U << ISO11898_SELT_TEST_LEN) - 1) << ISO11898_SELT_TEST_POS) -#define ISO11898_SELT_TEST_UMSK (~(((1U << ISO11898_SELT_TEST_LEN) - 1) << ISO11898_SELT_TEST_POS)) -#define ISO11898_ACCEPTANCE_FILTER ISO11898_ACCEPTANCE_FILTER -#define ISO11898_ACCEPTANCE_FILTER_POS (3U) -#define ISO11898_ACCEPTANCE_FILTER_LEN (1U) -#define ISO11898_ACCEPTANCE_FILTER_MSK (((1U << ISO11898_ACCEPTANCE_FILTER_LEN) - 1) << ISO11898_ACCEPTANCE_FILTER_POS) -#define ISO11898_ACCEPTANCE_FILTER_UMSK (~(((1U << ISO11898_ACCEPTANCE_FILTER_LEN) - 1) << ISO11898_ACCEPTANCE_FILTER_POS)) - -/* 0x4 : op mode:w r -> 8'h00 -reset mode:w r -> 8'h00 */ -#define ISO11898_COMMAND_OFFSET (0x4) -#define ISO11898_TRANSMIT_REQUEST ISO11898_TRANSMIT_REQUEST -#define ISO11898_TRANSMIT_REQUEST_POS (0U) -#define ISO11898_TRANSMIT_REQUEST_LEN (1U) -#define ISO11898_TRANSMIT_REQUEST_MSK (((1U << ISO11898_TRANSMIT_REQUEST_LEN) - 1) << ISO11898_TRANSMIT_REQUEST_POS) -#define ISO11898_TRANSMIT_REQUEST_UMSK (~(((1U << ISO11898_TRANSMIT_REQUEST_LEN) - 1) << ISO11898_TRANSMIT_REQUEST_POS)) -#define ISO11898_ABORT_TRANSMISSION ISO11898_ABORT_TRANSMISSION -#define ISO11898_ABORT_TRANSMISSION_POS (1U) -#define ISO11898_ABORT_TRANSMISSION_LEN (1U) -#define ISO11898_ABORT_TRANSMISSION_MSK (((1U << ISO11898_ABORT_TRANSMISSION_LEN) - 1) << ISO11898_ABORT_TRANSMISSION_POS) -#define ISO11898_ABORT_TRANSMISSION_UMSK (~(((1U << ISO11898_ABORT_TRANSMISSION_LEN) - 1) << ISO11898_ABORT_TRANSMISSION_POS)) -#define ISO11898_RELEASE_RECEIVE_BUFFER ISO11898_RELEASE_RECEIVE_BUFFER -#define ISO11898_RELEASE_RECEIVE_BUFFER_POS (2U) -#define ISO11898_RELEASE_RECEIVE_BUFFER_LEN (1U) -#define ISO11898_RELEASE_RECEIVE_BUFFER_MSK (((1U << ISO11898_RELEASE_RECEIVE_BUFFER_LEN) - 1) << ISO11898_RELEASE_RECEIVE_BUFFER_POS) -#define ISO11898_RELEASE_RECEIVE_BUFFER_UMSK (~(((1U << ISO11898_RELEASE_RECEIVE_BUFFER_LEN) - 1) << ISO11898_RELEASE_RECEIVE_BUFFER_POS)) -#define ISO11898_CLEAR_DATA_OVERRUN ISO11898_CLEAR_DATA_OVERRUN -#define ISO11898_CLEAR_DATA_OVERRUN_POS (3U) -#define ISO11898_CLEAR_DATA_OVERRUN_LEN (1U) -#define ISO11898_CLEAR_DATA_OVERRUN_MSK (((1U << ISO11898_CLEAR_DATA_OVERRUN_LEN) - 1) << ISO11898_CLEAR_DATA_OVERRUN_POS) -#define ISO11898_CLEAR_DATA_OVERRUN_UMSK (~(((1U << ISO11898_CLEAR_DATA_OVERRUN_LEN) - 1) << ISO11898_CLEAR_DATA_OVERRUN_POS)) -#define ISO11898_SELF_REQUEST ISO11898_SELF_REQUEST -#define ISO11898_SELF_REQUEST_POS (4U) -#define ISO11898_SELF_REQUEST_LEN (1U) -#define ISO11898_SELF_REQUEST_MSK (((1U << ISO11898_SELF_REQUEST_LEN) - 1) << ISO11898_SELF_REQUEST_POS) -#define ISO11898_SELF_REQUEST_UMSK (~(((1U << ISO11898_SELF_REQUEST_LEN) - 1) << ISO11898_SELF_REQUEST_POS)) - -/* 0x8 : op mode:r reset mode:r */ -#define ISO11898_STATUS_OFFSET (0x8) -#define ISO11898_RECEIVE_BUFFER_STS ISO11898_RECEIVE_BUFFER_STS -#define ISO11898_RECEIVE_BUFFER_STS_POS (0U) -#define ISO11898_RECEIVE_BUFFER_STS_LEN (1U) -#define ISO11898_RECEIVE_BUFFER_STS_MSK (((1U << ISO11898_RECEIVE_BUFFER_STS_LEN) - 1) << ISO11898_RECEIVE_BUFFER_STS_POS) -#define ISO11898_RECEIVE_BUFFER_STS_UMSK (~(((1U << ISO11898_RECEIVE_BUFFER_STS_LEN) - 1) << ISO11898_RECEIVE_BUFFER_STS_POS)) -#define ISO11898_DATA_OVERRUN_STS ISO11898_DATA_OVERRUN_STS -#define ISO11898_DATA_OVERRUN_STS_POS (1U) -#define ISO11898_DATA_OVERRUN_STS_LEN (1U) -#define ISO11898_DATA_OVERRUN_STS_MSK (((1U << ISO11898_DATA_OVERRUN_STS_LEN) - 1) << ISO11898_DATA_OVERRUN_STS_POS) -#define ISO11898_DATA_OVERRUN_STS_UMSK (~(((1U << ISO11898_DATA_OVERRUN_STS_LEN) - 1) << ISO11898_DATA_OVERRUN_STS_POS)) -#define ISO11898_TRANSMIT_BUFFER_STS ISO11898_TRANSMIT_BUFFER_STS -#define ISO11898_TRANSMIT_BUFFER_STS_POS (2U) -#define ISO11898_TRANSMIT_BUFFER_STS_LEN (1U) -#define ISO11898_TRANSMIT_BUFFER_STS_MSK (((1U << ISO11898_TRANSMIT_BUFFER_STS_LEN) - 1) << ISO11898_TRANSMIT_BUFFER_STS_POS) -#define ISO11898_TRANSMIT_BUFFER_STS_UMSK (~(((1U << ISO11898_TRANSMIT_BUFFER_STS_LEN) - 1) << ISO11898_TRANSMIT_BUFFER_STS_POS)) -#define ISO11898_TRANSMIT_COMPLETE_STS ISO11898_TRANSMIT_COMPLETE_STS -#define ISO11898_TRANSMIT_COMPLETE_STS_POS (3U) -#define ISO11898_TRANSMIT_COMPLETE_STS_LEN (1U) -#define ISO11898_TRANSMIT_COMPLETE_STS_MSK (((1U << ISO11898_TRANSMIT_COMPLETE_STS_LEN) - 1) << ISO11898_TRANSMIT_COMPLETE_STS_POS) -#define ISO11898_TRANSMIT_COMPLETE_STS_UMSK (~(((1U << ISO11898_TRANSMIT_COMPLETE_STS_LEN) - 1) << ISO11898_TRANSMIT_COMPLETE_STS_POS)) -#define ISO11898_RECEIVE_STS ISO11898_RECEIVE_STS -#define ISO11898_RECEIVE_STS_POS (4U) -#define ISO11898_RECEIVE_STS_LEN (1U) -#define ISO11898_RECEIVE_STS_MSK (((1U << ISO11898_RECEIVE_STS_LEN) - 1) << ISO11898_RECEIVE_STS_POS) -#define ISO11898_RECEIVE_STS_UMSK (~(((1U << ISO11898_RECEIVE_STS_LEN) - 1) << ISO11898_RECEIVE_STS_POS)) -#define ISO11898_TRANSMIT_STS ISO11898_TRANSMIT_STS -#define ISO11898_TRANSMIT_STS_POS (5U) -#define ISO11898_TRANSMIT_STS_LEN (1U) -#define ISO11898_TRANSMIT_STS_MSK (((1U << ISO11898_TRANSMIT_STS_LEN) - 1) << ISO11898_TRANSMIT_STS_POS) -#define ISO11898_TRANSMIT_STS_UMSK (~(((1U << ISO11898_TRANSMIT_STS_LEN) - 1) << ISO11898_TRANSMIT_STS_POS)) -#define ISO11898_ERROR_STS ISO11898_ERROR_STS -#define ISO11898_ERROR_STS_POS (6U) -#define ISO11898_ERROR_STS_LEN (1U) -#define ISO11898_ERROR_STS_MSK (((1U << ISO11898_ERROR_STS_LEN) - 1) << ISO11898_ERROR_STS_POS) -#define ISO11898_ERROR_STS_UMSK (~(((1U << ISO11898_ERROR_STS_LEN) - 1) << ISO11898_ERROR_STS_POS)) -#define ISO11898_BUS_STS ISO11898_BUS_STS -#define ISO11898_BUS_STS_POS (7U) -#define ISO11898_BUS_STS_LEN (1U) -#define ISO11898_BUS_STS_MSK (((1U << ISO11898_BUS_STS_LEN) - 1) << ISO11898_BUS_STS_POS) -#define ISO11898_BUS_STS_UMSK (~(((1U << ISO11898_BUS_STS_LEN) - 1) << ISO11898_BUS_STS_POS)) - -/* 0xc : op mode:r reset mode:r when be read,all bits are reseted and iso11898_int disappear */ -#define ISO11898_INTERRUPT_OFFSET (0xc) -#define ISO11898_RECEIVE_INT ISO11898_RECEIVE_INT -#define ISO11898_RECEIVE_INT_POS (0U) -#define ISO11898_RECEIVE_INT_LEN (1U) -#define ISO11898_RECEIVE_INT_MSK (((1U << ISO11898_RECEIVE_INT_LEN) - 1) << ISO11898_RECEIVE_INT_POS) -#define ISO11898_RECEIVE_INT_UMSK (~(((1U << ISO11898_RECEIVE_INT_LEN) - 1) << ISO11898_RECEIVE_INT_POS)) -#define ISO11898_TRANSMIT_INT ISO11898_TRANSMIT_INT -#define ISO11898_TRANSMIT_INT_POS (1U) -#define ISO11898_TRANSMIT_INT_LEN (1U) -#define ISO11898_TRANSMIT_INT_MSK (((1U << ISO11898_TRANSMIT_INT_LEN) - 1) << ISO11898_TRANSMIT_INT_POS) -#define ISO11898_TRANSMIT_INT_UMSK (~(((1U << ISO11898_TRANSMIT_INT_LEN) - 1) << ISO11898_TRANSMIT_INT_POS)) -#define ISO11898_ERROR_INT ISO11898_ERROR_INT -#define ISO11898_ERROR_INT_POS (2U) -#define ISO11898_ERROR_INT_LEN (1U) -#define ISO11898_ERROR_INT_MSK (((1U << ISO11898_ERROR_INT_LEN) - 1) << ISO11898_ERROR_INT_POS) -#define ISO11898_ERROR_INT_UMSK (~(((1U << ISO11898_ERROR_INT_LEN) - 1) << ISO11898_ERROR_INT_POS)) -#define ISO11898_DATA_OVERRUN_INT ISO11898_DATA_OVERRUN_INT -#define ISO11898_DATA_OVERRUN_INT_POS (3U) -#define ISO11898_DATA_OVERRUN_INT_LEN (1U) -#define ISO11898_DATA_OVERRUN_INT_MSK (((1U << ISO11898_DATA_OVERRUN_INT_LEN) - 1) << ISO11898_DATA_OVERRUN_INT_POS) -#define ISO11898_DATA_OVERRUN_INT_UMSK (~(((1U << ISO11898_DATA_OVERRUN_INT_LEN) - 1) << ISO11898_DATA_OVERRUN_INT_POS)) -#define ISO11898_ERROR_PASSIVE_INT ISO11898_ERROR_PASSIVE_INT -#define ISO11898_ERROR_PASSIVE_INT_POS (5U) -#define ISO11898_ERROR_PASSIVE_INT_LEN (1U) -#define ISO11898_ERROR_PASSIVE_INT_MSK (((1U << ISO11898_ERROR_PASSIVE_INT_LEN) - 1) << ISO11898_ERROR_PASSIVE_INT_POS) -#define ISO11898_ERROR_PASSIVE_INT_UMSK (~(((1U << ISO11898_ERROR_PASSIVE_INT_LEN) - 1) << ISO11898_ERROR_PASSIVE_INT_POS)) -#define ISO11898_ARB_LOST_INT ISO11898_ARB_LOST_INT -#define ISO11898_ARB_LOST_INT_POS (6U) -#define ISO11898_ARB_LOST_INT_LEN (1U) -#define ISO11898_ARB_LOST_INT_MSK (((1U << ISO11898_ARB_LOST_INT_LEN) - 1) << ISO11898_ARB_LOST_INT_POS) -#define ISO11898_ARB_LOST_INT_UMSK (~(((1U << ISO11898_ARB_LOST_INT_LEN) - 1) << ISO11898_ARB_LOST_INT_POS)) -#define ISO11898_BUS_ERROR_INT ISO11898_BUS_ERROR_INT -#define ISO11898_BUS_ERROR_INT_POS (7U) -#define ISO11898_BUS_ERROR_INT_LEN (1U) -#define ISO11898_BUS_ERROR_INT_MSK (((1U << ISO11898_BUS_ERROR_INT_LEN) - 1) << ISO11898_BUS_ERROR_INT_POS) -#define ISO11898_BUS_ERROR_INT_UMSK (~(((1U << ISO11898_BUS_ERROR_INT_LEN) - 1) << ISO11898_BUS_ERROR_INT_POS)) - -/* 0x10 : op mode:rw reset mode:rw when be read,all bits are reseted and iso11898_int disappear */ -#define ISO11898_INTERRUPT_ENABLE_OFFSET (0x10) -#define ISO11898_RECEIVE_INT_EN ISO11898_RECEIVE_INT_EN -#define ISO11898_RECEIVE_INT_EN_POS (0U) -#define ISO11898_RECEIVE_INT_EN_LEN (1U) -#define ISO11898_RECEIVE_INT_EN_MSK (((1U << ISO11898_RECEIVE_INT_EN_LEN) - 1) << ISO11898_RECEIVE_INT_EN_POS) -#define ISO11898_RECEIVE_INT_EN_UMSK (~(((1U << ISO11898_RECEIVE_INT_EN_LEN) - 1) << ISO11898_RECEIVE_INT_EN_POS)) -#define ISO11898_TRANSMIT_INT_EN ISO11898_TRANSMIT_INT_EN -#define ISO11898_TRANSMIT_INT_EN_POS (1U) -#define ISO11898_TRANSMIT_INT_EN_LEN (1U) -#define ISO11898_TRANSMIT_INT_EN_MSK (((1U << ISO11898_TRANSMIT_INT_EN_LEN) - 1) << ISO11898_TRANSMIT_INT_EN_POS) -#define ISO11898_TRANSMIT_INT_EN_UMSK (~(((1U << ISO11898_TRANSMIT_INT_EN_LEN) - 1) << ISO11898_TRANSMIT_INT_EN_POS)) -#define ISO11898_ERROR_INT_EN ISO11898_ERROR_INT_EN -#define ISO11898_ERROR_INT_EN_POS (2U) -#define ISO11898_ERROR_INT_EN_LEN (1U) -#define ISO11898_ERROR_INT_EN_MSK (((1U << ISO11898_ERROR_INT_EN_LEN) - 1) << ISO11898_ERROR_INT_EN_POS) -#define ISO11898_ERROR_INT_EN_UMSK (~(((1U << ISO11898_ERROR_INT_EN_LEN) - 1) << ISO11898_ERROR_INT_EN_POS)) -#define ISO11898_DATA_OVERRUN_INT_EN ISO11898_DATA_OVERRUN_INT_EN -#define ISO11898_DATA_OVERRUN_INT_EN_POS (3U) -#define ISO11898_DATA_OVERRUN_INT_EN_LEN (1U) -#define ISO11898_DATA_OVERRUN_INT_EN_MSK (((1U << ISO11898_DATA_OVERRUN_INT_EN_LEN) - 1) << ISO11898_DATA_OVERRUN_INT_EN_POS) -#define ISO11898_DATA_OVERRUN_INT_EN_UMSK (~(((1U << ISO11898_DATA_OVERRUN_INT_EN_LEN) - 1) << ISO11898_DATA_OVERRUN_INT_EN_POS)) -#define ISO11898_ERROR_PASSIVE_INT_EN ISO11898_ERROR_PASSIVE_INT_EN -#define ISO11898_ERROR_PASSIVE_INT_EN_POS (5U) -#define ISO11898_ERROR_PASSIVE_INT_EN_LEN (1U) -#define ISO11898_ERROR_PASSIVE_INT_EN_MSK (((1U << ISO11898_ERROR_PASSIVE_INT_EN_LEN) - 1) << ISO11898_ERROR_PASSIVE_INT_EN_POS) -#define ISO11898_ERROR_PASSIVE_INT_EN_UMSK (~(((1U << ISO11898_ERROR_PASSIVE_INT_EN_LEN) - 1) << ISO11898_ERROR_PASSIVE_INT_EN_POS)) -#define ISO11898_ARB_LOST_INT_EN ISO11898_ARB_LOST_INT_EN -#define ISO11898_ARB_LOST_INT_EN_POS (6U) -#define ISO11898_ARB_LOST_INT_EN_LEN (1U) -#define ISO11898_ARB_LOST_INT_EN_MSK (((1U << ISO11898_ARB_LOST_INT_EN_LEN) - 1) << ISO11898_ARB_LOST_INT_EN_POS) -#define ISO11898_ARB_LOST_INT_EN_UMSK (~(((1U << ISO11898_ARB_LOST_INT_EN_LEN) - 1) << ISO11898_ARB_LOST_INT_EN_POS)) -#define ISO11898_BUS_ERROR_INT_EN ISO11898_BUS_ERROR_INT_EN -#define ISO11898_BUS_ERROR_INT_EN_POS (7U) -#define ISO11898_BUS_ERROR_INT_EN_LEN (1U) -#define ISO11898_BUS_ERROR_INT_EN_MSK (((1U << ISO11898_BUS_ERROR_INT_EN_LEN) - 1) << ISO11898_BUS_ERROR_INT_EN_POS) -#define ISO11898_BUS_ERROR_INT_EN_UMSK (~(((1U << ISO11898_BUS_ERROR_INT_EN_LEN) - 1) << ISO11898_BUS_ERROR_INT_EN_POS)) - -/* 0x18 : op mode:r reset mode:rw */ -#define ISO11898_BUS_TIMING_0_OFFSET (0x18) -#define ISO11898_BAUD_RATE_PRESCALER ISO11898_BAUD_RATE_PRESCALER -#define ISO11898_BAUD_RATE_PRESCALER_POS (0U) -#define ISO11898_BAUD_RATE_PRESCALER_LEN (6U) -#define ISO11898_BAUD_RATE_PRESCALER_MSK (((1U << ISO11898_BAUD_RATE_PRESCALER_LEN) - 1) << ISO11898_BAUD_RATE_PRESCALER_POS) -#define ISO11898_BAUD_RATE_PRESCALER_UMSK (~(((1U << ISO11898_BAUD_RATE_PRESCALER_LEN) - 1) << ISO11898_BAUD_RATE_PRESCALER_POS)) -#define ISO11898_SYNC_JUMP_WIDTH ISO11898_SYNC_JUMP_WIDTH -#define ISO11898_SYNC_JUMP_WIDTH_POS (6U) -#define ISO11898_SYNC_JUMP_WIDTH_LEN (2U) -#define ISO11898_SYNC_JUMP_WIDTH_MSK (((1U << ISO11898_SYNC_JUMP_WIDTH_LEN) - 1) << ISO11898_SYNC_JUMP_WIDTH_POS) -#define ISO11898_SYNC_JUMP_WIDTH_UMSK (~(((1U << ISO11898_SYNC_JUMP_WIDTH_LEN) - 1) << ISO11898_SYNC_JUMP_WIDTH_POS)) - -/* 0x1c : op mode:r reset mode:rw */ -#define ISO11898_BUS_TIMING_1_OFFSET (0x1c) -#define ISO11898_TIME_SEGMENT_1 ISO11898_TIME_SEGMENT_1 -#define ISO11898_TIME_SEGMENT_1_POS (0U) -#define ISO11898_TIME_SEGMENT_1_LEN (4U) -#define ISO11898_TIME_SEGMENT_1_MSK (((1U << ISO11898_TIME_SEGMENT_1_LEN) - 1) << ISO11898_TIME_SEGMENT_1_POS) -#define ISO11898_TIME_SEGMENT_1_UMSK (~(((1U << ISO11898_TIME_SEGMENT_1_LEN) - 1) << ISO11898_TIME_SEGMENT_1_POS)) -#define ISO11898_TIME_SEGMENT_2 ISO11898_TIME_SEGMENT_2 -#define ISO11898_TIME_SEGMENT_2_POS (4U) -#define ISO11898_TIME_SEGMENT_2_LEN (3U) -#define ISO11898_TIME_SEGMENT_2_MSK (((1U << ISO11898_TIME_SEGMENT_2_LEN) - 1) << ISO11898_TIME_SEGMENT_2_POS) -#define ISO11898_TIME_SEGMENT_2_UMSK (~(((1U << ISO11898_TIME_SEGMENT_2_LEN) - 1) << ISO11898_TIME_SEGMENT_2_POS)) -#define ISO11898_SAMPLING ISO11898_SAMPLING -#define ISO11898_SAMPLING_POS (7U) -#define ISO11898_SAMPLING_LEN (1U) -#define ISO11898_SAMPLING_MSK (((1U << ISO11898_SAMPLING_LEN) - 1) << ISO11898_SAMPLING_POS) -#define ISO11898_SAMPLING_UMSK (~(((1U << ISO11898_SAMPLING_LEN) - 1) << ISO11898_SAMPLING_POS)) - -/* 0x2c : op mode:r reset mode:r */ -#define ISO11898_ARB_LOST_CAPTURE_OFFSET (0x2c) -#define ISO11898_ALC4_0 ISO11898_ALC4_0 -#define ISO11898_ALC4_0_POS (0U) -#define ISO11898_ALC4_0_LEN (5U) -#define ISO11898_ALC4_0_MSK (((1U << ISO11898_ALC4_0_LEN) - 1) << ISO11898_ALC4_0_POS) -#define ISO11898_ALC4_0_UMSK (~(((1U << ISO11898_ALC4_0_LEN) - 1) << ISO11898_ALC4_0_POS)) - -/* 0x30 : op mode:r reset mode:r */ -#define ISO11898_ERROR_CODE_CAPTURE_OFFSET (0x30) -#define ISO11898_SEGMENT4_0 ISO11898_SEGMENT4_0 -#define ISO11898_SEGMENT4_0_POS (0U) -#define ISO11898_SEGMENT4_0_LEN (5U) -#define ISO11898_SEGMENT4_0_MSK (((1U << ISO11898_SEGMENT4_0_LEN) - 1) << ISO11898_SEGMENT4_0_POS) -#define ISO11898_SEGMENT4_0_UMSK (~(((1U << ISO11898_SEGMENT4_0_LEN) - 1) << ISO11898_SEGMENT4_0_POS)) -#define ISO11898_DIR ISO11898_DIR -#define ISO11898_DIR_POS (5U) -#define ISO11898_DIR_LEN (1U) -#define ISO11898_DIR_MSK (((1U << ISO11898_DIR_LEN) - 1) << ISO11898_DIR_POS) -#define ISO11898_DIR_UMSK (~(((1U << ISO11898_DIR_LEN) - 1) << ISO11898_DIR_POS)) -#define ISO11898_ERR_CODE ISO11898_ERR_CODE -#define ISO11898_ERR_CODE_POS (6U) -#define ISO11898_ERR_CODE_LEN (2U) -#define ISO11898_ERR_CODE_MSK (((1U << ISO11898_ERR_CODE_LEN) - 1) << ISO11898_ERR_CODE_POS) -#define ISO11898_ERR_CODE_UMSK (~(((1U << ISO11898_ERR_CODE_LEN) - 1) << ISO11898_ERR_CODE_POS)) - -/* 0x34 : op mode:r reset mode:rw */ -#define ISO11898_ERROR_WARNING_LIMIT_OFFSET (0x34) -#define ISO11898_ERR_WARNING_LIMIT ISO11898_ERR_WARNING_LIMIT -#define ISO11898_ERR_WARNING_LIMIT_POS (0U) -#define ISO11898_ERR_WARNING_LIMIT_LEN (8U) -#define ISO11898_ERR_WARNING_LIMIT_MSK (((1U << ISO11898_ERR_WARNING_LIMIT_LEN) - 1) << ISO11898_ERR_WARNING_LIMIT_POS) -#define ISO11898_ERR_WARNING_LIMIT_UMSK (~(((1U << ISO11898_ERR_WARNING_LIMIT_LEN) - 1) << ISO11898_ERR_WARNING_LIMIT_POS)) - -/* 0x38 : op mode:r reset mode:rw */ -#define ISO11898_RX_ERR_COUNT_OFFSET (0x38) -#define ISO11898_RX_ERR_CNT ISO11898_RX_ERR_CNT -#define ISO11898_RX_ERR_CNT_POS (0U) -#define ISO11898_RX_ERR_CNT_LEN (8U) -#define ISO11898_RX_ERR_CNT_MSK (((1U << ISO11898_RX_ERR_CNT_LEN) - 1) << ISO11898_RX_ERR_CNT_POS) -#define ISO11898_RX_ERR_CNT_UMSK (~(((1U << ISO11898_RX_ERR_CNT_LEN) - 1) << ISO11898_RX_ERR_CNT_POS)) - -/* 0x3c : op mode:r reset mode:rw */ -#define ISO11898_TX_ERR_COUNT_OFFSET (0x3c) -#define ISO11898_TX_ERR_CNT ISO11898_TX_ERR_CNT -#define ISO11898_TX_ERR_CNT_POS (0U) -#define ISO11898_TX_ERR_CNT_LEN (8U) -#define ISO11898_TX_ERR_CNT_MSK (((1U << ISO11898_TX_ERR_CNT_LEN) - 1) << ISO11898_TX_ERR_CNT_POS) -#define ISO11898_TX_ERR_CNT_UMSK (~(((1U << ISO11898_TX_ERR_CNT_LEN) - 1) << ISO11898_TX_ERR_CNT_POS)) - -/* 0x40 : op mode: w -> tx_frm_info - r -> rx_frm_info -reset mode:rw -> acceptance_code0 */ -#define ISO11898_TXRX_FRM_INFO_OR_ACCEPTANCE_CODE0_OFFSET (0x40) -#define ISO11898_TXRX_FRM_INFO_OR_ACCEPTANCE_CODE0 ISO11898_TXRX_FRM_INFO_OR_ACCEPTANCE_CODE0 -#define ISO11898_TXRX_FRM_INFO_OR_ACCEPTANCE_CODE0_POS (0U) -#define ISO11898_TXRX_FRM_INFO_OR_ACCEPTANCE_CODE0_LEN (8U) -#define ISO11898_TXRX_FRM_INFO_OR_ACCEPTANCE_CODE0_MSK (((1U << ISO11898_TXRX_FRM_INFO_OR_ACCEPTANCE_CODE0_LEN) - 1) << ISO11898_TXRX_FRM_INFO_OR_ACCEPTANCE_CODE0_POS) -#define ISO11898_TXRX_FRM_INFO_OR_ACCEPTANCE_CODE0_UMSK (~(((1U << ISO11898_TXRX_FRM_INFO_OR_ACCEPTANCE_CODE0_LEN) - 1) << ISO11898_TXRX_FRM_INFO_OR_ACCEPTANCE_CODE0_POS)) - -/* 0x44 : op mode:w -> tx_id1 - r -> rx_id1 -reset mode:rw -> acceptance_code1 */ -#define ISO11898_TXRX_ID1_OR_ACCEPTANCE_CODE1_OFFSET (0x44) -#define ISO11898_TXRX_ID1_OR_ACCEPTANCE_CODE1 ISO11898_TXRX_ID1_OR_ACCEPTANCE_CODE1 -#define ISO11898_TXRX_ID1_OR_ACCEPTANCE_CODE1_POS (0U) -#define ISO11898_TXRX_ID1_OR_ACCEPTANCE_CODE1_LEN (8U) -#define ISO11898_TXRX_ID1_OR_ACCEPTANCE_CODE1_MSK (((1U << ISO11898_TXRX_ID1_OR_ACCEPTANCE_CODE1_LEN) - 1) << ISO11898_TXRX_ID1_OR_ACCEPTANCE_CODE1_POS) -#define ISO11898_TXRX_ID1_OR_ACCEPTANCE_CODE1_UMSK (~(((1U << ISO11898_TXRX_ID1_OR_ACCEPTANCE_CODE1_LEN) - 1) << ISO11898_TXRX_ID1_OR_ACCEPTANCE_CODE1_POS)) - -/* 0x48 : op mode:w -> tx_id2 - r -> rx_id2 - reset mode:rw -> acceptance_code2 */ -#define ISO11898_TXRX_ID2_OR_ACCEPTANCE_CODE2_OFFSET (0x48) -#define ISO11898_TXRX_ID2_OR_ACCEPTANCE_CODE2 ISO11898_TXRX_ID2_OR_ACCEPTANCE_CODE2 -#define ISO11898_TXRX_ID2_OR_ACCEPTANCE_CODE2_POS (0U) -#define ISO11898_TXRX_ID2_OR_ACCEPTANCE_CODE2_LEN (8U) -#define ISO11898_TXRX_ID2_OR_ACCEPTANCE_CODE2_MSK (((1U << ISO11898_TXRX_ID2_OR_ACCEPTANCE_CODE2_LEN) - 1) << ISO11898_TXRX_ID2_OR_ACCEPTANCE_CODE2_POS) -#define ISO11898_TXRX_ID2_OR_ACCEPTANCE_CODE2_UMSK (~(((1U << ISO11898_TXRX_ID2_OR_ACCEPTANCE_CODE2_LEN) - 1) << ISO11898_TXRX_ID2_OR_ACCEPTANCE_CODE2_POS)) - -/* 0x74 : op mode:r reset mode:r */ -#define ISO11898_RX_MESSAGE_COUNT_OFFSET (0x74) -#define ISO11898_RX_MESSAGE_CNT ISO11898_RX_MESSAGE_CNT -#define ISO11898_RX_MESSAGE_CNT_POS (0U) -#define ISO11898_RX_MESSAGE_CNT_LEN (5U) -#define ISO11898_RX_MESSAGE_CNT_MSK (((1U << ISO11898_RX_MESSAGE_CNT_LEN) - 1) << ISO11898_RX_MESSAGE_CNT_POS) -#define ISO11898_RX_MESSAGE_CNT_UMSK (~(((1U << ISO11898_RX_MESSAGE_CNT_LEN) - 1) << ISO11898_RX_MESSAGE_CNT_POS)) - -/* 0x7c : op mode:rw reset mode:rw iso11898_mode and cbp can be write in reset mode only */ -#define ISO11898_CLOCK_DIVIDER_OFFSET (0x7c) -#define ISO11898_CD ISO11898_CD -#define ISO11898_CD_POS (0U) -#define ISO11898_CD_LEN (3U) -#define ISO11898_CD_MSK (((1U << ISO11898_CD_LEN) - 1) << ISO11898_CD_POS) -#define ISO11898_CD_UMSK (~(((1U << ISO11898_CD_LEN) - 1) << ISO11898_CD_POS)) -#define ISO11898_CLOCKOFF ISO11898_CLOCKOFF -#define ISO11898_CLOCKOFF_POS (3U) -#define ISO11898_CLOCKOFF_LEN (1U) -#define ISO11898_CLOCKOFF_MSK (((1U << ISO11898_CLOCKOFF_LEN) - 1) << ISO11898_CLOCKOFF_POS) -#define ISO11898_CLOCKOFF_UMSK (~(((1U << ISO11898_CLOCKOFF_LEN) - 1) << ISO11898_CLOCKOFF_POS)) -#define ISO11898_READONLY ISO11898_READONLY -#define ISO11898_READONLY_POS (4U) -#define ISO11898_READONLY_LEN (1U) -#define ISO11898_READONLY_MSK (((1U << ISO11898_READONLY_LEN) - 1) << ISO11898_READONLY_POS) -#define ISO11898_READONLY_UMSK (~(((1U << ISO11898_READONLY_LEN) - 1) << ISO11898_READONLY_POS)) -#define ISO11898_RXINTEN ISO11898_RXINTEN -#define ISO11898_RXINTEN_POS (5U) -#define ISO11898_RXINTEN_LEN (1U) -#define ISO11898_RXINTEN_MSK (((1U << ISO11898_RXINTEN_LEN) - 1) << ISO11898_RXINTEN_POS) -#define ISO11898_RXINTEN_UMSK (~(((1U << ISO11898_RXINTEN_LEN) - 1) << ISO11898_RXINTEN_POS)) -#define ISO11898_CBP ISO11898_CBP -#define ISO11898_CBP_POS (6U) -#define ISO11898_CBP_LEN (1U) -#define ISO11898_CBP_MSK (((1U << ISO11898_CBP_LEN) - 1) << ISO11898_CBP_POS) -#define ISO11898_CBP_UMSK (~(((1U << ISO11898_CBP_LEN) - 1) << ISO11898_CBP_POS)) -#define ISO11898_MODE ISO11898_MODE -#define ISO11898_MODE_POS (7U) -#define ISO11898_MODE_LEN (1U) -#define ISO11898_MODE_MSK (((1U << ISO11898_MODE_LEN) - 1) << ISO11898_MODE_POS) -#define ISO11898_MODE_UMSK (~(((1U << ISO11898_MODE_LEN) - 1) << ISO11898_MODE_POS)) - -/* 0x40 : Frame information */ -#define ISO11898_INFORMATION_OFFSET (0x40) -#define ISO11898_INF_DLC ISO11898_INF_DLC -#define ISO11898_INF_DLC_POS (0U) -#define ISO11898_INF_DLC_LEN (4U) -#define ISO11898_INF_DLC_MSK (((1U << ISO11898_INF_DLC_LEN) - 1) << ISO11898_INF_DLC_POS) -#define ISO11898_INF_DLC_UMSK (~(((1U << ISO11898_INF_DLC_LEN) - 1) << ISO11898_INF_DLC_POS)) -#define ISO11898_INF_RTR ISO11898_INF_RTR -#define ISO11898_INF_RTR_POS (6U) -#define ISO11898_INF_RTR_LEN (1U) -#define ISO11898_INF_RTR_MSK (((1U << ISO11898_INF_RTR_LEN) - 1) << ISO11898_INF_RTR_POS) -#define ISO11898_INF_RTR_UMSK (~(((1U << ISO11898_INF_RTR_LEN) - 1) << ISO11898_INF_RTR_POS)) -#define ISO11898_INF_FF ISO11898_INF_FF -#define ISO11898_INF_FF_POS (7U) -#define ISO11898_INF_FF_LEN (1U) -#define ISO11898_INF_FF_MSK (((1U << ISO11898_INF_FF_LEN) - 1) << ISO11898_INF_FF_POS) -#define ISO11898_INF_FF_UMSK (~(((1U << ISO11898_INF_FF_LEN) - 1) << ISO11898_INF_FF_POS)) - -/* 0x44 : Identifier 1, ID28~21 */ -#define ISO11898_IDENTIFIER_1_OFFSET (0x44) - -/* 0x48 : Identifier 2, ID20~13, SFF Only use ID20~18 */ -#define ISO11898_IDENTIFIER_2_OFFSET (0x48) - -/* 0x4C : Identifier 3, ID12~5, only for EFF */ -#define ISO11898_IDENTIFIER_3_OFFSET (0x4C) - -/* 0x50 : Identifier 4, ID4~0, only for EFF */ -#define ISO11898_IDENTIFIER_4_OFFSET (0x50) - -/* 0x4C : Standard Format Data 1 buffer */ -#define ISO11898_SFF_DATA_1_OFFSET (0x4C) - -/* 0x50 : Standard Format Data 2 buffer */ -#define ISO11898_SFF_DATA_2_OFFSET (0x50) - -/* 0x54 : Standard Format Data 3 buffer */ -#define ISO11898_SFF_DATA_3_OFFSET (0x54) - -/* 0x58 : Standard Format Data 4 buffer */ -#define ISO11898_SFF_DATA_4_OFFSET (0x58) - -/* 0x5C : Standard Format Data 5 buffer */ -#define ISO11898_SFF_DATA_5_OFFSET (0x5C) - -/* 0x60 : Standard Format Data 6 buffer */ -#define ISO11898_SFF_DATA_6_OFFSET (0x60) - -/* 0x64 : Standard Format Data 7 buffer */ -#define ISO11898_SFF_DATA_7_OFFSET (0x64) - -/* 0x68 : Standard Format Data 8 buffer */ -#define ISO11898_SFF_DATA_8_OFFSET (0x68) - -/* 0x54 : Extended Format Data 1 buffer */ -#define ISO11898_EFF_DATA_1_OFFSET (0x54) - -/* 0x58 : Extended Format Data 2 buffer */ -#define ISO11898_EFF_DATA_2_OFFSET (0x58) - -/* 0x5C : Extended Format Data 3 buffer */ -#define ISO11898_EFF_DATA_3_OFFSET (0x5C) - -/* 0x60 : Extended Format Data 4 buffer */ -#define ISO11898_EFF_DATA_4_OFFSET (0x60) - -/* 0x64 : Extended Format Data 5 buffer */ -#define ISO11898_EFF_DATA_5_OFFSET (0x64) - -/* 0x68 : Extended Format Data 6 buffer */ -#define ISO11898_EFF_DATA_6_OFFSET (0x68) - -/* 0x6C : Extended Format Data 7 buffer */ -#define ISO11898_EFF_DATA_7_OFFSET (0x6C) - -/* 0x70 : Extended Format Data 8 buffer */ -#define ISO11898_EFF_DATA_8_OFFSET (0x70) - -/* 0x70 : Extended Format Data 8 buffer */ -#define ISO11898_EFF_DATA_8_OFFSET (0x70) - -/* 0x40 : Filter Acceptance 0 */ -#define ISO11898_FILTER_ACCEPTANCE_0_OFFSET (0x40) - -/* 0x44 : Filter Acceptance 1 */ -#define ISO11898_FILTER_ACCEPTANCE_1_OFFSET (0x44) - -/* 0x48 : Filter Acceptance 2 */ -#define ISO11898_FILTER_ACCEPTANCE_2_OFFSET (0x48) - -/* 0x4C : Filter Acceptance 3 */ -#define ISO11898_FILTER_ACCEPTANCE_3_OFFSET (0x4C) - -/* 0x50 : Filter Mask 0 */ -#define ISO11898_FILTER_Mask_0_OFFSET (0x50) - -/* 0x54 : Filter Mask 1 */ -#define ISO11898_FILTER_Mask_1_OFFSET (0x54) - -/* 0x58 : Filter Mask 2 */ -#define ISO11898_FILTER_Mask_2_OFFSET (0x58) - -/* 0x5C : Filter Mask 3 */ -#define ISO11898_FILTER_Mask_3_OFFSET (0x5C) - -/* 0x4C : Extended Format, Tx information 5, ID4~0 */ -#define ISO11898_IDENTIFIER_4_OFFSET (0x50) - -struct iso11898_reg { - /* 0x0 : op mode:rw reset mode:rw */ - union { - struct { - uint32_t reset_request : 1; /* [ 0], w1c, 0x0 */ - uint32_t listen_only : 1; /* [ 1], w1c, 0x0 */ - uint32_t selt_test : 1; /* [ 2], w1c, 0x0 */ - uint32_t acceptance_filter : 1; /* [ 3], w1c, 0x0 */ - uint32_t rsvd_7_4 : 4; /* [ 7: 4], rsvd, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mode; - - /* 0x4 : op mode:w r -> 8'h00 -reset mode:w r -> 8'h00 */ - union { - struct { - uint32_t transmit_request : 1; /* [ 0], w1c, 0x0 */ - uint32_t abort_transmission : 1; /* [ 1], w1c, 0x0 */ - uint32_t release_receive_buffer : 1; /* [ 2], w1c, 0x0 */ - uint32_t clear_data_overrun : 1; /* [ 3], w1c, 0x0 */ - uint32_t self_request : 1; /* [ 4], w1c, 0x0 */ - uint32_t rsvd_7_5 : 3; /* [ 7: 5], rsvd, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } command; - - /* 0x8 : op mode:r reset mode:r */ - union { - struct { - uint32_t receive_buffer_sts : 1; /* [ 0], r, 0x0 */ - uint32_t data_overrun_sts : 1; /* [ 1], r, 0x0 */ - uint32_t transmit_buffer_sts : 1; /* [ 2], r, 0x0 */ - uint32_t transmit_complete_sts : 1; /* [ 3], r, 0x0 */ - uint32_t receive_sts : 1; /* [ 4], r, 0x0 */ - uint32_t transmit_sts : 1; /* [ 5], r, 0x0 */ - uint32_t error_sts : 1; /* [ 6], r, 0x0 */ - uint32_t bus_sts : 1; /* [ 7], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } status; - - /* 0xc : op mode:r reset mode:r when be read,all bits are reseted and iso11898_int disappear */ - union { - struct { - uint32_t receive_int : 1; /* [ 0], r, 0x0 */ - uint32_t transmit_int : 1; /* [ 1], r, 0x0 */ - uint32_t error_int : 1; /* [ 2], r, 0x0 */ - uint32_t data_overrun_int : 1; /* [ 3], r, 0x0 */ - uint32_t rsvd_4 : 1; /* [ 4], rsvd, 0x0 */ - uint32_t error_passive_int : 1; /* [ 5], r, 0x0 */ - uint32_t arb_lost_int : 1; /* [ 6], r, 0x0 */ - uint32_t bus_error_int : 1; /* [ 7], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } interrupt; - - /* 0x10 : op mode:rw reset mode:rw when be read,all bits are reseted and iso11898_int disappear */ - union { - struct { - uint32_t receive_int_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t transmit_int_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t error_int_en : 1; /* [ 2], r/w, 0x0 */ - uint32_t data_overrun_int_en : 1; /* [ 3], r/w, 0x0 */ - uint32_t rsvd_4 : 1; /* [ 4], rsvd, 0x0 */ - uint32_t error_passive_int_en : 1; /* [ 5], r/w, 0x0 */ - uint32_t arb_lost_int_en : 1; /* [ 6], r/w, 0x0 */ - uint32_t bus_error_int_en : 1; /* [ 7], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } interrupt_enable; - - /* 0x14 reserved */ - uint8_t RESERVED0x14[4]; - - /* 0x18 : op mode:r reset mode:rw */ - union { - struct { - uint32_t baud_rate_prescaler_0 : 1; /* [ 0], r/w, 0x0 */ - uint32_t baud_rate_prescaler_1 : 1; /* [ 1], r/w, 0x0 */ - uint32_t baud_rate_prescaler_2 : 1; /* [ 2], r/w, 0x0 */ - uint32_t baud_rate_prescaler_3 : 1; /* [ 3], r/w, 0x0 */ - uint32_t baud_rate_prescaler_4 : 1; /* [ 4], r/w, 0x0 */ - uint32_t baud_rate_prescaler_5 : 1; /* [ 5], r/w, 0x0 */ - uint32_t sync_jump_width_0 : 1; /* [ 6], r/w, 0x0 */ - uint32_t sync_jump_width_1 : 1; /* [ 7], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } bus_timing_0; - - /* 0x1c : op mode:r reset mode:rw */ - union { - struct { - uint32_t time_segment_1_0 : 1; /* [ 0], r/w, 0x0 */ - uint32_t time_segment_1_1 : 1; /* [ 1], r/w, 0x0 */ - uint32_t time_segment_1_2 : 1; /* [ 2], r/w, 0x0 */ - uint32_t time_segment_1_3 : 1; /* [ 3], r/w, 0x0 */ - uint32_t time_segment_2_0 : 1; /* [ 4], r/w, 0x0 */ - uint32_t time_segment_2_1 : 1; /* [ 5], r/w, 0x0 */ - uint32_t time_segment_2_2 : 1; /* [ 6], r/w, 0x0 */ - uint32_t sampling : 1; /* [ 7], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } bus_timing_1; - - /* 0x20 reserved */ - uint8_t RESERVED0x20[12]; - - /* 0x2c : op mode:r reset mode:r */ - union { - struct { - uint32_t ALC4_0 : 5; /* [ 4: 0], r, 0x0 */ - uint32_t rsvd_7_5 : 3; /* [ 7: 5], rsvd, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } arb_lost_capture; - - /* 0x30 : op mode:r reset mode:r */ - union { - struct { - uint32_t segment4_0 : 5; /* [ 4: 0], r, 0x0 */ - uint32_t dir : 1; /* [ 5], r, 0x0 */ - uint32_t err_code : 2; /* [ 7: 6], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } error_code_capture; - - /* 0x34 : op mode:r reset mode:rw */ - union { - struct { - uint32_t err_warning_limit : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } error_warning_limit; - - /* 0x38 : op mode:r reset mode:rw */ - union { - struct { - uint32_t rx_err_cnt : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } rx_err_count; - - /* 0x3c : op mode:r reset mode:rw */ - union { - struct { - uint32_t tx_err_cnt : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } tx_err_count; - - /* 0x40 : op mode: w -> tx_frm_info - r -> rx_frm_info -reset mode:rw -> acceptance_code0 */ - union { - struct { - uint32_t txrx_frm_info_or_acceptance_code0 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_frm_info_or_acceptance_code0; - - /* 0x44 : op mode:w -> tx_id1 - r -> rx_id1 -reset mode:rw -> acceptance_code1 */ - union { - struct { - uint32_t txrx_id1_or_acceptance_code1 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_id1_or_acceptance_code1; - - /* 0x48 : op mode:w -> tx_id2 - r -> rx_id2 - reset mode:rw -> acceptance_code2 */ - union { - struct { - uint32_t txrx_id2_or_acceptance_code2 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_id2_or_acceptance_code2; - - /* 0x4c : op mode:w -> tx_data1_s or tx_id3 - r -> rx_data1_s or rx_id3 - reset mode:rw -> acceptance_code3 */ - union { - struct { - uint32_t txrx_data1_s_or_txrx_id3_e_or_acceptance_code3 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_data1_s_or_txrx_id3_e_or_acceptance_code3; - - /* 0x50 : op mode:w -> tx_data2_s or tx_id4 - r -> rx_data2_s or rx_id4 -reset mode:rw -> acceptance_mask0 */ - union { - struct { - uint32_t txrx_data2_s_or_txrx_id4_e_or_acceptance_mask0 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_data2_s_or_txrx_id4_e_or_acceptance_mask0; - - /* 0x54 : op mode:w -> tx_data3_s or tx_data1_e - r -> rx_data3_s or rx_data1_e -reset mode:rw -> acceptance_mask1 */ - union { - struct { - uint32_t txrx_data3_s_or_txrx_data1_e_or_acceptance_mask1 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_data3_s_or_txrx_data1_e_or_acceptance_mask1; - - /* 0x58 : op mode:w -> tx_data4_s or tx_data2_e - r -> rx_data4_s or rx_data2_e -reset mode:rw -> acceptance_mask2 */ - union { - struct { - uint32_t txrx_data4_s_or_txrx_data2_e_or_acceptance_mask2 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_data4_s_or_txrx_data2_e_or_acceptance_mask2; - - /* 0x5c : op mode:w -> tx_data5_s or tx_data3_e - r -> rx_data5_s or rx_data3_e -reset mode:rw -> acceptance_mask3 */ - union { - struct { - uint32_t txrx_data5_s_or_txrx_data3_e_or_acceptance_mask3 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_data5_s_or_txrx_data3_e_or_acceptance_mask3; - - /* 0x60 : op mode:w -> tx_data6_s or tx_data4_e - r -> rx_data6_s or rx_data4_e -reset mode:r -> 8'H00 */ - union { - struct { - uint32_t txrx_data6_s_or_txrx_data4_e : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_data6_s_or_txrx_data4_e; - - /* 0x64 : op mode:w -> tx_data7_s or tx_data5_e - r -> rx_data7_s or rx_data5_e -reset mode:r -> 8'H00 */ - union { - struct { - uint32_t txrx_data7_s_or_txrx_data5_e : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_data7_s_or_txrx_data5_e; - - /* 0x68 : op mode:w -> tx_data8_s or tx_data6_e - r -> rx_data8_s or rx_data6_e -reset mode:r -> 8'H00 */ - union { - struct { - uint32_t txrx_data8_s_or_txrx_data6_e : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_data8_s_or_txrx_data6_e; - - /* 0x6c : op mode:w -> tx_data7_e - r -> rx_data7_e -reset mode:r -> 8'H00 */ - union { - struct { - uint32_t txrx_data7_e : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_data7_e; - - /* 0x70 : op mode:w -> tx_data8_e - r -> rx_data8_e -reset mode:r -> 8'H00 */ - union { - struct { - uint32_t txrx_data8_e : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_data8_e; - - /* 0x74 : op mode:r reset mode:r */ - union { - struct { - uint32_t rx_message_cnt : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } rx_message_count; - - /* 0x78 reserved */ - uint8_t RESERVED0x78[4]; - - /* 0x7c : op mode:rw reset mode:rw iso11898_mode and cbp can be write in reset mode only */ - union { - struct { - uint32_t cd : 3; /* [ 2: 0], r/w, 0x0 */ - uint32_t clockoff : 1; /* [ 3], r/w, 0x0 */ - uint32_t readonly : 1; /* [ 4], r, 0x0 */ - uint32_t rxinten : 1; /* [ 5], r/w, 0x0 */ - uint32_t cbp : 1; /* [ 6], r/w, 0x0 */ - uint32_t iso11898_mode : 1; /* [ 7], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } clock_divider; -}; - -typedef volatile struct iso11898_reg iso11898_reg_t; - -#endif /* __ISO11898_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/lz4_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/lz4_reg.h deleted file mode 100644 index 9d21f7a184..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/lz4_reg.h +++ /dev/null @@ -1,276 +0,0 @@ -/** - ****************************************************************************** - * @file lz4_reg.h - * @version V1.0 - * @date 2021-06-15 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __LZ4_REG_H__ -#define __LZ4_REG_H__ - -#include "bl808.h" - -/* 0x0 : lz4_config */ -#define LZ4_CONFIG_OFFSET (0x0) -#define LZ4_EN LZ4_EN -#define LZ4_EN_POS (0U) -#define LZ4_EN_LEN (1U) -#define LZ4_EN_MSK (((1U << LZ4_EN_LEN) - 1) << LZ4_EN_POS) -#define LZ4_EN_UMSK (~(((1U << LZ4_EN_LEN) - 1) << LZ4_EN_POS)) -#define LZ4_SUSPEND LZ4_SUSPEND -#define LZ4_SUSPEND_POS (1U) -#define LZ4_SUSPEND_LEN (1U) -#define LZ4_SUSPEND_MSK (((1U << LZ4_SUSPEND_LEN) - 1) << LZ4_SUSPEND_POS) -#define LZ4_SUSPEND_UMSK (~(((1U << LZ4_SUSPEND_LEN) - 1) << LZ4_SUSPEND_POS)) -#define LZ4_CHECKSUM LZ4_CHECKSUM -#define LZ4_CHECKSUM_POS (4U) -#define LZ4_CHECKSUM_LEN (1U) -#define LZ4_CHECKSUM_MSK (((1U << LZ4_CHECKSUM_LEN) - 1) << LZ4_CHECKSUM_POS) -#define LZ4_CHECKSUM_UMSK (~(((1U << LZ4_CHECKSUM_LEN) - 1) << LZ4_CHECKSUM_POS)) - -/* 0x4 : lz4_src_fix */ -#define LZ4_SRC_FIX_OFFSET (0x4) -#define LZ4_SRC_FIX LZ4_SRC_FIX -#define LZ4_SRC_FIX_POS (12U) -#define LZ4_SRC_FIX_LEN (14U) -#define LZ4_SRC_FIX_MSK (((1U << LZ4_SRC_FIX_LEN) - 1) << LZ4_SRC_FIX_POS) -#define LZ4_SRC_FIX_UMSK (~(((1U << LZ4_SRC_FIX_LEN) - 1) << LZ4_SRC_FIX_POS)) - -/* 0x8 : lz4_dst_fix */ -#define LZ4_DST_FIX_OFFSET (0x8) -#define LZ4_DST_FIX LZ4_DST_FIX -#define LZ4_DST_FIX_POS (12U) -#define LZ4_DST_FIX_LEN (14U) -#define LZ4_DST_FIX_MSK (((1U << LZ4_DST_FIX_LEN) - 1) << LZ4_DST_FIX_POS) -#define LZ4_DST_FIX_UMSK (~(((1U << LZ4_DST_FIX_LEN) - 1) << LZ4_DST_FIX_POS)) - -/* 0x10 : lz4_src_start */ -#define LZ4_SRC_START_OFFSET (0x10) -#define LZ4_SRC_START LZ4_SRC_START -#define LZ4_SRC_START_POS (0U) -#define LZ4_SRC_START_LEN (26U) -#define LZ4_SRC_START_MSK (((1U << LZ4_SRC_START_LEN) - 1) << LZ4_SRC_START_POS) -#define LZ4_SRC_START_UMSK (~(((1U << LZ4_SRC_START_LEN) - 1) << LZ4_SRC_START_POS)) -#define LZ4_SRC_BASE LZ4_SRC_BASE -#define LZ4_SRC_BASE_POS (26U) -#define LZ4_SRC_BASE_LEN (6U) -#define LZ4_SRC_BASE_MSK (((1U << LZ4_SRC_BASE_LEN) - 1) << LZ4_SRC_BASE_POS) -#define LZ4_SRC_BASE_UMSK (~(((1U << LZ4_SRC_BASE_LEN) - 1) << LZ4_SRC_BASE_POS)) - -/* 0x14 : lz4_src_end */ -#define LZ4_SRC_END_OFFSET (0x14) -#define LZ4_SRC_END LZ4_SRC_END -#define LZ4_SRC_END_POS (0U) -#define LZ4_SRC_END_LEN (26U) -#define LZ4_SRC_END_MSK (((1U << LZ4_SRC_END_LEN) - 1) << LZ4_SRC_END_POS) -#define LZ4_SRC_END_UMSK (~(((1U << LZ4_SRC_END_LEN) - 1) << LZ4_SRC_END_POS)) - -/* 0x18 : lz4_dst_start */ -#define LZ4_DST_START_OFFSET (0x18) -#define LZ4_DST_START LZ4_DST_START -#define LZ4_DST_START_POS (0U) -#define LZ4_DST_START_LEN (26U) -#define LZ4_DST_START_MSK (((1U << LZ4_DST_START_LEN) - 1) << LZ4_DST_START_POS) -#define LZ4_DST_START_UMSK (~(((1U << LZ4_DST_START_LEN) - 1) << LZ4_DST_START_POS)) -#define LZ4_DST_BASE LZ4_DST_BASE -#define LZ4_DST_BASE_POS (26U) -#define LZ4_DST_BASE_LEN (6U) -#define LZ4_DST_BASE_MSK (((1U << LZ4_DST_BASE_LEN) - 1) << LZ4_DST_BASE_POS) -#define LZ4_DST_BASE_UMSK (~(((1U << LZ4_DST_BASE_LEN) - 1) << LZ4_DST_BASE_POS)) - -/* 0x1C : lz4_dst_end */ -#define LZ4_DST_END_OFFSET (0x1C) -#define LZ4_DST_END LZ4_DST_END -#define LZ4_DST_END_POS (0U) -#define LZ4_DST_END_LEN (26U) -#define LZ4_DST_END_MSK (((1U << LZ4_DST_END_LEN) - 1) << LZ4_DST_END_POS) -#define LZ4_DST_END_UMSK (~(((1U << LZ4_DST_END_LEN) - 1) << LZ4_DST_END_POS)) - -/* 0x20 : lz4_int_en */ -#define LZ4_INT_EN_OFFSET (0x20) -#define LZ4_DONE_EN LZ4_DONE_EN -#define LZ4_DONE_EN_POS (0U) -#define LZ4_DONE_EN_LEN (1U) -#define LZ4_DONE_EN_MSK (((1U << LZ4_DONE_EN_LEN) - 1) << LZ4_DONE_EN_POS) -#define LZ4_DONE_EN_UMSK (~(((1U << LZ4_DONE_EN_LEN) - 1) << LZ4_DONE_EN_POS)) -#define LZ4_ERR_EN LZ4_ERR_EN -#define LZ4_ERR_EN_POS (1U) -#define LZ4_ERR_EN_LEN (1U) -#define LZ4_ERR_EN_MSK (((1U << LZ4_ERR_EN_LEN) - 1) << LZ4_ERR_EN_POS) -#define LZ4_ERR_EN_UMSK (~(((1U << LZ4_ERR_EN_LEN) - 1) << LZ4_ERR_EN_POS)) -#define LZ4_DST_INT_EN LZ4_DST_INT_EN -#define LZ4_DST_INT_EN_POS (10U) -#define LZ4_DST_INT_EN_LEN (6U) -#define LZ4_DST_INT_EN_MSK (((1U << LZ4_DST_INT_EN_LEN) - 1) << LZ4_DST_INT_EN_POS) -#define LZ4_DST_INT_EN_UMSK (~(((1U << LZ4_DST_INT_EN_LEN) - 1) << LZ4_DST_INT_EN_POS)) -#define LZ4_DST_INT_INV LZ4_DST_INT_INV -#define LZ4_DST_INT_INV_POS (26U) -#define LZ4_DST_INT_INV_LEN (6U) -#define LZ4_DST_INT_INV_MSK (((1U << LZ4_DST_INT_INV_LEN) - 1) << LZ4_DST_INT_INV_POS) -#define LZ4_DST_INT_INV_UMSK (~(((1U << LZ4_DST_INT_INV_LEN) - 1) << LZ4_DST_INT_INV_POS)) - -/* 0x24 : lz4_int_sta */ -#define LZ4_INT_STA_OFFSET (0x24) -#define LZ4_DONE_STA LZ4_DONE_STA -#define LZ4_DONE_STA_POS (0U) -#define LZ4_DONE_STA_LEN (1U) -#define LZ4_DONE_STA_MSK (((1U << LZ4_DONE_STA_LEN) - 1) << LZ4_DONE_STA_POS) -#define LZ4_DONE_STA_UMSK (~(((1U << LZ4_DONE_STA_LEN) - 1) << LZ4_DONE_STA_POS)) -#define LZ4_ERR_STA LZ4_ERR_STA -#define LZ4_ERR_STA_POS (1U) -#define LZ4_ERR_STA_LEN (1U) -#define LZ4_ERR_STA_MSK (((1U << LZ4_ERR_STA_LEN) - 1) << LZ4_ERR_STA_POS) -#define LZ4_ERR_STA_UMSK (~(((1U << LZ4_ERR_STA_LEN) - 1) << LZ4_ERR_STA_POS)) -#define LZ4_DST_INT_STA LZ4_DST_INT_STA -#define LZ4_DST_INT_STA_POS (10U) -#define LZ4_DST_INT_STA_LEN (6U) -#define LZ4_DST_INT_STA_MSK (((1U << LZ4_DST_INT_STA_LEN) - 1) << LZ4_DST_INT_STA_POS) -#define LZ4_DST_INT_STA_UMSK (~(((1U << LZ4_DST_INT_STA_LEN) - 1) << LZ4_DST_INT_STA_POS)) - -/* 0x28 : lz4_monitor */ -#define LZ4_MONITOR_OFFSET (0x28) -#define LZ4_CS LZ4_CS -#define LZ4_CS_POS (0U) -#define LZ4_CS_LEN (4U) -#define LZ4_CS_MSK (((1U << LZ4_CS_LEN) - 1) << LZ4_CS_POS) -#define LZ4_CS_UMSK (~(((1U << LZ4_CS_LEN) - 1) << LZ4_CS_POS)) - -struct lz4_reg { - /* 0x0 : lz4_config */ - union { - struct { - uint32_t lz4_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t lz4_suspend : 1; /* [ 1], r/w, 0x0 */ - uint32_t reserved_2_3 : 2; /* [ 3: 2], rsvd, 0x0 */ - uint32_t lz4_checksum : 1; /* [ 4], r/w, 0x0 */ - uint32_t reserved_5_27 : 23; /* [27: 5], rsvd, 0x0 */ - uint32_t rsvd_31_28 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } lz4_config; - - /* 0x4 : lz4_src_fix */ - union { - struct { - uint32_t reserved_0_11 : 12; /* [11: 0], rsvd, 0x0 */ - uint32_t lz4_src_fix : 14; /* [25:12], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } lz4_src_fix; - - /* 0x8 : lz4_dst_fix */ - union { - struct { - uint32_t reserved_0_11 : 12; /* [11: 0], rsvd, 0x0 */ - uint32_t lz4_dst_fix : 14; /* [25:12], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } lz4_dst_fix; - - /* 0xc reserved */ - uint8_t RESERVED0xc[4]; - - /* 0x10 : lz4_src_start */ - union { - struct { - uint32_t lz4_src_start : 26; /* [25: 0], r/w, 0x0 */ - uint32_t lz4_src_base : 6; /* [31:26], r/w, 0x0 */ - } BF; - uint32_t WORD; - } lz4_src_start; - - /* 0x14 : lz4_src_end */ - union { - struct { - uint32_t lz4_src_end : 26; /* [25: 0], r, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } lz4_src_end; - - /* 0x18 : lz4_dst_start */ - union { - struct { - uint32_t lz4_dst_start : 26; /* [25: 0], r/w, 0x0 */ - uint32_t lz4_dst_base : 6; /* [31:26], r/w, 0x0 */ - } BF; - uint32_t WORD; - } lz4_dst_start; - - /* 0x1C : lz4_dst_end */ - union { - struct { - uint32_t lz4_dst_end : 26; /* [25: 0], r, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } lz4_dst_end; - - /* 0x20 : lz4_int_en */ - union { - struct { - uint32_t lz4_done_en : 1; /* [ 0], r/w, 0x1 */ - uint32_t lz4_err_en : 1; /* [ 1], r/w, 0x1 */ - uint32_t reserved_2_9 : 8; /* [ 9: 2], rsvd, 0x0 */ - uint32_t lz4_dst_int_en : 6; /* [15:10], r/w, 0x0 */ - uint32_t reserved_16_25 : 10; /* [25:16], rsvd, 0x0 */ - uint32_t lz4_dst_int_inv : 6; /* [31:26], r/w, 0x0 */ - } BF; - uint32_t WORD; - } lz4_int_en; - - /* 0x24 : lz4_int_sta */ - union { - struct { - uint32_t lz4_done_sta : 1; /* [ 0], r, 0x0 */ - uint32_t lz4_err_sta : 1; /* [ 1], r, 0x0 */ - uint32_t reserved_2_9 : 8; /* [ 9: 2], rsvd, 0x0 */ - uint32_t lz4_dst_int_sta : 6; /* [15:10], r, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } lz4_int_sta; - - /* 0x28 : lz4_monitor */ - union { - struct { - uint32_t lz4_cs : 4; /* [ 3: 0], r, 0x0 */ - uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } lz4_monitor; -}; - -typedef volatile struct lz4_reg lz4_reg_t; - -#endif /* __LZ4_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/mjdec_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/mjdec_reg.h deleted file mode 100644 index c92e3ed9fe..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/mjdec_reg.h +++ /dev/null @@ -1,652 +0,0 @@ -/** - ****************************************************************************** - * @file mjdec_reg.h - * @version V1.0 - * @date 2021-07-02 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __MJDEC_REG_H__ -#define __MJDEC_REG_H__ - -#include "bl808.h" - -/* 0x0 : jdec_control_1 */ -#define MJDEC_JDEC_CONTROL_1_OFFSET (0x0) -#define MJDEC_REG_MJ_DEC_ENABLE MJDEC_REG_MJ_DEC_ENABLE -#define MJDEC_REG_MJ_DEC_ENABLE_POS (0U) -#define MJDEC_REG_MJ_DEC_ENABLE_LEN (1U) -#define MJDEC_REG_MJ_DEC_ENABLE_MSK (((1U << MJDEC_REG_MJ_DEC_ENABLE_LEN) - 1) << MJDEC_REG_MJ_DEC_ENABLE_POS) -#define MJDEC_REG_MJ_DEC_ENABLE_UMSK (~(((1U << MJDEC_REG_MJ_DEC_ENABLE_LEN) - 1) << MJDEC_REG_MJ_DEC_ENABLE_POS)) -#define MJDEC_REG_SWAP_MODE MJDEC_REG_SWAP_MODE -#define MJDEC_REG_SWAP_MODE_POS (1U) -#define MJDEC_REG_SWAP_MODE_LEN (1U) -#define MJDEC_REG_SWAP_MODE_MSK (((1U << MJDEC_REG_SWAP_MODE_LEN) - 1) << MJDEC_REG_SWAP_MODE_POS) -#define MJDEC_REG_SWAP_MODE_UMSK (~(((1U << MJDEC_REG_SWAP_MODE_LEN) - 1) << MJDEC_REG_SWAP_MODE_POS)) -#define MJDEC_REG_U_EVEN MJDEC_REG_U_EVEN -#define MJDEC_REG_U_EVEN_POS (2U) -#define MJDEC_REG_U_EVEN_LEN (1U) -#define MJDEC_REG_U_EVEN_MSK (((1U << MJDEC_REG_U_EVEN_LEN) - 1) << MJDEC_REG_U_EVEN_POS) -#define MJDEC_REG_U_EVEN_UMSK (~(((1U << MJDEC_REG_U_EVEN_LEN) - 1) << MJDEC_REG_U_EVEN_POS)) -#define MJDEC_REG_YUV_MODE MJDEC_REG_YUV_MODE -#define MJDEC_REG_YUV_MODE_POS (3U) -#define MJDEC_REG_YUV_MODE_LEN (2U) -#define MJDEC_REG_YUV_MODE_MSK (((1U << MJDEC_REG_YUV_MODE_LEN) - 1) << MJDEC_REG_YUV_MODE_POS) -#define MJDEC_REG_YUV_MODE_UMSK (~(((1U << MJDEC_REG_YUV_MODE_LEN) - 1) << MJDEC_REG_YUV_MODE_POS)) -#define MJDEC_REG_LAST_HF_WBLK_DMY MJDEC_REG_LAST_HF_WBLK_DMY -#define MJDEC_REG_LAST_HF_WBLK_DMY_POS (5U) -#define MJDEC_REG_LAST_HF_WBLK_DMY_LEN (1U) -#define MJDEC_REG_LAST_HF_WBLK_DMY_MSK (((1U << MJDEC_REG_LAST_HF_WBLK_DMY_LEN) - 1) << MJDEC_REG_LAST_HF_WBLK_DMY_POS) -#define MJDEC_REG_LAST_HF_WBLK_DMY_UMSK (~(((1U << MJDEC_REG_LAST_HF_WBLK_DMY_LEN) - 1) << MJDEC_REG_LAST_HF_WBLK_DMY_POS)) -#define MJDEC_REG_LAST_HF_HBLK_DMY MJDEC_REG_LAST_HF_HBLK_DMY -#define MJDEC_REG_LAST_HF_HBLK_DMY_POS (6U) -#define MJDEC_REG_LAST_HF_HBLK_DMY_LEN (1U) -#define MJDEC_REG_LAST_HF_HBLK_DMY_MSK (((1U << MJDEC_REG_LAST_HF_HBLK_DMY_LEN) - 1) << MJDEC_REG_LAST_HF_HBLK_DMY_POS) -#define MJDEC_REG_LAST_HF_HBLK_DMY_UMSK (~(((1U << MJDEC_REG_LAST_HF_HBLK_DMY_LEN) - 1) << MJDEC_REG_LAST_HF_HBLK_DMY_POS)) -#define MJDEC_REG_W_XLEN MJDEC_REG_W_XLEN -#define MJDEC_REG_W_XLEN_POS (8U) -#define MJDEC_REG_W_XLEN_LEN (3U) -#define MJDEC_REG_W_XLEN_MSK (((1U << MJDEC_REG_W_XLEN_LEN) - 1) << MJDEC_REG_W_XLEN_POS) -#define MJDEC_REG_W_XLEN_UMSK (~(((1U << MJDEC_REG_W_XLEN_LEN) - 1) << MJDEC_REG_W_XLEN_POS)) -#define MJDEC_REG_LAST_HF_BLK_DMY MJDEC_REG_LAST_HF_BLK_DMY -#define MJDEC_REG_LAST_HF_BLK_DMY_POS (11U) -#define MJDEC_REG_LAST_HF_BLK_DMY_LEN (1U) -#define MJDEC_REG_LAST_HF_BLK_DMY_MSK (((1U << MJDEC_REG_LAST_HF_BLK_DMY_LEN) - 1) << MJDEC_REG_LAST_HF_BLK_DMY_POS) -#define MJDEC_REG_LAST_HF_BLK_DMY_UMSK (~(((1U << MJDEC_REG_LAST_HF_BLK_DMY_LEN) - 1) << MJDEC_REG_LAST_HF_BLK_DMY_POS)) -#define MJDEC_REG_R_XLEN MJDEC_REG_R_XLEN -#define MJDEC_REG_R_XLEN_POS (12U) -#define MJDEC_REG_R_XLEN_LEN (3U) -#define MJDEC_REG_R_XLEN_MSK (((1U << MJDEC_REG_R_XLEN_LEN) - 1) << MJDEC_REG_R_XLEN_POS) -#define MJDEC_REG_R_XLEN_UMSK (~(((1U << MJDEC_REG_R_XLEN_LEN) - 1) << MJDEC_REG_R_XLEN_POS)) -#define MJDEC_REG_Q_MODE MJDEC_REG_Q_MODE -#define MJDEC_REG_Q_MODE_POS (16U) -#define MJDEC_REG_Q_MODE_LEN (7U) -#define MJDEC_REG_Q_MODE_MSK (((1U << MJDEC_REG_Q_MODE_LEN) - 1) << MJDEC_REG_Q_MODE_POS) -#define MJDEC_REG_Q_MODE_UMSK (~(((1U << MJDEC_REG_Q_MODE_LEN) - 1) << MJDEC_REG_Q_MODE_POS)) - -/* 0x08 : jdec_yy_frame_addr */ -#define MJDEC_JDEC_YY_FRAME_ADDR_OFFSET (0x08) -#define MJDEC_REG_YY_ADDR_START MJDEC_REG_YY_ADDR_START -#define MJDEC_REG_YY_ADDR_START_POS (0U) -#define MJDEC_REG_YY_ADDR_START_LEN (32U) -#define MJDEC_REG_YY_ADDR_START_MSK (((1U << MJDEC_REG_YY_ADDR_START_LEN) - 1) << MJDEC_REG_YY_ADDR_START_POS) -#define MJDEC_REG_YY_ADDR_START_UMSK (~(((1U << MJDEC_REG_YY_ADDR_START_LEN) - 1) << MJDEC_REG_YY_ADDR_START_POS)) - -/* 0x0C : jdec_uv_frame_addr */ -#define MJDEC_JDEC_UV_FRAME_ADDR_OFFSET (0x0C) -#define MJDEC_REG_UV_ADDR_START MJDEC_REG_UV_ADDR_START -#define MJDEC_REG_UV_ADDR_START_POS (0U) -#define MJDEC_REG_UV_ADDR_START_LEN (32U) -#define MJDEC_REG_UV_ADDR_START_MSK (((1U << MJDEC_REG_UV_ADDR_START_LEN) - 1) << MJDEC_REG_UV_ADDR_START_POS) -#define MJDEC_REG_UV_ADDR_START_UMSK (~(((1U << MJDEC_REG_UV_ADDR_START_LEN) - 1) << MJDEC_REG_UV_ADDR_START_POS)) - -/* 0x1C : jdec_control_3 */ -#define MJDEC_JDEC_CONTROL_3_OFFSET (0x1C) -#define MJDEC_REG_INT_NORMAL_EN MJDEC_REG_INT_NORMAL_EN -#define MJDEC_REG_INT_NORMAL_EN_POS (0U) -#define MJDEC_REG_INT_NORMAL_EN_LEN (1U) -#define MJDEC_REG_INT_NORMAL_EN_MSK (((1U << MJDEC_REG_INT_NORMAL_EN_LEN) - 1) << MJDEC_REG_INT_NORMAL_EN_POS) -#define MJDEC_REG_INT_NORMAL_EN_UMSK (~(((1U << MJDEC_REG_INT_NORMAL_EN_LEN) - 1) << MJDEC_REG_INT_NORMAL_EN_POS)) -#define MJDEC_REG_INT_IDLE_EN MJDEC_REG_INT_IDLE_EN -#define MJDEC_REG_INT_IDLE_EN_POS (1U) -#define MJDEC_REG_INT_IDLE_EN_LEN (1U) -#define MJDEC_REG_INT_IDLE_EN_MSK (((1U << MJDEC_REG_INT_IDLE_EN_LEN) - 1) << MJDEC_REG_INT_IDLE_EN_POS) -#define MJDEC_REG_INT_IDLE_EN_UMSK (~(((1U << MJDEC_REG_INT_IDLE_EN_LEN) - 1) << MJDEC_REG_INT_IDLE_EN_POS)) -#define MJDEC_STS_NORMAL_INT MJDEC_STS_NORMAL_INT -#define MJDEC_STS_NORMAL_INT_POS (4U) -#define MJDEC_STS_NORMAL_INT_LEN (1U) -#define MJDEC_STS_NORMAL_INT_MSK (((1U << MJDEC_STS_NORMAL_INT_LEN) - 1) << MJDEC_STS_NORMAL_INT_POS) -#define MJDEC_STS_NORMAL_INT_UMSK (~(((1U << MJDEC_STS_NORMAL_INT_LEN) - 1) << MJDEC_STS_NORMAL_INT_POS)) -#define MJDEC_STS_IDLE_INT MJDEC_STS_IDLE_INT -#define MJDEC_STS_IDLE_INT_POS (5U) -#define MJDEC_STS_IDLE_INT_LEN (1U) -#define MJDEC_STS_IDLE_INT_MSK (((1U << MJDEC_STS_IDLE_INT_LEN) - 1) << MJDEC_STS_IDLE_INT_POS) -#define MJDEC_STS_IDLE_INT_UMSK (~(((1U << MJDEC_STS_IDLE_INT_LEN) - 1) << MJDEC_STS_IDLE_INT_POS)) -#define MJDEC_MJPEG_IDLE MJDEC_MJPEG_IDLE -#define MJDEC_MJPEG_IDLE_POS (8U) -#define MJDEC_MJPEG_IDLE_LEN (1U) -#define MJDEC_MJPEG_IDLE_MSK (((1U << MJDEC_MJPEG_IDLE_LEN) - 1) << MJDEC_MJPEG_IDLE_POS) -#define MJDEC_MJPEG_IDLE_UMSK (~(((1U << MJDEC_MJPEG_IDLE_LEN) - 1) << MJDEC_MJPEG_IDLE_POS)) -#define MJDEC_MJPEG_FUNC MJDEC_MJPEG_FUNC -#define MJDEC_MJPEG_FUNC_POS (9U) -#define MJDEC_MJPEG_FUNC_LEN (1U) -#define MJDEC_MJPEG_FUNC_MSK (((1U << MJDEC_MJPEG_FUNC_LEN) - 1) << MJDEC_MJPEG_FUNC_POS) -#define MJDEC_MJPEG_FUNC_UMSK (~(((1U << MJDEC_MJPEG_FUNC_LEN) - 1) << MJDEC_MJPEG_FUNC_POS)) -#define MJDEC_MJPEG_FLSH MJDEC_MJPEG_FLSH -#define MJDEC_MJPEG_FLSH_POS (11U) -#define MJDEC_MJPEG_FLSH_LEN (1U) -#define MJDEC_MJPEG_FLSH_MSK (((1U << MJDEC_MJPEG_FLSH_LEN) - 1) << MJDEC_MJPEG_FLSH_POS) -#define MJDEC_MJPEG_FLSH_UMSK (~(((1U << MJDEC_MJPEG_FLSH_LEN) - 1) << MJDEC_MJPEG_FLSH_POS)) -#define MJDEC_AXI_READ_IDLE MJDEC_AXI_READ_IDLE -#define MJDEC_AXI_READ_IDLE_POS (14U) -#define MJDEC_AXI_READ_IDLE_LEN (1U) -#define MJDEC_AXI_READ_IDLE_MSK (((1U << MJDEC_AXI_READ_IDLE_LEN) - 1) << MJDEC_AXI_READ_IDLE_POS) -#define MJDEC_AXI_READ_IDLE_UMSK (~(((1U << MJDEC_AXI_READ_IDLE_LEN) - 1) << MJDEC_AXI_READ_IDLE_POS)) -#define MJDEC_AXI_WRITE_IDLE MJDEC_AXI_WRITE_IDLE -#define MJDEC_AXI_WRITE_IDLE_POS (15U) -#define MJDEC_AXI_WRITE_IDLE_LEN (1U) -#define MJDEC_AXI_WRITE_IDLE_MSK (((1U << MJDEC_AXI_WRITE_IDLE_LEN) - 1) << MJDEC_AXI_WRITE_IDLE_POS) -#define MJDEC_AXI_WRITE_IDLE_UMSK (~(((1U << MJDEC_AXI_WRITE_IDLE_LEN) - 1) << MJDEC_AXI_WRITE_IDLE_POS)) -#define MJDEC_REG_FRAME_CNT_TRGR_INT MJDEC_REG_FRAME_CNT_TRGR_INT -#define MJDEC_REG_FRAME_CNT_TRGR_INT_POS (16U) -#define MJDEC_REG_FRAME_CNT_TRGR_INT_LEN (5U) -#define MJDEC_REG_FRAME_CNT_TRGR_INT_MSK (((1U << MJDEC_REG_FRAME_CNT_TRGR_INT_LEN) - 1) << MJDEC_REG_FRAME_CNT_TRGR_INT_POS) -#define MJDEC_REG_FRAME_CNT_TRGR_INT_UMSK (~(((1U << MJDEC_REG_FRAME_CNT_TRGR_INT_LEN) - 1) << MJDEC_REG_FRAME_CNT_TRGR_INT_POS)) -#define MJDEC_FRAME_VALID_CNT MJDEC_FRAME_VALID_CNT -#define MJDEC_FRAME_VALID_CNT_POS (24U) -#define MJDEC_FRAME_VALID_CNT_LEN (8U) -#define MJDEC_FRAME_VALID_CNT_MSK (((1U << MJDEC_FRAME_VALID_CNT_LEN) - 1) << MJDEC_FRAME_VALID_CNT_POS) -#define MJDEC_FRAME_VALID_CNT_UMSK (~(((1U << MJDEC_FRAME_VALID_CNT_LEN) - 1) << MJDEC_FRAME_VALID_CNT_POS)) - -/* 0x20 : jdec_int_clr */ -#define MJDEC_JDEC_INT_CLR_OFFSET (0x20) -#define MJDEC_REG_INT_CLR MJDEC_REG_INT_CLR -#define MJDEC_REG_INT_CLR_POS (0U) -#define MJDEC_REG_INT_CLR_LEN (1U) -#define MJDEC_REG_INT_CLR_MSK (((1U << MJDEC_REG_INT_CLR_LEN) - 1) << MJDEC_REG_INT_CLR_POS) -#define MJDEC_REG_INT_CLR_UMSK (~(((1U << MJDEC_REG_INT_CLR_LEN) - 1) << MJDEC_REG_INT_CLR_POS)) -#define MJDEC_REG_YUV_FRAME_POP MJDEC_REG_YUV_FRAME_POP -#define MJDEC_REG_YUV_FRAME_POP_POS (1U) -#define MJDEC_REG_YUV_FRAME_POP_LEN (1U) -#define MJDEC_REG_YUV_FRAME_POP_MSK (((1U << MJDEC_REG_YUV_FRAME_POP_LEN) - 1) << MJDEC_REG_YUV_FRAME_POP_POS) -#define MJDEC_REG_YUV_FRAME_POP_UMSK (~(((1U << MJDEC_REG_YUV_FRAME_POP_LEN) - 1) << MJDEC_REG_YUV_FRAME_POP_POS)) - -/* 0x24 : jdec_fram_push */ -#define MJDEC_JDEC_FRAM_PUSH_OFFSET (0x24) -#define MJDEC_REG_JP_PUSH MJDEC_REG_JP_PUSH -#define MJDEC_REG_JP_PUSH_POS (0U) -#define MJDEC_REG_JP_PUSH_LEN (1U) -#define MJDEC_REG_JP_PUSH_MSK (((1U << MJDEC_REG_JP_PUSH_LEN) - 1) << MJDEC_REG_JP_PUSH_POS) -#define MJDEC_REG_JP_PUSH_UMSK (~(((1U << MJDEC_REG_JP_PUSH_LEN) - 1) << MJDEC_REG_JP_PUSH_POS)) -#define MJDEC_REG_JP_ADDR MJDEC_REG_JP_ADDR -#define MJDEC_REG_JP_ADDR_POS (2U) -#define MJDEC_REG_JP_ADDR_LEN (30U) -#define MJDEC_REG_JP_ADDR_MSK (((1U << MJDEC_REG_JP_ADDR_LEN) - 1) << MJDEC_REG_JP_ADDR_POS) -#define MJDEC_REG_JP_ADDR_UMSK (~(((1U << MJDEC_REG_JP_ADDR_LEN) - 1) << MJDEC_REG_JP_ADDR_POS)) - -/* 0x28 : jdec_fram_sts */ -#define MJDEC_JDEC_FRAM_STS_OFFSET (0x28) -#define MJDEC_JP_FRAME_CNT MJDEC_JP_FRAME_CNT -#define MJDEC_JP_FRAME_CNT_POS (0U) -#define MJDEC_JP_FRAME_CNT_LEN (5U) -#define MJDEC_JP_FRAME_CNT_MSK (((1U << MJDEC_JP_FRAME_CNT_LEN) - 1) << MJDEC_JP_FRAME_CNT_POS) -#define MJDEC_JP_FRAME_CNT_UMSK (~(((1U << MJDEC_JP_FRAME_CNT_LEN) - 1) << MJDEC_JP_FRAME_CNT_POS)) - -/* 0x2C : jdec_frame_size */ -#define MJDEC_JDEC_FRAME_SIZE_OFFSET (0x2C) -#define MJDEC_REG_FRAME_WBLK MJDEC_REG_FRAME_WBLK -#define MJDEC_REG_FRAME_WBLK_POS (0U) -#define MJDEC_REG_FRAME_WBLK_LEN (12U) -#define MJDEC_REG_FRAME_WBLK_MSK (((1U << MJDEC_REG_FRAME_WBLK_LEN) - 1) << MJDEC_REG_FRAME_WBLK_POS) -#define MJDEC_REG_FRAME_WBLK_UMSK (~(((1U << MJDEC_REG_FRAME_WBLK_LEN) - 1) << MJDEC_REG_FRAME_WBLK_POS)) -#define MJDEC_REG_FRAME_HBLK MJDEC_REG_FRAME_HBLK -#define MJDEC_REG_FRAME_HBLK_POS (16U) -#define MJDEC_REG_FRAME_HBLK_LEN (12U) -#define MJDEC_REG_FRAME_HBLK_MSK (((1U << MJDEC_REG_FRAME_HBLK_LEN) - 1) << MJDEC_REG_FRAME_HBLK_POS) -#define MJDEC_REG_FRAME_HBLK_UMSK (~(((1U << MJDEC_REG_FRAME_HBLK_LEN) - 1) << MJDEC_REG_FRAME_HBLK_POS)) - -/* 0x30 : jdec_header_skip */ -#define MJDEC_JDEC_HEADER_SKIP_OFFSET (0x30) -#define MJDEC_REG_HDER_SKIP_BYTE MJDEC_REG_HDER_SKIP_BYTE -#define MJDEC_REG_HDER_SKIP_BYTE_POS (0U) -#define MJDEC_REG_HDER_SKIP_BYTE_LEN (16U) -#define MJDEC_REG_HDER_SKIP_BYTE_MSK (((1U << MJDEC_REG_HDER_SKIP_BYTE_LEN) - 1) << MJDEC_REG_HDER_SKIP_BYTE_POS) -#define MJDEC_REG_HDER_SKIP_BYTE_UMSK (~(((1U << MJDEC_REG_HDER_SKIP_BYTE_LEN) - 1) << MJDEC_REG_HDER_SKIP_BYTE_POS)) -#define MJDEC_REG_HDER_SKIP MJDEC_REG_HDER_SKIP -#define MJDEC_REG_HDER_SKIP_POS (16U) -#define MJDEC_REG_HDER_SKIP_LEN (1U) -#define MJDEC_REG_HDER_SKIP_MSK (((1U << MJDEC_REG_HDER_SKIP_LEN) - 1) << MJDEC_REG_HDER_SKIP_POS) -#define MJDEC_REG_HDER_SKIP_UMSK (~(((1U << MJDEC_REG_HDER_SKIP_LEN) - 1) << MJDEC_REG_HDER_SKIP_POS)) - -/* 0x40 : jp_addr0 */ -#define MJDEC_JP_ADDR0_OFFSET (0x40) -#define MJDEC_JP_ADDR_0 MJDEC_JP_ADDR_0 -#define MJDEC_JP_ADDR_0_POS (0U) -#define MJDEC_JP_ADDR_0_LEN (32U) -#define MJDEC_JP_ADDR_0_MSK (((1U << MJDEC_JP_ADDR_0_LEN) - 1) << MJDEC_JP_ADDR_0_POS) -#define MJDEC_JP_ADDR_0_UMSK (~(((1U << MJDEC_JP_ADDR_0_LEN) - 1) << MJDEC_JP_ADDR_0_POS)) - -/* 0x44 : jp_addr1 */ -#define MJDEC_JP_ADDR1_OFFSET (0x44) -#define MJDEC_JP_ADDR_1 MJDEC_JP_ADDR_1 -#define MJDEC_JP_ADDR_1_POS (0U) -#define MJDEC_JP_ADDR_1_LEN (32U) -#define MJDEC_JP_ADDR_1_MSK (((1U << MJDEC_JP_ADDR_1_LEN) - 1) << MJDEC_JP_ADDR_1_POS) -#define MJDEC_JP_ADDR_1_UMSK (~(((1U << MJDEC_JP_ADDR_1_LEN) - 1) << MJDEC_JP_ADDR_1_POS)) - -/* 0x48 : jp_addr2 */ -#define MJDEC_JP_ADDR2_OFFSET (0x48) -#define MJDEC_JP_ADDR_2 MJDEC_JP_ADDR_2 -#define MJDEC_JP_ADDR_2_POS (0U) -#define MJDEC_JP_ADDR_2_LEN (32U) -#define MJDEC_JP_ADDR_2_MSK (((1U << MJDEC_JP_ADDR_2_LEN) - 1) << MJDEC_JP_ADDR_2_POS) -#define MJDEC_JP_ADDR_2_UMSK (~(((1U << MJDEC_JP_ADDR_2_LEN) - 1) << MJDEC_JP_ADDR_2_POS)) - -/* 0x4C : jp_addr3 */ -#define MJDEC_JP_ADDR3_OFFSET (0x4C) -#define MJDEC_JP_ADDR_3 MJDEC_JP_ADDR_3 -#define MJDEC_JP_ADDR_3_POS (0U) -#define MJDEC_JP_ADDR_3_LEN (32U) -#define MJDEC_JP_ADDR_3_MSK (((1U << MJDEC_JP_ADDR_3_LEN) - 1) << MJDEC_JP_ADDR_3_POS) -#define MJDEC_JP_ADDR_3_UMSK (~(((1U << MJDEC_JP_ADDR_3_LEN) - 1) << MJDEC_JP_ADDR_3_POS)) - -/* 0x50 : jp_addr4 */ -#define MJDEC_JP_ADDR4_OFFSET (0x50) -#define MJDEC_JP_ADDR_4 MJDEC_JP_ADDR_4 -#define MJDEC_JP_ADDR_4_POS (0U) -#define MJDEC_JP_ADDR_4_LEN (32U) -#define MJDEC_JP_ADDR_4_MSK (((1U << MJDEC_JP_ADDR_4_LEN) - 1) << MJDEC_JP_ADDR_4_POS) -#define MJDEC_JP_ADDR_4_UMSK (~(((1U << MJDEC_JP_ADDR_4_LEN) - 1) << MJDEC_JP_ADDR_4_POS)) - -/* 0x54 : jp_addr5 */ -#define MJDEC_JP_ADDR5_OFFSET (0x54) -#define MJDEC_JP_ADDR_5 MJDEC_JP_ADDR_5 -#define MJDEC_JP_ADDR_5_POS (0U) -#define MJDEC_JP_ADDR_5_LEN (32U) -#define MJDEC_JP_ADDR_5_MSK (((1U << MJDEC_JP_ADDR_5_LEN) - 1) << MJDEC_JP_ADDR_5_POS) -#define MJDEC_JP_ADDR_5_UMSK (~(((1U << MJDEC_JP_ADDR_5_LEN) - 1) << MJDEC_JP_ADDR_5_POS)) - -/* 0x58 : jp_addr6 */ -#define MJDEC_JP_ADDR6_OFFSET (0x58) -#define MJDEC_JP_ADDR_6 MJDEC_JP_ADDR_6 -#define MJDEC_JP_ADDR_6_POS (0U) -#define MJDEC_JP_ADDR_6_LEN (32U) -#define MJDEC_JP_ADDR_6_MSK (((1U << MJDEC_JP_ADDR_6_LEN) - 1) << MJDEC_JP_ADDR_6_POS) -#define MJDEC_JP_ADDR_6_UMSK (~(((1U << MJDEC_JP_ADDR_6_LEN) - 1) << MJDEC_JP_ADDR_6_POS)) - -/* 0x5C : jp_addr7 */ -#define MJDEC_JP_ADDR7_OFFSET (0x5C) -#define MJDEC_JP_ADDR_7 MJDEC_JP_ADDR_7 -#define MJDEC_JP_ADDR_7_POS (0U) -#define MJDEC_JP_ADDR_7_LEN (32U) -#define MJDEC_JP_ADDR_7_MSK (((1U << MJDEC_JP_ADDR_7_LEN) - 1) << MJDEC_JP_ADDR_7_POS) -#define MJDEC_JP_ADDR_7_UMSK (~(((1U << MJDEC_JP_ADDR_7_LEN) - 1) << MJDEC_JP_ADDR_7_POS)) - -/* 0x60 : jp_addr_8 */ -#define MJDEC_JP_ADDR_8_OFFSET (0x60) -#define MJDEC_JP_ADDR_8 MJDEC_JP_ADDR_8 -#define MJDEC_JP_ADDR_8_POS (0U) -#define MJDEC_JP_ADDR_8_LEN (32U) -#define MJDEC_JP_ADDR_8_MSK (((1U << MJDEC_JP_ADDR_8_LEN) - 1) << MJDEC_JP_ADDR_8_POS) -#define MJDEC_JP_ADDR_8_UMSK (~(((1U << MJDEC_JP_ADDR_8_LEN) - 1) << MJDEC_JP_ADDR_8_POS)) - -/* 0x64 : jp_addr_9 */ -#define MJDEC_JP_ADDR_9_OFFSET (0x64) -#define MJDEC_JP_ADDR_9 MJDEC_JP_ADDR_9 -#define MJDEC_JP_ADDR_9_POS (0U) -#define MJDEC_JP_ADDR_9_LEN (32U) -#define MJDEC_JP_ADDR_9_MSK (((1U << MJDEC_JP_ADDR_9_LEN) - 1) << MJDEC_JP_ADDR_9_POS) -#define MJDEC_JP_ADDR_9_UMSK (~(((1U << MJDEC_JP_ADDR_9_LEN) - 1) << MJDEC_JP_ADDR_9_POS)) - -/* 0x68 : jp_addr_a */ -#define MJDEC_JP_ADDR_A_OFFSET (0x68) -#define MJDEC_JP_ADDR_A MJDEC_JP_ADDR_A -#define MJDEC_JP_ADDR_A_POS (0U) -#define MJDEC_JP_ADDR_A_LEN (32U) -#define MJDEC_JP_ADDR_A_MSK (((1U << MJDEC_JP_ADDR_A_LEN) - 1) << MJDEC_JP_ADDR_A_POS) -#define MJDEC_JP_ADDR_A_UMSK (~(((1U << MJDEC_JP_ADDR_A_LEN) - 1) << MJDEC_JP_ADDR_A_POS)) - -/* 0x6C : jp_addr_b */ -#define MJDEC_JP_ADDR_B_OFFSET (0x6C) -#define MJDEC_JP_ADDR_B MJDEC_JP_ADDR_B -#define MJDEC_JP_ADDR_B_POS (0U) -#define MJDEC_JP_ADDR_B_LEN (32U) -#define MJDEC_JP_ADDR_B_MSK (((1U << MJDEC_JP_ADDR_B_LEN) - 1) << MJDEC_JP_ADDR_B_POS) -#define MJDEC_JP_ADDR_B_UMSK (~(((1U << MJDEC_JP_ADDR_B_LEN) - 1) << MJDEC_JP_ADDR_B_POS)) - -/* 0x70 : jp_addr_c */ -#define MJDEC_JP_ADDR_C_OFFSET (0x70) -#define MJDEC_JP_ADDR_C MJDEC_JP_ADDR_C -#define MJDEC_JP_ADDR_C_POS (0U) -#define MJDEC_JP_ADDR_C_LEN (32U) -#define MJDEC_JP_ADDR_C_MSK (((1U << MJDEC_JP_ADDR_C_LEN) - 1) << MJDEC_JP_ADDR_C_POS) -#define MJDEC_JP_ADDR_C_UMSK (~(((1U << MJDEC_JP_ADDR_C_LEN) - 1) << MJDEC_JP_ADDR_C_POS)) - -/* 0x74 : jp_addr_d */ -#define MJDEC_JP_ADDR_D_OFFSET (0x74) -#define MJDEC_JP_ADDR_D MJDEC_JP_ADDR_D -#define MJDEC_JP_ADDR_D_POS (0U) -#define MJDEC_JP_ADDR_D_LEN (32U) -#define MJDEC_JP_ADDR_D_MSK (((1U << MJDEC_JP_ADDR_D_LEN) - 1) << MJDEC_JP_ADDR_D_POS) -#define MJDEC_JP_ADDR_D_UMSK (~(((1U << MJDEC_JP_ADDR_D_LEN) - 1) << MJDEC_JP_ADDR_D_POS)) - -/* 0x78 : jp_addr_e */ -#define MJDEC_JP_ADDR_E_OFFSET (0x78) -#define MJDEC_JP_ADDR_E MJDEC_JP_ADDR_E -#define MJDEC_JP_ADDR_E_POS (0U) -#define MJDEC_JP_ADDR_E_LEN (32U) -#define MJDEC_JP_ADDR_E_MSK (((1U << MJDEC_JP_ADDR_E_LEN) - 1) << MJDEC_JP_ADDR_E_POS) -#define MJDEC_JP_ADDR_E_UMSK (~(((1U << MJDEC_JP_ADDR_E_LEN) - 1) << MJDEC_JP_ADDR_E_POS)) - -/* 0x7C : jp_addr_f */ -#define MJDEC_JP_ADDR_F_OFFSET (0x7C) -#define MJDEC_JP_ADDR_F MJDEC_JP_ADDR_F -#define MJDEC_JP_ADDR_F_POS (0U) -#define MJDEC_JP_ADDR_F_LEN (32U) -#define MJDEC_JP_ADDR_F_MSK (((1U << MJDEC_JP_ADDR_F_LEN) - 1) << MJDEC_JP_ADDR_F_POS) -#define MJDEC_JP_ADDR_F_UMSK (~(((1U << MJDEC_JP_ADDR_F_LEN) - 1) << MJDEC_JP_ADDR_F_POS)) - -/* 0x1F0 : mjdec_debug */ -#define MJDEC_DEBUG_OFFSET (0x1F0) -#define MJDEC_REG_MJDEC_DBG_EN MJDEC_REG_MJDEC_DBG_EN -#define MJDEC_REG_MJDEC_DBG_EN_POS (0U) -#define MJDEC_REG_MJDEC_DBG_EN_LEN (1U) -#define MJDEC_REG_MJDEC_DBG_EN_MSK (((1U << MJDEC_REG_MJDEC_DBG_EN_LEN) - 1) << MJDEC_REG_MJDEC_DBG_EN_POS) -#define MJDEC_REG_MJDEC_DBG_EN_UMSK (~(((1U << MJDEC_REG_MJDEC_DBG_EN_LEN) - 1) << MJDEC_REG_MJDEC_DBG_EN_POS)) -#define MJDEC_REG_MJDEC_DBG_SEL MJDEC_REG_MJDEC_DBG_SEL -#define MJDEC_REG_MJDEC_DBG_SEL_POS (4U) -#define MJDEC_REG_MJDEC_DBG_SEL_LEN (4U) -#define MJDEC_REG_MJDEC_DBG_SEL_MSK (((1U << MJDEC_REG_MJDEC_DBG_SEL_LEN) - 1) << MJDEC_REG_MJDEC_DBG_SEL_POS) -#define MJDEC_REG_MJDEC_DBG_SEL_UMSK (~(((1U << MJDEC_REG_MJDEC_DBG_SEL_LEN) - 1) << MJDEC_REG_MJDEC_DBG_SEL_POS)) - -/* 0x1FC : mjdec_dummy_reg */ -#define MJDEC_DUMMY_REG_OFFSET (0x1FC) -#define MJDEC_JDEC_DUMMY_REG MJDEC_JDEC_DUMMY_REG -#define MJDEC_JDEC_DUMMY_REG_POS (0U) -#define MJDEC_JDEC_DUMMY_REG_LEN (32U) -#define MJDEC_JDEC_DUMMY_REG_MSK (((1U << MJDEC_JDEC_DUMMY_REG_LEN) - 1) << MJDEC_JDEC_DUMMY_REG_POS) -#define MJDEC_JDEC_DUMMY_REG_UMSK (~(((1U << MJDEC_JDEC_DUMMY_REG_LEN) - 1) << MJDEC_JDEC_DUMMY_REG_POS)) - -struct mjdec_reg { - /* 0x0 : jdec_control_1 */ - union { - struct { - uint32_t reg_mj_dec_enable : 1; /* [ 0], r/w, 0x0 */ - uint32_t reg_swap_mode : 1; /* [ 1], r/w, 0x0 */ - uint32_t reg_u_even : 1; /* [ 2], r/w, 0x1 */ - uint32_t reg_yuv_mode : 2; /* [ 4: 3], r/w, 0x0 */ - uint32_t reg_last_hf_wblk_dmy : 1; /* [ 5], r/w, 0x0 */ - uint32_t reg_last_hf_hblk_dmy : 1; /* [ 6], r/w, 0x0 */ - uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ - uint32_t reg_w_xlen : 3; /* [10: 8], r/w, 0x3 */ - uint32_t reg_last_hf_blk_dmy : 1; /* [ 11], r/w, 0x0 */ - uint32_t reg_r_xlen : 3; /* [14:12], r/w, 0x3 */ - uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */ - uint32_t reg_q_mode : 7; /* [22:16], r/w, 0x32 */ - uint32_t reserved_23_31 : 9; /* [31:23], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } jdec_control_1; - - /* 0x4 reserved */ - uint8_t RESERVED0x4[4]; - - /* 0x08 : jdec_yy_frame_addr */ - union { - struct { - uint32_t reg_yy_addr_start : 32; /* [31: 0], r/w, 0x80000000 */ - } BF; - uint32_t WORD; - } jdec_yy_frame_addr; - - /* 0x0C : jdec_uv_frame_addr */ - union { - struct { - uint32_t reg_uv_addr_start : 32; /* [31: 0], r/w, 0x80000000 */ - } BF; - uint32_t WORD; - } jdec_uv_frame_addr; - - /* 0x10 reserved */ - uint8_t RESERVED0x10[12]; - - /* 0x1C : jdec_control_3 */ - union { - struct { - uint32_t reg_int_normal_en : 1; /* [ 0], r/w, 0x1 */ - uint32_t reg_int_idle_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t reserved_2_3 : 2; /* [ 3: 2], rsvd, 0x0 */ - uint32_t sts_normal_int : 1; /* [ 4], r, 0x0 */ - uint32_t sts_idle_int : 1; /* [ 5], r, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t mjpeg_idle : 1; /* [ 8], r, 0x1 */ - uint32_t mjpeg_func : 1; /* [ 9], r, 0x0 */ - uint32_t reserved_10 : 1; /* [ 10], rsvd, 0x0 */ - uint32_t mjpeg_flsh : 1; /* [ 11], r, 0x0 */ - uint32_t reserved_12_13 : 2; /* [13:12], rsvd, 0x0 */ - uint32_t axi_read_idle : 1; /* [ 14], r, 0x0 */ - uint32_t axi_write_idle : 1; /* [ 15], r, 0x0 */ - uint32_t reg_frame_cnt_trgr_int : 5; /* [20:16], r/w, 0x0 */ - uint32_t reserved_21_23 : 3; /* [23:21], rsvd, 0x0 */ - uint32_t frame_valid_cnt : 8; /* [31:24], r, 0x0 */ - } BF; - uint32_t WORD; - } jdec_control_3; - - /* 0x20 : jdec_int_clr */ - union { - struct { - uint32_t reg_int_clr : 1; /* [ 0], w1p, 0x0 */ - uint32_t reg_yuv_frame_pop : 1; /* [ 1], w1p, 0x0 */ - uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } jdec_int_clr; - - /* 0x24 : jdec_fram_push */ - union { - struct { - uint32_t reg_jp_push : 1; /* [ 0], w1p, 0x0 */ - uint32_t reserved_1 : 1; /* [ 1], rsvd, 0x0 */ - uint32_t reg_jp_addr : 30; /* [31: 2], r/w, 0x0 */ - } BF; - uint32_t WORD; - } jdec_fram_push; - - /* 0x28 : jdec_fram_sts */ - union { - struct { - uint32_t jp_frame_cnt : 5; /* [ 4: 0], r, 0x0 */ - uint32_t reserved_5_31 : 27; /* [31: 5], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } jdec_fram_sts; - - /* 0x2C : jdec_frame_size */ - union { - struct { - uint32_t reg_frame_wblk : 12; /* [11: 0], r/w, 0xf */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_frame_hblk : 12; /* [27:16], r/w, 0x14 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } jdec_frame_size; - - /* 0x30 : jdec_header_skip */ - union { - struct { - uint32_t reg_hder_skip_byte : 16; /* [15: 0], r/w, 0x0 */ - uint32_t reg_hder_skip : 1; /* [ 16], r/w, 0x0 */ - uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } jdec_header_skip; - - /* 0x34 reserved */ - uint8_t RESERVED0x34[12]; - - /* 0x40 : jp_addr0 */ - union { - struct { - uint32_t jp_addr_0 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } jp_addr0; - - /* 0x44 : jp_addr1 */ - union { - struct { - uint32_t jp_addr_1 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } jp_addr1; - - /* 0x48 : jp_addr2 */ - union { - struct { - uint32_t jp_addr_2 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } jp_addr2; - - /* 0x4C : jp_addr3 */ - union { - struct { - uint32_t jp_addr_3 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } jp_addr3; - - /* 0x50 : jp_addr4 */ - union { - struct { - uint32_t jp_addr_4 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } jp_addr4; - - /* 0x54 : jp_addr5 */ - union { - struct { - uint32_t jp_addr_5 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } jp_addr5; - - /* 0x58 : jp_addr6 */ - union { - struct { - uint32_t jp_addr_6 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } jp_addr6; - - /* 0x5C : jp_addr7 */ - union { - struct { - uint32_t jp_addr_7 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } jp_addr7; - - /* 0x60 : jp_addr_8 */ - union { - struct { - uint32_t jp_addr_8 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } jp_addr_8; - - /* 0x64 : jp_addr_9 */ - union { - struct { - uint32_t jp_addr_9 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } jp_addr_9; - - /* 0x68 : jp_addr_a */ - union { - struct { - uint32_t jp_addr_a : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } jp_addr_a; - - /* 0x6C : jp_addr_b */ - union { - struct { - uint32_t jp_addr_b : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } jp_addr_b; - - /* 0x70 : jp_addr_c */ - union { - struct { - uint32_t jp_addr_c : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } jp_addr_c; - - /* 0x74 : jp_addr_d */ - union { - struct { - uint32_t jp_addr_d : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } jp_addr_d; - - /* 0x78 : jp_addr_e */ - union { - struct { - uint32_t jp_addr_e : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } jp_addr_e; - - /* 0x7C : jp_addr_f */ - union { - struct { - uint32_t jp_addr_f : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } jp_addr_f; - - /* 0x80 reserved */ - uint8_t RESERVED0x80[368]; - - /* 0x1F0 : mjdec_debug */ - union { - struct { - uint32_t reg_mjdec_dbg_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ - uint32_t reg_mjdec_dbg_sel : 4; /* [ 7: 4], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjdec_debug; - - /* 0x1f4 reserved */ - uint8_t RESERVED0x1f4[8]; - - /* 0x1FC : mjdec_dummy_reg */ - union { - struct { - uint32_t jdec_dummy_reg : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } mjdec_dummy_reg; -}; - -typedef volatile struct mjdec_reg mjdec_reg_t; - -#endif /* __MJDEC_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/mjpeg_q_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/mjpeg_q_reg.h deleted file mode 100644 index e429e76e28..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/mjpeg_q_reg.h +++ /dev/null @@ -1,1584 +0,0 @@ -/** - ****************************************************************************** - * @file mjpeg_q_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __MJPEG_Q_REG_H__ -#define __MJPEG_Q_REG_H__ - -#include "bl808.h" - -/* 0x400 : mjpeg_q_param_00 */ -#define MJPEG_Q_PARAM_00_OFFSET (0x400) -#define MJPEG_Q_REG_Q_0_00 MJPEG_Q_REG_Q_0_00 -#define MJPEG_Q_REG_Q_0_00_POS (0U) -#define MJPEG_Q_REG_Q_0_00_LEN (12U) -#define MJPEG_Q_REG_Q_0_00_MSK (((1U << MJPEG_Q_REG_Q_0_00_LEN) - 1) << MJPEG_Q_REG_Q_0_00_POS) -#define MJPEG_Q_REG_Q_0_00_UMSK (~(((1U << MJPEG_Q_REG_Q_0_00_LEN) - 1) << MJPEG_Q_REG_Q_0_00_POS)) -#define MJPEG_Q_REG_Q_0_01 MJPEG_Q_REG_Q_0_01 -#define MJPEG_Q_REG_Q_0_01_POS (16U) -#define MJPEG_Q_REG_Q_0_01_LEN (12U) -#define MJPEG_Q_REG_Q_0_01_MSK (((1U << MJPEG_Q_REG_Q_0_01_LEN) - 1) << MJPEG_Q_REG_Q_0_01_POS) -#define MJPEG_Q_REG_Q_0_01_UMSK (~(((1U << MJPEG_Q_REG_Q_0_01_LEN) - 1) << MJPEG_Q_REG_Q_0_01_POS)) - -/* 0x404 : mjpeg_q_param_02 */ -#define MJPEG_Q_PARAM_02_OFFSET (0x404) -#define MJPEG_Q_REG_Q_0_02 MJPEG_Q_REG_Q_0_02 -#define MJPEG_Q_REG_Q_0_02_POS (0U) -#define MJPEG_Q_REG_Q_0_02_LEN (12U) -#define MJPEG_Q_REG_Q_0_02_MSK (((1U << MJPEG_Q_REG_Q_0_02_LEN) - 1) << MJPEG_Q_REG_Q_0_02_POS) -#define MJPEG_Q_REG_Q_0_02_UMSK (~(((1U << MJPEG_Q_REG_Q_0_02_LEN) - 1) << MJPEG_Q_REG_Q_0_02_POS)) -#define MJPEG_Q_REG_Q_0_03 MJPEG_Q_REG_Q_0_03 -#define MJPEG_Q_REG_Q_0_03_POS (16U) -#define MJPEG_Q_REG_Q_0_03_LEN (12U) -#define MJPEG_Q_REG_Q_0_03_MSK (((1U << MJPEG_Q_REG_Q_0_03_LEN) - 1) << MJPEG_Q_REG_Q_0_03_POS) -#define MJPEG_Q_REG_Q_0_03_UMSK (~(((1U << MJPEG_Q_REG_Q_0_03_LEN) - 1) << MJPEG_Q_REG_Q_0_03_POS)) - -/* 0x408 : mjpeg_q_param_04 */ -#define MJPEG_Q_PARAM_04_OFFSET (0x408) -#define MJPEG_Q_REG_Q_0_04 MJPEG_Q_REG_Q_0_04 -#define MJPEG_Q_REG_Q_0_04_POS (0U) -#define MJPEG_Q_REG_Q_0_04_LEN (12U) -#define MJPEG_Q_REG_Q_0_04_MSK (((1U << MJPEG_Q_REG_Q_0_04_LEN) - 1) << MJPEG_Q_REG_Q_0_04_POS) -#define MJPEG_Q_REG_Q_0_04_UMSK (~(((1U << MJPEG_Q_REG_Q_0_04_LEN) - 1) << MJPEG_Q_REG_Q_0_04_POS)) -#define MJPEG_Q_REG_Q_0_05 MJPEG_Q_REG_Q_0_05 -#define MJPEG_Q_REG_Q_0_05_POS (16U) -#define MJPEG_Q_REG_Q_0_05_LEN (12U) -#define MJPEG_Q_REG_Q_0_05_MSK (((1U << MJPEG_Q_REG_Q_0_05_LEN) - 1) << MJPEG_Q_REG_Q_0_05_POS) -#define MJPEG_Q_REG_Q_0_05_UMSK (~(((1U << MJPEG_Q_REG_Q_0_05_LEN) - 1) << MJPEG_Q_REG_Q_0_05_POS)) - -/* 0x40C : mjpeg_q_param_06 */ -#define MJPEG_Q_PARAM_06_OFFSET (0x40C) -#define MJPEG_Q_REG_Q_0_06 MJPEG_Q_REG_Q_0_06 -#define MJPEG_Q_REG_Q_0_06_POS (0U) -#define MJPEG_Q_REG_Q_0_06_LEN (12U) -#define MJPEG_Q_REG_Q_0_06_MSK (((1U << MJPEG_Q_REG_Q_0_06_LEN) - 1) << MJPEG_Q_REG_Q_0_06_POS) -#define MJPEG_Q_REG_Q_0_06_UMSK (~(((1U << MJPEG_Q_REG_Q_0_06_LEN) - 1) << MJPEG_Q_REG_Q_0_06_POS)) -#define MJPEG_Q_REG_Q_0_07 MJPEG_Q_REG_Q_0_07 -#define MJPEG_Q_REG_Q_0_07_POS (16U) -#define MJPEG_Q_REG_Q_0_07_LEN (12U) -#define MJPEG_Q_REG_Q_0_07_MSK (((1U << MJPEG_Q_REG_Q_0_07_LEN) - 1) << MJPEG_Q_REG_Q_0_07_POS) -#define MJPEG_Q_REG_Q_0_07_UMSK (~(((1U << MJPEG_Q_REG_Q_0_07_LEN) - 1) << MJPEG_Q_REG_Q_0_07_POS)) - -/* 0x410 : mjpeg_q_param_08 */ -#define MJPEG_Q_PARAM_08_OFFSET (0x410) -#define MJPEG_Q_REG_Q_0_08 MJPEG_Q_REG_Q_0_08 -#define MJPEG_Q_REG_Q_0_08_POS (0U) -#define MJPEG_Q_REG_Q_0_08_LEN (12U) -#define MJPEG_Q_REG_Q_0_08_MSK (((1U << MJPEG_Q_REG_Q_0_08_LEN) - 1) << MJPEG_Q_REG_Q_0_08_POS) -#define MJPEG_Q_REG_Q_0_08_UMSK (~(((1U << MJPEG_Q_REG_Q_0_08_LEN) - 1) << MJPEG_Q_REG_Q_0_08_POS)) -#define MJPEG_Q_REG_Q_0_09 MJPEG_Q_REG_Q_0_09 -#define MJPEG_Q_REG_Q_0_09_POS (16U) -#define MJPEG_Q_REG_Q_0_09_LEN (12U) -#define MJPEG_Q_REG_Q_0_09_MSK (((1U << MJPEG_Q_REG_Q_0_09_LEN) - 1) << MJPEG_Q_REG_Q_0_09_POS) -#define MJPEG_Q_REG_Q_0_09_UMSK (~(((1U << MJPEG_Q_REG_Q_0_09_LEN) - 1) << MJPEG_Q_REG_Q_0_09_POS)) - -/* 0x414 : mjpeg_q_param_0a */ -#define MJPEG_Q_PARAM_0A_OFFSET (0x414) -#define MJPEG_Q_REG_Q_0_0A MJPEG_Q_REG_Q_0_0A -#define MJPEG_Q_REG_Q_0_0A_POS (0U) -#define MJPEG_Q_REG_Q_0_0A_LEN (12U) -#define MJPEG_Q_REG_Q_0_0A_MSK (((1U << MJPEG_Q_REG_Q_0_0A_LEN) - 1) << MJPEG_Q_REG_Q_0_0A_POS) -#define MJPEG_Q_REG_Q_0_0A_UMSK (~(((1U << MJPEG_Q_REG_Q_0_0A_LEN) - 1) << MJPEG_Q_REG_Q_0_0A_POS)) -#define MJPEG_Q_REG_Q_0_0B MJPEG_Q_REG_Q_0_0B -#define MJPEG_Q_REG_Q_0_0B_POS (16U) -#define MJPEG_Q_REG_Q_0_0B_LEN (12U) -#define MJPEG_Q_REG_Q_0_0B_MSK (((1U << MJPEG_Q_REG_Q_0_0B_LEN) - 1) << MJPEG_Q_REG_Q_0_0B_POS) -#define MJPEG_Q_REG_Q_0_0B_UMSK (~(((1U << MJPEG_Q_REG_Q_0_0B_LEN) - 1) << MJPEG_Q_REG_Q_0_0B_POS)) - -/* 0x418 : mjpeg_q_param_0c */ -#define MJPEG_Q_PARAM_0C_OFFSET (0x418) -#define MJPEG_Q_REG_Q_0_0C MJPEG_Q_REG_Q_0_0C -#define MJPEG_Q_REG_Q_0_0C_POS (0U) -#define MJPEG_Q_REG_Q_0_0C_LEN (12U) -#define MJPEG_Q_REG_Q_0_0C_MSK (((1U << MJPEG_Q_REG_Q_0_0C_LEN) - 1) << MJPEG_Q_REG_Q_0_0C_POS) -#define MJPEG_Q_REG_Q_0_0C_UMSK (~(((1U << MJPEG_Q_REG_Q_0_0C_LEN) - 1) << MJPEG_Q_REG_Q_0_0C_POS)) -#define MJPEG_Q_REG_Q_0_0D MJPEG_Q_REG_Q_0_0D -#define MJPEG_Q_REG_Q_0_0D_POS (16U) -#define MJPEG_Q_REG_Q_0_0D_LEN (12U) -#define MJPEG_Q_REG_Q_0_0D_MSK (((1U << MJPEG_Q_REG_Q_0_0D_LEN) - 1) << MJPEG_Q_REG_Q_0_0D_POS) -#define MJPEG_Q_REG_Q_0_0D_UMSK (~(((1U << MJPEG_Q_REG_Q_0_0D_LEN) - 1) << MJPEG_Q_REG_Q_0_0D_POS)) - -/* 0x41C : mjpeg_q_param_0e */ -#define MJPEG_Q_PARAM_0E_OFFSET (0x41C) -#define MJPEG_Q_REG_Q_0_0E MJPEG_Q_REG_Q_0_0E -#define MJPEG_Q_REG_Q_0_0E_POS (0U) -#define MJPEG_Q_REG_Q_0_0E_LEN (12U) -#define MJPEG_Q_REG_Q_0_0E_MSK (((1U << MJPEG_Q_REG_Q_0_0E_LEN) - 1) << MJPEG_Q_REG_Q_0_0E_POS) -#define MJPEG_Q_REG_Q_0_0E_UMSK (~(((1U << MJPEG_Q_REG_Q_0_0E_LEN) - 1) << MJPEG_Q_REG_Q_0_0E_POS)) -#define MJPEG_Q_REG_Q_0_0F MJPEG_Q_REG_Q_0_0F -#define MJPEG_Q_REG_Q_0_0F_POS (16U) -#define MJPEG_Q_REG_Q_0_0F_LEN (12U) -#define MJPEG_Q_REG_Q_0_0F_MSK (((1U << MJPEG_Q_REG_Q_0_0F_LEN) - 1) << MJPEG_Q_REG_Q_0_0F_POS) -#define MJPEG_Q_REG_Q_0_0F_UMSK (~(((1U << MJPEG_Q_REG_Q_0_0F_LEN) - 1) << MJPEG_Q_REG_Q_0_0F_POS)) - -/* 0x420 : mjpeg_q_param_10 */ -#define MJPEG_Q_PARAM_10_OFFSET (0x420) -#define MJPEG_Q_REG_Q_0_10 MJPEG_Q_REG_Q_0_10 -#define MJPEG_Q_REG_Q_0_10_POS (0U) -#define MJPEG_Q_REG_Q_0_10_LEN (12U) -#define MJPEG_Q_REG_Q_0_10_MSK (((1U << MJPEG_Q_REG_Q_0_10_LEN) - 1) << MJPEG_Q_REG_Q_0_10_POS) -#define MJPEG_Q_REG_Q_0_10_UMSK (~(((1U << MJPEG_Q_REG_Q_0_10_LEN) - 1) << MJPEG_Q_REG_Q_0_10_POS)) -#define MJPEG_Q_REG_Q_0_11 MJPEG_Q_REG_Q_0_11 -#define MJPEG_Q_REG_Q_0_11_POS (16U) -#define MJPEG_Q_REG_Q_0_11_LEN (12U) -#define MJPEG_Q_REG_Q_0_11_MSK (((1U << MJPEG_Q_REG_Q_0_11_LEN) - 1) << MJPEG_Q_REG_Q_0_11_POS) -#define MJPEG_Q_REG_Q_0_11_UMSK (~(((1U << MJPEG_Q_REG_Q_0_11_LEN) - 1) << MJPEG_Q_REG_Q_0_11_POS)) - -/* 0x424 : mjpeg_q_param_12 */ -#define MJPEG_Q_PARAM_12_OFFSET (0x424) -#define MJPEG_Q_REG_Q_0_12 MJPEG_Q_REG_Q_0_12 -#define MJPEG_Q_REG_Q_0_12_POS (0U) -#define MJPEG_Q_REG_Q_0_12_LEN (12U) -#define MJPEG_Q_REG_Q_0_12_MSK (((1U << MJPEG_Q_REG_Q_0_12_LEN) - 1) << MJPEG_Q_REG_Q_0_12_POS) -#define MJPEG_Q_REG_Q_0_12_UMSK (~(((1U << MJPEG_Q_REG_Q_0_12_LEN) - 1) << MJPEG_Q_REG_Q_0_12_POS)) -#define MJPEG_Q_REG_Q_0_13 MJPEG_Q_REG_Q_0_13 -#define MJPEG_Q_REG_Q_0_13_POS (16U) -#define MJPEG_Q_REG_Q_0_13_LEN (12U) -#define MJPEG_Q_REG_Q_0_13_MSK (((1U << MJPEG_Q_REG_Q_0_13_LEN) - 1) << MJPEG_Q_REG_Q_0_13_POS) -#define MJPEG_Q_REG_Q_0_13_UMSK (~(((1U << MJPEG_Q_REG_Q_0_13_LEN) - 1) << MJPEG_Q_REG_Q_0_13_POS)) - -/* 0x428 : mjpeg_q_param_14 */ -#define MJPEG_Q_PARAM_14_OFFSET (0x428) -#define MJPEG_Q_REG_Q_0_14 MJPEG_Q_REG_Q_0_14 -#define MJPEG_Q_REG_Q_0_14_POS (0U) -#define MJPEG_Q_REG_Q_0_14_LEN (12U) -#define MJPEG_Q_REG_Q_0_14_MSK (((1U << MJPEG_Q_REG_Q_0_14_LEN) - 1) << MJPEG_Q_REG_Q_0_14_POS) -#define MJPEG_Q_REG_Q_0_14_UMSK (~(((1U << MJPEG_Q_REG_Q_0_14_LEN) - 1) << MJPEG_Q_REG_Q_0_14_POS)) -#define MJPEG_Q_REG_Q_0_15 MJPEG_Q_REG_Q_0_15 -#define MJPEG_Q_REG_Q_0_15_POS (16U) -#define MJPEG_Q_REG_Q_0_15_LEN (12U) -#define MJPEG_Q_REG_Q_0_15_MSK (((1U << MJPEG_Q_REG_Q_0_15_LEN) - 1) << MJPEG_Q_REG_Q_0_15_POS) -#define MJPEG_Q_REG_Q_0_15_UMSK (~(((1U << MJPEG_Q_REG_Q_0_15_LEN) - 1) << MJPEG_Q_REG_Q_0_15_POS)) - -/* 0x42C : mjpeg_q_param_16 */ -#define MJPEG_Q_PARAM_16_OFFSET (0x42C) -#define MJPEG_Q_REG_Q_0_16 MJPEG_Q_REG_Q_0_16 -#define MJPEG_Q_REG_Q_0_16_POS (0U) -#define MJPEG_Q_REG_Q_0_16_LEN (12U) -#define MJPEG_Q_REG_Q_0_16_MSK (((1U << MJPEG_Q_REG_Q_0_16_LEN) - 1) << MJPEG_Q_REG_Q_0_16_POS) -#define MJPEG_Q_REG_Q_0_16_UMSK (~(((1U << MJPEG_Q_REG_Q_0_16_LEN) - 1) << MJPEG_Q_REG_Q_0_16_POS)) -#define MJPEG_Q_REG_Q_0_17 MJPEG_Q_REG_Q_0_17 -#define MJPEG_Q_REG_Q_0_17_POS (16U) -#define MJPEG_Q_REG_Q_0_17_LEN (12U) -#define MJPEG_Q_REG_Q_0_17_MSK (((1U << MJPEG_Q_REG_Q_0_17_LEN) - 1) << MJPEG_Q_REG_Q_0_17_POS) -#define MJPEG_Q_REG_Q_0_17_UMSK (~(((1U << MJPEG_Q_REG_Q_0_17_LEN) - 1) << MJPEG_Q_REG_Q_0_17_POS)) - -/* 0x430 : mjpeg_q_param_18 */ -#define MJPEG_Q_PARAM_18_OFFSET (0x430) -#define MJPEG_Q_REG_Q_0_18 MJPEG_Q_REG_Q_0_18 -#define MJPEG_Q_REG_Q_0_18_POS (0U) -#define MJPEG_Q_REG_Q_0_18_LEN (12U) -#define MJPEG_Q_REG_Q_0_18_MSK (((1U << MJPEG_Q_REG_Q_0_18_LEN) - 1) << MJPEG_Q_REG_Q_0_18_POS) -#define MJPEG_Q_REG_Q_0_18_UMSK (~(((1U << MJPEG_Q_REG_Q_0_18_LEN) - 1) << MJPEG_Q_REG_Q_0_18_POS)) -#define MJPEG_Q_REG_Q_0_19 MJPEG_Q_REG_Q_0_19 -#define MJPEG_Q_REG_Q_0_19_POS (16U) -#define MJPEG_Q_REG_Q_0_19_LEN (12U) -#define MJPEG_Q_REG_Q_0_19_MSK (((1U << MJPEG_Q_REG_Q_0_19_LEN) - 1) << MJPEG_Q_REG_Q_0_19_POS) -#define MJPEG_Q_REG_Q_0_19_UMSK (~(((1U << MJPEG_Q_REG_Q_0_19_LEN) - 1) << MJPEG_Q_REG_Q_0_19_POS)) - -/* 0x434 : mjpeg_q_param_1a */ -#define MJPEG_Q_PARAM_1A_OFFSET (0x434) -#define MJPEG_Q_REG_Q_0_1A MJPEG_Q_REG_Q_0_1A -#define MJPEG_Q_REG_Q_0_1A_POS (0U) -#define MJPEG_Q_REG_Q_0_1A_LEN (12U) -#define MJPEG_Q_REG_Q_0_1A_MSK (((1U << MJPEG_Q_REG_Q_0_1A_LEN) - 1) << MJPEG_Q_REG_Q_0_1A_POS) -#define MJPEG_Q_REG_Q_0_1A_UMSK (~(((1U << MJPEG_Q_REG_Q_0_1A_LEN) - 1) << MJPEG_Q_REG_Q_0_1A_POS)) -#define MJPEG_Q_REG_Q_0_1B MJPEG_Q_REG_Q_0_1B -#define MJPEG_Q_REG_Q_0_1B_POS (16U) -#define MJPEG_Q_REG_Q_0_1B_LEN (12U) -#define MJPEG_Q_REG_Q_0_1B_MSK (((1U << MJPEG_Q_REG_Q_0_1B_LEN) - 1) << MJPEG_Q_REG_Q_0_1B_POS) -#define MJPEG_Q_REG_Q_0_1B_UMSK (~(((1U << MJPEG_Q_REG_Q_0_1B_LEN) - 1) << MJPEG_Q_REG_Q_0_1B_POS)) - -/* 0x438 : mjpeg_q_param_1c */ -#define MJPEG_Q_PARAM_1C_OFFSET (0x438) -#define MJPEG_Q_REG_Q_0_1C MJPEG_Q_REG_Q_0_1C -#define MJPEG_Q_REG_Q_0_1C_POS (0U) -#define MJPEG_Q_REG_Q_0_1C_LEN (12U) -#define MJPEG_Q_REG_Q_0_1C_MSK (((1U << MJPEG_Q_REG_Q_0_1C_LEN) - 1) << MJPEG_Q_REG_Q_0_1C_POS) -#define MJPEG_Q_REG_Q_0_1C_UMSK (~(((1U << MJPEG_Q_REG_Q_0_1C_LEN) - 1) << MJPEG_Q_REG_Q_0_1C_POS)) -#define MJPEG_Q_REG_Q_0_1D MJPEG_Q_REG_Q_0_1D -#define MJPEG_Q_REG_Q_0_1D_POS (16U) -#define MJPEG_Q_REG_Q_0_1D_LEN (12U) -#define MJPEG_Q_REG_Q_0_1D_MSK (((1U << MJPEG_Q_REG_Q_0_1D_LEN) - 1) << MJPEG_Q_REG_Q_0_1D_POS) -#define MJPEG_Q_REG_Q_0_1D_UMSK (~(((1U << MJPEG_Q_REG_Q_0_1D_LEN) - 1) << MJPEG_Q_REG_Q_0_1D_POS)) - -/* 0x43C : mjpeg_q_param_1e */ -#define MJPEG_Q_PARAM_1E_OFFSET (0x43C) -#define MJPEG_Q_REG_Q_0_1E MJPEG_Q_REG_Q_0_1E -#define MJPEG_Q_REG_Q_0_1E_POS (0U) -#define MJPEG_Q_REG_Q_0_1E_LEN (12U) -#define MJPEG_Q_REG_Q_0_1E_MSK (((1U << MJPEG_Q_REG_Q_0_1E_LEN) - 1) << MJPEG_Q_REG_Q_0_1E_POS) -#define MJPEG_Q_REG_Q_0_1E_UMSK (~(((1U << MJPEG_Q_REG_Q_0_1E_LEN) - 1) << MJPEG_Q_REG_Q_0_1E_POS)) -#define MJPEG_Q_REG_Q_0_1F MJPEG_Q_REG_Q_0_1F -#define MJPEG_Q_REG_Q_0_1F_POS (16U) -#define MJPEG_Q_REG_Q_0_1F_LEN (12U) -#define MJPEG_Q_REG_Q_0_1F_MSK (((1U << MJPEG_Q_REG_Q_0_1F_LEN) - 1) << MJPEG_Q_REG_Q_0_1F_POS) -#define MJPEG_Q_REG_Q_0_1F_UMSK (~(((1U << MJPEG_Q_REG_Q_0_1F_LEN) - 1) << MJPEG_Q_REG_Q_0_1F_POS)) - -/* 0x440 : mjpeg_q_param_20 */ -#define MJPEG_Q_PARAM_20_OFFSET (0x440) -#define MJPEG_Q_REG_Q_0_20 MJPEG_Q_REG_Q_0_20 -#define MJPEG_Q_REG_Q_0_20_POS (0U) -#define MJPEG_Q_REG_Q_0_20_LEN (12U) -#define MJPEG_Q_REG_Q_0_20_MSK (((1U << MJPEG_Q_REG_Q_0_20_LEN) - 1) << MJPEG_Q_REG_Q_0_20_POS) -#define MJPEG_Q_REG_Q_0_20_UMSK (~(((1U << MJPEG_Q_REG_Q_0_20_LEN) - 1) << MJPEG_Q_REG_Q_0_20_POS)) -#define MJPEG_Q_REG_Q_0_21 MJPEG_Q_REG_Q_0_21 -#define MJPEG_Q_REG_Q_0_21_POS (16U) -#define MJPEG_Q_REG_Q_0_21_LEN (12U) -#define MJPEG_Q_REG_Q_0_21_MSK (((1U << MJPEG_Q_REG_Q_0_21_LEN) - 1) << MJPEG_Q_REG_Q_0_21_POS) -#define MJPEG_Q_REG_Q_0_21_UMSK (~(((1U << MJPEG_Q_REG_Q_0_21_LEN) - 1) << MJPEG_Q_REG_Q_0_21_POS)) - -/* 0x444 : mjpeg_q_param_22 */ -#define MJPEG_Q_PARAM_22_OFFSET (0x444) -#define MJPEG_Q_REG_Q_0_22 MJPEG_Q_REG_Q_0_22 -#define MJPEG_Q_REG_Q_0_22_POS (0U) -#define MJPEG_Q_REG_Q_0_22_LEN (12U) -#define MJPEG_Q_REG_Q_0_22_MSK (((1U << MJPEG_Q_REG_Q_0_22_LEN) - 1) << MJPEG_Q_REG_Q_0_22_POS) -#define MJPEG_Q_REG_Q_0_22_UMSK (~(((1U << MJPEG_Q_REG_Q_0_22_LEN) - 1) << MJPEG_Q_REG_Q_0_22_POS)) -#define MJPEG_Q_REG_Q_0_23 MJPEG_Q_REG_Q_0_23 -#define MJPEG_Q_REG_Q_0_23_POS (16U) -#define MJPEG_Q_REG_Q_0_23_LEN (12U) -#define MJPEG_Q_REG_Q_0_23_MSK (((1U << MJPEG_Q_REG_Q_0_23_LEN) - 1) << MJPEG_Q_REG_Q_0_23_POS) -#define MJPEG_Q_REG_Q_0_23_UMSK (~(((1U << MJPEG_Q_REG_Q_0_23_LEN) - 1) << MJPEG_Q_REG_Q_0_23_POS)) - -/* 0x448 : mjpeg_q_param_24 */ -#define MJPEG_Q_PARAM_24_OFFSET (0x448) -#define MJPEG_Q_REG_Q_0_24 MJPEG_Q_REG_Q_0_24 -#define MJPEG_Q_REG_Q_0_24_POS (0U) -#define MJPEG_Q_REG_Q_0_24_LEN (12U) -#define MJPEG_Q_REG_Q_0_24_MSK (((1U << MJPEG_Q_REG_Q_0_24_LEN) - 1) << MJPEG_Q_REG_Q_0_24_POS) -#define MJPEG_Q_REG_Q_0_24_UMSK (~(((1U << MJPEG_Q_REG_Q_0_24_LEN) - 1) << MJPEG_Q_REG_Q_0_24_POS)) -#define MJPEG_Q_REG_Q_0_25 MJPEG_Q_REG_Q_0_25 -#define MJPEG_Q_REG_Q_0_25_POS (16U) -#define MJPEG_Q_REG_Q_0_25_LEN (12U) -#define MJPEG_Q_REG_Q_0_25_MSK (((1U << MJPEG_Q_REG_Q_0_25_LEN) - 1) << MJPEG_Q_REG_Q_0_25_POS) -#define MJPEG_Q_REG_Q_0_25_UMSK (~(((1U << MJPEG_Q_REG_Q_0_25_LEN) - 1) << MJPEG_Q_REG_Q_0_25_POS)) - -/* 0x44C : mjpeg_q_param_26 */ -#define MJPEG_Q_PARAM_26_OFFSET (0x44C) -#define MJPEG_Q_REG_Q_0_26 MJPEG_Q_REG_Q_0_26 -#define MJPEG_Q_REG_Q_0_26_POS (0U) -#define MJPEG_Q_REG_Q_0_26_LEN (12U) -#define MJPEG_Q_REG_Q_0_26_MSK (((1U << MJPEG_Q_REG_Q_0_26_LEN) - 1) << MJPEG_Q_REG_Q_0_26_POS) -#define MJPEG_Q_REG_Q_0_26_UMSK (~(((1U << MJPEG_Q_REG_Q_0_26_LEN) - 1) << MJPEG_Q_REG_Q_0_26_POS)) -#define MJPEG_Q_REG_Q_0_27 MJPEG_Q_REG_Q_0_27 -#define MJPEG_Q_REG_Q_0_27_POS (16U) -#define MJPEG_Q_REG_Q_0_27_LEN (12U) -#define MJPEG_Q_REG_Q_0_27_MSK (((1U << MJPEG_Q_REG_Q_0_27_LEN) - 1) << MJPEG_Q_REG_Q_0_27_POS) -#define MJPEG_Q_REG_Q_0_27_UMSK (~(((1U << MJPEG_Q_REG_Q_0_27_LEN) - 1) << MJPEG_Q_REG_Q_0_27_POS)) - -/* 0x450 : mjpeg_q_param_28 */ -#define MJPEG_Q_PARAM_28_OFFSET (0x450) -#define MJPEG_Q_REG_Q_0_28 MJPEG_Q_REG_Q_0_28 -#define MJPEG_Q_REG_Q_0_28_POS (0U) -#define MJPEG_Q_REG_Q_0_28_LEN (12U) -#define MJPEG_Q_REG_Q_0_28_MSK (((1U << MJPEG_Q_REG_Q_0_28_LEN) - 1) << MJPEG_Q_REG_Q_0_28_POS) -#define MJPEG_Q_REG_Q_0_28_UMSK (~(((1U << MJPEG_Q_REG_Q_0_28_LEN) - 1) << MJPEG_Q_REG_Q_0_28_POS)) -#define MJPEG_Q_REG_Q_0_29 MJPEG_Q_REG_Q_0_29 -#define MJPEG_Q_REG_Q_0_29_POS (16U) -#define MJPEG_Q_REG_Q_0_29_LEN (12U) -#define MJPEG_Q_REG_Q_0_29_MSK (((1U << MJPEG_Q_REG_Q_0_29_LEN) - 1) << MJPEG_Q_REG_Q_0_29_POS) -#define MJPEG_Q_REG_Q_0_29_UMSK (~(((1U << MJPEG_Q_REG_Q_0_29_LEN) - 1) << MJPEG_Q_REG_Q_0_29_POS)) - -/* 0x454 : mjpeg_q_param_2a */ -#define MJPEG_Q_PARAM_2A_OFFSET (0x454) -#define MJPEG_Q_REG_Q_0_2A MJPEG_Q_REG_Q_0_2A -#define MJPEG_Q_REG_Q_0_2A_POS (0U) -#define MJPEG_Q_REG_Q_0_2A_LEN (12U) -#define MJPEG_Q_REG_Q_0_2A_MSK (((1U << MJPEG_Q_REG_Q_0_2A_LEN) - 1) << MJPEG_Q_REG_Q_0_2A_POS) -#define MJPEG_Q_REG_Q_0_2A_UMSK (~(((1U << MJPEG_Q_REG_Q_0_2A_LEN) - 1) << MJPEG_Q_REG_Q_0_2A_POS)) -#define MJPEG_Q_REG_Q_0_2B MJPEG_Q_REG_Q_0_2B -#define MJPEG_Q_REG_Q_0_2B_POS (16U) -#define MJPEG_Q_REG_Q_0_2B_LEN (12U) -#define MJPEG_Q_REG_Q_0_2B_MSK (((1U << MJPEG_Q_REG_Q_0_2B_LEN) - 1) << MJPEG_Q_REG_Q_0_2B_POS) -#define MJPEG_Q_REG_Q_0_2B_UMSK (~(((1U << MJPEG_Q_REG_Q_0_2B_LEN) - 1) << MJPEG_Q_REG_Q_0_2B_POS)) - -/* 0x458 : mjpeg_q_param_2c */ -#define MJPEG_Q_PARAM_2C_OFFSET (0x458) -#define MJPEG_Q_REG_Q_0_2C MJPEG_Q_REG_Q_0_2C -#define MJPEG_Q_REG_Q_0_2C_POS (0U) -#define MJPEG_Q_REG_Q_0_2C_LEN (12U) -#define MJPEG_Q_REG_Q_0_2C_MSK (((1U << MJPEG_Q_REG_Q_0_2C_LEN) - 1) << MJPEG_Q_REG_Q_0_2C_POS) -#define MJPEG_Q_REG_Q_0_2C_UMSK (~(((1U << MJPEG_Q_REG_Q_0_2C_LEN) - 1) << MJPEG_Q_REG_Q_0_2C_POS)) -#define MJPEG_Q_REG_Q_0_2D MJPEG_Q_REG_Q_0_2D -#define MJPEG_Q_REG_Q_0_2D_POS (16U) -#define MJPEG_Q_REG_Q_0_2D_LEN (12U) -#define MJPEG_Q_REG_Q_0_2D_MSK (((1U << MJPEG_Q_REG_Q_0_2D_LEN) - 1) << MJPEG_Q_REG_Q_0_2D_POS) -#define MJPEG_Q_REG_Q_0_2D_UMSK (~(((1U << MJPEG_Q_REG_Q_0_2D_LEN) - 1) << MJPEG_Q_REG_Q_0_2D_POS)) - -/* 0x45C : mjpeg_q_param_2e */ -#define MJPEG_Q_PARAM_2E_OFFSET (0x45C) -#define MJPEG_Q_REG_Q_0_2E MJPEG_Q_REG_Q_0_2E -#define MJPEG_Q_REG_Q_0_2E_POS (0U) -#define MJPEG_Q_REG_Q_0_2E_LEN (12U) -#define MJPEG_Q_REG_Q_0_2E_MSK (((1U << MJPEG_Q_REG_Q_0_2E_LEN) - 1) << MJPEG_Q_REG_Q_0_2E_POS) -#define MJPEG_Q_REG_Q_0_2E_UMSK (~(((1U << MJPEG_Q_REG_Q_0_2E_LEN) - 1) << MJPEG_Q_REG_Q_0_2E_POS)) -#define MJPEG_Q_REG_Q_0_2F MJPEG_Q_REG_Q_0_2F -#define MJPEG_Q_REG_Q_0_2F_POS (16U) -#define MJPEG_Q_REG_Q_0_2F_LEN (12U) -#define MJPEG_Q_REG_Q_0_2F_MSK (((1U << MJPEG_Q_REG_Q_0_2F_LEN) - 1) << MJPEG_Q_REG_Q_0_2F_POS) -#define MJPEG_Q_REG_Q_0_2F_UMSK (~(((1U << MJPEG_Q_REG_Q_0_2F_LEN) - 1) << MJPEG_Q_REG_Q_0_2F_POS)) - -/* 0x460 : mjpeg_q_param_30 */ -#define MJPEG_Q_PARAM_30_OFFSET (0x460) -#define MJPEG_Q_REG_Q_0_30 MJPEG_Q_REG_Q_0_30 -#define MJPEG_Q_REG_Q_0_30_POS (0U) -#define MJPEG_Q_REG_Q_0_30_LEN (12U) -#define MJPEG_Q_REG_Q_0_30_MSK (((1U << MJPEG_Q_REG_Q_0_30_LEN) - 1) << MJPEG_Q_REG_Q_0_30_POS) -#define MJPEG_Q_REG_Q_0_30_UMSK (~(((1U << MJPEG_Q_REG_Q_0_30_LEN) - 1) << MJPEG_Q_REG_Q_0_30_POS)) -#define MJPEG_Q_REG_Q_0_31 MJPEG_Q_REG_Q_0_31 -#define MJPEG_Q_REG_Q_0_31_POS (16U) -#define MJPEG_Q_REG_Q_0_31_LEN (12U) -#define MJPEG_Q_REG_Q_0_31_MSK (((1U << MJPEG_Q_REG_Q_0_31_LEN) - 1) << MJPEG_Q_REG_Q_0_31_POS) -#define MJPEG_Q_REG_Q_0_31_UMSK (~(((1U << MJPEG_Q_REG_Q_0_31_LEN) - 1) << MJPEG_Q_REG_Q_0_31_POS)) - -/* 0x464 : mjpeg_q_param_32 */ -#define MJPEG_Q_PARAM_32_OFFSET (0x464) -#define MJPEG_Q_REG_Q_0_32 MJPEG_Q_REG_Q_0_32 -#define MJPEG_Q_REG_Q_0_32_POS (0U) -#define MJPEG_Q_REG_Q_0_32_LEN (12U) -#define MJPEG_Q_REG_Q_0_32_MSK (((1U << MJPEG_Q_REG_Q_0_32_LEN) - 1) << MJPEG_Q_REG_Q_0_32_POS) -#define MJPEG_Q_REG_Q_0_32_UMSK (~(((1U << MJPEG_Q_REG_Q_0_32_LEN) - 1) << MJPEG_Q_REG_Q_0_32_POS)) -#define MJPEG_Q_REG_Q_0_33 MJPEG_Q_REG_Q_0_33 -#define MJPEG_Q_REG_Q_0_33_POS (16U) -#define MJPEG_Q_REG_Q_0_33_LEN (12U) -#define MJPEG_Q_REG_Q_0_33_MSK (((1U << MJPEG_Q_REG_Q_0_33_LEN) - 1) << MJPEG_Q_REG_Q_0_33_POS) -#define MJPEG_Q_REG_Q_0_33_UMSK (~(((1U << MJPEG_Q_REG_Q_0_33_LEN) - 1) << MJPEG_Q_REG_Q_0_33_POS)) - -/* 0x468 : mjpeg_q_param_34 */ -#define MJPEG_Q_PARAM_34_OFFSET (0x468) -#define MJPEG_Q_REG_Q_0_34 MJPEG_Q_REG_Q_0_34 -#define MJPEG_Q_REG_Q_0_34_POS (0U) -#define MJPEG_Q_REG_Q_0_34_LEN (12U) -#define MJPEG_Q_REG_Q_0_34_MSK (((1U << MJPEG_Q_REG_Q_0_34_LEN) - 1) << MJPEG_Q_REG_Q_0_34_POS) -#define MJPEG_Q_REG_Q_0_34_UMSK (~(((1U << MJPEG_Q_REG_Q_0_34_LEN) - 1) << MJPEG_Q_REG_Q_0_34_POS)) -#define MJPEG_Q_REG_Q_0_35 MJPEG_Q_REG_Q_0_35 -#define MJPEG_Q_REG_Q_0_35_POS (16U) -#define MJPEG_Q_REG_Q_0_35_LEN (12U) -#define MJPEG_Q_REG_Q_0_35_MSK (((1U << MJPEG_Q_REG_Q_0_35_LEN) - 1) << MJPEG_Q_REG_Q_0_35_POS) -#define MJPEG_Q_REG_Q_0_35_UMSK (~(((1U << MJPEG_Q_REG_Q_0_35_LEN) - 1) << MJPEG_Q_REG_Q_0_35_POS)) - -/* 0x46C : mjpeg_q_param_36 */ -#define MJPEG_Q_PARAM_36_OFFSET (0x46C) -#define MJPEG_Q_REG_Q_0_36 MJPEG_Q_REG_Q_0_36 -#define MJPEG_Q_REG_Q_0_36_POS (0U) -#define MJPEG_Q_REG_Q_0_36_LEN (12U) -#define MJPEG_Q_REG_Q_0_36_MSK (((1U << MJPEG_Q_REG_Q_0_36_LEN) - 1) << MJPEG_Q_REG_Q_0_36_POS) -#define MJPEG_Q_REG_Q_0_36_UMSK (~(((1U << MJPEG_Q_REG_Q_0_36_LEN) - 1) << MJPEG_Q_REG_Q_0_36_POS)) -#define MJPEG_Q_REG_Q_0_37 MJPEG_Q_REG_Q_0_37 -#define MJPEG_Q_REG_Q_0_37_POS (16U) -#define MJPEG_Q_REG_Q_0_37_LEN (12U) -#define MJPEG_Q_REG_Q_0_37_MSK (((1U << MJPEG_Q_REG_Q_0_37_LEN) - 1) << MJPEG_Q_REG_Q_0_37_POS) -#define MJPEG_Q_REG_Q_0_37_UMSK (~(((1U << MJPEG_Q_REG_Q_0_37_LEN) - 1) << MJPEG_Q_REG_Q_0_37_POS)) - -/* 0x470 : mjpeg_q_param_38 */ -#define MJPEG_Q_PARAM_38_OFFSET (0x470) -#define MJPEG_Q_REG_Q_0_38 MJPEG_Q_REG_Q_0_38 -#define MJPEG_Q_REG_Q_0_38_POS (0U) -#define MJPEG_Q_REG_Q_0_38_LEN (12U) -#define MJPEG_Q_REG_Q_0_38_MSK (((1U << MJPEG_Q_REG_Q_0_38_LEN) - 1) << MJPEG_Q_REG_Q_0_38_POS) -#define MJPEG_Q_REG_Q_0_38_UMSK (~(((1U << MJPEG_Q_REG_Q_0_38_LEN) - 1) << MJPEG_Q_REG_Q_0_38_POS)) -#define MJPEG_Q_REG_Q_0_39 MJPEG_Q_REG_Q_0_39 -#define MJPEG_Q_REG_Q_0_39_POS (16U) -#define MJPEG_Q_REG_Q_0_39_LEN (12U) -#define MJPEG_Q_REG_Q_0_39_MSK (((1U << MJPEG_Q_REG_Q_0_39_LEN) - 1) << MJPEG_Q_REG_Q_0_39_POS) -#define MJPEG_Q_REG_Q_0_39_UMSK (~(((1U << MJPEG_Q_REG_Q_0_39_LEN) - 1) << MJPEG_Q_REG_Q_0_39_POS)) - -/* 0x474 : mjpeg_q_param_3a */ -#define MJPEG_Q_PARAM_3A_OFFSET (0x474) -#define MJPEG_Q_REG_Q_0_3A MJPEG_Q_REG_Q_0_3A -#define MJPEG_Q_REG_Q_0_3A_POS (0U) -#define MJPEG_Q_REG_Q_0_3A_LEN (12U) -#define MJPEG_Q_REG_Q_0_3A_MSK (((1U << MJPEG_Q_REG_Q_0_3A_LEN) - 1) << MJPEG_Q_REG_Q_0_3A_POS) -#define MJPEG_Q_REG_Q_0_3A_UMSK (~(((1U << MJPEG_Q_REG_Q_0_3A_LEN) - 1) << MJPEG_Q_REG_Q_0_3A_POS)) -#define MJPEG_Q_REG_Q_0_3B MJPEG_Q_REG_Q_0_3B -#define MJPEG_Q_REG_Q_0_3B_POS (16U) -#define MJPEG_Q_REG_Q_0_3B_LEN (12U) -#define MJPEG_Q_REG_Q_0_3B_MSK (((1U << MJPEG_Q_REG_Q_0_3B_LEN) - 1) << MJPEG_Q_REG_Q_0_3B_POS) -#define MJPEG_Q_REG_Q_0_3B_UMSK (~(((1U << MJPEG_Q_REG_Q_0_3B_LEN) - 1) << MJPEG_Q_REG_Q_0_3B_POS)) - -/* 0x478 : mjpeg_q_param_3c */ -#define MJPEG_Q_PARAM_3C_OFFSET (0x478) -#define MJPEG_Q_REG_Q_0_3C MJPEG_Q_REG_Q_0_3C -#define MJPEG_Q_REG_Q_0_3C_POS (0U) -#define MJPEG_Q_REG_Q_0_3C_LEN (12U) -#define MJPEG_Q_REG_Q_0_3C_MSK (((1U << MJPEG_Q_REG_Q_0_3C_LEN) - 1) << MJPEG_Q_REG_Q_0_3C_POS) -#define MJPEG_Q_REG_Q_0_3C_UMSK (~(((1U << MJPEG_Q_REG_Q_0_3C_LEN) - 1) << MJPEG_Q_REG_Q_0_3C_POS)) -#define MJPEG_Q_REG_Q_0_3D MJPEG_Q_REG_Q_0_3D -#define MJPEG_Q_REG_Q_0_3D_POS (16U) -#define MJPEG_Q_REG_Q_0_3D_LEN (12U) -#define MJPEG_Q_REG_Q_0_3D_MSK (((1U << MJPEG_Q_REG_Q_0_3D_LEN) - 1) << MJPEG_Q_REG_Q_0_3D_POS) -#define MJPEG_Q_REG_Q_0_3D_UMSK (~(((1U << MJPEG_Q_REG_Q_0_3D_LEN) - 1) << MJPEG_Q_REG_Q_0_3D_POS)) - -/* 0x47C : mjpeg_q_param_3e */ -#define MJPEG_Q_PARAM_3E_OFFSET (0x47C) -#define MJPEG_Q_REG_Q_0_3E MJPEG_Q_REG_Q_0_3E -#define MJPEG_Q_REG_Q_0_3E_POS (0U) -#define MJPEG_Q_REG_Q_0_3E_LEN (12U) -#define MJPEG_Q_REG_Q_0_3E_MSK (((1U << MJPEG_Q_REG_Q_0_3E_LEN) - 1) << MJPEG_Q_REG_Q_0_3E_POS) -#define MJPEG_Q_REG_Q_0_3E_UMSK (~(((1U << MJPEG_Q_REG_Q_0_3E_LEN) - 1) << MJPEG_Q_REG_Q_0_3E_POS)) -#define MJPEG_Q_REG_Q_0_3F MJPEG_Q_REG_Q_0_3F -#define MJPEG_Q_REG_Q_0_3F_POS (16U) -#define MJPEG_Q_REG_Q_0_3F_LEN (12U) -#define MJPEG_Q_REG_Q_0_3F_MSK (((1U << MJPEG_Q_REG_Q_0_3F_LEN) - 1) << MJPEG_Q_REG_Q_0_3F_POS) -#define MJPEG_Q_REG_Q_0_3F_UMSK (~(((1U << MJPEG_Q_REG_Q_0_3F_LEN) - 1) << MJPEG_Q_REG_Q_0_3F_POS)) - -/* 0x480 : mjpeg_q_param_40 */ -#define MJPEG_Q_PARAM_40_OFFSET (0x480) -#define MJPEG_Q_REG_Q_1_00 MJPEG_Q_REG_Q_1_00 -#define MJPEG_Q_REG_Q_1_00_POS (0U) -#define MJPEG_Q_REG_Q_1_00_LEN (12U) -#define MJPEG_Q_REG_Q_1_00_MSK (((1U << MJPEG_Q_REG_Q_1_00_LEN) - 1) << MJPEG_Q_REG_Q_1_00_POS) -#define MJPEG_Q_REG_Q_1_00_UMSK (~(((1U << MJPEG_Q_REG_Q_1_00_LEN) - 1) << MJPEG_Q_REG_Q_1_00_POS)) -#define MJPEG_Q_REG_Q_1_01 MJPEG_Q_REG_Q_1_01 -#define MJPEG_Q_REG_Q_1_01_POS (16U) -#define MJPEG_Q_REG_Q_1_01_LEN (12U) -#define MJPEG_Q_REG_Q_1_01_MSK (((1U << MJPEG_Q_REG_Q_1_01_LEN) - 1) << MJPEG_Q_REG_Q_1_01_POS) -#define MJPEG_Q_REG_Q_1_01_UMSK (~(((1U << MJPEG_Q_REG_Q_1_01_LEN) - 1) << MJPEG_Q_REG_Q_1_01_POS)) - -/* 0x484 : mjpeg_q_param_42 */ -#define MJPEG_Q_PARAM_42_OFFSET (0x484) -#define MJPEG_Q_REG_Q_1_02 MJPEG_Q_REG_Q_1_02 -#define MJPEG_Q_REG_Q_1_02_POS (0U) -#define MJPEG_Q_REG_Q_1_02_LEN (12U) -#define MJPEG_Q_REG_Q_1_02_MSK (((1U << MJPEG_Q_REG_Q_1_02_LEN) - 1) << MJPEG_Q_REG_Q_1_02_POS) -#define MJPEG_Q_REG_Q_1_02_UMSK (~(((1U << MJPEG_Q_REG_Q_1_02_LEN) - 1) << MJPEG_Q_REG_Q_1_02_POS)) -#define MJPEG_Q_REG_Q_1_03 MJPEG_Q_REG_Q_1_03 -#define MJPEG_Q_REG_Q_1_03_POS (16U) -#define MJPEG_Q_REG_Q_1_03_LEN (12U) -#define MJPEG_Q_REG_Q_1_03_MSK (((1U << MJPEG_Q_REG_Q_1_03_LEN) - 1) << MJPEG_Q_REG_Q_1_03_POS) -#define MJPEG_Q_REG_Q_1_03_UMSK (~(((1U << MJPEG_Q_REG_Q_1_03_LEN) - 1) << MJPEG_Q_REG_Q_1_03_POS)) - -/* 0x488 : mjpeg_q_param_44 */ -#define MJPEG_Q_PARAM_44_OFFSET (0x488) -#define MJPEG_Q_REG_Q_1_04 MJPEG_Q_REG_Q_1_04 -#define MJPEG_Q_REG_Q_1_04_POS (0U) -#define MJPEG_Q_REG_Q_1_04_LEN (12U) -#define MJPEG_Q_REG_Q_1_04_MSK (((1U << MJPEG_Q_REG_Q_1_04_LEN) - 1) << MJPEG_Q_REG_Q_1_04_POS) -#define MJPEG_Q_REG_Q_1_04_UMSK (~(((1U << MJPEG_Q_REG_Q_1_04_LEN) - 1) << MJPEG_Q_REG_Q_1_04_POS)) -#define MJPEG_Q_REG_Q_1_05 MJPEG_Q_REG_Q_1_05 -#define MJPEG_Q_REG_Q_1_05_POS (16U) -#define MJPEG_Q_REG_Q_1_05_LEN (12U) -#define MJPEG_Q_REG_Q_1_05_MSK (((1U << MJPEG_Q_REG_Q_1_05_LEN) - 1) << MJPEG_Q_REG_Q_1_05_POS) -#define MJPEG_Q_REG_Q_1_05_UMSK (~(((1U << MJPEG_Q_REG_Q_1_05_LEN) - 1) << MJPEG_Q_REG_Q_1_05_POS)) - -/* 0x48C : mjpeg_q_param_46 */ -#define MJPEG_Q_PARAM_46_OFFSET (0x48C) -#define MJPEG_Q_REG_Q_1_06 MJPEG_Q_REG_Q_1_06 -#define MJPEG_Q_REG_Q_1_06_POS (0U) -#define MJPEG_Q_REG_Q_1_06_LEN (12U) -#define MJPEG_Q_REG_Q_1_06_MSK (((1U << MJPEG_Q_REG_Q_1_06_LEN) - 1) << MJPEG_Q_REG_Q_1_06_POS) -#define MJPEG_Q_REG_Q_1_06_UMSK (~(((1U << MJPEG_Q_REG_Q_1_06_LEN) - 1) << MJPEG_Q_REG_Q_1_06_POS)) -#define MJPEG_Q_REG_Q_1_07 MJPEG_Q_REG_Q_1_07 -#define MJPEG_Q_REG_Q_1_07_POS (16U) -#define MJPEG_Q_REG_Q_1_07_LEN (12U) -#define MJPEG_Q_REG_Q_1_07_MSK (((1U << MJPEG_Q_REG_Q_1_07_LEN) - 1) << MJPEG_Q_REG_Q_1_07_POS) -#define MJPEG_Q_REG_Q_1_07_UMSK (~(((1U << MJPEG_Q_REG_Q_1_07_LEN) - 1) << MJPEG_Q_REG_Q_1_07_POS)) - -/* 0x490 : mjpeg_q_param_48 */ -#define MJPEG_Q_PARAM_48_OFFSET (0x490) -#define MJPEG_Q_REG_Q_1_08 MJPEG_Q_REG_Q_1_08 -#define MJPEG_Q_REG_Q_1_08_POS (0U) -#define MJPEG_Q_REG_Q_1_08_LEN (12U) -#define MJPEG_Q_REG_Q_1_08_MSK (((1U << MJPEG_Q_REG_Q_1_08_LEN) - 1) << MJPEG_Q_REG_Q_1_08_POS) -#define MJPEG_Q_REG_Q_1_08_UMSK (~(((1U << MJPEG_Q_REG_Q_1_08_LEN) - 1) << MJPEG_Q_REG_Q_1_08_POS)) -#define MJPEG_Q_REG_Q_1_09 MJPEG_Q_REG_Q_1_09 -#define MJPEG_Q_REG_Q_1_09_POS (16U) -#define MJPEG_Q_REG_Q_1_09_LEN (12U) -#define MJPEG_Q_REG_Q_1_09_MSK (((1U << MJPEG_Q_REG_Q_1_09_LEN) - 1) << MJPEG_Q_REG_Q_1_09_POS) -#define MJPEG_Q_REG_Q_1_09_UMSK (~(((1U << MJPEG_Q_REG_Q_1_09_LEN) - 1) << MJPEG_Q_REG_Q_1_09_POS)) - -/* 0x494 : mjpeg_q_param_4a */ -#define MJPEG_Q_PARAM_4A_OFFSET (0x494) -#define MJPEG_Q_REG_Q_1_0A MJPEG_Q_REG_Q_1_0A -#define MJPEG_Q_REG_Q_1_0A_POS (0U) -#define MJPEG_Q_REG_Q_1_0A_LEN (12U) -#define MJPEG_Q_REG_Q_1_0A_MSK (((1U << MJPEG_Q_REG_Q_1_0A_LEN) - 1) << MJPEG_Q_REG_Q_1_0A_POS) -#define MJPEG_Q_REG_Q_1_0A_UMSK (~(((1U << MJPEG_Q_REG_Q_1_0A_LEN) - 1) << MJPEG_Q_REG_Q_1_0A_POS)) -#define MJPEG_Q_REG_Q_1_0B MJPEG_Q_REG_Q_1_0B -#define MJPEG_Q_REG_Q_1_0B_POS (16U) -#define MJPEG_Q_REG_Q_1_0B_LEN (12U) -#define MJPEG_Q_REG_Q_1_0B_MSK (((1U << MJPEG_Q_REG_Q_1_0B_LEN) - 1) << MJPEG_Q_REG_Q_1_0B_POS) -#define MJPEG_Q_REG_Q_1_0B_UMSK (~(((1U << MJPEG_Q_REG_Q_1_0B_LEN) - 1) << MJPEG_Q_REG_Q_1_0B_POS)) - -/* 0x498 : mjpeg_q_param_4c */ -#define MJPEG_Q_PARAM_4C_OFFSET (0x498) -#define MJPEG_Q_REG_Q_1_0C MJPEG_Q_REG_Q_1_0C -#define MJPEG_Q_REG_Q_1_0C_POS (0U) -#define MJPEG_Q_REG_Q_1_0C_LEN (12U) -#define MJPEG_Q_REG_Q_1_0C_MSK (((1U << MJPEG_Q_REG_Q_1_0C_LEN) - 1) << MJPEG_Q_REG_Q_1_0C_POS) -#define MJPEG_Q_REG_Q_1_0C_UMSK (~(((1U << MJPEG_Q_REG_Q_1_0C_LEN) - 1) << MJPEG_Q_REG_Q_1_0C_POS)) -#define MJPEG_Q_REG_Q_1_0D MJPEG_Q_REG_Q_1_0D -#define MJPEG_Q_REG_Q_1_0D_POS (16U) -#define MJPEG_Q_REG_Q_1_0D_LEN (12U) -#define MJPEG_Q_REG_Q_1_0D_MSK (((1U << MJPEG_Q_REG_Q_1_0D_LEN) - 1) << MJPEG_Q_REG_Q_1_0D_POS) -#define MJPEG_Q_REG_Q_1_0D_UMSK (~(((1U << MJPEG_Q_REG_Q_1_0D_LEN) - 1) << MJPEG_Q_REG_Q_1_0D_POS)) - -/* 0x49C : mjpeg_q_param_4e */ -#define MJPEG_Q_PARAM_4E_OFFSET (0x49C) -#define MJPEG_Q_REG_Q_1_0E MJPEG_Q_REG_Q_1_0E -#define MJPEG_Q_REG_Q_1_0E_POS (0U) -#define MJPEG_Q_REG_Q_1_0E_LEN (12U) -#define MJPEG_Q_REG_Q_1_0E_MSK (((1U << MJPEG_Q_REG_Q_1_0E_LEN) - 1) << MJPEG_Q_REG_Q_1_0E_POS) -#define MJPEG_Q_REG_Q_1_0E_UMSK (~(((1U << MJPEG_Q_REG_Q_1_0E_LEN) - 1) << MJPEG_Q_REG_Q_1_0E_POS)) -#define MJPEG_Q_REG_Q_1_0F MJPEG_Q_REG_Q_1_0F -#define MJPEG_Q_REG_Q_1_0F_POS (16U) -#define MJPEG_Q_REG_Q_1_0F_LEN (12U) -#define MJPEG_Q_REG_Q_1_0F_MSK (((1U << MJPEG_Q_REG_Q_1_0F_LEN) - 1) << MJPEG_Q_REG_Q_1_0F_POS) -#define MJPEG_Q_REG_Q_1_0F_UMSK (~(((1U << MJPEG_Q_REG_Q_1_0F_LEN) - 1) << MJPEG_Q_REG_Q_1_0F_POS)) - -/* 0x4A0 : mjpeg_q_param_50 */ -#define MJPEG_Q_PARAM_50_OFFSET (0x4A0) -#define MJPEG_Q_REG_Q_1_10 MJPEG_Q_REG_Q_1_10 -#define MJPEG_Q_REG_Q_1_10_POS (0U) -#define MJPEG_Q_REG_Q_1_10_LEN (12U) -#define MJPEG_Q_REG_Q_1_10_MSK (((1U << MJPEG_Q_REG_Q_1_10_LEN) - 1) << MJPEG_Q_REG_Q_1_10_POS) -#define MJPEG_Q_REG_Q_1_10_UMSK (~(((1U << MJPEG_Q_REG_Q_1_10_LEN) - 1) << MJPEG_Q_REG_Q_1_10_POS)) -#define MJPEG_Q_REG_Q_1_11 MJPEG_Q_REG_Q_1_11 -#define MJPEG_Q_REG_Q_1_11_POS (16U) -#define MJPEG_Q_REG_Q_1_11_LEN (12U) -#define MJPEG_Q_REG_Q_1_11_MSK (((1U << MJPEG_Q_REG_Q_1_11_LEN) - 1) << MJPEG_Q_REG_Q_1_11_POS) -#define MJPEG_Q_REG_Q_1_11_UMSK (~(((1U << MJPEG_Q_REG_Q_1_11_LEN) - 1) << MJPEG_Q_REG_Q_1_11_POS)) - -/* 0x4A4 : mjpeg_q_param_52 */ -#define MJPEG_Q_PARAM_52_OFFSET (0x4A4) -#define MJPEG_Q_REG_Q_1_12 MJPEG_Q_REG_Q_1_12 -#define MJPEG_Q_REG_Q_1_12_POS (0U) -#define MJPEG_Q_REG_Q_1_12_LEN (12U) -#define MJPEG_Q_REG_Q_1_12_MSK (((1U << MJPEG_Q_REG_Q_1_12_LEN) - 1) << MJPEG_Q_REG_Q_1_12_POS) -#define MJPEG_Q_REG_Q_1_12_UMSK (~(((1U << MJPEG_Q_REG_Q_1_12_LEN) - 1) << MJPEG_Q_REG_Q_1_12_POS)) -#define MJPEG_Q_REG_Q_1_13 MJPEG_Q_REG_Q_1_13 -#define MJPEG_Q_REG_Q_1_13_POS (16U) -#define MJPEG_Q_REG_Q_1_13_LEN (12U) -#define MJPEG_Q_REG_Q_1_13_MSK (((1U << MJPEG_Q_REG_Q_1_13_LEN) - 1) << MJPEG_Q_REG_Q_1_13_POS) -#define MJPEG_Q_REG_Q_1_13_UMSK (~(((1U << MJPEG_Q_REG_Q_1_13_LEN) - 1) << MJPEG_Q_REG_Q_1_13_POS)) - -/* 0x4A8 : mjpeg_q_param_54 */ -#define MJPEG_Q_PARAM_54_OFFSET (0x4A8) -#define MJPEG_Q_REG_Q_1_14 MJPEG_Q_REG_Q_1_14 -#define MJPEG_Q_REG_Q_1_14_POS (0U) -#define MJPEG_Q_REG_Q_1_14_LEN (12U) -#define MJPEG_Q_REG_Q_1_14_MSK (((1U << MJPEG_Q_REG_Q_1_14_LEN) - 1) << MJPEG_Q_REG_Q_1_14_POS) -#define MJPEG_Q_REG_Q_1_14_UMSK (~(((1U << MJPEG_Q_REG_Q_1_14_LEN) - 1) << MJPEG_Q_REG_Q_1_14_POS)) -#define MJPEG_Q_REG_Q_1_15 MJPEG_Q_REG_Q_1_15 -#define MJPEG_Q_REG_Q_1_15_POS (16U) -#define MJPEG_Q_REG_Q_1_15_LEN (12U) -#define MJPEG_Q_REG_Q_1_15_MSK (((1U << MJPEG_Q_REG_Q_1_15_LEN) - 1) << MJPEG_Q_REG_Q_1_15_POS) -#define MJPEG_Q_REG_Q_1_15_UMSK (~(((1U << MJPEG_Q_REG_Q_1_15_LEN) - 1) << MJPEG_Q_REG_Q_1_15_POS)) - -/* 0x4AC : mjpeg_q_param_56 */ -#define MJPEG_Q_PARAM_56_OFFSET (0x4AC) -#define MJPEG_Q_REG_Q_1_16 MJPEG_Q_REG_Q_1_16 -#define MJPEG_Q_REG_Q_1_16_POS (0U) -#define MJPEG_Q_REG_Q_1_16_LEN (12U) -#define MJPEG_Q_REG_Q_1_16_MSK (((1U << MJPEG_Q_REG_Q_1_16_LEN) - 1) << MJPEG_Q_REG_Q_1_16_POS) -#define MJPEG_Q_REG_Q_1_16_UMSK (~(((1U << MJPEG_Q_REG_Q_1_16_LEN) - 1) << MJPEG_Q_REG_Q_1_16_POS)) -#define MJPEG_Q_REG_Q_1_17 MJPEG_Q_REG_Q_1_17 -#define MJPEG_Q_REG_Q_1_17_POS (16U) -#define MJPEG_Q_REG_Q_1_17_LEN (12U) -#define MJPEG_Q_REG_Q_1_17_MSK (((1U << MJPEG_Q_REG_Q_1_17_LEN) - 1) << MJPEG_Q_REG_Q_1_17_POS) -#define MJPEG_Q_REG_Q_1_17_UMSK (~(((1U << MJPEG_Q_REG_Q_1_17_LEN) - 1) << MJPEG_Q_REG_Q_1_17_POS)) - -/* 0x4B0 : mjpeg_q_param_58 */ -#define MJPEG_Q_PARAM_58_OFFSET (0x4B0) -#define MJPEG_Q_REG_Q_1_18 MJPEG_Q_REG_Q_1_18 -#define MJPEG_Q_REG_Q_1_18_POS (0U) -#define MJPEG_Q_REG_Q_1_18_LEN (12U) -#define MJPEG_Q_REG_Q_1_18_MSK (((1U << MJPEG_Q_REG_Q_1_18_LEN) - 1) << MJPEG_Q_REG_Q_1_18_POS) -#define MJPEG_Q_REG_Q_1_18_UMSK (~(((1U << MJPEG_Q_REG_Q_1_18_LEN) - 1) << MJPEG_Q_REG_Q_1_18_POS)) -#define MJPEG_Q_REG_Q_1_19 MJPEG_Q_REG_Q_1_19 -#define MJPEG_Q_REG_Q_1_19_POS (16U) -#define MJPEG_Q_REG_Q_1_19_LEN (12U) -#define MJPEG_Q_REG_Q_1_19_MSK (((1U << MJPEG_Q_REG_Q_1_19_LEN) - 1) << MJPEG_Q_REG_Q_1_19_POS) -#define MJPEG_Q_REG_Q_1_19_UMSK (~(((1U << MJPEG_Q_REG_Q_1_19_LEN) - 1) << MJPEG_Q_REG_Q_1_19_POS)) - -/* 0x4B4 : mjpeg_q_param_5a */ -#define MJPEG_Q_PARAM_5A_OFFSET (0x4B4) -#define MJPEG_Q_REG_Q_1_1A MJPEG_Q_REG_Q_1_1A -#define MJPEG_Q_REG_Q_1_1A_POS (0U) -#define MJPEG_Q_REG_Q_1_1A_LEN (12U) -#define MJPEG_Q_REG_Q_1_1A_MSK (((1U << MJPEG_Q_REG_Q_1_1A_LEN) - 1) << MJPEG_Q_REG_Q_1_1A_POS) -#define MJPEG_Q_REG_Q_1_1A_UMSK (~(((1U << MJPEG_Q_REG_Q_1_1A_LEN) - 1) << MJPEG_Q_REG_Q_1_1A_POS)) -#define MJPEG_Q_REG_Q_1_1B MJPEG_Q_REG_Q_1_1B -#define MJPEG_Q_REG_Q_1_1B_POS (16U) -#define MJPEG_Q_REG_Q_1_1B_LEN (12U) -#define MJPEG_Q_REG_Q_1_1B_MSK (((1U << MJPEG_Q_REG_Q_1_1B_LEN) - 1) << MJPEG_Q_REG_Q_1_1B_POS) -#define MJPEG_Q_REG_Q_1_1B_UMSK (~(((1U << MJPEG_Q_REG_Q_1_1B_LEN) - 1) << MJPEG_Q_REG_Q_1_1B_POS)) - -/* 0x4B8 : mjpeg_q_param_5c */ -#define MJPEG_Q_PARAM_5C_OFFSET (0x4B8) -#define MJPEG_Q_REG_Q_1_1C MJPEG_Q_REG_Q_1_1C -#define MJPEG_Q_REG_Q_1_1C_POS (0U) -#define MJPEG_Q_REG_Q_1_1C_LEN (12U) -#define MJPEG_Q_REG_Q_1_1C_MSK (((1U << MJPEG_Q_REG_Q_1_1C_LEN) - 1) << MJPEG_Q_REG_Q_1_1C_POS) -#define MJPEG_Q_REG_Q_1_1C_UMSK (~(((1U << MJPEG_Q_REG_Q_1_1C_LEN) - 1) << MJPEG_Q_REG_Q_1_1C_POS)) -#define MJPEG_Q_REG_Q_1_1D MJPEG_Q_REG_Q_1_1D -#define MJPEG_Q_REG_Q_1_1D_POS (16U) -#define MJPEG_Q_REG_Q_1_1D_LEN (12U) -#define MJPEG_Q_REG_Q_1_1D_MSK (((1U << MJPEG_Q_REG_Q_1_1D_LEN) - 1) << MJPEG_Q_REG_Q_1_1D_POS) -#define MJPEG_Q_REG_Q_1_1D_UMSK (~(((1U << MJPEG_Q_REG_Q_1_1D_LEN) - 1) << MJPEG_Q_REG_Q_1_1D_POS)) - -/* 0x4BC : mjpeg_q_param_5e */ -#define MJPEG_Q_PARAM_5E_OFFSET (0x4BC) -#define MJPEG_Q_REG_Q_1_1E MJPEG_Q_REG_Q_1_1E -#define MJPEG_Q_REG_Q_1_1E_POS (0U) -#define MJPEG_Q_REG_Q_1_1E_LEN (12U) -#define MJPEG_Q_REG_Q_1_1E_MSK (((1U << MJPEG_Q_REG_Q_1_1E_LEN) - 1) << MJPEG_Q_REG_Q_1_1E_POS) -#define MJPEG_Q_REG_Q_1_1E_UMSK (~(((1U << MJPEG_Q_REG_Q_1_1E_LEN) - 1) << MJPEG_Q_REG_Q_1_1E_POS)) -#define MJPEG_Q_REG_Q_1_1F MJPEG_Q_REG_Q_1_1F -#define MJPEG_Q_REG_Q_1_1F_POS (16U) -#define MJPEG_Q_REG_Q_1_1F_LEN (12U) -#define MJPEG_Q_REG_Q_1_1F_MSK (((1U << MJPEG_Q_REG_Q_1_1F_LEN) - 1) << MJPEG_Q_REG_Q_1_1F_POS) -#define MJPEG_Q_REG_Q_1_1F_UMSK (~(((1U << MJPEG_Q_REG_Q_1_1F_LEN) - 1) << MJPEG_Q_REG_Q_1_1F_POS)) - -/* 0x4C0 : mjpeg_q_param_60 */ -#define MJPEG_Q_PARAM_60_OFFSET (0x4C0) -#define MJPEG_Q_REG_Q_1_20 MJPEG_Q_REG_Q_1_20 -#define MJPEG_Q_REG_Q_1_20_POS (0U) -#define MJPEG_Q_REG_Q_1_20_LEN (12U) -#define MJPEG_Q_REG_Q_1_20_MSK (((1U << MJPEG_Q_REG_Q_1_20_LEN) - 1) << MJPEG_Q_REG_Q_1_20_POS) -#define MJPEG_Q_REG_Q_1_20_UMSK (~(((1U << MJPEG_Q_REG_Q_1_20_LEN) - 1) << MJPEG_Q_REG_Q_1_20_POS)) -#define MJPEG_Q_REG_Q_1_21 MJPEG_Q_REG_Q_1_21 -#define MJPEG_Q_REG_Q_1_21_POS (16U) -#define MJPEG_Q_REG_Q_1_21_LEN (12U) -#define MJPEG_Q_REG_Q_1_21_MSK (((1U << MJPEG_Q_REG_Q_1_21_LEN) - 1) << MJPEG_Q_REG_Q_1_21_POS) -#define MJPEG_Q_REG_Q_1_21_UMSK (~(((1U << MJPEG_Q_REG_Q_1_21_LEN) - 1) << MJPEG_Q_REG_Q_1_21_POS)) - -/* 0x4C4 : mjpeg_q_param_62 */ -#define MJPEG_Q_PARAM_62_OFFSET (0x4C4) -#define MJPEG_Q_REG_Q_1_22 MJPEG_Q_REG_Q_1_22 -#define MJPEG_Q_REG_Q_1_22_POS (0U) -#define MJPEG_Q_REG_Q_1_22_LEN (12U) -#define MJPEG_Q_REG_Q_1_22_MSK (((1U << MJPEG_Q_REG_Q_1_22_LEN) - 1) << MJPEG_Q_REG_Q_1_22_POS) -#define MJPEG_Q_REG_Q_1_22_UMSK (~(((1U << MJPEG_Q_REG_Q_1_22_LEN) - 1) << MJPEG_Q_REG_Q_1_22_POS)) -#define MJPEG_Q_REG_Q_1_23 MJPEG_Q_REG_Q_1_23 -#define MJPEG_Q_REG_Q_1_23_POS (16U) -#define MJPEG_Q_REG_Q_1_23_LEN (12U) -#define MJPEG_Q_REG_Q_1_23_MSK (((1U << MJPEG_Q_REG_Q_1_23_LEN) - 1) << MJPEG_Q_REG_Q_1_23_POS) -#define MJPEG_Q_REG_Q_1_23_UMSK (~(((1U << MJPEG_Q_REG_Q_1_23_LEN) - 1) << MJPEG_Q_REG_Q_1_23_POS)) - -/* 0x4C8 : mjpeg_q_param_64 */ -#define MJPEG_Q_PARAM_64_OFFSET (0x4C8) -#define MJPEG_Q_REG_Q_1_24 MJPEG_Q_REG_Q_1_24 -#define MJPEG_Q_REG_Q_1_24_POS (0U) -#define MJPEG_Q_REG_Q_1_24_LEN (12U) -#define MJPEG_Q_REG_Q_1_24_MSK (((1U << MJPEG_Q_REG_Q_1_24_LEN) - 1) << MJPEG_Q_REG_Q_1_24_POS) -#define MJPEG_Q_REG_Q_1_24_UMSK (~(((1U << MJPEG_Q_REG_Q_1_24_LEN) - 1) << MJPEG_Q_REG_Q_1_24_POS)) -#define MJPEG_Q_REG_Q_1_25 MJPEG_Q_REG_Q_1_25 -#define MJPEG_Q_REG_Q_1_25_POS (16U) -#define MJPEG_Q_REG_Q_1_25_LEN (12U) -#define MJPEG_Q_REG_Q_1_25_MSK (((1U << MJPEG_Q_REG_Q_1_25_LEN) - 1) << MJPEG_Q_REG_Q_1_25_POS) -#define MJPEG_Q_REG_Q_1_25_UMSK (~(((1U << MJPEG_Q_REG_Q_1_25_LEN) - 1) << MJPEG_Q_REG_Q_1_25_POS)) - -/* 0x4CC : mjpeg_q_param_66 */ -#define MJPEG_Q_PARAM_66_OFFSET (0x4CC) -#define MJPEG_Q_REG_Q_1_26 MJPEG_Q_REG_Q_1_26 -#define MJPEG_Q_REG_Q_1_26_POS (0U) -#define MJPEG_Q_REG_Q_1_26_LEN (12U) -#define MJPEG_Q_REG_Q_1_26_MSK (((1U << MJPEG_Q_REG_Q_1_26_LEN) - 1) << MJPEG_Q_REG_Q_1_26_POS) -#define MJPEG_Q_REG_Q_1_26_UMSK (~(((1U << MJPEG_Q_REG_Q_1_26_LEN) - 1) << MJPEG_Q_REG_Q_1_26_POS)) -#define MJPEG_Q_REG_Q_1_27 MJPEG_Q_REG_Q_1_27 -#define MJPEG_Q_REG_Q_1_27_POS (16U) -#define MJPEG_Q_REG_Q_1_27_LEN (12U) -#define MJPEG_Q_REG_Q_1_27_MSK (((1U << MJPEG_Q_REG_Q_1_27_LEN) - 1) << MJPEG_Q_REG_Q_1_27_POS) -#define MJPEG_Q_REG_Q_1_27_UMSK (~(((1U << MJPEG_Q_REG_Q_1_27_LEN) - 1) << MJPEG_Q_REG_Q_1_27_POS)) - -/* 0x4D0 : mjpeg_q_param_68 */ -#define MJPEG_Q_PARAM_68_OFFSET (0x4D0) -#define MJPEG_Q_REG_Q_1_28 MJPEG_Q_REG_Q_1_28 -#define MJPEG_Q_REG_Q_1_28_POS (0U) -#define MJPEG_Q_REG_Q_1_28_LEN (12U) -#define MJPEG_Q_REG_Q_1_28_MSK (((1U << MJPEG_Q_REG_Q_1_28_LEN) - 1) << MJPEG_Q_REG_Q_1_28_POS) -#define MJPEG_Q_REG_Q_1_28_UMSK (~(((1U << MJPEG_Q_REG_Q_1_28_LEN) - 1) << MJPEG_Q_REG_Q_1_28_POS)) -#define MJPEG_Q_REG_Q_1_29 MJPEG_Q_REG_Q_1_29 -#define MJPEG_Q_REG_Q_1_29_POS (16U) -#define MJPEG_Q_REG_Q_1_29_LEN (12U) -#define MJPEG_Q_REG_Q_1_29_MSK (((1U << MJPEG_Q_REG_Q_1_29_LEN) - 1) << MJPEG_Q_REG_Q_1_29_POS) -#define MJPEG_Q_REG_Q_1_29_UMSK (~(((1U << MJPEG_Q_REG_Q_1_29_LEN) - 1) << MJPEG_Q_REG_Q_1_29_POS)) - -/* 0x4D4 : mjpeg_q_param_6a */ -#define MJPEG_Q_PARAM_6A_OFFSET (0x4D4) -#define MJPEG_Q_REG_Q_1_2A MJPEG_Q_REG_Q_1_2A -#define MJPEG_Q_REG_Q_1_2A_POS (0U) -#define MJPEG_Q_REG_Q_1_2A_LEN (12U) -#define MJPEG_Q_REG_Q_1_2A_MSK (((1U << MJPEG_Q_REG_Q_1_2A_LEN) - 1) << MJPEG_Q_REG_Q_1_2A_POS) -#define MJPEG_Q_REG_Q_1_2A_UMSK (~(((1U << MJPEG_Q_REG_Q_1_2A_LEN) - 1) << MJPEG_Q_REG_Q_1_2A_POS)) -#define MJPEG_Q_REG_Q_1_2B MJPEG_Q_REG_Q_1_2B -#define MJPEG_Q_REG_Q_1_2B_POS (16U) -#define MJPEG_Q_REG_Q_1_2B_LEN (12U) -#define MJPEG_Q_REG_Q_1_2B_MSK (((1U << MJPEG_Q_REG_Q_1_2B_LEN) - 1) << MJPEG_Q_REG_Q_1_2B_POS) -#define MJPEG_Q_REG_Q_1_2B_UMSK (~(((1U << MJPEG_Q_REG_Q_1_2B_LEN) - 1) << MJPEG_Q_REG_Q_1_2B_POS)) - -/* 0x4D8 : mjpeg_q_param_6c */ -#define MJPEG_Q_PARAM_6C_OFFSET (0x4D8) -#define MJPEG_Q_REG_Q_1_2C MJPEG_Q_REG_Q_1_2C -#define MJPEG_Q_REG_Q_1_2C_POS (0U) -#define MJPEG_Q_REG_Q_1_2C_LEN (12U) -#define MJPEG_Q_REG_Q_1_2C_MSK (((1U << MJPEG_Q_REG_Q_1_2C_LEN) - 1) << MJPEG_Q_REG_Q_1_2C_POS) -#define MJPEG_Q_REG_Q_1_2C_UMSK (~(((1U << MJPEG_Q_REG_Q_1_2C_LEN) - 1) << MJPEG_Q_REG_Q_1_2C_POS)) -#define MJPEG_Q_REG_Q_1_2D MJPEG_Q_REG_Q_1_2D -#define MJPEG_Q_REG_Q_1_2D_POS (16U) -#define MJPEG_Q_REG_Q_1_2D_LEN (12U) -#define MJPEG_Q_REG_Q_1_2D_MSK (((1U << MJPEG_Q_REG_Q_1_2D_LEN) - 1) << MJPEG_Q_REG_Q_1_2D_POS) -#define MJPEG_Q_REG_Q_1_2D_UMSK (~(((1U << MJPEG_Q_REG_Q_1_2D_LEN) - 1) << MJPEG_Q_REG_Q_1_2D_POS)) - -/* 0x4DC : mjpeg_q_param_6e */ -#define MJPEG_Q_PARAM_6E_OFFSET (0x4DC) -#define MJPEG_Q_REG_Q_1_2E MJPEG_Q_REG_Q_1_2E -#define MJPEG_Q_REG_Q_1_2E_POS (0U) -#define MJPEG_Q_REG_Q_1_2E_LEN (12U) -#define MJPEG_Q_REG_Q_1_2E_MSK (((1U << MJPEG_Q_REG_Q_1_2E_LEN) - 1) << MJPEG_Q_REG_Q_1_2E_POS) -#define MJPEG_Q_REG_Q_1_2E_UMSK (~(((1U << MJPEG_Q_REG_Q_1_2E_LEN) - 1) << MJPEG_Q_REG_Q_1_2E_POS)) -#define MJPEG_Q_REG_Q_1_2F MJPEG_Q_REG_Q_1_2F -#define MJPEG_Q_REG_Q_1_2F_POS (16U) -#define MJPEG_Q_REG_Q_1_2F_LEN (12U) -#define MJPEG_Q_REG_Q_1_2F_MSK (((1U << MJPEG_Q_REG_Q_1_2F_LEN) - 1) << MJPEG_Q_REG_Q_1_2F_POS) -#define MJPEG_Q_REG_Q_1_2F_UMSK (~(((1U << MJPEG_Q_REG_Q_1_2F_LEN) - 1) << MJPEG_Q_REG_Q_1_2F_POS)) - -/* 0x4E0 : mjpeg_q_param_70 */ -#define MJPEG_Q_PARAM_70_OFFSET (0x4E0) -#define MJPEG_Q_REG_Q_1_30 MJPEG_Q_REG_Q_1_30 -#define MJPEG_Q_REG_Q_1_30_POS (0U) -#define MJPEG_Q_REG_Q_1_30_LEN (12U) -#define MJPEG_Q_REG_Q_1_30_MSK (((1U << MJPEG_Q_REG_Q_1_30_LEN) - 1) << MJPEG_Q_REG_Q_1_30_POS) -#define MJPEG_Q_REG_Q_1_30_UMSK (~(((1U << MJPEG_Q_REG_Q_1_30_LEN) - 1) << MJPEG_Q_REG_Q_1_30_POS)) -#define MJPEG_Q_REG_Q_1_31 MJPEG_Q_REG_Q_1_31 -#define MJPEG_Q_REG_Q_1_31_POS (16U) -#define MJPEG_Q_REG_Q_1_31_LEN (12U) -#define MJPEG_Q_REG_Q_1_31_MSK (((1U << MJPEG_Q_REG_Q_1_31_LEN) - 1) << MJPEG_Q_REG_Q_1_31_POS) -#define MJPEG_Q_REG_Q_1_31_UMSK (~(((1U << MJPEG_Q_REG_Q_1_31_LEN) - 1) << MJPEG_Q_REG_Q_1_31_POS)) - -/* 0x4E4 : mjpeg_q_param_72 */ -#define MJPEG_Q_PARAM_72_OFFSET (0x4E4) -#define MJPEG_Q_REG_Q_1_32 MJPEG_Q_REG_Q_1_32 -#define MJPEG_Q_REG_Q_1_32_POS (0U) -#define MJPEG_Q_REG_Q_1_32_LEN (12U) -#define MJPEG_Q_REG_Q_1_32_MSK (((1U << MJPEG_Q_REG_Q_1_32_LEN) - 1) << MJPEG_Q_REG_Q_1_32_POS) -#define MJPEG_Q_REG_Q_1_32_UMSK (~(((1U << MJPEG_Q_REG_Q_1_32_LEN) - 1) << MJPEG_Q_REG_Q_1_32_POS)) -#define MJPEG_Q_REG_Q_1_33 MJPEG_Q_REG_Q_1_33 -#define MJPEG_Q_REG_Q_1_33_POS (16U) -#define MJPEG_Q_REG_Q_1_33_LEN (12U) -#define MJPEG_Q_REG_Q_1_33_MSK (((1U << MJPEG_Q_REG_Q_1_33_LEN) - 1) << MJPEG_Q_REG_Q_1_33_POS) -#define MJPEG_Q_REG_Q_1_33_UMSK (~(((1U << MJPEG_Q_REG_Q_1_33_LEN) - 1) << MJPEG_Q_REG_Q_1_33_POS)) - -/* 0x4E8 : mjpeg_q_param_74 */ -#define MJPEG_Q_PARAM_74_OFFSET (0x4E8) -#define MJPEG_Q_REG_Q_1_34 MJPEG_Q_REG_Q_1_34 -#define MJPEG_Q_REG_Q_1_34_POS (0U) -#define MJPEG_Q_REG_Q_1_34_LEN (12U) -#define MJPEG_Q_REG_Q_1_34_MSK (((1U << MJPEG_Q_REG_Q_1_34_LEN) - 1) << MJPEG_Q_REG_Q_1_34_POS) -#define MJPEG_Q_REG_Q_1_34_UMSK (~(((1U << MJPEG_Q_REG_Q_1_34_LEN) - 1) << MJPEG_Q_REG_Q_1_34_POS)) -#define MJPEG_Q_REG_Q_1_35 MJPEG_Q_REG_Q_1_35 -#define MJPEG_Q_REG_Q_1_35_POS (16U) -#define MJPEG_Q_REG_Q_1_35_LEN (12U) -#define MJPEG_Q_REG_Q_1_35_MSK (((1U << MJPEG_Q_REG_Q_1_35_LEN) - 1) << MJPEG_Q_REG_Q_1_35_POS) -#define MJPEG_Q_REG_Q_1_35_UMSK (~(((1U << MJPEG_Q_REG_Q_1_35_LEN) - 1) << MJPEG_Q_REG_Q_1_35_POS)) - -/* 0x4EC : mjpeg_q_param_76 */ -#define MJPEG_Q_PARAM_76_OFFSET (0x4EC) -#define MJPEG_Q_REG_Q_1_36 MJPEG_Q_REG_Q_1_36 -#define MJPEG_Q_REG_Q_1_36_POS (0U) -#define MJPEG_Q_REG_Q_1_36_LEN (12U) -#define MJPEG_Q_REG_Q_1_36_MSK (((1U << MJPEG_Q_REG_Q_1_36_LEN) - 1) << MJPEG_Q_REG_Q_1_36_POS) -#define MJPEG_Q_REG_Q_1_36_UMSK (~(((1U << MJPEG_Q_REG_Q_1_36_LEN) - 1) << MJPEG_Q_REG_Q_1_36_POS)) -#define MJPEG_Q_REG_Q_1_37 MJPEG_Q_REG_Q_1_37 -#define MJPEG_Q_REG_Q_1_37_POS (16U) -#define MJPEG_Q_REG_Q_1_37_LEN (12U) -#define MJPEG_Q_REG_Q_1_37_MSK (((1U << MJPEG_Q_REG_Q_1_37_LEN) - 1) << MJPEG_Q_REG_Q_1_37_POS) -#define MJPEG_Q_REG_Q_1_37_UMSK (~(((1U << MJPEG_Q_REG_Q_1_37_LEN) - 1) << MJPEG_Q_REG_Q_1_37_POS)) - -/* 0x4F0 : mjpeg_q_param_78 */ -#define MJPEG_Q_PARAM_78_OFFSET (0x4F0) -#define MJPEG_Q_REG_Q_1_38 MJPEG_Q_REG_Q_1_38 -#define MJPEG_Q_REG_Q_1_38_POS (0U) -#define MJPEG_Q_REG_Q_1_38_LEN (12U) -#define MJPEG_Q_REG_Q_1_38_MSK (((1U << MJPEG_Q_REG_Q_1_38_LEN) - 1) << MJPEG_Q_REG_Q_1_38_POS) -#define MJPEG_Q_REG_Q_1_38_UMSK (~(((1U << MJPEG_Q_REG_Q_1_38_LEN) - 1) << MJPEG_Q_REG_Q_1_38_POS)) -#define MJPEG_Q_REG_Q_1_39 MJPEG_Q_REG_Q_1_39 -#define MJPEG_Q_REG_Q_1_39_POS (16U) -#define MJPEG_Q_REG_Q_1_39_LEN (12U) -#define MJPEG_Q_REG_Q_1_39_MSK (((1U << MJPEG_Q_REG_Q_1_39_LEN) - 1) << MJPEG_Q_REG_Q_1_39_POS) -#define MJPEG_Q_REG_Q_1_39_UMSK (~(((1U << MJPEG_Q_REG_Q_1_39_LEN) - 1) << MJPEG_Q_REG_Q_1_39_POS)) - -/* 0x4F4 : mjpeg_q_param_7a */ -#define MJPEG_Q_PARAM_7A_OFFSET (0x4F4) -#define MJPEG_Q_REG_Q_1_3A MJPEG_Q_REG_Q_1_3A -#define MJPEG_Q_REG_Q_1_3A_POS (0U) -#define MJPEG_Q_REG_Q_1_3A_LEN (12U) -#define MJPEG_Q_REG_Q_1_3A_MSK (((1U << MJPEG_Q_REG_Q_1_3A_LEN) - 1) << MJPEG_Q_REG_Q_1_3A_POS) -#define MJPEG_Q_REG_Q_1_3A_UMSK (~(((1U << MJPEG_Q_REG_Q_1_3A_LEN) - 1) << MJPEG_Q_REG_Q_1_3A_POS)) -#define MJPEG_Q_REG_Q_1_3B MJPEG_Q_REG_Q_1_3B -#define MJPEG_Q_REG_Q_1_3B_POS (16U) -#define MJPEG_Q_REG_Q_1_3B_LEN (12U) -#define MJPEG_Q_REG_Q_1_3B_MSK (((1U << MJPEG_Q_REG_Q_1_3B_LEN) - 1) << MJPEG_Q_REG_Q_1_3B_POS) -#define MJPEG_Q_REG_Q_1_3B_UMSK (~(((1U << MJPEG_Q_REG_Q_1_3B_LEN) - 1) << MJPEG_Q_REG_Q_1_3B_POS)) - -/* 0x4F8 : mjpeg_q_param_7c */ -#define MJPEG_Q_PARAM_7C_OFFSET (0x4F8) -#define MJPEG_Q_REG_Q_1_3C MJPEG_Q_REG_Q_1_3C -#define MJPEG_Q_REG_Q_1_3C_POS (0U) -#define MJPEG_Q_REG_Q_1_3C_LEN (12U) -#define MJPEG_Q_REG_Q_1_3C_MSK (((1U << MJPEG_Q_REG_Q_1_3C_LEN) - 1) << MJPEG_Q_REG_Q_1_3C_POS) -#define MJPEG_Q_REG_Q_1_3C_UMSK (~(((1U << MJPEG_Q_REG_Q_1_3C_LEN) - 1) << MJPEG_Q_REG_Q_1_3C_POS)) -#define MJPEG_Q_REG_Q_1_3D MJPEG_Q_REG_Q_1_3D -#define MJPEG_Q_REG_Q_1_3D_POS (16U) -#define MJPEG_Q_REG_Q_1_3D_LEN (12U) -#define MJPEG_Q_REG_Q_1_3D_MSK (((1U << MJPEG_Q_REG_Q_1_3D_LEN) - 1) << MJPEG_Q_REG_Q_1_3D_POS) -#define MJPEG_Q_REG_Q_1_3D_UMSK (~(((1U << MJPEG_Q_REG_Q_1_3D_LEN) - 1) << MJPEG_Q_REG_Q_1_3D_POS)) - -/* 0x4FC : mjpeg_q_param_7e */ -#define MJPEG_Q_PARAM_7E_OFFSET (0x4FC) -#define MJPEG_Q_REG_Q_1_3E MJPEG_Q_REG_Q_1_3E -#define MJPEG_Q_REG_Q_1_3E_POS (0U) -#define MJPEG_Q_REG_Q_1_3E_LEN (12U) -#define MJPEG_Q_REG_Q_1_3E_MSK (((1U << MJPEG_Q_REG_Q_1_3E_LEN) - 1) << MJPEG_Q_REG_Q_1_3E_POS) -#define MJPEG_Q_REG_Q_1_3E_UMSK (~(((1U << MJPEG_Q_REG_Q_1_3E_LEN) - 1) << MJPEG_Q_REG_Q_1_3E_POS)) -#define MJPEG_Q_REG_Q_1_3F MJPEG_Q_REG_Q_1_3F -#define MJPEG_Q_REG_Q_1_3F_POS (16U) -#define MJPEG_Q_REG_Q_1_3F_LEN (12U) -#define MJPEG_Q_REG_Q_1_3F_MSK (((1U << MJPEG_Q_REG_Q_1_3F_LEN) - 1) << MJPEG_Q_REG_Q_1_3F_POS) -#define MJPEG_Q_REG_Q_1_3F_UMSK (~(((1U << MJPEG_Q_REG_Q_1_3F_LEN) - 1) << MJPEG_Q_REG_Q_1_3F_POS)) - -struct mjpeg_q_reg { - /* 0x0 reserved */ - uint8_t RESERVED0x0[1024]; - - /* 0x400 : mjpeg_q_param_00 */ - union { - struct { - uint32_t reg_q_0_00 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_01 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_00; - - /* 0x404 : mjpeg_q_param_02 */ - union { - struct { - uint32_t reg_q_0_02 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_03 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_02; - - /* 0x408 : mjpeg_q_param_04 */ - union { - struct { - uint32_t reg_q_0_04 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_05 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_04; - - /* 0x40C : mjpeg_q_param_06 */ - union { - struct { - uint32_t reg_q_0_06 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_07 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_06; - - /* 0x410 : mjpeg_q_param_08 */ - union { - struct { - uint32_t reg_q_0_08 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_09 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_08; - - /* 0x414 : mjpeg_q_param_0a */ - union { - struct { - uint32_t reg_q_0_0a : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_0b : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_0a; - - /* 0x418 : mjpeg_q_param_0c */ - union { - struct { - uint32_t reg_q_0_0c : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_0d : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_0c; - - /* 0x41C : mjpeg_q_param_0e */ - union { - struct { - uint32_t reg_q_0_0e : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_0f : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_0e; - - /* 0x420 : mjpeg_q_param_10 */ - union { - struct { - uint32_t reg_q_0_10 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_11 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_10; - - /* 0x424 : mjpeg_q_param_12 */ - union { - struct { - uint32_t reg_q_0_12 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_13 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_12; - - /* 0x428 : mjpeg_q_param_14 */ - union { - struct { - uint32_t reg_q_0_14 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_15 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_14; - - /* 0x42C : mjpeg_q_param_16 */ - union { - struct { - uint32_t reg_q_0_16 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_17 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_16; - - /* 0x430 : mjpeg_q_param_18 */ - union { - struct { - uint32_t reg_q_0_18 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_19 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_18; - - /* 0x434 : mjpeg_q_param_1a */ - union { - struct { - uint32_t reg_q_0_1a : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_1b : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_1a; - - /* 0x438 : mjpeg_q_param_1c */ - union { - struct { - uint32_t reg_q_0_1c : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_1d : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_1c; - - /* 0x43C : mjpeg_q_param_1e */ - union { - struct { - uint32_t reg_q_0_1e : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_1f : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_1e; - - /* 0x440 : mjpeg_q_param_20 */ - union { - struct { - uint32_t reg_q_0_20 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_21 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_20; - - /* 0x444 : mjpeg_q_param_22 */ - union { - struct { - uint32_t reg_q_0_22 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_23 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_22; - - /* 0x448 : mjpeg_q_param_24 */ - union { - struct { - uint32_t reg_q_0_24 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_25 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_24; - - /* 0x44C : mjpeg_q_param_26 */ - union { - struct { - uint32_t reg_q_0_26 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_27 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_26; - - /* 0x450 : mjpeg_q_param_28 */ - union { - struct { - uint32_t reg_q_0_28 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_29 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_28; - - /* 0x454 : mjpeg_q_param_2a */ - union { - struct { - uint32_t reg_q_0_2a : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_2b : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_2a; - - /* 0x458 : mjpeg_q_param_2c */ - union { - struct { - uint32_t reg_q_0_2c : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_2d : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_2c; - - /* 0x45C : mjpeg_q_param_2e */ - union { - struct { - uint32_t reg_q_0_2e : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_2f : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_2e; - - /* 0x460 : mjpeg_q_param_30 */ - union { - struct { - uint32_t reg_q_0_30 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_31 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_30; - - /* 0x464 : mjpeg_q_param_32 */ - union { - struct { - uint32_t reg_q_0_32 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_33 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_32; - - /* 0x468 : mjpeg_q_param_34 */ - union { - struct { - uint32_t reg_q_0_34 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_35 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_34; - - /* 0x46C : mjpeg_q_param_36 */ - union { - struct { - uint32_t reg_q_0_36 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_37 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_36; - - /* 0x470 : mjpeg_q_param_38 */ - union { - struct { - uint32_t reg_q_0_38 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_39 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_38; - - /* 0x474 : mjpeg_q_param_3a */ - union { - struct { - uint32_t reg_q_0_3a : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_3b : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_3a; - - /* 0x478 : mjpeg_q_param_3c */ - union { - struct { - uint32_t reg_q_0_3c : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_3d : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_3c; - - /* 0x47C : mjpeg_q_param_3e */ - union { - struct { - uint32_t reg_q_0_3e : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_3f : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_3e; - - /* 0x480 : mjpeg_q_param_40 */ - union { - struct { - uint32_t reg_q_1_00 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_01 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_40; - - /* 0x484 : mjpeg_q_param_42 */ - union { - struct { - uint32_t reg_q_1_02 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_03 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_42; - - /* 0x488 : mjpeg_q_param_44 */ - union { - struct { - uint32_t reg_q_1_04 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_05 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_44; - - /* 0x48C : mjpeg_q_param_46 */ - union { - struct { - uint32_t reg_q_1_06 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_07 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_46; - - /* 0x490 : mjpeg_q_param_48 */ - union { - struct { - uint32_t reg_q_1_08 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_09 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_48; - - /* 0x494 : mjpeg_q_param_4a */ - union { - struct { - uint32_t reg_q_1_0a : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_0b : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_4a; - - /* 0x498 : mjpeg_q_param_4c */ - union { - struct { - uint32_t reg_q_1_0c : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_0d : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_4c; - - /* 0x49C : mjpeg_q_param_4e */ - union { - struct { - uint32_t reg_q_1_0e : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_0f : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_4e; - - /* 0x4A0 : mjpeg_q_param_50 */ - union { - struct { - uint32_t reg_q_1_10 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_11 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_50; - - /* 0x4A4 : mjpeg_q_param_52 */ - union { - struct { - uint32_t reg_q_1_12 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_13 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_52; - - /* 0x4A8 : mjpeg_q_param_54 */ - union { - struct { - uint32_t reg_q_1_14 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_15 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_54; - - /* 0x4AC : mjpeg_q_param_56 */ - union { - struct { - uint32_t reg_q_1_16 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_17 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_56; - - /* 0x4B0 : mjpeg_q_param_58 */ - union { - struct { - uint32_t reg_q_1_18 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_19 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_58; - - /* 0x4B4 : mjpeg_q_param_5a */ - union { - struct { - uint32_t reg_q_1_1a : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_1b : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_5a; - - /* 0x4B8 : mjpeg_q_param_5c */ - union { - struct { - uint32_t reg_q_1_1c : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_1d : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_5c; - - /* 0x4BC : mjpeg_q_param_5e */ - union { - struct { - uint32_t reg_q_1_1e : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_1f : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_5e; - - /* 0x4C0 : mjpeg_q_param_60 */ - union { - struct { - uint32_t reg_q_1_20 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_21 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_60; - - /* 0x4C4 : mjpeg_q_param_62 */ - union { - struct { - uint32_t reg_q_1_22 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_23 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_62; - - /* 0x4C8 : mjpeg_q_param_64 */ - union { - struct { - uint32_t reg_q_1_24 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_25 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_64; - - /* 0x4CC : mjpeg_q_param_66 */ - union { - struct { - uint32_t reg_q_1_26 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_27 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_66; - - /* 0x4D0 : mjpeg_q_param_68 */ - union { - struct { - uint32_t reg_q_1_28 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_29 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_68; - - /* 0x4D4 : mjpeg_q_param_6a */ - union { - struct { - uint32_t reg_q_1_2a : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_2b : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_6a; - - /* 0x4D8 : mjpeg_q_param_6c */ - union { - struct { - uint32_t reg_q_1_2c : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_2d : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_6c; - - /* 0x4DC : mjpeg_q_param_6e */ - union { - struct { - uint32_t reg_q_1_2e : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_2f : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_6e; - - /* 0x4E0 : mjpeg_q_param_70 */ - union { - struct { - uint32_t reg_q_1_30 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_31 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_70; - - /* 0x4E4 : mjpeg_q_param_72 */ - union { - struct { - uint32_t reg_q_1_32 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_33 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_72; - - /* 0x4E8 : mjpeg_q_param_74 */ - union { - struct { - uint32_t reg_q_1_34 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_35 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_74; - - /* 0x4EC : mjpeg_q_param_76 */ - union { - struct { - uint32_t reg_q_1_36 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_37 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_76; - - /* 0x4F0 : mjpeg_q_param_78 */ - union { - struct { - uint32_t reg_q_1_38 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_39 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_78; - - /* 0x4F4 : mjpeg_q_param_7a */ - union { - struct { - uint32_t reg_q_1_3a : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_3b : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_7a; - - /* 0x4F8 : mjpeg_q_param_7c */ - union { - struct { - uint32_t reg_q_1_3c : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_3d : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_7c; - - /* 0x4FC : mjpeg_q_param_7e */ - union { - struct { - uint32_t reg_q_1_3e : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_3f : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_7e; -}; - -typedef volatile struct mjpeg_q_reg mjpeg_q_reg_t; - -#endif /* __MJPEG_Q_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/mjpeg_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/mjpeg_reg.h deleted file mode 100644 index 84d0cac053..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/mjpeg_reg.h +++ /dev/null @@ -1,1098 +0,0 @@ -/** - ****************************************************************************** - * @file mjpeg_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __MJPEG_REG_H__ -#define __MJPEG_REG_H__ - -#include "bl808.h" - -/* 0x0 : mjpeg_control_1 */ -#define MJPEG_CONTROL_1_OFFSET (0x0) -#define MJPEG_REG_MJPEG_ENABLE MJPEG_REG_MJPEG_ENABLE -#define MJPEG_REG_MJPEG_ENABLE_POS (0U) -#define MJPEG_REG_MJPEG_ENABLE_LEN (1U) -#define MJPEG_REG_MJPEG_ENABLE_MSK (((1U << MJPEG_REG_MJPEG_ENABLE_LEN) - 1) << MJPEG_REG_MJPEG_ENABLE_POS) -#define MJPEG_REG_MJPEG_ENABLE_UMSK (~(((1U << MJPEG_REG_MJPEG_ENABLE_LEN) - 1) << MJPEG_REG_MJPEG_ENABLE_POS)) -#define MJPEG_REG_MJPEG_BIT_ORDER MJPEG_REG_MJPEG_BIT_ORDER -#define MJPEG_REG_MJPEG_BIT_ORDER_POS (1U) -#define MJPEG_REG_MJPEG_BIT_ORDER_LEN (1U) -#define MJPEG_REG_MJPEG_BIT_ORDER_MSK (((1U << MJPEG_REG_MJPEG_BIT_ORDER_LEN) - 1) << MJPEG_REG_MJPEG_BIT_ORDER_POS) -#define MJPEG_REG_MJPEG_BIT_ORDER_UMSK (~(((1U << MJPEG_REG_MJPEG_BIT_ORDER_LEN) - 1) << MJPEG_REG_MJPEG_BIT_ORDER_POS)) -#define MJPEG_REG_ORDER_U_EVEN MJPEG_REG_ORDER_U_EVEN -#define MJPEG_REG_ORDER_U_EVEN_POS (2U) -#define MJPEG_REG_ORDER_U_EVEN_LEN (1U) -#define MJPEG_REG_ORDER_U_EVEN_MSK (((1U << MJPEG_REG_ORDER_U_EVEN_LEN) - 1) << MJPEG_REG_ORDER_U_EVEN_POS) -#define MJPEG_REG_ORDER_U_EVEN_UMSK (~(((1U << MJPEG_REG_ORDER_U_EVEN_LEN) - 1) << MJPEG_REG_ORDER_U_EVEN_POS)) -#define MJPEG_REG_LAST_HF_WBLK_DMY MJPEG_REG_LAST_HF_WBLK_DMY -#define MJPEG_REG_LAST_HF_WBLK_DMY_POS (4U) -#define MJPEG_REG_LAST_HF_WBLK_DMY_LEN (1U) -#define MJPEG_REG_LAST_HF_WBLK_DMY_MSK (((1U << MJPEG_REG_LAST_HF_WBLK_DMY_LEN) - 1) << MJPEG_REG_LAST_HF_WBLK_DMY_POS) -#define MJPEG_REG_LAST_HF_WBLK_DMY_UMSK (~(((1U << MJPEG_REG_LAST_HF_WBLK_DMY_LEN) - 1) << MJPEG_REG_LAST_HF_WBLK_DMY_POS)) -#define MJPEG_REG_LAST_HF_HBLK_DMY MJPEG_REG_LAST_HF_HBLK_DMY -#define MJPEG_REG_LAST_HF_HBLK_DMY_POS (5U) -#define MJPEG_REG_LAST_HF_HBLK_DMY_LEN (1U) -#define MJPEG_REG_LAST_HF_HBLK_DMY_MSK (((1U << MJPEG_REG_LAST_HF_HBLK_DMY_LEN) - 1) << MJPEG_REG_LAST_HF_HBLK_DMY_POS) -#define MJPEG_REG_LAST_HF_HBLK_DMY_UMSK (~(((1U << MJPEG_REG_LAST_HF_HBLK_DMY_LEN) - 1) << MJPEG_REG_LAST_HF_HBLK_DMY_POS)) -#define MJPEG_REG_REFLECT_DMY MJPEG_REG_REFLECT_DMY -#define MJPEG_REG_REFLECT_DMY_POS (6U) -#define MJPEG_REG_REFLECT_DMY_LEN (1U) -#define MJPEG_REG_REFLECT_DMY_MSK (((1U << MJPEG_REG_REFLECT_DMY_LEN) - 1) << MJPEG_REG_REFLECT_DMY_POS) -#define MJPEG_REG_REFLECT_DMY_UMSK (~(((1U << MJPEG_REG_REFLECT_DMY_LEN) - 1) << MJPEG_REG_REFLECT_DMY_POS)) -#define MJPEG_REG_READ_FWRAP MJPEG_REG_READ_FWRAP -#define MJPEG_REG_READ_FWRAP_POS (7U) -#define MJPEG_REG_READ_FWRAP_LEN (1U) -#define MJPEG_REG_READ_FWRAP_MSK (((1U << MJPEG_REG_READ_FWRAP_LEN) - 1) << MJPEG_REG_READ_FWRAP_POS) -#define MJPEG_REG_READ_FWRAP_UMSK (~(((1U << MJPEG_REG_READ_FWRAP_LEN) - 1) << MJPEG_REG_READ_FWRAP_POS)) -#define MJPEG_REG_W_XLEN MJPEG_REG_W_XLEN -#define MJPEG_REG_W_XLEN_POS (8U) -#define MJPEG_REG_W_XLEN_LEN (3U) -#define MJPEG_REG_W_XLEN_MSK (((1U << MJPEG_REG_W_XLEN_LEN) - 1) << MJPEG_REG_W_XLEN_POS) -#define MJPEG_REG_W_XLEN_UMSK (~(((1U << MJPEG_REG_W_XLEN_LEN) - 1) << MJPEG_REG_W_XLEN_POS)) -#define MJPEG_REG_YUV_MODE MJPEG_REG_YUV_MODE -#define MJPEG_REG_YUV_MODE_POS (12U) -#define MJPEG_REG_YUV_MODE_LEN (2U) -#define MJPEG_REG_YUV_MODE_MSK (((1U << MJPEG_REG_YUV_MODE_LEN) - 1) << MJPEG_REG_YUV_MODE_POS) -#define MJPEG_REG_YUV_MODE_UMSK (~(((1U << MJPEG_REG_YUV_MODE_LEN) - 1) << MJPEG_REG_YUV_MODE_POS)) -#define MJPEG_REG_MJPEG_HW_FRAME MJPEG_REG_MJPEG_HW_FRAME -#define MJPEG_REG_MJPEG_HW_FRAME_POS (24U) -#define MJPEG_REG_MJPEG_HW_FRAME_LEN (6U) -#define MJPEG_REG_MJPEG_HW_FRAME_MSK (((1U << MJPEG_REG_MJPEG_HW_FRAME_LEN) - 1) << MJPEG_REG_MJPEG_HW_FRAME_POS) -#define MJPEG_REG_MJPEG_HW_FRAME_UMSK (~(((1U << MJPEG_REG_MJPEG_HW_FRAME_LEN) - 1) << MJPEG_REG_MJPEG_HW_FRAME_POS)) - -/* 0x4 : mjpeg_control_2 */ -#define MJPEG_CONTROL_2_OFFSET (0x4) -#define MJPEG_REG_SW_FRAME MJPEG_REG_SW_FRAME -#define MJPEG_REG_SW_FRAME_POS (0U) -#define MJPEG_REG_SW_FRAME_LEN (5U) -#define MJPEG_REG_SW_FRAME_MSK (((1U << MJPEG_REG_SW_FRAME_LEN) - 1) << MJPEG_REG_SW_FRAME_POS) -#define MJPEG_REG_SW_FRAME_UMSK (~(((1U << MJPEG_REG_SW_FRAME_LEN) - 1) << MJPEG_REG_SW_FRAME_POS)) -#define MJPEG_REG_SW_KICK MJPEG_REG_SW_KICK -#define MJPEG_REG_SW_KICK_POS (6U) -#define MJPEG_REG_SW_KICK_LEN (1U) -#define MJPEG_REG_SW_KICK_MSK (((1U << MJPEG_REG_SW_KICK_LEN) - 1) << MJPEG_REG_SW_KICK_POS) -#define MJPEG_REG_SW_KICK_UMSK (~(((1U << MJPEG_REG_SW_KICK_LEN) - 1) << MJPEG_REG_SW_KICK_POS)) -#define MJPEG_REG_SW_KICK_MODE MJPEG_REG_SW_KICK_MODE -#define MJPEG_REG_SW_KICK_MODE_POS (7U) -#define MJPEG_REG_SW_KICK_MODE_LEN (1U) -#define MJPEG_REG_SW_KICK_MODE_MSK (((1U << MJPEG_REG_SW_KICK_MODE_LEN) - 1) << MJPEG_REG_SW_KICK_MODE_POS) -#define MJPEG_REG_SW_KICK_MODE_UMSK (~(((1U << MJPEG_REG_SW_KICK_MODE_LEN) - 1) << MJPEG_REG_SW_KICK_MODE_POS)) -#define MJPEG_REG_MJPEG_SW_MODE MJPEG_REG_MJPEG_SW_MODE -#define MJPEG_REG_MJPEG_SW_MODE_POS (8U) -#define MJPEG_REG_MJPEG_SW_MODE_LEN (1U) -#define MJPEG_REG_MJPEG_SW_MODE_MSK (((1U << MJPEG_REG_MJPEG_SW_MODE_LEN) - 1) << MJPEG_REG_MJPEG_SW_MODE_POS) -#define MJPEG_REG_MJPEG_SW_MODE_UMSK (~(((1U << MJPEG_REG_MJPEG_SW_MODE_LEN) - 1) << MJPEG_REG_MJPEG_SW_MODE_POS)) -#define MJPEG_REG_MJPEG_SW_RUN MJPEG_REG_MJPEG_SW_RUN -#define MJPEG_REG_MJPEG_SW_RUN_POS (9U) -#define MJPEG_REG_MJPEG_SW_RUN_LEN (1U) -#define MJPEG_REG_MJPEG_SW_RUN_MSK (((1U << MJPEG_REG_MJPEG_SW_RUN_LEN) - 1) << MJPEG_REG_MJPEG_SW_RUN_POS) -#define MJPEG_REG_MJPEG_SW_RUN_UMSK (~(((1U << MJPEG_REG_MJPEG_SW_RUN_LEN) - 1) << MJPEG_REG_MJPEG_SW_RUN_POS)) -#define MJPEG_REG_YY_DVP2AXI_SEL MJPEG_REG_YY_DVP2AXI_SEL -#define MJPEG_REG_YY_DVP2AXI_SEL_POS (10U) -#define MJPEG_REG_YY_DVP2AXI_SEL_LEN (3U) -#define MJPEG_REG_YY_DVP2AXI_SEL_MSK (((1U << MJPEG_REG_YY_DVP2AXI_SEL_LEN) - 1) << MJPEG_REG_YY_DVP2AXI_SEL_POS) -#define MJPEG_REG_YY_DVP2AXI_SEL_UMSK (~(((1U << MJPEG_REG_YY_DVP2AXI_SEL_LEN) - 1) << MJPEG_REG_YY_DVP2AXI_SEL_POS)) -#define MJPEG_REG_UV_DVP2AXI_SEL MJPEG_REG_UV_DVP2AXI_SEL -#define MJPEG_REG_UV_DVP2AXI_SEL_POS (13U) -#define MJPEG_REG_UV_DVP2AXI_SEL_LEN (3U) -#define MJPEG_REG_UV_DVP2AXI_SEL_MSK (((1U << MJPEG_REG_UV_DVP2AXI_SEL_LEN) - 1) << MJPEG_REG_UV_DVP2AXI_SEL_POS) -#define MJPEG_REG_UV_DVP2AXI_SEL_UMSK (~(((1U << MJPEG_REG_UV_DVP2AXI_SEL_LEN) - 1) << MJPEG_REG_UV_DVP2AXI_SEL_POS)) -#define MJPEG_REG_MJPEG_WAIT_CYCLE MJPEG_REG_MJPEG_WAIT_CYCLE -#define MJPEG_REG_MJPEG_WAIT_CYCLE_POS (16U) -#define MJPEG_REG_MJPEG_WAIT_CYCLE_LEN (16U) -#define MJPEG_REG_MJPEG_WAIT_CYCLE_MSK (((1U << MJPEG_REG_MJPEG_WAIT_CYCLE_LEN) - 1) << MJPEG_REG_MJPEG_WAIT_CYCLE_POS) -#define MJPEG_REG_MJPEG_WAIT_CYCLE_UMSK (~(((1U << MJPEG_REG_MJPEG_WAIT_CYCLE_LEN) - 1) << MJPEG_REG_MJPEG_WAIT_CYCLE_POS)) - -/* 0x08 : mjpeg_yy_frame_addr */ -#define MJPEG_YY_FRAME_ADDR_OFFSET (0x08) -#define MJPEG_REG_YY_ADDR_START MJPEG_REG_YY_ADDR_START -#define MJPEG_REG_YY_ADDR_START_POS (0U) -#define MJPEG_REG_YY_ADDR_START_LEN (32U) -#define MJPEG_REG_YY_ADDR_START_MSK (((1U << MJPEG_REG_YY_ADDR_START_LEN) - 1) << MJPEG_REG_YY_ADDR_START_POS) -#define MJPEG_REG_YY_ADDR_START_UMSK (~(((1U << MJPEG_REG_YY_ADDR_START_LEN) - 1) << MJPEG_REG_YY_ADDR_START_POS)) - -/* 0x0C : mjpeg_uv_frame_addr */ -#define MJPEG_UV_FRAME_ADDR_OFFSET (0x0C) -#define MJPEG_REG_UV_ADDR_START MJPEG_REG_UV_ADDR_START -#define MJPEG_REG_UV_ADDR_START_POS (0U) -#define MJPEG_REG_UV_ADDR_START_LEN (32U) -#define MJPEG_REG_UV_ADDR_START_MSK (((1U << MJPEG_REG_UV_ADDR_START_LEN) - 1) << MJPEG_REG_UV_ADDR_START_POS) -#define MJPEG_REG_UV_ADDR_START_UMSK (~(((1U << MJPEG_REG_UV_ADDR_START_LEN) - 1) << MJPEG_REG_UV_ADDR_START_POS)) - -/* 0x10 : mjpeg_yuv_mem */ -#define MJPEG_YUV_MEM_OFFSET (0x10) -#define MJPEG_REG_YY_MEM_HBLK MJPEG_REG_YY_MEM_HBLK -#define MJPEG_REG_YY_MEM_HBLK_POS (0U) -#define MJPEG_REG_YY_MEM_HBLK_LEN (13U) -#define MJPEG_REG_YY_MEM_HBLK_MSK (((1U << MJPEG_REG_YY_MEM_HBLK_LEN) - 1) << MJPEG_REG_YY_MEM_HBLK_POS) -#define MJPEG_REG_YY_MEM_HBLK_UMSK (~(((1U << MJPEG_REG_YY_MEM_HBLK_LEN) - 1) << MJPEG_REG_YY_MEM_HBLK_POS)) -#define MJPEG_REG_UV_MEM_HBLK MJPEG_REG_UV_MEM_HBLK -#define MJPEG_REG_UV_MEM_HBLK_POS (16U) -#define MJPEG_REG_UV_MEM_HBLK_LEN (13U) -#define MJPEG_REG_UV_MEM_HBLK_MSK (((1U << MJPEG_REG_UV_MEM_HBLK_LEN) - 1) << MJPEG_REG_UV_MEM_HBLK_POS) -#define MJPEG_REG_UV_MEM_HBLK_UMSK (~(((1U << MJPEG_REG_UV_MEM_HBLK_LEN) - 1) << MJPEG_REG_UV_MEM_HBLK_POS)) - -/* 0x14 : jpeg_frame_addr */ -#define MJPEG_JPEG_FRAME_ADDR_OFFSET (0x14) -#define MJPEG_REG_W_ADDR_START MJPEG_REG_W_ADDR_START -#define MJPEG_REG_W_ADDR_START_POS (0U) -#define MJPEG_REG_W_ADDR_START_LEN (32U) -#define MJPEG_REG_W_ADDR_START_MSK (((1U << MJPEG_REG_W_ADDR_START_LEN) - 1) << MJPEG_REG_W_ADDR_START_POS) -#define MJPEG_REG_W_ADDR_START_UMSK (~(((1U << MJPEG_REG_W_ADDR_START_LEN) - 1) << MJPEG_REG_W_ADDR_START_POS)) - -/* 0x18 : jpeg_store_memory */ -#define MJPEG_JPEG_STORE_MEMORY_OFFSET (0x18) -#define MJPEG_REG_W_BURST_CNT MJPEG_REG_W_BURST_CNT -#define MJPEG_REG_W_BURST_CNT_POS (0U) -#define MJPEG_REG_W_BURST_CNT_LEN (32U) -#define MJPEG_REG_W_BURST_CNT_MSK (((1U << MJPEG_REG_W_BURST_CNT_LEN) - 1) << MJPEG_REG_W_BURST_CNT_POS) -#define MJPEG_REG_W_BURST_CNT_UMSK (~(((1U << MJPEG_REG_W_BURST_CNT_LEN) - 1) << MJPEG_REG_W_BURST_CNT_POS)) - -/* 0x1C : mjpeg_control_3 */ -#define MJPEG_CONTROL_3_OFFSET (0x1C) -#define MJPEG_REG_INT_NORMAL_EN MJPEG_REG_INT_NORMAL_EN -#define MJPEG_REG_INT_NORMAL_EN_POS (0U) -#define MJPEG_REG_INT_NORMAL_EN_LEN (1U) -#define MJPEG_REG_INT_NORMAL_EN_MSK (((1U << MJPEG_REG_INT_NORMAL_EN_LEN) - 1) << MJPEG_REG_INT_NORMAL_EN_POS) -#define MJPEG_REG_INT_NORMAL_EN_UMSK (~(((1U << MJPEG_REG_INT_NORMAL_EN_LEN) - 1) << MJPEG_REG_INT_NORMAL_EN_POS)) -#define MJPEG_REG_INT_CAM_EN MJPEG_REG_INT_CAM_EN -#define MJPEG_REG_INT_CAM_EN_POS (1U) -#define MJPEG_REG_INT_CAM_EN_LEN (1U) -#define MJPEG_REG_INT_CAM_EN_MSK (((1U << MJPEG_REG_INT_CAM_EN_LEN) - 1) << MJPEG_REG_INT_CAM_EN_POS) -#define MJPEG_REG_INT_CAM_EN_UMSK (~(((1U << MJPEG_REG_INT_CAM_EN_LEN) - 1) << MJPEG_REG_INT_CAM_EN_POS)) -#define MJPEG_REG_INT_MEM_EN MJPEG_REG_INT_MEM_EN -#define MJPEG_REG_INT_MEM_EN_POS (2U) -#define MJPEG_REG_INT_MEM_EN_LEN (1U) -#define MJPEG_REG_INT_MEM_EN_MSK (((1U << MJPEG_REG_INT_MEM_EN_LEN) - 1) << MJPEG_REG_INT_MEM_EN_POS) -#define MJPEG_REG_INT_MEM_EN_UMSK (~(((1U << MJPEG_REG_INT_MEM_EN_LEN) - 1) << MJPEG_REG_INT_MEM_EN_POS)) -#define MJPEG_REG_INT_FRAME_EN MJPEG_REG_INT_FRAME_EN -#define MJPEG_REG_INT_FRAME_EN_POS (3U) -#define MJPEG_REG_INT_FRAME_EN_LEN (1U) -#define MJPEG_REG_INT_FRAME_EN_MSK (((1U << MJPEG_REG_INT_FRAME_EN_LEN) - 1) << MJPEG_REG_INT_FRAME_EN_POS) -#define MJPEG_REG_INT_FRAME_EN_UMSK (~(((1U << MJPEG_REG_INT_FRAME_EN_LEN) - 1) << MJPEG_REG_INT_FRAME_EN_POS)) -#define MJPEG_STS_NORMAL_INT MJPEG_STS_NORMAL_INT -#define MJPEG_STS_NORMAL_INT_POS (4U) -#define MJPEG_STS_NORMAL_INT_LEN (1U) -#define MJPEG_STS_NORMAL_INT_MSK (((1U << MJPEG_STS_NORMAL_INT_LEN) - 1) << MJPEG_STS_NORMAL_INT_POS) -#define MJPEG_STS_NORMAL_INT_UMSK (~(((1U << MJPEG_STS_NORMAL_INT_LEN) - 1) << MJPEG_STS_NORMAL_INT_POS)) -#define MJPEG_STS_CAM_INT MJPEG_STS_CAM_INT -#define MJPEG_STS_CAM_INT_POS (5U) -#define MJPEG_STS_CAM_INT_LEN (1U) -#define MJPEG_STS_CAM_INT_MSK (((1U << MJPEG_STS_CAM_INT_LEN) - 1) << MJPEG_STS_CAM_INT_POS) -#define MJPEG_STS_CAM_INT_UMSK (~(((1U << MJPEG_STS_CAM_INT_LEN) - 1) << MJPEG_STS_CAM_INT_POS)) -#define MJPEG_STS_MEM_INT MJPEG_STS_MEM_INT -#define MJPEG_STS_MEM_INT_POS (6U) -#define MJPEG_STS_MEM_INT_LEN (1U) -#define MJPEG_STS_MEM_INT_MSK (((1U << MJPEG_STS_MEM_INT_LEN) - 1) << MJPEG_STS_MEM_INT_POS) -#define MJPEG_STS_MEM_INT_UMSK (~(((1U << MJPEG_STS_MEM_INT_LEN) - 1) << MJPEG_STS_MEM_INT_POS)) -#define MJPEG_STS_FRAME_INT MJPEG_STS_FRAME_INT -#define MJPEG_STS_FRAME_INT_POS (7U) -#define MJPEG_STS_FRAME_INT_LEN (1U) -#define MJPEG_STS_FRAME_INT_MSK (((1U << MJPEG_STS_FRAME_INT_LEN) - 1) << MJPEG_STS_FRAME_INT_POS) -#define MJPEG_STS_FRAME_INT_UMSK (~(((1U << MJPEG_STS_FRAME_INT_LEN) - 1) << MJPEG_STS_FRAME_INT_POS)) -#define MJPEG_IDLE MJPEG_IDLE -#define MJPEG_IDLE_POS (8U) -#define MJPEG_IDLE_LEN (1U) -#define MJPEG_IDLE_MSK (((1U << MJPEG_IDLE_LEN) - 1) << MJPEG_IDLE_POS) -#define MJPEG_IDLE_UMSK (~(((1U << MJPEG_IDLE_LEN) - 1) << MJPEG_IDLE_POS)) -#define MJPEG_FUNC MJPEG_FUNC -#define MJPEG_FUNC_POS (9U) -#define MJPEG_FUNC_LEN (1U) -#define MJPEG_FUNC_MSK (((1U << MJPEG_FUNC_LEN) - 1) << MJPEG_FUNC_POS) -#define MJPEG_FUNC_UMSK (~(((1U << MJPEG_FUNC_LEN) - 1) << MJPEG_FUNC_POS)) -#define MJPEG_WAIT MJPEG_WAIT -#define MJPEG_WAIT_POS (10U) -#define MJPEG_WAIT_LEN (1U) -#define MJPEG_WAIT_MSK (((1U << MJPEG_WAIT_LEN) - 1) << MJPEG_WAIT_POS) -#define MJPEG_WAIT_UMSK (~(((1U << MJPEG_WAIT_LEN) - 1) << MJPEG_WAIT_POS)) -#define MJPEG_FLSH MJPEG_FLSH -#define MJPEG_FLSH_POS (11U) -#define MJPEG_FLSH_LEN (1U) -#define MJPEG_FLSH_MSK (((1U << MJPEG_FLSH_LEN) - 1) << MJPEG_FLSH_POS) -#define MJPEG_FLSH_UMSK (~(((1U << MJPEG_FLSH_LEN) - 1) << MJPEG_FLSH_POS)) -#define MJPEG_MANS MJPEG_MANS -#define MJPEG_MANS_POS (12U) -#define MJPEG_MANS_LEN (1U) -#define MJPEG_MANS_MSK (((1U << MJPEG_MANS_LEN) - 1) << MJPEG_MANS_POS) -#define MJPEG_MANS_UMSK (~(((1U << MJPEG_MANS_LEN) - 1) << MJPEG_MANS_POS)) -#define MJPEG_MANF MJPEG_MANF -#define MJPEG_MANF_POS (13U) -#define MJPEG_MANF_LEN (1U) -#define MJPEG_MANF_MSK (((1U << MJPEG_MANF_LEN) - 1) << MJPEG_MANF_POS) -#define MJPEG_MANF_UMSK (~(((1U << MJPEG_MANF_LEN) - 1) << MJPEG_MANF_POS)) -#define MJPEG_AXI_READ_IDLE MJPEG_AXI_READ_IDLE -#define MJPEG_AXI_READ_IDLE_POS (14U) -#define MJPEG_AXI_READ_IDLE_LEN (1U) -#define MJPEG_AXI_READ_IDLE_MSK (((1U << MJPEG_AXI_READ_IDLE_LEN) - 1) << MJPEG_AXI_READ_IDLE_POS) -#define MJPEG_AXI_READ_IDLE_UMSK (~(((1U << MJPEG_AXI_READ_IDLE_LEN) - 1) << MJPEG_AXI_READ_IDLE_POS)) -#define MJPEG_AXI_WRITE_IDLE MJPEG_AXI_WRITE_IDLE -#define MJPEG_AXI_WRITE_IDLE_POS (15U) -#define MJPEG_AXI_WRITE_IDLE_LEN (1U) -#define MJPEG_AXI_WRITE_IDLE_MSK (((1U << MJPEG_AXI_WRITE_IDLE_LEN) - 1) << MJPEG_AXI_WRITE_IDLE_POS) -#define MJPEG_AXI_WRITE_IDLE_UMSK (~(((1U << MJPEG_AXI_WRITE_IDLE_LEN) - 1) << MJPEG_AXI_WRITE_IDLE_POS)) -#define MJPEG_REG_FRAME_CNT_TRGR_INT MJPEG_REG_FRAME_CNT_TRGR_INT -#define MJPEG_REG_FRAME_CNT_TRGR_INT_POS (16U) -#define MJPEG_REG_FRAME_CNT_TRGR_INT_LEN (5U) -#define MJPEG_REG_FRAME_CNT_TRGR_INT_MSK (((1U << MJPEG_REG_FRAME_CNT_TRGR_INT_LEN) - 1) << MJPEG_REG_FRAME_CNT_TRGR_INT_POS) -#define MJPEG_REG_FRAME_CNT_TRGR_INT_UMSK (~(((1U << MJPEG_REG_FRAME_CNT_TRGR_INT_LEN) - 1) << MJPEG_REG_FRAME_CNT_TRGR_INT_POS)) -#define MJPEG_REG_INT_IDLE_EN MJPEG_REG_INT_IDLE_EN -#define MJPEG_REG_INT_IDLE_EN_POS (21U) -#define MJPEG_REG_INT_IDLE_EN_LEN (1U) -#define MJPEG_REG_INT_IDLE_EN_MSK (((1U << MJPEG_REG_INT_IDLE_EN_LEN) - 1) << MJPEG_REG_INT_IDLE_EN_POS) -#define MJPEG_REG_INT_IDLE_EN_UMSK (~(((1U << MJPEG_REG_INT_IDLE_EN_LEN) - 1) << MJPEG_REG_INT_IDLE_EN_POS)) -#define MJPEG_STS_IDLE_INT MJPEG_STS_IDLE_INT -#define MJPEG_STS_IDLE_INT_POS (22U) -#define MJPEG_STS_IDLE_INT_LEN (1U) -#define MJPEG_STS_IDLE_INT_MSK (((1U << MJPEG_STS_IDLE_INT_LEN) - 1) << MJPEG_STS_IDLE_INT_POS) -#define MJPEG_STS_IDLE_INT_UMSK (~(((1U << MJPEG_STS_IDLE_INT_LEN) - 1) << MJPEG_STS_IDLE_INT_POS)) -#define MJPEG_FRAME_VALID_CNT MJPEG_FRAME_VALID_CNT -#define MJPEG_FRAME_VALID_CNT_POS (24U) -#define MJPEG_FRAME_VALID_CNT_LEN (5U) -#define MJPEG_FRAME_VALID_CNT_MSK (((1U << MJPEG_FRAME_VALID_CNT_LEN) - 1) << MJPEG_FRAME_VALID_CNT_POS) -#define MJPEG_FRAME_VALID_CNT_UMSK (~(((1U << MJPEG_FRAME_VALID_CNT_LEN) - 1) << MJPEG_FRAME_VALID_CNT_POS)) -#define MJPEG_REG_INT_SWAP_EN MJPEG_REG_INT_SWAP_EN -#define MJPEG_REG_INT_SWAP_EN_POS (29U) -#define MJPEG_REG_INT_SWAP_EN_LEN (1U) -#define MJPEG_REG_INT_SWAP_EN_MSK (((1U << MJPEG_REG_INT_SWAP_EN_LEN) - 1) << MJPEG_REG_INT_SWAP_EN_POS) -#define MJPEG_REG_INT_SWAP_EN_UMSK (~(((1U << MJPEG_REG_INT_SWAP_EN_LEN) - 1) << MJPEG_REG_INT_SWAP_EN_POS)) -#define MJPEG_STS_SWAP_INT MJPEG_STS_SWAP_INT -#define MJPEG_STS_SWAP_INT_POS (30U) -#define MJPEG_STS_SWAP_INT_LEN (1U) -#define MJPEG_STS_SWAP_INT_MSK (((1U << MJPEG_STS_SWAP_INT_LEN) - 1) << MJPEG_STS_SWAP_INT_POS) -#define MJPEG_STS_SWAP_INT_UMSK (~(((1U << MJPEG_STS_SWAP_INT_LEN) - 1) << MJPEG_STS_SWAP_INT_POS)) - -/* 0x20 : mjpeg_frame_fifo_pop */ -#define MJPEG_FRAME_FIFO_POP_OFFSET (0x20) -#define MJPEG_RFIFO_POP MJPEG_RFIFO_POP -#define MJPEG_RFIFO_POP_POS (0U) -#define MJPEG_RFIFO_POP_LEN (1U) -#define MJPEG_RFIFO_POP_MSK (((1U << MJPEG_RFIFO_POP_LEN) - 1) << MJPEG_RFIFO_POP_POS) -#define MJPEG_RFIFO_POP_UMSK (~(((1U << MJPEG_RFIFO_POP_LEN) - 1) << MJPEG_RFIFO_POP_POS)) -#define MJPEG_REG_W_SWAP_CLR MJPEG_REG_W_SWAP_CLR -#define MJPEG_REG_W_SWAP_CLR_POS (1U) -#define MJPEG_REG_W_SWAP_CLR_LEN (1U) -#define MJPEG_REG_W_SWAP_CLR_MSK (((1U << MJPEG_REG_W_SWAP_CLR_LEN) - 1) << MJPEG_REG_W_SWAP_CLR_POS) -#define MJPEG_REG_W_SWAP_CLR_UMSK (~(((1U << MJPEG_REG_W_SWAP_CLR_LEN) - 1) << MJPEG_REG_W_SWAP_CLR_POS)) -#define MJPEG_REG_INT_NORMAL_CLR MJPEG_REG_INT_NORMAL_CLR -#define MJPEG_REG_INT_NORMAL_CLR_POS (8U) -#define MJPEG_REG_INT_NORMAL_CLR_LEN (1U) -#define MJPEG_REG_INT_NORMAL_CLR_MSK (((1U << MJPEG_REG_INT_NORMAL_CLR_LEN) - 1) << MJPEG_REG_INT_NORMAL_CLR_POS) -#define MJPEG_REG_INT_NORMAL_CLR_UMSK (~(((1U << MJPEG_REG_INT_NORMAL_CLR_LEN) - 1) << MJPEG_REG_INT_NORMAL_CLR_POS)) -#define MJPEG_REG_INT_CAM_CLR MJPEG_REG_INT_CAM_CLR -#define MJPEG_REG_INT_CAM_CLR_POS (9U) -#define MJPEG_REG_INT_CAM_CLR_LEN (1U) -#define MJPEG_REG_INT_CAM_CLR_MSK (((1U << MJPEG_REG_INT_CAM_CLR_LEN) - 1) << MJPEG_REG_INT_CAM_CLR_POS) -#define MJPEG_REG_INT_CAM_CLR_UMSK (~(((1U << MJPEG_REG_INT_CAM_CLR_LEN) - 1) << MJPEG_REG_INT_CAM_CLR_POS)) -#define MJPEG_REG_INT_MEM_CLR MJPEG_REG_INT_MEM_CLR -#define MJPEG_REG_INT_MEM_CLR_POS (10U) -#define MJPEG_REG_INT_MEM_CLR_LEN (1U) -#define MJPEG_REG_INT_MEM_CLR_MSK (((1U << MJPEG_REG_INT_MEM_CLR_LEN) - 1) << MJPEG_REG_INT_MEM_CLR_POS) -#define MJPEG_REG_INT_MEM_CLR_UMSK (~(((1U << MJPEG_REG_INT_MEM_CLR_LEN) - 1) << MJPEG_REG_INT_MEM_CLR_POS)) -#define MJPEG_REG_INT_FRAME_CLR MJPEG_REG_INT_FRAME_CLR -#define MJPEG_REG_INT_FRAME_CLR_POS (11U) -#define MJPEG_REG_INT_FRAME_CLR_LEN (1U) -#define MJPEG_REG_INT_FRAME_CLR_MSK (((1U << MJPEG_REG_INT_FRAME_CLR_LEN) - 1) << MJPEG_REG_INT_FRAME_CLR_POS) -#define MJPEG_REG_INT_FRAME_CLR_UMSK (~(((1U << MJPEG_REG_INT_FRAME_CLR_LEN) - 1) << MJPEG_REG_INT_FRAME_CLR_POS)) -#define MJPEG_REG_INT_IDLE_CLR MJPEG_REG_INT_IDLE_CLR -#define MJPEG_REG_INT_IDLE_CLR_POS (12U) -#define MJPEG_REG_INT_IDLE_CLR_LEN (1U) -#define MJPEG_REG_INT_IDLE_CLR_MSK (((1U << MJPEG_REG_INT_IDLE_CLR_LEN) - 1) << MJPEG_REG_INT_IDLE_CLR_POS) -#define MJPEG_REG_INT_IDLE_CLR_UMSK (~(((1U << MJPEG_REG_INT_IDLE_CLR_LEN) - 1) << MJPEG_REG_INT_IDLE_CLR_POS)) -#define MJPEG_REG_INT_SWAP_CLR MJPEG_REG_INT_SWAP_CLR -#define MJPEG_REG_INT_SWAP_CLR_POS (13U) -#define MJPEG_REG_INT_SWAP_CLR_LEN (1U) -#define MJPEG_REG_INT_SWAP_CLR_MSK (((1U << MJPEG_REG_INT_SWAP_CLR_LEN) - 1) << MJPEG_REG_INT_SWAP_CLR_POS) -#define MJPEG_REG_INT_SWAP_CLR_UMSK (~(((1U << MJPEG_REG_INT_SWAP_CLR_LEN) - 1) << MJPEG_REG_INT_SWAP_CLR_POS)) - -/* 0x24 : mjpeg_frame_size */ -#define MJPEG_FRAME_SIZE_OFFSET (0x24) -#define MJPEG_REG_FRAME_WBLK MJPEG_REG_FRAME_WBLK -#define MJPEG_REG_FRAME_WBLK_POS (0U) -#define MJPEG_REG_FRAME_WBLK_LEN (12U) -#define MJPEG_REG_FRAME_WBLK_MSK (((1U << MJPEG_REG_FRAME_WBLK_LEN) - 1) << MJPEG_REG_FRAME_WBLK_POS) -#define MJPEG_REG_FRAME_WBLK_UMSK (~(((1U << MJPEG_REG_FRAME_WBLK_LEN) - 1) << MJPEG_REG_FRAME_WBLK_POS)) -#define MJPEG_REG_FRAME_HBLK MJPEG_REG_FRAME_HBLK -#define MJPEG_REG_FRAME_HBLK_POS (16U) -#define MJPEG_REG_FRAME_HBLK_LEN (12U) -#define MJPEG_REG_FRAME_HBLK_MSK (((1U << MJPEG_REG_FRAME_HBLK_LEN) - 1) << MJPEG_REG_FRAME_HBLK_POS) -#define MJPEG_REG_FRAME_HBLK_UMSK (~(((1U << MJPEG_REG_FRAME_HBLK_LEN) - 1) << MJPEG_REG_FRAME_HBLK_POS)) - -/* 0x28 : mjpeg_header_byte */ -#define MJPEG_HEADER_BYTE_OFFSET (0x28) -#define MJPEG_REG_HEAD_BYTE MJPEG_REG_HEAD_BYTE -#define MJPEG_REG_HEAD_BYTE_POS (0U) -#define MJPEG_REG_HEAD_BYTE_LEN (12U) -#define MJPEG_REG_HEAD_BYTE_MSK (((1U << MJPEG_REG_HEAD_BYTE_LEN) - 1) << MJPEG_REG_HEAD_BYTE_POS) -#define MJPEG_REG_HEAD_BYTE_UMSK (~(((1U << MJPEG_REG_HEAD_BYTE_LEN) - 1) << MJPEG_REG_HEAD_BYTE_POS)) -#define MJPEG_REG_TAIL_EXP MJPEG_REG_TAIL_EXP -#define MJPEG_REG_TAIL_EXP_POS (16U) -#define MJPEG_REG_TAIL_EXP_LEN (1U) -#define MJPEG_REG_TAIL_EXP_MSK (((1U << MJPEG_REG_TAIL_EXP_LEN) - 1) << MJPEG_REG_TAIL_EXP_POS) -#define MJPEG_REG_TAIL_EXP_UMSK (~(((1U << MJPEG_REG_TAIL_EXP_LEN) - 1) << MJPEG_REG_TAIL_EXP_POS)) -#define MJPEG_REG_Y0_ORDER MJPEG_REG_Y0_ORDER -#define MJPEG_REG_Y0_ORDER_POS (24U) -#define MJPEG_REG_Y0_ORDER_LEN (2U) -#define MJPEG_REG_Y0_ORDER_MSK (((1U << MJPEG_REG_Y0_ORDER_LEN) - 1) << MJPEG_REG_Y0_ORDER_POS) -#define MJPEG_REG_Y0_ORDER_UMSK (~(((1U << MJPEG_REG_Y0_ORDER_LEN) - 1) << MJPEG_REG_Y0_ORDER_POS)) -#define MJPEG_REG_U0_ORDER MJPEG_REG_U0_ORDER -#define MJPEG_REG_U0_ORDER_POS (26U) -#define MJPEG_REG_U0_ORDER_LEN (2U) -#define MJPEG_REG_U0_ORDER_MSK (((1U << MJPEG_REG_U0_ORDER_LEN) - 1) << MJPEG_REG_U0_ORDER_POS) -#define MJPEG_REG_U0_ORDER_UMSK (~(((1U << MJPEG_REG_U0_ORDER_LEN) - 1) << MJPEG_REG_U0_ORDER_POS)) -#define MJPEG_REG_Y1_ORDER MJPEG_REG_Y1_ORDER -#define MJPEG_REG_Y1_ORDER_POS (28U) -#define MJPEG_REG_Y1_ORDER_LEN (2U) -#define MJPEG_REG_Y1_ORDER_MSK (((1U << MJPEG_REG_Y1_ORDER_LEN) - 1) << MJPEG_REG_Y1_ORDER_POS) -#define MJPEG_REG_Y1_ORDER_UMSK (~(((1U << MJPEG_REG_Y1_ORDER_LEN) - 1) << MJPEG_REG_Y1_ORDER_POS)) -#define MJPEG_REG_V0_ORDER MJPEG_REG_V0_ORDER -#define MJPEG_REG_V0_ORDER_POS (30U) -#define MJPEG_REG_V0_ORDER_LEN (2U) -#define MJPEG_REG_V0_ORDER_MSK (((1U << MJPEG_REG_V0_ORDER_LEN) - 1) << MJPEG_REG_V0_ORDER_POS) -#define MJPEG_REG_V0_ORDER_UMSK (~(((1U << MJPEG_REG_V0_ORDER_LEN) - 1) << MJPEG_REG_V0_ORDER_POS)) - -/* 0x30 : mjpeg_swap_mode */ -#define MJPEG_SWAP_MODE_OFFSET (0x30) -#define MJPEG_REG_W_SWAP_MODE MJPEG_REG_W_SWAP_MODE -#define MJPEG_REG_W_SWAP_MODE_POS (0U) -#define MJPEG_REG_W_SWAP_MODE_LEN (1U) -#define MJPEG_REG_W_SWAP_MODE_MSK (((1U << MJPEG_REG_W_SWAP_MODE_LEN) - 1) << MJPEG_REG_W_SWAP_MODE_POS) -#define MJPEG_REG_W_SWAP_MODE_UMSK (~(((1U << MJPEG_REG_W_SWAP_MODE_LEN) - 1) << MJPEG_REG_W_SWAP_MODE_POS)) -#define MJPEG_STS_SWAP0_FULL MJPEG_STS_SWAP0_FULL -#define MJPEG_STS_SWAP0_FULL_POS (8U) -#define MJPEG_STS_SWAP0_FULL_LEN (1U) -#define MJPEG_STS_SWAP0_FULL_MSK (((1U << MJPEG_STS_SWAP0_FULL_LEN) - 1) << MJPEG_STS_SWAP0_FULL_POS) -#define MJPEG_STS_SWAP0_FULL_UMSK (~(((1U << MJPEG_STS_SWAP0_FULL_LEN) - 1) << MJPEG_STS_SWAP0_FULL_POS)) -#define MJPEG_STS_SWAP1_FULL MJPEG_STS_SWAP1_FULL -#define MJPEG_STS_SWAP1_FULL_POS (9U) -#define MJPEG_STS_SWAP1_FULL_LEN (1U) -#define MJPEG_STS_SWAP1_FULL_MSK (((1U << MJPEG_STS_SWAP1_FULL_LEN) - 1) << MJPEG_STS_SWAP1_FULL_POS) -#define MJPEG_STS_SWAP1_FULL_UMSK (~(((1U << MJPEG_STS_SWAP1_FULL_LEN) - 1) << MJPEG_STS_SWAP1_FULL_POS)) -#define MJPEG_STS_READ_SWAP_IDX MJPEG_STS_READ_SWAP_IDX -#define MJPEG_STS_READ_SWAP_IDX_POS (10U) -#define MJPEG_STS_READ_SWAP_IDX_LEN (1U) -#define MJPEG_STS_READ_SWAP_IDX_MSK (((1U << MJPEG_STS_READ_SWAP_IDX_LEN) - 1) << MJPEG_STS_READ_SWAP_IDX_POS) -#define MJPEG_STS_READ_SWAP_IDX_UMSK (~(((1U << MJPEG_STS_READ_SWAP_IDX_LEN) - 1) << MJPEG_STS_READ_SWAP_IDX_POS)) -#define MJPEG_STS_SWAP_FSTART MJPEG_STS_SWAP_FSTART -#define MJPEG_STS_SWAP_FSTART_POS (11U) -#define MJPEG_STS_SWAP_FSTART_LEN (1U) -#define MJPEG_STS_SWAP_FSTART_MSK (((1U << MJPEG_STS_SWAP_FSTART_LEN) - 1) << MJPEG_STS_SWAP_FSTART_POS) -#define MJPEG_STS_SWAP_FSTART_UMSK (~(((1U << MJPEG_STS_SWAP_FSTART_LEN) - 1) << MJPEG_STS_SWAP_FSTART_POS)) -#define MJPEG_STS_SWAP_FEND MJPEG_STS_SWAP_FEND -#define MJPEG_STS_SWAP_FEND_POS (12U) -#define MJPEG_STS_SWAP_FEND_LEN (1U) -#define MJPEG_STS_SWAP_FEND_MSK (((1U << MJPEG_STS_SWAP_FEND_LEN) - 1) << MJPEG_STS_SWAP_FEND_POS) -#define MJPEG_STS_SWAP_FEND_UMSK (~(((1U << MJPEG_STS_SWAP_FEND_LEN) - 1) << MJPEG_STS_SWAP_FEND_POS)) - -/* 0x34 : mjpeg_swap_bit_cnt */ -#define MJPEG_SWAP_BIT_CNT_OFFSET (0x34) -#define MJPEG_FRAME_SWAP_END_BIT_CNT MJPEG_FRAME_SWAP_END_BIT_CNT -#define MJPEG_FRAME_SWAP_END_BIT_CNT_POS (0U) -#define MJPEG_FRAME_SWAP_END_BIT_CNT_LEN (32U) -#define MJPEG_FRAME_SWAP_END_BIT_CNT_MSK (((1U << MJPEG_FRAME_SWAP_END_BIT_CNT_LEN) - 1) << MJPEG_FRAME_SWAP_END_BIT_CNT_POS) -#define MJPEG_FRAME_SWAP_END_BIT_CNT_UMSK (~(((1U << MJPEG_FRAME_SWAP_END_BIT_CNT_LEN) - 1) << MJPEG_FRAME_SWAP_END_BIT_CNT_POS)) - -/* 0x38 : mjpeg_yuv_mem_sw */ -#define MJPEG_YUV_MEM_SW_OFFSET (0x38) -#define MJPEG_REG_SW_KICK_HBLK MJPEG_REG_SW_KICK_HBLK -#define MJPEG_REG_SW_KICK_HBLK_POS (0U) -#define MJPEG_REG_SW_KICK_HBLK_LEN (13U) -#define MJPEG_REG_SW_KICK_HBLK_MSK (((1U << MJPEG_REG_SW_KICK_HBLK_LEN) - 1) << MJPEG_REG_SW_KICK_HBLK_POS) -#define MJPEG_REG_SW_KICK_HBLK_UMSK (~(((1U << MJPEG_REG_SW_KICK_HBLK_LEN) - 1) << MJPEG_REG_SW_KICK_HBLK_POS)) - -/* 0x40 : mjpeg_Y_frame_read_status_1 */ -#define MJPEG_Y_FRAME_READ_STATUS_1_OFFSET (0x40) -#define MJPEG_YY_MEM_HBLK_R MJPEG_YY_MEM_HBLK_R -#define MJPEG_YY_MEM_HBLK_R_POS (0U) -#define MJPEG_YY_MEM_HBLK_R_LEN (13U) -#define MJPEG_YY_MEM_HBLK_R_MSK (((1U << MJPEG_YY_MEM_HBLK_R_LEN) - 1) << MJPEG_YY_MEM_HBLK_R_POS) -#define MJPEG_YY_MEM_HBLK_R_UMSK (~(((1U << MJPEG_YY_MEM_HBLK_R_LEN) - 1) << MJPEG_YY_MEM_HBLK_R_POS)) -#define MJPEG_YY_FRM_HBLK_R MJPEG_YY_FRM_HBLK_R -#define MJPEG_YY_FRM_HBLK_R_POS (16U) -#define MJPEG_YY_FRM_HBLK_R_LEN (13U) -#define MJPEG_YY_FRM_HBLK_R_MSK (((1U << MJPEG_YY_FRM_HBLK_R_LEN) - 1) << MJPEG_YY_FRM_HBLK_R_POS) -#define MJPEG_YY_FRM_HBLK_R_UMSK (~(((1U << MJPEG_YY_FRM_HBLK_R_LEN) - 1) << MJPEG_YY_FRM_HBLK_R_POS)) - -/* 0x44 : mjpeg_Y_frame_read_status_2 */ -#define MJPEG_Y_FRAME_READ_STATUS_2_OFFSET (0x44) -#define MJPEG_YY_WBLK_R MJPEG_YY_WBLK_R -#define MJPEG_YY_WBLK_R_POS (0U) -#define MJPEG_YY_WBLK_R_LEN (13U) -#define MJPEG_YY_WBLK_R_MSK (((1U << MJPEG_YY_WBLK_R_LEN) - 1) << MJPEG_YY_WBLK_R_POS) -#define MJPEG_YY_WBLK_R_UMSK (~(((1U << MJPEG_YY_WBLK_R_LEN) - 1) << MJPEG_YY_WBLK_R_POS)) -#define MJPEG_YY_MEM_RND_R MJPEG_YY_MEM_RND_R -#define MJPEG_YY_MEM_RND_R_POS (16U) -#define MJPEG_YY_MEM_RND_R_LEN (8U) -#define MJPEG_YY_MEM_RND_R_MSK (((1U << MJPEG_YY_MEM_RND_R_LEN) - 1) << MJPEG_YY_MEM_RND_R_POS) -#define MJPEG_YY_MEM_RND_R_UMSK (~(((1U << MJPEG_YY_MEM_RND_R_LEN) - 1) << MJPEG_YY_MEM_RND_R_POS)) -#define MJPEG_YY_FRM_CNT_R MJPEG_YY_FRM_CNT_R -#define MJPEG_YY_FRM_CNT_R_POS (24U) -#define MJPEG_YY_FRM_CNT_R_LEN (8U) -#define MJPEG_YY_FRM_CNT_R_MSK (((1U << MJPEG_YY_FRM_CNT_R_LEN) - 1) << MJPEG_YY_FRM_CNT_R_POS) -#define MJPEG_YY_FRM_CNT_R_UMSK (~(((1U << MJPEG_YY_FRM_CNT_R_LEN) - 1) << MJPEG_YY_FRM_CNT_R_POS)) - -/* 0x48 : mjpeg_Y_frame_write_status */ -#define MJPEG_Y_FRAME_WRITE_STATUS_OFFSET (0x48) -#define MJPEG_YY_MEM_HBLK_W MJPEG_YY_MEM_HBLK_W -#define MJPEG_YY_MEM_HBLK_W_POS (0U) -#define MJPEG_YY_MEM_HBLK_W_LEN (13U) -#define MJPEG_YY_MEM_HBLK_W_MSK (((1U << MJPEG_YY_MEM_HBLK_W_LEN) - 1) << MJPEG_YY_MEM_HBLK_W_POS) -#define MJPEG_YY_MEM_HBLK_W_UMSK (~(((1U << MJPEG_YY_MEM_HBLK_W_LEN) - 1) << MJPEG_YY_MEM_HBLK_W_POS)) -#define MJPEG_YY_MEM_RND_W MJPEG_YY_MEM_RND_W -#define MJPEG_YY_MEM_RND_W_POS (16U) -#define MJPEG_YY_MEM_RND_W_LEN (8U) -#define MJPEG_YY_MEM_RND_W_MSK (((1U << MJPEG_YY_MEM_RND_W_LEN) - 1) << MJPEG_YY_MEM_RND_W_POS) -#define MJPEG_YY_MEM_RND_W_UMSK (~(((1U << MJPEG_YY_MEM_RND_W_LEN) - 1) << MJPEG_YY_MEM_RND_W_POS)) -#define MJPEG_YY_FRM_CNT_W MJPEG_YY_FRM_CNT_W -#define MJPEG_YY_FRM_CNT_W_POS (24U) -#define MJPEG_YY_FRM_CNT_W_LEN (8U) -#define MJPEG_YY_FRM_CNT_W_MSK (((1U << MJPEG_YY_FRM_CNT_W_LEN) - 1) << MJPEG_YY_FRM_CNT_W_POS) -#define MJPEG_YY_FRM_CNT_W_UMSK (~(((1U << MJPEG_YY_FRM_CNT_W_LEN) - 1) << MJPEG_YY_FRM_CNT_W_POS)) - -/* 0x4C : mjpeg_UV_frame_read_status_1 */ -#define MJPEG_UV_FRAME_READ_STATUS_1_OFFSET (0x4C) -#define MJPEG_UV_MEM_HBLK_R MJPEG_UV_MEM_HBLK_R -#define MJPEG_UV_MEM_HBLK_R_POS (0U) -#define MJPEG_UV_MEM_HBLK_R_LEN (13U) -#define MJPEG_UV_MEM_HBLK_R_MSK (((1U << MJPEG_UV_MEM_HBLK_R_LEN) - 1) << MJPEG_UV_MEM_HBLK_R_POS) -#define MJPEG_UV_MEM_HBLK_R_UMSK (~(((1U << MJPEG_UV_MEM_HBLK_R_LEN) - 1) << MJPEG_UV_MEM_HBLK_R_POS)) -#define MJPEG_UV_FRM_HBLK_R MJPEG_UV_FRM_HBLK_R -#define MJPEG_UV_FRM_HBLK_R_POS (16U) -#define MJPEG_UV_FRM_HBLK_R_LEN (13U) -#define MJPEG_UV_FRM_HBLK_R_MSK (((1U << MJPEG_UV_FRM_HBLK_R_LEN) - 1) << MJPEG_UV_FRM_HBLK_R_POS) -#define MJPEG_UV_FRM_HBLK_R_UMSK (~(((1U << MJPEG_UV_FRM_HBLK_R_LEN) - 1) << MJPEG_UV_FRM_HBLK_R_POS)) - -/* 0x50 : mjpeg_UV_frame_read_status_2 */ -#define MJPEG_UV_FRAME_READ_STATUS_2_OFFSET (0x50) -#define MJPEG_UV_WBLK_R MJPEG_UV_WBLK_R -#define MJPEG_UV_WBLK_R_POS (0U) -#define MJPEG_UV_WBLK_R_LEN (13U) -#define MJPEG_UV_WBLK_R_MSK (((1U << MJPEG_UV_WBLK_R_LEN) - 1) << MJPEG_UV_WBLK_R_POS) -#define MJPEG_UV_WBLK_R_UMSK (~(((1U << MJPEG_UV_WBLK_R_LEN) - 1) << MJPEG_UV_WBLK_R_POS)) -#define MJPEG_UV_MEM_RND_R MJPEG_UV_MEM_RND_R -#define MJPEG_UV_MEM_RND_R_POS (16U) -#define MJPEG_UV_MEM_RND_R_LEN (8U) -#define MJPEG_UV_MEM_RND_R_MSK (((1U << MJPEG_UV_MEM_RND_R_LEN) - 1) << MJPEG_UV_MEM_RND_R_POS) -#define MJPEG_UV_MEM_RND_R_UMSK (~(((1U << MJPEG_UV_MEM_RND_R_LEN) - 1) << MJPEG_UV_MEM_RND_R_POS)) -#define MJPEG_UV_FRM_CNT_R MJPEG_UV_FRM_CNT_R -#define MJPEG_UV_FRM_CNT_R_POS (24U) -#define MJPEG_UV_FRM_CNT_R_LEN (8U) -#define MJPEG_UV_FRM_CNT_R_MSK (((1U << MJPEG_UV_FRM_CNT_R_LEN) - 1) << MJPEG_UV_FRM_CNT_R_POS) -#define MJPEG_UV_FRM_CNT_R_UMSK (~(((1U << MJPEG_UV_FRM_CNT_R_LEN) - 1) << MJPEG_UV_FRM_CNT_R_POS)) - -/* 0x54 : mjpeg_UV_frame_write_status */ -#define MJPEG_UV_FRAME_WRITE_STATUS_OFFSET (0x54) -#define MJPEG_UV_MEM_HBLK_W MJPEG_UV_MEM_HBLK_W -#define MJPEG_UV_MEM_HBLK_W_POS (0U) -#define MJPEG_UV_MEM_HBLK_W_LEN (13U) -#define MJPEG_UV_MEM_HBLK_W_MSK (((1U << MJPEG_UV_MEM_HBLK_W_LEN) - 1) << MJPEG_UV_MEM_HBLK_W_POS) -#define MJPEG_UV_MEM_HBLK_W_UMSK (~(((1U << MJPEG_UV_MEM_HBLK_W_LEN) - 1) << MJPEG_UV_MEM_HBLK_W_POS)) -#define MJPEG_UV_MEM_RND_W MJPEG_UV_MEM_RND_W -#define MJPEG_UV_MEM_RND_W_POS (16U) -#define MJPEG_UV_MEM_RND_W_LEN (8U) -#define MJPEG_UV_MEM_RND_W_MSK (((1U << MJPEG_UV_MEM_RND_W_LEN) - 1) << MJPEG_UV_MEM_RND_W_POS) -#define MJPEG_UV_MEM_RND_W_UMSK (~(((1U << MJPEG_UV_MEM_RND_W_LEN) - 1) << MJPEG_UV_MEM_RND_W_POS)) -#define MJPEG_UV_FRM_CNT_W MJPEG_UV_FRM_CNT_W -#define MJPEG_UV_FRM_CNT_W_POS (24U) -#define MJPEG_UV_FRM_CNT_W_LEN (8U) -#define MJPEG_UV_FRM_CNT_W_MSK (((1U << MJPEG_UV_FRM_CNT_W_LEN) - 1) << MJPEG_UV_FRM_CNT_W_POS) -#define MJPEG_UV_FRM_CNT_W_UMSK (~(((1U << MJPEG_UV_FRM_CNT_W_LEN) - 1) << MJPEG_UV_FRM_CNT_W_POS)) - -/* 0x58 : mjpeg_frame_w_hblk_status */ -#define MJPEG_FRAME_W_HBLK_STATUS_OFFSET (0x58) -#define MJPEG_YY_FRM_HBLK_W MJPEG_YY_FRM_HBLK_W -#define MJPEG_YY_FRM_HBLK_W_POS (0U) -#define MJPEG_YY_FRM_HBLK_W_LEN (13U) -#define MJPEG_YY_FRM_HBLK_W_MSK (((1U << MJPEG_YY_FRM_HBLK_W_LEN) - 1) << MJPEG_YY_FRM_HBLK_W_POS) -#define MJPEG_YY_FRM_HBLK_W_UMSK (~(((1U << MJPEG_YY_FRM_HBLK_W_LEN) - 1) << MJPEG_YY_FRM_HBLK_W_POS)) -#define MJPEG_UV_FRM_HBLK_W MJPEG_UV_FRM_HBLK_W -#define MJPEG_UV_FRM_HBLK_W_POS (16U) -#define MJPEG_UV_FRM_HBLK_W_LEN (13U) -#define MJPEG_UV_FRM_HBLK_W_MSK (((1U << MJPEG_UV_FRM_HBLK_W_LEN) - 1) << MJPEG_UV_FRM_HBLK_W_POS) -#define MJPEG_UV_FRM_HBLK_W_UMSK (~(((1U << MJPEG_UV_FRM_HBLK_W_LEN) - 1) << MJPEG_UV_FRM_HBLK_W_POS)) - -/* 0x80 : mjpeg_start_addr0 */ -#define MJPEG_START_ADDR0_OFFSET (0x80) -#define MJPEG_FRAME_START_ADDR_0 MJPEG_FRAME_START_ADDR_0 -#define MJPEG_FRAME_START_ADDR_0_POS (0U) -#define MJPEG_FRAME_START_ADDR_0_LEN (32U) -#define MJPEG_FRAME_START_ADDR_0_MSK (((1U << MJPEG_FRAME_START_ADDR_0_LEN) - 1) << MJPEG_FRAME_START_ADDR_0_POS) -#define MJPEG_FRAME_START_ADDR_0_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_0_LEN) - 1) << MJPEG_FRAME_START_ADDR_0_POS)) - -/* 0x84 : mjpeg_bit_cnt0 */ -#define MJPEG_BIT_CNT0_OFFSET (0x84) -#define MJPEG_FRAME_BIT_CNT_0 MJPEG_FRAME_BIT_CNT_0 -#define MJPEG_FRAME_BIT_CNT_0_POS (0U) -#define MJPEG_FRAME_BIT_CNT_0_LEN (32U) -#define MJPEG_FRAME_BIT_CNT_0_MSK (((1U << MJPEG_FRAME_BIT_CNT_0_LEN) - 1) << MJPEG_FRAME_BIT_CNT_0_POS) -#define MJPEG_FRAME_BIT_CNT_0_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_0_LEN) - 1) << MJPEG_FRAME_BIT_CNT_0_POS)) - -/* 0x88 : mjpeg_start_addr1 */ -#define MJPEG_START_ADDR1_OFFSET (0x88) -#define MJPEG_FRAME_START_ADDR_1 MJPEG_FRAME_START_ADDR_1 -#define MJPEG_FRAME_START_ADDR_1_POS (0U) -#define MJPEG_FRAME_START_ADDR_1_LEN (32U) -#define MJPEG_FRAME_START_ADDR_1_MSK (((1U << MJPEG_FRAME_START_ADDR_1_LEN) - 1) << MJPEG_FRAME_START_ADDR_1_POS) -#define MJPEG_FRAME_START_ADDR_1_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_1_LEN) - 1) << MJPEG_FRAME_START_ADDR_1_POS)) - -/* 0x8C : mjpeg_bit_cnt1 */ -#define MJPEG_BIT_CNT1_OFFSET (0x8C) -#define MJPEG_FRAME_BIT_CNT_1 MJPEG_FRAME_BIT_CNT_1 -#define MJPEG_FRAME_BIT_CNT_1_POS (0U) -#define MJPEG_FRAME_BIT_CNT_1_LEN (32U) -#define MJPEG_FRAME_BIT_CNT_1_MSK (((1U << MJPEG_FRAME_BIT_CNT_1_LEN) - 1) << MJPEG_FRAME_BIT_CNT_1_POS) -#define MJPEG_FRAME_BIT_CNT_1_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_1_LEN) - 1) << MJPEG_FRAME_BIT_CNT_1_POS)) - -/* 0x90 : mjpeg_start_addr2 */ -#define MJPEG_START_ADDR2_OFFSET (0x90) -#define MJPEG_FRAME_START_ADDR_2 MJPEG_FRAME_START_ADDR_2 -#define MJPEG_FRAME_START_ADDR_2_POS (0U) -#define MJPEG_FRAME_START_ADDR_2_LEN (32U) -#define MJPEG_FRAME_START_ADDR_2_MSK (((1U << MJPEG_FRAME_START_ADDR_2_LEN) - 1) << MJPEG_FRAME_START_ADDR_2_POS) -#define MJPEG_FRAME_START_ADDR_2_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_2_LEN) - 1) << MJPEG_FRAME_START_ADDR_2_POS)) - -/* 0x94 : mjpeg_bit_cnt2 */ -#define MJPEG_BIT_CNT2_OFFSET (0x94) -#define MJPEG_FRAME_BIT_CNT_2 MJPEG_FRAME_BIT_CNT_2 -#define MJPEG_FRAME_BIT_CNT_2_POS (0U) -#define MJPEG_FRAME_BIT_CNT_2_LEN (32U) -#define MJPEG_FRAME_BIT_CNT_2_MSK (((1U << MJPEG_FRAME_BIT_CNT_2_LEN) - 1) << MJPEG_FRAME_BIT_CNT_2_POS) -#define MJPEG_FRAME_BIT_CNT_2_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_2_LEN) - 1) << MJPEG_FRAME_BIT_CNT_2_POS)) - -/* 0x98 : mjpeg_start_addr3 */ -#define MJPEG_START_ADDR3_OFFSET (0x98) -#define MJPEG_FRAME_START_ADDR_3 MJPEG_FRAME_START_ADDR_3 -#define MJPEG_FRAME_START_ADDR_3_POS (0U) -#define MJPEG_FRAME_START_ADDR_3_LEN (32U) -#define MJPEG_FRAME_START_ADDR_3_MSK (((1U << MJPEG_FRAME_START_ADDR_3_LEN) - 1) << MJPEG_FRAME_START_ADDR_3_POS) -#define MJPEG_FRAME_START_ADDR_3_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_3_LEN) - 1) << MJPEG_FRAME_START_ADDR_3_POS)) - -/* 0x9C : mjpeg_bit_cnt3 */ -#define MJPEG_BIT_CNT3_OFFSET (0x9C) -#define MJPEG_FRAME_BIT_CNT_3 MJPEG_FRAME_BIT_CNT_3 -#define MJPEG_FRAME_BIT_CNT_3_POS (0U) -#define MJPEG_FRAME_BIT_CNT_3_LEN (32U) -#define MJPEG_FRAME_BIT_CNT_3_MSK (((1U << MJPEG_FRAME_BIT_CNT_3_LEN) - 1) << MJPEG_FRAME_BIT_CNT_3_POS) -#define MJPEG_FRAME_BIT_CNT_3_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_3_LEN) - 1) << MJPEG_FRAME_BIT_CNT_3_POS)) - -/* 0x100 : mjpeg_q_enc */ -#define MJPEG_Q_ENC_OFFSET (0x100) -#define MJPEG_FRAME_Q_SRAM_0 MJPEG_FRAME_Q_SRAM_0 -#define MJPEG_FRAME_Q_SRAM_0_POS (0U) -#define MJPEG_FRAME_Q_SRAM_0_LEN (1U) -#define MJPEG_FRAME_Q_SRAM_0_MSK (((1U << MJPEG_FRAME_Q_SRAM_0_LEN) - 1) << MJPEG_FRAME_Q_SRAM_0_POS) -#define MJPEG_FRAME_Q_SRAM_0_UMSK (~(((1U << MJPEG_FRAME_Q_SRAM_0_LEN) - 1) << MJPEG_FRAME_Q_SRAM_0_POS)) -#define MJPEG_FRAME_Q_SRAM_1 MJPEG_FRAME_Q_SRAM_1 -#define MJPEG_FRAME_Q_SRAM_1_POS (1U) -#define MJPEG_FRAME_Q_SRAM_1_LEN (1U) -#define MJPEG_FRAME_Q_SRAM_1_MSK (((1U << MJPEG_FRAME_Q_SRAM_1_LEN) - 1) << MJPEG_FRAME_Q_SRAM_1_POS) -#define MJPEG_FRAME_Q_SRAM_1_UMSK (~(((1U << MJPEG_FRAME_Q_SRAM_1_LEN) - 1) << MJPEG_FRAME_Q_SRAM_1_POS)) -#define MJPEG_FRAME_Q_SRAM_2 MJPEG_FRAME_Q_SRAM_2 -#define MJPEG_FRAME_Q_SRAM_2_POS (2U) -#define MJPEG_FRAME_Q_SRAM_2_LEN (1U) -#define MJPEG_FRAME_Q_SRAM_2_MSK (((1U << MJPEG_FRAME_Q_SRAM_2_LEN) - 1) << MJPEG_FRAME_Q_SRAM_2_POS) -#define MJPEG_FRAME_Q_SRAM_2_UMSK (~(((1U << MJPEG_FRAME_Q_SRAM_2_LEN) - 1) << MJPEG_FRAME_Q_SRAM_2_POS)) -#define MJPEG_FRAME_Q_SRAM_3 MJPEG_FRAME_Q_SRAM_3 -#define MJPEG_FRAME_Q_SRAM_3_POS (3U) -#define MJPEG_FRAME_Q_SRAM_3_LEN (1U) -#define MJPEG_FRAME_Q_SRAM_3_MSK (((1U << MJPEG_FRAME_Q_SRAM_3_LEN) - 1) << MJPEG_FRAME_Q_SRAM_3_POS) -#define MJPEG_FRAME_Q_SRAM_3_UMSK (~(((1U << MJPEG_FRAME_Q_SRAM_3_LEN) - 1) << MJPEG_FRAME_Q_SRAM_3_POS)) -#define MJPEG_REG_Q_SRAM_SW MJPEG_REG_Q_SRAM_SW -#define MJPEG_REG_Q_SRAM_SW_POS (24U) -#define MJPEG_REG_Q_SRAM_SW_LEN (1U) -#define MJPEG_REG_Q_SRAM_SW_MSK (((1U << MJPEG_REG_Q_SRAM_SW_LEN) - 1) << MJPEG_REG_Q_SRAM_SW_POS) -#define MJPEG_REG_Q_SRAM_SW_UMSK (~(((1U << MJPEG_REG_Q_SRAM_SW_LEN) - 1) << MJPEG_REG_Q_SRAM_SW_POS)) -#define MJPEG_STS_Q_SRAM_ENC MJPEG_STS_Q_SRAM_ENC -#define MJPEG_STS_Q_SRAM_ENC_POS (25U) -#define MJPEG_STS_Q_SRAM_ENC_LEN (1U) -#define MJPEG_STS_Q_SRAM_ENC_MSK (((1U << MJPEG_STS_Q_SRAM_ENC_LEN) - 1) << MJPEG_STS_Q_SRAM_ENC_POS) -#define MJPEG_STS_Q_SRAM_ENC_UMSK (~(((1U << MJPEG_STS_Q_SRAM_ENC_LEN) - 1) << MJPEG_STS_Q_SRAM_ENC_POS)) - -/* 0x110 : mjpeg_frame_id_10 */ -#define MJPEG_FRAME_ID_10_OFFSET (0x110) -#define MJPEG_FRAME_ID_0 MJPEG_FRAME_ID_0 -#define MJPEG_FRAME_ID_0_POS (0U) -#define MJPEG_FRAME_ID_0_LEN (16U) -#define MJPEG_FRAME_ID_0_MSK (((1U << MJPEG_FRAME_ID_0_LEN) - 1) << MJPEG_FRAME_ID_0_POS) -#define MJPEG_FRAME_ID_0_UMSK (~(((1U << MJPEG_FRAME_ID_0_LEN) - 1) << MJPEG_FRAME_ID_0_POS)) -#define MJPEG_FRAME_ID_1 MJPEG_FRAME_ID_1 -#define MJPEG_FRAME_ID_1_POS (16U) -#define MJPEG_FRAME_ID_1_LEN (16U) -#define MJPEG_FRAME_ID_1_MSK (((1U << MJPEG_FRAME_ID_1_LEN) - 1) << MJPEG_FRAME_ID_1_POS) -#define MJPEG_FRAME_ID_1_UMSK (~(((1U << MJPEG_FRAME_ID_1_LEN) - 1) << MJPEG_FRAME_ID_1_POS)) - -/* 0x114 : mjpeg_frame_id_32 */ -#define MJPEG_FRAME_ID_32_OFFSET (0x114) -#define MJPEG_FRAME_ID_2 MJPEG_FRAME_ID_2 -#define MJPEG_FRAME_ID_2_POS (0U) -#define MJPEG_FRAME_ID_2_LEN (16U) -#define MJPEG_FRAME_ID_2_MSK (((1U << MJPEG_FRAME_ID_2_LEN) - 1) << MJPEG_FRAME_ID_2_POS) -#define MJPEG_FRAME_ID_2_UMSK (~(((1U << MJPEG_FRAME_ID_2_LEN) - 1) << MJPEG_FRAME_ID_2_POS)) -#define MJPEG_FRAME_ID_3 MJPEG_FRAME_ID_3 -#define MJPEG_FRAME_ID_3_POS (16U) -#define MJPEG_FRAME_ID_3_LEN (16U) -#define MJPEG_FRAME_ID_3_MSK (((1U << MJPEG_FRAME_ID_3_LEN) - 1) << MJPEG_FRAME_ID_3_POS) -#define MJPEG_FRAME_ID_3_UMSK (~(((1U << MJPEG_FRAME_ID_3_LEN) - 1) << MJPEG_FRAME_ID_3_POS)) - -/* 0x1F0 : mjpeg_debug */ -#define MJPEG_DEBUG_OFFSET (0x1F0) -#define MJPEG_REG_MJPEG_DBG_EN MJPEG_REG_MJPEG_DBG_EN -#define MJPEG_REG_MJPEG_DBG_EN_POS (0U) -#define MJPEG_REG_MJPEG_DBG_EN_LEN (1U) -#define MJPEG_REG_MJPEG_DBG_EN_MSK (((1U << MJPEG_REG_MJPEG_DBG_EN_LEN) - 1) << MJPEG_REG_MJPEG_DBG_EN_POS) -#define MJPEG_REG_MJPEG_DBG_EN_UMSK (~(((1U << MJPEG_REG_MJPEG_DBG_EN_LEN) - 1) << MJPEG_REG_MJPEG_DBG_EN_POS)) -#define MJPEG_REG_MJPEG_DBG_SEL MJPEG_REG_MJPEG_DBG_SEL -#define MJPEG_REG_MJPEG_DBG_SEL_POS (4U) -#define MJPEG_REG_MJPEG_DBG_SEL_LEN (4U) -#define MJPEG_REG_MJPEG_DBG_SEL_MSK (((1U << MJPEG_REG_MJPEG_DBG_SEL_LEN) - 1) << MJPEG_REG_MJPEG_DBG_SEL_POS) -#define MJPEG_REG_MJPEG_DBG_SEL_UMSK (~(((1U << MJPEG_REG_MJPEG_DBG_SEL_LEN) - 1) << MJPEG_REG_MJPEG_DBG_SEL_POS)) -#define MJPEG_REG_ID_LATCH_HBLK MJPEG_REG_ID_LATCH_HBLK -#define MJPEG_REG_ID_LATCH_HBLK_POS (8U) -#define MJPEG_REG_ID_LATCH_HBLK_LEN (4U) -#define MJPEG_REG_ID_LATCH_HBLK_MSK (((1U << MJPEG_REG_ID_LATCH_HBLK_LEN) - 1) << MJPEG_REG_ID_LATCH_HBLK_POS) -#define MJPEG_REG_ID_LATCH_HBLK_UMSK (~(((1U << MJPEG_REG_ID_LATCH_HBLK_LEN) - 1) << MJPEG_REG_ID_LATCH_HBLK_POS)) - -/* 0x1FC : mjpeg_dummy_reg */ -#define MJPEG_DUMMY_REG_OFFSET (0x1FC) -#define MJPEG_DUMMY_REG MJPEG_DUMMY_REG -#define MJPEG_DUMMY_REG_POS (0U) -#define MJPEG_DUMMY_REG_LEN (32U) -#define MJPEG_DUMMY_REG_MSK (((1U << MJPEG_DUMMY_REG_LEN) - 1) << MJPEG_DUMMY_REG_POS) -#define MJPEG_DUMMY_REG_UMSK (~(((1U << MJPEG_DUMMY_REG_LEN) - 1) << MJPEG_DUMMY_REG_POS)) - -struct mjpeg_reg { - /* 0x0 : mjpeg_control_1 */ - union { - struct { - uint32_t reg_mjpeg_enable : 1; /* [ 0], r/w, 0x0 */ - uint32_t reg_mjpeg_bit_order : 1; /* [ 1], r/w, 0x1 */ - uint32_t reg_order_u_even : 1; /* [ 2], r/w, 0x1 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t reg_last_hf_wblk_dmy : 1; /* [ 4], r/w, 0x0 */ - uint32_t reg_last_hf_hblk_dmy : 1; /* [ 5], r/w, 0x0 */ - uint32_t reg_reflect_dmy : 1; /* [ 6], r/w, 0x0 */ - uint32_t reg_read_fwrap : 1; /* [ 7], r/w, 0x1 */ - uint32_t reg_w_xlen : 3; /* [10: 8], r/w, 0x3 */ - uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */ - uint32_t reg_yuv_mode : 2; /* [13:12], r/w, 0x0 */ - uint32_t reserved_14_23 : 10; /* [23:14], rsvd, 0x0 */ - uint32_t reg_mjpeg_hw_frame : 6; /* [29:24], r/w, 0x0 */ - uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_control_1; - - /* 0x4 : mjpeg_control_2 */ - union { - struct { - uint32_t reg_sw_frame : 5; /* [ 4: 0], r/w, 0x0 */ - uint32_t reserved_5 : 1; /* [ 5], rsvd, 0x0 */ - uint32_t reg_sw_kick : 1; /* [ 6], w1p, 0x0 */ - uint32_t reg_sw_kick_mode : 1; /* [ 7], r/w, 0x0 */ - uint32_t reg_mjpeg_sw_mode : 1; /* [ 8], r/w, 0x0 */ - uint32_t reg_mjpeg_sw_run : 1; /* [ 9], r/w, 0x0 */ - uint32_t reg_yy_dvp2axi_sel : 3; /* [12:10], r/w, 0x0 */ - uint32_t reg_uv_dvp2axi_sel : 3; /* [15:13], r/w, 0x1 */ - uint32_t reg_mjpeg_wait_cycle : 16; /* [31:16], r/w, 0x100 */ - } BF; - uint32_t WORD; - } mjpeg_control_2; - - /* 0x08 : mjpeg_yy_frame_addr */ - union { - struct { - uint32_t reg_yy_addr_start : 32; /* [31: 0], r/w, 0x80000000 */ - } BF; - uint32_t WORD; - } mjpeg_yy_frame_addr; - - /* 0x0C : mjpeg_uv_frame_addr */ - union { - struct { - uint32_t reg_uv_addr_start : 32; /* [31: 0], r/w, 0x80000000 */ - } BF; - uint32_t WORD; - } mjpeg_uv_frame_addr; - - /* 0x10 : mjpeg_yuv_mem */ - union { - struct { - uint32_t reg_yy_mem_hblk : 13; /* [12: 0], r/w, 0x2 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t reg_uv_mem_hblk : 13; /* [28:16], r/w, 0x2 */ - uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_yuv_mem; - - /* 0x14 : jpeg_frame_addr */ - union { - struct { - uint32_t reg_w_addr_start : 32; /* [31: 0], r/w, 0x80400000 */ - } BF; - uint32_t WORD; - } jpeg_frame_addr; - - /* 0x18 : jpeg_store_memory */ - union { - struct { - uint32_t reg_w_burst_cnt : 32; /* [31: 0], r/w, 0x4000 */ - } BF; - uint32_t WORD; - } jpeg_store_memory; - - /* 0x1C : mjpeg_control_3 */ - union { - struct { - uint32_t reg_int_normal_en : 1; /* [ 0], r/w, 0x1 */ - uint32_t reg_int_cam_en : 1; /* [ 1], r/w, 0x1 */ - uint32_t reg_int_mem_en : 1; /* [ 2], r/w, 0x0 */ - uint32_t reg_int_frame_en : 1; /* [ 3], r/w, 0x0 */ - uint32_t sts_normal_int : 1; /* [ 4], r, 0x0 */ - uint32_t sts_cam_int : 1; /* [ 5], r, 0x0 */ - uint32_t sts_mem_int : 1; /* [ 6], r, 0x0 */ - uint32_t sts_frame_int : 1; /* [ 7], r, 0x0 */ - uint32_t mjpeg_idle : 1; /* [ 8], r, 0x1 */ - uint32_t mjpeg_func : 1; /* [ 9], r, 0x0 */ - uint32_t mjpeg_wait : 1; /* [ 10], r, 0x0 */ - uint32_t mjpeg_flsh : 1; /* [ 11], r, 0x0 */ - uint32_t mjpeg_mans : 1; /* [ 12], r, 0x0 */ - uint32_t mjpeg_manf : 1; /* [ 13], r, 0x0 */ - uint32_t axi_read_idle : 1; /* [ 14], r, 0x0 */ - uint32_t axi_write_idle : 1; /* [ 15], r, 0x0 */ - uint32_t reg_frame_cnt_trgr_int : 5; /* [20:16], r/w, 0x0 */ - uint32_t reg_int_idle_en : 1; /* [ 21], r/w, 0x0 */ - uint32_t sts_idle_int : 1; /* [ 22], r, 0x0 */ - uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */ - uint32_t frame_valid_cnt : 5; /* [28:24], r, 0x0 */ - uint32_t reg_int_swap_en : 1; /* [ 29], r/w, 0x0 */ - uint32_t sts_swap_int : 1; /* [ 30], r, 0x0 */ - uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_control_3; - - /* 0x20 : mjpeg_frame_fifo_pop */ - union { - struct { - uint32_t rfifo_pop : 1; /* [ 0], w1p, 0x0 */ - uint32_t reg_w_swap_clr : 1; /* [ 1], w1p, 0x0 */ - uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ - uint32_t reg_int_normal_clr : 1; /* [ 8], w1p, 0x0 */ - uint32_t reg_int_cam_clr : 1; /* [ 9], w1p, 0x0 */ - uint32_t reg_int_mem_clr : 1; /* [ 10], w1p, 0x0 */ - uint32_t reg_int_frame_clr : 1; /* [ 11], w1p, 0x0 */ - uint32_t reg_int_idle_clr : 1; /* [ 12], w1p, 0x0 */ - uint32_t reg_int_swap_clr : 1; /* [ 13], w1p, 0x0 */ - uint32_t reserved_14_31 : 18; /* [31:14], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_frame_fifo_pop; - - /* 0x24 : mjpeg_frame_size */ - union { - struct { - uint32_t reg_frame_wblk : 12; /* [11: 0], r/w, 0xf */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_frame_hblk : 12; /* [27:16], r/w, 0x14 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_frame_size; - - /* 0x28 : mjpeg_header_byte */ - union { - struct { - uint32_t reg_head_byte : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_tail_exp : 1; /* [ 16], r/w, 0x0 */ - uint32_t reserved_17_23 : 7; /* [23:17], rsvd, 0x0 */ - uint32_t reg_y0_order : 2; /* [25:24], r/w, 0x0 */ - uint32_t reg_u0_order : 2; /* [27:26], r/w, 0x1 */ - uint32_t reg_y1_order : 2; /* [29:28], r/w, 0x2 */ - uint32_t reg_v0_order : 2; /* [31:30], r/w, 0x3 */ - } BF; - uint32_t WORD; - } mjpeg_header_byte; - - /* 0x2c reserved */ - uint8_t RESERVED0x2c[4]; - - /* 0x30 : mjpeg_swap_mode */ - union { - struct { - uint32_t reg_w_swap_mode : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_7 : 7; /* [ 7: 1], rsvd, 0x0 */ - uint32_t sts_swap0_full : 1; /* [ 8], r, 0x0 */ - uint32_t sts_swap1_full : 1; /* [ 9], r, 0x0 */ - uint32_t sts_read_swap_idx : 1; /* [ 10], r, 0x0 */ - uint32_t sts_swap_fstart : 1; /* [ 11], r, 0x0 */ - uint32_t sts_swap_fend : 1; /* [ 12], r, 0x0 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_swap_mode; - - /* 0x34 : mjpeg_swap_bit_cnt */ - union { - struct { - uint32_t frame_swap_end_bit_cnt : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_swap_bit_cnt; - - /* 0x38 : mjpeg_yuv_mem_sw */ - union { - struct { - uint32_t reg_sw_kick_hblk : 13; /* [12: 0], r/w, 0x2 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_yuv_mem_sw; - - /* 0x3c reserved */ - uint8_t RESERVED0x3c[4]; - - /* 0x40 : mjpeg_Y_frame_read_status_1 */ - union { - struct { - uint32_t yy_mem_hblk_r : 13; /* [12: 0], r, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t yy_frm_hblk_r : 13; /* [28:16], r, 0x0 */ - uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_Y_frame_read_status_1; - - /* 0x44 : mjpeg_Y_frame_read_status_2 */ - union { - struct { - uint32_t yy_wblk_r : 13; /* [12: 0], r, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t yy_mem_rnd_r : 8; /* [23:16], r, 0x0 */ - uint32_t yy_frm_cnt_r : 8; /* [31:24], r, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_Y_frame_read_status_2; - - /* 0x48 : mjpeg_Y_frame_write_status */ - union { - struct { - uint32_t yy_mem_hblk_w : 13; /* [12: 0], r, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t yy_mem_rnd_w : 8; /* [23:16], r, 0x0 */ - uint32_t yy_frm_cnt_w : 8; /* [31:24], r, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_Y_frame_write_status; - - /* 0x4C : mjpeg_UV_frame_read_status_1 */ - union { - struct { - uint32_t uv_mem_hblk_r : 13; /* [12: 0], r, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t uv_frm_hblk_r : 13; /* [28:16], r, 0x0 */ - uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_UV_frame_read_status_1; - - /* 0x50 : mjpeg_UV_frame_read_status_2 */ - union { - struct { - uint32_t uv_wblk_r : 13; /* [12: 0], r, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t uv_mem_rnd_r : 8; /* [23:16], r, 0x0 */ - uint32_t uv_frm_cnt_r : 8; /* [31:24], r, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_UV_frame_read_status_2; - - /* 0x54 : mjpeg_UV_frame_write_status */ - union { - struct { - uint32_t uv_mem_hblk_w : 13; /* [12: 0], r, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t uv_mem_rnd_w : 8; /* [23:16], r, 0x0 */ - uint32_t uv_frm_cnt_w : 8; /* [31:24], r, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_UV_frame_write_status; - - /* 0x58 : mjpeg_frame_w_hblk_status */ - union { - struct { - uint32_t yy_frm_hblk_w : 13; /* [12: 0], r, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t uv_frm_hblk_w : 13; /* [28:16], r, 0x0 */ - uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_frame_w_hblk_status; - - /* 0x5c reserved */ - uint8_t RESERVED0x5c[36]; - - /* 0x80 : mjpeg_start_addr0 */ - union { - struct { - uint32_t frame_start_addr_0 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_start_addr0; - - /* 0x84 : mjpeg_bit_cnt0 */ - union { - struct { - uint32_t frame_bit_cnt_0 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_bit_cnt0; - - /* 0x88 : mjpeg_start_addr1 */ - union { - struct { - uint32_t frame_start_addr_1 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_start_addr1; - - /* 0x8C : mjpeg_bit_cnt1 */ - union { - struct { - uint32_t frame_bit_cnt_1 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_bit_cnt1; - - /* 0x90 : mjpeg_start_addr2 */ - union { - struct { - uint32_t frame_start_addr_2 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_start_addr2; - - /* 0x94 : mjpeg_bit_cnt2 */ - union { - struct { - uint32_t frame_bit_cnt_2 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_bit_cnt2; - - /* 0x98 : mjpeg_start_addr3 */ - union { - struct { - uint32_t frame_start_addr_3 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_start_addr3; - - /* 0x9C : mjpeg_bit_cnt3 */ - union { - struct { - uint32_t frame_bit_cnt_3 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_bit_cnt3; - - /* 0xa0 reserved */ - uint8_t RESERVED0xa0[96]; - - /* 0x100 : mjpeg_q_enc */ - union { - struct { - uint32_t frame_q_sram_0 : 1; /* [ 0], r, 0x0 */ - uint32_t frame_q_sram_1 : 1; /* [ 1], r, 0x0 */ - uint32_t frame_q_sram_2 : 1; /* [ 2], r, 0x0 */ - uint32_t frame_q_sram_3 : 1; /* [ 3], r, 0x0 */ - uint32_t reserved_4_23 : 20; /* [23: 4], rsvd, 0x0 */ - uint32_t reg_q_sram_sw : 1; /* [ 24], w1p, 0x0 */ - uint32_t sts_q_sram_enc : 1; /* [ 25], r, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_enc; - - /* 0x104 reserved */ - uint8_t RESERVED0x104[12]; - - /* 0x110 : mjpeg_frame_id_10 */ - union { - struct { - uint32_t frame_id_0 : 16; /* [15: 0], r, 0x0 */ - uint32_t frame_id_1 : 16; /* [31:16], r, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_frame_id_10; - - /* 0x114 : mjpeg_frame_id_32 */ - union { - struct { - uint32_t frame_id_2 : 16; /* [15: 0], r, 0x0 */ - uint32_t frame_id_3 : 16; /* [31:16], r, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_frame_id_32; - - /* 0x118 reserved */ - uint8_t RESERVED0x118[216]; - - /* 0x1F0 : mjpeg_debug */ - union { - struct { - uint32_t reg_mjpeg_dbg_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ - uint32_t reg_mjpeg_dbg_sel : 4; /* [ 7: 4], r/w, 0x0 */ - uint32_t reg_id_latch_hblk : 4; /* [11: 8], r/w, 0x1 */ - uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_debug; - - /* 0x1f4 reserved */ - uint8_t RESERVED0x1f4[8]; - - /* 0x1FC : mjpeg_dummy_reg */ - union { - struct { - uint32_t mjpeg_dummy_reg : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_dummy_reg; -}; - -typedef volatile struct mjpeg_reg mjpeg_reg_t; - -#endif /* __MJPEG_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/osd_blend_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/osd_blend_reg.h deleted file mode 100644 index 89d54af045..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/osd_blend_reg.h +++ /dev/null @@ -1,500 +0,0 @@ -/** - ****************************************************************************** - * @file osd_blend_reg.h - * @version V1.0 - * @date 2021-06-28 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __OSD_BLEND_REG_H__ -#define __OSD_BLEND_REG_H__ - -#include "bl808.h" - -/* 0x0 : obnd_layer_xconfig */ -#define OSD_BLEND_OBND_LAYER_XCONFIG_OFFSET (0x0) -#define OSD_BLEND_OBND_X_MIN OSD_BLEND_OBND_X_MIN -#define OSD_BLEND_OBND_X_MIN_POS (0U) -#define OSD_BLEND_OBND_X_MIN_LEN (11U) -#define OSD_BLEND_OBND_X_MIN_MSK (((1U << OSD_BLEND_OBND_X_MIN_LEN) - 1) << OSD_BLEND_OBND_X_MIN_POS) -#define OSD_BLEND_OBND_X_MIN_UMSK (~(((1U << OSD_BLEND_OBND_X_MIN_LEN) - 1) << OSD_BLEND_OBND_X_MIN_POS)) -#define OSD_BLEND_OBND_X_MAX OSD_BLEND_OBND_X_MAX -#define OSD_BLEND_OBND_X_MAX_POS (16U) -#define OSD_BLEND_OBND_X_MAX_LEN (11U) -#define OSD_BLEND_OBND_X_MAX_MSK (((1U << OSD_BLEND_OBND_X_MAX_LEN) - 1) << OSD_BLEND_OBND_X_MAX_POS) -#define OSD_BLEND_OBND_X_MAX_UMSK (~(((1U << OSD_BLEND_OBND_X_MAX_LEN) - 1) << OSD_BLEND_OBND_X_MAX_POS)) - -/* 0x4 : obnd_layer_yconfig */ -#define OSD_BLEND_OBND_LAYER_YCONFIG_OFFSET (0x4) -#define OSD_BLEND_OBND_Y_MIN OSD_BLEND_OBND_Y_MIN -#define OSD_BLEND_OBND_Y_MIN_POS (0U) -#define OSD_BLEND_OBND_Y_MIN_LEN (11U) -#define OSD_BLEND_OBND_Y_MIN_MSK (((1U << OSD_BLEND_OBND_Y_MIN_LEN) - 1) << OSD_BLEND_OBND_Y_MIN_POS) -#define OSD_BLEND_OBND_Y_MIN_UMSK (~(((1U << OSD_BLEND_OBND_Y_MIN_LEN) - 1) << OSD_BLEND_OBND_Y_MIN_POS)) -#define OSD_BLEND_OBND_Y_MAX OSD_BLEND_OBND_Y_MAX -#define OSD_BLEND_OBND_Y_MAX_POS (16U) -#define OSD_BLEND_OBND_Y_MAX_LEN (11U) -#define OSD_BLEND_OBND_Y_MAX_MSK (((1U << OSD_BLEND_OBND_Y_MAX_LEN) - 1) << OSD_BLEND_OBND_Y_MAX_POS) -#define OSD_BLEND_OBND_Y_MAX_UMSK (~(((1U << OSD_BLEND_OBND_Y_MAX_LEN) - 1) << OSD_BLEND_OBND_Y_MAX_POS)) - -/* 0x8 : obnd_mem_config0 */ -#define OSD_BLEND_OBND_MEM_CONFIG0_OFFSET (0x8) -#define OSD_BLEND_OBND_FORCE_SH OSD_BLEND_OBND_FORCE_SH -#define OSD_BLEND_OBND_FORCE_SH_POS (0U) -#define OSD_BLEND_OBND_FORCE_SH_LEN (1U) -#define OSD_BLEND_OBND_FORCE_SH_MSK (((1U << OSD_BLEND_OBND_FORCE_SH_LEN) - 1) << OSD_BLEND_OBND_FORCE_SH_POS) -#define OSD_BLEND_OBND_FORCE_SH_UMSK (~(((1U << OSD_BLEND_OBND_FORCE_SH_LEN) - 1) << OSD_BLEND_OBND_FORCE_SH_POS)) -#define OSD_BLEND_OBND_LAYER_EN OSD_BLEND_OBND_LAYER_EN -#define OSD_BLEND_OBND_LAYER_EN_POS (15U) -#define OSD_BLEND_OBND_LAYER_EN_LEN (1U) -#define OSD_BLEND_OBND_LAYER_EN_MSK (((1U << OSD_BLEND_OBND_LAYER_EN_LEN) - 1) << OSD_BLEND_OBND_LAYER_EN_POS) -#define OSD_BLEND_OBND_LAYER_EN_UMSK (~(((1U << OSD_BLEND_OBND_LAYER_EN_LEN) - 1) << OSD_BLEND_OBND_LAYER_EN_POS)) - -/* 0xC : obnd_mem_config1 */ -#define OSD_BLEND_OBND_MEM_CONFIG1_OFFSET (0xC) -#define OSD_BLEND_OBND_MEM_ADDR OSD_BLEND_OBND_MEM_ADDR -#define OSD_BLEND_OBND_MEM_ADDR_POS (0U) -#define OSD_BLEND_OBND_MEM_ADDR_LEN (32U) -#define OSD_BLEND_OBND_MEM_ADDR_MSK (((1U << OSD_BLEND_OBND_MEM_ADDR_LEN) - 1) << OSD_BLEND_OBND_MEM_ADDR_POS) -#define OSD_BLEND_OBND_MEM_ADDR_UMSK (~(((1U << OSD_BLEND_OBND_MEM_ADDR_LEN) - 1) << OSD_BLEND_OBND_MEM_ADDR_POS)) - -/* 0x10 : obnd_mem_config2 */ -#define OSD_BLEND_OBND_MEM_CONFIG2_OFFSET (0x10) -#define OSD_BLEND_OBND_MEM_DW_CNT OSD_BLEND_OBND_MEM_DW_CNT -#define OSD_BLEND_OBND_MEM_DW_CNT_POS (0U) -#define OSD_BLEND_OBND_MEM_DW_CNT_LEN (32U) -#define OSD_BLEND_OBND_MEM_DW_CNT_MSK (((1U << OSD_BLEND_OBND_MEM_DW_CNT_LEN) - 1) << OSD_BLEND_OBND_MEM_DW_CNT_POS) -#define OSD_BLEND_OBND_MEM_DW_CNT_UMSK (~(((1U << OSD_BLEND_OBND_MEM_DW_CNT_LEN) - 1) << OSD_BLEND_OBND_MEM_DW_CNT_POS)) - -/* 0x14 : obnd_layer_config0 */ -#define OSD_BLEND_OBND_LAYER_CONFIG0_OFFSET (0x14) -#define OSD_BLEND_OBND_COLOR_FORMAT OSD_BLEND_OBND_COLOR_FORMAT -#define OSD_BLEND_OBND_COLOR_FORMAT_POS (0U) -#define OSD_BLEND_OBND_COLOR_FORMAT_LEN (5U) -#define OSD_BLEND_OBND_COLOR_FORMAT_MSK (((1U << OSD_BLEND_OBND_COLOR_FORMAT_LEN) - 1) << OSD_BLEND_OBND_COLOR_FORMAT_POS) -#define OSD_BLEND_OBND_COLOR_FORMAT_UMSK (~(((1U << OSD_BLEND_OBND_COLOR_FORMAT_LEN) - 1) << OSD_BLEND_OBND_COLOR_FORMAT_POS)) -#define OSD_BLEND_OBND_ORDER_A OSD_BLEND_OBND_ORDER_A -#define OSD_BLEND_OBND_ORDER_A_POS (8U) -#define OSD_BLEND_OBND_ORDER_A_LEN (2U) -#define OSD_BLEND_OBND_ORDER_A_MSK (((1U << OSD_BLEND_OBND_ORDER_A_LEN) - 1) << OSD_BLEND_OBND_ORDER_A_POS) -#define OSD_BLEND_OBND_ORDER_A_UMSK (~(((1U << OSD_BLEND_OBND_ORDER_A_LEN) - 1) << OSD_BLEND_OBND_ORDER_A_POS)) -#define OSD_BLEND_OBND_ORDER_RV OSD_BLEND_OBND_ORDER_RV -#define OSD_BLEND_OBND_ORDER_RV_POS (10U) -#define OSD_BLEND_OBND_ORDER_RV_LEN (2U) -#define OSD_BLEND_OBND_ORDER_RV_MSK (((1U << OSD_BLEND_OBND_ORDER_RV_LEN) - 1) << OSD_BLEND_OBND_ORDER_RV_POS) -#define OSD_BLEND_OBND_ORDER_RV_UMSK (~(((1U << OSD_BLEND_OBND_ORDER_RV_LEN) - 1) << OSD_BLEND_OBND_ORDER_RV_POS)) -#define OSD_BLEND_OBND_ORDER_GY OSD_BLEND_OBND_ORDER_GY -#define OSD_BLEND_OBND_ORDER_GY_POS (12U) -#define OSD_BLEND_OBND_ORDER_GY_LEN (2U) -#define OSD_BLEND_OBND_ORDER_GY_MSK (((1U << OSD_BLEND_OBND_ORDER_GY_LEN) - 1) << OSD_BLEND_OBND_ORDER_GY_POS) -#define OSD_BLEND_OBND_ORDER_GY_UMSK (~(((1U << OSD_BLEND_OBND_ORDER_GY_LEN) - 1) << OSD_BLEND_OBND_ORDER_GY_POS)) -#define OSD_BLEND_OBND_ORDER_BU OSD_BLEND_OBND_ORDER_BU -#define OSD_BLEND_OBND_ORDER_BU_POS (14U) -#define OSD_BLEND_OBND_ORDER_BU_LEN (2U) -#define OSD_BLEND_OBND_ORDER_BU_MSK (((1U << OSD_BLEND_OBND_ORDER_BU_LEN) - 1) << OSD_BLEND_OBND_ORDER_BU_POS) -#define OSD_BLEND_OBND_ORDER_BU_UMSK (~(((1U << OSD_BLEND_OBND_ORDER_BU_LEN) - 1) << OSD_BLEND_OBND_ORDER_BU_POS)) -#define OSD_BLEND_OBND_GLOBAL_A_EN OSD_BLEND_OBND_GLOBAL_A_EN -#define OSD_BLEND_OBND_GLOBAL_A_EN_POS (16U) -#define OSD_BLEND_OBND_GLOBAL_A_EN_LEN (1U) -#define OSD_BLEND_OBND_GLOBAL_A_EN_MSK (((1U << OSD_BLEND_OBND_GLOBAL_A_EN_LEN) - 1) << OSD_BLEND_OBND_GLOBAL_A_EN_POS) -#define OSD_BLEND_OBND_GLOBAL_A_EN_UMSK (~(((1U << OSD_BLEND_OBND_GLOBAL_A_EN_LEN) - 1) << OSD_BLEND_OBND_GLOBAL_A_EN_POS)) -#define OSD_BLEND_OBND_GLOBAL_A OSD_BLEND_OBND_GLOBAL_A -#define OSD_BLEND_OBND_GLOBAL_A_POS (24U) -#define OSD_BLEND_OBND_GLOBAL_A_LEN (8U) -#define OSD_BLEND_OBND_GLOBAL_A_MSK (((1U << OSD_BLEND_OBND_GLOBAL_A_LEN) - 1) << OSD_BLEND_OBND_GLOBAL_A_POS) -#define OSD_BLEND_OBND_GLOBAL_A_UMSK (~(((1U << OSD_BLEND_OBND_GLOBAL_A_LEN) - 1) << OSD_BLEND_OBND_GLOBAL_A_POS)) - -/* 0x18 : obnd_layer_config1 */ -#define OSD_BLEND_OBND_LAYER_CONFIG1_OFFSET (0x18) -#define OSD_BLEND_OBND_GLOBAL_COLOR_EN OSD_BLEND_OBND_GLOBAL_COLOR_EN -#define OSD_BLEND_OBND_GLOBAL_COLOR_EN_POS (0U) -#define OSD_BLEND_OBND_GLOBAL_COLOR_EN_LEN (1U) -#define OSD_BLEND_OBND_GLOBAL_COLOR_EN_MSK (((1U << OSD_BLEND_OBND_GLOBAL_COLOR_EN_LEN) - 1) << OSD_BLEND_OBND_GLOBAL_COLOR_EN_POS) -#define OSD_BLEND_OBND_GLOBAL_COLOR_EN_UMSK (~(((1U << OSD_BLEND_OBND_GLOBAL_COLOR_EN_LEN) - 1) << OSD_BLEND_OBND_GLOBAL_COLOR_EN_POS)) -#define OSD_BLEND_OBND_GLOBAL_RV OSD_BLEND_OBND_GLOBAL_RV -#define OSD_BLEND_OBND_GLOBAL_RV_POS (8U) -#define OSD_BLEND_OBND_GLOBAL_RV_LEN (8U) -#define OSD_BLEND_OBND_GLOBAL_RV_MSK (((1U << OSD_BLEND_OBND_GLOBAL_RV_LEN) - 1) << OSD_BLEND_OBND_GLOBAL_RV_POS) -#define OSD_BLEND_OBND_GLOBAL_RV_UMSK (~(((1U << OSD_BLEND_OBND_GLOBAL_RV_LEN) - 1) << OSD_BLEND_OBND_GLOBAL_RV_POS)) -#define OSD_BLEND_OBND_GLOBAL_GY OSD_BLEND_OBND_GLOBAL_GY -#define OSD_BLEND_OBND_GLOBAL_GY_POS (16U) -#define OSD_BLEND_OBND_GLOBAL_GY_LEN (8U) -#define OSD_BLEND_OBND_GLOBAL_GY_MSK (((1U << OSD_BLEND_OBND_GLOBAL_GY_LEN) - 1) << OSD_BLEND_OBND_GLOBAL_GY_POS) -#define OSD_BLEND_OBND_GLOBAL_GY_UMSK (~(((1U << OSD_BLEND_OBND_GLOBAL_GY_LEN) - 1) << OSD_BLEND_OBND_GLOBAL_GY_POS)) -#define OSD_BLEND_OBND_GLOBAL_BU OSD_BLEND_OBND_GLOBAL_BU -#define OSD_BLEND_OBND_GLOBAL_BU_POS (24U) -#define OSD_BLEND_OBND_GLOBAL_BU_LEN (8U) -#define OSD_BLEND_OBND_GLOBAL_BU_MSK (((1U << OSD_BLEND_OBND_GLOBAL_BU_LEN) - 1) << OSD_BLEND_OBND_GLOBAL_BU_POS) -#define OSD_BLEND_OBND_GLOBAL_BU_UMSK (~(((1U << OSD_BLEND_OBND_GLOBAL_BU_LEN) - 1) << OSD_BLEND_OBND_GLOBAL_BU_POS)) - -/* 0x1C : obnd_layer_config2 */ -#define OSD_BLEND_OBND_LAYER_CONFIG2_OFFSET (0x1C) -#define OSD_BLEND_OBND_KEY_PALETTE_EN OSD_BLEND_OBND_KEY_PALETTE_EN -#define OSD_BLEND_OBND_KEY_PALETTE_EN_POS (0U) -#define OSD_BLEND_OBND_KEY_PALETTE_EN_LEN (1U) -#define OSD_BLEND_OBND_KEY_PALETTE_EN_MSK (((1U << OSD_BLEND_OBND_KEY_PALETTE_EN_LEN) - 1) << OSD_BLEND_OBND_KEY_PALETTE_EN_POS) -#define OSD_BLEND_OBND_KEY_PALETTE_EN_UMSK (~(((1U << OSD_BLEND_OBND_KEY_PALETTE_EN_LEN) - 1) << OSD_BLEND_OBND_KEY_PALETTE_EN_POS)) -#define OSD_BLEND_OBND_KEY_INDEX_INV OSD_BLEND_OBND_KEY_INDEX_INV -#define OSD_BLEND_OBND_KEY_INDEX_INV_POS (1U) -#define OSD_BLEND_OBND_KEY_INDEX_INV_LEN (1U) -#define OSD_BLEND_OBND_KEY_INDEX_INV_MSK (((1U << OSD_BLEND_OBND_KEY_INDEX_INV_LEN) - 1) << OSD_BLEND_OBND_KEY_INDEX_INV_POS) -#define OSD_BLEND_OBND_KEY_INDEX_INV_UMSK (~(((1U << OSD_BLEND_OBND_KEY_INDEX_INV_LEN) - 1) << OSD_BLEND_OBND_KEY_INDEX_INV_POS)) -#define OSD_BLEND_OBND_KEY_INDEX_MIN OSD_BLEND_OBND_KEY_INDEX_MIN -#define OSD_BLEND_OBND_KEY_INDEX_MIN_POS (8U) -#define OSD_BLEND_OBND_KEY_INDEX_MIN_LEN (8U) -#define OSD_BLEND_OBND_KEY_INDEX_MIN_MSK (((1U << OSD_BLEND_OBND_KEY_INDEX_MIN_LEN) - 1) << OSD_BLEND_OBND_KEY_INDEX_MIN_POS) -#define OSD_BLEND_OBND_KEY_INDEX_MIN_UMSK (~(((1U << OSD_BLEND_OBND_KEY_INDEX_MIN_LEN) - 1) << OSD_BLEND_OBND_KEY_INDEX_MIN_POS)) -#define OSD_BLEND_OBND_KEY_INDEX_MAX OSD_BLEND_OBND_KEY_INDEX_MAX -#define OSD_BLEND_OBND_KEY_INDEX_MAX_POS (16U) -#define OSD_BLEND_OBND_KEY_INDEX_MAX_LEN (8U) -#define OSD_BLEND_OBND_KEY_INDEX_MAX_MSK (((1U << OSD_BLEND_OBND_KEY_INDEX_MAX_LEN) - 1) << OSD_BLEND_OBND_KEY_INDEX_MAX_POS) -#define OSD_BLEND_OBND_KEY_INDEX_MAX_UMSK (~(((1U << OSD_BLEND_OBND_KEY_INDEX_MAX_LEN) - 1) << OSD_BLEND_OBND_KEY_INDEX_MAX_POS)) -#define OSD_BLEND_OBND_KEY_REPLACE_INDEX OSD_BLEND_OBND_KEY_REPLACE_INDEX -#define OSD_BLEND_OBND_KEY_REPLACE_INDEX_POS (24U) -#define OSD_BLEND_OBND_KEY_REPLACE_INDEX_LEN (8U) -#define OSD_BLEND_OBND_KEY_REPLACE_INDEX_MSK (((1U << OSD_BLEND_OBND_KEY_REPLACE_INDEX_LEN) - 1) << OSD_BLEND_OBND_KEY_REPLACE_INDEX_POS) -#define OSD_BLEND_OBND_KEY_REPLACE_INDEX_UMSK (~(((1U << OSD_BLEND_OBND_KEY_REPLACE_INDEX_LEN) - 1) << OSD_BLEND_OBND_KEY_REPLACE_INDEX_POS)) - -/* 0x20 : obnd_layer_config3 */ -#define OSD_BLEND_OBND_LAYER_CONFIG3_OFFSET (0x20) -#define OSD_BLEND_OBND_KEY_A_MIN OSD_BLEND_OBND_KEY_A_MIN -#define OSD_BLEND_OBND_KEY_A_MIN_POS (0U) -#define OSD_BLEND_OBND_KEY_A_MIN_LEN (8U) -#define OSD_BLEND_OBND_KEY_A_MIN_MSK (((1U << OSD_BLEND_OBND_KEY_A_MIN_LEN) - 1) << OSD_BLEND_OBND_KEY_A_MIN_POS) -#define OSD_BLEND_OBND_KEY_A_MIN_UMSK (~(((1U << OSD_BLEND_OBND_KEY_A_MIN_LEN) - 1) << OSD_BLEND_OBND_KEY_A_MIN_POS)) -#define OSD_BLEND_OBND_KEY_A_MAX OSD_BLEND_OBND_KEY_A_MAX -#define OSD_BLEND_OBND_KEY_A_MAX_POS (8U) -#define OSD_BLEND_OBND_KEY_A_MAX_LEN (8U) -#define OSD_BLEND_OBND_KEY_A_MAX_MSK (((1U << OSD_BLEND_OBND_KEY_A_MAX_LEN) - 1) << OSD_BLEND_OBND_KEY_A_MAX_POS) -#define OSD_BLEND_OBND_KEY_A_MAX_UMSK (~(((1U << OSD_BLEND_OBND_KEY_A_MAX_LEN) - 1) << OSD_BLEND_OBND_KEY_A_MAX_POS)) -#define OSD_BLEND_OBND_KEY_RV_MIN OSD_BLEND_OBND_KEY_RV_MIN -#define OSD_BLEND_OBND_KEY_RV_MIN_POS (16U) -#define OSD_BLEND_OBND_KEY_RV_MIN_LEN (8U) -#define OSD_BLEND_OBND_KEY_RV_MIN_MSK (((1U << OSD_BLEND_OBND_KEY_RV_MIN_LEN) - 1) << OSD_BLEND_OBND_KEY_RV_MIN_POS) -#define OSD_BLEND_OBND_KEY_RV_MIN_UMSK (~(((1U << OSD_BLEND_OBND_KEY_RV_MIN_LEN) - 1) << OSD_BLEND_OBND_KEY_RV_MIN_POS)) -#define OSD_BLEND_OBND_KEY_RV_MAX OSD_BLEND_OBND_KEY_RV_MAX -#define OSD_BLEND_OBND_KEY_RV_MAX_POS (24U) -#define OSD_BLEND_OBND_KEY_RV_MAX_LEN (8U) -#define OSD_BLEND_OBND_KEY_RV_MAX_MSK (((1U << OSD_BLEND_OBND_KEY_RV_MAX_LEN) - 1) << OSD_BLEND_OBND_KEY_RV_MAX_POS) -#define OSD_BLEND_OBND_KEY_RV_MAX_UMSK (~(((1U << OSD_BLEND_OBND_KEY_RV_MAX_LEN) - 1) << OSD_BLEND_OBND_KEY_RV_MAX_POS)) - -/* 0x24 : obnd_layer_config4 */ -#define OSD_BLEND_OBND_LAYER_CONFIG4_OFFSET (0x24) -#define OSD_BLEND_OBND_KEY_GY_MIN OSD_BLEND_OBND_KEY_GY_MIN -#define OSD_BLEND_OBND_KEY_GY_MIN_POS (0U) -#define OSD_BLEND_OBND_KEY_GY_MIN_LEN (8U) -#define OSD_BLEND_OBND_KEY_GY_MIN_MSK (((1U << OSD_BLEND_OBND_KEY_GY_MIN_LEN) - 1) << OSD_BLEND_OBND_KEY_GY_MIN_POS) -#define OSD_BLEND_OBND_KEY_GY_MIN_UMSK (~(((1U << OSD_BLEND_OBND_KEY_GY_MIN_LEN) - 1) << OSD_BLEND_OBND_KEY_GY_MIN_POS)) -#define OSD_BLEND_OBND_KEY_GY_MAX OSD_BLEND_OBND_KEY_GY_MAX -#define OSD_BLEND_OBND_KEY_GY_MAX_POS (8U) -#define OSD_BLEND_OBND_KEY_GY_MAX_LEN (8U) -#define OSD_BLEND_OBND_KEY_GY_MAX_MSK (((1U << OSD_BLEND_OBND_KEY_GY_MAX_LEN) - 1) << OSD_BLEND_OBND_KEY_GY_MAX_POS) -#define OSD_BLEND_OBND_KEY_GY_MAX_UMSK (~(((1U << OSD_BLEND_OBND_KEY_GY_MAX_LEN) - 1) << OSD_BLEND_OBND_KEY_GY_MAX_POS)) -#define OSD_BLEND_OBND_KEY_BU_MIN OSD_BLEND_OBND_KEY_BU_MIN -#define OSD_BLEND_OBND_KEY_BU_MIN_POS (16U) -#define OSD_BLEND_OBND_KEY_BU_MIN_LEN (8U) -#define OSD_BLEND_OBND_KEY_BU_MIN_MSK (((1U << OSD_BLEND_OBND_KEY_BU_MIN_LEN) - 1) << OSD_BLEND_OBND_KEY_BU_MIN_POS) -#define OSD_BLEND_OBND_KEY_BU_MIN_UMSK (~(((1U << OSD_BLEND_OBND_KEY_BU_MIN_LEN) - 1) << OSD_BLEND_OBND_KEY_BU_MIN_POS)) -#define OSD_BLEND_OBND_KEY_BU_MAX OSD_BLEND_OBND_KEY_BU_MAX -#define OSD_BLEND_OBND_KEY_BU_MAX_POS (24U) -#define OSD_BLEND_OBND_KEY_BU_MAX_LEN (8U) -#define OSD_BLEND_OBND_KEY_BU_MAX_MSK (((1U << OSD_BLEND_OBND_KEY_BU_MAX_LEN) - 1) << OSD_BLEND_OBND_KEY_BU_MAX_POS) -#define OSD_BLEND_OBND_KEY_BU_MAX_UMSK (~(((1U << OSD_BLEND_OBND_KEY_BU_MAX_LEN) - 1) << OSD_BLEND_OBND_KEY_BU_MAX_POS)) - -/* 0x28 : obnd_layer_config5 */ -#define OSD_BLEND_OBND_LAYER_CONFIG5_OFFSET (0x28) -#define OSD_BLEND_OBND_KEY_REPLACE_A OSD_BLEND_OBND_KEY_REPLACE_A -#define OSD_BLEND_OBND_KEY_REPLACE_A_POS (0U) -#define OSD_BLEND_OBND_KEY_REPLACE_A_LEN (8U) -#define OSD_BLEND_OBND_KEY_REPLACE_A_MSK (((1U << OSD_BLEND_OBND_KEY_REPLACE_A_LEN) - 1) << OSD_BLEND_OBND_KEY_REPLACE_A_POS) -#define OSD_BLEND_OBND_KEY_REPLACE_A_UMSK (~(((1U << OSD_BLEND_OBND_KEY_REPLACE_A_LEN) - 1) << OSD_BLEND_OBND_KEY_REPLACE_A_POS)) -#define OSD_BLEND_OBND_KEY_REPLACE_RV OSD_BLEND_OBND_KEY_REPLACE_RV -#define OSD_BLEND_OBND_KEY_REPLACE_RV_POS (8U) -#define OSD_BLEND_OBND_KEY_REPLACE_RV_LEN (8U) -#define OSD_BLEND_OBND_KEY_REPLACE_RV_MSK (((1U << OSD_BLEND_OBND_KEY_REPLACE_RV_LEN) - 1) << OSD_BLEND_OBND_KEY_REPLACE_RV_POS) -#define OSD_BLEND_OBND_KEY_REPLACE_RV_UMSK (~(((1U << OSD_BLEND_OBND_KEY_REPLACE_RV_LEN) - 1) << OSD_BLEND_OBND_KEY_REPLACE_RV_POS)) -#define OSD_BLEND_OBND_KEY_REPLACE_GY OSD_BLEND_OBND_KEY_REPLACE_GY -#define OSD_BLEND_OBND_KEY_REPLACE_GY_POS (16U) -#define OSD_BLEND_OBND_KEY_REPLACE_GY_LEN (8U) -#define OSD_BLEND_OBND_KEY_REPLACE_GY_MSK (((1U << OSD_BLEND_OBND_KEY_REPLACE_GY_LEN) - 1) << OSD_BLEND_OBND_KEY_REPLACE_GY_POS) -#define OSD_BLEND_OBND_KEY_REPLACE_GY_UMSK (~(((1U << OSD_BLEND_OBND_KEY_REPLACE_GY_LEN) - 1) << OSD_BLEND_OBND_KEY_REPLACE_GY_POS)) -#define OSD_BLEND_OBND_KEY_REPLACE_BU OSD_BLEND_OBND_KEY_REPLACE_BU -#define OSD_BLEND_OBND_KEY_REPLACE_BU_POS (24U) -#define OSD_BLEND_OBND_KEY_REPLACE_BU_LEN (8U) -#define OSD_BLEND_OBND_KEY_REPLACE_BU_MSK (((1U << OSD_BLEND_OBND_KEY_REPLACE_BU_LEN) - 1) << OSD_BLEND_OBND_KEY_REPLACE_BU_POS) -#define OSD_BLEND_OBND_KEY_REPLACE_BU_UMSK (~(((1U << OSD_BLEND_OBND_KEY_REPLACE_BU_LEN) - 1) << OSD_BLEND_OBND_KEY_REPLACE_BU_POS)) - -/* 0x2C : obnd_layer_config6 */ -#define OSD_BLEND_OBND_LAYER_CONFIG6_OFFSET (0x2C) -#define OSD_BLEND_OBND_KEY_COLOR_EN OSD_BLEND_OBND_KEY_COLOR_EN -#define OSD_BLEND_OBND_KEY_COLOR_EN_POS (0U) -#define OSD_BLEND_OBND_KEY_COLOR_EN_LEN (1U) -#define OSD_BLEND_OBND_KEY_COLOR_EN_MSK (((1U << OSD_BLEND_OBND_KEY_COLOR_EN_LEN) - 1) << OSD_BLEND_OBND_KEY_COLOR_EN_POS) -#define OSD_BLEND_OBND_KEY_COLOR_EN_UMSK (~(((1U << OSD_BLEND_OBND_KEY_COLOR_EN_LEN) - 1) << OSD_BLEND_OBND_KEY_COLOR_EN_POS)) -#define OSD_BLEND_OBND_KEY_A_INV OSD_BLEND_OBND_KEY_A_INV -#define OSD_BLEND_OBND_KEY_A_INV_POS (1U) -#define OSD_BLEND_OBND_KEY_A_INV_LEN (1U) -#define OSD_BLEND_OBND_KEY_A_INV_MSK (((1U << OSD_BLEND_OBND_KEY_A_INV_LEN) - 1) << OSD_BLEND_OBND_KEY_A_INV_POS) -#define OSD_BLEND_OBND_KEY_A_INV_UMSK (~(((1U << OSD_BLEND_OBND_KEY_A_INV_LEN) - 1) << OSD_BLEND_OBND_KEY_A_INV_POS)) -#define OSD_BLEND_OBND_KEY_RV_INV OSD_BLEND_OBND_KEY_RV_INV -#define OSD_BLEND_OBND_KEY_RV_INV_POS (2U) -#define OSD_BLEND_OBND_KEY_RV_INV_LEN (1U) -#define OSD_BLEND_OBND_KEY_RV_INV_MSK (((1U << OSD_BLEND_OBND_KEY_RV_INV_LEN) - 1) << OSD_BLEND_OBND_KEY_RV_INV_POS) -#define OSD_BLEND_OBND_KEY_RV_INV_UMSK (~(((1U << OSD_BLEND_OBND_KEY_RV_INV_LEN) - 1) << OSD_BLEND_OBND_KEY_RV_INV_POS)) -#define OSD_BLEND_OBND_KEY_GY_INV OSD_BLEND_OBND_KEY_GY_INV -#define OSD_BLEND_OBND_KEY_GY_INV_POS (3U) -#define OSD_BLEND_OBND_KEY_GY_INV_LEN (1U) -#define OSD_BLEND_OBND_KEY_GY_INV_MSK (((1U << OSD_BLEND_OBND_KEY_GY_INV_LEN) - 1) << OSD_BLEND_OBND_KEY_GY_INV_POS) -#define OSD_BLEND_OBND_KEY_GY_INV_UMSK (~(((1U << OSD_BLEND_OBND_KEY_GY_INV_LEN) - 1) << OSD_BLEND_OBND_KEY_GY_INV_POS)) -#define OSD_BLEND_OBND_KEY_BU_INV OSD_BLEND_OBND_KEY_BU_INV -#define OSD_BLEND_OBND_KEY_BU_INV_POS (4U) -#define OSD_BLEND_OBND_KEY_BU_INV_LEN (1U) -#define OSD_BLEND_OBND_KEY_BU_INV_MSK (((1U << OSD_BLEND_OBND_KEY_BU_INV_LEN) - 1) << OSD_BLEND_OBND_KEY_BU_INV_POS) -#define OSD_BLEND_OBND_KEY_BU_INV_UMSK (~(((1U << OSD_BLEND_OBND_KEY_BU_INV_LEN) - 1) << OSD_BLEND_OBND_KEY_BU_INV_POS)) -#define OSD_BLEND_OBND_UPDATE_TRIGGER OSD_BLEND_OBND_UPDATE_TRIGGER -#define OSD_BLEND_OBND_UPDATE_TRIGGER_POS (5U) -#define OSD_BLEND_OBND_UPDATE_TRIGGER_LEN (1U) -#define OSD_BLEND_OBND_UPDATE_TRIGGER_MSK (((1U << OSD_BLEND_OBND_UPDATE_TRIGGER_LEN) - 1) << OSD_BLEND_OBND_UPDATE_TRIGGER_POS) -#define OSD_BLEND_OBND_UPDATE_TRIGGER_UMSK (~(((1U << OSD_BLEND_OBND_UPDATE_TRIGGER_LEN) - 1) << OSD_BLEND_OBND_UPDATE_TRIGGER_POS)) -#define OSD_BLEND_OBND_UPDATE_INDEX OSD_BLEND_OBND_UPDATE_INDEX -#define OSD_BLEND_OBND_UPDATE_INDEX_POS (8U) -#define OSD_BLEND_OBND_UPDATE_INDEX_LEN (8U) -#define OSD_BLEND_OBND_UPDATE_INDEX_MSK (((1U << OSD_BLEND_OBND_UPDATE_INDEX_LEN) - 1) << OSD_BLEND_OBND_UPDATE_INDEX_POS) -#define OSD_BLEND_OBND_UPDATE_INDEX_UMSK (~(((1U << OSD_BLEND_OBND_UPDATE_INDEX_LEN) - 1) << OSD_BLEND_OBND_UPDATE_INDEX_POS)) - -/* 0x30 : obnd_layer_config7 */ -#define OSD_BLEND_OBND_LAYER_CONFIG7_OFFSET (0x30) -#define OSD_BLEND_OBND_UPDATE_COLOR OSD_BLEND_OBND_UPDATE_COLOR -#define OSD_BLEND_OBND_UPDATE_COLOR_POS (0U) -#define OSD_BLEND_OBND_UPDATE_COLOR_LEN (32U) -#define OSD_BLEND_OBND_UPDATE_COLOR_MSK (((1U << OSD_BLEND_OBND_UPDATE_COLOR_LEN) - 1) << OSD_BLEND_OBND_UPDATE_COLOR_POS) -#define OSD_BLEND_OBND_UPDATE_COLOR_UMSK (~(((1U << OSD_BLEND_OBND_UPDATE_COLOR_LEN) - 1) << OSD_BLEND_OBND_UPDATE_COLOR_POS)) - -/* 0x40 : obnd_error */ -#define OSD_BLEND_OBND_ERROR_OFFSET (0x40) -#define OSD_BLEND_REG_RFIFO_DRAIN_CLR_W OSD_BLEND_REG_RFIFO_DRAIN_CLR_W -#define OSD_BLEND_REG_RFIFO_DRAIN_CLR_W_POS (0U) -#define OSD_BLEND_REG_RFIFO_DRAIN_CLR_W_LEN (1U) -#define OSD_BLEND_REG_RFIFO_DRAIN_CLR_W_MSK (((1U << OSD_BLEND_REG_RFIFO_DRAIN_CLR_W_LEN) - 1) << OSD_BLEND_REG_RFIFO_DRAIN_CLR_W_POS) -#define OSD_BLEND_REG_RFIFO_DRAIN_CLR_W_UMSK (~(((1U << OSD_BLEND_REG_RFIFO_DRAIN_CLR_W_LEN) - 1) << OSD_BLEND_REG_RFIFO_DRAIN_CLR_W_POS)) -#define OSD_BLEND_REG_RFIFO_DRAIN_MASK_W OSD_BLEND_REG_RFIFO_DRAIN_MASK_W -#define OSD_BLEND_REG_RFIFO_DRAIN_MASK_W_POS (1U) -#define OSD_BLEND_REG_RFIFO_DRAIN_MASK_W_LEN (1U) -#define OSD_BLEND_REG_RFIFO_DRAIN_MASK_W_MSK (((1U << OSD_BLEND_REG_RFIFO_DRAIN_MASK_W_LEN) - 1) << OSD_BLEND_REG_RFIFO_DRAIN_MASK_W_POS) -#define OSD_BLEND_REG_RFIFO_DRAIN_MASK_W_UMSK (~(((1U << OSD_BLEND_REG_RFIFO_DRAIN_MASK_W_LEN) - 1) << OSD_BLEND_REG_RFIFO_DRAIN_MASK_W_POS)) -#define OSD_BLEND_STS_RFIFO_DRAIN_R OSD_BLEND_STS_RFIFO_DRAIN_R -#define OSD_BLEND_STS_RFIFO_DRAIN_R_POS (16U) -#define OSD_BLEND_STS_RFIFO_DRAIN_R_LEN (1U) -#define OSD_BLEND_STS_RFIFO_DRAIN_R_MSK (((1U << OSD_BLEND_STS_RFIFO_DRAIN_R_LEN) - 1) << OSD_BLEND_STS_RFIFO_DRAIN_R_POS) -#define OSD_BLEND_STS_RFIFO_DRAIN_R_UMSK (~(((1U << OSD_BLEND_STS_RFIFO_DRAIN_R_LEN) - 1) << OSD_BLEND_STS_RFIFO_DRAIN_R_POS)) - -/* 0x44 : obnd_sh */ -#define OSD_BLEND_OBND_SH_OFFSET (0x44) -#define OSD_BLEND_OBND_LAYER_MEM_REQ_CNT OSD_BLEND_OBND_LAYER_MEM_REQ_CNT -#define OSD_BLEND_OBND_LAYER_MEM_REQ_CNT_POS (0U) -#define OSD_BLEND_OBND_LAYER_MEM_REQ_CNT_LEN (32U) -#define OSD_BLEND_OBND_LAYER_MEM_REQ_CNT_MSK (((1U << OSD_BLEND_OBND_LAYER_MEM_REQ_CNT_LEN) - 1) << OSD_BLEND_OBND_LAYER_MEM_REQ_CNT_POS) -#define OSD_BLEND_OBND_LAYER_MEM_REQ_CNT_UMSK (~(((1U << OSD_BLEND_OBND_LAYER_MEM_REQ_CNT_LEN) - 1) << OSD_BLEND_OBND_LAYER_MEM_REQ_CNT_POS)) - -struct osd_blend_reg { - /* 0x0 : obnd_layer_xconfig */ - union { - struct { - uint32_t obnd_x_min : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t obnd_x_max : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } obnd_layer_xconfig; - - /* 0x4 : obnd_layer_yconfig */ - union { - struct { - uint32_t obnd_y_min : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t obnd_y_max : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } obnd_layer_yconfig; - - /* 0x8 : obnd_mem_config0 */ - union { - struct { - uint32_t obnd_force_sh : 1; /* [ 0], w1p, 0x0 */ - uint32_t reserved_1_14 : 14; /* [14: 1], rsvd, 0x0 */ - uint32_t obnd_layer_en : 1; /* [ 15], r/w, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } obnd_mem_config0; - - /* 0xC : obnd_mem_config1 */ - union { - struct { - uint32_t obnd_mem_addr : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } obnd_mem_config1; - - /* 0x10 : obnd_mem_config2 */ - union { - struct { - uint32_t obnd_mem_dw_cnt : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } obnd_mem_config2; - - /* 0x14 : obnd_layer_config0 */ - union { - struct { - uint32_t obnd_color_format : 5; /* [ 4: 0], r/w, 0x0 */ - uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ - uint32_t obnd_order_a : 2; /* [ 9: 8], r/w, 0x0 */ - uint32_t obnd_order_rv : 2; /* [11:10], r/w, 0x0 */ - uint32_t obnd_order_gy : 2; /* [13:12], r/w, 0x0 */ - uint32_t obnd_order_bu : 2; /* [15:14], r/w, 0x0 */ - uint32_t obnd_global_a_en : 1; /* [ 16], r/w, 0x0 */ - uint32_t reserved_17_23 : 7; /* [23:17], rsvd, 0x0 */ - uint32_t obnd_global_a : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } obnd_layer_config0; - - /* 0x18 : obnd_layer_config1 */ - union { - struct { - uint32_t obnd_global_color_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_7 : 7; /* [ 7: 1], rsvd, 0x0 */ - uint32_t obnd_global_rv : 8; /* [15: 8], r/w, 0x0 */ - uint32_t obnd_global_gy : 8; /* [23:16], r/w, 0x0 */ - uint32_t obnd_global_bu : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } obnd_layer_config1; - - /* 0x1C : obnd_layer_config2 */ - union { - struct { - uint32_t obnd_key_palette_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t obnd_key_index_inv : 1; /* [ 1], r/w, 0x0 */ - uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ - uint32_t obnd_key_index_min : 8; /* [15: 8], r/w, 0x0 */ - uint32_t obnd_key_index_max : 8; /* [23:16], r/w, 0x0 */ - uint32_t obnd_key_replace_index : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } obnd_layer_config2; - - /* 0x20 : obnd_layer_config3 */ - union { - struct { - uint32_t obnd_key_a_min : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t obnd_key_a_max : 8; /* [15: 8], r/w, 0x0 */ - uint32_t obnd_key_rv_min : 8; /* [23:16], r/w, 0x0 */ - uint32_t obnd_key_rv_max : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } obnd_layer_config3; - - /* 0x24 : obnd_layer_config4 */ - union { - struct { - uint32_t obnd_key_gy_min : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t obnd_key_gy_max : 8; /* [15: 8], r/w, 0x0 */ - uint32_t obnd_key_bu_min : 8; /* [23:16], r/w, 0x0 */ - uint32_t obnd_key_bu_max : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } obnd_layer_config4; - - /* 0x28 : obnd_layer_config5 */ - union { - struct { - uint32_t obnd_key_replace_a : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t obnd_key_replace_rv : 8; /* [15: 8], r/w, 0x0 */ - uint32_t obnd_key_replace_gy : 8; /* [23:16], r/w, 0x0 */ - uint32_t obnd_key_replace_bu : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } obnd_layer_config5; - - /* 0x2C : obnd_layer_config6 */ - union { - struct { - uint32_t obnd_key_color_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t obnd_key_a_inv : 1; /* [ 1], r/w, 0x0 */ - uint32_t obnd_key_rv_inv : 1; /* [ 2], r/w, 0x0 */ - uint32_t obnd_key_gy_inv : 1; /* [ 3], r/w, 0x0 */ - uint32_t obnd_key_bu_inv : 1; /* [ 4], r/w, 0x0 */ - uint32_t obnd_update_trigger : 1; /* [ 5], w1p, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t obnd_update_index : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } obnd_layer_config6; - - /* 0x30 : obnd_layer_config7 */ - union { - struct { - uint32_t obnd_update_color : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } obnd_layer_config7; - - /* 0x34 reserved */ - uint8_t RESERVED0x34[12]; - - /* 0x40 : obnd_error */ - union { - struct { - uint32_t reg_rfifo_drain_clr_w : 1; /* [ 0], w1p, 0x0 */ - uint32_t reg_rfifo_drain_mask_w : 1; /* [ 1], r/w, 0x0 */ - uint32_t reserved_2_15 : 14; /* [15: 2], rsvd, 0x0 */ - uint32_t sts_rfifo_drain_r : 1; /* [ 16], r, 0x0 */ - uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } obnd_error; - - /* 0x44 : obnd_sh */ - union { - struct { - uint32_t obnd_layer_mem_req_cnt : 32; /* [31: 0], r/w, 0x1000 */ - } BF; - uint32_t WORD; - } obnd_sh; -}; - -typedef volatile struct osd_blend_reg osd_blend_reg_t; - -#endif /* __OSD_BLEND_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/osd_draw_h_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/osd_draw_h_reg.h deleted file mode 100644 index c1348a356e..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/osd_draw_h_reg.h +++ /dev/null @@ -1,1382 +0,0 @@ -/** - ****************************************************************************** - * @file osd_draw_h_reg.h - * @version V1.0 - * @date 2021-06-28 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __OSD_DRAW_H_REG_H__ -#define __OSD_DRAW_H_REG_H__ - -#include "bl808.h" - -/* 0x4 : draw_partial_config */ -#define OSD_DRAW_H_DRAW_PARTIAL_CONFIG_OFFSET (0x4) -#define OSD_DRAW_H_REG_DRAW_EN_H OSD_DRAW_H_REG_DRAW_EN_H -#define OSD_DRAW_H_REG_DRAW_EN_H_POS (0U) -#define OSD_DRAW_H_REG_DRAW_EN_H_LEN (16U) -#define OSD_DRAW_H_REG_DRAW_EN_H_MSK (((1U << OSD_DRAW_H_REG_DRAW_EN_H_LEN) - 1) << OSD_DRAW_H_REG_DRAW_EN_H_POS) -#define OSD_DRAW_H_REG_DRAW_EN_H_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_EN_H_LEN) - 1) << OSD_DRAW_H_REG_DRAW_EN_H_POS)) -#define OSD_DRAW_H_REG_DRAW_TYPE_H OSD_DRAW_H_REG_DRAW_TYPE_H -#define OSD_DRAW_H_REG_DRAW_TYPE_H_POS (16U) -#define OSD_DRAW_H_REG_DRAW_TYPE_H_LEN (16U) -#define OSD_DRAW_H_REG_DRAW_TYPE_H_MSK (((1U << OSD_DRAW_H_REG_DRAW_TYPE_H_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TYPE_H_POS) -#define OSD_DRAW_H_REG_DRAW_TYPE_H_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_TYPE_H_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TYPE_H_POS)) - -/* 0x8 : draw_partial_yuv_config10 */ -#define OSD_DRAW_H_DRAW_PARTIAL_YUV_CONFIG10_OFFSET (0x8) -#define OSD_DRAW_H_REG_DRAW_TH_10 OSD_DRAW_H_REG_DRAW_TH_10 -#define OSD_DRAW_H_REG_DRAW_TH_10_POS (0U) -#define OSD_DRAW_H_REG_DRAW_TH_10_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_TH_10_MSK (((1U << OSD_DRAW_H_REG_DRAW_TH_10_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_10_POS) -#define OSD_DRAW_H_REG_DRAW_TH_10_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_TH_10_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_10_POS)) -#define OSD_DRAW_H_REG_DRAW_V_10 OSD_DRAW_H_REG_DRAW_V_10 -#define OSD_DRAW_H_REG_DRAW_V_10_POS (8U) -#define OSD_DRAW_H_REG_DRAW_V_10_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_V_10_MSK (((1U << OSD_DRAW_H_REG_DRAW_V_10_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_10_POS) -#define OSD_DRAW_H_REG_DRAW_V_10_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_V_10_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_10_POS)) -#define OSD_DRAW_H_REG_DRAW_U_10 OSD_DRAW_H_REG_DRAW_U_10 -#define OSD_DRAW_H_REG_DRAW_U_10_POS (16U) -#define OSD_DRAW_H_REG_DRAW_U_10_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_U_10_MSK (((1U << OSD_DRAW_H_REG_DRAW_U_10_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_10_POS) -#define OSD_DRAW_H_REG_DRAW_U_10_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_U_10_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_10_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_10 OSD_DRAW_H_REG_DRAW_Y_10 -#define OSD_DRAW_H_REG_DRAW_Y_10_POS (24U) -#define OSD_DRAW_H_REG_DRAW_Y_10_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_Y_10_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_10_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_10_POS) -#define OSD_DRAW_H_REG_DRAW_Y_10_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_10_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_10_POS)) - -/* 0xC : draw_partial_x_config10 */ -#define OSD_DRAW_H_DRAW_PARTIAL_X_CONFIG10_OFFSET (0xC) -#define OSD_DRAW_H_REG_DRAW_X_MIN_10 OSD_DRAW_H_REG_DRAW_X_MIN_10 -#define OSD_DRAW_H_REG_DRAW_X_MIN_10_POS (0U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_10_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_10_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MIN_10_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_10_POS) -#define OSD_DRAW_H_REG_DRAW_X_MIN_10_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MIN_10_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_10_POS)) -#define OSD_DRAW_H_REG_DRAW_X_MAX_10 OSD_DRAW_H_REG_DRAW_X_MAX_10 -#define OSD_DRAW_H_REG_DRAW_X_MAX_10_POS (16U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_10_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_10_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MAX_10_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_10_POS) -#define OSD_DRAW_H_REG_DRAW_X_MAX_10_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MAX_10_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_10_POS)) - -/* 0x10 : draw_partial_y_config10 */ -#define OSD_DRAW_H_DRAW_PARTIAL_Y_CONFIG10_OFFSET (0x10) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_10 OSD_DRAW_H_REG_DRAW_Y_MIN_10 -#define OSD_DRAW_H_REG_DRAW_Y_MIN_10_POS (0U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_10_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_10_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_10_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_10_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_10_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_10_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_10_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_10 OSD_DRAW_H_REG_DRAW_Y_MAX_10 -#define OSD_DRAW_H_REG_DRAW_Y_MAX_10_POS (16U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_10_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_10_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_10_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_10_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_10_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_10_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_10_POS)) - -/* 0x14 : draw_partial_yuv_config11 */ -#define OSD_DRAW_H_DRAW_PARTIAL_YUV_CONFIG11_OFFSET (0x14) -#define OSD_DRAW_H_REG_DRAW_TH_11 OSD_DRAW_H_REG_DRAW_TH_11 -#define OSD_DRAW_H_REG_DRAW_TH_11_POS (0U) -#define OSD_DRAW_H_REG_DRAW_TH_11_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_TH_11_MSK (((1U << OSD_DRAW_H_REG_DRAW_TH_11_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_11_POS) -#define OSD_DRAW_H_REG_DRAW_TH_11_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_TH_11_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_11_POS)) -#define OSD_DRAW_H_REG_DRAW_V_11 OSD_DRAW_H_REG_DRAW_V_11 -#define OSD_DRAW_H_REG_DRAW_V_11_POS (8U) -#define OSD_DRAW_H_REG_DRAW_V_11_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_V_11_MSK (((1U << OSD_DRAW_H_REG_DRAW_V_11_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_11_POS) -#define OSD_DRAW_H_REG_DRAW_V_11_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_V_11_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_11_POS)) -#define OSD_DRAW_H_REG_DRAW_U_11 OSD_DRAW_H_REG_DRAW_U_11 -#define OSD_DRAW_H_REG_DRAW_U_11_POS (16U) -#define OSD_DRAW_H_REG_DRAW_U_11_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_U_11_MSK (((1U << OSD_DRAW_H_REG_DRAW_U_11_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_11_POS) -#define OSD_DRAW_H_REG_DRAW_U_11_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_U_11_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_11_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_11 OSD_DRAW_H_REG_DRAW_Y_11 -#define OSD_DRAW_H_REG_DRAW_Y_11_POS (24U) -#define OSD_DRAW_H_REG_DRAW_Y_11_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_Y_11_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_11_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_11_POS) -#define OSD_DRAW_H_REG_DRAW_Y_11_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_11_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_11_POS)) - -/* 0x18 : draw_partial_x_config11 */ -#define OSD_DRAW_H_DRAW_PARTIAL_X_CONFIG11_OFFSET (0x18) -#define OSD_DRAW_H_REG_DRAW_X_MIN_11 OSD_DRAW_H_REG_DRAW_X_MIN_11 -#define OSD_DRAW_H_REG_DRAW_X_MIN_11_POS (0U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_11_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_11_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MIN_11_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_11_POS) -#define OSD_DRAW_H_REG_DRAW_X_MIN_11_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MIN_11_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_11_POS)) -#define OSD_DRAW_H_REG_DRAW_X_MAX_11 OSD_DRAW_H_REG_DRAW_X_MAX_11 -#define OSD_DRAW_H_REG_DRAW_X_MAX_11_POS (16U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_11_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_11_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MAX_11_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_11_POS) -#define OSD_DRAW_H_REG_DRAW_X_MAX_11_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MAX_11_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_11_POS)) - -/* 0x1C : draw_partial_y_config11 */ -#define OSD_DRAW_H_DRAW_PARTIAL_Y_CONFIG11_OFFSET (0x1C) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_11 OSD_DRAW_H_REG_DRAW_Y_MIN_11 -#define OSD_DRAW_H_REG_DRAW_Y_MIN_11_POS (0U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_11_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_11_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_11_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_11_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_11_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_11_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_11_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_11 OSD_DRAW_H_REG_DRAW_Y_MAX_11 -#define OSD_DRAW_H_REG_DRAW_Y_MAX_11_POS (16U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_11_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_11_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_11_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_11_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_11_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_11_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_11_POS)) - -/* 0x20 : draw_partial_yuv_config12 */ -#define OSD_DRAW_H_DRAW_PARTIAL_YUV_CONFIG12_OFFSET (0x20) -#define OSD_DRAW_H_REG_DRAW_TH_12 OSD_DRAW_H_REG_DRAW_TH_12 -#define OSD_DRAW_H_REG_DRAW_TH_12_POS (0U) -#define OSD_DRAW_H_REG_DRAW_TH_12_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_TH_12_MSK (((1U << OSD_DRAW_H_REG_DRAW_TH_12_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_12_POS) -#define OSD_DRAW_H_REG_DRAW_TH_12_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_TH_12_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_12_POS)) -#define OSD_DRAW_H_REG_DRAW_V_12 OSD_DRAW_H_REG_DRAW_V_12 -#define OSD_DRAW_H_REG_DRAW_V_12_POS (8U) -#define OSD_DRAW_H_REG_DRAW_V_12_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_V_12_MSK (((1U << OSD_DRAW_H_REG_DRAW_V_12_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_12_POS) -#define OSD_DRAW_H_REG_DRAW_V_12_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_V_12_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_12_POS)) -#define OSD_DRAW_H_REG_DRAW_U_12 OSD_DRAW_H_REG_DRAW_U_12 -#define OSD_DRAW_H_REG_DRAW_U_12_POS (16U) -#define OSD_DRAW_H_REG_DRAW_U_12_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_U_12_MSK (((1U << OSD_DRAW_H_REG_DRAW_U_12_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_12_POS) -#define OSD_DRAW_H_REG_DRAW_U_12_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_U_12_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_12_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_12 OSD_DRAW_H_REG_DRAW_Y_12 -#define OSD_DRAW_H_REG_DRAW_Y_12_POS (24U) -#define OSD_DRAW_H_REG_DRAW_Y_12_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_Y_12_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_12_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_12_POS) -#define OSD_DRAW_H_REG_DRAW_Y_12_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_12_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_12_POS)) - -/* 0x24 : draw_partial_x_config12 */ -#define OSD_DRAW_H_DRAW_PARTIAL_X_CONFIG12_OFFSET (0x24) -#define OSD_DRAW_H_REG_DRAW_X_MIN_12 OSD_DRAW_H_REG_DRAW_X_MIN_12 -#define OSD_DRAW_H_REG_DRAW_X_MIN_12_POS (0U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_12_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_12_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MIN_12_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_12_POS) -#define OSD_DRAW_H_REG_DRAW_X_MIN_12_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MIN_12_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_12_POS)) -#define OSD_DRAW_H_REG_DRAW_X_MAX_12 OSD_DRAW_H_REG_DRAW_X_MAX_12 -#define OSD_DRAW_H_REG_DRAW_X_MAX_12_POS (16U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_12_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_12_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MAX_12_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_12_POS) -#define OSD_DRAW_H_REG_DRAW_X_MAX_12_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MAX_12_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_12_POS)) - -/* 0x28 : draw_partial_y_config12 */ -#define OSD_DRAW_H_DRAW_PARTIAL_Y_CONFIG12_OFFSET (0x28) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_12 OSD_DRAW_H_REG_DRAW_Y_MIN_12 -#define OSD_DRAW_H_REG_DRAW_Y_MIN_12_POS (0U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_12_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_12_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_12_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_12_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_12_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_12_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_12_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_12 OSD_DRAW_H_REG_DRAW_Y_MAX_12 -#define OSD_DRAW_H_REG_DRAW_Y_MAX_12_POS (16U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_12_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_12_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_12_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_12_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_12_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_12_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_12_POS)) - -/* 0x2C : draw_partial_yuv_config13 */ -#define OSD_DRAW_H_DRAW_PARTIAL_YUV_CONFIG13_OFFSET (0x2C) -#define OSD_DRAW_H_REG_DRAW_TH_13 OSD_DRAW_H_REG_DRAW_TH_13 -#define OSD_DRAW_H_REG_DRAW_TH_13_POS (0U) -#define OSD_DRAW_H_REG_DRAW_TH_13_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_TH_13_MSK (((1U << OSD_DRAW_H_REG_DRAW_TH_13_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_13_POS) -#define OSD_DRAW_H_REG_DRAW_TH_13_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_TH_13_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_13_POS)) -#define OSD_DRAW_H_REG_DRAW_V_13 OSD_DRAW_H_REG_DRAW_V_13 -#define OSD_DRAW_H_REG_DRAW_V_13_POS (8U) -#define OSD_DRAW_H_REG_DRAW_V_13_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_V_13_MSK (((1U << OSD_DRAW_H_REG_DRAW_V_13_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_13_POS) -#define OSD_DRAW_H_REG_DRAW_V_13_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_V_13_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_13_POS)) -#define OSD_DRAW_H_REG_DRAW_U_13 OSD_DRAW_H_REG_DRAW_U_13 -#define OSD_DRAW_H_REG_DRAW_U_13_POS (16U) -#define OSD_DRAW_H_REG_DRAW_U_13_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_U_13_MSK (((1U << OSD_DRAW_H_REG_DRAW_U_13_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_13_POS) -#define OSD_DRAW_H_REG_DRAW_U_13_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_U_13_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_13_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_13 OSD_DRAW_H_REG_DRAW_Y_13 -#define OSD_DRAW_H_REG_DRAW_Y_13_POS (24U) -#define OSD_DRAW_H_REG_DRAW_Y_13_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_Y_13_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_13_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_13_POS) -#define OSD_DRAW_H_REG_DRAW_Y_13_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_13_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_13_POS)) - -/* 0x30 : draw_partial_x_config13 */ -#define OSD_DRAW_H_DRAW_PARTIAL_X_CONFIG13_OFFSET (0x30) -#define OSD_DRAW_H_REG_DRAW_X_MIN_13 OSD_DRAW_H_REG_DRAW_X_MIN_13 -#define OSD_DRAW_H_REG_DRAW_X_MIN_13_POS (0U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_13_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_13_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MIN_13_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_13_POS) -#define OSD_DRAW_H_REG_DRAW_X_MIN_13_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MIN_13_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_13_POS)) -#define OSD_DRAW_H_REG_DRAW_X_MAX_13 OSD_DRAW_H_REG_DRAW_X_MAX_13 -#define OSD_DRAW_H_REG_DRAW_X_MAX_13_POS (16U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_13_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_13_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MAX_13_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_13_POS) -#define OSD_DRAW_H_REG_DRAW_X_MAX_13_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MAX_13_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_13_POS)) - -/* 0x34 : draw_partial_y_config13 */ -#define OSD_DRAW_H_DRAW_PARTIAL_Y_CONFIG13_OFFSET (0x34) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_13 OSD_DRAW_H_REG_DRAW_Y_MIN_13 -#define OSD_DRAW_H_REG_DRAW_Y_MIN_13_POS (0U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_13_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_13_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_13_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_13_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_13_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_13_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_13_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_13 OSD_DRAW_H_REG_DRAW_Y_MAX_13 -#define OSD_DRAW_H_REG_DRAW_Y_MAX_13_POS (16U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_13_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_13_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_13_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_13_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_13_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_13_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_13_POS)) - -/* 0x38 : draw_partial_yuv_config14 */ -#define OSD_DRAW_H_DRAW_PARTIAL_YUV_CONFIG14_OFFSET (0x38) -#define OSD_DRAW_H_REG_DRAW_TH_14 OSD_DRAW_H_REG_DRAW_TH_14 -#define OSD_DRAW_H_REG_DRAW_TH_14_POS (0U) -#define OSD_DRAW_H_REG_DRAW_TH_14_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_TH_14_MSK (((1U << OSD_DRAW_H_REG_DRAW_TH_14_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_14_POS) -#define OSD_DRAW_H_REG_DRAW_TH_14_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_TH_14_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_14_POS)) -#define OSD_DRAW_H_REG_DRAW_V_14 OSD_DRAW_H_REG_DRAW_V_14 -#define OSD_DRAW_H_REG_DRAW_V_14_POS (8U) -#define OSD_DRAW_H_REG_DRAW_V_14_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_V_14_MSK (((1U << OSD_DRAW_H_REG_DRAW_V_14_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_14_POS) -#define OSD_DRAW_H_REG_DRAW_V_14_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_V_14_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_14_POS)) -#define OSD_DRAW_H_REG_DRAW_U_14 OSD_DRAW_H_REG_DRAW_U_14 -#define OSD_DRAW_H_REG_DRAW_U_14_POS (16U) -#define OSD_DRAW_H_REG_DRAW_U_14_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_U_14_MSK (((1U << OSD_DRAW_H_REG_DRAW_U_14_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_14_POS) -#define OSD_DRAW_H_REG_DRAW_U_14_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_U_14_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_14_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_14 OSD_DRAW_H_REG_DRAW_Y_14 -#define OSD_DRAW_H_REG_DRAW_Y_14_POS (24U) -#define OSD_DRAW_H_REG_DRAW_Y_14_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_Y_14_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_14_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_14_POS) -#define OSD_DRAW_H_REG_DRAW_Y_14_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_14_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_14_POS)) - -/* 0x3C : draw_partial_x_config14 */ -#define OSD_DRAW_H_DRAW_PARTIAL_X_CONFIG14_OFFSET (0x3C) -#define OSD_DRAW_H_REG_DRAW_X_MIN_14 OSD_DRAW_H_REG_DRAW_X_MIN_14 -#define OSD_DRAW_H_REG_DRAW_X_MIN_14_POS (0U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_14_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_14_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MIN_14_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_14_POS) -#define OSD_DRAW_H_REG_DRAW_X_MIN_14_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MIN_14_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_14_POS)) -#define OSD_DRAW_H_REG_DRAW_X_MAX_14 OSD_DRAW_H_REG_DRAW_X_MAX_14 -#define OSD_DRAW_H_REG_DRAW_X_MAX_14_POS (16U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_14_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_14_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MAX_14_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_14_POS) -#define OSD_DRAW_H_REG_DRAW_X_MAX_14_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MAX_14_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_14_POS)) - -/* 0x40 : draw_partial_y_config14 */ -#define OSD_DRAW_H_DRAW_PARTIAL_Y_CONFIG14_OFFSET (0x40) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_14 OSD_DRAW_H_REG_DRAW_Y_MIN_14 -#define OSD_DRAW_H_REG_DRAW_Y_MIN_14_POS (0U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_14_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_14_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_14_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_14_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_14_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_14_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_14_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_14 OSD_DRAW_H_REG_DRAW_Y_MAX_14 -#define OSD_DRAW_H_REG_DRAW_Y_MAX_14_POS (16U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_14_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_14_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_14_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_14_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_14_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_14_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_14_POS)) - -/* 0x44 : draw_partial_yuv_config15 */ -#define OSD_DRAW_H_DRAW_PARTIAL_YUV_CONFIG15_OFFSET (0x44) -#define OSD_DRAW_H_REG_DRAW_TH_15 OSD_DRAW_H_REG_DRAW_TH_15 -#define OSD_DRAW_H_REG_DRAW_TH_15_POS (0U) -#define OSD_DRAW_H_REG_DRAW_TH_15_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_TH_15_MSK (((1U << OSD_DRAW_H_REG_DRAW_TH_15_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_15_POS) -#define OSD_DRAW_H_REG_DRAW_TH_15_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_TH_15_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_15_POS)) -#define OSD_DRAW_H_REG_DRAW_V_15 OSD_DRAW_H_REG_DRAW_V_15 -#define OSD_DRAW_H_REG_DRAW_V_15_POS (8U) -#define OSD_DRAW_H_REG_DRAW_V_15_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_V_15_MSK (((1U << OSD_DRAW_H_REG_DRAW_V_15_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_15_POS) -#define OSD_DRAW_H_REG_DRAW_V_15_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_V_15_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_15_POS)) -#define OSD_DRAW_H_REG_DRAW_U_15 OSD_DRAW_H_REG_DRAW_U_15 -#define OSD_DRAW_H_REG_DRAW_U_15_POS (16U) -#define OSD_DRAW_H_REG_DRAW_U_15_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_U_15_MSK (((1U << OSD_DRAW_H_REG_DRAW_U_15_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_15_POS) -#define OSD_DRAW_H_REG_DRAW_U_15_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_U_15_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_15_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_15 OSD_DRAW_H_REG_DRAW_Y_15 -#define OSD_DRAW_H_REG_DRAW_Y_15_POS (24U) -#define OSD_DRAW_H_REG_DRAW_Y_15_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_Y_15_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_15_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_15_POS) -#define OSD_DRAW_H_REG_DRAW_Y_15_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_15_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_15_POS)) - -/* 0x48 : draw_partial_x_config15 */ -#define OSD_DRAW_H_DRAW_PARTIAL_X_CONFIG15_OFFSET (0x48) -#define OSD_DRAW_H_REG_DRAW_X_MIN_15 OSD_DRAW_H_REG_DRAW_X_MIN_15 -#define OSD_DRAW_H_REG_DRAW_X_MIN_15_POS (0U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_15_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_15_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MIN_15_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_15_POS) -#define OSD_DRAW_H_REG_DRAW_X_MIN_15_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MIN_15_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_15_POS)) -#define OSD_DRAW_H_REG_DRAW_X_MAX_15 OSD_DRAW_H_REG_DRAW_X_MAX_15 -#define OSD_DRAW_H_REG_DRAW_X_MAX_15_POS (16U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_15_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_15_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MAX_15_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_15_POS) -#define OSD_DRAW_H_REG_DRAW_X_MAX_15_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MAX_15_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_15_POS)) - -/* 0x4C : draw_partial_y_config15 */ -#define OSD_DRAW_H_DRAW_PARTIAL_Y_CONFIG15_OFFSET (0x4C) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_15 OSD_DRAW_H_REG_DRAW_Y_MIN_15 -#define OSD_DRAW_H_REG_DRAW_Y_MIN_15_POS (0U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_15_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_15_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_15_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_15_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_15_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_15_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_15_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_15 OSD_DRAW_H_REG_DRAW_Y_MAX_15 -#define OSD_DRAW_H_REG_DRAW_Y_MAX_15_POS (16U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_15_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_15_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_15_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_15_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_15_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_15_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_15_POS)) - -/* 0x50 : draw_partial_yuv_config16 */ -#define OSD_DRAW_H_DRAW_PARTIAL_YUV_CONFIG16_OFFSET (0x50) -#define OSD_DRAW_H_REG_DRAW_TH_16 OSD_DRAW_H_REG_DRAW_TH_16 -#define OSD_DRAW_H_REG_DRAW_TH_16_POS (0U) -#define OSD_DRAW_H_REG_DRAW_TH_16_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_TH_16_MSK (((1U << OSD_DRAW_H_REG_DRAW_TH_16_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_16_POS) -#define OSD_DRAW_H_REG_DRAW_TH_16_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_TH_16_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_16_POS)) -#define OSD_DRAW_H_REG_DRAW_V_16 OSD_DRAW_H_REG_DRAW_V_16 -#define OSD_DRAW_H_REG_DRAW_V_16_POS (8U) -#define OSD_DRAW_H_REG_DRAW_V_16_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_V_16_MSK (((1U << OSD_DRAW_H_REG_DRAW_V_16_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_16_POS) -#define OSD_DRAW_H_REG_DRAW_V_16_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_V_16_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_16_POS)) -#define OSD_DRAW_H_REG_DRAW_U_16 OSD_DRAW_H_REG_DRAW_U_16 -#define OSD_DRAW_H_REG_DRAW_U_16_POS (16U) -#define OSD_DRAW_H_REG_DRAW_U_16_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_U_16_MSK (((1U << OSD_DRAW_H_REG_DRAW_U_16_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_16_POS) -#define OSD_DRAW_H_REG_DRAW_U_16_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_U_16_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_16_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_16 OSD_DRAW_H_REG_DRAW_Y_16 -#define OSD_DRAW_H_REG_DRAW_Y_16_POS (24U) -#define OSD_DRAW_H_REG_DRAW_Y_16_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_Y_16_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_16_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_16_POS) -#define OSD_DRAW_H_REG_DRAW_Y_16_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_16_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_16_POS)) - -/* 0x54 : draw_partial_x_config16 */ -#define OSD_DRAW_H_DRAW_PARTIAL_X_CONFIG16_OFFSET (0x54) -#define OSD_DRAW_H_REG_DRAW_X_MIN_16 OSD_DRAW_H_REG_DRAW_X_MIN_16 -#define OSD_DRAW_H_REG_DRAW_X_MIN_16_POS (0U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_16_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_16_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MIN_16_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_16_POS) -#define OSD_DRAW_H_REG_DRAW_X_MIN_16_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MIN_16_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_16_POS)) -#define OSD_DRAW_H_REG_DRAW_X_MAX_16 OSD_DRAW_H_REG_DRAW_X_MAX_16 -#define OSD_DRAW_H_REG_DRAW_X_MAX_16_POS (16U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_16_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_16_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MAX_16_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_16_POS) -#define OSD_DRAW_H_REG_DRAW_X_MAX_16_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MAX_16_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_16_POS)) - -/* 0x58 : draw_partial_y_config16 */ -#define OSD_DRAW_H_DRAW_PARTIAL_Y_CONFIG16_OFFSET (0x58) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_16 OSD_DRAW_H_REG_DRAW_Y_MIN_16 -#define OSD_DRAW_H_REG_DRAW_Y_MIN_16_POS (0U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_16_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_16_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_16_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_16_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_16_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_16_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_16_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_16 OSD_DRAW_H_REG_DRAW_Y_MAX_16 -#define OSD_DRAW_H_REG_DRAW_Y_MAX_16_POS (16U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_16_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_16_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_16_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_16_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_16_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_16_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_16_POS)) - -/* 0x5C : draw_partial_yuv_config17 */ -#define OSD_DRAW_H_DRAW_PARTIAL_YUV_CONFIG17_OFFSET (0x5C) -#define OSD_DRAW_H_REG_DRAW_TH_17 OSD_DRAW_H_REG_DRAW_TH_17 -#define OSD_DRAW_H_REG_DRAW_TH_17_POS (0U) -#define OSD_DRAW_H_REG_DRAW_TH_17_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_TH_17_MSK (((1U << OSD_DRAW_H_REG_DRAW_TH_17_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_17_POS) -#define OSD_DRAW_H_REG_DRAW_TH_17_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_TH_17_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_17_POS)) -#define OSD_DRAW_H_REG_DRAW_V_17 OSD_DRAW_H_REG_DRAW_V_17 -#define OSD_DRAW_H_REG_DRAW_V_17_POS (8U) -#define OSD_DRAW_H_REG_DRAW_V_17_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_V_17_MSK (((1U << OSD_DRAW_H_REG_DRAW_V_17_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_17_POS) -#define OSD_DRAW_H_REG_DRAW_V_17_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_V_17_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_17_POS)) -#define OSD_DRAW_H_REG_DRAW_U_17 OSD_DRAW_H_REG_DRAW_U_17 -#define OSD_DRAW_H_REG_DRAW_U_17_POS (16U) -#define OSD_DRAW_H_REG_DRAW_U_17_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_U_17_MSK (((1U << OSD_DRAW_H_REG_DRAW_U_17_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_17_POS) -#define OSD_DRAW_H_REG_DRAW_U_17_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_U_17_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_17_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_17 OSD_DRAW_H_REG_DRAW_Y_17 -#define OSD_DRAW_H_REG_DRAW_Y_17_POS (24U) -#define OSD_DRAW_H_REG_DRAW_Y_17_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_Y_17_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_17_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_17_POS) -#define OSD_DRAW_H_REG_DRAW_Y_17_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_17_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_17_POS)) - -/* 0x60 : draw_partial_x_config17 */ -#define OSD_DRAW_H_DRAW_PARTIAL_X_CONFIG17_OFFSET (0x60) -#define OSD_DRAW_H_REG_DRAW_X_MIN_17 OSD_DRAW_H_REG_DRAW_X_MIN_17 -#define OSD_DRAW_H_REG_DRAW_X_MIN_17_POS (0U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_17_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_17_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MIN_17_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_17_POS) -#define OSD_DRAW_H_REG_DRAW_X_MIN_17_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MIN_17_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_17_POS)) -#define OSD_DRAW_H_REG_DRAW_X_MAX_17 OSD_DRAW_H_REG_DRAW_X_MAX_17 -#define OSD_DRAW_H_REG_DRAW_X_MAX_17_POS (16U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_17_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_17_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MAX_17_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_17_POS) -#define OSD_DRAW_H_REG_DRAW_X_MAX_17_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MAX_17_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_17_POS)) - -/* 0x64 : draw_partial_y_config17 */ -#define OSD_DRAW_H_DRAW_PARTIAL_Y_CONFIG17_OFFSET (0x64) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_17 OSD_DRAW_H_REG_DRAW_Y_MIN_17 -#define OSD_DRAW_H_REG_DRAW_Y_MIN_17_POS (0U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_17_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_17_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_17_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_17_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_17_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_17_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_17_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_17 OSD_DRAW_H_REG_DRAW_Y_MAX_17 -#define OSD_DRAW_H_REG_DRAW_Y_MAX_17_POS (16U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_17_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_17_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_17_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_17_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_17_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_17_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_17_POS)) - -/* 0x68 : draw_partial_yuv_config18 */ -#define OSD_DRAW_H_DRAW_PARTIAL_YUV_CONFIG18_OFFSET (0x68) -#define OSD_DRAW_H_REG_DRAW_TH_18 OSD_DRAW_H_REG_DRAW_TH_18 -#define OSD_DRAW_H_REG_DRAW_TH_18_POS (0U) -#define OSD_DRAW_H_REG_DRAW_TH_18_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_TH_18_MSK (((1U << OSD_DRAW_H_REG_DRAW_TH_18_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_18_POS) -#define OSD_DRAW_H_REG_DRAW_TH_18_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_TH_18_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_18_POS)) -#define OSD_DRAW_H_REG_DRAW_V_18 OSD_DRAW_H_REG_DRAW_V_18 -#define OSD_DRAW_H_REG_DRAW_V_18_POS (8U) -#define OSD_DRAW_H_REG_DRAW_V_18_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_V_18_MSK (((1U << OSD_DRAW_H_REG_DRAW_V_18_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_18_POS) -#define OSD_DRAW_H_REG_DRAW_V_18_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_V_18_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_18_POS)) -#define OSD_DRAW_H_REG_DRAW_U_18 OSD_DRAW_H_REG_DRAW_U_18 -#define OSD_DRAW_H_REG_DRAW_U_18_POS (16U) -#define OSD_DRAW_H_REG_DRAW_U_18_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_U_18_MSK (((1U << OSD_DRAW_H_REG_DRAW_U_18_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_18_POS) -#define OSD_DRAW_H_REG_DRAW_U_18_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_U_18_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_18_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_18 OSD_DRAW_H_REG_DRAW_Y_18 -#define OSD_DRAW_H_REG_DRAW_Y_18_POS (24U) -#define OSD_DRAW_H_REG_DRAW_Y_18_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_Y_18_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_18_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_18_POS) -#define OSD_DRAW_H_REG_DRAW_Y_18_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_18_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_18_POS)) - -/* 0x6C : draw_partial_x_config18 */ -#define OSD_DRAW_H_DRAW_PARTIAL_X_CONFIG18_OFFSET (0x6C) -#define OSD_DRAW_H_REG_DRAW_X_MIN_18 OSD_DRAW_H_REG_DRAW_X_MIN_18 -#define OSD_DRAW_H_REG_DRAW_X_MIN_18_POS (0U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_18_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_18_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MIN_18_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_18_POS) -#define OSD_DRAW_H_REG_DRAW_X_MIN_18_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MIN_18_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_18_POS)) -#define OSD_DRAW_H_REG_DRAW_X_MAX_18 OSD_DRAW_H_REG_DRAW_X_MAX_18 -#define OSD_DRAW_H_REG_DRAW_X_MAX_18_POS (16U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_18_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_18_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MAX_18_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_18_POS) -#define OSD_DRAW_H_REG_DRAW_X_MAX_18_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MAX_18_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_18_POS)) - -/* 0x70 : draw_partial_y_config18 */ -#define OSD_DRAW_H_DRAW_PARTIAL_Y_CONFIG18_OFFSET (0x70) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_18 OSD_DRAW_H_REG_DRAW_Y_MIN_18 -#define OSD_DRAW_H_REG_DRAW_Y_MIN_18_POS (0U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_18_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_18_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_18_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_18_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_18_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_18_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_18_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_18 OSD_DRAW_H_REG_DRAW_Y_MAX_18 -#define OSD_DRAW_H_REG_DRAW_Y_MAX_18_POS (16U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_18_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_18_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_18_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_18_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_18_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_18_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_18_POS)) - -/* 0x74 : draw_partial_yuv_config19 */ -#define OSD_DRAW_H_DRAW_PARTIAL_YUV_CONFIG19_OFFSET (0x74) -#define OSD_DRAW_H_REG_DRAW_TH_19 OSD_DRAW_H_REG_DRAW_TH_19 -#define OSD_DRAW_H_REG_DRAW_TH_19_POS (0U) -#define OSD_DRAW_H_REG_DRAW_TH_19_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_TH_19_MSK (((1U << OSD_DRAW_H_REG_DRAW_TH_19_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_19_POS) -#define OSD_DRAW_H_REG_DRAW_TH_19_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_TH_19_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_19_POS)) -#define OSD_DRAW_H_REG_DRAW_V_19 OSD_DRAW_H_REG_DRAW_V_19 -#define OSD_DRAW_H_REG_DRAW_V_19_POS (8U) -#define OSD_DRAW_H_REG_DRAW_V_19_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_V_19_MSK (((1U << OSD_DRAW_H_REG_DRAW_V_19_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_19_POS) -#define OSD_DRAW_H_REG_DRAW_V_19_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_V_19_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_19_POS)) -#define OSD_DRAW_H_REG_DRAW_U_19 OSD_DRAW_H_REG_DRAW_U_19 -#define OSD_DRAW_H_REG_DRAW_U_19_POS (16U) -#define OSD_DRAW_H_REG_DRAW_U_19_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_U_19_MSK (((1U << OSD_DRAW_H_REG_DRAW_U_19_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_19_POS) -#define OSD_DRAW_H_REG_DRAW_U_19_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_U_19_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_19_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_19 OSD_DRAW_H_REG_DRAW_Y_19 -#define OSD_DRAW_H_REG_DRAW_Y_19_POS (24U) -#define OSD_DRAW_H_REG_DRAW_Y_19_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_Y_19_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_19_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_19_POS) -#define OSD_DRAW_H_REG_DRAW_Y_19_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_19_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_19_POS)) - -/* 0x78 : draw_partial_x_config19 */ -#define OSD_DRAW_H_DRAW_PARTIAL_X_CONFIG19_OFFSET (0x78) -#define OSD_DRAW_H_REG_DRAW_X_MIN_19 OSD_DRAW_H_REG_DRAW_X_MIN_19 -#define OSD_DRAW_H_REG_DRAW_X_MIN_19_POS (0U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_19_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_19_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MIN_19_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_19_POS) -#define OSD_DRAW_H_REG_DRAW_X_MIN_19_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MIN_19_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_19_POS)) -#define OSD_DRAW_H_REG_DRAW_X_MAX_19 OSD_DRAW_H_REG_DRAW_X_MAX_19 -#define OSD_DRAW_H_REG_DRAW_X_MAX_19_POS (16U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_19_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_19_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MAX_19_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_19_POS) -#define OSD_DRAW_H_REG_DRAW_X_MAX_19_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MAX_19_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_19_POS)) - -/* 0x7C : draw_partial_y_config19 */ -#define OSD_DRAW_H_DRAW_PARTIAL_Y_CONFIG19_OFFSET (0x7C) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_19 OSD_DRAW_H_REG_DRAW_Y_MIN_19 -#define OSD_DRAW_H_REG_DRAW_Y_MIN_19_POS (0U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_19_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_19_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_19_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_19_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_19_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_19_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_19_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_19 OSD_DRAW_H_REG_DRAW_Y_MAX_19 -#define OSD_DRAW_H_REG_DRAW_Y_MAX_19_POS (16U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_19_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_19_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_19_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_19_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_19_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_19_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_19_POS)) - -/* 0x80 : draw_partial_yuv_config1a */ -#define OSD_DRAW_H_DRAW_PARTIAL_YUV_CONFIG1A_OFFSET (0x80) -#define OSD_DRAW_H_REG_DRAW_TH_1A OSD_DRAW_H_REG_DRAW_TH_1A -#define OSD_DRAW_H_REG_DRAW_TH_1A_POS (0U) -#define OSD_DRAW_H_REG_DRAW_TH_1A_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_TH_1A_MSK (((1U << OSD_DRAW_H_REG_DRAW_TH_1A_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_1A_POS) -#define OSD_DRAW_H_REG_DRAW_TH_1A_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_TH_1A_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_1A_POS)) -#define OSD_DRAW_H_REG_DRAW_V_1A OSD_DRAW_H_REG_DRAW_V_1A -#define OSD_DRAW_H_REG_DRAW_V_1A_POS (8U) -#define OSD_DRAW_H_REG_DRAW_V_1A_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_V_1A_MSK (((1U << OSD_DRAW_H_REG_DRAW_V_1A_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_1A_POS) -#define OSD_DRAW_H_REG_DRAW_V_1A_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_V_1A_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_1A_POS)) -#define OSD_DRAW_H_REG_DRAW_U_1A OSD_DRAW_H_REG_DRAW_U_1A -#define OSD_DRAW_H_REG_DRAW_U_1A_POS (16U) -#define OSD_DRAW_H_REG_DRAW_U_1A_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_U_1A_MSK (((1U << OSD_DRAW_H_REG_DRAW_U_1A_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_1A_POS) -#define OSD_DRAW_H_REG_DRAW_U_1A_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_U_1A_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_1A_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_1A OSD_DRAW_H_REG_DRAW_Y_1A -#define OSD_DRAW_H_REG_DRAW_Y_1A_POS (24U) -#define OSD_DRAW_H_REG_DRAW_Y_1A_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_Y_1A_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_1A_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_1A_POS) -#define OSD_DRAW_H_REG_DRAW_Y_1A_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_1A_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_1A_POS)) - -/* 0x84 : draw_partial_x_config1a */ -#define OSD_DRAW_H_DRAW_PARTIAL_X_CONFIG1A_OFFSET (0x84) -#define OSD_DRAW_H_REG_DRAW_X_MIN_1A OSD_DRAW_H_REG_DRAW_X_MIN_1A -#define OSD_DRAW_H_REG_DRAW_X_MIN_1A_POS (0U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_1A_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_1A_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MIN_1A_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_1A_POS) -#define OSD_DRAW_H_REG_DRAW_X_MIN_1A_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MIN_1A_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_1A_POS)) -#define OSD_DRAW_H_REG_DRAW_X_MAX_1A OSD_DRAW_H_REG_DRAW_X_MAX_1A -#define OSD_DRAW_H_REG_DRAW_X_MAX_1A_POS (16U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_1A_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_1A_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MAX_1A_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_1A_POS) -#define OSD_DRAW_H_REG_DRAW_X_MAX_1A_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MAX_1A_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_1A_POS)) - -/* 0x88 : draw_partial_y_config1a */ -#define OSD_DRAW_H_DRAW_PARTIAL_Y_CONFIG1A_OFFSET (0x88) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1A OSD_DRAW_H_REG_DRAW_Y_MIN_1A -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1A_POS (0U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1A_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1A_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_1A_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_1A_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1A_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_1A_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_1A_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1A OSD_DRAW_H_REG_DRAW_Y_MAX_1A -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1A_POS (16U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1A_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1A_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_1A_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_1A_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1A_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_1A_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_1A_POS)) - -/* 0x8C : draw_partial_yuv_config1b */ -#define OSD_DRAW_H_DRAW_PARTIAL_YUV_CONFIG1B_OFFSET (0x8C) -#define OSD_DRAW_H_REG_DRAW_TH_1B OSD_DRAW_H_REG_DRAW_TH_1B -#define OSD_DRAW_H_REG_DRAW_TH_1B_POS (0U) -#define OSD_DRAW_H_REG_DRAW_TH_1B_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_TH_1B_MSK (((1U << OSD_DRAW_H_REG_DRAW_TH_1B_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_1B_POS) -#define OSD_DRAW_H_REG_DRAW_TH_1B_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_TH_1B_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_1B_POS)) -#define OSD_DRAW_H_REG_DRAW_V_1B OSD_DRAW_H_REG_DRAW_V_1B -#define OSD_DRAW_H_REG_DRAW_V_1B_POS (8U) -#define OSD_DRAW_H_REG_DRAW_V_1B_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_V_1B_MSK (((1U << OSD_DRAW_H_REG_DRAW_V_1B_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_1B_POS) -#define OSD_DRAW_H_REG_DRAW_V_1B_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_V_1B_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_1B_POS)) -#define OSD_DRAW_H_REG_DRAW_U_1B OSD_DRAW_H_REG_DRAW_U_1B -#define OSD_DRAW_H_REG_DRAW_U_1B_POS (16U) -#define OSD_DRAW_H_REG_DRAW_U_1B_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_U_1B_MSK (((1U << OSD_DRAW_H_REG_DRAW_U_1B_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_1B_POS) -#define OSD_DRAW_H_REG_DRAW_U_1B_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_U_1B_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_1B_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_1B OSD_DRAW_H_REG_DRAW_Y_1B -#define OSD_DRAW_H_REG_DRAW_Y_1B_POS (24U) -#define OSD_DRAW_H_REG_DRAW_Y_1B_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_Y_1B_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_1B_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_1B_POS) -#define OSD_DRAW_H_REG_DRAW_Y_1B_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_1B_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_1B_POS)) - -/* 0x90 : draw_partial_x_config1b */ -#define OSD_DRAW_H_DRAW_PARTIAL_X_CONFIG1B_OFFSET (0x90) -#define OSD_DRAW_H_REG_DRAW_X_MIN_1B OSD_DRAW_H_REG_DRAW_X_MIN_1B -#define OSD_DRAW_H_REG_DRAW_X_MIN_1B_POS (0U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_1B_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_1B_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MIN_1B_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_1B_POS) -#define OSD_DRAW_H_REG_DRAW_X_MIN_1B_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MIN_1B_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_1B_POS)) -#define OSD_DRAW_H_REG_DRAW_X_MAX_1B OSD_DRAW_H_REG_DRAW_X_MAX_1B -#define OSD_DRAW_H_REG_DRAW_X_MAX_1B_POS (16U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_1B_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_1B_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MAX_1B_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_1B_POS) -#define OSD_DRAW_H_REG_DRAW_X_MAX_1B_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MAX_1B_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_1B_POS)) - -/* 0x94 : draw_partial_y_config1b */ -#define OSD_DRAW_H_DRAW_PARTIAL_Y_CONFIG1B_OFFSET (0x94) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1B OSD_DRAW_H_REG_DRAW_Y_MIN_1B -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1B_POS (0U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1B_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1B_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_1B_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_1B_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1B_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_1B_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_1B_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1B OSD_DRAW_H_REG_DRAW_Y_MAX_1B -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1B_POS (16U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1B_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1B_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_1B_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_1B_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1B_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_1B_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_1B_POS)) - -/* 0x98 : draw_partial_yuv_config1c */ -#define OSD_DRAW_H_DRAW_PARTIAL_YUV_CONFIG1C_OFFSET (0x98) -#define OSD_DRAW_H_REG_DRAW_TH_1C OSD_DRAW_H_REG_DRAW_TH_1C -#define OSD_DRAW_H_REG_DRAW_TH_1C_POS (0U) -#define OSD_DRAW_H_REG_DRAW_TH_1C_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_TH_1C_MSK (((1U << OSD_DRAW_H_REG_DRAW_TH_1C_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_1C_POS) -#define OSD_DRAW_H_REG_DRAW_TH_1C_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_TH_1C_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_1C_POS)) -#define OSD_DRAW_H_REG_DRAW_V_1C OSD_DRAW_H_REG_DRAW_V_1C -#define OSD_DRAW_H_REG_DRAW_V_1C_POS (8U) -#define OSD_DRAW_H_REG_DRAW_V_1C_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_V_1C_MSK (((1U << OSD_DRAW_H_REG_DRAW_V_1C_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_1C_POS) -#define OSD_DRAW_H_REG_DRAW_V_1C_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_V_1C_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_1C_POS)) -#define OSD_DRAW_H_REG_DRAW_U_1C OSD_DRAW_H_REG_DRAW_U_1C -#define OSD_DRAW_H_REG_DRAW_U_1C_POS (16U) -#define OSD_DRAW_H_REG_DRAW_U_1C_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_U_1C_MSK (((1U << OSD_DRAW_H_REG_DRAW_U_1C_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_1C_POS) -#define OSD_DRAW_H_REG_DRAW_U_1C_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_U_1C_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_1C_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_1C OSD_DRAW_H_REG_DRAW_Y_1C -#define OSD_DRAW_H_REG_DRAW_Y_1C_POS (24U) -#define OSD_DRAW_H_REG_DRAW_Y_1C_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_Y_1C_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_1C_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_1C_POS) -#define OSD_DRAW_H_REG_DRAW_Y_1C_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_1C_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_1C_POS)) - -/* 0x9C : draw_partial_x_config1c */ -#define OSD_DRAW_H_DRAW_PARTIAL_X_CONFIG1C_OFFSET (0x9C) -#define OSD_DRAW_H_REG_DRAW_X_MIN_1C OSD_DRAW_H_REG_DRAW_X_MIN_1C -#define OSD_DRAW_H_REG_DRAW_X_MIN_1C_POS (0U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_1C_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_1C_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MIN_1C_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_1C_POS) -#define OSD_DRAW_H_REG_DRAW_X_MIN_1C_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MIN_1C_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_1C_POS)) -#define OSD_DRAW_H_REG_DRAW_X_MAX_1C OSD_DRAW_H_REG_DRAW_X_MAX_1C -#define OSD_DRAW_H_REG_DRAW_X_MAX_1C_POS (16U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_1C_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_1C_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MAX_1C_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_1C_POS) -#define OSD_DRAW_H_REG_DRAW_X_MAX_1C_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MAX_1C_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_1C_POS)) - -/* 0xA0 : draw_partial_y_config1c */ -#define OSD_DRAW_H_DRAW_PARTIAL_Y_CONFIG1C_OFFSET (0xA0) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1C OSD_DRAW_H_REG_DRAW_Y_MIN_1C -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1C_POS (0U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1C_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1C_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_1C_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_1C_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1C_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_1C_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_1C_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1C OSD_DRAW_H_REG_DRAW_Y_MAX_1C -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1C_POS (16U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1C_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1C_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_1C_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_1C_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1C_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_1C_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_1C_POS)) - -/* 0xA4 : draw_partial_yuv_config1d */ -#define OSD_DRAW_H_DRAW_PARTIAL_YUV_CONFIG1D_OFFSET (0xA4) -#define OSD_DRAW_H_REG_DRAW_TH_1D OSD_DRAW_H_REG_DRAW_TH_1D -#define OSD_DRAW_H_REG_DRAW_TH_1D_POS (0U) -#define OSD_DRAW_H_REG_DRAW_TH_1D_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_TH_1D_MSK (((1U << OSD_DRAW_H_REG_DRAW_TH_1D_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_1D_POS) -#define OSD_DRAW_H_REG_DRAW_TH_1D_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_TH_1D_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_1D_POS)) -#define OSD_DRAW_H_REG_DRAW_V_1D OSD_DRAW_H_REG_DRAW_V_1D -#define OSD_DRAW_H_REG_DRAW_V_1D_POS (8U) -#define OSD_DRAW_H_REG_DRAW_V_1D_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_V_1D_MSK (((1U << OSD_DRAW_H_REG_DRAW_V_1D_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_1D_POS) -#define OSD_DRAW_H_REG_DRAW_V_1D_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_V_1D_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_1D_POS)) -#define OSD_DRAW_H_REG_DRAW_U_1D OSD_DRAW_H_REG_DRAW_U_1D -#define OSD_DRAW_H_REG_DRAW_U_1D_POS (16U) -#define OSD_DRAW_H_REG_DRAW_U_1D_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_U_1D_MSK (((1U << OSD_DRAW_H_REG_DRAW_U_1D_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_1D_POS) -#define OSD_DRAW_H_REG_DRAW_U_1D_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_U_1D_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_1D_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_1D OSD_DRAW_H_REG_DRAW_Y_1D -#define OSD_DRAW_H_REG_DRAW_Y_1D_POS (24U) -#define OSD_DRAW_H_REG_DRAW_Y_1D_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_Y_1D_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_1D_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_1D_POS) -#define OSD_DRAW_H_REG_DRAW_Y_1D_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_1D_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_1D_POS)) - -/* 0xA8 : draw_partial_x_config1d */ -#define OSD_DRAW_H_DRAW_PARTIAL_X_CONFIG1D_OFFSET (0xA8) -#define OSD_DRAW_H_REG_DRAW_X_MIN_1D OSD_DRAW_H_REG_DRAW_X_MIN_1D -#define OSD_DRAW_H_REG_DRAW_X_MIN_1D_POS (0U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_1D_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_1D_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MIN_1D_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_1D_POS) -#define OSD_DRAW_H_REG_DRAW_X_MIN_1D_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MIN_1D_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_1D_POS)) -#define OSD_DRAW_H_REG_DRAW_X_MAX_1D OSD_DRAW_H_REG_DRAW_X_MAX_1D -#define OSD_DRAW_H_REG_DRAW_X_MAX_1D_POS (16U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_1D_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_1D_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MAX_1D_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_1D_POS) -#define OSD_DRAW_H_REG_DRAW_X_MAX_1D_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MAX_1D_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_1D_POS)) - -/* 0xAC : draw_partial_y_config1d */ -#define OSD_DRAW_H_DRAW_PARTIAL_Y_CONFIG1D_OFFSET (0xAC) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1D OSD_DRAW_H_REG_DRAW_Y_MIN_1D -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1D_POS (0U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1D_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1D_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_1D_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_1D_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1D_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_1D_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_1D_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1D OSD_DRAW_H_REG_DRAW_Y_MAX_1D -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1D_POS (16U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1D_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1D_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_1D_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_1D_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1D_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_1D_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_1D_POS)) - -/* 0xB0 : draw_partial_yuv_config1e */ -#define OSD_DRAW_H_DRAW_PARTIAL_YUV_CONFIG1E_OFFSET (0xB0) -#define OSD_DRAW_H_REG_DRAW_TH_1E OSD_DRAW_H_REG_DRAW_TH_1E -#define OSD_DRAW_H_REG_DRAW_TH_1E_POS (0U) -#define OSD_DRAW_H_REG_DRAW_TH_1E_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_TH_1E_MSK (((1U << OSD_DRAW_H_REG_DRAW_TH_1E_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_1E_POS) -#define OSD_DRAW_H_REG_DRAW_TH_1E_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_TH_1E_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_1E_POS)) -#define OSD_DRAW_H_REG_DRAW_V_1E OSD_DRAW_H_REG_DRAW_V_1E -#define OSD_DRAW_H_REG_DRAW_V_1E_POS (8U) -#define OSD_DRAW_H_REG_DRAW_V_1E_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_V_1E_MSK (((1U << OSD_DRAW_H_REG_DRAW_V_1E_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_1E_POS) -#define OSD_DRAW_H_REG_DRAW_V_1E_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_V_1E_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_1E_POS)) -#define OSD_DRAW_H_REG_DRAW_U_1E OSD_DRAW_H_REG_DRAW_U_1E -#define OSD_DRAW_H_REG_DRAW_U_1E_POS (16U) -#define OSD_DRAW_H_REG_DRAW_U_1E_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_U_1E_MSK (((1U << OSD_DRAW_H_REG_DRAW_U_1E_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_1E_POS) -#define OSD_DRAW_H_REG_DRAW_U_1E_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_U_1E_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_1E_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_1E OSD_DRAW_H_REG_DRAW_Y_1E -#define OSD_DRAW_H_REG_DRAW_Y_1E_POS (24U) -#define OSD_DRAW_H_REG_DRAW_Y_1E_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_Y_1E_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_1E_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_1E_POS) -#define OSD_DRAW_H_REG_DRAW_Y_1E_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_1E_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_1E_POS)) - -/* 0xB4 : draw_partial_x_config1e */ -#define OSD_DRAW_H_DRAW_PARTIAL_X_CONFIG1E_OFFSET (0xB4) -#define OSD_DRAW_H_REG_DRAW_X_MIN_1E OSD_DRAW_H_REG_DRAW_X_MIN_1E -#define OSD_DRAW_H_REG_DRAW_X_MIN_1E_POS (0U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_1E_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_1E_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MIN_1E_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_1E_POS) -#define OSD_DRAW_H_REG_DRAW_X_MIN_1E_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MIN_1E_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_1E_POS)) -#define OSD_DRAW_H_REG_DRAW_X_MAX_1E OSD_DRAW_H_REG_DRAW_X_MAX_1E -#define OSD_DRAW_H_REG_DRAW_X_MAX_1E_POS (16U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_1E_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_1E_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MAX_1E_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_1E_POS) -#define OSD_DRAW_H_REG_DRAW_X_MAX_1E_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MAX_1E_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_1E_POS)) - -/* 0xB8 : draw_partial_y_config1e */ -#define OSD_DRAW_H_DRAW_PARTIAL_Y_CONFIG1E_OFFSET (0xB8) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1E OSD_DRAW_H_REG_DRAW_Y_MIN_1E -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1E_POS (0U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1E_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1E_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_1E_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_1E_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1E_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_1E_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_1E_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1E OSD_DRAW_H_REG_DRAW_Y_MAX_1E -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1E_POS (16U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1E_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1E_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_1E_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_1E_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1E_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_1E_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_1E_POS)) - -/* 0xBC : draw_partial_yuv_config1f */ -#define OSD_DRAW_H_DRAW_PARTIAL_YUV_CONFIG1F_OFFSET (0xBC) -#define OSD_DRAW_H_REG_DRAW_TH_1F OSD_DRAW_H_REG_DRAW_TH_1F -#define OSD_DRAW_H_REG_DRAW_TH_1F_POS (0U) -#define OSD_DRAW_H_REG_DRAW_TH_1F_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_TH_1F_MSK (((1U << OSD_DRAW_H_REG_DRAW_TH_1F_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_1F_POS) -#define OSD_DRAW_H_REG_DRAW_TH_1F_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_TH_1F_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_1F_POS)) -#define OSD_DRAW_H_REG_DRAW_V_1F OSD_DRAW_H_REG_DRAW_V_1F -#define OSD_DRAW_H_REG_DRAW_V_1F_POS (8U) -#define OSD_DRAW_H_REG_DRAW_V_1F_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_V_1F_MSK (((1U << OSD_DRAW_H_REG_DRAW_V_1F_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_1F_POS) -#define OSD_DRAW_H_REG_DRAW_V_1F_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_V_1F_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_1F_POS)) -#define OSD_DRAW_H_REG_DRAW_U_1F OSD_DRAW_H_REG_DRAW_U_1F -#define OSD_DRAW_H_REG_DRAW_U_1F_POS (16U) -#define OSD_DRAW_H_REG_DRAW_U_1F_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_U_1F_MSK (((1U << OSD_DRAW_H_REG_DRAW_U_1F_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_1F_POS) -#define OSD_DRAW_H_REG_DRAW_U_1F_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_U_1F_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_1F_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_1F OSD_DRAW_H_REG_DRAW_Y_1F -#define OSD_DRAW_H_REG_DRAW_Y_1F_POS (24U) -#define OSD_DRAW_H_REG_DRAW_Y_1F_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_Y_1F_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_1F_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_1F_POS) -#define OSD_DRAW_H_REG_DRAW_Y_1F_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_1F_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_1F_POS)) - -/* 0xC0 : draw_partial_x_config1f */ -#define OSD_DRAW_H_DRAW_PARTIAL_X_CONFIG1F_OFFSET (0xC0) -#define OSD_DRAW_H_REG_DRAW_X_MIN_1F OSD_DRAW_H_REG_DRAW_X_MIN_1F -#define OSD_DRAW_H_REG_DRAW_X_MIN_1F_POS (0U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_1F_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_1F_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MIN_1F_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_1F_POS) -#define OSD_DRAW_H_REG_DRAW_X_MIN_1F_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MIN_1F_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_1F_POS)) -#define OSD_DRAW_H_REG_DRAW_X_MAX_1F OSD_DRAW_H_REG_DRAW_X_MAX_1F -#define OSD_DRAW_H_REG_DRAW_X_MAX_1F_POS (16U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_1F_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_1F_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MAX_1F_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_1F_POS) -#define OSD_DRAW_H_REG_DRAW_X_MAX_1F_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MAX_1F_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_1F_POS)) - -/* 0xC4 : draw_partial_y_config1f */ -#define OSD_DRAW_H_DRAW_PARTIAL_Y_CONFIG1F_OFFSET (0xC4) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1F OSD_DRAW_H_REG_DRAW_Y_MIN_1F -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1F_POS (0U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1F_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1F_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_1F_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_1F_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1F_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_1F_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_1F_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1F OSD_DRAW_H_REG_DRAW_Y_MAX_1F -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1F_POS (16U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1F_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1F_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_1F_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_1F_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1F_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_1F_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_1F_POS)) - -struct osd_draw_h_reg { - /* 0x0 reserved */ - uint8_t RESERVED0x0[4]; - - /* 0x4 : draw_partial_config */ - union { - struct { - uint32_t reg_draw_en_h : 16; /* [15: 0], r/w, 0x0 */ - uint32_t reg_draw_type_h : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_config; - - /* 0x8 : draw_partial_yuv_config10 */ - union { - struct { - uint32_t reg_draw_th_10 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_10 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_10 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_10 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config10; - - /* 0xC : draw_partial_x_config10 */ - union { - struct { - uint32_t reg_draw_x_min_10 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_10 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config10; - - /* 0x10 : draw_partial_y_config10 */ - union { - struct { - uint32_t reg_draw_y_min_10 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_10 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config10; - - /* 0x14 : draw_partial_yuv_config11 */ - union { - struct { - uint32_t reg_draw_th_11 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_11 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_11 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_11 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config11; - - /* 0x18 : draw_partial_x_config11 */ - union { - struct { - uint32_t reg_draw_x_min_11 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_11 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config11; - - /* 0x1C : draw_partial_y_config11 */ - union { - struct { - uint32_t reg_draw_y_min_11 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_11 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config11; - - /* 0x20 : draw_partial_yuv_config12 */ - union { - struct { - uint32_t reg_draw_th_12 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_12 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_12 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_12 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config12; - - /* 0x24 : draw_partial_x_config12 */ - union { - struct { - uint32_t reg_draw_x_min_12 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_12 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config12; - - /* 0x28 : draw_partial_y_config12 */ - union { - struct { - uint32_t reg_draw_y_min_12 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_12 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config12; - - /* 0x2C : draw_partial_yuv_config13 */ - union { - struct { - uint32_t reg_draw_th_13 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_13 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_13 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_13 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config13; - - /* 0x30 : draw_partial_x_config13 */ - union { - struct { - uint32_t reg_draw_x_min_13 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_13 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config13; - - /* 0x34 : draw_partial_y_config13 */ - union { - struct { - uint32_t reg_draw_y_min_13 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_13 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config13; - - /* 0x38 : draw_partial_yuv_config14 */ - union { - struct { - uint32_t reg_draw_th_14 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_14 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_14 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_14 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config14; - - /* 0x3C : draw_partial_x_config14 */ - union { - struct { - uint32_t reg_draw_x_min_14 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_14 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config14; - - /* 0x40 : draw_partial_y_config14 */ - union { - struct { - uint32_t reg_draw_y_min_14 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_14 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config14; - - /* 0x44 : draw_partial_yuv_config15 */ - union { - struct { - uint32_t reg_draw_th_15 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_15 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_15 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_15 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config15; - - /* 0x48 : draw_partial_x_config15 */ - union { - struct { - uint32_t reg_draw_x_min_15 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_15 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config15; - - /* 0x4C : draw_partial_y_config15 */ - union { - struct { - uint32_t reg_draw_y_min_15 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_15 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config15; - - /* 0x50 : draw_partial_yuv_config16 */ - union { - struct { - uint32_t reg_draw_th_16 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_16 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_16 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_16 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config16; - - /* 0x54 : draw_partial_x_config16 */ - union { - struct { - uint32_t reg_draw_x_min_16 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_16 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config16; - - /* 0x58 : draw_partial_y_config16 */ - union { - struct { - uint32_t reg_draw_y_min_16 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_16 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config16; - - /* 0x5C : draw_partial_yuv_config17 */ - union { - struct { - uint32_t reg_draw_th_17 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_17 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_17 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_17 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config17; - - /* 0x60 : draw_partial_x_config17 */ - union { - struct { - uint32_t reg_draw_x_min_17 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_17 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config17; - - /* 0x64 : draw_partial_y_config17 */ - union { - struct { - uint32_t reg_draw_y_min_17 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_17 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config17; - - /* 0x68 : draw_partial_yuv_config18 */ - union { - struct { - uint32_t reg_draw_th_18 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_18 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_18 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_18 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config18; - - /* 0x6C : draw_partial_x_config18 */ - union { - struct { - uint32_t reg_draw_x_min_18 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_18 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config18; - - /* 0x70 : draw_partial_y_config18 */ - union { - struct { - uint32_t reg_draw_y_min_18 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_18 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config18; - - /* 0x74 : draw_partial_yuv_config19 */ - union { - struct { - uint32_t reg_draw_th_19 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_19 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_19 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_19 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config19; - - /* 0x78 : draw_partial_x_config19 */ - union { - struct { - uint32_t reg_draw_x_min_19 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_19 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config19; - - /* 0x7C : draw_partial_y_config19 */ - union { - struct { - uint32_t reg_draw_y_min_19 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_19 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config19; - - /* 0x80 : draw_partial_yuv_config1a */ - union { - struct { - uint32_t reg_draw_th_1a : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_1a : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_1a : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_1a : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config1a; - - /* 0x84 : draw_partial_x_config1a */ - union { - struct { - uint32_t reg_draw_x_min_1a : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_1a : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config1a; - - /* 0x88 : draw_partial_y_config1a */ - union { - struct { - uint32_t reg_draw_y_min_1a : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_1a : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config1a; - - /* 0x8C : draw_partial_yuv_config1b */ - union { - struct { - uint32_t reg_draw_th_1b : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_1b : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_1b : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_1b : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config1b; - - /* 0x90 : draw_partial_x_config1b */ - union { - struct { - uint32_t reg_draw_x_min_1b : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_1b : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config1b; - - /* 0x94 : draw_partial_y_config1b */ - union { - struct { - uint32_t reg_draw_y_min_1b : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_1b : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config1b; - - /* 0x98 : draw_partial_yuv_config1c */ - union { - struct { - uint32_t reg_draw_th_1c : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_1c : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_1c : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_1c : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config1c; - - /* 0x9C : draw_partial_x_config1c */ - union { - struct { - uint32_t reg_draw_x_min_1c : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_1c : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config1c; - - /* 0xA0 : draw_partial_y_config1c */ - union { - struct { - uint32_t reg_draw_y_min_1c : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_1c : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config1c; - - /* 0xA4 : draw_partial_yuv_config1d */ - union { - struct { - uint32_t reg_draw_th_1d : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_1d : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_1d : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_1d : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config1d; - - /* 0xA8 : draw_partial_x_config1d */ - union { - struct { - uint32_t reg_draw_x_min_1d : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_1d : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config1d; - - /* 0xAC : draw_partial_y_config1d */ - union { - struct { - uint32_t reg_draw_y_min_1d : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_1d : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config1d; - - /* 0xB0 : draw_partial_yuv_config1e */ - union { - struct { - uint32_t reg_draw_th_1e : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_1e : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_1e : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_1e : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config1e; - - /* 0xB4 : draw_partial_x_config1e */ - union { - struct { - uint32_t reg_draw_x_min_1e : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_1e : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config1e; - - /* 0xB8 : draw_partial_y_config1e */ - union { - struct { - uint32_t reg_draw_y_min_1e : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_1e : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config1e; - - /* 0xBC : draw_partial_yuv_config1f */ - union { - struct { - uint32_t reg_draw_th_1f : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_1f : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_1f : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_1f : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config1f; - - /* 0xC0 : draw_partial_x_config1f */ - union { - struct { - uint32_t reg_draw_x_min_1f : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_1f : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config1f; - - /* 0xC4 : draw_partial_y_config1f */ - union { - struct { - uint32_t reg_draw_y_min_1f : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_1f : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config1f; -}; - -typedef volatile struct osd_draw_h_reg osd_draw_h_reg_t; - -#endif /* __OSD_DRAW_H_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/osd_draw_l_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/osd_draw_l_reg.h deleted file mode 100644 index 8e8e1dd23f..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/osd_draw_l_reg.h +++ /dev/null @@ -1,1511 +0,0 @@ -/** - ****************************************************************************** - * @file osd_draw_l_reg.h - * @version V1.0 - * @date 2021-06-28 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __OSD_DRAW_L_REG_H__ -#define __OSD_DRAW_L_REG_H__ - -#include "bl808.h" - -/* 0x0 : osd_draw_config */ -#define OSD_DRAW_L_OSD_DRAW_CONFIG_OFFSET (0x0) -#define OSD_DRAW_L_REG_DRAW_EN_L OSD_DRAW_L_REG_DRAW_EN_L -#define OSD_DRAW_L_REG_DRAW_EN_L_POS (0U) -#define OSD_DRAW_L_REG_DRAW_EN_L_LEN (16U) -#define OSD_DRAW_L_REG_DRAW_EN_L_MSK (((1U << OSD_DRAW_L_REG_DRAW_EN_L_LEN) - 1) << OSD_DRAW_L_REG_DRAW_EN_L_POS) -#define OSD_DRAW_L_REG_DRAW_EN_L_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_EN_L_LEN) - 1) << OSD_DRAW_L_REG_DRAW_EN_L_POS)) -#define OSD_DRAW_L_REG_DRAW_TYPE_L OSD_DRAW_L_REG_DRAW_TYPE_L -#define OSD_DRAW_L_REG_DRAW_TYPE_L_POS (16U) -#define OSD_DRAW_L_REG_DRAW_TYPE_L_LEN (16U) -#define OSD_DRAW_L_REG_DRAW_TYPE_L_MSK (((1U << OSD_DRAW_L_REG_DRAW_TYPE_L_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TYPE_L_POS) -#define OSD_DRAW_L_REG_DRAW_TYPE_L_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_TYPE_L_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TYPE_L_POS)) - -/* 0x4 : draw_partial_yuv_config0 */ -#define OSD_DRAW_L_DRAW_PARTIAL_YUV_CONFIG0_OFFSET (0x4) -#define OSD_DRAW_L_REG_DRAW_TH_00 OSD_DRAW_L_REG_DRAW_TH_00 -#define OSD_DRAW_L_REG_DRAW_TH_00_POS (0U) -#define OSD_DRAW_L_REG_DRAW_TH_00_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_TH_00_MSK (((1U << OSD_DRAW_L_REG_DRAW_TH_00_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_00_POS) -#define OSD_DRAW_L_REG_DRAW_TH_00_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_TH_00_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_00_POS)) -#define OSD_DRAW_L_REG_DRAW_V_00 OSD_DRAW_L_REG_DRAW_V_00 -#define OSD_DRAW_L_REG_DRAW_V_00_POS (8U) -#define OSD_DRAW_L_REG_DRAW_V_00_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_V_00_MSK (((1U << OSD_DRAW_L_REG_DRAW_V_00_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_00_POS) -#define OSD_DRAW_L_REG_DRAW_V_00_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_V_00_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_00_POS)) -#define OSD_DRAW_L_REG_DRAW_U_00 OSD_DRAW_L_REG_DRAW_U_00 -#define OSD_DRAW_L_REG_DRAW_U_00_POS (16U) -#define OSD_DRAW_L_REG_DRAW_U_00_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_U_00_MSK (((1U << OSD_DRAW_L_REG_DRAW_U_00_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_00_POS) -#define OSD_DRAW_L_REG_DRAW_U_00_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_U_00_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_00_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_00 OSD_DRAW_L_REG_DRAW_Y_00 -#define OSD_DRAW_L_REG_DRAW_Y_00_POS (24U) -#define OSD_DRAW_L_REG_DRAW_Y_00_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_Y_00_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_00_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_00_POS) -#define OSD_DRAW_L_REG_DRAW_Y_00_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_00_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_00_POS)) - -/* 0x8 : draw_partial_x_config0 */ -#define OSD_DRAW_L_DRAW_PARTIAL_X_CONFIG0_OFFSET (0x8) -#define OSD_DRAW_L_REG_DRAW_X_MIN_00 OSD_DRAW_L_REG_DRAW_X_MIN_00 -#define OSD_DRAW_L_REG_DRAW_X_MIN_00_POS (0U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_00_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_00_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MIN_00_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_00_POS) -#define OSD_DRAW_L_REG_DRAW_X_MIN_00_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MIN_00_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_00_POS)) -#define OSD_DRAW_L_REG_DRAW_X_MAX_00 OSD_DRAW_L_REG_DRAW_X_MAX_00 -#define OSD_DRAW_L_REG_DRAW_X_MAX_00_POS (16U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_00_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_00_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MAX_00_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_00_POS) -#define OSD_DRAW_L_REG_DRAW_X_MAX_00_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MAX_00_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_00_POS)) - -/* 0xC : draw_partial_y_config0 */ -#define OSD_DRAW_L_DRAW_PARTIAL_Y_CONFIG0_OFFSET (0xC) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_00 OSD_DRAW_L_REG_DRAW_Y_MIN_00 -#define OSD_DRAW_L_REG_DRAW_Y_MIN_00_POS (0U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_00_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_00_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_00_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_00_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_00_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_00_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_00_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_00 OSD_DRAW_L_REG_DRAW_Y_MAX_00 -#define OSD_DRAW_L_REG_DRAW_Y_MAX_00_POS (16U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_00_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_00_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_00_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_00_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_00_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_00_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_00_POS)) - -/* 0x10 : draw_partial_yuv_config1 */ -#define OSD_DRAW_L_DRAW_PARTIAL_YUV_CONFIG1_OFFSET (0x10) -#define OSD_DRAW_L_REG_DRAW_TH_01 OSD_DRAW_L_REG_DRAW_TH_01 -#define OSD_DRAW_L_REG_DRAW_TH_01_POS (0U) -#define OSD_DRAW_L_REG_DRAW_TH_01_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_TH_01_MSK (((1U << OSD_DRAW_L_REG_DRAW_TH_01_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_01_POS) -#define OSD_DRAW_L_REG_DRAW_TH_01_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_TH_01_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_01_POS)) -#define OSD_DRAW_L_REG_DRAW_V_01 OSD_DRAW_L_REG_DRAW_V_01 -#define OSD_DRAW_L_REG_DRAW_V_01_POS (8U) -#define OSD_DRAW_L_REG_DRAW_V_01_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_V_01_MSK (((1U << OSD_DRAW_L_REG_DRAW_V_01_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_01_POS) -#define OSD_DRAW_L_REG_DRAW_V_01_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_V_01_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_01_POS)) -#define OSD_DRAW_L_REG_DRAW_U_01 OSD_DRAW_L_REG_DRAW_U_01 -#define OSD_DRAW_L_REG_DRAW_U_01_POS (16U) -#define OSD_DRAW_L_REG_DRAW_U_01_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_U_01_MSK (((1U << OSD_DRAW_L_REG_DRAW_U_01_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_01_POS) -#define OSD_DRAW_L_REG_DRAW_U_01_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_U_01_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_01_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_01 OSD_DRAW_L_REG_DRAW_Y_01 -#define OSD_DRAW_L_REG_DRAW_Y_01_POS (24U) -#define OSD_DRAW_L_REG_DRAW_Y_01_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_Y_01_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_01_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_01_POS) -#define OSD_DRAW_L_REG_DRAW_Y_01_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_01_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_01_POS)) - -/* 0x14 : draw_partial_x_config1 */ -#define OSD_DRAW_L_DRAW_PARTIAL_X_CONFIG1_OFFSET (0x14) -#define OSD_DRAW_L_REG_DRAW_X_MIN_01 OSD_DRAW_L_REG_DRAW_X_MIN_01 -#define OSD_DRAW_L_REG_DRAW_X_MIN_01_POS (0U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_01_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_01_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MIN_01_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_01_POS) -#define OSD_DRAW_L_REG_DRAW_X_MIN_01_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MIN_01_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_01_POS)) -#define OSD_DRAW_L_REG_DRAW_X_MAX_01 OSD_DRAW_L_REG_DRAW_X_MAX_01 -#define OSD_DRAW_L_REG_DRAW_X_MAX_01_POS (16U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_01_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_01_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MAX_01_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_01_POS) -#define OSD_DRAW_L_REG_DRAW_X_MAX_01_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MAX_01_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_01_POS)) - -/* 0x18 : draw_partial_y_config1 */ -#define OSD_DRAW_L_DRAW_PARTIAL_Y_CONFIG1_OFFSET (0x18) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_01 OSD_DRAW_L_REG_DRAW_Y_MIN_01 -#define OSD_DRAW_L_REG_DRAW_Y_MIN_01_POS (0U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_01_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_01_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_01_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_01_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_01_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_01_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_01_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_01 OSD_DRAW_L_REG_DRAW_Y_MAX_01 -#define OSD_DRAW_L_REG_DRAW_Y_MAX_01_POS (16U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_01_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_01_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_01_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_01_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_01_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_01_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_01_POS)) - -/* 0x1C : draw_partial_yuv_config2 */ -#define OSD_DRAW_L_DRAW_PARTIAL_YUV_CONFIG2_OFFSET (0x1C) -#define OSD_DRAW_L_REG_DRAW_TH_02 OSD_DRAW_L_REG_DRAW_TH_02 -#define OSD_DRAW_L_REG_DRAW_TH_02_POS (0U) -#define OSD_DRAW_L_REG_DRAW_TH_02_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_TH_02_MSK (((1U << OSD_DRAW_L_REG_DRAW_TH_02_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_02_POS) -#define OSD_DRAW_L_REG_DRAW_TH_02_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_TH_02_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_02_POS)) -#define OSD_DRAW_L_REG_DRAW_V_02 OSD_DRAW_L_REG_DRAW_V_02 -#define OSD_DRAW_L_REG_DRAW_V_02_POS (8U) -#define OSD_DRAW_L_REG_DRAW_V_02_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_V_02_MSK (((1U << OSD_DRAW_L_REG_DRAW_V_02_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_02_POS) -#define OSD_DRAW_L_REG_DRAW_V_02_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_V_02_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_02_POS)) -#define OSD_DRAW_L_REG_DRAW_U_02 OSD_DRAW_L_REG_DRAW_U_02 -#define OSD_DRAW_L_REG_DRAW_U_02_POS (16U) -#define OSD_DRAW_L_REG_DRAW_U_02_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_U_02_MSK (((1U << OSD_DRAW_L_REG_DRAW_U_02_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_02_POS) -#define OSD_DRAW_L_REG_DRAW_U_02_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_U_02_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_02_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_02 OSD_DRAW_L_REG_DRAW_Y_02 -#define OSD_DRAW_L_REG_DRAW_Y_02_POS (24U) -#define OSD_DRAW_L_REG_DRAW_Y_02_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_Y_02_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_02_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_02_POS) -#define OSD_DRAW_L_REG_DRAW_Y_02_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_02_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_02_POS)) - -/* 0x20 : draw_partial_x_config2 */ -#define OSD_DRAW_L_DRAW_PARTIAL_X_CONFIG2_OFFSET (0x20) -#define OSD_DRAW_L_REG_DRAW_X_MIN_02 OSD_DRAW_L_REG_DRAW_X_MIN_02 -#define OSD_DRAW_L_REG_DRAW_X_MIN_02_POS (0U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_02_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_02_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MIN_02_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_02_POS) -#define OSD_DRAW_L_REG_DRAW_X_MIN_02_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MIN_02_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_02_POS)) -#define OSD_DRAW_L_REG_DRAW_X_MAX_02 OSD_DRAW_L_REG_DRAW_X_MAX_02 -#define OSD_DRAW_L_REG_DRAW_X_MAX_02_POS (16U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_02_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_02_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MAX_02_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_02_POS) -#define OSD_DRAW_L_REG_DRAW_X_MAX_02_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MAX_02_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_02_POS)) - -/* 0x24 : draw_partial_y_config2 */ -#define OSD_DRAW_L_DRAW_PARTIAL_Y_CONFIG2_OFFSET (0x24) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_02 OSD_DRAW_L_REG_DRAW_Y_MIN_02 -#define OSD_DRAW_L_REG_DRAW_Y_MIN_02_POS (0U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_02_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_02_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_02_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_02_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_02_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_02_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_02_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_02 OSD_DRAW_L_REG_DRAW_Y_MAX_02 -#define OSD_DRAW_L_REG_DRAW_Y_MAX_02_POS (16U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_02_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_02_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_02_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_02_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_02_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_02_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_02_POS)) - -/* 0x28 : draw_partial_yuv_config3 */ -#define OSD_DRAW_L_DRAW_PARTIAL_YUV_CONFIG3_OFFSET (0x28) -#define OSD_DRAW_L_REG_DRAW_TH_03 OSD_DRAW_L_REG_DRAW_TH_03 -#define OSD_DRAW_L_REG_DRAW_TH_03_POS (0U) -#define OSD_DRAW_L_REG_DRAW_TH_03_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_TH_03_MSK (((1U << OSD_DRAW_L_REG_DRAW_TH_03_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_03_POS) -#define OSD_DRAW_L_REG_DRAW_TH_03_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_TH_03_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_03_POS)) -#define OSD_DRAW_L_REG_DRAW_V_03 OSD_DRAW_L_REG_DRAW_V_03 -#define OSD_DRAW_L_REG_DRAW_V_03_POS (8U) -#define OSD_DRAW_L_REG_DRAW_V_03_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_V_03_MSK (((1U << OSD_DRAW_L_REG_DRAW_V_03_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_03_POS) -#define OSD_DRAW_L_REG_DRAW_V_03_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_V_03_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_03_POS)) -#define OSD_DRAW_L_REG_DRAW_U_03 OSD_DRAW_L_REG_DRAW_U_03 -#define OSD_DRAW_L_REG_DRAW_U_03_POS (16U) -#define OSD_DRAW_L_REG_DRAW_U_03_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_U_03_MSK (((1U << OSD_DRAW_L_REG_DRAW_U_03_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_03_POS) -#define OSD_DRAW_L_REG_DRAW_U_03_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_U_03_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_03_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_03 OSD_DRAW_L_REG_DRAW_Y_03 -#define OSD_DRAW_L_REG_DRAW_Y_03_POS (24U) -#define OSD_DRAW_L_REG_DRAW_Y_03_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_Y_03_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_03_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_03_POS) -#define OSD_DRAW_L_REG_DRAW_Y_03_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_03_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_03_POS)) - -/* 0x2C : draw_partial_x_config3 */ -#define OSD_DRAW_L_DRAW_PARTIAL_X_CONFIG3_OFFSET (0x2C) -#define OSD_DRAW_L_REG_DRAW_X_MIN_03 OSD_DRAW_L_REG_DRAW_X_MIN_03 -#define OSD_DRAW_L_REG_DRAW_X_MIN_03_POS (0U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_03_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_03_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MIN_03_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_03_POS) -#define OSD_DRAW_L_REG_DRAW_X_MIN_03_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MIN_03_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_03_POS)) -#define OSD_DRAW_L_REG_DRAW_X_MAX_03 OSD_DRAW_L_REG_DRAW_X_MAX_03 -#define OSD_DRAW_L_REG_DRAW_X_MAX_03_POS (16U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_03_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_03_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MAX_03_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_03_POS) -#define OSD_DRAW_L_REG_DRAW_X_MAX_03_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MAX_03_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_03_POS)) - -/* 0x30 : draw_partial_y_config3 */ -#define OSD_DRAW_L_DRAW_PARTIAL_Y_CONFIG3_OFFSET (0x30) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_03 OSD_DRAW_L_REG_DRAW_Y_MIN_03 -#define OSD_DRAW_L_REG_DRAW_Y_MIN_03_POS (0U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_03_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_03_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_03_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_03_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_03_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_03_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_03_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_03 OSD_DRAW_L_REG_DRAW_Y_MAX_03 -#define OSD_DRAW_L_REG_DRAW_Y_MAX_03_POS (16U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_03_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_03_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_03_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_03_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_03_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_03_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_03_POS)) - -/* 0x34 : draw_partial_yuv_config4 */ -#define OSD_DRAW_L_DRAW_PARTIAL_YUV_CONFIG4_OFFSET (0x34) -#define OSD_DRAW_L_REG_DRAW_TH_04 OSD_DRAW_L_REG_DRAW_TH_04 -#define OSD_DRAW_L_REG_DRAW_TH_04_POS (0U) -#define OSD_DRAW_L_REG_DRAW_TH_04_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_TH_04_MSK (((1U << OSD_DRAW_L_REG_DRAW_TH_04_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_04_POS) -#define OSD_DRAW_L_REG_DRAW_TH_04_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_TH_04_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_04_POS)) -#define OSD_DRAW_L_REG_DRAW_V_04 OSD_DRAW_L_REG_DRAW_V_04 -#define OSD_DRAW_L_REG_DRAW_V_04_POS (8U) -#define OSD_DRAW_L_REG_DRAW_V_04_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_V_04_MSK (((1U << OSD_DRAW_L_REG_DRAW_V_04_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_04_POS) -#define OSD_DRAW_L_REG_DRAW_V_04_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_V_04_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_04_POS)) -#define OSD_DRAW_L_REG_DRAW_U_04 OSD_DRAW_L_REG_DRAW_U_04 -#define OSD_DRAW_L_REG_DRAW_U_04_POS (16U) -#define OSD_DRAW_L_REG_DRAW_U_04_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_U_04_MSK (((1U << OSD_DRAW_L_REG_DRAW_U_04_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_04_POS) -#define OSD_DRAW_L_REG_DRAW_U_04_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_U_04_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_04_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_04 OSD_DRAW_L_REG_DRAW_Y_04 -#define OSD_DRAW_L_REG_DRAW_Y_04_POS (24U) -#define OSD_DRAW_L_REG_DRAW_Y_04_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_Y_04_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_04_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_04_POS) -#define OSD_DRAW_L_REG_DRAW_Y_04_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_04_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_04_POS)) - -/* 0x38 : draw_partial_x_config4 */ -#define OSD_DRAW_L_DRAW_PARTIAL_X_CONFIG4_OFFSET (0x38) -#define OSD_DRAW_L_REG_DRAW_X_MIN_04 OSD_DRAW_L_REG_DRAW_X_MIN_04 -#define OSD_DRAW_L_REG_DRAW_X_MIN_04_POS (0U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_04_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_04_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MIN_04_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_04_POS) -#define OSD_DRAW_L_REG_DRAW_X_MIN_04_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MIN_04_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_04_POS)) -#define OSD_DRAW_L_REG_DRAW_X_MAX_04 OSD_DRAW_L_REG_DRAW_X_MAX_04 -#define OSD_DRAW_L_REG_DRAW_X_MAX_04_POS (16U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_04_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_04_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MAX_04_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_04_POS) -#define OSD_DRAW_L_REG_DRAW_X_MAX_04_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MAX_04_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_04_POS)) - -/* 0x3C : draw_partial_y_config4 */ -#define OSD_DRAW_L_DRAW_PARTIAL_Y_CONFIG4_OFFSET (0x3C) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_04 OSD_DRAW_L_REG_DRAW_Y_MIN_04 -#define OSD_DRAW_L_REG_DRAW_Y_MIN_04_POS (0U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_04_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_04_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_04_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_04_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_04_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_04_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_04_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_04 OSD_DRAW_L_REG_DRAW_Y_MAX_04 -#define OSD_DRAW_L_REG_DRAW_Y_MAX_04_POS (16U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_04_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_04_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_04_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_04_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_04_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_04_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_04_POS)) - -/* 0x40 : draw_partial_yuv_config5 */ -#define OSD_DRAW_L_DRAW_PARTIAL_YUV_CONFIG5_OFFSET (0x40) -#define OSD_DRAW_L_REG_DRAW_TH_05 OSD_DRAW_L_REG_DRAW_TH_05 -#define OSD_DRAW_L_REG_DRAW_TH_05_POS (0U) -#define OSD_DRAW_L_REG_DRAW_TH_05_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_TH_05_MSK (((1U << OSD_DRAW_L_REG_DRAW_TH_05_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_05_POS) -#define OSD_DRAW_L_REG_DRAW_TH_05_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_TH_05_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_05_POS)) -#define OSD_DRAW_L_REG_DRAW_V_05 OSD_DRAW_L_REG_DRAW_V_05 -#define OSD_DRAW_L_REG_DRAW_V_05_POS (8U) -#define OSD_DRAW_L_REG_DRAW_V_05_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_V_05_MSK (((1U << OSD_DRAW_L_REG_DRAW_V_05_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_05_POS) -#define OSD_DRAW_L_REG_DRAW_V_05_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_V_05_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_05_POS)) -#define OSD_DRAW_L_REG_DRAW_U_05 OSD_DRAW_L_REG_DRAW_U_05 -#define OSD_DRAW_L_REG_DRAW_U_05_POS (16U) -#define OSD_DRAW_L_REG_DRAW_U_05_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_U_05_MSK (((1U << OSD_DRAW_L_REG_DRAW_U_05_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_05_POS) -#define OSD_DRAW_L_REG_DRAW_U_05_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_U_05_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_05_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_05 OSD_DRAW_L_REG_DRAW_Y_05 -#define OSD_DRAW_L_REG_DRAW_Y_05_POS (24U) -#define OSD_DRAW_L_REG_DRAW_Y_05_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_Y_05_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_05_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_05_POS) -#define OSD_DRAW_L_REG_DRAW_Y_05_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_05_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_05_POS)) - -/* 0x44 : draw_partial_x_config5 */ -#define OSD_DRAW_L_DRAW_PARTIAL_X_CONFIG5_OFFSET (0x44) -#define OSD_DRAW_L_REG_DRAW_X_MIN_05 OSD_DRAW_L_REG_DRAW_X_MIN_05 -#define OSD_DRAW_L_REG_DRAW_X_MIN_05_POS (0U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_05_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_05_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MIN_05_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_05_POS) -#define OSD_DRAW_L_REG_DRAW_X_MIN_05_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MIN_05_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_05_POS)) -#define OSD_DRAW_L_REG_DRAW_X_MAX_05 OSD_DRAW_L_REG_DRAW_X_MAX_05 -#define OSD_DRAW_L_REG_DRAW_X_MAX_05_POS (16U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_05_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_05_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MAX_05_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_05_POS) -#define OSD_DRAW_L_REG_DRAW_X_MAX_05_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MAX_05_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_05_POS)) - -/* 0x48 : draw_partial_y_config5 */ -#define OSD_DRAW_L_DRAW_PARTIAL_Y_CONFIG5_OFFSET (0x48) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_05 OSD_DRAW_L_REG_DRAW_Y_MIN_05 -#define OSD_DRAW_L_REG_DRAW_Y_MIN_05_POS (0U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_05_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_05_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_05_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_05_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_05_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_05_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_05_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_05 OSD_DRAW_L_REG_DRAW_Y_MAX_05 -#define OSD_DRAW_L_REG_DRAW_Y_MAX_05_POS (16U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_05_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_05_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_05_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_05_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_05_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_05_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_05_POS)) - -/* 0x4C : draw_partial_yuv_config6 */ -#define OSD_DRAW_L_DRAW_PARTIAL_YUV_CONFIG6_OFFSET (0x4C) -#define OSD_DRAW_L_REG_DRAW_TH_06 OSD_DRAW_L_REG_DRAW_TH_06 -#define OSD_DRAW_L_REG_DRAW_TH_06_POS (0U) -#define OSD_DRAW_L_REG_DRAW_TH_06_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_TH_06_MSK (((1U << OSD_DRAW_L_REG_DRAW_TH_06_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_06_POS) -#define OSD_DRAW_L_REG_DRAW_TH_06_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_TH_06_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_06_POS)) -#define OSD_DRAW_L_REG_DRAW_V_06 OSD_DRAW_L_REG_DRAW_V_06 -#define OSD_DRAW_L_REG_DRAW_V_06_POS (8U) -#define OSD_DRAW_L_REG_DRAW_V_06_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_V_06_MSK (((1U << OSD_DRAW_L_REG_DRAW_V_06_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_06_POS) -#define OSD_DRAW_L_REG_DRAW_V_06_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_V_06_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_06_POS)) -#define OSD_DRAW_L_REG_DRAW_U_06 OSD_DRAW_L_REG_DRAW_U_06 -#define OSD_DRAW_L_REG_DRAW_U_06_POS (16U) -#define OSD_DRAW_L_REG_DRAW_U_06_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_U_06_MSK (((1U << OSD_DRAW_L_REG_DRAW_U_06_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_06_POS) -#define OSD_DRAW_L_REG_DRAW_U_06_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_U_06_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_06_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_06 OSD_DRAW_L_REG_DRAW_Y_06 -#define OSD_DRAW_L_REG_DRAW_Y_06_POS (24U) -#define OSD_DRAW_L_REG_DRAW_Y_06_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_Y_06_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_06_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_06_POS) -#define OSD_DRAW_L_REG_DRAW_Y_06_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_06_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_06_POS)) - -/* 0x50 : draw_partial_x_config6 */ -#define OSD_DRAW_L_DRAW_PARTIAL_X_CONFIG6_OFFSET (0x50) -#define OSD_DRAW_L_REG_DRAW_X_MIN_06 OSD_DRAW_L_REG_DRAW_X_MIN_06 -#define OSD_DRAW_L_REG_DRAW_X_MIN_06_POS (0U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_06_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_06_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MIN_06_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_06_POS) -#define OSD_DRAW_L_REG_DRAW_X_MIN_06_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MIN_06_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_06_POS)) -#define OSD_DRAW_L_REG_DRAW_X_MAX_06 OSD_DRAW_L_REG_DRAW_X_MAX_06 -#define OSD_DRAW_L_REG_DRAW_X_MAX_06_POS (16U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_06_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_06_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MAX_06_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_06_POS) -#define OSD_DRAW_L_REG_DRAW_X_MAX_06_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MAX_06_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_06_POS)) - -/* 0x54 : draw_partial_y_config6 */ -#define OSD_DRAW_L_DRAW_PARTIAL_Y_CONFIG6_OFFSET (0x54) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_06 OSD_DRAW_L_REG_DRAW_Y_MIN_06 -#define OSD_DRAW_L_REG_DRAW_Y_MIN_06_POS (0U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_06_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_06_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_06_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_06_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_06_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_06_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_06_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_06 OSD_DRAW_L_REG_DRAW_Y_MAX_06 -#define OSD_DRAW_L_REG_DRAW_Y_MAX_06_POS (16U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_06_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_06_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_06_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_06_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_06_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_06_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_06_POS)) - -/* 0x58 : draw_partial_yuv_config7 */ -#define OSD_DRAW_L_DRAW_PARTIAL_YUV_CONFIG7_OFFSET (0x58) -#define OSD_DRAW_L_REG_DRAW_TH_07 OSD_DRAW_L_REG_DRAW_TH_07 -#define OSD_DRAW_L_REG_DRAW_TH_07_POS (0U) -#define OSD_DRAW_L_REG_DRAW_TH_07_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_TH_07_MSK (((1U << OSD_DRAW_L_REG_DRAW_TH_07_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_07_POS) -#define OSD_DRAW_L_REG_DRAW_TH_07_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_TH_07_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_07_POS)) -#define OSD_DRAW_L_REG_DRAW_V_07 OSD_DRAW_L_REG_DRAW_V_07 -#define OSD_DRAW_L_REG_DRAW_V_07_POS (8U) -#define OSD_DRAW_L_REG_DRAW_V_07_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_V_07_MSK (((1U << OSD_DRAW_L_REG_DRAW_V_07_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_07_POS) -#define OSD_DRAW_L_REG_DRAW_V_07_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_V_07_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_07_POS)) -#define OSD_DRAW_L_REG_DRAW_U_07 OSD_DRAW_L_REG_DRAW_U_07 -#define OSD_DRAW_L_REG_DRAW_U_07_POS (16U) -#define OSD_DRAW_L_REG_DRAW_U_07_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_U_07_MSK (((1U << OSD_DRAW_L_REG_DRAW_U_07_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_07_POS) -#define OSD_DRAW_L_REG_DRAW_U_07_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_U_07_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_07_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_07 OSD_DRAW_L_REG_DRAW_Y_07 -#define OSD_DRAW_L_REG_DRAW_Y_07_POS (24U) -#define OSD_DRAW_L_REG_DRAW_Y_07_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_Y_07_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_07_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_07_POS) -#define OSD_DRAW_L_REG_DRAW_Y_07_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_07_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_07_POS)) - -/* 0x5C : draw_partial_x_config7 */ -#define OSD_DRAW_L_DRAW_PARTIAL_X_CONFIG7_OFFSET (0x5C) -#define OSD_DRAW_L_REG_DRAW_X_MIN_07 OSD_DRAW_L_REG_DRAW_X_MIN_07 -#define OSD_DRAW_L_REG_DRAW_X_MIN_07_POS (0U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_07_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_07_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MIN_07_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_07_POS) -#define OSD_DRAW_L_REG_DRAW_X_MIN_07_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MIN_07_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_07_POS)) -#define OSD_DRAW_L_REG_DRAW_X_MAX_07 OSD_DRAW_L_REG_DRAW_X_MAX_07 -#define OSD_DRAW_L_REG_DRAW_X_MAX_07_POS (16U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_07_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_07_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MAX_07_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_07_POS) -#define OSD_DRAW_L_REG_DRAW_X_MAX_07_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MAX_07_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_07_POS)) - -/* 0x60 : draw_partial_y_config7 */ -#define OSD_DRAW_L_DRAW_PARTIAL_Y_CONFIG7_OFFSET (0x60) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_07 OSD_DRAW_L_REG_DRAW_Y_MIN_07 -#define OSD_DRAW_L_REG_DRAW_Y_MIN_07_POS (0U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_07_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_07_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_07_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_07_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_07_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_07_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_07_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_07 OSD_DRAW_L_REG_DRAW_Y_MAX_07 -#define OSD_DRAW_L_REG_DRAW_Y_MAX_07_POS (16U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_07_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_07_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_07_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_07_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_07_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_07_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_07_POS)) - -/* 0x64 : draw_partial_yuv_config8 */ -#define OSD_DRAW_L_DRAW_PARTIAL_YUV_CONFIG8_OFFSET (0x64) -#define OSD_DRAW_L_REG_DRAW_TH_08 OSD_DRAW_L_REG_DRAW_TH_08 -#define OSD_DRAW_L_REG_DRAW_TH_08_POS (0U) -#define OSD_DRAW_L_REG_DRAW_TH_08_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_TH_08_MSK (((1U << OSD_DRAW_L_REG_DRAW_TH_08_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_08_POS) -#define OSD_DRAW_L_REG_DRAW_TH_08_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_TH_08_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_08_POS)) -#define OSD_DRAW_L_REG_DRAW_V_08 OSD_DRAW_L_REG_DRAW_V_08 -#define OSD_DRAW_L_REG_DRAW_V_08_POS (8U) -#define OSD_DRAW_L_REG_DRAW_V_08_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_V_08_MSK (((1U << OSD_DRAW_L_REG_DRAW_V_08_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_08_POS) -#define OSD_DRAW_L_REG_DRAW_V_08_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_V_08_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_08_POS)) -#define OSD_DRAW_L_REG_DRAW_U_08 OSD_DRAW_L_REG_DRAW_U_08 -#define OSD_DRAW_L_REG_DRAW_U_08_POS (16U) -#define OSD_DRAW_L_REG_DRAW_U_08_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_U_08_MSK (((1U << OSD_DRAW_L_REG_DRAW_U_08_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_08_POS) -#define OSD_DRAW_L_REG_DRAW_U_08_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_U_08_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_08_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_08 OSD_DRAW_L_REG_DRAW_Y_08 -#define OSD_DRAW_L_REG_DRAW_Y_08_POS (24U) -#define OSD_DRAW_L_REG_DRAW_Y_08_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_Y_08_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_08_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_08_POS) -#define OSD_DRAW_L_REG_DRAW_Y_08_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_08_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_08_POS)) - -/* 0x68 : draw_partial_x_config8 */ -#define OSD_DRAW_L_DRAW_PARTIAL_X_CONFIG8_OFFSET (0x68) -#define OSD_DRAW_L_REG_DRAW_X_MIN_08 OSD_DRAW_L_REG_DRAW_X_MIN_08 -#define OSD_DRAW_L_REG_DRAW_X_MIN_08_POS (0U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_08_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_08_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MIN_08_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_08_POS) -#define OSD_DRAW_L_REG_DRAW_X_MIN_08_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MIN_08_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_08_POS)) -#define OSD_DRAW_L_REG_DRAW_X_MAX_08 OSD_DRAW_L_REG_DRAW_X_MAX_08 -#define OSD_DRAW_L_REG_DRAW_X_MAX_08_POS (16U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_08_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_08_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MAX_08_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_08_POS) -#define OSD_DRAW_L_REG_DRAW_X_MAX_08_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MAX_08_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_08_POS)) - -/* 0x6C : draw_partial_y_config8 */ -#define OSD_DRAW_L_DRAW_PARTIAL_Y_CONFIG8_OFFSET (0x6C) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_08 OSD_DRAW_L_REG_DRAW_Y_MIN_08 -#define OSD_DRAW_L_REG_DRAW_Y_MIN_08_POS (0U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_08_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_08_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_08_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_08_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_08_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_08_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_08_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_08 OSD_DRAW_L_REG_DRAW_Y_MAX_08 -#define OSD_DRAW_L_REG_DRAW_Y_MAX_08_POS (16U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_08_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_08_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_08_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_08_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_08_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_08_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_08_POS)) - -/* 0x70 : draw_partial_yuv_config9 */ -#define OSD_DRAW_L_DRAW_PARTIAL_YUV_CONFIG9_OFFSET (0x70) -#define OSD_DRAW_L_REG_DRAW_TH_09 OSD_DRAW_L_REG_DRAW_TH_09 -#define OSD_DRAW_L_REG_DRAW_TH_09_POS (0U) -#define OSD_DRAW_L_REG_DRAW_TH_09_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_TH_09_MSK (((1U << OSD_DRAW_L_REG_DRAW_TH_09_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_09_POS) -#define OSD_DRAW_L_REG_DRAW_TH_09_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_TH_09_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_09_POS)) -#define OSD_DRAW_L_REG_DRAW_V_09 OSD_DRAW_L_REG_DRAW_V_09 -#define OSD_DRAW_L_REG_DRAW_V_09_POS (8U) -#define OSD_DRAW_L_REG_DRAW_V_09_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_V_09_MSK (((1U << OSD_DRAW_L_REG_DRAW_V_09_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_09_POS) -#define OSD_DRAW_L_REG_DRAW_V_09_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_V_09_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_09_POS)) -#define OSD_DRAW_L_REG_DRAW_U_09 OSD_DRAW_L_REG_DRAW_U_09 -#define OSD_DRAW_L_REG_DRAW_U_09_POS (16U) -#define OSD_DRAW_L_REG_DRAW_U_09_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_U_09_MSK (((1U << OSD_DRAW_L_REG_DRAW_U_09_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_09_POS) -#define OSD_DRAW_L_REG_DRAW_U_09_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_U_09_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_09_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_09 OSD_DRAW_L_REG_DRAW_Y_09 -#define OSD_DRAW_L_REG_DRAW_Y_09_POS (24U) -#define OSD_DRAW_L_REG_DRAW_Y_09_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_Y_09_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_09_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_09_POS) -#define OSD_DRAW_L_REG_DRAW_Y_09_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_09_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_09_POS)) - -/* 0x74 : draw_partial_x_config9 */ -#define OSD_DRAW_L_DRAW_PARTIAL_X_CONFIG9_OFFSET (0x74) -#define OSD_DRAW_L_REG_DRAW_X_MIN_09 OSD_DRAW_L_REG_DRAW_X_MIN_09 -#define OSD_DRAW_L_REG_DRAW_X_MIN_09_POS (0U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_09_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_09_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MIN_09_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_09_POS) -#define OSD_DRAW_L_REG_DRAW_X_MIN_09_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MIN_09_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_09_POS)) -#define OSD_DRAW_L_REG_DRAW_X_MAX_09 OSD_DRAW_L_REG_DRAW_X_MAX_09 -#define OSD_DRAW_L_REG_DRAW_X_MAX_09_POS (16U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_09_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_09_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MAX_09_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_09_POS) -#define OSD_DRAW_L_REG_DRAW_X_MAX_09_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MAX_09_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_09_POS)) - -/* 0x78 : draw_partial_y_config9 */ -#define OSD_DRAW_L_DRAW_PARTIAL_Y_CONFIG9_OFFSET (0x78) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_09 OSD_DRAW_L_REG_DRAW_Y_MIN_09 -#define OSD_DRAW_L_REG_DRAW_Y_MIN_09_POS (0U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_09_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_09_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_09_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_09_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_09_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_09_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_09_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_09 OSD_DRAW_L_REG_DRAW_Y_MAX_09 -#define OSD_DRAW_L_REG_DRAW_Y_MAX_09_POS (16U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_09_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_09_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_09_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_09_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_09_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_09_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_09_POS)) - -/* 0x7C : draw_partial_yuv_configa */ -#define OSD_DRAW_L_DRAW_PARTIAL_YUV_CONFIGA_OFFSET (0x7C) -#define OSD_DRAW_L_REG_DRAW_TH_0A OSD_DRAW_L_REG_DRAW_TH_0A -#define OSD_DRAW_L_REG_DRAW_TH_0A_POS (0U) -#define OSD_DRAW_L_REG_DRAW_TH_0A_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_TH_0A_MSK (((1U << OSD_DRAW_L_REG_DRAW_TH_0A_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_0A_POS) -#define OSD_DRAW_L_REG_DRAW_TH_0A_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_TH_0A_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_0A_POS)) -#define OSD_DRAW_L_REG_DRAW_V_0A OSD_DRAW_L_REG_DRAW_V_0A -#define OSD_DRAW_L_REG_DRAW_V_0A_POS (8U) -#define OSD_DRAW_L_REG_DRAW_V_0A_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_V_0A_MSK (((1U << OSD_DRAW_L_REG_DRAW_V_0A_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_0A_POS) -#define OSD_DRAW_L_REG_DRAW_V_0A_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_V_0A_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_0A_POS)) -#define OSD_DRAW_L_REG_DRAW_U_0A OSD_DRAW_L_REG_DRAW_U_0A -#define OSD_DRAW_L_REG_DRAW_U_0A_POS (16U) -#define OSD_DRAW_L_REG_DRAW_U_0A_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_U_0A_MSK (((1U << OSD_DRAW_L_REG_DRAW_U_0A_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_0A_POS) -#define OSD_DRAW_L_REG_DRAW_U_0A_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_U_0A_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_0A_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_0A OSD_DRAW_L_REG_DRAW_Y_0A -#define OSD_DRAW_L_REG_DRAW_Y_0A_POS (24U) -#define OSD_DRAW_L_REG_DRAW_Y_0A_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_Y_0A_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_0A_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_0A_POS) -#define OSD_DRAW_L_REG_DRAW_Y_0A_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_0A_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_0A_POS)) - -/* 0x80 : draw_partial_x_configa */ -#define OSD_DRAW_L_DRAW_PARTIAL_X_CONFIGA_OFFSET (0x80) -#define OSD_DRAW_L_REG_DRAW_X_MIN_0A OSD_DRAW_L_REG_DRAW_X_MIN_0A -#define OSD_DRAW_L_REG_DRAW_X_MIN_0A_POS (0U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_0A_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_0A_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MIN_0A_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_0A_POS) -#define OSD_DRAW_L_REG_DRAW_X_MIN_0A_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MIN_0A_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_0A_POS)) -#define OSD_DRAW_L_REG_DRAW_X_MAX_0A OSD_DRAW_L_REG_DRAW_X_MAX_0A -#define OSD_DRAW_L_REG_DRAW_X_MAX_0A_POS (16U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_0A_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_0A_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MAX_0A_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_0A_POS) -#define OSD_DRAW_L_REG_DRAW_X_MAX_0A_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MAX_0A_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_0A_POS)) - -/* 0x84 : draw_partial_y_configa */ -#define OSD_DRAW_L_DRAW_PARTIAL_Y_CONFIGA_OFFSET (0x84) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0A OSD_DRAW_L_REG_DRAW_Y_MIN_0A -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0A_POS (0U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0A_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0A_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_0A_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_0A_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0A_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_0A_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_0A_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0A OSD_DRAW_L_REG_DRAW_Y_MAX_0A -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0A_POS (16U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0A_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0A_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_0A_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_0A_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0A_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_0A_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_0A_POS)) - -/* 0x88 : draw_partial_yuv_configb */ -#define OSD_DRAW_L_DRAW_PARTIAL_YUV_CONFIGB_OFFSET (0x88) -#define OSD_DRAW_L_REG_DRAW_TH_0B OSD_DRAW_L_REG_DRAW_TH_0B -#define OSD_DRAW_L_REG_DRAW_TH_0B_POS (0U) -#define OSD_DRAW_L_REG_DRAW_TH_0B_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_TH_0B_MSK (((1U << OSD_DRAW_L_REG_DRAW_TH_0B_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_0B_POS) -#define OSD_DRAW_L_REG_DRAW_TH_0B_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_TH_0B_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_0B_POS)) -#define OSD_DRAW_L_REG_DRAW_V_0B OSD_DRAW_L_REG_DRAW_V_0B -#define OSD_DRAW_L_REG_DRAW_V_0B_POS (8U) -#define OSD_DRAW_L_REG_DRAW_V_0B_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_V_0B_MSK (((1U << OSD_DRAW_L_REG_DRAW_V_0B_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_0B_POS) -#define OSD_DRAW_L_REG_DRAW_V_0B_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_V_0B_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_0B_POS)) -#define OSD_DRAW_L_REG_DRAW_U_0B OSD_DRAW_L_REG_DRAW_U_0B -#define OSD_DRAW_L_REG_DRAW_U_0B_POS (16U) -#define OSD_DRAW_L_REG_DRAW_U_0B_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_U_0B_MSK (((1U << OSD_DRAW_L_REG_DRAW_U_0B_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_0B_POS) -#define OSD_DRAW_L_REG_DRAW_U_0B_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_U_0B_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_0B_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_0B OSD_DRAW_L_REG_DRAW_Y_0B -#define OSD_DRAW_L_REG_DRAW_Y_0B_POS (24U) -#define OSD_DRAW_L_REG_DRAW_Y_0B_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_Y_0B_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_0B_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_0B_POS) -#define OSD_DRAW_L_REG_DRAW_Y_0B_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_0B_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_0B_POS)) - -/* 0x8C : draw_partial_x_configb */ -#define OSD_DRAW_L_DRAW_PARTIAL_X_CONFIGB_OFFSET (0x8C) -#define OSD_DRAW_L_REG_DRAW_X_MIN_0B OSD_DRAW_L_REG_DRAW_X_MIN_0B -#define OSD_DRAW_L_REG_DRAW_X_MIN_0B_POS (0U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_0B_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_0B_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MIN_0B_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_0B_POS) -#define OSD_DRAW_L_REG_DRAW_X_MIN_0B_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MIN_0B_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_0B_POS)) -#define OSD_DRAW_L_REG_DRAW_X_MAX_0B OSD_DRAW_L_REG_DRAW_X_MAX_0B -#define OSD_DRAW_L_REG_DRAW_X_MAX_0B_POS (16U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_0B_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_0B_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MAX_0B_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_0B_POS) -#define OSD_DRAW_L_REG_DRAW_X_MAX_0B_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MAX_0B_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_0B_POS)) - -/* 0x90 : draw_partial_y_configb */ -#define OSD_DRAW_L_DRAW_PARTIAL_Y_CONFIGB_OFFSET (0x90) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0B OSD_DRAW_L_REG_DRAW_Y_MIN_0B -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0B_POS (0U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0B_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0B_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_0B_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_0B_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0B_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_0B_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_0B_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0B OSD_DRAW_L_REG_DRAW_Y_MAX_0B -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0B_POS (16U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0B_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0B_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_0B_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_0B_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0B_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_0B_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_0B_POS)) - -/* 0x94 : draw_partial_yuv_configc */ -#define OSD_DRAW_L_DRAW_PARTIAL_YUV_CONFIGC_OFFSET (0x94) -#define OSD_DRAW_L_REG_DRAW_TH_0C OSD_DRAW_L_REG_DRAW_TH_0C -#define OSD_DRAW_L_REG_DRAW_TH_0C_POS (0U) -#define OSD_DRAW_L_REG_DRAW_TH_0C_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_TH_0C_MSK (((1U << OSD_DRAW_L_REG_DRAW_TH_0C_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_0C_POS) -#define OSD_DRAW_L_REG_DRAW_TH_0C_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_TH_0C_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_0C_POS)) -#define OSD_DRAW_L_REG_DRAW_V_0C OSD_DRAW_L_REG_DRAW_V_0C -#define OSD_DRAW_L_REG_DRAW_V_0C_POS (8U) -#define OSD_DRAW_L_REG_DRAW_V_0C_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_V_0C_MSK (((1U << OSD_DRAW_L_REG_DRAW_V_0C_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_0C_POS) -#define OSD_DRAW_L_REG_DRAW_V_0C_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_V_0C_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_0C_POS)) -#define OSD_DRAW_L_REG_DRAW_U_0C OSD_DRAW_L_REG_DRAW_U_0C -#define OSD_DRAW_L_REG_DRAW_U_0C_POS (16U) -#define OSD_DRAW_L_REG_DRAW_U_0C_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_U_0C_MSK (((1U << OSD_DRAW_L_REG_DRAW_U_0C_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_0C_POS) -#define OSD_DRAW_L_REG_DRAW_U_0C_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_U_0C_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_0C_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_0C OSD_DRAW_L_REG_DRAW_Y_0C -#define OSD_DRAW_L_REG_DRAW_Y_0C_POS (24U) -#define OSD_DRAW_L_REG_DRAW_Y_0C_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_Y_0C_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_0C_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_0C_POS) -#define OSD_DRAW_L_REG_DRAW_Y_0C_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_0C_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_0C_POS)) - -/* 0x98 : draw_partial_x_configc */ -#define OSD_DRAW_L_DRAW_PARTIAL_X_CONFIGC_OFFSET (0x98) -#define OSD_DRAW_L_REG_DRAW_X_MIN_0C OSD_DRAW_L_REG_DRAW_X_MIN_0C -#define OSD_DRAW_L_REG_DRAW_X_MIN_0C_POS (0U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_0C_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_0C_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MIN_0C_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_0C_POS) -#define OSD_DRAW_L_REG_DRAW_X_MIN_0C_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MIN_0C_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_0C_POS)) -#define OSD_DRAW_L_REG_DRAW_X_MAX_0C OSD_DRAW_L_REG_DRAW_X_MAX_0C -#define OSD_DRAW_L_REG_DRAW_X_MAX_0C_POS (16U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_0C_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_0C_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MAX_0C_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_0C_POS) -#define OSD_DRAW_L_REG_DRAW_X_MAX_0C_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MAX_0C_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_0C_POS)) - -/* 0x9C : draw_partial_y_configc */ -#define OSD_DRAW_L_DRAW_PARTIAL_Y_CONFIGC_OFFSET (0x9C) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0C OSD_DRAW_L_REG_DRAW_Y_MIN_0C -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0C_POS (0U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0C_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0C_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_0C_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_0C_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0C_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_0C_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_0C_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0C OSD_DRAW_L_REG_DRAW_Y_MAX_0C -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0C_POS (16U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0C_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0C_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_0C_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_0C_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0C_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_0C_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_0C_POS)) - -/* 0xA0 : draw_partial_yuv_configd */ -#define OSD_DRAW_L_DRAW_PARTIAL_YUV_CONFIGD_OFFSET (0xA0) -#define OSD_DRAW_L_REG_DRAW_TH_0D OSD_DRAW_L_REG_DRAW_TH_0D -#define OSD_DRAW_L_REG_DRAW_TH_0D_POS (0U) -#define OSD_DRAW_L_REG_DRAW_TH_0D_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_TH_0D_MSK (((1U << OSD_DRAW_L_REG_DRAW_TH_0D_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_0D_POS) -#define OSD_DRAW_L_REG_DRAW_TH_0D_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_TH_0D_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_0D_POS)) -#define OSD_DRAW_L_REG_DRAW_V_0D OSD_DRAW_L_REG_DRAW_V_0D -#define OSD_DRAW_L_REG_DRAW_V_0D_POS (8U) -#define OSD_DRAW_L_REG_DRAW_V_0D_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_V_0D_MSK (((1U << OSD_DRAW_L_REG_DRAW_V_0D_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_0D_POS) -#define OSD_DRAW_L_REG_DRAW_V_0D_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_V_0D_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_0D_POS)) -#define OSD_DRAW_L_REG_DRAW_U_0D OSD_DRAW_L_REG_DRAW_U_0D -#define OSD_DRAW_L_REG_DRAW_U_0D_POS (16U) -#define OSD_DRAW_L_REG_DRAW_U_0D_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_U_0D_MSK (((1U << OSD_DRAW_L_REG_DRAW_U_0D_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_0D_POS) -#define OSD_DRAW_L_REG_DRAW_U_0D_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_U_0D_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_0D_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_0D OSD_DRAW_L_REG_DRAW_Y_0D -#define OSD_DRAW_L_REG_DRAW_Y_0D_POS (24U) -#define OSD_DRAW_L_REG_DRAW_Y_0D_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_Y_0D_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_0D_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_0D_POS) -#define OSD_DRAW_L_REG_DRAW_Y_0D_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_0D_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_0D_POS)) - -/* 0xA4 : draw_partial_x_configd */ -#define OSD_DRAW_L_DRAW_PARTIAL_X_CONFIGD_OFFSET (0xA4) -#define OSD_DRAW_L_REG_DRAW_X_MIN_0D OSD_DRAW_L_REG_DRAW_X_MIN_0D -#define OSD_DRAW_L_REG_DRAW_X_MIN_0D_POS (0U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_0D_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_0D_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MIN_0D_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_0D_POS) -#define OSD_DRAW_L_REG_DRAW_X_MIN_0D_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MIN_0D_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_0D_POS)) -#define OSD_DRAW_L_REG_DRAW_X_MAX_0D OSD_DRAW_L_REG_DRAW_X_MAX_0D -#define OSD_DRAW_L_REG_DRAW_X_MAX_0D_POS (16U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_0D_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_0D_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MAX_0D_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_0D_POS) -#define OSD_DRAW_L_REG_DRAW_X_MAX_0D_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MAX_0D_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_0D_POS)) - -/* 0xA8 : draw_partial_y_configd */ -#define OSD_DRAW_L_DRAW_PARTIAL_Y_CONFIGD_OFFSET (0xA8) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0D OSD_DRAW_L_REG_DRAW_Y_MIN_0D -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0D_POS (0U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0D_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0D_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_0D_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_0D_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0D_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_0D_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_0D_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0D OSD_DRAW_L_REG_DRAW_Y_MAX_0D -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0D_POS (16U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0D_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0D_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_0D_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_0D_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0D_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_0D_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_0D_POS)) - -/* 0xAC : draw_partial_yuv_confige */ -#define OSD_DRAW_L_DRAW_PARTIAL_YUV_CONFIGE_OFFSET (0xAC) -#define OSD_DRAW_L_REG_DRAW_TH_0E OSD_DRAW_L_REG_DRAW_TH_0E -#define OSD_DRAW_L_REG_DRAW_TH_0E_POS (0U) -#define OSD_DRAW_L_REG_DRAW_TH_0E_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_TH_0E_MSK (((1U << OSD_DRAW_L_REG_DRAW_TH_0E_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_0E_POS) -#define OSD_DRAW_L_REG_DRAW_TH_0E_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_TH_0E_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_0E_POS)) -#define OSD_DRAW_L_REG_DRAW_V_0E OSD_DRAW_L_REG_DRAW_V_0E -#define OSD_DRAW_L_REG_DRAW_V_0E_POS (8U) -#define OSD_DRAW_L_REG_DRAW_V_0E_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_V_0E_MSK (((1U << OSD_DRAW_L_REG_DRAW_V_0E_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_0E_POS) -#define OSD_DRAW_L_REG_DRAW_V_0E_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_V_0E_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_0E_POS)) -#define OSD_DRAW_L_REG_DRAW_U_0E OSD_DRAW_L_REG_DRAW_U_0E -#define OSD_DRAW_L_REG_DRAW_U_0E_POS (16U) -#define OSD_DRAW_L_REG_DRAW_U_0E_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_U_0E_MSK (((1U << OSD_DRAW_L_REG_DRAW_U_0E_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_0E_POS) -#define OSD_DRAW_L_REG_DRAW_U_0E_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_U_0E_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_0E_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_0E OSD_DRAW_L_REG_DRAW_Y_0E -#define OSD_DRAW_L_REG_DRAW_Y_0E_POS (24U) -#define OSD_DRAW_L_REG_DRAW_Y_0E_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_Y_0E_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_0E_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_0E_POS) -#define OSD_DRAW_L_REG_DRAW_Y_0E_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_0E_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_0E_POS)) - -/* 0xB0 : draw_partial_x_confige */ -#define OSD_DRAW_L_DRAW_PARTIAL_X_CONFIGE_OFFSET (0xB0) -#define OSD_DRAW_L_REG_DRAW_X_MIN_0E OSD_DRAW_L_REG_DRAW_X_MIN_0E -#define OSD_DRAW_L_REG_DRAW_X_MIN_0E_POS (0U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_0E_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_0E_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MIN_0E_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_0E_POS) -#define OSD_DRAW_L_REG_DRAW_X_MIN_0E_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MIN_0E_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_0E_POS)) -#define OSD_DRAW_L_REG_DRAW_X_MAX_0E OSD_DRAW_L_REG_DRAW_X_MAX_0E -#define OSD_DRAW_L_REG_DRAW_X_MAX_0E_POS (16U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_0E_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_0E_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MAX_0E_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_0E_POS) -#define OSD_DRAW_L_REG_DRAW_X_MAX_0E_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MAX_0E_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_0E_POS)) - -/* 0xB4 : draw_partial_y_confige */ -#define OSD_DRAW_L_DRAW_PARTIAL_Y_CONFIGE_OFFSET (0xB4) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0E OSD_DRAW_L_REG_DRAW_Y_MIN_0E -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0E_POS (0U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0E_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0E_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_0E_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_0E_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0E_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_0E_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_0E_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0E OSD_DRAW_L_REG_DRAW_Y_MAX_0E -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0E_POS (16U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0E_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0E_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_0E_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_0E_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0E_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_0E_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_0E_POS)) - -/* 0xB8 : draw_partial_yuv_configf */ -#define OSD_DRAW_L_DRAW_PARTIAL_YUV_CONFIGF_OFFSET (0xB8) -#define OSD_DRAW_L_REG_DRAW_TH_0F OSD_DRAW_L_REG_DRAW_TH_0F -#define OSD_DRAW_L_REG_DRAW_TH_0F_POS (0U) -#define OSD_DRAW_L_REG_DRAW_TH_0F_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_TH_0F_MSK (((1U << OSD_DRAW_L_REG_DRAW_TH_0F_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_0F_POS) -#define OSD_DRAW_L_REG_DRAW_TH_0F_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_TH_0F_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_0F_POS)) -#define OSD_DRAW_L_REG_DRAW_V_0F OSD_DRAW_L_REG_DRAW_V_0F -#define OSD_DRAW_L_REG_DRAW_V_0F_POS (8U) -#define OSD_DRAW_L_REG_DRAW_V_0F_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_V_0F_MSK (((1U << OSD_DRAW_L_REG_DRAW_V_0F_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_0F_POS) -#define OSD_DRAW_L_REG_DRAW_V_0F_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_V_0F_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_0F_POS)) -#define OSD_DRAW_L_REG_DRAW_U_0F OSD_DRAW_L_REG_DRAW_U_0F -#define OSD_DRAW_L_REG_DRAW_U_0F_POS (16U) -#define OSD_DRAW_L_REG_DRAW_U_0F_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_U_0F_MSK (((1U << OSD_DRAW_L_REG_DRAW_U_0F_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_0F_POS) -#define OSD_DRAW_L_REG_DRAW_U_0F_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_U_0F_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_0F_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_0F OSD_DRAW_L_REG_DRAW_Y_0F -#define OSD_DRAW_L_REG_DRAW_Y_0F_POS (24U) -#define OSD_DRAW_L_REG_DRAW_Y_0F_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_Y_0F_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_0F_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_0F_POS) -#define OSD_DRAW_L_REG_DRAW_Y_0F_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_0F_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_0F_POS)) - -/* 0xBC : draw_partial_x_configf */ -#define OSD_DRAW_L_DRAW_PARTIAL_X_CONFIGF_OFFSET (0xBC) -#define OSD_DRAW_L_REG_DRAW_X_MIN_0F OSD_DRAW_L_REG_DRAW_X_MIN_0F -#define OSD_DRAW_L_REG_DRAW_X_MIN_0F_POS (0U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_0F_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_0F_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MIN_0F_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_0F_POS) -#define OSD_DRAW_L_REG_DRAW_X_MIN_0F_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MIN_0F_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_0F_POS)) -#define OSD_DRAW_L_REG_DRAW_X_MAX_0F OSD_DRAW_L_REG_DRAW_X_MAX_0F -#define OSD_DRAW_L_REG_DRAW_X_MAX_0F_POS (16U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_0F_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_0F_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MAX_0F_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_0F_POS) -#define OSD_DRAW_L_REG_DRAW_X_MAX_0F_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MAX_0F_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_0F_POS)) - -/* 0xC0 : draw_partial_y_configf */ -#define OSD_DRAW_L_DRAW_PARTIAL_Y_CONFIGF_OFFSET (0xC0) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0F OSD_DRAW_L_REG_DRAW_Y_MIN_0F -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0F_POS (0U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0F_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0F_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_0F_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_0F_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0F_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_0F_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_0F_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0F OSD_DRAW_L_REG_DRAW_Y_MAX_0F -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0F_POS (16U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0F_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0F_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_0F_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_0F_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0F_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_0F_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_0F_POS)) - -/* 0xF8 : osd_int_sts */ -#define OSD_DRAW_L_OSD_INT_STS_OFFSET (0xF8) -#define OSD_DRAW_L_REG_OSD_SEOF_INT_CLR_W OSD_DRAW_L_REG_OSD_SEOF_INT_CLR_W -#define OSD_DRAW_L_REG_OSD_SEOF_INT_CLR_W_POS (0U) -#define OSD_DRAW_L_REG_OSD_SEOF_INT_CLR_W_LEN (1U) -#define OSD_DRAW_L_REG_OSD_SEOF_INT_CLR_W_MSK (((1U << OSD_DRAW_L_REG_OSD_SEOF_INT_CLR_W_LEN) - 1) << OSD_DRAW_L_REG_OSD_SEOF_INT_CLR_W_POS) -#define OSD_DRAW_L_REG_OSD_SEOF_INT_CLR_W_UMSK (~(((1U << OSD_DRAW_L_REG_OSD_SEOF_INT_CLR_W_LEN) - 1) << OSD_DRAW_L_REG_OSD_SEOF_INT_CLR_W_POS)) -#define OSD_DRAW_L_REG_OSD_SEOF_INT_MASK_W OSD_DRAW_L_REG_OSD_SEOF_INT_MASK_W -#define OSD_DRAW_L_REG_OSD_SEOF_INT_MASK_W_POS (1U) -#define OSD_DRAW_L_REG_OSD_SEOF_INT_MASK_W_LEN (1U) -#define OSD_DRAW_L_REG_OSD_SEOF_INT_MASK_W_MSK (((1U << OSD_DRAW_L_REG_OSD_SEOF_INT_MASK_W_LEN) - 1) << OSD_DRAW_L_REG_OSD_SEOF_INT_MASK_W_POS) -#define OSD_DRAW_L_REG_OSD_SEOF_INT_MASK_W_UMSK (~(((1U << OSD_DRAW_L_REG_OSD_SEOF_INT_MASK_W_LEN) - 1) << OSD_DRAW_L_REG_OSD_SEOF_INT_MASK_W_POS)) -#define OSD_DRAW_L_REG_OSD_SEOF_INT_EDGE_W OSD_DRAW_L_REG_OSD_SEOF_INT_EDGE_W -#define OSD_DRAW_L_REG_OSD_SEOF_INT_EDGE_W_POS (2U) -#define OSD_DRAW_L_REG_OSD_SEOF_INT_EDGE_W_LEN (1U) -#define OSD_DRAW_L_REG_OSD_SEOF_INT_EDGE_W_MSK (((1U << OSD_DRAW_L_REG_OSD_SEOF_INT_EDGE_W_LEN) - 1) << OSD_DRAW_L_REG_OSD_SEOF_INT_EDGE_W_POS) -#define OSD_DRAW_L_REG_OSD_SEOF_INT_EDGE_W_UMSK (~(((1U << OSD_DRAW_L_REG_OSD_SEOF_INT_EDGE_W_LEN) - 1) << OSD_DRAW_L_REG_OSD_SEOF_INT_EDGE_W_POS)) -#define OSD_DRAW_L_STS_OSD_DRAIN_INT_R OSD_DRAW_L_STS_OSD_DRAIN_INT_R -#define OSD_DRAW_L_STS_OSD_DRAIN_INT_R_POS (16U) -#define OSD_DRAW_L_STS_OSD_DRAIN_INT_R_LEN (4U) -#define OSD_DRAW_L_STS_OSD_DRAIN_INT_R_MSK (((1U << OSD_DRAW_L_STS_OSD_DRAIN_INT_R_LEN) - 1) << OSD_DRAW_L_STS_OSD_DRAIN_INT_R_POS) -#define OSD_DRAW_L_STS_OSD_DRAIN_INT_R_UMSK (~(((1U << OSD_DRAW_L_STS_OSD_DRAIN_INT_R_LEN) - 1) << OSD_DRAW_L_STS_OSD_DRAIN_INT_R_POS)) -#define OSD_DRAW_L_STS_OSD_SEOF_INT_R OSD_DRAW_L_STS_OSD_SEOF_INT_R -#define OSD_DRAW_L_STS_OSD_SEOF_INT_R_POS (20U) -#define OSD_DRAW_L_STS_OSD_SEOF_INT_R_LEN (1U) -#define OSD_DRAW_L_STS_OSD_SEOF_INT_R_MSK (((1U << OSD_DRAW_L_STS_OSD_SEOF_INT_R_LEN) - 1) << OSD_DRAW_L_STS_OSD_SEOF_INT_R_POS) -#define OSD_DRAW_L_STS_OSD_SEOF_INT_R_UMSK (~(((1U << OSD_DRAW_L_STS_OSD_SEOF_INT_R_LEN) - 1) << OSD_DRAW_L_STS_OSD_SEOF_INT_R_POS)) - -/* 0xFC : osd_misc */ -#define OSD_DRAW_L_OSD_MISC_OFFSET (0xFC) -#define OSD_DRAW_L_REG_OSD_BUS_STRT_W OSD_DRAW_L_REG_OSD_BUS_STRT_W -#define OSD_DRAW_L_REG_OSD_BUS_STRT_W_POS (0U) -#define OSD_DRAW_L_REG_OSD_BUS_STRT_W_LEN (1U) -#define OSD_DRAW_L_REG_OSD_BUS_STRT_W_MSK (((1U << OSD_DRAW_L_REG_OSD_BUS_STRT_W_LEN) - 1) << OSD_DRAW_L_REG_OSD_BUS_STRT_W_POS) -#define OSD_DRAW_L_REG_OSD_BUS_STRT_W_UMSK (~(((1U << OSD_DRAW_L_REG_OSD_BUS_STRT_W_LEN) - 1) << OSD_DRAW_L_REG_OSD_BUS_STRT_W_POS)) -#define OSD_DRAW_L_REG_OSD_FIFO_AUTO_CLR_W OSD_DRAW_L_REG_OSD_FIFO_AUTO_CLR_W -#define OSD_DRAW_L_REG_OSD_FIFO_AUTO_CLR_W_POS (1U) -#define OSD_DRAW_L_REG_OSD_FIFO_AUTO_CLR_W_LEN (1U) -#define OSD_DRAW_L_REG_OSD_FIFO_AUTO_CLR_W_MSK (((1U << OSD_DRAW_L_REG_OSD_FIFO_AUTO_CLR_W_LEN) - 1) << OSD_DRAW_L_REG_OSD_FIFO_AUTO_CLR_W_POS) -#define OSD_DRAW_L_REG_OSD_FIFO_AUTO_CLR_W_UMSK (~(((1U << OSD_DRAW_L_REG_OSD_FIFO_AUTO_CLR_W_LEN) - 1) << OSD_DRAW_L_REG_OSD_FIFO_AUTO_CLR_W_POS)) -#define OSD_DRAW_L_REG_QOS_SW_MODE_W OSD_DRAW_L_REG_QOS_SW_MODE_W -#define OSD_DRAW_L_REG_QOS_SW_MODE_W_POS (4U) -#define OSD_DRAW_L_REG_QOS_SW_MODE_W_LEN (1U) -#define OSD_DRAW_L_REG_QOS_SW_MODE_W_MSK (((1U << OSD_DRAW_L_REG_QOS_SW_MODE_W_LEN) - 1) << OSD_DRAW_L_REG_QOS_SW_MODE_W_POS) -#define OSD_DRAW_L_REG_QOS_SW_MODE_W_UMSK (~(((1U << OSD_DRAW_L_REG_QOS_SW_MODE_W_LEN) - 1) << OSD_DRAW_L_REG_QOS_SW_MODE_W_POS)) -#define OSD_DRAW_L_REG_QOS_SW_W OSD_DRAW_L_REG_QOS_SW_W -#define OSD_DRAW_L_REG_QOS_SW_W_POS (5U) -#define OSD_DRAW_L_REG_QOS_SW_W_LEN (1U) -#define OSD_DRAW_L_REG_QOS_SW_W_MSK (((1U << OSD_DRAW_L_REG_QOS_SW_W_LEN) - 1) << OSD_DRAW_L_REG_QOS_SW_W_POS) -#define OSD_DRAW_L_REG_QOS_SW_W_UMSK (~(((1U << OSD_DRAW_L_REG_QOS_SW_W_LEN) - 1) << OSD_DRAW_L_REG_QOS_SW_W_POS)) -#define OSD_DRAW_L_REG_OSD_OSTD_MAX_W OSD_DRAW_L_REG_OSD_OSTD_MAX_W -#define OSD_DRAW_L_REG_OSD_OSTD_MAX_W_POS (8U) -#define OSD_DRAW_L_REG_OSD_OSTD_MAX_W_LEN (2U) -#define OSD_DRAW_L_REG_OSD_OSTD_MAX_W_MSK (((1U << OSD_DRAW_L_REG_OSD_OSTD_MAX_W_LEN) - 1) << OSD_DRAW_L_REG_OSD_OSTD_MAX_W_POS) -#define OSD_DRAW_L_REG_OSD_OSTD_MAX_W_UMSK (~(((1U << OSD_DRAW_L_REG_OSD_OSTD_MAX_W_LEN) - 1) << OSD_DRAW_L_REG_OSD_OSTD_MAX_W_POS)) -#define OSD_DRAW_L_REG_XLEN_W OSD_DRAW_L_REG_XLEN_W -#define OSD_DRAW_L_REG_XLEN_W_POS (12U) -#define OSD_DRAW_L_REG_XLEN_W_LEN (3U) -#define OSD_DRAW_L_REG_XLEN_W_MSK (((1U << OSD_DRAW_L_REG_XLEN_W_LEN) - 1) << OSD_DRAW_L_REG_XLEN_W_POS) -#define OSD_DRAW_L_REG_XLEN_W_UMSK (~(((1U << OSD_DRAW_L_REG_XLEN_W_LEN) - 1) << OSD_DRAW_L_REG_XLEN_W_POS)) -#define OSD_DRAW_L_STS_OSD_L0_CMD_IDLE_R OSD_DRAW_L_STS_OSD_L0_CMD_IDLE_R -#define OSD_DRAW_L_STS_OSD_L0_CMD_IDLE_R_POS (16U) -#define OSD_DRAW_L_STS_OSD_L0_CMD_IDLE_R_LEN (1U) -#define OSD_DRAW_L_STS_OSD_L0_CMD_IDLE_R_MSK (((1U << OSD_DRAW_L_STS_OSD_L0_CMD_IDLE_R_LEN) - 1) << OSD_DRAW_L_STS_OSD_L0_CMD_IDLE_R_POS) -#define OSD_DRAW_L_STS_OSD_L0_CMD_IDLE_R_UMSK (~(((1U << OSD_DRAW_L_STS_OSD_L0_CMD_IDLE_R_LEN) - 1) << OSD_DRAW_L_STS_OSD_L0_CMD_IDLE_R_POS)) -#define OSD_DRAW_L_STS_OSD_L1_CMD_IDLE_R OSD_DRAW_L_STS_OSD_L1_CMD_IDLE_R -#define OSD_DRAW_L_STS_OSD_L1_CMD_IDLE_R_POS (17U) -#define OSD_DRAW_L_STS_OSD_L1_CMD_IDLE_R_LEN (1U) -#define OSD_DRAW_L_STS_OSD_L1_CMD_IDLE_R_MSK (((1U << OSD_DRAW_L_STS_OSD_L1_CMD_IDLE_R_LEN) - 1) << OSD_DRAW_L_STS_OSD_L1_CMD_IDLE_R_POS) -#define OSD_DRAW_L_STS_OSD_L1_CMD_IDLE_R_UMSK (~(((1U << OSD_DRAW_L_STS_OSD_L1_CMD_IDLE_R_LEN) - 1) << OSD_DRAW_L_STS_OSD_L1_CMD_IDLE_R_POS)) -#define OSD_DRAW_L_STS_OSD_L2_CMD_IDLE_R OSD_DRAW_L_STS_OSD_L2_CMD_IDLE_R -#define OSD_DRAW_L_STS_OSD_L2_CMD_IDLE_R_POS (18U) -#define OSD_DRAW_L_STS_OSD_L2_CMD_IDLE_R_LEN (1U) -#define OSD_DRAW_L_STS_OSD_L2_CMD_IDLE_R_MSK (((1U << OSD_DRAW_L_STS_OSD_L2_CMD_IDLE_R_LEN) - 1) << OSD_DRAW_L_STS_OSD_L2_CMD_IDLE_R_POS) -#define OSD_DRAW_L_STS_OSD_L2_CMD_IDLE_R_UMSK (~(((1U << OSD_DRAW_L_STS_OSD_L2_CMD_IDLE_R_LEN) - 1) << OSD_DRAW_L_STS_OSD_L2_CMD_IDLE_R_POS)) -#define OSD_DRAW_L_STS_OSD_L3_CMD_IDLE_R OSD_DRAW_L_STS_OSD_L3_CMD_IDLE_R -#define OSD_DRAW_L_STS_OSD_L3_CMD_IDLE_R_POS (19U) -#define OSD_DRAW_L_STS_OSD_L3_CMD_IDLE_R_LEN (1U) -#define OSD_DRAW_L_STS_OSD_L3_CMD_IDLE_R_MSK (((1U << OSD_DRAW_L_STS_OSD_L3_CMD_IDLE_R_LEN) - 1) << OSD_DRAW_L_STS_OSD_L3_CMD_IDLE_R_POS) -#define OSD_DRAW_L_STS_OSD_L3_CMD_IDLE_R_UMSK (~(((1U << OSD_DRAW_L_STS_OSD_L3_CMD_IDLE_R_LEN) - 1) << OSD_DRAW_L_STS_OSD_L3_CMD_IDLE_R_POS)) -#define OSD_DRAW_L_STS_OSD_AXI_IDLE_R OSD_DRAW_L_STS_OSD_AXI_IDLE_R -#define OSD_DRAW_L_STS_OSD_AXI_IDLE_R_POS (20U) -#define OSD_DRAW_L_STS_OSD_AXI_IDLE_R_LEN (1U) -#define OSD_DRAW_L_STS_OSD_AXI_IDLE_R_MSK (((1U << OSD_DRAW_L_STS_OSD_AXI_IDLE_R_LEN) - 1) << OSD_DRAW_L_STS_OSD_AXI_IDLE_R_POS) -#define OSD_DRAW_L_STS_OSD_AXI_IDLE_R_UMSK (~(((1U << OSD_DRAW_L_STS_OSD_AXI_IDLE_R_LEN) - 1) << OSD_DRAW_L_STS_OSD_AXI_IDLE_R_POS)) -#define OSD_DRAW_L_REG_OSD_PCLK_FORCE_ON_W OSD_DRAW_L_REG_OSD_PCLK_FORCE_ON_W -#define OSD_DRAW_L_REG_OSD_PCLK_FORCE_ON_W_POS (24U) -#define OSD_DRAW_L_REG_OSD_PCLK_FORCE_ON_W_LEN (8U) -#define OSD_DRAW_L_REG_OSD_PCLK_FORCE_ON_W_MSK (((1U << OSD_DRAW_L_REG_OSD_PCLK_FORCE_ON_W_LEN) - 1) << OSD_DRAW_L_REG_OSD_PCLK_FORCE_ON_W_POS) -#define OSD_DRAW_L_REG_OSD_PCLK_FORCE_ON_W_UMSK (~(((1U << OSD_DRAW_L_REG_OSD_PCLK_FORCE_ON_W_LEN) - 1) << OSD_DRAW_L_REG_OSD_PCLK_FORCE_ON_W_POS)) - -struct osd_draw_l_reg { - /* 0x0 : osd_draw_config */ - union { - struct { - uint32_t reg_draw_en_l : 16; /* [15: 0], r/w, 0x0 */ - uint32_t reg_draw_type_l : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } osd_draw_config; - - /* 0x4 : draw_partial_yuv_config0 */ - union { - struct { - uint32_t reg_draw_th_00 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_00 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_00 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_00 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config0; - - /* 0x8 : draw_partial_x_config0 */ - union { - struct { - uint32_t reg_draw_x_min_00 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_00 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config0; - - /* 0xC : draw_partial_y_config0 */ - union { - struct { - uint32_t reg_draw_y_min_00 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_00 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config0; - - /* 0x10 : draw_partial_yuv_config1 */ - union { - struct { - uint32_t reg_draw_th_01 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_01 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_01 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_01 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config1; - - /* 0x14 : draw_partial_x_config1 */ - union { - struct { - uint32_t reg_draw_x_min_01 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_01 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config1; - - /* 0x18 : draw_partial_y_config1 */ - union { - struct { - uint32_t reg_draw_y_min_01 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_01 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config1; - - /* 0x1C : draw_partial_yuv_config2 */ - union { - struct { - uint32_t reg_draw_th_02 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_02 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_02 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_02 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config2; - - /* 0x20 : draw_partial_x_config2 */ - union { - struct { - uint32_t reg_draw_x_min_02 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_02 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config2; - - /* 0x24 : draw_partial_y_config2 */ - union { - struct { - uint32_t reg_draw_y_min_02 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_02 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config2; - - /* 0x28 : draw_partial_yuv_config3 */ - union { - struct { - uint32_t reg_draw_th_03 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_03 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_03 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_03 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config3; - - /* 0x2C : draw_partial_x_config3 */ - union { - struct { - uint32_t reg_draw_x_min_03 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_03 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config3; - - /* 0x30 : draw_partial_y_config3 */ - union { - struct { - uint32_t reg_draw_y_min_03 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_03 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config3; - - /* 0x34 : draw_partial_yuv_config4 */ - union { - struct { - uint32_t reg_draw_th_04 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_04 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_04 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_04 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config4; - - /* 0x38 : draw_partial_x_config4 */ - union { - struct { - uint32_t reg_draw_x_min_04 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_04 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config4; - - /* 0x3C : draw_partial_y_config4 */ - union { - struct { - uint32_t reg_draw_y_min_04 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_04 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config4; - - /* 0x40 : draw_partial_yuv_config5 */ - union { - struct { - uint32_t reg_draw_th_05 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_05 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_05 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_05 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config5; - - /* 0x44 : draw_partial_x_config5 */ - union { - struct { - uint32_t reg_draw_x_min_05 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_05 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config5; - - /* 0x48 : draw_partial_y_config5 */ - union { - struct { - uint32_t reg_draw_y_min_05 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_05 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config5; - - /* 0x4C : draw_partial_yuv_config6 */ - union { - struct { - uint32_t reg_draw_th_06 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_06 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_06 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_06 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config6; - - /* 0x50 : draw_partial_x_config6 */ - union { - struct { - uint32_t reg_draw_x_min_06 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_06 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config6; - - /* 0x54 : draw_partial_y_config6 */ - union { - struct { - uint32_t reg_draw_y_min_06 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_06 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config6; - - /* 0x58 : draw_partial_yuv_config7 */ - union { - struct { - uint32_t reg_draw_th_07 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_07 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_07 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_07 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config7; - - /* 0x5C : draw_partial_x_config7 */ - union { - struct { - uint32_t reg_draw_x_min_07 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_07 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config7; - - /* 0x60 : draw_partial_y_config7 */ - union { - struct { - uint32_t reg_draw_y_min_07 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_07 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config7; - - /* 0x64 : draw_partial_yuv_config8 */ - union { - struct { - uint32_t reg_draw_th_08 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_08 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_08 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_08 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config8; - - /* 0x68 : draw_partial_x_config8 */ - union { - struct { - uint32_t reg_draw_x_min_08 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_08 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config8; - - /* 0x6C : draw_partial_y_config8 */ - union { - struct { - uint32_t reg_draw_y_min_08 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_08 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config8; - - /* 0x70 : draw_partial_yuv_config9 */ - union { - struct { - uint32_t reg_draw_th_09 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_09 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_09 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_09 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config9; - - /* 0x74 : draw_partial_x_config9 */ - union { - struct { - uint32_t reg_draw_x_min_09 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_09 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config9; - - /* 0x78 : draw_partial_y_config9 */ - union { - struct { - uint32_t reg_draw_y_min_09 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_09 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config9; - - /* 0x7C : draw_partial_yuv_configa */ - union { - struct { - uint32_t reg_draw_th_0a : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_0a : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_0a : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_0a : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_configa; - - /* 0x80 : draw_partial_x_configa */ - union { - struct { - uint32_t reg_draw_x_min_0a : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_0a : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_configa; - - /* 0x84 : draw_partial_y_configa */ - union { - struct { - uint32_t reg_draw_y_min_0a : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_0a : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_configa; - - /* 0x88 : draw_partial_yuv_configb */ - union { - struct { - uint32_t reg_draw_th_0b : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_0b : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_0b : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_0b : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_configb; - - /* 0x8C : draw_partial_x_configb */ - union { - struct { - uint32_t reg_draw_x_min_0b : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_0b : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_configb; - - /* 0x90 : draw_partial_y_configb */ - union { - struct { - uint32_t reg_draw_y_min_0b : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_0b : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_configb; - - /* 0x94 : draw_partial_yuv_configc */ - union { - struct { - uint32_t reg_draw_th_0c : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_0c : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_0c : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_0c : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_configc; - - /* 0x98 : draw_partial_x_configc */ - union { - struct { - uint32_t reg_draw_x_min_0c : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_0c : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_configc; - - /* 0x9C : draw_partial_y_configc */ - union { - struct { - uint32_t reg_draw_y_min_0c : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_0c : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_configc; - - /* 0xA0 : draw_partial_yuv_configd */ - union { - struct { - uint32_t reg_draw_th_0d : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_0d : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_0d : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_0d : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_configd; - - /* 0xA4 : draw_partial_x_configd */ - union { - struct { - uint32_t reg_draw_x_min_0d : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_0d : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_configd; - - /* 0xA8 : draw_partial_y_configd */ - union { - struct { - uint32_t reg_draw_y_min_0d : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_0d : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_configd; - - /* 0xAC : draw_partial_yuv_confige */ - union { - struct { - uint32_t reg_draw_th_0e : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_0e : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_0e : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_0e : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_confige; - - /* 0xB0 : draw_partial_x_confige */ - union { - struct { - uint32_t reg_draw_x_min_0e : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_0e : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_confige; - - /* 0xB4 : draw_partial_y_confige */ - union { - struct { - uint32_t reg_draw_y_min_0e : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_0e : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_confige; - - /* 0xB8 : draw_partial_yuv_configf */ - union { - struct { - uint32_t reg_draw_th_0f : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_0f : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_0f : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_0f : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_configf; - - /* 0xBC : draw_partial_x_configf */ - union { - struct { - uint32_t reg_draw_x_min_0f : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_0f : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_configf; - - /* 0xC0 : draw_partial_y_configf */ - union { - struct { - uint32_t reg_draw_y_min_0f : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_0f : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_configf; - - /* 0xc4 reserved */ - uint8_t RESERVED0xc4[52]; - - /* 0xF8 : osd_int_sts */ - union { - struct { - uint32_t reg_osd_seof_int_clr_w : 1; /* [ 0], w1p, 0x0 */ - uint32_t reg_osd_seof_int_mask_w : 1; /* [ 1], r/w, 0x0 */ - uint32_t reg_osd_seof_int_edge_w : 1; /* [ 2], r/w, 0x0 */ - uint32_t reserved_3_15 : 13; /* [15: 3], rsvd, 0x0 */ - uint32_t sts_osd_drain_int_r : 4; /* [19:16], r, 0x0 */ - uint32_t sts_osd_seof_int_r : 1; /* [ 20], r, 0x0 */ - uint32_t reserved_21_31 : 11; /* [31:21], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_int_sts; - - /* 0xFC : osd_misc */ - union { - struct { - uint32_t reg_osd_bus_strt_w : 1; /* [ 0], w1p, 0x0 */ - uint32_t reg_osd_fifo_auto_clr_w : 1; /* [ 1], r/w, 0x1 */ - uint32_t reserved_2_3 : 2; /* [ 3: 2], rsvd, 0x0 */ - uint32_t reg_qos_sw_mode_w : 1; /* [ 4], r/w, 0x0 */ - uint32_t reg_qos_sw_w : 1; /* [ 5], r/w, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t reg_osd_ostd_max_w : 2; /* [ 9: 8], r/w, 0x3 */ - uint32_t reserved_10_11 : 2; /* [11:10], rsvd, 0x0 */ - uint32_t reg_xlen_w : 3; /* [14:12], r/w, 0x4 */ - uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */ - uint32_t sts_osd_l0_cmd_idle_r : 1; /* [ 16], r, 0x0 */ - uint32_t sts_osd_l1_cmd_idle_r : 1; /* [ 17], r, 0x0 */ - uint32_t sts_osd_l2_cmd_idle_r : 1; /* [ 18], r, 0x0 */ - uint32_t sts_osd_l3_cmd_idle_r : 1; /* [ 19], r, 0x0 */ - uint32_t sts_osd_axi_idle_r : 1; /* [ 20], r, 0x0 */ - uint32_t reserved_21_23 : 3; /* [23:21], rsvd, 0x0 */ - uint32_t reg_osd_pclk_force_on_w : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } osd_misc; -}; - -typedef volatile struct osd_draw_l_reg osd_draw_l_reg_t; - -#endif /* __OSD_DRAW_L_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/osd_draw_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/osd_draw_reg.h deleted file mode 100644 index cb72bcfc1b..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/osd_draw_reg.h +++ /dev/null @@ -1,1511 +0,0 @@ -/** - ****************************************************************************** - * @file osd_reg.h - * @version V1.0 - * @date 2020-12-25 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __OSD_REG_H__ -#define __OSD_REG_H__ - -#include "bl808.h" - -/* 0x0 : osd_draw_config */ -#define OSD_DRAW_CONFIG_OFFSET (0x0) -#define OSD_REG_DRAW_EN_L OSD_REG_DRAW_EN_L -#define OSD_REG_DRAW_EN_L_POS (0U) -#define OSD_REG_DRAW_EN_L_LEN (16U) -#define OSD_REG_DRAW_EN_L_MSK (((1U << OSD_REG_DRAW_EN_L_LEN) - 1) << OSD_REG_DRAW_EN_L_POS) -#define OSD_REG_DRAW_EN_L_UMSK (~(((1U << OSD_REG_DRAW_EN_L_LEN) - 1) << OSD_REG_DRAW_EN_L_POS)) -#define OSD_REG_DRAW_TYPE_L OSD_REG_DRAW_TYPE_L -#define OSD_REG_DRAW_TYPE_L_POS (16U) -#define OSD_REG_DRAW_TYPE_L_LEN (16U) -#define OSD_REG_DRAW_TYPE_L_MSK (((1U << OSD_REG_DRAW_TYPE_L_LEN) - 1) << OSD_REG_DRAW_TYPE_L_POS) -#define OSD_REG_DRAW_TYPE_L_UMSK (~(((1U << OSD_REG_DRAW_TYPE_L_LEN) - 1) << OSD_REG_DRAW_TYPE_L_POS)) - -/* 0x4 : draw_partial_yuv_config0 */ -#define OSD_DRAW_PARTIAL_YUV_CONFIG0_OFFSET (0x4) -#define OSD_REG_DRAW_TH_00 OSD_REG_DRAW_TH_00 -#define OSD_REG_DRAW_TH_00_POS (0U) -#define OSD_REG_DRAW_TH_00_LEN (8U) -#define OSD_REG_DRAW_TH_00_MSK (((1U << OSD_REG_DRAW_TH_00_LEN) - 1) << OSD_REG_DRAW_TH_00_POS) -#define OSD_REG_DRAW_TH_00_UMSK (~(((1U << OSD_REG_DRAW_TH_00_LEN) - 1) << OSD_REG_DRAW_TH_00_POS)) -#define OSD_REG_DRAW_V_00 OSD_REG_DRAW_V_00 -#define OSD_REG_DRAW_V_00_POS (8U) -#define OSD_REG_DRAW_V_00_LEN (8U) -#define OSD_REG_DRAW_V_00_MSK (((1U << OSD_REG_DRAW_V_00_LEN) - 1) << OSD_REG_DRAW_V_00_POS) -#define OSD_REG_DRAW_V_00_UMSK (~(((1U << OSD_REG_DRAW_V_00_LEN) - 1) << OSD_REG_DRAW_V_00_POS)) -#define OSD_REG_DRAW_U_00 OSD_REG_DRAW_U_00 -#define OSD_REG_DRAW_U_00_POS (16U) -#define OSD_REG_DRAW_U_00_LEN (8U) -#define OSD_REG_DRAW_U_00_MSK (((1U << OSD_REG_DRAW_U_00_LEN) - 1) << OSD_REG_DRAW_U_00_POS) -#define OSD_REG_DRAW_U_00_UMSK (~(((1U << OSD_REG_DRAW_U_00_LEN) - 1) << OSD_REG_DRAW_U_00_POS)) -#define OSD_REG_DRAW_Y_00 OSD_REG_DRAW_Y_00 -#define OSD_REG_DRAW_Y_00_POS (24U) -#define OSD_REG_DRAW_Y_00_LEN (8U) -#define OSD_REG_DRAW_Y_00_MSK (((1U << OSD_REG_DRAW_Y_00_LEN) - 1) << OSD_REG_DRAW_Y_00_POS) -#define OSD_REG_DRAW_Y_00_UMSK (~(((1U << OSD_REG_DRAW_Y_00_LEN) - 1) << OSD_REG_DRAW_Y_00_POS)) - -/* 0x8 : draw_partial_x_config0 */ -#define OSD_DRAW_PARTIAL_X_CONFIG0_OFFSET (0x8) -#define OSD_REG_DRAW_X_MIN_00 OSD_REG_DRAW_X_MIN_00 -#define OSD_REG_DRAW_X_MIN_00_POS (0U) -#define OSD_REG_DRAW_X_MIN_00_LEN (11U) -#define OSD_REG_DRAW_X_MIN_00_MSK (((1U << OSD_REG_DRAW_X_MIN_00_LEN) - 1) << OSD_REG_DRAW_X_MIN_00_POS) -#define OSD_REG_DRAW_X_MIN_00_UMSK (~(((1U << OSD_REG_DRAW_X_MIN_00_LEN) - 1) << OSD_REG_DRAW_X_MIN_00_POS)) -#define OSD_REG_DRAW_X_MAX_00 OSD_REG_DRAW_X_MAX_00 -#define OSD_REG_DRAW_X_MAX_00_POS (16U) -#define OSD_REG_DRAW_X_MAX_00_LEN (11U) -#define OSD_REG_DRAW_X_MAX_00_MSK (((1U << OSD_REG_DRAW_X_MAX_00_LEN) - 1) << OSD_REG_DRAW_X_MAX_00_POS) -#define OSD_REG_DRAW_X_MAX_00_UMSK (~(((1U << OSD_REG_DRAW_X_MAX_00_LEN) - 1) << OSD_REG_DRAW_X_MAX_00_POS)) - -/* 0xC : draw_partial_y_config0 */ -#define OSD_DRAW_PARTIAL_Y_CONFIG0_OFFSET (0xC) -#define OSD_REG_DRAW_Y_MIN_00 OSD_REG_DRAW_Y_MIN_00 -#define OSD_REG_DRAW_Y_MIN_00_POS (0U) -#define OSD_REG_DRAW_Y_MIN_00_LEN (11U) -#define OSD_REG_DRAW_Y_MIN_00_MSK (((1U << OSD_REG_DRAW_Y_MIN_00_LEN) - 1) << OSD_REG_DRAW_Y_MIN_00_POS) -#define OSD_REG_DRAW_Y_MIN_00_UMSK (~(((1U << OSD_REG_DRAW_Y_MIN_00_LEN) - 1) << OSD_REG_DRAW_Y_MIN_00_POS)) -#define OSD_REG_DRAW_Y_MAX_00 OSD_REG_DRAW_Y_MAX_00 -#define OSD_REG_DRAW_Y_MAX_00_POS (16U) -#define OSD_REG_DRAW_Y_MAX_00_LEN (11U) -#define OSD_REG_DRAW_Y_MAX_00_MSK (((1U << OSD_REG_DRAW_Y_MAX_00_LEN) - 1) << OSD_REG_DRAW_Y_MAX_00_POS) -#define OSD_REG_DRAW_Y_MAX_00_UMSK (~(((1U << OSD_REG_DRAW_Y_MAX_00_LEN) - 1) << OSD_REG_DRAW_Y_MAX_00_POS)) - -/* 0x10 : draw_partial_yuv_config1 */ -#define OSD_DRAW_PARTIAL_YUV_CONFIG1_OFFSET (0x10) -#define OSD_REG_DRAW_TH_01 OSD_REG_DRAW_TH_01 -#define OSD_REG_DRAW_TH_01_POS (0U) -#define OSD_REG_DRAW_TH_01_LEN (8U) -#define OSD_REG_DRAW_TH_01_MSK (((1U << OSD_REG_DRAW_TH_01_LEN) - 1) << OSD_REG_DRAW_TH_01_POS) -#define OSD_REG_DRAW_TH_01_UMSK (~(((1U << OSD_REG_DRAW_TH_01_LEN) - 1) << OSD_REG_DRAW_TH_01_POS)) -#define OSD_REG_DRAW_V_01 OSD_REG_DRAW_V_01 -#define OSD_REG_DRAW_V_01_POS (8U) -#define OSD_REG_DRAW_V_01_LEN (8U) -#define OSD_REG_DRAW_V_01_MSK (((1U << OSD_REG_DRAW_V_01_LEN) - 1) << OSD_REG_DRAW_V_01_POS) -#define OSD_REG_DRAW_V_01_UMSK (~(((1U << OSD_REG_DRAW_V_01_LEN) - 1) << OSD_REG_DRAW_V_01_POS)) -#define OSD_REG_DRAW_U_01 OSD_REG_DRAW_U_01 -#define OSD_REG_DRAW_U_01_POS (16U) -#define OSD_REG_DRAW_U_01_LEN (8U) -#define OSD_REG_DRAW_U_01_MSK (((1U << OSD_REG_DRAW_U_01_LEN) - 1) << OSD_REG_DRAW_U_01_POS) -#define OSD_REG_DRAW_U_01_UMSK (~(((1U << OSD_REG_DRAW_U_01_LEN) - 1) << OSD_REG_DRAW_U_01_POS)) -#define OSD_REG_DRAW_Y_01 OSD_REG_DRAW_Y_01 -#define OSD_REG_DRAW_Y_01_POS (24U) -#define OSD_REG_DRAW_Y_01_LEN (8U) -#define OSD_REG_DRAW_Y_01_MSK (((1U << OSD_REG_DRAW_Y_01_LEN) - 1) << OSD_REG_DRAW_Y_01_POS) -#define OSD_REG_DRAW_Y_01_UMSK (~(((1U << OSD_REG_DRAW_Y_01_LEN) - 1) << OSD_REG_DRAW_Y_01_POS)) - -/* 0x14 : draw_partial_x_config1 */ -#define OSD_DRAW_PARTIAL_X_CONFIG1_OFFSET (0x14) -#define OSD_REG_DRAW_X_MIN_01 OSD_REG_DRAW_X_MIN_01 -#define OSD_REG_DRAW_X_MIN_01_POS (0U) -#define OSD_REG_DRAW_X_MIN_01_LEN (11U) -#define OSD_REG_DRAW_X_MIN_01_MSK (((1U << OSD_REG_DRAW_X_MIN_01_LEN) - 1) << OSD_REG_DRAW_X_MIN_01_POS) -#define OSD_REG_DRAW_X_MIN_01_UMSK (~(((1U << OSD_REG_DRAW_X_MIN_01_LEN) - 1) << OSD_REG_DRAW_X_MIN_01_POS)) -#define OSD_REG_DRAW_X_MAX_01 OSD_REG_DRAW_X_MAX_01 -#define OSD_REG_DRAW_X_MAX_01_POS (16U) -#define OSD_REG_DRAW_X_MAX_01_LEN (11U) -#define OSD_REG_DRAW_X_MAX_01_MSK (((1U << OSD_REG_DRAW_X_MAX_01_LEN) - 1) << OSD_REG_DRAW_X_MAX_01_POS) -#define OSD_REG_DRAW_X_MAX_01_UMSK (~(((1U << OSD_REG_DRAW_X_MAX_01_LEN) - 1) << OSD_REG_DRAW_X_MAX_01_POS)) - -/* 0x18 : draw_partial_y_config1 */ -#define OSD_DRAW_PARTIAL_Y_CONFIG1_OFFSET (0x18) -#define OSD_REG_DRAW_Y_MIN_01 OSD_REG_DRAW_Y_MIN_01 -#define OSD_REG_DRAW_Y_MIN_01_POS (0U) -#define OSD_REG_DRAW_Y_MIN_01_LEN (11U) -#define OSD_REG_DRAW_Y_MIN_01_MSK (((1U << OSD_REG_DRAW_Y_MIN_01_LEN) - 1) << OSD_REG_DRAW_Y_MIN_01_POS) -#define OSD_REG_DRAW_Y_MIN_01_UMSK (~(((1U << OSD_REG_DRAW_Y_MIN_01_LEN) - 1) << OSD_REG_DRAW_Y_MIN_01_POS)) -#define OSD_REG_DRAW_Y_MAX_01 OSD_REG_DRAW_Y_MAX_01 -#define OSD_REG_DRAW_Y_MAX_01_POS (16U) -#define OSD_REG_DRAW_Y_MAX_01_LEN (11U) -#define OSD_REG_DRAW_Y_MAX_01_MSK (((1U << OSD_REG_DRAW_Y_MAX_01_LEN) - 1) << OSD_REG_DRAW_Y_MAX_01_POS) -#define OSD_REG_DRAW_Y_MAX_01_UMSK (~(((1U << OSD_REG_DRAW_Y_MAX_01_LEN) - 1) << OSD_REG_DRAW_Y_MAX_01_POS)) - -/* 0x1C : draw_partial_yuv_config2 */ -#define OSD_DRAW_PARTIAL_YUV_CONFIG2_OFFSET (0x1C) -#define OSD_REG_DRAW_TH_02 OSD_REG_DRAW_TH_02 -#define OSD_REG_DRAW_TH_02_POS (0U) -#define OSD_REG_DRAW_TH_02_LEN (8U) -#define OSD_REG_DRAW_TH_02_MSK (((1U << OSD_REG_DRAW_TH_02_LEN) - 1) << OSD_REG_DRAW_TH_02_POS) -#define OSD_REG_DRAW_TH_02_UMSK (~(((1U << OSD_REG_DRAW_TH_02_LEN) - 1) << OSD_REG_DRAW_TH_02_POS)) -#define OSD_REG_DRAW_V_02 OSD_REG_DRAW_V_02 -#define OSD_REG_DRAW_V_02_POS (8U) -#define OSD_REG_DRAW_V_02_LEN (8U) -#define OSD_REG_DRAW_V_02_MSK (((1U << OSD_REG_DRAW_V_02_LEN) - 1) << OSD_REG_DRAW_V_02_POS) -#define OSD_REG_DRAW_V_02_UMSK (~(((1U << OSD_REG_DRAW_V_02_LEN) - 1) << OSD_REG_DRAW_V_02_POS)) -#define OSD_REG_DRAW_U_02 OSD_REG_DRAW_U_02 -#define OSD_REG_DRAW_U_02_POS (16U) -#define OSD_REG_DRAW_U_02_LEN (8U) -#define OSD_REG_DRAW_U_02_MSK (((1U << OSD_REG_DRAW_U_02_LEN) - 1) << OSD_REG_DRAW_U_02_POS) -#define OSD_REG_DRAW_U_02_UMSK (~(((1U << OSD_REG_DRAW_U_02_LEN) - 1) << OSD_REG_DRAW_U_02_POS)) -#define OSD_REG_DRAW_Y_02 OSD_REG_DRAW_Y_02 -#define OSD_REG_DRAW_Y_02_POS (24U) -#define OSD_REG_DRAW_Y_02_LEN (8U) -#define OSD_REG_DRAW_Y_02_MSK (((1U << OSD_REG_DRAW_Y_02_LEN) - 1) << OSD_REG_DRAW_Y_02_POS) -#define OSD_REG_DRAW_Y_02_UMSK (~(((1U << OSD_REG_DRAW_Y_02_LEN) - 1) << OSD_REG_DRAW_Y_02_POS)) - -/* 0x20 : draw_partial_x_config2 */ -#define OSD_DRAW_PARTIAL_X_CONFIG2_OFFSET (0x20) -#define OSD_REG_DRAW_X_MIN_02 OSD_REG_DRAW_X_MIN_02 -#define OSD_REG_DRAW_X_MIN_02_POS (0U) -#define OSD_REG_DRAW_X_MIN_02_LEN (11U) -#define OSD_REG_DRAW_X_MIN_02_MSK (((1U << OSD_REG_DRAW_X_MIN_02_LEN) - 1) << OSD_REG_DRAW_X_MIN_02_POS) -#define OSD_REG_DRAW_X_MIN_02_UMSK (~(((1U << OSD_REG_DRAW_X_MIN_02_LEN) - 1) << OSD_REG_DRAW_X_MIN_02_POS)) -#define OSD_REG_DRAW_X_MAX_02 OSD_REG_DRAW_X_MAX_02 -#define OSD_REG_DRAW_X_MAX_02_POS (16U) -#define OSD_REG_DRAW_X_MAX_02_LEN (11U) -#define OSD_REG_DRAW_X_MAX_02_MSK (((1U << OSD_REG_DRAW_X_MAX_02_LEN) - 1) << OSD_REG_DRAW_X_MAX_02_POS) -#define OSD_REG_DRAW_X_MAX_02_UMSK (~(((1U << OSD_REG_DRAW_X_MAX_02_LEN) - 1) << OSD_REG_DRAW_X_MAX_02_POS)) - -/* 0x24 : draw_partial_y_config2 */ -#define OSD_DRAW_PARTIAL_Y_CONFIG2_OFFSET (0x24) -#define OSD_REG_DRAW_Y_MIN_02 OSD_REG_DRAW_Y_MIN_02 -#define OSD_REG_DRAW_Y_MIN_02_POS (0U) -#define OSD_REG_DRAW_Y_MIN_02_LEN (11U) -#define OSD_REG_DRAW_Y_MIN_02_MSK (((1U << OSD_REG_DRAW_Y_MIN_02_LEN) - 1) << OSD_REG_DRAW_Y_MIN_02_POS) -#define OSD_REG_DRAW_Y_MIN_02_UMSK (~(((1U << OSD_REG_DRAW_Y_MIN_02_LEN) - 1) << OSD_REG_DRAW_Y_MIN_02_POS)) -#define OSD_REG_DRAW_Y_MAX_02 OSD_REG_DRAW_Y_MAX_02 -#define OSD_REG_DRAW_Y_MAX_02_POS (16U) -#define OSD_REG_DRAW_Y_MAX_02_LEN (11U) -#define OSD_REG_DRAW_Y_MAX_02_MSK (((1U << OSD_REG_DRAW_Y_MAX_02_LEN) - 1) << OSD_REG_DRAW_Y_MAX_02_POS) -#define OSD_REG_DRAW_Y_MAX_02_UMSK (~(((1U << OSD_REG_DRAW_Y_MAX_02_LEN) - 1) << OSD_REG_DRAW_Y_MAX_02_POS)) - -/* 0x28 : draw_partial_yuv_config3 */ -#define OSD_DRAW_PARTIAL_YUV_CONFIG3_OFFSET (0x28) -#define OSD_REG_DRAW_TH_03 OSD_REG_DRAW_TH_03 -#define OSD_REG_DRAW_TH_03_POS (0U) -#define OSD_REG_DRAW_TH_03_LEN (8U) -#define OSD_REG_DRAW_TH_03_MSK (((1U << OSD_REG_DRAW_TH_03_LEN) - 1) << OSD_REG_DRAW_TH_03_POS) -#define OSD_REG_DRAW_TH_03_UMSK (~(((1U << OSD_REG_DRAW_TH_03_LEN) - 1) << OSD_REG_DRAW_TH_03_POS)) -#define OSD_REG_DRAW_V_03 OSD_REG_DRAW_V_03 -#define OSD_REG_DRAW_V_03_POS (8U) -#define OSD_REG_DRAW_V_03_LEN (8U) -#define OSD_REG_DRAW_V_03_MSK (((1U << OSD_REG_DRAW_V_03_LEN) - 1) << OSD_REG_DRAW_V_03_POS) -#define OSD_REG_DRAW_V_03_UMSK (~(((1U << OSD_REG_DRAW_V_03_LEN) - 1) << OSD_REG_DRAW_V_03_POS)) -#define OSD_REG_DRAW_U_03 OSD_REG_DRAW_U_03 -#define OSD_REG_DRAW_U_03_POS (16U) -#define OSD_REG_DRAW_U_03_LEN (8U) -#define OSD_REG_DRAW_U_03_MSK (((1U << OSD_REG_DRAW_U_03_LEN) - 1) << OSD_REG_DRAW_U_03_POS) -#define OSD_REG_DRAW_U_03_UMSK (~(((1U << OSD_REG_DRAW_U_03_LEN) - 1) << OSD_REG_DRAW_U_03_POS)) -#define OSD_REG_DRAW_Y_03 OSD_REG_DRAW_Y_03 -#define OSD_REG_DRAW_Y_03_POS (24U) -#define OSD_REG_DRAW_Y_03_LEN (8U) -#define OSD_REG_DRAW_Y_03_MSK (((1U << OSD_REG_DRAW_Y_03_LEN) - 1) << OSD_REG_DRAW_Y_03_POS) -#define OSD_REG_DRAW_Y_03_UMSK (~(((1U << OSD_REG_DRAW_Y_03_LEN) - 1) << OSD_REG_DRAW_Y_03_POS)) - -/* 0x2C : draw_partial_x_config3 */ -#define OSD_DRAW_PARTIAL_X_CONFIG3_OFFSET (0x2C) -#define OSD_REG_DRAW_X_MIN_03 OSD_REG_DRAW_X_MIN_03 -#define OSD_REG_DRAW_X_MIN_03_POS (0U) -#define OSD_REG_DRAW_X_MIN_03_LEN (11U) -#define OSD_REG_DRAW_X_MIN_03_MSK (((1U << OSD_REG_DRAW_X_MIN_03_LEN) - 1) << OSD_REG_DRAW_X_MIN_03_POS) -#define OSD_REG_DRAW_X_MIN_03_UMSK (~(((1U << OSD_REG_DRAW_X_MIN_03_LEN) - 1) << OSD_REG_DRAW_X_MIN_03_POS)) -#define OSD_REG_DRAW_X_MAX_03 OSD_REG_DRAW_X_MAX_03 -#define OSD_REG_DRAW_X_MAX_03_POS (16U) -#define OSD_REG_DRAW_X_MAX_03_LEN (11U) -#define OSD_REG_DRAW_X_MAX_03_MSK (((1U << OSD_REG_DRAW_X_MAX_03_LEN) - 1) << OSD_REG_DRAW_X_MAX_03_POS) -#define OSD_REG_DRAW_X_MAX_03_UMSK (~(((1U << OSD_REG_DRAW_X_MAX_03_LEN) - 1) << OSD_REG_DRAW_X_MAX_03_POS)) - -/* 0x30 : draw_partial_y_config3 */ -#define OSD_DRAW_PARTIAL_Y_CONFIG3_OFFSET (0x30) -#define OSD_REG_DRAW_Y_MIN_03 OSD_REG_DRAW_Y_MIN_03 -#define OSD_REG_DRAW_Y_MIN_03_POS (0U) -#define OSD_REG_DRAW_Y_MIN_03_LEN (11U) -#define OSD_REG_DRAW_Y_MIN_03_MSK (((1U << OSD_REG_DRAW_Y_MIN_03_LEN) - 1) << OSD_REG_DRAW_Y_MIN_03_POS) -#define OSD_REG_DRAW_Y_MIN_03_UMSK (~(((1U << OSD_REG_DRAW_Y_MIN_03_LEN) - 1) << OSD_REG_DRAW_Y_MIN_03_POS)) -#define OSD_REG_DRAW_Y_MAX_03 OSD_REG_DRAW_Y_MAX_03 -#define OSD_REG_DRAW_Y_MAX_03_POS (16U) -#define OSD_REG_DRAW_Y_MAX_03_LEN (11U) -#define OSD_REG_DRAW_Y_MAX_03_MSK (((1U << OSD_REG_DRAW_Y_MAX_03_LEN) - 1) << OSD_REG_DRAW_Y_MAX_03_POS) -#define OSD_REG_DRAW_Y_MAX_03_UMSK (~(((1U << OSD_REG_DRAW_Y_MAX_03_LEN) - 1) << OSD_REG_DRAW_Y_MAX_03_POS)) - -/* 0x34 : draw_partial_yuv_config4 */ -#define OSD_DRAW_PARTIAL_YUV_CONFIG4_OFFSET (0x34) -#define OSD_REG_DRAW_TH_04 OSD_REG_DRAW_TH_04 -#define OSD_REG_DRAW_TH_04_POS (0U) -#define OSD_REG_DRAW_TH_04_LEN (8U) -#define OSD_REG_DRAW_TH_04_MSK (((1U << OSD_REG_DRAW_TH_04_LEN) - 1) << OSD_REG_DRAW_TH_04_POS) -#define OSD_REG_DRAW_TH_04_UMSK (~(((1U << OSD_REG_DRAW_TH_04_LEN) - 1) << OSD_REG_DRAW_TH_04_POS)) -#define OSD_REG_DRAW_V_04 OSD_REG_DRAW_V_04 -#define OSD_REG_DRAW_V_04_POS (8U) -#define OSD_REG_DRAW_V_04_LEN (8U) -#define OSD_REG_DRAW_V_04_MSK (((1U << OSD_REG_DRAW_V_04_LEN) - 1) << OSD_REG_DRAW_V_04_POS) -#define OSD_REG_DRAW_V_04_UMSK (~(((1U << OSD_REG_DRAW_V_04_LEN) - 1) << OSD_REG_DRAW_V_04_POS)) -#define OSD_REG_DRAW_U_04 OSD_REG_DRAW_U_04 -#define OSD_REG_DRAW_U_04_POS (16U) -#define OSD_REG_DRAW_U_04_LEN (8U) -#define OSD_REG_DRAW_U_04_MSK (((1U << OSD_REG_DRAW_U_04_LEN) - 1) << OSD_REG_DRAW_U_04_POS) -#define OSD_REG_DRAW_U_04_UMSK (~(((1U << OSD_REG_DRAW_U_04_LEN) - 1) << OSD_REG_DRAW_U_04_POS)) -#define OSD_REG_DRAW_Y_04 OSD_REG_DRAW_Y_04 -#define OSD_REG_DRAW_Y_04_POS (24U) -#define OSD_REG_DRAW_Y_04_LEN (8U) -#define OSD_REG_DRAW_Y_04_MSK (((1U << OSD_REG_DRAW_Y_04_LEN) - 1) << OSD_REG_DRAW_Y_04_POS) -#define OSD_REG_DRAW_Y_04_UMSK (~(((1U << OSD_REG_DRAW_Y_04_LEN) - 1) << OSD_REG_DRAW_Y_04_POS)) - -/* 0x38 : draw_partial_x_config4 */ -#define OSD_DRAW_PARTIAL_X_CONFIG4_OFFSET (0x38) -#define OSD_REG_DRAW_X_MIN_04 OSD_REG_DRAW_X_MIN_04 -#define OSD_REG_DRAW_X_MIN_04_POS (0U) -#define OSD_REG_DRAW_X_MIN_04_LEN (11U) -#define OSD_REG_DRAW_X_MIN_04_MSK (((1U << OSD_REG_DRAW_X_MIN_04_LEN) - 1) << OSD_REG_DRAW_X_MIN_04_POS) -#define OSD_REG_DRAW_X_MIN_04_UMSK (~(((1U << OSD_REG_DRAW_X_MIN_04_LEN) - 1) << OSD_REG_DRAW_X_MIN_04_POS)) -#define OSD_REG_DRAW_X_MAX_04 OSD_REG_DRAW_X_MAX_04 -#define OSD_REG_DRAW_X_MAX_04_POS (16U) -#define OSD_REG_DRAW_X_MAX_04_LEN (11U) -#define OSD_REG_DRAW_X_MAX_04_MSK (((1U << OSD_REG_DRAW_X_MAX_04_LEN) - 1) << OSD_REG_DRAW_X_MAX_04_POS) -#define OSD_REG_DRAW_X_MAX_04_UMSK (~(((1U << OSD_REG_DRAW_X_MAX_04_LEN) - 1) << OSD_REG_DRAW_X_MAX_04_POS)) - -/* 0x3C : draw_partial_y_config4 */ -#define OSD_DRAW_PARTIAL_Y_CONFIG4_OFFSET (0x3C) -#define OSD_REG_DRAW_Y_MIN_04 OSD_REG_DRAW_Y_MIN_04 -#define OSD_REG_DRAW_Y_MIN_04_POS (0U) -#define OSD_REG_DRAW_Y_MIN_04_LEN (11U) -#define OSD_REG_DRAW_Y_MIN_04_MSK (((1U << OSD_REG_DRAW_Y_MIN_04_LEN) - 1) << OSD_REG_DRAW_Y_MIN_04_POS) -#define OSD_REG_DRAW_Y_MIN_04_UMSK (~(((1U << OSD_REG_DRAW_Y_MIN_04_LEN) - 1) << OSD_REG_DRAW_Y_MIN_04_POS)) -#define OSD_REG_DRAW_Y_MAX_04 OSD_REG_DRAW_Y_MAX_04 -#define OSD_REG_DRAW_Y_MAX_04_POS (16U) -#define OSD_REG_DRAW_Y_MAX_04_LEN (11U) -#define OSD_REG_DRAW_Y_MAX_04_MSK (((1U << OSD_REG_DRAW_Y_MAX_04_LEN) - 1) << OSD_REG_DRAW_Y_MAX_04_POS) -#define OSD_REG_DRAW_Y_MAX_04_UMSK (~(((1U << OSD_REG_DRAW_Y_MAX_04_LEN) - 1) << OSD_REG_DRAW_Y_MAX_04_POS)) - -/* 0x40 : draw_partial_yuv_config5 */ -#define OSD_DRAW_PARTIAL_YUV_CONFIG5_OFFSET (0x40) -#define OSD_REG_DRAW_TH_05 OSD_REG_DRAW_TH_05 -#define OSD_REG_DRAW_TH_05_POS (0U) -#define OSD_REG_DRAW_TH_05_LEN (8U) -#define OSD_REG_DRAW_TH_05_MSK (((1U << OSD_REG_DRAW_TH_05_LEN) - 1) << OSD_REG_DRAW_TH_05_POS) -#define OSD_REG_DRAW_TH_05_UMSK (~(((1U << OSD_REG_DRAW_TH_05_LEN) - 1) << OSD_REG_DRAW_TH_05_POS)) -#define OSD_REG_DRAW_V_05 OSD_REG_DRAW_V_05 -#define OSD_REG_DRAW_V_05_POS (8U) -#define OSD_REG_DRAW_V_05_LEN (8U) -#define OSD_REG_DRAW_V_05_MSK (((1U << OSD_REG_DRAW_V_05_LEN) - 1) << OSD_REG_DRAW_V_05_POS) -#define OSD_REG_DRAW_V_05_UMSK (~(((1U << OSD_REG_DRAW_V_05_LEN) - 1) << OSD_REG_DRAW_V_05_POS)) -#define OSD_REG_DRAW_U_05 OSD_REG_DRAW_U_05 -#define OSD_REG_DRAW_U_05_POS (16U) -#define OSD_REG_DRAW_U_05_LEN (8U) -#define OSD_REG_DRAW_U_05_MSK (((1U << OSD_REG_DRAW_U_05_LEN) - 1) << OSD_REG_DRAW_U_05_POS) -#define OSD_REG_DRAW_U_05_UMSK (~(((1U << OSD_REG_DRAW_U_05_LEN) - 1) << OSD_REG_DRAW_U_05_POS)) -#define OSD_REG_DRAW_Y_05 OSD_REG_DRAW_Y_05 -#define OSD_REG_DRAW_Y_05_POS (24U) -#define OSD_REG_DRAW_Y_05_LEN (8U) -#define OSD_REG_DRAW_Y_05_MSK (((1U << OSD_REG_DRAW_Y_05_LEN) - 1) << OSD_REG_DRAW_Y_05_POS) -#define OSD_REG_DRAW_Y_05_UMSK (~(((1U << OSD_REG_DRAW_Y_05_LEN) - 1) << OSD_REG_DRAW_Y_05_POS)) - -/* 0x44 : draw_partial_x_config5 */ -#define OSD_DRAW_PARTIAL_X_CONFIG5_OFFSET (0x44) -#define OSD_REG_DRAW_X_MIN_05 OSD_REG_DRAW_X_MIN_05 -#define OSD_REG_DRAW_X_MIN_05_POS (0U) -#define OSD_REG_DRAW_X_MIN_05_LEN (11U) -#define OSD_REG_DRAW_X_MIN_05_MSK (((1U << OSD_REG_DRAW_X_MIN_05_LEN) - 1) << OSD_REG_DRAW_X_MIN_05_POS) -#define OSD_REG_DRAW_X_MIN_05_UMSK (~(((1U << OSD_REG_DRAW_X_MIN_05_LEN) - 1) << OSD_REG_DRAW_X_MIN_05_POS)) -#define OSD_REG_DRAW_X_MAX_05 OSD_REG_DRAW_X_MAX_05 -#define OSD_REG_DRAW_X_MAX_05_POS (16U) -#define OSD_REG_DRAW_X_MAX_05_LEN (11U) -#define OSD_REG_DRAW_X_MAX_05_MSK (((1U << OSD_REG_DRAW_X_MAX_05_LEN) - 1) << OSD_REG_DRAW_X_MAX_05_POS) -#define OSD_REG_DRAW_X_MAX_05_UMSK (~(((1U << OSD_REG_DRAW_X_MAX_05_LEN) - 1) << OSD_REG_DRAW_X_MAX_05_POS)) - -/* 0x48 : draw_partial_y_config5 */ -#define OSD_DRAW_PARTIAL_Y_CONFIG5_OFFSET (0x48) -#define OSD_REG_DRAW_Y_MIN_05 OSD_REG_DRAW_Y_MIN_05 -#define OSD_REG_DRAW_Y_MIN_05_POS (0U) -#define OSD_REG_DRAW_Y_MIN_05_LEN (11U) -#define OSD_REG_DRAW_Y_MIN_05_MSK (((1U << OSD_REG_DRAW_Y_MIN_05_LEN) - 1) << OSD_REG_DRAW_Y_MIN_05_POS) -#define OSD_REG_DRAW_Y_MIN_05_UMSK (~(((1U << OSD_REG_DRAW_Y_MIN_05_LEN) - 1) << OSD_REG_DRAW_Y_MIN_05_POS)) -#define OSD_REG_DRAW_Y_MAX_05 OSD_REG_DRAW_Y_MAX_05 -#define OSD_REG_DRAW_Y_MAX_05_POS (16U) -#define OSD_REG_DRAW_Y_MAX_05_LEN (11U) -#define OSD_REG_DRAW_Y_MAX_05_MSK (((1U << OSD_REG_DRAW_Y_MAX_05_LEN) - 1) << OSD_REG_DRAW_Y_MAX_05_POS) -#define OSD_REG_DRAW_Y_MAX_05_UMSK (~(((1U << OSD_REG_DRAW_Y_MAX_05_LEN) - 1) << OSD_REG_DRAW_Y_MAX_05_POS)) - -/* 0x4C : draw_partial_yuv_config6 */ -#define OSD_DRAW_PARTIAL_YUV_CONFIG6_OFFSET (0x4C) -#define OSD_REG_DRAW_TH_06 OSD_REG_DRAW_TH_06 -#define OSD_REG_DRAW_TH_06_POS (0U) -#define OSD_REG_DRAW_TH_06_LEN (8U) -#define OSD_REG_DRAW_TH_06_MSK (((1U << OSD_REG_DRAW_TH_06_LEN) - 1) << OSD_REG_DRAW_TH_06_POS) -#define OSD_REG_DRAW_TH_06_UMSK (~(((1U << OSD_REG_DRAW_TH_06_LEN) - 1) << OSD_REG_DRAW_TH_06_POS)) -#define OSD_REG_DRAW_V_06 OSD_REG_DRAW_V_06 -#define OSD_REG_DRAW_V_06_POS (8U) -#define OSD_REG_DRAW_V_06_LEN (8U) -#define OSD_REG_DRAW_V_06_MSK (((1U << OSD_REG_DRAW_V_06_LEN) - 1) << OSD_REG_DRAW_V_06_POS) -#define OSD_REG_DRAW_V_06_UMSK (~(((1U << OSD_REG_DRAW_V_06_LEN) - 1) << OSD_REG_DRAW_V_06_POS)) -#define OSD_REG_DRAW_U_06 OSD_REG_DRAW_U_06 -#define OSD_REG_DRAW_U_06_POS (16U) -#define OSD_REG_DRAW_U_06_LEN (8U) -#define OSD_REG_DRAW_U_06_MSK (((1U << OSD_REG_DRAW_U_06_LEN) - 1) << OSD_REG_DRAW_U_06_POS) -#define OSD_REG_DRAW_U_06_UMSK (~(((1U << OSD_REG_DRAW_U_06_LEN) - 1) << OSD_REG_DRAW_U_06_POS)) -#define OSD_REG_DRAW_Y_06 OSD_REG_DRAW_Y_06 -#define OSD_REG_DRAW_Y_06_POS (24U) -#define OSD_REG_DRAW_Y_06_LEN (8U) -#define OSD_REG_DRAW_Y_06_MSK (((1U << OSD_REG_DRAW_Y_06_LEN) - 1) << OSD_REG_DRAW_Y_06_POS) -#define OSD_REG_DRAW_Y_06_UMSK (~(((1U << OSD_REG_DRAW_Y_06_LEN) - 1) << OSD_REG_DRAW_Y_06_POS)) - -/* 0x50 : draw_partial_x_config6 */ -#define OSD_DRAW_PARTIAL_X_CONFIG6_OFFSET (0x50) -#define OSD_REG_DRAW_X_MIN_06 OSD_REG_DRAW_X_MIN_06 -#define OSD_REG_DRAW_X_MIN_06_POS (0U) -#define OSD_REG_DRAW_X_MIN_06_LEN (11U) -#define OSD_REG_DRAW_X_MIN_06_MSK (((1U << OSD_REG_DRAW_X_MIN_06_LEN) - 1) << OSD_REG_DRAW_X_MIN_06_POS) -#define OSD_REG_DRAW_X_MIN_06_UMSK (~(((1U << OSD_REG_DRAW_X_MIN_06_LEN) - 1) << OSD_REG_DRAW_X_MIN_06_POS)) -#define OSD_REG_DRAW_X_MAX_06 OSD_REG_DRAW_X_MAX_06 -#define OSD_REG_DRAW_X_MAX_06_POS (16U) -#define OSD_REG_DRAW_X_MAX_06_LEN (11U) -#define OSD_REG_DRAW_X_MAX_06_MSK (((1U << OSD_REG_DRAW_X_MAX_06_LEN) - 1) << OSD_REG_DRAW_X_MAX_06_POS) -#define OSD_REG_DRAW_X_MAX_06_UMSK (~(((1U << OSD_REG_DRAW_X_MAX_06_LEN) - 1) << OSD_REG_DRAW_X_MAX_06_POS)) - -/* 0x54 : draw_partial_y_config6 */ -#define OSD_DRAW_PARTIAL_Y_CONFIG6_OFFSET (0x54) -#define OSD_REG_DRAW_Y_MIN_06 OSD_REG_DRAW_Y_MIN_06 -#define OSD_REG_DRAW_Y_MIN_06_POS (0U) -#define OSD_REG_DRAW_Y_MIN_06_LEN (11U) -#define OSD_REG_DRAW_Y_MIN_06_MSK (((1U << OSD_REG_DRAW_Y_MIN_06_LEN) - 1) << OSD_REG_DRAW_Y_MIN_06_POS) -#define OSD_REG_DRAW_Y_MIN_06_UMSK (~(((1U << OSD_REG_DRAW_Y_MIN_06_LEN) - 1) << OSD_REG_DRAW_Y_MIN_06_POS)) -#define OSD_REG_DRAW_Y_MAX_06 OSD_REG_DRAW_Y_MAX_06 -#define OSD_REG_DRAW_Y_MAX_06_POS (16U) -#define OSD_REG_DRAW_Y_MAX_06_LEN (11U) -#define OSD_REG_DRAW_Y_MAX_06_MSK (((1U << OSD_REG_DRAW_Y_MAX_06_LEN) - 1) << OSD_REG_DRAW_Y_MAX_06_POS) -#define OSD_REG_DRAW_Y_MAX_06_UMSK (~(((1U << OSD_REG_DRAW_Y_MAX_06_LEN) - 1) << OSD_REG_DRAW_Y_MAX_06_POS)) - -/* 0x58 : draw_partial_yuv_config7 */ -#define OSD_DRAW_PARTIAL_YUV_CONFIG7_OFFSET (0x58) -#define OSD_REG_DRAW_TH_07 OSD_REG_DRAW_TH_07 -#define OSD_REG_DRAW_TH_07_POS (0U) -#define OSD_REG_DRAW_TH_07_LEN (8U) -#define OSD_REG_DRAW_TH_07_MSK (((1U << OSD_REG_DRAW_TH_07_LEN) - 1) << OSD_REG_DRAW_TH_07_POS) -#define OSD_REG_DRAW_TH_07_UMSK (~(((1U << OSD_REG_DRAW_TH_07_LEN) - 1) << OSD_REG_DRAW_TH_07_POS)) -#define OSD_REG_DRAW_V_07 OSD_REG_DRAW_V_07 -#define OSD_REG_DRAW_V_07_POS (8U) -#define OSD_REG_DRAW_V_07_LEN (8U) -#define OSD_REG_DRAW_V_07_MSK (((1U << OSD_REG_DRAW_V_07_LEN) - 1) << OSD_REG_DRAW_V_07_POS) -#define OSD_REG_DRAW_V_07_UMSK (~(((1U << OSD_REG_DRAW_V_07_LEN) - 1) << OSD_REG_DRAW_V_07_POS)) -#define OSD_REG_DRAW_U_07 OSD_REG_DRAW_U_07 -#define OSD_REG_DRAW_U_07_POS (16U) -#define OSD_REG_DRAW_U_07_LEN (8U) -#define OSD_REG_DRAW_U_07_MSK (((1U << OSD_REG_DRAW_U_07_LEN) - 1) << OSD_REG_DRAW_U_07_POS) -#define OSD_REG_DRAW_U_07_UMSK (~(((1U << OSD_REG_DRAW_U_07_LEN) - 1) << OSD_REG_DRAW_U_07_POS)) -#define OSD_REG_DRAW_Y_07 OSD_REG_DRAW_Y_07 -#define OSD_REG_DRAW_Y_07_POS (24U) -#define OSD_REG_DRAW_Y_07_LEN (8U) -#define OSD_REG_DRAW_Y_07_MSK (((1U << OSD_REG_DRAW_Y_07_LEN) - 1) << OSD_REG_DRAW_Y_07_POS) -#define OSD_REG_DRAW_Y_07_UMSK (~(((1U << OSD_REG_DRAW_Y_07_LEN) - 1) << OSD_REG_DRAW_Y_07_POS)) - -/* 0x5C : draw_partial_x_config7 */ -#define OSD_DRAW_PARTIAL_X_CONFIG7_OFFSET (0x5C) -#define OSD_REG_DRAW_X_MIN_07 OSD_REG_DRAW_X_MIN_07 -#define OSD_REG_DRAW_X_MIN_07_POS (0U) -#define OSD_REG_DRAW_X_MIN_07_LEN (11U) -#define OSD_REG_DRAW_X_MIN_07_MSK (((1U << OSD_REG_DRAW_X_MIN_07_LEN) - 1) << OSD_REG_DRAW_X_MIN_07_POS) -#define OSD_REG_DRAW_X_MIN_07_UMSK (~(((1U << OSD_REG_DRAW_X_MIN_07_LEN) - 1) << OSD_REG_DRAW_X_MIN_07_POS)) -#define OSD_REG_DRAW_X_MAX_07 OSD_REG_DRAW_X_MAX_07 -#define OSD_REG_DRAW_X_MAX_07_POS (16U) -#define OSD_REG_DRAW_X_MAX_07_LEN (11U) -#define OSD_REG_DRAW_X_MAX_07_MSK (((1U << OSD_REG_DRAW_X_MAX_07_LEN) - 1) << OSD_REG_DRAW_X_MAX_07_POS) -#define OSD_REG_DRAW_X_MAX_07_UMSK (~(((1U << OSD_REG_DRAW_X_MAX_07_LEN) - 1) << OSD_REG_DRAW_X_MAX_07_POS)) - -/* 0x60 : draw_partial_y_config7 */ -#define OSD_DRAW_PARTIAL_Y_CONFIG7_OFFSET (0x60) -#define OSD_REG_DRAW_Y_MIN_07 OSD_REG_DRAW_Y_MIN_07 -#define OSD_REG_DRAW_Y_MIN_07_POS (0U) -#define OSD_REG_DRAW_Y_MIN_07_LEN (11U) -#define OSD_REG_DRAW_Y_MIN_07_MSK (((1U << OSD_REG_DRAW_Y_MIN_07_LEN) - 1) << OSD_REG_DRAW_Y_MIN_07_POS) -#define OSD_REG_DRAW_Y_MIN_07_UMSK (~(((1U << OSD_REG_DRAW_Y_MIN_07_LEN) - 1) << OSD_REG_DRAW_Y_MIN_07_POS)) -#define OSD_REG_DRAW_Y_MAX_07 OSD_REG_DRAW_Y_MAX_07 -#define OSD_REG_DRAW_Y_MAX_07_POS (16U) -#define OSD_REG_DRAW_Y_MAX_07_LEN (11U) -#define OSD_REG_DRAW_Y_MAX_07_MSK (((1U << OSD_REG_DRAW_Y_MAX_07_LEN) - 1) << OSD_REG_DRAW_Y_MAX_07_POS) -#define OSD_REG_DRAW_Y_MAX_07_UMSK (~(((1U << OSD_REG_DRAW_Y_MAX_07_LEN) - 1) << OSD_REG_DRAW_Y_MAX_07_POS)) - -/* 0x64 : draw_partial_yuv_config8 */ -#define OSD_DRAW_PARTIAL_YUV_CONFIG8_OFFSET (0x64) -#define OSD_REG_DRAW_TH_08 OSD_REG_DRAW_TH_08 -#define OSD_REG_DRAW_TH_08_POS (0U) -#define OSD_REG_DRAW_TH_08_LEN (8U) -#define OSD_REG_DRAW_TH_08_MSK (((1U << OSD_REG_DRAW_TH_08_LEN) - 1) << OSD_REG_DRAW_TH_08_POS) -#define OSD_REG_DRAW_TH_08_UMSK (~(((1U << OSD_REG_DRAW_TH_08_LEN) - 1) << OSD_REG_DRAW_TH_08_POS)) -#define OSD_REG_DRAW_V_08 OSD_REG_DRAW_V_08 -#define OSD_REG_DRAW_V_08_POS (8U) -#define OSD_REG_DRAW_V_08_LEN (8U) -#define OSD_REG_DRAW_V_08_MSK (((1U << OSD_REG_DRAW_V_08_LEN) - 1) << OSD_REG_DRAW_V_08_POS) -#define OSD_REG_DRAW_V_08_UMSK (~(((1U << OSD_REG_DRAW_V_08_LEN) - 1) << OSD_REG_DRAW_V_08_POS)) -#define OSD_REG_DRAW_U_08 OSD_REG_DRAW_U_08 -#define OSD_REG_DRAW_U_08_POS (16U) -#define OSD_REG_DRAW_U_08_LEN (8U) -#define OSD_REG_DRAW_U_08_MSK (((1U << OSD_REG_DRAW_U_08_LEN) - 1) << OSD_REG_DRAW_U_08_POS) -#define OSD_REG_DRAW_U_08_UMSK (~(((1U << OSD_REG_DRAW_U_08_LEN) - 1) << OSD_REG_DRAW_U_08_POS)) -#define OSD_REG_DRAW_Y_08 OSD_REG_DRAW_Y_08 -#define OSD_REG_DRAW_Y_08_POS (24U) -#define OSD_REG_DRAW_Y_08_LEN (8U) -#define OSD_REG_DRAW_Y_08_MSK (((1U << OSD_REG_DRAW_Y_08_LEN) - 1) << OSD_REG_DRAW_Y_08_POS) -#define OSD_REG_DRAW_Y_08_UMSK (~(((1U << OSD_REG_DRAW_Y_08_LEN) - 1) << OSD_REG_DRAW_Y_08_POS)) - -/* 0x68 : draw_partial_x_config8 */ -#define OSD_DRAW_PARTIAL_X_CONFIG8_OFFSET (0x68) -#define OSD_REG_DRAW_X_MIN_08 OSD_REG_DRAW_X_MIN_08 -#define OSD_REG_DRAW_X_MIN_08_POS (0U) -#define OSD_REG_DRAW_X_MIN_08_LEN (11U) -#define OSD_REG_DRAW_X_MIN_08_MSK (((1U << OSD_REG_DRAW_X_MIN_08_LEN) - 1) << OSD_REG_DRAW_X_MIN_08_POS) -#define OSD_REG_DRAW_X_MIN_08_UMSK (~(((1U << OSD_REG_DRAW_X_MIN_08_LEN) - 1) << OSD_REG_DRAW_X_MIN_08_POS)) -#define OSD_REG_DRAW_X_MAX_08 OSD_REG_DRAW_X_MAX_08 -#define OSD_REG_DRAW_X_MAX_08_POS (16U) -#define OSD_REG_DRAW_X_MAX_08_LEN (11U) -#define OSD_REG_DRAW_X_MAX_08_MSK (((1U << OSD_REG_DRAW_X_MAX_08_LEN) - 1) << OSD_REG_DRAW_X_MAX_08_POS) -#define OSD_REG_DRAW_X_MAX_08_UMSK (~(((1U << OSD_REG_DRAW_X_MAX_08_LEN) - 1) << OSD_REG_DRAW_X_MAX_08_POS)) - -/* 0x6C : draw_partial_y_config8 */ -#define OSD_DRAW_PARTIAL_Y_CONFIG8_OFFSET (0x6C) -#define OSD_REG_DRAW_Y_MIN_08 OSD_REG_DRAW_Y_MIN_08 -#define OSD_REG_DRAW_Y_MIN_08_POS (0U) -#define OSD_REG_DRAW_Y_MIN_08_LEN (11U) -#define OSD_REG_DRAW_Y_MIN_08_MSK (((1U << OSD_REG_DRAW_Y_MIN_08_LEN) - 1) << OSD_REG_DRAW_Y_MIN_08_POS) -#define OSD_REG_DRAW_Y_MIN_08_UMSK (~(((1U << OSD_REG_DRAW_Y_MIN_08_LEN) - 1) << OSD_REG_DRAW_Y_MIN_08_POS)) -#define OSD_REG_DRAW_Y_MAX_08 OSD_REG_DRAW_Y_MAX_08 -#define OSD_REG_DRAW_Y_MAX_08_POS (16U) -#define OSD_REG_DRAW_Y_MAX_08_LEN (11U) -#define OSD_REG_DRAW_Y_MAX_08_MSK (((1U << OSD_REG_DRAW_Y_MAX_08_LEN) - 1) << OSD_REG_DRAW_Y_MAX_08_POS) -#define OSD_REG_DRAW_Y_MAX_08_UMSK (~(((1U << OSD_REG_DRAW_Y_MAX_08_LEN) - 1) << OSD_REG_DRAW_Y_MAX_08_POS)) - -/* 0x70 : draw_partial_yuv_config9 */ -#define OSD_DRAW_PARTIAL_YUV_CONFIG9_OFFSET (0x70) -#define OSD_REG_DRAW_TH_09 OSD_REG_DRAW_TH_09 -#define OSD_REG_DRAW_TH_09_POS (0U) -#define OSD_REG_DRAW_TH_09_LEN (8U) -#define OSD_REG_DRAW_TH_09_MSK (((1U << OSD_REG_DRAW_TH_09_LEN) - 1) << OSD_REG_DRAW_TH_09_POS) -#define OSD_REG_DRAW_TH_09_UMSK (~(((1U << OSD_REG_DRAW_TH_09_LEN) - 1) << OSD_REG_DRAW_TH_09_POS)) -#define OSD_REG_DRAW_V_09 OSD_REG_DRAW_V_09 -#define OSD_REG_DRAW_V_09_POS (8U) -#define OSD_REG_DRAW_V_09_LEN (8U) -#define OSD_REG_DRAW_V_09_MSK (((1U << OSD_REG_DRAW_V_09_LEN) - 1) << OSD_REG_DRAW_V_09_POS) -#define OSD_REG_DRAW_V_09_UMSK (~(((1U << OSD_REG_DRAW_V_09_LEN) - 1) << OSD_REG_DRAW_V_09_POS)) -#define OSD_REG_DRAW_U_09 OSD_REG_DRAW_U_09 -#define OSD_REG_DRAW_U_09_POS (16U) -#define OSD_REG_DRAW_U_09_LEN (8U) -#define OSD_REG_DRAW_U_09_MSK (((1U << OSD_REG_DRAW_U_09_LEN) - 1) << OSD_REG_DRAW_U_09_POS) -#define OSD_REG_DRAW_U_09_UMSK (~(((1U << OSD_REG_DRAW_U_09_LEN) - 1) << OSD_REG_DRAW_U_09_POS)) -#define OSD_REG_DRAW_Y_09 OSD_REG_DRAW_Y_09 -#define OSD_REG_DRAW_Y_09_POS (24U) -#define OSD_REG_DRAW_Y_09_LEN (8U) -#define OSD_REG_DRAW_Y_09_MSK (((1U << OSD_REG_DRAW_Y_09_LEN) - 1) << OSD_REG_DRAW_Y_09_POS) -#define OSD_REG_DRAW_Y_09_UMSK (~(((1U << OSD_REG_DRAW_Y_09_LEN) - 1) << OSD_REG_DRAW_Y_09_POS)) - -/* 0x74 : draw_partial_x_config9 */ -#define OSD_DRAW_PARTIAL_X_CONFIG9_OFFSET (0x74) -#define OSD_REG_DRAW_X_MIN_09 OSD_REG_DRAW_X_MIN_09 -#define OSD_REG_DRAW_X_MIN_09_POS (0U) -#define OSD_REG_DRAW_X_MIN_09_LEN (11U) -#define OSD_REG_DRAW_X_MIN_09_MSK (((1U << OSD_REG_DRAW_X_MIN_09_LEN) - 1) << OSD_REG_DRAW_X_MIN_09_POS) -#define OSD_REG_DRAW_X_MIN_09_UMSK (~(((1U << OSD_REG_DRAW_X_MIN_09_LEN) - 1) << OSD_REG_DRAW_X_MIN_09_POS)) -#define OSD_REG_DRAW_X_MAX_09 OSD_REG_DRAW_X_MAX_09 -#define OSD_REG_DRAW_X_MAX_09_POS (16U) -#define OSD_REG_DRAW_X_MAX_09_LEN (11U) -#define OSD_REG_DRAW_X_MAX_09_MSK (((1U << OSD_REG_DRAW_X_MAX_09_LEN) - 1) << OSD_REG_DRAW_X_MAX_09_POS) -#define OSD_REG_DRAW_X_MAX_09_UMSK (~(((1U << OSD_REG_DRAW_X_MAX_09_LEN) - 1) << OSD_REG_DRAW_X_MAX_09_POS)) - -/* 0x78 : draw_partial_y_config9 */ -#define OSD_DRAW_PARTIAL_Y_CONFIG9_OFFSET (0x78) -#define OSD_REG_DRAW_Y_MIN_09 OSD_REG_DRAW_Y_MIN_09 -#define OSD_REG_DRAW_Y_MIN_09_POS (0U) -#define OSD_REG_DRAW_Y_MIN_09_LEN (11U) -#define OSD_REG_DRAW_Y_MIN_09_MSK (((1U << OSD_REG_DRAW_Y_MIN_09_LEN) - 1) << OSD_REG_DRAW_Y_MIN_09_POS) -#define OSD_REG_DRAW_Y_MIN_09_UMSK (~(((1U << OSD_REG_DRAW_Y_MIN_09_LEN) - 1) << OSD_REG_DRAW_Y_MIN_09_POS)) -#define OSD_REG_DRAW_Y_MAX_09 OSD_REG_DRAW_Y_MAX_09 -#define OSD_REG_DRAW_Y_MAX_09_POS (16U) -#define OSD_REG_DRAW_Y_MAX_09_LEN (11U) -#define OSD_REG_DRAW_Y_MAX_09_MSK (((1U << OSD_REG_DRAW_Y_MAX_09_LEN) - 1) << OSD_REG_DRAW_Y_MAX_09_POS) -#define OSD_REG_DRAW_Y_MAX_09_UMSK (~(((1U << OSD_REG_DRAW_Y_MAX_09_LEN) - 1) << OSD_REG_DRAW_Y_MAX_09_POS)) - -/* 0x7C : draw_partial_yuv_configa */ -#define OSD_DRAW_PARTIAL_YUV_CONFIGA_OFFSET (0x7C) -#define OSD_REG_DRAW_TH_0A OSD_REG_DRAW_TH_0A -#define OSD_REG_DRAW_TH_0A_POS (0U) -#define OSD_REG_DRAW_TH_0A_LEN (8U) -#define OSD_REG_DRAW_TH_0A_MSK (((1U << OSD_REG_DRAW_TH_0A_LEN) - 1) << OSD_REG_DRAW_TH_0A_POS) -#define OSD_REG_DRAW_TH_0A_UMSK (~(((1U << OSD_REG_DRAW_TH_0A_LEN) - 1) << OSD_REG_DRAW_TH_0A_POS)) -#define OSD_REG_DRAW_V_0A OSD_REG_DRAW_V_0A -#define OSD_REG_DRAW_V_0A_POS (8U) -#define OSD_REG_DRAW_V_0A_LEN (8U) -#define OSD_REG_DRAW_V_0A_MSK (((1U << OSD_REG_DRAW_V_0A_LEN) - 1) << OSD_REG_DRAW_V_0A_POS) -#define OSD_REG_DRAW_V_0A_UMSK (~(((1U << OSD_REG_DRAW_V_0A_LEN) - 1) << OSD_REG_DRAW_V_0A_POS)) -#define OSD_REG_DRAW_U_0A OSD_REG_DRAW_U_0A -#define OSD_REG_DRAW_U_0A_POS (16U) -#define OSD_REG_DRAW_U_0A_LEN (8U) -#define OSD_REG_DRAW_U_0A_MSK (((1U << OSD_REG_DRAW_U_0A_LEN) - 1) << OSD_REG_DRAW_U_0A_POS) -#define OSD_REG_DRAW_U_0A_UMSK (~(((1U << OSD_REG_DRAW_U_0A_LEN) - 1) << OSD_REG_DRAW_U_0A_POS)) -#define OSD_REG_DRAW_Y_0A OSD_REG_DRAW_Y_0A -#define OSD_REG_DRAW_Y_0A_POS (24U) -#define OSD_REG_DRAW_Y_0A_LEN (8U) -#define OSD_REG_DRAW_Y_0A_MSK (((1U << OSD_REG_DRAW_Y_0A_LEN) - 1) << OSD_REG_DRAW_Y_0A_POS) -#define OSD_REG_DRAW_Y_0A_UMSK (~(((1U << OSD_REG_DRAW_Y_0A_LEN) - 1) << OSD_REG_DRAW_Y_0A_POS)) - -/* 0x80 : draw_partial_x_configa */ -#define OSD_DRAW_PARTIAL_X_CONFIGA_OFFSET (0x80) -#define OSD_REG_DRAW_X_MIN_0A OSD_REG_DRAW_X_MIN_0A -#define OSD_REG_DRAW_X_MIN_0A_POS (0U) -#define OSD_REG_DRAW_X_MIN_0A_LEN (11U) -#define OSD_REG_DRAW_X_MIN_0A_MSK (((1U << OSD_REG_DRAW_X_MIN_0A_LEN) - 1) << OSD_REG_DRAW_X_MIN_0A_POS) -#define OSD_REG_DRAW_X_MIN_0A_UMSK (~(((1U << OSD_REG_DRAW_X_MIN_0A_LEN) - 1) << OSD_REG_DRAW_X_MIN_0A_POS)) -#define OSD_REG_DRAW_X_MAX_0A OSD_REG_DRAW_X_MAX_0A -#define OSD_REG_DRAW_X_MAX_0A_POS (16U) -#define OSD_REG_DRAW_X_MAX_0A_LEN (11U) -#define OSD_REG_DRAW_X_MAX_0A_MSK (((1U << OSD_REG_DRAW_X_MAX_0A_LEN) - 1) << OSD_REG_DRAW_X_MAX_0A_POS) -#define OSD_REG_DRAW_X_MAX_0A_UMSK (~(((1U << OSD_REG_DRAW_X_MAX_0A_LEN) - 1) << OSD_REG_DRAW_X_MAX_0A_POS)) - -/* 0x84 : draw_partial_y_configa */ -#define OSD_DRAW_PARTIAL_Y_CONFIGA_OFFSET (0x84) -#define OSD_REG_DRAW_Y_MIN_0A OSD_REG_DRAW_Y_MIN_0A -#define OSD_REG_DRAW_Y_MIN_0A_POS (0U) -#define OSD_REG_DRAW_Y_MIN_0A_LEN (11U) -#define OSD_REG_DRAW_Y_MIN_0A_MSK (((1U << OSD_REG_DRAW_Y_MIN_0A_LEN) - 1) << OSD_REG_DRAW_Y_MIN_0A_POS) -#define OSD_REG_DRAW_Y_MIN_0A_UMSK (~(((1U << OSD_REG_DRAW_Y_MIN_0A_LEN) - 1) << OSD_REG_DRAW_Y_MIN_0A_POS)) -#define OSD_REG_DRAW_Y_MAX_0A OSD_REG_DRAW_Y_MAX_0A -#define OSD_REG_DRAW_Y_MAX_0A_POS (16U) -#define OSD_REG_DRAW_Y_MAX_0A_LEN (11U) -#define OSD_REG_DRAW_Y_MAX_0A_MSK (((1U << OSD_REG_DRAW_Y_MAX_0A_LEN) - 1) << OSD_REG_DRAW_Y_MAX_0A_POS) -#define OSD_REG_DRAW_Y_MAX_0A_UMSK (~(((1U << OSD_REG_DRAW_Y_MAX_0A_LEN) - 1) << OSD_REG_DRAW_Y_MAX_0A_POS)) - -/* 0x88 : draw_partial_yuv_configb */ -#define OSD_DRAW_PARTIAL_YUV_CONFIGB_OFFSET (0x88) -#define OSD_REG_DRAW_TH_0B OSD_REG_DRAW_TH_0B -#define OSD_REG_DRAW_TH_0B_POS (0U) -#define OSD_REG_DRAW_TH_0B_LEN (8U) -#define OSD_REG_DRAW_TH_0B_MSK (((1U << OSD_REG_DRAW_TH_0B_LEN) - 1) << OSD_REG_DRAW_TH_0B_POS) -#define OSD_REG_DRAW_TH_0B_UMSK (~(((1U << OSD_REG_DRAW_TH_0B_LEN) - 1) << OSD_REG_DRAW_TH_0B_POS)) -#define OSD_REG_DRAW_V_0B OSD_REG_DRAW_V_0B -#define OSD_REG_DRAW_V_0B_POS (8U) -#define OSD_REG_DRAW_V_0B_LEN (8U) -#define OSD_REG_DRAW_V_0B_MSK (((1U << OSD_REG_DRAW_V_0B_LEN) - 1) << OSD_REG_DRAW_V_0B_POS) -#define OSD_REG_DRAW_V_0B_UMSK (~(((1U << OSD_REG_DRAW_V_0B_LEN) - 1) << OSD_REG_DRAW_V_0B_POS)) -#define OSD_REG_DRAW_U_0B OSD_REG_DRAW_U_0B -#define OSD_REG_DRAW_U_0B_POS (16U) -#define OSD_REG_DRAW_U_0B_LEN (8U) -#define OSD_REG_DRAW_U_0B_MSK (((1U << OSD_REG_DRAW_U_0B_LEN) - 1) << OSD_REG_DRAW_U_0B_POS) -#define OSD_REG_DRAW_U_0B_UMSK (~(((1U << OSD_REG_DRAW_U_0B_LEN) - 1) << OSD_REG_DRAW_U_0B_POS)) -#define OSD_REG_DRAW_Y_0B OSD_REG_DRAW_Y_0B -#define OSD_REG_DRAW_Y_0B_POS (24U) -#define OSD_REG_DRAW_Y_0B_LEN (8U) -#define OSD_REG_DRAW_Y_0B_MSK (((1U << OSD_REG_DRAW_Y_0B_LEN) - 1) << OSD_REG_DRAW_Y_0B_POS) -#define OSD_REG_DRAW_Y_0B_UMSK (~(((1U << OSD_REG_DRAW_Y_0B_LEN) - 1) << OSD_REG_DRAW_Y_0B_POS)) - -/* 0x8C : draw_partial_x_configb */ -#define OSD_DRAW_PARTIAL_X_CONFIGB_OFFSET (0x8C) -#define OSD_REG_DRAW_X_MIN_0B OSD_REG_DRAW_X_MIN_0B -#define OSD_REG_DRAW_X_MIN_0B_POS (0U) -#define OSD_REG_DRAW_X_MIN_0B_LEN (11U) -#define OSD_REG_DRAW_X_MIN_0B_MSK (((1U << OSD_REG_DRAW_X_MIN_0B_LEN) - 1) << OSD_REG_DRAW_X_MIN_0B_POS) -#define OSD_REG_DRAW_X_MIN_0B_UMSK (~(((1U << OSD_REG_DRAW_X_MIN_0B_LEN) - 1) << OSD_REG_DRAW_X_MIN_0B_POS)) -#define OSD_REG_DRAW_X_MAX_0B OSD_REG_DRAW_X_MAX_0B -#define OSD_REG_DRAW_X_MAX_0B_POS (16U) -#define OSD_REG_DRAW_X_MAX_0B_LEN (11U) -#define OSD_REG_DRAW_X_MAX_0B_MSK (((1U << OSD_REG_DRAW_X_MAX_0B_LEN) - 1) << OSD_REG_DRAW_X_MAX_0B_POS) -#define OSD_REG_DRAW_X_MAX_0B_UMSK (~(((1U << OSD_REG_DRAW_X_MAX_0B_LEN) - 1) << OSD_REG_DRAW_X_MAX_0B_POS)) - -/* 0x90 : draw_partial_y_configb */ -#define OSD_DRAW_PARTIAL_Y_CONFIGB_OFFSET (0x90) -#define OSD_REG_DRAW_Y_MIN_0B OSD_REG_DRAW_Y_MIN_0B -#define OSD_REG_DRAW_Y_MIN_0B_POS (0U) -#define OSD_REG_DRAW_Y_MIN_0B_LEN (11U) -#define OSD_REG_DRAW_Y_MIN_0B_MSK (((1U << OSD_REG_DRAW_Y_MIN_0B_LEN) - 1) << OSD_REG_DRAW_Y_MIN_0B_POS) -#define OSD_REG_DRAW_Y_MIN_0B_UMSK (~(((1U << OSD_REG_DRAW_Y_MIN_0B_LEN) - 1) << OSD_REG_DRAW_Y_MIN_0B_POS)) -#define OSD_REG_DRAW_Y_MAX_0B OSD_REG_DRAW_Y_MAX_0B -#define OSD_REG_DRAW_Y_MAX_0B_POS (16U) -#define OSD_REG_DRAW_Y_MAX_0B_LEN (11U) -#define OSD_REG_DRAW_Y_MAX_0B_MSK (((1U << OSD_REG_DRAW_Y_MAX_0B_LEN) - 1) << OSD_REG_DRAW_Y_MAX_0B_POS) -#define OSD_REG_DRAW_Y_MAX_0B_UMSK (~(((1U << OSD_REG_DRAW_Y_MAX_0B_LEN) - 1) << OSD_REG_DRAW_Y_MAX_0B_POS)) - -/* 0x94 : draw_partial_yuv_configc */ -#define OSD_DRAW_PARTIAL_YUV_CONFIGC_OFFSET (0x94) -#define OSD_REG_DRAW_TH_0C OSD_REG_DRAW_TH_0C -#define OSD_REG_DRAW_TH_0C_POS (0U) -#define OSD_REG_DRAW_TH_0C_LEN (8U) -#define OSD_REG_DRAW_TH_0C_MSK (((1U << OSD_REG_DRAW_TH_0C_LEN) - 1) << OSD_REG_DRAW_TH_0C_POS) -#define OSD_REG_DRAW_TH_0C_UMSK (~(((1U << OSD_REG_DRAW_TH_0C_LEN) - 1) << OSD_REG_DRAW_TH_0C_POS)) -#define OSD_REG_DRAW_V_0C OSD_REG_DRAW_V_0C -#define OSD_REG_DRAW_V_0C_POS (8U) -#define OSD_REG_DRAW_V_0C_LEN (8U) -#define OSD_REG_DRAW_V_0C_MSK (((1U << OSD_REG_DRAW_V_0C_LEN) - 1) << OSD_REG_DRAW_V_0C_POS) -#define OSD_REG_DRAW_V_0C_UMSK (~(((1U << OSD_REG_DRAW_V_0C_LEN) - 1) << OSD_REG_DRAW_V_0C_POS)) -#define OSD_REG_DRAW_U_0C OSD_REG_DRAW_U_0C -#define OSD_REG_DRAW_U_0C_POS (16U) -#define OSD_REG_DRAW_U_0C_LEN (8U) -#define OSD_REG_DRAW_U_0C_MSK (((1U << OSD_REG_DRAW_U_0C_LEN) - 1) << OSD_REG_DRAW_U_0C_POS) -#define OSD_REG_DRAW_U_0C_UMSK (~(((1U << OSD_REG_DRAW_U_0C_LEN) - 1) << OSD_REG_DRAW_U_0C_POS)) -#define OSD_REG_DRAW_Y_0C OSD_REG_DRAW_Y_0C -#define OSD_REG_DRAW_Y_0C_POS (24U) -#define OSD_REG_DRAW_Y_0C_LEN (8U) -#define OSD_REG_DRAW_Y_0C_MSK (((1U << OSD_REG_DRAW_Y_0C_LEN) - 1) << OSD_REG_DRAW_Y_0C_POS) -#define OSD_REG_DRAW_Y_0C_UMSK (~(((1U << OSD_REG_DRAW_Y_0C_LEN) - 1) << OSD_REG_DRAW_Y_0C_POS)) - -/* 0x98 : draw_partial_x_configc */ -#define OSD_DRAW_PARTIAL_X_CONFIGC_OFFSET (0x98) -#define OSD_REG_DRAW_X_MIN_0C OSD_REG_DRAW_X_MIN_0C -#define OSD_REG_DRAW_X_MIN_0C_POS (0U) -#define OSD_REG_DRAW_X_MIN_0C_LEN (11U) -#define OSD_REG_DRAW_X_MIN_0C_MSK (((1U << OSD_REG_DRAW_X_MIN_0C_LEN) - 1) << OSD_REG_DRAW_X_MIN_0C_POS) -#define OSD_REG_DRAW_X_MIN_0C_UMSK (~(((1U << OSD_REG_DRAW_X_MIN_0C_LEN) - 1) << OSD_REG_DRAW_X_MIN_0C_POS)) -#define OSD_REG_DRAW_X_MAX_0C OSD_REG_DRAW_X_MAX_0C -#define OSD_REG_DRAW_X_MAX_0C_POS (16U) -#define OSD_REG_DRAW_X_MAX_0C_LEN (11U) -#define OSD_REG_DRAW_X_MAX_0C_MSK (((1U << OSD_REG_DRAW_X_MAX_0C_LEN) - 1) << OSD_REG_DRAW_X_MAX_0C_POS) -#define OSD_REG_DRAW_X_MAX_0C_UMSK (~(((1U << OSD_REG_DRAW_X_MAX_0C_LEN) - 1) << OSD_REG_DRAW_X_MAX_0C_POS)) - -/* 0x9C : draw_partial_y_configc */ -#define OSD_DRAW_PARTIAL_Y_CONFIGC_OFFSET (0x9C) -#define OSD_REG_DRAW_Y_MIN_0C OSD_REG_DRAW_Y_MIN_0C -#define OSD_REG_DRAW_Y_MIN_0C_POS (0U) -#define OSD_REG_DRAW_Y_MIN_0C_LEN (11U) -#define OSD_REG_DRAW_Y_MIN_0C_MSK (((1U << OSD_REG_DRAW_Y_MIN_0C_LEN) - 1) << OSD_REG_DRAW_Y_MIN_0C_POS) -#define OSD_REG_DRAW_Y_MIN_0C_UMSK (~(((1U << OSD_REG_DRAW_Y_MIN_0C_LEN) - 1) << OSD_REG_DRAW_Y_MIN_0C_POS)) -#define OSD_REG_DRAW_Y_MAX_0C OSD_REG_DRAW_Y_MAX_0C -#define OSD_REG_DRAW_Y_MAX_0C_POS (16U) -#define OSD_REG_DRAW_Y_MAX_0C_LEN (11U) -#define OSD_REG_DRAW_Y_MAX_0C_MSK (((1U << OSD_REG_DRAW_Y_MAX_0C_LEN) - 1) << OSD_REG_DRAW_Y_MAX_0C_POS) -#define OSD_REG_DRAW_Y_MAX_0C_UMSK (~(((1U << OSD_REG_DRAW_Y_MAX_0C_LEN) - 1) << OSD_REG_DRAW_Y_MAX_0C_POS)) - -/* 0xA0 : draw_partial_yuv_configd */ -#define OSD_DRAW_PARTIAL_YUV_CONFIGD_OFFSET (0xA0) -#define OSD_REG_DRAW_TH_0D OSD_REG_DRAW_TH_0D -#define OSD_REG_DRAW_TH_0D_POS (0U) -#define OSD_REG_DRAW_TH_0D_LEN (8U) -#define OSD_REG_DRAW_TH_0D_MSK (((1U << OSD_REG_DRAW_TH_0D_LEN) - 1) << OSD_REG_DRAW_TH_0D_POS) -#define OSD_REG_DRAW_TH_0D_UMSK (~(((1U << OSD_REG_DRAW_TH_0D_LEN) - 1) << OSD_REG_DRAW_TH_0D_POS)) -#define OSD_REG_DRAW_V_0D OSD_REG_DRAW_V_0D -#define OSD_REG_DRAW_V_0D_POS (8U) -#define OSD_REG_DRAW_V_0D_LEN (8U) -#define OSD_REG_DRAW_V_0D_MSK (((1U << OSD_REG_DRAW_V_0D_LEN) - 1) << OSD_REG_DRAW_V_0D_POS) -#define OSD_REG_DRAW_V_0D_UMSK (~(((1U << OSD_REG_DRAW_V_0D_LEN) - 1) << OSD_REG_DRAW_V_0D_POS)) -#define OSD_REG_DRAW_U_0D OSD_REG_DRAW_U_0D -#define OSD_REG_DRAW_U_0D_POS (16U) -#define OSD_REG_DRAW_U_0D_LEN (8U) -#define OSD_REG_DRAW_U_0D_MSK (((1U << OSD_REG_DRAW_U_0D_LEN) - 1) << OSD_REG_DRAW_U_0D_POS) -#define OSD_REG_DRAW_U_0D_UMSK (~(((1U << OSD_REG_DRAW_U_0D_LEN) - 1) << OSD_REG_DRAW_U_0D_POS)) -#define OSD_REG_DRAW_Y_0D OSD_REG_DRAW_Y_0D -#define OSD_REG_DRAW_Y_0D_POS (24U) -#define OSD_REG_DRAW_Y_0D_LEN (8U) -#define OSD_REG_DRAW_Y_0D_MSK (((1U << OSD_REG_DRAW_Y_0D_LEN) - 1) << OSD_REG_DRAW_Y_0D_POS) -#define OSD_REG_DRAW_Y_0D_UMSK (~(((1U << OSD_REG_DRAW_Y_0D_LEN) - 1) << OSD_REG_DRAW_Y_0D_POS)) - -/* 0xA4 : draw_partial_x_configd */ -#define OSD_DRAW_PARTIAL_X_CONFIGD_OFFSET (0xA4) -#define OSD_REG_DRAW_X_MIN_0D OSD_REG_DRAW_X_MIN_0D -#define OSD_REG_DRAW_X_MIN_0D_POS (0U) -#define OSD_REG_DRAW_X_MIN_0D_LEN (11U) -#define OSD_REG_DRAW_X_MIN_0D_MSK (((1U << OSD_REG_DRAW_X_MIN_0D_LEN) - 1) << OSD_REG_DRAW_X_MIN_0D_POS) -#define OSD_REG_DRAW_X_MIN_0D_UMSK (~(((1U << OSD_REG_DRAW_X_MIN_0D_LEN) - 1) << OSD_REG_DRAW_X_MIN_0D_POS)) -#define OSD_REG_DRAW_X_MAX_0D OSD_REG_DRAW_X_MAX_0D -#define OSD_REG_DRAW_X_MAX_0D_POS (16U) -#define OSD_REG_DRAW_X_MAX_0D_LEN (11U) -#define OSD_REG_DRAW_X_MAX_0D_MSK (((1U << OSD_REG_DRAW_X_MAX_0D_LEN) - 1) << OSD_REG_DRAW_X_MAX_0D_POS) -#define OSD_REG_DRAW_X_MAX_0D_UMSK (~(((1U << OSD_REG_DRAW_X_MAX_0D_LEN) - 1) << OSD_REG_DRAW_X_MAX_0D_POS)) - -/* 0xA8 : draw_partial_y_configd */ -#define OSD_DRAW_PARTIAL_Y_CONFIGD_OFFSET (0xA8) -#define OSD_REG_DRAW_Y_MIN_0D OSD_REG_DRAW_Y_MIN_0D -#define OSD_REG_DRAW_Y_MIN_0D_POS (0U) -#define OSD_REG_DRAW_Y_MIN_0D_LEN (11U) -#define OSD_REG_DRAW_Y_MIN_0D_MSK (((1U << OSD_REG_DRAW_Y_MIN_0D_LEN) - 1) << OSD_REG_DRAW_Y_MIN_0D_POS) -#define OSD_REG_DRAW_Y_MIN_0D_UMSK (~(((1U << OSD_REG_DRAW_Y_MIN_0D_LEN) - 1) << OSD_REG_DRAW_Y_MIN_0D_POS)) -#define OSD_REG_DRAW_Y_MAX_0D OSD_REG_DRAW_Y_MAX_0D -#define OSD_REG_DRAW_Y_MAX_0D_POS (16U) -#define OSD_REG_DRAW_Y_MAX_0D_LEN (11U) -#define OSD_REG_DRAW_Y_MAX_0D_MSK (((1U << OSD_REG_DRAW_Y_MAX_0D_LEN) - 1) << OSD_REG_DRAW_Y_MAX_0D_POS) -#define OSD_REG_DRAW_Y_MAX_0D_UMSK (~(((1U << OSD_REG_DRAW_Y_MAX_0D_LEN) - 1) << OSD_REG_DRAW_Y_MAX_0D_POS)) - -/* 0xAC : draw_partial_yuv_confige */ -#define OSD_DRAW_PARTIAL_YUV_CONFIGE_OFFSET (0xAC) -#define OSD_REG_DRAW_TH_0E OSD_REG_DRAW_TH_0E -#define OSD_REG_DRAW_TH_0E_POS (0U) -#define OSD_REG_DRAW_TH_0E_LEN (8U) -#define OSD_REG_DRAW_TH_0E_MSK (((1U << OSD_REG_DRAW_TH_0E_LEN) - 1) << OSD_REG_DRAW_TH_0E_POS) -#define OSD_REG_DRAW_TH_0E_UMSK (~(((1U << OSD_REG_DRAW_TH_0E_LEN) - 1) << OSD_REG_DRAW_TH_0E_POS)) -#define OSD_REG_DRAW_V_0E OSD_REG_DRAW_V_0E -#define OSD_REG_DRAW_V_0E_POS (8U) -#define OSD_REG_DRAW_V_0E_LEN (8U) -#define OSD_REG_DRAW_V_0E_MSK (((1U << OSD_REG_DRAW_V_0E_LEN) - 1) << OSD_REG_DRAW_V_0E_POS) -#define OSD_REG_DRAW_V_0E_UMSK (~(((1U << OSD_REG_DRAW_V_0E_LEN) - 1) << OSD_REG_DRAW_V_0E_POS)) -#define OSD_REG_DRAW_U_0E OSD_REG_DRAW_U_0E -#define OSD_REG_DRAW_U_0E_POS (16U) -#define OSD_REG_DRAW_U_0E_LEN (8U) -#define OSD_REG_DRAW_U_0E_MSK (((1U << OSD_REG_DRAW_U_0E_LEN) - 1) << OSD_REG_DRAW_U_0E_POS) -#define OSD_REG_DRAW_U_0E_UMSK (~(((1U << OSD_REG_DRAW_U_0E_LEN) - 1) << OSD_REG_DRAW_U_0E_POS)) -#define OSD_REG_DRAW_Y_0E OSD_REG_DRAW_Y_0E -#define OSD_REG_DRAW_Y_0E_POS (24U) -#define OSD_REG_DRAW_Y_0E_LEN (8U) -#define OSD_REG_DRAW_Y_0E_MSK (((1U << OSD_REG_DRAW_Y_0E_LEN) - 1) << OSD_REG_DRAW_Y_0E_POS) -#define OSD_REG_DRAW_Y_0E_UMSK (~(((1U << OSD_REG_DRAW_Y_0E_LEN) - 1) << OSD_REG_DRAW_Y_0E_POS)) - -/* 0xB0 : draw_partial_x_confige */ -#define OSD_DRAW_PARTIAL_X_CONFIGE_OFFSET (0xB0) -#define OSD_REG_DRAW_X_MIN_0E OSD_REG_DRAW_X_MIN_0E -#define OSD_REG_DRAW_X_MIN_0E_POS (0U) -#define OSD_REG_DRAW_X_MIN_0E_LEN (11U) -#define OSD_REG_DRAW_X_MIN_0E_MSK (((1U << OSD_REG_DRAW_X_MIN_0E_LEN) - 1) << OSD_REG_DRAW_X_MIN_0E_POS) -#define OSD_REG_DRAW_X_MIN_0E_UMSK (~(((1U << OSD_REG_DRAW_X_MIN_0E_LEN) - 1) << OSD_REG_DRAW_X_MIN_0E_POS)) -#define OSD_REG_DRAW_X_MAX_0E OSD_REG_DRAW_X_MAX_0E -#define OSD_REG_DRAW_X_MAX_0E_POS (16U) -#define OSD_REG_DRAW_X_MAX_0E_LEN (11U) -#define OSD_REG_DRAW_X_MAX_0E_MSK (((1U << OSD_REG_DRAW_X_MAX_0E_LEN) - 1) << OSD_REG_DRAW_X_MAX_0E_POS) -#define OSD_REG_DRAW_X_MAX_0E_UMSK (~(((1U << OSD_REG_DRAW_X_MAX_0E_LEN) - 1) << OSD_REG_DRAW_X_MAX_0E_POS)) - -/* 0xB4 : draw_partial_y_confige */ -#define OSD_DRAW_PARTIAL_Y_CONFIGE_OFFSET (0xB4) -#define OSD_REG_DRAW_Y_MIN_0E OSD_REG_DRAW_Y_MIN_0E -#define OSD_REG_DRAW_Y_MIN_0E_POS (0U) -#define OSD_REG_DRAW_Y_MIN_0E_LEN (11U) -#define OSD_REG_DRAW_Y_MIN_0E_MSK (((1U << OSD_REG_DRAW_Y_MIN_0E_LEN) - 1) << OSD_REG_DRAW_Y_MIN_0E_POS) -#define OSD_REG_DRAW_Y_MIN_0E_UMSK (~(((1U << OSD_REG_DRAW_Y_MIN_0E_LEN) - 1) << OSD_REG_DRAW_Y_MIN_0E_POS)) -#define OSD_REG_DRAW_Y_MAX_0E OSD_REG_DRAW_Y_MAX_0E -#define OSD_REG_DRAW_Y_MAX_0E_POS (16U) -#define OSD_REG_DRAW_Y_MAX_0E_LEN (11U) -#define OSD_REG_DRAW_Y_MAX_0E_MSK (((1U << OSD_REG_DRAW_Y_MAX_0E_LEN) - 1) << OSD_REG_DRAW_Y_MAX_0E_POS) -#define OSD_REG_DRAW_Y_MAX_0E_UMSK (~(((1U << OSD_REG_DRAW_Y_MAX_0E_LEN) - 1) << OSD_REG_DRAW_Y_MAX_0E_POS)) - -/* 0xB8 : draw_partial_yuv_configf */ -#define OSD_DRAW_PARTIAL_YUV_CONFIGF_OFFSET (0xB8) -#define OSD_REG_DRAW_TH_0F OSD_REG_DRAW_TH_0F -#define OSD_REG_DRAW_TH_0F_POS (0U) -#define OSD_REG_DRAW_TH_0F_LEN (8U) -#define OSD_REG_DRAW_TH_0F_MSK (((1U << OSD_REG_DRAW_TH_0F_LEN) - 1) << OSD_REG_DRAW_TH_0F_POS) -#define OSD_REG_DRAW_TH_0F_UMSK (~(((1U << OSD_REG_DRAW_TH_0F_LEN) - 1) << OSD_REG_DRAW_TH_0F_POS)) -#define OSD_REG_DRAW_V_0F OSD_REG_DRAW_V_0F -#define OSD_REG_DRAW_V_0F_POS (8U) -#define OSD_REG_DRAW_V_0F_LEN (8U) -#define OSD_REG_DRAW_V_0F_MSK (((1U << OSD_REG_DRAW_V_0F_LEN) - 1) << OSD_REG_DRAW_V_0F_POS) -#define OSD_REG_DRAW_V_0F_UMSK (~(((1U << OSD_REG_DRAW_V_0F_LEN) - 1) << OSD_REG_DRAW_V_0F_POS)) -#define OSD_REG_DRAW_U_0F OSD_REG_DRAW_U_0F -#define OSD_REG_DRAW_U_0F_POS (16U) -#define OSD_REG_DRAW_U_0F_LEN (8U) -#define OSD_REG_DRAW_U_0F_MSK (((1U << OSD_REG_DRAW_U_0F_LEN) - 1) << OSD_REG_DRAW_U_0F_POS) -#define OSD_REG_DRAW_U_0F_UMSK (~(((1U << OSD_REG_DRAW_U_0F_LEN) - 1) << OSD_REG_DRAW_U_0F_POS)) -#define OSD_REG_DRAW_Y_0F OSD_REG_DRAW_Y_0F -#define OSD_REG_DRAW_Y_0F_POS (24U) -#define OSD_REG_DRAW_Y_0F_LEN (8U) -#define OSD_REG_DRAW_Y_0F_MSK (((1U << OSD_REG_DRAW_Y_0F_LEN) - 1) << OSD_REG_DRAW_Y_0F_POS) -#define OSD_REG_DRAW_Y_0F_UMSK (~(((1U << OSD_REG_DRAW_Y_0F_LEN) - 1) << OSD_REG_DRAW_Y_0F_POS)) - -/* 0xBC : draw_partial_x_configf */ -#define OSD_DRAW_PARTIAL_X_CONFIGF_OFFSET (0xBC) -#define OSD_REG_DRAW_X_MIN_0F OSD_REG_DRAW_X_MIN_0F -#define OSD_REG_DRAW_X_MIN_0F_POS (0U) -#define OSD_REG_DRAW_X_MIN_0F_LEN (11U) -#define OSD_REG_DRAW_X_MIN_0F_MSK (((1U << OSD_REG_DRAW_X_MIN_0F_LEN) - 1) << OSD_REG_DRAW_X_MIN_0F_POS) -#define OSD_REG_DRAW_X_MIN_0F_UMSK (~(((1U << OSD_REG_DRAW_X_MIN_0F_LEN) - 1) << OSD_REG_DRAW_X_MIN_0F_POS)) -#define OSD_REG_DRAW_X_MAX_0F OSD_REG_DRAW_X_MAX_0F -#define OSD_REG_DRAW_X_MAX_0F_POS (16U) -#define OSD_REG_DRAW_X_MAX_0F_LEN (11U) -#define OSD_REG_DRAW_X_MAX_0F_MSK (((1U << OSD_REG_DRAW_X_MAX_0F_LEN) - 1) << OSD_REG_DRAW_X_MAX_0F_POS) -#define OSD_REG_DRAW_X_MAX_0F_UMSK (~(((1U << OSD_REG_DRAW_X_MAX_0F_LEN) - 1) << OSD_REG_DRAW_X_MAX_0F_POS)) - -/* 0xC0 : draw_partial_y_configf */ -#define OSD_DRAW_PARTIAL_Y_CONFIGF_OFFSET (0xC0) -#define OSD_REG_DRAW_Y_MIN_0F OSD_REG_DRAW_Y_MIN_0F -#define OSD_REG_DRAW_Y_MIN_0F_POS (0U) -#define OSD_REG_DRAW_Y_MIN_0F_LEN (11U) -#define OSD_REG_DRAW_Y_MIN_0F_MSK (((1U << OSD_REG_DRAW_Y_MIN_0F_LEN) - 1) << OSD_REG_DRAW_Y_MIN_0F_POS) -#define OSD_REG_DRAW_Y_MIN_0F_UMSK (~(((1U << OSD_REG_DRAW_Y_MIN_0F_LEN) - 1) << OSD_REG_DRAW_Y_MIN_0F_POS)) -#define OSD_REG_DRAW_Y_MAX_0F OSD_REG_DRAW_Y_MAX_0F -#define OSD_REG_DRAW_Y_MAX_0F_POS (16U) -#define OSD_REG_DRAW_Y_MAX_0F_LEN (11U) -#define OSD_REG_DRAW_Y_MAX_0F_MSK (((1U << OSD_REG_DRAW_Y_MAX_0F_LEN) - 1) << OSD_REG_DRAW_Y_MAX_0F_POS) -#define OSD_REG_DRAW_Y_MAX_0F_UMSK (~(((1U << OSD_REG_DRAW_Y_MAX_0F_LEN) - 1) << OSD_REG_DRAW_Y_MAX_0F_POS)) - -/* 0xF8 : osd_int_sts */ -#define OSD_DRAW_INT_STS_OFFSET (0xF8) -#define OSD_DRAW_REG_SEOF_INT_CLR_W OSD_DRAW_REG_SEOF_INT_CLR_W -#define OSD_DRAW_REG_SEOF_INT_CLR_W_POS (0U) -#define OSD_DRAW_REG_SEOF_INT_CLR_W_LEN (1U) -#define OSD_DRAW_REG_SEOF_INT_CLR_W_MSK (((1U << OSD_DRAW_REG_SEOF_INT_CLR_W_LEN) - 1) << OSD_DRAW_REG_SEOF_INT_CLR_W_POS) -#define OSD_DRAW_REG_SEOF_INT_CLR_W_UMSK (~(((1U << OSD_DRAW_REG_SEOF_INT_CLR_W_LEN) - 1) << OSD_DRAW_REG_SEOF_INT_CLR_W_POS)) -#define OSD_DRAW_REG_SEOF_INT_MASK_W OSD_DRAW_REG_SEOF_INT_MASK_W -#define OSD_DRAW_REG_SEOF_INT_MASK_W_POS (1U) -#define OSD_DRAW_REG_SEOF_INT_MASK_W_LEN (1U) -#define OSD_DRAW_REG_SEOF_INT_MASK_W_MSK (((1U << OSD_DRAW_REG_SEOF_INT_MASK_W_LEN) - 1) << OSD_DRAW_REG_SEOF_INT_MASK_W_POS) -#define OSD_DRAW_REG_SEOF_INT_MASK_W_UMSK (~(((1U << OSD_DRAW_REG_SEOF_INT_MASK_W_LEN) - 1) << OSD_DRAW_REG_SEOF_INT_MASK_W_POS)) -#define OSD_DRAW_REG_SEOF_INT_EDGE_W OSD_DRAW_REG_SEOF_INT_EDGE_W -#define OSD_DRAW_REG_SEOF_INT_EDGE_W_POS (2U) -#define OSD_DRAW_REG_SEOF_INT_EDGE_W_LEN (1U) -#define OSD_DRAW_REG_SEOF_INT_EDGE_W_MSK (((1U << OSD_DRAW_REG_SEOF_INT_EDGE_W_LEN) - 1) << OSD_DRAW_REG_SEOF_INT_EDGE_W_POS) -#define OSD_DRAW_REG_SEOF_INT_EDGE_W_UMSK (~(((1U << OSD_DRAW_REG_SEOF_INT_EDGE_W_LEN) - 1) << OSD_DRAW_REG_SEOF_INT_EDGE_W_POS)) -#define OSD_DRAW_STS_DRAIN_INT_R OSD_DRAW_STS_DRAIN_INT_R -#define OSD_DRAW_STS_DRAIN_INT_R_POS (16U) -#define OSD_DRAW_STS_DRAIN_INT_R_LEN (4U) -#define OSD_DRAW_STS_DRAIN_INT_R_MSK (((1U << OSD_DRAW_STS_DRAIN_INT_R_LEN) - 1) << OSD_DRAW_STS_DRAIN_INT_R_POS) -#define OSD_DRAW_STS_DRAIN_INT_R_UMSK (~(((1U << OSD_DRAW_STS_DRAIN_INT_R_LEN) - 1) << OSD_DRAW_STS_DRAIN_INT_R_POS)) -#define OSD_DRAW_STS_SEOF_INT_R OSD_DRAW_STS_SEOF_INT_R -#define OSD_DRAW_STS_SEOF_INT_R_POS (20U) -#define OSD_DRAW_STS_SEOF_INT_R_LEN (1U) -#define OSD_DRAW_STS_SEOF_INT_R_MSK (((1U << OSD_DRAW_STS_SEOF_INT_R_LEN) - 1) << OSD_DRAW_STS_SEOF_INT_R_POS) -#define OSD_DRAW_STS_SEOF_INT_R_UMSK (~(((1U << OSD_DRAW_STS_SEOF_INT_R_LEN) - 1) << OSD_DRAW_STS_SEOF_INT_R_POS)) - -/* 0xFC : osd_misc */ -#define OSD_DRAW_MISC_OFFSET (0xFC) -#define OSD_DRAW_REG_BUS_STRT_W OSD_DRAW_REG_BUS_STRT_W -#define OSD_DRAW_REG_BUS_STRT_W_POS (0U) -#define OSD_DRAW_REG_BUS_STRT_W_LEN (1U) -#define OSD_DRAW_REG_BUS_STRT_W_MSK (((1U << OSD_DRAW_REG_BUS_STRT_W_LEN) - 1) << OSD_DRAW_REG_BUS_STRT_W_POS) -#define OSD_DRAW_REG_BUS_STRT_W_UMSK (~(((1U << OSD_DRAW_REG_BUS_STRT_W_LEN) - 1) << OSD_DRAW_REG_BUS_STRT_W_POS)) -#define OSD_DRAW_REG_FIFO_AUTO_CLR_W OSD_DRAW_REG_FIFO_AUTO_CLR_W -#define OSD_DRAW_REG_FIFO_AUTO_CLR_W_POS (1U) -#define OSD_DRAW_REG_FIFO_AUTO_CLR_W_LEN (1U) -#define OSD_DRAW_REG_FIFO_AUTO_CLR_W_MSK (((1U << OSD_DRAW_REG_FIFO_AUTO_CLR_W_LEN) - 1) << OSD_DRAW_REG_FIFO_AUTO_CLR_W_POS) -#define OSD_DRAW_REG_FIFO_AUTO_CLR_W_UMSK (~(((1U << OSD_DRAW_REG_FIFO_AUTO_CLR_W_LEN) - 1) << OSD_DRAW_REG_FIFO_AUTO_CLR_W_POS)) -#define OSD_DRAW_REG_QOS_SW_MODE_W OSD_DRAW_REG_QOS_SW_MODE_W -#define OSD_DRAW_REG_QOS_SW_MODE_W_POS (4U) -#define OSD_DRAW_REG_QOS_SW_MODE_W_LEN (1U) -#define OSD_DRAW_REG_QOS_SW_MODE_W_MSK (((1U << OSD_DRAW_REG_QOS_SW_MODE_W_LEN) - 1) << OSD_DRAW_REG_QOS_SW_MODE_W_POS) -#define OSD_DRAW_REG_QOS_SW_MODE_W_UMSK (~(((1U << OSD_DRAW_REG_QOS_SW_MODE_W_LEN) - 1) << OSD_DRAW_REG_QOS_SW_MODE_W_POS)) -#define OSD_DRAW_REG_QOS_SW_W OSD_DRAW_REG_QOS_SW_W -#define OSD_DRAW_REG_QOS_SW_W_POS (5U) -#define OSD_DRAW_REG_QOS_SW_W_LEN (1U) -#define OSD_DRAW_REG_QOS_SW_W_MSK (((1U << OSD_DRAW_REG_QOS_SW_W_LEN) - 1) << OSD_DRAW_REG_QOS_SW_W_POS) -#define OSD_DRAW_REG_QOS_SW_W_UMSK (~(((1U << OSD_DRAW_REG_QOS_SW_W_LEN) - 1) << OSD_DRAW_REG_QOS_SW_W_POS)) -#define OSD_DRAW_REG_OSTD_MAX_W OSD_DRAW_REG_OSTD_MAX_W -#define OSD_DRAW_REG_OSTD_MAX_W_POS (8U) -#define OSD_DRAW_REG_OSTD_MAX_W_LEN (2U) -#define OSD_DRAW_REG_OSTD_MAX_W_MSK (((1U << OSD_DRAW_REG_OSTD_MAX_W_LEN) - 1) << OSD_DRAW_REG_OSTD_MAX_W_POS) -#define OSD_DRAW_REG_OSTD_MAX_W_UMSK (~(((1U << OSD_DRAW_REG_OSTD_MAX_W_LEN) - 1) << OSD_DRAW_REG_OSTD_MAX_W_POS)) -#define OSD_DRAW_REG_XLEN_W OSD_DRAW_REG_XLEN_W -#define OSD_DRAW_REG_XLEN_W_POS (12U) -#define OSD_DRAW_REG_XLEN_W_LEN (3U) -#define OSD_DRAW_REG_XLEN_W_MSK (((1U << OSD_DRAW_REG_XLEN_W_LEN) - 1) << OSD_DRAW_REG_XLEN_W_POS) -#define OSD_DRAW_REG_XLEN_W_UMSK (~(((1U << OSD_DRAW_REG_XLEN_W_LEN) - 1) << OSD_DRAW_REG_XLEN_W_POS)) -#define OSD_DRAW_STS_L0_CMD_IDLE_R OSD_DRAW_STS_L0_CMD_IDLE_R -#define OSD_DRAW_STS_L0_CMD_IDLE_R_POS (16U) -#define OSD_DRAW_STS_L0_CMD_IDLE_R_LEN (1U) -#define OSD_DRAW_STS_L0_CMD_IDLE_R_MSK (((1U << OSD_DRAW_STS_L0_CMD_IDLE_R_LEN) - 1) << OSD_DRAW_STS_L0_CMD_IDLE_R_POS) -#define OSD_DRAW_STS_L0_CMD_IDLE_R_UMSK (~(((1U << OSD_DRAW_STS_L0_CMD_IDLE_R_LEN) - 1) << OSD_DRAW_STS_L0_CMD_IDLE_R_POS)) -#define OSD_DRAW_STS_L1_CMD_IDLE_R OSD_DRAW_STS_L1_CMD_IDLE_R -#define OSD_DRAW_STS_L1_CMD_IDLE_R_POS (17U) -#define OSD_DRAW_STS_L1_CMD_IDLE_R_LEN (1U) -#define OSD_DRAW_STS_L1_CMD_IDLE_R_MSK (((1U << OSD_DRAW_STS_L1_CMD_IDLE_R_LEN) - 1) << OSD_DRAW_STS_L1_CMD_IDLE_R_POS) -#define OSD_DRAW_STS_L1_CMD_IDLE_R_UMSK (~(((1U << OSD_DRAW_STS_L1_CMD_IDLE_R_LEN) - 1) << OSD_DRAW_STS_L1_CMD_IDLE_R_POS)) -#define OSD_DRAW_STS_L2_CMD_IDLE_R OSD_DRAW_STS_L2_CMD_IDLE_R -#define OSD_DRAW_STS_L2_CMD_IDLE_R_POS (18U) -#define OSD_DRAW_STS_L2_CMD_IDLE_R_LEN (1U) -#define OSD_DRAW_STS_L2_CMD_IDLE_R_MSK (((1U << OSD_DRAW_STS_L2_CMD_IDLE_R_LEN) - 1) << OSD_DRAW_STS_L2_CMD_IDLE_R_POS) -#define OSD_DRAW_STS_L2_CMD_IDLE_R_UMSK (~(((1U << OSD_DRAW_STS_L2_CMD_IDLE_R_LEN) - 1) << OSD_DRAW_STS_L2_CMD_IDLE_R_POS)) -#define OSD_DRAW_STS_L3_CMD_IDLE_R OSD_DRAW_STS_L3_CMD_IDLE_R -#define OSD_DRAW_STS_L3_CMD_IDLE_R_POS (19U) -#define OSD_DRAW_STS_L3_CMD_IDLE_R_LEN (1U) -#define OSD_DRAW_STS_L3_CMD_IDLE_R_MSK (((1U << OSD_DRAW_STS_L3_CMD_IDLE_R_LEN) - 1) << OSD_DRAW_STS_L3_CMD_IDLE_R_POS) -#define OSD_DRAW_STS_L3_CMD_IDLE_R_UMSK (~(((1U << OSD_DRAW_STS_L3_CMD_IDLE_R_LEN) - 1) << OSD_DRAW_STS_L3_CMD_IDLE_R_POS)) -#define OSD_DRAW_STS_AXI_IDLE_R OSD_DRAW_STS_AXI_IDLE_R -#define OSD_DRAW_STS_AXI_IDLE_R_POS (20U) -#define OSD_DRAW_STS_AXI_IDLE_R_LEN (1U) -#define OSD_DRAW_STS_AXI_IDLE_R_MSK (((1U << OSD_DRAW_STS_AXI_IDLE_R_LEN) - 1) << OSD_DRAW_STS_AXI_IDLE_R_POS) -#define OSD_DRAW_STS_AXI_IDLE_R_UMSK (~(((1U << OSD_DRAW_STS_AXI_IDLE_R_LEN) - 1) << OSD_DRAW_STS_AXI_IDLE_R_POS)) -#define OSD_DRAW_REG_PCLK_FORCE_ON_W OSD_DRAW_REG_PCLK_FORCE_ON_W -#define OSD_DRAW_REG_PCLK_FORCE_ON_W_POS (24U) -#define OSD_DRAW_REG_PCLK_FORCE_ON_W_LEN (8U) -#define OSD_DRAW_REG_PCLK_FORCE_ON_W_MSK (((1U << OSD_DRAW_REG_PCLK_FORCE_ON_W_LEN) - 1) << OSD_DRAW_REG_PCLK_FORCE_ON_W_POS) -#define OSD_DRAW_REG_PCLK_FORCE_ON_W_UMSK (~(((1U << OSD_DRAW_REG_PCLK_FORCE_ON_W_LEN) - 1) << OSD_DRAW_REG_PCLK_FORCE_ON_W_POS)) - -struct osd_draw_reg { - /* 0x0 : osd_draw_config */ - union { - struct { - uint32_t reg_draw_en_l : 16; /* [15: 0], r/w, 0x0 */ - uint32_t reg_draw_type_l : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } osd_draw_config; - - /* 0x4 : draw_partial_yuv_config0 */ - union { - struct { - uint32_t reg_draw_th_00 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_00 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_00 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_00 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config0; - - /* 0x8 : draw_partial_x_config0 */ - union { - struct { - uint32_t reg_draw_x_min_00 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_00 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config0; - - /* 0xC : draw_partial_y_config0 */ - union { - struct { - uint32_t reg_draw_y_min_00 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_00 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config0; - - /* 0x10 : draw_partial_yuv_config1 */ - union { - struct { - uint32_t reg_draw_th_01 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_01 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_01 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_01 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config1; - - /* 0x14 : draw_partial_x_config1 */ - union { - struct { - uint32_t reg_draw_x_min_01 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_01 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config1; - - /* 0x18 : draw_partial_y_config1 */ - union { - struct { - uint32_t reg_draw_y_min_01 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_01 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config1; - - /* 0x1C : draw_partial_yuv_config2 */ - union { - struct { - uint32_t reg_draw_th_02 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_02 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_02 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_02 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config2; - - /* 0x20 : draw_partial_x_config2 */ - union { - struct { - uint32_t reg_draw_x_min_02 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_02 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config2; - - /* 0x24 : draw_partial_y_config2 */ - union { - struct { - uint32_t reg_draw_y_min_02 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_02 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config2; - - /* 0x28 : draw_partial_yuv_config3 */ - union { - struct { - uint32_t reg_draw_th_03 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_03 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_03 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_03 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config3; - - /* 0x2C : draw_partial_x_config3 */ - union { - struct { - uint32_t reg_draw_x_min_03 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_03 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config3; - - /* 0x30 : draw_partial_y_config3 */ - union { - struct { - uint32_t reg_draw_y_min_03 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_03 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config3; - - /* 0x34 : draw_partial_yuv_config4 */ - union { - struct { - uint32_t reg_draw_th_04 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_04 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_04 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_04 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config4; - - /* 0x38 : draw_partial_x_config4 */ - union { - struct { - uint32_t reg_draw_x_min_04 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_04 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config4; - - /* 0x3C : draw_partial_y_config4 */ - union { - struct { - uint32_t reg_draw_y_min_04 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_04 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config4; - - /* 0x40 : draw_partial_yuv_config5 */ - union { - struct { - uint32_t reg_draw_th_05 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_05 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_05 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_05 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config5; - - /* 0x44 : draw_partial_x_config5 */ - union { - struct { - uint32_t reg_draw_x_min_05 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_05 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config5; - - /* 0x48 : draw_partial_y_config5 */ - union { - struct { - uint32_t reg_draw_y_min_05 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_05 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config5; - - /* 0x4C : draw_partial_yuv_config6 */ - union { - struct { - uint32_t reg_draw_th_06 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_06 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_06 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_06 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config6; - - /* 0x50 : draw_partial_x_config6 */ - union { - struct { - uint32_t reg_draw_x_min_06 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_06 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config6; - - /* 0x54 : draw_partial_y_config6 */ - union { - struct { - uint32_t reg_draw_y_min_06 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_06 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config6; - - /* 0x58 : draw_partial_yuv_config7 */ - union { - struct { - uint32_t reg_draw_th_07 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_07 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_07 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_07 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config7; - - /* 0x5C : draw_partial_x_config7 */ - union { - struct { - uint32_t reg_draw_x_min_07 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_07 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config7; - - /* 0x60 : draw_partial_y_config7 */ - union { - struct { - uint32_t reg_draw_y_min_07 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_07 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config7; - - /* 0x64 : draw_partial_yuv_config8 */ - union { - struct { - uint32_t reg_draw_th_08 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_08 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_08 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_08 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config8; - - /* 0x68 : draw_partial_x_config8 */ - union { - struct { - uint32_t reg_draw_x_min_08 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_08 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config8; - - /* 0x6C : draw_partial_y_config8 */ - union { - struct { - uint32_t reg_draw_y_min_08 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_08 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config8; - - /* 0x70 : draw_partial_yuv_config9 */ - union { - struct { - uint32_t reg_draw_th_09 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_09 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_09 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_09 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config9; - - /* 0x74 : draw_partial_x_config9 */ - union { - struct { - uint32_t reg_draw_x_min_09 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_09 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config9; - - /* 0x78 : draw_partial_y_config9 */ - union { - struct { - uint32_t reg_draw_y_min_09 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_09 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config9; - - /* 0x7C : draw_partial_yuv_configa */ - union { - struct { - uint32_t reg_draw_th_0a : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_0a : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_0a : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_0a : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_configa; - - /* 0x80 : draw_partial_x_configa */ - union { - struct { - uint32_t reg_draw_x_min_0a : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_0a : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_configa; - - /* 0x84 : draw_partial_y_configa */ - union { - struct { - uint32_t reg_draw_y_min_0a : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_0a : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_configa; - - /* 0x88 : draw_partial_yuv_configb */ - union { - struct { - uint32_t reg_draw_th_0b : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_0b : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_0b : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_0b : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_configb; - - /* 0x8C : draw_partial_x_configb */ - union { - struct { - uint32_t reg_draw_x_min_0b : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_0b : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_configb; - - /* 0x90 : draw_partial_y_configb */ - union { - struct { - uint32_t reg_draw_y_min_0b : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_0b : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_configb; - - /* 0x94 : draw_partial_yuv_configc */ - union { - struct { - uint32_t reg_draw_th_0c : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_0c : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_0c : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_0c : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_configc; - - /* 0x98 : draw_partial_x_configc */ - union { - struct { - uint32_t reg_draw_x_min_0c : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_0c : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_configc; - - /* 0x9C : draw_partial_y_configc */ - union { - struct { - uint32_t reg_draw_y_min_0c : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_0c : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_configc; - - /* 0xA0 : draw_partial_yuv_configd */ - union { - struct { - uint32_t reg_draw_th_0d : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_0d : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_0d : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_0d : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_configd; - - /* 0xA4 : draw_partial_x_configd */ - union { - struct { - uint32_t reg_draw_x_min_0d : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_0d : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_configd; - - /* 0xA8 : draw_partial_y_configd */ - union { - struct { - uint32_t reg_draw_y_min_0d : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_0d : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_configd; - - /* 0xAC : draw_partial_yuv_confige */ - union { - struct { - uint32_t reg_draw_th_0e : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_0e : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_0e : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_0e : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_confige; - - /* 0xB0 : draw_partial_x_confige */ - union { - struct { - uint32_t reg_draw_x_min_0e : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_0e : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_confige; - - /* 0xB4 : draw_partial_y_confige */ - union { - struct { - uint32_t reg_draw_y_min_0e : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_0e : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_confige; - - /* 0xB8 : draw_partial_yuv_configf */ - union { - struct { - uint32_t reg_draw_th_0f : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_0f : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_0f : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_0f : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_configf; - - /* 0xBC : draw_partial_x_configf */ - union { - struct { - uint32_t reg_draw_x_min_0f : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_0f : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_configf; - - /* 0xC0 : draw_partial_y_configf */ - union { - struct { - uint32_t reg_draw_y_min_0f : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_0f : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_configf; - - /* 0xc4 reserved */ - uint8_t RESERVED0xc4[52]; - - /* 0xF8 : osd_int_sts */ - union { - struct { - uint32_t reg_seof_int_clr_w : 1; /* [ 0], w1p, 0x0 */ - uint32_t reg_seof_int_mask_w : 1; /* [ 1], r/w, 0x0 */ - uint32_t reg_seof_int_edge_w : 1; /* [ 2], r/w, 0x0 */ - uint32_t reserved_3_15 : 13; /* [15: 3], rsvd, 0x0 */ - uint32_t sts_drain_int_r : 4; /* [19:16], r, 0x0 */ - uint32_t sts_seof_int_r : 1; /* [ 20], r, 0x0 */ - uint32_t reserved_21_31 : 11; /* [31:21], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_int_sts; - - /* 0xFC : osd_misc */ - union { - struct { - uint32_t reg_bus_strt_w : 1; /* [ 0], w1p, 0x0 */ - uint32_t reg_fifo_auto_clr_w : 1; /* [ 1], r/w, 0x1 */ - uint32_t reserved_2_3 : 2; /* [ 3: 2], rsvd, 0x0 */ - uint32_t reg_qos_sw_mode_w : 1; /* [ 4], r/w, 0x0 */ - uint32_t reg_qos_sw_w : 1; /* [ 5], r/w, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t reg_ostd_max_w : 2; /* [ 9: 8], r/w, 0x3 */ - uint32_t reserved_10_11 : 2; /* [11:10], rsvd, 0x0 */ - uint32_t reg_xlen_w : 3; /* [14:12], r/w, 0x4 */ - uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */ - uint32_t sts_l0_cmd_idle_r : 1; /* [ 16], r, 0x0 */ - uint32_t sts_l1_cmd_idle_r : 1; /* [ 17], r, 0x0 */ - uint32_t sts_l2_cmd_idle_r : 1; /* [ 18], r, 0x0 */ - uint32_t sts_l3_cmd_idle_r : 1; /* [ 19], r, 0x0 */ - uint32_t sts_axi_idle_r : 1; /* [ 20], r, 0x0 */ - uint32_t reserved_21_23 : 3; /* [23:21], rsvd, 0x0 */ - uint32_t reg_pclk_force_on_w : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } osd_misc; -}; - -typedef volatile struct osd_draw_reg osd_draw_reg_t; - -#endif /* __OSD_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/osd_pb_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/osd_pb_reg.h deleted file mode 100644 index 0ab8b710d0..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/osd_pb_reg.h +++ /dev/null @@ -1,878 +0,0 @@ -/** - ****************************************************************************** - * @file osd_pb_reg.h - * @version V1.0 - * @date 2021-06-28 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __OSD_PB_REG_H__ -#define __OSD_PB_REG_H__ - -#include "bl808.h" - -/* 0x000 : osd_pb_ctrl_reg */ -#define OSD_PB_CTRL_REG_OFFSET (0x000) -#define OSD_PB_REG_OSD_PB_LUMA_TH OSD_PB_REG_OSD_PB_LUMA_TH -#define OSD_PB_REG_OSD_PB_LUMA_TH_POS (0U) -#define OSD_PB_REG_OSD_PB_LUMA_TH_LEN (8U) -#define OSD_PB_REG_OSD_PB_LUMA_TH_MSK (((1U << OSD_PB_REG_OSD_PB_LUMA_TH_LEN) - 1) << OSD_PB_REG_OSD_PB_LUMA_TH_POS) -#define OSD_PB_REG_OSD_PB_LUMA_TH_UMSK (~(((1U << OSD_PB_REG_OSD_PB_LUMA_TH_LEN) - 1) << OSD_PB_REG_OSD_PB_LUMA_TH_POS)) -#define OSD_PB_STS_OSD_PB_W_CNT_R OSD_PB_STS_OSD_PB_W_CNT_R -#define OSD_PB_STS_OSD_PB_W_CNT_R_POS (8U) -#define OSD_PB_STS_OSD_PB_W_CNT_R_LEN (5U) -#define OSD_PB_STS_OSD_PB_W_CNT_R_MSK (((1U << OSD_PB_STS_OSD_PB_W_CNT_R_LEN) - 1) << OSD_PB_STS_OSD_PB_W_CNT_R_POS) -#define OSD_PB_STS_OSD_PB_W_CNT_R_UMSK (~(((1U << OSD_PB_STS_OSD_PB_W_CNT_R_LEN) - 1) << OSD_PB_STS_OSD_PB_W_CNT_R_POS)) -#define OSD_PB_STS_OSD_PB_IDX_R OSD_PB_STS_OSD_PB_IDX_R -#define OSD_PB_STS_OSD_PB_IDX_R_POS (15U) -#define OSD_PB_STS_OSD_PB_IDX_R_LEN (1U) -#define OSD_PB_STS_OSD_PB_IDX_R_MSK (((1U << OSD_PB_STS_OSD_PB_IDX_R_LEN) - 1) << OSD_PB_STS_OSD_PB_IDX_R_POS) -#define OSD_PB_STS_OSD_PB_IDX_R_UMSK (~(((1U << OSD_PB_STS_OSD_PB_IDX_R_LEN) - 1) << OSD_PB_STS_OSD_PB_IDX_R_POS)) - -/* 0x004 : osd_pb_result0 */ -#define OSD_PB_RESULT0_OFFSET (0x004) -#define OSD_PB_STS_OSD_PB_RESULT_0_R OSD_PB_STS_OSD_PB_RESULT_0_R -#define OSD_PB_STS_OSD_PB_RESULT_0_R_POS (0U) -#define OSD_PB_STS_OSD_PB_RESULT_0_R_LEN (32U) -#define OSD_PB_STS_OSD_PB_RESULT_0_R_MSK (((1U << OSD_PB_STS_OSD_PB_RESULT_0_R_LEN) - 1) << OSD_PB_STS_OSD_PB_RESULT_0_R_POS) -#define OSD_PB_STS_OSD_PB_RESULT_0_R_UMSK (~(((1U << OSD_PB_STS_OSD_PB_RESULT_0_R_LEN) - 1) << OSD_PB_STS_OSD_PB_RESULT_0_R_POS)) - -/* 0x008 : osd_pb_result1 */ -#define OSD_PB_RESULT1_OFFSET (0x008) -#define OSD_PB_STS_OSD_PB_RESULT_1_R OSD_PB_STS_OSD_PB_RESULT_1_R -#define OSD_PB_STS_OSD_PB_RESULT_1_R_POS (0U) -#define OSD_PB_STS_OSD_PB_RESULT_1_R_LEN (32U) -#define OSD_PB_STS_OSD_PB_RESULT_1_R_MSK (((1U << OSD_PB_STS_OSD_PB_RESULT_1_R_LEN) - 1) << OSD_PB_STS_OSD_PB_RESULT_1_R_POS) -#define OSD_PB_STS_OSD_PB_RESULT_1_R_UMSK (~(((1U << OSD_PB_STS_OSD_PB_RESULT_1_R_LEN) - 1) << OSD_PB_STS_OSD_PB_RESULT_1_R_POS)) - -/* 0x010 : osd_pb_addr_00 */ -#define OSD_PB_ADDR_00_OFFSET (0x010) -#define OSD_PB_REG_OSD_PB_X_00 OSD_PB_REG_OSD_PB_X_00 -#define OSD_PB_REG_OSD_PB_X_00_POS (0U) -#define OSD_PB_REG_OSD_PB_X_00_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_00_MSK (((1U << OSD_PB_REG_OSD_PB_X_00_LEN) - 1) << OSD_PB_REG_OSD_PB_X_00_POS) -#define OSD_PB_REG_OSD_PB_X_00_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_00_LEN) - 1) << OSD_PB_REG_OSD_PB_X_00_POS)) -#define OSD_PB_REG_OSD_PB_Y_00 OSD_PB_REG_OSD_PB_Y_00 -#define OSD_PB_REG_OSD_PB_Y_00_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_00_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_00_MSK (((1U << OSD_PB_REG_OSD_PB_Y_00_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_00_POS) -#define OSD_PB_REG_OSD_PB_Y_00_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_00_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_00_POS)) - -/* 0x014 : osd_pb_addr_01 */ -#define OSD_PB_ADDR_01_OFFSET (0x014) -#define OSD_PB_REG_OSD_PB_X_01 OSD_PB_REG_OSD_PB_X_01 -#define OSD_PB_REG_OSD_PB_X_01_POS (0U) -#define OSD_PB_REG_OSD_PB_X_01_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_01_MSK (((1U << OSD_PB_REG_OSD_PB_X_01_LEN) - 1) << OSD_PB_REG_OSD_PB_X_01_POS) -#define OSD_PB_REG_OSD_PB_X_01_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_01_LEN) - 1) << OSD_PB_REG_OSD_PB_X_01_POS)) -#define OSD_PB_REG_OSD_PB_Y_01 OSD_PB_REG_OSD_PB_Y_01 -#define OSD_PB_REG_OSD_PB_Y_01_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_01_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_01_MSK (((1U << OSD_PB_REG_OSD_PB_Y_01_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_01_POS) -#define OSD_PB_REG_OSD_PB_Y_01_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_01_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_01_POS)) - -/* 0x018 : osd_pb_addr_02 */ -#define OSD_PB_ADDR_02_OFFSET (0x018) -#define OSD_PB_REG_OSD_PB_X_02 OSD_PB_REG_OSD_PB_X_02 -#define OSD_PB_REG_OSD_PB_X_02_POS (0U) -#define OSD_PB_REG_OSD_PB_X_02_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_02_MSK (((1U << OSD_PB_REG_OSD_PB_X_02_LEN) - 1) << OSD_PB_REG_OSD_PB_X_02_POS) -#define OSD_PB_REG_OSD_PB_X_02_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_02_LEN) - 1) << OSD_PB_REG_OSD_PB_X_02_POS)) -#define OSD_PB_REG_OSD_PB_Y_02 OSD_PB_REG_OSD_PB_Y_02 -#define OSD_PB_REG_OSD_PB_Y_02_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_02_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_02_MSK (((1U << OSD_PB_REG_OSD_PB_Y_02_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_02_POS) -#define OSD_PB_REG_OSD_PB_Y_02_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_02_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_02_POS)) - -/* 0x01C : osd_pb_addr_03 */ -#define OSD_PB_ADDR_03_OFFSET (0x01C) -#define OSD_PB_REG_OSD_PB_X_03 OSD_PB_REG_OSD_PB_X_03 -#define OSD_PB_REG_OSD_PB_X_03_POS (0U) -#define OSD_PB_REG_OSD_PB_X_03_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_03_MSK (((1U << OSD_PB_REG_OSD_PB_X_03_LEN) - 1) << OSD_PB_REG_OSD_PB_X_03_POS) -#define OSD_PB_REG_OSD_PB_X_03_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_03_LEN) - 1) << OSD_PB_REG_OSD_PB_X_03_POS)) -#define OSD_PB_REG_OSD_PB_Y_03 OSD_PB_REG_OSD_PB_Y_03 -#define OSD_PB_REG_OSD_PB_Y_03_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_03_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_03_MSK (((1U << OSD_PB_REG_OSD_PB_Y_03_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_03_POS) -#define OSD_PB_REG_OSD_PB_Y_03_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_03_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_03_POS)) - -/* 0x020 : osd_pb_addr_04 */ -#define OSD_PB_ADDR_04_OFFSET (0x020) -#define OSD_PB_REG_OSD_PB_X_04 OSD_PB_REG_OSD_PB_X_04 -#define OSD_PB_REG_OSD_PB_X_04_POS (0U) -#define OSD_PB_REG_OSD_PB_X_04_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_04_MSK (((1U << OSD_PB_REG_OSD_PB_X_04_LEN) - 1) << OSD_PB_REG_OSD_PB_X_04_POS) -#define OSD_PB_REG_OSD_PB_X_04_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_04_LEN) - 1) << OSD_PB_REG_OSD_PB_X_04_POS)) -#define OSD_PB_REG_OSD_PB_Y_04 OSD_PB_REG_OSD_PB_Y_04 -#define OSD_PB_REG_OSD_PB_Y_04_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_04_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_04_MSK (((1U << OSD_PB_REG_OSD_PB_Y_04_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_04_POS) -#define OSD_PB_REG_OSD_PB_Y_04_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_04_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_04_POS)) - -/* 0x024 : osd_pb_addr_05 */ -#define OSD_PB_ADDR_05_OFFSET (0x024) -#define OSD_PB_REG_OSD_PB_X_05 OSD_PB_REG_OSD_PB_X_05 -#define OSD_PB_REG_OSD_PB_X_05_POS (0U) -#define OSD_PB_REG_OSD_PB_X_05_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_05_MSK (((1U << OSD_PB_REG_OSD_PB_X_05_LEN) - 1) << OSD_PB_REG_OSD_PB_X_05_POS) -#define OSD_PB_REG_OSD_PB_X_05_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_05_LEN) - 1) << OSD_PB_REG_OSD_PB_X_05_POS)) -#define OSD_PB_REG_OSD_PB_Y_05 OSD_PB_REG_OSD_PB_Y_05 -#define OSD_PB_REG_OSD_PB_Y_05_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_05_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_05_MSK (((1U << OSD_PB_REG_OSD_PB_Y_05_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_05_POS) -#define OSD_PB_REG_OSD_PB_Y_05_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_05_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_05_POS)) - -/* 0x028 : osd_pb_addr_06 */ -#define OSD_PB_ADDR_06_OFFSET (0x028) -#define OSD_PB_REG_OSD_PB_X_06 OSD_PB_REG_OSD_PB_X_06 -#define OSD_PB_REG_OSD_PB_X_06_POS (0U) -#define OSD_PB_REG_OSD_PB_X_06_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_06_MSK (((1U << OSD_PB_REG_OSD_PB_X_06_LEN) - 1) << OSD_PB_REG_OSD_PB_X_06_POS) -#define OSD_PB_REG_OSD_PB_X_06_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_06_LEN) - 1) << OSD_PB_REG_OSD_PB_X_06_POS)) -#define OSD_PB_REG_OSD_PB_Y_06 OSD_PB_REG_OSD_PB_Y_06 -#define OSD_PB_REG_OSD_PB_Y_06_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_06_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_06_MSK (((1U << OSD_PB_REG_OSD_PB_Y_06_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_06_POS) -#define OSD_PB_REG_OSD_PB_Y_06_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_06_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_06_POS)) - -/* 0x02C : osd_pb_addr_07 */ -#define OSD_PB_ADDR_07_OFFSET (0x02C) -#define OSD_PB_REG_OSD_PB_X_07 OSD_PB_REG_OSD_PB_X_07 -#define OSD_PB_REG_OSD_PB_X_07_POS (0U) -#define OSD_PB_REG_OSD_PB_X_07_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_07_MSK (((1U << OSD_PB_REG_OSD_PB_X_07_LEN) - 1) << OSD_PB_REG_OSD_PB_X_07_POS) -#define OSD_PB_REG_OSD_PB_X_07_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_07_LEN) - 1) << OSD_PB_REG_OSD_PB_X_07_POS)) -#define OSD_PB_REG_OSD_PB_Y_07 OSD_PB_REG_OSD_PB_Y_07 -#define OSD_PB_REG_OSD_PB_Y_07_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_07_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_07_MSK (((1U << OSD_PB_REG_OSD_PB_Y_07_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_07_POS) -#define OSD_PB_REG_OSD_PB_Y_07_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_07_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_07_POS)) - -/* 0x030 : osd_pb_addr_08 */ -#define OSD_PB_ADDR_08_OFFSET (0x030) -#define OSD_PB_REG_OSD_PB_X_08 OSD_PB_REG_OSD_PB_X_08 -#define OSD_PB_REG_OSD_PB_X_08_POS (0U) -#define OSD_PB_REG_OSD_PB_X_08_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_08_MSK (((1U << OSD_PB_REG_OSD_PB_X_08_LEN) - 1) << OSD_PB_REG_OSD_PB_X_08_POS) -#define OSD_PB_REG_OSD_PB_X_08_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_08_LEN) - 1) << OSD_PB_REG_OSD_PB_X_08_POS)) -#define OSD_PB_REG_OSD_PB_Y_08 OSD_PB_REG_OSD_PB_Y_08 -#define OSD_PB_REG_OSD_PB_Y_08_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_08_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_08_MSK (((1U << OSD_PB_REG_OSD_PB_Y_08_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_08_POS) -#define OSD_PB_REG_OSD_PB_Y_08_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_08_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_08_POS)) - -/* 0x034 : osd_pb_addr_09 */ -#define OSD_PB_ADDR_09_OFFSET (0x034) -#define OSD_PB_REG_OSD_PB_X_09 OSD_PB_REG_OSD_PB_X_09 -#define OSD_PB_REG_OSD_PB_X_09_POS (0U) -#define OSD_PB_REG_OSD_PB_X_09_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_09_MSK (((1U << OSD_PB_REG_OSD_PB_X_09_LEN) - 1) << OSD_PB_REG_OSD_PB_X_09_POS) -#define OSD_PB_REG_OSD_PB_X_09_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_09_LEN) - 1) << OSD_PB_REG_OSD_PB_X_09_POS)) -#define OSD_PB_REG_OSD_PB_Y_09 OSD_PB_REG_OSD_PB_Y_09 -#define OSD_PB_REG_OSD_PB_Y_09_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_09_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_09_MSK (((1U << OSD_PB_REG_OSD_PB_Y_09_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_09_POS) -#define OSD_PB_REG_OSD_PB_Y_09_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_09_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_09_POS)) - -/* 0x038 : osd_pb_addr_0a */ -#define OSD_PB_ADDR_0A_OFFSET (0x038) -#define OSD_PB_REG_OSD_PB_X_0A OSD_PB_REG_OSD_PB_X_0A -#define OSD_PB_REG_OSD_PB_X_0A_POS (0U) -#define OSD_PB_REG_OSD_PB_X_0A_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_0A_MSK (((1U << OSD_PB_REG_OSD_PB_X_0A_LEN) - 1) << OSD_PB_REG_OSD_PB_X_0A_POS) -#define OSD_PB_REG_OSD_PB_X_0A_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_0A_LEN) - 1) << OSD_PB_REG_OSD_PB_X_0A_POS)) -#define OSD_PB_REG_OSD_PB_Y_0A OSD_PB_REG_OSD_PB_Y_0A -#define OSD_PB_REG_OSD_PB_Y_0A_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_0A_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_0A_MSK (((1U << OSD_PB_REG_OSD_PB_Y_0A_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_0A_POS) -#define OSD_PB_REG_OSD_PB_Y_0A_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_0A_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_0A_POS)) - -/* 0x03C : osd_pb_addr_0b */ -#define OSD_PB_ADDR_0B_OFFSET (0x03C) -#define OSD_PB_REG_OSD_PB_X_0B OSD_PB_REG_OSD_PB_X_0B -#define OSD_PB_REG_OSD_PB_X_0B_POS (0U) -#define OSD_PB_REG_OSD_PB_X_0B_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_0B_MSK (((1U << OSD_PB_REG_OSD_PB_X_0B_LEN) - 1) << OSD_PB_REG_OSD_PB_X_0B_POS) -#define OSD_PB_REG_OSD_PB_X_0B_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_0B_LEN) - 1) << OSD_PB_REG_OSD_PB_X_0B_POS)) -#define OSD_PB_REG_OSD_PB_Y_0B OSD_PB_REG_OSD_PB_Y_0B -#define OSD_PB_REG_OSD_PB_Y_0B_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_0B_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_0B_MSK (((1U << OSD_PB_REG_OSD_PB_Y_0B_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_0B_POS) -#define OSD_PB_REG_OSD_PB_Y_0B_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_0B_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_0B_POS)) - -/* 0x040 : osd_pb_addr_0c */ -#define OSD_PB_ADDR_0C_OFFSET (0x040) -#define OSD_PB_REG_OSD_PB_X_0C OSD_PB_REG_OSD_PB_X_0C -#define OSD_PB_REG_OSD_PB_X_0C_POS (0U) -#define OSD_PB_REG_OSD_PB_X_0C_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_0C_MSK (((1U << OSD_PB_REG_OSD_PB_X_0C_LEN) - 1) << OSD_PB_REG_OSD_PB_X_0C_POS) -#define OSD_PB_REG_OSD_PB_X_0C_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_0C_LEN) - 1) << OSD_PB_REG_OSD_PB_X_0C_POS)) -#define OSD_PB_REG_OSD_PB_Y_0C OSD_PB_REG_OSD_PB_Y_0C -#define OSD_PB_REG_OSD_PB_Y_0C_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_0C_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_0C_MSK (((1U << OSD_PB_REG_OSD_PB_Y_0C_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_0C_POS) -#define OSD_PB_REG_OSD_PB_Y_0C_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_0C_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_0C_POS)) - -/* 0x044 : osd_pb_addr_0d */ -#define OSD_PB_ADDR_0D_OFFSET (0x044) -#define OSD_PB_REG_OSD_PB_X_0D OSD_PB_REG_OSD_PB_X_0D -#define OSD_PB_REG_OSD_PB_X_0D_POS (0U) -#define OSD_PB_REG_OSD_PB_X_0D_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_0D_MSK (((1U << OSD_PB_REG_OSD_PB_X_0D_LEN) - 1) << OSD_PB_REG_OSD_PB_X_0D_POS) -#define OSD_PB_REG_OSD_PB_X_0D_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_0D_LEN) - 1) << OSD_PB_REG_OSD_PB_X_0D_POS)) -#define OSD_PB_REG_OSD_PB_Y_0D OSD_PB_REG_OSD_PB_Y_0D -#define OSD_PB_REG_OSD_PB_Y_0D_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_0D_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_0D_MSK (((1U << OSD_PB_REG_OSD_PB_Y_0D_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_0D_POS) -#define OSD_PB_REG_OSD_PB_Y_0D_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_0D_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_0D_POS)) - -/* 0x048 : osd_pb_addr_0e */ -#define OSD_PB_ADDR_0E_OFFSET (0x048) -#define OSD_PB_REG_OSD_PB_X_0E OSD_PB_REG_OSD_PB_X_0E -#define OSD_PB_REG_OSD_PB_X_0E_POS (0U) -#define OSD_PB_REG_OSD_PB_X_0E_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_0E_MSK (((1U << OSD_PB_REG_OSD_PB_X_0E_LEN) - 1) << OSD_PB_REG_OSD_PB_X_0E_POS) -#define OSD_PB_REG_OSD_PB_X_0E_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_0E_LEN) - 1) << OSD_PB_REG_OSD_PB_X_0E_POS)) -#define OSD_PB_REG_OSD_PB_Y_0E OSD_PB_REG_OSD_PB_Y_0E -#define OSD_PB_REG_OSD_PB_Y_0E_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_0E_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_0E_MSK (((1U << OSD_PB_REG_OSD_PB_Y_0E_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_0E_POS) -#define OSD_PB_REG_OSD_PB_Y_0E_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_0E_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_0E_POS)) - -/* 0x04C : osd_pb_addr_0f */ -#define OSD_PB_ADDR_0F_OFFSET (0x04C) -#define OSD_PB_REG_OSD_PB_X_0F OSD_PB_REG_OSD_PB_X_0F -#define OSD_PB_REG_OSD_PB_X_0F_POS (0U) -#define OSD_PB_REG_OSD_PB_X_0F_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_0F_MSK (((1U << OSD_PB_REG_OSD_PB_X_0F_LEN) - 1) << OSD_PB_REG_OSD_PB_X_0F_POS) -#define OSD_PB_REG_OSD_PB_X_0F_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_0F_LEN) - 1) << OSD_PB_REG_OSD_PB_X_0F_POS)) -#define OSD_PB_REG_OSD_PB_Y_0F OSD_PB_REG_OSD_PB_Y_0F -#define OSD_PB_REG_OSD_PB_Y_0F_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_0F_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_0F_MSK (((1U << OSD_PB_REG_OSD_PB_Y_0F_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_0F_POS) -#define OSD_PB_REG_OSD_PB_Y_0F_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_0F_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_0F_POS)) - -/* 0x050 : osd_pb_addr_10 */ -#define OSD_PB_ADDR_10_OFFSET (0x050) -#define OSD_PB_REG_OSD_PB_X_10 OSD_PB_REG_OSD_PB_X_10 -#define OSD_PB_REG_OSD_PB_X_10_POS (0U) -#define OSD_PB_REG_OSD_PB_X_10_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_10_MSK (((1U << OSD_PB_REG_OSD_PB_X_10_LEN) - 1) << OSD_PB_REG_OSD_PB_X_10_POS) -#define OSD_PB_REG_OSD_PB_X_10_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_10_LEN) - 1) << OSD_PB_REG_OSD_PB_X_10_POS)) -#define OSD_PB_REG_OSD_PB_Y_10 OSD_PB_REG_OSD_PB_Y_10 -#define OSD_PB_REG_OSD_PB_Y_10_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_10_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_10_MSK (((1U << OSD_PB_REG_OSD_PB_Y_10_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_10_POS) -#define OSD_PB_REG_OSD_PB_Y_10_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_10_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_10_POS)) - -/* 0x054 : osd_pb_addr_11 */ -#define OSD_PB_ADDR_11_OFFSET (0x054) -#define OSD_PB_REG_OSD_PB_X_11 OSD_PB_REG_OSD_PB_X_11 -#define OSD_PB_REG_OSD_PB_X_11_POS (0U) -#define OSD_PB_REG_OSD_PB_X_11_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_11_MSK (((1U << OSD_PB_REG_OSD_PB_X_11_LEN) - 1) << OSD_PB_REG_OSD_PB_X_11_POS) -#define OSD_PB_REG_OSD_PB_X_11_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_11_LEN) - 1) << OSD_PB_REG_OSD_PB_X_11_POS)) -#define OSD_PB_REG_OSD_PB_Y_11 OSD_PB_REG_OSD_PB_Y_11 -#define OSD_PB_REG_OSD_PB_Y_11_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_11_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_11_MSK (((1U << OSD_PB_REG_OSD_PB_Y_11_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_11_POS) -#define OSD_PB_REG_OSD_PB_Y_11_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_11_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_11_POS)) - -/* 0x058 : osd_pb_addr_12 */ -#define OSD_PB_ADDR_12_OFFSET (0x058) -#define OSD_PB_REG_OSD_PB_X_12 OSD_PB_REG_OSD_PB_X_12 -#define OSD_PB_REG_OSD_PB_X_12_POS (0U) -#define OSD_PB_REG_OSD_PB_X_12_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_12_MSK (((1U << OSD_PB_REG_OSD_PB_X_12_LEN) - 1) << OSD_PB_REG_OSD_PB_X_12_POS) -#define OSD_PB_REG_OSD_PB_X_12_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_12_LEN) - 1) << OSD_PB_REG_OSD_PB_X_12_POS)) -#define OSD_PB_REG_OSD_PB_Y_12 OSD_PB_REG_OSD_PB_Y_12 -#define OSD_PB_REG_OSD_PB_Y_12_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_12_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_12_MSK (((1U << OSD_PB_REG_OSD_PB_Y_12_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_12_POS) -#define OSD_PB_REG_OSD_PB_Y_12_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_12_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_12_POS)) - -/* 0x05C : osd_pb_addr_13 */ -#define OSD_PB_ADDR_13_OFFSET (0x05C) -#define OSD_PB_REG_OSD_PB_X_13 OSD_PB_REG_OSD_PB_X_13 -#define OSD_PB_REG_OSD_PB_X_13_POS (0U) -#define OSD_PB_REG_OSD_PB_X_13_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_13_MSK (((1U << OSD_PB_REG_OSD_PB_X_13_LEN) - 1) << OSD_PB_REG_OSD_PB_X_13_POS) -#define OSD_PB_REG_OSD_PB_X_13_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_13_LEN) - 1) << OSD_PB_REG_OSD_PB_X_13_POS)) -#define OSD_PB_REG_OSD_PB_Y_13 OSD_PB_REG_OSD_PB_Y_13 -#define OSD_PB_REG_OSD_PB_Y_13_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_13_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_13_MSK (((1U << OSD_PB_REG_OSD_PB_Y_13_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_13_POS) -#define OSD_PB_REG_OSD_PB_Y_13_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_13_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_13_POS)) - -/* 0x060 : osd_pb_addr_14 */ -#define OSD_PB_ADDR_14_OFFSET (0x060) -#define OSD_PB_REG_OSD_PB_X_14 OSD_PB_REG_OSD_PB_X_14 -#define OSD_PB_REG_OSD_PB_X_14_POS (0U) -#define OSD_PB_REG_OSD_PB_X_14_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_14_MSK (((1U << OSD_PB_REG_OSD_PB_X_14_LEN) - 1) << OSD_PB_REG_OSD_PB_X_14_POS) -#define OSD_PB_REG_OSD_PB_X_14_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_14_LEN) - 1) << OSD_PB_REG_OSD_PB_X_14_POS)) -#define OSD_PB_REG_OSD_PB_Y_14 OSD_PB_REG_OSD_PB_Y_14 -#define OSD_PB_REG_OSD_PB_Y_14_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_14_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_14_MSK (((1U << OSD_PB_REG_OSD_PB_Y_14_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_14_POS) -#define OSD_PB_REG_OSD_PB_Y_14_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_14_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_14_POS)) - -/* 0x064 : osd_pb_addr_15 */ -#define OSD_PB_ADDR_15_OFFSET (0x064) -#define OSD_PB_REG_OSD_PB_X_15 OSD_PB_REG_OSD_PB_X_15 -#define OSD_PB_REG_OSD_PB_X_15_POS (0U) -#define OSD_PB_REG_OSD_PB_X_15_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_15_MSK (((1U << OSD_PB_REG_OSD_PB_X_15_LEN) - 1) << OSD_PB_REG_OSD_PB_X_15_POS) -#define OSD_PB_REG_OSD_PB_X_15_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_15_LEN) - 1) << OSD_PB_REG_OSD_PB_X_15_POS)) -#define OSD_PB_REG_OSD_PB_Y_15 OSD_PB_REG_OSD_PB_Y_15 -#define OSD_PB_REG_OSD_PB_Y_15_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_15_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_15_MSK (((1U << OSD_PB_REG_OSD_PB_Y_15_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_15_POS) -#define OSD_PB_REG_OSD_PB_Y_15_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_15_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_15_POS)) - -/* 0x068 : osd_pb_addr_16 */ -#define OSD_PB_ADDR_16_OFFSET (0x068) -#define OSD_PB_REG_OSD_PB_X_16 OSD_PB_REG_OSD_PB_X_16 -#define OSD_PB_REG_OSD_PB_X_16_POS (0U) -#define OSD_PB_REG_OSD_PB_X_16_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_16_MSK (((1U << OSD_PB_REG_OSD_PB_X_16_LEN) - 1) << OSD_PB_REG_OSD_PB_X_16_POS) -#define OSD_PB_REG_OSD_PB_X_16_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_16_LEN) - 1) << OSD_PB_REG_OSD_PB_X_16_POS)) -#define OSD_PB_REG_OSD_PB_Y_16 OSD_PB_REG_OSD_PB_Y_16 -#define OSD_PB_REG_OSD_PB_Y_16_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_16_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_16_MSK (((1U << OSD_PB_REG_OSD_PB_Y_16_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_16_POS) -#define OSD_PB_REG_OSD_PB_Y_16_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_16_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_16_POS)) - -/* 0x06C : osd_pb_addr_17 */ -#define OSD_PB_ADDR_17_OFFSET (0x06C) -#define OSD_PB_REG_OSD_PB_X_17 OSD_PB_REG_OSD_PB_X_17 -#define OSD_PB_REG_OSD_PB_X_17_POS (0U) -#define OSD_PB_REG_OSD_PB_X_17_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_17_MSK (((1U << OSD_PB_REG_OSD_PB_X_17_LEN) - 1) << OSD_PB_REG_OSD_PB_X_17_POS) -#define OSD_PB_REG_OSD_PB_X_17_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_17_LEN) - 1) << OSD_PB_REG_OSD_PB_X_17_POS)) -#define OSD_PB_REG_OSD_PB_Y_17 OSD_PB_REG_OSD_PB_Y_17 -#define OSD_PB_REG_OSD_PB_Y_17_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_17_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_17_MSK (((1U << OSD_PB_REG_OSD_PB_Y_17_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_17_POS) -#define OSD_PB_REG_OSD_PB_Y_17_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_17_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_17_POS)) - -/* 0x070 : osd_pb_addr_18 */ -#define OSD_PB_ADDR_18_OFFSET (0x070) -#define OSD_PB_REG_OSD_PB_X_18 OSD_PB_REG_OSD_PB_X_18 -#define OSD_PB_REG_OSD_PB_X_18_POS (0U) -#define OSD_PB_REG_OSD_PB_X_18_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_18_MSK (((1U << OSD_PB_REG_OSD_PB_X_18_LEN) - 1) << OSD_PB_REG_OSD_PB_X_18_POS) -#define OSD_PB_REG_OSD_PB_X_18_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_18_LEN) - 1) << OSD_PB_REG_OSD_PB_X_18_POS)) -#define OSD_PB_REG_OSD_PB_Y_18 OSD_PB_REG_OSD_PB_Y_18 -#define OSD_PB_REG_OSD_PB_Y_18_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_18_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_18_MSK (((1U << OSD_PB_REG_OSD_PB_Y_18_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_18_POS) -#define OSD_PB_REG_OSD_PB_Y_18_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_18_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_18_POS)) - -/* 0x074 : osd_pb_addr_19 */ -#define OSD_PB_ADDR_19_OFFSET (0x074) -#define OSD_PB_REG_OSD_PB_X_19 OSD_PB_REG_OSD_PB_X_19 -#define OSD_PB_REG_OSD_PB_X_19_POS (0U) -#define OSD_PB_REG_OSD_PB_X_19_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_19_MSK (((1U << OSD_PB_REG_OSD_PB_X_19_LEN) - 1) << OSD_PB_REG_OSD_PB_X_19_POS) -#define OSD_PB_REG_OSD_PB_X_19_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_19_LEN) - 1) << OSD_PB_REG_OSD_PB_X_19_POS)) -#define OSD_PB_REG_OSD_PB_Y_19 OSD_PB_REG_OSD_PB_Y_19 -#define OSD_PB_REG_OSD_PB_Y_19_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_19_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_19_MSK (((1U << OSD_PB_REG_OSD_PB_Y_19_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_19_POS) -#define OSD_PB_REG_OSD_PB_Y_19_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_19_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_19_POS)) - -/* 0x078 : osd_pb_addr_1a */ -#define OSD_PB_ADDR_1A_OFFSET (0x078) -#define OSD_PB_REG_OSD_PB_X_1A OSD_PB_REG_OSD_PB_X_1A -#define OSD_PB_REG_OSD_PB_X_1A_POS (0U) -#define OSD_PB_REG_OSD_PB_X_1A_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_1A_MSK (((1U << OSD_PB_REG_OSD_PB_X_1A_LEN) - 1) << OSD_PB_REG_OSD_PB_X_1A_POS) -#define OSD_PB_REG_OSD_PB_X_1A_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_1A_LEN) - 1) << OSD_PB_REG_OSD_PB_X_1A_POS)) -#define OSD_PB_REG_OSD_PB_Y_1A OSD_PB_REG_OSD_PB_Y_1A -#define OSD_PB_REG_OSD_PB_Y_1A_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_1A_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_1A_MSK (((1U << OSD_PB_REG_OSD_PB_Y_1A_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_1A_POS) -#define OSD_PB_REG_OSD_PB_Y_1A_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_1A_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_1A_POS)) - -/* 0x07C : osd_pb_addr_1b */ -#define OSD_PB_ADDR_1B_OFFSET (0x07C) -#define OSD_PB_REG_OSD_PB_X_1B OSD_PB_REG_OSD_PB_X_1B -#define OSD_PB_REG_OSD_PB_X_1B_POS (0U) -#define OSD_PB_REG_OSD_PB_X_1B_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_1B_MSK (((1U << OSD_PB_REG_OSD_PB_X_1B_LEN) - 1) << OSD_PB_REG_OSD_PB_X_1B_POS) -#define OSD_PB_REG_OSD_PB_X_1B_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_1B_LEN) - 1) << OSD_PB_REG_OSD_PB_X_1B_POS)) -#define OSD_PB_REG_OSD_PB_Y_1B OSD_PB_REG_OSD_PB_Y_1B -#define OSD_PB_REG_OSD_PB_Y_1B_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_1B_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_1B_MSK (((1U << OSD_PB_REG_OSD_PB_Y_1B_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_1B_POS) -#define OSD_PB_REG_OSD_PB_Y_1B_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_1B_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_1B_POS)) - -/* 0x080 : osd_pb_addr_1c */ -#define OSD_PB_ADDR_1C_OFFSET (0x080) -#define OSD_PB_REG_OSD_PB_X_1C OSD_PB_REG_OSD_PB_X_1C -#define OSD_PB_REG_OSD_PB_X_1C_POS (0U) -#define OSD_PB_REG_OSD_PB_X_1C_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_1C_MSK (((1U << OSD_PB_REG_OSD_PB_X_1C_LEN) - 1) << OSD_PB_REG_OSD_PB_X_1C_POS) -#define OSD_PB_REG_OSD_PB_X_1C_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_1C_LEN) - 1) << OSD_PB_REG_OSD_PB_X_1C_POS)) -#define OSD_PB_REG_OSD_PB_Y_1C OSD_PB_REG_OSD_PB_Y_1C -#define OSD_PB_REG_OSD_PB_Y_1C_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_1C_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_1C_MSK (((1U << OSD_PB_REG_OSD_PB_Y_1C_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_1C_POS) -#define OSD_PB_REG_OSD_PB_Y_1C_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_1C_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_1C_POS)) - -/* 0x084 : osd_pb_addr_1d */ -#define OSD_PB_ADDR_1D_OFFSET (0x084) -#define OSD_PB_REG_OSD_PB_X_1D OSD_PB_REG_OSD_PB_X_1D -#define OSD_PB_REG_OSD_PB_X_1D_POS (0U) -#define OSD_PB_REG_OSD_PB_X_1D_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_1D_MSK (((1U << OSD_PB_REG_OSD_PB_X_1D_LEN) - 1) << OSD_PB_REG_OSD_PB_X_1D_POS) -#define OSD_PB_REG_OSD_PB_X_1D_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_1D_LEN) - 1) << OSD_PB_REG_OSD_PB_X_1D_POS)) -#define OSD_PB_REG_OSD_PB_Y_1D OSD_PB_REG_OSD_PB_Y_1D -#define OSD_PB_REG_OSD_PB_Y_1D_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_1D_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_1D_MSK (((1U << OSD_PB_REG_OSD_PB_Y_1D_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_1D_POS) -#define OSD_PB_REG_OSD_PB_Y_1D_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_1D_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_1D_POS)) - -/* 0x088 : osd_pb_addr_1e */ -#define OSD_PB_ADDR_1E_OFFSET (0x088) -#define OSD_PB_REG_OSD_PB_X_1E OSD_PB_REG_OSD_PB_X_1E -#define OSD_PB_REG_OSD_PB_X_1E_POS (0U) -#define OSD_PB_REG_OSD_PB_X_1E_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_1E_MSK (((1U << OSD_PB_REG_OSD_PB_X_1E_LEN) - 1) << OSD_PB_REG_OSD_PB_X_1E_POS) -#define OSD_PB_REG_OSD_PB_X_1E_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_1E_LEN) - 1) << OSD_PB_REG_OSD_PB_X_1E_POS)) -#define OSD_PB_REG_OSD_PB_Y_1E OSD_PB_REG_OSD_PB_Y_1E -#define OSD_PB_REG_OSD_PB_Y_1E_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_1E_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_1E_MSK (((1U << OSD_PB_REG_OSD_PB_Y_1E_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_1E_POS) -#define OSD_PB_REG_OSD_PB_Y_1E_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_1E_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_1E_POS)) - -/* 0x08C : osd_pb_addr_1f */ -#define OSD_PB_ADDR_1F_OFFSET (0x08C) -#define OSD_PB_REG_OSD_PB_X_1F OSD_PB_REG_OSD_PB_X_1F -#define OSD_PB_REG_OSD_PB_X_1F_POS (0U) -#define OSD_PB_REG_OSD_PB_X_1F_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_1F_MSK (((1U << OSD_PB_REG_OSD_PB_X_1F_LEN) - 1) << OSD_PB_REG_OSD_PB_X_1F_POS) -#define OSD_PB_REG_OSD_PB_X_1F_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_1F_LEN) - 1) << OSD_PB_REG_OSD_PB_X_1F_POS)) -#define OSD_PB_REG_OSD_PB_Y_1F OSD_PB_REG_OSD_PB_Y_1F -#define OSD_PB_REG_OSD_PB_Y_1F_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_1F_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_1F_MSK (((1U << OSD_PB_REG_OSD_PB_Y_1F_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_1F_POS) -#define OSD_PB_REG_OSD_PB_Y_1F_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_1F_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_1F_POS)) - -struct osd_pb_reg { - /* 0x000 : osd_pb_ctrl_reg */ - union { - struct { - uint32_t reg_osd_pb_luma_th : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t sts_osd_pb_w_cnt_r : 5; /* [12: 8], r, 0x0 */ - uint32_t reserved_13_14 : 2; /* [14:13], rsvd, 0x0 */ - uint32_t sts_osd_pb_idx_r : 1; /* [ 15], r, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_ctrl_reg; - - /* 0x004 : osd_pb_result0 */ - union { - struct { - uint32_t sts_osd_pb_result_0_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_result0; - - /* 0x008 : osd_pb_result1 */ - union { - struct { - uint32_t sts_osd_pb_result_1_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_result1; - - /* 0xc reserved */ - uint8_t RESERVED0xc[4]; - - /* 0x010 : osd_pb_addr_00 */ - union { - struct { - uint32_t reg_osd_pb_x_00 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_00 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_00; - - /* 0x014 : osd_pb_addr_01 */ - union { - struct { - uint32_t reg_osd_pb_x_01 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_01 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_01; - - /* 0x018 : osd_pb_addr_02 */ - union { - struct { - uint32_t reg_osd_pb_x_02 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_02 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_02; - - /* 0x01C : osd_pb_addr_03 */ - union { - struct { - uint32_t reg_osd_pb_x_03 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_03 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_03; - - /* 0x020 : osd_pb_addr_04 */ - union { - struct { - uint32_t reg_osd_pb_x_04 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_04 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_04; - - /* 0x024 : osd_pb_addr_05 */ - union { - struct { - uint32_t reg_osd_pb_x_05 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_05 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_05; - - /* 0x028 : osd_pb_addr_06 */ - union { - struct { - uint32_t reg_osd_pb_x_06 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_06 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_06; - - /* 0x02C : osd_pb_addr_07 */ - union { - struct { - uint32_t reg_osd_pb_x_07 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_07 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_07; - - /* 0x030 : osd_pb_addr_08 */ - union { - struct { - uint32_t reg_osd_pb_x_08 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_08 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_08; - - /* 0x034 : osd_pb_addr_09 */ - union { - struct { - uint32_t reg_osd_pb_x_09 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_09 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_09; - - /* 0x038 : osd_pb_addr_0a */ - union { - struct { - uint32_t reg_osd_pb_x_0a : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_0a : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_0a; - - /* 0x03C : osd_pb_addr_0b */ - union { - struct { - uint32_t reg_osd_pb_x_0b : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_0b : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_0b; - - /* 0x040 : osd_pb_addr_0c */ - union { - struct { - uint32_t reg_osd_pb_x_0c : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_0c : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_0c; - - /* 0x044 : osd_pb_addr_0d */ - union { - struct { - uint32_t reg_osd_pb_x_0d : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_0d : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_0d; - - /* 0x048 : osd_pb_addr_0e */ - union { - struct { - uint32_t reg_osd_pb_x_0e : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_0e : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_0e; - - /* 0x04C : osd_pb_addr_0f */ - union { - struct { - uint32_t reg_osd_pb_x_0f : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_0f : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_0f; - - /* 0x050 : osd_pb_addr_10 */ - union { - struct { - uint32_t reg_osd_pb_x_10 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_10 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_10; - - /* 0x054 : osd_pb_addr_11 */ - union { - struct { - uint32_t reg_osd_pb_x_11 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_11 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_11; - - /* 0x058 : osd_pb_addr_12 */ - union { - struct { - uint32_t reg_osd_pb_x_12 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_12 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_12; - - /* 0x05C : osd_pb_addr_13 */ - union { - struct { - uint32_t reg_osd_pb_x_13 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_13 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_13; - - /* 0x060 : osd_pb_addr_14 */ - union { - struct { - uint32_t reg_osd_pb_x_14 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_14 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_14; - - /* 0x064 : osd_pb_addr_15 */ - union { - struct { - uint32_t reg_osd_pb_x_15 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_15 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_15; - - /* 0x068 : osd_pb_addr_16 */ - union { - struct { - uint32_t reg_osd_pb_x_16 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_16 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_16; - - /* 0x06C : osd_pb_addr_17 */ - union { - struct { - uint32_t reg_osd_pb_x_17 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_17 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_17; - - /* 0x070 : osd_pb_addr_18 */ - union { - struct { - uint32_t reg_osd_pb_x_18 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_18 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_18; - - /* 0x074 : osd_pb_addr_19 */ - union { - struct { - uint32_t reg_osd_pb_x_19 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_19 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_19; - - /* 0x078 : osd_pb_addr_1a */ - union { - struct { - uint32_t reg_osd_pb_x_1a : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_1a : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_1a; - - /* 0x07C : osd_pb_addr_1b */ - union { - struct { - uint32_t reg_osd_pb_x_1b : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_1b : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_1b; - - /* 0x080 : osd_pb_addr_1c */ - union { - struct { - uint32_t reg_osd_pb_x_1c : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_1c : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_1c; - - /* 0x084 : osd_pb_addr_1d */ - union { - struct { - uint32_t reg_osd_pb_x_1d : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_1d : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_1d; - - /* 0x088 : osd_pb_addr_1e */ - union { - struct { - uint32_t reg_osd_pb_x_1e : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_1e : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_1e; - - /* 0x08C : osd_pb_addr_1f */ - union { - struct { - uint32_t reg_osd_pb_x_1f : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_1f : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_1f; -}; - -typedef volatile struct osd_pb_reg osd_pb_reg_t; - -#endif /* __OSD_PB_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/osd_probe_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/osd_probe_reg.h deleted file mode 100644 index e9db19a3fc..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/osd_probe_reg.h +++ /dev/null @@ -1,913 +0,0 @@ -/** - ****************************************************************************** - * @file osd_probe_reg.h - * @version V1.0 - * @date 2021-03-30 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __OSD_PROBE_REG_H__ -#define __OSD_PROBE_REG_H__ - -#include "bl808.h" - -/* 0x000 : osd_pb_ctrl_reg */ -#define OSD_PB_CTRL_REG_OFFSET (0x000) -#define OSD_PB_REG_OSD_PB_LUMA_TH OSD_PB_REG_OSD_PB_LUMA_TH -#define OSD_PB_REG_OSD_PB_LUMA_TH_POS (0U) -#define OSD_PB_REG_OSD_PB_LUMA_TH_LEN (8U) -#define OSD_PB_REG_OSD_PB_LUMA_TH_MSK (((1U << OSD_PB_REG_OSD_PB_LUMA_TH_LEN) - 1) << OSD_PB_REG_OSD_PB_LUMA_TH_POS) -#define OSD_PB_REG_OSD_PB_LUMA_TH_UMSK (~(((1U << OSD_PB_REG_OSD_PB_LUMA_TH_LEN) - 1) << OSD_PB_REG_OSD_PB_LUMA_TH_POS)) -#define OSD_PB_STS_OSD_PB_W_CNT_R OSD_PB_STS_OSD_PB_W_CNT_R -#define OSD_PB_STS_OSD_PB_W_CNT_R_POS (8U) -#define OSD_PB_STS_OSD_PB_W_CNT_R_LEN (5U) -#define OSD_PB_STS_OSD_PB_W_CNT_R_MSK (((1U << OSD_PB_STS_OSD_PB_W_CNT_R_LEN) - 1) << OSD_PB_STS_OSD_PB_W_CNT_R_POS) -#define OSD_PB_STS_OSD_PB_W_CNT_R_UMSK (~(((1U << OSD_PB_STS_OSD_PB_W_CNT_R_LEN) - 1) << OSD_PB_STS_OSD_PB_W_CNT_R_POS)) -#define OSD_PB_STS_OSD_PB_IDX_R OSD_PB_STS_OSD_PB_IDX_R -#define OSD_PB_STS_OSD_PB_IDX_R_POS (15U) -#define OSD_PB_STS_OSD_PB_IDX_R_LEN (1U) -#define OSD_PB_STS_OSD_PB_IDX_R_MSK (((1U << OSD_PB_STS_OSD_PB_IDX_R_LEN) - 1) << OSD_PB_STS_OSD_PB_IDX_R_POS) -#define OSD_PB_STS_OSD_PB_IDX_R_UMSK (~(((1U << OSD_PB_STS_OSD_PB_IDX_R_LEN) - 1) << OSD_PB_STS_OSD_PB_IDX_R_POS)) - -/* 0x004 : osd_pb_result0 */ -#define OSD_PB_RESULT0_OFFSET (0x004) -#define OSD_PB_STS_OSD_PB_RESULT_0_R OSD_PB_STS_OSD_PB_RESULT_0_R -#define OSD_PB_STS_OSD_PB_RESULT_0_R_POS (0U) -#define OSD_PB_STS_OSD_PB_RESULT_0_R_LEN (32U) -#define OSD_PB_STS_OSD_PB_RESULT_0_R_MSK (((1U << OSD_PB_STS_OSD_PB_RESULT_0_R_LEN) - 1) << OSD_PB_STS_OSD_PB_RESULT_0_R_POS) -#define OSD_PB_STS_OSD_PB_RESULT_0_R_UMSK (~(((1U << OSD_PB_STS_OSD_PB_RESULT_0_R_LEN) - 1) << OSD_PB_STS_OSD_PB_RESULT_0_R_POS)) - -/* 0x008 : osd_pb_result1 */ -#define OSD_PB_RESULT1_OFFSET (0x008) -#define OSD_PB_STS_OSD_PB_RESULT_1_R OSD_PB_STS_OSD_PB_RESULT_1_R -#define OSD_PB_STS_OSD_PB_RESULT_1_R_POS (0U) -#define OSD_PB_STS_OSD_PB_RESULT_1_R_LEN (32U) -#define OSD_PB_STS_OSD_PB_RESULT_1_R_MSK (((1U << OSD_PB_STS_OSD_PB_RESULT_1_R_LEN) - 1) << OSD_PB_STS_OSD_PB_RESULT_1_R_POS) -#define OSD_PB_STS_OSD_PB_RESULT_1_R_UMSK (~(((1U << OSD_PB_STS_OSD_PB_RESULT_1_R_LEN) - 1) << OSD_PB_STS_OSD_PB_RESULT_1_R_POS)) - -/* 0x010 : osd_pb_addr_00 */ -#define OSD_PB_ADDR_00_OFFSET (0x010) -#define OSD_PB_REG_OSD_PB_X_00 OSD_PB_REG_OSD_PB_X_00 -#define OSD_PB_REG_OSD_PB_X_00_POS (0U) -#define OSD_PB_REG_OSD_PB_X_00_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_00_MSK (((1U << OSD_PB_REG_OSD_PB_X_00_LEN) - 1) << OSD_PB_REG_OSD_PB_X_00_POS) -#define OSD_PB_REG_OSD_PB_X_00_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_00_LEN) - 1) << OSD_PB_REG_OSD_PB_X_00_POS)) -#define OSD_PB_REG_OSD_PB_Y_00 OSD_PB_REG_OSD_PB_Y_00 -#define OSD_PB_REG_OSD_PB_Y_00_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_00_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_00_MSK (((1U << OSD_PB_REG_OSD_PB_Y_00_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_00_POS) -#define OSD_PB_REG_OSD_PB_Y_00_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_00_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_00_POS)) - -/* 0x014 : osd_pb_addr_01 */ -#define OSD_PB_ADDR_01_OFFSET (0x014) -#define OSD_PB_REG_OSD_PB_X_01 OSD_PB_REG_OSD_PB_X_01 -#define OSD_PB_REG_OSD_PB_X_01_POS (0U) -#define OSD_PB_REG_OSD_PB_X_01_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_01_MSK (((1U << OSD_PB_REG_OSD_PB_X_01_LEN) - 1) << OSD_PB_REG_OSD_PB_X_01_POS) -#define OSD_PB_REG_OSD_PB_X_01_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_01_LEN) - 1) << OSD_PB_REG_OSD_PB_X_01_POS)) -#define OSD_PB_REG_OSD_PB_Y_01 OSD_PB_REG_OSD_PB_Y_01 -#define OSD_PB_REG_OSD_PB_Y_01_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_01_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_01_MSK (((1U << OSD_PB_REG_OSD_PB_Y_01_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_01_POS) -#define OSD_PB_REG_OSD_PB_Y_01_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_01_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_01_POS)) - -/* 0x018 : osd_pb_addr_02 */ -#define OSD_PB_ADDR_02_OFFSET (0x018) -#define OSD_PB_REG_OSD_PB_X_02 OSD_PB_REG_OSD_PB_X_02 -#define OSD_PB_REG_OSD_PB_X_02_POS (0U) -#define OSD_PB_REG_OSD_PB_X_02_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_02_MSK (((1U << OSD_PB_REG_OSD_PB_X_02_LEN) - 1) << OSD_PB_REG_OSD_PB_X_02_POS) -#define OSD_PB_REG_OSD_PB_X_02_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_02_LEN) - 1) << OSD_PB_REG_OSD_PB_X_02_POS)) -#define OSD_PB_REG_OSD_PB_Y_02 OSD_PB_REG_OSD_PB_Y_02 -#define OSD_PB_REG_OSD_PB_Y_02_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_02_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_02_MSK (((1U << OSD_PB_REG_OSD_PB_Y_02_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_02_POS) -#define OSD_PB_REG_OSD_PB_Y_02_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_02_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_02_POS)) - -/* 0x01C : osd_pb_addr_03 */ -#define OSD_PB_ADDR_03_OFFSET (0x01C) -#define OSD_PB_REG_OSD_PB_X_03 OSD_PB_REG_OSD_PB_X_03 -#define OSD_PB_REG_OSD_PB_X_03_POS (0U) -#define OSD_PB_REG_OSD_PB_X_03_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_03_MSK (((1U << OSD_PB_REG_OSD_PB_X_03_LEN) - 1) << OSD_PB_REG_OSD_PB_X_03_POS) -#define OSD_PB_REG_OSD_PB_X_03_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_03_LEN) - 1) << OSD_PB_REG_OSD_PB_X_03_POS)) -#define OSD_PB_REG_OSD_PB_Y_03 OSD_PB_REG_OSD_PB_Y_03 -#define OSD_PB_REG_OSD_PB_Y_03_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_03_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_03_MSK (((1U << OSD_PB_REG_OSD_PB_Y_03_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_03_POS) -#define OSD_PB_REG_OSD_PB_Y_03_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_03_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_03_POS)) - -/* 0x020 : osd_pb_addr_04 */ -#define OSD_PB_ADDR_04_OFFSET (0x020) -#define OSD_PB_REG_OSD_PB_X_04 OSD_PB_REG_OSD_PB_X_04 -#define OSD_PB_REG_OSD_PB_X_04_POS (0U) -#define OSD_PB_REG_OSD_PB_X_04_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_04_MSK (((1U << OSD_PB_REG_OSD_PB_X_04_LEN) - 1) << OSD_PB_REG_OSD_PB_X_04_POS) -#define OSD_PB_REG_OSD_PB_X_04_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_04_LEN) - 1) << OSD_PB_REG_OSD_PB_X_04_POS)) -#define OSD_PB_REG_OSD_PB_Y_04 OSD_PB_REG_OSD_PB_Y_04 -#define OSD_PB_REG_OSD_PB_Y_04_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_04_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_04_MSK (((1U << OSD_PB_REG_OSD_PB_Y_04_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_04_POS) -#define OSD_PB_REG_OSD_PB_Y_04_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_04_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_04_POS)) - -/* 0x024 : osd_pb_addr_05 */ -#define OSD_PB_ADDR_05_OFFSET (0x024) -#define OSD_PB_REG_OSD_PB_X_05 OSD_PB_REG_OSD_PB_X_05 -#define OSD_PB_REG_OSD_PB_X_05_POS (0U) -#define OSD_PB_REG_OSD_PB_X_05_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_05_MSK (((1U << OSD_PB_REG_OSD_PB_X_05_LEN) - 1) << OSD_PB_REG_OSD_PB_X_05_POS) -#define OSD_PB_REG_OSD_PB_X_05_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_05_LEN) - 1) << OSD_PB_REG_OSD_PB_X_05_POS)) -#define OSD_PB_REG_OSD_PB_Y_05 OSD_PB_REG_OSD_PB_Y_05 -#define OSD_PB_REG_OSD_PB_Y_05_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_05_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_05_MSK (((1U << OSD_PB_REG_OSD_PB_Y_05_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_05_POS) -#define OSD_PB_REG_OSD_PB_Y_05_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_05_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_05_POS)) - -/* 0x028 : osd_pb_addr_06 */ -#define OSD_PB_ADDR_06_OFFSET (0x028) -#define OSD_PB_REG_OSD_PB_X_06 OSD_PB_REG_OSD_PB_X_06 -#define OSD_PB_REG_OSD_PB_X_06_POS (0U) -#define OSD_PB_REG_OSD_PB_X_06_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_06_MSK (((1U << OSD_PB_REG_OSD_PB_X_06_LEN) - 1) << OSD_PB_REG_OSD_PB_X_06_POS) -#define OSD_PB_REG_OSD_PB_X_06_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_06_LEN) - 1) << OSD_PB_REG_OSD_PB_X_06_POS)) -#define OSD_PB_REG_OSD_PB_Y_06 OSD_PB_REG_OSD_PB_Y_06 -#define OSD_PB_REG_OSD_PB_Y_06_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_06_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_06_MSK (((1U << OSD_PB_REG_OSD_PB_Y_06_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_06_POS) -#define OSD_PB_REG_OSD_PB_Y_06_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_06_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_06_POS)) - -/* 0x02C : osd_pb_addr_07 */ -#define OSD_PB_ADDR_07_OFFSET (0x02C) -#define OSD_PB_REG_OSD_PB_X_07 OSD_PB_REG_OSD_PB_X_07 -#define OSD_PB_REG_OSD_PB_X_07_POS (0U) -#define OSD_PB_REG_OSD_PB_X_07_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_07_MSK (((1U << OSD_PB_REG_OSD_PB_X_07_LEN) - 1) << OSD_PB_REG_OSD_PB_X_07_POS) -#define OSD_PB_REG_OSD_PB_X_07_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_07_LEN) - 1) << OSD_PB_REG_OSD_PB_X_07_POS)) -#define OSD_PB_REG_OSD_PB_Y_07 OSD_PB_REG_OSD_PB_Y_07 -#define OSD_PB_REG_OSD_PB_Y_07_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_07_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_07_MSK (((1U << OSD_PB_REG_OSD_PB_Y_07_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_07_POS) -#define OSD_PB_REG_OSD_PB_Y_07_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_07_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_07_POS)) - -/* 0x030 : osd_pb_addr_08 */ -#define OSD_PB_ADDR_08_OFFSET (0x030) -#define OSD_PB_REG_OSD_PB_X_08 OSD_PB_REG_OSD_PB_X_08 -#define OSD_PB_REG_OSD_PB_X_08_POS (0U) -#define OSD_PB_REG_OSD_PB_X_08_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_08_MSK (((1U << OSD_PB_REG_OSD_PB_X_08_LEN) - 1) << OSD_PB_REG_OSD_PB_X_08_POS) -#define OSD_PB_REG_OSD_PB_X_08_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_08_LEN) - 1) << OSD_PB_REG_OSD_PB_X_08_POS)) -#define OSD_PB_REG_OSD_PB_Y_08 OSD_PB_REG_OSD_PB_Y_08 -#define OSD_PB_REG_OSD_PB_Y_08_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_08_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_08_MSK (((1U << OSD_PB_REG_OSD_PB_Y_08_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_08_POS) -#define OSD_PB_REG_OSD_PB_Y_08_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_08_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_08_POS)) - -/* 0x034 : osd_pb_addr_09 */ -#define OSD_PB_ADDR_09_OFFSET (0x034) -#define OSD_PB_REG_OSD_PB_X_09 OSD_PB_REG_OSD_PB_X_09 -#define OSD_PB_REG_OSD_PB_X_09_POS (0U) -#define OSD_PB_REG_OSD_PB_X_09_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_09_MSK (((1U << OSD_PB_REG_OSD_PB_X_09_LEN) - 1) << OSD_PB_REG_OSD_PB_X_09_POS) -#define OSD_PB_REG_OSD_PB_X_09_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_09_LEN) - 1) << OSD_PB_REG_OSD_PB_X_09_POS)) -#define OSD_PB_REG_OSD_PB_Y_09 OSD_PB_REG_OSD_PB_Y_09 -#define OSD_PB_REG_OSD_PB_Y_09_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_09_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_09_MSK (((1U << OSD_PB_REG_OSD_PB_Y_09_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_09_POS) -#define OSD_PB_REG_OSD_PB_Y_09_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_09_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_09_POS)) - -/* 0x038 : osd_pb_addr_0a */ -#define OSD_PB_ADDR_0A_OFFSET (0x038) -#define OSD_PB_REG_OSD_PB_X_0A OSD_PB_REG_OSD_PB_X_0A -#define OSD_PB_REG_OSD_PB_X_0A_POS (0U) -#define OSD_PB_REG_OSD_PB_X_0A_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_0A_MSK (((1U << OSD_PB_REG_OSD_PB_X_0A_LEN) - 1) << OSD_PB_REG_OSD_PB_X_0A_POS) -#define OSD_PB_REG_OSD_PB_X_0A_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_0A_LEN) - 1) << OSD_PB_REG_OSD_PB_X_0A_POS)) -#define OSD_PB_REG_OSD_PB_Y_0A OSD_PB_REG_OSD_PB_Y_0A -#define OSD_PB_REG_OSD_PB_Y_0A_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_0A_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_0A_MSK (((1U << OSD_PB_REG_OSD_PB_Y_0A_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_0A_POS) -#define OSD_PB_REG_OSD_PB_Y_0A_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_0A_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_0A_POS)) - -/* 0x03C : osd_pb_addr_0b */ -#define OSD_PB_ADDR_0B_OFFSET (0x03C) -#define OSD_PB_REG_OSD_PB_X_0B OSD_PB_REG_OSD_PB_X_0B -#define OSD_PB_REG_OSD_PB_X_0B_POS (0U) -#define OSD_PB_REG_OSD_PB_X_0B_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_0B_MSK (((1U << OSD_PB_REG_OSD_PB_X_0B_LEN) - 1) << OSD_PB_REG_OSD_PB_X_0B_POS) -#define OSD_PB_REG_OSD_PB_X_0B_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_0B_LEN) - 1) << OSD_PB_REG_OSD_PB_X_0B_POS)) -#define OSD_PB_REG_OSD_PB_Y_0B OSD_PB_REG_OSD_PB_Y_0B -#define OSD_PB_REG_OSD_PB_Y_0B_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_0B_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_0B_MSK (((1U << OSD_PB_REG_OSD_PB_Y_0B_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_0B_POS) -#define OSD_PB_REG_OSD_PB_Y_0B_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_0B_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_0B_POS)) - -/* 0x040 : osd_pb_addr_0c */ -#define OSD_PB_ADDR_0C_OFFSET (0x040) -#define OSD_PB_REG_OSD_PB_X_0C OSD_PB_REG_OSD_PB_X_0C -#define OSD_PB_REG_OSD_PB_X_0C_POS (0U) -#define OSD_PB_REG_OSD_PB_X_0C_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_0C_MSK (((1U << OSD_PB_REG_OSD_PB_X_0C_LEN) - 1) << OSD_PB_REG_OSD_PB_X_0C_POS) -#define OSD_PB_REG_OSD_PB_X_0C_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_0C_LEN) - 1) << OSD_PB_REG_OSD_PB_X_0C_POS)) -#define OSD_PB_REG_OSD_PB_Y_0C OSD_PB_REG_OSD_PB_Y_0C -#define OSD_PB_REG_OSD_PB_Y_0C_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_0C_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_0C_MSK (((1U << OSD_PB_REG_OSD_PB_Y_0C_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_0C_POS) -#define OSD_PB_REG_OSD_PB_Y_0C_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_0C_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_0C_POS)) - -/* 0x044 : osd_pb_addr_0d */ -#define OSD_PB_ADDR_0D_OFFSET (0x044) -#define OSD_PB_REG_OSD_PB_X_0D OSD_PB_REG_OSD_PB_X_0D -#define OSD_PB_REG_OSD_PB_X_0D_POS (0U) -#define OSD_PB_REG_OSD_PB_X_0D_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_0D_MSK (((1U << OSD_PB_REG_OSD_PB_X_0D_LEN) - 1) << OSD_PB_REG_OSD_PB_X_0D_POS) -#define OSD_PB_REG_OSD_PB_X_0D_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_0D_LEN) - 1) << OSD_PB_REG_OSD_PB_X_0D_POS)) -#define OSD_PB_REG_OSD_PB_Y_0D OSD_PB_REG_OSD_PB_Y_0D -#define OSD_PB_REG_OSD_PB_Y_0D_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_0D_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_0D_MSK (((1U << OSD_PB_REG_OSD_PB_Y_0D_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_0D_POS) -#define OSD_PB_REG_OSD_PB_Y_0D_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_0D_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_0D_POS)) - -/* 0x048 : osd_pb_addr_0e */ -#define OSD_PB_ADDR_0E_OFFSET (0x048) -#define OSD_PB_REG_OSD_PB_X_0E OSD_PB_REG_OSD_PB_X_0E -#define OSD_PB_REG_OSD_PB_X_0E_POS (0U) -#define OSD_PB_REG_OSD_PB_X_0E_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_0E_MSK (((1U << OSD_PB_REG_OSD_PB_X_0E_LEN) - 1) << OSD_PB_REG_OSD_PB_X_0E_POS) -#define OSD_PB_REG_OSD_PB_X_0E_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_0E_LEN) - 1) << OSD_PB_REG_OSD_PB_X_0E_POS)) -#define OSD_PB_REG_OSD_PB_Y_0E OSD_PB_REG_OSD_PB_Y_0E -#define OSD_PB_REG_OSD_PB_Y_0E_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_0E_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_0E_MSK (((1U << OSD_PB_REG_OSD_PB_Y_0E_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_0E_POS) -#define OSD_PB_REG_OSD_PB_Y_0E_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_0E_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_0E_POS)) - -/* 0x04C : osd_pb_addr_0f */ -#define OSD_PB_ADDR_0F_OFFSET (0x04C) -#define OSD_PB_REG_OSD_PB_X_0F OSD_PB_REG_OSD_PB_X_0F -#define OSD_PB_REG_OSD_PB_X_0F_POS (0U) -#define OSD_PB_REG_OSD_PB_X_0F_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_0F_MSK (((1U << OSD_PB_REG_OSD_PB_X_0F_LEN) - 1) << OSD_PB_REG_OSD_PB_X_0F_POS) -#define OSD_PB_REG_OSD_PB_X_0F_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_0F_LEN) - 1) << OSD_PB_REG_OSD_PB_X_0F_POS)) -#define OSD_PB_REG_OSD_PB_Y_0F OSD_PB_REG_OSD_PB_Y_0F -#define OSD_PB_REG_OSD_PB_Y_0F_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_0F_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_0F_MSK (((1U << OSD_PB_REG_OSD_PB_Y_0F_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_0F_POS) -#define OSD_PB_REG_OSD_PB_Y_0F_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_0F_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_0F_POS)) - -/* 0x050 : osd_pb_addr_10 */ -#define OSD_PB_ADDR_10_OFFSET (0x050) -#define OSD_PB_REG_OSD_PB_X_10 OSD_PB_REG_OSD_PB_X_10 -#define OSD_PB_REG_OSD_PB_X_10_POS (0U) -#define OSD_PB_REG_OSD_PB_X_10_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_10_MSK (((1U << OSD_PB_REG_OSD_PB_X_10_LEN) - 1) << OSD_PB_REG_OSD_PB_X_10_POS) -#define OSD_PB_REG_OSD_PB_X_10_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_10_LEN) - 1) << OSD_PB_REG_OSD_PB_X_10_POS)) -#define OSD_PB_REG_OSD_PB_Y_10 OSD_PB_REG_OSD_PB_Y_10 -#define OSD_PB_REG_OSD_PB_Y_10_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_10_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_10_MSK (((1U << OSD_PB_REG_OSD_PB_Y_10_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_10_POS) -#define OSD_PB_REG_OSD_PB_Y_10_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_10_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_10_POS)) - -/* 0x054 : osd_pb_addr_11 */ -#define OSD_PB_ADDR_11_OFFSET (0x054) -#define OSD_PB_REG_OSD_PB_X_11 OSD_PB_REG_OSD_PB_X_11 -#define OSD_PB_REG_OSD_PB_X_11_POS (0U) -#define OSD_PB_REG_OSD_PB_X_11_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_11_MSK (((1U << OSD_PB_REG_OSD_PB_X_11_LEN) - 1) << OSD_PB_REG_OSD_PB_X_11_POS) -#define OSD_PB_REG_OSD_PB_X_11_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_11_LEN) - 1) << OSD_PB_REG_OSD_PB_X_11_POS)) -#define OSD_PB_REG_OSD_PB_Y_11 OSD_PB_REG_OSD_PB_Y_11 -#define OSD_PB_REG_OSD_PB_Y_11_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_11_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_11_MSK (((1U << OSD_PB_REG_OSD_PB_Y_11_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_11_POS) -#define OSD_PB_REG_OSD_PB_Y_11_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_11_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_11_POS)) - -/* 0x058 : osd_pb_addr_12 */ -#define OSD_PB_ADDR_12_OFFSET (0x058) -#define OSD_PB_REG_OSD_PB_X_12 OSD_PB_REG_OSD_PB_X_12 -#define OSD_PB_REG_OSD_PB_X_12_POS (0U) -#define OSD_PB_REG_OSD_PB_X_12_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_12_MSK (((1U << OSD_PB_REG_OSD_PB_X_12_LEN) - 1) << OSD_PB_REG_OSD_PB_X_12_POS) -#define OSD_PB_REG_OSD_PB_X_12_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_12_LEN) - 1) << OSD_PB_REG_OSD_PB_X_12_POS)) -#define OSD_PB_REG_OSD_PB_Y_12 OSD_PB_REG_OSD_PB_Y_12 -#define OSD_PB_REG_OSD_PB_Y_12_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_12_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_12_MSK (((1U << OSD_PB_REG_OSD_PB_Y_12_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_12_POS) -#define OSD_PB_REG_OSD_PB_Y_12_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_12_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_12_POS)) - -/* 0x05C : osd_pb_addr_13 */ -#define OSD_PB_ADDR_13_OFFSET (0x05C) -#define OSD_PB_REG_OSD_PB_X_13 OSD_PB_REG_OSD_PB_X_13 -#define OSD_PB_REG_OSD_PB_X_13_POS (0U) -#define OSD_PB_REG_OSD_PB_X_13_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_13_MSK (((1U << OSD_PB_REG_OSD_PB_X_13_LEN) - 1) << OSD_PB_REG_OSD_PB_X_13_POS) -#define OSD_PB_REG_OSD_PB_X_13_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_13_LEN) - 1) << OSD_PB_REG_OSD_PB_X_13_POS)) -#define OSD_PB_REG_OSD_PB_Y_13 OSD_PB_REG_OSD_PB_Y_13 -#define OSD_PB_REG_OSD_PB_Y_13_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_13_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_13_MSK (((1U << OSD_PB_REG_OSD_PB_Y_13_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_13_POS) -#define OSD_PB_REG_OSD_PB_Y_13_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_13_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_13_POS)) - -/* 0x060 : osd_pb_addr_14 */ -#define OSD_PB_ADDR_14_OFFSET (0x060) -#define OSD_PB_REG_OSD_PB_X_14 OSD_PB_REG_OSD_PB_X_14 -#define OSD_PB_REG_OSD_PB_X_14_POS (0U) -#define OSD_PB_REG_OSD_PB_X_14_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_14_MSK (((1U << OSD_PB_REG_OSD_PB_X_14_LEN) - 1) << OSD_PB_REG_OSD_PB_X_14_POS) -#define OSD_PB_REG_OSD_PB_X_14_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_14_LEN) - 1) << OSD_PB_REG_OSD_PB_X_14_POS)) -#define OSD_PB_REG_OSD_PB_Y_14 OSD_PB_REG_OSD_PB_Y_14 -#define OSD_PB_REG_OSD_PB_Y_14_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_14_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_14_MSK (((1U << OSD_PB_REG_OSD_PB_Y_14_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_14_POS) -#define OSD_PB_REG_OSD_PB_Y_14_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_14_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_14_POS)) - -/* 0x064 : osd_pb_addr_15 */ -#define OSD_PB_ADDR_15_OFFSET (0x064) -#define OSD_PB_REG_OSD_PB_X_15 OSD_PB_REG_OSD_PB_X_15 -#define OSD_PB_REG_OSD_PB_X_15_POS (0U) -#define OSD_PB_REG_OSD_PB_X_15_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_15_MSK (((1U << OSD_PB_REG_OSD_PB_X_15_LEN) - 1) << OSD_PB_REG_OSD_PB_X_15_POS) -#define OSD_PB_REG_OSD_PB_X_15_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_15_LEN) - 1) << OSD_PB_REG_OSD_PB_X_15_POS)) -#define OSD_PB_REG_OSD_PB_Y_15 OSD_PB_REG_OSD_PB_Y_15 -#define OSD_PB_REG_OSD_PB_Y_15_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_15_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_15_MSK (((1U << OSD_PB_REG_OSD_PB_Y_15_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_15_POS) -#define OSD_PB_REG_OSD_PB_Y_15_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_15_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_15_POS)) - -/* 0x068 : osd_pb_addr_16 */ -#define OSD_PB_ADDR_16_OFFSET (0x068) -#define OSD_PB_REG_OSD_PB_X_16 OSD_PB_REG_OSD_PB_X_16 -#define OSD_PB_REG_OSD_PB_X_16_POS (0U) -#define OSD_PB_REG_OSD_PB_X_16_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_16_MSK (((1U << OSD_PB_REG_OSD_PB_X_16_LEN) - 1) << OSD_PB_REG_OSD_PB_X_16_POS) -#define OSD_PB_REG_OSD_PB_X_16_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_16_LEN) - 1) << OSD_PB_REG_OSD_PB_X_16_POS)) -#define OSD_PB_REG_OSD_PB_Y_16 OSD_PB_REG_OSD_PB_Y_16 -#define OSD_PB_REG_OSD_PB_Y_16_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_16_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_16_MSK (((1U << OSD_PB_REG_OSD_PB_Y_16_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_16_POS) -#define OSD_PB_REG_OSD_PB_Y_16_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_16_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_16_POS)) - -/* 0x06C : osd_pb_addr_17 */ -#define OSD_PB_ADDR_17_OFFSET (0x06C) -#define OSD_PB_REG_OSD_PB_X_17 OSD_PB_REG_OSD_PB_X_17 -#define OSD_PB_REG_OSD_PB_X_17_POS (0U) -#define OSD_PB_REG_OSD_PB_X_17_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_17_MSK (((1U << OSD_PB_REG_OSD_PB_X_17_LEN) - 1) << OSD_PB_REG_OSD_PB_X_17_POS) -#define OSD_PB_REG_OSD_PB_X_17_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_17_LEN) - 1) << OSD_PB_REG_OSD_PB_X_17_POS)) -#define OSD_PB_REG_OSD_PB_Y_17 OSD_PB_REG_OSD_PB_Y_17 -#define OSD_PB_REG_OSD_PB_Y_17_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_17_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_17_MSK (((1U << OSD_PB_REG_OSD_PB_Y_17_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_17_POS) -#define OSD_PB_REG_OSD_PB_Y_17_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_17_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_17_POS)) - -/* 0x070 : osd_pb_addr_18 */ -#define OSD_PB_ADDR_18_OFFSET (0x070) -#define OSD_PB_REG_OSD_PB_X_18 OSD_PB_REG_OSD_PB_X_18 -#define OSD_PB_REG_OSD_PB_X_18_POS (0U) -#define OSD_PB_REG_OSD_PB_X_18_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_18_MSK (((1U << OSD_PB_REG_OSD_PB_X_18_LEN) - 1) << OSD_PB_REG_OSD_PB_X_18_POS) -#define OSD_PB_REG_OSD_PB_X_18_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_18_LEN) - 1) << OSD_PB_REG_OSD_PB_X_18_POS)) -#define OSD_PB_REG_OSD_PB_Y_18 OSD_PB_REG_OSD_PB_Y_18 -#define OSD_PB_REG_OSD_PB_Y_18_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_18_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_18_MSK (((1U << OSD_PB_REG_OSD_PB_Y_18_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_18_POS) -#define OSD_PB_REG_OSD_PB_Y_18_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_18_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_18_POS)) - -/* 0x074 : osd_pb_addr_19 */ -#define OSD_PB_ADDR_19_OFFSET (0x074) -#define OSD_PB_REG_OSD_PB_X_19 OSD_PB_REG_OSD_PB_X_19 -#define OSD_PB_REG_OSD_PB_X_19_POS (0U) -#define OSD_PB_REG_OSD_PB_X_19_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_19_MSK (((1U << OSD_PB_REG_OSD_PB_X_19_LEN) - 1) << OSD_PB_REG_OSD_PB_X_19_POS) -#define OSD_PB_REG_OSD_PB_X_19_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_19_LEN) - 1) << OSD_PB_REG_OSD_PB_X_19_POS)) -#define OSD_PB_REG_OSD_PB_Y_19 OSD_PB_REG_OSD_PB_Y_19 -#define OSD_PB_REG_OSD_PB_Y_19_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_19_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_19_MSK (((1U << OSD_PB_REG_OSD_PB_Y_19_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_19_POS) -#define OSD_PB_REG_OSD_PB_Y_19_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_19_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_19_POS)) - -/* 0x078 : osd_pb_addr_1a */ -#define OSD_PB_ADDR_1A_OFFSET (0x078) -#define OSD_PB_REG_OSD_PB_X_1A OSD_PB_REG_OSD_PB_X_1A -#define OSD_PB_REG_OSD_PB_X_1A_POS (0U) -#define OSD_PB_REG_OSD_PB_X_1A_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_1A_MSK (((1U << OSD_PB_REG_OSD_PB_X_1A_LEN) - 1) << OSD_PB_REG_OSD_PB_X_1A_POS) -#define OSD_PB_REG_OSD_PB_X_1A_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_1A_LEN) - 1) << OSD_PB_REG_OSD_PB_X_1A_POS)) -#define OSD_PB_REG_OSD_PB_Y_1A OSD_PB_REG_OSD_PB_Y_1A -#define OSD_PB_REG_OSD_PB_Y_1A_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_1A_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_1A_MSK (((1U << OSD_PB_REG_OSD_PB_Y_1A_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_1A_POS) -#define OSD_PB_REG_OSD_PB_Y_1A_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_1A_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_1A_POS)) - -/* 0x07C : osd_pb_addr_1b */ -#define OSD_PB_ADDR_1B_OFFSET (0x07C) -#define OSD_PB_REG_OSD_PB_X_1B OSD_PB_REG_OSD_PB_X_1B -#define OSD_PB_REG_OSD_PB_X_1B_POS (0U) -#define OSD_PB_REG_OSD_PB_X_1B_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_1B_MSK (((1U << OSD_PB_REG_OSD_PB_X_1B_LEN) - 1) << OSD_PB_REG_OSD_PB_X_1B_POS) -#define OSD_PB_REG_OSD_PB_X_1B_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_1B_LEN) - 1) << OSD_PB_REG_OSD_PB_X_1B_POS)) -#define OSD_PB_REG_OSD_PB_Y_1B OSD_PB_REG_OSD_PB_Y_1B -#define OSD_PB_REG_OSD_PB_Y_1B_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_1B_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_1B_MSK (((1U << OSD_PB_REG_OSD_PB_Y_1B_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_1B_POS) -#define OSD_PB_REG_OSD_PB_Y_1B_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_1B_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_1B_POS)) - -/* 0x080 : osd_pb_addr_1c */ -#define OSD_PB_ADDR_1C_OFFSET (0x080) -#define OSD_PB_REG_OSD_PB_X_1C OSD_PB_REG_OSD_PB_X_1C -#define OSD_PB_REG_OSD_PB_X_1C_POS (0U) -#define OSD_PB_REG_OSD_PB_X_1C_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_1C_MSK (((1U << OSD_PB_REG_OSD_PB_X_1C_LEN) - 1) << OSD_PB_REG_OSD_PB_X_1C_POS) -#define OSD_PB_REG_OSD_PB_X_1C_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_1C_LEN) - 1) << OSD_PB_REG_OSD_PB_X_1C_POS)) -#define OSD_PB_REG_OSD_PB_Y_1C OSD_PB_REG_OSD_PB_Y_1C -#define OSD_PB_REG_OSD_PB_Y_1C_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_1C_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_1C_MSK (((1U << OSD_PB_REG_OSD_PB_Y_1C_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_1C_POS) -#define OSD_PB_REG_OSD_PB_Y_1C_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_1C_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_1C_POS)) - -/* 0x084 : osd_pb_addr_1d */ -#define OSD_PB_ADDR_1D_OFFSET (0x084) -#define OSD_PB_REG_OSD_PB_X_1D OSD_PB_REG_OSD_PB_X_1D -#define OSD_PB_REG_OSD_PB_X_1D_POS (0U) -#define OSD_PB_REG_OSD_PB_X_1D_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_1D_MSK (((1U << OSD_PB_REG_OSD_PB_X_1D_LEN) - 1) << OSD_PB_REG_OSD_PB_X_1D_POS) -#define OSD_PB_REG_OSD_PB_X_1D_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_1D_LEN) - 1) << OSD_PB_REG_OSD_PB_X_1D_POS)) -#define OSD_PB_REG_OSD_PB_Y_1D OSD_PB_REG_OSD_PB_Y_1D -#define OSD_PB_REG_OSD_PB_Y_1D_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_1D_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_1D_MSK (((1U << OSD_PB_REG_OSD_PB_Y_1D_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_1D_POS) -#define OSD_PB_REG_OSD_PB_Y_1D_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_1D_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_1D_POS)) - -/* 0x088 : osd_pb_addr_1e */ -#define OSD_PB_ADDR_1E_OFFSET (0x088) -#define OSD_PB_REG_OSD_PB_X_1E OSD_PB_REG_OSD_PB_X_1E -#define OSD_PB_REG_OSD_PB_X_1E_POS (0U) -#define OSD_PB_REG_OSD_PB_X_1E_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_1E_MSK (((1U << OSD_PB_REG_OSD_PB_X_1E_LEN) - 1) << OSD_PB_REG_OSD_PB_X_1E_POS) -#define OSD_PB_REG_OSD_PB_X_1E_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_1E_LEN) - 1) << OSD_PB_REG_OSD_PB_X_1E_POS)) -#define OSD_PB_REG_OSD_PB_Y_1E OSD_PB_REG_OSD_PB_Y_1E -#define OSD_PB_REG_OSD_PB_Y_1E_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_1E_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_1E_MSK (((1U << OSD_PB_REG_OSD_PB_Y_1E_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_1E_POS) -#define OSD_PB_REG_OSD_PB_Y_1E_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_1E_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_1E_POS)) - -/* 0x08C : osd_pb_addr_1f */ -#define OSD_PB_ADDR_1F_OFFSET (0x08C) -#define OSD_PB_REG_OSD_PB_X_1F OSD_PB_REG_OSD_PB_X_1F -#define OSD_PB_REG_OSD_PB_X_1F_POS (0U) -#define OSD_PB_REG_OSD_PB_X_1F_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_1F_MSK (((1U << OSD_PB_REG_OSD_PB_X_1F_LEN) - 1) << OSD_PB_REG_OSD_PB_X_1F_POS) -#define OSD_PB_REG_OSD_PB_X_1F_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_1F_LEN) - 1) << OSD_PB_REG_OSD_PB_X_1F_POS)) -#define OSD_PB_REG_OSD_PB_Y_1F OSD_PB_REG_OSD_PB_Y_1F -#define OSD_PB_REG_OSD_PB_Y_1F_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_1F_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_1F_MSK (((1U << OSD_PB_REG_OSD_PB_Y_1F_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_1F_POS) -#define OSD_PB_REG_OSD_PB_Y_1F_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_1F_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_1F_POS)) - -struct osd_pb_reg { - /* 0x000 : osd_pb_ctrl_reg */ - union { - struct - { - uint32_t reg_osd_pb_luma_th : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t sts_osd_pb_w_cnt_r : 5; /* [12: 8], r, 0x0 */ - uint32_t reserved_13_14 : 2; /* [14:13], rsvd, 0x0 */ - uint32_t sts_osd_pb_idx_r : 1; /* [ 15], r, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_ctrl_reg; - - /* 0x004 : osd_pb_result0 */ - union { - struct - { - uint32_t sts_osd_pb_result_0_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_result0; - - /* 0x008 : osd_pb_result1 */ - union { - struct - { - uint32_t sts_osd_pb_result_1_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_result1; - - /* 0xc reserved */ - uint8_t RESERVED0xc[4]; - - /* 0x010 : osd_pb_addr_00 */ - union { - struct - { - uint32_t reg_osd_pb_x_00 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_00 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_00; - - /* 0x014 : osd_pb_addr_01 */ - union { - struct - { - uint32_t reg_osd_pb_x_01 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_01 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_01; - - /* 0x018 : osd_pb_addr_02 */ - union { - struct - { - uint32_t reg_osd_pb_x_02 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_02 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_02; - - /* 0x01C : osd_pb_addr_03 */ - union { - struct - { - uint32_t reg_osd_pb_x_03 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_03 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_03; - - /* 0x020 : osd_pb_addr_04 */ - union { - struct - { - uint32_t reg_osd_pb_x_04 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_04 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_04; - - /* 0x024 : osd_pb_addr_05 */ - union { - struct - { - uint32_t reg_osd_pb_x_05 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_05 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_05; - - /* 0x028 : osd_pb_addr_06 */ - union { - struct - { - uint32_t reg_osd_pb_x_06 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_06 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_06; - - /* 0x02C : osd_pb_addr_07 */ - union { - struct - { - uint32_t reg_osd_pb_x_07 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_07 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_07; - - /* 0x030 : osd_pb_addr_08 */ - union { - struct - { - uint32_t reg_osd_pb_x_08 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_08 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_08; - - /* 0x034 : osd_pb_addr_09 */ - union { - struct - { - uint32_t reg_osd_pb_x_09 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_09 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_09; - - /* 0x038 : osd_pb_addr_0a */ - union { - struct - { - uint32_t reg_osd_pb_x_0a : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_0a : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_0a; - - /* 0x03C : osd_pb_addr_0b */ - union { - struct - { - uint32_t reg_osd_pb_x_0b : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_0b : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_0b; - - /* 0x040 : osd_pb_addr_0c */ - union { - struct - { - uint32_t reg_osd_pb_x_0c : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_0c : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_0c; - - /* 0x044 : osd_pb_addr_0d */ - union { - struct - { - uint32_t reg_osd_pb_x_0d : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_0d : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_0d; - - /* 0x048 : osd_pb_addr_0e */ - union { - struct - { - uint32_t reg_osd_pb_x_0e : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_0e : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_0e; - - /* 0x04C : osd_pb_addr_0f */ - union { - struct - { - uint32_t reg_osd_pb_x_0f : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_0f : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_0f; - - /* 0x050 : osd_pb_addr_10 */ - union { - struct - { - uint32_t reg_osd_pb_x_10 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_10 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_10; - - /* 0x054 : osd_pb_addr_11 */ - union { - struct - { - uint32_t reg_osd_pb_x_11 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_11 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_11; - - /* 0x058 : osd_pb_addr_12 */ - union { - struct - { - uint32_t reg_osd_pb_x_12 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_12 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_12; - - /* 0x05C : osd_pb_addr_13 */ - union { - struct - { - uint32_t reg_osd_pb_x_13 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_13 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_13; - - /* 0x060 : osd_pb_addr_14 */ - union { - struct - { - uint32_t reg_osd_pb_x_14 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_14 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_14; - - /* 0x064 : osd_pb_addr_15 */ - union { - struct - { - uint32_t reg_osd_pb_x_15 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_15 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_15; - - /* 0x068 : osd_pb_addr_16 */ - union { - struct - { - uint32_t reg_osd_pb_x_16 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_16 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_16; - - /* 0x06C : osd_pb_addr_17 */ - union { - struct - { - uint32_t reg_osd_pb_x_17 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_17 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_17; - - /* 0x070 : osd_pb_addr_18 */ - union { - struct - { - uint32_t reg_osd_pb_x_18 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_18 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_18; - - /* 0x074 : osd_pb_addr_19 */ - union { - struct - { - uint32_t reg_osd_pb_x_19 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_19 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_19; - - /* 0x078 : osd_pb_addr_1a */ - union { - struct - { - uint32_t reg_osd_pb_x_1a : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_1a : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_1a; - - /* 0x07C : osd_pb_addr_1b */ - union { - struct - { - uint32_t reg_osd_pb_x_1b : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_1b : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_1b; - - /* 0x080 : osd_pb_addr_1c */ - union { - struct - { - uint32_t reg_osd_pb_x_1c : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_1c : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_1c; - - /* 0x084 : osd_pb_addr_1d */ - union { - struct - { - uint32_t reg_osd_pb_x_1d : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_1d : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_1d; - - /* 0x088 : osd_pb_addr_1e */ - union { - struct - { - uint32_t reg_osd_pb_x_1e : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_1e : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_1e; - - /* 0x08C : osd_pb_addr_1f */ - union { - struct - { - uint32_t reg_osd_pb_x_1f : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_1f : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_1f; -}; - -typedef volatile struct osd_pb_reg osd_pb_reg_t; - -#endif /* __OSD_PROBE_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/pdm_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/pdm_reg.h deleted file mode 100644 index f5ad643be6..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/pdm_reg.h +++ /dev/null @@ -1,722 +0,0 @@ -/** - ****************************************************************************** - * @file pdm_reg.h - * @version V1.0 - * @date 2021-07-19 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __PDM_REG_H__ -#define __PDM_REG_H__ - -#include "bl808.h" - -/* 0xC00 : audpdm_top */ -#define PDM_AUDPDM_TOP_OFFSET (0xC00) -#define PDM_AUDIO_CKG_EN PDM_AUDIO_CKG_EN -#define PDM_AUDIO_CKG_EN_POS (0U) -#define PDM_AUDIO_CKG_EN_LEN (1U) -#define PDM_AUDIO_CKG_EN_MSK (((1U << PDM_AUDIO_CKG_EN_LEN) - 1) << PDM_AUDIO_CKG_EN_POS) -#define PDM_AUDIO_CKG_EN_UMSK (~(((1U << PDM_AUDIO_CKG_EN_LEN) - 1) << PDM_AUDIO_CKG_EN_POS)) -#define PDM_ADC_ITF_INV_SEL PDM_ADC_ITF_INV_SEL -#define PDM_ADC_ITF_INV_SEL_POS (2U) -#define PDM_ADC_ITF_INV_SEL_LEN (1U) -#define PDM_ADC_ITF_INV_SEL_MSK (((1U << PDM_ADC_ITF_INV_SEL_LEN) - 1) << PDM_ADC_ITF_INV_SEL_POS) -#define PDM_ADC_ITF_INV_SEL_UMSK (~(((1U << PDM_ADC_ITF_INV_SEL_LEN) - 1) << PDM_ADC_ITF_INV_SEL_POS)) -#define PDM_ITF_INV_SEL PDM_ITF_INV_SEL -#define PDM_ITF_INV_SEL_POS (3U) -#define PDM_ITF_INV_SEL_LEN (1U) -#define PDM_ITF_INV_SEL_MSK (((1U << PDM_ITF_INV_SEL_LEN) - 1) << PDM_ITF_INV_SEL_POS) -#define PDM_ITF_INV_SEL_UMSK (~(((1U << PDM_ITF_INV_SEL_LEN) - 1) << PDM_ITF_INV_SEL_POS)) -#define PDM_ADC_RATE PDM_ADC_RATE -#define PDM_ADC_RATE_POS (28U) -#define PDM_ADC_RATE_LEN (3U) -#define PDM_ADC_RATE_MSK (((1U << PDM_ADC_RATE_LEN) - 1) << PDM_ADC_RATE_POS) -#define PDM_ADC_RATE_UMSK (~(((1U << PDM_ADC_RATE_LEN) - 1) << PDM_ADC_RATE_POS)) - -/* 0xC04 : audpdm_itf */ -#define PDM_AUDPDM_ITF_OFFSET (0xC04) -#define PDM_ADC_0_EN PDM_ADC_0_EN -#define PDM_ADC_0_EN_POS (0U) -#define PDM_ADC_0_EN_LEN (1U) -#define PDM_ADC_0_EN_MSK (((1U << PDM_ADC_0_EN_LEN) - 1) << PDM_ADC_0_EN_POS) -#define PDM_ADC_0_EN_UMSK (~(((1U << PDM_ADC_0_EN_LEN) - 1) << PDM_ADC_0_EN_POS)) -#define PDM_ADC_1_EN PDM_ADC_1_EN -#define PDM_ADC_1_EN_POS (1U) -#define PDM_ADC_1_EN_LEN (1U) -#define PDM_ADC_1_EN_MSK (((1U << PDM_ADC_1_EN_LEN) - 1) << PDM_ADC_1_EN_POS) -#define PDM_ADC_1_EN_UMSK (~(((1U << PDM_ADC_1_EN_LEN) - 1) << PDM_ADC_1_EN_POS)) -#define PDM_ADC_2_EN PDM_ADC_2_EN -#define PDM_ADC_2_EN_POS (2U) -#define PDM_ADC_2_EN_LEN (1U) -#define PDM_ADC_2_EN_MSK (((1U << PDM_ADC_2_EN_LEN) - 1) << PDM_ADC_2_EN_POS) -#define PDM_ADC_2_EN_UMSK (~(((1U << PDM_ADC_2_EN_LEN) - 1) << PDM_ADC_2_EN_POS)) -#define PDM_AUD_RX0_SEL PDM_AUD_RX0_SEL -#define PDM_AUD_RX0_SEL_POS (13U) -#define PDM_AUD_RX0_SEL_LEN (3U) -#define PDM_AUD_RX0_SEL_MSK (((1U << PDM_AUD_RX0_SEL_LEN) - 1) << PDM_AUD_RX0_SEL_POS) -#define PDM_AUD_RX0_SEL_UMSK (~(((1U << PDM_AUD_RX0_SEL_LEN) - 1) << PDM_AUD_RX0_SEL_POS)) -#define PDM_AUD_RX1_SEL PDM_AUD_RX1_SEL -#define PDM_AUD_RX1_SEL_POS (16U) -#define PDM_AUD_RX1_SEL_LEN (3U) -#define PDM_AUD_RX1_SEL_MSK (((1U << PDM_AUD_RX1_SEL_LEN) - 1) << PDM_AUD_RX1_SEL_POS) -#define PDM_AUD_RX1_SEL_UMSK (~(((1U << PDM_AUD_RX1_SEL_LEN) - 1) << PDM_AUD_RX1_SEL_POS)) -#define PDM_AUD_RX2_SEL PDM_AUD_RX2_SEL -#define PDM_AUD_RX2_SEL_POS (19U) -#define PDM_AUD_RX2_SEL_LEN (3U) -#define PDM_AUD_RX2_SEL_MSK (((1U << PDM_AUD_RX2_SEL_LEN) - 1) << PDM_AUD_RX2_SEL_POS) -#define PDM_AUD_RX2_SEL_UMSK (~(((1U << PDM_AUD_RX2_SEL_LEN) - 1) << PDM_AUD_RX2_SEL_POS)) -#define PDM_ADC_ITF_EN PDM_ADC_ITF_EN -#define PDM_ADC_ITF_EN_POS (30U) -#define PDM_ADC_ITF_EN_LEN (1U) -#define PDM_ADC_ITF_EN_MSK (((1U << PDM_ADC_ITF_EN_LEN) - 1) << PDM_ADC_ITF_EN_POS) -#define PDM_ADC_ITF_EN_UMSK (~(((1U << PDM_ADC_ITF_EN_LEN) - 1) << PDM_ADC_ITF_EN_POS)) - -/* 0xC08 : pdm_adc_0 */ -#define PDM_ADC_0_OFFSET (0xC08) -#define PDM_ADC_0_FIR_MODE PDM_ADC_0_FIR_MODE -#define PDM_ADC_0_FIR_MODE_POS (0U) -#define PDM_ADC_0_FIR_MODE_LEN (1U) -#define PDM_ADC_0_FIR_MODE_MSK (((1U << PDM_ADC_0_FIR_MODE_LEN) - 1) << PDM_ADC_0_FIR_MODE_POS) -#define PDM_ADC_0_FIR_MODE_UMSK (~(((1U << PDM_ADC_0_FIR_MODE_LEN) - 1) << PDM_ADC_0_FIR_MODE_POS)) -#define PDM_ADC_1_FIR_MODE PDM_ADC_1_FIR_MODE -#define PDM_ADC_1_FIR_MODE_POS (1U) -#define PDM_ADC_1_FIR_MODE_LEN (1U) -#define PDM_ADC_1_FIR_MODE_MSK (((1U << PDM_ADC_1_FIR_MODE_LEN) - 1) << PDM_ADC_1_FIR_MODE_POS) -#define PDM_ADC_1_FIR_MODE_UMSK (~(((1U << PDM_ADC_1_FIR_MODE_LEN) - 1) << PDM_ADC_1_FIR_MODE_POS)) -#define PDM_ADC_2_FIR_MODE PDM_ADC_2_FIR_MODE -#define PDM_ADC_2_FIR_MODE_POS (2U) -#define PDM_ADC_2_FIR_MODE_LEN (1U) -#define PDM_ADC_2_FIR_MODE_MSK (((1U << PDM_ADC_2_FIR_MODE_LEN) - 1) << PDM_ADC_2_FIR_MODE_POS) -#define PDM_ADC_2_FIR_MODE_UMSK (~(((1U << PDM_ADC_2_FIR_MODE_LEN) - 1) << PDM_ADC_2_FIR_MODE_POS)) -#define PDM_ADC_0_SCAL PDM_ADC_0_SCAL -#define PDM_ADC_0_SCAL_POS (3U) -#define PDM_ADC_0_SCAL_LEN (6U) -#define PDM_ADC_0_SCAL_MSK (((1U << PDM_ADC_0_SCAL_LEN) - 1) << PDM_ADC_0_SCAL_POS) -#define PDM_ADC_0_SCAL_UMSK (~(((1U << PDM_ADC_0_SCAL_LEN) - 1) << PDM_ADC_0_SCAL_POS)) -#define PDM_ADC_1_SCAL PDM_ADC_1_SCAL -#define PDM_ADC_1_SCAL_POS (9U) -#define PDM_ADC_1_SCAL_LEN (6U) -#define PDM_ADC_1_SCAL_MSK (((1U << PDM_ADC_1_SCAL_LEN) - 1) << PDM_ADC_1_SCAL_POS) -#define PDM_ADC_1_SCAL_UMSK (~(((1U << PDM_ADC_1_SCAL_LEN) - 1) << PDM_ADC_1_SCAL_POS)) -#define PDM_ADC_2_SCAL PDM_ADC_2_SCAL -#define PDM_ADC_2_SCAL_POS (15U) -#define PDM_ADC_2_SCAL_LEN (6U) -#define PDM_ADC_2_SCAL_MSK (((1U << PDM_ADC_2_SCAL_LEN) - 1) << PDM_ADC_2_SCAL_POS) -#define PDM_ADC_2_SCAL_UMSK (~(((1U << PDM_ADC_2_SCAL_LEN) - 1) << PDM_ADC_2_SCAL_POS)) - -/* 0xC0C : pdm_adc_1 */ -#define PDM_ADC_1_OFFSET (0xC0C) -#define PDM_ADC_0_K1 PDM_ADC_0_K1 -#define PDM_ADC_0_K1_POS (0U) -#define PDM_ADC_0_K1_LEN (4U) -#define PDM_ADC_0_K1_MSK (((1U << PDM_ADC_0_K1_LEN) - 1) << PDM_ADC_0_K1_POS) -#define PDM_ADC_0_K1_UMSK (~(((1U << PDM_ADC_0_K1_LEN) - 1) << PDM_ADC_0_K1_POS)) -#define PDM_ADC_0_K1_EN PDM_ADC_0_K1_EN -#define PDM_ADC_0_K1_EN_POS (4U) -#define PDM_ADC_0_K1_EN_LEN (1U) -#define PDM_ADC_0_K1_EN_MSK (((1U << PDM_ADC_0_K1_EN_LEN) - 1) << PDM_ADC_0_K1_EN_POS) -#define PDM_ADC_0_K1_EN_UMSK (~(((1U << PDM_ADC_0_K1_EN_LEN) - 1) << PDM_ADC_0_K1_EN_POS)) -#define PDM_ADC_0_K2 PDM_ADC_0_K2 -#define PDM_ADC_0_K2_POS (5U) -#define PDM_ADC_0_K2_LEN (4U) -#define PDM_ADC_0_K2_MSK (((1U << PDM_ADC_0_K2_LEN) - 1) << PDM_ADC_0_K2_POS) -#define PDM_ADC_0_K2_UMSK (~(((1U << PDM_ADC_0_K2_LEN) - 1) << PDM_ADC_0_K2_POS)) -#define PDM_ADC_0_K2_EN PDM_ADC_0_K2_EN -#define PDM_ADC_0_K2_EN_POS (9U) -#define PDM_ADC_0_K2_EN_LEN (1U) -#define PDM_ADC_0_K2_EN_MSK (((1U << PDM_ADC_0_K2_EN_LEN) - 1) << PDM_ADC_0_K2_EN_POS) -#define PDM_ADC_0_K2_EN_UMSK (~(((1U << PDM_ADC_0_K2_EN_LEN) - 1) << PDM_ADC_0_K2_EN_POS)) -#define PDM_ADC_1_K1 PDM_ADC_1_K1 -#define PDM_ADC_1_K1_POS (10U) -#define PDM_ADC_1_K1_LEN (4U) -#define PDM_ADC_1_K1_MSK (((1U << PDM_ADC_1_K1_LEN) - 1) << PDM_ADC_1_K1_POS) -#define PDM_ADC_1_K1_UMSK (~(((1U << PDM_ADC_1_K1_LEN) - 1) << PDM_ADC_1_K1_POS)) -#define PDM_ADC_1_K1_EN PDM_ADC_1_K1_EN -#define PDM_ADC_1_K1_EN_POS (14U) -#define PDM_ADC_1_K1_EN_LEN (1U) -#define PDM_ADC_1_K1_EN_MSK (((1U << PDM_ADC_1_K1_EN_LEN) - 1) << PDM_ADC_1_K1_EN_POS) -#define PDM_ADC_1_K1_EN_UMSK (~(((1U << PDM_ADC_1_K1_EN_LEN) - 1) << PDM_ADC_1_K1_EN_POS)) -#define PDM_ADC_1_K2 PDM_ADC_1_K2 -#define PDM_ADC_1_K2_POS (15U) -#define PDM_ADC_1_K2_LEN (4U) -#define PDM_ADC_1_K2_MSK (((1U << PDM_ADC_1_K2_LEN) - 1) << PDM_ADC_1_K2_POS) -#define PDM_ADC_1_K2_UMSK (~(((1U << PDM_ADC_1_K2_LEN) - 1) << PDM_ADC_1_K2_POS)) -#define PDM_ADC_1_K2_EN PDM_ADC_1_K2_EN -#define PDM_ADC_1_K2_EN_POS (19U) -#define PDM_ADC_1_K2_EN_LEN (1U) -#define PDM_ADC_1_K2_EN_MSK (((1U << PDM_ADC_1_K2_EN_LEN) - 1) << PDM_ADC_1_K2_EN_POS) -#define PDM_ADC_1_K2_EN_UMSK (~(((1U << PDM_ADC_1_K2_EN_LEN) - 1) << PDM_ADC_1_K2_EN_POS)) -#define PDM_ADC_2_K1 PDM_ADC_2_K1 -#define PDM_ADC_2_K1_POS (20U) -#define PDM_ADC_2_K1_LEN (4U) -#define PDM_ADC_2_K1_MSK (((1U << PDM_ADC_2_K1_LEN) - 1) << PDM_ADC_2_K1_POS) -#define PDM_ADC_2_K1_UMSK (~(((1U << PDM_ADC_2_K1_LEN) - 1) << PDM_ADC_2_K1_POS)) -#define PDM_ADC_2_K1_EN PDM_ADC_2_K1_EN -#define PDM_ADC_2_K1_EN_POS (24U) -#define PDM_ADC_2_K1_EN_LEN (1U) -#define PDM_ADC_2_K1_EN_MSK (((1U << PDM_ADC_2_K1_EN_LEN) - 1) << PDM_ADC_2_K1_EN_POS) -#define PDM_ADC_2_K1_EN_UMSK (~(((1U << PDM_ADC_2_K1_EN_LEN) - 1) << PDM_ADC_2_K1_EN_POS)) -#define PDM_ADC_2_K2 PDM_ADC_2_K2 -#define PDM_ADC_2_K2_POS (25U) -#define PDM_ADC_2_K2_LEN (4U) -#define PDM_ADC_2_K2_MSK (((1U << PDM_ADC_2_K2_LEN) - 1) << PDM_ADC_2_K2_POS) -#define PDM_ADC_2_K2_UMSK (~(((1U << PDM_ADC_2_K2_LEN) - 1) << PDM_ADC_2_K2_POS)) -#define PDM_ADC_2_K2_EN PDM_ADC_2_K2_EN -#define PDM_ADC_2_K2_EN_POS (29U) -#define PDM_ADC_2_K2_EN_LEN (1U) -#define PDM_ADC_2_K2_EN_MSK (((1U << PDM_ADC_2_K2_EN_LEN) - 1) << PDM_ADC_2_K2_EN_POS) -#define PDM_ADC_2_K2_EN_UMSK (~(((1U << PDM_ADC_2_K2_EN_LEN) - 1) << PDM_ADC_2_K2_EN_POS)) - -/* 0xC10 : pdm_dac_0 */ -#define PDM_DAC_0_OFFSET (0xC10) -#define PDM_ADC_PDM_H PDM_ADC_PDM_H -#define PDM_ADC_PDM_H_POS (0U) -#define PDM_ADC_PDM_H_LEN (6U) -#define PDM_ADC_PDM_H_MSK (((1U << PDM_ADC_PDM_H_LEN) - 1) << PDM_ADC_PDM_H_POS) -#define PDM_ADC_PDM_H_UMSK (~(((1U << PDM_ADC_PDM_H_LEN) - 1) << PDM_ADC_PDM_H_POS)) -#define PDM_ADC_PDM_L PDM_ADC_PDM_L -#define PDM_ADC_PDM_L_POS (6U) -#define PDM_ADC_PDM_L_LEN (6U) -#define PDM_ADC_PDM_L_MSK (((1U << PDM_ADC_PDM_L_LEN) - 1) << PDM_ADC_PDM_L_POS) -#define PDM_ADC_PDM_L_UMSK (~(((1U << PDM_ADC_PDM_L_LEN) - 1) << PDM_ADC_PDM_L_POS)) -#define PDM_ADC_0_PDM_LVL_SWAP PDM_ADC_0_PDM_LVL_SWAP -#define PDM_ADC_0_PDM_LVL_SWAP_POS (13U) -#define PDM_ADC_0_PDM_LVL_SWAP_LEN (1U) -#define PDM_ADC_0_PDM_LVL_SWAP_MSK (((1U << PDM_ADC_0_PDM_LVL_SWAP_LEN) - 1) << PDM_ADC_0_PDM_LVL_SWAP_POS) -#define PDM_ADC_0_PDM_LVL_SWAP_UMSK (~(((1U << PDM_ADC_0_PDM_LVL_SWAP_LEN) - 1) << PDM_ADC_0_PDM_LVL_SWAP_POS)) -#define PDM_ADC_1_PDM_LVL_SWAP PDM_ADC_1_PDM_LVL_SWAP -#define PDM_ADC_1_PDM_LVL_SWAP_POS (16U) -#define PDM_ADC_1_PDM_LVL_SWAP_LEN (1U) -#define PDM_ADC_1_PDM_LVL_SWAP_MSK (((1U << PDM_ADC_1_PDM_LVL_SWAP_LEN) - 1) << PDM_ADC_1_PDM_LVL_SWAP_POS) -#define PDM_ADC_1_PDM_LVL_SWAP_UMSK (~(((1U << PDM_ADC_1_PDM_LVL_SWAP_LEN) - 1) << PDM_ADC_1_PDM_LVL_SWAP_POS)) -#define PDM_ADC_2_PDM_LVL_SWAP PDM_ADC_2_PDM_LVL_SWAP -#define PDM_ADC_2_PDM_LVL_SWAP_POS (19U) -#define PDM_ADC_2_PDM_LVL_SWAP_LEN (1U) -#define PDM_ADC_2_PDM_LVL_SWAP_MSK (((1U << PDM_ADC_2_PDM_LVL_SWAP_LEN) - 1) << PDM_ADC_2_PDM_LVL_SWAP_POS) -#define PDM_ADC_2_PDM_LVL_SWAP_UMSK (~(((1U << PDM_ADC_2_PDM_LVL_SWAP_LEN) - 1) << PDM_ADC_2_PDM_LVL_SWAP_POS)) - -/* 0xC1C : pdm_pdm_0 */ -#define PDM_PDM_0_OFFSET (0xC1C) -#define PDM_0_EN PDM_0_EN -#define PDM_0_EN_POS (0U) -#define PDM_0_EN_LEN (1U) -#define PDM_0_EN_MSK (((1U << PDM_0_EN_LEN) - 1) << PDM_0_EN_POS) -#define PDM_0_EN_UMSK (~(((1U << PDM_0_EN_LEN) - 1) << PDM_0_EN_POS)) -#define PDM_1_EN PDM_1_EN -#define PDM_1_EN_POS (1U) -#define PDM_1_EN_LEN (1U) -#define PDM_1_EN_MSK (((1U << PDM_1_EN_LEN) - 1) << PDM_1_EN_POS) -#define PDM_1_EN_UMSK (~(((1U << PDM_1_EN_LEN) - 1) << PDM_1_EN_POS)) -#define PDM_2_EN PDM_2_EN -#define PDM_2_EN_POS (2U) -#define PDM_2_EN_LEN (1U) -#define PDM_2_EN_MSK (((1U << PDM_2_EN_LEN) - 1) << PDM_2_EN_POS) -#define PDM_2_EN_UMSK (~(((1U << PDM_2_EN_LEN) - 1) << PDM_2_EN_POS)) -#define PDM_ADC_0_PDM_SEL PDM_ADC_0_PDM_SEL -#define PDM_ADC_0_PDM_SEL_POS (3U) -#define PDM_ADC_0_PDM_SEL_LEN (3U) -#define PDM_ADC_0_PDM_SEL_MSK (((1U << PDM_ADC_0_PDM_SEL_LEN) - 1) << PDM_ADC_0_PDM_SEL_POS) -#define PDM_ADC_0_PDM_SEL_UMSK (~(((1U << PDM_ADC_0_PDM_SEL_LEN) - 1) << PDM_ADC_0_PDM_SEL_POS)) -#define PDM_ADC_1_PDM_SEL PDM_ADC_1_PDM_SEL -#define PDM_ADC_1_PDM_SEL_POS (6U) -#define PDM_ADC_1_PDM_SEL_LEN (3U) -#define PDM_ADC_1_PDM_SEL_MSK (((1U << PDM_ADC_1_PDM_SEL_LEN) - 1) << PDM_ADC_1_PDM_SEL_POS) -#define PDM_ADC_1_PDM_SEL_UMSK (~(((1U << PDM_ADC_1_PDM_SEL_LEN) - 1) << PDM_ADC_1_PDM_SEL_POS)) -#define PDM_ADC_2_PDM_SEL PDM_ADC_2_PDM_SEL -#define PDM_ADC_2_PDM_SEL_POS (9U) -#define PDM_ADC_2_PDM_SEL_LEN (3U) -#define PDM_ADC_2_PDM_SEL_MSK (((1U << PDM_ADC_2_PDM_SEL_LEN) - 1) << PDM_ADC_2_PDM_SEL_POS) -#define PDM_ADC_2_PDM_SEL_UMSK (~(((1U << PDM_ADC_2_PDM_SEL_LEN) - 1) << PDM_ADC_2_PDM_SEL_POS)) - -/* 0xC20 : pdm_rsvd0 */ -#define PDM_RSVD0_OFFSET (0xC20) - -/* 0xC24 : pdm_dbg_0 */ -#define PDM_DBG_0_OFFSET (0xC24) -#define PDM_ADC_TEST_CLKIN_EN PDM_ADC_TEST_CLKIN_EN -#define PDM_ADC_TEST_CLKIN_EN_POS (21U) -#define PDM_ADC_TEST_CLKIN_EN_LEN (1U) -#define PDM_ADC_TEST_CLKIN_EN_MSK (((1U << PDM_ADC_TEST_CLKIN_EN_LEN) - 1) << PDM_ADC_TEST_CLKIN_EN_POS) -#define PDM_ADC_TEST_CLKIN_EN_UMSK (~(((1U << PDM_ADC_TEST_CLKIN_EN_LEN) - 1) << PDM_ADC_TEST_CLKIN_EN_POS)) -#define PDM_ADC_TEST_DIN_EN PDM_ADC_TEST_DIN_EN -#define PDM_ADC_TEST_DIN_EN_POS (23U) -#define PDM_ADC_TEST_DIN_EN_LEN (1U) -#define PDM_ADC_TEST_DIN_EN_MSK (((1U << PDM_ADC_TEST_DIN_EN_LEN) - 1) << PDM_ADC_TEST_DIN_EN_POS) -#define PDM_ADC_TEST_DIN_EN_UMSK (~(((1U << PDM_ADC_TEST_DIN_EN_LEN) - 1) << PDM_ADC_TEST_DIN_EN_POS)) -#define PDM_AUD_TEST_READ_SEL PDM_AUD_TEST_READ_SEL -#define PDM_AUD_TEST_READ_SEL_POS (24U) -#define PDM_AUD_TEST_READ_SEL_LEN (6U) -#define PDM_AUD_TEST_READ_SEL_MSK (((1U << PDM_AUD_TEST_READ_SEL_LEN) - 1) << PDM_AUD_TEST_READ_SEL_POS) -#define PDM_AUD_TEST_READ_SEL_UMSK (~(((1U << PDM_AUD_TEST_READ_SEL_LEN) - 1) << PDM_AUD_TEST_READ_SEL_POS)) - -/* 0xC28 : pdm_dbg_1 */ -#define PDM_DBG_1_OFFSET (0xC28) -#define PDM_AUD_TEST_READ PDM_AUD_TEST_READ -#define PDM_AUD_TEST_READ_POS (0U) -#define PDM_AUD_TEST_READ_LEN (32U) -#define PDM_AUD_TEST_READ_MSK (((1U << PDM_AUD_TEST_READ_LEN) - 1) << PDM_AUD_TEST_READ_POS) -#define PDM_AUD_TEST_READ_UMSK (~(((1U << PDM_AUD_TEST_READ_LEN) - 1) << PDM_AUD_TEST_READ_POS)) - -/* 0xC2C : pdm_dbg_2 */ -#define PDM_DBG_2_OFFSET (0xC2C) -#define PDM_ADC_FIR_4S_VAL PDM_ADC_FIR_4S_VAL -#define PDM_ADC_FIR_4S_VAL_POS (0U) -#define PDM_ADC_FIR_4S_VAL_LEN (20U) -#define PDM_ADC_FIR_4S_VAL_MSK (((1U << PDM_ADC_FIR_4S_VAL_LEN) - 1) << PDM_ADC_FIR_4S_VAL_POS) -#define PDM_ADC_FIR_4S_VAL_UMSK (~(((1U << PDM_ADC_FIR_4S_VAL_LEN) - 1) << PDM_ADC_FIR_4S_VAL_POS)) -#define PDM_ADC_0_FIR_4S_EN PDM_ADC_0_FIR_4S_EN -#define PDM_ADC_0_FIR_4S_EN_POS (20U) -#define PDM_ADC_0_FIR_4S_EN_LEN (1U) -#define PDM_ADC_0_FIR_4S_EN_MSK (((1U << PDM_ADC_0_FIR_4S_EN_LEN) - 1) << PDM_ADC_0_FIR_4S_EN_POS) -#define PDM_ADC_0_FIR_4S_EN_UMSK (~(((1U << PDM_ADC_0_FIR_4S_EN_LEN) - 1) << PDM_ADC_0_FIR_4S_EN_POS)) -#define PDM_ADC_1_FIR_4S_EN PDM_ADC_1_FIR_4S_EN -#define PDM_ADC_1_FIR_4S_EN_POS (21U) -#define PDM_ADC_1_FIR_4S_EN_LEN (1U) -#define PDM_ADC_1_FIR_4S_EN_MSK (((1U << PDM_ADC_1_FIR_4S_EN_LEN) - 1) << PDM_ADC_1_FIR_4S_EN_POS) -#define PDM_ADC_1_FIR_4S_EN_UMSK (~(((1U << PDM_ADC_1_FIR_4S_EN_LEN) - 1) << PDM_ADC_1_FIR_4S_EN_POS)) -#define PDM_ADC_2_FIR_4S_EN PDM_ADC_2_FIR_4S_EN -#define PDM_ADC_2_FIR_4S_EN_POS (22U) -#define PDM_ADC_2_FIR_4S_EN_LEN (1U) -#define PDM_ADC_2_FIR_4S_EN_MSK (((1U << PDM_ADC_2_FIR_4S_EN_LEN) - 1) << PDM_ADC_2_FIR_4S_EN_POS) -#define PDM_ADC_2_FIR_4S_EN_UMSK (~(((1U << PDM_ADC_2_FIR_4S_EN_LEN) - 1) << PDM_ADC_2_FIR_4S_EN_POS)) -#define PDM_ADC_IN_0_TEST_SEL PDM_ADC_IN_0_TEST_SEL -#define PDM_ADC_IN_0_TEST_SEL_POS (23U) -#define PDM_ADC_IN_0_TEST_SEL_LEN (1U) -#define PDM_ADC_IN_0_TEST_SEL_MSK (((1U << PDM_ADC_IN_0_TEST_SEL_LEN) - 1) << PDM_ADC_IN_0_TEST_SEL_POS) -#define PDM_ADC_IN_0_TEST_SEL_UMSK (~(((1U << PDM_ADC_IN_0_TEST_SEL_LEN) - 1) << PDM_ADC_IN_0_TEST_SEL_POS)) -#define PDM_ADC_IN_1_TEST_SEL PDM_ADC_IN_1_TEST_SEL -#define PDM_ADC_IN_1_TEST_SEL_POS (24U) -#define PDM_ADC_IN_1_TEST_SEL_LEN (1U) -#define PDM_ADC_IN_1_TEST_SEL_MSK (((1U << PDM_ADC_IN_1_TEST_SEL_LEN) - 1) << PDM_ADC_IN_1_TEST_SEL_POS) -#define PDM_ADC_IN_1_TEST_SEL_UMSK (~(((1U << PDM_ADC_IN_1_TEST_SEL_LEN) - 1) << PDM_ADC_IN_1_TEST_SEL_POS)) -#define PDM_ADC_IN_2_TEST_SEL PDM_ADC_IN_2_TEST_SEL -#define PDM_ADC_IN_2_TEST_SEL_POS (25U) -#define PDM_ADC_IN_2_TEST_SEL_LEN (1U) -#define PDM_ADC_IN_2_TEST_SEL_MSK (((1U << PDM_ADC_IN_2_TEST_SEL_LEN) - 1) << PDM_ADC_IN_2_TEST_SEL_POS) -#define PDM_ADC_IN_2_TEST_SEL_UMSK (~(((1U << PDM_ADC_IN_2_TEST_SEL_LEN) - 1) << PDM_ADC_IN_2_TEST_SEL_POS)) - -/* 0xC30 : pdm_dbg_3 */ -#define PDM_DBG_3_OFFSET (0xC30) - -/* 0xC34 : pdm_dbg_4 */ -#define PDM_DBG_4_OFFSET (0xC34) -#define PDM_ADC_IN_RATIO_4S_VAL PDM_ADC_IN_RATIO_4S_VAL -#define PDM_ADC_IN_RATIO_4S_VAL_POS (0U) -#define PDM_ADC_IN_RATIO_4S_VAL_LEN (1U) -#define PDM_ADC_IN_RATIO_4S_VAL_MSK (((1U << PDM_ADC_IN_RATIO_4S_VAL_LEN) - 1) << PDM_ADC_IN_RATIO_4S_VAL_POS) -#define PDM_ADC_IN_RATIO_4S_VAL_UMSK (~(((1U << PDM_ADC_IN_RATIO_4S_VAL_LEN) - 1) << PDM_ADC_IN_RATIO_4S_VAL_POS)) -#define PDM_ADC_IN_CH0_RATIO_4S_VAL PDM_ADC_IN_CH0_RATIO_4S_VAL -#define PDM_ADC_IN_CH0_RATIO_4S_VAL_POS (1U) -#define PDM_ADC_IN_CH0_RATIO_4S_VAL_LEN (1U) -#define PDM_ADC_IN_CH0_RATIO_4S_VAL_MSK (((1U << PDM_ADC_IN_CH0_RATIO_4S_VAL_LEN) - 1) << PDM_ADC_IN_CH0_RATIO_4S_VAL_POS) -#define PDM_ADC_IN_CH0_RATIO_4S_VAL_UMSK (~(((1U << PDM_ADC_IN_CH0_RATIO_4S_VAL_LEN) - 1) << PDM_ADC_IN_CH0_RATIO_4S_VAL_POS)) -#define PDM_ADC_IN_CH1_RATIO_4S_VAL PDM_ADC_IN_CH1_RATIO_4S_VAL -#define PDM_ADC_IN_CH1_RATIO_4S_VAL_POS (2U) -#define PDM_ADC_IN_CH1_RATIO_4S_VAL_LEN (1U) -#define PDM_ADC_IN_CH1_RATIO_4S_VAL_MSK (((1U << PDM_ADC_IN_CH1_RATIO_4S_VAL_LEN) - 1) << PDM_ADC_IN_CH1_RATIO_4S_VAL_POS) -#define PDM_ADC_IN_CH1_RATIO_4S_VAL_UMSK (~(((1U << PDM_ADC_IN_CH1_RATIO_4S_VAL_LEN) - 1) << PDM_ADC_IN_CH1_RATIO_4S_VAL_POS)) -#define PDM_ADC_IN_CH2_RATIO_4S_VAL PDM_ADC_IN_CH2_RATIO_4S_VAL -#define PDM_ADC_IN_CH2_RATIO_4S_VAL_POS (3U) -#define PDM_ADC_IN_CH2_RATIO_4S_VAL_LEN (1U) -#define PDM_ADC_IN_CH2_RATIO_4S_VAL_MSK (((1U << PDM_ADC_IN_CH2_RATIO_4S_VAL_LEN) - 1) << PDM_ADC_IN_CH2_RATIO_4S_VAL_POS) -#define PDM_ADC_IN_CH2_RATIO_4S_VAL_UMSK (~(((1U << PDM_ADC_IN_CH2_RATIO_4S_VAL_LEN) - 1) << PDM_ADC_IN_CH2_RATIO_4S_VAL_POS)) -#define PDM_IN_RATIO_4S_VAL PDM_IN_RATIO_4S_VAL -#define PDM_IN_RATIO_4S_VAL_POS (4U) -#define PDM_IN_RATIO_4S_VAL_LEN (1U) -#define PDM_IN_RATIO_4S_VAL_MSK (((1U << PDM_IN_RATIO_4S_VAL_LEN) - 1) << PDM_IN_RATIO_4S_VAL_POS) -#define PDM_IN_RATIO_4S_VAL_UMSK (~(((1U << PDM_IN_RATIO_4S_VAL_LEN) - 1) << PDM_IN_RATIO_4S_VAL_POS)) -#define PDM_IN_RATIO_4S PDM_IN_RATIO_4S -#define PDM_IN_RATIO_4S_POS (5U) -#define PDM_IN_RATIO_4S_LEN (1U) -#define PDM_IN_RATIO_4S_MSK (((1U << PDM_IN_RATIO_4S_LEN) - 1) << PDM_IN_RATIO_4S_POS) -#define PDM_IN_RATIO_4S_UMSK (~(((1U << PDM_IN_RATIO_4S_LEN) - 1) << PDM_IN_RATIO_4S_POS)) - -/* 0xC38 : pdm_adc_s0 */ -#define PDM_ADC_S0_OFFSET (0xC38) -#define PDM_ADC_S0_VOLUME PDM_ADC_S0_VOLUME -#define PDM_ADC_S0_VOLUME_POS (0U) -#define PDM_ADC_S0_VOLUME_LEN (9U) -#define PDM_ADC_S0_VOLUME_MSK (((1U << PDM_ADC_S0_VOLUME_LEN) - 1) << PDM_ADC_S0_VOLUME_POS) -#define PDM_ADC_S0_VOLUME_UMSK (~(((1U << PDM_ADC_S0_VOLUME_LEN) - 1) << PDM_ADC_S0_VOLUME_POS)) - -/* 0xC3C : pdm_adc_s1 */ -#define PDM_ADC_S1_OFFSET (0xC3C) -#define PDM_ADC_S1_VOLUME PDM_ADC_S1_VOLUME -#define PDM_ADC_S1_VOLUME_POS (0U) -#define PDM_ADC_S1_VOLUME_LEN (9U) -#define PDM_ADC_S1_VOLUME_MSK (((1U << PDM_ADC_S1_VOLUME_LEN) - 1) << PDM_ADC_S1_VOLUME_POS) -#define PDM_ADC_S1_VOLUME_UMSK (~(((1U << PDM_ADC_S1_VOLUME_LEN) - 1) << PDM_ADC_S1_VOLUME_POS)) - -/* 0xC40 : pdm_adc_s2 */ -#define PDM_ADC_S2_OFFSET (0xC40) -#define PDM_ADC_S2_VOLUME PDM_ADC_S2_VOLUME -#define PDM_ADC_S2_VOLUME_POS (0U) -#define PDM_ADC_S2_VOLUME_LEN (9U) -#define PDM_ADC_S2_VOLUME_MSK (((1U << PDM_ADC_S2_VOLUME_LEN) - 1) << PDM_ADC_S2_VOLUME_POS) -#define PDM_ADC_S2_VOLUME_UMSK (~(((1U << PDM_ADC_S2_VOLUME_LEN) - 1) << PDM_ADC_S2_VOLUME_POS)) - -/* 0xC80 : pdm_rx_fifo_ctrl */ -#define PDM_RX_FIFO_CTRL_OFFSET (0xC80) -#define PDM_RX_FIFO_FLUSH PDM_RX_FIFO_FLUSH -#define PDM_RX_FIFO_FLUSH_POS (0U) -#define PDM_RX_FIFO_FLUSH_LEN (1U) -#define PDM_RX_FIFO_FLUSH_MSK (((1U << PDM_RX_FIFO_FLUSH_LEN) - 1) << PDM_RX_FIFO_FLUSH_POS) -#define PDM_RX_FIFO_FLUSH_UMSK (~(((1U << PDM_RX_FIFO_FLUSH_LEN) - 1) << PDM_RX_FIFO_FLUSH_POS)) -#define PDM_RXO_INT_EN PDM_RXO_INT_EN -#define PDM_RXO_INT_EN_POS (1U) -#define PDM_RXO_INT_EN_LEN (1U) -#define PDM_RXO_INT_EN_MSK (((1U << PDM_RXO_INT_EN_LEN) - 1) << PDM_RXO_INT_EN_POS) -#define PDM_RXO_INT_EN_UMSK (~(((1U << PDM_RXO_INT_EN_LEN) - 1) << PDM_RXO_INT_EN_POS)) -#define PDM_RXU_INT_EN PDM_RXU_INT_EN -#define PDM_RXU_INT_EN_POS (2U) -#define PDM_RXU_INT_EN_LEN (1U) -#define PDM_RXU_INT_EN_MSK (((1U << PDM_RXU_INT_EN_LEN) - 1) << PDM_RXU_INT_EN_POS) -#define PDM_RXU_INT_EN_UMSK (~(((1U << PDM_RXU_INT_EN_LEN) - 1) << PDM_RXU_INT_EN_POS)) -#define PDM_RXA_INT_EN PDM_RXA_INT_EN -#define PDM_RXA_INT_EN_POS (3U) -#define PDM_RXA_INT_EN_LEN (1U) -#define PDM_RXA_INT_EN_MSK (((1U << PDM_RXA_INT_EN_LEN) - 1) << PDM_RXA_INT_EN_POS) -#define PDM_RXA_INT_EN_UMSK (~(((1U << PDM_RXA_INT_EN_LEN) - 1) << PDM_RXA_INT_EN_POS)) -#define PDM_RX_DRQ_EN PDM_RX_DRQ_EN -#define PDM_RX_DRQ_EN_POS (4U) -#define PDM_RX_DRQ_EN_LEN (1U) -#define PDM_RX_DRQ_EN_MSK (((1U << PDM_RX_DRQ_EN_LEN) - 1) << PDM_RX_DRQ_EN_POS) -#define PDM_RX_DRQ_EN_UMSK (~(((1U << PDM_RX_DRQ_EN_LEN) - 1) << PDM_RX_DRQ_EN_POS)) -#define PDM_RX_DATA_RES PDM_RX_DATA_RES -#define PDM_RX_DATA_RES_POS (5U) -#define PDM_RX_DATA_RES_LEN (1U) -#define PDM_RX_DATA_RES_MSK (((1U << PDM_RX_DATA_RES_LEN) - 1) << PDM_RX_DATA_RES_POS) -#define PDM_RX_DATA_RES_UMSK (~(((1U << PDM_RX_DATA_RES_LEN) - 1) << PDM_RX_DATA_RES_POS)) -#define PDM_RX_CH_EN PDM_RX_CH_EN -#define PDM_RX_CH_EN_POS (8U) -#define PDM_RX_CH_EN_LEN (3U) -#define PDM_RX_CH_EN_MSK (((1U << PDM_RX_CH_EN_LEN) - 1) << PDM_RX_CH_EN_POS) -#define PDM_RX_CH_EN_UMSK (~(((1U << PDM_RX_CH_EN_LEN) - 1) << PDM_RX_CH_EN_POS)) -#define PDM_RX_DRQ_CNT PDM_RX_DRQ_CNT -#define PDM_RX_DRQ_CNT_POS (14U) -#define PDM_RX_DRQ_CNT_LEN (2U) -#define PDM_RX_DRQ_CNT_MSK (((1U << PDM_RX_DRQ_CNT_LEN) - 1) << PDM_RX_DRQ_CNT_POS) -#define PDM_RX_DRQ_CNT_UMSK (~(((1U << PDM_RX_DRQ_CNT_LEN) - 1) << PDM_RX_DRQ_CNT_POS)) -#define PDM_RX_TRG_LEVEL PDM_RX_TRG_LEVEL -#define PDM_RX_TRG_LEVEL_POS (16U) -#define PDM_RX_TRG_LEVEL_LEN (6U) -#define PDM_RX_TRG_LEVEL_MSK (((1U << PDM_RX_TRG_LEVEL_LEN) - 1) << PDM_RX_TRG_LEVEL_POS) -#define PDM_RX_TRG_LEVEL_UMSK (~(((1U << PDM_RX_TRG_LEVEL_LEN) - 1) << PDM_RX_TRG_LEVEL_POS)) -#define PDM_RX_DATA_MODE PDM_RX_DATA_MODE -#define PDM_RX_DATA_MODE_POS (24U) -#define PDM_RX_DATA_MODE_LEN (2U) -#define PDM_RX_DATA_MODE_MSK (((1U << PDM_RX_DATA_MODE_LEN) - 1) << PDM_RX_DATA_MODE_POS) -#define PDM_RX_DATA_MODE_UMSK (~(((1U << PDM_RX_DATA_MODE_LEN) - 1) << PDM_RX_DATA_MODE_POS)) - -/* 0xC84 : pdm_rx_fifo_status */ -#define PDM_RX_FIFO_STATUS_OFFSET (0xC84) -#define PDM_RXO_INT PDM_RXO_INT -#define PDM_RXO_INT_POS (1U) -#define PDM_RXO_INT_LEN (1U) -#define PDM_RXO_INT_MSK (((1U << PDM_RXO_INT_LEN) - 1) << PDM_RXO_INT_POS) -#define PDM_RXO_INT_UMSK (~(((1U << PDM_RXO_INT_LEN) - 1) << PDM_RXO_INT_POS)) -#define PDM_RXU_INT PDM_RXU_INT -#define PDM_RXU_INT_POS (2U) -#define PDM_RXU_INT_LEN (1U) -#define PDM_RXU_INT_MSK (((1U << PDM_RXU_INT_LEN) - 1) << PDM_RXU_INT_POS) -#define PDM_RXU_INT_UMSK (~(((1U << PDM_RXU_INT_LEN) - 1) << PDM_RXU_INT_POS)) -#define PDM_RXA_INT PDM_RXA_INT -#define PDM_RXA_INT_POS (4U) -#define PDM_RXA_INT_LEN (1U) -#define PDM_RXA_INT_MSK (((1U << PDM_RXA_INT_LEN) - 1) << PDM_RXA_INT_POS) -#define PDM_RXA_INT_UMSK (~(((1U << PDM_RXA_INT_LEN) - 1) << PDM_RXA_INT_POS)) -#define PDM_RXA_CNT PDM_RXA_CNT -#define PDM_RXA_CNT_POS (16U) -#define PDM_RXA_CNT_LEN (6U) -#define PDM_RXA_CNT_MSK (((1U << PDM_RXA_CNT_LEN) - 1) << PDM_RXA_CNT_POS) -#define PDM_RXA_CNT_UMSK (~(((1U << PDM_RXA_CNT_LEN) - 1) << PDM_RXA_CNT_POS)) -#define PDM_RXA PDM_RXA -#define PDM_RXA_POS (24U) -#define PDM_RXA_LEN (1U) -#define PDM_RXA_MSK (((1U << PDM_RXA_LEN) - 1) << PDM_RXA_POS) -#define PDM_RXA_UMSK (~(((1U << PDM_RXA_LEN) - 1) << PDM_RXA_POS)) - -/* 0xC88 : pdm_rx_fifo_data */ -#define PDM_RX_FIFO_DATA_OFFSET (0xC88) -#define PDM_RX_DATA PDM_RX_DATA -#define PDM_RX_DATA_POS (0U) -#define PDM_RX_DATA_LEN (32U) -#define PDM_RX_DATA_MSK (((1U << PDM_RX_DATA_LEN) - 1) << PDM_RX_DATA_POS) -#define PDM_RX_DATA_UMSK (~(((1U << PDM_RX_DATA_LEN) - 1) << PDM_RX_DATA_POS)) - -struct pdm_reg { - /* 0x0 reserved */ - uint8_t RESERVED0x0[3072]; - - /* 0xC00 : audpdm_top */ - union { - struct { - uint32_t audio_ckg_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1 : 1; /* [ 1], rsvd, 0x0 */ - uint32_t adc_itf_inv_sel : 1; /* [ 2], r/w, 0x0 */ - uint32_t pdm_itf_inv_sel : 1; /* [ 3], r/w, 0x0 */ - uint32_t reserved_4_27 : 24; /* [27: 4], rsvd, 0x0 */ - uint32_t adc_rate : 3; /* [30:28], r/w, 0x1 */ - uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } audpdm_top; - - /* 0xC04 : audpdm_itf */ - union { - struct { - uint32_t adc_0_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t adc_1_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t adc_2_en : 1; /* [ 2], r/w, 0x0 */ - uint32_t reserved_3_12 : 10; /* [12: 3], rsvd, 0x0 */ - uint32_t aud_rx0_sel : 3; /* [15:13], r/w, 0x0 */ - uint32_t aud_rx1_sel : 3; /* [18:16], r/w, 0x1 */ - uint32_t aud_rx2_sel : 3; /* [21:19], r/w, 0x2 */ - uint32_t reserved_22_29 : 8; /* [29:22], rsvd, 0x0 */ - uint32_t adc_itf_en : 1; /* [ 30], r/w, 0x0 */ - uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } audpdm_itf; - - /* 0xC08 : pdm_adc_0 */ - union { - struct { - uint32_t adc_0_fir_mode : 1; /* [ 0], r/w, 0x0 */ - uint32_t adc_1_fir_mode : 1; /* [ 1], r/w, 0x0 */ - uint32_t adc_2_fir_mode : 1; /* [ 2], r/w, 0x0 */ - uint32_t adc_0_scal : 6; /* [ 8: 3], r/w, 0x20 */ - uint32_t adc_1_scal : 6; /* [14: 9], r/w, 0x20 */ - uint32_t adc_2_scal : 6; /* [20:15], r/w, 0x20 */ - uint32_t reserved_21_31 : 11; /* [31:21], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } pdm_adc_0; - - /* 0xC0C : pdm_adc_1 */ - union { - struct { - uint32_t adc_0_k1 : 4; /* [ 3: 0], r/w, 0x8 */ - uint32_t adc_0_k1_en : 1; /* [ 4], r/w, 0x1 */ - uint32_t adc_0_k2 : 4; /* [ 8: 5], r/w, 0xd */ - uint32_t adc_0_k2_en : 1; /* [ 9], r/w, 0x0 */ - uint32_t adc_1_k1 : 4; /* [13:10], r/w, 0x8 */ - uint32_t adc_1_k1_en : 1; /* [ 14], r/w, 0x1 */ - uint32_t adc_1_k2 : 4; /* [18:15], r/w, 0xd */ - uint32_t adc_1_k2_en : 1; /* [ 19], r/w, 0x0 */ - uint32_t adc_2_k1 : 4; /* [23:20], r/w, 0x8 */ - uint32_t adc_2_k1_en : 1; /* [ 24], r/w, 0x1 */ - uint32_t adc_2_k2 : 4; /* [28:25], r/w, 0xd */ - uint32_t adc_2_k2_en : 1; /* [ 29], r/w, 0x0 */ - uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } pdm_adc_1; - - /* 0xC10 : pdm_dac_0 */ - union { - struct { - uint32_t adc_pdm_h : 6; /* [ 5: 0], r/w, 0x1 */ - uint32_t adc_pdm_l : 6; /* [11: 6], r/w, 0x3f */ - uint32_t reserved_12 : 1; /* [ 12], rsvd, 0x0 */ - uint32_t adc_0_pdm_lvl_swap : 1; /* [ 13], r/w, 0x0 */ - uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ - uint32_t adc_1_pdm_lvl_swap : 1; /* [ 16], r/w, 0x0 */ - uint32_t reserved_17_18 : 2; /* [18:17], rsvd, 0x0 */ - uint32_t adc_2_pdm_lvl_swap : 1; /* [ 19], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } pdm_dac_0; - - /* 0xc14 reserved */ - uint8_t RESERVED0xc14[8]; - - /* 0xC1C : pdm_pdm_0 */ - union { - struct { - uint32_t pdm_0_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t pdm_1_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t pdm_2_en : 1; /* [ 2], r/w, 0x0 */ - uint32_t adc_0_pdm_sel : 3; /* [ 5: 3], r/w, 0x0 */ - uint32_t adc_1_pdm_sel : 3; /* [ 8: 6], r/w, 0x1 */ - uint32_t adc_2_pdm_sel : 3; /* [11: 9], r/w, 0x2 */ - uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } pdm_pdm_0; - - /* 0xC20 : pdm_rsvd0 */ - union { - struct { - uint32_t rsvd0 : 32; /* [31: 0], r/w, 0xffff */ - } BF; - uint32_t WORD; - } pdm_rsvd0; - - /* 0xC24 : pdm_dbg_0 */ - union { - struct { - uint32_t reserved_0_20 : 21; /* [20: 0], rsvd, 0x0 */ - uint32_t adc_test_clkin_en : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22 : 1; /* [ 22], rsvd, 0x0 */ - uint32_t adc_test_din_en : 1; /* [ 23], r/w, 0x0 */ - uint32_t aud_test_read_sel : 6; /* [29:24], r/w, 0x0 */ - uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } pdm_dbg_0; - - /* 0xC28 : pdm_dbg_1 */ - union { - struct { - uint32_t aud_test_read : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } pdm_dbg_1; - - /* 0xC2C : pdm_dbg_2 */ - union { - struct { - uint32_t adc_fir_4s_val : 20; /* [19: 0], r/w, 0x0 */ - uint32_t adc_0_fir_4s_en : 1; /* [ 20], r/w, 0x0 */ - uint32_t adc_1_fir_4s_en : 1; /* [ 21], r/w, 0x0 */ - uint32_t adc_2_fir_4s_en : 1; /* [ 22], r/w, 0x0 */ - uint32_t adc_in_0_test_sel : 1; /* [ 23], r/w, 0x0 */ - uint32_t adc_in_1_test_sel : 1; /* [ 24], r/w, 0x0 */ - uint32_t adc_in_2_test_sel : 1; /* [ 25], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } pdm_dbg_2; - - /* 0xC30 : pdm_dbg_3 */ - union { - struct { - uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } pdm_dbg_3; - - /* 0xC34 : pdm_dbg_4 */ - union { - struct { - uint32_t adc_in_ratio_4s_val : 1; /* [ 0], r/w, 0x0 */ - uint32_t adc_in_ch0_ratio_4s_val : 1; /* [ 1], r/w, 0x0 */ - uint32_t adc_in_ch1_ratio_4s_val : 1; /* [ 2], r/w, 0x0 */ - uint32_t adc_in_ch2_ratio_4s_val : 1; /* [ 3], r/w, 0x0 */ - uint32_t pdm_in_ratio_4s_val : 1; /* [ 4], r/w, 0x0 */ - uint32_t pdm_in_ratio_4s : 1; /* [ 5], r/w, 0x0 */ - uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } pdm_dbg_4; - - /* 0xC38 : pdm_adc_s0 */ - union { - struct { - uint32_t adc_s0_volume : 9; /* [ 8: 0], r/w, 0x0 */ - uint32_t reserved_9_31 : 23; /* [31: 9], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } pdm_adc_s0; - - /* 0xC3C : pdm_adc_s1 */ - union { - struct { - uint32_t adc_s1_volume : 9; /* [ 8: 0], r/w, 0x0 */ - uint32_t reserved_9_31 : 23; /* [31: 9], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } pdm_adc_s1; - - /* 0xC40 : pdm_adc_s2 */ - union { - struct { - uint32_t adc_s2_volume : 9; /* [ 8: 0], r/w, 0x0 */ - uint32_t reserved_9_31 : 23; /* [31: 9], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } pdm_adc_s2; - - /* 0xc44 reserved */ - uint8_t RESERVED0xc44[60]; - - /* 0xC80 : pdm_rx_fifo_ctrl */ - union { - struct { - uint32_t rx_fifo_flush : 1; /* [ 0], w1c, 0x0 */ - uint32_t rxo_int_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t rxu_int_en : 1; /* [ 2], r/w, 0x0 */ - uint32_t rxa_int_en : 1; /* [ 3], r/w, 0x0 */ - uint32_t rx_drq_en : 1; /* [ 4], r/w, 0x0 */ - uint32_t rx_data_res : 1; /* [ 5], r/w, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t rx_ch_en : 3; /* [10: 8], r/w, 0x0 */ - uint32_t reserved_11_13 : 3; /* [13:11], rsvd, 0x0 */ - uint32_t rx_drq_cnt : 2; /* [15:14], r/w, 0x0 */ - uint32_t rx_trg_level : 6; /* [21:16], r/w, 0x17 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t rx_data_mode : 2; /* [25:24], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } pdm_rx_fifo_ctrl; - - /* 0xC84 : pdm_rx_fifo_status */ - union { - struct { - uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */ - uint32_t rxo_int : 1; /* [ 1], r, 0x0 */ - uint32_t rxu_int : 1; /* [ 2], r, 0x0 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t rxa_int : 1; /* [ 4], r, 0x0 */ - uint32_t reserved_5_15 : 11; /* [15: 5], rsvd, 0x0 */ - uint32_t rxa_cnt : 6; /* [21:16], r, 0x0 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t rxa : 1; /* [ 24], r, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } pdm_rx_fifo_status; - - /* 0xC88 : pdm_rx_fifo_data */ - union { - struct { - uint32_t rx_data : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } pdm_rx_fifo_data; -}; - -typedef volatile struct pdm_reg pdm_reg_t; - -#endif /* __PDM_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/pwm_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/pwm_reg.h deleted file mode 100644 index cd1d6bc6db..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/pwm_reg.h +++ /dev/null @@ -1,1502 +0,0 @@ -/** - ****************************************************************************** - * @file pwm_reg.h - * @version V1.0 - * @date 2020-11-24 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __PWM_REG_H__ -#define __PWM_REG_H__ - -#include "bl808.h" - -/* 0x00 : pwm0_config0 */ -#define PWM0_CONFIG0_OFFSET (0x00) -#define PWM_CLK_DIV PWM_CLK_DIV -#define PWM_CLK_DIV_POS (0U) -#define PWM_CLK_DIV_LEN (16U) -#define PWM_CLK_DIV_MSK (((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS) -#define PWM_CLK_DIV_UMSK (~(((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS)) -#define PWM_STOP_ON_REPT PWM_STOP_ON_REPT -#define PWM_STOP_ON_REPT_POS (19U) -#define PWM_STOP_ON_REPT_LEN (1U) -#define PWM_STOP_ON_REPT_MSK (((1U << PWM_STOP_ON_REPT_LEN) - 1) << PWM_STOP_ON_REPT_POS) -#define PWM_STOP_ON_REPT_UMSK (~(((1U << PWM_STOP_ON_REPT_LEN) - 1) << PWM_STOP_ON_REPT_POS)) -#define PWM_ADC_TRG_SRC PWM_ADC_TRG_SRC -#define PWM_ADC_TRG_SRC_POS (20U) -#define PWM_ADC_TRG_SRC_LEN (4U) -#define PWM_ADC_TRG_SRC_MSK (((1U << PWM_ADC_TRG_SRC_LEN) - 1) << PWM_ADC_TRG_SRC_POS) -#define PWM_ADC_TRG_SRC_UMSK (~(((1U << PWM_ADC_TRG_SRC_LEN) - 1) << PWM_ADC_TRG_SRC_POS)) -#define PWM_SW_BREAK_EN PWM_SW_BREAK_EN -#define PWM_SW_BREAK_EN_POS (24U) -#define PWM_SW_BREAK_EN_LEN (1U) -#define PWM_SW_BREAK_EN_MSK (((1U << PWM_SW_BREAK_EN_LEN) - 1) << PWM_SW_BREAK_EN_POS) -#define PWM_SW_BREAK_EN_UMSK (~(((1U << PWM_SW_BREAK_EN_LEN) - 1) << PWM_SW_BREAK_EN_POS)) -#define PWM_EXT_BREAK_EN PWM_EXT_BREAK_EN -#define PWM_EXT_BREAK_EN_POS (25U) -#define PWM_EXT_BREAK_EN_LEN (1U) -#define PWM_EXT_BREAK_EN_MSK (((1U << PWM_EXT_BREAK_EN_LEN) - 1) << PWM_EXT_BREAK_EN_POS) -#define PWM_EXT_BREAK_EN_UMSK (~(((1U << PWM_EXT_BREAK_EN_LEN) - 1) << PWM_EXT_BREAK_EN_POS)) -#define PWM_EXT_BREAK_PL PWM_EXT_BREAK_PL -#define PWM_EXT_BREAK_PL_POS (26U) -#define PWM_EXT_BREAK_PL_LEN (1U) -#define PWM_EXT_BREAK_PL_MSK (((1U << PWM_EXT_BREAK_PL_LEN) - 1) << PWM_EXT_BREAK_PL_POS) -#define PWM_EXT_BREAK_PL_UMSK (~(((1U << PWM_EXT_BREAK_PL_LEN) - 1) << PWM_EXT_BREAK_PL_POS)) -#define PWM_STOP_EN PWM_STOP_EN -#define PWM_STOP_EN_POS (27U) -#define PWM_STOP_EN_LEN (1U) -#define PWM_STOP_EN_MSK (((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS) -#define PWM_STOP_EN_UMSK (~(((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS)) -#define PWM_STOP_MODE PWM_STOP_MODE -#define PWM_STOP_MODE_POS (28U) -#define PWM_STOP_MODE_LEN (1U) -#define PWM_STOP_MODE_MSK (((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS) -#define PWM_STOP_MODE_UMSK (~(((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS)) -#define PWM_STS_STOP PWM_STS_STOP -#define PWM_STS_STOP_POS (29U) -#define PWM_STS_STOP_LEN (1U) -#define PWM_STS_STOP_MSK (((1U << PWM_STS_STOP_LEN) - 1) << PWM_STS_STOP_POS) -#define PWM_STS_STOP_UMSK (~(((1U << PWM_STS_STOP_LEN) - 1) << PWM_STS_STOP_POS)) -#define PWM_REG_CLK_SEL PWM_REG_CLK_SEL -#define PWM_REG_CLK_SEL_POS (30U) -#define PWM_REG_CLK_SEL_LEN (2U) -#define PWM_REG_CLK_SEL_MSK (((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS) -#define PWM_REG_CLK_SEL_UMSK (~(((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS)) - -/* 0x04 : pwm0_config1 */ -#define PWM0_CONFIG1_OFFSET (0x04) -#define PWM_CH0_PEN PWM_CH0_PEN -#define PWM_CH0_PEN_POS (0U) -#define PWM_CH0_PEN_LEN (1U) -#define PWM_CH0_PEN_MSK (((1U << PWM_CH0_PEN_LEN) - 1) << PWM_CH0_PEN_POS) -#define PWM_CH0_PEN_UMSK (~(((1U << PWM_CH0_PEN_LEN) - 1) << PWM_CH0_PEN_POS)) -#define PWM_CH0_PSI PWM_CH0_PSI -#define PWM_CH0_PSI_POS (1U) -#define PWM_CH0_PSI_LEN (1U) -#define PWM_CH0_PSI_MSK (((1U << PWM_CH0_PSI_LEN) - 1) << PWM_CH0_PSI_POS) -#define PWM_CH0_PSI_UMSK (~(((1U << PWM_CH0_PSI_LEN) - 1) << PWM_CH0_PSI_POS)) -#define PWM_CH0_NEN PWM_CH0_NEN -#define PWM_CH0_NEN_POS (2U) -#define PWM_CH0_NEN_LEN (1U) -#define PWM_CH0_NEN_MSK (((1U << PWM_CH0_NEN_LEN) - 1) << PWM_CH0_NEN_POS) -#define PWM_CH0_NEN_UMSK (~(((1U << PWM_CH0_NEN_LEN) - 1) << PWM_CH0_NEN_POS)) -#define PWM_CH0_NSI PWM_CH0_NSI -#define PWM_CH0_NSI_POS (3U) -#define PWM_CH0_NSI_LEN (1U) -#define PWM_CH0_NSI_MSK (((1U << PWM_CH0_NSI_LEN) - 1) << PWM_CH0_NSI_POS) -#define PWM_CH0_NSI_UMSK (~(((1U << PWM_CH0_NSI_LEN) - 1) << PWM_CH0_NSI_POS)) -#define PWM_CH1_PEN PWM_CH1_PEN -#define PWM_CH1_PEN_POS (4U) -#define PWM_CH1_PEN_LEN (1U) -#define PWM_CH1_PEN_MSK (((1U << PWM_CH1_PEN_LEN) - 1) << PWM_CH1_PEN_POS) -#define PWM_CH1_PEN_UMSK (~(((1U << PWM_CH1_PEN_LEN) - 1) << PWM_CH1_PEN_POS)) -#define PWM_CH1_PSI PWM_CH1_PSI -#define PWM_CH1_PSI_POS (5U) -#define PWM_CH1_PSI_LEN (1U) -#define PWM_CH1_PSI_MSK (((1U << PWM_CH1_PSI_LEN) - 1) << PWM_CH1_PSI_POS) -#define PWM_CH1_PSI_UMSK (~(((1U << PWM_CH1_PSI_LEN) - 1) << PWM_CH1_PSI_POS)) -#define PWM_CH1_NEN PWM_CH1_NEN -#define PWM_CH1_NEN_POS (6U) -#define PWM_CH1_NEN_LEN (1U) -#define PWM_CH1_NEN_MSK (((1U << PWM_CH1_NEN_LEN) - 1) << PWM_CH1_NEN_POS) -#define PWM_CH1_NEN_UMSK (~(((1U << PWM_CH1_NEN_LEN) - 1) << PWM_CH1_NEN_POS)) -#define PWM_CH1_NSI PWM_CH1_NSI -#define PWM_CH1_NSI_POS (7U) -#define PWM_CH1_NSI_LEN (1U) -#define PWM_CH1_NSI_MSK (((1U << PWM_CH1_NSI_LEN) - 1) << PWM_CH1_NSI_POS) -#define PWM_CH1_NSI_UMSK (~(((1U << PWM_CH1_NSI_LEN) - 1) << PWM_CH1_NSI_POS)) -#define PWM_CH2_PEN PWM_CH2_PEN -#define PWM_CH2_PEN_POS (8U) -#define PWM_CH2_PEN_LEN (1U) -#define PWM_CH2_PEN_MSK (((1U << PWM_CH2_PEN_LEN) - 1) << PWM_CH2_PEN_POS) -#define PWM_CH2_PEN_UMSK (~(((1U << PWM_CH2_PEN_LEN) - 1) << PWM_CH2_PEN_POS)) -#define PWM_CH2_PSI PWM_CH2_PSI -#define PWM_CH2_PSI_POS (9U) -#define PWM_CH2_PSI_LEN (1U) -#define PWM_CH2_PSI_MSK (((1U << PWM_CH2_PSI_LEN) - 1) << PWM_CH2_PSI_POS) -#define PWM_CH2_PSI_UMSK (~(((1U << PWM_CH2_PSI_LEN) - 1) << PWM_CH2_PSI_POS)) -#define PWM_CH2_NEN PWM_CH2_NEN -#define PWM_CH2_NEN_POS (10U) -#define PWM_CH2_NEN_LEN (1U) -#define PWM_CH2_NEN_MSK (((1U << PWM_CH2_NEN_LEN) - 1) << PWM_CH2_NEN_POS) -#define PWM_CH2_NEN_UMSK (~(((1U << PWM_CH2_NEN_LEN) - 1) << PWM_CH2_NEN_POS)) -#define PWM_CH2_NSI PWM_CH2_NSI -#define PWM_CH2_NSI_POS (11U) -#define PWM_CH2_NSI_LEN (1U) -#define PWM_CH2_NSI_MSK (((1U << PWM_CH2_NSI_LEN) - 1) << PWM_CH2_NSI_POS) -#define PWM_CH2_NSI_UMSK (~(((1U << PWM_CH2_NSI_LEN) - 1) << PWM_CH2_NSI_POS)) -#define PWM_CH3_PEN PWM_CH3_PEN -#define PWM_CH3_PEN_POS (12U) -#define PWM_CH3_PEN_LEN (1U) -#define PWM_CH3_PEN_MSK (((1U << PWM_CH3_PEN_LEN) - 1) << PWM_CH3_PEN_POS) -#define PWM_CH3_PEN_UMSK (~(((1U << PWM_CH3_PEN_LEN) - 1) << PWM_CH3_PEN_POS)) -#define PWM_CH3_PSI PWM_CH3_PSI -#define PWM_CH3_PSI_POS (13U) -#define PWM_CH3_PSI_LEN (1U) -#define PWM_CH3_PSI_MSK (((1U << PWM_CH3_PSI_LEN) - 1) << PWM_CH3_PSI_POS) -#define PWM_CH3_PSI_UMSK (~(((1U << PWM_CH3_PSI_LEN) - 1) << PWM_CH3_PSI_POS)) -#define PWM_CH3_NEN PWM_CH3_NEN -#define PWM_CH3_NEN_POS (14U) -#define PWM_CH3_NEN_LEN (1U) -#define PWM_CH3_NEN_MSK (((1U << PWM_CH3_NEN_LEN) - 1) << PWM_CH3_NEN_POS) -#define PWM_CH3_NEN_UMSK (~(((1U << PWM_CH3_NEN_LEN) - 1) << PWM_CH3_NEN_POS)) -#define PWM_CH3_NSI PWM_CH3_NSI -#define PWM_CH3_NSI_POS (15U) -#define PWM_CH3_NSI_LEN (1U) -#define PWM_CH3_NSI_MSK (((1U << PWM_CH3_NSI_LEN) - 1) << PWM_CH3_NSI_POS) -#define PWM_CH3_NSI_UMSK (~(((1U << PWM_CH3_NSI_LEN) - 1) << PWM_CH3_NSI_POS)) -#define PWM_CH0_PPL PWM_CH0_PPL -#define PWM_CH0_PPL_POS (16U) -#define PWM_CH0_PPL_LEN (1U) -#define PWM_CH0_PPL_MSK (((1U << PWM_CH0_PPL_LEN) - 1) << PWM_CH0_PPL_POS) -#define PWM_CH0_PPL_UMSK (~(((1U << PWM_CH0_PPL_LEN) - 1) << PWM_CH0_PPL_POS)) -#define PWM_CH0_NPL PWM_CH0_NPL -#define PWM_CH0_NPL_POS (17U) -#define PWM_CH0_NPL_LEN (1U) -#define PWM_CH0_NPL_MSK (((1U << PWM_CH0_NPL_LEN) - 1) << PWM_CH0_NPL_POS) -#define PWM_CH0_NPL_UMSK (~(((1U << PWM_CH0_NPL_LEN) - 1) << PWM_CH0_NPL_POS)) -#define PWM_CH1_PPL PWM_CH1_PPL -#define PWM_CH1_PPL_POS (18U) -#define PWM_CH1_PPL_LEN (1U) -#define PWM_CH1_PPL_MSK (((1U << PWM_CH1_PPL_LEN) - 1) << PWM_CH1_PPL_POS) -#define PWM_CH1_PPL_UMSK (~(((1U << PWM_CH1_PPL_LEN) - 1) << PWM_CH1_PPL_POS)) -#define PWM_CH1_NPL PWM_CH1_NPL -#define PWM_CH1_NPL_POS (19U) -#define PWM_CH1_NPL_LEN (1U) -#define PWM_CH1_NPL_MSK (((1U << PWM_CH1_NPL_LEN) - 1) << PWM_CH1_NPL_POS) -#define PWM_CH1_NPL_UMSK (~(((1U << PWM_CH1_NPL_LEN) - 1) << PWM_CH1_NPL_POS)) -#define PWM_CH2_PPL PWM_CH2_PPL -#define PWM_CH2_PPL_POS (20U) -#define PWM_CH2_PPL_LEN (1U) -#define PWM_CH2_PPL_MSK (((1U << PWM_CH2_PPL_LEN) - 1) << PWM_CH2_PPL_POS) -#define PWM_CH2_PPL_UMSK (~(((1U << PWM_CH2_PPL_LEN) - 1) << PWM_CH2_PPL_POS)) -#define PWM_CH2_NPL PWM_CH2_NPL -#define PWM_CH2_NPL_POS (21U) -#define PWM_CH2_NPL_LEN (1U) -#define PWM_CH2_NPL_MSK (((1U << PWM_CH2_NPL_LEN) - 1) << PWM_CH2_NPL_POS) -#define PWM_CH2_NPL_UMSK (~(((1U << PWM_CH2_NPL_LEN) - 1) << PWM_CH2_NPL_POS)) -#define PWM_CH3_PPL PWM_CH3_PPL -#define PWM_CH3_PPL_POS (22U) -#define PWM_CH3_PPL_LEN (1U) -#define PWM_CH3_PPL_MSK (((1U << PWM_CH3_PPL_LEN) - 1) << PWM_CH3_PPL_POS) -#define PWM_CH3_PPL_UMSK (~(((1U << PWM_CH3_PPL_LEN) - 1) << PWM_CH3_PPL_POS)) -#define PWM_CH3_NPL PWM_CH3_NPL -#define PWM_CH3_NPL_POS (23U) -#define PWM_CH3_NPL_LEN (1U) -#define PWM_CH3_NPL_MSK (((1U << PWM_CH3_NPL_LEN) - 1) << PWM_CH3_NPL_POS) -#define PWM_CH3_NPL_UMSK (~(((1U << PWM_CH3_NPL_LEN) - 1) << PWM_CH3_NPL_POS)) -#define PWM_CH0_PBS PWM_CH0_PBS -#define PWM_CH0_PBS_POS (24U) -#define PWM_CH0_PBS_LEN (1U) -#define PWM_CH0_PBS_MSK (((1U << PWM_CH0_PBS_LEN) - 1) << PWM_CH0_PBS_POS) -#define PWM_CH0_PBS_UMSK (~(((1U << PWM_CH0_PBS_LEN) - 1) << PWM_CH0_PBS_POS)) -#define PWM_CH0_NBS PWM_CH0_NBS -#define PWM_CH0_NBS_POS (25U) -#define PWM_CH0_NBS_LEN (1U) -#define PWM_CH0_NBS_MSK (((1U << PWM_CH0_NBS_LEN) - 1) << PWM_CH0_NBS_POS) -#define PWM_CH0_NBS_UMSK (~(((1U << PWM_CH0_NBS_LEN) - 1) << PWM_CH0_NBS_POS)) -#define PWM_CH1_PBS PWM_CH1_PBS -#define PWM_CH1_PBS_POS (26U) -#define PWM_CH1_PBS_LEN (1U) -#define PWM_CH1_PBS_MSK (((1U << PWM_CH1_PBS_LEN) - 1) << PWM_CH1_PBS_POS) -#define PWM_CH1_PBS_UMSK (~(((1U << PWM_CH1_PBS_LEN) - 1) << PWM_CH1_PBS_POS)) -#define PWM_CH1_NBS PWM_CH1_NBS -#define PWM_CH1_NBS_POS (27U) -#define PWM_CH1_NBS_LEN (1U) -#define PWM_CH1_NBS_MSK (((1U << PWM_CH1_NBS_LEN) - 1) << PWM_CH1_NBS_POS) -#define PWM_CH1_NBS_UMSK (~(((1U << PWM_CH1_NBS_LEN) - 1) << PWM_CH1_NBS_POS)) -#define PWM_CH2_PBS PWM_CH2_PBS -#define PWM_CH2_PBS_POS (28U) -#define PWM_CH2_PBS_LEN (1U) -#define PWM_CH2_PBS_MSK (((1U << PWM_CH2_PBS_LEN) - 1) << PWM_CH2_PBS_POS) -#define PWM_CH2_PBS_UMSK (~(((1U << PWM_CH2_PBS_LEN) - 1) << PWM_CH2_PBS_POS)) -#define PWM_CH2_NBS PWM_CH2_NBS -#define PWM_CH2_NBS_POS (29U) -#define PWM_CH2_NBS_LEN (1U) -#define PWM_CH2_NBS_MSK (((1U << PWM_CH2_NBS_LEN) - 1) << PWM_CH2_NBS_POS) -#define PWM_CH2_NBS_UMSK (~(((1U << PWM_CH2_NBS_LEN) - 1) << PWM_CH2_NBS_POS)) -#define PWM_CH3_PBS PWM_CH3_PBS -#define PWM_CH3_PBS_POS (30U) -#define PWM_CH3_PBS_LEN (1U) -#define PWM_CH3_PBS_MSK (((1U << PWM_CH3_PBS_LEN) - 1) << PWM_CH3_PBS_POS) -#define PWM_CH3_PBS_UMSK (~(((1U << PWM_CH3_PBS_LEN) - 1) << PWM_CH3_PBS_POS)) -#define PWM_CH3_NBS PWM_CH3_NBS -#define PWM_CH3_NBS_POS (31U) -#define PWM_CH3_NBS_LEN (1U) -#define PWM_CH3_NBS_MSK (((1U << PWM_CH3_NBS_LEN) - 1) << PWM_CH3_NBS_POS) -#define PWM_CH3_NBS_UMSK (~(((1U << PWM_CH3_NBS_LEN) - 1) << PWM_CH3_NBS_POS)) -/* 0x08 : pwm0_period */ -#define PWM0_PERIOD_OFFSET (0x08) -#define PWM_PERIOD PWM_PERIOD -#define PWM_PERIOD_POS (0U) -#define PWM_PERIOD_LEN (16U) -#define PWM_PERIOD_MSK (((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS) -#define PWM_PERIOD_UMSK (~(((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS)) -#define PWM_INT_PERIOD_CNT PWM_INT_PERIOD_CNT -#define PWM_INT_PERIOD_CNT_POS (16U) -#define PWM_INT_PERIOD_CNT_LEN (16U) -#define PWM_INT_PERIOD_CNT_MSK (((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS) -#define PWM_INT_PERIOD_CNT_UMSK (~(((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS)) - -/* 0x0C : pwm0_dead_time */ -#define PWM0_DEAD_TIME_OFFSET (0x0C) -#define PWM_CH0_DTG PWM_CH0_DTG -#define PWM_CH0_DTG_POS (0U) -#define PWM_CH0_DTG_LEN (8U) -#define PWM_CH0_DTG_MSK (((1U << PWM_CH0_DTG_LEN) - 1) << PWM_CH0_DTG_POS) -#define PWM_CH0_DTG_UMSK (~(((1U << PWM_CH0_DTG_LEN) - 1) << PWM_CH0_DTG_POS)) -#define PWM_CH1_DTG PWM_CH1_DTG -#define PWM_CH1_DTG_POS (8U) -#define PWM_CH1_DTG_LEN (8U) -#define PWM_CH1_DTG_MSK (((1U << PWM_CH1_DTG_LEN) - 1) << PWM_CH1_DTG_POS) -#define PWM_CH1_DTG_UMSK (~(((1U << PWM_CH1_DTG_LEN) - 1) << PWM_CH1_DTG_POS)) -#define PWM_CH2_DTG PWM_CH2_DTG -#define PWM_CH2_DTG_POS (16U) -#define PWM_CH2_DTG_LEN (8U) -#define PWM_CH2_DTG_MSK (((1U << PWM_CH2_DTG_LEN) - 1) << PWM_CH2_DTG_POS) -#define PWM_CH2_DTG_UMSK (~(((1U << PWM_CH2_DTG_LEN) - 1) << PWM_CH2_DTG_POS)) -#define PWM_CH3_DTG PWM_CH3_DTG -#define PWM_CH3_DTG_POS (24U) -#define PWM_CH3_DTG_LEN (8U) -#define PWM_CH3_DTG_MSK (((1U << PWM_CH3_DTG_LEN) - 1) << PWM_CH3_DTG_POS) -#define PWM_CH3_DTG_UMSK (~(((1U << PWM_CH3_DTG_LEN) - 1) << PWM_CH3_DTG_POS)) - -/* 0x10 : pwm0_ch0_thre */ -#define PWM0_CH0_THRE_OFFSET (0x10) -#define PWM_CH0_THREL PWM_CH0_THREL -#define PWM_CH0_THREL_POS (0U) -#define PWM_CH0_THREL_LEN (16U) -#define PWM_CH0_THREL_MSK (((1U << PWM_CH0_THREL_LEN) - 1) << PWM_CH0_THREL_POS) -#define PWM_CH0_THREL_UMSK (~(((1U << PWM_CH0_THREL_LEN) - 1) << PWM_CH0_THREL_POS)) -#define PWM_CH0_THREH PWM_CH0_THREH -#define PWM_CH0_THREH_POS (16U) -#define PWM_CH0_THREH_LEN (16U) -#define PWM_CH0_THREH_MSK (((1U << PWM_CH0_THREH_LEN) - 1) << PWM_CH0_THREH_POS) -#define PWM_CH0_THREH_UMSK (~(((1U << PWM_CH0_THREH_LEN) - 1) << PWM_CH0_THREH_POS)) - -/* 0x14 : pwm0_ch1_thre */ -#define PWM0_CH1_THRE_OFFSET (0x14) -#define PWM_CH1_THREL PWM_CH1_THREL -#define PWM_CH1_THREL_POS (0U) -#define PWM_CH1_THREL_LEN (16U) -#define PWM_CH1_THREL_MSK (((1U << PWM_CH1_THREL_LEN) - 1) << PWM_CH1_THREL_POS) -#define PWM_CH1_THREL_UMSK (~(((1U << PWM_CH1_THREL_LEN) - 1) << PWM_CH1_THREL_POS)) -#define PWM_CH1_THREH PWM_CH1_THREH -#define PWM_CH1_THREH_POS (16U) -#define PWM_CH1_THREH_LEN (16U) -#define PWM_CH1_THREH_MSK (((1U << PWM_CH1_THREH_LEN) - 1) << PWM_CH1_THREH_POS) -#define PWM_CH1_THREH_UMSK (~(((1U << PWM_CH1_THREH_LEN) - 1) << PWM_CH1_THREH_POS)) - -/* 0x18 : pwm0_ch2_thre */ -#define PWM0_CH2_THRE_OFFSET (0x18) -#define PWM_CH2_THREL PWM_CH2_THREL -#define PWM_CH2_THREL_POS (0U) -#define PWM_CH2_THREL_LEN (16U) -#define PWM_CH2_THREL_MSK (((1U << PWM_CH2_THREL_LEN) - 1) << PWM_CH2_THREL_POS) -#define PWM_CH2_THREL_UMSK (~(((1U << PWM_CH2_THREL_LEN) - 1) << PWM_CH2_THREL_POS)) -#define PWM_CH2_THREH PWM_CH2_THREH -#define PWM_CH2_THREH_POS (16U) -#define PWM_CH2_THREH_LEN (16U) -#define PWM_CH2_THREH_MSK (((1U << PWM_CH2_THREH_LEN) - 1) << PWM_CH2_THREH_POS) -#define PWM_CH2_THREH_UMSK (~(((1U << PWM_CH2_THREH_LEN) - 1) << PWM_CH2_THREH_POS)) - -/* 0x1C : pwm0_ch3_thre */ -#define PWM0_CH3_THRE_OFFSET (0x1C) -#define PWM_CH3_THREL PWM_CH3_THREL -#define PWM_CH3_THREL_POS (0U) -#define PWM_CH3_THREL_LEN (16U) -#define PWM_CH3_THREL_MSK (((1U << PWM_CH3_THREL_LEN) - 1) << PWM_CH3_THREL_POS) -#define PWM_CH3_THREL_UMSK (~(((1U << PWM_CH3_THREL_LEN) - 1) << PWM_CH3_THREL_POS)) -#define PWM_CH3_THREH PWM_CH3_THREH -#define PWM_CH3_THREH_POS (16U) -#define PWM_CH3_THREH_LEN (16U) -#define PWM_CH3_THREH_MSK (((1U << PWM_CH3_THREH_LEN) - 1) << PWM_CH3_THREH_POS) -#define PWM_CH3_THREH_UMSK (~(((1U << PWM_CH3_THREH_LEN) - 1) << PWM_CH3_THREH_POS)) - -/* 0x20 : pwm0_int_sts */ -#define PWM0_INT_STS_OFFSET (0x20) -#define PWM_CH0L_INT PWM_CH0L_INT -#define PWM_CH0L_INT_POS (0U) -#define PWM_CH0L_INT_LEN (1U) -#define PWM_CH0L_INT_MSK (((1U << PWM_CH0L_INT_LEN) - 1) << PWM_CH0L_INT_POS) -#define PWM_CH0L_INT_UMSK (~(((1U << PWM_CH0L_INT_LEN) - 1) << PWM_CH0L_INT_POS)) -#define PWM_CH0H_INT PWM_CH0H_INT -#define PWM_CH0H_INT_POS (1U) -#define PWM_CH0H_INT_LEN (1U) -#define PWM_CH0H_INT_MSK (((1U << PWM_CH0H_INT_LEN) - 1) << PWM_CH0H_INT_POS) -#define PWM_CH0H_INT_UMSK (~(((1U << PWM_CH0H_INT_LEN) - 1) << PWM_CH0H_INT_POS)) -#define PWM_CH1L_INT PWM_CH1L_INT -#define PWM_CH1L_INT_POS (2U) -#define PWM_CH1L_INT_LEN (1U) -#define PWM_CH1L_INT_MSK (((1U << PWM_CH1L_INT_LEN) - 1) << PWM_CH1L_INT_POS) -#define PWM_CH1L_INT_UMSK (~(((1U << PWM_CH1L_INT_LEN) - 1) << PWM_CH1L_INT_POS)) -#define PWM_CH1H_INT PWM_CH1H_INT -#define PWM_CH1H_INT_POS (3U) -#define PWM_CH1H_INT_LEN (1U) -#define PWM_CH1H_INT_MSK (((1U << PWM_CH1H_INT_LEN) - 1) << PWM_CH1H_INT_POS) -#define PWM_CH1H_INT_UMSK (~(((1U << PWM_CH1H_INT_LEN) - 1) << PWM_CH1H_INT_POS)) -#define PWM_CH2L_INT PWM_CH2L_INT -#define PWM_CH2L_INT_POS (4U) -#define PWM_CH2L_INT_LEN (1U) -#define PWM_CH2L_INT_MSK (((1U << PWM_CH2L_INT_LEN) - 1) << PWM_CH2L_INT_POS) -#define PWM_CH2L_INT_UMSK (~(((1U << PWM_CH2L_INT_LEN) - 1) << PWM_CH2L_INT_POS)) -#define PWM_CH2H_INT PWM_CH2H_INT -#define PWM_CH2H_INT_POS (5U) -#define PWM_CH2H_INT_LEN (1U) -#define PWM_CH2H_INT_MSK (((1U << PWM_CH2H_INT_LEN) - 1) << PWM_CH2H_INT_POS) -#define PWM_CH2H_INT_UMSK (~(((1U << PWM_CH2H_INT_LEN) - 1) << PWM_CH2H_INT_POS)) -#define PWM_CH3L_INT PWM_CH3L_INT -#define PWM_CH3L_INT_POS (6U) -#define PWM_CH3L_INT_LEN (1U) -#define PWM_CH3L_INT_MSK (((1U << PWM_CH3L_INT_LEN) - 1) << PWM_CH3L_INT_POS) -#define PWM_CH3L_INT_UMSK (~(((1U << PWM_CH3L_INT_LEN) - 1) << PWM_CH3L_INT_POS)) -#define PWM_CH3H_INT PWM_CH3H_INT -#define PWM_CH3H_INT_POS (7U) -#define PWM_CH3H_INT_LEN (1U) -#define PWM_CH3H_INT_MSK (((1U << PWM_CH3H_INT_LEN) - 1) << PWM_CH3H_INT_POS) -#define PWM_CH3H_INT_UMSK (~(((1U << PWM_CH3H_INT_LEN) - 1) << PWM_CH3H_INT_POS)) -#define PWM_PRDE_INT PWM_PRDE_INT -#define PWM_PRDE_INT_POS (8U) -#define PWM_PRDE_INT_LEN (1U) -#define PWM_PRDE_INT_MSK (((1U << PWM_PRDE_INT_LEN) - 1) << PWM_PRDE_INT_POS) -#define PWM_PRDE_INT_UMSK (~(((1U << PWM_PRDE_INT_LEN) - 1) << PWM_PRDE_INT_POS)) -#define PWM_BRK_INT PWM_BRK_INT -#define PWM_BRK_INT_POS (9U) -#define PWM_BRK_INT_LEN (1U) -#define PWM_BRK_INT_MSK (((1U << PWM_BRK_INT_LEN) - 1) << PWM_BRK_INT_POS) -#define PWM_BRK_INT_UMSK (~(((1U << PWM_BRK_INT_LEN) - 1) << PWM_BRK_INT_POS)) -#define PWM_REPT_INT PWM_REPT_INT -#define PWM_REPT_INT_POS (10U) -#define PWM_REPT_INT_LEN (1U) -#define PWM_REPT_INT_MSK (((1U << PWM_REPT_INT_LEN) - 1) << PWM_REPT_INT_POS) -#define PWM_REPT_INT_UMSK (~(((1U << PWM_REPT_INT_LEN) - 1) << PWM_REPT_INT_POS)) - -/* 0x24 : pwm0_int_mask */ -#define PWM0_INT_MASK_OFFSET (0x24) -#define PWM_CR_PWM_CH0L_MASK PWM_CR_PWM_CH0L_MASK -#define PWM_CR_PWM_CH0L_MASK_POS (0U) -#define PWM_CR_PWM_CH0L_MASK_LEN (1U) -#define PWM_CR_PWM_CH0L_MASK_MSK (((1U << PWM_CR_PWM_CH0L_MASK_LEN) - 1) << PWM_CR_PWM_CH0L_MASK_POS) -#define PWM_CR_PWM_CH0L_MASK_UMSK (~(((1U << PWM_CR_PWM_CH0L_MASK_LEN) - 1) << PWM_CR_PWM_CH0L_MASK_POS)) -#define PWM_CR_PWM_CH0H_MASK PWM_CR_PWM_CH0H_MASK -#define PWM_CR_PWM_CH0H_MASK_POS (1U) -#define PWM_CR_PWM_CH0H_MASK_LEN (1U) -#define PWM_CR_PWM_CH0H_MASK_MSK (((1U << PWM_CR_PWM_CH0H_MASK_LEN) - 1) << PWM_CR_PWM_CH0H_MASK_POS) -#define PWM_CR_PWM_CH0H_MASK_UMSK (~(((1U << PWM_CR_PWM_CH0H_MASK_LEN) - 1) << PWM_CR_PWM_CH0H_MASK_POS)) -#define PWM_CR_PWM_CH1L_MASK PWM_CR_PWM_CH1L_MASK -#define PWM_CR_PWM_CH1L_MASK_POS (2U) -#define PWM_CR_PWM_CH1L_MASK_LEN (1U) -#define PWM_CR_PWM_CH1L_MASK_MSK (((1U << PWM_CR_PWM_CH1L_MASK_LEN) - 1) << PWM_CR_PWM_CH1L_MASK_POS) -#define PWM_CR_PWM_CH1L_MASK_UMSK (~(((1U << PWM_CR_PWM_CH1L_MASK_LEN) - 1) << PWM_CR_PWM_CH1L_MASK_POS)) -#define PWM_CR_PWM_CH1H_MASK PWM_CR_PWM_CH1H_MASK -#define PWM_CR_PWM_CH1H_MASK_POS (3U) -#define PWM_CR_PWM_CH1H_MASK_LEN (1U) -#define PWM_CR_PWM_CH1H_MASK_MSK (((1U << PWM_CR_PWM_CH1H_MASK_LEN) - 1) << PWM_CR_PWM_CH1H_MASK_POS) -#define PWM_CR_PWM_CH1H_MASK_UMSK (~(((1U << PWM_CR_PWM_CH1H_MASK_LEN) - 1) << PWM_CR_PWM_CH1H_MASK_POS)) -#define PWM_CR_PWM_CH2L_MASK PWM_CR_PWM_CH2L_MASK -#define PWM_CR_PWM_CH2L_MASK_POS (4U) -#define PWM_CR_PWM_CH2L_MASK_LEN (1U) -#define PWM_CR_PWM_CH2L_MASK_MSK (((1U << PWM_CR_PWM_CH2L_MASK_LEN) - 1) << PWM_CR_PWM_CH2L_MASK_POS) -#define PWM_CR_PWM_CH2L_MASK_UMSK (~(((1U << PWM_CR_PWM_CH2L_MASK_LEN) - 1) << PWM_CR_PWM_CH2L_MASK_POS)) -#define PWM_CR_PWM_CH2H_MASK PWM_CR_PWM_CH2H_MASK -#define PWM_CR_PWM_CH2H_MASK_POS (5U) -#define PWM_CR_PWM_CH2H_MASK_LEN (1U) -#define PWM_CR_PWM_CH2H_MASK_MSK (((1U << PWM_CR_PWM_CH2H_MASK_LEN) - 1) << PWM_CR_PWM_CH2H_MASK_POS) -#define PWM_CR_PWM_CH2H_MASK_UMSK (~(((1U << PWM_CR_PWM_CH2H_MASK_LEN) - 1) << PWM_CR_PWM_CH2H_MASK_POS)) -#define PWM_CR_PWM_CH3L_MASK PWM_CR_PWM_CH3L_MASK -#define PWM_CR_PWM_CH3L_MASK_POS (6U) -#define PWM_CR_PWM_CH3L_MASK_LEN (1U) -#define PWM_CR_PWM_CH3L_MASK_MSK (((1U << PWM_CR_PWM_CH3L_MASK_LEN) - 1) << PWM_CR_PWM_CH3L_MASK_POS) -#define PWM_CR_PWM_CH3L_MASK_UMSK (~(((1U << PWM_CR_PWM_CH3L_MASK_LEN) - 1) << PWM_CR_PWM_CH3L_MASK_POS)) -#define PWM_CR_PWM_CH3H_MASK PWM_CR_PWM_CH3H_MASK -#define PWM_CR_PWM_CH3H_MASK_POS (7U) -#define PWM_CR_PWM_CH3H_MASK_LEN (1U) -#define PWM_CR_PWM_CH3H_MASK_MSK (((1U << PWM_CR_PWM_CH3H_MASK_LEN) - 1) << PWM_CR_PWM_CH3H_MASK_POS) -#define PWM_CR_PWM_CH3H_MASK_UMSK (~(((1U << PWM_CR_PWM_CH3H_MASK_LEN) - 1) << PWM_CR_PWM_CH3H_MASK_POS)) -#define PWM_CR_PWM_PRDE_MASK PWM_CR_PWM_PRDE_MASK -#define PWM_CR_PWM_PRDE_MASK_POS (8U) -#define PWM_CR_PWM_PRDE_MASK_LEN (1U) -#define PWM_CR_PWM_PRDE_MASK_MSK (((1U << PWM_CR_PWM_PRDE_MASK_LEN) - 1) << PWM_CR_PWM_PRDE_MASK_POS) -#define PWM_CR_PWM_PRDE_MASK_UMSK (~(((1U << PWM_CR_PWM_PRDE_MASK_LEN) - 1) << PWM_CR_PWM_PRDE_MASK_POS)) -#define PWM_CR_PWM_BRK_MASK PWM_CR_PWM_BRK_MASK -#define PWM_CR_PWM_BRK_MASK_POS (9U) -#define PWM_CR_PWM_BRK_MASK_LEN (1U) -#define PWM_CR_PWM_BRK_MASK_MSK (((1U << PWM_CR_PWM_BRK_MASK_LEN) - 1) << PWM_CR_PWM_BRK_MASK_POS) -#define PWM_CR_PWM_BRK_MASK_UMSK (~(((1U << PWM_CR_PWM_BRK_MASK_LEN) - 1) << PWM_CR_PWM_BRK_MASK_POS)) -#define PWM_CR_PWM_REPT_MASK PWM_CR_PWM_REPT_MASK -#define PWM_CR_PWM_REPT_MASK_POS (10U) -#define PWM_CR_PWM_REPT_MASK_LEN (1U) -#define PWM_CR_PWM_REPT_MASK_MSK (((1U << PWM_CR_PWM_REPT_MASK_LEN) - 1) << PWM_CR_PWM_REPT_MASK_POS) -#define PWM_CR_PWM_REPT_MASK_UMSK (~(((1U << PWM_CR_PWM_REPT_MASK_LEN) - 1) << PWM_CR_PWM_REPT_MASK_POS)) - -/* 0x28 : pwm0_int_clear */ -#define PWM0_INT_CLEAR_OFFSET (0x28) -#define PWM_CR_PWM_CH0L_CLR PWM_CR_PWM_CH0L_CLR -#define PWM_CR_PWM_CH0L_CLR_POS (0U) -#define PWM_CR_PWM_CH0L_CLR_LEN (1U) -#define PWM_CR_PWM_CH0L_CLR_MSK (((1U << PWM_CR_PWM_CH0L_CLR_LEN) - 1) << PWM_CR_PWM_CH0L_CLR_POS) -#define PWM_CR_PWM_CH0L_CLR_UMSK (~(((1U << PWM_CR_PWM_CH0L_CLR_LEN) - 1) << PWM_CR_PWM_CH0L_CLR_POS)) -#define PWM_CR_PWM_CH0H_CLR PWM_CR_PWM_CH0H_CLR -#define PWM_CR_PWM_CH0H_CLR_POS (1U) -#define PWM_CR_PWM_CH0H_CLR_LEN (1U) -#define PWM_CR_PWM_CH0H_CLR_MSK (((1U << PWM_CR_PWM_CH0H_CLR_LEN) - 1) << PWM_CR_PWM_CH0H_CLR_POS) -#define PWM_CR_PWM_CH0H_CLR_UMSK (~(((1U << PWM_CR_PWM_CH0H_CLR_LEN) - 1) << PWM_CR_PWM_CH0H_CLR_POS)) -#define PWM_CR_PWM_CH1L_CLR PWM_CR_PWM_CH1L_CLR -#define PWM_CR_PWM_CH1L_CLR_POS (2U) -#define PWM_CR_PWM_CH1L_CLR_LEN (1U) -#define PWM_CR_PWM_CH1L_CLR_MSK (((1U << PWM_CR_PWM_CH1L_CLR_LEN) - 1) << PWM_CR_PWM_CH1L_CLR_POS) -#define PWM_CR_PWM_CH1L_CLR_UMSK (~(((1U << PWM_CR_PWM_CH1L_CLR_LEN) - 1) << PWM_CR_PWM_CH1L_CLR_POS)) -#define PWM_CR_PWM_CH1H_CLR PWM_CR_PWM_CH1H_CLR -#define PWM_CR_PWM_CH1H_CLR_POS (3U) -#define PWM_CR_PWM_CH1H_CLR_LEN (1U) -#define PWM_CR_PWM_CH1H_CLR_MSK (((1U << PWM_CR_PWM_CH1H_CLR_LEN) - 1) << PWM_CR_PWM_CH1H_CLR_POS) -#define PWM_CR_PWM_CH1H_CLR_UMSK (~(((1U << PWM_CR_PWM_CH1H_CLR_LEN) - 1) << PWM_CR_PWM_CH1H_CLR_POS)) -#define PWM_CR_PWM_CH2L_CLR PWM_CR_PWM_CH2L_CLR -#define PWM_CR_PWM_CH2L_CLR_POS (4U) -#define PWM_CR_PWM_CH2L_CLR_LEN (1U) -#define PWM_CR_PWM_CH2L_CLR_MSK (((1U << PWM_CR_PWM_CH2L_CLR_LEN) - 1) << PWM_CR_PWM_CH2L_CLR_POS) -#define PWM_CR_PWM_CH2L_CLR_UMSK (~(((1U << PWM_CR_PWM_CH2L_CLR_LEN) - 1) << PWM_CR_PWM_CH2L_CLR_POS)) -#define PWM_CR_PWM_CH2H_CLR PWM_CR_PWM_CH2H_CLR -#define PWM_CR_PWM_CH2H_CLR_POS (5U) -#define PWM_CR_PWM_CH2H_CLR_LEN (1U) -#define PWM_CR_PWM_CH2H_CLR_MSK (((1U << PWM_CR_PWM_CH2H_CLR_LEN) - 1) << PWM_CR_PWM_CH2H_CLR_POS) -#define PWM_CR_PWM_CH2H_CLR_UMSK (~(((1U << PWM_CR_PWM_CH2H_CLR_LEN) - 1) << PWM_CR_PWM_CH2H_CLR_POS)) -#define PWM_CR_PWM_CH3L_CLR PWM_CR_PWM_CH3L_CLR -#define PWM_CR_PWM_CH3L_CLR_POS (6U) -#define PWM_CR_PWM_CH3L_CLR_LEN (1U) -#define PWM_CR_PWM_CH3L_CLR_MSK (((1U << PWM_CR_PWM_CH3L_CLR_LEN) - 1) << PWM_CR_PWM_CH3L_CLR_POS) -#define PWM_CR_PWM_CH3L_CLR_UMSK (~(((1U << PWM_CR_PWM_CH3L_CLR_LEN) - 1) << PWM_CR_PWM_CH3L_CLR_POS)) -#define PWM_CR_PWM_CH3H_CLR PWM_CR_PWM_CH3H_CLR -#define PWM_CR_PWM_CH3H_CLR_POS (7U) -#define PWM_CR_PWM_CH3H_CLR_LEN (1U) -#define PWM_CR_PWM_CH3H_CLR_MSK (((1U << PWM_CR_PWM_CH3H_CLR_LEN) - 1) << PWM_CR_PWM_CH3H_CLR_POS) -#define PWM_CR_PWM_CH3H_CLR_UMSK (~(((1U << PWM_CR_PWM_CH3H_CLR_LEN) - 1) << PWM_CR_PWM_CH3H_CLR_POS)) -#define PWM_CR_PWM_PRDE_CLR PWM_CR_PWM_PRDE_CLR -#define PWM_CR_PWM_PRDE_CLR_POS (8U) -#define PWM_CR_PWM_PRDE_CLR_LEN (1U) -#define PWM_CR_PWM_PRDE_CLR_MSK (((1U << PWM_CR_PWM_PRDE_CLR_LEN) - 1) << PWM_CR_PWM_PRDE_CLR_POS) -#define PWM_CR_PWM_PRDE_CLR_UMSK (~(((1U << PWM_CR_PWM_PRDE_CLR_LEN) - 1) << PWM_CR_PWM_PRDE_CLR_POS)) -#define PWM_CR_PWM_BRK_CLR PWM_CR_PWM_BRK_CLR -#define PWM_CR_PWM_BRK_CLR_POS (9U) -#define PWM_CR_PWM_BRK_CLR_LEN (1U) -#define PWM_CR_PWM_BRK_CLR_MSK (((1U << PWM_CR_PWM_BRK_CLR_LEN) - 1) << PWM_CR_PWM_BRK_CLR_POS) -#define PWM_CR_PWM_BRK_CLR_UMSK (~(((1U << PWM_CR_PWM_BRK_CLR_LEN) - 1) << PWM_CR_PWM_BRK_CLR_POS)) -#define PWM_CR_PWM_REPT_CLR PWM_CR_PWM_REPT_CLR -#define PWM_CR_PWM_REPT_CLR_POS (10U) -#define PWM_CR_PWM_REPT_CLR_LEN (1U) -#define PWM_CR_PWM_REPT_CLR_MSK (((1U << PWM_CR_PWM_REPT_CLR_LEN) - 1) << PWM_CR_PWM_REPT_CLR_POS) -#define PWM_CR_PWM_REPT_CLR_UMSK (~(((1U << PWM_CR_PWM_REPT_CLR_LEN) - 1) << PWM_CR_PWM_REPT_CLR_POS)) - -/* 0x2C : pwm0_int_en */ -#define PWM0_INT_EN_OFFSET (0x2C) -#define PWM_CR_PWM_CH0L_EN PWM_CR_PWM_CH0L_EN -#define PWM_CR_PWM_CH0L_EN_POS (0U) -#define PWM_CR_PWM_CH0L_EN_LEN (1U) -#define PWM_CR_PWM_CH0L_EN_MSK (((1U << PWM_CR_PWM_CH0L_EN_LEN) - 1) << PWM_CR_PWM_CH0L_EN_POS) -#define PWM_CR_PWM_CH0L_EN_UMSK (~(((1U << PWM_CR_PWM_CH0L_EN_LEN) - 1) << PWM_CR_PWM_CH0L_EN_POS)) -#define PWM_CR_PWM_CH0H_EN PWM_CR_PWM_CH0H_EN -#define PWM_CR_PWM_CH0H_EN_POS (1U) -#define PWM_CR_PWM_CH0H_EN_LEN (1U) -#define PWM_CR_PWM_CH0H_EN_MSK (((1U << PWM_CR_PWM_CH0H_EN_LEN) - 1) << PWM_CR_PWM_CH0H_EN_POS) -#define PWM_CR_PWM_CH0H_EN_UMSK (~(((1U << PWM_CR_PWM_CH0H_EN_LEN) - 1) << PWM_CR_PWM_CH0H_EN_POS)) -#define PWM_CR_PWM_CH1L_EN PWM_CR_PWM_CH1L_EN -#define PWM_CR_PWM_CH1L_EN_POS (2U) -#define PWM_CR_PWM_CH1L_EN_LEN (1U) -#define PWM_CR_PWM_CH1L_EN_MSK (((1U << PWM_CR_PWM_CH1L_EN_LEN) - 1) << PWM_CR_PWM_CH1L_EN_POS) -#define PWM_CR_PWM_CH1L_EN_UMSK (~(((1U << PWM_CR_PWM_CH1L_EN_LEN) - 1) << PWM_CR_PWM_CH1L_EN_POS)) -#define PWM_CR_PWM_CH1H_EN PWM_CR_PWM_CH1H_EN -#define PWM_CR_PWM_CH1H_EN_POS (3U) -#define PWM_CR_PWM_CH1H_EN_LEN (1U) -#define PWM_CR_PWM_CH1H_EN_MSK (((1U << PWM_CR_PWM_CH1H_EN_LEN) - 1) << PWM_CR_PWM_CH1H_EN_POS) -#define PWM_CR_PWM_CH1H_EN_UMSK (~(((1U << PWM_CR_PWM_CH1H_EN_LEN) - 1) << PWM_CR_PWM_CH1H_EN_POS)) -#define PWM_CR_PWM_CH2L_EN PWM_CR_PWM_CH2L_EN -#define PWM_CR_PWM_CH2L_EN_POS (4U) -#define PWM_CR_PWM_CH2L_EN_LEN (1U) -#define PWM_CR_PWM_CH2L_EN_MSK (((1U << PWM_CR_PWM_CH2L_EN_LEN) - 1) << PWM_CR_PWM_CH2L_EN_POS) -#define PWM_CR_PWM_CH2L_EN_UMSK (~(((1U << PWM_CR_PWM_CH2L_EN_LEN) - 1) << PWM_CR_PWM_CH2L_EN_POS)) -#define PWM_CR_PWM_CH2H_EN PWM_CR_PWM_CH2H_EN -#define PWM_CR_PWM_CH2H_EN_POS (5U) -#define PWM_CR_PWM_CH2H_EN_LEN (1U) -#define PWM_CR_PWM_CH2H_EN_MSK (((1U << PWM_CR_PWM_CH2H_EN_LEN) - 1) << PWM_CR_PWM_CH2H_EN_POS) -#define PWM_CR_PWM_CH2H_EN_UMSK (~(((1U << PWM_CR_PWM_CH2H_EN_LEN) - 1) << PWM_CR_PWM_CH2H_EN_POS)) -#define PWM_CR_PWM_CH3L_EN PWM_CR_PWM_CH3L_EN -#define PWM_CR_PWM_CH3L_EN_POS (6U) -#define PWM_CR_PWM_CH3L_EN_LEN (1U) -#define PWM_CR_PWM_CH3L_EN_MSK (((1U << PWM_CR_PWM_CH3L_EN_LEN) - 1) << PWM_CR_PWM_CH3L_EN_POS) -#define PWM_CR_PWM_CH3L_EN_UMSK (~(((1U << PWM_CR_PWM_CH3L_EN_LEN) - 1) << PWM_CR_PWM_CH3L_EN_POS)) -#define PWM_CR_PWM_CH3H_EN PWM_CR_PWM_CH3H_EN -#define PWM_CR_PWM_CH3H_EN_POS (7U) -#define PWM_CR_PWM_CH3H_EN_LEN (1U) -#define PWM_CR_PWM_CH3H_EN_MSK (((1U << PWM_CR_PWM_CH3H_EN_LEN) - 1) << PWM_CR_PWM_CH3H_EN_POS) -#define PWM_CR_PWM_CH3H_EN_UMSK (~(((1U << PWM_CR_PWM_CH3H_EN_LEN) - 1) << PWM_CR_PWM_CH3H_EN_POS)) -#define PWM_CR_PWM_PRDE_EN PWM_CR_PWM_PRDE_EN -#define PWM_CR_PWM_PRDE_EN_POS (8U) -#define PWM_CR_PWM_PRDE_EN_LEN (1U) -#define PWM_CR_PWM_PRDE_EN_MSK (((1U << PWM_CR_PWM_PRDE_EN_LEN) - 1) << PWM_CR_PWM_PRDE_EN_POS) -#define PWM_CR_PWM_PRDE_EN_UMSK (~(((1U << PWM_CR_PWM_PRDE_EN_LEN) - 1) << PWM_CR_PWM_PRDE_EN_POS)) -#define PWM_CR_PWM_BRK_EN PWM_CR_PWM_BRK_EN -#define PWM_CR_PWM_BRK_EN_POS (9U) -#define PWM_CR_PWM_BRK_EN_LEN (1U) -#define PWM_CR_PWM_BRK_EN_MSK (((1U << PWM_CR_PWM_BRK_EN_LEN) - 1) << PWM_CR_PWM_BRK_EN_POS) -#define PWM_CR_PWM_BRK_EN_UMSK (~(((1U << PWM_CR_PWM_BRK_EN_LEN) - 1) << PWM_CR_PWM_BRK_EN_POS)) -#define PWM_CR_PWM_REPT_EN PWM_CR_PWM_REPT_EN -#define PWM_CR_PWM_REPT_EN_POS (10U) -#define PWM_CR_PWM_REPT_EN_LEN (1U) -#define PWM_CR_PWM_REPT_EN_MSK (((1U << PWM_CR_PWM_REPT_EN_LEN) - 1) << PWM_CR_PWM_REPT_EN_POS) -#define PWM_CR_PWM_REPT_EN_UMSK (~(((1U << PWM_CR_PWM_REPT_EN_LEN) - 1) << PWM_CR_PWM_REPT_EN_POS)) - -struct pwm_reg { - /* 0x00 : pwm0_config0 */ - union { - struct { - uint32_t pwm_clk_div : 16; /* [15: 0], r/w, 0x0 */ - uint32_t reserved_16_18 : 3; /* [18:16], rsvd, 0x0 */ - uint32_t pwm_stop_on_rept : 1; /* [ 19], r/w, 0x0 */ - uint32_t pwm_adc_trg_src : 4; /* [23:20], r/w, 0xf */ - uint32_t pwm_sw_break_en : 1; /* [ 24], r/w, 0x0 */ - uint32_t pwm_ext_break_en : 1; /* [ 25], r/w, 0x0 */ - uint32_t pwm_ext_break_pl : 1; /* [ 26], r/w, 0x0 */ - uint32_t pwm_stop_en : 1; /* [ 27], r/w, 0x0 */ - uint32_t pwm_stop_mode : 1; /* [ 28], r/w, 0x1 */ - uint32_t pwm_sts_stop : 1; /* [ 29], r, 0x0 */ - uint32_t reg_clk_sel : 2; /* [31:30], r/w, 0x0 */ - } BF; - uint32_t WORD; - } pwm0_config0; - - /* 0x04 : pwm0_config1 */ - union { - struct { - uint32_t pwm_ch0_pen : 1; /* [ 0], r/w, 0x0 */ - uint32_t pwm_ch0_psi : 1; /* [ 1], r/w, 0x0 */ - uint32_t pwm_ch0_nen : 1; /* [ 2], r/w, 0x0 */ - uint32_t pwm_ch0_nsi : 1; /* [ 3], r/w, 0x1 */ - uint32_t pwm_ch1_pen : 1; /* [ 4], r/w, 0x0 */ - uint32_t pwm_ch1_psi : 1; /* [ 5], r/w, 0x0 */ - uint32_t pwm_ch1_nen : 1; /* [ 6], r/w, 0x0 */ - uint32_t pwm_ch1_nsi : 1; /* [ 7], r/w, 0x1 */ - uint32_t pwm_ch2_pen : 1; /* [ 8], r/w, 0x0 */ - uint32_t pwm_ch2_psi : 1; /* [ 9], r/w, 0x0 */ - uint32_t pwm_ch2_nen : 1; /* [ 10], r/w, 0x0 */ - uint32_t pwm_ch2_nsi : 1; /* [ 11], r/w, 0x1 */ - uint32_t pwm_ch3_pen : 1; /* [ 12], r/w, 0x0 */ - uint32_t pwm_ch3_psi : 1; /* [ 13], r/w, 0x0 */ - uint32_t pwm_ch3_nen : 1; /* [ 14], r/w, 0x0 */ - uint32_t pwm_ch3_nsi : 1; /* [ 15], r/w, 0x1 */ - uint32_t pwm_ch0_ppl : 1; /* [ 16], r/w, 0x1 */ - uint32_t pwm_ch0_npl : 1; /* [ 17], r/w, 0x1 */ - uint32_t pwm_ch1_ppl : 1; /* [ 18], r/w, 0x1 */ - uint32_t pwm_ch1_npl : 1; /* [ 19], r/w, 0x1 */ - uint32_t pwm_ch2_ppl : 1; /* [ 20], r/w, 0x1 */ - uint32_t pwm_ch2_npl : 1; /* [ 21], r/w, 0x1 */ - uint32_t pwm_ch3_ppl : 1; /* [ 22], r/w, 0x1 */ - uint32_t pwm_ch3_npl : 1; /* [ 23], r/w, 0x1 */ - uint32_t pwm_ch0_pbs : 1; /* [ 24], r/w, 0x0 */ - uint32_t pwm_ch0_nbs : 1; /* [ 25], r/w, 0x0 */ - uint32_t pwm_ch1_pbs : 1; /* [ 26], r/w, 0x0 */ - uint32_t pwm_ch1_nbs : 1; /* [ 27], r/w, 0x0 */ - uint32_t pwm_ch2_pbs : 1; /* [ 28], r/w, 0x0 */ - uint32_t pwm_ch2_nbs : 1; /* [ 29], r/w, 0x0 */ - uint32_t pwm_ch3_pbs : 1; /* [ 30], r/w, 0x0 */ - uint32_t pwm_ch3_nbs : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } pwm0_config1; - - /* 0x08 : pwm0_period */ - union { - struct { - uint32_t pwm_period : 16; /* [15: 0], r/w, 0x0 */ - uint32_t pwm_int_period_cnt : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } pwm0_period; - - /* 0x0C : pwm0_dead_time */ - union { - struct { - uint32_t pwm_ch0_dtg : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t pwm_ch1_dtg : 8; /* [15: 8], r/w, 0x0 */ - uint32_t pwm_ch2_dtg : 8; /* [23:16], r/w, 0x0 */ - uint32_t pwm_ch3_dtg : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } pwm0_dead_time; - - /* 0x10 : pwm0_ch0_thre */ - union { - struct { - uint32_t pwm_ch0_threL : 16; /* [15: 0], r/w, 0x0 */ - uint32_t pwm_ch0_threH : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } pwm0_ch0_thre; - - /* 0x14 : pwm0_ch1_thre */ - union { - struct { - uint32_t pwm_ch1_threL : 16; /* [15: 0], r/w, 0x0 */ - uint32_t pwm_ch1_threH : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } pwm0_ch1_thre; - - /* 0x18 : pwm0_ch2_thre */ - union { - struct { - uint32_t pwm_ch2_threL : 16; /* [15: 0], r/w, 0x0 */ - uint32_t pwm_ch2_threH : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } pwm0_ch2_thre; - - /* 0x1C : pwm0_ch3_thre */ - union { - struct { - uint32_t pwm_ch3_threL : 16; /* [15: 0], r/w, 0x0 */ - uint32_t pwm_ch3_threH : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } pwm0_ch3_thre; - - /* 0x20 : pwm0_int_sts */ - union { - struct { - uint32_t pwm_ch0l_int : 1; /* [ 0], r, 0x0 */ - uint32_t pwm_ch0h_int : 1; /* [ 1], r, 0x0 */ - uint32_t pwm_ch1l_int : 1; /* [ 2], r, 0x0 */ - uint32_t pwm_ch1h_int : 1; /* [ 3], r, 0x0 */ - uint32_t pwm_ch2l_int : 1; /* [ 4], r, 0x0 */ - uint32_t pwm_ch2h_int : 1; /* [ 5], r, 0x0 */ - uint32_t pwm_ch3l_int : 1; /* [ 6], r, 0x0 */ - uint32_t pwm_ch3h_int : 1; /* [ 7], r, 0x0 */ - uint32_t pwm_prde_int : 1; /* [ 8], r, 0x0 */ - uint32_t pwm_brk_int : 1; /* [ 9], r, 0x0 */ - uint32_t pwm_rept_int : 1; /* [ 10], r, 0x0 */ - uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } pwm0_int_sts; - - /* 0x24 : pwm0_int_mask */ - union { - struct { - uint32_t cr_pwm_ch0l_mask : 1; /* [ 0], r/w, 0x1 */ - uint32_t cr_pwm_ch0h_mask : 1; /* [ 1], r/w, 0x1 */ - uint32_t cr_pwm_ch1l_mask : 1; /* [ 2], r/w, 0x1 */ - uint32_t cr_pwm_ch1h_mask : 1; /* [ 3], r/w, 0x1 */ - uint32_t cr_pwm_ch2l_mask : 1; /* [ 4], r/w, 0x1 */ - uint32_t cr_pwm_ch2h_mask : 1; /* [ 5], r/w, 0x1 */ - uint32_t cr_pwm_ch3l_mask : 1; /* [ 6], r/w, 0x1 */ - uint32_t cr_pwm_ch3h_mask : 1; /* [ 7], r/w, 0x1 */ - uint32_t cr_pwm_prde_mask : 1; /* [ 8], r/w, 0x1 */ - uint32_t cr_pwm_brk_mask : 1; /* [ 9], r/w, 0x1 */ - uint32_t cr_pwm_rept_mask : 1; /* [ 10], r/w, 0x1 */ - uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } pwm0_int_mask; - - /* 0x28 : pwm0_int_clear */ - union { - struct { - uint32_t cr_pwm_ch0l_clr : 1; /* [ 0], w1c, 0x0 */ - uint32_t cr_pwm_ch0h_clr : 1; /* [ 1], w1c, 0x0 */ - uint32_t cr_pwm_ch1l_clr : 1; /* [ 2], w1c, 0x0 */ - uint32_t cr_pwm_ch1h_clr : 1; /* [ 3], w1c, 0x0 */ - uint32_t cr_pwm_ch2l_clr : 1; /* [ 4], w1c, 0x0 */ - uint32_t cr_pwm_ch2h_clr : 1; /* [ 5], w1c, 0x0 */ - uint32_t cr_pwm_ch3l_clr : 1; /* [ 6], w1c, 0x0 */ - uint32_t cr_pwm_ch3h_clr : 1; /* [ 7], w1c, 0x0 */ - uint32_t cr_pwm_prde_clr : 1; /* [ 8], w1c, 0x0 */ - uint32_t cr_pwm_brk_clr : 1; /* [ 9], w1c, 0x0 */ - uint32_t cr_pwm_rept_clr : 1; /* [ 10], w1c, 0x0 */ - uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } pwm0_int_clear; - - /* 0x2C : pwm0_int_en */ - union { - struct { - uint32_t cr_pwm_ch0l_en : 1; /* [ 0], r/w, 0x1 */ - uint32_t cr_pwm_ch0h_en : 1; /* [ 1], r/w, 0x1 */ - uint32_t cr_pwm_ch1l_en : 1; /* [ 2], r/w, 0x1 */ - uint32_t cr_pwm_ch1h_en : 1; /* [ 3], r/w, 0x1 */ - uint32_t cr_pwm_ch2l_en : 1; /* [ 4], r/w, 0x1 */ - uint32_t cr_pwm_ch2h_en : 1; /* [ 5], r/w, 0x1 */ - uint32_t cr_pwm_ch3l_en : 1; /* [ 6], r/w, 0x1 */ - uint32_t cr_pwm_ch3h_en : 1; /* [ 7], r/w, 0x1 */ - uint32_t cr_pwm_prde_en : 1; /* [ 8], r/w, 0x1 */ - uint32_t cr_pwm_brk_en : 1; /* [ 9], r/w, 0x0 */ - uint32_t cr_pwm_rept_en : 1; /* [ 10], r/w, 0x1 */ - uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } pwm0_int_en; -}; - -typedef volatile struct pwm_reg pwm_reg_t; - -/*Following is reg patch*/ - -/* 0x00 : pwm_config0 */ -#define PWM_CONFIG0_OFFSET (0x00) -#define PWM_CLK_DIV PWM_CLK_DIV -#define PWM_CLK_DIV_POS (0U) -#define PWM_CLK_DIV_LEN (16U) -#define PWM_CLK_DIV_MSK (((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS) -#define PWM_CLK_DIV_UMSK (~(((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS)) -#define PWM_STOP_ON_REPT PWM_STOP_ON_REPT -#define PWM_STOP_ON_REPT_POS (19U) -#define PWM_STOP_ON_REPT_LEN (1U) -#define PWM_STOP_ON_REPT_MSK (((1U << PWM_STOP_ON_REPT_LEN) - 1) << PWM_STOP_ON_REPT_POS) -#define PWM_STOP_ON_REPT_UMSK (~(((1U << PWM_STOP_ON_REPT_LEN) - 1) << PWM_STOP_ON_REPT_POS)) -#define PWM_ADC_TRG_SRC PWM_ADC_TRG_SRC -#define PWM_ADC_TRG_SRC_POS (20U) -#define PWM_ADC_TRG_SRC_LEN (4U) -#define PWM_ADC_TRG_SRC_MSK (((1U << PWM_ADC_TRG_SRC_LEN) - 1) << PWM_ADC_TRG_SRC_POS) -#define PWM_ADC_TRG_SRC_UMSK (~(((1U << PWM_ADC_TRG_SRC_LEN) - 1) << PWM_ADC_TRG_SRC_POS)) -#define PWM_SW_BREAK_EN PWM_SW_BREAK_EN -#define PWM_SW_BREAK_EN_POS (24U) -#define PWM_SW_BREAK_EN_LEN (1U) -#define PWM_SW_BREAK_EN_MSK (((1U << PWM_SW_BREAK_EN_LEN) - 1) << PWM_SW_BREAK_EN_POS) -#define PWM_SW_BREAK_EN_UMSK (~(((1U << PWM_SW_BREAK_EN_LEN) - 1) << PWM_SW_BREAK_EN_POS)) -#define PWM_EXT_BREAK_EN PWM_EXT_BREAK_EN -#define PWM_EXT_BREAK_EN_POS (25U) -#define PWM_EXT_BREAK_EN_LEN (1U) -#define PWM_EXT_BREAK_EN_MSK (((1U << PWM_EXT_BREAK_EN_LEN) - 1) << PWM_EXT_BREAK_EN_POS) -#define PWM_EXT_BREAK_EN_UMSK (~(((1U << PWM_EXT_BREAK_EN_LEN) - 1) << PWM_EXT_BREAK_EN_POS)) -#define PWM_EXT_BREAK_PL PWM_EXT_BREAK_PL -#define PWM_EXT_BREAK_PL_POS (26U) -#define PWM_EXT_BREAK_PL_LEN (1U) -#define PWM_EXT_BREAK_PL_MSK (((1U << PWM_EXT_BREAK_PL_LEN) - 1) << PWM_EXT_BREAK_PL_POS) -#define PWM_EXT_BREAK_PL_UMSK (~(((1U << PWM_EXT_BREAK_PL_LEN) - 1) << PWM_EXT_BREAK_PL_POS)) -#define PWM_STOP_EN PWM_STOP_EN -#define PWM_STOP_EN_POS (27U) -#define PWM_STOP_EN_LEN (1U) -#define PWM_STOP_EN_MSK (((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS) -#define PWM_STOP_EN_UMSK (~(((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS)) -#define PWM_STOP_MODE PWM_STOP_MODE -#define PWM_STOP_MODE_POS (28U) -#define PWM_STOP_MODE_LEN (1U) -#define PWM_STOP_MODE_MSK (((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS) -#define PWM_STOP_MODE_UMSK (~(((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS)) -#define PWM_STS_STOP PWM_STS_STOP -#define PWM_STS_STOP_POS (29U) -#define PWM_STS_STOP_LEN (1U) -#define PWM_STS_STOP_MSK (((1U << PWM_STS_STOP_LEN) - 1) << PWM_STS_STOP_POS) -#define PWM_STS_STOP_UMSK (~(((1U << PWM_STS_STOP_LEN) - 1) << PWM_STS_STOP_POS)) -#define PWM_REG_CLK_SEL PWM_REG_CLK_SEL -#define PWM_REG_CLK_SEL_POS (30U) -#define PWM_REG_CLK_SEL_LEN (2U) -#define PWM_REG_CLK_SEL_MSK (((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS) -#define PWM_REG_CLK_SEL_UMSK (~(((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS)) - -/* 0x04 : pwm_config1 */ -#define PWM_CONFIG1_OFFSET (0x04) -#define PWM_CH0_PEN PWM_CH0_PEN -#define PWM_CH0_PEN_POS (0U) -#define PWM_CH0_PEN_LEN (1U) -#define PWM_CH0_PEN_MSK (((1U << PWM_CH0_PEN_LEN) - 1) << PWM_CH0_PEN_POS) -#define PWM_CH0_PEN_UMSK (~(((1U << PWM_CH0_PEN_LEN) - 1) << PWM_CH0_PEN_POS)) -#define PWM_CH0_PSI PWM_CH0_PSI -#define PWM_CH0_PSI_POS (1U) -#define PWM_CH0_PSI_LEN (1U) -#define PWM_CH0_PSI_MSK (((1U << PWM_CH0_PSI_LEN) - 1) << PWM_CH0_PSI_POS) -#define PWM_CH0_PSI_UMSK (~(((1U << PWM_CH0_PSI_LEN) - 1) << PWM_CH0_PSI_POS)) -#define PWM_CH0_NEN PWM_CH0_NEN -#define PWM_CH0_NEN_POS (2U) -#define PWM_CH0_NEN_LEN (1U) -#define PWM_CH0_NEN_MSK (((1U << PWM_CH0_NEN_LEN) - 1) << PWM_CH0_NEN_POS) -#define PWM_CH0_NEN_UMSK (~(((1U << PWM_CH0_NEN_LEN) - 1) << PWM_CH0_NEN_POS)) -#define PWM_CH0_NSI PWM_CH0_NSI -#define PWM_CH0_NSI_POS (3U) -#define PWM_CH0_NSI_LEN (1U) -#define PWM_CH0_NSI_MSK (((1U << PWM_CH0_NSI_LEN) - 1) << PWM_CH0_NSI_POS) -#define PWM_CH0_NSI_UMSK (~(((1U << PWM_CH0_NSI_LEN) - 1) << PWM_CH0_NSI_POS)) -#define PWM_CH1_PEN PWM_CH1_PEN -#define PWM_CH1_PEN_POS (4U) -#define PWM_CH1_PEN_LEN (1U) -#define PWM_CH1_PEN_MSK (((1U << PWM_CH1_PEN_LEN) - 1) << PWM_CH1_PEN_POS) -#define PWM_CH1_PEN_UMSK (~(((1U << PWM_CH1_PEN_LEN) - 1) << PWM_CH1_PEN_POS)) -#define PWM_CH1_PSI PWM_CH1_PSI -#define PWM_CH1_PSI_POS (5U) -#define PWM_CH1_PSI_LEN (1U) -#define PWM_CH1_PSI_MSK (((1U << PWM_CH1_PSI_LEN) - 1) << PWM_CH1_PSI_POS) -#define PWM_CH1_PSI_UMSK (~(((1U << PWM_CH1_PSI_LEN) - 1) << PWM_CH1_PSI_POS)) -#define PWM_CH1_NEN PWM_CH1_NEN -#define PWM_CH1_NEN_POS (6U) -#define PWM_CH1_NEN_LEN (1U) -#define PWM_CH1_NEN_MSK (((1U << PWM_CH1_NEN_LEN) - 1) << PWM_CH1_NEN_POS) -#define PWM_CH1_NEN_UMSK (~(((1U << PWM_CH1_NEN_LEN) - 1) << PWM_CH1_NEN_POS)) -#define PWM_CH1_NSI PWM_CH1_NSI -#define PWM_CH1_NSI_POS (7U) -#define PWM_CH1_NSI_LEN (1U) -#define PWM_CH1_NSI_MSK (((1U << PWM_CH1_NSI_LEN) - 1) << PWM_CH1_NSI_POS) -#define PWM_CH1_NSI_UMSK (~(((1U << PWM_CH1_NSI_LEN) - 1) << PWM_CH1_NSI_POS)) -#define PWM_CH2_PEN PWM_CH2_PEN -#define PWM_CH2_PEN_POS (8U) -#define PWM_CH2_PEN_LEN (1U) -#define PWM_CH2_PEN_MSK (((1U << PWM_CH2_PEN_LEN) - 1) << PWM_CH2_PEN_POS) -#define PWM_CH2_PEN_UMSK (~(((1U << PWM_CH2_PEN_LEN) - 1) << PWM_CH2_PEN_POS)) -#define PWM_CH2_PSI PWM_CH2_PSI -#define PWM_CH2_PSI_POS (9U) -#define PWM_CH2_PSI_LEN (1U) -#define PWM_CH2_PSI_MSK (((1U << PWM_CH2_PSI_LEN) - 1) << PWM_CH2_PSI_POS) -#define PWM_CH2_PSI_UMSK (~(((1U << PWM_CH2_PSI_LEN) - 1) << PWM_CH2_PSI_POS)) -#define PWM_CH2_NEN PWM_CH2_NEN -#define PWM_CH2_NEN_POS (10U) -#define PWM_CH2_NEN_LEN (1U) -#define PWM_CH2_NEN_MSK (((1U << PWM_CH2_NEN_LEN) - 1) << PWM_CH2_NEN_POS) -#define PWM_CH2_NEN_UMSK (~(((1U << PWM_CH2_NEN_LEN) - 1) << PWM_CH2_NEN_POS)) -#define PWM_CH2_NSI PWM_CH2_NSI -#define PWM_CH2_NSI_POS (11U) -#define PWM_CH2_NSI_LEN (1U) -#define PWM_CH2_NSI_MSK (((1U << PWM_CH2_NSI_LEN) - 1) << PWM_CH2_NSI_POS) -#define PWM_CH2_NSI_UMSK (~(((1U << PWM_CH2_NSI_LEN) - 1) << PWM_CH2_NSI_POS)) -#define PWM_CH3_PEN PWM_CH3_PEN -#define PWM_CH3_PEN_POS (12U) -#define PWM_CH3_PEN_LEN (1U) -#define PWM_CH3_PEN_MSK (((1U << PWM_CH3_PEN_LEN) - 1) << PWM_CH3_PEN_POS) -#define PWM_CH3_PEN_UMSK (~(((1U << PWM_CH3_PEN_LEN) - 1) << PWM_CH3_PEN_POS)) -#define PWM_CH3_PSI PWM_CH3_PSI -#define PWM_CH3_PSI_POS (13U) -#define PWM_CH3_PSI_LEN (1U) -#define PWM_CH3_PSI_MSK (((1U << PWM_CH3_PSI_LEN) - 1) << PWM_CH3_PSI_POS) -#define PWM_CH3_PSI_UMSK (~(((1U << PWM_CH3_PSI_LEN) - 1) << PWM_CH3_PSI_POS)) -#define PWM_CH3_NEN PWM_CH3_NEN -#define PWM_CH3_NEN_POS (14U) -#define PWM_CH3_NEN_LEN (1U) -#define PWM_CH3_NEN_MSK (((1U << PWM_CH3_NEN_LEN) - 1) << PWM_CH3_NEN_POS) -#define PWM_CH3_NEN_UMSK (~(((1U << PWM_CH3_NEN_LEN) - 1) << PWM_CH3_NEN_POS)) -#define PWM_CH3_NSI PWM_CH3_NSI -#define PWM_CH3_NSI_POS (15U) -#define PWM_CH3_NSI_LEN (1U) -#define PWM_CH3_NSI_MSK (((1U << PWM_CH3_NSI_LEN) - 1) << PWM_CH3_NSI_POS) -#define PWM_CH3_NSI_UMSK (~(((1U << PWM_CH3_NSI_LEN) - 1) << PWM_CH3_NSI_POS)) -#define PWM_CH0_PPL PWM_CH0_PPL -#define PWM_CH0_PPL_POS (16U) -#define PWM_CH0_PPL_LEN (1U) -#define PWM_CH0_PPL_MSK (((1U << PWM_CH0_PPL_LEN) - 1) << PWM_CH0_PPL_POS) -#define PWM_CH0_PPL_UMSK (~(((1U << PWM_CH0_PPL_LEN) - 1) << PWM_CH0_PPL_POS)) -#define PWM_CH0_NPL PWM_CH0_NPL -#define PWM_CH0_NPL_POS (17U) -#define PWM_CH0_NPL_LEN (1U) -#define PWM_CH0_NPL_MSK (((1U << PWM_CH0_NPL_LEN) - 1) << PWM_CH0_NPL_POS) -#define PWM_CH0_NPL_UMSK (~(((1U << PWM_CH0_NPL_LEN) - 1) << PWM_CH0_NPL_POS)) -#define PWM_CH1_PPL PWM_CH1_PPL -#define PWM_CH1_PPL_POS (18U) -#define PWM_CH1_PPL_LEN (1U) -#define PWM_CH1_PPL_MSK (((1U << PWM_CH1_PPL_LEN) - 1) << PWM_CH1_PPL_POS) -#define PWM_CH1_PPL_UMSK (~(((1U << PWM_CH1_PPL_LEN) - 1) << PWM_CH1_PPL_POS)) -#define PWM_CH1_NPL PWM_CH1_NPL -#define PWM_CH1_NPL_POS (19U) -#define PWM_CH1_NPL_LEN (1U) -#define PWM_CH1_NPL_MSK (((1U << PWM_CH1_NPL_LEN) - 1) << PWM_CH1_NPL_POS) -#define PWM_CH1_NPL_UMSK (~(((1U << PWM_CH1_NPL_LEN) - 1) << PWM_CH1_NPL_POS)) -#define PWM_CH2_PPL PWM_CH2_PPL -#define PWM_CH2_PPL_POS (20U) -#define PWM_CH2_PPL_LEN (1U) -#define PWM_CH2_PPL_MSK (((1U << PWM_CH2_PPL_LEN) - 1) << PWM_CH2_PPL_POS) -#define PWM_CH2_PPL_UMSK (~(((1U << PWM_CH2_PPL_LEN) - 1) << PWM_CH2_PPL_POS)) -#define PWM_CH2_NPL PWM_CH2_NPL -#define PWM_CH2_NPL_POS (21U) -#define PWM_CH2_NPL_LEN (1U) -#define PWM_CH2_NPL_MSK (((1U << PWM_CH2_NPL_LEN) - 1) << PWM_CH2_NPL_POS) -#define PWM_CH2_NPL_UMSK (~(((1U << PWM_CH2_NPL_LEN) - 1) << PWM_CH2_NPL_POS)) -#define PWM_CH3_PPL PWM_CH3_PPL -#define PWM_CH3_PPL_POS (22U) -#define PWM_CH3_PPL_LEN (1U) -#define PWM_CH3_PPL_MSK (((1U << PWM_CH3_PPL_LEN) - 1) << PWM_CH3_PPL_POS) -#define PWM_CH3_PPL_UMSK (~(((1U << PWM_CH3_PPL_LEN) - 1) << PWM_CH3_PPL_POS)) -#define PWM_CH3_NPL PWM_CH3_NPL -#define PWM_CH3_NPL_POS (23U) -#define PWM_CH3_NPL_LEN (1U) -#define PWM_CH3_NPL_MSK (((1U << PWM_CH3_NPL_LEN) - 1) << PWM_CH3_NPL_POS) -#define PWM_CH3_NPL_UMSK (~(((1U << PWM_CH3_NPL_LEN) - 1) << PWM_CH3_NPL_POS)) -#define PWM_CH0_PBS PWM_CH0_PBS -#define PWM_CH0_PBS_POS (24U) -#define PWM_CH0_PBS_LEN (1U) -#define PWM_CH0_PBS_MSK (((1U << PWM_CH0_PBS_LEN) - 1) << PWM_CH0_PBS_POS) -#define PWM_CH0_PBS_UMSK (~(((1U << PWM_CH0_PBS_LEN) - 1) << PWM_CH0_PBS_POS)) -#define PWM_CH0_NBS PWM_CH0_NBS -#define PWM_CH0_NBS_POS (25U) -#define PWM_CH0_NBS_LEN (1U) -#define PWM_CH0_NBS_MSK (((1U << PWM_CH0_NBS_LEN) - 1) << PWM_CH0_NBS_POS) -#define PWM_CH0_NBS_UMSK (~(((1U << PWM_CH0_NBS_LEN) - 1) << PWM_CH0_NBS_POS)) -#define PWM_CH1_PBS PWM_CH1_PBS -#define PWM_CH1_PBS_POS (26U) -#define PWM_CH1_PBS_LEN (1U) -#define PWM_CH1_PBS_MSK (((1U << PWM_CH1_PBS_LEN) - 1) << PWM_CH1_PBS_POS) -#define PWM_CH1_PBS_UMSK (~(((1U << PWM_CH1_PBS_LEN) - 1) << PWM_CH1_PBS_POS)) -#define PWM_CH1_NBS PWM_CH1_NBS -#define PWM_CH1_NBS_POS (27U) -#define PWM_CH1_NBS_LEN (1U) -#define PWM_CH1_NBS_MSK (((1U << PWM_CH1_NBS_LEN) - 1) << PWM_CH1_NBS_POS) -#define PWM_CH1_NBS_UMSK (~(((1U << PWM_CH1_NBS_LEN) - 1) << PWM_CH1_NBS_POS)) -#define PWM_CH2_PBS PWM_CH2_PBS -#define PWM_CH2_PBS_POS (28U) -#define PWM_CH2_PBS_LEN (1U) -#define PWM_CH2_PBS_MSK (((1U << PWM_CH2_PBS_LEN) - 1) << PWM_CH2_PBS_POS) -#define PWM_CH2_PBS_UMSK (~(((1U << PWM_CH2_PBS_LEN) - 1) << PWM_CH2_PBS_POS)) -#define PWM_CH2_NBS PWM_CH2_NBS -#define PWM_CH2_NBS_POS (29U) -#define PWM_CH2_NBS_LEN (1U) -#define PWM_CH2_NBS_MSK (((1U << PWM_CH2_NBS_LEN) - 1) << PWM_CH2_NBS_POS) -#define PWM_CH2_NBS_UMSK (~(((1U << PWM_CH2_NBS_LEN) - 1) << PWM_CH2_NBS_POS)) -#define PWM_CH3_PBS PWM_CH3_PBS -#define PWM_CH3_PBS_POS (30U) -#define PWM_CH3_PBS_LEN (1U) -#define PWM_CH3_PBS_MSK (((1U << PWM_CH3_PBS_LEN) - 1) << PWM_CH3_PBS_POS) -#define PWM_CH3_PBS_UMSK (~(((1U << PWM_CH3_PBS_LEN) - 1) << PWM_CH3_PBS_POS)) -#define PWM_CH3_NBS PWM_CH3_NBS -#define PWM_CH3_NBS_POS (31U) -#define PWM_CH3_NBS_LEN (1U) -#define PWM_CH3_NBS_MSK (((1U << PWM_CH3_NBS_LEN) - 1) << PWM_CH3_NBS_POS) -#define PWM_CH3_NBS_UMSK (~(((1U << PWM_CH3_NBS_LEN) - 1) << PWM_CH3_NBS_POS)) - -/* 0x08 : pwm_period */ -#define PWM_PERIOD_OFFSET (0x08) -#define PWM_PERIOD PWM_PERIOD -#define PWM_PERIOD_POS (0U) -#define PWM_PERIOD_LEN (16U) -#define PWM_PERIOD_MSK (((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS) -#define PWM_PERIOD_UMSK (~(((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS)) -#define PWM_INT_PERIOD_CNT PWM_INT_PERIOD_CNT -#define PWM_INT_PERIOD_CNT_POS (16U) -#define PWM_INT_PERIOD_CNT_LEN (16U) -#define PWM_INT_PERIOD_CNT_MSK (((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS) -#define PWM_INT_PERIOD_CNT_UMSK (~(((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS)) - -/* 0x0C : pwm_dead_time */ -#define PWM_DEAD_TIME_OFFSET (0x0C) -#define PWM_CH0_DTG PWM_CH0_DTG -#define PWM_CH0_DTG_POS (0U) -#define PWM_CH0_DTG_LEN (8U) -#define PWM_CH0_DTG_MSK (((1U << PWM_CH0_DTG_LEN) - 1) << PWM_CH0_DTG_POS) -#define PWM_CH0_DTG_UMSK (~(((1U << PWM_CH0_DTG_LEN) - 1) << PWM_CH0_DTG_POS)) -#define PWM_CH1_DTG PWM_CH1_DTG -#define PWM_CH1_DTG_POS (8U) -#define PWM_CH1_DTG_LEN (8U) -#define PWM_CH1_DTG_MSK (((1U << PWM_CH1_DTG_LEN) - 1) << PWM_CH1_DTG_POS) -#define PWM_CH1_DTG_UMSK (~(((1U << PWM_CH1_DTG_LEN) - 1) << PWM_CH1_DTG_POS)) -#define PWM_CH2_DTG PWM_CH2_DTG -#define PWM_CH2_DTG_POS (16U) -#define PWM_CH2_DTG_LEN (8U) -#define PWM_CH2_DTG_MSK (((1U << PWM_CH2_DTG_LEN) - 1) << PWM_CH2_DTG_POS) -#define PWM_CH2_DTG_UMSK (~(((1U << PWM_CH2_DTG_LEN) - 1) << PWM_CH2_DTG_POS)) -#define PWM_CH3_DTG PWM_CH3_DTG -#define PWM_CH3_DTG_POS (24U) -#define PWM_CH3_DTG_LEN (8U) -#define PWM_CH3_DTG_MSK (((1U << PWM_CH3_DTG_LEN) - 1) << PWM_CH3_DTG_POS) -#define PWM_CH3_DTG_UMSK (~(((1U << PWM_CH3_DTG_LEN) - 1) << PWM_CH3_DTG_POS)) - -/* 0x10 : pwm_ch0_thre */ -#define PWM_CH0_THRE_OFFSET (0x10) -#define PWM_CH0_THREL PWM_CH0_THREL -#define PWM_CH0_THREL_POS (0U) -#define PWM_CH0_THREL_LEN (16U) -#define PWM_CH0_THREL_MSK (((1U << PWM_CH0_THREL_LEN) - 1) << PWM_CH0_THREL_POS) -#define PWM_CH0_THREL_UMSK (~(((1U << PWM_CH0_THREL_LEN) - 1) << PWM_CH0_THREL_POS)) -#define PWM_CH0_THREH PWM_CH0_THREH -#define PWM_CH0_THREH_POS (16U) -#define PWM_CH0_THREH_LEN (16U) -#define PWM_CH0_THREH_MSK (((1U << PWM_CH0_THREH_LEN) - 1) << PWM_CH0_THREH_POS) -#define PWM_CH0_THREH_UMSK (~(((1U << PWM_CH0_THREH_LEN) - 1) << PWM_CH0_THREH_POS)) - -/* 0x14 : pwm_ch1_thre */ -#define PWM_CH1_THRE_OFFSET (0x14) -#define PWM_CH1_THREL PWM_CH1_THREL -#define PWM_CH1_THREL_POS (0U) -#define PWM_CH1_THREL_LEN (16U) -#define PWM_CH1_THREL_MSK (((1U << PWM_CH1_THREL_LEN) - 1) << PWM_CH1_THREL_POS) -#define PWM_CH1_THREL_UMSK (~(((1U << PWM_CH1_THREL_LEN) - 1) << PWM_CH1_THREL_POS)) -#define PWM_CH1_THREH PWM_CH1_THREH -#define PWM_CH1_THREH_POS (16U) -#define PWM_CH1_THREH_LEN (16U) -#define PWM_CH1_THREH_MSK (((1U << PWM_CH1_THREH_LEN) - 1) << PWM_CH1_THREH_POS) -#define PWM_CH1_THREH_UMSK (~(((1U << PWM_CH1_THREH_LEN) - 1) << PWM_CH1_THREH_POS)) - -/* 0x18 : pwm_ch2_thre */ -#define PWM_CH2_THRE_OFFSET (0x18) -#define PWM_CH2_THREL PWM_CH2_THREL -#define PWM_CH2_THREL_POS (0U) -#define PWM_CH2_THREL_LEN (16U) -#define PWM_CH2_THREL_MSK (((1U << PWM_CH2_THREL_LEN) - 1) << PWM_CH2_THREL_POS) -#define PWM_CH2_THREL_UMSK (~(((1U << PWM_CH2_THREL_LEN) - 1) << PWM_CH2_THREL_POS)) -#define PWM_CH2_THREH PWM_CH2_THREH -#define PWM_CH2_THREH_POS (16U) -#define PWM_CH2_THREH_LEN (16U) -#define PWM_CH2_THREH_MSK (((1U << PWM_CH2_THREH_LEN) - 1) << PWM_CH2_THREH_POS) -#define PWM_CH2_THREH_UMSK (~(((1U << PWM_CH2_THREH_LEN) - 1) << PWM_CH2_THREH_POS)) - -/* 0x1C : pwm_ch3_thre */ -#define PWM_CH3_THRE_OFFSET (0x1C) -#define PWM_CH3_THREL PWM_CH3_THREL -#define PWM_CH3_THREL_POS (0U) -#define PWM_CH3_THREL_LEN (16U) -#define PWM_CH3_THREL_MSK (((1U << PWM_CH3_THREL_LEN) - 1) << PWM_CH3_THREL_POS) -#define PWM_CH3_THREL_UMSK (~(((1U << PWM_CH3_THREL_LEN) - 1) << PWM_CH3_THREL_POS)) -#define PWM_CH3_THREH PWM_CH3_THREH -#define PWM_CH3_THREH_POS (16U) -#define PWM_CH3_THREH_LEN (16U) -#define PWM_CH3_THREH_MSK (((1U << PWM_CH3_THREH_LEN) - 1) << PWM_CH3_THREH_POS) -#define PWM_CH3_THREH_UMSK (~(((1U << PWM_CH3_THREH_LEN) - 1) << PWM_CH3_THREH_POS)) - -/* 0x20 : pwm_int_sts */ -#define PWM_INT_STS_OFFSET (0x20) -#define PWM_CH0L_INT PWM_CH0L_INT -#define PWM_CH0L_INT_POS (0U) -#define PWM_CH0L_INT_LEN (1U) -#define PWM_CH0L_INT_MSK (((1U << PWM_CH0L_INT_LEN) - 1) << PWM_CH0L_INT_POS) -#define PWM_CH0L_INT_UMSK (~(((1U << PWM_CH0L_INT_LEN) - 1) << PWM_CH0L_INT_POS)) -#define PWM_CH0H_INT PWM_CH0H_INT -#define PWM_CH0H_INT_POS (1U) -#define PWM_CH0H_INT_LEN (1U) -#define PWM_CH0H_INT_MSK (((1U << PWM_CH0H_INT_LEN) - 1) << PWM_CH0H_INT_POS) -#define PWM_CH0H_INT_UMSK (~(((1U << PWM_CH0H_INT_LEN) - 1) << PWM_CH0H_INT_POS)) -#define PWM_CH1L_INT PWM_CH1L_INT -#define PWM_CH1L_INT_POS (2U) -#define PWM_CH1L_INT_LEN (1U) -#define PWM_CH1L_INT_MSK (((1U << PWM_CH1L_INT_LEN) - 1) << PWM_CH1L_INT_POS) -#define PWM_CH1L_INT_UMSK (~(((1U << PWM_CH1L_INT_LEN) - 1) << PWM_CH1L_INT_POS)) -#define PWM_CH1H_INT PWM_CH1H_INT -#define PWM_CH1H_INT_POS (3U) -#define PWM_CH1H_INT_LEN (1U) -#define PWM_CH1H_INT_MSK (((1U << PWM_CH1H_INT_LEN) - 1) << PWM_CH1H_INT_POS) -#define PWM_CH1H_INT_UMSK (~(((1U << PWM_CH1H_INT_LEN) - 1) << PWM_CH1H_INT_POS)) -#define PWM_CH2L_INT PWM_CH2L_INT -#define PWM_CH2L_INT_POS (4U) -#define PWM_CH2L_INT_LEN (1U) -#define PWM_CH2L_INT_MSK (((1U << PWM_CH2L_INT_LEN) - 1) << PWM_CH2L_INT_POS) -#define PWM_CH2L_INT_UMSK (~(((1U << PWM_CH2L_INT_LEN) - 1) << PWM_CH2L_INT_POS)) -#define PWM_CH2H_INT PWM_CH2H_INT -#define PWM_CH2H_INT_POS (5U) -#define PWM_CH2H_INT_LEN (1U) -#define PWM_CH2H_INT_MSK (((1U << PWM_CH2H_INT_LEN) - 1) << PWM_CH2H_INT_POS) -#define PWM_CH2H_INT_UMSK (~(((1U << PWM_CH2H_INT_LEN) - 1) << PWM_CH2H_INT_POS)) -#define PWM_CH3L_INT PWM_CH3L_INT -#define PWM_CH3L_INT_POS (6U) -#define PWM_CH3L_INT_LEN (1U) -#define PWM_CH3L_INT_MSK (((1U << PWM_CH3L_INT_LEN) - 1) << PWM_CH3L_INT_POS) -#define PWM_CH3L_INT_UMSK (~(((1U << PWM_CH3L_INT_LEN) - 1) << PWM_CH3L_INT_POS)) -#define PWM_CH3H_INT PWM_CH3H_INT -#define PWM_CH3H_INT_POS (7U) -#define PWM_CH3H_INT_LEN (1U) -#define PWM_CH3H_INT_MSK (((1U << PWM_CH3H_INT_LEN) - 1) << PWM_CH3H_INT_POS) -#define PWM_CH3H_INT_UMSK (~(((1U << PWM_CH3H_INT_LEN) - 1) << PWM_CH3H_INT_POS)) -#define PWM_PRDE_INT PWM_PRDE_INT -#define PWM_PRDE_INT_POS (8U) -#define PWM_PRDE_INT_LEN (1U) -#define PWM_PRDE_INT_MSK (((1U << PWM_PRDE_INT_LEN) - 1) << PWM_PRDE_INT_POS) -#define PWM_PRDE_INT_UMSK (~(((1U << PWM_PRDE_INT_LEN) - 1) << PWM_PRDE_INT_POS)) -#define PWM_BRK_INT PWM_BRK_INT -#define PWM_BRK_INT_POS (9U) -#define PWM_BRK_INT_LEN (1U) -#define PWM_BRK_INT_MSK (((1U << PWM_BRK_INT_LEN) - 1) << PWM_BRK_INT_POS) -#define PWM_BRK_INT_UMSK (~(((1U << PWM_BRK_INT_LEN) - 1) << PWM_BRK_INT_POS)) -#define PWM_REPT_INT PWM_REPT_INT -#define PWM_REPT_INT_POS (10U) -#define PWM_REPT_INT_LEN (1U) -#define PWM_REPT_INT_MSK (((1U << PWM_REPT_INT_LEN) - 1) << PWM_REPT_INT_POS) -#define PWM_REPT_INT_UMSK (~(((1U << PWM_REPT_INT_LEN) - 1) << PWM_REPT_INT_POS)) - -/* 0x24 : pwm_int_mask */ -#define PWM_INT_MASK_OFFSET (0x24) -#define PWM_CR_PWM_CH0L_MASK PWM_CR_PWM_CH0L_MASK -#define PWM_CR_PWM_CH0L_MASK_POS (0U) -#define PWM_CR_PWM_CH0L_MASK_LEN (1U) -#define PWM_CR_PWM_CH0L_MASK_MSK (((1U << PWM_CR_PWM_CH0L_MASK_LEN) - 1) << PWM_CR_PWM_CH0L_MASK_POS) -#define PWM_CR_PWM_CH0L_MASK_UMSK (~(((1U << PWM_CR_PWM_CH0L_MASK_LEN) - 1) << PWM_CR_PWM_CH0L_MASK_POS)) -#define PWM_CR_PWM_CH0H_MASK PWM_CR_PWM_CH0H_MASK -#define PWM_CR_PWM_CH0H_MASK_POS (1U) -#define PWM_CR_PWM_CH0H_MASK_LEN (1U) -#define PWM_CR_PWM_CH0H_MASK_MSK (((1U << PWM_CR_PWM_CH0H_MASK_LEN) - 1) << PWM_CR_PWM_CH0H_MASK_POS) -#define PWM_CR_PWM_CH0H_MASK_UMSK (~(((1U << PWM_CR_PWM_CH0H_MASK_LEN) - 1) << PWM_CR_PWM_CH0H_MASK_POS)) -#define PWM_CR_PWM_CH1L_MASK PWM_CR_PWM_CH1L_MASK -#define PWM_CR_PWM_CH1L_MASK_POS (2U) -#define PWM_CR_PWM_CH1L_MASK_LEN (1U) -#define PWM_CR_PWM_CH1L_MASK_MSK (((1U << PWM_CR_PWM_CH1L_MASK_LEN) - 1) << PWM_CR_PWM_CH1L_MASK_POS) -#define PWM_CR_PWM_CH1L_MASK_UMSK (~(((1U << PWM_CR_PWM_CH1L_MASK_LEN) - 1) << PWM_CR_PWM_CH1L_MASK_POS)) -#define PWM_CR_PWM_CH1H_MASK PWM_CR_PWM_CH1H_MASK -#define PWM_CR_PWM_CH1H_MASK_POS (3U) -#define PWM_CR_PWM_CH1H_MASK_LEN (1U) -#define PWM_CR_PWM_CH1H_MASK_MSK (((1U << PWM_CR_PWM_CH1H_MASK_LEN) - 1) << PWM_CR_PWM_CH1H_MASK_POS) -#define PWM_CR_PWM_CH1H_MASK_UMSK (~(((1U << PWM_CR_PWM_CH1H_MASK_LEN) - 1) << PWM_CR_PWM_CH1H_MASK_POS)) -#define PWM_CR_PWM_CH2L_MASK PWM_CR_PWM_CH2L_MASK -#define PWM_CR_PWM_CH2L_MASK_POS (4U) -#define PWM_CR_PWM_CH2L_MASK_LEN (1U) -#define PWM_CR_PWM_CH2L_MASK_MSK (((1U << PWM_CR_PWM_CH2L_MASK_LEN) - 1) << PWM_CR_PWM_CH2L_MASK_POS) -#define PWM_CR_PWM_CH2L_MASK_UMSK (~(((1U << PWM_CR_PWM_CH2L_MASK_LEN) - 1) << PWM_CR_PWM_CH2L_MASK_POS)) -#define PWM_CR_PWM_CH2H_MASK PWM_CR_PWM_CH2H_MASK -#define PWM_CR_PWM_CH2H_MASK_POS (5U) -#define PWM_CR_PWM_CH2H_MASK_LEN (1U) -#define PWM_CR_PWM_CH2H_MASK_MSK (((1U << PWM_CR_PWM_CH2H_MASK_LEN) - 1) << PWM_CR_PWM_CH2H_MASK_POS) -#define PWM_CR_PWM_CH2H_MASK_UMSK (~(((1U << PWM_CR_PWM_CH2H_MASK_LEN) - 1) << PWM_CR_PWM_CH2H_MASK_POS)) -#define PWM_CR_PWM_CH3L_MASK PWM_CR_PWM_CH3L_MASK -#define PWM_CR_PWM_CH3L_MASK_POS (6U) -#define PWM_CR_PWM_CH3L_MASK_LEN (1U) -#define PWM_CR_PWM_CH3L_MASK_MSK (((1U << PWM_CR_PWM_CH3L_MASK_LEN) - 1) << PWM_CR_PWM_CH3L_MASK_POS) -#define PWM_CR_PWM_CH3L_MASK_UMSK (~(((1U << PWM_CR_PWM_CH3L_MASK_LEN) - 1) << PWM_CR_PWM_CH3L_MASK_POS)) -#define PWM_CR_PWM_CH3H_MASK PWM_CR_PWM_CH3H_MASK -#define PWM_CR_PWM_CH3H_MASK_POS (7U) -#define PWM_CR_PWM_CH3H_MASK_LEN (1U) -#define PWM_CR_PWM_CH3H_MASK_MSK (((1U << PWM_CR_PWM_CH3H_MASK_LEN) - 1) << PWM_CR_PWM_CH3H_MASK_POS) -#define PWM_CR_PWM_CH3H_MASK_UMSK (~(((1U << PWM_CR_PWM_CH3H_MASK_LEN) - 1) << PWM_CR_PWM_CH3H_MASK_POS)) -#define PWM_CR_PWM_PRDE_MASK PWM_CR_PWM_PRDE_MASK -#define PWM_CR_PWM_PRDE_MASK_POS (8U) -#define PWM_CR_PWM_PRDE_MASK_LEN (1U) -#define PWM_CR_PWM_PRDE_MASK_MSK (((1U << PWM_CR_PWM_PRDE_MASK_LEN) - 1) << PWM_CR_PWM_PRDE_MASK_POS) -#define PWM_CR_PWM_PRDE_MASK_UMSK (~(((1U << PWM_CR_PWM_PRDE_MASK_LEN) - 1) << PWM_CR_PWM_PRDE_MASK_POS)) -#define PWM_CR_PWM_BRK_MASK PWM_CR_PWM_BRK_MASK -#define PWM_CR_PWM_BRK_MASK_POS (9U) -#define PWM_CR_PWM_BRK_MASK_LEN (1U) -#define PWM_CR_PWM_BRK_MASK_MSK (((1U << PWM_CR_PWM_BRK_MASK_LEN) - 1) << PWM_CR_PWM_BRK_MASK_POS) -#define PWM_CR_PWM_BRK_MASK_UMSK (~(((1U << PWM_CR_PWM_BRK_MASK_LEN) - 1) << PWM_CR_PWM_BRK_MASK_POS)) -#define PWM_CR_PWM_REPT_MASK PWM_CR_PWM_REPT_MASK -#define PWM_CR_PWM_REPT_MASK_POS (10U) -#define PWM_CR_PWM_REPT_MASK_LEN (1U) -#define PWM_CR_PWM_REPT_MASK_MSK (((1U << PWM_CR_PWM_REPT_MASK_LEN) - 1) << PWM_CR_PWM_REPT_MASK_POS) -#define PWM_CR_PWM_REPT_MASK_UMSK (~(((1U << PWM_CR_PWM_REPT_MASK_LEN) - 1) << PWM_CR_PWM_REPT_MASK_POS)) - -/* 0x28 : pwm_int_clear */ -#define PWM_INT_CLEAR_OFFSET (0x28) -#define PWM_CR_PWM_CH0L_CLR PWM_CR_PWM_CH0L_CLR -#define PWM_CR_PWM_CH0L_CLR_POS (0U) -#define PWM_CR_PWM_CH0L_CLR_LEN (1U) -#define PWM_CR_PWM_CH0L_CLR_MSK (((1U << PWM_CR_PWM_CH0L_CLR_LEN) - 1) << PWM_CR_PWM_CH0L_CLR_POS) -#define PWM_CR_PWM_CH0L_CLR_UMSK (~(((1U << PWM_CR_PWM_CH0L_CLR_LEN) - 1) << PWM_CR_PWM_CH0L_CLR_POS)) -#define PWM_CR_PWM_CH0H_CLR PWM_CR_PWM_CH0H_CLR -#define PWM_CR_PWM_CH0H_CLR_POS (1U) -#define PWM_CR_PWM_CH0H_CLR_LEN (1U) -#define PWM_CR_PWM_CH0H_CLR_MSK (((1U << PWM_CR_PWM_CH0H_CLR_LEN) - 1) << PWM_CR_PWM_CH0H_CLR_POS) -#define PWM_CR_PWM_CH0H_CLR_UMSK (~(((1U << PWM_CR_PWM_CH0H_CLR_LEN) - 1) << PWM_CR_PWM_CH0H_CLR_POS)) -#define PWM_CR_PWM_CH1L_CLR PWM_CR_PWM_CH1L_CLR -#define PWM_CR_PWM_CH1L_CLR_POS (2U) -#define PWM_CR_PWM_CH1L_CLR_LEN (1U) -#define PWM_CR_PWM_CH1L_CLR_MSK (((1U << PWM_CR_PWM_CH1L_CLR_LEN) - 1) << PWM_CR_PWM_CH1L_CLR_POS) -#define PWM_CR_PWM_CH1L_CLR_UMSK (~(((1U << PWM_CR_PWM_CH1L_CLR_LEN) - 1) << PWM_CR_PWM_CH1L_CLR_POS)) -#define PWM_CR_PWM_CH1H_CLR PWM_CR_PWM_CH1H_CLR -#define PWM_CR_PWM_CH1H_CLR_POS (3U) -#define PWM_CR_PWM_CH1H_CLR_LEN (1U) -#define PWM_CR_PWM_CH1H_CLR_MSK (((1U << PWM_CR_PWM_CH1H_CLR_LEN) - 1) << PWM_CR_PWM_CH1H_CLR_POS) -#define PWM_CR_PWM_CH1H_CLR_UMSK (~(((1U << PWM_CR_PWM_CH1H_CLR_LEN) - 1) << PWM_CR_PWM_CH1H_CLR_POS)) -#define PWM_CR_PWM_CH2L_CLR PWM_CR_PWM_CH2L_CLR -#define PWM_CR_PWM_CH2L_CLR_POS (4U) -#define PWM_CR_PWM_CH2L_CLR_LEN (1U) -#define PWM_CR_PWM_CH2L_CLR_MSK (((1U << PWM_CR_PWM_CH2L_CLR_LEN) - 1) << PWM_CR_PWM_CH2L_CLR_POS) -#define PWM_CR_PWM_CH2L_CLR_UMSK (~(((1U << PWM_CR_PWM_CH2L_CLR_LEN) - 1) << PWM_CR_PWM_CH2L_CLR_POS)) -#define PWM_CR_PWM_CH2H_CLR PWM_CR_PWM_CH2H_CLR -#define PWM_CR_PWM_CH2H_CLR_POS (5U) -#define PWM_CR_PWM_CH2H_CLR_LEN (1U) -#define PWM_CR_PWM_CH2H_CLR_MSK (((1U << PWM_CR_PWM_CH2H_CLR_LEN) - 1) << PWM_CR_PWM_CH2H_CLR_POS) -#define PWM_CR_PWM_CH2H_CLR_UMSK (~(((1U << PWM_CR_PWM_CH2H_CLR_LEN) - 1) << PWM_CR_PWM_CH2H_CLR_POS)) -#define PWM_CR_PWM_CH3L_CLR PWM_CR_PWM_CH3L_CLR -#define PWM_CR_PWM_CH3L_CLR_POS (6U) -#define PWM_CR_PWM_CH3L_CLR_LEN (1U) -#define PWM_CR_PWM_CH3L_CLR_MSK (((1U << PWM_CR_PWM_CH3L_CLR_LEN) - 1) << PWM_CR_PWM_CH3L_CLR_POS) -#define PWM_CR_PWM_CH3L_CLR_UMSK (~(((1U << PWM_CR_PWM_CH3L_CLR_LEN) - 1) << PWM_CR_PWM_CH3L_CLR_POS)) -#define PWM_CR_PWM_CH3H_CLR PWM_CR_PWM_CH3H_CLR -#define PWM_CR_PWM_CH3H_CLR_POS (7U) -#define PWM_CR_PWM_CH3H_CLR_LEN (1U) -#define PWM_CR_PWM_CH3H_CLR_MSK (((1U << PWM_CR_PWM_CH3H_CLR_LEN) - 1) << PWM_CR_PWM_CH3H_CLR_POS) -#define PWM_CR_PWM_CH3H_CLR_UMSK (~(((1U << PWM_CR_PWM_CH3H_CLR_LEN) - 1) << PWM_CR_PWM_CH3H_CLR_POS)) -#define PWM_CR_PWM_PRDE_CLR PWM_CR_PWM_PRDE_CLR -#define PWM_CR_PWM_PRDE_CLR_POS (8U) -#define PWM_CR_PWM_PRDE_CLR_LEN (1U) -#define PWM_CR_PWM_PRDE_CLR_MSK (((1U << PWM_CR_PWM_PRDE_CLR_LEN) - 1) << PWM_CR_PWM_PRDE_CLR_POS) -#define PWM_CR_PWM_PRDE_CLR_UMSK (~(((1U << PWM_CR_PWM_PRDE_CLR_LEN) - 1) << PWM_CR_PWM_PRDE_CLR_POS)) -#define PWM_CR_PWM_BRK_CLR PWM_CR_PWM_BRK_CLR -#define PWM_CR_PWM_BRK_CLR_POS (9U) -#define PWM_CR_PWM_BRK_CLR_LEN (1U) -#define PWM_CR_PWM_BRK_CLR_MSK (((1U << PWM_CR_PWM_BRK_CLR_LEN) - 1) << PWM_CR_PWM_BRK_CLR_POS) -#define PWM_CR_PWM_BRK_CLR_UMSK (~(((1U << PWM_CR_PWM_BRK_CLR_LEN) - 1) << PWM_CR_PWM_BRK_CLR_POS)) -#define PWM_CR_PWM_REPT_CLR PWM_CR_PWM_REPT_CLR -#define PWM_CR_PWM_REPT_CLR_POS (10U) -#define PWM_CR_PWM_REPT_CLR_LEN (1U) -#define PWM_CR_PWM_REPT_CLR_MSK (((1U << PWM_CR_PWM_REPT_CLR_LEN) - 1) << PWM_CR_PWM_REPT_CLR_POS) -#define PWM_CR_PWM_REPT_CLR_UMSK (~(((1U << PWM_CR_PWM_REPT_CLR_LEN) - 1) << PWM_CR_PWM_REPT_CLR_POS)) - -/* 0x2C : pwm_int_en */ -#define PWM_INT_EN_OFFSET (0x2C) -#define PWM_CR_PWM_CH0L_EN PWM_CR_PWM_CH0L_EN -#define PWM_CR_PWM_CH0L_EN_POS (0U) -#define PWM_CR_PWM_CH0L_EN_LEN (1U) -#define PWM_CR_PWM_CH0L_EN_MSK (((1U << PWM_CR_PWM_CH0L_EN_LEN) - 1) << PWM_CR_PWM_CH0L_EN_POS) -#define PWM_CR_PWM_CH0L_EN_UMSK (~(((1U << PWM_CR_PWM_CH0L_EN_LEN) - 1) << PWM_CR_PWM_CH0L_EN_POS)) -#define PWM_CR_PWM_CH0H_EN PWM_CR_PWM_CH0H_EN -#define PWM_CR_PWM_CH0H_EN_POS (1U) -#define PWM_CR_PWM_CH0H_EN_LEN (1U) -#define PWM_CR_PWM_CH0H_EN_MSK (((1U << PWM_CR_PWM_CH0H_EN_LEN) - 1) << PWM_CR_PWM_CH0H_EN_POS) -#define PWM_CR_PWM_CH0H_EN_UMSK (~(((1U << PWM_CR_PWM_CH0H_EN_LEN) - 1) << PWM_CR_PWM_CH0H_EN_POS)) -#define PWM_CR_PWM_CH1L_EN PWM_CR_PWM_CH1L_EN -#define PWM_CR_PWM_CH1L_EN_POS (2U) -#define PWM_CR_PWM_CH1L_EN_LEN (1U) -#define PWM_CR_PWM_CH1L_EN_MSK (((1U << PWM_CR_PWM_CH1L_EN_LEN) - 1) << PWM_CR_PWM_CH1L_EN_POS) -#define PWM_CR_PWM_CH1L_EN_UMSK (~(((1U << PWM_CR_PWM_CH1L_EN_LEN) - 1) << PWM_CR_PWM_CH1L_EN_POS)) -#define PWM_CR_PWM_CH1H_EN PWM_CR_PWM_CH1H_EN -#define PWM_CR_PWM_CH1H_EN_POS (3U) -#define PWM_CR_PWM_CH1H_EN_LEN (1U) -#define PWM_CR_PWM_CH1H_EN_MSK (((1U << PWM_CR_PWM_CH1H_EN_LEN) - 1) << PWM_CR_PWM_CH1H_EN_POS) -#define PWM_CR_PWM_CH1H_EN_UMSK (~(((1U << PWM_CR_PWM_CH1H_EN_LEN) - 1) << PWM_CR_PWM_CH1H_EN_POS)) -#define PWM_CR_PWM_CH2L_EN PWM_CR_PWM_CH2L_EN -#define PWM_CR_PWM_CH2L_EN_POS (4U) -#define PWM_CR_PWM_CH2L_EN_LEN (1U) -#define PWM_CR_PWM_CH2L_EN_MSK (((1U << PWM_CR_PWM_CH2L_EN_LEN) - 1) << PWM_CR_PWM_CH2L_EN_POS) -#define PWM_CR_PWM_CH2L_EN_UMSK (~(((1U << PWM_CR_PWM_CH2L_EN_LEN) - 1) << PWM_CR_PWM_CH2L_EN_POS)) -#define PWM_CR_PWM_CH2H_EN PWM_CR_PWM_CH2H_EN -#define PWM_CR_PWM_CH2H_EN_POS (5U) -#define PWM_CR_PWM_CH2H_EN_LEN (1U) -#define PWM_CR_PWM_CH2H_EN_MSK (((1U << PWM_CR_PWM_CH2H_EN_LEN) - 1) << PWM_CR_PWM_CH2H_EN_POS) -#define PWM_CR_PWM_CH2H_EN_UMSK (~(((1U << PWM_CR_PWM_CH2H_EN_LEN) - 1) << PWM_CR_PWM_CH2H_EN_POS)) -#define PWM_CR_PWM_CH3L_EN PWM_CR_PWM_CH3L_EN -#define PWM_CR_PWM_CH3L_EN_POS (6U) -#define PWM_CR_PWM_CH3L_EN_LEN (1U) -#define PWM_CR_PWM_CH3L_EN_MSK (((1U << PWM_CR_PWM_CH3L_EN_LEN) - 1) << PWM_CR_PWM_CH3L_EN_POS) -#define PWM_CR_PWM_CH3L_EN_UMSK (~(((1U << PWM_CR_PWM_CH3L_EN_LEN) - 1) << PWM_CR_PWM_CH3L_EN_POS)) -#define PWM_CR_PWM_CH3H_EN PWM_CR_PWM_CH3H_EN -#define PWM_CR_PWM_CH3H_EN_POS (7U) -#define PWM_CR_PWM_CH3H_EN_LEN (1U) -#define PWM_CR_PWM_CH3H_EN_MSK (((1U << PWM_CR_PWM_CH3H_EN_LEN) - 1) << PWM_CR_PWM_CH3H_EN_POS) -#define PWM_CR_PWM_CH3H_EN_UMSK (~(((1U << PWM_CR_PWM_CH3H_EN_LEN) - 1) << PWM_CR_PWM_CH3H_EN_POS)) -#define PWM_CR_PWM_PRDE_EN PWM_CR_PWM_PRDE_EN -#define PWM_CR_PWM_PRDE_EN_POS (8U) -#define PWM_CR_PWM_PRDE_EN_LEN (1U) -#define PWM_CR_PWM_PRDE_EN_MSK (((1U << PWM_CR_PWM_PRDE_EN_LEN) - 1) << PWM_CR_PWM_PRDE_EN_POS) -#define PWM_CR_PWM_PRDE_EN_UMSK (~(((1U << PWM_CR_PWM_PRDE_EN_LEN) - 1) << PWM_CR_PWM_PRDE_EN_POS)) -#define PWM_CR_PWM_BRK_EN PWM_CR_PWM_BRK_EN -#define PWM_CR_PWM_BRK_EN_POS (9U) -#define PWM_CR_PWM_BRK_EN_LEN (1U) -#define PWM_CR_PWM_BRK_EN_MSK (((1U << PWM_CR_PWM_BRK_EN_LEN) - 1) << PWM_CR_PWM_BRK_EN_POS) -#define PWM_CR_PWM_BRK_EN_UMSK (~(((1U << PWM_CR_PWM_BRK_EN_LEN) - 1) << PWM_CR_PWM_BRK_EN_POS)) -#define PWM_CR_PWM_REPT_EN PWM_CR_PWM_REPT_EN -#define PWM_CR_PWM_REPT_EN_POS (10U) -#define PWM_CR_PWM_REPT_EN_LEN (1U) -#define PWM_CR_PWM_REPT_EN_MSK (((1U << PWM_CR_PWM_REPT_EN_LEN) - 1) << PWM_CR_PWM_REPT_EN_POS) -#define PWM_CR_PWM_REPT_EN_UMSK (~(((1U << PWM_CR_PWM_REPT_EN_LEN) - 1) << PWM_CR_PWM_REPT_EN_POS)) - -struct pwm_channel_reg { - /* 0x00 : pwm_config0 */ - union { - struct { - uint32_t pwm_clk_div : 16; /* [15: 0], r/w, 0x0 */ - uint32_t reserved_16_18 : 3; /* [18:16], rsvd, 0x0 */ - uint32_t pwm_stop_on_rept : 1; /* [ 19], r/w, 0x0 */ - uint32_t pwm_adc_trg_src : 4; /* [23:20], r/w, 0xf */ - uint32_t pwm_sw_break_en : 1; /* [ 24], r/w, 0x0 */ - uint32_t pwm_ext_break_en : 1; /* [ 25], r/w, 0x0 */ - uint32_t pwm_ext_break_pl : 1; /* [ 26], r/w, 0x0 */ - uint32_t pwm_stop_en : 1; /* [ 27], r/w, 0x0 */ - uint32_t pwm_stop_mode : 1; /* [ 28], r/w, 0x1 */ - uint32_t pwm_sts_stop : 1; /* [ 29], r, 0x0 */ - uint32_t reg_clk_sel : 2; /* [31:30], r/w, 0x0 */ - } BF; - uint32_t WORD; - } pwm_config0; - - /* 0x04 : pwm_config1 */ - union { - struct { - uint32_t pwm_ch0_pen : 1; /* [ 0], r/w, 0x0 */ - uint32_t pwm_ch0_psi : 1; /* [ 1], r/w, 0x0 */ - uint32_t pwm_ch0_nen : 1; /* [ 2], r/w, 0x0 */ - uint32_t pwm_ch0_nsi : 1; /* [ 3], r/w, 0x1 */ - uint32_t pwm_ch1_pen : 1; /* [ 4], r/w, 0x0 */ - uint32_t pwm_ch1_psi : 1; /* [ 5], r/w, 0x0 */ - uint32_t pwm_ch1_nen : 1; /* [ 6], r/w, 0x0 */ - uint32_t pwm_ch1_nsi : 1; /* [ 7], r/w, 0x1 */ - uint32_t pwm_ch2_pen : 1; /* [ 8], r/w, 0x0 */ - uint32_t pwm_ch2_psi : 1; /* [ 9], r/w, 0x0 */ - uint32_t pwm_ch2_nen : 1; /* [ 10], r/w, 0x0 */ - uint32_t pwm_ch2_nsi : 1; /* [ 11], r/w, 0x1 */ - uint32_t pwm_ch3_pen : 1; /* [ 12], r/w, 0x0 */ - uint32_t pwm_ch3_psi : 1; /* [ 13], r/w, 0x0 */ - uint32_t pwm_ch3_nen : 1; /* [ 14], r/w, 0x0 */ - uint32_t pwm_ch3_nsi : 1; /* [ 15], r/w, 0x1 */ - uint32_t pwm_ch0_ppl : 1; /* [ 16], r/w, 0x1 */ - uint32_t pwm_ch0_npl : 1; /* [ 17], r/w, 0x1 */ - uint32_t pwm_ch1_ppl : 1; /* [ 18], r/w, 0x1 */ - uint32_t pwm_ch1_npl : 1; /* [ 19], r/w, 0x1 */ - uint32_t pwm_ch2_ppl : 1; /* [ 20], r/w, 0x1 */ - uint32_t pwm_ch2_npl : 1; /* [ 21], r/w, 0x1 */ - uint32_t pwm_ch3_ppl : 1; /* [ 22], r/w, 0x1 */ - uint32_t pwm_ch3_npl : 1; /* [ 23], r/w, 0x1 */ - uint32_t pwm_ch0_pbs : 1; /* [ 24], r/w, 0x0 */ - uint32_t pwm_ch0_nbs : 1; /* [ 25], r/w, 0x0 */ - uint32_t pwm_ch1_pbs : 1; /* [ 26], r/w, 0x0 */ - uint32_t pwm_ch1_nbs : 1; /* [ 27], r/w, 0x0 */ - uint32_t pwm_ch2_pbs : 1; /* [ 28], r/w, 0x0 */ - uint32_t pwm_ch2_nbs : 1; /* [ 29], r/w, 0x0 */ - uint32_t pwm_ch3_pbs : 1; /* [ 30], r/w, 0x0 */ - uint32_t pwm_ch3_nbs : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } pwm_config1; - - /* 0x08 : pwm_period */ - union { - struct { - uint32_t pwm_period : 16; /* [15: 0], r/w, 0x0 */ - uint32_t pwm_int_period_cnt : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } pwm_period; - - /* 0x0C : pwm_dead_time */ - union { - struct { - uint32_t pwm_ch0_dtg : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t pwm_ch1_dtg : 8; /* [15: 8], r/w, 0x0 */ - uint32_t pwm_ch2_dtg : 8; /* [23:16], r/w, 0x0 */ - uint32_t pwm_ch3_dtg : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } pwm_dead_time; - - /* 0x10 : pwm_ch0_thre */ - union { - struct { - uint32_t pwm_ch0_threL : 16; /* [15: 0], r/w, 0x0 */ - uint32_t pwm_ch0_threH : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } pwm_ch0_thre; - - /* 0x14 : pwm_ch1_thre */ - union { - struct { - uint32_t pwm_ch1_threL : 16; /* [15: 0], r/w, 0x0 */ - uint32_t pwm_ch1_threH : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } pwm_ch1_thre; - - /* 0x18 : pwm_ch2_thre */ - union { - struct { - uint32_t pwm_ch2_threL : 16; /* [15: 0], r/w, 0x0 */ - uint32_t pwm_ch2_threH : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } pwm_ch2_thre; - - /* 0x1C : pwm_ch3_thre */ - union { - struct { - uint32_t pwm_ch3_threL : 16; /* [15: 0], r/w, 0x0 */ - uint32_t pwm_ch3_threH : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } pwm_ch3_thre; - - /* 0x20 : pwm_int_sts */ - union { - struct { - uint32_t pwm_ch0l_int : 1; /* [ 0], r, 0x0 */ - uint32_t pwm_ch0h_int : 1; /* [ 1], r, 0x0 */ - uint32_t pwm_ch1l_int : 1; /* [ 2], r, 0x0 */ - uint32_t pwm_ch1h_int : 1; /* [ 3], r, 0x0 */ - uint32_t pwm_ch2l_int : 1; /* [ 4], r, 0x0 */ - uint32_t pwm_ch2h_int : 1; /* [ 5], r, 0x0 */ - uint32_t pwm_ch3l_int : 1; /* [ 6], r, 0x0 */ - uint32_t pwm_ch3h_int : 1; /* [ 7], r, 0x0 */ - uint32_t pwm_prde_int : 1; /* [ 8], r, 0x0 */ - uint32_t pwm_brk_int : 1; /* [ 9], r, 0x0 */ - uint32_t pwm_rept_int : 1; /* [ 10], r, 0x0 */ - uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } pwm_int_sts; - - /* 0x24 : pwm_int_mask */ - union { - struct { - uint32_t cr_pwm_ch0l_mask : 1; /* [ 0], r/w, 0x1 */ - uint32_t cr_pwm_ch0h_mask : 1; /* [ 1], r/w, 0x1 */ - uint32_t cr_pwm_ch1l_mask : 1; /* [ 2], r/w, 0x1 */ - uint32_t cr_pwm_ch1h_mask : 1; /* [ 3], r/w, 0x1 */ - uint32_t cr_pwm_ch2l_mask : 1; /* [ 4], r/w, 0x1 */ - uint32_t cr_pwm_ch2h_mask : 1; /* [ 5], r/w, 0x1 */ - uint32_t cr_pwm_ch3l_mask : 1; /* [ 6], r/w, 0x1 */ - uint32_t cr_pwm_ch3h_mask : 1; /* [ 7], r/w, 0x1 */ - uint32_t cr_pwm_prde_mask : 1; /* [ 8], r/w, 0x1 */ - uint32_t cr_pwm_brk_mask : 1; /* [ 9], r/w, 0x1 */ - uint32_t cr_pwm_rept_mask : 1; /* [ 10], r/w, 0x1 */ - uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } pwm_int_mask; - - /* 0x28 : pwm_int_clear */ - union { - struct { - uint32_t cr_pwm_ch0l_clr : 1; /* [ 0], w1c, 0x0 */ - uint32_t cr_pwm_ch0h_clr : 1; /* [ 1], w1c, 0x0 */ - uint32_t cr_pwm_ch1l_clr : 1; /* [ 2], w1c, 0x0 */ - uint32_t cr_pwm_ch1h_clr : 1; /* [ 3], w1c, 0x0 */ - uint32_t cr_pwm_ch2l_clr : 1; /* [ 4], w1c, 0x0 */ - uint32_t cr_pwm_ch2h_clr : 1; /* [ 5], w1c, 0x0 */ - uint32_t cr_pwm_ch3l_clr : 1; /* [ 6], w1c, 0x0 */ - uint32_t cr_pwm_ch3h_clr : 1; /* [ 7], w1c, 0x0 */ - uint32_t cr_pwm_prde_clr : 1; /* [ 8], w1c, 0x0 */ - uint32_t cr_pwm_brk_clr : 1; /* [ 9], w1c, 0x0 */ - uint32_t cr_pwm_rept_clr : 1; /* [ 10], w1c, 0x0 */ - uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } pwm_int_clear; - - /* 0x2C : pwm_int_en */ - union { - struct { - uint32_t cr_pwm_ch0l_en : 1; /* [ 0], r/w, 0x1 */ - uint32_t cr_pwm_ch0h_en : 1; /* [ 1], r/w, 0x1 */ - uint32_t cr_pwm_ch1l_en : 1; /* [ 2], r/w, 0x1 */ - uint32_t cr_pwm_ch1h_en : 1; /* [ 3], r/w, 0x1 */ - uint32_t cr_pwm_ch2l_en : 1; /* [ 4], r/w, 0x1 */ - uint32_t cr_pwm_ch2h_en : 1; /* [ 5], r/w, 0x1 */ - uint32_t cr_pwm_ch3l_en : 1; /* [ 6], r/w, 0x1 */ - uint32_t cr_pwm_ch3h_en : 1; /* [ 7], r/w, 0x1 */ - uint32_t cr_pwm_prde_en : 1; /* [ 8], r/w, 0x1 */ - uint32_t cr_pwm_brk_en : 1; /* [ 9], r/w, 0x0 */ - uint32_t cr_pwm_rept_en : 1; /* [ 10], r/w, 0x1 */ - uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } pwm_int_en; -}; - -typedef volatile struct pwm_channel_reg pwm_channel_reg_t; - -#define PWM_CHANNEL_OFFSET 0x40 - -#endif /* __PWM_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/sec_dbg_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/sec_dbg_reg.h deleted file mode 100644 index acde0e77f7..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/sec_dbg_reg.h +++ /dev/null @@ -1,209 +0,0 @@ -/** - ****************************************************************************** - * @file sec_dbg_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __SEC_DBG_REG_H__ -#define __SEC_DBG_REG_H__ - -#include "bl808.h" - -/* 0x0 : sd_chip_id_low */ -#define SEC_DBG_SD_CHIP_ID_LOW_OFFSET (0x0) -#define SEC_DBG_SD_CHIP_ID_LOW SEC_DBG_SD_CHIP_ID_LOW -#define SEC_DBG_SD_CHIP_ID_LOW_POS (0U) -#define SEC_DBG_SD_CHIP_ID_LOW_LEN (32U) -#define SEC_DBG_SD_CHIP_ID_LOW_MSK (((1U << SEC_DBG_SD_CHIP_ID_LOW_LEN) - 1) << SEC_DBG_SD_CHIP_ID_LOW_POS) -#define SEC_DBG_SD_CHIP_ID_LOW_UMSK (~(((1U << SEC_DBG_SD_CHIP_ID_LOW_LEN) - 1) << SEC_DBG_SD_CHIP_ID_LOW_POS)) - -/* 0x4 : sd_chip_id_high */ -#define SEC_DBG_SD_CHIP_ID_HIGH_OFFSET (0x4) -#define SEC_DBG_SD_CHIP_ID_HIGH SEC_DBG_SD_CHIP_ID_HIGH -#define SEC_DBG_SD_CHIP_ID_HIGH_POS (0U) -#define SEC_DBG_SD_CHIP_ID_HIGH_LEN (32U) -#define SEC_DBG_SD_CHIP_ID_HIGH_MSK (((1U << SEC_DBG_SD_CHIP_ID_HIGH_LEN) - 1) << SEC_DBG_SD_CHIP_ID_HIGH_POS) -#define SEC_DBG_SD_CHIP_ID_HIGH_UMSK (~(((1U << SEC_DBG_SD_CHIP_ID_HIGH_LEN) - 1) << SEC_DBG_SD_CHIP_ID_HIGH_POS)) - -/* 0x8 : sd_dbg_pwd_low */ -#define SEC_DBG_SD_DBG_PWD_LOW_OFFSET (0x8) -#define SEC_DBG_SD_DBG_PWD_LOW SEC_DBG_SD_DBG_PWD_LOW -#define SEC_DBG_SD_DBG_PWD_LOW_POS (0U) -#define SEC_DBG_SD_DBG_PWD_LOW_LEN (32U) -#define SEC_DBG_SD_DBG_PWD_LOW_MSK (((1U << SEC_DBG_SD_DBG_PWD_LOW_LEN) - 1) << SEC_DBG_SD_DBG_PWD_LOW_POS) -#define SEC_DBG_SD_DBG_PWD_LOW_UMSK (~(((1U << SEC_DBG_SD_DBG_PWD_LOW_LEN) - 1) << SEC_DBG_SD_DBG_PWD_LOW_POS)) - -/* 0xC : sd_dbg_pwd_high */ -#define SEC_DBG_SD_DBG_PWD_HIGH_OFFSET (0xC) -#define SEC_DBG_SD_DBG_PWD_HIGH SEC_DBG_SD_DBG_PWD_HIGH -#define SEC_DBG_SD_DBG_PWD_HIGH_POS (0U) -#define SEC_DBG_SD_DBG_PWD_HIGH_LEN (32U) -#define SEC_DBG_SD_DBG_PWD_HIGH_MSK (((1U << SEC_DBG_SD_DBG_PWD_HIGH_LEN) - 1) << SEC_DBG_SD_DBG_PWD_HIGH_POS) -#define SEC_DBG_SD_DBG_PWD_HIGH_UMSK (~(((1U << SEC_DBG_SD_DBG_PWD_HIGH_LEN) - 1) << SEC_DBG_SD_DBG_PWD_HIGH_POS)) - -/* 0x10 : sd_dbg_pwd2_low */ -#define SEC_DBG_SD_DBG_PWD2_LOW_OFFSET (0x10) -#define SEC_DBG_SD_DBG_PWD2_LOW SEC_DBG_SD_DBG_PWD2_LOW -#define SEC_DBG_SD_DBG_PWD2_LOW_POS (0U) -#define SEC_DBG_SD_DBG_PWD2_LOW_LEN (32U) -#define SEC_DBG_SD_DBG_PWD2_LOW_MSK (((1U << SEC_DBG_SD_DBG_PWD2_LOW_LEN) - 1) << SEC_DBG_SD_DBG_PWD2_LOW_POS) -#define SEC_DBG_SD_DBG_PWD2_LOW_UMSK (~(((1U << SEC_DBG_SD_DBG_PWD2_LOW_LEN) - 1) << SEC_DBG_SD_DBG_PWD2_LOW_POS)) - -/* 0x14 : sd_dbg_pwd2_high */ -#define SEC_DBG_SD_DBG_PWD2_HIGH_OFFSET (0x14) -#define SEC_DBG_SD_DBG_PWD2_HIGH SEC_DBG_SD_DBG_PWD2_HIGH -#define SEC_DBG_SD_DBG_PWD2_HIGH_POS (0U) -#define SEC_DBG_SD_DBG_PWD2_HIGH_LEN (32U) -#define SEC_DBG_SD_DBG_PWD2_HIGH_MSK (((1U << SEC_DBG_SD_DBG_PWD2_HIGH_LEN) - 1) << SEC_DBG_SD_DBG_PWD2_HIGH_POS) -#define SEC_DBG_SD_DBG_PWD2_HIGH_UMSK (~(((1U << SEC_DBG_SD_DBG_PWD2_HIGH_LEN) - 1) << SEC_DBG_SD_DBG_PWD2_HIGH_POS)) - -/* 0x18 : sd_status */ -#define SEC_DBG_SD_STATUS_OFFSET (0x18) -#define SEC_DBG_SD_DBG_PWD_BUSY SEC_DBG_SD_DBG_PWD_BUSY -#define SEC_DBG_SD_DBG_PWD_BUSY_POS (0U) -#define SEC_DBG_SD_DBG_PWD_BUSY_LEN (1U) -#define SEC_DBG_SD_DBG_PWD_BUSY_MSK (((1U << SEC_DBG_SD_DBG_PWD_BUSY_LEN) - 1) << SEC_DBG_SD_DBG_PWD_BUSY_POS) -#define SEC_DBG_SD_DBG_PWD_BUSY_UMSK (~(((1U << SEC_DBG_SD_DBG_PWD_BUSY_LEN) - 1) << SEC_DBG_SD_DBG_PWD_BUSY_POS)) -#define SEC_DBG_SD_DBG_PWD_TRIG SEC_DBG_SD_DBG_PWD_TRIG -#define SEC_DBG_SD_DBG_PWD_TRIG_POS (1U) -#define SEC_DBG_SD_DBG_PWD_TRIG_LEN (1U) -#define SEC_DBG_SD_DBG_PWD_TRIG_MSK (((1U << SEC_DBG_SD_DBG_PWD_TRIG_LEN) - 1) << SEC_DBG_SD_DBG_PWD_TRIG_POS) -#define SEC_DBG_SD_DBG_PWD_TRIG_UMSK (~(((1U << SEC_DBG_SD_DBG_PWD_TRIG_LEN) - 1) << SEC_DBG_SD_DBG_PWD_TRIG_POS)) -#define SEC_DBG_SD_DBG_CCI_READ_EN SEC_DBG_SD_DBG_CCI_READ_EN -#define SEC_DBG_SD_DBG_CCI_READ_EN_POS (2U) -#define SEC_DBG_SD_DBG_CCI_READ_EN_LEN (1U) -#define SEC_DBG_SD_DBG_CCI_READ_EN_MSK (((1U << SEC_DBG_SD_DBG_CCI_READ_EN_LEN) - 1) << SEC_DBG_SD_DBG_CCI_READ_EN_POS) -#define SEC_DBG_SD_DBG_CCI_READ_EN_UMSK (~(((1U << SEC_DBG_SD_DBG_CCI_READ_EN_LEN) - 1) << SEC_DBG_SD_DBG_CCI_READ_EN_POS)) -#define SEC_DBG_SD_DBG_CCI_CLK_SEL SEC_DBG_SD_DBG_CCI_CLK_SEL -#define SEC_DBG_SD_DBG_CCI_CLK_SEL_POS (3U) -#define SEC_DBG_SD_DBG_CCI_CLK_SEL_LEN (1U) -#define SEC_DBG_SD_DBG_CCI_CLK_SEL_MSK (((1U << SEC_DBG_SD_DBG_CCI_CLK_SEL_LEN) - 1) << SEC_DBG_SD_DBG_CCI_CLK_SEL_POS) -#define SEC_DBG_SD_DBG_CCI_CLK_SEL_UMSK (~(((1U << SEC_DBG_SD_DBG_CCI_CLK_SEL_LEN) - 1) << SEC_DBG_SD_DBG_CCI_CLK_SEL_POS)) -#define SEC_DBG_SD_DBG_PWD_CNT SEC_DBG_SD_DBG_PWD_CNT -#define SEC_DBG_SD_DBG_PWD_CNT_POS (4U) -#define SEC_DBG_SD_DBG_PWD_CNT_LEN (20U) -#define SEC_DBG_SD_DBG_PWD_CNT_MSK (((1U << SEC_DBG_SD_DBG_PWD_CNT_LEN) - 1) << SEC_DBG_SD_DBG_PWD_CNT_POS) -#define SEC_DBG_SD_DBG_PWD_CNT_UMSK (~(((1U << SEC_DBG_SD_DBG_PWD_CNT_LEN) - 1) << SEC_DBG_SD_DBG_PWD_CNT_POS)) -#define SEC_DBG_SD_DBG_MODE SEC_DBG_SD_DBG_MODE -#define SEC_DBG_SD_DBG_MODE_POS (24U) -#define SEC_DBG_SD_DBG_MODE_LEN (4U) -#define SEC_DBG_SD_DBG_MODE_MSK (((1U << SEC_DBG_SD_DBG_MODE_LEN) - 1) << SEC_DBG_SD_DBG_MODE_POS) -#define SEC_DBG_SD_DBG_MODE_UMSK (~(((1U << SEC_DBG_SD_DBG_MODE_LEN) - 1) << SEC_DBG_SD_DBG_MODE_POS)) -#define SEC_DBG_SD_DBG_ENA SEC_DBG_SD_DBG_ENA -#define SEC_DBG_SD_DBG_ENA_POS (28U) -#define SEC_DBG_SD_DBG_ENA_LEN (4U) -#define SEC_DBG_SD_DBG_ENA_MSK (((1U << SEC_DBG_SD_DBG_ENA_LEN) - 1) << SEC_DBG_SD_DBG_ENA_POS) -#define SEC_DBG_SD_DBG_ENA_UMSK (~(((1U << SEC_DBG_SD_DBG_ENA_LEN) - 1) << SEC_DBG_SD_DBG_ENA_POS)) - -/* 0x1C : sd_dbg_reserved */ -#define SEC_DBG_SD_DBG_RESERVED_OFFSET (0x1C) -#define SEC_DBG_SD_DBG_RESERVED SEC_DBG_SD_DBG_RESERVED -#define SEC_DBG_SD_DBG_RESERVED_POS (0U) -#define SEC_DBG_SD_DBG_RESERVED_LEN (32U) -#define SEC_DBG_SD_DBG_RESERVED_MSK (((1U << SEC_DBG_SD_DBG_RESERVED_LEN) - 1) << SEC_DBG_SD_DBG_RESERVED_POS) -#define SEC_DBG_SD_DBG_RESERVED_UMSK (~(((1U << SEC_DBG_SD_DBG_RESERVED_LEN) - 1) << SEC_DBG_SD_DBG_RESERVED_POS)) - -struct sec_dbg_reg { - /* 0x0 : sd_chip_id_low */ - union { - struct { - uint32_t sd_chip_id_low : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } sd_chip_id_low; - - /* 0x4 : sd_chip_id_high */ - union { - struct { - uint32_t sd_chip_id_high : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } sd_chip_id_high; - - /* 0x8 : sd_dbg_pwd_low */ - union { - struct { - uint32_t sd_dbg_pwd_low : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } sd_dbg_pwd_low; - - /* 0xC : sd_dbg_pwd_high */ - union { - struct { - uint32_t sd_dbg_pwd_high : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } sd_dbg_pwd_high; - - /* 0x10 : sd_dbg_pwd2_low */ - union { - struct { - uint32_t sd_dbg_pwd2_low : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } sd_dbg_pwd2_low; - - /* 0x14 : sd_dbg_pwd2_high */ - union { - struct { - uint32_t sd_dbg_pwd2_high : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } sd_dbg_pwd2_high; - - /* 0x18 : sd_status */ - union { - struct { - uint32_t sd_dbg_pwd_busy : 1; /* [ 0], r, 0x0 */ - uint32_t sd_dbg_pwd_trig : 1; /* [ 1], r/w, 0x0 */ - uint32_t sd_dbg_cci_read_en : 1; /* [ 2], r/w, 0x0 */ - uint32_t sd_dbg_cci_clk_sel : 1; /* [ 3], r/w, 0x0 */ - uint32_t sd_dbg_pwd_cnt : 20; /* [23: 4], r, 0x0 */ - uint32_t sd_dbg_mode : 4; /* [27:24], r, 0x0 */ - uint32_t sd_dbg_ena : 4; /* [31:28], r, 0x0 */ - } BF; - uint32_t WORD; - } sd_status; - - /* 0x1C : sd_dbg_reserved */ - union { - struct { - uint32_t sd_dbg_reserved : 32; /* [31: 0], r/w, 0xffff */ - } BF; - uint32_t WORD; - } sd_dbg_reserved; -}; - -typedef volatile struct sec_dbg_reg sec_dbg_reg_t; - -#endif /* __SEC_DBG_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/sec_eng_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/sec_eng_reg.h deleted file mode 100644 index e3ea2ef9e9..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/sec_eng_reg.h +++ /dev/null @@ -1,1966 +0,0 @@ -/** - ****************************************************************************** - * @file sec_eng_reg.h - * @version V1.0 - * @date 2021-07-13 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __SEC_ENG_REG_H__ -#define __SEC_ENG_REG_H__ - -#include "bl808.h" - -/* 0x0 : se_sha_0_ctrl */ -#define SEC_ENG_SE_SHA_0_CTRL_OFFSET (0x0) -#define SEC_ENG_SE_SHA_0_BUSY SEC_ENG_SE_SHA_0_BUSY -#define SEC_ENG_SE_SHA_0_BUSY_POS (0U) -#define SEC_ENG_SE_SHA_0_BUSY_LEN (1U) -#define SEC_ENG_SE_SHA_0_BUSY_MSK (((1U << SEC_ENG_SE_SHA_0_BUSY_LEN) - 1) << SEC_ENG_SE_SHA_0_BUSY_POS) -#define SEC_ENG_SE_SHA_0_BUSY_UMSK (~(((1U << SEC_ENG_SE_SHA_0_BUSY_LEN) - 1) << SEC_ENG_SE_SHA_0_BUSY_POS)) -#define SEC_ENG_SE_SHA_0_TRIG_1T SEC_ENG_SE_SHA_0_TRIG_1T -#define SEC_ENG_SE_SHA_0_TRIG_1T_POS (1U) -#define SEC_ENG_SE_SHA_0_TRIG_1T_LEN (1U) -#define SEC_ENG_SE_SHA_0_TRIG_1T_MSK (((1U << SEC_ENG_SE_SHA_0_TRIG_1T_LEN) - 1) << SEC_ENG_SE_SHA_0_TRIG_1T_POS) -#define SEC_ENG_SE_SHA_0_TRIG_1T_UMSK (~(((1U << SEC_ENG_SE_SHA_0_TRIG_1T_LEN) - 1) << SEC_ENG_SE_SHA_0_TRIG_1T_POS)) -#define SEC_ENG_SE_SHA_0_MODE SEC_ENG_SE_SHA_0_MODE -#define SEC_ENG_SE_SHA_0_MODE_POS (2U) -#define SEC_ENG_SE_SHA_0_MODE_LEN (3U) -#define SEC_ENG_SE_SHA_0_MODE_MSK (((1U << SEC_ENG_SE_SHA_0_MODE_LEN) - 1) << SEC_ENG_SE_SHA_0_MODE_POS) -#define SEC_ENG_SE_SHA_0_MODE_UMSK (~(((1U << SEC_ENG_SE_SHA_0_MODE_LEN) - 1) << SEC_ENG_SE_SHA_0_MODE_POS)) -#define SEC_ENG_SE_SHA_0_EN SEC_ENG_SE_SHA_0_EN -#define SEC_ENG_SE_SHA_0_EN_POS (5U) -#define SEC_ENG_SE_SHA_0_EN_LEN (1U) -#define SEC_ENG_SE_SHA_0_EN_MSK (((1U << SEC_ENG_SE_SHA_0_EN_LEN) - 1) << SEC_ENG_SE_SHA_0_EN_POS) -#define SEC_ENG_SE_SHA_0_EN_UMSK (~(((1U << SEC_ENG_SE_SHA_0_EN_LEN) - 1) << SEC_ENG_SE_SHA_0_EN_POS)) -#define SEC_ENG_SE_SHA_0_HASH_SEL SEC_ENG_SE_SHA_0_HASH_SEL -#define SEC_ENG_SE_SHA_0_HASH_SEL_POS (6U) -#define SEC_ENG_SE_SHA_0_HASH_SEL_LEN (1U) -#define SEC_ENG_SE_SHA_0_HASH_SEL_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_SEL_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_SEL_POS) -#define SEC_ENG_SE_SHA_0_HASH_SEL_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_SEL_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_SEL_POS)) -#define SEC_ENG_SE_SHA_0_INT SEC_ENG_SE_SHA_0_INT -#define SEC_ENG_SE_SHA_0_INT_POS (8U) -#define SEC_ENG_SE_SHA_0_INT_LEN (1U) -#define SEC_ENG_SE_SHA_0_INT_MSK (((1U << SEC_ENG_SE_SHA_0_INT_LEN) - 1) << SEC_ENG_SE_SHA_0_INT_POS) -#define SEC_ENG_SE_SHA_0_INT_UMSK (~(((1U << SEC_ENG_SE_SHA_0_INT_LEN) - 1) << SEC_ENG_SE_SHA_0_INT_POS)) -#define SEC_ENG_SE_SHA_0_INT_CLR_1T SEC_ENG_SE_SHA_0_INT_CLR_1T -#define SEC_ENG_SE_SHA_0_INT_CLR_1T_POS (9U) -#define SEC_ENG_SE_SHA_0_INT_CLR_1T_LEN (1U) -#define SEC_ENG_SE_SHA_0_INT_CLR_1T_MSK (((1U << SEC_ENG_SE_SHA_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_SHA_0_INT_CLR_1T_POS) -#define SEC_ENG_SE_SHA_0_INT_CLR_1T_UMSK (~(((1U << SEC_ENG_SE_SHA_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_SHA_0_INT_CLR_1T_POS)) -#define SEC_ENG_SE_SHA_0_INT_SET_1T SEC_ENG_SE_SHA_0_INT_SET_1T -#define SEC_ENG_SE_SHA_0_INT_SET_1T_POS (10U) -#define SEC_ENG_SE_SHA_0_INT_SET_1T_LEN (1U) -#define SEC_ENG_SE_SHA_0_INT_SET_1T_MSK (((1U << SEC_ENG_SE_SHA_0_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_SHA_0_INT_SET_1T_POS) -#define SEC_ENG_SE_SHA_0_INT_SET_1T_UMSK (~(((1U << SEC_ENG_SE_SHA_0_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_SHA_0_INT_SET_1T_POS)) -#define SEC_ENG_SE_SHA_0_INT_MASK SEC_ENG_SE_SHA_0_INT_MASK -#define SEC_ENG_SE_SHA_0_INT_MASK_POS (11U) -#define SEC_ENG_SE_SHA_0_INT_MASK_LEN (1U) -#define SEC_ENG_SE_SHA_0_INT_MASK_MSK (((1U << SEC_ENG_SE_SHA_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_SHA_0_INT_MASK_POS) -#define SEC_ENG_SE_SHA_0_INT_MASK_UMSK (~(((1U << SEC_ENG_SE_SHA_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_SHA_0_INT_MASK_POS)) -#define SEC_ENG_SE_SHA_0_MODE_EXT SEC_ENG_SE_SHA_0_MODE_EXT -#define SEC_ENG_SE_SHA_0_MODE_EXT_POS (12U) -#define SEC_ENG_SE_SHA_0_MODE_EXT_LEN (2U) -#define SEC_ENG_SE_SHA_0_MODE_EXT_MSK (((1U << SEC_ENG_SE_SHA_0_MODE_EXT_LEN) - 1) << SEC_ENG_SE_SHA_0_MODE_EXT_POS) -#define SEC_ENG_SE_SHA_0_MODE_EXT_UMSK (~(((1U << SEC_ENG_SE_SHA_0_MODE_EXT_LEN) - 1) << SEC_ENG_SE_SHA_0_MODE_EXT_POS)) -#define SEC_ENG_SE_SHA_0_LINK_MODE SEC_ENG_SE_SHA_0_LINK_MODE -#define SEC_ENG_SE_SHA_0_LINK_MODE_POS (15U) -#define SEC_ENG_SE_SHA_0_LINK_MODE_LEN (1U) -#define SEC_ENG_SE_SHA_0_LINK_MODE_MSK (((1U << SEC_ENG_SE_SHA_0_LINK_MODE_LEN) - 1) << SEC_ENG_SE_SHA_0_LINK_MODE_POS) -#define SEC_ENG_SE_SHA_0_LINK_MODE_UMSK (~(((1U << SEC_ENG_SE_SHA_0_LINK_MODE_LEN) - 1) << SEC_ENG_SE_SHA_0_LINK_MODE_POS)) -#define SEC_ENG_SE_SHA_0_MSG_LEN SEC_ENG_SE_SHA_0_MSG_LEN -#define SEC_ENG_SE_SHA_0_MSG_LEN_POS (16U) -#define SEC_ENG_SE_SHA_0_MSG_LEN_LEN (16U) -#define SEC_ENG_SE_SHA_0_MSG_LEN_MSK (((1U << SEC_ENG_SE_SHA_0_MSG_LEN_LEN) - 1) << SEC_ENG_SE_SHA_0_MSG_LEN_POS) -#define SEC_ENG_SE_SHA_0_MSG_LEN_UMSK (~(((1U << SEC_ENG_SE_SHA_0_MSG_LEN_LEN) - 1) << SEC_ENG_SE_SHA_0_MSG_LEN_POS)) - -/* 0x4 : se_sha_0_msa */ -#define SEC_ENG_SE_SHA_0_MSA_OFFSET (0x4) -#define SEC_ENG_SE_SHA_0_MSA SEC_ENG_SE_SHA_0_MSA -#define SEC_ENG_SE_SHA_0_MSA_POS (0U) -#define SEC_ENG_SE_SHA_0_MSA_LEN (32U) -#define SEC_ENG_SE_SHA_0_MSA_MSK (((1U << SEC_ENG_SE_SHA_0_MSA_LEN) - 1) << SEC_ENG_SE_SHA_0_MSA_POS) -#define SEC_ENG_SE_SHA_0_MSA_UMSK (~(((1U << SEC_ENG_SE_SHA_0_MSA_LEN) - 1) << SEC_ENG_SE_SHA_0_MSA_POS)) - -/* 0x8 : se_sha_0_status */ -#define SEC_ENG_SE_SHA_0_STATUS_OFFSET (0x8) -#define SEC_ENG_SE_SHA_0_STATUS SEC_ENG_SE_SHA_0_STATUS -#define SEC_ENG_SE_SHA_0_STATUS_POS (0U) -#define SEC_ENG_SE_SHA_0_STATUS_LEN (32U) -#define SEC_ENG_SE_SHA_0_STATUS_MSK (((1U << SEC_ENG_SE_SHA_0_STATUS_LEN) - 1) << SEC_ENG_SE_SHA_0_STATUS_POS) -#define SEC_ENG_SE_SHA_0_STATUS_UMSK (~(((1U << SEC_ENG_SE_SHA_0_STATUS_LEN) - 1) << SEC_ENG_SE_SHA_0_STATUS_POS)) - -/* 0xC : se_sha_0_endian */ -#define SEC_ENG_SE_SHA_0_ENDIAN_OFFSET (0xC) -#define SEC_ENG_SE_SHA_0_DOUT_ENDIAN SEC_ENG_SE_SHA_0_DOUT_ENDIAN -#define SEC_ENG_SE_SHA_0_DOUT_ENDIAN_POS (0U) -#define SEC_ENG_SE_SHA_0_DOUT_ENDIAN_LEN (1U) -#define SEC_ENG_SE_SHA_0_DOUT_ENDIAN_MSK (((1U << SEC_ENG_SE_SHA_0_DOUT_ENDIAN_LEN) - 1) << SEC_ENG_SE_SHA_0_DOUT_ENDIAN_POS) -#define SEC_ENG_SE_SHA_0_DOUT_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_SHA_0_DOUT_ENDIAN_LEN) - 1) << SEC_ENG_SE_SHA_0_DOUT_ENDIAN_POS)) - -/* 0x10 : se_sha_0_hash_l_0 */ -#define SEC_ENG_SE_SHA_0_HASH_L_0_OFFSET (0x10) -#define SEC_ENG_SE_SHA_0_HASH_L_0 SEC_ENG_SE_SHA_0_HASH_L_0 -#define SEC_ENG_SE_SHA_0_HASH_L_0_POS (0U) -#define SEC_ENG_SE_SHA_0_HASH_L_0_LEN (32U) -#define SEC_ENG_SE_SHA_0_HASH_L_0_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_L_0_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_0_POS) -#define SEC_ENG_SE_SHA_0_HASH_L_0_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_L_0_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_0_POS)) - -/* 0x14 : se_sha_0_hash_l_1 */ -#define SEC_ENG_SE_SHA_0_HASH_L_1_OFFSET (0x14) -#define SEC_ENG_SE_SHA_0_HASH_L_1 SEC_ENG_SE_SHA_0_HASH_L_1 -#define SEC_ENG_SE_SHA_0_HASH_L_1_POS (0U) -#define SEC_ENG_SE_SHA_0_HASH_L_1_LEN (32U) -#define SEC_ENG_SE_SHA_0_HASH_L_1_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_L_1_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_1_POS) -#define SEC_ENG_SE_SHA_0_HASH_L_1_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_L_1_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_1_POS)) - -/* 0x18 : se_sha_0_hash_l_2 */ -#define SEC_ENG_SE_SHA_0_HASH_L_2_OFFSET (0x18) -#define SEC_ENG_SE_SHA_0_HASH_L_2 SEC_ENG_SE_SHA_0_HASH_L_2 -#define SEC_ENG_SE_SHA_0_HASH_L_2_POS (0U) -#define SEC_ENG_SE_SHA_0_HASH_L_2_LEN (32U) -#define SEC_ENG_SE_SHA_0_HASH_L_2_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_L_2_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_2_POS) -#define SEC_ENG_SE_SHA_0_HASH_L_2_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_L_2_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_2_POS)) - -/* 0x1C : se_sha_0_hash_l_3 */ -#define SEC_ENG_SE_SHA_0_HASH_L_3_OFFSET (0x1C) -#define SEC_ENG_SE_SHA_0_HASH_L_3 SEC_ENG_SE_SHA_0_HASH_L_3 -#define SEC_ENG_SE_SHA_0_HASH_L_3_POS (0U) -#define SEC_ENG_SE_SHA_0_HASH_L_3_LEN (32U) -#define SEC_ENG_SE_SHA_0_HASH_L_3_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_L_3_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_3_POS) -#define SEC_ENG_SE_SHA_0_HASH_L_3_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_L_3_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_3_POS)) - -/* 0x20 : se_sha_0_hash_l_4 */ -#define SEC_ENG_SE_SHA_0_HASH_L_4_OFFSET (0x20) -#define SEC_ENG_SE_SHA_0_HASH_L_4 SEC_ENG_SE_SHA_0_HASH_L_4 -#define SEC_ENG_SE_SHA_0_HASH_L_4_POS (0U) -#define SEC_ENG_SE_SHA_0_HASH_L_4_LEN (32U) -#define SEC_ENG_SE_SHA_0_HASH_L_4_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_L_4_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_4_POS) -#define SEC_ENG_SE_SHA_0_HASH_L_4_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_L_4_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_4_POS)) - -/* 0x24 : se_sha_0_hash_l_5 */ -#define SEC_ENG_SE_SHA_0_HASH_L_5_OFFSET (0x24) -#define SEC_ENG_SE_SHA_0_HASH_L_5 SEC_ENG_SE_SHA_0_HASH_L_5 -#define SEC_ENG_SE_SHA_0_HASH_L_5_POS (0U) -#define SEC_ENG_SE_SHA_0_HASH_L_5_LEN (32U) -#define SEC_ENG_SE_SHA_0_HASH_L_5_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_L_5_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_5_POS) -#define SEC_ENG_SE_SHA_0_HASH_L_5_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_L_5_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_5_POS)) - -/* 0x28 : se_sha_0_hash_l_6 */ -#define SEC_ENG_SE_SHA_0_HASH_L_6_OFFSET (0x28) -#define SEC_ENG_SE_SHA_0_HASH_L_6 SEC_ENG_SE_SHA_0_HASH_L_6 -#define SEC_ENG_SE_SHA_0_HASH_L_6_POS (0U) -#define SEC_ENG_SE_SHA_0_HASH_L_6_LEN (32U) -#define SEC_ENG_SE_SHA_0_HASH_L_6_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_L_6_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_6_POS) -#define SEC_ENG_SE_SHA_0_HASH_L_6_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_L_6_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_6_POS)) - -/* 0x2C : se_sha_0_hash_l_7 */ -#define SEC_ENG_SE_SHA_0_HASH_L_7_OFFSET (0x2C) -#define SEC_ENG_SE_SHA_0_HASH_L_7 SEC_ENG_SE_SHA_0_HASH_L_7 -#define SEC_ENG_SE_SHA_0_HASH_L_7_POS (0U) -#define SEC_ENG_SE_SHA_0_HASH_L_7_LEN (32U) -#define SEC_ENG_SE_SHA_0_HASH_L_7_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_L_7_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_7_POS) -#define SEC_ENG_SE_SHA_0_HASH_L_7_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_L_7_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_7_POS)) - -/* 0x30 : se_sha_0_hash_h_0 */ -#define SEC_ENG_SE_SHA_0_HASH_H_0_OFFSET (0x30) -#define SEC_ENG_SE_SHA_0_HASH_H_0 SEC_ENG_SE_SHA_0_HASH_H_0 -#define SEC_ENG_SE_SHA_0_HASH_H_0_POS (0U) -#define SEC_ENG_SE_SHA_0_HASH_H_0_LEN (32U) -#define SEC_ENG_SE_SHA_0_HASH_H_0_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_H_0_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_0_POS) -#define SEC_ENG_SE_SHA_0_HASH_H_0_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_H_0_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_0_POS)) - -/* 0x34 : se_sha_0_hash_h_1 */ -#define SEC_ENG_SE_SHA_0_HASH_H_1_OFFSET (0x34) -#define SEC_ENG_SE_SHA_0_HASH_H_1 SEC_ENG_SE_SHA_0_HASH_H_1 -#define SEC_ENG_SE_SHA_0_HASH_H_1_POS (0U) -#define SEC_ENG_SE_SHA_0_HASH_H_1_LEN (32U) -#define SEC_ENG_SE_SHA_0_HASH_H_1_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_H_1_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_1_POS) -#define SEC_ENG_SE_SHA_0_HASH_H_1_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_H_1_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_1_POS)) - -/* 0x38 : se_sha_0_hash_h_2 */ -#define SEC_ENG_SE_SHA_0_HASH_H_2_OFFSET (0x38) -#define SEC_ENG_SE_SHA_0_HASH_H_2 SEC_ENG_SE_SHA_0_HASH_H_2 -#define SEC_ENG_SE_SHA_0_HASH_H_2_POS (0U) -#define SEC_ENG_SE_SHA_0_HASH_H_2_LEN (32U) -#define SEC_ENG_SE_SHA_0_HASH_H_2_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_H_2_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_2_POS) -#define SEC_ENG_SE_SHA_0_HASH_H_2_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_H_2_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_2_POS)) - -/* 0x3C : se_sha_0_hash_h_3 */ -#define SEC_ENG_SE_SHA_0_HASH_H_3_OFFSET (0x3C) -#define SEC_ENG_SE_SHA_0_HASH_H_3 SEC_ENG_SE_SHA_0_HASH_H_3 -#define SEC_ENG_SE_SHA_0_HASH_H_3_POS (0U) -#define SEC_ENG_SE_SHA_0_HASH_H_3_LEN (32U) -#define SEC_ENG_SE_SHA_0_HASH_H_3_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_H_3_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_3_POS) -#define SEC_ENG_SE_SHA_0_HASH_H_3_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_H_3_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_3_POS)) - -/* 0x40 : se_sha_0_hash_h_4 */ -#define SEC_ENG_SE_SHA_0_HASH_H_4_OFFSET (0x40) -#define SEC_ENG_SE_SHA_0_HASH_H_4 SEC_ENG_SE_SHA_0_HASH_H_4 -#define SEC_ENG_SE_SHA_0_HASH_H_4_POS (0U) -#define SEC_ENG_SE_SHA_0_HASH_H_4_LEN (32U) -#define SEC_ENG_SE_SHA_0_HASH_H_4_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_H_4_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_4_POS) -#define SEC_ENG_SE_SHA_0_HASH_H_4_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_H_4_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_4_POS)) - -/* 0x44 : se_sha_0_hash_h_5 */ -#define SEC_ENG_SE_SHA_0_HASH_H_5_OFFSET (0x44) -#define SEC_ENG_SE_SHA_0_HASH_H_5 SEC_ENG_SE_SHA_0_HASH_H_5 -#define SEC_ENG_SE_SHA_0_HASH_H_5_POS (0U) -#define SEC_ENG_SE_SHA_0_HASH_H_5_LEN (32U) -#define SEC_ENG_SE_SHA_0_HASH_H_5_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_H_5_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_5_POS) -#define SEC_ENG_SE_SHA_0_HASH_H_5_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_H_5_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_5_POS)) - -/* 0x48 : se_sha_0_hash_h_6 */ -#define SEC_ENG_SE_SHA_0_HASH_H_6_OFFSET (0x48) -#define SEC_ENG_SE_SHA_0_HASH_H_6 SEC_ENG_SE_SHA_0_HASH_H_6 -#define SEC_ENG_SE_SHA_0_HASH_H_6_POS (0U) -#define SEC_ENG_SE_SHA_0_HASH_H_6_LEN (32U) -#define SEC_ENG_SE_SHA_0_HASH_H_6_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_H_6_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_6_POS) -#define SEC_ENG_SE_SHA_0_HASH_H_6_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_H_6_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_6_POS)) - -/* 0x4C : se_sha_0_hash_h_7 */ -#define SEC_ENG_SE_SHA_0_HASH_H_7_OFFSET (0x4C) -#define SEC_ENG_SE_SHA_0_HASH_H_7 SEC_ENG_SE_SHA_0_HASH_H_7 -#define SEC_ENG_SE_SHA_0_HASH_H_7_POS (0U) -#define SEC_ENG_SE_SHA_0_HASH_H_7_LEN (32U) -#define SEC_ENG_SE_SHA_0_HASH_H_7_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_H_7_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_7_POS) -#define SEC_ENG_SE_SHA_0_HASH_H_7_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_H_7_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_7_POS)) - -/* 0x50 : se_sha_0_link */ -#define SEC_ENG_SE_SHA_0_LINK_OFFSET (0x50) -#define SEC_ENG_SE_SHA_0_LCA SEC_ENG_SE_SHA_0_LCA -#define SEC_ENG_SE_SHA_0_LCA_POS (0U) -#define SEC_ENG_SE_SHA_0_LCA_LEN (32U) -#define SEC_ENG_SE_SHA_0_LCA_MSK (((1U << SEC_ENG_SE_SHA_0_LCA_LEN) - 1) << SEC_ENG_SE_SHA_0_LCA_POS) -#define SEC_ENG_SE_SHA_0_LCA_UMSK (~(((1U << SEC_ENG_SE_SHA_0_LCA_LEN) - 1) << SEC_ENG_SE_SHA_0_LCA_POS)) - -/* 0xFC : se_sha_0_ctrl_prot */ -#define SEC_ENG_SE_SHA_0_CTRL_PROT_OFFSET (0xFC) -#define SEC_ENG_SE_SHA_ID0_EN SEC_ENG_SE_SHA_ID0_EN -#define SEC_ENG_SE_SHA_ID0_EN_POS (1U) -#define SEC_ENG_SE_SHA_ID0_EN_LEN (1U) -#define SEC_ENG_SE_SHA_ID0_EN_MSK (((1U << SEC_ENG_SE_SHA_ID0_EN_LEN) - 1) << SEC_ENG_SE_SHA_ID0_EN_POS) -#define SEC_ENG_SE_SHA_ID0_EN_UMSK (~(((1U << SEC_ENG_SE_SHA_ID0_EN_LEN) - 1) << SEC_ENG_SE_SHA_ID0_EN_POS)) -#define SEC_ENG_SE_SHA_ID1_EN SEC_ENG_SE_SHA_ID1_EN -#define SEC_ENG_SE_SHA_ID1_EN_POS (2U) -#define SEC_ENG_SE_SHA_ID1_EN_LEN (1U) -#define SEC_ENG_SE_SHA_ID1_EN_MSK (((1U << SEC_ENG_SE_SHA_ID1_EN_LEN) - 1) << SEC_ENG_SE_SHA_ID1_EN_POS) -#define SEC_ENG_SE_SHA_ID1_EN_UMSK (~(((1U << SEC_ENG_SE_SHA_ID1_EN_LEN) - 1) << SEC_ENG_SE_SHA_ID1_EN_POS)) - -/* 0x100 : se_aes_0_ctrl */ -#define SEC_ENG_SE_AES_0_CTRL_OFFSET (0x100) -#define SEC_ENG_SE_AES_0_BUSY SEC_ENG_SE_AES_0_BUSY -#define SEC_ENG_SE_AES_0_BUSY_POS (0U) -#define SEC_ENG_SE_AES_0_BUSY_LEN (1U) -#define SEC_ENG_SE_AES_0_BUSY_MSK (((1U << SEC_ENG_SE_AES_0_BUSY_LEN) - 1) << SEC_ENG_SE_AES_0_BUSY_POS) -#define SEC_ENG_SE_AES_0_BUSY_UMSK (~(((1U << SEC_ENG_SE_AES_0_BUSY_LEN) - 1) << SEC_ENG_SE_AES_0_BUSY_POS)) -#define SEC_ENG_SE_AES_0_TRIG_1T SEC_ENG_SE_AES_0_TRIG_1T -#define SEC_ENG_SE_AES_0_TRIG_1T_POS (1U) -#define SEC_ENG_SE_AES_0_TRIG_1T_LEN (1U) -#define SEC_ENG_SE_AES_0_TRIG_1T_MSK (((1U << SEC_ENG_SE_AES_0_TRIG_1T_LEN) - 1) << SEC_ENG_SE_AES_0_TRIG_1T_POS) -#define SEC_ENG_SE_AES_0_TRIG_1T_UMSK (~(((1U << SEC_ENG_SE_AES_0_TRIG_1T_LEN) - 1) << SEC_ENG_SE_AES_0_TRIG_1T_POS)) -#define SEC_ENG_SE_AES_0_EN SEC_ENG_SE_AES_0_EN -#define SEC_ENG_SE_AES_0_EN_POS (2U) -#define SEC_ENG_SE_AES_0_EN_LEN (1U) -#define SEC_ENG_SE_AES_0_EN_MSK (((1U << SEC_ENG_SE_AES_0_EN_LEN) - 1) << SEC_ENG_SE_AES_0_EN_POS) -#define SEC_ENG_SE_AES_0_EN_UMSK (~(((1U << SEC_ENG_SE_AES_0_EN_LEN) - 1) << SEC_ENG_SE_AES_0_EN_POS)) -#define SEC_ENG_SE_AES_0_MODE SEC_ENG_SE_AES_0_MODE -#define SEC_ENG_SE_AES_0_MODE_POS (3U) -#define SEC_ENG_SE_AES_0_MODE_LEN (2U) -#define SEC_ENG_SE_AES_0_MODE_MSK (((1U << SEC_ENG_SE_AES_0_MODE_LEN) - 1) << SEC_ENG_SE_AES_0_MODE_POS) -#define SEC_ENG_SE_AES_0_MODE_UMSK (~(((1U << SEC_ENG_SE_AES_0_MODE_LEN) - 1) << SEC_ENG_SE_AES_0_MODE_POS)) -#define SEC_ENG_SE_AES_0_DEC_EN SEC_ENG_SE_AES_0_DEC_EN -#define SEC_ENG_SE_AES_0_DEC_EN_POS (5U) -#define SEC_ENG_SE_AES_0_DEC_EN_LEN (1U) -#define SEC_ENG_SE_AES_0_DEC_EN_MSK (((1U << SEC_ENG_SE_AES_0_DEC_EN_LEN) - 1) << SEC_ENG_SE_AES_0_DEC_EN_POS) -#define SEC_ENG_SE_AES_0_DEC_EN_UMSK (~(((1U << SEC_ENG_SE_AES_0_DEC_EN_LEN) - 1) << SEC_ENG_SE_AES_0_DEC_EN_POS)) -#define SEC_ENG_SE_AES_0_DEC_KEY_SEL SEC_ENG_SE_AES_0_DEC_KEY_SEL -#define SEC_ENG_SE_AES_0_DEC_KEY_SEL_POS (6U) -#define SEC_ENG_SE_AES_0_DEC_KEY_SEL_LEN (1U) -#define SEC_ENG_SE_AES_0_DEC_KEY_SEL_MSK (((1U << SEC_ENG_SE_AES_0_DEC_KEY_SEL_LEN) - 1) << SEC_ENG_SE_AES_0_DEC_KEY_SEL_POS) -#define SEC_ENG_SE_AES_0_DEC_KEY_SEL_UMSK (~(((1U << SEC_ENG_SE_AES_0_DEC_KEY_SEL_LEN) - 1) << SEC_ENG_SE_AES_0_DEC_KEY_SEL_POS)) -#define SEC_ENG_SE_AES_0_HW_KEY_EN SEC_ENG_SE_AES_0_HW_KEY_EN -#define SEC_ENG_SE_AES_0_HW_KEY_EN_POS (7U) -#define SEC_ENG_SE_AES_0_HW_KEY_EN_LEN (1U) -#define SEC_ENG_SE_AES_0_HW_KEY_EN_MSK (((1U << SEC_ENG_SE_AES_0_HW_KEY_EN_LEN) - 1) << SEC_ENG_SE_AES_0_HW_KEY_EN_POS) -#define SEC_ENG_SE_AES_0_HW_KEY_EN_UMSK (~(((1U << SEC_ENG_SE_AES_0_HW_KEY_EN_LEN) - 1) << SEC_ENG_SE_AES_0_HW_KEY_EN_POS)) -#define SEC_ENG_SE_AES_0_INT SEC_ENG_SE_AES_0_INT -#define SEC_ENG_SE_AES_0_INT_POS (8U) -#define SEC_ENG_SE_AES_0_INT_LEN (1U) -#define SEC_ENG_SE_AES_0_INT_MSK (((1U << SEC_ENG_SE_AES_0_INT_LEN) - 1) << SEC_ENG_SE_AES_0_INT_POS) -#define SEC_ENG_SE_AES_0_INT_UMSK (~(((1U << SEC_ENG_SE_AES_0_INT_LEN) - 1) << SEC_ENG_SE_AES_0_INT_POS)) -#define SEC_ENG_SE_AES_0_INT_CLR_1T SEC_ENG_SE_AES_0_INT_CLR_1T -#define SEC_ENG_SE_AES_0_INT_CLR_1T_POS (9U) -#define SEC_ENG_SE_AES_0_INT_CLR_1T_LEN (1U) -#define SEC_ENG_SE_AES_0_INT_CLR_1T_MSK (((1U << SEC_ENG_SE_AES_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_AES_0_INT_CLR_1T_POS) -#define SEC_ENG_SE_AES_0_INT_CLR_1T_UMSK (~(((1U << SEC_ENG_SE_AES_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_AES_0_INT_CLR_1T_POS)) -#define SEC_ENG_SE_AES_0_INT_SET_1T SEC_ENG_SE_AES_0_INT_SET_1T -#define SEC_ENG_SE_AES_0_INT_SET_1T_POS (10U) -#define SEC_ENG_SE_AES_0_INT_SET_1T_LEN (1U) -#define SEC_ENG_SE_AES_0_INT_SET_1T_MSK (((1U << SEC_ENG_SE_AES_0_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_AES_0_INT_SET_1T_POS) -#define SEC_ENG_SE_AES_0_INT_SET_1T_UMSK (~(((1U << SEC_ENG_SE_AES_0_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_AES_0_INT_SET_1T_POS)) -#define SEC_ENG_SE_AES_0_INT_MASK SEC_ENG_SE_AES_0_INT_MASK -#define SEC_ENG_SE_AES_0_INT_MASK_POS (11U) -#define SEC_ENG_SE_AES_0_INT_MASK_LEN (1U) -#define SEC_ENG_SE_AES_0_INT_MASK_MSK (((1U << SEC_ENG_SE_AES_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_AES_0_INT_MASK_POS) -#define SEC_ENG_SE_AES_0_INT_MASK_UMSK (~(((1U << SEC_ENG_SE_AES_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_AES_0_INT_MASK_POS)) -#define SEC_ENG_SE_AES_0_BLOCK_MODE SEC_ENG_SE_AES_0_BLOCK_MODE -#define SEC_ENG_SE_AES_0_BLOCK_MODE_POS (12U) -#define SEC_ENG_SE_AES_0_BLOCK_MODE_LEN (2U) -#define SEC_ENG_SE_AES_0_BLOCK_MODE_MSK (((1U << SEC_ENG_SE_AES_0_BLOCK_MODE_LEN) - 1) << SEC_ENG_SE_AES_0_BLOCK_MODE_POS) -#define SEC_ENG_SE_AES_0_BLOCK_MODE_UMSK (~(((1U << SEC_ENG_SE_AES_0_BLOCK_MODE_LEN) - 1) << SEC_ENG_SE_AES_0_BLOCK_MODE_POS)) -#define SEC_ENG_SE_AES_0_IV_SEL SEC_ENG_SE_AES_0_IV_SEL -#define SEC_ENG_SE_AES_0_IV_SEL_POS (14U) -#define SEC_ENG_SE_AES_0_IV_SEL_LEN (1U) -#define SEC_ENG_SE_AES_0_IV_SEL_MSK (((1U << SEC_ENG_SE_AES_0_IV_SEL_LEN) - 1) << SEC_ENG_SE_AES_0_IV_SEL_POS) -#define SEC_ENG_SE_AES_0_IV_SEL_UMSK (~(((1U << SEC_ENG_SE_AES_0_IV_SEL_LEN) - 1) << SEC_ENG_SE_AES_0_IV_SEL_POS)) -#define SEC_ENG_SE_AES_0_LINK_MODE SEC_ENG_SE_AES_0_LINK_MODE -#define SEC_ENG_SE_AES_0_LINK_MODE_POS (15U) -#define SEC_ENG_SE_AES_0_LINK_MODE_LEN (1U) -#define SEC_ENG_SE_AES_0_LINK_MODE_MSK (((1U << SEC_ENG_SE_AES_0_LINK_MODE_LEN) - 1) << SEC_ENG_SE_AES_0_LINK_MODE_POS) -#define SEC_ENG_SE_AES_0_LINK_MODE_UMSK (~(((1U << SEC_ENG_SE_AES_0_LINK_MODE_LEN) - 1) << SEC_ENG_SE_AES_0_LINK_MODE_POS)) -#define SEC_ENG_SE_AES_0_MSG_LEN SEC_ENG_SE_AES_0_MSG_LEN -#define SEC_ENG_SE_AES_0_MSG_LEN_POS (16U) -#define SEC_ENG_SE_AES_0_MSG_LEN_LEN (16U) -#define SEC_ENG_SE_AES_0_MSG_LEN_MSK (((1U << SEC_ENG_SE_AES_0_MSG_LEN_LEN) - 1) << SEC_ENG_SE_AES_0_MSG_LEN_POS) -#define SEC_ENG_SE_AES_0_MSG_LEN_UMSK (~(((1U << SEC_ENG_SE_AES_0_MSG_LEN_LEN) - 1) << SEC_ENG_SE_AES_0_MSG_LEN_POS)) - -/* 0x104 : se_aes_0_msa */ -#define SEC_ENG_SE_AES_0_MSA_OFFSET (0x104) -#define SEC_ENG_SE_AES_0_MSA SEC_ENG_SE_AES_0_MSA -#define SEC_ENG_SE_AES_0_MSA_POS (0U) -#define SEC_ENG_SE_AES_0_MSA_LEN (32U) -#define SEC_ENG_SE_AES_0_MSA_MSK (((1U << SEC_ENG_SE_AES_0_MSA_LEN) - 1) << SEC_ENG_SE_AES_0_MSA_POS) -#define SEC_ENG_SE_AES_0_MSA_UMSK (~(((1U << SEC_ENG_SE_AES_0_MSA_LEN) - 1) << SEC_ENG_SE_AES_0_MSA_POS)) - -/* 0x108 : se_aes_0_mda */ -#define SEC_ENG_SE_AES_0_MDA_OFFSET (0x108) -#define SEC_ENG_SE_AES_0_MDA SEC_ENG_SE_AES_0_MDA -#define SEC_ENG_SE_AES_0_MDA_POS (0U) -#define SEC_ENG_SE_AES_0_MDA_LEN (32U) -#define SEC_ENG_SE_AES_0_MDA_MSK (((1U << SEC_ENG_SE_AES_0_MDA_LEN) - 1) << SEC_ENG_SE_AES_0_MDA_POS) -#define SEC_ENG_SE_AES_0_MDA_UMSK (~(((1U << SEC_ENG_SE_AES_0_MDA_LEN) - 1) << SEC_ENG_SE_AES_0_MDA_POS)) - -/* 0x10C : se_aes_0_status */ -#define SEC_ENG_SE_AES_0_STATUS_OFFSET (0x10C) -#define SEC_ENG_SE_AES_0_STATUS SEC_ENG_SE_AES_0_STATUS -#define SEC_ENG_SE_AES_0_STATUS_POS (0U) -#define SEC_ENG_SE_AES_0_STATUS_LEN (32U) -#define SEC_ENG_SE_AES_0_STATUS_MSK (((1U << SEC_ENG_SE_AES_0_STATUS_LEN) - 1) << SEC_ENG_SE_AES_0_STATUS_POS) -#define SEC_ENG_SE_AES_0_STATUS_UMSK (~(((1U << SEC_ENG_SE_AES_0_STATUS_LEN) - 1) << SEC_ENG_SE_AES_0_STATUS_POS)) - -/* 0x110 : se_aes_0_iv_0 */ -#define SEC_ENG_SE_AES_0_IV_0_OFFSET (0x110) -#define SEC_ENG_SE_AES_0_IV_0 SEC_ENG_SE_AES_0_IV_0 -#define SEC_ENG_SE_AES_0_IV_0_POS (0U) -#define SEC_ENG_SE_AES_0_IV_0_LEN (32U) -#define SEC_ENG_SE_AES_0_IV_0_MSK (((1U << SEC_ENG_SE_AES_0_IV_0_LEN) - 1) << SEC_ENG_SE_AES_0_IV_0_POS) -#define SEC_ENG_SE_AES_0_IV_0_UMSK (~(((1U << SEC_ENG_SE_AES_0_IV_0_LEN) - 1) << SEC_ENG_SE_AES_0_IV_0_POS)) - -/* 0x114 : se_aes_0_iv_1 */ -#define SEC_ENG_SE_AES_0_IV_1_OFFSET (0x114) -#define SEC_ENG_SE_AES_0_IV_1 SEC_ENG_SE_AES_0_IV_1 -#define SEC_ENG_SE_AES_0_IV_1_POS (0U) -#define SEC_ENG_SE_AES_0_IV_1_LEN (32U) -#define SEC_ENG_SE_AES_0_IV_1_MSK (((1U << SEC_ENG_SE_AES_0_IV_1_LEN) - 1) << SEC_ENG_SE_AES_0_IV_1_POS) -#define SEC_ENG_SE_AES_0_IV_1_UMSK (~(((1U << SEC_ENG_SE_AES_0_IV_1_LEN) - 1) << SEC_ENG_SE_AES_0_IV_1_POS)) - -/* 0x118 : se_aes_0_iv_2 */ -#define SEC_ENG_SE_AES_0_IV_2_OFFSET (0x118) -#define SEC_ENG_SE_AES_0_IV_2 SEC_ENG_SE_AES_0_IV_2 -#define SEC_ENG_SE_AES_0_IV_2_POS (0U) -#define SEC_ENG_SE_AES_0_IV_2_LEN (32U) -#define SEC_ENG_SE_AES_0_IV_2_MSK (((1U << SEC_ENG_SE_AES_0_IV_2_LEN) - 1) << SEC_ENG_SE_AES_0_IV_2_POS) -#define SEC_ENG_SE_AES_0_IV_2_UMSK (~(((1U << SEC_ENG_SE_AES_0_IV_2_LEN) - 1) << SEC_ENG_SE_AES_0_IV_2_POS)) - -/* 0x11C : se_aes_0_iv_3 */ -#define SEC_ENG_SE_AES_0_IV_3_OFFSET (0x11C) -#define SEC_ENG_SE_AES_0_IV_3 SEC_ENG_SE_AES_0_IV_3 -#define SEC_ENG_SE_AES_0_IV_3_POS (0U) -#define SEC_ENG_SE_AES_0_IV_3_LEN (32U) -#define SEC_ENG_SE_AES_0_IV_3_MSK (((1U << SEC_ENG_SE_AES_0_IV_3_LEN) - 1) << SEC_ENG_SE_AES_0_IV_3_POS) -#define SEC_ENG_SE_AES_0_IV_3_UMSK (~(((1U << SEC_ENG_SE_AES_0_IV_3_LEN) - 1) << SEC_ENG_SE_AES_0_IV_3_POS)) - -/* 0x120 : se_aes_0_key_0 */ -#define SEC_ENG_SE_AES_0_KEY_0_OFFSET (0x120) -#define SEC_ENG_SE_AES_0_KEY_0 SEC_ENG_SE_AES_0_KEY_0 -#define SEC_ENG_SE_AES_0_KEY_0_POS (0U) -#define SEC_ENG_SE_AES_0_KEY_0_LEN (32U) -#define SEC_ENG_SE_AES_0_KEY_0_MSK (((1U << SEC_ENG_SE_AES_0_KEY_0_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_0_POS) -#define SEC_ENG_SE_AES_0_KEY_0_UMSK (~(((1U << SEC_ENG_SE_AES_0_KEY_0_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_0_POS)) - -/* 0x124 : se_aes_0_key_1 */ -#define SEC_ENG_SE_AES_0_KEY_1_OFFSET (0x124) -#define SEC_ENG_SE_AES_0_KEY_1 SEC_ENG_SE_AES_0_KEY_1 -#define SEC_ENG_SE_AES_0_KEY_1_POS (0U) -#define SEC_ENG_SE_AES_0_KEY_1_LEN (32U) -#define SEC_ENG_SE_AES_0_KEY_1_MSK (((1U << SEC_ENG_SE_AES_0_KEY_1_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_1_POS) -#define SEC_ENG_SE_AES_0_KEY_1_UMSK (~(((1U << SEC_ENG_SE_AES_0_KEY_1_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_1_POS)) - -/* 0x128 : se_aes_0_key_2 */ -#define SEC_ENG_SE_AES_0_KEY_2_OFFSET (0x128) -#define SEC_ENG_SE_AES_0_KEY_2 SEC_ENG_SE_AES_0_KEY_2 -#define SEC_ENG_SE_AES_0_KEY_2_POS (0U) -#define SEC_ENG_SE_AES_0_KEY_2_LEN (32U) -#define SEC_ENG_SE_AES_0_KEY_2_MSK (((1U << SEC_ENG_SE_AES_0_KEY_2_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_2_POS) -#define SEC_ENG_SE_AES_0_KEY_2_UMSK (~(((1U << SEC_ENG_SE_AES_0_KEY_2_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_2_POS)) - -/* 0x12C : se_aes_0_key_3 */ -#define SEC_ENG_SE_AES_0_KEY_3_OFFSET (0x12C) -#define SEC_ENG_SE_AES_0_KEY_3 SEC_ENG_SE_AES_0_KEY_3 -#define SEC_ENG_SE_AES_0_KEY_3_POS (0U) -#define SEC_ENG_SE_AES_0_KEY_3_LEN (32U) -#define SEC_ENG_SE_AES_0_KEY_3_MSK (((1U << SEC_ENG_SE_AES_0_KEY_3_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_3_POS) -#define SEC_ENG_SE_AES_0_KEY_3_UMSK (~(((1U << SEC_ENG_SE_AES_0_KEY_3_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_3_POS)) - -/* 0x130 : se_aes_0_key_4 */ -#define SEC_ENG_SE_AES_0_KEY_4_OFFSET (0x130) -#define SEC_ENG_SE_AES_0_KEY_4 SEC_ENG_SE_AES_0_KEY_4 -#define SEC_ENG_SE_AES_0_KEY_4_POS (0U) -#define SEC_ENG_SE_AES_0_KEY_4_LEN (32U) -#define SEC_ENG_SE_AES_0_KEY_4_MSK (((1U << SEC_ENG_SE_AES_0_KEY_4_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_4_POS) -#define SEC_ENG_SE_AES_0_KEY_4_UMSK (~(((1U << SEC_ENG_SE_AES_0_KEY_4_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_4_POS)) - -/* 0x134 : se_aes_0_key_5 */ -#define SEC_ENG_SE_AES_0_KEY_5_OFFSET (0x134) -#define SEC_ENG_SE_AES_0_KEY_5 SEC_ENG_SE_AES_0_KEY_5 -#define SEC_ENG_SE_AES_0_KEY_5_POS (0U) -#define SEC_ENG_SE_AES_0_KEY_5_LEN (32U) -#define SEC_ENG_SE_AES_0_KEY_5_MSK (((1U << SEC_ENG_SE_AES_0_KEY_5_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_5_POS) -#define SEC_ENG_SE_AES_0_KEY_5_UMSK (~(((1U << SEC_ENG_SE_AES_0_KEY_5_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_5_POS)) - -/* 0x138 : se_aes_0_key_6 */ -#define SEC_ENG_SE_AES_0_KEY_6_OFFSET (0x138) -#define SEC_ENG_SE_AES_0_KEY_6 SEC_ENG_SE_AES_0_KEY_6 -#define SEC_ENG_SE_AES_0_KEY_6_POS (0U) -#define SEC_ENG_SE_AES_0_KEY_6_LEN (32U) -#define SEC_ENG_SE_AES_0_KEY_6_MSK (((1U << SEC_ENG_SE_AES_0_KEY_6_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_6_POS) -#define SEC_ENG_SE_AES_0_KEY_6_UMSK (~(((1U << SEC_ENG_SE_AES_0_KEY_6_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_6_POS)) - -/* 0x13C : se_aes_0_key_7 */ -#define SEC_ENG_SE_AES_0_KEY_7_OFFSET (0x13C) -#define SEC_ENG_SE_AES_0_KEY_7 SEC_ENG_SE_AES_0_KEY_7 -#define SEC_ENG_SE_AES_0_KEY_7_POS (0U) -#define SEC_ENG_SE_AES_0_KEY_7_LEN (32U) -#define SEC_ENG_SE_AES_0_KEY_7_MSK (((1U << SEC_ENG_SE_AES_0_KEY_7_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_7_POS) -#define SEC_ENG_SE_AES_0_KEY_7_UMSK (~(((1U << SEC_ENG_SE_AES_0_KEY_7_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_7_POS)) - -/* 0x140 : se_aes_0_key_sel */ -#define SEC_ENG_SE_AES_0_KEY_SEL_OFFSET (0x140) -#define SEC_ENG_SE_AES_0_KEY_SEL SEC_ENG_SE_AES_0_KEY_SEL -#define SEC_ENG_SE_AES_0_KEY_SEL_POS (0U) -#define SEC_ENG_SE_AES_0_KEY_SEL_LEN (2U) -#define SEC_ENG_SE_AES_0_KEY_SEL_MSK (((1U << SEC_ENG_SE_AES_0_KEY_SEL_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_SEL_POS) -#define SEC_ENG_SE_AES_0_KEY_SEL_UMSK (~(((1U << SEC_ENG_SE_AES_0_KEY_SEL_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_SEL_POS)) - -/* 0x144 : se_aes_1_key_sel */ -#define SEC_ENG_SE_AES_1_KEY_SEL_OFFSET (0x144) -#define SEC_ENG_SE_AES_1_KEY_SEL SEC_ENG_SE_AES_1_KEY_SEL -#define SEC_ENG_SE_AES_1_KEY_SEL_POS (0U) -#define SEC_ENG_SE_AES_1_KEY_SEL_LEN (2U) -#define SEC_ENG_SE_AES_1_KEY_SEL_MSK (((1U << SEC_ENG_SE_AES_1_KEY_SEL_LEN) - 1) << SEC_ENG_SE_AES_1_KEY_SEL_POS) -#define SEC_ENG_SE_AES_1_KEY_SEL_UMSK (~(((1U << SEC_ENG_SE_AES_1_KEY_SEL_LEN) - 1) << SEC_ENG_SE_AES_1_KEY_SEL_POS)) - -/* 0x148 : se_aes_0_endian */ -#define SEC_ENG_SE_AES_0_ENDIAN_OFFSET (0x148) -#define SEC_ENG_SE_AES_0_DOUT_ENDIAN SEC_ENG_SE_AES_0_DOUT_ENDIAN -#define SEC_ENG_SE_AES_0_DOUT_ENDIAN_POS (0U) -#define SEC_ENG_SE_AES_0_DOUT_ENDIAN_LEN (1U) -#define SEC_ENG_SE_AES_0_DOUT_ENDIAN_MSK (((1U << SEC_ENG_SE_AES_0_DOUT_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_DOUT_ENDIAN_POS) -#define SEC_ENG_SE_AES_0_DOUT_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_AES_0_DOUT_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_DOUT_ENDIAN_POS)) -#define SEC_ENG_SE_AES_0_DIN_ENDIAN SEC_ENG_SE_AES_0_DIN_ENDIAN -#define SEC_ENG_SE_AES_0_DIN_ENDIAN_POS (1U) -#define SEC_ENG_SE_AES_0_DIN_ENDIAN_LEN (1U) -#define SEC_ENG_SE_AES_0_DIN_ENDIAN_MSK (((1U << SEC_ENG_SE_AES_0_DIN_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_DIN_ENDIAN_POS) -#define SEC_ENG_SE_AES_0_DIN_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_AES_0_DIN_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_DIN_ENDIAN_POS)) -#define SEC_ENG_SE_AES_0_KEY_ENDIAN SEC_ENG_SE_AES_0_KEY_ENDIAN -#define SEC_ENG_SE_AES_0_KEY_ENDIAN_POS (2U) -#define SEC_ENG_SE_AES_0_KEY_ENDIAN_LEN (1U) -#define SEC_ENG_SE_AES_0_KEY_ENDIAN_MSK (((1U << SEC_ENG_SE_AES_0_KEY_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_ENDIAN_POS) -#define SEC_ENG_SE_AES_0_KEY_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_AES_0_KEY_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_ENDIAN_POS)) -#define SEC_ENG_SE_AES_0_IV_ENDIAN SEC_ENG_SE_AES_0_IV_ENDIAN -#define SEC_ENG_SE_AES_0_IV_ENDIAN_POS (3U) -#define SEC_ENG_SE_AES_0_IV_ENDIAN_LEN (1U) -#define SEC_ENG_SE_AES_0_IV_ENDIAN_MSK (((1U << SEC_ENG_SE_AES_0_IV_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_IV_ENDIAN_POS) -#define SEC_ENG_SE_AES_0_IV_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_AES_0_IV_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_IV_ENDIAN_POS)) -#define SEC_ENG_SE_AES_0_TWK_ENDIAN SEC_ENG_SE_AES_0_TWK_ENDIAN -#define SEC_ENG_SE_AES_0_TWK_ENDIAN_POS (4U) -#define SEC_ENG_SE_AES_0_TWK_ENDIAN_LEN (1U) -#define SEC_ENG_SE_AES_0_TWK_ENDIAN_MSK (((1U << SEC_ENG_SE_AES_0_TWK_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_TWK_ENDIAN_POS) -#define SEC_ENG_SE_AES_0_TWK_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_AES_0_TWK_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_TWK_ENDIAN_POS)) -#define SEC_ENG_SE_AES_0_CTR_LEN SEC_ENG_SE_AES_0_CTR_LEN -#define SEC_ENG_SE_AES_0_CTR_LEN_POS (30U) -#define SEC_ENG_SE_AES_0_CTR_LEN_LEN (2U) -#define SEC_ENG_SE_AES_0_CTR_LEN_MSK (((1U << SEC_ENG_SE_AES_0_CTR_LEN_LEN) - 1) << SEC_ENG_SE_AES_0_CTR_LEN_POS) -#define SEC_ENG_SE_AES_0_CTR_LEN_UMSK (~(((1U << SEC_ENG_SE_AES_0_CTR_LEN_LEN) - 1) << SEC_ENG_SE_AES_0_CTR_LEN_POS)) - -/* 0x14C : se_aes_sboot */ -#define SEC_ENG_SE_AES_0_SBOOT_OFFSET (0x14C) -#define SEC_ENG_SE_AES_0_SBOOT_KEY_SEL SEC_ENG_SE_AES_0_SBOOT_KEY_SEL -#define SEC_ENG_SE_AES_0_SBOOT_KEY_SEL_POS (0U) -#define SEC_ENG_SE_AES_0_SBOOT_KEY_SEL_LEN (1U) -#define SEC_ENG_SE_AES_0_SBOOT_KEY_SEL_MSK (((1U << SEC_ENG_SE_AES_0_SBOOT_KEY_SEL_LEN) - 1) << SEC_ENG_SE_AES_0_SBOOT_KEY_SEL_POS) -#define SEC_ENG_SE_AES_0_SBOOT_KEY_SEL_UMSK (~(((1U << SEC_ENG_SE_AES_0_SBOOT_KEY_SEL_LEN) - 1) << SEC_ENG_SE_AES_0_SBOOT_KEY_SEL_POS)) -#define SEC_ENG_SE_AES_0_XTS_MODE SEC_ENG_SE_AES_0_XTS_MODE -#define SEC_ENG_SE_AES_0_XTS_MODE_POS (15U) -#define SEC_ENG_SE_AES_0_XTS_MODE_LEN (1U) -#define SEC_ENG_SE_AES_0_XTS_MODE_MSK (((1U << SEC_ENG_SE_AES_0_XTS_MODE_LEN) - 1) << SEC_ENG_SE_AES_0_XTS_MODE_POS) -#define SEC_ENG_SE_AES_0_XTS_MODE_UMSK (~(((1U << SEC_ENG_SE_AES_0_XTS_MODE_LEN) - 1) << SEC_ENG_SE_AES_0_XTS_MODE_POS)) -#define SEC_ENG_SE_AES_0_UNI_LEN SEC_ENG_SE_AES_0_UNI_LEN -#define SEC_ENG_SE_AES_0_UNI_LEN_POS (16U) -#define SEC_ENG_SE_AES_0_UNI_LEN_LEN (16U) -#define SEC_ENG_SE_AES_0_UNI_LEN_MSK (((1U << SEC_ENG_SE_AES_0_UNI_LEN_LEN) - 1) << SEC_ENG_SE_AES_0_UNI_LEN_POS) -#define SEC_ENG_SE_AES_0_UNI_LEN_UMSK (~(((1U << SEC_ENG_SE_AES_0_UNI_LEN_LEN) - 1) << SEC_ENG_SE_AES_0_UNI_LEN_POS)) - -/* 0x150 : se_aes_0_link */ -#define SEC_ENG_SE_AES_0_LINK_OFFSET (0x150) -#define SEC_ENG_SE_AES_0_LCA SEC_ENG_SE_AES_0_LCA -#define SEC_ENG_SE_AES_0_LCA_POS (0U) -#define SEC_ENG_SE_AES_0_LCA_LEN (32U) -#define SEC_ENG_SE_AES_0_LCA_MSK (((1U << SEC_ENG_SE_AES_0_LCA_LEN) - 1) << SEC_ENG_SE_AES_0_LCA_POS) -#define SEC_ENG_SE_AES_0_LCA_UMSK (~(((1U << SEC_ENG_SE_AES_0_LCA_LEN) - 1) << SEC_ENG_SE_AES_0_LCA_POS)) - -/* 0x1FC : se_aes_0_ctrl_prot */ -#define SEC_ENG_SE_AES_0_CTRL_PROT_OFFSET (0x1FC) -#define SEC_ENG_SE_AES_ID0_EN SEC_ENG_SE_AES_ID0_EN -#define SEC_ENG_SE_AES_ID0_EN_POS (1U) -#define SEC_ENG_SE_AES_ID0_EN_LEN (1U) -#define SEC_ENG_SE_AES_ID0_EN_MSK (((1U << SEC_ENG_SE_AES_ID0_EN_LEN) - 1) << SEC_ENG_SE_AES_ID0_EN_POS) -#define SEC_ENG_SE_AES_ID0_EN_UMSK (~(((1U << SEC_ENG_SE_AES_ID0_EN_LEN) - 1) << SEC_ENG_SE_AES_ID0_EN_POS)) -#define SEC_ENG_SE_AES_ID1_EN SEC_ENG_SE_AES_ID1_EN -#define SEC_ENG_SE_AES_ID1_EN_POS (2U) -#define SEC_ENG_SE_AES_ID1_EN_LEN (1U) -#define SEC_ENG_SE_AES_ID1_EN_MSK (((1U << SEC_ENG_SE_AES_ID1_EN_LEN) - 1) << SEC_ENG_SE_AES_ID1_EN_POS) -#define SEC_ENG_SE_AES_ID1_EN_UMSK (~(((1U << SEC_ENG_SE_AES_ID1_EN_LEN) - 1) << SEC_ENG_SE_AES_ID1_EN_POS)) - -/* 0x200 : se_trng_0_ctrl_0 */ -#define SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET (0x200) -#define SEC_ENG_SE_TRNG_0_BUSY SEC_ENG_SE_TRNG_0_BUSY -#define SEC_ENG_SE_TRNG_0_BUSY_POS (0U) -#define SEC_ENG_SE_TRNG_0_BUSY_LEN (1U) -#define SEC_ENG_SE_TRNG_0_BUSY_MSK (((1U << SEC_ENG_SE_TRNG_0_BUSY_LEN) - 1) << SEC_ENG_SE_TRNG_0_BUSY_POS) -#define SEC_ENG_SE_TRNG_0_BUSY_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_BUSY_LEN) - 1) << SEC_ENG_SE_TRNG_0_BUSY_POS)) -#define SEC_ENG_SE_TRNG_0_TRIG_1T SEC_ENG_SE_TRNG_0_TRIG_1T -#define SEC_ENG_SE_TRNG_0_TRIG_1T_POS (1U) -#define SEC_ENG_SE_TRNG_0_TRIG_1T_LEN (1U) -#define SEC_ENG_SE_TRNG_0_TRIG_1T_MSK (((1U << SEC_ENG_SE_TRNG_0_TRIG_1T_LEN) - 1) << SEC_ENG_SE_TRNG_0_TRIG_1T_POS) -#define SEC_ENG_SE_TRNG_0_TRIG_1T_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_TRIG_1T_LEN) - 1) << SEC_ENG_SE_TRNG_0_TRIG_1T_POS)) -#define SEC_ENG_SE_TRNG_0_EN SEC_ENG_SE_TRNG_0_EN -#define SEC_ENG_SE_TRNG_0_EN_POS (2U) -#define SEC_ENG_SE_TRNG_0_EN_LEN (1U) -#define SEC_ENG_SE_TRNG_0_EN_MSK (((1U << SEC_ENG_SE_TRNG_0_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_EN_POS) -#define SEC_ENG_SE_TRNG_0_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_EN_POS)) -#define SEC_ENG_SE_TRNG_0_DOUT_CLR_1T SEC_ENG_SE_TRNG_0_DOUT_CLR_1T -#define SEC_ENG_SE_TRNG_0_DOUT_CLR_1T_POS (3U) -#define SEC_ENG_SE_TRNG_0_DOUT_CLR_1T_LEN (1U) -#define SEC_ENG_SE_TRNG_0_DOUT_CLR_1T_MSK (((1U << SEC_ENG_SE_TRNG_0_DOUT_CLR_1T_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_CLR_1T_POS) -#define SEC_ENG_SE_TRNG_0_DOUT_CLR_1T_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_CLR_1T_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_CLR_1T_POS)) -#define SEC_ENG_SE_TRNG_0_HT_ERROR SEC_ENG_SE_TRNG_0_HT_ERROR -#define SEC_ENG_SE_TRNG_0_HT_ERROR_POS (4U) -#define SEC_ENG_SE_TRNG_0_HT_ERROR_LEN (1U) -#define SEC_ENG_SE_TRNG_0_HT_ERROR_MSK (((1U << SEC_ENG_SE_TRNG_0_HT_ERROR_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_ERROR_POS) -#define SEC_ENG_SE_TRNG_0_HT_ERROR_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_HT_ERROR_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_ERROR_POS)) -#define SEC_ENG_SE_TRNG_0_INT SEC_ENG_SE_TRNG_0_INT -#define SEC_ENG_SE_TRNG_0_INT_POS (8U) -#define SEC_ENG_SE_TRNG_0_INT_LEN (1U) -#define SEC_ENG_SE_TRNG_0_INT_MSK (((1U << SEC_ENG_SE_TRNG_0_INT_LEN) - 1) << SEC_ENG_SE_TRNG_0_INT_POS) -#define SEC_ENG_SE_TRNG_0_INT_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_INT_LEN) - 1) << SEC_ENG_SE_TRNG_0_INT_POS)) -#define SEC_ENG_SE_TRNG_0_INT_CLR_1T SEC_ENG_SE_TRNG_0_INT_CLR_1T -#define SEC_ENG_SE_TRNG_0_INT_CLR_1T_POS (9U) -#define SEC_ENG_SE_TRNG_0_INT_CLR_1T_LEN (1U) -#define SEC_ENG_SE_TRNG_0_INT_CLR_1T_MSK (((1U << SEC_ENG_SE_TRNG_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_TRNG_0_INT_CLR_1T_POS) -#define SEC_ENG_SE_TRNG_0_INT_CLR_1T_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_TRNG_0_INT_CLR_1T_POS)) -#define SEC_ENG_SE_TRNG_0_INT_SET_1T SEC_ENG_SE_TRNG_0_INT_SET_1T -#define SEC_ENG_SE_TRNG_0_INT_SET_1T_POS (10U) -#define SEC_ENG_SE_TRNG_0_INT_SET_1T_LEN (1U) -#define SEC_ENG_SE_TRNG_0_INT_SET_1T_MSK (((1U << SEC_ENG_SE_TRNG_0_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_TRNG_0_INT_SET_1T_POS) -#define SEC_ENG_SE_TRNG_0_INT_SET_1T_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_TRNG_0_INT_SET_1T_POS)) -#define SEC_ENG_SE_TRNG_0_INT_MASK SEC_ENG_SE_TRNG_0_INT_MASK -#define SEC_ENG_SE_TRNG_0_INT_MASK_POS (11U) -#define SEC_ENG_SE_TRNG_0_INT_MASK_LEN (1U) -#define SEC_ENG_SE_TRNG_0_INT_MASK_MSK (((1U << SEC_ENG_SE_TRNG_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_TRNG_0_INT_MASK_POS) -#define SEC_ENG_SE_TRNG_0_INT_MASK_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_TRNG_0_INT_MASK_POS)) -#define SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL -#define SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL_POS (13U) -#define SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL_LEN (1U) -#define SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL_MSK (((1U << SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL_LEN) - 1) << SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL_POS) -#define SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL_LEN) - 1) << SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL_POS)) -#define SEC_ENG_SE_TRNG_0_MANUAL_RESEED SEC_ENG_SE_TRNG_0_MANUAL_RESEED -#define SEC_ENG_SE_TRNG_0_MANUAL_RESEED_POS (14U) -#define SEC_ENG_SE_TRNG_0_MANUAL_RESEED_LEN (1U) -#define SEC_ENG_SE_TRNG_0_MANUAL_RESEED_MSK (((1U << SEC_ENG_SE_TRNG_0_MANUAL_RESEED_LEN) - 1) << SEC_ENG_SE_TRNG_0_MANUAL_RESEED_POS) -#define SEC_ENG_SE_TRNG_0_MANUAL_RESEED_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_MANUAL_RESEED_LEN) - 1) << SEC_ENG_SE_TRNG_0_MANUAL_RESEED_POS)) -#define SEC_ENG_SE_TRNG_0_MANUAL_EN SEC_ENG_SE_TRNG_0_MANUAL_EN -#define SEC_ENG_SE_TRNG_0_MANUAL_EN_POS (15U) -#define SEC_ENG_SE_TRNG_0_MANUAL_EN_LEN (1U) -#define SEC_ENG_SE_TRNG_0_MANUAL_EN_MSK (((1U << SEC_ENG_SE_TRNG_0_MANUAL_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_MANUAL_EN_POS) -#define SEC_ENG_SE_TRNG_0_MANUAL_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_MANUAL_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_MANUAL_EN_POS)) - -/* 0x204 : se_trng_0_status */ -#define SEC_ENG_SE_TRNG_0_STATUS_OFFSET (0x204) -#define SEC_ENG_SE_TRNG_0_STATUS SEC_ENG_SE_TRNG_0_STATUS -#define SEC_ENG_SE_TRNG_0_STATUS_POS (0U) -#define SEC_ENG_SE_TRNG_0_STATUS_LEN (32U) -#define SEC_ENG_SE_TRNG_0_STATUS_MSK (((1U << SEC_ENG_SE_TRNG_0_STATUS_LEN) - 1) << SEC_ENG_SE_TRNG_0_STATUS_POS) -#define SEC_ENG_SE_TRNG_0_STATUS_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_STATUS_LEN) - 1) << SEC_ENG_SE_TRNG_0_STATUS_POS)) - -/* 0x208 : se_trng_0_dout_0 */ -#define SEC_ENG_SE_TRNG_0_DOUT_0_OFFSET (0x208) -#define SEC_ENG_SE_TRNG_0_DOUT_0 SEC_ENG_SE_TRNG_0_DOUT_0 -#define SEC_ENG_SE_TRNG_0_DOUT_0_POS (0U) -#define SEC_ENG_SE_TRNG_0_DOUT_0_LEN (32U) -#define SEC_ENG_SE_TRNG_0_DOUT_0_MSK (((1U << SEC_ENG_SE_TRNG_0_DOUT_0_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_0_POS) -#define SEC_ENG_SE_TRNG_0_DOUT_0_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_0_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_0_POS)) - -/* 0x20C : se_trng_0_dout_1 */ -#define SEC_ENG_SE_TRNG_0_DOUT_1_OFFSET (0x20C) -#define SEC_ENG_SE_TRNG_0_DOUT_1 SEC_ENG_SE_TRNG_0_DOUT_1 -#define SEC_ENG_SE_TRNG_0_DOUT_1_POS (0U) -#define SEC_ENG_SE_TRNG_0_DOUT_1_LEN (32U) -#define SEC_ENG_SE_TRNG_0_DOUT_1_MSK (((1U << SEC_ENG_SE_TRNG_0_DOUT_1_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_1_POS) -#define SEC_ENG_SE_TRNG_0_DOUT_1_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_1_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_1_POS)) - -/* 0x210 : se_trng_0_dout_2 */ -#define SEC_ENG_SE_TRNG_0_DOUT_2_OFFSET (0x210) -#define SEC_ENG_SE_TRNG_0_DOUT_2 SEC_ENG_SE_TRNG_0_DOUT_2 -#define SEC_ENG_SE_TRNG_0_DOUT_2_POS (0U) -#define SEC_ENG_SE_TRNG_0_DOUT_2_LEN (32U) -#define SEC_ENG_SE_TRNG_0_DOUT_2_MSK (((1U << SEC_ENG_SE_TRNG_0_DOUT_2_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_2_POS) -#define SEC_ENG_SE_TRNG_0_DOUT_2_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_2_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_2_POS)) - -/* 0x214 : se_trng_0_dout_3 */ -#define SEC_ENG_SE_TRNG_0_DOUT_3_OFFSET (0x214) -#define SEC_ENG_SE_TRNG_0_DOUT_3 SEC_ENG_SE_TRNG_0_DOUT_3 -#define SEC_ENG_SE_TRNG_0_DOUT_3_POS (0U) -#define SEC_ENG_SE_TRNG_0_DOUT_3_LEN (32U) -#define SEC_ENG_SE_TRNG_0_DOUT_3_MSK (((1U << SEC_ENG_SE_TRNG_0_DOUT_3_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_3_POS) -#define SEC_ENG_SE_TRNG_0_DOUT_3_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_3_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_3_POS)) - -/* 0x218 : se_trng_0_dout_4 */ -#define SEC_ENG_SE_TRNG_0_DOUT_4_OFFSET (0x218) -#define SEC_ENG_SE_TRNG_0_DOUT_4 SEC_ENG_SE_TRNG_0_DOUT_4 -#define SEC_ENG_SE_TRNG_0_DOUT_4_POS (0U) -#define SEC_ENG_SE_TRNG_0_DOUT_4_LEN (32U) -#define SEC_ENG_SE_TRNG_0_DOUT_4_MSK (((1U << SEC_ENG_SE_TRNG_0_DOUT_4_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_4_POS) -#define SEC_ENG_SE_TRNG_0_DOUT_4_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_4_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_4_POS)) - -/* 0x21C : se_trng_0_dout_5 */ -#define SEC_ENG_SE_TRNG_0_DOUT_5_OFFSET (0x21C) -#define SEC_ENG_SE_TRNG_0_DOUT_5 SEC_ENG_SE_TRNG_0_DOUT_5 -#define SEC_ENG_SE_TRNG_0_DOUT_5_POS (0U) -#define SEC_ENG_SE_TRNG_0_DOUT_5_LEN (32U) -#define SEC_ENG_SE_TRNG_0_DOUT_5_MSK (((1U << SEC_ENG_SE_TRNG_0_DOUT_5_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_5_POS) -#define SEC_ENG_SE_TRNG_0_DOUT_5_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_5_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_5_POS)) - -/* 0x220 : se_trng_0_dout_6 */ -#define SEC_ENG_SE_TRNG_0_DOUT_6_OFFSET (0x220) -#define SEC_ENG_SE_TRNG_0_DOUT_6 SEC_ENG_SE_TRNG_0_DOUT_6 -#define SEC_ENG_SE_TRNG_0_DOUT_6_POS (0U) -#define SEC_ENG_SE_TRNG_0_DOUT_6_LEN (32U) -#define SEC_ENG_SE_TRNG_0_DOUT_6_MSK (((1U << SEC_ENG_SE_TRNG_0_DOUT_6_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_6_POS) -#define SEC_ENG_SE_TRNG_0_DOUT_6_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_6_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_6_POS)) - -/* 0x224 : se_trng_0_dout_7 */ -#define SEC_ENG_SE_TRNG_0_DOUT_7_OFFSET (0x224) -#define SEC_ENG_SE_TRNG_0_DOUT_7 SEC_ENG_SE_TRNG_0_DOUT_7 -#define SEC_ENG_SE_TRNG_0_DOUT_7_POS (0U) -#define SEC_ENG_SE_TRNG_0_DOUT_7_LEN (32U) -#define SEC_ENG_SE_TRNG_0_DOUT_7_MSK (((1U << SEC_ENG_SE_TRNG_0_DOUT_7_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_7_POS) -#define SEC_ENG_SE_TRNG_0_DOUT_7_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_7_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_7_POS)) - -/* 0x228 : se_trng_0_test */ -#define SEC_ENG_SE_TRNG_0_TEST_OFFSET (0x228) -#define SEC_ENG_SE_TRNG_0_TEST_EN SEC_ENG_SE_TRNG_0_TEST_EN -#define SEC_ENG_SE_TRNG_0_TEST_EN_POS (0U) -#define SEC_ENG_SE_TRNG_0_TEST_EN_LEN (1U) -#define SEC_ENG_SE_TRNG_0_TEST_EN_MSK (((1U << SEC_ENG_SE_TRNG_0_TEST_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_EN_POS) -#define SEC_ENG_SE_TRNG_0_TEST_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_TEST_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_EN_POS)) -#define SEC_ENG_SE_TRNG_0_CP_TEST_EN SEC_ENG_SE_TRNG_0_CP_TEST_EN -#define SEC_ENG_SE_TRNG_0_CP_TEST_EN_POS (1U) -#define SEC_ENG_SE_TRNG_0_CP_TEST_EN_LEN (1U) -#define SEC_ENG_SE_TRNG_0_CP_TEST_EN_MSK (((1U << SEC_ENG_SE_TRNG_0_CP_TEST_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_CP_TEST_EN_POS) -#define SEC_ENG_SE_TRNG_0_CP_TEST_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_CP_TEST_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_CP_TEST_EN_POS)) -#define SEC_ENG_SE_TRNG_0_CP_BYPASS SEC_ENG_SE_TRNG_0_CP_BYPASS -#define SEC_ENG_SE_TRNG_0_CP_BYPASS_POS (2U) -#define SEC_ENG_SE_TRNG_0_CP_BYPASS_LEN (1U) -#define SEC_ENG_SE_TRNG_0_CP_BYPASS_MSK (((1U << SEC_ENG_SE_TRNG_0_CP_BYPASS_LEN) - 1) << SEC_ENG_SE_TRNG_0_CP_BYPASS_POS) -#define SEC_ENG_SE_TRNG_0_CP_BYPASS_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_CP_BYPASS_LEN) - 1) << SEC_ENG_SE_TRNG_0_CP_BYPASS_POS)) -#define SEC_ENG_SE_TRNG_0_HT_DIS SEC_ENG_SE_TRNG_0_HT_DIS -#define SEC_ENG_SE_TRNG_0_HT_DIS_POS (3U) -#define SEC_ENG_SE_TRNG_0_HT_DIS_LEN (1U) -#define SEC_ENG_SE_TRNG_0_HT_DIS_MSK (((1U << SEC_ENG_SE_TRNG_0_HT_DIS_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_DIS_POS) -#define SEC_ENG_SE_TRNG_0_HT_DIS_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_HT_DIS_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_DIS_POS)) -#define SEC_ENG_SE_TRNG_0_HT_ALARM_N SEC_ENG_SE_TRNG_0_HT_ALARM_N -#define SEC_ENG_SE_TRNG_0_HT_ALARM_N_POS (4U) -#define SEC_ENG_SE_TRNG_0_HT_ALARM_N_LEN (8U) -#define SEC_ENG_SE_TRNG_0_HT_ALARM_N_MSK (((1U << SEC_ENG_SE_TRNG_0_HT_ALARM_N_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_ALARM_N_POS) -#define SEC_ENG_SE_TRNG_0_HT_ALARM_N_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_HT_ALARM_N_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_ALARM_N_POS)) - -/* 0x22C : se_trng_0_ctrl_1 */ -#define SEC_ENG_SE_TRNG_0_CTRL_1_OFFSET (0x22C) -#define SEC_ENG_SE_TRNG_0_RESEED_N_LSB SEC_ENG_SE_TRNG_0_RESEED_N_LSB -#define SEC_ENG_SE_TRNG_0_RESEED_N_LSB_POS (0U) -#define SEC_ENG_SE_TRNG_0_RESEED_N_LSB_LEN (32U) -#define SEC_ENG_SE_TRNG_0_RESEED_N_LSB_MSK (((1U << SEC_ENG_SE_TRNG_0_RESEED_N_LSB_LEN) - 1) << SEC_ENG_SE_TRNG_0_RESEED_N_LSB_POS) -#define SEC_ENG_SE_TRNG_0_RESEED_N_LSB_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_RESEED_N_LSB_LEN) - 1) << SEC_ENG_SE_TRNG_0_RESEED_N_LSB_POS)) - -/* 0x230 : se_trng_0_ctrl_2 */ -#define SEC_ENG_SE_TRNG_0_CTRL_2_OFFSET (0x230) -#define SEC_ENG_SE_TRNG_0_RESEED_N_MSB SEC_ENG_SE_TRNG_0_RESEED_N_MSB -#define SEC_ENG_SE_TRNG_0_RESEED_N_MSB_POS (0U) -#define SEC_ENG_SE_TRNG_0_RESEED_N_MSB_LEN (16U) -#define SEC_ENG_SE_TRNG_0_RESEED_N_MSB_MSK (((1U << SEC_ENG_SE_TRNG_0_RESEED_N_MSB_LEN) - 1) << SEC_ENG_SE_TRNG_0_RESEED_N_MSB_POS) -#define SEC_ENG_SE_TRNG_0_RESEED_N_MSB_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_RESEED_N_MSB_LEN) - 1) << SEC_ENG_SE_TRNG_0_RESEED_N_MSB_POS)) - -/* 0x234 : se_trng_0_ctrl_3 */ -#define SEC_ENG_SE_TRNG_0_CTRL_3_OFFSET (0x234) -#define SEC_ENG_SE_TRNG_0_CP_RATIO SEC_ENG_SE_TRNG_0_CP_RATIO -#define SEC_ENG_SE_TRNG_0_CP_RATIO_POS (0U) -#define SEC_ENG_SE_TRNG_0_CP_RATIO_LEN (8U) -#define SEC_ENG_SE_TRNG_0_CP_RATIO_MSK (((1U << SEC_ENG_SE_TRNG_0_CP_RATIO_LEN) - 1) << SEC_ENG_SE_TRNG_0_CP_RATIO_POS) -#define SEC_ENG_SE_TRNG_0_CP_RATIO_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_CP_RATIO_LEN) - 1) << SEC_ENG_SE_TRNG_0_CP_RATIO_POS)) -#define SEC_ENG_SE_TRNG_0_HT_RCT_C SEC_ENG_SE_TRNG_0_HT_RCT_C -#define SEC_ENG_SE_TRNG_0_HT_RCT_C_POS (8U) -#define SEC_ENG_SE_TRNG_0_HT_RCT_C_LEN (8U) -#define SEC_ENG_SE_TRNG_0_HT_RCT_C_MSK (((1U << SEC_ENG_SE_TRNG_0_HT_RCT_C_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_RCT_C_POS) -#define SEC_ENG_SE_TRNG_0_HT_RCT_C_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_HT_RCT_C_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_RCT_C_POS)) -#define SEC_ENG_SE_TRNG_0_HT_APT_C SEC_ENG_SE_TRNG_0_HT_APT_C -#define SEC_ENG_SE_TRNG_0_HT_APT_C_POS (16U) -#define SEC_ENG_SE_TRNG_0_HT_APT_C_LEN (10U) -#define SEC_ENG_SE_TRNG_0_HT_APT_C_MSK (((1U << SEC_ENG_SE_TRNG_0_HT_APT_C_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_APT_C_POS) -#define SEC_ENG_SE_TRNG_0_HT_APT_C_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_HT_APT_C_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_APT_C_POS)) -#define SEC_ENG_SE_TRNG_0_HT_OD_EN SEC_ENG_SE_TRNG_0_HT_OD_EN -#define SEC_ENG_SE_TRNG_0_HT_OD_EN_POS (26U) -#define SEC_ENG_SE_TRNG_0_HT_OD_EN_LEN (1U) -#define SEC_ENG_SE_TRNG_0_HT_OD_EN_MSK (((1U << SEC_ENG_SE_TRNG_0_HT_OD_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_OD_EN_POS) -#define SEC_ENG_SE_TRNG_0_HT_OD_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_HT_OD_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_OD_EN_POS)) -#define SEC_ENG_SE_TRNG_0_ROSC_EN SEC_ENG_SE_TRNG_0_ROSC_EN -#define SEC_ENG_SE_TRNG_0_ROSC_EN_POS (31U) -#define SEC_ENG_SE_TRNG_0_ROSC_EN_LEN (1U) -#define SEC_ENG_SE_TRNG_0_ROSC_EN_MSK (((1U << SEC_ENG_SE_TRNG_0_ROSC_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_ROSC_EN_POS) -#define SEC_ENG_SE_TRNG_0_ROSC_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_ROSC_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_ROSC_EN_POS)) - -/* 0x240 : se_trng_0_test_out_0 */ -#define SEC_ENG_SE_TRNG_0_TEST_OUT_0_OFFSET (0x240) -#define SEC_ENG_SE_TRNG_0_TEST_OUT_0 SEC_ENG_SE_TRNG_0_TEST_OUT_0 -#define SEC_ENG_SE_TRNG_0_TEST_OUT_0_POS (0U) -#define SEC_ENG_SE_TRNG_0_TEST_OUT_0_LEN (32U) -#define SEC_ENG_SE_TRNG_0_TEST_OUT_0_MSK (((1U << SEC_ENG_SE_TRNG_0_TEST_OUT_0_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_OUT_0_POS) -#define SEC_ENG_SE_TRNG_0_TEST_OUT_0_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_TEST_OUT_0_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_OUT_0_POS)) - -/* 0x244 : se_trng_0_test_out_1 */ -#define SEC_ENG_SE_TRNG_0_TEST_OUT_1_OFFSET (0x244) -#define SEC_ENG_SE_TRNG_0_TEST_OUT_1 SEC_ENG_SE_TRNG_0_TEST_OUT_1 -#define SEC_ENG_SE_TRNG_0_TEST_OUT_1_POS (0U) -#define SEC_ENG_SE_TRNG_0_TEST_OUT_1_LEN (32U) -#define SEC_ENG_SE_TRNG_0_TEST_OUT_1_MSK (((1U << SEC_ENG_SE_TRNG_0_TEST_OUT_1_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_OUT_1_POS) -#define SEC_ENG_SE_TRNG_0_TEST_OUT_1_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_TEST_OUT_1_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_OUT_1_POS)) - -/* 0x248 : se_trng_0_test_out_2 */ -#define SEC_ENG_SE_TRNG_0_TEST_OUT_2_OFFSET (0x248) -#define SEC_ENG_SE_TRNG_0_TEST_OUT_2 SEC_ENG_SE_TRNG_0_TEST_OUT_2 -#define SEC_ENG_SE_TRNG_0_TEST_OUT_2_POS (0U) -#define SEC_ENG_SE_TRNG_0_TEST_OUT_2_LEN (32U) -#define SEC_ENG_SE_TRNG_0_TEST_OUT_2_MSK (((1U << SEC_ENG_SE_TRNG_0_TEST_OUT_2_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_OUT_2_POS) -#define SEC_ENG_SE_TRNG_0_TEST_OUT_2_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_TEST_OUT_2_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_OUT_2_POS)) - -/* 0x24C : se_trng_0_test_out_3 */ -#define SEC_ENG_SE_TRNG_0_TEST_OUT_3_OFFSET (0x24C) -#define SEC_ENG_SE_TRNG_0_TEST_OUT_3 SEC_ENG_SE_TRNG_0_TEST_OUT_3 -#define SEC_ENG_SE_TRNG_0_TEST_OUT_3_POS (0U) -#define SEC_ENG_SE_TRNG_0_TEST_OUT_3_LEN (32U) -#define SEC_ENG_SE_TRNG_0_TEST_OUT_3_MSK (((1U << SEC_ENG_SE_TRNG_0_TEST_OUT_3_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_OUT_3_POS) -#define SEC_ENG_SE_TRNG_0_TEST_OUT_3_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_TEST_OUT_3_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_OUT_3_POS)) - -/* 0x2FC : se_trng_0_ctrl_prot */ -#define SEC_ENG_SE_TRNG_0_CTRL_PROT_OFFSET (0x2FC) -#define SEC_ENG_SE_TRNG_ID0_EN SEC_ENG_SE_TRNG_ID0_EN -#define SEC_ENG_SE_TRNG_ID0_EN_POS (1U) -#define SEC_ENG_SE_TRNG_ID0_EN_LEN (1U) -#define SEC_ENG_SE_TRNG_ID0_EN_MSK (((1U << SEC_ENG_SE_TRNG_ID0_EN_LEN) - 1) << SEC_ENG_SE_TRNG_ID0_EN_POS) -#define SEC_ENG_SE_TRNG_ID0_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_ID0_EN_LEN) - 1) << SEC_ENG_SE_TRNG_ID0_EN_POS)) -#define SEC_ENG_SE_TRNG_ID1_EN SEC_ENG_SE_TRNG_ID1_EN -#define SEC_ENG_SE_TRNG_ID1_EN_POS (2U) -#define SEC_ENG_SE_TRNG_ID1_EN_LEN (1U) -#define SEC_ENG_SE_TRNG_ID1_EN_MSK (((1U << SEC_ENG_SE_TRNG_ID1_EN_LEN) - 1) << SEC_ENG_SE_TRNG_ID1_EN_POS) -#define SEC_ENG_SE_TRNG_ID1_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_ID1_EN_LEN) - 1) << SEC_ENG_SE_TRNG_ID1_EN_POS)) - -/* 0x300 : se_pka_0_ctrl_0 */ -#define SEC_ENG_SE_PKA_0_CTRL_0_OFFSET (0x300) -#define SEC_ENG_SE_PKA_0_DONE SEC_ENG_SE_PKA_0_DONE -#define SEC_ENG_SE_PKA_0_DONE_POS (0U) -#define SEC_ENG_SE_PKA_0_DONE_LEN (1U) -#define SEC_ENG_SE_PKA_0_DONE_MSK (((1U << SEC_ENG_SE_PKA_0_DONE_LEN) - 1) << SEC_ENG_SE_PKA_0_DONE_POS) -#define SEC_ENG_SE_PKA_0_DONE_UMSK (~(((1U << SEC_ENG_SE_PKA_0_DONE_LEN) - 1) << SEC_ENG_SE_PKA_0_DONE_POS)) -#define SEC_ENG_SE_PKA_0_DONE_CLR_1T SEC_ENG_SE_PKA_0_DONE_CLR_1T -#define SEC_ENG_SE_PKA_0_DONE_CLR_1T_POS (1U) -#define SEC_ENG_SE_PKA_0_DONE_CLR_1T_LEN (1U) -#define SEC_ENG_SE_PKA_0_DONE_CLR_1T_MSK (((1U << SEC_ENG_SE_PKA_0_DONE_CLR_1T_LEN) - 1) << SEC_ENG_SE_PKA_0_DONE_CLR_1T_POS) -#define SEC_ENG_SE_PKA_0_DONE_CLR_1T_UMSK (~(((1U << SEC_ENG_SE_PKA_0_DONE_CLR_1T_LEN) - 1) << SEC_ENG_SE_PKA_0_DONE_CLR_1T_POS)) -#define SEC_ENG_SE_PKA_0_BUSY SEC_ENG_SE_PKA_0_BUSY -#define SEC_ENG_SE_PKA_0_BUSY_POS (2U) -#define SEC_ENG_SE_PKA_0_BUSY_LEN (1U) -#define SEC_ENG_SE_PKA_0_BUSY_MSK (((1U << SEC_ENG_SE_PKA_0_BUSY_LEN) - 1) << SEC_ENG_SE_PKA_0_BUSY_POS) -#define SEC_ENG_SE_PKA_0_BUSY_UMSK (~(((1U << SEC_ENG_SE_PKA_0_BUSY_LEN) - 1) << SEC_ENG_SE_PKA_0_BUSY_POS)) -#define SEC_ENG_SE_PKA_0_EN SEC_ENG_SE_PKA_0_EN -#define SEC_ENG_SE_PKA_0_EN_POS (3U) -#define SEC_ENG_SE_PKA_0_EN_LEN (1U) -#define SEC_ENG_SE_PKA_0_EN_MSK (((1U << SEC_ENG_SE_PKA_0_EN_LEN) - 1) << SEC_ENG_SE_PKA_0_EN_POS) -#define SEC_ENG_SE_PKA_0_EN_UMSK (~(((1U << SEC_ENG_SE_PKA_0_EN_LEN) - 1) << SEC_ENG_SE_PKA_0_EN_POS)) -#define SEC_ENG_SE_PKA_0_PROT_MD SEC_ENG_SE_PKA_0_PROT_MD -#define SEC_ENG_SE_PKA_0_PROT_MD_POS (4U) -#define SEC_ENG_SE_PKA_0_PROT_MD_LEN (4U) -#define SEC_ENG_SE_PKA_0_PROT_MD_MSK (((1U << SEC_ENG_SE_PKA_0_PROT_MD_LEN) - 1) << SEC_ENG_SE_PKA_0_PROT_MD_POS) -#define SEC_ENG_SE_PKA_0_PROT_MD_UMSK (~(((1U << SEC_ENG_SE_PKA_0_PROT_MD_LEN) - 1) << SEC_ENG_SE_PKA_0_PROT_MD_POS)) -#define SEC_ENG_SE_PKA_0_INT SEC_ENG_SE_PKA_0_INT -#define SEC_ENG_SE_PKA_0_INT_POS (8U) -#define SEC_ENG_SE_PKA_0_INT_LEN (1U) -#define SEC_ENG_SE_PKA_0_INT_MSK (((1U << SEC_ENG_SE_PKA_0_INT_LEN) - 1) << SEC_ENG_SE_PKA_0_INT_POS) -#define SEC_ENG_SE_PKA_0_INT_UMSK (~(((1U << SEC_ENG_SE_PKA_0_INT_LEN) - 1) << SEC_ENG_SE_PKA_0_INT_POS)) -#define SEC_ENG_SE_PKA_0_INT_CLR_1T SEC_ENG_SE_PKA_0_INT_CLR_1T -#define SEC_ENG_SE_PKA_0_INT_CLR_1T_POS (9U) -#define SEC_ENG_SE_PKA_0_INT_CLR_1T_LEN (1U) -#define SEC_ENG_SE_PKA_0_INT_CLR_1T_MSK (((1U << SEC_ENG_SE_PKA_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_PKA_0_INT_CLR_1T_POS) -#define SEC_ENG_SE_PKA_0_INT_CLR_1T_UMSK (~(((1U << SEC_ENG_SE_PKA_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_PKA_0_INT_CLR_1T_POS)) -#define SEC_ENG_SE_PKA_0_INT_SET SEC_ENG_SE_PKA_0_INT_SET -#define SEC_ENG_SE_PKA_0_INT_SET_POS (10U) -#define SEC_ENG_SE_PKA_0_INT_SET_LEN (1U) -#define SEC_ENG_SE_PKA_0_INT_SET_MSK (((1U << SEC_ENG_SE_PKA_0_INT_SET_LEN) - 1) << SEC_ENG_SE_PKA_0_INT_SET_POS) -#define SEC_ENG_SE_PKA_0_INT_SET_UMSK (~(((1U << SEC_ENG_SE_PKA_0_INT_SET_LEN) - 1) << SEC_ENG_SE_PKA_0_INT_SET_POS)) -#define SEC_ENG_SE_PKA_0_INT_MASK SEC_ENG_SE_PKA_0_INT_MASK -#define SEC_ENG_SE_PKA_0_INT_MASK_POS (11U) -#define SEC_ENG_SE_PKA_0_INT_MASK_LEN (1U) -#define SEC_ENG_SE_PKA_0_INT_MASK_MSK (((1U << SEC_ENG_SE_PKA_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_PKA_0_INT_MASK_POS) -#define SEC_ENG_SE_PKA_0_INT_MASK_UMSK (~(((1U << SEC_ENG_SE_PKA_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_PKA_0_INT_MASK_POS)) -#define SEC_ENG_SE_PKA_0_ENDIAN SEC_ENG_SE_PKA_0_ENDIAN -#define SEC_ENG_SE_PKA_0_ENDIAN_POS (12U) -#define SEC_ENG_SE_PKA_0_ENDIAN_LEN (1U) -#define SEC_ENG_SE_PKA_0_ENDIAN_MSK (((1U << SEC_ENG_SE_PKA_0_ENDIAN_LEN) - 1) << SEC_ENG_SE_PKA_0_ENDIAN_POS) -#define SEC_ENG_SE_PKA_0_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_PKA_0_ENDIAN_LEN) - 1) << SEC_ENG_SE_PKA_0_ENDIAN_POS)) -#define SEC_ENG_SE_PKA_0_RAM_CLR_MD SEC_ENG_SE_PKA_0_RAM_CLR_MD -#define SEC_ENG_SE_PKA_0_RAM_CLR_MD_POS (13U) -#define SEC_ENG_SE_PKA_0_RAM_CLR_MD_LEN (1U) -#define SEC_ENG_SE_PKA_0_RAM_CLR_MD_MSK (((1U << SEC_ENG_SE_PKA_0_RAM_CLR_MD_LEN) - 1) << SEC_ENG_SE_PKA_0_RAM_CLR_MD_POS) -#define SEC_ENG_SE_PKA_0_RAM_CLR_MD_UMSK (~(((1U << SEC_ENG_SE_PKA_0_RAM_CLR_MD_LEN) - 1) << SEC_ENG_SE_PKA_0_RAM_CLR_MD_POS)) -#define SEC_ENG_SE_PKA_0_STATUS_CLR_1T SEC_ENG_SE_PKA_0_STATUS_CLR_1T -#define SEC_ENG_SE_PKA_0_STATUS_CLR_1T_POS (15U) -#define SEC_ENG_SE_PKA_0_STATUS_CLR_1T_LEN (1U) -#define SEC_ENG_SE_PKA_0_STATUS_CLR_1T_MSK (((1U << SEC_ENG_SE_PKA_0_STATUS_CLR_1T_LEN) - 1) << SEC_ENG_SE_PKA_0_STATUS_CLR_1T_POS) -#define SEC_ENG_SE_PKA_0_STATUS_CLR_1T_UMSK (~(((1U << SEC_ENG_SE_PKA_0_STATUS_CLR_1T_LEN) - 1) << SEC_ENG_SE_PKA_0_STATUS_CLR_1T_POS)) -#define SEC_ENG_SE_PKA_0_STATUS SEC_ENG_SE_PKA_0_STATUS -#define SEC_ENG_SE_PKA_0_STATUS_POS (16U) -#define SEC_ENG_SE_PKA_0_STATUS_LEN (16U) -#define SEC_ENG_SE_PKA_0_STATUS_MSK (((1U << SEC_ENG_SE_PKA_0_STATUS_LEN) - 1) << SEC_ENG_SE_PKA_0_STATUS_POS) -#define SEC_ENG_SE_PKA_0_STATUS_UMSK (~(((1U << SEC_ENG_SE_PKA_0_STATUS_LEN) - 1) << SEC_ENG_SE_PKA_0_STATUS_POS)) - -/* 0x30C : se_pka_0_seed */ -#define SEC_ENG_SE_PKA_0_SEED_OFFSET (0x30C) -#define SEC_ENG_SE_PKA_0_SEED SEC_ENG_SE_PKA_0_SEED -#define SEC_ENG_SE_PKA_0_SEED_POS (0U) -#define SEC_ENG_SE_PKA_0_SEED_LEN (32U) -#define SEC_ENG_SE_PKA_0_SEED_MSK (((1U << SEC_ENG_SE_PKA_0_SEED_LEN) - 1) << SEC_ENG_SE_PKA_0_SEED_POS) -#define SEC_ENG_SE_PKA_0_SEED_UMSK (~(((1U << SEC_ENG_SE_PKA_0_SEED_LEN) - 1) << SEC_ENG_SE_PKA_0_SEED_POS)) - -/* 0x310 : se_pka_0_ctrl_1 */ -#define SEC_ENG_SE_PKA_0_CTRL_1_OFFSET (0x310) -#define SEC_ENG_SE_PKA_0_HBURST SEC_ENG_SE_PKA_0_HBURST -#define SEC_ENG_SE_PKA_0_HBURST_POS (0U) -#define SEC_ENG_SE_PKA_0_HBURST_LEN (3U) -#define SEC_ENG_SE_PKA_0_HBURST_MSK (((1U << SEC_ENG_SE_PKA_0_HBURST_LEN) - 1) << SEC_ENG_SE_PKA_0_HBURST_POS) -#define SEC_ENG_SE_PKA_0_HBURST_UMSK (~(((1U << SEC_ENG_SE_PKA_0_HBURST_LEN) - 1) << SEC_ENG_SE_PKA_0_HBURST_POS)) -#define SEC_ENG_SE_PKA_0_HBYPASS SEC_ENG_SE_PKA_0_HBYPASS -#define SEC_ENG_SE_PKA_0_HBYPASS_POS (3U) -#define SEC_ENG_SE_PKA_0_HBYPASS_LEN (1U) -#define SEC_ENG_SE_PKA_0_HBYPASS_MSK (((1U << SEC_ENG_SE_PKA_0_HBYPASS_LEN) - 1) << SEC_ENG_SE_PKA_0_HBYPASS_POS) -#define SEC_ENG_SE_PKA_0_HBYPASS_UMSK (~(((1U << SEC_ENG_SE_PKA_0_HBYPASS_LEN) - 1) << SEC_ENG_SE_PKA_0_HBYPASS_POS)) - -/* 0x340 : se_pka_0_rw */ -#define SEC_ENG_SE_PKA_0_RW_OFFSET (0x340) - -/* 0x360 : se_pka_0_rw_burst */ -#define SEC_ENG_SE_PKA_0_RW_BURST_OFFSET (0x360) - -/* 0x3FC : se_pka_0_ctrl_prot */ -#define SEC_ENG_SE_PKA_0_CTRL_PROT_OFFSET (0x3FC) -#define SEC_ENG_SE_PKA_ID0_EN SEC_ENG_SE_PKA_ID0_EN -#define SEC_ENG_SE_PKA_ID0_EN_POS (1U) -#define SEC_ENG_SE_PKA_ID0_EN_LEN (1U) -#define SEC_ENG_SE_PKA_ID0_EN_MSK (((1U << SEC_ENG_SE_PKA_ID0_EN_LEN) - 1) << SEC_ENG_SE_PKA_ID0_EN_POS) -#define SEC_ENG_SE_PKA_ID0_EN_UMSK (~(((1U << SEC_ENG_SE_PKA_ID0_EN_LEN) - 1) << SEC_ENG_SE_PKA_ID0_EN_POS)) -#define SEC_ENG_SE_PKA_ID1_EN SEC_ENG_SE_PKA_ID1_EN -#define SEC_ENG_SE_PKA_ID1_EN_POS (2U) -#define SEC_ENG_SE_PKA_ID1_EN_LEN (1U) -#define SEC_ENG_SE_PKA_ID1_EN_MSK (((1U << SEC_ENG_SE_PKA_ID1_EN_LEN) - 1) << SEC_ENG_SE_PKA_ID1_EN_POS) -#define SEC_ENG_SE_PKA_ID1_EN_UMSK (~(((1U << SEC_ENG_SE_PKA_ID1_EN_LEN) - 1) << SEC_ENG_SE_PKA_ID1_EN_POS)) - -/* 0x400 : se_cdet_0_ctrl_0 */ -#define SEC_ENG_SE_CDET_0_CTRL_0_OFFSET (0x400) -#define SEC_ENG_SE_CDET_0_EN SEC_ENG_SE_CDET_0_EN -#define SEC_ENG_SE_CDET_0_EN_POS (0U) -#define SEC_ENG_SE_CDET_0_EN_LEN (1U) -#define SEC_ENG_SE_CDET_0_EN_MSK (((1U << SEC_ENG_SE_CDET_0_EN_LEN) - 1) << SEC_ENG_SE_CDET_0_EN_POS) -#define SEC_ENG_SE_CDET_0_EN_UMSK (~(((1U << SEC_ENG_SE_CDET_0_EN_LEN) - 1) << SEC_ENG_SE_CDET_0_EN_POS)) -#define SEC_ENG_SE_CDET_0_ERROR SEC_ENG_SE_CDET_0_ERROR -#define SEC_ENG_SE_CDET_0_ERROR_POS (1U) -#define SEC_ENG_SE_CDET_0_ERROR_LEN (1U) -#define SEC_ENG_SE_CDET_0_ERROR_MSK (((1U << SEC_ENG_SE_CDET_0_ERROR_LEN) - 1) << SEC_ENG_SE_CDET_0_ERROR_POS) -#define SEC_ENG_SE_CDET_0_ERROR_UMSK (~(((1U << SEC_ENG_SE_CDET_0_ERROR_LEN) - 1) << SEC_ENG_SE_CDET_0_ERROR_POS)) -#define SEC_ENG_SE_CDET_0_STATUS SEC_ENG_SE_CDET_0_STATUS -#define SEC_ENG_SE_CDET_0_STATUS_POS (2U) -#define SEC_ENG_SE_CDET_0_STATUS_LEN (14U) -#define SEC_ENG_SE_CDET_0_STATUS_MSK (((1U << SEC_ENG_SE_CDET_0_STATUS_LEN) - 1) << SEC_ENG_SE_CDET_0_STATUS_POS) -#define SEC_ENG_SE_CDET_0_STATUS_UMSK (~(((1U << SEC_ENG_SE_CDET_0_STATUS_LEN) - 1) << SEC_ENG_SE_CDET_0_STATUS_POS)) -#define SEC_ENG_SE_CDET_0_G_LOOP_MAX SEC_ENG_SE_CDET_0_G_LOOP_MAX -#define SEC_ENG_SE_CDET_0_G_LOOP_MAX_POS (16U) -#define SEC_ENG_SE_CDET_0_G_LOOP_MAX_LEN (8U) -#define SEC_ENG_SE_CDET_0_G_LOOP_MAX_MSK (((1U << SEC_ENG_SE_CDET_0_G_LOOP_MAX_LEN) - 1) << SEC_ENG_SE_CDET_0_G_LOOP_MAX_POS) -#define SEC_ENG_SE_CDET_0_G_LOOP_MAX_UMSK (~(((1U << SEC_ENG_SE_CDET_0_G_LOOP_MAX_LEN) - 1) << SEC_ENG_SE_CDET_0_G_LOOP_MAX_POS)) -#define SEC_ENG_SE_CDET_0_G_LOOP_MIN SEC_ENG_SE_CDET_0_G_LOOP_MIN -#define SEC_ENG_SE_CDET_0_G_LOOP_MIN_POS (24U) -#define SEC_ENG_SE_CDET_0_G_LOOP_MIN_LEN (8U) -#define SEC_ENG_SE_CDET_0_G_LOOP_MIN_MSK (((1U << SEC_ENG_SE_CDET_0_G_LOOP_MIN_LEN) - 1) << SEC_ENG_SE_CDET_0_G_LOOP_MIN_POS) -#define SEC_ENG_SE_CDET_0_G_LOOP_MIN_UMSK (~(((1U << SEC_ENG_SE_CDET_0_G_LOOP_MIN_LEN) - 1) << SEC_ENG_SE_CDET_0_G_LOOP_MIN_POS)) - -/* 0x404 : se_cdet_0_ctrl_1 */ -#define SEC_ENG_SE_CDET_0_CTRL_1_OFFSET (0x404) -#define SEC_ENG_SE_CDET_0_T_LOOP_N SEC_ENG_SE_CDET_0_T_LOOP_N -#define SEC_ENG_SE_CDET_0_T_LOOP_N_POS (0U) -#define SEC_ENG_SE_CDET_0_T_LOOP_N_LEN (8U) -#define SEC_ENG_SE_CDET_0_T_LOOP_N_MSK (((1U << SEC_ENG_SE_CDET_0_T_LOOP_N_LEN) - 1) << SEC_ENG_SE_CDET_0_T_LOOP_N_POS) -#define SEC_ENG_SE_CDET_0_T_LOOP_N_UMSK (~(((1U << SEC_ENG_SE_CDET_0_T_LOOP_N_LEN) - 1) << SEC_ENG_SE_CDET_0_T_LOOP_N_POS)) -#define SEC_ENG_SE_CDET_0_T_DLY_N SEC_ENG_SE_CDET_0_T_DLY_N -#define SEC_ENG_SE_CDET_0_T_DLY_N_POS (8U) -#define SEC_ENG_SE_CDET_0_T_DLY_N_LEN (8U) -#define SEC_ENG_SE_CDET_0_T_DLY_N_MSK (((1U << SEC_ENG_SE_CDET_0_T_DLY_N_LEN) - 1) << SEC_ENG_SE_CDET_0_T_DLY_N_POS) -#define SEC_ENG_SE_CDET_0_T_DLY_N_UMSK (~(((1U << SEC_ENG_SE_CDET_0_T_DLY_N_LEN) - 1) << SEC_ENG_SE_CDET_0_T_DLY_N_POS)) -#define SEC_ENG_SE_CDET_0_G_SLP_N SEC_ENG_SE_CDET_0_G_SLP_N -#define SEC_ENG_SE_CDET_0_G_SLP_N_POS (16U) -#define SEC_ENG_SE_CDET_0_G_SLP_N_LEN (8U) -#define SEC_ENG_SE_CDET_0_G_SLP_N_MSK (((1U << SEC_ENG_SE_CDET_0_G_SLP_N_LEN) - 1) << SEC_ENG_SE_CDET_0_G_SLP_N_POS) -#define SEC_ENG_SE_CDET_0_G_SLP_N_UMSK (~(((1U << SEC_ENG_SE_CDET_0_G_SLP_N_LEN) - 1) << SEC_ENG_SE_CDET_0_G_SLP_N_POS)) - -/* 0x4FC : se_cdet_0_ctrl_prot */ -#define SEC_ENG_SE_CDET_0_CTRL_PROT_OFFSET (0x4FC) -#define SEC_ENG_SE_CDET_PROT_EN SEC_ENG_SE_CDET_PROT_EN -#define SEC_ENG_SE_CDET_PROT_EN_POS (0U) -#define SEC_ENG_SE_CDET_PROT_EN_LEN (1U) -#define SEC_ENG_SE_CDET_PROT_EN_MSK (((1U << SEC_ENG_SE_CDET_PROT_EN_LEN) - 1) << SEC_ENG_SE_CDET_PROT_EN_POS) -#define SEC_ENG_SE_CDET_PROT_EN_UMSK (~(((1U << SEC_ENG_SE_CDET_PROT_EN_LEN) - 1) << SEC_ENG_SE_CDET_PROT_EN_POS)) -#define SEC_ENG_SE_CDET_ID0_EN SEC_ENG_SE_CDET_ID0_EN -#define SEC_ENG_SE_CDET_ID0_EN_POS (1U) -#define SEC_ENG_SE_CDET_ID0_EN_LEN (1U) -#define SEC_ENG_SE_CDET_ID0_EN_MSK (((1U << SEC_ENG_SE_CDET_ID0_EN_LEN) - 1) << SEC_ENG_SE_CDET_ID0_EN_POS) -#define SEC_ENG_SE_CDET_ID0_EN_UMSK (~(((1U << SEC_ENG_SE_CDET_ID0_EN_LEN) - 1) << SEC_ENG_SE_CDET_ID0_EN_POS)) -#define SEC_ENG_SE_CDET_ID1_EN SEC_ENG_SE_CDET_ID1_EN -#define SEC_ENG_SE_CDET_ID1_EN_POS (2U) -#define SEC_ENG_SE_CDET_ID1_EN_LEN (1U) -#define SEC_ENG_SE_CDET_ID1_EN_MSK (((1U << SEC_ENG_SE_CDET_ID1_EN_LEN) - 1) << SEC_ENG_SE_CDET_ID1_EN_POS) -#define SEC_ENG_SE_CDET_ID1_EN_UMSK (~(((1U << SEC_ENG_SE_CDET_ID1_EN_LEN) - 1) << SEC_ENG_SE_CDET_ID1_EN_POS)) - -/* 0x500 : se_gmac_0_ctrl_0 */ -#define SEC_ENG_SE_GMAC_0_CTRL_0_OFFSET (0x500) -#define SEC_ENG_SE_GMAC_0_BUSY SEC_ENG_SE_GMAC_0_BUSY -#define SEC_ENG_SE_GMAC_0_BUSY_POS (0U) -#define SEC_ENG_SE_GMAC_0_BUSY_LEN (1U) -#define SEC_ENG_SE_GMAC_0_BUSY_MSK (((1U << SEC_ENG_SE_GMAC_0_BUSY_LEN) - 1) << SEC_ENG_SE_GMAC_0_BUSY_POS) -#define SEC_ENG_SE_GMAC_0_BUSY_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_BUSY_LEN) - 1) << SEC_ENG_SE_GMAC_0_BUSY_POS)) -#define SEC_ENG_SE_GMAC_0_TRIG_1T SEC_ENG_SE_GMAC_0_TRIG_1T -#define SEC_ENG_SE_GMAC_0_TRIG_1T_POS (1U) -#define SEC_ENG_SE_GMAC_0_TRIG_1T_LEN (1U) -#define SEC_ENG_SE_GMAC_0_TRIG_1T_MSK (((1U << SEC_ENG_SE_GMAC_0_TRIG_1T_LEN) - 1) << SEC_ENG_SE_GMAC_0_TRIG_1T_POS) -#define SEC_ENG_SE_GMAC_0_TRIG_1T_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_TRIG_1T_LEN) - 1) << SEC_ENG_SE_GMAC_0_TRIG_1T_POS)) -#define SEC_ENG_SE_GMAC_0_EN SEC_ENG_SE_GMAC_0_EN -#define SEC_ENG_SE_GMAC_0_EN_POS (2U) -#define SEC_ENG_SE_GMAC_0_EN_LEN (1U) -#define SEC_ENG_SE_GMAC_0_EN_MSK (((1U << SEC_ENG_SE_GMAC_0_EN_LEN) - 1) << SEC_ENG_SE_GMAC_0_EN_POS) -#define SEC_ENG_SE_GMAC_0_EN_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_EN_LEN) - 1) << SEC_ENG_SE_GMAC_0_EN_POS)) -#define SEC_ENG_SE_GMAC_0_INT SEC_ENG_SE_GMAC_0_INT -#define SEC_ENG_SE_GMAC_0_INT_POS (8U) -#define SEC_ENG_SE_GMAC_0_INT_LEN (1U) -#define SEC_ENG_SE_GMAC_0_INT_MSK (((1U << SEC_ENG_SE_GMAC_0_INT_LEN) - 1) << SEC_ENG_SE_GMAC_0_INT_POS) -#define SEC_ENG_SE_GMAC_0_INT_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_INT_LEN) - 1) << SEC_ENG_SE_GMAC_0_INT_POS)) -#define SEC_ENG_SE_GMAC_0_INT_CLR_1T SEC_ENG_SE_GMAC_0_INT_CLR_1T -#define SEC_ENG_SE_GMAC_0_INT_CLR_1T_POS (9U) -#define SEC_ENG_SE_GMAC_0_INT_CLR_1T_LEN (1U) -#define SEC_ENG_SE_GMAC_0_INT_CLR_1T_MSK (((1U << SEC_ENG_SE_GMAC_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_GMAC_0_INT_CLR_1T_POS) -#define SEC_ENG_SE_GMAC_0_INT_CLR_1T_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_GMAC_0_INT_CLR_1T_POS)) -#define SEC_ENG_SE_GMAC_0_INT_SET_1T SEC_ENG_SE_GMAC_0_INT_SET_1T -#define SEC_ENG_SE_GMAC_0_INT_SET_1T_POS (10U) -#define SEC_ENG_SE_GMAC_0_INT_SET_1T_LEN (1U) -#define SEC_ENG_SE_GMAC_0_INT_SET_1T_MSK (((1U << SEC_ENG_SE_GMAC_0_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_GMAC_0_INT_SET_1T_POS) -#define SEC_ENG_SE_GMAC_0_INT_SET_1T_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_GMAC_0_INT_SET_1T_POS)) -#define SEC_ENG_SE_GMAC_0_INT_MASK SEC_ENG_SE_GMAC_0_INT_MASK -#define SEC_ENG_SE_GMAC_0_INT_MASK_POS (11U) -#define SEC_ENG_SE_GMAC_0_INT_MASK_LEN (1U) -#define SEC_ENG_SE_GMAC_0_INT_MASK_MSK (((1U << SEC_ENG_SE_GMAC_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_GMAC_0_INT_MASK_POS) -#define SEC_ENG_SE_GMAC_0_INT_MASK_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_GMAC_0_INT_MASK_POS)) -#define SEC_ENG_SE_GMAC_0_T_ENDIAN SEC_ENG_SE_GMAC_0_T_ENDIAN -#define SEC_ENG_SE_GMAC_0_T_ENDIAN_POS (12U) -#define SEC_ENG_SE_GMAC_0_T_ENDIAN_LEN (1U) -#define SEC_ENG_SE_GMAC_0_T_ENDIAN_MSK (((1U << SEC_ENG_SE_GMAC_0_T_ENDIAN_LEN) - 1) << SEC_ENG_SE_GMAC_0_T_ENDIAN_POS) -#define SEC_ENG_SE_GMAC_0_T_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_T_ENDIAN_LEN) - 1) << SEC_ENG_SE_GMAC_0_T_ENDIAN_POS)) -#define SEC_ENG_SE_GMAC_0_H_ENDIAN SEC_ENG_SE_GMAC_0_H_ENDIAN -#define SEC_ENG_SE_GMAC_0_H_ENDIAN_POS (13U) -#define SEC_ENG_SE_GMAC_0_H_ENDIAN_LEN (1U) -#define SEC_ENG_SE_GMAC_0_H_ENDIAN_MSK (((1U << SEC_ENG_SE_GMAC_0_H_ENDIAN_LEN) - 1) << SEC_ENG_SE_GMAC_0_H_ENDIAN_POS) -#define SEC_ENG_SE_GMAC_0_H_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_H_ENDIAN_LEN) - 1) << SEC_ENG_SE_GMAC_0_H_ENDIAN_POS)) -#define SEC_ENG_SE_GMAC_0_X_ENDIAN SEC_ENG_SE_GMAC_0_X_ENDIAN -#define SEC_ENG_SE_GMAC_0_X_ENDIAN_POS (14U) -#define SEC_ENG_SE_GMAC_0_X_ENDIAN_LEN (1U) -#define SEC_ENG_SE_GMAC_0_X_ENDIAN_MSK (((1U << SEC_ENG_SE_GMAC_0_X_ENDIAN_LEN) - 1) << SEC_ENG_SE_GMAC_0_X_ENDIAN_POS) -#define SEC_ENG_SE_GMAC_0_X_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_X_ENDIAN_LEN) - 1) << SEC_ENG_SE_GMAC_0_X_ENDIAN_POS)) - -/* 0x504 : se_gmac_0_lca */ -#define SEC_ENG_SE_GMAC_0_LCA_OFFSET (0x504) -#define SEC_ENG_SE_GMAC_0_LCA SEC_ENG_SE_GMAC_0_LCA -#define SEC_ENG_SE_GMAC_0_LCA_POS (0U) -#define SEC_ENG_SE_GMAC_0_LCA_LEN (32U) -#define SEC_ENG_SE_GMAC_0_LCA_MSK (((1U << SEC_ENG_SE_GMAC_0_LCA_LEN) - 1) << SEC_ENG_SE_GMAC_0_LCA_POS) -#define SEC_ENG_SE_GMAC_0_LCA_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_LCA_LEN) - 1) << SEC_ENG_SE_GMAC_0_LCA_POS)) - -/* 0x508 : se_gmac_0_status */ -#define SEC_ENG_SE_GMAC_0_STATUS_OFFSET (0x508) -#define SEC_ENG_SE_GMAC_0_STATUS SEC_ENG_SE_GMAC_0_STATUS -#define SEC_ENG_SE_GMAC_0_STATUS_POS (0U) -#define SEC_ENG_SE_GMAC_0_STATUS_LEN (32U) -#define SEC_ENG_SE_GMAC_0_STATUS_MSK (((1U << SEC_ENG_SE_GMAC_0_STATUS_LEN) - 1) << SEC_ENG_SE_GMAC_0_STATUS_POS) -#define SEC_ENG_SE_GMAC_0_STATUS_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_STATUS_LEN) - 1) << SEC_ENG_SE_GMAC_0_STATUS_POS)) - -/* 0x5FC : se_gmac_0_ctrl_prot */ -#define SEC_ENG_SE_GMAC_0_CTRL_PROT_OFFSET (0x5FC) -#define SEC_ENG_SE_GMAC_ID0_EN SEC_ENG_SE_GMAC_ID0_EN -#define SEC_ENG_SE_GMAC_ID0_EN_POS (1U) -#define SEC_ENG_SE_GMAC_ID0_EN_LEN (1U) -#define SEC_ENG_SE_GMAC_ID0_EN_MSK (((1U << SEC_ENG_SE_GMAC_ID0_EN_LEN) - 1) << SEC_ENG_SE_GMAC_ID0_EN_POS) -#define SEC_ENG_SE_GMAC_ID0_EN_UMSK (~(((1U << SEC_ENG_SE_GMAC_ID0_EN_LEN) - 1) << SEC_ENG_SE_GMAC_ID0_EN_POS)) -#define SEC_ENG_SE_GMAC_ID1_EN SEC_ENG_SE_GMAC_ID1_EN -#define SEC_ENG_SE_GMAC_ID1_EN_POS (2U) -#define SEC_ENG_SE_GMAC_ID1_EN_LEN (1U) -#define SEC_ENG_SE_GMAC_ID1_EN_MSK (((1U << SEC_ENG_SE_GMAC_ID1_EN_LEN) - 1) << SEC_ENG_SE_GMAC_ID1_EN_POS) -#define SEC_ENG_SE_GMAC_ID1_EN_UMSK (~(((1U << SEC_ENG_SE_GMAC_ID1_EN_LEN) - 1) << SEC_ENG_SE_GMAC_ID1_EN_POS)) - -/* 0xF00 : se_ctrl_prot_rd */ -#define SEC_ENG_SE_CTRL_PROT_RD_OFFSET (0xF00) -#define SEC_ENG_SE_SHA_ID0_EN_RD SEC_ENG_SE_SHA_ID0_EN_RD -#define SEC_ENG_SE_SHA_ID0_EN_RD_POS (0U) -#define SEC_ENG_SE_SHA_ID0_EN_RD_LEN (1U) -#define SEC_ENG_SE_SHA_ID0_EN_RD_MSK (((1U << SEC_ENG_SE_SHA_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_SHA_ID0_EN_RD_POS) -#define SEC_ENG_SE_SHA_ID0_EN_RD_UMSK (~(((1U << SEC_ENG_SE_SHA_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_SHA_ID0_EN_RD_POS)) -#define SEC_ENG_SE_SHA_ID1_EN_RD SEC_ENG_SE_SHA_ID1_EN_RD -#define SEC_ENG_SE_SHA_ID1_EN_RD_POS (1U) -#define SEC_ENG_SE_SHA_ID1_EN_RD_LEN (1U) -#define SEC_ENG_SE_SHA_ID1_EN_RD_MSK (((1U << SEC_ENG_SE_SHA_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_SHA_ID1_EN_RD_POS) -#define SEC_ENG_SE_SHA_ID1_EN_RD_UMSK (~(((1U << SEC_ENG_SE_SHA_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_SHA_ID1_EN_RD_POS)) -#define SEC_ENG_SE_AES_ID0_EN_RD SEC_ENG_SE_AES_ID0_EN_RD -#define SEC_ENG_SE_AES_ID0_EN_RD_POS (2U) -#define SEC_ENG_SE_AES_ID0_EN_RD_LEN (1U) -#define SEC_ENG_SE_AES_ID0_EN_RD_MSK (((1U << SEC_ENG_SE_AES_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_AES_ID0_EN_RD_POS) -#define SEC_ENG_SE_AES_ID0_EN_RD_UMSK (~(((1U << SEC_ENG_SE_AES_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_AES_ID0_EN_RD_POS)) -#define SEC_ENG_SE_AES_ID1_EN_RD SEC_ENG_SE_AES_ID1_EN_RD -#define SEC_ENG_SE_AES_ID1_EN_RD_POS (3U) -#define SEC_ENG_SE_AES_ID1_EN_RD_LEN (1U) -#define SEC_ENG_SE_AES_ID1_EN_RD_MSK (((1U << SEC_ENG_SE_AES_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_AES_ID1_EN_RD_POS) -#define SEC_ENG_SE_AES_ID1_EN_RD_UMSK (~(((1U << SEC_ENG_SE_AES_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_AES_ID1_EN_RD_POS)) -#define SEC_ENG_SE_TRNG_ID0_EN_RD SEC_ENG_SE_TRNG_ID0_EN_RD -#define SEC_ENG_SE_TRNG_ID0_EN_RD_POS (4U) -#define SEC_ENG_SE_TRNG_ID0_EN_RD_LEN (1U) -#define SEC_ENG_SE_TRNG_ID0_EN_RD_MSK (((1U << SEC_ENG_SE_TRNG_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_TRNG_ID0_EN_RD_POS) -#define SEC_ENG_SE_TRNG_ID0_EN_RD_UMSK (~(((1U << SEC_ENG_SE_TRNG_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_TRNG_ID0_EN_RD_POS)) -#define SEC_ENG_SE_TRNG_ID1_EN_RD SEC_ENG_SE_TRNG_ID1_EN_RD -#define SEC_ENG_SE_TRNG_ID1_EN_RD_POS (5U) -#define SEC_ENG_SE_TRNG_ID1_EN_RD_LEN (1U) -#define SEC_ENG_SE_TRNG_ID1_EN_RD_MSK (((1U << SEC_ENG_SE_TRNG_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_TRNG_ID1_EN_RD_POS) -#define SEC_ENG_SE_TRNG_ID1_EN_RD_UMSK (~(((1U << SEC_ENG_SE_TRNG_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_TRNG_ID1_EN_RD_POS)) -#define SEC_ENG_SE_PKA_ID0_EN_RD SEC_ENG_SE_PKA_ID0_EN_RD -#define SEC_ENG_SE_PKA_ID0_EN_RD_POS (6U) -#define SEC_ENG_SE_PKA_ID0_EN_RD_LEN (1U) -#define SEC_ENG_SE_PKA_ID0_EN_RD_MSK (((1U << SEC_ENG_SE_PKA_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_PKA_ID0_EN_RD_POS) -#define SEC_ENG_SE_PKA_ID0_EN_RD_UMSK (~(((1U << SEC_ENG_SE_PKA_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_PKA_ID0_EN_RD_POS)) -#define SEC_ENG_SE_PKA_ID1_EN_RD SEC_ENG_SE_PKA_ID1_EN_RD -#define SEC_ENG_SE_PKA_ID1_EN_RD_POS (7U) -#define SEC_ENG_SE_PKA_ID1_EN_RD_LEN (1U) -#define SEC_ENG_SE_PKA_ID1_EN_RD_MSK (((1U << SEC_ENG_SE_PKA_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_PKA_ID1_EN_RD_POS) -#define SEC_ENG_SE_PKA_ID1_EN_RD_UMSK (~(((1U << SEC_ENG_SE_PKA_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_PKA_ID1_EN_RD_POS)) -#define SEC_ENG_SE_CDET_ID0_EN_RD SEC_ENG_SE_CDET_ID0_EN_RD -#define SEC_ENG_SE_CDET_ID0_EN_RD_POS (8U) -#define SEC_ENG_SE_CDET_ID0_EN_RD_LEN (1U) -#define SEC_ENG_SE_CDET_ID0_EN_RD_MSK (((1U << SEC_ENG_SE_CDET_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_CDET_ID0_EN_RD_POS) -#define SEC_ENG_SE_CDET_ID0_EN_RD_UMSK (~(((1U << SEC_ENG_SE_CDET_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_CDET_ID0_EN_RD_POS)) -#define SEC_ENG_SE_CDET_ID1_EN_RD SEC_ENG_SE_CDET_ID1_EN_RD -#define SEC_ENG_SE_CDET_ID1_EN_RD_POS (9U) -#define SEC_ENG_SE_CDET_ID1_EN_RD_LEN (1U) -#define SEC_ENG_SE_CDET_ID1_EN_RD_MSK (((1U << SEC_ENG_SE_CDET_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_CDET_ID1_EN_RD_POS) -#define SEC_ENG_SE_CDET_ID1_EN_RD_UMSK (~(((1U << SEC_ENG_SE_CDET_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_CDET_ID1_EN_RD_POS)) -#define SEC_ENG_SE_GMAC_ID0_EN_RD SEC_ENG_SE_GMAC_ID0_EN_RD -#define SEC_ENG_SE_GMAC_ID0_EN_RD_POS (10U) -#define SEC_ENG_SE_GMAC_ID0_EN_RD_LEN (1U) -#define SEC_ENG_SE_GMAC_ID0_EN_RD_MSK (((1U << SEC_ENG_SE_GMAC_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_GMAC_ID0_EN_RD_POS) -#define SEC_ENG_SE_GMAC_ID0_EN_RD_UMSK (~(((1U << SEC_ENG_SE_GMAC_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_GMAC_ID0_EN_RD_POS)) -#define SEC_ENG_SE_GMAC_ID1_EN_RD SEC_ENG_SE_GMAC_ID1_EN_RD -#define SEC_ENG_SE_GMAC_ID1_EN_RD_POS (11U) -#define SEC_ENG_SE_GMAC_ID1_EN_RD_LEN (1U) -#define SEC_ENG_SE_GMAC_ID1_EN_RD_MSK (((1U << SEC_ENG_SE_GMAC_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_GMAC_ID1_EN_RD_POS) -#define SEC_ENG_SE_GMAC_ID1_EN_RD_UMSK (~(((1U << SEC_ENG_SE_GMAC_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_GMAC_ID1_EN_RD_POS)) -#define SEC_ENG_SE_DBG_DIS SEC_ENG_SE_DBG_DIS -#define SEC_ENG_SE_DBG_DIS_POS (31U) -#define SEC_ENG_SE_DBG_DIS_LEN (1U) -#define SEC_ENG_SE_DBG_DIS_MSK (((1U << SEC_ENG_SE_DBG_DIS_LEN) - 1) << SEC_ENG_SE_DBG_DIS_POS) -#define SEC_ENG_SE_DBG_DIS_UMSK (~(((1U << SEC_ENG_SE_DBG_DIS_LEN) - 1) << SEC_ENG_SE_DBG_DIS_POS)) - -/* 0xF04 : se_ctrl_reserved_0 */ -#define SEC_ENG_SE_CTRL_RESERVED_0_OFFSET (0xF04) -#define SEC_ENG_SE_CTRL_RESERVED_0 SEC_ENG_SE_CTRL_RESERVED_0 -#define SEC_ENG_SE_CTRL_RESERVED_0_POS (0U) -#define SEC_ENG_SE_CTRL_RESERVED_0_LEN (32U) -#define SEC_ENG_SE_CTRL_RESERVED_0_MSK (((1U << SEC_ENG_SE_CTRL_RESERVED_0_LEN) - 1) << SEC_ENG_SE_CTRL_RESERVED_0_POS) -#define SEC_ENG_SE_CTRL_RESERVED_0_UMSK (~(((1U << SEC_ENG_SE_CTRL_RESERVED_0_LEN) - 1) << SEC_ENG_SE_CTRL_RESERVED_0_POS)) - -/* 0xF08 : se_ctrl_reserved_1 */ -#define SEC_ENG_SE_CTRL_RESERVED_1_OFFSET (0xF08) -#define SEC_ENG_SE_CTRL_RESERVED_1 SEC_ENG_SE_CTRL_RESERVED_1 -#define SEC_ENG_SE_CTRL_RESERVED_1_POS (0U) -#define SEC_ENG_SE_CTRL_RESERVED_1_LEN (32U) -#define SEC_ENG_SE_CTRL_RESERVED_1_MSK (((1U << SEC_ENG_SE_CTRL_RESERVED_1_LEN) - 1) << SEC_ENG_SE_CTRL_RESERVED_1_POS) -#define SEC_ENG_SE_CTRL_RESERVED_1_UMSK (~(((1U << SEC_ENG_SE_CTRL_RESERVED_1_LEN) - 1) << SEC_ENG_SE_CTRL_RESERVED_1_POS)) - -/* 0xF0C : se_ctrl_reserved_2 */ -#define SEC_ENG_SE_CTRL_RESERVED_2_OFFSET (0xF0C) -#define SEC_ENG_SE_CTRL_RESERVED_2 SEC_ENG_SE_CTRL_RESERVED_2 -#define SEC_ENG_SE_CTRL_RESERVED_2_POS (0U) -#define SEC_ENG_SE_CTRL_RESERVED_2_LEN (32U) -#define SEC_ENG_SE_CTRL_RESERVED_2_MSK (((1U << SEC_ENG_SE_CTRL_RESERVED_2_LEN) - 1) << SEC_ENG_SE_CTRL_RESERVED_2_POS) -#define SEC_ENG_SE_CTRL_RESERVED_2_UMSK (~(((1U << SEC_ENG_SE_CTRL_RESERVED_2_LEN) - 1) << SEC_ENG_SE_CTRL_RESERVED_2_POS)) - -struct sec_eng_reg { - /* 0x0 : se_sha_0_ctrl */ - union { - struct { - uint32_t se_sha_0_busy : 1; /* [ 0], r, 0x0 */ - uint32_t se_sha_0_trig_1t : 1; /* [ 1], w1p, 0x0 */ - uint32_t se_sha_0_mode : 3; /* [ 4: 2], r/w, 0x0 */ - uint32_t se_sha_0_en : 1; /* [ 5], r/w, 0x0 */ - uint32_t se_sha_0_hash_sel : 1; /* [ 6], r/w, 0x0 */ - uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ - uint32_t se_sha_0_int : 1; /* [ 8], r, 0x0 */ - uint32_t se_sha_0_int_clr_1t : 1; /* [ 9], w1p, 0x0 */ - uint32_t se_sha_0_int_set_1t : 1; /* [ 10], w1p, 0x0 */ - uint32_t se_sha_0_int_mask : 1; /* [ 11], r/w, 0x0 */ - uint32_t se_sha_0_mode_ext : 2; /* [13:12], r/w, 0x0 */ - uint32_t reserved_14 : 1; /* [ 14], rsvd, 0x0 */ - uint32_t se_sha_0_link_mode : 1; /* [ 15], r/w, 0x0 */ - uint32_t se_sha_0_msg_len : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } se_sha_0_ctrl; - - /* 0x4 : se_sha_0_msa */ - union { - struct { - uint32_t se_sha_0_msa : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } se_sha_0_msa; - - /* 0x8 : se_sha_0_status */ - union { - struct { - uint32_t se_sha_0_status : 32; /* [31: 0], r, 0x41 */ - } BF; - uint32_t WORD; - } se_sha_0_status; - - /* 0xC : se_sha_0_endian */ - union { - struct { - uint32_t se_sha_0_dout_endian : 1; /* [ 0], r/w, 0x1 */ - uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } se_sha_0_endian; - - /* 0x10 : se_sha_0_hash_l_0 */ - union { - struct { - uint32_t se_sha_0_hash_l_0 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_sha_0_hash_l_0; - - /* 0x14 : se_sha_0_hash_l_1 */ - union { - struct { - uint32_t se_sha_0_hash_l_1 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_sha_0_hash_l_1; - - /* 0x18 : se_sha_0_hash_l_2 */ - union { - struct { - uint32_t se_sha_0_hash_l_2 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_sha_0_hash_l_2; - - /* 0x1C : se_sha_0_hash_l_3 */ - union { - struct { - uint32_t se_sha_0_hash_l_3 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_sha_0_hash_l_3; - - /* 0x20 : se_sha_0_hash_l_4 */ - union { - struct { - uint32_t se_sha_0_hash_l_4 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_sha_0_hash_l_4; - - /* 0x24 : se_sha_0_hash_l_5 */ - union { - struct { - uint32_t se_sha_0_hash_l_5 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_sha_0_hash_l_5; - - /* 0x28 : se_sha_0_hash_l_6 */ - union { - struct { - uint32_t se_sha_0_hash_l_6 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_sha_0_hash_l_6; - - /* 0x2C : se_sha_0_hash_l_7 */ - union { - struct { - uint32_t se_sha_0_hash_l_7 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_sha_0_hash_l_7; - - /* 0x30 : se_sha_0_hash_h_0 */ - union { - struct { - uint32_t se_sha_0_hash_h_0 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_sha_0_hash_h_0; - - /* 0x34 : se_sha_0_hash_h_1 */ - union { - struct { - uint32_t se_sha_0_hash_h_1 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_sha_0_hash_h_1; - - /* 0x38 : se_sha_0_hash_h_2 */ - union { - struct { - uint32_t se_sha_0_hash_h_2 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_sha_0_hash_h_2; - - /* 0x3C : se_sha_0_hash_h_3 */ - union { - struct { - uint32_t se_sha_0_hash_h_3 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_sha_0_hash_h_3; - - /* 0x40 : se_sha_0_hash_h_4 */ - union { - struct { - uint32_t se_sha_0_hash_h_4 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_sha_0_hash_h_4; - - /* 0x44 : se_sha_0_hash_h_5 */ - union { - struct { - uint32_t se_sha_0_hash_h_5 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_sha_0_hash_h_5; - - /* 0x48 : se_sha_0_hash_h_6 */ - union { - struct { - uint32_t se_sha_0_hash_h_6 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_sha_0_hash_h_6; - - /* 0x4C : se_sha_0_hash_h_7 */ - union { - struct { - uint32_t se_sha_0_hash_h_7 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_sha_0_hash_h_7; - - /* 0x50 : se_sha_0_link */ - union { - struct { - uint32_t se_sha_0_lca : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } se_sha_0_link; - - /* 0x54 reserved */ - uint8_t RESERVED0x54[168]; - - /* 0xFC : se_sha_0_ctrl_prot */ - union { - struct { - uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */ - uint32_t se_sha_id0_en : 1; /* [ 1], r/w, 0x1 */ - uint32_t se_sha_id1_en : 1; /* [ 2], r/w, 0x1 */ - uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } se_sha_0_ctrl_prot; - - /* 0x100 : se_aes_0_ctrl */ - union { - struct { - uint32_t se_aes_0_busy : 1; /* [ 0], r, 0x0 */ - uint32_t se_aes_0_trig_1t : 1; /* [ 1], w1p, 0x0 */ - uint32_t se_aes_0_en : 1; /* [ 2], r/w, 0x0 */ - uint32_t se_aes_0_mode : 2; /* [ 4: 3], r/w, 0x0 */ - uint32_t se_aes_0_dec_en : 1; /* [ 5], r/w, 0x0 */ - uint32_t se_aes_0_dec_key_sel : 1; /* [ 6], r/w, 0x0 */ - uint32_t se_aes_0_hw_key_en : 1; /* [ 7], r/w, 0x0 */ - uint32_t se_aes_0_int : 1; /* [ 8], r, 0x0 */ - uint32_t se_aes_0_int_clr_1t : 1; /* [ 9], w1p, 0x0 */ - uint32_t se_aes_0_int_set_1t : 1; /* [ 10], w1p, 0x0 */ - uint32_t se_aes_0_int_mask : 1; /* [ 11], r/w, 0x0 */ - uint32_t se_aes_0_block_mode : 2; /* [13:12], r/w, 0x0 */ - uint32_t se_aes_0_iv_sel : 1; /* [ 14], r/w, 0x0 */ - uint32_t se_aes_0_link_mode : 1; /* [ 15], r/w, 0x0 */ - uint32_t se_aes_0_msg_len : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } se_aes_0_ctrl; - - /* 0x104 : se_aes_0_msa */ - union { - struct { - uint32_t se_aes_0_msa : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } se_aes_0_msa; - - /* 0x108 : se_aes_0_mda */ - union { - struct { - uint32_t se_aes_0_mda : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } se_aes_0_mda; - - /* 0x10C : se_aes_0_status */ - union { - struct { - uint32_t se_aes_0_status : 32; /* [31: 0], r, 0x4100 */ - } BF; - uint32_t WORD; - } se_aes_0_status; - - /* 0x110 : se_aes_0_iv_0 */ - union { - struct { - uint32_t se_aes_0_iv_0 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } se_aes_0_iv_0; - - /* 0x114 : se_aes_0_iv_1 */ - union { - struct { - uint32_t se_aes_0_iv_1 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } se_aes_0_iv_1; - - /* 0x118 : se_aes_0_iv_2 */ - union { - struct { - uint32_t se_aes_0_iv_2 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } se_aes_0_iv_2; - - /* 0x11C : se_aes_0_iv_3 */ - union { - struct { - uint32_t se_aes_0_iv_3 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } se_aes_0_iv_3; - - /* 0x120 : se_aes_0_key_0 */ - union { - struct { - uint32_t se_aes_0_key_0 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } se_aes_0_key_0; - - /* 0x124 : se_aes_0_key_1 */ - union { - struct { - uint32_t se_aes_0_key_1 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } se_aes_0_key_1; - - /* 0x128 : se_aes_0_key_2 */ - union { - struct { - uint32_t se_aes_0_key_2 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } se_aes_0_key_2; - - /* 0x12C : se_aes_0_key_3 */ - union { - struct { - uint32_t se_aes_0_key_3 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } se_aes_0_key_3; - - /* 0x130 : se_aes_0_key_4 */ - union { - struct { - uint32_t se_aes_0_key_4 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } se_aes_0_key_4; - - /* 0x134 : se_aes_0_key_5 */ - union { - struct { - uint32_t se_aes_0_key_5 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } se_aes_0_key_5; - - /* 0x138 : se_aes_0_key_6 */ - union { - struct { - uint32_t se_aes_0_key_6 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } se_aes_0_key_6; - - /* 0x13C : se_aes_0_key_7 */ - union { - struct { - uint32_t se_aes_0_key_7 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } se_aes_0_key_7; - - /* 0x140 : se_aes_0_key_sel */ - union { - struct { - uint32_t se_aes_0_key_sel : 2; /* [ 1: 0], r/w, 0x0 */ - uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } se_aes_0_key_sel; - - /* 0x144 : se_aes_1_key_sel */ - union { - struct { - uint32_t se_aes_1_key_sel : 2; /* [ 1: 0], r/w, 0x0 */ - uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } se_aes_1_key_sel; - - /* 0x148 : se_aes_0_endian */ - union { - struct { - uint32_t se_aes_0_dout_endian : 1; /* [ 0], r/w, 0x1 */ - uint32_t se_aes_0_din_endian : 1; /* [ 1], r/w, 0x1 */ - uint32_t se_aes_0_key_endian : 1; /* [ 2], r/w, 0x1 */ - uint32_t se_aes_0_iv_endian : 1; /* [ 3], r/w, 0x1 */ - uint32_t se_aes_0_twk_endian : 1; /* [ 4], r/w, 0x1 */ - uint32_t reserved_5_29 : 25; /* [29: 5], rsvd, 0x0 */ - uint32_t se_aes_0_ctr_len : 2; /* [31:30], r/w, 0x0 */ - } BF; - uint32_t WORD; - } se_aes_0_endian; - - /* 0x14C : se_aes_sboot */ - union { - struct { - uint32_t se_aes_sboot_key_sel : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_14 : 14; /* [14: 1], rsvd, 0x0 */ - uint32_t se_aes_0_xts_mode : 1; /* [ 15], r/w, 0x0 */ - uint32_t se_aes_0_uni_len : 16; /* [31:16], r/w, 0x2 */ - } BF; - uint32_t WORD; - } se_aes_sboot; - - /* 0x150 : se_aes_0_link */ - union { - struct { - uint32_t se_aes_0_lca : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } se_aes_0_link; - - /* 0x154 reserved */ - uint8_t RESERVED0x154[168]; - - /* 0x1FC : se_aes_0_ctrl_prot */ - union { - struct { - uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */ - uint32_t se_aes_id0_en : 1; /* [ 1], r/w, 0x1 */ - uint32_t se_aes_id1_en : 1; /* [ 2], r/w, 0x1 */ - uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } se_aes_0_ctrl_prot; - - /* 0x200 : se_trng_0_ctrl_0 */ - union { - struct { - uint32_t se_trng_0_busy : 1; /* [ 0], r, 0x0 */ - uint32_t se_trng_0_trig_1t : 1; /* [ 1], w1p, 0x0 */ - uint32_t se_trng_0_en : 1; /* [ 2], r/w, 0x0 */ - uint32_t se_trng_0_dout_clr_1t : 1; /* [ 3], w1p, 0x0 */ - uint32_t se_trng_0_ht_error : 1; /* [ 4], r, 0x0 */ - uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ - uint32_t se_trng_0_int : 1; /* [ 8], r, 0x0 */ - uint32_t se_trng_0_int_clr_1t : 1; /* [ 9], w1p, 0x0 */ - uint32_t se_trng_0_int_set_1t : 1; /* [ 10], w1p, 0x0 */ - uint32_t se_trng_0_int_mask : 1; /* [ 11], r/w, 0x0 */ - uint32_t reserved_12 : 1; /* [ 12], rsvd, 0x0 */ - uint32_t se_trng_0_manual_fun_sel : 1; /* [ 13], r/w, 0x0 */ - uint32_t se_trng_0_manual_reseed : 1; /* [ 14], r/w, 0x0 */ - uint32_t se_trng_0_manual_en : 1; /* [ 15], r/w, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } se_trng_0_ctrl_0; - - /* 0x204 : se_trng_0_status */ - union { - struct { - uint32_t se_trng_0_status : 32; /* [31: 0], r, 0x100020 */ - } BF; - uint32_t WORD; - } se_trng_0_status; - - /* 0x208 : se_trng_0_dout_0 */ - union { - struct { - uint32_t se_trng_0_dout_0 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_trng_0_dout_0; - - /* 0x20C : se_trng_0_dout_1 */ - union { - struct { - uint32_t se_trng_0_dout_1 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_trng_0_dout_1; - - /* 0x210 : se_trng_0_dout_2 */ - union { - struct { - uint32_t se_trng_0_dout_2 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_trng_0_dout_2; - - /* 0x214 : se_trng_0_dout_3 */ - union { - struct { - uint32_t se_trng_0_dout_3 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_trng_0_dout_3; - - /* 0x218 : se_trng_0_dout_4 */ - union { - struct { - uint32_t se_trng_0_dout_4 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_trng_0_dout_4; - - /* 0x21C : se_trng_0_dout_5 */ - union { - struct { - uint32_t se_trng_0_dout_5 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_trng_0_dout_5; - - /* 0x220 : se_trng_0_dout_6 */ - union { - struct { - uint32_t se_trng_0_dout_6 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_trng_0_dout_6; - - /* 0x224 : se_trng_0_dout_7 */ - union { - struct { - uint32_t se_trng_0_dout_7 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_trng_0_dout_7; - - /* 0x228 : se_trng_0_test */ - union { - struct { - uint32_t se_trng_0_test_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t se_trng_0_cp_test_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t se_trng_0_cp_bypass : 1; /* [ 2], r/w, 0x0 */ - uint32_t se_trng_0_ht_dis : 1; /* [ 3], r/w, 0x0 */ - uint32_t se_trng_0_ht_alarm_n : 8; /* [11: 4], r/w, 0x0 */ - uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } se_trng_0_test; - - /* 0x22C : se_trng_0_ctrl_1 */ - union { - struct { - uint32_t se_trng_0_reseed_n_lsb : 32; /* [31: 0], r/w, 0xffff */ - } BF; - uint32_t WORD; - } se_trng_0_ctrl_1; - - /* 0x230 : se_trng_0_ctrl_2 */ - union { - struct { - uint32_t se_trng_0_reseed_n_msb : 16; /* [15: 0], r/w, 0xff */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } se_trng_0_ctrl_2; - - /* 0x234 : se_trng_0_ctrl_3 */ - union { - struct { - uint32_t se_trng_0_cp_ratio : 8; /* [ 7: 0], r/w, 0x3 */ - uint32_t se_trng_0_ht_rct_c : 8; /* [15: 8], r/w, 0x42 */ - uint32_t se_trng_0_ht_apt_c : 10; /* [25:16], r/w, 0x37a */ - uint32_t se_trng_0_ht_od_en : 1; /* [ 26], r/w, 0x0 */ - uint32_t reserved_27_30 : 4; /* [30:27], rsvd, 0x0 */ - uint32_t se_trng_0_rosc_en : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } se_trng_0_ctrl_3; - - /* 0x238 reserved */ - uint8_t RESERVED0x238[8]; - - /* 0x240 : se_trng_0_test_out_0 */ - union { - struct { - uint32_t se_trng_0_test_out_0 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_trng_0_test_out_0; - - /* 0x244 : se_trng_0_test_out_1 */ - union { - struct { - uint32_t se_trng_0_test_out_1 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_trng_0_test_out_1; - - /* 0x248 : se_trng_0_test_out_2 */ - union { - struct { - uint32_t se_trng_0_test_out_2 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_trng_0_test_out_2; - - /* 0x24C : se_trng_0_test_out_3 */ - union { - struct { - uint32_t se_trng_0_test_out_3 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_trng_0_test_out_3; - - /* 0x250 reserved */ - uint8_t RESERVED0x250[172]; - - /* 0x2FC : se_trng_0_ctrl_prot */ - union { - struct { - uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */ - uint32_t se_trng_id0_en : 1; /* [ 1], r/w, 0x1 */ - uint32_t se_trng_id1_en : 1; /* [ 2], r/w, 0x1 */ - uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } se_trng_0_ctrl_prot; - - /* 0x300 : se_pka_0_ctrl_0 */ - union { - struct { - uint32_t se_pka_0_done : 1; /* [ 0], r, 0x0 */ - uint32_t se_pka_0_done_clr_1t : 1; /* [ 1], w1p, 0x0 */ - uint32_t se_pka_0_busy : 1; /* [ 2], r, 0x0 */ - uint32_t se_pka_0_en : 1; /* [ 3], r/w, 0x0 */ - uint32_t se_pka_0_prot_md : 4; /* [ 7: 4], r/w, 0x0 */ - uint32_t se_pka_0_int : 1; /* [ 8], r, 0x0 */ - uint32_t se_pka_0_int_clr_1t : 1; /* [ 9], w1p, 0x0 */ - uint32_t se_pka_0_int_set : 1; /* [ 10], r/w, 0x0 */ - uint32_t se_pka_0_int_mask : 1; /* [ 11], r/w, 0x0 */ - uint32_t se_pka_0_endian : 1; /* [ 12], r/w, 0x0 */ - uint32_t se_pka_0_ram_clr_md : 1; /* [ 13], r/w, 0x0 */ - uint32_t reserved_14 : 1; /* [ 14], rsvd, 0x0 */ - uint32_t se_pka_0_status_clr_1t : 1; /* [ 15], w1p, 0x0 */ - uint32_t se_pka_0_status : 16; /* [31:16], r, 0x0 */ - } BF; - uint32_t WORD; - } se_pka_0_ctrl_0; - - /* 0x304 reserved */ - uint8_t RESERVED0x304[8]; - - /* 0x30C : se_pka_0_seed */ - union { - struct { - uint32_t se_pka_0_seed : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } se_pka_0_seed; - - /* 0x310 : se_pka_0_ctrl_1 */ - union { - struct { - uint32_t se_pka_0_hburst : 3; /* [ 2: 0], r/w, 0x5 */ - uint32_t se_pka_0_hbypass : 1; /* [ 3], r/w, 0x0 */ - uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } se_pka_0_ctrl_1; - - /* 0x314 reserved */ - uint8_t RESERVED0x314[44]; - - /* 0x340 : se_pka_0_rw */ - union { - struct { - uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } se_pka_0_rw; - - /* 0x344 reserved */ - uint8_t RESERVED0x344[28]; - - /* 0x360 : se_pka_0_rw_burst */ - union { - struct { - uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } se_pka_0_rw_burst; - - /* 0x364 reserved */ - uint8_t RESERVED0x364[152]; - - /* 0x3FC : se_pka_0_ctrl_prot */ - union { - struct { - uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */ - uint32_t se_pka_id0_en : 1; /* [ 1], r/w, 0x1 */ - uint32_t se_pka_id1_en : 1; /* [ 2], r/w, 0x1 */ - uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } se_pka_0_ctrl_prot; - - /* 0x400 : se_cdet_0_ctrl_0 */ - union { - struct { - uint32_t se_cdet_0_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t se_cdet_0_error : 1; /* [ 1], r, 0x0 */ - uint32_t se_cdet_0_status : 14; /* [15: 2], r, 0x1 */ - uint32_t se_cdet_0_g_loop_max : 8; /* [23:16], r/w, 0x64 */ - uint32_t se_cdet_0_g_loop_min : 8; /* [31:24], r/w, 0x21 */ - } BF; - uint32_t WORD; - } se_cdet_0_ctrl_0; - - /* 0x404 : se_cdet_0_ctrl_1 */ - union { - struct { - uint32_t se_cdet_0_t_loop_n : 8; /* [ 7: 0], r/w, 0x32 */ - uint32_t se_cdet_0_t_dly_n : 8; /* [15: 8], r/w, 0x3 */ - uint32_t se_cdet_0_g_slp_n : 8; /* [23:16], r/w, 0xff */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } se_cdet_0_ctrl_1; - - /* 0x408 reserved */ - uint8_t RESERVED0x408[244]; - - /* 0x4FC : se_cdet_0_ctrl_prot */ - union { - struct { - uint32_t se_cdet_prot_en : 1; /* [ 0], r/w, 0x1 */ - uint32_t se_cdet_id0_en : 1; /* [ 1], r/w, 0x1 */ - uint32_t se_cdet_id1_en : 1; /* [ 2], r/w, 0x1 */ - uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } se_cdet_0_ctrl_prot; - - /* 0x500 : se_gmac_0_ctrl_0 */ - union { - struct { - uint32_t se_gmac_0_busy : 1; /* [ 0], r, 0x0 */ - uint32_t se_gmac_0_trig_1t : 1; /* [ 1], w1p, 0x0 */ - uint32_t se_gmac_0_en : 1; /* [ 2], r/w, 0x0 */ - uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */ - uint32_t se_gmac_0_int : 1; /* [ 8], r, 0x0 */ - uint32_t se_gmac_0_int_clr_1t : 1; /* [ 9], w1p, 0x0 */ - uint32_t se_gmac_0_int_set_1t : 1; /* [ 10], w1p, 0x0 */ - uint32_t se_gmac_0_int_mask : 1; /* [ 11], r/w, 0x0 */ - uint32_t se_gmac_0_t_endian : 1; /* [ 12], r/w, 0x1 */ - uint32_t se_gmac_0_h_endian : 1; /* [ 13], r/w, 0x1 */ - uint32_t se_gmac_0_x_endian : 1; /* [ 14], r/w, 0x1 */ - uint32_t reserved_15_31 : 17; /* [31:15], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } se_gmac_0_ctrl_0; - - /* 0x504 : se_gmac_0_lca */ - union { - struct { - uint32_t se_gmac_0_lca : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } se_gmac_0_lca; - - /* 0x508 : se_gmac_0_status */ - union { - struct { - uint32_t se_gmac_0_status : 32; /* [31: 0], r, 0xf1000000 */ - } BF; - uint32_t WORD; - } se_gmac_0_status; - - /* 0x50c reserved */ - uint8_t RESERVED0x50c[240]; - - /* 0x5FC : se_gmac_0_ctrl_prot */ - union { - struct { - uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */ - uint32_t se_gmac_id0_en : 1; /* [ 1], r/w, 0x1 */ - uint32_t se_gmac_id1_en : 1; /* [ 2], r/w, 0x1 */ - uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } se_gmac_0_ctrl_prot; - - /* 0x600 reserved */ - uint8_t RESERVED0x600[2304]; - - /* 0xF00 : se_ctrl_prot_rd */ - union { - struct { - uint32_t se_sha_id0_en_rd : 1; /* [ 0], r, 0x1 */ - uint32_t se_sha_id1_en_rd : 1; /* [ 1], r, 0x1 */ - uint32_t se_aes_id0_en_rd : 1; /* [ 2], r, 0x1 */ - uint32_t se_aes_id1_en_rd : 1; /* [ 3], r, 0x1 */ - uint32_t se_trng_id0_en_rd : 1; /* [ 4], r, 0x1 */ - uint32_t se_trng_id1_en_rd : 1; /* [ 5], r, 0x1 */ - uint32_t se_pka_id0_en_rd : 1; /* [ 6], r, 0x1 */ - uint32_t se_pka_id1_en_rd : 1; /* [ 7], r, 0x1 */ - uint32_t se_cdet_id0_en_rd : 1; /* [ 8], r, 0x1 */ - uint32_t se_cdet_id1_en_rd : 1; /* [ 9], r, 0x1 */ - uint32_t se_gmac_id0_en_rd : 1; /* [ 10], r, 0x1 */ - uint32_t se_gmac_id1_en_rd : 1; /* [ 11], r, 0x1 */ - uint32_t reserved_12_30 : 19; /* [30:12], rsvd, 0x0 */ - uint32_t se_dbg_dis : 1; /* [ 31], r, 0x0 */ - } BF; - uint32_t WORD; - } se_ctrl_prot_rd; - - /* 0xF04 : se_ctrl_reserved_0 */ - union { - struct { - uint32_t se_ctrl_reserved_0 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } se_ctrl_reserved_0; - - /* 0xF08 : se_ctrl_reserved_1 */ - union { - struct { - uint32_t se_ctrl_reserved_1 : 32; /* [31: 0], r/w, 0xffffffff */ - } BF; - uint32_t WORD; - } se_ctrl_reserved_1; - - /* 0xF0C : se_ctrl_reserved_2 */ - union { - struct { - uint32_t se_ctrl_reserved_2 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_ctrl_reserved_2; -}; - -typedef volatile struct sec_eng_reg sec_eng_reg_t; - -#endif /* __SEC_ENG_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/spi_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/spi_reg.h deleted file mode 100644 index f1e92fd357..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/spi_reg.h +++ /dev/null @@ -1,535 +0,0 @@ -/** - ****************************************************************************** - * @file spi_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __SPI_REG_H__ -#define __SPI_REG_H__ - -#include "bl808.h" - -/* 0x0 : spi_config */ -#define SPI_CONFIG_OFFSET (0x0) -#define SPI_CR_SPI_M_EN SPI_CR_SPI_M_EN -#define SPI_CR_SPI_M_EN_POS (0U) -#define SPI_CR_SPI_M_EN_LEN (1U) -#define SPI_CR_SPI_M_EN_MSK (((1U << SPI_CR_SPI_M_EN_LEN) - 1) << SPI_CR_SPI_M_EN_POS) -#define SPI_CR_SPI_M_EN_UMSK (~(((1U << SPI_CR_SPI_M_EN_LEN) - 1) << SPI_CR_SPI_M_EN_POS)) -#define SPI_CR_SPI_S_EN SPI_CR_SPI_S_EN -#define SPI_CR_SPI_S_EN_POS (1U) -#define SPI_CR_SPI_S_EN_LEN (1U) -#define SPI_CR_SPI_S_EN_MSK (((1U << SPI_CR_SPI_S_EN_LEN) - 1) << SPI_CR_SPI_S_EN_POS) -#define SPI_CR_SPI_S_EN_UMSK (~(((1U << SPI_CR_SPI_S_EN_LEN) - 1) << SPI_CR_SPI_S_EN_POS)) -#define SPI_CR_SPI_FRAME_SIZE SPI_CR_SPI_FRAME_SIZE -#define SPI_CR_SPI_FRAME_SIZE_POS (2U) -#define SPI_CR_SPI_FRAME_SIZE_LEN (2U) -#define SPI_CR_SPI_FRAME_SIZE_MSK (((1U << SPI_CR_SPI_FRAME_SIZE_LEN) - 1) << SPI_CR_SPI_FRAME_SIZE_POS) -#define SPI_CR_SPI_FRAME_SIZE_UMSK (~(((1U << SPI_CR_SPI_FRAME_SIZE_LEN) - 1) << SPI_CR_SPI_FRAME_SIZE_POS)) -#define SPI_CR_SPI_SCLK_POL SPI_CR_SPI_SCLK_POL -#define SPI_CR_SPI_SCLK_POL_POS (4U) -#define SPI_CR_SPI_SCLK_POL_LEN (1U) -#define SPI_CR_SPI_SCLK_POL_MSK (((1U << SPI_CR_SPI_SCLK_POL_LEN) - 1) << SPI_CR_SPI_SCLK_POL_POS) -#define SPI_CR_SPI_SCLK_POL_UMSK (~(((1U << SPI_CR_SPI_SCLK_POL_LEN) - 1) << SPI_CR_SPI_SCLK_POL_POS)) -#define SPI_CR_SPI_SCLK_PH SPI_CR_SPI_SCLK_PH -#define SPI_CR_SPI_SCLK_PH_POS (5U) -#define SPI_CR_SPI_SCLK_PH_LEN (1U) -#define SPI_CR_SPI_SCLK_PH_MSK (((1U << SPI_CR_SPI_SCLK_PH_LEN) - 1) << SPI_CR_SPI_SCLK_PH_POS) -#define SPI_CR_SPI_SCLK_PH_UMSK (~(((1U << SPI_CR_SPI_SCLK_PH_LEN) - 1) << SPI_CR_SPI_SCLK_PH_POS)) -#define SPI_CR_SPI_BIT_INV SPI_CR_SPI_BIT_INV -#define SPI_CR_SPI_BIT_INV_POS (6U) -#define SPI_CR_SPI_BIT_INV_LEN (1U) -#define SPI_CR_SPI_BIT_INV_MSK (((1U << SPI_CR_SPI_BIT_INV_LEN) - 1) << SPI_CR_SPI_BIT_INV_POS) -#define SPI_CR_SPI_BIT_INV_UMSK (~(((1U << SPI_CR_SPI_BIT_INV_LEN) - 1) << SPI_CR_SPI_BIT_INV_POS)) -#define SPI_CR_SPI_BYTE_INV SPI_CR_SPI_BYTE_INV -#define SPI_CR_SPI_BYTE_INV_POS (7U) -#define SPI_CR_SPI_BYTE_INV_LEN (1U) -#define SPI_CR_SPI_BYTE_INV_MSK (((1U << SPI_CR_SPI_BYTE_INV_LEN) - 1) << SPI_CR_SPI_BYTE_INV_POS) -#define SPI_CR_SPI_BYTE_INV_UMSK (~(((1U << SPI_CR_SPI_BYTE_INV_LEN) - 1) << SPI_CR_SPI_BYTE_INV_POS)) -#define SPI_CR_SPI_RXD_IGNR_EN SPI_CR_SPI_RXD_IGNR_EN -#define SPI_CR_SPI_RXD_IGNR_EN_POS (8U) -#define SPI_CR_SPI_RXD_IGNR_EN_LEN (1U) -#define SPI_CR_SPI_RXD_IGNR_EN_MSK (((1U << SPI_CR_SPI_RXD_IGNR_EN_LEN) - 1) << SPI_CR_SPI_RXD_IGNR_EN_POS) -#define SPI_CR_SPI_RXD_IGNR_EN_UMSK (~(((1U << SPI_CR_SPI_RXD_IGNR_EN_LEN) - 1) << SPI_CR_SPI_RXD_IGNR_EN_POS)) -#define SPI_CR_SPI_M_CONT_EN SPI_CR_SPI_M_CONT_EN -#define SPI_CR_SPI_M_CONT_EN_POS (9U) -#define SPI_CR_SPI_M_CONT_EN_LEN (1U) -#define SPI_CR_SPI_M_CONT_EN_MSK (((1U << SPI_CR_SPI_M_CONT_EN_LEN) - 1) << SPI_CR_SPI_M_CONT_EN_POS) -#define SPI_CR_SPI_M_CONT_EN_UMSK (~(((1U << SPI_CR_SPI_M_CONT_EN_LEN) - 1) << SPI_CR_SPI_M_CONT_EN_POS)) -#define SPI_CR_SPI_S_3PIN_MODE SPI_CR_SPI_S_3PIN_MODE -#define SPI_CR_SPI_S_3PIN_MODE_POS (10U) -#define SPI_CR_SPI_S_3PIN_MODE_LEN (1U) -#define SPI_CR_SPI_S_3PIN_MODE_MSK (((1U << SPI_CR_SPI_S_3PIN_MODE_LEN) - 1) << SPI_CR_SPI_S_3PIN_MODE_POS) -#define SPI_CR_SPI_S_3PIN_MODE_UMSK (~(((1U << SPI_CR_SPI_S_3PIN_MODE_LEN) - 1) << SPI_CR_SPI_S_3PIN_MODE_POS)) -#define SPI_CR_SPI_DEG_EN SPI_CR_SPI_DEG_EN -#define SPI_CR_SPI_DEG_EN_POS (11U) -#define SPI_CR_SPI_DEG_EN_LEN (1U) -#define SPI_CR_SPI_DEG_EN_MSK (((1U << SPI_CR_SPI_DEG_EN_LEN) - 1) << SPI_CR_SPI_DEG_EN_POS) -#define SPI_CR_SPI_DEG_EN_UMSK (~(((1U << SPI_CR_SPI_DEG_EN_LEN) - 1) << SPI_CR_SPI_DEG_EN_POS)) -#define SPI_CR_SPI_DEG_CNT SPI_CR_SPI_DEG_CNT -#define SPI_CR_SPI_DEG_CNT_POS (12U) -#define SPI_CR_SPI_DEG_CNT_LEN (4U) -#define SPI_CR_SPI_DEG_CNT_MSK (((1U << SPI_CR_SPI_DEG_CNT_LEN) - 1) << SPI_CR_SPI_DEG_CNT_POS) -#define SPI_CR_SPI_DEG_CNT_UMSK (~(((1U << SPI_CR_SPI_DEG_CNT_LEN) - 1) << SPI_CR_SPI_DEG_CNT_POS)) - -/* 0x4 : spi_int_sts */ -#define SPI_INT_STS_OFFSET (0x4) -#define SPI_END_INT SPI_END_INT -#define SPI_END_INT_POS (0U) -#define SPI_END_INT_LEN (1U) -#define SPI_END_INT_MSK (((1U << SPI_END_INT_LEN) - 1) << SPI_END_INT_POS) -#define SPI_END_INT_UMSK (~(((1U << SPI_END_INT_LEN) - 1) << SPI_END_INT_POS)) -#define SPI_TXF_INT SPI_TXF_INT -#define SPI_TXF_INT_POS (1U) -#define SPI_TXF_INT_LEN (1U) -#define SPI_TXF_INT_MSK (((1U << SPI_TXF_INT_LEN) - 1) << SPI_TXF_INT_POS) -#define SPI_TXF_INT_UMSK (~(((1U << SPI_TXF_INT_LEN) - 1) << SPI_TXF_INT_POS)) -#define SPI_RXF_INT SPI_RXF_INT -#define SPI_RXF_INT_POS (2U) -#define SPI_RXF_INT_LEN (1U) -#define SPI_RXF_INT_MSK (((1U << SPI_RXF_INT_LEN) - 1) << SPI_RXF_INT_POS) -#define SPI_RXF_INT_UMSK (~(((1U << SPI_RXF_INT_LEN) - 1) << SPI_RXF_INT_POS)) -#define SPI_STO_INT SPI_STO_INT -#define SPI_STO_INT_POS (3U) -#define SPI_STO_INT_LEN (1U) -#define SPI_STO_INT_MSK (((1U << SPI_STO_INT_LEN) - 1) << SPI_STO_INT_POS) -#define SPI_STO_INT_UMSK (~(((1U << SPI_STO_INT_LEN) - 1) << SPI_STO_INT_POS)) -#define SPI_TXU_INT SPI_TXU_INT -#define SPI_TXU_INT_POS (4U) -#define SPI_TXU_INT_LEN (1U) -#define SPI_TXU_INT_MSK (((1U << SPI_TXU_INT_LEN) - 1) << SPI_TXU_INT_POS) -#define SPI_TXU_INT_UMSK (~(((1U << SPI_TXU_INT_LEN) - 1) << SPI_TXU_INT_POS)) -#define SPI_FER_INT SPI_FER_INT -#define SPI_FER_INT_POS (5U) -#define SPI_FER_INT_LEN (1U) -#define SPI_FER_INT_MSK (((1U << SPI_FER_INT_LEN) - 1) << SPI_FER_INT_POS) -#define SPI_FER_INT_UMSK (~(((1U << SPI_FER_INT_LEN) - 1) << SPI_FER_INT_POS)) -#define SPI_CR_SPI_END_MASK SPI_CR_SPI_END_MASK -#define SPI_CR_SPI_END_MASK_POS (8U) -#define SPI_CR_SPI_END_MASK_LEN (1U) -#define SPI_CR_SPI_END_MASK_MSK (((1U << SPI_CR_SPI_END_MASK_LEN) - 1) << SPI_CR_SPI_END_MASK_POS) -#define SPI_CR_SPI_END_MASK_UMSK (~(((1U << SPI_CR_SPI_END_MASK_LEN) - 1) << SPI_CR_SPI_END_MASK_POS)) -#define SPI_CR_SPI_TXF_MASK SPI_CR_SPI_TXF_MASK -#define SPI_CR_SPI_TXF_MASK_POS (9U) -#define SPI_CR_SPI_TXF_MASK_LEN (1U) -#define SPI_CR_SPI_TXF_MASK_MSK (((1U << SPI_CR_SPI_TXF_MASK_LEN) - 1) << SPI_CR_SPI_TXF_MASK_POS) -#define SPI_CR_SPI_TXF_MASK_UMSK (~(((1U << SPI_CR_SPI_TXF_MASK_LEN) - 1) << SPI_CR_SPI_TXF_MASK_POS)) -#define SPI_CR_SPI_RXF_MASK SPI_CR_SPI_RXF_MASK -#define SPI_CR_SPI_RXF_MASK_POS (10U) -#define SPI_CR_SPI_RXF_MASK_LEN (1U) -#define SPI_CR_SPI_RXF_MASK_MSK (((1U << SPI_CR_SPI_RXF_MASK_LEN) - 1) << SPI_CR_SPI_RXF_MASK_POS) -#define SPI_CR_SPI_RXF_MASK_UMSK (~(((1U << SPI_CR_SPI_RXF_MASK_LEN) - 1) << SPI_CR_SPI_RXF_MASK_POS)) -#define SPI_CR_SPI_STO_MASK SPI_CR_SPI_STO_MASK -#define SPI_CR_SPI_STO_MASK_POS (11U) -#define SPI_CR_SPI_STO_MASK_LEN (1U) -#define SPI_CR_SPI_STO_MASK_MSK (((1U << SPI_CR_SPI_STO_MASK_LEN) - 1) << SPI_CR_SPI_STO_MASK_POS) -#define SPI_CR_SPI_STO_MASK_UMSK (~(((1U << SPI_CR_SPI_STO_MASK_LEN) - 1) << SPI_CR_SPI_STO_MASK_POS)) -#define SPI_CR_SPI_TXU_MASK SPI_CR_SPI_TXU_MASK -#define SPI_CR_SPI_TXU_MASK_POS (12U) -#define SPI_CR_SPI_TXU_MASK_LEN (1U) -#define SPI_CR_SPI_TXU_MASK_MSK (((1U << SPI_CR_SPI_TXU_MASK_LEN) - 1) << SPI_CR_SPI_TXU_MASK_POS) -#define SPI_CR_SPI_TXU_MASK_UMSK (~(((1U << SPI_CR_SPI_TXU_MASK_LEN) - 1) << SPI_CR_SPI_TXU_MASK_POS)) -#define SPI_CR_SPI_FER_MASK SPI_CR_SPI_FER_MASK -#define SPI_CR_SPI_FER_MASK_POS (13U) -#define SPI_CR_SPI_FER_MASK_LEN (1U) -#define SPI_CR_SPI_FER_MASK_MSK (((1U << SPI_CR_SPI_FER_MASK_LEN) - 1) << SPI_CR_SPI_FER_MASK_POS) -#define SPI_CR_SPI_FER_MASK_UMSK (~(((1U << SPI_CR_SPI_FER_MASK_LEN) - 1) << SPI_CR_SPI_FER_MASK_POS)) -#define SPI_CR_SPI_END_CLR SPI_CR_SPI_END_CLR -#define SPI_CR_SPI_END_CLR_POS (16U) -#define SPI_CR_SPI_END_CLR_LEN (1U) -#define SPI_CR_SPI_END_CLR_MSK (((1U << SPI_CR_SPI_END_CLR_LEN) - 1) << SPI_CR_SPI_END_CLR_POS) -#define SPI_CR_SPI_END_CLR_UMSK (~(((1U << SPI_CR_SPI_END_CLR_LEN) - 1) << SPI_CR_SPI_END_CLR_POS)) -#define SPI_CR_SPI_STO_CLR SPI_CR_SPI_STO_CLR -#define SPI_CR_SPI_STO_CLR_POS (19U) -#define SPI_CR_SPI_STO_CLR_LEN (1U) -#define SPI_CR_SPI_STO_CLR_MSK (((1U << SPI_CR_SPI_STO_CLR_LEN) - 1) << SPI_CR_SPI_STO_CLR_POS) -#define SPI_CR_SPI_STO_CLR_UMSK (~(((1U << SPI_CR_SPI_STO_CLR_LEN) - 1) << SPI_CR_SPI_STO_CLR_POS)) -#define SPI_CR_SPI_TXU_CLR SPI_CR_SPI_TXU_CLR -#define SPI_CR_SPI_TXU_CLR_POS (20U) -#define SPI_CR_SPI_TXU_CLR_LEN (1U) -#define SPI_CR_SPI_TXU_CLR_MSK (((1U << SPI_CR_SPI_TXU_CLR_LEN) - 1) << SPI_CR_SPI_TXU_CLR_POS) -#define SPI_CR_SPI_TXU_CLR_UMSK (~(((1U << SPI_CR_SPI_TXU_CLR_LEN) - 1) << SPI_CR_SPI_TXU_CLR_POS)) -#define SPI_CR_SPI_END_EN SPI_CR_SPI_END_EN -#define SPI_CR_SPI_END_EN_POS (24U) -#define SPI_CR_SPI_END_EN_LEN (1U) -#define SPI_CR_SPI_END_EN_MSK (((1U << SPI_CR_SPI_END_EN_LEN) - 1) << SPI_CR_SPI_END_EN_POS) -#define SPI_CR_SPI_END_EN_UMSK (~(((1U << SPI_CR_SPI_END_EN_LEN) - 1) << SPI_CR_SPI_END_EN_POS)) -#define SPI_CR_SPI_TXF_EN SPI_CR_SPI_TXF_EN -#define SPI_CR_SPI_TXF_EN_POS (25U) -#define SPI_CR_SPI_TXF_EN_LEN (1U) -#define SPI_CR_SPI_TXF_EN_MSK (((1U << SPI_CR_SPI_TXF_EN_LEN) - 1) << SPI_CR_SPI_TXF_EN_POS) -#define SPI_CR_SPI_TXF_EN_UMSK (~(((1U << SPI_CR_SPI_TXF_EN_LEN) - 1) << SPI_CR_SPI_TXF_EN_POS)) -#define SPI_CR_SPI_RXF_EN SPI_CR_SPI_RXF_EN -#define SPI_CR_SPI_RXF_EN_POS (26U) -#define SPI_CR_SPI_RXF_EN_LEN (1U) -#define SPI_CR_SPI_RXF_EN_MSK (((1U << SPI_CR_SPI_RXF_EN_LEN) - 1) << SPI_CR_SPI_RXF_EN_POS) -#define SPI_CR_SPI_RXF_EN_UMSK (~(((1U << SPI_CR_SPI_RXF_EN_LEN) - 1) << SPI_CR_SPI_RXF_EN_POS)) -#define SPI_CR_SPI_STO_EN SPI_CR_SPI_STO_EN -#define SPI_CR_SPI_STO_EN_POS (27U) -#define SPI_CR_SPI_STO_EN_LEN (1U) -#define SPI_CR_SPI_STO_EN_MSK (((1U << SPI_CR_SPI_STO_EN_LEN) - 1) << SPI_CR_SPI_STO_EN_POS) -#define SPI_CR_SPI_STO_EN_UMSK (~(((1U << SPI_CR_SPI_STO_EN_LEN) - 1) << SPI_CR_SPI_STO_EN_POS)) -#define SPI_CR_SPI_TXU_EN SPI_CR_SPI_TXU_EN -#define SPI_CR_SPI_TXU_EN_POS (28U) -#define SPI_CR_SPI_TXU_EN_LEN (1U) -#define SPI_CR_SPI_TXU_EN_MSK (((1U << SPI_CR_SPI_TXU_EN_LEN) - 1) << SPI_CR_SPI_TXU_EN_POS) -#define SPI_CR_SPI_TXU_EN_UMSK (~(((1U << SPI_CR_SPI_TXU_EN_LEN) - 1) << SPI_CR_SPI_TXU_EN_POS)) -#define SPI_CR_SPI_FER_EN SPI_CR_SPI_FER_EN -#define SPI_CR_SPI_FER_EN_POS (29U) -#define SPI_CR_SPI_FER_EN_LEN (1U) -#define SPI_CR_SPI_FER_EN_MSK (((1U << SPI_CR_SPI_FER_EN_LEN) - 1) << SPI_CR_SPI_FER_EN_POS) -#define SPI_CR_SPI_FER_EN_UMSK (~(((1U << SPI_CR_SPI_FER_EN_LEN) - 1) << SPI_CR_SPI_FER_EN_POS)) - -/* 0x8 : spi_bus_busy */ -#define SPI_BUS_BUSY_OFFSET (0x8) -#define SPI_STS_SPI_BUS_BUSY SPI_STS_SPI_BUS_BUSY -#define SPI_STS_SPI_BUS_BUSY_POS (0U) -#define SPI_STS_SPI_BUS_BUSY_LEN (1U) -#define SPI_STS_SPI_BUS_BUSY_MSK (((1U << SPI_STS_SPI_BUS_BUSY_LEN) - 1) << SPI_STS_SPI_BUS_BUSY_POS) -#define SPI_STS_SPI_BUS_BUSY_UMSK (~(((1U << SPI_STS_SPI_BUS_BUSY_LEN) - 1) << SPI_STS_SPI_BUS_BUSY_POS)) - -/* 0x10 : spi_prd_0 */ -#define SPI_PRD_0_OFFSET (0x10) -#define SPI_CR_SPI_PRD_S SPI_CR_SPI_PRD_S -#define SPI_CR_SPI_PRD_S_POS (0U) -#define SPI_CR_SPI_PRD_S_LEN (8U) -#define SPI_CR_SPI_PRD_S_MSK (((1U << SPI_CR_SPI_PRD_S_LEN) - 1) << SPI_CR_SPI_PRD_S_POS) -#define SPI_CR_SPI_PRD_S_UMSK (~(((1U << SPI_CR_SPI_PRD_S_LEN) - 1) << SPI_CR_SPI_PRD_S_POS)) -#define SPI_CR_SPI_PRD_P SPI_CR_SPI_PRD_P -#define SPI_CR_SPI_PRD_P_POS (8U) -#define SPI_CR_SPI_PRD_P_LEN (8U) -#define SPI_CR_SPI_PRD_P_MSK (((1U << SPI_CR_SPI_PRD_P_LEN) - 1) << SPI_CR_SPI_PRD_P_POS) -#define SPI_CR_SPI_PRD_P_UMSK (~(((1U << SPI_CR_SPI_PRD_P_LEN) - 1) << SPI_CR_SPI_PRD_P_POS)) -#define SPI_CR_SPI_PRD_D_PH_0 SPI_CR_SPI_PRD_D_PH_0 -#define SPI_CR_SPI_PRD_D_PH_0_POS (16U) -#define SPI_CR_SPI_PRD_D_PH_0_LEN (8U) -#define SPI_CR_SPI_PRD_D_PH_0_MSK (((1U << SPI_CR_SPI_PRD_D_PH_0_LEN) - 1) << SPI_CR_SPI_PRD_D_PH_0_POS) -#define SPI_CR_SPI_PRD_D_PH_0_UMSK (~(((1U << SPI_CR_SPI_PRD_D_PH_0_LEN) - 1) << SPI_CR_SPI_PRD_D_PH_0_POS)) -#define SPI_CR_SPI_PRD_D_PH_1 SPI_CR_SPI_PRD_D_PH_1 -#define SPI_CR_SPI_PRD_D_PH_1_POS (24U) -#define SPI_CR_SPI_PRD_D_PH_1_LEN (8U) -#define SPI_CR_SPI_PRD_D_PH_1_MSK (((1U << SPI_CR_SPI_PRD_D_PH_1_LEN) - 1) << SPI_CR_SPI_PRD_D_PH_1_POS) -#define SPI_CR_SPI_PRD_D_PH_1_UMSK (~(((1U << SPI_CR_SPI_PRD_D_PH_1_LEN) - 1) << SPI_CR_SPI_PRD_D_PH_1_POS)) - -/* 0x14 : spi_prd_1 */ -#define SPI_PRD_1_OFFSET (0x14) -#define SPI_CR_SPI_PRD_I SPI_CR_SPI_PRD_I -#define SPI_CR_SPI_PRD_I_POS (0U) -#define SPI_CR_SPI_PRD_I_LEN (8U) -#define SPI_CR_SPI_PRD_I_MSK (((1U << SPI_CR_SPI_PRD_I_LEN) - 1) << SPI_CR_SPI_PRD_I_POS) -#define SPI_CR_SPI_PRD_I_UMSK (~(((1U << SPI_CR_SPI_PRD_I_LEN) - 1) << SPI_CR_SPI_PRD_I_POS)) - -/* 0x18 : spi_rxd_ignr */ -#define SPI_RXD_IGNR_OFFSET (0x18) -#define SPI_CR_SPI_RXD_IGNR_P SPI_CR_SPI_RXD_IGNR_P -#define SPI_CR_SPI_RXD_IGNR_P_POS (0U) -#define SPI_CR_SPI_RXD_IGNR_P_LEN (5U) -#define SPI_CR_SPI_RXD_IGNR_P_MSK (((1U << SPI_CR_SPI_RXD_IGNR_P_LEN) - 1) << SPI_CR_SPI_RXD_IGNR_P_POS) -#define SPI_CR_SPI_RXD_IGNR_P_UMSK (~(((1U << SPI_CR_SPI_RXD_IGNR_P_LEN) - 1) << SPI_CR_SPI_RXD_IGNR_P_POS)) -#define SPI_CR_SPI_RXD_IGNR_S SPI_CR_SPI_RXD_IGNR_S -#define SPI_CR_SPI_RXD_IGNR_S_POS (16U) -#define SPI_CR_SPI_RXD_IGNR_S_LEN (5U) -#define SPI_CR_SPI_RXD_IGNR_S_MSK (((1U << SPI_CR_SPI_RXD_IGNR_S_LEN) - 1) << SPI_CR_SPI_RXD_IGNR_S_POS) -#define SPI_CR_SPI_RXD_IGNR_S_UMSK (~(((1U << SPI_CR_SPI_RXD_IGNR_S_LEN) - 1) << SPI_CR_SPI_RXD_IGNR_S_POS)) - -/* 0x1C : spi_sto_value */ -#define SPI_STO_VALUE_OFFSET (0x1C) -#define SPI_CR_SPI_STO_VALUE SPI_CR_SPI_STO_VALUE -#define SPI_CR_SPI_STO_VALUE_POS (0U) -#define SPI_CR_SPI_STO_VALUE_LEN (12U) -#define SPI_CR_SPI_STO_VALUE_MSK (((1U << SPI_CR_SPI_STO_VALUE_LEN) - 1) << SPI_CR_SPI_STO_VALUE_POS) -#define SPI_CR_SPI_STO_VALUE_UMSK (~(((1U << SPI_CR_SPI_STO_VALUE_LEN) - 1) << SPI_CR_SPI_STO_VALUE_POS)) - -/* 0x80 : spi_fifo_config_0 */ -#define SPI_FIFO_CONFIG_0_OFFSET (0x80) -#define SPI_DMA_TX_EN SPI_DMA_TX_EN -#define SPI_DMA_TX_EN_POS (0U) -#define SPI_DMA_TX_EN_LEN (1U) -#define SPI_DMA_TX_EN_MSK (((1U << SPI_DMA_TX_EN_LEN) - 1) << SPI_DMA_TX_EN_POS) -#define SPI_DMA_TX_EN_UMSK (~(((1U << SPI_DMA_TX_EN_LEN) - 1) << SPI_DMA_TX_EN_POS)) -#define SPI_DMA_RX_EN SPI_DMA_RX_EN -#define SPI_DMA_RX_EN_POS (1U) -#define SPI_DMA_RX_EN_LEN (1U) -#define SPI_DMA_RX_EN_MSK (((1U << SPI_DMA_RX_EN_LEN) - 1) << SPI_DMA_RX_EN_POS) -#define SPI_DMA_RX_EN_UMSK (~(((1U << SPI_DMA_RX_EN_LEN) - 1) << SPI_DMA_RX_EN_POS)) -#define SPI_TX_FIFO_CLR SPI_TX_FIFO_CLR -#define SPI_TX_FIFO_CLR_POS (2U) -#define SPI_TX_FIFO_CLR_LEN (1U) -#define SPI_TX_FIFO_CLR_MSK (((1U << SPI_TX_FIFO_CLR_LEN) - 1) << SPI_TX_FIFO_CLR_POS) -#define SPI_TX_FIFO_CLR_UMSK (~(((1U << SPI_TX_FIFO_CLR_LEN) - 1) << SPI_TX_FIFO_CLR_POS)) -#define SPI_RX_FIFO_CLR SPI_RX_FIFO_CLR -#define SPI_RX_FIFO_CLR_POS (3U) -#define SPI_RX_FIFO_CLR_LEN (1U) -#define SPI_RX_FIFO_CLR_MSK (((1U << SPI_RX_FIFO_CLR_LEN) - 1) << SPI_RX_FIFO_CLR_POS) -#define SPI_RX_FIFO_CLR_UMSK (~(((1U << SPI_RX_FIFO_CLR_LEN) - 1) << SPI_RX_FIFO_CLR_POS)) -#define SPI_TX_FIFO_OVERFLOW SPI_TX_FIFO_OVERFLOW -#define SPI_TX_FIFO_OVERFLOW_POS (4U) -#define SPI_TX_FIFO_OVERFLOW_LEN (1U) -#define SPI_TX_FIFO_OVERFLOW_MSK (((1U << SPI_TX_FIFO_OVERFLOW_LEN) - 1) << SPI_TX_FIFO_OVERFLOW_POS) -#define SPI_TX_FIFO_OVERFLOW_UMSK (~(((1U << SPI_TX_FIFO_OVERFLOW_LEN) - 1) << SPI_TX_FIFO_OVERFLOW_POS)) -#define SPI_TX_FIFO_UNDERFLOW SPI_TX_FIFO_UNDERFLOW -#define SPI_TX_FIFO_UNDERFLOW_POS (5U) -#define SPI_TX_FIFO_UNDERFLOW_LEN (1U) -#define SPI_TX_FIFO_UNDERFLOW_MSK (((1U << SPI_TX_FIFO_UNDERFLOW_LEN) - 1) << SPI_TX_FIFO_UNDERFLOW_POS) -#define SPI_TX_FIFO_UNDERFLOW_UMSK (~(((1U << SPI_TX_FIFO_UNDERFLOW_LEN) - 1) << SPI_TX_FIFO_UNDERFLOW_POS)) -#define SPI_RX_FIFO_OVERFLOW SPI_RX_FIFO_OVERFLOW -#define SPI_RX_FIFO_OVERFLOW_POS (6U) -#define SPI_RX_FIFO_OVERFLOW_LEN (1U) -#define SPI_RX_FIFO_OVERFLOW_MSK (((1U << SPI_RX_FIFO_OVERFLOW_LEN) - 1) << SPI_RX_FIFO_OVERFLOW_POS) -#define SPI_RX_FIFO_OVERFLOW_UMSK (~(((1U << SPI_RX_FIFO_OVERFLOW_LEN) - 1) << SPI_RX_FIFO_OVERFLOW_POS)) -#define SPI_RX_FIFO_UNDERFLOW SPI_RX_FIFO_UNDERFLOW -#define SPI_RX_FIFO_UNDERFLOW_POS (7U) -#define SPI_RX_FIFO_UNDERFLOW_LEN (1U) -#define SPI_RX_FIFO_UNDERFLOW_MSK (((1U << SPI_RX_FIFO_UNDERFLOW_LEN) - 1) << SPI_RX_FIFO_UNDERFLOW_POS) -#define SPI_RX_FIFO_UNDERFLOW_UMSK (~(((1U << SPI_RX_FIFO_UNDERFLOW_LEN) - 1) << SPI_RX_FIFO_UNDERFLOW_POS)) - -/* 0x84 : spi_fifo_config_1 */ -#define SPI_FIFO_CONFIG_1_OFFSET (0x84) -#define SPI_TX_FIFO_CNT SPI_TX_FIFO_CNT -#define SPI_TX_FIFO_CNT_POS (0U) -#define SPI_TX_FIFO_CNT_LEN (6U) -#define SPI_TX_FIFO_CNT_MSK (((1U << SPI_TX_FIFO_CNT_LEN) - 1) << SPI_TX_FIFO_CNT_POS) -#define SPI_TX_FIFO_CNT_UMSK (~(((1U << SPI_TX_FIFO_CNT_LEN) - 1) << SPI_TX_FIFO_CNT_POS)) -#define SPI_RX_FIFO_CNT SPI_RX_FIFO_CNT -#define SPI_RX_FIFO_CNT_POS (8U) -#define SPI_RX_FIFO_CNT_LEN (6U) -#define SPI_RX_FIFO_CNT_MSK (((1U << SPI_RX_FIFO_CNT_LEN) - 1) << SPI_RX_FIFO_CNT_POS) -#define SPI_RX_FIFO_CNT_UMSK (~(((1U << SPI_RX_FIFO_CNT_LEN) - 1) << SPI_RX_FIFO_CNT_POS)) -#define SPI_TX_FIFO_TH SPI_TX_FIFO_TH -#define SPI_TX_FIFO_TH_POS (16U) -#define SPI_TX_FIFO_TH_LEN (5U) -#define SPI_TX_FIFO_TH_MSK (((1U << SPI_TX_FIFO_TH_LEN) - 1) << SPI_TX_FIFO_TH_POS) -#define SPI_TX_FIFO_TH_UMSK (~(((1U << SPI_TX_FIFO_TH_LEN) - 1) << SPI_TX_FIFO_TH_POS)) -#define SPI_RX_FIFO_TH SPI_RX_FIFO_TH -#define SPI_RX_FIFO_TH_POS (24U) -#define SPI_RX_FIFO_TH_LEN (5U) -#define SPI_RX_FIFO_TH_MSK (((1U << SPI_RX_FIFO_TH_LEN) - 1) << SPI_RX_FIFO_TH_POS) -#define SPI_RX_FIFO_TH_UMSK (~(((1U << SPI_RX_FIFO_TH_LEN) - 1) << SPI_RX_FIFO_TH_POS)) - -/* 0x88 : spi_fifo_wdata */ -#define SPI_FIFO_WDATA_OFFSET (0x88) -#define SPI_FIFO_WDATA SPI_FIFO_WDATA -#define SPI_FIFO_WDATA_POS (0U) -#define SPI_FIFO_WDATA_LEN (32U) -#define SPI_FIFO_WDATA_MSK (((1U << SPI_FIFO_WDATA_LEN) - 1) << SPI_FIFO_WDATA_POS) -#define SPI_FIFO_WDATA_UMSK (~(((1U << SPI_FIFO_WDATA_LEN) - 1) << SPI_FIFO_WDATA_POS)) - -/* 0x8C : spi_fifo_rdata */ -#define SPI_FIFO_RDATA_OFFSET (0x8C) -#define SPI_FIFO_RDATA SPI_FIFO_RDATA -#define SPI_FIFO_RDATA_POS (0U) -#define SPI_FIFO_RDATA_LEN (32U) -#define SPI_FIFO_RDATA_MSK (((1U << SPI_FIFO_RDATA_LEN) - 1) << SPI_FIFO_RDATA_POS) -#define SPI_FIFO_RDATA_UMSK (~(((1U << SPI_FIFO_RDATA_LEN) - 1) << SPI_FIFO_RDATA_POS)) - -/* 0xFC : backup_io_en */ -#define SPI_BACKUP_IO_EN_OFFSET (0xFC) -#define SPI_BACKUP_IO_EN SPI_BACKUP_IO_EN -#define SPI_BACKUP_IO_EN_POS (0U) -#define SPI_BACKUP_IO_EN_LEN (1U) -#define SPI_BACKUP_IO_EN_MSK (((1U << SPI_BACKUP_IO_EN_LEN) - 1) << SPI_BACKUP_IO_EN_POS) -#define SPI_BACKUP_IO_EN_UMSK (~(((1U << SPI_BACKUP_IO_EN_LEN) - 1) << SPI_BACKUP_IO_EN_POS)) - -struct spi_reg { - /* 0x0 : spi_config */ - union { - struct { - uint32_t cr_spi_m_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t cr_spi_s_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t cr_spi_frame_size : 2; /* [ 3: 2], r/w, 0x0 */ - uint32_t cr_spi_sclk_pol : 1; /* [ 4], r/w, 0x0 */ - uint32_t cr_spi_sclk_ph : 1; /* [ 5], r/w, 0x0 */ - uint32_t cr_spi_bit_inv : 1; /* [ 6], r/w, 0x0 */ - uint32_t cr_spi_byte_inv : 1; /* [ 7], r/w, 0x0 */ - uint32_t cr_spi_rxd_ignr_en : 1; /* [ 8], r/w, 0x0 */ - uint32_t cr_spi_m_cont_en : 1; /* [ 9], r/w, 0x0 */ - uint32_t cr_spi_s_3pin_mode : 1; /* [ 10], r/w, 0x0 */ - uint32_t cr_spi_deg_en : 1; /* [ 11], r/w, 0x0 */ - uint32_t cr_spi_deg_cnt : 4; /* [15:12], r/w, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } spi_config; - - /* 0x4 : spi_int_sts */ - union { - struct { - uint32_t spi_end_int : 1; /* [ 0], r, 0x0 */ - uint32_t spi_txf_int : 1; /* [ 1], r, 0x1 */ - uint32_t spi_rxf_int : 1; /* [ 2], r, 0x0 */ - uint32_t spi_sto_int : 1; /* [ 3], r, 0x0 */ - uint32_t spi_txu_int : 1; /* [ 4], r, 0x0 */ - uint32_t spi_fer_int : 1; /* [ 5], r, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t cr_spi_end_mask : 1; /* [ 8], r/w, 0x1 */ - uint32_t cr_spi_txf_mask : 1; /* [ 9], r/w, 0x1 */ - uint32_t cr_spi_rxf_mask : 1; /* [ 10], r/w, 0x1 */ - uint32_t cr_spi_sto_mask : 1; /* [ 11], r/w, 0x1 */ - uint32_t cr_spi_txu_mask : 1; /* [ 12], r/w, 0x1 */ - uint32_t cr_spi_fer_mask : 1; /* [ 13], r/w, 0x1 */ - uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ - uint32_t cr_spi_end_clr : 1; /* [ 16], w1c, 0x0 */ - uint32_t rsvd_17 : 1; /* [ 17], rsvd, 0x0 */ - uint32_t rsvd_18 : 1; /* [ 18], rsvd, 0x0 */ - uint32_t cr_spi_sto_clr : 1; /* [ 19], w1c, 0x0 */ - uint32_t cr_spi_txu_clr : 1; /* [ 20], w1c, 0x0 */ - uint32_t rsvd_21 : 1; /* [ 21], rsvd, 0x0 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t cr_spi_end_en : 1; /* [ 24], r/w, 0x1 */ - uint32_t cr_spi_txf_en : 1; /* [ 25], r/w, 0x1 */ - uint32_t cr_spi_rxf_en : 1; /* [ 26], r/w, 0x1 */ - uint32_t cr_spi_sto_en : 1; /* [ 27], r/w, 0x1 */ - uint32_t cr_spi_txu_en : 1; /* [ 28], r/w, 0x1 */ - uint32_t cr_spi_fer_en : 1; /* [ 29], r/w, 0x1 */ - uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } spi_int_sts; - - /* 0x8 : spi_bus_busy */ - union { - struct { - uint32_t sts_spi_bus_busy : 1; /* [ 0], r, 0x0 */ - uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } spi_bus_busy; - - /* 0xc reserved */ - uint8_t RESERVED0xc[4]; - - /* 0x10 : spi_prd_0 */ - union { - struct { - uint32_t cr_spi_prd_s : 8; /* [ 7: 0], r/w, 0xf */ - uint32_t cr_spi_prd_p : 8; /* [15: 8], r/w, 0xf */ - uint32_t cr_spi_prd_d_ph_0 : 8; /* [23:16], r/w, 0xf */ - uint32_t cr_spi_prd_d_ph_1 : 8; /* [31:24], r/w, 0xf */ - } BF; - uint32_t WORD; - } spi_prd_0; - - /* 0x14 : spi_prd_1 */ - union { - struct { - uint32_t cr_spi_prd_i : 8; /* [ 7: 0], r/w, 0xf */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } spi_prd_1; - - /* 0x18 : spi_rxd_ignr */ - union { - struct { - uint32_t cr_spi_rxd_ignr_p : 5; /* [ 4: 0], r/w, 0x0 */ - uint32_t reserved_5_15 : 11; /* [15: 5], rsvd, 0x0 */ - uint32_t cr_spi_rxd_ignr_s : 5; /* [20:16], r/w, 0x0 */ - uint32_t reserved_21_31 : 11; /* [31:21], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } spi_rxd_ignr; - - /* 0x1C : spi_sto_value */ - union { - struct { - uint32_t cr_spi_sto_value : 12; /* [11: 0], r/w, 0xfff */ - uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } spi_sto_value; - - /* 0x20 reserved */ - uint8_t RESERVED0x20[96]; - - /* 0x80 : spi_fifo_config_0 */ - union { - struct { - uint32_t spi_dma_tx_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t spi_dma_rx_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t tx_fifo_clr : 1; /* [ 2], w1c, 0x0 */ - uint32_t rx_fifo_clr : 1; /* [ 3], w1c, 0x0 */ - uint32_t tx_fifo_overflow : 1; /* [ 4], r, 0x0 */ - uint32_t tx_fifo_underflow : 1; /* [ 5], r, 0x0 */ - uint32_t rx_fifo_overflow : 1; /* [ 6], r, 0x0 */ - uint32_t rx_fifo_underflow : 1; /* [ 7], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } spi_fifo_config_0; - - /* 0x84 : spi_fifo_config_1 */ - union { - struct { - uint32_t tx_fifo_cnt : 6; /* [ 5: 0], r, 0x20 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t rx_fifo_cnt : 6; /* [13: 8], r, 0x0 */ - uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ - uint32_t tx_fifo_th : 5; /* [20:16], r/w, 0x0 */ - uint32_t reserved_21_23 : 3; /* [23:21], rsvd, 0x0 */ - uint32_t rx_fifo_th : 5; /* [28:24], r/w, 0x0 */ - uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } spi_fifo_config_1; - - /* 0x88 : spi_fifo_wdata */ - union { - struct { - uint32_t spi_fifo_wdata : 32; /* [31: 0], w, x */ - } BF; - uint32_t WORD; - } spi_fifo_wdata; - - /* 0x8C : spi_fifo_rdata */ - union { - struct { - uint32_t spi_fifo_rdata : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } spi_fifo_rdata; - - /* 0x90 reserved */ - uint8_t RESERVED0x90[108]; - - /* 0xFC : backup_io_en */ - union { - struct { - uint32_t backup_io_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } backup_io_en; -}; - -typedef volatile struct spi_reg spi_reg_t; - -#endif /* __SPI_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/timer_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/timer_reg.h deleted file mode 100644 index 9f07d690a2..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/timer_reg.h +++ /dev/null @@ -1,963 +0,0 @@ -/** - ****************************************************************************** - * @file timer_reg.h - * @version V1.0 - * @date 2022-03-03 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __TIMER_REG_H__ -#define __TIMER_REG_H__ - -#include "bl808.h" - -/* 0x0 : Timer Clock Source */ -#define TIMER_TCCR_OFFSET (0x0) -#define TIMER_CS_2 TIMER_CS_2 -#define TIMER_CS_2_POS (0U) -#define TIMER_CS_2_LEN (4U) -#define TIMER_CS_2_MSK (((1U << TIMER_CS_2_LEN) - 1) << TIMER_CS_2_POS) -#define TIMER_CS_2_UMSK (~(((1U << TIMER_CS_2_LEN) - 1) << TIMER_CS_2_POS)) -#define TIMER_CS_3 TIMER_CS_3 -#define TIMER_CS_3_POS (4U) -#define TIMER_CS_3_LEN (4U) -#define TIMER_CS_3_MSK (((1U << TIMER_CS_3_LEN) - 1) << TIMER_CS_3_POS) -#define TIMER_CS_3_UMSK (~(((1U << TIMER_CS_3_LEN) - 1) << TIMER_CS_3_POS)) -#define TIMER_CS_WDT TIMER_CS_WDT -#define TIMER_CS_WDT_POS (8U) -#define TIMER_CS_WDT_LEN (4U) -#define TIMER_CS_WDT_MSK (((1U << TIMER_CS_WDT_LEN) - 1) << TIMER_CS_WDT_POS) -#define TIMER_CS_WDT_UMSK (~(((1U << TIMER_CS_WDT_LEN) - 1) << TIMER_CS_WDT_POS)) -#define TIMER_TMR_RSV TIMER_TMR_RSV -#define TIMER_TMR_RSV_POS (16U) -#define TIMER_TMR_RSV_LEN (8U) -#define TIMER_TMR_RSV_MSK (((1U << TIMER_TMR_RSV_LEN) - 1) << TIMER_TMR_RSV_POS) -#define TIMER_TMR_RSV_UMSK (~(((1U << TIMER_TMR_RSV_LEN) - 1) << TIMER_TMR_RSV_POS)) -#define TIMER_ID TIMER_ID -#define TIMER_ID_POS (24U) -#define TIMER_ID_LEN (8U) -#define TIMER_ID_MSK (((1U << TIMER_ID_LEN) - 1) << TIMER_ID_POS) -#define TIMER_ID_UMSK (~(((1U << TIMER_ID_LEN) - 1) << TIMER_ID_POS)) - -/* 0x10 : Timer2 Match Value 0 */ -#define TIMER_TMR2_0_OFFSET (0x10) -#define TIMER_TMR2_0 TIMER_TMR2_0 -#define TIMER_TMR2_0_POS (0U) -#define TIMER_TMR2_0_LEN (32U) -#define TIMER_TMR2_0_MSK (((1U << TIMER_TMR2_0_LEN) - 1) << TIMER_TMR2_0_POS) -#define TIMER_TMR2_0_UMSK (~(((1U << TIMER_TMR2_0_LEN) - 1) << TIMER_TMR2_0_POS)) - -/* 0x14 : Timer2 Match Value 1 */ -#define TIMER_TMR2_1_OFFSET (0x14) -#define TIMER_TMR2_1 TIMER_TMR2_1 -#define TIMER_TMR2_1_POS (0U) -#define TIMER_TMR2_1_LEN (32U) -#define TIMER_TMR2_1_MSK (((1U << TIMER_TMR2_1_LEN) - 1) << TIMER_TMR2_1_POS) -#define TIMER_TMR2_1_UMSK (~(((1U << TIMER_TMR2_1_LEN) - 1) << TIMER_TMR2_1_POS)) - -/* 0x18 : Timer2 Match Value 2 */ -#define TIMER_TMR2_2_OFFSET (0x18) -#define TIMER_TMR2_2 TIMER_TMR2_2 -#define TIMER_TMR2_2_POS (0U) -#define TIMER_TMR2_2_LEN (32U) -#define TIMER_TMR2_2_MSK (((1U << TIMER_TMR2_2_LEN) - 1) << TIMER_TMR2_2_POS) -#define TIMER_TMR2_2_UMSK (~(((1U << TIMER_TMR2_2_LEN) - 1) << TIMER_TMR2_2_POS)) - -/* 0x1C : Timer3 Match Value 0 */ -#define TIMER_TMR3_0_OFFSET (0x1C) -#define TIMER_TMR3_0 TIMER_TMR3_0 -#define TIMER_TMR3_0_POS (0U) -#define TIMER_TMR3_0_LEN (32U) -#define TIMER_TMR3_0_MSK (((1U << TIMER_TMR3_0_LEN) - 1) << TIMER_TMR3_0_POS) -#define TIMER_TMR3_0_UMSK (~(((1U << TIMER_TMR3_0_LEN) - 1) << TIMER_TMR3_0_POS)) - -/* 0x20 : Timer3 Match Value 1 */ -#define TIMER_TMR3_1_OFFSET (0x20) -#define TIMER_TMR3_1 TIMER_TMR3_1 -#define TIMER_TMR3_1_POS (0U) -#define TIMER_TMR3_1_LEN (32U) -#define TIMER_TMR3_1_MSK (((1U << TIMER_TMR3_1_LEN) - 1) << TIMER_TMR3_1_POS) -#define TIMER_TMR3_1_UMSK (~(((1U << TIMER_TMR3_1_LEN) - 1) << TIMER_TMR3_1_POS)) - -/* 0x24 : Timer3 Match Value 2 */ -#define TIMER_TMR3_2_OFFSET (0x24) -#define TIMER_TMR3_2 TIMER_TMR3_2 -#define TIMER_TMR3_2_POS (0U) -#define TIMER_TMR3_2_LEN (32U) -#define TIMER_TMR3_2_MSK (((1U << TIMER_TMR3_2_LEN) - 1) << TIMER_TMR3_2_POS) -#define TIMER_TMR3_2_UMSK (~(((1U << TIMER_TMR3_2_LEN) - 1) << TIMER_TMR3_2_POS)) - -/* 0x2C : Timer2 Counter Value */ -#define TIMER_TCR2_OFFSET (0x2C) -#define TIMER_TCR2_CNT TIMER_TCR2_CNT -#define TIMER_TCR2_CNT_POS (0U) -#define TIMER_TCR2_CNT_LEN (32U) -#define TIMER_TCR2_CNT_MSK (((1U << TIMER_TCR2_CNT_LEN) - 1) << TIMER_TCR2_CNT_POS) -#define TIMER_TCR2_CNT_UMSK (~(((1U << TIMER_TCR2_CNT_LEN) - 1) << TIMER_TCR2_CNT_POS)) - -/* 0x30 : Timer3 Counter Value */ -#define TIMER_TCR3_OFFSET (0x30) -#define TIMER_TCR3_CNT TIMER_TCR3_CNT -#define TIMER_TCR3_CNT_POS (0U) -#define TIMER_TCR3_CNT_LEN (32U) -#define TIMER_TCR3_CNT_MSK (((1U << TIMER_TCR3_CNT_LEN) - 1) << TIMER_TCR3_CNT_POS) -#define TIMER_TCR3_CNT_UMSK (~(((1U << TIMER_TCR3_CNT_LEN) - 1) << TIMER_TCR3_CNT_POS)) - -/* 0x38 : Timer2 Match Status */ -#define TIMER_TSR2_OFFSET (0x38) -#define TIMER_TSR2_0 TIMER_TSR2_0 -#define TIMER_TSR2_0_POS (0U) -#define TIMER_TSR2_0_LEN (1U) -#define TIMER_TSR2_0_MSK (((1U << TIMER_TSR2_0_LEN) - 1) << TIMER_TSR2_0_POS) -#define TIMER_TSR2_0_UMSK (~(((1U << TIMER_TSR2_0_LEN) - 1) << TIMER_TSR2_0_POS)) -#define TIMER_TSR2_1 TIMER_TSR2_1 -#define TIMER_TSR2_1_POS (1U) -#define TIMER_TSR2_1_LEN (1U) -#define TIMER_TSR2_1_MSK (((1U << TIMER_TSR2_1_LEN) - 1) << TIMER_TSR2_1_POS) -#define TIMER_TSR2_1_UMSK (~(((1U << TIMER_TSR2_1_LEN) - 1) << TIMER_TSR2_1_POS)) -#define TIMER_TSR2_2 TIMER_TSR2_2 -#define TIMER_TSR2_2_POS (2U) -#define TIMER_TSR2_2_LEN (1U) -#define TIMER_TSR2_2_MSK (((1U << TIMER_TSR2_2_LEN) - 1) << TIMER_TSR2_2_POS) -#define TIMER_TSR2_2_UMSK (~(((1U << TIMER_TSR2_2_LEN) - 1) << TIMER_TSR2_2_POS)) - -/* 0x3C : Timer3 Match Status */ -#define TIMER_TSR3_OFFSET (0x3C) -#define TIMER_TSR3_0 TIMER_TSR3_0 -#define TIMER_TSR3_0_POS (0U) -#define TIMER_TSR3_0_LEN (1U) -#define TIMER_TSR3_0_MSK (((1U << TIMER_TSR3_0_LEN) - 1) << TIMER_TSR3_0_POS) -#define TIMER_TSR3_0_UMSK (~(((1U << TIMER_TSR3_0_LEN) - 1) << TIMER_TSR3_0_POS)) -#define TIMER_TSR3_1 TIMER_TSR3_1 -#define TIMER_TSR3_1_POS (1U) -#define TIMER_TSR3_1_LEN (1U) -#define TIMER_TSR3_1_MSK (((1U << TIMER_TSR3_1_LEN) - 1) << TIMER_TSR3_1_POS) -#define TIMER_TSR3_1_UMSK (~(((1U << TIMER_TSR3_1_LEN) - 1) << TIMER_TSR3_1_POS)) -#define TIMER_TSR3_2 TIMER_TSR3_2 -#define TIMER_TSR3_2_POS (2U) -#define TIMER_TSR3_2_LEN (1U) -#define TIMER_TSR3_2_MSK (((1U << TIMER_TSR3_2_LEN) - 1) << TIMER_TSR3_2_POS) -#define TIMER_TSR3_2_UMSK (~(((1U << TIMER_TSR3_2_LEN) - 1) << TIMER_TSR3_2_POS)) - -/* 0x44 : Timer2 Match Interrupt Enable */ -#define TIMER_TIER2_OFFSET (0x44) -#define TIMER_TIER2_0 TIMER_TIER2_0 -#define TIMER_TIER2_0_POS (0U) -#define TIMER_TIER2_0_LEN (1U) -#define TIMER_TIER2_0_MSK (((1U << TIMER_TIER2_0_LEN) - 1) << TIMER_TIER2_0_POS) -#define TIMER_TIER2_0_UMSK (~(((1U << TIMER_TIER2_0_LEN) - 1) << TIMER_TIER2_0_POS)) -#define TIMER_TIER2_1 TIMER_TIER2_1 -#define TIMER_TIER2_1_POS (1U) -#define TIMER_TIER2_1_LEN (1U) -#define TIMER_TIER2_1_MSK (((1U << TIMER_TIER2_1_LEN) - 1) << TIMER_TIER2_1_POS) -#define TIMER_TIER2_1_UMSK (~(((1U << TIMER_TIER2_1_LEN) - 1) << TIMER_TIER2_1_POS)) -#define TIMER_TIER2_2 TIMER_TIER2_2 -#define TIMER_TIER2_2_POS (2U) -#define TIMER_TIER2_2_LEN (1U) -#define TIMER_TIER2_2_MSK (((1U << TIMER_TIER2_2_LEN) - 1) << TIMER_TIER2_2_POS) -#define TIMER_TIER2_2_UMSK (~(((1U << TIMER_TIER2_2_LEN) - 1) << TIMER_TIER2_2_POS)) - -/* 0x48 : Timer3 Match Interrupt Enable */ -#define TIMER_TIER3_OFFSET (0x48) -#define TIMER_TIER3_0 TIMER_TIER3_0 -#define TIMER_TIER3_0_POS (0U) -#define TIMER_TIER3_0_LEN (1U) -#define TIMER_TIER3_0_MSK (((1U << TIMER_TIER3_0_LEN) - 1) << TIMER_TIER3_0_POS) -#define TIMER_TIER3_0_UMSK (~(((1U << TIMER_TIER3_0_LEN) - 1) << TIMER_TIER3_0_POS)) -#define TIMER_TIER3_1 TIMER_TIER3_1 -#define TIMER_TIER3_1_POS (1U) -#define TIMER_TIER3_1_LEN (1U) -#define TIMER_TIER3_1_MSK (((1U << TIMER_TIER3_1_LEN) - 1) << TIMER_TIER3_1_POS) -#define TIMER_TIER3_1_UMSK (~(((1U << TIMER_TIER3_1_LEN) - 1) << TIMER_TIER3_1_POS)) -#define TIMER_TIER3_2 TIMER_TIER3_2 -#define TIMER_TIER3_2_POS (2U) -#define TIMER_TIER3_2_LEN (1U) -#define TIMER_TIER3_2_MSK (((1U << TIMER_TIER3_2_LEN) - 1) << TIMER_TIER3_2_POS) -#define TIMER_TIER3_2_UMSK (~(((1U << TIMER_TIER3_2_LEN) - 1) << TIMER_TIER3_2_POS)) - -/* 0x50 : Timer2 Pre-Load Value */ -#define TIMER_TPLVR2_OFFSET (0x50) -#define TIMER_TPLVR2 TIMER_TPLVR2 -#define TIMER_TPLVR2_POS (0U) -#define TIMER_TPLVR2_LEN (32U) -#define TIMER_TPLVR2_MSK (((1U << TIMER_TPLVR2_LEN) - 1) << TIMER_TPLVR2_POS) -#define TIMER_TPLVR2_UMSK (~(((1U << TIMER_TPLVR2_LEN) - 1) << TIMER_TPLVR2_POS)) - -/* 0x54 : Timer3 Pre-Load Value */ -#define TIMER_TPLVR3_OFFSET (0x54) -#define TIMER_TPLVR3 TIMER_TPLVR3 -#define TIMER_TPLVR3_POS (0U) -#define TIMER_TPLVR3_LEN (32U) -#define TIMER_TPLVR3_MSK (((1U << TIMER_TPLVR3_LEN) - 1) << TIMER_TPLVR3_POS) -#define TIMER_TPLVR3_UMSK (~(((1U << TIMER_TPLVR3_LEN) - 1) << TIMER_TPLVR3_POS)) - -/* 0x5C : Timer2 Pre-Load Control */ -#define TIMER_TPLCR2_OFFSET (0x5C) -#define TIMER_TPLCR2 TIMER_TPLCR2 -#define TIMER_TPLCR2_POS (0U) -#define TIMER_TPLCR2_LEN (2U) -#define TIMER_TPLCR2_MSK (((1U << TIMER_TPLCR2_LEN) - 1) << TIMER_TPLCR2_POS) -#define TIMER_TPLCR2_UMSK (~(((1U << TIMER_TPLCR2_LEN) - 1) << TIMER_TPLCR2_POS)) - -/* 0x60 : Timer3 Pre-Load Control */ -#define TIMER_TPLCR3_OFFSET (0x60) -#define TIMER_TPLCR3 TIMER_TPLCR3 -#define TIMER_TPLCR3_POS (0U) -#define TIMER_TPLCR3_LEN (2U) -#define TIMER_TPLCR3_MSK (((1U << TIMER_TPLCR3_LEN) - 1) << TIMER_TPLCR3_POS) -#define TIMER_TPLCR3_UMSK (~(((1U << TIMER_TPLCR3_LEN) - 1) << TIMER_TPLCR3_POS)) - -/* 0x64 : Watch-dog reset/interrupt Mode */ -#define TIMER_WMER_OFFSET (0x64) -#define TIMER_WE TIMER_WE -#define TIMER_WE_POS (0U) -#define TIMER_WE_LEN (1U) -#define TIMER_WE_MSK (((1U << TIMER_WE_LEN) - 1) << TIMER_WE_POS) -#define TIMER_WE_UMSK (~(((1U << TIMER_WE_LEN) - 1) << TIMER_WE_POS)) -#define TIMER_WRIE TIMER_WRIE -#define TIMER_WRIE_POS (1U) -#define TIMER_WRIE_LEN (1U) -#define TIMER_WRIE_MSK (((1U << TIMER_WRIE_LEN) - 1) << TIMER_WRIE_POS) -#define TIMER_WRIE_UMSK (~(((1U << TIMER_WRIE_LEN) - 1) << TIMER_WRIE_POS)) - -/* 0x68 : Watch-dog Match Value */ -#define TIMER_WMR_OFFSET (0x68) -#define TIMER_WMR TIMER_WMR -#define TIMER_WMR_POS (0U) -#define TIMER_WMR_LEN (16U) -#define TIMER_WMR_MSK (((1U << TIMER_WMR_LEN) - 1) << TIMER_WMR_POS) -#define TIMER_WMR_UMSK (~(((1U << TIMER_WMR_LEN) - 1) << TIMER_WMR_POS)) -#define TIMER_WDT_ALIGN TIMER_WDT_ALIGN -#define TIMER_WDT_ALIGN_POS (16U) -#define TIMER_WDT_ALIGN_LEN (1U) -#define TIMER_WDT_ALIGN_MSK (((1U << TIMER_WDT_ALIGN_LEN) - 1) << TIMER_WDT_ALIGN_POS) -#define TIMER_WDT_ALIGN_UMSK (~(((1U << TIMER_WDT_ALIGN_LEN) - 1) << TIMER_WDT_ALIGN_POS)) - -/* 0x6C : Watch-dog Counter Value */ -#define TIMER_WVR_OFFSET (0x6C) -#define TIMER_WDT_CNT TIMER_WDT_CNT -#define TIMER_WDT_CNT_POS (0U) -#define TIMER_WDT_CNT_LEN (16U) -#define TIMER_WDT_CNT_MSK (((1U << TIMER_WDT_CNT_LEN) - 1) << TIMER_WDT_CNT_POS) -#define TIMER_WDT_CNT_UMSK (~(((1U << TIMER_WDT_CNT_LEN) - 1) << TIMER_WDT_CNT_POS)) - -/* 0x70 : Watch-dog Reset Status */ -#define TIMER_WSR_OFFSET (0x70) -#define TIMER_WTS TIMER_WTS -#define TIMER_WTS_POS (0U) -#define TIMER_WTS_LEN (1U) -#define TIMER_WTS_MSK (((1U << TIMER_WTS_LEN) - 1) << TIMER_WTS_POS) -#define TIMER_WTS_UMSK (~(((1U << TIMER_WTS_LEN) - 1) << TIMER_WTS_POS)) - -/* 0x78 : Timer2 Interrupt Clear */ -#define TIMER_TICR2_OFFSET (0x78) -#define TIMER_TCLR2_0 TIMER_TCLR2_0 -#define TIMER_TCLR2_0_POS (0U) -#define TIMER_TCLR2_0_LEN (1U) -#define TIMER_TCLR2_0_MSK (((1U << TIMER_TCLR2_0_LEN) - 1) << TIMER_TCLR2_0_POS) -#define TIMER_TCLR2_0_UMSK (~(((1U << TIMER_TCLR2_0_LEN) - 1) << TIMER_TCLR2_0_POS)) -#define TIMER_TCLR2_1 TIMER_TCLR2_1 -#define TIMER_TCLR2_1_POS (1U) -#define TIMER_TCLR2_1_LEN (1U) -#define TIMER_TCLR2_1_MSK (((1U << TIMER_TCLR2_1_LEN) - 1) << TIMER_TCLR2_1_POS) -#define TIMER_TCLR2_1_UMSK (~(((1U << TIMER_TCLR2_1_LEN) - 1) << TIMER_TCLR2_1_POS)) -#define TIMER_TCLR2_2 TIMER_TCLR2_2 -#define TIMER_TCLR2_2_POS (2U) -#define TIMER_TCLR2_2_LEN (1U) -#define TIMER_TCLR2_2_MSK (((1U << TIMER_TCLR2_2_LEN) - 1) << TIMER_TCLR2_2_POS) -#define TIMER_TCLR2_2_UMSK (~(((1U << TIMER_TCLR2_2_LEN) - 1) << TIMER_TCLR2_2_POS)) - -/* 0x7C : Timer3 Interrupt Clear */ -#define TIMER_TICR3_OFFSET (0x7C) -#define TIMER_TCLR3_0 TIMER_TCLR3_0 -#define TIMER_TCLR3_0_POS (0U) -#define TIMER_TCLR3_0_LEN (1U) -#define TIMER_TCLR3_0_MSK (((1U << TIMER_TCLR3_0_LEN) - 1) << TIMER_TCLR3_0_POS) -#define TIMER_TCLR3_0_UMSK (~(((1U << TIMER_TCLR3_0_LEN) - 1) << TIMER_TCLR3_0_POS)) -#define TIMER_TCLR3_1 TIMER_TCLR3_1 -#define TIMER_TCLR3_1_POS (1U) -#define TIMER_TCLR3_1_LEN (1U) -#define TIMER_TCLR3_1_MSK (((1U << TIMER_TCLR3_1_LEN) - 1) << TIMER_TCLR3_1_POS) -#define TIMER_TCLR3_1_UMSK (~(((1U << TIMER_TCLR3_1_LEN) - 1) << TIMER_TCLR3_1_POS)) -#define TIMER_TCLR3_2 TIMER_TCLR3_2 -#define TIMER_TCLR3_2_POS (2U) -#define TIMER_TCLR3_2_LEN (1U) -#define TIMER_TCLR3_2_MSK (((1U << TIMER_TCLR3_2_LEN) - 1) << TIMER_TCLR3_2_POS) -#define TIMER_TCLR3_2_UMSK (~(((1U << TIMER_TCLR3_2_LEN) - 1) << TIMER_TCLR3_2_POS)) - -/* 0x80 : WDT Interrupt Clear */ -#define TIMER_WICR_OFFSET (0x80) -#define TIMER_WICLR TIMER_WICLR -#define TIMER_WICLR_POS (0U) -#define TIMER_WICLR_LEN (1U) -#define TIMER_WICLR_MSK (((1U << TIMER_WICLR_LEN) - 1) << TIMER_WICLR_POS) -#define TIMER_WICLR_UMSK (~(((1U << TIMER_WICLR_LEN) - 1) << TIMER_WICLR_POS)) - -/* 0x84 : Timer Counter Enable/Clear */ -#define TIMER_TCER_OFFSET (0x84) -#define TIMER2_EN TIMER2_EN -#define TIMER2_EN_POS (1U) -#define TIMER2_EN_LEN (1U) -#define TIMER2_EN_MSK (((1U << TIMER2_EN_LEN) - 1) << TIMER2_EN_POS) -#define TIMER2_EN_UMSK (~(((1U << TIMER2_EN_LEN) - 1) << TIMER2_EN_POS)) -#define TIMER3_EN TIMER3_EN -#define TIMER3_EN_POS (2U) -#define TIMER3_EN_LEN (1U) -#define TIMER3_EN_MSK (((1U << TIMER3_EN_LEN) - 1) << TIMER3_EN_POS) -#define TIMER3_EN_UMSK (~(((1U << TIMER3_EN_LEN) - 1) << TIMER3_EN_POS)) -#define TIMER_TCR2_CNT_CLR TIMER_TCR2_CNT_CLR -#define TIMER_TCR2_CNT_CLR_POS (5U) -#define TIMER_TCR2_CNT_CLR_LEN (1U) -#define TIMER_TCR2_CNT_CLR_MSK (((1U << TIMER_TCR2_CNT_CLR_LEN) - 1) << TIMER_TCR2_CNT_CLR_POS) -#define TIMER_TCR2_CNT_CLR_UMSK (~(((1U << TIMER_TCR2_CNT_CLR_LEN) - 1) << TIMER_TCR2_CNT_CLR_POS)) -#define TIMER_TCR3_CNT_CLR TIMER_TCR3_CNT_CLR -#define TIMER_TCR3_CNT_CLR_POS (6U) -#define TIMER_TCR3_CNT_CLR_LEN (1U) -#define TIMER_TCR3_CNT_CLR_MSK (((1U << TIMER_TCR3_CNT_CLR_LEN) - 1) << TIMER_TCR3_CNT_CLR_POS) -#define TIMER_TCR3_CNT_CLR_UMSK (~(((1U << TIMER_TCR3_CNT_CLR_LEN) - 1) << TIMER_TCR3_CNT_CLR_POS)) - -/* 0x88 : Timer Counter Mode */ -#define TIMER_TCMR_OFFSET (0x88) -#define TIMER2_MODE TIMER2_MODE -#define TIMER2_MODE_POS (1U) -#define TIMER2_MODE_LEN (1U) -#define TIMER2_MODE_MSK (((1U << TIMER2_MODE_LEN) - 1) << TIMER2_MODE_POS) -#define TIMER2_MODE_UMSK (~(((1U << TIMER2_MODE_LEN) - 1) << TIMER2_MODE_POS)) -#define TIMER3_MODE TIMER3_MODE -#define TIMER3_MODE_POS (2U) -#define TIMER3_MODE_LEN (1U) -#define TIMER3_MODE_MSK (((1U << TIMER3_MODE_LEN) - 1) << TIMER3_MODE_POS) -#define TIMER3_MODE_UMSK (~(((1U << TIMER3_MODE_LEN) - 1) << TIMER3_MODE_POS)) -#define TIMER2_ALIGN TIMER2_ALIGN -#define TIMER2_ALIGN_POS (5U) -#define TIMER2_ALIGN_LEN (1U) -#define TIMER2_ALIGN_MSK (((1U << TIMER2_ALIGN_LEN) - 1) << TIMER2_ALIGN_POS) -#define TIMER2_ALIGN_UMSK (~(((1U << TIMER2_ALIGN_LEN) - 1) << TIMER2_ALIGN_POS)) -#define TIMER3_ALIGN TIMER3_ALIGN -#define TIMER3_ALIGN_POS (6U) -#define TIMER3_ALIGN_LEN (1U) -#define TIMER3_ALIGN_MSK (((1U << TIMER3_ALIGN_LEN) - 1) << TIMER3_ALIGN_POS) -#define TIMER3_ALIGN_UMSK (~(((1U << TIMER3_ALIGN_LEN) - 1) << TIMER3_ALIGN_POS)) - -/* 0x90 : Timer2 Match Interrupt Mode */ -#define TIMER_TILR2_OFFSET (0x90) -#define TIMER_TILR2_0 TIMER_TILR2_0 -#define TIMER_TILR2_0_POS (0U) -#define TIMER_TILR2_0_LEN (1U) -#define TIMER_TILR2_0_MSK (((1U << TIMER_TILR2_0_LEN) - 1) << TIMER_TILR2_0_POS) -#define TIMER_TILR2_0_UMSK (~(((1U << TIMER_TILR2_0_LEN) - 1) << TIMER_TILR2_0_POS)) -#define TIMER_TILR2_1 TIMER_TILR2_1 -#define TIMER_TILR2_1_POS (1U) -#define TIMER_TILR2_1_LEN (1U) -#define TIMER_TILR2_1_MSK (((1U << TIMER_TILR2_1_LEN) - 1) << TIMER_TILR2_1_POS) -#define TIMER_TILR2_1_UMSK (~(((1U << TIMER_TILR2_1_LEN) - 1) << TIMER_TILR2_1_POS)) -#define TIMER_TILR2_2 TIMER_TILR2_2 -#define TIMER_TILR2_2_POS (2U) -#define TIMER_TILR2_2_LEN (1U) -#define TIMER_TILR2_2_MSK (((1U << TIMER_TILR2_2_LEN) - 1) << TIMER_TILR2_2_POS) -#define TIMER_TILR2_2_UMSK (~(((1U << TIMER_TILR2_2_LEN) - 1) << TIMER_TILR2_2_POS)) - -/* 0x94 : Timer3 Match Interrupt Mode */ -#define TIMER_TILR3_OFFSET (0x94) -#define TIMER_TILR3_0 TIMER_TILR3_0 -#define TIMER_TILR3_0_POS (0U) -#define TIMER_TILR3_0_LEN (1U) -#define TIMER_TILR3_0_MSK (((1U << TIMER_TILR3_0_LEN) - 1) << TIMER_TILR3_0_POS) -#define TIMER_TILR3_0_UMSK (~(((1U << TIMER_TILR3_0_LEN) - 1) << TIMER_TILR3_0_POS)) -#define TIMER_TILR3_1 TIMER_TILR3_1 -#define TIMER_TILR3_1_POS (1U) -#define TIMER_TILR3_1_LEN (1U) -#define TIMER_TILR3_1_MSK (((1U << TIMER_TILR3_1_LEN) - 1) << TIMER_TILR3_1_POS) -#define TIMER_TILR3_1_UMSK (~(((1U << TIMER_TILR3_1_LEN) - 1) << TIMER_TILR3_1_POS)) -#define TIMER_TILR3_2 TIMER_TILR3_2 -#define TIMER_TILR3_2_POS (2U) -#define TIMER_TILR3_2_LEN (1U) -#define TIMER_TILR3_2_MSK (((1U << TIMER_TILR3_2_LEN) - 1) << TIMER_TILR3_2_POS) -#define TIMER_TILR3_2_UMSK (~(((1U << TIMER_TILR3_2_LEN) - 1) << TIMER_TILR3_2_POS)) - -/* 0x98 : WDT Counter Reset */ -#define TIMER_WCR_OFFSET (0x98) -#define TIMER_WCR TIMER_WCR -#define TIMER_WCR_POS (0U) -#define TIMER_WCR_LEN (1U) -#define TIMER_WCR_MSK (((1U << TIMER_WCR_LEN) - 1) << TIMER_WCR_POS) -#define TIMER_WCR_UMSK (~(((1U << TIMER_WCR_LEN) - 1) << TIMER_WCR_POS)) - -/* 0x9C : WDT Access Key1 */ -#define TIMER_WFAR_OFFSET (0x9C) -#define TIMER_WFAR TIMER_WFAR -#define TIMER_WFAR_POS (0U) -#define TIMER_WFAR_LEN (16U) -#define TIMER_WFAR_MSK (((1U << TIMER_WFAR_LEN) - 1) << TIMER_WFAR_POS) -#define TIMER_WFAR_UMSK (~(((1U << TIMER_WFAR_LEN) - 1) << TIMER_WFAR_POS)) - -/* 0xA0 : WDT Access Key2 */ -#define TIMER_WSAR_OFFSET (0xA0) -#define TIMER_WSAR TIMER_WSAR -#define TIMER_WSAR_POS (0U) -#define TIMER_WSAR_LEN (16U) -#define TIMER_WSAR_MSK (((1U << TIMER_WSAR_LEN) - 1) << TIMER_WSAR_POS) -#define TIMER_WSAR_UMSK (~(((1U << TIMER_WSAR_LEN) - 1) << TIMER_WSAR_POS)) - -/* 0xA8 : Timer2 Counter Latch Value */ -#define TIMER_TCVWR2_OFFSET (0xA8) -#define TIMER_TCR2_CNT_LAT TIMER_TCR2_CNT_LAT -#define TIMER_TCR2_CNT_LAT_POS (0U) -#define TIMER_TCR2_CNT_LAT_LEN (32U) -#define TIMER_TCR2_CNT_LAT_MSK (((1U << TIMER_TCR2_CNT_LAT_LEN) - 1) << TIMER_TCR2_CNT_LAT_POS) -#define TIMER_TCR2_CNT_LAT_UMSK (~(((1U << TIMER_TCR2_CNT_LAT_LEN) - 1) << TIMER_TCR2_CNT_LAT_POS)) - -/* 0xAC : Timer3 Counter Latch Value */ -#define TIMER_TCVWR3_OFFSET (0xAC) -#define TIMER_TCR3_CNT_LAT TIMER_TCR3_CNT_LAT -#define TIMER_TCR3_CNT_LAT_POS (0U) -#define TIMER_TCR3_CNT_LAT_LEN (32U) -#define TIMER_TCR3_CNT_LAT_MSK (((1U << TIMER_TCR3_CNT_LAT_LEN) - 1) << TIMER_TCR3_CNT_LAT_POS) -#define TIMER_TCR3_CNT_LAT_UMSK (~(((1U << TIMER_TCR3_CNT_LAT_LEN) - 1) << TIMER_TCR3_CNT_LAT_POS)) - -/* 0xB4 : Timer2 Counter Sync Value */ -#define TIMER_TCVSYN2_OFFSET (0xB4) -#define TIMER_TCR2_CNT_SYNC TIMER_TCR2_CNT_SYNC -#define TIMER_TCR2_CNT_SYNC_POS (0U) -#define TIMER_TCR2_CNT_SYNC_LEN (32U) -#define TIMER_TCR2_CNT_SYNC_MSK (((1U << TIMER_TCR2_CNT_SYNC_LEN) - 1) << TIMER_TCR2_CNT_SYNC_POS) -#define TIMER_TCR2_CNT_SYNC_UMSK (~(((1U << TIMER_TCR2_CNT_SYNC_LEN) - 1) << TIMER_TCR2_CNT_SYNC_POS)) - -/* 0xB8 : Timer3 Counter Sync Value */ -#define TIMER_TCVSYN3_OFFSET (0xB8) -#define TIMER_TCR3_CNT_SYNC TIMER_TCR3_CNT_SYNC -#define TIMER_TCR3_CNT_SYNC_POS (0U) -#define TIMER_TCR3_CNT_SYNC_LEN (32U) -#define TIMER_TCR3_CNT_SYNC_MSK (((1U << TIMER_TCR3_CNT_SYNC_LEN) - 1) << TIMER_TCR3_CNT_SYNC_POS) -#define TIMER_TCR3_CNT_SYNC_UMSK (~(((1U << TIMER_TCR3_CNT_SYNC_LEN) - 1) << TIMER_TCR3_CNT_SYNC_POS)) - -/* 0xBC : Timer Division */ -#define TIMER_TCDR_OFFSET (0xBC) -#define TIMER_TCDR2 TIMER_TCDR2 -#define TIMER_TCDR2_POS (8U) -#define TIMER_TCDR2_LEN (8U) -#define TIMER_TCDR2_MSK (((1U << TIMER_TCDR2_LEN) - 1) << TIMER_TCDR2_POS) -#define TIMER_TCDR2_UMSK (~(((1U << TIMER_TCDR2_LEN) - 1) << TIMER_TCDR2_POS)) -#define TIMER_TCDR3 TIMER_TCDR3 -#define TIMER_TCDR3_POS (16U) -#define TIMER_TCDR3_LEN (8U) -#define TIMER_TCDR3_MSK (((1U << TIMER_TCDR3_LEN) - 1) << TIMER_TCDR3_POS) -#define TIMER_TCDR3_UMSK (~(((1U << TIMER_TCDR3_LEN) - 1) << TIMER_TCDR3_POS)) -#define TIMER_WCDR TIMER_WCDR -#define TIMER_WCDR_POS (24U) -#define TIMER_WCDR_LEN (8U) -#define TIMER_WCDR_MSK (((1U << TIMER_WCDR_LEN) - 1) << TIMER_WCDR_POS) -#define TIMER_WCDR_UMSK (~(((1U << TIMER_WCDR_LEN) - 1) << TIMER_WCDR_POS)) - -/* 0xC0 : GPIO Mode */ -#define TIMER_GPIO_OFFSET (0xC0) -#define TIMER2_GPIO_EN TIMER2_GPIO_EN -#define TIMER2_GPIO_EN_POS (1U) -#define TIMER2_GPIO_EN_LEN (1U) -#define TIMER2_GPIO_EN_MSK (((1U << TIMER2_GPIO_EN_LEN) - 1) << TIMER2_GPIO_EN_POS) -#define TIMER2_GPIO_EN_UMSK (~(((1U << TIMER2_GPIO_EN_LEN) - 1) << TIMER2_GPIO_EN_POS)) -#define TIMER2_GPIO_INV TIMER2_GPIO_INV -#define TIMER2_GPIO_INV_POS (5U) -#define TIMER2_GPIO_INV_LEN (1U) -#define TIMER2_GPIO_INV_MSK (((1U << TIMER2_GPIO_INV_LEN) - 1) << TIMER2_GPIO_INV_POS) -#define TIMER2_GPIO_INV_UMSK (~(((1U << TIMER2_GPIO_INV_LEN) - 1) << TIMER2_GPIO_INV_POS)) -#define TIMER3_GPIO_INV TIMER3_GPIO_INV -#define TIMER3_GPIO_INV_POS (6U) -#define TIMER3_GPIO_INV_LEN (1U) -#define TIMER3_GPIO_INV_MSK (((1U << TIMER3_GPIO_INV_LEN) - 1) << TIMER3_GPIO_INV_POS) -#define TIMER3_GPIO_INV_UMSK (~(((1U << TIMER3_GPIO_INV_LEN) - 1) << TIMER3_GPIO_INV_POS)) -#define TIMER_WDT_GPIO_INV TIMER_WDT_GPIO_INV -#define TIMER_WDT_GPIO_INV_POS (7U) -#define TIMER_WDT_GPIO_INV_LEN (1U) -#define TIMER_WDT_GPIO_INV_MSK (((1U << TIMER_WDT_GPIO_INV_LEN) - 1) << TIMER_WDT_GPIO_INV_POS) -#define TIMER_WDT_GPIO_INV_UMSK (~(((1U << TIMER_WDT_GPIO_INV_LEN) - 1) << TIMER_WDT_GPIO_INV_POS)) -#define TIMER_GPIO_LAT_OK TIMER_GPIO_LAT_OK -#define TIMER_GPIO_LAT_OK_POS (31U) -#define TIMER_GPIO_LAT_OK_LEN (1U) -#define TIMER_GPIO_LAT_OK_MSK (((1U << TIMER_GPIO_LAT_OK_LEN) - 1) << TIMER_GPIO_LAT_OK_POS) -#define TIMER_GPIO_LAT_OK_UMSK (~(((1U << TIMER_GPIO_LAT_OK_LEN) - 1) << TIMER_GPIO_LAT_OK_POS)) - -/* 0xC4 : GPIO Latch Value1 */ -#define TIMER_GPIO_LAT1_OFFSET (0xC4) -#define TIMER_GPIO_LAT1 TIMER_GPIO_LAT1 -#define TIMER_GPIO_LAT1_POS (0U) -#define TIMER_GPIO_LAT1_LEN (32U) -#define TIMER_GPIO_LAT1_MSK (((1U << TIMER_GPIO_LAT1_LEN) - 1) << TIMER_GPIO_LAT1_POS) -#define TIMER_GPIO_LAT1_UMSK (~(((1U << TIMER_GPIO_LAT1_LEN) - 1) << TIMER_GPIO_LAT1_POS)) - -/* 0xC8 : GPIO Latch Value2 */ -#define TIMER_GPIO_LAT2_OFFSET (0xC8) -#define TIMER_GPIO_LAT2 TIMER_GPIO_LAT2 -#define TIMER_GPIO_LAT2_POS (0U) -#define TIMER_GPIO_LAT2_LEN (32U) -#define TIMER_GPIO_LAT2_MSK (((1U << TIMER_GPIO_LAT2_LEN) - 1) << TIMER_GPIO_LAT2_POS) -#define TIMER_GPIO_LAT2_UMSK (~(((1U << TIMER_GPIO_LAT2_LEN) - 1) << TIMER_GPIO_LAT2_POS)) - -/* 0xCC : Timer Division Force */ -#define TIMER_TCDR_FORCE_OFFSET (0xCC) -#define TIMER_TCDR2_FORCE TIMER_TCDR2_FORCE -#define TIMER_TCDR2_FORCE_POS (1U) -#define TIMER_TCDR2_FORCE_LEN (1U) -#define TIMER_TCDR2_FORCE_MSK (((1U << TIMER_TCDR2_FORCE_LEN) - 1) << TIMER_TCDR2_FORCE_POS) -#define TIMER_TCDR2_FORCE_UMSK (~(((1U << TIMER_TCDR2_FORCE_LEN) - 1) << TIMER_TCDR2_FORCE_POS)) -#define TIMER_TCDR3_FORCE TIMER_TCDR3_FORCE -#define TIMER_TCDR3_FORCE_POS (2U) -#define TIMER_TCDR3_FORCE_LEN (1U) -#define TIMER_TCDR3_FORCE_MSK (((1U << TIMER_TCDR3_FORCE_LEN) - 1) << TIMER_TCDR3_FORCE_POS) -#define TIMER_TCDR3_FORCE_UMSK (~(((1U << TIMER_TCDR3_FORCE_LEN) - 1) << TIMER_TCDR3_FORCE_POS)) -#define TIMER_WCDR_FORCE TIMER_WCDR_FORCE -#define TIMER_WCDR_FORCE_POS (4U) -#define TIMER_WCDR_FORCE_LEN (1U) -#define TIMER_WCDR_FORCE_MSK (((1U << TIMER_WCDR_FORCE_LEN) - 1) << TIMER_WCDR_FORCE_POS) -#define TIMER_WCDR_FORCE_UMSK (~(((1U << TIMER_WCDR_FORCE_LEN) - 1) << TIMER_WCDR_FORCE_POS)) - -struct timer_reg { - /* 0x0 : Timer Clock Source */ - union { - struct { - uint32_t cs_2 : 4; /* [ 3: 0], r/w, 0x5 */ - uint32_t cs_3 : 4; /* [ 7: 4], r/w, 0x5 */ - uint32_t cs_wdt : 4; /* [11: 8], r/w, 0x1 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t tmr_rsv : 8; /* [23:16], rsvd, 0x0 */ - uint32_t ID : 8; /* [31:24], r, 0xa5 */ - } BF; - uint32_t WORD; - } TCCR; - - /* 0x4 reserved */ - uint8_t RESERVED0x4[12]; - - /* 0x10 : Timer2 Match Value 0 */ - union { - struct { - uint32_t tmr2_0 : 32; /* [31: 0], r/w, 0xffffffff */ - } BF; - uint32_t WORD; - } TMR2_0; - - /* 0x14 : Timer2 Match Value 1 */ - union { - struct { - uint32_t tmr2_1 : 32; /* [31: 0], r/w, 0xffffffff */ - } BF; - uint32_t WORD; - } TMR2_1; - - /* 0x18 : Timer2 Match Value 2 */ - union { - struct { - uint32_t tmr2_2 : 32; /* [31: 0], r/w, 0xffffffff */ - } BF; - uint32_t WORD; - } TMR2_2; - - /* 0x1C : Timer3 Match Value 0 */ - union { - struct { - uint32_t tmr3_0 : 32; /* [31: 0], r/w, 0xffffffff */ - } BF; - uint32_t WORD; - } TMR3_0; - - /* 0x20 : Timer3 Match Value 1 */ - union { - struct { - uint32_t tmr3_1 : 32; /* [31: 0], r/w, 0xffffffff */ - } BF; - uint32_t WORD; - } TMR3_1; - - /* 0x24 : Timer3 Match Value 2 */ - union { - struct { - uint32_t tmr3_2 : 32; /* [31: 0], r/w, 0xffffffff */ - } BF; - uint32_t WORD; - } TMR3_2; - - /* 0x28 reserved */ - uint8_t RESERVED0x28[4]; - - /* 0x2C : Timer2 Counter Value */ - union { - struct { - uint32_t tcr2_cnt : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } TCR2; - - /* 0x30 : Timer3 Counter Value */ - union { - struct { - uint32_t tcr3_cnt : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } TCR3; - - /* 0x34 reserved */ - uint8_t RESERVED0x34[4]; - - /* 0x38 : Timer2 Match Status */ - union { - struct { - uint32_t tsr2_0 : 1; /* [ 0], r, 0x0 */ - uint32_t tsr2_1 : 1; /* [ 1], r, 0x0 */ - uint32_t tsr2_2 : 1; /* [ 2], r, 0x0 */ - uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } TSR2; - - /* 0x3C : Timer3 Match Status */ - union { - struct { - uint32_t tsr3_0 : 1; /* [ 0], r, 0x0 */ - uint32_t tsr3_1 : 1; /* [ 1], r, 0x0 */ - uint32_t tsr3_2 : 1; /* [ 2], r, 0x0 */ - uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } TSR3; - - /* 0x40 reserved */ - uint8_t RESERVED0x40[4]; - - /* 0x44 : Timer2 Match Interrupt Enable */ - union { - struct { - uint32_t tier2_0 : 1; /* [ 0], r/w, 0x0 */ - uint32_t tier2_1 : 1; /* [ 1], r/w, 0x0 */ - uint32_t tier2_2 : 1; /* [ 2], r/w, 0x0 */ - uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } TIER2; - - /* 0x48 : Timer3 Match Interrupt Enable */ - union { - struct { - uint32_t tier3_0 : 1; /* [ 0], r/w, 0x0 */ - uint32_t tier3_1 : 1; /* [ 1], r/w, 0x0 */ - uint32_t tier3_2 : 1; /* [ 2], r/w, 0x0 */ - uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } TIER3; - - /* 0x4c reserved */ - uint8_t RESERVED0x4c[4]; - - /* 0x50 : Timer2 Pre-Load Value */ - union { - struct { - uint32_t tplvr2 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } TPLVR2; - - /* 0x54 : Timer3 Pre-Load Value */ - union { - struct { - uint32_t tplvr3 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } TPLVR3; - - /* 0x58 reserved */ - uint8_t RESERVED0x58[4]; - - /* 0x5C : Timer2 Pre-Load Control */ - union { - struct { - uint32_t tplcr2 : 2; /* [ 1: 0], r/w, 0x0 */ - uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } TPLCR2; - - /* 0x60 : Timer3 Pre-Load Control */ - union { - struct { - uint32_t tplcr3 : 2; /* [ 1: 0], r/w, 0x0 */ - uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } TPLCR3; - - /* 0x64 : Watch-dog reset/interrupt Mode */ - union { - struct { - uint32_t we : 1; /* [ 0], r/w, 0x0 */ - uint32_t wrie : 1; /* [ 1], r/w, 0x0 */ - uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WMER; - - /* 0x68 : Watch-dog Match Value */ - union { - struct { - uint32_t wmr : 16; /* [15: 0], r/w, 0xffff */ - uint32_t wdt_align : 1; /* [ 16], r/w, 0x0 */ - uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WMR; - - /* 0x6C : Watch-dog Counter Value */ - union { - struct { - uint32_t wdt_cnt : 16; /* [15: 0], r, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WVR; - - /* 0x70 : Watch-dog Reset Status */ - union { - struct { - uint32_t wts : 1; /* [ 0], w, 0x0 */ - uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WSR; - - /* 0x74 reserved */ - uint8_t RESERVED0x74[4]; - - /* 0x78 : Timer2 Interrupt Clear */ - union { - struct { - uint32_t tclr2_0 : 1; /* [ 0], w, 0x0 */ - uint32_t tclr2_1 : 1; /* [ 1], w, 0x0 */ - uint32_t tclr2_2 : 1; /* [ 2], w, 0x0 */ - uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } TICR2; - - /* 0x7C : Timer3 Interrupt Clear */ - union { - struct { - uint32_t tclr3_0 : 1; /* [ 0], w, 0x0 */ - uint32_t tclr3_1 : 1; /* [ 1], w, 0x0 */ - uint32_t tclr3_2 : 1; /* [ 2], w, 0x0 */ - uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } TICR3; - - /* 0x80 : WDT Interrupt Clear */ - union { - struct { - uint32_t wiclr : 1; /* [ 0], w, 0x0 */ - uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WICR; - - /* 0x84 : Timer Counter Enable/Clear */ - union { - struct { - uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */ - uint32_t timer2_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t timer3_en : 1; /* [ 2], r/w, 0x0 */ - uint32_t reserved_3_4 : 2; /* [ 4: 3], rsvd, 0x0 */ - uint32_t tcr2_cnt_clr : 1; /* [ 5], r/w, 0x0 */ - uint32_t tcr3_cnt_clr : 1; /* [ 6], r/w, 0x0 */ - uint32_t reserved_7_31 : 25; /* [31: 7], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } TCER; - - /* 0x88 : Timer Counter Mode */ - union { - struct { - uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */ - uint32_t timer2_mode : 1; /* [ 1], r/w, 0x0 */ - uint32_t timer3_mode : 1; /* [ 2], r/w, 0x0 */ - uint32_t reserved_3_4 : 2; /* [ 4: 3], rsvd, 0x0 */ - uint32_t timer2_align : 1; /* [ 5], r/w, 0x0 */ - uint32_t timer3_align : 1; /* [ 6], r/w, 0x0 */ - uint32_t reserved_7_31 : 25; /* [31: 7], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } TCMR; - - /* 0x8c reserved */ - uint8_t RESERVED0x8c[4]; - - /* 0x90 : Timer2 Match Interrupt Mode */ - union { - struct { - uint32_t tilr2_0 : 1; /* [ 0], r/w, 0x0 */ - uint32_t tilr2_1 : 1; /* [ 1], r/w, 0x0 */ - uint32_t tilr2_2 : 1; /* [ 2], r/w, 0x0 */ - uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } TILR2; - - /* 0x94 : Timer3 Match Interrupt Mode */ - union { - struct { - uint32_t tilr3_0 : 1; /* [ 0], r/w, 0x0 */ - uint32_t tilr3_1 : 1; /* [ 1], r/w, 0x0 */ - uint32_t tilr3_2 : 1; /* [ 2], r/w, 0x0 */ - uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } TILR3; - - /* 0x98 : WDT Counter Reset */ - union { - struct { - uint32_t wcr : 1; /* [ 0], w, 0x0 */ - uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WCR; - - /* 0x9C : WDT Access Key1 */ - union { - struct { - uint32_t wfar : 16; /* [15: 0], w, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WFAR; - - /* 0xA0 : WDT Access Key2 */ - union { - struct { - uint32_t wsar : 16; /* [15: 0], w, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WSAR; - - /* 0xa4 reserved */ - uint8_t RESERVED0xa4[4]; - - /* 0xA8 : Timer2 Counter Latch Value */ - union { - struct { - uint32_t tcr2_cnt_lat : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } TCVWR2; - - /* 0xAC : Timer3 Counter Latch Value */ - union { - struct { - uint32_t tcr3_cnt_lat : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } TCVWR3; - - /* 0xb0 reserved */ - uint8_t RESERVED0xb0[4]; - - /* 0xB4 : Timer2 Counter Sync Value */ - union { - struct { - uint32_t tcr2_cnt_sync : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } TCVSYN2; - - /* 0xB8 : Timer3 Counter Sync Value */ - union { - struct { - uint32_t tcr3_cnt_sync : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } TCVSYN3; - - /* 0xBC : Timer Division */ - union { - struct { - uint32_t reserved_0_7 : 8; /* [ 7: 0], rsvd, 0x0 */ - uint32_t tcdr2 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t tcdr3 : 8; /* [23:16], r/w, 0x0 */ - uint32_t wcdr : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } TCDR; - - /* 0xC0 : GPIO Mode */ - union { - struct { - uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */ - uint32_t timer2_gpio_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t reserved_2_4 : 3; /* [ 4: 2], rsvd, 0x0 */ - uint32_t timer2_gpio_inv : 1; /* [ 5], r/w, 0x0 */ - uint32_t timer3_gpio_inv : 1; /* [ 6], r/w, 0x0 */ - uint32_t wdt_gpio_inv : 1; /* [ 7], r/w, 0x0 */ - uint32_t reserved_8_30 : 23; /* [30: 8], rsvd, 0x0 */ - uint32_t gpio_lat_ok : 1; /* [ 31], r, 0x0 */ - } BF; - uint32_t WORD; - } GPIO; - - /* 0xC4 : GPIO Latch Value1 */ - union { - struct { - uint32_t gpio_lat1 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } GPIO_LAT1; - - /* 0xC8 : GPIO Latch Value2 */ - union { - struct { - uint32_t gpio_lat2 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } GPIO_LAT2; - - /* 0xCC : Timer Division Force */ - union { - struct { - uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */ - uint32_t tcdr2_force : 1; /* [ 1], r/w, 0x0 */ - uint32_t tcdr3_force : 1; /* [ 2], r/w, 0x0 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t wcdr_force : 1; /* [ 4], r/w, 0x0 */ - uint32_t reserved_5_31 : 27; /* [31: 5], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } TCDR_FORCE; -}; - -typedef volatile struct timer_reg timer_reg_t; - -#endif /* __TIMER_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/uart_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/uart_reg.h deleted file mode 100644 index 81c34e6234..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/uart_reg.h +++ /dev/null @@ -1,978 +0,0 @@ -/** - ****************************************************************************** - * @file uart_reg.h - * @version V1.0 - * @date 2021-07-08 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __UART_REG_H__ -#define __UART_REG_H__ - -#include "bl808.h" - -/* 0x0 : utx_config */ -#define UART_UTX_CONFIG_OFFSET (0x0) -#define UART_CR_UTX_EN UART_CR_UTX_EN -#define UART_CR_UTX_EN_POS (0U) -#define UART_CR_UTX_EN_LEN (1U) -#define UART_CR_UTX_EN_MSK (((1U << UART_CR_UTX_EN_LEN) - 1) << UART_CR_UTX_EN_POS) -#define UART_CR_UTX_EN_UMSK (~(((1U << UART_CR_UTX_EN_LEN) - 1) << UART_CR_UTX_EN_POS)) -#define UART_CR_UTX_CTS_EN UART_CR_UTX_CTS_EN -#define UART_CR_UTX_CTS_EN_POS (1U) -#define UART_CR_UTX_CTS_EN_LEN (1U) -#define UART_CR_UTX_CTS_EN_MSK (((1U << UART_CR_UTX_CTS_EN_LEN) - 1) << UART_CR_UTX_CTS_EN_POS) -#define UART_CR_UTX_CTS_EN_UMSK (~(((1U << UART_CR_UTX_CTS_EN_LEN) - 1) << UART_CR_UTX_CTS_EN_POS)) -#define UART_CR_UTX_FRM_EN UART_CR_UTX_FRM_EN -#define UART_CR_UTX_FRM_EN_POS (2U) -#define UART_CR_UTX_FRM_EN_LEN (1U) -#define UART_CR_UTX_FRM_EN_MSK (((1U << UART_CR_UTX_FRM_EN_LEN) - 1) << UART_CR_UTX_FRM_EN_POS) -#define UART_CR_UTX_FRM_EN_UMSK (~(((1U << UART_CR_UTX_FRM_EN_LEN) - 1) << UART_CR_UTX_FRM_EN_POS)) -#define UART_CR_UTX_LIN_EN UART_CR_UTX_LIN_EN -#define UART_CR_UTX_LIN_EN_POS (3U) -#define UART_CR_UTX_LIN_EN_LEN (1U) -#define UART_CR_UTX_LIN_EN_MSK (((1U << UART_CR_UTX_LIN_EN_LEN) - 1) << UART_CR_UTX_LIN_EN_POS) -#define UART_CR_UTX_LIN_EN_UMSK (~(((1U << UART_CR_UTX_LIN_EN_LEN) - 1) << UART_CR_UTX_LIN_EN_POS)) -#define UART_CR_UTX_PRT_EN UART_CR_UTX_PRT_EN -#define UART_CR_UTX_PRT_EN_POS (4U) -#define UART_CR_UTX_PRT_EN_LEN (1U) -#define UART_CR_UTX_PRT_EN_MSK (((1U << UART_CR_UTX_PRT_EN_LEN) - 1) << UART_CR_UTX_PRT_EN_POS) -#define UART_CR_UTX_PRT_EN_UMSK (~(((1U << UART_CR_UTX_PRT_EN_LEN) - 1) << UART_CR_UTX_PRT_EN_POS)) -#define UART_CR_UTX_PRT_SEL UART_CR_UTX_PRT_SEL -#define UART_CR_UTX_PRT_SEL_POS (5U) -#define UART_CR_UTX_PRT_SEL_LEN (1U) -#define UART_CR_UTX_PRT_SEL_MSK (((1U << UART_CR_UTX_PRT_SEL_LEN) - 1) << UART_CR_UTX_PRT_SEL_POS) -#define UART_CR_UTX_PRT_SEL_UMSK (~(((1U << UART_CR_UTX_PRT_SEL_LEN) - 1) << UART_CR_UTX_PRT_SEL_POS)) -#define UART_CR_UTX_IR_EN UART_CR_UTX_IR_EN -#define UART_CR_UTX_IR_EN_POS (6U) -#define UART_CR_UTX_IR_EN_LEN (1U) -#define UART_CR_UTX_IR_EN_MSK (((1U << UART_CR_UTX_IR_EN_LEN) - 1) << UART_CR_UTX_IR_EN_POS) -#define UART_CR_UTX_IR_EN_UMSK (~(((1U << UART_CR_UTX_IR_EN_LEN) - 1) << UART_CR_UTX_IR_EN_POS)) -#define UART_CR_UTX_IR_INV UART_CR_UTX_IR_INV -#define UART_CR_UTX_IR_INV_POS (7U) -#define UART_CR_UTX_IR_INV_LEN (1U) -#define UART_CR_UTX_IR_INV_MSK (((1U << UART_CR_UTX_IR_INV_LEN) - 1) << UART_CR_UTX_IR_INV_POS) -#define UART_CR_UTX_IR_INV_UMSK (~(((1U << UART_CR_UTX_IR_INV_LEN) - 1) << UART_CR_UTX_IR_INV_POS)) -#define UART_CR_UTX_BIT_CNT_D UART_CR_UTX_BIT_CNT_D -#define UART_CR_UTX_BIT_CNT_D_POS (8U) -#define UART_CR_UTX_BIT_CNT_D_LEN (3U) -#define UART_CR_UTX_BIT_CNT_D_MSK (((1U << UART_CR_UTX_BIT_CNT_D_LEN) - 1) << UART_CR_UTX_BIT_CNT_D_POS) -#define UART_CR_UTX_BIT_CNT_D_UMSK (~(((1U << UART_CR_UTX_BIT_CNT_D_LEN) - 1) << UART_CR_UTX_BIT_CNT_D_POS)) -#define UART_CR_UTX_BIT_CNT_P UART_CR_UTX_BIT_CNT_P -#define UART_CR_UTX_BIT_CNT_P_POS (11U) -#define UART_CR_UTX_BIT_CNT_P_LEN (2U) -#define UART_CR_UTX_BIT_CNT_P_MSK (((1U << UART_CR_UTX_BIT_CNT_P_LEN) - 1) << UART_CR_UTX_BIT_CNT_P_POS) -#define UART_CR_UTX_BIT_CNT_P_UMSK (~(((1U << UART_CR_UTX_BIT_CNT_P_LEN) - 1) << UART_CR_UTX_BIT_CNT_P_POS)) -#define UART_CR_UTX_BIT_CNT_B UART_CR_UTX_BIT_CNT_B -#define UART_CR_UTX_BIT_CNT_B_POS (13U) -#define UART_CR_UTX_BIT_CNT_B_LEN (3U) -#define UART_CR_UTX_BIT_CNT_B_MSK (((1U << UART_CR_UTX_BIT_CNT_B_LEN) - 1) << UART_CR_UTX_BIT_CNT_B_POS) -#define UART_CR_UTX_BIT_CNT_B_UMSK (~(((1U << UART_CR_UTX_BIT_CNT_B_LEN) - 1) << UART_CR_UTX_BIT_CNT_B_POS)) -#define UART_CR_UTX_LEN UART_CR_UTX_LEN -#define UART_CR_UTX_LEN_POS (16U) -#define UART_CR_UTX_LEN_LEN (16U) -#define UART_CR_UTX_LEN_MSK (((1U << UART_CR_UTX_LEN_LEN) - 1) << UART_CR_UTX_LEN_POS) -#define UART_CR_UTX_LEN_UMSK (~(((1U << UART_CR_UTX_LEN_LEN) - 1) << UART_CR_UTX_LEN_POS)) - -/* 0x4 : urx_config */ -#define UART_URX_CONFIG_OFFSET (0x4) -#define UART_CR_URX_EN UART_CR_URX_EN -#define UART_CR_URX_EN_POS (0U) -#define UART_CR_URX_EN_LEN (1U) -#define UART_CR_URX_EN_MSK (((1U << UART_CR_URX_EN_LEN) - 1) << UART_CR_URX_EN_POS) -#define UART_CR_URX_EN_UMSK (~(((1U << UART_CR_URX_EN_LEN) - 1) << UART_CR_URX_EN_POS)) -#define UART_CR_URX_ABR_EN UART_CR_URX_ABR_EN -#define UART_CR_URX_ABR_EN_POS (1U) -#define UART_CR_URX_ABR_EN_LEN (1U) -#define UART_CR_URX_ABR_EN_MSK (((1U << UART_CR_URX_ABR_EN_LEN) - 1) << UART_CR_URX_ABR_EN_POS) -#define UART_CR_URX_ABR_EN_UMSK (~(((1U << UART_CR_URX_ABR_EN_LEN) - 1) << UART_CR_URX_ABR_EN_POS)) -#define UART_CR_URX_LIN_EN UART_CR_URX_LIN_EN -#define UART_CR_URX_LIN_EN_POS (3U) -#define UART_CR_URX_LIN_EN_LEN (1U) -#define UART_CR_URX_LIN_EN_MSK (((1U << UART_CR_URX_LIN_EN_LEN) - 1) << UART_CR_URX_LIN_EN_POS) -#define UART_CR_URX_LIN_EN_UMSK (~(((1U << UART_CR_URX_LIN_EN_LEN) - 1) << UART_CR_URX_LIN_EN_POS)) -#define UART_CR_URX_PRT_EN UART_CR_URX_PRT_EN -#define UART_CR_URX_PRT_EN_POS (4U) -#define UART_CR_URX_PRT_EN_LEN (1U) -#define UART_CR_URX_PRT_EN_MSK (((1U << UART_CR_URX_PRT_EN_LEN) - 1) << UART_CR_URX_PRT_EN_POS) -#define UART_CR_URX_PRT_EN_UMSK (~(((1U << UART_CR_URX_PRT_EN_LEN) - 1) << UART_CR_URX_PRT_EN_POS)) -#define UART_CR_URX_PRT_SEL UART_CR_URX_PRT_SEL -#define UART_CR_URX_PRT_SEL_POS (5U) -#define UART_CR_URX_PRT_SEL_LEN (1U) -#define UART_CR_URX_PRT_SEL_MSK (((1U << UART_CR_URX_PRT_SEL_LEN) - 1) << UART_CR_URX_PRT_SEL_POS) -#define UART_CR_URX_PRT_SEL_UMSK (~(((1U << UART_CR_URX_PRT_SEL_LEN) - 1) << UART_CR_URX_PRT_SEL_POS)) -#define UART_CR_URX_IR_EN UART_CR_URX_IR_EN -#define UART_CR_URX_IR_EN_POS (6U) -#define UART_CR_URX_IR_EN_LEN (1U) -#define UART_CR_URX_IR_EN_MSK (((1U << UART_CR_URX_IR_EN_LEN) - 1) << UART_CR_URX_IR_EN_POS) -#define UART_CR_URX_IR_EN_UMSK (~(((1U << UART_CR_URX_IR_EN_LEN) - 1) << UART_CR_URX_IR_EN_POS)) -#define UART_CR_URX_IR_INV UART_CR_URX_IR_INV -#define UART_CR_URX_IR_INV_POS (7U) -#define UART_CR_URX_IR_INV_LEN (1U) -#define UART_CR_URX_IR_INV_MSK (((1U << UART_CR_URX_IR_INV_LEN) - 1) << UART_CR_URX_IR_INV_POS) -#define UART_CR_URX_IR_INV_UMSK (~(((1U << UART_CR_URX_IR_INV_LEN) - 1) << UART_CR_URX_IR_INV_POS)) -#define UART_CR_URX_BIT_CNT_D UART_CR_URX_BIT_CNT_D -#define UART_CR_URX_BIT_CNT_D_POS (8U) -#define UART_CR_URX_BIT_CNT_D_LEN (3U) -#define UART_CR_URX_BIT_CNT_D_MSK (((1U << UART_CR_URX_BIT_CNT_D_LEN) - 1) << UART_CR_URX_BIT_CNT_D_POS) -#define UART_CR_URX_BIT_CNT_D_UMSK (~(((1U << UART_CR_URX_BIT_CNT_D_LEN) - 1) << UART_CR_URX_BIT_CNT_D_POS)) -#define UART_CR_URX_DEG_EN UART_CR_URX_DEG_EN -#define UART_CR_URX_DEG_EN_POS (11U) -#define UART_CR_URX_DEG_EN_LEN (1U) -#define UART_CR_URX_DEG_EN_MSK (((1U << UART_CR_URX_DEG_EN_LEN) - 1) << UART_CR_URX_DEG_EN_POS) -#define UART_CR_URX_DEG_EN_UMSK (~(((1U << UART_CR_URX_DEG_EN_LEN) - 1) << UART_CR_URX_DEG_EN_POS)) -#define UART_CR_URX_DEG_CNT UART_CR_URX_DEG_CNT -#define UART_CR_URX_DEG_CNT_POS (12U) -#define UART_CR_URX_DEG_CNT_LEN (4U) -#define UART_CR_URX_DEG_CNT_MSK (((1U << UART_CR_URX_DEG_CNT_LEN) - 1) << UART_CR_URX_DEG_CNT_POS) -#define UART_CR_URX_DEG_CNT_UMSK (~(((1U << UART_CR_URX_DEG_CNT_LEN) - 1) << UART_CR_URX_DEG_CNT_POS)) -#define UART_CR_URX_LEN UART_CR_URX_LEN -#define UART_CR_URX_LEN_POS (16U) -#define UART_CR_URX_LEN_LEN (16U) -#define UART_CR_URX_LEN_MSK (((1U << UART_CR_URX_LEN_LEN) - 1) << UART_CR_URX_LEN_POS) -#define UART_CR_URX_LEN_UMSK (~(((1U << UART_CR_URX_LEN_LEN) - 1) << UART_CR_URX_LEN_POS)) - -/* 0x8 : uart_bit_prd */ -#define UART_BIT_PRD_OFFSET (0x8) -#define UART_CR_UTX_BIT_PRD UART_CR_UTX_BIT_PRD -#define UART_CR_UTX_BIT_PRD_POS (0U) -#define UART_CR_UTX_BIT_PRD_LEN (16U) -#define UART_CR_UTX_BIT_PRD_MSK (((1U << UART_CR_UTX_BIT_PRD_LEN) - 1) << UART_CR_UTX_BIT_PRD_POS) -#define UART_CR_UTX_BIT_PRD_UMSK (~(((1U << UART_CR_UTX_BIT_PRD_LEN) - 1) << UART_CR_UTX_BIT_PRD_POS)) -#define UART_CR_URX_BIT_PRD UART_CR_URX_BIT_PRD -#define UART_CR_URX_BIT_PRD_POS (16U) -#define UART_CR_URX_BIT_PRD_LEN (16U) -#define UART_CR_URX_BIT_PRD_MSK (((1U << UART_CR_URX_BIT_PRD_LEN) - 1) << UART_CR_URX_BIT_PRD_POS) -#define UART_CR_URX_BIT_PRD_UMSK (~(((1U << UART_CR_URX_BIT_PRD_LEN) - 1) << UART_CR_URX_BIT_PRD_POS)) - -/* 0xC : data_config */ -#define UART_DATA_CONFIG_OFFSET (0xC) -#define UART_CR_UART_BIT_INV UART_CR_UART_BIT_INV -#define UART_CR_UART_BIT_INV_POS (0U) -#define UART_CR_UART_BIT_INV_LEN (1U) -#define UART_CR_UART_BIT_INV_MSK (((1U << UART_CR_UART_BIT_INV_LEN) - 1) << UART_CR_UART_BIT_INV_POS) -#define UART_CR_UART_BIT_INV_UMSK (~(((1U << UART_CR_UART_BIT_INV_LEN) - 1) << UART_CR_UART_BIT_INV_POS)) - -/* 0x10 : utx_ir_position */ -#define UART_UTX_IR_POSITION_OFFSET (0x10) -#define UART_CR_UTX_IR_POS_S UART_CR_UTX_IR_POS_S -#define UART_CR_UTX_IR_POS_S_POS (0U) -#define UART_CR_UTX_IR_POS_S_LEN (16U) -#define UART_CR_UTX_IR_POS_S_MSK (((1U << UART_CR_UTX_IR_POS_S_LEN) - 1) << UART_CR_UTX_IR_POS_S_POS) -#define UART_CR_UTX_IR_POS_S_UMSK (~(((1U << UART_CR_UTX_IR_POS_S_LEN) - 1) << UART_CR_UTX_IR_POS_S_POS)) -#define UART_CR_UTX_IR_POS_P UART_CR_UTX_IR_POS_P -#define UART_CR_UTX_IR_POS_P_POS (16U) -#define UART_CR_UTX_IR_POS_P_LEN (16U) -#define UART_CR_UTX_IR_POS_P_MSK (((1U << UART_CR_UTX_IR_POS_P_LEN) - 1) << UART_CR_UTX_IR_POS_P_POS) -#define UART_CR_UTX_IR_POS_P_UMSK (~(((1U << UART_CR_UTX_IR_POS_P_LEN) - 1) << UART_CR_UTX_IR_POS_P_POS)) - -/* 0x14 : urx_ir_position */ -#define UART_URX_IR_POSITION_OFFSET (0x14) -#define UART_CR_URX_IR_POS_S UART_CR_URX_IR_POS_S -#define UART_CR_URX_IR_POS_S_POS (0U) -#define UART_CR_URX_IR_POS_S_LEN (16U) -#define UART_CR_URX_IR_POS_S_MSK (((1U << UART_CR_URX_IR_POS_S_LEN) - 1) << UART_CR_URX_IR_POS_S_POS) -#define UART_CR_URX_IR_POS_S_UMSK (~(((1U << UART_CR_URX_IR_POS_S_LEN) - 1) << UART_CR_URX_IR_POS_S_POS)) - -/* 0x18 : urx_rto_timer */ -#define UART_URX_RTO_TIMER_OFFSET (0x18) -#define UART_CR_URX_RTO_VALUE UART_CR_URX_RTO_VALUE -#define UART_CR_URX_RTO_VALUE_POS (0U) -#define UART_CR_URX_RTO_VALUE_LEN (8U) -#define UART_CR_URX_RTO_VALUE_MSK (((1U << UART_CR_URX_RTO_VALUE_LEN) - 1) << UART_CR_URX_RTO_VALUE_POS) -#define UART_CR_URX_RTO_VALUE_UMSK (~(((1U << UART_CR_URX_RTO_VALUE_LEN) - 1) << UART_CR_URX_RTO_VALUE_POS)) - -/* 0x1C : uart_sw_mode */ -#define UART_SW_MODE_OFFSET (0x1C) -#define UART_CR_UTX_TXD_SW_MODE UART_CR_UTX_TXD_SW_MODE -#define UART_CR_UTX_TXD_SW_MODE_POS (0U) -#define UART_CR_UTX_TXD_SW_MODE_LEN (1U) -#define UART_CR_UTX_TXD_SW_MODE_MSK (((1U << UART_CR_UTX_TXD_SW_MODE_LEN) - 1) << UART_CR_UTX_TXD_SW_MODE_POS) -#define UART_CR_UTX_TXD_SW_MODE_UMSK (~(((1U << UART_CR_UTX_TXD_SW_MODE_LEN) - 1) << UART_CR_UTX_TXD_SW_MODE_POS)) -#define UART_CR_UTX_TXD_SW_VAL UART_CR_UTX_TXD_SW_VAL -#define UART_CR_UTX_TXD_SW_VAL_POS (1U) -#define UART_CR_UTX_TXD_SW_VAL_LEN (1U) -#define UART_CR_UTX_TXD_SW_VAL_MSK (((1U << UART_CR_UTX_TXD_SW_VAL_LEN) - 1) << UART_CR_UTX_TXD_SW_VAL_POS) -#define UART_CR_UTX_TXD_SW_VAL_UMSK (~(((1U << UART_CR_UTX_TXD_SW_VAL_LEN) - 1) << UART_CR_UTX_TXD_SW_VAL_POS)) -#define UART_CR_URX_RTS_SW_MODE UART_CR_URX_RTS_SW_MODE -#define UART_CR_URX_RTS_SW_MODE_POS (2U) -#define UART_CR_URX_RTS_SW_MODE_LEN (1U) -#define UART_CR_URX_RTS_SW_MODE_MSK (((1U << UART_CR_URX_RTS_SW_MODE_LEN) - 1) << UART_CR_URX_RTS_SW_MODE_POS) -#define UART_CR_URX_RTS_SW_MODE_UMSK (~(((1U << UART_CR_URX_RTS_SW_MODE_LEN) - 1) << UART_CR_URX_RTS_SW_MODE_POS)) -#define UART_CR_URX_RTS_SW_VAL UART_CR_URX_RTS_SW_VAL -#define UART_CR_URX_RTS_SW_VAL_POS (3U) -#define UART_CR_URX_RTS_SW_VAL_LEN (1U) -#define UART_CR_URX_RTS_SW_VAL_MSK (((1U << UART_CR_URX_RTS_SW_VAL_LEN) - 1) << UART_CR_URX_RTS_SW_VAL_POS) -#define UART_CR_URX_RTS_SW_VAL_UMSK (~(((1U << UART_CR_URX_RTS_SW_VAL_LEN) - 1) << UART_CR_URX_RTS_SW_VAL_POS)) - -/* 0x20 : UART interrupt status */ -#define UART_INT_STS_OFFSET (0x20) -#define UART_UTX_END_INT UART_UTX_END_INT -#define UART_UTX_END_INT_POS (0U) -#define UART_UTX_END_INT_LEN (1U) -#define UART_UTX_END_INT_MSK (((1U << UART_UTX_END_INT_LEN) - 1) << UART_UTX_END_INT_POS) -#define UART_UTX_END_INT_UMSK (~(((1U << UART_UTX_END_INT_LEN) - 1) << UART_UTX_END_INT_POS)) -#define UART_URX_END_INT UART_URX_END_INT -#define UART_URX_END_INT_POS (1U) -#define UART_URX_END_INT_LEN (1U) -#define UART_URX_END_INT_MSK (((1U << UART_URX_END_INT_LEN) - 1) << UART_URX_END_INT_POS) -#define UART_URX_END_INT_UMSK (~(((1U << UART_URX_END_INT_LEN) - 1) << UART_URX_END_INT_POS)) -#define UART_UTX_FRDY_INT UART_UTX_FRDY_INT -#define UART_UTX_FRDY_INT_POS (2U) -#define UART_UTX_FRDY_INT_LEN (1U) -#define UART_UTX_FRDY_INT_MSK (((1U << UART_UTX_FRDY_INT_LEN) - 1) << UART_UTX_FRDY_INT_POS) -#define UART_UTX_FRDY_INT_UMSK (~(((1U << UART_UTX_FRDY_INT_LEN) - 1) << UART_UTX_FRDY_INT_POS)) -#define UART_URX_FRDY_INT UART_URX_FRDY_INT -#define UART_URX_FRDY_INT_POS (3U) -#define UART_URX_FRDY_INT_LEN (1U) -#define UART_URX_FRDY_INT_MSK (((1U << UART_URX_FRDY_INT_LEN) - 1) << UART_URX_FRDY_INT_POS) -#define UART_URX_FRDY_INT_UMSK (~(((1U << UART_URX_FRDY_INT_LEN) - 1) << UART_URX_FRDY_INT_POS)) -#define UART_URX_RTO_INT UART_URX_RTO_INT -#define UART_URX_RTO_INT_POS (4U) -#define UART_URX_RTO_INT_LEN (1U) -#define UART_URX_RTO_INT_MSK (((1U << UART_URX_RTO_INT_LEN) - 1) << UART_URX_RTO_INT_POS) -#define UART_URX_RTO_INT_UMSK (~(((1U << UART_URX_RTO_INT_LEN) - 1) << UART_URX_RTO_INT_POS)) -#define UART_URX_PCE_INT UART_URX_PCE_INT -#define UART_URX_PCE_INT_POS (5U) -#define UART_URX_PCE_INT_LEN (1U) -#define UART_URX_PCE_INT_MSK (((1U << UART_URX_PCE_INT_LEN) - 1) << UART_URX_PCE_INT_POS) -#define UART_URX_PCE_INT_UMSK (~(((1U << UART_URX_PCE_INT_LEN) - 1) << UART_URX_PCE_INT_POS)) -#define UART_UTX_FER_INT UART_UTX_FER_INT -#define UART_UTX_FER_INT_POS (6U) -#define UART_UTX_FER_INT_LEN (1U) -#define UART_UTX_FER_INT_MSK (((1U << UART_UTX_FER_INT_LEN) - 1) << UART_UTX_FER_INT_POS) -#define UART_UTX_FER_INT_UMSK (~(((1U << UART_UTX_FER_INT_LEN) - 1) << UART_UTX_FER_INT_POS)) -#define UART_URX_FER_INT UART_URX_FER_INT -#define UART_URX_FER_INT_POS (7U) -#define UART_URX_FER_INT_LEN (1U) -#define UART_URX_FER_INT_MSK (((1U << UART_URX_FER_INT_LEN) - 1) << UART_URX_FER_INT_POS) -#define UART_URX_FER_INT_UMSK (~(((1U << UART_URX_FER_INT_LEN) - 1) << UART_URX_FER_INT_POS)) -#define UART_URX_LSE_INT UART_URX_LSE_INT -#define UART_URX_LSE_INT_POS (8U) -#define UART_URX_LSE_INT_LEN (1U) -#define UART_URX_LSE_INT_MSK (((1U << UART_URX_LSE_INT_LEN) - 1) << UART_URX_LSE_INT_POS) -#define UART_URX_LSE_INT_UMSK (~(((1U << UART_URX_LSE_INT_LEN) - 1) << UART_URX_LSE_INT_POS)) -#define UART_URX_BCR_INT UART_URX_BCR_INT -#define UART_URX_BCR_INT_POS (9U) -#define UART_URX_BCR_INT_LEN (1U) -#define UART_URX_BCR_INT_MSK (((1U << UART_URX_BCR_INT_LEN) - 1) << UART_URX_BCR_INT_POS) -#define UART_URX_BCR_INT_UMSK (~(((1U << UART_URX_BCR_INT_LEN) - 1) << UART_URX_BCR_INT_POS)) -#define UART_URX_ADS_INT UART_URX_ADS_INT -#define UART_URX_ADS_INT_POS (10U) -#define UART_URX_ADS_INT_LEN (1U) -#define UART_URX_ADS_INT_MSK (((1U << UART_URX_ADS_INT_LEN) - 1) << UART_URX_ADS_INT_POS) -#define UART_URX_ADS_INT_UMSK (~(((1U << UART_URX_ADS_INT_LEN) - 1) << UART_URX_ADS_INT_POS)) -#define UART_URX_AD5_INT UART_URX_AD5_INT -#define UART_URX_AD5_INT_POS (11U) -#define UART_URX_AD5_INT_LEN (1U) -#define UART_URX_AD5_INT_MSK (((1U << UART_URX_AD5_INT_LEN) - 1) << UART_URX_AD5_INT_POS) -#define UART_URX_AD5_INT_UMSK (~(((1U << UART_URX_AD5_INT_LEN) - 1) << UART_URX_AD5_INT_POS)) - -/* 0x24 : UART interrupt mask */ -#define UART_INT_MASK_OFFSET (0x24) -#define UART_CR_UTX_END_MASK UART_CR_UTX_END_MASK -#define UART_CR_UTX_END_MASK_POS (0U) -#define UART_CR_UTX_END_MASK_LEN (1U) -#define UART_CR_UTX_END_MASK_MSK (((1U << UART_CR_UTX_END_MASK_LEN) - 1) << UART_CR_UTX_END_MASK_POS) -#define UART_CR_UTX_END_MASK_UMSK (~(((1U << UART_CR_UTX_END_MASK_LEN) - 1) << UART_CR_UTX_END_MASK_POS)) -#define UART_CR_URX_END_MASK UART_CR_URX_END_MASK -#define UART_CR_URX_END_MASK_POS (1U) -#define UART_CR_URX_END_MASK_LEN (1U) -#define UART_CR_URX_END_MASK_MSK (((1U << UART_CR_URX_END_MASK_LEN) - 1) << UART_CR_URX_END_MASK_POS) -#define UART_CR_URX_END_MASK_UMSK (~(((1U << UART_CR_URX_END_MASK_LEN) - 1) << UART_CR_URX_END_MASK_POS)) -#define UART_CR_UTX_FRDY_MASK UART_CR_UTX_FRDY_MASK -#define UART_CR_UTX_FRDY_MASK_POS (2U) -#define UART_CR_UTX_FRDY_MASK_LEN (1U) -#define UART_CR_UTX_FRDY_MASK_MSK (((1U << UART_CR_UTX_FRDY_MASK_LEN) - 1) << UART_CR_UTX_FRDY_MASK_POS) -#define UART_CR_UTX_FRDY_MASK_UMSK (~(((1U << UART_CR_UTX_FRDY_MASK_LEN) - 1) << UART_CR_UTX_FRDY_MASK_POS)) -#define UART_CR_URX_FRDY_MASK UART_CR_URX_FRDY_MASK -#define UART_CR_URX_FRDY_MASK_POS (3U) -#define UART_CR_URX_FRDY_MASK_LEN (1U) -#define UART_CR_URX_FRDY_MASK_MSK (((1U << UART_CR_URX_FRDY_MASK_LEN) - 1) << UART_CR_URX_FRDY_MASK_POS) -#define UART_CR_URX_FRDY_MASK_UMSK (~(((1U << UART_CR_URX_FRDY_MASK_LEN) - 1) << UART_CR_URX_FRDY_MASK_POS)) -#define UART_CR_URX_RTO_MASK UART_CR_URX_RTO_MASK -#define UART_CR_URX_RTO_MASK_POS (4U) -#define UART_CR_URX_RTO_MASK_LEN (1U) -#define UART_CR_URX_RTO_MASK_MSK (((1U << UART_CR_URX_RTO_MASK_LEN) - 1) << UART_CR_URX_RTO_MASK_POS) -#define UART_CR_URX_RTO_MASK_UMSK (~(((1U << UART_CR_URX_RTO_MASK_LEN) - 1) << UART_CR_URX_RTO_MASK_POS)) -#define UART_CR_URX_PCE_MASK UART_CR_URX_PCE_MASK -#define UART_CR_URX_PCE_MASK_POS (5U) -#define UART_CR_URX_PCE_MASK_LEN (1U) -#define UART_CR_URX_PCE_MASK_MSK (((1U << UART_CR_URX_PCE_MASK_LEN) - 1) << UART_CR_URX_PCE_MASK_POS) -#define UART_CR_URX_PCE_MASK_UMSK (~(((1U << UART_CR_URX_PCE_MASK_LEN) - 1) << UART_CR_URX_PCE_MASK_POS)) -#define UART_CR_UTX_FER_MASK UART_CR_UTX_FER_MASK -#define UART_CR_UTX_FER_MASK_POS (6U) -#define UART_CR_UTX_FER_MASK_LEN (1U) -#define UART_CR_UTX_FER_MASK_MSK (((1U << UART_CR_UTX_FER_MASK_LEN) - 1) << UART_CR_UTX_FER_MASK_POS) -#define UART_CR_UTX_FER_MASK_UMSK (~(((1U << UART_CR_UTX_FER_MASK_LEN) - 1) << UART_CR_UTX_FER_MASK_POS)) -#define UART_CR_URX_FER_MASK UART_CR_URX_FER_MASK -#define UART_CR_URX_FER_MASK_POS (7U) -#define UART_CR_URX_FER_MASK_LEN (1U) -#define UART_CR_URX_FER_MASK_MSK (((1U << UART_CR_URX_FER_MASK_LEN) - 1) << UART_CR_URX_FER_MASK_POS) -#define UART_CR_URX_FER_MASK_UMSK (~(((1U << UART_CR_URX_FER_MASK_LEN) - 1) << UART_CR_URX_FER_MASK_POS)) -#define UART_CR_URX_LSE_MASK UART_CR_URX_LSE_MASK -#define UART_CR_URX_LSE_MASK_POS (8U) -#define UART_CR_URX_LSE_MASK_LEN (1U) -#define UART_CR_URX_LSE_MASK_MSK (((1U << UART_CR_URX_LSE_MASK_LEN) - 1) << UART_CR_URX_LSE_MASK_POS) -#define UART_CR_URX_LSE_MASK_UMSK (~(((1U << UART_CR_URX_LSE_MASK_LEN) - 1) << UART_CR_URX_LSE_MASK_POS)) -#define UART_CR_URX_BCR_MASK UART_CR_URX_BCR_MASK -#define UART_CR_URX_BCR_MASK_POS (9U) -#define UART_CR_URX_BCR_MASK_LEN (1U) -#define UART_CR_URX_BCR_MASK_MSK (((1U << UART_CR_URX_BCR_MASK_LEN) - 1) << UART_CR_URX_BCR_MASK_POS) -#define UART_CR_URX_BCR_MASK_UMSK (~(((1U << UART_CR_URX_BCR_MASK_LEN) - 1) << UART_CR_URX_BCR_MASK_POS)) -#define UART_CR_URX_ADS_MASK UART_CR_URX_ADS_MASK -#define UART_CR_URX_ADS_MASK_POS (10U) -#define UART_CR_URX_ADS_MASK_LEN (1U) -#define UART_CR_URX_ADS_MASK_MSK (((1U << UART_CR_URX_ADS_MASK_LEN) - 1) << UART_CR_URX_ADS_MASK_POS) -#define UART_CR_URX_ADS_MASK_UMSK (~(((1U << UART_CR_URX_ADS_MASK_LEN) - 1) << UART_CR_URX_ADS_MASK_POS)) -#define UART_CR_URX_AD5_MASK UART_CR_URX_AD5_MASK -#define UART_CR_URX_AD5_MASK_POS (11U) -#define UART_CR_URX_AD5_MASK_LEN (1U) -#define UART_CR_URX_AD5_MASK_MSK (((1U << UART_CR_URX_AD5_MASK_LEN) - 1) << UART_CR_URX_AD5_MASK_POS) -#define UART_CR_URX_AD5_MASK_UMSK (~(((1U << UART_CR_URX_AD5_MASK_LEN) - 1) << UART_CR_URX_AD5_MASK_POS)) - -/* 0x28 : UART interrupt clear */ -#define UART_INT_CLEAR_OFFSET (0x28) -#define UART_CR_UTX_END_CLR UART_CR_UTX_END_CLR -#define UART_CR_UTX_END_CLR_POS (0U) -#define UART_CR_UTX_END_CLR_LEN (1U) -#define UART_CR_UTX_END_CLR_MSK (((1U << UART_CR_UTX_END_CLR_LEN) - 1) << UART_CR_UTX_END_CLR_POS) -#define UART_CR_UTX_END_CLR_UMSK (~(((1U << UART_CR_UTX_END_CLR_LEN) - 1) << UART_CR_UTX_END_CLR_POS)) -#define UART_CR_URX_END_CLR UART_CR_URX_END_CLR -#define UART_CR_URX_END_CLR_POS (1U) -#define UART_CR_URX_END_CLR_LEN (1U) -#define UART_CR_URX_END_CLR_MSK (((1U << UART_CR_URX_END_CLR_LEN) - 1) << UART_CR_URX_END_CLR_POS) -#define UART_CR_URX_END_CLR_UMSK (~(((1U << UART_CR_URX_END_CLR_LEN) - 1) << UART_CR_URX_END_CLR_POS)) -#define UART_CR_URX_RTO_CLR UART_CR_URX_RTO_CLR -#define UART_CR_URX_RTO_CLR_POS (4U) -#define UART_CR_URX_RTO_CLR_LEN (1U) -#define UART_CR_URX_RTO_CLR_MSK (((1U << UART_CR_URX_RTO_CLR_LEN) - 1) << UART_CR_URX_RTO_CLR_POS) -#define UART_CR_URX_RTO_CLR_UMSK (~(((1U << UART_CR_URX_RTO_CLR_LEN) - 1) << UART_CR_URX_RTO_CLR_POS)) -#define UART_CR_URX_PCE_CLR UART_CR_URX_PCE_CLR -#define UART_CR_URX_PCE_CLR_POS (5U) -#define UART_CR_URX_PCE_CLR_LEN (1U) -#define UART_CR_URX_PCE_CLR_MSK (((1U << UART_CR_URX_PCE_CLR_LEN) - 1) << UART_CR_URX_PCE_CLR_POS) -#define UART_CR_URX_PCE_CLR_UMSK (~(((1U << UART_CR_URX_PCE_CLR_LEN) - 1) << UART_CR_URX_PCE_CLR_POS)) -#define UART_CR_URX_LSE_CLR UART_CR_URX_LSE_CLR -#define UART_CR_URX_LSE_CLR_POS (8U) -#define UART_CR_URX_LSE_CLR_LEN (1U) -#define UART_CR_URX_LSE_CLR_MSK (((1U << UART_CR_URX_LSE_CLR_LEN) - 1) << UART_CR_URX_LSE_CLR_POS) -#define UART_CR_URX_LSE_CLR_UMSK (~(((1U << UART_CR_URX_LSE_CLR_LEN) - 1) << UART_CR_URX_LSE_CLR_POS)) -#define UART_CR_URX_BCR_CLR UART_CR_URX_BCR_CLR -#define UART_CR_URX_BCR_CLR_POS (9U) -#define UART_CR_URX_BCR_CLR_LEN (1U) -#define UART_CR_URX_BCR_CLR_MSK (((1U << UART_CR_URX_BCR_CLR_LEN) - 1) << UART_CR_URX_BCR_CLR_POS) -#define UART_CR_URX_BCR_CLR_UMSK (~(((1U << UART_CR_URX_BCR_CLR_LEN) - 1) << UART_CR_URX_BCR_CLR_POS)) -#define UART_CR_URX_ADS_CLR UART_CR_URX_ADS_CLR -#define UART_CR_URX_ADS_CLR_POS (10U) -#define UART_CR_URX_ADS_CLR_LEN (1U) -#define UART_CR_URX_ADS_CLR_MSK (((1U << UART_CR_URX_ADS_CLR_LEN) - 1) << UART_CR_URX_ADS_CLR_POS) -#define UART_CR_URX_ADS_CLR_UMSK (~(((1U << UART_CR_URX_ADS_CLR_LEN) - 1) << UART_CR_URX_ADS_CLR_POS)) -#define UART_CR_URX_AD5_CLR UART_CR_URX_AD5_CLR -#define UART_CR_URX_AD5_CLR_POS (11U) -#define UART_CR_URX_AD5_CLR_LEN (1U) -#define UART_CR_URX_AD5_CLR_MSK (((1U << UART_CR_URX_AD5_CLR_LEN) - 1) << UART_CR_URX_AD5_CLR_POS) -#define UART_CR_URX_AD5_CLR_UMSK (~(((1U << UART_CR_URX_AD5_CLR_LEN) - 1) << UART_CR_URX_AD5_CLR_POS)) - -/* 0x2C : UART interrupt enable */ -#define UART_INT_EN_OFFSET (0x2C) -#define UART_CR_UTX_END_EN UART_CR_UTX_END_EN -#define UART_CR_UTX_END_EN_POS (0U) -#define UART_CR_UTX_END_EN_LEN (1U) -#define UART_CR_UTX_END_EN_MSK (((1U << UART_CR_UTX_END_EN_LEN) - 1) << UART_CR_UTX_END_EN_POS) -#define UART_CR_UTX_END_EN_UMSK (~(((1U << UART_CR_UTX_END_EN_LEN) - 1) << UART_CR_UTX_END_EN_POS)) -#define UART_CR_URX_END_EN UART_CR_URX_END_EN -#define UART_CR_URX_END_EN_POS (1U) -#define UART_CR_URX_END_EN_LEN (1U) -#define UART_CR_URX_END_EN_MSK (((1U << UART_CR_URX_END_EN_LEN) - 1) << UART_CR_URX_END_EN_POS) -#define UART_CR_URX_END_EN_UMSK (~(((1U << UART_CR_URX_END_EN_LEN) - 1) << UART_CR_URX_END_EN_POS)) -#define UART_CR_UTX_FRDY_EN UART_CR_UTX_FRDY_EN -#define UART_CR_UTX_FRDY_EN_POS (2U) -#define UART_CR_UTX_FRDY_EN_LEN (1U) -#define UART_CR_UTX_FRDY_EN_MSK (((1U << UART_CR_UTX_FRDY_EN_LEN) - 1) << UART_CR_UTX_FRDY_EN_POS) -#define UART_CR_UTX_FRDY_EN_UMSK (~(((1U << UART_CR_UTX_FRDY_EN_LEN) - 1) << UART_CR_UTX_FRDY_EN_POS)) -#define UART_CR_URX_FRDY_EN UART_CR_URX_FRDY_EN -#define UART_CR_URX_FRDY_EN_POS (3U) -#define UART_CR_URX_FRDY_EN_LEN (1U) -#define UART_CR_URX_FRDY_EN_MSK (((1U << UART_CR_URX_FRDY_EN_LEN) - 1) << UART_CR_URX_FRDY_EN_POS) -#define UART_CR_URX_FRDY_EN_UMSK (~(((1U << UART_CR_URX_FRDY_EN_LEN) - 1) << UART_CR_URX_FRDY_EN_POS)) -#define UART_CR_URX_RTO_EN UART_CR_URX_RTO_EN -#define UART_CR_URX_RTO_EN_POS (4U) -#define UART_CR_URX_RTO_EN_LEN (1U) -#define UART_CR_URX_RTO_EN_MSK (((1U << UART_CR_URX_RTO_EN_LEN) - 1) << UART_CR_URX_RTO_EN_POS) -#define UART_CR_URX_RTO_EN_UMSK (~(((1U << UART_CR_URX_RTO_EN_LEN) - 1) << UART_CR_URX_RTO_EN_POS)) -#define UART_CR_URX_PCE_EN UART_CR_URX_PCE_EN -#define UART_CR_URX_PCE_EN_POS (5U) -#define UART_CR_URX_PCE_EN_LEN (1U) -#define UART_CR_URX_PCE_EN_MSK (((1U << UART_CR_URX_PCE_EN_LEN) - 1) << UART_CR_URX_PCE_EN_POS) -#define UART_CR_URX_PCE_EN_UMSK (~(((1U << UART_CR_URX_PCE_EN_LEN) - 1) << UART_CR_URX_PCE_EN_POS)) -#define UART_CR_UTX_FER_EN UART_CR_UTX_FER_EN -#define UART_CR_UTX_FER_EN_POS (6U) -#define UART_CR_UTX_FER_EN_LEN (1U) -#define UART_CR_UTX_FER_EN_MSK (((1U << UART_CR_UTX_FER_EN_LEN) - 1) << UART_CR_UTX_FER_EN_POS) -#define UART_CR_UTX_FER_EN_UMSK (~(((1U << UART_CR_UTX_FER_EN_LEN) - 1) << UART_CR_UTX_FER_EN_POS)) -#define UART_CR_URX_FER_EN UART_CR_URX_FER_EN -#define UART_CR_URX_FER_EN_POS (7U) -#define UART_CR_URX_FER_EN_LEN (1U) -#define UART_CR_URX_FER_EN_MSK (((1U << UART_CR_URX_FER_EN_LEN) - 1) << UART_CR_URX_FER_EN_POS) -#define UART_CR_URX_FER_EN_UMSK (~(((1U << UART_CR_URX_FER_EN_LEN) - 1) << UART_CR_URX_FER_EN_POS)) -#define UART_CR_URX_LSE_EN UART_CR_URX_LSE_EN -#define UART_CR_URX_LSE_EN_POS (8U) -#define UART_CR_URX_LSE_EN_LEN (1U) -#define UART_CR_URX_LSE_EN_MSK (((1U << UART_CR_URX_LSE_EN_LEN) - 1) << UART_CR_URX_LSE_EN_POS) -#define UART_CR_URX_LSE_EN_UMSK (~(((1U << UART_CR_URX_LSE_EN_LEN) - 1) << UART_CR_URX_LSE_EN_POS)) -#define UART_CR_URX_BCR_EN UART_CR_URX_BCR_EN -#define UART_CR_URX_BCR_EN_POS (9U) -#define UART_CR_URX_BCR_EN_LEN (1U) -#define UART_CR_URX_BCR_EN_MSK (((1U << UART_CR_URX_BCR_EN_LEN) - 1) << UART_CR_URX_BCR_EN_POS) -#define UART_CR_URX_BCR_EN_UMSK (~(((1U << UART_CR_URX_BCR_EN_LEN) - 1) << UART_CR_URX_BCR_EN_POS)) -#define UART_CR_URX_ADS_EN UART_CR_URX_ADS_EN -#define UART_CR_URX_ADS_EN_POS (10U) -#define UART_CR_URX_ADS_EN_LEN (1U) -#define UART_CR_URX_ADS_EN_MSK (((1U << UART_CR_URX_ADS_EN_LEN) - 1) << UART_CR_URX_ADS_EN_POS) -#define UART_CR_URX_ADS_EN_UMSK (~(((1U << UART_CR_URX_ADS_EN_LEN) - 1) << UART_CR_URX_ADS_EN_POS)) -#define UART_CR_URX_AD5_EN UART_CR_URX_AD5_EN -#define UART_CR_URX_AD5_EN_POS (11U) -#define UART_CR_URX_AD5_EN_LEN (1U) -#define UART_CR_URX_AD5_EN_MSK (((1U << UART_CR_URX_AD5_EN_LEN) - 1) << UART_CR_URX_AD5_EN_POS) -#define UART_CR_URX_AD5_EN_UMSK (~(((1U << UART_CR_URX_AD5_EN_LEN) - 1) << UART_CR_URX_AD5_EN_POS)) - -/* 0x30 : uart_status */ -#define UART_STATUS_OFFSET (0x30) -#define UART_STS_UTX_BUS_BUSY UART_STS_UTX_BUS_BUSY -#define UART_STS_UTX_BUS_BUSY_POS (0U) -#define UART_STS_UTX_BUS_BUSY_LEN (1U) -#define UART_STS_UTX_BUS_BUSY_MSK (((1U << UART_STS_UTX_BUS_BUSY_LEN) - 1) << UART_STS_UTX_BUS_BUSY_POS) -#define UART_STS_UTX_BUS_BUSY_UMSK (~(((1U << UART_STS_UTX_BUS_BUSY_LEN) - 1) << UART_STS_UTX_BUS_BUSY_POS)) -#define UART_STS_URX_BUS_BUSY UART_STS_URX_BUS_BUSY -#define UART_STS_URX_BUS_BUSY_POS (1U) -#define UART_STS_URX_BUS_BUSY_LEN (1U) -#define UART_STS_URX_BUS_BUSY_MSK (((1U << UART_STS_URX_BUS_BUSY_LEN) - 1) << UART_STS_URX_BUS_BUSY_POS) -#define UART_STS_URX_BUS_BUSY_UMSK (~(((1U << UART_STS_URX_BUS_BUSY_LEN) - 1) << UART_STS_URX_BUS_BUSY_POS)) - -/* 0x34 : sts_urx_abr_prd */ -#define UART_STS_URX_ABR_PRD_OFFSET (0x34) -#define UART_STS_URX_ABR_PRD_START UART_STS_URX_ABR_PRD_START -#define UART_STS_URX_ABR_PRD_START_POS (0U) -#define UART_STS_URX_ABR_PRD_START_LEN (16U) -#define UART_STS_URX_ABR_PRD_START_MSK (((1U << UART_STS_URX_ABR_PRD_START_LEN) - 1) << UART_STS_URX_ABR_PRD_START_POS) -#define UART_STS_URX_ABR_PRD_START_UMSK (~(((1U << UART_STS_URX_ABR_PRD_START_LEN) - 1) << UART_STS_URX_ABR_PRD_START_POS)) -#define UART_STS_URX_ABR_PRD_0X55 UART_STS_URX_ABR_PRD_0X55 -#define UART_STS_URX_ABR_PRD_0X55_POS (16U) -#define UART_STS_URX_ABR_PRD_0X55_LEN (16U) -#define UART_STS_URX_ABR_PRD_0X55_MSK (((1U << UART_STS_URX_ABR_PRD_0X55_LEN) - 1) << UART_STS_URX_ABR_PRD_0X55_POS) -#define UART_STS_URX_ABR_PRD_0X55_UMSK (~(((1U << UART_STS_URX_ABR_PRD_0X55_LEN) - 1) << UART_STS_URX_ABR_PRD_0X55_POS)) - -/* 0x38 : urx_abr_prd_b01 */ -#define UART_URX_ABR_PRD_B01_OFFSET (0x38) -#define UART_STS_URX_ABR_PRD_BIT0 UART_STS_URX_ABR_PRD_BIT0 -#define UART_STS_URX_ABR_PRD_BIT0_POS (0U) -#define UART_STS_URX_ABR_PRD_BIT0_LEN (16U) -#define UART_STS_URX_ABR_PRD_BIT0_MSK (((1U << UART_STS_URX_ABR_PRD_BIT0_LEN) - 1) << UART_STS_URX_ABR_PRD_BIT0_POS) -#define UART_STS_URX_ABR_PRD_BIT0_UMSK (~(((1U << UART_STS_URX_ABR_PRD_BIT0_LEN) - 1) << UART_STS_URX_ABR_PRD_BIT0_POS)) -#define UART_STS_URX_ABR_PRD_BIT1 UART_STS_URX_ABR_PRD_BIT1 -#define UART_STS_URX_ABR_PRD_BIT1_POS (16U) -#define UART_STS_URX_ABR_PRD_BIT1_LEN (16U) -#define UART_STS_URX_ABR_PRD_BIT1_MSK (((1U << UART_STS_URX_ABR_PRD_BIT1_LEN) - 1) << UART_STS_URX_ABR_PRD_BIT1_POS) -#define UART_STS_URX_ABR_PRD_BIT1_UMSK (~(((1U << UART_STS_URX_ABR_PRD_BIT1_LEN) - 1) << UART_STS_URX_ABR_PRD_BIT1_POS)) - -/* 0x3C : urx_abr_prd_b23 */ -#define UART_URX_ABR_PRD_B23_OFFSET (0x3C) -#define UART_STS_URX_ABR_PRD_BIT2 UART_STS_URX_ABR_PRD_BIT2 -#define UART_STS_URX_ABR_PRD_BIT2_POS (0U) -#define UART_STS_URX_ABR_PRD_BIT2_LEN (16U) -#define UART_STS_URX_ABR_PRD_BIT2_MSK (((1U << UART_STS_URX_ABR_PRD_BIT2_LEN) - 1) << UART_STS_URX_ABR_PRD_BIT2_POS) -#define UART_STS_URX_ABR_PRD_BIT2_UMSK (~(((1U << UART_STS_URX_ABR_PRD_BIT2_LEN) - 1) << UART_STS_URX_ABR_PRD_BIT2_POS)) -#define UART_STS_URX_ABR_PRD_BIT3 UART_STS_URX_ABR_PRD_BIT3 -#define UART_STS_URX_ABR_PRD_BIT3_POS (16U) -#define UART_STS_URX_ABR_PRD_BIT3_LEN (16U) -#define UART_STS_URX_ABR_PRD_BIT3_MSK (((1U << UART_STS_URX_ABR_PRD_BIT3_LEN) - 1) << UART_STS_URX_ABR_PRD_BIT3_POS) -#define UART_STS_URX_ABR_PRD_BIT3_UMSK (~(((1U << UART_STS_URX_ABR_PRD_BIT3_LEN) - 1) << UART_STS_URX_ABR_PRD_BIT3_POS)) - -/* 0x40 : urx_abr_prd_b45 */ -#define UART_URX_ABR_PRD_B45_OFFSET (0x40) -#define UART_STS_URX_ABR_PRD_BIT4 UART_STS_URX_ABR_PRD_BIT4 -#define UART_STS_URX_ABR_PRD_BIT4_POS (0U) -#define UART_STS_URX_ABR_PRD_BIT4_LEN (16U) -#define UART_STS_URX_ABR_PRD_BIT4_MSK (((1U << UART_STS_URX_ABR_PRD_BIT4_LEN) - 1) << UART_STS_URX_ABR_PRD_BIT4_POS) -#define UART_STS_URX_ABR_PRD_BIT4_UMSK (~(((1U << UART_STS_URX_ABR_PRD_BIT4_LEN) - 1) << UART_STS_URX_ABR_PRD_BIT4_POS)) -#define UART_STS_URX_ABR_PRD_BIT5 UART_STS_URX_ABR_PRD_BIT5 -#define UART_STS_URX_ABR_PRD_BIT5_POS (16U) -#define UART_STS_URX_ABR_PRD_BIT5_LEN (16U) -#define UART_STS_URX_ABR_PRD_BIT5_MSK (((1U << UART_STS_URX_ABR_PRD_BIT5_LEN) - 1) << UART_STS_URX_ABR_PRD_BIT5_POS) -#define UART_STS_URX_ABR_PRD_BIT5_UMSK (~(((1U << UART_STS_URX_ABR_PRD_BIT5_LEN) - 1) << UART_STS_URX_ABR_PRD_BIT5_POS)) - -/* 0x44 : urx_abr_prd_b67 */ -#define UART_URX_ABR_PRD_B67_OFFSET (0x44) -#define UART_STS_URX_ABR_PRD_BIT6 UART_STS_URX_ABR_PRD_BIT6 -#define UART_STS_URX_ABR_PRD_BIT6_POS (0U) -#define UART_STS_URX_ABR_PRD_BIT6_LEN (16U) -#define UART_STS_URX_ABR_PRD_BIT6_MSK (((1U << UART_STS_URX_ABR_PRD_BIT6_LEN) - 1) << UART_STS_URX_ABR_PRD_BIT6_POS) -#define UART_STS_URX_ABR_PRD_BIT6_UMSK (~(((1U << UART_STS_URX_ABR_PRD_BIT6_LEN) - 1) << UART_STS_URX_ABR_PRD_BIT6_POS)) -#define UART_STS_URX_ABR_PRD_BIT7 UART_STS_URX_ABR_PRD_BIT7 -#define UART_STS_URX_ABR_PRD_BIT7_POS (16U) -#define UART_STS_URX_ABR_PRD_BIT7_LEN (16U) -#define UART_STS_URX_ABR_PRD_BIT7_MSK (((1U << UART_STS_URX_ABR_PRD_BIT7_LEN) - 1) << UART_STS_URX_ABR_PRD_BIT7_POS) -#define UART_STS_URX_ABR_PRD_BIT7_UMSK (~(((1U << UART_STS_URX_ABR_PRD_BIT7_LEN) - 1) << UART_STS_URX_ABR_PRD_BIT7_POS)) - -/* 0x48 : urx_abr_pw_tol */ -#define UART_URX_ABR_PW_TOL_OFFSET (0x48) -#define UART_CR_URX_ABR_PW_TOL UART_CR_URX_ABR_PW_TOL -#define UART_CR_URX_ABR_PW_TOL_POS (0U) -#define UART_CR_URX_ABR_PW_TOL_LEN (8U) -#define UART_CR_URX_ABR_PW_TOL_MSK (((1U << UART_CR_URX_ABR_PW_TOL_LEN) - 1) << UART_CR_URX_ABR_PW_TOL_POS) -#define UART_CR_URX_ABR_PW_TOL_UMSK (~(((1U << UART_CR_URX_ABR_PW_TOL_LEN) - 1) << UART_CR_URX_ABR_PW_TOL_POS)) - -/* 0x50 : urx_bcr_int_cfg */ -#define UART_URX_BCR_INT_CFG_OFFSET (0x50) -#define UART_CR_URX_BCR_VALUE UART_CR_URX_BCR_VALUE -#define UART_CR_URX_BCR_VALUE_POS (0U) -#define UART_CR_URX_BCR_VALUE_LEN (16U) -#define UART_CR_URX_BCR_VALUE_MSK (((1U << UART_CR_URX_BCR_VALUE_LEN) - 1) << UART_CR_URX_BCR_VALUE_POS) -#define UART_CR_URX_BCR_VALUE_UMSK (~(((1U << UART_CR_URX_BCR_VALUE_LEN) - 1) << UART_CR_URX_BCR_VALUE_POS)) -#define UART_STS_URX_BCR_COUNT UART_STS_URX_BCR_COUNT -#define UART_STS_URX_BCR_COUNT_POS (16U) -#define UART_STS_URX_BCR_COUNT_LEN (16U) -#define UART_STS_URX_BCR_COUNT_MSK (((1U << UART_STS_URX_BCR_COUNT_LEN) - 1) << UART_STS_URX_BCR_COUNT_POS) -#define UART_STS_URX_BCR_COUNT_UMSK (~(((1U << UART_STS_URX_BCR_COUNT_LEN) - 1) << UART_STS_URX_BCR_COUNT_POS)) - -/* 0x54 : utx_rs485_cfg */ -#define UART_UTX_RS485_CFG_OFFSET (0x54) -#define UART_CR_UTX_RS485_EN UART_CR_UTX_RS485_EN -#define UART_CR_UTX_RS485_EN_POS (0U) -#define UART_CR_UTX_RS485_EN_LEN (1U) -#define UART_CR_UTX_RS485_EN_MSK (((1U << UART_CR_UTX_RS485_EN_LEN) - 1) << UART_CR_UTX_RS485_EN_POS) -#define UART_CR_UTX_RS485_EN_UMSK (~(((1U << UART_CR_UTX_RS485_EN_LEN) - 1) << UART_CR_UTX_RS485_EN_POS)) -#define UART_CR_UTX_RS485_POL UART_CR_UTX_RS485_POL -#define UART_CR_UTX_RS485_POL_POS (1U) -#define UART_CR_UTX_RS485_POL_LEN (1U) -#define UART_CR_UTX_RS485_POL_MSK (((1U << UART_CR_UTX_RS485_POL_LEN) - 1) << UART_CR_UTX_RS485_POL_POS) -#define UART_CR_UTX_RS485_POL_UMSK (~(((1U << UART_CR_UTX_RS485_POL_LEN) - 1) << UART_CR_UTX_RS485_POL_POS)) - -/* 0x80 : uart_fifo_config_0 */ -#define UART_FIFO_CONFIG_0_OFFSET (0x80) -#define UART_DMA_TX_EN UART_DMA_TX_EN -#define UART_DMA_TX_EN_POS (0U) -#define UART_DMA_TX_EN_LEN (1U) -#define UART_DMA_TX_EN_MSK (((1U << UART_DMA_TX_EN_LEN) - 1) << UART_DMA_TX_EN_POS) -#define UART_DMA_TX_EN_UMSK (~(((1U << UART_DMA_TX_EN_LEN) - 1) << UART_DMA_TX_EN_POS)) -#define UART_DMA_RX_EN UART_DMA_RX_EN -#define UART_DMA_RX_EN_POS (1U) -#define UART_DMA_RX_EN_LEN (1U) -#define UART_DMA_RX_EN_MSK (((1U << UART_DMA_RX_EN_LEN) - 1) << UART_DMA_RX_EN_POS) -#define UART_DMA_RX_EN_UMSK (~(((1U << UART_DMA_RX_EN_LEN) - 1) << UART_DMA_RX_EN_POS)) -#define UART_TX_FIFO_CLR UART_TX_FIFO_CLR -#define UART_TX_FIFO_CLR_POS (2U) -#define UART_TX_FIFO_CLR_LEN (1U) -#define UART_TX_FIFO_CLR_MSK (((1U << UART_TX_FIFO_CLR_LEN) - 1) << UART_TX_FIFO_CLR_POS) -#define UART_TX_FIFO_CLR_UMSK (~(((1U << UART_TX_FIFO_CLR_LEN) - 1) << UART_TX_FIFO_CLR_POS)) -#define UART_RX_FIFO_CLR UART_RX_FIFO_CLR -#define UART_RX_FIFO_CLR_POS (3U) -#define UART_RX_FIFO_CLR_LEN (1U) -#define UART_RX_FIFO_CLR_MSK (((1U << UART_RX_FIFO_CLR_LEN) - 1) << UART_RX_FIFO_CLR_POS) -#define UART_RX_FIFO_CLR_UMSK (~(((1U << UART_RX_FIFO_CLR_LEN) - 1) << UART_RX_FIFO_CLR_POS)) -#define UART_TX_FIFO_OVERFLOW UART_TX_FIFO_OVERFLOW -#define UART_TX_FIFO_OVERFLOW_POS (4U) -#define UART_TX_FIFO_OVERFLOW_LEN (1U) -#define UART_TX_FIFO_OVERFLOW_MSK (((1U << UART_TX_FIFO_OVERFLOW_LEN) - 1) << UART_TX_FIFO_OVERFLOW_POS) -#define UART_TX_FIFO_OVERFLOW_UMSK (~(((1U << UART_TX_FIFO_OVERFLOW_LEN) - 1) << UART_TX_FIFO_OVERFLOW_POS)) -#define UART_TX_FIFO_UNDERFLOW UART_TX_FIFO_UNDERFLOW -#define UART_TX_FIFO_UNDERFLOW_POS (5U) -#define UART_TX_FIFO_UNDERFLOW_LEN (1U) -#define UART_TX_FIFO_UNDERFLOW_MSK (((1U << UART_TX_FIFO_UNDERFLOW_LEN) - 1) << UART_TX_FIFO_UNDERFLOW_POS) -#define UART_TX_FIFO_UNDERFLOW_UMSK (~(((1U << UART_TX_FIFO_UNDERFLOW_LEN) - 1) << UART_TX_FIFO_UNDERFLOW_POS)) -#define UART_RX_FIFO_OVERFLOW UART_RX_FIFO_OVERFLOW -#define UART_RX_FIFO_OVERFLOW_POS (6U) -#define UART_RX_FIFO_OVERFLOW_LEN (1U) -#define UART_RX_FIFO_OVERFLOW_MSK (((1U << UART_RX_FIFO_OVERFLOW_LEN) - 1) << UART_RX_FIFO_OVERFLOW_POS) -#define UART_RX_FIFO_OVERFLOW_UMSK (~(((1U << UART_RX_FIFO_OVERFLOW_LEN) - 1) << UART_RX_FIFO_OVERFLOW_POS)) -#define UART_RX_FIFO_UNDERFLOW UART_RX_FIFO_UNDERFLOW -#define UART_RX_FIFO_UNDERFLOW_POS (7U) -#define UART_RX_FIFO_UNDERFLOW_LEN (1U) -#define UART_RX_FIFO_UNDERFLOW_MSK (((1U << UART_RX_FIFO_UNDERFLOW_LEN) - 1) << UART_RX_FIFO_UNDERFLOW_POS) -#define UART_RX_FIFO_UNDERFLOW_UMSK (~(((1U << UART_RX_FIFO_UNDERFLOW_LEN) - 1) << UART_RX_FIFO_UNDERFLOW_POS)) - -/* 0x84 : uart_fifo_config_1 */ -#define UART_FIFO_CONFIG_1_OFFSET (0x84) -#define UART_TX_FIFO_CNT UART_TX_FIFO_CNT -#define UART_TX_FIFO_CNT_POS (0U) -#define UART_TX_FIFO_CNT_LEN (6U) -#define UART_TX_FIFO_CNT_MSK (((1U << UART_TX_FIFO_CNT_LEN) - 1) << UART_TX_FIFO_CNT_POS) -#define UART_TX_FIFO_CNT_UMSK (~(((1U << UART_TX_FIFO_CNT_LEN) - 1) << UART_TX_FIFO_CNT_POS)) -#define UART_RX_FIFO_CNT UART_RX_FIFO_CNT -#define UART_RX_FIFO_CNT_POS (8U) -#define UART_RX_FIFO_CNT_LEN (6U) -#define UART_RX_FIFO_CNT_MSK (((1U << UART_RX_FIFO_CNT_LEN) - 1) << UART_RX_FIFO_CNT_POS) -#define UART_RX_FIFO_CNT_UMSK (~(((1U << UART_RX_FIFO_CNT_LEN) - 1) << UART_RX_FIFO_CNT_POS)) -#define UART_TX_FIFO_TH UART_TX_FIFO_TH -#define UART_TX_FIFO_TH_POS (16U) -#define UART_TX_FIFO_TH_LEN (5U) -#define UART_TX_FIFO_TH_MSK (((1U << UART_TX_FIFO_TH_LEN) - 1) << UART_TX_FIFO_TH_POS) -#define UART_TX_FIFO_TH_UMSK (~(((1U << UART_TX_FIFO_TH_LEN) - 1) << UART_TX_FIFO_TH_POS)) -#define UART_RX_FIFO_TH UART_RX_FIFO_TH -#define UART_RX_FIFO_TH_POS (24U) -#define UART_RX_FIFO_TH_LEN (5U) -#define UART_RX_FIFO_TH_MSK (((1U << UART_RX_FIFO_TH_LEN) - 1) << UART_RX_FIFO_TH_POS) -#define UART_RX_FIFO_TH_UMSK (~(((1U << UART_RX_FIFO_TH_LEN) - 1) << UART_RX_FIFO_TH_POS)) - -/* 0x88 : uart_fifo_wdata */ -#define UART_FIFO_WDATA_OFFSET (0x88) -#define UART_FIFO_WDATA UART_FIFO_WDATA -#define UART_FIFO_WDATA_POS (0U) -#define UART_FIFO_WDATA_LEN (8U) -#define UART_FIFO_WDATA_MSK (((1U << UART_FIFO_WDATA_LEN) - 1) << UART_FIFO_WDATA_POS) -#define UART_FIFO_WDATA_UMSK (~(((1U << UART_FIFO_WDATA_LEN) - 1) << UART_FIFO_WDATA_POS)) - -/* 0x8C : uart_fifo_rdata */ -#define UART_FIFO_RDATA_OFFSET (0x8C) -#define UART_FIFO_RDATA UART_FIFO_RDATA -#define UART_FIFO_RDATA_POS (0U) -#define UART_FIFO_RDATA_LEN (8U) -#define UART_FIFO_RDATA_MSK (((1U << UART_FIFO_RDATA_LEN) - 1) << UART_FIFO_RDATA_POS) -#define UART_FIFO_RDATA_UMSK (~(((1U << UART_FIFO_RDATA_LEN) - 1) << UART_FIFO_RDATA_POS)) - -struct uart_reg { - /* 0x0 : utx_config */ - union { - struct { - uint32_t cr_utx_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t cr_utx_cts_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t cr_utx_frm_en : 1; /* [ 2], r/w, 0x0 */ - uint32_t cr_utx_lin_en : 1; /* [ 3], r/w, 0x0 */ - uint32_t cr_utx_prt_en : 1; /* [ 4], r/w, 0x0 */ - uint32_t cr_utx_prt_sel : 1; /* [ 5], r/w, 0x0 */ - uint32_t cr_utx_ir_en : 1; /* [ 6], r/w, 0x0 */ - uint32_t cr_utx_ir_inv : 1; /* [ 7], r/w, 0x0 */ - uint32_t cr_utx_bit_cnt_d : 3; /* [10: 8], r/w, 0x7 */ - uint32_t cr_utx_bit_cnt_p : 2; /* [12:11], r/w, 0x1 */ - uint32_t cr_utx_bit_cnt_b : 3; /* [15:13], r/w, 0x4 */ - uint32_t cr_utx_len : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } utx_config; - - /* 0x4 : urx_config */ - union { - struct { - uint32_t cr_urx_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t cr_urx_abr_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t reserved_2 : 1; /* [ 2], rsvd, 0x0 */ - uint32_t cr_urx_lin_en : 1; /* [ 3], r/w, 0x0 */ - uint32_t cr_urx_prt_en : 1; /* [ 4], r/w, 0x0 */ - uint32_t cr_urx_prt_sel : 1; /* [ 5], r/w, 0x0 */ - uint32_t cr_urx_ir_en : 1; /* [ 6], r/w, 0x0 */ - uint32_t cr_urx_ir_inv : 1; /* [ 7], r/w, 0x0 */ - uint32_t cr_urx_bit_cnt_d : 3; /* [10: 8], r/w, 0x7 */ - uint32_t cr_urx_deg_en : 1; /* [ 11], r/w, 0x0 */ - uint32_t cr_urx_deg_cnt : 4; /* [15:12], r/w, 0x0 */ - uint32_t cr_urx_len : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } urx_config; - - /* 0x8 : uart_bit_prd */ - union { - struct { - uint32_t cr_utx_bit_prd : 16; /* [15: 0], r/w, 0xff */ - uint32_t cr_urx_bit_prd : 16; /* [31:16], r/w, 0xff */ - } BF; - uint32_t WORD; - } uart_bit_prd; - - /* 0xC : data_config */ - union { - struct { - uint32_t cr_uart_bit_inv : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } data_config; - - /* 0x10 : utx_ir_position */ - union { - struct { - uint32_t cr_utx_ir_pos_s : 16; /* [15: 0], r/w, 0x70 */ - uint32_t cr_utx_ir_pos_p : 16; /* [31:16], r/w, 0x9f */ - } BF; - uint32_t WORD; - } utx_ir_position; - - /* 0x14 : urx_ir_position */ - union { - struct { - uint32_t cr_urx_ir_pos_s : 16; /* [15: 0], r/w, 0x6f */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } urx_ir_position; - - /* 0x18 : urx_rto_timer */ - union { - struct { - uint32_t cr_urx_rto_value : 8; /* [ 7: 0], r/w, 0xf */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } urx_rto_timer; - - /* 0x1C : uart_sw_mode */ - union { - struct { - uint32_t cr_utx_txd_sw_mode : 1; /* [ 0], r/w, 0x0 */ - uint32_t cr_utx_txd_sw_val : 1; /* [ 1], r/w, 0x0 */ - uint32_t cr_urx_rts_sw_mode : 1; /* [ 2], r/w, 0x0 */ - uint32_t cr_urx_rts_sw_val : 1; /* [ 3], r/w, 0x0 */ - uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } uart_sw_mode; - - /* 0x20 : UART interrupt status */ - union { - struct { - uint32_t utx_end_int : 1; /* [ 0], r, 0x0 */ - uint32_t urx_end_int : 1; /* [ 1], r, 0x0 */ - uint32_t utx_frdy_int : 1; /* [ 2], r, 0x1 */ - uint32_t urx_frdy_int : 1; /* [ 3], r, 0x0 */ - uint32_t urx_rto_int : 1; /* [ 4], r, 0x0 */ - uint32_t urx_pce_int : 1; /* [ 5], r, 0x0 */ - uint32_t utx_fer_int : 1; /* [ 6], r, 0x0 */ - uint32_t urx_fer_int : 1; /* [ 7], r, 0x0 */ - uint32_t urx_lse_int : 1; /* [ 8], r, 0x0 */ - uint32_t urx_bcr_int : 1; /* [ 9], r, 0x0 */ - uint32_t urx_ads_int : 1; /* [ 10], r, 0x0 */ - uint32_t urx_ad5_int : 1; /* [ 11], r, 0x0 */ - uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } uart_int_sts; - - /* 0x24 : UART interrupt mask */ - union { - struct { - uint32_t cr_utx_end_mask : 1; /* [ 0], r/w, 0x1 */ - uint32_t cr_urx_end_mask : 1; /* [ 1], r/w, 0x1 */ - uint32_t cr_utx_frdy_mask : 1; /* [ 2], r/w, 0x1 */ - uint32_t cr_urx_frdy_mask : 1; /* [ 3], r/w, 0x1 */ - uint32_t cr_urx_rto_mask : 1; /* [ 4], r/w, 0x1 */ - uint32_t cr_urx_pce_mask : 1; /* [ 5], r/w, 0x1 */ - uint32_t cr_utx_fer_mask : 1; /* [ 6], r/w, 0x1 */ - uint32_t cr_urx_fer_mask : 1; /* [ 7], r/w, 0x1 */ - uint32_t cr_urx_lse_mask : 1; /* [ 8], r/w, 0x1 */ - uint32_t cr_urx_bcr_mask : 1; /* [ 9], r/w, 0x1 */ - uint32_t cr_urx_ads_mask : 1; /* [ 10], r/w, 0x1 */ - uint32_t cr_urx_ad5_mask : 1; /* [ 11], r/w, 0x1 */ - uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } uart_int_mask; - - /* 0x28 : UART interrupt clear */ - union { - struct { - uint32_t cr_utx_end_clr : 1; /* [ 0], w1c, 0x0 */ - uint32_t cr_urx_end_clr : 1; /* [ 1], w1c, 0x0 */ - uint32_t rsvd_2 : 1; /* [ 2], rsvd, 0x0 */ - uint32_t rsvd_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t cr_urx_rto_clr : 1; /* [ 4], w1c, 0x0 */ - uint32_t cr_urx_pce_clr : 1; /* [ 5], w1c, 0x0 */ - uint32_t rsvd_6 : 1; /* [ 6], rsvd, 0x0 */ - uint32_t rsvd_7 : 1; /* [ 7], rsvd, 0x0 */ - uint32_t cr_urx_lse_clr : 1; /* [ 8], w1c, 0x0 */ - uint32_t cr_urx_bcr_clr : 1; /* [ 9], w1c, 0x0 */ - uint32_t cr_urx_ads_clr : 1; /* [ 10], w1c, 0x0 */ - uint32_t cr_urx_ad5_clr : 1; /* [ 11], w1c, 0x0 */ - uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } uart_int_clear; - - /* 0x2C : UART interrupt enable */ - union { - struct { - uint32_t cr_utx_end_en : 1; /* [ 0], r/w, 0x1 */ - uint32_t cr_urx_end_en : 1; /* [ 1], r/w, 0x1 */ - uint32_t cr_utx_frdy_en : 1; /* [ 2], r/w, 0x1 */ - uint32_t cr_urx_frdy_en : 1; /* [ 3], r/w, 0x1 */ - uint32_t cr_urx_rto_en : 1; /* [ 4], r/w, 0x1 */ - uint32_t cr_urx_pce_en : 1; /* [ 5], r/w, 0x1 */ - uint32_t cr_utx_fer_en : 1; /* [ 6], r/w, 0x1 */ - uint32_t cr_urx_fer_en : 1; /* [ 7], r/w, 0x1 */ - uint32_t cr_urx_lse_en : 1; /* [ 8], r/w, 0x1 */ - uint32_t cr_urx_bcr_en : 1; /* [ 9], r/w, 0x1 */ - uint32_t cr_urx_ads_en : 1; /* [ 10], r/w, 0x1 */ - uint32_t cr_urx_ad5_en : 1; /* [ 11], r/w, 0x1 */ - uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } uart_int_en; - - /* 0x30 : uart_status */ - union { - struct { - uint32_t sts_utx_bus_busy : 1; /* [ 0], r, 0x0 */ - uint32_t sts_urx_bus_busy : 1; /* [ 1], r, 0x0 */ - uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } uart_status; - - /* 0x34 : sts_urx_abr_prd */ - union { - struct { - uint32_t sts_urx_abr_prd_start : 16; /* [15: 0], r, 0x0 */ - uint32_t sts_urx_abr_prd_0x55 : 16; /* [31:16], r, 0x0 */ - } BF; - uint32_t WORD; - } sts_urx_abr_prd; - - /* 0x38 : urx_abr_prd_b01 */ - union { - struct { - uint32_t sts_urx_abr_prd_bit0 : 16; /* [15: 0], r, 0x0 */ - uint32_t sts_urx_abr_prd_bit1 : 16; /* [31:16], r, 0x0 */ - } BF; - uint32_t WORD; - } urx_abr_prd_b01; - - /* 0x3C : urx_abr_prd_b23 */ - union { - struct { - uint32_t sts_urx_abr_prd_bit2 : 16; /* [15: 0], r, 0x0 */ - uint32_t sts_urx_abr_prd_bit3 : 16; /* [31:16], r, 0x0 */ - } BF; - uint32_t WORD; - } urx_abr_prd_b23; - - /* 0x40 : urx_abr_prd_b45 */ - union { - struct { - uint32_t sts_urx_abr_prd_bit4 : 16; /* [15: 0], r, 0x0 */ - uint32_t sts_urx_abr_prd_bit5 : 16; /* [31:16], r, 0x0 */ - } BF; - uint32_t WORD; - } urx_abr_prd_b45; - - /* 0x44 : urx_abr_prd_b67 */ - union { - struct { - uint32_t sts_urx_abr_prd_bit6 : 16; /* [15: 0], r, 0x0 */ - uint32_t sts_urx_abr_prd_bit7 : 16; /* [31:16], r, 0x0 */ - } BF; - uint32_t WORD; - } urx_abr_prd_b67; - - /* 0x48 : urx_abr_pw_tol */ - union { - struct { - uint32_t cr_urx_abr_pw_tol : 8; /* [ 7: 0], r/w, 0x3 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } urx_abr_pw_tol; - - /* 0x4c reserved */ - uint8_t RESERVED0x4c[4]; - - /* 0x50 : urx_bcr_int_cfg */ - union { - struct { - uint32_t cr_urx_bcr_value : 16; /* [15: 0], r/w, 0xffff */ - uint32_t sts_urx_bcr_count : 16; /* [31:16], r, 0x0 */ - } BF; - uint32_t WORD; - } urx_bcr_int_cfg; - - /* 0x54 : utx_rs485_cfg */ - union { - struct { - uint32_t cr_utx_rs485_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t cr_utx_rs485_pol : 1; /* [ 1], r/w, 0x1 */ - uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } utx_rs485_cfg; - - /* 0x58 reserved */ - uint8_t RESERVED0x58[40]; - - /* 0x80 : uart_fifo_config_0 */ - union { - struct { - uint32_t uart_dma_tx_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t uart_dma_rx_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t tx_fifo_clr : 1; /* [ 2], w1c, 0x0 */ - uint32_t rx_fifo_clr : 1; /* [ 3], w1c, 0x0 */ - uint32_t tx_fifo_overflow : 1; /* [ 4], r, 0x0 */ - uint32_t tx_fifo_underflow : 1; /* [ 5], r, 0x0 */ - uint32_t rx_fifo_overflow : 1; /* [ 6], r, 0x0 */ - uint32_t rx_fifo_underflow : 1; /* [ 7], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } uart_fifo_config_0; - - /* 0x84 : uart_fifo_config_1 */ - union { - struct { - uint32_t tx_fifo_cnt : 6; /* [ 5: 0], r, 0x20 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t rx_fifo_cnt : 6; /* [13: 8], r, 0x0 */ - uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ - uint32_t tx_fifo_th : 5; /* [20:16], r/w, 0x0 */ - uint32_t reserved_21_23 : 3; /* [23:21], rsvd, 0x0 */ - uint32_t rx_fifo_th : 5; /* [28:24], r/w, 0x0 */ - uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } uart_fifo_config_1; - - /* 0x88 : uart_fifo_wdata */ - union { - struct { - uint32_t uart_fifo_wdata : 8; /* [ 7: 0], w, x */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } uart_fifo_wdata; - - /* 0x8C : uart_fifo_rdata */ - union { - struct { - uint32_t uart_fifo_rdata : 8; /* [ 7: 0], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } uart_fifo_rdata; -}; - -typedef volatile struct uart_reg uart_reg_t; - -#endif /* __UART_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/usb_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/usb_reg.h deleted file mode 100644 index 32c552ef54..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/usb_reg.h +++ /dev/null @@ -1,5352 +0,0 @@ -/** - ****************************************************************************** - * @file usb_reg.h - * @version V1.0 - * @date 2021-04-20 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __USB_REG_H__ -#define __USB_REG_H__ - -#include "bl808.h" - -/* 0x000 : HCCAP */ -#define USB_HCCAP_OFFSET (0x000) -#define USB_CAPLENGTH USB_CAPLENGTH -#define USB_CAPLENGTH_POS (0U) -#define USB_CAPLENGTH_LEN (8U) -#define USB_CAPLENGTH_MSK (((1U << USB_CAPLENGTH_LEN) - 1) << USB_CAPLENGTH_POS) -#define USB_CAPLENGTH_UMSK (~(((1U << USB_CAPLENGTH_LEN) - 1) << USB_CAPLENGTH_POS)) -#define USB_HCIVERSION USB_HCIVERSION -#define USB_HCIVERSION_POS (16U) -#define USB_HCIVERSION_LEN (16U) -#define USB_HCIVERSION_MSK (((1U << USB_HCIVERSION_LEN) - 1) << USB_HCIVERSION_POS) -#define USB_HCIVERSION_UMSK (~(((1U << USB_HCIVERSION_LEN) - 1) << USB_HCIVERSION_POS)) - -/* 0x004 : HCSPARAMS */ -#define USB_HCSPARAMS_OFFSET (0x004) -#define USB_N_PORTS USB_N_PORTS -#define USB_N_PORTS_POS (0U) -#define USB_N_PORTS_LEN (4U) -#define USB_N_PORTS_MSK (((1U << USB_N_PORTS_LEN) - 1) << USB_N_PORTS_POS) -#define USB_N_PORTS_UMSK (~(((1U << USB_N_PORTS_LEN) - 1) << USB_N_PORTS_POS)) - -/* 0x008 : HCCPARAMS */ -#define USB_HCCPARAMS_OFFSET (0x008) -#define USB_PROG_FR_LIST_FLAG USB_PROG_FR_LIST_FLAG -#define USB_PROG_FR_LIST_FLAG_POS (1U) -#define USB_PROG_FR_LIST_FLAG_LEN (1U) -#define USB_PROG_FR_LIST_FLAG_MSK (((1U << USB_PROG_FR_LIST_FLAG_LEN) - 1) << USB_PROG_FR_LIST_FLAG_POS) -#define USB_PROG_FR_LIST_FLAG_UMSK (~(((1U << USB_PROG_FR_LIST_FLAG_LEN) - 1) << USB_PROG_FR_LIST_FLAG_POS)) -#define USB_ASYN_SCH_PARK_CAP USB_ASYN_SCH_PARK_CAP -#define USB_ASYN_SCH_PARK_CAP_POS (2U) -#define USB_ASYN_SCH_PARK_CAP_LEN (1U) -#define USB_ASYN_SCH_PARK_CAP_MSK (((1U << USB_ASYN_SCH_PARK_CAP_LEN) - 1) << USB_ASYN_SCH_PARK_CAP_POS) -#define USB_ASYN_SCH_PARK_CAP_UMSK (~(((1U << USB_ASYN_SCH_PARK_CAP_LEN) - 1) << USB_ASYN_SCH_PARK_CAP_POS)) - -/* 0x010 : USBCMD */ -#define USBCMD_OFFSET (0x010) -#define USB_RS USB_RS -#define USB_RS_POS (0U) -#define USB_RS_LEN (1U) -#define USB_RS_MSK (((1U << USB_RS_LEN) - 1) << USB_RS_POS) -#define USB_RS_UMSK (~(((1U << USB_RS_LEN) - 1) << USB_RS_POS)) -#define USB_HC_RESET USB_HC_RESET -#define USB_HC_RESET_POS (1U) -#define USB_HC_RESET_LEN (1U) -#define USB_HC_RESET_MSK (((1U << USB_HC_RESET_LEN) - 1) << USB_HC_RESET_POS) -#define USB_HC_RESET_UMSK (~(((1U << USB_HC_RESET_LEN) - 1) << USB_HC_RESET_POS)) -#define USB_FRL_SIZE USB_FRL_SIZE -#define USB_FRL_SIZE_POS (2U) -#define USB_FRL_SIZE_LEN (2U) -#define USB_FRL_SIZE_MSK (((1U << USB_FRL_SIZE_LEN) - 1) << USB_FRL_SIZE_POS) -#define USB_FRL_SIZE_UMSK (~(((1U << USB_FRL_SIZE_LEN) - 1) << USB_FRL_SIZE_POS)) -#define USB_PSCH_EN USB_PSCH_EN -#define USB_PSCH_EN_POS (4U) -#define USB_PSCH_EN_LEN (1U) -#define USB_PSCH_EN_MSK (((1U << USB_PSCH_EN_LEN) - 1) << USB_PSCH_EN_POS) -#define USB_PSCH_EN_UMSK (~(((1U << USB_PSCH_EN_LEN) - 1) << USB_PSCH_EN_POS)) -#define USB_ASCH_EN USB_ASCH_EN -#define USB_ASCH_EN_POS (5U) -#define USB_ASCH_EN_LEN (1U) -#define USB_ASCH_EN_MSK (((1U << USB_ASCH_EN_LEN) - 1) << USB_ASCH_EN_POS) -#define USB_ASCH_EN_UMSK (~(((1U << USB_ASCH_EN_LEN) - 1) << USB_ASCH_EN_POS)) -#define USB_INT_OAAD USB_INT_OAAD -#define USB_INT_OAAD_POS (6U) -#define USB_INT_OAAD_LEN (1U) -#define USB_INT_OAAD_MSK (((1U << USB_INT_OAAD_LEN) - 1) << USB_INT_OAAD_POS) -#define USB_INT_OAAD_UMSK (~(((1U << USB_INT_OAAD_LEN) - 1) << USB_INT_OAAD_POS)) -#define USB_ASYN_PK_CNT USB_ASYN_PK_CNT -#define USB_ASYN_PK_CNT_POS (8U) -#define USB_ASYN_PK_CNT_LEN (2U) -#define USB_ASYN_PK_CNT_MSK (((1U << USB_ASYN_PK_CNT_LEN) - 1) << USB_ASYN_PK_CNT_POS) -#define USB_ASYN_PK_CNT_UMSK (~(((1U << USB_ASYN_PK_CNT_LEN) - 1) << USB_ASYN_PK_CNT_POS)) -#define USB_ASYN_PK_EN USB_ASYN_PK_EN -#define USB_ASYN_PK_EN_POS (11U) -#define USB_ASYN_PK_EN_LEN (1U) -#define USB_ASYN_PK_EN_MSK (((1U << USB_ASYN_PK_EN_LEN) - 1) << USB_ASYN_PK_EN_POS) -#define USB_ASYN_PK_EN_UMSK (~(((1U << USB_ASYN_PK_EN_LEN) - 1) << USB_ASYN_PK_EN_POS)) -#define USB_INT_THRC USB_INT_THRC -#define USB_INT_THRC_POS (16U) -#define USB_INT_THRC_LEN (8U) -#define USB_INT_THRC_MSK (((1U << USB_INT_THRC_LEN) - 1) << USB_INT_THRC_POS) -#define USB_INT_THRC_UMSK (~(((1U << USB_INT_THRC_LEN) - 1) << USB_INT_THRC_POS)) - -/* 0x014 : USBSTS */ -#define USBSTS_OFFSET (0x014) -#define USB_INT USB_INT -#define USB_INT_POS (0U) -#define USB_INT_LEN (1U) -#define USB_INT_MSK (((1U << USB_INT_LEN) - 1) << USB_INT_POS) -#define USB_INT_UMSK (~(((1U << USB_INT_LEN) - 1) << USB_INT_POS)) -#define USBERR_INT USBERR_INT -#define USBERR_INT_POS (1U) -#define USBERR_INT_LEN (1U) -#define USBERR_INT_MSK (((1U << USBERR_INT_LEN) - 1) << USBERR_INT_POS) -#define USBERR_INT_UMSK (~(((1U << USBERR_INT_LEN) - 1) << USBERR_INT_POS)) -#define USB_PO_CHG_DET USB_PO_CHG_DET -#define USB_PO_CHG_DET_POS (2U) -#define USB_PO_CHG_DET_LEN (1U) -#define USB_PO_CHG_DET_MSK (((1U << USB_PO_CHG_DET_LEN) - 1) << USB_PO_CHG_DET_POS) -#define USB_PO_CHG_DET_UMSK (~(((1U << USB_PO_CHG_DET_LEN) - 1) << USB_PO_CHG_DET_POS)) -#define USB_FRL_ROL USB_FRL_ROL -#define USB_FRL_ROL_POS (3U) -#define USB_FRL_ROL_LEN (1U) -#define USB_FRL_ROL_MSK (((1U << USB_FRL_ROL_LEN) - 1) << USB_FRL_ROL_POS) -#define USB_FRL_ROL_UMSK (~(((1U << USB_FRL_ROL_LEN) - 1) << USB_FRL_ROL_POS)) -#define USB_H_SYSERR USB_H_SYSERR -#define USB_H_SYSERR_POS (4U) -#define USB_H_SYSERR_LEN (1U) -#define USB_H_SYSERR_MSK (((1U << USB_H_SYSERR_LEN) - 1) << USB_H_SYSERR_POS) -#define USB_H_SYSERR_UMSK (~(((1U << USB_H_SYSERR_LEN) - 1) << USB_H_SYSERR_POS)) -#define USB_INT_OAA USB_INT_OAA -#define USB_INT_OAA_POS (5U) -#define USB_INT_OAA_LEN (1U) -#define USB_INT_OAA_MSK (((1U << USB_INT_OAA_LEN) - 1) << USB_INT_OAA_POS) -#define USB_INT_OAA_UMSK (~(((1U << USB_INT_OAA_LEN) - 1) << USB_INT_OAA_POS)) -#define USB_HCHALTED USB_HCHALTED -#define USB_HCHALTED_POS (12U) -#define USB_HCHALTED_LEN (1U) -#define USB_HCHALTED_MSK (((1U << USB_HCHALTED_LEN) - 1) << USB_HCHALTED_POS) -#define USB_HCHALTED_UMSK (~(((1U << USB_HCHALTED_LEN) - 1) << USB_HCHALTED_POS)) -#define USB_RECLAMATION USB_RECLAMATION -#define USB_RECLAMATION_POS (13U) -#define USB_RECLAMATION_LEN (1U) -#define USB_RECLAMATION_MSK (((1U << USB_RECLAMATION_LEN) - 1) << USB_RECLAMATION_POS) -#define USB_RECLAMATION_UMSK (~(((1U << USB_RECLAMATION_LEN) - 1) << USB_RECLAMATION_POS)) -#define USB_PSCH_STS USB_PSCH_STS -#define USB_PSCH_STS_POS (14U) -#define USB_PSCH_STS_LEN (1U) -#define USB_PSCH_STS_MSK (((1U << USB_PSCH_STS_LEN) - 1) << USB_PSCH_STS_POS) -#define USB_PSCH_STS_UMSK (~(((1U << USB_PSCH_STS_LEN) - 1) << USB_PSCH_STS_POS)) -#define USB_ASCH_STS USB_ASCH_STS -#define USB_ASCH_STS_POS (15U) -#define USB_ASCH_STS_LEN (1U) -#define USB_ASCH_STS_MSK (((1U << USB_ASCH_STS_LEN) - 1) << USB_ASCH_STS_POS) -#define USB_ASCH_STS_UMSK (~(((1U << USB_ASCH_STS_LEN) - 1) << USB_ASCH_STS_POS)) - -/* 0x018 : USBINTR */ -#define USBINTR_OFFSET (0x018) -#define USB_INT_EN USB_INT_EN -#define USB_INT_EN_POS (0U) -#define USB_INT_EN_LEN (1U) -#define USB_INT_EN_MSK (((1U << USB_INT_EN_LEN) - 1) << USB_INT_EN_POS) -#define USB_INT_EN_UMSK (~(((1U << USB_INT_EN_LEN) - 1) << USB_INT_EN_POS)) -#define USBERR_INT_EN USBERR_INT_EN -#define USBERR_INT_EN_POS (1U) -#define USBERR_INT_EN_LEN (1U) -#define USBERR_INT_EN_MSK (((1U << USBERR_INT_EN_LEN) - 1) << USBERR_INT_EN_POS) -#define USBERR_INT_EN_UMSK (~(((1U << USBERR_INT_EN_LEN) - 1) << USBERR_INT_EN_POS)) -#define USB_PO_CHG_INT_EN USB_PO_CHG_INT_EN -#define USB_PO_CHG_INT_EN_POS (2U) -#define USB_PO_CHG_INT_EN_LEN (1U) -#define USB_PO_CHG_INT_EN_MSK (((1U << USB_PO_CHG_INT_EN_LEN) - 1) << USB_PO_CHG_INT_EN_POS) -#define USB_PO_CHG_INT_EN_UMSK (~(((1U << USB_PO_CHG_INT_EN_LEN) - 1) << USB_PO_CHG_INT_EN_POS)) -#define USB_FRL_ROL_EN USB_FRL_ROL_EN -#define USB_FRL_ROL_EN_POS (3U) -#define USB_FRL_ROL_EN_LEN (1U) -#define USB_FRL_ROL_EN_MSK (((1U << USB_FRL_ROL_EN_LEN) - 1) << USB_FRL_ROL_EN_POS) -#define USB_FRL_ROL_EN_UMSK (~(((1U << USB_FRL_ROL_EN_LEN) - 1) << USB_FRL_ROL_EN_POS)) -#define USB_H_SYSERR_EN USB_H_SYSERR_EN -#define USB_H_SYSERR_EN_POS (4U) -#define USB_H_SYSERR_EN_LEN (1U) -#define USB_H_SYSERR_EN_MSK (((1U << USB_H_SYSERR_EN_LEN) - 1) << USB_H_SYSERR_EN_POS) -#define USB_H_SYSERR_EN_UMSK (~(((1U << USB_H_SYSERR_EN_LEN) - 1) << USB_H_SYSERR_EN_POS)) -#define USB_INT_OAA_EN USB_INT_OAA_EN -#define USB_INT_OAA_EN_POS (5U) -#define USB_INT_OAA_EN_LEN (1U) -#define USB_INT_OAA_EN_MSK (((1U << USB_INT_OAA_EN_LEN) - 1) << USB_INT_OAA_EN_POS) -#define USB_INT_OAA_EN_UMSK (~(((1U << USB_INT_OAA_EN_LEN) - 1) << USB_INT_OAA_EN_POS)) - -/* 0x01C : FRINDEX */ -#define USB_FRINDEX_OFFSET (0x01C) -#define USB_FRINDEX USB_FRINDEX -#define USB_FRINDEX_POS (0U) -#define USB_FRINDEX_LEN (14U) -#define USB_FRINDEX_MSK (((1U << USB_FRINDEX_LEN) - 1) << USB_FRINDEX_POS) -#define USB_FRINDEX_UMSK (~(((1U << USB_FRINDEX_LEN) - 1) << USB_FRINDEX_POS)) - -/* 0x024 : PERIODICLISTBASE */ -#define USB_PERIODICLISTBASE_OFFSET (0x024) -#define USB_PERI_BASADR USB_PERI_BASADR -#define USB_PERI_BASADR_POS (12U) -#define USB_PERI_BASADR_LEN (20U) -#define USB_PERI_BASADR_MSK (((1U << USB_PERI_BASADR_LEN) - 1) << USB_PERI_BASADR_POS) -#define USB_PERI_BASADR_UMSK (~(((1U << USB_PERI_BASADR_LEN) - 1) << USB_PERI_BASADR_POS)) - -/* 0x028 : ASYNCLISTADDR */ -#define USB_ASYNCLISTADDR_OFFSET (0x028) -#define USB_ASYNC_LADR USB_ASYNC_LADR -#define USB_ASYNC_LADR_POS (5U) -#define USB_ASYNC_LADR_LEN (27U) -#define USB_ASYNC_LADR_MSK (((1U << USB_ASYNC_LADR_LEN) - 1) << USB_ASYNC_LADR_POS) -#define USB_ASYNC_LADR_UMSK (~(((1U << USB_ASYNC_LADR_LEN) - 1) << USB_ASYNC_LADR_POS)) - -/* 0x030 : PORTSC */ -#define USB_PORTSC_OFFSET (0x030) -#define USB_CONN_STS USB_CONN_STS -#define USB_CONN_STS_POS (0U) -#define USB_CONN_STS_LEN (1U) -#define USB_CONN_STS_MSK (((1U << USB_CONN_STS_LEN) - 1) << USB_CONN_STS_POS) -#define USB_CONN_STS_UMSK (~(((1U << USB_CONN_STS_LEN) - 1) << USB_CONN_STS_POS)) -#define USB_CONN_CHG USB_CONN_CHG -#define USB_CONN_CHG_POS (1U) -#define USB_CONN_CHG_LEN (1U) -#define USB_CONN_CHG_MSK (((1U << USB_CONN_CHG_LEN) - 1) << USB_CONN_CHG_POS) -#define USB_CONN_CHG_UMSK (~(((1U << USB_CONN_CHG_LEN) - 1) << USB_CONN_CHG_POS)) -#define USB_PO_EN USB_PO_EN -#define USB_PO_EN_POS (2U) -#define USB_PO_EN_LEN (1U) -#define USB_PO_EN_MSK (((1U << USB_PO_EN_LEN) - 1) << USB_PO_EN_POS) -#define USB_PO_EN_UMSK (~(((1U << USB_PO_EN_LEN) - 1) << USB_PO_EN_POS)) -#define USB_PO_EN_CHG USB_PO_EN_CHG -#define USB_PO_EN_CHG_POS (3U) -#define USB_PO_EN_CHG_LEN (1U) -#define USB_PO_EN_CHG_MSK (((1U << USB_PO_EN_CHG_LEN) - 1) << USB_PO_EN_CHG_POS) -#define USB_PO_EN_CHG_UMSK (~(((1U << USB_PO_EN_CHG_LEN) - 1) << USB_PO_EN_CHG_POS)) -#define USB_F_PO_RESM USB_F_PO_RESM -#define USB_F_PO_RESM_POS (6U) -#define USB_F_PO_RESM_LEN (1U) -#define USB_F_PO_RESM_MSK (((1U << USB_F_PO_RESM_LEN) - 1) << USB_F_PO_RESM_POS) -#define USB_F_PO_RESM_UMSK (~(((1U << USB_F_PO_RESM_LEN) - 1) << USB_F_PO_RESM_POS)) -#define USB_PO_SUSP USB_PO_SUSP -#define USB_PO_SUSP_POS (7U) -#define USB_PO_SUSP_LEN (1U) -#define USB_PO_SUSP_MSK (((1U << USB_PO_SUSP_LEN) - 1) << USB_PO_SUSP_POS) -#define USB_PO_SUSP_UMSK (~(((1U << USB_PO_SUSP_LEN) - 1) << USB_PO_SUSP_POS)) -#define USB_PO_RESET USB_PO_RESET -#define USB_PO_RESET_POS (8U) -#define USB_PO_RESET_LEN (1U) -#define USB_PO_RESET_MSK (((1U << USB_PO_RESET_LEN) - 1) << USB_PO_RESET_POS) -#define USB_PO_RESET_UMSK (~(((1U << USB_PO_RESET_LEN) - 1) << USB_PO_RESET_POS)) -#define USB_LINE_STS USB_LINE_STS -#define USB_LINE_STS_POS (10U) -#define USB_LINE_STS_LEN (2U) -#define USB_LINE_STS_MSK (((1U << USB_LINE_STS_LEN) - 1) << USB_LINE_STS_POS) -#define USB_LINE_STS_UMSK (~(((1U << USB_LINE_STS_LEN) - 1) << USB_LINE_STS_POS)) -#define USB_PORT_TEST USB_PORT_TEST -#define USB_PORT_TEST_POS (16U) -#define USB_PORT_TEST_LEN (4U) -#define USB_PORT_TEST_MSK (((1U << USB_PORT_TEST_LEN) - 1) << USB_PORT_TEST_POS) -#define USB_PORT_TEST_UMSK (~(((1U << USB_PORT_TEST_LEN) - 1) << USB_PORT_TEST_POS)) -#define USB_HC_TST_PKDONE USB_HC_TST_PKDONE -#define USB_HC_TST_PKDONE_POS (20U) -#define USB_HC_TST_PKDONE_LEN (1U) -#define USB_HC_TST_PKDONE_MSK (((1U << USB_HC_TST_PKDONE_LEN) - 1) << USB_HC_TST_PKDONE_POS) -#define USB_HC_TST_PKDONE_UMSK (~(((1U << USB_HC_TST_PKDONE_LEN) - 1) << USB_HC_TST_PKDONE_POS)) - -/* 0x040 : HCMISC */ -#define USB_HCMISC_OFFSET (0x040) -#define USB_ASYN_SCH_SLPT USB_ASYN_SCH_SLPT -#define USB_ASYN_SCH_SLPT_POS (0U) -#define USB_ASYN_SCH_SLPT_LEN (2U) -#define USB_ASYN_SCH_SLPT_MSK (((1U << USB_ASYN_SCH_SLPT_LEN) - 1) << USB_ASYN_SCH_SLPT_POS) -#define USB_ASYN_SCH_SLPT_UMSK (~(((1U << USB_ASYN_SCH_SLPT_LEN) - 1) << USB_ASYN_SCH_SLPT_POS)) -#define USB_EOF1_TIME USB_EOF1_TIME -#define USB_EOF1_TIME_POS (2U) -#define USB_EOF1_TIME_LEN (2U) -#define USB_EOF1_TIME_MSK (((1U << USB_EOF1_TIME_LEN) - 1) << USB_EOF1_TIME_POS) -#define USB_EOF1_TIME_UMSK (~(((1U << USB_EOF1_TIME_LEN) - 1) << USB_EOF1_TIME_POS)) -#define USB_EOF2_TIME USB_EOF2_TIME -#define USB_EOF2_TIME_POS (4U) -#define USB_EOF2_TIME_LEN (2U) -#define USB_EOF2_TIME_MSK (((1U << USB_EOF2_TIME_LEN) - 1) << USB_EOF2_TIME_POS) -#define USB_EOF2_TIME_UMSK (~(((1U << USB_EOF2_TIME_LEN) - 1) << USB_EOF2_TIME_POS)) -#define USB_HOSTPHY_SUSPEND USB_HOSTPHY_SUSPEND -#define USB_HOSTPHY_SUSPEND_POS (6U) -#define USB_HOSTPHY_SUSPEND_LEN (1U) -#define USB_HOSTPHY_SUSPEND_MSK (((1U << USB_HOSTPHY_SUSPEND_LEN) - 1) << USB_HOSTPHY_SUSPEND_POS) -#define USB_HOSTPHY_SUSPEND_UMSK (~(((1U << USB_HOSTPHY_SUSPEND_LEN) - 1) << USB_HOSTPHY_SUSPEND_POS)) -#define USB_HC_WKP_DET_EN USB_HC_WKP_DET_EN -#define USB_HC_WKP_DET_EN_POS (8U) -#define USB_HC_WKP_DET_EN_LEN (1U) -#define USB_HC_WKP_DET_EN_MSK (((1U << USB_HC_WKP_DET_EN_LEN) - 1) << USB_HC_WKP_DET_EN_POS) -#define USB_HC_WKP_DET_EN_UMSK (~(((1U << USB_HC_WKP_DET_EN_LEN) - 1) << USB_HC_WKP_DET_EN_POS)) -#define USB_HC_CONN_DET_EN USB_HC_CONN_DET_EN -#define USB_HC_CONN_DET_EN_POS (9U) -#define USB_HC_CONN_DET_EN_LEN (1U) -#define USB_HC_CONN_DET_EN_MSK (((1U << USB_HC_CONN_DET_EN_LEN) - 1) << USB_HC_CONN_DET_EN_POS) -#define USB_HC_CONN_DET_EN_UMSK (~(((1U << USB_HC_CONN_DET_EN_LEN) - 1) << USB_HC_CONN_DET_EN_POS)) - -/* 0x044 : FS_EOF */ -#define USB_FS_EOF_OFFSET (0x044) -#define USB_FS_EOF1_TIME USB_FS_EOF1_TIME -#define USB_FS_EOF1_TIME_POS (0U) -#define USB_FS_EOF1_TIME_LEN (12U) -#define USB_FS_EOF1_TIME_MSK (((1U << USB_FS_EOF1_TIME_LEN) - 1) << USB_FS_EOF1_TIME_POS) -#define USB_FS_EOF1_TIME_UMSK (~(((1U << USB_FS_EOF1_TIME_LEN) - 1) << USB_FS_EOF1_TIME_POS)) -#define USB_FS_EOF1_TIME_125US USB_FS_EOF1_TIME_125US -#define USB_FS_EOF1_TIME_125US_POS (12U) -#define USB_FS_EOF1_TIME_125US_LEN (3U) -#define USB_FS_EOF1_TIME_125US_MSK (((1U << USB_FS_EOF1_TIME_125US_LEN) - 1) << USB_FS_EOF1_TIME_125US_POS) -#define USB_FS_EOF1_TIME_125US_UMSK (~(((1U << USB_FS_EOF1_TIME_125US_LEN) - 1) << USB_FS_EOF1_TIME_125US_POS)) -#define USB_ITDDMASM USB_ITDDMASM -#define USB_ITDDMASM_POS (16U) -#define USB_ITDDMASM_LEN (4U) -#define USB_ITDDMASM_MSK (((1U << USB_ITDDMASM_LEN) - 1) << USB_ITDDMASM_POS) -#define USB_ITDDMASM_UMSK (~(((1U << USB_ITDDMASM_LEN) - 1) << USB_ITDDMASM_POS)) -#define USB_ITDTRAVSM USB_ITDTRAVSM -#define USB_ITDTRAVSM_POS (20U) -#define USB_ITDTRAVSM_LEN (2U) -#define USB_ITDTRAVSM_MSK (((1U << USB_ITDTRAVSM_LEN) - 1) << USB_ITDTRAVSM_POS) -#define USB_ITDTRAVSM_UMSK (~(((1U << USB_ITDTRAVSM_LEN) - 1) << USB_ITDTRAVSM_POS)) -#define USB_DMADMSM USB_DMADMSM -#define USB_DMADMSM_POS (22U) -#define USB_DMADMSM_LEN (4U) -#define USB_DMADMSM_MSK (((1U << USB_DMADMSM_LEN) - 1) << USB_DMADMSM_POS) -#define USB_DMADMSM_UMSK (~(((1U << USB_DMADMSM_LEN) - 1) << USB_DMADMSM_POS)) -#define USB_QHTTRSM USB_QHTTRSM -#define USB_QHTTRSM_POS (26U) -#define USB_QHTTRSM_LEN (3U) -#define USB_QHTTRSM_MSK (((1U << USB_QHTTRSM_LEN) - 1) << USB_QHTTRSM_POS) -#define USB_QHTTRSM_UMSK (~(((1U << USB_QHTTRSM_LEN) - 1) << USB_QHTTRSM_POS)) -#define USB_QHTRAVSM USB_QHTRAVSM -#define USB_QHTRAVSM_POS (29U) -#define USB_QHTRAVSM_LEN (3U) -#define USB_QHTRAVSM_MSK (((1U << USB_QHTRAVSM_LEN) - 1) << USB_QHTRAVSM_POS) -#define USB_QHTRAVSM_UMSK (~(((1U << USB_QHTRAVSM_LEN) - 1) << USB_QHTRAVSM_POS)) - -/* 0x048 : HS_EOF */ -#define USB_HS_EOF_OFFSET (0x048) -#define USB_HS_EOF1_TIME USB_HS_EOF1_TIME -#define USB_HS_EOF1_TIME_POS (0U) -#define USB_HS_EOF1_TIME_LEN (12U) -#define USB_HS_EOF1_TIME_MSK (((1U << USB_HS_EOF1_TIME_LEN) - 1) << USB_HS_EOF1_TIME_POS) -#define USB_HS_EOF1_TIME_UMSK (~(((1U << USB_HS_EOF1_TIME_LEN) - 1) << USB_HS_EOF1_TIME_POS)) -#define USB_SITDDMASM USB_SITDDMASM -#define USB_SITDDMASM_POS (16U) -#define USB_SITDDMASM_LEN (4U) -#define USB_SITDDMASM_MSK (((1U << USB_SITDDMASM_LEN) - 1) << USB_SITDDMASM_POS) -#define USB_SITDDMASM_UMSK (~(((1U << USB_SITDDMASM_LEN) - 1) << USB_SITDDMASM_POS)) -#define USB_SITDTRAVSM USB_SITDTRAVSM -#define USB_SITDTRAVSM_POS (20U) -#define USB_SITDTRAVSM_LEN (2U) -#define USB_SITDTRAVSM_MSK (((1U << USB_SITDTRAVSM_LEN) - 1) << USB_SITDTRAVSM_POS) -#define USB_SITDTRAVSM_UMSK (~(((1U << USB_SITDTRAVSM_LEN) - 1) << USB_SITDTRAVSM_POS)) - -/* 0x080 : OTG_CSR */ -#define USB_OTG_CSR_OFFSET (0x080) -#define USB_B_BUS_REQ USB_B_BUS_REQ -#define USB_B_BUS_REQ_POS (0U) -#define USB_B_BUS_REQ_LEN (1U) -#define USB_B_BUS_REQ_MSK (((1U << USB_B_BUS_REQ_LEN) - 1) << USB_B_BUS_REQ_POS) -#define USB_B_BUS_REQ_UMSK (~(((1U << USB_B_BUS_REQ_LEN) - 1) << USB_B_BUS_REQ_POS)) -#define USB_B_HNP_EN USB_B_HNP_EN -#define USB_B_HNP_EN_POS (1U) -#define USB_B_HNP_EN_LEN (1U) -#define USB_B_HNP_EN_MSK (((1U << USB_B_HNP_EN_LEN) - 1) << USB_B_HNP_EN_POS) -#define USB_B_HNP_EN_UMSK (~(((1U << USB_B_HNP_EN_LEN) - 1) << USB_B_HNP_EN_POS)) -#define USB_B_DSCHRG_VBUS USB_B_DSCHRG_VBUS -#define USB_B_DSCHRG_VBUS_POS (2U) -#define USB_B_DSCHRG_VBUS_LEN (1U) -#define USB_B_DSCHRG_VBUS_MSK (((1U << USB_B_DSCHRG_VBUS_LEN) - 1) << USB_B_DSCHRG_VBUS_POS) -#define USB_B_DSCHRG_VBUS_UMSK (~(((1U << USB_B_DSCHRG_VBUS_LEN) - 1) << USB_B_DSCHRG_VBUS_POS)) -#define USB_A_BUS_REQ_HOV USB_A_BUS_REQ_HOV -#define USB_A_BUS_REQ_HOV_POS (4U) -#define USB_A_BUS_REQ_HOV_LEN (1U) -#define USB_A_BUS_REQ_HOV_MSK (((1U << USB_A_BUS_REQ_HOV_LEN) - 1) << USB_A_BUS_REQ_HOV_POS) -#define USB_A_BUS_REQ_HOV_UMSK (~(((1U << USB_A_BUS_REQ_HOV_LEN) - 1) << USB_A_BUS_REQ_HOV_POS)) -#define USB_A_BUS_DROP_HOV USB_A_BUS_DROP_HOV -#define USB_A_BUS_DROP_HOV_POS (5U) -#define USB_A_BUS_DROP_HOV_LEN (1U) -#define USB_A_BUS_DROP_HOV_MSK (((1U << USB_A_BUS_DROP_HOV_LEN) - 1) << USB_A_BUS_DROP_HOV_POS) -#define USB_A_BUS_DROP_HOV_UMSK (~(((1U << USB_A_BUS_DROP_HOV_LEN) - 1) << USB_A_BUS_DROP_HOV_POS)) -#define USB_A_SET_B_HNP_EN USB_A_SET_B_HNP_EN -#define USB_A_SET_B_HNP_EN_POS (6U) -#define USB_A_SET_B_HNP_EN_LEN (1U) -#define USB_A_SET_B_HNP_EN_MSK (((1U << USB_A_SET_B_HNP_EN_LEN) - 1) << USB_A_SET_B_HNP_EN_POS) -#define USB_A_SET_B_HNP_EN_UMSK (~(((1U << USB_A_SET_B_HNP_EN_LEN) - 1) << USB_A_SET_B_HNP_EN_POS)) -#define USB_A_SRP_DET_EN USB_A_SRP_DET_EN -#define USB_A_SRP_DET_EN_POS (7U) -#define USB_A_SRP_DET_EN_LEN (1U) -#define USB_A_SRP_DET_EN_MSK (((1U << USB_A_SRP_DET_EN_LEN) - 1) << USB_A_SRP_DET_EN_POS) -#define USB_A_SRP_DET_EN_UMSK (~(((1U << USB_A_SRP_DET_EN_LEN) - 1) << USB_A_SRP_DET_EN_POS)) -#define USB_A_SRP_RESP_TYP USB_A_SRP_RESP_TYP -#define USB_A_SRP_RESP_TYP_POS (8U) -#define USB_A_SRP_RESP_TYP_LEN (1U) -#define USB_A_SRP_RESP_TYP_MSK (((1U << USB_A_SRP_RESP_TYP_LEN) - 1) << USB_A_SRP_RESP_TYP_POS) -#define USB_A_SRP_RESP_TYP_UMSK (~(((1U << USB_A_SRP_RESP_TYP_LEN) - 1) << USB_A_SRP_RESP_TYP_POS)) -#define USB_ID_FLT_SEL USB_ID_FLT_SEL -#define USB_ID_FLT_SEL_POS (9U) -#define USB_ID_FLT_SEL_LEN (1U) -#define USB_ID_FLT_SEL_MSK (((1U << USB_ID_FLT_SEL_LEN) - 1) << USB_ID_FLT_SEL_POS) -#define USB_ID_FLT_SEL_UMSK (~(((1U << USB_ID_FLT_SEL_LEN) - 1) << USB_ID_FLT_SEL_POS)) -#define USB_VBUS_FLT_SEL_HOV_POV USB_VBUS_FLT_SEL_HOV_POV -#define USB_VBUS_FLT_SEL_HOV_POV_POS (10U) -#define USB_VBUS_FLT_SEL_HOV_POV_LEN (1U) -#define USB_VBUS_FLT_SEL_HOV_POV_MSK (((1U << USB_VBUS_FLT_SEL_HOV_POV_LEN) - 1) << USB_VBUS_FLT_SEL_HOV_POV_POS) -#define USB_VBUS_FLT_SEL_HOV_POV_UMSK (~(((1U << USB_VBUS_FLT_SEL_HOV_POV_LEN) - 1) << USB_VBUS_FLT_SEL_HOV_POV_POS)) -#define USB_HDISCON_FLT_SEL_HOV USB_HDISCON_FLT_SEL_HOV -#define USB_HDISCON_FLT_SEL_HOV_POS (11U) -#define USB_HDISCON_FLT_SEL_HOV_LEN (1U) -#define USB_HDISCON_FLT_SEL_HOV_MSK (((1U << USB_HDISCON_FLT_SEL_HOV_LEN) - 1) << USB_HDISCON_FLT_SEL_HOV_POS) -#define USB_HDISCON_FLT_SEL_HOV_UMSK (~(((1U << USB_HDISCON_FLT_SEL_HOV_LEN) - 1) << USB_HDISCON_FLT_SEL_HOV_POS)) -#define USB_IDPULUP_HOV_POV USB_IDPULUP_HOV_POV -#define USB_IDPULUP_HOV_POV_POS (13U) -#define USB_IDPULUP_HOV_POV_LEN (1U) -#define USB_IDPULUP_HOV_POV_MSK (((1U << USB_IDPULUP_HOV_POV_LEN) - 1) << USB_IDPULUP_HOV_POV_POS) -#define USB_IDPULUP_HOV_POV_UMSK (~(((1U << USB_IDPULUP_HOV_POV_LEN) - 1) << USB_IDPULUP_HOV_POV_POS)) -#define USB_B_SESS_END_POV USB_B_SESS_END_POV -#define USB_B_SESS_END_POV_POS (16U) -#define USB_B_SESS_END_POV_LEN (1U) -#define USB_B_SESS_END_POV_MSK (((1U << USB_B_SESS_END_POV_LEN) - 1) << USB_B_SESS_END_POV_POS) -#define USB_B_SESS_END_POV_UMSK (~(((1U << USB_B_SESS_END_POV_LEN) - 1) << USB_B_SESS_END_POV_POS)) -#define USB_B_SESS_VLD_POV USB_B_SESS_VLD_POV -#define USB_B_SESS_VLD_POV_POS (17U) -#define USB_B_SESS_VLD_POV_LEN (1U) -#define USB_B_SESS_VLD_POV_MSK (((1U << USB_B_SESS_VLD_POV_LEN) - 1) << USB_B_SESS_VLD_POV_POS) -#define USB_B_SESS_VLD_POV_UMSK (~(((1U << USB_B_SESS_VLD_POV_LEN) - 1) << USB_B_SESS_VLD_POV_POS)) -#define USB_A_SESS_VLD USB_A_SESS_VLD -#define USB_A_SESS_VLD_POS (18U) -#define USB_A_SESS_VLD_LEN (1U) -#define USB_A_SESS_VLD_MSK (((1U << USB_A_SESS_VLD_LEN) - 1) << USB_A_SESS_VLD_POS) -#define USB_A_SESS_VLD_UMSK (~(((1U << USB_A_SESS_VLD_LEN) - 1) << USB_A_SESS_VLD_POS)) -#define USB_VBUS_VLD_HOV USB_VBUS_VLD_HOV -#define USB_VBUS_VLD_HOV_POS (19U) -#define USB_VBUS_VLD_HOV_LEN (1U) -#define USB_VBUS_VLD_HOV_MSK (((1U << USB_VBUS_VLD_HOV_LEN) - 1) << USB_VBUS_VLD_HOV_POS) -#define USB_VBUS_VLD_HOV_UMSK (~(((1U << USB_VBUS_VLD_HOV_LEN) - 1) << USB_VBUS_VLD_HOV_POS)) -#define USB_CROLE_HOV_POV USB_CROLE_HOV_POV -#define USB_CROLE_HOV_POV_POS (20U) -#define USB_CROLE_HOV_POV_LEN (1U) -#define USB_CROLE_HOV_POV_MSK (((1U << USB_CROLE_HOV_POV_LEN) - 1) << USB_CROLE_HOV_POV_POS) -#define USB_CROLE_HOV_POV_UMSK (~(((1U << USB_CROLE_HOV_POV_LEN) - 1) << USB_CROLE_HOV_POV_POS)) -#define USB_ID_HOV_POV USB_ID_HOV_POV -#define USB_ID_HOV_POV_POS (21U) -#define USB_ID_HOV_POV_LEN (1U) -#define USB_ID_HOV_POV_MSK (((1U << USB_ID_HOV_POV_LEN) - 1) << USB_ID_HOV_POV_POS) -#define USB_ID_HOV_POV_UMSK (~(((1U << USB_ID_HOV_POV_LEN) - 1) << USB_ID_HOV_POV_POS)) -#define USB_SPD_TYP_HOV_POV USB_SPD_TYP_HOV_POV -#define USB_SPD_TYP_HOV_POV_POS (22U) -#define USB_SPD_TYP_HOV_POV_LEN (2U) -#define USB_SPD_TYP_HOV_POV_MSK (((1U << USB_SPD_TYP_HOV_POV_LEN) - 1) << USB_SPD_TYP_HOV_POV_POS) -#define USB_SPD_TYP_HOV_POV_UMSK (~(((1U << USB_SPD_TYP_HOV_POV_LEN) - 1) << USB_SPD_TYP_HOV_POV_POS)) - -/* 0x084 : OTG_ISR */ -#define USB_OTG_ISR_OFFSET (0x084) -#define USB_B_SRP_DN USB_B_SRP_DN -#define USB_B_SRP_DN_POS (0U) -#define USB_B_SRP_DN_LEN (1U) -#define USB_B_SRP_DN_MSK (((1U << USB_B_SRP_DN_LEN) - 1) << USB_B_SRP_DN_POS) -#define USB_B_SRP_DN_UMSK (~(((1U << USB_B_SRP_DN_LEN) - 1) << USB_B_SRP_DN_POS)) -#define USB_A_SRP_DET USB_A_SRP_DET -#define USB_A_SRP_DET_POS (4U) -#define USB_A_SRP_DET_LEN (1U) -#define USB_A_SRP_DET_MSK (((1U << USB_A_SRP_DET_LEN) - 1) << USB_A_SRP_DET_POS) -#define USB_A_SRP_DET_UMSK (~(((1U << USB_A_SRP_DET_LEN) - 1) << USB_A_SRP_DET_POS)) -#define USB_A_VBUS_ERR_HOV USB_A_VBUS_ERR_HOV -#define USB_A_VBUS_ERR_HOV_POS (5U) -#define USB_A_VBUS_ERR_HOV_LEN (1U) -#define USB_A_VBUS_ERR_HOV_MSK (((1U << USB_A_VBUS_ERR_HOV_LEN) - 1) << USB_A_VBUS_ERR_HOV_POS) -#define USB_A_VBUS_ERR_HOV_UMSK (~(((1U << USB_A_VBUS_ERR_HOV_LEN) - 1) << USB_A_VBUS_ERR_HOV_POS)) -#define USB_B_SESS_END_INT_POV USB_B_SESS_END_INT_POV -#define USB_B_SESS_END_INT_POV_POS (6U) -#define USB_B_SESS_END_INT_POV_LEN (1U) -#define USB_B_SESS_END_INT_POV_MSK (((1U << USB_B_SESS_END_INT_POV_LEN) - 1) << USB_B_SESS_END_INT_POV_POS) -#define USB_B_SESS_END_INT_POV_UMSK (~(((1U << USB_B_SESS_END_INT_POV_LEN) - 1) << USB_B_SESS_END_INT_POV_POS)) -#define USB_RLCHG USB_RLCHG -#define USB_RLCHG_POS (8U) -#define USB_RLCHG_LEN (1U) -#define USB_RLCHG_MSK (((1U << USB_RLCHG_LEN) - 1) << USB_RLCHG_POS) -#define USB_RLCHG_UMSK (~(((1U << USB_RLCHG_LEN) - 1) << USB_RLCHG_POS)) -#define USB_IDCHG USB_IDCHG -#define USB_IDCHG_POS (9U) -#define USB_IDCHG_LEN (1U) -#define USB_IDCHG_MSK (((1U << USB_IDCHG_LEN) - 1) << USB_IDCHG_POS) -#define USB_IDCHG_UMSK (~(((1U << USB_IDCHG_LEN) - 1) << USB_IDCHG_POS)) -#define USB_OVC_HOV USB_OVC_HOV -#define USB_OVC_HOV_POS (10U) -#define USB_OVC_HOV_LEN (1U) -#define USB_OVC_HOV_MSK (((1U << USB_OVC_HOV_LEN) - 1) << USB_OVC_HOV_POS) -#define USB_OVC_HOV_UMSK (~(((1U << USB_OVC_HOV_LEN) - 1) << USB_OVC_HOV_POS)) -#define USB_A_WAIT_CON_HOV USB_A_WAIT_CON_HOV -#define USB_A_WAIT_CON_HOV_POS (11U) -#define USB_A_WAIT_CON_HOV_LEN (1U) -#define USB_A_WAIT_CON_HOV_MSK (((1U << USB_A_WAIT_CON_HOV_LEN) - 1) << USB_A_WAIT_CON_HOV_POS) -#define USB_A_WAIT_CON_HOV_UMSK (~(((1U << USB_A_WAIT_CON_HOV_LEN) - 1) << USB_A_WAIT_CON_HOV_POS)) -#define USB_APLGRMV USB_APLGRMV -#define USB_APLGRMV_POS (12U) -#define USB_APLGRMV_LEN (1U) -#define USB_APLGRMV_MSK (((1U << USB_APLGRMV_LEN) - 1) << USB_APLGRMV_POS) -#define USB_APLGRMV_UMSK (~(((1U << USB_APLGRMV_LEN) - 1) << USB_APLGRMV_POS)) - -/* 0x088 : OTG_IER */ -#define USB_OTG_IER_OFFSET (0x088) -#define USB_B_SRP_DN_EN USB_B_SRP_DN_EN -#define USB_B_SRP_DN_EN_POS (0U) -#define USB_B_SRP_DN_EN_LEN (1U) -#define USB_B_SRP_DN_EN_MSK (((1U << USB_B_SRP_DN_EN_LEN) - 1) << USB_B_SRP_DN_EN_POS) -#define USB_B_SRP_DN_EN_UMSK (~(((1U << USB_B_SRP_DN_EN_LEN) - 1) << USB_B_SRP_DN_EN_POS)) -#define USB_A_SRP_DET_INT_EN USB_A_SRP_DET_INT_EN -#define USB_A_SRP_DET_INT_EN_POS (4U) -#define USB_A_SRP_DET_INT_EN_LEN (1U) -#define USB_A_SRP_DET_INT_EN_MSK (((1U << USB_A_SRP_DET_INT_EN_LEN) - 1) << USB_A_SRP_DET_INT_EN_POS) -#define USB_A_SRP_DET_INT_EN_UMSK (~(((1U << USB_A_SRP_DET_INT_EN_LEN) - 1) << USB_A_SRP_DET_INT_EN_POS)) -#define USB_A_VBUS_ERR_EN_HOV USB_A_VBUS_ERR_EN_HOV -#define USB_A_VBUS_ERR_EN_HOV_POS (5U) -#define USB_A_VBUS_ERR_EN_HOV_LEN (1U) -#define USB_A_VBUS_ERR_EN_HOV_MSK (((1U << USB_A_VBUS_ERR_EN_HOV_LEN) - 1) << USB_A_VBUS_ERR_EN_HOV_POS) -#define USB_A_VBUS_ERR_EN_HOV_UMSK (~(((1U << USB_A_VBUS_ERR_EN_HOV_LEN) - 1) << USB_A_VBUS_ERR_EN_HOV_POS)) -#define USB_B_SESS_END_EN_POV USB_B_SESS_END_EN_POV -#define USB_B_SESS_END_EN_POV_POS (6U) -#define USB_B_SESS_END_EN_POV_LEN (1U) -#define USB_B_SESS_END_EN_POV_MSK (((1U << USB_B_SESS_END_EN_POV_LEN) - 1) << USB_B_SESS_END_EN_POV_POS) -#define USB_B_SESS_END_EN_POV_UMSK (~(((1U << USB_B_SESS_END_EN_POV_LEN) - 1) << USB_B_SESS_END_EN_POV_POS)) -#define USB_RLCHG_EN USB_RLCHG_EN -#define USB_RLCHG_EN_POS (8U) -#define USB_RLCHG_EN_LEN (1U) -#define USB_RLCHG_EN_MSK (((1U << USB_RLCHG_EN_LEN) - 1) << USB_RLCHG_EN_POS) -#define USB_RLCHG_EN_UMSK (~(((1U << USB_RLCHG_EN_LEN) - 1) << USB_RLCHG_EN_POS)) -#define USB_IDCHG_EN USB_IDCHG_EN -#define USB_IDCHG_EN_POS (9U) -#define USB_IDCHG_EN_LEN (1U) -#define USB_IDCHG_EN_MSK (((1U << USB_IDCHG_EN_LEN) - 1) << USB_IDCHG_EN_POS) -#define USB_IDCHG_EN_UMSK (~(((1U << USB_IDCHG_EN_LEN) - 1) << USB_IDCHG_EN_POS)) -#define USB_OVC_EN_HOV USB_OVC_EN_HOV -#define USB_OVC_EN_HOV_POS (10U) -#define USB_OVC_EN_HOV_LEN (1U) -#define USB_OVC_EN_HOV_MSK (((1U << USB_OVC_EN_HOV_LEN) - 1) << USB_OVC_EN_HOV_POS) -#define USB_OVC_EN_HOV_UMSK (~(((1U << USB_OVC_EN_HOV_LEN) - 1) << USB_OVC_EN_HOV_POS)) -#define USB_A_WAIT_CON_EN_HOV USB_A_WAIT_CON_EN_HOV -#define USB_A_WAIT_CON_EN_HOV_POS (11U) -#define USB_A_WAIT_CON_EN_HOV_LEN (1U) -#define USB_A_WAIT_CON_EN_HOV_MSK (((1U << USB_A_WAIT_CON_EN_HOV_LEN) - 1) << USB_A_WAIT_CON_EN_HOV_POS) -#define USB_A_WAIT_CON_EN_HOV_UMSK (~(((1U << USB_A_WAIT_CON_EN_HOV_LEN) - 1) << USB_A_WAIT_CON_EN_HOV_POS)) -#define USB_APLGRMV_EN USB_APLGRMV_EN -#define USB_APLGRMV_EN_POS (12U) -#define USB_APLGRMV_EN_LEN (1U) -#define USB_APLGRMV_EN_MSK (((1U << USB_APLGRMV_EN_LEN) - 1) << USB_APLGRMV_EN_POS) -#define USB_APLGRMV_EN_UMSK (~(((1U << USB_APLGRMV_EN_LEN) - 1) << USB_APLGRMV_EN_POS)) - -/* 0x0C0 : GLB_ISR */ -#define USB_GLB_ISR_OFFSET (0x0C0) -#define USB_DEV_INT USB_DEV_INT -#define USB_DEV_INT_POS (0U) -#define USB_DEV_INT_LEN (1U) -#define USB_DEV_INT_MSK (((1U << USB_DEV_INT_LEN) - 1) << USB_DEV_INT_POS) -#define USB_DEV_INT_UMSK (~(((1U << USB_DEV_INT_LEN) - 1) << USB_DEV_INT_POS)) -#define USB_OTG_INT USB_OTG_INT -#define USB_OTG_INT_POS (1U) -#define USB_OTG_INT_LEN (1U) -#define USB_OTG_INT_MSK (((1U << USB_OTG_INT_LEN) - 1) << USB_OTG_INT_POS) -#define USB_OTG_INT_UMSK (~(((1U << USB_OTG_INT_LEN) - 1) << USB_OTG_INT_POS)) -#define USB_HC_INT USB_HC_INT -#define USB_HC_INT_POS (2U) -#define USB_HC_INT_LEN (1U) -#define USB_HC_INT_MSK (((1U << USB_HC_INT_LEN) - 1) << USB_HC_INT_POS) -#define USB_HC_INT_UMSK (~(((1U << USB_HC_INT_LEN) - 1) << USB_HC_INT_POS)) - -/* 0x0C4 : GLB_INT */ -#define USB_GLB_INT_OFFSET (0x0C4) -#define USB_MDEV_INT USB_MDEV_INT -#define USB_MDEV_INT_POS (0U) -#define USB_MDEV_INT_LEN (1U) -#define USB_MDEV_INT_MSK (((1U << USB_MDEV_INT_LEN) - 1) << USB_MDEV_INT_POS) -#define USB_MDEV_INT_UMSK (~(((1U << USB_MDEV_INT_LEN) - 1) << USB_MDEV_INT_POS)) -#define USB_MOTG_INT USB_MOTG_INT -#define USB_MOTG_INT_POS (1U) -#define USB_MOTG_INT_LEN (1U) -#define USB_MOTG_INT_MSK (((1U << USB_MOTG_INT_LEN) - 1) << USB_MOTG_INT_POS) -#define USB_MOTG_INT_UMSK (~(((1U << USB_MOTG_INT_LEN) - 1) << USB_MOTG_INT_POS)) -#define USB_MHC_INT USB_MHC_INT -#define USB_MHC_INT_POS (2U) -#define USB_MHC_INT_LEN (1U) -#define USB_MHC_INT_MSK (((1U << USB_MHC_INT_LEN) - 1) << USB_MHC_INT_POS) -#define USB_MHC_INT_UMSK (~(((1U << USB_MHC_INT_LEN) - 1) << USB_MHC_INT_POS)) -#define USB_INT_POLARITY USB_INT_POLARITY -#define USB_INT_POLARITY_POS (3U) -#define USB_INT_POLARITY_LEN (1U) -#define USB_INT_POLARITY_MSK (((1U << USB_INT_POLARITY_LEN) - 1) << USB_INT_POLARITY_POS) -#define USB_INT_POLARITY_UMSK (~(((1U << USB_INT_POLARITY_LEN) - 1) << USB_INT_POLARITY_POS)) - -/* 0x0E0 : REVISION */ -#define USB_REVISION_OFFSET (0x0E0) -#define USB_REVISION USB_REVISION -#define USB_REVISION_POS (0U) -#define USB_REVISION_LEN (32U) -#define USB_REVISION_MSK (((1U << USB_REVISION_LEN) - 1) << USB_REVISION_POS) -#define USB_REVISION_UMSK (~(((1U << USB_REVISION_LEN) - 1) << USB_REVISION_POS)) - -/* 0x0E4 : FEATURE */ -#define USB_FEATURE_OFFSET (0x0E4) -#define USB_DMABUFSIZE USB_DMABUFSIZE -#define USB_DMABUFSIZE_POS (0U) -#define USB_DMABUFSIZE_LEN (5U) -#define USB_DMABUFSIZE_MSK (((1U << USB_DMABUFSIZE_LEN) - 1) << USB_DMABUFSIZE_POS) -#define USB_DMABUFSIZE_UMSK (~(((1U << USB_DMABUFSIZE_LEN) - 1) << USB_DMABUFSIZE_POS)) -#define USB_FIFO_NUM USB_FIFO_NUM -#define USB_FIFO_NUM_POS (5U) -#define USB_FIFO_NUM_LEN (5U) -#define USB_FIFO_NUM_MSK (((1U << USB_FIFO_NUM_LEN) - 1) << USB_FIFO_NUM_POS) -#define USB_FIFO_NUM_UMSK (~(((1U << USB_FIFO_NUM_LEN) - 1) << USB_FIFO_NUM_POS)) -#define USB_EP_NUM USB_EP_NUM -#define USB_EP_NUM_POS (10U) -#define USB_EP_NUM_LEN (5U) -#define USB_EP_NUM_MSK (((1U << USB_EP_NUM_LEN) - 1) << USB_EP_NUM_POS) -#define USB_EP_NUM_UMSK (~(((1U << USB_EP_NUM_LEN) - 1) << USB_EP_NUM_POS)) -#define USB_DEV_ONLY USB_DEV_ONLY -#define USB_DEV_ONLY_POS (15U) -#define USB_DEV_ONLY_LEN (1U) -#define USB_DEV_ONLY_MSK (((1U << USB_DEV_ONLY_LEN) - 1) << USB_DEV_ONLY_POS) -#define USB_DEV_ONLY_UMSK (~(((1U << USB_DEV_ONLY_LEN) - 1) << USB_DEV_ONLY_POS)) -#define USB_HOST_ONLY USB_HOST_ONLY -#define USB_HOST_ONLY_POS (16U) -#define USB_HOST_ONLY_LEN (1U) -#define USB_HOST_ONLY_MSK (((1U << USB_HOST_ONLY_LEN) - 1) << USB_HOST_ONLY_POS) -#define USB_HOST_ONLY_UMSK (~(((1U << USB_HOST_ONLY_LEN) - 1) << USB_HOST_ONLY_POS)) - -/* 0x0E8 : AXI_CR */ -#define USB_AXI_CR_OFFSET (0x0E8) -#define USB_AXI_SGLBST USB_AXI_SGLBST -#define USB_AXI_SGLBST_POS (0U) -#define USB_AXI_SGLBST_LEN (1U) -#define USB_AXI_SGLBST_MSK (((1U << USB_AXI_SGLBST_LEN) - 1) << USB_AXI_SGLBST_POS) -#define USB_AXI_SGLBST_UMSK (~(((1U << USB_AXI_SGLBST_LEN) - 1) << USB_AXI_SGLBST_POS)) - -/* 0x100 : DEV_CTL */ -#define USB_DEV_CTL_OFFSET (0x100) -#define USB_CAP_RMWAKUP USB_CAP_RMWAKUP -#define USB_CAP_RMWAKUP_POS (0U) -#define USB_CAP_RMWAKUP_LEN (1U) -#define USB_CAP_RMWAKUP_MSK (((1U << USB_CAP_RMWAKUP_LEN) - 1) << USB_CAP_RMWAKUP_POS) -#define USB_CAP_RMWAKUP_UMSK (~(((1U << USB_CAP_RMWAKUP_LEN) - 1) << USB_CAP_RMWAKUP_POS)) -#define USB_HALF_SPEED_HOV USB_HALF_SPEED_HOV -#define USB_HALF_SPEED_HOV_POS (1U) -#define USB_HALF_SPEED_HOV_LEN (1U) -#define USB_HALF_SPEED_HOV_MSK (((1U << USB_HALF_SPEED_HOV_LEN) - 1) << USB_HALF_SPEED_HOV_POS) -#define USB_HALF_SPEED_HOV_UMSK (~(((1U << USB_HALF_SPEED_HOV_LEN) - 1) << USB_HALF_SPEED_HOV_POS)) -#define USB_GLINT_EN_HOV USB_GLINT_EN_HOV -#define USB_GLINT_EN_HOV_POS (2U) -#define USB_GLINT_EN_HOV_LEN (1U) -#define USB_GLINT_EN_HOV_MSK (((1U << USB_GLINT_EN_HOV_LEN) - 1) << USB_GLINT_EN_HOV_POS) -#define USB_GLINT_EN_HOV_UMSK (~(((1U << USB_GLINT_EN_HOV_LEN) - 1) << USB_GLINT_EN_HOV_POS)) -#define USB_GOSUSP USB_GOSUSP -#define USB_GOSUSP_POS (3U) -#define USB_GOSUSP_LEN (1U) -#define USB_GOSUSP_MSK (((1U << USB_GOSUSP_LEN) - 1) << USB_GOSUSP_POS) -#define USB_GOSUSP_UMSK (~(((1U << USB_GOSUSP_LEN) - 1) << USB_GOSUSP_POS)) -#define USB_SFRST_HOV USB_SFRST_HOV -#define USB_SFRST_HOV_POS (4U) -#define USB_SFRST_HOV_LEN (1U) -#define USB_SFRST_HOV_MSK (((1U << USB_SFRST_HOV_LEN) - 1) << USB_SFRST_HOV_POS) -#define USB_SFRST_HOV_UMSK (~(((1U << USB_SFRST_HOV_LEN) - 1) << USB_SFRST_HOV_POS)) -#define USB_CHIP_EN_HOV USB_CHIP_EN_HOV -#define USB_CHIP_EN_HOV_POS (5U) -#define USB_CHIP_EN_HOV_LEN (1U) -#define USB_CHIP_EN_HOV_MSK (((1U << USB_CHIP_EN_HOV_LEN) - 1) << USB_CHIP_EN_HOV_POS) -#define USB_CHIP_EN_HOV_UMSK (~(((1U << USB_CHIP_EN_HOV_LEN) - 1) << USB_CHIP_EN_HOV_POS)) -#define USB_HS_EN_HOV USB_HS_EN_HOV -#define USB_HS_EN_HOV_POS (6U) -#define USB_HS_EN_HOV_LEN (1U) -#define USB_HS_EN_HOV_MSK (((1U << USB_HS_EN_HOV_LEN) - 1) << USB_HS_EN_HOV_POS) -#define USB_HS_EN_HOV_UMSK (~(((1U << USB_HS_EN_HOV_LEN) - 1) << USB_HS_EN_HOV_POS)) -#define USB_SYSBUS_WIDTH_HOV USB_SYSBUS_WIDTH_HOV -#define USB_SYSBUS_WIDTH_HOV_POS (7U) -#define USB_SYSBUS_WIDTH_HOV_LEN (1U) -#define USB_SYSBUS_WIDTH_HOV_MSK (((1U << USB_SYSBUS_WIDTH_HOV_LEN) - 1) << USB_SYSBUS_WIDTH_HOV_POS) -#define USB_SYSBUS_WIDTH_HOV_UMSK (~(((1U << USB_SYSBUS_WIDTH_HOV_LEN) - 1) << USB_SYSBUS_WIDTH_HOV_POS)) -#define USB_FORCE_FS USB_FORCE_FS -#define USB_FORCE_FS_POS (9U) -#define USB_FORCE_FS_LEN (1U) -#define USB_FORCE_FS_MSK (((1U << USB_FORCE_FS_LEN) - 1) << USB_FORCE_FS_POS) -#define USB_FORCE_FS_UMSK (~(((1U << USB_FORCE_FS_LEN) - 1) << USB_FORCE_FS_POS)) -#define USB_IDLE_DEGLITCH_HOV USB_IDLE_DEGLITCH_HOV -#define USB_IDLE_DEGLITCH_HOV_POS (10U) -#define USB_IDLE_DEGLITCH_HOV_LEN (2U) -#define USB_IDLE_DEGLITCH_HOV_MSK (((1U << USB_IDLE_DEGLITCH_HOV_LEN) - 1) << USB_IDLE_DEGLITCH_HOV_POS) -#define USB_IDLE_DEGLITCH_HOV_UMSK (~(((1U << USB_IDLE_DEGLITCH_HOV_LEN) - 1) << USB_IDLE_DEGLITCH_HOV_POS)) -#define USB_LPM_BESL_MAX USB_LPM_BESL_MAX -#define USB_LPM_BESL_MAX_POS (12U) -#define USB_LPM_BESL_MAX_LEN (4U) -#define USB_LPM_BESL_MAX_MSK (((1U << USB_LPM_BESL_MAX_LEN) - 1) << USB_LPM_BESL_MAX_POS) -#define USB_LPM_BESL_MAX_UMSK (~(((1U << USB_LPM_BESL_MAX_LEN) - 1) << USB_LPM_BESL_MAX_POS)) -#define USB_LPM_BESL_MIN USB_LPM_BESL_MIN -#define USB_LPM_BESL_MIN_POS (16U) -#define USB_LPM_BESL_MIN_LEN (4U) -#define USB_LPM_BESL_MIN_MSK (((1U << USB_LPM_BESL_MIN_LEN) - 1) << USB_LPM_BESL_MIN_POS) -#define USB_LPM_BESL_MIN_UMSK (~(((1U << USB_LPM_BESL_MIN_LEN) - 1) << USB_LPM_BESL_MIN_POS)) -#define USB_LPM_BESL USB_LPM_BESL -#define USB_LPM_BESL_POS (20U) -#define USB_LPM_BESL_LEN (4U) -#define USB_LPM_BESL_MSK (((1U << USB_LPM_BESL_LEN) - 1) << USB_LPM_BESL_POS) -#define USB_LPM_BESL_UMSK (~(((1U << USB_LPM_BESL_LEN) - 1) << USB_LPM_BESL_POS)) -#define USB_LPM_EN USB_LPM_EN -#define USB_LPM_EN_POS (25U) -#define USB_LPM_EN_LEN (1U) -#define USB_LPM_EN_MSK (((1U << USB_LPM_EN_LEN) - 1) << USB_LPM_EN_POS) -#define USB_LPM_EN_UMSK (~(((1U << USB_LPM_EN_LEN) - 1) << USB_LPM_EN_POS)) -#define USB_LPM_ACCEPT USB_LPM_ACCEPT -#define USB_LPM_ACCEPT_POS (26U) -#define USB_LPM_ACCEPT_LEN (1U) -#define USB_LPM_ACCEPT_MSK (((1U << USB_LPM_ACCEPT_LEN) - 1) << USB_LPM_ACCEPT_POS) -#define USB_LPM_ACCEPT_UMSK (~(((1U << USB_LPM_ACCEPT_LEN) - 1) << USB_LPM_ACCEPT_POS)) - -/* 0x104 : DEV_ADR */ -#define USB_DEV_ADR_OFFSET (0x104) -#define USB_DEVADR USB_DEVADR -#define USB_DEVADR_POS (0U) -#define USB_DEVADR_LEN (7U) -#define USB_DEVADR_MSK (((1U << USB_DEVADR_LEN) - 1) << USB_DEVADR_POS) -#define USB_DEVADR_UMSK (~(((1U << USB_DEVADR_LEN) - 1) << USB_DEVADR_POS)) -#define USB_AFT_CONF USB_AFT_CONF -#define USB_AFT_CONF_POS (7U) -#define USB_AFT_CONF_LEN (1U) -#define USB_AFT_CONF_MSK (((1U << USB_AFT_CONF_LEN) - 1) << USB_AFT_CONF_POS) -#define USB_AFT_CONF_UMSK (~(((1U << USB_AFT_CONF_LEN) - 1) << USB_AFT_CONF_POS)) - -/* 0x108 : DEV_TST */ -#define USB_DEV_TST_OFFSET (0x108) -#define USB_TST_CLRFF_HOV USB_TST_CLRFF_HOV -#define USB_TST_CLRFF_HOV_POS (0U) -#define USB_TST_CLRFF_HOV_LEN (1U) -#define USB_TST_CLRFF_HOV_MSK (((1U << USB_TST_CLRFF_HOV_LEN) - 1) << USB_TST_CLRFF_HOV_POS) -#define USB_TST_CLRFF_HOV_UMSK (~(((1U << USB_TST_CLRFF_HOV_LEN) - 1) << USB_TST_CLRFF_HOV_POS)) -#define USB_TST_LPCX USB_TST_LPCX -#define USB_TST_LPCX_POS (1U) -#define USB_TST_LPCX_LEN (1U) -#define USB_TST_LPCX_MSK (((1U << USB_TST_LPCX_LEN) - 1) << USB_TST_LPCX_POS) -#define USB_TST_LPCX_UMSK (~(((1U << USB_TST_LPCX_LEN) - 1) << USB_TST_LPCX_POS)) -#define USB_TST_CLREA USB_TST_CLREA -#define USB_TST_CLREA_POS (2U) -#define USB_TST_CLREA_LEN (1U) -#define USB_TST_CLREA_MSK (((1U << USB_TST_CLREA_LEN) - 1) << USB_TST_CLREA_POS) -#define USB_TST_CLREA_UMSK (~(((1U << USB_TST_CLREA_LEN) - 1) << USB_TST_CLREA_POS)) -#define USB_TST_DISTO_HOV USB_TST_DISTO_HOV -#define USB_TST_DISTO_HOV_POS (4U) -#define USB_TST_DISTO_HOV_LEN (1U) -#define USB_TST_DISTO_HOV_MSK (((1U << USB_TST_DISTO_HOV_LEN) - 1) << USB_TST_DISTO_HOV_POS) -#define USB_TST_DISTO_HOV_UMSK (~(((1U << USB_TST_DISTO_HOV_LEN) - 1) << USB_TST_DISTO_HOV_POS)) -#define USB_TST_MOD_HOV USB_TST_MOD_HOV -#define USB_TST_MOD_HOV_POS (5U) -#define USB_TST_MOD_HOV_LEN (1U) -#define USB_TST_MOD_HOV_MSK (((1U << USB_TST_MOD_HOV_LEN) - 1) << USB_TST_MOD_HOV_POS) -#define USB_TST_MOD_HOV_UMSK (~(((1U << USB_TST_MOD_HOV_LEN) - 1) << USB_TST_MOD_HOV_POS)) -#define USB_DISGENSOF USB_DISGENSOF -#define USB_DISGENSOF_POS (6U) -#define USB_DISGENSOF_LEN (1U) -#define USB_DISGENSOF_MSK (((1U << USB_DISGENSOF_LEN) - 1) << USB_DISGENSOF_POS) -#define USB_DISGENSOF_UMSK (~(((1U << USB_DISGENSOF_LEN) - 1) << USB_DISGENSOF_POS)) -#define USB_TST_MOD_TYP_HOV USB_TST_MOD_TYP_HOV -#define USB_TST_MOD_TYP_HOV_POS (7U) -#define USB_TST_MOD_TYP_HOV_LEN (1U) -#define USB_TST_MOD_TYP_HOV_MSK (((1U << USB_TST_MOD_TYP_HOV_LEN) - 1) << USB_TST_MOD_TYP_HOV_POS) -#define USB_TST_MOD_TYP_HOV_UMSK (~(((1U << USB_TST_MOD_TYP_HOV_LEN) - 1) << USB_TST_MOD_TYP_HOV_POS)) - -/* 0x10C : DEV_SFN */ -#define USB_DEV_SFN_OFFSET (0x10C) -#define USB_SOFN USB_SOFN -#define USB_SOFN_POS (0U) -#define USB_SOFN_LEN (11U) -#define USB_SOFN_MSK (((1U << USB_SOFN_LEN) - 1) << USB_SOFN_POS) -#define USB_SOFN_UMSK (~(((1U << USB_SOFN_LEN) - 1) << USB_SOFN_POS)) -#define USB_USOFN USB_USOFN -#define USB_USOFN_POS (11U) -#define USB_USOFN_LEN (3U) -#define USB_USOFN_MSK (((1U << USB_USOFN_LEN) - 1) << USB_USOFN_POS) -#define USB_USOFN_UMSK (~(((1U << USB_USOFN_LEN) - 1) << USB_USOFN_POS)) - -/* 0x110 : DEV_SMT */ -#define USB_DEV_SMT_OFFSET (0x110) -#define USB_SOFMT USB_SOFMT -#define USB_SOFMT_POS (0U) -#define USB_SOFMT_LEN (16U) -#define USB_SOFMT_MSK (((1U << USB_SOFMT_LEN) - 1) << USB_SOFMT_POS) -#define USB_SOFMT_UMSK (~(((1U << USB_SOFMT_LEN) - 1) << USB_SOFMT_POS)) - -/* 0x114 : PHY_TST */ -#define USB_PHY_TST_OFFSET (0x114) -#define USB_UNPLUG USB_UNPLUG -#define USB_UNPLUG_POS (0U) -#define USB_UNPLUG_LEN (1U) -#define USB_UNPLUG_MSK (((1U << USB_UNPLUG_LEN) - 1) << USB_UNPLUG_POS) -#define USB_UNPLUG_UMSK (~(((1U << USB_UNPLUG_LEN) - 1) << USB_UNPLUG_POS)) -#define USB_TST_JSTA USB_TST_JSTA -#define USB_TST_JSTA_POS (1U) -#define USB_TST_JSTA_LEN (1U) -#define USB_TST_JSTA_MSK (((1U << USB_TST_JSTA_LEN) - 1) << USB_TST_JSTA_POS) -#define USB_TST_JSTA_UMSK (~(((1U << USB_TST_JSTA_LEN) - 1) << USB_TST_JSTA_POS)) -#define USB_TST_KSTA USB_TST_KSTA -#define USB_TST_KSTA_POS (2U) -#define USB_TST_KSTA_LEN (1U) -#define USB_TST_KSTA_MSK (((1U << USB_TST_KSTA_LEN) - 1) << USB_TST_KSTA_POS) -#define USB_TST_KSTA_UMSK (~(((1U << USB_TST_KSTA_LEN) - 1) << USB_TST_KSTA_POS)) -#define USB_TST_SE0NAK USB_TST_SE0NAK -#define USB_TST_SE0NAK_POS (3U) -#define USB_TST_SE0NAK_LEN (1U) -#define USB_TST_SE0NAK_MSK (((1U << USB_TST_SE0NAK_LEN) - 1) << USB_TST_SE0NAK_POS) -#define USB_TST_SE0NAK_UMSK (~(((1U << USB_TST_SE0NAK_LEN) - 1) << USB_TST_SE0NAK_POS)) -#define USB_TST_PKT USB_TST_PKT -#define USB_TST_PKT_POS (4U) -#define USB_TST_PKT_LEN (1U) -#define USB_TST_PKT_MSK (((1U << USB_TST_PKT_LEN) - 1) << USB_TST_PKT_POS) -#define USB_TST_PKT_UMSK (~(((1U << USB_TST_PKT_LEN) - 1) << USB_TST_PKT_POS)) - -/* 0x118 : DEV_VCTL */ -#define USB_DEV_VCTL_OFFSET (0x118) -#define USB_VCTL_HOV USB_VCTL_HOV -#define USB_VCTL_HOV_POS (0U) -#define USB_VCTL_HOV_LEN (5U) -#define USB_VCTL_HOV_MSK (((1U << USB_VCTL_HOV_LEN) - 1) << USB_VCTL_HOV_POS) -#define USB_VCTL_HOV_UMSK (~(((1U << USB_VCTL_HOV_LEN) - 1) << USB_VCTL_HOV_POS)) -#define USB_VCTLOAD_N_HOV USB_VCTLOAD_N_HOV -#define USB_VCTLOAD_N_HOV_POS (5U) -#define USB_VCTLOAD_N_HOV_LEN (1U) -#define USB_VCTLOAD_N_HOV_MSK (((1U << USB_VCTLOAD_N_HOV_LEN) - 1) << USB_VCTLOAD_N_HOV_POS) -#define USB_VCTLOAD_N_HOV_UMSK (~(((1U << USB_VCTLOAD_N_HOV_LEN) - 1) << USB_VCTLOAD_N_HOV_POS)) - -/* 0x11C : DEV_CXCFG */ -#define USB_DEV_CXCFG_OFFSET (0x11C) -#define USB_VSTA_HOV USB_VSTA_HOV -#define USB_VSTA_HOV_POS (0U) -#define USB_VSTA_HOV_LEN (8U) -#define USB_VSTA_HOV_MSK (((1U << USB_VSTA_HOV_LEN) - 1) << USB_VSTA_HOV_POS) -#define USB_VSTA_HOV_UMSK (~(((1U << USB_VSTA_HOV_LEN) - 1) << USB_VSTA_HOV_POS)) - -/* 0x120 : DEV_CXCFE */ -#define USB_DEV_CXCFE_OFFSET (0x120) -#define USB_CX_DONE USB_CX_DONE -#define USB_CX_DONE_POS (0U) -#define USB_CX_DONE_LEN (1U) -#define USB_CX_DONE_MSK (((1U << USB_CX_DONE_LEN) - 1) << USB_CX_DONE_POS) -#define USB_CX_DONE_UMSK (~(((1U << USB_CX_DONE_LEN) - 1) << USB_CX_DONE_POS)) -#define USB_TST_PKDONE USB_TST_PKDONE -#define USB_TST_PKDONE_POS (1U) -#define USB_TST_PKDONE_LEN (1U) -#define USB_TST_PKDONE_MSK (((1U << USB_TST_PKDONE_LEN) - 1) << USB_TST_PKDONE_POS) -#define USB_TST_PKDONE_UMSK (~(((1U << USB_TST_PKDONE_LEN) - 1) << USB_TST_PKDONE_POS)) -#define USB_CX_STL USB_CX_STL -#define USB_CX_STL_POS (2U) -#define USB_CX_STL_LEN (1U) -#define USB_CX_STL_MSK (((1U << USB_CX_STL_LEN) - 1) << USB_CX_STL_POS) -#define USB_CX_STL_UMSK (~(((1U << USB_CX_STL_LEN) - 1) << USB_CX_STL_POS)) -#define USB_CX_CLR USB_CX_CLR -#define USB_CX_CLR_POS (3U) -#define USB_CX_CLR_LEN (1U) -#define USB_CX_CLR_MSK (((1U << USB_CX_CLR_LEN) - 1) << USB_CX_CLR_POS) -#define USB_CX_CLR_UMSK (~(((1U << USB_CX_CLR_LEN) - 1) << USB_CX_CLR_POS)) -#define USB_CX_FUL USB_CX_FUL -#define USB_CX_FUL_POS (4U) -#define USB_CX_FUL_LEN (1U) -#define USB_CX_FUL_MSK (((1U << USB_CX_FUL_LEN) - 1) << USB_CX_FUL_POS) -#define USB_CX_FUL_UMSK (~(((1U << USB_CX_FUL_LEN) - 1) << USB_CX_FUL_POS)) -#define USB_CX_EMP USB_CX_EMP -#define USB_CX_EMP_POS (5U) -#define USB_CX_EMP_LEN (1U) -#define USB_CX_EMP_MSK (((1U << USB_CX_EMP_LEN) - 1) << USB_CX_EMP_POS) -#define USB_CX_EMP_UMSK (~(((1U << USB_CX_EMP_LEN) - 1) << USB_CX_EMP_POS)) -#define USB_F0_EMP USB_F0_EMP -#define USB_F0_EMP_POS (8U) -#define USB_F0_EMP_LEN (1U) -#define USB_F0_EMP_MSK (((1U << USB_F0_EMP_LEN) - 1) << USB_F0_EMP_POS) -#define USB_F0_EMP_UMSK (~(((1U << USB_F0_EMP_LEN) - 1) << USB_F0_EMP_POS)) -#define USB_F1_EMP USB_F1_EMP -#define USB_F1_EMP_POS (9U) -#define USB_F1_EMP_LEN (1U) -#define USB_F1_EMP_MSK (((1U << USB_F1_EMP_LEN) - 1) << USB_F1_EMP_POS) -#define USB_F1_EMP_UMSK (~(((1U << USB_F1_EMP_LEN) - 1) << USB_F1_EMP_POS)) -#define USB_F2_EMP USB_F2_EMP -#define USB_F2_EMP_POS (10U) -#define USB_F2_EMP_LEN (1U) -#define USB_F2_EMP_MSK (((1U << USB_F2_EMP_LEN) - 1) << USB_F2_EMP_POS) -#define USB_F2_EMP_UMSK (~(((1U << USB_F2_EMP_LEN) - 1) << USB_F2_EMP_POS)) -#define USB_F3_EMP USB_F3_EMP -#define USB_F3_EMP_POS (11U) -#define USB_F3_EMP_LEN (1U) -#define USB_F3_EMP_MSK (((1U << USB_F3_EMP_LEN) - 1) << USB_F3_EMP_POS) -#define USB_F3_EMP_UMSK (~(((1U << USB_F3_EMP_LEN) - 1) << USB_F3_EMP_POS)) -#define USB_F4_EMP USB_F4_EMP -#define USB_F4_EMP_POS (12U) -#define USB_F4_EMP_LEN (1U) -#define USB_F4_EMP_MSK (((1U << USB_F4_EMP_LEN) - 1) << USB_F4_EMP_POS) -#define USB_F4_EMP_UMSK (~(((1U << USB_F4_EMP_LEN) - 1) << USB_F4_EMP_POS)) -#define USB_F5_EMP USB_F5_EMP -#define USB_F5_EMP_POS (13U) -#define USB_F5_EMP_LEN (1U) -#define USB_F5_EMP_MSK (((1U << USB_F5_EMP_LEN) - 1) << USB_F5_EMP_POS) -#define USB_F5_EMP_UMSK (~(((1U << USB_F5_EMP_LEN) - 1) << USB_F5_EMP_POS)) -#define USB_F6_EMP USB_F6_EMP -#define USB_F6_EMP_POS (14U) -#define USB_F6_EMP_LEN (1U) -#define USB_F6_EMP_MSK (((1U << USB_F6_EMP_LEN) - 1) << USB_F6_EMP_POS) -#define USB_F6_EMP_UMSK (~(((1U << USB_F6_EMP_LEN) - 1) << USB_F6_EMP_POS)) -#define USB_F7_EMP USB_F7_EMP -#define USB_F7_EMP_POS (15U) -#define USB_F7_EMP_LEN (1U) -#define USB_F7_EMP_MSK (((1U << USB_F7_EMP_LEN) - 1) << USB_F7_EMP_POS) -#define USB_F7_EMP_UMSK (~(((1U << USB_F7_EMP_LEN) - 1) << USB_F7_EMP_POS)) -#define USB_F8_EMP USB_F8_EMP -#define USB_F8_EMP_POS (16U) -#define USB_F8_EMP_LEN (1U) -#define USB_F8_EMP_MSK (((1U << USB_F8_EMP_LEN) - 1) << USB_F8_EMP_POS) -#define USB_F8_EMP_UMSK (~(((1U << USB_F8_EMP_LEN) - 1) << USB_F8_EMP_POS)) -#define USB_F9_EMP USB_F9_EMP -#define USB_F9_EMP_POS (17U) -#define USB_F9_EMP_LEN (1U) -#define USB_F9_EMP_MSK (((1U << USB_F9_EMP_LEN) - 1) << USB_F9_EMP_POS) -#define USB_F9_EMP_UMSK (~(((1U << USB_F9_EMP_LEN) - 1) << USB_F9_EMP_POS)) -#define USB_F10_EMP USB_F10_EMP -#define USB_F10_EMP_POS (18U) -#define USB_F10_EMP_LEN (1U) -#define USB_F10_EMP_MSK (((1U << USB_F10_EMP_LEN) - 1) << USB_F10_EMP_POS) -#define USB_F10_EMP_UMSK (~(((1U << USB_F10_EMP_LEN) - 1) << USB_F10_EMP_POS)) -#define USB_F11_EMP USB_F11_EMP -#define USB_F11_EMP_POS (19U) -#define USB_F11_EMP_LEN (1U) -#define USB_F11_EMP_MSK (((1U << USB_F11_EMP_LEN) - 1) << USB_F11_EMP_POS) -#define USB_F11_EMP_UMSK (~(((1U << USB_F11_EMP_LEN) - 1) << USB_F11_EMP_POS)) -#define USB_F12_EMP USB_F12_EMP -#define USB_F12_EMP_POS (20U) -#define USB_F12_EMP_LEN (1U) -#define USB_F12_EMP_MSK (((1U << USB_F12_EMP_LEN) - 1) << USB_F12_EMP_POS) -#define USB_F12_EMP_UMSK (~(((1U << USB_F12_EMP_LEN) - 1) << USB_F12_EMP_POS)) -#define USB_F13_EMP USB_F13_EMP -#define USB_F13_EMP_POS (21U) -#define USB_F13_EMP_LEN (1U) -#define USB_F13_EMP_MSK (((1U << USB_F13_EMP_LEN) - 1) << USB_F13_EMP_POS) -#define USB_F13_EMP_UMSK (~(((1U << USB_F13_EMP_LEN) - 1) << USB_F13_EMP_POS)) -#define USB_F14_EMP USB_F14_EMP -#define USB_F14_EMP_POS (22U) -#define USB_F14_EMP_LEN (1U) -#define USB_F14_EMP_MSK (((1U << USB_F14_EMP_LEN) - 1) << USB_F14_EMP_POS) -#define USB_F14_EMP_UMSK (~(((1U << USB_F14_EMP_LEN) - 1) << USB_F14_EMP_POS)) -#define USB_F15_EMP USB_F15_EMP -#define USB_F15_EMP_POS (23U) -#define USB_F15_EMP_LEN (1U) -#define USB_F15_EMP_MSK (((1U << USB_F15_EMP_LEN) - 1) << USB_F15_EMP_POS) -#define USB_F15_EMP_UMSK (~(((1U << USB_F15_EMP_LEN) - 1) << USB_F15_EMP_POS)) -#define USB_CX_FNT USB_CX_FNT -#define USB_CX_FNT_POS (24U) -#define USB_CX_FNT_LEN (7U) -#define USB_CX_FNT_MSK (((1U << USB_CX_FNT_LEN) - 1) << USB_CX_FNT_POS) -#define USB_CX_FNT_UMSK (~(((1U << USB_CX_FNT_LEN) - 1) << USB_CX_FNT_POS)) - -/* 0x124 : DEV_ICR */ -#define USB_DEV_ICR_OFFSET (0x124) -#define USB_IDLE_CNT USB_IDLE_CNT -#define USB_IDLE_CNT_POS (0U) -#define USB_IDLE_CNT_LEN (3U) -#define USB_IDLE_CNT_MSK (((1U << USB_IDLE_CNT_LEN) - 1) << USB_IDLE_CNT_POS) -#define USB_IDLE_CNT_UMSK (~(((1U << USB_IDLE_CNT_LEN) - 1) << USB_IDLE_CNT_POS)) - -/* 0x130 : DEV_MIGR */ -#define USB_DEV_MIGR_OFFSET (0x130) -#define USB_MINT_G0 USB_MINT_G0 -#define USB_MINT_G0_POS (0U) -#define USB_MINT_G0_LEN (1U) -#define USB_MINT_G0_MSK (((1U << USB_MINT_G0_LEN) - 1) << USB_MINT_G0_POS) -#define USB_MINT_G0_UMSK (~(((1U << USB_MINT_G0_LEN) - 1) << USB_MINT_G0_POS)) -#define USB_MINT_G1 USB_MINT_G1 -#define USB_MINT_G1_POS (1U) -#define USB_MINT_G1_LEN (1U) -#define USB_MINT_G1_MSK (((1U << USB_MINT_G1_LEN) - 1) << USB_MINT_G1_POS) -#define USB_MINT_G1_UMSK (~(((1U << USB_MINT_G1_LEN) - 1) << USB_MINT_G1_POS)) -#define USB_MINT_G2 USB_MINT_G2 -#define USB_MINT_G2_POS (2U) -#define USB_MINT_G2_LEN (1U) -#define USB_MINT_G2_MSK (((1U << USB_MINT_G2_LEN) - 1) << USB_MINT_G2_POS) -#define USB_MINT_G2_UMSK (~(((1U << USB_MINT_G2_LEN) - 1) << USB_MINT_G2_POS)) -#define USB_MINT_G3 USB_MINT_G3 -#define USB_MINT_G3_POS (3U) -#define USB_MINT_G3_LEN (1U) -#define USB_MINT_G3_MSK (((1U << USB_MINT_G3_LEN) - 1) << USB_MINT_G3_POS) -#define USB_MINT_G3_UMSK (~(((1U << USB_MINT_G3_LEN) - 1) << USB_MINT_G3_POS)) -#define USB_MINT_G4 USB_MINT_G4 -#define USB_MINT_G4_POS (4U) -#define USB_MINT_G4_LEN (1U) -#define USB_MINT_G4_MSK (((1U << USB_MINT_G4_LEN) - 1) << USB_MINT_G4_POS) -#define USB_MINT_G4_UMSK (~(((1U << USB_MINT_G4_LEN) - 1) << USB_MINT_G4_POS)) - -/* 0x134 : DEV_MISG0 */ -#define USB_DEV_MISG0_OFFSET (0x134) -#define USB_MCX_SETUP_INT USB_MCX_SETUP_INT -#define USB_MCX_SETUP_INT_POS (0U) -#define USB_MCX_SETUP_INT_LEN (1U) -#define USB_MCX_SETUP_INT_MSK (((1U << USB_MCX_SETUP_INT_LEN) - 1) << USB_MCX_SETUP_INT_POS) -#define USB_MCX_SETUP_INT_UMSK (~(((1U << USB_MCX_SETUP_INT_LEN) - 1) << USB_MCX_SETUP_INT_POS)) -#define USB_MCX_IN_INT USB_MCX_IN_INT -#define USB_MCX_IN_INT_POS (1U) -#define USB_MCX_IN_INT_LEN (1U) -#define USB_MCX_IN_INT_MSK (((1U << USB_MCX_IN_INT_LEN) - 1) << USB_MCX_IN_INT_POS) -#define USB_MCX_IN_INT_UMSK (~(((1U << USB_MCX_IN_INT_LEN) - 1) << USB_MCX_IN_INT_POS)) -#define USB_MCX_OUT_INT USB_MCX_OUT_INT -#define USB_MCX_OUT_INT_POS (2U) -#define USB_MCX_OUT_INT_LEN (1U) -#define USB_MCX_OUT_INT_MSK (((1U << USB_MCX_OUT_INT_LEN) - 1) << USB_MCX_OUT_INT_POS) -#define USB_MCX_OUT_INT_UMSK (~(((1U << USB_MCX_OUT_INT_LEN) - 1) << USB_MCX_OUT_INT_POS)) -#define USB_MCX_COMFAIL_INT USB_MCX_COMFAIL_INT -#define USB_MCX_COMFAIL_INT_POS (4U) -#define USB_MCX_COMFAIL_INT_LEN (1U) -#define USB_MCX_COMFAIL_INT_MSK (((1U << USB_MCX_COMFAIL_INT_LEN) - 1) << USB_MCX_COMFAIL_INT_POS) -#define USB_MCX_COMFAIL_INT_UMSK (~(((1U << USB_MCX_COMFAIL_INT_LEN) - 1) << USB_MCX_COMFAIL_INT_POS)) -#define USB_MCX_COMABORT_INT USB_MCX_COMABORT_INT -#define USB_MCX_COMABORT_INT_POS (5U) -#define USB_MCX_COMABORT_INT_LEN (1U) -#define USB_MCX_COMABORT_INT_MSK (((1U << USB_MCX_COMABORT_INT_LEN) - 1) << USB_MCX_COMABORT_INT_POS) -#define USB_MCX_COMABORT_INT_UMSK (~(((1U << USB_MCX_COMABORT_INT_LEN) - 1) << USB_MCX_COMABORT_INT_POS)) - -/* 0x138 : DEV_MISG1 */ -#define USB_DEV_MISG1_OFFSET (0x138) -#define USB_MF0_OUT_INT USB_MF0_OUT_INT -#define USB_MF0_OUT_INT_POS (0U) -#define USB_MF0_OUT_INT_LEN (1U) -#define USB_MF0_OUT_INT_MSK (((1U << USB_MF0_OUT_INT_LEN) - 1) << USB_MF0_OUT_INT_POS) -#define USB_MF0_OUT_INT_UMSK (~(((1U << USB_MF0_OUT_INT_LEN) - 1) << USB_MF0_OUT_INT_POS)) -#define USB_MF0_SPK_INT USB_MF0_SPK_INT -#define USB_MF0_SPK_INT_POS (1U) -#define USB_MF0_SPK_INT_LEN (1U) -#define USB_MF0_SPK_INT_MSK (((1U << USB_MF0_SPK_INT_LEN) - 1) << USB_MF0_SPK_INT_POS) -#define USB_MF0_SPK_INT_UMSK (~(((1U << USB_MF0_SPK_INT_LEN) - 1) << USB_MF0_SPK_INT_POS)) -#define USB_MF1_OUT_INT USB_MF1_OUT_INT -#define USB_MF1_OUT_INT_POS (2U) -#define USB_MF1_OUT_INT_LEN (1U) -#define USB_MF1_OUT_INT_MSK (((1U << USB_MF1_OUT_INT_LEN) - 1) << USB_MF1_OUT_INT_POS) -#define USB_MF1_OUT_INT_UMSK (~(((1U << USB_MF1_OUT_INT_LEN) - 1) << USB_MF1_OUT_INT_POS)) -#define USB_MF1_SPK_INT USB_MF1_SPK_INT -#define USB_MF1_SPK_INT_POS (3U) -#define USB_MF1_SPK_INT_LEN (1U) -#define USB_MF1_SPK_INT_MSK (((1U << USB_MF1_SPK_INT_LEN) - 1) << USB_MF1_SPK_INT_POS) -#define USB_MF1_SPK_INT_UMSK (~(((1U << USB_MF1_SPK_INT_LEN) - 1) << USB_MF1_SPK_INT_POS)) -#define USB_MF2_OUT_INT USB_MF2_OUT_INT -#define USB_MF2_OUT_INT_POS (4U) -#define USB_MF2_OUT_INT_LEN (1U) -#define USB_MF2_OUT_INT_MSK (((1U << USB_MF2_OUT_INT_LEN) - 1) << USB_MF2_OUT_INT_POS) -#define USB_MF2_OUT_INT_UMSK (~(((1U << USB_MF2_OUT_INT_LEN) - 1) << USB_MF2_OUT_INT_POS)) -#define USB_MF2_SPK_INT USB_MF2_SPK_INT -#define USB_MF2_SPK_INT_POS (5U) -#define USB_MF2_SPK_INT_LEN (1U) -#define USB_MF2_SPK_INT_MSK (((1U << USB_MF2_SPK_INT_LEN) - 1) << USB_MF2_SPK_INT_POS) -#define USB_MF2_SPK_INT_UMSK (~(((1U << USB_MF2_SPK_INT_LEN) - 1) << USB_MF2_SPK_INT_POS)) -#define USB_MF3_OUT_INT USB_MF3_OUT_INT -#define USB_MF3_OUT_INT_POS (6U) -#define USB_MF3_OUT_INT_LEN (1U) -#define USB_MF3_OUT_INT_MSK (((1U << USB_MF3_OUT_INT_LEN) - 1) << USB_MF3_OUT_INT_POS) -#define USB_MF3_OUT_INT_UMSK (~(((1U << USB_MF3_OUT_INT_LEN) - 1) << USB_MF3_OUT_INT_POS)) -#define USB_MF3_SPK_INT USB_MF3_SPK_INT -#define USB_MF3_SPK_INT_POS (7U) -#define USB_MF3_SPK_INT_LEN (1U) -#define USB_MF3_SPK_INT_MSK (((1U << USB_MF3_SPK_INT_LEN) - 1) << USB_MF3_SPK_INT_POS) -#define USB_MF3_SPK_INT_UMSK (~(((1U << USB_MF3_SPK_INT_LEN) - 1) << USB_MF3_SPK_INT_POS)) -#define USB_MF4_OUT_INT USB_MF4_OUT_INT -#define USB_MF4_OUT_INT_POS (8U) -#define USB_MF4_OUT_INT_LEN (1U) -#define USB_MF4_OUT_INT_MSK (((1U << USB_MF4_OUT_INT_LEN) - 1) << USB_MF4_OUT_INT_POS) -#define USB_MF4_OUT_INT_UMSK (~(((1U << USB_MF4_OUT_INT_LEN) - 1) << USB_MF4_OUT_INT_POS)) -#define USB_MF4_SPK_INT USB_MF4_SPK_INT -#define USB_MF4_SPK_INT_POS (9U) -#define USB_MF4_SPK_INT_LEN (1U) -#define USB_MF4_SPK_INT_MSK (((1U << USB_MF4_SPK_INT_LEN) - 1) << USB_MF4_SPK_INT_POS) -#define USB_MF4_SPK_INT_UMSK (~(((1U << USB_MF4_SPK_INT_LEN) - 1) << USB_MF4_SPK_INT_POS)) -#define USB_MF5_OUT_INT USB_MF5_OUT_INT -#define USB_MF5_OUT_INT_POS (10U) -#define USB_MF5_OUT_INT_LEN (1U) -#define USB_MF5_OUT_INT_MSK (((1U << USB_MF5_OUT_INT_LEN) - 1) << USB_MF5_OUT_INT_POS) -#define USB_MF5_OUT_INT_UMSK (~(((1U << USB_MF5_OUT_INT_LEN) - 1) << USB_MF5_OUT_INT_POS)) -#define USB_MF5_SPK_INT USB_MF5_SPK_INT -#define USB_MF5_SPK_INT_POS (11U) -#define USB_MF5_SPK_INT_LEN (1U) -#define USB_MF5_SPK_INT_MSK (((1U << USB_MF5_SPK_INT_LEN) - 1) << USB_MF5_SPK_INT_POS) -#define USB_MF5_SPK_INT_UMSK (~(((1U << USB_MF5_SPK_INT_LEN) - 1) << USB_MF5_SPK_INT_POS)) -#define USB_MF6_OUT_INT USB_MF6_OUT_INT -#define USB_MF6_OUT_INT_POS (12U) -#define USB_MF6_OUT_INT_LEN (1U) -#define USB_MF6_OUT_INT_MSK (((1U << USB_MF6_OUT_INT_LEN) - 1) << USB_MF6_OUT_INT_POS) -#define USB_MF6_OUT_INT_UMSK (~(((1U << USB_MF6_OUT_INT_LEN) - 1) << USB_MF6_OUT_INT_POS)) -#define USB_MF6_SPK_INT USB_MF6_SPK_INT -#define USB_MF6_SPK_INT_POS (13U) -#define USB_MF6_SPK_INT_LEN (1U) -#define USB_MF6_SPK_INT_MSK (((1U << USB_MF6_SPK_INT_LEN) - 1) << USB_MF6_SPK_INT_POS) -#define USB_MF6_SPK_INT_UMSK (~(((1U << USB_MF6_SPK_INT_LEN) - 1) << USB_MF6_SPK_INT_POS)) -#define USB_MF7_OUT_INT USB_MF7_OUT_INT -#define USB_MF7_OUT_INT_POS (14U) -#define USB_MF7_OUT_INT_LEN (1U) -#define USB_MF7_OUT_INT_MSK (((1U << USB_MF7_OUT_INT_LEN) - 1) << USB_MF7_OUT_INT_POS) -#define USB_MF7_OUT_INT_UMSK (~(((1U << USB_MF7_OUT_INT_LEN) - 1) << USB_MF7_OUT_INT_POS)) -#define USB_MF7_SPK_INT USB_MF7_SPK_INT -#define USB_MF7_SPK_INT_POS (15U) -#define USB_MF7_SPK_INT_LEN (1U) -#define USB_MF7_SPK_INT_MSK (((1U << USB_MF7_SPK_INT_LEN) - 1) << USB_MF7_SPK_INT_POS) -#define USB_MF7_SPK_INT_UMSK (~(((1U << USB_MF7_SPK_INT_LEN) - 1) << USB_MF7_SPK_INT_POS)) -#define USB_MF0_IN_INT USB_MF0_IN_INT -#define USB_MF0_IN_INT_POS (16U) -#define USB_MF0_IN_INT_LEN (1U) -#define USB_MF0_IN_INT_MSK (((1U << USB_MF0_IN_INT_LEN) - 1) << USB_MF0_IN_INT_POS) -#define USB_MF0_IN_INT_UMSK (~(((1U << USB_MF0_IN_INT_LEN) - 1) << USB_MF0_IN_INT_POS)) -#define USB_MF1_IN_INT USB_MF1_IN_INT -#define USB_MF1_IN_INT_POS (17U) -#define USB_MF1_IN_INT_LEN (1U) -#define USB_MF1_IN_INT_MSK (((1U << USB_MF1_IN_INT_LEN) - 1) << USB_MF1_IN_INT_POS) -#define USB_MF1_IN_INT_UMSK (~(((1U << USB_MF1_IN_INT_LEN) - 1) << USB_MF1_IN_INT_POS)) -#define USB_MF2_IN_INT USB_MF2_IN_INT -#define USB_MF2_IN_INT_POS (18U) -#define USB_MF2_IN_INT_LEN (1U) -#define USB_MF2_IN_INT_MSK (((1U << USB_MF2_IN_INT_LEN) - 1) << USB_MF2_IN_INT_POS) -#define USB_MF2_IN_INT_UMSK (~(((1U << USB_MF2_IN_INT_LEN) - 1) << USB_MF2_IN_INT_POS)) -#define USB_MF3_IN_INT USB_MF3_IN_INT -#define USB_MF3_IN_INT_POS (19U) -#define USB_MF3_IN_INT_LEN (1U) -#define USB_MF3_IN_INT_MSK (((1U << USB_MF3_IN_INT_LEN) - 1) << USB_MF3_IN_INT_POS) -#define USB_MF3_IN_INT_UMSK (~(((1U << USB_MF3_IN_INT_LEN) - 1) << USB_MF3_IN_INT_POS)) -#define USB_MF4_IN_INT USB_MF4_IN_INT -#define USB_MF4_IN_INT_POS (20U) -#define USB_MF4_IN_INT_LEN (1U) -#define USB_MF4_IN_INT_MSK (((1U << USB_MF4_IN_INT_LEN) - 1) << USB_MF4_IN_INT_POS) -#define USB_MF4_IN_INT_UMSK (~(((1U << USB_MF4_IN_INT_LEN) - 1) << USB_MF4_IN_INT_POS)) -#define USB_MF5_IN_INT USB_MF5_IN_INT -#define USB_MF5_IN_INT_POS (21U) -#define USB_MF5_IN_INT_LEN (1U) -#define USB_MF5_IN_INT_MSK (((1U << USB_MF5_IN_INT_LEN) - 1) << USB_MF5_IN_INT_POS) -#define USB_MF5_IN_INT_UMSK (~(((1U << USB_MF5_IN_INT_LEN) - 1) << USB_MF5_IN_INT_POS)) -#define USB_MF6_IN_INT USB_MF6_IN_INT -#define USB_MF6_IN_INT_POS (22U) -#define USB_MF6_IN_INT_LEN (1U) -#define USB_MF6_IN_INT_MSK (((1U << USB_MF6_IN_INT_LEN) - 1) << USB_MF6_IN_INT_POS) -#define USB_MF6_IN_INT_UMSK (~(((1U << USB_MF6_IN_INT_LEN) - 1) << USB_MF6_IN_INT_POS)) -#define USB_MF7_IN_INT USB_MF7_IN_INT -#define USB_MF7_IN_INT_POS (23U) -#define USB_MF7_IN_INT_LEN (1U) -#define USB_MF7_IN_INT_MSK (((1U << USB_MF7_IN_INT_LEN) - 1) << USB_MF7_IN_INT_POS) -#define USB_MF7_IN_INT_UMSK (~(((1U << USB_MF7_IN_INT_LEN) - 1) << USB_MF7_IN_INT_POS)) -#define USB_MF8_IN_INT USB_MF8_IN_INT -#define USB_MF8_IN_INT_POS (24U) -#define USB_MF8_IN_INT_LEN (1U) -#define USB_MF8_IN_INT_MSK (((1U << USB_MF8_IN_INT_LEN) - 1) << USB_MF8_IN_INT_POS) -#define USB_MF8_IN_INT_UMSK (~(((1U << USB_MF8_IN_INT_LEN) - 1) << USB_MF8_IN_INT_POS)) -#define USB_MF9_IN_INT USB_MF9_IN_INT -#define USB_MF9_IN_INT_POS (25U) -#define USB_MF9_IN_INT_LEN (1U) -#define USB_MF9_IN_INT_MSK (((1U << USB_MF9_IN_INT_LEN) - 1) << USB_MF9_IN_INT_POS) -#define USB_MF9_IN_INT_UMSK (~(((1U << USB_MF9_IN_INT_LEN) - 1) << USB_MF9_IN_INT_POS)) -#define USB_MF10_IN_INT USB_MF10_IN_INT -#define USB_MF10_IN_INT_POS (26U) -#define USB_MF10_IN_INT_LEN (1U) -#define USB_MF10_IN_INT_MSK (((1U << USB_MF10_IN_INT_LEN) - 1) << USB_MF10_IN_INT_POS) -#define USB_MF10_IN_INT_UMSK (~(((1U << USB_MF10_IN_INT_LEN) - 1) << USB_MF10_IN_INT_POS)) -#define USB_MF11_IN_INT USB_MF11_IN_INT -#define USB_MF11_IN_INT_POS (27U) -#define USB_MF11_IN_INT_LEN (1U) -#define USB_MF11_IN_INT_MSK (((1U << USB_MF11_IN_INT_LEN) - 1) << USB_MF11_IN_INT_POS) -#define USB_MF11_IN_INT_UMSK (~(((1U << USB_MF11_IN_INT_LEN) - 1) << USB_MF11_IN_INT_POS)) -#define USB_MF12_IN_INT USB_MF12_IN_INT -#define USB_MF12_IN_INT_POS (28U) -#define USB_MF12_IN_INT_LEN (1U) -#define USB_MF12_IN_INT_MSK (((1U << USB_MF12_IN_INT_LEN) - 1) << USB_MF12_IN_INT_POS) -#define USB_MF12_IN_INT_UMSK (~(((1U << USB_MF12_IN_INT_LEN) - 1) << USB_MF12_IN_INT_POS)) -#define USB_MF13_IN_INT USB_MF13_IN_INT -#define USB_MF13_IN_INT_POS (29U) -#define USB_MF13_IN_INT_LEN (1U) -#define USB_MF13_IN_INT_MSK (((1U << USB_MF13_IN_INT_LEN) - 1) << USB_MF13_IN_INT_POS) -#define USB_MF13_IN_INT_UMSK (~(((1U << USB_MF13_IN_INT_LEN) - 1) << USB_MF13_IN_INT_POS)) -#define USB_MF14_IN_INT USB_MF14_IN_INT -#define USB_MF14_IN_INT_POS (30U) -#define USB_MF14_IN_INT_LEN (1U) -#define USB_MF14_IN_INT_MSK (((1U << USB_MF14_IN_INT_LEN) - 1) << USB_MF14_IN_INT_POS) -#define USB_MF14_IN_INT_UMSK (~(((1U << USB_MF14_IN_INT_LEN) - 1) << USB_MF14_IN_INT_POS)) -#define USB_MF15_IN_INT USB_MF15_IN_INT -#define USB_MF15_IN_INT_POS (31U) -#define USB_MF15_IN_INT_LEN (1U) -#define USB_MF15_IN_INT_MSK (((1U << USB_MF15_IN_INT_LEN) - 1) << USB_MF15_IN_INT_POS) -#define USB_MF15_IN_INT_UMSK (~(((1U << USB_MF15_IN_INT_LEN) - 1) << USB_MF15_IN_INT_POS)) - -/* 0x13C : DEV_MISG2 */ -#define USB_DEV_MISG2_OFFSET (0x13C) -#define USB_MUSBRST_INT USB_MUSBRST_INT -#define USB_MUSBRST_INT_POS (0U) -#define USB_MUSBRST_INT_LEN (1U) -#define USB_MUSBRST_INT_MSK (((1U << USB_MUSBRST_INT_LEN) - 1) << USB_MUSBRST_INT_POS) -#define USB_MUSBRST_INT_UMSK (~(((1U << USB_MUSBRST_INT_LEN) - 1) << USB_MUSBRST_INT_POS)) -#define USB_MSUSP_INT USB_MSUSP_INT -#define USB_MSUSP_INT_POS (1U) -#define USB_MSUSP_INT_LEN (1U) -#define USB_MSUSP_INT_MSK (((1U << USB_MSUSP_INT_LEN) - 1) << USB_MSUSP_INT_POS) -#define USB_MSUSP_INT_UMSK (~(((1U << USB_MSUSP_INT_LEN) - 1) << USB_MSUSP_INT_POS)) -#define USB_MRESM_INT USB_MRESM_INT -#define USB_MRESM_INT_POS (2U) -#define USB_MRESM_INT_LEN (1U) -#define USB_MRESM_INT_MSK (((1U << USB_MRESM_INT_LEN) - 1) << USB_MRESM_INT_POS) -#define USB_MRESM_INT_UMSK (~(((1U << USB_MRESM_INT_LEN) - 1) << USB_MRESM_INT_POS)) -#define USB_MSEQ_ERR_INT USB_MSEQ_ERR_INT -#define USB_MSEQ_ERR_INT_POS (3U) -#define USB_MSEQ_ERR_INT_LEN (1U) -#define USB_MSEQ_ERR_INT_MSK (((1U << USB_MSEQ_ERR_INT_LEN) - 1) << USB_MSEQ_ERR_INT_POS) -#define USB_MSEQ_ERR_INT_UMSK (~(((1U << USB_MSEQ_ERR_INT_LEN) - 1) << USB_MSEQ_ERR_INT_POS)) -#define USB_MSEQ_ABORT_INT USB_MSEQ_ABORT_INT -#define USB_MSEQ_ABORT_INT_POS (4U) -#define USB_MSEQ_ABORT_INT_LEN (1U) -#define USB_MSEQ_ABORT_INT_MSK (((1U << USB_MSEQ_ABORT_INT_LEN) - 1) << USB_MSEQ_ABORT_INT_POS) -#define USB_MSEQ_ABORT_INT_UMSK (~(((1U << USB_MSEQ_ABORT_INT_LEN) - 1) << USB_MSEQ_ABORT_INT_POS)) -#define USB_MTX0BYTE_INT USB_MTX0BYTE_INT -#define USB_MTX0BYTE_INT_POS (5U) -#define USB_MTX0BYTE_INT_LEN (1U) -#define USB_MTX0BYTE_INT_MSK (((1U << USB_MTX0BYTE_INT_LEN) - 1) << USB_MTX0BYTE_INT_POS) -#define USB_MTX0BYTE_INT_UMSK (~(((1U << USB_MTX0BYTE_INT_LEN) - 1) << USB_MTX0BYTE_INT_POS)) -#define USB_MRX0BYTE_INT USB_MRX0BYTE_INT -#define USB_MRX0BYTE_INT_POS (6U) -#define USB_MRX0BYTE_INT_LEN (1U) -#define USB_MRX0BYTE_INT_MSK (((1U << USB_MRX0BYTE_INT_LEN) - 1) << USB_MRX0BYTE_INT_POS) -#define USB_MRX0BYTE_INT_UMSK (~(((1U << USB_MRX0BYTE_INT_LEN) - 1) << USB_MRX0BYTE_INT_POS)) -#define USB_MDMA_CMPLT_HOV USB_MDMA_CMPLT_HOV -#define USB_MDMA_CMPLT_HOV_POS (7U) -#define USB_MDMA_CMPLT_HOV_LEN (1U) -#define USB_MDMA_CMPLT_HOV_MSK (((1U << USB_MDMA_CMPLT_HOV_LEN) - 1) << USB_MDMA_CMPLT_HOV_POS) -#define USB_MDMA_CMPLT_HOV_UMSK (~(((1U << USB_MDMA_CMPLT_HOV_LEN) - 1) << USB_MDMA_CMPLT_HOV_POS)) -#define USB_MDMA_ERROR_HOV USB_MDMA_ERROR_HOV -#define USB_MDMA_ERROR_HOV_POS (8U) -#define USB_MDMA_ERROR_HOV_LEN (1U) -#define USB_MDMA_ERROR_HOV_MSK (((1U << USB_MDMA_ERROR_HOV_LEN) - 1) << USB_MDMA_ERROR_HOV_POS) -#define USB_MDMA_ERROR_HOV_UMSK (~(((1U << USB_MDMA_ERROR_HOV_LEN) - 1) << USB_MDMA_ERROR_HOV_POS)) -#define USB_MDEV_IDLE_HOV USB_MDEV_IDLE_HOV -#define USB_MDEV_IDLE_HOV_POS (9U) -#define USB_MDEV_IDLE_HOV_LEN (1U) -#define USB_MDEV_IDLE_HOV_MSK (((1U << USB_MDEV_IDLE_HOV_LEN) - 1) << USB_MDEV_IDLE_HOV_POS) -#define USB_MDEV_IDLE_HOV_UMSK (~(((1U << USB_MDEV_IDLE_HOV_LEN) - 1) << USB_MDEV_IDLE_HOV_POS)) -#define USB_MDEV_WAKEUP_BYVBUS USB_MDEV_WAKEUP_BYVBUS -#define USB_MDEV_WAKEUP_BYVBUS_POS (10U) -#define USB_MDEV_WAKEUP_BYVBUS_LEN (1U) -#define USB_MDEV_WAKEUP_BYVBUS_MSK (((1U << USB_MDEV_WAKEUP_BYVBUS_LEN) - 1) << USB_MDEV_WAKEUP_BYVBUS_POS) -#define USB_MDEV_WAKEUP_BYVBUS_UMSK (~(((1U << USB_MDEV_WAKEUP_BYVBUS_LEN) - 1) << USB_MDEV_WAKEUP_BYVBUS_POS)) -#define USB_MF8_OUT_INT USB_MF8_OUT_INT -#define USB_MF8_OUT_INT_POS (16U) -#define USB_MF8_OUT_INT_LEN (1U) -#define USB_MF8_OUT_INT_MSK (((1U << USB_MF8_OUT_INT_LEN) - 1) << USB_MF8_OUT_INT_POS) -#define USB_MF8_OUT_INT_UMSK (~(((1U << USB_MF8_OUT_INT_LEN) - 1) << USB_MF8_OUT_INT_POS)) -#define USB_MF8_SPK_INT USB_MF8_SPK_INT -#define USB_MF8_SPK_INT_POS (17U) -#define USB_MF8_SPK_INT_LEN (1U) -#define USB_MF8_SPK_INT_MSK (((1U << USB_MF8_SPK_INT_LEN) - 1) << USB_MF8_SPK_INT_POS) -#define USB_MF8_SPK_INT_UMSK (~(((1U << USB_MF8_SPK_INT_LEN) - 1) << USB_MF8_SPK_INT_POS)) -#define USB_MF9_OUT_INT USB_MF9_OUT_INT -#define USB_MF9_OUT_INT_POS (18U) -#define USB_MF9_OUT_INT_LEN (1U) -#define USB_MF9_OUT_INT_MSK (((1U << USB_MF9_OUT_INT_LEN) - 1) << USB_MF9_OUT_INT_POS) -#define USB_MF9_OUT_INT_UMSK (~(((1U << USB_MF9_OUT_INT_LEN) - 1) << USB_MF9_OUT_INT_POS)) -#define USB_MF9_SPK_INT USB_MF9_SPK_INT -#define USB_MF9_SPK_INT_POS (19U) -#define USB_MF9_SPK_INT_LEN (1U) -#define USB_MF9_SPK_INT_MSK (((1U << USB_MF9_SPK_INT_LEN) - 1) << USB_MF9_SPK_INT_POS) -#define USB_MF9_SPK_INT_UMSK (~(((1U << USB_MF9_SPK_INT_LEN) - 1) << USB_MF9_SPK_INT_POS)) -#define USB_MF10_OUT_INT USB_MF10_OUT_INT -#define USB_MF10_OUT_INT_POS (20U) -#define USB_MF10_OUT_INT_LEN (1U) -#define USB_MF10_OUT_INT_MSK (((1U << USB_MF10_OUT_INT_LEN) - 1) << USB_MF10_OUT_INT_POS) -#define USB_MF10_OUT_INT_UMSK (~(((1U << USB_MF10_OUT_INT_LEN) - 1) << USB_MF10_OUT_INT_POS)) -#define USB_MF10_SPK_INT USB_MF10_SPK_INT -#define USB_MF10_SPK_INT_POS (21U) -#define USB_MF10_SPK_INT_LEN (1U) -#define USB_MF10_SPK_INT_MSK (((1U << USB_MF10_SPK_INT_LEN) - 1) << USB_MF10_SPK_INT_POS) -#define USB_MF10_SPK_INT_UMSK (~(((1U << USB_MF10_SPK_INT_LEN) - 1) << USB_MF10_SPK_INT_POS)) -#define USB_MF11_OUT_INT USB_MF11_OUT_INT -#define USB_MF11_OUT_INT_POS (22U) -#define USB_MF11_OUT_INT_LEN (1U) -#define USB_MF11_OUT_INT_MSK (((1U << USB_MF11_OUT_INT_LEN) - 1) << USB_MF11_OUT_INT_POS) -#define USB_MF11_OUT_INT_UMSK (~(((1U << USB_MF11_OUT_INT_LEN) - 1) << USB_MF11_OUT_INT_POS)) -#define USB_MF11_SPK_INT USB_MF11_SPK_INT -#define USB_MF11_SPK_INT_POS (23U) -#define USB_MF11_SPK_INT_LEN (1U) -#define USB_MF11_SPK_INT_MSK (((1U << USB_MF11_SPK_INT_LEN) - 1) << USB_MF11_SPK_INT_POS) -#define USB_MF11_SPK_INT_UMSK (~(((1U << USB_MF11_SPK_INT_LEN) - 1) << USB_MF11_SPK_INT_POS)) -#define USB_MF12_OUT_INT USB_MF12_OUT_INT -#define USB_MF12_OUT_INT_POS (24U) -#define USB_MF12_OUT_INT_LEN (1U) -#define USB_MF12_OUT_INT_MSK (((1U << USB_MF12_OUT_INT_LEN) - 1) << USB_MF12_OUT_INT_POS) -#define USB_MF12_OUT_INT_UMSK (~(((1U << USB_MF12_OUT_INT_LEN) - 1) << USB_MF12_OUT_INT_POS)) -#define USB_MF12_SPK_INT USB_MF12_SPK_INT -#define USB_MF12_SPK_INT_POS (25U) -#define USB_MF12_SPK_INT_LEN (1U) -#define USB_MF12_SPK_INT_MSK (((1U << USB_MF12_SPK_INT_LEN) - 1) << USB_MF12_SPK_INT_POS) -#define USB_MF12_SPK_INT_UMSK (~(((1U << USB_MF12_SPK_INT_LEN) - 1) << USB_MF12_SPK_INT_POS)) -#define USB_MF13_OUT_INT USB_MF13_OUT_INT -#define USB_MF13_OUT_INT_POS (26U) -#define USB_MF13_OUT_INT_LEN (1U) -#define USB_MF13_OUT_INT_MSK (((1U << USB_MF13_OUT_INT_LEN) - 1) << USB_MF13_OUT_INT_POS) -#define USB_MF13_OUT_INT_UMSK (~(((1U << USB_MF13_OUT_INT_LEN) - 1) << USB_MF13_OUT_INT_POS)) -#define USB_MF13_SPK_INT USB_MF13_SPK_INT -#define USB_MF13_SPK_INT_POS (27U) -#define USB_MF13_SPK_INT_LEN (1U) -#define USB_MF13_SPK_INT_MSK (((1U << USB_MF13_SPK_INT_LEN) - 1) << USB_MF13_SPK_INT_POS) -#define USB_MF13_SPK_INT_UMSK (~(((1U << USB_MF13_SPK_INT_LEN) - 1) << USB_MF13_SPK_INT_POS)) -#define USB_MF14_OUT_INT USB_MF14_OUT_INT -#define USB_MF14_OUT_INT_POS (28U) -#define USB_MF14_OUT_INT_LEN (1U) -#define USB_MF14_OUT_INT_MSK (((1U << USB_MF14_OUT_INT_LEN) - 1) << USB_MF14_OUT_INT_POS) -#define USB_MF14_OUT_INT_UMSK (~(((1U << USB_MF14_OUT_INT_LEN) - 1) << USB_MF14_OUT_INT_POS)) -#define USB_MF14_SPK_INT USB_MF14_SPK_INT -#define USB_MF14_SPK_INT_POS (29U) -#define USB_MF14_SPK_INT_LEN (1U) -#define USB_MF14_SPK_INT_MSK (((1U << USB_MF14_SPK_INT_LEN) - 1) << USB_MF14_SPK_INT_POS) -#define USB_MF14_SPK_INT_UMSK (~(((1U << USB_MF14_SPK_INT_LEN) - 1) << USB_MF14_SPK_INT_POS)) -#define USB_MF15_OUT_INT USB_MF15_OUT_INT -#define USB_MF15_OUT_INT_POS (30U) -#define USB_MF15_OUT_INT_LEN (1U) -#define USB_MF15_OUT_INT_MSK (((1U << USB_MF15_OUT_INT_LEN) - 1) << USB_MF15_OUT_INT_POS) -#define USB_MF15_OUT_INT_UMSK (~(((1U << USB_MF15_OUT_INT_LEN) - 1) << USB_MF15_OUT_INT_POS)) -#define USB_MF15_SPK_INT USB_MF15_SPK_INT -#define USB_MF15_SPK_INT_POS (31U) -#define USB_MF15_SPK_INT_LEN (1U) -#define USB_MF15_SPK_INT_MSK (((1U << USB_MF15_SPK_INT_LEN) - 1) << USB_MF15_SPK_INT_POS) -#define USB_MF15_SPK_INT_UMSK (~(((1U << USB_MF15_SPK_INT_LEN) - 1) << USB_MF15_SPK_INT_POS)) - -/* 0x140 : DEV_IGR */ -#define USB_DEV_IGR_OFFSET (0x140) -#define USB_INT_G0 USB_INT_G0 -#define USB_INT_G0_POS (0U) -#define USB_INT_G0_LEN (1U) -#define USB_INT_G0_MSK (((1U << USB_INT_G0_LEN) - 1) << USB_INT_G0_POS) -#define USB_INT_G0_UMSK (~(((1U << USB_INT_G0_LEN) - 1) << USB_INT_G0_POS)) -#define USB_INT_G1 USB_INT_G1 -#define USB_INT_G1_POS (1U) -#define USB_INT_G1_LEN (1U) -#define USB_INT_G1_MSK (((1U << USB_INT_G1_LEN) - 1) << USB_INT_G1_POS) -#define USB_INT_G1_UMSK (~(((1U << USB_INT_G1_LEN) - 1) << USB_INT_G1_POS)) -#define USB_INT_G2_HOV USB_INT_G2_HOV -#define USB_INT_G2_HOV_POS (2U) -#define USB_INT_G2_HOV_LEN (1U) -#define USB_INT_G2_HOV_MSK (((1U << USB_INT_G2_HOV_LEN) - 1) << USB_INT_G2_HOV_POS) -#define USB_INT_G2_HOV_UMSK (~(((1U << USB_INT_G2_HOV_LEN) - 1) << USB_INT_G2_HOV_POS)) -#define USB_INT_G3 USB_INT_G3 -#define USB_INT_G3_POS (3U) -#define USB_INT_G3_LEN (1U) -#define USB_INT_G3_MSK (((1U << USB_INT_G3_LEN) - 1) << USB_INT_G3_POS) -#define USB_INT_G3_UMSK (~(((1U << USB_INT_G3_LEN) - 1) << USB_INT_G3_POS)) -#define USB_INT_G4 USB_INT_G4 -#define USB_INT_G4_POS (4U) -#define USB_INT_G4_LEN (1U) -#define USB_INT_G4_MSK (((1U << USB_INT_G4_LEN) - 1) << USB_INT_G4_POS) -#define USB_INT_G4_UMSK (~(((1U << USB_INT_G4_LEN) - 1) << USB_INT_G4_POS)) - -/* 0x144 : DEV_ISG0 */ -#define USB_DEV_ISG0_OFFSET (0x144) -#define USB_CX_SETUP_INT USB_CX_SETUP_INT -#define USB_CX_SETUP_INT_POS (0U) -#define USB_CX_SETUP_INT_LEN (1U) -#define USB_CX_SETUP_INT_MSK (((1U << USB_CX_SETUP_INT_LEN) - 1) << USB_CX_SETUP_INT_POS) -#define USB_CX_SETUP_INT_UMSK (~(((1U << USB_CX_SETUP_INT_LEN) - 1) << USB_CX_SETUP_INT_POS)) -#define USB_CX_IN_INT USB_CX_IN_INT -#define USB_CX_IN_INT_POS (1U) -#define USB_CX_IN_INT_LEN (1U) -#define USB_CX_IN_INT_MSK (((1U << USB_CX_IN_INT_LEN) - 1) << USB_CX_IN_INT_POS) -#define USB_CX_IN_INT_UMSK (~(((1U << USB_CX_IN_INT_LEN) - 1) << USB_CX_IN_INT_POS)) -#define USB_CX_OUT_INT USB_CX_OUT_INT -#define USB_CX_OUT_INT_POS (2U) -#define USB_CX_OUT_INT_LEN (1U) -#define USB_CX_OUT_INT_MSK (((1U << USB_CX_OUT_INT_LEN) - 1) << USB_CX_OUT_INT_POS) -#define USB_CX_OUT_INT_UMSK (~(((1U << USB_CX_OUT_INT_LEN) - 1) << USB_CX_OUT_INT_POS)) -#define USB_CX_COMFAIL_INT USB_CX_COMFAIL_INT -#define USB_CX_COMFAIL_INT_POS (4U) -#define USB_CX_COMFAIL_INT_LEN (1U) -#define USB_CX_COMFAIL_INT_MSK (((1U << USB_CX_COMFAIL_INT_LEN) - 1) << USB_CX_COMFAIL_INT_POS) -#define USB_CX_COMFAIL_INT_UMSK (~(((1U << USB_CX_COMFAIL_INT_LEN) - 1) << USB_CX_COMFAIL_INT_POS)) -#define USB_CX_COMABT_INT USB_CX_COMABT_INT -#define USB_CX_COMABT_INT_POS (5U) -#define USB_CX_COMABT_INT_LEN (1U) -#define USB_CX_COMABT_INT_MSK (((1U << USB_CX_COMABT_INT_LEN) - 1) << USB_CX_COMABT_INT_POS) -#define USB_CX_COMABT_INT_UMSK (~(((1U << USB_CX_COMABT_INT_LEN) - 1) << USB_CX_COMABT_INT_POS)) - -/* 0x148 : DEV_ISG1 */ -#define USB_DEV_ISG1_OFFSET (0x148) -#define USB_F0_OUT_INT USB_F0_OUT_INT -#define USB_F0_OUT_INT_POS (0U) -#define USB_F0_OUT_INT_LEN (1U) -#define USB_F0_OUT_INT_MSK (((1U << USB_F0_OUT_INT_LEN) - 1) << USB_F0_OUT_INT_POS) -#define USB_F0_OUT_INT_UMSK (~(((1U << USB_F0_OUT_INT_LEN) - 1) << USB_F0_OUT_INT_POS)) -#define USB_F0_SPK_INT USB_F0_SPK_INT -#define USB_F0_SPK_INT_POS (1U) -#define USB_F0_SPK_INT_LEN (1U) -#define USB_F0_SPK_INT_MSK (((1U << USB_F0_SPK_INT_LEN) - 1) << USB_F0_SPK_INT_POS) -#define USB_F0_SPK_INT_UMSK (~(((1U << USB_F0_SPK_INT_LEN) - 1) << USB_F0_SPK_INT_POS)) -#define USB_F1_OUT_INT USB_F1_OUT_INT -#define USB_F1_OUT_INT_POS (2U) -#define USB_F1_OUT_INT_LEN (1U) -#define USB_F1_OUT_INT_MSK (((1U << USB_F1_OUT_INT_LEN) - 1) << USB_F1_OUT_INT_POS) -#define USB_F1_OUT_INT_UMSK (~(((1U << USB_F1_OUT_INT_LEN) - 1) << USB_F1_OUT_INT_POS)) -#define USB_F1_SPK_INT USB_F1_SPK_INT -#define USB_F1_SPK_INT_POS (3U) -#define USB_F1_SPK_INT_LEN (1U) -#define USB_F1_SPK_INT_MSK (((1U << USB_F1_SPK_INT_LEN) - 1) << USB_F1_SPK_INT_POS) -#define USB_F1_SPK_INT_UMSK (~(((1U << USB_F1_SPK_INT_LEN) - 1) << USB_F1_SPK_INT_POS)) -#define USB_F2_OUT_INT USB_F2_OUT_INT -#define USB_F2_OUT_INT_POS (4U) -#define USB_F2_OUT_INT_LEN (1U) -#define USB_F2_OUT_INT_MSK (((1U << USB_F2_OUT_INT_LEN) - 1) << USB_F2_OUT_INT_POS) -#define USB_F2_OUT_INT_UMSK (~(((1U << USB_F2_OUT_INT_LEN) - 1) << USB_F2_OUT_INT_POS)) -#define USB_F2_SPK_INT USB_F2_SPK_INT -#define USB_F2_SPK_INT_POS (5U) -#define USB_F2_SPK_INT_LEN (1U) -#define USB_F2_SPK_INT_MSK (((1U << USB_F2_SPK_INT_LEN) - 1) << USB_F2_SPK_INT_POS) -#define USB_F2_SPK_INT_UMSK (~(((1U << USB_F2_SPK_INT_LEN) - 1) << USB_F2_SPK_INT_POS)) -#define USB_F3_OUT_INT USB_F3_OUT_INT -#define USB_F3_OUT_INT_POS (6U) -#define USB_F3_OUT_INT_LEN (1U) -#define USB_F3_OUT_INT_MSK (((1U << USB_F3_OUT_INT_LEN) - 1) << USB_F3_OUT_INT_POS) -#define USB_F3_OUT_INT_UMSK (~(((1U << USB_F3_OUT_INT_LEN) - 1) << USB_F3_OUT_INT_POS)) -#define USB_F3_SPK_INT USB_F3_SPK_INT -#define USB_F3_SPK_INT_POS (7U) -#define USB_F3_SPK_INT_LEN (1U) -#define USB_F3_SPK_INT_MSK (((1U << USB_F3_SPK_INT_LEN) - 1) << USB_F3_SPK_INT_POS) -#define USB_F3_SPK_INT_UMSK (~(((1U << USB_F3_SPK_INT_LEN) - 1) << USB_F3_SPK_INT_POS)) -#define USB_F4_OUT_INT USB_F4_OUT_INT -#define USB_F4_OUT_INT_POS (8U) -#define USB_F4_OUT_INT_LEN (1U) -#define USB_F4_OUT_INT_MSK (((1U << USB_F4_OUT_INT_LEN) - 1) << USB_F4_OUT_INT_POS) -#define USB_F4_OUT_INT_UMSK (~(((1U << USB_F4_OUT_INT_LEN) - 1) << USB_F4_OUT_INT_POS)) -#define USB_F4_SPK_INT USB_F4_SPK_INT -#define USB_F4_SPK_INT_POS (9U) -#define USB_F4_SPK_INT_LEN (1U) -#define USB_F4_SPK_INT_MSK (((1U << USB_F4_SPK_INT_LEN) - 1) << USB_F4_SPK_INT_POS) -#define USB_F4_SPK_INT_UMSK (~(((1U << USB_F4_SPK_INT_LEN) - 1) << USB_F4_SPK_INT_POS)) -#define USB_F5_OUT_INT USB_F5_OUT_INT -#define USB_F5_OUT_INT_POS (10U) -#define USB_F5_OUT_INT_LEN (1U) -#define USB_F5_OUT_INT_MSK (((1U << USB_F5_OUT_INT_LEN) - 1) << USB_F5_OUT_INT_POS) -#define USB_F5_OUT_INT_UMSK (~(((1U << USB_F5_OUT_INT_LEN) - 1) << USB_F5_OUT_INT_POS)) -#define USB_F5_SPK_INT USB_F5_SPK_INT -#define USB_F5_SPK_INT_POS (11U) -#define USB_F5_SPK_INT_LEN (1U) -#define USB_F5_SPK_INT_MSK (((1U << USB_F5_SPK_INT_LEN) - 1) << USB_F5_SPK_INT_POS) -#define USB_F5_SPK_INT_UMSK (~(((1U << USB_F5_SPK_INT_LEN) - 1) << USB_F5_SPK_INT_POS)) -#define USB_F6_OUT_INT USB_F6_OUT_INT -#define USB_F6_OUT_INT_POS (12U) -#define USB_F6_OUT_INT_LEN (1U) -#define USB_F6_OUT_INT_MSK (((1U << USB_F6_OUT_INT_LEN) - 1) << USB_F6_OUT_INT_POS) -#define USB_F6_OUT_INT_UMSK (~(((1U << USB_F6_OUT_INT_LEN) - 1) << USB_F6_OUT_INT_POS)) -#define USB_F6_SPK_INT USB_F6_SPK_INT -#define USB_F6_SPK_INT_POS (13U) -#define USB_F6_SPK_INT_LEN (1U) -#define USB_F6_SPK_INT_MSK (((1U << USB_F6_SPK_INT_LEN) - 1) << USB_F6_SPK_INT_POS) -#define USB_F6_SPK_INT_UMSK (~(((1U << USB_F6_SPK_INT_LEN) - 1) << USB_F6_SPK_INT_POS)) -#define USB_F7_OUT_INT USB_F7_OUT_INT -#define USB_F7_OUT_INT_POS (14U) -#define USB_F7_OUT_INT_LEN (1U) -#define USB_F7_OUT_INT_MSK (((1U << USB_F7_OUT_INT_LEN) - 1) << USB_F7_OUT_INT_POS) -#define USB_F7_OUT_INT_UMSK (~(((1U << USB_F7_OUT_INT_LEN) - 1) << USB_F7_OUT_INT_POS)) -#define USB_F7_SPK_INT USB_F7_SPK_INT -#define USB_F7_SPK_INT_POS (15U) -#define USB_F7_SPK_INT_LEN (1U) -#define USB_F7_SPK_INT_MSK (((1U << USB_F7_SPK_INT_LEN) - 1) << USB_F7_SPK_INT_POS) -#define USB_F7_SPK_INT_UMSK (~(((1U << USB_F7_SPK_INT_LEN) - 1) << USB_F7_SPK_INT_POS)) -#define USB_F0_IN_INT USB_F0_IN_INT -#define USB_F0_IN_INT_POS (16U) -#define USB_F0_IN_INT_LEN (1U) -#define USB_F0_IN_INT_MSK (((1U << USB_F0_IN_INT_LEN) - 1) << USB_F0_IN_INT_POS) -#define USB_F0_IN_INT_UMSK (~(((1U << USB_F0_IN_INT_LEN) - 1) << USB_F0_IN_INT_POS)) -#define USB_F1_IN_INT USB_F1_IN_INT -#define USB_F1_IN_INT_POS (17U) -#define USB_F1_IN_INT_LEN (1U) -#define USB_F1_IN_INT_MSK (((1U << USB_F1_IN_INT_LEN) - 1) << USB_F1_IN_INT_POS) -#define USB_F1_IN_INT_UMSK (~(((1U << USB_F1_IN_INT_LEN) - 1) << USB_F1_IN_INT_POS)) -#define USB_F2_IN_INT USB_F2_IN_INT -#define USB_F2_IN_INT_POS (18U) -#define USB_F2_IN_INT_LEN (1U) -#define USB_F2_IN_INT_MSK (((1U << USB_F2_IN_INT_LEN) - 1) << USB_F2_IN_INT_POS) -#define USB_F2_IN_INT_UMSK (~(((1U << USB_F2_IN_INT_LEN) - 1) << USB_F2_IN_INT_POS)) -#define USB_F3_IN_INT USB_F3_IN_INT -#define USB_F3_IN_INT_POS (19U) -#define USB_F3_IN_INT_LEN (1U) -#define USB_F3_IN_INT_MSK (((1U << USB_F3_IN_INT_LEN) - 1) << USB_F3_IN_INT_POS) -#define USB_F3_IN_INT_UMSK (~(((1U << USB_F3_IN_INT_LEN) - 1) << USB_F3_IN_INT_POS)) -#define USB_F4_IN_INT USB_F4_IN_INT -#define USB_F4_IN_INT_POS (20U) -#define USB_F4_IN_INT_LEN (1U) -#define USB_F4_IN_INT_MSK (((1U << USB_F4_IN_INT_LEN) - 1) << USB_F4_IN_INT_POS) -#define USB_F4_IN_INT_UMSK (~(((1U << USB_F4_IN_INT_LEN) - 1) << USB_F4_IN_INT_POS)) -#define USB_F5_IN_INT USB_F5_IN_INT -#define USB_F5_IN_INT_POS (21U) -#define USB_F5_IN_INT_LEN (1U) -#define USB_F5_IN_INT_MSK (((1U << USB_F5_IN_INT_LEN) - 1) << USB_F5_IN_INT_POS) -#define USB_F5_IN_INT_UMSK (~(((1U << USB_F5_IN_INT_LEN) - 1) << USB_F5_IN_INT_POS)) -#define USB_F6_IN_INT USB_F6_IN_INT -#define USB_F6_IN_INT_POS (22U) -#define USB_F6_IN_INT_LEN (1U) -#define USB_F6_IN_INT_MSK (((1U << USB_F6_IN_INT_LEN) - 1) << USB_F6_IN_INT_POS) -#define USB_F6_IN_INT_UMSK (~(((1U << USB_F6_IN_INT_LEN) - 1) << USB_F6_IN_INT_POS)) -#define USB_F7_IN_INT USB_F7_IN_INT -#define USB_F7_IN_INT_POS (23U) -#define USB_F7_IN_INT_LEN (1U) -#define USB_F7_IN_INT_MSK (((1U << USB_F7_IN_INT_LEN) - 1) << USB_F7_IN_INT_POS) -#define USB_F7_IN_INT_UMSK (~(((1U << USB_F7_IN_INT_LEN) - 1) << USB_F7_IN_INT_POS)) -#define USB_F8_IN_INT USB_F8_IN_INT -#define USB_F8_IN_INT_POS (24U) -#define USB_F8_IN_INT_LEN (1U) -#define USB_F8_IN_INT_MSK (((1U << USB_F8_IN_INT_LEN) - 1) << USB_F8_IN_INT_POS) -#define USB_F8_IN_INT_UMSK (~(((1U << USB_F8_IN_INT_LEN) - 1) << USB_F8_IN_INT_POS)) -#define USB_F9_IN_INT USB_F9_IN_INT -#define USB_F9_IN_INT_POS (25U) -#define USB_F9_IN_INT_LEN (1U) -#define USB_F9_IN_INT_MSK (((1U << USB_F9_IN_INT_LEN) - 1) << USB_F9_IN_INT_POS) -#define USB_F9_IN_INT_UMSK (~(((1U << USB_F9_IN_INT_LEN) - 1) << USB_F9_IN_INT_POS)) -#define USB_F10_IN_INT USB_F10_IN_INT -#define USB_F10_IN_INT_POS (26U) -#define USB_F10_IN_INT_LEN (1U) -#define USB_F10_IN_INT_MSK (((1U << USB_F10_IN_INT_LEN) - 1) << USB_F10_IN_INT_POS) -#define USB_F10_IN_INT_UMSK (~(((1U << USB_F10_IN_INT_LEN) - 1) << USB_F10_IN_INT_POS)) -#define USB_F11_IN_INT USB_F11_IN_INT -#define USB_F11_IN_INT_POS (27U) -#define USB_F11_IN_INT_LEN (1U) -#define USB_F11_IN_INT_MSK (((1U << USB_F11_IN_INT_LEN) - 1) << USB_F11_IN_INT_POS) -#define USB_F11_IN_INT_UMSK (~(((1U << USB_F11_IN_INT_LEN) - 1) << USB_F11_IN_INT_POS)) -#define USB_F12_IN_INT USB_F12_IN_INT -#define USB_F12_IN_INT_POS (28U) -#define USB_F12_IN_INT_LEN (1U) -#define USB_F12_IN_INT_MSK (((1U << USB_F12_IN_INT_LEN) - 1) << USB_F12_IN_INT_POS) -#define USB_F12_IN_INT_UMSK (~(((1U << USB_F12_IN_INT_LEN) - 1) << USB_F12_IN_INT_POS)) -#define USB_F13_IN_INT USB_F13_IN_INT -#define USB_F13_IN_INT_POS (29U) -#define USB_F13_IN_INT_LEN (1U) -#define USB_F13_IN_INT_MSK (((1U << USB_F13_IN_INT_LEN) - 1) << USB_F13_IN_INT_POS) -#define USB_F13_IN_INT_UMSK (~(((1U << USB_F13_IN_INT_LEN) - 1) << USB_F13_IN_INT_POS)) -#define USB_F14_IN_INT USB_F14_IN_INT -#define USB_F14_IN_INT_POS (30U) -#define USB_F14_IN_INT_LEN (1U) -#define USB_F14_IN_INT_MSK (((1U << USB_F14_IN_INT_LEN) - 1) << USB_F14_IN_INT_POS) -#define USB_F14_IN_INT_UMSK (~(((1U << USB_F14_IN_INT_LEN) - 1) << USB_F14_IN_INT_POS)) -#define USB_F15_IN_INT USB_F15_IN_INT -#define USB_F15_IN_INT_POS (31U) -#define USB_F15_IN_INT_LEN (1U) -#define USB_F15_IN_INT_MSK (((1U << USB_F15_IN_INT_LEN) - 1) << USB_F15_IN_INT_POS) -#define USB_F15_IN_INT_UMSK (~(((1U << USB_F15_IN_INT_LEN) - 1) << USB_F15_IN_INT_POS)) - -/* 0x14C : DEV_ISG2 */ -#define USB_DEV_ISG2_OFFSET (0x14C) -#define USBRST_INT USBRST_INT -#define USBRST_INT_POS (0U) -#define USBRST_INT_LEN (1U) -#define USBRST_INT_MSK (((1U << USBRST_INT_LEN) - 1) << USBRST_INT_POS) -#define USBRST_INT_UMSK (~(((1U << USBRST_INT_LEN) - 1) << USBRST_INT_POS)) -#define USB_SUSP_INT USB_SUSP_INT -#define USB_SUSP_INT_POS (1U) -#define USB_SUSP_INT_LEN (1U) -#define USB_SUSP_INT_MSK (((1U << USB_SUSP_INT_LEN) - 1) << USB_SUSP_INT_POS) -#define USB_SUSP_INT_UMSK (~(((1U << USB_SUSP_INT_LEN) - 1) << USB_SUSP_INT_POS)) -#define USB_RESM_INT USB_RESM_INT -#define USB_RESM_INT_POS (2U) -#define USB_RESM_INT_LEN (1U) -#define USB_RESM_INT_MSK (((1U << USB_RESM_INT_LEN) - 1) << USB_RESM_INT_POS) -#define USB_RESM_INT_UMSK (~(((1U << USB_RESM_INT_LEN) - 1) << USB_RESM_INT_POS)) -#define USB_ISO_SEQ_ERR_INT USB_ISO_SEQ_ERR_INT -#define USB_ISO_SEQ_ERR_INT_POS (3U) -#define USB_ISO_SEQ_ERR_INT_LEN (1U) -#define USB_ISO_SEQ_ERR_INT_MSK (((1U << USB_ISO_SEQ_ERR_INT_LEN) - 1) << USB_ISO_SEQ_ERR_INT_POS) -#define USB_ISO_SEQ_ERR_INT_UMSK (~(((1U << USB_ISO_SEQ_ERR_INT_LEN) - 1) << USB_ISO_SEQ_ERR_INT_POS)) -#define USB_ISO_SEQ_ABORT_INT USB_ISO_SEQ_ABORT_INT -#define USB_ISO_SEQ_ABORT_INT_POS (4U) -#define USB_ISO_SEQ_ABORT_INT_LEN (1U) -#define USB_ISO_SEQ_ABORT_INT_MSK (((1U << USB_ISO_SEQ_ABORT_INT_LEN) - 1) << USB_ISO_SEQ_ABORT_INT_POS) -#define USB_ISO_SEQ_ABORT_INT_UMSK (~(((1U << USB_ISO_SEQ_ABORT_INT_LEN) - 1) << USB_ISO_SEQ_ABORT_INT_POS)) -#define USB_TX0BYTE_INT USB_TX0BYTE_INT -#define USB_TX0BYTE_INT_POS (5U) -#define USB_TX0BYTE_INT_LEN (1U) -#define USB_TX0BYTE_INT_MSK (((1U << USB_TX0BYTE_INT_LEN) - 1) << USB_TX0BYTE_INT_POS) -#define USB_TX0BYTE_INT_UMSK (~(((1U << USB_TX0BYTE_INT_LEN) - 1) << USB_TX0BYTE_INT_POS)) -#define USB_RX0BYTE_INT USB_RX0BYTE_INT -#define USB_RX0BYTE_INT_POS (6U) -#define USB_RX0BYTE_INT_LEN (1U) -#define USB_RX0BYTE_INT_MSK (((1U << USB_RX0BYTE_INT_LEN) - 1) << USB_RX0BYTE_INT_POS) -#define USB_RX0BYTE_INT_UMSK (~(((1U << USB_RX0BYTE_INT_LEN) - 1) << USB_RX0BYTE_INT_POS)) -#define USB_DMA_CMPLT_HOV USB_DMA_CMPLT_HOV -#define USB_DMA_CMPLT_HOV_POS (7U) -#define USB_DMA_CMPLT_HOV_LEN (1U) -#define USB_DMA_CMPLT_HOV_MSK (((1U << USB_DMA_CMPLT_HOV_LEN) - 1) << USB_DMA_CMPLT_HOV_POS) -#define USB_DMA_CMPLT_HOV_UMSK (~(((1U << USB_DMA_CMPLT_HOV_LEN) - 1) << USB_DMA_CMPLT_HOV_POS)) -#define USB_DMA_ERROR_HOV USB_DMA_ERROR_HOV -#define USB_DMA_ERROR_HOV_POS (8U) -#define USB_DMA_ERROR_HOV_LEN (1U) -#define USB_DMA_ERROR_HOV_MSK (((1U << USB_DMA_ERROR_HOV_LEN) - 1) << USB_DMA_ERROR_HOV_POS) -#define USB_DMA_ERROR_HOV_UMSK (~(((1U << USB_DMA_ERROR_HOV_LEN) - 1) << USB_DMA_ERROR_HOV_POS)) -#define USB_DEV_IDLE_HOV USB_DEV_IDLE_HOV -#define USB_DEV_IDLE_HOV_POS (9U) -#define USB_DEV_IDLE_HOV_LEN (1U) -#define USB_DEV_IDLE_HOV_MSK (((1U << USB_DEV_IDLE_HOV_LEN) - 1) << USB_DEV_IDLE_HOV_POS) -#define USB_DEV_IDLE_HOV_UMSK (~(((1U << USB_DEV_IDLE_HOV_LEN) - 1) << USB_DEV_IDLE_HOV_POS)) -#define USB_DEV_WAKEUP_BYVBUS USB_DEV_WAKEUP_BYVBUS -#define USB_DEV_WAKEUP_BYVBUS_POS (10U) -#define USB_DEV_WAKEUP_BYVBUS_LEN (1U) -#define USB_DEV_WAKEUP_BYVBUS_MSK (((1U << USB_DEV_WAKEUP_BYVBUS_LEN) - 1) << USB_DEV_WAKEUP_BYVBUS_POS) -#define USB_DEV_WAKEUP_BYVBUS_UMSK (~(((1U << USB_DEV_WAKEUP_BYVBUS_LEN) - 1) << USB_DEV_WAKEUP_BYVBUS_POS)) -#define USB_F8_OUT_INT USB_F8_OUT_INT -#define USB_F8_OUT_INT_POS (16U) -#define USB_F8_OUT_INT_LEN (1U) -#define USB_F8_OUT_INT_MSK (((1U << USB_F8_OUT_INT_LEN) - 1) << USB_F8_OUT_INT_POS) -#define USB_F8_OUT_INT_UMSK (~(((1U << USB_F8_OUT_INT_LEN) - 1) << USB_F8_OUT_INT_POS)) -#define USB_F8_SPK_INT USB_F8_SPK_INT -#define USB_F8_SPK_INT_POS (17U) -#define USB_F8_SPK_INT_LEN (1U) -#define USB_F8_SPK_INT_MSK (((1U << USB_F8_SPK_INT_LEN) - 1) << USB_F8_SPK_INT_POS) -#define USB_F8_SPK_INT_UMSK (~(((1U << USB_F8_SPK_INT_LEN) - 1) << USB_F8_SPK_INT_POS)) -#define USB_F9_OUT_INT USB_F9_OUT_INT -#define USB_F9_OUT_INT_POS (18U) -#define USB_F9_OUT_INT_LEN (1U) -#define USB_F9_OUT_INT_MSK (((1U << USB_F9_OUT_INT_LEN) - 1) << USB_F9_OUT_INT_POS) -#define USB_F9_OUT_INT_UMSK (~(((1U << USB_F9_OUT_INT_LEN) - 1) << USB_F9_OUT_INT_POS)) -#define USB_F9_SPK_INT USB_F9_SPK_INT -#define USB_F9_SPK_INT_POS (19U) -#define USB_F9_SPK_INT_LEN (1U) -#define USB_F9_SPK_INT_MSK (((1U << USB_F9_SPK_INT_LEN) - 1) << USB_F9_SPK_INT_POS) -#define USB_F9_SPK_INT_UMSK (~(((1U << USB_F9_SPK_INT_LEN) - 1) << USB_F9_SPK_INT_POS)) -#define USB_F10_OUT_INT USB_F10_OUT_INT -#define USB_F10_OUT_INT_POS (20U) -#define USB_F10_OUT_INT_LEN (1U) -#define USB_F10_OUT_INT_MSK (((1U << USB_F10_OUT_INT_LEN) - 1) << USB_F10_OUT_INT_POS) -#define USB_F10_OUT_INT_UMSK (~(((1U << USB_F10_OUT_INT_LEN) - 1) << USB_F10_OUT_INT_POS)) -#define USB_F10_SPK_INT USB_F10_SPK_INT -#define USB_F10_SPK_INT_POS (21U) -#define USB_F10_SPK_INT_LEN (1U) -#define USB_F10_SPK_INT_MSK (((1U << USB_F10_SPK_INT_LEN) - 1) << USB_F10_SPK_INT_POS) -#define USB_F10_SPK_INT_UMSK (~(((1U << USB_F10_SPK_INT_LEN) - 1) << USB_F10_SPK_INT_POS)) -#define USB_F11_OUT_INT USB_F11_OUT_INT -#define USB_F11_OUT_INT_POS (22U) -#define USB_F11_OUT_INT_LEN (1U) -#define USB_F11_OUT_INT_MSK (((1U << USB_F11_OUT_INT_LEN) - 1) << USB_F11_OUT_INT_POS) -#define USB_F11_OUT_INT_UMSK (~(((1U << USB_F11_OUT_INT_LEN) - 1) << USB_F11_OUT_INT_POS)) -#define USB_F11_SPK_INT USB_F11_SPK_INT -#define USB_F11_SPK_INT_POS (23U) -#define USB_F11_SPK_INT_LEN (1U) -#define USB_F11_SPK_INT_MSK (((1U << USB_F11_SPK_INT_LEN) - 1) << USB_F11_SPK_INT_POS) -#define USB_F11_SPK_INT_UMSK (~(((1U << USB_F11_SPK_INT_LEN) - 1) << USB_F11_SPK_INT_POS)) -#define USB_F12_OUT_INT USB_F12_OUT_INT -#define USB_F12_OUT_INT_POS (24U) -#define USB_F12_OUT_INT_LEN (1U) -#define USB_F12_OUT_INT_MSK (((1U << USB_F12_OUT_INT_LEN) - 1) << USB_F12_OUT_INT_POS) -#define USB_F12_OUT_INT_UMSK (~(((1U << USB_F12_OUT_INT_LEN) - 1) << USB_F12_OUT_INT_POS)) -#define USB_F12_SPK_INT USB_F12_SPK_INT -#define USB_F12_SPK_INT_POS (25U) -#define USB_F12_SPK_INT_LEN (1U) -#define USB_F12_SPK_INT_MSK (((1U << USB_F12_SPK_INT_LEN) - 1) << USB_F12_SPK_INT_POS) -#define USB_F12_SPK_INT_UMSK (~(((1U << USB_F12_SPK_INT_LEN) - 1) << USB_F12_SPK_INT_POS)) -#define USB_F13_OUT_INT USB_F13_OUT_INT -#define USB_F13_OUT_INT_POS (26U) -#define USB_F13_OUT_INT_LEN (1U) -#define USB_F13_OUT_INT_MSK (((1U << USB_F13_OUT_INT_LEN) - 1) << USB_F13_OUT_INT_POS) -#define USB_F13_OUT_INT_UMSK (~(((1U << USB_F13_OUT_INT_LEN) - 1) << USB_F13_OUT_INT_POS)) -#define USB_F13_SPK_INT USB_F13_SPK_INT -#define USB_F13_SPK_INT_POS (27U) -#define USB_F13_SPK_INT_LEN (1U) -#define USB_F13_SPK_INT_MSK (((1U << USB_F13_SPK_INT_LEN) - 1) << USB_F13_SPK_INT_POS) -#define USB_F13_SPK_INT_UMSK (~(((1U << USB_F13_SPK_INT_LEN) - 1) << USB_F13_SPK_INT_POS)) -#define USB_F14_OUT_INT USB_F14_OUT_INT -#define USB_F14_OUT_INT_POS (28U) -#define USB_F14_OUT_INT_LEN (1U) -#define USB_F14_OUT_INT_MSK (((1U << USB_F14_OUT_INT_LEN) - 1) << USB_F14_OUT_INT_POS) -#define USB_F14_OUT_INT_UMSK (~(((1U << USB_F14_OUT_INT_LEN) - 1) << USB_F14_OUT_INT_POS)) -#define USB_F14_SPK_INT USB_F14_SPK_INT -#define USB_F14_SPK_INT_POS (29U) -#define USB_F14_SPK_INT_LEN (1U) -#define USB_F14_SPK_INT_MSK (((1U << USB_F14_SPK_INT_LEN) - 1) << USB_F14_SPK_INT_POS) -#define USB_F14_SPK_INT_UMSK (~(((1U << USB_F14_SPK_INT_LEN) - 1) << USB_F14_SPK_INT_POS)) -#define USB_F15_OUT_INT USB_F15_OUT_INT -#define USB_F15_OUT_INT_POS (30U) -#define USB_F15_OUT_INT_LEN (1U) -#define USB_F15_OUT_INT_MSK (((1U << USB_F15_OUT_INT_LEN) - 1) << USB_F15_OUT_INT_POS) -#define USB_F15_OUT_INT_UMSK (~(((1U << USB_F15_OUT_INT_LEN) - 1) << USB_F15_OUT_INT_POS)) -#define USB_F15_SPK_INT USB_F15_SPK_INT -#define USB_F15_SPK_INT_POS (31U) -#define USB_F15_SPK_INT_LEN (1U) -#define USB_F15_SPK_INT_MSK (((1U << USB_F15_SPK_INT_LEN) - 1) << USB_F15_SPK_INT_POS) -#define USB_F15_SPK_INT_UMSK (~(((1U << USB_F15_SPK_INT_LEN) - 1) << USB_F15_SPK_INT_POS)) - -/* 0x150 : DEV_RXZ */ -#define USB_DEV_RXZ_OFFSET (0x150) -#define USB_RX0BYTE_EP1 USB_RX0BYTE_EP1 -#define USB_RX0BYTE_EP1_POS (0U) -#define USB_RX0BYTE_EP1_LEN (1U) -#define USB_RX0BYTE_EP1_MSK (((1U << USB_RX0BYTE_EP1_LEN) - 1) << USB_RX0BYTE_EP1_POS) -#define USB_RX0BYTE_EP1_UMSK (~(((1U << USB_RX0BYTE_EP1_LEN) - 1) << USB_RX0BYTE_EP1_POS)) -#define USB_RX0BYTE_EP2 USB_RX0BYTE_EP2 -#define USB_RX0BYTE_EP2_POS (1U) -#define USB_RX0BYTE_EP2_LEN (1U) -#define USB_RX0BYTE_EP2_MSK (((1U << USB_RX0BYTE_EP2_LEN) - 1) << USB_RX0BYTE_EP2_POS) -#define USB_RX0BYTE_EP2_UMSK (~(((1U << USB_RX0BYTE_EP2_LEN) - 1) << USB_RX0BYTE_EP2_POS)) -#define USB_RX0BYTE_EP3 USB_RX0BYTE_EP3 -#define USB_RX0BYTE_EP3_POS (2U) -#define USB_RX0BYTE_EP3_LEN (1U) -#define USB_RX0BYTE_EP3_MSK (((1U << USB_RX0BYTE_EP3_LEN) - 1) << USB_RX0BYTE_EP3_POS) -#define USB_RX0BYTE_EP3_UMSK (~(((1U << USB_RX0BYTE_EP3_LEN) - 1) << USB_RX0BYTE_EP3_POS)) -#define USB_RX0BYTE_EP4 USB_RX0BYTE_EP4 -#define USB_RX0BYTE_EP4_POS (3U) -#define USB_RX0BYTE_EP4_LEN (1U) -#define USB_RX0BYTE_EP4_MSK (((1U << USB_RX0BYTE_EP4_LEN) - 1) << USB_RX0BYTE_EP4_POS) -#define USB_RX0BYTE_EP4_UMSK (~(((1U << USB_RX0BYTE_EP4_LEN) - 1) << USB_RX0BYTE_EP4_POS)) -#define USB_RX0BYTE_EP5 USB_RX0BYTE_EP5 -#define USB_RX0BYTE_EP5_POS (4U) -#define USB_RX0BYTE_EP5_LEN (1U) -#define USB_RX0BYTE_EP5_MSK (((1U << USB_RX0BYTE_EP5_LEN) - 1) << USB_RX0BYTE_EP5_POS) -#define USB_RX0BYTE_EP5_UMSK (~(((1U << USB_RX0BYTE_EP5_LEN) - 1) << USB_RX0BYTE_EP5_POS)) -#define USB_RX0BYTE_EP6 USB_RX0BYTE_EP6 -#define USB_RX0BYTE_EP6_POS (5U) -#define USB_RX0BYTE_EP6_LEN (1U) -#define USB_RX0BYTE_EP6_MSK (((1U << USB_RX0BYTE_EP6_LEN) - 1) << USB_RX0BYTE_EP6_POS) -#define USB_RX0BYTE_EP6_UMSK (~(((1U << USB_RX0BYTE_EP6_LEN) - 1) << USB_RX0BYTE_EP6_POS)) -#define USB_RX0BYTE_EP7 USB_RX0BYTE_EP7 -#define USB_RX0BYTE_EP7_POS (6U) -#define USB_RX0BYTE_EP7_LEN (1U) -#define USB_RX0BYTE_EP7_MSK (((1U << USB_RX0BYTE_EP7_LEN) - 1) << USB_RX0BYTE_EP7_POS) -#define USB_RX0BYTE_EP7_UMSK (~(((1U << USB_RX0BYTE_EP7_LEN) - 1) << USB_RX0BYTE_EP7_POS)) -#define USB_RX0BYTE_EP8 USB_RX0BYTE_EP8 -#define USB_RX0BYTE_EP8_POS (7U) -#define USB_RX0BYTE_EP8_LEN (1U) -#define USB_RX0BYTE_EP8_MSK (((1U << USB_RX0BYTE_EP8_LEN) - 1) << USB_RX0BYTE_EP8_POS) -#define USB_RX0BYTE_EP8_UMSK (~(((1U << USB_RX0BYTE_EP8_LEN) - 1) << USB_RX0BYTE_EP8_POS)) - -/* 0x154 : DEV_TXZ */ -#define USB_DEV_TXZ_OFFSET (0x154) -#define USB_TX0BYTE_EP1 USB_TX0BYTE_EP1 -#define USB_TX0BYTE_EP1_POS (0U) -#define USB_TX0BYTE_EP1_LEN (1U) -#define USB_TX0BYTE_EP1_MSK (((1U << USB_TX0BYTE_EP1_LEN) - 1) << USB_TX0BYTE_EP1_POS) -#define USB_TX0BYTE_EP1_UMSK (~(((1U << USB_TX0BYTE_EP1_LEN) - 1) << USB_TX0BYTE_EP1_POS)) -#define USB_TX0BYTE_EP2 USB_TX0BYTE_EP2 -#define USB_TX0BYTE_EP2_POS (1U) -#define USB_TX0BYTE_EP2_LEN (1U) -#define USB_TX0BYTE_EP2_MSK (((1U << USB_TX0BYTE_EP2_LEN) - 1) << USB_TX0BYTE_EP2_POS) -#define USB_TX0BYTE_EP2_UMSK (~(((1U << USB_TX0BYTE_EP2_LEN) - 1) << USB_TX0BYTE_EP2_POS)) -#define USB_TX0BYTE_EP3 USB_TX0BYTE_EP3 -#define USB_TX0BYTE_EP3_POS (2U) -#define USB_TX0BYTE_EP3_LEN (1U) -#define USB_TX0BYTE_EP3_MSK (((1U << USB_TX0BYTE_EP3_LEN) - 1) << USB_TX0BYTE_EP3_POS) -#define USB_TX0BYTE_EP3_UMSK (~(((1U << USB_TX0BYTE_EP3_LEN) - 1) << USB_TX0BYTE_EP3_POS)) -#define USB_TX0BYTE_EP4 USB_TX0BYTE_EP4 -#define USB_TX0BYTE_EP4_POS (3U) -#define USB_TX0BYTE_EP4_LEN (1U) -#define USB_TX0BYTE_EP4_MSK (((1U << USB_TX0BYTE_EP4_LEN) - 1) << USB_TX0BYTE_EP4_POS) -#define USB_TX0BYTE_EP4_UMSK (~(((1U << USB_TX0BYTE_EP4_LEN) - 1) << USB_TX0BYTE_EP4_POS)) -#define USB_TX0BYTE_EP5 USB_TX0BYTE_EP5 -#define USB_TX0BYTE_EP5_POS (4U) -#define USB_TX0BYTE_EP5_LEN (1U) -#define USB_TX0BYTE_EP5_MSK (((1U << USB_TX0BYTE_EP5_LEN) - 1) << USB_TX0BYTE_EP5_POS) -#define USB_TX0BYTE_EP5_UMSK (~(((1U << USB_TX0BYTE_EP5_LEN) - 1) << USB_TX0BYTE_EP5_POS)) -#define USB_TX0BYTE_EP6 USB_TX0BYTE_EP6 -#define USB_TX0BYTE_EP6_POS (5U) -#define USB_TX0BYTE_EP6_LEN (1U) -#define USB_TX0BYTE_EP6_MSK (((1U << USB_TX0BYTE_EP6_LEN) - 1) << USB_TX0BYTE_EP6_POS) -#define USB_TX0BYTE_EP6_UMSK (~(((1U << USB_TX0BYTE_EP6_LEN) - 1) << USB_TX0BYTE_EP6_POS)) -#define USB_TX0BYTE_EP7 USB_TX0BYTE_EP7 -#define USB_TX0BYTE_EP7_POS (6U) -#define USB_TX0BYTE_EP7_LEN (1U) -#define USB_TX0BYTE_EP7_MSK (((1U << USB_TX0BYTE_EP7_LEN) - 1) << USB_TX0BYTE_EP7_POS) -#define USB_TX0BYTE_EP7_UMSK (~(((1U << USB_TX0BYTE_EP7_LEN) - 1) << USB_TX0BYTE_EP7_POS)) -#define USB_TX0BYTE_EP8 USB_TX0BYTE_EP8 -#define USB_TX0BYTE_EP8_POS (7U) -#define USB_TX0BYTE_EP8_LEN (1U) -#define USB_TX0BYTE_EP8_MSK (((1U << USB_TX0BYTE_EP8_LEN) - 1) << USB_TX0BYTE_EP8_POS) -#define USB_TX0BYTE_EP8_UMSK (~(((1U << USB_TX0BYTE_EP8_LEN) - 1) << USB_TX0BYTE_EP8_POS)) - -/* 0x158 : DEV_ISE */ -#define USB_DEV_ISE_OFFSET (0x158) -#define USB_ISO_ABT_ERR_EP1 USB_ISO_ABT_ERR_EP1 -#define USB_ISO_ABT_ERR_EP1_POS (0U) -#define USB_ISO_ABT_ERR_EP1_LEN (1U) -#define USB_ISO_ABT_ERR_EP1_MSK (((1U << USB_ISO_ABT_ERR_EP1_LEN) - 1) << USB_ISO_ABT_ERR_EP1_POS) -#define USB_ISO_ABT_ERR_EP1_UMSK (~(((1U << USB_ISO_ABT_ERR_EP1_LEN) - 1) << USB_ISO_ABT_ERR_EP1_POS)) -#define USB_ISO_ABT_ERR_EP2 USB_ISO_ABT_ERR_EP2 -#define USB_ISO_ABT_ERR_EP2_POS (1U) -#define USB_ISO_ABT_ERR_EP2_LEN (1U) -#define USB_ISO_ABT_ERR_EP2_MSK (((1U << USB_ISO_ABT_ERR_EP2_LEN) - 1) << USB_ISO_ABT_ERR_EP2_POS) -#define USB_ISO_ABT_ERR_EP2_UMSK (~(((1U << USB_ISO_ABT_ERR_EP2_LEN) - 1) << USB_ISO_ABT_ERR_EP2_POS)) -#define USB_ISO_ABT_ERR_EP3 USB_ISO_ABT_ERR_EP3 -#define USB_ISO_ABT_ERR_EP3_POS (2U) -#define USB_ISO_ABT_ERR_EP3_LEN (1U) -#define USB_ISO_ABT_ERR_EP3_MSK (((1U << USB_ISO_ABT_ERR_EP3_LEN) - 1) << USB_ISO_ABT_ERR_EP3_POS) -#define USB_ISO_ABT_ERR_EP3_UMSK (~(((1U << USB_ISO_ABT_ERR_EP3_LEN) - 1) << USB_ISO_ABT_ERR_EP3_POS)) -#define USB_ISO_ABT_ERR_EP4 USB_ISO_ABT_ERR_EP4 -#define USB_ISO_ABT_ERR_EP4_POS (3U) -#define USB_ISO_ABT_ERR_EP4_LEN (1U) -#define USB_ISO_ABT_ERR_EP4_MSK (((1U << USB_ISO_ABT_ERR_EP4_LEN) - 1) << USB_ISO_ABT_ERR_EP4_POS) -#define USB_ISO_ABT_ERR_EP4_UMSK (~(((1U << USB_ISO_ABT_ERR_EP4_LEN) - 1) << USB_ISO_ABT_ERR_EP4_POS)) -#define USB_ISO_ABT_ERR_EP5 USB_ISO_ABT_ERR_EP5 -#define USB_ISO_ABT_ERR_EP5_POS (4U) -#define USB_ISO_ABT_ERR_EP5_LEN (1U) -#define USB_ISO_ABT_ERR_EP5_MSK (((1U << USB_ISO_ABT_ERR_EP5_LEN) - 1) << USB_ISO_ABT_ERR_EP5_POS) -#define USB_ISO_ABT_ERR_EP5_UMSK (~(((1U << USB_ISO_ABT_ERR_EP5_LEN) - 1) << USB_ISO_ABT_ERR_EP5_POS)) -#define USB_ISO_ABT_ERR_EP6 USB_ISO_ABT_ERR_EP6 -#define USB_ISO_ABT_ERR_EP6_POS (5U) -#define USB_ISO_ABT_ERR_EP6_LEN (1U) -#define USB_ISO_ABT_ERR_EP6_MSK (((1U << USB_ISO_ABT_ERR_EP6_LEN) - 1) << USB_ISO_ABT_ERR_EP6_POS) -#define USB_ISO_ABT_ERR_EP6_UMSK (~(((1U << USB_ISO_ABT_ERR_EP6_LEN) - 1) << USB_ISO_ABT_ERR_EP6_POS)) -#define USB_ISO_ABT_ERR_EP7 USB_ISO_ABT_ERR_EP7 -#define USB_ISO_ABT_ERR_EP7_POS (6U) -#define USB_ISO_ABT_ERR_EP7_LEN (1U) -#define USB_ISO_ABT_ERR_EP7_MSK (((1U << USB_ISO_ABT_ERR_EP7_LEN) - 1) << USB_ISO_ABT_ERR_EP7_POS) -#define USB_ISO_ABT_ERR_EP7_UMSK (~(((1U << USB_ISO_ABT_ERR_EP7_LEN) - 1) << USB_ISO_ABT_ERR_EP7_POS)) -#define USB_ISO_ABT_ERR_EP8 USB_ISO_ABT_ERR_EP8 -#define USB_ISO_ABT_ERR_EP8_POS (7U) -#define USB_ISO_ABT_ERR_EP8_LEN (1U) -#define USB_ISO_ABT_ERR_EP8_MSK (((1U << USB_ISO_ABT_ERR_EP8_LEN) - 1) << USB_ISO_ABT_ERR_EP8_POS) -#define USB_ISO_ABT_ERR_EP8_UMSK (~(((1U << USB_ISO_ABT_ERR_EP8_LEN) - 1) << USB_ISO_ABT_ERR_EP8_POS)) -#define USB_ISO_SEQ_ERR_EP1 USB_ISO_SEQ_ERR_EP1 -#define USB_ISO_SEQ_ERR_EP1_POS (16U) -#define USB_ISO_SEQ_ERR_EP1_LEN (1U) -#define USB_ISO_SEQ_ERR_EP1_MSK (((1U << USB_ISO_SEQ_ERR_EP1_LEN) - 1) << USB_ISO_SEQ_ERR_EP1_POS) -#define USB_ISO_SEQ_ERR_EP1_UMSK (~(((1U << USB_ISO_SEQ_ERR_EP1_LEN) - 1) << USB_ISO_SEQ_ERR_EP1_POS)) -#define USB_ISO_SEQ_ERR_EP2 USB_ISO_SEQ_ERR_EP2 -#define USB_ISO_SEQ_ERR_EP2_POS (17U) -#define USB_ISO_SEQ_ERR_EP2_LEN (1U) -#define USB_ISO_SEQ_ERR_EP2_MSK (((1U << USB_ISO_SEQ_ERR_EP2_LEN) - 1) << USB_ISO_SEQ_ERR_EP2_POS) -#define USB_ISO_SEQ_ERR_EP2_UMSK (~(((1U << USB_ISO_SEQ_ERR_EP2_LEN) - 1) << USB_ISO_SEQ_ERR_EP2_POS)) -#define USB_ISO_SEQ_ERR_EP3 USB_ISO_SEQ_ERR_EP3 -#define USB_ISO_SEQ_ERR_EP3_POS (18U) -#define USB_ISO_SEQ_ERR_EP3_LEN (1U) -#define USB_ISO_SEQ_ERR_EP3_MSK (((1U << USB_ISO_SEQ_ERR_EP3_LEN) - 1) << USB_ISO_SEQ_ERR_EP3_POS) -#define USB_ISO_SEQ_ERR_EP3_UMSK (~(((1U << USB_ISO_SEQ_ERR_EP3_LEN) - 1) << USB_ISO_SEQ_ERR_EP3_POS)) -#define USB_ISO_SEQ_ERR_EP4 USB_ISO_SEQ_ERR_EP4 -#define USB_ISO_SEQ_ERR_EP4_POS (19U) -#define USB_ISO_SEQ_ERR_EP4_LEN (1U) -#define USB_ISO_SEQ_ERR_EP4_MSK (((1U << USB_ISO_SEQ_ERR_EP4_LEN) - 1) << USB_ISO_SEQ_ERR_EP4_POS) -#define USB_ISO_SEQ_ERR_EP4_UMSK (~(((1U << USB_ISO_SEQ_ERR_EP4_LEN) - 1) << USB_ISO_SEQ_ERR_EP4_POS)) -#define USB_ISO_SEQ_ERR_EP5 USB_ISO_SEQ_ERR_EP5 -#define USB_ISO_SEQ_ERR_EP5_POS (20U) -#define USB_ISO_SEQ_ERR_EP5_LEN (1U) -#define USB_ISO_SEQ_ERR_EP5_MSK (((1U << USB_ISO_SEQ_ERR_EP5_LEN) - 1) << USB_ISO_SEQ_ERR_EP5_POS) -#define USB_ISO_SEQ_ERR_EP5_UMSK (~(((1U << USB_ISO_SEQ_ERR_EP5_LEN) - 1) << USB_ISO_SEQ_ERR_EP5_POS)) -#define USB_ISO_SEQ_ERR_EP6 USB_ISO_SEQ_ERR_EP6 -#define USB_ISO_SEQ_ERR_EP6_POS (21U) -#define USB_ISO_SEQ_ERR_EP6_LEN (1U) -#define USB_ISO_SEQ_ERR_EP6_MSK (((1U << USB_ISO_SEQ_ERR_EP6_LEN) - 1) << USB_ISO_SEQ_ERR_EP6_POS) -#define USB_ISO_SEQ_ERR_EP6_UMSK (~(((1U << USB_ISO_SEQ_ERR_EP6_LEN) - 1) << USB_ISO_SEQ_ERR_EP6_POS)) -#define USB_ISO_SEQ_ERR_EP7 USB_ISO_SEQ_ERR_EP7 -#define USB_ISO_SEQ_ERR_EP7_POS (22U) -#define USB_ISO_SEQ_ERR_EP7_LEN (1U) -#define USB_ISO_SEQ_ERR_EP7_MSK (((1U << USB_ISO_SEQ_ERR_EP7_LEN) - 1) << USB_ISO_SEQ_ERR_EP7_POS) -#define USB_ISO_SEQ_ERR_EP7_UMSK (~(((1U << USB_ISO_SEQ_ERR_EP7_LEN) - 1) << USB_ISO_SEQ_ERR_EP7_POS)) -#define USB_ISO_SEQ_ERR_EP8 USB_ISO_SEQ_ERR_EP8 -#define USB_ISO_SEQ_ERR_EP8_POS (23U) -#define USB_ISO_SEQ_ERR_EP8_LEN (1U) -#define USB_ISO_SEQ_ERR_EP8_MSK (((1U << USB_ISO_SEQ_ERR_EP8_LEN) - 1) << USB_ISO_SEQ_ERR_EP8_POS) -#define USB_ISO_SEQ_ERR_EP8_UMSK (~(((1U << USB_ISO_SEQ_ERR_EP8_LEN) - 1) << USB_ISO_SEQ_ERR_EP8_POS)) - -/* 0x160 : DEV_INMPS1 */ -#define USB_DEV_INMPS1_OFFSET (0x160) -#define USB_MAXPS_IEP1 USB_MAXPS_IEP1 -#define USB_MAXPS_IEP1_POS (0U) -#define USB_MAXPS_IEP1_LEN (11U) -#define USB_MAXPS_IEP1_MSK (((1U << USB_MAXPS_IEP1_LEN) - 1) << USB_MAXPS_IEP1_POS) -#define USB_MAXPS_IEP1_UMSK (~(((1U << USB_MAXPS_IEP1_LEN) - 1) << USB_MAXPS_IEP1_POS)) -#define USB_STL_IEP1 USB_STL_IEP1 -#define USB_STL_IEP1_POS (11U) -#define USB_STL_IEP1_LEN (1U) -#define USB_STL_IEP1_MSK (((1U << USB_STL_IEP1_LEN) - 1) << USB_STL_IEP1_POS) -#define USB_STL_IEP1_UMSK (~(((1U << USB_STL_IEP1_LEN) - 1) << USB_STL_IEP1_POS)) -#define USB_RSTG_IEP1 USB_RSTG_IEP1 -#define USB_RSTG_IEP1_POS (12U) -#define USB_RSTG_IEP1_LEN (1U) -#define USB_RSTG_IEP1_MSK (((1U << USB_RSTG_IEP1_LEN) - 1) << USB_RSTG_IEP1_POS) -#define USB_RSTG_IEP1_UMSK (~(((1U << USB_RSTG_IEP1_LEN) - 1) << USB_RSTG_IEP1_POS)) -#define USB_TX_NUM_HBW_IEP1 USB_TX_NUM_HBW_IEP1 -#define USB_TX_NUM_HBW_IEP1_POS (13U) -#define USB_TX_NUM_HBW_IEP1_LEN (2U) -#define USB_TX_NUM_HBW_IEP1_MSK (((1U << USB_TX_NUM_HBW_IEP1_LEN) - 1) << USB_TX_NUM_HBW_IEP1_POS) -#define USB_TX_NUM_HBW_IEP1_UMSK (~(((1U << USB_TX_NUM_HBW_IEP1_LEN) - 1) << USB_TX_NUM_HBW_IEP1_POS)) -#define USB_TX0BYTE_IEP1 USB_TX0BYTE_IEP1 -#define USB_TX0BYTE_IEP1_POS (15U) -#define USB_TX0BYTE_IEP1_LEN (1U) -#define USB_TX0BYTE_IEP1_MSK (((1U << USB_TX0BYTE_IEP1_LEN) - 1) << USB_TX0BYTE_IEP1_POS) -#define USB_TX0BYTE_IEP1_UMSK (~(((1U << USB_TX0BYTE_IEP1_LEN) - 1) << USB_TX0BYTE_IEP1_POS)) - -/* 0x164 : DEV_INMPS2 */ -#define USB_DEV_INMPS2_OFFSET (0x164) -#define USB_MAXPS_IEP2 USB_MAXPS_IEP2 -#define USB_MAXPS_IEP2_POS (0U) -#define USB_MAXPS_IEP2_LEN (11U) -#define USB_MAXPS_IEP2_MSK (((1U << USB_MAXPS_IEP2_LEN) - 1) << USB_MAXPS_IEP2_POS) -#define USB_MAXPS_IEP2_UMSK (~(((1U << USB_MAXPS_IEP2_LEN) - 1) << USB_MAXPS_IEP2_POS)) -#define USB_STL_IEP2 USB_STL_IEP2 -#define USB_STL_IEP2_POS (11U) -#define USB_STL_IEP2_LEN (1U) -#define USB_STL_IEP2_MSK (((1U << USB_STL_IEP2_LEN) - 1) << USB_STL_IEP2_POS) -#define USB_STL_IEP2_UMSK (~(((1U << USB_STL_IEP2_LEN) - 1) << USB_STL_IEP2_POS)) -#define USB_RSTG_IEP2 USB_RSTG_IEP2 -#define USB_RSTG_IEP2_POS (12U) -#define USB_RSTG_IEP2_LEN (1U) -#define USB_RSTG_IEP2_MSK (((1U << USB_RSTG_IEP2_LEN) - 1) << USB_RSTG_IEP2_POS) -#define USB_RSTG_IEP2_UMSK (~(((1U << USB_RSTG_IEP2_LEN) - 1) << USB_RSTG_IEP2_POS)) -#define USB_TX_NUM_HBW_IEP2 USB_TX_NUM_HBW_IEP2 -#define USB_TX_NUM_HBW_IEP2_POS (13U) -#define USB_TX_NUM_HBW_IEP2_LEN (2U) -#define USB_TX_NUM_HBW_IEP2_MSK (((1U << USB_TX_NUM_HBW_IEP2_LEN) - 1) << USB_TX_NUM_HBW_IEP2_POS) -#define USB_TX_NUM_HBW_IEP2_UMSK (~(((1U << USB_TX_NUM_HBW_IEP2_LEN) - 1) << USB_TX_NUM_HBW_IEP2_POS)) -#define USB_TX0BYTE_IEP2 USB_TX0BYTE_IEP2 -#define USB_TX0BYTE_IEP2_POS (15U) -#define USB_TX0BYTE_IEP2_LEN (1U) -#define USB_TX0BYTE_IEP2_MSK (((1U << USB_TX0BYTE_IEP2_LEN) - 1) << USB_TX0BYTE_IEP2_POS) -#define USB_TX0BYTE_IEP2_UMSK (~(((1U << USB_TX0BYTE_IEP2_LEN) - 1) << USB_TX0BYTE_IEP2_POS)) - -/* 0x168 : DEV_INMPS3 */ -#define USB_DEV_INMPS3_OFFSET (0x168) -#define USB_MAXPS_IEP3 USB_MAXPS_IEP3 -#define USB_MAXPS_IEP3_POS (0U) -#define USB_MAXPS_IEP3_LEN (11U) -#define USB_MAXPS_IEP3_MSK (((1U << USB_MAXPS_IEP3_LEN) - 1) << USB_MAXPS_IEP3_POS) -#define USB_MAXPS_IEP3_UMSK (~(((1U << USB_MAXPS_IEP3_LEN) - 1) << USB_MAXPS_IEP3_POS)) -#define USB_STL_IEP3 USB_STL_IEP3 -#define USB_STL_IEP3_POS (11U) -#define USB_STL_IEP3_LEN (1U) -#define USB_STL_IEP3_MSK (((1U << USB_STL_IEP3_LEN) - 1) << USB_STL_IEP3_POS) -#define USB_STL_IEP3_UMSK (~(((1U << USB_STL_IEP3_LEN) - 1) << USB_STL_IEP3_POS)) -#define USB_RSTG_IEP3 USB_RSTG_IEP3 -#define USB_RSTG_IEP3_POS (12U) -#define USB_RSTG_IEP3_LEN (1U) -#define USB_RSTG_IEP3_MSK (((1U << USB_RSTG_IEP3_LEN) - 1) << USB_RSTG_IEP3_POS) -#define USB_RSTG_IEP3_UMSK (~(((1U << USB_RSTG_IEP3_LEN) - 1) << USB_RSTG_IEP3_POS)) -#define USB_TX_NUM_HBW_IEP3 USB_TX_NUM_HBW_IEP3 -#define USB_TX_NUM_HBW_IEP3_POS (13U) -#define USB_TX_NUM_HBW_IEP3_LEN (2U) -#define USB_TX_NUM_HBW_IEP3_MSK (((1U << USB_TX_NUM_HBW_IEP3_LEN) - 1) << USB_TX_NUM_HBW_IEP3_POS) -#define USB_TX_NUM_HBW_IEP3_UMSK (~(((1U << USB_TX_NUM_HBW_IEP3_LEN) - 1) << USB_TX_NUM_HBW_IEP3_POS)) -#define USB_TX0BYTE_IEP3 USB_TX0BYTE_IEP3 -#define USB_TX0BYTE_IEP3_POS (15U) -#define USB_TX0BYTE_IEP3_LEN (1U) -#define USB_TX0BYTE_IEP3_MSK (((1U << USB_TX0BYTE_IEP3_LEN) - 1) << USB_TX0BYTE_IEP3_POS) -#define USB_TX0BYTE_IEP3_UMSK (~(((1U << USB_TX0BYTE_IEP3_LEN) - 1) << USB_TX0BYTE_IEP3_POS)) - -/* 0x16C : DEV_INMPS4 */ -#define USB_DEV_INMPS4_OFFSET (0x16C) -#define USB_MAXPS_IEP4 USB_MAXPS_IEP4 -#define USB_MAXPS_IEP4_POS (0U) -#define USB_MAXPS_IEP4_LEN (11U) -#define USB_MAXPS_IEP4_MSK (((1U << USB_MAXPS_IEP4_LEN) - 1) << USB_MAXPS_IEP4_POS) -#define USB_MAXPS_IEP4_UMSK (~(((1U << USB_MAXPS_IEP4_LEN) - 1) << USB_MAXPS_IEP4_POS)) -#define USB_STL_IEP4 USB_STL_IEP4 -#define USB_STL_IEP4_POS (11U) -#define USB_STL_IEP4_LEN (1U) -#define USB_STL_IEP4_MSK (((1U << USB_STL_IEP4_LEN) - 1) << USB_STL_IEP4_POS) -#define USB_STL_IEP4_UMSK (~(((1U << USB_STL_IEP4_LEN) - 1) << USB_STL_IEP4_POS)) -#define USB_RSTG_IEP4 USB_RSTG_IEP4 -#define USB_RSTG_IEP4_POS (12U) -#define USB_RSTG_IEP4_LEN (1U) -#define USB_RSTG_IEP4_MSK (((1U << USB_RSTG_IEP4_LEN) - 1) << USB_RSTG_IEP4_POS) -#define USB_RSTG_IEP4_UMSK (~(((1U << USB_RSTG_IEP4_LEN) - 1) << USB_RSTG_IEP4_POS)) -#define USB_TX_NUM_HBW_IEP4 USB_TX_NUM_HBW_IEP4 -#define USB_TX_NUM_HBW_IEP4_POS (13U) -#define USB_TX_NUM_HBW_IEP4_LEN (2U) -#define USB_TX_NUM_HBW_IEP4_MSK (((1U << USB_TX_NUM_HBW_IEP4_LEN) - 1) << USB_TX_NUM_HBW_IEP4_POS) -#define USB_TX_NUM_HBW_IEP4_UMSK (~(((1U << USB_TX_NUM_HBW_IEP4_LEN) - 1) << USB_TX_NUM_HBW_IEP4_POS)) -#define USB_TX0BYTE_IEP4 USB_TX0BYTE_IEP4 -#define USB_TX0BYTE_IEP4_POS (15U) -#define USB_TX0BYTE_IEP4_LEN (1U) -#define USB_TX0BYTE_IEP4_MSK (((1U << USB_TX0BYTE_IEP4_LEN) - 1) << USB_TX0BYTE_IEP4_POS) -#define USB_TX0BYTE_IEP4_UMSK (~(((1U << USB_TX0BYTE_IEP4_LEN) - 1) << USB_TX0BYTE_IEP4_POS)) - -/* 0x170 : DEV_INMPS5 */ -#define USB_DEV_INMPS5_OFFSET (0x170) -#define USB_MAXPS_IEP5 USB_MAXPS_IEP5 -#define USB_MAXPS_IEP5_POS (0U) -#define USB_MAXPS_IEP5_LEN (11U) -#define USB_MAXPS_IEP5_MSK (((1U << USB_MAXPS_IEP5_LEN) - 1) << USB_MAXPS_IEP5_POS) -#define USB_MAXPS_IEP5_UMSK (~(((1U << USB_MAXPS_IEP5_LEN) - 1) << USB_MAXPS_IEP5_POS)) -#define USB_STL_IEP5 USB_STL_IEP5 -#define USB_STL_IEP5_POS (11U) -#define USB_STL_IEP5_LEN (1U) -#define USB_STL_IEP5_MSK (((1U << USB_STL_IEP5_LEN) - 1) << USB_STL_IEP5_POS) -#define USB_STL_IEP5_UMSK (~(((1U << USB_STL_IEP5_LEN) - 1) << USB_STL_IEP5_POS)) -#define USB_RSTG_IEP5 USB_RSTG_IEP5 -#define USB_RSTG_IEP5_POS (12U) -#define USB_RSTG_IEP5_LEN (1U) -#define USB_RSTG_IEP5_MSK (((1U << USB_RSTG_IEP5_LEN) - 1) << USB_RSTG_IEP5_POS) -#define USB_RSTG_IEP5_UMSK (~(((1U << USB_RSTG_IEP5_LEN) - 1) << USB_RSTG_IEP5_POS)) -#define USB_TX_NUM_HBW_IEP5 USB_TX_NUM_HBW_IEP5 -#define USB_TX_NUM_HBW_IEP5_POS (13U) -#define USB_TX_NUM_HBW_IEP5_LEN (2U) -#define USB_TX_NUM_HBW_IEP5_MSK (((1U << USB_TX_NUM_HBW_IEP5_LEN) - 1) << USB_TX_NUM_HBW_IEP5_POS) -#define USB_TX_NUM_HBW_IEP5_UMSK (~(((1U << USB_TX_NUM_HBW_IEP5_LEN) - 1) << USB_TX_NUM_HBW_IEP5_POS)) -#define USB_TX0BYTE_IEP5 USB_TX0BYTE_IEP5 -#define USB_TX0BYTE_IEP5_POS (15U) -#define USB_TX0BYTE_IEP5_LEN (1U) -#define USB_TX0BYTE_IEP5_MSK (((1U << USB_TX0BYTE_IEP5_LEN) - 1) << USB_TX0BYTE_IEP5_POS) -#define USB_TX0BYTE_IEP5_UMSK (~(((1U << USB_TX0BYTE_IEP5_LEN) - 1) << USB_TX0BYTE_IEP5_POS)) - -/* 0x174 : DEV_INMPS6 */ -#define USB_DEV_INMPS6_OFFSET (0x174) -#define USB_MAXPS_IEP6 USB_MAXPS_IEP6 -#define USB_MAXPS_IEP6_POS (0U) -#define USB_MAXPS_IEP6_LEN (11U) -#define USB_MAXPS_IEP6_MSK (((1U << USB_MAXPS_IEP6_LEN) - 1) << USB_MAXPS_IEP6_POS) -#define USB_MAXPS_IEP6_UMSK (~(((1U << USB_MAXPS_IEP6_LEN) - 1) << USB_MAXPS_IEP6_POS)) -#define USB_STL_IEP6 USB_STL_IEP6 -#define USB_STL_IEP6_POS (11U) -#define USB_STL_IEP6_LEN (1U) -#define USB_STL_IEP6_MSK (((1U << USB_STL_IEP6_LEN) - 1) << USB_STL_IEP6_POS) -#define USB_STL_IEP6_UMSK (~(((1U << USB_STL_IEP6_LEN) - 1) << USB_STL_IEP6_POS)) -#define USB_RSTG_IEP6 USB_RSTG_IEP6 -#define USB_RSTG_IEP6_POS (12U) -#define USB_RSTG_IEP6_LEN (1U) -#define USB_RSTG_IEP6_MSK (((1U << USB_RSTG_IEP6_LEN) - 1) << USB_RSTG_IEP6_POS) -#define USB_RSTG_IEP6_UMSK (~(((1U << USB_RSTG_IEP6_LEN) - 1) << USB_RSTG_IEP6_POS)) -#define USB_TX_NUM_HBW_IEP6 USB_TX_NUM_HBW_IEP6 -#define USB_TX_NUM_HBW_IEP6_POS (13U) -#define USB_TX_NUM_HBW_IEP6_LEN (2U) -#define USB_TX_NUM_HBW_IEP6_MSK (((1U << USB_TX_NUM_HBW_IEP6_LEN) - 1) << USB_TX_NUM_HBW_IEP6_POS) -#define USB_TX_NUM_HBW_IEP6_UMSK (~(((1U << USB_TX_NUM_HBW_IEP6_LEN) - 1) << USB_TX_NUM_HBW_IEP6_POS)) -#define USB_TX0BYTE_IEP6 USB_TX0BYTE_IEP6 -#define USB_TX0BYTE_IEP6_POS (15U) -#define USB_TX0BYTE_IEP6_LEN (1U) -#define USB_TX0BYTE_IEP6_MSK (((1U << USB_TX0BYTE_IEP6_LEN) - 1) << USB_TX0BYTE_IEP6_POS) -#define USB_TX0BYTE_IEP6_UMSK (~(((1U << USB_TX0BYTE_IEP6_LEN) - 1) << USB_TX0BYTE_IEP6_POS)) - -/* 0x178 : DEV_INMPS7 */ -#define USB_DEV_INMPS7_OFFSET (0x178) -#define USB_MAXPS_IEP7 USB_MAXPS_IEP7 -#define USB_MAXPS_IEP7_POS (0U) -#define USB_MAXPS_IEP7_LEN (11U) -#define USB_MAXPS_IEP7_MSK (((1U << USB_MAXPS_IEP7_LEN) - 1) << USB_MAXPS_IEP7_POS) -#define USB_MAXPS_IEP7_UMSK (~(((1U << USB_MAXPS_IEP7_LEN) - 1) << USB_MAXPS_IEP7_POS)) -#define USB_STL_IEP7 USB_STL_IEP7 -#define USB_STL_IEP7_POS (11U) -#define USB_STL_IEP7_LEN (1U) -#define USB_STL_IEP7_MSK (((1U << USB_STL_IEP7_LEN) - 1) << USB_STL_IEP7_POS) -#define USB_STL_IEP7_UMSK (~(((1U << USB_STL_IEP7_LEN) - 1) << USB_STL_IEP7_POS)) -#define USB_RSTG_IEP7 USB_RSTG_IEP7 -#define USB_RSTG_IEP7_POS (12U) -#define USB_RSTG_IEP7_LEN (1U) -#define USB_RSTG_IEP7_MSK (((1U << USB_RSTG_IEP7_LEN) - 1) << USB_RSTG_IEP7_POS) -#define USB_RSTG_IEP7_UMSK (~(((1U << USB_RSTG_IEP7_LEN) - 1) << USB_RSTG_IEP7_POS)) -#define USB_TX_NUM_HBW_IEP7 USB_TX_NUM_HBW_IEP7 -#define USB_TX_NUM_HBW_IEP7_POS (13U) -#define USB_TX_NUM_HBW_IEP7_LEN (2U) -#define USB_TX_NUM_HBW_IEP7_MSK (((1U << USB_TX_NUM_HBW_IEP7_LEN) - 1) << USB_TX_NUM_HBW_IEP7_POS) -#define USB_TX_NUM_HBW_IEP7_UMSK (~(((1U << USB_TX_NUM_HBW_IEP7_LEN) - 1) << USB_TX_NUM_HBW_IEP7_POS)) -#define USB_TX0BYTE_IEP7 USB_TX0BYTE_IEP7 -#define USB_TX0BYTE_IEP7_POS (15U) -#define USB_TX0BYTE_IEP7_LEN (1U) -#define USB_TX0BYTE_IEP7_MSK (((1U << USB_TX0BYTE_IEP7_LEN) - 1) << USB_TX0BYTE_IEP7_POS) -#define USB_TX0BYTE_IEP7_UMSK (~(((1U << USB_TX0BYTE_IEP7_LEN) - 1) << USB_TX0BYTE_IEP7_POS)) - -/* 0x17C : DEV_INMPS8 */ -#define USB_DEV_INMPS8_OFFSET (0x17C) -#define USB_MAXPS_IEP8 USB_MAXPS_IEP8 -#define USB_MAXPS_IEP8_POS (0U) -#define USB_MAXPS_IEP8_LEN (11U) -#define USB_MAXPS_IEP8_MSK (((1U << USB_MAXPS_IEP8_LEN) - 1) << USB_MAXPS_IEP8_POS) -#define USB_MAXPS_IEP8_UMSK (~(((1U << USB_MAXPS_IEP8_LEN) - 1) << USB_MAXPS_IEP8_POS)) -#define USB_STL_IEP8 USB_STL_IEP8 -#define USB_STL_IEP8_POS (11U) -#define USB_STL_IEP8_LEN (1U) -#define USB_STL_IEP8_MSK (((1U << USB_STL_IEP8_LEN) - 1) << USB_STL_IEP8_POS) -#define USB_STL_IEP8_UMSK (~(((1U << USB_STL_IEP8_LEN) - 1) << USB_STL_IEP8_POS)) -#define USB_RSTG_IEP8 USB_RSTG_IEP8 -#define USB_RSTG_IEP8_POS (12U) -#define USB_RSTG_IEP8_LEN (1U) -#define USB_RSTG_IEP8_MSK (((1U << USB_RSTG_IEP8_LEN) - 1) << USB_RSTG_IEP8_POS) -#define USB_RSTG_IEP8_UMSK (~(((1U << USB_RSTG_IEP8_LEN) - 1) << USB_RSTG_IEP8_POS)) -#define USB_TX_NUM_HBW_IEP8 USB_TX_NUM_HBW_IEP8 -#define USB_TX_NUM_HBW_IEP8_POS (13U) -#define USB_TX_NUM_HBW_IEP8_LEN (2U) -#define USB_TX_NUM_HBW_IEP8_MSK (((1U << USB_TX_NUM_HBW_IEP8_LEN) - 1) << USB_TX_NUM_HBW_IEP8_POS) -#define USB_TX_NUM_HBW_IEP8_UMSK (~(((1U << USB_TX_NUM_HBW_IEP8_LEN) - 1) << USB_TX_NUM_HBW_IEP8_POS)) -#define USB_TX0BYTE_IEP8 USB_TX0BYTE_IEP8 -#define USB_TX0BYTE_IEP8_POS (15U) -#define USB_TX0BYTE_IEP8_LEN (1U) -#define USB_TX0BYTE_IEP8_MSK (((1U << USB_TX0BYTE_IEP8_LEN) - 1) << USB_TX0BYTE_IEP8_POS) -#define USB_TX0BYTE_IEP8_UMSK (~(((1U << USB_TX0BYTE_IEP8_LEN) - 1) << USB_TX0BYTE_IEP8_POS)) - -/* 0x180 : DEV_OUTMPS1 */ -#define USB_DEV_OUTMPS1_OFFSET (0x180) -#define USB_MAXPS_OEP1 USB_MAXPS_OEP1 -#define USB_MAXPS_OEP1_POS (0U) -#define USB_MAXPS_OEP1_LEN (11U) -#define USB_MAXPS_OEP1_MSK (((1U << USB_MAXPS_OEP1_LEN) - 1) << USB_MAXPS_OEP1_POS) -#define USB_MAXPS_OEP1_UMSK (~(((1U << USB_MAXPS_OEP1_LEN) - 1) << USB_MAXPS_OEP1_POS)) -#define USB_STL_OEP1 USB_STL_OEP1 -#define USB_STL_OEP1_POS (11U) -#define USB_STL_OEP1_LEN (1U) -#define USB_STL_OEP1_MSK (((1U << USB_STL_OEP1_LEN) - 1) << USB_STL_OEP1_POS) -#define USB_STL_OEP1_UMSK (~(((1U << USB_STL_OEP1_LEN) - 1) << USB_STL_OEP1_POS)) -#define USB_RSTG_OEP1 USB_RSTG_OEP1 -#define USB_RSTG_OEP1_POS (12U) -#define USB_RSTG_OEP1_LEN (1U) -#define USB_RSTG_OEP1_MSK (((1U << USB_RSTG_OEP1_LEN) - 1) << USB_RSTG_OEP1_POS) -#define USB_RSTG_OEP1_UMSK (~(((1U << USB_RSTG_OEP1_LEN) - 1) << USB_RSTG_OEP1_POS)) - -/* 0x184 : DEV_OUTMPS2 */ -#define USB_DEV_OUTMPS2_OFFSET (0x184) -#define USB_MAXPS_OEP2 USB_MAXPS_OEP2 -#define USB_MAXPS_OEP2_POS (0U) -#define USB_MAXPS_OEP2_LEN (11U) -#define USB_MAXPS_OEP2_MSK (((1U << USB_MAXPS_OEP2_LEN) - 1) << USB_MAXPS_OEP2_POS) -#define USB_MAXPS_OEP2_UMSK (~(((1U << USB_MAXPS_OEP2_LEN) - 1) << USB_MAXPS_OEP2_POS)) -#define USB_STL_OEP2 USB_STL_OEP2 -#define USB_STL_OEP2_POS (11U) -#define USB_STL_OEP2_LEN (1U) -#define USB_STL_OEP2_MSK (((1U << USB_STL_OEP2_LEN) - 1) << USB_STL_OEP2_POS) -#define USB_STL_OEP2_UMSK (~(((1U << USB_STL_OEP2_LEN) - 1) << USB_STL_OEP2_POS)) -#define USB_RSTG_OEP2 USB_RSTG_OEP2 -#define USB_RSTG_OEP2_POS (12U) -#define USB_RSTG_OEP2_LEN (1U) -#define USB_RSTG_OEP2_MSK (((1U << USB_RSTG_OEP2_LEN) - 1) << USB_RSTG_OEP2_POS) -#define USB_RSTG_OEP2_UMSK (~(((1U << USB_RSTG_OEP2_LEN) - 1) << USB_RSTG_OEP2_POS)) - -/* 0x188 : DEV_OUTMPS3 */ -#define USB_DEV_OUTMPS3_OFFSET (0x188) -#define USB_MAXPS_OEP3 USB_MAXPS_OEP3 -#define USB_MAXPS_OEP3_POS (0U) -#define USB_MAXPS_OEP3_LEN (11U) -#define USB_MAXPS_OEP3_MSK (((1U << USB_MAXPS_OEP3_LEN) - 1) << USB_MAXPS_OEP3_POS) -#define USB_MAXPS_OEP3_UMSK (~(((1U << USB_MAXPS_OEP3_LEN) - 1) << USB_MAXPS_OEP3_POS)) -#define USB_STL_OEP3 USB_STL_OEP3 -#define USB_STL_OEP3_POS (11U) -#define USB_STL_OEP3_LEN (1U) -#define USB_STL_OEP3_MSK (((1U << USB_STL_OEP3_LEN) - 1) << USB_STL_OEP3_POS) -#define USB_STL_OEP3_UMSK (~(((1U << USB_STL_OEP3_LEN) - 1) << USB_STL_OEP3_POS)) -#define USB_RSTG_OEP3 USB_RSTG_OEP3 -#define USB_RSTG_OEP3_POS (12U) -#define USB_RSTG_OEP3_LEN (1U) -#define USB_RSTG_OEP3_MSK (((1U << USB_RSTG_OEP3_LEN) - 1) << USB_RSTG_OEP3_POS) -#define USB_RSTG_OEP3_UMSK (~(((1U << USB_RSTG_OEP3_LEN) - 1) << USB_RSTG_OEP3_POS)) - -/* 0x18C : DEV_OUTMPS4 */ -#define USB_DEV_OUTMPS4_OFFSET (0x18C) -#define USB_MAXPS_OEP4 USB_MAXPS_OEP4 -#define USB_MAXPS_OEP4_POS (0U) -#define USB_MAXPS_OEP4_LEN (11U) -#define USB_MAXPS_OEP4_MSK (((1U << USB_MAXPS_OEP4_LEN) - 1) << USB_MAXPS_OEP4_POS) -#define USB_MAXPS_OEP4_UMSK (~(((1U << USB_MAXPS_OEP4_LEN) - 1) << USB_MAXPS_OEP4_POS)) -#define USB_STL_OEP4 USB_STL_OEP4 -#define USB_STL_OEP4_POS (11U) -#define USB_STL_OEP4_LEN (1U) -#define USB_STL_OEP4_MSK (((1U << USB_STL_OEP4_LEN) - 1) << USB_STL_OEP4_POS) -#define USB_STL_OEP4_UMSK (~(((1U << USB_STL_OEP4_LEN) - 1) << USB_STL_OEP4_POS)) -#define USB_RSTG_OEP4 USB_RSTG_OEP4 -#define USB_RSTG_OEP4_POS (12U) -#define USB_RSTG_OEP4_LEN (1U) -#define USB_RSTG_OEP4_MSK (((1U << USB_RSTG_OEP4_LEN) - 1) << USB_RSTG_OEP4_POS) -#define USB_RSTG_OEP4_UMSK (~(((1U << USB_RSTG_OEP4_LEN) - 1) << USB_RSTG_OEP4_POS)) - -/* 0x190 : DEV_OUTMPS5 */ -#define USB_DEV_OUTMPS5_OFFSET (0x190) -#define USB_MAXPS_OEP5 USB_MAXPS_OEP5 -#define USB_MAXPS_OEP5_POS (0U) -#define USB_MAXPS_OEP5_LEN (11U) -#define USB_MAXPS_OEP5_MSK (((1U << USB_MAXPS_OEP5_LEN) - 1) << USB_MAXPS_OEP5_POS) -#define USB_MAXPS_OEP5_UMSK (~(((1U << USB_MAXPS_OEP5_LEN) - 1) << USB_MAXPS_OEP5_POS)) -#define USB_STL_OEP5 USB_STL_OEP5 -#define USB_STL_OEP5_POS (11U) -#define USB_STL_OEP5_LEN (1U) -#define USB_STL_OEP5_MSK (((1U << USB_STL_OEP5_LEN) - 1) << USB_STL_OEP5_POS) -#define USB_STL_OEP5_UMSK (~(((1U << USB_STL_OEP5_LEN) - 1) << USB_STL_OEP5_POS)) -#define USB_RSTG_OEP5 USB_RSTG_OEP5 -#define USB_RSTG_OEP5_POS (12U) -#define USB_RSTG_OEP5_LEN (1U) -#define USB_RSTG_OEP5_MSK (((1U << USB_RSTG_OEP5_LEN) - 1) << USB_RSTG_OEP5_POS) -#define USB_RSTG_OEP5_UMSK (~(((1U << USB_RSTG_OEP5_LEN) - 1) << USB_RSTG_OEP5_POS)) - -/* 0x194 : DEV_OUTMPS6 */ -#define USB_DEV_OUTMPS6_OFFSET (0x194) -#define USB_MAXPS_OEP6 USB_MAXPS_OEP6 -#define USB_MAXPS_OEP6_POS (0U) -#define USB_MAXPS_OEP6_LEN (11U) -#define USB_MAXPS_OEP6_MSK (((1U << USB_MAXPS_OEP6_LEN) - 1) << USB_MAXPS_OEP6_POS) -#define USB_MAXPS_OEP6_UMSK (~(((1U << USB_MAXPS_OEP6_LEN) - 1) << USB_MAXPS_OEP6_POS)) -#define USB_STL_OEP6 USB_STL_OEP6 -#define USB_STL_OEP6_POS (11U) -#define USB_STL_OEP6_LEN (1U) -#define USB_STL_OEP6_MSK (((1U << USB_STL_OEP6_LEN) - 1) << USB_STL_OEP6_POS) -#define USB_STL_OEP6_UMSK (~(((1U << USB_STL_OEP6_LEN) - 1) << USB_STL_OEP6_POS)) -#define USB_RSTG_OEP6 USB_RSTG_OEP6 -#define USB_RSTG_OEP6_POS (12U) -#define USB_RSTG_OEP6_LEN (1U) -#define USB_RSTG_OEP6_MSK (((1U << USB_RSTG_OEP6_LEN) - 1) << USB_RSTG_OEP6_POS) -#define USB_RSTG_OEP6_UMSK (~(((1U << USB_RSTG_OEP6_LEN) - 1) << USB_RSTG_OEP6_POS)) - -/* 0x198 : DEV_OUTMPS7 */ -#define USB_DEV_OUTMPS7_OFFSET (0x198) -#define USB_MAXPS_OEP7 USB_MAXPS_OEP7 -#define USB_MAXPS_OEP7_POS (0U) -#define USB_MAXPS_OEP7_LEN (11U) -#define USB_MAXPS_OEP7_MSK (((1U << USB_MAXPS_OEP7_LEN) - 1) << USB_MAXPS_OEP7_POS) -#define USB_MAXPS_OEP7_UMSK (~(((1U << USB_MAXPS_OEP7_LEN) - 1) << USB_MAXPS_OEP7_POS)) -#define USB_STL_OEP7 USB_STL_OEP7 -#define USB_STL_OEP7_POS (11U) -#define USB_STL_OEP7_LEN (1U) -#define USB_STL_OEP7_MSK (((1U << USB_STL_OEP7_LEN) - 1) << USB_STL_OEP7_POS) -#define USB_STL_OEP7_UMSK (~(((1U << USB_STL_OEP7_LEN) - 1) << USB_STL_OEP7_POS)) -#define USB_RSTG_OEP7 USB_RSTG_OEP7 -#define USB_RSTG_OEP7_POS (12U) -#define USB_RSTG_OEP7_LEN (1U) -#define USB_RSTG_OEP7_MSK (((1U << USB_RSTG_OEP7_LEN) - 1) << USB_RSTG_OEP7_POS) -#define USB_RSTG_OEP7_UMSK (~(((1U << USB_RSTG_OEP7_LEN) - 1) << USB_RSTG_OEP7_POS)) - -/* 0x19C : DEV_OUTMPS8 */ -#define USB_DEV_OUTMPS8_OFFSET (0x19C) -#define USB_MAXPS_OEP8 USB_MAXPS_OEP8 -#define USB_MAXPS_OEP8_POS (0U) -#define USB_MAXPS_OEP8_LEN (11U) -#define USB_MAXPS_OEP8_MSK (((1U << USB_MAXPS_OEP8_LEN) - 1) << USB_MAXPS_OEP8_POS) -#define USB_MAXPS_OEP8_UMSK (~(((1U << USB_MAXPS_OEP8_LEN) - 1) << USB_MAXPS_OEP8_POS)) -#define USB_STL_OEP8 USB_STL_OEP8 -#define USB_STL_OEP8_POS (11U) -#define USB_STL_OEP8_LEN (1U) -#define USB_STL_OEP8_MSK (((1U << USB_STL_OEP8_LEN) - 1) << USB_STL_OEP8_POS) -#define USB_STL_OEP8_UMSK (~(((1U << USB_STL_OEP8_LEN) - 1) << USB_STL_OEP8_POS)) -#define USB_RSTG_OEP8 USB_RSTG_OEP8 -#define USB_RSTG_OEP8_POS (12U) -#define USB_RSTG_OEP8_LEN (1U) -#define USB_RSTG_OEP8_MSK (((1U << USB_RSTG_OEP8_LEN) - 1) << USB_RSTG_OEP8_POS) -#define USB_RSTG_OEP8_UMSK (~(((1U << USB_RSTG_OEP8_LEN) - 1) << USB_RSTG_OEP8_POS)) - -/* 0x1A0 : DEV_EPMAP0 */ -#define USB_DEV_EPMAP0_OFFSET (0x1A0) -#define USB_FNO_IEP1 USB_FNO_IEP1 -#define USB_FNO_IEP1_POS (0U) -#define USB_FNO_IEP1_LEN (4U) -#define USB_FNO_IEP1_MSK (((1U << USB_FNO_IEP1_LEN) - 1) << USB_FNO_IEP1_POS) -#define USB_FNO_IEP1_UMSK (~(((1U << USB_FNO_IEP1_LEN) - 1) << USB_FNO_IEP1_POS)) -#define USB_FNO_OEP1 USB_FNO_OEP1 -#define USB_FNO_OEP1_POS (4U) -#define USB_FNO_OEP1_LEN (4U) -#define USB_FNO_OEP1_MSK (((1U << USB_FNO_OEP1_LEN) - 1) << USB_FNO_OEP1_POS) -#define USB_FNO_OEP1_UMSK (~(((1U << USB_FNO_OEP1_LEN) - 1) << USB_FNO_OEP1_POS)) -#define USB_FNO_IEP2 USB_FNO_IEP2 -#define USB_FNO_IEP2_POS (8U) -#define USB_FNO_IEP2_LEN (4U) -#define USB_FNO_IEP2_MSK (((1U << USB_FNO_IEP2_LEN) - 1) << USB_FNO_IEP2_POS) -#define USB_FNO_IEP2_UMSK (~(((1U << USB_FNO_IEP2_LEN) - 1) << USB_FNO_IEP2_POS)) -#define USB_FNO_OEP2 USB_FNO_OEP2 -#define USB_FNO_OEP2_POS (12U) -#define USB_FNO_OEP2_LEN (4U) -#define USB_FNO_OEP2_MSK (((1U << USB_FNO_OEP2_LEN) - 1) << USB_FNO_OEP2_POS) -#define USB_FNO_OEP2_UMSK (~(((1U << USB_FNO_OEP2_LEN) - 1) << USB_FNO_OEP2_POS)) -#define USB_FNO_IEP3 USB_FNO_IEP3 -#define USB_FNO_IEP3_POS (16U) -#define USB_FNO_IEP3_LEN (4U) -#define USB_FNO_IEP3_MSK (((1U << USB_FNO_IEP3_LEN) - 1) << USB_FNO_IEP3_POS) -#define USB_FNO_IEP3_UMSK (~(((1U << USB_FNO_IEP3_LEN) - 1) << USB_FNO_IEP3_POS)) -#define USB_FNO_OEP3 USB_FNO_OEP3 -#define USB_FNO_OEP3_POS (20U) -#define USB_FNO_OEP3_LEN (4U) -#define USB_FNO_OEP3_MSK (((1U << USB_FNO_OEP3_LEN) - 1) << USB_FNO_OEP3_POS) -#define USB_FNO_OEP3_UMSK (~(((1U << USB_FNO_OEP3_LEN) - 1) << USB_FNO_OEP3_POS)) -#define USB_FNO_IEP4 USB_FNO_IEP4 -#define USB_FNO_IEP4_POS (24U) -#define USB_FNO_IEP4_LEN (4U) -#define USB_FNO_IEP4_MSK (((1U << USB_FNO_IEP4_LEN) - 1) << USB_FNO_IEP4_POS) -#define USB_FNO_IEP4_UMSK (~(((1U << USB_FNO_IEP4_LEN) - 1) << USB_FNO_IEP4_POS)) -#define USB_FNO_OEP4 USB_FNO_OEP4 -#define USB_FNO_OEP4_POS (28U) -#define USB_FNO_OEP4_LEN (4U) -#define USB_FNO_OEP4_MSK (((1U << USB_FNO_OEP4_LEN) - 1) << USB_FNO_OEP4_POS) -#define USB_FNO_OEP4_UMSK (~(((1U << USB_FNO_OEP4_LEN) - 1) << USB_FNO_OEP4_POS)) - -/* 0x1A4 : DEV_EPMAP1 */ -#define USB_DEV_EPMAP1_OFFSET (0x1A4) -#define USB_FNO_IEP5 USB_FNO_IEP5 -#define USB_FNO_IEP5_POS (0U) -#define USB_FNO_IEP5_LEN (4U) -#define USB_FNO_IEP5_MSK (((1U << USB_FNO_IEP5_LEN) - 1) << USB_FNO_IEP5_POS) -#define USB_FNO_IEP5_UMSK (~(((1U << USB_FNO_IEP5_LEN) - 1) << USB_FNO_IEP5_POS)) -#define USB_FNO_OEP5 USB_FNO_OEP5 -#define USB_FNO_OEP5_POS (4U) -#define USB_FNO_OEP5_LEN (4U) -#define USB_FNO_OEP5_MSK (((1U << USB_FNO_OEP5_LEN) - 1) << USB_FNO_OEP5_POS) -#define USB_FNO_OEP5_UMSK (~(((1U << USB_FNO_OEP5_LEN) - 1) << USB_FNO_OEP5_POS)) -#define USB_FNO_IEP6 USB_FNO_IEP6 -#define USB_FNO_IEP6_POS (8U) -#define USB_FNO_IEP6_LEN (4U) -#define USB_FNO_IEP6_MSK (((1U << USB_FNO_IEP6_LEN) - 1) << USB_FNO_IEP6_POS) -#define USB_FNO_IEP6_UMSK (~(((1U << USB_FNO_IEP6_LEN) - 1) << USB_FNO_IEP6_POS)) -#define USB_FNO_OEP6 USB_FNO_OEP6 -#define USB_FNO_OEP6_POS (12U) -#define USB_FNO_OEP6_LEN (4U) -#define USB_FNO_OEP6_MSK (((1U << USB_FNO_OEP6_LEN) - 1) << USB_FNO_OEP6_POS) -#define USB_FNO_OEP6_UMSK (~(((1U << USB_FNO_OEP6_LEN) - 1) << USB_FNO_OEP6_POS)) -#define USB_FNO_IEP7 USB_FNO_IEP7 -#define USB_FNO_IEP7_POS (16U) -#define USB_FNO_IEP7_LEN (4U) -#define USB_FNO_IEP7_MSK (((1U << USB_FNO_IEP7_LEN) - 1) << USB_FNO_IEP7_POS) -#define USB_FNO_IEP7_UMSK (~(((1U << USB_FNO_IEP7_LEN) - 1) << USB_FNO_IEP7_POS)) -#define USB_FNO_OEP7 USB_FNO_OEP7 -#define USB_FNO_OEP7_POS (20U) -#define USB_FNO_OEP7_LEN (4U) -#define USB_FNO_OEP7_MSK (((1U << USB_FNO_OEP7_LEN) - 1) << USB_FNO_OEP7_POS) -#define USB_FNO_OEP7_UMSK (~(((1U << USB_FNO_OEP7_LEN) - 1) << USB_FNO_OEP7_POS)) -#define USB_FNO_IEP8 USB_FNO_IEP8 -#define USB_FNO_IEP8_POS (24U) -#define USB_FNO_IEP8_LEN (4U) -#define USB_FNO_IEP8_MSK (((1U << USB_FNO_IEP8_LEN) - 1) << USB_FNO_IEP8_POS) -#define USB_FNO_IEP8_UMSK (~(((1U << USB_FNO_IEP8_LEN) - 1) << USB_FNO_IEP8_POS)) -#define USB_FNO_OEP8 USB_FNO_OEP8 -#define USB_FNO_OEP8_POS (28U) -#define USB_FNO_OEP8_LEN (4U) -#define USB_FNO_OEP8_MSK (((1U << USB_FNO_OEP8_LEN) - 1) << USB_FNO_OEP8_POS) -#define USB_FNO_OEP8_UMSK (~(((1U << USB_FNO_OEP8_LEN) - 1) << USB_FNO_OEP8_POS)) - -/* 0x1A8 : DEV_FMAP */ -#define USB_DEV_FMAP_OFFSET (0x1A8) -#define USB_EPNO_FIFO0 USB_EPNO_FIFO0 -#define USB_EPNO_FIFO0_POS (0U) -#define USB_EPNO_FIFO0_LEN (4U) -#define USB_EPNO_FIFO0_MSK (((1U << USB_EPNO_FIFO0_LEN) - 1) << USB_EPNO_FIFO0_POS) -#define USB_EPNO_FIFO0_UMSK (~(((1U << USB_EPNO_FIFO0_LEN) - 1) << USB_EPNO_FIFO0_POS)) -#define USB_DIR_FIFO0 USB_DIR_FIFO0 -#define USB_DIR_FIFO0_POS (4U) -#define USB_DIR_FIFO0_LEN (2U) -#define USB_DIR_FIFO0_MSK (((1U << USB_DIR_FIFO0_LEN) - 1) << USB_DIR_FIFO0_POS) -#define USB_DIR_FIFO0_UMSK (~(((1U << USB_DIR_FIFO0_LEN) - 1) << USB_DIR_FIFO0_POS)) -#define USB_EPNO_FIFO1 USB_EPNO_FIFO1 -#define USB_EPNO_FIFO1_POS (8U) -#define USB_EPNO_FIFO1_LEN (4U) -#define USB_EPNO_FIFO1_MSK (((1U << USB_EPNO_FIFO1_LEN) - 1) << USB_EPNO_FIFO1_POS) -#define USB_EPNO_FIFO1_UMSK (~(((1U << USB_EPNO_FIFO1_LEN) - 1) << USB_EPNO_FIFO1_POS)) -#define USB_DIR_FIFO1 USB_DIR_FIFO1 -#define USB_DIR_FIFO1_POS (12U) -#define USB_DIR_FIFO1_LEN (2U) -#define USB_DIR_FIFO1_MSK (((1U << USB_DIR_FIFO1_LEN) - 1) << USB_DIR_FIFO1_POS) -#define USB_DIR_FIFO1_UMSK (~(((1U << USB_DIR_FIFO1_LEN) - 1) << USB_DIR_FIFO1_POS)) -#define USB_EPNO_FIFO2 USB_EPNO_FIFO2 -#define USB_EPNO_FIFO2_POS (16U) -#define USB_EPNO_FIFO2_LEN (4U) -#define USB_EPNO_FIFO2_MSK (((1U << USB_EPNO_FIFO2_LEN) - 1) << USB_EPNO_FIFO2_POS) -#define USB_EPNO_FIFO2_UMSK (~(((1U << USB_EPNO_FIFO2_LEN) - 1) << USB_EPNO_FIFO2_POS)) -#define USB_DIR_FIFO2 USB_DIR_FIFO2 -#define USB_DIR_FIFO2_POS (20U) -#define USB_DIR_FIFO2_LEN (2U) -#define USB_DIR_FIFO2_MSK (((1U << USB_DIR_FIFO2_LEN) - 1) << USB_DIR_FIFO2_POS) -#define USB_DIR_FIFO2_UMSK (~(((1U << USB_DIR_FIFO2_LEN) - 1) << USB_DIR_FIFO2_POS)) -#define USB_EPNO_FIFO3 USB_EPNO_FIFO3 -#define USB_EPNO_FIFO3_POS (24U) -#define USB_EPNO_FIFO3_LEN (4U) -#define USB_EPNO_FIFO3_MSK (((1U << USB_EPNO_FIFO3_LEN) - 1) << USB_EPNO_FIFO3_POS) -#define USB_EPNO_FIFO3_UMSK (~(((1U << USB_EPNO_FIFO3_LEN) - 1) << USB_EPNO_FIFO3_POS)) -#define USB_DIR_FIFO3 USB_DIR_FIFO3 -#define USB_DIR_FIFO3_POS (28U) -#define USB_DIR_FIFO3_LEN (2U) -#define USB_DIR_FIFO3_MSK (((1U << USB_DIR_FIFO3_LEN) - 1) << USB_DIR_FIFO3_POS) -#define USB_DIR_FIFO3_UMSK (~(((1U << USB_DIR_FIFO3_LEN) - 1) << USB_DIR_FIFO3_POS)) - -/* 0x1AC : DEV_FCFG */ -#define USB_DEV_FCFG_OFFSET (0x1AC) -#define USB_BLK_TYP_F0 USB_BLK_TYP_F0 -#define USB_BLK_TYP_F0_POS (0U) -#define USB_BLK_TYP_F0_LEN (2U) -#define USB_BLK_TYP_F0_MSK (((1U << USB_BLK_TYP_F0_LEN) - 1) << USB_BLK_TYP_F0_POS) -#define USB_BLK_TYP_F0_UMSK (~(((1U << USB_BLK_TYP_F0_LEN) - 1) << USB_BLK_TYP_F0_POS)) -#define USB_BLKNO_F0 USB_BLKNO_F0 -#define USB_BLKNO_F0_POS (2U) -#define USB_BLKNO_F0_LEN (2U) -#define USB_BLKNO_F0_MSK (((1U << USB_BLKNO_F0_LEN) - 1) << USB_BLKNO_F0_POS) -#define USB_BLKNO_F0_UMSK (~(((1U << USB_BLKNO_F0_LEN) - 1) << USB_BLKNO_F0_POS)) -#define USB_BLKSZ_F0 USB_BLKSZ_F0 -#define USB_BLKSZ_F0_POS (4U) -#define USB_BLKSZ_F0_LEN (1U) -#define USB_BLKSZ_F0_MSK (((1U << USB_BLKSZ_F0_LEN) - 1) << USB_BLKSZ_F0_POS) -#define USB_BLKSZ_F0_UMSK (~(((1U << USB_BLKSZ_F0_LEN) - 1) << USB_BLKSZ_F0_POS)) -#define USB_EN_F0 USB_EN_F0 -#define USB_EN_F0_POS (5U) -#define USB_EN_F0_LEN (1U) -#define USB_EN_F0_MSK (((1U << USB_EN_F0_LEN) - 1) << USB_EN_F0_POS) -#define USB_EN_F0_UMSK (~(((1U << USB_EN_F0_LEN) - 1) << USB_EN_F0_POS)) -#define USB_BLK_TYP_F1 USB_BLK_TYP_F1 -#define USB_BLK_TYP_F1_POS (8U) -#define USB_BLK_TYP_F1_LEN (2U) -#define USB_BLK_TYP_F1_MSK (((1U << USB_BLK_TYP_F1_LEN) - 1) << USB_BLK_TYP_F1_POS) -#define USB_BLK_TYP_F1_UMSK (~(((1U << USB_BLK_TYP_F1_LEN) - 1) << USB_BLK_TYP_F1_POS)) -#define USB_BLKNO_F1 USB_BLKNO_F1 -#define USB_BLKNO_F1_POS (10U) -#define USB_BLKNO_F1_LEN (2U) -#define USB_BLKNO_F1_MSK (((1U << USB_BLKNO_F1_LEN) - 1) << USB_BLKNO_F1_POS) -#define USB_BLKNO_F1_UMSK (~(((1U << USB_BLKNO_F1_LEN) - 1) << USB_BLKNO_F1_POS)) -#define USB_BLKSZ_F1 USB_BLKSZ_F1 -#define USB_BLKSZ_F1_POS (12U) -#define USB_BLKSZ_F1_LEN (1U) -#define USB_BLKSZ_F1_MSK (((1U << USB_BLKSZ_F1_LEN) - 1) << USB_BLKSZ_F1_POS) -#define USB_BLKSZ_F1_UMSK (~(((1U << USB_BLKSZ_F1_LEN) - 1) << USB_BLKSZ_F1_POS)) -#define USB_EN_F1 USB_EN_F1 -#define USB_EN_F1_POS (13U) -#define USB_EN_F1_LEN (1U) -#define USB_EN_F1_MSK (((1U << USB_EN_F1_LEN) - 1) << USB_EN_F1_POS) -#define USB_EN_F1_UMSK (~(((1U << USB_EN_F1_LEN) - 1) << USB_EN_F1_POS)) -#define USB_BLK_TYP_F2 USB_BLK_TYP_F2 -#define USB_BLK_TYP_F2_POS (16U) -#define USB_BLK_TYP_F2_LEN (2U) -#define USB_BLK_TYP_F2_MSK (((1U << USB_BLK_TYP_F2_LEN) - 1) << USB_BLK_TYP_F2_POS) -#define USB_BLK_TYP_F2_UMSK (~(((1U << USB_BLK_TYP_F2_LEN) - 1) << USB_BLK_TYP_F2_POS)) -#define USB_BLKNO_F2 USB_BLKNO_F2 -#define USB_BLKNO_F2_POS (18U) -#define USB_BLKNO_F2_LEN (2U) -#define USB_BLKNO_F2_MSK (((1U << USB_BLKNO_F2_LEN) - 1) << USB_BLKNO_F2_POS) -#define USB_BLKNO_F2_UMSK (~(((1U << USB_BLKNO_F2_LEN) - 1) << USB_BLKNO_F2_POS)) -#define USB_BLKSZ_F2 USB_BLKSZ_F2 -#define USB_BLKSZ_F2_POS (20U) -#define USB_BLKSZ_F2_LEN (1U) -#define USB_BLKSZ_F2_MSK (((1U << USB_BLKSZ_F2_LEN) - 1) << USB_BLKSZ_F2_POS) -#define USB_BLKSZ_F2_UMSK (~(((1U << USB_BLKSZ_F2_LEN) - 1) << USB_BLKSZ_F2_POS)) -#define USB_EN_F2 USB_EN_F2 -#define USB_EN_F2_POS (21U) -#define USB_EN_F2_LEN (1U) -#define USB_EN_F2_MSK (((1U << USB_EN_F2_LEN) - 1) << USB_EN_F2_POS) -#define USB_EN_F2_UMSK (~(((1U << USB_EN_F2_LEN) - 1) << USB_EN_F2_POS)) -#define USB_BLK_TYP_F3 USB_BLK_TYP_F3 -#define USB_BLK_TYP_F3_POS (24U) -#define USB_BLK_TYP_F3_LEN (2U) -#define USB_BLK_TYP_F3_MSK (((1U << USB_BLK_TYP_F3_LEN) - 1) << USB_BLK_TYP_F3_POS) -#define USB_BLK_TYP_F3_UMSK (~(((1U << USB_BLK_TYP_F3_LEN) - 1) << USB_BLK_TYP_F3_POS)) -#define USB_BLKNO_F3 USB_BLKNO_F3 -#define USB_BLKNO_F3_POS (26U) -#define USB_BLKNO_F3_LEN (2U) -#define USB_BLKNO_F3_MSK (((1U << USB_BLKNO_F3_LEN) - 1) << USB_BLKNO_F3_POS) -#define USB_BLKNO_F3_UMSK (~(((1U << USB_BLKNO_F3_LEN) - 1) << USB_BLKNO_F3_POS)) -#define USB_BLKSZ_F3 USB_BLKSZ_F3 -#define USB_BLKSZ_F3_POS (28U) -#define USB_BLKSZ_F3_LEN (1U) -#define USB_BLKSZ_F3_MSK (((1U << USB_BLKSZ_F3_LEN) - 1) << USB_BLKSZ_F3_POS) -#define USB_BLKSZ_F3_UMSK (~(((1U << USB_BLKSZ_F3_LEN) - 1) << USB_BLKSZ_F3_POS)) -#define USB_EN_F3 USB_EN_F3 -#define USB_EN_F3_POS (29U) -#define USB_EN_F3_LEN (1U) -#define USB_EN_F3_MSK (((1U << USB_EN_F3_LEN) - 1) << USB_EN_F3_POS) -#define USB_EN_F3_UMSK (~(((1U << USB_EN_F3_LEN) - 1) << USB_EN_F3_POS)) - -/* 0x1B0 : DEV_FIBC0 */ -#define USB_DEV_FIBC0_OFFSET (0x1B0) -#define USB_BC_F0 USB_BC_F0 -#define USB_BC_F0_POS (0U) -#define USB_BC_F0_LEN (11U) -#define USB_BC_F0_MSK (((1U << USB_BC_F0_LEN) - 1) << USB_BC_F0_POS) -#define USB_BC_F0_UMSK (~(((1U << USB_BC_F0_LEN) - 1) << USB_BC_F0_POS)) -#define USB_FFRST0_HOV USB_FFRST0_HOV -#define USB_FFRST0_HOV_POS (12U) -#define USB_FFRST0_HOV_LEN (1U) -#define USB_FFRST0_HOV_MSK (((1U << USB_FFRST0_HOV_LEN) - 1) << USB_FFRST0_HOV_POS) -#define USB_FFRST0_HOV_UMSK (~(((1U << USB_FFRST0_HOV_LEN) - 1) << USB_FFRST0_HOV_POS)) - -/* 0x1B4 : DEV_FIBC1 */ -#define USB_DEV_FIBC1_OFFSET (0x1B4) -#define USB_BC_F1 USB_BC_F1 -#define USB_BC_F1_POS (0U) -#define USB_BC_F1_LEN (11U) -#define USB_BC_F1_MSK (((1U << USB_BC_F1_LEN) - 1) << USB_BC_F1_POS) -#define USB_BC_F1_UMSK (~(((1U << USB_BC_F1_LEN) - 1) << USB_BC_F1_POS)) -#define USB_FFRST1_HOV USB_FFRST1_HOV -#define USB_FFRST1_HOV_POS (12U) -#define USB_FFRST1_HOV_LEN (1U) -#define USB_FFRST1_HOV_MSK (((1U << USB_FFRST1_HOV_LEN) - 1) << USB_FFRST1_HOV_POS) -#define USB_FFRST1_HOV_UMSK (~(((1U << USB_FFRST1_HOV_LEN) - 1) << USB_FFRST1_HOV_POS)) - -/* 0x1B8 : DEV_FIBC2 */ -#define USB_DEV_FIBC2_OFFSET (0x1B8) -#define USB_BC_F2 USB_BC_F2 -#define USB_BC_F2_POS (0U) -#define USB_BC_F2_LEN (11U) -#define USB_BC_F2_MSK (((1U << USB_BC_F2_LEN) - 1) << USB_BC_F2_POS) -#define USB_BC_F2_UMSK (~(((1U << USB_BC_F2_LEN) - 1) << USB_BC_F2_POS)) -#define USB_FFRST2_HOV USB_FFRST2_HOV -#define USB_FFRST2_HOV_POS (12U) -#define USB_FFRST2_HOV_LEN (1U) -#define USB_FFRST2_HOV_MSK (((1U << USB_FFRST2_HOV_LEN) - 1) << USB_FFRST2_HOV_POS) -#define USB_FFRST2_HOV_UMSK (~(((1U << USB_FFRST2_HOV_LEN) - 1) << USB_FFRST2_HOV_POS)) - -/* 0x1BC : DEV_FIBC3 */ -#define USB_DEV_FIBC3_OFFSET (0x1BC) -#define USB_BC_F3 USB_BC_F3 -#define USB_BC_F3_POS (0U) -#define USB_BC_F3_LEN (11U) -#define USB_BC_F3_MSK (((1U << USB_BC_F3_LEN) - 1) << USB_BC_F3_POS) -#define USB_BC_F3_UMSK (~(((1U << USB_BC_F3_LEN) - 1) << USB_BC_F3_POS)) -#define USB_FFRST3_HOV USB_FFRST3_HOV -#define USB_FFRST3_HOV_POS (12U) -#define USB_FFRST3_HOV_LEN (1U) -#define USB_FFRST3_HOV_MSK (((1U << USB_FFRST3_HOV_LEN) - 1) << USB_FFRST3_HOV_POS) -#define USB_FFRST3_HOV_UMSK (~(((1U << USB_FFRST3_HOV_LEN) - 1) << USB_FFRST3_HOV_POS)) - -/* 0x1C0 : DMA_TFN */ -#define USB_DMA_TFN_OFFSET (0x1C0) -#define USB_ACC_F0_HOV USB_ACC_F0_HOV -#define USB_ACC_F0_HOV_POS (0U) -#define USB_ACC_F0_HOV_LEN (1U) -#define USB_ACC_F0_HOV_MSK (((1U << USB_ACC_F0_HOV_LEN) - 1) << USB_ACC_F0_HOV_POS) -#define USB_ACC_F0_HOV_UMSK (~(((1U << USB_ACC_F0_HOV_LEN) - 1) << USB_ACC_F0_HOV_POS)) -#define USB_ACC_F1_HOV USB_ACC_F1_HOV -#define USB_ACC_F1_HOV_POS (1U) -#define USB_ACC_F1_HOV_LEN (1U) -#define USB_ACC_F1_HOV_MSK (((1U << USB_ACC_F1_HOV_LEN) - 1) << USB_ACC_F1_HOV_POS) -#define USB_ACC_F1_HOV_UMSK (~(((1U << USB_ACC_F1_HOV_LEN) - 1) << USB_ACC_F1_HOV_POS)) -#define USB_ACC_F2_HOV USB_ACC_F2_HOV -#define USB_ACC_F2_HOV_POS (2U) -#define USB_ACC_F2_HOV_LEN (1U) -#define USB_ACC_F2_HOV_MSK (((1U << USB_ACC_F2_HOV_LEN) - 1) << USB_ACC_F2_HOV_POS) -#define USB_ACC_F2_HOV_UMSK (~(((1U << USB_ACC_F2_HOV_LEN) - 1) << USB_ACC_F2_HOV_POS)) -#define USB_ACC_F3_HOV USB_ACC_F3_HOV -#define USB_ACC_F3_HOV_POS (3U) -#define USB_ACC_F3_HOV_LEN (1U) -#define USB_ACC_F3_HOV_MSK (((1U << USB_ACC_F3_HOV_LEN) - 1) << USB_ACC_F3_HOV_POS) -#define USB_ACC_F3_HOV_UMSK (~(((1U << USB_ACC_F3_HOV_LEN) - 1) << USB_ACC_F3_HOV_POS)) -#define USB_ACC_CXF_HOV USB_ACC_CXF_HOV -#define USB_ACC_CXF_HOV_POS (4U) -#define USB_ACC_CXF_HOV_LEN (1U) -#define USB_ACC_CXF_HOV_MSK (((1U << USB_ACC_CXF_HOV_LEN) - 1) << USB_ACC_CXF_HOV_POS) -#define USB_ACC_CXF_HOV_UMSK (~(((1U << USB_ACC_CXF_HOV_LEN) - 1) << USB_ACC_CXF_HOV_POS)) -#define USB_ACC_F4_HOV USB_ACC_F4_HOV -#define USB_ACC_F4_HOV_POS (5U) -#define USB_ACC_F4_HOV_LEN (1U) -#define USB_ACC_F4_HOV_MSK (((1U << USB_ACC_F4_HOV_LEN) - 1) << USB_ACC_F4_HOV_POS) -#define USB_ACC_F4_HOV_UMSK (~(((1U << USB_ACC_F4_HOV_LEN) - 1) << USB_ACC_F4_HOV_POS)) -#define USB_ACC_F5_HOV USB_ACC_F5_HOV -#define USB_ACC_F5_HOV_POS (6U) -#define USB_ACC_F5_HOV_LEN (1U) -#define USB_ACC_F5_HOV_MSK (((1U << USB_ACC_F5_HOV_LEN) - 1) << USB_ACC_F5_HOV_POS) -#define USB_ACC_F5_HOV_UMSK (~(((1U << USB_ACC_F5_HOV_LEN) - 1) << USB_ACC_F5_HOV_POS)) -#define USB_ACC_F6_HOV USB_ACC_F6_HOV -#define USB_ACC_F6_HOV_POS (7U) -#define USB_ACC_F6_HOV_LEN (1U) -#define USB_ACC_F6_HOV_MSK (((1U << USB_ACC_F6_HOV_LEN) - 1) << USB_ACC_F6_HOV_POS) -#define USB_ACC_F6_HOV_UMSK (~(((1U << USB_ACC_F6_HOV_LEN) - 1) << USB_ACC_F6_HOV_POS)) -#define USB_ACC_F7_HOV USB_ACC_F7_HOV -#define USB_ACC_F7_HOV_POS (8U) -#define USB_ACC_F7_HOV_LEN (1U) -#define USB_ACC_F7_HOV_MSK (((1U << USB_ACC_F7_HOV_LEN) - 1) << USB_ACC_F7_HOV_POS) -#define USB_ACC_F7_HOV_UMSK (~(((1U << USB_ACC_F7_HOV_LEN) - 1) << USB_ACC_F7_HOV_POS)) -#define USB_ACC_F8_HOV USB_ACC_F8_HOV -#define USB_ACC_F8_HOV_POS (9U) -#define USB_ACC_F8_HOV_LEN (1U) -#define USB_ACC_F8_HOV_MSK (((1U << USB_ACC_F8_HOV_LEN) - 1) << USB_ACC_F8_HOV_POS) -#define USB_ACC_F8_HOV_UMSK (~(((1U << USB_ACC_F8_HOV_LEN) - 1) << USB_ACC_F8_HOV_POS)) -#define USB_ACC_F9_HOV USB_ACC_F9_HOV -#define USB_ACC_F9_HOV_POS (10U) -#define USB_ACC_F9_HOV_LEN (1U) -#define USB_ACC_F9_HOV_MSK (((1U << USB_ACC_F9_HOV_LEN) - 1) << USB_ACC_F9_HOV_POS) -#define USB_ACC_F9_HOV_UMSK (~(((1U << USB_ACC_F9_HOV_LEN) - 1) << USB_ACC_F9_HOV_POS)) -#define USB_ACC_F10_HOV USB_ACC_F10_HOV -#define USB_ACC_F10_HOV_POS (11U) -#define USB_ACC_F10_HOV_LEN (1U) -#define USB_ACC_F10_HOV_MSK (((1U << USB_ACC_F10_HOV_LEN) - 1) << USB_ACC_F10_HOV_POS) -#define USB_ACC_F10_HOV_UMSK (~(((1U << USB_ACC_F10_HOV_LEN) - 1) << USB_ACC_F10_HOV_POS)) -#define USB_ACC_F11_HOV USB_ACC_F11_HOV -#define USB_ACC_F11_HOV_POS (12U) -#define USB_ACC_F11_HOV_LEN (1U) -#define USB_ACC_F11_HOV_MSK (((1U << USB_ACC_F11_HOV_LEN) - 1) << USB_ACC_F11_HOV_POS) -#define USB_ACC_F11_HOV_UMSK (~(((1U << USB_ACC_F11_HOV_LEN) - 1) << USB_ACC_F11_HOV_POS)) -#define USB_ACC_F12_HOV USB_ACC_F12_HOV -#define USB_ACC_F12_HOV_POS (13U) -#define USB_ACC_F12_HOV_LEN (1U) -#define USB_ACC_F12_HOV_MSK (((1U << USB_ACC_F12_HOV_LEN) - 1) << USB_ACC_F12_HOV_POS) -#define USB_ACC_F12_HOV_UMSK (~(((1U << USB_ACC_F12_HOV_LEN) - 1) << USB_ACC_F12_HOV_POS)) -#define USB_ACC_F13_HOV USB_ACC_F13_HOV -#define USB_ACC_F13_HOV_POS (14U) -#define USB_ACC_F13_HOV_LEN (1U) -#define USB_ACC_F13_HOV_MSK (((1U << USB_ACC_F13_HOV_LEN) - 1) << USB_ACC_F13_HOV_POS) -#define USB_ACC_F13_HOV_UMSK (~(((1U << USB_ACC_F13_HOV_LEN) - 1) << USB_ACC_F13_HOV_POS)) -#define USB_ACC_F14_HOV USB_ACC_F14_HOV -#define USB_ACC_F14_HOV_POS (15U) -#define USB_ACC_F14_HOV_LEN (1U) -#define USB_ACC_F14_HOV_MSK (((1U << USB_ACC_F14_HOV_LEN) - 1) << USB_ACC_F14_HOV_POS) -#define USB_ACC_F14_HOV_UMSK (~(((1U << USB_ACC_F14_HOV_LEN) - 1) << USB_ACC_F14_HOV_POS)) -#define USB_ACC_F15_HOV USB_ACC_F15_HOV -#define USB_ACC_F15_HOV_POS (16U) -#define USB_ACC_F15_HOV_LEN (1U) -#define USB_ACC_F15_HOV_MSK (((1U << USB_ACC_F15_HOV_LEN) - 1) << USB_ACC_F15_HOV_POS) -#define USB_ACC_F15_HOV_UMSK (~(((1U << USB_ACC_F15_HOV_LEN) - 1) << USB_ACC_F15_HOV_POS)) - -/* 0x1C4 : DMA_CPS0 */ -#define USB_DMA_CPS0_OFFSET (0x1C4) -#define USB_AWCHACHE_HOV USB_AWCHACHE_HOV -#define USB_AWCHACHE_HOV_POS (0U) -#define USB_AWCHACHE_HOV_LEN (4U) -#define USB_AWCHACHE_HOV_MSK (((1U << USB_AWCHACHE_HOV_LEN) - 1) << USB_AWCHACHE_HOV_POS) -#define USB_AWCHACHE_HOV_UMSK (~(((1U << USB_AWCHACHE_HOV_LEN) - 1) << USB_AWCHACHE_HOV_POS)) -#define USB_AWPORT_HOV USB_AWPORT_HOV -#define USB_AWPORT_HOV_POS (4U) -#define USB_AWPORT_HOV_LEN (3U) -#define USB_AWPORT_HOV_MSK (((1U << USB_AWPORT_HOV_LEN) - 1) << USB_AWPORT_HOV_POS) -#define USB_AWPORT_HOV_UMSK (~(((1U << USB_AWPORT_HOV_LEN) - 1) << USB_AWPORT_HOV_POS)) -#define USB_AWLOCK_HOV USB_AWLOCK_HOV -#define USB_AWLOCK_HOV_POS (7U) -#define USB_AWLOCK_HOV_LEN (2U) -#define USB_AWLOCK_HOV_MSK (((1U << USB_AWLOCK_HOV_LEN) - 1) << USB_AWLOCK_HOV_POS) -#define USB_AWLOCK_HOV_UMSK (~(((1U << USB_AWLOCK_HOV_LEN) - 1) << USB_AWLOCK_HOV_POS)) -#define USB_ARCACHE_HOV USB_ARCACHE_HOV -#define USB_ARCACHE_HOV_POS (9U) -#define USB_ARCACHE_HOV_LEN (4U) -#define USB_ARCACHE_HOV_MSK (((1U << USB_ARCACHE_HOV_LEN) - 1) << USB_ARCACHE_HOV_POS) -#define USB_ARCACHE_HOV_UMSK (~(((1U << USB_ARCACHE_HOV_LEN) - 1) << USB_ARCACHE_HOV_POS)) -#define USB_ARPORT_HOV USB_ARPORT_HOV -#define USB_ARPORT_HOV_POS (13U) -#define USB_ARPORT_HOV_LEN (3U) -#define USB_ARPORT_HOV_MSK (((1U << USB_ARPORT_HOV_LEN) - 1) << USB_ARPORT_HOV_POS) -#define USB_ARPORT_HOV_UMSK (~(((1U << USB_ARPORT_HOV_LEN) - 1) << USB_ARPORT_HOV_POS)) -#define USB_ARLOCK_HOV USB_ARLOCK_HOV -#define USB_ARLOCK_HOV_POS (16U) -#define USB_ARLOCK_HOV_LEN (2U) -#define USB_ARLOCK_HOV_MSK (((1U << USB_ARLOCK_HOV_LEN) - 1) << USB_ARLOCK_HOV_POS) -#define USB_ARLOCK_HOV_UMSK (~(((1U << USB_ARLOCK_HOV_LEN) - 1) << USB_ARLOCK_HOV_POS)) -#define USB_BUF_LD_EN_HOV USB_BUF_LD_EN_HOV -#define USB_BUF_LD_EN_HOV_POS (18U) -#define USB_BUF_LD_EN_HOV_LEN (1U) -#define USB_BUF_LD_EN_HOV_MSK (((1U << USB_BUF_LD_EN_HOV_LEN) - 1) << USB_BUF_LD_EN_HOV_POS) -#define USB_BUF_LD_EN_HOV_UMSK (~(((1U << USB_BUF_LD_EN_HOV_LEN) - 1) << USB_BUF_LD_EN_HOV_POS)) -#define USB_DST_WD_HOV USB_DST_WD_HOV -#define USB_DST_WD_HOV_POS (19U) -#define USB_DST_WD_HOV_LEN (1U) -#define USB_DST_WD_HOV_MSK (((1U << USB_DST_WD_HOV_LEN) - 1) << USB_DST_WD_HOV_POS) -#define USB_DST_WD_HOV_UMSK (~(((1U << USB_DST_WD_HOV_LEN) - 1) << USB_DST_WD_HOV_POS)) - -/* 0x1C8 : DMA_CPS1 */ -#define USB_DMA_CPS1_OFFSET (0x1C8) -#define USB_DMA_START_HOV USB_DMA_START_HOV -#define USB_DMA_START_HOV_POS (0U) -#define USB_DMA_START_HOV_LEN (1U) -#define USB_DMA_START_HOV_MSK (((1U << USB_DMA_START_HOV_LEN) - 1) << USB_DMA_START_HOV_POS) -#define USB_DMA_START_HOV_UMSK (~(((1U << USB_DMA_START_HOV_LEN) - 1) << USB_DMA_START_HOV_POS)) -#define USB_DMA_TYPE_HOV USB_DMA_TYPE_HOV -#define USB_DMA_TYPE_HOV_POS (1U) -#define USB_DMA_TYPE_HOV_LEN (1U) -#define USB_DMA_TYPE_HOV_MSK (((1U << USB_DMA_TYPE_HOV_LEN) - 1) << USB_DMA_TYPE_HOV_POS) -#define USB_DMA_TYPE_HOV_UMSK (~(((1U << USB_DMA_TYPE_HOV_LEN) - 1) << USB_DMA_TYPE_HOV_POS)) -#define USB_DMA_IO_HOV USB_DMA_IO_HOV -#define USB_DMA_IO_HOV_POS (2U) -#define USB_DMA_IO_HOV_LEN (1U) -#define USB_DMA_IO_HOV_MSK (((1U << USB_DMA_IO_HOV_LEN) - 1) << USB_DMA_IO_HOV_POS) -#define USB_DMA_IO_HOV_UMSK (~(((1U << USB_DMA_IO_HOV_LEN) - 1) << USB_DMA_IO_HOV_POS)) -#define USB_DMA_ABORT_HOV USB_DMA_ABORT_HOV -#define USB_DMA_ABORT_HOV_POS (3U) -#define USB_DMA_ABORT_HOV_LEN (1U) -#define USB_DMA_ABORT_HOV_MSK (((1U << USB_DMA_ABORT_HOV_LEN) - 1) << USB_DMA_ABORT_HOV_POS) -#define USB_DMA_ABORT_HOV_UMSK (~(((1U << USB_DMA_ABORT_HOV_LEN) - 1) << USB_DMA_ABORT_HOV_POS)) -#define USB_CLRFIFO_DMAABORT_HOV USB_CLRFIFO_DMAABORT_HOV -#define USB_CLRFIFO_DMAABORT_HOV_POS (4U) -#define USB_CLRFIFO_DMAABORT_HOV_LEN (1U) -#define USB_CLRFIFO_DMAABORT_HOV_MSK (((1U << USB_CLRFIFO_DMAABORT_HOV_LEN) - 1) << USB_CLRFIFO_DMAABORT_HOV_POS) -#define USB_CLRFIFO_DMAABORT_HOV_UMSK (~(((1U << USB_CLRFIFO_DMAABORT_HOV_LEN) - 1) << USB_CLRFIFO_DMAABORT_HOV_POS)) -#define USB_DMA_LEN_HOV USB_DMA_LEN_HOV -#define USB_DMA_LEN_HOV_POS (8U) -#define USB_DMA_LEN_HOV_LEN (17U) -#define USB_DMA_LEN_HOV_MSK (((1U << USB_DMA_LEN_HOV_LEN) - 1) << USB_DMA_LEN_HOV_POS) -#define USB_DMA_LEN_HOV_UMSK (~(((1U << USB_DMA_LEN_HOV_LEN) - 1) << USB_DMA_LEN_HOV_POS)) -#define USB_R_HPORT_HOV USB_R_HPORT_HOV -#define USB_R_HPORT_HOV_POS (25U) -#define USB_R_HPORT_HOV_LEN (4U) -#define USB_R_HPORT_HOV_MSK (((1U << USB_R_HPORT_HOV_LEN) - 1) << USB_R_HPORT_HOV_POS) -#define USB_R_HPORT_HOV_UMSK (~(((1U << USB_R_HPORT_HOV_LEN) - 1) << USB_R_HPORT_HOV_POS)) -#define USB_UNDEF_LEN_BURST_HOV USB_UNDEF_LEN_BURST_HOV -#define USB_UNDEF_LEN_BURST_HOV_POS (29U) -#define USB_UNDEF_LEN_BURST_HOV_LEN (1U) -#define USB_UNDEF_LEN_BURST_HOV_MSK (((1U << USB_UNDEF_LEN_BURST_HOV_LEN) - 1) << USB_UNDEF_LEN_BURST_HOV_POS) -#define USB_UNDEF_LEN_BURST_HOV_UMSK (~(((1U << USB_UNDEF_LEN_BURST_HOV_LEN) - 1) << USB_UNDEF_LEN_BURST_HOV_POS)) -#define USB_L1_WAKEUP USB_L1_WAKEUP -#define USB_L1_WAKEUP_POS (30U) -#define USB_L1_WAKEUP_LEN (1U) -#define USB_L1_WAKEUP_MSK (((1U << USB_L1_WAKEUP_LEN) - 1) << USB_L1_WAKEUP_POS) -#define USB_L1_WAKEUP_UMSK (~(((1U << USB_L1_WAKEUP_LEN) - 1) << USB_L1_WAKEUP_POS)) -#define USB_DEVPHY_SUSPEND_HOV USB_DEVPHY_SUSPEND_HOV -#define USB_DEVPHY_SUSPEND_HOV_POS (31U) -#define USB_DEVPHY_SUSPEND_HOV_LEN (1U) -#define USB_DEVPHY_SUSPEND_HOV_MSK (((1U << USB_DEVPHY_SUSPEND_HOV_LEN) - 1) << USB_DEVPHY_SUSPEND_HOV_POS) -#define USB_DEVPHY_SUSPEND_HOV_UMSK (~(((1U << USB_DEVPHY_SUSPEND_HOV_LEN) - 1) << USB_DEVPHY_SUSPEND_HOV_POS)) - -/* 0x1CC : DMA_CPS2 */ -#define USB_DMA_CPS2_OFFSET (0x1CC) -#define USB_DMA_MADDR_HOV USB_DMA_MADDR_HOV -#define USB_DMA_MADDR_HOV_POS (0U) -#define USB_DMA_MADDR_HOV_LEN (32U) -#define USB_DMA_MADDR_HOV_MSK (((1U << USB_DMA_MADDR_HOV_LEN) - 1) << USB_DMA_MADDR_HOV_POS) -#define USB_DMA_MADDR_HOV_UMSK (~(((1U << USB_DMA_MADDR_HOV_LEN) - 1) << USB_DMA_MADDR_HOV_POS)) - -/* 0x1D0 : DMA_CPS3 */ -#define USB_DMA_CPS3_OFFSET (0x1D0) -#define USB_SETUP_CMD_RPORT USB_SETUP_CMD_RPORT -#define USB_SETUP_CMD_RPORT_POS (0U) -#define USB_SETUP_CMD_RPORT_LEN (32U) -#define USB_SETUP_CMD_RPORT_MSK (((1U << USB_SETUP_CMD_RPORT_LEN) - 1) << USB_SETUP_CMD_RPORT_POS) -#define USB_SETUP_CMD_RPORT_UMSK (~(((1U << USB_SETUP_CMD_RPORT_LEN) - 1) << USB_SETUP_CMD_RPORT_POS)) - -/* 0x1D4 : DMA_CPS4 */ -#define USB_DMA_CPS4_OFFSET (0x1D4) - -/* 0x1D8 : DEV_FMAP2 */ -#define USB_DEV_FMAP2_OFFSET (0x1D8) -#define USB_EPNO_FIFO4 USB_EPNO_FIFO4 -#define USB_EPNO_FIFO4_POS (0U) -#define USB_EPNO_FIFO4_LEN (4U) -#define USB_EPNO_FIFO4_MSK (((1U << USB_EPNO_FIFO4_LEN) - 1) << USB_EPNO_FIFO4_POS) -#define USB_EPNO_FIFO4_UMSK (~(((1U << USB_EPNO_FIFO4_LEN) - 1) << USB_EPNO_FIFO4_POS)) -#define USB_DIR_FIFO4 USB_DIR_FIFO4 -#define USB_DIR_FIFO4_POS (4U) -#define USB_DIR_FIFO4_LEN (2U) -#define USB_DIR_FIFO4_MSK (((1U << USB_DIR_FIFO4_LEN) - 1) << USB_DIR_FIFO4_POS) -#define USB_DIR_FIFO4_UMSK (~(((1U << USB_DIR_FIFO4_LEN) - 1) << USB_DIR_FIFO4_POS)) -#define USB_EPNO_FIFO5 USB_EPNO_FIFO5 -#define USB_EPNO_FIFO5_POS (8U) -#define USB_EPNO_FIFO5_LEN (4U) -#define USB_EPNO_FIFO5_MSK (((1U << USB_EPNO_FIFO5_LEN) - 1) << USB_EPNO_FIFO5_POS) -#define USB_EPNO_FIFO5_UMSK (~(((1U << USB_EPNO_FIFO5_LEN) - 1) << USB_EPNO_FIFO5_POS)) -#define USB_DIR_FIFO5 USB_DIR_FIFO5 -#define USB_DIR_FIFO5_POS (12U) -#define USB_DIR_FIFO5_LEN (2U) -#define USB_DIR_FIFO5_MSK (((1U << USB_DIR_FIFO5_LEN) - 1) << USB_DIR_FIFO5_POS) -#define USB_DIR_FIFO5_UMSK (~(((1U << USB_DIR_FIFO5_LEN) - 1) << USB_DIR_FIFO5_POS)) -#define USB_EPNO_FIFO6 USB_EPNO_FIFO6 -#define USB_EPNO_FIFO6_POS (16U) -#define USB_EPNO_FIFO6_LEN (4U) -#define USB_EPNO_FIFO6_MSK (((1U << USB_EPNO_FIFO6_LEN) - 1) << USB_EPNO_FIFO6_POS) -#define USB_EPNO_FIFO6_UMSK (~(((1U << USB_EPNO_FIFO6_LEN) - 1) << USB_EPNO_FIFO6_POS)) -#define USB_DIR_FIFO6 USB_DIR_FIFO6 -#define USB_DIR_FIFO6_POS (20U) -#define USB_DIR_FIFO6_LEN (2U) -#define USB_DIR_FIFO6_MSK (((1U << USB_DIR_FIFO6_LEN) - 1) << USB_DIR_FIFO6_POS) -#define USB_DIR_FIFO6_UMSK (~(((1U << USB_DIR_FIFO6_LEN) - 1) << USB_DIR_FIFO6_POS)) -#define USB_EPNO_FIFO7 USB_EPNO_FIFO7 -#define USB_EPNO_FIFO7_POS (24U) -#define USB_EPNO_FIFO7_LEN (4U) -#define USB_EPNO_FIFO7_MSK (((1U << USB_EPNO_FIFO7_LEN) - 1) << USB_EPNO_FIFO7_POS) -#define USB_EPNO_FIFO7_UMSK (~(((1U << USB_EPNO_FIFO7_LEN) - 1) << USB_EPNO_FIFO7_POS)) -#define USB_DIR_FIFO7 USB_DIR_FIFO7 -#define USB_DIR_FIFO7_POS (28U) -#define USB_DIR_FIFO7_LEN (2U) -#define USB_DIR_FIFO7_MSK (((1U << USB_DIR_FIFO7_LEN) - 1) << USB_DIR_FIFO7_POS) -#define USB_DIR_FIFO7_UMSK (~(((1U << USB_DIR_FIFO7_LEN) - 1) << USB_DIR_FIFO7_POS)) - -/* 0x1DC : DEV_FCFG2 */ -#define USB_DEV_FCFG2_OFFSET (0x1DC) -#define USB_BLK_TYP_F4 USB_BLK_TYP_F4 -#define USB_BLK_TYP_F4_POS (0U) -#define USB_BLK_TYP_F4_LEN (2U) -#define USB_BLK_TYP_F4_MSK (((1U << USB_BLK_TYP_F4_LEN) - 1) << USB_BLK_TYP_F4_POS) -#define USB_BLK_TYP_F4_UMSK (~(((1U << USB_BLK_TYP_F4_LEN) - 1) << USB_BLK_TYP_F4_POS)) -#define USB_BLKNO_F4 USB_BLKNO_F4 -#define USB_BLKNO_F4_POS (2U) -#define USB_BLKNO_F4_LEN (2U) -#define USB_BLKNO_F4_MSK (((1U << USB_BLKNO_F4_LEN) - 1) << USB_BLKNO_F4_POS) -#define USB_BLKNO_F4_UMSK (~(((1U << USB_BLKNO_F4_LEN) - 1) << USB_BLKNO_F4_POS)) -#define USB_BLKSZ_F4 USB_BLKSZ_F4 -#define USB_BLKSZ_F4_POS (4U) -#define USB_BLKSZ_F4_LEN (1U) -#define USB_BLKSZ_F4_MSK (((1U << USB_BLKSZ_F4_LEN) - 1) << USB_BLKSZ_F4_POS) -#define USB_BLKSZ_F4_UMSK (~(((1U << USB_BLKSZ_F4_LEN) - 1) << USB_BLKSZ_F4_POS)) -#define USB_EN_F4 USB_EN_F4 -#define USB_EN_F4_POS (5U) -#define USB_EN_F4_LEN (1U) -#define USB_EN_F4_MSK (((1U << USB_EN_F4_LEN) - 1) << USB_EN_F4_POS) -#define USB_EN_F4_UMSK (~(((1U << USB_EN_F4_LEN) - 1) << USB_EN_F4_POS)) -#define USB_BLK_TYP_F5 USB_BLK_TYP_F5 -#define USB_BLK_TYP_F5_POS (8U) -#define USB_BLK_TYP_F5_LEN (2U) -#define USB_BLK_TYP_F5_MSK (((1U << USB_BLK_TYP_F5_LEN) - 1) << USB_BLK_TYP_F5_POS) -#define USB_BLK_TYP_F5_UMSK (~(((1U << USB_BLK_TYP_F5_LEN) - 1) << USB_BLK_TYP_F5_POS)) -#define USB_BLKNO_F5 USB_BLKNO_F5 -#define USB_BLKNO_F5_POS (10U) -#define USB_BLKNO_F5_LEN (2U) -#define USB_BLKNO_F5_MSK (((1U << USB_BLKNO_F5_LEN) - 1) << USB_BLKNO_F5_POS) -#define USB_BLKNO_F5_UMSK (~(((1U << USB_BLKNO_F5_LEN) - 1) << USB_BLKNO_F5_POS)) -#define USB_BLKSZ_F5 USB_BLKSZ_F5 -#define USB_BLKSZ_F5_POS (12U) -#define USB_BLKSZ_F5_LEN (1U) -#define USB_BLKSZ_F5_MSK (((1U << USB_BLKSZ_F5_LEN) - 1) << USB_BLKSZ_F5_POS) -#define USB_BLKSZ_F5_UMSK (~(((1U << USB_BLKSZ_F5_LEN) - 1) << USB_BLKSZ_F5_POS)) -#define USB_EN_F5 USB_EN_F5 -#define USB_EN_F5_POS (13U) -#define USB_EN_F5_LEN (1U) -#define USB_EN_F5_MSK (((1U << USB_EN_F5_LEN) - 1) << USB_EN_F5_POS) -#define USB_EN_F5_UMSK (~(((1U << USB_EN_F5_LEN) - 1) << USB_EN_F5_POS)) -#define USB_BLK_TYP_F6 USB_BLK_TYP_F6 -#define USB_BLK_TYP_F6_POS (16U) -#define USB_BLK_TYP_F6_LEN (2U) -#define USB_BLK_TYP_F6_MSK (((1U << USB_BLK_TYP_F6_LEN) - 1) << USB_BLK_TYP_F6_POS) -#define USB_BLK_TYP_F6_UMSK (~(((1U << USB_BLK_TYP_F6_LEN) - 1) << USB_BLK_TYP_F6_POS)) -#define USB_BLKNO_F6 USB_BLKNO_F6 -#define USB_BLKNO_F6_POS (18U) -#define USB_BLKNO_F6_LEN (2U) -#define USB_BLKNO_F6_MSK (((1U << USB_BLKNO_F6_LEN) - 1) << USB_BLKNO_F6_POS) -#define USB_BLKNO_F6_UMSK (~(((1U << USB_BLKNO_F6_LEN) - 1) << USB_BLKNO_F6_POS)) -#define USB_BLKSZ_F6 USB_BLKSZ_F6 -#define USB_BLKSZ_F6_POS (20U) -#define USB_BLKSZ_F6_LEN (1U) -#define USB_BLKSZ_F6_MSK (((1U << USB_BLKSZ_F6_LEN) - 1) << USB_BLKSZ_F6_POS) -#define USB_BLKSZ_F6_UMSK (~(((1U << USB_BLKSZ_F6_LEN) - 1) << USB_BLKSZ_F6_POS)) -#define USB_EN_F6 USB_EN_F6 -#define USB_EN_F6_POS (21U) -#define USB_EN_F6_LEN (1U) -#define USB_EN_F6_MSK (((1U << USB_EN_F6_LEN) - 1) << USB_EN_F6_POS) -#define USB_EN_F6_UMSK (~(((1U << USB_EN_F6_LEN) - 1) << USB_EN_F6_POS)) -#define USB_BLK_TYP_F7 USB_BLK_TYP_F7 -#define USB_BLK_TYP_F7_POS (24U) -#define USB_BLK_TYP_F7_LEN (2U) -#define USB_BLK_TYP_F7_MSK (((1U << USB_BLK_TYP_F7_LEN) - 1) << USB_BLK_TYP_F7_POS) -#define USB_BLK_TYP_F7_UMSK (~(((1U << USB_BLK_TYP_F7_LEN) - 1) << USB_BLK_TYP_F7_POS)) -#define USB_BLKNO_F7 USB_BLKNO_F7 -#define USB_BLKNO_F7_POS (26U) -#define USB_BLKNO_F7_LEN (2U) -#define USB_BLKNO_F7_MSK (((1U << USB_BLKNO_F7_LEN) - 1) << USB_BLKNO_F7_POS) -#define USB_BLKNO_F7_UMSK (~(((1U << USB_BLKNO_F7_LEN) - 1) << USB_BLKNO_F7_POS)) -#define USB_BLKSZ_F7 USB_BLKSZ_F7 -#define USB_BLKSZ_F7_POS (28U) -#define USB_BLKSZ_F7_LEN (1U) -#define USB_BLKSZ_F7_MSK (((1U << USB_BLKSZ_F7_LEN) - 1) << USB_BLKSZ_F7_POS) -#define USB_BLKSZ_F7_UMSK (~(((1U << USB_BLKSZ_F7_LEN) - 1) << USB_BLKSZ_F7_POS)) -#define USB_EN_F7 USB_EN_F7 -#define USB_EN_F7_POS (29U) -#define USB_EN_F7_LEN (1U) -#define USB_EN_F7_MSK (((1U << USB_EN_F7_LEN) - 1) << USB_EN_F7_POS) -#define USB_EN_F7_UMSK (~(((1U << USB_EN_F7_LEN) - 1) << USB_EN_F7_POS)) - -/* 0x1E0 : DEV_FMAP3 */ -#define USB_DEV_FMAP3_OFFSET (0x1E0) -#define USB_EPNO_FIFO8 USB_EPNO_FIFO8 -#define USB_EPNO_FIFO8_POS (0U) -#define USB_EPNO_FIFO8_LEN (4U) -#define USB_EPNO_FIFO8_MSK (((1U << USB_EPNO_FIFO8_LEN) - 1) << USB_EPNO_FIFO8_POS) -#define USB_EPNO_FIFO8_UMSK (~(((1U << USB_EPNO_FIFO8_LEN) - 1) << USB_EPNO_FIFO8_POS)) -#define USB_DIR_FIFO8 USB_DIR_FIFO8 -#define USB_DIR_FIFO8_POS (4U) -#define USB_DIR_FIFO8_LEN (2U) -#define USB_DIR_FIFO8_MSK (((1U << USB_DIR_FIFO8_LEN) - 1) << USB_DIR_FIFO8_POS) -#define USB_DIR_FIFO8_UMSK (~(((1U << USB_DIR_FIFO8_LEN) - 1) << USB_DIR_FIFO8_POS)) -#define USB_EPNO_FIFO9 USB_EPNO_FIFO9 -#define USB_EPNO_FIFO9_POS (8U) -#define USB_EPNO_FIFO9_LEN (4U) -#define USB_EPNO_FIFO9_MSK (((1U << USB_EPNO_FIFO9_LEN) - 1) << USB_EPNO_FIFO9_POS) -#define USB_EPNO_FIFO9_UMSK (~(((1U << USB_EPNO_FIFO9_LEN) - 1) << USB_EPNO_FIFO9_POS)) -#define USB_DIR_FIFO9 USB_DIR_FIFO9 -#define USB_DIR_FIFO9_POS (12U) -#define USB_DIR_FIFO9_LEN (2U) -#define USB_DIR_FIFO9_MSK (((1U << USB_DIR_FIFO9_LEN) - 1) << USB_DIR_FIFO9_POS) -#define USB_DIR_FIFO9_UMSK (~(((1U << USB_DIR_FIFO9_LEN) - 1) << USB_DIR_FIFO9_POS)) -#define USB_EPNO_FIFO10 USB_EPNO_FIFO10 -#define USB_EPNO_FIFO10_POS (16U) -#define USB_EPNO_FIFO10_LEN (4U) -#define USB_EPNO_FIFO10_MSK (((1U << USB_EPNO_FIFO10_LEN) - 1) << USB_EPNO_FIFO10_POS) -#define USB_EPNO_FIFO10_UMSK (~(((1U << USB_EPNO_FIFO10_LEN) - 1) << USB_EPNO_FIFO10_POS)) -#define USB_DIR_FIFO10 USB_DIR_FIFO10 -#define USB_DIR_FIFO10_POS (20U) -#define USB_DIR_FIFO10_LEN (2U) -#define USB_DIR_FIFO10_MSK (((1U << USB_DIR_FIFO10_LEN) - 1) << USB_DIR_FIFO10_POS) -#define USB_DIR_FIFO10_UMSK (~(((1U << USB_DIR_FIFO10_LEN) - 1) << USB_DIR_FIFO10_POS)) -#define USB_EPNO_FIFO11 USB_EPNO_FIFO11 -#define USB_EPNO_FIFO11_POS (24U) -#define USB_EPNO_FIFO11_LEN (4U) -#define USB_EPNO_FIFO11_MSK (((1U << USB_EPNO_FIFO11_LEN) - 1) << USB_EPNO_FIFO11_POS) -#define USB_EPNO_FIFO11_UMSK (~(((1U << USB_EPNO_FIFO11_LEN) - 1) << USB_EPNO_FIFO11_POS)) -#define USB_DIR_FIFO11 USB_DIR_FIFO11 -#define USB_DIR_FIFO11_POS (28U) -#define USB_DIR_FIFO11_LEN (2U) -#define USB_DIR_FIFO11_MSK (((1U << USB_DIR_FIFO11_LEN) - 1) << USB_DIR_FIFO11_POS) -#define USB_DIR_FIFO11_UMSK (~(((1U << USB_DIR_FIFO11_LEN) - 1) << USB_DIR_FIFO11_POS)) - -/* 0x1E4 : DEV_FCFG3 */ -#define USB_DEV_FCFG3_OFFSET (0x1E4) -#define USB_BLK_TYP_F8 USB_BLK_TYP_F8 -#define USB_BLK_TYP_F8_POS (0U) -#define USB_BLK_TYP_F8_LEN (2U) -#define USB_BLK_TYP_F8_MSK (((1U << USB_BLK_TYP_F8_LEN) - 1) << USB_BLK_TYP_F8_POS) -#define USB_BLK_TYP_F8_UMSK (~(((1U << USB_BLK_TYP_F8_LEN) - 1) << USB_BLK_TYP_F8_POS)) -#define USB_BLKNO_F8 USB_BLKNO_F8 -#define USB_BLKNO_F8_POS (2U) -#define USB_BLKNO_F8_LEN (2U) -#define USB_BLKNO_F8_MSK (((1U << USB_BLKNO_F8_LEN) - 1) << USB_BLKNO_F8_POS) -#define USB_BLKNO_F8_UMSK (~(((1U << USB_BLKNO_F8_LEN) - 1) << USB_BLKNO_F8_POS)) -#define USB_BLKSZ_F8 USB_BLKSZ_F8 -#define USB_BLKSZ_F8_POS (4U) -#define USB_BLKSZ_F8_LEN (1U) -#define USB_BLKSZ_F8_MSK (((1U << USB_BLKSZ_F8_LEN) - 1) << USB_BLKSZ_F8_POS) -#define USB_BLKSZ_F8_UMSK (~(((1U << USB_BLKSZ_F8_LEN) - 1) << USB_BLKSZ_F8_POS)) -#define USB_EN_F8 USB_EN_F8 -#define USB_EN_F8_POS (5U) -#define USB_EN_F8_LEN (1U) -#define USB_EN_F8_MSK (((1U << USB_EN_F8_LEN) - 1) << USB_EN_F8_POS) -#define USB_EN_F8_UMSK (~(((1U << USB_EN_F8_LEN) - 1) << USB_EN_F8_POS)) -#define USB_BLK_TYP_F9 USB_BLK_TYP_F9 -#define USB_BLK_TYP_F9_POS (8U) -#define USB_BLK_TYP_F9_LEN (2U) -#define USB_BLK_TYP_F9_MSK (((1U << USB_BLK_TYP_F9_LEN) - 1) << USB_BLK_TYP_F9_POS) -#define USB_BLK_TYP_F9_UMSK (~(((1U << USB_BLK_TYP_F9_LEN) - 1) << USB_BLK_TYP_F9_POS)) -#define USB_BLKNO_F9 USB_BLKNO_F9 -#define USB_BLKNO_F9_POS (10U) -#define USB_BLKNO_F9_LEN (2U) -#define USB_BLKNO_F9_MSK (((1U << USB_BLKNO_F9_LEN) - 1) << USB_BLKNO_F9_POS) -#define USB_BLKNO_F9_UMSK (~(((1U << USB_BLKNO_F9_LEN) - 1) << USB_BLKNO_F9_POS)) -#define USB_BLKSZ_F9 USB_BLKSZ_F9 -#define USB_BLKSZ_F9_POS (12U) -#define USB_BLKSZ_F9_LEN (1U) -#define USB_BLKSZ_F9_MSK (((1U << USB_BLKSZ_F9_LEN) - 1) << USB_BLKSZ_F9_POS) -#define USB_BLKSZ_F9_UMSK (~(((1U << USB_BLKSZ_F9_LEN) - 1) << USB_BLKSZ_F9_POS)) -#define USB_EN_F9 USB_EN_F9 -#define USB_EN_F9_POS (13U) -#define USB_EN_F9_LEN (1U) -#define USB_EN_F9_MSK (((1U << USB_EN_F9_LEN) - 1) << USB_EN_F9_POS) -#define USB_EN_F9_UMSK (~(((1U << USB_EN_F9_LEN) - 1) << USB_EN_F9_POS)) -#define USB_BLK_TYP_F10 USB_BLK_TYP_F10 -#define USB_BLK_TYP_F10_POS (16U) -#define USB_BLK_TYP_F10_LEN (2U) -#define USB_BLK_TYP_F10_MSK (((1U << USB_BLK_TYP_F10_LEN) - 1) << USB_BLK_TYP_F10_POS) -#define USB_BLK_TYP_F10_UMSK (~(((1U << USB_BLK_TYP_F10_LEN) - 1) << USB_BLK_TYP_F10_POS)) -#define USB_BLKNO_F10 USB_BLKNO_F10 -#define USB_BLKNO_F10_POS (18U) -#define USB_BLKNO_F10_LEN (2U) -#define USB_BLKNO_F10_MSK (((1U << USB_BLKNO_F10_LEN) - 1) << USB_BLKNO_F10_POS) -#define USB_BLKNO_F10_UMSK (~(((1U << USB_BLKNO_F10_LEN) - 1) << USB_BLKNO_F10_POS)) -#define USB_BLKSZ_F10 USB_BLKSZ_F10 -#define USB_BLKSZ_F10_POS (20U) -#define USB_BLKSZ_F10_LEN (1U) -#define USB_BLKSZ_F10_MSK (((1U << USB_BLKSZ_F10_LEN) - 1) << USB_BLKSZ_F10_POS) -#define USB_BLKSZ_F10_UMSK (~(((1U << USB_BLKSZ_F10_LEN) - 1) << USB_BLKSZ_F10_POS)) -#define USB_EN_F10 USB_EN_F10 -#define USB_EN_F10_POS (21U) -#define USB_EN_F10_LEN (1U) -#define USB_EN_F10_MSK (((1U << USB_EN_F10_LEN) - 1) << USB_EN_F10_POS) -#define USB_EN_F10_UMSK (~(((1U << USB_EN_F10_LEN) - 1) << USB_EN_F10_POS)) -#define USB_BLK_TYP_F11 USB_BLK_TYP_F11 -#define USB_BLK_TYP_F11_POS (24U) -#define USB_BLK_TYP_F11_LEN (2U) -#define USB_BLK_TYP_F11_MSK (((1U << USB_BLK_TYP_F11_LEN) - 1) << USB_BLK_TYP_F11_POS) -#define USB_BLK_TYP_F11_UMSK (~(((1U << USB_BLK_TYP_F11_LEN) - 1) << USB_BLK_TYP_F11_POS)) -#define USB_BLKNO_F11 USB_BLKNO_F11 -#define USB_BLKNO_F11_POS (26U) -#define USB_BLKNO_F11_LEN (2U) -#define USB_BLKNO_F11_MSK (((1U << USB_BLKNO_F11_LEN) - 1) << USB_BLKNO_F11_POS) -#define USB_BLKNO_F11_UMSK (~(((1U << USB_BLKNO_F11_LEN) - 1) << USB_BLKNO_F11_POS)) -#define USB_BLKSZ_F11 USB_BLKSZ_F11 -#define USB_BLKSZ_F11_POS (28U) -#define USB_BLKSZ_F11_LEN (1U) -#define USB_BLKSZ_F11_MSK (((1U << USB_BLKSZ_F11_LEN) - 1) << USB_BLKSZ_F11_POS) -#define USB_BLKSZ_F11_UMSK (~(((1U << USB_BLKSZ_F11_LEN) - 1) << USB_BLKSZ_F11_POS)) -#define USB_EN_F11 USB_EN_F11 -#define USB_EN_F11_POS (29U) -#define USB_EN_F11_LEN (1U) -#define USB_EN_F11_MSK (((1U << USB_EN_F11_LEN) - 1) << USB_EN_F11_POS) -#define USB_EN_F11_UMSK (~(((1U << USB_EN_F11_LEN) - 1) << USB_EN_F11_POS)) - -/* 0x1E8 : DEV_FMAP4 */ -#define USB_DEV_FMAP4_OFFSET (0x1E8) -#define USB_EPNO_FIFO12 USB_EPNO_FIFO12 -#define USB_EPNO_FIFO12_POS (0U) -#define USB_EPNO_FIFO12_LEN (4U) -#define USB_EPNO_FIFO12_MSK (((1U << USB_EPNO_FIFO12_LEN) - 1) << USB_EPNO_FIFO12_POS) -#define USB_EPNO_FIFO12_UMSK (~(((1U << USB_EPNO_FIFO12_LEN) - 1) << USB_EPNO_FIFO12_POS)) -#define USB_DIR_FIFO12 USB_DIR_FIFO12 -#define USB_DIR_FIFO12_POS (4U) -#define USB_DIR_FIFO12_LEN (2U) -#define USB_DIR_FIFO12_MSK (((1U << USB_DIR_FIFO12_LEN) - 1) << USB_DIR_FIFO12_POS) -#define USB_DIR_FIFO12_UMSK (~(((1U << USB_DIR_FIFO12_LEN) - 1) << USB_DIR_FIFO12_POS)) -#define USB_EPNO_FIFO13 USB_EPNO_FIFO13 -#define USB_EPNO_FIFO13_POS (8U) -#define USB_EPNO_FIFO13_LEN (4U) -#define USB_EPNO_FIFO13_MSK (((1U << USB_EPNO_FIFO13_LEN) - 1) << USB_EPNO_FIFO13_POS) -#define USB_EPNO_FIFO13_UMSK (~(((1U << USB_EPNO_FIFO13_LEN) - 1) << USB_EPNO_FIFO13_POS)) -#define USB_DIR_FIFO13 USB_DIR_FIFO13 -#define USB_DIR_FIFO13_POS (12U) -#define USB_DIR_FIFO13_LEN (2U) -#define USB_DIR_FIFO13_MSK (((1U << USB_DIR_FIFO13_LEN) - 1) << USB_DIR_FIFO13_POS) -#define USB_DIR_FIFO13_UMSK (~(((1U << USB_DIR_FIFO13_LEN) - 1) << USB_DIR_FIFO13_POS)) -#define USB_EPNO_FIFO14 USB_EPNO_FIFO14 -#define USB_EPNO_FIFO14_POS (16U) -#define USB_EPNO_FIFO14_LEN (4U) -#define USB_EPNO_FIFO14_MSK (((1U << USB_EPNO_FIFO14_LEN) - 1) << USB_EPNO_FIFO14_POS) -#define USB_EPNO_FIFO14_UMSK (~(((1U << USB_EPNO_FIFO14_LEN) - 1) << USB_EPNO_FIFO14_POS)) -#define USB_DIR_FIFO14 USB_DIR_FIFO14 -#define USB_DIR_FIFO14_POS (20U) -#define USB_DIR_FIFO14_LEN (2U) -#define USB_DIR_FIFO14_MSK (((1U << USB_DIR_FIFO14_LEN) - 1) << USB_DIR_FIFO14_POS) -#define USB_DIR_FIFO14_UMSK (~(((1U << USB_DIR_FIFO14_LEN) - 1) << USB_DIR_FIFO14_POS)) -#define USB_EPNO_FIFO15 USB_EPNO_FIFO15 -#define USB_EPNO_FIFO15_POS (24U) -#define USB_EPNO_FIFO15_LEN (4U) -#define USB_EPNO_FIFO15_MSK (((1U << USB_EPNO_FIFO15_LEN) - 1) << USB_EPNO_FIFO15_POS) -#define USB_EPNO_FIFO15_UMSK (~(((1U << USB_EPNO_FIFO15_LEN) - 1) << USB_EPNO_FIFO15_POS)) -#define USB_DIR_FIFO15 USB_DIR_FIFO15 -#define USB_DIR_FIFO15_POS (28U) -#define USB_DIR_FIFO15_LEN (2U) -#define USB_DIR_FIFO15_MSK (((1U << USB_DIR_FIFO15_LEN) - 1) << USB_DIR_FIFO15_POS) -#define USB_DIR_FIFO15_UMSK (~(((1U << USB_DIR_FIFO15_LEN) - 1) << USB_DIR_FIFO15_POS)) - -/* 0x1EC : DEV_FCFG4 */ -#define USB_DEV_FCFG4_OFFSET (0x1EC) -#define USB_BLK_TYP_F12 USB_BLK_TYP_F12 -#define USB_BLK_TYP_F12_POS (0U) -#define USB_BLK_TYP_F12_LEN (2U) -#define USB_BLK_TYP_F12_MSK (((1U << USB_BLK_TYP_F12_LEN) - 1) << USB_BLK_TYP_F12_POS) -#define USB_BLK_TYP_F12_UMSK (~(((1U << USB_BLK_TYP_F12_LEN) - 1) << USB_BLK_TYP_F12_POS)) -#define USB_BLKNO_F12 USB_BLKNO_F12 -#define USB_BLKNO_F12_POS (2U) -#define USB_BLKNO_F12_LEN (2U) -#define USB_BLKNO_F12_MSK (((1U << USB_BLKNO_F12_LEN) - 1) << USB_BLKNO_F12_POS) -#define USB_BLKNO_F12_UMSK (~(((1U << USB_BLKNO_F12_LEN) - 1) << USB_BLKNO_F12_POS)) -#define USB_BLKSZ_F12 USB_BLKSZ_F12 -#define USB_BLKSZ_F12_POS (4U) -#define USB_BLKSZ_F12_LEN (1U) -#define USB_BLKSZ_F12_MSK (((1U << USB_BLKSZ_F12_LEN) - 1) << USB_BLKSZ_F12_POS) -#define USB_BLKSZ_F12_UMSK (~(((1U << USB_BLKSZ_F12_LEN) - 1) << USB_BLKSZ_F12_POS)) -#define USB_EN_F12 USB_EN_F12 -#define USB_EN_F12_POS (5U) -#define USB_EN_F12_LEN (1U) -#define USB_EN_F12_MSK (((1U << USB_EN_F12_LEN) - 1) << USB_EN_F12_POS) -#define USB_EN_F12_UMSK (~(((1U << USB_EN_F12_LEN) - 1) << USB_EN_F12_POS)) -#define USB_BLK_TYP_F13 USB_BLK_TYP_F13 -#define USB_BLK_TYP_F13_POS (8U) -#define USB_BLK_TYP_F13_LEN (2U) -#define USB_BLK_TYP_F13_MSK (((1U << USB_BLK_TYP_F13_LEN) - 1) << USB_BLK_TYP_F13_POS) -#define USB_BLK_TYP_F13_UMSK (~(((1U << USB_BLK_TYP_F13_LEN) - 1) << USB_BLK_TYP_F13_POS)) -#define USB_BLKNO_F13 USB_BLKNO_F13 -#define USB_BLKNO_F13_POS (10U) -#define USB_BLKNO_F13_LEN (2U) -#define USB_BLKNO_F13_MSK (((1U << USB_BLKNO_F13_LEN) - 1) << USB_BLKNO_F13_POS) -#define USB_BLKNO_F13_UMSK (~(((1U << USB_BLKNO_F13_LEN) - 1) << USB_BLKNO_F13_POS)) -#define USB_BLKSZ_F13 USB_BLKSZ_F13 -#define USB_BLKSZ_F13_POS (12U) -#define USB_BLKSZ_F13_LEN (1U) -#define USB_BLKSZ_F13_MSK (((1U << USB_BLKSZ_F13_LEN) - 1) << USB_BLKSZ_F13_POS) -#define USB_BLKSZ_F13_UMSK (~(((1U << USB_BLKSZ_F13_LEN) - 1) << USB_BLKSZ_F13_POS)) -#define USB_EN_F13 USB_EN_F13 -#define USB_EN_F13_POS (13U) -#define USB_EN_F13_LEN (1U) -#define USB_EN_F13_MSK (((1U << USB_EN_F13_LEN) - 1) << USB_EN_F13_POS) -#define USB_EN_F13_UMSK (~(((1U << USB_EN_F13_LEN) - 1) << USB_EN_F13_POS)) -#define USB_BLK_TYP_F14 USB_BLK_TYP_F14 -#define USB_BLK_TYP_F14_POS (16U) -#define USB_BLK_TYP_F14_LEN (2U) -#define USB_BLK_TYP_F14_MSK (((1U << USB_BLK_TYP_F14_LEN) - 1) << USB_BLK_TYP_F14_POS) -#define USB_BLK_TYP_F14_UMSK (~(((1U << USB_BLK_TYP_F14_LEN) - 1) << USB_BLK_TYP_F14_POS)) -#define USB_BLKNO_F14 USB_BLKNO_F14 -#define USB_BLKNO_F14_POS (18U) -#define USB_BLKNO_F14_LEN (2U) -#define USB_BLKNO_F14_MSK (((1U << USB_BLKNO_F14_LEN) - 1) << USB_BLKNO_F14_POS) -#define USB_BLKNO_F14_UMSK (~(((1U << USB_BLKNO_F14_LEN) - 1) << USB_BLKNO_F14_POS)) -#define USB_BLKSZ_F14 USB_BLKSZ_F14 -#define USB_BLKSZ_F14_POS (20U) -#define USB_BLKSZ_F14_LEN (1U) -#define USB_BLKSZ_F14_MSK (((1U << USB_BLKSZ_F14_LEN) - 1) << USB_BLKSZ_F14_POS) -#define USB_BLKSZ_F14_UMSK (~(((1U << USB_BLKSZ_F14_LEN) - 1) << USB_BLKSZ_F14_POS)) -#define USB_EN_F14 USB_EN_F14 -#define USB_EN_F14_POS (21U) -#define USB_EN_F14_LEN (1U) -#define USB_EN_F14_MSK (((1U << USB_EN_F14_LEN) - 1) << USB_EN_F14_POS) -#define USB_EN_F14_UMSK (~(((1U << USB_EN_F14_LEN) - 1) << USB_EN_F14_POS)) -#define USB_BLK_TYP_F15 USB_BLK_TYP_F15 -#define USB_BLK_TYP_F15_POS (24U) -#define USB_BLK_TYP_F15_LEN (2U) -#define USB_BLK_TYP_F15_MSK (((1U << USB_BLK_TYP_F15_LEN) - 1) << USB_BLK_TYP_F15_POS) -#define USB_BLK_TYP_F15_UMSK (~(((1U << USB_BLK_TYP_F15_LEN) - 1) << USB_BLK_TYP_F15_POS)) -#define USB_BLKNO_F15 USB_BLKNO_F15 -#define USB_BLKNO_F15_POS (26U) -#define USB_BLKNO_F15_LEN (2U) -#define USB_BLKNO_F15_MSK (((1U << USB_BLKNO_F15_LEN) - 1) << USB_BLKNO_F15_POS) -#define USB_BLKNO_F15_UMSK (~(((1U << USB_BLKNO_F15_LEN) - 1) << USB_BLKNO_F15_POS)) -#define USB_BLKSZ_F15 USB_BLKSZ_F15 -#define USB_BLKSZ_F15_POS (28U) -#define USB_BLKSZ_F15_LEN (1U) -#define USB_BLKSZ_F15_MSK (((1U << USB_BLKSZ_F15_LEN) - 1) << USB_BLKSZ_F15_POS) -#define USB_BLKSZ_F15_UMSK (~(((1U << USB_BLKSZ_F15_LEN) - 1) << USB_BLKSZ_F15_POS)) -#define USB_EN_F15 USB_EN_F15 -#define USB_EN_F15_POS (29U) -#define USB_EN_F15_LEN (1U) -#define USB_EN_F15_MSK (((1U << USB_EN_F15_LEN) - 1) << USB_EN_F15_POS) -#define USB_EN_F15_UMSK (~(((1U << USB_EN_F15_LEN) - 1) << USB_EN_F15_POS)) - -/* 0x1F0 : DEV_FIBC4 */ -#define USB_DEV_FIBC4_OFFSET (0x1F0) -#define USB_BC_F4 USB_BC_F4 -#define USB_BC_F4_POS (0U) -#define USB_BC_F4_LEN (11U) -#define USB_BC_F4_MSK (((1U << USB_BC_F4_LEN) - 1) << USB_BC_F4_POS) -#define USB_BC_F4_UMSK (~(((1U << USB_BC_F4_LEN) - 1) << USB_BC_F4_POS)) -#define USB_FFRST4_HOV USB_FFRST4_HOV -#define USB_FFRST4_HOV_POS (12U) -#define USB_FFRST4_HOV_LEN (1U) -#define USB_FFRST4_HOV_MSK (((1U << USB_FFRST4_HOV_LEN) - 1) << USB_FFRST4_HOV_POS) -#define USB_FFRST4_HOV_UMSK (~(((1U << USB_FFRST4_HOV_LEN) - 1) << USB_FFRST4_HOV_POS)) - -/* 0x1F4 : DEV_FIBC5 */ -#define USB_DEV_FIBC5_OFFSET (0x1F4) -#define USB_BC_F5 USB_BC_F5 -#define USB_BC_F5_POS (0U) -#define USB_BC_F5_LEN (11U) -#define USB_BC_F5_MSK (((1U << USB_BC_F5_LEN) - 1) << USB_BC_F5_POS) -#define USB_BC_F5_UMSK (~(((1U << USB_BC_F5_LEN) - 1) << USB_BC_F5_POS)) -#define USB_FFRST5_HOV USB_FFRST5_HOV -#define USB_FFRST5_HOV_POS (12U) -#define USB_FFRST5_HOV_LEN (1U) -#define USB_FFRST5_HOV_MSK (((1U << USB_FFRST5_HOV_LEN) - 1) << USB_FFRST5_HOV_POS) -#define USB_FFRST5_HOV_UMSK (~(((1U << USB_FFRST5_HOV_LEN) - 1) << USB_FFRST5_HOV_POS)) - -/* 0x1F8 : DEV_FIBC6 */ -#define USB_DEV_FIBC6_OFFSET (0x1F8) -#define USB_BC_F6 USB_BC_F6 -#define USB_BC_F6_POS (0U) -#define USB_BC_F6_LEN (11U) -#define USB_BC_F6_MSK (((1U << USB_BC_F6_LEN) - 1) << USB_BC_F6_POS) -#define USB_BC_F6_UMSK (~(((1U << USB_BC_F6_LEN) - 1) << USB_BC_F6_POS)) -#define USB_FFRST6_HOV USB_FFRST6_HOV -#define USB_FFRST6_HOV_POS (12U) -#define USB_FFRST6_HOV_LEN (1U) -#define USB_FFRST6_HOV_MSK (((1U << USB_FFRST6_HOV_LEN) - 1) << USB_FFRST6_HOV_POS) -#define USB_FFRST6_HOV_UMSK (~(((1U << USB_FFRST6_HOV_LEN) - 1) << USB_FFRST6_HOV_POS)) - -/* 0x1FC : DEV_FIBC7 */ -#define USB_DEV_FIBC7_OFFSET (0x1FC) -#define USB_BC_F7 USB_BC_F7 -#define USB_BC_F7_POS (0U) -#define USB_BC_F7_LEN (11U) -#define USB_BC_F7_MSK (((1U << USB_BC_F7_LEN) - 1) << USB_BC_F7_POS) -#define USB_BC_F7_UMSK (~(((1U << USB_BC_F7_LEN) - 1) << USB_BC_F7_POS)) -#define USB_FFRST7_HOV USB_FFRST7_HOV -#define USB_FFRST7_HOV_POS (12U) -#define USB_FFRST7_HOV_LEN (1U) -#define USB_FFRST7_HOV_MSK (((1U << USB_FFRST7_HOV_LEN) - 1) << USB_FFRST7_HOV_POS) -#define USB_FFRST7_HOV_UMSK (~(((1U << USB_FFRST7_HOV_LEN) - 1) << USB_FFRST7_HOV_POS)) - -/* 0x300 : VDMA_CXFPS1 */ -#define USB_VDMA_CXFPS1_OFFSET (0x300) -#define USB_VDMA_START_CXF USB_VDMA_START_CXF -#define USB_VDMA_START_CXF_POS (0U) -#define USB_VDMA_START_CXF_LEN (1U) -#define USB_VDMA_START_CXF_MSK (((1U << USB_VDMA_START_CXF_LEN) - 1) << USB_VDMA_START_CXF_POS) -#define USB_VDMA_START_CXF_UMSK (~(((1U << USB_VDMA_START_CXF_LEN) - 1) << USB_VDMA_START_CXF_POS)) -#define USB_VDMA_TYPE_CXF USB_VDMA_TYPE_CXF -#define USB_VDMA_TYPE_CXF_POS (1U) -#define USB_VDMA_TYPE_CXF_LEN (1U) -#define USB_VDMA_TYPE_CXF_MSK (((1U << USB_VDMA_TYPE_CXF_LEN) - 1) << USB_VDMA_TYPE_CXF_POS) -#define USB_VDMA_TYPE_CXF_UMSK (~(((1U << USB_VDMA_TYPE_CXF_LEN) - 1) << USB_VDMA_TYPE_CXF_POS)) -#define USB_VDMA_IO_CXF USB_VDMA_IO_CXF -#define USB_VDMA_IO_CXF_POS (2U) -#define USB_VDMA_IO_CXF_LEN (1U) -#define USB_VDMA_IO_CXF_MSK (((1U << USB_VDMA_IO_CXF_LEN) - 1) << USB_VDMA_IO_CXF_POS) -#define USB_VDMA_IO_CXF_UMSK (~(((1U << USB_VDMA_IO_CXF_LEN) - 1) << USB_VDMA_IO_CXF_POS)) -#define USB_VDMA_LEN_CXF USB_VDMA_LEN_CXF -#define USB_VDMA_LEN_CXF_POS (8U) -#define USB_VDMA_LEN_CXF_LEN (17U) -#define USB_VDMA_LEN_CXF_MSK (((1U << USB_VDMA_LEN_CXF_LEN) - 1) << USB_VDMA_LEN_CXF_POS) -#define USB_VDMA_LEN_CXF_UMSK (~(((1U << USB_VDMA_LEN_CXF_LEN) - 1) << USB_VDMA_LEN_CXF_POS)) - -/* 0x304 : None */ -#define USB_VDMA_CXFPS2_OFFSET (0x304) -#define USB_VDMA_MADDR_CXF USB_VDMA_MADDR_CXF -#define USB_VDMA_MADDR_CXF_POS (0U) -#define USB_VDMA_MADDR_CXF_LEN (32U) -#define USB_VDMA_MADDR_CXF_MSK (((1U << USB_VDMA_MADDR_CXF_LEN) - 1) << USB_VDMA_MADDR_CXF_POS) -#define USB_VDMA_MADDR_CXF_UMSK (~(((1U << USB_VDMA_MADDR_CXF_LEN) - 1) << USB_VDMA_MADDR_CXF_POS)) - -/* 0x308 : None */ -#define USB_VDMA_F0PS1_OFFSET (0x308) -#define USB_VDMA_START_F0 USB_VDMA_START_F0 -#define USB_VDMA_START_F0_POS (0U) -#define USB_VDMA_START_F0_LEN (1U) -#define USB_VDMA_START_F0_MSK (((1U << USB_VDMA_START_F0_LEN) - 1) << USB_VDMA_START_F0_POS) -#define USB_VDMA_START_F0_UMSK (~(((1U << USB_VDMA_START_F0_LEN) - 1) << USB_VDMA_START_F0_POS)) -#define USB_VDMA_TYPE_F0 USB_VDMA_TYPE_F0 -#define USB_VDMA_TYPE_F0_POS (1U) -#define USB_VDMA_TYPE_F0_LEN (1U) -#define USB_VDMA_TYPE_F0_MSK (((1U << USB_VDMA_TYPE_F0_LEN) - 1) << USB_VDMA_TYPE_F0_POS) -#define USB_VDMA_TYPE_F0_UMSK (~(((1U << USB_VDMA_TYPE_F0_LEN) - 1) << USB_VDMA_TYPE_F0_POS)) -#define USB_VDMA_IO_F0 USB_VDMA_IO_F0 -#define USB_VDMA_IO_F0_POS (2U) -#define USB_VDMA_IO_F0_LEN (1U) -#define USB_VDMA_IO_F0_MSK (((1U << USB_VDMA_IO_F0_LEN) - 1) << USB_VDMA_IO_F0_POS) -#define USB_VDMA_IO_F0_UMSK (~(((1U << USB_VDMA_IO_F0_LEN) - 1) << USB_VDMA_IO_F0_POS)) -#define USB_VDMA_LEN_F0 USB_VDMA_LEN_F0 -#define USB_VDMA_LEN_F0_POS (8U) -#define USB_VDMA_LEN_F0_LEN (17U) -#define USB_VDMA_LEN_F0_MSK (((1U << USB_VDMA_LEN_F0_LEN) - 1) << USB_VDMA_LEN_F0_POS) -#define USB_VDMA_LEN_F0_UMSK (~(((1U << USB_VDMA_LEN_F0_LEN) - 1) << USB_VDMA_LEN_F0_POS)) - -/* 0x30C : VDMA_F0PS2 */ -#define USB_VDMA_F0PS2_OFFSET (0x30C) -#define USB_VDMA_MADDR_F0 USB_VDMA_MADDR_F0 -#define USB_VDMA_MADDR_F0_POS (0U) -#define USB_VDMA_MADDR_F0_LEN (32U) -#define USB_VDMA_MADDR_F0_MSK (((1U << USB_VDMA_MADDR_F0_LEN) - 1) << USB_VDMA_MADDR_F0_POS) -#define USB_VDMA_MADDR_F0_UMSK (~(((1U << USB_VDMA_MADDR_F0_LEN) - 1) << USB_VDMA_MADDR_F0_POS)) - -/* 0x310 : VDMA_F1PS1 */ -#define USB_VDMA_F1PS1_OFFSET (0x310) -#define USB_VDMA_START_F1 USB_VDMA_START_F1 -#define USB_VDMA_START_F1_POS (0U) -#define USB_VDMA_START_F1_LEN (1U) -#define USB_VDMA_START_F1_MSK (((1U << USB_VDMA_START_F1_LEN) - 1) << USB_VDMA_START_F1_POS) -#define USB_VDMA_START_F1_UMSK (~(((1U << USB_VDMA_START_F1_LEN) - 1) << USB_VDMA_START_F1_POS)) -#define USB_VDMA_TYPE_F1 USB_VDMA_TYPE_F1 -#define USB_VDMA_TYPE_F1_POS (1U) -#define USB_VDMA_TYPE_F1_LEN (1U) -#define USB_VDMA_TYPE_F1_MSK (((1U << USB_VDMA_TYPE_F1_LEN) - 1) << USB_VDMA_TYPE_F1_POS) -#define USB_VDMA_TYPE_F1_UMSK (~(((1U << USB_VDMA_TYPE_F1_LEN) - 1) << USB_VDMA_TYPE_F1_POS)) -#define USB_VDMA_IO_F1 USB_VDMA_IO_F1 -#define USB_VDMA_IO_F1_POS (2U) -#define USB_VDMA_IO_F1_LEN (1U) -#define USB_VDMA_IO_F1_MSK (((1U << USB_VDMA_IO_F1_LEN) - 1) << USB_VDMA_IO_F1_POS) -#define USB_VDMA_IO_F1_UMSK (~(((1U << USB_VDMA_IO_F1_LEN) - 1) << USB_VDMA_IO_F1_POS)) -#define USB_VDMA_LEN_F1 USB_VDMA_LEN_F1 -#define USB_VDMA_LEN_F1_POS (8U) -#define USB_VDMA_LEN_F1_LEN (17U) -#define USB_VDMA_LEN_F1_MSK (((1U << USB_VDMA_LEN_F1_LEN) - 1) << USB_VDMA_LEN_F1_POS) -#define USB_VDMA_LEN_F1_UMSK (~(((1U << USB_VDMA_LEN_F1_LEN) - 1) << USB_VDMA_LEN_F1_POS)) - -/* 0x314 : VDMA_F1PS2 */ -#define USB_VDMA_F1PS2_OFFSET (0x314) -#define USB_VDMA_MADDR_F1 USB_VDMA_MADDR_F1 -#define USB_VDMA_MADDR_F1_POS (0U) -#define USB_VDMA_MADDR_F1_LEN (32U) -#define USB_VDMA_MADDR_F1_MSK (((1U << USB_VDMA_MADDR_F1_LEN) - 1) << USB_VDMA_MADDR_F1_POS) -#define USB_VDMA_MADDR_F1_UMSK (~(((1U << USB_VDMA_MADDR_F1_LEN) - 1) << USB_VDMA_MADDR_F1_POS)) - -/* 0x318 : VDMA_F2PS1 */ -#define USB_VDMA_F2PS1_OFFSET (0x318) -#define USB_VDMA_START_F2 USB_VDMA_START_F2 -#define USB_VDMA_START_F2_POS (0U) -#define USB_VDMA_START_F2_LEN (1U) -#define USB_VDMA_START_F2_MSK (((1U << USB_VDMA_START_F2_LEN) - 1) << USB_VDMA_START_F2_POS) -#define USB_VDMA_START_F2_UMSK (~(((1U << USB_VDMA_START_F2_LEN) - 1) << USB_VDMA_START_F2_POS)) -#define USB_VDMA_TYPE_F2 USB_VDMA_TYPE_F2 -#define USB_VDMA_TYPE_F2_POS (1U) -#define USB_VDMA_TYPE_F2_LEN (1U) -#define USB_VDMA_TYPE_F2_MSK (((1U << USB_VDMA_TYPE_F2_LEN) - 1) << USB_VDMA_TYPE_F2_POS) -#define USB_VDMA_TYPE_F2_UMSK (~(((1U << USB_VDMA_TYPE_F2_LEN) - 1) << USB_VDMA_TYPE_F2_POS)) -#define USB_VDMA_IO_F2 USB_VDMA_IO_F2 -#define USB_VDMA_IO_F2_POS (2U) -#define USB_VDMA_IO_F2_LEN (1U) -#define USB_VDMA_IO_F2_MSK (((1U << USB_VDMA_IO_F2_LEN) - 1) << USB_VDMA_IO_F2_POS) -#define USB_VDMA_IO_F2_UMSK (~(((1U << USB_VDMA_IO_F2_LEN) - 1) << USB_VDMA_IO_F2_POS)) -#define USB_VDMA_LEN_F2 USB_VDMA_LEN_F2 -#define USB_VDMA_LEN_F2_POS (8U) -#define USB_VDMA_LEN_F2_LEN (17U) -#define USB_VDMA_LEN_F2_MSK (((1U << USB_VDMA_LEN_F2_LEN) - 1) << USB_VDMA_LEN_F2_POS) -#define USB_VDMA_LEN_F2_UMSK (~(((1U << USB_VDMA_LEN_F2_LEN) - 1) << USB_VDMA_LEN_F2_POS)) - -/* 0x31C : VDMA_F2PS2 */ -#define USB_VDMA_F2PS2_OFFSET (0x31C) -#define USB_VDMA_MADDR_F2 USB_VDMA_MADDR_F2 -#define USB_VDMA_MADDR_F2_POS (0U) -#define USB_VDMA_MADDR_F2_LEN (32U) -#define USB_VDMA_MADDR_F2_MSK (((1U << USB_VDMA_MADDR_F2_LEN) - 1) << USB_VDMA_MADDR_F2_POS) -#define USB_VDMA_MADDR_F2_UMSK (~(((1U << USB_VDMA_MADDR_F2_LEN) - 1) << USB_VDMA_MADDR_F2_POS)) - -/* 0x320 : VDMA_F3PS1 */ -#define USB_VDMA_F3PS1_OFFSET (0x320) -#define USB_VDMA_START_F3 USB_VDMA_START_F3 -#define USB_VDMA_START_F3_POS (0U) -#define USB_VDMA_START_F3_LEN (1U) -#define USB_VDMA_START_F3_MSK (((1U << USB_VDMA_START_F3_LEN) - 1) << USB_VDMA_START_F3_POS) -#define USB_VDMA_START_F3_UMSK (~(((1U << USB_VDMA_START_F3_LEN) - 1) << USB_VDMA_START_F3_POS)) -#define USB_VDMA_TYPE_F3 USB_VDMA_TYPE_F3 -#define USB_VDMA_TYPE_F3_POS (1U) -#define USB_VDMA_TYPE_F3_LEN (1U) -#define USB_VDMA_TYPE_F3_MSK (((1U << USB_VDMA_TYPE_F3_LEN) - 1) << USB_VDMA_TYPE_F3_POS) -#define USB_VDMA_TYPE_F3_UMSK (~(((1U << USB_VDMA_TYPE_F3_LEN) - 1) << USB_VDMA_TYPE_F3_POS)) -#define USB_VDMA_IO_F3 USB_VDMA_IO_F3 -#define USB_VDMA_IO_F3_POS (2U) -#define USB_VDMA_IO_F3_LEN (1U) -#define USB_VDMA_IO_F3_MSK (((1U << USB_VDMA_IO_F3_LEN) - 1) << USB_VDMA_IO_F3_POS) -#define USB_VDMA_IO_F3_UMSK (~(((1U << USB_VDMA_IO_F3_LEN) - 1) << USB_VDMA_IO_F3_POS)) -#define USB_VDMA_LEN_F3 USB_VDMA_LEN_F3 -#define USB_VDMA_LEN_F3_POS (8U) -#define USB_VDMA_LEN_F3_LEN (17U) -#define USB_VDMA_LEN_F3_MSK (((1U << USB_VDMA_LEN_F3_LEN) - 1) << USB_VDMA_LEN_F3_POS) -#define USB_VDMA_LEN_F3_UMSK (~(((1U << USB_VDMA_LEN_F3_LEN) - 1) << USB_VDMA_LEN_F3_POS)) - -/* 0x324 : VDMA_F3PS2 */ -#define USB_VDMA_F3PS2_OFFSET (0x324) -#define USB_VDMA_MADDR_F3 USB_VDMA_MADDR_F3 -#define USB_VDMA_MADDR_F3_POS (0U) -#define USB_VDMA_MADDR_F3_LEN (32U) -#define USB_VDMA_MADDR_F3_MSK (((1U << USB_VDMA_MADDR_F3_LEN) - 1) << USB_VDMA_MADDR_F3_POS) -#define USB_VDMA_MADDR_F3_UMSK (~(((1U << USB_VDMA_MADDR_F3_LEN) - 1) << USB_VDMA_MADDR_F3_POS)) - -/* 0x328 : DEV_ISG3 */ -#define USB_DEV_ISG3_OFFSET (0x328) -#define USB_VDMA_CMPLT_CXF USB_VDMA_CMPLT_CXF -#define USB_VDMA_CMPLT_CXF_POS (0U) -#define USB_VDMA_CMPLT_CXF_LEN (1U) -#define USB_VDMA_CMPLT_CXF_MSK (((1U << USB_VDMA_CMPLT_CXF_LEN) - 1) << USB_VDMA_CMPLT_CXF_POS) -#define USB_VDMA_CMPLT_CXF_UMSK (~(((1U << USB_VDMA_CMPLT_CXF_LEN) - 1) << USB_VDMA_CMPLT_CXF_POS)) -#define USB_VDMA_CMPLT_F0 USB_VDMA_CMPLT_F0 -#define USB_VDMA_CMPLT_F0_POS (1U) -#define USB_VDMA_CMPLT_F0_LEN (1U) -#define USB_VDMA_CMPLT_F0_MSK (((1U << USB_VDMA_CMPLT_F0_LEN) - 1) << USB_VDMA_CMPLT_F0_POS) -#define USB_VDMA_CMPLT_F0_UMSK (~(((1U << USB_VDMA_CMPLT_F0_LEN) - 1) << USB_VDMA_CMPLT_F0_POS)) -#define USB_VDMA_CMPLT_F1 USB_VDMA_CMPLT_F1 -#define USB_VDMA_CMPLT_F1_POS (2U) -#define USB_VDMA_CMPLT_F1_LEN (1U) -#define USB_VDMA_CMPLT_F1_MSK (((1U << USB_VDMA_CMPLT_F1_LEN) - 1) << USB_VDMA_CMPLT_F1_POS) -#define USB_VDMA_CMPLT_F1_UMSK (~(((1U << USB_VDMA_CMPLT_F1_LEN) - 1) << USB_VDMA_CMPLT_F1_POS)) -#define USB_VDMA_CMPLT_F2 USB_VDMA_CMPLT_F2 -#define USB_VDMA_CMPLT_F2_POS (3U) -#define USB_VDMA_CMPLT_F2_LEN (1U) -#define USB_VDMA_CMPLT_F2_MSK (((1U << USB_VDMA_CMPLT_F2_LEN) - 1) << USB_VDMA_CMPLT_F2_POS) -#define USB_VDMA_CMPLT_F2_UMSK (~(((1U << USB_VDMA_CMPLT_F2_LEN) - 1) << USB_VDMA_CMPLT_F2_POS)) -#define USB_VDMA_CMPLT_F3 USB_VDMA_CMPLT_F3 -#define USB_VDMA_CMPLT_F3_POS (4U) -#define USB_VDMA_CMPLT_F3_LEN (1U) -#define USB_VDMA_CMPLT_F3_MSK (((1U << USB_VDMA_CMPLT_F3_LEN) - 1) << USB_VDMA_CMPLT_F3_POS) -#define USB_VDMA_CMPLT_F3_UMSK (~(((1U << USB_VDMA_CMPLT_F3_LEN) - 1) << USB_VDMA_CMPLT_F3_POS)) -#define USB_VDMA_CMPLT_F4 USB_VDMA_CMPLT_F4 -#define USB_VDMA_CMPLT_F4_POS (5U) -#define USB_VDMA_CMPLT_F4_LEN (1U) -#define USB_VDMA_CMPLT_F4_MSK (((1U << USB_VDMA_CMPLT_F4_LEN) - 1) << USB_VDMA_CMPLT_F4_POS) -#define USB_VDMA_CMPLT_F4_UMSK (~(((1U << USB_VDMA_CMPLT_F4_LEN) - 1) << USB_VDMA_CMPLT_F4_POS)) -#define USB_VDMA_CMPLT_F5 USB_VDMA_CMPLT_F5 -#define USB_VDMA_CMPLT_F5_POS (6U) -#define USB_VDMA_CMPLT_F5_LEN (1U) -#define USB_VDMA_CMPLT_F5_MSK (((1U << USB_VDMA_CMPLT_F5_LEN) - 1) << USB_VDMA_CMPLT_F5_POS) -#define USB_VDMA_CMPLT_F5_UMSK (~(((1U << USB_VDMA_CMPLT_F5_LEN) - 1) << USB_VDMA_CMPLT_F5_POS)) -#define USB_VDMA_CMPLT_F6 USB_VDMA_CMPLT_F6 -#define USB_VDMA_CMPLT_F6_POS (7U) -#define USB_VDMA_CMPLT_F6_LEN (1U) -#define USB_VDMA_CMPLT_F6_MSK (((1U << USB_VDMA_CMPLT_F6_LEN) - 1) << USB_VDMA_CMPLT_F6_POS) -#define USB_VDMA_CMPLT_F6_UMSK (~(((1U << USB_VDMA_CMPLT_F6_LEN) - 1) << USB_VDMA_CMPLT_F6_POS)) -#define USB_VDMA_CMPLT_F7 USB_VDMA_CMPLT_F7 -#define USB_VDMA_CMPLT_F7_POS (8U) -#define USB_VDMA_CMPLT_F7_LEN (1U) -#define USB_VDMA_CMPLT_F7_MSK (((1U << USB_VDMA_CMPLT_F7_LEN) - 1) << USB_VDMA_CMPLT_F7_POS) -#define USB_VDMA_CMPLT_F7_UMSK (~(((1U << USB_VDMA_CMPLT_F7_LEN) - 1) << USB_VDMA_CMPLT_F7_POS)) -#define USB_VDMA_CMPLT_F8 USB_VDMA_CMPLT_F8 -#define USB_VDMA_CMPLT_F8_POS (9U) -#define USB_VDMA_CMPLT_F8_LEN (1U) -#define USB_VDMA_CMPLT_F8_MSK (((1U << USB_VDMA_CMPLT_F8_LEN) - 1) << USB_VDMA_CMPLT_F8_POS) -#define USB_VDMA_CMPLT_F8_UMSK (~(((1U << USB_VDMA_CMPLT_F8_LEN) - 1) << USB_VDMA_CMPLT_F8_POS)) -#define USB_VDMA_CMPLT_F9 USB_VDMA_CMPLT_F9 -#define USB_VDMA_CMPLT_F9_POS (10U) -#define USB_VDMA_CMPLT_F9_LEN (1U) -#define USB_VDMA_CMPLT_F9_MSK (((1U << USB_VDMA_CMPLT_F9_LEN) - 1) << USB_VDMA_CMPLT_F9_POS) -#define USB_VDMA_CMPLT_F9_UMSK (~(((1U << USB_VDMA_CMPLT_F9_LEN) - 1) << USB_VDMA_CMPLT_F9_POS)) -#define USB_VDMA_CMPLT_F10 USB_VDMA_CMPLT_F10 -#define USB_VDMA_CMPLT_F10_POS (11U) -#define USB_VDMA_CMPLT_F10_LEN (1U) -#define USB_VDMA_CMPLT_F10_MSK (((1U << USB_VDMA_CMPLT_F10_LEN) - 1) << USB_VDMA_CMPLT_F10_POS) -#define USB_VDMA_CMPLT_F10_UMSK (~(((1U << USB_VDMA_CMPLT_F10_LEN) - 1) << USB_VDMA_CMPLT_F10_POS)) -#define USB_VDMA_CMPLT_F11 USB_VDMA_CMPLT_F11 -#define USB_VDMA_CMPLT_F11_POS (12U) -#define USB_VDMA_CMPLT_F11_LEN (1U) -#define USB_VDMA_CMPLT_F11_MSK (((1U << USB_VDMA_CMPLT_F11_LEN) - 1) << USB_VDMA_CMPLT_F11_POS) -#define USB_VDMA_CMPLT_F11_UMSK (~(((1U << USB_VDMA_CMPLT_F11_LEN) - 1) << USB_VDMA_CMPLT_F11_POS)) -#define USB_VDMA_CMPLT_F12 USB_VDMA_CMPLT_F12 -#define USB_VDMA_CMPLT_F12_POS (13U) -#define USB_VDMA_CMPLT_F12_LEN (1U) -#define USB_VDMA_CMPLT_F12_MSK (((1U << USB_VDMA_CMPLT_F12_LEN) - 1) << USB_VDMA_CMPLT_F12_POS) -#define USB_VDMA_CMPLT_F12_UMSK (~(((1U << USB_VDMA_CMPLT_F12_LEN) - 1) << USB_VDMA_CMPLT_F12_POS)) -#define USB_VDMA_CMPLT_F13 USB_VDMA_CMPLT_F13 -#define USB_VDMA_CMPLT_F13_POS (14U) -#define USB_VDMA_CMPLT_F13_LEN (1U) -#define USB_VDMA_CMPLT_F13_MSK (((1U << USB_VDMA_CMPLT_F13_LEN) - 1) << USB_VDMA_CMPLT_F13_POS) -#define USB_VDMA_CMPLT_F13_UMSK (~(((1U << USB_VDMA_CMPLT_F13_LEN) - 1) << USB_VDMA_CMPLT_F13_POS)) -#define USB_VDMA_CMPLT_F14 USB_VDMA_CMPLT_F14 -#define USB_VDMA_CMPLT_F14_POS (15U) -#define USB_VDMA_CMPLT_F14_LEN (1U) -#define USB_VDMA_CMPLT_F14_MSK (((1U << USB_VDMA_CMPLT_F14_LEN) - 1) << USB_VDMA_CMPLT_F14_POS) -#define USB_VDMA_CMPLT_F14_UMSK (~(((1U << USB_VDMA_CMPLT_F14_LEN) - 1) << USB_VDMA_CMPLT_F14_POS)) -#define USB_VDMA_ERROR_CXF USB_VDMA_ERROR_CXF -#define USB_VDMA_ERROR_CXF_POS (16U) -#define USB_VDMA_ERROR_CXF_LEN (1U) -#define USB_VDMA_ERROR_CXF_MSK (((1U << USB_VDMA_ERROR_CXF_LEN) - 1) << USB_VDMA_ERROR_CXF_POS) -#define USB_VDMA_ERROR_CXF_UMSK (~(((1U << USB_VDMA_ERROR_CXF_LEN) - 1) << USB_VDMA_ERROR_CXF_POS)) -#define USB_VDMA_ERROR_F0 USB_VDMA_ERROR_F0 -#define USB_VDMA_ERROR_F0_POS (17U) -#define USB_VDMA_ERROR_F0_LEN (1U) -#define USB_VDMA_ERROR_F0_MSK (((1U << USB_VDMA_ERROR_F0_LEN) - 1) << USB_VDMA_ERROR_F0_POS) -#define USB_VDMA_ERROR_F0_UMSK (~(((1U << USB_VDMA_ERROR_F0_LEN) - 1) << USB_VDMA_ERROR_F0_POS)) -#define USB_VDMA_ERROR_F1 USB_VDMA_ERROR_F1 -#define USB_VDMA_ERROR_F1_POS (18U) -#define USB_VDMA_ERROR_F1_LEN (1U) -#define USB_VDMA_ERROR_F1_MSK (((1U << USB_VDMA_ERROR_F1_LEN) - 1) << USB_VDMA_ERROR_F1_POS) -#define USB_VDMA_ERROR_F1_UMSK (~(((1U << USB_VDMA_ERROR_F1_LEN) - 1) << USB_VDMA_ERROR_F1_POS)) -#define USB_VDMA_ERROR_F2 USB_VDMA_ERROR_F2 -#define USB_VDMA_ERROR_F2_POS (19U) -#define USB_VDMA_ERROR_F2_LEN (1U) -#define USB_VDMA_ERROR_F2_MSK (((1U << USB_VDMA_ERROR_F2_LEN) - 1) << USB_VDMA_ERROR_F2_POS) -#define USB_VDMA_ERROR_F2_UMSK (~(((1U << USB_VDMA_ERROR_F2_LEN) - 1) << USB_VDMA_ERROR_F2_POS)) -#define USB_VDMA_ERROR_F3 USB_VDMA_ERROR_F3 -#define USB_VDMA_ERROR_F3_POS (20U) -#define USB_VDMA_ERROR_F3_LEN (1U) -#define USB_VDMA_ERROR_F3_MSK (((1U << USB_VDMA_ERROR_F3_LEN) - 1) << USB_VDMA_ERROR_F3_POS) -#define USB_VDMA_ERROR_F3_UMSK (~(((1U << USB_VDMA_ERROR_F3_LEN) - 1) << USB_VDMA_ERROR_F3_POS)) -#define USB_VDMA_ERROR_F4 USB_VDMA_ERROR_F4 -#define USB_VDMA_ERROR_F4_POS (21U) -#define USB_VDMA_ERROR_F4_LEN (1U) -#define USB_VDMA_ERROR_F4_MSK (((1U << USB_VDMA_ERROR_F4_LEN) - 1) << USB_VDMA_ERROR_F4_POS) -#define USB_VDMA_ERROR_F4_UMSK (~(((1U << USB_VDMA_ERROR_F4_LEN) - 1) << USB_VDMA_ERROR_F4_POS)) -#define USB_VDMA_ERROR_F5 USB_VDMA_ERROR_F5 -#define USB_VDMA_ERROR_F5_POS (22U) -#define USB_VDMA_ERROR_F5_LEN (1U) -#define USB_VDMA_ERROR_F5_MSK (((1U << USB_VDMA_ERROR_F5_LEN) - 1) << USB_VDMA_ERROR_F5_POS) -#define USB_VDMA_ERROR_F5_UMSK (~(((1U << USB_VDMA_ERROR_F5_LEN) - 1) << USB_VDMA_ERROR_F5_POS)) -#define USB_VDMA_ERROR_F6 USB_VDMA_ERROR_F6 -#define USB_VDMA_ERROR_F6_POS (23U) -#define USB_VDMA_ERROR_F6_LEN (1U) -#define USB_VDMA_ERROR_F6_MSK (((1U << USB_VDMA_ERROR_F6_LEN) - 1) << USB_VDMA_ERROR_F6_POS) -#define USB_VDMA_ERROR_F6_UMSK (~(((1U << USB_VDMA_ERROR_F6_LEN) - 1) << USB_VDMA_ERROR_F6_POS)) -#define USB_VDMA_ERROR_F7 USB_VDMA_ERROR_F7 -#define USB_VDMA_ERROR_F7_POS (24U) -#define USB_VDMA_ERROR_F7_LEN (1U) -#define USB_VDMA_ERROR_F7_MSK (((1U << USB_VDMA_ERROR_F7_LEN) - 1) << USB_VDMA_ERROR_F7_POS) -#define USB_VDMA_ERROR_F7_UMSK (~(((1U << USB_VDMA_ERROR_F7_LEN) - 1) << USB_VDMA_ERROR_F7_POS)) -#define USB_VDMA_ERROR_F8 USB_VDMA_ERROR_F8 -#define USB_VDMA_ERROR_F8_POS (25U) -#define USB_VDMA_ERROR_F8_LEN (1U) -#define USB_VDMA_ERROR_F8_MSK (((1U << USB_VDMA_ERROR_F8_LEN) - 1) << USB_VDMA_ERROR_F8_POS) -#define USB_VDMA_ERROR_F8_UMSK (~(((1U << USB_VDMA_ERROR_F8_LEN) - 1) << USB_VDMA_ERROR_F8_POS)) -#define USB_VDMA_ERROR_F9 USB_VDMA_ERROR_F9 -#define USB_VDMA_ERROR_F9_POS (26U) -#define USB_VDMA_ERROR_F9_LEN (1U) -#define USB_VDMA_ERROR_F9_MSK (((1U << USB_VDMA_ERROR_F9_LEN) - 1) << USB_VDMA_ERROR_F9_POS) -#define USB_VDMA_ERROR_F9_UMSK (~(((1U << USB_VDMA_ERROR_F9_LEN) - 1) << USB_VDMA_ERROR_F9_POS)) -#define USB_VDMA_ERROR_F10 USB_VDMA_ERROR_F10 -#define USB_VDMA_ERROR_F10_POS (27U) -#define USB_VDMA_ERROR_F10_LEN (1U) -#define USB_VDMA_ERROR_F10_MSK (((1U << USB_VDMA_ERROR_F10_LEN) - 1) << USB_VDMA_ERROR_F10_POS) -#define USB_VDMA_ERROR_F10_UMSK (~(((1U << USB_VDMA_ERROR_F10_LEN) - 1) << USB_VDMA_ERROR_F10_POS)) -#define USB_VDMA_ERROR_F11 USB_VDMA_ERROR_F11 -#define USB_VDMA_ERROR_F11_POS (28U) -#define USB_VDMA_ERROR_F11_LEN (1U) -#define USB_VDMA_ERROR_F11_MSK (((1U << USB_VDMA_ERROR_F11_LEN) - 1) << USB_VDMA_ERROR_F11_POS) -#define USB_VDMA_ERROR_F11_UMSK (~(((1U << USB_VDMA_ERROR_F11_LEN) - 1) << USB_VDMA_ERROR_F11_POS)) -#define USB_VDMA_ERROR_F12 USB_VDMA_ERROR_F12 -#define USB_VDMA_ERROR_F12_POS (29U) -#define USB_VDMA_ERROR_F12_LEN (1U) -#define USB_VDMA_ERROR_F12_MSK (((1U << USB_VDMA_ERROR_F12_LEN) - 1) << USB_VDMA_ERROR_F12_POS) -#define USB_VDMA_ERROR_F12_UMSK (~(((1U << USB_VDMA_ERROR_F12_LEN) - 1) << USB_VDMA_ERROR_F12_POS)) -#define USB_VDMA_ERROR_F13 USB_VDMA_ERROR_F13 -#define USB_VDMA_ERROR_F13_POS (30U) -#define USB_VDMA_ERROR_F13_LEN (1U) -#define USB_VDMA_ERROR_F13_MSK (((1U << USB_VDMA_ERROR_F13_LEN) - 1) << USB_VDMA_ERROR_F13_POS) -#define USB_VDMA_ERROR_F13_UMSK (~(((1U << USB_VDMA_ERROR_F13_LEN) - 1) << USB_VDMA_ERROR_F13_POS)) -#define USB_VDMA_ERROR_F14 USB_VDMA_ERROR_F14 -#define USB_VDMA_ERROR_F14_POS (31U) -#define USB_VDMA_ERROR_F14_LEN (1U) -#define USB_VDMA_ERROR_F14_MSK (((1U << USB_VDMA_ERROR_F14_LEN) - 1) << USB_VDMA_ERROR_F14_POS) -#define USB_VDMA_ERROR_F14_UMSK (~(((1U << USB_VDMA_ERROR_F14_LEN) - 1) << USB_VDMA_ERROR_F14_POS)) - -/* 0x32C : DEV_MISG3 */ -#define USB_DEV_MISG3_OFFSET (0x32C) -#define USB_MVDMA_CMPLT_CXF USB_MVDMA_CMPLT_CXF -#define USB_MVDMA_CMPLT_CXF_POS (0U) -#define USB_MVDMA_CMPLT_CXF_LEN (1U) -#define USB_MVDMA_CMPLT_CXF_MSK (((1U << USB_MVDMA_CMPLT_CXF_LEN) - 1) << USB_MVDMA_CMPLT_CXF_POS) -#define USB_MVDMA_CMPLT_CXF_UMSK (~(((1U << USB_MVDMA_CMPLT_CXF_LEN) - 1) << USB_MVDMA_CMPLT_CXF_POS)) -#define USB_MVDMA_CMPLT_F0 USB_MVDMA_CMPLT_F0 -#define USB_MVDMA_CMPLT_F0_POS (1U) -#define USB_MVDMA_CMPLT_F0_LEN (1U) -#define USB_MVDMA_CMPLT_F0_MSK (((1U << USB_MVDMA_CMPLT_F0_LEN) - 1) << USB_MVDMA_CMPLT_F0_POS) -#define USB_MVDMA_CMPLT_F0_UMSK (~(((1U << USB_MVDMA_CMPLT_F0_LEN) - 1) << USB_MVDMA_CMPLT_F0_POS)) -#define USB_MVDMA_CMPLT_F1 USB_MVDMA_CMPLT_F1 -#define USB_MVDMA_CMPLT_F1_POS (2U) -#define USB_MVDMA_CMPLT_F1_LEN (1U) -#define USB_MVDMA_CMPLT_F1_MSK (((1U << USB_MVDMA_CMPLT_F1_LEN) - 1) << USB_MVDMA_CMPLT_F1_POS) -#define USB_MVDMA_CMPLT_F1_UMSK (~(((1U << USB_MVDMA_CMPLT_F1_LEN) - 1) << USB_MVDMA_CMPLT_F1_POS)) -#define USB_MVDMA_CMPLT_F2 USB_MVDMA_CMPLT_F2 -#define USB_MVDMA_CMPLT_F2_POS (3U) -#define USB_MVDMA_CMPLT_F2_LEN (1U) -#define USB_MVDMA_CMPLT_F2_MSK (((1U << USB_MVDMA_CMPLT_F2_LEN) - 1) << USB_MVDMA_CMPLT_F2_POS) -#define USB_MVDMA_CMPLT_F2_UMSK (~(((1U << USB_MVDMA_CMPLT_F2_LEN) - 1) << USB_MVDMA_CMPLT_F2_POS)) -#define USB_MVDMA_CMPLT_F3 USB_MVDMA_CMPLT_F3 -#define USB_MVDMA_CMPLT_F3_POS (4U) -#define USB_MVDMA_CMPLT_F3_LEN (1U) -#define USB_MVDMA_CMPLT_F3_MSK (((1U << USB_MVDMA_CMPLT_F3_LEN) - 1) << USB_MVDMA_CMPLT_F3_POS) -#define USB_MVDMA_CMPLT_F3_UMSK (~(((1U << USB_MVDMA_CMPLT_F3_LEN) - 1) << USB_MVDMA_CMPLT_F3_POS)) -#define USB_MVDMA_CMPLT_F4 USB_MVDMA_CMPLT_F4 -#define USB_MVDMA_CMPLT_F4_POS (5U) -#define USB_MVDMA_CMPLT_F4_LEN (1U) -#define USB_MVDMA_CMPLT_F4_MSK (((1U << USB_MVDMA_CMPLT_F4_LEN) - 1) << USB_MVDMA_CMPLT_F4_POS) -#define USB_MVDMA_CMPLT_F4_UMSK (~(((1U << USB_MVDMA_CMPLT_F4_LEN) - 1) << USB_MVDMA_CMPLT_F4_POS)) -#define USB_MVDMA_CMPLT_F5 USB_MVDMA_CMPLT_F5 -#define USB_MVDMA_CMPLT_F5_POS (6U) -#define USB_MVDMA_CMPLT_F5_LEN (1U) -#define USB_MVDMA_CMPLT_F5_MSK (((1U << USB_MVDMA_CMPLT_F5_LEN) - 1) << USB_MVDMA_CMPLT_F5_POS) -#define USB_MVDMA_CMPLT_F5_UMSK (~(((1U << USB_MVDMA_CMPLT_F5_LEN) - 1) << USB_MVDMA_CMPLT_F5_POS)) -#define USB_MVDMA_CMPLT_F6 USB_MVDMA_CMPLT_F6 -#define USB_MVDMA_CMPLT_F6_POS (7U) -#define USB_MVDMA_CMPLT_F6_LEN (1U) -#define USB_MVDMA_CMPLT_F6_MSK (((1U << USB_MVDMA_CMPLT_F6_LEN) - 1) << USB_MVDMA_CMPLT_F6_POS) -#define USB_MVDMA_CMPLT_F6_UMSK (~(((1U << USB_MVDMA_CMPLT_F6_LEN) - 1) << USB_MVDMA_CMPLT_F6_POS)) -#define USB_MVDMA_CMPLT_F7 USB_MVDMA_CMPLT_F7 -#define USB_MVDMA_CMPLT_F7_POS (8U) -#define USB_MVDMA_CMPLT_F7_LEN (1U) -#define USB_MVDMA_CMPLT_F7_MSK (((1U << USB_MVDMA_CMPLT_F7_LEN) - 1) << USB_MVDMA_CMPLT_F7_POS) -#define USB_MVDMA_CMPLT_F7_UMSK (~(((1U << USB_MVDMA_CMPLT_F7_LEN) - 1) << USB_MVDMA_CMPLT_F7_POS)) -#define USB_MVDMA_CMPLT_F8 USB_MVDMA_CMPLT_F8 -#define USB_MVDMA_CMPLT_F8_POS (9U) -#define USB_MVDMA_CMPLT_F8_LEN (1U) -#define USB_MVDMA_CMPLT_F8_MSK (((1U << USB_MVDMA_CMPLT_F8_LEN) - 1) << USB_MVDMA_CMPLT_F8_POS) -#define USB_MVDMA_CMPLT_F8_UMSK (~(((1U << USB_MVDMA_CMPLT_F8_LEN) - 1) << USB_MVDMA_CMPLT_F8_POS)) -#define USB_MVDMA_CMPLT_F9 USB_MVDMA_CMPLT_F9 -#define USB_MVDMA_CMPLT_F9_POS (10U) -#define USB_MVDMA_CMPLT_F9_LEN (1U) -#define USB_MVDMA_CMPLT_F9_MSK (((1U << USB_MVDMA_CMPLT_F9_LEN) - 1) << USB_MVDMA_CMPLT_F9_POS) -#define USB_MVDMA_CMPLT_F9_UMSK (~(((1U << USB_MVDMA_CMPLT_F9_LEN) - 1) << USB_MVDMA_CMPLT_F9_POS)) -#define USB_MVDMA_CMPLT_F10 USB_MVDMA_CMPLT_F10 -#define USB_MVDMA_CMPLT_F10_POS (11U) -#define USB_MVDMA_CMPLT_F10_LEN (1U) -#define USB_MVDMA_CMPLT_F10_MSK (((1U << USB_MVDMA_CMPLT_F10_LEN) - 1) << USB_MVDMA_CMPLT_F10_POS) -#define USB_MVDMA_CMPLT_F10_UMSK (~(((1U << USB_MVDMA_CMPLT_F10_LEN) - 1) << USB_MVDMA_CMPLT_F10_POS)) -#define USB_MVDMA_CMPLT_F11 USB_MVDMA_CMPLT_F11 -#define USB_MVDMA_CMPLT_F11_POS (12U) -#define USB_MVDMA_CMPLT_F11_LEN (1U) -#define USB_MVDMA_CMPLT_F11_MSK (((1U << USB_MVDMA_CMPLT_F11_LEN) - 1) << USB_MVDMA_CMPLT_F11_POS) -#define USB_MVDMA_CMPLT_F11_UMSK (~(((1U << USB_MVDMA_CMPLT_F11_LEN) - 1) << USB_MVDMA_CMPLT_F11_POS)) -#define USB_MVDMA_CMPLT_F12 USB_MVDMA_CMPLT_F12 -#define USB_MVDMA_CMPLT_F12_POS (13U) -#define USB_MVDMA_CMPLT_F12_LEN (1U) -#define USB_MVDMA_CMPLT_F12_MSK (((1U << USB_MVDMA_CMPLT_F12_LEN) - 1) << USB_MVDMA_CMPLT_F12_POS) -#define USB_MVDMA_CMPLT_F12_UMSK (~(((1U << USB_MVDMA_CMPLT_F12_LEN) - 1) << USB_MVDMA_CMPLT_F12_POS)) -#define USB_MVDMA_CMPLT_F13 USB_MVDMA_CMPLT_F13 -#define USB_MVDMA_CMPLT_F13_POS (14U) -#define USB_MVDMA_CMPLT_F13_LEN (1U) -#define USB_MVDMA_CMPLT_F13_MSK (((1U << USB_MVDMA_CMPLT_F13_LEN) - 1) << USB_MVDMA_CMPLT_F13_POS) -#define USB_MVDMA_CMPLT_F13_UMSK (~(((1U << USB_MVDMA_CMPLT_F13_LEN) - 1) << USB_MVDMA_CMPLT_F13_POS)) -#define USB_MVDMA_CMPLT_F14 USB_MVDMA_CMPLT_F14 -#define USB_MVDMA_CMPLT_F14_POS (15U) -#define USB_MVDMA_CMPLT_F14_LEN (1U) -#define USB_MVDMA_CMPLT_F14_MSK (((1U << USB_MVDMA_CMPLT_F14_LEN) - 1) << USB_MVDMA_CMPLT_F14_POS) -#define USB_MVDMA_CMPLT_F14_UMSK (~(((1U << USB_MVDMA_CMPLT_F14_LEN) - 1) << USB_MVDMA_CMPLT_F14_POS)) -#define USB_MVDMA_ERROR_CXF USB_MVDMA_ERROR_CXF -#define USB_MVDMA_ERROR_CXF_POS (16U) -#define USB_MVDMA_ERROR_CXF_LEN (1U) -#define USB_MVDMA_ERROR_CXF_MSK (((1U << USB_MVDMA_ERROR_CXF_LEN) - 1) << USB_MVDMA_ERROR_CXF_POS) -#define USB_MVDMA_ERROR_CXF_UMSK (~(((1U << USB_MVDMA_ERROR_CXF_LEN) - 1) << USB_MVDMA_ERROR_CXF_POS)) -#define USB_MVDMA_ERROR_F0 USB_MVDMA_ERROR_F0 -#define USB_MVDMA_ERROR_F0_POS (17U) -#define USB_MVDMA_ERROR_F0_LEN (1U) -#define USB_MVDMA_ERROR_F0_MSK (((1U << USB_MVDMA_ERROR_F0_LEN) - 1) << USB_MVDMA_ERROR_F0_POS) -#define USB_MVDMA_ERROR_F0_UMSK (~(((1U << USB_MVDMA_ERROR_F0_LEN) - 1) << USB_MVDMA_ERROR_F0_POS)) -#define USB_MVDMA_ERROR_F1 USB_MVDMA_ERROR_F1 -#define USB_MVDMA_ERROR_F1_POS (18U) -#define USB_MVDMA_ERROR_F1_LEN (1U) -#define USB_MVDMA_ERROR_F1_MSK (((1U << USB_MVDMA_ERROR_F1_LEN) - 1) << USB_MVDMA_ERROR_F1_POS) -#define USB_MVDMA_ERROR_F1_UMSK (~(((1U << USB_MVDMA_ERROR_F1_LEN) - 1) << USB_MVDMA_ERROR_F1_POS)) -#define USB_MVDMA_ERROR_F2 USB_MVDMA_ERROR_F2 -#define USB_MVDMA_ERROR_F2_POS (19U) -#define USB_MVDMA_ERROR_F2_LEN (1U) -#define USB_MVDMA_ERROR_F2_MSK (((1U << USB_MVDMA_ERROR_F2_LEN) - 1) << USB_MVDMA_ERROR_F2_POS) -#define USB_MVDMA_ERROR_F2_UMSK (~(((1U << USB_MVDMA_ERROR_F2_LEN) - 1) << USB_MVDMA_ERROR_F2_POS)) -#define USB_MVDMA_ERROR_F3 USB_MVDMA_ERROR_F3 -#define USB_MVDMA_ERROR_F3_POS (20U) -#define USB_MVDMA_ERROR_F3_LEN (1U) -#define USB_MVDMA_ERROR_F3_MSK (((1U << USB_MVDMA_ERROR_F3_LEN) - 1) << USB_MVDMA_ERROR_F3_POS) -#define USB_MVDMA_ERROR_F3_UMSK (~(((1U << USB_MVDMA_ERROR_F3_LEN) - 1) << USB_MVDMA_ERROR_F3_POS)) -#define USB_MVDMA_ERROR_F4 USB_MVDMA_ERROR_F4 -#define USB_MVDMA_ERROR_F4_POS (21U) -#define USB_MVDMA_ERROR_F4_LEN (1U) -#define USB_MVDMA_ERROR_F4_MSK (((1U << USB_MVDMA_ERROR_F4_LEN) - 1) << USB_MVDMA_ERROR_F4_POS) -#define USB_MVDMA_ERROR_F4_UMSK (~(((1U << USB_MVDMA_ERROR_F4_LEN) - 1) << USB_MVDMA_ERROR_F4_POS)) -#define USB_MVDMA_ERROR_F5 USB_MVDMA_ERROR_F5 -#define USB_MVDMA_ERROR_F5_POS (22U) -#define USB_MVDMA_ERROR_F5_LEN (1U) -#define USB_MVDMA_ERROR_F5_MSK (((1U << USB_MVDMA_ERROR_F5_LEN) - 1) << USB_MVDMA_ERROR_F5_POS) -#define USB_MVDMA_ERROR_F5_UMSK (~(((1U << USB_MVDMA_ERROR_F5_LEN) - 1) << USB_MVDMA_ERROR_F5_POS)) -#define USB_MVDMA_ERROR_F6 USB_MVDMA_ERROR_F6 -#define USB_MVDMA_ERROR_F6_POS (23U) -#define USB_MVDMA_ERROR_F6_LEN (1U) -#define USB_MVDMA_ERROR_F6_MSK (((1U << USB_MVDMA_ERROR_F6_LEN) - 1) << USB_MVDMA_ERROR_F6_POS) -#define USB_MVDMA_ERROR_F6_UMSK (~(((1U << USB_MVDMA_ERROR_F6_LEN) - 1) << USB_MVDMA_ERROR_F6_POS)) -#define USB_MVDMA_ERROR_F7 USB_MVDMA_ERROR_F7 -#define USB_MVDMA_ERROR_F7_POS (24U) -#define USB_MVDMA_ERROR_F7_LEN (1U) -#define USB_MVDMA_ERROR_F7_MSK (((1U << USB_MVDMA_ERROR_F7_LEN) - 1) << USB_MVDMA_ERROR_F7_POS) -#define USB_MVDMA_ERROR_F7_UMSK (~(((1U << USB_MVDMA_ERROR_F7_LEN) - 1) << USB_MVDMA_ERROR_F7_POS)) -#define USB_MVDMA_ERROR_F8 USB_MVDMA_ERROR_F8 -#define USB_MVDMA_ERROR_F8_POS (25U) -#define USB_MVDMA_ERROR_F8_LEN (1U) -#define USB_MVDMA_ERROR_F8_MSK (((1U << USB_MVDMA_ERROR_F8_LEN) - 1) << USB_MVDMA_ERROR_F8_POS) -#define USB_MVDMA_ERROR_F8_UMSK (~(((1U << USB_MVDMA_ERROR_F8_LEN) - 1) << USB_MVDMA_ERROR_F8_POS)) -#define USB_MVDMA_ERROR_F9 USB_MVDMA_ERROR_F9 -#define USB_MVDMA_ERROR_F9_POS (26U) -#define USB_MVDMA_ERROR_F9_LEN (1U) -#define USB_MVDMA_ERROR_F9_MSK (((1U << USB_MVDMA_ERROR_F9_LEN) - 1) << USB_MVDMA_ERROR_F9_POS) -#define USB_MVDMA_ERROR_F9_UMSK (~(((1U << USB_MVDMA_ERROR_F9_LEN) - 1) << USB_MVDMA_ERROR_F9_POS)) -#define USB_MVDMA_ERROR_F10 USB_MVDMA_ERROR_F10 -#define USB_MVDMA_ERROR_F10_POS (27U) -#define USB_MVDMA_ERROR_F10_LEN (1U) -#define USB_MVDMA_ERROR_F10_MSK (((1U << USB_MVDMA_ERROR_F10_LEN) - 1) << USB_MVDMA_ERROR_F10_POS) -#define USB_MVDMA_ERROR_F10_UMSK (~(((1U << USB_MVDMA_ERROR_F10_LEN) - 1) << USB_MVDMA_ERROR_F10_POS)) -#define USB_MVDMA_ERROR_F11 USB_MVDMA_ERROR_F11 -#define USB_MVDMA_ERROR_F11_POS (28U) -#define USB_MVDMA_ERROR_F11_LEN (1U) -#define USB_MVDMA_ERROR_F11_MSK (((1U << USB_MVDMA_ERROR_F11_LEN) - 1) << USB_MVDMA_ERROR_F11_POS) -#define USB_MVDMA_ERROR_F11_UMSK (~(((1U << USB_MVDMA_ERROR_F11_LEN) - 1) << USB_MVDMA_ERROR_F11_POS)) -#define USB_MVDMA_ERROR_F12 USB_MVDMA_ERROR_F12 -#define USB_MVDMA_ERROR_F12_POS (29U) -#define USB_MVDMA_ERROR_F12_LEN (1U) -#define USB_MVDMA_ERROR_F12_MSK (((1U << USB_MVDMA_ERROR_F12_LEN) - 1) << USB_MVDMA_ERROR_F12_POS) -#define USB_MVDMA_ERROR_F12_UMSK (~(((1U << USB_MVDMA_ERROR_F12_LEN) - 1) << USB_MVDMA_ERROR_F12_POS)) -#define USB_MVDMA_ERROR_F13 USB_MVDMA_ERROR_F13 -#define USB_MVDMA_ERROR_F13_POS (30U) -#define USB_MVDMA_ERROR_F13_LEN (1U) -#define USB_MVDMA_ERROR_F13_MSK (((1U << USB_MVDMA_ERROR_F13_LEN) - 1) << USB_MVDMA_ERROR_F13_POS) -#define USB_MVDMA_ERROR_F13_UMSK (~(((1U << USB_MVDMA_ERROR_F13_LEN) - 1) << USB_MVDMA_ERROR_F13_POS)) -#define USB_MVDMA_ERROR_F14 USB_MVDMA_ERROR_F14 -#define USB_MVDMA_ERROR_F14_POS (31U) -#define USB_MVDMA_ERROR_F14_LEN (1U) -#define USB_MVDMA_ERROR_F14_MSK (((1U << USB_MVDMA_ERROR_F14_LEN) - 1) << USB_MVDMA_ERROR_F14_POS) -#define USB_MVDMA_ERROR_F14_UMSK (~(((1U << USB_MVDMA_ERROR_F14_LEN) - 1) << USB_MVDMA_ERROR_F14_POS)) - -/* 0x330 : VDMA_CTRL */ -#define USB_VDMA_CTRL_OFFSET (0x330) -#define USB_VDMA_EN USB_VDMA_EN -#define USB_VDMA_EN_POS (0U) -#define USB_VDMA_EN_LEN (1U) -#define USB_VDMA_EN_MSK (((1U << USB_VDMA_EN_LEN) - 1) << USB_VDMA_EN_POS) -#define USB_VDMA_EN_UMSK (~(((1U << USB_VDMA_EN_LEN) - 1) << USB_VDMA_EN_POS)) - -/* 0x334 : LPM_CAP */ -#define USB_LPM_CAP_OFFSET (0x334) -#define USB_LPM_WAKEUP_EN USB_LPM_WAKEUP_EN -#define USB_LPM_WAKEUP_EN_POS (0U) -#define USB_LPM_WAKEUP_EN_LEN (1U) -#define USB_LPM_WAKEUP_EN_MSK (((1U << USB_LPM_WAKEUP_EN_LEN) - 1) << USB_LPM_WAKEUP_EN_POS) -#define USB_LPM_WAKEUP_EN_UMSK (~(((1U << USB_LPM_WAKEUP_EN_LEN) - 1) << USB_LPM_WAKEUP_EN_POS)) - -/* 0x338 : DEV_ISG4 */ -#define USB_DEV_ISG4_OFFSET (0x338) -#define USB_L1_INT USB_L1_INT -#define USB_L1_INT_POS (0U) -#define USB_L1_INT_LEN (1U) -#define USB_L1_INT_MSK (((1U << USB_L1_INT_LEN) - 1) << USB_L1_INT_POS) -#define USB_L1_INT_UMSK (~(((1U << USB_L1_INT_LEN) - 1) << USB_L1_INT_POS)) -#define USB_VDMA_CMPLT_F15 USB_VDMA_CMPLT_F15 -#define USB_VDMA_CMPLT_F15_POS (16U) -#define USB_VDMA_CMPLT_F15_LEN (1U) -#define USB_VDMA_CMPLT_F15_MSK (((1U << USB_VDMA_CMPLT_F15_LEN) - 1) << USB_VDMA_CMPLT_F15_POS) -#define USB_VDMA_CMPLT_F15_UMSK (~(((1U << USB_VDMA_CMPLT_F15_LEN) - 1) << USB_VDMA_CMPLT_F15_POS)) -#define USB_VDMA_ERROR_F15 USB_VDMA_ERROR_F15 -#define USB_VDMA_ERROR_F15_POS (24U) -#define USB_VDMA_ERROR_F15_LEN (1U) -#define USB_VDMA_ERROR_F15_MSK (((1U << USB_VDMA_ERROR_F15_LEN) - 1) << USB_VDMA_ERROR_F15_POS) -#define USB_VDMA_ERROR_F15_UMSK (~(((1U << USB_VDMA_ERROR_F15_LEN) - 1) << USB_VDMA_ERROR_F15_POS)) - -/* 0x33C : DEV_MISG4 */ -#define USB_DEV_MISG4_OFFSET (0x33C) -#define USB_ML1_INT USB_ML1_INT -#define USB_ML1_INT_POS (0U) -#define USB_ML1_INT_LEN (1U) -#define USB_ML1_INT_MSK (((1U << USB_ML1_INT_LEN) - 1) << USB_ML1_INT_POS) -#define USB_ML1_INT_UMSK (~(((1U << USB_ML1_INT_LEN) - 1) << USB_ML1_INT_POS)) -#define USB_MVDMA_CMPLT_F15 USB_MVDMA_CMPLT_F15 -#define USB_MVDMA_CMPLT_F15_POS (16U) -#define USB_MVDMA_CMPLT_F15_LEN (1U) -#define USB_MVDMA_CMPLT_F15_MSK (((1U << USB_MVDMA_CMPLT_F15_LEN) - 1) << USB_MVDMA_CMPLT_F15_POS) -#define USB_MVDMA_CMPLT_F15_UMSK (~(((1U << USB_MVDMA_CMPLT_F15_LEN) - 1) << USB_MVDMA_CMPLT_F15_POS)) -#define USB_MVDMA_ERROR_F15 USB_MVDMA_ERROR_F15 -#define USB_MVDMA_ERROR_F15_POS (24U) -#define USB_MVDMA_ERROR_F15_LEN (1U) -#define USB_MVDMA_ERROR_F15_MSK (((1U << USB_MVDMA_ERROR_F15_LEN) - 1) << USB_MVDMA_ERROR_F15_POS) -#define USB_MVDMA_ERROR_F15_UMSK (~(((1U << USB_MVDMA_ERROR_F15_LEN) - 1) << USB_MVDMA_ERROR_F15_POS)) - -/* 0x350 : VDMA_FnPS1 */ -#define USB_VDMA_FNPS1_OFFSET (0x350) -#define USB_VDMA_START_FN USB_VDMA_START_FN -#define USB_VDMA_START_FN_POS (0U) -#define USB_VDMA_START_FN_LEN (1U) -#define USB_VDMA_START_FN_MSK (((1U << USB_VDMA_START_FN_LEN) - 1) << USB_VDMA_START_FN_POS) -#define USB_VDMA_START_FN_UMSK (~(((1U << USB_VDMA_START_FN_LEN) - 1) << USB_VDMA_START_FN_POS)) -#define USB_VDMA_TYPE_FN USB_VDMA_TYPE_FN -#define USB_VDMA_TYPE_FN_POS (1U) -#define USB_VDMA_TYPE_FN_LEN (1U) -#define USB_VDMA_TYPE_FN_MSK (((1U << USB_VDMA_TYPE_FN_LEN) - 1) << USB_VDMA_TYPE_FN_POS) -#define USB_VDMA_TYPE_FN_UMSK (~(((1U << USB_VDMA_TYPE_FN_LEN) - 1) << USB_VDMA_TYPE_FN_POS)) -#define USB_VDMA_IO_FN USB_VDMA_IO_FN -#define USB_VDMA_IO_FN_POS (2U) -#define USB_VDMA_IO_FN_LEN (1U) -#define USB_VDMA_IO_FN_MSK (((1U << USB_VDMA_IO_FN_LEN) - 1) << USB_VDMA_IO_FN_POS) -#define USB_VDMA_IO_FN_UMSK (~(((1U << USB_VDMA_IO_FN_LEN) - 1) << USB_VDMA_IO_FN_POS)) -#define USB_VDMA_LEN_FN USB_VDMA_LEN_FN -#define USB_VDMA_LEN_FN_POS (8U) -#define USB_VDMA_LEN_FN_LEN (17U) -#define USB_VDMA_LEN_FN_MSK (((1U << USB_VDMA_LEN_FN_LEN) - 1) << USB_VDMA_LEN_FN_POS) -#define USB_VDMA_LEN_FN_UMSK (~(((1U << USB_VDMA_LEN_FN_LEN) - 1) << USB_VDMA_LEN_FN_POS)) - -/* 0x354 : VDMA_FnPS2 */ -#define USB_VDMA_FNPS2_OFFSET (0x354) -#define USB_VDMA_MADDR_FN USB_VDMA_MADDR_FN -#define USB_VDMA_MADDR_FN_POS (0U) -#define USB_VDMA_MADDR_FN_LEN (32U) -#define USB_VDMA_MADDR_FN_MSK (((1U << USB_VDMA_MADDR_FN_LEN) - 1) << USB_VDMA_MADDR_FN_POS) -#define USB_VDMA_MADDR_FN_UMSK (~(((1U << USB_VDMA_MADDR_FN_LEN) - 1) << USB_VDMA_MADDR_FN_POS)) - -struct usb_reg { - /* 0x000 : HCCAP */ - union { - struct - { - uint32_t CAPLENGTH : 8; /* [ 7: 0], None, 0x0 */ - uint32_t reserved_8_15 : 8; /* [15: 8], rsvd, 0x0 */ - uint32_t HCIVERSION : 16; /* [31:16], None, 0x0 */ - } BF; - uint32_t WORD; - } HCCAP; - - /* 0x004 : HCSPARAMS */ - union { - struct - { - uint32_t N_PORTS : 4; /* [ 3: 0], None, 0x0 */ - uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } HCSPARAMS; - - /* 0x008 : HCCPARAMS */ - union { - struct - { - uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */ - uint32_t PROG_FR_LIST_FLAG : 1; /* [ 1], None, 0x0 */ - uint32_t ASYN_SCH_PARK_CAP : 1; /* [ 2], None, 0x0 */ - uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } HCCPARAMS; - - /* 0xc reserved */ - uint8_t RESERVED0xc[4]; - - /* 0x010 : USBCMD */ - union { - struct - { - uint32_t RS : 1; /* [ 0], None, 0x0 */ - uint32_t HC_RESET : 1; /* [ 1], None, 0x0 */ - uint32_t FRL_SIZE : 2; /* [ 3: 2], None, 0x0 */ - uint32_t PSCH_EN : 1; /* [ 4], None, 0x0 */ - uint32_t ASCH_EN : 1; /* [ 5], None, 0x0 */ - uint32_t INT_OAAD : 1; /* [ 6], None, 0x0 */ - uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ - uint32_t ASYN_PK_CNT : 2; /* [ 9: 8], None, 0x0 */ - uint32_t reserved_10 : 1; /* [ 10], rsvd, 0x0 */ - uint32_t ASYN_PK_EN : 1; /* [ 11], None, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t INT_THRC : 8; /* [23:16], None, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } USBCMD; - - /* 0x014 : USBSTS */ - union { - struct - { - uint32_t USB_INT : 1; /* [ 0], None, 0x0 */ - uint32_t USBERR_INT : 1; /* [ 1], None, 0x0 */ - uint32_t PO_CHG_DET : 1; /* [ 2], None, 0x0 */ - uint32_t FRL_ROL : 1; /* [ 3], None, 0x0 */ - uint32_t H_SYSERR : 1; /* [ 4], None, 0x0 */ - uint32_t INT_OAA : 1; /* [ 5], None, 0x0 */ - uint32_t reserved_6_11 : 6; /* [11: 6], rsvd, 0x0 */ - uint32_t HCHalted : 1; /* [ 12], None, 0x0 */ - uint32_t Reclamation : 1; /* [ 13], None, 0x0 */ - uint32_t PSCH_STS : 1; /* [ 14], None, 0x0 */ - uint32_t ASCH_STS : 1; /* [ 15], None, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } USBSTS; - - /* 0x018 : USBINTR */ - union { - struct - { - uint32_t USB_INT_EN : 1; /* [ 0], None, 0x0 */ - uint32_t USBERR_INT_EN : 1; /* [ 1], None, 0x0 */ - uint32_t PO_CHG_INT_EN : 1; /* [ 2], None, 0x0 */ - uint32_t FRL_ROL_EN : 1; /* [ 3], None, 0x0 */ - uint32_t H_SYSERR_EN : 1; /* [ 4], None, 0x0 */ - uint32_t INT_OAA_EN : 1; /* [ 5], None, 0x0 */ - uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } USBINTR; - - /* 0x01C : FRINDEX */ - union { - struct - { - uint32_t FRINDEX : 14; /* [13: 0], None, 0x0 */ - uint32_t reserved_14_31 : 18; /* [31:14], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } FRINDEX; - - /* 0x20 reserved */ - uint8_t RESERVED0x20[4]; - - /* 0x024 : PERIODICLISTBASE */ - union { - struct - { - uint32_t reserved_0_11 : 12; /* [11: 0], rsvd, 0x0 */ - uint32_t PERI_BASADR : 20; /* [31:12], None, 0x0 */ - } BF; - uint32_t WORD; - } PERIODICLISTBASE; - - /* 0x028 : ASYNCLISTADDR */ - union { - struct - { - uint32_t reserved_0_4 : 5; /* [ 4: 0], rsvd, 0x0 */ - uint32_t Async_ladr : 27; /* [31: 5], None, 0x0 */ - } BF; - uint32_t WORD; - } ASYNCLISTADDR; - - /* 0x2c reserved */ - uint8_t RESERVED0x2c[4]; - - /* 0x030 : PORTSC */ - union { - struct - { - uint32_t CONN_STS : 1; /* [ 0], None, 0x0 */ - uint32_t CONN_CHG : 1; /* [ 1], None, 0x0 */ - uint32_t PO_EN : 1; /* [ 2], None, 0x0 */ - uint32_t PO_EN_CHG : 1; /* [ 3], None, 0x0 */ - uint32_t reserved_4_5 : 2; /* [ 5: 4], rsvd, 0x0 */ - uint32_t F_PO_RESM : 1; /* [ 6], None, 0x0 */ - uint32_t PO_SUSP : 1; /* [ 7], None, 0x0 */ - uint32_t PO_RESET : 1; /* [ 8], None, 0x0 */ - uint32_t reserved_9 : 1; /* [ 9], rsvd, 0x0 */ - uint32_t LINE_STS : 2; /* [11:10], None, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t PORT_TEST : 4; /* [19:16], None, 0x0 */ - uint32_t HC_TST_PKDONE : 1; /* [ 20], None, 0x0 */ - uint32_t reserved_21_31 : 11; /* [31:21], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } PORTSC; - - /* 0x34 reserved */ - uint8_t RESERVED0x34[12]; - - /* 0x040 : HCMISC */ - union { - struct - { - uint32_t ASYN_SCH_SLPT : 2; /* [ 1: 0], None, 0x0 */ - uint32_t EOF1_Time : 2; /* [ 3: 2], None, 0x0 */ - uint32_t EOF2_Time : 2; /* [ 5: 4], None, 0x0 */ - uint32_t HostPhy_Suspend : 1; /* [ 6], None, 0x0 */ - uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ - uint32_t HC_WKP_DET_EN : 1; /* [ 8], None, 0x0 */ - uint32_t HC_CONN_DET_EN : 1; /* [ 9], None, 0x0 */ - uint32_t reserved_10_31 : 22; /* [31:10], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } HCMISC; - - /* 0x044 : FS_EOF */ - union { - struct - { - uint32_t FS_EOF1_Time : 12; /* [11: 0], None, 0x0 */ - uint32_t FS_EOF1_Time_125us : 3; /* [14:12], None, 0x0 */ - uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */ - uint32_t iTDdmaSM : 4; /* [19:16], None, 0x0 */ - uint32_t iTDTravSM : 2; /* [21:20], None, 0x0 */ - uint32_t DMAdmSM : 4; /* [25:22], None, 0x0 */ - uint32_t QHTtrSM : 3; /* [28:26], None, 0x0 */ - uint32_t QHTravSM : 3; /* [31:29], None, 0x0 */ - } BF; - uint32_t WORD; - } FS_EOF; - - /* 0x048 : HS_EOF */ - union { - struct - { - uint32_t HS_EOF1_Time : 12; /* [11: 0], None, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t siTDdmaSM : 4; /* [19:16], None, 0x0 */ - uint32_t siTDTravSM : 2; /* [21:20], None, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } HS_EOF; - - /* 0x4c reserved */ - uint8_t RESERVED0x4c[52]; - - /* 0x080 : OTG_CSR */ - union { - struct - { - uint32_t B_BUS_REQ : 1; /* [ 0], None, 0x0 */ - uint32_t B_HNP_EN : 1; /* [ 1], None, 0x0 */ - uint32_t B_DSCHRG_VBUS : 1; /* [ 2], None, 0x0 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t A_BUS_REQ_HOV : 1; /* [ 4], None, 0x0 */ - uint32_t A_BUS_DROP_HOV : 1; /* [ 5], None, 0x0 */ - uint32_t A_SET_B_HNP_EN : 1; /* [ 6], None, 0x0 */ - uint32_t A_SRP_DET_EN : 1; /* [ 7], None, 0x0 */ - uint32_t A_SRP_RESP_TYP : 1; /* [ 8], None, 0x0 */ - uint32_t ID_FLT_SEL : 1; /* [ 9], None, 0x0 */ - uint32_t VBUS_FLT_SEL_HOV_POV : 1; /* [ 10], None, 0x0 */ - uint32_t HDISCON_FLT_SEL_HOV : 1; /* [ 11], None, 0x0 */ - uint32_t reserved_12 : 1; /* [ 12], rsvd, 0x0 */ - uint32_t IDPULUP_HOV_POV : 1; /* [ 13], None, 0x0 */ - uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ - uint32_t B_SESS_END_POV : 1; /* [ 16], None, 0x0 */ - uint32_t B_SESS_VLD_POV : 1; /* [ 17], None, 0x0 */ - uint32_t A_SESS_VLD : 1; /* [ 18], None, 0x0 */ - uint32_t VBUS_VLD_HOV : 1; /* [ 19], None, 0x0 */ - uint32_t CROLE_HOV_POV : 1; /* [ 20], None, 0x0 */ - uint32_t ID_HOV_POV : 1; /* [ 21], None, 0x0 */ - uint32_t SPD_TYP_HOV_POV : 2; /* [23:22], None, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } OTG_CSR; - - /* 0x084 : OTG_ISR */ - union { - struct - { - uint32_t B_SRP_DN : 1; /* [ 0], None, 0x0 */ - uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ - uint32_t A_SRP_DET : 1; /* [ 4], None, 0x0 */ - uint32_t A_VBUS_ERR_HOV : 1; /* [ 5], None, 0x0 */ - uint32_t B_SESS_END_POV : 1; /* [ 6], None, 0x0 */ - uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ - uint32_t RLCHG : 1; /* [ 8], None, 0x0 */ - uint32_t IDCHG : 1; /* [ 9], None, 0x0 */ - uint32_t OVC_HOV : 1; /* [ 10], None, 0x0 */ - uint32_t A_WAIT_CON_HOV : 1; /* [ 11], None, 0x0 */ - uint32_t APLGRMV : 1; /* [ 12], None, 0x0 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } OTG_ISR; - - /* 0x088 : OTG_IER */ - union { - struct - { - uint32_t B_SRP_DN_EN : 1; /* [ 0], None, 0x0 */ - uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ - uint32_t A_SRP_DET_EN : 1; /* [ 4], None, 0x0 */ - uint32_t A_VBUS_ERR_EN_HOV : 1; /* [ 5], None, 0x0 */ - uint32_t B_SESS_END_EN_POV : 1; /* [ 6], None, 0x0 */ - uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ - uint32_t RLCHG_EN : 1; /* [ 8], None, 0x0 */ - uint32_t IDCHG_EN : 1; /* [ 9], None, 0x0 */ - uint32_t OVC_EN_HOV : 1; /* [ 10], None, 0x0 */ - uint32_t A_WAIT_CON_EN_HOV : 1; /* [ 11], None, 0x0 */ - uint32_t APLGRMV_EN : 1; /* [ 12], None, 0x0 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } OTG_IER; - - /* 0x8c reserved */ - uint8_t RESERVED0x8c[52]; - - /* 0x0C0 : GLB_ISR */ - union { - struct - { - uint32_t DEV_INT : 1; /* [ 0], None, 0x0 */ - uint32_t OTG_INT : 1; /* [ 1], None, 0x0 */ - uint32_t HC_INT : 1; /* [ 2], None, 0x0 */ - uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } GLB_ISR; - - /* 0x0C4 : GLB_INT */ - union { - struct - { - uint32_t MDEV_INT : 1; /* [ 0], None, 0x0 */ - uint32_t MOTG_INT : 1; /* [ 1], None, 0x0 */ - uint32_t MHC_INT : 1; /* [ 2], None, 0x0 */ - uint32_t INT_POLARITY : 1; /* [ 3], None, 0x0 */ - uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } GLB_INT; - - /* 0xc8 reserved */ - uint8_t RESERVED0xc8[24]; - - /* 0x0E0 : REVISION */ - union { - struct - { - uint32_t REVISION : 32; /* [31: 0], None, 0x0 */ - } BF; - uint32_t WORD; - } REVISION; - - /* 0x0E4 : FEATURE */ - union { - struct - { - uint32_t DMABUFSIZE : 5; /* [ 4: 0], None, 0x0 */ - uint32_t FIFO_NUM : 5; /* [ 9: 5], None, 0x0 */ - uint32_t EP_NUM : 5; /* [14:10], None, 0x0 */ - uint32_t DEV_ONLY : 1; /* [ 15], None, 0x0 */ - uint32_t HOST_ONLY : 1; /* [ 16], None, 0x0 */ - uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } FEATURE; - - /* 0x0E8 : AXI_CR */ - union { - struct - { - uint32_t AXI_SGLBST : 1; /* [ 0], None, 0x0 */ - uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } AXI_CR; - - /* 0xec reserved */ - uint8_t RESERVED0xec[20]; - - /* 0x100 : DEV_CTL */ - union { - struct - { - uint32_t CAP_RMWAKUP : 1; /* [ 0], None, 0x0 */ - uint32_t HALF_SPEED_HOV : 1; /* [ 1], None, 0x0 */ - uint32_t GLINT_EN_HOV : 1; /* [ 2], None, 0x0 */ - uint32_t GOSUSP : 1; /* [ 3], None, 0x0 */ - uint32_t SFRST_HOV : 1; /* [ 4], None, 0x0 */ - uint32_t CHIP_EN_HOV : 1; /* [ 5], None, 0x0 */ - uint32_t HS_EN_HOV : 1; /* [ 6], None, 0x0 */ - uint32_t SYSBUS_WIDTH_HOV : 1; /* [ 7], None, 0x0 */ - uint32_t reserved_8 : 1; /* [ 8], rsvd, 0x0 */ - uint32_t FORCE_FS : 1; /* [ 9], None, 0x0 */ - uint32_t IDLE_DEGLITCH_HOV : 2; /* [11:10], None, 0x0 */ - uint32_t LPM_BESL_MAX : 4; /* [15:12], None, 0x0 */ - uint32_t LPM_BESL_MIN : 4; /* [19:16], None, 0x0 */ - uint32_t LPM_BESL : 4; /* [23:20], None, 0x0 */ - uint32_t reserved_24 : 1; /* [ 24], rsvd, 0x0 */ - uint32_t LPM_EN : 1; /* [ 25], None, 0x0 */ - uint32_t LPM_ACCEPT : 1; /* [ 26], None, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_CTL; - - /* 0x104 : DEV_ADR */ - union { - struct - { - uint32_t DEVADR : 7; /* [ 6: 0], None, 0x0 */ - uint32_t AFT_CONF : 1; /* [ 7], None, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_ADR; - - /* 0x108 : DEV_TST */ - union { - struct - { - uint32_t TST_CLRFF_HOV : 1; /* [ 0], None, 0x0 */ - uint32_t TST_LPCX : 1; /* [ 1], None, 0x0 */ - uint32_t TST_CLREA : 1; /* [ 2], None, 0x0 */ - uint32_t rsvd_3 : 1; /* [ 3], None, 0x0 */ - uint32_t TST_DISTO_HOV : 1; /* [ 4], None, 0x0 */ - uint32_t TST_MOD_HOV : 1; /* [ 5], None, 0x0 */ - uint32_t DISGENSOF : 1; /* [ 6], None, 0x0 */ - uint32_t TST_MOD_TYP_HOV : 1; /* [ 7], None, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_TST; - - /* 0x10C : DEV_SFN */ - union { - struct - { - uint32_t SOFN : 11; /* [10: 0], None, 0x0 */ - uint32_t USOFN : 3; /* [13:11], None, 0x0 */ - uint32_t reserved_14_31 : 18; /* [31:14], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_SFN; - - /* 0x110 : DEV_SMT */ - union { - struct - { - uint32_t SOFMT : 16; /* [15: 0], None, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_SMT; - - /* 0x114 : PHY_TST */ - union { - struct - { - uint32_t UNPLUG : 1; /* [ 0], None, 0x0 */ - uint32_t TST_JSTA : 1; /* [ 1], None, 0x0 */ - uint32_t TST_KSTA : 1; /* [ 2], None, 0x0 */ - uint32_t TST_SE0NAK : 1; /* [ 3], None, 0x0 */ - uint32_t TST_PKT : 1; /* [ 4], None, 0x0 */ - uint32_t reserved_5_31 : 27; /* [31: 5], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } PHY_TST; - - /* 0x118 : DEV_VCTL */ - union { - struct - { - uint32_t VCTL_HOV : 5; /* [ 4: 0], None, 0x0 */ - uint32_t VCTLOAD_N_HOV : 1; /* [ 5], None, 0x0 */ - uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_VCTL; - - /* 0x11C : DEV_CXCFG */ - union { - struct - { - uint32_t VSTA_HOV : 8; /* [ 7: 0], None, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_CXCFG; - - /* 0x120 : DEV_CXCFE */ - union { - struct - { - uint32_t CX_DONE : 1; /* [ 0], None, 0x0 */ - uint32_t TST_PKDONE : 1; /* [ 1], None, 0x0 */ - uint32_t CX_STL : 1; /* [ 2], None, 0x0 */ - uint32_t CX_CLR : 1; /* [ 3], None, 0x0 */ - uint32_t CX_FUL : 1; /* [ 4], None, 0x0 */ - uint32_t CX_EMP : 1; /* [ 5], None, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t F0_EMP : 1; /* [ 8], None, 0x0 */ - uint32_t F1_EMP : 1; /* [ 9], None, 0x0 */ - uint32_t F2_EMP : 1; /* [ 10], None, 0x0 */ - uint32_t F3_EMP : 1; /* [ 11], None, 0x0 */ - uint32_t F4_EMP : 1; /* [ 12], None, 0x0 */ - uint32_t F5_EMP : 1; /* [ 13], None, 0x0 */ - uint32_t F6_EMP : 1; /* [ 14], None, 0x0 */ - uint32_t F7_EMP : 1; /* [ 15], None, 0x0 */ - uint32_t F8_EMP : 1; /* [ 16], None, 0x0 */ - uint32_t F9_EMP : 1; /* [ 17], None, 0x0 */ - uint32_t F10_EMP : 1; /* [ 18], None, 0x0 */ - uint32_t F11_EMP : 1; /* [ 19], None, 0x0 */ - uint32_t F12_EMP : 1; /* [ 20], None, 0x0 */ - uint32_t F13_EMP : 1; /* [ 21], None, 0x0 */ - uint32_t F14_EMP : 1; /* [ 22], None, 0x0 */ - uint32_t F15_EMP : 1; /* [ 23], None, 0x0 */ - uint32_t CX_FNT : 7; /* [30:24], None, 0x0 */ - uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_CXCFE; - - /* 0x124 : DEV_ICR */ - union { - struct - { - uint32_t IDLE_CNT : 3; /* [ 2: 0], None, 0x0 */ - uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_ICR; - - /* 0x128 reserved */ - uint8_t RESERVED0x128[8]; - - /* 0x130 : DEV_MIGR */ - union { - struct - { - uint32_t MINT_G0 : 1; /* [ 0], None, 0x0 */ - uint32_t MINT_G1 : 1; /* [ 1], None, 0x0 */ - uint32_t MINT_G2 : 1; /* [ 2], None, 0x0 */ - uint32_t MINT_G3 : 1; /* [ 3], None, 0x0 */ - uint32_t MINT_G4 : 1; /* [ 4], None, 0x0 */ - uint32_t reserved_5_31 : 27; /* [31: 5], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_MIGR; - - /* 0x134 : DEV_MISG0 */ - union { - struct - { - uint32_t MCX_SETUP_INT : 1; /* [ 0], None, 0x0 */ - uint32_t MCX_IN_INT : 1; /* [ 1], None, 0x0 */ - uint32_t MCX_OUT_INT : 1; /* [ 2], None, 0x0 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t MCX_COMFAIL_INT : 1; /* [ 4], None, 0x0 */ - uint32_t MCX_COMABORT_INT : 1; /* [ 5], None, 0x0 */ - uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_MISG0; - - /* 0x138 : DEV_MISG1 */ - union { - struct - { - uint32_t MF0_OUT_INT : 1; /* [ 0], None, 0x0 */ - uint32_t MF0_SPK_INT : 1; /* [ 1], None, 0x0 */ - uint32_t MF1_OUT_INT : 1; /* [ 2], None, 0x0 */ - uint32_t MF1_SPK_INT : 1; /* [ 3], None, 0x0 */ - uint32_t MF2_OUT_INT : 1; /* [ 4], None, 0x0 */ - uint32_t MF2_SPK_INT : 1; /* [ 5], None, 0x0 */ - uint32_t MF3_OUT_INT : 1; /* [ 6], None, 0x0 */ - uint32_t MF3_SPK_INT : 1; /* [ 7], None, 0x0 */ - uint32_t MF4_OUT_INT : 1; /* [ 8], None, 0x0 */ - uint32_t MF4_SPK_INT : 1; /* [ 9], None, 0x0 */ - uint32_t MF5_OUT_INT : 1; /* [ 10], None, 0x0 */ - uint32_t MF5_SPK_INT : 1; /* [ 11], None, 0x0 */ - uint32_t MF6_OUT_INT : 1; /* [ 12], None, 0x0 */ - uint32_t MF6_SPK_INT : 1; /* [ 13], None, 0x0 */ - uint32_t MF7_OUT_INT : 1; /* [ 14], None, 0x0 */ - uint32_t MF7_SPK_INT : 1; /* [ 15], None, 0x0 */ - uint32_t MF0_IN_INT : 1; /* [ 16], None, 0x0 */ - uint32_t MF1_IN_INT : 1; /* [ 17], None, 0x0 */ - uint32_t MF2_IN_INT : 1; /* [ 18], None, 0x0 */ - uint32_t MF3_IN_INT : 1; /* [ 19], None, 0x0 */ - uint32_t MF4_IN_INT : 1; /* [ 20], None, 0x0 */ - uint32_t MF5_IN_INT : 1; /* [ 21], None, 0x0 */ - uint32_t MF6_IN_INT : 1; /* [ 22], None, 0x0 */ - uint32_t MF7_IN_INT : 1; /* [ 23], None, 0x0 */ - uint32_t MF8_IN_INT : 1; /* [ 24], None, 0x0 */ - uint32_t MF9_IN_INT : 1; /* [ 25], None, 0x0 */ - uint32_t MF10_IN_INT : 1; /* [ 26], None, 0x0 */ - uint32_t MF11_IN_INT : 1; /* [ 27], None, 0x0 */ - uint32_t MF12_IN_INT : 1; /* [ 28], None, 0x0 */ - uint32_t MF13_IN_INT : 1; /* [ 29], None, 0x0 */ - uint32_t MF14_IN_INT : 1; /* [ 30], None, 0x0 */ - uint32_t MF15_IN_INT : 1; /* [ 31], None, 0x0 */ - } BF; - uint32_t WORD; - } DEV_MISG1; - - /* 0x13C : DEV_MISG2 */ - union { - struct - { - uint32_t MUSBRST_INT : 1; /* [ 0], None, 0x0 */ - uint32_t MSUSP_INT : 1; /* [ 1], None, 0x0 */ - uint32_t MRESM_INT : 1; /* [ 2], None, 0x0 */ - uint32_t MSEQ_ERR_INT : 1; /* [ 3], None, 0x0 */ - uint32_t MSEQ_ABORT_INT : 1; /* [ 4], None, 0x0 */ - uint32_t MTX0BYTE_INT : 1; /* [ 5], None, 0x0 */ - uint32_t MRX0BYTE_INT : 1; /* [ 6], None, 0x0 */ - uint32_t MDMA_CMPLT_HOV : 1; /* [ 7], None, 0x0 */ - uint32_t MDMA_ERROR_HOV : 1; /* [ 8], None, 0x0 */ - uint32_t MDev_Idle_HOV : 1; /* [ 9], None, 0x0 */ - uint32_t MDev_Wakeup_byVBUS : 1; /* [ 10], None, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t MF8_OUT_INT : 1; /* [ 16], None, 0x0 */ - uint32_t MF8_SPK_INT : 1; /* [ 17], None, 0x0 */ - uint32_t MF9_OUT_INT : 1; /* [ 18], None, 0x0 */ - uint32_t MF9_SPK_INT : 1; /* [ 19], None, 0x0 */ - uint32_t MF10_OUT_INT : 1; /* [ 20], None, 0x0 */ - uint32_t MF10_SPK_INT : 1; /* [ 21], None, 0x0 */ - uint32_t MF11_OUT_INT : 1; /* [ 22], None, 0x0 */ - uint32_t MF11_SPK_INT : 1; /* [ 23], None, 0x0 */ - uint32_t MF12_OUT_INT : 1; /* [ 24], None, 0x0 */ - uint32_t MF12_SPK_INT : 1; /* [ 25], None, 0x0 */ - uint32_t MF13_OUT_INT : 1; /* [ 26], None, 0x0 */ - uint32_t MF13_SPK_INT : 1; /* [ 27], None, 0x0 */ - uint32_t MF14_OUT_INT : 1; /* [ 28], None, 0x0 */ - uint32_t MF14_SPK_INT : 1; /* [ 29], None, 0x0 */ - uint32_t MF15_OUT_INT : 1; /* [ 30], None, 0x0 */ - uint32_t MF15_SPK_INT : 1; /* [ 31], None, 0x0 */ - } BF; - uint32_t WORD; - } DEV_MISG2; - - /* 0x140 : DEV_IGR */ - union { - struct - { - uint32_t INT_G0 : 1; /* [ 0], None, 0x0 */ - uint32_t INT_G1 : 1; /* [ 1], None, 0x0 */ - uint32_t INT_G2_HOV : 1; /* [ 2], None, 0x0 */ - uint32_t INT_G3 : 1; /* [ 3], None, 0x0 */ - uint32_t INT_G4 : 1; /* [ 4], None, 0x0 */ - uint32_t reserved_5_31 : 27; /* [31: 5], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_IGR; - - /* 0x144 : DEV_ISG0 */ - union { - struct - { - uint32_t CX_SETUP_INT : 1; /* [ 0], None, 0x0 */ - uint32_t CX_IN_INT : 1; /* [ 1], None, 0x0 */ - uint32_t CX_OUT_INT : 1; /* [ 2], None, 0x0 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t CX_COMFAIL_INT : 1; /* [ 4], None, 0x0 */ - uint32_t CX_COMABT_INT : 1; /* [ 5], None, 0x0 */ - uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_ISG0; - - /* 0x148 : DEV_ISG1 */ - union { - struct - { - uint32_t F0_OUT_INT : 1; /* [ 0], None, 0x0 */ - uint32_t F0_SPK_INT : 1; /* [ 1], None, 0x0 */ - uint32_t F1_OUT_INT : 1; /* [ 2], None, 0x0 */ - uint32_t F1_SPK_INT : 1; /* [ 3], None, 0x0 */ - uint32_t F2_OUT_INT : 1; /* [ 4], None, 0x0 */ - uint32_t F2_SPK_INT : 1; /* [ 5], None, 0x0 */ - uint32_t F3_OUT_INT : 1; /* [ 6], None, 0x0 */ - uint32_t F3_SPK_INT : 1; /* [ 7], None, 0x0 */ - uint32_t F4_OUT_INT : 1; /* [ 8], None, 0x0 */ - uint32_t F4_SPK_INT : 1; /* [ 9], None, 0x0 */ - uint32_t F5_OUT_INT : 1; /* [ 10], None, 0x0 */ - uint32_t F5_SPK_INT : 1; /* [ 11], None, 0x0 */ - uint32_t F6_OUT_INT : 1; /* [ 12], None, 0x0 */ - uint32_t F6_SPK_INT : 1; /* [ 13], None, 0x0 */ - uint32_t F7_OUT_INT : 1; /* [ 14], None, 0x0 */ - uint32_t F7_SPK_INT : 1; /* [ 15], None, 0x0 */ - uint32_t F0_IN_INT : 1; /* [ 16], None, 0x0 */ - uint32_t F1_IN_INT : 1; /* [ 17], None, 0x0 */ - uint32_t F2_IN_INT : 1; /* [ 18], None, 0x0 */ - uint32_t F3_IN_INT : 1; /* [ 19], None, 0x0 */ - uint32_t F4_IN_INT : 1; /* [ 20], None, 0x0 */ - uint32_t F5_IN_INT : 1; /* [ 21], None, 0x0 */ - uint32_t F6_IN_INT : 1; /* [ 22], None, 0x0 */ - uint32_t F7_IN_INT : 1; /* [ 23], None, 0x0 */ - uint32_t F8_IN_INT : 1; /* [ 24], None, 0x0 */ - uint32_t F9_IN_INT : 1; /* [ 25], None, 0x0 */ - uint32_t F10_IN_INT : 1; /* [ 26], None, 0x0 */ - uint32_t F11_IN_INT : 1; /* [ 27], None, 0x0 */ - uint32_t F12_IN_INT : 1; /* [ 28], None, 0x0 */ - uint32_t F13_IN_INT : 1; /* [ 29], None, 0x0 */ - uint32_t F14_IN_INT : 1; /* [ 30], None, 0x0 */ - uint32_t F15_IN_INT : 1; /* [ 31], None, 0x0 */ - } BF; - uint32_t WORD; - } DEV_ISG1; - - /* 0x14C : DEV_ISG2 */ - union { - struct - { - uint32_t USBRST_INT : 1; /* [ 0], None, 0x0 */ - uint32_t SUSP_INT : 1; /* [ 1], None, 0x0 */ - uint32_t RESM_INT : 1; /* [ 2], None, 0x0 */ - uint32_t ISO_SEQ_ERR_INT : 1; /* [ 3], None, 0x0 */ - uint32_t ISO_SEQ_ABORT_INT : 1; /* [ 4], None, 0x0 */ - uint32_t TX0BYTE_INT : 1; /* [ 5], None, 0x0 */ - uint32_t RX0BYTE_INT : 1; /* [ 6], None, 0x0 */ - uint32_t DMA_CMPLT_HOV : 1; /* [ 7], None, 0x0 */ - uint32_t DMA_ERROR_HOV : 1; /* [ 8], None, 0x0 */ - uint32_t Dev_Idle_HOV : 1; /* [ 9], None, 0x0 */ - uint32_t Dev_Wakeup_byVBUS : 1; /* [ 10], None, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t F8_OUT_INT : 1; /* [ 16], None, 0x0 */ - uint32_t F8_SPK_INT : 1; /* [ 17], None, 0x0 */ - uint32_t F9_OUT_INT : 1; /* [ 18], None, 0x0 */ - uint32_t F9_SPK_INT : 1; /* [ 19], None, 0x0 */ - uint32_t F10_OUT_INT : 1; /* [ 20], None, 0x0 */ - uint32_t F10_SPK_INT : 1; /* [ 21], None, 0x0 */ - uint32_t F11_OUT_INT : 1; /* [ 22], None, 0x0 */ - uint32_t F11_SPK_INT : 1; /* [ 23], None, 0x0 */ - uint32_t F12_OUT_INT : 1; /* [ 24], None, 0x0 */ - uint32_t F12_SPK_INT : 1; /* [ 25], None, 0x0 */ - uint32_t F13_OUT_INT : 1; /* [ 26], None, 0x0 */ - uint32_t F13_SPK_INT : 1; /* [ 27], None, 0x0 */ - uint32_t F14_OUT_INT : 1; /* [ 28], None, 0x0 */ - uint32_t F14_SPK_INT : 1; /* [ 29], None, 0x0 */ - uint32_t F15_OUT_INT : 1; /* [ 30], None, 0x0 */ - uint32_t F15_SPK_INT : 1; /* [ 31], None, 0x0 */ - } BF; - uint32_t WORD; - } DEV_ISG2; - - /* 0x150 : DEV_RXZ */ - union { - struct - { - uint32_t RX0BYTE_EP1 : 1; /* [ 0], None, 0x0 */ - uint32_t RX0BYTE_EP2 : 1; /* [ 1], None, 0x0 */ - uint32_t RX0BYTE_EP3 : 1; /* [ 2], None, 0x0 */ - uint32_t RX0BYTE_EP4 : 1; /* [ 3], None, 0x0 */ - uint32_t RX0BYTE_EP5 : 1; /* [ 4], None, 0x0 */ - uint32_t RX0BYTE_EP6 : 1; /* [ 5], None, 0x0 */ - uint32_t RX0BYTE_EP7 : 1; /* [ 6], None, 0x0 */ - uint32_t RX0BYTE_EP8 : 1; /* [ 7], None, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_RXZ; - - /* 0x154 : DEV_TXZ */ - union { - struct - { - uint32_t TX0BYTE_EP1 : 1; /* [ 0], None, 0x0 */ - uint32_t TX0BYTE_EP2 : 1; /* [ 1], None, 0x0 */ - uint32_t TX0BYTE_EP3 : 1; /* [ 2], None, 0x0 */ - uint32_t TX0BYTE_EP4 : 1; /* [ 3], None, 0x0 */ - uint32_t TX0BYTE_EP5 : 1; /* [ 4], None, 0x0 */ - uint32_t TX0BYTE_EP6 : 1; /* [ 5], None, 0x0 */ - uint32_t TX0BYTE_EP7 : 1; /* [ 6], None, 0x0 */ - uint32_t TX0BYTE_EP8 : 1; /* [ 7], None, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_TXZ; - - /* 0x158 : DEV_ISE */ - union { - struct - { - uint32_t ISO_ABT_ERR_EP1 : 1; /* [ 0], None, 0x0 */ - uint32_t ISO_ABT_ERR_EP2 : 1; /* [ 1], None, 0x0 */ - uint32_t ISO_ABT_ERR_EP3 : 1; /* [ 2], None, 0x0 */ - uint32_t ISO_ABT_ERR_EP4 : 1; /* [ 3], None, 0x0 */ - uint32_t ISO_ABT_ERR_EP5 : 1; /* [ 4], None, 0x0 */ - uint32_t ISO_ABT_ERR_EP6 : 1; /* [ 5], None, 0x0 */ - uint32_t ISO_ABT_ERR_EP7 : 1; /* [ 6], None, 0x0 */ - uint32_t ISO_ABT_ERR_EP8 : 1; /* [ 7], None, 0x0 */ - uint32_t reserved_8_15 : 8; /* [15: 8], rsvd, 0x0 */ - uint32_t ISO_SEQ_ERR_EP1 : 1; /* [ 16], None, 0x0 */ - uint32_t ISO_SEQ_ERR_EP2 : 1; /* [ 17], None, 0x0 */ - uint32_t ISO_SEQ_ERR_EP3 : 1; /* [ 18], None, 0x0 */ - uint32_t ISO_SEQ_ERR_EP4 : 1; /* [ 19], None, 0x0 */ - uint32_t ISO_SEQ_ERR_EP5 : 1; /* [ 20], None, 0x0 */ - uint32_t ISO_SEQ_ERR_EP6 : 1; /* [ 21], None, 0x0 */ - uint32_t ISO_SEQ_ERR_EP7 : 1; /* [ 22], None, 0x0 */ - uint32_t ISO_SEQ_ERR_EP8 : 1; /* [ 23], None, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_ISE; - - /* 0x15c reserved */ - uint8_t RESERVED0x15c[4]; - - /* 0x160 : DEV_INMPS1 */ - union { - struct - { - uint32_t MAXPS_IEP1 : 11; /* [10: 0], None, 0x0 */ - uint32_t STL_IEP1 : 1; /* [ 11], None, 0x0 */ - uint32_t RSTG_IEP1 : 1; /* [ 12], None, 0x0 */ - uint32_t TX_NUM_HBW_IEP1 : 2; /* [14:13], None, 0x0 */ - uint32_t TX0BYTE_IEP1 : 1; /* [ 15], None, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_INMPS1; - - /* 0x164 : DEV_INMPS2 */ - union { - struct - { - uint32_t MAXPS_IEP2 : 11; /* [10: 0], None, 0x0 */ - uint32_t STL_IEP2 : 1; /* [ 11], None, 0x0 */ - uint32_t RSTG_IEP2 : 1; /* [ 12], None, 0x0 */ - uint32_t TX_NUM_HBW_IEP2 : 2; /* [14:13], None, 0x0 */ - uint32_t TX0BYTE_IEP2 : 1; /* [ 15], None, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_INMPS2; - - /* 0x168 : DEV_INMPS3 */ - union { - struct - { - uint32_t MAXPS_IEP3 : 11; /* [10: 0], None, 0x0 */ - uint32_t STL_IEP3 : 1; /* [ 11], None, 0x0 */ - uint32_t RSTG_IEP3 : 1; /* [ 12], None, 0x0 */ - uint32_t TX_NUM_HBW_IEP3 : 2; /* [14:13], None, 0x0 */ - uint32_t TX0BYTE_IEP3 : 1; /* [ 15], None, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_INMPS3; - - /* 0x16C : DEV_INMPS4 */ - union { - struct - { - uint32_t MAXPS_IEP4 : 11; /* [10: 0], None, 0x0 */ - uint32_t STL_IEP4 : 1; /* [ 11], None, 0x0 */ - uint32_t RSTG_IEP4 : 1; /* [ 12], None, 0x0 */ - uint32_t TX_NUM_HBW_IEP4 : 2; /* [14:13], None, 0x0 */ - uint32_t TX0BYTE_IEP4 : 1; /* [ 15], None, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_INMPS4; - - /* 0x170 : DEV_INMPS5 */ - union { - struct - { - uint32_t MAXPS_IEP5 : 11; /* [10: 0], None, 0x0 */ - uint32_t STL_IEP5 : 1; /* [ 11], None, 0x0 */ - uint32_t RSTG_IEP5 : 1; /* [ 12], None, 0x0 */ - uint32_t TX_NUM_HBW_IEP5 : 2; /* [14:13], None, 0x0 */ - uint32_t TX0BYTE_IEP5 : 1; /* [ 15], None, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_INMPS5; - - /* 0x174 : DEV_INMPS6 */ - union { - struct - { - uint32_t MAXPS_IEP6 : 11; /* [10: 0], None, 0x0 */ - uint32_t STL_IEP6 : 1; /* [ 11], None, 0x0 */ - uint32_t RSTG_IEP6 : 1; /* [ 12], None, 0x0 */ - uint32_t TX_NUM_HBW_IEP6 : 2; /* [14:13], None, 0x0 */ - uint32_t TX0BYTE_IEP6 : 1; /* [ 15], None, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_INMPS6; - - /* 0x178 : DEV_INMPS7 */ - union { - struct - { - uint32_t MAXPS_IEP7 : 11; /* [10: 0], None, 0x0 */ - uint32_t STL_IEP7 : 1; /* [ 11], None, 0x0 */ - uint32_t RSTG_IEP7 : 1; /* [ 12], None, 0x0 */ - uint32_t TX_NUM_HBW_IEP7 : 2; /* [14:13], None, 0x0 */ - uint32_t TX0BYTE_IEP7 : 1; /* [ 15], None, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_INMPS7; - - /* 0x17C : DEV_INMPS8 */ - union { - struct - { - uint32_t MAXPS_IEP8 : 11; /* [10: 0], None, 0x0 */ - uint32_t STL_IEP8 : 1; /* [ 11], None, 0x0 */ - uint32_t RSTG_IEP8 : 1; /* [ 12], None, 0x0 */ - uint32_t TX_NUM_HBW_IEP8 : 2; /* [14:13], None, 0x0 */ - uint32_t TX0BYTE_IEP8 : 1; /* [ 15], None, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_INMPS8; - - /* 0x180 : DEV_OUTMPS1 */ - union { - struct - { - uint32_t MAXPS_OEP1 : 11; /* [10: 0], None, 0x0 */ - uint32_t STL_OEP1 : 1; /* [ 11], None, 0x0 */ - uint32_t RSTG_OEP1 : 1; /* [ 12], None, 0x0 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_OUTMPS1; - - /* 0x184 : DEV_OUTMPS2 */ - union { - struct - { - uint32_t MAXPS_OEP2 : 11; /* [10: 0], None, 0x0 */ - uint32_t STL_OEP2 : 1; /* [ 11], None, 0x0 */ - uint32_t RSTG_OEP2 : 1; /* [ 12], None, 0x0 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_OUTMPS2; - - /* 0x188 : DEV_OUTMPS3 */ - union { - struct - { - uint32_t MAXPS_OEP3 : 11; /* [10: 0], None, 0x0 */ - uint32_t STL_OEP3 : 1; /* [ 11], None, 0x0 */ - uint32_t RSTG_OEP3 : 1; /* [ 12], None, 0x0 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_OUTMPS3; - - /* 0x18C : DEV_OUTMPS4 */ - union { - struct - { - uint32_t MAXPS_OEP4 : 11; /* [10: 0], None, 0x0 */ - uint32_t STL_OEP4 : 1; /* [ 11], None, 0x0 */ - uint32_t RSTG_OEP4 : 1; /* [ 12], None, 0x0 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_OUTMPS4; - - /* 0x190 : DEV_OUTMPS5 */ - union { - struct - { - uint32_t MAXPS_OEP5 : 11; /* [10: 0], None, 0x0 */ - uint32_t STL_OEP5 : 1; /* [ 11], None, 0x0 */ - uint32_t RSTG_OEP5 : 1; /* [ 12], None, 0x0 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_OUTMPS5; - - /* 0x194 : DEV_OUTMPS6 */ - union { - struct - { - uint32_t MAXPS_OEP6 : 11; /* [10: 0], None, 0x0 */ - uint32_t STL_OEP6 : 1; /* [ 11], None, 0x0 */ - uint32_t RSTG_OEP6 : 1; /* [ 12], None, 0x0 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_OUTMPS6; - - /* 0x198 : DEV_OUTMPS7 */ - union { - struct - { - uint32_t MAXPS_OEP7 : 11; /* [10: 0], None, 0x0 */ - uint32_t STL_OEP7 : 1; /* [ 11], None, 0x0 */ - uint32_t RSTG_OEP7 : 1; /* [ 12], None, 0x0 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_OUTMPS7; - - /* 0x19C : DEV_OUTMPS8 */ - union { - struct - { - uint32_t MAXPS_OEP8 : 11; /* [10: 0], None, 0x0 */ - uint32_t STL_OEP8 : 1; /* [ 11], None, 0x0 */ - uint32_t RSTG_OEP8 : 1; /* [ 12], None, 0x0 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_OUTMPS8; - - /* 0x1A0 : DEV_EPMAP08 */ - union { - struct - { - uint32_t FNO_IEP1 : 4; /* [ 3: 0], None, 0x0 */ - uint32_t FNO_OEP1 : 4; /* [ 7: 4], None, 0x0 */ - uint32_t FNO_IEP2 : 4; /* [11: 8], None, 0x0 */ - uint32_t FNO_OEP2 : 4; /* [15:12], None, 0x0 */ - uint32_t FNO_IEP3 : 4; /* [19:16], None, 0x0 */ - uint32_t FNO_OEP3 : 4; /* [23:20], None, 0x0 */ - uint32_t FNO_IEP4 : 4; /* [27:24], None, 0x0 */ - uint32_t FNO_OEP4 : 4; /* [31:28], None, 0x0 */ - } BF; - uint32_t WORD; - } DEV_EPMAP08; - - /* 0x1A4 : DEV_EPMAP1 */ - union { - struct - { - uint32_t FNO_IEP5 : 4; /* [ 3: 0], None, 0x0 */ - uint32_t FNO_OEP5 : 4; /* [ 7: 4], None, 0x0 */ - uint32_t FNO_IEP6 : 4; /* [11: 8], None, 0x0 */ - uint32_t FNO_OEP6 : 4; /* [15:12], None, 0x0 */ - uint32_t FNO_IEP7 : 4; /* [19:16], None, 0x0 */ - uint32_t FNO_OEP7 : 4; /* [23:20], None, 0x0 */ - uint32_t FNO_IEP8 : 4; /* [27:24], None, 0x0 */ - uint32_t FNO_OEP8 : 4; /* [31:28], None, 0x0 */ - } BF; - uint32_t WORD; - } DEV_EPMAP1; - - /* 0x1A8 : DEV_FMAP */ - union { - struct - { - uint32_t EPNO_FIFO0 : 4; /* [ 3: 0], None, 0x0 */ - uint32_t Dir_FIFO0 : 2; /* [ 5: 4], None, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t EPNO_FIFO1 : 4; /* [11: 8], None, 0x0 */ - uint32_t Dir_FIFO1 : 2; /* [13:12], None, 0x0 */ - uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ - uint32_t EPNO_FIFO2 : 4; /* [19:16], None, 0x0 */ - uint32_t Dir_FIFO2 : 2; /* [21:20], None, 0x0 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t EPNO_FIFO3 : 4; /* [27:24], None, 0x0 */ - uint32_t Dir_FIFO3 : 2; /* [29:28], None, 0x0 */ - uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_FMAP; - - /* 0x1AC : DEV_FCFG */ - union { - struct - { - uint32_t BLK_TYP_F0 : 2; /* [ 1: 0], None, 0x0 */ - uint32_t BLKNO_F0 : 2; /* [ 3: 2], None, 0x0 */ - uint32_t BLKSZ_F0 : 1; /* [ 4], None, 0x0 */ - uint32_t EN_F0 : 1; /* [ 5], None, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t BLK_TYP_F1 : 2; /* [ 9: 8], None, 0x0 */ - uint32_t BLKNO_F1 : 2; /* [11:10], None, 0x0 */ - uint32_t BLKSZ_F1 : 1; /* [ 12], None, 0x0 */ - uint32_t EN_F1 : 1; /* [ 13], None, 0x0 */ - uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ - uint32_t BLK_TYP_F2 : 2; /* [17:16], None, 0x0 */ - uint32_t BLKNO_F2 : 2; /* [19:18], None, 0x0 */ - uint32_t BLKSZ_F2 : 1; /* [ 20], None, 0x0 */ - uint32_t EN_F2 : 1; /* [ 21], None, 0x0 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t BLK_TYP_F3 : 2; /* [25:24], None, 0x0 */ - uint32_t BLKNO_F3 : 2; /* [27:26], None, 0x0 */ - uint32_t BLKSZ_F3 : 1; /* [ 28], None, 0x0 */ - uint32_t EN_F3 : 1; /* [ 29], None, 0x0 */ - uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_FCFG; - - /* 0x1B0 : DEV_FIBC0 */ - union { - struct - { - uint32_t BC_F0 : 11; /* [10: 0], None, 0x0 */ - uint32_t rsvdp : 1; /* [ 11], None, 0x0 */ - uint32_t FFRST0_HOV : 1; /* [ 12], None, 0x0 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_FIBC0; - - /* 0x1B4 : DEV_FIBC1 */ - union { - struct - { - uint32_t BC_F1 : 11; /* [10: 0], None, 0x0 */ - uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */ - uint32_t FFRST1_HOV : 1; /* [ 12], None, 0x0 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_FIBC1; - - /* 0x1B8 : DEV_FIBC2 */ - union { - struct - { - uint32_t BC_F2 : 11; /* [10: 0], None, 0x0 */ - uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */ - uint32_t FFRST2_HOV : 1; /* [ 12], None, 0x0 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_FIBC2; - - /* 0x1BC : DEV_FIBC3 */ - union { - struct - { - uint32_t BC_F3 : 11; /* [10: 0], None, 0x0 */ - uint32_t rsvdp : 1; /* [ 11], None, 0x0 */ - uint32_t FFRST3_HOV : 1; /* [ 12], None, 0x0 */ - uint32_t rsvd_31_13 : 19; /* [31:13], None, 0x0 */ - } BF; - uint32_t WORD; - } DEV_FIBC3; - - /* 0x1C0 : DMA_TFN */ - union { - struct - { - uint32_t ACC_F0_HOV : 1; /* [ 0], None, 0x0 */ - uint32_t ACC_F1_HOV : 1; /* [ 1], None, 0x0 */ - uint32_t ACC_F2_HOV : 1; /* [ 2], None, 0x0 */ - uint32_t ACC_F3_HOV : 1; /* [ 3], None, 0x0 */ - uint32_t ACC_CXF_HOV : 1; /* [ 4], None, 0x0 */ - uint32_t ACC_F4_HOV : 1; /* [ 5], None, 0x0 */ - uint32_t ACC_F5_HOV : 1; /* [ 6], None, 0x0 */ - uint32_t ACC_F6_HOV : 1; /* [ 7], None, 0x0 */ - uint32_t ACC_F7_HOV : 1; /* [ 8], None, 0x0 */ - uint32_t ACC_F8_HOV : 1; /* [ 9], None, 0x0 */ - uint32_t ACC_F9_HOV : 1; /* [ 10], None, 0x0 */ - uint32_t ACC_F10_HOV : 1; /* [ 11], None, 0x0 */ - uint32_t ACC_F11_HOV : 1; /* [ 12], None, 0x0 */ - uint32_t ACC_F12_HOV : 1; /* [ 13], None, 0x0 */ - uint32_t ACC_F13_HOV : 1; /* [ 14], None, 0x0 */ - uint32_t ACC_F14_HOV : 1; /* [ 15], None, 0x0 */ - uint32_t ACC_F15_HOV : 1; /* [ 16], None, 0x0 */ - uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_TFN; - - /* 0x1C4 : DMA_CPS0 */ - union { - struct - { - uint32_t AWCHACHE_HOV : 4; /* [ 3: 0], None, 0x0 */ - uint32_t AWPORT_HOV : 3; /* [ 6: 4], None, 0x0 */ - uint32_t AWLOCK_HOV : 2; /* [ 8: 7], None, 0x0 */ - uint32_t ARCACHE_HOV : 4; /* [12: 9], None, 0x0 */ - uint32_t ARPORT_HOV : 3; /* [15:13], None, 0x0 */ - uint32_t ARLOCK_HOV : 2; /* [17:16], None, 0x0 */ - uint32_t BUF_LD_EN_HOV : 1; /* [ 18], None, 0x0 */ - uint32_t DST_WD_HOV : 1; /* [ 19], None, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_CPS0; - - /* 0x1C8 : DMA_CPS1 */ - union { - struct - { - uint32_t DMA_START_HOV : 1; /* [ 0], None, 0x0 */ - uint32_t DMA_TYPE_HOV : 1; /* [ 1], None, 0x0 */ - uint32_t DMA_IO_HOV : 1; /* [ 2], None, 0x0 */ - uint32_t DMA_ABORT_HOV : 1; /* [ 3], None, 0x0 */ - uint32_t CLRFIFO_DMAABORT_HOV : 1; /* [ 4], None, 0x0 */ - uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ - uint32_t DMA_LEN_HOV : 17; /* [24: 8], None, 0x0 */ - uint32_t R_HPORT_HOV : 4; /* [28:25], None, 0x0 */ - uint32_t UNDEF_LEN_BURST_HOV : 1; /* [ 29], None, 0x0 */ - uint32_t L1_WAKEUP : 1; /* [ 30], None, 0x0 */ - uint32_t DevPhy_Suspend_HOV : 1; /* [ 31], None, 0x0 */ - } BF; - uint32_t WORD; - } DMA_CPS1; - - /* 0x1CC : DMA_CPS2 */ - union { - struct - { - uint32_t DMA_MADDR_HOV : 32; /* [31: 0], None, 0x0 */ - } BF; - uint32_t WORD; - } DMA_CPS2; - - /* 0x1D0 : DMA_CPS3 */ - union { - struct - { - uint32_t SETUP_CMD_RPORT : 32; /* [31: 0], None, 0x0 */ - } BF; - uint32_t WORD; - } DMA_CPS3; - - /* 0x1D4 : DMA_CPS4 */ - union { - struct - { - uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_CPS4; - - /* 0x1D8 : DEV_FMAP2 */ - union { - struct - { - uint32_t EPNO_FIFO4 : 4; /* [ 3: 0], None, 0x0 */ - uint32_t Dir_FIFO4 : 2; /* [ 5: 4], None, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t EPNO_FIFO5 : 4; /* [11: 8], None, 0x0 */ - uint32_t Dir_FIFO5 : 2; /* [13:12], None, 0x0 */ - uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ - uint32_t EPNO_FIFO6 : 4; /* [19:16], None, 0x0 */ - uint32_t Dir_FIFO6 : 2; /* [21:20], None, 0x0 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t EPNO_FIFO7 : 4; /* [27:24], None, 0x0 */ - uint32_t Dir_FIFO7 : 2; /* [29:28], None, 0x0 */ - uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_FMAP2; - - /* 0x1DC : DEV_FCFG2 */ - union { - struct - { - uint32_t BLK_TYP_F4 : 2; /* [ 1: 0], None, 0x0 */ - uint32_t BLKNO_F4 : 2; /* [ 3: 2], None, 0x0 */ - uint32_t BLKSZ_F4 : 1; /* [ 4], None, 0x0 */ - uint32_t EN_F4 : 1; /* [ 5], None, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t BLK_TYP_F5 : 2; /* [ 9: 8], None, 0x0 */ - uint32_t BLKNO_F5 : 2; /* [11:10], None, 0x0 */ - uint32_t BLKSZ_F5 : 1; /* [ 12], None, 0x0 */ - uint32_t EN_F5 : 1; /* [ 13], None, 0x0 */ - uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ - uint32_t BLK_TYP_F6 : 2; /* [17:16], None, 0x0 */ - uint32_t BLKNO_F6 : 2; /* [19:18], None, 0x0 */ - uint32_t BLKSZ_F6 : 1; /* [ 20], None, 0x0 */ - uint32_t EN_F6 : 1; /* [ 21], None, 0x0 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t BLK_TYP_F7 : 2; /* [25:24], None, 0x0 */ - uint32_t BLKNO_F7 : 2; /* [27:26], None, 0x0 */ - uint32_t BLKSZ_F7 : 1; /* [ 28], None, 0x0 */ - uint32_t EN_F7 : 1; /* [ 29], None, 0x0 */ - uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_FCFG2; - - /* 0x1E0 : DEV_FMAP3 */ - union { - struct - { - uint32_t EPNO_FIFO8 : 4; /* [ 3: 0], None, 0x0 */ - uint32_t Dir_FIFO8 : 2; /* [ 5: 4], None, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t EPNO_FIFO9 : 4; /* [11: 8], None, 0x0 */ - uint32_t Dir_FIFO9 : 2; /* [13:12], None, 0x0 */ - uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ - uint32_t EPNO_FIFO10 : 4; /* [19:16], None, 0x0 */ - uint32_t Dir_FIFO10 : 2; /* [21:20], None, 0x0 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t EPNO_FIFO11 : 4; /* [27:24], None, 0x0 */ - uint32_t Dir_FIFO11 : 2; /* [29:28], None, 0x0 */ - uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_FMAP3; - - /* 0x1E4 : DEV_FCFG3 */ - union { - struct - { - uint32_t BLK_TYP_F8 : 2; /* [ 1: 0], None, 0x0 */ - uint32_t BLKNO_F8 : 2; /* [ 3: 2], None, 0x0 */ - uint32_t BLKSZ_F8 : 1; /* [ 4], None, 0x0 */ - uint32_t EN_F8 : 1; /* [ 5], None, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t BLK_TYP_F9 : 2; /* [ 9: 8], None, 0x0 */ - uint32_t BLKNO_F9 : 2; /* [11:10], None, 0x0 */ - uint32_t BLKSZ_F9 : 1; /* [ 12], None, 0x0 */ - uint32_t EN_F9 : 1; /* [ 13], None, 0x0 */ - uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ - uint32_t BLK_TYP_F10 : 2; /* [17:16], None, 0x0 */ - uint32_t BLKNO_F10 : 2; /* [19:18], None, 0x0 */ - uint32_t BLKSZ_F10 : 1; /* [ 20], None, 0x0 */ - uint32_t EN_F10 : 1; /* [ 21], None, 0x0 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t BLK_TYP_F11 : 2; /* [25:24], None, 0x0 */ - uint32_t BLKNO_F11 : 2; /* [27:26], None, 0x0 */ - uint32_t BLKSZ_F11 : 1; /* [ 28], None, 0x0 */ - uint32_t EN_F11 : 1; /* [ 29], None, 0x0 */ - uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_FCFG3; - - /* 0x1E8 : DEV_FMAP4 */ - union { - struct - { - uint32_t EPNO_FIFO12 : 4; /* [ 3: 0], None, 0x0 */ - uint32_t Dir_FIFO12 : 2; /* [ 5: 4], None, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t EPNO_FIFO13 : 4; /* [11: 8], None, 0x0 */ - uint32_t Dir_FIFO13 : 2; /* [13:12], None, 0x0 */ - uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ - uint32_t EPNO_FIFO14 : 4; /* [19:16], None, 0x0 */ - uint32_t Dir_FIFO14 : 2; /* [21:20], None, 0x0 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t EPNO_FIFO15 : 4; /* [27:24], None, 0x0 */ - uint32_t Dir_FIFO15 : 2; /* [29:28], None, 0x0 */ - uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_FMAP4; - - /* 0x1EC : DEV_FCFG4 */ - union { - struct - { - uint32_t BLK_TYP_F12 : 2; /* [ 1: 0], None, 0x0 */ - uint32_t BLKNO_F12 : 2; /* [ 3: 2], None, 0x0 */ - uint32_t BLKSZ_F12 : 1; /* [ 4], None, 0x0 */ - uint32_t EN_F12 : 1; /* [ 5], None, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t BLK_TYP_F13 : 2; /* [ 9: 8], None, 0x0 */ - uint32_t BLKNO_F13 : 2; /* [11:10], None, 0x0 */ - uint32_t BLKSZ_F13 : 1; /* [ 12], None, 0x0 */ - uint32_t EN_F13 : 1; /* [ 13], None, 0x0 */ - uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ - uint32_t BLK_TYP_F14 : 2; /* [17:16], None, 0x0 */ - uint32_t BLKNO_F14 : 2; /* [19:18], None, 0x0 */ - uint32_t BLKSZ_F14 : 1; /* [ 20], None, 0x0 */ - uint32_t EN_F14 : 1; /* [ 21], None, 0x0 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t BLK_TYP_F15 : 2; /* [25:24], None, 0x0 */ - uint32_t BLKNO_F15 : 2; /* [27:26], None, 0x0 */ - uint32_t BLKSZ_F15 : 1; /* [ 28], None, 0x0 */ - uint32_t EN_F15 : 1; /* [ 29], None, 0x0 */ - uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_FCFG4; - - /* 0x1F0 : DEV_FIBC4 */ - union { - struct - { - uint32_t BC_F4 : 11; /* [10: 0], None, 0x0 */ - uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */ - uint32_t FFRST4_HOV : 1; /* [ 12], None, 0x0 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_FIBC4; - - /* 0x1F4 : DEV_FIBC5 */ - union { - struct - { - uint32_t BC_F5 : 11; /* [10: 0], None, 0x0 */ - uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */ - uint32_t FFRST5_HOV : 1; /* [ 12], None, 0x0 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_FIBC5; - - /* 0x1F8 : DEV_FIBC6 */ - union { - struct - { - uint32_t BC_F6 : 11; /* [10: 0], None, 0x0 */ - uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */ - uint32_t FFRST6_HOV : 1; /* [ 12], None, 0x0 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_FIBC6; - - /* 0x1FC : DEV_FIBC7 */ - union { - struct - { - uint32_t BC_F7 : 11; /* [10: 0], None, 0x0 */ - uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */ - uint32_t FFRST7_HOV : 1; /* [ 12], None, 0x0 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_FIBC7; - - /* 0x200 reserved */ - uint8_t RESERVED0x200[256]; - - /* 0x300 : VDMA_CXFPS1 */ - union { - struct - { - uint32_t VDMA_START_CXF : 1; /* [ 0], None, 0x0 */ - uint32_t VDMA_TYPE_CXF : 1; /* [ 1], None, 0x0 */ - uint32_t VDMA_IO_CXF : 1; /* [ 2], None, 0x0 */ - uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */ - uint32_t VDMA_LEN_CXF : 17; /* [24: 8], None, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } VDMA_CXFPS1; - - /* 0x304 : None */ - union { - struct - { - uint32_t VDMA_MADDR_CXF : 32; /* [31: 0], None, 0x0 */ - } BF; - uint32_t WORD; - } VDMA_CXFPS2; - - /* 0x308 : None */ - union { - struct - { - uint32_t VDMA_START_F0 : 1; /* [ 0], None, 0x0 */ - uint32_t VDMA_TYPE_F0 : 1; /* [ 1], None, 0x0 */ - uint32_t VDMA_IO_F0 : 1; /* [ 2], None, 0x0 */ - uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */ - uint32_t VDMA_LEN_F0 : 17; /* [24: 8], None, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } VDMA_F0PS1; - - /* 0x30C : VDMA_F0PS2 */ - union { - struct - { - uint32_t VDMA_MADDR_F0 : 32; /* [31: 0], None, 0x0 */ - } BF; - uint32_t WORD; - } VDMA_F0PS2; - - /* 0x310 : VDMA_F1PS1 */ - union { - struct - { - uint32_t VDMA_START_F1 : 1; /* [ 0], None, 0x0 */ - uint32_t VDMA_TYPE_F1 : 1; /* [ 1], None, 0x0 */ - uint32_t VDMA_IO_F1 : 1; /* [ 2], None, 0x0 */ - uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */ - uint32_t VDMA_LEN_F1 : 17; /* [24: 8], None, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } VDMA_F1PS1; - - /* 0x314 : VDMA_F1PS2 */ - union { - struct - { - uint32_t VDMA_MADDR_F1 : 32; /* [31: 0], None, 0x0 */ - } BF; - uint32_t WORD; - } VDMA_F1PS2; - - /* 0x318 : VDMA_F2PS1 */ - union { - struct - { - uint32_t VDMA_START_F2 : 1; /* [ 0], None, 0x0 */ - uint32_t VDMA_TYPE_F2 : 1; /* [ 1], None, 0x0 */ - uint32_t VDMA_IO_F2 : 1; /* [ 2], None, 0x0 */ - uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */ - uint32_t VDMA_LEN_F2 : 17; /* [24: 8], None, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } VDMA_F2PS1; - - /* 0x31C : VDMA_F2PS2 */ - union { - struct - { - uint32_t VDMA_MADDR_F2 : 32; /* [31: 0], None, 0x0 */ - } BF; - uint32_t WORD; - } VDMA_F2PS2; - - /* 0x320 : VDMA_F3PS1 */ - union { - struct - { - uint32_t VDMA_START_F3 : 1; /* [ 0], None, 0x0 */ - uint32_t VDMA_TYPE_F3 : 1; /* [ 1], None, 0x0 */ - uint32_t VDMA_IO_F3 : 1; /* [ 2], None, 0x0 */ - uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */ - uint32_t VDMA_LEN_F3 : 17; /* [24: 8], None, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } VDMA_F3PS1; - - /* 0x324 : VDMA_F3PS2 */ - union { - struct - { - uint32_t VDMA_MADDR_F3 : 32; /* [31: 0], None, 0x0 */ - } BF; - uint32_t WORD; - } VDMA_F3PS2; - - /* 0x328 : DEV_ISG3 */ - union { - struct - { - uint32_t VDMA_CMPLT_CXF : 1; /* [ 0], None, 0x0 */ - uint32_t VDMA_CMPLT_F0 : 1; /* [ 1], None, 0x0 */ - uint32_t VDMA_CMPLT_F1 : 1; /* [ 2], None, 0x0 */ - uint32_t VDMA_CMPLT_F2 : 1; /* [ 3], None, 0x0 */ - uint32_t VDMA_CMPLT_F3 : 1; /* [ 4], None, 0x0 */ - uint32_t VDMA_CMPLT_F4 : 1; /* [ 5], None, 0x0 */ - uint32_t VDMA_CMPLT_F5 : 1; /* [ 6], None, 0x0 */ - uint32_t VDMA_CMPLT_F6 : 1; /* [ 7], None, 0x0 */ - uint32_t VDMA_CMPLT_F7 : 1; /* [ 8], None, 0x0 */ - uint32_t VDMA_CMPLT_F8 : 1; /* [ 9], None, 0x0 */ - uint32_t VDMA_CMPLT_F9 : 1; /* [ 10], None, 0x0 */ - uint32_t VDMA_CMPLT_F10 : 1; /* [ 11], None, 0x0 */ - uint32_t VDMA_CMPLT_F11 : 1; /* [ 12], None, 0x0 */ - uint32_t VDMA_CMPLT_F12 : 1; /* [ 13], None, 0x0 */ - uint32_t VDMA_CMPLT_F13 : 1; /* [ 14], None, 0x0 */ - uint32_t VDMA_CMPLT_F14 : 1; /* [ 15], None, 0x0 */ - uint32_t VDMA_ERROR_CXF : 1; /* [ 16], None, 0x0 */ - uint32_t VDMA_ERROR_F0 : 1; /* [ 17], None, 0x0 */ - uint32_t VDMA_ERROR_F1 : 1; /* [ 18], None, 0x0 */ - uint32_t VDMA_ERROR_F2 : 1; /* [ 19], None, 0x0 */ - uint32_t VDMA_ERROR_F3 : 1; /* [ 20], None, 0x0 */ - uint32_t VDMA_ERROR_F4 : 1; /* [ 21], None, 0x0 */ - uint32_t VDMA_ERROR_F5 : 1; /* [ 22], None, 0x0 */ - uint32_t VDMA_ERROR_F6 : 1; /* [ 23], None, 0x0 */ - uint32_t VDMA_ERROR_F7 : 1; /* [ 24], None, 0x0 */ - uint32_t VDMA_ERROR_F8 : 1; /* [ 25], None, 0x0 */ - uint32_t VDMA_ERROR_F9 : 1; /* [ 26], None, 0x0 */ - uint32_t VDMA_ERROR_F10 : 1; /* [ 27], None, 0x0 */ - uint32_t VDMA_ERROR_F11 : 1; /* [ 28], None, 0x0 */ - uint32_t VDMA_ERROR_F12 : 1; /* [ 29], None, 0x0 */ - uint32_t VDMA_ERROR_F13 : 1; /* [ 30], None, 0x0 */ - uint32_t VDMA_ERROR_F14 : 1; /* [ 31], None, 0x0 */ - } BF; - uint32_t WORD; - } DEV_ISG3; - - /* 0x32C : DEV_MISG3 */ - union { - struct - { - uint32_t MVDMA_CMPLT_CXF : 1; /* [ 0], None, 0x0 */ - uint32_t MVDMA_CMPLT_F0 : 1; /* [ 1], None, 0x0 */ - uint32_t MVDMA_CMPLT_F1 : 1; /* [ 2], None, 0x0 */ - uint32_t MVDMA_CMPLT_F2 : 1; /* [ 3], None, 0x0 */ - uint32_t MVDMA_CMPLT_F3 : 1; /* [ 4], None, 0x0 */ - uint32_t MVDMA_CMPLT_F4 : 1; /* [ 5], None, 0x0 */ - uint32_t MVDMA_CMPLT_F5 : 1; /* [ 6], None, 0x0 */ - uint32_t MVDMA_CMPLT_F6 : 1; /* [ 7], None, 0x0 */ - uint32_t MVDMA_CMPLT_F7 : 1; /* [ 8], None, 0x0 */ - uint32_t MVDMA_CMPLT_F8 : 1; /* [ 9], None, 0x0 */ - uint32_t MVDMA_CMPLT_F9 : 1; /* [ 10], None, 0x0 */ - uint32_t MVDMA_CMPLT_F10 : 1; /* [ 11], None, 0x0 */ - uint32_t MVDMA_CMPLT_F11 : 1; /* [ 12], None, 0x0 */ - uint32_t MVDMA_CMPLT_F12 : 1; /* [ 13], None, 0x0 */ - uint32_t MVDMA_CMPLT_F13 : 1; /* [ 14], None, 0x0 */ - uint32_t MVDMA_CMPLT_F14 : 1; /* [ 15], None, 0x0 */ - uint32_t MVDMA_ERROR_CXF : 1; /* [ 16], None, 0x0 */ - uint32_t MVDMA_ERROR_F0 : 1; /* [ 17], None, 0x0 */ - uint32_t MVDMA_ERROR_F1 : 1; /* [ 18], None, 0x0 */ - uint32_t MVDMA_ERROR_F2 : 1; /* [ 19], None, 0x0 */ - uint32_t MVDMA_ERROR_F3 : 1; /* [ 20], None, 0x0 */ - uint32_t MVDMA_ERROR_F4 : 1; /* [ 21], None, 0x0 */ - uint32_t MVDMA_ERROR_F5 : 1; /* [ 22], None, 0x0 */ - uint32_t MVDMA_ERROR_F6 : 1; /* [ 23], None, 0x0 */ - uint32_t MVDMA_ERROR_F7 : 1; /* [ 24], None, 0x0 */ - uint32_t MVDMA_ERROR_F8 : 1; /* [ 25], None, 0x0 */ - uint32_t MVDMA_ERROR_F9 : 1; /* [ 26], None, 0x0 */ - uint32_t MVDMA_ERROR_F10 : 1; /* [ 27], None, 0x0 */ - uint32_t MVDMA_ERROR_F11 : 1; /* [ 28], None, 0x0 */ - uint32_t MVDMA_ERROR_F12 : 1; /* [ 29], None, 0x0 */ - uint32_t MVDMA_ERROR_F13 : 1; /* [ 30], None, 0x0 */ - uint32_t MVDMA_ERROR_F14 : 1; /* [ 31], None, 0x0 */ - } BF; - uint32_t WORD; - } DEV_MISG3; - - /* 0x330 : VDMA_CTRL */ - union { - struct - { - uint32_t VDMA_EN : 1; /* [ 0], None, 0x0 */ - uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } VDMA_CTRL; - - /* 0x334 : LPM_CAP */ - union { - struct - { - uint32_t LPM_WAKEUP_EN : 1; /* [ 0], None, 0x0 */ - uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } LPM_CAP; - - /* 0x338 : DEV_ISG4 */ - union { - struct - { - uint32_t L1_INT : 1; /* [ 0], None, 0x0 */ - uint32_t reserved_1_15 : 15; /* [15: 1], rsvd, 0x0 */ - uint32_t VDMA_CMPLT_F15 : 1; /* [ 16], None, 0x0 */ - uint32_t reserved_17_23 : 7; /* [23:17], rsvd, 0x0 */ - uint32_t VDMA_ERROR_F15 : 1; /* [ 24], None, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_ISG4; - - /* 0x33C : DEV_MISG4 */ - union { - struct - { - uint32_t ML1_INT : 1; /* [ 0], None, 0x0 */ - uint32_t reserved_1_15 : 15; /* [15: 1], rsvd, 0x0 */ - uint32_t MVDMA_CMPLT_F15 : 1; /* [ 16], None, 0x0 */ - uint32_t reserved_17_23 : 7; /* [23:17], rsvd, 0x0 */ - uint32_t MVDMA_ERROR_F15 : 1; /* [ 24], None, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_MISG4; - - /* 0x340 reserved */ - uint8_t RESERVED0x340[16]; - - /* 0x350 : VDMA_FnPS1 */ - union { - struct - { - uint32_t VDMA_START_Fn : 1; /* [ 0], None, 0x0 */ - uint32_t VDMA_TYPE_Fn : 1; /* [ 1], None, 0x0 */ - uint32_t VDMA_IO_Fn : 1; /* [ 2], None, 0x0 */ - uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */ - uint32_t VDMA_LEN_Fn : 17; /* [24: 8], None, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } VDMA_FnPS1; - - /* 0x354 : VDMA_FnPS2 */ - union { - struct - { - uint32_t VDMA_MADDR_Fn : 32; /* [31: 0], None, 0x0 */ - } BF; - uint32_t WORD; - } VDMA_FnPS2; -}; - -typedef volatile struct usb_reg usb_reg_t; - -#endif /* __USB_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/Core/Include/clic.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/Core/Include/clic.h deleted file mode 100644 index 3ea51390b8..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/Core/Include/clic.h +++ /dev/null @@ -1,21 +0,0 @@ -// See LICENSE for license details. - -#ifndef _SIFIVE_CLIC_H -#define _SIFIVE_CLIC_H - -#define CLIC_CTRL_ADDR 0x02000000UL -#define CLIC_HART0_ADDR 0x02800000UL - -#define CLIC_MSIP 0x0000 -#define CLIC_MSIP_size 0x4 -#define CLIC_MTIMECMP 0x4000 -#define CLIC_MTIMECMP_size 0x8 -#define CLIC_MTIME 0xBFF8 -#define CLIC_MTIME_size 0x8 - -#define CLIC_INTIP 0x000 -#define CLIC_INTIE 0x400 -#define CLIC_INTCFG 0x800 -#define CLIC_CFG 0xc00 - -#endif /* _SIFIVE_CLIC_H */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/Core/Include/riscv_bits.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/Core/Include/riscv_bits.h deleted file mode 100644 index 16b15bcddd..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/Core/Include/riscv_bits.h +++ /dev/null @@ -1,36 +0,0 @@ -// See LICENSE for license details. -#ifndef _RISCV_BITS_H -#define _RISCV_BITS_H - -#define likely(x) __builtin_expect((x), 1) -#define unlikely(x) __builtin_expect((x), 0) - -#define ROUNDUP(a, b) ((((a)-1) / (b) + 1) * (b)) -#define ROUNDDOWN(a, b) ((a) / (b) * (b)) - -#define MAX(a, b) ((a) > (b) ? (a) : (b)) -#define MIN(a, b) ((a) < (b) ? (a) : (b)) -#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi) - -#define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1))) -#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1)))) - -#define STR(x) XSTR(x) -#define XSTR(x) #x - -#if __riscv_xlen == 64 -#define SLL32 sllw -#define STORE sd -#define LOAD ld -#define LWU lwu -#define LOG_REGBYTES 3 -#else -#define SLL32 sll -#define STORE sw -#define LOAD lw -#define LWU lw -#define LOG_REGBYTES 2 -#endif -#define REGBYTES (1 << LOG_REGBYTES) - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/Core/Include/riscv_const.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/Core/Include/riscv_const.h deleted file mode 100644 index 109d1dff76..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/Core/Include/riscv_const.h +++ /dev/null @@ -1,18 +0,0 @@ -// See LICENSE for license details. -/* Derived from */ - -#ifndef _RISCV_CONST_H -#define _RISCV_CONST_H - -#ifdef __ASSEMBLER__ -#define _AC(X, Y) X -#define _AT(T, X) X -#else -#define _AC(X, Y) (X##Y) -#define _AT(T, X) ((T)(X)) -#endif /* !__ASSEMBLER__*/ - -#define _BITUL(x) (_AC(1, UL) << (x)) -#define _BITULL(x) (_AC(1, ULL) << (x)) - -#endif /* _NUCLEI_CONST_H */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/Core/Include/riscv_encoding.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/Core/Include/riscv_encoding.h deleted file mode 100644 index f1dbf3a185..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/Core/Include/riscv_encoding.h +++ /dev/null @@ -1,1363 +0,0 @@ -// See LICENSE for license details. - -#ifndef RISCV_CSR_ENCODING_H -#define RISCV_CSR_ENCODING_H - -#define MSTATUS_UIE 0x00000001 -#define MSTATUS_SIE 0x00000002 -#define MSTATUS_HIE 0x00000004 -#define MSTATUS_MIE 0x00000008 -#define MSTATUS_UPIE 0x00000010 -#define MSTATUS_SPIE 0x00000020 -#define MSTATUS_HPIE 0x00000040 -#define MSTATUS_MPIE 0x00000080 -#define MSTATUS_SPP 0x00000100 -#define MSTATUS_MPP 0x00001800 -#define MSTATUS_FS 0x00006000 -#define MSTATUS_XS 0x00018000 -#define MSTATUS_MPRV 0x00020000 -#define MSTATUS_SUM 0x00040000 -#define MSTATUS_MXR 0x00080000 -#define MSTATUS_VM 0x1F000000 -#define MSTATUS32_SD 0x80000000 -#define MSTATUS64_SD 0x8000000000000000 - -#define SSTATUS_UIE 0x00000001 -#define SSTATUS_SIE 0x00000002 -#define SSTATUS_UPIE 0x00000010 -#define SSTATUS_SPIE 0x00000020 -#define SSTATUS_SPP 0x00000100 -#define SSTATUS_FS 0x00006000 -#define SSTATUS_XS 0x00018000 -#define SSTATUS_PUM 0x00040000 -#define SSTATUS32_SD 0x80000000 -#define SSTATUS64_SD 0x8000000000000000 - -#define DCSR_XDEBUGVER (3U << 30) -#define DCSR_NDRESET (1 << 29) -#define DCSR_FULLRESET (1 << 28) -#define DCSR_EBREAKM (1 << 15) -#define DCSR_EBREAKH (1 << 14) -#define DCSR_EBREAKS (1 << 13) -#define DCSR_EBREAKU (1 << 12) -#define DCSR_STOPCYCLE (1 << 10) -#define DCSR_STOPTIME (1 << 9) -#define DCSR_CAUSE (7 << 6) -#define DCSR_DEBUGINT (1 << 5) -#define DCSR_HALT (1 << 3) -#define DCSR_STEP (1 << 2) -#define DCSR_PRV (3 << 0) - -#define DCSR_CAUSE_NONE 0 -#define DCSR_CAUSE_SWBP 1 -#define DCSR_CAUSE_HWBP 2 -#define DCSR_CAUSE_DEBUGINT 3 -#define DCSR_CAUSE_STEP 4 -#define DCSR_CAUSE_HALT 5 - -#define MCONTROL_TYPE(xlen) (0xfULL << ((xlen)-4)) -#define MCONTROL_DMODE(xlen) (1ULL << ((xlen)-5)) -#define MCONTROL_MASKMAX(xlen) (0x3fULL << ((xlen)-11)) - -#define MCONTROL_SELECT (1 << 19) -#define MCONTROL_TIMING (1 << 18) -#define MCONTROL_ACTION (0x3f << 12) -#define MCONTROL_CHAIN (1 << 11) -#define MCONTROL_MATCH (0xf << 7) -#define MCONTROL_M (1 << 6) -#define MCONTROL_H (1 << 5) -#define MCONTROL_S (1 << 4) -#define MCONTROL_U (1 << 3) -#define MCONTROL_EXECUTE (1 << 2) -#define MCONTROL_STORE (1 << 1) -#define MCONTROL_LOAD (1 << 0) - -#define MCONTROL_TYPE_NONE 0 -#define MCONTROL_TYPE_MATCH 2 - -#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 -#define MCONTROL_ACTION_DEBUG_MODE 1 -#define MCONTROL_ACTION_TRACE_START 2 -#define MCONTROL_ACTION_TRACE_STOP 3 -#define MCONTROL_ACTION_TRACE_EMIT 4 - -#define MCONTROL_MATCH_EQUAL 0 -#define MCONTROL_MATCH_NAPOT 1 -#define MCONTROL_MATCH_GE 2 -#define MCONTROL_MATCH_LT 3 -#define MCONTROL_MATCH_MASK_LOW 4 -#define MCONTROL_MATCH_MASK_HIGH 5 - -#define MIP_SSIP (1 << IRQ_S_SOFT) -#define MIP_HSIP (1 << IRQ_H_SOFT) -#define MIP_MSIP (1 << IRQ_M_SOFT) -#define MIP_STIP (1 << IRQ_S_TIMER) -#define MIP_HTIP (1 << IRQ_H_TIMER) -#define MIP_MTIP (1 << IRQ_M_TIMER) -#define MIP_SEIP (1 << IRQ_S_EXT) -#define MIP_HEIP (1 << IRQ_H_EXT) -#define MIP_MEIP (1 << IRQ_M_EXT) - -#define MIE_SSIE MIP_SSIP -#define MIE_HSIE MIP_HSIP -#define MIE_MSIE MIP_MSIP -#define MIE_STIE MIP_STIP -#define MIE_HTIE MIP_HTIP -#define MIE_MTIE MIP_MTIP -#define MIE_SEIE MIP_SEIP -#define MIE_HEIE MIP_HEIP -#define MIE_MEIE MIP_MEIP - -#define SIP_SSIP MIP_SSIP -#define SIP_STIP MIP_STIP - -#define PRV_U 0 -#define PRV_S 1 -#define PRV_H 2 -#define PRV_M 3 - -#define VM_MBARE 0 -#define VM_MBB 1 -#define VM_MBBID 2 -#define VM_SV32 8 -#define VM_SV39 9 -#define VM_SV48 10 - -#define IRQ_S_SOFT 1 -#define IRQ_H_SOFT 2 -#define IRQ_M_SOFT 3 -#define IRQ_S_TIMER 5 -#define IRQ_H_TIMER 6 -#define IRQ_M_TIMER 7 -#define IRQ_S_EXT 9 -#define IRQ_H_EXT 10 -#define IRQ_M_EXT 11 -#define IRQ_COP 12 -#define IRQ_HOST 13 - -#define DEFAULT_RSTVEC 0x00001000 -#define DEFAULT_NMIVEC 0x00001004 -#define DEFAULT_MTVEC 0x00001010 -#define CONFIG_STRING_ADDR 0x0000100C -#define EXT_IO_BASE 0x40000000 -#define DRAM_BASE 0x80000000 - -// page table entry (PTE) fields -#define PTE_V 0x001 // Valid -#define PTE_R 0x002 // Read -#define PTE_W 0x004 // Write -#define PTE_X 0x008 // Execute -#define PTE_U 0x010 // User -#define PTE_G 0x020 // Global -#define PTE_A 0x040 // Accessed -#define PTE_D 0x080 // Dirty -#define PTE_SOFT 0x300 // Reserved for Software - -#define PTE_PPN_SHIFT 10 - -#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) - -#ifdef __riscv - -#ifdef __riscv64 -#define MSTATUS_SD MSTATUS64_SD -#define SSTATUS_SD SSTATUS64_SD -#define RISCV_PGLEVEL_BITS 9 -#else -#define MSTATUS_SD MSTATUS32_SD -#define SSTATUS_SD SSTATUS32_SD -#define RISCV_PGLEVEL_BITS 10 -#endif -#define RISCV_PGSHIFT 12 -#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) - -#ifndef __ASSEMBLER__ - -#ifdef __GNUC__ - -#define asm __asm - -#define read_fpu(reg) ({ unsigned long __tmp; \ - asm volatile ("fmv.x.w %0, " #reg : "=r"(__tmp)); \ - __tmp; }) - -#define write_fpu(reg, val) ({ \ - if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ - asm volatile ("fmv.w.x " #reg ", %0" :: "i"(val)); \ - else \ - asm volatile ("fmv.w.x " #reg ", %0" :: "r"(val)); }) - -#define read_csr(reg) ({ unsigned long __tmp; \ - asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ - __tmp; }) - -#define write_csr(reg, val) ({ \ - if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ - asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ - else \ - asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) - -#define swap_csr(reg, val) ({ unsigned long __tmp; \ - if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ - asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \ - else \ - asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \ - __tmp; }) - -#define set_csr(reg, bit) ({ unsigned long __tmp; \ - if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ - asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ - else \ - asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ - __tmp; }) - -#define clear_csr(reg, bit) ({ unsigned long __tmp; \ - if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ - asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ - else \ - asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ - __tmp; }) - -#define rdtime() read_csr(time) -#define rdcycle() read_csr(cycle) -#define rdinstret() read_csr(instret) - -#endif - -#endif - -#endif - -#endif -/* Automatically generated by parse-opcodes */ -#ifndef RISCV_ENCODING_H -#define RISCV_ENCODING_H -#define MATCH_BEQ 0x63 -#define MASK_BEQ 0x707f -#define MATCH_BNE 0x1063 -#define MASK_BNE 0x707f -#define MATCH_BLT 0x4063 -#define MASK_BLT 0x707f -#define MATCH_BGE 0x5063 -#define MASK_BGE 0x707f -#define MATCH_BLTU 0x6063 -#define MASK_BLTU 0x707f -#define MATCH_BGEU 0x7063 -#define MASK_BGEU 0x707f -#define MATCH_JALR 0x67 -#define MASK_JALR 0x707f -#define MATCH_JAL 0x6f -#define MASK_JAL 0x7f -#define MATCH_LUI 0x37 -#define MASK_LUI 0x7f -#define MATCH_AUIPC 0x17 -#define MASK_AUIPC 0x7f -#define MATCH_ADDI 0x13 -#define MASK_ADDI 0x707f -#define MATCH_SLLI 0x1013 -#define MASK_SLLI 0xfc00707f -#define MATCH_SLTI 0x2013 -#define MASK_SLTI 0x707f -#define MATCH_SLTIU 0x3013 -#define MASK_SLTIU 0x707f -#define MATCH_XORI 0x4013 -#define MASK_XORI 0x707f -#define MATCH_SRLI 0x5013 -#define MASK_SRLI 0xfc00707f -#define MATCH_SRAI 0x40005013 -#define MASK_SRAI 0xfc00707f -#define MATCH_ORI 0x6013 -#define MASK_ORI 0x707f -#define MATCH_ANDI 0x7013 -#define MASK_ANDI 0x707f -#define MATCH_ADD 0x33 -#define MASK_ADD 0xfe00707f -#define MATCH_SUB 0x40000033 -#define MASK_SUB 0xfe00707f -#define MATCH_SLL 0x1033 -#define MASK_SLL 0xfe00707f -#define MATCH_SLT 0x2033 -#define MASK_SLT 0xfe00707f -#define MATCH_SLTU 0x3033 -#define MASK_SLTU 0xfe00707f -#define MATCH_XOR 0x4033 -#define MASK_XOR 0xfe00707f -#define MATCH_SRL 0x5033 -#define MASK_SRL 0xfe00707f -#define MATCH_SRA 0x40005033 -#define MASK_SRA 0xfe00707f -#define MATCH_OR 0x6033 -#define MASK_OR 0xfe00707f -#define MATCH_AND 0x7033 -#define MASK_AND 0xfe00707f -#define MATCH_ADDIW 0x1b -#define MASK_ADDIW 0x707f -#define MATCH_SLLIW 0x101b -#define MASK_SLLIW 0xfe00707f -#define MATCH_SRLIW 0x501b -#define MASK_SRLIW 0xfe00707f -#define MATCH_SRAIW 0x4000501b -#define MASK_SRAIW 0xfe00707f -#define MATCH_ADDW 0x3b -#define MASK_ADDW 0xfe00707f -#define MATCH_SUBW 0x4000003b -#define MASK_SUBW 0xfe00707f -#define MATCH_SLLW 0x103b -#define MASK_SLLW 0xfe00707f -#define MATCH_SRLW 0x503b -#define MASK_SRLW 0xfe00707f -#define MATCH_SRAW 0x4000503b -#define MASK_SRAW 0xfe00707f -#define MATCH_LB 0x3 -#define MASK_LB 0x707f -#define MATCH_LH 0x1003 -#define MASK_LH 0x707f -#define MATCH_LW 0x2003 -#define MASK_LW 0x707f -#define MATCH_LD 0x3003 -#define MASK_LD 0x707f -#define MATCH_LBU 0x4003 -#define MASK_LBU 0x707f -#define MATCH_LHU 0x5003 -#define MASK_LHU 0x707f -#define MATCH_LWU 0x6003 -#define MASK_LWU 0x707f -#define MATCH_SB 0x23 -#define MASK_SB 0x707f -#define MATCH_SH 0x1023 -#define MASK_SH 0x707f -#define MATCH_SW 0x2023 -#define MASK_SW 0x707f -#define MATCH_SD 0x3023 -#define MASK_SD 0x707f -#define MATCH_FENCE 0xf -#define MASK_FENCE 0x707f -#define MATCH_FENCE_I 0x100f -#define MASK_FENCE_I 0x707f -#define MATCH_MUL 0x2000033 -#define MASK_MUL 0xfe00707f -#define MATCH_MULH 0x2001033 -#define MASK_MULH 0xfe00707f -#define MATCH_MULHSU 0x2002033 -#define MASK_MULHSU 0xfe00707f -#define MATCH_MULHU 0x2003033 -#define MASK_MULHU 0xfe00707f -#define MATCH_DIV 0x2004033 -#define MASK_DIV 0xfe00707f -#define MATCH_DIVU 0x2005033 -#define MASK_DIVU 0xfe00707f -#define MATCH_REM 0x2006033 -#define MASK_REM 0xfe00707f -#define MATCH_REMU 0x2007033 -#define MASK_REMU 0xfe00707f -#define MATCH_MULW 0x200003b -#define MASK_MULW 0xfe00707f -#define MATCH_DIVW 0x200403b -#define MASK_DIVW 0xfe00707f -#define MATCH_DIVUW 0x200503b -#define MASK_DIVUW 0xfe00707f -#define MATCH_REMW 0x200603b -#define MASK_REMW 0xfe00707f -#define MATCH_REMUW 0x200703b -#define MASK_REMUW 0xfe00707f -#define MATCH_AMOADD_W 0x202f -#define MASK_AMOADD_W 0xf800707f -#define MATCH_AMOXOR_W 0x2000202f -#define MASK_AMOXOR_W 0xf800707f -#define MATCH_AMOOR_W 0x4000202f -#define MASK_AMOOR_W 0xf800707f -#define MATCH_AMOAND_W 0x6000202f -#define MASK_AMOAND_W 0xf800707f -#define MATCH_AMOMIN_W 0x8000202f -#define MASK_AMOMIN_W 0xf800707f -#define MATCH_AMOMAX_W 0xa000202f -#define MASK_AMOMAX_W 0xf800707f -#define MATCH_AMOMINU_W 0xc000202f -#define MASK_AMOMINU_W 0xf800707f -#define MATCH_AMOMAXU_W 0xe000202f -#define MASK_AMOMAXU_W 0xf800707f -#define MATCH_AMOSWAP_W 0x800202f -#define MASK_AMOSWAP_W 0xf800707f -#define MATCH_LR_W 0x1000202f -#define MASK_LR_W 0xf9f0707f -#define MATCH_SC_W 0x1800202f -#define MASK_SC_W 0xf800707f -#define MATCH_AMOADD_D 0x302f -#define MASK_AMOADD_D 0xf800707f -#define MATCH_AMOXOR_D 0x2000302f -#define MASK_AMOXOR_D 0xf800707f -#define MATCH_AMOOR_D 0x4000302f -#define MASK_AMOOR_D 0xf800707f -#define MATCH_AMOAND_D 0x6000302f -#define MASK_AMOAND_D 0xf800707f -#define MATCH_AMOMIN_D 0x8000302f -#define MASK_AMOMIN_D 0xf800707f -#define MATCH_AMOMAX_D 0xa000302f -#define MASK_AMOMAX_D 0xf800707f -#define MATCH_AMOMINU_D 0xc000302f -#define MASK_AMOMINU_D 0xf800707f -#define MATCH_AMOMAXU_D 0xe000302f -#define MASK_AMOMAXU_D 0xf800707f -#define MATCH_AMOSWAP_D 0x800302f -#define MASK_AMOSWAP_D 0xf800707f -#define MATCH_LR_D 0x1000302f -#define MASK_LR_D 0xf9f0707f -#define MATCH_SC_D 0x1800302f -#define MASK_SC_D 0xf800707f -#define MATCH_ECALL 0x73 -#define MASK_ECALL 0xffffffff -#define MATCH_EBREAK 0x100073 -#define MASK_EBREAK 0xffffffff -#define MATCH_URET 0x200073 -#define MASK_URET 0xffffffff -#define MATCH_SRET 0x10200073 -#define MASK_SRET 0xffffffff -#define MATCH_HRET 0x20200073 -#define MASK_HRET 0xffffffff -#define MATCH_MRET 0x30200073 -#define MASK_MRET 0xffffffff -#define MATCH_DRET 0x7b200073 -#define MASK_DRET 0xffffffff -#define MATCH_SFENCE_VM 0x10400073 -#define MASK_SFENCE_VM 0xfff07fff -#define MATCH_WFI 0x10500073 -#define MASK_WFI 0xffffffff -#define MATCH_CSRRW 0x1073 -#define MASK_CSRRW 0x707f -#define MATCH_CSRRS 0x2073 -#define MASK_CSRRS 0x707f -#define MATCH_CSRRC 0x3073 -#define MASK_CSRRC 0x707f -#define MATCH_CSRRWI 0x5073 -#define MASK_CSRRWI 0x707f -#define MATCH_CSRRSI 0x6073 -#define MASK_CSRRSI 0x707f -#define MATCH_CSRRCI 0x7073 -#define MASK_CSRRCI 0x707f -#define MATCH_FADD_S 0x53 -#define MASK_FADD_S 0xfe00007f -#define MATCH_FSUB_S 0x8000053 -#define MASK_FSUB_S 0xfe00007f -#define MATCH_FMUL_S 0x10000053 -#define MASK_FMUL_S 0xfe00007f -#define MATCH_FDIV_S 0x18000053 -#define MASK_FDIV_S 0xfe00007f -#define MATCH_FSGNJ_S 0x20000053 -#define MASK_FSGNJ_S 0xfe00707f -#define MATCH_FSGNJN_S 0x20001053 -#define MASK_FSGNJN_S 0xfe00707f -#define MATCH_FSGNJX_S 0x20002053 -#define MASK_FSGNJX_S 0xfe00707f -#define MATCH_FMIN_S 0x28000053 -#define MASK_FMIN_S 0xfe00707f -#define MATCH_FMAX_S 0x28001053 -#define MASK_FMAX_S 0xfe00707f -#define MATCH_FSQRT_S 0x58000053 -#define MASK_FSQRT_S 0xfff0007f -#define MATCH_FADD_D 0x2000053 -#define MASK_FADD_D 0xfe00007f -#define MATCH_FSUB_D 0xa000053 -#define MASK_FSUB_D 0xfe00007f -#define MATCH_FMUL_D 0x12000053 -#define MASK_FMUL_D 0xfe00007f -#define MATCH_FDIV_D 0x1a000053 -#define MASK_FDIV_D 0xfe00007f -#define MATCH_FSGNJ_D 0x22000053 -#define MASK_FSGNJ_D 0xfe00707f -#define MATCH_FSGNJN_D 0x22001053 -#define MASK_FSGNJN_D 0xfe00707f -#define MATCH_FSGNJX_D 0x22002053 -#define MASK_FSGNJX_D 0xfe00707f -#define MATCH_FMIN_D 0x2a000053 -#define MASK_FMIN_D 0xfe00707f -#define MATCH_FMAX_D 0x2a001053 -#define MASK_FMAX_D 0xfe00707f -#define MATCH_FCVT_S_D 0x40100053 -#define MASK_FCVT_S_D 0xfff0007f -#define MATCH_FCVT_D_S 0x42000053 -#define MASK_FCVT_D_S 0xfff0007f -#define MATCH_FSQRT_D 0x5a000053 -#define MASK_FSQRT_D 0xfff0007f -#define MATCH_FLE_S 0xa0000053 -#define MASK_FLE_S 0xfe00707f -#define MATCH_FLT_S 0xa0001053 -#define MASK_FLT_S 0xfe00707f -#define MATCH_FEQ_S 0xa0002053 -#define MASK_FEQ_S 0xfe00707f -#define MATCH_FLE_D 0xa2000053 -#define MASK_FLE_D 0xfe00707f -#define MATCH_FLT_D 0xa2001053 -#define MASK_FLT_D 0xfe00707f -#define MATCH_FEQ_D 0xa2002053 -#define MASK_FEQ_D 0xfe00707f -#define MATCH_FCVT_W_S 0xc0000053 -#define MASK_FCVT_W_S 0xfff0007f -#define MATCH_FCVT_WU_S 0xc0100053 -#define MASK_FCVT_WU_S 0xfff0007f -#define MATCH_FCVT_L_S 0xc0200053 -#define MASK_FCVT_L_S 0xfff0007f -#define MATCH_FCVT_LU_S 0xc0300053 -#define MASK_FCVT_LU_S 0xfff0007f -#define MATCH_FMV_X_S 0xe0000053 -#define MASK_FMV_X_S 0xfff0707f -#define MATCH_FCLASS_S 0xe0001053 -#define MASK_FCLASS_S 0xfff0707f -#define MATCH_FCVT_W_D 0xc2000053 -#define MASK_FCVT_W_D 0xfff0007f -#define MATCH_FCVT_WU_D 0xc2100053 -#define MASK_FCVT_WU_D 0xfff0007f -#define MATCH_FCVT_L_D 0xc2200053 -#define MASK_FCVT_L_D 0xfff0007f -#define MATCH_FCVT_LU_D 0xc2300053 -#define MASK_FCVT_LU_D 0xfff0007f -#define MATCH_FMV_X_D 0xe2000053 -#define MASK_FMV_X_D 0xfff0707f -#define MATCH_FCLASS_D 0xe2001053 -#define MASK_FCLASS_D 0xfff0707f -#define MATCH_FCVT_S_W 0xd0000053 -#define MASK_FCVT_S_W 0xfff0007f -#define MATCH_FCVT_S_WU 0xd0100053 -#define MASK_FCVT_S_WU 0xfff0007f -#define MATCH_FCVT_S_L 0xd0200053 -#define MASK_FCVT_S_L 0xfff0007f -#define MATCH_FCVT_S_LU 0xd0300053 -#define MASK_FCVT_S_LU 0xfff0007f -#define MATCH_FMV_S_X 0xf0000053 -#define MASK_FMV_S_X 0xfff0707f -#define MATCH_FCVT_D_W 0xd2000053 -#define MASK_FCVT_D_W 0xfff0007f -#define MATCH_FCVT_D_WU 0xd2100053 -#define MASK_FCVT_D_WU 0xfff0007f -#define MATCH_FCVT_D_L 0xd2200053 -#define MASK_FCVT_D_L 0xfff0007f -#define MATCH_FCVT_D_LU 0xd2300053 -#define MASK_FCVT_D_LU 0xfff0007f -#define MATCH_FMV_D_X 0xf2000053 -#define MASK_FMV_D_X 0xfff0707f -#define MATCH_FLW 0x2007 -#define MASK_FLW 0x707f -#define MATCH_FLD 0x3007 -#define MASK_FLD 0x707f -#define MATCH_FSW 0x2027 -#define MASK_FSW 0x707f -#define MATCH_FSD 0x3027 -#define MASK_FSD 0x707f -#define MATCH_FMADD_S 0x43 -#define MASK_FMADD_S 0x600007f -#define MATCH_FMSUB_S 0x47 -#define MASK_FMSUB_S 0x600007f -#define MATCH_FNMSUB_S 0x4b -#define MASK_FNMSUB_S 0x600007f -#define MATCH_FNMADD_S 0x4f -#define MASK_FNMADD_S 0x600007f -#define MATCH_FMADD_D 0x2000043 -#define MASK_FMADD_D 0x600007f -#define MATCH_FMSUB_D 0x2000047 -#define MASK_FMSUB_D 0x600007f -#define MATCH_FNMSUB_D 0x200004b -#define MASK_FNMSUB_D 0x600007f -#define MATCH_FNMADD_D 0x200004f -#define MASK_FNMADD_D 0x600007f -#define MATCH_C_NOP 0x1 -#define MASK_C_NOP 0xffff -#define MATCH_C_ADDI16SP 0x6101 -#define MASK_C_ADDI16SP 0xef83 -#define MATCH_C_JR 0x8002 -#define MASK_C_JR 0xf07f -#define MATCH_C_JALR 0x9002 -#define MASK_C_JALR 0xf07f -#define MATCH_C_EBREAK 0x9002 -#define MASK_C_EBREAK 0xffff -#define MATCH_C_LD 0x6000 -#define MASK_C_LD 0xe003 -#define MATCH_C_SD 0xe000 -#define MASK_C_SD 0xe003 -#define MATCH_C_ADDIW 0x2001 -#define MASK_C_ADDIW 0xe003 -#define MATCH_C_LDSP 0x6002 -#define MASK_C_LDSP 0xe003 -#define MATCH_C_SDSP 0xe002 -#define MASK_C_SDSP 0xe003 -#define MATCH_C_ADDI4SPN 0x0 -#define MASK_C_ADDI4SPN 0xe003 -#define MATCH_C_FLD 0x2000 -#define MASK_C_FLD 0xe003 -#define MATCH_C_LW 0x4000 -#define MASK_C_LW 0xe003 -#define MATCH_C_FLW 0x6000 -#define MASK_C_FLW 0xe003 -#define MATCH_C_FSD 0xa000 -#define MASK_C_FSD 0xe003 -#define MATCH_C_SW 0xc000 -#define MASK_C_SW 0xe003 -#define MATCH_C_FSW 0xe000 -#define MASK_C_FSW 0xe003 -#define MATCH_C_ADDI 0x1 -#define MASK_C_ADDI 0xe003 -#define MATCH_C_JAL 0x2001 -#define MASK_C_JAL 0xe003 -#define MATCH_C_LI 0x4001 -#define MASK_C_LI 0xe003 -#define MATCH_C_LUI 0x6001 -#define MASK_C_LUI 0xe003 -#define MATCH_C_SRLI 0x8001 -#define MASK_C_SRLI 0xec03 -#define MATCH_C_SRAI 0x8401 -#define MASK_C_SRAI 0xec03 -#define MATCH_C_ANDI 0x8801 -#define MASK_C_ANDI 0xec03 -#define MATCH_C_SUB 0x8c01 -#define MASK_C_SUB 0xfc63 -#define MATCH_C_XOR 0x8c21 -#define MASK_C_XOR 0xfc63 -#define MATCH_C_OR 0x8c41 -#define MASK_C_OR 0xfc63 -#define MATCH_C_AND 0x8c61 -#define MASK_C_AND 0xfc63 -#define MATCH_C_SUBW 0x9c01 -#define MASK_C_SUBW 0xfc63 -#define MATCH_C_ADDW 0x9c21 -#define MASK_C_ADDW 0xfc63 -#define MATCH_C_J 0xa001 -#define MASK_C_J 0xe003 -#define MATCH_C_BEQZ 0xc001 -#define MASK_C_BEQZ 0xe003 -#define MATCH_C_BNEZ 0xe001 -#define MASK_C_BNEZ 0xe003 -#define MATCH_C_SLLI 0x2 -#define MASK_C_SLLI 0xe003 -#define MATCH_C_FLDSP 0x2002 -#define MASK_C_FLDSP 0xe003 -#define MATCH_C_LWSP 0x4002 -#define MASK_C_LWSP 0xe003 -#define MATCH_C_FLWSP 0x6002 -#define MASK_C_FLWSP 0xe003 -#define MATCH_C_MV 0x8002 -#define MASK_C_MV 0xf003 -#define MATCH_C_ADD 0x9002 -#define MASK_C_ADD 0xf003 -#define MATCH_C_FSDSP 0xa002 -#define MASK_C_FSDSP 0xe003 -#define MATCH_C_SWSP 0xc002 -#define MASK_C_SWSP 0xe003 -#define MATCH_C_FSWSP 0xe002 -#define MASK_C_FSWSP 0xe003 -#define MATCH_CUSTOM0 0xb -#define MASK_CUSTOM0 0x707f -#define MATCH_CUSTOM0_RS1 0x200b -#define MASK_CUSTOM0_RS1 0x707f -#define MATCH_CUSTOM0_RS1_RS2 0x300b -#define MASK_CUSTOM0_RS1_RS2 0x707f -#define MATCH_CUSTOM0_RD 0x400b -#define MASK_CUSTOM0_RD 0x707f -#define MATCH_CUSTOM0_RD_RS1 0x600b -#define MASK_CUSTOM0_RD_RS1 0x707f -#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b -#define MASK_CUSTOM0_RD_RS1_RS2 0x707f -#define MATCH_CUSTOM1 0x2b -#define MASK_CUSTOM1 0x707f -#define MATCH_CUSTOM1_RS1 0x202b -#define MASK_CUSTOM1_RS1 0x707f -#define MATCH_CUSTOM1_RS1_RS2 0x302b -#define MASK_CUSTOM1_RS1_RS2 0x707f -#define MATCH_CUSTOM1_RD 0x402b -#define MASK_CUSTOM1_RD 0x707f -#define MATCH_CUSTOM1_RD_RS1 0x602b -#define MASK_CUSTOM1_RD_RS1 0x707f -#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b -#define MASK_CUSTOM1_RD_RS1_RS2 0x707f -#define MATCH_CUSTOM2 0x5b -#define MASK_CUSTOM2 0x707f -#define MATCH_CUSTOM2_RS1 0x205b -#define MASK_CUSTOM2_RS1 0x707f -#define MATCH_CUSTOM2_RS1_RS2 0x305b -#define MASK_CUSTOM2_RS1_RS2 0x707f -#define MATCH_CUSTOM2_RD 0x405b -#define MASK_CUSTOM2_RD 0x707f -#define MATCH_CUSTOM2_RD_RS1 0x605b -#define MASK_CUSTOM2_RD_RS1 0x707f -#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b -#define MASK_CUSTOM2_RD_RS1_RS2 0x707f -#define MATCH_CUSTOM3 0x7b -#define MASK_CUSTOM3 0x707f -#define MATCH_CUSTOM3_RS1 0x207b -#define MASK_CUSTOM3_RS1 0x707f -#define MATCH_CUSTOM3_RS1_RS2 0x307b -#define MASK_CUSTOM3_RS1_RS2 0x707f -#define MATCH_CUSTOM3_RD 0x407b -#define MASK_CUSTOM3_RD 0x707f -#define MATCH_CUSTOM3_RD_RS1 0x607b -#define MASK_CUSTOM3_RD_RS1 0x707f -#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b -#define MASK_CUSTOM3_RD_RS1_RS2 0x707f -#define CSR_FFLAGS 0x1 -#define CSR_FRM 0x2 -#define CSR_FCSR 0x3 -#define CSR_CYCLE 0xc00 -#define CSR_TIME 0xc01 -#define CSR_INSTRET 0xc02 -#define CSR_HPMCOUNTER3 0xc03 -#define CSR_HPMCOUNTER4 0xc04 -#define CSR_HPMCOUNTER5 0xc05 -#define CSR_HPMCOUNTER6 0xc06 -#define CSR_HPMCOUNTER7 0xc07 -#define CSR_HPMCOUNTER8 0xc08 -#define CSR_HPMCOUNTER9 0xc09 -#define CSR_HPMCOUNTER10 0xc0a -#define CSR_HPMCOUNTER11 0xc0b -#define CSR_HPMCOUNTER12 0xc0c -#define CSR_HPMCOUNTER13 0xc0d -#define CSR_HPMCOUNTER14 0xc0e -#define CSR_HPMCOUNTER15 0xc0f -#define CSR_HPMCOUNTER16 0xc10 -#define CSR_HPMCOUNTER17 0xc11 -#define CSR_HPMCOUNTER18 0xc12 -#define CSR_HPMCOUNTER19 0xc13 -#define CSR_HPMCOUNTER20 0xc14 -#define CSR_HPMCOUNTER21 0xc15 -#define CSR_HPMCOUNTER22 0xc16 -#define CSR_HPMCOUNTER23 0xc17 -#define CSR_HPMCOUNTER24 0xc18 -#define CSR_HPMCOUNTER25 0xc19 -#define CSR_HPMCOUNTER26 0xc1a -#define CSR_HPMCOUNTER27 0xc1b -#define CSR_HPMCOUNTER28 0xc1c -#define CSR_HPMCOUNTER29 0xc1d -#define CSR_HPMCOUNTER30 0xc1e -#define CSR_HPMCOUNTER31 0xc1f -#define CSR_SSTATUS 0x100 -#define CSR_SIE 0x104 -#define CSR_STVEC 0x105 -#define CSR_SSCRATCH 0x140 -#define CSR_SEPC 0x141 -#define CSR_SCAUSE 0x142 -#define CSR_SBADADDR 0x143 -#define CSR_SIP 0x144 -#define CSR_SPTBR 0x180 -#define CSR_MSTATUS 0x300 -#define CSR_MISA 0x301 -#define CSR_MEDELEG 0x302 -#define CSR_MIDELEG 0x303 -#define CSR_MIE 0x304 -#define CSR_MTVEC 0x305 -#define CSR_MCOUNTEREN 0x306 -#define CSR_MSCRATCH 0x340 -#define CSR_MEPC 0x341 -#define CSR_MCAUSE 0x342 -#define CSR_MBADADDR 0x343 -#define CSR_MIP 0x344 -#define CSR_TSELECT 0x7a0 -#define CSR_TDATA1 0x7a1 -#define CSR_TDATA2 0x7a2 -#define CSR_TDATA3 0x7a3 -#define CSR_DCSR 0x7b0 -#define CSR_DPC 0x7b1 -#define CSR_DSCRATCH 0x7b2 -#define CSR_MCYCLE 0xb00 -#define CSR_MINSTRET 0xb02 -#define CSR_MHPMCOUNTER3 0xb03 -#define CSR_MHPMCOUNTER4 0xb04 -#define CSR_MHPMCOUNTER5 0xb05 -#define CSR_MHPMCOUNTER6 0xb06 -#define CSR_MHPMCOUNTER7 0xb07 -#define CSR_MHPMCOUNTER8 0xb08 -#define CSR_MHPMCOUNTER9 0xb09 -#define CSR_MHPMCOUNTER10 0xb0a -#define CSR_MHPMCOUNTER11 0xb0b -#define CSR_MHPMCOUNTER12 0xb0c -#define CSR_MHPMCOUNTER13 0xb0d -#define CSR_MHPMCOUNTER14 0xb0e -#define CSR_MHPMCOUNTER15 0xb0f -#define CSR_MHPMCOUNTER16 0xb10 -#define CSR_MHPMCOUNTER17 0xb11 -#define CSR_MHPMCOUNTER18 0xb12 -#define CSR_MHPMCOUNTER19 0xb13 -#define CSR_MHPMCOUNTER20 0xb14 -#define CSR_MHPMCOUNTER21 0xb15 -#define CSR_MHPMCOUNTER22 0xb16 -#define CSR_MHPMCOUNTER23 0xb17 -#define CSR_MHPMCOUNTER24 0xb18 -#define CSR_MHPMCOUNTER25 0xb19 -#define CSR_MHPMCOUNTER26 0xb1a -#define CSR_MHPMCOUNTER27 0xb1b -#define CSR_MHPMCOUNTER28 0xb1c -#define CSR_MHPMCOUNTER29 0xb1d -#define CSR_MHPMCOUNTER30 0xb1e -#define CSR_MHPMCOUNTER31 0xb1f -#define CSR_MUCOUNTEREN 0x320 -#define CSR_MSCOUNTEREN 0x321 -#define CSR_MHPMEVENT3 0x323 -#define CSR_MHPMEVENT4 0x324 -#define CSR_MHPMEVENT5 0x325 -#define CSR_MHPMEVENT6 0x326 -#define CSR_MHPMEVENT7 0x327 -#define CSR_MHPMEVENT8 0x328 -#define CSR_MHPMEVENT9 0x329 -#define CSR_MHPMEVENT10 0x32a -#define CSR_MHPMEVENT11 0x32b -#define CSR_MHPMEVENT12 0x32c -#define CSR_MHPMEVENT13 0x32d -#define CSR_MHPMEVENT14 0x32e -#define CSR_MHPMEVENT15 0x32f -#define CSR_MHPMEVENT16 0x330 -#define CSR_MHPMEVENT17 0x331 -#define CSR_MHPMEVENT18 0x332 -#define CSR_MHPMEVENT19 0x333 -#define CSR_MHPMEVENT20 0x334 -#define CSR_MHPMEVENT21 0x335 -#define CSR_MHPMEVENT22 0x336 -#define CSR_MHPMEVENT23 0x337 -#define CSR_MHPMEVENT24 0x338 -#define CSR_MHPMEVENT25 0x339 -#define CSR_MHPMEVENT26 0x33a -#define CSR_MHPMEVENT27 0x33b -#define CSR_MHPMEVENT28 0x33c -#define CSR_MHPMEVENT29 0x33d -#define CSR_MHPMEVENT30 0x33e -#define CSR_MHPMEVENT31 0x33f -#define CSR_MVENDORID 0xf11 -#define CSR_MARCHID 0xf12 -#define CSR_MIMPID 0xf13 -#define CSR_MHARTID 0xf14 -#define CSR_CYCLEH 0xc80 -#define CSR_TIMEH 0xc81 -#define CSR_INSTRETH 0xc82 -#define CSR_HPMCOUNTER3H 0xc83 -#define CSR_HPMCOUNTER4H 0xc84 -#define CSR_HPMCOUNTER5H 0xc85 -#define CSR_HPMCOUNTER6H 0xc86 -#define CSR_HPMCOUNTER7H 0xc87 -#define CSR_HPMCOUNTER8H 0xc88 -#define CSR_HPMCOUNTER9H 0xc89 -#define CSR_HPMCOUNTER10H 0xc8a -#define CSR_HPMCOUNTER11H 0xc8b -#define CSR_HPMCOUNTER12H 0xc8c -#define CSR_HPMCOUNTER13H 0xc8d -#define CSR_HPMCOUNTER14H 0xc8e -#define CSR_HPMCOUNTER15H 0xc8f -#define CSR_HPMCOUNTER16H 0xc90 -#define CSR_HPMCOUNTER17H 0xc91 -#define CSR_HPMCOUNTER18H 0xc92 -#define CSR_HPMCOUNTER19H 0xc93 -#define CSR_HPMCOUNTER20H 0xc94 -#define CSR_HPMCOUNTER21H 0xc95 -#define CSR_HPMCOUNTER22H 0xc96 -#define CSR_HPMCOUNTER23H 0xc97 -#define CSR_HPMCOUNTER24H 0xc98 -#define CSR_HPMCOUNTER25H 0xc99 -#define CSR_HPMCOUNTER26H 0xc9a -#define CSR_HPMCOUNTER27H 0xc9b -#define CSR_HPMCOUNTER28H 0xc9c -#define CSR_HPMCOUNTER29H 0xc9d -#define CSR_HPMCOUNTER30H 0xc9e -#define CSR_HPMCOUNTER31H 0xc9f -#define CSR_MCYCLEH 0xb80 -#define CSR_MINSTRETH 0xb82 -#define CSR_MHPMCOUNTER3H 0xb83 -#define CSR_MHPMCOUNTER4H 0xb84 -#define CSR_MHPMCOUNTER5H 0xb85 -#define CSR_MHPMCOUNTER6H 0xb86 -#define CSR_MHPMCOUNTER7H 0xb87 -#define CSR_MHPMCOUNTER8H 0xb88 -#define CSR_MHPMCOUNTER9H 0xb89 -#define CSR_MHPMCOUNTER10H 0xb8a -#define CSR_MHPMCOUNTER11H 0xb8b -#define CSR_MHPMCOUNTER12H 0xb8c -#define CSR_MHPMCOUNTER13H 0xb8d -#define CSR_MHPMCOUNTER14H 0xb8e -#define CSR_MHPMCOUNTER15H 0xb8f -#define CSR_MHPMCOUNTER16H 0xb90 -#define CSR_MHPMCOUNTER17H 0xb91 -#define CSR_MHPMCOUNTER18H 0xb92 -#define CSR_MHPMCOUNTER19H 0xb93 -#define CSR_MHPMCOUNTER20H 0xb94 -#define CSR_MHPMCOUNTER21H 0xb95 -#define CSR_MHPMCOUNTER22H 0xb96 -#define CSR_MHPMCOUNTER23H 0xb97 -#define CSR_MHPMCOUNTER24H 0xb98 -#define CSR_MHPMCOUNTER25H 0xb99 -#define CSR_MHPMCOUNTER26H 0xb9a -#define CSR_MHPMCOUNTER27H 0xb9b -#define CSR_MHPMCOUNTER28H 0xb9c -#define CSR_MHPMCOUNTER29H 0xb9d -#define CSR_MHPMCOUNTER30H 0xb9e -#define CSR_MHPMCOUNTER31H 0xb9f - -#define CSR_MTVT 0x307 -#define CSR_MNXTI 0x345 - -#define CSR_MCOUNTINHIBIT 0x320 - -#define CSR_MNVEC 0x7C3 - -#define CSR_MTVT2 0x7EC -#define CSR_JALMNXTI 0x7ED -#define CSR_PUSHMCAUSE 0x7EE -#define CSR_PUSHMEPC 0x7EF -#define CSR_PUSHMSUBM 0x7EB - -#define CSR_WFE 0x810 -#define CSR_SLEEPVALUE 0x811 -#define CSR_TXEVT 0x812 - -#define CSR_MMISC_CTL 0x7d0 -#define CSR_MSUBM 0x7c4 - -#define CAUSE_MISALIGNED_FETCH 0x0 -#define CAUSE_FAULT_FETCH 0x1 -#define CAUSE_ILLEGAL_INSTRUCTION 0x2 -#define CAUSE_BREAKPOINT 0x3 -#define CAUSE_MISALIGNED_LOAD 0x4 -#define CAUSE_FAULT_LOAD 0x5 -#define CAUSE_MISALIGNED_STORE 0x6 -#define CAUSE_FAULT_STORE 0x7 -#define CAUSE_USER_ECALL 0x8 -#define CAUSE_SUPERVISOR_ECALL 0x9 -#define CAUSE_HYPERVISOR_ECALL 0xa -#define CAUSE_MACHINE_ECALL 0xb -#define CAUSE_INSTRUCTION_PAGE_FAULT 0xc -#define CAUSE_LOAD_PAGE_FAULT 0xd -#define CAUSE_STORE_AMO_PAGE_FAULT 0xf -#endif -#ifdef DECLARE_INSN -DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) -DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) -DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) -DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) -DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) -DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) -DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) -DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) -DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) -DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) -DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) -DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) -DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) -DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) -DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) -DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) -DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) -DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) -DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) -DECLARE_INSN(add, MATCH_ADD, MASK_ADD) -DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) -DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) -DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) -DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) -DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) -DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) -DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) -DECLARE_INSN(or, MATCH_OR, MASK_OR) -DECLARE_INSN(and, MATCH_AND, MASK_AND) -DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) -DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) -DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) -DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) -DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) -DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) -DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) -DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) -DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) -DECLARE_INSN(lb, MATCH_LB, MASK_LB) -DECLARE_INSN(lh, MATCH_LH, MASK_LH) -DECLARE_INSN(lw, MATCH_LW, MASK_LW) -DECLARE_INSN(ld, MATCH_LD, MASK_LD) -DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) -DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) -DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) -DECLARE_INSN(sb, MATCH_SB, MASK_SB) -DECLARE_INSN(sh, MATCH_SH, MASK_SH) -DECLARE_INSN(sw, MATCH_SW, MASK_SW) -DECLARE_INSN(sd, MATCH_SD, MASK_SD) -DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) -DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) -DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) -DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) -DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) -DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) -DECLARE_INSN(div, MATCH_DIV, MASK_DIV) -DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) -DECLARE_INSN(rem, MATCH_REM, MASK_REM) -DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) -DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) -DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) -DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) -DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) -DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) -DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) -DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) -DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) -DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) -DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) -DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) -DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) -DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) -DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) -DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) -DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) -DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) -DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) -DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) -DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) -DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) -DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) -DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) -DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) -DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) -DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) -DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) -DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) -DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) -DECLARE_INSN(uret, MATCH_URET, MASK_URET) -DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) -DECLARE_INSN(hret, MATCH_HRET, MASK_HRET) -DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) -DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) -DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM) -DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) -DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) -DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) -DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) -DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) -DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) -DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) -DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) -DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) -DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) -DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) -DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) -DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) -DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) -DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) -DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) -DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) -DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) -DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) -DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) -DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) -DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) -DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) -DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) -DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) -DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) -DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) -DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) -DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) -DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) -DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) -DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) -DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) -DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) -DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) -DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) -DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) -DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) -DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) -DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S) -DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) -DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) -DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) -DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) -DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) -DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) -DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) -DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) -DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) -DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) -DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) -DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X) -DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) -DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) -DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) -DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) -DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) -DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) -DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) -DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) -DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) -DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) -DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) -DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) -DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) -DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) -DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) -DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) -DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) -DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) -DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) -DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) -DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) -DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) -DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) -DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) -DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) -DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) -DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) -DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) -DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) -DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) -DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) -DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) -DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) -DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) -DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) -DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) -DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) -DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) -DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) -DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) -DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) -DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) -DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) -DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) -DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) -DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) -DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) -DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) -DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) -DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) -DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) -DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) -DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) -DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) -DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) -DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) -DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) -DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) -DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) -DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) -DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) -DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) -DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) -DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) -DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, - MASK_CUSTOM0_RD_RS1_RS2) -DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) -DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) -DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) -DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) -DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) -DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, - MASK_CUSTOM1_RD_RS1_RS2) -DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) -DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) -DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) -DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) -DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) -DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, - MASK_CUSTOM2_RD_RS1_RS2) -DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) -DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) -DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) -DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) -DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) -DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, - MASK_CUSTOM3_RD_RS1_RS2) -#endif -#ifdef DECLARE_CSR -DECLARE_CSR(fflags, CSR_FFLAGS) -DECLARE_CSR(frm, CSR_FRM) -DECLARE_CSR(fcsr, CSR_FCSR) -DECLARE_CSR(cycle, CSR_CYCLE) -DECLARE_CSR(time, CSR_TIME) -DECLARE_CSR(instret, CSR_INSTRET) -DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) -DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) -DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) -DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) -DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) -DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) -DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) -DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) -DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) -DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) -DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) -DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) -DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) -DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) -DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) -DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) -DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) -DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) -DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) -DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) -DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) -DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) -DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) -DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) -DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) -DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) -DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) -DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) -DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) -DECLARE_CSR(sstatus, CSR_SSTATUS) -DECLARE_CSR(sie, CSR_SIE) -DECLARE_CSR(stvec, CSR_STVEC) -DECLARE_CSR(sscratch, CSR_SSCRATCH) -DECLARE_CSR(sepc, CSR_SEPC) -DECLARE_CSR(scause, CSR_SCAUSE) -DECLARE_CSR(sbadaddr, CSR_SBADADDR) -DECLARE_CSR(sip, CSR_SIP) -DECLARE_CSR(sptbr, CSR_SPTBR) -DECLARE_CSR(mstatus, CSR_MSTATUS) -DECLARE_CSR(misa, CSR_MISA) -DECLARE_CSR(medeleg, CSR_MEDELEG) -DECLARE_CSR(mideleg, CSR_MIDELEG) -DECLARE_CSR(mie, CSR_MIE) -DECLARE_CSR(mtvec, CSR_MTVEC) -DECLARE_CSR(mscratch, CSR_MSCRATCH) -DECLARE_CSR(mepc, CSR_MEPC) -DECLARE_CSR(mcause, CSR_MCAUSE) -DECLARE_CSR(mbadaddr, CSR_MBADADDR) -DECLARE_CSR(mip, CSR_MIP) -DECLARE_CSR(tselect, CSR_TSELECT) -DECLARE_CSR(tdata1, CSR_TDATA1) -DECLARE_CSR(tdata2, CSR_TDATA2) -DECLARE_CSR(tdata3, CSR_TDATA3) -DECLARE_CSR(dcsr, CSR_DCSR) -DECLARE_CSR(dpc, CSR_DPC) -DECLARE_CSR(dscratch, CSR_DSCRATCH) -DECLARE_CSR(mcycle, CSR_MCYCLE) -DECLARE_CSR(minstret, CSR_MINSTRET) -DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) -DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) -DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) -DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) -DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) -DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) -DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) -DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) -DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) -DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) -DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) -DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) -DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) -DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) -DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) -DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) -DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) -DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) -DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) -DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) -DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) -DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) -DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) -DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) -DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) -DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) -DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) -DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) -DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) -DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN) -DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN) -DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) -DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) -DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) -DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) -DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) -DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) -DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) -DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) -DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) -DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) -DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) -DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) -DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) -DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) -DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) -DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) -DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) -DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) -DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) -DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) -DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) -DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) -DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) -DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) -DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) -DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) -DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) -DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) -DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) -DECLARE_CSR(mvendorid, CSR_MVENDORID) -DECLARE_CSR(marchid, CSR_MARCHID) -DECLARE_CSR(mimpid, CSR_MIMPID) -DECLARE_CSR(mhartid, CSR_MHARTID) -DECLARE_CSR(cycleh, CSR_CYCLEH) -DECLARE_CSR(timeh, CSR_TIMEH) -DECLARE_CSR(instreth, CSR_INSTRETH) -DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) -DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) -DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) -DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) -DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) -DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) -DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) -DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) -DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) -DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) -DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) -DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) -DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) -DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) -DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) -DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) -DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) -DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) -DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) -DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) -DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) -DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) -DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) -DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) -DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) -DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) -DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) -DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) -DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) -DECLARE_CSR(mcycleh, CSR_MCYCLEH) -DECLARE_CSR(minstreth, CSR_MINSTRETH) -DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) -DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) -DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) -DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) -DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) -DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) -DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) -DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) -DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) -DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) -DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) -DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) -DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) -DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) -DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) -DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) -DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) -DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) -DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) -DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) -DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) -DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) -DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) -DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) -DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) -DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) -DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) -DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) -DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) -#endif -#ifdef DECLARE_CAUSE -DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) -DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH) -DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) -DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) -DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) -DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD) -DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) -DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE) -DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) -DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) -DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) -DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/rv_pmp.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/rv_pmp.h deleted file mode 100644 index 238eacc3d2..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/rv_pmp.h +++ /dev/null @@ -1,73 +0,0 @@ -#ifndef _RV_PMP_H_ -#define _RV_PMP_H_ - -#define RV_PMP_ENTRY (8) - -#define ENTRY_FLAG_PERM_R (1 << 0) -#define ENTRY_FLAG_PERM_W (1 << 1) -#define ENTRY_FLAG_PERM_X (1 << 2) -#define ENTRY_FLAG_ADDR_OFF (0 << 3) -#define ENTRY_FLAG_ADDR_TOR (1 << 3) -#define ENTRY_FLAG_ADDR_NAPOT (3 << 3) -#define ENTRY_FLAG_ADDR_MASK (3 << 3) -#define ENTRY_FLAG_M_MODE_L (1 << 7) - -#define ENTRY_FLAG_SIZE (8) -#define ENTRY_FLAG_MASK (0xFF) - -#define ENTRY_IN_CFG_REG (__riscv_xlen / ENTRY_FLAG_SIZE) - -/* E907: the smallest granularity is 128B */ -/* C906: the smallest granularity is 4K */ -#define PMP_REG_SZ_128B (1 << 8) -#define PMP_REG_SZ_256B (1 << 9) -#define PMP_REG_SZ_512B (1 << 10) -#define PMP_REG_SZ_1K (1 << 11) -#define PMP_REG_SZ_2K (1 << 12) -#define PMP_REG_SZ_4K (1 << 12) -#define PMP_REG_SZ_8K (1 << 13) -#define PMP_REG_SZ_16K (1 << 14) -#define PMP_REG_SZ_32K (1 << 15) -#define PMP_REG_SZ_64K (1 << 16) -#define PMP_REG_SZ_128K (1 << 17) -#define PMP_REG_SZ_256K (1 << 18) -#define PMP_REG_SZ_512K (1 << 19) -#define PMP_REG_SZ_1M (1 << 20) -#define PMP_REG_SZ_2M (1 << 21) -#define PMP_REG_SZ_4M (1 << 22) -#define PMP_REG_SZ_8M (1 << 23) -#define PMP_REG_SZ_16M (1 << 24) -#define PMP_REG_SZ_32M (1 << 25) -#define PMP_REG_SZ_64M (1 << 26) -#define PMP_REG_SZ_128M (1 << 27) -#define PMP_REG_SZ_256M (1 << 28) -#define PMP_REG_SZ_512M (1 << 29) -#define PMP_REG_SZ_1G (1 << 30) -#define PMP_REG_SZ_1024M (PMP_REG_SZ_1G) - -typedef enum _pmp_status_type_ { - PMP_STATUS_OK = 0, - PMP_STATUS_BUSY, - PMP_STATUS_DENIED, - PMP_STATUS_INVALID, - PMP_STATUS_UNSUPPORTED, - PMP_STATUS_MAX = 0x7FFFFFFF -} pmp_status_type_e; - -typedef enum _addr_match_type_ { - PMP_ADDR_MATCH_OFF = 0, - PMP_ADDR_MATCH_TOR, - PMP_ADDR_MATCH_NA4, - PMP_ADDR_MATCH_NAPOT -} pmp_addr_match_type_e; - -typedef struct _pmp_config_entry { - uintptr_t entry_pa_base; - uintptr_t entry_pa_length; - uintptr_t entry_flag; -} pmp_config_entry_t; - -pmp_status_type_e rvpmp_fill_entry(const pmp_config_entry_t *entry, uintptr_t i, uintptr_t force); -pmp_status_type_e rvpmp_init(const pmp_config_entry_t *entry, uintptr_t n); - -#endif /* _RV_PMP_H_ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/bl808_ram_dv.ld b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/bl808_ram_dv.ld deleted file mode 100644 index 6726215465..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/bl808_ram_dv.ld +++ /dev/null @@ -1,195 +0,0 @@ -/**************************************************************************************** -* @file ram.ld -* -* @brief This file is the link script file (gnuarm or armgcc). -* -* Copyright (C) BouffaloLab 2021 -* -**************************************************************************************** -*/ - -/* configure the CPU type */ -OUTPUT_ARCH( "riscv" ) -/* link with the standard c library */ -INPUT(-lc) -/* link with the standard GCC library */ -INPUT(-lgcc) -/* configure the entry point */ -ENTRY(Reset_Handler) - -StackSize = 0x0400; /* 1KB */ -HeapMinSize = 0x1000; /* 4KB */ - -MEMORY -{ - code_memory (rx) : ORIGIN = 0x3eff0000, LENGTH = 64K - itcm_memory (rx) : ORIGIN = 0x3eff0000, LENGTH = 64K - dtcm_memory (rx) : ORIGIN = 0x3f000000, LENGTH = 32K - ram_memory (!rx) : ORIGIN = 0x3f008000, LENGTH = 32K - xram_memory (!rx) : ORIGIN = 0x40004000, LENGTH = 16K -} - -SECTIONS -{ - PROVIDE(__metal_chicken_bit = 0); - - .text : - { - . = ALIGN(4); - __text_code_start__ = .; - - KEEP (*(SORT_NONE(_start))) - KEEP (*(SORT_NONE(Reset_Handler))) - - *(.text) - *(.text.*) - - *(.rodata) - *(.rodata.*) - - *(.srodata) - *(.srodata.*) - - *(.tcm_code.*) - *(.tcm_const.*) - *(.sclock_rlt_code.*) - *(.sclock_rlt_const.*) - - . = ALIGN(4); - __text_code_end__ = .; - } > code_memory - - . = ALIGN(4); - __itcm_load_addr = .; - - .itcm_region : AT (__itcm_load_addr) - { - . = ALIGN(4); - __tcm_code_start__ = .; - - . = ALIGN(4); - __tcm_code_end__ = .; - } > itcm_memory - - __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region); - - .dtcm_region : AT (__dtcm_load_addr) - { - . = ALIGN(4); - __tcm_data_start__ = .; - - *(.tcm_data) - /* *finger_print.o(.data*) */ - - . = ALIGN(4); - __tcm_data_end__ = .; - } > dtcm_memory - - /*************************************************************************/ - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (NOLOAD): - { - . = ALIGN(0x4); - . = . + StackSize; - . = ALIGN(0x4); - } > dtcm_memory - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory); - PROVIDE( __freertos_irq_stack_top = __StackTop); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack") - /*************************************************************************/ - - __system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region); - - .system_ram_data_region : AT (__system_ram_load_addr) - { - . = ALIGN(4); - __system_ram_data_start__ = .; - - *(.system_ram) - - . = ALIGN(4); - __system_ram_data_end__ = .; - } > ram_memory - - .system_ram_noinit_data_region (NOLOAD) : - { - . = ALIGN(4); - *(.system_ram_noinit) - - . = ALIGN(4); - } > ram_memory - - __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region); - - /* Data section */ - RAM_DATA : AT (__ram_load_addr) - { - . = ALIGN(4); - __ram_data_start__ = .; - - PROVIDE( __global_pointer$ = . + 0x800 ); - - *(.data) - *(.data.*) - *(.sdata) - *(.sdata.*) - *(.sdata2) - *(.sdata2.*) - - . = ALIGN(4); - __ram_data_end__ = .; - } > ram_memory - - __etext_final = (__ram_load_addr + SIZEOF (RAM_DATA)); - ASSERT(__etext_final <= ORIGIN(code_memory) + LENGTH(code_memory), "code memory overflow") - - .bss (NOLOAD) : - { - . = ALIGN(4); - __bss_start__ = .; - - *(.bss*) - *(.sbss*) - *(COMMON) - - . = ALIGN(4); - __bss_end__ = .; - } > ram_memory - - .noinit_data (NOLOAD) : - { - . = ALIGN(4); - __noinit_data_start__ = .; - - *(.noinit_data*) - - . = ALIGN(4); - __noinit_data_end__ = .; - } > ram_memory - - .heap (NOLOAD): - { - . = ALIGN(4); - __HeapBase = .; - - /*__end__ = .;*/ - /*end = __end__;*/ - KEEP(*(.heap*)) - - . = ALIGN(4); - __HeapLimit = .; - } > ram_memory - - __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory); - ASSERT(__HeapLimit - __HeapBase >= HeapMinSize, "heap region overflow") - -} - diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/cpu_flags.cmake b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/cpu_flags.cmake deleted file mode 100644 index 4c67fb5250..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/cpu_flags.cmake +++ /dev/null @@ -1,18 +0,0 @@ -# CPU_ARCH := RISCV -# MCPU := c906 -# MARCH := rv64gcvxtheadc -# MABI := lp64d - -SET(CPU_ARCH "RISCV") -SET(MCPU "c906") - -SET(MARCH "rv64imafdcv0p7_zfh_xtheadc") -SET(MABI "lp64d") - -list(APPEND GLOBAL_C_FLAGS -march=${MARCH} -mabi=${MABI} -mtune=${MCPU} -mcmodel=medany) -list(APPEND GLOBAL_LD_FLAGS -march=${MARCH} -mabi=${MABI} -mtune=${MCPU} -mcmodel=medany) - -SET(LINKER_SCRIPT ${CMAKE_SOURCE_DIR}/drivers/bl808_driver/startup/d0/bl808_flash.ld) -#SET(LINKER_SCRIPT ${CMAKE_SOURCE_DIR}/drivers/bl808_driver/startup/d0/bl808_fpga.ld) -#SET(LINKER_SCRIPT ${CMAKE_SOURCE_DIR}/drivers/bl808_driver/startup/d0/bl808_ram.ld) -#SET(LINKER_SCRIPT ${CMAKE_SOURCE_DIR}/drivers/bl808_driver/startup/d0/bl808_ram_dv.ld) diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/source/interrupt.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/source/interrupt.c deleted file mode 100644 index 3a60bfbe88..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/source/interrupt.c +++ /dev/null @@ -1,218 +0,0 @@ -#include -#include -#include -#include -#include "bl808_glb.h" -#include "irq_ctx.h" - -#define DUMP_ALL_REGS -#define DUMP_MCAUSE_INFO - -pFunc g_irqvector[IRQn_LAST] __attribute__((aligned(16))) = { NULL }; - -void Interrupt_Default_Handler(void) __attribute__((weak)); -void Interrupt_Default_Handler(void) -{ - /* un-handled external IRQ */ - MSG("Enter interrupt default handler\r\n"); -} - -void Interrupt_Handler_Register(IRQn_Type irq, pFunc interruptFun) -{ - if (irq < IRQn_LAST) { - g_irqvector[irq] = interruptFun; - } -} - -static uintptr_t exception_handler_default(uintptr_t cause, uintptr_t val, uintptr_t *regs) __attribute__((noreturn)); -static uintptr_t exception_handler_default(uintptr_t cause, uintptr_t val, uintptr_t *regs) -{ - MSG("\n\rUn-handled Exception on CPU %d:\n\r", GLB_Get_Core_Type()); - // clang-format off - MSG("mstatus = 0x%16llx, FS=%d, MPP=%d, MPIE=%d\n\r", regs[REG_INT_CTX_NDX], - (regs[REG_INT_CTX_NDX] >> 13) & 0x3, - (regs[REG_INT_CTX_NDX] >> 11) & 0x3, - (regs[REG_INT_CTX_NDX] >> 7) & 1); - MSG("mcause: %d, mtval = 0x%16llx, mepc = 0x%16llx\n\r\n\r", (cause & 0xf), val, regs[REG_EPC_NDX]); -#ifdef DUMP_MCAUSE_INFO -const char *mcause_str[] = { - "Instruction address misaligned", - "Instruction access fault", - "Illegal instruction", - "Breakpoint", - "Load address misaligned", - "Load access fault", - "Store/AMO address misaligned", - "Store/AMO access fault", - "Environment call from U-mode", - "Environment call from S-mode", - "RSVD", - "Environment call from M-mode", - "Instruction page fault", - "Load page fault", - "RSVD", - "Store/AMO page fault" -}; - if ((cause & 0xf)) - MSG("%s\r\n\r\n", mcause_str[cause & 0xf]); -#endif - -#ifdef DUMP_ALL_REGS - MSG("ra = 0x%16llx ", regs[REG_RA]); MSG("sp = 0x%16llx ", regs[REG_SP]); MSG("gp = 0x%16llx ", regs[REG_GP]); - MSG("tp = 0x%16llx ", regs[REG_TP]); MSG("\n\r"); - - MSG("t0 = 0x%16llx ", regs[REG_T0]); MSG("t1 = 0x%16llx ", regs[REG_T1]); MSG("t2 = 0x%16llx ", regs[REG_T2]); - MSG("t3 = 0x%16llx ", regs[REG_T3]); MSG("\n\r"); - MSG("t4 = 0x%16llx ", regs[REG_T4]); MSG("t5 = 0x%16llx ", regs[REG_T5]); MSG("t6 = 0x%16llx ", regs[REG_T6]); - MSG("\n\r"); - - MSG("a0 = 0x%16llx ", regs[REG_A0]); MSG("a1 = 0x%16llx ", regs[REG_A1]); MSG("a2 = 0x%16llx ", regs[REG_A2]); - MSG("a3 = 0x%16llx ", regs[REG_A3]); MSG("\n\r"); - MSG("a4 = 0x%16llx ", regs[REG_A4]); MSG("a5 = 0x%16llx ", regs[REG_A5]); MSG("a6 = 0x%16llx ", regs[REG_A6]); - MSG("a7 = 0x%16llx ", regs[REG_A7]); MSG("\n\r"); - - MSG("s0 = 0x%16llx ", regs[REG_S0]); MSG("s1 = 0x%16llx ", regs[REG_S1]); MSG("s2 = 0x%16llx ", regs[REG_S2]); - MSG("s3 = 0x%16llx ", regs[REG_S3]); MSG("\n\r"); - MSG("s4 = 0x%16llx ", regs[REG_S4]); MSG("s5 = 0x%16llx ", regs[REG_S5]); MSG("s6 = 0x%16llx ", regs[REG_S6]); - MSG("s7 = 0x%16llx ", regs[REG_S7]); MSG("\n\r"); - MSG("s8 = 0x%16llx ", regs[REG_S8]); MSG("s9 = 0x%16llx ", regs[REG_S9]); MSG("s10 = 0x%16llx ", regs[REG_S10]); - MSG("s11 = 0x%16llx ", regs[REG_S11]); MSG("\n\r"); -#endif - // clang-format on - MSG("\n\r"); - - while (1) - ; -} - -static uintptr_t exception_handler_ECALL_M(uintptr_t cause, uintptr_t val, uintptr_t *regs) -{ - regs[REG_EPC_NDX] += 4; - __asm volatile("nop" :: - : "memory"); - - return 0; -} - -static exception_handler exception_handlers[RV_EXCEPTION_NUM] = { - exception_handler_default, /* 0: Instruction Address Misaligned */ - exception_handler_default, /* 1: Instruction Access Fault */ - exception_handler_default, /* 2: Illegal Instruction */ - exception_handler_default, /* 3: Breakpoint */ - exception_handler_default, /* 4: Load Address Misaligned */ - exception_handler_default, /* 5: Load Access Fault */ - exception_handler_default, /* 6: Store/AMO Address Misaligned */ - exception_handler_default, /* 7: Store/AMO Access Fault */ - exception_handler_default, /* 8: Environment Call from U-mode */ - exception_handler_default, /* 9: Environment Call from S-mode */ - exception_handler_default, /* 10: Environment Call from H-mode */ - exception_handler_ECALL_M, /* 11: Environment Call from M-mode */ - exception_handler_default, /* 12: Instruction Page Fault */ - exception_handler_default, /* 13: Load Page Fault */ - exception_handler_default, /* 14: Reserved */ - exception_handler_default, /* 15: Store/AMO Page Fault */ -}; - -exception_handler exception_handler_install(uintptr_t vec, exception_handler handler) -{ - exception_handler previous = NULL; - - if (RV_EXCEPTION_NUM > vec) { - previous = exception_handlers[vec]; - exception_handlers[vec] = handler; - } - - return previous; -} - -uintptr_t *trap_c(uintptr_t cause, uintptr_t *regs) -{ - uint32_t vec = 0; - uintptr_t tval = __get_MTVAL(); - - riscv_savefpu(regs); - - vec = cause & 0x3FF; - - if (RV_EXCEPTION_NUM > vec) { - exception_handlers[vec](cause, tval, regs); - } else { - while (1) - ; - } - - riscv_restorefpu(regs); - - return regs; -} - -/** - \brief enable irq. - \param[in] irq_num Number of IRQ. - \return None. -*/ -void ATTR_TCM_SECTION CPU_Interrupt_Enable(uint32_t irq_num) -{ - if (irq_num >= IRQn_LAST) { - //MSG("Error! This interrupt don't support!\n"); - } else { - if (csi_vic_get_prio(irq_num) == 0) { - csi_vic_set_prio(irq_num, 1); - } - -#ifdef CONFIG_SYSTEM_SECURE - csi_vic_enable_sirq(irq_num); -#else - csi_vic_enable_irq(irq_num); -#endif - } -} - -/** - \brief disable irq. - \param[in] irq_num Number of IRQ. - \return None. -*/ -void ATTR_TCM_SECTION CPU_Interrupt_Disable(uint32_t irq_num) -{ - if (irq_num >= IRQn_LAST) { - //MSG("Error! This interrupt don't support!\n"); - } else { -#ifdef CONFIG_SYSTEM_SECURE - csi_vic_disable_sirq(irq_num); -#else - csi_vic_disable_irq(irq_num); -#endif - } -} - -/** - \brief Clear Pending Interrupt - \details Clear the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -void ATTR_TCM_SECTION CPU_Interrupt_Pending_Clear(uint32_t irq_num) -{ - if (irq_num >= IRQn_LAST) { - //MSG("Error! This interrupt don't support!\n"); - return; - } else { -#ifdef CONFIG_SYSTEM_SECURE - csi_vic_clear_pending_irq(irq_num); -#else - csi_vic_clear_pending_irq(irq_num); -#endif - } -} - -void System_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) -{ - csi_vic_set_prio(IRQn, PreemptPriority); -} - -void System_Interrupt_Init(void) -{ - for (uintptr_t irq = 0; irq < IRQn_LAST; irq++) { - g_irqvector[irq] = Interrupt_Default_Handler; - } -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/source/system_bl808.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/source/system_bl808.c deleted file mode 100644 index 048683937d..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/source/system_bl808.c +++ /dev/null @@ -1,105 +0,0 @@ -#include "csi_core.h" -#include "bl808.h" -#include "bl808_clock.h" -#include "bl808_glb.h" -#include "bl808_ef_cfg.h" -#ifdef BOOTROM -#include "bflb_bootrom.h" -#endif - -#define BL808_B0 (0x0) -#define BL808_B1 (0x1) -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define SYSTEM_CLOCK (32000000UL) -uintptr_t g_system_clock = SYSTEM_CLOCK; - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ - -void System_BOR_Init(void) -{ - //HBN_BOR_CFG_Type borCfg = {1/* pu_bor */, 0/* irq_bor_en */, 1/* bor_vth */, 1/* bor_sel */}; - //HBN_Set_BOR_Cfg(&borCfg); -} - -void System_Core_Clock_Set(BL_System_Clock_Type type, uint32_t clock) -{ - Clock_Cfg_Type *pClk = (Clock_Cfg_Type *)SYS_CLOCK_CFG_ADDR; - - CHECK_PARAM(IS_BL_SYSTEM_CLOCK_TYPE(type)); - - if (type < BL_SYSTEM_CLOCK_MAX) { - pClk->systemClock[type] = clock; - pClk->magic = SYS_CLOCK_CFG_MAGIC; - } -} - -void System_Init(void) -{ - uintptr_t tmpVal = 0; -#ifdef DUALCORE - while ((BL_RD_WORD(IPC_SYNC_ADDR1) != IPC_SYNC_FLAG) || - (BL_RD_WORD(IPC_SYNC_ADDR2) != IPC_SYNC_FLAG)) { - // clang-format off - __NOP(); __NOP(); __NOP(); __NOP(); - __NOP(); __NOP(); __NOP(); __NOP(); - __NOP(); __NOP(); __NOP(); __NOP(); - __NOP(); __NOP(); __NOP(); __NOP(); - // clang-format on - /* if cache is off, comment this and this api need to start load itcm*/ - // L1C_DCache_Invalid_By_Addr(IPC_SYNC_ADDR1, 8); - }; - /* clear this flags for system reboot */ - BL_WR_WORD(IPC_SYNC_ADDR1, 0x0); - BL_WR_WORD(IPC_SYNC_ADDR2, 0x0); -#endif - /* turn on cache to speed up boot sequence */ - csi_icache_enable(); - csi_dcache_enable(); - /* enable I/D Cache preload. */ - tmpVal = __get_MHINT(); - tmpVal |= (1 << 8) | (1 << 2); - /* clear AMR */ - tmpVal &= (~0x18); - __set_MHINT(tmpVal); - __DSB(); - - /* init bor for all platform */ - System_BOR_Init(); -} - -void System_Post_Init(void) -{ - /* fix amr setting */ - uintptr_t tmpVal = 0; - Efuse_Chip_Info_Type chip_info; - EF_Ctrl_Get_Chip_Info(&chip_info); - /* if not B0 enable AMR */ - if (chip_info.chipInfo != BL808_B0) { - tmpVal = __get_MHINT(); - tmpVal |= (1 << 3); - __set_MHINT(tmpVal); - } - - System_Interrupt_Init(); - - /* global IRQ enable */ - __enable_irq(); -} - -int32_t drv_get_cpu_id(void) -{ - return __get_MHARTID(); -} - -int32_t drv_get_cpu_freq(int32_t idx) -{ - return g_system_clock; -} - -#if defined(DUAL_CORE) -extern void Reset_Handler(void); -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/source/system_bl808.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/source/system_bl808.h deleted file mode 100644 index 07e4e07efc..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/source/system_bl808.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef __SYSTEM_BL808_H__ -#define __SYSTEM_BL808_H__ - -#define RV_EXCEPTION_NUM (16) -typedef uintptr_t (*exception_handler)(uintptr_t cause, uintptr_t val, uintptr_t *regs); -typedef void (*pFunc)(void); - -extern void System_Interrupt_Init(void); -extern void CPU_Interrupt_Enable(uint32_t irq_num); -extern void CPU_Interrupt_Disable(uint32_t irq_num); -extern void CPU_Interrupt_Pending_Clear(uint32_t irq_num); -void Interrupt_Handler_Register(IRQn_Type irq, pFunc interruptFun); -extern void System_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); - -exception_handler exception_handler_install(uintptr_t vec, exception_handler handler); - -void riscv_savefpu(uintptr_t *regs); -void riscv_restorefpu(const uintptr_t *regs); - -int32_t drv_get_cpu_id(void); -int32_t drv_get_cpu_freq(int32_t idx); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/bl808_flash.ld b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/bl808_flash.ld deleted file mode 100644 index eb99463384..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/bl808_flash.ld +++ /dev/null @@ -1,264 +0,0 @@ -/**************************************************************************************** -* @file flash.ld -* -* @brief This file is the link script file (gnuarm or armgcc). -* -* Copyright (C) BouffaloLab 2021 -* -**************************************************************************************** -*/ - -/* configure the CPU type */ -OUTPUT_ARCH( "riscv" ) -/* link with the standard c library */ -INPUT(-lc) -/* link with the standard GCC library */ -INPUT(-lgcc) -/* configure the entry point */ -ENTRY(Reset_Handler) - -StackSize = 0x0400; /* 1KB */ -HeapMinSize = 0x1000; /* 4KB */ - -MEMORY -{ - xip_memory (rx) : ORIGIN = 0xD8000000, LENGTH = 32M - itcm_memory (rx) : ORIGIN = 0x62020000, LENGTH = 16K - dtcm_memory (rx) : ORIGIN = 0x62024000, LENGTH = 4K - nocache_ram_memory (!rx) : ORIGIN = 0x22050000, LENGTH = 0K - ram_memory (!rx) : ORIGIN = 0x62050000, LENGTH = 12K - xram_memory (!rx) : ORIGIN = 0x40000000, LENGTH = 16K -} - -SECTIONS -{ - - .text : - { - . = ALIGN(4); - __text_code_start__ = .; - KEEP(*startup*.*o(*.text*)) - KEEP (*(SORT_NONE(_start))) - KEEP (*(SORT_NONE(Reset_Handler))) - - *(.text) - *(.text.*) - - /* section information for shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - - /* section information for usb desc */ - . = ALIGN(4); - _usb_desc_start = .; - KEEP(*(usb_desc)) - . = ALIGN(4); - _usb_desc_end = .; - - /*put .rodata**/ - *(EXCLUDE_FILE( *bl808_glb*.o* \ - *bl808_glb_gpio*.o* \ - *bl808_pds*.o* \ - *bl808_aon*.o* \ - *bl808_hbn*.o* \ - *bl808_l1c*.o* \ - *bl808_common*.o* \ - *bl808_clock*.o* \ - *bl808_ef_ctrl*.o* \ - *bl808_sf_cfg*.o* \ - *bl808_sf_ctrl*.o* \ - *bl808_sflash*.o* \ - *bl808_xip_sflash*.o* \ - *bl808_romapi_patch*.o* ) .rodata*) - - *(.srodata) - *(.srodata.*) - - . = ALIGN(4); - __text_code_end__ = .; - } > xip_memory - - . = ALIGN(4); - __itcm_load_addr = .; - - .itcm_region : AT (__itcm_load_addr) - { - . = ALIGN(4); - __tcm_code_start__ = .; - - *(.tcm_code.*) - *(.tcm_const.*) - *(.sclock_rlt_code.*) - *(.sclock_rlt_const.*) - - *bl808_glb*.o*(.rodata*) - *bl808_glb_gpio*.o*(.rodata*) - *bl808_pds*.o*(.rodata*) - *bl808_aon*.o*(.rodata*) - *bl808_hbn*.o*(.rodata*) - *bl808_l1c*.o*(.rodata*) - *bl808_common*.o*(.rodata*) - *bl808_clock*.o*(.rodata*) - *bl808_ef_ctrl*.o*(.rodata*) - *bl808_sf_cfg*.o*(.rodata*) - *bl808_sf_ctrl*.o*(.rodata*) - *bl808_sflash*.o*(.rodata*) - *bl808_xip_sflash*.o*(.rodata*) - *bl808_romapi_patch*.o*(.rodata*) - - . = ALIGN(4); - __tcm_code_end__ = .; - } > itcm_memory - - __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region); - - .dtcm_region : AT (__dtcm_load_addr) - { - . = ALIGN(4); - __tcm_data_start__ = .; - - *(.tcm_data) - /* *finger_print.o(.data*) */ - - . = ALIGN(4); - __tcm_data_end__ = .; - } > dtcm_memory - - /*************************************************************************/ - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (NOLOAD): - { - . = ALIGN(0x4); - . = . + StackSize; - . = ALIGN(0x4); - } > dtcm_memory - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory); - PROVIDE( __freertos_irq_stack_top = __StackTop); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack") - /*************************************************************************/ - __nocache_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region); - - .nocache_ram_region (NOLOAD) : AT (__nocache_ram_load_addr) - { - . = ALIGN(4); - __nocache_ram_data_start__ = .; - - *(.nocache_ram) - - . = ALIGN(4); - __nocache_ram_data_end__ = .; - } > nocache_ram_memory - - __system_ram_load_addr = __nocache_ram_load_addr + SIZEOF(.nocache_ram_region); - - .system_ram_data_region : AT (__system_ram_load_addr) - { - . = ALIGN(4); - __system_ram_data_start__ = .; - - *(.system_ram) - - . = ALIGN(4); - __system_ram_data_end__ = .; - } > ram_memory - - .system_ram_noinit_data_region (NOLOAD) : - { - . = ALIGN(4); - *(.system_ram_noinit) - - . = ALIGN(4); - } > ram_memory - - __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region); - - /* Data section */ - RAM_DATA : AT (__ram_load_addr) - { - . = ALIGN(4); - __ram_data_start__ = .; - - PROVIDE( __global_pointer$ = . + 0x800 ); - - *(.data) - *(.data.*) - *(.sdata) - *(.sdata.*) - *(.sdata2) - *(.sdata2.*) - - . = ALIGN(4); - __ram_data_end__ = .; - } > ram_memory - - __etext_final = (__ram_load_addr + SIZEOF (RAM_DATA)); - ASSERT(__etext_final <= ORIGIN(xip_memory) + LENGTH(xip_memory), "code memory overflow") - - .bss (NOLOAD) : - { - . = ALIGN(4); - __bss_start__ = .; - - *(.bss*) - *(.sbss*) - *(COMMON) - - . = ALIGN(4); - __bss_end__ = .; - } > ram_memory - - .noinit_data (NOLOAD) : - { - . = ALIGN(4); - __noinit_data_start__ = .; - - *(.noinit_data*) - - . = ALIGN(4); - __noinit_data_end__ = .; - } > ram_memory - - .nocache_noinit_ram_region (NOLOAD) : - { - . = ALIGN(4); - __nocache_ram_data_start__ = .; - - *(.nocache_noinit_ram) - - . = ALIGN(4); - __nocache_ram_data_end__ = .; - } > nocache_ram_memory - - .heap (NOLOAD): - { - . = ALIGN(4); - __HeapBase = .; - - /*__end__ = .;*/ - /*end = __end__;*/ - KEEP(*(.heap*)) - - . = ALIGN(4); - __HeapLimit = .; - } > ram_memory - - __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory); - ASSERT(__HeapLimit - __HeapBase >= HeapMinSize, "heap region overflow") - -} - diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/bl808_ram.ld b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/bl808_ram.ld deleted file mode 100644 index 5fe6bd2ec6..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/bl808_ram.ld +++ /dev/null @@ -1,191 +0,0 @@ -/**************************************************************************************** -* @file ram.ld -* -* @brief This file is the link script file (gnuarm or armgcc). -* -* Copyright (C) BouffaloLab 2021 -* -**************************************************************************************** -*/ - -/* configure the CPU type */ -OUTPUT_ARCH( "riscv" ) -/* link with the standard c library */ -INPUT(-lc) -/* link with the standard GCC library */ -INPUT(-lgcc) -/* configure the entry point */ -ENTRY(Reset_Handler) - -StackSize = 0x0400; /* 1KB */ -HeapMinSize = 0x1000; /* 4KB */ - -MEMORY -{ - code_memory (rx) : ORIGIN = 0x62020000, LENGTH = 16K - itcm_memory (rx) : ORIGIN = 0x62020000, LENGTH = 16K - dtcm_memory (rx) : ORIGIN = 0x62024000, LENGTH = 4K - nocache_ram_memory (!rx) : ORIGIN = 0x22025000, LENGTH = 0K - ram_memory (!rx) : ORIGIN = 0x62025000, LENGTH = 12K - xram_memory (!rx) : ORIGIN = 0x40000000, LENGTH = 16K -} - -SECTIONS -{ - PROVIDE(__metal_chicken_bit = 0); - - .text : - { - . = ALIGN(4); - __text_code_start__ = .; - - KEEP (*(SORT_NONE(_start))) - KEEP (*(SORT_NONE(Reset_Handler))) - - *(.text) - *(.text.*) - - *(.rodata) - *(.rodata.*) - - *(.srodata) - *(.srodata.*) - - . = ALIGN(4); - __text_code_end__ = .; - } > code_memory - - . = ALIGN(4); - __itcm_load_addr = .; - - .itcm_region : AT (__itcm_load_addr) - { - . = ALIGN(4); - __tcm_code_start__ = .; - - . = ALIGN(4); - __tcm_code_end__ = .; - } > itcm_memory - - __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region); - - .dtcm_region : AT (__dtcm_load_addr) - { - . = ALIGN(4); - __tcm_data_start__ = .; - - *(.tcm_data) - /* *finger_print.o(.data*) */ - - . = ALIGN(4); - __tcm_data_end__ = .; - } > dtcm_memory - - /*************************************************************************/ - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (NOLOAD): - { - . = ALIGN(0x4); - . = . + StackSize; - . = ALIGN(0x4); - } > dtcm_memory - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory); - PROVIDE( __freertos_irq_stack_top = __StackTop); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack") - /*************************************************************************/ - - __system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region); - - .system_ram_data_region : AT (__system_ram_load_addr) - { - . = ALIGN(4); - __system_ram_data_start__ = .; - - *(.system_ram) - - . = ALIGN(4); - __system_ram_data_end__ = .; - } > ram_memory - - .system_ram_noinit_data_region (NOLOAD) : - { - . = ALIGN(4); - *(.system_ram_noinit) - - . = ALIGN(4); - } > ram_memory - - __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region); - - /* Data section */ - RAM_DATA : AT (__ram_load_addr) - { - . = ALIGN(4); - __ram_data_start__ = .; - - PROVIDE( __global_pointer$ = . + 0x800 ); - - *(.data) - *(.data.*) - *(.sdata) - *(.sdata.*) - *(.sdata2) - *(.sdata2.*) - - . = ALIGN(4); - __ram_data_end__ = .; - } > ram_memory - - __etext_final = (__ram_load_addr + SIZEOF (RAM_DATA)); - ASSERT(__etext_final <= ORIGIN(code_memory) + LENGTH(code_memory), "code memory overflow") - - .bss (NOLOAD) : - { - . = ALIGN(4); - __bss_start__ = .; - - *(.bss*) - *(.sbss*) - *(COMMON) - - . = ALIGN(4); - __bss_end__ = .; - } > ram_memory - - .noinit_data (NOLOAD) : - { - . = ALIGN(4); - __noinit_data_start__ = .; - - *(.noinit_data*) - - . = ALIGN(4); - __noinit_data_end__ = .; - } > ram_memory - - .heap (NOLOAD): - { - . = ALIGN(4); - __HeapBase = .; - - /*__end__ = .;*/ - /*end = __end__;*/ - KEEP(*(.heap*)) - - . = ALIGN(4); - __HeapLimit = .; - } > ram_memory - - __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory); - ASSERT(__HeapLimit - __HeapBase >= HeapMinSize, "heap region overflow") - -} - diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/bl808_ram_dv.ld b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/bl808_ram_dv.ld deleted file mode 100644 index 3a992e09a4..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/bl808_ram_dv.ld +++ /dev/null @@ -1,195 +0,0 @@ -/**************************************************************************************** -* @file ram.ld -* -* @brief This file is the link script file (gnuarm or armgcc). -* -* Copyright (C) BouffaloLab 2021 -* -**************************************************************************************** -*/ - -/* configure the CPU type */ -OUTPUT_ARCH( "riscv" ) -/* link with the standard c library */ -INPUT(-lc) -/* link with the standard GCC library */ -INPUT(-lgcc) -/* configure the entry point */ -ENTRY(Reset_Handler) - -StackSize = 0x0400; /* 1KB */ -HeapMinSize = 0x1000; /* 4KB */ - -MEMORY -{ - code_memory (rx) : ORIGIN = 0x22020000, LENGTH = 32K - itcm_memory (rx) : ORIGIN = 0x22020000, LENGTH = 32K - dtcm_memory (rx) : ORIGIN = 0x22028000, LENGTH = 32K - ram_memory (!rx) : ORIGIN = 0x22030000, LENGTH = 32K - xram_memory (!rx) : ORIGIN = 0x40000000, LENGTH = 16K -} - -SECTIONS -{ - PROVIDE(__metal_chicken_bit = 0); - - .text : - { - . = ALIGN(4); - __text_code_start__ = .; - - KEEP (*(SORT_NONE(_start))) - KEEP (*(SORT_NONE(Reset_Handler))) - - *(.text) - *(.text.*) - - *(.rodata) - *(.rodata.*) - - *(.srodata) - *(.srodata.*) - - *(.tcm_code.*) - *(.tcm_const.*) - *(.sclock_rlt_code.*) - *(.sclock_rlt_const.*) - - . = ALIGN(4); - __text_code_end__ = .; - } > code_memory - - . = ALIGN(4); - __itcm_load_addr = .; - - .itcm_region : AT (__itcm_load_addr) - { - . = ALIGN(4); - __tcm_code_start__ = .; - - . = ALIGN(4); - __tcm_code_end__ = .; - } > itcm_memory - - __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region); - - .dtcm_region : AT (__dtcm_load_addr) - { - . = ALIGN(4); - __tcm_data_start__ = .; - - *(.tcm_data) - /* *finger_print.o(.data*) */ - - . = ALIGN(4); - __tcm_data_end__ = .; - } > dtcm_memory - - /*************************************************************************/ - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (NOLOAD): - { - . = ALIGN(0x4); - . = . + StackSize; - . = ALIGN(0x4); - } > dtcm_memory - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory); - PROVIDE( __freertos_irq_stack_top = __StackTop); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack") - /*************************************************************************/ - - __system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region); - - .system_ram_data_region : AT (__system_ram_load_addr) - { - . = ALIGN(4); - __system_ram_data_start__ = .; - - *(.system_ram) - - . = ALIGN(4); - __system_ram_data_end__ = .; - } > ram_memory - - .system_ram_noinit_data_region (NOLOAD) : - { - . = ALIGN(4); - *(.system_ram_noinit) - - . = ALIGN(4); - } > ram_memory - - __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region); - - /* Data section */ - RAM_DATA : AT (__ram_load_addr) - { - . = ALIGN(4); - __ram_data_start__ = .; - - PROVIDE( __global_pointer$ = . + 0x800 ); - - *(.data) - *(.data.*) - *(.sdata) - *(.sdata.*) - *(.sdata2) - *(.sdata2.*) - - . = ALIGN(4); - __ram_data_end__ = .; - } > ram_memory - - __etext_final = (__ram_load_addr + SIZEOF (RAM_DATA)); - ASSERT(__etext_final <= ORIGIN(code_memory) + LENGTH(code_memory), "code memory overflow") - - .bss (NOLOAD) : - { - . = ALIGN(4); - __bss_start__ = .; - - *(.bss*) - *(.sbss*) - *(COMMON) - - . = ALIGN(4); - __bss_end__ = .; - } > ram_memory - - .noinit_data (NOLOAD) : - { - . = ALIGN(4); - __noinit_data_start__ = .; - - *(.noinit_data*) - - . = ALIGN(4); - __noinit_data_end__ = .; - } > ram_memory - - .heap (NOLOAD): - { - . = ALIGN(4); - __HeapBase = .; - - /*__end__ = .;*/ - /*end = __end__;*/ - KEEP(*(.heap*)) - - . = ALIGN(4); - __HeapLimit = .; - } > ram_memory - - __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory); - ASSERT(__HeapLimit - __HeapBase >= HeapMinSize, "heap region overflow") - -} - diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/cpu_flags.cmake b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/cpu_flags.cmake deleted file mode 100644 index 982896cb2f..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/cpu_flags.cmake +++ /dev/null @@ -1,22 +0,0 @@ -#CPU_ARCH := RISCV -#MCPU := e902 -#E902 rv32ecxthead ilp32e e902 -#E902M rv32emcxthead ilp32e e902 -#E902T rv32ecxthead ilp32e e902 -#E902MT rv32emcxthead ilp32e e902 -#MARCH := rv32emcxthead -#MARCH := rv32emc -#MABI := ilp32e - -SET(CPU_ARCH "RISCV") -SET(MCPU "e902") - -SET(MARCH "rv32emcxtheadse") -SET(MABI "ilp32e") - -list(APPEND GLOBAL_C_FLAGS -march=${MARCH} -mabi=${MABI} -mtune=${MCPU}) -list(APPEND GLOBAL_LD_FLAGS -march=${MARCH} -mabi=${MABI} -mtune=${MCPU}) - -SET(LINKER_SCRIPT ${CMAKE_SOURCE_DIR}/drivers/bl808_driver/startup/lp/bl808_flash.ld) -#SET(LINKER_SCRIPT ${CMAKE_SOURCE_DIR}/drivers/bl808_driver/startup/lp/bl808_ram.ld) -#SET(LINKER_SCRIPT ${CMAKE_SOURCE_DIR}/drivers/bl808_driver/startup/lp/bl808_ram_dv.ld) \ No newline at end of file diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/source/interrupt.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/source/interrupt.c deleted file mode 100644 index a167bb8416..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/source/interrupt.c +++ /dev/null @@ -1,361 +0,0 @@ -#include -#include -#include -#include -#include -#include "irq_ctx.h" -#include "bl808_common.h" - -#define DUMP_ALL_REGS -#define DUMP_MCAUSE_INFO - -typedef void (*pFunc)(void); -void NMI_Handler(void); - -pFunc g_irqvector[IRQn_LAST] = { 0 }; -pFunc g_nmivector = NMI_Handler; - -extern void Default_IRQHandler(void); -extern void Default_Handler(void); -extern void Mtspend_Handler(void); - -void Interrupt_Default_Handler(void) __attribute__((weak)); -void Interrupt_Default_Handler(void) -{ - /* un-handled external IRQ */ -#if !defined(__OS_FREERTOS__) - MSG("Enter interrupt Default_Handler\r\n"); -#endif -} - -#if 0 - extern void Trap_Handler(void); - extern void Interrupt_Handler(void); - void Interrupt_Handler_Stub(void); - - void clic_msip_handler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void clic_mtimer_handler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void clic_mext_handler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void clic_csoft_handler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void BMX_ERR_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void BMX_TO_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void L1C_BMX_ERR_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void L1C_BMX_TO_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void SEC_BMX_ERR_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void RF_TOP_INT0_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void RF_TOP_INT1_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void SDIO_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void DMA_BMX_ERR_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void SEC_GMAC_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void SEC_CDET_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void SEC_PKA_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void SEC_TRNG_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void SEC_AES_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void SEC_SHA_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void DMA_ALL_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void IRTX_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void IRRX_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void SF_CTRL_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void GPADC_DMA_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void EFUSE_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void SPI_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void UART0_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void UART1_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void I2C_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void PWM_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void TIMER_CH0_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void TIMER_CH1_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void TIMER_WDT_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void GPIO_INT0_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void PDS_WAKEUP_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void HBN_OUT0_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void HBN_OUT1_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void BOR_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void WIFI_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void BZ_PHY_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void BLE_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void MAC_TXRX_TIMER_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void MAC_TXRX_MISC_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void MAC_RX_TRG_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void MAC_TX_TRG_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void MAC_GEN_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void MAC_PORT_TRG_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void WIFI_IPC_PUBLIC_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); -#endif - -const pFunc __Vectors[] __attribute__((section(".init"), aligned(64))) = { - Default_Handler, /* */ - Default_Handler, /* */ - Default_Handler, /* */ -#if defined(__OS_FREERTOS__) - Mtspend_Handler, /* 3: M-mode Soft IRQ */ -#else - Default_IRQHandler, /* 3: M-mode Soft IRQ */ -#endif - Default_Handler, /* */ - Default_Handler, /* */ - Default_Handler, /* */ - Default_IRQHandler, /* 7: M-mode Timer IRQ */ - Default_Handler, /* */ - Default_Handler, /* */ - Default_Handler, /* */ - Default_Handler, /* */ - Default_Handler, /* */ - Default_Handler, /* */ - Default_Handler, /* */ - Default_Handler, /* */ - - Default_IRQHandler, //BMX_ERR_IRQHandler_Wrapper, /* 16 + 0 */ - Default_IRQHandler, //BMX_TO_IRQHandler_Wrapper, /* 16 + 1 */ - Default_IRQHandler, //L1C_BMX_ERR_IRQHandler_Wrapper, /* 16 + 2 */ - Default_IRQHandler, //L1C_BMX_TO_IRQHandler_Wrapper, /* 16 + 3 */ - Default_IRQHandler, //SEC_BMX_ERR_IRQHandler_Wrapper, /* 16 + 4 */ - Default_IRQHandler, //RF_TOP_INT0_IRQHandler_Wrapper, /* 16 + 5 */ - Default_IRQHandler, //RF_TOP_INT1_IRQHandler_Wrapper, /* 16 + 6 */ - Default_IRQHandler, //SDIO_IRQHandler_Wrapper, /* 16 + 7 */ - Default_IRQHandler, //DMA_BMX_ERR_IRQHandler_Wrapper, /* 16 + 8 */ - Default_IRQHandler, //SEC_GMAC_IRQHandler_Wrapper, /* 16 + 9 */ - Default_IRQHandler, //SEC_CDET_IRQHandler_Wrapper, /* 16 + 10 */ - Default_IRQHandler, //SEC_PKA_IRQHandler_Wrapper, /* 16 + 11 */ - Default_IRQHandler, //SEC_TRNG_IRQHandler_Wrapper, /* 16 + 12 */ - Default_IRQHandler, //SEC_AES_IRQHandler_Wrapper, /* 16 + 13 */ - Default_IRQHandler, //SEC_SHA_IRQHandler_Wrapper, /* 16 + 14 */ - Default_IRQHandler, //DMA_ALL_IRQHandler_Wrapper, /* 16 + 15 */ - Default_IRQHandler, //0, /* 16 + 16 */ - Default_IRQHandler, //0, /* 16 + 17 */ - Default_IRQHandler, //0, /* 16 + 18 */ - Default_IRQHandler, //IRTX_IRQHandler_Wrapper, /* 16 + 19 */ - Default_IRQHandler, //IRRX_IRQHandler_Wrapper, /* 16 + 20 */ - Default_IRQHandler, //0, /* 16 + 21 */ - Default_IRQHandler, //0, /* 16 + 22 */ - Default_IRQHandler, //SF_CTRL_IRQHandler_Wrapper, /* 16 + 23 */ - Default_IRQHandler, //0, /* 16 + 24 */ - Default_IRQHandler, //GPADC_DMA_IRQHandler_Wrapper, /* 16 + 25 */ - Default_IRQHandler, //EFUSE_IRQHandler_Wrapper, /* 16 + 26 */ - Default_IRQHandler, //SPI_IRQHandler_Wrapper, /* 16 + 27 */ - Default_IRQHandler, //0, /* 16 + 28 */ - Default_IRQHandler, //UART0_IRQHandler_Wrapper, /* 16 + 29 */ - Default_IRQHandler, //UART1_IRQHandler_Wrapper, /* 16 + 30 */ - Default_IRQHandler, //0, /* 16 + 31 */ - Default_IRQHandler, //I2C_IRQHandler_Wrapper, /* 16 + 32 */ - Default_IRQHandler, //0, /* 16 + 33 */ - Default_IRQHandler, //PWM_IRQHandler_Wrapper, /* 16 + 34 */ - Default_IRQHandler, //0, /* 16 + 35 */ - Default_IRQHandler, //TIMER_CH0_IRQHandler_Wrapper, /* 16 + 36 */ - Default_IRQHandler, //TIMER_CH1_IRQHandler_Wrapper, /* 16 + 37 */ - Default_IRQHandler, //TIMER_WDT_IRQHandler_Wrapper, /* 16 + 38 */ - Default_IRQHandler, //0, /* 16 + 39 */ - Default_IRQHandler, //0, /* 16 + 40 */ - Default_IRQHandler, //0, /* 16 + 41 */ - Default_IRQHandler, //0, /* 16 + 42 */ - Default_IRQHandler, //0, /* 16 + 43 */ - Default_IRQHandler, //GPIO_INT0_IRQHandler_Wrapper, /* 16 + 44 */ - Default_IRQHandler, //0, /* 16 + 45 */ - Default_IRQHandler, //0, /* 16 + 46 */ - Default_IRQHandler, //0, /* 16 + 47 */ - Default_IRQHandler, //0, /* 16 + 48 */ - Default_IRQHandler, //0, /* 16 + 49 */ - Default_IRQHandler, //PDS_WAKEUP_IRQHandler_Wrapper, /* 16 + 50 */ - Default_IRQHandler, //HBN_OUT0_IRQHandler_Wrapper, /* 16 + 51 */ - Default_IRQHandler, //HBN_OUT1_IRQHandler_Wrapper, /* 16 + 52 */ - Default_IRQHandler, //BOR_IRQHandler_Wrapper, /* 16 + 53 */ - Default_IRQHandler, //WIFI_IRQHandler_Wrapper, /* 16 + 54 */ - Default_IRQHandler, //BZ_PHY_IRQHandler_Wrapper, /* 16 + 55 */ - Default_IRQHandler, //BLE_IRQHandler_Wrapper, /* 16 + 56 */ - Default_IRQHandler, //MAC_TXRX_TIMER_IRQHandler_Wrapper, /* 16 + 57 */ - Default_IRQHandler, //MAC_TXRX_MISC_IRQHandler_Wrapper, /* 16 + 58 */ - Default_IRQHandler, //MAC_RX_TRG_IRQHandler_Wrapper, /* 16 + 59 */ - Default_IRQHandler, //MAC_TX_TRG_IRQHandler_Wrapper, /* 16 + 60 */ - Default_IRQHandler, //MAC_GEN_IRQHandler_Wrapper, /* 16 + 61 */ - Default_IRQHandler, //MAC_PORT_TRG_IRQHandler_Wrapper, /* 16 + 62 */ - Default_IRQHandler, //WIFI_IPC_PUBLIC_IRQHandler_Wrapper, /* 16 + 63 */ -}; - -static uintptr_t exception_handler_default(uintptr_t cause, uintptr_t val, uintptr_t *regs) __attribute__((noreturn)); -static uintptr_t exception_handler_default(uintptr_t cause, uintptr_t val, uintptr_t *regs) -{ - MSG("\n\rUn-handled Exception on CPU %d:\n\r", GLB_Get_Core_Type()); - MSG("cause: 0x%8x, tval = 0x%8x, epc = 0x%8x\n\r", cause, val, regs[REG_EPC_NDX]); -#ifdef DUMP_MCAUSE_INFO - const char *mcause_str[] = { - "Instruction address misaligned", - "Instruction access fault", - "Illegal instruction", - "Breakpoint", - "Load address misaligned", - "Load access fault", - "Store/AMO address misaligned", - "Store/AMO access fault", - "Environment call from U-mode", - "Environment call from S-mode", - "RSVD", - "Environment call from M-mode", - "Instruction page fault", - "Load page fault", - "RSVD", - "Store/AMO page fault" - }; - if ((cause & 0xf)) - MSG("%s\r\n\r\n", mcause_str[cause & 0xf]); -#endif - -// clang-format off -#ifdef DUMP_ALL_REGS - MSG("ra = 0x%08x ", regs[REG_RA]); MSG("sp = 0x%08x ", regs[REG_SP]); MSG("gp = 0x%08x ", regs[REG_GP]); - MSG("tp = 0x%08x ", regs[REG_TP]); MSG("\n\r"); - - MSG("t0 = 0x%08x ", regs[REG_T0]); MSG("t1 = 0x%08x ", regs[REG_T1]); MSG("t2 = 0x%08x ", regs[REG_T2]); - MSG("\n\r"); - - MSG("a0 = 0x%08x ", regs[REG_A0]); MSG("a1 = 0x%08x ", regs[REG_A1]); MSG("a2 = 0x%08x ", regs[REG_A2]); - MSG("a3 = 0x%08x ", regs[REG_A3]); MSG("\n\r"); - MSG("a4 = 0x%08x ", regs[REG_A4]); MSG("a5 = 0x%08x ", regs[REG_A5]); MSG("\n\r"); - - MSG("s0 = 0x%08x ", regs[REG_S0]); MSG("s1 = 0x%08x ", regs[REG_S1]); MSG("\n\r"); -#endif - // clang-format on - - while (1) - ; -} - -static uintptr_t exception_handler_ECALL_M(uintptr_t cause, uintptr_t val, uintptr_t *regs) -{ - regs[REG_EPC_NDX] += 4; - __asm volatile("nop" :: - : "memory"); - - return 0; -} - -static exception_handler exception_handlers[RV_EXCEPTION_NUM] = { - exception_handler_default, /* 0: Instruction Address Misaligned */ - exception_handler_default, /* 1: Instruction Access Fault */ - exception_handler_default, /* 2: Illegal Instruction */ - exception_handler_default, /* 3: Breakpoint */ - exception_handler_default, /* 4: Load Address Misaligned */ - exception_handler_default, /* 5: Load Access Fault */ - exception_handler_default, /* 6: Store/AMO Address Misaligned */ - exception_handler_default, /* 7: Store/AMO Access Fault */ - exception_handler_default, /* 8: Environment Call from U-mode */ - exception_handler_default, /* 9: Environment Call from S-mode */ - exception_handler_default, /* 10: Environment Call from H-mode */ - exception_handler_ECALL_M, /* 11: Environment Call from M-mode */ - exception_handler_default, /* 12: Instruction Page Fault */ - exception_handler_default, /* 13: Load Page Fault */ - exception_handler_default, /* 14: Reserved */ - exception_handler_default, /* 15: Store/AMO Page Fault */ -}; - -exception_handler exception_handler_install(uintptr_t vec, exception_handler handler) -{ - exception_handler previous = NULL; - - if (RV_EXCEPTION_NUM > vec) { - previous = exception_handlers[vec]; - exception_handlers[vec] = handler; - } - - return previous; -} - -void trap_c(uint32_t *regs) -{ - uint32_t vec = 0; - uintptr_t cause = __get_MCAUSE(); - uintptr_t tval = __get_MTVAL(); - - vec = cause & 0x3FF; - - if (RV_EXCEPTION_NUM > vec) { - exception_handlers[vec](cause, tval, regs); - } else { - while (1) - ; - } -} - -void NMI_Handler(void) -{ - MSG("NMI_Handler\r\n"); - - while (1) - ; -} - -void Interrupt_Handler_Register(IRQn_Type irq, pFunc interruptFun) -{ - if (irq < IRQn_LAST) { - g_irqvector[irq] = interruptFun; - } -} - -/** - \brief enable irq. - \param[in] irq_num Number of IRQ. - \return None. -*/ -void ATTR_TCM_SECTION CPU_Interrupt_Enable(uint32_t irq_num) -{ - if (irq_num >= IRQn_LAST) { - //MSG("Error! This interrupt don't support!\n"); - } else { - if (irq_num >= CPU_LP_MAX_IRQ_NUM) { - irq_num -= 32; - } - -#ifdef CONFIG_SYSTEM_SECURE - csi_vic_enable_sirq(irq_num); -#else - csi_vic_enable_irq(irq_num); -#endif - } -} - -/** - \brief disable irq. - \param[in] irq_num Number of IRQ. - \return None. -*/ -void ATTR_TCM_SECTION CPU_Interrupt_Disable(uint32_t irq_num) -{ - if (irq_num >= IRQn_LAST) { - //MSG("Error! This interrupt don't support!\n"); - } else { - if (irq_num >= CPU_LP_MAX_IRQ_NUM) { - irq_num -= 32; - } - -#ifdef CONFIG_SYSTEM_SECURE - csi_vic_disable_sirq(irq_num); -#else - csi_vic_disable_irq(irq_num); -#endif - } -} - -/** - \brief Clear Pending Interrupt - \details Clear the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -void ATTR_TCM_SECTION CPU_Interrupt_Pending_Clear(uint32_t irq_num) -{ - if (irq_num >= IRQn_LAST) { - //MSG("Error! This interrupt don't support!\n"); - return; - } else { -#ifdef CONFIG_SYSTEM_SECURE - csi_vic_clear_pending_irq(irq_num); -#else - csi_vic_clear_pending_irq(irq_num); -#endif - } -} - -void System_Interrupt_Init(void) -{ - for (uintptr_t irq = 0; irq < IRQn_LAST; irq++) { - g_irqvector[irq] = Interrupt_Default_Handler; - } -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/source/irq_ctx.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/source/irq_ctx.h deleted file mode 100644 index 909a05658e..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/source/irq_ctx.h +++ /dev/null @@ -1,172 +0,0 @@ -#ifndef __IRQ_CTX_H__ -#define __IRQ_CTX_H__ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Processor PC */ - -#define REG_EPC_NDX 0 - -/* General pupose registers - * $0: Zero register does not need to be saved - * $1: ra (return address) - */ - -#define REG_X1_NDX 1 - -/* $2: Stack POinter - * $3: Global Pointer - * $4: Thread Pointer - */ - -#define REG_X2_NDX 2 -#define REG_X3_NDX 3 -#define REG_X4_NDX 4 - -/* $5-$7 = t0-t3: Temporary registers */ - -#define REG_X5_NDX 5 -#define REG_X6_NDX 6 -#define REG_X7_NDX 7 - -/* $8: s0 / fp Frame pointer */ - -#define REG_X8_NDX 8 - -/* $89 s1 Saved register */ - -#define REG_X9_NDX 9 - -/* $10-$17 = a0-a7: Argument registers */ - -#define REG_X10_NDX 10 -#define REG_X11_NDX 11 -#define REG_X12_NDX 12 -#define REG_X13_NDX 13 -#define REG_X14_NDX 14 -#define REG_X15_NDX 15 - -/* Interrupt Context register */ - -#define REG_INT_CTX_NDX 16 - -#define INT_XCPT_REGS 17 - -#define INT_XCPT_SIZE (4 * INT_XCPT_REGS) - -#define XCPTCONTEXT_REGS (INT_XCPT_REGS) - -#define XCPTCONTEXT_SIZE (4 * XCPTCONTEXT_REGS) - -/* In assembly language, values have to be referenced as byte address - * offsets. But in C, it is more convenient to reference registers as - * register save table offsets. - */ - -#ifdef __ASSEMBLY__ -#define REG_EPC (4 * REG_EPC_NDX) -#define REG_X1 (4 * REG_X1_NDX) -#define REG_X2 (4 * REG_X2_NDX) -#define REG_X3 (4 * REG_X3_NDX) -#define REG_X4 (4 * REG_X4_NDX) -#define REG_X5 (4 * REG_X5_NDX) -#define REG_X6 (4 * REG_X6_NDX) -#define REG_X7 (4 * REG_X7_NDX) -#define REG_X8 (4 * REG_X8_NDX) -#define REG_X9 (4 * REG_X9_NDX) -#define REG_X10 (4 * REG_X10_NDX) -#define REG_X11 (4 * REG_X11_NDX) -#define REG_X12 (4 * REG_X12_NDX) -#define REG_X13 (4 * REG_X13_NDX) -#define REG_X14 (4 * REG_X14_NDX) -#define REG_X15 (4 * REG_X15_NDX) -#define REG_INT_CTX (4 * REG_INT_CTX_NDX) - -#else -#define REG_EPC REG_EPC_NDX -#define REG_X1 REG_X1_NDX -#define REG_X2 REG_X2_NDX -#define REG_X3 REG_X3_NDX -#define REG_X4 REG_X4_NDX -#define REG_X5 REG_X5_NDX -#define REG_X6 REG_X6_NDX -#define REG_X7 REG_X7_NDX -#define REG_X8 REG_X8_NDX -#define REG_X9 REG_X9_NDX -#define REG_X10 REG_X10_NDX -#define REG_X11 REG_X11_NDX -#define REG_X12 REG_X12_NDX -#define REG_X13 REG_X13_NDX -#define REG_X14 REG_X14_NDX -#define REG_X15 REG_X15_NDX -#define REG_INT_CTX REG_INT_CTX_NDX - -#endif - -/* Now define more user friendly alternative name that can be used either - * in assembly or C contexts. - */ - -/* $1 = ra: Return address */ - -#define REG_RA REG_X1 - -/* $2 = sp: The value of the stack pointer on return from the exception */ - -#define REG_SP REG_X2 - -/* $3 = gp: Only needs to be saved under conditions where there are - * multiple, per-thread values for the GP. - */ - -#define REG_GP REG_X3 - -/* $4 = tp: Thread Pointer */ - -#define REG_TP REG_X4 - -/* $5-$7 = t0-t2: Caller saved temporary registers */ - -#define REG_T0 REG_X5 -#define REG_T1 REG_X6 -#define REG_T2 REG_X7 - -/* $8 = either s0 or fp: Depends if a frame pointer is used or not */ - -#define REG_S0 REG_X8 -#define REG_FP REG_X8 - -/* $9 = s1: Caller saved register */ - -#define REG_S1 REG_X9 - -/* $10-$17 = a0-a7: Argument registers */ - -#define REG_A0 REG_X10 -#define REG_A1 REG_X11 -#define REG_A2 REG_X12 -#define REG_A3 REG_X13 -#define REG_A4 REG_X14 -#define REG_A5 REG_X15 - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Variables - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#endif /* __IRQ_CTX_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/source/system_bl808.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/source/system_bl808.c deleted file mode 100644 index 2db677c54c..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/source/system_bl808.c +++ /dev/null @@ -1,84 +0,0 @@ -#include "bl808.h" -#include "bl808_clock.h" -#ifdef BOOTROM -#include "bflb_bootrom.h" -#endif - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define SYSTEM_CLOCK (16000000UL) - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ - -void System_BOR_Init(void) -{ - //HBN_BOR_CFG_Type borCfg = {1/* pu_bor */, 0/* irq_bor_en */, 1/* bor_vth */, 1/* bor_sel */}; - //HBN_Set_BOR_Cfg(&borCfg); -} - -void System_Core_Clock_Set(BL_System_Clock_Type type, uint32_t clock) -{ - Clock_Cfg_Type *pClk = (Clock_Cfg_Type *)SYS_CLOCK_CFG_ADDR; - - CHECK_PARAM(IS_BL_SYSTEM_CLOCK_TYPE(type)); - - if (type < BL_SYSTEM_CLOCK_MAX) { - pClk->systemClock[type] = clock; - pClk->magic = SYS_CLOCK_CFG_MAGIC; - } -} - -void System_Init(void) -{ - uint32_t i = 0; - - /* get interrupt level from info */ - CLIC->CLICCFG = (((CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos) << CLIC_CLICCFG_NLBIT_Pos); - - /* Every interrupt should be clear by software*/ - for (i = 0; i < IRQn_LAST; i++) { - CLIC->CLICINT[i].IP = 0; - CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */ - } - - /* tspend interrupt will be clear auto*/ - /* tspend use positive interrupt */ - CLIC->CLICINT[MSOFT_IRQn].ATTR = 0x3; - - //csi_dcache_enable(); - //csi_icache_enable(); - //CPU_Interrupt_Enable(MSOFT_IRQn); - - /* init bor for all platform */ - System_BOR_Init(); -} - -void System_Post_Init(void) -{ - System_Interrupt_Init(); - - /* global IRQ enable */ - __enable_irq(); -} - -void System_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) -{ - if (IRQn >= CPU_LP_MAX_IRQ_NUM) { - IRQn -= 32; - } - - csi_vic_set_prio(IRQn, PreemptPriority); -} - -int32_t drv_get_cpu_id(void) -{ - return __get_MHARTID(); -} - -int32_t drv_get_cpu_freq(int32_t idx) -{ - return 16 * 1000 * 1000UL; -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/source/system_bl808.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/source/system_bl808.h deleted file mode 100644 index 2ed33137a7..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/source/system_bl808.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef __SYSTEM_BL808_H__ -#define __SYSTEM_BL808_H__ - -#define RV_EXCEPTION_NUM (16) -typedef uintptr_t (*exception_handler)(uintptr_t cause, uintptr_t val, uintptr_t *regs); -typedef void (*pFunc)(void); - -extern void System_Interrupt_Init(void); -extern void CPU_Interrupt_Enable(uint32_t irq_num); -extern void CPU_Interrupt_Disable(uint32_t irq_num); -extern void CPU_Interrupt_Pending_Clear(uint32_t irq_num); -void Interrupt_Handler_Register(IRQn_Type irq, pFunc interruptFun); -extern void System_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); - -exception_handler exception_handler_install(uintptr_t vec, exception_handler handler); - -int32_t drv_get_cpu_id(void); -int32_t drv_get_cpu_freq(int32_t idx); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/bl808_flash_dv.ld b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/bl808_flash_dv.ld deleted file mode 100644 index aebfaa8fc7..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/bl808_flash_dv.ld +++ /dev/null @@ -1,213 +0,0 @@ -/**************************************************************************************** -* @file flash.ld -* -* @brief This file is the link script file (gnuarm or armgcc). -* -* Copyright (C) BouffaloLab 2021 -* -**************************************************************************************** -*/ - -/* configure the CPU type */ -OUTPUT_ARCH( "riscv" ) -/* link with the standard c library */ -INPUT(-lc) -/* link with the standard GCC library */ -INPUT(-lgcc) -/* configure the entry point */ -ENTRY(Reset_Handler) - -StackSize = 0x0400; /* 1KB */ -HeapMinSize = 0x1000; /* 4KB */ - -MEMORY -{ - xip_memory (rx) : ORIGIN = 0x90000000, LENGTH = 32M - itcm_memory (rx) : ORIGIN = 0x62028000, LENGTH = 48K - dtcm_memory (rx) : ORIGIN = 0x62034000, LENGTH = 16K - ram_memory (!rx) : ORIGIN = 0x62038000, LENGTH = 32K - xram_memory (!rx) : ORIGIN = 0x40000000, LENGTH = 16K -} - -SECTIONS -{ - PROVIDE(__metal_chicken_bit = 0); - - .text : - { - . = ALIGN(4); - __text_code_start__ = .; - - KEEP (*(SORT_NONE(_start))) - KEEP (*(SORT_NONE(Reset_Handler))) - - *(.text) - *(.text.*) - - /*put .rodata**/ - *(EXCLUDE_FILE( *bl602_glb.o \ - *bl602_pds.o \ - *bl602_common.o \ - *bl602_sf_cfg.o \ - *bl602_sf_ctrl.o \ - *bl602_sflash.o \ - *bl602_xip_sflash.o \ - *bl602_ef_ctrl.o) .rodata*) - *(.rodata) - *(.rodata.*) - - *(.srodata) - *(.srodata.*) - - . = ALIGN(4); - __text_code_end__ = .; - } > xip_memory - - . = ALIGN(4); - __itcm_load_addr = .; - - .itcm_region : AT (__itcm_load_addr) - { - . = ALIGN(4); - __tcm_code_start__ = .; - - *(.tcm_code.*) - *(.tcm_const.*) - *(.sclock_rlt_code.*) - *(.sclock_rlt_const.*) - - *bl602_glb.o*(.rodata*) - *bl602_pds.o*(.rodata*) - *bl602_common.o*(.rodata*) - *bl602_sf_cfg.o*(.rodata*) - *bl602_sf_ctrl.o*(.rodata*) - *bl602_sflash.o*(.rodata*) - *bl602_xip_sflash.o*(.rodata*) - *bl602_ef_ctrl.o*(.rodata*) - - . = ALIGN(4); - __tcm_code_end__ = .; - } > itcm_memory - - __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region); - - .dtcm_region : AT (__dtcm_load_addr) - { - . = ALIGN(4); - __tcm_data_start__ = .; - - *(.tcm_data) - /* *finger_print.o(.data*) */ - - . = ALIGN(4); - __tcm_data_end__ = .; - } > dtcm_memory - - /*************************************************************************/ - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (NOLOAD): - { - . = ALIGN(0x4); - . = . + StackSize; - . = ALIGN(0x4); - } > dtcm_memory - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory); - PROVIDE( __freertos_irq_stack_top = __StackTop); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack") - /*************************************************************************/ - - __system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region); - - .system_ram_data_region : AT (__system_ram_load_addr) - { - . = ALIGN(4); - __system_ram_data_start__ = .; - - *(.system_ram) - - . = ALIGN(4); - __system_ram_data_end__ = .; - } > ram_memory - - .system_ram_noinit_data_region (NOLOAD) : - { - . = ALIGN(4); - *(.system_ram_noinit) - - . = ALIGN(4); - } > ram_memory - - __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region); - - /* Data section */ - RAM_DATA : AT (__ram_load_addr) - { - . = ALIGN(4); - __ram_data_start__ = .; - - PROVIDE( __global_pointer$ = . + 0x800 ); - - *(.data) - *(.data.*) - *(.sdata) - *(.sdata.*) - *(.sdata2) - *(.sdata2.*) - - . = ALIGN(4); - __ram_data_end__ = .; - } > ram_memory - - __etext_final = (__ram_load_addr + SIZEOF (RAM_DATA)); - ASSERT(__etext_final <= ORIGIN(code_memory) + LENGTH(code_memory), "code memory overflow") - - .bss (NOLOAD) : - { - . = ALIGN(4); - __bss_start__ = .; - - *(.bss*) - *(.sbss*) - *(COMMON) - - . = ALIGN(4); - __bss_end__ = .; - } > ram_memory - - .noinit_data (NOLOAD) : - { - . = ALIGN(4); - __noinit_data_start__ = .; - - *(.noinit_data*) - - . = ALIGN(4); - __noinit_data_end__ = .; - } > ram_memory - - .heap (NOLOAD): - { - . = ALIGN(4); - __HeapBase = .; - - /*__end__ = .;*/ - /*end = __end__;*/ - KEEP(*(.heap*)) - - . = ALIGN(4); - __HeapLimit = .; - } > ram_memory - - __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory); - ASSERT(__HeapLimit - __HeapBase >= HeapMinSize, "heap region overflow") - -} - diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/bl808_ram.ld b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/bl808_ram.ld deleted file mode 100644 index 60b6da837f..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/bl808_ram.ld +++ /dev/null @@ -1,221 +0,0 @@ -/**************************************************************************************** -* @file ram.ld -* -* @brief This file is the link script file (gnuarm or armgcc). -* -* Copyright (C) BouffaloLab 2021 -* -**************************************************************************************** -*/ - -/* configure the CPU type */ -OUTPUT_ARCH( "riscv" ) -/* link with the standard c library */ -INPUT(-lc) -/* link with the standard GCC library */ -INPUT(-lgcc) -/* configure the entry point */ -ENTRY(Reset_Handler) - -StackSize = 0x0400; /* 1KB */ -HeapMinSize = 0x1000; /* 4KB */ - -MEMORY -{ - code_memory (rx) : ORIGIN = 0x62028000, LENGTH = 60K - itcm_memory (rx) : ORIGIN = 0x62028000, LENGTH = 60K - dtcm_memory (rx) : ORIGIN = 0x62037000, LENGTH = 4K - nocache_ram_memory (!rx) : ORIGIN = 0x22038000, LENGTH = 0K - ram_memory (!rx) : ORIGIN = 0x62038000, LENGTH = 160K-32K - xram_memory (!rx) : ORIGIN = 0x40000000, LENGTH = 16K -} - -SECTIONS -{ - - .text : - { - . = ALIGN(4); - __text_code_start__ = .; - KEEP(*startup*.*o(*.text*)) - KEEP (*(SORT_NONE(_start))) - KEEP (*(SORT_NONE(Reset_Handler))) - - *(.text) - *(.text.*) - - /* section information for shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - - /* section information for usb desc */ - . = ALIGN(4); - _usb_desc_start = .; - KEEP(*(usb_desc)) - . = ALIGN(4); - _usb_desc_end = .; - - - *(.rodata) - *(.rodata.*) - - *(.srodata) - *(.srodata.*) - - . = ALIGN(4); - __text_code_end__ = .; - } > code_memory - - . = ALIGN(4); - __itcm_load_addr = .; - - .itcm_region : AT (__itcm_load_addr) - { - . = ALIGN(4); - __tcm_code_start__ = .; - - . = ALIGN(4); - __tcm_code_end__ = .; - } > itcm_memory - - __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region); - - .dtcm_region : AT (__dtcm_load_addr) - { - . = ALIGN(4); - __tcm_data_start__ = .; - - *(.tcm_data) - /* *finger_print.o(.data*) */ - - . = ALIGN(4); - __tcm_data_end__ = .; - } > dtcm_memory - - /*************************************************************************/ - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (NOLOAD): - { - . = ALIGN(0x4); - . = . + StackSize; - . = ALIGN(0x4); - } > dtcm_memory - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory); - PROVIDE( __freertos_irq_stack_top = __StackTop); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack") - /*************************************************************************/ - __nocache_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region); - - .nocache_ram_region (NOLOAD) : AT (__nocache_ram_load_addr) - { - . = ALIGN(4); - __nocache_ram_data_start__ = .; - - *(.nocache_ram) - - . = ALIGN(4); - __nocache_ram_data_end__ = .; - } > nocache_ram_memory - - __system_ram_load_addr = __nocache_ram_load_addr + SIZEOF(.nocache_ram_region); - - .system_ram_data_region : AT (__system_ram_load_addr) - { - . = ALIGN(4); - __system_ram_data_start__ = .; - - *(.system_ram) - - . = ALIGN(4); - __system_ram_data_end__ = .; - } > ram_memory - - .system_ram_noinit_data_region (NOLOAD) : - { - . = ALIGN(4); - *(.system_ram_noinit) - - . = ALIGN(4); - } > ram_memory - - __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region); - - /* Data section */ - RAM_DATA : AT (__ram_load_addr) - { - . = ALIGN(4); - __ram_data_start__ = .; - - PROVIDE( __global_pointer$ = . + 0x800 ); - - *(.data) - *(.data.*) - *(.sdata) - *(.sdata.*) - *(.sdata2) - *(.sdata2.*) - - . = ALIGN(4); - __ram_data_end__ = .; - } > ram_memory - - __etext_final = (__ram_load_addr + SIZEOF (RAM_DATA)); - ASSERT(__etext_final <= ORIGIN(code_memory) + LENGTH(code_memory), "code memory overflow") - - .bss (NOLOAD) : - { - . = ALIGN(4); - __bss_start__ = .; - - *(.bss*) - *(.sbss*) - *(COMMON) - - . = ALIGN(4); - __bss_end__ = .; - } > ram_memory - - .noinit_data (NOLOAD) : - { - . = ALIGN(4); - __noinit_data_start__ = .; - - *(.noinit_data*) - - . = ALIGN(4); - __noinit_data_end__ = .; - } > ram_memory - - .heap (NOLOAD): - { - . = ALIGN(4); - __HeapBase = .; - - /*__end__ = .;*/ - /*end = __end__;*/ - KEEP(*(.heap*)) - - . = ALIGN(4); - __HeapLimit = .; - } > ram_memory - - __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory); - ASSERT(__HeapLimit - __HeapBase >= HeapMinSize, "heap region overflow") - -} - diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/bl808_ram_dv.ld b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/bl808_ram_dv.ld deleted file mode 100644 index d27ef9b8d9..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/bl808_ram_dv.ld +++ /dev/null @@ -1,195 +0,0 @@ -/**************************************************************************************** -* @file ram.ld -* -* @brief This file is the link script file (gnuarm or armgcc). -* -* Copyright (C) BouffaloLab 2021 -* -**************************************************************************************** -*/ - -/* configure the CPU type */ -OUTPUT_ARCH( "riscv" ) -/* link with the standard c library */ -INPUT(-lc) -/* link with the standard GCC library */ -INPUT(-lgcc) -/* configure the entry point */ -ENTRY(Reset_Handler) - -StackSize = 0x0400; /* 1KB */ -HeapMinSize = 0x1000; /* 4KB */ - -MEMORY -{ - code_memory (rx) : ORIGIN = 0x90000000, LENGTH = 48K - itcm_memory (rx) : ORIGIN = 0x22020000, LENGTH = 48K - dtcm_memory (rx) : ORIGIN = 0x2202C000, LENGTH = 16K - ram_memory (!rx) : ORIGIN = 0x62038000, LENGTH = 32K - xram_memory (!rx) : ORIGIN = 0x40000000, LENGTH = 16K -} - -SECTIONS -{ - PROVIDE(__metal_chicken_bit = 0); - - .text : - { - . = ALIGN(4); - __text_code_start__ = .; - - KEEP (*(SORT_NONE(_start))) - KEEP (*(SORT_NONE(Reset_Handler))) - - *(.text) - *(.text.*) - - *(.rodata) - *(.rodata.*) - - *(.srodata) - *(.srodata.*) - - *(.tcm_code.*) - *(.tcm_const.*) - *(.sclock_rlt_code.*) - *(.sclock_rlt_const.*) - - . = ALIGN(4); - __text_code_end__ = .; - } > code_memory - - . = ALIGN(4); - __itcm_load_addr = .; - - .itcm_region : AT (__itcm_load_addr) - { - . = ALIGN(4); - __tcm_code_start__ = .; - - . = ALIGN(4); - __tcm_code_end__ = .; - } > itcm_memory - - __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region); - - .dtcm_region : AT (__dtcm_load_addr) - { - . = ALIGN(4); - __tcm_data_start__ = .; - - *(.tcm_data) - /* *finger_print.o(.data*) */ - - . = ALIGN(4); - __tcm_data_end__ = .; - } > dtcm_memory - - /*************************************************************************/ - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (NOLOAD): - { - . = ALIGN(0x4); - . = . + StackSize; - . = ALIGN(0x4); - } > dtcm_memory - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory); - PROVIDE( __freertos_irq_stack_top = __StackTop); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack") - /*************************************************************************/ - - __system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region); - - .system_ram_data_region : AT (__system_ram_load_addr) - { - . = ALIGN(4); - __system_ram_data_start__ = .; - - *(.system_ram) - - . = ALIGN(4); - __system_ram_data_end__ = .; - } > ram_memory - - .system_ram_noinit_data_region (NOLOAD) : - { - . = ALIGN(4); - *(.system_ram_noinit) - - . = ALIGN(4); - } > ram_memory - - __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region); - - /* Data section */ - RAM_DATA : AT (__ram_load_addr) - { - . = ALIGN(4); - __ram_data_start__ = .; - - PROVIDE( __global_pointer$ = . + 0x800 ); - - *(.data) - *(.data.*) - *(.sdata) - *(.sdata.*) - *(.sdata2) - *(.sdata2.*) - - . = ALIGN(4); - __ram_data_end__ = .; - } > ram_memory - - __etext_final = (__ram_load_addr + SIZEOF (RAM_DATA)); - ASSERT(__etext_final <= ORIGIN(code_memory) + LENGTH(code_memory), "code memory overflow") - - .bss (NOLOAD) : - { - . = ALIGN(4); - __bss_start__ = .; - - *(.bss*) - *(.sbss*) - *(COMMON) - - . = ALIGN(4); - __bss_end__ = .; - } > ram_memory - - .noinit_data (NOLOAD) : - { - . = ALIGN(4); - __noinit_data_start__ = .; - - *(.noinit_data*) - - . = ALIGN(4); - __noinit_data_end__ = .; - } > ram_memory - - .heap (NOLOAD): - { - . = ALIGN(4); - __HeapBase = .; - - /*__end__ = .;*/ - /*end = __end__;*/ - KEEP(*(.heap*)) - - . = ALIGN(4); - __HeapLimit = .; - } > ram_memory - - __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory); - ASSERT(__HeapLimit - __HeapBase >= HeapMinSize, "heap region overflow") - -} - diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/bl808_rom.ld b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/bl808_rom.ld deleted file mode 100644 index 64ca7f6f7c..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/bl808_rom.ld +++ /dev/null @@ -1,195 +0,0 @@ -/**************************************************************************************** -* @file ram.ld -* -* @brief This file is the link script file (gnuarm or armgcc). -* -* Copyright (C) BouffaloLab 2021 -* -**************************************************************************************** -*/ - -/* configure the CPU type */ -OUTPUT_ARCH( "riscv" ) -/* link with the standard c library */ -INPUT(-lc) -/* link with the standard GCC library */ -INPUT(-lgcc) -/* configure the entry point */ -ENTRY(Reset_Handler) - -StackSize = 0x0400; /* 1KB */ -HeapMinSize = 0x1000; /* 4KB */ - -MEMORY -{ - code_memory (rx) : ORIGIN = 0x90000000, LENGTH = 128K - itcm_memory (rx) : ORIGIN = 0x62028000, LENGTH = 1K - dtcm_memory (rx) : ORIGIN = 0x62030000, LENGTH = 4K - ram_memory (!rx) : ORIGIN = 0x62031000, LENGTH = 124K - xram_memory (!rx) : ORIGIN = 0x40000000, LENGTH = 16K -} - -SECTIONS -{ - PROVIDE(__metal_chicken_bit = 0); - - .text : - { - . = ALIGN(4); - __text_code_start__ = .; - - KEEP (*(SORT_NONE(_start))) - KEEP (*(SORT_NONE(Reset_Handler))) - - *(.text) - *(.text.*) - - *(.rodata) - *(.rodata.*) - - *(.srodata) - *(.srodata.*) - - *(.tcm_code.*) - *(.tcm_const.*) - *(.sclock_rlt_code.*) - *(.sclock_rlt_const.*) - - . = ALIGN(4); - __text_code_end__ = .; - } > code_memory - - . = ALIGN(4); - __itcm_load_addr = .; - - .itcm_region : AT (__itcm_load_addr) - { - . = ALIGN(4); - __tcm_code_start__ = .; - - . = ALIGN(4); - __tcm_code_end__ = .; - } > itcm_memory - - __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region); - - .dtcm_region : AT (__dtcm_load_addr) - { - . = ALIGN(4); - __tcm_data_start__ = .; - - *(.tcm_data) - /* *finger_print.o(.data*) */ - - . = ALIGN(4); - __tcm_data_end__ = .; - } > dtcm_memory - - /*************************************************************************/ - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (NOLOAD): - { - . = ALIGN(0x4); - . = . + StackSize; - . = ALIGN(0x4); - } > dtcm_memory - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory); - PROVIDE( __freertos_irq_stack_top = __StackTop); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack") - /*************************************************************************/ - - __system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region); - - .system_ram_data_region : AT (__system_ram_load_addr) - { - . = ALIGN(4); - __system_ram_data_start__ = .; - - *(.system_ram) - - . = ALIGN(4); - __system_ram_data_end__ = .; - } > ram_memory - - .system_ram_noinit_data_region (NOLOAD) : - { - . = ALIGN(4); - *(.system_ram_noinit) - - . = ALIGN(4); - } > ram_memory - - __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region); - - /* Data section */ - RAM_DATA : AT (__ram_load_addr) - { - . = ALIGN(4); - __ram_data_start__ = .; - - PROVIDE( __global_pointer$ = . + 0x800 ); - - *(.data) - *(.data.*) - *(.sdata) - *(.sdata.*) - *(.sdata2) - *(.sdata2.*) - - . = ALIGN(4); - __ram_data_end__ = .; - } > ram_memory - - __etext_final = (__ram_load_addr + SIZEOF (RAM_DATA)); - ASSERT(__etext_final <= ORIGIN(code_memory) + LENGTH(code_memory), "code memory overflow") - - .bss (NOLOAD) : - { - . = ALIGN(4); - __bss_start__ = .; - - *(.bss*) - *(.sbss*) - *(COMMON) - - . = ALIGN(4); - __bss_end__ = .; - } > ram_memory - - .noinit_data (NOLOAD) : - { - . = ALIGN(4); - __noinit_data_start__ = .; - - *(.noinit_data*) - - . = ALIGN(4); - __noinit_data_end__ = .; - } > ram_memory - - .heap (NOLOAD): - { - . = ALIGN(4); - __HeapBase = .; - - /*__end__ = .;*/ - /*end = __end__;*/ - KEEP(*(.heap*)) - - . = ALIGN(4); - __HeapLimit = .; - } > ram_memory - - __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory); - ASSERT(__HeapLimit - __HeapBase >= HeapMinSize, "heap region overflow") - -} - diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/cpu_flags.cmake b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/cpu_flags.cmake deleted file mode 100644 index 45614d164c..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/cpu_flags.cmake +++ /dev/null @@ -1,20 +0,0 @@ -#CPU_ARCH := RISCV -#MCPU := e907 -#E906 rv32imacxthead ilp32 e907 -#E906F rv32imacfxthead ilp32f e907 -#E906FD rv32imacfdxthead ilp32d e907 - -SET(CPU_ARCH "RISCV") -SET(MCPU "e907") - -SET(MARCH "rv32imafcpzpsfoperand_xtheade") -SET(MABI "ilp32f") - -list(APPEND GLOBAL_C_FLAGS -march=${MARCH} -mabi=${MABI} -mtune=${MCPU}) -list(APPEND GLOBAL_LD_FLAGS -march=${MARCH} -mabi=${MABI} -mtune=${MCPU}) - -SET(LINKER_SCRIPT ${CMAKE_SOURCE_DIR}/drivers/bl808_driver/startup/m0/bl808_flash.ld) -#SET(LINKER_SCRIPT ${CMAKE_SOURCE_DIR}/drivers/bl808_driver/startup/m0/bl808_rom.ld) -#SET(LINKER_SCRIPT ${CMAKE_SOURCE_DIR}/drivers/bl808_driver/startup/m0/bl808_flash.ld) -#SET(LINKER_SCRIPT ${CMAKE_SOURCE_DIR}/drivers/bl808_driver/startup/m0/bl808_ram_dv.ld) -#SET(LINKER_SCRIPT ${CMAKE_SOURCE_DIR}/drivers/bl808_driver/startup/m0/bl808_flash_dv.ld) \ No newline at end of file diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/source/GCC/startup.S b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/source/GCC/startup.S deleted file mode 100644 index 7275d29aa7..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/source/GCC/startup.S +++ /dev/null @@ -1,168 +0,0 @@ -/* - * Copyright (C) 2016-2020 Bouffalo Lab - */ - /* stack for IRQs */ - .extern g_irq_sp - -_start: - .text - .align 2 - .globl Reset_Handler - .type Reset_Handler, %function -Reset_Handler: -.option push -.option norelax - la gp, __global_pointer$ -.option pop - csrci mstatus, 8 - /* TODO: debug */ - csrw mcycle, zero - csrw mcycleh, zero - csrw minstret, zero - csrw minstreth, zero -#ifndef __NO_HBN_RECV_IN_STARTUP - /* clear hbn ram ret/slp */ - /* 0x2000F034[7:6] = 0 */ - li a0, 0x2000F034 - li a2, 0xFFFFFF3F - lw a1, 0(a0) - and a1, a1, a2 - sw a1, 0(a0) - - /* clear pds ram ret/slp */ - /* 0x2000E020[31:30][7:0] = 0 */ - li a0, 0x2000E020 - li a2, 0x3FFFFF00 - lw a1, 0(a0) - and a1, a1, a2 - sw a1, 0(a0) - /* 0x2000E028[19:0] = 0 */ - li a0, 0x2000E028 - li a2, 0xFFF00000 - lw a1, 0(a0) - and a1, a1, a2 - sw a1, 0(a0) - - /* load efuse value:if bit[31] is 1,can not jump */ - li a0, 0x2005605C - lw a0, 0(a0) - srli a0, a0, 0x1b - andi a0, a0, 0x10 - li t0, 0x10 - beq t0, a0, .HBN_NOT_JUMP - - /* check hbn mode */ - li a0, 0x2000f100 - lw a0, 0(a0) - li t0, 0x4e424845 - bne t0, a0, .HBN_NOT_JUMP - li a1, 0x4e424857 - li a2, 0x2000f100 - sw a1, 0(a2) - - /* we can jump unless it's not 0 or 0xffffffff */ - li a0, 0x2000f104 - lw a0, 0(a0) - addi t0, a0, -1 - li t1, -3 - bltu t1, t0, .HBN_NOT_JUMP - jalr a0 - -.HBN_NOT_JUMP: - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - /* - li a0, 0x40000060 - li t0, 0x00206F00 - sw t0, 0(a0) - */ - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop -#endif - - /* mtvec: for all exceptions and non-vector mode IRQs */ - la a0, Default_Handler - ori a0, a0, 3 - csrw mtvec, a0 - - /* mtvt: for all vector mode IRQs */ - la a0, __Vectors - csrw mtvt, a0 - -#if defined(__riscv_flen) - /* FP: initial state */ - csrr t0, mstatus - li t1, ~0x6000 - and t0, t0, t1 - li t1, 0x2000 - or t0, t0, t1 - csrw mstatus, t0 - /* csrwi fcsr, 0 */ -#endif - - .weak __StackTop - la sp, __StackTop - /* stack: 16-byte aligned */ - andi sp, sp, -16 - la t0, g_irq_sp - /* utilizes the stack point auto-exchange feature */ - csrw mscratch, t0 - - /* Load data section removed */ - - /* Clear bss section removed */ - -#ifndef __NO_SYSTEM_INIT - jal System_Init -#endif - - /* start load code to itcm like. */ - jal start_load - -#ifndef __NO_BOARD_INIT - jal System_Post_Init -#endif - - jal main - - .size Reset_Handler, . - Reset_Handler - -__exit: - j __exit - diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/source/interrupt.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/source/interrupt.c deleted file mode 100644 index cb93179e59..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/source/interrupt.c +++ /dev/null @@ -1,343 +0,0 @@ -#include -#include -#include -#include -#include -#include "bl808_glb.h" -#include "irq_ctx.h" - -typedef void (*pFunc)(void); -void NMI_Handler(void); - -/* - * g_irqvector is the real ISRs written in simple C style: no __attribute__ ((interrupt)) needed! - * An when IRQ is in vector mode, the __Vectors is the pesudo handler entry, which redirects the CPU - * to a single handler: Default_IRQHandler, and who will call the corresponding ISR in g_irqvector, - * as well as context save/restore work. - * BTW, some of the special IRQs have different solutions, such as mtime for the RTOS "tick". - */ -pFunc g_irqvector[IRQn_LAST] __attribute__((section(".noinit_data"))); -pFunc g_nmivector = NMI_Handler; - -extern void Default_IRQHandler(void); -extern void Default_Handler(void); -extern void Mtspend_Handler(); - - -const pFunc __Vectors[] __attribute__((section(".init"), aligned(64))) = { - Default_Handler, /* */ - Default_Handler, /* */ - Default_Handler, /* */ -#if defined(__OS_FREERTOS__) - Mtspend_Handler, /* 3: M-mode Soft IRQ */ -#else - Default_IRQHandler, /* 3: M-mode Soft IRQ */ -#endif - Default_Handler, /* */ - Default_Handler, /* */ - Default_Handler, /* */ - Default_IRQHandler, /* 7: M-mode Timer IRQ */ - Default_Handler, /* */ - Default_Handler, /* */ - Default_Handler, /* */ - Default_Handler, /* */ - Default_Handler, /* */ - Default_Handler, /* */ - Default_Handler, /* */ - Default_Handler, /* */ - - Default_IRQHandler, //BMX_ERR_IRQHandler_Wrapper, /* 16 + 0 */ - Default_IRQHandler, //BMX_TO_IRQHandler_Wrapper, /* 16 + 1 */ - Default_IRQHandler, //L1C_BMX_ERR_IRQHandler_Wrapper, /* 16 + 2 */ - Default_IRQHandler, //L1C_BMX_TO_IRQHandler_Wrapper, /* 16 + 3 */ - Default_IRQHandler, //SEC_BMX_ERR_IRQHandler_Wrapper, /* 16 + 4 */ - Default_IRQHandler, //RF_TOP_INT0_IRQHandler_Wrapper, /* 16 + 5 */ - Default_IRQHandler, //RF_TOP_INT1_IRQHandler_Wrapper, /* 16 + 6 */ - Default_IRQHandler, //SDIO_IRQHandler_Wrapper, /* 16 + 7 */ - Default_IRQHandler, //DMA_BMX_ERR_IRQHandler_Wrapper, /* 16 + 8 */ - Default_IRQHandler, //SEC_GMAC_IRQHandler_Wrapper, /* 16 + 9 */ - Default_IRQHandler, //SEC_CDET_IRQHandler_Wrapper, /* 16 + 10 */ - Default_IRQHandler, //SEC_PKA_IRQHandler_Wrapper, /* 16 + 11 */ - Default_IRQHandler, //SEC_TRNG_IRQHandler_Wrapper, /* 16 + 12 */ - Default_IRQHandler, //SEC_AES_IRQHandler_Wrapper, /* 16 + 13 */ - Default_IRQHandler, //SEC_SHA_IRQHandler_Wrapper, /* 16 + 14 */ - Default_IRQHandler, //DMA_ALL_IRQHandler_Wrapper, /* 16 + 15 */ - Default_IRQHandler, //0, /* 16 + 16 */ - Default_IRQHandler, //0, /* 16 + 17 */ - Default_IRQHandler, //0, /* 16 + 18 */ - Default_IRQHandler, //IRTX_IRQHandler_Wrapper, /* 16 + 19 */ - Default_IRQHandler, //IRRX_IRQHandler_Wrapper, /* 16 + 20 */ - Default_IRQHandler, //0, /* 16 + 21 */ - Default_IRQHandler, //0, /* 16 + 22 */ - Default_IRQHandler, //SF_CTRL_IRQHandler_Wrapper, /* 16 + 23 */ - Default_IRQHandler, //0, /* 16 + 24 */ - Default_IRQHandler, //GPADC_DMA_IRQHandler_Wrapper, /* 16 + 25 */ - Default_IRQHandler, //EFUSE_IRQHandler_Wrapper, /* 16 + 26 */ - Default_IRQHandler, //SPI_IRQHandler_Wrapper, /* 16 + 27 */ - Default_IRQHandler, //0, /* 16 + 28 */ - Default_IRQHandler, //UART0_IRQHandler_Wrapper, /* 16 + 29 */ - Default_IRQHandler, //UART1_IRQHandler_Wrapper, /* 16 + 30 */ - Default_IRQHandler, //0, /* 16 + 31 */ - Default_IRQHandler, //I2C_IRQHandler_Wrapper, /* 16 + 32 */ - Default_IRQHandler, //0, /* 16 + 33 */ - Default_IRQHandler, //PWM_IRQHandler_Wrapper, /* 16 + 34 */ - Default_IRQHandler, //0, /* 16 + 35 */ - Default_IRQHandler, //TIMER_CH0_IRQHandler_Wrapper, /* 16 + 36 */ - Default_IRQHandler, //TIMER_CH1_IRQHandler_Wrapper, /* 16 + 37 */ - Default_IRQHandler, //TIMER_WDT_IRQHandler_Wrapper, /* 16 + 38 */ - Default_IRQHandler, //0, /* 16 + 39 */ - Default_IRQHandler, //0, /* 16 + 40 */ - Default_IRQHandler, //0, /* 16 + 41 */ - Default_IRQHandler, //0, /* 16 + 42 */ - Default_IRQHandler, //0, /* 16 + 43 */ - Default_IRQHandler, //GPIO_INT0_IRQHandler_Wrapper, /* 16 + 44 */ - Default_IRQHandler, //0, /* 16 + 45 */ - Default_IRQHandler, //0, /* 16 + 46 */ - Default_IRQHandler, //0, /* 16 + 47 */ - Default_IRQHandler, //0, /* 16 + 48 */ - Default_IRQHandler, //0, /* 16 + 49 */ - Default_IRQHandler, //PDS_WAKEUP_IRQHandler_Wrapper, /* 16 + 50 */ - Default_IRQHandler, //HBN_OUT0_IRQHandler_Wrapper, /* 16 + 51 */ - Default_IRQHandler, //HBN_OUT1_IRQHandler_Wrapper, /* 16 + 52 */ - Default_IRQHandler, //BOR_IRQHandler_Wrapper, /* 16 + 53 */ - Default_IRQHandler, //WIFI_IRQHandler_Wrapper, /* 16 + 54 */ - Default_IRQHandler, //BZ_PHY_IRQHandler_Wrapper, /* 16 + 55 */ - Default_IRQHandler, //BLE_IRQHandler_Wrapper, /* 16 + 56 */ - Default_IRQHandler, //MAC_TXRX_TIMER_IRQHandler_Wrapper, /* 16 + 57 */ - Default_IRQHandler, //MAC_TXRX_MISC_IRQHandler_Wrapper, /* 16 + 58 */ - Default_IRQHandler, //MAC_RX_TRG_IRQHandler_Wrapper, /* 16 + 59 */ - Default_IRQHandler, //MAC_TX_TRG_IRQHandler_Wrapper, /* 16 + 60 */ - Default_IRQHandler, //MAC_GEN_IRQHandler_Wrapper, /* 16 + 61 */ - Default_IRQHandler, //MAC_PORT_TRG_IRQHandler_Wrapper, /* 16 + 62 */ - Default_IRQHandler, //WIFI_IPC_PUBLIC_IRQHandler_Wrapper, /* 16 + 63 */ -}; - -/** - \brief the default IRQ handler. - \param[in] cause Number of IRQ. - \return no return. -*/ -void Interrupt_Default_Handler(uintptr_t cause) __attribute__((weak)); -void Interrupt_Default_Handler(uintptr_t cause) -{ - /* un-handled external IRQ */ - MSG("Enter interrupt default handler %x\r\n", cause); -} - -/** - \brief the default Trap handler. - \param[in] cause Number of Trap. - \param[in] val from mtval reg. - \param[in] regs CPU context of the Trap. - \return no return. -*/ -static uintptr_t exception_handler_default(uintptr_t cause, uintptr_t val, uintptr_t *regs); -static uintptr_t exception_handler_default(uintptr_t cause, uintptr_t val, uintptr_t *regs) -{ - uint32_t mepc_val; - - /* 0x80000000-0x90000000 is protected by PMP for CPU Prefetching */ - if(val>=0x80000000&&val<0x90000000){ - uint32_t tmp_cause=cause&0xf; - if(tmp_cause==0x01||tmp_cause==0x05){ - /*Instruction access fault or Load access fault*/ - mepc_val=BL_RD_WORD(regs[REG_EPC_NDX]); - if((mepc_val&0x03)==0x03){ - regs[REG_EPC_NDX] += 4; - }else{ - regs[REG_EPC_NDX] += 2; - } - return 0; - } - } - - MSG("\n\rUn-handled Exception on CPU %d:\n\r", GLB_Get_Core_Type()); - - MSG("cause: 0x%8x, tval = 0x%8x, epc = 0x%8x\n\r", cause, val, regs[REG_EPC_NDX]); -#ifndef CONFIG_ERR_NOT_DUMP_MCAUSE_INFO - const char *mcause_str[] = { - "Instruction address misaligned", - "Instruction access fault", - "Illegal instruction", - "Breakpoint", - "Load address misaligned", - "Load access fault", - "Store/AMO address misaligned", - "Store/AMO access fault", - "Environment call from U-mode", - "Environment call from S-mode", - "RSVD", - "Environment call from M-mode", - "Instruction page fault", - "Load page fault", - "RSVD", - "Store/AMO page fault" - }; - if ((cause & 0xf)) - MSG("%s\r\n\r\n", mcause_str[cause & 0xf]); -#endif - -// clang-format off -#ifndef CONFIG_ERR_NOT_DUMP_ALL_REGS - MSG("ra = 0x%08x ", regs[REG_RA]); MSG("sp = 0x%08x ", regs[REG_SP]); MSG("gp = 0x%08x ", regs[REG_GP]); - MSG("tp = 0x%08x ", regs[REG_TP]); MSG("\n\r"); - - MSG("t0 = 0x%08x ", regs[REG_T0]); MSG("t1 = 0x%08x ", regs[REG_T1]); MSG("t2 = 0x%08x ", regs[REG_T2]); - MSG("t3 = 0x%08x ", regs[REG_T3]); MSG("\n\r"); - MSG("t4 = 0x%08x ", regs[REG_T4]); MSG("t5 = 0x%08x ", regs[REG_T5]); MSG("t6 = 0x%08x ", regs[REG_T6]); - MSG("\n\r"); - - MSG("a0 = 0x%08x ", regs[REG_A0]); MSG("a1 = 0x%08x ", regs[REG_A1]); MSG("a2 = 0x%08x ", regs[REG_A2]); - MSG("a3 = 0x%08x ", regs[REG_A3]); MSG("\n\r"); - MSG("a4 = 0x%08x ", regs[REG_A4]); MSG("a5 = 0x%08x ", regs[REG_A5]); MSG("a6 = 0x%08x ", regs[REG_A6]); - MSG("a7 = 0x%08x ", regs[REG_A7]); MSG("\n\r"); - - MSG("s0 = 0x%08x ", regs[REG_S0]); MSG("s1 = 0x%08x ", regs[REG_S1]); MSG("s2 = 0x%08x ", regs[REG_S2]); - MSG("s3 = 0x%08x ", regs[REG_S3]); MSG("\n\r"); - MSG("s4 = 0x%08x ", regs[REG_S4]); MSG("s5 = 0x%08x ", regs[REG_S5]); MSG("s6 = 0x%08x ", regs[REG_S6]); - MSG("s7 = 0x%08x ", regs[REG_S7]); MSG("\n\r"); - MSG("s8 = 0x%08x ", regs[REG_S8]); MSG("s9 = 0x%08x ", regs[REG_S9]); MSG("s10 = 0x%08x ", regs[REG_S10]); - MSG("s11 = 0x%08x ", regs[REG_S11]); MSG("\n\r"); -#endif - // clang-format on - - while (1) - ; -} - -/** - \brief the trap handler for ecall from M-mode. - \param[in] cause Number of Trap. - \param[in] val from mtval reg. - \param[in] regs CPU context of the Trap. - \return no return. -*/ -static uintptr_t exception_handler_ECALL_M(uintptr_t cause, uintptr_t val, uintptr_t *regs) -{ - regs[REG_EPC_NDX] += 4; - __asm volatile("nop" :: - : "memory"); - - /* indicated ecall from Machine-Mode */ - regs[REG_A0] = 1; - return 0; -} - -static exception_handler exception_handlers[RV_EXCEPTION_NUM] = { - exception_handler_default, /* 0: Instruction Address Misaligned */ - exception_handler_default, /* 1: Instruction Access Fault */ - exception_handler_default, /* 2: Illegal Instruction */ - exception_handler_default, /* 3: Breakpoint */ - exception_handler_default, /* 4: Load Address Misaligned */ - exception_handler_default, /* 5: Load Access Fault */ - exception_handler_default, /* 6: Store/AMO Address Misaligned */ - exception_handler_default, /* 7: Store/AMO Access Fault */ - exception_handler_default, /* 8: Environment Call from U-mode */ - exception_handler_default, /* 9: Environment Call from S-mode */ - exception_handler_default, /* 10: Environment Call from H-mode */ - exception_handler_ECALL_M, /* 11: Environment Call from M-mode */ - exception_handler_default, /* 12: Instruction Page Fault */ - exception_handler_default, /* 13: Load Page Fault */ - exception_handler_default, /* 14: Reserved */ - exception_handler_default, /* 15: Store/AMO Page Fault */ -}; - -/** - \brief install handler to Trap handler. - \param[in] vec Number of Trap. - \param[in] handler the handler for Trap. - \return the previous handler. -*/ -exception_handler exception_handler_install(uintptr_t vec, exception_handler handler) -{ - exception_handler previous = NULL; - - if (RV_EXCEPTION_NUM > vec) { - previous = exception_handlers[vec]; - exception_handlers[vec] = handler; - } - - return previous; -} - -/** - \brief C handler for CPU Traps. - \param[in] regs is the CPU context. - \return None. -*/ -void trap_c(uintptr_t *regs) -{ - uint32_t vec = 0; - uintptr_t cause = __get_MCAUSE(); - uintptr_t tval = __get_MTVAL(); - - //riscv_savefpu(regs); - - vec = cause & 0x3FF; - - if (RV_EXCEPTION_NUM > vec) { - exception_handlers[vec](cause, tval, (uintptr_t *)regs); - } else { - while (1) - ; - } - - //riscv_restorefpu(regs); -} - -/** - \brief set all ISRs in g_irqvector to the default one. - \return None. -*/ -void System_Interrupt_Init(void) -{ - for (uintptr_t irq = 0; irq < IRQn_LAST; irq++) { - g_irqvector[irq] = (pFunc)Interrupt_Default_Handler; - } -} - -/** - \brief install ISR to g_irqvector. - \param[in] irq Number of IRQ. - \param[in] interruptFun the ISR for irq. - \return None. -*/ -void Interrupt_Handler_Register(IRQn_Type irq, pFunc interruptFun) -{ - if (irq < IRQn_LAST) { - g_irqvector[irq] = interruptFun; - } -} - -/** - \brief enable irq. - \param[in] irq_num Number of IRQ. - \return None. -*/ -void CPU_Interrupt_Enable(uint32_t irq_num) -{ - if (irq_num < IRQn_LAST) - csi_vic_enable_irq(irq_num); -} - -/** - \brief disable irq. - \param[in] irq_num Number of IRQ. - \return None. -*/ -void CPU_Interrupt_Disable(uint32_t irq_num) -{ - if (irq_num < IRQn_LAST) - csi_vic_disable_irq(irq_num); -} - -/** - \brief Clear Pending Interrupt - \details Clear the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -void CPU_Interrupt_Pending_Clear(uint32_t irq_num) -{ - if (irq_num < IRQn_LAST) - csi_vic_clear_pending_irq(irq_num); -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/source/system_bl808.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/source/system_bl808.h deleted file mode 100644 index 2ed33137a7..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/source/system_bl808.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef __SYSTEM_BL808_H__ -#define __SYSTEM_BL808_H__ - -#define RV_EXCEPTION_NUM (16) -typedef uintptr_t (*exception_handler)(uintptr_t cause, uintptr_t val, uintptr_t *regs); -typedef void (*pFunc)(void); - -extern void System_Interrupt_Init(void); -extern void CPU_Interrupt_Enable(uint32_t irq_num); -extern void CPU_Interrupt_Disable(uint32_t irq_num); -extern void CPU_Interrupt_Pending_Clear(uint32_t irq_num); -void Interrupt_Handler_Register(IRQn_Type irq, pFunc interruptFun); -extern void System_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); - -exception_handler exception_handler_install(uintptr_t vec, exception_handler handler); - -int32_t drv_get_cpu_id(void); -int32_t drv_get_cpu_freq(int32_t idx); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_adc.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_adc.h deleted file mode 100644 index db4f23c74b..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_adc.h +++ /dev/null @@ -1,550 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_adc.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_ADC_H__ -#define __BL808_ADC_H__ - -#include "aon_reg.h" -#include "gpip_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup ADC - * @{ - */ - -/** @defgroup ADC_Public_Types - * @{ - */ - -/** - * @brief ADC channel type definition - */ -typedef enum { - ADC_CHAN0, /*!< ADC channel 0 */ - ADC_CHAN1, /*!< ADC channel 1 */ - ADC_CHAN2, /*!< ADC channel 2 */ - ADC_CHAN3, /*!< ADC channel 3 */ - ADC_CHAN4, /*!< ADC channel 4 */ - ADC_CHAN5, /*!< ADC channel 5 */ - ADC_CHAN6, /*!< ADC channel 6 */ - ADC_CHAN7, /*!< ADC channel 7 */ - ADC_CHAN8, /*!< ADC channel 8 */ - ADC_CHAN9, /*!< ADC channel 9 */ - ADC_CHAN10, /*!< ADC channel 10 */ - ADC_CHAN11, /*!< ADC channel 11 */ - ADC_CHAN_DAC_OUTA, /*!< DACA, ADC channel 12 */ - ADC_CHAN_DAC_OUTB, /*!< DACB, ADC channel 13 */ - ADC_CHAN_TSEN_P, /*!< TSenp, ADC channel 14 */ - ADC_CHAN_TSEN_N, /*!< TSenn, ADC channel 15 */ - ADC_CHAN_VREF, /*!< Vref, ADC channel 16 */ - ADC_CHAN_DCTEST, /*!< DCTest, ADC channel 17 */ - ADC_CHAN_VABT_HALF, /*!< VBAT/2, ADC channel 18 */ - ADC_CHAN_SENP3, /*!< SenVP3, ADC channel 19 */ - ADC_CHAN_SENP2, /*!< SenVP2, ADC channel 20 */ - ADC_CHAN_SENP1, /*!< SenVP1, ADC channel 21 */ - ADC_CHAN_SENP0, /*!< SenVP0, ADC channel 22 */ - ADC_CHAN_GND, /*!< GND, ADC channel 23 */ -} ADC_Chan_Type; - -/** - * @brief ADC V18 selection type definition - */ -typedef enum { - ADC_V18_SEL_1P62V, /*!< V18 select 1.62V */ - ADC_V18_SEL_1P72V, /*!< V18 select 1.72V */ - ADC_V18_SEL_1P82V, /*!< V18 select 1.82V */ - ADC_V18_SEL_1P92V, /*!< V18 select 1.92V */ -} ADC_V18_SEL_Type; - -/** - * @brief ADC V11 selection type definition - */ -typedef enum { - ADC_V11_SEL_1P0V, /*!< V11 select 1.0V */ - ADC_V11_SEL_1P1V, /*!< V11 select 1.1V */ - ADC_V11_SEL_1P18V, /*!< V11 select 1.18V */ - ADC_V11_SEL_1P26V, /*!< V11 select 1.26V */ -} ADC_V11_SEL_Type; - -/** - * @brief ADC clock type definition - */ -typedef enum { - ADC_CLK_DIV_1, /*!< ADC clock:on 32M clock is 32M */ - ADC_CLK_DIV_4, /*!< ADC clock:on 32M clock is 8M */ - ADC_CLK_DIV_8, /*!< ADC clock:on 32M clock is 4M */ - ADC_CLK_DIV_12, /*!< ADC clock:on 32M clock is 2.666M */ - ADC_CLK_DIV_16, /*!< ADC clock:on 32M clock is 2M */ - ADC_CLK_DIV_20, /*!< ADC clock:on 32M clock is 1.6M */ - ADC_CLK_DIV_24, /*!< ADC clock:on 32M clock is 1.333M */ - ADC_CLK_DIV_32, /*!< ADC clock:on 32M clock is 1M */ -} ADC_CLK_Type; - -/** - * @brief ADC conversion speed type definition - */ -typedef enum { - ADC_DELAY_SEL_0, /*!< Select delay 0 */ - ADC_DELAY_SEL_1, /*!< Select delay 1 */ - ADC_DELAY_SEL_2, /*!< Select delay 2 */ - ADC_DELAY_SEL_3, /*!< Select delay 3 */ - ADC_DELAY_SEL_4, /*!< Select delay 4, not recommend */ - ADC_DELAY_SEL_5, /*!< Select delay 5, not recommend */ - ADC_DELAY_SEL_6, /*!< Select delay 6, not recommend */ - ADC_DELAY_SEL_7, /*!< Select delay 7, not recommend */ -} ADC_DELAY_SEL_Type; - -/** - * @brief ADC PGA gain type definition - */ -typedef enum { - ADC_PGA_GAIN_NONE, /*!< No PGA gain */ - ADC_PGA_GAIN_1, /*!< PGA gain 1 */ - ADC_PGA_GAIN_2, /*!< PGA gain 2 */ - ADC_PGA_GAIN_4, /*!< PGA gain 4 */ - ADC_PGA_GAIN_8, /*!< PGA gain 8 */ - ADC_PGA_GAIN_16, /*!< PGA gain 16 */ - ADC_PGA_GAIN_32, /*!< PGA gain 32 */ -} ADC_PGA_GAIN_Type; - -/** - * @brief ADC analog portion low power mode selection type definition - */ -typedef enum { - ADC_BIAS_SEL_MAIN_BANDGAP, /*!< ADC current from main bandgap */ - ADC_BIAS_SEL_AON_BANDGAP, /*!< ADC current from aon bandgap for HBN mode */ -} ADC_BIAS_SEL_Type; - -/** - * @brief ADC chop mode type definition - */ -typedef enum { - ADC_CHOP_MOD_ALL_OFF, /*!< all off */ - ADC_CHOP_MOD_AZ_ON, /*!< Vref AZ on */ - ADC_CHOP_MOD_AZ_PGA_ON, /*!< Vref AZ and PGA chop on */ - ADC_CHOP_MOD_AZ_PGA_RPC_ON, /*!< Vref AZ and PGA chop+RPC on */ -} ADC_CHOP_MOD_Type; - -/** - * @brief ADC audio PGA output common mode control type definition - */ -typedef enum { - ADC_PGA_VCM_1V, /*!< ADC VCM=1V */ - ADC_PGA_VCM_1P2V, /*!< ADC VCM=1.2V */ - ADC_PGA_VCM_1P4V, /*!< ADC VCM=1.4V */ - ADC_PGA_VCM_1P6V, /*!< ADC VCM=1.6V */ -} ADC_PGA_VCM_Type; - -/** - * @brief ADC tsen diode mode type definition - */ -typedef enum { - ADC_TSEN_MOD_INTERNAL_DIODE, /*!< Internal diode mode */ - ADC_TSEN_MOD_EXTERNAL_DIODE, /*!< External diode mode */ -} ADC_TSEN_MOD_Type; - -/** - * @brief ADC voltage reference type definition - */ -typedef enum { - ADC_VREF_3P2V, /*!< ADC select 3.2V as reference voltage */ - ADC_VREF_2P0V, /*!< ADC select 2V as reference voltage */ -} ADC_VREF_Type; - -/** - * @brief ADC signal input type definition - */ -typedef enum { - ADC_INPUT_SINGLE_END, /*!< ADC signal is single end */ - ADC_INPUT_DIFF, /*!< ADC signal is differential */ -} ADC_SIG_INPUT_Type; - -/** - * @brief ADC data width type definition - */ -typedef enum { - ADC_DATA_WIDTH_12, /*!< ADC 12 bits */ - ADC_DATA_WIDTH_14_WITH_16_AVERAGE, /*!< ADC 14 bits,and the value is average of 16 converts */ - ADC_DATA_WIDTH_14_WITH_64_AVERAGE, /*!< ADC 14 bits,and the value is average of 64 converts */ - ADC_DATA_WIDTH_16_WITH_128_AVERAGE, /*!< ADC 16 bits,and the value is average of 128 converts */ - ADC_DATA_WIDTH_16_WITH_256_AVERAGE, /*!< ADC 16 bits,and the value is average of 256 converts */ -} ADC_Data_Width_Type; - -/** - * @brief ADC micboost 32db type definition - */ -typedef enum { - ADC_MICBOOST_DB_16DB, /*!< MIC boost 16db */ - ADC_MICBOOST_DB_32DB, /*!< MIC boost 32db */ -} ADC_MICBOOST_DB_Type; - -/** - * @brief ADC pga2 gain type definition - */ -typedef enum { - ADC_PGA2_GAIN_0DB, /*!< MIC pga2 gain 0db */ - ADC_PGA2_GAIN_6DB, /*!< MIC pga2 gain 6db */ - ADC_PGA2_GAIN_N6DB, /*!< MIC pga2 gain -6db */ - ADC_PGA2_GAIN_12DB, /*!< MIC pga2 gain 12db */ -} ADC_PGA2_GAIN_Type; - -/** - * @brief ADC mic mode type definition - */ -typedef enum { - ADC_MIC_MODE_SINGLE, /*!< MIC single mode */ - ADC_MIC_MODE_DIFF, /*!< MIC diff mode */ -} ADC_MIC_MODE_Type; - -/** - * @brief ADC mic type definition - */ -typedef struct -{ - ADC_MICBOOST_DB_Type micboostDb; /*!< MIC boost db */ - ADC_PGA2_GAIN_Type micPga2Gain; /*!< MIC pga2 gain */ - ADC_MIC_MODE_Type mic1Mode; /*!< MIC1 single or diff */ - ADC_MIC_MODE_Type mic2Mode; /*!< MIC2 single or diff */ - BL_Fun_Type dwaEn; /*!< Improve dynamic performance */ - BL_Fun_Type micboostBypassEn; /*!< MIC boost amp bypass enable or disable */ - BL_Fun_Type micPgaEn; /*!< MIC pga enable or disable */ - BL_Fun_Type micBiasEn; /*!< MIC bias enable or disable */ -} ADC_MIC_Type; - -/** - * @brief ADC configuration type definition - */ -typedef struct -{ - ADC_V18_SEL_Type v18Sel; /*!< ADC 1.8V select */ - ADC_V11_SEL_Type v11Sel; /*!< ADC 1.1V select */ - ADC_CLK_Type clkDiv; /*!< Clock divider */ - ADC_PGA_GAIN_Type gain1; /*!< PGA gain 1 */ - ADC_PGA_GAIN_Type gain2; /*!< PGA gain 2 */ - ADC_CHOP_MOD_Type chopMode; /*!< ADC chop mode select */ - ADC_BIAS_SEL_Type biasSel; /*!< ADC current form main bandgap or aon bandgap */ - ADC_PGA_VCM_Type vcm; /*!< ADC VCM value */ - ADC_VREF_Type vref; /*!< ADC voltage reference */ - ADC_SIG_INPUT_Type inputMode; /*!< ADC input signal type */ - ADC_Data_Width_Type resWidth; /*!< ADC resolution and oversample rate */ - BL_Fun_Type offsetCalibEn; /*!< Offset calibration enable */ - int16_t offsetCalibVal; /*!< Offset calibration value */ -} ADC_CFG_Type; - -/** - * @brief ADC configuration type definition - */ -typedef struct -{ - int8_t posChan; /*!< Positive channel */ - int8_t negChan; /*!< Negative channel */ - uint16_t value; /*!< ADC value */ - float volt; /*!< ADC voltage result */ -} ADC_Result_Type; - -/** - * @brief ADC FIFO threshold type definition - */ -typedef enum { - ADC_FIFO_THRESHOLD_1, /*!< ADC FIFO threshold is 1 */ - ADC_FIFO_THRESHOLD_4, /*!< ADC FIFO threshold is 4 */ - ADC_FIFO_THRESHOLD_8, /*!< ADC FIFO threshold is 8 */ - ADC_FIFO_THRESHOLD_16, /*!< ADC FIFO threshold is 16 */ -} ADC_FIFO_Threshold_Type; - -/** - * @brief ADC interrupt type definition - */ -typedef enum { - ADC_INT_POS_SATURATION, /*!< ADC positive channel saturation */ - ADC_INT_NEG_SATURATION, /*!< ADC negative channel saturation */ - ADC_INT_FIFO_UNDERRUN, /*!< ADC FIFO underrun interrupt */ - ADC_INT_FIFO_OVERRUN, /*!< ADC FIFO overrun interrupt */ - ADC_INT_ADC_READY, /*!< ADC data ready interrupt */ - ADC_INT_ALL, /*!< ADC all the interrupt */ -} ADC_INT_Type; - -/** - * @brief ADC FIFO configuration structure type definition - */ -typedef struct -{ - ADC_FIFO_Threshold_Type fifoThreshold; /*!< ADC FIFO threshold */ - BL_Fun_Type dmaEn; /*!< ADC DMA enable */ -} ADC_FIFO_Cfg_Type; - -/** - * @brief ADC REG GAIN CAL - */ -typedef struct -{ - BL_Fun_Type adcGainCoeffEnable; /*!< ADC_Gain_Coeff enable */ - uint16_t adcgainCoeffVal; /*!< ADC_Gain_Coeff value */ - float coe; /*!< ADC_Gain_Coeff result */ -} ADC_Gain_Coeff_Type; - -/*@} end of group ADC_Public_Types */ - -/** @defgroup ADC_Public_Constants - * @{ - */ - -/** @defgroup ADC_CHAN_TYPE - * @{ - */ -#define IS_ADC_CHAN_TYPE(type) (((type) == ADC_CHAN0) || \ - ((type) == ADC_CHAN1) || \ - ((type) == ADC_CHAN2) || \ - ((type) == ADC_CHAN3) || \ - ((type) == ADC_CHAN4) || \ - ((type) == ADC_CHAN5) || \ - ((type) == ADC_CHAN6) || \ - ((type) == ADC_CHAN7) || \ - ((type) == ADC_CHAN8) || \ - ((type) == ADC_CHAN9) || \ - ((type) == ADC_CHAN10) || \ - ((type) == ADC_CHAN11) || \ - ((type) == ADC_CHAN_DAC_OUTA) || \ - ((type) == ADC_CHAN_DAC_OUTB) || \ - ((type) == ADC_CHAN_TSEN_P) || \ - ((type) == ADC_CHAN_TSEN_N) || \ - ((type) == ADC_CHAN_VREF) || \ - ((type) == ADC_CHAN_DCTEST) || \ - ((type) == ADC_CHAN_VABT_HALF) || \ - ((type) == ADC_CHAN_SENP3) || \ - ((type) == ADC_CHAN_SENP2) || \ - ((type) == ADC_CHAN_SENP1) || \ - ((type) == ADC_CHAN_SENP0) || \ - ((type) == ADC_CHAN_GND)) - -/** @defgroup ADC_V18_SEL_TYPE - * @{ - */ -#define IS_ADC_V18_SEL_TYPE(type) (((type) == ADC_V18_SEL_1P62V) || \ - ((type) == ADC_V18_SEL_1P72V) || \ - ((type) == ADC_V18_SEL_1P82V) || \ - ((type) == ADC_V18_SEL_1P92V)) - -/** @defgroup ADC_V11_SEL_TYPE - * @{ - */ -#define IS_ADC_V11_SEL_TYPE(type) (((type) == ADC_V11_SEL_1P0V) || \ - ((type) == ADC_V11_SEL_1P1V) || \ - ((type) == ADC_V11_SEL_1P18V) || \ - ((type) == ADC_V11_SEL_1P26V)) - -/** @defgroup ADC_CLK_TYPE - * @{ - */ -#define IS_ADC_CLK_TYPE(type) (((type) == ADC_CLK_DIV_1) || \ - ((type) == ADC_CLK_DIV_4) || \ - ((type) == ADC_CLK_DIV_8) || \ - ((type) == ADC_CLK_DIV_12) || \ - ((type) == ADC_CLK_DIV_16) || \ - ((type) == ADC_CLK_DIV_20) || \ - ((type) == ADC_CLK_DIV_24) || \ - ((type) == ADC_CLK_DIV_32)) - -/** @defgroup ADC_DELAY_SEL_TYPE - * @{ - */ -#define IS_ADC_DELAY_SEL_TYPE(type) (((type) == ADC_DELAY_SEL_0) || \ - ((type) == ADC_DELAY_SEL_1) || \ - ((type) == ADC_DELAY_SEL_2) || \ - ((type) == ADC_DELAY_SEL_3) || \ - ((type) == ADC_DELAY_SEL_4) || \ - ((type) == ADC_DELAY_SEL_5) || \ - ((type) == ADC_DELAY_SEL_6) || \ - ((type) == ADC_DELAY_SEL_7)) - -/** @defgroup ADC_PGA_GAIN_TYPE - * @{ - */ -#define IS_ADC_PGA_GAIN_TYPE(type) (((type) == ADC_PGA_GAIN_NONE) || \ - ((type) == ADC_PGA_GAIN_1) || \ - ((type) == ADC_PGA_GAIN_2) || \ - ((type) == ADC_PGA_GAIN_4) || \ - ((type) == ADC_PGA_GAIN_8) || \ - ((type) == ADC_PGA_GAIN_16) || \ - ((type) == ADC_PGA_GAIN_32)) - -/** @defgroup ADC_BIAS_SEL_TYPE - * @{ - */ -#define IS_ADC_BIAS_SEL_TYPE(type) (((type) == ADC_BIAS_SEL_MAIN_BANDGAP) || \ - ((type) == ADC_BIAS_SEL_AON_BANDGAP)) - -/** @defgroup ADC_CHOP_MOD_TYPE - * @{ - */ -#define IS_ADC_CHOP_MOD_TYPE(type) (((type) == ADC_CHOP_MOD_ALL_OFF) || \ - ((type) == ADC_CHOP_MOD_AZ_ON) || \ - ((type) == ADC_CHOP_MOD_AZ_PGA_ON) || \ - ((type) == ADC_CHOP_MOD_AZ_PGA_RPC_ON)) - -/** @defgroup ADC_PGA_VCM_TYPE - * @{ - */ -#define IS_ADC_PGA_VCM_TYPE(type) (((type) == ADC_PGA_VCM_1V) || \ - ((type) == ADC_PGA_VCM_1P2V) || \ - ((type) == ADC_PGA_VCM_1P4V) || \ - ((type) == ADC_PGA_VCM_1P6V)) - -/** @defgroup ADC_TSEN_MOD_TYPE - * @{ - */ -#define IS_ADC_TSEN_MOD_TYPE(type) (((type) == ADC_TSEN_MOD_INTERNAL_DIODE) || \ - ((type) == ADC_TSEN_MOD_EXTERNAL_DIODE)) - -/** @defgroup ADC_VREF_TYPE - * @{ - */ -#define IS_ADC_VREF_TYPE(type) (((type) == ADC_VREF_3P3V) || \ - ((type) == ADC_VREF_2V)) - -/** @defgroup ADC_SIG_INPUT_TYPE - * @{ - */ -#define IS_ADC_SIG_INPUT_TYPE(type) (((type) == ADC_INPUT_SINGLE_END) || \ - ((type) == ADC_INPUT_DIFF)) - -/** @defgroup ADC_DATA_WIDTH_TYPE - * @{ - */ -#define IS_ADC_DATA_WIDTH_TYPE(type) (((type) == ADC_DATA_WIDTH_12) || \ - ((type) == ADC_DATA_WIDTH_14_WITH_16_AVERAGE) || \ - ((type) == ADC_DATA_WIDTH_14_WITH_64_AVERAGE) || \ - ((type) == ADC_DATA_WIDTH_16_WITH_128_AVERAGE) || \ - ((type) == ADC_DATA_WIDTH_16_WITH_256_AVERAGE)) - -/** @defgroup ADC_MICBOOST_DB_TYPE - * @{ - */ -#define IS_ADC_MICBOOST_DB_TYPE(type) (((type) == ADC_MICBOOST_DB_16DB) || \ - ((type) == ADC_MICBOOST_DB_32DB)) - -/** @defgroup ADC_PGA2_GAIN_TYPE - * @{ - */ -#define IS_ADC_PGA2_GAIN_TYPE(type) (((type) == ADC_PGA2_GAIN_0DB) || \ - ((type) == ADC_PGA2_GAIN_6DB) || \ - ((type) == ADC_PGA2_GAIN_N6DB) || \ - ((type) == ADC_PGA2_GAIN_12DB)) - -/** @defgroup ADC_MIC_MODE_TYPE - * @{ - */ -#define IS_ADC_MIC_MODE_TYPE(type) (((type) == ADC_MIC_MODE_SINGLE) || \ - ((type) == ADC_MIC_MODE_DIFF)) - -/** @defgroup ADC_FIFO_THRESHOLD_TYPE - * @{ - */ -#define IS_ADC_FIFO_THRESHOLD_TYPE(type) (((type) == ADC_FIFO_THRESHOLD_1) || \ - ((type) == ADC_FIFO_THRESHOLD_4) || \ - ((type) == ADC_FIFO_THRESHOLD_8) || \ - ((type) == ADC_FIFO_THRESHOLD_16)) - -/** @defgroup ADC_INT_TYPE - * @{ - */ -#define IS_ADC_INT_TYPE(type) (((type) == ADC_INT_POS_SATURATION) || \ - ((type) == ADC_INT_NEG_SATURATION) || \ - ((type) == ADC_INT_FIFO_UNDERRUN) || \ - ((type) == ADC_INT_FIFO_OVERRUN) || \ - ((type) == ADC_INT_ADC_READY) || \ - ((type) == ADC_INT_ALL)) - -/*@} end of group ADC_Public_Constants */ - -/** @defgroup ADC_Public_Macros - * @{ - */ - -/*@} end of group ADC_Public_Macros */ - -/** @defgroup ADC_Public_Functions - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -void GPADC_DMA_IRQHandler(void); -#endif -void ADC_Vbat_Enable(void); -void ADC_Vbat_Disable(void); -void ADC_Reset(void); -void ADC_Enable(void); -void ADC_Disable(void); -void ADC_Init(ADC_CFG_Type *cfg); -void ADC_Channel_Config(ADC_Chan_Type posCh, ADC_Chan_Type negCh, BL_Fun_Type contEn); -void ADC_Scan_Channel_Config(ADC_Chan_Type posChList[], ADC_Chan_Type negChList[], uint8_t scanLength, BL_Fun_Type contEn); -void ADC_Start(void); -void ADC_Stop(void); -void ADC_FIFO_Cfg(ADC_FIFO_Cfg_Type *fifoCfg); -uint8_t ADC_Get_FIFO_Count(void); -BL_Sts_Type ADC_FIFO_Is_Empty(void); -BL_Sts_Type ADC_FIFO_Is_Full(void); -void ADC_FIFO_Clear(void); -uint32_t ADC_Read_FIFO(void); -void ADC_Parse_Result(uint32_t *orgVal, uint32_t len, ADC_Result_Type *result); -void ADC_IntClr(ADC_INT_Type intType); -BL_Mask_Type ADC_IntGetMask(ADC_INT_Type intType); -BL_Sts_Type ADC_GetIntStatus(ADC_INT_Type intType); -void ADC_Int_Callback_Install(ADC_INT_Type intType, intCallback_Type *cbFun); -void ADC_IntMask(ADC_INT_Type intType, BL_Mask_Type intMask); -void ADC_SET_TSVBE_LOW(void); -void ADC_SET_TSVBE_HIGH(void); -void ADC_Tsen_Init(ADC_TSEN_MOD_Type tsenMod); -void ADC_Tsen_Enable(void); -void ADC_Tsen_Disable(void); -void ADC_PGA_Config(uint8_t pga_vcmi_enable, uint8_t pga_os_cal); -BL_Err_Type ADC_Mic_Init(ADC_MIC_Type *adc_mic_config); -void ADC_MIC_Bias_Disable(void); -void ADC_MIC_Bias_Enable(void); -BL_Err_Type ADC_Trim_TSEN(uint16_t *tsen_offset); -BL_Err_Type ADC_Gain_Trim(void); -uint32_t ADC_Cal_Reg_Coeff_Value(uint32_t raw_reg); -float TSEN_Get_Temp(uint32_t tsen_offset); - -/*@} end of group ADC_Public_Functions */ - -/*@} end of group ADC */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_ADC_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_audio.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_audio.h deleted file mode 100644 index 63b81cd65e..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_audio.h +++ /dev/null @@ -1,971 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_audio.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_AUDIO_H__ -#define __BL808_AUDIO_H__ - -#include "audio_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup AUDIO - * @{ - */ - -/** @defgroup AUDIO_Public_Types - * @{ - */ - -/** - * @brief Audio ADC ID - */ -typedef enum { - AUDIO_ADC_0, /*!< Audio ADC 0 */ - AUDIO_ADC_1, /*!< Audio ADC 1 */ - AUDIO_ADC_2, /*!< Audio ADC 2 */ -} Audio_ADC_ID_Type; - -/** - * @brief Audio DAC ID - */ -typedef enum { - AUDIO_DAC_0, /*!< Audio DAC 0 */ - AUDIO_DAC_1, /*!< Audio DAC 1 */ -} Audio_DAC_ID_Type; - -/** - * @brief Audio AEC ID - */ -typedef enum { - AUDIO_AEC_0, /*!< Audio AEC 0 */ - AUDIO_AEC_1, /*!< Audio AEC 1 */ -} Audio_AEC_ID_Type; - -/** - * @brief Audio PDM ID - */ -typedef enum { - AUDIO_PDM_0, /*!< select PDM Channel 0 */ - AUDIO_PDM_1, /*!< select PDM Channel 1 */ - AUDIO_PDM_2, /*!< select PDM Channel 2 */ -} Audio_PDM_ID_Type; - -/** - * @brief Audio MUTE - */ -typedef enum { - AUDIO_UNMUTE, /*!< unmute */ - AUDIO_MUTE, /*!< mute */ -} Audio_Mute_Type; - -/** - * @brief Audio ADC Clock - */ -typedef enum { - AUDIO_ADC_8_KHZ, /*!< Audio ADC Clock set as 8KHZ */ - AUDIO_ADC_16_KHZ, /*!< Audio ADC Clock set as 16KHZ */ - AUDIO_ADC_24_KHZ, /*!< Audio ADC Clock set as 24KHZ */ - AUDIO_ADC_32_KHZ, /*!< Audio ADC Clock set as 32KHZ */ - AUDIO_ADC_48_KHZ, /*!< Audio ADC Clock set as 48KHZ */ - AUDIO_ADC_96_KHZ, /*!< Audio ADC Clock set as 96KHZ */ -} Audio_ADC_Clock_Type; - -/** - * @brief Audio DAC Clock - */ -typedef enum { - AUDIO_DAC_8_KHZ, /*!< Audio DAC Clock set as 8KHZ */ - AUDIO_DAC_16_KHZ, /*!< Audio DAC Clock set as 16KHZ */ - AUDIO_DAC_24_KHZ, /*!< Audio DAC Clock set as 24KHZ */ - AUDIO_DAC_32_KHZ, /*!< Audio DAC Clock set as 32KHZ */ - AUDIO_DAC_48_KHZ, /*!< Audio DAC Clock set as 48KHZ */ - AUDIO_DAC_96_KHZ, /*!< Audio DAC Clock set as 96KHZ */ - AUDIO_DAC_192_KHZ, /*!< Audio DAC Clock set as 192KHZ */ -} Audio_DAC_Clock_Type; - -/** - * @brief Audio ADC Source Interface - */ -typedef enum { - AUDIO_ADC_ANALOG, /*!< set AUDIO ADC as ANALOG mode connect AMIC */ - AUDIO_ADC_PDM, /*!< set AUDIO ADC as PDM mode connect to DMIC */ -} Audio_ADC_Source_Type; - -/** - * @brief Audio LSFR Type - */ -typedef enum { - AUDIO_LFSR32, /*!< Audio LFSR32 */ - AUDIO_LFSR24, /*!< Audio LFSR24 */ - AUDIO_LFSR16, /*!< Audio LFSR16 */ - AUDIO_LFSR12, /*!< Audio LFSR12 */ -} Audio_LFSR_Type; - -/** - * @brief Audio Mixer Mode - */ -typedef enum { - AUDIO_SECOND_DEBUG_MODE = 0x1, /*!< Audio second mode debug mode */ - AUDIO_SIDETONE_LOOPBACK = 0x2, /*!< Audio sidetone mode mix will mixer dac with adc data */ -} Audio_Mixer_Mode; - -/** - * @brief Audio Mixer Volume Type - */ -typedef enum { - AUDIO_MIXER_VOLUME_0_DB, /*!< Audio Mix Volume 0DB */ - AUDIO_MIXER_VOLUME_6_DB, /*!< Audio Mix Volume 6DB */ - AUDIO_MIXER_VOLUME_12_DB, /*!< Audio Mix Volume 12DB */ - AUDIO_MIXER_VOLUME_18_DB, /*!< Audio Mix Volume 18DB */ - AUDIO_MIXER_VOLUME_36_DB, /*!< Audio Mix Volume 36DB */ - AUDIO_MIXER_VOLUME_54_DB, /*!< Audio Mix Volume 54DB */ - AUDIO_MIXER_VOLUME_72_DB, /*!< Audio Mix Volume 72DB */ - AUDIO_MIXER_VOLUME_MUTE, /*!< Audio Mix Volume Mute */ -} Audio_Mixer_Volume_Type; - -/** - * @brief Audio Mixer ID - */ -typedef enum { - AUDIO_MIXER_ID_0, /*!< Audio Mix ID 0 */ - AUDIO_MIXER_ID_1, /*!< Audio Mix ID 1 */ -} Audio_Mixer_ID_Type; - -/** - * @brief Audio dac order - */ -typedef enum { - AUDIO_DAC_2_ORDER, /*!< Audio ORDER 2 */ - AUDIO_DAC_3_ORDER, /*!< Audio ORDER 3 */ -} Audio_DAC_Order_Type; - -/** - * @brief Audio aec attenuation mode - */ -typedef enum { - AUDIO_AEC_NO_DROP, /*!< DROP 0 LSB */ - AUDIO_AEC_DROP_1LSB, /*!< DROP 1 LSB */ - AUDIO_AEC_DROP_2LSB, /*!< DROP 2 LSB */ - AUDIO_AEC_DROP_3LSB, /*!< DROP 3 LSB */ - AUDIO_AEC_DROP_6LSB, /*!< DROP 6 LSB */ - AUDIO_AEC_DROP_9LSB, /*!< DROP 9 LSB */ - AUDIO_AEC_DROP_12LSB, /*!< DROP 12 LSB */ -} Audio_AEC_Atten_Mode; - -/** - * @brief Audio PDM Source Select - */ -typedef enum { - AUDIO_PDM_0_L, /*!< select PDM0 Left Channel */ - AUDIO_PDM_0_R, /*!< select PDM0 Right Channel */ - AUDIO_PDM_1_L, /*!< select PDM1 Left Channel */ - AUDIO_PDM_1_R, /*!< select PDM1 Right Channel */ - AUDIO_PDM_2_L, /*!< select PDM2 Left Channel */ - AUDIO_PDM_2_R, /*!< select PDM2 Right Channel */ -} Audio_PDM_Source_Type; - -/** - * @brief Audio Resolution - */ -typedef enum { - AUDIO_RES_16_BITS, /*!< select ADC Resolution as 16 bit */ - AUDIO_RES_20_BITS, /*!< select ADC Resolution as 20 bit */ -} Audio_Resolution_Type; - -/** - * @brief Audio Resolution - */ -typedef enum { - AUDIO_FIFO_AILGN_MSB_AT_BIT31, /*!< Mode 0: Valid data's MSB is at [31] of FIFO register */ - AUDIO_FIFO_AILGN_MSB_AT_BIT23, /*!< Mode 1: Valid data's MSB is at [23] of FIFO register */ - AUDIO_FIFO_AILGN_MSB_AT_BIT19, /*!< Mode 2: Valid data's MSB is at [19] of FIFO register */ - AUDIO_FIFO_AILGN_MSB_AT_BIT15, /*!< Mode 3: Valid data's MSB is at [15] of FIFO register */ -} Audio_FIFO_Ailgn_Mode; - -/** - * @brief Audio Resolution - */ -typedef enum { - AUDIO_DRQ_EQUEL_TO_IRQ, /*!< DMA request threhold is equeal to Interrupt threhold */ - AUDIO_DRQ_THR_AS_4_TX_8_RX, /*!< DMA request threhold is 4 when config TX FIFO DRQ , 8 when config RX FIFO */ - AUDIO_DRQ_THR_AS_8_TX_16_RX, /*!< DMA request threhold is 8 when config TX FIFO DRQ , 16 when config RX FIFO */ - AUDIO_DRQ_THR_AS_16_TX_32_RX, /*!< DMA request threhold is 16 when config TX FIFO DRQ , 32 when config RX FIFO */ -} Audio_FIFO_DQR_Threshold_Mode; - -/** - * @brief Audio initerrupt type - */ -typedef enum { - AUDIO_INT_RX_FIFO_THR, /*!< Audio RX FIFO counter upper than threhold interrupt */ - AUDIO_INT_RX_FIFO_OVERRUN, /*!< Audio RX FIFO overrun */ - AUDIO_INT_RX_FIFO_UNDERRUN, /*!< Audio RX FIFO underrun */ - AUDIO_INT_TX_FIFO_THR, /*!< Audio TX FIFO THL */ - AUDIO_INT_TX_FIFO_OVERRUN, /*!< Audio TX FIFO overrun */ - AUDIO_INT_TX_FIFO_UNDERRUN, /*!< Audio TX FIFO underrun */ - AUDIO_INT_ADC0_SET_VOLUME_DONE, /*!< Audio set ADC0 volume done */ - AUDIO_INT_ADC1_SET_VOLUME_DONE, /*!< Audio set ADC1 volume done */ - AUDIO_INT_ADC2_SET_VOLUME_DONE, /*!< Audio set ADC2 volume done */ - AUDIO_INT_DAC0_SET_VOLUME_DONE, /*!< Audio set DAC0 volume done */ - AUDIO_INT_DAC1_SET_VOLUME_DONE, /*!< Audio set DAC1 volume done */ - AUDIO_INT_VAD, /*!< Audio VAD */ - AUDIO_INT_NUM_ALL, /*!< Audio int all */ -} Audio_INT_Type; - -/** - * @brief Audio peq qtfm - */ -typedef enum { - AUDIO_PEQ_QFMT_20_17, /*!< Audio QFMT 20.17 */ - AUDIO_PEQ_QFMT_20_16, /*!< Audio QFMT 20.16 */ -} Audio_PEQ_QTFM_Type; - -/** - * @brief Audio mute mode - */ -typedef enum { - AUIDO_MUTE_DIRECTLY, /*!< mute directly */ - AUDIO_MUTE_WITH_RAMP_DOWN, /*!< mute with rampdown */ -} Audio_Mute_Mode; - -/** - * @brief Audio ramp rate - */ -typedef enum { - AUIDO_RAMP_RATE_2_FS, /*!< ramp rate 2 fs */ - AUIDO_RAMP_RATE_4_FS, /*!< ramp rate 4 fs */ - AUIDO_RAMP_RATE_8_FS, /*!< ramp rate 8 fs */ - AUIDO_RAMP_RATE_16_FS, /*!< ramp rate 16 fs */ - AUIDO_RAMP_RATE_32_FS, /*!< ramp rate 32 fs */ - AUIDO_RAMP_RATE_64_FS, /*!< ramp rate 64 fs */ - AUIDO_RAMP_RATE_128_FS, /*!< ramp rate 128 fs */ - AUIDO_RAMP_RATE_256_FS, /*!< ramp rate 256 fs */ - AUIDO_RAMP_RATE_512_FS, /*!< ramp rate 512 fs */ - AUIDO_RAMP_RATE_1024_FS, /*!< ramp rate 1024 fs */ - AUIDO_RAMP_RATE_2048_FS, /*!< ramp rate 2048 fs */ -} Audio_Ramp_Rate_Type; - -/** - * @brief Audio zero cross rate - */ -typedef enum { - AUIDO_ZERO_CROSS_RATE_2_FS, /*!< ramp rate 2 fs */ - AUIDO_ZERO_CROSS_RATE_4_FS, /*!< ramp rate 4 fs */ - AUIDO_ZERO_CROSS_RATE_8_FS, /*!< ramp rate 8 fs */ - AUIDO_ZERO_CROSS_RATE_16_FS, /*!< ramp rate 16 fs */ - AUIDO_ZERO_CROSS_RATE_32_FS, /*!< ramp rate 32 fs */ - AUIDO_ZERO_CROSS_RATE_64_FS, /*!< ramp rate 64 fs */ - AUIDO_ZERO_CROSS_RATE_128_FS, /*!< ramp rate 128 fs */ - AUIDO_ZERO_CROSS_RATE_256_FS, /*!< ramp rate 256 fs */ - AUIDO_ZERO_CROSS_RATE_512_FS, /*!< ramp rate 512 fs */ - AUIDO_ZERO_CROSS_RATE_1024_FS, /*!< ramp rate 1024 fs */ - AUIDO_ZERO_CROSS_RATE_2048_FS, /*!< ramp rate 2048 fs */ -} Audio_Zero_Cross_Rate_Type; - -/** - * @brief Audio volume ctr mode - */ -typedef enum { - AUIDO_VOLUME_UPDATE_FORCE, /*!< volume update force */ - AUIDO_VOLUME_UPDATE_AT_ZERO_CROSSING, /*!< volume update at zero crossing */ - AUIDO_VOLUME_UPDATE_AT_RAMP, /*!< volume update at zero crossing */ -} Audio_Volume_Ctr_Mode; - -/** - * @brief Audio_AGC_Detect_Mode - */ -typedef enum { - AUIDO_AGC_DETECT_BY_PEAK, /*!< detect by peak */ - AUIDO_AGC_DETECT_BY_AVERAGE, /*!< detect by average */ -} Audio_AGC_Detect_Mode; - -/** - * @brief Audio_AGC_Src_Type - */ -typedef enum { - AUIDO_AGC_CH0_ABSOLUTE_VALUE, /*!< Audio AGC CH0 */ - AUIDO_AGC_CH1_ABSOLUTE_VALUE, /*!< Audio AGC CH1 */ - AUIDO_AGC_CH2_ABSOLUTE_VALUE, /*!< Audio AGC CH2 */ - AUIDO_AGC_MAXIMUM_VALUE_OF_CH012, /*!< Audio AGC Max value of ch012 */ -} Audio_AGC_Src_Type; - -/** - * @brief Auido_DRC_Data_Type - */ -typedef enum { - AUIDO_DRC_DATA_SOURCE_CH0, /*!< Audio DRC SOURCE CH0 */ - AUIDO_DRC_DATA_SOURCE_CH1, /*!< Audio DRC SOURCE CH1 */ - AUIDO_DRC_DATA_SOURCE_AVERAGE_OF_CH0_CH1, /*!< Audio DRC SOURCE (CH0+CH1)/2 */ - AUIDO_DRC_DATA_SOURCE_MAX_OF_CH0_CH1, /*!< Audio DRC MAX(CH0,CH1) */ -} Auido_DRC_Data_Type; - -/** - * @brief Auido_VAD_Source_Type - */ -typedef enum { - AUIDO_VAD_DATA_SOURCE_ADC_CH0, /*!< Audio ADC CH0 */ - AUIDO_VAD_DATA_SOURCE_ADC_CH1, /*!< Audio ADC CH1 */ - AUIDO_VAD_DATA_SOURCE_ADC_CH2, /*!< Audio ADC CH2 */ - AUIDO_VAD_DATA_SOURCE_AEC_CH0, /*!< Audio AEC CH0 */ - AUIDO_VAD_DATA_SOURCE_AEC_CH1, /*!< Audio AEC CH1 */ - AUDIO_VAD_DATA_SOURCE_AVERAGE_ADC_CH0_ADD_CH1, /*!< Audio (ADC0+ADC1)/2 */ - AUDIO_VAD_DATA_SOURCE_AVERAGE_ADC_CH1_ADD_CH2, /*!< Audio (ADC1+ADC2)/2 */ - AUDIO_VAD_DATA_SOURCE_AVERAGE_ADC_CH2_ADD_CH0, /*!< Audio (ADC2+ADC0)/2 */ -} Auido_VAD_Source_Type; - -/** - * @brief Auido_VAD_FramingShift_Type - */ -typedef enum { - AUIDO_VAD_FRAMING_SHIFT_2P5_MS, /*!< Audio VAD FramingShift = 2.5 */ - AUIDO_VAD_FRAMING_SHIFT_5_MS, /*!< Audio VAD FramingShift = 5 */ - AUIDO_VAD_FRAMING_SHIFT_7P5_MS, /*!< Audio VAD FramingShift = 7.5 */ - AUIDO_VAD_FRAMING_SHIFT_10_MS, /*!< Audio VAD FramingShift = 10 */ - AUIDO_VAD_FRAMING_SHIFT_12P5_MS, /*!< Audio VAD FramingShift = 12.5 */ - AUIDO_VAD_FRAMING_SHIFT_15_MS, /*!< Audio VAD FramingShift = 15 */ - AUIDO_VAD_FRAMING_SHIFT_17P5_MS, /*!< Audio VAD FramingShift = 17.5 */ - AUIDO_VAD_FRAMING_SHIFT_20_MS, /*!< Audio VAD FramingShift = 20 */ -} Auido_VAD_FramingShift_Type; - -/** - * @brief Auido_VAD_FramingTime_Type - */ -typedef enum { - AUIDO_VAD_FRAMING_TIME_2, /*!< Audio VAD FramingTime K= 2 */ - AUIDO_VAD_FRAMING_TIME_3, /*!< Audio VAD FramingTime K= 3 */ - AUIDO_VAD_FRAMING_TIME_4, /*!< Audio VAD FramingTime K= 4 */ - AUIDO_VAD_FRAMING_TIME_5, /*!< Audio VAD FramingTime K= 5 */ -} Auido_VAD_FramingTime_Type; - -/** - * @brief Auido_VAD_FramingTime_Type - */ -typedef enum { - AUIDO_VAD_ORIGINAL_OUTPUT, /*!< Original VAD output(VAD00) */ - AUIDO_VAD_OUT0, /*!< Debounced VAD output(VADout0), with small NDV but large DL */ - AUIDO_VAD_OUT1, /*!< Debounced VAD output(VADout1) */ - AUIDO_VAD_OUT2, /*!< Debounced VAD output(VADout2), with small DL but large NDV */ -} Auido_VAD_IRQ_Source_Type; - -/** - * @brief Auido_VAD_NoisyBufferLen_Type - */ -typedef enum { - AUIDO_VAD_NOISY_BUF_LEN_4, /*!< noise buffer length control 4 */ - AUIDO_VAD_NOISY_BUF_LEN_8, /*!< noise buffer length control 8 */ - AUIDO_VAD_NOISY_BUF_LEN_12, /*!< noise buffer length control 12 */ - AUIDO_VAD_NOISY_BUF_LEN_16, /*!< noise buffer length control 16 */ - AUIDO_VAD_NOISY_BUF_LEN_20, /*!< noise buffer length control 20 */ - AUIDO_VAD_NOISY_BUF_LEN_24, /*!< noise buffer length control 24 */ - AUIDO_VAD_NOISY_BUF_LEN_28, /*!< noise buffer length control 28 */ - AUIDO_VAD_NOISY_BUF_LEN_32, /*!< noise buffer length control 32 */ -} Auido_VAD_NoisyBufferLen_Type; - -/** - * @brief noise buffer monitor control, forcing noise buffer to refresh when both:VAD goes into high and VAD high last for2'h0: 1s2'h1: 2s2'h2: 4s 2'h3: 8s this monit function is designed in case that VAD is locked into active state and noise buffer no longer refreshes itself. this will happen when audio-background-noise suddenly changes from a relative low level to a much higher one - */ -typedef enum { - AUIDO_VAD_NOISY_MONITOR_1_S, /*!< noise monitor 1 s */ - AUIDO_VAD_NOISY_MONITOR_2_S, /*!< noise monitor 2 s */ - AUIDO_VAD_NOISY_MONITOR_4_S, /*!< noise monitor 4 s */ - AUIDO_VAD_NOISY_MONITOR_8_S, /*!< noise monitor 8 s */ -} Auido_VAD_NoisyBufferMonitor_Type; - -/** - * @brief Audio Clock Configuration - */ -typedef struct { - Audio_ADC_Clock_Type adc_clock; /*!< ADC Rate Configuration */ - Audio_DAC_Clock_Type dac_clock; /*!< DAC Rate Configuration */ - BL_Fun_Type pdm_clk_inv; /*!< enable or not pdm clock inv */ - BL_Fun_Type adc_clk_inv; /*!< enable or not adc clock inv */ - BL_Fun_Type dac_clk_inv; /*!< enable or not dac clock inv */ -} Audio_Clock_CFG_Type; - -/** - * @brief Audio FIFO Configuration - */ -typedef struct { - Audio_Resolution_Type resolution; /*!< Receiving Audio Sample Resolution */ - Audio_FIFO_Ailgn_Mode ailgnMode; /*!< FIFO alignMode */ - uint8_t FifoIntThreshold; /*!< FIFO IRQ Threshold */ - Audio_FIFO_DQR_Threshold_Mode dmaThresholdMode; /*!< FIFO DRQ Threshold mode */ - BL_Fun_Type dmaEn; /*!< enable DMA FIFO interface */ -} Audio_FifoCfg_Type; - -/** - * @brief Audio Volume Configuration - */ -typedef struct { - Audio_Mute_Mode muteMode; /*!< Audio mute mode directly mute or use ramp down */ - Audio_Ramp_Rate_Type muteRmpdnRate; /*!< mute ramp down rate when voice is in up process this parameter define slope */ - Audio_Ramp_Rate_Type muteRmpupRate; /*!< mute ramp up rate when voice is in down process this parameter define slop */ - Audio_Volume_Ctr_Mode volumeCtrMode; /*!< volume will update at direct or zero crossing or ramp */ - Audio_Zero_Cross_Rate_Type volumeZeroCrossRate; /*!< when volume ctrl is zero crossing , select crossing rate */ - Audio_Ramp_Rate_Type volumeRmpRate; /*!< when volume ctrl is ramp ,select ramp rate */ - Audio_Zero_Cross_Rate_Type volumeZeroCrossTimeout; /*!< if select zero cross mode , set volume directly when time out */ -} Audio_Volume_Cfg_Type; - -/** - * @brief Audio VAD Configuration - */ -typedef struct { - Auido_VAD_Source_Type vadSource; /*!< VAD source select */ - Auido_VAD_FramingShift_Type vadFramingShift; /*!< framing-shift control */ - Auido_VAD_FramingTime_Type vadFramingTime; /*!< framing-time control, K times of framing-shift */ - Auido_VAD_IRQ_Source_Type vadIRQSource; /*!< select witch VAD output as final IRQ */ - BL_Fun_Type vadNoisyBufferMonitorEnable; /*!< enable or not noisy buffer monitor */ - Auido_VAD_NoisyBufferLen_Type vadNoisyBufferLen; /*!< noise buffer length control */ - Auido_VAD_NoisyBufferMonitor_Type vadNoisyBufferMonitor; /*!< this monit function is designed in case that VAD is locked into active state and noise buffer - no longer refreshes itself. this will happen when audio-background-noise suddenly changes from a - relative low level to a much higher one */ - uint32_t noisyBufferThr; /*!< vad_noise_th */ - uint8_t noisyBufferDiscardNumber; /*!< noise buffer discard number: */ - uint16_t noisyBufferThrBais; /*!< bias for noise threshold(s8.8, 2's) */ - uint8_t noisyBufferThrScale; /*!< noise threshold scale factor, real scale factor in circuit=dec(nth_scale)/256 */ - uint16_t vadNoisyMaxLimit; /*!< noise threshold max limitation */ - BL_Fun_Type vadNoisyMaxLimitEnable; /*!< noise threshold max limitation enable signal */ - uint16_t vadNoisyMinLimit; /*!< noise threshold min limitation */ - BL_Fun_Type vadNoisyMinLimitEnable; /*!< noise threshold min limitation enable signal */ - uint16_t vadSmoothRise; /*!< VAD output debouce, remove the positive pulse whose width is smaller than Register Value, the - real debouce time = Resister Vale * framing-shift */ - uint16_t vadSmoothFall; /*!< VAD output debouce, remove the negative pulse whose width is smaller than Register Value, the - real debouce time = Resister Vale * framing-shift */ -} Audio_VAD_Cfg_Type; - -/** - * @brief Audio agc Config - */ -typedef struct { - BL_Fun_Type agc_force_gain_en; /*!< 1 force agc gain */ - uint16_t agc_force_gain_ind; /*!< force agc gain index //default 0 -6-24 */ - uint16_t agc_max_gain_qdb; /*!< agc maximun gain //default 24 -6-24 */ - uint16_t agc_min_gain_qdb; /*!< agc minimum gain */ - uint8_t agc_level_target; /*!< agc level target //default-12 -6--20 */ - uint8_t agc_level_hyst_attack; /*!< agc level hysteresis attack */ - uint8_t agc_level_hyst_decay; /*!< agc level hysteresis decay */ - uint8_t agc_hold_time_ms; /*!< agc hold time(ms)//0-32,1-64,2-96,3-128,4-256,5-512 default 96 */ - uint8_t agc_decay_time_ms; /*!< agc decay time(ms) //0-32,1-64,2-96,3-128,4-256,5-512 default 64 */ - uint8_t agc_attack_time_ms; /*!< agc attack time(ms) //0-8,1-16,2-24,3-32,4-64,5-128 default 16 */ - BL_Fun_Type adc3_pga_hw_ctrl; /*!< 1 enable hw control */ - BL_Fun_Type adc2_pga_hw_ctrl; /*!< 1 enable hw control */ - BL_Fun_Type adc1_pga_hw_ctrl; /*!< 1 enable hw control */ - uint8_t agc_noise_gate_th; /*!< agc noise gate threshold //default -48 -32--72 */ - uint8_t agc_noise_gate_hyst; /*!< agc noise gate hysteresis //default 2 0/1/2/4 */ - uint8_t agc_silence_gain_qdb; /*!< agc silence gain qdb //s9.2, default 0 */ - uint8_t agc_silence_gain_wait_ms; /*!< agc silence gain wait time(ms) */ - uint8_t agc_noise_enter_time_ms; /*!< agc noise enter time //default 0 NORMAL_SILENCE_DEBOUNCE_TIME_MS 0/1/2/4/8/16/32/64/96/128 */ - uint8_t agc_noise_exit_time_ms; /*!< agc noise exit time(ms) //default 0 SILENCE_NORMAL_DEBOUNCE_TIME_MS 0/1/2/4/8/16/32/64/96/128 */ - uint8_t agc_dbv_settle_time; /*!< agc dbv settle time */ - Audio_AGC_Src_Type agc_src_select; /*!< agc source select 0 ch0 absolute value, 1 ch1 absolute value, 2 ch2 absolute value, 3 maximum - value of ch0/1/2 */ - Audio_AGC_Detect_Mode agc_detect_mode; /*!< 0 detect by peak, 1 detect by average */ - uint8_t agc_attack_time; /*!< agc peak filter attack time */ - uint8_t agc_release_time; /*!< agc peak filter release time */ - uint8_t agc_average_time; /*!< agc rms filter average time */ - BL_Fun_Type agc_pga_ctrl_en; /*!< 1 enable pga controlled by hw agc */ -} Audio_AGC_Config_Type; - -/** - * @brief Audio agc Config - */ -typedef struct { - Auido_DRC_Data_Type drc_raw_sel; /*!< drc raw data select 0 ch0, 1 ch1, 2 (ch0+ch1)/2, 3 max(ch0,ch1) */ - Auido_DRC_Data_Type drc_peak_sel; /*!< drc peak data select 0 ch0, 1 ch1, 2 (ch0+ch1)/2, 3 max(ch0,ch1) */ - Auido_DRC_Data_Type drc_avg_sel; /*!< drc average data select 0 ch0, 1 ch1, 2 (ch0+ch1)/2, 3 max(ch0,ch1) */ - BL_Fun_Type drc_avg_en; /*!< 1 enable average filter */ - uint8_t drc_avg_time; /*!< drc average filter period */ - uint8_t drc_att_time; /*!< drc peak filter attack time */ - uint8_t drc_rls_time; /*!< drc peak filter release time */ - uint8_t drc_ngt_downsample_en; /*!< 1 drc and noise gate down sample by dac_rate */ - uint8_t drc_threshold_l; /*!< drc threshold of limiter */ - uint8_t drc_threshold_c; /*!< drc threshold of compressor */ - uint8_t drc_threshold_e; /*!< drc threshold of expander */ - uint8_t drc_slope_mode_c; /*!< drc compressor slope mode 0 1-8/8, 1 1-5/8, 2 1-4/8, 3 1-2/8 */ - uint8_t drc_slope_mode_e; /*!< drc expander slope mode 0 0, 1 -1, 2 -2, 3 -3 */ - uint8_t drc_makeup_gain; /*!< drc make up gain */ - uint8_t drc_attack_time; /*!< drc attack time */ - uint8_t drc_release_time; /*!< drc release time */ - BL_Fun_Type ngt_en; /*!< 1 enable noise gate */ - Auido_DRC_Data_Type ngt_src_sel; /*!< noise gate source select 0 ch0, 1 ch1, 2 (ch0+ch1)/2, 3 max(ch0,ch1) */ - uint8_t ngt_avg_time; /*!< noise gate average time */ - uint8_t ngt_threshold; /*!< noise gate threshold */ - uint8_t ngt_hysteresis; /*!< noise gate hysteresis */ - BL_Fun_Type ngt_noise_hold_en; /*!< noise hold enable */ - uint8_t ngt_noise_hold_time_k; /*!< noise hold time k */ - BL_Fun_Type ngt_signal_hold_en; /*!< signal hold enable */ - uint8_t ngt_signal_hold_time_k; /*!< signal hold time k */ - BL_Fun_Type ngt_dmute_on; /*!< 1 enanle noise gate mute hw */ - BL_Fun_Type zd_en; /*!< two channels, 0 zd disabled, 1 zd on channel0, 2 zd on channel1, 3 zd on both channels */ - uint16_t zd_time; /*!< number of zeros */ -} Audio_DRC_Config_Type; - -/*@} end of group AUDIO_Public_Types */ - -/** @defgroup AUDIO_Public_Constants - * @{ - */ - -/** @defgroup AUDIO_ADC_ID_TYPE - * @{ - */ -#define IS_AUDIO_ADC_ID_TYPE(type) (((type) == AUDIO_ADC_0) || \ - ((type) == AUDIO_ADC_1) || \ - ((type) == AUDIO_ADC_2)) - -/** @defgroup AUDIO_DAC_ID_TYPE - * @{ - */ -#define IS_AUDIO_DAC_ID_TYPE(type) (((type) == AUDIO_DAC_0) || \ - ((type) == AUDIO_DAC_1)) - -/** @defgroup AUDIO_AEC_ID_TYPE - * @{ - */ -#define IS_AUDIO_AEC_ID_TYPE(type) (((type) == AUDIO_AEC_0) || \ - ((type) == AUDIO_AEC_1)) - -/** @defgroup AUDIO_PDM_ID_TYPE - * @{ - */ -#define IS_AUDIO_PDM_ID_TYPE(type) (((type) == AUDIO_PDM_0) || \ - ((type) == AUDIO_PDM_1) || \ - ((type) == AUDIO_PDM_2)) - -/** @defgroup AUDIO_MUTE_TYPE - * @{ - */ -#define IS_AUDIO_MUTE_TYPE(type) (((type) == AUDIO_UNMUTE) || \ - ((type) == AUDIO_MUTE)) - -/** @defgroup AUDIO_ADC_CLOCK_TYPE - * @{ - */ -#define IS_AUDIO_ADC_CLOCK_TYPE(type) (((type) == AUDIO_ADC_8_KHZ) || \ - ((type) == AUDIO_ADC_16_KHZ) || \ - ((type) == AUDIO_ADC_24_KHZ) || \ - ((type) == AUDIO_ADC_32_KHZ) || \ - ((type) == AUDIO_ADC_48_KHZ) || \ - ((type) == AUDIO_ADC_96_KHZ)) - -/** @defgroup AUDIO_DAC_CLOCK_TYPE - * @{ - */ -#define IS_AUDIO_DAC_CLOCK_TYPE(type) (((type) == AUDIO_DAC_8_KHZ) || \ - ((type) == AUDIO_DAC_16_KHZ) || \ - ((type) == AUDIO_DAC_24_KHZ) || \ - ((type) == AUDIO_DAC_32_KHZ) || \ - ((type) == AUDIO_DAC_48_KHZ) || \ - ((type) == AUDIO_DAC_96_KHZ) || \ - ((type) == AUDIO_DAC_192_KHZ)) - -/** @defgroup AUDIO_ADC_SOURCE_TYPE - * @{ - */ -#define IS_AUDIO_ADC_SOURCE_TYPE(type) (((type) == AUDIO_ADC_ANALOG) || \ - ((type) == AUDIO_ADC_PDM)) - -/** @defgroup AUDIO_LFSR_TYPE - * @{ - */ -#define IS_AUDIO_LFSR_TYPE(type) (((type) == AUDIO_LFSR32) || \ - ((type) == AUDIO_LFSR24) || \ - ((type) == AUDIO_LFSR16) || \ - ((type) == AUDIO_LFSR12)) - -/** @defgroup AUDIO_MIXER_MODE - * @{ - */ -#define IS_AUDIO_MIXER_MODE(type) (((type) == AUDIO_SECOND_DEBUG_MODE) || \ - ((type) == AUDIO_SIDETONE_LOOPBACK)) - -/** @defgroup AUDIO_MIXER_VOLUME_TYPE - * @{ - */ -#define IS_AUDIO_MIXER_VOLUME_TYPE(type) (((type) == AUDIO_MIXER_VOLUME_0_DB) || \ - ((type) == AUDIO_MIXER_VOLUME_6_DB) || \ - ((type) == AUDIO_MIXER_VOLUME_12_DB) || \ - ((type) == AUDIO_MIXER_VOLUME_18_DB) || \ - ((type) == AUDIO_MIXER_VOLUME_36_DB) || \ - ((type) == AUDIO_MIXER_VOLUME_54_DB) || \ - ((type) == AUDIO_MIXER_VOLUME_72_DB) || \ - ((type) == AUDIO_MIXER_VOLUME_MUTE)) - -/** @defgroup AUDIO_MIXER_ID_TYPE - * @{ - */ -#define IS_AUDIO_MIXER_ID_TYPE(type) (((type) == AUDIO_MIXER_ID_0) || \ - ((type) == AUDIO_MIXER_ID_1)) - -/** @defgroup AUDIO_DAC_ORDER_TYPE - * @{ - */ -#define IS_AUDIO_DAC_ORDER_TYPE(type) (((type) == AUDIO_DAC_2_ORDER) || \ - ((type) == AUDIO_DAC_3_ORDER)) - -/** @defgroup AUDIO_AEC_ATTEN_MODE - * @{ - */ -#define IS_AUDIO_AEC_ATTEN_MODE(type) (((type) == AUDIO_AEC_NO_DROP) || \ - ((type) == AUDIO_AEC_DROP_1LSB) || \ - ((type) == AUDIO_AEC_DROP_2LSB) || \ - ((type) == AUDIO_AEC_DROP_3LSB) || \ - ((type) == AUDIO_AEC_DROP_6LSB) || \ - ((type) == AUDIO_AEC_DROP_9LSB) || \ - ((type) == AUDIO_AEC_DROP_12LSB)) - -/** @defgroup AUDIO_PDM_SOURCE_TYPE - * @{ - */ -#define IS_AUDIO_PDM_SOURCE_TYPE(type) (((type) == AUDIO_PDM_0_L) || \ - ((type) == AUDIO_PDM_0_R) || \ - ((type) == AUDIO_PDM_1_L) || \ - ((type) == AUDIO_PDM_1_R) || \ - ((type) == AUDIO_PDM_2_L) || \ - ((type) == AUDIO_PDM_2_R)) - -/** @defgroup AUDIO_RESOLUTION_TYPE - * @{ - */ -#define IS_AUDIO_RESOLUTION_TYPE(type) (((type) == AUDIO_RES_16_BITS) || \ - ((type) == AUDIO_RES_20_BITS)) - -/** @defgroup AUDIO_FIFO_AILGN_MODE - * @{ - */ -#define IS_AUDIO_FIFO_AILGN_MODE(type) (((type) == AUDIO_FIFO_AILGN_MSB_AT_BIT31) || \ - ((type) == AUDIO_FIFO_AILGN_MSB_AT_BIT23) || \ - ((type) == AUDIO_FIFO_AILGN_MSB_AT_BIT19) || \ - ((type) == AUDIO_FIFO_AILGN_MSB_AT_BIT15)) - -/** @defgroup AUDIO_FIFO_DQR_THRESHOLD_MODE - * @{ - */ -#define IS_AUDIO_FIFO_DQR_THRESHOLD_MODE(type) (((type) == AUDIO_DRQ_EQUEL_TO_IRQ) || \ - ((type) == AUDIO_DRQ_THR_AS_4_TX_8_RX) || \ - ((type) == AUDIO_DRQ_THR_AS_8_TX_16_RX) || \ - ((type) == AUDIO_DRQ_THR_AS_16_TX_32_RX)) - -/** @defgroup AUDIO_INT_TYPE - * @{ - */ -#define IS_AUDIO_INT_TYPE(type) (((type) == AUDIO_INT_RX_FIFO_THR) || \ - ((type) == AUDIO_INT_RX_FIFO_OVERRUN) || \ - ((type) == AUDIO_INT_RX_FIFO_UNDERRUN) || \ - ((type) == AUDIO_INT_TX_FIFO_THR) || \ - ((type) == AUDIO_INT_TX_FIFO_OVERRUN) || \ - ((type) == AUDIO_INT_TX_FIFO_UNDERRUN) || \ - ((type) == AUDIO_INT_ADC0_SET_VOLUME_DONE) || \ - ((type) == AUDIO_INT_ADC1_SET_VOLUME_DONE) || \ - ((type) == AUDIO_INT_ADC2_SET_VOLUME_DONE) || \ - ((type) == AUDIO_INT_DAC0_SET_VOLUME_DONE) || \ - ((type) == AUDIO_INT_DAC1_SET_VOLUME_DONE) || \ - ((type) == AUDIO_INT_VAD) || \ - ((type) == AUDIO_INT_NUM_ALL)) - -/** @defgroup AUDIO_PEQ_QTFM_TYPE - * @{ - */ -#define IS_AUDIO_PEQ_QTFM_TYPE(type) (((type) == AUDIO_PEQ_QFMT_20_17) || \ - ((type) == AUDIO_PEQ_QFMT_20_16)) - -/** @defgroup AUDIO_MUTE_MODE - * @{ - */ -#define IS_AUDIO_MUTE_MODE(type) (((type) == AUIDO_MUTE_DIRECTLY) || \ - ((type) == AUDIO_MUTE_WITH_RAMP_DOWN)) - -/** @defgroup AUDIO_RAMP_RATE_TYPE - * @{ - */ -#define IS_AUDIO_RAMP_RATE_TYPE(type) (((type) == AUIDO_RAMP_RATE_2_FS) || \ - ((type) == AUIDO_RAMP_RATE_4_FS) || \ - ((type) == AUIDO_RAMP_RATE_8_FS) || \ - ((type) == AUIDO_RAMP_RATE_16_FS) || \ - ((type) == AUIDO_RAMP_RATE_32_FS) || \ - ((type) == AUIDO_RAMP_RATE_64_FS) || \ - ((type) == AUIDO_RAMP_RATE_128_FS) || \ - ((type) == AUIDO_RAMP_RATE_256_FS) || \ - ((type) == AUIDO_RAMP_RATE_512_FS) || \ - ((type) == AUIDO_RAMP_RATE_1024_FS) || \ - ((type) == AUIDO_RAMP_RATE_2048_FS)) - -/** @defgroup AUDIO_ZERO_CROSS_RATE_TYPE - * @{ - */ -#define IS_AUDIO_ZERO_CROSS_RATE_TYPE(type) (((type) == AUIDO_ZERO_CROSS_RATE_2_FS) || \ - ((type) == AUIDO_ZERO_CROSS_RATE_4_FS) || \ - ((type) == AUIDO_ZERO_CROSS_RATE_8_FS) || \ - ((type) == AUIDO_ZERO_CROSS_RATE_16_FS) || \ - ((type) == AUIDO_ZERO_CROSS_RATE_32_FS) || \ - ((type) == AUIDO_ZERO_CROSS_RATE_64_FS) || \ - ((type) == AUIDO_ZERO_CROSS_RATE_128_FS) || \ - ((type) == AUIDO_ZERO_CROSS_RATE_256_FS) || \ - ((type) == AUIDO_ZERO_CROSS_RATE_512_FS) || \ - ((type) == AUIDO_ZERO_CROSS_RATE_1024_FS) || \ - ((type) == AUIDO_ZERO_CROSS_RATE_2048_FS)) - -/** @defgroup AUDIO_VOLUME_CTR_MODE - * @{ - */ -#define IS_AUDIO_VOLUME_CTR_MODE(type) (((type) == AUIDO_VOLUME_UPDATE_FORCE) || \ - ((type) == AUIDO_VOLUME_UPDATE_AT_ZERO_CROSSING) || \ - ((type) == AUIDO_VOLUME_UPDATE_AT_RAMP)) - -/** @defgroup AUDIO_AGC_DETECT_MODE - * @{ - */ -#define IS_AUDIO_AGC_DETECT_MODE(type) (((type) == AUIDO_AGC_DETECT_BY_PEAK) || \ - ((type) == AUIDO_AGC_DETECT_BY_AVERAGE)) - -/** @defgroup AUDIO_AGC_SRC_TYPE - * @{ - */ -#define IS_AUDIO_AGC_SRC_TYPE(type) (((type) == AUIDO_AGC_CH0_ABSOLUTE_VALUE) || \ - ((type) == AUIDO_AGC_CH1_ABSOLUTE_VALUE) || \ - ((type) == AUIDO_AGC_CH2_ABSOLUTE_VALUE) || \ - ((type) == AUIDO_AGC_MAXIMUM_VALUE_OF_CH012)) - -/** @defgroup AUIDO_DRC_DATA_TYPE - * @{ - */ -#define IS_AUIDO_DRC_DATA_TYPE(type) (((type) == AUIDO_DRC_DATA_SOURCE_CH0) || \ - ((type) == AUIDO_DRC_DATA_SOURCE_CH1) || \ - ((type) == AUIDO_DRC_DATA_SOURCE_AVERAGE_OF_CH0_CH1) || \ - ((type) == AUIDO_DRC_DATA_SOURCE_MAX_OF_CH0_CH1)) - -/** @defgroup AUIDO_VAD_SOURCE_TYPE - * @{ - */ -#define IS_AUIDO_VAD_SOURCE_TYPE(type) (((type) == AUIDO_VAD_DATA_SOURCE_ADC_CH0) || \ - ((type) == AUIDO_VAD_DATA_SOURCE_ADC_CH1) || \ - ((type) == AUIDO_VAD_DATA_SOURCE_ADC_CH2) || \ - ((type) == AUIDO_VAD_DATA_SOURCE_AEC_CH0) || \ - ((type) == AUIDO_VAD_DATA_SOURCE_AEC_CH1) || \ - ((type) == AUDIO_VAD_DATA_SOURCE_AVERAGE_ADC_CH0_ADD_CH1) || \ - ((type) == AUDIO_VAD_DATA_SOURCE_AVERAGE_ADC_CH1_ADD_CH2) || \ - ((type) == AUDIO_VAD_DATA_SOURCE_AVERAGE_ADC_CH2_ADD_CH0)) - -/** @defgroup AUIDO_VAD_FRAMINGSHIFT_TYPE - * @{ - */ -#define IS_AUIDO_VAD_FRAMINGSHIFT_TYPE(type) (((type) == AUIDO_VAD_FRAMING_SHIFT_2P5_MS) || \ - ((type) == AUIDO_VAD_FRAMING_SHIFT_5_MS) || \ - ((type) == AUIDO_VAD_FRAMING_SHIFT_7P5_MS) || \ - ((type) == AUIDO_VAD_FRAMING_SHIFT_10_MS) || \ - ((type) == AUIDO_VAD_FRAMING_SHIFT_12P5_MS) || \ - ((type) == AUIDO_VAD_FRAMING_SHIFT_15_MS) || \ - ((type) == AUIDO_VAD_FRAMING_SHIFT_17P5_MS) || \ - ((type) == AUIDO_VAD_FRAMING_SHIFT_20_MS)) - -/** @defgroup AUIDO_VAD_FRAMINGTIME_TYPE - * @{ - */ -#define IS_AUIDO_VAD_FRAMINGTIME_TYPE(type) (((type) == AUIDO_VAD_FRAMING_TIME_2) || \ - ((type) == AUIDO_VAD_FRAMING_TIME_3) || \ - ((type) == AUIDO_VAD_FRAMING_TIME_4) || \ - ((type) == AUIDO_VAD_FRAMING_TIME_5)) - -/** @defgroup AUIDO_VAD_IRQ_SOURCE_TYPE - * @{ - */ -#define IS_AUIDO_VAD_IRQ_SOURCE_TYPE(type) (((type) == AUIDO_VAD_ORIGINAL_OUTPUT) || \ - ((type) == AUIDO_VAD_OUT0) || \ - ((type) == AUIDO_VAD_OUT1) || \ - ((type) == AUIDO_VAD_OUT2)) - -/** @defgroup AUIDO_VAD_NOISYBUFFERLEN_TYPE - * @{ - */ -#define IS_AUIDO_VAD_NOISYBUFFERLEN_TYPE(type) (((type) == AUIDO_VAD_NOISY_BUF_LEN_4) || \ - ((type) == AUIDO_VAD_NOISY_BUF_LEN_8) || \ - ((type) == AUIDO_VAD_NOISY_BUF_LEN_12) || \ - ((type) == AUIDO_VAD_NOISY_BUF_LEN_16) || \ - ((type) == AUIDO_VAD_NOISY_BUF_LEN_20) || \ - ((type) == AUIDO_VAD_NOISY_BUF_LEN_24) || \ - ((type) == AUIDO_VAD_NOISY_BUF_LEN_28) || \ - ((type) == AUIDO_VAD_NOISY_BUF_LEN_32)) - -/** @defgroup AUIDO_VAD_NOISYBUFFERMONITOR_TYPE - * @{ - */ -#define IS_AUIDO_VAD_NOISYBUFFERMONITOR_TYPE(type) (((type) == AUIDO_VAD_NOISY_MONITOR_1_S) || \ - ((type) == AUIDO_VAD_NOISY_MONITOR_2_S) || \ - ((type) == AUIDO_VAD_NOISY_MONITOR_4_S) || \ - ((type) == AUIDO_VAD_NOISY_MONITOR_8_S)) - -/*@} end of group AUDIO_Public_Constants */ - -/** @defgroup AUDIO_Public_Macros - * @{ - */ -#define AUDIO_PRIVATE_BIT_POS(n) (0x01 << n) -#define ADC1_DATA_CHANNEL_FIFO_EN AUDIO_PRIVATE_BIT_POS(0) -#define ADC2_DATA_CHANNEL_FIFO_EN AUDIO_PRIVATE_BIT_POS(1) -#define ADC3_DATA_CHANNEL_FIFO_EN AUDIO_PRIVATE_BIT_POS(2) -#define AEC1_DATA_CHANNEL_FIFO_EN AUDIO_PRIVATE_BIT_POS(3) -#define AEC2_DATA_CHANNEL_FIFO_EN AUDIO_PRIVATE_BIT_POS(4) -#define DAC1_DATA_CHANNEL_FIFO_EN AUDIO_PRIVATE_BIT_POS(0) -#define DAC2_DATA_CHANNEL_FIFO_EN AUDIO_PRIVATE_BIT_POS(1) - -/*@} end of group AUDIO_Public_Macros */ - -/** @defgroup AUDIO_Public_Functions - * @{ - */ -void Audio_Clock_Init(Audio_Clock_CFG_Type *cfg); -//debug api -void Debug0_Write(uint32_t wCmd); -uint32_t Debug1_Read(void); -void Debug2_Write(uint32_t wCmd); -void Debug3_Write(uint32_t wCmd); -// -BL_Err_Type Audio_Tx_Source_DAC_Sel(uint8_t tx_channel, Audio_DAC_ID_Type dac_id); -BL_Err_Type Audio_Rx_Source_ADC_Sel(uint8_t rx_channel, Audio_ADC_ID_Type adc_id); -BL_Err_Type Audio_Rx_Source_AEC_Sel(uint8_t rx_channel, Audio_AEC_ID_Type aec_id); -// -void Audio_Set_ADC_Source(Audio_ADC_ID_Type id, Audio_ADC_Source_Type adc_source); -// -void Audio_AEC_Enable(Audio_AEC_ID_Type id); -void Audio_AEC_Disable(Audio_AEC_ID_Type id); -void Audio_ADC_Enable(Audio_ADC_ID_Type id); -void Audio_ADC_Disable(Audio_ADC_ID_Type id); -void Audio_DAC_Enable(Audio_DAC_ID_Type id); -void Audio_DAC_Disable(Audio_DAC_ID_Type id); -//performance -void Audio_Set_HPF_Parameter(Audio_ADC_ID_Type id, uint8_t k1_enable, uint8_t k1, - uint8_t k2_enable, uint8_t k2); -//0x08 -void Audio_Set_ADC_LFSR(Audio_LFSR_Type lfsrType); -BL_Sts_Type Audio_Get_ADC_LFSR(void); -void Audio_Set_ADC_Scaling_Value(Audio_ADC_ID_Type id, uint8_t scalingVal); -void Audio_Set_Fir_Mode(Audio_ADC_ID_Type id, uint8_t enable); -//0x10 -void Audio_ADC_Mash_Bit_Swap(Audio_ADC_ID_Type id, uint8_t swap); -void Audio_ADC_PDM_Inv_Swap(Audio_ADC_ID_Type id, uint8_t swap); -void Audio_ADC_Set_PDM_Value(uint8_t pdm_l, uint8_t pdm_h); -//0x14 -void Audio_Set_DAC_LFSR(Audio_LFSR_Type lfsrType); -void Audio_Set_DAC_Dither(uint8_t enable, uint8_t amp); -void Audio_Set_DAC_Scaling(uint8_t enable, uint8_t scaling); -void Audio_Set_DAC_Order(Audio_DAC_Order_Type order); -void Audio_Set_DAC_Dwa_Swap(uint8_t swap); -void Audio_Set_DAC_Dwa_Bypass(uint8_t bypass); -//0x18 -void Audio_Set_AEC_Record_Vid(uint8_t enable, uint8_t div); -void Audio_Set_AEC_Atten_mode(Audio_AEC_ID_Type aec_id, Audio_AEC_Atten_Mode mode); -//0x1c PDM Source sel -void Audio_ADC_PDM_Channel_Sel(Audio_PDM_ID_Type id, - Audio_PDM_Source_Type pdmSel); -void Audio_ADC_PDM_Enable(Audio_PDM_ID_Type id); -void Audio_ADC_PDM_Disable(Audio_PDM_ID_Type id); -//mix about -void Audio_Set_Mixer_Mode(uint8_t enable, Audio_Mixer_ID_Type mixerId, Audio_Mixer_Mode mode, - Audio_ADC_ID_Type sidetoneChannel, Audio_Mixer_Volume_Type Volume); -//int about -void Auido_IntMask(Audio_INT_Type intType, BL_Mask_Type intMask); -void Auido_IntClear(Audio_INT_Type intType); -BL_Err_Type Audio_Int_Callback_Install(Audio_INT_Type intType, intCallback_Type *cbFun); -BL_Sts_Type Audio_GetIntStatus(Audio_INT_Type intType); -void Audio_RxFifoClear(void); -uint32_t Audio_GetRxFifoCount(void); -uint32_t Audio_ReadRxFifo(void); -void Audio_TxFifoClear(void); -uint32_t Audio_GetTxFifoCount(void); -void Audio_WriteTxFifo(uint32_t da); -//fifo about -void Audio_RxFifoConfig(Audio_FifoCfg_Type *cfg); -void Audio_TxFifoConfig(Audio_FifoCfg_Type *Cfg); -void Audio_RxFifoEnable(uint8_t ch); -void Audio_RxFifoDisable(uint8_t ch); -void Audio_TxFifoEnable(uint8_t ch); -void Audio_TxFifoDisable(uint8_t ch); -//PEQ about -BL_Err_Type Audio_PEQ_Config(uint8_t peq_index, uint8_t peqBypass, Audio_PEQ_QTFM_Type qtfm, - uint32_t *b_pra, uint32_t *a_pra); -//volume control -BL_Err_Type Audio_DAC_Set_Mute(BL_Fun_Type muteSyncAllDac, Audio_DAC_ID_Type dac_id, - Audio_Mute_Type mute); -BL_Err_Type Audio_ADC_Set_Mute(BL_Fun_Type muteSyncAllAdc, Audio_ADC_ID_Type adc_id, Audio_Mute_Type mute); -BL_Err_Type Audio_ADC_Software_Volume_Config(Audio_ADC_ID_Type adc_id, Audio_Volume_Cfg_Type *cfg); -BL_Err_Type Audio_DAC_Software_Volume_Config(Audio_DAC_ID_Type dac_id, Audio_Volume_Cfg_Type *cfg); -BL_Err_Type Audio_ADC_Set_Volume(BL_Fun_Type volumeSyncAllAdc, Audio_ADC_ID_Type adc_id, uint16_t volume); -BL_Err_Type Audio_DAC_Set_Volume(BL_Fun_Type volumeSyncAllDac, Audio_DAC_ID_Type dac_id, uint16_t volume); -BL_Err_Type Audio_ADC_Set_Volume_Block(BL_Fun_Type volumeSyncAllAdc, Audio_ADC_ID_Type adc_id, uint16_t volume, - uint32_t blockTimeout); -BL_Err_Type Audio_DAC_Set_Volume_Block(BL_Fun_Type volumeSyncAllDac, Audio_DAC_ID_Type dac_id, uint16_t volume, - uint32_t blockTimeout); -BL_Err_Type Audio_ADC_Set_Volume_Reg(BL_Fun_Type volumeSyncAllAdc, Audio_ADC_ID_Type adc_id, uint16_t volume); -BL_Err_Type Audio_DAC_Set_Volume_Reg(BL_Fun_Type volumeSyncAllDac, Audio_DAC_ID_Type dac_id, uint16_t volume); -void Audio_ADC_Reset_Volume_Update(Audio_ADC_ID_Type adc_id); -void Audio_ADC_Reset_Volume_Update(Audio_ADC_ID_Type dac_id); -void Audio_Reset_Volume_All_Update(uint8_t isAdcOrDac); -BL_Err_Type Audio_ADC_Hardware_Volume_Config(Audio_Volume_Cfg_Type *cfg); -uint16_t Audio_ADC_Get_Hardware_Volume(void); -uint16_t Audio_ADC_Get_Volume(Audio_ADC_ID_Type adc_id); -uint16_t Audio_DAC_Get_Volume(Audio_DAC_ID_Type dac_id); -BL_Sts_Type Audio_IS_ADC_Mute_Done(Audio_ADC_ID_Type adc_id); -BL_Sts_Type Audio_IS_ADC_Volume_Set_Busy(Audio_ADC_ID_Type adc_id); -BL_Sts_Type Audio_IS_DAC_Mute_Set_Done(Audio_DAC_ID_Type dac_id); -BL_Sts_Type Audio_IS_DAC_Volume_Set_Busy(Audio_DAC_ID_Type dac_id); -//agc about -void Audio_AGC_Init(uint8_t enable, Audio_AGC_Config_Type *cfg); -//drc about -void Audio_DRC_Init(uint8_t enable, Audio_DRC_Config_Type *cfg); -//vad about -void Audio_VAD_Init(Audio_VAD_Cfg_Type *cfg); -void Audio_VAD_Enable(void); -void Audio_VAD_Disable(void); -uint32_t Audio_VAD_Get_EK(void); -void Audio_DAC_Reset_Volume_Update(Audio_DAC_ID_Type dac_id); - -/*power */ -void Audio_Poweron(void); - -/*analog gain */ -void Audio_SetADCAnalogGain(Audio_ADC_ID_Type adc, uint8_t analogGain); -void Audio_SetDACAnalogGain(Audio_DAC_ID_Type dac, uint8_t analogGain); - -void AUDIO_IRQHandler(void); - -/*@} end of group AUDIO_Public_Functions */ - -/*@} end of group AUDIO */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_AUDIO_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_aupdm.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_aupdm.h deleted file mode 100644 index 3387cb9dfa..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_aupdm.h +++ /dev/null @@ -1,267 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_audiopdm.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_AUDIOPDM_H__ -#define __BL808_AUDIOPDM_H__ - -#include "pdm_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup AUDIOPDM - * @{ - */ - -/** @defgroup AUDIOPDM_Public_Types - * @{ - */ - -/** - * @brief Aupdm ADC ID - */ -typedef enum { - AUPDM_ADC_0, /*!< Aupdm ADC 0 */ - AUPDM_ADC_1, /*!< Aupdm ADC 1 */ - AUPDM_ADC_2, /*!< Aupdm ADC 2 */ -} Aupdm_ADC_ID_Type; - -/** - * @brief Aupdm PDM ADC Clock - */ -typedef enum { - AUPDM_PDM_ADC_8_KHZ, /*!< Aupdm PDM ADC Clock set as 8KHZ */ - AUPDM_PDM_ADC_16_KHZ, /*!< Aupdm PDM ADC Clock set as 16KHZ */ - AUPDM_PDM_ADC_24_KHZ, /*!< Aupdm PDM ADC Clock set as 24KHZ */ - AUPDM_PDM_ADC_32_KHZ, /*!< Aupdm PDM ADC Clock set as 32KHZ */ - AUPDM_PDM_ADC_48_KHZ, /*!< Aupdm PDM ADC Clock set as 48KHZ */ - AUPDM_PDM_ADC_96_KHZ, /*!< Aupdm PDM ADC Clock set as 96KHZ */ -} Aupdm_ADC_Clock_Type; - -/** - * @brief Aupdm PDM ID - */ -typedef enum { - AUPDM_PDM_0, /*!< select PDM Channel 0 */ - AUPDM_PDM_1, /*!< select PDM Channel 1 */ - AUPDM_PDM_2, /*!< select PDM Channel 2 */ -} Aupdm_PDM_ID_Type; - -/** - * @brief Aupdm PDM Source Select - */ -typedef enum { - AUPDM_PDM_0_L, /*!< select PDM0 Left Channel */ - AUPDM_PDM_0_R, /*!< select PDM0 Right Channel */ - AUPDM_PDM_1_L, /*!< select PDM1 Left Channel */ - AUPDM_PDM_1_R, /*!< select PDM1 Right Channel */ - AUPDM_PDM_2_L, /*!< select PDM2 Left Channel */ - AUPDM_PDM_2_R, /*!< select PDM2 Right Channel */ -} Aupdm_PDM_Source_Type; - -/** - * @brief Aupdm Resolution - */ -typedef enum { - AUPDM_RES_16_BITS, /*!< select ADC Resolution as 16 bit */ - AUPDM_RES_20_BITS, /*!< select ADC Resolution as 20 bit */ -} Aupdm_Resolution_Type; - -/** - * @brief Aupdm Resolution - */ -typedef enum { - AUPDM_FIFO_AILGN_MSB_AT_BIT31, /*!< Mode 0: Valid data's MSB is at [31] of FIFO register */ - AUPDM_FIFO_AILGN_MSB_AT_BIT23, /*!< Mode 1: Valid data's MSB is at [23] of FIFO register */ - AUPDM_FIFO_AILGN_MSB_AT_BIT19, /*!< Mode 2: Valid data's MSB is at [19] of FIFO register */ - AUPDM_FIFO_AILGN_MSB_AT_BIT15, /*!< Mode 3: Valid data's MSB is at [15] of FIFO register */ -} Aupdm_FIFO_Ailgn_Mode; - -/** - * @brief Aupdm Resolution - */ -typedef enum { - AUPDM_DRQ_EQUEL_TO_IRQ, /*!< DMA request threhold is equeal to Interrupt threhold */ - AUPDM_DRQ_THR_AS_4_TX_8_RX, /*!< DMA request threhold is 4 when config TX FIFO DRQ , 8 when config RX FIFO */ - AUPDM_DRQ_THR_AS_8_TX_16_RX, /*!< DMA request threhold is 8 when config TX FIFO DRQ , 16 when config RX FIFO */ - AUPDM_DRQ_THR_AS_16_TX_32_RX, /*!< DMA request threhold is 16 when config TX FIFO DRQ , 32 when config RX FIFO */ -} Aupdm_FIFO_DQR_Threshold_Mode; - -/** - * @brief Aupdm initerrupt type - */ -typedef enum { - AUPDM_INT_RX_FIFO_THR, /*!< Aupdm RX FIFO counter upper than threhold interrupt */ - AUPDM_INT_RX_FIFO_OVERRUN, /*!< Aupdm RX FIFO overrun */ - AUPDM_INT_RX_FIFO_UNDERRUN, /*!< Aupdm RX FIFO underrun */ - AUPDM_INT_NUM_ALL, /*!< Aupdm int all */ -} Aupdm_INT_Type; - -/** - * @brief Aupdm PDM Clock Configuration - */ -typedef struct { - Aupdm_ADC_Clock_Type adc_clock; /*!< ADC Rate Configuration */ - BL_Fun_Type pdm_clk_inv; /*!< enable or not pdm clock inv */ - BL_Fun_Type adc_clk_inv; /*!< enable or not adc clock inv */ -} Aupdm_Clock_CFG_Type; - -/** - * @brief Aupdm FIFO Configuration - */ -typedef struct { - Aupdm_Resolution_Type resolution; /*!< Receiving Aupdm Sample Resolution */ - Aupdm_FIFO_Ailgn_Mode ailgnMode; /*!< FIFO alignMode */ - uint8_t FifoIntThreshold; /*!< FIFO IRQ Threshold */ - Aupdm_FIFO_DQR_Threshold_Mode dmaThresholdMode; /*!< FIFO DRQ Threshold mode */ - BL_Fun_Type dmaEn; /*!< enable DMA FIFO interface */ -} Aupdm_FifoCfg_Type; - -/*@} end of group AUDIOPDM_Public_Types */ - -/** @defgroup AUDIOPDM_Public_Constants - * @{ - */ - -/** @defgroup AUPDM_ADC_ID_TYPE - * @{ - */ -#define IS_AUPDM_ADC_ID_TYPE(type) (((type) == AUPDM_ADC_0) || \ - ((type) == AUPDM_ADC_1) || \ - ((type) == AUPDM_ADC_2)) - -/** @defgroup AUPDM_ADC_CLOCK_TYPE - * @{ - */ -#define IS_AUPDM_ADC_CLOCK_TYPE(type) (((type) == AUPDM_PDM_ADC_8_KHZ) || \ - ((type) == AUPDM_PDM_ADC_16_KHZ) || \ - ((type) == AUPDM_PDM_ADC_24_KHZ) || \ - ((type) == AUPDM_PDM_ADC_32_KHZ) || \ - ((type) == AUPDM_PDM_ADC_48_KHZ) || \ - ((type) == AUPDM_PDM_ADC_96_KHZ)) - -/** @defgroup AUPDM_PDM_ID_TYPE - * @{ - */ -#define IS_AUPDM_PDM_ID_TYPE(type) (((type) == AUPDM_PDM_0) || \ - ((type) == AUPDM_PDM_1) || \ - ((type) == AUPDM_PDM_2)) - -/** @defgroup AUPDM_PDM_SOURCE_TYPE - * @{ - */ -#define IS_AUPDM_PDM_SOURCE_TYPE(type) (((type) == AUPDM_PDM_0_L) || \ - ((type) == AUPDM_PDM_0_R) || \ - ((type) == AUPDM_PDM_1_L) || \ - ((type) == AUPDM_PDM_1_R) || \ - ((type) == AUPDM_PDM_2_L) || \ - ((type) == AUPDM_PDM_2_R)) - -/** @defgroup AUPDM_RESOLUTION_TYPE - * @{ - */ -#define IS_AUPDM_RESOLUTION_TYPE(type) (((type) == AUDIO_RES_16_BITS) || \ - ((type) == AUDIO_RES_20_BITS)) - -/** @defgroup AUPDM_FIFO_AILGN_MODE - * @{ - */ -#define IS_AUPDM_FIFO_AILGN_MODE(type) (((type) == AUPDM_FIFO_AILGN_MSB_AT_BIT31) || \ - ((type) == AUPDM_FIFO_AILGN_MSB_AT_BIT23) || \ - ((type) == AUPDM_FIFO_AILGN_MSB_AT_BIT19) || \ - ((type) == AUPDM_FIFO_AILGN_MSB_AT_BIT15)) - -/** @defgroup AUPDM_FIFO_DQR_THRESHOLD_MODE - * @{ - */ -#define IS_AUPDM_FIFO_DQR_THRESHOLD_MODE(type) (((type) == AUPDM_DRQ_EQUEL_TO_IRQ) || \ - ((type) == AUPDM_DRQ_THR_AS_4_TX_8_RX) || \ - ((type) == AUPDM_DRQ_THR_AS_8_TX_16_RX) || \ - ((type) == AUPDM_DRQ_THR_AS_16_TX_32_RX)) - -/** @defgroup AUPDM_INT_TYPE - * @{ - */ -#define IS_AUPDM_INT_TYPE(type) (((type) == AUPDM_INT_RX_FIFO_THR) || \ - ((type) == AUPDM_INT_RX_FIFO_OVERRUN) || \ - ((type) == AUPDM_INT_RX_FIFO_UNDERRUN) || \ - ((type) == AUPDM_INT_NUM_ALL)) - -/*@} end of group AUDIOPDM_Public_Constants */ - -/** @defgroup AUDIOPDM_Public_Macros - * @{ - */ -#define AUDIO_PRIVATE_BIT_POS(n) (0x01 << n) -#define ADC1_DATA_CHANNEL_FIFO_EN AUDIO_PRIVATE_BIT_POS(0) -#define ADC2_DATA_CHANNEL_FIFO_EN AUDIO_PRIVATE_BIT_POS(1) -#define ADC3_DATA_CHANNEL_FIFO_EN AUDIO_PRIVATE_BIT_POS(2) - -/*@} end of group AUDIOPDM_Public_Macros */ - -/** @defgroup AUDIOPDM_Public_Functions - * @{ - */ -void Aupdm_IntMask(Aupdm_INT_Type intType, BL_Mask_Type intMask); -BL_Sts_Type Aupdm_GetIntStatus(Aupdm_INT_Type intType); -void Aupdm_IntClear(Aupdm_INT_Type intType); -void Aupdm_Clock_Init(Aupdm_Clock_CFG_Type *cfg); -void Aupdm_PDM_Channel_Sel(Aupdm_PDM_ID_Type id, Aupdm_PDM_Source_Type pdmSel); -void Aupdm_PDM_Enable(Aupdm_PDM_ID_Type id); -BL_Err_Type Aupdm_Int_Callback_Install(Aupdm_INT_Type intType, intCallback_Type *cbFun); -void Aupdm_RxFifoClear(void); -uint32_t Aupdm_GetRxFifoCount(void); -uint32_t Aupdm_ReadRxFifo(void); -void Aupdm_RxFifoConfig(Aupdm_FifoCfg_Type *cfg); -void Aupdm_RxFifoEnable(uint8_t ch); -void Aupdm_RxFifoDisable(uint8_t ch); -BL_Err_Type Aupdm_Rx_Source_ADC_Sel(uint8_t rx_channel, Aupdm_ADC_ID_Type adc_id); -void Aupdm_ADC_Enable(Aupdm_ADC_ID_Type id); -void Aupdm_ADC_Disable(Aupdm_ADC_ID_Type id); -void Aupdm_Set_ADC_Scaling_Value(Aupdm_ADC_ID_Type id, uint8_t scalingVal); -void Aupdm_Set_Fir_Mode(Aupdm_ADC_ID_Type id, uint8_t enable); -void Aupdm_Set_HPF_Parameter(Aupdm_ADC_ID_Type id, uint8_t k1_enable, uint8_t k1, uint8_t k2_enable, uint8_t k2); -void Aupdm_ADC_PDM_Inv_Swap(Aupdm_ADC_ID_Type id, uint8_t swap); -void Audio_ADC_Set_PDM_Value(uint8_t pdm_l, uint8_t pdm_h); -BL_Err_Type Aupdm_ADC_Volume_Config(Aupdm_ADC_ID_Type adc_id, uint8_t volume); -/*@} end of group AUDIOPDM_Public_Functions */ - -/*@} end of group AUDIOPDM */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_AUDIOPDM_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_cam.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_cam.h deleted file mode 100644 index 211c393750..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_cam.h +++ /dev/null @@ -1,349 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_cam.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_CAM_H__ -#define __BL808_CAM_H__ - -#include "cam_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup CAM - * @{ - */ - -/** @defgroup CAM_Public_Types - * @{ - */ - -/** - * @brief CAM port type definition - */ -typedef enum { - CAM0_ID, /*!< Camera0 port define */ - CAM1_ID, /*!< Camera1 port define */ - CAM2_ID, /*!< Camera2 port define */ - CAM3_ID, /*!< Camera3 port define */ - CAM4_ID, /*!< Camera4 port define */ - CAM5_ID, /*!< Camera5 port define */ - CAM6_ID, /*!< Camera6 port define */ - CAM7_ID, /*!< Camera7 port define */ - CAM_ID_MAX, /*!< Camera max ID define */ -} CAM_ID_Type; - -/** - * @brief CAM AHB burst type definition - */ -typedef enum { - CAM_BURST_TYPE_SINGLE, /*!< Camera AHB burst type:single */ - CAM_BURST_TYPE_INCR4, /*!< Camera AHB burst type:incrementing 4 */ - CAM_BURST_TYPE_INCR8, /*!< Camera AHB burst type:incrementing 8 */ - CAM_BURST_TYPE_INCR16, /*!< Camera AHB burst type:incrementing 16 */ - CAM_BURST_TYPE_INCR32 = 5, /*!< Camera AHB burst type:incrementing 32 */ - CAM_BURST_TYPE_INCR64, /*!< Camera AHB burst type:incrementing 64 */ -} CAM_Burst_Type; - -/** - * @brief CAM software mode type definition - */ -typedef enum { - CAM_SW_MODE_AUTO, /*!< CAM auto mode with mjpeg */ - CAM_SW_MODE_MANUAL, /*!< CAM manual mode(software mode) */ -} CAM_SW_Mode_Type; - -/** - * @brief CAM output drop mode type definition - */ -typedef enum { - CAM_DROP_NONE, /*!< Not drop */ - CAM_DROP_ODD_ROW_ODD_PIXEL, /*!< Dropp odd pix data in odd rows, for example:(raw data:YUYV YUYV..., processed data:YUYV YY...) */ - CAM_DROP_ODD_ROW_EVEN_PIXEL, /*!< Dropp even pix data in odd rows, for example:(raw data:UYVY UYVY..., processed data:UYVY YY...) */ - CAM_DROP_ALL_ODD_PIXEL, /*!< Dropp odd pix data, for example:(raw data:YUYV YUYV..., processed data:YY YY...) */ - CAM_DROP_ALL_EVEN_PIXEL, /*!< Dropp even pix data, for example:(raw data:UYVY UYVY..., processed data:YY YY...) */ -} CAM_Output_Drop_Mode_Type; - -/** - * @brief CAM input pix data width type definition - */ -typedef enum { - CAM_PIX_DATA_BIT_16, /*!< CAM pix data is 16-bit */ - CAM_PIX_DATA_BIT_24, /*!< CAM pix data is 24-bit */ - CAM_PIX_DATA_BIT_24TO16, /*!< CAM pix data is 24-comp-16-bit */ - CAM_PIX_DATA_BIT_24TO32, /*!< CAM pix data is 24-exp-32-bit */ - CAM_PIX_DATA_BIT_8, /*!< CAM pix data is 8-bit */ -} CAM_Input_Pix_Width_Type; - -/** - * @brief CAM 8-bit mode byte select type definition - */ -typedef enum { - CAM_8_BIT_SELECT_LOWER, /*!< CAM select the lower byte of pix data */ - CAM_8_BIT_SELECT_UPPER, /*!< CAM select the upper byte of pix data */ -} CAM_8_Bit_Byte_Type; - -/** - * @brief CAM pix data 24-comp-16-bit mode RGB order type definition - */ -typedef enum { - CAM_16_BIT_RGB, /*!< CAM 16-bit pix data is RGB */ - CAM_16_BIT_GRB, /*!< CAM 16-bit pix data is GRB */ - CAM_16_BIT_RBG, /*!< CAM 16-bit pix data is RBG */ - CAM_16_BIT_GBR, /*!< CAM 16-bit pix data is GBR */ - CAM_16_BIT_BRG, /*!< CAM 16-bit pix data is BRG */ - CAM_16_BIT_BGR, /*!< CAM 16-bit pix data is BGR */ -} CAM_16_Bit_RGB_Type; - -/** - * @brief CAM line active polarity type definition - */ -typedef enum { - CAM_LINE_ACTIVE_POLARITY_LOW, /*!< CAM line active polarity low */ - CAM_LINE_ACTIVE_POLARITY_HIGH, /*!< CAM line active polarity high */ -} CAM_Line_Active_Pol; - -/** - * @brief CAM frame active polarity type definition - */ -typedef enum { - CAM_FRAME_ACTIVE_POLARITY_LOW, /*!< CAM frame active polarity low */ - CAM_FRAME_ACTIVE_POLARITY_HIGH, /*!< CAM frame active polarity high */ -} CAM_Frame_Active_Pol; - -/** - * @brief CAM sensor mode type definition - */ -typedef enum { - CAM_SENSOR_MODE_V_AND_H, /*!< CAM sensor type v and h */ - CAM_SENSOR_MODE_V_OR_H, /*!< CAM sensor type v or h */ - CAM_SENSOR_MODE_V, /*!< CAM sensor type v */ - CAM_SENSOR_MODE_H, /*!< CAM sensor type h */ -} CAM_Sensor_Mode_Type; - -/** - * @brief CAM interrupt type definition - */ -typedef enum { - CAM_INT_NORMAL, /*!< Normal write interrupt */ - CAM_INT_MEMORY_OVERWRITE, /*!< Memory overwrite interrupt */ - CAM_INT_FRAME_OVERWRITE, /*!< Frame overwrite interrupt */ - CAM_INT_FIFO_OVERWRITE, /*!< Fifo overwrite interrupt */ - CAM_INT_VSYNC_CNT_ERROR, /*!< Vsync valid line count non-match interrupt */ - CAM_INT_HSYNC_CNT_ERROR, /*!< Hsync valid pixel count non-match interrupt */ - CAM_INT_ALL, /*!< All of interrupt */ -} CAM_INT_Type; - -/** - * @brief CAM configuration strcut definition - */ -typedef struct -{ - CAM_SW_Mode_Type swMode; /*!< Software mode */ - uint8_t swIntCnt; /*!< Set frame count to issue interrupt at software mode */ - CAM_Input_Pix_Width_Type pixWidth; /*!< Input pix data width */ - CAM_Output_Drop_Mode_Type dropMode; /*!< Drop mode */ - CAM_Frame_Active_Pol framePol; /*!< Frame polarity */ - CAM_Line_Active_Pol linePol; /*!< Line polarity */ - CAM_Burst_Type burstType; /*!< AHB burst type */ - CAM_Sensor_Mode_Type camSensorMode; /*!< CAM sensor mode */ - uint8_t waitCount; /*!< Cycles in FSM wait mode, default value:0x40 */ - uint32_t memStart; /*!< Data start address */ - uint32_t memSize; /*!< Memory size in burst */ - uint32_t frameSize; /*!< Frame byte size */ -} CAM_CFG_Type; - -/** - * @brief CAM frame information strcut definition - */ -typedef struct -{ - uint8_t validFrames; /*!< Valid frames */ - uint16_t curFrameId; /*!< Current frame id */ - uint32_t curFrameAddr; /*!< Current frame address */ - uint32_t curFrameBytes; /*!< Current frame bytes */ - uint32_t status; /*!< CAM module status */ -} CAM_Frame_Info; - -/*@} end of group CAM_Public_Types */ - -/** @defgroup CAM_Public_Constants - * @{ - */ - -/** @defgroup CAM_ID_TYPE - * @{ - */ -#define IS_CAM_ID_TYPE(type) (((type) == CAM0_ID) || \ - ((type) == CAM1_ID) || \ - ((type) == CAM2_ID) || \ - ((type) == CAM3_ID) || \ - ((type) == CAM4_ID) || \ - ((type) == CAM5_ID) || \ - ((type) == CAM6_ID) || \ - ((type) == CAM7_ID) || \ - ((type) == CAM_ID_MAX)) - -/** @defgroup CAM_BURST_TYPE - * @{ - */ -#define IS_CAM_BURST_TYPE(type) (((type) == CAM_BURST_TYPE_SINGLE) || \ - ((type) == CAM_BURST_TYPE_INCR4) || \ - ((type) == CAM_BURST_TYPE_INCR8) || \ - ((type) == CAM_BURST_TYPE_INCR16) || \ - ((type) == CAM_BURST_TYPE_INCR32) || \ - ((type) == CAM_BURST_TYPE_INCR64)) - -/** @defgroup CAM_SW_MODE_TYPE - * @{ - */ -#define IS_CAM_SW_MODE_TYPE(type) (((type) == CAM_SW_MODE_AUTO) || \ - ((type) == CAM_SW_MODE_MANUAL)) - -/** @defgroup CAM_OUTPUT_DROP_MODE_TYPE - * @{ - */ -#define IS_CAM_OUTPUT_DROP_MODE_TYPE(type) (((type) == CAM_DROP_NONE) || \ - ((type) == CAM_DROP_ODD_ROW_ODD_PIXEL) || \ - ((type) == CAM_DROP_ODD_ROW_EVEN_PIXEL) || \ - ((type) == CAM_DROP_ALL_ODD_PIXEL) || \ - ((type) == CAM_DROP_ALL_EVEN_PIXEL)) - -/** @defgroup CAM_INPUT_PIX_WIDTH_TYPE - * @{ - */ -#define IS_CAM_INPUT_PIX_WIDTH_TYPE(type) (((type) == CAM_PIX_DATA_BIT_16) || \ - ((type) == CAM_PIX_DATA_BIT_24) || \ - ((type) == CAM_PIX_DATA_BIT_24TO16) || \ - ((type) == CAM_PIX_DATA_BIT_24TO32) || \ - ((type) == CAM_PIX_DATA_BIT_8)) - -/** @defgroup CAM_8_BIT_BYTE_TYPE - * @{ - */ -#define IS_CAM_8_BIT_BYTE_TYPE(type) (((type) == CAM_8_BIT_SELECT_LOWER) || \ - ((type) == CAM_8_BIT_SELECT_UPPER)) - -/** @defgroup CAM_16_BIT_RGB_TYPE - * @{ - */ -#define IS_CAM_16_BIT_RGB_TYPE(type) (((type) == CAM_16_BIT_RGB) || \ - ((type) == CAM_16_BIT_GRB) || \ - ((type) == CAM_16_BIT_RBG) || \ - ((type) == CAM_16_BIT_GBR) || \ - ((type) == CAM_16_BIT_BRG) || \ - ((type) == CAM_16_BIT_BGR)) - -/** @defgroup CAM_LINE_ACTIVE_POL - * @{ - */ -#define IS_CAM_LINE_ACTIVE_POL(type) (((type) == CAM_LINE_ACTIVE_POLARITY_LOW) || \ - ((type) == CAM_LINE_ACTIVE_POLARITY_HIGH)) - -/** @defgroup CAM_FRAME_ACTIVE_POL - * @{ - */ -#define IS_CAM_FRAME_ACTIVE_POL(type) (((type) == CAM_FRAME_ACTIVE_POLARITY_LOW) || \ - ((type) == CAM_FRAME_ACTIVE_POLARITY_HIGH)) - -/** @defgroup CAM_SENSOR_MODE_TYPE - * @{ - */ -#define IS_CAM_SENSOR_MODE_TYPE(type) (((type) == CAM_SENSOR_MODE_V_AND_H) || \ - ((type) == CAM_SENSOR_MODE_V_OR_H) || \ - ((type) == CAM_SENSOR_MODE_V) || \ - ((type) == CAM_SENSOR_MODE_H)) - -/** @defgroup CAM_INT_TYPE - * @{ - */ -#define IS_CAM_INT_TYPE(type) (((type) == CAM_INT_NORMAL) || \ - ((type) == CAM_INT_MEMORY_OVERWRITE) || \ - ((type) == CAM_INT_FRAME_OVERWRITE) || \ - ((type) == CAM_INT_FIFO_OVERWRITE) || \ - ((type) == CAM_INT_VSYNC_CNT_ERROR) || \ - ((type) == CAM_INT_HSYNC_CNT_ERROR) || \ - ((type) == CAM_INT_ALL)) - -/*@} end of group CAM_Public_Constants */ - -/** @defgroup CAM_Public_Macros - * @{ - */ - -/*@} end of group CAM_Public_Macros */ - -/** @defgroup CAM_Public_Functions - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -void CAM0_IRQHandler(void); -void CAM1_IRQHandler(void); -void CAM2_IRQHandler(void); -void CAM3_IRQHandler(void); -void CAM4_IRQHandler(void); -void CAM5_IRQHandler(void); -void CAM6_IRQHandler(void); -void CAM7_IRQHandler(void); -#endif -void CAM_Init(CAM_ID_Type camId, CAM_CFG_Type *cfg); -void CAM_Deinit(CAM_ID_Type camId); -void CAM_Enable(CAM_ID_Type camId); -void CAM_Disable(CAM_ID_Type camId); -void CAM_Clock_Gate(CAM_ID_Type camId, BL_Fun_Type enable); -void CAM_Hsync_Crop(CAM_ID_Type camId, uint16_t start, uint16_t end); -void CAM_Vsync_Crop(CAM_ID_Type camId, uint16_t start, uint16_t end); -void CAM_Set_Hsync_Total_Count(CAM_ID_Type camId, uint16_t count); -void CAM_Set_Vsync_Total_Count(CAM_ID_Type camId, uint16_t count); -void CAM_Get_Frame_Info(CAM_ID_Type camId, CAM_Frame_Info *info); -uint8_t CAM_Get_Frame_Count(CAM_ID_Type camId); -void CAM_Pop_Frame(CAM_ID_Type camId); -void CAM_IntMask(CAM_ID_Type camId, CAM_INT_Type intType, BL_Mask_Type intMask); -void CAM_IntClr(CAM_ID_Type camId, CAM_INT_Type intType); -void CAM_Int_Callback_Install(CAM_ID_Type camId, CAM_INT_Type intType, intCallback_Type *cbFun); -void CAM_8_Bit_Byte_Select(CAM_ID_Type camId, CAM_8_Bit_Byte_Type byteType); -void CAM_16_Bit_RGB_order(CAM_ID_Type camId, CAM_16_Bit_RGB_Type rgbType); -void CAM_32_Bit_Alpha_Set(CAM_ID_Type camId, uint8_t alpha); -void CAM_Set_Frame_Valid_Period(CAM_ID_Type camId, uint8_t period, uint32_t validBit); -void CAM_HW_Cover_First_Frame_Everytime(CAM_ID_Type camId, BL_Fun_Type enable); - -/*@} end of group CAM_Public_Functions */ - -/*@} end of group CAM */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_CAM_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_can.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_can.h deleted file mode 100644 index 4a5bf5b3f0..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_can.h +++ /dev/null @@ -1,244 +0,0 @@ -#ifndef __BL808_CAN_H__ -#define __BL808_CAN_H__ - -#include "can_reg.h" -#include "bl808_common.h" - -#define CAN_BASE CAN_FD_BASE -#define CAN_TIMEOUT_MAX (32 * 1000) - -typedef enum { - CAN_FRAME_FORMAT_STANDARD = 0, - CAN_FRAME_FORMAT_EXTENDED, -}CAN_FRAME_FORMAT_Type; - -typedef enum { - CAN_FRAME_TYPE_DATA = 0, - CAN_FRAME_TYPE_REMOTE, -}CAN_FRAME_Type; - -typedef enum { - CAN_MODE_TYPE_RESET = 0, - CAN_MODE_TYPE_LISTEN_ONLY, - CAN_MODE_TYPE_SELF_TSET, - CAN_MODE_TYPE_ACCEPTANCE_FILTER, -}CAN_MODE_Type; - -typedef enum -{ - CAN_MODE_VALUE_NORMAL = 0, - CAN_MODE_VALUE_RESET = 1, - CAN_MODE_VALUE_LISTEN_ONLY = 1, - CAN_MODE_VALUE_SELF_TSET = 1, - CAN_MODE_VALUE_ACCEPTANCE_FILTER_DUAL = 0, - CAN_MODE_VALUE_ACCEPTANCE_FILTER_SINGLE = 1, -} CAN_MODE_VALUE_Type; - -typedef enum { - CAN_INT_RECEIVE = 0, - CAN_INT_TRANSMIT, - CAN_INT_ERROR_WARNING, - CAN_INT_OVERRUN, - CAN_INT_RESERVED, - CAN_INT_PASSIVE = 5, - CAN_INT_ARBITRATION_LOST, - CAN_INT_BUS_ERROR, - CAN_INT_ALL, -}CAN_INT_Type; - -typedef enum { - CAN_STATUS_RECEIVE_BUFFER = 0, - CAN_STATUS_DATA_OVERRUN, - CAN_STATUS_TRANSMIT_BUFFER, - CAN_STATUS_TRANSMISSION_COMPLETE, - CAN_STATUS_RECEIVE, - CAN_STATUS_TRANSMIT, - CAN_STATUS_ERROR, - CAN_STATUS_BUS, -}CAN_STATUS_Type; - -typedef enum { - CAN_STATUS_RECEIVE_BUFFER_EMPTY = 0, - CAN_STATUS_RECEIVE_BUFFER_NONEMPTY = 1, - CAN_STATUS_DATA_OVERRUN_NULL = 0, - CAN_STATUS_DATA_OVERRUN_EXIST = 1, - CAN_STATUS_TRANSMIT_BUFFER_LOCKED = 0, - CAN_STATUS_TRANSMIT_BUFFER_ACCESSIBLE = 1, - CAN_STATUS_TRANSMISSION_COMPLETE_NOT = 0, - CAN_STATUS_TRANSMISSION_COMPLETE_YES = 1, - CAN_STATUS_RECEIVE_IDLE = 0, - CAN_STATUS_RECEIVE_ONGOING = 1, - CAN_STATUS_TRANSMIT_IDLE = 0, - CAN_STATUS_TRANSMIT_ONGOING = 1, - CAN_STATUS_ERROR_NULL = 0, - CAN_STATUS_ERROR_EXIST = 1, - CAN_STATUS_BUS_ON = 0, - CAN_STATUS_BUS_OFF = 1, -}CAN_STATUS_VALUE_Type; - -typedef enum { - CAN_ERROR_TYPE_BIT = 0, - CAN_ERROR_TYPE_FORM, - CAN_ERROR_TYPE_STUFF, - CAN_ERROR_TYPE_OTHERS, -}CAN_ERROR_CODE_Type; - -typedef enum { - CAN_ERROR_DIRECTION_TX = 0, - CAN_ERROR_DIRECTION_RX, -}CAN_ERROR_DIRECTION_Type; - -typedef enum { - CAN_ERROR_LOCATION_ID28_TO_ID21 = 2, - CAN_ERROR_LOCATION_START_OF_FRAME = 3, - CAN_ERROR_LOCATION_BIT_SRTR = 4, - CAN_ERROR_LOCATION_BIT_IDE = 5, - CAN_ERROR_LOCATION_ID20_TO_ID18 = 6, - CAN_ERROR_LOCATION_ID17_TO_ID13 = 7, - CAN_ERROR_LOCATION_CRC_SEQUENCE = 8, - CAN_ERROR_LOCATION_BIT_RESERVED_0 = 9, - CAN_ERROR_LOCATION_DATA_FIELD = 10, - CAN_ERROR_LOCATION_DATA_LENGTH_CODE = 11, - CAN_ERROR_LOCATION_BIT_RTR = 12, - CAN_ERROR_LOCATION_BIT_RESERVED_1 = 13, - CAN_ERROR_LOCATION_ID4_TO_ID0 = 14, - CAN_ERROR_LOCATION_ID12_TO_ID15 = 15, - CAN_ERROR_LOCATION_ACTIVE_ERROR_FLAG = 17, - CAN_ERROR_LOCATION_INTERMISSION = 18, - CAN_ERROR_LOCATION_BIT_TOLERATE_DOMINANT = 19, - CAN_ERROR_LOCATION_PASSIVE_ERROR_FLAG = 22, - CAN_ERROR_LOCATION_ERROR_DELIMITER = 23, - CAN_ERROR_LOCATION_CRC_DELIMITER = 24, - CAN_ERROR_LOCATION_ACK_SLOT = 25, - CAN_ERROR_LOCATION_END_OF_FRAME = 26, - CAN_ERROR_LOCATION_ACK_DELIMITER = 27, - CAN_ERROR_LOCATION_OVERLOAD_FLAG = 28, -} CAN_ERROR_LOCATION_Type; - -typedef enum { - CAN_FILTER_REGISTER_ACR0 = 0, - CAN_FILTER_REGISTER_ACR1, - CAN_FILTER_REGISTER_ACR2, - CAN_FILTER_REGISTER_ACR3, - CAN_FILTER_REGISTER_AMR0, - CAN_FILTER_REGISTER_AMR1, - CAN_FILTER_REGISTER_AMR2, - CAN_FILTER_REGISTER_AMR3, -} CAN_FILTER_REGISTER_Type; - -typedef struct { - CAN_ERROR_CODE_Type code; - CAN_ERROR_DIRECTION_Type dir; - CAN_ERROR_LOCATION_Type location; -} CAN_ERROR_Type; - -typedef struct { - CAN_FRAME_FORMAT_Type formatType; - CAN_MODE_VALUE_Type filterMode; - CAN_FRAME_Type matchRtr1; - CAN_FRAME_Type matchRtr2; - uint8_t matchData1; - uint8_t matchData2; - uint32_t matchId1; - uint32_t matchId2; - BL_Mask_Type maskRtr1; - BL_Mask_Type maskRtr2; - uint8_t maskData1; - uint8_t maskData2; - uint32_t maskId1; - uint32_t maskId2; -}CAN_FILTER_CFG_Type; - -typedef struct { - CAN_FRAME_Type frameType; - CAN_FRAME_FORMAT_Type frameFormat; - uint8_t dataLen; - uint8_t *dataAddr; - uint32_t id; - uint32_t timeout; -}CAN_CFG_Type; - -#define IS_CAN_FRAME_FORMAT_TYPE(type) (((type) == CAN_FRAME_FORMAT_STANDARD) || \ - ((type) == CAN_FRAME_FORMAT_EXTENDED)) - -#define IS_CAN_FRAME_TYPE(type) (((type) == CAN_FRAME_TYPE_DATA) || \ - ((type) == CAN_FRAME_TYPE_REMOTE)) - -#define IS_CAN_MODE_TYPE(type) (((type) == CAN_MODE_TYPE_RESET) || \ - ((type) == CAN_MODE_TYPE_LISTEN_ONLY) || \ - ((type) == CAN_MODE_TYPE_SELF_TSET) || \ - ((type) == CAN_MODE_TYPE_ACCEPTANCE_FILTER) || \ - -#define IS_CAN_MODE_VALUE_TYPE(type) (((type) == CAN_MODE_VALUE_NORMAL) || \ - ((type) == CAN_MODE_VALUE_RESET) || \ - ((type) == CAN_MODE_VALUE_LISTEN_ONLY) || \ - ((type) == CAN_MODE_VALUE_SELF_TSET) || \ - ((type) == CAN_MODE_VALUE_ACCEPTANCE_FILTER_DUAL) || \ - ((type) == CAN_MODE_VALUE_ACCEPTANCE_FILTER_SINGLE) || \ - -#define IS_CAN_INT_TYPE(type) (((type) == CAN_INT_RECEIVE) || \ - ((type) == CAN_INT_TRANSMIT) || \ - ((type) == CAN_INT_ERROR_WARNING) || \ - ((type) == CAN_INT_OVERRUN) || \ - ((type) == CAN_INT_PASSIVE) || \ - ((type) == CAN_INT_ARBITRATION_LOST) || \ - ((type) == CAN_INT_BUSERROR) || \ - ((type) == CAN_INT_ALL)) - -#define IS_CAN_STATUS_TYPE(type) (((type) == CAN_STATUS_RECEIVE_BUFFER) || \ - ((type) == CAN_STATUS_DATA_OVERRUN) || \ - ((type) == CAN_STATUS_TRANSMIT_BUFFER) || \ - ((type) == CAN_STATUS_TRANSMISSION_COMPLETE) || \ - ((type) == CAN_STATUS_RECEIVE) || \ - ((type) == CAN_STATUS_TRANSMIT) || \ - ((type) == CAN_STATUS_ERROR) || \ - ((type) == CAN_STATUS_BUS)) - -#define IS_CAN_STATUS_VALUE_TYPE(type) (((type) == CAN_STATUS_VALUE_RECEIVE_BUFFER_EMPTY || \ - ((type) == CAN_STATUS_VALUE_RECEIVE_BUFFER_NONEMPTY || \ - ((type) == CAN_STATUS_VALUE_DATA_OVERRUN_NULL || \ - ((type) == CAN_STATUS_VALUE_DATA_OVERRUN_EXIST || \ - ((type) == CAN_STATUS_VALUE_TRANSMIT_BUFFER_LOCKED || \ - ((type) == CAN_STATUS_VALUE_TRANSMIT_BUFFER_ACCESSIBLE || \ - ((type) == CAN_STATUS_VALUE_TRANSMISSION_COMPLETE_NOT || \ - ((type) == CAN_STATUS_VALUE_TRANSMISSION_COMPLETE_YES || \ - ((type) == CAN_STATUS_VALUE_RECEIVE_IDLE || \ - ((type) == CAN_STATUS_VALUE_RECEIVE_ONGOING || \ - ((type) == CAN_STATUS_VALUE_TRANSMIT_IDLE || \ - ((type) == CAN_STATUS_VALUE_TRANSMIT_ONGOING || \ - ((type) == CAN_STATUS_VALUE_ERROR_NULL || \ - ((type) == CAN_STATUS_VALUE_ERROR_EXIST || \ - ((type) == CAN_STATUS_VALUE_BUS_ON || \ - ((type) == CAN_STATUS_VALUE_BUS_OFF)) - -void CAN_Init(void); -void CAN_Mode_Set(CAN_MODE_Type type, CAN_MODE_VALUE_Type value); -CAN_MODE_VALUE_Type CAN_Mode_Get(CAN_MODE_Type type); -void CAN_Int_Enable(CAN_INT_Type intType, BL_Fun_Type enable); -void CAN_Cmd_Request_Transmit(void); -void CAN_Cmd_Abort_Transmit(void); -void CAN_Cmd_Release_Recv_Buff(void); -void CAN_Cmd_Clear_Data_Overrun(void); -void CAN_Cmd_Request_Self_Reception(void); -CAN_STATUS_VALUE_Type CAN_Status_Get(CAN_STATUS_Type type); -uint8_t CAN_Arbitration_Lost_Position_Get(void); -void CAN_Error_Get(CAN_ERROR_Type *const code); -BL_Err_Type CAN_Error_Warning_Limit_Set(uint8_t limit); -uint8_t CAN_Error_Warning_Limit_Get(void); -uint8_t CAN_Error_Rx_Counter_Get(void); -uint8_t CAN_Error_Tx_Counter_Get(void); -BL_Err_Type CAN_Transmit(const CAN_CFG_Type *cfg); -BL_Err_Type CAN_Receive(CAN_CFG_Type *cfg); -uint8_t CAN_Receive_Buff_Frame_Count_Get(void); -BL_Err_Type CAN_Clock_Div_Set(uint8_t div); -uint8_t CAN_Clock_Div_Get(void); -BL_Err_Type CAN_Synchronization_Jump_Width_Set(uint8_t width); -uint8_t CAN_Synchronization_Jump_Width_Get(void); -BL_Err_Type CAN_Sample_Parameter_Set(uint8_t num, uint8_t head, uint8_t tail); -void CAN_Sample_Parameter_Get(uint8_t *num, uint8_t *head, uint8_t *tail); -void CAN_Filter_Set(const CAN_FILTER_CFG_Type *cfg); -void CAN_Filter_Register_Set(CAN_FILTER_REGISTER_Type reg, uint8_t value); -void CAN_Filter_Registers_Set(uint8_t *valueArr); - -BL_Err_Type CAN_Int_Callback_Install(CAN_INT_Type intType, intCallback_Type *cbFun); -#endif /* __BL606p_CAN_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_common.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_common.h deleted file mode 100644 index dc0d456910..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_common.h +++ /dev/null @@ -1,56 +0,0 @@ -#ifndef __BL808_COMMON_H__ -#define __BL808_COMMON_H__ - -#include "bl808.h" -#include "misc.h" - -#ifndef __set_MSP -#define __set_MSP(msp) __ASM volatile("add sp, x0, %0" ::"r"(msp)) -#endif - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup COMMON - * @{ - */ - -/** @defgroup COMMON_Public_Types - * @{ - */ - -/*@} end of group COMMON_Public_Types */ - -/** @defgroup COMMON_Public_Constants - * @{ - */ - -/** @defgroup DRIVER_INT_PERIPH - * @{ - */ -#define IS_INT_PERIPH(INT_PERIPH) ((INT_PERIPH) < IRQn_LAST) - -/*@} end of group DRIVER_INT_PERIPH */ - -/** @defgroup DRIVER_INT_MASK - * @{ - */ -#define IS_BL_MASK_TYPE(type) (((type) == MASK) || ((type) == UNMASK)) - -/*@} end of group COMMON_Public_Constants */ - -/** @defgroup DRIVER_Public_FunctionDeclaration - * @brief DRIVER functions declaration - * @{ - */ - -void ASM_Delay_Us(uint32_t core, uint32_t cnt, uint32_t loopT); -void arch_delay_us(uint32_t cnt); -void arch_delay_ms(uint32_t cnt); - -void C906_All_Int_Enable(void); -void C906_All_Int_Disable(void); -/*@} end of group DRIVER_COMMON */ - -#endif /* __BL808_COMMON_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dac.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dac.h deleted file mode 100644 index 980930debe..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dac.h +++ /dev/null @@ -1,290 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_dac.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_DAC_H__ -#define __BL808_DAC_H__ - -#include "aon_reg.h" -#include "glb_reg.h" -#include "gpip_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup DAC - * @{ - */ - -/** @defgroup DAC_Public_Types - * @{ - */ - -/** - * @brief DAC reference voltage definition - */ -typedef enum { - GLB_DAC_REF_SEL_INTERNAL, /*!< DAC reference select internal */ - GLB_DAC_REF_SEL_EXTERNAL, /*!< DAC reference select external */ -} GLB_DAC_Ref_Sel_Type; - -/** - * @brief DAC reference voltage definition - */ -typedef enum { - GLB_DAC_Output_Volt_0P2_1, /*!< DAC output voltage is 0.2-1V */ - GLB_DAC_Output_Volt_0P225_1P425, /*!< DAC output voltage is 0.225-1.425V */ - GLB_DAC_Output_Volt_RESEVED, /*!< DAC output voltage is 0.225-1.425V */ - GLB_DAC_Output_Volt_0P2_1P8, /*!< DAC output voltage is 0.2-1.8V */ -} GLB_DAC_Output_Volt_Range_Type; - -/** - * @brief DAC channel type definition - */ -typedef enum { - GLB_DAC_CHAN0, /*!< DAC channel 0 */ - GLB_DAC_CHAN1, /*!< DAC channel 1 */ - GLB_DAC_CHAN2, /*!< DAC channel 2 */ - GLB_DAC_CHAN3, /*!< DAC channel 3 */ - GLB_DAC_CHAN4, /*!< DAC channel 4 */ - GLB_DAC_CHAN5, /*!< DAC channel 5 */ - GLB_DAC_CHAN6, /*!< DAC channel 6 */ - GLB_DAC_CHAN7, /*!< DAC channel 7 */ - GLB_DAC_CHAN_ALL, /*!< DAC channel all */ -} GLB_DAC_Chan_Type; - -/** - * @brief DAC channel configuration structure type definition - */ -typedef struct -{ - BL_Fun_Type chanEn; /*!< Enable this channel or not */ - BL_Fun_Type outputEn; /*!< Output this channel result to PAD */ - GLB_DAC_Chan_Type outMux; /*!< DAC output mux,NOT implement yet,DAC use fixed GPIO9 and GPIO10 */ - GLB_DAC_Output_Volt_Range_Type outRange; /*!< DAC output voltage range */ -} GLB_DAC_Chan_Cfg_Type; - -/** - * @brief DAC configuration structure type definition - */ -typedef struct -{ - GLB_DAC_Ref_Sel_Type refSel; /*!< DAC reference voltage select */ - BL_Fun_Type resetChanA; /*!< Reset DAC channel A */ - BL_Fun_Type resetChanB; /*!< Reset DAC channel B */ -} GLB_DAC_Cfg_Type; - -/** - * @brief DAC channel B source selection type definition - */ -typedef enum { - GPIP_DAC_ChanB_SRC_REG, /*!< select Reg as source of DAC channel B */ - GPIP_DAC_ChanB_SRC_DMA, /*!< select DMA as source of DAC channel B */ - GPIP_DAC_ChanB_SRC_DMA_WITH_FILTER, /*!< select DMA with Filter as source of DAC channel B */ - GPIP_DAC_ChanB_SRC_SIN_GEN, /*!< select Sin Gen as source of DAC channel B */ - GPIP_DAC_ChanB_SRC_A, /*!< select channel A as source of DAC channel B */ - GPIP_DAC_ChanB_SRC_INVERSE_A, /*!< select inverse of channel A as source of DAC channel B */ -} GPIP_DAC_ChanB_SRC_Type; - -/** - * @brief DAC channel A source selection type definition - */ -typedef enum { - GPIP_DAC_ChanA_SRC_REG, /*!< select Reg as source of DAC channel A */ - GPIP_DAC_ChanA_SRC_DMA, /*!< select DMA as source of DAC channel A */ - GPIP_DAC_ChanA_SRC_DMA_WITH_FILTER, /*!< select DMA with Filter as source of DAC channel A */ - GPIP_DAC_ChanA_SRC_SIN_GEN, /*!< select Sin Gen as source of DAC channel A */ -} GPIP_DAC_ChanA_SRC_Type; - -/** - * @brief DAC clock divider type definition - */ -typedef enum { - DAC_CLK_DIV_16, /*!< ADC clock:on 32M clock is 2M */ - DAC_CLK_DIV_32, /*!< ADC clock:on 32M clock is 1M */ - DAC_CLK_DIV_RESERVE, /*!< reserved */ - DAC_CLK_DIV_64, /*!< ADC clock:on 32M clock is 0.5M */ - DAC_CLK_DIV_1, /*!< ADC clock:on 32M clock is 32M */ -} DAC_CLK_Type; - -/** - * @brief DAC DMA TX format selection type definition - */ -typedef enum { - GPIP_DAC_DMA_FORMAT_0, /*!< {A0},{A1},{A2},... */ - GPIP_DAC_DMA_FORMAT_1, /*!< {B0,A0},{B1,A1},{B2,A2},... */ - GPIP_DAC_DMA_FORMAT_2, /*!< {A1,A0},{A3,A2},{A5,A4},... */ -} GPIP_DAC_DMA_TX_FORMAT_Type; - -/** - * @brief AON and GPIP DAC configuration structure type definition - */ -typedef struct -{ - GLB_DAC_Ref_Sel_Type refSel; /*!< DAC reference voltage select */ - BL_Fun_Type resetChanA; /*!< Reset DAC channel A */ - BL_Fun_Type resetChanB; /*!< Reset DAC channel B */ - DAC_CLK_Type div; /*!< DAC clock div */ - BL_Fun_Type dmaEn; /*!< DAC DMA transfer enable */ - GPIP_DAC_DMA_TX_FORMAT_Type dmaFmt; /*!< DAC DMA TX format selection */ -} GLB_GPIP_DAC_Cfg_Type; - -/** - * @brief AON and GPIP DAC channel A configuration structure type definition - */ -typedef struct -{ - BL_Fun_Type chanCovtEn; /*!< Enable this channel conversion or not */ - BL_Fun_Type outputEn; /*!< Output this channel result to PAD */ - BL_Fun_Type chanEn; /*!< Enable this channel or not */ - GPIP_DAC_ChanA_SRC_Type src; /*!< DAC channel A source */ -} GLB_GPIP_DAC_ChanA_Cfg_Type; - -/** - * @brief AON and GPIP DAC channel B configuration structure type definition - */ -typedef struct -{ - BL_Fun_Type chanCovtEn; /*!< Enable this channel conversion or not */ - BL_Fun_Type outputEn; /*!< Output this channel result to PAD */ - BL_Fun_Type chanEn; /*!< Enable this channel or not */ - GPIP_DAC_ChanB_SRC_Type src; /*!< DAC channel B source */ -} GLB_GPIP_DAC_ChanB_Cfg_Type; - -/*@} end of group DAC_Public_Types */ - -/** @defgroup DAC_Public_Constants - * @{ - */ - -/** @defgroup GLB_DAC_REF_SEL_TYPE - * @{ - */ -#define IS_GLB_DAC_REF_SEL_TYPE(type) (((type) == GLB_DAC_REF_SEL_INTERNAL) || \ - ((type) == GLB_DAC_REF_SEL_EXTERNAL)) - -/** @defgroup GLB_DAC_OUTPUT_VOLT_RANGE_TYPE - * @{ - */ -#define IS_GLB_DAC_OUTPUT_VOLT_RANGE_TYPE(type) (((type) == GLB_DAC_Output_Volt_0P2_1) || \ - ((type) == GLB_DAC_Output_Volt_0P225_1P425) || \ - ((type) == GLB_DAC_Output_Volt_RESEVED) || \ - ((type) == GLB_DAC_Output_Volt_0P2_1P8)) - -/** @defgroup GLB_DAC_CHAN_TYPE - * @{ - */ -#define IS_GLB_DAC_CHAN_TYPE(type) (((type) == GLB_DAC_CHAN0) || \ - ((type) == GLB_DAC_CHAN1) || \ - ((type) == GLB_DAC_CHAN2) || \ - ((type) == GLB_DAC_CHAN3) || \ - ((type) == GLB_DAC_CHAN4) || \ - ((type) == GLB_DAC_CHAN5) || \ - ((type) == GLB_DAC_CHAN6) || \ - ((type) == GLB_DAC_CHAN7) || \ - ((type) == GLB_DAC_CHAN_ALL)) - -/** @defgroup GPIP_DAC_CHANB_SRC_TYPE - * @{ - */ -#define IS_GPIP_DAC_CHANB_SRC_TYPE(type) (((type) == GPIP_DAC_ChanB_SRC_REG) || \ - ((type) == GPIP_DAC_ChanB_SRC_DMA) || \ - ((type) == GPIP_DAC_ChanB_SRC_DMA_WITH_FILTER) || \ - ((type) == GPIP_DAC_ChanB_SRC_SIN_GEN) || \ - ((type) == GPIP_DAC_ChanB_SRC_A) || \ - ((type) == GPIP_DAC_ChanB_SRC_INVERSE_A)) - -/** @defgroup GPIP_DAC_CHANA_SRC_TYPE - * @{ - */ -#define IS_GPIP_DAC_CHANA_SRC_TYPE(type) (((type) == GPIP_DAC_ChanA_SRC_REG) || \ - ((type) == GPIP_DAC_ChanA_SRC_DMA) || \ - ((type) == GPIP_DAC_ChanA_SRC_DMA_WITH_FILTER) || \ - ((type) == GPIP_DAC_ChanA_SRC_SIN_GEN)) - -/** @defgroup DAC_CLK_TYPE - * @{ - */ -#define IS_DAC_CLK_TYPE(type) (((type) == DAC_CLK_DIV_16) || \ - ((type) == DAC_CLK_DIV_32) || \ - ((type) == DAC_CLK_DIV_RESERVE) || \ - ((type) == DAC_CLK_DIV_64) || \ - ((type) == DAC_CLK_DIV_1)) - -/** @defgroup GPIP_DAC_DMA_TX_FORMAT_TYPE - * @{ - */ -#define IS_GPIP_DAC_DMA_TX_FORMAT_TYPE(type) (((type) == GPIP_DAC_DMA_FORMAT_0) || \ - ((type) == GPIP_DAC_DMA_FORMAT_1) || \ - ((type) == GPIP_DAC_DMA_FORMAT_2)) - -/*@} end of group DAC_Public_Constants */ - -/** @defgroup DAC_Public_Macros - * @{ - */ - -/*@} end of group DAC_Public_Macros */ - -/** @defgroup DAC_Public_Functions - * @{ - */ -void GLB_DAC_Init(GLB_DAC_Cfg_Type *cfg); -void GLB_DAC_Set_ChanA_Config(GLB_DAC_Chan_Cfg_Type *cfg); -void GLB_DAC_Set_ChanB_Config(GLB_DAC_Chan_Cfg_Type *cfg); -void GPIP_Set_DAC_ChanB_SRC_SEL(GPIP_DAC_ChanB_SRC_Type src); -void GPIP_Set_DAC_ChanA_SRC_SEL(GPIP_DAC_ChanA_SRC_Type src); -void GPIP_DAC_ChanB_Enable(void); -void GPIP_DAC_ChanB_Disable(void); -void GPIP_DAC_ChanA_Enable(void); -void GPIP_DAC_ChanA_Disable(void); -void GPIP_Set_DAC_DMA_TX_FORMAT_SEL(GPIP_DAC_DMA_TX_FORMAT_Type fmt); -void GPIP_Set_DAC_DMA_TX_Enable(void); -void GPIP_Set_DAC_DMA_TX_Disable(void); -void GPIP_DAC_DMA_WriteData(uint32_t data); -BL_Err_Type GLB_GPIP_DAC_Init(GLB_GPIP_DAC_Cfg_Type *cfg); -void GLB_GPIP_DAC_Set_ChanA_Config(GLB_GPIP_DAC_ChanA_Cfg_Type *cfg); -void GLB_GPIP_DAC_Set_ChanB_Config(GLB_GPIP_DAC_ChanB_Cfg_Type *cfg); -void GLB_DAC_Set_ChanA_Value(uint16_t val); -void GLB_DAC_Set_ChanB_Value(uint16_t val); - -/*@} end of group DAC_Public_Functions */ - -/*@} end of group DAC */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_DAC_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dbi.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dbi.h deleted file mode 100644 index 4bbdeb4aa4..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dbi.h +++ /dev/null @@ -1,294 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_dbi.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_DBI_H__ -#define __BL808_DBI_H__ - -#include "dbi_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup DBI - * @{ - */ - -/** @defgroup DBI_Public_Types - * @{ - */ - -/** - * @brief DBI mode type definition - */ -typedef enum { - DBI_TYPE_B = 0, /*!< DBI type B */ - DBI_TYPE_C_3_WIRE, /*!< DBI type C 3 wire mode */ - DBI_TYPE_C_4_WIRE, /*!< DBI type C 4 wire mode */ -} DBI_Mode_Type; - -/** - * @brief DBI pixel format type definition - */ -typedef enum { - DBI_PIXEL_RGB565 = 0, /*!< DBI pixel format is RGB565 */ - DBI_PIXEL_RGB666 = 1, /*!< DBI pixel format is RGB666 */ - DBI_PIXEL_RGB888 = 1, /*!< DBI pixel format is RGB888 */ -} DBI_Pixel_Format_Type; - -/** - * @brief DBI SCL clock phase definition - */ -typedef enum { - DBI_SCL_CLK_PHASE_0 = 0, /*!< DBI SCL clock phase 0 */ - DBI_SCL_CLK_PHASE_1, /*!< DBI SCL clock phase 1 */ -} DBI_SCL_CLK_Phase_Type; - -/** - * @brief DBI SCL clock polarity definition - */ -typedef enum { - DBI_SCL_CLK_POLARITY_LOW = 0, /*!< DBI SCL clock output low at idle state */ - DBI_SCL_CLK_POLARITY_HIGH, /*!< DBI SCL clock output high at idle state */ -} DBI_SCL_CLK_Polarity_Type; - -/** - * @brief DBI read/write data direction type definition - */ -typedef enum { - DBI_DATA_READ = 0, /*!< DBI read data */ - DBI_DATA_WRITE, /*!< DBI write data */ -} DBI_Data_Direction_Type; - -/** - * @brief DBI data type definition - */ -typedef enum { - DBI_DATA_NORMAL = 0, /*!< Normal data */ - DBI_DATA_PIXEL, /*!< Pixel data */ -} DBI_Data_Type; - -/** - * @brief DBI interrupt type definition - */ -typedef enum { - DBI_INT_END = 0, /*!< DBI transfer end interrupt,shared by both type B and C mode */ - DBI_INT_TX_FIFO_REQ, /*!< DBI tx fifo ready interrupt(tx fifo count > tx fifo threshold) */ - DBI_INT_FIFO_ERR, /*!< DBI tx/rx fifo overflow/underflow error interrupt */ - DBI_INT_ALL, /*!< DBI all interrupt */ -} DBI_INT_Type; - -/** - * @brief DBI tx fifo overflow or underflow type definition - */ -typedef enum { - DBI_TX_OVERFLOW, /*!< DBI tx fifo overflow */ - DBI_TX_UNDERFLOW, /*!< DBI tx fifo underflow */ -} DBI_Overflow_Type; - -/** - * @brief DBI fifo format type definition - */ -typedef enum { - DBI_FIFO_888_NBGR = 0, /*!< DBI fifo format is None[31:24] B[23:16] G[15:8] R[7:0] */ - DBI_FIFO_888_NRGB, /*!< DBI fifo format is None[31:24] R[23:16] G[15:8] B[7:0] */ - DBI_FIFO_888_BGRN, /*!< DBI fifo format is B[31:24] G[23:16] R[15:8] None[7:0] */ - DBI_FIFO_888_RGBN, /*!< DBI fifo format is R[31:24] G[23:16] B[15:8] None[7:0] */ - DBI_FIFO_888_RGBR, /*!< DBI fifo format is R[31:24] G[23:16] B[15:8] R[7:0] */ - DBI_FIFO_888_BGRB, /*!< DBI fifo format is B[31:24] G[23:16] R[15:8] B[7:0] */ - DBI_FIFO_565_BGRBGR, /*!< DBI fifo format is B[31:27] G[26:21] R[20:16] B[15:11] G[10:5] R[4:0] */ - DBI_FIFO_565_RGBRGB, /*!< DBI fifo format is R[31:27] G[26:21] B[20:16] R[15:11] G[10:5] B[4:0] */ -} DBI_FIFO_Format_Type; - -typedef struct -{ - uint8_t startLen; /*!< Length of start/stop condition */ - uint8_t dataPhase0Len; /*!< Length of data phase 0 */ - uint8_t dataPhase1Len; /*!< Length of data phase 1 */ - uint8_t intervalLen; /*!< Length of interval between pixel data */ -}DBI_Period_CFG_Type; - -/** - * @brief DBI configuration structure type definition - */ -typedef struct -{ - DBI_Mode_Type mode; /*!< DBI type B or C select */ - DBI_Pixel_Format_Type pixelFormat; /*!< DBI pixel format */ - DBI_FIFO_Format_Type fifoFormat; /*!< DBI fifo format */ - BL_Fun_Type continueEn; /*!< Enable:CS will stay asserted between each consecutive pixel, disable:CS will de-assert between each pixel */ - BL_Fun_Type dummyEn; /*!< Enable:dummy cycle will be inserted between command phase adn data phase, disable:no dummy cycle */ - uint8_t dummyCnt; /*!< Dummy cycle count,effective only in type C(fixed to 1 in type B) */ - DBI_SCL_CLK_Phase_Type clkPhase; /*!< DBI clock phase */ - DBI_SCL_CLK_Polarity_Type clkPolarity; /*!< DBI clock polarity */ - DBI_Period_CFG_Type period; /*!< Period configuration */ -} DBI_CFG_Type; - -/** - * @brief DBI command and data configuration structure type definition - */ -typedef struct -{ - BL_Fun_Type commandEn; /*!< Enable or disable command */ - uint8_t command; /*!< Command to send */ - BL_Fun_Type dataEn; /*!< Enable or disable data */ - DBI_Data_Type dataType; /*!< Select normal data or pixel data */ - DBI_Data_Direction_Type dataDir; /*!< Select read or write data */ - uint8_t dataCnt; /*!< Set byte count of normal data */ - uint32_t data; /*!< Data to send */ -} DBI_CD_CFG_Type; - -/*@} end of group DBI_Public_Types */ - -/** @defgroup DBI_Public_Constants - * @{ - */ - -/** @defgroup DBI_MODE_TYPE - * @{ - */ -#define IS_DBI_MODE_TYPE(type) (((type) == DBI_TYPE_B) || \ - ((type) == DBI_TYPE_C_3_WIRE) || \ - ((type) == DBI_TYPE_C_4_WIRE)) - -/** @defgroup DBI_PIXEL_FORMAT_TYPE - * @{ - */ -#define IS_DBI_PIXEL_FORMAT_TYPE(type) (((type) == DBI_PIXEL_RGB565) || \ - ((type) == DBI_PIXEL_RGB666) || \ - ((type) == DBI_PIXEL_RGB888)) - -/** @defgroup DBI_SCL_CLK_PHASE_TYPE - * @{ - */ -#define IS_DBI_SCL_CLK_PHASE_TYPE(type) (((type) == DBI_SCL_CLK_PHASE_0) || \ - ((type) == DBI_SCL_CLK_PHASE_1)) - -/** @defgroup DBI_SCL_CLK_POLARITY_TYPE - * @{ - */ -#define IS_DBI_SCL_CLK_POLARITY_TYPE(type) (((type) == DBI_SCL_CLK_POLARITY_LOW) || \ - ((type) == DBI_SCL_CLK_POLARITY_HIGH)) - -/** @defgroup DBI_DATA_DIRECTION_TYPE - * @{ - */ -#define IS_DBI_DATA_DIRECTION_TYPE(type) (((type) == DBI_DATA_READ) || \ - ((type) == DBI_DATA_WRITE)) - -/** @defgroup DBI_DATA_TYPE - * @{ - */ -#define IS_DBI_DATA_TYPE(type) (((type) == DBI_DATA_NORMAL) || \ - ((type) == DBI_DATA_PIXEL)) - -/** @defgroup DBI_INT_TYPE - * @{ - */ -#define IS_DBI_INT_TYPE(type) (((type) == DBI_INT_END) || \ - ((type) == DBI_INT_TX_FIFO_REQ) || \ - ((type) == DBI_INT_FIFO_ERR) || \ - ((type) == DBI_INT_ALL)) - -/** @defgroup DBI_OVERFLOW_TYPE - * @{ - */ -#define IS_DBI_OVERFLOW_TYPE(type) (((type) == DBI_TX_OVERFLOW) || \ - ((type) == DBI_TX_UNDERFLOW)) - -/** @defgroup DBI_FIFO_FORMAT_TYPE - * @{ - */ -#define IS_DBI_FIFO_FORMAT_TYPE(type) (((type) == DBI_FIFO_888_NBGR) || \ - ((type) == DBI_FIFO_888_NRGB) || \ - ((type) == DBI_FIFO_888_BGRN) || \ - ((type) == DBI_FIFO_888_RGBN) || \ - ((type) == DBI_FIFO_888_RGBR) || \ - ((type) == DBI_FIFO_888_BGRB) || \ - ((type) == DBI_FIFO_565_BGRBGR) || \ - ((type) == DBI_FIFO_565_RGBRGB)) - -/*@} end of group DBI_Public_Constants */ - -/** @defgroup DBI_Public_Macros - * @{ - */ -#define DBI_TX_FIFO_SIZE 8 - -/*@} end of group DBI_Public_Macros */ - -/** @defgroup DBI_Public_Functions - * @{ - */ -#ifndef BL808_USE_HAL_DRIVER -void DBI_IRQHandler(void); -#endif -BL_Err_Type DBI_Init(DBI_CFG_Type *dbiCfg); -void DBI_Enable(void); -void DBI_Disable(void); - -void DBI_SetPeriod(DBI_Period_CFG_Type *period); -void DBI_SetCommand(uint8_t Command); -void DBI_SetPhaseState(BL_Fun_Type commandEn, BL_Fun_Type dataEn); -void DBI_SetDataTypeAndCount(DBI_Data_Type dataType, uint32_t dataCount); -void DBI_SetNormalDataDir(DBI_Data_Direction_Type dataDir); -void DBI_ReadNormlData(uint8_t dataSize, uint8_t *dataBuff); -void DBI_WriteNormlData(uint8_t dataSize, uint8_t *dataBuff); -void DBI_WirteData2FIFO(uint32_t wordCount, uint32_t *dataBuff); - -uint32_t DBI_GetWordCountOfPixelData(int32_t PixelCount); -void DBI_SendCmdWithNormalData(uint8_t command, uint8_t dataSize, uint8_t *dataBuff); -void DBI_SendCmdAndReadNormalData(uint8_t command, uint8_t dataSize, uint8_t *dataBuff); -void DBI_SendCmdWithPixelData(uint8_t command, int32_t PixelCount, uint32_t *pixelBuff); - -void DBI_TxFifoClear(void); -void DBI_SetDMA(BL_Fun_Type dmaEn); -void DBI_SetTxFifoThreshold(uint8_t threshold); -uint8_t DBI_GetTxFifoCount(void); -BL_Sts_Type DBI_GetIntStatus(DBI_INT_Type intType); -BL_Sts_Type DBI_GetOverflowStatus(DBI_Overflow_Type overflow); -BL_Sts_Type DBI_GetBusBusyStatus(void); -void DBI_IntMask(DBI_INT_Type intType, BL_Mask_Type intMask); -void DBI_IntClear(void); -void DBI_Int_Callback_Install(DBI_INT_Type intType, intCallback_Type *cbFun); - -/*@} end of group DBI_Public_Functions */ - -/*@} end of group DBI */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_DBI_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dma.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dma.h deleted file mode 100644 index 49787ac2e4..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dma.h +++ /dev/null @@ -1,439 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_dma.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_DMA_H__ -#define __BL808_DMA_H__ - -#include "dma_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup DMA - * @{ - */ - -/** @defgroup DMA_Public_Types - * @{ - */ - -/** - * @brief DMA port type definition - */ -typedef enum { - DMA0_ID, /*!< DMA0 port define,WLSYS,8 channels */ - DMA1_ID, /*!< DMA1 port define,WLSYS,4 channels */ - DMA2_ID, /*!< DMA2 port define,MMSYS,8 channels */ - DMA_ID_MAX, /*!< DMA MAX ID define */ -} DMA_ID_Type; - -/** - * @brief DMA endian type definition - */ -typedef enum { - DMA_LITTLE_ENDIAN = 0, /*!< DMA use little endian */ - DMA_BIG_ENDIAN, /*!< DMA use big endian */ -} DMA_Endian_Type; - -/** - * @brief DMA synchronization logic type definition - */ -typedef enum { - DMA_SYNC_LOGIC_ENABLE = 0, /*!< DMA synchronization logic enable */ - DMA_SYNC_LOGIC_DISABLE, /*!< DMA synchronization logic disable */ -} DMA_Sync_Logic_Type; - -/** - * @brief DMA transfer width type definition - */ -typedef enum { - DMA_TRNS_WIDTH_8BITS = 0, /*!< DMA transfer width:8 bits */ - DMA_TRNS_WIDTH_16BITS, /*!< DMA transfer width:16 bits */ - DMA_TRNS_WIDTH_32BITS, /*!< DMA transfer width:32 bits */ - DMA_TRNS_WIDTH_64BITS, /*!< DMA transfer width:64 bits, only for DMA2 channel 0 and channel 1, others should not use this */ -} DMA_Trans_Width_Type; - -/** - * @brief DMA transfer direction type definition - */ -typedef enum { - DMA_TRNS_M2M = 0, /*!< DMA transfer tyep:memory to memory */ - DMA_TRNS_M2P, /*!< DMA transfer tyep:memory to peripheral */ - DMA_TRNS_P2M, /*!< DMA transfer tyep:peripheral to memory */ - DMA_TRNS_P2P, /*!< DMA transfer tyep:peripheral to peripheral */ -} DMA_Trans_Dir_Type; - -/** - * @brief DMA burst size type definition - */ -typedef enum { - DMA_BURST_SIZE_1 = 0, /*!< DMA burst size:1 * transfer width */ - DMA_BURST_SIZE_4, /*!< DMA burst size:4 * transfer width */ - DMA_BURST_SIZE_8, /*!< DMA burst size:8 * transfer width */ - DMA_BURST_SIZE_16, /*!< DMA burst size:16 * transfer width */ -} DMA_Burst_Size_Type; - -/** - * @brief DMA destination peripheral type definition - */ -typedef enum { - DMA_REQ_UART0_RX = 0, /*!< DMA request peripheral:UART0 RX, DMA0 and DMA1 support */ - DMA_REQ_UART0_TX = 1, /*!< DMA request peripheral:UART0 TX, DMA0 and DMA1 support */ - DMA_REQ_UART1_RX = 2, /*!< DMA request peripheral:UART1 RX, DMA0 and DMA1 support */ - DMA_REQ_UART1_TX = 3, /*!< DMA request peripheral:UART1 TX, DMA0 and DMA1 support */ - DMA_REQ_UART2_RX = 4, /*!< DMA request peripheral:UART2 RX, DMA0 and DMA1 support */ - DMA_REQ_UART2_TX = 5, /*!< DMA request peripheral:UART2 TX, DMA0 and DMA1 support */ - DMA_REQ_I2C0_RX = 6, /*!< DMA request peripheral:I2C0 RX, DMA0 and DMA1 support */ - DMA_REQ_I2C0_TX = 7, /*!< DMA request peripheral:I2C0 TX, DMA0 and DMA1 support */ - DMA_REQ_IR_TX = 8, /*!< DMA request peripheral:IR TX, DMA0 and DMA1 support */ - DMA_REQ_GPIO_TX = 9, /*!< DMA request peripheral:GPIO TX, DMA0 and DMA1 support */ - DMA_REQ_SPI0_RX = 10, /*!< DMA request peripheral:SPI0 RX, DMA0 and DMA1 support */ - DMA_REQ_SPI0_TX = 11, /*!< DMA request peripheral:SPI0 TX, DMA0 and DMA1 support */ - DMA_REQ_AUDIO_RX = 12, /*!< DMA request peripheral:AUDIO RX, DMA0 and DMA1 support */ - DMA_REQ_AUDIO_TX = 13, /*!< DMA request peripheral:AUDIO TX, DMA0 and DMA1 support */ - DMA_REQ_I2C1_RX = 14, /*!< DMA request peripheral:I2C1 RX, DMA0 and DMA1 support */ - DMA_REQ_I2C1_TX = 15, /*!< DMA request peripheral:I2C1 TX, DMA0 and DMA1 support */ - DMA_REQ_I2S_RX = 16, /*!< DMA request peripheral:I2S RX, DMA0 and DMA1 support */ - DMA_REQ_I2S_TX = 17, /*!< DMA request peripheral:I2S TX, DMA0 and DMA1 support */ - DMA_REQ_PDM_RX = 18, /*!< DMA request peripheral:PDM RX, DMA0 and DMA1 support */ - DMA_REQ_GPADC_RX = 22, /*!< DMA request peripheral:GPADC RX, DMA0 and DMA1 support */ - DMA_REQ_GPADC_TX = 23, /*!< DMA request peripheral:GPADC TX, DMA0 and DMA1 support */ - DMA_REQ_UART3_RX = 0, /*!< DMA request peripheral:UART3 RX, only DMA2 support */ - DMA_REQ_UART3_TX = 1, /*!< DMA request peripheral:UART3 TX, only DMA2 support */ - DMA_REQ_SPI1_RX = 2, /*!< DMA request peripheral:SPI1 RX, only DMA2 support */ - DMA_REQ_SPI1_TX = 3, /*!< DMA request peripheral:SPI1 TX, only DMA2 support */ - DMA_REQ_I2C2_RX = 6, /*!< DMA request peripheral:I2C2 RX, only DMA2 support */ - DMA_REQ_I2C2_TX = 7, /*!< DMA request peripheral:I2C2 TX, only DMA2 support */ - DMA_REQ_I2C3_RX = 8, /*!< DMA request peripheral:I2C3 RX, only DMA2 support */ - DMA_REQ_I2C3_TX = 9, /*!< DMA request peripheral:I2C3 TX, only DMA2 support */ - DMA_REQ_DSI_RX = 10, /*!< DMA request peripheral:DSI RX, only DMA2 support */ - DMA_REQ_DSI_TX = 11, /*!< DMA request peripheral:DSI TX, only DMA2 support */ - DMA_REQ_DBI_TX = 22, /*!< DMA request peripheral:DBI TX, only DMA2 support */ - DMA_REQ_NONE = 0, /*!< DMA request peripheral:None */ -} DMA_Periph_Req_Type; - -/** - * @brief DMA channel type definition - */ -typedef enum { - DMA_CH0 = 0, /*!< DMA channel 0 */ - DMA_CH1, /*!< DMA channel 1 */ - DMA_CH2, /*!< DMA channel 2 */ - DMA_CH3, /*!< DMA channel 3 */ - DMA_CH4, /*!< DMA channel 4 */ - DMA_CH5, /*!< DMA channel 5 */ - DMA_CH6, /*!< DMA channel 6 */ - DMA_CH7, /*!< DMA channel 7 */ - DMA_CH_MAX, /*!< */ -} DMA_Chan_Type; - -/** - * @brief DMA LLI Structure PING-PONG - */ -typedef enum { - PING_INDEX = 0, /*!< PING INDEX */ - PONG_INDEX, /*!< PONG INDEX */ -} DMA_LLI_PP_Index_Type; - -/** - * @brief DMA interrupt type definition - */ -typedef enum { - DMA_INT_TCOMPLETED = 0, /*!< DMA completed interrupt */ - DMA_INT_ERR, /*!< DMA error interrupt */ - DMA_INT_ALL, /*!< All the interrupt */ -} DMA_INT_Type; - -/** - * @brief DMA Configuration Structure type definition - */ -typedef struct -{ - DMA_Endian_Type endian; /*!< DMA endian type */ - DMA_Sync_Logic_Type syncLogic; /*!< DMA synchronization logic */ -} DMA_Cfg_Type; - -/** - * @brief DMA channel Configuration Structure type definition - */ -typedef struct -{ - uint32_t srcDmaAddr; /*!< Source address of DMA transfer */ - uint32_t destDmaAddr; /*!< Destination address of DMA transfer */ - uint32_t transfLength; /*!< Transfer length, 0~4095, this is burst count */ - DMA_Trans_Dir_Type dir; /*!< Transfer dir control. 0: Memory to Memory, 1: Memory to peripheral, 2: Peripheral to memory */ - DMA_Chan_Type ch; /*!< Channel select 0-7 */ - DMA_Trans_Width_Type srcTransfWidth; /*!< Transfer width. 0: 8 bits, 1: 16 bits, 2: 32 bits, 3: 64 bits(only for DMA2 channel 0 and - channel 1) */ - DMA_Trans_Width_Type dstTransfWidth; /*!< Transfer width. 0: 8 bits, 1: 16 bits, 2: 32 bits, 3: 64 bits(only for DMA2 channel 0 and - channel 1) */ - DMA_Burst_Size_Type srcBurstSize; /*!< Number of data items for burst transaction length. Each item width is as same as tansfer width. - 0: 1 item, 1: 4 items, 2: 8 items, 3: 16 items */ - DMA_Burst_Size_Type dstBurstSize; /*!< Number of data items for burst transaction length. Each item width is as same as tansfer width. - 0: 1 item, 1: 4 items, 2: 8 items, 3: 16 items */ - BL_Fun_Type dstAddMode; /*!< */ - BL_Fun_Type dstMinMode; /*!< */ - uint8_t fixCnt; /*!< */ - uint8_t srcAddrInc; /*!< Source address increment. 0: No change, 1: Increment */ - uint8_t destAddrInc; /*!< Destination address increment. 0: No change, 1: Increment */ - DMA_Periph_Req_Type srcPeriph; /*!< Source peripheral select */ - DMA_Periph_Req_Type dstPeriph; /*!< Destination peripheral select */ -} DMA_Channel_Cfg_Type; - -/** - * @brief DMA LLI control structure type definition - */ -typedef struct -{ - uint32_t srcDmaAddr; /*!< Source address of DMA transfer */ - uint32_t destDmaAddr; /*!< Destination address of DMA transfer */ - uint32_t nextLLI; /*!< Next LLI address */ - struct DMA_Control_Reg dmaCtrl; /*!< DMA transaction control */ -} DMA_LLI_Ctrl_Type; - -/** - * @brief DMA LLI configuration structure type definition - */ -typedef struct -{ - DMA_Trans_Dir_Type dir; /*!< Transfer dir control. 0: Memory to Memory, 1: Memory to peripheral, 2: Peripheral to memory */ - DMA_Periph_Req_Type srcPeriph; /*!< Source peripheral select */ - DMA_Periph_Req_Type dstPeriph; /*!< Destination peripheral select */ -} DMA_LLI_Cfg_Type; - -/** - * @brief DMA LLI Ping-Pong Buf definition - */ -typedef struct -{ - uint8_t idleIndex; /*!< Index Idle lliListHeader */ - uint8_t dmaId; /*!< DMA ID used */ - uint8_t dmaChan; /*!< DMA LLI Channel used */ - DMA_LLI_Ctrl_Type *lliListHeader[2]; /*!< Ping-Pong BUf List Header */ - void (*onTransCompleted)(DMA_LLI_Ctrl_Type *); /*!< Completed Transmit One List Callback Function */ -} DMA_LLI_PP_Buf; - -/** - * @brief DMA LLI Ping-Pong Structure definition - */ -typedef struct -{ - uint8_t pingpongIndex; /*!< Ping or Pong Trigger TC */ - uint8_t dmaId; /*!< DMA ID used */ - uint8_t dmaChan; /*!< DMA LLI Channel used */ - struct DMA_Control_Reg dmaCtrlRegVal; /*!< DMA Basic Pararmeter */ - DMA_LLI_Cfg_Type *lliCfg; /*!< LLI Config parameter */ - uint32_t operatePeriphAddr; /*!< Operate Peripheral register address */ - uint32_t pingpongBufAddr[2]; /*!< Ping-Pong addr */ -} DMA_LLI_PP_Struct; - -/*@} end of group DMA_Public_Types */ - -/** @defgroup DMA_Public_Constants - * @{ - */ - -/** @defgroup DMA_ID_TYPE - * @{ - */ -#define IS_DMA_ID_TYPE(type) (((type) == DMA0_ID) || \ - ((type) == DMA1_ID) || \ - ((type) == DMA2_ID) || \ - ((type) == DMA_ID_MAX)) - -/** @defgroup DMA_ENDIAN_TYPE - * @{ - */ -#define IS_DMA_ENDIAN_TYPE(type) (((type) == DMA_LITTLE_ENDIAN) || \ - ((type) == DMA_BIG_ENDIAN)) - -/** @defgroup DMA_SYNC_LOGIC_TYPE - * @{ - */ -#define IS_DMA_SYNC_LOGIC_TYPE(type) (((type) == DMA_SYNC_LOGIC_ENABLE) || \ - ((type) == DMA_SYNC_LOGIC_DISABLE)) - -/** @defgroup DMA_TRANS_WIDTH_TYPE - * @{ - */ -#define IS_DMA_TRANS_WIDTH_TYPE(type) (((type) == DMA_TRNS_WIDTH_8BITS) || \ - ((type) == DMA_TRNS_WIDTH_16BITS) || \ - ((type) == DMA_TRNS_WIDTH_32BITS) || \ - ((type) == DMA_TRNS_WIDTH_64BITS)) - -/** @defgroup DMA_TRANS_DIR_TYPE - * @{ - */ -#define IS_DMA_TRANS_DIR_TYPE(type) (((type) == DMA_TRNS_M2M) || \ - ((type) == DMA_TRNS_M2P) || \ - ((type) == DMA_TRNS_P2M) || \ - ((type) == DMA_TRNS_P2P)) - -/** @defgroup DMA_BURST_SIZE_TYPE - * @{ - */ -#define IS_DMA_BURST_SIZE_TYPE(type) (((type) == DMA_BURST_SIZE_1) || \ - ((type) == DMA_BURST_SIZE_4) || \ - ((type) == DMA_BURST_SIZE_8) || \ - ((type) == DMA_BURST_SIZE_16)) - -/** @defgroup DMA_PERIPH_REQ_TYPE - * @{ - */ -#define IS_DMA_PERIPH_REQ_TYPE(type) (((type) == DMA_REQ_UART0_RX) || \ - ((type) == DMA_REQ_UART0_TX) || \ - ((type) == DMA_REQ_UART1_RX) || \ - ((type) == DMA_REQ_UART1_TX) || \ - ((type) == DMA_REQ_UART2_RX) || \ - ((type) == DMA_REQ_UART2_TX) || \ - ((type) == DMA_REQ_I2C0_RX) || \ - ((type) == DMA_REQ_I2C0_TX) || \ - ((type) == DMA_REQ_IR_TX) || \ - ((type) == DMA_REQ_GPIO_TX) || \ - ((type) == DMA_REQ_SPI0_RX) || \ - ((type) == DMA_REQ_SPI0_TX) || \ - ((type) == DMA_REQ_AUDIO_RX) || \ - ((type) == DMA_REQ_AUDIO_TX) || \ - ((type) == DMA_REQ_I2C1_RX) || \ - ((type) == DMA_REQ_I2C1_TX) || \ - ((type) == DMA_REQ_I2S_RX) || \ - ((type) == DMA_REQ_I2S_TX) || \ - ((type) == DMA_REQ_PDM_RX) || \ - ((type) == DMA_REQ_GPADC_RX) || \ - ((type) == DMA_REQ_GPADC_TX) || \ - ((type) == DMA_REQ_UART3_RX) || \ - ((type) == DMA_REQ_UART3_TX) || \ - ((type) == DMA_REQ_SPI1_RX) || \ - ((type) == DMA_REQ_SPI1_TX) || \ - ((type) == DMA_REQ_I2C2_RX) || \ - ((type) == DMA_REQ_I2C2_TX) || \ - ((type) == DMA_REQ_I2C3_RX) || \ - ((type) == DMA_REQ_I2C3_TX) || \ - ((type) == DMA_REQ_DSI_RX) || \ - ((type) == DMA_REQ_DBI_TX) || \ - ((type) == DMA_REQ_DBI_TX) || \ - ((type) == DMA_REQ_NONE)) - -/** @defgroup DMA_CHAN_TYPE - * @{ - */ -#define IS_DMA_CHAN_TYPE(type) (((type) == DMA_CH0) || \ - ((type) == DMA_CH1) || \ - ((type) == DMA_CH2) || \ - ((type) == DMA_CH3) || \ - ((type) == DMA_CH4) || \ - ((type) == DMA_CH5) || \ - ((type) == DMA_CH6) || \ - ((type) == DMA_CH7) || \ - ((type) == DMA_CH_MAX)) - -/** @defgroup DMA_LLI_PP_INDEX_TYPE - * @{ - */ -#define IS_DMA_LLI_PP_INDEX_TYPE(type) (((type) == PING_INDEX) || \ - ((type) == PONG_INDEX)) - -/** @defgroup DMA_INT_TYPE - * @{ - */ -#define IS_DMA_INT_TYPE(type) (((type) == DMA_INT_TCOMPLETED) || \ - ((type) == DMA_INT_ERR) || \ - ((type) == DMA_INT_ALL)) - -/*@} end of group DMA_Public_Constants */ - -/** @defgroup DMA_Public_Macros - * @{ - */ -#define DMA_PINC_ENABLE 1 -#define DMA_PINC_DISABLE 0 -#define DMA_MINC_ENABLE 1 -#define DMA_MINC_DISABLE 0 - -/*@} end of group DMA_Public_Macros */ - -/** @defgroup DMA_Public_Functions - * @{ - */ - -/** - * @brief DMA Functions - */ -#ifndef BFLB_USE_HAL_DRIVER -void DMA0_ALL_IRQHandler(void); -void DMA1_ALL_IRQHandler(void); -void DMA2_INT0_IRQHandler(void); -void DMA2_INT1_IRQHandler(void); -void DMA2_INT2_IRQHandler(void); -void DMA2_INT3_IRQHandler(void); -void DMA2_INT4_IRQHandler(void); -void DMA2_INT5_IRQHandler(void); -void DMA2_INT6_IRQHandler(void); -void DMA2_INT7_IRQHandler(void); -#endif -void DMA_Enable(DMA_ID_Type dmaId); -void DMA_Disable(DMA_ID_Type dmaId); -void DMA_Channel_Init(DMA_ID_Type dmaId, DMA_Channel_Cfg_Type *chCfg); -void DMA_DeInit(DMA_ID_Type dmaId); -void DMA_Channel_Update_SrcMemcfg(DMA_ID_Type dmaId, uint8_t ch, uint32_t memAddr, uint32_t len); -void DMA_Channel_Update_DstMemcfg(DMA_ID_Type dmaId, uint8_t ch, uint32_t memAddr, uint32_t len); -uint32_t DMA_Channel_TranferSize(DMA_ID_Type dmaId, uint8_t ch); -BL_Sts_Type DMA_Channel_Is_Busy(DMA_ID_Type dmaId, uint8_t ch); -void DMA_Channel_Enable(DMA_ID_Type dmaId, uint8_t ch); -void DMA_Channel_Disable(DMA_ID_Type dmaId, uint8_t ch); -void DMA_LLI_Init(DMA_ID_Type dmaId, uint8_t ch, DMA_LLI_Cfg_Type *lliCfg); -void DMA_LLI_Update(DMA_ID_Type dmaId, uint8_t ch, uint32_t LLI); -uint32_t DMA_LLI_Get_Counter(DMA_ID_Type dmaId, uint8_t ch); -void DMA_IntMask(DMA_ID_Type dmaId, uint8_t ch, DMA_INT_Type intType, BL_Mask_Type intMask); -void DMA_LLI_PpBuf_Start_New_Transmit(DMA_LLI_PP_Buf *dmaPpBuf); -DMA_LLI_Ctrl_Type *DMA_LLI_PpBuf_Remove_Completed_List(DMA_LLI_PP_Buf *dmaPpBuf); -void DMA_LLI_PpBuf_Append(DMA_LLI_PP_Buf *dmaPpBuf, DMA_LLI_Ctrl_Type *dmaLliList); -void DMA_LLI_PpBuf_Destroy(DMA_LLI_PP_Buf *dmaPpBuf); -void DMA_Int_Callback_Install(DMA_ID_Type dmaId, DMA_Chan_Type dmaChan, DMA_INT_Type intType, intCallback_Type *cbFun); -void DMA_LLI_PpStruct_Start(DMA_LLI_PP_Struct *dmaPpStruct); -void DMA_LLI_PpStruct_Stop(DMA_LLI_PP_Struct *dmaPpStruct); -BL_Err_Type DMA_LLI_PpStruct_Init(DMA_LLI_PP_Struct *dmaPpStruct); -BL_Err_Type DMA_LLI_PpStruct_Set_Transfer_Len(DMA_LLI_PP_Struct *dmaPpStruct, - uint16_t Ping_Transfer_len, uint16_t Pong_Transfer_len); - -/*@} end of group DMA_Public_Functions */ - -/*@} end of group DMA */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_DMA_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dma2d.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dma2d.h deleted file mode 100644 index dd51a48aa5..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dma2d.h +++ /dev/null @@ -1,492 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_dma2d.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_DMA2D_H__ -#define __BL808_DMA2D_H__ - -#include "dma2d_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup DMA2D - * @{ - */ - -/** @defgroup DMA2D_Public_Types - * @{ - */ - -/** - * @brief DMA2D port type definition - */ -typedef enum { - DMA2D0_ID, /*!< DMA2D0 port define */ - DMA2D_ID_MAX, /*!< DMA2D MAX ID define */ -} DMA2D_ID_Type; - -/** - * @brief DMA2D endian type definition - */ -typedef enum { - DMA2D_LITTLE_ENDIAN = 0, /*!< DMA2D use little endian */ - DMA2D_BIG_ENDIAN, /*!< DMA2D use big endian */ -} DMA2D_Endian_Type; - -/** - * @brief DMA2D synchronization logic type definition - */ -typedef enum { - DMA2D_SYNC_LOGIC_ENABLE = 0, /*!< DMA2D synchronization logic enable */ - DMA2D_SYNC_LOGIC_DISABLE, /*!< DMA2D synchronization logic disable */ -} DMA2D_Sync_Logic_Type; - -/** - * @brief DMA2D transfer width type definition - */ -typedef enum { - DMA2D_TRNS_WIDTH_8BITS = 0, /*!< DMA2D transfer width:8 bits */ - DMA2D_TRNS_WIDTH_16BITS, /*!< DMA2D transfer width:16 bits */ - DMA2D_TRNS_WIDTH_32BITS, /*!< DMA2D transfer width:32 bits */ -} DMA2D_Trans_Width_Type; - -/** - * @brief DMA2D transfer direction type definition - */ -typedef enum { - DMA2D_TRNS_M2M = 0, /*!< DMA2D transfer type:memory to memory */ - DMA2D_TRNS_M2P, /*!< DMA2D transfer type:memory to peripheral */ - DMA2D_TRNS_P2M, /*!< DMA2D transfer type:peripheral to memory */ - DMA2D_TRNS_P2P, /*!< DMA2D transfer type:peripheral to peripheral */ -} DMA2D_Trans_Dir_Type; - -/** - * @brief DMA2D burst size type definition - */ -typedef enum { - DMA2D_BURST_SIZE_1 = 0, /*!< DMA2D burst size:1 * transfer width */ - DMA2D_BURST_SIZE_4, /*!< DMA2D burst size:4 * transfer width */ - DMA2D_BURST_SIZE_8, /*!< DMA2D burst size:8 * transfer width */ - DMA2D_BURST_SIZE_16, /*!< DMA2D burst size:16 * transfer width */ -} DMA2D_Burst_Size_Type; - -/** - * @brief DMA2D destination peripheral type definition - */ -typedef enum { - DMA2D_REQ_UART0_RX = 0, /*!< DMA2D request peripheral:UART0 RX, DMA2D0 and DMA2D1 support */ - DMA2D_REQ_UART0_TX = 1, /*!< DMA2D request peripheral:UART0 TX, DMA2D0 and DMA2D1 support */ - DMA2D_REQ_UART1_RX = 2, /*!< DMA2D request peripheral:UART1 RX, DMA2D0 and DMA2D1 support */ - DMA2D_REQ_UART1_TX = 3, /*!< DMA2D request peripheral:UART1 TX, DMA2D0 and DMA2D1 support */ - DMA2D_REQ_UART2_RX = 4, /*!< DMA2D request peripheral:UART2 RX, DMA2D0 and DMA2D1 support */ - DMA2D_REQ_UART2_TX = 5, /*!< DMA2D request peripheral:UART2 TX, DMA2D0 and DMA2D1 support */ - DMA2D_REQ_I2C0_RX = 6, /*!< DMA2D request peripheral:I2C0 RX, DMA2D0 and DMA2D1 support */ - DMA2D_REQ_I2C0_TX = 7, /*!< DMA2D request peripheral:I2C0 TX, DMA2D0 and DMA2D1 support */ - DMA2D_REQ_IR_TX = 8, /*!< DMA2D request peripheral:IR TX, DMA2D0 and DMA2D1 support */ - DMA2D_REQ_GPIO = 9, /*!< DMA2D request peripheral:GPIO, DMA2D0 and DMA2D1 support */ - DMA2D_REQ_SPI0_RX = 10, /*!< DMA2D request peripheral:SPI0 RX, DMA2D0 and DMA2D1 support */ - DMA2D_REQ_SPI0_TX = 11, /*!< DMA2D request peripheral:SPI0 TX, DMA2D0 and DMA2D1 support */ - DMA2D_REQ_AUDIO_RX = 12, /*!< DMA2D request peripheral:AUDIO RX, DMA2D0 and DMA2D1 support */ - DMA2D_REQ_AUDIO_TX = 13, /*!< DMA2D request peripheral:AUDIO TX, DMA2D0 and DMA2D1 support */ - DMA2D_REQ_GPADC0 = 22, /*!< DMA2D request peripheral:GPADC0, DMA2D0 and DMA2D1 support */ - DMA2D_REQ_GPADC1 = 23, /*!< DMA2D request peripheral:GPADC1, DMA2D0 and DMA2D1 support */ - DMA2D_REQ_USB_EP0 = 24, /*!< DMA2D request peripheral:USB EP 0, DMA2D0 and DMA2D1 support */ - DMA2D_REQ_USB_EP1 = 25, /*!< DMA2D request peripheral:USB EP 1, DMA2D0 and DMA2D1 support */ - DMA2D_REQ_USB_EP2 = 26, /*!< DMA2D request peripheral:USB EP 2, DMA2D0 and DMA2D1 support */ - DMA2D_REQ_USB_EP3 = 27, /*!< DMA2D request peripheral:USB EP 3, DMA2D0 and DMA2D1 support */ - DMA2D_REQ_USB_EP4 = 28, /*!< DMA2D request peripheral:USB EP 4, DMA2D0 and DMA2D1 support */ - DMA2D_REQ_USB_EP5 = 29, /*!< DMA2D request peripheral:USB EP 5, DMA2D0 and DMA2D1 support */ - DMA2D_REQ_USB_EP6 = 30, /*!< DMA2D request peripheral:USB EP 6, DMA2D0 and DMA2D1 support */ - DMA2D_REQ_USB_EP7 = 31, /*!< DMA2D request peripheral:USB EP 7, DMA2D0 and DMA2D1 support */ - DMA2D_REQ_UART3_RX = 0, /*!< DMA2D request peripheral:UART3 RX, only DMA2D2 support */ - DMA2D_REQ_UART3_TX = 1, /*!< DMA2D request peripheral:UART3 TX, only DMA2D2 support */ - DMA2D_REQ_SPI1_RX = 2, /*!< DMA2D request peripheral:SPI1 RX, only DMA2D2 support */ - DMA2D_REQ_SPI1_TX = 3, /*!< DMA2D request peripheral:SPI1 TX, only DMA2D2 support */ - DMA2D_REQ_I2C1_RX = 6, /*!< DMA2D request peripheral:I2C1 RX, only DMA2D2 support */ - DMA2D_REQ_I2C1_TX = 7, /*!< DMA2D request peripheral:I2C1 TX, only DMA2D2 support */ - DMA2D_REQ_I2S_TX = 12, /*!< DMA2D request peripheral:I2S TX, only DMA2D2 support */ - DMA2D_REQ_I2S_RX = 13, /*!< DMA2D request peripheral:I2S RX, only DMA2D2 support */ - DMA2D_REQ_DBI_TX = 22, /*!< DMA2D request peripheral:DBI TX, only DMA2D2 support */ - DMA2D_REQ_NONE = 0, /*!< DMA2D request peripheral:None */ -} DMA2D_Periph_Req_Type; - -/** - * @brief DMA2D channel type definition - */ -typedef enum { - DMA2D_CH0 = 0, /*!< DMA2D channel 0 */ - DMA2D_CH1, /*!< DMA2D channel 1 */ - DMA2D_CH_MAX, /*!< */ -} DMA2D_Chan_Type; - -/** - * @brief DMA2D LLI Structure PING-PONG - */ -typedef enum { - DMA2D_PING_INDEX = 0, /*!< PING INDEX */ - DMA2D_PONG_INDEX, /*!< PONG INDEX */ -} DMA2D_LLI_PP_Index_Type; - -/** - * @brief DMA2D interrupt type definition - */ -typedef enum { - DMA2D_INT_TCOMPLETED = 0, /*!< DMA2D completed interrupt */ - DMA2D_INT_ALL, /*!< All the interrupt */ -} DMA2D_INT_Type; - -/** - * @brief DMA2D rotate type definition - */ -typedef enum { - DMA2D_ROTATE_DEGREE_90 = 0, /*!< DMA2D rotate 90 degrees */ - DMA2D_ROTATE_DEGREE_180, /*!< DMA2D rotate 180 degrees */ - DMA2D_ROTATE_DEGREE_270, /*!< DMA2D rotate 270 degrees */ -} DMA2D_Rotate_Type; - -/** - * @brief DMA2D fold type definition - */ -typedef enum { - DMA2D_FOLD_LEFT_RIGHT = 0, /*!< DMA2D fold left and right */ - DMA2D_FOLD_UP_DOWN, /*!< DMA2D fold up and down */ -} DMA2D_Fold_Type; - -/** - * @brief DMA2D color key type definition - */ -typedef enum { - DMA2D_COLOR_KEY_8BIT = 0, /*!< DMA2D color key is 8-bit */ - DMA2D_COLOR_KEY_16BIT, /*!< DMA2D color key is 16-bit */ - DMA2D_COLOR_KEY_24BIT, /*!< DMA2D color key is 24-bit */ - DMA2D_COLOR_KEY_32BIT, /*!< DMA2D color key is 32-bit */ -} DMA2D_Color_Key_Type; - -/** - * @brief DMA2D channel Configuration Structure type definition - */ -typedef struct -{ - uint32_t srcDmaAddr; /*!< Source address of DMA2D transfer */ - uint32_t destDmaAddr; /*!< Destination address of DMA2D transfer */ - uint32_t transfLength; /*!< Transfer length, 0~4095, this is burst count */ - DMA2D_Trans_Dir_Type dir; /*!< Transfer dir control. 0: Memory to Memory, 1: Memory to peripheral, 2: Peripheral to memory */ - DMA2D_Chan_Type ch; /*!< Channel select 0-7 */ - DMA2D_Trans_Width_Type srcTransfWidth; /*!< Transfer width. 0: 8 bits, 1: 16 bits, 2: 32 bits, 3: 64 bits(only for DMA2D2 channel 0 and - channel 1) */ - DMA2D_Trans_Width_Type dstTransfWidth; /*!< Transfer width. 0: 8 bits, 1: 16 bits, 2: 32 bits, 3: 64 bits(only for DMA2D2 channel 0 and - channel 1) */ - DMA2D_Burst_Size_Type srcBurstSize; /*!< Number of data items for burst transaction length. Each item width is as same as tansfer width. - 0: 1 item, 1: 4 items, 2: 8 items, 3: 16 items */ - DMA2D_Burst_Size_Type dstBurstSize; /*!< Number of data items for burst transaction length. Each item width is as same as tansfer width. - 0: 1 item, 1: 4 items, 2: 8 items, 3: 16 items */ - uint8_t srcAddrInc; /*!< Source address increment. 0: No change, 1: Increment */ - uint8_t destAddrInc; /*!< Destination address increment. 0: No change, 1: Increment */ - DMA2D_Periph_Req_Type srcPeriph; /*!< Source peripheral select */ - DMA2D_Periph_Req_Type dstPeriph; /*!< Destination peripheral select */ -} DMA2D_Channel_Cfg_Type; - -/** - * @brief DMA2D configuration Structure definition - */ -typedef struct -{ - uint16_t srcCntX; /*!< Source x count */ - uint16_t srcCntY; /*!< Source y count */ - int32_t srcIncrX; /*!< Source x increment */ - int32_t srcIncrY; /*!< Source y increment */ - uint16_t dstCntX; /*!< Destination x count */ - uint16_t reserve; /*!< Reserved */ - int32_t dstIncrX; /*!< Destination x increment */ - int32_t dstIncrY; /*!< Destination y increment */ -} DMA2D_Cfg_Type; - -/** - * @brief DMA2D LLI control structure type definition - */ -typedef struct -{ - uint32_t srcDmaAddr; /*!< Source address of DMA2D transfer */ - uint32_t destDmaAddr; /*!< Destination address of DMA2D transfer */ - uint32_t nextLLI; /*!< Next LLI address */ - struct DMA2D_Control_Reg dmaCtrl; /*!< DMA2D transaction control */ - DMA2D_Cfg_Type dma2dCfg; /*!< DMA2D configuration */ -} DMA2D_LLI_Ctrl_Type; - -/** - * @brief DMA2D LLI configuration structure type definition - */ -typedef struct -{ - DMA2D_Trans_Dir_Type dir; /*!< Transfer dir control. 0: Memory to Memory, 1: Memory to peripheral, 2: Peripheral to memory */ - DMA2D_Periph_Req_Type srcPeriph; /*!< Source peripheral select */ - DMA2D_Periph_Req_Type dstPeriph; /*!< Destination peripheral select */ -} DMA2D_LLI_Cfg_Type; - -/** - * @brief DMA2D LLI Ping-Pong Buf definition - */ -typedef struct -{ - uint8_t idleIndex; /*!< Index Idle lliListHeader */ - uint8_t dmaId; /*!< DMA2D ID used */ - uint8_t dmaChan; /*!< DMA2D LLI Channel used */ - DMA2D_LLI_Ctrl_Type *lliListHeader[2]; /*!< Ping-Pong BUf List Header */ - void (*onTransCompleted)(DMA2D_LLI_Ctrl_Type *); /*!< Completed Transmit One List Callback Function */ -} DMA2D_LLI_PP_Buf; - -/** - * @brief DMA2D LLI Ping-Pong Structure definition - */ -typedef struct -{ - uint8_t pingpongIndex; /*!< Ping or Pong Trigger TC */ - uint8_t dmaId; /*!< DMA2D ID used */ - uint8_t dmaChan; /*!< DMA2D LLI Channel used */ - struct DMA2D_Control_Reg dmaCtrlRegVal; /*!< DMA2D Basic Pararmeter */ - DMA2D_LLI_Cfg_Type *lliCfg; /*!< LLI Config parameter */ - uint32_t operatePeriphAddr; /*!< Operate Peripheral register address */ - uint32_t pingpongBufAddr[2]; /*!< Ping-Pong addr */ -} DMA2D_LLI_PP_Struct; - -/** - * @brief DMA2D picture configure definition - */ -typedef struct -{ - DMA2D_Trans_Width_Type transWidth; /*!< Transfer width */ - uint32_t pixWidth; /*!< Pixel width, unit: byte */ - uint32_t srcAddr; /*!< Source address */ - uint32_t srcWidth; /*!< Source picture width */ - uint32_t srcX0; /*!< Source start x */ - uint32_t srcY0; /*!< Source start y */ - uint32_t srcX1; /*!< Source stop x */ - uint32_t srcY1; /*!< Source stop y */ - uint32_t dstAddr; /*!< Destination address */ - uint32_t dstWidth; /*!< Destination width */ - uint32_t dstX0; /*!< Destination start x */ - uint32_t dstY0; /*!< Destination start y */ -} DMA2D_Picture_Cfg_Type; - -/*@} end of group DMA2D_Public_Types */ - -/** @defgroup DMA2D_Public_Constants - * @{ - */ - -/** @defgroup DMA2D_ID_TYPE - * @{ - */ -#define IS_DMA2D_ID_TYPE(type) (((type) == DMA2D0_ID) || \ - ((type) == DMA2D_ID_MAX)) - -/** @defgroup DMA2D_ENDIAN_TYPE - * @{ - */ -#define IS_DMA2D_ENDIAN_TYPE(type) (((type) == DMA2D_LITTLE_ENDIAN) || \ - ((type) == DMA2D_BIG_ENDIAN)) - -/** @defgroup DMA2D_SYNC_LOGIC_TYPE - * @{ - */ -#define IS_DMA2D_SYNC_LOGIC_TYPE(type) (((type) == DMA2D_SYNC_LOGIC_ENABLE) || \ - ((type) == DMA2D_SYNC_LOGIC_DISABLE)) - -/** @defgroup DMA2D_TRANS_WIDTH_TYPE - * @{ - */ -#define IS_DMA2D_TRANS_WIDTH_TYPE(type) (((type) == DMA2D_TRNS_WIDTH_8BITS) || \ - ((type) == DMA2D_TRNS_WIDTH_16BITS) || \ - ((type) == DMA2D_TRNS_WIDTH_32BITS)) - -/** @defgroup DMA2D_TRANS_DIR_TYPE - * @{ - */ -#define IS_DMA2D_TRANS_DIR_TYPE(type) (((type) == DMA2D_TRNS_M2M) || \ - ((type) == DMA2D_TRNS_M2P) || \ - ((type) == DMA2D_TRNS_P2M) || \ - ((type) == DMA2D_TRNS_P2P)) - -/** @defgroup DMA2D_BURST_SIZE_TYPE - * @{ - */ -#define IS_DMA2D_BURST_SIZE_TYPE(type) (((type) == DMA2D_BURST_SIZE_1) || \ - ((type) == DMA2D_BURST_SIZE_4) || \ - ((type) == DMA2D_BURST_SIZE_8) || \ - ((type) == DMA2D_BURST_SIZE_16)) - -/** @defgroup DMA2D_PERIPH_REQ_TYPE - * @{ - */ -#define IS_DMA2D_PERIPH_REQ_TYPE(type) (((type) == DMA2D_REQ_UART0_RX) || \ - ((type) == DMA2D_REQ_UART0_TX) || \ - ((type) == DMA2D_REQ_UART1_RX) || \ - ((type) == DMA2D_REQ_UART1_TX) || \ - ((type) == DMA2D_REQ_UART2_RX) || \ - ((type) == DMA2D_REQ_UART2_TX) || \ - ((type) == DMA2D_REQ_I2C0_RX) || \ - ((type) == DMA2D_REQ_I2C0_TX) || \ - ((type) == DMA2D_REQ_IR_TX) || \ - ((type) == DMA2D_REQ_GPIO) || \ - ((type) == DMA2D_REQ_SPI0_RX) || \ - ((type) == DMA2D_REQ_SPI0_TX) || \ - ((type) == DMA2D_REQ_AUDIO_RX) || \ - ((type) == DMA2D_REQ_AUDIO_TX) || \ - ((type) == DMA2D_REQ_GPADC0) || \ - ((type) == DMA2D_REQ_GPADC1) || \ - ((type) == DMA2D_REQ_USB_EP0) || \ - ((type) == DMA2D_REQ_USB_EP1) || \ - ((type) == DMA2D_REQ_USB_EP2) || \ - ((type) == DMA2D_REQ_USB_EP3) || \ - ((type) == DMA2D_REQ_USB_EP4) || \ - ((type) == DMA2D_REQ_USB_EP5) || \ - ((type) == DMA2D_REQ_USB_EP6) || \ - ((type) == DMA2D_REQ_USB_EP7) || \ - ((type) == DMA2D_REQ_UART3_RX) || \ - ((type) == DMA2D_REQ_UART3_TX) || \ - ((type) == DMA2D_REQ_SPI1_RX) || \ - ((type) == DMA2D_REQ_SPI1_TX) || \ - ((type) == DMA2D_REQ_I2C1_RX) || \ - ((type) == DMA2D_REQ_I2C1_TX) || \ - ((type) == DMA2D_REQ_I2S_TX) || \ - ((type) == DMA2D_REQ_I2S_RX) || \ - ((type) == DMA2D_REQ_DBI_TX) || \ - ((type) == DMA2D_REQ_NONE)) - -/** @defgroup DMA2D_CHAN_TYPE - * @{ - */ -#define IS_DMA2D_CHAN_TYPE(type) (((type) == DMA2D_CH0) || \ - ((type) == DMA2D_CH1) || \ - ((type) == DMA2D_CH_MAX)) - -/** @defgroup DMA2D_LLI_PP_INDEX_TYPE - * @{ - */ -#define IS_DMA2D_LLI_PP_INDEX_TYPE(type) (((type) == DMA2D_PING_INDEX) || \ - ((type) == DMA2D_PONG_INDEX)) - -/** @defgroup DMA2D_INT_TYPE - * @{ - */ -#define IS_DMA2D_INT_TYPE(type) (((type) == DMA2D_INT_TCOMPLETED) || \ - ((type) == DMA2D_INT_ALL)) - -/** @defgroup DMA2D_ROTATE_TYPE - * @{ - */ -#define IS_DMA2D_ROTATE_TYPE(type) (((type) == DMA2D_ROTATE_DEGREE_90) || \ - ((type) == DMA2D_ROTATE_DEGREE_180) || \ - ((type) == DMA2D_ROTATE_DEGREE_270)) - -/** @defgroup DMA2D_FOLD_TYPE - * @{ - */ -#define IS_DMA2D_FOLD_TYPE(type) (((type) == DMA2D_FOLD_LEFT_RIGHT) || \ - ((type) == DMA2D_FOLD_UP_DOWN)) - -/** @defgroup DMA2D_COLOR_KEY_TYPE - * @{ - */ -#define IS_DMA2D_COLOR_KEY_TYPE(type) (((type) == DMA2D_COLOR_KEY_8BIT) || \ - ((type) == DMA2D_COLOR_KEY_16BIT) || \ - ((type) == DMA2D_COLOR_KEY_24BIT) || \ - ((type) == DMA2D_COLOR_KEY_32BIT)) - -/*@} end of group DMA2D_Public_Constants */ - -/** @defgroup DMA2D_Public_Macros - * @{ - */ -#define DMA2D_PINC_ENABLE 1 -#define DMA2D_PINC_DISABLE 0 -#define DMA2D_MINC_ENABLE 1 -#define DMA2D_MINC_DISABLE 0 - -/*@} end of group DMA2D_Public_Macros */ - -/** @defgroup DMA2D_Public_Functions - * @{ - */ - -/** - * @brief DMA2D Functions - */ -#ifndef BFLB_USE_HAL_DRIVER -void DMA2D_INT0_IRQHandler(void); -void DMA2D_INT1_IRQHandler(void); -#endif -void DMA2D_Enable(DMA2D_ID_Type dmaId); -void DMA2D_Disable(DMA2D_ID_Type dmaId); -void DMA2D_Init(DMA2D_ID_Type dmaId, uint8_t ch, DMA2D_Cfg_Type *cfg); -void DMA2D_Channel_Init(DMA2D_ID_Type dmaId, DMA2D_Channel_Cfg_Type *chCfg); -void DMA2D_DeInit(DMA2D_ID_Type dmaId); -void DMA2D_Channel_Update_SrcMemcfg(DMA2D_ID_Type dmaId, uint8_t ch, uint32_t memAddr, uint32_t len); -void DMA2D_Channel_Update_DstMemcfg(DMA2D_ID_Type dmaId, uint8_t ch, uint32_t memAddr, uint32_t len); -uint32_t DMA2D_Channel_TranferSize(DMA2D_ID_Type dmaId, uint8_t ch); -BL_Sts_Type DMA2D_Channel_Is_Busy(DMA2D_ID_Type dmaId, uint8_t ch); -void DMA2D_Channel_Enable(DMA2D_ID_Type dmaId, uint8_t ch); -void DMA2D_Channel_Disable(DMA2D_ID_Type dmaId, uint8_t ch); -void DMA2D_LLI_Init(DMA2D_ID_Type dmaId, uint8_t ch, DMA2D_LLI_Cfg_Type *lliCfg); -void DMA2D_LLI_Update(DMA2D_ID_Type dmaId, uint8_t ch, uint32_t LLI); -uint32_t DMA2D_LLI_Get_Counter(DMA2D_ID_Type dmaId, uint8_t ch); -void DMA2D_IntMask(DMA2D_ID_Type dmaId, uint8_t ch, DMA2D_INT_Type intType, BL_Mask_Type intMask); -void DMA2D_LLI_PpBuf_Start_New_Transmit(DMA2D_LLI_PP_Buf *dmaPpBuf); -DMA2D_LLI_Ctrl_Type *DMA2D_LLI_PpBuf_Remove_Completed_List(DMA2D_LLI_PP_Buf *dmaPpBuf); -void DMA2D_LLI_PpBuf_Append(DMA2D_LLI_PP_Buf *dmaPpBuf, DMA2D_LLI_Ctrl_Type *dmaLliList); -void DMA2D_LLI_PpBuf_Destroy(DMA2D_LLI_PP_Buf *dmaPpBuf); -void DMA2D_Int_Callback_Install(DMA2D_ID_Type dmaId, DMA2D_Chan_Type dmaChan, DMA2D_INT_Type intType, intCallback_Type *cbFun); -void DMA2D_LLI_PpStruct_Start(DMA2D_LLI_PP_Struct *dmaPpStruct); -void DMA2D_LLI_PpStruct_Stop(DMA2D_LLI_PP_Struct *dmaPpStruct); -BL_Err_Type DMA2D_LLI_PpStruct_Init(DMA2D_LLI_PP_Struct *dmaPpStruct); -BL_Err_Type DMA2D_LLI_PpStruct_Set_Transfer_Len(DMA2D_LLI_PP_Struct *dmaPpStruct, - uint16_t Ping_Transfer_len, uint16_t Pong_Transfer_len); -void DMA2D_Picture_Translate_Calculate(DMA2D_Picture_Cfg_Type *cfg, DMA2D_LLI_Ctrl_Type *lliCfg); -void DMA2D_Picture_Rotate_Calculate(DMA2D_Picture_Cfg_Type *cfg, DMA2D_LLI_Ctrl_Type *lliCfg, DMA2D_Rotate_Type rotate); -void DMA2D_Picture_Fold_Calculate(DMA2D_Picture_Cfg_Type *cfg, DMA2D_LLI_Ctrl_Type *lliCfg, DMA2D_Fold_Type fold); -void DMA2D_Picture_Fill_Calculate(DMA2D_Picture_Cfg_Type *cfg, DMA2D_LLI_Ctrl_Type *lliCfg); -void DMA2D_Picture_Transfer_Start(DMA2D_ID_Type dmaId, uint8_t ch, DMA2D_LLI_Ctrl_Type *lliCfg); -void DMA2D_Color_Key_Set(DMA2D_ID_Type dmaId, uint8_t ch, DMA2D_Color_Key_Type keyType, uint32_t keyValue); -void DMA2D_Color_Key_Enable(DMA2D_ID_Type dmaId, uint8_t ch); -void DMA2D_Color_Key_Disable(DMA2D_ID_Type dmaId, uint8_t ch); -/*@} end of group DMA2D_Public_Functions */ - -/*@} end of group DMA2D */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_DMA2D_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dsi.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dsi.h deleted file mode 100644 index 7e8ecf2a6c..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dsi.h +++ /dev/null @@ -1,382 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_dsi.h - * @version V1.0 - * @date 2021-04-22 - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2021 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_DSI_H__ -#define __BL808_DSI_H__ - -#include "dsi_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup DSI - * @{ - */ - -/** @defgroup DSI_Public_Types - * @{ - */ - -/** - * @brief DSI port type definition - */ -typedef enum { - DSI0_ID, /*!< DSI0 port define */ - DSI_ID_MAX, /*!< DSI max ID define */ -} DSI_ID_Type; - -/** - * @brief DSI interrupt type definition - */ -typedef enum { - DSI_INT_ESCAPE_TX_END = 0x01, /*!< DSI escape tx end interrupt */ - DSI_INT_LPDT_RX_END = 0x02, /*!< DSI lpdt rx end interrupt */ - DSI_INT_ULPS_RX_END = 0x04, /*!< DSI ulps rx end interrupt */ - DSI_INT_TRIGGER0_RX_END = 0x08, /*!< DSI trigger0 rx end interrupt */ - DSI_INT_TRIGGER1_RX_END = 0x10, /*!< DSI trigger1 rx end interrupt */ - DSI_INT_TRIGGER2_RX_END = 0x20, /*!< DSI trigger2 rx end interrupt */ - DSI_INT_TRIGGER3_RX_END = 0x40, /*!< DSI trigger3 rx end interrupt */ - DSI_INT_TX_FIFO_READY = 0x80, /*!< DSI tx fifo ready interrupt */ - DSI_INT_RX_FIFO_READY = 0x100, /*!< DSI rx fifo ready interrupt */ - DSI_INT_DATA_OVERRUN_ERR = 0x200, /*!< DSI data overrun error interrupt */ - DSI_INT_DATA_UNDERRUN_ERR = 0x400, /*!< DSI data underrun error interrupt */ - DSI_INT_PIXEL_COUNT_SMALL_ERR = 0x800, /*!< DSI pixel count too small error interrupt */ - DSI_INT_PIXEL_COUNT_LARGE_ERR = 0x1000, /*!< DSI pixel count too large error interrupt */ - DSI_INT_FIFO_ERROR = 0x2000, /*!< DSI fifo error interrupt */ - DSI_INT_ALL = 0x3FFF, /*!< All interrupt */ - DSI_INT_COUNT = 0x0E, /*!< Interrupt count */ -} DSI_INT_Type; - -/** - * @brief DSI fifo error type definition - */ -typedef enum { - DSI_FIFO_ERR_TX_OVERFLOW = 0x01, /*!< DSI tx fifo overflow */ - DSI_FIFO_ERR_TX_UNDERFLOW = 0x02, /*!< DSI tx fifo underflow */ - DSI_FIFO_ERR_RX_OVERFLOW = 0x04, /*!< DSI rx fifo overflow */ - DSI_FIFO_ERR_RX_UNDERFLOW = 0x08, /*!< DSI rx fifo underflow */ -} DSI_FIFO_Error_Type; - -/** - * @brief DSI lane type definition - */ -typedef enum { - DSI_LANE_DATA0 = 0x01, /*!< Data0 */ - DSI_LANE_DATA1 = 0x02, /*!< Data1 */ - DSI_LANE_DATA2 = 0x04, /*!< Data2 */ - DSI_LANE_DATA3 = 0x08, /*!< Data3 */ - DSI_LANE_CLOCK = 0x010, /*!< Clcok */ -} DSI_Lane_Type; - -/** - * @brief DSI data type definition - */ -typedef enum { - DSI_DATA_YUV422 = 0x2c, /*!< YUV422, 8-bit */ - DSI_DATA_RGB565 = 0x0e, /*!< RGB565 */ - DSI_DATA_RGB666 = 0x2e, /*!< RGB666, lossely packed */ - DSI_DATA_RGB888 = 0x3e, /*!< RGB888 */ -} DSI_Data_Type; - -/** - * @brief DSI lane number type definition - */ -typedef enum { - DSI_LANE_NUMBER_1, /*!< 1-lane TX */ - DSI_LANE_NUMBER_2, /*!< 2-lane TX */ - DSI_LANE_NUMBER_4, /*!< 4-lane TX */ -} DSI_Lane_Number_Type; - -/** - * @brief DSI lane order type definition - */ -typedef enum { - DSI_LANE_ORDER_3210, /*!< Lane 3, 2, 1, 0 */ - DSI_LANE_ORDER_2130, /*!< Lane 2, 1, 3, 0 */ - DSI_LANE_ORDER_1320, /*!< Lane 1, 3, 2, 0 */ - DSI_LANE_ORDER_3120, /*!< Lane 3, 1, 2, 0 */ -} DSI_Lane_Order_Type; - -/** - * @brief DSI lane state type definition - */ -typedef enum { - DSI_LANE_STAT_NORMAL = 0x00, /*!< Status normal */ - DSI_LANE_STAT_STOP = 0x01, /*!< Status stop */ - DSI_LANE_STAT_BRIDGE = 0x02, /*!< Status bridge changing */ - DSI_LANE_STAT_ULP = 0x04, /*!< Status ultra low power */ - DSI_LANE_STAT_HS=0x08, /*!< Status high speed */ -} DSI_Lane_State_Type; - -/** - * @brief DSI clock lane option type definition - */ -typedef enum { - DSI_CLOCK_LANE_OPT_ULP_ENTER = 0x01, /*!< Clock lane low power enter */ - DSI_CLOCK_LANE_OPT_ULP_EXIT = 0x02, /*!< Clock lane low power exit */ - DSI_CLOCK_LANE_OPT_HS_REQ = 0x04, /*!< Clock lane hs request */ - DSI_CLOCK_LANE_OPT_HS_EXIT = 0x08, /*!< Clock lane hs exit */ -} DSI_Clock_Lane_Opt_Type; - -/** - * @brief Escape mode type definition - */ -typedef enum { - DSI_ESCAPSE_TYPE_LPDT, /*!< Escape type:LPDT */ - DSI_ESCAPSE_TYPE_TRIGGER, /*!< Escape type:TRIGGER */ - DSI_ESCAPSE_TYPE_ULPS, /*!< Escape type:UPLS */ -} DSI_Escape_Type; - -/** - * @brief HS sync mode type definition - */ -typedef enum { - DSI_HS_SYNC_EVENT_MODE, /*!< HS sync event mode */ - DSI_HS_SYNC_PULSE_MODE, /*!< HS sync pulse mode */ -} DSI_HS_Sync_Type; - -/** - * @brief DSI configuration strcut definition - */ -typedef struct -{ - uint8_t virtualChan; /*!< DSI virtual channels */ - DSI_Lane_Number_Type laneNum; /*!< DSI lane numbers */ - DSI_Lane_Order_Type laneOrder; /*!< DSI lane order */ - DSI_Data_Type dataType; /*!< DSI data type */ - DSI_HS_Sync_Type syncType; /*!< DSI HS sync mode select */ - uint8_t vsa; /*!< HS vertical sync active width */ - uint8_t vfp; /*!< HS vertical front porch width */ -} DSI_CFG_Type; - -/** - * @brief DSI configuration strcut definition - */ -typedef struct -{ - uint8_t virtualChan; /*!< DSI LPDT msg virtual channels */ - uint8_t dataType; /*!< DSI LPDT msg data type */ - uint8_t flag; /*!< DSI LPDT msg flag */ - uint16_t tx_len; /*!< DSI LPDT msg len */ - const uint8_t *tx_buf; /*!< DSI LPDT msg buffer */ - uint16_t rx_len; /*!< DSI LPDT rx len */ - uint8_t *rx_buf; /*!< DSI LPDT rx buffer */ -} DSI_LPDT_MSG_Type; - -/** - * @brief DSI DPHY configuration strcut definition - */ -typedef struct -{ - uint8_t time_clk_zero; /*!< Clock lane zero time */ - uint8_t time_clk_trail; /*!< Clock lane trail time */ - uint8_t time_clk_exit; /*!< Clock lane exit time */ - uint8_t time_data_prepare; /*!< Data lane prepare time*/ - uint8_t time_data_zero; /*!< Data lane zero time*/ - uint8_t time_data_trail; /*!< Data lane trail time */ - uint8_t time_data_exit; /*!< Data lane exit time */ - uint8_t time_lpx; /*!< Low power time */ - uint8_t time_req_ready; /*!< HS request time */ - uint8_t time_ta_get; /*!< Bus turn around get time */ - uint8_t time_ta_go; /*!< Bus turn around go time */ - uint32_t time_wakeup; /*!< Low power wake up time */ -} DSI_DPhy_CFG_Type; - -/** - * @brief DSI FIFO configuration structure type definition - */ -typedef struct -{ - uint8_t txFifoDmaThreshold; /*!< TX FIFO threshold, dma tx request will not be asserted if tx fifo count is less than this value */ - uint8_t rxFifoDmaThreshold; /*!< RX FIFO threshold, dma rx request will not be asserted if rx fifo count is less than this value */ - BL_Fun_Type txFifoDmaEnable; /*!< Enable or disable tx dma req/ack interface */ - BL_Fun_Type rxFifoDmaEnable; /*!< Enable or disable rx dma req/ack interface */ -} DSI_FifoCfg_Type; - -/*@} end of group DSI_Public_Types */ - -/** @defgroup DSI_Public_Constants - * @{ - */ - -/** @defgroup DSI_ID_TYPE - * @{ - */ -#define IS_DSI_ID_TYPE(type) (((type) == DSI0_ID) || \ - ((type) == DSI_ID_MAX)) - -/** @defgroup DSI_INT_TYPE - * @{ - */ -#define IS_DSI_INT_TYPE(type) (((type) == DSI_INT_ESCAPE_TX_END) || \ - ((type) == DSI_INT_LPDT_RX_END) || \ - ((type) == DSI_INT_ULPS_RX_END) || \ - ((type) == DSI_INT_TRIGGER0_RX_END) || \ - ((type) == DSI_INT_TRIGGER1_RX_END) || \ - ((type) == DSI_INT_TRIGGER2_RX_END) || \ - ((type) == DSI_INT_TRIGGER3_RX_END) || \ - ((type) == DSI_INT_TX_FIFO_READY) || \ - ((type) == DSI_INT_RX_FIFO_READY) || \ - ((type) == DSI_INT_DATA_OVERRUN_ERR) || \ - ((type) == DSI_INT_DATA_UNDERRUN_ERR) || \ - ((type) == DSI_INT_PIXEL_COUNT_SMALL_ERR) || \ - ((type) == DSI_INT_PIXEL_COUNT_LARGE_ERR) || \ - ((type) == DSI_INT_FIFO_ERROR) || \ - ((type) == DSI_INT_ALL)) - -/** @defgroup DSI_FIFO_ERROR_TYPE - * @{ - */ -#define IS_DSI_FIFO_ERROR_TYPE(type) (((type) == DSI_FIFO_ERR_TX_OVERFLOW) || \ - ((type) == DSI_FIFO_ERR_TX_UNDERFLOW) || \ - ((type) == DSI_FIFO_ERR_RX_OVERFLOW) || \ - ((type) == DSI_FIFO_ERR_RX_UNDERFLOW)) - -/** @defgroup DSI_LANE_TYPE - * @{ - */ -#define IS_DSI_LANE_TYPE(type) (((type) == DSI_LANE_DATA0) || \ - ((type) == DSI_LANE_DATA1) || \ - ((type) == DSI_LANE_DATA2) || \ - ((type) == DSI_LANE_DATA3) || \ - ((type) == DSI_LANE_CLOCK)) - -/** @defgroup DSI_DATA_TYPE - * @{ - */ -#define IS_DSI_DATA_TYPE(type) (((type) == DSI_DATA_YUV422) || \ - ((type) == DSI_DATA_RGB565) || \ - ((type) == DSI_DATA_RGB666) || \ - ((type) == DSI_DATA_RGB888)) - -/** @defgroup DSI_LANE_NUMBER_TYPE - * @{ - */ -#define IS_DSI_LANE_NUMBER_TYPE(type) (((type) == DSI_LANE_NUMBER_1) || \ - ((type) == DSI_LANE_NUMBER_2) || \ - ((type) == DSI_LANE_NUMBER_4)) - -/** @defgroup DSI_LANE_ORDER_TYPE - * @{ - */ -#define IS_DSI_LANE_ORDER_TYPE(type) (((type) == DSI_LANE_ORDER_3210) || \ - ((type) == DSI_LANE_ORDER_2130) || \ - ((type) == DSI_LANE_ORDER_1320) || \ - ((type) == DSI_LANE_ORDER_3120)) - -/** @defgroup DSI_LANE_STATE_TYPE - * @{ - */ -#define IS_DSI_LANE_STATE_TYPE(type) (((type) == DSI_LANE_STAT_NORMAL) || \ - ((type) == DSI_LANE_STAT_STOP) || \ - ((type) == DSI_LANE_STAT_BRIDGE) || \ - ((type) == DSI_LANE_STAT_ULP) || \ - ((type) == DSI_LANE_STAT_HS)) - -/** @defgroup DSI_CLOCK_LANE_OPT_TYPE - * @{ - */ -#define IS_DSI_CLOCK_LANE_OPT_TYPE(type) (((type) == DSI_CLOCK_LANE_OPT_ULP_ENTER) || \ - ((type) == DSI_CLOCK_LANE_OPT_ULP_EXIT) || \ - ((type) == DSI_CLOCK_LANE_OPT_HS_REQ) || \ - ((type) == DSI_CLOCK_LANE_OPT_HS_EXIT)) - -/** @defgroup DSI_ESCAPE_TYPE - * @{ - */ -#define IS_DSI_ESCAPE_TYPE(type) (((type) == DSI_ESCAPSE_TYPE_LPDT) || \ - ((type) == DSI_ESCAPSE_TYPE_TRIGGER) || \ - ((type) == DSI_ESCAPSE_TYPE_ULPS)) - -/** @defgroup DSI_HS_SYNC_TYPE - * @{ - */ -#define IS_DSI_HS_SYNC_TYPE(type) (((type) == DSI_HS_SYNC_EVENT_MODE) || \ - ((type) == DSI_HS_SYNC_PULSE_MODE)) - -/*@} end of group DSI_Public_Constants */ - -/** @defgroup DSI_Public_Macros - * @{ - */ -#define DSI_TX_FIFO_SIZE 4 -#define DSI_RX_FIFO_SIZE 4 -/*@} end of group DSI_Public_Macros */ - -/** @defgroup DSI_Public_Functions - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -void DSI_IRQHandler(void); -#endif -void DSI_Init(DSI_ID_Type disId, DSI_CFG_Type *cfg); -void DSI_Deinit(DSI_ID_Type disId); -void DSI_Enable(DSI_ID_Type disId); -void DSI_Disable(DSI_ID_Type disId); -void DSI_IntMask(DSI_ID_Type dsiId, DSI_INT_Type intType, BL_Mask_Type intMask); -void DSI_IntClear(DSI_ID_Type dsiId, DSI_INT_Type intType); -void DSI_IntEnable(DSI_ID_Type dsiId, DSI_INT_Type intType); -DSI_INT_Type DSI_IntGet(DSI_ID_Type dsiId); -void DSI_Set_Line_Buffer_Threshold(DSI_ID_Type dsiId, uint32_t frameWidth, uint32_t dvpTsrcClock, uint32_t dsiClock, \ - DSI_Data_Type dataType, DSI_Lane_Number_Type laneNumber); -void DSI_Set_VSA_VFP(DSI_ID_Type dsiId, uint8_t vsa, uint8_t vfp); -void DSI_PHY_Reset(DSI_ID_Type dsiId); -void DSI_PHY_Config(DSI_ID_Type dsiId, DSI_DPhy_CFG_Type *phyCfg); -void DSI_PHY_Reinit_Data_Lanes(DSI_ID_Type dsiId, DSI_Lane_Type lanes); -void DSI_PHY_Enable_Lanes(DSI_ID_Type dsiId, DSI_Lane_Type lanes); -void DSI_PHY_Disable_Lanes(DSI_ID_Type dsiId, DSI_Lane_Type lanes); -void DSI_PHY_Data_Lane0_TurnAround(DSI_ID_Type dsiId); -void DSI_PHY_Stop_Data_Lanes(DSI_ID_Type dsiId, DSI_Lane_Type lanes); -void DSI_PHY_Get_Lanes_State(DSI_ID_Type dsiId, DSI_Lane_Type lane, DSI_Lane_State_Type *state); -void DSI_PHY_Set_Clock_Lane(DSI_ID_Type dsiId, DSI_Clock_Lane_Opt_Type opt); -void DSI_PHY_HS_Mode_Start(DSI_ID_Type dsiId); -void DSI_PHY_HS_Mode_Stop(DSI_ID_Type dsiId); -BL_Err_Type DSI_FifoConfig(DSI_ID_Type dsiId, DSI_FifoCfg_Type *fifoCfg); -BL_Err_Type DSI_LPDT_Send_Short_Packet(DSI_ID_Type dsiId, DSI_LPDT_MSG_Type *msg); -BL_Err_Type DSI_LPDT_Send_Long_Packet(DSI_ID_Type dsiId, DSI_LPDT_MSG_Type *msg); -BL_Err_Type DSI_LPDT_Recv_Packet(DSI_ID_Type dsiId, DSI_LPDT_MSG_Type *msg); -BL_Err_Type DSI_Send_Trigger_Command(DSI_ID_Type dsiId, uint8_t cmd); -BL_Err_Type DSI_Send_ULPS_Command(DSI_ID_Type dsiId); -BL_Err_Type DSI_Exit_ULPS(DSI_ID_Type dsiId); - -/*@} end of group DSI_Public_Functions */ - -/*@} end of group DSI */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_DSI_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dsp2.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dsp2.h deleted file mode 100644 index 3c3a3b43c8..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dsp2.h +++ /dev/null @@ -1,689 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_dsp2.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_DSP2_H__ -#define __BL808_DSP2_H__ - -#include -#include "bl808_common.h" -#include "dsp2_tg_reg.h" -#include "dsp2_front_reg.h" -#include "dsp2_back_reg.h" -#include "dsp2_blback_reg.h" -#include "dsp2_middle_reg.h" -#include "dsp2_middle3_reg.h" -#include "dsp2_middle4_reg.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup DSP2 - * @{ - */ - -/** @defgroup DSP2_Public_Types - * @{ - */ - -#define DSP2_EE_LUMA_WEIGHT_NUM (32) -#define DSP2_AWB2_STA_Y_NUM (5) -#define DSP2_AWB2_STA_C_NUM (8) -#define CCM_COEF_NUM (9) -#define GAMMA_COEF_NUM (256) - -/** - * @brief Bayer pattern - */ -typedef enum { - BAYER_PATTERN_RG = 0, - BAYER_PATTERN_GR, - BAYER_PATTERN_BG, - BAYER_PATTERN_GB, -} BAYER_PATTERN_E; - -/** - * @brief LSC coefficient - */ -typedef enum { - LSC_COEF_A = 0, - LSC_COEF_B = 1, - LSC_COEF_C = 2, - LSC_COEF_D = 3, - LSC_COEF_E = 4, - LSC_COEF_G = 5, - LSC_COEF_NUM = 6, -} DSP2_LSC_COEF_E; - -/** - * @brief DSP2 sync mode type definition - */ -typedef enum { - DSP2_SYNC_MODE_INPUT = 0, - DSP2_SYNC_MODE_OUTPUT, - DSP2_SYNC_MODE_OUTPUT_INPUT, - DSP2_SYNC_MODE_INPUT_VBLANK_NO_TOGGLE, -} DSP2_SYNC_MODE_TYPE; - -/** - * @brief Color correction matrix coefficient - */ -typedef enum { - DSP2_CCM_11 = 0, - DSP2_CCM_12 = 1, - DSP2_CCM_13 = 2, - DSP2_CCM_21 = 3, - DSP2_CCM_22 = 4, - DSP2_CCM_23 = 5, - DSP2_CCM_31 = 6, - DSP2_CCM_32 = 7, - DSP2_CCM_33 = 8, -} DSP2_CCM_COEF_TYPE_E; - -/** - * @brief YUV conversion mode - */ -typedef enum { - DSP2_YUV_CONV_FULL_SCALE = 0, - DSP2_YUV_CONV_BT601, -} DSP2_YUV_CONV_TYPE; - -/** - * @brief Defect correction enhance state - */ -typedef enum { - DSP2_DPC_Enhance1 = 0, - DSP2_DPC_Enhance2, - DSP2_DPC_Enhance3, - DSP2_DPC_Enhance_Num, -} DSP2_DPC_ENHANCE_TYPE; - -/** - * @brief Defect correction threadhold - */ -typedef enum { - DSP2_DPC_th1 = 0, - DSP2_DPC_th2, - DSP2_DPC_th3, - DSP2_DPC_th4, - DSP2_DPC_th5, - DSP2_DPC_th_Num, -} DSP2_DPC_THRESHOLD_TYPE; - -/** - * @brief AE grid data type - */ -typedef enum { - AE_GRID_DATA_RGB = 0, - AE_GRID_DATA_Y = 1, -} AE_GRID_DATA_TYPE_E; - -/** - * @brief AWB grid data type - */ -typedef enum { - AWB_GRID_DATA_RG = 0, - AWB_GRID_DATA_B = 1, -} AWB_GRID_DATA_TYPE_E; - -/** - * @brief Image size - */ -typedef struct -{ - uint32_t width; - uint32_t height; -} BL_Img_Size_T; - -/** - * @brief RGB sum - */ -typedef struct blRGB_SUM_S { - uint32_t r_sum; - uint32_t g_sum; - uint32_t b_sum; -} RGB_SUM_S; - -/** - * @brief R,Gr,Gb,B black level - */ -typedef struct blDSP2_CLAMP_S { - int clamp_r; - int clamp_gr; - int clamp_gb; - int clamp_b; -} DSP2_CLAMP_S; - -/** - * @brief Color correction matrix coefficient group - */ -typedef struct blDSP2_CCM_COEF_GROUP_S { - int ccm_coef[CCM_COEF_NUM]; -} DSP2_CCM_COEF_S; - -/** - * @brief Gamma curve type - */ -typedef struct blDSP2_GAMMA_COEF_GROUP_S { - uint16_t curve_coef[GAMMA_COEF_NUM]; -} DSP2_Gamma_Curve_Type; - -/** - * @brief Saturation - */ -typedef struct blDSP2_SATURATION_S { - uint32_t saturation_cb; - uint32_t saturation_cr; -} DSP2_SATURATION_S; - -/** - * @brief Defect correction enhance state group - */ -typedef struct -{ - BL_Fun_Type data[DSP2_DPC_Enhance_Num]; -} DSP2_DPC_ENHANCE_GROUP_TYPE; - -/** - * @brief Defect correction threadhold group - */ -typedef struct -{ - int data[DSP2_DPC_th_Num]; -} DSP2_DPC_THRESHOLD_GROUP_TYPE; - -/* - Lens Shading Coef - Acoef range: -4194304-4194303 - Bcoef range: -4096-4095 - Ccoef range: 0-255 - Dcoef range: -4194304-4194303 - Ecoef range: -4096-4095 - Gcoef range: -4194304-4194303 -*/ - -/** - * @brief BNR threshold type - */ -typedef struct -{ - uint16_t th_base_r; /*!< r/w, shadow, 10'b, range: 0 ~ (2 ^ TH_BW - 1) */ - uint16_t th_base_g; /*!< r/w, shadow, 10'b, range: 0 ~ (2 ^ TH_BW - 1) */ - uint16_t th_base_b; /*!< r/w, shadow, 10'b, range: 0 ~ (2 ^ TH_BW - 1) */ - uint16_t th_slope_r; /*!< r/w, shadow, 8'b, = TH_SLOPE_PRECISION, range: 0 ~ (2 ^ TH_SLOPE_PRECISION - 1) */ - uint16_t th_slope_g; /*!< r/w, shadow, 8'b, = TH_SLOPE_PRECISION, range: 0 ~ (2 ^ TH_SLOPE_PRECISION - 1) */ - uint16_t th_slope_b; /*!< r/w, shadow, 8'b, = TH_SLOPE_PRECISION, range: 0 ~ (2 ^ TH_SLOPE_PRECISION - 1) */ - uint16_t slope_gain; /*!< r/w, shadow, 6'b, = 2 + SLOPE_GAIN_PRECISION, 2.4 fixed-point, range: 0 ~ (2 ^ 6 - 1) */ -} DSP2_BNR_THRESHOLD_TYPE; - -/** - * @brief BNR fallback type - */ -typedef struct -{ - uint16_t fb_lpf_weight; /*!< r/w, shadow, 5'b, = 1 + LPF_WEIGHT_PRECISION, range: 0 ~ (2 ^ LPF_WEIGHT_PRECISION) */ - uint16_t fb_level; /*!< r/w, shadow, 3'b, = FB_LEVEL_BW, range: 0 ~ (2 ^ FB_LEVEL_BW - 1) */ -} DSP2_BNR_FALLBACK_TYPE; - -/** - * @brief LSC coefficient type - */ -typedef struct -{ - int coef[LSC_COEF_NUM]; -} DSP2_LSC_COEF_TYPE; - -/** - * @brief LSC coefficient group - */ -typedef struct blDSP2_LSC_COEF_S { - DSP2_LSC_COEF_TYPE lsc_coef_r; - DSP2_LSC_COEF_TYPE lsc_coef_g; - DSP2_LSC_COEF_TYPE lsc_coef_b; -} DSP2_LSC_COEF_S; - -/** - * @brief LSC max - */ -typedef struct blDSP2_LSC_MAX_S { - int max_r; - int max_g; - int max_b; -} DSP2_LSC_MAX_S; - -/** - * @brief TG configuration - */ -typedef struct -{ - DSP2_SYNC_MODE_TYPE sync_mode_value; - uint32_t DSP2_clk; - uint32_t pix_clk; - uint16_t fps; - uint16_t total_width; - uint16_t total_height; - uint16_t active_width; - uint16_t active_height; - uint16_t out_width; - uint16_t out_height; -} DSP2_TG_Cfg_Type; - -/** - * @brief AE status configuration - */ -typedef struct _dsp2_ae_stats_conf { - uint16_t roi_start_x; - uint16_t roi_start_y; - uint16_t roi_width; - uint16_t roi_height; - uint16_t img_width; - uint16_t img_height; - uint8_t grid_width; - uint8_t grid_height; - uint8_t grid_num_x; - uint8_t grid_num_y; -} dsp2_ae_stats_conf_t; - -/** - * @brief AE sum - */ -typedef struct _dsp2_ae_sum { - uint32_t r_sum : 8; - uint32_t g_sum : 8; - uint32_t b_sum : 8; - uint32_t reserved_24_31 : 8; - uint32_t y_sum : 8; - uint32_t reserved_8_31 : 24; -} dsp2_ae_sum_t; - -/** - * @brief AWB status configuration - */ -typedef struct _dsp2_awb_stats_conf { - uint16_t roi_start_x; - uint16_t roi_start_y; - uint16_t roi_width; - uint16_t roi_height; - uint16_t img_width; - uint16_t img_height; - uint8_t grid_width; - uint8_t grid_height; - uint8_t grid_num_x; - uint8_t grid_num_y; - uint16_t r_max_thr; - uint16_t r_min_thr; - uint16_t g_max_thr; - uint16_t g_min_thr; - uint16_t b_max_thr; - uint16_t b_min_thr; -} dsp2_awb_stats_conf_t; - -/** - * @brief AWB2 status configuration - */ -typedef struct _dsp2_awb2_stats_conf { - uint16_t stat_x_min; /*!< r/w, shadow, 11'b, range: 0 ~ (width - 1) */ - uint16_t stat_x_max; /*!< r/w, shadow, 11'b, range: 0 ~ (width - 1) */ - uint16_t stat_y_min; /*!< r/w, shadow, 11'b, range: 0 ~ (height - 1) */ - uint16_t stat_y_max; /*!< r/w, shadow, 11'b, range: 0 ~ (height - 1) */ - uint32_t stat_pixel_num; /*!< r/w, shadow, 21'b, = (stat_x_max - stat_x_min + 1) * (stat_y_max - stat_y_min + 1) */ - uint16_t stat_r_gain; /*!< r/w, shadow, 16'b, = 4 + GAIN_PRECISION, 4.12 fixed-point, range: 0 ~ (2 ^ 16 - 1) */ - uint16_t stat_g_gain; /*!< r/w, shadow, 16'b, = 4 + GAIN_PRECISION, 4.12 fixed-point, range: 0 ~ (2 ^ 16 - 1) */ - uint16_t stat_b_gain; /*!< r/w, shadow, 16'b, = 4 + GAIN_PRECISION, 4.12 fixed-point, range: 0 ~ (2 ^ 16 - 1) */ - uint16_t stat_u_gain; /*!< r/w, shadow, 10'b, = 2 + C_GAIN_PRECISION, 2.8 fixed-point, range: 0 ~ (2 ^ 10 - 1) */ - uint16_t stat_v_gain; /*!< r/w, shadow, 10'b, = 2 + C_GAIN_PRECISION, 2.8 fixed-point, range: 0 ~ (2 ^ 10 - 1) */ - uint16_t reserved0; /*!< reserved */ - uint8_t y_th[DSP2_AWB2_STA_Y_NUM]; /*!< r/w, shadow, 8'b, = STAT_PIXEL_BW, range: 0 ~ (2 ^ 8 - 1) */ - uint8_t y_weight[DSP2_AWB2_STA_Y_NUM]; /*!< r/w, shadow, 8'b, = STAT_PIXEL_BW, range: 0 ~ (2 ^ 8 - 1) */ - uint16_t reserved1; /*!< reserved */ - int16_t y_slope[DSP2_AWB2_STA_Y_NUM]; /*!< r/w, shadow, 9'b, = 7 + SLOPE_PRECISION, signed 2's complement, range: -256 ~ +255 */ - uint16_t reserved2; /*!< reserved */ - int8_t u[DSP2_AWB2_STA_C_NUM]; /*!< r/w, shadow, 8'b, = STAT_PIXEL_BW, signed 2's complement, range: -128 ~ +127 */ - int8_t v[DSP2_AWB2_STA_C_NUM]; /*!< r/w, shadow, 8'b, = STAT_PIXEL_BW, signed 2's complement, range: -128 ~ +127 */ - uint8_t c_th[DSP2_AWB2_STA_C_NUM]; /*!< r/w, shadow, 6'b, = STAT_PIXEL_BW - 2, range: 0 ~ (2 ^ 6 - 1) */ - uint8_t c_slope[DSP2_AWB2_STA_C_NUM]; /*!< r/w, shadow, 8'b, = 6 + SLOPE_PRECISION, range: 0 ~ (2 ^ 8 - 1) */ -} dsp2_awb2_stats_conf_t; - -/** - * @brief AWB2 sum - */ -typedef struct _dsp2_awb2_sum { - uint32_t r_avg; /*!< r, ping-pong, 12'b, = PIXEL_BW */ - uint32_t g_avg; /*!< r, ping-pong, 12'b, = PIXEL_BW */ - uint32_t b_avg; /*!< r, ping-pong, 12'b, = PIXEL_BW */ - uint64_t white_r_sum; /*!< r, ping-pong, 41'b, = max. width * height in bit + WEIGHT_PRECISION + PIXEL_BW */ - uint64_t white_g_sum; /*!< r, ping-pong, 41'b, = max. width * height in bit + WEIGHT_PRECISION + PIXEL_BW */ - uint64_t white_b_sum; /*!< r, ping-pong, 41'b, = max. width * height in bit + WEIGHT_PRECISION + PIXEL_BW */ - uint32_t white_ratio; /*!< r, ping-pong, 15'b, = 1 + RATIO_PRECISION, 1.14 fixed-point */ -} dsp2_awb2_sum_t; - -/** - * @brief AWB sum - */ -typedef struct _dsp2_awb_sum { - uint32_t r_sum : 12; - uint32_t reserved_12_15 : 4; - uint32_t g_sum : 12; - uint32_t reserved_28_31 : 4; - uint32_t b_sum : 12; - uint32_t reserved_12_31 : 20; -} dsp2_awb_sum_t; - -/** - * @brief EE threshold type - */ -typedef struct -{ - uint8_t dirShpnessThresh; - uint8_t noDirShpnessThresh; - uint8_t flatThresh; - uint16_t textureThresh; - uint16_t edgeThresh; -} DSP2_EE_Thresh_Type; - -/** - * @brief EE str type - */ -typedef struct -{ - uint8_t posEdgeOvrshtStr; - uint8_t negEdgeOvrshtStr; - uint8_t posEdgeStr; - uint8_t negEdgeStr; - uint8_t nrStr; -} DSP2_EE_Str_Type; - -/** - * @brief EE luma weight type - */ -typedef struct -{ - uint16_t lumaWgtTbl[DSP2_EE_LUMA_WEIGHT_NUM]; -} DSP2_EE_Luma_Weight_Type; - -/** - * @brief Chroma suppress type - */ -typedef struct -{ - uint16_t gain; - uint8_t weight; - uint8_t gain_thresh; -} DSP2_Chroma_Suppress_Type; - -/** - * @brief RGB gain type - */ -typedef struct -{ - uint16_t r_gain; - uint16_t g_gain; - uint16_t b_gain; -} DSP2_RGB_Gain_Type; - -/** - * @brief RB gain type - */ -typedef struct -{ - uint16_t r_gain; - uint16_t b_gain; -} DSP2_RB_Gain_Type; - -/*@} end of group DSP2_Public_Types */ - -/** @defgroup DSP2_Public_Constants - * @{ - */ - -/** @defgroup DSP2_SYNC_MODE_TYPE - * @{ - */ -#define IS_DSP2_SYNC_MODE_TYPE(type) (((type) == DSP2_SYNC_MODE_INPUT) || \ - ((type) == DSP2_SYNC_MODE_OUTPUT) || \ - ((type) == DSP2_SYNC_MODE_OUTPUT_INPUT) || \ - ((type) == DSP2_SYNC_MODE_INPUT_VBLANK_NO_TOGGLE)) - -/** @defgroup DSP2_CCM_COEF_TYPE_E - * @{ - */ -#define IS_DSP2_CCM_COEF_TYPE_E(type) (((type) == DSP2_CCM_11) || \ - ((type) == DSP2_CCM_12) || \ - ((type) == DSP2_CCM_13) || \ - ((type) == DSP2_CCM_21) || \ - ((type) == DSP2_CCM_22) || \ - ((type) == DSP2_CCM_23) || \ - ((type) == DSP2_CCM_31) || \ - ((type) == DSP2_CCM_32) || \ - ((type) == DSP2_CCM_33)) - -/** @defgroup DSP2_YUV_CONV_TYPE - * @{ - */ -#define IS_DSP2_YUV_CONV_TYPE(type) (((type) == DSP2_YUV_CONV_FULL_SCALE) || \ - ((type) == DSP2_YUV_CONV_BT601)) - -/** @defgroup DSP2_DPC_ENHANCE_TYPE - * @{ - */ -#define IS_DSP2_DPC_ENHANCE_TYPE(type) (((type) == DSP2_DPC_Enhance1) || \ - ((type) == DSP2_DPC_Enhance2) || \ - ((type) == DSP2_DPC_Enhance3) || \ - ((type) == DSP2_DPC_Enhance_Num)) - -/** @defgroup DSP2_DPC_THRESHOLD_TYPE - * @{ - */ -#define IS_DSP2_DPC_THRESHOLD_TYPE(type) (((type) == DSP2_DPC_th1) || \ - ((type) == DSP2_DPC_th2) || \ - ((type) == DSP2_DPC_th3) || \ - ((type) == DSP2_DPC_th4) || \ - ((type) == DSP2_DPC_th5) || \ - ((type) == DSP2_DPC_th_Num)) - -/** @defgroup AE_GRID_DATA_TYPE_E - * @{ - */ -#define IS_AE_GRID_DATA_TYPE_E(type) (((type) == AE_GRID_DATA_RGB) || \ - ((type) == AE_GRID_DATA_Y)) - -/** @defgroup AWB_GRID_DATA_TYPE_E - * @{ - */ -#define IS_AWB_GRID_DATA_TYPE_E(type) (((type) == AWB_GRID_DATA_RG) || \ - ((type) == AWB_GRID_DATA_B)) - -/*@} end of group DSP2_Public_Constants */ - -/** @defgroup DSP2_Public_Macros - * @{ - */ -#define CHECK_PARAM_RANGE(value, min, max) \ - CHECK_PARAM((value) >= min && (value) <= max) -#define CHECK_PARAM_MAX(value, max) \ - CHECK_PARAM((value) <= max) -#define CHECK_PARAM_MIN(value, min) \ - CHECK_PARAM((value) >= min) - -/*@} end of group DSP2_Public_Macros */ - -/** @defgroup DSP2_Public_Functions - * @{ - */ -void DSP2_Init(void); - -void DSP2_Set_TG_Cfg(const DSP2_TG_Cfg_Type *cfg); -void DSP2_Set_Bayer_Pattern(const BAYER_PATTERN_E *pattern); - -void DSP2_Set_AE_State(BL_Fun_Type state); -void DSP2_Set_AE_Stats_Conf(const dsp2_ae_stats_conf_t *ae_stats_conf); -void DSP2_Get_AE_Stats_Conf(dsp2_ae_stats_conf_t *ae_stats_conf); -void DSP2_Get_AE_Sum(int grid_idx, AE_GRID_DATA_TYPE_E data_type, uint32_t *data); -int DSP2_Get_AE_Stats(int grid_num, uint32_t *data); - -void DSP2_Set_AWB_State(BL_Fun_Type state); -int DSP2_Get_AWB_Stats(int grid_num, uint32_t *data); -void DSP2_Set_AWB_Stats_Conf(const dsp2_awb_stats_conf_t *awb_stats_conf); -void DSP2_Get_AWB_Stats_Conf(dsp2_awb_stats_conf_t *awb_stats_conf); -void DSP2_Get_AWB_Sum(int grid_idx, RGB_SUM_S *rgb_sum); -void DSP2_Get_AWB_ValidGridNum(int *valid_grid_num); - -void DSP2_Set_AWB_Gain(const DSP2_RGB_Gain_Type *rgb_gain); -void DSP2_Get_AWB_Gain(DSP2_RGB_Gain_Type *rgb_gain); -void DSP2_Set_RB_Gain(const DSP2_RB_Gain_Type *rb_gain); - -void DSP2_Set_AWB2_State(BL_Fun_Type state); -void DSP2_Set_AWB2_Stats_Conf(const dsp2_awb2_stats_conf_t *awb_stats_conf); -int DSP2_Get_AWB2_Sum(dsp2_awb2_sum_t *sum); -void DSP2_Set_AWB2_Gain_State(BL_Fun_Type state); -void DSP2_Set_AWB2_Gain(const DSP2_RGB_Gain_Type *gain); -void DSP2_Get_AWB2_Gain(DSP2_RGB_Gain_Type *rgb_gain); - -int DSP2_Get_Output_Window(BL_Img_Size_T *out_win); - -/* Set R/G/B BLC, value range : 0-1023 */ -int DSP2_Set_BLC(const DSP2_CLAMP_S *clamp); -int DSP2_Get_BLC(DSP2_CLAMP_S *clamp); - -void DSP2_Set_DPC_State(BL_Fun_Type state); -void DSP2_Enable_DPC(void); -void DSP2_Disable_DPC(void); -int DSP2_Set_Defect_Correction_Enhance_Group(const DSP2_DPC_ENHANCE_GROUP_TYPE *value); -int DSP2_Get_Defect_Correction_Enhance_Group(DSP2_DPC_ENHANCE_GROUP_TYPE *value); -int DSP2_Set_Defect_Correction_Threshold_Group(const DSP2_DPC_THRESHOLD_GROUP_TYPE *value); -int DSP2_Get_Defect_Correction_Threshold_Group(DSP2_DPC_THRESHOLD_GROUP_TYPE *value); - -void DSP2_Set_BNR_State(BL_Fun_Type state); -void DSP2_Get_BNR_State(BL_Fun_Type *state); -void DSP2_Set_BNR_Weight(int value); -void DSP2_Get_BNR_Weight(int *value); -void DSP2_Set_BNR_LPF_Weight(int value); -void DSP2_Get_BNR_LPF_Weight(int *value); -void DSP2_Set_BNR_Threshold(const DSP2_BNR_THRESHOLD_TYPE *value); -void DSP2_Get_BNR_Threshold(DSP2_BNR_THRESHOLD_TYPE *value); -void DSP2_Set_BNR_Fallback(const DSP2_BNR_FALLBACK_TYPE *value); -void DSP2_Get_BNR_Fallback(DSP2_BNR_FALLBACK_TYPE *value); - -void DSP2_Set_Brightness(int value); -void DSP2_Get_Brightness(int *value); - -void DSP2_Set_LSC_State(BL_Fun_Type state); -void DSP2_Enable_LSC(void); -void DSP2_Disable_LSC(void); -void DSP2_Get_LSC_State(BL_Fun_Type *state); - -/* Set Lens Shading Correction offset */ -int DSP2_Set_LSC_Offset(int xoffset, int yoffset); - -/* Set/Get Lens Shading Correction setting, value range: please see DSP2_LSC_COEF_S */ -int DSP2_Set_LSC_Coeff(const DSP2_LSC_COEF_S *lsc); -int DSP2_Get_LSC_Coeff(DSP2_LSC_COEF_S *lsc); - -/* Set/Get Lens Shading Correction R,G,B MAX, value range: 0-255 (refs to demo app) */ -int DSP2_Set_LSC_Max(const DSP2_LSC_MAX_S *lsc_max); -int DSP2_Get_LSC_Max(DSP2_LSC_MAX_S *lsc_max); - -void DSP2_Set_Digital_Gain(uint16_t dgain); - -void DSP2_Set_CCM_State(BL_Fun_Type state); -void DSP2_Get_CCM_State(BL_Fun_Type *state); - -/* Set/Get Color Correction Matrix Coefficient Value, value range: 0-4095, 512 normalize to 1 */ -void DSP2_Set_CCM_Coef(const DSP2_CCM_COEF_S *ccm); -void DSP2_Get_CCM_Coef(DSP2_CCM_COEF_S *ccm); - -void DSP2_Set_Gamma_State(BL_Fun_Type state); -void DSP2_Get_Gamma_State(BL_Fun_Type *state); - -/* Set/Get Gamma, value range: 0-4095 */ -void DSP2_Set_Gamma_Coef(const DSP2_Gamma_Curve_Type *gamma_curve); -void DSP2_Get_Gamma_Coef(DSP2_Gamma_Curve_Type *gamma_curve); - -void DSP2_Init_Color_Enhancement(); - -/* Set/Get YUV Conversion mode, if you want to change the yuv range, please set yuv adjust */ -void DSP2_Set_YUV_Conv_Mode(DSP2_YUV_CONV_TYPE type); -void DSP2_Get_YUV_Conv_Mode(DSP2_YUV_CONV_TYPE *type); - -/* Set/Get Brightness, value range: TODO -128-127 */ -void DSP2_Set_Brightness(int value); -void DSP2_Get_Brightness(int *value); - -/* Set/Get Contrast, value range: TODO 0-255 */ -void DSP2_Set_Contrast(int value); -void DSP2_Get_Contrast(int *value); - -/* Set/Get Saturation, value range: TODO 0-255 */ -void DSP2_Set_Saturation(const DSP2_SATURATION_S *saturation); -void DSP2_Get_Saturation(DSP2_SATURATION_S *saturation); - -/* Set/Get Noise Level, value range: 0-63 */ -void DSP2_Set_Noise_Level(int value); -void DSP2_Get_Noise_Level(int *value); - -/* Set/Get 2D Noise Reduction, value range: 0-31 */ -void DSP2_Set_2D_NR(int value); -void DSP2_Get_2D_NR(int *value); - -/* Set/Get 3D Noise Reduction, value range: 0-31 */ -void DSP2_Set_3D_NR(int value); -void DSP2_Get_3D_NR(int *value); - -void DSP2_Set_EE_State(BL_Fun_Type state); -void DSP2_Enable_EE(void); -void DSP2_Disable_EE(void); -void DSP2_EnableEEOverShoot(void); -void DSP2_DisableEEOverShoot(void); -void DSP2_Set_EE_Thresh(const DSP2_EE_Thresh_Type *threshCfg); -void DSP2_Get_EE_Thresh(DSP2_EE_Thresh_Type *threshCfg); -void DSP2_Set_EE_Strength(const DSP2_EE_Str_Type *strCfg); -void DSP2_Get_EE_Strength(DSP2_EE_Str_Type *strCfg); -void DSP2_Set_EE_LumaWeight(const DSP2_EE_Luma_Weight_Type *lumaWgtCfg); -void DSP2_Get_EE_LumaWeight(DSP2_EE_Luma_Weight_Type *lumaWgtCfg); - -void DSP2_Set_ChromaSuppress_State(BL_Fun_Type state); -void DSP2_Enable_ChromaSuppress(void); -void DSP2_Disable_ChromaSuppress(void); - -void DSP2_Set_ChromaSuppress(const DSP2_Chroma_Suppress_Type *chromaSupprCfg); -void DSP2_Get_ChromaSuppress(DSP2_Chroma_Suppress_Type *chromaSupprCfg); - -/*@} end of group DSP2_Public_Functions */ - -/*@} end of group DSP2 */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_DSP2_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dsp2_axi_ctrl.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dsp2_axi_ctrl.h deleted file mode 100644 index 25f9933a71..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dsp2_axi_ctrl.h +++ /dev/null @@ -1,174 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_dsp2_axi_ctrl.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_DSP2_AXI_CTRL_H__ -#define __BL808_DSP2_AXI_CTRL_H__ - -#include "dsp2_axi_ctrl_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup DSP2_AXI_CTRL - * @{ - */ - -/** @defgroup DSP2_AXI_CTRL_Public_Types - * @{ - */ - -/** - * @brief 3DNR burst type definition - */ -typedef enum { - DSP2_3DNR_BURST_TYPE_SINGLE, /*!< DSP2 3DNR burst type:single */ - DSP2_3DNR_BURST_TYPE_INCR4, /*!< DSP2 3DNR burst type:incrementing 4 */ - DSP2_3DNR_BURST_TYPE_INCR8, /*!< DSP2 3DNR burst type:incrementing 8 */ - DSP2_3DNR_BURST_TYPE_INCR16, /*!< DSP2 3DNR burst type:incrementing 16 */ - DSP2_3DNR_BURST_TYPE_INCR32 = 5, /*!< DSP2 3DNR burst type:incrementing 32 */ - DSP2_3DNR_BURST_TYPE_INCR64, /*!< DSP2 3DNR burst type:incrementing 64 */ -} DSP2_3DNR_Burst_Type; - -/** - * @brief 3DNR status type definition - */ -typedef enum { - DSP2_3DNR_STATUS_R_DRAIN = 4, /*!< Read fifo drain error status */ - DSP2_3DNR_STATUS_W_OVERFLOW, /*!< Write overflow status */ - DSP2_3DNR_STATUS_W_DVP_IDLE = 8, /*!< Write dvp idle status */ - DSP2_3DNR_STATUS_W_DVP_WTST, /*!< Write dvp wait start status */ - DSP2_3DNR_STATUS_W_DVP_FUNC, /*!< Write dvp function status */ - DSP2_3DNR_STATUS_W_DVP_FEND, /*!< Write dvp function end status */ - DSP2_3DNR_STATUS_W_DVP_FLSH, /*!< Write dvp flush status */ - DSP2_3DNR_STATUS_W_BUS_IDLE, /*!< Write bus idle status */ - DSP2_3DNR_STATUS_W_BUS_FUNC, /*!< Write bus function status */ - DSP2_3DNR_STATUS_W_BUS_FEND, /*!< Write bus function end status */ - DSP2_3DNR_STATUS_W_BUS_FLSH, /*!< Write bus flush status */ - DSP2_3DNR_STATUS_R_DVP_IDLE, /*!< Read dvp idle status */ - DSP2_3DNR_STATUS_R_DVP_WTST, /*!< Read dvp wait start status */ - DSP2_3DNR_STATUS_R_DVP_FUNC, /*!< Read dvp function status */ - DSP2_3DNR_STATUS_R_DVP_FEND, /*!< Read dvp function end status */ - DSP2_3DNR_STATUS_R_DVP_FLSH, /*!< Read dvp flush status */ - DSP2_3DNR_STATUS_R_BUS_IDLE, /*!< Read bus idle status */ - DSP2_3DNR_STATUS_R_BUS_FUNC, /*!< Read bus function status */ - DSP2_3DNR_STATUS_R_BUS_FEND, /*!< Read bus function end status */ - DSP2_3DNR_STATUS_R_BUS_FLSH, /*!< Read bus flush status */ - DSP2_3DNR_STATUS_R_IDLE, /*!< AXI read channel idle status */ - DSP2_3DNR_STATUS_W_IDLE, /*!< AXI write channel idle status */ -} DSP2_3DNR_Status_Type; - -/** - * @brief 3DNR configure strcut definition - */ -typedef struct -{ - DSP2_3DNR_Burst_Type burst; /*!< 3DNR burst length */ - uint32_t memStart; /*!< Data start address */ - uint32_t memSize; /*!< Memory size */ - uint16_t hsyncStart; /*!< Hsync active start count */ - uint16_t hsyncEnd; /*!< Hsync active end count */ - uint16_t vsyncStart; /*!< Vsync active start count */ - uint16_t vsyncEnd; /*!< Vsync active end count */ -} DSP2_3DNR_Cfg_Type; - -/*@} end of group DSP2_AXI_CTRL_Public_Types */ - -/** @defgroup DSP2_AXI_CTRL_Public_Constants - * @{ - */ - -/** @defgroup DSP2_3DNR_BURST_TYPE - * @{ - */ -#define IS_DSP2_3DNR_BURST_TYPE(type) (((type) == DSP2_3DNR_BURST_TYPE_SINGLE) || \ - ((type) == DSP2_3DNR_BURST_TYPE_INCR4) || \ - ((type) == DSP2_3DNR_BURST_TYPE_INCR8) || \ - ((type) == DSP2_3DNR_BURST_TYPE_INCR16) || \ - ((type) == DSP2_3DNR_BURST_TYPE_INCR32) || \ - ((type) == DSP2_3DNR_BURST_TYPE_INCR64)) - -/** @defgroup DSP2_3DNR_STATUS_TYPE - * @{ - */ -#define IS_DSP2_3DNR_STATUS_TYPE(type) (((type) == DSP2_3DNR_STATUS_R_DRAIN) || \ - ((type) == DSP2_3DNR_STATUS_W_OVERFLOW) || \ - ((type) == DSP2_3DNR_STATUS_W_DVP_IDLE) || \ - ((type) == DSP2_3DNR_STATUS_W_DVP_WTST) || \ - ((type) == DSP2_3DNR_STATUS_W_DVP_FUNC) || \ - ((type) == DSP2_3DNR_STATUS_W_DVP_FEND) || \ - ((type) == DSP2_3DNR_STATUS_W_DVP_FLSH) || \ - ((type) == DSP2_3DNR_STATUS_W_BUS_IDLE) || \ - ((type) == DSP2_3DNR_STATUS_W_BUS_FUNC) || \ - ((type) == DSP2_3DNR_STATUS_W_BUS_FEND) || \ - ((type) == DSP2_3DNR_STATUS_W_BUS_FLSH) || \ - ((type) == DSP2_3DNR_STATUS_R_DVP_IDLE) || \ - ((type) == DSP2_3DNR_STATUS_R_DVP_WTST) || \ - ((type) == DSP2_3DNR_STATUS_R_DVP_FUNC) || \ - ((type) == DSP2_3DNR_STATUS_R_DVP_FEND) || \ - ((type) == DSP2_3DNR_STATUS_R_DVP_FLSH) || \ - ((type) == DSP2_3DNR_STATUS_R_BUS_IDLE) || \ - ((type) == DSP2_3DNR_STATUS_R_BUS_FUNC) || \ - ((type) == DSP2_3DNR_STATUS_R_BUS_FEND) || \ - ((type) == DSP2_3DNR_STATUS_R_BUS_FLSH) || \ - ((type) == DSP2_3DNR_STATUS_R_IDLE) || \ - ((type) == DSP2_3DNR_STATUS_W_IDLE)) - -/*@} end of group DSP2_AXI_CTRL_Public_Constants */ - -/** @defgroup DSP2_AXI_CTRL_Public_Macros - * @{ - */ - -/*@} end of group DSP2_AXI_CTRL_Public_Macros */ - -/** @defgroup DSP2_AXI_CTRL_Public_Functions - * @{ - */ -void DSP2_3DNR_Init(DSP2_3DNR_Cfg_Type *dsp23DNRCfg); -void DSP2_3DNR_Enable(void); -void DSP2_3DNR_Disable(void); -void DSP2_3DNR_Clear_Write_Overflow(void); -void DSP2_3DNR_Clear_Read_Drain(void); -BL_Sts_Type DSP2_3DNR_Get_status(DSP2_3DNR_Status_Type dsp23DNRStatus); - -/*@} end of group DSP2_AXI_CTRL_Public_Functions */ - -/*@} end of group DSP2_AXI_CTRL */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_DSP2_AXI_CTRL_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dsp2_misc.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dsp2_misc.h deleted file mode 100644 index 2c65e57ecf..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dsp2_misc.h +++ /dev/null @@ -1,722 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_dsp2_misc.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_DSP2_MISC_H__ -#define __BL808_DSP2_MISC_H__ - -#include "dsp2_misc_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup DSP2_MISC - * @{ - */ - -/** @defgroup DSP2_MISC_Public_Types - * @{ - */ - -/** - * @brief DVP 2X input data order type definition - */ -typedef enum { - DSP2_MISC_2X_DATA_BYTE_LOWER, /*!< The first data is lower-byte */ - DSP2_MISC_2X_DATA_BYTE_HIGHER, /*!< The first data is higher-byte */ -}DSP2_MISC_2X_Data_Order_Type; - -/** - * @brief Input V/H sync active level type definition - */ -typedef enum { - DSP2_MISC_ACTIVE_HIGH, /*!< Input is active-high */ - DSP2_MISC_ACTIVE_LOW, /*!< Input is active-low */ -}DSP2_MISC_Active_Level_Type; - -/** - * @brief DVP TSRC data source type definition - */ -typedef enum { - DSP2_MISC_TSRC_SOURCE_DVP, /*!< DVP TSRC data source is DVP */ - DSP2_MISC_TSRC_SOURCE_CSI, /*!< DVP TSRC data source is MIPI CSI */ -}DSP2_MISC_TSRC_Source_Type; - -/** - * @brief CAM id type definition - */ -typedef enum { - DSP2_MISC_CAM_0_ID, /*!< CAM 0 port define */ - DSP2_MISC_CAM_1_ID, /*!< CAM 1 port define */ - DSP2_MISC_CAM_2_ID, /*!< CAM 2 port define */ - DSP2_MISC_CAM_3_ID, /*!< CAM 3 port define */ - DSP2_MISC_CAM_4_ID, /*!< CAM 4 port define */ - DSP2_MISC_CAM_5_ID, /*!< CAM 5 port define */ - DSP2_MISC_CAM_6_ID, /*!< CAM 6 port define */ - DSP2_MISC_CAM_7_ID, /*!< CAM 7 port define */ - DSP2_MISC_CAM_ID_MAX, /*!< CAM max ID define */ -} DSP2_MISC_CAM_ID_Type; - -/** - * @brief Crop id type definition - */ -typedef enum { - DSP2_MISC_CROP_0_ID, /*!< Crop 0 port define */ - DSP2_MISC_CROP_1_ID, /*!< Crop 1 port define */ - DSP2_MISC_CROP_2_ID, /*!< Crop 2 port define */ - DSP2_MISC_CROP_3_ID, /*!< Crop 3 port define */ - DSP2_MISC_CROP_ID_MAX, /*!< Crop max ID define */ -} DSP2_MISC_Crop_ID_Type; - -/** - * @brief Scaler id type definition - */ -typedef enum { - DSP2_MISC_SCALER_0_ID, /*!< Scaler 0 port define */ - DSP2_MISC_SCALER_1_ID, /*!< Scaler 1 port define */ - DSP2_MISC_SCALER_2_ID, /*!< Scaler 2 port define */ - DSP2_MISC_SCALER_3_ID, /*!< Scaler 3 port define */ - DSP2_MISC_SCALER_ID_MAX, /*!< Scaler max ID define */ -} DSP2_MISC_Scaler_ID_Type; - -/** - * @brief OSD id type definition - */ -typedef enum { - DSP2_MISC_OSD_0_ID, /*!< OSD 0 port define */ - DSP2_MISC_OSD_1_ID, /*!< OSD 1 port define */ - DSP2_MISC_OSD_2_ID, /*!< OSD 2 port define */ - DSP2_MISC_OSD_3_ID, /*!< OSD 3 port define */ - DSP2_MISC_OSD_ID_MAX, /*!< OSD max ID define */ -} DSP2_MISC_OSD_ID_Type; - -/** - * @brief Adjust id type definition - */ -typedef enum { - DSP2_MISC_ADJUST_0_ID, /*!< Adjust 0 port define */ - DSP2_MISC_ADJUST_1_ID, /*!< Adjust 1 port define */ - DSP2_MISC_ADJUST_2_ID, /*!< Adjust 2 port define */ - DSP2_MISC_ADJUST_3_ID, /*!< Adjust 3 port define */ - DSP2_MISC_ADJUST_ID_MAX, /*!< Adjust max ID define */ -} DSP2_MISC_Adjust_ID_Type; - -/** - * @brief YUV2RGB id type definition - */ -typedef enum { - DSP2_MISC_YUV2RGB_DISPLAY_ID, /*!< Display YUV2RGB port define */ - DSP2_MISC_YUV2RGB_NORMAL_ID, /*!< Normal YUV2RGB port define */ - DSP2_MISC_YUV2RGB_ID_MAX, /*!< YUV2RGB max ID define */ -} DSP2_MISC_YUV2RGB_ID_Type; - -/** - * @brief Frame id type definition - */ -typedef enum { - DSP2_MISC_FRAME_BAYER_ID, /*!< Bayer ID */ - DSP2_MISC_FRAME_YUV_ID, /*!< YUV ID */ -} DSP2_MISC_Frame_ID_Type; - -/** - * @brief Frame id vsync edge type definition - */ -typedef enum { - DSP2_MISC_FRAME_ID_VSYNC_NEGEDGE, /*!< Frame ID base on vsync negedge */ - DSP2_MISC_FRAME_ID_VSYNC_POSEDGE, /*!< Frame ID base on vsync posedge */ -} DSP2_MISC_Frame_ID_Edge_Type; - -/** - * @brief CAM input type definition - */ -typedef enum { - DSP2_MISC_CAM_DSP2_INPUT, /*!< Use DSP2 input as CAM input */ - DSP2_MISC_CAM_ACTIVE_DVP_OUTPUT, /*!< Use active DVP(TG) as CAM input */ - DSP2_MISC_CAM_DEFECT_CORRECT_OUTPUT, /*!< Use defect correct as CAM input */ - DSP2_MISC_CAM_CCM_R_OUTPUT, /*!< Use CCM R as CAM input */ - DSP2_MISC_CAM_CCM_G_OUTPUT, /*!< Use CCM G as CAM input */ - DSP2_MISC_CAM_CCM_B_OUTPUT, /*!< Use CCM B as CAM input */ - DSP2_MISC_CAM_GAMMA_R_OUTPUT, /*!< Use gamma R as CAM input */ - DSP2_MISC_CAM_GAMMA_G_OUTPUT, /*!< Use gamma G as CAM input */ - DSP2_MISC_CAM_NONE_OUTPUT, /*!< Don't use */ - DSP2_MISC_CAM_BNR_OUTPUT, /*!< Use BNR as CAM input */ - DSP2_MISC_CAM_NR_OUTPUT, /*!< Use NR as CAM input */ - DSP2_MISC_CAM_EE_OUTPUT, /*!< Use EE as CAM input */ - DSP2_MISC_CAM_DSP2_OUTPUT, /*!< Use DSP2 output as CAM input */ - DSP2_MISC_CAM_OSD_0_OUTPUT, /*!< Use OSD 0 as CAM input */ - DSP2_MISC_CAM_OSD_1_OUTPUT, /*!< Use OSD 1 as CAM input */ - DSP2_MISC_CAM_OSD_2_OUTPUT, /*!< Use OSD 2 as CAM input */ - DSP2_MISC_CAM_OSD_3_OUTPUT, /*!< Use OSD 3 as CAM input */ - DSP2_MISC_CAM_SCALER_0_OUTPUT, /*!< Use scaler 0 as CAM input */ - DSP2_MISC_CAM_SCALER_1_OUTPUT, /*!< Use scaler 1 as CAM input */ - DSP2_MISC_CAM_SCALER_2_OUTPUT, /*!< Use scaler 2 as CAM input */ - DSP2_MISC_CAM_SCALER_3_OUTPUT, /*!< Use scaler 3 as CAM input */ - DSP2_MISC_CAM_ADJUST_0_OUTPUT, /*!< Use adjust 0 as CAM input */ - DSP2_MISC_CAM_ADJUST_1_OUTPUT, /*!< Use adjust 1 as CAM input */ - DSP2_MISC_CAM_ADJUST_2_OUTPUT, /*!< Use adjust 2 as CAM input */ - DSP2_MISC_CAM_ADJUST_3_OUTPUT, /*!< Use adjust 3 as CAM input */ - DSP2_MISC_CAM_YUV420_0_OUTPUT, /*!< Use YUV420 0 as CAM input */ - DSP2_MISC_CAM_YUV420_1_OUTPUT, /*!< Use YUV420 1 as CAM input */ - DSP2_MISC_CAM_YUV420_2_OUTPUT, /*!< Use YUV420 2 as CAM input */ - DSP2_MISC_CAM_YUV420_3_OUTPUT, /*!< Use YUV420 3 as CAM input */ - DSP2_MISC_CAM_GAMMA_B_OUTPUT, /*!< Use gamma B as CAM input */ - DSP2_MISC_CAM_WDR_Y_OUTPUT, /*!< Use WDR Y as CAM input */ - DSP2_MISC_CAM_WDR_U_OUTPUT, /*!< Use WDR U as CAM input */ - DSP2_MISC_CAM_WDR_V_OUTPUT, /*!< Use WDR V as CAM input */ - DSP2_MISC_CAM_LSC_OUTPUT, /*!< Use LSC as CAM input */ - DSP2_MISC_CAM_AWB2_OUTPUT, /*!< Use AWB2 as CAM input */ - DSP2_MISC_CAM_YUV2RGB_OUTPUT, /*!< Use YUV2RGB as CAM input */ - DSP2_MISC_CAM_DVP_AS_2X_OUTPUT, /*!< Use DVP AS 2X as CAM input */ -} DSP2_MISC_CAM_Input_Type; - -/** - * @brief Scaler input type definition - */ -typedef enum { - DSP2_MISC_SCALER_DSP2_OUTPUT, /*!< Use DSP2 output as scaler input */ - DSP2_MISC_SCALER_DSP2_INPUT, /*!< Use DSP2 input as scaler input */ - DSP2_MISC_SCALER_OSD_0_OUTPUT, /*!< Use OSD 0 as scaler input */ - DSP2_MISC_SCALER_OSD_1_OUTPUT, /*!< Use OSD 1 as scaler input */ - DSP2_MISC_SCALER_OSD_2_OUTPUT, /*!< Use OSD 2 as scaler input */ - DSP2_MISC_SCALER_OSD_3_OUTPUT, /*!< Use OSD 3 as scaler input */ -} DSP2_MISC_Scaler_Input_Type; - -/** - * @brief OSD input type definition - */ -typedef enum { - DSP2_MISC_OSD_DSP2_OUTPUT, /*!< Use DSP2 output as OSD input */ - DSP2_MISC_OSD_DSP2_INPUT, /*!< Use DSP2 input as OSD input */ - DSP2_MISC_OSD_SCALER_0_OUTPUT, /*!< Use scaler 0 as OSD input */ - DSP2_MISC_OSD_SCALER_1_OUTPUT, /*!< Use scaler 1 as OSD input */ - DSP2_MISC_OSD_SCALER_2_OUTPUT, /*!< Use scaler 2 as OSD input */ - DSP2_MISC_OSD_SCALER_3_OUTPUT, /*!< Use scaler 3 as OSD input */ - DSP2_MISC_OSD_OSD_0_OUTPUT, /*!< Use osd 0 as OSD input */ - DSP2_MISC_OSD_DVP_AS_2X_OUTPUT, /*!< Use dvp_as_2x as OSD input */ -} DSP2_MISC_OSD_Input_Type; - -/** - * @brief Adjust input type definition - */ -typedef enum { - DSP2_MISC_ADJUST_DSP2_OUTPUT, /*!< Use DSP2 output as adjust input */ - DSP2_MISC_ADJUST_DSP2_INPUT, /*!< Use DSP2 input as adjust input */ - DSP2_MISC_ADJUST_OSD_0_OUTPUT, /*!< Use OSD 0 as adjust input */ - DSP2_MISC_ADJUST_OSD_1_OUTPUT, /*!< Use OSD 1 as adjust input */ - DSP2_MISC_ADJUST_OSD_2_OUTPUT, /*!< Use OSD 2 as adjust input */ - DSP2_MISC_ADJUST_OSD_3_OUTPUT, /*!< Use OSD 3 as adjust input */ - DSP2_MISC_ADJUST_SCALER_0_OUTPUT, /*!< Use scaler 0 as adjust input */ - DSP2_MISC_ADJUST_SCALER_1_OUTPUT, /*!< Use scaler 1 as adjust input */ - DSP2_MISC_ADJUST_SCALER_2_OUTPUT, /*!< Use scaler 2 as adjust input */ - DSP2_MISC_ADJUST_SCALER_3_OUTPUT, /*!< Use scaler 3 as adjust input */ -} DSP2_MISC_Adjust_Input_Type; - -/** - * @brief YUV2RGB input type definition - */ -typedef enum { - DSP2_MISC_YUV2RGB_DSP2_OUTPUT, /*!< Use DSP2 output as yuv2rgb input */ - DSP2_MISC_YUV2RGB_DSP2_INPUT, /*!< Use DSP2 input as yuv2rgb input */ - DSP2_MISC_YUV2RGB_OSD_0_OUTPUT, /*!< Use OSD 0 as yuv2rgb input */ - DSP2_MISC_YUV2RGB_OSD_1_OUTPUT, /*!< Use OSD 1 as yuv2rgb input */ - DSP2_MISC_YUV2RGB_OSD_2_OUTPUT, /*!< Use OSD 2 as yuv2rgb input */ - DSP2_MISC_YUV2RGB_OSD_3_OUTPUT, /*!< Use OSD 3 as yuv2rgb input */ - DSP2_MISC_YUV2RGB_SCALER_0_OUTPUT, /*!< Use scaler 0 as yuv2rgb input */ - DSP2_MISC_YUV2RGB_SCALER_1_OUTPUT, /*!< Use scaler 1 as yuv2rgb input */ - DSP2_MISC_YUV2RGB_SCALER_2_OUTPUT, /*!< Use scaler 2 as yuv2rgb input */ - DSP2_MISC_YUV2RGB_SCALER_3_OUTPUT, /*!< Use scaler 3 as yuv2rgb input */ -} DSP2_MISC_YUV2RGB_Input_Type; - -/** - * @brief Bayer data shift direction type definition - */ -typedef enum { - DSP2_MISC_BAYER_SHIFT_LEFT, /*!< Bayer data shift left */ - DSP2_MISC_BAYER_SHIFT_RIGHT, /*!< Bayer data shift right */ -} DSP2_MISC_Bayer_Shift_Type; - -/** - * @brief DSP2 MISC interrupt type definition - */ -typedef enum { - DSP2_MISC_INT_AWB0, /*!< AWB 0 interrupt */ - DSP2_MISC_INT_AE, /*!< AE interrupt */ - DSP2_MISC_INT_WDR, /*!< WDR interrupt */ - DSP2_MISC_INT_AWB1, /*!< AWB 1 interrupt */ - DSP2_MISC_INT_OSD_PB, /*!< OSD probe interrupt */ - DSP2_MISC_INT_SEOF0, /*!< S/E-oF 0 interrupt */ - DSP2_MISC_INT_SEOF1, /*!< S/E-oF 1 interrupt */ - DSP2_MISC_INT_SEOF2, /*!< S/E-oF 2 interrupt */ - DSP2_MISC_INT_AE_HIST, /*!< AE hist interrupt */ - DSP2_MISC_INT_AWB2, /*!< AWB 2 interrupt */ - DSP2_MISC_INT_DISPLAY, /*!< Display S/E-oF 0 interrupt */ - DSP2_MISC_INT_SEOF3, /*!< S/E-oF 3 interrupt */ - DSP2_MISC_INT_ALL, /*!< All the interrupt */ -} DSP2_MISC_INT_Type; - -/** - * @brief SEOF interrupt vsync source type definition - */ -typedef enum { - DSP2_MISC_SEOF_VSYNC_SENSOR = 0, /*!< Use sensor vsync as SEOF vsync source */ - DSP2_MISC_SEOF_VSYNC_DSP2_ACT = 1, /*!< Use dsp2 active vsync as SEOF vsync source */ - DSP2_MISC_SEOF_VSYNC_DSP2_OUT = 2, /*!< Use dsp2 out vsync as SEOF vsync source */ - DSP2_MISC_SEOF_VSYNC_DVP_TSRC = 3, /*!< Use dvp tsrc vsync as SEOF vsync source */ - DSP2_MISC_SEOF_DISPLAY_TEST_SRC = 0, /*!< Use display test source as display SEOF vsync source */ - DSP2_MISC_SEOF_DISPLAY_OUTPUT = 1, /*!< Use display output as display SEOF vsync source */ -} DSP2_MISC_SEOF_Source_Type; - -/** - * @brief SEOF interrupt trigger vsync edge type definition - */ -typedef enum { - DSP2_MISC_SEOF_VSYNC_NEGEDGE, /*!< Vsync negedge will trigger interrupt */ - DSP2_MISC_SEOF_VSYNC_POSEDGE, /*!< Vsync posedge will trigger interrupt */ -} DSP2_MISC_SEOF_Edge_Type; - -/** - * @brief Display input type definition - */ -typedef enum { - DSP2_MISC_DISPLAY_YUV2RGB_OUTPUT, /*!< Use yuv2rgb output as display input */ - DSP2_MISC_DISPLAY_OSD_DP_OUTPUT, /*!< Use OSD_DP output as display input */ - DSP2_MISC_DISPLAY_TSRC_RGB_OUTPUT, /*!< Use dvp tsrc rgb output as display input */ - DSP2_MISC_DISPLAY_TSRC_YUV422_OUTPUT, /*!< Use dvp tsrc yuv422 output as display input */ -} DSP2_MISC_Display_Input_Type; - -/** - * @brief Display OSD input type definition - */ -typedef enum { - DSP2_MISC_DISPLAY_OSD_YUV420TO422_OUTPUT, /*!< Use yuv420to422 output as display OSD input */ - DSP2_MISC_DISPLAY_OSD_RGB2YUV422_OUTPUT, /*!< Use rgb2yuv422 output as display OSD input */ - DSP2_MISC_DISPLAY_OSD_TSRCYUV422_OUTPUT, /*!< Use dvp tsrc yuv422 output as display OSD input */ -} DSP2_MISC_Display_OSD_Input_Type; - -/** - * @brief DVP AS 2X configuration struct definition - */ -typedef struct { - DSP2_MISC_Active_Level_Type hSyncLevel; /*!< Input H-Sync active level */ - DSP2_MISC_Active_Level_Type vSyncLevel; /*!< Input V-Sync active level */ - DSP2_MISC_2X_Data_Order_Type dataOrder; /*!< Input data order */ - uint16_t fifoThreshold; /*!< Fifo threshold for each DVP line to start to - output,((Width-Fifo_th)*T_in*2)<(Width*T_out)<((Width-Fifo_th)*T_in*2+Blank*T_in) */ -}DSP2_MISC_2X_Cfg_Type; - -/** - * @brief DVP reshape configuration struct definition - */ -typedef struct { - DSP2_MISC_Active_Level_Type hSyncLevel; /*!< Input H-Sync active level */ - DSP2_MISC_Active_Level_Type vSyncLevel; /*!< Input V-Sync active level */ - BL_Fun_Type enable; /*!< Enable or disable sensor vsync toggle remove */ - uint8_t vsyncNumber; /*!< Number of sensor vsync toggle before sensor stable */ -}DSP2_MISC_Reshape_Cfg_Type; - -/** - * @brief Display configuration structure type definition - */ -typedef struct -{ - BL_Fun_Type dpiEnable; /*!< Enable or disable dpi function, only one of the four functions can be enabled at the same time */ - BL_Fun_Type bt1120Enable; /*!< Enable or disable BT1120 function, only one of the four functions can be enabled at the same time */ - BL_Fun_Type hdmiEnable; /*!< Enable or disable HDMI function, only one of the four functions can be enabled at the same time */ - DSP2_MISC_Display_Input_Type inputType; /*!< Select display input */ - DSP2_MISC_Display_OSD_Input_Type osdType; /*!< Select display OSD input */ - uint8_t hsyncWidth; /*!< Horizontal synchronization width */ - uint8_t hfpWidth; /*!< Horizontal front porch width */ - uint8_t vsyncWidth; /*!< Vertical synchronization width */ - uint8_t vfpWidth; /*!< Vertical front porch width */ -} DSP2_MISC_Display_Cfg_Type; - -/** - * @brief Display gamma configuration structure type definition - */ -typedef struct -{ - BL_Fun_Type ch0Enable; /*!< Enable or disable display gamma channel 0 */ - BL_Fun_Type ch1Enable; /*!< Enable or disable display gamma channel 1 */ - BL_Fun_Type ch2Enable; /*!< Enable or disable display gamma channel 2 */ - uint8_t *gammaCurve; /*!< Gamma curve */ -} DSP2_MISC_Display_Gamma_Cfg_Type; - -/** - * @brief YUV2RGB configuration struct definition - */ -typedef struct -{ - BL_Fun_Type enable; /*!< Enable or disable yuv2rgb function */ - uint16_t preOffset0; /*!< YUV2RGB pre offset 0 */ - uint16_t preOffset1; /*!< YUV2RGB pre offset 1 */ - uint16_t preOffset2; /*!< YUV2RGB pre offset 2 */ - uint16_t postOffset0; /*!< YUV2RGB post offset 0 */ - uint16_t postOffset1; /*!< YUV2RGB post offset 1 */ - uint16_t postOffset2; /*!< YUV2RGB post offset 2 */ - uint16_t matrix00; /*!< YUV2RGB matrix 00 */ - uint16_t matrix01; /*!< YUV2RGB matrix 01 */ - uint16_t matrix02; /*!< YUV2RGB matrix 02 */ - uint16_t matrix10; /*!< YUV2RGB matrix 10 */ - uint16_t matrix11; /*!< YUV2RGB matrix 11 */ - uint16_t matrix12; /*!< YUV2RGB matrix 12 */ - uint16_t matrix20; /*!< YUV2RGB matrix 20 */ - uint16_t matrix21; /*!< YUV2RGB matrix 21 */ - uint16_t matrix22; /*!< YUV2RGB matrix 22 */ -} DSP2_MISC_YUV2RGB_Cfg_Type; - -/** - * @brief Crop configuration struct definition - */ -typedef struct -{ - uint16_t hsyncStart; /*!< Hsync valid start */ - uint16_t hsyncEnd; /*!< Hsync valid end */ - uint16_t vsyncStart; /*!< Vsync valid start */ - uint16_t vsyncEnd; /*!< Vsync valid end */ -} DSP2_MISC_Crop_Cfg_Type; - -/** - * @brief Scaler configuration struct definition - */ -typedef struct -{ - uint16_t inputWidth; /*!< Width of input frame */ - uint16_t inputHeight; /*!< Height of input frame */ - uint16_t outputWidth; /*!< Width of output frame */ - uint16_t outputHeight; /*!< Height of output frame */ -} DSP2_MISC_Scaler_Cfg_Type; - -/** - * @brief Adjust configuration struct definition - */ -typedef struct -{ - uint16_t yLuma; /*!< Y luma,higher luma */ - uint16_t yMul0; /*!< Contrast adjust mul0 */ - uint16_t yMul1; /*!< Contrast adjust mul1 */ - uint8_t yMin; /*!< Y min clip value */ - uint8_t yMax; /*!< Y max clip value */ - uint16_t uvMul0; /*!< Saturation adjust, software can multipiler gain to this value */ - uint16_t uvMul1; /*!< Saturation adjust, software can multipiler gain to this value */ - uint8_t uvMin; /*!< UV min clip value */ - uint8_t uvMax; /*!< UV max clip value */ -} DSP2_MISC_Adjust_Cfg_Type; - -/*@} end of group DSP2_MISC_Public_Types */ - -/** @defgroup DSP2_MISC_Public_Constants - * @{ - */ - -/** @defgroup DSP2_MISC_2X_DATA_ORDER_TYPE - * @{ - */ -#define IS_DSP2_MISC_2X_DATA_ORDER_TYPE(type) (((type) == DSP2_MISC_2X_DATA_BYTE_LOWER) || \ - ((type) == DSP2_MISC_2X_DATA_BYTE_HIGHER)) - -/** @defgroup DSP2_MISC_ACTIVE_LEVEL_TYPE - * @{ - */ -#define IS_DSP2_MISC_ACTIVE_LEVEL_TYPE(type) (((type) == DSP2_MISC_ACTIVE_HIGH) || \ - ((type) == DSP2_MISC_ACTIVE_LOW)) - -/** @defgroup DSP2_MISC_TSRC_SOURCE_TYPE - * @{ - */ -#define IS_DSP2_MISC_TSRC_SOURCE_TYPE(type) (((type) == DSP2_MISC_TSRC_SOURCE_DVP) || \ - ((type) == DSP2_MISC_TSRC_SOURCE_CSI)) - -/** @defgroup DSP2_MISC_CAM_ID_TYPE - * @{ - */ -#define IS_DSP2_MISC_CAM_ID_TYPE(type) (((type) == DSP2_MISC_CAM_0_ID) || \ - ((type) == DSP2_MISC_CAM_1_ID) || \ - ((type) == DSP2_MISC_CAM_2_ID) || \ - ((type) == DSP2_MISC_CAM_3_ID) || \ - ((type) == DSP2_MISC_CAM_4_ID) || \ - ((type) == DSP2_MISC_CAM_5_ID) || \ - ((type) == DSP2_MISC_CAM_6_ID) || \ - ((type) == DSP2_MISC_CAM_7_ID) || \ - ((type) == DSP2_MISC_CAM_ID_MAX)) - -/** @defgroup DSP2_MISC_CROP_ID_TYPE - * @{ - */ -#define IS_DSP2_MISC_CROP_ID_TYPE(type) (((type) == DSP2_MISC_CROP_0_ID) || \ - ((type) == DSP2_MISC_CROP_1_ID) || \ - ((type) == DSP2_MISC_CROP_2_ID) || \ - ((type) == DSP2_MISC_CROP_3_ID) || \ - ((type) == DSP2_MISC_CROP_ID_MAX)) - -/** @defgroup DSP2_MISC_SCALER_ID_TYPE - * @{ - */ -#define IS_DSP2_MISC_SCALER_ID_TYPE(type) (((type) == DSP2_MISC_SCALER_0_ID) || \ - ((type) == DSP2_MISC_SCALER_1_ID) || \ - ((type) == DSP2_MISC_SCALER_2_ID) || \ - ((type) == DSP2_MISC_SCALER_3_ID) || \ - ((type) == DSP2_MISC_SCALER_ID_MAX)) - -/** @defgroup DSP2_MISC_OSD_ID_TYPE - * @{ - */ -#define IS_DSP2_MISC_OSD_ID_TYPE(type) (((type) == DSP2_MISC_OSD_0_ID) || \ - ((type) == DSP2_MISC_OSD_1_ID) || \ - ((type) == DSP2_MISC_OSD_2_ID) || \ - ((type) == DSP2_MISC_OSD_3_ID) || \ - ((type) == DSP2_MISC_OSD_ID_MAX)) - -/** @defgroup DSP2_MISC_ADJUST_ID_TYPE - * @{ - */ -#define IS_DSP2_MISC_ADJUST_ID_TYPE(type) (((type) == DSP2_MISC_ADJUST_0_ID) || \ - ((type) == DSP2_MISC_ADJUST_1_ID) || \ - ((type) == DSP2_MISC_ADJUST_2_ID) || \ - ((type) == DSP2_MISC_ADJUST_3_ID) || \ - ((type) == DSP2_MISC_ADJUST_ID_MAX)) - -/** @defgroup DSP2_MISC_YUV2RGB_ID_TYPE - * @{ - */ -#define IS_DSP2_MISC_YUV2RGB_ID_TYPE(type) (((type) == DSP2_MISC_YUV2RGB_DISPLAY_ID) || \ - ((type) == DSP2_MISC_YUV2RGB_NORMAL_ID) || \ - ((type) == DSP2_MISC_YUV2RGB_ID_MAX)) - -/** @defgroup DSP2_MISC_FRAME_ID_TYPE - * @{ - */ -#define IS_DSP2_MISC_FRAME_ID_TYPE(type) (((type) == DSP2_MISC_FRAME_BAYER_ID) || \ - ((type) == DSP2_MISC_FRAME_YUV_ID)) - -/** @defgroup DSP2_MISC_FRAME_ID_EDGE_TYPE - * @{ - */ -#define IS_DSP2_MISC_FRAME_ID_EDGE_TYPE(type) (((type) == DSP2_MISC_FRAME_ID_VSYNC_NEGEDGE) || \ - ((type) == DSP2_MISC_FRAME_ID_VSYNC_POSEDGE)) - -/** @defgroup DSP2_MISC_CAM_INPUT_TYPE - * @{ - */ -#define IS_DSP2_MISC_CAM_INPUT_TYPE(type) (((type) == DSP2_MISC_CAM_DSP2_INPUT) || \ - ((type) == DSP2_MISC_CAM_ACTIVE_DVP_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_DEFECT_CORRECT_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_CCM_R_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_CCM_G_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_CCM_B_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_GAMMA_R_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_GAMMA_G_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_NONE_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_BNR_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_NR_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_EE_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_DSP2_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_OSD_0_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_OSD_1_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_OSD_2_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_OSD_3_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_SCALER_0_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_SCALER_1_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_SCALER_2_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_SCALER_3_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_ADJUST_0_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_ADJUST_1_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_ADJUST_2_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_ADJUST_3_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_YUV420_0_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_YUV420_1_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_YUV420_2_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_YUV420_3_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_GAMMA_B_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_WDR_Y_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_WDR_U_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_WDR_V_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_LSC_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_AWB2_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_YUV2RGB_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_DVP_AS_2X_OUTPUT)) - -/** @defgroup DSP2_MISC_SCALER_INPUT_TYPE - * @{ - */ -#define IS_DSP2_MISC_SCALER_INPUT_TYPE(type) (((type) == DSP2_MISC_SCALER_DSP2_OUTPUT) || \ - ((type) == DSP2_MISC_SCALER_DSP2_INPUT) || \ - ((type) == DSP2_MISC_SCALER_OSD_0_OUTPUT) || \ - ((type) == DSP2_MISC_SCALER_OSD_1_OUTPUT) || \ - ((type) == DSP2_MISC_SCALER_OSD_2_OUTPUT) || \ - ((type) == DSP2_MISC_SCALER_OSD_3_OUTPUT)) - -/** @defgroup DSP2_MISC_OSD_INPUT_TYPE - * @{ - */ -#define IS_DSP2_MISC_OSD_INPUT_TYPE(type) (((type) == DSP2_MISC_OSD_DSP2_OUTPUT) || \ - ((type) == DSP2_MISC_OSD_DSP2_INPUT) || \ - ((type) == DSP2_MISC_OSD_SCALER_0_OUTPUT) || \ - ((type) == DSP2_MISC_OSD_SCALER_1_OUTPUT) || \ - ((type) == DSP2_MISC_OSD_SCALER_2_OUTPUT) || \ - ((type) == DSP2_MISC_OSD_SCALER_3_OUTPUT) || \ - ((type) == DSP2_MISC_OSD_OSD_0_OUTPUT) || \ - ((type) == DSP2_MISC_OSD_DVP_AS_2X_OUTPUT)) - -/** @defgroup DSP2_MISC_YUV2RGB_INPUT_TYPE - * @{ - */ -#define IS_DSP2_MISC_YUV2RGB_INPUT_TYPE(type) (((type) == DSP2_MISC_YUV2RGB_DSP2_OUTPUT) || \ - ((type) == DSP2_MISC_YUV2RGB_DSP2_INPUT) || \ - ((type) == DSP2_MISC_YUV2RGB_OSD_0_OUTPUT) || \ - ((type) == DSP2_MISC_YUV2RGB_OSD_1_OUTPUT) || \ - ((type) == DSP2_MISC_YUV2RGB_OSD_2_OUTPUT) || \ - ((type) == DSP2_MISC_YUV2RGB_OSD_3_OUTPUT) || \ - ((type) == DSP2_MISC_YUV2RGB_SCALER_0_OUTPUT) || \ - ((type) == DSP2_MISC_YUV2RGB_SCALER_1_OUTPUT) || \ - ((type) == DSP2_MISC_YUV2RGB_SCALER_2_OUTPUT) || \ - ((type) == DSP2_MISC_YUV2RGB_SCALER_3_OUTPUT)) - -/** @defgroup DSP2_MISC_BAYER_SHIFT_TYPE - * @{ - */ -#define IS_DSP2_MISC_BAYER_SHIFT_TYPE(type) (((type) == DSP2_MISC_BAYER_SHIFT_LEFT) || \ - ((type) == DSP2_MISC_BAYER_SHIFT_RIGHT)) - -/** @defgroup DSP2_MISC_INT_TYPE - * @{ - */ -#define IS_DSP2_MISC_INT_TYPE(type) (((type) == DSP2_MISC_INT_AWB0) || \ - ((type) == DSP2_MISC_INT_AE) || \ - ((type) == DSP2_MISC_INT_WDR) || \ - ((type) == DSP2_MISC_INT_AWB1) || \ - ((type) == DSP2_MISC_INT_OSD_PB) || \ - ((type) == DSP2_MISC_INT_SEOF0) || \ - ((type) == DSP2_MISC_INT_SEOF1) || \ - ((type) == DSP2_MISC_INT_SEOF2) || \ - ((type) == DSP2_MISC_INT_AE_HIST) || \ - ((type) == DSP2_MISC_INT_AWB2) || \ - ((type) == DSP2_MISC_INT_DISPLAY) || \ - ((type) == DSP2_MISC_INT_SEOF3) || \ - ((type) == DSP2_MISC_INT_ALL)) - -/** @defgroup DSP2_MISC_SEOF_SOURCE_TYPE - * @{ - */ -#define IS_DSP2_MISC_SEOF_SOURCE_TYPE(type) (((type) == DSP2_MISC_SEOF_VSYNC_SENSOR) || \ - ((type) == DSP2_MISC_SEOF_VSYNC_DSP2_ACT) || \ - ((type) == DSP2_MISC_SEOF_VSYNC_DSP2_OUT) || \ - ((type) == DSP2_MISC_SEOF_VSYNC_DVP_TSRC) || \ - ((type) == DSP2_MISC_SEOF_DISPLAY_TEST_SRC) || \ - ((type) == DSP2_MISC_SEOF_DISPLAY_OUTPUT)) - -/** @defgroup DSP2_MISC_SEOF_EDGE_TYPE - * @{ - */ -#define IS_DSP2_MISC_SEOF_EDGE_TYPE(type) (((type) == DSP2_MISC_SEOF_VSYNC_NEGEDGE) || \ - ((type) == DSP2_MISC_SEOF_VSYNC_POSEDGE)) - -/** @defgroup DSP2_MISC_DISPLAY_INPUT_TYPE - * @{ - */ -#define IS_DSP2_MISC_DISPLAY_INPUT_TYPE(type) (((type) == DSP2_MISC_DISPLAY_YUV2RGB_OUTPUT) || \ - ((type) == DSP2_MISC_DISPLAY_YUV422_OUTPUT)) - -/*@} end of group DSP2_MISC_Public_Constants */ - -/** @defgroup DSP2_MISC_Public_Macros - * @{ - */ - -/*@} end of group DSP2_MISC_Public_Macros */ - -/** @defgroup DSP2_MISC_Public_Functions - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -void SEOF0_IRQHandler(void); -void SEOF1_IRQHandler(void); -void SEOF2_IRQHandler(void); -void SEOF3_IRQHandler(void); -void AWB0_IRQHandler(void); -void AWB1_IRQHandler(void); -void AWB2_IRQHandler(void); -void AE_IRQHandler(void); -void AE_HIST_IRQHandler(void); -void WDR_IRQHandler(void); -void OSD_PB_IRQHandler(void); -void Display_IRQHandler(void); -#endif -void DSP2_MISC_2X_Init(DSP2_MISC_2X_Cfg_Type *dvp2xCfg); -void DSP2_MISC_2X_Enable(void); -void DSP2_MISC_2X_Disable(void); -void DSP2_MISC_CAM_Input_Select(DSP2_MISC_CAM_ID_Type camId, DSP2_MISC_CAM_Input_Type inputType); -void DSP2_MISC_CAM_Frame_ID_Select(DSP2_MISC_CAM_ID_Type camId, DSP2_MISC_Frame_ID_Type idType); -void DSP2_MISC_Frame_ID_Init(DSP2_MISC_Frame_ID_Type idType, DSP2_MISC_Frame_ID_Edge_Type edgeType, uint16_t vsyncCnt); -void DSP2_MISC_Frame_ID_Reset(DSP2_MISC_Frame_ID_Type idType); -void DSP2_MISC_OSD_Input_Select(DSP2_MISC_OSD_ID_Type osdId, DSP2_MISC_OSD_Input_Type inputType); -void DSP2_MISC_OSD_Probe_Input_Select(DSP2_MISC_OSD_Input_Type inputType); -void DSP2_MISC_Crop_Init(DSP2_MISC_Crop_ID_Type cropId, DSP2_MISC_Crop_Cfg_Type *cropCfg); -void DSP2_MISC_Crop_Enable(DSP2_MISC_Crop_ID_Type cropId); -void DSP2_MISC_Crop_Disable(DSP2_MISC_Crop_ID_Type cropId); -void DSP2_MISC_Scaler_Input_Select(DSP2_MISC_Scaler_ID_Type scalerId, DSP2_MISC_Scaler_Input_Type inputType); -void DSP2_MISC_Scaler_Init(DSP2_MISC_Scaler_ID_Type scalerId, DSP2_MISC_Scaler_Cfg_Type *scalerCfg); -void DSP2_MISC_Scaler_Enable(DSP2_MISC_Scaler_ID_Type scalerId); -void DSP2_MISC_Scaler_Disable(DSP2_MISC_Scaler_ID_Type scalerId); -void DSP2_MISC_Scaler_Shadow(DSP2_MISC_Scaler_ID_Type scalerId); -void DSP2_MISC_Adjust_Input_Select(DSP2_MISC_Adjust_ID_Type adjustId, DSP2_MISC_Adjust_Input_Type inputType); -void DSP2_MISC_Adjust_Init(DSP2_MISC_Adjust_ID_Type adjustId, DSP2_MISC_Adjust_Cfg_Type *adjustCfg); -void DSP2_MISC_Adjust_Enable(DSP2_MISC_Adjust_ID_Type adjustId); -void DSP2_MISC_Adjust_Disable(DSP2_MISC_Adjust_ID_Type adjustId); -void DSP2_MISC_Display_Init(DSP2_MISC_Display_Cfg_Type *displayCfg); -void DSP2_MISC_Display_Gamma_Init(DSP2_MISC_Display_Gamma_Cfg_Type *gammaCfg); -void DSP2_MISC_YUV2RGB_Input_Select(DSP2_MISC_YUV2RGB_Input_Type inputType); -void DSP2_MISC_YUV2RGB_Init(DSP2_MISC_YUV2RGB_ID_Type yuv2rgbId, DSP2_MISC_YUV2RGB_Cfg_Type *yuv2rgbCfg); -void DSP2_MISC_RGB2YUV_Init(DSP2_MISC_YUV2RGB_Cfg_Type *rgb2yuvCfg); -void DSP2_MISC_Int_Clear(DSP2_MISC_INT_Type intType); -void DSP2_MISC_Int_Mask(DSP2_MISC_INT_Type intType, BL_Mask_Type intMask); -void DSP2_MISC_Int_Callback_Install(DSP2_MISC_INT_Type intType, intCallback_Type *cbFun); -void DSP2_MISC_SEOF_Set_Source(DSP2_MISC_INT_Type intType, DSP2_MISC_SEOF_Source_Type source); -void DSP2_MISC_SEOF_Set_Edge(DSP2_MISC_INT_Type intType, DSP2_MISC_SEOF_Edge_Type edge); -void DSP2_MISC_Reshape_Init(DSP2_MISC_Reshape_Cfg_Type *reshapeCfg); -void DSP2_MISC_Reshape_Counter_Clear(void); -void DSP2_MISC_DE_As_Hsync(BL_Fun_Type enable); -void DSP2_MISC_TSRC_Source_Select(DSP2_MISC_TSRC_Source_Type sourceType); -void DSP2_MISC_Bayer_Shift(uint16_t bitEnable, DSP2_MISC_Bayer_Shift_Type shiftType, uint8_t bitShift); -void DSP2_MISC_M2N_Enable(uint8_t m, uint8_t n, uint8_t step); -void DSP2_MISC_M2N_Disable(void); - -/*@} end of group DSP2_MISC_Public_Functions */ - -/*@} end of group DSP2_MISC */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_DSP2_MISC_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dsp2_wdr.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dsp2_wdr.h deleted file mode 100644 index 09e9fd92fb..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dsp2_wdr.h +++ /dev/null @@ -1,121 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_dsp2_wdr.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_DSP2_WDR_H__ -#define __BL808_DSP2_WDR_H__ - -#include "bl808_common.h" -#include "bl808_dsp2.h" - -#define DSP2_WDR_HIST_BIN_NUM (65) -#define DSP2_WDR_CURVE_COEF_NUM (64) - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup DSP2_WDR - * @{ - */ - -/** @defgroup DSP2_WDR_Public_Types - * @{ - */ - -/** - * @brief WDR hist data struct definition - */ -typedef struct -{ - uint32_t hist_bin[DSP2_WDR_HIST_BIN_NUM]; -} DSP2_WDR_Hist_Data_Type; - -/** - * @brief WDR curve strcut definition - */ -typedef struct -{ - uint16_t curve_coef[DSP2_WDR_CURVE_COEF_NUM]; -} DSP2_WDR_Curve_Type; - -/*@} end of group DSP2_WDR_Public_Types */ - -/** @defgroup DSP2_WDR_Public_Constants - * @{ - */ - -/*@} end of group DSP2_WDR_Public_Constants */ - -/** @defgroup DSP2_WDR_Public_Macros - * @{ - */ - -/*@} end of group DSP2_WDR_Public_Macros */ - -/** @defgroup DSP2_WDR_Public_Functions - * @{ - */ -void DSP2_WDR_Get_WDR_State(BL_Fun_Type *state); -void DSP2_WDR_Set_WDR_State(BL_Fun_Type state); -void DSP2_WDR_Set_CS_State(BL_Fun_Type state); -void DSP2_WDR_Set_CS_Config(const DSP2_Chroma_Suppress_Type *chromaSupprCfg); -void DSP2_WDR_Get_CS_Config(DSP2_Chroma_Suppress_Type *chromaSupprCfg); -void DSP2_WDR_Set_ROI_State(int roi_id, BL_Fun_Type state); -void DSP2_WDR_Set_ROI_Position(int roi_id, uint32_t left_x, uint32_t right_x, - uint32_t top_y, uint32_t bottom_y); -void DSP2_WDR_Set_ROI_Weight(int roi_id, uint32_t weight); -int DSP2_WDR_Get_Hist_Data(DSP2_WDR_Hist_Data_Type *hist); -void DSP2_WDR_Set_WDR_Curve_State(BL_Fun_Type state); -void DSP2_WDR_Set_WDR_Curve(const DSP2_WDR_Curve_Type *wdr_curve); -void DSP2_WDR_Get_WDR_Curve(DSP2_WDR_Curve_Type *wdr_curve); -void DSP2_WDR_Set_WDR_Curve_Weight(uint32_t weight); -void DSP2_WDR_Get_WDR_Curve_Weight(uint32_t *weight); -void DSP2_WDR_Set_Post_Enhance_State(BL_Fun_Type state); -void DSP2_WDR_Set_Post_Enhance_Weight(uint32_t weight); -void DSP2_WDR_Get_Post_Enhance_Weight(uint32_t *weight); -void DSP2_WDR_Set_Post_Enhance_Y_Offset(uint32_t y_offset); -void DSP2_WDR_Get_Post_Enhance_Y_Offset(uint32_t *y_offset); -void DSP2_WDR_Set_Post_Enhance_Luma_Gain(uint32_t gain); -void DSP2_WDR_Get_Post_Enhance_Luma_Gain(uint32_t *gain); -void DSP2_WDR_Set_Post_Enhance_Chroma_Gain(uint32_t gain); -void DSP2_WDR_Get_Post_Enhance_Chroma_Gain(uint32_t *gain); - -/*@} end of group DSP2_WDR_Public_Functions */ - -/*@} end of group DSP2_WDR */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_DSP2_WDR_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dvp_tsrc.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dvp_tsrc.h deleted file mode 100644 index 8fbf07e27c..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dvp_tsrc.h +++ /dev/null @@ -1,255 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_dvp_tsrc.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_DVP_TSRC_H__ -#define __BL808_DVP_TSRC_H__ - -#include "dtsrc_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup DVP_TSRC - * @{ - */ - -/** @defgroup DVP_TSRC_Public_Types - * @{ - */ - -/** - * @brief DVP_TSRC port type definition - */ -typedef enum { - DVP_TSRC0_ID, /*!< DVP TSRC0 port define */ - DVP_TSRC1_ID, /*!< DVP TSRC1 port define */ - DVP_TSRC_ID_MAX, /*!< DVP TSRC MAX ID define */ -} DVP_TSRC_ID_Type; - -/** - * @brief YUV420 valid line select type definition - */ -typedef enum { - DVP_TSRC_YUV420_LINE_EVEN, /*!< The even lines are valid, UV will send in Y even lines */ - DVP_TSRC_YUV420_LINE_ODD, /*!< The odd lines are valid, UV will send in Y odd lines */ -} DVP_TSRC_YUV420_Line_Type; - -/** - * @brief DVP_TSRC swap mode DVP2AXI type definition - */ -typedef enum { - DVP_TSRC_DVP2AXI_0, /*!< Choose DVP2AXI 0 */ - DVP_TSRC_DVP2AXI_1, /*!< Choose DVP2AXI 1 */ - DVP_TSRC_DVP2AXI_2, /*!< Choose DVP2AXI 2 */ - DVP_TSRC_DVP2AXI_3, /*!< Choose DVP2AXI 3 */ - DVP_TSRC_DVP2AXI_4, /*!< Choose DVP2AXI 4 */ - DVP_TSRC_DVP2AXI_5, /*!< Choose DVP2AXI 5 */ - DVP_TSRC_DVP2AXI_6, /*!< Choose DVP2AXI 6 */ - DVP_TSRC_DVP2AXI_7, /*!< Choose DVP2AXI 7 */ - DVP_TSRC_MJDEC_YY, /*!< Choose MJDEC YY */ - DVP_TSRC_MJDEC_UV, /*!< Choose MJDEC UV */ -} DVP_TSRC_DVP2AXI_Type; - -/** - * @brief DVP_TSRC swap index control mode type definition - */ -typedef enum { - DVP_TSRC_SWAP_HARDWARE, /*!< Swap index is controlled by hardware */ - DVP_TSRC_SWAP_SOFTWARE, /*!< Swap index is controlled by software */ -} DVP_TSRC_Swap_Control_Type; - -/** - * @brief DVP_TSRC pixel format type definition - */ -typedef enum { - DVP_TSRC_PIXEL_YUV422_16BIT, /*!< YUV422 16-bit mode */ - DVP_TSRC_PIXEL_RGB888_24BIT, /*!< RGB888 24-bit mode */ - DVP_TSRC_PIXEL_RGB565_16TO24BIT, /*!< RGB565 16-bit extend 24-bit mode */ - DVP_TSRC_PIXEL_RGBA8888_32TO24BIT, /*!< RGBA8888 32-bit compress 24-bit mode */ - DVP_TSRC_PIXEL_YUV400_8BIT, /*!< YUV400 8-bit mode */ -} DVP_TSRC_Pixel_Format_Type; - -/** - * @brief DVP_TSRC AXI burst type definition - */ -typedef enum { - DVP_TSRC_BURST_TYPE_SINGLE, /*!< DVP_TSRC AXI burst type:single */ - DVP_TSRC_BURST_TYPE_INCR4, /*!< DVP_TSRC AXI burst type:incrementing 4 */ - DVP_TSRC_BURST_TYPE_INCR8, /*!< DVP_TSRC AXI burst type:incrementing 8 */ - DVP_TSRC_BURST_TYPE_INCR16, /*!< DVP_TSRC AXI burst type:incrementing 16 */ - DVP_TSRC_BURST_TYPE_INCR32 = 5, /*!< DVP_TSRC AXI burst type:incrementing 32 */ - DVP_TSRC_BURST_TYPE_INCR64, /*!< DVP_TSRC AXI burst type:incrementing 64 */ -} DVP_TSRC_Burst_Type; - -/** - * @brief DVP_TSRC configuration structure type definition - */ -typedef struct -{ - BL_Fun_Type dataFromSensor; /*!< Enable: pixel data is from sensor, disable: pixel data is from AXI */ - BL_Fun_Type sensorHsyncInverse; /*!< Enable or disable inverse signal of sensor hsync */ - BL_Fun_Type sensorVsyncInverse; /*!< Enable or disable inverse signal of sensor vsync */ - BL_Fun_Type yuv420Enable; /*!< Enable or disable YUV420 mode, YUV420 data is from 2 different planar buffers when enable */ - DVP_TSRC_YUV420_Line_Type lineType; /*!< Select UV send in Y even lines or odd lines */ - BL_Fun_Type swapMode; /*!< Enable or disable swap mode */ - DVP_TSRC_Swap_Control_Type swapControl; /*!< Set swap index controlled by hardware or software */ - DVP_TSRC_DVP2AXI_Type dvp2axi; /*!< Choose dvp2axi used */ - DVP_TSRC_Pixel_Format_Type format; /*!< Set pixel data format */ - DVP_TSRC_Burst_Type burst; /*!< AXI burst length */ - uint8_t byte0; /*!< Byte 0 selection */ - uint8_t byte1; /*!< Byte 1 Selection */ - uint8_t byte2; /*!< Byte 2 Selection */ - uint16_t hTotalCnt; /*!< Horizontal total pixel count */ - uint16_t hBlankCnt; /*!< Horizontal blank stage pixel count */ - uint16_t vTotalCnt; /*!< Vertical total pixel count */ - uint16_t vBlankCnt; /*!< Vertical blank stage pixel count */ - uint16_t prefetch; /*!< Vertical prefetch start position, relativeto blank start position */ - uint16_t fifoThreshold; /*!< FIFO threshold for each DVP line to start to output */ - uint32_t memStartY0; /*!< AXI2DVP start address, Y-planar in YUV420 mode, frame 0 in swap mode */ - uint32_t memSizeY0; /*!< AXI2DVP memory size of memStartY0 */ - uint32_t memStartY1; /*!< AXI2DVP start address, Y-planar in YUV420 mode, frame 1 in swap mode, don't care if not swap mode */ - uint32_t memStartUV0; /*!< AXI2DVP start address, UV-planar in YUV420 mode, frame 0 in swap mode, don't care if not YUV420 mode */ - uint32_t memStartUV1; /*!< AXI2DVP start address, UV-planar in YUV420 mode, frame 1 in swap mode, don't care if not YUV420 swap mode */ -} DVP_TSRC_Cfg_Type; - -/** - * @brief DVP_TSRC fake gradient data configuration structure type definition - */ -typedef struct -{ - uint16_t minData; /*!< Minimum data value of fake gradient data */ - uint16_t maxData; /*!< Maximum data value of fake gradient data */ - uint8_t step; /*!< Data step value for eack line of fake gradient data */ -} DVP_TSRC_Fake_Data_Cfg_Type; - -/** - * @brief DVP_TSRC CEA-861 configuration structure type definition - */ -typedef struct -{ - uint8_t hsyncStart; /*!< Hsync start position, relative to blank start position */ - uint8_t hsyncEnd; /*!< Hsync end position, relative to blank start position */ - uint8_t vsyncStart; /*!< Vsync start position, relative to blank start position */ - uint8_t vsyncEnd; /*!< Vsync end position, relative to blank start position */ -} DVP_TSRC_CEA861_Cfg_Type; - -/*@} end of group DVP_TSRC_Public_Types */ - -/** @defgroup DVP_TSRC_Public_Constants - * @{ - */ - -/** @defgroup DVP_TSRC_ID_TYPE - * @{ - */ -#define IS_DVP_TSRC_ID_TYPE(type) (((type) == DVP_TSRC0_ID) || \ - ((type) == DVP_TSRC1_ID) || \ - ((type) == DVP_TSRC_ID_MAX)) - -/** @defgroup DVP_TSRC_YUV420_LINE_TYPE - * @{ - */ -#define IS_DVP_TSRC_YUV420_LINE_TYPE(type) (((type) == DVP_TSRC_YUV420_LINE_EVEN) || \ - ((type) == DVP_TSRC_YUV420_LINE_ODD)) - -/** @defgroup DVP_TSRC_DVP2AXI_TYPE - * @{ - */ -#define IS_DVP_TSRC_DVP2AXI_TYPE(type) (((type) == DVP_TSRC_DVP2AXI_0) || \ - ((type) == DVP_TSRC_DVP2AXI_1) || \ - ((type) == DVP_TSRC_DVP2AXI_2) || \ - ((type) == DVP_TSRC_DVP2AXI_3) || \ - ((type) == DVP_TSRC_DVP2AXI_4) || \ - ((type) == DVP_TSRC_DVP2AXI_5) || \ - ((type) == DVP_TSRC_DVP2AXI_6) || \ - ((type) == DVP_TSRC_DVP2AXI_7) || \ - ((type) == DVP_TSRC_MJDEC_YY) || \ - ((type) == DVP_TSRC_MJDEC_UV)) - -/** @defgroup DVP_TSRC_SWAP_CONTROL_TYPE - * @{ - */ -#define IS_DVP_TSRC_SWAP_CONTROL_TYPE(type) (((type) == DVP_TSRC_SWAP_HARDWARE) || \ - ((type) == DVP_TSRC_SWAP_SOFTWARE)) - -/** @defgroup DVP_TSRC_PIXEL_FORMAT_TYPE - * @{ - */ -#define IS_DVP_TSRC_PIXEL_FORMAT_TYPE(type) (((type) == DVP_TSRC_PIXEL_YUV422_16BIT) || \ - ((type) == DVP_TSRC_PIXEL_RGB888_24BIT) || \ - ((type) == DVP_TSRC_PIXEL_RGB565_16TO24BIT) || \ - ((type) == DVP_TSRC_PIXEL_RGBA8888_32TO24BIT) || \ - ((type) == DVP_TSRC_PIXEL_YUV400_8BIT)) - -/** @defgroup DVP_TSRC_BURST_TYPE - * @{ - */ -#define IS_DVP_TSRC_BURST_TYPE(type) (((type) == DVP_TSRC_BURST_TYPE_SINGLE) || \ - ((type) == DVP_TSRC_BURST_TYPE_INCR4) || \ - ((type) == DVP_TSRC_BURST_TYPE_INCR8) || \ - ((type) == DVP_TSRC_BURST_TYPE_INCR16) || \ - ((type) == DVP_TSRC_BURST_TYPE_INCR32) || \ - ((type) == DVP_TSRC_BURST_TYPE_INCR64)) - -/*@} end of group DVP_TSRC_Public_Constants */ - -/** @defgroup DVP_TSRC_Public_Macros - * @{ - */ - -/*@} end of group DVP_TSRC_Public_Macros */ - -/** @defgroup DVP_TSRC_Public_Functions - * @{ - */ -BL_Err_Type DVP_TSRC_Init(DVP_TSRC_ID_Type tsrcId, DVP_TSRC_Cfg_Type *dvpTsrcCfg); -void DVP_TSRC_Fake_Data_Init(DVP_TSRC_ID_Type tsrcId, DVP_TSRC_Fake_Data_Cfg_Type *dataCfg); -void DVP_TSRC_CEA861_Init(DVP_TSRC_ID_Type tsrcId, DVP_TSRC_CEA861_Cfg_Type *ceaCfg); -void DVP_TSRC_Sensor_Input_Set(DVP_TSRC_ID_Type tsrcId, uint16_t threshold, BL_Fun_Type hsyncInv, BL_Fun_Type vsyncInv); -void DVP_TSRC_Enable(DVP_TSRC_ID_Type tsrcId); -void DVP_TSRC_Disable(DVP_TSRC_ID_Type tsrcId); -void DVP_TSRC_Set_Swap_Index(DVP_TSRC_ID_Type tsrcId, uint8_t index); -void DVP_TSRC_Clear_Drain_Error(DVP_TSRC_ID_Type tsrcId); -uint32_t DVP_TSRC_Get_Status(DVP_TSRC_ID_Type tsrcId); - -/*@} end of group DVP_TSRC_Public_Functions */ - -/*@} end of group DVP_TSRC */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_DVP_TSRC_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_ef_cfg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_ef_cfg.h deleted file mode 100644 index 8fc0e24916..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_ef_cfg.h +++ /dev/null @@ -1,238 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_ef_ctrl.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_EF_CFG_H__ -#define __BL808_EF_CFG_H__ - -#include "ef_ctrl_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup EF_CTRL - * @{ - */ - -/** @defgroup EF_CTRL_Public_Types - * @{ - */ - -/** - * @brief Efuse analog device info type definition - */ -typedef struct -{ - uint8_t chipInfo; /*!< Efuse chip revision */ - uint8_t memoryInfo; /*!< Efuse memory info 0:no memory, 8:1MB flash */ - uint8_t psramInfo; /*!< Efuse psram info 0:no psram, 1:BW 4MB, 2:UHS 64MB */ - uint8_t deviceInfo; /*!< Efuse device information */ -} Efuse_Chip_Info_Type; - -/** - * @brief Efuse analog ldo15rf vout sel aon type definition - */ -typedef struct -{ - uint32_t trimLDO15RFVoutAon : 3; /*!< Efuse analog trim:ldo15rf_vout_sel_aon */ - uint32_t trimLDO15RFVoutAonParity : 1; /*!< Efuse analog trim:ldo15rf_vout_sel_aon_parity */ - uint32_t trimLDO15RFVoutAonEn : 1; /*!< Efuse analog trim:ldo15rf_vout_sel_aon_en */ - uint32_t reserved : 27; /*!< Efuse analog trim:reserved */ -} Efuse_Ana_LDO15RF_Vout_Sel_Type; - -/** - * @brief Efuse analog rcal iptat code type definition - */ -typedef struct -{ - uint32_t trimRcalIptatCode : 5; /*!< Efuse analog trim:rcal_iptat_code */ - uint32_t trimRcalIptatCodeParity : 1; /*!< Efuse analog trim:rcal_iptat_code_parity */ - uint32_t trimRcalIptatCodeEn : 1; /*!< Efuse analog trim:rcal_iptat_code_en */ - uint32_t reserved : 25; /*!< Efuse analog trim:reserved */ -} Efuse_Ana_Rcal_Iptat_Code_Type; - -/** - * @brief Efuse analog rcal icx code type definition - */ -typedef struct -{ - uint32_t trimRcalIcxCode : 6; /*!< Efuse analog trim:rcal_icx_code */ - uint32_t trimRcalIcxCodeParity : 1; /*!< Efuse analog trim:rcal_icx_code_parity */ - uint32_t trimRcalIcxCodeEn : 1; /*!< Efuse analog trim:rcal_icx_code_en */ - uint32_t reserved : 24; /*!< Efuse analog trim:reserved */ -} Efuse_Ana_Rcal_Icx_Code_Type; - -/** - * @brief Efuse analog LDO28CIS vout trim type definition - */ -typedef struct -{ - uint32_t trimLDO28CISVout : 4; /*!< Efuse analog trim:ldo28cis_vout_trim */ - uint32_t trimLDO28CISVoutParity : 1; /*!< Efuse analog trim:ldo28cis_vout_trim_parity */ - uint32_t trimLDO28CISVoutEn : 1; /*!< Efuse analog trim:ldo28cis_vout_trim_en */ - uint32_t reserved : 26; /*!< Efuse analog trim:reserved */ -} Efuse_Ana_LDO28CIS_Vout_Trim_Type; - -/** - * @brief Efuse analog LDO15CIS vout trim type definition - */ -typedef struct -{ - uint32_t trimLDO15CISVout : 4; /*!< Efuse analog trim:ldo15cis_vout_trim */ - uint32_t trimLDO15CISVoutParity : 1; /*!< Efuse analog trim:ldo15cis_vout_trim_parity */ - uint32_t trimLDO15CISVoutEn : 1; /*!< Efuse analog trim:ldo15cis_vout_trim_en */ - uint32_t reserved : 26; /*!< Efuse analog trim:reserved */ -} Efuse_Ana_LDO15CIS_Vout_Trim_Type; - -/** - * @brief Efuse analog LDO12UHS vout trim type definition - */ -typedef struct -{ - uint32_t trimLDO12UHSVout : 4; /*!< Efuse analog trim:ldo12uhs_vout_trim */ - uint32_t trimLDO12UHSVoutParity : 1; /*!< Efuse analog trim:ldo12uhs_vout_trim_parity */ - uint32_t trimLDO12UHSVoutEn : 1; /*!< Efuse analog trim:ldo12uhs_vout_trim_en */ - uint32_t reserved : 26; /*!< Efuse analog trim:reserved */ -} Efuse_Ana_LDO12UHS_Vout_Trim_Type; - -/** - * @brief Efuse analog xtal capcode 1 inout type definition - */ -typedef struct -{ - uint32_t trimXtalCapcode1 : 6; /*!< Efuse analog trim:ctal_capcode_1_inout */ - uint32_t trimXtalCapcode1Parity : 1; /*!< Efuse analog trim:ctal_capcode_1_inout_parity */ - uint32_t trimXtalCapcode1En : 1; /*!< Efuse analog trim:ctal_capcode_1_inout_en */ - uint32_t reserved : 24; /*!< Efuse analog trim:reserved */ -} Efuse_Ana_Xtal_Capcode_1_Type; - -/** - * @brief Efuse analog xtal capcode 2 inout type definition - */ -typedef struct -{ - uint32_t trimXtalCapcode2 : 6; /*!< Efuse analog trim:ctal_capcode_2_inout */ - uint32_t trimXtalCapcode2Parity : 1; /*!< Efuse analog trim:ctal_capcode_2_inout_parity */ - uint32_t trimXtalCapcode2En : 1; /*!< Efuse analog trim:ctal_capcode_2_inout_en */ - uint32_t reserved : 24; /*!< Efuse analog trim:reserved */ -} Efuse_Ana_Xtal_Capcode_2_Type; - -/** - * @brief Efuse analog xtal capcode 3 inout type definition - */ -typedef struct -{ - uint32_t trimXtalCapcode3 : 6; /*!< Efuse analog trim:ctal_capcode_3_inout */ - uint32_t trimXtalCapcode3Parity : 1; /*!< Efuse analog trim:ctal_capcode_3_inout_parity */ - uint32_t trimXtalCapcode3En : 1; /*!< Efuse analog trim:ctal_capcode_3_inout_en */ - uint32_t reserved : 24; /*!< Efuse analog trim:reserved */ -} Efuse_Ana_Xtal_Capcode_3_Type; - -/** - * @brief Efuse analog gauge vpack offset type definition - */ -typedef struct -{ - uint32_t trimGaugeVpackOffset : 16; /*!< Efuse analog trim:gauge_vpack_offset */ - uint32_t trimGaugeVpackOffsetParity : 1; /*!< Efuse analog trim:gauge_vpack_offset_parity */ - uint32_t trimGaugeVpackOffsetEn : 1; /*!< Efuse analog trim:gauge_vpack_offset_en */ - uint32_t reserved : 14; /*!< Efuse analog trim:reserved */ -} Efuse_Ana_Gauge_Vpack_Offset_Type; - -/** - * @brief Efuse analog gauge vtemp offset type definition - */ -typedef struct -{ - uint32_t trimGaugeVtempOffset : 16; /*!< Efuse analog trim:gauge_vtemp_offset */ - uint32_t trimGaugeVtempOffsetParity : 1; /*!< Efuse analog trim:gauge_vtemp_offset_parity */ - uint32_t trimGaugeVtempOffsetEn : 1; /*!< Efuse analog trim:gauge_vtemp_offset_en */ - uint32_t reserved : 14; /*!< Efuse analog trim:reserved */ -} Efuse_Ana_Gauge_Vtemp_Offset_Type; - -/** - * @brief Efuse psram trim type definition - */ -typedef struct -{ - uint32_t psramTrim : 11; /*!< Efuse analog trim:psram trim date */ - uint32_t psramTrimParity : 1; /*!< Efuse analog trim:psram trim_parity */ - uint32_t psramTrimEn : 1; /*!< Efuse analog trim:psram trim_en */ - uint32_t reserved : 19; /*!< Efuse analog trim:reserved */ -} Efuse_Psram_Trim_Type; - -/*@} end of group EF_CTRL_Public_Types */ - -/** @defgroup EF_CTRL_Public_Constants - * @{ - */ - -/*@} end of group EF_CTRL_Public_Constants */ - -/** @defgroup EF_CTRL_Public_Macros - * @{ - */ - -/*@} end of group EF_CTRL_Public_Macros */ - -/** @defgroup EF_CTRL_Public_Functions - * @{ - */ -void EF_Ctrl_Get_Chip_Info(Efuse_Chip_Info_Type *chipInfo); -void EF_Ctrl_Read_LDO15RF_Vout_Sel(Efuse_Ana_LDO15RF_Vout_Sel_Type *trim); -void EF_Ctrl_Read_Rcal_Iptat_Code(Efuse_Ana_Rcal_Iptat_Code_Type *trim); -void EF_Ctrl_Read_Rcal_Icx_Code(Efuse_Ana_Rcal_Icx_Code_Type *trim); -void EF_Ctrl_Read_LDO28CIS_Vout_Trim(Efuse_Ana_LDO28CIS_Vout_Trim_Type *trim); -void EF_Ctrl_Read_LDO15CIS_Vout_Trim(Efuse_Ana_LDO15CIS_Vout_Trim_Type *trim); -void EF_Ctrl_Read_LDO12UHS_Vout_Trim(Efuse_Ana_LDO12UHS_Vout_Trim_Type *trim); -void EF_Ctrl_Read_Xtal_Capcode1_Inout(Efuse_Ana_Xtal_Capcode_1_Type *trim); -void EF_Ctrl_Read_Xtal_Capcode2_Inout(Efuse_Ana_Xtal_Capcode_2_Type *trim); -void EF_Ctrl_Read_Xtal_Capcode3_Inout(Efuse_Ana_Xtal_Capcode_3_Type *trim); -void EF_Ctrl_Read_Gauge_Vpack_Offset(Efuse_Ana_Gauge_Vpack_Offset_Type *trim); -void EF_Ctrl_Read_Gauge_Vtemp_Offset(Efuse_Ana_Gauge_Vtemp_Offset_Type *trim); -void EF_Ctrl_Read_Psram_Trim(Efuse_Psram_Trim_Type *trim); -void EF_Ctrl_Write_Psram_Trim(Efuse_Psram_Trim_Type *trim, uint8_t program); -uint8_t EF_Ctrl_Is_MAC_Address_Slot_Empty(uint8_t slot, uint8_t reload); -BL_Err_Type EF_Ctrl_Write_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t program); -BL_Err_Type EF_Ctrl_Read_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t reload); - -/*@} end of group EF_CTRL_Public_Functions */ - -/*@} end of group EF_CTRL */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_EF_CFG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_emac.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_emac.h deleted file mode 100644 index 38fdb8aac3..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_emac.h +++ /dev/null @@ -1,360 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_emac.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_EMAC_H__ -#define __BL808_EMAC_H__ - -#include "emac_reg.h" -#include "bl808_common.h" - - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup EMAC - * @{ - */ - -/** @defgroup EMAC_Public_Types - * @{ - */ - -typedef enum { - EMAC0_ID, /*!< EMAC0 port define */ - EMAC_ID_MAX, /*!< I2S MAX ID define */ -} EMAC_ID_Type; - -/** - * @brief EMAC half/full-duplex type definition - */ -typedef enum { - EMAC_MODE_HALFDUPLEX, /*!< ETH half-duplex */ - EMAC_MODE_FULLDUPLEX, /*!< ETH full-duplex */ -} EMAC_Duplex_Type; - -/** - * @brief EMAC speed type definition - */ -typedef enum { - EMAC_SPEED_10M, /*!< ETH speed 10M */ - EMAC_SPEED_100M, /*!< ETH speed 100M */ -} EMAC_Speed_Type; - -/** - * @brief EMAC interrupt type definition - */ -typedef enum { - EMAC_INT_TX_DONE = 0x01, /*!< Transmit one frame done */ - EMAC_INT_TX_ERROR = 0x02, /*!< Transmit error occur */ - EMAC_INT_RX_DONE = 0x04, /*!< Receive one frame done */ - EMAC_INT_RX_ERROR = 0x08, /*!< Receive error occur */ - EMAC_INT_RX_BUSY = 0x10, /*!< Receive busy due to no free RX buffer Descripter */ - EMAC_INT_TX_CTRL = 0x20, /*!< Transmit control frame */ - EMAC_INT_RX_CTRL = 0x40, /*!< Receive control frame */ - EMAC_INT_ALL = 0x7F, /*!< */ -} EMAC_INT_Type; - -/** - * @brief EMAC interrupt Index - */ -typedef enum { - EMAC_INT_TX_DONE_IDX = 0x0, /*!< Transmit one frame done */ - EMAC_INT_TX_ERROR_IDX = 0x1, /*!< Transmit error occur */ - EMAC_INT_RX_DONE_IDX = 0x2, /*!< Receive one frame done */ - EMAC_INT_RX_ERROR_IDX = 0x3, /*!< Receive error occur */ - EMAC_INT_RX_BUSY_IDX = 0x4, /*!< Receive busy due to no free RX buffer Descripter */ - EMAC_INT_TX_CTRL_IDX = 0x5, /*!< Transmit control frame */ - EMAC_INT_RX_CTRL_IDX = 0x6, /*!< Receive control frame */ - EMAC_INT_CNT, /*!< EMAC INT source count */ -} EMAC_INT_Index; - -/** - * @brief EMAC configuration type definition - */ -typedef struct -{ - BL_Fun_Type recvSmallFrame; /*!< Receive small frmae or not */ - BL_Fun_Type recvHugeFrame; /*!< Receive huge frmae(>64K bytes) or not */ - BL_Fun_Type padEnable; /*!< Enable padding for frame which is less than MINFL or not */ - BL_Fun_Type crcEnable; /*!< Enable hardware CRC or not */ - BL_Fun_Type noPreamble; /*!< Enable preamble or not */ - BL_Fun_Type recvBroadCast; /*!< Receive broadcast frame or not */ - BL_Fun_Type interFrameGapCheck; /*!< Check inter frame gap or not */ - BL_Fun_Type miiNoPreamble; /*!< Enable MII interface preamble or not */ - uint8_t miiClkDiv; /*!< MII interface clock divider from bus clock */ - uint8_t maxTxRetry; /*!< Maximum tx retry count */ - uint16_t interFrameGapValue; /*!< Inter frame gap vaule in clock cycles(default 24),which equals 9.6 us for 10 Mbps and 0.96 us - for 100 Mbps mode */ - uint16_t minFrameLen; /*!< Minimum frame length */ - uint16_t maxFrameLen; /*!< Maximum frame length */ - uint16_t collisionValid; /*!< Collision valid value */ - uint8_t macAddr[6]; /*!< MAC Address */ -} EMAC_CFG_Type; - - -/** - * @brief EMAC TX DMA description type definition - */ -typedef struct -{ - uint32_t CS : 1; /*!< Carrier Sense Lost */ - uint32_t DF : 1; /*!< Defer Indication */ - uint32_t LC : 1; /*!< Late Collision */ - uint32_t RL : 1; /*!< Retransmission Limit */ - uint32_t RC : 4; /*!< Retry Count */ - uint32_t UR : 1; /*!< Underrun */ - uint32_t RSVD : 1; /*!< Reserved */ - uint32_t EoF : 1; /*!< EOF or not */ - uint32_t CRC : 1; /*!< CRC Enable */ - uint32_t PAD : 1; /*!< PAD enable */ - uint32_t WR : 1; /*!< Wrap */ - uint32_t IRQ : 1; /*!< Interrupt Request Enable */ - uint32_t Busy : 1; /*!< The data buffer is ready for transmission or is currently being transmitted. You are not - allowed to change it */ - uint32_t TxLen : 16; /*!< TX Data buffer length */ - uint32_t TXBuffer; /*!< TX buffer address */ -} EMAC_Tx_DMA_Desc_Type; - -/** - * @brief EMAC RX DMA description type definition - */ -typedef struct -{ - uint32_t LC : 1; /*!< Late Collision */ - uint32_t CRC : 1; /*!< RX CRC Error */ - uint32_t SF : 1; /*!< Short Frame */ - uint32_t TL : 1; /*!< Too Long */ - uint32_t DN : 4; /*!< Dribble Nibble */ - uint32_t RE : 1; /*!< Receive Error */ - uint32_t OR : 1; /*!< Overrun */ - uint32_t M : 1; /*!< Miss */ - uint32_t CF : 1; /*!< Control Frame */ - uint32_t RSVD : 4; /*!< PAD enable */ - uint32_t WR : 1; /*!< Wrap */ - uint32_t IRQ : 1; /*!< Interrupt Request Enable */ - uint32_t Empty : 1; /*!< The data buffer is empty (and ready for receiving data) or currently receiving data */ - uint32_t RxLen : 16; /*!< RX Data buffer length */ - uint32_t RXBuffer; /*!< RX buffer address */ -} EMAC_Rx_DMA_Desc_Type; - -/** - * @brief Note: Always write DWORD1 (buffer addr) first then DWORD0 for racing concern. - */ -typedef struct -{ - uint32_t C_S_L; /*!< Buffer Descriptors(BD) control,status,length */ - uint32_t Buffer; /*!< BD buffer address */ -} EMAC_BD_Desc_Type; - -/** - * @brief EMAC Handle type definition - */ -typedef struct -{ - EMAC_BD_Desc_Type *bd; /*!< Tx descriptor header pointer */ - uint8_t txIndexEMAC; /*!< TX index: EMAC */ - uint8_t txIndexCPU; /*!< TX index: CPU/SW */ - uint8_t txBuffLimit; /*!< TX index max */ - uint8_t rsv0; /*!< RSV0 */ - uint8_t rxIndexEMAC; /*!< RX index: EMAC */ - uint8_t rxIndexCPU; /*!< RX index: CPU/SW */ - uint8_t rxBuffLimit; /*!< RX index max */ - uint8_t rsv1; /*!< rsv1 */ -} EMAC_Handle_Type; - -/*@} end of group EMAC_Public_Types */ - -/** @defgroup EMAC_Public_Constants - * @{ - */ - -/** @defgroup EMAC_ID_TYPE - * @{ - */ -#define IS_EMAC_ID_TYPE(type) (((type) == EMAC0_ID) || \ - ((type) == EMAC_ID_MAX)) - -/** @defgroup EMAC_DUPLEX_TYPE - * @{ - */ -#define IS_EMAC_DUPLEX_TYPE(type) (((type) == EMAC_MODE_HALFDUPLEX) || \ - ((type) == EMAC_MODE_FULLDUPLEX)) - -/** @defgroup EMAC_SPEED_TYPE - * @{ - */ -#define IS_EMAC_SPEED_TYPE(type) (((type) == EMAC_SPEED_10M) || \ - ((type) == EMAC_SPEED_100M)) - -/** @defgroup EMAC_INT_TYPE - * @{ - */ -#define IS_EMAC_INT_TYPE(type) (((type) == EMAC_INT_TX_DONE) || \ - ((type) == EMAC_INT_TX_ERROR) || \ - ((type) == EMAC_INT_RX_DONE) || \ - ((type) == EMAC_INT_RX_ERROR) || \ - ((type) == EMAC_INT_RX_BUSY) || \ - ((type) == EMAC_INT_TX_CTRL) || \ - ((type) == EMAC_INT_RX_CTRL) || \ - ((type) == EMAC_INT_ALL)) - -/** @defgroup EMAC_INT_INDEX - * @{ - */ -#define IS_EMAC_INT_INDEX(type) (((type) == EMAC_INT_TX_DONE_IDX) || \ - ((type) == EMAC_INT_TX_ERROR_IDX) || \ - ((type) == EMAC_INT_RX_DONE_IDX) || \ - ((type) == EMAC_INT_RX_ERROR_IDX) || \ - ((type) == EMAC_INT_RX_BUSY_IDX) || \ - ((type) == EMAC_INT_TX_CTRL_IDX) || \ - ((type) == EMAC_INT_RX_CTRL_IDX) || \ - ((type) == EMAC_INT_CNT)) - -/*@} end of group EMAC_Public_Constants */ - -/** @defgroup EMAC_Public_Macros - * @{ - */ -#define BD_TX_CS_POS (0) /*!< Carrier Sense Lost */ -#define BD_TX_CS_LEN (1) -#define BD_TX_DF_POS (1) /*!< Defer Indication */ -#define BD_TX_DF_LEN (1) -#define BD_TX_LC_POS (2) /*!< Late Collision */ -#define BD_TX_LC_LEN (1) -#define BD_TX_RL_POS (3) /*!< Retransmission Limit */ -#define BD_TX_RL_LEN (1) -#define BD_TX_RTRY_POS (4) /*!< Retry Count */ -#define BD_TX_RTRY_LEN (4) -#define BD_TX_UR_POS (8) /*!< Underrun */ -#define BD_TX_UR_LEN (1) -#define BD_TX_EOF_POS (10) /*!< EOF */ -#define BD_TX_EOF_LEN (1) -#define BD_TX_CRC_POS (11) /*!< CRC Enable */ -#define BD_TX_CRC_LEN (1) -#define BD_TX_PAD_POS (12) /*!< PAD enable */ -#define BD_TX_PAD_LEN (1) -#define BD_TX_WR_POS (13) /*!< Wrap */ -#define BD_TX_WR_LEN (1) -#define BD_TX_IRQ_POS (14) /*!< Interrupt Request Enable */ -#define BD_TX_IRQ_LEN (1) -#define BD_TX_RD_POS (15) /*!< The data buffer is ready for transmission or is currently being transmitted. You are not allowed to change it */ -#define BD_TX_RD_LEN (1) -#define BD_TX_LEN_POS (16) /*!< TX Data buffer length */ -#define BD_TX_LEN_LEN (16) -#define BD_RX_LC_POS (0) /*!< Late Collision */ -#define BD_RX_LC_LEN (1) -#define BD_RX_CRC_POS (1) /*!< RX CRC Error */ -#define BD_RX_CRC_LEN (1) -#define BD_RX_SF_POS (2) /*!< Short Frame */ -#define BD_RX_SF_LEN (1) -#define BD_RX_TL_POS (3) /*!< Too Long */ -#define BD_RX_TL_LEN (1) -#define BD_RX_DN_POS (4) /*!< Dribble Nibble */ -#define BD_RX_DN_LEN (1) -#define BD_RX_RE_POS (5) /*!< Receive Error */ -#define BD_RX_RE_LEN (1) -#define BD_RX_OR_POS (6) /*!< Overrun */ -#define BD_RX_OR_LEN (1) -#define BD_RX_M_POS (7) /*!< Miss */ -#define BD_RX_M_LEN (1) -#define BD_RX_CF_POS (8) /*!< Control Frame Received */ -#define BD_RX_CF_LEN (1) -#define BD_RX_WR_POS (13) /*!< Wrap */ -#define BD_RX_WR_LEN (1) -#define BD_RX_IRQ_POS (14) /*!< Interrupt Request Enable */ -#define BD_RX_IRQ_LEN (1) -#define BD_RX_E_POS (15) /*!< The data buffer is empty (and ready for receiving data) or currently receiving data */ -#define BD_RX_E_LEN (1) -#define BD_RX_LEN_POS (16) /*!< RX Data buffer length */ -#define BD_RX_LEN_LEN (16) -#define EMAC_BD_FIELD_MSK(field) (((1U << BD_##field##_LEN) - 1) << BD_##field##_POS) -#define EMAC_BD_FIELD_UMSK(field) (~(((1U << BD_##field##_LEN) - 1) << BD_##field##_POS)) -/* DMA Descriptor offset */ -#define EMAC_DMA_DESC_OFFSET 0x400 - -/* ETH packet size */ -// ETH | Header | Extra | VLAN tag | Payload | CRC | -// Size | 14 | 2 | 4 | 46 ~ 1500 | 4 | -#define ETH_MAX_PACKET_SIZE ((uint32_t)1524U) /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */ -#define ETH_HEADER_SZIE ((uint32_t)14U) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ -#define ETH_CRC_SIZE ((uint32_t)4U) /*!< Ethernet CRC */ -#define ETH_EXTRA_SIZE ((uint32_t)2U) /*!< Extra bytes in some cases */ -#define ETH_VLAN_TAG_SIZE ((uint32_t)4U) /*!< optional 802.1q VLAN Tag */ -#define ETH_MIN_ETH_PAYLOAD_SIZE ((uint32_t)46U) /*!< Minimum Ethernet payload size */ -#define ETH_MAX_ETH_PAYLOAD_SIZE ((uint32_t)1500U) /*!< Maximum Ethernet payload size */ -#define ETH_JUMBO_FRAME_PAYLOAD_SIZE ((uint32_t)9000U) /*!< Jumbo frame payload size */ - -/*@} end of group EMAC_Public_Macros */ - -/** @defgroup EMAC_Public_Functions - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -void EMAC_IRQHandler(EMAC_ID_Type emacId); -void EMAC0_IRQHandler(); -#endif -BL_Err_Type EMAC_Init(EMAC_ID_Type emacId, EMAC_CFG_Type *cfg); -BL_Err_Type EMAC_DeInit(EMAC_ID_Type emacId); -BL_Err_Type EMAC_DMADescListInit(EMAC_ID_Type emacId, EMAC_Handle_Type *handle, uint8_t *txBuff, uint32_t txBuffCount, - uint8_t *rxBuff, uint32_t rxBuffCount); -BL_Err_Type EMAC_DMATxDescGet(EMAC_Handle_Type *handle, EMAC_BD_Desc_Type **txDMADesc); -BL_Err_Type EMAC_StartTx(EMAC_Handle_Type *handle, EMAC_BD_Desc_Type *txDMADesc, uint32_t len); -BL_Err_Type EMAC_Enable(EMAC_ID_Type emacId); -BL_Err_Type EMAC_Disable(EMAC_ID_Type emacId); -BL_Err_Type EMAC_IntMask(EMAC_ID_Type emacId, EMAC_INT_Type intType, BL_Mask_Type intMask); -BL_Sts_Type EMAC_GetIntStatus(EMAC_ID_Type emacId, EMAC_INT_Type intType); -BL_Err_Type EMAC_ClrIntStatus(EMAC_ID_Type emacId, EMAC_INT_Type intType); -BL_Err_Type EMAC_Int_Callback_Install(EMAC_ID_Type emacId, EMAC_INT_Index intIdx, intCallback_Type *cbFun); -BL_Err_Type EMAC_TxPauseReq(EMAC_ID_Type emacId, uint16_t timeCount); -BL_Err_Type EMAC_SetHash(EMAC_ID_Type emacId, uint32_t hash0, uint32_t hash1); -BL_Err_Type EMAC_Phy_Read(EMAC_ID_Type emacId, uint16_t phyReg, uint16_t *regValue); -BL_Err_Type EMAC_Phy_Write(EMAC_ID_Type emacId, uint16_t phyReg, uint16_t regValue); -BL_Err_Type EMAC_Enable_TX(EMAC_ID_Type emacId); -BL_Err_Type EMAC_Disable_TX(EMAC_ID_Type emacId); -BL_Err_Type EMAC_Enable_RX(EMAC_ID_Type emacId); -BL_Err_Type EMAC_Disable_RX(EMAC_ID_Type emacId); -BL_Err_Type EMAC_GetFramLen(EMAC_ID_Type emacId, uint16_t * max, uint16_t *min); -BL_Err_Type EMAC_GetBD(EMAC_ID_Type emacId, uint32_t *bd); -void EMAC_Phy_SetAddress(EMAC_ID_Type emacId,uint16_t phyAddress); -void EMAC_Phy_Set_Full_Duplex(EMAC_ID_Type emacId,uint8_t fullDuplex); - -/*@} end of group EMAC_Public_Functions */ - -/*@} end of group EMAC */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_EMAC_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_i2c.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_i2c.h deleted file mode 100644 index ca897bd2ac..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_i2c.h +++ /dev/null @@ -1,210 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_i2c.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_I2C_H__ -#define __BL808_I2C_H__ - -#include "i2c_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup I2C - * @{ - */ - -/** @defgroup I2C_Public_Types - * @{ - */ - -/** - * @brief I2C No. type definition - */ -typedef enum { - I2C0_ID = 0, /*!< I2C0 define */ - I2C1_ID = 1, /*!< I2C1 define */ - I2C0_MM_ID = 2, /*!< MM system I2C0 define */ - I2C1_MM_ID = 3, /*!< MM system I2C1 define */ - I2C_ID_MAX, /*!< I2C max define */ -} I2C_ID_Type; - -/** - * @brief I2C read/write type definition - */ -typedef enum { - I2C_WRITE = 0, /*!< I2C write direction */ - I2C_READ, /*!< I2C read direction */ -} I2C_Direction_Type; - -/** - * @brief I2C interrupt type definition - */ -typedef enum { - I2C_TRANS_END_INT, /*!< I2C transfer end interrupt */ - I2C_TX_FIFO_READY_INT, /*!< I2C TX fifo ready interrupt */ - I2C_RX_FIFO_READY_INT, /*!< I2C RX fifo ready interrupt */ - I2C_NACK_RECV_INT, /*!< I2C nack received interrupt */ - I2C_ARB_LOST_INT, /*!< I2C arbitration lost interrupt */ - I2C_FIFO_ERR_INT, /*!< I2C TX/RX FIFO error interrupt */ - I2C_INT_ALL, /*!< I2C interrupt all type */ -} I2C_INT_Type; - -/** - * @brief I2S start condition phase structure type definition - */ -typedef struct -{ - uint8_t len0; /*!< Length of START condition phase 0 */ - uint8_t len1; /*!< Length of START condition phase 1 */ - uint8_t len2; /*!< Length of START condition phase 2 */ - uint8_t len3; /*!< Length of START condition phase 3 */ -} I2C_Start_Condition_Phase_Type; - -/** - * @brief I2S stop condition phase structure type definition - */ -typedef struct -{ - uint8_t len0; /*!< Length of STOP condition phase 0 */ - uint8_t len1; /*!< Length of STOP condition phase 1 */ - uint8_t len2; /*!< Length of STOP condition phase 2 */ - uint8_t len3; /*!< Length of STOP condition phase 3 */ -} I2C_Stop_Condition_Phase_Type; - -/** - * @brief I2S data phase structure type definition - */ -typedef struct -{ - uint8_t len0; /*!< Length of DATA phase 0 */ - uint8_t len1; /*!< Length of DATA phase 1 */ - uint8_t len2; /*!< Length of DATA phase 2 */ - uint8_t len3; /*!< Length of DATA phase 3 */ -} I2C_Data_Phase_Type; - -/** - * @brief I2S transfer structure type definition - */ -typedef struct -{ - uint16_t slaveAddr; /*!< I2C slave address */ - BL_Fun_Type slaveAddr10Bit; /*!< Enable or disable slave address 10-bit mode */ - BL_Fun_Type stopEveryByte; /*!< I2C all data byte with stop bit */ - uint8_t subAddrSize; /*!< Specifies the size of I2C sub address section */ - uint32_t subAddr; /*!< I2C sub address */ - uint16_t dataSize; /*!< Specifies the size of I2C data section */ - uint8_t *data; /*!< Specifies the pointer of I2C R/W data */ - uint32_t clk; /*!< I2C clk:default is 400k */ -} I2C_Transfer_Cfg; - -/*@} end of group I2C_Public_Types */ - -/** @defgroup I2C_Public_Constants - * @{ - */ - -/** @defgroup I2C_ID_TYPE - * @{ - */ -#define IS_I2C_ID_TYPE(type) (((type) == I2C0_ID) || \ - ((type) == I2C1_ID) || \ - ((type) == I2C0_MM_ID) || \ - ((type) == I2C1_MM_ID) || \ - ((type) == I2C_ID_MAX)) - -/** @defgroup I2C_DIRECTION_TYPE - * @{ - */ -#define IS_I2C_DIRECTION_TYPE(type) (((type) == I2C_WRITE) || \ - ((type) == I2C_READ)) - -/** @defgroup I2C_INT_TYPE - * @{ - */ -#define IS_I2C_INT_TYPE(type) (((type) == I2C_TRANS_END_INT) || \ - ((type) == I2C_TX_FIFO_READY_INT) || \ - ((type) == I2C_RX_FIFO_READY_INT) || \ - ((type) == I2C_NACK_RECV_INT) || \ - ((type) == I2C_ARB_LOST_INT) || \ - ((type) == I2C_FIFO_ERR_INT) || \ - ((type) == I2C_INT_ALL)) - -/*@} end of group I2C_Public_Constants */ - -/** @defgroup I2C_Public_Macros - * @{ - */ - -/*@} end of group I2C_Public_Macros */ - -/** @defgroup I2C_Public_Functions - * @{ - */ - -/** - * @brief I2C Functions - */ -#ifndef BFLB_USE_HAL_DRIVER -void I2C0_IRQHandler(void); -void I2C1_IRQHandler(void); -void I2C2_IRQHandler(void); -void I2C3_IRQHandler(void); -#endif -BL_Err_Type I2C_SendWord(I2C_ID_Type i2cNo, uint32_t data); -BL_Err_Type I2C_RecieveWord(I2C_ID_Type i2cNo, uint32_t *recvBuff); -void I2C_Enable(I2C_ID_Type i2cNo); -void I2C_Disable(I2C_ID_Type i2cNo); -BL_Err_Type I2C_SetDeglitchCount(I2C_ID_Type i2cNo, uint8_t cnt); -BL_Err_Type I2C_DeInit(I2C_ID_Type i2cNo); -void I2C_SetPrd(I2C_ID_Type i2cNo, uint8_t phase); -void I2C_ClockSet(I2C_ID_Type i2cNo, uint32_t clk); -void I2C_SetSclSync(I2C_ID_Type i2cNo, uint8_t enable); -void I2C_Init(I2C_ID_Type i2cNo, I2C_Direction_Type direct, I2C_Transfer_Cfg *cfg); -BL_Sts_Type I2C_IsBusy(I2C_ID_Type i2cNo); -BL_Sts_Type I2C_TransferEndStatus(I2C_ID_Type i2cNo); -BL_Err_Type I2C_MasterSendBlocking(I2C_ID_Type i2cNo, I2C_Transfer_Cfg *cfg); -BL_Err_Type I2C_MasterReceiveBlocking(I2C_ID_Type i2cNo, I2C_Transfer_Cfg *cfg); -void I2C_IntMask(I2C_ID_Type i2cNo, I2C_INT_Type intType, BL_Mask_Type intMask); -void I2C_Int_Callback_Install(I2C_ID_Type i2cNo, I2C_INT_Type intType, intCallback_Type *cbFun); - -/*@} end of group I2C_Public_Functions */ - -/*@} end of group I2C */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_I2C_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_i2s.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_i2s.h deleted file mode 100644 index 30d6e85d2d..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_i2s.h +++ /dev/null @@ -1,309 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_i2s.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_I2S_H__ -#define __BL808_I2S_H__ - -#include "i2s_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup I2S - * @{ - */ - -/** @defgroup I2S_Public_Types - * @{ - */ - -/** - * @brief I2S mode type definition - */ -typedef enum { - I2S_MODE_I2S_LEFT, /*!< Left-Justified Mode */ - I2S_MODE_I2S_RIGHT, /*!< Right-Justified Mode */ - I2S_MODE_I2S_DSP, /*!< DSP Mode */ -} I2S_Mode_Type; - -typedef enum { - I2S0_ID, /*!< I2S0 port define */ - I2S_ID_MAX, /*!< I2S MAX ID define */ -} I2S_ID_Type; - -/** - * @brief I2S role type definition - */ -typedef enum { - I2S_ROLE_MASTER = 0, /*!< I2S as master */ - I2S_ROLE_SLAVE = 1, /*!< I2S as slave */ -} I2S_Role_Type; - -/** - * @brief I2S data size type definition - */ -typedef enum { - I2S_SIZE_DATA_8 = 0, /*!< I2S data size 8 bits */ - I2S_SIZE_DATA_16, /*!< I2S data size 16 bits */ - I2S_SIZE_DATA_24, /*!< I2S data size 24 bits */ - I2S_SIZE_DATA_32, /*!< I2S data size 32 bits */ -} I2S_Data_Size_Type; - -/** - * @brief I2S frame size type definition - */ -typedef enum { - I2S_SIZE_FRAME_8 = 0, /*!< I2S frame size 8 bits */ - I2S_SIZE_FRAME_16, /*!< I2S frame size 16 bits */ - I2S_SIZE_FRAME_24, /*!< I2S frame size 24 bits */ - I2S_SIZE_FRAME_32, /*!< I2S frame size 32 bits */ -} I2S_Frame_Size_Type; - -/** - * @brief I2S endian data type definition - */ -typedef enum { - I2S_DATA_ENDIAN_MSB = 0, /*!< I2S use MSB first */ - I2S_DATA_ENDIAN_LSB, /*!< I2S use LSB first */ -} I2S_Endian_Type; - -/** - * @brief I2S frame select mode type definition - */ -typedef enum { - I2S_FS_MODE_EVEN = 0, /*!< I2S frame is even */ - I2S_FS_MODE_1T, /*!< I2S frame is only 1T high */ -} I2S_Fs_Mode_Type; - -/** - * @brief I2S rx mono mode channel select type definition - */ -typedef enum { - I2S_RX_MONO_MODE_LEFT_CHANNEL, /*!< I2S rx mono mode left channel */ - I2S_RX_MONO_MODE_RIGHT_CHANNEL, /*!< I2S rx mono mode right channel */ -} I2S_Mono_Mode_Channel; - -/** - * @brief I2S frame channel mode type definition - */ -typedef enum { - I2S_FS_CHANNELS_2 = 0, /*!< I2S frame is for 2 channels */ - I2S_FS_CHANNELS_3, /*!< I2S frame is for 3 channels */ - I2S_FS_CHANNELS_4, /*!< I2S frame is for 4 channels */ - I2S_FS_CHANNELS_6, /*!< I2S frame is for 6 channels */ -} I2S_Fs_Channel_Type; - -/** - * @brief I2S mono control definition - */ -typedef enum { - I2S_MONO_CONTROL_STEREO = 0, /*!< I2S output stereo */ - I2S_MONO_CONTROL_MONO, /*!< I2S output mono */ -} I2S_MonoControl_Type; - -/** - * @brief I2S fifo 24-bit data align type definition - */ -typedef enum { - I2S_FIFO_24_RIGHT_JUSTIFIED = 0, /*!< I2S fifo:[31:24]0x00,[23:0]24bit_data */ - I2S_FIFO_24_LEFT_JUSTIFIED, /*!< I2S fifo:[31:8]24bit_data,[7:0]0x00 */ -} I2S_FIFO_24_Justified_Type; - -/** - * @brief I2S configuration structure type definition - */ -typedef struct -{ - I2S_Endian_Type endianType; /*!< I2S endian configuration */ - I2S_Mode_Type modeType; /*!< I2S mode configuration */ - uint32_t audioFreqHz; /*!< I2S audio pll output frequency in Hz */ - uint32_t sampleFreqHz; /*!< I2S sample data frequency in Hz */ - BL_Fun_Type bclkInvert; /*!< I2S bclk invert configuration */ - I2S_Frame_Size_Type frameSize; /*!< I2S frame size configuration */ - BL_Fun_Type fsInvert; /*!< I2S frame select invert configuration */ - I2S_Fs_Mode_Type fsMode; /*!< I2S frame mode configuration */ - I2S_Fs_Channel_Type fsChannel; /*!< I2S frame channels configuration */ - uint32_t dataOffset; /*!< I2S data output offset configuration */ - I2S_Data_Size_Type dataSize; /*!< I2S data size configuration */ - BL_Fun_Type monoMode; /*!< I2S enable mono mode,when this mode enable,lRMerge must be disabled */ - I2S_Mono_Mode_Channel monoModeChannel; /*!< I2S mono mode channel configuration */ -} I2S_CFG_Type; - -/** - * @brief I2S FIFO configuration structure type definition - */ -typedef struct -{ - BL_Fun_Type lRMerge; /*!< I2S FIFO contains both left and right channel data in one entry */ - BL_Fun_Type frameDataExchange; /*!< I2S exchange left and right channel data in one entry */ - BL_Fun_Type txfifoDmaEnable; /*!< Enable or disable I2S tx fifo dma function. */ - BL_Fun_Type rxfifoDmaEnable; /*!< Enable or disable I2S rx fifo dma function. */ - uint8_t rxFifoLevel; /*!< I2S receive fifo interrupt trigger level. only valid when fifo mode enabled. */ - uint8_t txFifoLevel; /*!< I2S transmit fifo interrupt trigger level. only valid when fifo mode enabled. */ -} I2S_FifoCfg_Type; - -/** - * @brief I2S IO configuration structure type definition - */ -typedef struct -{ - BL_Fun_Type deglitchEn; /*!< Enable or disable deglitch(for all the input pins) */ - uint8_t deglitchCnt; /*!< Deglitch cycle count(unit:cycle of I2S kernel clock) */ - BL_Fun_Type inverseBCLK; /*!< Enable or disable inverse BCLK signal */ - BL_Fun_Type inverseFS; /*!< Enable or disable inverse FS signal */ - BL_Fun_Type inverseRX; /*!< Enable or disable inverse RX signal */ - BL_Fun_Type inverseTX; /*!< Enable or disable inverse TX signal */ -} I2S_IOCfg_Type; - -/*@} end of group I2S_Public_Types */ - -/** @defgroup I2S_Public_Constants - * @{ - */ - -/** @defgroup I2S_MODE_TYPE - * @{ - */ -#define IS_I2S_MODE_TYPE(type) (((type) == I2S_MODE_I2S_LEFT) || \ - ((type) == I2S_MODE_I2S_RIGHT) || \ - ((type) == I2S_MODE_I2S_DSP)) - -/** @defgroup I2S_ID_TYPE - * @{ - */ -#define IS_I2S_ID_TYPE(type) (((type) == I2S0_ID) || \ - ((type) == I2S1_ID) || \ - ((type) == I2S_ID_MAX)) - -/** @defgroup I2S_ROLE_TYPE - * @{ - */ -#define IS_I2S_ROLE_TYPE(type) (((type) == I2S_ROLE_MASTER) || \ - ((type) == I2S_ROLE_SLAVE)) - -/** @defgroup I2S_DATA_SIZE_TYPE - * @{ - */ -#define IS_I2S_DATA_SIZE_TYPE(type) (((type) == I2S_SIZE_DATA_8) || \ - ((type) == I2S_SIZE_DATA_16) || \ - ((type) == I2S_SIZE_DATA_24) || \ - ((type) == I2S_SIZE_DATA_32)) - -/** @defgroup I2S_FRAME_SIZE_TYPE - * @{ - */ -#define IS_I2S_FRAME_SIZE_TYPE(type) (((type) == I2S_SIZE_FRAME_8) || \ - ((type) == I2S_SIZE_FRAME_16) || \ - ((type) == I2S_SIZE_FRAME_24) || \ - ((type) == I2S_SIZE_FRAME_32)) - -/** @defgroup I2S_ENDIAN_TYPE - * @{ - */ -#define IS_I2S_ENDIAN_TYPE(type) (((type) == I2S_DATA_ENDIAN_MSB) || \ - ((type) == I2S_DATA_ENDIAN_LSB)) - -/** @defgroup I2S_FS_MODE_TYPE - * @{ - */ -#define IS_I2S_FS_MODE_TYPE(type) (((type) == I2S_FS_MODE_EVEN) || \ - ((type) == I2S_FS_MODE_1T)) - -/** @defgroup I2S_MONO_MODE_CHANNEL - * @{ - */ -#define IS_I2S_MONO_MODE_CHANNEL(type) (((type) == I2S_RX_MONO_MODE_LEFT_CHANNEL) || \ - ((type) == I2S_RX_MONO_MODE_RIGHT_CHANNEL)) - -/** @defgroup I2S_FS_CHANNEL_TYPE - * @{ - */ -#define IS_I2S_FS_CHANNEL_TYPE(type) (((type) == I2S_FS_CHANNELS_2) || \ - ((type) == I2S_FS_CHANNELS_3) || \ - ((type) == I2S_FS_CHANNELS_4)) - -/** @defgroup I2S_MONOCONTROL_TYPE - * @{ - */ -#define IS_I2S_MONOCONTROL_TYPE(type) (((type) == I2S_MONO_CONTROL_STEREO) || \ - ((type) == I2S_MONO_CONTROL_MONO)) - -/** @defgroup I2S_FIFO_24_JUSTIFIED_TYPE - * @{ - */ -#define IS_I2S_FIFO_24_JUSTIFIED_TYPE(type) (((type) == I2S_FIFO_24_RIGHT_JUSTIFIED) || \ - ((type) == I2S_FIFO_24_LEFT_JUSTIFIED)) - -/*@} end of group I2S_Public_Constants */ - -/** @defgroup I2S_Public_Macros - * @{ - */ -#define I2S_TX_FIFO_SIZE 16 -#define I2S_RX_FIFO_SIZE 16 - -/*@} end of group I2S_Public_Macros */ - -/** @defgroup I2S_Public_Functions - * @{ - */ - -/** - * @brief I2S Functions - */ -void I2S_SetBclkPeriod(I2S_ID_Type i2sId, I2S_CFG_Type *i2sCfg); -void I2S_Init(I2S_ID_Type i2sId, I2S_CFG_Type *i2sCfg); -void I2S_FifoConfig(I2S_ID_Type i2sId, I2S_FifoCfg_Type *fifoCfg); -void I2S_IOConfig(I2S_ID_Type i2sId, I2S_IOCfg_Type *ioCfg); -void I2S_Enable(I2S_ID_Type i2sId, I2S_Role_Type roleType); -void I2S_Disable(I2S_ID_Type i2sId); -uint32_t I2S_Read(I2S_ID_Type i2sId); -void I2S_Write(I2S_ID_Type i2sId, uint32_t data); -void I2S_Mute(I2S_ID_Type i2sId, BL_Fun_Type enabled); -void I2S_SetFifoJustified(I2S_ID_Type i2sId, I2S_FIFO_24_Justified_Type justType); -uint32_t I2S_GetTxFIFO_AvlCnt(I2S_ID_Type i2sId); -uint32_t I2S_GetRxFIFO_AvlCnt(I2S_ID_Type i2sId); -void I2S_Rx_FIFO_Flush(I2S_ID_Type i2sId); -void I2S_Tx_FIFO_Flush(I2S_ID_Type i2sId); - -/*@} end of group I2S_Public_Functions */ - -/*@} end of group I2S */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_I2S_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_ir.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_ir.h deleted file mode 100644 index 43f709d7a8..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_ir.h +++ /dev/null @@ -1,289 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_ir.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_IR_H__ -#define __BL808_IR_H__ - -#include "ir_reg.h" -#include "bl808_common.h" -#include "bl808_hbn.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup IR - * @{ - */ - -/** @defgroup IR_Public_Types - * @{ - */ - -/** - * @brief IR direction type definition - */ -typedef enum { - IR_TX, /*!< IR TX direction */ - IR_RX, /*!< IR RX direction */ - IR_TXRX, /*!< IR TX and RX direction */ -} IR_Direction_Type; - -/** - * @brief IR word type definition - */ -typedef enum { - IR_WORD_0, /*!< IR data word 0 */ - IR_WORD_1, /*!< IR data word 1 */ -} IR_Word_Type; - -/** - * @brief IR frame size(also the valid width for each fifo entry) type definition - */ -typedef enum { - IR_FRAME_SIZE_8, /*!< IR frame size 8 bit */ - IR_FRAME_SIZE_16, /*!< IR frame size 16 bit */ - IR_FRAME_SIZE_24, /*!< IR frame size 24 bit */ - IR_FRAME_SIZE_32, /*!< IR frame size 32 bit */ -} IR_FrameSize_Type; - -/** - * @brief IR RX mode type definition - */ -typedef enum { - IR_RX_NEC, /*!< IR RX NEC mode */ - IR_RX_RC5, /*!< IR RX RC5 mode */ - IR_RX_SWM, /*!< IR RX software pulse-width detection mode */ -} IR_RxMode_Type; - -/** - * @brief IR interrupt type definition - */ -typedef enum { - IR_INT_TX_END, /*!< IR TX transfer end interrupt */ - IR_INT_TX_FIFO_REQ, /*!< IR TX fifo ready interrupt (tx fifo count > tx fifo threshold) */ - IR_INT_TX_FIFO_ERROR, /*!< IR TX fifo error interrupt (overflow/underflow) */ - IR_INT_RX_END, /*!< IR RX transfer end interrupt */ - IR_INT_RX_FIFO_REQ, /*!< IR RX fifo ready interrupt (rx fifo count > rx fifo threshold) */ - IR_INT_RX_FIFO_ERROR, /*!< IR RX fifo error interrupt (overflow/underflow) */ - IR_INT_ALL, /*!< IR all interrupt */ -} IR_INT_Type; - -/** - * @brief IR fifo underflow or overflow type definition - */ -typedef enum { - IR_FIFO_TX_OVERFLOW, /*!< IR tx fifo overflow flag */ - IR_FIFO_TX_UNDERFLOW, /*!< IR tx fifo underflow flag */ - IR_FIFO_RX_OVERFLOW, /*!< IR rx fifo overflow flag */ - IR_FIFO_RX_UNDERFLOW, /*!< IR rx fifo underflow flag */ -} IR_FifoStatus_Type; - -/** - * @brief IR TX configuration structure type definition - */ -typedef struct -{ - uint8_t dataBits; /*!< Bit count of data phase (don't care if tx freerun mode is enabled) */ - BL_Fun_Type tailPulseInverse; /*!< Enable or disable signal of tail pulse inverse (don't care if SWM is enabled) */ - BL_Fun_Type tailPulse; /*!< Enable or disable signal of tail pulse (don't care if SWM is enabled) */ - BL_Fun_Type headPulseInverse; /*!< Enable or disable signal of head pulse inverse (don't care if SWM is enabled) */ - BL_Fun_Type headPulse; /*!< Enable or disable signal of head pulse (don't care if SWM is enabled) */ - BL_Fun_Type logic1PulseInverse; /*!< Enable or disable signal of logic 1 pulse inverse (don't care if SWM is enabled) */ - BL_Fun_Type logic0PulseInverse; /*!< Enable or disable signal of logic 0 pulse inverse (don't care if SWM is enabled) */ - BL_Fun_Type dataPulse; /*!< Enable or disable signal of data pulse (don't care if SWM is enabled) */ - BL_Fun_Type outputModulation; /*!< Enable or disable signal of output modulation */ - BL_Fun_Type outputInverse; /*!< Enable or disable signal of output inverse,0:output stays at low during idle state,1:stay at high */ - BL_Fun_Type freerunEnable; /*!< Enable or disable tx freerun mode (don't care if SWM is enabled) */ - BL_Fun_Type continueEnable; /*!< Disable:idle time between frames = (tailPulseWidth_0+tailPulseWidth_1)*pulseWidthUnit,Enable:no - idle time between frames */ - IR_FrameSize_Type frameSize; /*!< IR frame size(also the valid width for each fifo entry) */ -} IR_TxCfg_Type; - -/** - * @brief IR TX pulse width configuration structure type definition - */ -typedef struct -{ - uint8_t logic0PulseWidth_1; /*!< Pulse width of logic 0 pulse phase 1 (don't care if SWM is enabled) */ - uint8_t logic0PulseWidth_0; /*!< Pulse width of logic 0 pulse phase 0 (don't care if SWM is enabled) */ - uint8_t logic1PulseWidth_1; /*!< Pulse width of logic 1 pulse phase 1 (don't care if SWM is enabled) */ - uint8_t logic1PulseWidth_0; /*!< Pulse width of logic 1 pulse phase 0 (don't care if SWM is enabled) */ - uint8_t headPulseWidth_1; /*!< Pulse width of head pulse phase 1 (don't care if SWM is enabled) */ - uint8_t headPulseWidth_0; /*!< Pulse width of head pulse phase 0 (don't care if SWM is enabled) */ - uint8_t tailPulseWidth_1; /*!< Pulse width of tail pulse phase 1 (don't care if SWM is enabled) */ - uint8_t tailPulseWidth_0; /*!< Pulse width of tail pulse phase 0 (don't care if SWM is enabled) */ - uint8_t moduWidth_1; /*!< Modulation phase 1 width */ - uint8_t moduWidth_0; /*!< Modulation phase 0 width */ - uint16_t pulseWidthUnit; /*!< Pulse width unit */ -} IR_TxPulseWidthCfg_Type; - -/** - * @brief IR RX configuration structure type definition - */ -typedef struct -{ - IR_RxMode_Type rxMode; /*!< Set ir rx mode */ - BL_Fun_Type inputInverse; /*!< Enable or disable signal of input inverse */ - uint16_t endThreshold; /*!< Pulse width threshold to trigger end condition */ - uint16_t dataThreshold; /*!< Pulse width threshold for logic 0/1 detection (don't care if SWM is enabled) */ - BL_Fun_Type rxDeglitch; /*!< Enable or disable signal of rx input de-glitch function */ - uint8_t DeglitchCnt; /*!< De-glitch function cycle count */ -} IR_RxCfg_Type; - -/** - * @brief IR DMA configuration structure type definition - */ -typedef struct -{ - uint8_t txFifoThreshold; /*!< IR tx FIFO threshold */ - uint8_t rxFifoThreshold; /*!< IR rx FIFO threshold */ - BL_Fun_Type txFifoDmaEnable; /*!< Enable or disable tx dma req/ack interface */ -} IR_FifoCfg_Type; - -/*@} end of group IR_Public_Types */ - -/** @defgroup IR_Public_Constants - * @{ - */ - -/** @defgroup IR_DIRECTION_TYPE - * @{ - */ -#define IS_IR_DIRECTION_TYPE(type) (((type) == IR_TX) || \ - ((type) == IR_RX) || \ - ((type) == IR_TXRX)) - -/** @defgroup IR_WORD_TYPE - * @{ - */ -#define IS_IR_WORD_TYPE(type) (((type) == IR_WORD_0) || \ - ((type) == IR_WORD_1)) - -/** @defgroup IR_FRAMESIZE_TYPE - * @{ - */ -#define IS_IR_FRAMESIZE_TYPE(type) (((type) == IR_FRAME_SIZE_8) || \ - ((type) == IR_FRAME_SIZE_16) || \ - ((type) == IR_FRAME_SIZE_24) || \ - ((type) == IR_FRAME_SIZE_32)) - -/** @defgroup IR_RXMODE_TYPE - * @{ - */ -#define IS_IR_RXMODE_TYPE(type) (((type) == IR_RX_NEC) || \ - ((type) == IR_RX_RC5) || \ - ((type) == IR_RX_SWM)) - -/** @defgroup IR_INT_TYPE - * @{ - */ -#define IS_IR_INT_TYPE(type) (((type) == IR_INT_TX_END) || \ - ((type) == IR_INT_TX_FIFO_REQ) || \ - ((type) == IR_INT_TX_FIFO_ERROR) || \ - ((type) == IR_INT_RX_END) || \ - ((type) == IR_INT_RX_FIFO_REQ) || \ - ((type) == IR_INT_RX_FIFO_ERROR) || \ - ((type) == IR_INT_ALL)) - -/** @defgroup IR_FIFOSTATUS_TYPE - * @{ - */ -#define IS_IR_FIFOSTATUS_TYPE(type) (((type) == IR_FIFO_TX_OVERFLOW) || \ - ((type) == IR_FIFO_TX_UNDERFLOW) || \ - ((type) == IR_FIFO_RX_OVERFLOW) || \ - ((type) == IR_FIFO_RX_UNDERFLOW)) - -/*@} end of group IR_Public_Constants */ - -/** @defgroup IR_Public_Macros - * @{ - */ -#define IR_RX_FIFO_SIZE 64 -#define IR_TX_FIFO_SIZE 4 - -/*@} end of group IR_Public_Macros */ - -/** @defgroup IR_Public_Functions - * @{ - */ - -/** - * @brief IR Functions - */ -#ifndef BFLB_USE_HAL_DRIVER -void IRRX_IRQHandler(void); -void IRTX_IRQHandler(void); -#endif -BL_Err_Type IR_TxInit(IR_TxCfg_Type *irTxCfg); -BL_Err_Type IR_TxPulseWidthConfig(IR_TxPulseWidthCfg_Type *irTxPulseWidthCfg); -BL_Err_Type IR_RxInit(IR_RxCfg_Type *irRxCfg); -BL_Err_Type IR_FifoConfig(IR_FifoCfg_Type *fifoCfg); -BL_Err_Type IR_DeInit(void); -BL_Err_Type IR_Enable(IR_Direction_Type direct); -BL_Err_Type IR_Disable(IR_Direction_Type direct); -BL_Err_Type IR_TxSWM(BL_Fun_Type txSWM); -BL_Err_Type IR_RxFifoClear(void); -BL_Err_Type IR_TxFifoClear(void); -BL_Err_Type IR_SendData(uint32_t *data, uint8_t length); -BL_Err_Type IR_SWMSendData(uint16_t *data, uint8_t length); -BL_Err_Type IR_SendCommand(uint32_t *data, uint8_t length); -BL_Err_Type IR_SWMSendCommand(uint16_t *data, uint8_t length); -BL_Err_Type IR_SendNEC(uint8_t address, uint8_t command); -BL_Err_Type IR_IntMask(IR_INT_Type intType, BL_Mask_Type intMask); -BL_Err_Type IR_ClrIntStatus(IR_INT_Type intType); -BL_Err_Type IR_Int_Callback_Install(IR_INT_Type intType, intCallback_Type *cbFun); -BL_Sts_Type IR_GetIntStatus(IR_INT_Type intType); -BL_Sts_Type IR_GetFifoStatus(IR_FifoStatus_Type fifoSts); -uint32_t IR_ReceiveData(IR_Word_Type irWord); -uint8_t IR_SWMReceiveData(uint16_t *data, uint8_t length); -BL_Err_Type IR_ReceiveNEC(uint8_t *address, uint8_t *command); -uint8_t IR_GetRxDataBitCount(void); -uint8_t IR_GetRxFifoCount(void); -uint8_t IR_GetTxFifoCount(void); -IR_RxMode_Type IR_LearnToInit(uint32_t *data, uint8_t *length); -BL_Err_Type IR_LearnToSend(IR_RxMode_Type mode, uint32_t *data, uint8_t length); -uint8_t IR_LearnToReceive(IR_RxMode_Type mode, uint32_t *data); -BL_Err_Type IR_LEDInit(HBN_MCU_XCLK_Type clk, uint8_t div, uint8_t unit, uint8_t code0H, uint8_t code0L, uint8_t code1H, - uint8_t code1L); -BL_Err_Type IR_LEDSend(uint32_t data); - -/*@} end of group IR_Public_Functions */ - -/*@} end of group IR */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_IR_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_iso11898.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_iso11898.h deleted file mode 100644 index d98cd01ed4..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_iso11898.h +++ /dev/null @@ -1,242 +0,0 @@ -#ifndef __BL808_ISO11898_H__ -#define __BL808_ISO11898_H__ - -#include "iso11898_reg.h" -#include "bl808_common.h" - -#define ISO11898_TIMEOUT_MAX (32 * 1000) - -typedef enum { - ISO11898_FRAME_FORMAT_STANDARD = 0, - ISO11898_FRAME_FORMAT_EXTENDED, -} ISO11898_FRAME_FORMAT_Type; - -typedef enum { - ISO11898_FRAME_TYPE_DATA = 0, - ISO11898_FRAME_TYPE_REMOTE, -} ISO11898_FRAME_Type; - -typedef enum { - ISO11898_MODE_TYPE_RESET = 0, - ISO11898_MODE_TYPE_LISTEN_ONLY, - ISO11898_MODE_TYPE_SELF_TSET, - ISO11898_MODE_TYPE_ACCEPTANCE_FILTER, -} ISO11898_MODE_Type; - -typedef enum { - ISO11898_MODE_VALUE_NORMAL = 0, - ISO11898_MODE_VALUE_RESET = 1, - ISO11898_MODE_VALUE_LISTEN_ONLY = 1, - ISO11898_MODE_VALUE_SELF_TSET = 1, - ISO11898_MODE_VALUE_ACCEPTANCE_FILTER_DUAL = 0, - ISO11898_MODE_VALUE_ACCEPTANCE_FILTER_SINGLE = 1, -} ISO11898_MODE_VALUE_Type; - -typedef enum { - ISO11898_INT_RECEIVE = 0, - ISO11898_INT_TRANSMIT, - ISO11898_INT_ERROR_WARNING, - ISO11898_INT_OVERRUN, - ISO11898_INT_RESERVED, - ISO11898_INT_PASSIVE = 5, - ISO11898_INT_ARBITRATION_LOST, - ISO11898_INT_BUS_ERROR, - ISO11898_INT_ALL, -} ISO11898_INT_Type; - -typedef enum { - ISO11898_STATUS_RECEIVE_BUFFER = 0, - ISO11898_STATUS_DATA_OVERRUN, - ISO11898_STATUS_TRANSMIT_BUFFER, - ISO11898_STATUS_TRANSMISSION_COMPLETE, - ISO11898_STATUS_RECEIVE, - ISO11898_STATUS_TRANSMIT, - ISO11898_STATUS_ERROR, - ISO11898_STATUS_BUS, -} ISO11898_STATUS_Type; - -typedef enum { - ISO11898_STATUS_RECEIVE_BUFFER_EMPTY = 0, - ISO11898_STATUS_RECEIVE_BUFFER_NONEMPTY = 1, - ISO11898_STATUS_DATA_OVERRUN_NULL = 0, - ISO11898_STATUS_DATA_OVERRUN_EXIST = 1, - ISO11898_STATUS_TRANSMIT_BUFFER_LOCKED = 0, - ISO11898_STATUS_TRANSMIT_BUFFER_ACCESSIBLE = 1, - ISO11898_STATUS_TRANSMISSION_COMPLETE_NOT = 0, - ISO11898_STATUS_TRANSMISSION_COMPLETE_YES = 1, - ISO11898_STATUS_RECEIVE_IDLE = 0, - ISO11898_STATUS_RECEIVE_ONGOING = 1, - ISO11898_STATUS_TRANSMIT_IDLE = 0, - ISO11898_STATUS_TRANSMIT_ONGOING = 1, - ISO11898_STATUS_ERROR_NULL = 0, - ISO11898_STATUS_ERROR_EXIST = 1, - ISO11898_STATUS_BUS_ON = 0, - ISO11898_STATUS_BUS_OFF = 1, -} ISO11898_STATUS_VALUE_Type; - -typedef enum { - ISO11898_ERROR_TYPE_BIT = 0, - ISO11898_ERROR_TYPE_FORM, - ISO11898_ERROR_TYPE_STUFF, - ISO11898_ERROR_TYPE_OTHERS, -} ISO11898_ERROR_CODE_Type; - -typedef enum { - ISO11898_ERROR_DIRECTION_TX = 0, - ISO11898_ERROR_DIRECTION_RX, -} ISO11898_ERROR_DIRECTION_Type; - -typedef enum { - ISO11898_ERROR_LOCATION_ID28_TO_ID21 = 2, - ISO11898_ERROR_LOCATION_START_OF_FRAME = 3, - ISO11898_ERROR_LOCATION_BIT_SRTR = 4, - ISO11898_ERROR_LOCATION_BIT_IDE = 5, - ISO11898_ERROR_LOCATION_ID20_TO_ID18 = 6, - ISO11898_ERROR_LOCATION_ID17_TO_ID13 = 7, - ISO11898_ERROR_LOCATION_CRC_SEQUENCE = 8, - ISO11898_ERROR_LOCATION_BIT_RESERVED_0 = 9, - ISO11898_ERROR_LOCATION_DATA_FIELD = 10, - ISO11898_ERROR_LOCATION_DATA_LENGTH_CODE = 11, - ISO11898_ERROR_LOCATION_BIT_RTR = 12, - ISO11898_ERROR_LOCATION_BIT_RESERVED_1 = 13, - ISO11898_ERROR_LOCATION_ID4_TO_ID0 = 14, - ISO11898_ERROR_LOCATION_ID12_TO_ID15 = 15, - ISO11898_ERROR_LOCATION_ACTIVE_ERROR_FLAG = 17, - ISO11898_ERROR_LOCATION_INTERMISSION = 18, - ISO11898_ERROR_LOCATION_BIT_TOLERATE_DOMINANT = 19, - ISO11898_ERROR_LOCATION_PASSIVE_ERROR_FLAG = 22, - ISO11898_ERROR_LOCATION_ERROR_DELIMITER = 23, - ISO11898_ERROR_LOCATION_CRC_DELIMITER = 24, - ISO11898_ERROR_LOCATION_ACK_SLOT = 25, - ISO11898_ERROR_LOCATION_END_OF_FRAME = 26, - ISO11898_ERROR_LOCATION_ACK_DELIMITER = 27, - ISO11898_ERROR_LOCATION_OVERLOAD_FLAG = 28, -} ISO11898_ERROR_LOCATION_Type; - -typedef enum { - ISO11898_FILTER_REGISTER_ACR0 = 0, - ISO11898_FILTER_REGISTER_ACR1, - ISO11898_FILTER_REGISTER_ACR2, - ISO11898_FILTER_REGISTER_ACR3, - ISO11898_FILTER_REGISTER_AMR0, - ISO11898_FILTER_REGISTER_AMR1, - ISO11898_FILTER_REGISTER_AMR2, - ISO11898_FILTER_REGISTER_AMR3, -} ISO11898_FILTER_REGISTER_Type; - -typedef struct { - ISO11898_ERROR_CODE_Type code; - ISO11898_ERROR_DIRECTION_Type dir; - ISO11898_ERROR_LOCATION_Type location; -} ISO11898_ERROR_Type; - -typedef struct { - ISO11898_FRAME_FORMAT_Type formatType; - ISO11898_MODE_VALUE_Type filterMode; - ISO11898_FRAME_Type matchRtr1; - ISO11898_FRAME_Type matchRtr2; - uint8_t matchData1; - uint8_t matchData2; - uint32_t matchId1; - uint32_t matchId2; - BL_Mask_Type maskRtr1; - BL_Mask_Type maskRtr2; - uint8_t maskData1; - uint8_t maskData2; - uint32_t maskId1; - uint32_t maskId2; -} ISO11898_FILTER_CFG_Type; - -typedef struct { - ISO11898_FRAME_Type frameType; - ISO11898_FRAME_FORMAT_Type frameFormat; - uint8_t dataLen; - uint8_t *dataAddr; - uint32_t id; - uint32_t timeout; -} ISO11898_CFG_Type; - -#define IS_ISO11898_FRAME_FORMAT_TYPE(type) (((type) == ISO11898_FRAME_FORMAT_STANDARD) || \ - ((type) == ISO11898_FRAME_FORMAT_EXTENDED)) - -#define IS_ISO11898_FRAME_TYPE(type) (((type) == ISO11898_FRAME_TYPE_DATA) || \ - ((type) == ISO11898_FRAME_TYPE_REMOTE)) - -#define IS_ISO11898_MODE_TYPE(type) (((type) == ISO11898_MODE_TYPE_RESET) || \ - ((type) == ISO11898_MODE_TYPE_LISTEN_ONLY) || \ - ((type) == ISO11898_MODE_TYPE_SELF_TSET) || \ - ((type) == ISO11898_MODE_TYPE_ACCEPTANCE_FILTER) || \ - -#define IS_ISO11898_MODE_VALUE_TYPE(type) (((type) == ISO11898_MODE_VALUE_NORMAL) || \ - ((type) == ISO11898_MODE_VALUE_RESET) || \ - ((type) == ISO11898_MODE_VALUE_LISTEN_ONLY) || \ - ((type) == ISO11898_MODE_VALUE_SELF_TSET) || \ - ((type) == ISO11898_MODE_VALUE_ACCEPTANCE_FILTER_DUAL) || \ - ((type) == ISO11898_MODE_VALUE_ACCEPTANCE_FILTER_SINGLE) || \ - -#define IS_ISO11898_INT_TYPE(type) (((type) == ISO11898_INT_RECEIVE) || \ - ((type) == ISO11898_INT_TRANSMIT) || \ - ((type) == ISO11898_INT_ERROR_WARNING) || \ - ((type) == ISO11898_INT_OVERRUN) || \ - ((type) == ISO11898_INT_PASSIVE) || \ - ((type) == ISO11898_INT_ARBITRATION_LOST) || \ - ((type) == ISO11898_INT_BUSERROR) || \ - ((type) == ISO11898_INT_ALL)) - -#define IS_ISO11898_STATUS_TYPE(type) (((type) == ISO11898_STATUS_RECEIVE_BUFFER) || \ - ((type) == ISO11898_STATUS_DATA_OVERRUN) || \ - ((type) == ISO11898_STATUS_TRANSMIT_BUFFER) || \ - ((type) == ISO11898_STATUS_TRANSMISSION_COMPLETE) || \ - ((type) == ISO11898_STATUS_RECEIVE) || \ - ((type) == ISO11898_STATUS_TRANSMIT) || \ - ((type) == ISO11898_STATUS_ERROR) || \ - ((type) == ISO11898_STATUS_BUS)) - -#define IS_ISO11898_STATUS_VALUE_TYPE(type) (((type) == ISO11898_STATUS_VALUE_RECEIVE_BUFFER_EMPTY || \ - ((type) == ISO11898_STATUS_VALUE_RECEIVE_BUFFER_NONEMPTY || \ - ((type) == ISO11898_STATUS_VALUE_DATA_OVERRUN_NULL || \ - ((type) == ISO11898_STATUS_VALUE_DATA_OVERRUN_EXIST || \ - ((type) == ISO11898_STATUS_VALUE_TRANSMIT_BUFFER_LOCKED || \ - ((type) == ISO11898_STATUS_VALUE_TRANSMIT_BUFFER_ACCESSIBLE || \ - ((type) == ISO11898_STATUS_VALUE_TRANSMISSION_COMPLETE_NOT || \ - ((type) == ISO11898_STATUS_VALUE_TRANSMISSION_COMPLETE_YES || \ - ((type) == ISO11898_STATUS_VALUE_RECEIVE_IDLE || \ - ((type) == ISO11898_STATUS_VALUE_RECEIVE_ONGOING || \ - ((type) == ISO11898_STATUS_VALUE_TRANSMIT_IDLE || \ - ((type) == ISO11898_STATUS_VALUE_TRANSMIT_ONGOING || \ - ((type) == ISO11898_STATUS_VALUE_ERROR_NULL || \ - ((type) == ISO11898_STATUS_VALUE_ERROR_EXIST || \ - ((type) == ISO11898_STATUS_VALUE_BUS_ON || \ - ((type) == ISO11898_STATUS_VALUE_BUS_OFF)) - -void ISO11898_Init(void); -void ISO11898_Mode_Set(ISO11898_MODE_Type type, ISO11898_MODE_VALUE_Type value); -ISO11898_MODE_VALUE_Type ISO11898_Mode_Get(ISO11898_MODE_Type type); -void ISO11898_Int_Enable(ISO11898_INT_Type intType, BL_Fun_Type enable); -void ISO11898_Cmd_Request_Transmit(void); -void ISO11898_Cmd_Abort_Transmit(void); -void ISO11898_Cmd_Release_Recv_Buff(void); -void ISO11898_Cmd_Clear_Data_Overrun(void); -void ISO11898_Cmd_Request_Self_Reception(void); -ISO11898_STATUS_VALUE_Type ISO11898_Status_Get(ISO11898_STATUS_Type type); -uint8_t ISO11898_Arbitration_Lost_Position_Get(void); -void ISO11898_Error_Get(ISO11898_ERROR_Type *const code); -BL_Err_Type ISO11898_Error_Warning_Limit_Set(uint8_t limit); -uint8_t ISO11898_Error_Warning_Limit_Get(void); -uint8_t ISO11898_Error_Rx_Counter_Get(void); -uint8_t ISO11898_Error_Tx_Counter_Get(void); -BL_Err_Type ISO11898_Transmit(const ISO11898_CFG_Type *cfg); -BL_Err_Type ISO11898_Receive(ISO11898_CFG_Type *cfg); -uint8_t ISO11898_Receive_Buff_Frame_Count_Get(void); -BL_Err_Type ISO11898_Clock_Div_Set(uint8_t div); -uint8_t ISO11898_Clock_Div_Get(void); -BL_Err_Type ISO11898_Synchronization_Jump_Width_Set(uint8_t width); -uint8_t ISO11898_Synchronization_Jump_Width_Get(void); -BL_Err_Type ISO11898_Sample_Parameter_Set(uint8_t num, uint8_t head, uint8_t tail); -void ISO11898_Sample_Parameter_Get(uint8_t *num, uint8_t *head, uint8_t *tail); -void ISO11898_Filter_Set(const ISO11898_FILTER_CFG_Type *cfg); -void ISO11898_Filter_Register_Set(ISO11898_FILTER_REGISTER_Type reg, uint8_t value); -void ISO11898_Filter_Registers_Set(uint8_t *valueArr); - -BL_Err_Type ISO11898_Int_Callback_Install(ISO11898_INT_Type intType, intCallback_Type *cbFun); -#endif /* __BL606p_ISO11898_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_mfg_efuse.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_mfg_efuse.h deleted file mode 100644 index cbd7e585e8..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_mfg_efuse.h +++ /dev/null @@ -1,25 +0,0 @@ -#ifndef __BL602_MFG_EFUSE_H__ -#define __BL602_MFG_EFUSE_H__ - -#include "stdint.h" - -uint8_t mfg_efuse_get_rf_cal_slots(void); -void mfg_efuse_set_rf_cal_slots(uint8_t slots); -uint8_t mfg_efuse_is_xtal_capcode_slot_empty(uint8_t reload); -int8_t mfg_efuse_write_xtal_capcode_pre(uint8_t capcode,uint8_t program); -void mfg_efuse_write_xtal_capcode(void); -int8_t mfg_efuse_read_xtal_capcode(uint8_t *capcode,uint8_t reload); -uint8_t mfg_efuse_is_poweroffset_slot_empty(uint8_t reload); -int8_t mfg_efuse_write_poweroffset_pre(int8_t pwrOffset[14],uint8_t program); -void mfg_efuse_write_poweroffset(void); -int8_t mfg_efuse_read_poweroffset(int8_t pwrOffset[14],uint8_t reload); -uint8_t mfg_efuse_is_macaddr_slot_empty(uint8_t reload); -int8_t mfg_efuse_write_macaddr_pre(uint8_t mac[6],uint8_t program); -void mfg_efuse_write_macaddr(void); -int8_t mfg_efuse_read_macaddr(uint8_t mac[6],uint8_t reload); -int8_t mfg_efuse_read(uint32_t addr,uint32_t *data,uint32_t countInword,uint8_t reload); -int8_t mfg_efuse_program(void); -int8_t mfg_efuse_write_pre(uint32_t addr,uint32_t *data,uint32_t countInword); -int8_t mfg_efuse_read_poweroffset_ate(int8_t *pwrOffset); - -#endif/*__BL602_MFG_EFUSE_H__*/ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_mfg_flash.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_mfg_flash.h deleted file mode 100644 index 2089cc683c..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_mfg_flash.h +++ /dev/null @@ -1,30 +0,0 @@ -#ifndef __BL602_MFG_FLASH_H__ -#define __BL602_MFG_FLASH_H__ - -#include "stdint.h" -#include "bl808_xip_sflash.h" - -typedef struct rf_para_flash_tag{ - uint32_t magic; //"RFPA" - uint8_t capcode_valid; //0x5A - uint8_t capcode; - uint8_t poweroffset_valid; //0x5A - int8_t poweroffset[3]; - uint8_t mac_valid; //0x5A - uint8_t mac[6]; - uint8_t rsvd[3]; - uint32_t crc32; -}rf_para_flash_t; - -int8_t mfg_flash_init( SPI_Flash_Cfg_Type *flashCfg); -int8_t mfg_flash_write_xtal_capcode_pre(uint8_t capcode,uint8_t program); -void mfg_flash_write_xtal_capcode(void); -int8_t mfg_flash_read_xtal_capcode(uint8_t *capcode,uint8_t reload); -int8_t mfg_flash_write_poweroffset_pre(int8_t pwrOffset[14],uint8_t program); -void mfg_flash_write_poweroffset(void); -int8_t mfg_flash_read_poweroffset(int8_t pwrOffset[14],uint8_t reload); -int8_t mfg_flash_write_macaddr_pre(uint8_t mac[6],uint8_t program); -void mfg_flash_write_macaddr(void); -int8_t mfg_flash_read_macaddr(uint8_t mac[6],uint8_t reload); - -#endif/*__BL602_MFG_FLASH_H__*/ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_mfg_media.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_mfg_media.h deleted file mode 100644 index 47b103607a..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_mfg_media.h +++ /dev/null @@ -1,35 +0,0 @@ -#ifndef __BL602_MFG_MEDIA_H__ -#define __BL602_MFG_MEDIA_H__ - -#include "stdint.h" -#include "bl808_mfg_efuse.h" -#include "bl808_mfg_flash.h" - -int8_t mfg_media_init_need_lock( SPI_Flash_Cfg_Type *flashCfg); -int8_t mfg_media_init_with_lock( SPI_Flash_Cfg_Type *flashCfg); -uint8_t mfg_media_is_xtal_capcode_slot_empty(uint8_t reload); -int8_t mfg_media_write_xtal_capcode_pre_need_lock(uint8_t capcode,uint8_t program); -void mfg_media_write_xtal_capcode_need_lock(void); -int8_t mfg_media_read_xtal_capcode_need_lock(uint8_t *capcode,uint8_t reload); -int8_t mfg_media_write_xtal_capcode_pre_with_lock(uint8_t capcode,uint8_t program); -void mfg_media_write_xtal_capcode_with_lock(void); -int8_t mfg_media_read_xtal_capcode_with_lock(uint8_t *capcode,uint8_t reload); -int8_t mfg_media_read_xtal_capcode(uint8_t *capcode,uint8_t reload); -uint8_t mfg_media_is_poweroffset_slot_empty(uint8_t reload); -int8_t mfg_media_write_poweroffset_pre_need_lock(int8_t pwrOffset[14],uint8_t program); -void mfg_media_write_poweroffset_need_lock(void); -int8_t mfg_media_read_poweroffset_need_lock(int8_t pwrOffset[14],uint8_t reload); -int8_t mfg_media_read_poweroffset(int8_t pwrOffset[14],uint8_t reload); -int8_t mfg_media_write_poweroffset_pre_with_lock(int8_t pwrOffset[14],uint8_t program); -void mfg_media_write_poweroffset_with_lock(void); -int8_t mfg_media_read_poweroffset_with_lock(int8_t pwrOffset[14],uint8_t reload); -uint8_t mfg_media_is_macaddr_slot_empty(uint8_t reload); -int8_t mfg_media_write_macaddr_pre_need_lock(uint8_t mac[6],uint8_t program); -void mfg_media_write_macaddr_need_lock(void); -int8_t mfg_media_read_macaddr_need_lock(uint8_t mac[6],uint8_t reload); -int8_t mfg_media_write_macaddr_pre_with_lock(uint8_t mac[6],uint8_t program); -void mfg_media_write_macaddr_with_lock(void); -int8_t mfg_media_read_macaddr_with_lock(uint8_t mac[6],uint8_t reload); -int8_t mfg_media_read_macaddr(uint8_t mac[6],uint8_t reload); - -#endif/*__BL602_MFG_MEDIA_H__*/ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_mjdec.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_mjdec.h deleted file mode 100644 index 2456c85ae7..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_mjdec.h +++ /dev/null @@ -1,175 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_mjdec.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_MJDEC_H__ -#define __BL808_MJDEC_H__ - -#include "mjdec_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup MJDEC - * @{ - */ - -/** @defgroup MJDEC_Public_Types - * @{ - */ - -/** - * @brief MJDEC YUV format definition - */ -typedef enum { - MJDEC_YUV420, /*!< MJDEC YUV420 planar mode */ - MJDEC_YUV400, /*!< MJDEC YUV400 grey scale mode */ - MJDEC_YUV422_PLANAR, /*!< MJDEC YUV422 planar mode */ -} MJDEC_YUV_Mode_Type; - -/** - * @brief MJDEC burst type definition - */ -typedef enum { - MJDEC_BURST_SINGLE, /*!< MJDEC burst single */ - MJDEC_BURST_INCR4, /*!< MJDEC burst incr4 */ - MJDEC_BURST_INCR8, /*!< MJDEC burst incr8 */ - MJDEC_BURST_INCR16, /*!< MJDEC burst incr16 */ -} MJDEC_Burst_Type; - -/** - * @brief MJDEC interrupt type definition - */ -typedef enum { - MJDEC_INT_NORMAL, /*!< MJDEC normal write interrupt */ - MJDEC_INT_BACK_IDLE, /*!< MJDEC back idle interrupt */ - MJDEC_INT_ALL, /*!< MJDEC all interrupt type */ -} MJDEC_INT_Type; - -/** - * @brief MJDEC configuration strcut definition - */ -typedef struct { - MJDEC_Burst_Type burstRead; /*!< MJDEC burst read type */ - MJDEC_Burst_Type burstWrite; /*!< MJDEC burst write type */ - MJDEC_YUV_Mode_Type yuv; /*!< MJDEC control YUV mode */ - uint8_t intCnt; /*!< Set frame threshold to issue interrupt */ - uint32_t bufferFrameYY; /*!< YUV frame buffer address of YY frame */ - uint32_t bufferFrameUV; /*!< YUV frame buffer address of UV frame */ - uint16_t resolutionX; /*!< YUV frame RESOLUTION X */ - uint16_t resolutionY; /*!< YUV frame RESOLUTION Y */ - uint16_t headByte; /*!< Skip JPEG stream header byte */ - BL_Fun_Type headSkip; /*!< Skip JPEG stream header */ - BL_Fun_Type evenOrderEnable; /*!< Enable:U is even byte of UV frame and V is odd byte of UV frame */ - BL_Fun_Type dmyBlock; /*!< MJPEG last half block with dummy data 8'h80 */ - BL_Fun_Type dmyVertical; /*!< MJPEG last half vertical block drop */ - BL_Fun_Type dmyHorizational; /*!< MJPEG last half horizational block drop */ - BL_Fun_Type swapMode; /*!< MJDEC YUV Memory swap mode */ - uint8_t picQuality; /*!< Quality must be in 1-75 or 100 */ -} MJDEC_CFG_Type; - -/** - * @brief MJDEC frame information strcut definition - */ -typedef struct -{ - uint8_t validFrames; /*!< Valid frames */ - uint32_t curFrameAddr; /*!< Current frame address */ -} MJDEC_Frame_Info; - -/*@} end of group MJDEC_Public_Types */ - -/** @defgroup MJDEC_Public_Constants - * @{ - */ - -/** @defgroup MJDEC_YUV_MODE_TYPE - * @{ - */ -#define IS_MJDEC_YUV_MODE_TYPE(type) (((type) == MJDEC_YUV420) || \ - ((type) == MJDEC_YUV400) || \ - ((type) == MJDEC_YUV422_PLANAR)) - -/** @defgroup MJDEC_BURST_TYPE - * @{ - */ -#define IS_MJDEC_BURST_TYPE(type) (((type) == MJDEC_BURST_SINGLE) || \ - ((type) == MJDEC_BURST_INCR4) || \ - ((type) == MJDEC_BURST_INCR8) || \ - ((type) == MJDEC_BURST_INCR16)) - -/** @defgroup MJDEC_INT_TYPE - * @{ - */ -#define IS_MJDEC_INT_TYPE(type) (((type) == MJDEC_INT_NORMAL) || \ - ((type) == MJDEC_INT_BACK_IDLE) || \ - ((type) == MJDEC_INT_ALL)) - -/*@} end of group MJDEC_Public_Constants */ - -/** @defgroup MJDEC_Public_Macros - * @{ - */ -#define MJDEC_BASE MJPEG_DEC_BASE -/*@} end of group MJDEC_Public_Macros */ - -/** @defgroup MJDEC_Public_Functions - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -void MJDEC_IRQHandler(void); -#endif -void MJDEC_Init(MJDEC_CFG_Type *cfg); -void MJDEC_Deinit(void); -void MJDEC_Enable(void); -void MJDEC_Disable(void); -void MJDEC_Get_Frame_Info(MJDEC_Frame_Info *info); -uint8_t MJDEC_Get_Frame_Count(void); -BL_Err_Type MJDEC_Push_Frame(uint32_t bufferMjpeg); -void MJDEC_Pop_Frame(void); -void MJDEC_Set_Frame_Threshold(uint8_t count); -void MJDEC_Set_Q_Value(uint8_t q); -void MJDEC_IntMask(MJDEC_INT_Type intType, BL_Mask_Type intMask); -void MJDEC_IntClr(MJDEC_INT_Type intType); -void MJDEC_Int_Callback_Install(MJDEC_INT_Type intType, intCallback_Type *cbFun); - -/*@} end of group MJDEC_Public_Functions */ - -/*@} end of group MJDEC */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_MJDEC_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_mjpeg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_mjpeg.h deleted file mode 100644 index fa5ffc74f9..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_mjpeg.h +++ /dev/null @@ -1,259 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_mjpeg.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_MJPEG_H__ -#define __BL808_MJPEG_H__ - -#include "mjpeg_reg.h" -#include "bl808_common.h" -#include "mjpeg_q_reg.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup MJPEG - * @{ - */ - -/** @defgroup MJPEG_Public_Types - * @{ - */ - -/** - * @brief MJPEG YUV format definition - */ -typedef enum { - MJPEG_YUV420, /*!< MJPEG YUV420 planar mode */ - MJPEG_YUV400, /*!< MJPEG YUV400 grey scale mode */ - MJPEG_YUV422_PLANAR, /*!< MJPEG YUV422 planar mode */ - MJPEG_YUV422_INTERLEAVE, /*!< MJPEG YUV422 interleave mode */ -} MJPEG_YUV_Mode_Type; - -/** - * @brief MJPEG burst type definition - */ -typedef enum { - MJPEG_BURST_SINGLE, /*!< MJPEG burst single */ - MJPEG_BURST_INCR4, /*!< MJPEG burst incr4 */ - MJPEG_BURST_INCR8, /*!< MJPEG burst incr8 */ - MJPEG_BURST_INCR16, /*!< MJPEG burst incr16 */ -} MJPEG_Burst_Type; - -/** - * @brief MJPEG swap mode block definition - */ -typedef enum { - MJPEG_BLOCK_0, /*!< Memory block 0 */ - MJPEG_BLOCK_1, /*!< Memory block 1 */ -} MJPEG_Swap_Block_Type; - -/** - * @brief MJPEG SW mode type definition - */ -typedef enum { - MJPEG_SW_FRAME_MODE, /*!< SW frame mode */ - MJPEG_SW_KICK_MODE, /*!< SW kick mode */ -} MJPEG_SW_Mode_Type; - -/** - * @brief MJPEG frame id type definition - */ -typedef enum { - MJPEG_FRAME_0, /*!< MJPEG frame 0 */ - MJPEG_FRAME_1, /*!< MJPEG frame 1 */ - MJPEG_FRAME_2, /*!< MJPEG frame 2 */ - MJPEG_FRAME_3, /*!< MJPEG frame 3 */ -} MJPEG_Frame_ID_Type; - -/** - * @brief MJPEG interrupt type definition - */ -typedef enum { - MJPEG_INT_NORMAL, /*!< MJPEG normal write interrupt */ - MJPEG_INT_CAM_OVERWRITE, /*!< MJPEG camera overwrite interrupt */ - MJPEG_INT_MEM_OVERWRITE, /*!< MJPEG memory overwrite interrupt */ - MJPEG_INT_FRAME_OVERWRITE, /*!< MJPEG frame overwrite interrupt */ - MJPEG_INT_BACK_IDLE, /*!< MJPEG back idle interrupt */ - MJPEG_INT_SWAP, /*!< MJPEG swap memory block interrupt */ - MJPEG_INT_ALL, /*!< MJPEG all interrupt type */ -} MJPEG_INT_Type; - -/** - * @brief MJPEG configuration strcut definition - */ -typedef struct -{ - MJPEG_Burst_Type burst; /*!< MJPEG burst type */ - MJPEG_YUV_Mode_Type yuv; /*!< MJPEG control YUV mode */ - uint8_t frameCount; /*!< 0:MJPEG will not stop, !0:MJPEG will stop when count arrived */ - uint16_t waitCount; /*!< Cycle count in wait state, default value:0x400 */ - uint32_t bufferMjpeg; /*!< MJPEG buffer addr */ - uint32_t sizeMjpeg; /*!< MJPEG buffer size */ - uint32_t bufferCamYY; /*!< CAM buffer address of Y frame */ - uint32_t sizeCamYY; /*!< CAM buffer size of Y frame */ - uint32_t bufferCamUV; /*!< CAM buffer address of UV frame */ - uint32_t sizeCamUV; /*!< CAM buffer size of UV frame */ - uint16_t resolutionX; /*!< CAM RESOLUTION X */ - uint16_t resolutionY; /*!< CAM RESOLUTION Y */ - BL_Fun_Type bitOrderEnable; /*!< MJPEG bitstream order adjustment */ - BL_Fun_Type evenOrderEnable; /*!< Enable:U is even byte of UV frame and V is odd byte of UV frame */ - BL_Fun_Type swapModeEnable; /*!< Enable or disable write swap mode */ - BL_Fun_Type readStartEnable; /*!< Enable or disable frame read start at start address */ - BL_Fun_Type reflectDmy; /*!< UV dummy with relect */ - BL_Fun_Type verticalDmy; /*!< MJPEG last half vertical block with dummy data 0x80 */ - BL_Fun_Type horizationalDmy; /*!< MJPEG last half horizational block with dummy data 0x80 */ -} MJPEG_CFG_Type; - -/** - * @brief MJPEG frame information strcut definition - */ -typedef struct -{ - uint8_t validFrames; /*!< Valid frames */ - uint16_t curFrameId; /*!< Current frame id */ - uint32_t curFrameAddr; /*!< Current frame address */ - uint32_t curFrameBytes; /*!< Current frame bytes */ - uint32_t status; /*!< MJPEG module status */ -} MJPEG_Frame_Info; - -/*@} end of group MJPEG_Public_Types */ - -/** @defgroup MJPEG_Public_Constants - * @{ - */ - -/** @defgroup MJPEG_YUV_MODE_TYPE - * @{ - */ -#define IS_MJPEG_YUV_MODE_TYPE(type) (((type) == MJPEG_YUV420) || \ - ((type) == MJPEG_YUV400) || \ - ((type) == MJPEG_YUV422_PLANAR) || \ - ((type) == MJPEG_YUV422_INTERLEAVE)) - -/** @defgroup MJPEG_BURST_TYPE - * @{ - */ -#define IS_MJPEG_BURST_TYPE(type) (((type) == MJPEG_BURST_SINGLE) || \ - ((type) == MJPEG_BURST_INCR4) || \ - ((type) == MJPEG_BURST_INCR8) || \ - ((type) == MJPEG_BURST_INCR16)) - -/** @defgroup MJPEG_SWAP_BLOCK_TYPE - * @{ - */ -#define IS_MJPEG_SWAP_BLOCK_TYPE(type) (((type) == MJPEG_BLOCK_0) || \ - ((type) == MJPEG_BLOCK_1)) - -/** @defgroup MJPEG_SW_MODE_TYPE - * @{ - */ -#define IS_MJPEG_SW_MODE_TYPE(type) (((type) == MJPEG_SW_FRAME_MODE) || \ - ((type) == MJPEG_SW_KICK_MODE)) - -/** @defgroup MJPEG_FRAME_ID_TYPE - * @{ - */ -#define IS_MJPEG_FRAME_ID_TYPE(type) (((type) == MJPEG_FRAME_0) || \ - ((type) == MJPEG_FRAME_1) || \ - ((type) == MJPEG_FRAME_2) || \ - ((type) == MJPEG_FRAME_3)) - -/** @defgroup MJPEG_INT_TYPE - * @{ - */ -#define IS_MJPEG_INT_TYPE(type) (((type) == MJPEG_INT_NORMAL) || \ - ((type) == MJPEG_INT_CAM_OVERWRITE) || \ - ((type) == MJPEG_INT_MEM_OVERWRITE) || \ - ((type) == MJPEG_INT_FRAME_OVERWRITE) || \ - ((type) == MJPEG_INT_BACK_IDLE) || \ - ((type) == MJPEG_INT_SWAP) || \ - ((type) == MJPEG_INT_ALL)) - -/*@} end of group MJPEG_Public_Constants */ - -/** @defgroup MJPEG_Public_Macros - * @{ - */ - -/*@} end of group MJPEG_Public_Macros */ - -/** @defgroup MJPEG_Public_Functions - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -void MJPEG_IRQHandler(void); -#endif -void MJPEG_Init(MJPEG_CFG_Type *cfg); -void MJPEG_Set_YUYV_Order_Interleave(uint8_t y0, uint8_t u0, uint8_t y1, uint8_t v0); -void MJPEG_Set_Planar_Y_UV_Input(uint8_t yCamId, uint8_t uvCamId); -void MJPEG_Deinit(void); -void MJPEG_Enable(void); -void MJPEG_Disable(void); -void MJPEG_SW_Enable(MJPEG_SW_Mode_Type swType, uint8_t count); -void MJPEG_SW_Run(void); -void MJPEG_SW_Set_Kick_Block(uint16_t count); -void MJPEG_SW_Kick(void); -void MJPEG_Get_Frame_Info(MJPEG_Frame_Info *info); -uint8_t MJPEG_Get_Frame_Count(void); -void MJPEG_Pop_Frame(void); -void MJPEG_Current_Block_Clear(void); -MJPEG_Swap_Block_Type MJPEG_Get_Current_Block(void); -BL_Sts_Type MJPEG_Block_Is_Full(MJPEG_Swap_Block_Type block); -BL_Sts_Type MJPEG_Current_Block_Is_Start(void); -BL_Sts_Type MJPEG_Current_Block_Is_End(void); -uint32_t MJPEG_Get_Remain_Bit(void); -void MJPEG_Set_Frame_Threshold(uint8_t count); -void MJPEG_Frame_Head_Set_Size(uint16_t size); -void MJPEG_Frame_Tail_Auto_Fill(BL_Fun_Type enable); -void MJPEG_Set_Quantize_Parameter_Y(uint8_t index, uint16_t qParameter); -void MJPEG_Set_Quantize_Parameter_UV(uint8_t index, uint16_t qParameter); -void MJPEG_Set_Quantize_Table_Y(uint16_t *qTable); -void MJPEG_Set_Quantize_Table_UV(uint16_t *qTable); -void MJPEG_Calculate_Quantize_Table(uint16_t *inputTable, uint16_t *outputTable, uint8_t quality); -void MJPEG_Quantize_SRAM_Switch(void); -uint8_t MJPEG_Get_Current_Quantize_SRAM(void); -uint8_t MJPEG_Get_Frame_Quantize_SRAM(MJPEG_Frame_ID_Type frameId); -void MJPEG_IntMask(MJPEG_INT_Type intType, BL_Mask_Type intMask); -void MJPEG_IntClr(MJPEG_INT_Type intType); -void MJPEG_Int_Callback_Install(MJPEG_INT_Type intType, intCallback_Type *cbFun); - -/*@} end of group MJPEG_Public_Functions */ - -/*@} end of group MJPEG */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_MJPEG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_osd_blend.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_osd_blend.h deleted file mode 100644 index a45dd88fbb..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_osd_blend.h +++ /dev/null @@ -1,212 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_osd_blend.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2021 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef __BL808_OSD_BLEND_H__ -#define __BL808_OSD_BLEND_H__ - -#include -#include "bl808_common.h" -#include "osd_blend_reg.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup OSD_BLEND - * @{ - */ - -/** @defgroup OSD_BLEND_Public_Macros - * @{ - */ - -/** @defgroup OSD_BLEND layer definitions - * @{ - */ - -#define OSD_A_BLEND_LAYER0 ((osd_blend_reg_t *)(OSD_A_BASE + OSD_BLEND0_OFFSET)) -#define OSD_A_BLEND_LAYER1 ((osd_blend_reg_t *)(OSD_A_BASE + OSD_BLEND1_OFFSET)) -#define OSD_A_BLEND_LAYER2 ((osd_blend_reg_t *)(OSD_A_BASE + OSD_BLEND2_OFFSET)) -#define OSD_A_BLEND_LAYER3 ((osd_blend_reg_t *)(OSD_A_BASE + OSD_BLEND3_OFFSET)) - -#define OSD_B_BLEND_LAYER0 ((osd_blend_reg_t *)(OSD_B_BASE + OSD_BLEND0_OFFSET)) -#define OSD_B_BLEND_LAYER1 ((osd_blend_reg_t *)(OSD_B_BASE + OSD_BLEND1_OFFSET)) - -#define OSD_DP_BLEND_LAYER0 ((osd_blend_reg_t *)(OSD_DP_BASE + OSD_BLEND0_OFFSET)) -#define OSD_DP_BLEND_LAYER1 ((osd_blend_reg_t *)(OSD_DP_BASE + OSD_BLEND1_OFFSET)) -#define OSD_DP_BLEND_LAYER2 ((osd_blend_reg_t *)(OSD_DP_BASE + OSD_BLEND2_OFFSET)) -#define OSD_DP_BLEND_LAYER3 ((osd_blend_reg_t *)(OSD_DP_BASE + OSD_BLEND3_OFFSET)) - -/*@} end of group OSD_BLEND_Public_Macros */ - -/** @defgroup OSD_BLEND_Public_Constants - * @{ - */ - -/*@} end of group OSD_BLEND_Public_Constants */ - -/** @defgroup OSD_BLEND_Public_Types - * @{ - */ - -/** - * @brief OSD_BLEND state control definition - */ -typedef enum { - OSD_BLEND_ST_ENABLE = 0, - OSD_BLEND_ST_DISABLE, - OSD_BLEND_ST_MAX = 0x7FFFFFFF -} OSD_BLEND_ST_e; - -/* order --- from LSB to MSB. - * eg1: order_a = 3, order_rv=2, order_gy=1, order_bu=0 - * Byte Address: 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 - * ARGB8888: A1 R1 G1 B1 A0 R0 G0 B0 - * - * eg2: order_a = 3, order_rv=0, order_gy=2, order_bu=1 - * Byte Address: 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 - * AYUV8888: A1 Y1 U1 V1 A0 Y0 U0 V0 - */ - -typedef enum { - OSD_BLEND_COLOR_ORDER0 = 0, - OSD_BLEND_COLOR_ORDER1, - OSD_BLEND_COLOR_ORDER2, - OSD_BLEND_COLOR_ORDER3, - OSD_BLEND_COLOR_ORDER_MAX = 0x7F -} OSD_BLEND_COLOR_ORDER_e; - -typedef enum { - OSD_BLEND_COLOR_FMT_ARGB8888 = 0, - OSD_BLEND_COLOR_FMT_AYUV8888, - OSD_BLEND_COLOR_FMT_ARGB4444, - OSD_BLEND_COLOR_FMT_AYUV4444, - OSD_BLEND_COLOR_FMT_ARGB1555, - OSD_BLEND_COLOR_FMT_AYUV1555, - OSD_BLEND_COLOR_FMT_RGB565, - OSD_BLEND_COLOR_FMT_YUV655, - OSD_BLEND_COLOR_FMT_A8RGB, - OSD_BLEND_COLOR_FMT_A8YUV, - OSD_BLEND_COLOR_FMT_BPP8ARGB = 0x10, - OSD_BLEND_COLOR_FMT_BPP8AYUV, - OSD_BLEND_COLOR_FMT_BPP4ARGB, - OSD_BLEND_COLOR_FMT_BPP4AYUV, - OSD_BLEND_COLOR_FMT_BPP2ARGB, - OSD_BLEND_COLOR_FMT_BPP2AYUV, - OSD_BLEND_COLOR_FMT_BPP1ARGB, - OSD_BLEND_COLOR_FMT_BPP1AYUV, - OSD_BLEND_COLOR_FMT_CNT, - OSD_BLEND_COLOR_FMT_MAX = 0x7F -} OSD_BLEND_COLOR_FMT_e; - -/* OSD blending keying mode: nomarl or invert */ -typedef enum { - OSB_BLEND_KEYING_NORMAL = 0, - OSB_BLEND_KEYING_INVERT, - OSB_BLEND_KEYING_MAX = 0x7F -} OSB_BLEND_KEYING_MODE_e; - -typedef struct _osd_blend_color_keying_set_ { - /* obnd_layer_config3 */ - uint8_t min_key_alpha; - uint8_t max_key_alpha; - uint8_t min_key_rv; - uint8_t max_key_rv; - /* obnd_layer_config4 */ - uint8_t min_key_gy; - uint8_t max_key_gy; - uint8_t min_key_bu; - uint8_t max_key_bu; - /* obnd_layer_config5 */ - uint8_t replace_alpha; - uint8_t replace_rv; - uint8_t replace_gy; - uint8_t replace_bu; - /* obnd_layer_config6 */ - OSB_BLEND_KEYING_MODE_e mode_alpha; - OSB_BLEND_KEYING_MODE_e mode_rv; - OSB_BLEND_KEYING_MODE_e mode_gy; - OSB_BLEND_KEYING_MODE_e mode_bu; -} osd_blend_color_keying_set_t; - -/*@} end of group OSD_BLEND_Public_Types */ - -/** @defgroup OSD_BLEND_Public_Functions - * @{ - */ - -BL_Err_Type osd_blend_config_layer(osd_blend_reg_t *pblend, - uint32_t xstart, uint32_t ystart, - uint32_t xend, uint32_t yend, - uintptr_t *data, uint32_t dat_len); - -BL_Err_Type osd_blend_mem_access_line(osd_blend_reg_t *pblend, uint32_t req_hlen); -BL_Err_Type osd_blend_layer_early_commit(osd_blend_reg_t *pblend); -BL_Err_Type osd_blend_ctrl_layer(osd_blend_reg_t *pblend, OSD_BLEND_ST_e enable); - -BL_Err_Type osd_blend_set_color_format(osd_blend_reg_t *pblend, OSD_BLEND_COLOR_FMT_e fmt, - OSD_BLEND_COLOR_ORDER_e order_alpha, - OSD_BLEND_COLOR_ORDER_e order_r_v, - OSD_BLEND_COLOR_ORDER_e order_g_y, - OSD_BLEND_COLOR_ORDER_e order_b_u); - -BL_Err_Type osd_blend_set_global_alpha(osd_blend_reg_t *pblend, uint32_t enable, - uint8_t alpha); -BL_Err_Type osd_blend_set_global_color(osd_blend_reg_t *pblend, uint32_t enable, - uint8_t r_v, uint8_t g_y, uint8_t b_u); - -BL_Err_Type osd_blend_update_palette(osd_blend_reg_t *pblend, uint32_t color, uint8_t index); - -BL_Err_Type osd_blend_palette_keying_ctrl(osd_blend_reg_t *pblend, OSD_BLEND_ST_e enable); - -BL_Err_Type osd_blend_palette_keying(osd_blend_reg_t *pblend, OSD_BLEND_ST_e enable, - OSB_BLEND_KEYING_MODE_e mode, - uint8_t replace_index, - uint8_t min_key_index, uint8_t max_key_index); - -BL_Err_Type osd_blend_palette_keying_update_range(osd_blend_reg_t *pblend, - uint8_t min_key_index, uint8_t max_key_index); - -BL_Err_Type osd_blend_color_keying(osd_blend_reg_t *pblend, OSD_BLEND_ST_e enable, - osd_blend_color_keying_set_t *pset); - -/*@} end of group OSD_BLEND_Public_Functions */ - -/*@} end of group OSD_BLEND */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_OSD_BLEND_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_osd_draw.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_osd_draw.h deleted file mode 100644 index b424af9917..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_osd_draw.h +++ /dev/null @@ -1,212 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_osd_draw.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2021 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef __BL808_OSD_H__ -#define __BL808_OSD_H__ - -#include -#include "bl808_common.h" -#include "osd_draw_reg.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup OSD_DRAW - * @{ - */ - -/** @defgroup OSD_DRAW_Public_Macros - * @{ - */ - -/** @defgroup OSD_DRAW layer definitions - * @{ - */ - -#define OSD_A_DRAW_LAYER_L ((osd_draw_reg_t *)(OSD_A_BASE + OSD_DRAW_LOW_OFFSET)) -#define OSD_A_DRAW_LAYER_H ((osd_draw_reg_t *)(OSD_A_BASE + OSD_DRAW_HIGH_OFFSET)) - -#define OSD_B_DRAW_LAYER_L ((osd_draw_reg_t *)(OSD_B_BASE + OSD_DRAW_LOW_OFFSET)) - -#define OSD_DP_DRAW_LAYER_L ((osd_draw_reg_t *)(OSD_DP_BASE + OSD_DRAW_LOW_OFFSET)) -#define OSD_DP_DRAW_LAYER_H ((osd_draw_reg_t *)(OSD_DP_BASE + OSD_DRAW_HIGH_OFFSET)) - -/*@} end of group OSD_DRAW_Public_Macros */ -/** @defgroup OSD_DRAW_Public_Constants - * @{ - */ - -/*@} end of group OSD_DRAW_Public_Constants */ - -/** @defgroup OSD_DRAW_Public_Types - * @{ - */ - -/** - * @brief OSD_DRAW rectangle style definition - */ - -typedef enum { - OSD_RECT_STYLE_HOLLOW = 0, - OSD_RECT_STYLE_SOLID = 1, - OSD_RECT_STYLE_NUM, - OSD_RECT_STYLE_MAX = 0x7fffffff -} OSD_RECT_STYLE_Type; - -/** - * @brief OSD_DRAW rectangle state definition - */ - -typedef enum { - OSD_RECT_STATE_DISABLE = 0, - OSD_RECT_STATE_ENABLE = 1, - OSD_RECT_STATE_NUM, - OSD_RECT_STATE_MAX = 0x7fffffff -} OSD_RECT_STATE_Type; - -/** - * @brief OSD_DRAW rectangle attribute definition - */ - -typedef union _osd_attribute { - struct - { - uint32_t thinkness : 8; - uint32_t v : 8; - uint32_t u : 8; - uint32_t y : 8; -#define YUV2ATTR(y, u, v) ((y << 24) | (u << 16) | (v << 8)) -#define OSD_COLOR_BLACK YUV2ATTR(0, 128, 128) -#define OSD_COLOR_WHITE YUV2ATTR(255, 128, 128) -#define OSD_COLOR_SILVER YUV2ATTR(192, 128, 128) -#define OSD_COLOR_GRAY YUV2ATTR(127, 128, 128) -#define OSD_COLOR_DIMGRAY YUV2ATTR(105, 128, 128) -#define OSD_COLOR_RED YUV2ATTR(76, 84, 255) -#define OSD_COLOR_GREEN YUV2ATTR(149, 43, 21) -#define OSD_COLOR_BLUE YUV2ATTR(29, 255, 107) -#define OSD_COLOR_SKYBLUE YUV2ATTR(188, 154, 90) -#define OSD_COLOR_INDIGO YUV2ATTR(37, 180, 154) -#define OSD_COLOR_NAVY YUV2ATTR(14, 192, 117) -#define OSD_COLOR_MAGENTA YUV2ATTR(105, 212, 234) -#define OSD_COLOR_PURPLE YUV2ATTR(52, 170, 181) -#define OSD_COLOR_CYAN YUV2ATTR(178, 171, 0) -#define OSD_COLOR_TEAL YUV2ATTR(89, 149, 64) -#define OSD_COLOR_PINK YUV2ATTR(212, 122, 158) -#define OSD_COLOR_DEEPPINK YUV2ATTR(104, 151, 235) -#define OSD_COLOR_YELLOW YUV2ATTR(255, 0, 148) -#define OSD_COLOR_GREENYELLOW YUV2ATTR(206, 37, 103) -#define OSD_COLOR_GOLD YUV2ATTR(202, 13, 165) -#define OSD_COLOR_CHOCOLATE YUV2ATTR(127, 72, 186) -#define OSD_COLOR_ORANGE YUV2ATTR(173, 30, 186) - } yuvt; - uint32_t all; -} osd_attribute_t; - -/** - * @brief OSD_DRAW rectangle axis settings - */ - -typedef struct _osd_pos_axis { - uint32_t start : 11; /* must be EVEN */ - uint32_t rsvd0 : 5; - uint32_t end : 11; /* must be ODD */ - uint32_t rsvd1 : 5; -} osd_pos_axis_t; - -/** - * @brief OSD_DRAW rectangle position definition - */ - -typedef struct _osd_rectangle_position { - osd_pos_axis_t x; - osd_pos_axis_t y; -} osd_rectangle_pos_t; - -/** - * @brief OSD_DRAW rectangle descriptor definition - */ - -typedef struct _osd_rectangle_descriptor { - osd_attribute_t attr; - osd_rectangle_pos_t pos; -} osd_rectangle_desc_t; - -/** - * @brief OSD_DRAW rectangle definition - */ - -#define OSD_RECT_DESC_OFFSET(osd_draw) ((uintptr_t)(osd_draw) + 0x4) -#define OSD_RECT_DESC_SIZE (4 * 3) -#define OSD_RECT_DESC_ADDR(osd_draw, i) (OSD_RECT_DESC_OFFSET(osd_draw) + (i)*OSD_RECT_DESC_SIZE) -#define OSD_RECT_DESC(osd_draw, i) (osd_rectangle_desc_t *)((uintptr_t)(OSD_RECT_DESC_ADDR(osd_draw, i))) - -typedef struct _osd_rectangle { - osd_rectangle_desc_t desc; - -#define OSD_MAX_LAYER (16) -#define OSD_ALL_LAYER (-1) -#define OSD_VALID_LAYER(l) ((l)&0x0F) - uint32_t layer; - OSD_RECT_STYLE_Type style; -} osd_rectangle_t; - -/*@} end of group OSD_DRAW_Public_Types */ - -/** @defgroup OSD_DRAW_Public_Functions - * @{ - */ - -BL_Err_Type osd_draw_init(osd_draw_reg_t *odraw); -BL_Err_Type osd_draw_deinit(osd_draw_reg_t *odraw); - -BL_Err_Type osd_draw_set_layer_state(osd_draw_reg_t *odraw, uint32_t layer, OSD_RECT_STATE_Type state); -BL_Err_Type osd_draw_get_layer_state(osd_draw_reg_t *odraw, uint32_t layer, OSD_RECT_STATE_Type *state); -BL_Err_Type osd_draw_set_layer_style(osd_draw_reg_t *odraw, uint32_t layer, OSD_RECT_STYLE_Type style); -BL_Err_Type osd_draw_get_layer_style(osd_draw_reg_t *odraw, uint32_t layer, OSD_RECT_STYLE_Type *style); -BL_Err_Type osd_draw_config_rect_layer(osd_draw_reg_t *odraw, uint32_t layer, OSD_RECT_STATE_Type state, OSD_RECT_STYLE_Type style); - -BL_Err_Type osd_draw_rectangle(osd_draw_reg_t *odraw, osd_rectangle_t *rect); - -BL_Err_Type osd_draw_rectangle_onTop(osd_draw_reg_t *odraw, osd_rectangle_t *rect, uint32_t *layer); - -/*@} end of group OSD_DRAW_Public_Functions */ - -/*@} end of group OSD_DRAW */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_pwm.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_pwm.h deleted file mode 100644 index efdd41cfa8..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_pwm.h +++ /dev/null @@ -1,356 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_pwm.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_PWM_H__ -#define __BL808_PWM_H__ - -#include "pwm_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup PWM - * @{ - */ - -/** @defgroup PWM_Public_Types - * @{ - */ - -/** - * @brief PWM No. type definition - */ -typedef enum { - PWM0_ID = 0, /*!< PWM Channel 0 define */ - PWM1_ID, /*!< PWM Channel 1 define */ - PWMx_ID_MAX, /*!< */ -} PWMx_ID_Type; - -/** - * @brief PWM Clock definition - */ -typedef enum { - PWM_CLK_XCLK = 0, /*!< PWM Clock source :XTAL CLK */ - PWM_CLK_BCLK, /*!< PWM Clock source :Bus CLK */ - PWM_CLK_32K, /*!< PWM Clock source :32K CLK */ -} PWM_Clk_Type; - -/** - * @brief PWM Stop Mode definition - */ -typedef enum { - PWM_STOP_ABRUPT = 0, /*!< PWM stop abrupt select define */ - PWM_STOP_GRACEFUL, /*!< PWM stop graceful select define */ -} PWM_Stop_Mode_Type; - -/** - * @brief PWM mode type def - */ -typedef enum { - PWM_POL_ACTIVE_LOW = 0, /*!< PWM active low polarity mode define */ - PWM_POL_ACTIVE_HIGH, /*!< PWM active high polarity mode define */ -} PWM_Polarity_Type; - -/** - * @brief PWM interrupt type def - */ -typedef enum { - PWM_INT_CH0L = 0, /*!< PWM Channel 0L interrupt define */ - PWM_INT_CH0H, /*!< PWM Channel 0H interrupt define */ - PWM_INT_CH1L, /*!< PWM Channel 1H interrupt define */ - PWM_INT_CH1H, /*!< PWM Channel 1H interrupt define */ - PWM_INT_CH2L, /*!< PWM Channel 2L interrupt define */ - PWM_INT_CH2H, /*!< PWM Channel 2H interrupt define */ - PWM_INT_CH3L, /*!< PWM Channel 3L interrupt define */ - PWM_INT_CH3H, /*!< PWM Channel 3H interrupt define */ - PWM_INT_PRDE, /*!< PWM Period end interrupt define */ - PWM_INT_BRK, /*!< PWM break interrupt define */ - PWM_INT_REPT, /*!< PWM repeat interrupt define */ - PWM_INT_ALL, /*!< */ -} PWM_INT_Type; - -/** - * @brief PWM Channel No. type definition - */ -typedef enum { - PWM_CH0 = 0, /*!< PWM Channel 0 define */ - PWM_CH1, /*!< PWM Channel 1 define */ - PWM_CH2, /*!< PWM Channel 2 define */ - PWM_CH3, /*!< PWM Channel 3 define */ - PWM_CHx_MAX, /*!< */ -} PWM_CHx_Type; - -/** - * @brief PWM Mode type definition - */ -typedef enum { - PWM_MODE_DISABLE = 0, /*!< PWM Mode Disable define */ - PWM_MODE_ENABLE, /*!< PWM Mode Enable define */ -} PWM_Mode_Type; - -/** - * @brief PWM Idel State type definition - */ -typedef enum { - PWM_IDLE_STATE_INACTIVE = 0, /*!< PWM Idle State Inactive define */ - PWM_IDLE_STATE_ACTIVE, /*!< PWM Idle State Active define */ -} PWM_Idle_State_Type; - -/** - * @brief PWM break State type definition - */ -typedef enum { - PWM_BREAK_STATE_INACTIVE = 0, /*!< PWM Break State Inactive define */ - PWM_BREAK_STATE_ACTIVE, /*!< PWM Break State Active define */ -} PWM_Break_State_Type; - -/** - * @brief PWM EXT break Polarity Level type definition - */ -typedef enum { - PWM_BREAK_Polarity_LOW = 0, /*!< PWM EXT Break Polarity Low Level define */ - PWM_BREAK_Polarity_HIGH, /*!< PWM EXT Break Polarity High Level define */ -} PWM_EXT_Break_Polarity_Type; - -/** - * @brief PWM Trig ADC Source type definition - */ -typedef enum { - PWM_TRIGADC_SOURCE_0L = 0, /*!< PWM Channel 0 Threshold L Trig ADC Source define */ - PWM_TRIGADC_SOURCE_0H, /*!< PWM Channel 0 Threshold H Trig ADC Source define */ - PWM_TRIGADC_SOURCE_1L, /*!< PWM Channel 1 Threshold L Trig ADC Source define */ - PWM_TRIGADC_SOURCE_1H, /*!< PWM Channel 1 Threshold H Trig ADC Source define */ - PWM_TRIGADC_SOURCE_2L, /*!< PWM Channel 2 Threshold L Trig ADC Source define */ - PWM_TRIGADC_SOURCE_2H, /*!< PWM Channel 2 Threshold H Trig ADC Source define */ - PWM_TRIGADC_SOURCE_3L, /*!< PWM Channel 3 Threshold L Trig ADC Source define */ - PWM_TRIGADC_SOURCE_3H, /*!< PWM Channel 3 Threshold H Trig ADC Source define */ - PWM_TRIGADC_SOURCE_PRDE, /*!< PWM Period End Reached Trig ADC Source define */ - PWM_TRIGADC_SOURCE_NONE = 0xF, /*!< PWM None Trig ADC Source define */ -} PWM_TrigADC_Source_Type; - -/** - * @brief PWM configuration structure type definition - */ -typedef struct { - PWM_Clk_Type clk; /*!< PWM Clock */ - PWM_Stop_Mode_Type stopMode; /*!< PWM Stop Mode */ - PWM_EXT_Break_Polarity_Type extPol; /*!< PWM EXT_Break Polarity */ - PWM_TrigADC_Source_Type adcSrc; /*!< PWM TrigADC Source */ - BL_Fun_Type stpRept; /*!< PWM Stop On Rept */ - uint16_t clkDiv; /*!< PWM clkDiv num */ - uint16_t period; /*!< PWM period set */ - uint16_t intPulseCnt; /*!< PWM interrupt pulse count */ -} PWMx_CFG_Type; - -/** - * @brief PWM CC configuration structure type definition - */ -typedef struct { - PWM_Mode_Type modP; /*!< PWM Channelx Positive PWM mode type */ - PWM_Mode_Type modN; /*!< PWM Channelx Negative PWM mode type */ - PWM_Polarity_Type polP; /*!< PWM Channelx Positive polarity type */ - PWM_Polarity_Type polN; /*!< PWM Channelx Negative polarity type */ - PWM_Idle_State_Type idlP; /*!< PWM Channelx Positive idle state type */ - PWM_Idle_State_Type idlN; /*!< PWM Channelx Negative idle state type */ - PWM_Break_State_Type brkP; /*!< PWM Channelx Positive break state type */ - PWM_Break_State_Type brkN; /*!< PWM Channelx Negative break state type */ - uint16_t thresholdL; /*!< PWM thresholdL number */ - uint16_t thresholdH; /*!< PWM thresholdH number */ - uint8_t dtg; /*!< PWM Channelx deadtime generator */ -} PWM_CHx_CFG_Type; - -/*@} end of group PWM_Public_Types */ - -/** @defgroup PWM_Public_Constants - * @{ - */ - -/** @defgroup PWMx_ID_TYPE - * @{ - */ -#define IS_PWMx_ID_TYPE(type) (((type) == PWM0_ID) || \ - ((type) == PWM1_ID) || \ - ((type) == PWM_CH_MAX)) - -/** @defgroup PWM_CLK_TYPE - * @{ - */ -#define IS_PWM_CLK_TYPE(type) (((type) == PWM_CLK_XCLK) || \ - ((type) == PWM_CLK_BCLK) || \ - ((type) == PWM_CLK_32K)) - -/** @defgroup PWM_STOP_MODE_TYPE - * @{ - */ -#define IS_PWM_STOP_MODE_TYPE(type) (((type) == PWM_STOP_ABRUPT) || \ - ((type) == PWM_STOP_GRACEFUL)) - -/** @defgroup PWM_POLARITY_TYPE - * @{ - */ -#define IS_PWM_POLARITY_TYPE(type) (((type) == PWM_POL_ACTIVE_LOW) || \ - ((type) == PWM_POL_ACTIVE_HIGH)) - -/** @defgroup PWM_INT_TYPE - * @{ - */ -#define IS_PWM_INT_TYPE(type) (((type) == PWM_INT_CH0L) || \ - ((type) == PWM_INT_CH0H) || \ - ((type) == PWM_INT_CH1L) || \ - ((type) == PWM_INT_CH1H) || \ - ((type) == PWM_INT_CH2L) || \ - ((type) == PWM_INT_CH2H) || \ - ((type) == PWM_INT_CH3L) || \ - ((type) == PWM_INT_CH3H) || \ - ((type) == PWM_INT_PRDE) || \ - ((type) == PWM_INT_BRK) || \ - ((type) == PWM_INT_REPT) || \ - ((type) == PWM_INT_ALL)) - -/** @defgroup PWM_CHx_TYPE - * @{ - */ -#define IS_PWM_CHx_TYPE(type) (((type) == PWM_CH0) || \ - ((type) == PWM_CH1) || \ - ((type) == PWM_CH2) || \ - ((type) == PWM_CH3) || \ - ((type) == PWM_CH_MAX)) - -/** @defgroup PWM_MODE_TYPE - * @{ - */ -#define IS_PWM_MODE_TYPE(type) (((type) == PWM_MODE_DISABLE) || \ - ((type) == PWM_Mode_ENABLE)) - -/** @defgroup PWM_IDLE_STATE_TYPE - * @{ - */ -#define IS_PWM_IDLE_STATE_TYPE(type) (((type) == PWM_IDLE_STATE_INACTIVE) || \ - ((type) == PWM_IDLE_STATE_ACTIVE)) - -/** @defgroup PWM_BREAK_STATE_TYPE - * @{ - */ -#define IS_PWM_BREAK_STATE_TYPE(type) (((type) == PWM_BREAK_STATE_INACTIVE) || \ - ((type) == PWM_BREAK_STATE_ACTIVE)) - -/** @defgroup PWM_EXT_BREAK_POLARITY_TYPE - * @{ - */ -#define IS_PWM_EXT_BREAK_POLARITY_TYPE(type) (((type) == PWM_BREAK_Polarity_LOW) || \ - ((type) == PWM_BREAK_Polarity_HIGH)) - -/** @defgroup PWM_TRIGADC_SOURCE_TYPE - * @{ - */ -#define IS_PWM_TRIGADC_SOURCE_TYPE(type) (((type) == PWM_TRIGADC_SOURCE_0L) || \ - ((type) == PWM_TRIGADC_SOURCE_0H) || \ - ((type) == PWM_TRIGADC_SOURCE_1L) || \ - ((type) == PWM_TRIGADC_SOURCE_1H) || \ - ((type) == PWM_TRIGADC_SOURCE_2L) || \ - ((type) == PWM_TRIGADC_SOURCE_2H) || \ - ((type) == PWM_TRIGADC_SOURCE_3L) || \ - ((type) == PWM_TRIGADC_SOURCE_3H) || \ - ((type) == PWM_TRIGADC_SOURCE_PRDE) || \ - ((type) == PWM_TRIGADC_SOURCE_NONE)) - -/*@} end of group PWM_Public_Constants */ - -/** @defgroup PWM_Public_Macros - * @{ - */ -#define IS_PWMx_ID(CH) ((CH) < PWMx_ID_MAX) -#define IS_PWM_CHx(CH) ((CH) < PWM_CHx_MAX) - -/*@} end of group PWM_Public_Macros */ - -/** @defgroup PWM_Public_Functions - * @{ - */ - -/** - * @brief PWM Functions - */ -#ifndef BFLB_USE_HAL_DRIVER -void PWM_IRQHandler(void); -#endif -BL_Err_Type PWMx_Init(PWMx_ID_Type pwmx, PWMx_CFG_Type *cfg); -void PWMx_Div_Set(PWMx_ID_Type id, uint16_t div); -void PWMx_Period_Set(PWMx_ID_Type id, uint16_t period); -void PWMx_Period_Get(PWMx_ID_Type id, uint16_t *period); -void PWMx_Enable(PWMx_ID_Type id); -void PWMx_Disable(PWMx_ID_Type id); -void PWM_Channelx_Init(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_CHx_CFG_Type *cfg); -void PWM_Channelx_Threshold_Set(PWMx_ID_Type id, PWM_CHx_Type ch, uint16_t thresholdL, uint16_t thresholdH); -void PWM_Channelx_ThresholdL_Set(PWMx_ID_Type id, PWM_CHx_Type ch, uint16_t thresholdL); -void PWM_Channelx_ThresholdH_Set(PWMx_ID_Type id, PWM_CHx_Type ch, uint16_t thresholdH); -void PWM_Channelx_Threshold_Get(PWMx_ID_Type id, PWM_CHx_Type ch, uint16_t *thresholdL, uint16_t *thresholdH); -void PWM_Channelx_Pwm_Mode_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Mode_Type modP, PWM_Mode_Type modN); -void PWM_Channelx_Positive_Pwm_Mode_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Mode_Type mod); -void PWM_Channelx_Negative_Pwm_Mode_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Mode_Type mod); -void PWM_Channelx_Polarity_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Polarity_Type polP, PWM_Polarity_Type polN); -void PWM_Channelx_Positive_Polarity_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Polarity_Type pol); -void PWM_Channelx_Negative_Polarity_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Polarity_Type pol); -void PWM_Channelx_Idle_State_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Idle_State_Type idlP, PWM_Idle_State_Type idlN); -void PWM_Channelx_Positive_Idle_State_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Idle_State_Type idl); -void PWM_Channelx_Negative_Idle_State_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Idle_State_Type idl); -void PWM_Channelx_Break_State_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Break_State_Type brkP, PWM_Break_State_Type brkN); -void PWM_Channelx_Positive_Break_State_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Break_State_Type brk); -void PWM_Channelx_Negative_Break_State_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Break_State_Type brk); -void PWM_Config1_Set(PWMx_ID_Type id, uint32_t cfg); -void PWM_Config1_Get(PWMx_ID_Type id, uint32_t *cfg); -void PWM_Channelx_Dtg_Set(PWMx_ID_Type id, PWM_CHx_Type ch, uint8_t dtg); -void PWM_SW_Break_Enable(PWMx_ID_Type id); -void PWM_SW_Break_Disable(PWMx_ID_Type id); -void PWM_EXT_Break_Enable(PWMx_ID_Type id); -void PWM_EXT_Break_Disable(PWMx_ID_Type id); -void PWM_EXT_Break_Polarity_Set(PWMx_ID_Type id, PWM_EXT_Break_Polarity_Type pol); -void PWM_TrigADC_Source_Set(PWMx_ID_Type id, PWM_TrigADC_Source_Type src); -void PWM_Int_Mask(PWMx_ID_Type id, PWM_INT_Type intType, BL_Mask_Type intMask); -void PWM_Int_Clear(PWMx_ID_Type id, PWM_INT_Type intType); -BL_Sts_Type PWM_Int_Status_Get(PWMx_ID_Type id, PWM_INT_Type intType); -#ifndef BFLB_USE_HAL_DRIVER -void PWM_Int_Callback_Install(PWMx_ID_Type id, uint32_t intType, intCallback_Type *cbFun); -void PWM_IRQHandler(void); -#endif -/*@} end of group PWM_Public_Functions */ - -/*@} end of group PWM */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_PWM_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sec_eng.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sec_eng.h deleted file mode 100644 index 101c889048..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sec_eng.h +++ /dev/null @@ -1,778 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_sec_eng.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_SEC_ENG_H__ -#define __BL808_SEC_ENG_H__ - -#include "sec_eng_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup SEC_ENG - * @{ - */ - -/** @defgroup SEC_ENG_Public_Types - * @{ - */ - -/** - * @brief AES port type definition - */ -typedef enum { - SEC_ENG_AES_ID0, /*!< AES0 port define */ -} SEC_ENG_AES_ID_Type; - -/** - * @brief SHA port type definition - */ -typedef enum { - SEC_ENG_SHA_ID0, /*!< SHA0 port define */ -} SEC_ENG_SHA_ID_Type; - -/** - * @brief SHA type definition - */ -typedef enum { - SEC_ENG_SHA256, /*!< SHA type:SHA256 */ - SEC_ENG_SHA224, /*!< SHA type:SHA224 */ - SEC_ENG_SHA1, /*!< SHA type:SHA1 */ - SEC_ENG_SHA1_RSVD, /*!< SHA type:SHA1 */ - SEC_ENG_SHA512, /*!< SHA type:SHA512 */ - SEC_ENG_SHA384, /*!< SHA type:SHA384 */ - SEC_ENG_SHA512T224, /*!< SHA type:SHA512T224 */ - SEC_ENG_SHA512T256, /*!< SHA type:SHA512T156 */ - SEC_ENG_MD5, /*!< MD5 */ - SEC_ENG_CRC16, /*!< CRC-16 */ - SEC_ENG_CRC32, /*!< CRC-32 */ -} SEC_ENG_SHA_Type; - -/** - * @brief AES type definition - */ -typedef enum { - SEC_ENG_AES_ECB, /*!< AES mode type:ECB */ - SEC_ENG_AES_CTR, /*!< AES mode type:CTR */ - SEC_ENG_AES_CBC, /*!< AES mode type:CBC */ - SEC_ENG_AES_XTS, /*!< AES mode type:XTS */ -} SEC_ENG_AES_Type; - -/** - * @brief AES XTS mode type definition - */ -typedef enum { - SEC_ENG_AES_XTS_MODE1, /*!< AES xts mode type:mode1 */ - SEC_ENG_AES_XTS_MODE2, /*!< AES xts mode type:mode2 */ -} SEC_ENG_AES_XTS_MODE_Type; - -/** - * @brief AES KEY type definition - */ -typedef enum { - SEC_ENG_AES_KEY_128BITS, /*!< AES KEY type:128 bits */ - SEC_ENG_AES_KEY_256BITS, /*!< AES KEY type:256 bits */ - SEC_ENG_AES_KEY_192BITS, /*!< AES KEY type:192 bits */ - SEC_ENG_AES_DOUBLE_KEY_128BITS, /*!< AES double KEY type:128 bits */ -} SEC_ENG_AES_Key_Type; - -/** - * @brief AES CTR mode counter type definition - */ -typedef enum { - SEC_ENG_AES_COUNTER_BYTE_4, /*!< AES CTR mode counter type:4 bytes */ - SEC_ENG_AES_COUNTER_BYTE_1, /*!< AES CTR mode counter type:1 byte */ - SEC_ENG_AES_COUNTER_BYTE_2, /*!< AES CTR mode counter type:2 bytes */ - SEC_ENG_AES_COUNTER_BYTE_3, /*!< AES CTR mode counter type:3 bytes */ -} SEC_ENG_AES_Counter_Type; - -/** - * @brief AES use new or old value type definition - */ -typedef enum { - SEC_ENG_AES_USE_NEW, /*!< Use new value */ - SEC_ENG_AES_USE_OLD, /*!< Use old value same as last one */ -} SEC_ENG_AES_ValueUsed_Type; - -/** - * @brief AES KEY source type definition - */ -typedef enum { - SEC_ENG_AES_KEY_SW, /*!< AES KEY from software */ - SEC_ENG_AES_KEY_HW, /*!< AES KEY from hardware */ -} SEC_ENG_AES_Key_Src_Type; - -/** - * @brief AES KEY source type definition - */ -typedef enum { - SEC_ENG_AES_ENCRYPTION, /*!< AES encryption */ - SEC_ENG_AES_DECRYPTION, /*!< AES decryption */ -} SEC_ENG_AES_EnDec_Type; - -/** - * @brief AES PKA register size type definition - */ -typedef enum { - SEC_ENG_PKA_REG_SIZE_8 = 1, /*!< Register size is 8 Bytes */ - SEC_ENG_PKA_REG_SIZE_16, /*!< Register size is 16 Bytes */ - SEC_ENG_PKA_REG_SIZE_32, /*!< Register size is 32 Bytes */ - SEC_ENG_PKA_REG_SIZE_64, /*!< Register size is 64 Bytes */ - SEC_ENG_PKA_REG_SIZE_96, /*!< Register size is 96 Bytes */ - SEC_ENG_PKA_REG_SIZE_128, /*!< Register size is 128 Bytes */ - SEC_ENG_PKA_REG_SIZE_192, /*!< Register size is 192 Bytes */ - SEC_ENG_PKA_REG_SIZE_256, /*!< Register size is 256 Bytes */ - SEC_ENG_PKA_REG_SIZE_384, /*!< Register size is 384 Bytes */ - SEC_ENG_PKA_REG_SIZE_512, /*!< Register size is 512 Bytes */ -} SEC_ENG_PKA_REG_SIZE_Type; - -/** - * @brief AES PKA register size type definition - */ -typedef enum { - SEC_ENG_PKA_OP_PPSEL, /*!< PKA operation type */ - SEC_ENG_PKA_OP_MOD2N = 0x11, /*!< PKA operation type */ - SEC_ENG_PKA_OP_LDIV2N = 0x12, /*!< PKA operation type */ - SEC_ENG_PKA_OP_LMUL2N = 0x13, /*!< PKA operation type */ - SEC_ENG_PKA_OP_LDIV = 0x14, /*!< PKA operation type */ - SEC_ENG_PKA_OP_LSQR = 0x15, /*!< PKA operation type */ - SEC_ENG_PKA_OP_LMUL = 0x16, /*!< PKA operation type */ - SEC_ENG_PKA_OP_LSUB = 0x17, /*!< PKA operation type */ - SEC_ENG_PKA_OP_LADD = 0x18, /*!< PKA operation type */ - SEC_ENG_PKA_OP_LCMP = 0x19, /*!< PKA operation type */ - SEC_ENG_PKA_OP_MDIV2 = 0x21, /*!< PKA operation type */ - SEC_ENG_PKA_OP_MINV = 0x22, /*!< PKA operation type */ - SEC_ENG_PKA_OP_MEXP = 0x23, /*!< PKA operation type */ - SEC_ENG_PKA_OP_MSQR = 0x24, /*!< PKA operation type */ - SEC_ENG_PKA_OP_MMUL = 0x25, /*!< PKA operation type */ - SEC_ENG_PKA_OP_MREM = 0x26, /*!< PKA operation type */ - SEC_ENG_PKA_OP_MSUB = 0x27, /*!< PKA operation type */ - SEC_ENG_PKA_OP_MADD = 0x28, /*!< PKA operation type */ - SEC_ENG_PKA_OP_RESIZE = 0x31, /*!< PKA operation type */ - SEC_ENG_PKA_OP_MOVDAT = 0x32, /*!< PKA operation type */ - SEC_ENG_PKA_OP_NLIR = 0x33, /*!< PKA operation type */ - SEC_ENG_PKA_OP_SLIR = 0x34, /*!< PKA operation type */ - SEC_ENG_PKA_OP_CLIR = 0x35, /*!< PKA operation type */ - SEC_ENG_PKA_OP_CFLIRI_BUFFER = 0x36, /*!< PKA operation type */ - SEC_ENG_PKA_OP_CTLIRI_PLD = 0x37, /*!< PKA operation type */ - SEC_ENG_PKA_OP_CFLIR_BUFFER = 0x38, /*!< PKA operation type */ - SEC_ENG_PKA_OP_CTLIR_PLD = 0x39, /*!< PKA operation type */ -} SEC_ENG_PKA_OP_Type; - -/** - * @brief Sec Eng Interrupt Type Def - */ -typedef enum { - SEC_ENG_INT_TRNG, /*!< Sec Eng Trng Interrupt Type */ - SEC_ENG_INT_AES, /*!< Sec Eng Aes Interrupt Type */ - SEC_ENG_INT_SHA, /*!< Sec Eng Sha Interrupt Type */ - SEC_ENG_INT_PKA, /*!< Sec Eng Pka Interrupt Type */ - SEC_ENG_INT_CDET, /*!< Sec Eng Cdet Interrupt Type */ - SEC_ENG_INT_GMAC, /*!< Sec Eng Gmac Interrupt Type */ - SEC_ENG_INT_ALL, /*!< Sec Eng All Interrupt Types */ -} SEC_ENG_INT_Type; - -/** - * @brief SEC_ENG SHA256 context - */ -typedef struct -{ - uint32_t total[2]; /*!< Number of bytes processed */ - uint32_t *shaBuf; /*!< Data not processed but in this temp buffer */ - uint32_t *shaPadding; /*!< Padding data */ - uint8_t shaFeed; /*!< Sha has feed data */ -} SEC_Eng_SHA256_Ctx; - -/** - * @brief SEC_ENG SHA512 context - */ -typedef struct -{ - uint64_t total[2]; /*!< Number of bytes processed */ - uint64_t *shaBuf; /*!< Data not processed but in this temp buffer */ - uint64_t *shaPadding; /*!< Padding data */ - uint8_t shaFeed; /*!< Sha has feed data */ -} SEC_Eng_SHA512_Ctx; - -/** - * @brief SEC_ENG MD5 context - */ -typedef struct -{ - uint32_t total[2]; /*!< Number of bytes processed */ - uint32_t *md5Buf; /*!< Data not processed but in this temp buffer */ - uint32_t *md5Padding; /*!< Padding data */ - uint8_t md5Feed; /*!< md5 has feed data */ -} SEC_Eng_MD5_Ctx; - -/** - * @brief SEC_ENG SHA256 link mode context - */ -typedef struct -{ - uint32_t total[2]; /*!< Number of bytes processed */ - uint32_t *shaBuf; /*!< Data not processed but in this temp buffer */ - uint32_t *shaPadding; /*!< Padding data */ - uint32_t linkAddr; /*!< Link configure address */ -} SEC_Eng_SHA256_Link_Ctx; - -/** - * @brief SEC_ENG MD5 link mode context - */ -typedef struct -{ - uint64_t total[2]; /*!< Number of bytes processed */ - uint64_t *shaBuf; /*!< Data not processed but in this temp buffer */ - uint64_t *shaPadding; /*!< Padding data */ - uint32_t linkAddr; /*!< Link configure address */ -} SEC_Eng_SHA512_Link_Ctx; - -/** - * @brief SEC_ENG SHA256 link mode context - */ -typedef struct -{ - uint32_t total[2]; /*!< Number of bytes processed */ - uint32_t *md5Buf; /*!< Data not processed but in this temp buffer */ - uint32_t *md5Padding; /*!< Padding data */ - uint32_t linkAddr; /*!< Link configure address */ -} SEC_Eng_MD5_Link_Ctx; - -/** - * @brief SEC_ENG AES context - */ -typedef struct -{ - uint8_t aesFeed; /*!< AES has feed data */ - SEC_ENG_AES_Type mode; /*!< AES mode */ -} SEC_Eng_AES_Ctx; - -/** - * @brief SEC_ENG SHA link config structure type definition - */ -typedef struct -{ - uint32_t : 2; /*!< [1:0]Reserved */ - uint32_t shaMode : 3; /*!< [4:2]Sha-256/sha-224/sha-1/sha-1/sha-512/sha-384/sha-512T224/sha-512T256 */ - uint32_t : 1; /*!< [5]Reserved */ - uint32_t shaHashSel : 1; /*!< [6]New hash or accumulate last hash */ - uint32_t : 2; /*!< [8:7]Reserved */ - uint32_t shaIntClr : 1; /*!< [9]Clear interrupt */ - uint32_t shaIntSet : 1; /*!< [10]Set interrupt */ - uint32_t : 1; /*!< [11]Reserved */ - uint32_t shaModeExt : 2; /*!< [13:12]Extention,0:sha 1:md5 2:crc16 3:crc32 */ - uint32_t : 2; /*!< [15:14]Reserved */ - uint32_t shaMsgLen : 16; /*!< [31:16]Number of 512-bit block */ - uint32_t shaSrcAddr; /*!< Message source address */ - uint32_t result[16]; /*!< Result of SHA */ -} __attribute__((aligned(4))) SEC_Eng_SHA_Link_Config_Type; - -/** - * @brief SEC_ENG SHA link config structure type definition - */ -typedef struct -{ - uint32_t : 2; /*!< [1:0]Reserved */ - uint32_t shaMode : 3; /*!< [4:2]Sha-256/sha-224/sha-1/sha-1/sha-512/sha-384/sha-512T224/sha-512T256 */ - uint32_t : 1; /*!< [5]Reserved */ - uint32_t shaHashSel : 1; /*!< [6]New hash or accumulate last hash */ - uint32_t : 2; /*!< [8:7]Reserved */ - uint32_t shaIntClr : 1; /*!< [9]Clear interrupt */ - uint32_t shaIntSet : 1; /*!< [10]Set interrupt */ - uint32_t : 1; /*!< [11]Reserved */ - uint32_t shaModeExt : 2; /*!< [13:12]Extention,0:sha 1:md5 2:crc16 3:crc32 */ - uint32_t : 2; /*!< [15:14]Reserved */ - uint32_t shaMsgLen : 16; /*!< [31:16]Number of 512-bit block */ - uint32_t shaSrcAddr; /*!< Message source address */ - uint32_t poly; /*!< poly of CRC */ - uint32_t dout_inv : 1; /*!< [0]dout inv of CRC */ - uint32_t dout_ref : 1; /*!< [1]dout ref of CRC */ - uint32_t din_ref : 1; /*!< [2]din ref of CRC */ - uint32_t : 29; /*!< [31:3]Reserved */ - uint32_t ivAndHash; /*!< CRC hash and also used as iv in 1st block */ -} __attribute__((aligned(4))) SEC_Eng_CRC_Link_Config_Type; - -/** - * @brief SEC_ENG AES link config structure type definition - */ -typedef struct -{ - uint32_t : 3; /*!< [2:0]Reserved */ - uint32_t aesMode : 2; /*!< [4:3]128-bit/256-bit/192-bit/128-bit-double key mode select */ - uint32_t aesDecEn : 1; /*!< [5]Encode or decode */ - uint32_t aesDecKeySel : 1; /*!< [6]Use new key or use same key as last one */ - uint32_t aesHwKeyEn : 1; /*!< [7]Enable or disable using hardware hey */ - uint32_t : 1; /*!< [8]Reserved */ - uint32_t aesIntClr : 1; /*!< [9]Clear interrupt */ - uint32_t aesIntSet : 1; /*!< [10]Set interrupt */ - uint32_t : 1; /*!< [11]Reserved */ - uint32_t aesBlockMode : 2; /*!< [13:12]ECB/CTR/CBC mode select */ - uint32_t aesIVSel : 1; /*!< [14]Use new iv or use same iv as last one */ - uint32_t aesXTS : 1; /*!< [15]XTS mode select */ - uint32_t aesMsgLen : 16; /*!< [31:16]Number of 128-bit block */ - uint32_t aesSrcAddr; /*!< Message source address */ - uint32_t aesDstAddr; /*!< Message destination address */ - uint32_t aesIV0; /*!< Big endian initial vector(MSB) */ - uint32_t aesIV1; /*!< Big endian initial vector */ - uint32_t aesIV2; /*!< Big endian initial vector */ - uint32_t aesIV3; /*!< Big endian initial vector(LSB)(CTR mode:counter initial value) */ - uint32_t aesKey0; /*!< Big endian aes key(aes-128/256 key MSB) */ - uint32_t aesKey1; /*!< Big endian aes key */ - uint32_t aesKey2; /*!< Big endian aes key */ - uint32_t aesKey3; /*!< Big endian aes key(aes-128 key LSB) */ - uint32_t aesKey4; /*!< Big endian aes key */ - uint32_t aesKey5; /*!< Big endian aes key */ - uint32_t aesKey6; /*!< Big endian aes key */ - uint32_t aesKey7; /*!< Big endian aes key(aes-256 key LSB) */ -} __attribute__((aligned(4))) SEC_Eng_AES_Link_Config_Type; - -/** - * @brief SEC_ENG AES XTS mode1 link config structure type definition - */ -typedef struct -{ - uint32_t : 3; /*!< [2:0]Reserved */ - uint32_t aesMode : 2; /*!< [4:3]128-bit/256-bit/192-bit/128-bit-double key mode select */ - uint32_t aesDecEn : 1; /*!< [5]Encode or decode */ - uint32_t aesDecKeySel : 1; /*!< [6]Use new key or use same key as last one */ - uint32_t aesHwKeyEn : 1; /*!< [7]Enable or disable using hardware hey */ - uint32_t : 1; /*!< [8]Reserved */ - uint32_t aesIntClr : 1; /*!< [9]Clear interrupt */ - uint32_t aesIntSet : 1; /*!< [10]Set interrupt */ - uint32_t : 1; /*!< [11]Reserved */ - uint32_t aesBlockMode : 2; /*!< [13:12]ECB/CTR/CBC mode select */ - uint32_t aesIVSel : 1; /*!< [14]Use new iv or use same iv as last one */ - uint32_t aesXTS : 1; /*!< [15]XTS mode select */ - uint32_t aesMsgLen : 16; /*!< [31:16]Number of 128-bit block */ - uint32_t aesSrcAddr; /*!< Message source address */ - uint32_t aesDstAddr; /*!< Message destination address */ - uint32_t aesIV0; /*!< Big endian initial vector(MSB) */ - uint32_t aesIV1; /*!< Big endian initial vector */ - uint32_t aesIV2; /*!< Big endian initial vector */ - uint32_t aesIV3; /*!< Big endian initial vector(LSB)(CTR mode:counter initial value) */ - uint32_t aesKey10; /*!< Big endian aes key1(aes-128/256 key MSB) */ - uint32_t aesKey11; /*!< Big endian aes key1 */ - uint32_t aesKey12; /*!< Big endian aes key1 */ - uint32_t aesKey13; /*!< Big endian aes key1(aes-128 key LSB) */ - uint32_t aesKey14; /*!< Big endian aes key1 */ - uint32_t aesKey15; /*!< Big endian aes key1 */ - uint32_t aesKey16; /*!< Big endian aes key1 */ - uint32_t aesKey17; /*!< Big endian aes key1(aes-256 key LSB) */ - uint32_t : 16; /*!< [15:0]Reserved */ - uint32_t aesUnitLen : 16; /*!< [31:16]Big endian aes unit len */ - uint32_t aesKey20; /*!< Big endian aes key2(aes-128/256 key MSB) */ - uint32_t aesKey21; /*!< Big endian aes key2 */ - uint32_t aesKey22; /*!< Big endian aes key2 */ - uint32_t aesKey23; /*!< Big endian aes key2(aes-128 key LSB) */ - uint32_t aesKey24; /*!< Big endian aes key2 */ - uint32_t aesKey25; /*!< Big endian aes key2 */ - uint32_t aesKey26; /*!< Big endian aes key2 */ - uint32_t aesKey27; /*!< Big endian aes key2(aes-256 key LSB) */ -} __attribute__((aligned(4))) SEC_Eng_AES_XTS_Mode1_Link_Config_Type; - -/** - * @brief SEC_ENG GMAC link config structure type definition - */ -typedef struct -{ - uint32_t : 9; /*!< [8:0]reserved */ - uint32_t gmacIntClr : 1; /*!< [9]Clear interrupt */ - uint32_t gmacIntSet : 1; /*!< [10]Set interrupt */ - uint32_t : 5; /*!< [15:11]reserved */ - uint32_t gmacMsgLen : 16; /*!< [31:16]Number of 128-bit block */ - uint32_t gmacSrcAddr; /*!< Message source address */ - uint32_t gmacKey0; /*!< GMAC key */ - uint32_t gmacKey1; /*!< GMAC key */ - uint32_t gmacKey2; /*!< GMAC key */ - uint32_t gmacKey3; /*!< GMAC key */ - uint32_t result[4]; /*!< Result of GMAC */ -} __attribute__((aligned(4))) SEC_Eng_GMAC_Link_Config_Type; - -/** - * @brief SEC_ENG PKA status type definition - */ -typedef struct -{ - uint16_t primeFail : 1; /*!< [0]Prime fail */ - uint16_t errUnknown : 1; /*!< [1]Err unknown opc */ - uint16_t errOverflow : 1; /*!< [2]Err opq overflow */ - uint16_t errSrc2 : 1; /*!< [3]Err invalid src2 */ - uint16_t errSrc1 : 1; /*!< [4]Err invalid src1 */ - uint16_t errSrc0 : 1; /*!< [5]Err invalid src0 */ - uint16_t errDiv0 : 1; /*!< [6]Err div by 0 */ - uint16_t errFull : 1; /*!< [7]Err cam full */ - uint16_t lastOpc : 1; /*!< [8]Last opc */ - uint16_t opqFull : 1; /*!< [9]Opq full */ - uint16_t cmdIndex : 5; /*!< [14:10]Cmd err index */ - uint16_t errCmd : 1; /*!< [15]Err cmd */ -} SEC_Eng_PKA_Status_Type; - -/*@} end of group SEC_ENG_Public_Types */ - -/** @defgroup SEC_ENG_Public_Constants - * @{ - */ - -/** @defgroup SEC_ENG_AES_ID_TYPE - * @{ - */ -#define IS_SEC_ENG_AES_ID_TYPE(type) (((type) == SEC_ENG_AES_ID0)) - -/** @defgroup SEC_ENG_SHA_ID_TYPE - * @{ - */ -#define IS_SEC_ENG_SHA_ID_TYPE(type) (((type) == SEC_ENG_SHA_ID0)) - -/** @defgroup SEC_ENG_SHA_TYPE - * @{ - */ -#define IS_SEC_ENG_SHA_TYPE(type) (((type) == SEC_ENG_SHA256) || \ - ((type) == SEC_ENG_SHA224) || \ - ((type) == SEC_ENG_SHA1) || \ - ((type) == SEC_ENG_SHA1_RSVD) || \ - ((type) == SEC_ENG_SHA512) || \ - ((type) == SEC_ENG_SHA384) || \ - ((type) == SEC_ENG_SHA512T224) || \ - ((type) == SEC_ENG_SHA512T256) || \ - ((type) == SEC_ENG_MD5) || \ - ((type) == SEC_ENG_CRC16) || \ - ((type) == SEC_ENG_CRC32)) - -/** @defgroup SEC_ENG_AES_TYPE - * @{ - */ -#define IS_SEC_ENG_AES_TYPE(type) (((type) == SEC_ENG_AES_ECB) || \ - ((type) == SEC_ENG_AES_CTR) || \ - ((type) == SEC_ENG_AES_CBC) || \ - ((type) == SEC_ENG_AES_XTS)) - -/** @defgroup SEC_ENG_AES_XTS_MODE_TYPE - * @{ - */ -#define IS_SEC_ENG_AES_XTS_MODE_TYPE(type) (((type) == SEC_ENG_AES_XTS_MODE1) || \ - ((type) == SEC_ENG_AES_XTS_MODE2)) - -/** @defgroup SEC_ENG_AES_KEY_TYPE - * @{ - */ -#define IS_SEC_ENG_AES_KEY_TYPE(type) (((type) == SEC_ENG_AES_KEY_128BITS) || \ - ((type) == SEC_ENG_AES_KEY_256BITS) || \ - ((type) == SEC_ENG_AES_KEY_192BITS) || \ - ((type) == SEC_ENG_AES_DOUBLE_KEY_128BITS)) - -/** @defgroup SEC_ENG_AES_COUNTER_TYPE - * @{ - */ -#define IS_SEC_ENG_AES_COUNTER_TYPE(type) (((type) == SEC_ENG_AES_COUNTER_BYTE_4) || \ - ((type) == SEC_ENG_AES_COUNTER_BYTE_1) || \ - ((type) == SEC_ENG_AES_COUNTER_BYTE_2) || \ - ((type) == SEC_ENG_AES_COUNTER_BYTE_3)) - -/** @defgroup SEC_ENG_AES_VALUEUSED_TYPE - * @{ - */ -#define IS_SEC_ENG_AES_VALUEUSED_TYPE(type) (((type) == SEC_ENG_AES_USE_NEW) || \ - ((type) == SEC_ENG_AES_USE_OLD)) - -/** @defgroup SEC_ENG_AES_KEY_SRC_TYPE - * @{ - */ -#define IS_SEC_ENG_AES_KEY_SRC_TYPE(type) (((type) == SEC_ENG_AES_KEY_SW) || \ - ((type) == SEC_ENG_AES_KEY_HW)) - -/** @defgroup SEC_ENG_AES_ENDEC_TYPE - * @{ - */ -#define IS_SEC_ENG_AES_ENDEC_TYPE(type) (((type) == SEC_ENG_AES_ENCRYPTION) || \ - ((type) == SEC_ENG_AES_DECRYPTION)) - -/** @defgroup SEC_ENG_PKA_REG_SIZE_TYPE - * @{ - */ -#define IS_SEC_ENG_PKA_REG_SIZE_TYPE(type) (((type) == SEC_ENG_PKA_REG_SIZE_8) || \ - ((type) == SEC_ENG_PKA_REG_SIZE_16) || \ - ((type) == SEC_ENG_PKA_REG_SIZE_32) || \ - ((type) == SEC_ENG_PKA_REG_SIZE_64) || \ - ((type) == SEC_ENG_PKA_REG_SIZE_96) || \ - ((type) == SEC_ENG_PKA_REG_SIZE_128) || \ - ((type) == SEC_ENG_PKA_REG_SIZE_192) || \ - ((type) == SEC_ENG_PKA_REG_SIZE_256) || \ - ((type) == SEC_ENG_PKA_REG_SIZE_384) || \ - ((type) == SEC_ENG_PKA_REG_SIZE_512)) - -/** @defgroup SEC_ENG_PKA_OP_TYPE - * @{ - */ -#define IS_SEC_ENG_PKA_OP_TYPE(type) (((type) == SEC_ENG_PKA_OP_PPSEL) || \ - ((type) == SEC_ENG_PKA_OP_MOD2N) || \ - ((type) == SEC_ENG_PKA_OP_LDIV2N) || \ - ((type) == SEC_ENG_PKA_OP_LMUL2N) || \ - ((type) == SEC_ENG_PKA_OP_LDIV) || \ - ((type) == SEC_ENG_PKA_OP_LSQR) || \ - ((type) == SEC_ENG_PKA_OP_LMUL) || \ - ((type) == SEC_ENG_PKA_OP_LSUB) || \ - ((type) == SEC_ENG_PKA_OP_LADD) || \ - ((type) == SEC_ENG_PKA_OP_LCMP) || \ - ((type) == SEC_ENG_PKA_OP_MDIV2) || \ - ((type) == SEC_ENG_PKA_OP_MINV) || \ - ((type) == SEC_ENG_PKA_OP_MEXP) || \ - ((type) == SEC_ENG_PKA_OP_MSQR) || \ - ((type) == SEC_ENG_PKA_OP_MMUL) || \ - ((type) == SEC_ENG_PKA_OP_MREM) || \ - ((type) == SEC_ENG_PKA_OP_MSUB) || \ - ((type) == SEC_ENG_PKA_OP_MADD) || \ - ((type) == SEC_ENG_PKA_OP_RESIZE) || \ - ((type) == SEC_ENG_PKA_OP_MOVDAT) || \ - ((type) == SEC_ENG_PKA_OP_NLIR) || \ - ((type) == SEC_ENG_PKA_OP_SLIR) || \ - ((type) == SEC_ENG_PKA_OP_CLIR) || \ - ((type) == SEC_ENG_PKA_OP_CFLIRI_BUFFER) || \ - ((type) == SEC_ENG_PKA_OP_CTLIRI_PLD) || \ - ((type) == SEC_ENG_PKA_OP_CFLIR_BUFFER) || \ - ((type) == SEC_ENG_PKA_OP_CTLIR_PLD)) - -/** @defgroup SEC_ENG_INT_TYPE - * @{ - */ -#define IS_SEC_ENG_INT_TYPE(type) (((type) == SEC_ENG_INT_TRNG) || \ - ((type) == SEC_ENG_INT_AES) || \ - ((type) == SEC_ENG_INT_SHA) || \ - ((type) == SEC_ENG_INT_PKA) || \ - ((type) == SEC_ENG_INT_CDET) || \ - ((type) == SEC_ENG_INT_GMAC) || \ - ((type) == SEC_ENG_INT_ALL)) - -/*@} end of group SEC_ENG_Public_Constants */ - -/** @defgroup SEC_ENG_Public_Macros - * @{ - */ -#define SEC_ENG_PKA_STATUS_LAST_OPC_OFFSET 24 -#define SEC_ENG_PKA_STATUS_LAST_OPC_MASK 0x01000000 - -/*@} end of group SEC_ENG_Public_Macros */ - -/** @defgroup SEC_ENG_Public_Functions - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -void SEC_GMAC_IRQHandler(void); -void SEC_CDET_IRQHandler(void); -void SEC_TRNG_IRQHandler(void); -void SEC_PKA_IRQHandler(void); -void SEC_AES_IRQHandler(void); -void SEC_SHA_IRQHandler(void); -#endif -void Sec_Eng_SHA256_Init(SEC_Eng_SHA256_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, SEC_ENG_SHA_Type shaType, - uint32_t shaTmpBuf[16], uint32_t padding[16]); -void Sec_Eng_SHA512_Init(SEC_Eng_SHA512_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, SEC_ENG_SHA_Type shaType, - uint64_t shaTmpBuf[16], uint64_t padding[16]); -void Sec_Eng_MD5_Init(SEC_Eng_MD5_Ctx *md5Ctx, SEC_ENG_SHA_ID_Type shaNo, SEC_ENG_SHA_Type shaType, - uint32_t md5TmpBuf[16], uint32_t padding[16]); -void Sec_Eng_SHA_Start(SEC_ENG_SHA_ID_Type shaNo); -BL_Err_Type Sec_Eng_SHA256_Update(SEC_Eng_SHA256_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, const uint8_t *input, - uint32_t len); -BL_Err_Type Sec_Eng_SHA512_Update(SEC_Eng_SHA512_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, const uint8_t *input, - uint64_t len); -BL_Err_Type Sec_Eng_MD5_Update(SEC_Eng_MD5_Ctx *md5Ctx, SEC_ENG_SHA_ID_Type shaNo, const uint8_t *input, - uint32_t len); -BL_Err_Type Sec_Eng_SHA256_Finish(SEC_Eng_SHA256_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint8_t *hash); -BL_Err_Type Sec_Eng_SHA512_Finish(SEC_Eng_SHA512_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint8_t *hash); -BL_Err_Type Sec_Eng_MD5_Finish(SEC_Eng_MD5_Ctx *md5Ctx, SEC_ENG_SHA_ID_Type shaNo, uint8_t *hash); -void Sec_Eng_SHA_Enable_Link(SEC_ENG_SHA_ID_Type shaNo); -void Sec_Eng_SHA_Disable_Link(SEC_ENG_SHA_ID_Type shaNo); -void Sec_Eng_SHA256_Link_Init(SEC_Eng_SHA256_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint32_t linkAddr, - uint32_t shaTmpBuf[16], uint32_t padding[16]); -void Sec_Eng_SHA512_Link_Init(SEC_Eng_SHA512_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint32_t linkAddr, - uint64_t shaTmpBuf[16], uint64_t padding[16]); -void Sec_Eng_MD5_Link_Init(SEC_Eng_MD5_Link_Ctx *md5Ctx, SEC_ENG_SHA_ID_Type shaNo, uint32_t linkAddr, - uint32_t md5TmpBuf[16], uint32_t padding[16]); -void Sec_Eng_Set_MD5_Din(SEC_ENG_AES_ID_Type aesNo); -void Sec_Eng_Set_MD5_Din_Be(SEC_ENG_AES_ID_Type aesNo); -void Sec_Eng_Set_MD5_Dout(SEC_ENG_AES_ID_Type aesNo); -void Sec_Eng_Set_MD5_Dout_BE(SEC_ENG_AES_ID_Type aesNo); -BL_Err_Type Sec_Eng_SHA256_Link_Update(SEC_Eng_SHA256_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, - const uint8_t *input, uint32_t len); -BL_Err_Type Sec_Eng_SHA512_Link_Update(SEC_Eng_SHA512_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, - const uint8_t *input, uint64_t len); -BL_Err_Type Sec_Eng_MD5_Link_Update(SEC_Eng_MD5_Link_Ctx *md5Ctx, SEC_ENG_SHA_ID_Type shaNo, - const uint8_t *input, uint32_t len); -BL_Err_Type Sec_Eng_SHA256_Link_Finish(SEC_Eng_SHA256_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, - uint8_t *hash); -BL_Err_Type Sec_Eng_SHA512_Link_Finish(SEC_Eng_SHA512_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, - uint8_t *hash); -BL_Err_Type Sec_Eng_MD5_Link_Finish(SEC_Eng_MD5_Link_Ctx *md5Ctx, SEC_ENG_SHA_ID_Type shaNo, - uint8_t *hash); -BL_Err_Type Sec_Eng_Group0_Request_SHA_Access(void); -BL_Err_Type Sec_Eng_Group0_Release_SHA_Access(void); -BL_Err_Type Sec_Eng_Group1_Request_SHA_Access(void); -BL_Err_Type Sec_Eng_Group1_Release_SHA_Access(void); -BL_Err_Type Sec_Eng_AES_Init(SEC_Eng_AES_Ctx *aesCtx, SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Type aesType, - SEC_ENG_AES_Key_Type keyType, SEC_ENG_AES_EnDec_Type enDecType); -void Sec_Eng_AES_Enable_LE(SEC_ENG_AES_ID_Type aesNo); -void Sec_Eng_AES_Enable_BE(SEC_ENG_AES_ID_Type aesNo); -void Sec_Eng_AES_Enable_Link(SEC_ENG_AES_ID_Type aesNo); -void Sec_Eng_AES_Disable_Link(SEC_ENG_AES_ID_Type aesNo); -BL_Err_Type Sec_Eng_CRC16_Link_Work(SEC_ENG_SHA_ID_Type shaNo, uint32_t linkAddr, const uint8_t *in, uint32_t len, - uint8_t *out); -BL_Err_Type Sec_Eng_CRC32_Link_Work(SEC_ENG_SHA_ID_Type shaNo, uint32_t linkAddr, const uint8_t *in, uint32_t len, - uint8_t *out); -BL_Err_Type Sec_Eng_AES_Link_Work(SEC_ENG_AES_ID_Type aesNo, uint32_t linkAddr, const uint8_t *in, uint32_t len, - uint8_t *out); -void Sec_Eng_AES_Set_Hw_Key_Src(SEC_ENG_AES_ID_Type aesNo, uint8_t src); -void Sec_Eng_AES_Set_Key_IV(SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Key_Src_Type keySrc, const uint8_t *key, - const uint8_t *iv); -void Sec_Eng_AES_Set_Key_IV_BE(SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Key_Src_Type keySrc, const uint8_t *key, - const uint8_t *iv); -void Sec_Eng_AES_Set_Counter_Byte(SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Counter_Type counterType); -BL_Err_Type Sec_Eng_AES_Crypt(SEC_Eng_AES_Ctx *aesCtx, SEC_ENG_AES_ID_Type aesNo, const uint8_t *in, uint32_t len, - uint8_t *out); -BL_Err_Type Sec_Eng_AES_Finish(SEC_ENG_AES_ID_Type aesNo); -BL_Err_Type Sec_Eng_Group0_Request_AES_Access(void); -BL_Err_Type Sec_Eng_Group0_Release_AES_Access(void); -BL_Err_Type Sec_Eng_Group1_Request_AES_Access(void); -BL_Err_Type Sec_Eng_Group1_Release_AES_Access(void); -BL_Err_Type Sec_Eng_Trng_Enable(void); -void Sec_Eng_Trng_Int_Enable(void); -void Sec_Eng_Trng_Int_Disable(void); -BL_Err_Type Sec_Eng_Trng_Read(uint8_t data[32]); -BL_Err_Type Sec_Eng_Trng_Get_Random(uint8_t *data, uint32_t len); -void Sec_Eng_Trng_Int_Read_Trigger(void); -void Sec_Eng_Trng_Int_Read(uint8_t data[32]); -void Sec_Eng_Trng_Disable(void); -BL_Err_Type Sec_Eng_Group0_Request_Trng_Access(void); -BL_Err_Type Sec_Eng_Group0_Release_Trng_Access(void); -BL_Err_Type Sec_Eng_Group1_Request_Trng_Access(void); -BL_Err_Type Sec_Eng_Group1_Release_Trng_Access(void); -void Sec_Eng_PKA_Reset(void); -void Sec_Eng_PKA_BigEndian_Enable(void); -void Sec_Eng_PKA_LittleEndian_Enable(void); -void Sec_Eng_PKA_GetStatus(SEC_Eng_PKA_Status_Type *status); -void Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_Type regType, uint8_t regIndex, const uint32_t *data, uint16_t size, - uint8_t lastOp); -void Sec_Eng_PKA_Read_Data(SEC_ENG_PKA_REG_SIZE_Type regType, uint8_t regIdx, uint32_t *result, uint8_t retSize); -void Sec_Eng_PKA_CREG(SEC_ENG_PKA_REG_SIZE_Type dRegType, uint8_t dRegIdx, uint8_t size, uint8_t lastOp); -void Sec_Eng_PKA_Write_Immediate(SEC_ENG_PKA_REG_SIZE_Type regType, uint8_t regIndex, uint32_t data, uint8_t lastOp); -void Sec_Eng_PKA_NREG(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp); -void Sec_Eng_PKA_Move_Data(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp); -void Sec_Eng_PKA_RESIZE(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp); -void Sec_Eng_PKA_MADD(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint8_t s1RegType, - uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp); -void Sec_Eng_PKA_MSUB(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint8_t s1RegType, - uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp); -void Sec_Eng_PKA_MREM(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint8_t s2RegType, - uint8_t s2RegIdx, uint8_t lastOp); -void Sec_Eng_PKA_MMUL(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint8_t s1RegType, - uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp); -void Sec_Eng_PKA_MSQR(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint8_t s2RegType, - uint8_t s2RegIdx, uint8_t lastOp); -void Sec_Eng_PKA_MEXP(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint8_t s1RegType, - uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp); -void Sec_Eng_PKA_MINV(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint8_t s2RegType, - uint8_t s2RegIdx, uint8_t lastOp); -void Sec_Eng_PKA_MINV(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint8_t s2RegType, - uint8_t s2RegIdx, uint8_t lastOp); -void Sec_Eng_PKA_LCMP(uint8_t *cout, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t s1RegType, uint8_t s1RegIdx); -void Sec_Eng_PKA_LADD(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint8_t s1RegType, - uint8_t s1RegIdx, uint8_t lastOp); -void Sec_Eng_PKA_LSUB(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint8_t s1RegType, - uint8_t s1RegIdx, uint8_t lastOp); -void Sec_Eng_PKA_LMUL(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint8_t s1RegType, - uint8_t s1RegIdx, uint8_t lastOp); -void Sec_Eng_PKA_LSQR(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp); -void Sec_Eng_PKA_LDIV(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint8_t s2RegType, - uint8_t s2RegIdx, uint8_t lastOp); -void Sec_Eng_PKA_LMUL2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint16_t bit_shift, - uint8_t lastOp); -void Sec_Eng_PKA_LDIV2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint16_t bit_shift, - uint8_t lastOp); -void Sec_Eng_PKA_LMOD2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint16_t bit_shift, - uint8_t lastOp); -void Sec_Eng_PKA_GF2Mont(uint8_t dRegType, uint8_t dRegIdx, uint8_t sRegType, uint8_t sRegIdx, uint32_t size, - uint8_t tRegType, uint8_t tRegIdx, uint8_t pRegType, uint8_t pRegIdx); -void Sec_Eng_PKA_Mont2GF(uint8_t dRegType, uint8_t dRegIdx, uint8_t aRegType, uint8_t aRegIdx, uint8_t invrRegType, - uint8_t invrRegIdx, - uint8_t tRegType, uint8_t tRegIdx, uint8_t pRegType, uint8_t pRegIdx); -BL_Err_Type Sec_Eng_Group0_Request_PKA_Access(void); -BL_Err_Type Sec_Eng_Group0_Release_PKA_Access(void); -BL_Err_Type Sec_Eng_Group1_Request_PKA_Access(void); -BL_Err_Type Sec_Eng_Group1_Release_PKA_Access(void); -void Sec_Eng_GMAC_Enable_LE(void); -void Sec_Eng_GMAC_Enable_BE(void); -void Sec_Eng_GMAC_Enable_Link(void); -void Sec_Eng_GMAC_Disable_Link(void); -BL_Err_Type Sec_Eng_GMAC_Link_Work(uint32_t linkAddr, const uint8_t *in, uint32_t len, uint8_t *out); -BL_Err_Type Sec_Eng_Group0_Request_GMAC_Access(void); -BL_Err_Type Sec_Eng_Group0_Release_GMAC_Access(void); -BL_Err_Type Sec_Eng_Group1_Request_GMAC_Access(void); -BL_Err_Type Sec_Eng_Group1_Release_GMAC_Access(void); -void SEC_Eng_IntMask(SEC_ENG_INT_Type intType, BL_Mask_Type intMask); -void SEC_Eng_ClrIntStatus(SEC_ENG_INT_Type intType); -void SEC_Eng_Int_Callback_Install(SEC_ENG_INT_Type intType, intCallback_Type *cbFun); -BL_Sts_Type SEC_Eng_GetIntStatus(SEC_ENG_INT_Type intType); -/*----------*/ -void SEC_Eng_Turn_On_Sec_Ring(void); -void SEC_Eng_Turn_Off_Sec_Ring(void); -void Sec_Eng_PKA_Clear_Int(void); -void Sec_Eng_PKA_Read_Block(uint32_t *dest, const uint32_t *src, uint32_t len); -void Sec_Eng_PKA_Read_Block(uint32_t *dest, const uint32_t *src, uint32_t len); -void Sec_Eng_PKA_Write_Block(uint32_t *dest, const uint32_t *src, uint32_t len); -void Sec_Eng_PKA_Write_Block(uint32_t *dest, const uint32_t *src, uint32_t len); -/*----------*/; - -/*@} end of group SEC_ENG_Public_Functions */ - -/*@} end of group SEC_ENG */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_SEC_ENG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sf_cfg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sf_cfg.h deleted file mode 100644 index ee315f7f98..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sf_cfg.h +++ /dev/null @@ -1,106 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_sf_cfg.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_SF_CFG_H__ -#define __BL808_SF_CFG_H__ - -#include "string.h" -#include "bl808_glb.h" -#include "bl808_glb_gpio.h" -#include "bl808_sflash.h" -#include "bl808_sf_ctrl.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup SF_CFG - * @{ - */ - -/** @defgroup SF_CFG_Public_Types - * @{ - */ - -/*@} end of group SF_CFG_Public_Types */ - -/** @defgroup SF_CFG_Public_Constants - * @{ - */ - -/*@} end of group SF_CFG_Public_Constants */ - -/** @defgroup SF_CFG_Public_Macros - * @{ - */ -/* Flash option sf2 */ -/* Flash CLK */ -#define BFLB_EXTFLASH_CLK0_GPIO GLB_GPIO_PIN_34 -/* FLASH CS */ -#define BFLB_EXTFLASH_CS0_GPIO GLB_GPIO_PIN_35 -/* FLASH DATA */ -#define BFLB_EXTFLASH_DATA00_GPIO GLB_GPIO_PIN_36 -#define BFLB_EXTFLASH_DATA10_GPIO GLB_GPIO_PIN_37 -#define BFLB_EXTFLASH_DATA20_GPIO GLB_GPIO_PIN_38 -#define BFLB_EXTFLASH_DATA30_GPIO GLB_GPIO_PIN_39 -#define BFLB_FLASH_ID_VALID_FLAG 0x80000000 -#define BFLB_FLASH_ID_VALID_MASK 0x7FFFFFFF - -/*@} end of group SF_CFG_Public_Macros */ - -/** @defgroup SF_CFG_Public_Functions - * @{ - */ -BL_Err_Type SF_Cfg_Get_Flash_Cfg_Need_Lock(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg, - uint8_t group, SF_Ctrl_Bank_Select bank); -BL_Err_Type SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg, - uint8_t group, SF_Ctrl_Bank_Select bank); -BL_Err_Type SF_Cfg_Init_Flash_Gpio(SF_Ctrl_Pin_Select flashPinCfg, uint8_t restoreDefault); -BL_Err_Type SF_Cfg_Init_Ext_Flash_Gpio(uint8_t extFlashPin); -BL_Err_Type SF_Cfg_Deinit_Ext_Flash_Gpio(uint8_t extFlashPin); -uint32_t SF_Cfg_Flash_Identify(uint8_t callFromFlash, uint8_t flashPinCfg, uint8_t restoreDefault, - SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank); -uint32_t SF_Cfg_Flash_Identify_Ext(uint8_t callFromFlash, uint8_t flashPinCfg, uint8_t restoreDefault, - SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank); -BL_Err_Type SF_Cfg_Flash_Init(SF_Ctrl_Pin_Select sel, const SF_Ctrl_Cfg_Type *pSfCtrlCfg, const SF_Ctrl_Bank2_Cfg *pBank2Cfg); -BL_Err_Type SF_Cfg_Sbus2_Flash_Init(SF_Ctrl_Pin_Select sel, const SF_Ctrl_Bank2_Cfg *pBank2Cfg); - -/*@} end of group SF_CFG_Public_Functions */ - -/*@} end of group SF_CFG */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_SF_CFG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sf_ctrl.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sf_ctrl.h deleted file mode 100644 index eea942a1e6..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sf_ctrl.h +++ /dev/null @@ -1,470 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_sf_ctrl.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_SF_CTRL_H__ -#define __BL808_SF_CTRL_H__ - -#include "sf_ctrl_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup SF_CTRL - * @{ - */ - -/** @defgroup SF_CTRL_Public_Types - * @{ - */ - -/** - * @brief Serial flash pad type definition - */ -typedef enum { - SF_CTRL_PAD1, /*!< SF Ctrl pad 1 */ - SF_CTRL_PAD2, /*!< SF Ctrl pad 2 */ - SF_CTRL_PAD3, /*!< SF Ctrl pad 3 */ -} SF_Ctrl_Pad_Type; - -/** - * @brief Serial flash config pin select type definition - */ -typedef enum { - SF_IO_EMB_SWAP_IO0_IO3 = 0x0, /*!< SF select embedded flash swap io0 with io3 */ - SF_IO_EMB_SWAP_DUAL_IO0_IO3 = 0x1, /*!< SF select embedded flash swap dual io0 with io3 */ - SF_IO_EMB_SWAP_NONE = 0x2, /*!< SF select embedded flash no swap */ - SF_IO_EMB_SWAP_NONE_DUAL_IO0 = 0x3, /*!< SF select embedded flash no swap and use dual io0 */ - SF_IO_EXT_SF2 = 0x4, /*!< SF select external flash SF2 use gpio34-39 */ - SF_IO_EMB_SWAP_IO0_IO3_AND_EXT_SF2 = 0x14, /*!< SF select embedded flash swap io0 with io3 and external SF2 use gpio34-39 */ - SF_IO_EMB_SWAP_DUAL_IO0_IO3_AND_EXT_SF2 = 0x15, /*!< SF select embedded flash swap dual io0 with io3 and external SF2 use gpio34-39 */ - SF_IO_EMB_SWAP_NONE_AND_EXT_SF2 = 0x16, /*!< SF select embedded flash no swap and external SF2 use gpio34-39 */ - SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2 = 0x17, /*!< SF select embedded flash no swap, use dual io0 and external SF2 use gpio34-39 */ -} SF_Ctrl_Pin_Select; - -/** - * @brief Serial flash select bank control type definition - */ -typedef enum { - SF_CTRL_FLASH_BANK0, /*!< SF Ctrl select flash bank0 */ - SF_CTRL_FLASH_BANK1, /*!< SF Ctrl select flash bank1 */ -} SF_Ctrl_Bank_Select; - -/** - * @brief Serial flash controller wrap mode type definition - */ -typedef enum { - SF_CTRL_WRAP_MODE_0, /*!< Cmds bypass wrap commands to macro, original mode */ - SF_CTRL_WRAP_MODE_1, /*!< Cmds handle wrap commands, original mode */ - SF_CTRL_WRAP_MODE_2, /*!< Cmds bypass wrap commands to macro, cmds force wrap16*4 splitted into two wrap8*4 */ - SF_CTRL_WRAP_MODE_3, /*!< Cmds handle wrap commands, cmds force wrap16*4 splitted into two wrap8*4 */ -} SF_Ctrl_Wrap_Mode; - -/** - * @brief Serail flash controller wrap mode len type definition - */ -typedef enum { - SF_CTRL_WRAP_LEN_8, /*!< SF Ctrl wrap length: 8 */ - SF_CTRL_WRAP_LEN_16, /*!< SF Ctrl wrap length: 16 */ - SF_CTRL_WRAP_LEN_32, /*!< SF Ctrl wrap length: 32 */ - SF_CTRL_WRAP_LEN_64, /*!< SF Ctrl wrap length: 64 */ - SF_CTRL_WRAP_LEN_128, /*!< SF Ctrl wrap length: 128 */ - SF_CTRL_WRAP_LEN_256, /*!< SF Ctrl wrap length: 256 */ - SF_CTRL_WRAP_LEN_512, /*!< SF Ctrl wrap length: 512 */ - SF_CTRL_WRAP_LEN_1024, /*!< SF Ctrl wrap length: 1024 */ - SF_CTRL_WRAP_LEN_2048, /*!< SF Ctrl wrap length: 2048 */ - SF_CTRL_WRAP_LEN_4096, /*!< SF Ctrl wrap length: 4096 */ -} SF_Ctrl_Wrap_Len_Type; - -/** - * @brief Serail flash controller memory remap type define - */ -typedef enum { - SF_CTRL_ORIGINAL_MEMORY_MAP, /*!< Remap none, use two addr map when use dual flash */ - SF_CTRL_REMAP_16MB, /*!< Remap HADDR>16MB region to psram port HADDR[24] -> HADDR[28] */ - SF_CTRL_REMAP_8MB, /*!< Remap HADDR>8MB region to psram port HADDR[23] -> HADDR[28] */ - SF_CTRL_REMAP_4MB, /*!< Remap HADDR>4MB region to psram port HADDR[22] -> HADDR[28] */ -} SF_Ctrl_Remap_Type; - -/** - * @brief Serial flash controller owner type definition - */ -typedef enum { - SF_CTRL_OWNER_SAHB, /*!< System AHB bus control serial flash controller */ - SF_CTRL_OWNER_IAHB, /*!< I-Code AHB bus control serial flash controller */ -} SF_Ctrl_Owner_Type; - -/** - * @brief Read and write type definition - */ -typedef enum { - SF_CTRL_READ, /*!< Serail flash read command flag */ - SF_CTRL_WRITE, /*!< Serail flash write command flag */ -} SF_Ctrl_RW_Type; - -/** - * @brief Serail flash interface IO type definition - */ -typedef enum { - SF_CTRL_NIO_MODE, /*!< Normal IO mode define */ - SF_CTRL_DO_MODE, /*!< Dual Output mode define */ - SF_CTRL_QO_MODE, /*!< Quad Output mode define */ - SF_CTRL_DIO_MODE, /*!< Dual IO mode define */ - SF_CTRL_QIO_MODE, /*!< Quad IO mode define */ -} SF_Ctrl_IO_Type; - -/** - * @brief Serail flash controller interface mode type definition - */ -typedef enum { - SF_CTRL_SPI_MODE, /*!< SPI mode define */ - SF_CTRL_QPI_MODE, /*!< QPI mode define */ -} SF_Ctrl_Mode_Type; - -/** - * @brief Serail flash controller command mode type definition - */ -typedef enum { - SF_CTRL_CMD_1_LINE, /*!< Command in one line mode */ - SF_CTRL_CMD_4_LINES, /*!< Command in four lines mode */ -} SF_Ctrl_Cmd_Mode_Type; - -/** - * @brief Serail flash controller address mode type definition - */ -typedef enum { - SF_CTRL_ADDR_1_LINE, /*!< Address in one line mode */ - SF_CTRL_ADDR_2_LINES, /*!< Address in two lines mode */ - SF_CTRL_ADDR_4_LINES, /*!< Address in four lines mode */ -} SF_Ctrl_Addr_Mode_Type; - -/** - * @brief Serail flash controller dummy mode type definition - */ -typedef enum { - SF_CTRL_DUMMY_1_LINE, /*!< Dummy in one line mode */ - SF_CTRL_DUMMY_2_LINES, /*!< Dummy in two lines mode */ - SF_CTRL_DUMMY_4_LINES, /*!< Dummy in four lines mode */ -} SF_Ctrl_Dmy_Mode_Type; - -/** - * @brief Serail flash controller data mode type definition - */ -typedef enum { - SF_CTRL_DATA_1_LINE, /*!< Data in one line mode */ - SF_CTRL_DATA_2_LINES, /*!< Data in two lines mode */ - SF_CTRL_DATA_4_LINES, /*!< Data in four lines mode */ -} SF_Ctrl_Data_Mode_Type; - -/** - * @brief Serail flash controller AES mode type definition - */ -typedef enum { - SF_CTRL_AES_CTR_MODE, /*!< Serail flash AES CTR mode */ - SF_CTRL_AES_XTS_MODE, /*!< Serail flash AES XTS mode */ -} SF_Ctrl_AES_Mode_Type; - -/** - * @brief Serail flash controller AES key len type definition - */ -typedef enum { - SF_CTRL_AES_128BITS, /*!< Serail flash AES key 128 bits length */ - SF_CTRL_AES_256BITS, /*!< Serail flash AES key 256 bits length */ - SF_CTRL_AES_192BITS, /*!< Serail flash AES key 192 bits length */ - SF_CTRL_AES_128BITS_DOUBLE_KEY, /*!< Serail flash AES key 128 bits length double key */ -} SF_Ctrl_AES_Key_Type; - -/** - * @brief Serail flash controller configuration structure type definition - */ -typedef struct -{ - SF_Ctrl_Owner_Type owner; /*!< Sflash interface bus owner */ - BL_Fun_Type en32bAddr; /*!< Sflash enable 32-bits address */ - uint8_t clkDelay; /*!< Clock count for read due to pad delay */ - uint8_t clkInvert; /*!< Clock invert */ - uint8_t rxClkInvert; /*!< RX clock invert */ - uint8_t doDelay; /*!< Data out delay */ - uint8_t diDelay; /*!< Data in delay */ - uint8_t oeDelay; /*!< Output enable delay */ -} SF_Ctrl_Cfg_Type; - -/** - * @brief SF Ctrl bank2 controller configuration structure type definition - */ -typedef struct -{ - BL_Fun_Type sbus2Select; /*!< Select sbus2 as 2nd flash controller */ - BL_Fun_Type bank2RxClkInvertSrc; /*!< Select bank2 rx clock invert source */ - BL_Fun_Type bank2RxClkInvertSel; /*!< Select inveted bank2 rx clock */ - BL_Fun_Type bank2DelaySrc; /*!< Select bank2 read delay source */ - uint8_t bank2ClkDelay; /*!< Bank2 read delay cycle = n + 1 */ - uint8_t doDelay; /*!< Data out delay */ - uint8_t diDelay; /*!< Data in delay */ - uint8_t oeDelay; /*!< Output enable delay */ - SF_Ctrl_Remap_Type remap; /*!< Select dual flash memory remap set */ - uint8_t remapLock; /*!< Select memory remap lock */ -} SF_Ctrl_Bank2_Cfg; - -/** - * @brief SF Ctrl cmds configuration structure type definition - */ -typedef struct -{ - uint8_t ackLatency; /*!< SF Ctrl ack latency cycles */ - BL_Fun_Type cmdsCoreEn; /*!< SF Ctrl cmds core enable */ - BL_Fun_Type cmdsEn; /*!< SF Ctrl cmds enable */ - SF_Ctrl_Wrap_Mode cmdsWrapMode; /*!< SF Ctrl cmds wrap mode */ - SF_Ctrl_Wrap_Len_Type cmdsWrapLen; /*!< SF Ctrl cmds wrap length */ -} SF_Ctrl_Cmds_Cfg; - -/** - * @brief Serail flash command configuration structure type definition - */ -typedef struct -{ - uint8_t rwFlag; /*!< Read write flag */ - SF_Ctrl_Cmd_Mode_Type cmdMode; /*!< Command mode */ - SF_Ctrl_Addr_Mode_Type addrMode; /*!< Address mode */ - uint8_t addrSize; /*!< Address size */ - uint8_t dummyClks; /*!< Dummy clocks */ - SF_Ctrl_Dmy_Mode_Type dummyMode; /*!< Dummy mode */ - SF_Ctrl_Data_Mode_Type dataMode; /*!< Data mode */ - uint8_t rsv[1]; /*!< */ - uint32_t nbData; /*!< Transfer number of bytes */ - uint32_t cmdBuf[2]; /*!< Command buffer */ -} SF_Ctrl_Cmd_Cfg_Type; - -/*@} end of group SF_CTRL_Public_Types */ - -/** @defgroup SF_CTRL_Public_Constants - * @{ - */ - -/** @defgroup SF_CTRL_PAD_TYPE - * @{ - */ -#define IS_SF_CTRL_PAD_TYPE(type) (((type) == SF_CTRL_PAD1) || \ - ((type) == SF_CTRL_PAD2) || \ - ((type) == SF_CTRL_PAD3)) - -/** @defgroup SF_CTRL_PIN_SELECT - * @{ - */ -#define IS_SF_CTRL_PIN_SELECT(type) (((type) == SF_IO_EMB_SWAP_IO0_IO3) || \ - ((type) == SF_IO_EMB_SWAP_DUAL_IO0_IO3) || \ - ((type) == SF_IO_EMB_SWAP_NONE) || \ - ((type) == SF_IO_EMB_SWAP_NONE_DUAL_IO0) || \ - ((type) == SF_IO_EXT_SF2) || \ - ((type) == SF_IO_EMB_SWAP_IO0_IO3_AND_EXT_SF2) || \ - ((type) == SF_IO_EMB_SWAP_DUAL_IO0_IO3_AND_EXT_SF2) || \ - ((type) == SF_IO_EMB_SWAP_NONE_AND_EXT_SF2) || \ - ((type) == SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2)) - -/** @defgroup SF_CTRL_BANK_SELECT - * @{ - */ -#define IS_SF_CTRL_BANK_SELECT(type) (((type) == SF_CTRL_FLASH_BANK0) || \ - ((type) == SF_CTRL_FLASH_BANK1)) - -/** @defgroup SF_CTRL_WRAP_MODE - * @{ - */ -#define IS_SF_CTRL_WRAP_MODE(type) (((type) == SF_CTRL_WRAP_MODE_0) || \ - ((type) == SF_CTRL_WRAP_MODE_1) || \ - ((type) == SF_CTRL_WRAP_MODE_2) || \ - ((type) == SF_CTRL_WRAP_MODE_3)) - -/** @defgroup SF_CTRL_WRAP_LEN_TYPE - * @{ - */ -#define IS_SF_CTRL_WRAP_LEN_TYPE(type) (((type) == SF_CTRL_WRAP_LEN_8) || \ - ((type) == SF_CTRL_WRAP_LEN_16) || \ - ((type) == SF_CTRL_WRAP_LEN_32) || \ - ((type) == SF_CTRL_WRAP_LEN_64) || \ - ((type) == SF_CTRL_WRAP_LEN_128) || \ - ((type) == SF_CTRL_WRAP_LEN_256) || \ - ((type) == SF_CTRL_WRAP_LEN_512) || \ - ((type) == SF_CTRL_WRAP_LEN_1024) || \ - ((type) == SF_CTRL_WRAP_LEN_2048) || \ - ((type) == SF_CTRL_WRAP_LEN_4096)) - -/** @defgroup SF_CTRL_REMAP_TYPE - * @{ - */ -#define IS_SF_CTRL_REMAP_TYPE(type) (((type) == SF_CTRL_ORIGINAL_MEMORY_MAP) || \ - ((type) == SF_CTRL_REMAP_16MB) || \ - ((type) == SF_CTRL_REMAP_8MB) || \ - ((type) == SF_CTRL_REMAP_4MB)) - -/** @defgroup SF_CTRL_OWNER_TYPE - * @{ - */ -#define IS_SF_CTRL_OWNER_TYPE(type) (((type) == SF_CTRL_OWNER_SAHB) || \ - ((type) == SF_CTRL_OWNER_IAHB)) - -/** @defgroup SF_CTRL_RW_TYPE - * @{ - */ -#define IS_SF_CTRL_RW_TYPE(type) (((type) == SF_CTRL_READ) || \ - ((type) == SF_CTRL_WRITE)) - -/** @defgroup SF_CTRL_IO_TYPE - * @{ - */ -#define IS_SF_CTRL_IO_TYPE(type) (((type) == SF_CTRL_NIO_MODE) || \ - ((type) == SF_CTRL_DO_MODE) || \ - ((type) == SF_CTRL_QO_MODE) || \ - ((type) == SF_CTRL_DIO_MODE) || \ - ((type) == SF_CTRL_QIO_MODE)) - -/** @defgroup SF_CTRL_MODE_TYPE - * @{ - */ -#define IS_SF_CTRL_MODE_TYPE(type) (((type) == SF_CTRL_SPI_MODE) || \ - ((type) == SF_CTRL_QPI_MODE)) - -/** @defgroup SF_CTRL_CMD_MODE_TYPE - * @{ - */ -#define IS_SF_CTRL_CMD_MODE_TYPE(type) (((type) == SF_CTRL_CMD_1_LINE) || \ - ((type) == SF_CTRL_CMD_4_LINES)) - -/** @defgroup SF_CTRL_ADDR_MODE_TYPE - * @{ - */ -#define IS_SF_CTRL_ADDR_MODE_TYPE(type) (((type) == SF_CTRL_ADDR_1_LINE) || \ - ((type) == SF_CTRL_ADDR_2_LINES) || \ - ((type) == SF_CTRL_ADDR_4_LINES)) - -/** @defgroup SF_CTRL_DMY_MODE_TYPE - * @{ - */ -#define IS_SF_CTRL_DMY_MODE_TYPE(type) (((type) == SF_CTRL_DUMMY_1_LINE) || \ - ((type) == SF_CTRL_DUMMY_2_LINES) || \ - ((type) == SF_CTRL_DUMMY_4_LINES)) - -/** @defgroup SF_CTRL_DATA_MODE_TYPE - * @{ - */ -#define IS_SF_CTRL_DATA_MODE_TYPE(type) (((type) == SF_CTRL_DATA_1_LINE) || \ - ((type) == SF_CTRL_DATA_2_LINES) || \ - ((type) == SF_CTRL_DATA_4_LINES)) - -/** @defgroup SF_CTRL_AES_MODE_TYPE - * @{ - */ -#define IS_SF_CTRL_AES_MODE_TYPE(type) (((type) == SF_CTRL_AES_CTR_MODE) || \ - ((type) == SF_CTRL_AES_XTS_MODE)) - -/** @defgroup SF_CTRL_AES_KEY_TYPE - * @{ - */ -#define IS_SF_CTRL_AES_KEY_TYPE(type) (((type) == SF_CTRL_AES_128BITS) || \ - ((type) == SF_CTRL_AES_256BITS) || \ - ((type) == SF_CTRL_AES_192BITS) || \ - ((type) == SF_CTRL_AES_128BITS_DOUBLE_KEY)) - -/*@} end of group SF_CTRL_Public_Constants */ - -/** @defgroup SF_CTRL_Public_Macros - * @{ - */ -#define SF_CTRL_NO_ADDRESS 0xFFFFFFFF -#define NOR_FLASH_CTRL_BUF_SIZE 256 -#define NAND_FLASH_CTRL_BUF_SIZE 512 - -/*@} end of group SF_CTRL_Public_Macros */ - -/** @defgroup SF_CTRL_Public_Functions - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -void SF_Ctrl_IRQHandler(void); -#endif -void SF_Ctrl_Enable(const SF_Ctrl_Cfg_Type *cfg); -void SF_Ctrl_Bank2_Enable(const SF_Ctrl_Bank2_Cfg *bank2Cfg); -void SF_Ctrl_Set_IO_Delay(SF_Ctrl_Pad_Type pad, uint8_t doDelay, uint8_t diDelay, uint8_t oeDelay); -void SF_Ctrl_Sbus2_Hold_Sram(void); -void SF_Ctrl_Sbus2_Release_Sram(void); -BL_Sts_Type SF_Ctrl_Is_Sbus2_Enable(void); -void SF_Ctrl_Sbus2_Replace(SF_Ctrl_Pad_Type pad); -void SF_Ctrl_Sbus2_Revoke_replace(void); -void SF_Ctrl_Sbus2_Set_Delay(uint8_t clkDelay, uint8_t rxClkInvert); -void SF_Ctrl_32bits_Addr_En(BL_Fun_Type en32BitsAddr); -uint8_t SF_Ctrl_Get_Clock_Delay(void); -void SF_Ctrl_Set_Clock_Delay(uint8_t delay); -uint8_t SF_Ctrl_Get_Wrap_Queue_Value(void); -void SF_Ctrl_Cmds_Set(SF_Ctrl_Cmds_Cfg *cmdsCfg, SF_Ctrl_Bank_Select bank); -void SF_Ctrl_Remap_Set(SF_Ctrl_Remap_Type remap, uint8_t lock); -void SF_Ctrl_Select_Pad(SF_Ctrl_Pin_Select sel); -void SF_Ctrl_Sbus_Select_Bank(SF_Ctrl_Bank_Select bank); -void SF_Ctrl_Set_Owner(SF_Ctrl_Owner_Type owner); -void SF_Ctrl_Disable(void); -void SF_Ctrl_AES_Enable_BE(void); -void SF_Ctrl_AES_Enable_LE(void); -void SF_Ctrl_AES_Set_Region(uint8_t region, uint8_t enable, uint8_t hwKey, uint32_t startAddr, uint32_t endAddr, - uint8_t locked); -void SF_Ctrl_AES_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType); -void SF_Ctrl_AES_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType); -void SF_Ctrl_AES_XTS_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType); -void SF_Ctrl_AES_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType); -void SF_Ctrl_AES_XTS_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType); -void SF_Ctrl_AES_XTS_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType); -void SF_Ctrl_AES_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset); -void SF_Ctrl_AES_XTS_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset); -void SF_Ctrl_AES_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset); -void SF_Ctrl_AES_XTS_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset); -void SF_Ctrl_AES_Set_Mode(SF_Ctrl_AES_Mode_Type mode); -void SF_Ctrl_AES_Enable(void); -void SF_Ctrl_AES_Disable(void); -BL_Sts_Type SF_Ctrl_Is_AES_Enable(void); -void SF_Ctrl_Set_Flash_Image_Offset(uint32_t addrOffset, uint8_t group, SF_Ctrl_Bank_Select bank); -uint32_t SF_Ctrl_Get_Flash_Image_Offset(uint8_t group, SF_Ctrl_Bank_Select bank); -void SF_Ctrl_Lock_Flash_Image_Offset(uint8_t lock); -void SF_Ctrl_SendCmd(SF_Ctrl_Cmd_Cfg_Type *cfg); -void SF_Ctrl_Disable_Wrap_Access(uint8_t disable); -void SF_Ctrl_Flash_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid); -void SF_Ctrl_Flash2_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid); -BL_Sts_Type SF_Ctrl_GetBusyState(void); - -/*@} end of group SF_CTRL_Public_Functions */ - -/*@} end of group SF_CTRL */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_SF_CTRL_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_spi.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_spi.h deleted file mode 100644 index bddd2ee875..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_spi.h +++ /dev/null @@ -1,321 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_spi.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_SPI_H__ -#define __BL808_SPI_H__ - -#include "spi_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup SPI - * @{ - */ - -/** @defgroup SPI_Public_Types - * @{ - */ - -/** - * @brief SPI No. type definition - */ -typedef enum { - SPI0_ID, /*!< SPI0 port define */ - SPI0_MM_ID, /*!< MM system SPI0 port define */ - SPI_ID_MAX, /*!< SPI MAX ID define */ -} SPI_ID_Type; - -/** - * @brief SPI slave pin mode type definition - */ -typedef enum { - SPI_SLAVE_PIN_4, /*!< SPI 4-pin mode(CS is enabled) */ - SPI_SLAVE_PIN_3, /*!< SPI 3-pin mode(CS don't case) */ -} SPI_Slave_Pin_Type; - -/** - * @brief SPI byte inverse type definition - */ -typedef enum { - SPI_BYTE_INVERSE_BYTE0_FIRST, /*!< SPI byte 0 is sent out first */ - SPI_BYTE_INVERSE_BYTE3_FIRST, /*!< SPI byte 3 is sent out first */ -} SPI_BYTE_INVERSE_Type; - -/** - * @brief SPI bit inverse type definition - */ -typedef enum { - SPI_BIT_INVERSE_MSB_FIRST, /*!< SPI each byte is sent out MSB first */ - SPI_BIT_INVERSE_LSB_FIRST, /*!< SPI each byte is sent out LSB first */ -} SPI_BIT_INVERSE_Type; - -/** - * @brief SPI clock phase inverse type definition - */ -typedef enum { - SPI_CLK_PHASE_INVERSE_0, /*!< SPI clock phase inverse 0 */ - SPI_CLK_PHASE_INVERSE_1, /*!< SPI clock phase inverse 1 */ -} SPI_CLK_PHASE_INVERSE_Type; - -/** - * @brief SPI clock polarity type definition - */ -typedef enum { - SPI_CLK_POLARITY_LOW, /*!< SPI clock output low at IDLE state */ - SPI_CLK_POLARITY_HIGH, /*!< SPI clock output high at IDLE state */ -} SPI_CLK_POLARITY_Type; - -/** - * @brief SPI frame size(also the valid width for each fifo entry) type definition - */ -typedef enum { - SPI_FRAME_SIZE_8, /*!< SPI frame size 8 bit */ - SPI_FRAME_SIZE_16, /*!< SPI frame size 16 bit */ - SPI_FRAME_SIZE_24, /*!< SPI frame size 24 bit */ - SPI_FRAME_SIZE_32, /*!< SPI frame size 32 bit */ -} SPI_FrameSize_Type; - -/** - * @brief SPI work mode select type definition - */ -typedef enum { - SPI_WORK_MODE_SLAVE, /*!< SPI work at slave mode */ - SPI_WORK_MODE_MASTER, /*!< SPI work at master mode */ -} SPI_WORK_MODE_Type; - -/** - * @brief SPI enable or disable timeout judgment definition - */ -typedef enum { - SPI_TIMEOUT_DISABLE, /*!< SPI disable timeout judgment */ - SPI_TIMEOUT_ENABLE, /*!< SPI enable timeout judgment */ -} SPI_Timeout_Type; - -/** - * @brief SPI fifo overflow/underflow flag type definition - */ -typedef enum { - SPI_FIFO_TX_OVERFLOW, /*!< SPI tx fifo overflow flag */ - SPI_FIFO_TX_UNDERFLOW, /*!< SPI tx fifo underflow flag */ - SPI_FIFO_RX_OVERFLOW, /*!< SPI rx fifo overflow flag */ - SPI_FIFO_RX_UNDERFLOW, /*!< SPI rx fifo underflow flag */ -} SPI_FifoStatus_Type; - -/** - * @brief SPI interrupt type definition - */ -typedef enum { - SPI_INT_END, /*!< SPI transfer end interrupt,shared by both master and slave mode */ - SPI_INT_TX_FIFO_REQ, /*!< SPI tx fifo ready interrupt(tx fifo count > tx fifo threshold) */ - SPI_INT_RX_FIFO_REQ, /*!< SPI rx fifo ready interrupt(rx fifo count > rx fifo threshold) */ - SPI_INT_SLAVE_TIMEOUT, /*!< SPI slave mode transfer time-out interrupt,triggered when spi bus is idle for the given value */ - SPI_INT_SLAVE_UNDERRUN, /*!< SPI slave mode tx underrun error interrupt,triggered when tx is not ready during transfer */ - SPI_INT_FIFO_ERROR, /*!< SPI tx/rx fifo error interrupt(overflow/underflow) */ - SPI_INT_ALL, /*!< All the interrupt */ -} SPI_INT_Type; - -/** - * @brief SPI configuration type definition - */ -typedef struct -{ - BL_Fun_Type deglitchEnable; /*!< Enable or disable de-glitch function */ - SPI_Slave_Pin_Type slavePin; /*!< Slave 4/3 pin mode */ - BL_Fun_Type continuousEnable; /*!< Enable or disable master continuous transfer mode,enable:SS will stay asserted if next data is valid */ - SPI_BYTE_INVERSE_Type byteSequence; /*!< The byte is sent first in SPI transfer */ - SPI_BIT_INVERSE_Type bitSequence; /*!< The bit is sent first in SPI transfer */ - SPI_CLK_PHASE_INVERSE_Type clkPhaseInv; /*!< Inverse SPI clock phase */ - SPI_CLK_POLARITY_Type clkPolarity; /*!< SPI clock plarity */ - SPI_FrameSize_Type frameSize; /*!< SPI frame size(also the valid width for each fifo entry) */ -} SPI_CFG_Type; - -/** - * @brief SPI configuration type definition - */ -typedef struct -{ - uint8_t startLen; /*!< Length of start condition */ - uint8_t stopLen; /*!< Length of stop condition */ - uint8_t dataPhase0Len; /*!< Length of data phase 0,affecting clock */ - uint8_t dataPhase1Len; /*!< Length of data phase 1,affecting clock */ - uint8_t intervalLen; /*!< Length of interval between frame */ -} SPI_ClockCfg_Type; - -/** - * @brief SPI DMA configuration type definition - */ -typedef struct -{ - uint8_t txFifoThreshold; /*!< SPI tx FIFO threshold */ - uint8_t rxFifoThreshold; /*!< SPI rx FIFO threshold */ - BL_Fun_Type txFifoDmaEnable; /*!< Enable or disable tx dma req/ack interface */ - BL_Fun_Type rxFifoDmaEnable; /*!< Enable or disable rx dma req/ack interface */ -} SPI_FifoCfg_Type; - -/*@} end of group SPI_Public_Types */ - -/** @defgroup SPI_Public_Constants - * @{ - */ - -/** @defgroup SPI_ID_TYPE - * @{ - */ -#define IS_SPI_ID_TYPE(type) (((type) == SPI0_ID) || \ - ((type) == SPI0_MM_ID) || \ - ((type) == SPI_ID_MAX)) - -/** @defgroup SPI_SLAVE_PIN_TYPE - * @{ - */ -#define IS_SPI_SLAVE_PIN_TYPE(type) (((type) == SPI_SLAVE_PIN_4) || \ - ((type) == SPI_SLAVE_PIN_3)) - -/** @defgroup SPI_BYTE_INVERSE_TYPE - * @{ - */ -#define IS_SPI_BYTE_INVERSE_TYPE(type) (((type) == SPI_BYTE_INVERSE_BYTE0_FIRST) || \ - ((type) == SPI_BYTE_INVERSE_BYTE3_FIRST)) - -/** @defgroup SPI_BIT_INVERSE_TYPE - * @{ - */ -#define IS_SPI_BIT_INVERSE_TYPE(type) (((type) == SPI_BIT_INVERSE_MSB_FIRST) || \ - ((type) == SPI_BIT_INVERSE_LSB_FIRST)) - -/** @defgroup SPI_CLK_PHASE_INVERSE_TYPE - * @{ - */ -#define IS_SPI_CLK_PHASE_INVERSE_TYPE(type) (((type) == SPI_CLK_PHASE_INVERSE_0) || \ - ((type) == SPI_CLK_PHASE_INVERSE_1)) - -/** @defgroup SPI_CLK_POLARITY_TYPE - * @{ - */ -#define IS_SPI_CLK_POLARITY_TYPE(type) (((type) == SPI_CLK_POLARITY_LOW) || \ - ((type) == SPI_CLK_POLARITY_HIGH)) - -/** @defgroup SPI_FRAMESIZE_TYPE - * @{ - */ -#define IS_SPI_FRAMESIZE_TYPE(type) (((type) == SPI_FRAME_SIZE_8) || \ - ((type) == SPI_FRAME_SIZE_16) || \ - ((type) == SPI_FRAME_SIZE_24) || \ - ((type) == SPI_FRAME_SIZE_32)) - -/** @defgroup SPI_WORK_MODE_TYPE - * @{ - */ -#define IS_SPI_WORK_MODE_TYPE(type) (((type) == SPI_WORK_MODE_SLAVE) || \ - ((type) == SPI_WORK_MODE_MASTER)) - -/** @defgroup SPI_TIMEOUT_TYPE - * @{ - */ -#define IS_SPI_TIMEOUT_TYPE(type) (((type) == SPI_TIMEOUT_DISABLE) || \ - ((type) == SPI_TIMEOUT_ENABLE)) - -/** @defgroup SPI_FIFOSTATUS_TYPE - * @{ - */ -#define IS_SPI_FIFOSTATUS_TYPE(type) (((type) == SPI_FIFO_TX_OVERFLOW) || \ - ((type) == SPI_FIFO_TX_UNDERFLOW) || \ - ((type) == SPI_FIFO_RX_OVERFLOW) || \ - ((type) == SPI_FIFO_RX_UNDERFLOW)) - -/** @defgroup SPI_INT_TYPE - * @{ - */ -#define IS_SPI_INT_TYPE(type) (((type) == SPI_INT_END) || \ - ((type) == SPI_INT_TX_FIFO_REQ) || \ - ((type) == SPI_INT_RX_FIFO_REQ) || \ - ((type) == SPI_INT_SLAVE_TIMEOUT) || \ - ((type) == SPI_INT_SLAVE_UNDERRUN) || \ - ((type) == SPI_INT_FIFO_ERROR) || \ - ((type) == SPI_INT_ALL)) - -/*@} end of group SPI_Public_Constants */ - -/** @defgroup SPI_Public_Macros - * @{ - */ -#define SPI_RX_FIFO_SIZE 32 -#define SPI_TX_FIFO_SIZE 32 - -/*@} end of group SPI_Public_Macros */ - -/** @defgroup SPI_Public_Functions - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -void SPI0_IRQHandler(void); -void SPI1_IRQHandler(void); -#endif -BL_Err_Type SPI_Init(SPI_ID_Type spiNo, SPI_CFG_Type *spiCfg); -BL_Err_Type SPI_DeInit(SPI_ID_Type spiNo); -BL_Err_Type SPI_ClockConfig(SPI_ID_Type spiNo, SPI_ClockCfg_Type *clockCfg); -BL_Err_Type SPI_FifoConfig(SPI_ID_Type spiNo, SPI_FifoCfg_Type *fifoCfg); -BL_Err_Type SPI_Enable(SPI_ID_Type spiNo, SPI_WORK_MODE_Type modeType); -BL_Err_Type SPI_Disable(SPI_ID_Type spiNo, SPI_WORK_MODE_Type modeType); -BL_Err_Type SPI_SetFrameSize(SPI_ID_Type spiNo, SPI_FrameSize_Type frameSize); -BL_Err_Type SPI_SetTimeOutValue(SPI_ID_Type spiNo, uint16_t value); -BL_Err_Type SPI_SetDeglitchCount(SPI_ID_Type spiNo, uint8_t cnt); -BL_Err_Type SPI_RxIgnoreEnable(SPI_ID_Type spiNo, uint8_t startPoint, uint8_t stopPoint); -BL_Err_Type SPI_RxIgnoreDisable(SPI_ID_Type spiNo); -BL_Err_Type SPI_ClrTxFifo(SPI_ID_Type spiNo); -BL_Err_Type SPI_ClrRxFifo(SPI_ID_Type spiNo); -BL_Err_Type SPI_ClrIntStatus(SPI_ID_Type spiNo, SPI_INT_Type intType); -BL_Err_Type SPI_IntMask(SPI_ID_Type spiNo, SPI_INT_Type intType, BL_Mask_Type intMask); -BL_Err_Type SPI_Int_Callback_Install(SPI_ID_Type spiNo, SPI_INT_Type intType, intCallback_Type *cbFun); -BL_Err_Type SPI_SendData(SPI_ID_Type spiNo, void *buff, uint32_t length, SPI_Timeout_Type timeoutType); -BL_Err_Type SPI_ReceiveData(SPI_ID_Type spiNo, void *buff, uint32_t length, SPI_Timeout_Type timeoutType); -BL_Err_Type SPI_SendRecvData(SPI_ID_Type spiNo, void *sendBuff, void *recvBuff, uint32_t length, - SPI_Timeout_Type timeoutType); -uint8_t SPI_GetTxFifoCount(SPI_ID_Type spiNo); -uint8_t SPI_GetRxFifoCount(SPI_ID_Type spiNo); -BL_Sts_Type SPI_GetIntStatus(SPI_ID_Type spiNo, SPI_INT_Type intType); -BL_Sts_Type SPI_GetFifoStatus(SPI_ID_Type spiNo, SPI_FifoStatus_Type fifoSts); -BL_Sts_Type SPI_GetBusyStatus(SPI_ID_Type spiNo); -BL_Err_Type SPI_SetClock(SPI_ID_Type spiNo, uint32_t clk); -/*@} end of group SPI_Public_Functions */ - -/*@} end of group SPI */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_SPI_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_timer.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_timer.h deleted file mode 100644 index ac1c58efad..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_timer.h +++ /dev/null @@ -1,312 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_timer.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_TIMER_H__ -#define __BL808_TIMER_H__ - -#include "timer_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup TIMER - * @{ - */ - -/** @defgroup TIMER_Public_Types - * @{ - */ - -/** - * @brief TIMER port type definition - */ -typedef enum { - TIMER0_ID, /*!< TIMER0 port define */ - TIMER1_ID, /*!< TIMER1 port define */ - TIMER_ID_MAX, /*!< TIMER MAX ID define */ -} TIMER_ID_Type; - -/** - * @brief Watchdog timer port type definition - */ -typedef enum { - WDT0_ID, /*!< Watchdog0 port define */ - WDT1_ID, /*!< Watchdog1 port define */ - WDT_ID_MAX, /*!< Watchdog MAX ID define */ -} WDT_ID_Type; - -/** - * @brief TIMER channel type definition - */ -typedef enum { - TIMER_CH0, /*!< TIMER channel 0 port define */ - TIMER_CH1, /*!< TIMER channel 1 port define */ - TIMER_CH_MAX, /*!< */ -} TIMER_Chan_Type; - -/** - * @brief TIMER clock source type definition - */ -typedef enum { - TIMER_CLKSRC_FCLK, /*!< TIMER clock source :System CLK */ - TIMER_CLKSRC_32K, /*!< TIMER clock source :32K CLK */ - TIMER_CLKSRC_1K, /*!< TIMER clock source :1K CLK,Only for Timer not for Watchdog */ - TIMER_CLKSRC_XTAL, /*!< TIMER clock source :XTAL CLK */ - TIMER_CLKSRC_GPIO, /*!< TIMER clock source :GPIO */ - TIMER_CLKSRC_NO, /*!< TIMER clock source :No CLK */ -} TIMER_ClkSrc_Type; - -/** - * @brief TIMER match compare ID type definition - */ -typedef enum { - TIMER_COMP_ID_0, /*!< TIMER match compare ID 0 define */ - TIMER_COMP_ID_1, /*!< TIMER match compare ID 1 define */ - TIMER_COMP_ID_2, /*!< TIMER match compare ID 2 define */ -} TIMER_Comp_ID_Type; - -/** - * @brief TIMER preload source type definition - */ -typedef enum { - TIMER_PRELOAD_TRIG_NONE, /*!< TIMER no preload source, just free run */ - TIMER_PRELOAD_TRIG_COMP0, /*!< TIMER count register preload triggered by comparator 0 */ - TIMER_PRELOAD_TRIG_COMP1, /*!< TIMER count register preload triggered by comparator 1 */ - TIMER_PRELOAD_TRIG_COMP2, /*!< TIMER count register preload triggered by comparator 2 */ -} TIMER_PreLoad_Trig_Type; - -/** - * @brief TIMER count register run mode type definition - */ -typedef enum { - TIMER_COUNT_PRELOAD, /*!< TIMER count register preload from comparator register */ - TIMER_COUNT_FREERUN, /*!< TIMER count register free run */ -} TIMER_CountMode_Type; - -/** - * @brief TIMER gpio polarity type definition - */ -typedef enum { - TIMER_GPIO_POS, /*!< TIMER gpio plarity posedge */ - TIMER_GPIO_NEG, /*!< TIMER gpio plarity negedge */ -} TIMER_GPIO_Polarity_Type; - -/** - * @brief TIMER interrupt type definition - */ -typedef enum { - TIMER_INT_COMP_0, /*!< Comparator 0 match cause interrupt */ - TIMER_INT_COMP_1, /*!< Comparator 1 match cause interrupt */ - TIMER_INT_COMP_2, /*!< Comparator 2 match cause interrupt */ - TIMER_INT_ALL, /*!< */ -} TIMER_INT_Type; - -/** - * @brief Watchdog timer interrupt type definition - */ -typedef enum { - WDT_INT, /*!< Comparator 0 match cause interrupt */ - WDT_INT_ALL, /*!< */ -} WDT_INT_Type; - -/** - * @brief TIMER configuration structure type definition - */ -typedef struct -{ - TIMER_Chan_Type timerCh; /*!< Timer channel */ - TIMER_ClkSrc_Type clkSrc; /*!< Timer clock source */ - TIMER_PreLoad_Trig_Type plTrigSrc; /*!< Timer count register preload trigger source slelect */ - TIMER_CountMode_Type countMode; /*!< Timer count mode */ - uint8_t clockDivision; /*!< Timer clock divison value */ - uint32_t matchVal0; /*!< Timer match 0 value 0 */ - uint32_t matchVal1; /*!< Timer match 1 value 0 */ - uint32_t matchVal2; /*!< Timer match 2 value 0 */ - uint32_t preLoadVal; /*!< Timer preload value */ -} TIMER_CFG_Type; - -/*@} end of group TIMER_Public_Types */ - -/** @defgroup TIMER_Public_Constants - * @{ - */ - -/** @defgroup TIMER_ID_TYPE - * @{ - */ -#define IS_TIMER_ID_TYPE(type) (((type) == TIMER0_ID) || \ - ((type) == TIMER1_ID) || \ - ((type) == TIMER_ID_MAX)) - -/** @defgroup WDT_ID_TYPE - * @{ - */ -#define IS_WDT_ID_TYPE(type) (((type) == WDT0_ID) || \ - ((type) == WDT1_ID) || \ - ((type) == WDT_ID_MAX)) - -/** @defgroup TIMER_CHAN_TYPE - * @{ - */ -#define IS_TIMER_CHAN_TYPE(type) (((type) == TIMER_CH0) || \ - ((type) == TIMER_CH1) || \ - ((type) == TIMER_CH_MAX)) - -/** @defgroup TIMER_CLKSRC_TYPE - * @{ - */ -#define IS_TIMER_CLKSRC_TYPE(type) (((type) == TIMER_CLKSRC_FCLK) || \ - ((type) == TIMER_CLKSRC_32K) || \ - ((type) == TIMER_CLKSRC_1K) || \ - ((type) == TIMER_CLKSRC_XTAL) || \ - ((type) == TIMER_CLKSRC_GPIO) || \ - ((type) == TIMER_CLKSRC_NO)) - -/** @defgroup TIMER_COMP_ID_TYPE - * @{ - */ -#define IS_TIMER_COMP_ID_TYPE(type) (((type) == TIMER_COMP_ID_0) || \ - ((type) == TIMER_COMP_ID_1) || \ - ((type) == TIMER_COMP_ID_2)) - -/** @defgroup TIMER_PRELOAD_TRIG_TYPE - * @{ - */ -#define IS_TIMER_PRELOAD_TRIG_TYPE(type) (((type) == TIMER_PRELOAD_TRIG_NONE) || \ - ((type) == TIMER_PRELOAD_TRIG_COMP0) || \ - ((type) == TIMER_PRELOAD_TRIG_COMP1) || \ - ((type) == TIMER_PRELOAD_TRIG_COMP2)) - -/** @defgroup TIMER_COUNTMODE_TYPE - * @{ - */ -#define IS_TIMER_COUNTMODE_TYPE(type) (((type) == TIMER_COUNT_PRELOAD) || \ - ((type) == TIMER_COUNT_FREERUN)) - -/** @defgroup TIMER_GPIO_POLARITY_TYPE - * @{ - */ -#define IS_TIMER_GPIO_POLARITY_TYPE(type) (((type) == TIMER_GPIO_POS) || \ - ((type) == TIMER_GPIO_NEG)) - -/** @defgroup TIMER_INT_TYPE - * @{ - */ -#define IS_TIMER_INT_TYPE(type) (((type) == TIMER_INT_COMP_0) || \ - ((type) == TIMER_INT_COMP_1) || \ - ((type) == TIMER_INT_COMP_2) || \ - ((type) == TIMER_INT_ALL)) - -/** @defgroup WDT_INT_TYPE - * @{ - */ -#define IS_WDT_INT_TYPE(type) (((type) == WDT_INT) || \ - ((type) == WDT_INT_ALL)) - -/*@} end of group TIMER_Public_Constants */ - -/** @defgroup TIMER_Public_Macros - * @{ - */ -#define WDT_ENABLE_ACCESS(baseAddr) \ - { \ - BL_WR_REG(baseAddr, TIMER_WFAR, BL_SET_REG_BITS_VAL(BL_RD_REG(baseAddr, TIMER_WFAR), TIMER_WFAR, 0xBABA)); \ - BL_WR_REG(baseAddr, TIMER_WSAR, BL_SET_REG_BITS_VAL(BL_RD_REG(baseAddr, TIMER_WSAR), TIMER_WSAR, 0xEB10)); \ - } - -/*@} end of group TIMER_Public_Macros */ - -/** @defgroup TIMER_Public_Functions - * @{ - */ - -/** - * @brief UART Functions - */ -#ifndef BFLB_USE_HAL_DRIVER -void TIMER0_CH0_IRQHandler(void); -void TIMER0_CH1_IRQHandler(void); -void TIMER0_WDT_IRQHandler(void); -void TIMER1_CH0_IRQHandler(void); -void TIMER1_CH1_IRQHandler(void); -void TIMER1_WDT_IRQHandler(void); -#endif -BL_Err_Type TIMER_Init(TIMER_ID_Type timerId, TIMER_CFG_Type *timerCfg); -BL_Err_Type TIMER_DeInit(TIMER_ID_Type timerId); -uint32_t TIMER_GetCompValue(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo); -void TIMER_SetCompValue(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo, uint32_t val); -void TIMER_CompValueEffectImmediately(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, BL_Fun_Type enable); -uint32_t TIMER_GetCounterValue(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh); -void TIMER_ResetCounterValue(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh); -BL_Sts_Type TIMER_GetMatchStatus(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo); -uint32_t TIMER_GetPreloadValue(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh); -void TIMER_SetPreloadValue(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, uint32_t val); -void TIMER_SetPreloadSrc(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_PreLoad_Trig_Type plSrc); -void TIMER_SetCountMode(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_CountMode_Type countMode); -void TIMER_ClearIntStatus(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo); -void TIMER_Enable(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh); -void TIMER_Disable(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh); -void TIMER_IntMask(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_INT_Type intType, BL_Mask_Type intMask); -void TIMER_GPIOSetPolarity(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_GPIO_Polarity_Type polarity); -void TIMER_CH0_SetMeasurePulseWidth(TIMER_ID_Type timerId, BL_Fun_Type enable); -uint32_t TIMER_CH0_GetMeasurePulseWidth(TIMER_ID_Type timerId); -void TIMER_ForceClockDivision(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh); -void TIMER_SetPreloadTrigSrc(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_PreLoad_Trig_Type plSrc); -void TIMER_Int_Callback_Install(TIMER_ID_Type timerId, TIMER_Chan_Type timerChan, TIMER_INT_Type intType, intCallback_Type *cbFun); - -void WDT_Set_Clock(WDT_ID_Type wdtId, TIMER_ClkSrc_Type clkSrc, uint8_t div); -uint16_t WDT_GetMatchValue(WDT_ID_Type wdtId); -void WDT_SetCompValue(WDT_ID_Type wdtId, uint16_t val); -void WDT_CompValueEffectImmediately(WDT_ID_Type wdtId, BL_Fun_Type enable); -uint16_t WDT_GetCounterValue(WDT_ID_Type wdtId); -void WDT_ResetCounterValue(WDT_ID_Type wdtId); -BL_Sts_Type WDT_GetResetStatus(WDT_ID_Type wdtId); -void WDT_ClearResetStatus(WDT_ID_Type wdtId); -void WDT_Enable(WDT_ID_Type wdtId); -void WDT_Disable(WDT_ID_Type wdtId); -void WDT_IntMask(WDT_ID_Type wdtId, WDT_INT_Type intType, BL_Mask_Type intMask); -void WDT_ForceClockDivision(WDT_ID_Type wdtId); -void WDT_Int_Callback_Install(WDT_ID_Type wdtId, WDT_INT_Type wdtInt, intCallback_Type *cbFun); -void WDT_GPIOSetPolarity(WDT_ID_Type wdtId, TIMER_GPIO_Polarity_Type polarity); - -/*@} end of group TIMER_Public_Functions */ - -/*@} end of group TIMER */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_TIMER_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_touch.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_touch.h deleted file mode 100644 index 3768b9298e..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_touch.h +++ /dev/null @@ -1,480 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_touch.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_TOUCH_H__ -#define __BL808_TOUCH_H__ - -#include "pds_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup TOUCH - * @{ - */ - -/** @defgroup TOUCH_Public_Types - * @{ - */ - -/** - * @brief TOUCH ID type definition - */ -typedef enum { - TOUCH_ID_0, /*!< TOUCH ID 0 */ -} TOUCH_ID_Type; - -/** - * @brief TOUCH run mode select type definition - */ -typedef enum { - TOUCH_RUN_MODE_SINGLE_SHOT, /*!< TOUCH run in single shot mode */ - TOUCH_RUN_MODE_CONTINUE, /*!< TOUCH run in continue mode */ -} TOUCH_RUN_MODE_Type; - -/** - * @brief TOUCH pcharge low type definition - */ -typedef enum { - TOUCH_PCHARGE_LOW_127, /*!< for one channel, the max external cap leakage cycle is 127 */ - TOUCH_PCHARGE_LOW_255, /*!< for one channel, the max external cap leakage cycle is 255 */ - TOUCH_PCHARGE_LOW_511, /*!< for one channel, the max external cap leakage cycle is 511 */ - TOUCH_PCHARGE_LOW_1023, /*!< for one channel, the max external cap leakage cycle is 1023 */ - TOUCH_PCHARGE_LOW_2047, /*!< for one channel, the max external cap leakage cycle is 2047 */ - TOUCH_PCHARGE_LOW_4095, /*!< for one channel, the max external cap leakage cycle is 4095 */ -} TOUCH_PCHARGE_LOW_Type; - -/** - * @brief TOUCH pcharge high type definition - */ -typedef enum { - TOUCH_PCHARGE_HIGH_511, /*!< for one channel, the max external cap charge-transfer cycle is 511 */ - TOUCH_PCHARGE_HIGH_1023, /*!< for one channel, the max external cap charge-transfer cycle is 1023 */ - TOUCH_PCHARGE_HIGH_2047, /*!< for one channel, the max external cap charge-transfer cycle is 2047 */ - TOUCH_PCHARGE_HIGH_4095, /*!< for one channel, the max external cap charge-transfer cycle is 4095 */ - TOUCH_PCHARGE_HIGH_8191, /*!< for one channel, the max external cap charge-transfer cycle is 8191 */ - TOUCH_PCHARGE_HIGH_16383, /*!< for one channel, the max external cap charge-transfer cycle is 16383 */ - TOUCH_PCHARGE_HIGH_32767, /*!< for one channel, the max external cap charge-transfer cycle is 32767 */ - TOUCH_PCHARGE_HIGH_65535, /*!< for one channel, the max external cap charge-transfer cycle is 65535 */ -} TOUCH_PCHARGE_HIGH_Type; - -/** - * @brief TOUCH clock divider type definition - */ -typedef enum { - TOUCH_CLK_DIV_1, /*!< TOUCH clock div 1 */ - TOUCH_CLK_DIV_2, /*!< TOUCH clock div 2 */ - TOUCH_CLK_DIV_4, /*!< TOUCH clock div 4 */ - TOUCH_CLK_DIV_8, /*!< TOUCH clock div 8 */ - TOUCH_CLK_DIV_16, /*!< TOUCH clock div 16 */ - TOUCH_CLK_DIV_32, /*!< TOUCH clock div 32 */ - TOUCH_CLK_DIV_64, /*!< TOUCH clock div 64 */ - TOUCH_CLK_DIV_128, /*!< TOUCH clock div 128 */ -} TOUCH_CLK_DIV_Type; - -/** - * @brief TOUCH clock source select type definition - */ -typedef enum { - TOUCH_CLK_SEL_32K, /*!< select 32K as TOUCH clock */ - TOUCH_CLK_SEL_32M, /*!< select 32M as TOUCH clock */ -} TOUCH_CLK_SEL_Type; - -/** - * @brief TOUCH current source select type definition - */ -typedef enum { - TOUCH_POWER_SEL_AON, /*!< select touch current from AON bandgap,power up touch current in rf707_aon */ - TOUCH_POWER_SEL_INTERNAL_BG, /*!< select touch current from internal bandgap,power off touch current in rf707_aon */ -} TOUCH_POWER_SEL_Type; - -/** - * @brief TOUCH comparator hystersis voltage type definition - */ -typedef enum { - TOUCH_HYSTERSIS_VOLTAGE_30mV, /*!< set 30mV comparator hystersis voltage */ - TOUCH_HYSTERSIS_VOLTAGE_80mV, /*!< set 80mV comparator hystersis voltage */ -} TOUCH_HYSTERSIS_VOLTAGE_Type; - -/** - * @brief TOUCH LDO voltage control type definition - */ -typedef enum { - TOUCH_LDO_VOLTAGE_0P6V, /*!< LDO output 0.6V */ - TOUCH_LDO_VOLTAGE_0P8V, /*!< LDO output 0.8V */ - TOUCH_LDO_VOLTAGE_1P0V, /*!< LDO output 1.0V */ - TOUCH_LDO_VOLTAGE_1P2V, /*!< LDO output 1.2V */ - TOUCH_LDO_VOLTAGE_1P4V, /*!< LDO output 1.4V */ - TOUCH_LDO_VOLTAGE_1P6V, /*!< LDO output 1.6V */ - TOUCH_LDO_VOLTAGE_1P8V, /*!< LDO output 1.8V */ - TOUCH_LDO_VOLTAGE_2P0V, /*!< LDO output 2.0V */ -} TOUCH_LDO_VOLTAGE_Type; - -/** - * @brief TOUCH reference voltage control type definition - */ -typedef enum { - TOUCH_VREF_VOLTAGE_0P4V, /*!< LDO output 0.4V */ - TOUCH_VREF_VOLTAGE_0P6V, /*!< LDO output 0.6V */ - TOUCH_VREF_VOLTAGE_0P8V, /*!< LDO output 0.8V */ - TOUCH_VREF_VOLTAGE_1P0V, /*!< LDO output 1.0V */ - TOUCH_VREF_VOLTAGE_1P2V, /*!< LDO output 1.2V */ - TOUCH_VREF_VOLTAGE_1P4V, /*!< LDO output 1.4V */ - TOUCH_VREF_VOLTAGE_1P6V, /*!< LDO output 1.6V */ - TOUCH_VREF_VOLTAGE_1P8V, /*!< LDO output 1.8V */ -} TOUCH_VREF_VOLTAGE_Type; - -/** - * @brief TOUCH compensation cap control type definition - */ -typedef enum { - TOUCH_COMPENSATION_CAP_12pF, /*!< compensation cap is 12pF */ - TOUCH_COMPENSATION_CAP_13pF, /*!< compensation cap is 13pF */ - TOUCH_COMPENSATION_CAP_14pF, /*!< compensation cap is 14pF */ - TOUCH_COMPENSATION_CAP_15pF, /*!< compensation cap is 15pF */ -} TOUCH_COMPENSATION_CAP_Type; - -/** - * @brief TOUCH mode select type definition - */ -typedef enum { - TOUCH_WORK_MODE_SELF_CAP, /*!< self cap mode,each channel detection result can judge if this channel is touched */ - TOUCH_WORK_MODE_MUTUAL, /*!< mutual mode,channel 6~0 works,higher 3 channel-->column,lower 4 channel-->row */ -} TOUCH_WORK_MODE_Type; - -/** - * @brief TOUCH filter long time average order control,FLT(new)=(data_raw+FLT(former)*(2^N-1))/2^N - */ -typedef enum { - TOUCH_FILTER_ORDER_CTRL_0, /*!< N=0 (acted like disable actually) */ - TOUCH_FILTER_ORDER_CTRL_1, /*!< N=1 */ - TOUCH_FILTER_ORDER_CTRL_2, /*!< N=2 */ - TOUCH_FILTER_ORDER_CTRL_3, /*!< N=3 */ - TOUCH_FILTER_ORDER_CTRL_4, /*!< N=4 */ - TOUCH_FILTER_ORDER_CTRL_5, /*!< N=5 */ - TOUCH_FILTER_ORDER_CTRL_6, /*!< N=6 */ - TOUCH_FILTER_ORDER_CTRL_7, /*!< N=7 */ -} TOUCH_FILTER_ORDER_CTRL_Type; - -/** - * @brief TOUCH LTA long time average order control,LTA(new)=(data_raw+LTA(former)*(2^N-1))/2^N - */ -typedef enum { - TOUCH_LTA_ORDER_CTRL_0, /*!< N=0 (acted like disable actually) */ - TOUCH_LTA_ORDER_CTRL_1, /*!< N=1 */ - TOUCH_LTA_ORDER_CTRL_2, /*!< N=2 */ - TOUCH_LTA_ORDER_CTRL_3, /*!< N=3 */ - TOUCH_LTA_ORDER_CTRL_4, /*!< N=4 */ - TOUCH_LTA_ORDER_CTRL_5, /*!< N=5 */ - TOUCH_LTA_ORDER_CTRL_6, /*!< N=6 */ - TOUCH_LTA_ORDER_CTRL_7, /*!< N=7 */ -} TOUCH_LTA_ORDER_CTRL_Type; - -/** - * @brief TOUCH configuration type definition - */ -typedef struct -{ - TOUCH_CLK_SEL_Type clkSel; /*!< TOUCH clock source select */ - TOUCH_CLK_DIV_Type clkDiv; /*!< TOUCH clock divider */ - TOUCH_POWER_SEL_Type powerSel; /*!< TOUCH power source select */ - BL_Fun_Type calibrationEn; /*!< touch_channel calibration option, when enable,the counting number will be set as LTA data */ - TOUCH_WORK_MODE_Type workMode; /*!< touch_channel work mode select */ - TOUCH_RUN_MODE_Type runMode; /*!< 0-->single shot mode, 1-->continous mode */ - BL_Fun_Type ulpEn; /*!< ultra low power mode enable */ - BL_Fun_Type cycleEn; /*!< configure for low power mode with single shot, sleep for a time and then turn on */ - uint32_t sleepTime; /*!< Sleep clock_ana cycle, can save power by reduce turn on time */ - TOUCH_PCHARGE_LOW_Type pchargeLow; /*!< the max external cap leakage cycle */ - TOUCH_PCHARGE_HIGH_Type pchargeHigh; /*!< the max external cap charge-transfer cycle */ - TOUCH_LDO_VOLTAGE_Type ldoVol; /*!< TOUCH LDO voltage */ - TOUCH_VREF_VOLTAGE_Type vrefVol; /*!< TOUCH reference voltage control */ - TOUCH_HYSTERSIS_VOLTAGE_Type hystersisVol; /*!< TOUCH comparator hystersis voltage */ - TOUCH_COMPENSATION_CAP_Type compensationCap; /*!< TOUCH compensation cap control */ - BL_Fun_Type filterEn; /*!< touch_channel output data filter control, will do average(low pass filter) when enable */ - TOUCH_FILTER_ORDER_CTRL_Type filterCtrl; /*!< TOUCH filter long time average order control */ - BL_Fun_Type ltaEn; /*!< touch_channel long time average control, will do average(low pass filter) when enable */ - TOUCH_LTA_ORDER_CTRL_Type ltaCtrl; /*!< TOUCH LTA long time average order control */ - BL_Fun_Type dataHystersisEn; /*!< touch_channel hystersis data for touch action judgement, can reduce the false trigger */ - uint16_t dataHysCtrl; /*!< Hystersis data for data and dectection judgement */ -} TOUCH_CFG_Type; - -/** - * @brief TOUCH channel type definition - */ -typedef enum { - TOUCH_CHANNEL_0, /*!< TOUCH channel 0 */ - TOUCH_CHANNEL_1, /*!< TOUCH channel 1 */ - TOUCH_CHANNEL_2, /*!< TOUCH channel 2 */ - TOUCH_CHANNEL_3, /*!< TOUCH channel 3 */ - TOUCH_CHANNEL_4, /*!< TOUCH channel 4 */ - TOUCH_CHANNEL_5, /*!< TOUCH channel 5 */ - TOUCH_CHANNEL_6, /*!< TOUCH channel 6 */ - TOUCH_CHANNEL_7, /*!< TOUCH channel 7 */ - TOUCH_CHANNEL_8, /*!< TOUCH channel 8 */ - TOUCH_CHANNEL_9, /*!< TOUCH channel 9 */ - TOUCH_CHANNEL_10, /*!< TOUCH channel 10 */ - TOUCH_CHANNEL_11, /*!< TOUCH channel 11 */ -} TOUCH_CHANNEL_Type; - -/** - * @brief TOUCH channel config type definition - */ -typedef enum { - TOUCH_CHANNEL_HIGHZ_CFG_GND, /*!< channel tie to ground */ - TOUCH_CHANNEL_HIGHZ_CFG_HIGHZ, /*!< channel HighZ output */ -} TOUCH_CHANNEL_HIGHZ_CFG_Type; - -/** - * @brief TOUCH channel configuration type definition - */ -typedef struct -{ - TOUCH_CHANNEL_HIGHZ_CFG_Type ch0; /*!< TOUCH channel 0 HighZ config */ - TOUCH_CHANNEL_HIGHZ_CFG_Type ch1; /*!< TOUCH channel 1 HighZ config */ - TOUCH_CHANNEL_HIGHZ_CFG_Type ch2; /*!< TOUCH channel 2 HighZ config */ - TOUCH_CHANNEL_HIGHZ_CFG_Type ch3; /*!< TOUCH channel 3 HighZ config */ - TOUCH_CHANNEL_HIGHZ_CFG_Type ch4; /*!< TOUCH channel 4 HighZ config */ - TOUCH_CHANNEL_HIGHZ_CFG_Type ch5; /*!< TOUCH channel 5 HighZ config */ - TOUCH_CHANNEL_HIGHZ_CFG_Type ch6; /*!< TOUCH channel 6 HighZ config */ - TOUCH_CHANNEL_HIGHZ_CFG_Type ch7; /*!< TOUCH channel 7 HighZ config */ - TOUCH_CHANNEL_HIGHZ_CFG_Type ch8; /*!< TOUCH channel 8 HighZ config */ - TOUCH_CHANNEL_HIGHZ_CFG_Type ch9; /*!< TOUCH channel 9 HighZ config */ - TOUCH_CHANNEL_HIGHZ_CFG_Type ch10; /*!< TOUCH channel 10 HighZ config */ - TOUCH_CHANNEL_HIGHZ_CFG_Type ch11; /*!< TOUCH channel 11 HighZ config */ -} TOUCH_CHANNEL_CFG_Type; - -/** - * @brief TOUCH interrupt type definition - */ -typedef enum { - TOUCH_INT_INTERRUPT, /*!< TOUCH has only one interrupt */ -} TOUCH_INT_Type; - -/*@} end of group TOUCH_Public_Types */ - -/** @defgroup TOUCH_Public_Constants - * @{ - */ - -/** @defgroup TOUCH_ID_TYPE - * @{ - */ -#define IS_TOUCH_ID_TYPE(type) (((type) == TOUCH_ID_0)) - -/** @defgroup TOUCH_RUN_MODE_TYPE - * @{ - */ -#define IS_TOUCH_RUN_MODE_TYPE(type) (((type) == TOUCH_RUN_MODE_SINGLE_SHOT) || \ - ((type) == TOUCH_RUN_MODE_CONTINUE)) - -/** @defgroup TOUCH_PCHARGE_LOW_TYPE - * @{ - */ -#define IS_TOUCH_PCHARGE_LOW_TYPE(type) (((type) == TOUCH_PCHARGE_LOW_127) || \ - ((type) == TOUCH_PCHARGE_LOW_255) || \ - ((type) == TOUCH_PCHARGE_LOW_511) || \ - ((type) == TOUCH_PCHARGE_LOW_1023) || \ - ((type) == TOUCH_PCHARGE_LOW_2047) || \ - ((type) == TOUCH_PCHARGE_LOW_4095)) - -/** @defgroup TOUCH_PCHARGE_HIGH_TYPE - * @{ - */ -#define IS_TOUCH_PCHARGE_HIGH_TYPE(type) (((type) == TOUCH_PCHARGE_HIGH_511) || \ - ((type) == TOUCH_PCHARGE_HIGH_1023) || \ - ((type) == TOUCH_PCHARGE_HIGH_2047) || \ - ((type) == TOUCH_PCHARGE_HIGH_4095) || \ - ((type) == TOUCH_PCHARGE_HIGH_8191) || \ - ((type) == TOUCH_PCHARGE_HIGH_16383) || \ - ((type) == TOUCH_PCHARGE_HIGH_32767) || \ - ((type) == TOUCH_PCHARGE_HIGH_65535)) - -/** @defgroup TOUCH_CLK_DIV_TYPE - * @{ - */ -#define IS_TOUCH_CLK_DIV_TYPE(type) (((type) == TOUCH_CLK_DIV_1) || \ - ((type) == TOUCH_CLK_DIV_2) || \ - ((type) == TOUCH_CLK_DIV_4) || \ - ((type) == TOUCH_CLK_DIV_8) || \ - ((type) == TOUCH_CLK_DIV_16) || \ - ((type) == TOUCH_CLK_DIV_32) || \ - ((type) == TOUCH_CLK_DIV_64) || \ - ((type) == TOUCH_CLK_DIV_128)) - -/** @defgroup TOUCH_CLK_SEL_TYPE - * @{ - */ -#define IS_TOUCH_CLK_SEL_TYPE(type) (((type) == TOUCH_CLK_SEL_32K) || \ - ((type) == TOUCH_CLK_SEL_32M)) - -/** @defgroup TOUCH_POWER_SEL_TYPE - * @{ - */ -#define IS_TOUCH_POWER_SEL_TYPE(type) (((type) == TOUCH_POWER_SEL_AON) || \ - ((type) == TOUCH_POWER_SEL_INTERNAL_BG)) - -/** @defgroup TOUCH_HYSTERSIS_VOLTAGE_TYPE - * @{ - */ -#define IS_TOUCH_HYSTERSIS_VOLTAGE_TYPE(type) (((type) == TOUCH_HYSTERSIS_VOLTAGE_30mV) || \ - ((type) == TOUCH_HYSTERSIS_VOLTAGE_80mV)) - -/** @defgroup TOUCH_LDO_VOLTAGE_TYPE - * @{ - */ -#define IS_TOUCH_LDO_VOLTAGE_TYPE(type) (((type) == TOUCH_LDO_VOLTAGE_0P6V) || \ - ((type) == TOUCH_LDO_VOLTAGE_0P8V) || \ - ((type) == TOUCH_LDO_VOLTAGE_1P0V) || \ - ((type) == TOUCH_LDO_VOLTAGE_1P2V) || \ - ((type) == TOUCH_LDO_VOLTAGE_1P4V) || \ - ((type) == TOUCH_LDO_VOLTAGE_1P6V) || \ - ((type) == TOUCH_LDO_VOLTAGE_1P8V) || \ - ((type) == TOUCH_LDO_VOLTAGE_2P0V)) - -/** @defgroup TOUCH_VREF_VOLTAGE_TYPE - * @{ - */ -#define IS_TOUCH_VREF_VOLTAGE_TYPE(type) (((type) == TOUCH_VREF_VOLTAGE_0P4V) || \ - ((type) == TOUCH_VREF_VOLTAGE_0P6V) || \ - ((type) == TOUCH_VREF_VOLTAGE_0P8V) || \ - ((type) == TOUCH_VREF_VOLTAGE_1P0V) || \ - ((type) == TOUCH_VREF_VOLTAGE_1P2V) || \ - ((type) == TOUCH_VREF_VOLTAGE_1P4V) || \ - ((type) == TOUCH_VREF_VOLTAGE_1P6V) || \ - ((type) == TOUCH_VREF_VOLTAGE_1P8V)) - -/** @defgroup TOUCH_COMPENSATION_CAP_TYPE - * @{ - */ -#define IS_TOUCH_COMPENSATION_CAP_TYPE(type) (((type) == TOUCH_COMPENSATION_CAP_12pF) || \ - ((type) == TOUCH_COMPENSATION_CAP_13pF) || \ - ((type) == TOUCH_COMPENSATION_CAP_14pF) || \ - ((type) == TOUCH_COMPENSATION_CAP_15pF)) - -/** @defgroup TOUCH_WORK_MODE_TYPE - * @{ - */ -#define IS_TOUCH_WORK_MODE_TYPE(type) (((type) == TOUCH_WORK_MODE_SELF_CAP) || \ - ((type) == TOUCH_WORK_MODE_MUTUAL)) - -/** @defgroup TOUCH_FILTER_ORDER_CTRL_TYPE - * @{ - */ -#define IS_TOUCH_FILTER_ORDER_CTRL_TYPE(type) (((type) == TOUCH_FILTER_ORDER_CTRL_0) || \ - ((type) == TOUCH_FILTER_ORDER_CTRL_1) || \ - ((type) == TOUCH_FILTER_ORDER_CTRL_2) || \ - ((type) == TOUCH_FILTER_ORDER_CTRL_3) || \ - ((type) == TOUCH_FILTER_ORDER_CTRL_4) || \ - ((type) == TOUCH_FILTER_ORDER_CTRL_5) || \ - ((type) == TOUCH_FILTER_ORDER_CTRL_6) || \ - ((type) == TOUCH_FILTER_ORDER_CTRL_7)) - -/** @defgroup TOUCH_LTA_ORDER_CTRL_TYPE - * @{ - */ -#define IS_TOUCH_LTA_ORDER_CTRL_TYPE(type) (((type) == TOUCH_LTA_ORDER_CTRL_0) || \ - ((type) == TOUCH_LTA_ORDER_CTRL_1) || \ - ((type) == TOUCH_LTA_ORDER_CTRL_2) || \ - ((type) == TOUCH_LTA_ORDER_CTRL_3) || \ - ((type) == TOUCH_LTA_ORDER_CTRL_4) || \ - ((type) == TOUCH_LTA_ORDER_CTRL_5) || \ - ((type) == TOUCH_LTA_ORDER_CTRL_6) || \ - ((type) == TOUCH_LTA_ORDER_CTRL_7)) - -/** @defgroup TOUCH_CHANNEL_TYPE - * @{ - */ -#define IS_TOUCH_CHANNEL_TYPE(type) (((type) == TOUCH_CHANNEL_0) || \ - ((type) == TOUCH_CHANNEL_1) || \ - ((type) == TOUCH_CHANNEL_2) || \ - ((type) == TOUCH_CHANNEL_3) || \ - ((type) == TOUCH_CHANNEL_4) || \ - ((type) == TOUCH_CHANNEL_5) || \ - ((type) == TOUCH_CHANNEL_6) || \ - ((type) == TOUCH_CHANNEL_7) || \ - ((type) == TOUCH_CHANNEL_8) || \ - ((type) == TOUCH_CHANNEL_9) || \ - ((type) == TOUCH_CHANNEL_10) || \ - ((type) == TOUCH_CHANNEL_11)) - -/** @defgroup TOUCH_CHANNEL_HIGHZ_CFG_TYPE - * @{ - */ -#define IS_TOUCH_CHANNEL_HIGHZ_CFG_TYPE(type) (((type) == TOUCH_CHANNEL_HIGHZ_CFG_GND) || \ - ((type) == TOUCH_CHANNEL_HIGHZ_CFG_HIGHZ)) - -/** @defgroup TOUCH_INT_TYPE - * @{ - */ -#define IS_TOUCH_INT_TYPE(type) (((type) == TOUCH_INT_INTERRUPT)) - -/*@} end of group TOUCH_Public_Constants */ - -/** @defgroup TOUCH_Public_Macros - * @{ - */ - -/*@} end of group TOUCH_Public_Macros */ - -/** @defgroup TOUCH_Public_Functions - * @{ - */ -BL_Err_Type TOUCH_Init(TOUCH_ID_Type touchId, TOUCH_CFG_Type *tCfg); -BL_Err_Type TOUCH_CHANNEL_Init(TOUCH_ID_Type touchId, TOUCH_CHANNEL_CFG_Type *tChCfg, TOUCH_CHANNEL_Type tChSel); -BL_Err_Type TOUCH_Enable(TOUCH_ID_Type touchId); -BL_Err_Type TOUCH_Disable(TOUCH_ID_Type touchId); -BL_Err_Type TOUCH_SetVthData(TOUCH_ID_Type touchId, TOUCH_CHANNEL_Type tCh, uint8_t value); -uint32_t TOUCH_GetVthData(TOUCH_ID_Type touchId, TOUCH_CHANNEL_Type tCh); -uint32_t TOUCH_GetRawData(TOUCH_ID_Type touchId, TOUCH_CHANNEL_Type tCh); -uint32_t TOUCH_GetLtaData(TOUCH_ID_Type touchId, TOUCH_CHANNEL_Type tCh); -uint32_t TOUCH_GetFltData(TOUCH_ID_Type touchId, TOUCH_CHANNEL_Type tCh); -BL_Sts_Type TOUCH_GetEndStatus(TOUCH_ID_Type touchId); -BL_Err_Type TOUCH_IntEnable(TOUCH_ID_Type touchId, TOUCH_INT_Type intType); -BL_Err_Type TOUCH_IntDisable(TOUCH_ID_Type touchId, TOUCH_INT_Type intType); -BL_Err_Type TOUCH_IntMask(TOUCH_ID_Type touchId, TOUCH_INT_Type intType, TOUCH_CHANNEL_Type tCh, BL_Mask_Type intMask); -BL_Sts_Type TOUCH_GetIntStatus(TOUCH_ID_Type touchId, TOUCH_INT_Type intType, TOUCH_CHANNEL_Type tCh); -BL_Err_Type TOUCH_ClrIntStatus(TOUCH_ID_Type touchId, TOUCH_INT_Type intType, TOUCH_CHANNEL_Type tCh); -BL_Err_Type TOUCH_INT_Callback_Install(TOUCH_ID_Type touchId, TOUCH_INT_Type intType, TOUCH_CHANNEL_Type tCh, - intCallback_Type *cbFun); - -/*@} end of group TOUCH_Public_Functions */ - -/*@} end of group TOUCH */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_TOUCH_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_uart.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_uart.h deleted file mode 100644 index 1dd38360d3..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_uart.h +++ /dev/null @@ -1,359 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_uart.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_UART_H__ -#define __BL808_UART_H__ - -#include "uart_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup UART - * @{ - */ - -/** @defgroup UART_Public_Types - * @{ - */ - -/** - * @brief UART port type definition - */ -typedef enum { - UART0_ID, /*!< UART0 port define */ - UART1_ID, /*!< UART1 port define */ - UART2_ID, /*!< UART2 port define */ - UART0_MM_ID, /*!< MM system UART0 port define */ - UART_ID_MAX, /*!< UART MAX ID define */ -} UART_ID_Type; - -/** - * @brief UART direction type definition - */ -typedef enum { - UART_TX, /*!< UART TX Direction */ - UART_RX, /*!< UART RX Direction */ - UART_TXRX, /*!< UART TX and RX Direction */ -} UART_Direction_Type; - -/** - * @brief UART parity type definition - */ -typedef enum { - UART_PARITY_NONE, /*!< UART parity none define */ - UART_PARITY_ODD, /*!< UART parity odd define */ - UART_PARITY_EVEN, /*!< UART parity even define */ -} UART_Parity_Type; - -/** - * @brief UART data bits type definiton - */ -typedef enum { - UART_DATABITS_5, /*!< UART data bits length:5 bits */ - UART_DATABITS_6, /*!< UART data bits length:6 bits */ - UART_DATABITS_7, /*!< UART data bits length:7 bits */ - UART_DATABITS_8, /*!< UART data bits length:8 bits */ -} UART_DataBits_Type; - -/** - * @brief UART stop bits type definiton - */ -typedef enum { - UART_STOPBITS_0_5, /*!< UART data stop bits length:0.5 bits */ - UART_STOPBITS_1, /*!< UART data stop bits length:1 bits */ - UART_STOPBITS_1_5, /*!< UART data stop bits length:1.5 bits */ - UART_STOPBITS_2, /*!< UART data stop bits length:2 bits */ -} UART_StopBits_Type; - -/** - * @brief UART each data byte is send out LSB-first or MSB-first type definiton - */ -typedef enum { - UART_LSB_FIRST, /*!< UART each byte is send out LSB-first */ - UART_MSB_FIRST, /*!< UART each byte is send out MSB-first */ -} UART_ByteBitInverse_Type; - -/** - * @brief UART auto baudrate detection using codeword 0x55 or start bit definiton - */ -typedef enum { - UART_AUTOBAUD_0X55, /*!< UART auto baudrate detection using codeword 0x55 */ - UART_AUTOBAUD_STARTBIT, /*!< UART auto baudrate detection using start bit */ -} UART_AutoBaudDetection_Type; - -/** - * @brief UART RS-485 mode DE pin polarity definiton - */ -typedef enum { - UART_RS485_DE_ACTIVE_LOW, /*!< UART DE is active-low */ - UART_RS485_DE_ACTIVE_HIGH, /*!< UART DE is active-high */ -} UART_RS485Polarity_Type; - -/** - * @brief UART interrupt type definition - */ -typedef enum { - UART_INT_TX_END, /*!< UART tx transfer end interrupt */ - UART_INT_RX_END, /*!< UART rx transfer end interrupt */ - UART_INT_TX_FIFO_REQ, /*!< UART tx fifo interrupt when tx fifo count reaches,auto clear */ - UART_INT_RX_FIFO_REQ, /*!< UART rx fifo interrupt when rx fifo count reaches,auto clear */ - UART_INT_RTO, /*!< UART rx time-out interrupt */ - UART_INT_PCE, /*!< UART rx parity check error interrupt */ - UART_INT_TX_FER, /*!< UART tx fifo overflow/underflow error interrupt */ - UART_INT_RX_FER, /*!< UART rx fifo overflow/underflow error interrupt */ - UART_INT_LSE, /*!< UART rx lin mode sync field error interrupt */ - UART_INT_BCR, /*!< UART rx byte count reached interrupt */ - UART_INT_STARTBIT, /*!< UART rx auto baudrate detection finish interrupt using start bit */ - UART_INT_0X55, /*!< UART rx auto baudrate detection finish interrupt using codeword 0x55 */ - UART_INT_ALL, /*!< All the interrupt */ -} UART_INT_Type; - -/** - * @brief UART overflow or underflow type definition - */ -typedef enum { - UART_TX_OVERFLOW, /*!< UART tx fifo overflow */ - UART_TX_UNDERFLOW, /*!< UART tx fifo underflow */ - UART_RX_OVERFLOW, /*!< UART rx fifo overflow */ - UART_RX_UNDERFLOW, /*!< UART rx fifo underflow */ -} UART_Overflow_Type; - -/** - * @brief UART configuration structure type definition - */ -typedef struct -{ - uint32_t uartClk; /*!< Uart module clock */ - uint32_t baudRate; /*!< Uart baudrate */ - UART_DataBits_Type dataBits; /*!< Uart frame length of data bit */ - UART_StopBits_Type stopBits; /*!< Uart frame length of stop bit */ - UART_Parity_Type parity; /*!< Uart parity check type */ - BL_Fun_Type ctsFlowControl; /*!< Enable or disable tx CTS flow control */ - BL_Fun_Type rxDeglitch; /*!< Enable or disable rx input de-glitch function */ - BL_Fun_Type rtsSoftwareControl; /*!< Enable or disable rx RTS output SW control mode */ - BL_Fun_Type txSoftwareControl; /*!< Enable or disable tx output SW control mode */ - BL_Fun_Type txLinMode; /*!< Enable or disable tx LIN mode,LIN header will be sent before sending data */ - BL_Fun_Type rxLinMode; /*!< Enable or disable rx LIN mode,LIN header will be required and checked before receiving data */ - uint8_t txBreakBitCnt; /*!< Uart tx break bit count,additional 8 bit times will be added since LIN break field requires at - least 13 bit times */ - UART_ByteBitInverse_Type byteBitInverse; /*!< Uart each data byte is send out LSB-first or MSB-first */ -} UART_CFG_Type; - -/** - * @brief UART FIFO configuration structure type definition - */ -typedef struct -{ - uint8_t txFifoDmaThreshold; /*!< TX FIFO threshold, dma tx request will not be asserted if tx fifo count is less than this value */ - uint8_t rxFifoDmaThreshold; /*!< RX FIFO threshold, dma rx request will not be asserted if rx fifo count is less than this value */ - BL_Fun_Type txFifoDmaEnable; /*!< Enable or disable tx dma req/ack interface */ - BL_Fun_Type rxFifoDmaEnable; /*!< Enable or disable rx dma req/ack interface */ -} UART_FifoCfg_Type; - -/** - * @brief UART infrared configuration structure type definition - */ -typedef struct -{ - BL_Fun_Type txIrEnable; /*!< Enable or disable uart tx ir mode */ - BL_Fun_Type rxIrEnable; /*!< Enable or disable uart rx ir mode */ - BL_Fun_Type txIrInverse; /*!< Enable or disable inverse signal of uart tx output in ir mode */ - BL_Fun_Type rxIrInverse; /*!< Enable or disable inverse signal of uart rx input in ir mode */ - uint16_t txIrPulseStart; /*!< Set start position of uart tx ir pulse */ - uint16_t txIrPulseStop; /*!< Set stop position of uart tx ir pulse */ - uint16_t rxIrPulseStart; /*!< Set start position of uart rx pulse recovered from ir signal */ -} UART_IrCfg_Type; - -/*@} end of group UART_Public_Types */ - -/** @defgroup UART_Public_Constants - * @{ - */ - -/** @defgroup UART_ID_TYPE - * @{ - */ -#define IS_UART_ID_TYPE(type) (((type) == UART0_ID) || \ - ((type) == UART1_ID) || \ - ((type) == UART2_ID) || \ - ((type) == UART0_MM_ID) || \ - ((type) == UART_ID_MAX)) - -/** @defgroup UART_DIRECTION_TYPE - * @{ - */ -#define IS_UART_DIRECTION_TYPE(type) (((type) == UART_TX) || \ - ((type) == UART_RX) || \ - ((type) == UART_TXRX)) - -/** @defgroup UART_PARITY_TYPE - * @{ - */ -#define IS_UART_PARITY_TYPE(type) (((type) == UART_PARITY_NONE) || \ - ((type) == UART_PARITY_ODD) || \ - ((type) == UART_PARITY_EVEN)) - -/** @defgroup UART_DATABITS_TYPE - * @{ - */ -#define IS_UART_DATABITS_TYPE(type) (((type) == UART_DATABITS_5) || \ - ((type) == UART_DATABITS_6) || \ - ((type) == UART_DATABITS_7) || \ - ((type) == UART_DATABITS_8)) - -/** @defgroup UART_STOPBITS_TYPE - * @{ - */ -#define IS_UART_STOPBITS_TYPE(type) (((type) == UART_STOPBITS_1) || \ - ((type) == UART_STOPBITS_1_5) || \ - ((type) == UART_STOPBITS_2)) - -/** @defgroup UART_BYTEBITINVERSE_TYPE - * @{ - */ -#define IS_UART_BYTEBITINVERSE_TYPE(type) (((type) == UART_LSB_FIRST) || \ - ((type) == UART_MSB_FIRST)) - -/** @defgroup UART_AUTOBAUDDETECTION_TYPE - * @{ - */ -#define IS_UART_AUTOBAUDDETECTION_TYPE(type) (((type) == UART_AUTOBAUD_0X55) || \ - ((type) == UART_AUTOBAUD_STARTBIT)) - -/** @defgroup UART_RS485POLARITY_TYPE - * @{ - */ -#define IS_UART_RS485POLARITY_TYPE(type) (((type) == UART_RS485_DE_ACTIVE_LOW) || \ - ((type) == UART_RS485_DE_ACTIVE_HIGH)) - -/** @defgroup UART_INT_TYPE - * @{ - */ -#define IS_UART_INT_TYPE(type) (((type) == UART_INT_TX_END) || \ - ((type) == UART_INT_RX_END) || \ - ((type) == UART_INT_TX_FIFO_REQ) || \ - ((type) == UART_INT_RX_FIFO_REQ) || \ - ((type) == UART_INT_RTO) || \ - ((type) == UART_INT_PCE) || \ - ((type) == UART_INT_TX_FER) || \ - ((type) == UART_INT_RX_FER) || \ - ((type) == UART_INT_LSE) || \ - ((type) == UART_INT_BCR) || \ - ((type) == UART_INT_STARTBIT) || \ - ((type) == UART_INT_0X55) || \ - ((type) == UART_INT_ALL)) - -/** @defgroup UART_OVERFLOW_TYPE - * @{ - */ -#define IS_UART_OVERFLOW_TYPE(type) (((type) == UART_TX_OVERFLOW) || \ - ((type) == UART_TX_UNDERFLOW) || \ - ((type) == UART_RX_OVERFLOW) || \ - ((type) == UART_RX_UNDERFLOW)) - -/*@} end of group UART_Public_Constants */ - -/** @defgroup UART_Public_Macros - * @{ - */ -#define UART_RX_FIFO_SIZE 128 -#define UART_TX_FIFO_SIZE 128 -#define UART_DEFAULT_RECV_TIMEOUT 80 - -/*@} end of group UART_Public_Macros */ - -/** @defgroup UART_Public_Functions - * @{ - */ - -/** - * @brief UART Functions - */ -#if (defined BOOTROM) || (!defined BFLB_USE_HAL_DRIVER) || (defined BFLB_EFLASH_LOADER) -void UART0_IRQHandler(void); -void UART1_IRQHandler(void); -void UART2_IRQHandler(void); -void UART3_IRQHandler(void); -void UART4_IRQHandler(void); -#endif -BL_Err_Type UART_SetBaudRate(UART_ID_Type uartId, uint32_t baudRate); -BL_Err_Type UART_Init(UART_ID_Type uartId, UART_CFG_Type *uartCfg); -BL_Err_Type UART_DeInit(UART_ID_Type uartId); -BL_Err_Type UART_FifoConfig(UART_ID_Type uartId, UART_FifoCfg_Type *fifoCfg); -BL_Err_Type UART_IrConfig(UART_ID_Type uartId, UART_IrCfg_Type *irCfg); -BL_Err_Type UART_Enable(UART_ID_Type uartId, UART_Direction_Type direct); -BL_Err_Type UART_Disable(UART_ID_Type uartId, UART_Direction_Type direct); -BL_Err_Type UART_SetTxDataLength(UART_ID_Type uartId, uint16_t length); -BL_Err_Type UART_SetRxDataLength(UART_ID_Type uartId, uint16_t length); -BL_Err_Type UART_SetRxTimeoutValue(UART_ID_Type uartId, uint8_t time); -BL_Err_Type UART_SetRxByteCount(UART_ID_Type uartId, uint16_t count); -BL_Err_Type UART_SetDeglitchCount(UART_ID_Type uartId, uint8_t deglitchCnt); -BL_Err_Type UART_ApplyAbrResult(UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet); -BL_Err_Type UART_SetRtsValue(UART_ID_Type uartId); -BL_Err_Type UART_ClrRtsValue(UART_ID_Type uartId); -BL_Err_Type UART_SetTxValue(UART_ID_Type uartId); -BL_Err_Type UART_ClrTxValue(UART_ID_Type uartId); -BL_Err_Type UART_TxFreeRun(UART_ID_Type uartId, BL_Fun_Type txFreeRun); -BL_Err_Type UART_AutoBaudDetection(UART_ID_Type uartId, BL_Fun_Type autoBaud); -BL_Err_Type UART_SetAllowableError0X55(UART_ID_Type uartId, uint8_t allowableError); -BL_Err_Type UART_GetBitWidth0X55(UART_ID_Type uartId, uint16_t *width); -BL_Err_Type UART_SetRS485(UART_ID_Type uartId, BL_Fun_Type enable, UART_RS485Polarity_Type polarity); -BL_Err_Type UART_TxFifoClear(UART_ID_Type uartId); -BL_Err_Type UART_RxFifoClear(UART_ID_Type uartId); -BL_Err_Type UART_IntMask(UART_ID_Type uartId, UART_INT_Type intType, BL_Mask_Type intMask); -BL_Err_Type UART_IntClear(UART_ID_Type uartId, UART_INT_Type intType); -BL_Err_Type UART_Int_Callback_Install(UART_ID_Type uartId, UART_INT_Type intType, intCallback_Type *cbFun); -BL_Err_Type UART_SendData(UART_ID_Type uartId, uint8_t *data, uint32_t len); -BL_Err_Type UART_SendDataBlock(UART_ID_Type uartId, uint8_t *data, uint32_t len); -uint32_t UART_ReceiveData(UART_ID_Type uartId, uint8_t *data, uint32_t maxLen); -uint16_t UART_GetAutoBaudCount(UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet); -uint16_t UART_GetRxByteCount(UART_ID_Type uartId); -uint8_t UART_GetTxFifoCount(UART_ID_Type uartId); -uint8_t UART_GetRxFifoCount(UART_ID_Type uartId); -BL_Sts_Type UART_GetIntStatus(UART_ID_Type uartId, UART_INT_Type intType); -BL_Sts_Type UART_GetTxBusBusyStatus(UART_ID_Type uartId); -BL_Sts_Type UART_GetRxBusBusyStatus(UART_ID_Type uartId); -BL_Sts_Type UART_GetOverflowStatus(UART_ID_Type uartId, UART_Overflow_Type overflow); - -/*@} end of group UART_Public_Functions */ - -/*@} end of group UART */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_UART_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_uhs_phy.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_uhs_phy.h deleted file mode 100644 index 71bb906797..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_uhs_phy.h +++ /dev/null @@ -1,46 +0,0 @@ -#ifndef __UHS_PHY_H__ -#define __UHS_PHY_H__ - -#include "bl808_common.h" -// /** @addtogroup Configuration_section_for_RISCV -// * @{ -// */ -// #define BL_RD_WORD(addr) (*((volatile uint32_t*)(addr))) -// #define BL_WR_WORD(addr,val) ((*(volatile uint32_t*)(addr))=(val)) -// #define BL_RD_SHORT(addr) (*((volatile uint16_t*)(addr))) -// #define BL_WR_SHORT(addr,val) ((*(volatile uint16_t*)(addr))=(val)) -// #define BL_RD_BYTE(addr) (*((volatile uint8_t*)(addr))) -// #define BL_WR_BYTE(addr,val) ((*(volatile uint8_t*)(addr))=(val)) -// #define BL_RDWD_FRM_BYTEP(p) ((p[3]<<24)|(p[2]<<16)|(p[1]<<8)|(p[0])) -// #define BL_WRWD_TO_BYTEP(p,val) {p[0]=val&0xff;p[1]=(val>>8)&0xff;p[2]=(val>>16)&0xff;p[3]=(val>>24)&0xff;} -// /** -// * @brief Register access macro -// */ -// #define BL_RD_REG16(addr,regname) BL_RD_SHORT(addr+regname##_OFFSET) -// #define BL_WR_REG16(addr,regname,val) BL_WR_SHORT(addr+regname##_OFFSET,val) -// #define BL_RD_REG(addr,regname) BL_RD_WORD(addr+regname##_OFFSET) -// #define BL_WR_REG(addr,regname,val) BL_WR_WORD(addr+regname##_OFFSET,val) -// #define BL_SET_REG_BIT(val,bitname) ( (val) |(1U<> bitname##_POS ) -// #define BL_SET_REG_BITS_VAL(val,bitname,bitval) ( ((val)&bitname##_UMSK) | ((uint32_t)(bitval)<
© COPYRIGHT(c) 2020 Bouffalo Lab
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_USB_H__ -#define __BL808_USB_H__ - -#include "usb_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup USB - * @{ - */ - -/** @defgroup USB_Public_Types - * @{ - */ - -/** - * @brief USB LPM response type definition - */ -typedef enum { - USB_LPM_RESP_NYET = 0, /*!< response LPM with NYET */ - USB_LPM_RESP_ACK = 1, /*!< response LPM with ACK */ -} USB_LPM_RESP_Type; - -/** - * @brief USB LPM configuration structure type definition - */ -typedef struct -{ - uint8_t lpmEn; /*!< response LPM or not */ - USB_LPM_RESP_Type resp; /*!< response LPM with ACK or NAK */ - uint8_t minBesl; /*!< BESL min value */ - uint8_t maxBesl; /*!< BESL max value */ - uint8_t lpmWakeUpEn; /*!< LPM wakeup enable */ -} USB_LPM_Cfg_Type; - -/** - * @brief USB global interrupt type definition - */ -typedef enum { - USB_GLOBAL_INT_DEV = 0, /*!< USB device interrupt type */ - USB_GLOBAL_INT_OTG = 1, /*!< USB OTG interrupt type */ - USB_GLOBAL_INT_HC = 2, /*!< USB host interrupt type */ -} USB_GLOBAL_INT_Type; - -/** - * @brief USB global interrupt type definition - */ -typedef enum { - USB_DEVICE_SPEED_FULL_SPEED = 0, /*!< USB device interrupt type */ - USB_DEVICE_SPEED_HIGH_SPEED = 1, /*!< USB OTG interrupt type */ -} USB_DEVICE_SPEED_Type; - -/** - * @brief USB normal configuration structure type definition - */ -typedef struct -{ - uint8_t forceFullSpeed; /*!< force device to full speed */ - uint8_t chipEn; /*!< chip enable */ - uint8_t swRst; /*!< software reset */ - uint8_t remoteWakeupEn; /*!< remote wakeup capability enable */ - uint32_t rstTimeOut; /*!< software reset timeout count */ -} USB_NORMAL_Cfg_Type; - -/** - * @brief USB FIFO empty type definition - */ -typedef enum { - USB_FIFO_EMPTY_FIFO_0 = 8, /*!< USB FIFO 0 empty type */ - USB_FIFO_EMPTY_FIFO_1 = 9, /*!< USB FIFO 1 empty type */ - USB_FIFO_EMPTY_FIFO_2 = 10, /*!< USB FIFO 2 empty type */ - USB_FIFO_EMPTY_FIFO_3 = 11, /*!< USB FIFO 3 empty type */ -} USB_FIFO_EMPTY_Type; - -/** - * @brief USB endpoint ID type definition - */ -typedef enum { - USB_Endpoint_0 = 0, /*!< USB endpoint ID 0 */ - USB_Endpoint_1 = 1, /*!< USB endpoint ID 1 */ - USB_Endpoint_2 = 2, /*!< USB endpoint ID 2 */ - USB_Endpoint_3 = 3, /*!< USB endpoint ID 3 */ - USB_Endpoint_4 = 4, /*!< USB endpoint ID 4 */ - USB_Endpoint_5 = 5, /*!< USB endpoint ID 5 */ - USB_Endpoint_6 = 6, /*!< USB endpoint ID 6 */ - USB_Endpoint_7 = 7, /*!< USB endpoint ID 7 */ - USB_Endpoint_8 = 8, /*!< USB endpoint ID 8 */ -} USB_Endpoint_Type; - -/** - * @brief USB FIFO ID type definition - */ -typedef enum { - USB_FIFO_0 = 0, /*!< USB endpoint ID 0 */ - USB_FIFO_1 = 1, /*!< USB endpoint ID 1 */ - USB_FIFO_2 = 2, /*!< USB endpoint ID 2 */ - USB_FIFO_3 = 3, /*!< USB endpoint ID 3 */ -} USB_FIFO_Type; - -/** - * @brief USB FIFO direction type definition - */ -typedef enum { - USB_FIFO_DIR_OUT = 0, /*!< USB FIFO direction out */ - USB_FIFO_DIR_IN = 1, /*!< USB FIFO direction in */ - USB_FIFO_DIR_BID = 2, /*!< USB FIFO direction bidirectional */ -} USB_FIFO_DIR_Type; - -/** - * @brief USB FIFO block max size type definition - */ -typedef enum { - USB_FIFO_BLOCK_MAX_SIZE_512 = 0, /*!< USB FIFO block max packet size 512 */ - USB_FIFO_BLOCK_MAX_SIZE_1024 = 1, /*!< USB FIFO block max packet size 1024 */ -} USB_FIFO_BLOCK_MAX_SIZE_Type; - -/** - * @brief USB FIFO block count type definition - */ -typedef enum { - USB_FIFO_BLOCK_CNT_SINGLE_BLOCK = 0, /*!< USB FIFO single block */ - USB_FIFO_BLOCK_CNT_DOUBLE_BLOCKS = 1, /*!< USB FIFO double block */ - USB_FIFO_BLOCK_CNT_TRIPLE_BLOCKS = 2, /*!< USB FIFO triple block */ -} USB_FIFO_BLOCK_CNT_Type; - -/** - * @brief USB FIFO transfer type definition - */ -typedef enum { - USB_FIFO_TRANSFER_RSV = 0, /*!< USB FIFO transfer type is reserved */ - USB_FIFO_TRANSFER_ISO = 1, /*!< USB FIFO transfer type is isochronous */ - USB_FIFO_TRANSFER_BULK = 2, /*!< USB FIFO transfer type is bulk */ - USB_FIFO_TRANSFER_INT = 3, /*!< USB FIFO transfer type is interrupt */ -} USB_FIFO_TRANSFER_Type; - -/** - * @brief USB FIFO configuration structure type definition - */ -typedef struct -{ - uint8_t enable; /*!< FIFO enable or disable */ - USB_FIFO_DIR_Type dir; /*!< FIFO direction */ - USB_Endpoint_Type epID; /*!< Endpoint number of FIFO */ - USB_FIFO_BLOCK_MAX_SIZE_Type blockSize; /*!< FIFO block max size */ - USB_FIFO_BLOCK_CNT_Type blockType; /*!< FIFO block type */ - USB_FIFO_TRANSFER_Type fifoType; /*!< FIFO transfer type */ -} USB_FIFO_Cfg_Type; - -/** - * @brief USB DMA target FIFO type definition - */ -typedef enum { - USB_DMA_TARGET_FIFO_CTRL = 0, /*!< USB DMA target FIFO is control FIFO */ - USB_DMA_TARGET_FIFO_0 = 1, /*!< USB DMA target FIFO is FIFO 0 */ - USB_DMA_TARGET_FIFO_1 = 2, /*!< USB DMA target FIFO is FIFO 1 */ - USB_DMA_TARGET_FIFO_2 = 3, /*!< USB DMA target FIFO is FIFO 2 */ - USB_DMA_TARGET_FIFO_3 = 4, /*!< USB DMA target FIFO is FIFO 3 */ -} USB_DMA_TARGET_FIFO_Type; - -/** - * @brief USB DMA transfer type definition - */ -typedef enum { - USB_DMA_TRANS_DIR_FIFO_2_MEM = 0, /*!< USB DMA transfer type is FIFO to memory */ - USB_DMA_TRANS_DIR_MEM_2_FIFO = 1, /*!< USB DMA transfer type is memory to FIFO */ - USB_DMA_TRANS_DIR_FIFO_2_FIFO = 2, /*!< USB DMA transfer type is FIFO to FIFO */ -} USB_DMA_TRANS_DIR_Type; - -/** - * @brief USB DMA configuration structure type definition - */ -typedef struct -{ - USB_DMA_TRANS_DIR_Type dir; /*!< USB DMA transfer direction */ - uint32_t memAddr; /*!< USB DMA target memory address */ - uint32_t length; /*!< USB DMA transfer length */ -} USB_DMA_Cfg_Type; - -/** - * @brief USB Virtual DMA target FIFO type definition - */ -typedef enum { - USB_VDMA_TARGET_FIFO_CTRL = 0, /*!< USB VDMA target FIFO is control FIFO */ - USB_VDMA_TARGET_FIFO_0 = 1, /*!< USB VDMA target FIFO is FIFO 0 */ - USB_VDMA_TARGET_FIFO_1 = 2, /*!< USB VDMA target FIFO is FIFO 1 */ - USB_VDMA_TARGET_FIFO_2 = 3, /*!< USB VDMA target FIFO is FIFO 2 */ - USB_VDMA_TARGET_FIFO_3 = 4, /*!< USB VDMA target FIFO is FIFO 3 */ -} USB_VDMA_TARGET_FIFO_Type; - -/** - * @brief USB Virtual DMA transfer type definition - */ -typedef enum { - USB_VDMA_TRANS_DIR_FIFO_2_MEM = 0, /*!< USB VDMA transfer type is FIFO to memory */ - USB_VDMA_TRANS_DIR_MEM_2_FIFO = 1, /*!< USB VDMA transfer type is memory to FIFO */ - USB_VDMA_TRANS_DIR_FIFO_2_FIFO = 2, /*!< USB VDMA transfer type is FIFO to FIFO */ -} USB_VDMA_TRANS_DIR_Type; - -/** - * @brief USB Virtual DMA configuration structure type definition - */ -typedef struct -{ - USB_VDMA_TRANS_DIR_Type dir; /*!< USB VDMA transfer direction */ - uint32_t memAddr; /*!< USB VDMA target memory address */ - uint32_t length; /*!< USB VDMA transfer length */ -} USB_VDMA_Cfg_Type; - -/** - * @brief USB interrupt group type definition - */ -typedef enum { - USB_GRP_INT_G0 = 0, /*!< USB group 0 interrupt type */ - USB_GRP_INT_G1 = 1, /*!< USB group 1 interrupt type */ - USB_GRP_INT_G2 = 2, /*!< USB group 2 interrupt type */ - USB_GRP_INT_G3 = 3, /*!< USB group 3 interrupt type */ - USB_GRP_INT_G4 = 4, /*!< USB group 4 interrupt type */ -} USB_GRP_INT_Type; - -/** - * @brief USB interrupt group0 type definition - */ -typedef enum { - USB_SUB_GRP0_INT_CX_SETUP = 0, /*!< group0 endpoint 0 setup data received */ - USB_SUB_GRP0_INT_CX_IN = 1, /*!< group0 endpoint 0 IN */ - USB_SUB_GRP0_INT_CX_OUT = 2, /*!< group0 endpoint 0 OUT */ - USB_SUB_GRP0_INT_CX_COMFAIL = 3, /*!< group0 endpoint 0 COMFAIL */ - USB_SUB_GRP0_INT_CX_COMABORT = 4, /*!< group0 endpoint 0 COMABORT */ - USB_SUB_GRP1_INT_F0_OUT = 5, /*!< group1 OUT interrupt of FIFO 0 */ - USB_SUB_GRP1_INT_F0_SPK = 6, /*!< group1 short packet interrupt of FIFO 0 */ - USB_SUB_GRP1_INT_F1_OUT = 7, /*!< group1 OUT interrupt of FIFO 1 */ - USB_SUB_GRP1_INT_F1_SPK = 8, /*!< group1 short packet interrupt of FIFO 1 */ - USB_SUB_GRP1_INT_F2_OUT = 9, /*!< group1 OUT interrupt of FIFO 2 */ - USB_SUB_GRP1_INT_F2_SPK = 10, /*!< group1 short packet interrupt of FIFO 2 */ - USB_SUB_GRP1_INT_F3_OUT = 11, /*!< group1 OUT interrupt of FIFO 3 */ - USB_SUB_GRP1_INT_F3_SPK = 12, /*!< group1 short packet interrupt of FIFO 3 */ - USB_SUB_GRP1_INT_F0_IN = 13, /*!< group1 IN interrupt of FIFO 0 */ - USB_SUB_GRP1_INT_F1_IN = 14, /*!< group1 IN interrupt of FIFO 1 */ - USB_SUB_GRP1_INT_F2_IN = 15, /*!< group1 IN interrupt of FIFO 2 */ - USB_SUB_GRP1_INT_F3_IN = 16, /*!< group1 IN interrupt of FIFO 3 */ - USB_SUB_GRP2_INT_RESET = 17, /*!< group2 USB reset interrupt */ - USB_SUB_GRP2_INT_SUSPEND = 18, /*!< group2 suspend interrupt */ - USB_SUB_GRP2_INT_RESUME = 19, /*!< group2 resume interrupt */ - USB_SUB_GRP2_INT_TX0BYTE = 20, /*!< group2 transferred zero-length data packet interrupt */ - USB_SUB_GRP2_INT_RX0BYTE = 21, /*!< group2 received zero-length data packet interrupt */ - USB_SUB_GRP2_INT_DMA_CMPLT = 22, /*!< group2 DMA completion interrupt */ - USB_SUB_GRP2_INT_DMA_ERROR = 23, /*!< group2 DMA error interrupt */ - USB_SUB_GRP2_INT_IDLE = 24, /*!< group2 dev_idle interrupt */ - USB_SUB_GRP2_INT_WAKEUP_BY_VBUS = 25, /*!< group2 dev_wakeup_byVBUS interrupt */ - USB_SUB_GRP3_INT_VDMA_CMPLT_CXF = 26, /*!< group3 Virtual DMA completion interrupt for FIFO CXF */ - USB_SUB_GRP3_INT_VDMA_CMPLT_F0 = 27, /*!< group3 Virtual DMA completion interrupt for FIFO 0 */ - USB_SUB_GRP3_INT_VDMA_CMPLT_F1 = 28, /*!< group3 Virtual DMA completion interrupt for FIFO 1 */ - USB_SUB_GRP3_INT_VDMA_CMPLT_F2 = 29, /*!< group3 Virtual DMA completion interrupt for FIFO 2 */ - USB_SUB_GRP3_INT_VDMA_CMPLT_F3 = 30, /*!< group3 Virtual DMA completion interrupt for FIFO 3 */ - USB_SUB_GRP3_INT_VDMA_ERROR_CXF = 31, /*!< group3 Virtual DMA error interrupt for FIFO CXF */ - USB_SUB_GRP3_INT_VDMA_ERROR_F0 = 32, /*!< group3 Virtual DMA error interrupt for FIFO 0 */ - USB_SUB_GRP3_INT_VDMA_ERROR_F1 = 33, /*!< group3 Virtual DMA error interrupt for FIFO 1 */ - USB_SUB_GRP3_INT_VDMA_ERROR_F2 = 34, /*!< group3 Virtual DMA error interrupt for FIFO 2 */ - USB_SUB_GRP3_INT_VDMA_ERROR_F3 = 35, /*!< group3 Virtual DMA error interrupt for FIFO 3 */ - USB_SUB_GRP4_INT_L1 = 36, /*!< group4 L1-state-change interrupt */ -} USB_SUB_GRP_INT_Type; - -/*@} end of group USB_Public_Types */ - -/** @defgroup USB_Public_Constants - * @{ - */ - -/** @defgroup USB_LPM_RESP_TYPE - * @{ - */ -#define IS_USB_LPM_RESP_TYPE(type) (((type) == USB_LPM_RESP_NYET) || \ - ((type) == USB_LPM_RESP_ACK)) - -/** @defgroup USB_GLOBAL_INT_TYPE - * @{ - */ -#define IS_USB_GLOBAL_INT_TYPE(type) (((type) == USB_GLOBAL_INT_DEV) || \ - ((type) == USB_GLOBAL_INT_OTG) || \ - ((type) == USB_GLOBAL_INT_HC)) - -/** @defgroup USB_DEVICE_SPEED_TYPE - * @{ - */ -#define IS_USB_DEVICE_SPEED_TYPE(type) (((type) == USB_DEVICE_SPEED_FULL_SPEED) || \ - ((type) == USB_DEVICE_SPEED_HIGH_SPEED)) - -/** @defgroup USB_FIFO_EMPTY_TYPE - * @{ - */ -#define IS_USB_FIFO_EMPTY_TYPE(type) (((type) == USB_FIFO_EMPTY_FIFO_0) || \ - ((type) == USB_FIFO_EMPTY_FIFO_1) || \ - ((type) == USB_FIFO_EMPTY_FIFO_2) || \ - ((type) == USB_FIFO_EMPTY_FIFO_3)) - -/** @defgroup USB_ENDPOINT_TYPE - * @{ - */ -#define IS_USB_ENDPOINT_TYPE(type) (((type) == USB_Endpoint_1) || \ - ((type) == USB_Endpoint_2) || \ - ((type) == USB_Endpoint_3) || \ - ((type) == USB_Endpoint_4) || \ - ((type) == USB_Endpoint_5) || \ - ((type) == USB_Endpoint_6) || \ - ((type) == USB_Endpoint_7) || \ - ((type) == USB_Endpoint_8)) - -/** @defgroup USB_FIFO_TYPE - * @{ - */ -#define IS_USB_FIFO_TYPE(type) (((type) == USB_FIFO_0) || \ - ((type) == USB_FIFO_1) || \ - ((type) == USB_FIFO_2) || \ - ((type) == USB_FIFO_3)) - -/** @defgroup USB_FIFO_DIR_TYPE - * @{ - */ -#define IS_USB_FIFO_DIR_TYPE(type) (((type) == USB_FIFO_DIR_OUT) || \ - ((type) == USB_FIFO_DIR_IN) || \ - ((type) == USB_FIFO_DIR_BID)) - -/** @defgroup USB_FIFO_BLOCK_MAX_SIZE_TYPE - * @{ - */ -#define IS_USB_FIFO_BLOCK_MAX_SIZE_TYPE(type) (((type) == USB_FIFO_BLOCK_MAX_SIZE_512) || \ - ((type) == USB_FIFO_BLOCK_MAX_SIZE_1024)) - -/** @defgroup USB_FIFO_BLOCK_CNT_TYPE - * @{ - */ -#define IS_USB_FIFO_BLOCK_CNT_TYPE(type) (((type) == USB_FIFO_BLOCK_CNT_SINGLE_BLOCK) || \ - ((type) == USB_FIFO_BLOCK_CNT_DOUBLE_BLOCKS) || \ - ((type) == USB_FIFO_BLOCK_CNT_TRIPLE_BLOCKS)) - -/** @defgroup USB_FIFO_TRANSFER_TYPE - * @{ - */ -#define IS_USB_FIFO_TRANSFER_TYPE(type) (((type) == USB_FIFO_TRANSFER_RSV) || \ - ((type) == USB_FIFO_TRANSFER_ISO) || \ - ((type) == USB_FIFO_TRANSFER_BULK) || \ - ((type) == USB_FIFO_TRANSFER_INT)) - -/** @defgroup USB_DMA_TARGET_FIFO_TYPE - * @{ - */ -#define IS_USB_DMA_TARGET_FIFO_TYPE(type) (((type) == USB_DMA_TARGET_FIFO_0) || \ - ((type) == USB_DMA_TARGET_FIFO_1) || \ - ((type) == USB_DMA_TARGET_FIFO_2) || \ - ((type) == USB_DMA_TARGET_FIFO_3) || \ - ((type) == USB_DMA_TARGET_FIFO_CTRL)) - -/** @defgroup USB_DMA_TRANS_DIR_TYPE - * @{ - */ -#define IS_USB_DMA_TRANS_DIR_TYPE(type) (((type) == USB_DMA_TRANS_DIR_FIFO_2_MEM) || \ - ((type) == USB_DMA_TRANS_DIR_MEM_2_FIFO) || \ - ((type) == USB_DMA_TRANS_DIR_FIFO_2_FIFO)) - -/** @defgroup USB_VDMA_TARGET_FIFO_TYPE - * @{ - */ -#define IS_USB_VDMA_TARGET_FIFO_TYPE(type) (((type) == USB_VDMA_TARGET_FIFO_0) || \ - ((type) == USB_VDMA_TARGET_FIFO_1) || \ - ((type) == USB_VDMA_TARGET_FIFO_2) || \ - ((type) == USB_VDMA_TARGET_FIFO_3) || \ - ((type) == USB_VDMA_TARGET_FIFO_CTRL)) - -/** @defgroup USB_VDMA_TRANS_DIR_TYPE - * @{ - */ -#define IS_USB_VDMA_TRANS_DIR_TYPE(type) (((type) == USB_VDMA_TRANS_DIR_FIFO_2_MEM) || \ - ((type) == USB_VDMA_TRANS_DIR_MEM_2_FIFO) || \ - ((type) == USB_VDMA_TRANS_DIR_FIFO_2_FIFO)) - -/** @defgroup USB_GRP_INT_TYPE - * @{ - */ -#define IS_USB_GRP_INT_TYPE(type) (((type) == USB_GRP_INT_G0) || \ - ((type) == USB_GRP_INT_G1) || \ - ((type) == USB_GRP_INT_G2) || \ - ((type) == USB_GRP_INT_G3) || \ - ((type) == USB_GRP_INT_G4)) - -/** @defgroup USB_SUB_GRP_INT_TYPE - * @{ - */ -#define IS_USB_SUB_GRP_INT_TYPE(type) (((type) == USB_SUB_GRP0_INT_CX_SETUP) || \ - ((type) == USB_SUB_GRP0_INT_CX_IN) || \ - ((type) == USB_SUB_GRP0_INT_CX_OUT) || \ - ((type) == USB_SUB_GRP0_INT_CX_COMFAIL) || \ - ((type) == USB_SUB_GRP0_INT_CX_COMABORT) || \ - ((type) == USB_SUB_GRP1_INT_F0_OUT) || \ - ((type) == USB_SUB_GRP1_INT_F0_SPK) || \ - ((type) == USB_SUB_GRP1_INT_F1_OUT) || \ - ((type) == USB_SUB_GRP1_INT_F1_SPK) || \ - ((type) == USB_SUB_GRP1_INT_F2_OUT) || \ - ((type) == USB_SUB_GRP1_INT_F2_SPK) || \ - ((type) == USB_SUB_GRP1_INT_F3_OUT) || \ - ((type) == USB_SUB_GRP1_INT_F3_SPK) || \ - ((type) == USB_SUB_GRP1_INT_F0_IN) || \ - ((type) == USB_SUB_GRP1_INT_F1_IN) || \ - ((type) == USB_SUB_GRP1_INT_F2_IN) || \ - ((type) == USB_SUB_GRP1_INT_F3_IN) || \ - ((type) == USB_SUB_GRP2_INT_RESET) || \ - ((type) == USB_SUB_GRP2_INT_SUSPEND) || \ - ((type) == USB_SUB_GRP2_INT_RESUME) || \ - ((type) == USB_SUB_GRP2_INT_TX0BYTE) || \ - ((type) == USB_SUB_GRP2_INT_RX0BYTE) || \ - ((type) == USB_SUB_GRP2_INT_DMA_CMPLT) || \ - ((type) == USB_SUB_GRP2_INT_DMA_ERROR) || \ - ((type) == USB_SUB_GRP2_INT_IDLE) || \ - ((type) == USB_SUB_GRP2_INT_WAKEUP_BY_VBUS) || \ - ((type) == USB_SUB_GRP3_INT_VDMA_CMPLT_CXF) || \ - ((type) == USB_SUB_GRP3_INT_VDMA_CMPLT_F0) || \ - ((type) == USB_SUB_GRP3_INT_VDMA_CMPLT_F1) || \ - ((type) == USB_SUB_GRP3_INT_VDMA_CMPLT_F2) || \ - ((type) == USB_SUB_GRP3_INT_VDMA_CMPLT_F3) || \ - ((type) == USB_SUB_GRP3_INT_VDMA_ERROR_CXF) || \ - ((type) == USB_SUB_GRP3_INT_VDMA_ERROR_F0) || \ - ((type) == USB_SUB_GRP3_INT_VDMA_ERROR_F1) || \ - ((type) == USB_SUB_GRP3_INT_VDMA_ERROR_F2) || \ - ((type) == USB_SUB_GRP3_INT_VDMA_ERROR_F3) || \ - ((type) == USB_SUB_GRP4_INT_L1)) - -/*@} end of group USB_Public_Constants */ - -/** @defgroup USB_Public_Macros - * @{ - */ -#define USB_SUB_GRP0_INT_OFS (0) -#define USB_SUB_GRP1_INT_OFS (32) -#define USB_SUB_GRP2_INT_OFS (64) -#define USB_SUB_GRP3_INT_OFS (96) -#define USB_SUB_GRP4_INT_OFS (128) -#define USB_SOF_TIMER_MASK_AFTER_RESET_HS (0x44C) -#define USB_SOF_TIMER_MASK_AFTER_RESET_FS (0x2710) - -#define USB_INT_CX_SETUP (1ULL << USB_SUB_GRP0_INT_CX_SETUP) -#define USB_INT_CX_IN (1ULL << USB_SUB_GRP0_INT_CX_IN) -#define USB_INT_CX_OUT (1ULL << USB_SUB_GRP0_INT_CX_OUT) -#define USB_INT_CX_COMFAIL (1ULL << USB_SUB_GRP0_INT_CX_COMFAIL) -#define USB_INT_CX_COMABORT (1ULL << USB_SUB_GRP0_INT_CX_COMABORT) -#define USB_INT_F0_OUT (1ULL << USB_SUB_GRP1_INT_F0_OUT) -#define USB_INT_F0_SPK (1ULL << USB_SUB_GRP1_INT_F0_SPK) -#define USB_INT_F1_OUT (1ULL << USB_SUB_GRP1_INT_F1_OUT) -#define USB_INT_F1_SPK (1ULL << USB_SUB_GRP1_INT_F1_SPK) -#define USB_INT_F2_OUT (1ULL << USB_SUB_GRP1_INT_F2_OUT) -#define USB_INT_F2_SPK (1ULL << USB_SUB_GRP1_INT_F2_SPK) -#define USB_INT_F3_OUT (1ULL << USB_SUB_GRP1_INT_F3_OUT) -#define USB_INT_F3_SPK (1ULL << USB_SUB_GRP1_INT_F3_SPK) -#define USB_INT_F0_IN (1ULL << USB_SUB_GRP1_INT_F0_IN) -#define USB_INT_F1_IN (1ULL << USB_SUB_GRP1_INT_F1_IN) -#define USB_INT_F2_IN (1ULL << USB_SUB_GRP1_INT_F2_IN) -#define USB_INT_F3_IN (1ULL << USB_SUB_GRP1_INT_F3_IN) -#define USB_INT_RESET (1ULL << USB_SUB_GRP2_INT_RESET) -#define USB_INT_SUSPEND (1ULL << USB_SUB_GRP2_INT_SUSPEND) -#define USB_INT_RESUME (1ULL << USB_SUB_GRP2_INT_RESUME) -#define USB_INT_TX0BYTE (1ULL << USB_SUB_GRP2_INT_TX0BYTE) -#define USB_INT_RX0BYTE (1ULL << USB_SUB_GRP2_INT_RX0BYTE) -#define USB_INT_DMA_CMPLT (1ULL << USB_SUB_GRP2_INT_DMA_CMPLT) -#define USB_INT_DMA_ERROR (1ULL << USB_SUB_GRP2_INT_DMA_ERROR) -#define USB_INT_IDLE (1ULL << USB_SUB_GRP2_INT_IDLE) -#define USB_INT_WAKEUP_BY_VBUS (1ULL << USB_SUB_GRP2_INT_WAKEUP_BY_VBUS) -#define USB_INT_VDMA_CMPLT_CXF (1ULL << USB_SUB_GRP3_INT_VDMA_CMPLT_CXF) -#define USB_INT_VDMA_CMPLT_F0 (1ULL << USB_SUB_GRP3_INT_VDMA_CMPLT_F0) -#define USB_INT_VDMA_CMPLT_F1 (1ULL << USB_SUB_GRP3_INT_VDMA_CMPLT_F1) -#define USB_INT_VDMA_CMPLT_F2 (1ULL << USB_SUB_GRP3_INT_VDMA_CMPLT_F2) -#define USB_INT_VDMA_CMPLT_F3 (1ULL << USB_SUB_GRP3_INT_VDMA_CMPLT_F3) -#define USB_INT_VDMA_ERROR_CXF (1ULL << USB_SUB_GRP3_INT_VDMA_ERROR_CXF) -#define USB_INT_VDMA_ERROR_F0 (1ULL << USB_SUB_GRP3_INT_VDMA_ERROR_F0) -#define USB_INT_VDMA_ERROR_F1 (1ULL << USB_SUB_GRP3_INT_VDMA_ERROR_F1) -#define USB_INT_VDMA_ERROR_F2 (1ULL << USB_SUB_GRP3_INT_VDMA_ERROR_F2) -#define USB_INT_VDMA_ERROR_F3 (1ULL << USB_SUB_GRP3_INT_VDMA_ERROR_F3) -#define USB_INT_L1 (1ULL << USB_SUB_GRP4_INT_L1) - -#define USB_SUB_GROUP_0_CX_SETUP_BIT_MUSK (0x00000001) -#define USB_SUB_GROUP_0_CX_IN_BIT_MUSK (0x00000002) -#define USB_SUB_GROUP_0_CX_OUT_BIT_MUSK (0x00000004) -#define USB_SUB_GROUP_0_CX_COMFAIL_BIT_MUSK (0x00000010) -#define USB_SUB_GROUP_0_CX_COMABORT_BIT_MUSK (0x00000020) -#define USB_SUB_GROUP_1_F0_OUT_BIT_MUSK (0x00000001) -#define USB_SUB_GROUP_1_F0_SPK_BIT_MUSK (0x00000002) -#define USB_SUB_GROUP_1_F1_OUT_BIT_MUSK (0x00000004) -#define USB_SUB_GROUP_1_F1_SPK_BIT_MUSK (0x00000008) -#define USB_SUB_GROUP_1_F2_OUT_BIT_MUSK (0x00000010) -#define USB_SUB_GROUP_1_F2_SPK_BIT_MUSK (0x00000020) -#define USB_SUB_GROUP_1_F3_OUT_BIT_MUSK (0x00000040) -#define USB_SUB_GROUP_1_F3_SPK_BIT_MUSK (0x00000080) -#define USB_SUB_GROUP_1_F0_IN_BIT_MUSK (0x00010000) -#define USB_SUB_GROUP_1_F1_IN_BIT_MUSK (0x00020000) -#define USB_SUB_GROUP_1_F2_IN_BIT_MUSK (0x00040000) -#define USB_SUB_GROUP_1_F3_IN_BIT_MUSK (0x00080000) -#define USB_SUB_GROUP_2_RESET_BIT_MUSK (0x00000001) -#define USB_SUB_GROUP_2_SUSPEND_BIT_MUSK (0x00000002) -#define USB_SUB_GROUP_2_RESUME_BIT_MUSK (0x00000004) -#define USB_SUB_GROUP_2_TX0BYTE_BIT_MUSK (0x00000020) -#define USB_SUB_GROUP_2_RX0BYTE_BIT_MUSK (0x00000040) -#define USB_SUB_GROUP_2_CMPLT_BIT_MUSK (0x00000080) -#define USB_SUB_GROUP_2_ERROR_BIT_MUSK (0x00000100) -#define USB_SUB_GROUP_2_IDLE_BIT_MUSK (0x00000200) -#define USB_SUB_GROUP_2_WAKEUP_BY_VBUS_BIT_MUSK (0x00000400) -#define USB_SUB_GROUP_3_VDMA_CMPLT_CXF_BIT_MUSK (0x00000001) -#define USB_SUB_GROUP_3_VDMA_CMPLT_F0_BIT_MUSK (0x00000002) -#define USB_SUB_GROUP_3_VDMA_CMPLT_F1_BIT_MUSK (0x00000004) -#define USB_SUB_GROUP_3_VDMA_CMPLT_F2_BIT_MUSK (0x00000008) -#define USB_SUB_GROUP_3_VDMA_CMPLT_F3_BIT_MUSK (0x00000010) -#define USB_SUB_GROUP_3_VDMA_ERROR_CXF_BIT_MUSK (0x00010000) -#define USB_SUB_GROUP_3_VDMA_ERROR_F0_BIT_MUSK (0x00020000) -#define USB_SUB_GROUP_3_VDMA_ERROR_F1_BIT_MUSK (0x00040000) -#define USB_SUB_GROUP_3_VDMA_ERROR_F2_BIT_MUSK (0x00080000) -#define USB_SUB_GROUP_3_VDMA_ERROR_F3_BIT_MUSK (0x00100000) -#define USB_SUB_GROUP_4_L1_BIT_MUSK (0x00000001) - -/*@} end of group USB_Public_Macros */ - -/** @defgroup USB_Public_Functions - * @{ - */ - -/** - * @brief USB Functions - */ -BL_Err_Type USB_Set_Normal_Config(USB_NORMAL_Cfg_Type *cfg); -BL_Err_Type USB_SOF_Mask_Time_HighSpeed(void); -BL_Err_Type USB_SOF_Mask_Time_FullSpeed(void); -BL_Err_Type USB_SoftDetach_Enable(void); -BL_Err_Type USB_SoftDetach_Disable(void); -USB_DEVICE_SPEED_Type USB_Get_Device_Speed_Status(void); -BL_Err_Type USB_Go_Suspend(uint8_t enable); -BL_Err_Type USB_Set_Device_Address(uint8_t addr); -uint8_t USB_Get_Device_Address(void); -BL_Err_Type USB_Non_Ctrl_Transfer_Enable(void); -BL_Err_Type USB_Non_Ctrl_Transfer_Disable(void); -BL_Err_Type USB_Clear_CTRL_FIFO(void); -BL_Sts_Type USB_Is_CTRL_FIFO_Empty(void); -BL_Sts_Type USB_Is_CTRL_FIFO_Full(void); -BL_Err_Type USB_Clear_FIFO(void); -BL_Err_Type USB_Reset_FIFO(USB_FIFO_Type fifoID); -BL_Sts_Type USB_Is_FIFO_Empty(USB_FIFO_EMPTY_Type fifoNum); -BL_Err_Type USB_Set_FIFO_Of_Endpoint_IN(USB_Endpoint_Type epID, USB_FIFO_Type fifoID); -BL_Err_Type USB_Set_FIFO_Of_Endpoint_OUT(USB_Endpoint_Type epID, USB_FIFO_Type fifoID); -BL_Err_Type USB_Set_FIFO_Config(USB_FIFO_Type fifoID, USB_FIFO_Cfg_Type *cfg); -uint16_t USB_Get_OUT_FIFO_Count(USB_FIFO_Type fifoID); -BL_Err_Type USB_Set_Endpoint_IN_MaxPacketSize(USB_Endpoint_Type epID, uint16_t max); -BL_Err_Type USB_Set_Endpoint_OUT_MaxPacketSize(USB_Endpoint_Type epID, uint16_t max); -BL_Err_Type USB_Set_CTRL_Endpoint_Stall_Once(void); -BL_Err_Type USB_Set_Endpoint_IN_Stall(USB_Endpoint_Type epID, uint8_t enable); -BL_Err_Type USB_Set_Endpoint_OUT_Stall(USB_Endpoint_Type epID, uint8_t enable); -BL_Err_Type USB_CTRL_Endpoint_Data_Transfer_Done(void); -BL_Sts_Type USB_Is_Endpoint_Receive_Zero_Length_Packet(USB_Endpoint_Type epID); -BL_Err_Type USB_Clear_Endpoint_Receive_Zero_Length_Packet_Status(USB_Endpoint_Type epID); -BL_Err_Type USB_Reset_Endpoint_IN_Data_Toggle_Sequence(USB_Endpoint_Type epID); -BL_Err_Type USB_Reset_Endpoint_OUT_Data_Toggle_Sequence(USB_Endpoint_Type epID); -BL_Err_Type USB_Endpoint_Transmit_Zero_Length_Packet(USB_Endpoint_Type epID); -BL_Sts_Type USB_Is_Endpoint_Transfer_Zero_Length_Packet(USB_Endpoint_Type epID); -BL_Err_Type USB_Clear_Endpoint_Transfer_Zero_Length_Packet_Status(USB_Endpoint_Type epID); -BL_Err_Type USB_Get_Setup_Command(uint32_t setup[2]); -void USB_Reset_DMA_Accessing_Fifo(void); -BL_Err_Type USB_Update_DMA_Trans(uint32_t memAddr, uint32_t length); -BL_Err_Type USB_Set_DMA_Config(USB_DMA_TARGET_FIFO_Type fifoN, USB_DMA_Cfg_Type *cfg); -BL_Err_Type USB_Set_DMA_Start(void); -BL_Err_Type USB_Set_VDMA_Config(USB_VDMA_TARGET_FIFO_Type fifoN, USB_VDMA_Cfg_Type *cfg); -BL_Err_Type USB_Set_VDMA_Start(USB_VDMA_TARGET_FIFO_Type fifoN); -BL_Sts_Type USB_Get_VDMA_Start(USB_VDMA_TARGET_FIFO_Type fifoN); -BL_Err_Type USB_Set_VDMA_Enable(void); -BL_Err_Type USB_Set_LPM_Config(USB_LPM_Cfg_Type *cfg); -uint8_t USB_Get_LPM_BESL(void); -/*----------*/ -BL_Err_Type USB_Set_Suspend_Delay(uint8_t ms); -/*----------*/ -BL_Err_Type USB_Global_IntEnable(uint8_t enable); -BL_Err_Type USB_Global_IntMask(USB_GLOBAL_INT_Type intType, BL_Mask_Type intMask); -BL_Sts_Type USB_Global_IntStatus(USB_GLOBAL_INT_Type intType); -/*----------*/ -BL_Err_Type USB_Group_IntMask(USB_GRP_INT_Type intType, BL_Mask_Type intMask); -BL_Sts_Type USB_Group_IntStatus(USB_GRP_INT_Type intType); -/*----------*/ -BL_Err_Type USB_Sub_Group_IntMask(uint64_t intType); -BL_Err_Type USB_Sub_Group_IntUnmask(uint64_t intType); -/*----------*/ -uint32_t USB_Get_Sub_Group_0_IntStatus(void); -uint32_t USB_Get_Sub_Group_1_IntStatus(void); -uint32_t USB_Get_Sub_Group_2_IntStatus(void); -uint32_t USB_Get_Sub_Group_3_IntStatus(void); -uint32_t USB_Get_Sub_Group_4_IntStatus(void); -uint32_t USB_Get_Sub_Group_0_IntMask(void); -uint32_t USB_Get_Sub_Group_1_IntMask(void); -uint32_t USB_Get_Sub_Group_2_IntMask(void); -uint32_t USB_Get_Sub_Group_3_IntMask(void); -uint32_t USB_Get_Sub_Group_4_IntMask(void); -BL_Err_Type USB_Get_Sub_Group_0_IntClear(uint32_t clrVal); -BL_Err_Type USB_Get_Sub_Group_1_IntClear(uint32_t clrVal); -BL_Err_Type USB_Get_Sub_Group_2_IntClear(uint32_t clrVal); -BL_Err_Type USB_Get_Sub_Group_3_IntClear(uint32_t clrVal); -BL_Err_Type USB_Get_Sub_Group_4_IntClear(uint32_t clrVal); -/*----------*/; - -/*@} end of group USB_Public_Functions */ - -/*@} end of group USB */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_USB_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_acomp.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_acomp.c deleted file mode 100644 index bb4dfe39eb..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_acomp.c +++ /dev/null @@ -1,209 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_acomp.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_acomp.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup ACOMP - * @{ - */ - -/** @defgroup ACOMP_Private_Macros - * @{ - */ - -/*@} end of group ACOMP_Private_Macros */ - -/** @defgroup ACOMP_Private_Types - * @{ - */ - -/*@} end of group ACOMP_Private_Types */ - -/** @defgroup ACOMP_Private_Variables - * @{ - */ - -/*@} end of group ACOMP_Private_Variables */ - -/** @defgroup ACOMP_Global_Variables - * @{ - */ - -/*@} end of group ACOMP_Global_Variables */ - -/** @defgroup ACOMP_Private_Fun_Declaration - * @{ - */ - -/*@} end of group ACOMP_Private_Fun_Declaration */ - -/** @defgroup ACOMP_Private_Functions - * @{ - */ - -/*@} end of group ACOMP_Private_Functions */ - -/** @defgroup ACOMP_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Analog compare init - * - * @param acompNo: Compare ID - * @param cfg: Compare consideration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type AON_ACOMP_Init(AON_ACOMP_ID_Type acompNo, AON_ACOMP_CFG_Type *cfg) -{ - uint32_t tmpVal = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_AON_ACOMP_ID_TYPE(acompNo)); - - if (acompNo == AON_ACOMP0_ID) { - /* Disable ACOMP first */ - tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP0_CTRL); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_ACOMP0_EN); - tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP0_CTRL, tmpVal); - - /* Set ACOMP config */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_MUXEN, cfg->muxEn); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_POS_SEL, cfg->posChanSel); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_NEG_SEL, cfg->negChanSel); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_LEVEL_SEL, cfg->scalingFactor); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_BIAS_PROG, cfg->biasProg); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_HYST_SELP, cfg->hysteresisPosVolt); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_HYST_SELN, cfg->hysteresisNegVolt); - - tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP0_CTRL, tmpVal); - } else { - /* Disable ACOMP first */ - tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP1_CTRL); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_ACOMP1_EN); - tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP1_CTRL, tmpVal); - - /* Set ACOMP config */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_MUXEN, cfg->muxEn); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_POS_SEL, cfg->posChanSel); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_NEG_SEL, cfg->negChanSel); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_LEVEL_SEL, cfg->scalingFactor); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_BIAS_PROG, cfg->biasProg); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_HYST_SELP, cfg->hysteresisPosVolt); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_HYST_SELN, cfg->hysteresisNegVolt); - - tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP1_CTRL, tmpVal); - } - - tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP_CTRL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP_VREF_SEL, cfg->vioSel); - tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP_CTRL, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Analog compare enable - * - * @param acompNo: Compare ID - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type AON_ACOMP_Enable(AON_ACOMP_ID_Type acompNo) -{ - uint32_t tmpVal = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_AON_ACOMP_ID_TYPE(acompNo)); - - if (acompNo == AON_ACOMP0_ID) { - tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP0_CTRL); - tmpVal = BL_SET_REG_BIT(tmpVal, AON_ACOMP0_EN); - tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP0_CTRL, tmpVal); - } else { - tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP1_CTRL); - tmpVal = BL_SET_REG_BIT(tmpVal, AON_ACOMP1_EN); - tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP1_CTRL, tmpVal); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Analog compare enable - * - * @param acompNo: Compare ID - * - * @return SET or RESET - * -*******************************************************************************/ -BL_Sts_Type AON_ACOMP_Get_Result(AON_ACOMP_ID_Type acompNo) -{ - uint32_t tmpVal = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_AON_ACOMP_ID_TYPE(acompNo)); - - tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP_CTRL); - - /* Disable ACOMP first */ - if (acompNo == AON_ACOMP0_ID) { - if (BL_IS_REG_BIT_SET(tmpVal, AON_ACOMP0_OUT_RAW)) { - return SET; - } else { - return RESET; - } - } else { - if (BL_IS_REG_BIT_SET(tmpVal, AON_ACOMP1_OUT_RAW)) { - return SET; - } else { - return RESET; - } - } -} - -/*@} end of group ACOMP_Public_Functions */ - -/*@} end of group ACOMP */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_adc.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_adc.c deleted file mode 100644 index 0226b9d705..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_adc.c +++ /dev/null @@ -1,1487 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_adc.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_adc.h" -#include "bl808_ef_ctrl.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup ADC - * @{ - */ - -/** @defgroup ADC_Private_Macros - * @{ - */ -#undef MSG -#define MSG(...) -#define AON_CLK_SET_DUMMY_WAIT \ - { \ - __NOP(); \ - __NOP(); \ - __NOP(); \ - __NOP(); \ - __NOP(); \ - __NOP(); \ - __NOP(); \ - __NOP(); \ - } -#define ADC_RESTART_DUMMY_WAIT arch_delay_us(100) - -/*@} end of group ADC_Private_Macros */ - -/** @defgroup ADC_Private_Types - * @{ - */ - -/*@} end of group ADC_Private_Types */ - -/** @defgroup ADC_Private_Variables - * @{ - */ -static intCallback_Type *adcIntCbfArra[ADC_INT_ALL] = { NULL }; -static ADC_Gain_Coeff_Type adcGainCoeffCal = { - .adcGainCoeffEnable = DISABLE, - .adcgainCoeffVal = 0, - .coe = 1, -}; - -/*@} end of group ADC_Private_Variables */ - -/** @defgroup ADC_Global_Variables - * @{ - */ - -/*@} end of group ADC_Global_Variables */ - -/** @defgroup ADC_Private_Fun_Declaration - * @{ - */ - -/*@} end of group ADC_Private_Fun_Declaration */ - -/** @defgroup ADC_Private_Functions - * @{ - */ - -/*@} end of group ADC_Private_Functions */ - -/** @defgroup ADC_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Software reset the whole ADC - * - * @param None - * - * @return None - * -*******************************************************************************/ -void ADC_Reset(void) -{ - uint32_t regCmd; - - /* reset ADC */ - regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, BL_SET_REG_BIT(regCmd, AON_GPADC_SOFT_RST)); - AON_CLK_SET_DUMMY_WAIT; - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, BL_CLR_REG_BIT(regCmd, AON_GPADC_SOFT_RST)); -} - -/****************************************************************************/ /** - * @brief ADC glable enable - * - * @param None - * - * @return None - * -*******************************************************************************/ -void ADC_Enable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_GLOBAL_EN); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); -} - -/****************************************************************************/ /** - * @brief ADC glable disable - * - * @param None - * - * @return None - * -*******************************************************************************/ -void ADC_Disable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_GLOBAL_EN); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); -} - -/****************************************************************************/ /** - * @brief ADC normal mode init - * - * @param cfg: ADC normal mode configuration - * - * @return None - * -*******************************************************************************/ -void ADC_Init(ADC_CFG_Type *cfg) -{ - uint32_t regCfg1; - uint32_t regCfg2; - uint32_t regCalib; - uint32_t regCmd; - - CHECK_PARAM(IS_ADC_V18_SEL_TYPE(cfg->v18Sel)); - CHECK_PARAM(IS_ADC_V11_SEL_TYPE(cfg->v11Sel)); - CHECK_PARAM(IS_ADC_CLK_TYPE(cfg->clkDiv)); - CHECK_PARAM(IS_ADC_PGA_GAIN_TYPE(cfg->gain1)); - CHECK_PARAM(IS_ADC_PGA_GAIN_TYPE(cfg->gain2)); - CHECK_PARAM(IS_ADC_CHOP_MOD_TYPE(cfg->chopMode)); - CHECK_PARAM(IS_ADC_BIAS_SEL_TYPE(cfg->biasSel)); - CHECK_PARAM(IS_ADC_PGA_VCM_TYPE(cfg->vcm)); - CHECK_PARAM(IS_ADC_VREF_TYPE(cfg->vref)); - CHECK_PARAM(IS_ADC_SIG_INPUT_TYPE(cfg->inputMode)); - CHECK_PARAM(IS_ADC_DATA_WIDTH_TYPE(cfg->resWidth)); - - /* config 1 */ - regCfg1 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG1); - regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_V18_SEL, cfg->v18Sel); - regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_V11_SEL, cfg->v11Sel); - regCfg1 = BL_CLR_REG_BIT(regCfg1, AON_GPADC_DITHER_EN); - regCfg1 = BL_CLR_REG_BIT(regCfg1, AON_GPADC_SCAN_EN); - regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_SCAN_LENGTH, 0); - regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_CLK_DIV_RATIO, cfg->clkDiv); - regCfg1 = BL_CLR_REG_BIT(regCfg1, AON_GPADC_CLK_ANA_INV); - regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_CAL_OS_EN, cfg->offsetCalibEn); - regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_RES_SEL, cfg->resWidth); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG1, regCfg1); - AON_CLK_SET_DUMMY_WAIT; - - /* config 2 */ - regCfg2 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); - regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_DLY_SEL, 0x02); - regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_PGA1_GAIN, cfg->gain1); - regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_PGA2_GAIN, cfg->gain2); - regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_BIAS_SEL, cfg->biasSel); - regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_CHOP_MODE, cfg->chopMode); - /* pga_vcmi_en is for mic */ - regCfg2 = BL_CLR_REG_BIT(regCfg2, AON_GPADC_PGA_VCMI_EN); - - if ((cfg->gain1 != ADC_PGA_GAIN_NONE) || (cfg->gain2 != ADC_PGA_GAIN_NONE)) { - regCfg2 = BL_SET_REG_BIT(regCfg2, AON_GPADC_PGA_EN); - } else { - regCfg2 = BL_CLR_REG_BIT(regCfg2, AON_GPADC_PGA_EN); - } - - /* pga_os_cal is for mic */ - regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_PGA_OS_CAL, 8); - regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_PGA_VCM, cfg->vcm); - regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_VREF_SEL, cfg->vref); - regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_DIFF_MODE, cfg->inputMode); - - BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, regCfg2); - - /* mic2 diff enable */ - regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - regCmd = BL_SET_REG_BIT(regCmd, AON_GPADC_MIC2_DIFF); - if (cfg->inputMode == ADC_INPUT_SINGLE_END) { - regCmd = BL_SET_REG_BIT(regCmd, AON_GPADC_NEG_GND); - } else { - regCmd = BL_CLR_REG_BIT(regCmd, AON_GPADC_NEG_GND); - } - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd); - - /* calibration offset */ - regCalib = BL_RD_REG(AON_BASE, AON_GPADC_REG_DEFINE); - regCalib = BL_SET_REG_BITS_VAL(regCalib, AON_GPADC_OS_CAL_DATA, cfg->offsetCalibVal); - BL_WR_REG(AON_BASE, AON_GPADC_REG_DEFINE, regCalib); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(GPADC_DMA_IRQn, GPADC_DMA_IRQHandler); -#endif - - ADC_Gain_Trim(); -} - -/****************************************************************************/ /** - * @brief ADC normal mode channel config - * - * @param posCh: ADC pos channel type - * @param negCh: ADC neg channel type - * @param contEn: ENABLE or DISABLE continuous mode - * - * @return None - * -*******************************************************************************/ -void ADC_Channel_Config(ADC_Chan_Type posCh, ADC_Chan_Type negCh, BL_Fun_Type contEn) -{ - uint32_t regCmd; - uint32_t regCfg1; - - CHECK_PARAM(IS_AON_ADC_CHAN_TYPE(posCh)); - CHECK_PARAM(IS_AON_ADC_CHAN_TYPE(negCh)); - - /* set channel */ - regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - regCmd = BL_SET_REG_BITS_VAL(regCmd, AON_GPADC_POS_SEL, posCh); - regCmd = BL_SET_REG_BITS_VAL(regCmd, AON_GPADC_NEG_SEL, negCh); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd); - - /* set continuous mode */ - regCfg1 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG1); - regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_CONT_CONV_EN, contEn); - regCfg1 = BL_CLR_REG_BIT(regCfg1, AON_GPADC_SCAN_EN); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG1, regCfg1); -} - -/****************************************************************************/ /** - * @brief ADC scan mode channel config - * - * @param posChList[]: ADC pos channel list type - * @param negChList[]: ADC neg channel list type - * @param scanLength: ADC scan length - * @param contEn: ENABLE or DISABLE continuous mode - * - * @return None - * -*******************************************************************************/ -void ADC_Scan_Channel_Config(ADC_Chan_Type posChList[], ADC_Chan_Type negChList[], uint8_t scanLength, BL_Fun_Type contEn) -{ - uint32_t tmpVal, i; - uint32_t dealLen; - - CHECK_PARAM((scanLength < 13)); - - /* Deal with the first 6 */ - dealLen = 6; - - if (scanLength < dealLen) { - dealLen = scanLength; - } - - /* Set first 6 scan channels */ - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_SCN_POS1); - - for (i = 0; i < dealLen; i++) { - tmpVal = tmpVal & (~(0x1F << (i * 5))); - tmpVal |= (posChList[i] << (i * 5)); - } - - BL_WR_REG(AON_BASE, AON_GPADC_REG_SCN_POS1, tmpVal); - - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_SCN_NEG1); - - for (i = 0; i < dealLen; i++) { - tmpVal = tmpVal & (~(0x1F << (i * 5))); - tmpVal |= (negChList[i] << (i * 5)); - } - - BL_WR_REG(AON_BASE, AON_GPADC_REG_SCN_NEG1, tmpVal); - - /* Set the left channels */ - if (scanLength > dealLen) { - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_SCN_POS2); - - for (i = 0; i < scanLength - dealLen; i++) { - tmpVal = tmpVal & (~(0x1F << (i * 5))); - tmpVal |= (posChList[i + dealLen] << (i * 5)); - } - - BL_WR_REG(AON_BASE, AON_GPADC_REG_SCN_POS2, tmpVal); - - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_SCN_NEG2); - - for (i = 0; i < scanLength - dealLen; i++) { - tmpVal = tmpVal & (~(0x1F << (i * 5))); - tmpVal |= (negChList[i + dealLen] << (i * 5)); - } - - BL_WR_REG(AON_BASE, AON_GPADC_REG_SCN_NEG2, tmpVal); - } - - /* Scan mode */ - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_SCAN_LENGTH, scanLength - 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_CONT_CONV_EN, contEn); - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_CLK_ANA_INV); - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_SCAN_EN); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG1, tmpVal); -} - -/****************************************************************************/ /** - * @brief ADC normal mode convert start - * - * @param None - * - * @return None - * -*******************************************************************************/ -void ADC_Start(void) -{ - uint32_t regCmd; - - /* disable convert start */ - regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - regCmd = BL_CLR_REG_BIT(regCmd, AON_GPADC_CONV_START); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd); - - ADC_RESTART_DUMMY_WAIT; - - /* enable convert start */ - regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - regCmd = BL_SET_REG_BIT(regCmd, AON_GPADC_CONV_START); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd); -} - -/****************************************************************************/ /** - * @brief ADC normal mode convert stop - * - * @param None - * - * @return None - * -*******************************************************************************/ -void ADC_Stop(void) -{ - uint32_t regCmd; - - /* disable convert start */ - regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - regCmd = BL_CLR_REG_BIT(regCmd, AON_GPADC_CONV_START); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd); -} - -/****************************************************************************/ /** - * @brief ADC FIFO configuration - * - * @param fifoCfg: ADC FIFO confifuration pointer - * - * @return None - * -*******************************************************************************/ -void ADC_FIFO_Cfg(ADC_FIFO_Cfg_Type *fifoCfg) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_GPIP_ADC_FIFO_THRESHOLD_TYPE(fifoCfg->fifoThreshold)); - - /* - * DMA enable : ,When the fifo data is exceeded to fifoThreshold DMA request will occur - * DMA disable : fifoThreshold determine how many data will raise FIFO ready interrupt - */ - - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPADC_FIFO_THL, fifoCfg->fifoThreshold); - - /* Enable DMA */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPADC_DMA_EN, fifoCfg->dmaEn); - - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief ADC get DMA FIFO data count - * - * @param None - * - * @return data count in FIFO - * -*******************************************************************************/ -uint8_t ADC_Get_FIFO_Count(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - - return BL_GET_REG_BITS_VAL(tmpVal, GPIP_GPADC_FIFO_DATA_COUNT); -} - -/****************************************************************************/ /** - * @brief ADC get DMA FIFO full status - * - * @param None - * - * @return SET or RESET - * -*******************************************************************************/ -BL_Sts_Type ADC_FIFO_Is_Full(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - - if (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_FULL)) { - return SET; - } else { - return RESET; - } -} - -/****************************************************************************/ /** - * @brief ADC get DMA FIFO empty status - * - * @param None - * - * @return SET or RESET - * -*******************************************************************************/ -BL_Sts_Type ADC_FIFO_Is_Empty(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - - if (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_NE)) { - return RESET; - } else { - return SET; - } -} - -/****************************************************************************/ /** - * @brief ADC read DMA FIFO data - * - * @param None - * - * @return ADC result if return 0 that means this is error data,user should ignore this data. - * -*******************************************************************************/ -uint32_t ADC_Read_FIFO(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_DMA_RDATA); - - return (tmpVal); -} - -/****************************************************************************/ /** - * @brief ADC parse result - * - * @param orgVal: Original A to D value - * @param len: Original AD vaule count - * @param result: Final Result array pointer - * - * @return None - * -*******************************************************************************/ -void ADC_Parse_Result(uint32_t *orgVal, uint32_t len, ADC_Result_Type *result) -{ - uint8_t neg = 0; - uint32_t tmpVal1 = 0, tmpVal2 = 0; - ADC_Data_Width_Type dataType; - ADC_SIG_INPUT_Type sigType; - float ref = 2.0; - uint32_t i = 0; - - float coe = 1.0; - - if (adcGainCoeffCal.adcGainCoeffEnable) { - coe = adcGainCoeffCal.coe; - } - - tmpVal1 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG1); - tmpVal2 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); - dataType = BL_GET_REG_BITS_VAL(tmpVal1, AON_GPADC_RES_SEL); - sigType = BL_GET_REG_BITS_VAL(tmpVal2, AON_GPADC_DIFF_MODE); - - if (BL_GET_REG_BITS_VAL(tmpVal2, AON_GPADC_VREF_SEL) == ADC_VREF_3P2V) { - ref = 3.2; - } - - if (sigType == ADC_INPUT_SINGLE_END) { - for (i = 0; i < len; i++) { - result[i].posChan = orgVal[i] >> 21; - result[i].negChan = -1; - - if (dataType == ADC_DATA_WIDTH_12) { - result[i].value = (unsigned int)(((orgVal[i] & 0xffff) >> 4) / coe); - result[i].volt = result[i].value / 4096.0 * ref; - } else if ((dataType == ADC_DATA_WIDTH_14_WITH_16_AVERAGE) || - (dataType == ADC_DATA_WIDTH_14_WITH_64_AVERAGE)) { - result[i].value = (unsigned int)(((orgVal[i] & 0xffff) >> 2) / coe); - result[i].volt = result[i].value / 16384.0 * ref; - } else if ((dataType == ADC_DATA_WIDTH_16_WITH_128_AVERAGE) || - (dataType == ADC_DATA_WIDTH_16_WITH_256_AVERAGE)) { - result[i].value = (unsigned int)((orgVal[i] & 0xffff) / coe); - result[i].volt = result[i].value / 65536.0 * ref; - } - } - } else { - for (i = 0; i < len; i++) { - neg = 0; - result[i].posChan = orgVal[i] >> 21; - result[i].negChan = (orgVal[i] >> 16) & 0x1F; - - if (orgVal[i] & 0x8000) { - orgVal[i] = ~orgVal[i]; - orgVal[i] += 1; - neg = 1; - } - - if (dataType == ADC_DATA_WIDTH_12) { - result[i].value = (unsigned int)(((orgVal[i] & 0xffff) >> 4) / coe); - result[i].volt = result[i].value / 2048.0 * ref; - } else if ((dataType == ADC_DATA_WIDTH_14_WITH_16_AVERAGE) || - (dataType == ADC_DATA_WIDTH_14_WITH_64_AVERAGE)) { - result[i].value = (unsigned int)(((orgVal[i] & 0xffff) >> 2) / coe); - result[i].volt = result[i].value / 8192.0 * ref; - } else if ((dataType == ADC_DATA_WIDTH_16_WITH_128_AVERAGE) || - (dataType == ADC_DATA_WIDTH_16_WITH_256_AVERAGE)) { - result[i].value = (unsigned int)((orgVal[i] & 0xffff) / coe); - result[i].volt = result[i].value / 32768.0 * ref; - } - - if (neg) { - result[i].volt = -result[i].volt; - } - } - } -} - -/****************************************************************************/ /** - * @brief ADC mask or unmask certain or all interrupt - * - * @param intType: interrupt type - * @param intMask: mask or unmask - * - * @return None - * -*******************************************************************************/ -BL_Mask_Type ADC_IntGetMask(ADC_INT_Type intType) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType)); - CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); - - switch (intType) { - case ADC_INT_POS_SATURATION: - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); - return BL_IS_REG_BIT_SET(tmpVal, AON_GPADC_POS_SATUR_MASK); - break; - - case ADC_INT_NEG_SATURATION: - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); - return BL_IS_REG_BIT_SET(tmpVal, AON_GPADC_NEG_SATUR_MASK); - break; - - case ADC_INT_FIFO_UNDERRUN: - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - return BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_MASK); - break; - - case ADC_INT_FIFO_OVERRUN: - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - return BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_OVERRUN_MASK); - break; - - case ADC_INT_ADC_READY: - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - return BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_RDY_MASK); - break; - - default: - break; - } - return 0; -} - -/****************************************************************************/ /** - * @brief ADC mask or unmask certain or all interrupt - * - * @param intType: interrupt type - * @param intMask: mask or unmask - * - * @return None - * -*******************************************************************************/ -void ADC_IntMask(ADC_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType)); - CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); - - switch (intType) { - case ADC_INT_POS_SATURATION: - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); - - if (intMask == UNMASK) { - /* Enable this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_MASK); - } else { - /* Disable this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_MASK); - } - - BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); - break; - - case ADC_INT_NEG_SATURATION: - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); - - if (intMask == UNMASK) { - /* Enable this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_MASK); - } else { - /* Disable this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_MASK); - } - - BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); - break; - - case ADC_INT_FIFO_UNDERRUN: - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - - if (intMask == UNMASK) { - /* Enable this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_MASK); - } else { - /* Disable this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_MASK); - } - - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - break; - - case ADC_INT_FIFO_OVERRUN: - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - - if (intMask == UNMASK) { - /* Enable this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_MASK); - } else { - /* Disable this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_MASK); - } - - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - break; - - case ADC_INT_ADC_READY: - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - - if (intMask == UNMASK) { - /* Enable this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_MASK); - } else { - /* Disable this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_RDY_MASK); - } - - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - break; - - case ADC_INT_ALL: - if (intMask == UNMASK) { - /* Enable this interrupt */ - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_MASK); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_MASK); - BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); - - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_MASK); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_MASK); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_MASK); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - } else { - /* Disable this interrupt */ - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_MASK); - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_MASK); - BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); - - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_MASK); - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_MASK); - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_RDY_MASK); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - } - - break; - - default: - break; - } -} - -/****************************************************************************/ /** - * @brief ADC clear certain or all interrupt - * - * @param intType: interrupt type - * - * @return None - * -*******************************************************************************/ -void ADC_IntClr(ADC_INT_Type intType) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType)); - - switch (intType) { - case ADC_INT_POS_SATURATION: - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR); - BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); - - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR); - BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); - - /*Manual reset*/ - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR); - BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); - - break; - - case ADC_INT_NEG_SATURATION: - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR); - BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); - - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR); - BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); - - /*Manual reset*/ - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR); - BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); - - break; - - case ADC_INT_FIFO_UNDERRUN: - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - /*Manual reset*/ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - break; - - case ADC_INT_FIFO_OVERRUN: - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - /*Manual reset*/ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - break; - - case ADC_INT_ADC_READY: - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - /*Manual reset*/ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - break; - - case ADC_INT_ALL: - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR); - BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); - - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR); - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR); - BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); - - /*Manual reset*/ - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR); - BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); - - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR); - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR); - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - /*Manual reset*/ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - break; - - default: - break; - } -} - -/****************************************************************************/ /** - * @brief ADC get interrupt status - * - * @param intType: interrupt type - * - * @return SET or RESET - * -*******************************************************************************/ -BL_Sts_Type ADC_GetIntStatus(ADC_INT_Type intType) -{ - uint32_t tmpVal; - BL_Sts_Type bitStatus = RESET; - - /* Check the parameters */ - CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType)); - - switch (intType) { - case ADC_INT_POS_SATURATION: - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); - bitStatus = (BL_IS_REG_BIT_SET(tmpVal, AON_GPADC_POS_SATUR)) ? SET : RESET; - break; - - case ADC_INT_NEG_SATURATION: - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); - bitStatus = (BL_IS_REG_BIT_SET(tmpVal, AON_GPADC_NEG_SATUR)) ? SET : RESET; - break; - - case ADC_INT_FIFO_UNDERRUN: - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - bitStatus = (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_UNDERRUN)) ? SET : RESET; - break; - - case ADC_INT_FIFO_OVERRUN: - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - bitStatus = (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_OVERRUN)) ? SET : RESET; - break; - - case ADC_INT_ADC_READY: - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - bitStatus = (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_RDY)) ? SET : RESET; - break; - - case ADC_INT_ALL: - break; - - default: - break; - } - - return bitStatus; -} - -/****************************************************************************/ /** - * @brief ADC install interrupt callback - * - * @param intType: ADC interrupt type - * @param cbFun: ADC interrupt callback - * - * @return None - * -*******************************************************************************/ -void ADC_Int_Callback_Install(ADC_INT_Type intType, intCallback_Type *cbFun) -{ - /* Check the parameters */ - CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType)); - - adcIntCbfArra[intType] = cbFun; -} - -/****************************************************************************/ /** - * @brief ADC DMA interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void GPADC_DMA_IRQHandler(void) -{ - if (ADC_IntGetMask(ADC_INT_POS_SATURATION) == UNMASK && ADC_GetIntStatus(ADC_INT_POS_SATURATION) == SET) { - ADC_IntClr(ADC_INT_POS_SATURATION); - - if (adcIntCbfArra[ADC_INT_POS_SATURATION] != NULL) { - adcIntCbfArra[ADC_INT_POS_SATURATION](); - } - } - - if (ADC_IntGetMask(ADC_INT_NEG_SATURATION) == UNMASK && ADC_GetIntStatus(ADC_INT_NEG_SATURATION) == SET) { - ADC_IntClr(ADC_INT_NEG_SATURATION); - - if (adcIntCbfArra[ADC_INT_NEG_SATURATION] != NULL) { - adcIntCbfArra[ADC_INT_NEG_SATURATION](); - } - } - - if (ADC_IntGetMask(ADC_INT_FIFO_UNDERRUN) == UNMASK && ADC_GetIntStatus(ADC_INT_FIFO_UNDERRUN) == SET) { - ADC_IntClr(ADC_INT_FIFO_UNDERRUN); - - if (adcIntCbfArra[ADC_INT_FIFO_UNDERRUN] != NULL) { - adcIntCbfArra[ADC_INT_FIFO_UNDERRUN](); - } - } - - if (ADC_IntGetMask(ADC_INT_FIFO_OVERRUN) == UNMASK && ADC_GetIntStatus(ADC_INT_FIFO_OVERRUN) == SET) { - ADC_IntClr(ADC_INT_FIFO_OVERRUN); - - if (adcIntCbfArra[ADC_INT_FIFO_OVERRUN] != NULL) { - adcIntCbfArra[ADC_INT_FIFO_OVERRUN](); - } - } - - if (ADC_IntGetMask(ADC_INT_ADC_READY) == UNMASK && ADC_GetIntStatus(ADC_INT_ADC_READY) == SET) { - ADC_IntClr(ADC_INT_ADC_READY); - - if (adcIntCbfArra[ADC_INT_ADC_READY] != NULL) { - adcIntCbfArra[ADC_INT_ADC_READY](); - } - } -} -#endif - -/****************************************************************************/ /** - * @brief ADC VBAT enable - * - * @param None - * - * @return None - * -*******************************************************************************/ -void ADC_Vbat_Enable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_VBAT_EN); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); -} - -/****************************************************************************/ /** - * @brief ADC VBAT disable - * - * @param None - * - * @return None - * -*******************************************************************************/ -void ADC_Vbat_Disable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_VBAT_EN); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); -} - -/****************************************************************************/ /** - * @brief ADC TSEN Config - * - * @param tsenMod: None - * - * @return None - * -*******************************************************************************/ -void ADC_Tsen_Init(ADC_TSEN_MOD_Type tsenMod) -{ - uint32_t tmpVal; - - CHECK_PARAM(IS_AON_ADC_TSEN_MOD_TYPE(type)); - - /* config gpadc_reg_cmd */ - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - /* enable sensor dc test mux*/ - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_SEN_TEST_EN); - /*selected sen output current channel*/ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_SEN_SEL, 0); - /* enable chip sensor*/ - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_CHIP_SEN_PU); - /*dwa_en */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_DWA_EN, 1); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); - - /* config 2 */ - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); - /*tsvbe low=0*/ - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_TSVBE_LOW); - /*dly_sel=2*/ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_DLY_SEL, 2); - /*test_sel=0*/ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_TEST_SEL, 0); - /*test_en=0*/ - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_TEST_EN); - /*ts_en*/ - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_TS_EN); - /*select tsen ext or inner*/ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_TSEXT_SEL, tsenMod); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_PGA_VCM, 2); - /*pga vcmi enable*/ - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_PGA_VCMI_EN); - /*0:512uS;1:16mS;2:32mS;3:64mS*/ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_PGA_OS_CAL, 0); - - BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); - - /* config 3 */ - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG1); - /* set gpadc_dither_en */ - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_DITHER_EN); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG1, tmpVal); - - /* set 4000F90C[19](gpadc_mic2_diff) = 1 - * debug advise form Ran - * 2020.08.26 - */ - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_MIC2_DIFF, 1); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); -} - -/****************************************************************************/ /** - * @brief ADC TSEN Enable - * - * @return None - * -*******************************************************************************/ -void ADC_Tsen_Enable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_TS_EN); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); -} - -/****************************************************************************/ /** - * @brief ADC TSEN Disable - * - * @return None - * -*******************************************************************************/ -void ADC_Tsen_Disable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_TS_EN); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); -} - -/****************************************************************************/ /** - * @brief ADC Clear fifo - * - * @return None - * -*******************************************************************************/ -void ADC_FIFO_Clear(void) -{ - uint32_t tmpVal; - - /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief config pga - * - * @param pga_vcmi_enable: enable or not vcmi - * @param pga_os_cal: pga os cal value - * @return None - * -*******************************************************************************/ -void ADC_PGA_Config(uint8_t pga_vcmi_enable, uint8_t pga_os_cal) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); - - if (pga_vcmi_enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_PGA_VCMI_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_PGA_VCMI_EN); - } - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_PGA_OS_CAL, pga_os_cal); - - BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); -} -/****************************************************************************/ /** - * @brief TSEN_Get_V_Error - * - * @param None - * - * @return None - * -*******************************************************************************/ -uint32_t TSEN_Get_V_Error(void) -{ - uint32_t v0 = 0, v1 = 0; - uint32_t v_error = 0; - uint32_t regVal = 0; - ADC_Result_Type result; - uint32_t tmpVal; - uint8_t gainCalEnabled = 0; - - /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - ADC_SET_TSVBE_LOW(); - - ADC_Start(); - - while (ADC_Get_FIFO_Count() == 0) - ; - - regVal = ADC_Read_FIFO(); - gainCalEnabled = adcGainCoeffCal.adcGainCoeffEnable; - adcGainCoeffCal.adcGainCoeffEnable = 0; - ADC_Parse_Result(®Val, 1, &result); - adcGainCoeffCal.adcGainCoeffEnable = gainCalEnabled; - v0 = result.value; - - /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - ADC_SET_TSVBE_HIGH(); - - ADC_Start(); - - while (ADC_Get_FIFO_Count() == 0) - ; - - regVal = ADC_Read_FIFO(); - gainCalEnabled = adcGainCoeffCal.adcGainCoeffEnable; - adcGainCoeffCal.adcGainCoeffEnable = 0; - ADC_Parse_Result(®Val, 1, &result); - adcGainCoeffCal.adcGainCoeffEnable = gainCalEnabled; - v1 = result.value; - - v_error = v0 - v1; - - return v_error; -} - -/****************************************************************************/ /** - * @brief Trim TSEN - * - * @param tsen_offset: None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION ADC_Trim_TSEN(uint16_t *tsen_offset) -{ - Efuse_TSEN_Refcode_Corner_Type trim; - - EF_Ctrl_Read_TSEN_Trim(&trim); - if (trim.tsenRefcodeCornerEn) { - if (trim.tsenRefcodeCornerParity == EF_Ctrl_Get_Trim_Parity(trim.tsenRefcodeCorner, 12)) { - *tsen_offset = trim.tsenRefcodeCorner; - - return SUCCESS; - } - } - - return ERROR; -} - -/****************************************************************************/ /** - * @brief SET ADC TSEN TSVBE LOW/HIGH - * - * @param None - * - * @return None - * -*******************************************************************************/ -void ADC_SET_TSVBE_LOW(void) -{ - uint32_t tmpVal; - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_TSVBE_LOW); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); -} - -/****************************************************************************/ /** - * @brief SET ADC TSEN TSVBE LOW/HIGH - * - * @param None - * - * @return None - * -*******************************************************************************/ -void ADC_SET_TSVBE_HIGH(void) -{ - uint32_t tmpVal; - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_TSVBE_LOW); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); -} - -/****************************************************************************/ /** - * @brief SET ADC TSEN TSVBE LOW/HIGH - * - * @param tsen_offset: tsen_offset form efuse trim data - * - * @return tempture - * -*******************************************************************************/ -float TSEN_Get_Temp(uint32_t tsen_offset) -{ - uint32_t v0 = 0, v1 = 0; - float temp = 0; - uint32_t regVal = 0; - ADC_Result_Type result; - uint32_t tmpVal; - uint8_t gainCalEnabled = 0; - - /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - ADC_SET_TSVBE_LOW(); - - ADC_Start(); - - while (ADC_Get_FIFO_Count() == 0) - ; - - regVal = ADC_Read_FIFO(); - - gainCalEnabled = adcGainCoeffCal.adcGainCoeffEnable; - adcGainCoeffCal.adcGainCoeffEnable = 0; - ADC_Parse_Result(®Val, 1, &result); - adcGainCoeffCal.adcGainCoeffEnable = gainCalEnabled; - v0 = result.value; - - /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - ADC_SET_TSVBE_HIGH(); - - ADC_Start(); - - while (ADC_Get_FIFO_Count() == 0) - ; - - regVal = ADC_Read_FIFO(); - gainCalEnabled = adcGainCoeffCal.adcGainCoeffEnable; - adcGainCoeffCal.adcGainCoeffEnable = 0; - ADC_Parse_Result(®Val, 1, &result); - adcGainCoeffCal.adcGainCoeffEnable = gainCalEnabled; - v1 = result.value; - - if (v0 > v1) { - temp = (((float)v0 - (float)v1) - (float)tsen_offset) / 7.753; - } else { - temp = (((float)v1 - (float)v0) - (float)tsen_offset) / 7.753; - } - - return temp; -} - -/****************************************************************************/ /** - * @brief ADC MIC Config - * - * @param adc_mic_config: adc_mic_config - * - * @return success or not - * -*******************************************************************************/ -BL_Err_Type ADC_Mic_Init(ADC_MIC_Type *adc_mic_config) -{ - uint32_t tmpVal1 = 0, tmpVal2 = 0; - - CHECK_PARAM(IS_ADC_MICBOOST_DB_Type(adc_mic_config->micboostDb)); - CHECK_PARAM(IS_PGA2_GAIN_Type(adc_mic_config->micPga2Gain)); - CHECK_PARAM(IS_ADC_MIC_MODE_Type(adc_mic_config->mic1Mode)); - CHECK_PARAM(IS_ADC_MIC_MODE_Type(adc_mic_config->mic2Mode)); - CHECK_PARAM(IS_BL_Fun_Type(adc_mic_config->dwaEn)); - CHECK_PARAM(IS_BL_Fun_Type(adc_mic_config->micboostBypassEn)); - CHECK_PARAM(IS_BL_Fun_Type(adc_mic_config->micPgaEn)); - CHECK_PARAM(IS_BL_Fun_Type(adc_mic_config->micBiasEn)); - - tmpVal2 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); - - tmpVal1 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MICBOOST_32DB_EN, adc_mic_config->micboostDb); - tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MIC_PGA2_GAIN, adc_mic_config->micPga2Gain); - tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MIC1_DIFF, adc_mic_config->mic1Mode); - tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MIC2_DIFF, adc_mic_config->mic2Mode); - tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_DWA_EN, adc_mic_config->dwaEn); - tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_BYP_MICBOOST, adc_mic_config->micboostBypassEn); - - if (BL_IS_REG_BIT_SET(tmpVal2, AON_GPADC_PGA_EN) && adc_mic_config->micPgaEn == ENABLE) { - /* 0x4000F914[13] and 0x4000F90c[15] Cannot be both Enable*/ - return ERROR; - } else { - tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MICPGA_EN, adc_mic_config->micPgaEn); - } - - tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MICBIAS_EN, adc_mic_config->micBiasEn); - - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal1); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief ADC MIC bias control - * - * @param None - * - * @return None - * -*******************************************************************************/ -void ADC_MIC_Bias_Enable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_MICBIAS_EN); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); -} - -/****************************************************************************/ /** - * @brief ADC MIC bias control - * - * @param None - * - * @return None - * -*******************************************************************************/ -void ADC_MIC_Bias_Disable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_MICBIAS_EN); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); -} - -/****************************************************************************/ /** - * @brief Trim ADC Gain - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION ADC_Gain_Trim(void) -{ - Efuse_ADC_Gain_Coeff_Type trim; - uint32_t tmp; - - EF_Ctrl_Read_ADC_Gain_Trim(&trim); - - if (trim.adcGainCoeffEn) { - if (trim.adcGainCoeffParity == EF_Ctrl_Get_Trim_Parity(trim.adcGainCoeff, 12)) { - adcGainCoeffCal.adcGainCoeffEnable = ENABLE; - adcGainCoeffCal.adcgainCoeffVal = trim.adcGainCoeff; - tmp = adcGainCoeffCal.adcgainCoeffVal; - - if (tmp & 0x800) { - tmp = ~tmp; - tmp += 1; - tmp = tmp & 0xfff; - //printf("val==%08x\r\n",(unsigned int)tmp); - adcGainCoeffCal.coe = (1.0 + ((float)tmp / 2048.0)); - //printf("coe==%0f\r\n",adcGainCoeffCal.coe); - } else { - adcGainCoeffCal.coe = (1.0 - ((float)tmp / 2048.0)); - //printf("coe==%0f\r\n",adcGainCoeffCal.coe); - } - - return SUCCESS; - } - } - - return ERROR; -} - -/*@} end of group ADC_Public_Functions */ - -/*@} end of group ADC */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_audio.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_audio.c deleted file mode 100644 index ed3e902940..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_audio.c +++ /dev/null @@ -1,2814 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_audio.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_audio.h" -#include "audio_reg.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup AUDIO - * @{ - */ - -/** @defgroup AUDIO_Private_Macros - * @{ - */ - -/*@} end of group AUDIO_Private_Macros */ - -/** @defgroup AUDIO_Private_Types - * @{ - */ - -/*@} end of group AUDIO_Private_Types */ - -/** @defgroup AUDIO_Private_Variables - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -static intCallback_Type *audioIntCbfArra[AUDIO_INT_NUM_ALL] = { NULL }; -#endif -/*@} end of group AUDIO_Private_Variables */ - -/** @defgroup AUDIO_Global_Variables - * @{ - */ - -/*@} end of group AUDIO_Global_Variables */ - -/** @defgroup AUDIO_Private_Fun_Declaration - * @{ - */ - -/*@} end of group AUDIO_Private_Fun_Declaration */ - -/** @defgroup AUDIO_Private_Functions - * @{ - */ - -/*@} end of group AUDIO_Private_Functions */ - -/** @defgroup AUDIO_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Select Tx channel source Defaule is tx0-dac_0,tx1-dac_1 - * - * @param tx_channel: tx_channel index . Note tx_channel <=2 - * @param dac_id: tx[rx_channel] conect to dac_id - * - * @return Success or not - * -*******************************************************************************/ -BL_Err_Type Audio_Tx_Source_DAC_Sel(uint8_t tx_channel, Audio_DAC_ID_Type dac_id) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_DAC_ID_TYPE(dac_id)); - - if (tx_channel > 2) { - return ERROR; - /*tx channel sel can not larger than 2*/ - } - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_AUD_ITF); - - if (tx_channel == 0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AUD_TX0_SEL, dac_id); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AUD_TX1_SEL, dac_id); - } - - BL_WR_REG(AUDIO_BASE, AUDIO_AUD_ITF, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Select Rx channel form ADC Channel . source Default selction is - * rx0-adc_0,rx1-adc_1,rx2-adc_2,rx3-aec_0,rx4-aec_1 - * - * @param rx_channel: rx_channel index . Note tx_channel <=4 - * @param adc_id: rx[rx_channel] conect to adc_id - * - * @return Success or not - * -*******************************************************************************/ -BL_Err_Type Audio_Rx_Source_ADC_Sel(uint8_t rx_channel, Audio_ADC_ID_Type adc_id) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(adc_id)); - - if (rx_channel > 4) { - return ERROR; - /*rx channel sel can not larger than 4*/ - } - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_AUD_ITF); - - switch (rx_channel) { - case 0: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AUD_RX0_SEL, adc_id); - break; - case 1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AUD_RX1_SEL, adc_id); - break; - case 2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AUD_RX2_SEL, adc_id); - break; - case 3: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AUD_RX3_SEL, adc_id); - break; - case 4: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AUD_RX4_SEL, adc_id); - break; - default: - break; - } - - BL_WR_REG(AUDIO_BASE, AUDIO_AUD_ITF, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Select Rx channel form AEC Channel . source Default selction is - * rx0-adc_0,rx1-adc_1,rx2-adc_2,rx3-aec_0,rx4-aec_1 - * - * @param rx_channel: tx_channel index . Note tx_channel <=4 - * @param aec_id: rx[rx_channel] conect to aec_id - * - * @return Success or not - * -*******************************************************************************/ -BL_Err_Type Audio_Rx_Source_AEC_Sel(uint8_t rx_channel, Audio_AEC_ID_Type aec_id) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_AEC_ID_TYPE(aec_id)); - - if (rx_channel > 4) { - return ERROR; - /*rx channel sel can not larger than 4*/ - } - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_AUD_ITF); - - switch (rx_channel) { - case 0: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AUD_RX0_SEL, aec_id + 3); - break; - case 1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AUD_RX1_SEL, aec_id + 3); - break; - case 2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AUD_RX2_SEL, aec_id + 3); - break; - case 3: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AUD_RX3_SEL, aec_id + 3); - break; - case 4: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AUD_RX4_SEL, aec_id + 3); - break; - default: - break; - } - - BL_WR_REG(AUDIO_BASE, AUDIO_AUD_ITF, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Audio Set HPF Parameter - * - * @param id: ADC ID - * @param k1_enable: k1 parameter enable - * @param k1: k1 parameter in range 4 bit - * @param k2_enable: k2 parameter enable - * @param k2: k1 parameter in range 4 bit - * - * @return None - * -*******************************************************************************/ -void Audio_Set_HPF_Parameter(Audio_ADC_ID_Type id, uint8_t k1_enable, uint8_t k1, uint8_t k2_enable, uint8_t k2) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(id)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_ADC_1); - - switch (id) { - case AUDIO_ADC_0: - if (k1_enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_ADC_0_K1_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_0_K1, k1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_ADC_0_K1_EN); - } - if (k2_enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_ADC_0_K2_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_0_K2, k2); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_ADC_0_K2_EN); - } - break; - case AUDIO_ADC_1: - if (k1_enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_ADC_1_K1_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_1_K1, k1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_ADC_1_K1_EN); - } - if (k2_enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_ADC_1_K2_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_1_K2, k2); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_ADC_1_K2_EN); - } - break; - case AUDIO_ADC_2: - if (k1_enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_ADC_2_K1_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_2_K1, k1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_ADC_2_K1_EN); - } - - if (k2_enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_ADC_2_K2_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_2_K2, k2); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_ADC_2_K2_EN); - } - break; - default: - break; - } - - BL_WR_REG(AUDIO_BASE, AUDIO_ADC_1, tmpVal); -} - -/****************************************************************************/ /** - * @brief Audio Set ADC Source PDM or Analog - * - * @param id: k1 parameter in range 4 bit ,when k0=0 k0 parameter will disabled - * @param adc_source: k2 parameter in range 4 bit ,when k1=0 k1 parameter will disabled - * - * @return None - * -*******************************************************************************/ -void Audio_Set_ADC_Source(Audio_ADC_ID_Type id, Audio_ADC_Source_Type adc_source) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(id)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_0); - - if (id == AUDIO_ADC_0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_0_SRC, adc_source); - } else if (id == AUDIO_ADC_1) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_1_SRC, adc_source); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_2_SRC, adc_source); - } - - BL_WR_REG(AUDIO_BASE, AUDIO_DAC_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief Audio AEC enable - * - * @param id: Auido AEC ID - * - * @return None - * -*******************************************************************************/ -void Audio_AEC_Enable(Audio_AEC_ID_Type id) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_AEC_ID_TYPE(id)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_AUD_ITF); - if (id == AUDIO_AEC_0) { - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_AEC_0_EN); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_AEC_1_EN); - } - BL_WR_REG(AUDIO_BASE, AUDIO_AUD_ITF, tmpVal); -} - -/****************************************************************************/ /** - * @brief Audio AEC disable - * - * @param id: Auido AEC ID - * - * @return None - * -*******************************************************************************/ -void Audio_AEC_Disable(Audio_AEC_ID_Type id) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_AEC_ID_TYPE(id)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_AUD_ITF); - if (id == AUDIO_AEC_0) { - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_AEC_0_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_AEC_1_EN); - } - BL_WR_REG(AUDIO_BASE, AUDIO_AUD_ITF, tmpVal); -} - -/****************************************************************************/ /** - * @brief Audio ADC enable - * - * @param id: Auido ADC ID - * - * @return None - * -*******************************************************************************/ -void Audio_ADC_Enable(Audio_ADC_ID_Type id) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(id)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_AUD_ITF); - if (id == AUDIO_ADC_0) { - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_ADC_0_EN); - } else if (id == AUDIO_ADC_1) { - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_ADC_1_EN); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_ADC_2_EN); - } - BL_WR_REG(AUDIO_BASE, AUDIO_AUD_ITF, tmpVal); -} - -/****************************************************************************/ /** - * @brief Audio ADC disable - * - * @param id: Auido ADC ID - * - * @return None - * -*******************************************************************************/ -void Audio_ADC_Disable(Audio_ADC_ID_Type id) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(id)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_AUD_ITF); - if (id == AUDIO_ADC_0) { - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_ADC_0_EN); - } else if (id == AUDIO_ADC_1) { - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_ADC_1_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_ADC_2_EN); - } - BL_WR_REG(AUDIO_BASE, AUDIO_AUD_ITF, tmpVal); -} - -/****************************************************************************/ /** - * @brief Audio DAC disable - * - * @param id: Auido DAC ID - * - * @return None - * -*******************************************************************************/ -void Audio_DAC_Enable(Audio_DAC_ID_Type id) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_DAC_ID_TYPE(id)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_AUD_ITF); - if (id == AUDIO_DAC_0) { - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_DAC_0_EN); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_DAC_1_EN); - } - BL_WR_REG(AUDIO_BASE, AUDIO_AUD_ITF, tmpVal); -} - -/****************************************************************************/ /** - * @brief Audio DAC disable - * - * @param id: Auido DAC ID - * - * @return None - * -*******************************************************************************/ -void Audio_DAC_Disable(Audio_DAC_ID_Type id) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_DAC_ID_TYPE(id)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_AUD_ITF); - if (id == AUDIO_DAC_0) { - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_DAC_0_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_DAC_1_EN); - } - BL_WR_REG(AUDIO_BASE, AUDIO_AUD_ITF, tmpVal); -} - -/****************************************************************************/ /** - * @brief set dac amp - * - * @param enable: enable or noy - * @param amp: amp - * - * @return None - * -*******************************************************************************/ -void Audio_Set_DAC_Dither(uint8_t enable, uint8_t amp) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_1); - - if (enable) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_DSM_DITHER_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_DSM_DITHER_AMP, amp); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_DSM_DITHER_EN, 0); - } - - BL_WR_REG(AUDIO_BASE, AUDIO_DAC_1, tmpVal); -} - -/****************************************************************************/ /** - * @brief set dac scaling - * - * @param enable: enable or noy - * @param scaling: scaling - * - * @return None - * -*******************************************************************************/ -void Audio_Set_DAC_Scaling(uint8_t enable, uint8_t scaling) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_1); - if (enable) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_DSM_SCALING_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_DSM_SCALING_FACTOR, scaling); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_DSM_SCALING_EN, 0); - } - BL_WR_REG(AUDIO_BASE, AUDIO_DAC_1, tmpVal); -} - -/****************************************************************************/ /** - * @brief set order - * - * @param order: order - * - * @return None - * -*******************************************************************************/ -void Audio_Set_DAC_Order(Audio_DAC_Order_Type order) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_DAC_ORDER_TYPE(order)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_DSM_ORDER, order); - BL_WR_REG(AUDIO_BASE, AUDIO_DAC_1, tmpVal); -} - -/****************************************************************************/ /** - * @brief Audio_Set_DAC_Dwa_Swap - * - * @param swap: None - * - * @return None - * -*******************************************************************************/ -void Audio_Set_DAC_Dwa_Swap(uint8_t swap) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_DEM_OUT_SWAP, swap); - BL_WR_REG(AUDIO_BASE, AUDIO_DAC_1, tmpVal); -} - -/****************************************************************************/ /** - * @brief Audio_Set_DAC_Dsm_Bypass - * - * @param bypass: None - * - * @return None - * -*******************************************************************************/ -void Audio_Set_DAC_Dwa_Bypass(uint8_t bypass) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_DEM_BYPASS, bypass); - BL_WR_REG(AUDIO_BASE, AUDIO_DAC_1, tmpVal); -} - -/****************************************************************************/ /** - * @brief Audio set adc lfsr - * - * @param lfsrType: Auido ADC LFSR TYPE - * - * @return None - * -*******************************************************************************/ -void Audio_Set_DAC_LFSR(Audio_LFSR_Type lfsrType) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_ADC_LFSR_TYPE(lfsrType)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_ADC_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_LFSR_MODE, lfsrType); - BL_WR_REG(AUDIO_BASE, AUDIO_ADC_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief read LSFR - * - * @param None - * - * @return read LSFR out - * -*******************************************************************************/ -BL_Sts_Type Audio_Get_ADC_LFSR(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_ADC_0); - return BL_IS_REG_BIT_SET(tmpVal, AUDIO_ADC_DITHER_DATA); -} - -/****************************************************************************/ /** - * @brief set adc scaling value - * - * @param id: Auido ADC ID - * @param scalingVal: scaling value - * - * @return None - * -*******************************************************************************/ -void Audio_Set_ADC_Scaling_Value(Audio_ADC_ID_Type id, uint8_t scalingVal) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(id)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_ADC_0); - - if (id == AUDIO_ADC_0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_0_SCAL, scalingVal); - } else if (id == AUDIO_ADC_1) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_1_SCAL, scalingVal); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_2_SCAL, scalingVal); - } - BL_WR_REG(AUDIO_BASE, AUDIO_ADC_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief set fir mode - * - * @param id: Auido ADC ID - * @param enable: enable or disable - * - * @return None - * -*******************************************************************************/ -void Audio_Set_Fir_Mode(Audio_ADC_ID_Type id, uint8_t enable) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(id)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_ADC_0); - - if (id == AUDIO_ADC_0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_0_FIR_MODE, enable); - } else if (id == AUDIO_ADC_1) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_1_FIR_MODE, enable); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_2_FIR_MODE, enable); - } - BL_WR_REG(AUDIO_BASE, AUDIO_ADC_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief mixer setting function - * - * @param enable: enbale mixer or not,if disable mixer then other parameter is invalid - * @param mixerId: mixer Id,audio have two mixer to selected - * @param mode: mixer mode selection , debug mode or sidetone mode(other source is come form - * adc0-adc2) - * @param sidetoneChannel: mixer adc channel selection , if debug mode is selected this paramter is - * used , or user must select which adc source will be mixed with dac output. - * @param Volume: mixer Volume select - * - * @return None - * -*******************************************************************************/ -void Audio_Set_Mixer_Mode(uint8_t enable, Audio_Mixer_ID_Type mixerId, Audio_Mixer_Mode mode, Audio_ADC_ID_Type sidetoneChannel, Audio_Mixer_Volume_Type Volume) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_MIXER_ID_TYPE(sidetoneChannel)); - CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(sidetoneChannel)); - CHECK_PARAM(IS_AUDIO_MIXER_VOLUME_TYPE(Volume)); - CHECK_PARAM(IS_AUDIO_MIXER_MODE(mode)); - - if (mixerId == AUDIO_MIXER_ID_0) { - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_0); - } else { - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_1); - } - - if (enable) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_MIX_0_MODE, mode); - if (mode == AUDIO_SECOND_DEBUG_MODE) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_MIX_0_ATT_MODE1, Volume); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_MIX_0_SEL, sidetoneChannel + 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_MIX_0_ATT_MODE2, Volume); - } - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_MIX_0_MODE, 0); - } - - if (mixerId == AUDIO_MIXER_ID_0) { - BL_WR_REG(AUDIO_BASE, AUDIO_DAC_0, tmpVal); - } else { - BL_WR_REG(AUDIO_BASE, AUDIO_DAC_1, tmpVal); - } -} - -/****************************************************************************/ /** - * @brief set adc swap - * - * @param id: Auido ADC ID - * @param swap: swap - * - * @return None - * -*******************************************************************************/ -void Audio_ADC_Mash_Bit_Swap(Audio_ADC_ID_Type id, uint8_t swap) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(id)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_0); - if (id == AUDIO_ADC_0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_0_MASH_BIT_SWAP, swap); - } else if (id == AUDIO_ADC_1) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_1_MASH_BIT_SWAP, swap); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_2_MASH_BIT_SWAP, swap); - } - BL_WR_REG(AUDIO_BASE, AUDIO_DAC_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief set pdm inv - * - * @param id: Auido ADC ID - * @param swap: inv - * - * @return None - * -*******************************************************************************/ -void Audio_ADC_PDM_Inv_Swap(Audio_ADC_ID_Type id, uint8_t swap) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(id)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_0); - if (id == AUDIO_ADC_0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_1_PDM_LVL_SWAP, swap); - } else if (id == AUDIO_ADC_1) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_1_PDM_LVL_SWAP, swap); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_1_PDM_LVL_SWAP, swap); - } - BL_WR_REG(AUDIO_BASE, AUDIO_DAC_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief set pdm value - * - * @param pdm_l: pdm l - * @param pdm_h: pdm h - * - * @return None - * -*******************************************************************************/ -void Audio_ADC_Set_PDM_Value(uint8_t pdm_l, uint8_t pdm_h) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_PDM_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_PDM_L, pdm_l); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_PDM_H, pdm_l); - BL_WR_REG(AUDIO_BASE, AUDIO_PDM_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief Audio_Set_AEC_Record_Vid - * - * @param enable: enable or not - * @param div: div - * - * @return None - * -*******************************************************************************/ -void Audio_Set_AEC_Record_Vid(uint8_t enable, uint8_t div) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_AEC_0); - - if (enable) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AEC_RECORD_VLD_4S_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AEC_RECORD_VLD_4S_DIV, div); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AEC_RECORD_VLD_4S_EN, 0); - } - - BL_WR_REG(AUDIO_BASE, AUDIO_AEC_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief Audio_Set_AEC_Atten_mode - * - * @param aec_id: AEC ID - * @param mode: Atten Mode - * - * @return None - * -*******************************************************************************/ -void Audio_Set_AEC_Atten_mode(Audio_AEC_ID_Type aec_id, Audio_AEC_Atten_Mode mode) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_AEC_ID_TYPE(aec_id)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_AEC_0); - - if (aec_id == AUDIO_AEC_0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AEC_0_ATTEN_MODE, mode); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AEC_1_ATTEN_MODE, mode); - } - - BL_WR_REG(AUDIO_BASE, AUDIO_AEC_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief Audio support three channel for pdm .Meanwhile Audio support two DMIC Interface which - * supporting four pdm data source input.This function is used to select channel with pdm - * source. - * - * @param id: pdm channel,cannot be larger than 3 - * @param pdmSel: pdm source select - * - * @return Success or not - * -*******************************************************************************/ -void Audio_ADC_PDM_Channel_Sel(Audio_PDM_ID_Type id, Audio_PDM_Source_Type pdmSel) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_PDM_SOURCE_TYPE(pdmSel)); - CHECK_PARAM(IS_AUDIO_PDM_ID_TYPE(id)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_PDM_0); - - if (id == AUDIO_PDM_0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_0_PDM_SEL, pdmSel); - } else if (id == AUDIO_PDM_1) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_1_PDM_SEL, pdmSel); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_2_PDM_SEL, pdmSel); - } - BL_WR_REG(AUDIO_BASE, AUDIO_PDM_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief Audio Enable PDM - * - * @param id: PDM ID - * - * @return Success or not - * -*******************************************************************************/ -void Audio_ADC_PDM_Enable(Audio_PDM_ID_Type id) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_PDM_ID_TYPE(id)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_PDM_0); - - if (id == AUDIO_PDM_0) { - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_PDM_0_EN); - } else if (id == AUDIO_PDM_1) { - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_PDM_1_EN); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_PDM_2_EN); - } - BL_WR_REG(AUDIO_BASE, AUDIO_PDM_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief Audio Disable PDM - * - * @param id: None - * - * @return Success or not - * -*******************************************************************************/ -void Audio_ADC_PDM_Disable(Audio_PDM_ID_Type id) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_PDM_ID_TYPE(id)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_PDM_0); - - if (id == AUDIO_PDM_0) { - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_PDM_0_EN); - } else if (id == AUDIO_PDM_1) { - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_PDM_0_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_PDM_0_EN); - } - BL_WR_REG(AUDIO_BASE, AUDIO_PDM_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief debug 0x24 reigister - * - * @param wCmd: None - * - * @return None - * -*******************************************************************************/ -void Debug0_Write(uint32_t wCmd) -{ - BL_WR_REG(AUDIO_BASE, AUDIO_DBG_0, wCmd); -} - -/****************************************************************************/ /** - * @brief debug 0x28 reigister - * - * @param None - * - * @return None - * -*******************************************************************************/ -uint32_t Debug1_Read(void) -{ - return BL_RD_REG(AUDIO_BASE, AUDIO_DBG_1); -} - -/****************************************************************************/ /** - * @brief debug 0x2c reigister - * - * @param wCmd: None - * - * @return None - * -*******************************************************************************/ -void Debug2_Write(uint32_t wCmd) -{ - BL_WR_REG(AUDIO_BASE, AUDIO_DBG_2, wCmd); -} - -/****************************************************************************/ /** - * @brief debug 0x30 reigister - * - * @param wCmd: None - * - * @return None - * -*******************************************************************************/ -void Debug3_Write(uint32_t wCmd) -{ - BL_WR_REG(AUDIO_BASE, AUDIO_DBG_3, wCmd); -} - -/****************************************************************************/ /** - * @brief AUDIO Interrupt mask - * - * @param intType: intType - * @param intMask: intMask - * - * @return None - * -*******************************************************************************/ -void Auido_IntMask(Audio_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_INT_TYPE(intType)); - CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); - - switch (intType) { - case AUDIO_INT_RX_FIFO_THR: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL); - if (intMask) { - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_RXA_INT_EN); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_RXA_INT_EN); - } - BL_WR_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL, tmpVal); - break; - case AUDIO_INT_RX_FIFO_OVERRUN: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL); - if (intMask) { - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_RXO_INT_EN); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_RXO_INT_EN); - } - BL_WR_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL, tmpVal); - break; - case AUDIO_INT_RX_FIFO_UNDERRUN: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL); - if (intMask) { - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_RXU_INT_EN); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_RXU_INT_EN); - } - BL_WR_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL, tmpVal); - break; - - case AUDIO_INT_TX_FIFO_THR: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL); - if (intMask) { - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_TXA_INT_EN); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_TXA_INT_EN); - } - BL_WR_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL, tmpVal); - break; - case AUDIO_INT_TX_FIFO_OVERRUN: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL); - if (intMask) { - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_TXO_INT_EN); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_TXO_INT_EN); - } - BL_WR_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL, tmpVal); - break; - case AUDIO_INT_TX_FIFO_UNDERRUN: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL); - if (intMask) { - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_TXU_INT_EN); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_TXU_INT_EN); - } - BL_WR_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL, tmpVal); - break; - - case AUDIO_INT_ADC0_SET_VOLUME_DONE: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_INT_CLR, intMask); - BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal); - break; - case AUDIO_INT_ADC1_SET_VOLUME_DONE: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS); - tmpVal = BL_SET_REG_BITS_VAL(AUDIO_BASE, AUDIO_ADC_S1_INT_CLR, intMask); - BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal); - break; - - case AUDIO_INT_ADC2_SET_VOLUME_DONE: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S2_INT_CLR, intMask); - BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal); - break; - case AUDIO_INT_DAC0_SET_VOLUME_DONE: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_INT_CLR, intMask); - BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal); - break; - case AUDIO_INT_DAC1_SET_VOLUME_DONE: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S1_INT_CLR, intMask); - BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal); - break; - case AUDIO_INT_VAD: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_INT_CLR, intMask); - BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal); - break; - case AUDIO_INT_NUM_ALL: - if (intMask) { - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL); - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_RXA_INT_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_RXU_INT_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_RXO_INT_EN); - BL_WR_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL, tmpVal); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL); - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_TXA_INT_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_TXU_INT_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_TXO_INT_EN); - - BL_WR_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL, tmpVal); - - BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, 0x40A0A80); - } else { - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL); - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_RXA_INT_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_RXU_INT_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_RXO_INT_EN); - BL_WR_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL, tmpVal); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL); - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_TXA_INT_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_TXU_INT_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_TXO_INT_EN); - - BL_WR_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL, tmpVal); - - BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, 0); - } - - default: - break; - } -} - -/****************************************************************************/ /** - * @brief clear audio Interrupt flag - * - * @param intType: intType - * - * @return None - * -*******************************************************************************/ -void Auido_IntClear(Audio_INT_Type intType) -{ - uint32_t tmpVal = 0; - uint32_t tmpVal2 = 0; - - CHECK_PARAM(IS_AUDIO_INT_TYPE(intType)); - - switch (intType) { - case AUDIO_INT_RX_FIFO_THR: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_STATUS); - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_RXA_INT); - BL_WR_REG(AUDIO_BASE, AUDIO_RX_FIFO_STATUS, tmpVal); - break; - case AUDIO_INT_RX_FIFO_OVERRUN: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_STATUS); - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_RXO_INT); - BL_WR_REG(AUDIO_BASE, AUDIO_RX_FIFO_STATUS, tmpVal); - break; - case AUDIO_INT_RX_FIFO_UNDERRUN: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_STATUS); - tmpVal = BL_SET_REG_BIT(AUDIO_BASE, AUDIO_RXU_INT); - BL_WR_REG(AUDIO_BASE, AUDIO_RX_FIFO_STATUS, tmpVal); - break; - - case AUDIO_INT_TX_FIFO_THR: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_STATUS); - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_TXA_INT); - BL_WR_REG(AUDIO_BASE, AUDIO_TX_FIFO_STATUS, tmpVal); - break; - case AUDIO_INT_TX_FIFO_OVERRUN: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_STATUS); - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_TXO_INT); - BL_WR_REG(AUDIO_BASE, AUDIO_TX_FIFO_STATUS, tmpVal); - break; - case AUDIO_INT_TX_FIFO_UNDERRUN: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_STATUS); - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_TXU_INT); - BL_WR_REG(AUDIO_BASE, AUDIO_TX_FIFO_STATUS, tmpVal); - break; - - case AUDIO_INT_ADC0_SET_VOLUME_DONE: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS); - tmpVal2 = tmpVal; - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_INT_CLR, 1); - BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal); - - BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal2); - break; - case AUDIO_INT_ADC1_SET_VOLUME_DONE: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS); - tmpVal2 = tmpVal; - tmpVal = BL_SET_REG_BITS_VAL(AUDIO_BASE, AUDIO_ADC_S1_INT_CLR, 1); - BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal); - - BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal2); - break; - - case AUDIO_INT_ADC2_SET_VOLUME_DONE: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS); - tmpVal2 = tmpVal; - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S2_INT_CLR, 1); - BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal); - - BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal2); - break; - case AUDIO_INT_DAC0_SET_VOLUME_DONE: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS); - tmpVal2 = tmpVal; - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_INT_CLR, 1); - BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal); - - BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal2); - break; - case AUDIO_INT_DAC1_SET_VOLUME_DONE: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS); - tmpVal2 = tmpVal; - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S1_INT_CLR, 1); - BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal); - - BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal2); - break; - case AUDIO_INT_VAD: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS); - tmpVal2 = tmpVal; - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_INT_CLR, 1); - BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal); - - BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal2); - break; - case AUDIO_INT_NUM_ALL: - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_STATUS); - - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_RXA_INT); - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_RXU_INT); - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_RXO_INT); - - BL_WR_REG(AUDIO_BASE, AUDIO_RX_FIFO_STATUS, tmpVal); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_STATUS); - - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_TXA_INT); - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_TXU_INT); - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_TXO_INT); - - BL_WR_REG(AUDIO_BASE, AUDIO_TX_FIFO_STATUS, tmpVal); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS); - - BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal | 0x40A0A80); - BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal); - - default: - break; - } -} - -/****************************************************************************/ /** - * @brief register interrupt callback function pointer - * - * @param intType: intType - * @param cbFun: cbFun - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -BL_Err_Type Audio_Int_Callback_Install(Audio_INT_Type intType, intCallback_Type *cbFun) -{ - CHECK_PARAM(IS_AUDIO_INT_TYPE(intType)); - - audioIntCbfArra[intType] = cbFun; - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief read int flag - * - * @param intType: intType - * - * @return flag status - * -*******************************************************************************/ -BL_Sts_Type Audio_GetIntStatus(Audio_INT_Type intType) -{ - uint32_t tmpVal = 0; - BL_Sts_Type rlt = RESET; - - CHECK_PARAM(IS_AUDIO_INT_TYPE(intType)); - - switch (intType) { - case AUDIO_INT_RX_FIFO_THR: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_STATUS); - rlt = BL_IS_REG_BIT_SET(tmpVal, AUDIO_RXA_INT); - break; - case AUDIO_INT_RX_FIFO_OVERRUN: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_STATUS); - rlt = BL_IS_REG_BIT_SET(tmpVal, AUDIO_RXO_INT); - break; - case AUDIO_INT_RX_FIFO_UNDERRUN: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_STATUS); - rlt = BL_IS_REG_BIT_SET(tmpVal, AUDIO_RXU_INT); - break; - - case AUDIO_INT_TX_FIFO_THR: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_STATUS); - rlt = BL_IS_REG_BIT_SET(tmpVal, AUDIO_TXA_INT); - break; - case AUDIO_INT_TX_FIFO_OVERRUN: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_STATUS); - rlt = BL_IS_REG_BIT_SET(tmpVal, AUDIO_TXO_INT); - break; - case AUDIO_INT_TX_FIFO_UNDERRUN: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_STATUS); - rlt = BL_IS_REG_BIT_SET(tmpVal, AUDIO_TXU_INT); - break; - - case AUDIO_INT_ADC0_SET_VOLUME_DONE: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS); - rlt = BL_IS_REG_BIT_SET(tmpVal, AUDIO_ADC_S0_INT); - break; - case AUDIO_INT_ADC1_SET_VOLUME_DONE: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS); - rlt = BL_IS_REG_BIT_SET(tmpVal, AUDIO_ADC_S1_INT); - break; - - case AUDIO_INT_ADC2_SET_VOLUME_DONE: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS); - rlt = BL_IS_REG_BIT_SET(tmpVal, AUDIO_ADC_S2_INT); - break; - case AUDIO_INT_DAC0_SET_VOLUME_DONE: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS); - rlt = BL_IS_REG_BIT_SET(tmpVal, AUDIO_DAC_S0_INT); - break; - case AUDIO_INT_DAC1_SET_VOLUME_DONE: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS); - rlt = BL_IS_REG_BIT_SET(tmpVal, AUDIO_DAC_S1_INT); - break; - case AUDIO_INT_VAD: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS); - rlt = BL_IS_REG_BIT_SET(tmpVal, AUDIO_VAD_INT); - break; - default: - break; - } - - return rlt; -} - -/****************************************************************************/ /** - * @brief rx fifo flush - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Audio_RxFifoClear(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL); - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_RX_FIFO_FLUSH); - BL_WR_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL, tmpVal); -} - -/****************************************************************************/ /** - * @brief Get Rx FIFO Count - * - * @param None - * - * @return fifi count - * -*******************************************************************************/ -uint32_t Audio_GetRxFifoCount(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_STATUS); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, AUDIO_RXA_CNT); - - return tmpVal; -} - -/****************************************************************************/ /** - * @brief Read RX FIFO - * - * @param None - * - * @return fifo data - * -*******************************************************************************/ -uint32_t Audio_ReadRxFifo(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_DATA); - - return tmpVal; -} - -/****************************************************************************/ /** - * @brief tx fifo flush - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Audio_TxFifoClear(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL); - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_TX_FIFO_FLUSH); - BL_WR_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL, tmpVal); -} - -/****************************************************************************/ /** - * @brief Get Tx FIFO Count - * - * @param None - * - * @return fifi count - * -*******************************************************************************/ -uint32_t Audio_GetTxFifoCount(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_STATUS); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, AUDIO_TXA_CNT); - - return tmpVal; -} - -/****************************************************************************/ /** - * @brief Wirte TX FIFO - * - * @param da: None - * - * @return fifo data - * -*******************************************************************************/ -void Audio_WriteTxFifo(uint32_t da) -{ - BL_WR_REG(AUDIO_BASE, AUDIO_TX_FIFO_DATA, da); -} - -/****************************************************************************/ /** - * @brief Configure rx fifo - * - * @param cfg: fifo cfg - * - * @return None - * -*******************************************************************************/ -void Audio_RxFifoConfig(Audio_FifoCfg_Type *cfg) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_RESOLUTION_TYPE(cfg->resolution)); - CHECK_PARAM(IS_AUDIO_FIFO_AILGN_MODE(cfg->ailgnMode)); - CHECK_PARAM(IS_AUDIO_FIFO_DQR_THRESHOLD_MODE(cfg->dmaThresholdMode)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_RX_DATA_RES, cfg->resolution); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_RX_DATA_MODE, cfg->ailgnMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_RX_DRQ_CNT, cfg->dmaThresholdMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_RX_TRG_LEVEL, cfg->FifoIntThreshold); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_RX_DRQ_EN, cfg->dmaEn); - - BL_WR_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL, tmpVal); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_AUD_ITF); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_ITF_EN, cfg->dmaEn); - BL_WR_REG(AUDIO_BASE, AUDIO_AUD_ITF, tmpVal); -} - -/****************************************************************************/ /** - * @brief enable rx fifo - * - * @param ch: ch - * - * @return None - * -*******************************************************************************/ -void Audio_RxFifoEnable(uint8_t ch) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_RX_CH_EN, ch); - BL_WR_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL, tmpVal); -} - -/****************************************************************************/ /** - * @brief disable rx fifo - * - * @param ch: fifo cfg - * - * @return None - * -*******************************************************************************/ -void Audio_RxFifoDisable(uint8_t ch) -{ - uint32_t tmpVal = 0; - uint32_t tmpVal2 = 0; - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL); - tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, AUDIO_RX_CH_EN); - - tmpVal2 &= ~ch; - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_RX_CH_EN, tmpVal2); - - BL_WR_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL, tmpVal); -} - -/****************************************************************************/ /** - * @brief enable rx fifo - * - * @param ch: ch - * - * @return None - * -*******************************************************************************/ -void Audio_TxFifoEnable(uint8_t ch) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_TX_CH_EN, ch); - BL_WR_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL, tmpVal); -} - -/****************************************************************************/ /** - * @brief disable rx fifo - * - * @param ch: fifo cfg - * - * @return None - * -*******************************************************************************/ -void Audio_TxFifoDisable(uint8_t ch) -{ - uint32_t tmpVal = 0; - uint32_t tmpVal2 = 0; - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL); - tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, AUDIO_TX_CH_EN); - - tmpVal2 &= ~ch; - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_TX_CH_EN, tmpVal2); - - BL_WR_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL, tmpVal); -} - -/****************************************************************************/ /** - * @brief Get Tx FIFO Count - * - * @param cfg: None - * - * @return None - * -*******************************************************************************/ -void Audio_TxFifoConfig(Audio_FifoCfg_Type *cfg) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_RESOLUTION_TYPE(cfg->resolution)); - CHECK_PARAM(IS_AUDIO_FIFO_AILGN_MODE(cfg->ailgnMode)); - CHECK_PARAM(IS_AUDIO_FIFO_DQR_THRESHOLD_MODE(cfg->dmaThresholdMode)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_TX_DATA_RES, cfg->resolution); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_TX_DATA_MODE, cfg->ailgnMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_TX_DRQ_CNT, cfg->dmaThresholdMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_TX_TRG_LEVEL, cfg->FifoIntThreshold); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_TX_DRQ_EN, cfg->dmaEn); - - BL_WR_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL, tmpVal); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_AUD_ITF); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_ITF_EN, cfg->dmaEn); - BL_WR_REG(AUDIO_BASE, AUDIO_AUD_ITF, tmpVal); -} - -/****************************************************************************/ /** - * @brief Audio_PEQ_Config - * - * @param peq_index: PEQ index should be in range[0,19] - * @param peqBypass: PEQ is bypass,if bypass b_pra and a_pra is vaild - * @param qtfm: PEQ qtfm - * @param b_pra: PEQ b_pra ,should be set as [19:0] arrary pointer which length is 3 - * @param a_pra: PEQ a_bra ,should be set as [19:0] arrary pointer which length is 2 - * - * @return PEQ Setting is success or not - * -*******************************************************************************/ -BL_Err_Type Audio_DAC_PEQ_Config(uint8_t peq_index, uint8_t peqBypass, Audio_PEQ_QTFM_Type qtfm, uint32_t *b_pra, uint32_t *a_pra) -{ - uint32_t tmpVal = 0; - uint32_t peqAddr = 0; - if (peq_index > 19) { - return ERROR; - /* PEQ only support [0,19] index */ - } - peqAddr = AUDIO_BASE + 0x200 + (peq_index * 0x14); - - if (peqBypass == 0) { - tmpVal = BL_RD_WORD(peqAddr); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_PEQ_00_B0, b_pra[0]); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_PEQ_00_QFMT, qtfm); - - BL_WR_WORD(peqAddr, tmpVal); - - BL_WR_WORD(peqAddr + 0x04, b_pra[1]); - BL_WR_WORD(peqAddr + 0x08, b_pra[2]); - BL_WR_WORD(peqAddr + 0x0c, a_pra[0]); - BL_WR_WORD(peqAddr + 0x10, a_pra[1]); - - tmpVal = BL_RD_WORD(peqAddr); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_PEQ_00_BYP, peqBypass); - BL_WR_WORD(peqAddr, tmpVal); - - } else { - tmpVal = BL_RD_WORD(peqAddr); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_PEQ_00_BYP, peqBypass); - BL_WR_WORD(peqAddr, tmpVal); - } - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Audio_ADC_PEQ_Config - * - * @param peq_index: PEQ index should be in range[0,19] - * @param peqBypass: PEQ is bypass,if bypass b_pra and a_pra is vaild - * @param qtfm: PEQ qtfm - * @param b_pra: PEQ b_pra ,should be set as [19:0] arrary pointer which length is 3 - * @param a_pra: PEQ a_bra ,should be set as [19:0] arrary pointer which length is 2 - * - * @return PEQ Setting is success or not - * -*******************************************************************************/ -BL_Err_Type Audio_ADC_PEQ_Config(uint8_t peq_index, Audio_ADC_ID_Type adcChannel, uint8_t peqBypass, Audio_PEQ_QTFM_Type qtfm, uint32_t *b_pra, uint32_t *a_pra) -{ - uint32_t tmpVal = 0; - uint32_t peqAddr = 0; - if (peq_index > 19) { - return ERROR; - /* PEQ only support [0,19] index */ - } - peqAddr = AUDIO_BASE + 0x390 + (peq_index * 0x14); - - tmpVal = BL_RD_WORD(AUDIO_BASE + 0x390); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_PEQ_IN_SEL, adcChannel); - BL_WR_WORD(peqAddr, tmpVal); - - if (peqBypass == 0) { - tmpVal = BL_RD_WORD(peqAddr); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_PEQ_20_B0, b_pra[0]); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_PEQ_20_QFMT, qtfm); - - BL_WR_WORD(peqAddr, tmpVal); - - BL_WR_WORD(peqAddr + 0x04, b_pra[1]); - BL_WR_WORD(peqAddr + 0x08, b_pra[2]); - BL_WR_WORD(peqAddr + 0x0c, a_pra[0]); - BL_WR_WORD(peqAddr + 0x10, a_pra[1]); - - tmpVal = BL_RD_WORD(peqAddr); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_PEQ_20_BYP, peqBypass); - BL_WR_WORD(peqAddr, tmpVal); - - } else { - tmpVal = BL_RD_WORD(peqAddr); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_PEQ_20_BYP, peqBypass); - BL_WR_WORD(peqAddr, tmpVal); - } - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Audio adc Mute - * - * @param muteSyncAllAdc: mute Sync All ADC Channle - * @param adc_id: adc id - * @param mute: Mute Or Not - * - * @return success or not - * -*******************************************************************************/ -BL_Err_Type Audio_ADC_Set_Mute(BL_Fun_Type muteSyncAllAdc, Audio_ADC_ID_Type adc_id, Audio_Mute_Type mute) -{ - uint32_t tmpVal = 0; - uint32_t adcVolumeConfigAddrOffset = AUDIO_BASE + 0x408 + adc_id * 0x08; - - CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(adc_id)); - CHECK_PARAM(IS_AUDIO_MUTE_TYPE(mute)); - - if (muteSyncAllAdc) { - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_ADC_S0_MISC); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S012_MUTE, mute); - BL_WR_REG(AUDIO_BASE, AUDIO_ADC_S0_MISC, tmpVal); - } else { - if (adc_id > 2) { - return ERROR; - /*only support 3 adc*/ - } - - tmpVal = BL_RD_WORD(adcVolumeConfigAddrOffset); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_MUTE, mute); - BL_WR_WORD(adcVolumeConfigAddrOffset, tmpVal); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Audio adc Mute - * - * @param muteSyncAllDac: mute Sync All DAC Channle - * @param dac_id: dac id - * @param mute: Mute Or Not - * - * @return None - * -*******************************************************************************/ -BL_Err_Type Audio_DAC_Set_Mute(BL_Fun_Type muteSyncAllDac, Audio_DAC_ID_Type dac_id, Audio_Mute_Type mute) -{ - uint32_t tmpVal = 0; - uint32_t dacVolumeConfigAddrOffset = AUDIO_BASE + 0x434 + dac_id * 0x08; - - CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(dac_id)); - CHECK_PARAM(IS_AUDIO_MUTE_TYPE(Mute)); - - if (muteSyncAllDac) { - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_S0_MISC); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S01_MUTE, mute); - BL_WR_REG(AUDIO_BASE, AUDIO_DAC_S0_MISC, tmpVal); - } else { - if (dac_id > 1) { - return ERROR; - /*only support 2 dac*/ - } - - tmpVal = BL_RD_WORD(dacVolumeConfigAddrOffset); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_MUTE, mute); - BL_WR_WORD(dacVolumeConfigAddrOffset, tmpVal); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Audio adc Volume Config - * - * @param adc_id: adc id - * @param cfg: volume config cfg pointer - * - * @return None - * -*******************************************************************************/ -BL_Err_Type Audio_ADC_Software_Volume_Config(Audio_ADC_ID_Type adc_id, Audio_Volume_Cfg_Type *cfg) -{ - uint32_t adcVolumeConfigAddrOffset = AUDIO_BASE + 0x408 + adc_id * 0x08; - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(adc_id)); - CHECK_PARAM(IS_AUDIO_MUTE_MODE(cfg->muteMode)); - CHECK_PARAM(IS_AUDIO_RAMP_RATE_TYPE(cfg->muteRmpdnRate)); - CHECK_PARAM(IS_AUDIO_RAMP_RATE_TYPE(cfg->muteRmpupRate)); - CHECK_PARAM(IS_AUDIO_VOLUME_CTR_MODE(cfg->volumeCtrMode)); - CHECK_PARAM(IS_AUDIO_ZERO_CROSS_RATE_TYPE(cfg->resovolumeZeroCrossRatelution)); - CHECK_PARAM(IS_AUDIO_RAMP_RATE_TYPE(cfg->volumeRmpRate)); - - if (adc_id > 2) { - return ERROR; - /*only support 3 adc*/ - } - - tmpVal = BL_RD_WORD(adcVolumeConfigAddrOffset); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_MUTE_SOFTMODE, cfg->muteMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_MUTE_RMPDN_RATE, cfg->muteRmpdnRate); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_MUTE_RMPUP_RATE, cfg->muteRmpupRate); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_CTRL_MODE, cfg->volumeCtrMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_CTRL_ZCD_RATE, cfg->volumeZeroCrossRate); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_CTRL_RMP_RATE, cfg->volumeRmpRate); - BL_WR_WORD(adcVolumeConfigAddrOffset, tmpVal); - - tmpVal = BL_RD_WORD(adcVolumeConfigAddrOffset + 0x04); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_CTRL_ZCD_TIMEOUT, cfg->volumeZeroCrossTimeout); - BL_WR_WORD(adcVolumeConfigAddrOffset + 0x04, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Audio DAC Volume Config - * - * @param dac_id: dac id - * @param cfg: volume config cfg pointer - * - * @return None - * -*******************************************************************************/ -BL_Err_Type Audio_DAC_Software_Volume_Config(Audio_DAC_ID_Type dac_id, Audio_Volume_Cfg_Type *cfg) -{ - uint32_t dacVolumeConfigAddrOffset = AUDIO_BASE + 0x434 + dac_id * 0x08; - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_DAC_ID_TYPE(dac_id)); - CHECK_PARAM(IS_AUDIO_MUTE_MODE(cfg->muteMode)); - CHECK_PARAM(IS_AUDIO_RAMP_RATE_TYPE(cfg->muteRmpdnRate)); - CHECK_PARAM(IS_AUDIO_RAMP_RATE_TYPE(cfg->muteRmpupRate)); - CHECK_PARAM(IS_AUDIO_VOLUME_CTR_MODE(cfg->volumeCtrMode)); - CHECK_PARAM(IS_AUDIO_ZERO_CROSS_RATE_TYPE(cfg->resovolumeZeroCrossRatelution)); - CHECK_PARAM(IS_AUDIO_RAMP_RATE_TYPE(cfg->volumeRmpRate)); - - if (dac_id > 1) { - return ERROR; - /*only support 2 dac*/ - } - - tmpVal = BL_RD_WORD(dacVolumeConfigAddrOffset); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_MUTE_SOFTMODE, cfg->muteMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_MUTE_RMPDN_RATE, cfg->muteRmpdnRate); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_MUTE_RMPUP_RATE, cfg->muteRmpupRate); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_CTRL_MODE, cfg->volumeCtrMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_CTRL_ZCD_RATE, cfg->volumeZeroCrossRate); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_CTRL_RMP_RATE, cfg->volumeRmpRate); - BL_WR_WORD(dacVolumeConfigAddrOffset, tmpVal); - - tmpVal = BL_RD_WORD(dacVolumeConfigAddrOffset + 0x04); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_CTRL_ZCD_TIMEOUT, cfg->volumeZeroCrossTimeout); - BL_WR_WORD(dacVolumeConfigAddrOffset + 0x04, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Audio set adc volume - * - * @param volumeSyncAllAdc: sync volume configuration for three adc channel - * @param adc_id: adc id - * @param volume: volume - * - * @return None - * -*******************************************************************************/ -BL_Err_Type Audio_ADC_Set_Volume(BL_Fun_Type volumeSyncAllAdc, Audio_ADC_ID_Type adc_id, uint16_t volume) -{ - uint32_t adcVolumeAddrOffset = AUDIO_BASE + 0x408 + adc_id * 0x08; - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(adc_id)); - - if (adc_id > 2) { - return ERROR; - /*only support 3 adc*/ - } - - if (volumeSyncAllAdc) { - tmpVal = BL_RD_WORD(AUDIO_BASE + 0x408); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_VOLUME, volume); - BL_WR_WORD(AUDIO_BASE + 0x408, tmpVal); - - tmpVal = BL_RD_WORD(AUDIO_BASE + 0x410); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S1_VOLUME, volume); - BL_WR_WORD(AUDIO_BASE + 0x410, tmpVal); - - tmpVal = BL_RD_WORD(AUDIO_BASE + 0x418); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S2_VOLUME, volume); - BL_WR_WORD(AUDIO_BASE + 0x418, tmpVal); - - tmpVal = BL_RD_WORD(AUDIO_BASE + 0x408 + 0x04); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S012_VOLUME_UPDATE, 1); - BL_WR_WORD(AUDIO_BASE + 0x408 + 0x04, tmpVal); - - //TODO AUDIO_ADC_SX_VOLUME_UPDATE/AUDIO_ADC_S012_VOLUME_UPDATE should be reset in isr - - } else { - tmpVal = BL_RD_WORD(adcVolumeAddrOffset); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_VOLUME, volume); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_VOLUME_UPDATE, 1); - BL_WR_WORD(adcVolumeAddrOffset, tmpVal); - - //TODO AUDIO_ADC_SX_VOLUME_UPDATE/AUDIO_ADC_S012_VOLUME_UPDATE should be reset in isr - } - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Audio set dac volume - * - * @param volumeSyncAllDac: sync volume configuration for two dac channel - * @param dac_id: dac id - * @param volume: volume - * - * @return None - * -*******************************************************************************/ -BL_Err_Type Audio_DAC_Set_Volume(BL_Fun_Type volumeSyncAllDac, Audio_DAC_ID_Type dac_id, uint16_t volume) -{ - uint32_t dacVolumeConfigAddrOffset = AUDIO_BASE + 0x434 + dac_id * 0x08; - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_DAC_ID_TYPE(dac_id)); - - if (dac_id > 1) { - return ERROR; - /*only support 2 dac*/ - } - - if (volumeSyncAllDac) { - tmpVal = BL_RD_WORD(AUDIO_BASE + 0x434); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_VOLUME, volume); - BL_WR_WORD(AUDIO_BASE + 0x434, tmpVal); - - tmpVal = BL_RD_WORD(AUDIO_BASE + 0x43c); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S1_VOLUME, volume); - BL_WR_WORD(AUDIO_BASE + 0x43c, tmpVal); - - tmpVal = BL_RD_WORD(AUDIO_BASE + 0x434 + 0x04); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S01_VOLUME_UPDATE, 1); - BL_WR_WORD(AUDIO_BASE + 0x434 + 0x04, tmpVal); - - //TODO AUDIO_DAC_SX_VOLUME_UPDATE/AUDIO_DAC_S01_VOLUME_UPDATE should be reset in isr - - } else { - tmpVal = BL_RD_WORD(dacVolumeConfigAddrOffset); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_VOLUME, volume); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_VOLUME_UPDATE, 1); - BL_WR_WORD(dacVolumeConfigAddrOffset, tmpVal); - - //TODO AUDIO_DAC_SX_VOLUME_UPDATE/AUDIO_DAC_S01_VOLUME_UPDATE should be reset in isr - } - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief clear adc update bit - * - * @param adc_id: adc id - * - * @return None - * -*******************************************************************************/ -void Audio_ADC_Reset_Volume_Update(Audio_ADC_ID_Type adc_id) -{ - uint32_t adcVolumeAddrOffset = AUDIO_BASE + 0x408 + adc_id * 0x08; - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(adc_id)); - - if (adc_id > 2) { - return; - /*only support 3 adc*/ - } - - tmpVal = BL_RD_WORD(adcVolumeAddrOffset); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_VOLUME, 0); - BL_WR_WORD(adcVolumeAddrOffset, tmpVal); -} - -/****************************************************************************/ /** - * @brief clear dac update bit - * - * @param dac_id: dac id - * - * @return None - * -*******************************************************************************/ -void Audio_DAC_Reset_Volume_Update(Audio_DAC_ID_Type dac_id) -{ - uint32_t dacVolumeConfigAddrOffset = AUDIO_BASE + 0x434 + dac_id * 0x08; - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_DAC_ID_TYPE(dac_id)); - - if (dac_id > 1) { - return; - /*only support 2 dac*/ - } - - tmpVal = BL_RD_WORD(dacVolumeConfigAddrOffset); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_VOLUME, 0); - BL_WR_WORD(dacVolumeConfigAddrOffset, tmpVal); -} - -/****************************************************************************/ /** - * @brief clear adc or dac all update bit, when enable sync bit to set all channel dac/adc volume - * ,user should use this function to clear all update flag. - * - * @param isAdcOrDac: IS ADC or DAC,ADC=1 DAC=0 - * - * @return None - * -*******************************************************************************/ -void Audio_Reset_Volume_All_Update(uint8_t isAdcOrDac) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(adc_id)); - if (isAdcOrDac) { - BL_RD_REG(AUDIO_BASE, AUDIO_ADC_S0_MISC); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S012_VOLUME_UPDATE, 0); - BL_WR_REG(AUDIO_BASE, AUDIO_ADC_S0_MISC, tmpVal); - } else { - BL_RD_REG(AUDIO_BASE, AUDIO_DAC_S0_MISC); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S01_VOLUME_UPDATE, 0); - BL_WR_REG(AUDIO_BASE, AUDIO_DAC_S0_MISC, tmpVal); - } -} - -/****************************************************************************/ /** - * @brief Audio set all adc volume Reg Without seting update bit - * - * @param volumeSyncAllAdc: is set all adc - * @param adc_id: adc id - * @param volume: volume - * - * @return Success or Not - * -*******************************************************************************/ -BL_Err_Type Audio_ADC_Set_Volume_Reg(BL_Fun_Type volumeSyncAllAdc, Audio_ADC_ID_Type adc_id, uint16_t volume) -{ - uint32_t adcVolumeAddrOffset = AUDIO_BASE + 0x408 + adc_id * 0x08; - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(adc_id)); - - if (adc_id > 2) { - return ERROR; - /*only support 3 adc*/ - } - - if (volumeSyncAllAdc) { - tmpVal = BL_RD_WORD(AUDIO_BASE + 0x408); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_VOLUME, volume); - BL_WR_WORD(AUDIO_BASE + 0x408, tmpVal); - - tmpVal = BL_RD_WORD(AUDIO_BASE + 0x410); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S1_VOLUME, volume); - BL_WR_WORD(AUDIO_BASE + 0x410, tmpVal); - - tmpVal = BL_RD_WORD(AUDIO_BASE + 0x418); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S2_VOLUME, volume); - BL_WR_WORD(AUDIO_BASE + 0x418, tmpVal); - - } else { - tmpVal = BL_RD_WORD(adcVolumeAddrOffset); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_VOLUME, volume); - BL_WR_WORD(adcVolumeAddrOffset, tmpVal); - } - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Audio set all DAC volume Reg Without seting update bit - * - * @param volumeSyncAllDac: is set all dac - * @param dac_id: dac id - * @param volume: volume - * - * @return Success or Not - * -*******************************************************************************/ -BL_Err_Type Audio_DAC_Set_Volume_Reg(BL_Fun_Type volumeSyncAllDac, Audio_DAC_ID_Type dac_id, uint16_t volume) -{ - uint32_t dacVolumeConfigAddrOffset = AUDIO_BASE + 0x434 + dac_id * 0x08; - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_DAC_ID_TYPE(dac_id)); - - if (dac_id > 1) { - return ERROR; - /*only support 2 dac*/ - } - - if (volumeSyncAllDac) { - tmpVal = BL_RD_WORD(AUDIO_BASE + 0x434); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_VOLUME, volume); - BL_WR_WORD(AUDIO_BASE + 0x434, tmpVal); - - tmpVal = BL_RD_WORD(AUDIO_BASE + 0x43c); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S1_VOLUME, volume); - BL_WR_WORD(AUDIO_BASE + 0x43c, tmpVal); - - } else { - tmpVal = BL_RD_WORD(dacVolumeConfigAddrOffset); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_VOLUME, volume); - BL_WR_WORD(dacVolumeConfigAddrOffset, tmpVal); - } - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Audio set adc volume - * - * @param volumeSyncAllAdc: sync volume configuration for three adc channel,This function will - * blocking CPU until volume adjust task done - * @param adc_id: adc id - * @param volume: volume - * @param blockTimeout: volume block timeout - * - * @return Configuration is success - * -*******************************************************************************/ -BL_Err_Type Audio_ADC_Set_Volume_Block(BL_Fun_Type volumeSyncAllAdc, Audio_ADC_ID_Type adc_id, uint16_t volume, uint32_t blockTimeout) -{ - uint32_t adcVolumeAddrOffset = AUDIO_BASE + 0x408 + adc_id * 0x08; - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(adc_id)); - - if (adc_id > 2) { - return ERROR; - /*only support 3 adc*/ - } - - if (volumeSyncAllAdc) { - tmpVal = BL_RD_WORD(AUDIO_BASE + 0x408); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_VOLUME, volume); - BL_WR_WORD(AUDIO_BASE + 0x408, tmpVal); - - tmpVal = BL_RD_WORD(AUDIO_BASE + 0x410); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S1_VOLUME, volume); - BL_WR_WORD(AUDIO_BASE + 0x410, tmpVal); - - tmpVal = BL_RD_WORD(AUDIO_BASE + 0x418); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S2_VOLUME, volume); - BL_WR_WORD(AUDIO_BASE + 0x418, tmpVal); - - tmpVal = BL_RD_WORD(AUDIO_BASE + 0x408 + 0x04); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S012_VOLUME_UPDATE, 1); - BL_WR_WORD(AUDIO_BASE + 0x408 + 0x04, tmpVal); - - while (Audio_IS_ADC_Volume_Set_Busy(AUDIO_ADC_0) && Audio_IS_ADC_Volume_Set_Busy(AUDIO_ADC_1) && Audio_IS_ADC_Volume_Set_Busy(AUDIO_ADC_2)) { - blockTimeout--; - if (blockTimeout) { - return TIMEOUT; - } - } - //clear update - tmpVal = BL_RD_WORD(adcVolumeAddrOffset); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S012_VOLUME_UPDATE, 0); - BL_WR_WORD(adcVolumeAddrOffset, tmpVal); - - } else { - tmpVal = BL_RD_WORD(adcVolumeAddrOffset); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_VOLUME, volume); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_VOLUME_UPDATE, 1); - BL_WR_WORD(adcVolumeAddrOffset, tmpVal); - - while (Audio_IS_ADC_Volume_Set_Busy(adc_id)) { - blockTimeout--; - if (blockTimeout) { - return TIMEOUT; - } - } - //clear update - tmpVal = BL_RD_WORD(adcVolumeAddrOffset); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_VOLUME_UPDATE, 0); - BL_WR_WORD(adcVolumeAddrOffset, tmpVal); - } - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Audio set dac volume - * - * @param volumeSyncAllDac: sync volume configuration for two dac channel ,This function will - * blocking CPU until volume adjust task done - * @param dac_id: adc id - * @param volume: volume - * @param blockTimeout: volume block timeout - * - * @return is success or not - * -*******************************************************************************/ -BL_Err_Type Audio_DAC_Set_Volume_Block(BL_Fun_Type volumeSyncAllDac, Audio_DAC_ID_Type dac_id, uint16_t volume, uint32_t blockTimeout) -{ - uint32_t dacVolumeConfigAddrOffset = AUDIO_BASE + 0x434 + dac_id * 0x08; - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_DAC_ID_TYPE(dac_id)); - - if (dac_id > 1) { - return ERROR; - /*only support 2 dac*/ - } - - if (volumeSyncAllDac) { - tmpVal = BL_RD_WORD(AUDIO_BASE + 0x434); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_VOLUME, volume); - BL_WR_WORD(AUDIO_BASE + 0x434, tmpVal); - - tmpVal = BL_RD_WORD(AUDIO_BASE + 0x43c); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S1_VOLUME, volume); - BL_WR_WORD(AUDIO_BASE + 0x43c, tmpVal); - - tmpVal = BL_RD_WORD(AUDIO_BASE + 0x434 + 0x04); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S01_VOLUME_UPDATE, 1); - BL_WR_WORD(AUDIO_BASE + 0x434 + 0x04, tmpVal); - - while (Audio_IS_DAC_Volume_Set_Busy(AUDIO_DAC_0) && Audio_IS_DAC_Volume_Set_Busy(AUDIO_DAC_1)) { - blockTimeout--; - if (blockTimeout) { - return TIMEOUT; - } - } - //clear update - tmpVal = BL_RD_WORD(dacVolumeConfigAddrOffset); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S01_VOLUME_UPDATE, 0); - BL_WR_WORD(dacVolumeConfigAddrOffset, tmpVal); - - } else { - tmpVal = BL_RD_WORD(dacVolumeConfigAddrOffset); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_VOLUME, volume); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_VOLUME_UPDATE, 1); - BL_WR_WORD(dacVolumeConfigAddrOffset, tmpVal); - - //TODO AUDIO_DAC_SX_VOLUME_UPDATE/AUDIO_DAC_S01_VOLUME_UPDATE should be reset in isr - } - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Audio set adc agc hardware volume config - * - * @param cfg: cfg pointer - * - * @return None - * -*******************************************************************************/ -BL_Err_Type Audio_ADC_Hardware_Volume_Config(Audio_Volume_Cfg_Type *cfg) -{ - uint32_t adcVolumeConfigAddrOffset = AUDIO_BASE + AUDIO_ADC_H_OFFSET; - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_MUTE_MODE(cfg->muteMode)); - CHECK_PARAM(IS_AUDIO_RAMP_RATE_TYPE(cfg->muteRmpdnRate)); - CHECK_PARAM(IS_AUDIO_RAMP_RATE_TYPE(cfg->muteRmpupRate)); - CHECK_PARAM(IS_AUDIO_VOLUME_CTR_MODE(cfg->volumeCtrMode)); - CHECK_PARAM(IS_AUDIO_ZERO_CROSS_RATE_TYPE(cfg->resovolumeZeroCrossRatelution)); - CHECK_PARAM(IS_AUDIO_RAMP_RATE_TYPE(cfg->volumeRmpRate)); - - tmpVal = BL_RD_WORD(adcVolumeConfigAddrOffset); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_H_MUTE, cfg->muteMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_H_MUTE_RMPDN_RATE, cfg->muteRmpdnRate); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_H_MUTE_RMPUP_RATE, cfg->muteRmpupRate); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_H_CTRL_MODE, cfg->volumeCtrMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_H_CTRL_ZCD_RATE, cfg->volumeZeroCrossRate); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_H_CTRL_RMP_RATE, cfg->volumeRmpRate); - BL_WR_WORD(adcVolumeConfigAddrOffset, tmpVal); - - tmpVal = BL_RD_WORD(adcVolumeConfigAddrOffset + 0x04); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_H_CTRL_ZCD_TIMEOUT, cfg->volumeZeroCrossTimeout); - BL_WR_WORD(adcVolumeConfigAddrOffset + 0x04, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief when AGC is enable , software cannot change volume,but can read AGC ctrl result by this - * function - * - * @param None - * - * @return AGC ctr result - * -*******************************************************************************/ -uint16_t Audio_ADC_Get_Hardware_Volume(void) -{ - uint32_t tmpVal = 0; - uint16_t volume = 0; - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_ADC_H); - volume = BL_GET_REG_BITS_VAL(tmpVal, AUDIO_ADC_H_VOLUME); - - return volume; -} - -/****************************************************************************/ /** - * @brief when AGC is enable , software cannot change volume,but can read AGC ctrl result by this - * function - * - * @param adc_id: adc id - * - * @return adc volume - * -*******************************************************************************/ -uint16_t Audio_ADC_Get_Volume(Audio_ADC_ID_Type adc_id) -{ - uint32_t tmpVal = 0; - uint16_t volume = 0; - - if (adc_id == AUDIO_ADC_0) { - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_ADC_S0); - } else if (adc_id == AUDIO_ADC_1) { - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_ADC_S1); - } else { - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_ADC_S2); - } - - volume = BL_GET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_VOLUME); - - return volume; -} - -/****************************************************************************/ /** - * @brief when AGC is enable , software cannot change volume,but can read AGC ctrl result by this - * function - * - * @param dac_id: dac id - * - * @return dac volume - * -*******************************************************************************/ -uint16_t Audio_DAC_Get_Volume(Audio_DAC_ID_Type dac_id) -{ - uint32_t tmpVal = 0; - - if (dac_id == AUDIO_DAC_0) { - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_S0); - } else { - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_S1); - } - - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_VOLUME); - - return tmpVal; -} - -/****************************************************************************/ /** - * @brief is audio mute done or not . - * - * @param adc_id: adc id - * - * @return is adc mute done - * -*******************************************************************************/ -BL_Sts_Type Audio_IS_ADC_Mute_Done(Audio_ADC_ID_Type adc_id) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(adc_id)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS); - - if (adc_id == AUDIO_ADC_0) { - return BL_IS_REG_BIT_SET(tmpVal, AUDIO_ADC_H0_MUTE_DONE); - } else if (adc_id == AUDIO_ADC_1) { - return BL_IS_REG_BIT_SET(tmpVal, AUDIO_ADC_H1_MUTE_DONE); - } else { - return BL_IS_REG_BIT_SET(tmpVal, AUDIO_ADC_H2_MUTE_DONE); - } -} - -/****************************************************************************/ /** - * @brief is audio mute & volume set are busy or not . - * - * @param adc_id: adc id - * - * @return is adc volume set done - * -*******************************************************************************/ -BL_Sts_Type Audio_IS_ADC_Volume_Set_Busy(Audio_ADC_ID_Type adc_id) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(adc_id)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS); - - if (adc_id == AUDIO_ADC_0) { - return BL_IS_REG_BIT_SET(tmpVal, AUDIO_ADC_H0_BUSY); - } else if (adc_id == AUDIO_ADC_1) { - return BL_IS_REG_BIT_SET(tmpVal, AUDIO_ADC_H1_BUSY); - } else { - return BL_IS_REG_BIT_SET(tmpVal, AUDIO_ADC_H2_BUSY); - } -} - -/****************************************************************************/ /** - * @brief is audio mute done or not . - * - * @param dac_id: dac id - * - * @return is dac mute done - * -*******************************************************************************/ -BL_Sts_Type Audio_IS_DAC_Mute_Set_Done(Audio_DAC_ID_Type dac_id) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(dac_id)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS); - - if (dac_id == AUDIO_DAC_0) { - return BL_IS_REG_BIT_SET(tmpVal, AUDIO_DAC_H0_MUTE_DONE); - } else { - return BL_IS_REG_BIT_SET(tmpVal, AUDIO_DAC_H1_MUTE_DONE); - } -} - -/****************************************************************************/ /** - * @brief is audio mute & volume set are busy or not . - * - * @param dac_id: dac id - * - * @return is dac_id done - * -*******************************************************************************/ -BL_Sts_Type Audio_IS_DAC_Volume_Set_Busy(Audio_DAC_ID_Type dac_id) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(dac_id)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS); - - if (dac_id == AUDIO_DAC_0) { - return BL_IS_REG_BIT_SET(tmpVal, AUDIO_DAC_H0_BUSY); - } else { - return BL_IS_REG_BIT_SET(tmpVal, AUDIO_DAC_H1_BUSY); - } -} - -/****************************************************************************/ /** - * @brief is audio mute & volume set are busy or not . - * - * @param enable: enable agc - * @param cfg: agc cfg - * - * @return None - * -*******************************************************************************/ -void Audio_AGC_Init(uint8_t enable, Audio_AGC_Config_Type *cfg) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_AGC_SRC_TYPE(cfg->agc_src_select)); - CHECK_PARAM(IS_AUDIO_AGC_DETECT_MODE(cfg->agc_detect_mode)); - - if (enable) { - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_ADC_AGC_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_AGC_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_FORCE_GAIN_EN, cfg->agc_force_gain_en); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_FORCE_GAIN_IND, cfg->agc_force_gain_ind); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_MAX_GAIN_QDB, cfg->agc_max_gain_qdb); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_MIN_GAIN_QDB, cfg->agc_min_gain_qdb); - BL_WR_REG(AUDIO_BASE, AUDIO_ADC_AGC_0, tmpVal); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_ADC_AGC_1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_LEVEL_TARGET, cfg->agc_level_target); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_LEVEL_HYST_ATTACK, cfg->agc_level_hyst_attack); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_LEVEL_HYST_DECAY, cfg->agc_level_hyst_decay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_HOLD_TIME_MS, cfg->agc_hold_time_ms); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_DECAY_TIME_MS, cfg->agc_decay_time_ms); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_ATTACK_TIME_MS, cfg->agc_attack_time_ms); - //tmpVal = BL_SET_REG_BITS_VAL(tmpVal,AUDIO_ADC3_PGA_HW_CTRL,cfg->adc3_pga_hw_ctrl); //TODO - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC2_PGA_HW_CTRL, cfg->adc2_pga_hw_ctrl); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC1_PGA_HW_CTRL, cfg->adc1_pga_hw_ctrl); - BL_WR_REG(AUDIO_BASE, AUDIO_ADC_AGC_1, tmpVal); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_ADC_AGC_2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_NOISE_GATE_TH, cfg->agc_noise_gate_th); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_NOISE_GATE_HYST, cfg->agc_noise_gate_hyst); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_SILENCE_GAIN_QDB, cfg->agc_silence_gain_qdb); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_SILENCE_GAIN_WAIT_MS, cfg->agc_silence_gain_wait_ms); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_NOISE_ENTER_TIME_MS, cfg->agc_noise_enter_time_ms); - BL_WR_REG(AUDIO_BASE, AUDIO_ADC_AGC_2, tmpVal); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_ADC_AGC_3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_NOISE_EXIT_TIME_MS, cfg->agc_noise_exit_time_ms); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_DBV_SETTLE_TIME, cfg->agc_dbv_settle_time); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_SRC_SELECT, cfg->agc_src_select); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_DETECT_MODE, cfg->agc_detect_mode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_ATTACK_TIME, cfg->agc_attack_time); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_RELEASE_TIME, cfg->agc_release_time); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_AVERAGE_TIME, cfg->agc_average_time); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_PGA_CTRL_EN, cfg->agc_pga_ctrl_en); - BL_WR_REG(AUDIO_BASE, AUDIO_ADC_AGC_3, tmpVal); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_ADC_AGC_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_AGC_EN, 1); - BL_WR_REG(AUDIO_BASE, AUDIO_ADC_AGC_0, tmpVal); - - } else { - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_ADC_AGC_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_AGC_EN, 0); - BL_WR_REG(AUDIO_BASE, AUDIO_ADC_AGC_0, tmpVal); - } -} - -/****************************************************************************/ /** - * @brief is audio mute & volume set are busy or not . - * - * @param enable: enable drc - * @param cfg: drc cfg - * - * @return None - * -*******************************************************************************/ -void Audio_DRC_Init(uint8_t enable, Audio_DRC_Config_Type *cfg) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_DRC_DATA_TYPE(cfg->drc_raw_sel)); - CHECK_PARAM(IS_AUDIO_DRC_DATA_TYPE(cfg->drc_peak_sel)); - CHECK_PARAM(IS_AUDIO_DRC_DATA_TYPE(cfg->drc_avg_sel)); - CHECK_PARAM(IS_AUDIO_DRC_DATA_TYPE(cfg->ngt_src_sel)); - - if (enable) { - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_DRC_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_RAW_SEL, cfg->drc_raw_sel); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_PEAK_SEL, cfg->drc_peak_sel); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_AVG_SEL, cfg->drc_avg_sel); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_AVG_EN, cfg->drc_avg_en); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_AVG_TIME, cfg->drc_avg_time); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_ATT_TIME, cfg->drc_att_time); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_RLS_TIME, cfg->drc_rls_time); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_NGT_DOWNSAMPLE_EN, cfg->drc_ngt_downsample_en); - BL_WR_REG(AUDIO_BASE, AUDIO_DAC_DRC_0, tmpVal); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_DRC_1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_THRESHOLD_L, cfg->drc_threshold_l); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_THRESHOLD_C, cfg->drc_threshold_c); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_THRESHOLD_E, cfg->drc_threshold_e); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_SLOPE_MODE_C, cfg->drc_slope_mode_c); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_SLOPE_MODE_E, cfg->drc_slope_mode_e); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_MAKEUP_GAIN, cfg->drc_makeup_gain); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_ATTACK_TIME, cfg->drc_attack_time); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_RELEASE_TIME, cfg->drc_release_time); - BL_WR_REG(AUDIO_BASE, AUDIO_DAC_DRC_1, tmpVal); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_NGT_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_NGT_EN, cfg->ngt_en); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_NGT_SRC_SEL, cfg->ngt_src_sel); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_NGT_AVG_TIME, cfg->ngt_avg_time); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_NGT_THRESHOLD, cfg->ngt_threshold); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_NGT_HYSTERESIS, cfg->ngt_hysteresis); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_NGT_NOISE_HOLD_EN, cfg->ngt_noise_hold_en); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_NGT_NOISE_HOLD_TIME_K, cfg->ngt_noise_hold_time_k); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_NGT_SIGNAL_HOLD_EN, cfg->ngt_signal_hold_en); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_NGT_SIGNAL_HOLD_TIME_K, cfg->ngt_signal_hold_time_k); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_NGT_DMUTE_ON, cfg->ngt_dmute_on); - BL_WR_REG(AUDIO_BASE, AUDIO_DAC_NGT_0, tmpVal); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_ZD_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ZD_EN, cfg->zd_en); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ZD_TIME, cfg->zd_time); - BL_WR_REG(AUDIO_BASE, AUDIO_DAC_ZD_0, tmpVal); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_DRC_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_EN, 1); - BL_WR_REG(AUDIO_BASE, AUDIO_DAC_DRC_0, tmpVal); - - } else { - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_DRC_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_EN, 0); - BL_WR_REG(AUDIO_BASE, AUDIO_DAC_DRC_0, tmpVal); - } -} - -/****************************************************************************/ /** - * @brief Audio interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void AUDIO_IRQHandler(void) -{ - uint8_t intIndex = 0; - - for (intIndex = 0; intIndex < AUDIO_INT_NUM_ALL; intIndex++) { - if (Audio_GetIntStatus(intIndex) == SET) { - if (audioIntCbfArra[intIndex] != NULL) { - audioIntCbfArra[intIndex](); - } - Auido_IntClear(intIndex); - } - } -} -#endif - -/****************************************************************************/ /** - * @brief Audio Clock Initialization Function - * - * @param cfg: clock configuration pra - * - * @return None - * -*******************************************************************************/ -void Audio_Clock_Init(Audio_Clock_CFG_Type *cfg) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_ADC_CLOCK_TYPE(cfg->adc_clock)); - CHECK_PARAM(IS_AUDIO_DAC_CLOCK_TYPE(cfg->dac_clock)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_AUD_TOP); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_RATE, cfg->adc_clock); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_RATE, cfg->dac_clock); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_PDM_ITF_INV_SEL, cfg->pdm_clk_inv); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_ITF_INV_SEL, cfg->adc_clk_inv); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_ITF_INV_SEL, cfg->dac_clk_inv); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_CKG_EN, 1); - - BL_WR_REG(AUDIO_BASE, AUDIO_AUD_TOP, tmpVal); - - //TODO to select postion of register interrupt -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(AUDIO_IRQn, AUDIO_IRQHandler); -#endif -} - -/****************************************************************************/ /** - * @brief VAD Configuration function - * - * @param cfg: VAD configuration pra - * - * @return None - * -*******************************************************************************/ -void Audio_VAD_Init(Audio_VAD_Cfg_Type *cfg) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_VAD_SOURCE_TYPE(cfg->vadSource)); - CHECK_PARAM(IS_AUDIO_VAD_FRAMINGSHIFT_TYPE(cfg->vadFramingShift)); - CHECK_PARAM(IS_AUDIO_VAD_FRAMINGTIME_TYPE(cfg->vadFramingTime)); - CHECK_PARAM(IS_AUDIO_VAD_IRQ_SOURCE_TYPE(cfg->vadIRQSource)); - CHECK_PARAM(IS_AUDIO_VAD_NOISYBUFFERLEN_TYPE(cfg->vadNoisyBufferLen)); - CHECK_PARAM(IS_AUDIO_VAD_NOISYBUFFERMONITOR_TYPE(cfg->vadNoisyBufferMonitor)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_VAD_CTRL_0); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_NBUF_MONIT_EN, cfg->vadNoisyBufferMonitorEnable); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_NBUF_MONIT_CTRL, cfg->vadNoisyBufferMonitor); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_NBUF_LEN_CTRL, cfg->vadNoisyBufferLen); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_OUT_SEL, cfg->vadIRQSource); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_FRAMETIME_CTRL, cfg->vadFramingTime); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_FRAMESHIFT_CTRL, cfg->vadFramingShift); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_IN_SEL, cfg->vadSource); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_NTH_MAXLMT_EN, cfg->vadNoisyMaxLimitEnable); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_NTH_MINLMT_EN, cfg->vadNoisyMinLimitEnable); - - BL_WR_REG(AUDIO_BASE, AUDIO_VAD_CTRL_0, tmpVal); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_VAD_CTRL_2); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_NTH_MINLMT, cfg->vadNoisyMinLimit); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_NTH_MAXLMT, cfg->vadNoisyMaxLimit); - - BL_WR_REG(AUDIO_BASE, AUDIO_VAD_CTRL_2, tmpVal); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_VAD_CTRL_3); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_SMOOTH_FALL, cfg->vadSmoothFall); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_SMOOTH_RISE, cfg->vadSmoothRise); - - BL_WR_REG(AUDIO_BASE, AUDIO_VAD_CTRL_3, tmpVal); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_VAD_CTRL_1); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_NTH_SCALE, cfg->noisyBufferThrScale); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_NTH_BIAS, cfg->noisyBufferThrBais); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_NBUF_DISCARD, cfg->noisyBufferDiscardNumber); - - BL_WR_REG(AUDIO_BASE, AUDIO_VAD_CTRL_1, tmpVal); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_VAD_CTRL_5); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_NOISE_TH, cfg->noisyBufferThr); - - BL_WR_REG(AUDIO_BASE, AUDIO_VAD_CTRL_5, tmpVal); -} - -/****************************************************************************/ /** - * @brief enable VAD - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Audio_VAD_Enable(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_VAD_CTRL_0); - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_VAD_EN); - BL_WR_REG(AUDIO_BASE, AUDIO_VAD_CTRL_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief disable VAD - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Audio_VAD_Disable(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_VAD_CTRL_0); - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_VAD_EN); - BL_WR_REG(AUDIO_BASE, AUDIO_VAD_CTRL_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief VAD set EK function - * - * @param None - * - * @return None - * -*******************************************************************************/ -uint32_t Audio_VAD_Get_EK(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_VAD_CTRL_4); - - return tmpVal; -} - -/****************************************************************************/ /** - * @brief audio power on - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Audio_Poweron(void) -{ - uint32_t tmpVal = 0; - - /* common */ - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_CODEC_POWER1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_MICBIAS_PU, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_CODEC_VRDA_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_CODEC_IBIAS_CTRL, 5); - BL_WR_REG(AUDIO_BASE, AUDIO_CODEC_POWER1, tmpVal); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_CODEC_POWER2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_LDO25_PU, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_HPBG_PU, 1); - BL_WR_REG(AUDIO_BASE, AUDIO_CODEC_POWER2, tmpVal); - - /*DAC power on*/ - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_CODEC_DAC); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DACL_SDAC_LINEOUT, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DACL_LINEOUT_MODE, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DACL_EN_DAC, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DACL_EN_LINEOUT, 1); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DACR_SDAC_LINEOUT, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DACR_LINEOUT_MODE, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DACR_EN_DAC, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DACR_EN_LINEOUT, 1); - BL_WR_REG(AUDIO_BASE, AUDIO_CODEC_DAC, tmpVal); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_CODEC_DAC_RAMP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_RG_LO_VREF_RAMP_DCL_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_RG_PU_VREF_RAMP, 1); - BL_WR_REG(AUDIO_BASE, AUDIO_CODEC_DAC_RAMP, tmpVal); - - /*ADC Power on */ - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_CODEC_ADC0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC0_EN_SDM, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC0_EN_PGA, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC0_PGA_GAIN, 8); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC0_ICTRL_ADC2, 3); - BL_WR_REG(AUDIO_BASE, AUDIO_CODEC_ADC0, tmpVal); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_CODEC_ADC1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC1_EN_SDM, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC1_EN_PGA, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC1_PGA_GAIN, 8); - BL_WR_REG(AUDIO_BASE, AUDIO_CODEC_ADC1, tmpVal); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_CODEC_ADC2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC2_EN_SDM, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC2_EN_PGA, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC2_PGA_GAIN, 8); - BL_WR_REG(AUDIO_BASE, AUDIO_CODEC_ADC2, tmpVal); - - /* best digital filter configuration*/ - Audio_Set_DAC_Scaling(1, 14); -} - -void Audio_SetADCAnalogGain(Audio_ADC_ID_Type adc, uint8_t analogGain) -{ - uint32_t tmpVal = 0; - - if (adc == AUDIO_ADC_0) { - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_CODEC_ADC0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC0_PGA_GAIN, analogGain); - BL_WR_REG(AUDIO_BASE, AUDIO_CODEC_ADC0, tmpVal); - } else if (adc == AUDIO_ADC_1) { - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_CODEC_ADC1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC1_PGA_GAIN, analogGain); - BL_WR_REG(AUDIO_BASE, AUDIO_CODEC_ADC1, tmpVal); - } else { - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_CODEC_ADC2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC2_PGA_GAIN, analogGain); - BL_WR_REG(AUDIO_BASE, AUDIO_CODEC_ADC2, tmpVal); - } -} - -void Audio_SetDACAnalogGain(Audio_DAC_ID_Type dac, uint8_t analogGain) -{ - uint32_t tmpVal = 0; - - if (dac == AUDIO_DAC_0) { - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_CODEC_DAC); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DACL_LINEOUT_GAIN, analogGain); - BL_WR_REG(AUDIO_BASE, AUDIO_CODEC_DAC, tmpVal); - } else { - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_CODEC_DAC); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DACR_LINEOUT_GAIN, analogGain); - BL_WR_REG(AUDIO_BASE, AUDIO_CODEC_DAC, tmpVal); - } -} - -/*@} end of group AUDIO_Public_Functions */ - -/*@} end of group AUDIO */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_aupdm.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_aupdm.c deleted file mode 100644 index 374422e229..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_aupdm.c +++ /dev/null @@ -1,777 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_pdm.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_aupdm.h" -#include "pdm_reg.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup AUDIOPDM - * @{ - */ - -/** @defgroup AUDIOPDM_Private_Macros - * @{ - */ - -/*@} end of group AUDIOPDM_Private_Macros */ - -/** @defgroup AUDIOPDM_Private_Types - * @{ - */ - -/*@} end of group AUDIOPDM_Private_Types */ - -/** @defgroup AUDIOPDM_Private_Variables - * @{ - */ -static intCallback_Type *aupdmIntCbfArra[AUPDM_INT_NUM_ALL] = { NULL }; - -/*@} end of group AUDIOPDM_Private_Variables */ - -/** @defgroup AUDIOPDM_Global_Variables - * @{ - */ - -/*@} end of group AUDIOPDM_Global_Variables */ - -/** @defgroup AUDIOPDM_Private_Fun_Declaration - * @{ - */ - -/*@} end of group AUDIOPDM_Private_Fun_Declaration */ - -/** @defgroup AUDIOPDM_Private_Functions - * @{ - */ - -/*@} end of group AUDIOPDM_Private_Functions */ - -/** @defgroup AUDIOPDM_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief AUDIO Interrupt mask - * - * @param intType: intType - * @param intMask: intMask - * - * @return None - * -*******************************************************************************/ -void Aupdm_IntMask(Aupdm_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUPDM_INT_TYPE(intType)); - CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); - - switch (intType) { - case AUPDM_INT_RX_FIFO_THR: - tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_CTRL); - if (intMask) { - tmpVal = BL_CLR_REG_BIT(tmpVal, PDM_RXA_INT_EN); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, PDM_RXA_INT_EN); - } - BL_WR_REG(PDM0_BASE, PDM_RX_FIFO_CTRL, tmpVal); - break; - case AUPDM_INT_RX_FIFO_OVERRUN: - tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_CTRL); - if (intMask) { - tmpVal = BL_CLR_REG_BIT(tmpVal, PDM_RXO_INT_EN); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, PDM_RXO_INT_EN); - } - BL_WR_REG(PDM0_BASE, PDM_RX_FIFO_CTRL, tmpVal); - break; - case AUPDM_INT_RX_FIFO_UNDERRUN: - tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_CTRL); - if (intMask) { - tmpVal = BL_CLR_REG_BIT(tmpVal, PDM_RXU_INT_EN); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, PDM_RXU_INT_EN); - } - BL_WR_REG(PDM0_BASE, PDM_RX_FIFO_CTRL, tmpVal); - break; - - case AUPDM_INT_NUM_ALL: - if (intMask) { - tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_CTRL); - tmpVal = BL_CLR_REG_BIT(tmpVal, PDM_RXA_INT_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, PDM_RXU_INT_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, PDM_RXO_INT_EN); - BL_WR_REG(PDM0_BASE, PDM_RX_FIFO_CTRL, tmpVal); - - } else { - tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_CTRL); - tmpVal = BL_SET_REG_BIT(tmpVal, PDM_RXA_INT_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, PDM_RXU_INT_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, PDM_RXO_INT_EN); - BL_WR_REG(PDM0_BASE, PDM_RX_FIFO_CTRL, tmpVal); - } - break; - - default: - break; - } -} - -/****************************************************************************/ /** - * @brief read int flag - * - * @param intType: intType - * - * @return flag status - * -*******************************************************************************/ -BL_Sts_Type Aupdm_GetIntStatus(Aupdm_INT_Type intType) -{ - uint32_t tmpVal = 0; - BL_Sts_Type rlt = RESET; - - CHECK_PARAM(IS_AUPDM_INT_TYPE(intType)); - - switch (intType) { - case AUPDM_INT_RX_FIFO_THR: - tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_STATUS); - rlt = BL_IS_REG_BIT_SET(tmpVal, PDM_RXA_INT); - break; - case AUPDM_INT_RX_FIFO_OVERRUN: - tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_STATUS); - rlt = BL_IS_REG_BIT_SET(tmpVal, PDM_RXO_INT); - break; - case AUPDM_INT_RX_FIFO_UNDERRUN: - tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_STATUS); - rlt = BL_IS_REG_BIT_SET(tmpVal, PDM_RXU_INT); - break; - default: - break; - } - - return rlt; -} - -/****************************************************************************/ /** - * @brief clear audio Interrupt flag - * - * @param intType: intType - * - * @return None - * -*******************************************************************************/ -void Aupdm_IntClear(Aupdm_INT_Type intType) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUPDM_INT_TYPE(intType)); - - switch (intType) { - case AUPDM_INT_RX_FIFO_THR: - tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_STATUS); - tmpVal = BL_SET_REG_BIT(tmpVal, PDM_RXA_INT); - BL_WR_REG(PDM0_BASE, PDM_RX_FIFO_STATUS, tmpVal); - break; - case AUPDM_INT_RX_FIFO_OVERRUN: - tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_STATUS); - tmpVal = BL_SET_REG_BIT(tmpVal, PDM_RXO_INT); - BL_WR_REG(PDM0_BASE, PDM_RX_FIFO_STATUS, tmpVal); - break; - case AUPDM_INT_RX_FIFO_UNDERRUN: - tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_STATUS); - tmpVal = BL_SET_REG_BIT(PDM0_BASE, PDM_RXU_INT); - BL_WR_REG(PDM0_BASE, PDM_RX_FIFO_STATUS, tmpVal); - break; - - case AUPDM_INT_NUM_ALL: - - tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_STATUS); - - tmpVal = BL_SET_REG_BIT(tmpVal, PDM_RXA_INT); - tmpVal = BL_SET_REG_BIT(tmpVal, PDM_RXU_INT); - tmpVal = BL_SET_REG_BIT(tmpVal, PDM_RXO_INT); - - BL_WR_REG(PDM0_BASE, PDM_RX_FIFO_STATUS, tmpVal); - - default: - break; - } -} - -/****************************************************************************/ /** - * @brief AUPDM PDM interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -static void AUPDM_PDM_IRQHandler(void) -{ - uint8_t intIndex = 0; - - for (intIndex = 0; intIndex < AUPDM_INT_NUM_ALL; intIndex++) { - if (Aupdm_GetIntStatus(intIndex) == SET) { - aupdmIntCbfArra[intIndex](); - Aupdm_IntClear(intIndex); - } - } -} -#endif - -/****************************************************************************/ /** - * @brief AUPDM PDM Clock Initialization Function - * - * @param cfg: clock configuration pra - * - * @return None - * -*******************************************************************************/ -void Aupdm_Clock_Init(Aupdm_Clock_CFG_Type *cfg) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUPDM_ADC_CLOCK_TYPE(cfg->adc_clock)); - CHECK_PARAM(IS_AUPDM_DAC_CLOCK_TYPE(cfg->dac_clock)); - - tmpVal = BL_RD_REG(PDM0_BASE, PDM_AUDPDM_TOP); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_RATE, cfg->adc_clock); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ITF_INV_SEL, cfg->pdm_clk_inv); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_ITF_INV_SEL, cfg->adc_clk_inv); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_AUDIO_CKG_EN, 1); - - BL_WR_REG(PDM0_BASE, PDM_AUDPDM_TOP, tmpVal); - -//TODO to select postion of register interrupt -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(AUPDM_TOUCH_IRQn, AUPDM_PDM_IRQHandler); -#endif -} - -/****************************************************************************/ /** - * @brief AUPDM support three channel for pdm .Meanwhile AUPDM support two DMIC Interface which - * supporting four pdm data source input.This function is used to select channel with pdm - * source. - * - * @param id: pdm channel,cannot be larger than 3 - * @param pdmSel: pdm source select - * - * @return Success or not - * -*******************************************************************************/ -void Aupdm_PDM_Channel_Sel(Aupdm_PDM_ID_Type id, Aupdm_PDM_Source_Type pdmSel) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUPDM_PDM_SOURCE_TYPE(pdmSel)); - CHECK_PARAM(IS_AUPDM_PDM_ID_TYPE(id)); - - tmpVal = BL_RD_REG(PDM0_BASE, PDM_PDM_0); - - if (id == AUPDM_PDM_0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_0_PDM_SEL, pdmSel); - } else if (id == AUPDM_PDM_1) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_1_PDM_SEL, pdmSel); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_2_PDM_SEL, pdmSel); - } - BL_WR_REG(PDM0_BASE, PDM_PDM_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief AUPDM Enable PDM - * - * @param id: PDM ID - * - * @return Success or not - * -*******************************************************************************/ -void Aupdm_PDM_Enable(Aupdm_PDM_ID_Type id) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUPDM_PDM_ID_TYPE(id)); - - tmpVal = BL_RD_REG(PDM0_BASE, PDM_PDM_0); - - if (id == AUPDM_PDM_0) { - tmpVal = BL_SET_REG_BIT(tmpVal, PDM_0_EN); - } else if (id == AUPDM_PDM_1) { - tmpVal = BL_SET_REG_BIT(tmpVal, PDM_1_EN); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, PDM_2_EN); - } - BL_WR_REG(PDM0_BASE, PDM_PDM_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief register interrupt callback function pointer - * - * @param intType: intType - * @param cbFun: cbFun - * - * @return None - * -*******************************************************************************/ -BL_Err_Type Aupdm_Int_Callback_Install(Aupdm_INT_Type intType, intCallback_Type *cbFun) -{ - CHECK_PARAM(IS_AUPDM_INT_TYPE(intType)); - - aupdmIntCbfArra[intType] = cbFun; - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief rx fifo flush - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Aupdm_RxFifoClear(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_CTRL); - tmpVal = BL_SET_REG_BIT(tmpVal, PDM_RX_FIFO_FLUSH); - BL_WR_REG(PDM0_BASE, PDM_RX_FIFO_CTRL, tmpVal); -} - -/****************************************************************************/ /** - * @brief Get Rx FIFO Count - * - * @param None - * - * @return fifi count - * -*******************************************************************************/ -uint32_t Aupdm_GetRxFifoCount(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_STATUS); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDM_RXA_CNT); - - return tmpVal; -} - -/****************************************************************************/ /** - * @brief Read RX FIFO - * - * @param None - * - * @return fifo data - * -*******************************************************************************/ -uint32_t Aupdm_ReadRxFifo(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_DATA); - - return tmpVal; -} - -/****************************************************************************/ /** - * @brief Configure rx fifo - * - * @param cfg: fifo cfg - * - * @return None - * -*******************************************************************************/ -void Aupdm_RxFifoConfig(Aupdm_FifoCfg_Type *cfg) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUPDM_RESOLUTION_TYPE(cfg->resolution)); - CHECK_PARAM(IS_AUPDM_FIFO_AILGN_MODE(cfg->ailgnMode)); - CHECK_PARAM(IS_AUPDM_FIFO_DQR_THRESHOLD_MODE(cfg->dmaThresholdMode)); - - tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_CTRL); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_RX_DATA_RES, cfg->resolution); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_RX_DATA_MODE, cfg->ailgnMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_RX_DRQ_CNT, cfg->dmaThresholdMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_RX_TRG_LEVEL, cfg->FifoIntThreshold); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_RX_DRQ_EN, cfg->dmaEn); - - BL_WR_REG(PDM0_BASE, PDM_RX_FIFO_CTRL, tmpVal); - - tmpVal = BL_RD_REG(PDM0_BASE, PDM_AUDPDM_ITF); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_ITF_EN, cfg->dmaEn); - BL_WR_REG(PDM0_BASE, PDM_AUDPDM_ITF, tmpVal); -} - -/****************************************************************************/ /** - * @brief enable rx fifo - * - * @param ch: ch - * - * @return None - * -*******************************************************************************/ -void Aupdm_RxFifoEnable(uint8_t ch) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_CTRL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_RX_CH_EN, ch); - BL_WR_REG(PDM0_BASE, PDM_RX_FIFO_CTRL, tmpVal); -} - -/****************************************************************************/ /** - * @brief disable rx fifo - * - * @param ch: fifo cfg - * - * @return None - * -*******************************************************************************/ -void Aupdm_RxFifoDisable(uint8_t ch) -{ - uint32_t tmpVal = 0; - uint32_t tmpVal2 = 0; - - tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_CTRL); - tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, PDM_RX_CH_EN); - - tmpVal2 &= ~ch; - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_RX_CH_EN, tmpVal2); - - BL_WR_REG(PDM0_BASE, PDM_RX_FIFO_CTRL, tmpVal); -} - -/****************************************************************************/ /** - * @brief Select Rx channel form ADC Channel . source Default selction is - * rx0-adc_0,rx1-adc_1,rx2-adc_2,rx3-aec_0,rx4-aec_1 - * - * @param rx_channel: rx_channel index . Note tx_channel <=4 - * @param adc_id: rx[rx_channel] conect to adc_id - * - * @return Success or not - * -*******************************************************************************/ -BL_Err_Type Aupdm_Rx_Source_ADC_Sel(uint8_t rx_channel, Aupdm_ADC_ID_Type adc_id) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUPDM_ADC_ID_TYPE(adc_id)); - - if (rx_channel > 4) { - return ERROR; - /*rx channel sel can not larger than 4*/ - } - - tmpVal = BL_RD_REG(PDM0_BASE, PDM_AUDPDM_ITF); - - switch (rx_channel) { - case 0: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_AUD_RX0_SEL, adc_id); - break; - case 1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_AUD_RX1_SEL, adc_id); - break; - case 2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_AUD_RX2_SEL, adc_id); - break; - default: - break; - } - - BL_WR_REG(PDM0_BASE, PDM_AUDPDM_ITF, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief AUPDM ADC enable - * - * @param id: Auido ADC ID - * - * @return None - * -*******************************************************************************/ -void Aupdm_ADC_Enable(Aupdm_ADC_ID_Type id) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUPDM_ADC_ID_TYPE(id)); - - tmpVal = BL_RD_REG(PDM0_BASE, PDM_AUDPDM_ITF); - if (id == AUPDM_ADC_0) { - tmpVal = BL_SET_REG_BIT(tmpVal, PDM_ADC_0_EN); - } else if (id == AUPDM_ADC_1) { - tmpVal = BL_SET_REG_BIT(tmpVal, PDM_ADC_1_EN); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, PDM_ADC_2_EN); - } - BL_WR_REG(PDM0_BASE, PDM_AUDPDM_ITF, tmpVal); -} - -/****************************************************************************/ /** - * @brief AUPDM ADC disable - * - * @param id: Auido ADC ID - * - * @return None - * -*******************************************************************************/ -void Aupdm_ADC_Disable(Aupdm_ADC_ID_Type id) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(PDM0_BASE, PDM_AUDPDM_ITF); - if (id == AUPDM_ADC_0) { - tmpVal = BL_CLR_REG_BIT(tmpVal, PDM_ADC_0_EN); - } else if (id == AUPDM_ADC_1) { - tmpVal = BL_CLR_REG_BIT(tmpVal, PDM_ADC_1_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, PDM_ADC_2_EN); - } - BL_WR_REG(PDM0_BASE, PDM_AUDPDM_ITF, tmpVal); -} - -/****************************************************************************/ /** - * @brief set adc scaling value - * - * @param id: Auido ADC ID - * @param scalingVal: scaling value - * - * @return None - * -*******************************************************************************/ -void Aupdm_Set_ADC_Scaling_Value(Aupdm_ADC_ID_Type id, uint8_t scalingVal) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUPDM_ADC_ID_TYPE(id)); - - tmpVal = BL_RD_REG(PDM0_BASE, PDM_ADC_0); - - if (id == AUPDM_ADC_0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_0_SCAL, scalingVal); - } else if (id == AUPDM_ADC_1) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_1_SCAL, scalingVal); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_2_SCAL, scalingVal); - } - BL_WR_REG(PDM0_BASE, PDM_ADC_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief set fir mode - * - * @param id: Auido ADC ID - * @param enable: enable or disable - * - * @return None - * -*******************************************************************************/ -void Aupdm_Set_Fir_Mode(Aupdm_ADC_ID_Type id, uint8_t enable) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUPDM_ADC_ID_TYPE(id)); - - tmpVal = BL_RD_REG(PDM0_BASE, PDM_ADC_0); - - if (id == AUPDM_ADC_0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_0_FIR_MODE, enable); - } else if (id == AUPDM_ADC_1) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_1_FIR_MODE, enable); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_2_FIR_MODE, enable); - } - BL_WR_REG(PDM0_BASE, PDM_ADC_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief AUPDM Set HPF Parameter - * - * @param id: ADC ID - * @param k1_enable: k1 parameter enable - * @param k1: k1 parameter in range 4 bit - * @param k2_enable: k2 parameter enable - * @param k2: k1 parameter in range 4 bit - * - * @return None - * -*******************************************************************************/ -void Aupdm_Set_HPF_Parameter(Aupdm_ADC_ID_Type id, uint8_t k1_enable, uint8_t k1, uint8_t k2_enable, uint8_t k2) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUPDM_ADC_ID_TYPE(id)); - - tmpVal = BL_RD_REG(PDM0_BASE, PDM_ADC_1); - - switch (id) { - case AUPDM_ADC_0: - if (k1_enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, PDM_ADC_0_K1_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_0_K1, k1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, PDM_ADC_0_K1_EN); - } - if (k2_enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, PDM_ADC_0_K2_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_0_K2, k2); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, PDM_ADC_0_K2_EN); - } - break; - case AUPDM_ADC_1: - if (k1_enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, PDM_ADC_1_K1_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_1_K1, k1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, PDM_ADC_1_K1_EN); - } - if (k2_enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, PDM_ADC_1_K2_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_1_K2, k2); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, PDM_ADC_1_K2_EN); - } - break; - case AUPDM_ADC_2: - if (k1_enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, PDM_ADC_2_K1_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_2_K1, k1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, PDM_ADC_2_K1_EN); - } - - if (k2_enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, PDM_ADC_2_K2_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_2_K2, k2); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, PDM_ADC_2_K2_EN); - } - break; - default: - break; - } - - BL_WR_REG(PDM0_BASE, PDM_ADC_1, tmpVal); -} - -/****************************************************************************/ /** - * @brief set pdm inv - * - * @param id: Auido ADC ID - * @param swap: inv - * - * @return None - * -*******************************************************************************/ -void Aupdm_ADC_PDM_Inv_Swap(Aupdm_ADC_ID_Type id, uint8_t swap) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUPDM_ADC_ID_TYPE(id)); - - tmpVal = BL_RD_REG(PDM0_BASE, PDM_DAC_0); - if (id == AUPDM_ADC_0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_0_PDM_LVL_SWAP, swap); - } else if (id == AUPDM_ADC_1) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_1_PDM_LVL_SWAP, swap); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_2_PDM_LVL_SWAP, swap); - } - BL_WR_REG(PDM0_BASE, PDM_DAC_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief set pdm value - * - * @param pdm_l: pdm l - * @param pdm_h: pdm h - * - * @return None - * -*******************************************************************************/ -void Aupdm_ADC_Set_PDM_Value(uint8_t pdm_l, uint8_t pdm_h) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(PDM0_BASE, PDM_DAC_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_PDM_L, pdm_l); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_PDM_H, pdm_l); - BL_WR_REG(PDM0_BASE, PDM_DAC_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief AUPDM adc Volume Config - * - * @param adc_id: adc id - * @param volume: volume config cfg pointer - * - * @return None - * -*******************************************************************************/ -BL_Err_Type Aupdm_ADC_Volume_Config(Aupdm_ADC_ID_Type adc_id, uint8_t volume) -{ - if (adc_id > 2) { - return ERROR; - /*only support 3 adc*/ - } - - if (adc_id == AUPDM_ADC_0) { - BL_WR_REG(PDM0_BASE, PDM_ADC_S0, volume); - } else if (adc_id == AUPDM_ADC_1) { - BL_WR_REG(PDM0_BASE, PDM_ADC_S1, volume); - } else { - BL_WR_REG(PDM0_BASE, PDM_ADC_S2, volume); - } - - return SUCCESS; -} - -/*@} end of group AUPDMPDM_Public_Functions */ - -/*@} end of group AUPDMPDM */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_cam.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_cam.c deleted file mode 100644 index 45f6c65da2..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_cam.c +++ /dev/null @@ -1,979 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_cam.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808.h" -#include "bl808_cam.h" -#include "bl808_glb.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup CAM - * @{ - */ - -/** @defgroup CAM_Private_Macros - * @{ - */ - -/*@} end of group CAM_Private_Macros */ - -/** @defgroup CAM_Private_Types - * @{ - */ - -/*@} end of group CAM_Private_Types */ - -/** @defgroup CAM_Private_Variables - * @{ - */ -static const uint32_t camAddr[CAM_ID_MAX] = { DVP0_BASE, DVP1_BASE, DVP2_BASE, DVP3_BASE, - DVP4_BASE, DVP5_BASE, DVP6_BASE, DVP7_BASE }; -#ifndef BFLB_USE_HAL_DRIVER -static intCallback_Type *camIntCbfArra[CAM_ID_MAX][CAM_INT_ALL] = { { NULL } }; -#endif - -/*@} end of group CAM_Private_Variables */ - -/** @defgroup CAM_Global_Variables - * @{ - */ - -/*@} end of group CAM_Global_Variables */ - -/** @defgroup CAM_Private_Fun_Declaration - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -static void CAM_IntHandler(CAM_ID_Type camId); -#endif - -/*@} end of group CAM_Private_Fun_Declaration */ - -/** @defgroup CAM_Private_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Camera interrupt common handler function - * - * @param camId: Camera ID type - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -static void CAM_IntHandler(CAM_ID_Type camId) -{ - uint32_t tmpVal; - uint32_t CAMx = camAddr[camId]; - - /* Check the parameters */ - CHECK_PARAM(IS_CAM_ID_TYPE(camId)); - - tmpVal = BL_RD_REG(CAMx, CAM_DVP_STATUS_AND_ERROR); - - if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_NORMAL_INT)) { - CAM_IntClr(camId, CAM_INT_NORMAL); - - if (camIntCbfArra[camId][CAM_INT_NORMAL] != NULL) { - /* call the callback function */ - camIntCbfArra[camId][CAM_INT_NORMAL](); - } - } - - if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_MEM_INT)) { - CAM_IntClr(camId, CAM_INT_MEMORY_OVERWRITE); - - if (camIntCbfArra[camId][CAM_INT_MEMORY_OVERWRITE] != NULL) { - /* call the callback function */ - camIntCbfArra[camId][CAM_INT_MEMORY_OVERWRITE](); - } - } - - if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_FRAME_INT)) { - CAM_IntClr(camId, CAM_INT_FRAME_OVERWRITE); - - if (camIntCbfArra[camId][CAM_INT_FRAME_OVERWRITE] != NULL) { - /* call the callback function */ - camIntCbfArra[camId][CAM_INT_FRAME_OVERWRITE](); - } - } - - if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_FIFO_INT)) { - CAM_IntClr(camId, CAM_INT_FIFO_OVERWRITE); - - if (camIntCbfArra[camId][CAM_INT_FIFO_OVERWRITE] != NULL) { - /* call the callback function */ - camIntCbfArra[camId][CAM_INT_FIFO_OVERWRITE](); - } - } - - if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_HCNT_INT)) { - CAM_IntClr(camId, CAM_INT_HSYNC_CNT_ERROR); - - if (camIntCbfArra[camId][CAM_INT_HSYNC_CNT_ERROR] != NULL) { - /* call the callback function */ - camIntCbfArra[camId][CAM_INT_HSYNC_CNT_ERROR](); - } - } - - if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_VCNT_INT)) { - CAM_IntClr(camId, CAM_INT_VSYNC_CNT_ERROR); - - if (camIntCbfArra[camId][CAM_INT_VSYNC_CNT_ERROR] != NULL) { - /* call the callback function */ - camIntCbfArra[camId][CAM_INT_VSYNC_CNT_ERROR](); - } - } -} -#endif - -/*@} end of group CAM_Private_Functions */ - -/** @defgroup CAM_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Camera module init - * - * @param camId: CAM ID type - * @param cfg: Camera configuration structure pointer - * - * @return None - * -*******************************************************************************/ -void CAM_Init(CAM_ID_Type camId, CAM_CFG_Type *cfg) -{ - uint32_t tmpVal; - uint32_t CAMx = camAddr[camId]; - - /* Check the parameters */ - CHECK_PARAM(IS_CAM_ID_TYPE(camId)); - CHECK_PARAM(IS_CAM_SW_MODE_TYPE(cfg->swMode)); - CHECK_PARAM(IS_CAM_INPUT_PIX_WIDTH_TYPE(cfg->pixWidth)); - CHECK_PARAM(IS_CAM_OUTPUT_DROP_MODE_TYPE(cfg->dropMode)); - CHECK_PARAM(IS_CAM_FRAME_ACTIVE_POL(cfg->framePol)); - CHECK_PARAM(IS_CAM_LINE_ACTIVE_POL(cfg->linePol)); - CHECK_PARAM(IS_CAM_BURST_TYPE(cfg->burstType)); - CHECK_PARAM(IS_CAM_SENSOR_MODE_TYPE(cfg->camSensorMode)); - - /* Disable clock gate */ - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_CAM); - - /* Set camera configuration */ - tmpVal = BL_RD_REG(CAMx, CAM_DVP2AXI_CONFIGUE); - tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_DVP_ENABLE); - BL_WR_REG(CAMx, CAM_DVP2AXI_CONFIGUE, tmpVal); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_SW_MODE, cfg->swMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_DVP_DATA_MODE, cfg->pixWidth); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_FRAM_VLD_POL, cfg->framePol); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_LINE_VLD_POL, cfg->linePol); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_XLEN, cfg->burstType); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_DVP_MODE, cfg->camSensorMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_DVP_WAIT_CYCLE, cfg->waitCount); - - switch (cfg->dropMode) { - case CAM_DROP_NONE: - tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_DROP_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_V_SUBSAMPLE_EN); - break; - - case CAM_DROP_ODD_ROW_ODD_PIXEL: - tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_DROP_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_V_SUBSAMPLE_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_V_SUBSAMPLE_POL); - break; - - case CAM_DROP_ODD_ROW_EVEN_PIXEL: - tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_DROP_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_V_SUBSAMPLE_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_V_SUBSAMPLE_POL); - break; - - case CAM_DROP_ALL_ODD_PIXEL: - tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_DROP_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_DROP_EVEN); - tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_V_SUBSAMPLE_EN); - break; - - case CAM_DROP_ALL_EVEN_PIXEL: - tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_DROP_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_DROP_EVEN); - tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_V_SUBSAMPLE_EN); - break; - - default: - break; - } - - BL_WR_REG(CAMx, CAM_DVP2AXI_CONFIGUE, tmpVal); - - /* Set frame count to issue interrupt at sw mode */ - tmpVal = BL_RD_REG(CAMx, CAM_DVP_STATUS_AND_ERROR); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_FRAME_CNT_TRGR_INT, cfg->swIntCnt); - BL_WR_REG(CAMx, CAM_DVP_STATUS_AND_ERROR, tmpVal); - - /* Set camera memory start address, memory brust size and frame byte size */ - BL_WR_REG(CAMx, CAM_DVP2AXI_ADDR_START, cfg->memStart & 0xFFFFFFF0); - - switch (cfg->burstType) { - case CAM_BURST_TYPE_SINGLE: - tmpVal = cfg->memSize / 8; - break; - - case CAM_BURST_TYPE_INCR4: - tmpVal = cfg->memSize / 32; - break; - - case CAM_BURST_TYPE_INCR8: - tmpVal = cfg->memSize / 64; - break; - - case CAM_BURST_TYPE_INCR16: - tmpVal = cfg->memSize / 128; - break; - - case CAM_BURST_TYPE_INCR32: - tmpVal = cfg->memSize / 256; - break; - - case CAM_BURST_TYPE_INCR64: - tmpVal = cfg->memSize / 512; - break; - - default: - tmpVal = 0; - break; - } - - BL_WR_REG(CAMx, CAM_DVP2AXI_MEM_BCNT, tmpVal); - - BL_WR_REG(CAMx, CAM_DVP2AXI_FRAME_BCNT, cfg->frameSize); - - /* Clear interrupt */ - BL_WR_REG(CAMx, CAM_DVP_FRAME_FIFO_POP, 0xFFFF0); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(DVP2BUS_INT0_IRQn, CAM0_IRQHandler); - Interrupt_Handler_Register(DVP2BUS_INT1_IRQn, CAM1_IRQHandler); - Interrupt_Handler_Register(DVP2BUS_INT2_IRQn, CAM2_IRQHandler); - Interrupt_Handler_Register(DVP2BUS_INT3_IRQn, CAM3_IRQHandler); - Interrupt_Handler_Register(DVP2BUS_INT4_IRQn, CAM4_IRQHandler); - Interrupt_Handler_Register(DVP2BUS_INT5_IRQn, CAM5_IRQHandler); - Interrupt_Handler_Register(DVP2BUS_INT6_IRQn, CAM6_IRQHandler); - Interrupt_Handler_Register(DVP2BUS_INT7_IRQn, CAM7_IRQHandler); -#endif -} - -/****************************************************************************/ /** - * @brief Deinit camera module - * - * @param camId: CAM ID type - * - * @return None - * -*******************************************************************************/ -void CAM_Deinit(CAM_ID_Type camId) -{ - switch(camId){ - case CAM0_ID: - GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_DVP2BUSA); - break; - case CAM1_ID: - GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_DVP2BUSB); - break; - case CAM2_ID: - GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_DVP2BUSC); - break; - case CAM3_ID: - GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_DVP2BUSD); - break; - case CAM4_ID: - GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_DVP2BUSE); - break; - case CAM5_ID: - GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_DVP2BUSF); - break; - case CAM6_ID: - GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_DVP2BUSG); - break; - case CAM7_ID: - GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_DVP2BUSH); - break; - default: - break; - } -} - -/****************************************************************************/ /** - * @brief Enable camera module - * - * @param camId: CAM ID type - * - * @return None - * -*******************************************************************************/ -void CAM_Enable(CAM_ID_Type camId) -{ - uint32_t tmpVal; - uint32_t CAMx = camAddr[camId]; - - /* Check the parameters */ - CHECK_PARAM(IS_CAM_ID_TYPE(camId)); - - /* Enable camera module */ - tmpVal = BL_RD_REG(CAMx, CAM_DVP2AXI_CONFIGUE); - tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_DVP_ENABLE); - BL_WR_REG(CAMx, CAM_DVP2AXI_CONFIGUE, tmpVal); -} - -/****************************************************************************/ /** - * @brief Disable camera module - * - * @param camId: CAM ID type - * - * @return None - * -*******************************************************************************/ -void CAM_Disable(CAM_ID_Type camId) -{ - uint32_t tmpVal; - uint32_t CAMx = camAddr[camId]; - - /* Check the parameters */ - CHECK_PARAM(IS_CAM_ID_TYPE(camId)); - - /* Disable camera module */ - tmpVal = BL_RD_REG(CAMx, CAM_DVP2AXI_CONFIGUE); - tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_DVP_ENABLE); - BL_WR_REG(CAMx, CAM_DVP2AXI_CONFIGUE, tmpVal); -} - -/****************************************************************************/ /** - * @brief Camera clock gate function - * - * @param camId: CAM ID type - * @param enable: Enable or disable - * - * @return None - * -*******************************************************************************/ -void CAM_Clock_Gate(CAM_ID_Type camId, BL_Fun_Type enable) -{ - uint32_t tmpVal; - uint32_t CAMx = camAddr[camId]; - - /* Check the parameters */ - CHECK_PARAM(IS_CAM_ID_TYPE(camId)); - - tmpVal = BL_RD_REG(CAMx, CAM_DVP2AXI_CONFIGUE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_DVP_PIX_CLK_CG, enable); - BL_WR_REG(CAMx, CAM_DVP2AXI_CONFIGUE, tmpVal); -} - -/****************************************************************************/ /** - * @brief Camera hsync crop function - * - * @param camId: CAM ID type - * @param start: Valid hsync start count - * @param end: Valid hsync end count - * - * @return None - * -*******************************************************************************/ -void CAM_Hsync_Crop(CAM_ID_Type camId, uint16_t start, uint16_t end) -{ - uint32_t CAMx = camAddr[camId]; - - /* Check the parameters */ - CHECK_PARAM(IS_CAM_ID_TYPE(camId)); - - BL_WR_REG(CAMx, CAM_DVP2AXI_HSYNC_CROP, (start << 16) + end); -} - -/****************************************************************************/ /** - * @brief Camera vsync crop function - * - * @param camId: CAM ID type - * @param start: Valid vsync start count - * @param end: Valid vsync end count - * - * @return None - * -*******************************************************************************/ -void CAM_Vsync_Crop(CAM_ID_Type camId, uint16_t start, uint16_t end) -{ - uint32_t CAMx = camAddr[camId]; - - /* Check the parameters */ - CHECK_PARAM(IS_CAM_ID_TYPE(camId)); - - BL_WR_REG(CAMx, CAM_DVP2AXI_VSYNC_CROP, (start << 16) + end); -} - -/****************************************************************************/ /** - * @brief Camera set total valid pix count in a line function - * - * @param camId: CAM ID type - * @param count: Count value - * - * @return None - * -*******************************************************************************/ -void CAM_Set_Hsync_Total_Count(CAM_ID_Type camId, uint16_t count) -{ - uint32_t tmpVal; - uint32_t CAMx = camAddr[camId]; - - /* Check the parameters */ - CHECK_PARAM(IS_CAM_ID_TYPE(camId)); - - tmpVal = BL_RD_REG(CAMx, CAM_DVP2AXI_FRAM_EXM); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_TOTAL_HCNT, count); - BL_WR_REG(CAMx, CAM_DVP2AXI_FRAM_EXM, tmpVal); -} - -/****************************************************************************/ /** - * @brief Camera set total valid line count in a frame function - * - * @param camId: CAM ID type - * @param count: Count value - * - * @return None - * -*******************************************************************************/ -void CAM_Set_Vsync_Total_Count(CAM_ID_Type camId, uint16_t count) -{ - uint32_t tmpVal; - uint32_t CAMx = camAddr[camId]; - - /* Check the parameters */ - CHECK_PARAM(IS_CAM_ID_TYPE(camId)); - - tmpVal = BL_RD_REG(CAMx, CAM_DVP2AXI_FRAM_EXM); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_TOTAL_VCNT, count); - BL_WR_REG(CAMx, CAM_DVP2AXI_FRAM_EXM, tmpVal); -} - -/****************************************************************************/ /** - * @brief Get one camera frame - * - * @param camId: CAM ID type - * @param info: Camera frame infomation pointer - * - * @return None - * -*******************************************************************************/ -void CAM_Get_Frame_Info(CAM_ID_Type camId, CAM_Frame_Info *info) -{ - uint32_t tmpVal; - uint32_t CAMx = camAddr[camId]; - - /* Check the parameters */ - CHECK_PARAM(IS_CAM_ID_TYPE(camId)); - - tmpVal = BL_RD_REG(CAMx, CAM_DVP_STATUS_AND_ERROR); - - info->validFrames = BL_GET_REG_BITS_VAL(tmpVal, CAM_FRAME_VALID_CNT); - info->curFrameId = BL_GET_REG_BITS_VAL(BL_RD_REG(CAMx, CAM_FRAME_ID_STS01), CAM_FRAME_ID_0); - info->curFrameAddr = BL_RD_REG(CAMx, CAM_FRAME_START_ADDR0); - info->curFrameBytes = BL_RD_REG(CAMx, CAM_DVP2AXI_FRAME_BCNT); - info->status = tmpVal; -} - -/****************************************************************************/ /** - * @brief Get available count of frames - * - * @param camId: CAM ID type - * - * @return Frames count - * -*******************************************************************************/ -uint8_t CAM_Get_Frame_Count(CAM_ID_Type camId) -{ - uint32_t CAMx = camAddr[camId]; - - /* Check the parameters */ - CHECK_PARAM(IS_CAM_ID_TYPE(camId)); - - return BL_GET_REG_BITS_VAL(BL_RD_REG(CAMx, CAM_DVP_STATUS_AND_ERROR), CAM_FRAME_VALID_CNT); -} - -/****************************************************************************/ /** - * @brief Pop one camera frame - * - * @param camId: CAM ID type - * - * @return None - * -*******************************************************************************/ -void CAM_Pop_Frame(CAM_ID_Type camId) -{ - uint32_t CAMx = camAddr[camId]; - - /* Check the parameters */ - CHECK_PARAM(IS_CAM_ID_TYPE(camId)); - - /* Pop one frame */ - BL_WR_REG(CAMx, CAM_DVP_FRAME_FIFO_POP, 1); -} - -/****************************************************************************/ /** - * @brief CAMERA Enable Disable Interrupt - * - * @param camId: CAM ID type - * @param intType: CAMERA Interrupt Type - * @param intMask: Enable or Disable - * - * @return None - * -*******************************************************************************/ -void CAM_IntMask(CAM_ID_Type camId, CAM_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpVal; - uint32_t CAMx = camAddr[camId]; - - /* Check the parameters */ - CHECK_PARAM(IS_CAM_ID_TYPE(camId)); - CHECK_PARAM(IS_CAM_INT_TYPE(intType)); - CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); - - tmpVal = BL_RD_REG(CAMx, CAM_DVP_STATUS_AND_ERROR); - - switch (intType) { - case CAM_INT_NORMAL: - if (intMask == UNMASK) { - /* Enable this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_NORMAL_EN); - } else { - /* Disable this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_INT_NORMAL_EN); - } - - break; - - case CAM_INT_MEMORY_OVERWRITE: - if (intMask == UNMASK) { - /* Enable this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_MEM_EN); - } else { - /* Disable this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_INT_MEM_EN); - } - - break; - - case CAM_INT_FRAME_OVERWRITE: - if (intMask == UNMASK) { - /* Enable this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_FRAME_EN); - } else { - /* Disable this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_INT_FRAME_EN); - } - - break; - - case CAM_INT_FIFO_OVERWRITE: - if (intMask == UNMASK) { - /* Enable this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_FIFO_EN); - } else { - /* Disable this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_INT_FIFO_EN); - } - - break; - - case CAM_INT_VSYNC_CNT_ERROR: - if (intMask == UNMASK) { - /* Enable this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_VCNT_EN); - } else { - /* Disable this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_INT_VCNT_EN); - } - - break; - - case CAM_INT_HSYNC_CNT_ERROR: - if (intMask == UNMASK) { - /* Enable this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_HCNT_EN); - } else { - /* Disable this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_INT_HCNT_EN); - } - - break; - - case CAM_INT_ALL: - if (intMask == UNMASK) { - /* Enable all interrupt */ - tmpVal |= 0xFC0; - } else { - /* Disable all interrupt */ - tmpVal &= 0xFFFFF03F; - } - - break; - - default: - break; - } - - BL_WR_REG(CAMx, CAM_DVP_STATUS_AND_ERROR, tmpVal); -} - -/****************************************************************************/ /** - * @brief CAMERA Interrupt Clear - * - * @param camId: CAM ID type - * @param intType: CAMERA Interrupt Type - * - * @return None - * -*******************************************************************************/ -void CAM_IntClr(CAM_ID_Type camId, CAM_INT_Type intType) -{ - uint32_t tmpVal; - uint32_t CAMx = camAddr[camId]; - - /* Check the parameters */ - CHECK_PARAM(IS_CAM_ID_TYPE(camId)); - - tmpVal = BL_RD_REG(CAMx, CAM_DVP_FRAME_FIFO_POP); - - switch (intType) { - case CAM_INT_NORMAL: - tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_NORMAL_CLR); - break; - - case CAM_INT_MEMORY_OVERWRITE: - tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_MEM_CLR); - break; - - case CAM_INT_FRAME_OVERWRITE: - tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_FRAME_CLR); - break; - - case CAM_INT_FIFO_OVERWRITE: - tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_FIFO_CLR); - break; - - case CAM_INT_VSYNC_CNT_ERROR: - tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_VCNT_CLR); - break; - - case CAM_INT_HSYNC_CNT_ERROR: - tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_HCNT_CLR); - break; - - case CAM_INT_ALL: - tmpVal = 0xFFFF0; - - default: - break; - } - - BL_WR_REG(CAMx, CAM_DVP_FRAME_FIFO_POP, tmpVal); -} - -/****************************************************************************/ /** - * @brief Install camera interrupt callback function - * - * @param camId: CAM ID type - * @param intType: CAMERA interrupt type - * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void CAM_Int_Callback_Install(CAM_ID_Type camId, CAM_INT_Type intType, intCallback_Type *cbFun) -{ - /* Check the parameters */ - CHECK_PARAM(IS_CAM_ID_TYPE(camId)); - CHECK_PARAM(IS_CAM_INT_TYPE(intType)); - - camIntCbfArra[camId][intType] = cbFun; -} -#endif - -/****************************************************************************/ /** - * @brief CAMERA input 8-bit mode lower/upper byte select function - * - * @param camId: CAM ID type - * @param byteType: Byte type - * - * @return None - * -*******************************************************************************/ -void CAM_8_Bit_Byte_Select(CAM_ID_Type camId, CAM_8_Bit_Byte_Type byteType) -{ - uint32_t tmpVal; - uint32_t CAMx = camAddr[camId]; - - /* Check the parameters */ - CHECK_PARAM(IS_CAM_ID_TYPE(camId)); - CHECK_PARAM(IS_CAM_8_BIT_BYTE_TYPE(byteType)); - - tmpVal = BL_RD_REG(CAMx, CAM_DVP2AXI_CONFIGUE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_DVP_DATA_BSEL, byteType); - BL_WR_REG(CAMx, CAM_DVP2AXI_CONFIGUE, tmpVal); -} - -/****************************************************************************/ /** - * @brief CAMERA input 16-bit mode RGB order select function - * - * @param camId: CAM ID type - * @param rgbType: RGB order type - * - * @return None - * -*******************************************************************************/ -void CAM_16_Bit_RGB_order(CAM_ID_Type camId, CAM_16_Bit_RGB_Type rgbType) -{ - uint32_t tmpVal; - uint32_t CAMx = camAddr[camId]; - - /* Check the parameters */ - CHECK_PARAM(IS_CAM_ID_TYPE(camId)); - CHECK_PARAM(IS_CAM_16_BIT_RGB_TYPE(rgbType)); - - tmpVal = BL_RD_REG(CAMx, CAM_DVP2AXI_MISC); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_FORMAT_565, rgbType); - BL_WR_REG(CAMx, CAM_DVP2AXI_MISC, tmpVal); -} - -/****************************************************************************/ /** - * @brief CAMERA input 32-bit mode alpha value set function - * - * @param camId: CAM ID type - * @param alpha: Alpha value - * - * @return None - * -*******************************************************************************/ -void CAM_32_Bit_Alpha_Set(CAM_ID_Type camId, uint8_t alpha) -{ - uint32_t tmpVal; - uint32_t CAMx = camAddr[camId]; - - /* Check the parameters */ - CHECK_PARAM(IS_CAM_ID_TYPE(camId)); - - tmpVal = BL_RD_REG(CAMx, CAM_DVP2AXI_MISC); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_ALPHA, alpha); - BL_WR_REG(CAMx, CAM_DVP2AXI_MISC, tmpVal); -} - -/****************************************************************************/ /** - * @brief CAMERA set frame period and bitwise frame valid in period function - * - * @param camId: CAM ID type - * @param period: Frame period count - * @param validBit: Bitwise frame valid in period - * - * @return None - * -*******************************************************************************/ -void CAM_Set_Frame_Valid_Period(CAM_ID_Type camId, uint8_t period, uint32_t validBit) -{ - uint32_t tmpVal; - uint32_t CAMx = camAddr[camId]; - - /* Check the parameters */ - CHECK_PARAM(IS_CAM_ID_TYPE(camId)); - - tmpVal = BL_RD_REG(CAMx, CAM_DVP2AXI_FRAME_PERIOD); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_FRAME_PERIOD, period); - BL_WR_REG(CAMx, CAM_DVP2AXI_FRAME_PERIOD, tmpVal); - - BL_WR_REG(CAMx, CAM_DVP2AXI_FRAME_VLD, validBit); -} - -/****************************************************************************/ /** - * @brief Enable or disable function that covers first frame memory everytime in hardware mode - * - * @param camId: CAM ID type - * @param enable: Enable or disable - * - * @return None - * -*******************************************************************************/ -void CAM_HW_Cover_First_Frame_Everytime(CAM_ID_Type camId, BL_Fun_Type enable) -{ - uint32_t tmpVal; - uint32_t CAMx = camAddr[camId]; - - /* Check the parameters */ - CHECK_PARAM(IS_CAM_ID_TYPE(camId)); - - tmpVal = BL_RD_REG(CAMx, CAM_DVP2AXI_CONFIGUE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_HW_MODE_FWRAP, enable); - BL_WR_REG(CAMx, CAM_DVP2AXI_CONFIGUE, tmpVal); -} - -/****************************************************************************/ /** - * @brief Camera 0 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void CAM0_IRQHandler(void) -{ - CAM_IntHandler(CAM0_ID); -} -#endif - -/****************************************************************************/ /** - * @brief Camera 1 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void CAM1_IRQHandler(void) -{ - CAM_IntHandler(CAM1_ID); -} -#endif - -/****************************************************************************/ /** - * @brief Camera 2 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void CAM2_IRQHandler(void) -{ - CAM_IntHandler(CAM2_ID); -} -#endif - -/****************************************************************************/ /** - * @brief Camera 3 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void CAM3_IRQHandler(void) -{ - CAM_IntHandler(CAM3_ID); -} -#endif - -/****************************************************************************/ /** - * @brief Camera 4 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void CAM4_IRQHandler(void) -{ - CAM_IntHandler(CAM4_ID); -} -#endif - -/****************************************************************************/ /** - * @brief Camera 5 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void CAM5_IRQHandler(void) -{ - CAM_IntHandler(CAM5_ID); -} -#endif - -/****************************************************************************/ /** - * @brief Camera 6 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void CAM6_IRQHandler(void) -{ - CAM_IntHandler(CAM6_ID); -} -#endif - -/****************************************************************************/ /** - * @brief Camera 7 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void CAM7_IRQHandler(void) -{ - CAM_IntHandler(CAM7_ID); -} -#endif - -/*@} end of group CAM_Public_Functions */ - -/*@} end of group CAM */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_can.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_can.c deleted file mode 100644 index 9690d01f11..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_can.c +++ /dev/null @@ -1,671 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_can.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_glb.h" -#include "bl808_can.h" -#include "bflb_platform.h" - -#ifndef BFLB_USE_HAL_DRIVER -static intCallback_Type * canIntCbfArra[CAN_INT_ALL] = { NULL }; -static void CAN_IntHandler(void); -static void CAN_IRQHandler(void); -#endif - -void CAN_Init(void) -{ - uint32_t tmpVal; - - /* Enable CAN clock witch share with UART2 */ - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_UART2); - - /* Enable UART clock*/ - tmpVal=BL_RD_REG(GLB_BASE,GLB_UART_CFG0); - tmpVal=BL_SET_REG_BIT(tmpVal,GLB_UART_CLK_EN); - BL_WR_REG(GLB_BASE,GLB_UART_CFG0,tmpVal); - - /* UART2 and CAN can not work together */ - GLB_Set_UART2_IO_Sel(GLB_UART2_IO_SEL_CAN_FD); - - /* Need to enter reset mode before operating */ - CAN_Mode_Set(CAN_MODE_TYPE_RESET, CAN_MODE_VALUE_RESET); - - /* Force using PeliCAN not BasicCAN */ - tmpVal = BL_RD_REG(CAN_BASE, CAN_CLOCK_DIVIDER); - tmpVal = BL_SET_REG_BIT(tmpVal, CAN_MODE); - BL_WR_REG(CAN_BASE, CAN_CLOCK_DIVIDER, tmpVal); - - /* Disable all interrupts */ - BL_WR_REG(CAN_BASE, CAN_INTERRUPT_ENABLE, 0); - - /* Set clock and sample point */ - CAN_Clock_Div_Set(0); - CAN_Synchronization_Jump_Width_Set(3); - CAN_Sample_Parameter_Set(1, 8, 5); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(UART2_IRQn, CAN_IRQHandler); -#endif -} - -void CAN_Mode_Set(CAN_MODE_Type type, CAN_MODE_VALUE_Type value) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_CAN_MODE_TYPE(type)); - CHECK_PARAM(IS_CAN_MODE_VALUE_TYPE(value)); - - /* Set mode value */ - tmpVal = BL_RD_REG(CAN_BASE, CAN_MODE); - tmpVal &= ~(1 << type); - tmpVal |= (value << type); - - /* Write back */ - BL_WR_REG(CAN_BASE, CAN_MODE, tmpVal); -} - -CAN_MODE_VALUE_Type CAN_Mode_Get(CAN_MODE_Type type) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_CAN_MODE_TYPE(type)); - - tmpVal = BL_RD_REG(CAN_BASE, CAN_MODE); - tmpVal &= (1 << type); - tmpVal >>= type; - return (CAN_MODE_VALUE_Type)tmpVal; -} - -void CAN_Int_Enable(CAN_INT_Type intType, BL_Fun_Type enable) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_CAN_INT_TYPE(intType)); - - tmpVal = BL_RD_REG(CAN_BASE, CAN_INTERRUPT_ENABLE); - /* Enable or Disable certain or all interrupt */ - if(CAN_INT_ALL == intType){ - if(ENABLE == enable){ - tmpVal |= 0xFF; - }else{ - tmpVal &= 0; - } - }else{ - if(ENABLE == enable){ - tmpVal |= 1<>= type; - return (CAN_STATUS_VALUE_Type)tmpVal; -} - -uint8_t CAN_Arbitration_Lost_Position_Get(void) -{ - uint8_t tmpVal; - - tmpVal = BL_RD_REG(CAN_BASE, CAN_ARB_LOST_CAPTURE); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, CAN_ALC4_0); - return tmpVal; -} - -void CAN_Error_Get(CAN_ERROR_Type *const type) -{ - uint8_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_CAN_FRAME_FORMAT_TYPE(type)); - - tmpVal = BL_RD_REG(CAN_BASE, CAN_ERROR_CODE_CAPTURE); - type->code = BL_GET_REG_BITS_VAL(tmpVal, CAN_ERR_CODE); - type->dir = BL_GET_REG_BITS_VAL(tmpVal, CAN_DIR); - type->location = BL_GET_REG_BITS_VAL(tmpVal, CAN_SEGMENT4_0); -} - -BL_Err_Type CAN_Error_Warning_Limit_Set(uint8_t limit) -{ - if(CAN_MODE_VALUE_NORMAL == CAN_Mode_Get(CAN_MODE_TYPE_RESET)) - { - return ERROR; - } - BL_WR_REG(CAN_BASE, CAN_ERROR_WARNING_LIMIT, limit); - return SUCCESS; -} - -uint8_t CAN_Error_Warning_Limit_Get(void) -{ - return BL_RD_REG(CAN_BASE, CAN_ERROR_WARNING_LIMIT); -} - -uint8_t CAN_Error_Rx_Counter_Get(void) -{ - return BL_RD_REG(CAN_BASE, CAN_RX_ERR_COUNT); -} - -uint8_t CAN_Error_Tx_Counter_Get(void) -{ - return BL_RD_REG(CAN_BASE, CAN_TX_ERR_COUNT); -} - -BL_Err_Type CAN_Transmit(const CAN_CFG_Type *cfg) -{ - uint32_t timeOut; - uint32_t tmpVal; - uint32_t i; - volatile uint32_t *pData; - - /* Check the parameters */ - CHECK_PARAM(IS_CAN_FRAME_FORMAT_TYPE(cfg->dataAddr)); - CHECK_PARAM(IS_CAN_FRAME_TYPE(cfg->frameType)); - CHECK_PARAM(IS_CAN_FRAME_FORMAT_TYPE(cfg->frameFormat)); - - timeOut = cfg->timeout; - - /* Chcek Timeout type */ - while(CAN_STATUS_TRANSMIT_BUFFER_LOCKED == CAN_Status_Get(CAN_STATUS_TRANSMIT_BUFFER)) - { - /* Wait no time */ - if (cfg->timeout == 0) - { - return TIMEOUT; - } - /* Wait until transmit buffer accessible */ - if (cfg->timeout >= CAN_TIMEOUT_MAX) - { - - } - /* Wait time = cfg->timeOut */ - else - { - if(timeOut == 0) - { - return TIMEOUT; - } - timeOut--; - } - } - - /* Config information register */ - tmpVal = cfg->dataLen; - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAN_INF_FF, cfg->frameFormat); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAN_INF_RTR, cfg->frameType); - BL_WR_REG(CAN_BASE, CAN_INFORMATION, tmpVal); - - tmpVal = cfg->id; - /* Transmit format with 11 bits ID, SFF */ - if(CAN_FRAME_FORMAT_STANDARD == cfg->frameFormat) - { - /* Config identifier registers */ - BL_WR_REG(CAN_BASE, CAN_IDENTIFIER_1, (tmpVal >> 3) & 0xFF); - tmpVal <<= 5; - tmpVal |= (cfg->frameType << 4); - BL_WR_REG(CAN_BASE, CAN_IDENTIFIER_2, tmpVal & 0xFF); - /* Config SFF data registers start address */ - pData = (uint32_t *)(CAN_BASE + CAN_SFF_DATA_1_OFFSET); - } - /* Transmit format with 29 bits ID, EFF */ - else - { - /* Config identifier registers */ - BL_WR_REG(CAN_BASE, CAN_IDENTIFIER_1, (tmpVal >> 21) & 0xFF); - BL_WR_REG(CAN_BASE, CAN_IDENTIFIER_2, (tmpVal >> 13) & 0xFF); - BL_WR_REG(CAN_BASE, CAN_IDENTIFIER_3, (tmpVal >> 5) & 0xFF); - tmpVal <<= 3; - tmpVal |= (cfg->frameType << 2); - BL_WR_REG(CAN_BASE, CAN_IDENTIFIER_4, tmpVal & 0xFF); - /* Config EFF data registers start address */ - pData = (uint32_t *)(CAN_BASE + CAN_EFF_DATA_1_OFFSET); - } - /* Move data from user buff to registers */ - for (i = 0; i < cfg->dataLen; i++) - { - *(pData + i) = (uint32_t)(*(cfg->dataAddr + i)); - } - - /* Trig a request for transmit */ - if(CAN_MODE_VALUE_RESET == CAN_Mode_Get(CAN_MODE_TYPE_RESET)) - { - return ERROR; - } - else if(CAN_MODE_VALUE_LISTEN_ONLY == CAN_Mode_Get(CAN_MODE_TYPE_LISTEN_ONLY)) - { - return ERROR; - } - else if(CAN_MODE_VALUE_SELF_TSET == CAN_Mode_Get(CAN_MODE_TYPE_SELF_TSET)) - { - CAN_Cmd_Request_Self_Reception(); - } - else - { - CAN_Cmd_Request_Transmit(); - } - - return SUCCESS; -} - -BL_Err_Type CAN_Receive(CAN_CFG_Type *cfg) -{ - uint32_t timeOut; - uint32_t tmpVal; - uint32_t i; - uint32_t id; - volatile uint32_t *pData; - - /* Check the parameters */ - CHECK_PARAM(IS_CAN_FRAME_FORMAT_TYPE(cfg->dataAddr)); - - timeOut = cfg->timeout; - - /* Chcek Timeout type */ - while(CAN_STATUS_RECEIVE_BUFFER_EMPTY == CAN_Status_Get(CAN_STATUS_RECEIVE_BUFFER)) - { - /* Wait no time */ - if (cfg->timeout == 0) - { - return TIMEOUT; - } - /* Wait until transmit buffer accessible */ - if (cfg->timeout >= CAN_TIMEOUT_MAX) - { - - } - /* Wait time = cfg->timeOut */ - else - { - if(timeOut == 0) - { - return TIMEOUT; - } - timeOut--; - } - } - - /* Read information register */ - tmpVal = BL_RD_REG(CAN_BASE, CAN_INFORMATION); - cfg->frameFormat = BL_GET_REG_BITS_VAL(tmpVal, CAN_INF_FF); - cfg->frameType = BL_GET_REG_BITS_VAL(tmpVal, CAN_INF_RTR); - cfg->dataLen = BL_GET_REG_BITS_VAL(tmpVal, CAN_INF_DLC); - - /* Receive with 11 bits ID */ - if(CAN_FRAME_FORMAT_STANDARD == cfg->frameFormat) - { - /* Read identifier registers */ - tmpVal = BL_RD_REG(CAN_BASE, CAN_IDENTIFIER_1); - id = ((tmpVal & 0xFF) << 3); - tmpVal = BL_RD_REG(CAN_BASE, CAN_IDENTIFIER_2); - id |= (tmpVal & 0xFF) >> 5; - /* Config SFF data registers start address */ - pData = (uint32_t *)(CAN_BASE + CAN_SFF_DATA_1_OFFSET); - } - /* Receive with 29 bits ID */ - else - { - /* Read identifier registers */ - tmpVal = BL_RD_REG(CAN_BASE, CAN_IDENTIFIER_1); - id = ((tmpVal & 0xFF) << 21); - tmpVal = BL_RD_REG(CAN_BASE, CAN_IDENTIFIER_2); - id |= (tmpVal & 0xFF) << 13; - tmpVal = BL_RD_REG(CAN_BASE, CAN_IDENTIFIER_3); - id |= (tmpVal & 0xFF) << 5; - tmpVal = BL_RD_REG(CAN_BASE, CAN_IDENTIFIER_4); - id |= (tmpVal & 0xFF) >> 3; - /* Config EFF data registers start address */ - pData = (uint32_t *)(CAN_BASE + CAN_EFF_DATA_1_OFFSET); - } - cfg->id = id; - - /* Move data from registers to user buff */ - for (i = 0; i < cfg->dataLen; i++) - { - *(cfg->dataAddr + i) = (uint8_t)(*(pData + i) & 0xFF); - } - - CAN_Cmd_Release_Recv_Buff(); - - return SUCCESS; -} - -uint8_t CAN_Receive_Buff_Frame_Count_Get(void) -{ - volatile uint32_t tmpVal; - - tmpVal = BL_RD_REG(CAN_BASE, CAN_RX_MESSAGE_COUNT); - return (uint8_t)(tmpVal & 0xFF); -} - -BL_Err_Type CAN_Clock_Div_Set(uint8_t div) -{ - uint32_t tmpVal; - - /* Must be operated in reset mode */ - if (CAN_MODE_VALUE_NORMAL == CAN_Mode_Get(CAN_MODE_TYPE_RESET)) - { - return ERROR; - } - - tmpVal = BL_RD_REG(CAN_BASE, CAN_BUS_TIMING_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAN_BAUD_RATE_PRESCALER, div); - BL_WR_REG(CAN_BASE, CAN_BUS_TIMING_0, tmpVal); - - return SUCCESS; -} - -uint8_t CAN_Clock_Div_Get(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(CAN_BASE, CAN_BUS_TIMING_0); - return (uint8_t)BL_GET_REG_BITS_VAL(tmpVal, CAN_BAUD_RATE_PRESCALER); -} - -BL_Err_Type CAN_Synchronization_Jump_Width_Set(uint8_t width) -{ - uint32_t tmpVal; - - /* Must be operated in reset mode */ - if (CAN_MODE_VALUE_NORMAL == CAN_Mode_Get(CAN_MODE_TYPE_RESET)) - { - return ERROR; - } - - tmpVal = BL_RD_REG(CAN_BASE, CAN_BUS_TIMING_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAN_SYNC_JUMP_WIDTH, width); - BL_WR_REG(CAN_BASE, CAN_BUS_TIMING_0, tmpVal); - - return SUCCESS; -} - -uint8_t CAN_Synchronization_Jump_Width_Get(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(CAN_BASE, CAN_BUS_TIMING_0); - return (uint8_t)BL_GET_REG_BITS_VAL(tmpVal, CAN_SYNC_JUMP_WIDTH); -} - -BL_Err_Type CAN_Sample_Parameter_Set(uint8_t num, uint8_t head, uint8_t tail) -{ - uint32_t tmpVal = 0; - - /* Must be operated in reset mode */ - if (CAN_MODE_VALUE_NORMAL == CAN_Mode_Get(CAN_MODE_TYPE_RESET)) - { - return ERROR; - } - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAN_TIME_SEGMENT_1, head); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAN_TIME_SEGMENT_2, tail); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAN_SAMPLING, num); - BL_WR_REG(CAN_BASE, CAN_BUS_TIMING_1, tmpVal & 0xFF); - - return SUCCESS; -} - -void CAN_Sample_Parameter_Get(uint8_t *num, uint8_t *head, uint8_t *tail) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(CAN_BASE, CAN_BUS_TIMING_1); - *head = (uint8_t)BL_GET_REG_BITS_VAL(tmpVal, CAN_TIME_SEGMENT_1); - *tail = (uint8_t)BL_GET_REG_BITS_VAL(tmpVal, CAN_TIME_SEGMENT_2); - *num = (uint8_t)BL_GET_REG_BITS_VAL(tmpVal, CAN_SAMPLING); -} - -void CAN_Filter_Set(const CAN_FILTER_CFG_Type *cfg) -{ - uint8_t tmpVal[8] = {0}; //tmpVal[0~3] for match, tmpVal[4~7] for mask - - /* Config filter must be in reset mode */ - CAN_MODE_VALUE_Type modeReset = CAN_Mode_Get(CAN_MODE_TYPE_RESET); - CAN_Mode_Set(CAN_MODE_TYPE_RESET, CAN_MODE_VALUE_RESET); - - - /* Single filter mode */ - if (CAN_MODE_VALUE_ACCEPTANCE_FILTER_SINGLE == cfg->filterMode) - { - CAN_Mode_Set(CAN_MODE_TYPE_ACCEPTANCE_FILTER, CAN_MODE_VALUE_ACCEPTANCE_FILTER_SINGLE); - /* Filter: ID10~0 + RTR + Data1 + Data2 */ - if (CAN_FRAME_FORMAT_STANDARD == cfg->formatType) - { - tmpVal[0] = (uint8_t)(cfg->matchId1 >> 3); - tmpVal[1] = (uint8_t)(cfg->matchId1 << 5); - tmpVal[1] |= (uint8_t)(cfg->matchRtr1 << 4); - tmpVal[2] = cfg->matchData1; - tmpVal[3] = cfg->matchData2; - tmpVal[4] = (uint8_t)(cfg->maskId1 >> 3); - tmpVal[5] = (uint8_t)(cfg->maskId1 << 5); - tmpVal[5] |= (uint8_t)(cfg->maskRtr1 << 4); - tmpVal[5] |= (uint8_t)0x0F;//0b1111 for unused bit 3:0 - tmpVal[6] = cfg->maskData1; - tmpVal[7] = cfg->maskData2; - } - /* Filter: ID28~0 + RTR */ - else if(CAN_FRAME_FORMAT_EXTENDED == cfg->formatType) - { - tmpVal[0] = (uint8_t)(cfg->matchId1 >> 21); - tmpVal[1] = (uint8_t)(cfg->matchId1 >> 13); - tmpVal[2] = (uint8_t)(cfg->matchId1 >> 5); - tmpVal[3] = (uint8_t)(cfg->matchId1 << 3); - tmpVal[3] |= (uint8_t)(cfg->matchRtr1 << 2); - tmpVal[4] = (uint8_t)(cfg->maskId1 >> 21); - tmpVal[5] = (uint8_t)(cfg->maskId1 >> 13); - tmpVal[6] = (uint8_t)(cfg->maskId1 >> 5); - tmpVal[7] = (uint8_t)(cfg->maskId1 << 3); - tmpVal[7] |= (uint8_t)(cfg->maskRtr1 << 2); - tmpVal[7] |= (uint8_t)0x03;//0b11 for unused bit 1:0 - } - } - /* Dual filter mode */ - else if (CAN_MODE_VALUE_ACCEPTANCE_FILTER_DUAL == cfg->filterMode) - { - CAN_Mode_Set(CAN_MODE_TYPE_ACCEPTANCE_FILTER, CAN_MODE_VALUE_ACCEPTANCE_FILTER_DUAL); - /* Filter1: ID10~0 + RTR + Data1 */ - /* Filter2: ID10~0 + RTR */ - if (CAN_FRAME_FORMAT_STANDARD == cfg->formatType) - { - tmpVal[0] = (uint8_t)(cfg->matchId1 >> 3); - tmpVal[1] = (uint8_t)(cfg->matchId1 << 5); - tmpVal[1] |= (uint8_t)(cfg->matchRtr1 << 4); - tmpVal[1] |= (cfg->matchData1 >> 4); - tmpVal[2] = (uint8_t)(cfg->matchId2 >> 3); - tmpVal[3] = (uint8_t)(cfg->matchId2 << 5); - tmpVal[3] |= (uint8_t)(cfg->matchRtr2 << 4); - tmpVal[3] |= (cfg->matchData1 & 0xF); - tmpVal[4] = (uint8_t)(cfg->maskId1 >> 3); - tmpVal[5] = (uint8_t)(cfg->maskId1 << 5); - tmpVal[5] |= (uint8_t)(cfg->maskRtr1 << 4); - tmpVal[5] |= (cfg->maskData1 >> 4); - tmpVal[6] = (uint8_t)(cfg->maskId2 >> 3); - tmpVal[7] = (uint8_t)(cfg->maskId2 << 5); - tmpVal[7] |= (uint8_t)(cfg->maskRtr2 << 4); - tmpVal[7] |= (cfg->maskData1 & 0xF); - } - /* Filter1: ID28~13 */ - /* Filter2: ID28~13 */ - else if (CAN_FRAME_FORMAT_EXTENDED == cfg->formatType) - { - tmpVal[0] = (uint8_t)(cfg->matchId1 >> 21); - tmpVal[1] = (uint8_t)(cfg->matchId1 >> 13); - tmpVal[2] = (uint8_t)(cfg->matchId2 >> 21); - tmpVal[3] = (uint8_t)(cfg->matchId2 >> 13); - tmpVal[4] = (uint8_t)(cfg->maskId1 >> 21); - tmpVal[5] = (uint8_t)(cfg->maskId1 >> 13); - tmpVal[6] = (uint8_t)(cfg->maskId2 >> 21); - tmpVal[7] = (uint8_t)(cfg->maskId2 >> 13); - } - } - /* Write configuration to Registers*/ - BL_WR_REG(CAN_BASE, CAN_FILTER_ACCEPTANCE_0, (uint32_t)tmpVal[0]); - BL_WR_REG(CAN_BASE, CAN_FILTER_ACCEPTANCE_1, (uint32_t)tmpVal[1]); - BL_WR_REG(CAN_BASE, CAN_FILTER_ACCEPTANCE_2, (uint32_t)tmpVal[2]); - BL_WR_REG(CAN_BASE, CAN_FILTER_ACCEPTANCE_3, (uint32_t)tmpVal[3]); - BL_WR_REG(CAN_BASE, CAN_FILTER_Mask_0, (uint32_t)tmpVal[4]); - BL_WR_REG(CAN_BASE, CAN_FILTER_Mask_1, (uint32_t)tmpVal[5]); - BL_WR_REG(CAN_BASE, CAN_FILTER_Mask_2, (uint32_t)tmpVal[6]); - BL_WR_REG(CAN_BASE, CAN_FILTER_Mask_3, (uint32_t)tmpVal[7]); - - /* Recovery reset mode value */ - CAN_Mode_Set(CAN_MODE_TYPE_RESET, modeReset); -} - -void CAN_Filter_Register_Set(CAN_FILTER_REGISTER_Type reg, uint8_t value) -{ - /* Config filter must be in reset mode */ - CAN_MODE_VALUE_Type modeReset = CAN_Mode_Get(CAN_MODE_TYPE_RESET); - CAN_Mode_Set(CAN_MODE_TYPE_RESET, CAN_MODE_VALUE_RESET); - - /* Write configuration to Register*/ - BL_WR_WORD(CAN_BASE + CAN_FILTER_ACCEPTANCE_0_OFFSET + 4 * reg, value); - - /* Recovery reset mode value */ - CAN_Mode_Set(CAN_MODE_TYPE_RESET, modeReset); -} - -void CAN_Filter_Registers_Set(uint8_t *valueArr) -{ - /* Config filter must be in reset mode */ - CAN_MODE_VALUE_Type modeReset = CAN_Mode_Get(CAN_MODE_TYPE_RESET); - CAN_Mode_Set(CAN_MODE_TYPE_RESET, CAN_MODE_VALUE_RESET); - - /* Write configuration to Registers*/ - BL_WR_REG(CAN_BASE, CAN_FILTER_ACCEPTANCE_0, (uint32_t)valueArr[0]); - BL_WR_REG(CAN_BASE, CAN_FILTER_ACCEPTANCE_1, (uint32_t)valueArr[1]); - BL_WR_REG(CAN_BASE, CAN_FILTER_ACCEPTANCE_2, (uint32_t)valueArr[2]); - BL_WR_REG(CAN_BASE, CAN_FILTER_ACCEPTANCE_3, (uint32_t)valueArr[3]); - BL_WR_REG(CAN_BASE, CAN_FILTER_Mask_0, (uint32_t)valueArr[4]); - BL_WR_REG(CAN_BASE, CAN_FILTER_Mask_1, (uint32_t)valueArr[5]); - BL_WR_REG(CAN_BASE, CAN_FILTER_Mask_2, (uint32_t)valueArr[6]); - BL_WR_REG(CAN_BASE, CAN_FILTER_Mask_3, (uint32_t)valueArr[7]); - - /* Recovery reset mode value */ - CAN_Mode_Set(CAN_MODE_TYPE_RESET, modeReset); -} - -#ifndef BFLB_USE_HAL_DRIVER -BL_Err_Type CAN_Int_Callback_Install(CAN_INT_Type intType,intCallback_Type* cbFun) -{ - /* Check the parameters */ - CHECK_PARAM(IS_CAN_FRAME_FORMAT_TYPE(cbFun)); - CHECK_PARAM(IS_CAN_INT_TYPE(intType)); - - canIntCbfArra[intType] = cbFun; - - return SUCCESS; -} - -static void CAN_IntHandler(void) -{ - uint32_t tmpVal = 0; - uint32_t i = 0; - - tmpVal = BL_RD_REG(CAN_BASE, CAN_INTERRUPT); - - for(i=0; i
© COPYRIGHT(c) 2020 Bouffalo Lab
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_dac.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup DAC - * @{ - */ - -/** @defgroup DAC_Private_Macros - * @{ - */ -#define GPIP_CLK_SET_DUMMY_WAIT \ - { \ - __NOP(); \ - __NOP(); \ - __NOP(); \ - __NOP(); \ - __NOP(); \ - __NOP(); \ - __NOP(); \ - __NOP(); \ - } - -/*@} end of group DAC_Private_Macros */ - -/** @defgroup DAC_Private_Types - * @{ - */ - -/*@} end of group DAC_Private_Types */ - -/** @defgroup DAC_Private_Variables - * @{ - */ - -/*@} end of group DAC_Private_Variables */ - -/** @defgroup DAC_Global_Variables - * @{ - */ - -/*@} end of group DAC_Global_Variables */ - -/** @defgroup DAC_Private_Fun_Declaration - * @{ - */ - -/*@} end of group DAC_Private_Fun_Declaration */ - -/** @defgroup DAC_Private_Functions - * @{ - */ - -/*@} end of group DAC_Private_Functions */ - -/** @defgroup DAC_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief DAC initialization - * - * @param cfg: DAC configuration pointer - * - * @return None - * -*******************************************************************************/ -void GLB_DAC_Init(GLB_DAC_Cfg_Type *cfg) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_GLB_DAC_REF_SEL_TYPE(cfg->refSel)); - - /* Set DAC config */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_DAC_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_REF_SEL, cfg->refSel); - - if (ENABLE == cfg->resetChanA) { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPDACA_RSTN_ANA); - tmpVal = BL_WR_REG(GLB_BASE, GLB_DAC_CFG0, tmpVal); - __NOP(); - __NOP(); - __NOP(); - __NOP(); - } - - if (ENABLE == cfg->resetChanB) { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPDACB_RSTN_ANA); - tmpVal = BL_WR_REG(GLB_BASE, GLB_DAC_CFG0, tmpVal); - __NOP(); - __NOP(); - __NOP(); - __NOP(); - } - - /* Clear reset */ - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDACA_RSTN_ANA); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDACB_RSTN_ANA); - tmpVal = BL_WR_REG(GLB_BASE, GLB_DAC_CFG0, tmpVal); -} - -/****************************************************************************/ /** - * @brief DAC channel A initialization - * - * @param cfg: DAC channel configuration pointer - * - * @return None - * -*******************************************************************************/ -void GLB_DAC_Set_ChanA_Config(GLB_DAC_Chan_Cfg_Type *cfg) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_GLB_DAC_CHAN_TYPE(cfg->outMux)); - - /* Set channel A config */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_DAC_CFG1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_A_OUTMUX, cfg->outMux); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_IOA_EN, cfg->outputEn); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_A_EN, cfg->chanEn); - - tmpVal = BL_WR_REG(GLB_BASE, GLB_DAC_CFG1, tmpVal); -} - -/****************************************************************************/ /** - * @brief DAC channel B initialization - * - * @param cfg: DAC channel configuration pointer - * - * @return None - * -*******************************************************************************/ -void GLB_DAC_Set_ChanB_Config(GLB_DAC_Chan_Cfg_Type *cfg) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_GLB_DAC_CHAN_TYPE(cfg->outMux)); - - /* Set channel A config */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_DAC_CFG2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_B_OUTMUX, cfg->outMux); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_IOB_EN, cfg->outputEn); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_B_EN, cfg->chanEn); - - tmpVal = BL_WR_REG(GLB_BASE, GLB_DAC_CFG2, tmpVal); -} - -/****************************************************************************/ /** - * @brief Select DAC channel B source - * - * @param src: DAC channel B source selection type - * - * @return None - * -*******************************************************************************/ -void GPIP_Set_DAC_ChanB_SRC_SEL(GPIP_DAC_ChanB_SRC_Type src) -{ - uint32_t tmpVal; - - CHECK_PARAM(IS_GPIP_DAC_CHANB_SRC_TYPE(src)); - - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_CH_B_SEL, src); - BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief Select DAC channel A source - * - * @param src: DAC channel A source selection type - * - * @return None - * -*******************************************************************************/ -void GPIP_Set_DAC_ChanA_SRC_SEL(GPIP_DAC_ChanA_SRC_Type src) -{ - uint32_t tmpVal; - - CHECK_PARAM(IS_GPIP_DAC_CHANA_SRC_TYPE(src)); - - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_CH_A_SEL, src); - BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief Enable DAC channel B - * - * @param None - * - * @return None - * -*******************************************************************************/ -void GPIP_DAC_ChanB_Enable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPDAC_EN); - BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief Disable DAC channel B - * - * @param None - * - * @return None - * -*******************************************************************************/ -void GPIP_DAC_ChanB_Disable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPDAC_EN); - BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief Enable DAC channel A - * - * @param None - * - * @return None - * -*******************************************************************************/ -void GPIP_DAC_ChanA_Enable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPDAC_EN); - BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief Disable DAC channel A - * - * @param None - * - * @return None - * -*******************************************************************************/ -void GPIP_DAC_ChanA_Disable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPDAC_EN); - BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief Select DAC DMA TX format - * - * @param fmt: DAC DMA TX format selection type - * - * @return None - * -*******************************************************************************/ -void GPIP_Set_DAC_DMA_TX_FORMAT_SEL(GPIP_DAC_DMA_TX_FORMAT_Type fmt) -{ - uint32_t tmpVal; - - CHECK_PARAM(IS_GPIP_DAC_DMA_TX_FORMAT_TYPE(fmt)); - - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_DMA_FORMAT, fmt); - BL_WR_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief Enable DAC DMA TX - * - * @param None - * - * @return None - * -*******************************************************************************/ -void GPIP_Set_DAC_DMA_TX_Enable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPDAC_DMA_TX_EN); - BL_WR_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief Disable DAC DMA TX - * - * @param None - * - * @return None - * -*******************************************************************************/ -void GPIP_Set_DAC_DMA_TX_Disable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPDAC_DMA_TX_EN); - BL_WR_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief Disable DAC DMA TX - * - * @param data: The data to be send - * - * @return None - * -*******************************************************************************/ -void GPIP_DAC_DMA_WriteData(uint32_t data) -{ - BL_WR_REG(GPIP_BASE, GPIP_GPDAC_DMA_WDATA, data); -} - -/****************************************************************************/ /** - * @brief AON and GPIP DAC config - * - * @param cfg: AON and GPIP DAC configuration - * - * @return config success or not - * -*******************************************************************************/ -BL_Err_Type GLB_GPIP_DAC_Init(GLB_GPIP_DAC_Cfg_Type *cfg) -{ - uint32_t tmpVal; - - CHECK_PARAM(IS_GLB_DAC_REF_SEL_TYPE(cfg->refSel)); - CHECK_PARAM(IS_GPIP_DAC_MOD_TYPE(cfg->div)); - CHECK_PARAM(IS_GPIP_DAC_DMA_TX_FORMAT_TYPE(cfg->dmaFmt)); - - /* AON Set DAC config */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_DAC_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_REF_SEL, cfg->refSel); - - if (ENABLE == cfg->resetChanA) { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPDACA_RSTN_ANA); - tmpVal = BL_WR_REG(GLB_BASE, GLB_DAC_CFG0, tmpVal); - __NOP(); - __NOP(); - __NOP(); - __NOP(); - } - - if (ENABLE == cfg->resetChanB) { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPDACB_RSTN_ANA); - tmpVal = BL_WR_REG(GLB_BASE, GLB_DAC_CFG0, tmpVal); - __NOP(); - __NOP(); - __NOP(); - __NOP(); - } - - /* AON Clear reset */ - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDACA_RSTN_ANA); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDACB_RSTN_ANA); - tmpVal = BL_WR_REG(GLB_BASE, GLB_DAC_CFG0, tmpVal); - - /* GPIP Set DAC config */ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_MODE, cfg->div); - BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); - - /* GPIP Set DMA config */ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_DMA_TX_EN, cfg->dmaEn); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_DMA_FORMAT, cfg->dmaFmt); - BL_WR_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief AON and GPIP DAC channel A config - * - * @param cfg: AON and GPIP DAC channel A configuration - * - * @return None - * -*******************************************************************************/ -void GLB_GPIP_DAC_Set_ChanA_Config(GLB_GPIP_DAC_ChanA_Cfg_Type *cfg) -{ - uint32_t tmpVal; - - CHECK_PARAM(IS_GPIP_DAC_CHANA_SRC_TYPE(cfg->src)); - - /* GPIP select source */ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_CH_A_SEL, cfg->src); - BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); - - /* GPIP enable or disable channel */ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_EN, cfg->chanEn); - BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); - - /* AON enable or disable channel */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_DAC_CFG1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_IOA_EN, cfg->outputEn); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_A_EN, cfg->chanCovtEn); - tmpVal = BL_WR_REG(GLB_BASE, GLB_DAC_CFG1, tmpVal); -} - -/****************************************************************************/ /** - * @brief AON and GPIP DAC channel B config - * - * @param cfg: AON and GPIP DAC channel B configuration - * - * @return None - * -*******************************************************************************/ -void GLB_GPIP_DAC_Set_ChanB_Config(GLB_GPIP_DAC_ChanB_Cfg_Type *cfg) -{ - uint32_t tmpVal; - - CHECK_PARAM(IS_GPIP_DAC_CHANB_SRC_TYPE(cfg->src)); - - /* GPIP select source */ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_CH_B_SEL, cfg->src); - BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); - - /* GPIP enable or disable channel */ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_EN, cfg->chanEn); - BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); - - /* AON enable or disable channel */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_DAC_CFG2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_IOB_EN, cfg->outputEn); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_B_EN, cfg->chanCovtEn); - tmpVal = BL_WR_REG(GLB_BASE, GLB_DAC_CFG2, tmpVal); -} - -/****************************************************************************/ /** - * @brief DAC channel A set value - * - * @param val: DAC value - * - * @return None - * -*******************************************************************************/ -void GLB_DAC_Set_ChanA_Value(uint16_t val) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DAC_CFG3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_A_DATA, val); - tmpVal = BL_WR_REG(GLB_BASE, GLB_DAC_CFG3, tmpVal); -} - -/****************************************************************************/ /** - * @brief DAC channel B set value - * - * @param val: DAC value - * - * @return None - * -*******************************************************************************/ -void GLB_DAC_Set_ChanB_Value(uint16_t val) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DAC_CFG3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_B_DATA, val); - tmpVal = BL_WR_REG(GLB_BASE, GLB_DAC_CFG3, tmpVal); -} - -/*@} end of group DAC_Public_Functions */ - -/*@} end of group DAC */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dbi.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dbi.c deleted file mode 100644 index bde60e85a7..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dbi.c +++ /dev/null @@ -1,802 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_dbi.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_dbi.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup DBI - * @{ - */ - -/** @defgroup DBI_Private_Macros - * @{ - */ - -/*@} end of group DBI_Private_Macros */ - -/** @defgroup DBI_Private_Types - * @{ - */ - -/*@} end of group DBI_Private_Types */ - -/** @defgroup DBI_Private_Variables - * @{ - */ - -/** - * @brief DBI interrupt callback function address array - */ -#ifndef BFLB_USE_HAL_DRIVER -static intCallback_Type *DBIIntCbfArra[DBI_INT_ALL] = { - NULL -}; -#endif - -/*@} end of group DBI_Private_Variables */ - -/** @defgroup DBI_Global_Variables - * @{ - */ - -/*@} end of group DBI_Global_Variables */ - -/** @defgroup DBI_Private_Fun_Declaration - * @{ - */ - -/*@} end of group DBI_Private_Fun_Declaration */ - -/** @defgroup DBI_Private_Functions - * @{ - */ - -/*@} end of group DBI_Private_Functions */ - -/** @defgroup DBI_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief DBI interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void DBI_IRQHandler(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DBI_BASE, DBI_INT_STS); - - /* DBI transfer end interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, DBI_END_INT) && !BL_IS_REG_BIT_SET(tmpVal, DBI_CR_DBI_END_MASK)) { - BL_WR_REG(DBI_BASE, DBI_INT_STS, BL_SET_REG_BIT(tmpVal, DBI_CR_DBI_END_CLR)); - - if (DBIIntCbfArra[DBI_INT_END] != NULL) { - DBIIntCbfArra[DBI_INT_END](); - } - } - - /* DBI tx fifo ready interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, DBI_TXF_INT) && !BL_IS_REG_BIT_SET(tmpVal, DBI_CR_DBI_TXF_MASK)) { - if (DBIIntCbfArra[DBI_INT_TX_FIFO_REQ] != NULL) { - DBIIntCbfArra[DBI_INT_TX_FIFO_REQ](); - } - } - - /* DBI tx fifo ready interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, DBI_FER_INT) && !BL_IS_REG_BIT_SET(tmpVal, DBI_CR_DBI_FER_MASK)) { - if (DBIIntCbfArra[DBI_INT_FIFO_ERR] != NULL) { - DBIIntCbfArra[DBI_INT_FIFO_ERR](); - } - } -} -#endif - -/****************************************************************************/ /** - * @brief DBI init - * - * @param dbiCfg: DBI configuration - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type DBI_Init(DBI_CFG_Type *dbiCfg) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_DBI_MODE_TYPE(dbiCfg->mode)); - CHECK_PARAM(IS_DBI_PIXEL_FORMAT_TYPE(dbiCfg->pixelFormat)); - CHECK_PARAM(IS_DBI_FIFO_FORMAT_TYPE(dbiCfg->fifoFormat)); - CHECK_PARAM(IS_DBI_SCL_CLK_PHASE_TYPE(dbiCfg->clkPhase)); - CHECK_PARAM(IS_DBI_SCL_CLK_POLARITY_TYPE(dbiCfg->clkPolarity)); - - tmpVal = BL_RD_REG(DBI_BASE, DBI_CONFIG); - - /* Select DBI type B or C */ - if (dbiCfg->mode == DBI_TYPE_B) { - tmpVal = BL_CLR_REG_BIT(tmpVal, DBI_CR_DBI_SEL); - } else if (dbiCfg->mode == DBI_TYPE_C_3_WIRE) { - tmpVal = BL_SET_REG_BIT(tmpVal, DBI_CR_DBI_SEL); - tmpVal = BL_SET_REG_BIT(tmpVal, DBI_CR_DBI_TC_3W_MODE); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, DBI_CR_DBI_SEL); - tmpVal = BL_CLR_REG_BIT(tmpVal, DBI_CR_DBI_TC_3W_MODE); - } - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_CONT_EN, dbiCfg->continueEn); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_DMY_EN, dbiCfg->dummyEn); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_DMY_CNT, dbiCfg->dummyCnt); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_SCL_PH, dbiCfg->clkPhase); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_SCL_POL, dbiCfg->clkPolarity); - - BL_WR_REG(DBI_BASE, DBI_CONFIG, tmpVal); - - /* Set data period */ - DBI_SetPeriod(&(dbiCfg->period)); - - /* Set pixel format */ - tmpVal = BL_RD_REG(DBI_BASE, DBI_PIX_CNT); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_PIX_FORMAT, dbiCfg->pixelFormat); - BL_WR_REG(DBI_BASE, DBI_PIX_CNT, tmpVal); - - /* Set fifo format */ - tmpVal = BL_RD_REG(DBI_BASE, DBI_FIFO_CONFIG_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_FIFO_FORMAT, dbiCfg->fifoFormat); - BL_WR_REG(DBI_BASE, DBI_FIFO_CONFIG_0, tmpVal); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(DBI_IRQn, DBI_IRQHandler); -#endif - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief DBI command and data configuration - * - * @param cdCfg: Pointer of DBI CD configure type - * - * @return None - * -*******************************************************************************/ -void DBI_CDConfig(DBI_CD_CFG_Type *cdCfg) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_DBI_DATA_TYPE(cdCfg->dataType)); - CHECK_PARAM(IS_DBI_DATA_DIRECTION_TYPE(cdCfg->dataDir)); - - /* Set command and data comfiguration */ - tmpVal = BL_RD_REG(DBI_BASE, DBI_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_CMD_EN, cdCfg->commandEn); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_CMD, cdCfg->command); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_DAT_EN, cdCfg->dataEn); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_DAT_TP, cdCfg->dataType); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_DAT_WR, cdCfg->dataDir); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_DAT_BC, cdCfg->dataCnt); - BL_WR_REG(DBI_BASE, DBI_CONFIG, tmpVal); - BL_WR_REG(DBI_BASE, DBI_WDATA, cdCfg->data); -} - -/****************************************************************************/ /** - * @brief DBI enable - * - * @param None - * - * @return None - * -*******************************************************************************/ -void DBI_Enable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DBI_BASE, DBI_CONFIG); - BL_WR_REG(DBI_BASE, DBI_CONFIG, BL_SET_REG_BIT(tmpVal, DBI_CR_DBI_EN)); -} - -/****************************************************************************/ /** - * @brief DBI disable - * - * @param None - * - * @return None - * -*******************************************************************************/ -void DBI_Disable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DBI_BASE, DBI_CONFIG); - BL_WR_REG(DBI_BASE, DBI_CONFIG, BL_CLR_REG_BIT(tmpVal, DBI_CR_DBI_EN)); -} - -/****************************************************************************/ /** - * @brief DBI enable - * - * @param period: DBI period configuration - * - * @return None - * -*******************************************************************************/ -void DBI_SetPeriod(DBI_Period_CFG_Type *period) -{ - uint32_t tmpVal; - - /* Set data period */ - tmpVal = BL_RD_REG(DBI_BASE, DBI_PRD); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_PRD_S, period->startLen); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_PRD_D_PH_0, period->dataPhase0Len); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_PRD_D_PH_1, period->dataPhase1Len); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_PRD_I, period->intervalLen); - - BL_WR_REG(DBI_BASE, DBI_PRD, tmpVal); -} - -/****************************************************************************/ /** - * @brief DBI set Command - * - * @param Command: start Command (frist byte) - * @return None - * -*******************************************************************************/ -void DBI_SetCommand(uint8_t Command ) -{ - uint32_t tmpVal; - - /* Set command */ - tmpVal = BL_RD_REG(DBI_BASE, DBI_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_CMD, Command); - BL_WR_REG(DBI_BASE, DBI_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief DBI set Command and Data enable signal - * - * @param CommandEn: DISABLE:No command phase, ENABLE:Command will be sent - * @param dataEn: DISABLE:No data phase, ENABLE:data will be sent - * @return None - * -*******************************************************************************/ -void DBI_SetPhaseState(BL_Fun_Type commandEn, BL_Fun_Type dataEn) -{ - uint32_t tmpVal; - - /* Set command */ - tmpVal = BL_RD_REG(DBI_BASE, DBI_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_CMD_EN, commandEn); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_DAT_EN, dataEn); - BL_WR_REG(DBI_BASE, DBI_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief DBI set Data type and count, Automatically change data phase settings - * - * @param datatype: Data type select - * @param dataCount: count of data (Not the size of the data) - * normal data: max 4 - * @return None - * -*******************************************************************************/ -void DBI_SetDataTypeAndCount(DBI_Data_Type dataType, uint32_t dataCount) -{ - uint32_t tmpVal, tmpVal2; - - /* Set dbi config */ - tmpVal = BL_RD_REG(DBI_BASE, DBI_CONFIG); - /* Set data type */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_DAT_TP, dataType); - - if(!dataCount){ - /* No data phase */ - tmpVal = BL_CLR_REG_BIT(tmpVal, DBI_CR_DBI_DAT_EN); - }else{ - /* data will be sent */ - tmpVal = BL_SET_REG_BIT(tmpVal, DBI_CR_DBI_DAT_EN); - - if(dataType == DBI_DATA_NORMAL){ - if(dataCount > 4){ - dataCount = 4; - } - /* data byte count of normal-data */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_DAT_BC, dataCount-1); - }else{ - /* pixel count of pixel-data */ - tmpVal2 = BL_RD_REG(DBI_BASE, DBI_PIX_CNT); - tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, DBI_CR_DBI_PIX_CNT, dataCount-1); - BL_WR_REG(DBI_BASE, DBI_PIX_CNT, tmpVal2); - } - } - BL_WR_REG(DBI_BASE, DBI_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief DBI set normal data direction (It only works in normal data) - * - * @param dataDir: write or read - * @return None - * -*******************************************************************************/ -void DBI_SetNormalDataDir(DBI_Data_Direction_Type dataDir) -{ - uint32_t tmpVal; - /* Set dbi config */ - tmpVal = BL_RD_REG(DBI_BASE, DBI_CONFIG); - /* set normal data direction */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_DAT_WR, dataDir); - BL_WR_REG(DBI_BASE, DBI_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief DBI Read Norml-Data from rdata-register - * - * @param dataSize: size of data (max 4-byte) - * @param dataBuff: buff of data - * @return None - * -*******************************************************************************/ -void DBI_ReadNormlData(uint8_t dataSize, uint8_t *dataBuff) -{ - if(dataSize > 4){ - dataSize = 4; - } - - /* get receive data from registers*/ - uint32_t para_data = 0; - para_data = BL_RD_REG(DBI_BASE, DBI_RDATA); - - /* copy to buff */ - memcpy(dataBuff, ¶_data, dataSize); -} - -/****************************************************************************/ /** - * @brief DBI Write Norml-Data to rdata-register - * - * @param dataSize: size of data (max 4-byte) - * @param dataBuff: buff of data - * @return None - * -*******************************************************************************/ -void DBI_WriteNormlData(uint8_t dataSize, uint8_t *dataBuff) -{ - uint32_t para_data = 0; - - if(dataSize > 4){ - dataSize = 4; - } - - for(uint8_t i=0; i 0) { - BL_WR_REG(DBI_BASE, DBI_FIFO_WDATA, dataBuff[i++]); - } - } -} - -/****************************************************************************/ /** - * @brief DBI Calculate the WordCount of data in different pixel formats - * You should have configured the FIFO-format before - * @param PixelCount: pixel count - * @return Words Count - * -*******************************************************************************/ -uint32_t DBI_GetWordCountOfPixelData(int32_t PixelCount) -{ - uint32_t wordCount; - /* get pixel-formats of fifo*/ - DBI_FIFO_Format_Type fifoFormat = BL_GET_REG_BITS_VAL(BL_RD_REG(DBI_BASE, DBI_FIFO_CONFIG_0), DBI_FIFO_FORMAT); - - if(fifoFormat == DBI_FIFO_888_NBGR || fifoFormat == DBI_FIFO_888_NRGB){ - wordCount = PixelCount; - }else if(fifoFormat == DBI_FIFO_565_BGRBGR || fifoFormat == DBI_FIFO_565_RGBRGB){ - wordCount = (PixelCount + 1) >> 1; - }else{ - wordCount = (PixelCount * 3 + 3) >> 2; - } - return wordCount; -} - -/****************************************************************************/ /** - * @brief DBI send Command and write normal-data function - * - * @param command: Command to send (if command phase enable) - * @param dataSize: write size of NormalData (write max 4) - * @param dataBuff: buff of NormalData - * @return None - * -*******************************************************************************/ -void DBI_SendCmdWithNormalData(uint8_t command, uint8_t dataSize, uint8_t *dataBuff) -{ - /* disable transfer */ - DBI_Disable(); - - /* clear fifo and interrupt */ - DBI_IntClear(); - - /* set command */ - DBI_SetCommand(command); - - /* set data direction */ - DBI_SetNormalDataDir(DBI_DATA_WRITE); - - /* Data type select, and set data count */ - DBI_SetDataTypeAndCount(DBI_DATA_NORMAL, dataSize); - - /* Fill the data into the register */ - DBI_WriteNormlData(dataSize, dataBuff); - - /* enable transfer */ - DBI_Enable(); - - /* Wait transfer end */ - while (DBI_GetIntStatus(DBI_INT_END) != SET) { - } - - /* clear interrupt */ - DBI_IntClear(); -} - -/****************************************************************************/ /** - * @brief DBI send Command and read normal-data function - * - * @param command: Command to send (if command phase enable) - * @param dataSize: read size of NormalData (read max 4 ) - * @param dataBuff: buff of NormalData - * @return None - * -*******************************************************************************/ -void DBI_SendCmdAndReadNormalData(uint8_t command, uint8_t dataSize, uint8_t *dataBuff) -{ - /* disable transfer */ - DBI_Disable(); - - /* clear interrupt */ - DBI_IntClear(); - - /* set command */ - DBI_SetCommand(command); - - /* set data direction */ - DBI_SetNormalDataDir(DBI_DATA_READ); - - /* Data type select, and set data count */ - DBI_SetDataTypeAndCount(DBI_DATA_NORMAL, dataSize); - - /* enable transfer */ - DBI_Enable(); - - /* Wait transfer end */ - while (DBI_GetIntStatus(DBI_INT_END) != SET) { - } - - /* get data */ - DBI_ReadNormlData(dataSize, dataBuff); - - /* clear interrupt */ - DBI_IntClear(); -} - -/****************************************************************************/ /** - * @brief DBI send Command and write pixel-data function - * - * @param command: Command to send (if command phase enable) - * @param dataSize: write size of Pixel-Data - * @param dataBuff: buff of Pixel-Data - * @return None - * -*******************************************************************************/ -void DBI_SendCmdWithPixelData(uint8_t command, int32_t PixelCount, uint32_t *pixelBuff) -{ - /* disable transfer */ - DBI_Disable(); - - /* clear fifo and interrupt */ - DBI_TxFifoClear(); - DBI_IntClear(); - - /* set command */ - DBI_SetCommand(command); - - /* set data direction */ - DBI_SetNormalDataDir(DBI_DATA_WRITE); - - /* Data type select, and set data count */ - DBI_SetDataTypeAndCount(DBI_DATA_PIXEL, PixelCount); - - /* enable transfer */ - DBI_Enable(); - - /* get words count */ - uint32_t wordsCount = DBI_GetWordCountOfPixelData(PixelCount); - /* send data */ - DBI_WirteData2FIFO(wordsCount, pixelBuff); - - /* Wait transfer end */ - while (DBI_GetIntStatus(DBI_INT_END) != SET) { - } - - /* clear interrupt */ - DBI_IntClear(); -} - -/****************************************************************************/ /** - * @brief Clear tx fifo,overflow/underflow flag and fifo error interrupt will be cleared - * - * @param None - * - * @return None - * -*******************************************************************************/ -void DBI_TxFifoClear(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DBI_BASE, DBI_FIFO_CONFIG_0); - tmpVal = BL_SET_REG_BIT(tmpVal, DBI_TX_FIFO_CLR); - BL_WR_REG(DBI_BASE, DBI_FIFO_CONFIG_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief Enable or disable signal of dma interface - * - * @param dmaEn: Enable or disable - * - * @return None - * -*******************************************************************************/ -void DBI_SetDMA(BL_Fun_Type dmaEn) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DBI_BASE, DBI_FIFO_CONFIG_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_DMA_TX_EN, dmaEn); - BL_WR_REG(DBI_BASE, DBI_FIFO_CONFIG_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief Set tx fifo threshold - * - * @param threshold: Threshold value - * - * @return None - * -*******************************************************************************/ -void DBI_SetTxFifoThreshold(uint8_t threshold) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DBI_BASE, DBI_FIFO_CONFIG_1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_TX_FIFO_TH, threshold); - BL_WR_REG(DBI_BASE, DBI_FIFO_CONFIG_1, tmpVal); -} - -/****************************************************************************/ /** - * @brief Get tx fifo count value - * - * @param None - * - * @return Count value - * -*******************************************************************************/ -uint8_t DBI_GetTxFifoCount(void) -{ - return BL_GET_REG_BITS_VAL(BL_RD_REG(DBI_BASE, DBI_FIFO_CONFIG_1), DBI_TX_FIFO_CNT); -} - -/****************************************************************************/ /** - * @brief Get interrupt status - * - * @param intType: DBI interrupt type - * - * @return Status of interrupt - * -*******************************************************************************/ -BL_Sts_Type DBI_GetIntStatus(DBI_INT_Type intType) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DBI_BASE, DBI_INT_STS); - - if ((tmpVal >> intType & 1) == 1) { - return SET; - } else { - return RESET; - } -} - -/****************************************************************************/ /** - * @brief Get tx fifo overflow/underflow status - * - * @param overflow: Select overflow or underflow - * - * @return Status of tx fifo - * -*******************************************************************************/ -BL_Sts_Type DBI_GetOverflowStatus(DBI_Overflow_Type overflow) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_DBI_OVERFLOW_TYPE(overflow)); - - tmpVal = BL_RD_REG(DBI_BASE, DBI_FIFO_CONFIG_0); - - if (overflow == DBI_TX_OVERFLOW) { - if (BL_IS_REG_BIT_SET(tmpVal, DBI_TX_FIFO_OVERFLOW)) { - return SET; - } else { - return RESET; - } - } else { - if (BL_IS_REG_BIT_SET(tmpVal, DBI_TX_FIFO_UNDERFLOW)) { - return SET; - } else { - return RESET; - } - } -} - -/****************************************************************************/ /** - * @brief Get DBI bus busy status - * - * @param None - * - * @return Status of DBI bus - * -*******************************************************************************/ -BL_Sts_Type DBI_GetBusBusyStatus(void) -{ - if (BL_IS_REG_BIT_SET(BL_RD_REG(DBI_BASE, DBI_BUS_BUSY), DBI_STS_DBI_BUS_BUSY)) { - return SET; - } else { - return RESET; - } -} - -/****************************************************************************/ /** - * @brief Mask/Unmask the DBI interrupt - * - * @param intType: DBI interrupt type - * @param intMask: Mask/Unmask - * - * @return None - * -*******************************************************************************/ -void DBI_IntMask(DBI_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_DBI_INT_TYPE(intType)); - - tmpVal = BL_RD_REG(DBI_BASE, DBI_INT_STS); - - switch (intType) { - case DBI_INT_END: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_END_MASK, intMask); - break; - - case DBI_INT_TX_FIFO_REQ: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_TXF_MASK, intMask); - break; - - case DBI_INT_FIFO_ERR: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_FER_MASK, intMask); - break; - - case DBI_INT_ALL: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_END_MASK, intMask); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_TXF_MASK, intMask); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_FER_MASK, intMask); - break; - - default: - break; - } - - BL_WR_REG(DBI_BASE, DBI_INT_STS, tmpVal); -} - -/****************************************************************************/ /** - * @brief Clear DBI interrupt - * - * @param None - * - * @return None - * -*******************************************************************************/ -void DBI_IntClear(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DBI_BASE, DBI_INT_STS); - BL_WR_REG(DBI_BASE, DBI_INT_STS, BL_SET_REG_BIT(tmpVal, DBI_CR_DBI_END_CLR)); -} - -/****************************************************************************/ /** - * @brief Install DBI interrupt callback function - * - * @param intType: DBI interrupt type - * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void DBI_Int_Callback_Install(DBI_INT_Type intType, intCallback_Type *cbFun) -{ - /* Check the parameters */ - CHECK_PARAM(IS_DBI_INT_TYPE(intType)); - - DBIIntCbfArra[intType] = cbFun; -} -#endif - -/*@} end of group DBI_Public_Functions */ - -/*@} end of group DBI */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dma.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dma.c deleted file mode 100644 index aae3f9ae22..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dma.c +++ /dev/null @@ -1,1060 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_dma.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808.h" -#include "bl808_dma.h" -#include "bl808_glb.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup DMA - * @{ - */ - -/** @defgroup DMA_Private_Macros - * @{ - */ -#define DMA_CHANNEL_OFFSET 0x100 -#define DMA_Get_Channel(id_base, ch) ((id_base) + DMA_CHANNEL_OFFSET + (ch)*0x100) - -/*@} end of group DMA_Private_Macros */ - -/** @defgroup DMA_Private_Types - * @{ - */ - -/*@} end of group DMA_Private_Types */ - -/** @defgroup DMA_Private_Variables - * @{ - */ -static const uint32_t dmaAddr[DMA_ID_MAX] = { DMA0_BASE, DMA1_BASE, DMA2_BASE }; -#ifndef BFLB_USE_HAL_DRIVER -static intCallback_Type *dmaIntCbfArra[DMA_ID_MAX][DMA_CH_MAX][DMA_INT_ALL] = { - { { NULL } } -}; -#endif -static DMA_LLI_Ctrl_Type PingPongListArra[DMA_ID_MAX][DMA_CH_MAX][2]; - -/*@} end of group DMA_Private_Variables */ - -/** @defgroup DMA_Global_Variables - * @{ - */ - -/*@} end of group DMA_Global_Variables */ - -/** @defgroup DMA_Private_Fun_Declaration - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -static void DMA_IntHandler(DMA_ID_Type dmaId); -#endif -static void CPU_Interrupt_Enable_DMA(DMA_ID_Type dmaId); -static void CPU_Interrupt_Disable_DMA(DMA_ID_Type dmaId); - -/*@} end of group DMA_Private_Fun_Declaration */ - -/** @defgroup DMA_Private_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief DMA interrupt handler - * - * @param dmaId: DMA ID type - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -static void DMA_IntHandler(DMA_ID_Type dmaId) -{ - uint32_t tmpVal; - uint32_t intClr; - uint8_t ch; - /* Get DMA register */ - uint32_t DMAChs = dmaAddr[dmaId]; - - for (ch = 0; ch < DMA_CH_MAX; ch++) { - tmpVal = BL_RD_REG(DMAChs, DMA_INTTCSTATUS); - - if ((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCSTATUS) & (1 << ch)) != 0) { - /* Clear interrupt */ - tmpVal = BL_RD_REG(DMAChs, DMA_INTTCCLEAR); - intClr = BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCCLEAR); - intClr |= (1 << ch); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_INTTCCLEAR, intClr); - BL_WR_REG(DMAChs, DMA_INTTCCLEAR, tmpVal); - - if (dmaIntCbfArra[dmaId][ch][DMA_INT_TCOMPLETED] != NULL) { - /* Call the callback function */ - dmaIntCbfArra[dmaId][ch][DMA_INT_TCOMPLETED](); - } - } - } - - for (ch = 0; ch < DMA_CH_MAX; ch++) { - tmpVal = BL_RD_REG(DMAChs, DMA_INTERRORSTATUS); - - if ((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRORSTATUS) & (1 << ch)) != 0) { - /*Clear interrupt */ - tmpVal = BL_RD_REG(DMAChs, DMA_INTERRCLR); - intClr = BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRCLR); - intClr |= (1 << ch); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_INTERRCLR, intClr); - BL_WR_REG(DMAChs, DMA_INTERRCLR, tmpVal); - - if (dmaIntCbfArra[dmaId][ch][DMA_INT_ERR] != NULL) { - /* Call the callback function */ - dmaIntCbfArra[dmaId][ch][DMA_INT_ERR](); - } - } - } -} -#endif - -/****************************************************************************/ /** - * @brief CPU enable DMA interrupt - * - * @param dmaId: DMA ID type - * - * @return None - * -*******************************************************************************/ -static void CPU_Interrupt_Enable_DMA(DMA_ID_Type dmaId) -{ - /* Check the parameters */ - CHECK_PARAM(IS_DMA_ID_TYPE(dmaId)); - - if (DMA0_ID == dmaId) { - CPU_Interrupt_Enable(DMA0_ALL_IRQn); - } else if (DMA1_ID == dmaId) { - CPU_Interrupt_Enable(DMA1_ALL_IRQn); - } else { - CPU_Interrupt_Enable(DMA2_INT0_IRQn); - CPU_Interrupt_Enable(DMA2_INT1_IRQn); - CPU_Interrupt_Enable(DMA2_INT2_IRQn); - CPU_Interrupt_Enable(DMA2_INT3_IRQn); - CPU_Interrupt_Enable(DMA2_INT4_IRQn); - CPU_Interrupt_Enable(DMA2_INT5_IRQn); - CPU_Interrupt_Enable(DMA2_INT6_IRQn); - CPU_Interrupt_Enable(DMA2_INT7_IRQn); - } -} - -/****************************************************************************/ /** - * @brief CPU disable DMA interrupt - * - * @param dmaId: DMA ID type - * - * @return None - * -*******************************************************************************/ -static void CPU_Interrupt_Disable_DMA(DMA_ID_Type dmaId) -{ - /* Check the parameters */ - CHECK_PARAM(IS_DMA_ID_TYPE(dmaId)); - - if (DMA0_ID == dmaId) { - CPU_Interrupt_Disable(DMA0_ALL_IRQn); - } else if (DMA1_ID == dmaId) { - CPU_Interrupt_Disable(DMA1_ALL_IRQn); - } else { - CPU_Interrupt_Disable(DMA2_INT0_IRQn); - CPU_Interrupt_Disable(DMA2_INT1_IRQn); - CPU_Interrupt_Disable(DMA2_INT2_IRQn); - CPU_Interrupt_Disable(DMA2_INT3_IRQn); - CPU_Interrupt_Disable(DMA2_INT4_IRQn); - CPU_Interrupt_Disable(DMA2_INT5_IRQn); - CPU_Interrupt_Disable(DMA2_INT6_IRQn); - CPU_Interrupt_Disable(DMA2_INT7_IRQn); - } -} - -/*@} end of group DMA_Private_Functions */ - -/** @defgroup DMA_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief DMA enable - * - * @param dmaId: DMA ID type - * - * @return None - * -*******************************************************************************/ -void DMA_Enable(DMA_ID_Type dmaId) -{ - uint32_t tmpVal; - /* Get DMA register */ - uint32_t DMAChs = dmaAddr[dmaId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DMA_ID_TYPE(dmaId)); - - tmpVal = BL_RD_REG(DMAChs, DMA_TOP_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, DMA_E); - BL_WR_REG(DMAChs, DMA_TOP_CONFIG, tmpVal); -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(DMA0_ALL_IRQn, DMA0_ALL_IRQHandler); - Interrupt_Handler_Register(DMA1_ALL_IRQn, DMA1_ALL_IRQHandler); - Interrupt_Handler_Register(DMA2_INT0_IRQn, DMA2_INT0_IRQHandler); - Interrupt_Handler_Register(DMA2_INT1_IRQn, DMA2_INT1_IRQHandler); - Interrupt_Handler_Register(DMA2_INT2_IRQn, DMA2_INT2_IRQHandler); - Interrupt_Handler_Register(DMA2_INT3_IRQn, DMA2_INT3_IRQHandler); - Interrupt_Handler_Register(DMA2_INT4_IRQn, DMA2_INT4_IRQHandler); - Interrupt_Handler_Register(DMA2_INT5_IRQn, DMA2_INT5_IRQHandler); - Interrupt_Handler_Register(DMA2_INT6_IRQn, DMA2_INT6_IRQHandler); - Interrupt_Handler_Register(DMA2_INT7_IRQn, DMA2_INT7_IRQHandler); -#endif -} - -/****************************************************************************/ /** - * @brief DMA disable - * - * @param dmaId: DMA ID type - * - * @return None - * -*******************************************************************************/ -void DMA_Disable(DMA_ID_Type dmaId) -{ - uint32_t tmpVal; - /* Get DMA register */ - uint32_t DMAChs = dmaAddr[dmaId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DMA_ID_TYPE(dmaId)); - - tmpVal = BL_RD_REG(DMAChs, DMA_TOP_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_E); - BL_WR_REG(DMAChs, DMA_TOP_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief DMA channel init - * - * @param dmaId: DMA ID type - * @param chCfg: DMA configuration - * - * @return None - * -*******************************************************************************/ -void DMA_Channel_Init(DMA_ID_Type dmaId, DMA_Channel_Cfg_Type *chCfg) -{ - uint32_t tmpVal; - /* Get channel register */ - uint32_t DMAChs = DMA_Get_Channel(dmaAddr[dmaId], chCfg->ch); - - /* Check the parameters */ - CHECK_PARAM(IS_DMA_ID_TYPE(dmaId)); - CHECK_PARAM(IS_DMA_CHAN_TYPE(chCfg->ch)); - CHECK_PARAM(IS_DMA_TRANS_WIDTH_TYPE(chCfg->srcTransfWidth)); - CHECK_PARAM(IS_DMA_TRANS_WIDTH_TYPE(chCfg->dstTransfWidth)); - CHECK_PARAM(IS_DMA_BURST_SIZE_TYPE(chCfg->srcBurstSize)); - CHECK_PARAM(IS_DMA_BURST_SIZE_TYPE(chCfg->dstBurstSize)); - CHECK_PARAM(IS_DMA_TRANS_DIR_TYPE(chCfg->dir)); - CHECK_PARAM(IS_DMA_PERIPH_REQ_TYPE(chCfg->dstPeriph)); - CHECK_PARAM(IS_DMA_PERIPH_REQ_TYPE(chCfg->srcPeriph)); - - /* Disable clock gate when use DMA0 */ - if (DMA0_ID == dmaId) { - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_DMA_0); - } else if (DMA1_ID == dmaId) { - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_DMA_1); - } else if (DMA2_ID == dmaId) { - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_DMA_2); - } - - /* Config channel config */ - BL_WR_REG(DMAChs, DMA_SRCADDR, chCfg->srcDmaAddr); - BL_WR_REG(DMAChs, DMA_DSTADDR, chCfg->destDmaAddr); - - tmpVal = BL_RD_REG(DMAChs, DMA_CONTROL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_TRANSFERSIZE, chCfg->transfLength); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SWIDTH, chCfg->srcTransfWidth); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DWIDTH, chCfg->dstTransfWidth); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SBSIZE, chCfg->srcBurstSize); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DBSIZE, chCfg->dstBurstSize); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DST_ADD_MODE, chCfg->dstAddMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DST_MIN_MODE, chCfg->dstMinMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_FIX_CNT, chCfg->fixCnt); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SI, chCfg->srcAddrInc); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DI, chCfg->destAddrInc); - BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal); - - tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_FLOWCNTRL, chCfg->dir); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DSTPERIPHERAL, chCfg->dstPeriph); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SRCPERIPHERAL, chCfg->srcPeriph); - BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief DMA set default value of all registers function - * - * @param dmaId: DMA ID type - * - * @return SUCCESS - * -*******************************************************************************/ -void DMA_DeInit(DMA_ID_Type dmaId) -{ - switch (dmaId) { - case DMA0_ID: - GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_DMA); - break; - - case DMA1_ID: - GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_DMA2); - break; - - case DMA2_ID: - GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_DMA); - break; - - default: - break; - } -} - -/****************************************************************************/ /** - * @brief DMA channel update source memory address and len - * - * @param dmaId: DMA ID type - * @param ch: DMA channel - * @param memAddr: source memoty address - * @param len: source memory data length - * - * @return None - * -*******************************************************************************/ -void DMA_Channel_Update_SrcMemcfg(DMA_ID_Type dmaId, uint8_t ch, uint32_t memAddr, uint32_t len) -{ - uint32_t tmpVal; - /* Get channel register */ - uint32_t DMAChs = DMA_Get_Channel(dmaAddr[dmaId], ch); - - /* Check the parameters */ - CHECK_PARAM(IS_DMA_ID_TYPE(dmaId)); - CHECK_PARAM(IS_DMA_CHAN_TYPE(ch)); - - /* config channel config*/ - BL_WR_REG(DMAChs, DMA_SRCADDR, memAddr); - tmpVal = BL_RD_REG(DMAChs, DMA_CONTROL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_TRANSFERSIZE, len); - BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal); -} - -/****************************************************************************/ /** - * @brief DMA channel update destination memory address and len - * - * @param dmaId: DMA ID type - * @param ch: DMA channel - * @param memAddr: destination memoty address - * @param len: destination memory data length - * - * @return None - * -*******************************************************************************/ -void DMA_Channel_Update_DstMemcfg(DMA_ID_Type dmaId, uint8_t ch, uint32_t memAddr, uint32_t len) -{ - uint32_t tmpVal; - /* Get channel register */ - uint32_t DMAChs = DMA_Get_Channel(dmaAddr[dmaId], ch); - - /* Check the parameters */ - CHECK_PARAM(IS_DMA_ID_TYPE(dmaId)); - CHECK_PARAM(IS_DMA_CHAN_TYPE(ch)); - - /* config channel config*/ - BL_WR_REG(DMAChs, DMA_DSTADDR, memAddr); - tmpVal = BL_RD_REG(DMAChs, DMA_CONTROL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_TRANSFERSIZE, len); - BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal); -} - -/****************************************************************************/ /** - * @brief Get DMA channel tranfersize - * - * @param dmaId: DMA ID type - * @param ch: DMA channel - * - * @return tranfersize size - * -*******************************************************************************/ -uint32_t DMA_Channel_TranferSize(DMA_ID_Type dmaId, uint8_t ch) -{ - /* Get channel register */ - uint32_t DMAChs = DMA_Get_Channel(dmaAddr[dmaId], ch); - - /* Check the parameters */ - CHECK_PARAM(IS_DMA_ID_TYPE(dmaId)); - CHECK_PARAM(IS_DMA_CHAN_TYPE(ch)); - - return BL_GET_REG_BITS_VAL(BL_RD_REG(DMAChs, DMA_CONTROL), DMA_TRANSFERSIZE); -} - -/****************************************************************************/ /** - * @brief Get DMA channel busy status - * - * @param dmaId: DMA ID type - * @param ch: DMA channel - * - * @return SET or RESET - * -*******************************************************************************/ -BL_Sts_Type DMA_Channel_Is_Busy(DMA_ID_Type dmaId, uint8_t ch) -{ - /* Get channel register */ - uint32_t DMAChs = DMA_Get_Channel(dmaAddr[dmaId], ch); - - /* Check the parameters */ - CHECK_PARAM(IS_DMA_ID_TYPE(dmaId)); - CHECK_PARAM(IS_DMA_CHAN_TYPE(ch)); - - return BL_IS_REG_BIT_SET(BL_RD_REG(DMAChs, DMA_CONFIG), DMA_E) == 1 ? SET : RESET; -} - -/****************************************************************************/ /** - * @brief DMA enable - * - * @param dmaId: DMA ID type - * @param ch: DMA channel number - * - * @return None - * -*******************************************************************************/ -void DMA_Channel_Enable(DMA_ID_Type dmaId, uint8_t ch) -{ - uint32_t tmpVal; - /* Get channel register */ - uint32_t DMAChs = DMA_Get_Channel(dmaAddr[dmaId], ch); - - /* Check the parameters */ - CHECK_PARAM(IS_DMA_ID_TYPE(dmaId)); - CHECK_PARAM(IS_DMA_CHAN_TYPE(ch)); - - tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, DMA_E); - BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief DMA disable - * - * @param dmaId: DMA ID type - * @param ch: DMA channel number - * - * @return None - * -*******************************************************************************/ -void DMA_Channel_Disable(DMA_ID_Type dmaId, uint8_t ch) -{ - uint32_t tmpVal; - /* Get channel register */ - uint32_t DMAChs = DMA_Get_Channel(dmaAddr[dmaId], ch); - - /* Check the parameters */ - CHECK_PARAM(IS_DMA_ID_TYPE(dmaId)); - CHECK_PARAM(IS_DMA_CHAN_TYPE(ch)); - - tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_E); - BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief DMA init LLI transfer - * - * @param dmaId: DMA ID type - * @param ch: DMA channel number - * @param lliCfg: LLI configuration - * - * @return None - * -*******************************************************************************/ -void DMA_LLI_Init(DMA_ID_Type dmaId, uint8_t ch, DMA_LLI_Cfg_Type *lliCfg) -{ - uint32_t tmpVal; - /* Get channel register */ - uint32_t DMAChs = DMA_Get_Channel(dmaAddr[dmaId], ch); - - /* Check the parameters */ - CHECK_PARAM(IS_DMA_ID_TYPE(dmaId)); - CHECK_PARAM(IS_DMA_CHAN_TYPE(ch)); - CHECK_PARAM(IS_DMA_TRANS_DIR_TYPE(lliCfg->dir)); - CHECK_PARAM(IS_DMA_PERIPH_REQ_TYPE(lliCfg->dstPeriph)); - CHECK_PARAM(IS_DMA_PERIPH_REQ_TYPE(lliCfg->srcPeriph)); - - /* Disable clock gate when use DMA0 */ - if (DMA0_ID == dmaId) { - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_DMA_0); - } else if (DMA1_ID == dmaId) { - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_DMA_1); - } else if (DMA2_ID == dmaId) { - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_DMA_2); - } - - tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_FLOWCNTRL, lliCfg->dir); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DSTPERIPHERAL, lliCfg->dstPeriph); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SRCPERIPHERAL, lliCfg->srcPeriph); - BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief DMA channel update LLI - * - * @param dmaId: DMA ID type - * @param ch: DMA channel number - * @param LLI: LLI addr - * - * @return None - * -*******************************************************************************/ -void DMA_LLI_Update(DMA_ID_Type dmaId, uint8_t ch, uint32_t LLI) -{ - /* Get channel register */ - uint32_t DMAChs = DMA_Get_Channel(dmaAddr[dmaId], ch); - - /* Check the parameters */ - CHECK_PARAM(IS_DMA_ID_TYPE(dmaId)); - CHECK_PARAM(IS_DMA_CHAN_TYPE(ch)); - - /* Config channel config */ - //BL_WR_REG(DMAChs, DMA_LLI, LLI); - ARCH_MemCpy4((uint32_t *)(uintptr_t)DMAChs, (uint32_t *)(uintptr_t)LLI, 4); -} - -/****************************************************************************/ /** - * @brief DMA channel get LLI counter - * - * @param dmaId: DMA ID type - * @param ch: DMA channel number - * - * @return LLI counter - * -*******************************************************************************/ -uint32_t DMA_LLI_Get_Counter(DMA_ID_Type dmaId, uint8_t ch) -{ - /* Get channel register */ - uint32_t DMAChs = DMA_Get_Channel(dmaAddr[dmaId], ch); - - /* Check the parameters */ - CHECK_PARAM(IS_DMA_ID_TYPE(dmaId)); - CHECK_PARAM(IS_DMA_CHAN_TYPE(ch)); - - return BL_GET_REG_BITS_VAL(BL_RD_REG(DMAChs, DMA_CONFIG), DMA_LLICOUNTER); -} - -/****************************************************************************/ /** - * @brief DMA LLI PingPong Structure Start - * - * @param dmaPpStruct: dma pp struct pointer - * @param Ping_Transfer_len: ping len - * @param Pong_Transfer_len: pong len - * - * @return Succrss or not - * -*******************************************************************************/ -BL_Err_Type DMA_LLI_PpStruct_Set_Transfer_Len(DMA_LLI_PP_Struct *dmaPpStruct, uint16_t Ping_Transfer_len, uint16_t Pong_Transfer_len) -{ - struct DMA_Control_Reg dmaCtrlRegVal_temp; - - if (Ping_Transfer_len > 4096 || Pong_Transfer_len > 4096) { - return ERROR; - } - - dmaCtrlRegVal_temp = PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PING_INDEX].dmaCtrl; - dmaCtrlRegVal_temp.TransferSize = Ping_Transfer_len; - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PING_INDEX].dmaCtrl = dmaCtrlRegVal_temp; - - dmaCtrlRegVal_temp = PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PONG_INDEX].dmaCtrl; - dmaCtrlRegVal_temp.TransferSize = Pong_Transfer_len; - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PONG_INDEX].dmaCtrl = dmaCtrlRegVal_temp; - - DMA_LLI_Init(dmaPpStruct->dmaId, dmaPpStruct->dmaChan, dmaPpStruct->lliCfg); - DMA_LLI_Update(dmaPpStruct->dmaId, dmaPpStruct->dmaChan, (uint32_t)(uintptr_t)&PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PING_INDEX]); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief DMA LLI Start New Transmit for Ping-Pong Buf - * - * @param dmaPpBuf: DMA LLI Ping-Pong Buf - * - * @return None - * -*******************************************************************************/ -void DMA_LLI_PpBuf_Start_New_Transmit(DMA_LLI_PP_Buf *dmaPpBuf) -{ - CPU_Interrupt_Disable_DMA(dmaPpBuf->dmaId); - - if (dmaPpBuf->lliListHeader[dmaPpBuf->idleIndex] != NULL) { - DMA_LLI_Update(dmaPpBuf->dmaId, dmaPpBuf->dmaChan, (uint32_t)(uintptr_t)dmaPpBuf->lliListHeader[dmaPpBuf->idleIndex]); - DMA_Channel_Enable(dmaPpBuf->dmaId, dmaPpBuf->dmaChan); - dmaPpBuf->idleIndex = (dmaPpBuf->idleIndex == 0) ? 1 : 0; - } - - CPU_Interrupt_Enable_DMA(dmaPpBuf->dmaId); -} - -/****************************************************************************/ /** - * @brief DMA LLI Remove Completed Ping-Pong Buf List - * - * @param dmaPpBuf: DMA LLI Ping-Pong Buf - * - * @return Next Ping-Pong Buf List Header - * -*******************************************************************************/ -DMA_LLI_Ctrl_Type *DMA_LLI_PpBuf_Remove_Completed_List(DMA_LLI_PP_Buf *dmaPpBuf) -{ - CPU_Interrupt_Disable_DMA(dmaPpBuf->dmaId); - - dmaPpBuf->lliListHeader[!dmaPpBuf->idleIndex] = NULL; - CPU_Interrupt_Enable_DMA(dmaPpBuf->dmaId); - return dmaPpBuf->lliListHeader[!dmaPpBuf->idleIndex]; -} - -/****************************************************************************/ /** - * @brief DMA LLI Append Buf to List - * - * @param dmaPpBuf: DMA LLI Ping-Pong Buf - * @param dmaLliList: New LLI Buf to Append - * - * @return None - * -*******************************************************************************/ -void DMA_LLI_PpBuf_Append(DMA_LLI_PP_Buf *dmaPpBuf, DMA_LLI_Ctrl_Type *dmaLliList) -{ - DMA_LLI_Ctrl_Type *pLliList = NULL; - CPU_Interrupt_Disable_DMA(dmaPpBuf->dmaId); - - pLliList = dmaPpBuf->lliListHeader[dmaPpBuf->idleIndex]; - - if (pLliList == NULL) { - dmaLliList->nextLLI = 0; - dmaLliList->dmaCtrl.I = 1; - dmaPpBuf->lliListHeader[dmaPpBuf->idleIndex] = dmaLliList; - } else { - /*Append to last */ - while (pLliList->nextLLI != 0) { - pLliList = (DMA_LLI_Ctrl_Type *)(uintptr_t)pLliList->nextLLI; - } - - pLliList->nextLLI = (uint32_t)(uintptr_t)dmaLliList; - pLliList->dmaCtrl.I = 0; - dmaLliList->nextLLI = 0; - dmaLliList->dmaCtrl.I = 1; - } - - if (DMA_Channel_Is_Busy(dmaPpBuf->dmaId, dmaPpBuf->dmaChan) == RESET) { - /* DMA stopped: maybe stop just a few minutes ago(not enter INT due to CPU_Interrupt_Disable) - or has already stopped before this function is called */ - if (dmaPpBuf->lliListHeader[!dmaPpBuf->idleIndex] == NULL) { - /* DMA has already stopped before this function is called */ - DMA_LLI_PpBuf_Start_New_Transmit(dmaPpBuf); - } - } - - CPU_Interrupt_Enable_DMA(dmaPpBuf->dmaId); -} - -/****************************************************************************/ /** - * @brief DMA LLi Destroy Ping-Pong Buf - * - * @param dmaPpBuf: DMA LLI Ping-Pong Buf - * - * @return None - * -*******************************************************************************/ -void DMA_LLI_PpBuf_Destroy(DMA_LLI_PP_Buf *dmaPpBuf) -{ - /* DMA LLI Disable */ - DMA_Channel_Disable(dmaPpBuf->dmaId, dmaPpBuf->dmaChan); - - if (dmaPpBuf->lliListHeader[0] != NULL && dmaPpBuf->onTransCompleted != NULL) { - dmaPpBuf->onTransCompleted(dmaPpBuf->lliListHeader[0]); - } - - dmaPpBuf->lliListHeader[0] = NULL; - - if (dmaPpBuf->lliListHeader[1] != NULL && dmaPpBuf->onTransCompleted != NULL) { - dmaPpBuf->onTransCompleted(dmaPpBuf->lliListHeader[1]); - } - - dmaPpBuf->lliListHeader[1] = NULL; - dmaPpBuf->idleIndex = 0; -} - -/****************************************************************************/ /** - * @brief Mask/Unmask the DMA interrupt - * - * @param dmaId: DMA ID type - * @param ch: DMA channel number - * @param intType: Specifies the interrupt type - * @param intMask: Enable/Disable Specified interrupt type - * - * @return None - * -*******************************************************************************/ -void DMA_IntMask(DMA_ID_Type dmaId, uint8_t ch, DMA_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpVal; - /* Get channel register */ - uint32_t DMAChs = DMA_Get_Channel(dmaAddr[dmaId], ch); - - /* Check the parameters */ - CHECK_PARAM(IS_DMA_ID_TYPE(dmaId)); - CHECK_PARAM(IS_DMA_CHAN_TYPE(ch)); - CHECK_PARAM(IS_DMA_INT_TYPE(intType)); - - switch (intType) { - case DMA_INT_TCOMPLETED: - if (intMask == UNMASK) { - /* UNMASK(Enable) this interrupt */ - tmpVal = BL_CLR_REG_BIT(BL_RD_REG(DMAChs, DMA_CONFIG), DMA_ITC); - BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); - tmpVal = BL_SET_REG_BIT(BL_RD_REG(DMAChs, DMA_CONTROL), DMA_I); - BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal); - } else { - /* MASK(Disable) this interrupt */ - tmpVal = BL_SET_REG_BIT(BL_RD_REG(DMAChs, DMA_CONFIG), DMA_ITC); - BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); - tmpVal = BL_CLR_REG_BIT(BL_RD_REG(DMAChs, DMA_CONTROL), DMA_I); - BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal); - } - - break; - - case DMA_INT_ERR: - if (intMask == UNMASK) { - /* UNMASK(Enable) this interrupt */ - tmpVal = BL_CLR_REG_BIT(BL_RD_REG(DMAChs, DMA_CONFIG), DMA_IE); - BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); - } else { - /* MASK(Disable) this interrupt */ - tmpVal = BL_SET_REG_BIT(BL_RD_REG(DMAChs, DMA_CONFIG), DMA_IE); - BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); - } - - break; - - case DMA_INT_ALL: - if (intMask == UNMASK) { - /* UNMASK(Enable) this interrupt */ - tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_ITC); - tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_IE); - BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); - tmpVal = BL_RD_REG(DMAChs, DMA_CONTROL); - tmpVal = BL_SET_REG_BIT(tmpVal, DMA_I); - BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal); - } else { - /* MASK(Disable) this interrupt */ - tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, DMA_ITC); - tmpVal = BL_SET_REG_BIT(tmpVal, DMA_IE); - BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); - tmpVal = BL_RD_REG(DMAChs, DMA_CONTROL); - tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_I); - BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal); - } - - break; - - default: - break; - } -} - -/****************************************************************************/ /** - * @brief Install DMA interrupt callback function - * - * @param dmaId: DMA ID type - * @param dmaChan: DMA Channel type - * @param intType: DMA interrupt type - * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void DMA_Int_Callback_Install(DMA_ID_Type dmaId, DMA_Chan_Type dmaChan, DMA_INT_Type intType, intCallback_Type *cbFun) -{ - /* Check the parameters */ - CHECK_PARAM(IS_DMA_ID_TYPE(dmaId)); - CHECK_PARAM(IS_DMA_CHAN_TYPE(dmaChan)); - CHECK_PARAM(IS_DMA_INT_TYPE(intType)); - - dmaIntCbfArra[dmaId][dmaChan][intType] = cbFun; -} -#endif - -/****************************************************************************/ /** - * @brief WLSYS DMA0 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void DMA0_ALL_IRQHandler(void) -{ - DMA_IntHandler(DMA0_ID); -} -#endif - -/****************************************************************************/ /** - * @brief WLSYS DMA1 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void DMA1_ALL_IRQHandler(void) -{ - DMA_IntHandler(DMA1_ID); -} -#endif - -/****************************************************************************/ /** - * @brief MMSYS DMA channel 0 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void DMA2_INT0_IRQHandler(void) -{ - DMA_IntHandler(DMA2_ID); -} -#endif - -/****************************************************************************/ /** - * @brief MMSYS DMA channel 1 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void DMA2_INT1_IRQHandler(void) -{ - DMA_IntHandler(DMA2_ID); -} -#endif - -/****************************************************************************/ /** - * @brief MMSYS DMA channel 2 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void DMA2_INT2_IRQHandler(void) -{ - DMA_IntHandler(DMA2_ID); -} -#endif - -/****************************************************************************/ /** - * @brief MMSYS DMA channel 3 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void DMA2_INT3_IRQHandler(void) -{ - DMA_IntHandler(DMA2_ID); -} -#endif - -/****************************************************************************/ /** - * @brief MMSYS DMA channel 4 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void DMA2_INT4_IRQHandler(void) -{ - DMA_IntHandler(DMA2_ID); -} -#endif - -/****************************************************************************/ /** - * @brief MMSYS DMA channel 5 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void DMA2_INT5_IRQHandler(void) -{ - DMA_IntHandler(DMA2_ID); -} -#endif - -/****************************************************************************/ /** - * @brief MMSYS DMA channel 6 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void DMA2_INT6_IRQHandler(void) -{ - DMA_IntHandler(DMA2_ID); -} -#endif - -/****************************************************************************/ /** - * @brief MMSYS DMA channel 7 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void DMA2_INT7_IRQHandler(void) -{ - DMA_IntHandler(DMA2_ID); -} -#endif - -/****************************************************************************/ /** - * @brief DMA LLI PingPong Structure Initial - * - * @param dmaPpStruct: DMA LLI PingPong Config Parameter - * - * @return start success or not - * -*******************************************************************************/ -BL_Err_Type DMA_LLI_PpStruct_Init(DMA_LLI_PP_Struct *dmaPpStruct) -{ - //setup lliList - dmaPpStruct->dmaCtrlRegVal.I = 1; - dmaPpStruct->pingpongIndex = 0; - - if (dmaPpStruct->lliCfg->dir == DMA_TRNS_M2P) { - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PING_INDEX].srcDmaAddr = dmaPpStruct->pingpongBufAddr[0]; - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PING_INDEX].destDmaAddr = dmaPpStruct->operatePeriphAddr; - - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PONG_INDEX].srcDmaAddr = dmaPpStruct->pingpongBufAddr[1]; - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PONG_INDEX].destDmaAddr = dmaPpStruct->operatePeriphAddr; - } else if (dmaPpStruct->lliCfg->dir == DMA_TRNS_P2M) { - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PING_INDEX].srcDmaAddr = dmaPpStruct->operatePeriphAddr; - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PING_INDEX].destDmaAddr = dmaPpStruct->pingpongBufAddr[0]; - - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PONG_INDEX].srcDmaAddr = dmaPpStruct->operatePeriphAddr; - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PONG_INDEX].destDmaAddr = dmaPpStruct->pingpongBufAddr[1]; - } else { - return ERROR; - /*V1.0 version DMA LLI Ping-Pong structure not support P2P & M2M MODE*/ - } - - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PING_INDEX].nextLLI = (uint32_t)(uintptr_t)&PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PONG_INDEX]; - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PING_INDEX].dmaCtrl = dmaPpStruct->dmaCtrlRegVal; - - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PONG_INDEX].nextLLI = (uint32_t)(uintptr_t)&PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PING_INDEX]; - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PONG_INDEX].dmaCtrl = dmaPpStruct->dmaCtrlRegVal; - - DMA_LLI_Init(dmaPpStruct->dmaId, dmaPpStruct->dmaChan, dmaPpStruct->lliCfg); - - DMA_LLI_Update(dmaPpStruct->dmaId, dmaPpStruct->dmaChan, (uint32_t)(uintptr_t)&PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PING_INDEX]); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief DMA LLI PingPong Structure Start - * - * @param dmaPpStruct: None - * - * @return None - * -*******************************************************************************/ -void DMA_LLI_PpStruct_Start(DMA_LLI_PP_Struct *dmaPpStruct) -{ - DMA_Channel_Enable(dmaPpStruct->dmaId, dmaPpStruct->dmaChan); -} - -/****************************************************************************/ /** - * @brief DMA LLI PingPong Structure Stop - * - * @param dmaPpStruct: None - * - * @return None - * -*******************************************************************************/ -void DMA_LLI_PpStruct_Stop(DMA_LLI_PP_Struct *dmaPpStruct) -{ - DMA_Channel_Disable(dmaPpStruct->dmaId, dmaPpStruct->dmaChan); -} - -/*@} end of group DMA_Public_Functions */ - -/*@} end of group DMA */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dma2d.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dma2d.c deleted file mode 100644 index d406f906f0..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dma2d.c +++ /dev/null @@ -1,1228 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_dma2d.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808.h" -#include "bl808_dma2d.h" -#include "bl808_glb.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup DMA2D - * @{ - */ - -/** @defgroup DMA2D_Private_Macros - * @{ - */ -#define DMA2D_Get_Channel(id_base, ch) ((id_base) + (ch)*0x100) - -/*@} end of group DMA2D_Private_Macros */ - -/** @defgroup DMA2D_Private_Types - * @{ - */ - -/*@} end of group DMA2D_Private_Types */ - -/** @defgroup DMA2D_Private_Variables - * @{ - */ -static const uint32_t dma2dAddr[DMA2D_ID_MAX] = { DMA2D_BASE }; -#ifndef BFLB_USE_HAL_DRIVER -static intCallback_Type *dma2dIntCbfArra[DMA2D_ID_MAX][DMA2D_CH_MAX][DMA2D_INT_ALL] = { - { { NULL } } -}; -#endif -static DMA2D_LLI_Ctrl_Type PingPongListArra[DMA2D_ID_MAX][DMA2D_CH_MAX][2]; - -/*@} end of group DMA2D_Private_Variables */ - -/** @defgroup DMA2D_Global_Variables - * @{ - */ - -/*@} end of group DMA2D_Global_Variables */ - -/** @defgroup DMA2D_Private_Fun_Declaration - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -static void DMA2D_IntHandler(DMA2D_ID_Type dmaId); -#endif -static void CPU_Interrupt_Enable_DMA2D(DMA2D_ID_Type dmaId); -static void CPU_Interrupt_Disable_DMA2D(DMA2D_ID_Type dmaId); - -/*@} end of group DMA2D_Private_Fun_Declaration */ - -/** @defgroup DMA2D_Private_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief DMA2D interrupt handler - * - * @param dmaId: DMA2D ID type - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -static void DMA2D_IntHandler(DMA2D_ID_Type dmaId) -{ - uint32_t tmpVal; - uint8_t ch; - /* Get DMA2D register */ - uint32_t DMA2DChs = dma2dAddr[dmaId]; - - for (ch = 0; ch < DMA2D_CH_MAX; ch++) { - tmpVal = BL_RD_REG(DMA2DChs, DMA2D_DMA_INTSTATUS); - - if ((BL_GET_REG_BITS_VAL(tmpVal, DMA2D_INTSTATUS) & (1 << ch)) != 0) { - /* Clear interrupt */ - BL_WR_REG(DMA2DChs, DMA2D_DMA_INTTCCLEAR, 1 << ch); - - if (dma2dIntCbfArra[dmaId][ch][DMA2D_INT_TCOMPLETED] != NULL) { - /* Call the callback function */ - dma2dIntCbfArra[dmaId][ch][DMA2D_INT_TCOMPLETED](); - } - } - } -} -#endif - -/****************************************************************************/ /** - * @brief CPU enable DMA2D interrupt - * - * @param dmaId: DMA2D ID type - * - * @return None - * -*******************************************************************************/ -static void CPU_Interrupt_Enable_DMA2D(DMA2D_ID_Type dmaId) -{ - /* Check the parameters */ - CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId)); - - CPU_Interrupt_Enable(DMA2D_INT0_IRQn); - CPU_Interrupt_Enable(DMA2D_INT1_IRQn); -} - -/****************************************************************************/ /** - * @brief CPU disable DMA2D interrupt - * - * @param dmaId: DMA2D ID type - * - * @return None - * -*******************************************************************************/ -static void CPU_Interrupt_Disable_DMA2D(DMA2D_ID_Type dmaId) -{ - /* Check the parameters */ - CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId)); - - CPU_Interrupt_Disable(DMA2D_INT0_IRQn); - CPU_Interrupt_Disable(DMA2D_INT1_IRQn); -} - -/*@} end of group DMA2D_Private_Functions */ - -/** @defgroup DMA2D_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief DMA2D enable - * - * @param dmaId: DMA2D ID type - * - * @return None - * -*******************************************************************************/ -void DMA2D_Enable(DMA2D_ID_Type dmaId) -{ - uint32_t tmpVal; - /* Get DMA2D register */ - uint32_t DMA2DChs = dma2dAddr[dmaId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId)); - - tmpVal = BL_RD_REG(DMA2DChs, DMA2D_DMA_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, DMA2D_E); - BL_WR_REG(DMA2DChs, DMA2D_DMA_CONFIG, tmpVal); -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(DMA2D_INT0_IRQn, DMA2D_INT0_IRQHandler); - Interrupt_Handler_Register(DMA2D_INT1_IRQn, DMA2D_INT1_IRQHandler); -#endif -} - -/****************************************************************************/ /** - * @brief DMA2D disable - * - * @param dmaId: DMA2D ID type - * - * @return None - * -*******************************************************************************/ -void DMA2D_Disable(DMA2D_ID_Type dmaId) -{ - uint32_t tmpVal; - /* Get DMA2D register */ - uint32_t DMA2DChs = dma2dAddr[dmaId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId)); - - tmpVal = BL_RD_REG(DMA2DChs, DMA2D_DMA_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, DMA2D_E); - BL_WR_REG(DMA2DChs, DMA2D_DMA_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief DMA2D configure function - * - * @param dmaId: DMA2D ID type - * - * @return SUCCESS - * -*******************************************************************************/ -void DMA2D_Init(DMA2D_ID_Type dmaId, uint8_t ch, DMA2D_Cfg_Type *cfg) -{ - uint32_t tmpVal; - /* Get channel register */ - uint32_t DMA2DChs = DMA2D_Get_Channel(dma2dAddr[dmaId], ch); - - tmpVal = BL_RD_REG(DMA2DChs, DMA2D_C0_CFG); - BL_WR_REG(DMA2DChs, DMA2D_C0_CFG, BL_SET_REG_BIT(tmpVal, DMA2D_REG_DMA_2D_EN)); - - tmpVal = BL_RD_REG(DMA2DChs, DMA2D_C0_SRC_CNT); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_SRC_X_CNT, cfg->srcCntX); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_SRC_Y_CNT, cfg->srcCntY); - BL_WR_REG(DMA2DChs, DMA2D_C0_SRC_CNT, tmpVal); - - BL_WR_REG(DMA2DChs, DMA2D_C0_SRC_XIC, cfg->srcIncrX); - BL_WR_REG(DMA2DChs, DMA2D_C0_SRC_YIC, cfg->srcIncrY); - - tmpVal = BL_RD_REG(DMA2DChs, DMA2D_C0_DST_CNT); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_DST_X_CNT, cfg->dstCntX); - BL_WR_REG(DMA2DChs, DMA2D_C0_DST_CNT, tmpVal); - - BL_WR_REG(DMA2DChs, DMA2D_C0_DST_XIC, cfg->dstIncrX); - BL_WR_REG(DMA2DChs, DMA2D_C0_DST_YIC, cfg->dstIncrY); -} - -/****************************************************************************/ /** - * @brief DMA2D channel init - * - * @param dmaId: DMA2D ID type - * @param chCfg: DMA2D configuration - * - * @return None - * -*******************************************************************************/ -void DMA2D_Channel_Init(DMA2D_ID_Type dmaId, DMA2D_Channel_Cfg_Type *chCfg) -{ - uint32_t tmpVal; - /* Get channel register */ - uint32_t DMA2DChs = DMA2D_Get_Channel(dma2dAddr[dmaId], chCfg->ch); - - /* Check the parameters */ - CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId)); - CHECK_PARAM(IS_DMA2D_CHAN_TYPE(chCfg->ch)); - CHECK_PARAM(IS_DMA2D_TRANS_WIDTH_TYPE(chCfg->srcTransfWidth)); - CHECK_PARAM(IS_DMA2D_TRANS_WIDTH_TYPE(chCfg->dstTransfWidth)); - CHECK_PARAM(IS_DMA2D_BURST_SIZE_TYPE(chCfg->srcBurstSize)); - CHECK_PARAM(IS_DMA2D_BURST_SIZE_TYPE(chCfg->dstBurstSize)); - CHECK_PARAM(IS_DMA2D_TRANS_DIR_TYPE(chCfg->dir)); - CHECK_PARAM(IS_DMA2D_PERIPH_REQ_TYPE(chCfg->dstPeriph)); - CHECK_PARAM(IS_DMA2D_PERIPH_REQ_TYPE(chCfg->srcPeriph)); - - /* Config channel config */ - BL_WR_REG(DMA2DChs, DMA2D_C0SRCADDR, chCfg->srcDmaAddr); - BL_WR_REG(DMA2DChs, DMA2D_C0DSTADDR, chCfg->destDmaAddr); - - tmpVal = BL_RD_REG(DMA2DChs, DMA2D_C0_BUS); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_TRANSFERSIZE, chCfg->transfLength); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_SRC_SIZE, chCfg->srcTransfWidth); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_DST_SIZE, chCfg->dstTransfWidth); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_SRC_BURST, chCfg->srcBurstSize); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_DST_BURST, chCfg->dstBurstSize); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_SI, chCfg->srcAddrInc); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_DI, chCfg->destAddrInc); - BL_WR_REG(DMA2DChs, DMA2D_C0_BUS, tmpVal); - - tmpVal = BL_RD_REG(DMA2DChs, DMA2D_C0_CFG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_FLOWCNTRL, chCfg->dir); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_DSTPERIPHERAL, chCfg->dstPeriph); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_SRCPERIPHERAL, chCfg->srcPeriph); - BL_WR_REG(DMA2DChs, DMA2D_C0_CFG, tmpVal); -} - -/****************************************************************************/ /** - * @brief DMA2D set default value of all registers function - * - * @param dmaId: DMA2D ID type - * - * @return SUCCESS - * -*******************************************************************************/ -void DMA2D_DeInit(DMA2D_ID_Type dmaId) -{ - /* Check the parameters */ - CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId)); - - GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_DMA2D); -} - -/****************************************************************************/ /** - * @brief DMA2D channel update source memory address and len - * - * @param dmaId: DMA2D ID type - * @param ch: DMA2D channel - * @param memAddr: source memoty address - * @param len: source memory data length - * - * @return None - * -*******************************************************************************/ -void DMA2D_Channel_Update_SrcMemcfg(DMA2D_ID_Type dmaId, uint8_t ch, uint32_t memAddr, uint32_t len) -{ - uint32_t tmpVal; - /* Get channel register */ - uint32_t DMA2DChs = DMA2D_Get_Channel(dma2dAddr[dmaId], ch); - - /* Check the parameters */ - CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId)); - CHECK_PARAM(IS_DMA2D_CHAN_TYPE(ch)); - - /* config channel config*/ - BL_WR_REG(DMA2DChs, DMA2D_C0SRCADDR, memAddr); - tmpVal = BL_RD_REG(DMA2DChs, DMA2D_C0_BUS); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_TRANSFERSIZE, len); - BL_WR_REG(DMA2DChs, DMA2D_C0_BUS, tmpVal); -} - -/****************************************************************************/ /** - * @brief DMA2D channel update destination memory address and len - * - * @param dmaId: DMA2D ID type - * @param ch: DMA2D channel - * @param memAddr: destination memoty address - * @param len: destination memory data length - * - * @return None - * -*******************************************************************************/ -void DMA2D_Channel_Update_DstMemcfg(DMA2D_ID_Type dmaId, uint8_t ch, uint32_t memAddr, uint32_t len) -{ - uint32_t tmpVal; - /* Get channel register */ - uint32_t DMA2DChs = DMA2D_Get_Channel(dma2dAddr[dmaId], ch); - - /* Check the parameters */ - CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId)); - CHECK_PARAM(IS_DMA2D_CHAN_TYPE(ch)); - - /* config channel config*/ - BL_WR_REG(DMA2DChs, DMA2D_C0DSTADDR, memAddr); - tmpVal = BL_RD_REG(DMA2DChs, DMA2D_C0_BUS); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_TRANSFERSIZE, len); - BL_WR_REG(DMA2DChs, DMA2D_C0_BUS, tmpVal); -} - -/****************************************************************************/ /** - * @brief Get DMA2D channel tranfersize - * - * @param dmaId: DMA2D ID type - * @param ch: DMA2D channel - * - * @return tranfersize size - * -*******************************************************************************/ -uint32_t DMA2D_Channel_TranferSize(DMA2D_ID_Type dmaId, uint8_t ch) -{ - /* Get channel register */ - uint32_t DMA2DChs = DMA2D_Get_Channel(dma2dAddr[dmaId], ch); - - /* Check the parameters */ - CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId)); - CHECK_PARAM(IS_DMA2D_CHAN_TYPE(ch)); - - return BL_GET_REG_BITS_VAL(BL_RD_REG(DMA2DChs, DMA2D_C0_BUS), DMA2D_TRANSFERSIZE); -} - -/****************************************************************************/ /** - * @brief Get DMA2D channel busy status - * - * @param dmaId: DMA2D ID type - * @param ch: DMA2D channel - * - * @return SET or RESET - * -*******************************************************************************/ -BL_Sts_Type DMA2D_Channel_Is_Busy(DMA2D_ID_Type dmaId, uint8_t ch) -{ - /* Get channel register */ - uint32_t DMA2DChs = DMA2D_Get_Channel(dma2dAddr[dmaId], ch); - - /* Check the parameters */ - CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId)); - CHECK_PARAM(IS_DMA2D_CHAN_TYPE(ch)); - - return BL_IS_REG_BIT_SET(BL_RD_REG(DMA2DChs, DMA2D_C0_CFG), DMA2D_CH_EN) == 1 ? SET : RESET; -} - -/****************************************************************************/ /** - * @brief DMA2D enable - * - * @param dmaId: DMA2D ID type - * @param ch: DMA2D channel number - * - * @return None - * -*******************************************************************************/ -void DMA2D_Channel_Enable(DMA2D_ID_Type dmaId, uint8_t ch) -{ - uint32_t tmpVal; - /* Get channel register */ - uint32_t DMA2DChs = DMA2D_Get_Channel(dma2dAddr[dmaId], ch); - - /* Check the parameters */ - CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId)); - CHECK_PARAM(IS_DMA2D_CHAN_TYPE(ch)); - - tmpVal = BL_RD_REG(DMA2DChs, DMA2D_C0_CFG); - tmpVal = BL_SET_REG_BIT(tmpVal, DMA2D_CH_EN); - BL_WR_REG(DMA2DChs, DMA2D_C0_CFG, tmpVal); -} - -/****************************************************************************/ /** - * @brief DMA2D disable - * - * @param dmaId: DMA2D ID type - * @param ch: DMA2D channel number - * - * @return None - * -*******************************************************************************/ -void DMA2D_Channel_Disable(DMA2D_ID_Type dmaId, uint8_t ch) -{ - uint32_t tmpVal; - /* Get channel register */ - uint32_t DMA2DChs = DMA2D_Get_Channel(dma2dAddr[dmaId], ch); - - /* Check the parameters */ - CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId)); - CHECK_PARAM(IS_DMA2D_CHAN_TYPE(ch)); - - tmpVal = BL_RD_REG(DMA2DChs, DMA2D_C0_CFG); - tmpVal = BL_CLR_REG_BIT(tmpVal, DMA2D_CH_EN); - BL_WR_REG(DMA2DChs, DMA2D_C0_CFG, tmpVal); -} - -/****************************************************************************/ /** - * @brief DMA2D init LLI transfer - * - * @param dmaId: DMA2D ID type - * @param ch: DMA2D channel number - * @param lliCfg: LLI configuration - * - * @return None - * -*******************************************************************************/ -void DMA2D_LLI_Init(DMA2D_ID_Type dmaId, uint8_t ch, DMA2D_LLI_Cfg_Type *lliCfg) -{ - uint32_t tmpVal; - /* Get channel register */ - uint32_t DMA2DChs = DMA2D_Get_Channel(dma2dAddr[dmaId], ch); - - /* Check the parameters */ - CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId)); - CHECK_PARAM(IS_DMA2D_CHAN_TYPE(ch)); - CHECK_PARAM(IS_DMA2D_TRANS_DIR_TYPE(lliCfg->dir)); - CHECK_PARAM(IS_DMA2D_PERIPH_REQ_TYPE(lliCfg->dstPeriph)); - CHECK_PARAM(IS_DMA2D_PERIPH_REQ_TYPE(lliCfg->srcPeriph)); - - tmpVal = BL_RD_REG(DMA2DChs, DMA2D_C0_CFG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_FLOWCNTRL, lliCfg->dir); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_DSTPERIPHERAL, lliCfg->dstPeriph); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_SRCPERIPHERAL, lliCfg->srcPeriph); - BL_WR_REG(DMA2DChs, DMA2D_C0_CFG, tmpVal); -} - -/****************************************************************************/ /** - * @brief DMA2D channel update LLI - * - * @param dmaId: DMA2D ID type - * @param ch: DMA2D channel number - * @param LLI: LLI addr - * - * @return None - * -*******************************************************************************/ -void DMA2D_LLI_Update(DMA2D_ID_Type dmaId, uint8_t ch, uint32_t LLI) -{ - /* Get channel register */ - uint32_t DMA2DChs = DMA2D_Get_Channel(dma2dAddr[dmaId], ch) + 0x100; - - /* Check the parameters */ - CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId)); - CHECK_PARAM(IS_DMA2D_CHAN_TYPE(ch)); - - /* Config channel config */ - //BL_WR_REG(DMA2DChs, DMA2D_LLI, LLI); - ARCH_MemCpy4((uint32_t *)(uintptr_t)DMA2DChs, (uint32_t *)(uintptr_t)LLI, 10); -} - -/****************************************************************************/ /** - * @brief DMA2D channel get LLI counter - * - * @param dmaId: DMA2D ID type - * @param ch: DMA2D channel number - * - * @return LLI counter - * -*******************************************************************************/ -uint32_t DMA2D_LLI_Get_Counter(DMA2D_ID_Type dmaId, uint8_t ch) -{ - /* Get channel register */ - uint32_t DMA2DChs = DMA2D_Get_Channel(dma2dAddr[dmaId], ch); - - /* Check the parameters */ - CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId)); - CHECK_PARAM(IS_DMA2D_CHAN_TYPE(ch)); - - return BL_GET_REG_BITS_VAL(BL_RD_REG(DMA2DChs, DMA2D_C0_CFG), DMA2D_LLICOUNTER); -} - -/****************************************************************************/ /** - * @brief DMA2D LLI PingPong Structure Start - * - * @param dmaPpStruct: dma pp struct pointer - * @param Ping_Transfer_len: ping len - * @param Pong_Transfer_len: pong len - * - * @return Succrss or not - * -*******************************************************************************/ -BL_Err_Type DMA2D_LLI_PpStruct_Set_Transfer_Len(DMA2D_LLI_PP_Struct *dmaPpStruct, uint16_t Ping_Transfer_len, uint16_t Pong_Transfer_len) -{ - struct DMA2D_Control_Reg dmaCtrlRegVal_temp; - - if (Ping_Transfer_len > 4096 || Pong_Transfer_len > 4096) { - return ERROR; - } - - dmaCtrlRegVal_temp = PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PING_INDEX].dmaCtrl; - dmaCtrlRegVal_temp.TransferSize = Ping_Transfer_len; - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PING_INDEX].dmaCtrl = dmaCtrlRegVal_temp; - - dmaCtrlRegVal_temp = PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PONG_INDEX].dmaCtrl; - dmaCtrlRegVal_temp.TransferSize = Pong_Transfer_len; - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PONG_INDEX].dmaCtrl = dmaCtrlRegVal_temp; - - DMA2D_LLI_Init(dmaPpStruct->dmaId, dmaPpStruct->dmaChan, dmaPpStruct->lliCfg); - DMA2D_LLI_Update(dmaPpStruct->dmaId, dmaPpStruct->dmaChan, (uint32_t)(uintptr_t)&PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PING_INDEX]); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief DMA2D LLI Start New Transmit for Ping-Pong Buf - * - * @param dmaPpBuf: DMA2D LLI Ping-Pong Buf - * - * @return None - * -*******************************************************************************/ -void DMA2D_LLI_PpBuf_Start_New_Transmit(DMA2D_LLI_PP_Buf *dmaPpBuf) -{ - CPU_Interrupt_Disable_DMA2D(dmaPpBuf->dmaId); - - if (dmaPpBuf->lliListHeader[dmaPpBuf->idleIndex] != NULL) { - DMA2D_LLI_Update(dmaPpBuf->dmaId, dmaPpBuf->dmaChan, (uint32_t)(uintptr_t)dmaPpBuf->lliListHeader[dmaPpBuf->idleIndex]); - DMA2D_Channel_Enable(dmaPpBuf->dmaId, dmaPpBuf->dmaChan); - dmaPpBuf->idleIndex = (dmaPpBuf->idleIndex == 0) ? 1 : 0; - } - - CPU_Interrupt_Enable_DMA2D(dmaPpBuf->dmaId); -} - -/****************************************************************************/ /** - * @brief DMA2D LLI Remove Completed Ping-Pong Buf List - * - * @param dmaPpBuf: DMA2D LLI Ping-Pong Buf - * - * @return Next Ping-Pong Buf List Header - * -*******************************************************************************/ -DMA2D_LLI_Ctrl_Type *DMA2D_LLI_PpBuf_Remove_Completed_List(DMA2D_LLI_PP_Buf *dmaPpBuf) -{ - CPU_Interrupt_Disable_DMA2D(dmaPpBuf->dmaId); - - dmaPpBuf->lliListHeader[!dmaPpBuf->idleIndex] = NULL; - CPU_Interrupt_Enable_DMA2D(dmaPpBuf->dmaId); - return dmaPpBuf->lliListHeader[!dmaPpBuf->idleIndex]; -} - -/****************************************************************************/ /** - * @brief DMA2D LLI Append Buf to List - * - * @param dmaPpBuf: DMA2D LLI Ping-Pong Buf - * @param dmaLliList: New LLI Buf to Append - * - * @return None - * -*******************************************************************************/ -void DMA2D_LLI_PpBuf_Append(DMA2D_LLI_PP_Buf *dmaPpBuf, DMA2D_LLI_Ctrl_Type *dmaLliList) -{ - DMA2D_LLI_Ctrl_Type *pLliList = NULL; - CPU_Interrupt_Disable_DMA2D(dmaPpBuf->dmaId); - - pLliList = dmaPpBuf->lliListHeader[dmaPpBuf->idleIndex]; - - if (pLliList == NULL) { - dmaLliList->nextLLI = 0; - dmaLliList->dmaCtrl.I = 1; - dmaPpBuf->lliListHeader[dmaPpBuf->idleIndex] = dmaLliList; - } else { - /*Append to last */ - while (pLliList->nextLLI != 0) { - pLliList = (DMA2D_LLI_Ctrl_Type *)(uintptr_t)pLliList->nextLLI; - } - - pLliList->nextLLI = (uint32_t)(uintptr_t)dmaLliList; - pLliList->dmaCtrl.I = 0; - dmaLliList->nextLLI = 0; - dmaLliList->dmaCtrl.I = 1; - } - - if (DMA2D_Channel_Is_Busy(dmaPpBuf->dmaId, dmaPpBuf->dmaChan) == RESET) { - /* DMA2D stopped: maybe stop just a few minutes ago(not enter INT due to CPU_Interrupt_Disable) - or has already stopped before this function is called */ - if (dmaPpBuf->lliListHeader[!dmaPpBuf->idleIndex] == NULL) { - /* DMA2D has already stopped before this function is called */ - DMA2D_LLI_PpBuf_Start_New_Transmit(dmaPpBuf); - } - } - - CPU_Interrupt_Enable_DMA2D(dmaPpBuf->dmaId); -} - -/****************************************************************************/ /** - * @brief DMA2D LLi Destroy Ping-Pong Buf - * - * @param dmaPpBuf: DMA2D LLI Ping-Pong Buf - * - * @return None - * -*******************************************************************************/ -void DMA2D_LLI_PpBuf_Destroy(DMA2D_LLI_PP_Buf *dmaPpBuf) -{ - /* DMA2D LLI Disable */ - DMA2D_Channel_Disable(dmaPpBuf->dmaId, dmaPpBuf->dmaChan); - - if (dmaPpBuf->lliListHeader[0] != NULL && dmaPpBuf->onTransCompleted != NULL) { - dmaPpBuf->onTransCompleted(dmaPpBuf->lliListHeader[0]); - } - - dmaPpBuf->lliListHeader[0] = NULL; - - if (dmaPpBuf->lliListHeader[1] != NULL && dmaPpBuf->onTransCompleted != NULL) { - dmaPpBuf->onTransCompleted(dmaPpBuf->lliListHeader[1]); - } - - dmaPpBuf->lliListHeader[1] = NULL; - dmaPpBuf->idleIndex = 0; -} - -/****************************************************************************/ /** - * @brief Mask/Unmask the DMA2D interrupt - * - * @param dmaId: DMA2D ID type - * @param ch: DMA2D channel number - * @param intType: Specifies the interrupt type - * @param intMask: Enable/Disable Specified interrupt type - * - * @return None - * -*******************************************************************************/ -void DMA2D_IntMask(DMA2D_ID_Type dmaId, uint8_t ch, DMA2D_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpVal; - /* Get channel register */ - uint32_t DMA2DChs = DMA2D_Get_Channel(dma2dAddr[dmaId], ch); - - /* Check the parameters */ - CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId)); - CHECK_PARAM(IS_DMA2D_CHAN_TYPE(ch)); - CHECK_PARAM(IS_DMA2D_INT_TYPE(intType)); - - switch (intType) { - case DMA2D_INT_TCOMPLETED: - if (intMask == UNMASK) { - /* UNMASK(Enable) this interrupt */ - tmpVal = BL_SET_REG_BIT(BL_RD_REG(DMA2DChs, DMA2D_C0_BUS), DMA2D_I); - BL_WR_REG(DMA2DChs, DMA2D_C0_BUS, tmpVal); - } else { - /* MASK(Disable) this interrupt */ - tmpVal = BL_CLR_REG_BIT(BL_RD_REG(DMA2DChs, DMA2D_C0_BUS), DMA2D_I); - BL_WR_REG(DMA2DChs, DMA2D_C0_BUS, tmpVal); - } - - break; - - case DMA2D_INT_ALL: - if (intMask == UNMASK) { - /* UNMASK(Enable) this interrupt */ - tmpVal = BL_RD_REG(DMA2DChs, DMA2D_C0_BUS); - tmpVal = BL_SET_REG_BIT(tmpVal, DMA2D_I); - BL_WR_REG(DMA2DChs, DMA2D_C0_BUS, tmpVal); - } else { - /* MASK(Disable) this interrupt */ - tmpVal = BL_RD_REG(DMA2DChs, DMA2D_C0_BUS); - tmpVal = BL_CLR_REG_BIT(tmpVal, DMA2D_I); - BL_WR_REG(DMA2DChs, DMA2D_C0_BUS, tmpVal); - } - - break; - - default: - break; - } -} - -/****************************************************************************/ /** - * @brief Install DMA2D interrupt callback function - * - * @param dmaId: DMA2D ID type - * @param dmaChan: DMA2D Channel type - * @param intType: DMA2D interrupt type - * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void DMA2D_Int_Callback_Install(DMA2D_ID_Type dmaId, DMA2D_Chan_Type dmaChan, DMA2D_INT_Type intType, intCallback_Type *cbFun) -{ - /* Check the parameters */ - CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId)); - CHECK_PARAM(IS_DMA2D_CHAN_TYPE(dmaChan)); - CHECK_PARAM(IS_DMA2D_INT_TYPE(intType)); - - dma2dIntCbfArra[dmaId][dmaChan][intType] = cbFun; -} -#endif - -/****************************************************************************/ /** - * @brief MMSYS DMA2D channel 0 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void DMA2D_INT0_IRQHandler(void) -{ - DMA2D_IntHandler(DMA2D0_ID); -} -#endif - -/****************************************************************************/ /** - * @brief MMSYS DMA2D channel 1 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void DMA2D_INT1_IRQHandler(void) -{ - DMA2D_IntHandler(DMA2D0_ID); -} -#endif - -/****************************************************************************/ /** - * @brief DMA2D LLI PingPong Structure Initial - * - * @param dmaPpStruct: DMA2D LLI PingPong Config Parameter - * - * @return start success or not - * -*******************************************************************************/ -BL_Err_Type DMA2D_LLI_PpStruct_Init(DMA2D_LLI_PP_Struct *dmaPpStruct) -{ - //setup lliList - dmaPpStruct->dmaCtrlRegVal.I = 1; - dmaPpStruct->pingpongIndex = 0; - - if (dmaPpStruct->lliCfg->dir == DMA2D_TRNS_M2P) { - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PING_INDEX].srcDmaAddr = dmaPpStruct->pingpongBufAddr[0]; - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PING_INDEX].destDmaAddr = dmaPpStruct->operatePeriphAddr; - - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PONG_INDEX].srcDmaAddr = dmaPpStruct->pingpongBufAddr[1]; - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PONG_INDEX].destDmaAddr = dmaPpStruct->operatePeriphAddr; - } else if (dmaPpStruct->lliCfg->dir == DMA2D_TRNS_P2M) { - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PING_INDEX].srcDmaAddr = dmaPpStruct->operatePeriphAddr; - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PING_INDEX].destDmaAddr = dmaPpStruct->pingpongBufAddr[0]; - - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PONG_INDEX].srcDmaAddr = dmaPpStruct->operatePeriphAddr; - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PONG_INDEX].destDmaAddr = dmaPpStruct->pingpongBufAddr[1]; - } else { - return ERROR; - /*V1.0 version DMA2D LLI Ping-Pong structure not support P2P & M2M MODE*/ - } - - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PING_INDEX].nextLLI = (uint32_t)(uintptr_t)&PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PONG_INDEX]; - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PING_INDEX].dmaCtrl = dmaPpStruct->dmaCtrlRegVal; - - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PONG_INDEX].nextLLI = (uint32_t)(uintptr_t)&PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PING_INDEX]; - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PONG_INDEX].dmaCtrl = dmaPpStruct->dmaCtrlRegVal; - - DMA2D_LLI_Init(dmaPpStruct->dmaId, dmaPpStruct->dmaChan, dmaPpStruct->lliCfg); - - DMA2D_LLI_Update(dmaPpStruct->dmaId, dmaPpStruct->dmaChan, (uint32_t)(uintptr_t)&PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PING_INDEX]); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief DMA2D LLI PingPong Structure Start - * - * @param dmaPpStruct: None - * - * @return None - * -*******************************************************************************/ -void DMA2D_LLI_PpStruct_Start(DMA2D_LLI_PP_Struct *dmaPpStruct) -{ - DMA2D_Channel_Enable(dmaPpStruct->dmaId, dmaPpStruct->dmaChan); -} - -/****************************************************************************/ /** - * @brief DMA2D LLI PingPong Structure Stop - * - * @param dmaPpStruct: None - * - * @return None - * -*******************************************************************************/ -void DMA2D_LLI_PpStruct_Stop(DMA2D_LLI_PP_Struct *dmaPpStruct) -{ - DMA2D_Channel_Disable(dmaPpStruct->dmaId, dmaPpStruct->dmaChan); -} - -/****************************************************************************/ /** - * @brief DMA2D translate picture - * - * @param cfg: Pointer of DMA2D picture configure type - * @param lliCfg: Pointer of DMA2D LLI ctrl type - * - * @return None - * -*******************************************************************************/ -void DMA2D_Picture_Translate_Calculate(DMA2D_Picture_Cfg_Type *cfg, DMA2D_LLI_Ctrl_Type *lliCfg) -{ - uint32_t tmpVal = 1 << cfg->transWidth; - lliCfg->dmaCtrl.SRC_SIZE = cfg->transWidth; - lliCfg->dmaCtrl.DST_SIZE = cfg->transWidth; - - DMA2D_Picture_Cfg_Type pictureCfg = { - .transWidth = cfg->transWidth, - .pixWidth = cfg->pixWidth, - .srcAddr = cfg->srcAddr, - .srcWidth = cfg->srcWidth, - .srcX0 = cfg->srcX0, - .srcY0 = cfg->srcY0, - .srcX1 = cfg->srcX1, - .srcY1 = cfg->srcY1, - .dstAddr = cfg->dstAddr, - .dstWidth = cfg->dstWidth, - .dstX0 = cfg->dstX0, - .dstY0 = cfg->dstY0, - }; - - if (cfg->srcX0 > cfg->srcX1 && cfg->srcY0 <= cfg->srcY1) { - pictureCfg.srcX0 = cfg->srcX1; - pictureCfg.srcX1 = cfg->srcX0; - pictureCfg.dstAddr = pictureCfg.dstAddr - (pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth; - } else if (cfg->srcX0 <= cfg->srcX1 && cfg->srcY0 > cfg->srcY1) { - pictureCfg.srcY0 = cfg->srcY1; - pictureCfg.srcY1 = cfg->srcY0; - pictureCfg.dstAddr = pictureCfg.dstAddr - (pictureCfg.srcY1 - pictureCfg.srcY0) * pictureCfg.pixWidth * pictureCfg.srcWidth; - } else if (cfg->srcX0 > cfg->srcX1 && cfg->srcY0 > cfg->srcY1) { - pictureCfg.srcX0 = cfg->srcX1; - pictureCfg.srcX1 = cfg->srcX0; - pictureCfg.srcY0 = cfg->srcY1; - pictureCfg.srcY1 = cfg->srcY0; - pictureCfg.dstAddr = pictureCfg.dstAddr - (pictureCfg.srcY1 - pictureCfg.srcY0) * pictureCfg.pixWidth * pictureCfg.srcWidth - (pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth; - } - - lliCfg->srcDmaAddr = pictureCfg.srcAddr + pictureCfg.srcWidth * pictureCfg.pixWidth * pictureCfg.srcY0 + pictureCfg.pixWidth * pictureCfg.srcX0; - lliCfg->destDmaAddr = pictureCfg.dstAddr + pictureCfg.dstWidth * pictureCfg.pixWidth * pictureCfg.dstY0 + pictureCfg.pixWidth * pictureCfg.dstX0; - - lliCfg->dma2dCfg.srcCntX = (pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth / tmpVal; - lliCfg->dma2dCfg.srcIncrX = tmpVal; - lliCfg->dma2dCfg.srcCntY = pictureCfg.srcY1 - pictureCfg.srcY0; - lliCfg->dma2dCfg.srcIncrY = (pictureCfg.srcWidth - pictureCfg.srcX1 + pictureCfg.srcX0) * pictureCfg.pixWidth + tmpVal; - lliCfg->dma2dCfg.dstCntX = (pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth / tmpVal; - lliCfg->dma2dCfg.dstIncrX = tmpVal; - lliCfg->dma2dCfg.dstIncrY = (pictureCfg.dstWidth - pictureCfg.srcX1 + pictureCfg.srcX0) * pictureCfg.pixWidth + tmpVal; -} - -/****************************************************************************/ /** - * @brief DMA2D rotate picture - * - * @param cfg: Pointer of DMA2D picture configure type - * @param lliCfg: Pointer of DMA2D LLI ctrl type - * @param rotate: Rotate degree type - * - * @return None - * -*******************************************************************************/ -void DMA2D_Picture_Rotate_Calculate(DMA2D_Picture_Cfg_Type *cfg, DMA2D_LLI_Ctrl_Type *lliCfg, DMA2D_Rotate_Type rotate) -{ - uint32_t tmpVal = 1 << cfg->transWidth; - lliCfg->dmaCtrl.SRC_SIZE = cfg->transWidth; - lliCfg->dmaCtrl.DST_SIZE = cfg->transWidth; - - DMA2D_Picture_Cfg_Type pictureCfg = { - .transWidth = cfg->transWidth, - .pixWidth = cfg->pixWidth, - .srcAddr = cfg->srcAddr, - .srcWidth = cfg->srcWidth, - .srcX0 = cfg->srcX0, - .srcY0 = cfg->srcY0, - .srcX1 = cfg->srcX1, - .srcY1 = cfg->srcY1, - .dstAddr = cfg->dstAddr, - .dstWidth = cfg->dstWidth, - .dstX0 = cfg->dstX0, - .dstY0 = cfg->dstY0, - }; - - if (cfg->srcX0 > cfg->srcX1 && cfg->srcY0 <= cfg->srcY1) { - pictureCfg.srcX0 = cfg->srcX1; - pictureCfg.srcX1 = cfg->srcX0; - } else if (cfg->srcX0 <= cfg->srcX1 && cfg->srcY0 > cfg->srcY1) { - pictureCfg.srcY0 = cfg->srcY1; - pictureCfg.srcY1 = cfg->srcY0; - } else if (cfg->srcX0 > cfg->srcX1 && cfg->srcY0 > cfg->srcY1) { - pictureCfg.srcX0 = cfg->srcX1; - pictureCfg.srcX1 = cfg->srcX0; - pictureCfg.srcY0 = cfg->srcY1; - pictureCfg.srcY1 = cfg->srcY0; - } - - lliCfg->srcDmaAddr = pictureCfg.srcAddr + pictureCfg.srcWidth * pictureCfg.pixWidth * pictureCfg.srcY0 + pictureCfg.pixWidth * pictureCfg.srcX0; - lliCfg->destDmaAddr = pictureCfg.dstAddr + pictureCfg.dstWidth * pictureCfg.pixWidth * pictureCfg.dstY0 + pictureCfg.pixWidth * pictureCfg.dstX0; - - lliCfg->dma2dCfg.srcCntX = (pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth / tmpVal; - lliCfg->dma2dCfg.srcIncrX = tmpVal; - lliCfg->dma2dCfg.srcCntY = pictureCfg.srcY1 - pictureCfg.srcY0; - lliCfg->dma2dCfg.srcIncrY = (pictureCfg.srcWidth - pictureCfg.srcX1 + pictureCfg.srcX0) * pictureCfg.pixWidth + tmpVal; - lliCfg->dma2dCfg.dstCntX = (pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth / tmpVal; - lliCfg->dma2dCfg.dstIncrX = pictureCfg.dstWidth * pictureCfg.pixWidth; - lliCfg->dma2dCfg.dstIncrY = -((pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth / tmpVal * pictureCfg.pixWidth * pictureCfg.dstWidth) + pictureCfg.pixWidth * pictureCfg.dstWidth - tmpVal; - - if (rotate == DMA2D_ROTATE_DEGREE_90) { - lliCfg->destDmaAddr += (pictureCfg.srcY1 - pictureCfg.srcY0 - 1) * tmpVal; - } else if (rotate == DMA2D_ROTATE_DEGREE_180) { - lliCfg->destDmaAddr += (pictureCfg.srcY1 - pictureCfg.srcY0) * tmpVal * pictureCfg.dstWidth + (pictureCfg.srcX1 - pictureCfg.srcX0 - 1) * tmpVal; - lliCfg->dma2dCfg.dstIncrX = -tmpVal; - lliCfg->dma2dCfg.dstIncrY = -pictureCfg.dstWidth * pictureCfg.pixWidth + (pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth - tmpVal; - } else if (rotate == DMA2D_ROTATE_DEGREE_270) { - lliCfg->destDmaAddr += (pictureCfg.srcX1 - pictureCfg.srcX0 - 1) * tmpVal * pictureCfg.dstWidth; - lliCfg->dma2dCfg.dstIncrX = -pictureCfg.dstWidth * pictureCfg.pixWidth; - lliCfg->dma2dCfg.dstIncrY = -lliCfg->dma2dCfg.dstIncrY; - } -} - -/****************************************************************************/ /** - * @brief DMA2D fold picture - * - * @param cfg: Pointer of DMA2D picture configure type - * @param lliCfg: Pointer of DMA2D LLI ctrl type - * @param fold: Fold direction type - * - * @return None - * -*******************************************************************************/ -void DMA2D_Picture_Fold_Calculate(DMA2D_Picture_Cfg_Type *cfg, DMA2D_LLI_Ctrl_Type *lliCfg, DMA2D_Fold_Type fold) -{ - uint32_t tmpVal = 1 << cfg->transWidth; - lliCfg->dmaCtrl.SRC_SIZE = cfg->transWidth; - lliCfg->dmaCtrl.DST_SIZE = cfg->transWidth; - - DMA2D_Picture_Cfg_Type pictureCfg = { - .transWidth = cfg->transWidth, - .pixWidth = cfg->pixWidth, - .srcAddr = cfg->srcAddr, - .srcWidth = cfg->srcWidth, - .srcX0 = cfg->srcX0, - .srcY0 = cfg->srcY0, - .srcX1 = cfg->srcX1, - .srcY1 = cfg->srcY1, - .dstAddr = cfg->dstAddr, - .dstWidth = cfg->dstWidth, - .dstX0 = cfg->dstX0, - .dstY0 = cfg->dstY0, - }; - - if (cfg->srcX0 > cfg->srcX1 && cfg->srcY0 <= cfg->srcY1) { - pictureCfg.srcX0 = cfg->srcX1; - pictureCfg.srcX1 = cfg->srcX0; - pictureCfg.dstAddr = pictureCfg.dstAddr - (pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth; - } else if (cfg->srcX0 <= cfg->srcX1 && cfg->srcY0 > cfg->srcY1) { - pictureCfg.srcY0 = cfg->srcY1; - pictureCfg.srcY1 = cfg->srcY0; - pictureCfg.dstAddr = pictureCfg.dstAddr - (pictureCfg.srcY1 - pictureCfg.srcY0) * pictureCfg.pixWidth * pictureCfg.srcWidth; - } else if (cfg->srcX0 > cfg->srcX1 && cfg->srcY0 > cfg->srcY1) { - pictureCfg.srcX0 = cfg->srcX1; - pictureCfg.srcX1 = cfg->srcX0; - pictureCfg.srcY0 = cfg->srcY1; - pictureCfg.srcY1 = cfg->srcY0; - pictureCfg.dstAddr = pictureCfg.dstAddr - (pictureCfg.srcY1 - pictureCfg.srcY0) * pictureCfg.pixWidth * pictureCfg.srcWidth - (pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth; - } - - lliCfg->srcDmaAddr = pictureCfg.srcAddr + pictureCfg.srcWidth * pictureCfg.pixWidth * pictureCfg.srcY0 + pictureCfg.pixWidth * pictureCfg.srcX0; - lliCfg->destDmaAddr = pictureCfg.dstAddr + pictureCfg.dstWidth * pictureCfg.pixWidth * pictureCfg.dstY0 + pictureCfg.pixWidth * pictureCfg.dstX0 + (pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth - tmpVal; - - lliCfg->dma2dCfg.srcCntX = (pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth / tmpVal; - lliCfg->dma2dCfg.srcIncrX = tmpVal; - lliCfg->dma2dCfg.srcCntY = pictureCfg.srcY1 - pictureCfg.srcY0; - lliCfg->dma2dCfg.srcIncrY = (pictureCfg.srcWidth - pictureCfg.srcX1 + pictureCfg.srcX0) * pictureCfg.pixWidth + tmpVal; - lliCfg->dma2dCfg.dstCntX = (pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth / tmpVal; - lliCfg->dma2dCfg.dstIncrX = -tmpVal; - lliCfg->dma2dCfg.dstIncrY = (pictureCfg.dstWidth + pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth - tmpVal; - - if (fold == DMA2D_FOLD_UP_DOWN) { - lliCfg->destDmaAddr = pictureCfg.dstAddr + pictureCfg.dstWidth * pictureCfg.pixWidth * pictureCfg.dstY0 + pictureCfg.pixWidth * pictureCfg.dstX0 + (pictureCfg.srcY1 - pictureCfg.srcY0 - 1) * pictureCfg.pixWidth * pictureCfg.dstWidth; - lliCfg->dma2dCfg.dstIncrX = tmpVal; - lliCfg->dma2dCfg.dstIncrY = -lliCfg->dma2dCfg.dstIncrY; - } -} - -/****************************************************************************/ /** - * @brief DMA2D fill picture - * - * @param cfg: Pointer of DMA2D picture configure type - * @param lliCfg: Pointer of DMA2D LLI ctrl type - * - * @return None - * -*******************************************************************************/ -void DMA2D_Picture_Fill_Calculate(DMA2D_Picture_Cfg_Type *cfg, DMA2D_LLI_Ctrl_Type *lliCfg) -{ - uint32_t tmpVal = 1 << cfg->transWidth; - lliCfg->dmaCtrl.SRC_SIZE = cfg->transWidth; - lliCfg->dmaCtrl.DST_SIZE = cfg->transWidth; - - DMA2D_Picture_Cfg_Type pictureCfg = { - .transWidth = cfg->transWidth, - .pixWidth = cfg->pixWidth, - .srcAddr = cfg->srcAddr, - .srcWidth = cfg->srcWidth, - .srcX0 = cfg->srcX0, - .srcY0 = cfg->srcY0, - .srcX1 = cfg->srcX1, - .srcY1 = cfg->srcY1, - .dstAddr = cfg->dstAddr, - .dstWidth = cfg->dstWidth, - .dstX0 = cfg->dstX0, - .dstY0 = cfg->dstY0, - }; - - if (cfg->srcX0 > cfg->srcX1 && cfg->srcY0 <= cfg->srcY1) { - pictureCfg.srcX0 = cfg->srcX1; - pictureCfg.srcX1 = cfg->srcX0; - pictureCfg.dstAddr = pictureCfg.dstAddr - (pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth; - } else if (cfg->srcX0 <= cfg->srcX1 && cfg->srcY0 > cfg->srcY1) { - pictureCfg.srcY0 = cfg->srcY1; - pictureCfg.srcY1 = cfg->srcY0; - pictureCfg.dstAddr = pictureCfg.dstAddr - (pictureCfg.srcY1 - pictureCfg.srcY0) * pictureCfg.pixWidth * pictureCfg.srcWidth; - } else if (cfg->srcX0 > cfg->srcX1 && cfg->srcY0 > cfg->srcY1) { - pictureCfg.srcX0 = cfg->srcX1; - pictureCfg.srcX1 = cfg->srcX0; - pictureCfg.srcY0 = cfg->srcY1; - pictureCfg.srcY1 = cfg->srcY0; - pictureCfg.dstAddr = pictureCfg.dstAddr - (pictureCfg.srcY1 - pictureCfg.srcY0) * pictureCfg.pixWidth * pictureCfg.srcWidth - (pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth; - } - - lliCfg->srcDmaAddr = pictureCfg.srcAddr; - lliCfg->destDmaAddr = pictureCfg.dstAddr + pictureCfg.dstWidth * pictureCfg.pixWidth * pictureCfg.dstY0 + pictureCfg.pixWidth * pictureCfg.dstX0; - - lliCfg->dma2dCfg.srcCntX = (pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth / tmpVal; - lliCfg->dma2dCfg.srcIncrX = 0; - lliCfg->dma2dCfg.srcCntY = pictureCfg.srcY1 - pictureCfg.srcY0; - lliCfg->dma2dCfg.srcIncrY = 0; - lliCfg->dma2dCfg.dstCntX = (pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth / tmpVal; - lliCfg->dma2dCfg.dstIncrX = tmpVal; - lliCfg->dma2dCfg.dstIncrY = (pictureCfg.dstWidth - pictureCfg.srcX1 + pictureCfg.srcX0) * pictureCfg.pixWidth + tmpVal; -} - -/****************************************************************************/ /** - * @brief DMA2D transfer start - * - * @param dmaId: DMA2D id - * @param ch: DMA2D channel - * @param lliCfg: Pointer of DMA2D LLI ctrl type - * - * @return None - * -*******************************************************************************/ -void DMA2D_Picture_Transfer_Start(DMA2D_ID_Type dmaId, uint8_t ch, DMA2D_LLI_Ctrl_Type *lliCfg) -{ - DMA2D_Channel_Cfg_Type chCfg = { - .srcDmaAddr = lliCfg->srcDmaAddr, - .destDmaAddr = lliCfg->destDmaAddr, - .transfLength = 0, - .dir = DMA2D_TRNS_M2M, - .ch = ch, - .srcTransfWidth = lliCfg->dmaCtrl.SRC_SIZE, - .dstTransfWidth = lliCfg->dmaCtrl.DST_SIZE, - .srcBurstSize = DMA2D_BURST_SIZE_16, - .dstBurstSize = DMA2D_BURST_SIZE_16, - .srcAddrInc = DMA2D_MINC_ENABLE, - .destAddrInc = DMA2D_MINC_ENABLE, - .srcPeriph = DMA2D_REQ_NONE, - .dstPeriph = DMA2D_REQ_NONE, - }; - - DMA2D_Channel_Disable(dmaId, ch); - DMA2D_Init(dmaId, ch, &lliCfg->dma2dCfg); - DMA2D_Channel_Init(dmaId, &chCfg); - DMA2D_Enable(dmaId); - DMA2D_Channel_Enable(dmaId, ch); -} - -/****************************************************************************/ /** - * @brief DMA2D color key mode configure - * - * @param dmaId: DMA2D id - * @param ch: DMA2D channel - * @param keyType: Color key type - * @param keyValue: Color key value - * - * @return None - * -*******************************************************************************/ -void DMA2D_Color_Key_Set(DMA2D_ID_Type dmaId, uint8_t ch, DMA2D_Color_Key_Type keyType, uint32_t keyValue) -{ - uint32_t tmpVal; - /* Get DMA2D register */ - uint32_t DMA2DChs = DMA2D_Get_Channel(dma2dAddr[dmaId], ch); - - /* Check the parameters */ - CHECK_PARAM(IS_DMA2D_COLOR_KEY_TYPE(keyType)); - - tmpVal = BL_RD_REG(DMA2DChs, DMA2D_C0_KEY_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_KEY_MODE, keyType); - switch(keyType) - { - case DMA2D_COLOR_KEY_8BIT: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_KEY_STRB, 0x1); - break; - case DMA2D_COLOR_KEY_16BIT: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_KEY_STRB, 0x3); - break; - case DMA2D_COLOR_KEY_24BIT: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_KEY_STRB, 0x7); - break; - case DMA2D_COLOR_KEY_32BIT: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_KEY_STRB, 0xf); - break; - default: - break; - } - BL_WR_REG(DMA2DChs, DMA2D_C0_KEY_EN, tmpVal); - - BL_WR_REG(DMA2DChs, DMA2D_C0_KEY, keyValue); -} - -/****************************************************************************/ /** - * @brief DMA2D color key mode enable - * - * @param dmaId: DMA2D id - * @param ch: DMA2D channel - * - * @return None - * -*******************************************************************************/ -void DMA2D_Color_Key_Enable(DMA2D_ID_Type dmaId, uint8_t ch) -{ - uint32_t tmpVal; - /* Get DMA2D register */ - uint32_t DMA2DChs = DMA2D_Get_Channel(dma2dAddr[dmaId], ch); - - /* Check the parameters */ - CHECK_PARAM(IS_DMA2D_COLOR_KEY_TYPE(keyType)); - - tmpVal = BL_RD_REG(DMA2DChs, DMA2D_C0_KEY_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, DMA2D_KEY_EN); - BL_WR_REG(DMA2DChs, DMA2D_C0_KEY_EN, tmpVal); -} - -/****************************************************************************/ /** - * @brief DMA2D color key mode disable - * - * @param dmaId: DMA2D id - * @param ch: DMA2D channel - * - * @return None - * -*******************************************************************************/ -void DMA2D_Color_Key_Disable(DMA2D_ID_Type dmaId, uint8_t ch) -{ - uint32_t tmpVal; - /* Get DMA2D register */ - uint32_t DMA2DChs = DMA2D_Get_Channel(dma2dAddr[dmaId], ch); - - tmpVal = BL_RD_REG(DMA2DChs, DMA2D_C0_KEY_EN); - BL_WR_REG(DMA2DChs, DMA2D_C0_KEY_EN, BL_CLR_REG_BIT(tmpVal, DMA2D_KEY_EN)); -} - -/*@} end of group DMA2D_Public_Functions */ - -/*@} end of group DMA2D */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsi.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsi.c deleted file mode 100644 index cc52e40294..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsi.c +++ /dev/null @@ -1,1500 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_dsi.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_dsi.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup DSI - * @{ - */ - -/** @defgroup DSI_Private_Macros - * @{ - */ -#define DSI_TX_TIMEOUT_COUNT (320 * 1000) - -/*@} end of group DSI_Private_Macros */ - -/** @defgroup DSI_Private_Types - * @{ - */ - -/*@} end of group DSI_Private_Types */ - -/** @defgroup DSI_Private_Variables - * @{ - */ - -static const uint32_t dsiAddr[DSI_ID_MAX] = { DSI_BASE }; - -/** - * @brief DSI interrupt callback function address array -*/ -#ifndef BFLB_USE_HAL_DRIVER -static intCallback_Type *DSIIntCbfArra[DSI_ID_MAX][DSI_INT_COUNT] = { - { NULL, NULL, NULL } -}; -#endif -/*@} end of group DSI_Private_Variables */ - -/** @defgroup DSI_Global_Variables - * @{ - */ - -/*@} end of group DSI_Global_Variables */ - -/** @defgroup DSI_Private_Fun_Declaration - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -static BL_Err_Type DSI_IntHandler(DSI_ID_Type dsiId); -#endif - -/*@} end of group DSI_Private_Fun_Declaration */ - -/** @defgroup DSI_Private_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief DSI interrupt handle - * - * @param None - * - * @return SUCCESS - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -static BL_Err_Type DSI_IntHandler(DSI_ID_Type dsiId) -{ - uint32_t maskVal; - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - - /* Check the parameters */ - CHECK_PARAM(IS_CAM_ID_TYPE(dsiId)); - - maskVal = BL_RD_REG(DSIx, DSI_INT_MASK); - tmpVal = BL_RD_REG(DSIx, DSI_INT_STATUS); - - if (tmpVal & DSI_INT_ESCAPE_TX_END && !(maskVal & DSI_INT_ESCAPE_TX_END)) { - DSI_IntClear(dsiId, DSI_INT_ESCAPE_TX_END); - - if (DSIIntCbfArra[dsiId][0] != NULL) { - /* call the callback function */ - DSIIntCbfArra[dsiId][0](); - } - } - - if (tmpVal & DSI_INT_LPDT_RX_END && !(maskVal & DSI_INT_LPDT_RX_END)) { - DSI_IntClear(dsiId, DSI_INT_LPDT_RX_END); - - if (DSIIntCbfArra[dsiId][1] != NULL) { - /* call the callback function */ - DSIIntCbfArra[dsiId][1](); - } - } - - if (tmpVal & DSI_INT_ULPS_RX_END && !(maskVal & DSI_INT_ULPS_RX_END)) { - DSI_IntClear(dsiId, DSI_INT_ULPS_RX_END); - - if (DSIIntCbfArra[dsiId][2] != NULL) { - /* call the callback function */ - DSIIntCbfArra[dsiId][2](); - } - } - - if (tmpVal & DSI_INT_TRIGGER0_RX_END && !(maskVal & DSI_INT_TRIGGER0_RX_END)) { - DSI_IntClear(dsiId, DSI_INT_TRIGGER0_RX_END); - - if (DSIIntCbfArra[dsiId][3] != NULL) { - /* call the callback function */ - DSIIntCbfArra[dsiId][3](); - } - } - - if (tmpVal & DSI_INT_TRIGGER1_RX_END && !(maskVal & DSI_INT_TRIGGER1_RX_END)) { - DSI_IntClear(dsiId, DSI_INT_TRIGGER1_RX_END); - - if (DSIIntCbfArra[dsiId][4] != NULL) { - /* call the callback function */ - DSIIntCbfArra[dsiId][4](); - } - } - - if (tmpVal & DSI_INT_TRIGGER2_RX_END && !(maskVal & DSI_INT_TRIGGER2_RX_END)) { - DSI_IntClear(dsiId, DSI_INT_TRIGGER2_RX_END); - - if (DSIIntCbfArra[dsiId][5] != NULL) { - /* call the callback function */ - DSIIntCbfArra[dsiId][5](); - } - } - - if (tmpVal & DSI_INT_TRIGGER3_RX_END && !(maskVal & DSI_INT_TRIGGER3_RX_END)) { - DSI_IntClear(dsiId, DSI_INT_TRIGGER3_RX_END); - - if (DSIIntCbfArra[dsiId][6] != NULL) { - /* call the callback function */ - DSIIntCbfArra[dsiId][6](); - } - } - - if (tmpVal & DSI_INT_TX_FIFO_READY && !(maskVal & DSI_INT_TX_FIFO_READY)) { - DSI_IntClear(dsiId, DSI_INT_TX_FIFO_READY); - - if (DSIIntCbfArra[dsiId][7] != NULL) { - /* call the callback function */ - DSIIntCbfArra[dsiId][7](); - } - } - - if (tmpVal & DSI_INT_RX_FIFO_READY && !(maskVal & DSI_INT_RX_FIFO_READY)) { - DSI_IntClear(dsiId, DSI_INT_RX_FIFO_READY); - - if (DSIIntCbfArra[dsiId][8] != NULL) { - /* call the callback function */ - DSIIntCbfArra[dsiId][8](); - } - } - - if (tmpVal & DSI_INT_DATA_OVERRUN_ERR && !(maskVal & DSI_INT_DATA_OVERRUN_ERR)) { - DSI_IntClear(dsiId, DSI_INT_DATA_OVERRUN_ERR); - - if (DSIIntCbfArra[dsiId][9] != NULL) { - /* call the callback function */ - DSIIntCbfArra[dsiId][9](); - } - } - - if (tmpVal & DSI_INT_DATA_UNDERRUN_ERR && !(maskVal & DSI_INT_DATA_UNDERRUN_ERR)) { - DSI_IntClear(dsiId, DSI_INT_DATA_UNDERRUN_ERR); - - if (DSIIntCbfArra[dsiId][10] != NULL) { - /* call the callback function */ - DSIIntCbfArra[dsiId][10](); - } - } - - if (tmpVal & DSI_INT_PIXEL_COUNT_SMALL_ERR && !(maskVal & DSI_INT_PIXEL_COUNT_SMALL_ERR)) { - DSI_IntClear(dsiId, DSI_INT_PIXEL_COUNT_SMALL_ERR); - - if (DSIIntCbfArra[dsiId][11] != NULL) { - /* call the callback function */ - DSIIntCbfArra[dsiId][11](); - } - } - - if (tmpVal & DSI_INT_PIXEL_COUNT_LARGE_ERR && !(maskVal & DSI_INT_PIXEL_COUNT_LARGE_ERR)) { - DSI_IntClear(dsiId, DSI_INT_PIXEL_COUNT_LARGE_ERR); - - if (DSIIntCbfArra[dsiId][12] != NULL) { - /* call the callback function */ - DSIIntCbfArra[dsiId][12](); - } - } - - if (tmpVal & DSI_INT_FIFO_ERROR && !(maskVal & DSI_INT_FIFO_ERROR)) { - DSI_IntClear(dsiId, DSI_INT_FIFO_ERROR); - - if (DSIIntCbfArra[dsiId][13] != NULL) { - /* call the callback function */ - DSIIntCbfArra[dsiId][13](); - } - } - - return SUCCESS; -} -#endif - -/*@} end of group DSI_Private_Functions */ - -/** @defgroup DSI_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief DSI module init - * - * @param dsiId: DSI ID type - * @param cfg: DSI configuration structure pointer - * - * @return None - * -*******************************************************************************/ -void DSI_Init(DSI_ID_Type dsiId, DSI_CFG_Type *cfg) -{ - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - DSI_Lane_Type lanes=0; - - /* Check the parameters */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - CHECK_PARAM(IS_DSI_DATA_TYPE(cfg->dataType)); - CHECK_PARAM(IS_DSI_LANE_NUMBER_TYPE(cfg->laneNum)); - CHECK_PARAM(IS_DSI_LANE_ORDER_TYPE(cfg->laneOrder)); - CHECK_PARAM(IS_DSI_HS_SYNC_TYPE(cfg->syncType)); - - /* Set DSI configuration */ - tmpVal = BL_RD_REG(DSIx, DSI_CONFIG); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_LANE_NUM, cfg->laneNum); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_HSTX_MODE, cfg->syncType); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_LANE_MUX_SEL, cfg->laneOrder); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_DT, cfg->dataType); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_VC, cfg->virtualChan); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_HSTX_VFP, cfg->vfp); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_HSTX_VSA, cfg->vsa); - - BL_WR_REG(DSIx, DSI_CONFIG, tmpVal); - - if(cfg->laneNum == DSI_LANE_NUMBER_1){ - lanes=DSI_LANE_CLOCK|DSI_LANE_DATA0; - }else if(cfg->laneNum == DSI_LANE_NUMBER_2){ - lanes=DSI_LANE_CLOCK|DSI_LANE_DATA0|DSI_LANE_DATA1; - }else if(cfg->laneNum == DSI_LANE_NUMBER_4){ - lanes=DSI_LANE_CLOCK|DSI_LANE_DATA0|DSI_LANE_DATA1|DSI_LANE_DATA2|DSI_LANE_DATA3; - } - - DSI_PHY_Enable_Lanes(dsiId,lanes); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(MIPI_DSI_IRQn, DSI_IRQHandler); -#endif -} - -/****************************************************************************/ /** - * @brief Deinit DSI module - * - * @param dsiId: DSI ID type - * - * @return None - * -*******************************************************************************/ -void DSI_Deinit(DSI_ID_Type dsiId) -{ -} - -/****************************************************************************/ /** - * @brief DSI Enable Disable Interrupt - * - * @param dsiId: DSI ID type - * @param intType: DSI Interrupt Type - * @param intMask: mask or unmask - * - * @return None - * -*******************************************************************************/ -void DSI_IntMask(DSI_ID_Type dsiId, DSI_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - CHECK_PARAM(IS_DSI_INT_TYPE(intType)); - CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); - - tmpVal = BL_RD_REG(DSIx, DSI_INT_MASK); - - if (intMask == UNMASK) { - /* Unmask this interrupt */ - tmpVal &= (~intType); - - } else { - /* Mask this interrupt */ - tmpVal |= intType; - } - - BL_WR_REG(DSIx, DSI_INT_MASK, tmpVal); -} - -/****************************************************************************/ /** - * @brief DSI Clear Interrupt - * - * @param dsiId: DSI ID type - * @param intType: DSI Interrupt Type - * - * @return None - * -*******************************************************************************/ -void DSI_IntClear(DSI_ID_Type dsiId, DSI_INT_Type intType) -{ - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - CHECK_PARAM(IS_DSI_INT_TYPE(intType)); - - tmpVal = BL_RD_REG(DSIx, DSI_INT_CLEAR); - - /* Clear this interrupt */ - tmpVal |= intType; - - BL_WR_REG(DSIx, DSI_INT_CLEAR, tmpVal); -} - -/****************************************************************************/ /** - * @brief DSI Enable Interrupt - * - * @param dsiId: DSI ID type - * @param intType: DSI Interrupt Type - * - * @return None - * -*******************************************************************************/ -void DSI_IntEnable(DSI_ID_Type dsiId, DSI_INT_Type intType) -{ - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - CHECK_PARAM(IS_DSI_INT_TYPE(intType)); - - tmpVal = BL_RD_REG(DSIx, DSI_INT_ENABLE); - - /* Enable this interrupt */ - tmpVal |= intType; - - BL_WR_REG(DSIx, DSI_INT_ENABLE, tmpVal); -} - -/****************************************************************************/ /** - * @brief DSI Get Interrupt status - * - * @param dsiId: DSI ID type - * - * @return None - * -*******************************************************************************/ -DSI_INT_Type DSI_IntGet(DSI_ID_Type dsiId) -{ - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - - tmpVal = BL_RD_REG(DSIx, DSI_INT_STATUS); - - return BL_GET_REG_BITS_VAL(tmpVal, DSI_INT_STATUS); -} - -/****************************************************************************/ /** - * @brief DSI set line buffer threshold for controller to start transmitting each line(unit:pixel) - * - * @param dsiId: DSI ID type - * @param frameWidth: frame width - * @param dvpTsrcClock: display(dp_dvp_tsrc) clock rate - * @param dsiClock: DSI bit clock rate - * @param dataType: DSI data type - * @param laneNumber: DSI lane number - * - * @return None - * -*******************************************************************************/ -void DSI_Set_Line_Buffer_Threshold(DSI_ID_Type dsiId, uint32_t frameWidth, uint32_t dvpTsrcClock, uint32_t dsiClock, \ - DSI_Data_Type dataType, DSI_Lane_Number_Type laneNumber) -{ - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - int64_t threshold = dvpTsrcClock; - uint32_t pixelByte; - - /* Check the parameters */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - CHECK_PARAM(IS_DSI_DATA_TYPE(dataType)); - CHECK_PARAM(IS_DSI_LANE_NUMBER_TYPE(laneNumber)); - - /* Frame Width should not exceed 1280 and should be a multiple of 4 */ - if(frameWidth > 1280 || frameWidth % 4){ - return; - } - - if(dataType < DSI_DATA_RGB666){ - pixelByte = 2; - }else{ - pixelByte = 3; - } - - threshold = frameWidth - threshold*frameWidth*pixelByte/(dsiClock/8)/(1<time_clk_zero); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_REG_TIME_CK_TRAIL, phyCfg->time_clk_trail); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_REG_TIME_CK_EXIT, phyCfg->time_clk_exit); - BL_WR_REG(DSIx, DSI_DPHY_CONFIG_1, tmpVal); - - tmpVal = BL_RD_REG(DSIx, DSI_DPHY_CONFIG_2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_REG_TIME_HS_ZERO, phyCfg->time_data_zero); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_REG_TIME_HS_TRAIL, phyCfg->time_data_trail); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_REG_TIME_HS_EXIT, phyCfg->time_data_exit); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_REG_TIME_HS_PREP, phyCfg->time_data_prepare); - BL_WR_REG(DSIx, DSI_DPHY_CONFIG_2, tmpVal); - - tmpVal = BL_RD_REG(DSIx, DSI_DPHY_CONFIG_3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_REG_TIME_TA_GO, phyCfg->time_ta_go); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_REG_TIME_TA_GET, phyCfg->time_ta_get); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_REG_TIME_REQRDY, phyCfg->time_req_ready); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_REG_TIME_LPX, phyCfg->time_lpx); - BL_WR_REG(DSIx, DSI_DPHY_CONFIG_3, tmpVal); - - tmpVal = BL_RD_REG(DSIx, DSI_DPHY_CONFIG_4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_REG_TIME_WAKEUP, phyCfg->time_wakeup); - BL_WR_REG(DSIx, DSI_DPHY_CONFIG_4, tmpVal); -} - -/****************************************************************************/ /** - * @brief DSI Reinit data lanes - * - * @param dsiId: DSI ID type - * - * @param lanes: lanes - * - * @return None - * -*******************************************************************************/ -void DSI_PHY_Reinit_Data_Lanes(DSI_ID_Type dsiId, DSI_Lane_Type lanes) -{ - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - CHECK_PARAM(IS_DSI_LANE_TYPE(lanes)); - - tmpVal = BL_RD_REG(DSIx, DSI_DPHY_CONFIG_0); - - tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_DL0_FORCERXMODE); - tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_DL1_FORCERXMODE); - tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_DL2_FORCERXMODE); - tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_DL3_FORCERXMODE); - BL_WR_REG(DSIx, DSI_DPHY_CONFIG_0, tmpVal); - - if (lanes & DSI_LANE_DATA0) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_DL0_FORCERXMODE); - } - - if (lanes & DSI_LANE_DATA1) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_DL1_FORCERXMODE); - } - - if (lanes & DSI_LANE_DATA2) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_DL2_FORCERXMODE); - } - - if (lanes & DSI_LANE_DATA3) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_DL3_FORCERXMODE); - } - - BL_WR_REG(DSIx, DSI_DPHY_CONFIG_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief DSI enable lanes - * - * @param dsiId: DSI ID type - * - * @param lanes: lanes - * - * @return None - * -*******************************************************************************/ -void DSI_PHY_Enable_Lanes(DSI_ID_Type dsiId, DSI_Lane_Type lanes) -{ - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - CHECK_PARAM(IS_DSI_LANE_TYPE(lanes)); - - tmpVal = BL_RD_REG(DSIx, DSI_DPHY_CONFIG_0); - - if (lanes & DSI_LANE_DATA0) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_DL0_ENABLE); - } - - if (lanes & DSI_LANE_DATA1) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_DL1_ENABLE); - } - - if (lanes & DSI_LANE_DATA2) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_DL2_ENABLE); - } - - if (lanes & DSI_LANE_DATA3) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_DL3_ENABLE); - } - - if (lanes & DSI_LANE_CLOCK) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_CL_ENABLE); - } - - BL_WR_REG(DSIx, DSI_DPHY_CONFIG_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief DSI disable lanes - * - * @param dsiId: DSI ID type - * - * @param lanes: lanes - * - * @return None - * -*******************************************************************************/ -void DSI_PHY_Disable_Lanes(DSI_ID_Type dsiId, DSI_Lane_Type lanes) -{ - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - CHECK_PARAM(IS_DSI_LANE_TYPE(lanes)); - - tmpVal = BL_RD_REG(DSIx, DSI_DPHY_CONFIG_0); - - if (lanes & DSI_LANE_DATA0) { - tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_DL0_ENABLE); - } - - if (lanes & DSI_LANE_DATA1) { - tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_DL1_ENABLE); - } - - if (lanes & DSI_LANE_DATA2) { - tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_DL2_ENABLE); - } - - if (lanes & DSI_LANE_DATA3) { - tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_DL3_ENABLE); - } - - if (lanes & DSI_LANE_CLOCK) { - tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_CL_ENABLE); - } - - BL_WR_REG(DSIx, DSI_DPHY_CONFIG_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief DSI stop data lanes - * - * @param dsiId: DSI ID type - * - * @param lanes: lanes - * - * @return None - * -*******************************************************************************/ -void DSI_PHY_Stop_Data_Lanes(DSI_ID_Type dsiId, DSI_Lane_Type lanes) -{ - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - CHECK_PARAM(IS_DSI_LANE_TYPE(lanes)); - - tmpVal = BL_RD_REG(DSIx, DSI_DPHY_CONFIG_0); - - tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_DL0_FORCETXSTOPMODE); - tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_DL1_FORCETXSTOPMODE); - tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_DL2_FORCETXSTOPMODE); - tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_DL3_FORCETXSTOPMODE); - BL_WR_REG(DSIx, DSI_DPHY_CONFIG_0, tmpVal); - - if (lanes & DSI_LANE_DATA0) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_DL0_FORCETXSTOPMODE); - } - - if (lanes & DSI_LANE_DATA1) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_DL1_FORCETXSTOPMODE); - } - - if (lanes & DSI_LANE_DATA2) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_DL2_FORCETXSTOPMODE); - } - - if (lanes & DSI_LANE_DATA3) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_DL3_FORCETXSTOPMODE); - } - - BL_WR_REG(DSIx, DSI_DPHY_CONFIG_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief DSI stop data lanes - * - * @param dsiId: DSI ID type - * - * @return None - * -*******************************************************************************/ -void DSI_PHY_Data_Lane0_TurnAround(DSI_ID_Type dsiId) -{ - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - - tmpVal = BL_RD_REG(DSIx, DSI_DPHY_CONFIG_0); - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_DL0_TURNESC); - BL_WR_REG(DSIx, DSI_DPHY_CONFIG_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief DSI get lanes state - * - * @param dsiId: DSI ID type - * - * @param lanes: lanes - * - * @return None - * -*******************************************************************************/ -void DSI_PHY_Get_Lanes_State(DSI_ID_Type dsiId, DSI_Lane_Type lane, DSI_Lane_State_Type *state) -{ - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - uint32_t stop_state_pos = 0; - uint32_t ulp_state_pos = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - CHECK_PARAM(IS_DSI_LANE_TYPE(lanes)); - - tmpVal = BL_RD_REG(DSIx, DSI_DPHY_CONFIG_0); - - *state = DSI_LANE_STAT_NORMAL; - - if (lane == DSI_LANE_DATA0) { - stop_state_pos = DSI_DL0_STOPSTATE_POS; - ulp_state_pos = DSI_DL0_ULPSACTIVENOT_POS; - } else if (lane == DSI_LANE_DATA1) { - stop_state_pos = DSI_DL1_STOPSTATE_POS; - ulp_state_pos = DSI_DL1_ULPSACTIVENOT_POS; - } else if (lane == DSI_LANE_DATA2) { - stop_state_pos = DSI_DL2_STOPSTATE_POS; - ulp_state_pos = DSI_DL2_ULPSACTIVENOT_POS; - } else if (lane == DSI_LANE_DATA3) { - stop_state_pos = DSI_DL3_STOPSTATE_POS; - ulp_state_pos = DSI_DL3_ULPSACTIVENOT_POS; - } else if (lane == DSI_LANE_CLOCK) { - stop_state_pos = DSI_CL_STOPSTATE_POS; - ulp_state_pos = DSI_CL_ULPSACTIVENOT_POS; - } else { - return; - } - - if(!(tmpVal & (1 << ulp_state_pos))) { - *state = DSI_LANE_STAT_ULP; - } else if(tmpVal & (1 << stop_state_pos)) { - *state = DSI_LANE_STAT_STOP; - } else { - if(lane == DSI_LANE_CLOCK) { - if(tmpVal & (1 << DSI_CL_TXREQUESTHS_POS)) { - *state = DSI_LANE_STAT_HS; - } else { - *state = DSI_LANE_STAT_BRIDGE; - } - } else { - if(BL_RD_REG(DSIx, DSI_CONFIG) & (1 << DSI_CR_HSTX_EN_POS)) { - *state = DSI_LANE_STAT_HS; - } else { - *state = DSI_LANE_STAT_BRIDGE; - } - } - } -} - -/****************************************************************************/ /** - * @brief Set clock lane operation - * - * @param dsiId: DSI ID type - * - * @param opt: operation type - * - * @return None - * -*******************************************************************************/ -void DSI_PHY_Set_Clock_Lane(DSI_ID_Type dsiId, DSI_Clock_Lane_Opt_Type opt) -{ - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - CHECK_PARAM(IS_DSI_CLOCK_LANE_OPT_TYPE(opt)); - - tmpVal = BL_RD_REG(DSIx, DSI_DPHY_CONFIG_0); - - if (opt & DSI_CLOCK_LANE_OPT_ULP_ENTER) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_CL_TXULPSCLK); - } - - if (opt & DSI_CLOCK_LANE_OPT_ULP_EXIT) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_CL_TXULPSEXIT); - BL_WR_REG(DSIx, DSI_DPHY_CONFIG_0, tmpVal); - arch_delay_ms(1); - tmpVal = BL_RD_REG(DSIx, DSI_DPHY_CONFIG_0); - tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_CL_TXULPSCLK); - } - - if (opt & DSI_CLOCK_LANE_OPT_HS_REQ) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_CL_TXREQUESTHS); - } - - if (opt & DSI_CLOCK_LANE_OPT_HS_EXIT) { - tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_CL_TXREQUESTHS); - } - - BL_WR_REG(DSIx, DSI_DPHY_CONFIG_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief Start HS Mode - * - * @param dsiId: DSI ID type - * - * @return None - * -*******************************************************************************/ -void DSI_PHY_HS_Mode_Start(DSI_ID_Type dsiId) -{ - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - DSI_Lane_State_Type state = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - - /* bring clock lane to high speed */ - DSI_PHY_Get_Lanes_State(dsiId, DSI_LANE_CLOCK, &state); - if(state == DSI_LANE_STAT_STOP){ - DSI_PHY_Set_Clock_Lane(dsiId, DSI_CLOCK_LANE_OPT_HS_REQ); - } - - /* bring data lane to high speed */ - DSI_PHY_Get_Lanes_State(dsiId, DSI_LANE_DATA0, &state); - if(state == DSI_LANE_STAT_STOP){ - tmpVal = BL_RD_REG(DSIx, DSI_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_CR_HSTX_EN); - BL_WR_REG(DSIx, DSI_CONFIG, tmpVal); - } - -} - -/****************************************************************************/ /** - * @brief Stop HS Mode - * - * @param dsiId: DSI ID type - * - * @return None - * -*******************************************************************************/ -void DSI_PHY_HS_Mode_Stop(DSI_ID_Type dsiId) -{ - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - DSI_Lane_State_Type state = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - - /* set data lane to stop mode */ - DSI_PHY_Get_Lanes_State(dsiId, DSI_LANE_DATA0, &state); - if(state != DSI_LANE_STAT_STOP){ - tmpVal = BL_RD_REG(DSIx, DSI_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_CR_HSTX_EN); - BL_WR_REG(DSIx, DSI_CONFIG, tmpVal); - do{ - DSI_PHY_Get_Lanes_State(dsiId, DSI_LANE_DATA0, &state); - }while(state != DSI_LANE_STAT_STOP); - } - - /* set clock lane to stop mode */ - DSI_PHY_Get_Lanes_State(dsiId, DSI_LANE_CLOCK, &state); - if(state != DSI_LANE_STAT_STOP){ - DSI_PHY_Set_Clock_Lane(dsiId, DSI_CLOCK_LANE_OPT_HS_EXIT); - do{ - DSI_PHY_Get_Lanes_State(dsiId, DSI_LANE_CLOCK, &state); - }while(state != DSI_LANE_STAT_STOP); - } - -} - -/****************************************************************************/ /** - * @brief DSI configure fifo function - * - * @param dsiId: DSI ID type - * - * @param fifoCfg: FIFO configuration structure pointer - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type DSI_FifoConfig(DSI_ID_Type dsiId, DSI_FifoCfg_Type *fifoCfg) -{ - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - - /* Deal with DSI fifo configure register */ - tmpVal = BL_RD_REG(DSIx, DSI_FIFO_CONFIG_1); - /* Configure dma tx fifo threshold */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_TX_FIFO_TH, fifoCfg->txFifoDmaThreshold); - /* Configure dma rx fifo threshold */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_RX_FIFO_TH, fifoCfg->rxFifoDmaThreshold); - /* Write back */ - BL_WR_REG(DSIx, DSI_FIFO_CONFIG_1, tmpVal); - - /* Enable or disable DSI fifo dma function */ - tmpVal = BL_RD_REG(DSIx, DSI_FIFO_CONFIG_0); - - if (ENABLE == fifoCfg->txFifoDmaEnable) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_DMA_TX_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_DMA_TX_EN); - } - - if (ENABLE == fifoCfg->rxFifoDmaEnable) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_DMA_RX_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_DMA_RX_EN); - } - - BL_WR_REG(DSIx, DSI_FIFO_CONFIG_0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief DSI start tx for short and long packet - * - * @param dsiId: DSI ID type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type DSI_LPDT_Start_Tx(DSI_ID_Type dsiId) -{ - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - - tmpVal = BL_RD_REG(DSIx, DSI_ESC_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_CR_ESC_RX_EN); - BL_WR_REG(DSIx, DSI_ESC_CONFIG, tmpVal); - - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_CR_ESC_TX_EN); - BL_WR_REG(DSIx, DSI_ESC_CONFIG, tmpVal); - - return SUCCESS; -} - -/****************************************************************************//** - * @brief DSI wait for send done - * - * @param dsiId: DSI ID type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type DSI_Wait_For_Esc_Tx_Done(DSI_ID_Type dsiId) -{ - DSI_INT_Type intStatus; - - /* wait for Tx finished */ - do{ - intStatus=DSI_IntGet(dsiId); - }while(!(intStatus&DSI_INT_ESCAPE_TX_END)); - DSI_IntClear(dsiId,DSI_INT_ESCAPE_TX_END); - - return SUCCESS; -} -/****************************************************************************/ /** - * @brief DSI start rx for short and long packet - * - * @param dsiId: DSI ID type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type DSI_LPDT_Start_Rx(DSI_ID_Type dsiId) -{ - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - - tmpVal = BL_RD_REG(DSIx, DSI_ESC_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_CR_ESC_RX_EN); - BL_WR_REG(DSIx, DSI_ESC_CONFIG, tmpVal); - - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_CR_ESC_RX_EN); - BL_WR_REG(DSIx, DSI_ESC_CONFIG, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief DSI Get Rx length - * - * @param dsiId: DSI ID type - * - * @return RX length - * -*******************************************************************************/ -uint16_t DSI_LPDT_Get_Rx_Length(DSI_ID_Type dsiId) -{ - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - - tmpVal = BL_RD_REG(DSIx, DSI_ESC_CONFIG); - return BL_GET_REG_BITS_VAL(tmpVal, DSI_ST_ESC_RX_LEN); -} - -/****************************************************************************/ /** - * @brief DSI Escape mode send trigger command - * - * @param dsiId: DSI ID type - * - * @param cmd: trigger command - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type DSI_Send_Trigger_Command(DSI_ID_Type dsiId, uint8_t cmd) -{ - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - - DSI_PHY_HS_Mode_Stop(dsiId); - - tmpVal = BL_RD_REG(DSIx, DSI_ESC_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_ESC_TX_MODE, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_ESC_TX_TRIG, cmd); - BL_WR_REG(DSIx, DSI_ESC_CONFIG, tmpVal); - - tmpVal = BL_RD_REG(DSIx, DSI_ESC_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_CR_ESC_TX_EN); - BL_WR_REG(DSIx, DSI_ESC_CONFIG, tmpVal); - - return DSI_Wait_For_Esc_Tx_Done(dsiId); -} - -/****************************************************************************/ /** - * @brief DSI Escape mode send ULPS command - * - * @param dsiId: DSI ID type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type DSI_Send_ULPS_Command(DSI_ID_Type dsiId) -{ - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - - DSI_PHY_HS_Mode_Stop(dsiId); - - tmpVal = BL_RD_REG(DSIx, DSI_ESC_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_ESC_TX_MODE, 2); - BL_WR_REG(DSIx, DSI_ESC_CONFIG, tmpVal); - - tmpVal = BL_RD_REG(DSIx, DSI_ESC_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_CR_ESC_TX_EN); - BL_WR_REG(DSIx, DSI_ESC_CONFIG, tmpVal); - - return DSI_Wait_For_Esc_Tx_Done(dsiId); -} - -/****************************************************************************/ /** - * @brief DSI exit ULPS - * - * @param dsiId: DSI ID type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type DSI_Exit_ULPS(DSI_ID_Type dsiId) -{ - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - //DSI_Lane_State_Type state; - - /* Check the parameters */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - - tmpVal = BL_RD_REG(DSIx, DSI_ESC_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_ESC_TX_ULPS_EXIT, 1); - BL_WR_REG(DSIx, DSI_ESC_CONFIG, tmpVal); - - arch_delay_ms(2); -#if 0 - DSI_PHY_HS_Mode_Stop(dsiId); - - do - { - DSI_PHY_Get_Lanes_State(dsiId, DSI_LANE_DATA0, &state); - } while(state != DSI_LANE_STAT_STOP); - -#endif - tmpVal = BL_RD_REG(DSIx, DSI_ESC_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_ESC_TX_MODE, 3); - BL_WR_REG(DSIx, DSI_ESC_CONFIG, tmpVal); - - tmpVal = BL_RD_REG(DSIx, DSI_ESC_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_CR_ESC_TX_EN); - BL_WR_REG(DSIx, DSI_ESC_CONFIG, tmpVal); - - return DSI_Wait_For_Esc_Tx_Done(dsiId); -} - -/****************************************************************************/ /** - * @brief DSI config LPDT short packet - * - * @param dsiId: DSI ID type - * - * @param msg: LPDT long message config - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type DSI_LPDT_Config_Short_Packet(DSI_ID_Type dsiId, DSI_LPDT_MSG_Type *msg) -{ - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - - DSI_PHY_HS_Mode_Stop(dsiId); - - tmpVal = BL_RD_REG(DSIx, DSI_ESC_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_ESC_TX_MODE, 0); - BL_WR_REG(DSIx, DSI_ESC_CONFIG, tmpVal); - - /*short packet*/ - tmpVal = BL_RD_REG(DSIx, DSI_LPDT_TX_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_LPDT_PDLEN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_LPDT_VC, msg->virtualChan); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_LPDT_DI, msg->dataType); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_LPDT_WORD0, msg->tx_buf[0]); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_LPDT_WORD1, msg->tx_buf[1]); - BL_WR_REG(DSIx, DSI_LPDT_TX_CONFIG, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief DSI send LPDT short packet - * - * @param dsiId: DSI ID type - * - * @param msg: DSI message config - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type DSI_LPDT_Send_Short_Packet(DSI_ID_Type dsiId, DSI_LPDT_MSG_Type *msg) -{ - DSI_LPDT_Config_Short_Packet(dsiId, msg); - - DSI_LPDT_Start_Tx(dsiId); - - return DSI_Wait_For_Esc_Tx_Done(dsiId); -} - -/****************************************************************************/ /** - * @brief DSI config LPDT long packet - * - * @param dsiId: DSI ID type - * - * @param msg: LPDT long message config - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type DSI_LPDT_Config_Long_Packet(DSI_ID_Type dsiId, DSI_LPDT_MSG_Type *msg) -{ - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - - DSI_PHY_HS_Mode_Stop(dsiId); - - tmpVal = BL_RD_REG(DSIx, DSI_ESC_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_ESC_TX_MODE, 0); - BL_WR_REG(DSIx, DSI_ESC_CONFIG, tmpVal); - - /*long packet*/ - tmpVal = BL_RD_REG(DSIx, DSI_LPDT_TX_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_LPDT_VC, msg->virtualChan); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_LPDT_DI, msg->dataType); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_LPDT_WORD0, msg->tx_len & 0xff); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_LPDT_WORD1, (msg->tx_len >> 8) & 0xff); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_LPDT_PDLEN, msg->tx_len); - BL_WR_REG(DSIx, DSI_LPDT_TX_CONFIG, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief DSI get tx fifo unoccupied count value - * - * @param dsiId: DSI ID type - * - * @return Tx fifo unoccupied count value - * -*******************************************************************************/ -uint8_t DSI_GetTxFifoCount(DSI_ID_Type dsiId) -{ - uint32_t DSIx = dsiAddr[dsiId]; - - /* Check the parameter */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - - return BL_GET_REG_BITS_VAL(BL_RD_REG(DSIx, DSI_FIFO_CONFIG_1), DSI_TX_FIFO_CNT); -} - -/****************************************************************************/ /** - * @brief DSI get rx fifo count value - * - * @param dsiId: DSI ID type - * - * @return Rx fifo count value - * -*******************************************************************************/ -uint8_t DSI_GetRxFifoCount(DSI_ID_Type dsiId) -{ - uint32_t DSIx = dsiAddr[dsiId]; - - /* Check the parameter */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - - return BL_GET_REG_BITS_VAL(BL_RD_REG(DSIx, DSI_FIFO_CONFIG_1), DSI_RX_FIFO_CNT); -} - -/****************************************************************************/ /** - * @brief DSI full fill FIFO - * - * @param dsiId: DSI ID type - * - * @param data: Data to send buffer - * - * @param len: Data length to send - * - * @return Data length filled - * -*******************************************************************************/ -uint8_t DSI_Full_Fill_FIFO(DSI_ID_Type dsiId, const uint8_t *data, uint16_t len) -{ - uint32_t DSIx = dsiAddr[dsiId]; - const uint8_t *pDataEnd = data + len; - uint8_t filled = 0; - - /* Check the parameter */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Send data */ - while (data < pDataEnd) { - if (DSI_GetTxFifoCount(dsiId) > 0) { - BL_WR_WORD(DSIx + DSI_FIFO_WDATA_OFFSET, BL_RDWD_FRM_BYTEP(data)); - data += 4; - filled += 4; - } else { - return filled; - } - } - - return filled; -} - -/****************************************************************************/ /** - * @brief DSI feed FIFO with data - * - * @param dsiId: DSI ID type - * - * @param data: Data to send buffer - * - * @param len: Data length to send - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type DSI_Feed_FIFO(DSI_ID_Type dsiId, const uint8_t *data, uint16_t len) -{ - uint32_t timeoutCnt = DSI_TX_TIMEOUT_COUNT; - uint32_t DSIx = dsiAddr[dsiId]; - const uint8_t *pDataEnd = data + len; - - /* Check the parameter */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Send data */ - while (data < pDataEnd) { - if (DSI_GetTxFifoCount(dsiId) > 0) { - BL_WR_WORD(DSIx + DSI_FIFO_WDATA_OFFSET, BL_RDWD_FRM_BYTEP(data)); - timeoutCnt = DSI_TX_TIMEOUT_COUNT; - data += 4; - } else { - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief DSI Read FIFO - * - * @param dsiId: DSI ID type - * - * @param data: Data to receive buffer - * - * @param len: Data length to receive - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type DSI_Read_FIFO(DSI_ID_Type dsiId, uint8_t *data, uint16_t len) -{ - uint32_t DSIx = dsiAddr[dsiId]; - uint8_t *pDataEnd = data + len; - - /* Check the parameter */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Receive data */ - while (data < pDataEnd && DSI_GetRxFifoCount(dsiId) > 0) { - BL_WRWD_TO_BYTEP(data, BL_RD_WORD(DSIx + DSI_FIFO_RDATA_OFFSET)); - data += 4; - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief DSI send LPDT long packet - * - * @param dsiId: DSI ID type - * - * @param msg: DSI message config - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type DSI_LPDT_Send_Long_Packet(DSI_ID_Type dsiId, DSI_LPDT_MSG_Type *msg) -{ - uint8_t filled = 0; - - DSI_LPDT_Config_Long_Packet(dsiId, msg); - - filled = DSI_Full_Fill_FIFO(dsiId, msg->tx_buf, msg->tx_len); - - DSI_LPDT_Start_Tx(dsiId); - - if (filled < msg->tx_len) { - DSI_Feed_FIFO(dsiId, msg->tx_buf + filled, msg->tx_len - filled); - } - - return DSI_Wait_For_Esc_Tx_Done(dsiId); -} - -/****************************************************************************/ /** - * @brief DSI receive packet - * - * @param dsiId: DSI ID type - * - * @param msg: DSI message config - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type DSI_LPDT_Recv_Packet(DSI_ID_Type dsiId, DSI_LPDT_MSG_Type *msg) -{ - DSI_Lane_State_Type state; - DSI_INT_Type intStatus; - - /* wait for bus stop */ - do { - DSI_PHY_Get_Lanes_State(dsiId, DSI_LANE_DATA0, &state); - } while (state != DSI_LANE_STAT_STOP); - - /* turn around */ - DSI_PHY_Data_Lane0_TurnAround(dsiId); - - /* start rx */ - DSI_LPDT_Start_Rx(dsiId); - - /* wait for rx finished */ - do { - intStatus = DSI_IntGet(dsiId); - } while (!(intStatus & DSI_INT_LPDT_RX_END)); - DSI_IntClear(dsiId,DSI_INT_LPDT_RX_END); - - msg->rx_len = DSI_LPDT_Get_Rx_Length(dsiId); - - DSI_Read_FIFO(dsiId, msg->rx_buf, msg->rx_len); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief DSI interrupt function - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void DSI_IRQHandler(void) -{ - DSI_IntHandler(DSI0_ID); -} -#endif - -/*@} end of group DSI_Public_Functions */ - -/*@} end of group DSI */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsp2.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsp2.c deleted file mode 100644 index f2f25f3783..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsp2.c +++ /dev/null @@ -1,2029 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_dsp2.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_dsp2.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup DSP2 - * @{ - */ - -/** @defgroup DSP2_Private_Macros - * @{ - */ -#define DSP2_PRINT_LOG 0 -#if DSP2_PRINT_LOG -#include "bflb_platform.h" -#endif - -/* To avoid divide-0 exception in code */ -#define DIV_0_TO_1(a) ((0 == (a)) ? 1 : (a)) - -#define DIV_ROUND(divident, divider) (((divident) + ((divider) >> 1)) / (divider)) - -#define SIGN_EXTEND(x, num_bits) ((((int)(x)) & ((1 << num_bits) - 1)) << (32 - num_bits) >> (32 - num_bits)) - -#define BL_SET_REG_BITS_VAL_2(val, bitname, bitval) \ - (((val)&bitname##_UMSK) | (((uint32_t)(bitval) << bitname##_POS) & bitname##_MSK)) - -#define AE_SRAM_BASE ((uint32_t)0x30019000) /*!< AE status SRAM base address */ -#define AWB_SRAM_BASE ((uint32_t)0x3001c000) /*!< AWB status SRAM base address */ - -#define DSP2_BLC_MAX 1023 -#define DSP2_BLC_MIN 0 - -#define DSP2_BNR_WEIGHT_MAX 64 -#define DSP2_BNR_WEIGHT_MIN 0 -#define DSP2_BNR_LPF_WEIGHT_MAX 16 -#define DSP2_BNR_LPF_WEIGHT_MIN 0 - -#define DSP2_GAIN_MAX 2047 -#define DSP2_GAIN_MIN 0 - -#define DSP2_CCM_MAX 2047 -#define DSP2_CCM_MIN -2048 - -#define DSP2_BRIGHTNESS_MAX 127 -#define DSP2_BRIGHTNESS_MIN -128 - -#define DSP2_CONTRAST_MAX 255 -#define DSP2_CONTRAST_MIN 0 - -#define DSP2_SATURATION_MAX 255 -#define DSP2_SATURATION_MIN 0 - -#define DSP2_NOISE_LEVEL_MAX 63 -#define DSP2_NOISE_LEVEL_MIN 0 - -#define DSP2_NOISE_THRESHOLD_MAX 127 -#define DSP2_NOISE_THRESHOLD_MIN 0 - -#define DSP2_NR_STRENGTH_MAX 15 -#define DSP2_NR_STRENGTH_MIN 0 - -#define DSP2_Edge_Enhance_LEVEL_MAX 127 -#define DSP2_Edge_Enhance_LEVEL_MIN 0 - -#define DSP2_Edge_Enhance_LIMIT_MAX 255 -#define DSP2_Edge_Enhance_LIMIT_MIN 0 - -#define DSP2_Edge_Enhance_HPF_MAX 8 -#define DSP2_Edge_Enhance_HPF_MIN 0 - -#define DSP2_DPC_TH_MAX 255 -#define DSP2_DPC_TH_MIN 0 - -#define DSP2_AE_ROI_START_X_RANGE_MAX 2047 -#define DSP2_AE_ROI_START_Y_RANGE_MAX 2047 -#define DSP2_AE_ROI_WIDTH_RANGE_MAX 2047 -#define DSP2_AE_ROI_WIDTH_RANGE_MIN 32 -#define DSP2_AE_ROI_HEIGHT_RANGE_MAX 2047 -#define DSP2_AE_ROI_HEIGHT_RANGE_MIN 2 - -#define DSP2_AE_GRID_WIDTH_RANGE_MAX 255 -#define DSP2_AE_GRID_WIDTH_RANGE_MIN 32 -#define DSP2_AE_GRID_HEIGHT_RANGE_MAX 255 -#define DSP2_AE_GRID_HEIGHT_RANGE_MIN 2 -#define DSP2_AE_GRID_NUM_X_RANGE_MAX 12 -#define DSP2_AE_GRID_NUM_X_RANGE_MIN 1 -#define DSP2_AE_GRID_NUM_Y_RANGE_MAX 8 -#define DSP2_AE_GRID_NUM_Y_RANGE_MIN 1 - -#define DSP2_AWB_ROI_START_X_RANGE_MAX 2047 -#define DSP2_AWB_ROI_START_Y_RANGE_MAX 2047 -#define DSP2_AWB_ROI_WIDTH_RANGE_MAX 2047 -#define DSP2_AWB_ROI_WIDTH_RANGE_MIN 32 -#define DSP2_AWB_ROI_HEIGHT_RANGE_MAX 2047 -#define DSP2_AWB_ROI_HEIGHT_RANGE_MIN 2 - -#define DSP2_AWB_GRID_WIDTH_RANGE_MAX 255 -#define DSP2_AWB_GRID_WIDTH_RANGE_MIN 32 -#define DSP2_AWB_GRID_HEIGHT_RANGE_MAX 255 -#define DSP2_AWB_GRID_HEIGHT_RANGE_MIN 2 -#define DSP2_AWB_GRID_NUM_X_RANGE_MAX 32 -#define DSP2_AWB_GRID_NUM_X_RANGE_MIN 1 -#define DSP2_AWB_GRID_NUM_Y_RANGE_MAX 32 -#define DSP2_AWB_GRID_NUM_Y_RANGE_MIN 1 - -#define DSP2_AWB_R_MAX_THR_RANGE_MAX 4095 -#define DSP2_AWB_R_MIN_THR_RANGE_MAX 4095 -#define DSP2_AWB_G_MAX_THR_RANGE_MAX 4095 -#define DSP2_AWB_G_MIN_THR_RANGE_MAX 4095 -#define DSP2_AWB_B_MAX_THR_RANGE_MAX 4095 -#define DSP2_AWB_B_MIN_THR_RANGE_MAX 4095 - -#define DSP2_LSC_OFFSET_MAX 127 -#define DSP2_LSC_OFFSET_MIN -128 - -#define DSP2_EE_DIR_SHPNSS_THRESH_MAX 127 -#define DSP2_EE_NO_DIR_SHPNSS_THRESH_MAX 127 -#define DSP2_EE_FLAT_REGION_THRESH_MAX 255 -#define DSP2_EE_TEXTURE_REGION_THRESH_MAX 511 -#define DSP2_EE_EDGE_REGION_THRESH_MAX 65535 - -#define DSP2_EE_STRENGTH_MAX 127 -#define DSP2_EE_NR_STRENGTH_MAX 255 - -#define DSP2_EE_LUMA_WEIGHT_MAX 1023 - -#define DSP2_AE_SRAM_BANK1 (AE_SRAM_BASE) /*!< 0x30019000 */ -#define DSP2_AE_SRAM_BANK2 (AE_SRAM_BASE + (768)) /*!< 0x30019300 */ - -#define DSP2_AWB_SRAM_BANK1 (AWB_SRAM_BASE) /*!< 0x3001c000 */ -#define DSP2_AWB_SRAM_BANK2 (AWB_SRAM_BASE + (1024 * 8)) /*!< 0x3001e000 */ - -#define DSP2_LSC_MAX_MAX 255 -#define DSP2_LSC_MAX_MIN 0 - -#define DSP2_ERROR_ADDR 0xffffffff - -/* For 16bits reg, high 8bits offset 1Byte is low 8bits */ -#define DSP2_REG_H_L_OFFSET 0X1 - -/* Read 16 bits data consits of high 8bits and low 8bits */ -#define BL_RD_16_H_L_REG(addr_h, addr_l) \ - ((BL_RD_BYTE(addr_h)) << 8) + (BL_RD_BYTE(addr_l)) - -#define DSP2_RD_16_H_L_REG(regname_h, regname_l) \ - ((BL_RD_BYTE_REG(DSP2_BASE, regname_h)) << 8) + (BL_RD_BYTE_REG(DSP2_BASE, regname_l)) - -#define IS_BLACK_WHITE_MODE(mode) (mode == BLACK_WHITE_MODE_ON) - -/*@} end of group DSP2_Private_Macros */ - -/** @defgroup DSP2_Private_Types - * @{ - */ -typedef enum { - DSP2_DPC_OFF = 0, - DSP2_DPC_FLY, -} DSP2_DPC_MODE_TYPE; - -typedef enum { - DSP2_HSYNC_INVERT_NORMAL = 0, - DSP2_HSYNC_INVERT_INVERT, -} DSP2_HSYNC_INVERT_TYPE; - -typedef enum { - DSP2_VSYNC_INVERT_NORMAL = 0, - DSP2_VSYNC_INVERT_INVERT, -} DSP2_VSYNC_INVERT_TYPE; - -typedef enum { - DSP2_HCNT_RST_RISING = 0, - DSP2_HCNT_RST_FALLING, -} DSP2_HCNT_RST_TYPE; - -typedef enum { - DSP2_VCNT_RST_RISING = 0, - DSP2_VCNT_RST_FALLING, -} DSP2_VCNT_RST_TYPE; - -typedef enum { - DSP2_VCNT_RST_REVERT_FALLING = 0, - DSP2_VCNT_RST_REVERT_RISING, -} DSP2_VCNT_RST_REVERT_TYPE; - -typedef enum { - DSP2_FHBLK_LINE_OFF = 0, - DSP2_FHBLK_LINE_ON = 1, -} DSP2_FHBLK_LINE_TYPE; - -/*@} end of group DSP2_Private_Types */ - -/** @defgroup DSP2_Private_Variables - * @{ - */ - -/*@} end of group DSP2_Private_Variables */ - -/** @defgroup DSP2_Global_Variables - * @{ - */ - -/*@} end of group DSP2_Global_Variables */ - -/** @defgroup DSP2_Private_Fun_Declaration - * @{ - */ - -/*@} end of group DSP2_Private_Fun_Declaration */ - -/** @defgroup DSP2_Private_Functions - * @{ - */ -static uint16_t DSP2_Calc_Total_Width(const DSP2_TG_Cfg_Type *config) -{ - // uint32_t pix_clk = config->pix_clk; - // uint32_t DSP2_clk = config->DSP2_clk; - // uint16_t sns_tot_width = config->total_width; - - return (uint16_t)((uint64_t)config->DSP2_clk / config->total_height / config->fps + 48) & 0xFFFE; - - /* the final total width must be even */ - - // return (uint16_t)((uint64_t)DSP2_clk/1125/25) & 0xFFFE; - // return (uint16_t)((uint64_t)sns_tot_width * DSP2_clk / pix_clk + 48) & 0xFFFE; //TODO: remove magic number -} - -static bool is_LSC_Coeff_Valid(const DSP2_LSC_COEF_S *lsc) -{ - int i; - - const int DSP2_LSC_COEF_LIMIT[LSC_COEF_NUM][2] = { - { -4194304, 4194303 }, /*!< A */ - { -4096, 4095 }, /*!< B */ - { 0, 255 }, /*!< C */ - { -4194304, 4194303 }, /*!< D */ - { -4096, 4095 }, /*!< E */ - { -4194304, 4194303 }, /*!< G */ - }; - - for (i = 0; i < LSC_COEF_NUM; ++i) { - if ((lsc->lsc_coef_r.coef[i]) < DSP2_LSC_COEF_LIMIT[i][0] || (lsc->lsc_coef_r.coef[i]) > DSP2_LSC_COEF_LIMIT[i][1]) { - return false; - } - - if ((lsc->lsc_coef_g.coef[i]) < DSP2_LSC_COEF_LIMIT[i][0] || (lsc->lsc_coef_g.coef[i]) > DSP2_LSC_COEF_LIMIT[i][1]) { - return false; - } - - if ((lsc->lsc_coef_b.coef[i]) < DSP2_LSC_COEF_LIMIT[i][0] || (lsc->lsc_coef_b.coef[i]) > DSP2_LSC_COEF_LIMIT[i][1]) { - return false; - } - } - - return true; -} - -static int DSP2_Calc_Clamp_Gain(int black_level) -{ - return DIV_ROUND(4095 * 4096, (4095 - black_level)); -} - -/*@} end of group DSP2_Private_Functions */ - -/** @defgroup DSP2_Public_Functions - * @{ - */ - -void DSP2_Init(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AE_COEFF); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_YSUM_COEFF_R_PRE, 77); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_YSUM_COEFF_G_PRE, 150); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_YSUM_COEFF_B_PRE, 29); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_AE_COEFF, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_DNR_B); - /* yuv output 16bit mode */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_OUT_FORMAT_W, 1); - /* YUYV order */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CBCR_SELECT_W, 1); - - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_DNR_B, tmpVal); - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AWB_SETTING); - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MIDDLE_BL_AWB_GAIN_SEL_W); - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MIDDLE_BL_DIGITAL_GAIN_SEL_W); - - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_AWB_SETTING, tmpVal); -} - -void DSP2_Set_TG_Cfg(const DSP2_TG_Cfg_Type *cfg) -{ - dsp2_tg_reg_t *dsp2_tg_reg = (dsp2_tg_reg_t *)DSP2_BASE; - - uint16_t act_start_pixel = 0; - uint16_t act_pixel_width = 0; - uint16_t act_start_line = 0; - uint16_t act_line_height = 0; - - uint16_t out_pixel_width = 0; - uint16_t out_line_height = 0; - - uint16_t out_start_pixel = 0; - uint16_t out_start_line = 0; - - /* TODO: crop the best window */ - if (DSP2_SYNC_MODE_INPUT_VBLANK_NO_TOGGLE == cfg->sync_mode_value) { - act_start_pixel = 0; /* hcount reset in rising edge, so H blanking is put after valid line */ - act_pixel_width = cfg->active_width; - act_start_line = 0; - act_line_height = cfg->active_height; - } else { - act_start_pixel = cfg->total_width - cfg->active_width; - act_pixel_width = cfg->active_width; - act_start_line = cfg->total_height - cfg->active_height; - act_line_height = cfg->active_height; - } - - out_pixel_width = cfg->out_width; - out_line_height = cfg->out_height; - - out_start_pixel = (act_pixel_width - out_pixel_width) / 2; - out_start_line = (act_line_height - out_line_height) / 2; - - /* further reduce frame latency by enabling act_vsync reset mode on vsync edge */ - dsp2_tg_reg->dvp_mode.BF.reg_act_vsync_rst_en_w = 1; - - /* set sync mode */ - dsp2_tg_reg->dvp_mode.BF.sync_mode_w = cfg->sync_mode_value; - dsp2_tg_reg->dvp_mode.BF.hsync_in_inv_w = DSP2_HSYNC_INVERT_NORMAL; - /* dvp_tsrc would do vsync invert so vsync pulse is always active low */ - dsp2_tg_reg->dvp_mode.BF.vsync_in_inv_w = DSP2_VSYNC_INVERT_NORMAL; - dsp2_tg_reg->dvp_mode.BF.fhblk_line_on_w = DSP2_FHBLK_LINE_OFF; - - /* note: if vsync invert, vcnt reset mode set 0, means falling - else if vsync not invert, vcont reset mode set 1, also means falling - this value will not open to user now. - */ - if (DSP2_SYNC_MODE_INPUT_VBLANK_NO_TOGGLE == cfg->sync_mode_value) { - /* hcnt reset in rising edge, so H blanking is put after valid line - vcnt reset mode must be 0, to make sure vcnt is reset to 4095 instead of 0. */ - dsp2_tg_reg->dvp_mode.BF.hcnt_rst_mode_w = DSP2_HCNT_RST_RISING; - dsp2_tg_reg->dvp_mode.BF.vcnt_rst_mode_w = DSP2_VCNT_RST_RISING; - } else { - dsp2_tg_reg->dvp_mode.BF.hcnt_rst_mode_w = DSP2_HCNT_RST_FALLING; - dsp2_tg_reg->dvp_mode.BF.vcnt_rst_mode_w = DSP2_HCNT_RST_FALLING; - } - - /* set total pixels and total lines */ - dsp2_tg_reg->total_pixels.BF.total_hpixels_w = - DSP2_Calc_Total_Width(cfg); - - dsp2_tg_reg->total_pixels.BF.total_vlines_w = cfg->total_height; - ; - - /* act start pixel, act pixel width */ - dsp2_tg_reg->act_pixels_1.BF.act_start_pixel_w = act_start_pixel; - dsp2_tg_reg->act_pixels_1.BF.act_pixel_width_w = act_pixel_width; - - /* act start line, act line height */ - dsp2_tg_reg->act_pixels_2.BF.act_start_line_w = act_start_line; - dsp2_tg_reg->act_pixels_2.BF.act_line_height_w = act_line_height; - - /* out start pixel, out pixel width */ - dsp2_tg_reg->fact_pixels_1.BF.fact_start_pixel_w = out_start_pixel; - dsp2_tg_reg->fact_pixels_1.BF.fact_pixel_width_w = out_pixel_width; - - /* out start line, out line height*/ - dsp2_tg_reg->fact_pixels_2.BF.fact_start_line_w = out_start_line; - - dsp2_tg_reg->fact_pixels_2.BF.fact_line_height_w = out_line_height; -} - -int DSP2_Get_Output_Window(BL_Img_Size_T *out_win) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_TG_FACT_PIXELS_1); - out_win->width = BL_GET_REG_BITS_VAL(tmpVal, DSP2_TG_FACT_PIXEL_WIDTH_W); - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_TG_FACT_PIXELS_2); - out_win->height = BL_GET_REG_BITS_VAL(tmpVal, DSP2_TG_FACT_LINE_HEIGHT_W); - - return 0; -} - -void DSP2_Set_Bayer_Pattern(const BAYER_PATTERN_E *pattern) -{ - dsp2_front_reg_t *dsp2_front_reg = (dsp2_front_reg_t *)DSP2_BASE; - - dsp2_front_reg->pattern_mode.BF.pattern_mode_w = 0; - - /* fix issue: bayer pattern highly sensitive to total width setting */ - dsp2_front_reg->pattern_mode.BF.reg_bl_lpid_sel_w = 1; - - if (*pattern == BAYER_PATTERN_BG) { - /* lid invert depends on the total height */ - dsp2_front_reg->pattern_mode.BF.pid_inv_rgb_pre = 1; - dsp2_front_reg->pattern_mode.BF.lid_inv_rgb_pre = 1; - } else if (*pattern == BAYER_PATTERN_RG) { - dsp2_front_reg->pattern_mode.BF.pid_inv_rgb_pre = 0; - dsp2_front_reg->pattern_mode.BF.lid_inv_rgb_pre = 0; - } else if (*pattern == BAYER_PATTERN_GR) { - dsp2_front_reg->pattern_mode.BF.pid_inv_rgb_pre = 1; - dsp2_front_reg->pattern_mode.BF.lid_inv_rgb_pre = 0; - } else if (*pattern == BAYER_PATTERN_GB) { - dsp2_front_reg->pattern_mode.BF.pid_inv_rgb_pre = 0; - dsp2_front_reg->pattern_mode.BF.lid_inv_rgb_pre = 1; - } else { -#if DSP2_PRINT_LOG - MSG("Error bayer pattern!\n"); -#endif - return; - } - - /* hack for CISTA sensor */ - //dsp2_front_reg->pattern_mode.BF.pid_inv_rgb_pre = 1; - //dsp2_front_reg->pattern_mode.BF.lid_inv_rgb_pre = 0; -} - -void DSP2_Set_AE_State(BL_Fun_Type state) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AE_GRID_SIZE); - - if (ENABLE == state) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MIDDLE_NEW_AE_STA_ENABLE_W); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_MIDDLE_NEW_AE_STA_ENABLE_W); - } - - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_AE_GRID_SIZE, tmpVal); -} - -void DSP2_Set_AE_Stats_Conf(const dsp2_ae_stats_conf_t *ae_stats_conf) -{ - uint32_t tmpVal; - - CHECK_PARAM_MAX(ae_stats_conf->roi_start_x, DSP2_AE_ROI_START_X_RANGE_MAX); - CHECK_PARAM_MAX(ae_stats_conf->roi_start_y, DSP2_AE_ROI_START_Y_RANGE_MAX); - CHECK_PARAM_RANGE(ae_stats_conf->roi_width, - DSP2_AE_ROI_WIDTH_RANGE_MIN, DSP2_AE_ROI_WIDTH_RANGE_MAX); - CHECK_PARAM_RANGE(ae_stats_conf->roi_height, - DSP2_AE_ROI_HEIGHT_RANGE_MIN, DSP2_AE_ROI_HEIGHT_RANGE_MAX); - CHECK_PARAM_MIN(ae_stats_conf->grid_width, DSP2_AE_GRID_WIDTH_RANGE_MIN); - CHECK_PARAM_MIN(ae_stats_conf->grid_height, DSP2_AE_GRID_HEIGHT_RANGE_MIN); - CHECK_PARAM_RANGE(ae_stats_conf->grid_num_x, - DSP2_AE_GRID_NUM_X_RANGE_MIN, DSP2_AE_GRID_NUM_X_RANGE_MAX); - CHECK_PARAM_RANGE(ae_stats_conf->grid_num_y, - DSP2_AE_GRID_NUM_Y_RANGE_MIN, DSP2_AE_GRID_NUM_Y_RANGE_MAX); - - /* special check */ - - /* AE ROI must be in the active image region */ - if ((ae_stats_conf->roi_start_x + ae_stats_conf->roi_width > ae_stats_conf->img_width) || - (ae_stats_conf->roi_start_y + ae_stats_conf->roi_height > ae_stats_conf->img_height)) { -#if DSP2_PRINT_LOG - MSG("AE ROI must be in the active image region!\r\n"); -#endif - } - - /* grid width/height must be even number */ - if ((ae_stats_conf->grid_width & 0x1) & (ae_stats_conf->grid_height & 0x1)) { -#if DSP2_PRINT_LOG - MSG("Grid width/height must be even number!\r\n"); -#endif - } - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AE_ROI_X); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_ROI_START_X_PRE, ae_stats_conf->roi_start_x); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_ROI_WIDTH_PRE, ae_stats_conf->roi_width); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_AE_ROI_X, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AE_ROI_Y); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_ROI_START_Y_PRE, ae_stats_conf->roi_start_y); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_ROI_HEIGHT_PRE, ae_stats_conf->roi_height); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_AE_ROI_Y, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AE_IMAGE_SIZE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_IMAGE_WIDTH_PRE, ae_stats_conf->img_width); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_IMAGE_HEIGHT_PRE, ae_stats_conf->img_height); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_AE_IMAGE_SIZE, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AE_GRID_SIZE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_GRID_WIDTH_PRE, ae_stats_conf->grid_width); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_GRID_HEIGHT_PRE, ae_stats_conf->grid_height); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_GRID_X_MAX_PRE, ae_stats_conf->grid_num_x); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_GRID_Y_MAX_PRE, ae_stats_conf->grid_num_y); - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MIDDLE_NEW_AE_STA_ENABLE_W); - /* AE occupies 2 bank of memory*/ - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MIDDLE_AE_SWITCH_BANK_EN_PRE); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_AE_GRID_SIZE, tmpVal); -} - -void DSP2_Get_AE_Stats_Conf(dsp2_ae_stats_conf_t *ae_stats_conf) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AE_ROI_X); - ae_stats_conf->roi_start_x = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_ROI_START_X_PRE); - ae_stats_conf->roi_width = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_ROI_WIDTH_PRE); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AE_ROI_Y); - ae_stats_conf->roi_start_y = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_ROI_START_Y_PRE); - ae_stats_conf->roi_height = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_ROI_HEIGHT_PRE); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AE_IMAGE_SIZE); - ae_stats_conf->img_width = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_IMAGE_WIDTH_PRE); - ae_stats_conf->img_height = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_IMAGE_HEIGHT_PRE); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AE_GRID_SIZE); - ae_stats_conf->grid_width = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_GRID_WIDTH_PRE); - ae_stats_conf->grid_height = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_GRID_HEIGHT_PRE); - ae_stats_conf->grid_width = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_GRID_X_MAX_PRE); - ae_stats_conf->grid_height = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_GRID_Y_MAX_PRE); -} - -int DSP2_Get_AE_Stats(int grid_num, uint32_t *data) -{ - uint32_t tmpVal; - uint32_t buf_idx; - uint32_t buf_addr; - uint32_t w_cnt_idx_start; - uint32_t w_cnt_idx_end; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AE_STATUS); - buf_idx = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_BLAE_BUF_IDX_R); - w_cnt_idx_start = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_BLAE_W_CNT_R); - - buf_addr = (0 == buf_idx) ? DSP2_AE_SRAM_BANK1 : DSP2_AE_SRAM_BANK2; - ARCH_MemCpy4(data, (uint32_t *)(uintptr_t)buf_addr, grid_num * 2); // two word per grid - - w_cnt_idx_end = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_BLAE_W_CNT_R); - - if (w_cnt_idx_start != w_cnt_idx_end) { -#if DSP2_PRINT_LOG - MSG("AE statistics overwrite!\n"); -#endif - return -1; - } - - return 0; -} - -void DSP2_Get_AE_Sum(int grid_idx, AE_GRID_DATA_TYPE_E data_type, uint32_t *data) -{ - dsp2_ae_sum_t *grid_array; - uint32_t tmpVal; - uint32_t buf_idx; - uint32_t buf_addr; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AE_STATUS); - buf_idx = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_BLAE_BUF_IDX_R); - - buf_addr = (0 == buf_idx) ? DSP2_AE_SRAM_BANK1 : DSP2_AE_SRAM_BANK2; - grid_array = (dsp2_ae_sum_t *)(uintptr_t)buf_addr; - *data = grid_array[grid_idx].y_sum; -} - -void DSP2_Set_AWB_State(BL_Fun_Type state) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AWB_SETTING); - - if (ENABLE == state) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MIDDLE_NEW_AWB_STA_ENABLE_W); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_MIDDLE_NEW_AWB_STA_ENABLE_W); - } - - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_AWB_SETTING, tmpVal); -} - -void DSP2_Set_AWB_Stats_Conf(const dsp2_awb_stats_conf_t *awb_stats_conf) -{ - dsp2_middle_reg_t *dsp2_middle_reg = (dsp2_middle_reg_t *)DSP2_BASE; - - CHECK_PARAM_MAX(awb_stats_conf->roi_start_x, DSP2_AWB_ROI_START_X_RANGE_MAX); - CHECK_PARAM_MAX(awb_stats_conf->roi_start_y, DSP2_AWB_ROI_START_Y_RANGE_MAX); - CHECK_PARAM_MAX(awb_stats_conf->roi_width, DSP2_AWB_ROI_WIDTH_RANGE_MAX); - CHECK_PARAM_MAX(awb_stats_conf->roi_height, DSP2_AWB_ROI_HEIGHT_RANGE_MAX); - CHECK_PARAM_MAX(awb_stats_conf->grid_num_x, DSP2_AWB_GRID_NUM_X_RANGE_MAX); - CHECK_PARAM_MAX(awb_stats_conf->grid_num_y, DSP2_AWB_GRID_NUM_Y_RANGE_MAX); - CHECK_PARAM_MAX(awb_stats_conf->r_max_thr, DSP2_AWB_R_MAX_THR_RANGE_MAX); - CHECK_PARAM_MAX(awb_stats_conf->r_min_thr, DSP2_AWB_R_MIN_THR_RANGE_MAX); - CHECK_PARAM_MAX(awb_stats_conf->g_max_thr, DSP2_AWB_G_MAX_THR_RANGE_MAX); - CHECK_PARAM_MAX(awb_stats_conf->g_min_thr, DSP2_AWB_G_MIN_THR_RANGE_MAX); - CHECK_PARAM_MAX(awb_stats_conf->b_max_thr, DSP2_AWB_B_MAX_THR_RANGE_MAX); - CHECK_PARAM_MAX(awb_stats_conf->b_min_thr, DSP2_AWB_B_MIN_THR_RANGE_MAX); - - CHECK_PARAM_MIN(awb_stats_conf->grid_width, DSP2_AWB_GRID_WIDTH_RANGE_MIN); - CHECK_PARAM_MIN(awb_stats_conf->grid_height, DSP2_AWB_GRID_HEIGHT_RANGE_MIN); - - /* special check */ - /* AWB ROI must be in the active image region */ - if ((awb_stats_conf->roi_start_x + awb_stats_conf->roi_width > awb_stats_conf->img_width) || - (awb_stats_conf->roi_start_y + awb_stats_conf->roi_height > awb_stats_conf->img_height)) { -#if DSP2_PRINT_LOG - MSG("AWB ROI must be in the active image region!\r\n"); -#endif - } - - /* grid width/height must be even number */ - if ((awb_stats_conf->grid_width & 0x1) & (awb_stats_conf->grid_height & 0x1)) { -#if DSP2_PRINT_LOG - MSG("Grid width/height must be even number!\r\n"); -#endif - } - - dsp2_middle_reg->awb_roi_x.BF.awb_roi_start_x_w = awb_stats_conf->roi_start_x; - dsp2_middle_reg->awb_roi_x.BF.awb_roi_width_w = awb_stats_conf->roi_width; - dsp2_middle_reg->awb_roi_y.BF.awb_roi_start_y_w = awb_stats_conf->roi_start_y; - dsp2_middle_reg->awb_roi_y.BF.awb_roi_height_w = awb_stats_conf->roi_height; - - dsp2_middle_reg->awb_image_size.BF.awb_image_width_w = awb_stats_conf->img_width; - dsp2_middle_reg->awb_image_size.BF.awb_image_height_w = awb_stats_conf->img_height; - - dsp2_middle_reg->awb_grid_size.BF.awb_grid_width_w = awb_stats_conf->grid_width; - dsp2_middle_reg->awb_grid_size.BF.awb_grid_height_w = awb_stats_conf->grid_height; - - dsp2_middle_reg->awb_grid_size.BF.awb_grid_x_max_w = awb_stats_conf->grid_num_x; - dsp2_middle_reg->awb_grid_size.BF.awb_grid_y_max_w = awb_stats_conf->grid_num_y; - - dsp2_middle_reg->awb_r_thre.BF.awb_r_max_thr_w = awb_stats_conf->r_max_thr; - dsp2_middle_reg->awb_r_thre.BF.awb_r_min_thr_w = awb_stats_conf->r_min_thr; - - dsp2_middle_reg->awb_g_thre.BF.awb_g_max_thr_w = awb_stats_conf->g_max_thr; - dsp2_middle_reg->awb_g_thre.BF.awb_g_min_thr_w = awb_stats_conf->g_min_thr; - - dsp2_middle_reg->awb_b_thre.BF.awb_b_max_thr_w = awb_stats_conf->b_max_thr; - dsp2_middle_reg->awb_b_thre.BF.awb_b_min_thr_w = awb_stats_conf->b_min_thr; - - dsp2_middle_reg->awb_setting.BF.new_awb_sta_enable_w = 1; - - /* AWB occupies 2 banks of memory */ - dsp2_middle_reg->awb_setting.BF.awb_switch_bank_en_w = 1; -} - -void DSP2_Get_AWB_Stats_Conf(dsp2_awb_stats_conf_t *awb_stats_conf) -{ - dsp2_middle_reg_t *dsp2_middle_reg = (dsp2_middle_reg_t *)DSP2_BASE; - - awb_stats_conf->roi_start_x = dsp2_middle_reg->awb_roi_x.BF.awb_roi_start_x_w; - awb_stats_conf->roi_start_y = dsp2_middle_reg->awb_roi_y.BF.awb_roi_start_y_w; - awb_stats_conf->roi_width = dsp2_middle_reg->awb_roi_x.BF.awb_roi_width_w; - awb_stats_conf->roi_height = dsp2_middle_reg->awb_roi_y.BF.awb_roi_height_w; - awb_stats_conf->img_width = dsp2_middle_reg->awb_image_size.BF.awb_image_width_w; - awb_stats_conf->img_height = dsp2_middle_reg->awb_image_size.BF.awb_image_height_w; - - awb_stats_conf->grid_width = dsp2_middle_reg->awb_grid_size.BF.awb_grid_width_w; - awb_stats_conf->grid_height = dsp2_middle_reg->awb_grid_size.BF.awb_grid_height_w; - - awb_stats_conf->grid_num_x = dsp2_middle_reg->awb_grid_size.BF.awb_grid_x_max_w; - awb_stats_conf->grid_num_y = dsp2_middle_reg->awb_grid_size.BF.awb_grid_y_max_w; -} - -int DSP2_Get_AWB_Stats(int grid_num, uint32_t *data) -{ - uint32_t tmpVal; - uint32_t buf_idx; - uint32_t buf_addr; - uint32_t w_cnt_idx_start; - uint32_t w_cnt_idx_end; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AWB_STA_DBG1); - buf_idx = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_BLAWB_BUF_IDX_R); - w_cnt_idx_start = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_BLAWB_W_CNT_R); - - buf_addr = (0 == buf_idx) ? DSP2_AWB_SRAM_BANK1 : DSP2_AWB_SRAM_BANK2; - ARCH_MemCpy4(data, (uint32_t *)(uintptr_t)buf_addr, grid_num * 2); // two word per grid - - w_cnt_idx_end = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_BLAWB_W_CNT_R); - - if (w_cnt_idx_start != w_cnt_idx_end) { -#if DSP2_PRINT_LOG - MSG("AWB statistics overwrite!\n"); -#endif - return -1; - } - - return 0; -} - -void DSP2_Get_AWB_Sum(int grid_idx, RGB_SUM_S *rgb_sum) -{ - uint32_t tmpVal; - uint32_t buf_idx; - uint32_t buf_addr; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AWB_STA_DBG1); - buf_idx = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_BLAWB_BUF_IDX_R); - - buf_addr = (0 == buf_idx) ? DSP2_AWB_SRAM_BANK1 : DSP2_AWB_SRAM_BANK2; - - // dsp2_middle_reg_t *dsp2_middle_reg = (dsp2_middle_reg_t*)DSP2_BASE; - dsp2_awb_sum_t *grid_array = (dsp2_awb_sum_t *)(uintptr_t)buf_addr; - - rgb_sum->r_sum = grid_array[grid_idx].r_sum; - rgb_sum->g_sum = grid_array[grid_idx].g_sum; - rgb_sum->b_sum = grid_array[grid_idx].b_sum; - - // *buf_idx = dsp2_middle_reg->awb_sta_dbg1.BF.blawb_buf_idx_r; -} - -void DSP2_Get_AWB_ValidGridNum(int *valid_grid_num) -{ - dsp2_middle_reg_t *dsp2_middle_reg = (dsp2_middle_reg_t *)DSP2_BASE; - - *valid_grid_num = dsp2_middle_reg->awb_setting.BF.grid_cnt_within_thre_r; -} - -void DSP2_Set_AWB_Gain(const DSP2_RGB_Gain_Type *rgb_gain) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AWB_RGR_GAIN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AWB_R_GAIN_PRE, rgb_gain->r_gain); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AWB_GR_GAIN_PRE, rgb_gain->g_gain); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_AWB_RGR_GAIN, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AWB_BGB_GAIN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AWB_B_GAIN_PRE, rgb_gain->b_gain); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AWB_GB_GAIN_PRE, rgb_gain->g_gain); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_AWB_BGB_GAIN, tmpVal); -} - -void DSP2_Get_AWB_Gain(DSP2_RGB_Gain_Type *rgb_gain) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AWB_RGR_GAIN); - - rgb_gain->r_gain = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AWB_R_GAIN_PRE); - rgb_gain->g_gain = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AWB_GR_GAIN_PRE); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AWB_BGB_GAIN); - rgb_gain->b_gain = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AWB_B_GAIN_PRE); -} - -void DSP2_Set_AWB2_State(BL_Fun_Type state) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_INT); - - if (ENABLE == state) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MIDDLE3_AWB2_STAT_EN_PRE); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_MIDDLE3_AWB2_STAT_EN_PRE); - } - - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_INT, tmpVal); -} - -void DSP2_Set_AWB2_Gain_State(BL_Fun_Type state) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_INT); - - if (ENABLE == state) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MIDDLE3_AWB2_GAIN_EN_PRE); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_MIDDLE3_AWB2_GAIN_EN_PRE); - } - - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_INT, tmpVal); -} - -int DSP2_Get_AWB2_Sum(dsp2_awb2_sum_t *sum) -{ - uint32_t tmpVal; - uint64_t tmpVal64; - uint32_t buf_idx; - uint32_t w_cnt_idx_start; - uint32_t w_cnt_idx_end; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_INT); - buf_idx = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_BUF_IDX_R); - w_cnt_idx_start = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_W_CNT_R); - - if (0 == buf_idx) { - sum->r_avg = BL_GET_REG_BITS_VAL(BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_R0), DSP2_MIDDLE3_AWB2_R_AVG0_R); - sum->g_avg = BL_GET_REG_BITS_VAL(BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_R0), DSP2_MIDDLE3_AWB2_G_AVG0_R); - sum->b_avg = BL_GET_REG_BITS_VAL(BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_R1), DSP2_MIDDLE3_AWB2_B_AVG0_R); - sum->white_ratio = BL_GET_REG_BITS_VAL(BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_R1), DSP2_MIDDLE3_AWB2_WHITE_RATIO0_R); - - tmpVal64 = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_R4); - tmpVal = BL_GET_REG_BITS_VAL(BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_R5), DSP2_MIDDLE3_AWB2_WHITER_SUML0_R); - sum->white_r_sum = (tmpVal64 << 9) + tmpVal; - - tmpVal64 = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_R7); - tmpVal = BL_GET_REG_BITS_VAL(BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_R8), DSP2_MIDDLE3_AWB2_WHITEG_SUML0_R); - sum->white_g_sum = (tmpVal64 << 9) + tmpVal; - - tmpVal64 = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_RA); - tmpVal = BL_GET_REG_BITS_VAL(BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_RB), DSP2_MIDDLE3_AWB2_WHITEB_SUML0_R); - sum->white_b_sum = (tmpVal64 << 9) + tmpVal; - } else { - sum->r_avg = BL_GET_REG_BITS_VAL(BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_R2), DSP2_MIDDLE3_AWB2_R_AVG1_R); - sum->g_avg = BL_GET_REG_BITS_VAL(BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_R2), DSP2_MIDDLE3_AWB2_G_AVG1_R); - sum->b_avg = BL_GET_REG_BITS_VAL(BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_R3), DSP2_MIDDLE3_AWB2_B_AVG1_R); - sum->white_ratio = BL_GET_REG_BITS_VAL(BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_R3), DSP2_MIDDLE3_AWB2_WHITE_RATIO1_R); - - tmpVal64 = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_R6); - tmpVal = BL_GET_REG_BITS_VAL(BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_R5), DSP2_MIDDLE3_AWB2_WHITER_SUML1_R); - sum->white_r_sum = (tmpVal64 << 9) + tmpVal; - - tmpVal64 = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_R9); - tmpVal = BL_GET_REG_BITS_VAL(BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_R8), DSP2_MIDDLE3_AWB2_WHITEG_SUML1_R); - sum->white_g_sum = (tmpVal64 << 9) + tmpVal; - - tmpVal64 = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_RC); - tmpVal = BL_GET_REG_BITS_VAL(BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_RB), DSP2_MIDDLE3_AWB2_WHITEB_SUML1_R); - sum->white_b_sum = (tmpVal64 << 9) + tmpVal; - } - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_INT); - w_cnt_idx_end = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_W_CNT_R); - - // TODO: chang the algo - if (w_cnt_idx_start != w_cnt_idx_end) { -#if DSP2_PRINT_LOG - MSG("w_cnt_idx_start %d, w_cnt_idx_end %d \r\n", w_cnt_idx_start, w_cnt_idx_end); - MSG("AWB2 statistics overwrite!\n"); -#endif - return -1; - } - - return 0; -} - -void DSP2_Set_AWB2_Gain(const DSP2_RGB_Gain_Type *rgb_gain) -{ - DSP2_Set_AWB_Gain(rgb_gain); - // uint32_t tmpVal; - - // tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_GAIN1); - // tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_RGAIN_PRE, rgb_gain->r_gain); - // BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_GAIN1, tmpVal); - - // tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_GAIN2); - // tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_GGAIN_PRE, rgb_gain->g_gain); - // tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_BGAIN_PRE, rgb_gain->b_gain); - // BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_GAIN2, tmpVal); -} - -void DSP2_Get_AWB2_Gain(DSP2_RGB_Gain_Type *rgb_gain) -{ - DSP2_Get_AWB_Gain(rgb_gain); - // uint32_t tmpVal; - - // tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_GAIN1); - // rgb_gain->r_gain = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_RGAIN_PRE); - - // tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_GAIN2); - // rgb_gain->g_gain = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_GGAIN_PRE); - // rgb_gain->b_gain = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_BGAIN_PRE); -} - -void DSP2_Set_AWB2_Stats_Conf(const dsp2_awb2_stats_conf_t *awb_stats_conf) -{ - uint32_t tmpVal; - - CHECK_PARAM_MAX(awb_stats_conf->stat_x_min, DSP2_AWB_ROI_START_X_RANGE_MAX); - CHECK_PARAM_MAX(awb_stats_conf->stat_x_max, DSP2_AWB_ROI_START_X_RANGE_MAX); - CHECK_PARAM_MAX(awb_stats_conf->stat_y_min, DSP2_AWB_ROI_START_Y_RANGE_MAX); - CHECK_PARAM_MAX(awb_stats_conf->stat_y_max, DSP2_AWB_ROI_START_Y_RANGE_MAX); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_XAXIS); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_X_MIN_PRE, awb_stats_conf->stat_x_min); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_X_MAX_PRE, awb_stats_conf->stat_x_max); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_XAXIS, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_YAXIS); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_Y_MIN_PRE, awb_stats_conf->stat_y_min); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_Y_MAX_PRE, awb_stats_conf->stat_y_max); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_YAXIS, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_PIXEL_NUM); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_PIXEL_NUM_PRE, awb_stats_conf->stat_pixel_num); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_PIXEL_NUM, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_GAIN0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_STAT_GGAIN_PRE, awb_stats_conf->stat_g_gain); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_STAT_RGAIN_PRE, awb_stats_conf->stat_r_gain); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_GAIN0, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_GAIN1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_STAT_BGAIN_PRE, awb_stats_conf->stat_b_gain); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_GAIN1, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_GAIN3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_VGAIN_PRE, awb_stats_conf->stat_v_gain); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_UGAIN_PRE, awb_stats_conf->stat_u_gain); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_GAIN3, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_L0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_YTH1_PRE, awb_stats_conf->y_th[1]); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_YTH2_PRE, awb_stats_conf->y_th[2]); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_YTH3_PRE, awb_stats_conf->y_th[3]); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_YTH4_PRE, awb_stats_conf->y_th[4]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_L0, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_L1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_YTH0_PRE, awb_stats_conf->y_th[0]); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_YWEIGHT2_PRE, awb_stats_conf->y_weight[2]); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_YWEIGHT3_PRE, awb_stats_conf->y_weight[3]); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_YWEIGHT4_PRE, awb_stats_conf->y_weight[4]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_L1, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_L2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_YWEIGHT0_PRE, awb_stats_conf->y_weight[0]); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_YWEIGHT1_PRE, awb_stats_conf->y_weight[1]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_YSLOPE4_PRE, awb_stats_conf->y_slope[4]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_L2, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_L3); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_YSLOPE3_PRE, awb_stats_conf->y_slope[3]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_YSLOPE2_PRE, awb_stats_conf->y_slope[2]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_L3, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_L4); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_YSLOPE1_PRE, awb_stats_conf->y_slope[1]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_YSLOPE0_PRE, awb_stats_conf->y_slope[0]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_L4, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_C0); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_UREG4_PRE, awb_stats_conf->u[4]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_UREG5_PRE, awb_stats_conf->u[5]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_UREG6_PRE, awb_stats_conf->u[6]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_UREG7_PRE, awb_stats_conf->u[7]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_C0, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_C1); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_UREG0_PRE, awb_stats_conf->u[0]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_UREG1_PRE, awb_stats_conf->u[1]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_UREG2_PRE, awb_stats_conf->u[2]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_UREG3_PRE, awb_stats_conf->u[3]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_C1, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_C2); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_VREG4_PRE, awb_stats_conf->v[4]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_VREG5_PRE, awb_stats_conf->v[5]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_VREG6_PRE, awb_stats_conf->v[6]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_VREG7_PRE, awb_stats_conf->v[7]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_C2, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_C3); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_UREG0_PRE, awb_stats_conf->v[0]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_UREG1_PRE, awb_stats_conf->v[1]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_UREG2_PRE, awb_stats_conf->v[2]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_UREG3_PRE, awb_stats_conf->v[3]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_C3, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_C4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_CTH4_PRE, awb_stats_conf->c_th[4]); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_CTH5_PRE, awb_stats_conf->c_th[5]); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_CTH6_PRE, awb_stats_conf->c_th[6]); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_CTH7_PRE, awb_stats_conf->c_th[7]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_C4, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_C5); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_CTH0_PRE, awb_stats_conf->c_th[0]); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_CTH1_PRE, awb_stats_conf->c_th[1]); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_CTH2_PRE, awb_stats_conf->c_th[2]); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_CTH3_PRE, awb_stats_conf->c_th[3]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_C5, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_C6); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_CSLOPE4_PRE, awb_stats_conf->c_slope[4]); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_CSLOPE5_PRE, awb_stats_conf->c_slope[5]); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_CSLOPE6_PRE, awb_stats_conf->c_slope[6]); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_CSLOPE7_PRE, awb_stats_conf->c_slope[7]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_C6, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_C7); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_CSLOPE0_PRE, awb_stats_conf->c_slope[0]); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_CSLOPE1_PRE, awb_stats_conf->c_slope[1]); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_CSLOPE2_PRE, awb_stats_conf->c_slope[2]); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_CSLOPE3_PRE, awb_stats_conf->c_slope[3]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_C7, tmpVal); -} - -void DSP2_Set_RB_Gain(const DSP2_RB_Gain_Type *rb_gain) -{ - DSP2_RGB_Gain_Type rgb_gain; - - rgb_gain.r_gain = rb_gain->r_gain; - rgb_gain.g_gain = 4096; - rgb_gain.b_gain = rb_gain->b_gain; - - DSP2_Set_AWB_Gain(&rgb_gain); -} - -int DSP2_Set_BLC(const DSP2_CLAMP_S *clamp) -{ - dsp2_front_reg_t *dsp2_front_reg = (dsp2_front_reg_t *)DSP2_BASE; - - CHECK_PARAM_RANGE(clamp->clamp_r, DSP2_BLC_MIN, DSP2_BLC_MAX); - CHECK_PARAM_RANGE(clamp->clamp_gr, DSP2_BLC_MIN, DSP2_BLC_MAX); - CHECK_PARAM_RANGE(clamp->clamp_gb, DSP2_BLC_MIN, DSP2_BLC_MAX); - CHECK_PARAM_RANGE(clamp->clamp_b, DSP2_BLC_MIN, DSP2_BLC_MAX); - - dsp2_front_reg->clamp_R_Gr.BF.clp_R_pre = clamp->clamp_r; - dsp2_front_reg->clamp_R_Gr.BF.clp_Gr_pre = clamp->clamp_gr; - dsp2_front_reg->clamp_B_Gb.BF.clp_Gb_pre = clamp->clamp_gb; - dsp2_front_reg->clamp_B_Gb.BF.clp_B_pre = clamp->clamp_b; - - dsp2_front_reg->gain_R_G.BF.rgain1_pre = 128; - dsp2_front_reg->gain_R_G.BF.ggain1_pre = 128; - dsp2_front_reg->gain_B.BF.bgain1_pre = 128; - - /* compensate back the lost dynamic range for bayer image */ - dsp2_front_reg->clp_rgr_gain.BF.clp_gain_en_pre = 1; - dsp2_front_reg->clp_rgr_gain.BF.clp_r_gain_pre = DSP2_Calc_Clamp_Gain(clamp->clamp_r); - dsp2_front_reg->clp_rgr_gain.BF.clp_gr_gain_pre = DSP2_Calc_Clamp_Gain(clamp->clamp_gr); - dsp2_front_reg->clp_bgb_gain.BF.clp_gb_gain_pre = DSP2_Calc_Clamp_Gain(clamp->clamp_gb); - dsp2_front_reg->clp_bgb_gain.BF.clp_b_gain_pre = DSP2_Calc_Clamp_Gain(clamp->clamp_b); - - return 0; -} - -int DSP2_Get_BLC(DSP2_CLAMP_S *clamp) -{ - dsp2_front_reg_t *dsp2_front_reg = (dsp2_front_reg_t *)DSP2_BASE; - - clamp->clamp_r = dsp2_front_reg->clamp_R_Gr.BF.clp_R_pre; - clamp->clamp_gr = dsp2_front_reg->clamp_R_Gr.BF.clp_Gr_pre; - clamp->clamp_gb = dsp2_front_reg->clamp_B_Gb.BF.clp_Gb_pre; - clamp->clamp_b = dsp2_front_reg->clamp_B_Gb.BF.clp_B_pre; - - return 0; -} - -void DSP2_Set_DPC_State(BL_Fun_Type state) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_DEFECT_SETTING); - - if (ENABLE == state) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_DEFECT_CORRECT_MODE_W, DSP2_DPC_FLY); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_DEFECT_CORRECT_MODE_W, DSP2_DPC_OFF); - } - - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_DEFECT_SETTING, tmpVal); -} - -void DSP2_Enable_DPC(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_DEFECT_SETTING); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_DEFECT_CORRECT_MODE_W, DSP2_DPC_FLY); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_DEFECT_SETTING, tmpVal); -} - -void DSP2_Disable_DPC(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_DEFECT_SETTING); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_DEFECT_CORRECT_MODE_W, DSP2_DPC_OFF); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_DEFECT_SETTING, tmpVal); -} - -int DSP2_Set_Defect_Correction_Enhance_Group(const DSP2_DPC_ENHANCE_GROUP_TYPE *value) -{ - int i; - dsp2_middle_reg_t *dsp2_middle_reg = (dsp2_middle_reg_t *)DSP2_BASE; - - for (i = 0; i < DSP2_DPC_Enhance_Num; i++) { - if ((DISABLE != value->data[i]) && (ENABLE != value->data[i])) { - return -1; - } - } - - dsp2_middle_reg->defect_setting.BF.resolution_enhance1_w = value->data[DSP2_DPC_Enhance1]; - dsp2_middle_reg->defect_setting.BF.resolution_enhance2_w = value->data[DSP2_DPC_Enhance2]; - dsp2_middle_reg->defect_setting.BF.resolution_enhance3_w = value->data[DSP2_DPC_Enhance3]; - - return 0; -} - -int DSP2_Get_Defect_Correction_Enhance_Group(DSP2_DPC_ENHANCE_GROUP_TYPE *value) -{ - dsp2_middle_reg_t *dsp2_middle_reg = (dsp2_middle_reg_t *)DSP2_BASE; - - value->data[DSP2_DPC_Enhance1] = (BL_Fun_Type)dsp2_middle_reg->defect_setting.BF.resolution_enhance1_w; - value->data[DSP2_DPC_Enhance2] = (BL_Fun_Type)dsp2_middle_reg->defect_setting.BF.resolution_enhance2_w; - value->data[DSP2_DPC_Enhance3] = (BL_Fun_Type)dsp2_middle_reg->defect_setting.BF.resolution_enhance3_w; - - return 0; -} - -int DSP2_Set_Defect_Correction_Threshold_Group(const DSP2_DPC_THRESHOLD_GROUP_TYPE *value) -{ - int i; - dsp2_middle_reg_t *dsp2_middle_reg = (dsp2_middle_reg_t *)DSP2_BASE; - - for (i = 0; i < DSP2_DPC_th_Num; i++) { - CHECK_PARAM_RANGE(value->data[i], DSP2_DPC_TH_MIN, DSP2_DPC_TH_MAX); - } - - dsp2_middle_reg->defect_th_A.BF.defect_th1_w = value->data[DSP2_DPC_th1]; - dsp2_middle_reg->defect_th_A.BF.defect_th2_w = value->data[DSP2_DPC_th2]; - dsp2_middle_reg->defect_th_A.BF.defect_th3_w = value->data[DSP2_DPC_th3]; - dsp2_middle_reg->defect_th_A.BF.defect_th4_w = value->data[DSP2_DPC_th4]; - dsp2_middle_reg->defect_th_B.BF.defect_th5_w = value->data[DSP2_DPC_th5]; - - return 0; -} - -int DSP2_Get_Defect_Correction_Threshold_Group(DSP2_DPC_THRESHOLD_GROUP_TYPE *value) -{ - dsp2_middle_reg_t *dsp2_middle_reg = (dsp2_middle_reg_t *)DSP2_BASE; - - value->data[DSP2_DPC_th1] = dsp2_middle_reg->defect_th_A.BF.defect_th1_w; - value->data[DSP2_DPC_th2] = dsp2_middle_reg->defect_th_A.BF.defect_th2_w; - value->data[DSP2_DPC_th3] = dsp2_middle_reg->defect_th_A.BF.defect_th3_w; - value->data[DSP2_DPC_th4] = dsp2_middle_reg->defect_th_A.BF.defect_th4_w; - value->data[DSP2_DPC_th5] = dsp2_middle_reg->defect_th_B.BF.defect_th5_w; - - return 0; -} - -void DSP2_Set_BNR_State(BL_Fun_Type state) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_0); - - if (ENABLE == state) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MIDDLE4_BNR_EN_PRE); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_MIDDLE4_BNR_EN_PRE); - } - - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_0, tmpVal); -} - -void DSP2_Get_BNR_State(BL_Fun_Type *state) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_0); - - if (BL_IS_REG_BIT_SET(tmpVal, DSP2_MIDDLE4_BNR_EN_PRE)) { - *state = ENABLE; - } else { - *state = DISABLE; - } -} - -/* - Set/Get BNR Weight - value range: 0~64 -*/ -void DSP2_Set_BNR_Weight(int value) -{ - uint32_t tmpVal; - - CHECK_PARAM_RANGE(value, DSP2_BNR_WEIGHT_MIN, DSP2_BNR_WEIGHT_MAX); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_BNR_WEIGHT_PRE, value); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_0, tmpVal); -} - -void DSP2_Get_BNR_Weight(int *value) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_0); - *value = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_BNR_WEIGHT_PRE); -} - -/* - Set/Get BNR LPF Weight - value range: 0~16 -*/ -void DSP2_Set_BNR_LPF_Weight(int value) -{ - uint32_t tmpVal; - - CHECK_PARAM_RANGE(value, DSP2_BNR_LPF_WEIGHT_MIN, DSP2_BNR_LPF_WEIGHT_MAX); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_LPF_WEIGHT_PRE, value); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_0, tmpVal); -} - -void DSP2_Get_BNR_LPF_Weight(int *value) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_0); - *value = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_LPF_WEIGHT_PRE); -} - -void DSP2_Set_BNR_Threshold(const DSP2_BNR_THRESHOLD_TYPE *value) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_TH_BASE_B_PRE, value->th_base_b); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_0, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_TH_BASE_G_PRE, value->th_base_g); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_TH_BASE_R_PRE, value->th_base_r); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_1, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_TH_SLOPE_B_PRE, value->th_slope_b); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_TH_SLOPE_G_PRE, value->th_slope_g); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_TH_SLOPE_R_PRE, value->th_slope_r); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_SLOPE_GAIN_PRE, value->slope_gain); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_2, tmpVal); -} - -void DSP2_Get_BNR_Threshold(DSP2_BNR_THRESHOLD_TYPE *value) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_0); - value->th_base_b = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_TH_BASE_B_PRE); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_1); - value->th_base_g = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_TH_BASE_G_PRE); - value->th_base_r = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_TH_BASE_R_PRE); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_2); - value->th_slope_b = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_TH_SLOPE_B_PRE); - value->th_slope_g = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_TH_SLOPE_G_PRE); - value->th_slope_r = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_TH_SLOPE_R_PRE); - value->slope_gain = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_SLOPE_GAIN_PRE); -} - -void DSP2_Set_BNR_Fallback(const DSP2_BNR_FALLBACK_TYPE *value) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_FB_LEVEL_PRE, value->fb_level); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_FB_LPF_WEIGHT_PRE, value->fb_lpf_weight); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_3, tmpVal); -} - -void DSP2_Get_BNR_Fallback(DSP2_BNR_FALLBACK_TYPE *value) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_3); - value->fb_lpf_weight = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_FB_LPF_WEIGHT_PRE); - value->fb_level = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_FB_LEVEL_PRE); -} - -void DSP2_Set_LSC_State(BL_Fun_Type state) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_SETTING); - - if (ENABLE == state) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MIDDLE_LSC_ON_W); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_MIDDLE_LSC_ON_W); - } - - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_LSC_SETTING, tmpVal); -} - -void DSP2_Enable_LSC(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_SETTING); - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MIDDLE_LSC_ON_W); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_LSC_SETTING, tmpVal); -} - -void DSP2_Disable_LSC(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_SETTING); - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_MIDDLE_LSC_ON_W); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_LSC_SETTING, tmpVal); -} - -void DSP2_Get_LSC_State(BL_Fun_Type *state) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_SETTING); - - if (BL_IS_REG_BIT_SET(tmpVal, DSP2_MIDDLE_LSC_ON_W)) { - *state = ENABLE; - } else { - *state = DISABLE; - } -} - -/* - xoffset and yoffset caculated by active and out window - */ -int DSP2_Set_LSC_Offset(int xoffset, int yoffset) -{ - dsp2_middle_reg_t *dsp2_middle_reg = (dsp2_middle_reg_t *)DSP2_BASE; - - CHECK_PARAM_RANGE(xoffset, DSP2_LSC_OFFSET_MIN, DSP2_LSC_OFFSET_MAX); - CHECK_PARAM_RANGE(yoffset, DSP2_LSC_OFFSET_MIN, DSP2_LSC_OFFSET_MAX); - - dsp2_middle_reg->LSC_setting.BF.X_offset_w = xoffset; - dsp2_middle_reg->LSC_setting.BF.Y_offset_w = yoffset; - - return 0; -} - -int DSP2_Set_LSC_Coeff(const DSP2_LSC_COEF_S *lsc) -{ - uint32_t tmpVal; - - if (!is_LSC_Coeff_Valid(lsc)) { - return -1; - } - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_R_A); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_R_ACOEFF_W, lsc->lsc_coef_r.coef[LSC_COEF_A]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_R_A, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_R_BE); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_R_BCOEFF_W, lsc->lsc_coef_r.coef[LSC_COEF_B]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_R_ECOEFF_W, lsc->lsc_coef_r.coef[LSC_COEF_E]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_R_BE, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_R_CD); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_R_CCOEFF_W, lsc->lsc_coef_r.coef[LSC_COEF_C]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_R_DCOEFF_W, lsc->lsc_coef_r.coef[LSC_COEF_D]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_R_CD, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_R_G); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_R_GCOEFF_W, lsc->lsc_coef_r.coef[LSC_COEF_G]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_R_G, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_G_A); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_G_ACOEFF_W, lsc->lsc_coef_g.coef[LSC_COEF_A]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_G_A, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_G_BE); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_G_BCOEFF_W, lsc->lsc_coef_g.coef[LSC_COEF_B]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_G_ECOEFF_W, lsc->lsc_coef_g.coef[LSC_COEF_E]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_G_BE, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_G_CD); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_G_CCOEFF_W, lsc->lsc_coef_g.coef[LSC_COEF_C]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_G_DCOEFF_W, lsc->lsc_coef_g.coef[LSC_COEF_D]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_G_CD, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_G_G); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_G_GCOEFF_W, lsc->lsc_coef_g.coef[LSC_COEF_G]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_G_G, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_B_A); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_B_ACOEFF_W, lsc->lsc_coef_b.coef[LSC_COEF_A]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_B_A, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_B_BE); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_B_BCOEFF_W, lsc->lsc_coef_b.coef[LSC_COEF_B]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_B_ECOEFF_W, lsc->lsc_coef_b.coef[LSC_COEF_E]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_B_BE, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_B_CD); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_B_CCOEFF_W, lsc->lsc_coef_b.coef[LSC_COEF_C]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_B_DCOEFF_W, lsc->lsc_coef_b.coef[LSC_COEF_D]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_B_CD, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_B_G); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_B_GCOEFF_W, lsc->lsc_coef_b.coef[LSC_COEF_G]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_B_G, tmpVal); - - return 0; -} - -int DSP2_Get_LSC_Coeff(DSP2_LSC_COEF_S *lsc) -{ - uint32_t tmpVal; - - /* channel R */ - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_R_A); - lsc->lsc_coef_r.coef[LSC_COEF_A] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_R_ACOEFF_W), 23); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_R_BE); - lsc->lsc_coef_r.coef[LSC_COEF_B] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_R_BCOEFF_W), 13); - lsc->lsc_coef_r.coef[LSC_COEF_E] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_R_ECOEFF_W), 13); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_R_CD); - lsc->lsc_coef_r.coef[LSC_COEF_C] = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_R_CCOEFF_W); - lsc->lsc_coef_r.coef[LSC_COEF_D] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_R_DCOEFF_W), 23); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_R_G); - lsc->lsc_coef_r.coef[LSC_COEF_G] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_R_GCOEFF_W), 23); - - /* channel G */ - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_G_A); - lsc->lsc_coef_g.coef[LSC_COEF_A] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_G_ACOEFF_W), 23); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_G_BE); - lsc->lsc_coef_g.coef[LSC_COEF_B] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_G_BCOEFF_W), 13); - lsc->lsc_coef_g.coef[LSC_COEF_E] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_G_ECOEFF_W), 13); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_G_CD); - lsc->lsc_coef_g.coef[LSC_COEF_C] = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_G_CCOEFF_W); - lsc->lsc_coef_g.coef[LSC_COEF_D] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_G_DCOEFF_W), 23); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_G_G); - lsc->lsc_coef_g.coef[LSC_COEF_G] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_G_GCOEFF_W), 23); - - /* channel B */ - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_B_A); - lsc->lsc_coef_b.coef[LSC_COEF_A] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_B_ACOEFF_W), 23); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_B_BE); - lsc->lsc_coef_b.coef[LSC_COEF_B] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_B_BCOEFF_W), 13); - lsc->lsc_coef_b.coef[LSC_COEF_E] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_B_ECOEFF_W), 13); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_B_CD); - lsc->lsc_coef_b.coef[LSC_COEF_C] = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_B_CCOEFF_W); - lsc->lsc_coef_b.coef[LSC_COEF_D] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_B_DCOEFF_W), 23); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_B_G); - lsc->lsc_coef_b.coef[LSC_COEF_G] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_B_GCOEFF_W), 23); - - return 0; -} - -int DSP2_Set_LSC_Max(const DSP2_LSC_MAX_S *lsc_max) -{ - dsp2_middle_reg_t *dsp2_middle_reg = (dsp2_middle_reg_t *)DSP2_BASE; - - CHECK_PARAM_RANGE(lsc_max->max_r, DSP2_LSC_MAX_MIN, DSP2_LSC_MAX_MAX); - CHECK_PARAM_RANGE(lsc_max->max_g, DSP2_LSC_MAX_MIN, DSP2_LSC_MAX_MAX); - CHECK_PARAM_RANGE(lsc_max->max_b, DSP2_LSC_MAX_MIN, DSP2_LSC_MAX_MAX); - - dsp2_middle_reg->MAX_R_G.BF.MAXR_w = lsc_max->max_r; - dsp2_middle_reg->MAX_R_G.BF.MAXG_w = lsc_max->max_g; - dsp2_middle_reg->MAX_B.BF.MAXB_w = lsc_max->max_b; - - return 0; -} - -int DSP2_Get_LSC_Max(DSP2_LSC_MAX_S *lsc_max) -{ - dsp2_middle_reg_t *dsp2_middle_reg = (dsp2_middle_reg_t *)DSP2_BASE; - - lsc_max->max_r = dsp2_middle_reg->MAX_R_G.BF.MAXR_w; - lsc_max->max_g = dsp2_middle_reg->MAX_R_G.BF.MAXG_w; - lsc_max->max_b = dsp2_middle_reg->MAX_B.BF.MAXB_w; - - return 0; -} - -void DSP2_Set_Digital_Gain(uint16_t dgain) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_DIGITAL_RGR_GAIN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_DIGITAL_GR_GAIN_PRE, dgain); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_DIGITAL_R_GAIN_PRE, dgain); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_DIGITAL_RGR_GAIN, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_DIGITAL_BGB_GAIN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_DIGITAL_GB_GAIN_PRE, dgain); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_DIGITAL_B_GAIN_PRE, dgain); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_DIGITAL_BGB_GAIN, tmpVal); -} - -void DSP2_Set_CCM_State(BL_Fun_Type state) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CC_OFFSET_0); - - if (ENABLE == state) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_BLBACK_CC_ENABLE_PRE); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_BLBACK_CC_ENABLE_PRE); - } - - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_CC_OFFSET_0, tmpVal); -} - -void DSP2_Get_CCM_State(BL_Fun_Type *state) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CC_OFFSET_0); - - if (BL_IS_REG_BIT_SET(tmpVal, DSP2_BLBACK_CC_ENABLE_PRE)) { - *state = ENABLE; - } else { - *state = DISABLE; - } -} - -void DSP2_Set_CCM_Coef(const DSP2_CCM_COEF_S *ccm) -{ - int i; - uint32_t tmpVal; - - for (i = 0; i < CCM_COEF_NUM; i++) { - CHECK_PARAM_RANGE(ccm->ccm_coef[i], DSP2_CCM_MIN, DSP2_CCM_MAX); - } - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CC_MATRIX_0); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CC_MATRIX00_PRE, ccm->ccm_coef[DSP2_CCM_11]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CC_MATRIX01_PRE, ccm->ccm_coef[DSP2_CCM_12]); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_CC_MATRIX_0, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CC_MATRIX_1); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CC_MATRIX02_PRE, ccm->ccm_coef[DSP2_CCM_13]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CC_MATRIX10_PRE, ccm->ccm_coef[DSP2_CCM_21]); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_CC_MATRIX_1, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CC_MATRIX_2); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CC_MATRIX11_PRE, ccm->ccm_coef[DSP2_CCM_22]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CC_MATRIX12_PRE, ccm->ccm_coef[DSP2_CCM_23]); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_CC_MATRIX_2, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CC_MATRIX_3); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CC_MATRIX20_PRE, ccm->ccm_coef[DSP2_CCM_31]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CC_MATRIX21_PRE, ccm->ccm_coef[DSP2_CCM_32]); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_CC_MATRIX_3, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CC_CE_MATRIX); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CC_MATRIX22_PRE, ccm->ccm_coef[DSP2_CCM_33]); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_CC_CE_MATRIX, tmpVal); -} - -void DSP2_Get_CCM_Coef(DSP2_CCM_COEF_S *ccm) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CC_MATRIX_0); - ccm->ccm_coef[DSP2_CCM_11] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CC_MATRIX00_PRE), DSP2_BLBACK_CC_MATRIX00_PRE_LEN); - ccm->ccm_coef[DSP2_CCM_12] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CC_MATRIX01_PRE), DSP2_BLBACK_CC_MATRIX01_PRE_LEN); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CC_MATRIX_1); - ccm->ccm_coef[DSP2_CCM_13] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CC_MATRIX02_PRE), DSP2_BLBACK_CC_MATRIX02_PRE_LEN); - ccm->ccm_coef[DSP2_CCM_21] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CC_MATRIX10_PRE), DSP2_BLBACK_CC_MATRIX10_PRE_LEN); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CC_MATRIX_2); - ccm->ccm_coef[DSP2_CCM_22] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CC_MATRIX11_PRE), DSP2_BLBACK_CC_MATRIX11_PRE_LEN); - ccm->ccm_coef[DSP2_CCM_23] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CC_MATRIX12_PRE), DSP2_BLBACK_CC_MATRIX12_PRE_LEN); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CC_MATRIX_3); - ccm->ccm_coef[DSP2_CCM_31] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CC_MATRIX20_PRE), DSP2_BLBACK_CC_MATRIX20_PRE_LEN); - ccm->ccm_coef[DSP2_CCM_32] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CC_MATRIX21_PRE), DSP2_BLBACK_CC_MATRIX21_PRE_LEN); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CC_CE_MATRIX); - ccm->ccm_coef[DSP2_CCM_33] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CC_MATRIX22_PRE), DSP2_BLBACK_CC_MATRIX22_PRE_LEN); -} - -void DSP2_Set_Gamma_State(BL_Fun_Type state) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_GAMMA_A); - - if (ENABLE == state) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_BLBACK_BL_GAMMA_EN_PRE); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_BLBACK_BL_GAMMA_EN_PRE); - } - - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_GAMMA_A, tmpVal); -} - -void DSP2_Get_Gamma_State(BL_Fun_Type *state) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_GAMMA_A); - - if (BL_IS_REG_BIT_SET(tmpVal, DSP2_BLBACK_BL_GAMMA_EN_PRE)) { - *state = ENABLE; - } else { - *state = DISABLE; - } -} - -void DSP2_Set_Gamma_Coef(const DSP2_Gamma_Curve_Type *gamma_curve) -{ - ARCH_MemCpy4((uint32_t *)(DSP2_BASE + DSP2_BLBACK_BL_GAMMA_TABLE_1_OFFSET), (uint32_t *)&gamma_curve->curve_coef[0], - GAMMA_COEF_NUM / 2); -} - -void DSP2_Get_Gamma_Coef(DSP2_Gamma_Curve_Type *gamma_curve) -{ - ARCH_MemCpy4((uint32_t *)&gamma_curve->curve_coef[0], (uint32_t *)(DSP2_BASE + DSP2_BLBACK_BL_GAMMA_TABLE_1_OFFSET), - GAMMA_COEF_NUM / 2); -} - -/* - should not change, yuv range should change in yuv adjust module -*/ -void DSP2_Init_Color_Enhancement() -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CE_MATRIX_0); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CE_MATRIX00_PRE, 0x99); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CE_MATRIX01_PRE, 0x12D); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_CE_MATRIX_0, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CC_CE_MATRIX); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CE_MATRIX02_PRE, 0x3A); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_CC_CE_MATRIX, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CE_MATRIX_1); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CE_MATRIX10_PRE, 0xFA9); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CE_MATRIX11_PRE, 0xF57); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_CE_MATRIX_1, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CE_MATRIX_2); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CE_MATRIX12_PRE, 0x100); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CE_MATRIX20_PRE, 0x100); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_CE_MATRIX_2, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CE_MATRIX_3); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CE_MATRIX21_PRE, 0xF29); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CE_MATRIX22_PRE, 0xFD7); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_CE_MATRIX_3, tmpVal); -} - -void DSP2_Set_YUV_Conv_Mode(DSP2_YUV_CONV_TYPE type) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_YUV_CONV_TYPE(type)); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CONV_MODE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CONV_MODE_W, type); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_CONV_MODE, tmpVal); -} - -void DSP2_Get_YUV_Conv_Mode(DSP2_YUV_CONV_TYPE *type) -{ - *type = BL_GET_REG_BITS_VAL(BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CONV_MODE), DSP2_BLBACK_CONV_MODE_W); -} - -void DSP2_Set_Brightness(int value) -{ - uint32_t tmpVal; - - CHECK_PARAM_RANGE(value, DSP2_BRIGHTNESS_MIN, DSP2_BRIGHTNESS_MAX); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_YUVC_A); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_YBRIGHTNESS_W, value); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_YUVC_A, tmpVal); -} - -void DSP2_Get_Brightness(int *value) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_YUVC_A); - *value = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_YBRIGHTNESS_W), DSP2_BLBACK_YBRIGHTNESS_W_LEN); -} - -void DSP2_Set_Contrast(int value) -{ - uint32_t tmpVal; - - CHECK_PARAM_RANGE(value, DSP2_CONTRAST_MIN, DSP2_CONTRAST_MAX); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_YUVC_A); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_YCONTRAST_W, value); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_YUVC_A, tmpVal); -} - -void DSP2_Get_Contrast(int *value) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_YUVC_A); - *value = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_YCONTRAST_W); -} - -void DSP2_Set_Saturation(const DSP2_SATURATION_S *saturation) -{ - uint32_t tmpVal; - - CHECK_PARAM_MAX(saturation->saturation_cb, DSP2_SATURATION_MAX); - CHECK_PARAM_MAX(saturation->saturation_cr, DSP2_SATURATION_MAX); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_YUVC_A); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CBSATURATION_PRE, saturation->saturation_cb); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CRSATURATION_PRE, saturation->saturation_cr); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_YUVC_A, tmpVal); -} - -void DSP2_Get_Saturation(DSP2_SATURATION_S *saturation) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_YUVC_A); - saturation->saturation_cb = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CBSATURATION_PRE); - saturation->saturation_cr = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CRSATURATION_PRE); -} - -void DSP2_Set_Noise_Level(int value) -{ - uint32_t tmpVal; - - CHECK_PARAM_RANGE(value, DSP2_NOISE_LEVEL_MIN, DSP2_NOISE_LEVEL_MAX); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_DNR_A); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_NOISE_LEVEL_PRE, value); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_DNR_A, tmpVal); -} - -void DSP2_Get_Noise_Level(int *value) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_DNR_A); - *value = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_NOISE_LEVEL_PRE); -} - -void DSP2_Set_2D_NR(int value) -{ - uint32_t tmpVal; - - CHECK_PARAM_RANGE(value, DSP2_NR_STRENGTH_MIN, DSP2_NR_STRENGTH_MAX); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_DNR_A); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_FILT_STRENGTH_2D_PRE, value); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_DNR_A, tmpVal); -} - -void DSP2_Get_2D_NR(int *value) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_DNR_A); - *value = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_FILT_STRENGTH_2D_PRE); -} - -void DSP2_Set_3D_NR(const int value) -{ - uint32_t tmpVal; - - CHECK_PARAM_RANGE(value, DSP2_NR_STRENGTH_MIN, DSP2_NR_STRENGTH_MAX); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_DNR_A); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_FILT_STRENGTH_3D_PRE, value); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_DNR_A, tmpVal); -} - -void DSP2_Get_3D_NR(int *value) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_DNR_A); - *value = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_FILT_STRENGTH_3D_PRE); -} - -void DSP2_Set_EE_State(BL_Fun_Type state) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_BLEE_0); - - if (ENABLE == state) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_BLBACK_EE_EB_PRE); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_BLBACK_EE_EB_PRE); - } - - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_BLEE_0, tmpVal); -} - -void DSP2_Enable_EE(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_BLEE_0); - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_BLBACK_EE_EB_PRE); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_BLEE_0, tmpVal); -} - -void DSP2_Disable_EE(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_BLEE_0); - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_BLBACK_EE_EB_PRE); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_BLEE_0, tmpVal); -} - -void DSP2_EnableEEOverShoot(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_BLEE_0); - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_BLBACK_OVRSHT_EB_PRE); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_BLEE_0, tmpVal); -} - -void DSP2_DisableEEOverShoot(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_BLEE_0); - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_BLBACK_OVRSHT_EB_PRE); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_BLEE_0, tmpVal); -} - -void DSP2_Set_EE_Thresh(const DSP2_EE_Thresh_Type *threshCfg) -{ - uint32_t tmpVal; - - CHECK_PARAM_MAX(threshCfg->dirShpnessThresh, DSP2_EE_DIR_SHPNSS_THRESH_MAX); - CHECK_PARAM_MAX(threshCfg->noDirShpnessThresh, DSP2_EE_NO_DIR_SHPNSS_THRESH_MAX); - CHECK_PARAM_RANGE(threshCfg->textureThresh, (threshCfg->flatThresh + 1), DSP2_EE_TEXTURE_REGION_THRESH_MAX); - CHECK_PARAM_MIN(threshCfg->edgeThresh, (threshCfg->textureThresh + 1)); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_BLEE_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_TXT_THR_PRE, threshCfg->textureThresh); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_BLEE_0, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_BLEE_1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_THRESH1_PRE, threshCfg->dirShpnessThresh); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_THRESH2_PRE, threshCfg->noDirShpnessThresh); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_FLAT_THR_PRE, threshCfg->flatThresh); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_BLEE_1, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_BLEE_3); - ; - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_EDGE_THR_PRE, threshCfg->edgeThresh); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_BLEE_3, tmpVal); -} - -void DSP2_Get_EE_Thresh(DSP2_EE_Thresh_Type *threshCfg) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_BLEE_0); - threshCfg->textureThresh = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_TXT_THR_PRE); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_BLEE_1); - threshCfg->dirShpnessThresh = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_THRESH1_PRE); - threshCfg->noDirShpnessThresh = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_THRESH2_PRE); - threshCfg->flatThresh = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_FLAT_THR_PRE); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_BLEE_3); - threshCfg->edgeThresh = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_EDGE_THR_PRE); -} - -void DSP2_Set_EE_Strength(const DSP2_EE_Str_Type *strCfg) -{ - uint32_t tmpVal; - - CHECK_PARAM_MAX(strCfg->posEdgeOvrshtStr, DSP2_EE_STRENGTH_MAX); - CHECK_PARAM_MAX(strCfg->negEdgeOvrshtStr, DSP2_EE_STRENGTH_MAX); - CHECK_PARAM_MAX(strCfg->posEdgeStr, DSP2_EE_STRENGTH_MAX); - CHECK_PARAM_MAX(strCfg->negEdgeStr, DSP2_EE_STRENGTH_MAX); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_BLEE_2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_OVRSHT_POS_PRE, strCfg->posEdgeOvrshtStr); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_OVRSHT_NEG_PRE, strCfg->negEdgeOvrshtStr); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_POSEE_STR_PRE, strCfg->posEdgeStr); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_NEGEE_STR_PRE, strCfg->negEdgeStr); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_BLEE_2, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_BLEE_3); - ; - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_NR_STR_PRE, strCfg->nrStr); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_BLEE_3, tmpVal); -} - -void DSP2_Get_EE_Strength(DSP2_EE_Str_Type *strCfg) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_BLEE_2); - strCfg->posEdgeOvrshtStr = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_OVRSHT_POS_PRE); - strCfg->negEdgeOvrshtStr = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_OVRSHT_NEG_PRE); - strCfg->posEdgeStr = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_POSEE_STR_PRE); - strCfg->negEdgeStr = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_NEGEE_STR_PRE); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_BLEE_3); - ; - strCfg->nrStr = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_NR_STR_PRE); -} - -void DSP2_Set_EE_LumaWeight(const DSP2_EE_Luma_Weight_Type *lumaWgtCfg) -{ - int i; - uint32_t tmpVal; - uint32_t tmpAddr = DSP2_BASE + DSP2_BLBACK_BLEE_4_OFFSET; - - for (i = 0; i < DSP2_EE_LUMA_WEIGHT_NUM; i += 2, tmpAddr += 4) { - CHECK_PARAM_MAX(lumaWgtCfg->lumaWgtTbl[i], DSP2_EE_LUMA_WEIGHT_MAX); - CHECK_PARAM_MAX(lumaWgtCfg->lumaWgtTbl[i + 1], DSP2_EE_LUMA_WEIGHT_MAX); - tmpVal = BL_RD_WORD(tmpAddr); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_LUMA_WGT0_PRE, lumaWgtCfg->lumaWgtTbl[i]); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_LUMA_WGT1_PRE, lumaWgtCfg->lumaWgtTbl[i + 1]); - BL_WR_WORD(tmpAddr, tmpVal); - } -} - -void DSP2_Get_EE_LumaWeight(DSP2_EE_Luma_Weight_Type *lumaWgtCfg) -{ - int i; - uint32_t tmpVal; - uint32_t tmpAddr = DSP2_BASE + DSP2_BLBACK_BLEE_4_OFFSET; - - for (i = 0; i < DSP2_EE_LUMA_WEIGHT_NUM; i += 2, tmpAddr += 4) { - tmpVal = BL_RD_WORD(tmpAddr); - lumaWgtCfg->lumaWgtTbl[i] = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_LUMA_WGT0_PRE); - lumaWgtCfg->lumaWgtTbl[i + 1] = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_LUMA_WGT1_PRE); - } -} - -void DSP2_Set_ChromaSuppress_State(BL_Fun_Type state) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CS2); - - if (ENABLE == state) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_BLBACK_CS2_ENABLE_PRE); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_BLBACK_CS2_ENABLE_PRE); - } - - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_CS2, tmpVal); -} - -void DSP2_Enable_ChromaSuppress(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CS2); - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_BLBACK_CS2_ENABLE_PRE); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_CS2, tmpVal); -} - -void DSP2_Disable_ChromaSuppress(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CS2); - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_BLBACK_CS2_ENABLE_PRE); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_CS2, tmpVal); -} - -void DSP2_Set_ChromaSuppress(const DSP2_Chroma_Suppress_Type *chromaSupprCfg) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CS2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CS2_GAIN_PRE, chromaSupprCfg->gain); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CS2_WEIGHT_PRE, chromaSupprCfg->weight); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CS2_GREY_TH_PRE, chromaSupprCfg->gain_thresh); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_CS2, tmpVal); -} - -void DSP2_Get_ChromaSuppress(DSP2_Chroma_Suppress_Type *chromaSupprCfg) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CS2); - chromaSupprCfg->gain = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CS2_GAIN_PRE); - chromaSupprCfg->weight = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CS2_WEIGHT_PRE); - chromaSupprCfg->gain_thresh = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CS2_GREY_TH_PRE); -} - -/*@} end of group DSP2_Public_Functions */ - -/*@} end of group DSP2 */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsp2_axi_ctrl.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsp2_axi_ctrl.c deleted file mode 100644 index 67b078763f..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsp2_axi_ctrl.c +++ /dev/null @@ -1,234 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_dsp2_axi_ctrl.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_dsp2_axi_ctrl.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup DSP2_AXI_CTRL - * @{ - */ - -/** @defgroup DSP2_AXI_CTRL_Private_Macros - * @{ - */ - -/*@} end of group DSP2_AXI_CTRL_Private_Macros */ - -/** @defgroup DSP2_AXI_CTRL_Private_Types - * @{ - */ - -/*@} end of group DSP2_AXI_CTRL_Private_Types */ - -/** @defgroup DSP2_AXI_CTRL_Private_Variables - * @{ - */ - -/*@} end of group DSP2_AXI_CTRL_Private_Variables */ - -/** @defgroup DSP2_AXI_CTRL_Global_Variables - * @{ - */ - -/*@} end of group DSP2_AXI_CTRL_Global_Variables */ - -/** @defgroup DSP2_AXI_CTRL_Private_Fun_Declaration - * @{ - */ - -/*@} end of group DSP2_AXI_CTRL_Private_Fun_Declaration */ - -/** @defgroup DSP2_AXI_CTRL_Private_Functions - * @{ - */ - -/*@} end of group DSP2_AXI_CTRL_Private_Functions */ - -/** @defgroup DSP2_AXI_CTRL_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief 3DNR init function - * - * @param dsp23DNRCfg: 3DNR configuration structure pointer - * - * @return None - * -*******************************************************************************/ -void DSP2_3DNR_Init(DSP2_3DNR_Cfg_Type *dsp23DNRCfg) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_3DNR_BURST_TYPE(dsp23DNRCfg->burst)); - - tmpVal = BL_RD_REG(AXI_CTRL_NR3D_BASE, DSP2_AXI_CTRL_NR_CONTROL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_AXI_CTRL_REG_XLEN, dsp23DNRCfg->burst); - BL_WR_REG(AXI_CTRL_NR3D_BASE, DSP2_AXI_CTRL_NR_CONTROL, tmpVal); - - BL_WR_REG(AXI_CTRL_NR3D_BASE, DSP2_AXI_CTRL_NR_HADDR_START_ADDRESS, dsp23DNRCfg->memStart); - - /*Set memory brust size */ - switch (dsp23DNRCfg->burst) { - case DSP2_3DNR_BURST_TYPE_SINGLE: - tmpVal = dsp23DNRCfg->memSize / 8; - break; - - case DSP2_3DNR_BURST_TYPE_INCR4: - tmpVal = dsp23DNRCfg->memSize / 32; - break; - - case DSP2_3DNR_BURST_TYPE_INCR8: - tmpVal = dsp23DNRCfg->memSize / 64; - break; - - case DSP2_3DNR_BURST_TYPE_INCR16: - tmpVal = dsp23DNRCfg->memSize / 128; - break; - - case DSP2_3DNR_BURST_TYPE_INCR32: - tmpVal = dsp23DNRCfg->memSize / 256; - break; - - case DSP2_3DNR_BURST_TYPE_INCR64: - tmpVal = dsp23DNRCfg->memSize / 512; - break; - - default: - tmpVal = 0; - break; - } - - BL_WR_REG(AXI_CTRL_NR3D_BASE, DSP2_AXI_CTRL_NR_MEMORY_BURST_COUNT, tmpVal); - - BL_WR_REG(AXI_CTRL_NR3D_BASE, DSP2_AXI_CTRL_NR_HSYNC_CONTROL, dsp23DNRCfg->hsyncStart << 16 | dsp23DNRCfg->hsyncEnd); - BL_WR_REG(AXI_CTRL_NR3D_BASE, DSP2_AXI_CTRL_NR_VSYNC_CONTROL, dsp23DNRCfg->vsyncStart << 16 | dsp23DNRCfg->vsyncEnd); -} - -/****************************************************************************/ /** - * @brief 3DNR enable function - * - * @param None - * - * @return None - * -*******************************************************************************/ -void DSP2_3DNR_Enable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(AXI_CTRL_NR3D_BASE, DSP2_AXI_CTRL_NR_CONTROL); - BL_WR_REG(AXI_CTRL_NR3D_BASE, DSP2_AXI_CTRL_NR_CONTROL, BL_SET_REG_BIT(tmpVal, DSP2_AXI_CTRL_REG_ENABLE)); -} - -/****************************************************************************/ /** - * @brief 3DNR disable function - * - * @param None - * - * @return None - * -*******************************************************************************/ -void DSP2_3DNR_Disable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(AXI_CTRL_NR3D_BASE, DSP2_AXI_CTRL_NR_CONTROL); - BL_WR_REG(AXI_CTRL_NR3D_BASE, DSP2_AXI_CTRL_NR_CONTROL, BL_CLR_REG_BIT(tmpVal, DSP2_AXI_CTRL_REG_ENABLE)); -} - -/****************************************************************************/ /** - * @brief 3DNR clear write fifo overflow error function - * - * @param None - * - * @return None - * -*******************************************************************************/ -void DSP2_3DNR_Clear_Write_Overflow(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(AXI_CTRL_NR3D_BASE, DSP2_AXI_CTRL_NR_CONTROL); - BL_WR_REG(AXI_CTRL_NR3D_BASE, DSP2_AXI_CTRL_NR_CONTROL, BL_SET_REG_BIT(tmpVal, DSP2_AXI_CTRL_REG_OVERFLOW_CLR)); -} - -/****************************************************************************/ /** - * @brief 3DNR clear read fifo drain error function - * - * @param None - * - * @return None - * -*******************************************************************************/ -void DSP2_3DNR_Clear_Read_Drain(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(AXI_CTRL_NR3D_BASE, DSP2_AXI_CTRL_NR_CONTROL); - BL_WR_REG(AXI_CTRL_NR3D_BASE, DSP2_AXI_CTRL_NR_CONTROL, BL_SET_REG_BIT(tmpVal, DSP2_AXI_CTRL_REG_DRAIN_CLR)); -} - -/****************************************************************************/ /** - * @brief 3DNR get write and read status function - * - * @param dsp23DNRStatus: 3DNR write and read status type - * - * @return Set or reset - * -*******************************************************************************/ -BL_Sts_Type DSP2_3DNR_Get_status(DSP2_3DNR_Status_Type dsp23DNRStatus) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(AXI_CTRL_NR3D_BASE, DSP2_AXI_CTRL_NR_STATUS); - - if (tmpVal & 1 << dsp23DNRStatus) { - return SET; - } else { - return RESET; - } -} - -/*@} end of group DSP2_AXI_CTRL_Public_Functions */ - -/*@} end of group DSP2_AXI_CTRL */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsp2_misc.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsp2_misc.c deleted file mode 100644 index 33e2690c2a..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsp2_misc.c +++ /dev/null @@ -1,1575 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_dsp2_misc.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_dsp2_misc.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup DSP2_MISC - * @{ - */ - -/** @defgroup DSP2_MISC_Private_Macros - * @{ - */ - -/*@} end of group DSP2_MISC_Private_Macros */ - -/** @defgroup DSP2_MISC_Private_Types - * @{ - */ - -/*@} end of group DSP2_MISC_Private_Types */ - -/** @defgroup DSP2_MISC_Private_Variables - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -static intCallback_Type *dsp2MiscIntCbfArra[DSP2_MISC_INT_ALL] = { - NULL -}; -#endif - -/*@} end of group DSP2_MISC_Private_Variables */ - -/** @defgroup DSP2_MISC_Global_Variables - * @{ - */ - -/*@} end of group DSP2_MISC_Global_Variables */ - -/** @defgroup DSP2_MISC_Private_Fun_Declaration - * @{ - */ - -/*@} end of group DSP2_MISC_Private_Fun_Declaration */ - -/** @defgroup DSP2_MISC_Private_Functions - * @{ - */ - -/*@} end of group DSP2_MISC_Private_Functions */ - -/** @defgroup DSP2_MISC_Public_Functions - * @{ - */ - -/****************************************************************************//** - * @brief DVP AS 2X function init - * - * @param dvp2xCfg: DVP AS 2X configuration structure pointer - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_2X_Init(DSP2_MISC_2X_Cfg_Type *dvp2xCfg) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_ACTIVE_LEVEL_TYPE(dvp2xCfg->hSyncLevel)); - CHECK_PARAM(IS_DSP2_MISC_ACTIVE_LEVEL_TYPE(dvp2xCfg->vSyncLevel)); - CHECK_PARAM(IS_DSP2_MISC_2X_DATA_ORDER_TYPE(dvp2xCfg->dataOrder)); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DVPAS_HS_INV, dvp2xCfg->hSyncLevel); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DVPAS_VS_INV, dvp2xCfg->vSyncLevel); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DVPAS_DA_ORDER, dvp2xCfg->dataOrder); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DVPAS_FIFO_TH, dvp2xCfg->fifoThreshold & 0x7ff); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_CONFIG, tmpVal); -} - -/****************************************************************************//** - * @brief DVP AS 2X function enable - * - * @param None - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_2X_Enable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_CONFIG); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_CONFIG, BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_DVPAS_ENABLE)); -} - -/****************************************************************************//** - * @brief DVP AS 2X function disable - * - * @param None - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_2X_Disable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_CONFIG); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_CONFIG, BL_CLR_REG_BIT(tmpVal, DSP2_MISC_RG_DVPAS_ENABLE)); -} - -/****************************************************************************/ /** - * @brief CAM input selection - * - * @param camId: CAM id - * @param inputType: CAM input type - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_CAM_Input_Select(DSP2_MISC_CAM_ID_Type camId, DSP2_MISC_CAM_Input_Type inputType) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_CAM_ID_TYPE(camId)); - CHECK_PARAM(IS_DSP2_MISC_CAM_INPUT_TYPE(inputType)); - - if (camId < DSP2_MISC_CAM_4_ID) { - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DVP2BUS_SRC_SEL_1); - tmpVal = (tmpVal & ~(0x3f << (camId * 8))) | (inputType & 0x3f) << (camId * 8); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DVP2BUS_SRC_SEL_1, tmpVal); - } else { - camId -= 4; - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DVP2BUS_SRC_SEL_2); - tmpVal = (tmpVal & ~(0x3f << (camId * 8))) | (inputType & 0x3f) << (camId * 8); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DVP2BUS_SRC_SEL_2, tmpVal); - } -} - -/****************************************************************************/ /** - * @brief CAM frame id type selection - * - * @param camId: CAM id - * @param idType: Frame id type - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_CAM_Frame_ID_Select(DSP2_MISC_CAM_ID_Type camId, DSP2_MISC_Frame_ID_Type idType) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_CAM_ID_TYPE(camId)); - CHECK_PARAM(IS_DSP2_MISC_FRAME_ID_TYPE(idType)); - - if (camId < DSP2_MISC_CAM_4_ID) { - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DVP2BUS_SRC_SEL_1); - tmpVal = (tmpVal & ~(0x1 << (camId * 8 + DSP2_MISC_RG_D2X_ID_SEL_A_POS))) | idType << (camId * 8 + DSP2_MISC_RG_D2X_ID_SEL_A_POS); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DVP2BUS_SRC_SEL_1, tmpVal); - } else { - camId -= 4; - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DVP2BUS_SRC_SEL_2); - tmpVal = (tmpVal & ~(0x1 << (camId * 8 + DSP2_MISC_RG_D2X_ID_SEL_E_POS))) | idType << (camId * 8 + DSP2_MISC_RG_D2X_ID_SEL_E_POS); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DVP2BUS_SRC_SEL_2, tmpVal); - } -} - -/****************************************************************************/ /** - * @brief Frame id init - * - * @param idType: Frame id type - * @param edgeType: Frame id edge type - * @param vsyncCnt: Vsync count to trigger id increment - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_Frame_ID_Init(DSP2_MISC_Frame_ID_Type idType, DSP2_MISC_Frame_ID_Edge_Type edgeType, uint16_t vsyncCnt) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_FRAME_ID_TYPE(idType)); - CHECK_PARAM(IS_DSP2_MISC_FRAME_ID_EDGE_TYPE(edgeType)); - - if (idType == DSP2_MISC_FRAME_BAYER_ID) { - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DSP2_ID_BAYER); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_BAYER_IDGEN_EDGE, edgeType); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_BAYER_IDGEN_CNT_INCR, vsyncCnt); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DSP2_ID_BAYER, tmpVal); - } else { - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DSP2_ID_YUV); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_YUV_IDGEN_EDGE, edgeType); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_YUV_IDGEN_CNT_INCR, vsyncCnt); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DSP2_ID_YUV, tmpVal); - } -} - -/****************************************************************************/ /** - * @brief Reset frame id - * - * @param idType: Frame id type - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_Frame_ID_Reset(DSP2_MISC_Frame_ID_Type idType) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_FRAME_ID_TYPE(idType)); - - if (idType == DSP2_MISC_FRAME_BAYER_ID) { - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DSP2_ID_BAYER); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DSP2_ID_BAYER, BL_SET_REG_BIT(tmpVal, DSP2_MISC_REG_BAYER_IDGEN_RST)); - } else { - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DSP2_ID_YUV); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DSP2_ID_YUV, BL_SET_REG_BIT(tmpVal, DSP2_MISC_REG_YUV_IDGEN_RST)); - } -} - -/****************************************************************************/ /** - * @brief OSD input selection - * - * @param osdId: OSD id - * @param inputType: OSD input type - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_OSD_Input_Select(DSP2_MISC_OSD_ID_Type osdId, DSP2_MISC_OSD_Input_Type inputType) -{ - uint32_t tmpVal; - uint32_t osdAddr = DSP2_MISC_BASE + DSP2_MISC_OSDA_I_CTRL_OFFSET + 4 * osdId; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_OSD_ID_TYPE(osdId)); - CHECK_PARAM(IS_DSP2_MISC_OSD_INPUT_TYPE(inputType)); - - tmpVal = BL_RD_WORD(osdAddr); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_OSDA_SEL, inputType); - BL_WR_WORD(osdAddr, tmpVal); -} - -/****************************************************************************/ /** - * @brief OSD probe input selection - * - * @param inputType: OSD input type - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_OSD_Probe_Input_Select(DSP2_MISC_OSD_Input_Type inputType) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_OSD_INPUT_TYPE(inputType)); - - if (inputType > DSP2_MISC_OSD_DSP2_INPUT) { - return; - } - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_OSDA_I_CTRL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_OSD_PB_SEL, inputType); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_OSDA_I_CTRL, tmpVal); -} - -/****************************************************************************/ /** - * @brief Crop init - * - * @param cropId: Crop id - * @param cropCfg: Crop configuration structure pointer - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_Crop_Init(DSP2_MISC_Crop_ID_Type cropId, DSP2_MISC_Crop_Cfg_Type *cropCfg) -{ - uint32_t cropAddr = DSP2_MISC_BASE + DSP2_MISC_CROPA_HSYNC_OFFSET + 8 * cropId; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_CROP_ID_TYPE(cropId)); - - BL_WR_WORD(cropAddr, cropCfg->hsyncEnd << 16 | cropCfg->hsyncStart); - cropAddr += 4; - BL_WR_WORD(cropAddr, cropCfg->vsyncEnd << 16 | cropCfg->vsyncStart); -} - -/****************************************************************************/ /** - * @brief Crop enable - * - * @param cropId: Crop id - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_Crop_Enable(DSP2_MISC_Crop_ID_Type cropId) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_CROP_ID_TYPE(cropId)); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_CROP_ENABLE); - - switch (cropId) { - case DSP2_MISC_CROP_0_ID: - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_REG_CROPA_ENABLE); - break; - - case DSP2_MISC_CROP_1_ID: - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_REG_CROPB_ENABLE); - break; - - case DSP2_MISC_CROP_2_ID: - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_REG_CROPC_ENABLE); - break; - - case DSP2_MISC_CROP_3_ID: - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_REG_CROPD_ENABLE); - break; - - default: - break; - } - - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_CROP_ENABLE, tmpVal); -} - -/****************************************************************************/ /** - * @brief Crop disable - * - * @param cropId: Crop id - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_Crop_Disable(DSP2_MISC_Crop_ID_Type cropId) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_CROP_ID_TYPE(cropId)); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_CROP_ENABLE); - - switch (cropId) { - case DSP2_MISC_CROP_0_ID: - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_MISC_REG_CROPA_ENABLE); - break; - - case DSP2_MISC_CROP_1_ID: - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_MISC_REG_CROPB_ENABLE); - break; - - case DSP2_MISC_CROP_2_ID: - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_MISC_REG_CROPC_ENABLE); - break; - - case DSP2_MISC_CROP_3_ID: - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_MISC_REG_CROPD_ENABLE); - break; - - default: - break; - } - - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_CROP_ENABLE, tmpVal); -} - -/****************************************************************************/ /** - * @brief Scaler input selection - * - * @param scalerId: Scaler id - * @param inputType: Scaler input type - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_Scaler_Input_Select(DSP2_MISC_Scaler_ID_Type scalerId, DSP2_MISC_Scaler_Input_Type inputType) -{ - uint32_t tmpVal; - uint32_t scalerAddr = DSP2_MISC_BASE + DSP2_MISC_SCALERA_I_SIZE_OFFSET + 8 * scalerId; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_SCALER_ID_TYPE(scalerId)); - CHECK_PARAM(IS_DSP2_MISC_SCALER_INPUT_TYPE(inputType)); - - tmpVal = BL_RD_WORD(scalerAddr); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SCALERA_SEL, inputType); - BL_WR_WORD(scalerAddr, tmpVal); -} - -/****************************************************************************/ /** - * @brief Scaler init - * - * @param scalerId: Scaler id - * @param scalerCfg: Scaler configuration structure pointer - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_Scaler_Init(DSP2_MISC_Scaler_ID_Type scalerId, DSP2_MISC_Scaler_Cfg_Type *scalerCfg) -{ - uint32_t tmpVal; - uint32_t scalerAddr = DSP2_MISC_BASE + DSP2_MISC_SCALERA_I_SIZE_OFFSET + 8 * scalerId; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_SCALER_ID_TYPE(scalerId)); - - tmpVal = BL_RD_WORD(scalerAddr); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SCALERA_I_W, scalerCfg->inputWidth); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SCALERA_I_H, scalerCfg->inputHeight & 0x7ff); - BL_WR_WORD(scalerAddr, tmpVal); - - scalerAddr += 4; - tmpVal = BL_RD_WORD(scalerAddr); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SCALERA_O_W, scalerCfg->outputWidth); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SCALERA_O_H, scalerCfg->outputHeight); - BL_WR_WORD(scalerAddr, tmpVal); -} - -/****************************************************************************/ /** - * @brief Scaler enable - * - * @param scalerId: Scaler id - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_Scaler_Enable(DSP2_MISC_Scaler_ID_Type scalerId) -{ - uint32_t tmpVal; - uint32_t scalerAddr = DSP2_MISC_BASE + DSP2_MISC_SCALERA_I_SIZE_OFFSET + 8 * scalerId; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_SCALER_ID_TYPE(scalerId)); - - tmpVal = BL_RD_WORD(scalerAddr); - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_MISC_RG_SCALERA_BYPASS); - BL_WR_WORD(scalerAddr, tmpVal); -} - -/****************************************************************************/ /** - * @brief Scaler disable - * - * @param scalerId: Scaler id - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_Scaler_Disable(DSP2_MISC_Scaler_ID_Type scalerId) -{ - uint32_t tmpVal; - uint32_t scalerAddr = DSP2_MISC_BASE + DSP2_MISC_SCALERA_I_SIZE_OFFSET + 8 * scalerId; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_SCALER_ID_TYPE(scalerId)); - - tmpVal = BL_RD_WORD(scalerAddr); - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_SCALERA_BYPASS); - BL_WR_WORD(scalerAddr, tmpVal); -} - -/****************************************************************************/ /** - * @brief Adjust input selection - * - * @param adjustId: Adjust id - * @param inputType: Adjust input type - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_Scaler_Shadow(DSP2_MISC_Scaler_ID_Type scalerId) -{ - uint32_t tmpVal; - uint32_t scalerAddr = DSP2_MISC_BASE + DSP2_MISC_SCALERA_I_SIZE_OFFSET + 8 * scalerId; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_SCALER_ID_TYPE(scalerId)); - - tmpVal = BL_RD_WORD(scalerAddr); - BL_WR_WORD(scalerAddr, BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_SCLRA_SW_SH)); -} - -/****************************************************************************/ /** - * @brief Adjust input selection - * - * @param adjustId: Adjust id - * @param inputType: Adjust input type - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_Adjust_Input_Select(DSP2_MISC_Adjust_ID_Type adjustId, DSP2_MISC_Adjust_Input_Type inputType) -{ - uint32_t tmpVal; - uint32_t adjustAddr = DSP2_MISC_BASE + DSP2_MISC_ADJA_CTRL_2_OFFSET + 16 * adjustId; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_ADJUST_ID_TYPE(adjustId)); - CHECK_PARAM(IS_DSP2_MISC_ADJUST_INPUT_TYPE(inputType)); - - tmpVal = BL_RD_WORD(adjustAddr); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_ADJA_SEL, inputType); - BL_WR_WORD(adjustAddr, tmpVal); -} - -/****************************************************************************/ /** - * @brief Adjust init - * - * @param adjustId: Adjust id - * @param adjustCfg: Adjust configuration structure pointer - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_Adjust_Init(DSP2_MISC_Adjust_ID_Type adjustId, DSP2_MISC_Adjust_Cfg_Type *adjustCfg) -{ - uint32_t tmpVal; - uint32_t adjustAddr = DSP2_MISC_BASE + DSP2_MISC_ADJA_CTRL_0_OFFSET + 16 * adjustId; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_ADJUST_ID_TYPE(adjustId)); - - tmpVal = BL_RD_WORD(adjustAddr); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_ADJA_Y_LUMA, adjustCfg->yLuma); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_ADJA_Y_MUL0, adjustCfg->yMul0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_ADJA_Y_MUL1, adjustCfg->yMul1); - BL_WR_WORD(adjustAddr, tmpVal); - - adjustAddr += 4; - tmpVal = BL_RD_WORD(adjustAddr); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_ADJA_Y_MIN, adjustCfg->yMin); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_ADJA_Y_MAX, adjustCfg->yMax); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_ADJA_UV_MIN, adjustCfg->uvMin); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_ADJA_UV_MAX, adjustCfg->uvMax); - BL_WR_WORD(adjustAddr, tmpVal); - - adjustAddr += 4; - tmpVal = BL_RD_WORD(adjustAddr); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_ADJA_UV_MUL0, adjustCfg->uvMul0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_ADJA_UV_MUL1, adjustCfg->uvMul1); - BL_WR_WORD(adjustAddr, tmpVal); -} - -/****************************************************************************/ /** - * @brief Adjust enable - * - * @param adjustId: Adjust id - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_Adjust_Enable(DSP2_MISC_Adjust_ID_Type adjustId) -{ - uint32_t tmpVal; - uint32_t adjustAddr = DSP2_MISC_BASE + DSP2_MISC_ADJA_CTRL_0_OFFSET + 16 * adjustId; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_ADJUST_ID_TYPE(adjustId)); - - tmpVal = BL_RD_WORD(adjustAddr); - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_REG_ADJA_ADJ_EB); - BL_WR_WORD(adjustAddr, tmpVal); -} - -/****************************************************************************/ /** - * @brief Adjust disable - * - * @param adjustId: Adjust id - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_Adjust_Disable(DSP2_MISC_Adjust_ID_Type adjustId) -{ - uint32_t tmpVal; - uint32_t adjustAddr = DSP2_MISC_BASE + DSP2_MISC_ADJA_CTRL_0_OFFSET + 16 * adjustId; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_ADJUST_ID_TYPE(adjustId)); - - tmpVal = BL_RD_WORD(adjustAddr); - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_MISC_REG_ADJA_ADJ_EB); - BL_WR_WORD(adjustAddr, tmpVal); -} - -/****************************************************************************/ /** - * @brief Display init - * - * @param displayCfg: Display configuration structure pointer - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_Display_Init(DSP2_MISC_Display_Cfg_Type *displayCfg) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_ADJUST_ID_TYPE(adjustId)); - CHECK_PARAM(IS_DSP2_MISC_DISPLAY_OSD_INPUT_TYPE(displayCfg->osdType)); - CHECK_PARAM(IS_DSP2_MISC_DISPLAY_INPUT_TYPE(displayCfg->inputType)); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_MISC_RG_DISP_HDMI_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_MISC_RG_DISP_BT1120_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_MISC_RG_DISP_DPI_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_MUX_SEL, displayCfg->inputType); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_OSDDP_SEL, displayCfg->osdType); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_CONFIG, tmpVal); - - if (displayCfg->dpiEnable) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_DISP_DPI_EN); - } else if (displayCfg->hdmiEnable) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_DISP_HDMI_EN); - } else if (displayCfg->bt1120Enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_DISP_BT1120_EN); - } - - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_CONFIG, tmpVal); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_DPI_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_DPI_HS_W, displayCfg->hsyncWidth); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_DPI_HFP_W, displayCfg->hfpWidth); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_DPI_VS_W, displayCfg->vsyncWidth); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_DPI_VFP_W, displayCfg->vfpWidth); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_DPI_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief Display gamma init - * - * @param gammaCfg: Display gamma configuration structure pointer - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_Display_Gamma_Init(DSP2_MISC_Display_Gamma_Cfg_Type *gammaCfg) -{ - uint32_t tmpVal, i, j; - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_GMA_CFG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_DP_GMA_CH0_EN, gammaCfg->ch0Enable); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_DP_GMA_CH1_EN, gammaCfg->ch1Enable); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_DP_GMA_CH2_EN, gammaCfg->ch2Enable); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_GMA_CFG, tmpVal); - - if (gammaCfg->gammaCurve == NULL) { - return; - } - - for (i = 0; i < 64; i++) { - tmpVal = 0; - - for (j = 0; j < 4; j++) { - tmpVal |= gammaCfg->gammaCurve[j + 4 * i] << (8 * j); - } - - BL_WR_WORD(DSP2_MISC_BASE + DSP2_MISC_DISP_GMA_CURVE_00_OFFSET + 4 * i, tmpVal); - } -} - -/****************************************************************************/ /** - * @brief YUV2RGB input selection - * - * @param inputType: YUV2RGB input type - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_YUV2RGB_Input_Select(DSP2_MISC_YUV2RGB_Input_Type inputType) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_YUV2RGB_INPUT_TYPE(inputType)); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_SEL, inputType); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief YUV2RGB init - * - * @param yuv2rgbId: YUV2RGB ID type - * @param yuv2rgbCfg: YUV2RGB configuration structure pointer - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_YUV2RGB_Init(DSP2_MISC_YUV2RGB_ID_Type yuv2rgbId, DSP2_MISC_YUV2RGB_Cfg_Type *yuv2rgbCfg) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_YUV2RGB_ID_TYPE(yuv2rgbId)); - - if (yuv2rgbId == DSP2_MISC_YUV2RGB_DISPLAY_ID) { - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_YUV_RGB_CONFIG_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_PRE_0, yuv2rgbCfg->preOffset0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_PRE_1, yuv2rgbCfg->preOffset1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_PRE_2, yuv2rgbCfg->preOffset2); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_YUV_RGB_CONFIG_0, tmpVal); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_YUV_RGB_CONFIG_1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_POS_0, yuv2rgbCfg->postOffset0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_POS_1, yuv2rgbCfg->postOffset1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_POS_2, yuv2rgbCfg->postOffset2); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_YUV_RGB_CONFIG_1, tmpVal); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_YUV_RGB_CONFIG_2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_MTX_00, yuv2rgbCfg->matrix00); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_MTX_01, yuv2rgbCfg->matrix01); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_MTX_02_L, yuv2rgbCfg->matrix02); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_YUV_RGB_CONFIG_2, tmpVal); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_YUV_RGB_CONFIG_3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_MTX_02_U, yuv2rgbCfg->matrix02 >> 8); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_MTX_10, yuv2rgbCfg->matrix10); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_MTX_11, yuv2rgbCfg->matrix11); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_MTX_12_L, yuv2rgbCfg->matrix12); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_YUV_RGB_CONFIG_3, tmpVal); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_YUV_RGB_CONFIG_4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_MTX_12_U, yuv2rgbCfg->matrix12 >> 4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_MTX_20, yuv2rgbCfg->matrix20); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_MTX_21, yuv2rgbCfg->matrix21); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_YUV_RGB_CONFIG_4, tmpVal); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_YUV_RGB_CONFIG_5); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_MTX_22, yuv2rgbCfg->matrix22); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_YUV_RGB_CONFIG_5, tmpVal); - - /* Enable or disable function */ - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_YUV_RGB_CONFIG_0); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_YUV_RGB_CONFIG_0, BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_EN, yuv2rgbCfg->enable)); - - } else if (yuv2rgbId == DSP2_MISC_YUV2RGB_NORMAL_ID) { - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_PRE_0, yuv2rgbCfg->preOffset0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_POS_0, yuv2rgbCfg->postOffset0); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_0, tmpVal); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_PRE_1, yuv2rgbCfg->preOffset1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_POS_1, yuv2rgbCfg->postOffset1); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_1, tmpVal); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_PRE_2, yuv2rgbCfg->preOffset2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_POS_2, yuv2rgbCfg->postOffset2); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_2, tmpVal); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_MTX_00, yuv2rgbCfg->matrix00); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_MTX_01, yuv2rgbCfg->matrix01); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_3, tmpVal); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_MTX_02, yuv2rgbCfg->matrix02); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_MTX_10, yuv2rgbCfg->matrix10); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_4, tmpVal); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_5); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_MTX_11, yuv2rgbCfg->matrix11); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_MTX_12, yuv2rgbCfg->matrix12); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_5, tmpVal); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_6); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_MTX_20, yuv2rgbCfg->matrix20); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_MTX_21, yuv2rgbCfg->matrix21); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_6, tmpVal); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_7); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_MTX_22, yuv2rgbCfg->matrix22); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_7, tmpVal); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_0); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_0, BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_EN, yuv2rgbCfg->enable)); - } -} - -/****************************************************************************/ /** - * @brief RGB2YUV init - * - * @param rgb2yuvCfg: YUV2RGB configuration structure pointer - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_RGB2YUV_Init(DSP2_MISC_YUV2RGB_Cfg_Type *rgb2yuvCfg) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_RGB2YUV_CONFIG_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_PRE_0, rgb2yuvCfg->preOffset0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_PRE_1, rgb2yuvCfg->preOffset1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_PRE_2, rgb2yuvCfg->preOffset2); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_RGB2YUV_CONFIG_0, tmpVal); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_RGB2YUV_CONFIG_1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_POS_0, rgb2yuvCfg->postOffset0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_POS_1, rgb2yuvCfg->postOffset1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_POS_2, rgb2yuvCfg->postOffset2); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_RGB2YUV_CONFIG_1, tmpVal); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_RGB2YUV_CONFIG_2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_MTX_00, rgb2yuvCfg->matrix00); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_MTX_01, rgb2yuvCfg->matrix01); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_MTX_02_L, rgb2yuvCfg->matrix02); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_RGB2YUV_CONFIG_2, tmpVal); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_RGB2YUV_CONFIG_3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_MTX_02_U, rgb2yuvCfg->matrix02 >> 8); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_MTX_10, rgb2yuvCfg->matrix10); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_MTX_11, rgb2yuvCfg->matrix11); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_MTX_12_L, rgb2yuvCfg->matrix12); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_RGB2YUV_CONFIG_3, tmpVal); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_RGB2YUV_CONFIG_4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_MTX_12_U, rgb2yuvCfg->matrix12 >> 4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_MTX_20, rgb2yuvCfg->matrix20); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_MTX_21, rgb2yuvCfg->matrix21); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_RGB2YUV_CONFIG_4, tmpVal); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_RGB2YUV_CONFIG_5); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_MTX_22, rgb2yuvCfg->matrix22); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_RGB2YUV_CONFIG_5, tmpVal); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_RGB2YUV_CONFIG_0); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_RGB2YUV_CONFIG_0, BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_EN, rgb2yuvCfg->enable)); -} - -/****************************************************************************/ /** - * @brief Clear certain or all of the interrupt - * - * @param intType: Interrupt type - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_Int_Clear(DSP2_MISC_INT_Type intType) -{ - uint32_t tmpVal = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_INT_TYPE(intType)); - - switch (intType) { - case DSP2_MISC_INT_AWB0: - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_AWB_INT_CLR); - break; - - case DSP2_MISC_INT_AE: - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_AE_INT_CLR); - break; - - case DSP2_MISC_INT_WDR: - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_WDR_INT_CLR); - break; - - case DSP2_MISC_INT_AWB1: - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_AWB2_INT_CLR); - break; - - case DSP2_MISC_INT_OSD_PB: - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_OSD_PB_INT_CLR); - break; - - case DSP2_MISC_INT_SEOF0: - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_SEOF1_INT_CLR); - break; - - case DSP2_MISC_INT_SEOF1: - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_SEOF2_INT_CLR); - break; - - case DSP2_MISC_INT_SEOF2: - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_SEOF3_INT_CLR); - break; - - case DSP2_MISC_INT_AE_HIST: - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_AE_HIST_INT_CLR); - break; - - case DSP2_MISC_INT_AWB2: - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_AWB3_INT_CLR); - break; - - case DSP2_MISC_INT_DISPLAY: - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_DP_SEOF0_INT_CLR); - break; - - case DSP2_MISC_INT_SEOF3: - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_SEOF4_INT_CLR); - break; - - case DSP2_MISC_INT_ALL: - tmpVal = 0x7f1f; - break; - - default: - break; - } - - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_INT_CLR, tmpVal); -} - -/****************************************************************************/ /** - * @brief Mask/Unmask certain or all of the interrupt - * - * @param intType: Interrupt type - * @param intMask: Mask or unmask - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_Int_Mask(DSP2_MISC_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_INT_TYPE(intType)); - CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_INT_CTRL); - - switch (intType) { - case DSP2_MISC_INT_AWB0: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_AWB_INT_MASK, intMask); - break; - - case DSP2_MISC_INT_AE: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_AE_INT_MASK, intMask); - break; - - case DSP2_MISC_INT_WDR: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_WDR_INT_MASK, intMask); - break; - - case DSP2_MISC_INT_AWB1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_AWB2_INT_MASK, intMask); - break; - - case DSP2_MISC_INT_OSD_PB: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_OSD_PB_INT_MASK, intMask); - break; - - case DSP2_MISC_INT_SEOF0: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SEOF1_INT_MASK, intMask); - break; - - case DSP2_MISC_INT_SEOF1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SEOF2_INT_MASK, intMask); - break; - - case DSP2_MISC_INT_SEOF2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SEOF3_INT_MASK, intMask); - break; - - case DSP2_MISC_INT_AE_HIST: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_AE_HIST_INT_MASK, intMask); - break; - - case DSP2_MISC_INT_AWB2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_AWB3_INT_MASK, intMask); - break; - - case DSP2_MISC_INT_DISPLAY: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DP_SEOF0_INT_MASK, intMask); - break; - - case DSP2_MISC_INT_SEOF3: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SEOF4_INT_MASK, intMask); - break; - - case DSP2_MISC_INT_ALL: - if (intMask == MASK) { - tmpVal |= 0x1131111f; - } else { - tmpVal &= ~0x1131111f; - } - - break; - - default: - break; - } - - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_INT_CTRL, tmpVal); -} - -/****************************************************************************/ /** - * @brief Install dsp2 misc interrupt callback function - * - * @param intType: DSP2 misc interrupt type - * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void DSP2_MISC_Int_Callback_Install(DSP2_MISC_INT_Type intType, intCallback_Type *cbFun) -{ - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_INT_TYPE(intType)); - - switch (intType) { -#if defined(CPU_D0) - - case DSP2_MISC_INT_AWB0: - Interrupt_Handler_Register(DSP2_AWB0_IRQn, AWB0_IRQHandler); - break; -#endif - - case DSP2_MISC_INT_AE: - Interrupt_Handler_Register(DSP2_AE_IRQn, AE_IRQHandler); - break; - - case DSP2_MISC_INT_WDR: - Interrupt_Handler_Register(DSP2_WDR_IRQn, WDR_IRQHandler); - break; - - case DSP2_MISC_INT_AWB1: - Interrupt_Handler_Register(DSP2_AWB1_IRQn, AWB1_IRQHandler); - break; - - case DSP2_MISC_INT_OSD_PB: - Interrupt_Handler_Register(OSD_PB_IRQn, OSD_PB_IRQHandler); - break; - - case DSP2_MISC_INT_SEOF0: - Interrupt_Handler_Register(SEOF_INT0_IRQn, SEOF0_IRQHandler); - break; - - case DSP2_MISC_INT_SEOF1: - Interrupt_Handler_Register(SEOF_INT1_IRQn, SEOF1_IRQHandler); - break; - - case DSP2_MISC_INT_SEOF2: - Interrupt_Handler_Register(SEOF_INT2_IRQn, SEOF2_IRQHandler); - break; - - case DSP2_MISC_INT_AE_HIST: - Interrupt_Handler_Register(DSP2_AE_HIST_IRQn, AE_HIST_IRQHandler); - break; - - case DSP2_MISC_INT_AWB2: - Interrupt_Handler_Register(DSP2_AWB2_IRQn, AWB2_IRQHandler); - break; - - case DSP2_MISC_INT_DISPLAY: - Interrupt_Handler_Register(DISPLAY_IRQn, Display_IRQHandler); - break; - - case DSP2_MISC_INT_SEOF3: - Interrupt_Handler_Register(SEOF_INT3_IRQn, SEOF3_IRQHandler); - break; - - default: - break; - } - - dsp2MiscIntCbfArra[intType] = cbFun; -} -#endif - -/****************************************************************************/ /** - * @brief Select SEOF interrupt vsync source - * - * @param intType: SEOF interrupt type - * @param source: SEOF interrupt vsync source type - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_SEOF_Set_Source(DSP2_MISC_INT_Type intType, DSP2_MISC_SEOF_Source_Type source) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_INT_TYPE(intType)); - CHECK_PARAM(IS_DSP2_MISC_SEOF_SOURCE_TYPE(source)); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_INT_CTRL); - - switch (intType) { - case DSP2_MISC_INT_SEOF0: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SEOF1_INT_SRC, source); - break; - - case DSP2_MISC_INT_SEOF1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SEOF2_INT_SRC, source); - break; - - case DSP2_MISC_INT_SEOF2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SEOF3_INT_SRC, source); - break; - - case DSP2_MISC_INT_DISPLAY: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DP_SEOF0_INT_SRC, source & 0x1); - break; - - case DSP2_MISC_INT_SEOF3: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SEOF4_INT_SRC, source); - break; - - default: - return; - break; - } - - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_INT_CTRL, tmpVal); -} - -/****************************************************************************/ /** - * @brief Select SEOF interrupt vsync source - * - * @param intType: SEOF interrupt type - * @param edge: SEOF interrupt edge type - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_SEOF_Set_Edge(DSP2_MISC_INT_Type intType, DSP2_MISC_SEOF_Edge_Type edge) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_INT_TYPE(intType)); - CHECK_PARAM(IS_DSP2_MISC_SEOF_SOURCE_TYPE(edge)); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_INT_CTRL); - - switch (intType) { - case DSP2_MISC_INT_SEOF0: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SEOF1_INT_EDGE, edge); - break; - - case DSP2_MISC_INT_SEOF1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SEOF2_INT_EDGE, edge); - break; - - case DSP2_MISC_INT_SEOF2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SEOF3_INT_EDGE, edge); - break; - - case DSP2_MISC_INT_DISPLAY: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DP_SEOF0_INT_EDGE, edge); - break; - - case DSP2_MISC_INT_SEOF3: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SEOF4_INT_EDGE, edge); - break; - - default: - return; - break; - } - - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_INT_CTRL, tmpVal); -} - -/****************************************************************************/ /** - * @brief Reshape init - * - * @param reshapeCfg: Reshape configuration structure pointer - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_Reshape_Init(DSP2_MISC_Reshape_Cfg_Type *reshapeCfg) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_ACTIVE_LEVEL_TYPE(reshapeCfg->hSyncLevel)); - CHECK_PARAM(IS_DSP2_MISC_ACTIVE_LEVEL_TYPE(reshapeCfg->vSyncLevel)); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DVP_RESHAPE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_RSHP_TGL_COUNT, reshapeCfg->vsyncNumber & 0x1f); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_RSHP_HSYNC_INV, reshapeCfg->hSyncLevel); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_RSHP_VSYNC_INV, reshapeCfg->vSyncLevel); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_RSHP_EN, reshapeCfg->enable); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DVP_RESHAPE, tmpVal); -} - -/****************************************************************************/ /** - * @brief Clear vsync toggle counter - * - * @param None - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_Reshape_Counter_Clear(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DVP_RESHAPE); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DVP_RESHAPE, BL_SET_REG_BIT(tmpVal, DSP2_MISC_REG_RSHP_CLR)); -} - -/****************************************************************************/ /** - * @brief Enable or disable use DE as hsync for DSP2 - * - * @param enable: Enable or disable - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_DE_As_Hsync(BL_Fun_Type enable) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_CR_DSP2_DE_AS_HSYNC, enable); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief Select DVP TSRC data source - * - * @param sourceType: DVP or CSI - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_TSRC_Source_Select(DSP2_MISC_TSRC_Source_Type sourceType) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_PIX_DATA_CTRL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_DSP2_DTSRC_SRC, sourceType); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_PIX_DATA_CTRL, tmpVal); -} - -/****************************************************************************/ /** - * @brief Configure bayer data shift function - * - * @param bitEnable: Enable bits used - * @param shiftType: Set shift direction - * @param bitShift: Set Shift bits - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_Bayer_Shift(uint16_t bitEnable, DSP2_MISC_Bayer_Shift_Type shiftType, uint8_t bitShift) -{ - uint32_t tmpVal = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_BAYER_SHIFT_TYPE(shiftType)); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_PIX_DATA_CTRL, bitEnable); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_PIX_DATA_SHT_BIT, bitShift); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_PIX_DATA_SHT_DIR, shiftType); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_PIX_DATA_CTRL, tmpVal); -} - -/****************************************************************************/ /** - * @brief Reduce m frames to n frames function enable - * - * @param m: Total frame count - * @param n: Enabled frame count - * @param step: Step between enabled frames - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_M2N_Enable(uint8_t m, uint8_t n, uint8_t step) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DVP_FRAME_M_TO_N); - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_CR_FRAME_M_TO_N_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_CR_FRAME_INTERVAL, step); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_CR_FRAME_CNT_N, n); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_CR_FRAME_CNT_M, m); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DVP_FRAME_M_TO_N, tmpVal); -} - -/****************************************************************************/ /** - * @brief Reduce m frames to n frames function disable - * - * @param None - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_M2N_Disable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DVP_FRAME_M_TO_N); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DVP_FRAME_M_TO_N, BL_CLR_REG_BIT(tmpVal, DSP2_MISC_CR_FRAME_M_TO_N_EN)); -} - -/****************************************************************************/ /** - * @brief SEOF0 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void SEOF0_IRQHandler(void) -{ - DSP2_MISC_Int_Clear(DSP2_MISC_INT_SEOF0); - - if (dsp2MiscIntCbfArra[DSP2_MISC_INT_SEOF0] != NULL) { - dsp2MiscIntCbfArra[DSP2_MISC_INT_SEOF0](); - } -} -#endif - -/****************************************************************************/ /** - * @brief SEOF1 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void SEOF1_IRQHandler(void) -{ - DSP2_MISC_Int_Clear(DSP2_MISC_INT_SEOF1); - - if (dsp2MiscIntCbfArra[DSP2_MISC_INT_SEOF1] != NULL) { - dsp2MiscIntCbfArra[DSP2_MISC_INT_SEOF1](); - } -} -#endif - -/****************************************************************************/ /** - * @brief SEOF2 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void SEOF2_IRQHandler(void) -{ - DSP2_MISC_Int_Clear(DSP2_MISC_INT_SEOF2); - - if (dsp2MiscIntCbfArra[DSP2_MISC_INT_SEOF2] != NULL) { - dsp2MiscIntCbfArra[DSP2_MISC_INT_SEOF2](); - } -} -#endif - -/****************************************************************************/ /** - * @brief SEOF3 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void SEOF3_IRQHandler(void) -{ - DSP2_MISC_Int_Clear(DSP2_MISC_INT_SEOF3); - - if (dsp2MiscIntCbfArra[DSP2_MISC_INT_SEOF3] != NULL) { - dsp2MiscIntCbfArra[DSP2_MISC_INT_SEOF3](); - } -} -#endif - -/****************************************************************************/ /** - * @brief AWB0 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void AWB0_IRQHandler(void) -{ - DSP2_MISC_Int_Clear(DSP2_MISC_INT_AWB0); - - if (dsp2MiscIntCbfArra[DSP2_MISC_INT_AWB0] != NULL) { - dsp2MiscIntCbfArra[DSP2_MISC_INT_AWB0](); - } -} -#endif - -/****************************************************************************/ /** - * @brief AWB1 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void AWB1_IRQHandler(void) -{ - DSP2_MISC_Int_Clear(DSP2_MISC_INT_AWB1); - - if (dsp2MiscIntCbfArra[DSP2_MISC_INT_AWB1] != NULL) { - dsp2MiscIntCbfArra[DSP2_MISC_INT_AWB1](); - } -} -#endif - -/****************************************************************************/ /** - * @brief AWB2 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void AWB2_IRQHandler(void) -{ - DSP2_MISC_Int_Clear(DSP2_MISC_INT_AWB2); - - if (dsp2MiscIntCbfArra[DSP2_MISC_INT_AWB2] != NULL) { - dsp2MiscIntCbfArra[DSP2_MISC_INT_AWB2](); - } -} -#endif - -/****************************************************************************/ /** - * @brief AE interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void AE_IRQHandler(void) -{ - DSP2_MISC_Int_Clear(DSP2_MISC_INT_AE); - - if (dsp2MiscIntCbfArra[DSP2_MISC_INT_AE] != NULL) { - dsp2MiscIntCbfArra[DSP2_MISC_INT_AE](); - } -} -#endif - -/****************************************************************************/ /** - * @brief AE HIST interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void AE_HIST_IRQHandler(void) -{ - DSP2_MISC_Int_Clear(DSP2_MISC_INT_AE_HIST); - - if (dsp2MiscIntCbfArra[DSP2_MISC_INT_AE_HIST] != NULL) { - dsp2MiscIntCbfArra[DSP2_MISC_INT_AE_HIST](); - } -} -#endif - -/****************************************************************************/ /** - * @brief WDR interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void WDR_IRQHandler(void) -{ - DSP2_MISC_Int_Clear(DSP2_MISC_INT_WDR); - - if (dsp2MiscIntCbfArra[DSP2_MISC_INT_WDR] != NULL) { - dsp2MiscIntCbfArra[DSP2_MISC_INT_WDR](); - } -} -#endif - -/****************************************************************************/ /** - * @brief OSD PB interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void OSD_PB_IRQHandler(void) -{ - DSP2_MISC_Int_Clear(DSP2_MISC_INT_OSD_PB); - - if (dsp2MiscIntCbfArra[DSP2_MISC_INT_OSD_PB] != NULL) { - dsp2MiscIntCbfArra[DSP2_MISC_INT_OSD_PB](); - } -} -#endif - -/****************************************************************************/ /** - * @brief Display interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void Display_IRQHandler(void) -{ - DSP2_MISC_Int_Clear(DSP2_MISC_INT_DISPLAY); - - if (dsp2MiscIntCbfArra[DSP2_MISC_INT_DISPLAY] != NULL) { - dsp2MiscIntCbfArra[DSP2_MISC_INT_DISPLAY](); - } -} -#endif - -/*@} end of group DSP2_MISC_Public_Functions */ - -/*@} end of group DSP2_MISC */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsp2_wdr.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsp2_wdr.c deleted file mode 100644 index 92324196fe..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsp2_wdr.c +++ /dev/null @@ -1,557 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_dsp2_wdr.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_dsp2_wdr.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup DSP2_WDR - * @{ - */ - -/** @defgroup DSP2_WDR_Private_Macros - * @{ - */ -#define DSP2_WDR_ROI_WEIGHT_MAX (15) -#define DSP2_WDR_CURVE_WEIGHT_MAX (2 << 8) -#define DSP2_WDR_POST_ENHANCE_Y_OFFSET_MAX ((2 << 12) - 1) -#define DSP2_WDR_POST_ENHANCE_Y_GAIN_MAX ((2 << 15) - 1) -#define DSP2_WDR_POST_ENHANCE_C_GAIN_MAX ((2 << 15) - 1) - -/*@} end of group DSP2_WDR_Private_Macros */ - -/** @defgroup DSP2_WDR_Private_Types - * @{ - */ - -/*@} end of group DSP2_WDR_Private_Types */ - -/** @defgroup DSP2_WDR_Private_Variables - * @{ - */ - -/*@} end of group DSP2_WDR_Private_Variables */ - -/** @defgroup DSP2_WDR_Global_Variables - * @{ - */ - -/*@} end of group DSP2_WDR_Global_Variables */ - -/** @defgroup DSP2_WDR_Private_Fun_Declaration - * @{ - */ - -/*@} end of group DSP2_WDR_Private_Fun_Declaration */ - -/** @defgroup DSP2_WDR_Private_Functions - * @{ - */ - -/*@} end of group DSP2_WDR_Private_Functions */ - -/** @defgroup DSP2_WDR_Public_Functions - * @{ - */ - -void DSP2_WDR_Get_WDR_State(BL_Fun_Type *state) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_0); - - if (BL_IS_REG_BIT_SET(tmpVal, DSP2_BLBACK_WDR_EN_PRE)) { - *state = ENABLE; - } else { - *state = DISABLE; - } -} - -void DSP2_WDR_Set_WDR_State(BL_Fun_Type state) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_0); - - if (ENABLE == state) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_BLBACK_WDR_EN_PRE); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_BLBACK_WDR_EN_PRE); - } - - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_0, tmpVal); -} - -void DSP2_WDR_Set_CS_State(BL_Fun_Type state) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_CS_0); - - if (ENABLE == state) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_BLBACK_WDR_CS_EN_PRE); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_BLBACK_WDR_CS_EN_PRE); - } - - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_CS_0, tmpVal); -} - -void DSP2_WDR_Set_CS_Config(const DSP2_Chroma_Suppress_Type *chromaSupprCfg) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_WDR_CS_GAIN_PRE, chromaSupprCfg->gain); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_0, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_CS_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_WDR_CS_WEIGHT_PRE, chromaSupprCfg->weight); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_WDR_CS_GREY_TH_PRE, chromaSupprCfg->gain_thresh); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_CS_0, tmpVal); -} - -void DSP2_WDR_Get_CS_Config(DSP2_Chroma_Suppress_Type *chromaSupprCfg) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_0); - chromaSupprCfg->gain = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_WDR_CS_GAIN_PRE); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_CS_0); - chromaSupprCfg->weight = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_WDR_CS_WEIGHT_PRE); - chromaSupprCfg->gain_thresh = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_WDR_CS_GREY_TH_PRE); -} - -void DSP2_WDR_Set_ROI_State(int roi_id, BL_Fun_Type state) -{ - uint32_t tmpVal; - - switch (roi_id) { - case 0: - case 1: - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_1); - - if (roi_id & 0x01) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_ROI1_EN_PRE, state); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_ROI0_EN_PRE, state); - } - - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_1, tmpVal); - break; - - case 2: - case 3: - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_2); - - if (roi_id & 0x01) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_ROI3_EN_PRE, state); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_ROI2_EN_PRE, state); - } - - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_2, tmpVal); - break; - - case 4: - case 5: - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_3); - - if (roi_id & 0x01) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_ROI5_EN_PRE, state); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_ROI4_EN_PRE, state); - } - - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_3, tmpVal); - break; - - case 6: - case 7: - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_4); - - if (roi_id & 0x01) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_ROI7_EN_PRE, state); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_ROI6_EN_PRE, state); - } - - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_4, tmpVal); - break; - - default: - break; - } -} - -void DSP2_WDR_Set_ROI_Position(int roi_id, uint32_t left_x, uint32_t right_x, - uint32_t top_y, uint32_t bottom_y) -{ - uint32_t tmpVal; - - switch (roi_id) { - case 0: - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_5); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_X0_MIN_PRE, left_x); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_X0_MAX_PRE, right_x); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_5, tmpVal); - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_6); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_Y0_MIN_PRE, top_y); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_Y0_MAX_PRE, bottom_y); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_6, tmpVal); - break; - - case 1: - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_7); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_X1_MIN_PRE, left_x); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_X1_MAX_PRE, right_x); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_7, tmpVal); - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_8); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_Y1_MIN_PRE, top_y); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_Y1_MAX_PRE, bottom_y); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_8, tmpVal); - break; - - case 2: - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_9); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_X2_MIN_PRE, left_x); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_X2_MAX_PRE, right_x); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_9, tmpVal); - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_10); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_Y2_MIN_PRE, top_y); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_Y2_MAX_PRE, bottom_y); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_10, tmpVal); - break; - - case 3: - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_11); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_X3_MIN_PRE, left_x); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_X3_MAX_PRE, right_x); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_11, tmpVal); - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_12); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_Y3_MIN_PRE, top_y); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_Y3_MAX_PRE, bottom_y); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_12, tmpVal); - break; - - case 4: - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_13); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_X4_MIN_PRE, left_x); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_X4_MAX_PRE, right_x); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_13, tmpVal); - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_14); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_Y4_MIN_PRE, top_y); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_Y4_MAX_PRE, bottom_y); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_14, tmpVal); - break; - - case 5: - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_15); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_X5_MIN_PRE, left_x); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_X5_MAX_PRE, right_x); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_15, tmpVal); - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_16); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_Y5_MIN_PRE, top_y); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_Y5_MAX_PRE, bottom_y); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_16, tmpVal); - break; - - case 6: - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_17); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_X6_MIN_PRE, left_x); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_X6_MAX_PRE, right_x); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_17, tmpVal); - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_18); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_Y6_MIN_PRE, top_y); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_Y6_MAX_PRE, bottom_y); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_18, tmpVal); - break; - - case 7: - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_19); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_X7_MIN_PRE, left_x); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_X7_MAX_PRE, right_x); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_19, tmpVal); - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_20); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_Y7_MIN_PRE, top_y); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_Y7_MAX_PRE, bottom_y); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_20, tmpVal); - break; - - default: - break; - } -} - -void DSP2_WDR_Set_ROI_Weight(int roi_id, uint32_t weight) -{ - uint32_t tmpVal; - - CHECK_PARAM_MAX(weight, DSP2_WDR_ROI_WEIGHT_MAX); - - switch (roi_id) { - case 0: - case 1: - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_1); - - if (roi_id & 0x01) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_ROI1_WEIGHT_PRE, weight); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_ROI0_WEIGHT_PRE, weight); - } - - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_1, tmpVal); - break; - - case 2: - case 3: - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_2); - - if (roi_id & 0x01) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_ROI3_WEIGHT_PRE, weight); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_ROI2_WEIGHT_PRE, weight); - } - - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_2, tmpVal); - break; - - case 4: - case 5: - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_3); - - if (roi_id & 0x01) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_ROI5_WEIGHT_PRE, weight); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_ROI4_WEIGHT_PRE, weight); - } - - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_3, tmpVal); - break; - - case 6: - case 7: - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_4); - - if (roi_id & 0x01) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_ROI7_WEIGHT_PRE, weight); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_ROI6_WEIGHT_PRE, weight); - } - - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_4, tmpVal); - break; - - default: - break; - } -} - -int DSP2_WDR_Get_Hist_Data(DSP2_WDR_Hist_Data_Type *hist) -{ - uint32_t tmpVal; - uint32_t buf_idx; - uint32_t buf_addr; - uint32_t w_cnt_idx_start; - uint32_t w_cnt_idx_end; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_0); - buf_idx = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_BLWDR_BUF_IDX_R); - w_cnt_idx_start = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_BLWDR_W_CNT_R); - - if (0 == buf_idx) { - buf_addr = DSP2_BASE + DSP2_BLBACK_REG_HIST0_0_OFFSET; - hist->hist_bin[64] = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_REG_HIST0_64); - } else { - buf_addr = DSP2_BASE + DSP2_BLBACK_REG_HIST1_0_OFFSET; - hist->hist_bin[64] = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_REG_HIST1_64); - } - - /* copy all the histogram bin except for the last one */ - ARCH_MemCpy4(&hist->hist_bin[0], (uint32_t *)(uintptr_t)buf_addr, 64); - - w_cnt_idx_end = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_BLWDR_W_CNT_R); - - if (w_cnt_idx_start != w_cnt_idx_end) { - return -1; - } - - return 0; -} - -void DSP2_WDR_Set_WDR_Curve_State(BL_Fun_Type state) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_CURVE_33); - - if (ENABLE == state) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_BLBACK_CURVE_EN_PRE); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_BLBACK_CURVE_EN_PRE); - } - - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_CURVE_33, tmpVal); -} - -void DSP2_WDR_Set_WDR_Curve(const DSP2_WDR_Curve_Type *wdr_curve) -{ - ARCH_MemCpy4((uint32_t *)(DSP2_BASE + DSP2_BLBACK_WDR_CURVE_1_OFFSET), (uint32_t *)&wdr_curve->curve_coef[0], DSP2_WDR_CURVE_COEF_NUM / 2); -} - -void DSP2_WDR_Get_WDR_Curve(DSP2_WDR_Curve_Type *wdr_curve) -{ - ARCH_MemCpy4((uint32_t *)&wdr_curve->curve_coef[0], (uint32_t *)(DSP2_BASE + DSP2_BLBACK_WDR_CURVE_1_OFFSET), DSP2_WDR_CURVE_COEF_NUM / 2); -} - -void DSP2_WDR_Set_WDR_Curve_Weight(uint32_t weight) -{ - uint32_t tmpVal; - - CHECK_PARAM_MAX(weight, DSP2_WDR_CURVE_WEIGHT_MAX); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_CURVE_33); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CURVE_WEIGHT_PRE, weight); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_CURVE_33, tmpVal); -} - -void DSP2_WDR_Get_WDR_Curve_Weight(uint32_t *weight) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_CURVE_33); - *weight = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CURVE_WEIGHT_PRE); -} - -void DSP2_WDR_Set_Post_Enhance_State(BL_Fun_Type state) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_ENH_1); - - if (ENABLE == state) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_BLBACK_ENH_EN_PRE); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_BLBACK_ENH_EN_PRE); - } - - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_ENH_1, tmpVal); -} - -void DSP2_WDR_Set_Post_Enhance_Weight(uint32_t weight) -{ - uint32_t tmpVal; - - CHECK_PARAM_MAX(weight, DSP2_WDR_CURVE_WEIGHT_MAX); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_ENH_1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_ENH_WEIGHT_PRE, weight); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_ENH_1, tmpVal); -} - -void DSP2_WDR_Get_Post_Enhance_Weight(uint32_t *weight) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_ENH_1); - *weight = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_ENH_WEIGHT_PRE); -} - -void DSP2_WDR_Set_Post_Enhance_Y_Offset(uint32_t y_offset) -{ - uint32_t tmpVal; - - CHECK_PARAM_MAX(y_offset, DSP2_WDR_POST_ENHANCE_Y_OFFSET_MAX); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_ENH_1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_ENH_Y_OFFSET_PRE, y_offset); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_ENH_1, tmpVal); -} - -void DSP2_WDR_Get_Post_Enhance_Y_Offset(uint32_t *y_offset) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_ENH_1); - *y_offset = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_ENH_Y_OFFSET_PRE); -} - -void DSP2_WDR_Set_Post_Enhance_Luma_Gain(uint32_t gain) -{ - uint32_t tmpVal; - - CHECK_PARAM_MAX(gain, DSP2_WDR_POST_ENHANCE_Y_GAIN_MAX); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_ENH_2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_ENH_Y_GAIN_PRE, gain); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_ENH_2, tmpVal); -} - -void DSP2_WDR_Get_Post_Enhance_Luma_Gain(uint32_t *gain) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_ENH_2); - *gain = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_ENH_Y_GAIN_PRE); -} - -void DSP2_WDR_Set_Post_Enhance_Chroma_Gain(uint32_t gain) -{ - uint32_t tmpVal; - - CHECK_PARAM_MAX(gain, DSP2_WDR_POST_ENHANCE_C_GAIN_MAX); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_ENH_2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_ENH_C_GAIN_PRE, gain); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_ENH_2, tmpVal); -} - -void DSP2_WDR_Get_Post_Enhance_Chroma_Gain(uint32_t *gain) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_ENH_2); - *gain = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_ENH_C_GAIN_PRE); -} - -/*@} end of group DSP2_WDR_Public_Functions */ - -/*@} end of group DSP2_WDR */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dvp_tsrc.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dvp_tsrc.c deleted file mode 100644 index 1be3c39d98..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dvp_tsrc.c +++ /dev/null @@ -1,394 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_dvp_tsrc.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_dvp_tsrc.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup DVP_TSRC - * @{ - */ - -/** @defgroup DVP_TSRC_Private_Macros - * @{ - */ - -/*@} end of group DVP_TSRC_Private_Macros */ - -/** @defgroup DVP_TSRC_Private_Types - * @{ - */ - -/*@} end of group DVP_TSRC_Private_Types */ - -/** @defgroup DVP_TSRC_Private_Variables - * @{ - */ -static const uint32_t dvpTsrcAddr[DVP_TSRC_ID_MAX] = { DVP_TSRC0_BASE, DVP_TSRC1_BASE }; - -/*@} end of group DVP_TSRC_Private_Variables */ - -/** @defgroup DVP_TSRC_Global_Variables - * @{ - */ - -/*@} end of group DVP_TSRC_Global_Variables */ - -/** @defgroup DVP_TSRC_Private_Fun_Declaration - * @{ - */ - -/*@} end of group DVP_TSRC_Private_Fun_Declaration */ - -/** @defgroup DVP_TSRC_Private_Functions - * @{ - */ - -/*@} end of group DVP_TSRC_Private_Functions */ - -/** @defgroup DVP_TSRC_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief DVP_TSRC init - * - * @param tsrcId: DVP_TSRC ID type - * @param dvpTsrcCfg: DVP_TSRC configuration - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type DVP_TSRC_Init(DVP_TSRC_ID_Type tsrcId, DVP_TSRC_Cfg_Type *dvpTsrcCfg) -{ - uint32_t tmpVal; - uint32_t dvpTsrcX = dvpTsrcAddr[tsrcId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DVP_TSRC_ID_TYPE(tsrcId)); - CHECK_PARAM(IS_DVP_TSRC_PIXEL_FORMAT_TYPE(dvpTsrcCfg->format)); - CHECK_PARAM(IS_DVP_TSRC_DVP2AXI_TYPE(dvpTsrcCfg->dvp2axi)); - CHECK_PARAM(IS_DVP_TSRC_SWAP_CONTROL_TYPE(dvpTsrcCfg->swapControl)); - CHECK_PARAM(IS_DVP_TSRC_BURST_TYPE(dvpTsrcCfg->burst)); - CHECK_PARAM(IS_DVP_TSRC_YUV420_LINE_TYPE(dvpTsrcCfg->lineType)); - - /* Enable using AXI data */ - tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, DTSRC_CR_MODE_CEA_861); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_AXI_SWAP_MODE, dvpTsrcCfg->swapMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_AXI_SWAP_IDX_SWM, dvpTsrcCfg->swapControl); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_AXI_SWAP_IDX_SEL, dvpTsrcCfg->dvp2axi); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_AXI_DVP_DATA_MODE, dvpTsrcCfg->format); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_SNSR_EN, dvpTsrcCfg->dataFromSensor); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_SNSR_HSYNC_INV, dvpTsrcCfg->sensorHsyncInverse); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_SNSR_VSYNC_INV, dvpTsrcCfg->sensorVsyncInverse); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_AXI_B0_SEL, dvpTsrcCfg->byte0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_AXI_B1_SEL, dvpTsrcCfg->byte1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_AXI_B2_SEL, dvpTsrcCfg->byte2); - tmpVal = BL_SET_REG_BIT(tmpVal, DTSRC_CR_AXI_EN); - BL_WR_REG(dvpTsrcX, DTSRC_CONFIG, tmpVal); - - /* Set burst length */ - tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_AXI2DVP_SETTING); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_AXI_420_MODE, dvpTsrcCfg->yuv420Enable); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_AXI_420_UD_SEL, dvpTsrcCfg->lineType); - BL_WR_REG(dvpTsrcX, DTSRC_AXI2DVP_SETTING, BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_AXI_XLEN, dvpTsrcCfg->burst)); - - /* Set horizontal pixel count */ - tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_FRAME_SIZE_H); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_TOTAL_H, dvpTsrcCfg->hTotalCnt); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_BLANK_H, dvpTsrcCfg->hBlankCnt); - BL_WR_REG(dvpTsrcX, DTSRC_FRAME_SIZE_H, tmpVal); - - /* Set vertical pixel count */ - tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_FRAME_SIZE_V); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_TOTAL_V, dvpTsrcCfg->vTotalCnt); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_BLANK_V, dvpTsrcCfg->vBlankCnt); - BL_WR_REG(dvpTsrcX, DTSRC_FRAME_SIZE_V, tmpVal); - - /* Set vertical prefetch start position */ - tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_AXI2DVP_PREFETCH); - BL_WR_REG(dvpTsrcX, DTSRC_AXI2DVP_PREFETCH, BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_PREFETCH_V, dvpTsrcCfg->prefetch)); - - /* Set fifo threshold for each DVP line to start to output */ - tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_SNSR2DVP_WAIT_POS); - BL_WR_REG(dvpTsrcX, DTSRC_SNSR2DVP_WAIT_POS, BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_SNSR_FIFO_TH, dvpTsrcCfg->fifoThreshold)); - - /* Set axi2dvp start address, Y planar in YUV420 mode, frame 0 in swap mode */ - BL_WR_REG(dvpTsrcX, DTSRC_AXI2DVP_START_ADDR_BY, dvpTsrcCfg->memStartY0); - - /* Set axi2dvp memory size in burst */ - switch (dvpTsrcCfg->burst) { - case DVP_TSRC_BURST_TYPE_SINGLE: - tmpVal = dvpTsrcCfg->memSizeY0 / 8; - break; - - case DVP_TSRC_BURST_TYPE_INCR4: - tmpVal = dvpTsrcCfg->memSizeY0 / 32; - break; - - case DVP_TSRC_BURST_TYPE_INCR8: - tmpVal = dvpTsrcCfg->memSizeY0 / 64; - break; - - case DVP_TSRC_BURST_TYPE_INCR16: - tmpVal = dvpTsrcCfg->memSizeY0 / 128; - break; - - case DVP_TSRC_BURST_TYPE_INCR32: - tmpVal = dvpTsrcCfg->memSizeY0 / 256; - break; - - case DVP_TSRC_BURST_TYPE_INCR64: - tmpVal = dvpTsrcCfg->memSizeY0 / 512; - break; - - default: - tmpVal = 0; - break; - } - - BL_WR_REG(dvpTsrcX, DTSRC_AXI2DVP_BURST_CNT, tmpVal); - - /* Set axi2dvp start address, Y planar in YUV420 mode, frame 1 in swap mode */ - BL_WR_REG(dvpTsrcX, DTSRC_AXI2DVP_SWAP_ADDR_BY, dvpTsrcCfg->memStartY1); - - /* Set axi2dvp start address, UV planar in YUV420 mode, frame 0 in swap mode */ - BL_WR_REG(dvpTsrcX, DTSRC_AXI2DVP_START_ADDR_UV, dvpTsrcCfg->memStartUV0); - - /* Set axi2dvp start address, UV planar in YUV420 mode, frame 1 in swap mode */ - BL_WR_REG(dvpTsrcX, DTSRC_AXI2DVP_SWAP_ADDR_UV, dvpTsrcCfg->memStartUV1); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Use fake gradient data function init - * - * @param tsrcId: DVP_TSRC ID type - * @param dataCfg: Fake gradient data configuration structure pointer - * - * @return None - * -*******************************************************************************/ -void DVP_TSRC_Fake_Data_Init(DVP_TSRC_ID_Type tsrcId, DVP_TSRC_Fake_Data_Cfg_Type *dataCfg) -{ - uint32_t tmpVal; - uint32_t dvpTsrcX = dvpTsrcAddr[tsrcId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DVP_TSRC_ID_TYPE(tsrcId)); - - /* Enable using fake gradient data */ - tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_CONFIG); - BL_WR_REG(dvpTsrcX, DTSRC_CONFIG, BL_CLR_REG_BIT(tmpVal, DTSRC_CR_AXI_EN)); - - /* Set min and max value of fake gradient data */ - tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_PIX_DATA_RANGE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_DATA_MIN, dataCfg->minData); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_DATA_MAX, dataCfg->maxData); - BL_WR_REG(dvpTsrcX, DTSRC_PIX_DATA_RANGE, tmpVal); - - /* Set step value for eack line of fake gradient data */ - tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_PIX_DATA_STEP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_DATA_STEP, dataCfg->step); - BL_WR_REG(dvpTsrcX, DTSRC_PIX_DATA_STEP, tmpVal); -} - -/****************************************************************************/ /** - * @brief CEA-861 mode init - * - * @param tsrcId: DVP_TSRC ID type - * @param ceaCfg: CEA-861 configuration structure pointer - * - * @return None - * -*******************************************************************************/ -void DVP_TSRC_CEA861_Init(DVP_TSRC_ID_Type tsrcId, DVP_TSRC_CEA861_Cfg_Type *ceaCfg) -{ - uint32_t tmpVal; - uint32_t dvpTsrcX = dvpTsrcAddr[tsrcId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DVP_TSRC_ID_TYPE(tsrcId)); - - tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_CONFIG); - BL_WR_REG(dvpTsrcX, DTSRC_CONFIG, BL_SET_REG_BIT(tmpVal, DTSRC_CR_MODE_CEA_861)); - - tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_FRAME_SIZE_CEA_861); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_H_PLACEMENT, ceaCfg->hsyncStart); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_H_DURATION, ceaCfg->hsyncEnd); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_V_PLACEMENT, ceaCfg->vsyncStart); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_V_DURATION, ceaCfg->vsyncEnd); - BL_WR_REG(dvpTsrcX, DTSRC_FRAME_SIZE_CEA_861, tmpVal); -} - -/****************************************************************************/ /** - * @brief Sensor input configuration - * - * @param tsrcId: DVP_TSRC ID type - * @param threshold: FIFO threshold for each DVP line to start to output - * @param hsyncInv:Enable or disable inverse signal of sensor hsync - * @param vsyncInv:Enable or disable inverse signal of sensor vsync - * - * @return None - * -*******************************************************************************/ -void DVP_TSRC_Sensor_Input_Set(DVP_TSRC_ID_Type tsrcId, uint16_t threshold, BL_Fun_Type hsyncInv, BL_Fun_Type vsyncInv) -{ - uint32_t tmpVal; - uint32_t dvpTsrcX = dvpTsrcAddr[tsrcId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DVP_TSRC_ID_TYPE(tsrcId)); - - tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, DTSRC_CR_SNSR_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_SNSR_HSYNC_INV, hsyncInv); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_SNSR_VSYNC_INV, vsyncInv); - BL_WR_REG(dvpTsrcX, DTSRC_CONFIG, tmpVal); - - /* Set fifo threshold for each DVP line to start to output */ - tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_SNSR2DVP_WAIT_POS); - BL_WR_REG(dvpTsrcX, DTSRC_SNSR2DVP_WAIT_POS, BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_SNSR_FIFO_TH, threshold)); -} - -/****************************************************************************/ /** - * @brief DVP_TSRC enable - * - * @param tsrcId: DVP_TSRC ID type - * - * @return None - * -*******************************************************************************/ -void DVP_TSRC_Enable(DVP_TSRC_ID_Type tsrcId) -{ - uint32_t tmpVal; - uint32_t dvpTsrcX = dvpTsrcAddr[tsrcId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DVP_TSRC_ID_TYPE(tsrcId)); - - tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_CONFIG); - BL_WR_REG(dvpTsrcX, DTSRC_CONFIG, BL_SET_REG_BIT(tmpVal, DTSRC_CR_ENABLE)); -} - -/****************************************************************************/ /** - * @brief DVP_TSRC disable - * - * @param tsrcId: DVP_TSRC ID type - * - * @return None - * -*******************************************************************************/ -void DVP_TSRC_Disable(DVP_TSRC_ID_Type tsrcId) -{ - uint32_t tmpVal; - uint32_t dvpTsrcX = dvpTsrcAddr[tsrcId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DVP_TSRC_ID_TYPE(tsrcId)); - - tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_CONFIG); - BL_WR_REG(dvpTsrcX, DTSRC_CONFIG, BL_CLR_REG_BIT(tmpVal, DTSRC_CR_ENABLE)); -} - -/****************************************************************************/ /** - * @brief DVP_TSRC set swap index in software mode - * - * @param tsrcId: DVP_TSRC ID type - * @param index: Swap index used - * - * @return None - * -*******************************************************************************/ -void DVP_TSRC_Set_Swap_Index(DVP_TSRC_ID_Type tsrcId, uint8_t index) -{ - uint32_t tmpVal; - uint32_t dvpTsrcX = dvpTsrcAddr[tsrcId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DVP_TSRC_ID_TYPE(tsrcId)); - - tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_CONFIG); - BL_WR_REG(dvpTsrcX, DTSRC_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_AXI_SWAP_IDX_SWV, index)); -} - -/****************************************************************************/ /** - * @brief AXI2DVP clear drain error function - * - * @param tsrcId: DVP_TSRC ID type - * - * @return None - * -*******************************************************************************/ -void DVP_TSRC_Clear_Drain_Error(DVP_TSRC_ID_Type tsrcId) -{ - uint32_t tmpVal; - uint32_t dvpTsrcX = dvpTsrcAddr[tsrcId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DVP_TSRC_ID_TYPE(tsrcId)); - - tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_AXI2DVP_SETTING); - BL_WR_REG(dvpTsrcX, DTSRC_AXI2DVP_SETTING, BL_SET_REG_BIT(tmpVal, DTSRC_CR_AXI_DRAIN_ERR_CLR)); -} - -/****************************************************************************/ /** - * @brief Get AXI2DVP status function - * - * @param tsrcId: DVP_TSRC ID type - * - * @return Status - * -*******************************************************************************/ -uint32_t DVP_TSRC_Get_Status(DVP_TSRC_ID_Type tsrcId) -{ - uint32_t dvpTsrcX = dvpTsrcAddr[tsrcId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DVP_TSRC_ID_TYPE(tsrcId)); - - return (BL_RD_REG(dvpTsrcX, DTSRC_AXI2DVP_STATUS)); -} - -/*@} end of group DVP_TSRC_Public_Functions */ - -/*@} end of group DVP_TSRC */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_ef_cfg.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_ef_cfg.c deleted file mode 100644 index 05c3efc134..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_ef_cfg.c +++ /dev/null @@ -1,610 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_ef_cfg.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "string.h" -#include "bl808_ef_ctrl.h" -#include "bl808_ef_cfg.h" -#include "ef_data_0_reg.h" -#include "ef_data_1_reg.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup SEC_EF_CTRL - * @{ - */ - -/** @defgroup SEC_EF_CTRL_Private_Macros - * @{ - */ -#define EF_CTRL_LOAD_BEFORE_READ_R0 EF_Ctrl_Load_Efuse_R0() -#define EF_CTRL_LOAD_BEFORE_READ_R1 EF_Ctrl_Load_Efuse_R1() - -/*@} end of group SEC_EF_CTRL_Private_Macros */ - -/** @defgroup SEC_EF_CTRL_Private_Types - * @{ - */ - -/*@} end of group SEC_EF_CTRL_Private_Types */ - -/** @defgroup SEC_EF_CTRL_Private_Variables - * @{ - */ - -/*@} end of group SEC_EF_CTRL_Private_Variables */ - -/** @defgroup SEC_EF_CTRL_Global_Variables - * @{ - */ - -/*@} end of group SEC_EF_CTRL_Global_Variables */ - -/** @defgroup SEC_EF_CTRL_Private_Fun_Declaration - * @{ - */ - -/*@} end of group SEC_EF_CTRL_Private_Fun_Declaration */ - -/** @defgroup SEC_EF_CTRL_Private_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Efuse get zero bit count - * - * @param val: Value to count - * - * @return Zero bit count - * -*******************************************************************************/ -static uint32_t EF_Cfg_Get_Byte_Zero_Cnt(uint8_t val) -{ - uint32_t cnt = 0; - uint32_t i = 0; - - for (i = 0; i < 8; i++) { - if ((val & (1 << i)) == 0) { - cnt += 1; - } - } - - return cnt; -} - -/****************************************************************************/ /** - * @brief Efuse get chip info - * - * @param chipInfo: info pointer - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Get_Chip_Info(Efuse_Chip_Info_Type *chipInfo) -{ - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH); - chipInfo->chipInfo = (tmpVal>>29)&0x7; - chipInfo->memoryInfo = (tmpVal>>27)&0x3; - chipInfo->psramInfo = (tmpVal>>25)&0x3; - chipInfo->deviceInfo = (tmpVal>>22)&0x7; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0); - chipInfo->psramInfo |= ((tmpVal>>20)&0x1) << 2; -} - -/****************************************************************************/ /** - * @brief Efuse read xtal trim rc32m configuration - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_LDO15RF_Vout_Sel(Efuse_Ana_LDO15RF_Vout_Sel_Type *trim) -{ - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_3); - trim->trimLDO15RFVoutAon = (tmpVal >> 27) & 0x07; - trim->trimLDO15RFVoutAonParity = (tmpVal >> 30) & 0x01; - trim->trimLDO15RFVoutAonEn = (tmpVal >> 31) & 0x01; -} - - -/****************************************************************************/ /** - * @brief Efuse read rcal iptat code configuration - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Rcal_Iptat_Code(Efuse_Ana_Rcal_Iptat_Code_Type *trim) -{ - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_3); - trim->trimRcalIptatCode = (tmpVal >> 22) & 0x1f; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W2); - trim->trimRcalIptatCodeParity = (tmpVal >> 30) & 0x01; - trim->trimRcalIptatCodeEn = (tmpVal >> 31) & 0x01; -} - -/****************************************************************************/ /** - * @brief Efuse read rcal icx code configuration - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Rcal_Icx_Code(Efuse_Ana_Rcal_Icx_Code_Type *trim) -{ - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W2); - trim->trimRcalIcxCode = (tmpVal >> 22) & 0x3f; - trim->trimRcalIcxCodeParity = (tmpVal >> 28) & 0x01; - trim->trimRcalIcxCodeEn = (tmpVal >> 29) & 0x01; -} - -/****************************************************************************/ /** - * @brief Efuse read LDO28CIS vout trim configuration - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_LDO28CIS_Vout_Trim(Efuse_Ana_LDO28CIS_Vout_Trim_Type *trim) -{ - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W3); - trim->trimLDO28CISVout = (tmpVal >> 8) & 0xf; - trim->trimLDO28CISVoutParity = (tmpVal >> 12) & 0x01; - trim->trimLDO28CISVoutEn = (tmpVal >> 13) & 0x01; -} - -/****************************************************************************/ /** - * @brief Efuse read LDO15CIS vout trim configuration - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_LDO15CIS_Vout_Trim(Efuse_Ana_LDO15CIS_Vout_Trim_Type *trim) -{ - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W3); - trim->trimLDO15CISVout = (tmpVal >> 8) & 0xf; - trim->trimLDO15CISVoutParity = (tmpVal >> 12) & 0x01; - trim->trimLDO15CISVoutEn = (tmpVal >> 13) & 0x01; -} - -/****************************************************************************/ /** - * @brief Efuse read LDO12UHS vout trim configuration - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_LDO12UHS_Vout_Trim(Efuse_Ana_LDO12UHS_Vout_Trim_Type *trim) -{ - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R1; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_KEY_SLOT_10_W3); - trim->trimLDO12UHSVout = (tmpVal >> 20) & 0xf; - trim->trimLDO12UHSVoutParity = (tmpVal >> 24) & 0x01; - trim->trimLDO12UHSVoutEn = (tmpVal >> 25) & 0x01; -} - -/****************************************************************************/ /** - * @brief Efuse read xtal capcode 1 inout configuration - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Xtal_Capcode1_Inout(Efuse_Ana_Xtal_Capcode_1_Type *trim) -{ - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R1; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_KEY_SLOT_10_W3); - trim->trimXtalCapcode1 = (tmpVal >> 0) & 0x3f; - trim->trimXtalCapcode1Parity = (tmpVal >> 6) & 0x01; - trim->trimXtalCapcode1En = (tmpVal >> 7) & 0x01; -} - -/****************************************************************************/ /** - * @brief Efuse read xtal capcode 2 inout configuration - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Xtal_Capcode2_Inout(Efuse_Ana_Xtal_Capcode_2_Type *trim) -{ - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R1; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_DAT_1_RSVD_1); - trim->trimXtalCapcode2 = (tmpVal >> 26) & 0x3f; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_DAT_1_RSVD_0); - trim->trimXtalCapcode2Parity = (tmpVal >> 30) & 0x01; - trim->trimXtalCapcode2En = (tmpVal >> 31) & 0x01; -} - -/****************************************************************************/ /** - * @brief Efuse read xtal capcode 3 inout configuration - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Xtal_Capcode3_Inout(Efuse_Ana_Xtal_Capcode_3_Type *trim) -{ - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R1; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_DAT_1_RSVD_1); - trim->trimXtalCapcode3 = (tmpVal >> 20) & 0x3f; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_DAT_1_RSVD_0); - trim->trimXtalCapcode3Parity = (tmpVal >> 28) & 0x01; - trim->trimXtalCapcode3En = (tmpVal >> 29) & 0x01; -} - -/****************************************************************************/ /** - * @brief Efuse read gauge vpack offset configuration - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Gauge_Vpack_Offset(Efuse_Ana_Gauge_Vpack_Offset_Type *trim) -{ - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R1; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_DAT_1_RSVD_1); - trim->trimGaugeVpackOffset = (tmpVal >> 2) & 0xffff; - trim->trimGaugeVpackOffsetParity = (tmpVal >> 18) & 0x01; - trim->trimGaugeVpackOffsetEn = (tmpVal >> 19) & 0x01; -} - -/****************************************************************************/ /** - * @brief Efuse read gauge vtemp offset configuration - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Gauge_Vtemp_Offset(Efuse_Ana_Gauge_Vtemp_Offset_Type *trim) -{ - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R1; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_DAT_1_RSVD_2); - trim->trimGaugeVtempOffset = (tmpVal >> 16) & 0xffff; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_DAT_1_RSVD_1); - trim->trimGaugeVtempOffsetParity = (tmpVal >> 0) & 0x01; - trim->trimGaugeVtempOffsetEn = (tmpVal >> 1) & 0x01; -} - -/****************************************************************************/ /** - * @brief Efuse read psram trim configuration - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Psram_Trim(Efuse_Psram_Trim_Type *trim) -{ - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R1; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_KEY_SLOT_10_W2); - trim->psramTrim = (tmpVal >> 0) & 0x7ff; - trim->psramTrimParity = (tmpVal >> 11) & 0x01; - trim->psramTrimEn = (tmpVal >> 12) & 0x01; -} - -/****************************************************************************/ /** - * @brief Efuse write psram trim configuration - * - * @param trim: Trim data pointer - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Write_Psram_Trim(Efuse_Psram_Trim_Type *trim, uint8_t program) -{ - uint32_t tmpVal; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_1(); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_KEY_SLOT_10_W2); - tmpVal |= (trim->psramTrim<<0); - tmpVal |= (trim->psramTrimParity<<11); - tmpVal |= (trim->psramTrimEn<<12); - BL_WR_REG(EF_DATA_BASE, EF_DATA_1_EF_KEY_SLOT_10_W2, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_1(); - } -} - -/****************************************************************************/ /** - * @brief Whether MAC address slot is empty - * - * @param slot: MAC address slot - * @param reload: whether reload to check - * - * @return 0 for all slots full,1 for others - * -*******************************************************************************/ -uint8_t EF_Ctrl_Is_MAC_Address_Slot_Empty(uint8_t slot, uint8_t reload) -{ - uint32_t tmp1 = 0xffffffff, tmp2 = 0xffffffff; - uint32_t part1Empty = 0, part2Empty = 0; - - if (slot == 0) { - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - if (reload) { - EF_CTRL_LOAD_BEFORE_READ_R0; - } - - tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW); - tmp2 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH); - } else if (slot == 1) { - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - if (reload) { - EF_CTRL_LOAD_BEFORE_READ_R0; - } - - tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_2); - tmp2 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_3); - } else if (slot == 2) { - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - if (reload) { - EF_CTRL_LOAD_BEFORE_READ_R0; - } - - tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W1); - tmp2 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W2); - } - - part1Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp1, 0, 32)); - part2Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp2, 0, 22)); - - return (part1Empty && part2Empty); -} - -/****************************************************************************/ /** - * @brief Efuse write optional MAC address - * - * @param slot: MAC address slot - * @param mac[6]: MAC address buffer - * @param program: Whether program - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EF_Ctrl_Write_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t program) -{ - uint8_t *maclow = (uint8_t *)mac; - uint8_t *machigh = (uint8_t *)(mac + 4); - uint32_t tmpVal; - uint32_t i = 0, cnt; - - if (slot >= 3) { - return ERROR; - } - - /* Change to local order */ - for (i = 0; i < 3; i++) { - tmpVal = mac[i]; - mac[i] = mac[5 - i]; - mac[5 - i] = tmpVal; - } - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - /* The low 32 bits */ - if (slot == 0) { - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW, BL_RDWD_FRM_BYTEP(maclow)); - } else if (slot == 1) { - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_2, BL_RDWD_FRM_BYTEP(maclow)); - } else if (slot == 2) { - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W1, BL_RDWD_FRM_BYTEP(maclow)); - } - - /* The high 16 bits */ - tmpVal = machigh[0] + (machigh[1] << 8); - cnt = 0; - - for (i = 0; i < 6; i++) { - cnt += EF_Cfg_Get_Byte_Zero_Cnt(mac[i]); - } - - tmpVal |= ((cnt & 0x3f) << 16); - - if (slot == 0) { - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH, tmpVal); - } else if (slot == 1) { - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_3, tmpVal); - } else if (slot == 2) { - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W2, tmpVal); - } - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Efuse read optional MAC address - * - * @param slot: MAC address slot - * @param mac[6]: MAC address buffer - * @param reload: Whether reload - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EF_Ctrl_Read_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t reload) -{ - uint8_t *maclow = (uint8_t *)mac; - uint8_t *machigh = (uint8_t *)(mac + 4); - uint32_t tmpVal = 0; - uint32_t i = 0; - uint32_t cnt = 0; - - if (slot >= 3) { - return ERROR; - } - - /* Trigger read data from efuse */ - if (reload) { - EF_CTRL_LOAD_BEFORE_READ_R0; - } - - if (slot == 0) { - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW); - } else if (slot == 1) { - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_2); - } else if (slot == 2) { - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W1); - } - - BL_WRWD_TO_BYTEP(maclow, tmpVal); - - if (slot == 0) { - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH); - } else if (slot == 1) { - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_3); - } else if (slot == 2) { - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W2); - } - - machigh[0] = tmpVal & 0xff; - machigh[1] = (tmpVal >> 8) & 0xff; - - /* Check parity */ - for (i = 0; i < 6; i++) { - cnt += EF_Cfg_Get_Byte_Zero_Cnt(mac[i]); - } - - if ((cnt & 0x3f) == ((tmpVal >> 16) & 0x3f)) { - /* Change to network order */ - for (i = 0; i < 3; i++) { - tmpVal = mac[i]; - mac[i] = mac[5 - i]; - mac[5 - i] = tmpVal; - } - - return SUCCESS; - } else { - return ERROR; - } -} - -/*@} end of group SEC_EF_CTRL_Public_Functions */ - -/*@} end of group SEC_EF_CTRL */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_ef_ctrl.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_ef_ctrl.c deleted file mode 100644 index 1a28966881..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_ef_ctrl.c +++ /dev/null @@ -1,1727 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_ef_ctrl.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "string.h" -#include "bl808_ef_ctrl.h" -#include "ef_data_0_reg.h" -#include "ef_data_1_reg.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup SEC_EF_CTRL - * @{ - */ - -/** @defgroup SEC_EF_CTRL_Private_Macros - * @{ - */ -#define EF_CTRL_EFUSE_CYCLE_PROTECT (0xbf << 24) -#define EF_CTRL_EFUSE_CTRL_PROTECT (0xbf << 8) -#define EF_CTRL_DFT_TIMEOUT_VAL (320 * 1000) -#ifndef BOOTROM -#define EF_CTRL_LOAD_BEFORE_READ_R0 EF_Ctrl_Load_Efuse_R0() -#define EF_CTRL_LOAD_BEFORE_READ_R1 EF_Ctrl_Load_Efuse_R1() -#else -#define EF_CTRL_LOAD_BEFORE_READ_R0 -#define EF_CTRL_LOAD_BEFORE_READ_R1 -#endif -#define EF_CTRL_DATA0_CLEAR EF_Ctrl_Clear(0, 0, EF_CTRL_EFUSE_R0_SIZE / 4) -#define EF_CTRL_DATA1_CLEAR EF_Ctrl_Clear(1, 0, EF_CTRL_EFUSE_R1_SIZE / 4) - -/*@} end of group SEC_EF_CTRL_Private_Macros */ - -/** @defgroup SEC_EF_CTRL_Private_Types - * @{ - */ - -/*@} end of group SEC_EF_CTRL_Private_Types */ - -/** @defgroup SEC_EF_CTRL_Private_Variables - * @{ - */ - -/*@} end of group SEC_EF_CTRL_Private_Variables */ - -/** @defgroup SEC_EF_CTRL_Global_Variables - * @{ - */ - -/*@} end of group SEC_EF_CTRL_Global_Variables */ - -/** @defgroup SEC_EF_CTRL_Private_Fun_Declaration - * @{ - */ - -/*@} end of group SEC_EF_CTRL_Private_Fun_Declaration */ - -/** @defgroup SEC_EF_CTRL_Private_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief get custom USB PID VID - * - * @param PID - * - * @param VID - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION EF_Ctrl_Get_Customer_PIDVID(uint16_t pid[1], uint16_t vid[1]) -{ - uint32_t tmpVal; - - EF_Ctrl_Read_Sw_Usage(4, &tmpVal); - - pid[0] = (uint16_t)(tmpVal & 0xFFFF); - vid[0] = (uint16_t)(tmpVal >> 16); - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Switch efuse region 0 control to AHB clock - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION EF_Ctrl_Sw_AHB_Clk_0(void) -{ - uint32_t tmpVal; - uint32_t timeout = EF_CTRL_DFT_TIMEOUT_VAL; - - while (EF_Ctrl_Busy() == SET) { - timeout--; - - if (timeout == 0) { - break; - } - } - - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (0 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_0_RW_POS) | - (0 << EF_CTRL_EF_IF_0_TRIG_POS); - - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Switch efuse region 1 control to AHB clock - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION EF_Ctrl_Sw_AHB_Clk_1(void) -{ - uint32_t tmpVal; - uint32_t timeout = EF_CTRL_DFT_TIMEOUT_VAL; - - while (EF_Ctrl_Busy() == SET) { - timeout--; - - if (timeout == 0) { - break; - } - } - - /* Note:ef_if_ctrl_1 has no EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS bit as ef_if_ctrl_0, - so we select it(them) in ef_if_ctrl_0 */ - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (0 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_0_RW_POS) | - (0 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); - - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_1_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_1_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_1_RW_POS) | - (0 << EF_CTRL_EF_IF_1_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_1, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Program efuse region 0 - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION EF_Ctrl_Program_Efuse_0(void) -{ - uint32_t tmpVal; - - /* Select auto mode and select ef clock */ - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (0 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_0_RW_POS) | - (0 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); - - /* Program */ - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (1 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (1 << EF_CTRL_EF_IF_0_RW_POS) | - (0 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); - - /* Add delay for POR to be stable */ - arch_delay_us(4); - - /* Trigger */ - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (1 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (1 << EF_CTRL_EF_IF_0_RW_POS) | - (1 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Program efuse region 1 - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION EF_Ctrl_Program_Efuse_1(void) -{ - uint32_t tmpVal; - - /* Select auto mode and select ef clock */ - /* Note:ef_if_ctrl_1 has no EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS bit as ef_if_ctrl_0, - so we select it(them) in ef_if_ctrl_0 */ - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (0 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_0_RW_POS) | - (0 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); - - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_1_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_1_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_1_RW_POS) | - (0 << EF_CTRL_EF_IF_1_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_1, tmpVal); - - /* Program */ - /* Note:ef_if_ctrl_1 has no EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS bit as ef_if_ctrl_0, - so we select it(them) in ef_if_ctrl_0 */ - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (1 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_0_RW_POS) | - (0 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); - - /* Add delay for POR to be stable */ - arch_delay_us(4); - - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_1_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_1_INT_CLR_POS) | - (1 << EF_CTRL_EF_IF_1_RW_POS) | - (0 << EF_CTRL_EF_IF_1_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_1, tmpVal); - - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_1_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_1_INT_CLR_POS) | - (1 << EF_CTRL_EF_IF_1_RW_POS) | - (1 << EF_CTRL_EF_IF_1_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_1, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Load efuse region 0 - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION EF_Ctrl_Load_Efuse_R0(void) -{ - uint32_t tmpVal; - uint32_t timeout = EF_CTRL_DFT_TIMEOUT_VAL; - - EF_CTRL_DATA0_CLEAR; - - /* Trigger read */ - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (0 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_0_RW_POS) | - (0 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); - - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (0 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_0_RW_POS) | - (1 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); - - arch_delay_us(10); - - /* Wait for efuse control idle */ - do { - tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0); - timeout--; - - if (timeout == 0) { - break; - } - } while (BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_0_BUSY) || - - (!BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_0_AUTOLOAD_DONE))); - - /* Switch to AHB clock */ - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (0 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_0_RW_POS) | - (0 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Load efuse region 1 - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void EF_Ctrl_Load_Efuse_R1(void) -{ - uint32_t tmpVal; - - EF_CTRL_DATA1_CLEAR; - - /* Trigger read */ - /* Note:ef_if_ctrl_1 has no EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS bit as ef_if_ctrl_0, - so we select it(them) in ef_if_ctrl_0 */ - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (0 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_0_RW_POS) | - (0 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); - - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_1_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_1_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_1_RW_POS) | - (0 << EF_CTRL_EF_IF_1_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_1, tmpVal); - - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_1_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_1_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_1_RW_POS) | - (1 << EF_CTRL_EF_IF_1_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_1, tmpVal); - - arch_delay_us(10); - - /* Wait for efuse control idle */ - do { - tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_1); - } while (BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_1_BUSY)); - - do { - tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0); - } while (!BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_0_AUTOLOAD_DONE)); - - /* Switch to AHB clock since often read efuse data after load */ - /* Note:ef_if_ctrl_1 has no EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS bit as ef_if_ctrl_0, - so we select it(them) in ef_if_ctrl_0 */ - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (0 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_0_RW_POS) | - (0 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); - - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_1_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_1_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_1_RW_POS) | - (0 << EF_CTRL_EF_IF_1_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_1, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Check efuse busy status - * - * @param None - * - * @return SET or RESET - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Sts_Type ATTR_TCM_SECTION EF_Ctrl_Busy(void) -{ - if (BL_IS_REG_BIT_SET(BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0), EF_CTRL_EF_IF_0_BUSY) || - BL_IS_REG_BIT_SET(BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_1), EF_CTRL_EF_IF_1_BUSY)) { - return SET; - } - - return RESET; -} -#endif - -/****************************************************************************/ /** - * @brief Check efuse whether finish loading - * - * @param None - * - * @return SET or RESET - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Sts_Type ATTR_TCM_SECTION EF_Ctrl_AutoLoad_Done(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0); - - if (BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_0_AUTOLOAD_DONE)) { - return SET; - } else { - return RESET; - } -} -#endif - -/****************************************************************************/ /** - * @brief Efuse write debug password - * - * @param slot: password slot0 or slot1 - * @param passWdLow: password low 32 bits - * @param passWdHigh: password high 32 bits - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Write_Dbg_Pwd(uint8_t slot, uint32_t passWdLow, uint32_t passWdHigh, uint8_t program) -{ - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - if (slot == 0) { - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_LOW, passWdLow); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH, passWdHigh); - } else if (slot == 1) { - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD2_LOW, passWdLow); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD2_HIGH, passWdHigh); - } - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse read debug password - * - * @param slot: password slot0 or slot1 - * @param passWdLow: password low 32 bits pointer to store value - * @param passWdHigh: password high 32 bits pointer to store value - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Dbg_Pwd(uint8_t slot, uint32_t *passWdLow, uint32_t *passWdHigh) -{ - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - if (slot == 0) { - *passWdLow = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_LOW); - *passWdHigh = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH); - } else if (slot == 1) { - *passWdLow = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD2_LOW); - *passWdHigh = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD2_HIGH); - } -} - -/****************************************************************************/ /** - * @brief Efuse lock reading for passwd - * - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Readlock_Dbg_Pwd(uint8_t program) -{ - uint32_t tmpVal; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); - tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_RD_LOCK_DBG_PWD); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse lock writing for passwd - * - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Writelock_Dbg_Pwd(uint8_t program) -{ - uint32_t tmpVal; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); - tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_WR_LOCK_DBG_PWD); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse read security configuration - * - * @param cfg: security configuration pointer - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Write_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg, uint8_t program) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_DBG_MODE, cfg->ef_dbg_mode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_DBG_JTAG_0_DIS, cfg->ef_dbg_jtag_0_dis); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_DBG_JTAG_1_DIS, cfg->ef_dbg_jtag_1_dis); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SBOOT_EN, cfg->ef_sboot_en); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse read security configuration - * - * @param cfg: security configuration pointer - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg) -{ - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0); - - cfg->ef_dbg_mode = (EF_Ctrl_Dbg_Mode_Type)BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_DBG_MODE); - cfg->ef_dbg_jtag_0_dis = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_DBG_JTAG_0_DIS); - cfg->ef_dbg_jtag_1_dis = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_DBG_JTAG_1_DIS); - cfg->ef_sboot_en = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SBOOT_EN); -} - -/****************************************************************************/ /** - * @brief Efuse write security boot configuration - * - * @param sign[1]: Sign configuration pointer - * @param aes[1]: AES configuration pointer - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Write_Secure_Boot(EF_Ctrl_Sign_Type sign[1], EF_Ctrl_SF_AES_Type aes[1], uint8_t program) -{ - uint32_t tmpVal; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - if (aes[0] != EF_CTRL_SF_AES_NONE) { - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SF_AES_MODE, aes[0]); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0, tmpVal); - } - - if (EF_CTRL_SIGN_NONE != sign[0]) { - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SBOOT_SIGN_MODE, sign[0]); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_0, tmpVal); - } - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse write security boot configuration - * - * @param aes[2]: AES configuration pointer - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Secure_Boot(EF_Ctrl_SF_AES_Type aes[2]) -{ - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0); - - aes[1] = aes[0] = (EF_Ctrl_SF_AES_Type)BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SF_AES_MODE); -} - -/****************************************************************************/ /** - * @brief Efuse read xtal trim rc32m configuration - * - * @param forceNoTrim: force no trim - * @param noXtal: no xtal - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Xtal_Trim_RC32M(uint8_t *forceNoTrim, uint8_t *noXtal) -{ - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0); - - *forceNoTrim = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_FORCE_NO_TRIM); - *noXtal = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_NO_XTAL); -} - -/****************************************************************************/ /** - * @brief Efuse Set sf key re sel - * - * @param ef_sf_key_re_sel: Efuse sf key re sel - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Set_sf_key_re_sel(uint8_t ef_sf_key_re_sel) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SF_KEY_RE_SEL, ef_sf_key_re_sel); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief Analog Trim parity calculate - * - * @param val: Value of efuse trim data - * @param len: Length of bit to calculate - * - * @return Parity bit value - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -uint8_t ATTR_CLOCK_SECTION EF_Ctrl_Get_Trim_Parity(uint32_t val, uint8_t len) -{ - uint8_t cnt = 0; - uint8_t i = 0; - - for (i = 0; i < len; i++) { - if (val & (1 << i)) { - cnt++; - } - } - - return cnt & 0x01; -} -#endif - -/****************************************************************************/ /** - * @brief Efuse read DCDC11 trim - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_CLOCK_SECTION EF_Ctrl_Read_DCDC11_Trim(Efuse_Ana_DCDC11_Trim_Type *trim) -{ - uint32_t tmpVal = 0; - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W3); - trim->trimDcdc11VoutAon = (tmpVal >> 26) & 0x0f; - trim->trimDcdc11VoutAonParity = (tmpVal >> 30) & 0x01; - trim->trimDcdc11VoutAonEn = (tmpVal >> 31) & 0x01; -} -#endif - -/****************************************************************************/ /** - * @brief Efuse read DCDC18 trim - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_CLOCK_SECTION EF_Ctrl_Read_DCDC18_Trim(Efuse_Ana_DCDC18_Trim_Type *trim) -{ - uint32_t tmpVal = 0; - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W3); - trim->trimDcdc18VoutAon = (tmpVal >> 20) & 0x0f; - trim->trimDcdc18VoutAonParity = (tmpVal >> 24) & 0x01; - trim->trimDcdc18VoutAonEn = (tmpVal >> 25) & 0x01; -} -#endif - -/****************************************************************************/ /** - * @brief Efuse read LDO18FLASH trim - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_CLOCK_SECTION EF_Ctrl_Read_LDO18FLASH_Trim(Efuse_Ana_LDO18FLASH_Trim_Type *trim) -{ - uint32_t tmpVal = 0; - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R1; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_KEY_SLOT_10_W3); - trim->trimLdo18flashVoutAon = (tmpVal >> 26) & 0x0f; - trim->trimLdo18flashVoutAonParity = (tmpVal >> 30) & 0x01; - trim->trimLdo18flashVoutAonEn = (tmpVal >> 31) & 0x01; -} -#endif - -/****************************************************************************/ /** - * @brief Efuse read USB20RCAL trim - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_CLOCK_SECTION EF_Ctrl_Read_USB20RCAL_Trim(Efuse_Ana_USB20RCAL_Trim_Type *trim) -{ - uint32_t tmpVal = 0; - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R1; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_DAT_1_RSVD_2); - trim->trimUsb20rcalAon = (tmpVal >> 8) & 0x3f; - trim->trimUsb20rcalAonParity = (tmpVal >> 14) & 0x01; - trim->trimUsb20rcalAonEn = (tmpVal >> 15) & 0x01; -} -#endif - -/****************************************************************************/ /** - * @brief Efuse read RC32M trim - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_CLOCK_SECTION EF_Ctrl_Read_RC32M_Trim(Efuse_Ana_RC32M_Trim_Type *trim) -{ - uint32_t tmpVal = 0; - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); - trim->trimRc32mCodeFrExt = (tmpVal >> 4) & 0xff; - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W3); - trim->trimRc32mCodeFrExtParity = (tmpVal >> 0) & 0x01; - trim->trimRc32mExtCodeEn = (tmpVal >> 1) & 0x01; -} -#endif - -/****************************************************************************/ /** - * @brief Efuse read RC32K trim - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_CLOCK_SECTION EF_Ctrl_Read_RC32K_Trim(Efuse_Ana_RC32K_Trim_Type *trim) -{ - uint32_t tmpVal = 0; - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_1(); - - EF_CTRL_LOAD_BEFORE_READ_R1; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_KEY_SLOT_10_W3); - trim->trimRc32kCodeFrExt = (tmpVal >> 8) & 0x3ff; - trim->trimRc32kCodeFrExtParity = (tmpVal >> 18) & 0x01; - trim->trimRc32kExtCodeEn = (tmpVal >> 19) & 0x01; -} -#endif - -/****************************************************************************/ /** - * @brief - * - * @param - * - * @return - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_CLOCK_SECTION EF_Ctrl_Read_LDO18IO_Vout_Trim(Efuse_Ana_LDO18IO_VOUT_Trim_Type *trim) -{ - uint32_t tmpVal = 0; - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W3); - trim->trimLdo18ioVoutVal = (tmpVal >> 14) & 0x0f; - trim->trimLdo18ioVoutParity = (tmpVal >> 18) & 0x01; - trim->trimLdo18ioVoutEn = (tmpVal >> 19) & 0x01; -} -#endif - -/****************************************************************************/ /** - * @brief Efuse read TSEN trim - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -void ATTR_CLOCK_SECTION EF_Ctrl_Read_TSEN_Trim(Efuse_TSEN_Refcode_Corner_Type *trim) -{ - uint32_t tmpVal = 0; - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_1(); - - EF_CTRL_LOAD_BEFORE_READ_R1; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_DAT_1_RSVD_0); - trim->tsenRefcodeCorner = (tmpVal >> 0) & 0xfff; - trim->tsenRefcodeCornerParity = (tmpVal >> 12) & 0x01; - trim->tsenRefcodeCornerEn = (tmpVal >> 13) & 0x01; -} - -/****************************************************************************/ /** - * @brief Efuse read ADC Gain trim - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -void ATTR_CLOCK_SECTION EF_Ctrl_Read_ADC_Gain_Trim(Efuse_ADC_Gain_Coeff_Type *trim) -{ - uint32_t tmpVal = 0; - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_1(); - - EF_CTRL_LOAD_BEFORE_READ_R1; - - tmpVal = BL_RD_REG(EF_DATA_BASE,EF_DATA_1_EF_DAT_1_RSVD_0); - trim->adcGainCoeff = (tmpVal >> 14) & 0xfff; - trim->adcGainCoeffParity = (tmpVal >> 26) & 0x01; - trim->adcGainCoeffEn = (tmpVal >> 27) & 0x01; -} - -/****************************************************************************/ /** - * @brief Efuse write software usage - * - * @param index: index of software usage - * @param usage: usage value - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Write_Sw_Usage(uint32_t index, uint32_t usage, uint8_t program) -{ - /* switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - switch (index) { - case 0: - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_0, usage); - break; - - case 1: - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_1, usage); - break; - - case 2: - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_2, usage); - break; - - case 3: - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_3, usage); - break; - - case 4: - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W0, usage); - break; - - default: - break; - } - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse read software usage - * - * @param index: index of software usage - * @param usage: usage value - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Sw_Usage(uint32_t index, uint32_t *usage) -{ - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R0; - - switch (index) { - case 0: - *usage = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_0); - break; - - case 1: - *usage = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_1); - break; - - case 2: - *usage = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_2); - break; - - case 3: - *usage = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_3); - break; - - case 4: - *usage = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W0); - break; - - default: - break; - } -} - -/****************************************************************************/ /** - * @brief Efuse read software usage - * - * @param index: index of software usage - * @param program: usage value - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Writelock_Sw_Usage(uint32_t index, uint8_t program) -{ - uint32_t tmpVal; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); - - if (index == 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_WR_LOCK_SW_USAGE_0); - } else if (index == 1) { - tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_WR_LOCK_SW_USAGE_1); - } else if (index == 2) { - tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_WR_LOCK_SW_USAGE_2); - } else if (index == 3) { - tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_WR_LOCK_SW_USAGE_3); - } - - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse write MAC address - * - * @param mac[6]: MAC address buffer - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Write_MAC_Address(uint8_t mac[6], uint8_t program) -{ - uint8_t *maclow = (uint8_t *)mac; - uint8_t *machigh = (uint8_t *)(mac + 4); - uint32_t tmpVal; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - /* The low 32 bits */ - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW, BL_RDWD_FRM_BYTEP(maclow)); - /* The high 16 bits */ - tmpVal = machigh[0] + (machigh[1] << 8); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse Ctrl get zero bit count - * - * @param val: Value to count - * - * @return Zero bit count - * -*******************************************************************************/ -static uint32_t EF_Ctrl_Get_Byte_Zero_Cnt(uint8_t val) -{ - uint32_t cnt = 0; - uint32_t i = 0; - - for (i = 0; i < 8; i++) { - if ((val & (1 << i)) == 0) { - cnt += 1; - } - } - - return cnt; -} - -/****************************************************************************/ /** - * @brief Efuse read MAC address - * - * @param mac[6]: MAC address buffer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EF_Ctrl_Read_MAC_Address(uint8_t mac[6]) -{ - uint8_t *maclow = (uint8_t *)mac; - uint8_t *machigh = (uint8_t *)(mac + 4); - uint32_t tmpVal; - uint32_t i = 0; - uint32_t cnt = 0; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW); - BL_WRWD_TO_BYTEP(maclow, tmpVal); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH); - machigh[0] = tmpVal & 0xff; - machigh[1] = (tmpVal >> 8) & 0xff; - - /* Check parity */ - for (i = 0; i < 6; i++) { - cnt += EF_Ctrl_Get_Byte_Zero_Cnt(mac[i]); - } - - if ((cnt & 0x3f) == ((tmpVal >> 16) & 0x3f)) { - /* Change to network order */ - for (i = 0; i < 3; i++) { - tmpVal = mac[i]; - mac[i] = mac[5 - i]; - mac[5 - i] = tmpVal; - } - - return SUCCESS; - } else { - return ERROR; - } -} - -/****************************************************************************/ /** - * @brief Efuse read MAC address - * - * @param mac[7]: MAC address buffer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EF_Ctrl_Read_MAC_Address_Raw(uint8_t mac[7]) -{ - uint8_t *maclow = (uint8_t *)mac; - uint8_t *machigh = (uint8_t *)(mac + 4); - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW); - BL_WRWD_TO_BYTEP(maclow, tmpVal); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH); - machigh[0] = tmpVal & 0xff; - machigh[1] = (tmpVal >> 8) & 0xff; - machigh[2] = (tmpVal >> 16) & 0xff; - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Efuse lock writing for MAC address - * - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Writelock_MAC_Address(uint8_t program) -{ - uint32_t tmpVal; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); - tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_WR_LOCK_WIFI_MAC); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Whether a value bits is all zero - * - * @param val: value to check - * @param start: start bit - * @param len: total length of bits to check - * - * @return 1 for all bits zero 0 for others - * -*******************************************************************************/ -uint8_t EF_Ctrl_Is_All_Bits_Zero(uint32_t val, uint8_t start, uint8_t len) -{ - uint32_t mask = 0; - - val = (val >> start); - - if (len >= 32) { - mask = 0xffffffff; - } else { - mask = (1 << len) - 1; - } - - if ((val & mask) == 0) { - return 1; - } else { - return 0; - } -} - -/****************************************************************************/ /** - * @brief Efuse read chip ID - * - * @param chipID[8]: Chip ID buffer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EF_Ctrl_Read_Chip_ID(uint8_t chipID[8]) -{ - chipID[6] = 0; - chipID[7] = 0; - return EF_Ctrl_Read_MAC_Address_Raw(chipID); -} - -/****************************************************************************/ /** - * @brief Efuse write AES key - * - * @param keyRegion: efuse key region - * @param index: index of key slot - * @param keyData: key data buffer - * @param len: key data length in words - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Write_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len, uint8_t program) -{ - uint32_t *pAESKeyStart0 = (uint32_t *)(EF_DATA_BASE + 0x1C); - uint32_t *pAESKeyStart1 = (uint32_t *)(EF_DATA_BASE + 0x80); - - /* slot_w0~slot_w3,slot_w11 in ef_data0 - slot_w4~slot_w10,in ef_data1 */ - - if ((index <= 3) || (index == 11)) { - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - index = ((index == 11) ? 5 : index); - - /* Every key is 4 words len*/ - - ARCH_MemCpy4(pAESKeyStart0 + index * 4, keyData, len); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } - } else if ((index < 11) && (index > 3)) { - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_1(); - - index = index - 4; - - /* Every key is 4 words len*/ - ARCH_MemCpy4(pAESKeyStart1 + index * 4, keyData, len); - - if (program) { - EF_Ctrl_Program_Efuse_1(); - } - } -} - -/****************************************************************************/ /** - * @brief Efuse read AES key from specified region and index - * - * @param keyRegion: efuse key region - * @param index: index of key slot - * @param keyData: key data buffer - * @param len: key data length in words - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len) -{ - uint32_t *pAESKeyStart0 = (uint32_t *)(EF_DATA_BASE + 0x1C); - uint32_t *pAESKeyStart1 = (uint32_t *)(EF_DATA_BASE + 0x80); - - if ((index <= 3) || (index == 11)) { - /* Trigger read data from efuse*/ - EF_CTRL_LOAD_BEFORE_READ_R0; - - index = ((index == 11) ? 5 : index); - - /* Every key is 4 words len*/ - ARCH_MemCpy4(keyData, pAESKeyStart0 + index * 4, len); - } else if ((index < 11) && (index > 3)) { - /* Trigger read data from efuse*/ - EF_CTRL_LOAD_BEFORE_READ_R1; - index = index - 4; - /* Every key is 4 words len*/ - ARCH_MemCpy4(keyData, pAESKeyStart1 + index * 4, len); - } -} - -/****************************************************************************/ /** - * @brief Efuse lock writing for aes key - * - * @param keyRegion: efuse key region - * @param index: index of key slot - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Writelock_AES_Key(uint8_t index, uint8_t program) -{ - uint32_t tmpVal; - - if ((index <= 3) || (index == 11)) { - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - index = ((index == 11) ? 8 : index); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); - tmpVal |= (1 << (index + 17)); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } - } else if ((index < 11) && (index > 3)) { - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_1(); - - index = index - 4; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_LOCK); - tmpVal |= (1 << (index + 15)); - BL_WR_REG(EF_DATA_BASE, EF_DATA_1_LOCK, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_1(); - } - } -} - -/****************************************************************************/ /** - * @brief Efuse lock reading for aes key - * - * @param keyRegion: efuse key region - * @param index: index of key slot - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Readlock_AES_Key(uint8_t index, uint8_t program) -{ - uint32_t tmpVal; - - if ((index <= 3) || (index == 11)) { - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - index = ((index == 11) ? 4 : index); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); - tmpVal |= (1 << (index + 27)); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } - } else if ((index < 11) && (index > 3)) { - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_1(); - - index = index - 4; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_LOCK); - tmpVal |= (1 << (index + 25)); - BL_WR_REG(EF_DATA_BASE, EF_DATA_1_LOCK, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_1(); - } - } -} - -/****************************************************************************/ /** - * @brief Program data to efuse region 0 - * - * @param index: index of efuse in word - * @param data: data buffer - * @param len: data length - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Program_Direct_R0(uint32_t index, uint32_t *data, uint32_t len) -{ - uint32_t *pEfuseStart0 = (uint32_t *)(EF_DATA_BASE + 0x00); - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - /* Add delay for CLK to be stable */ - arch_delay_us(4); - - if (data != NULL) { - ARCH_MemCpy4(pEfuseStart0 + index, data, len); - } - - EF_Ctrl_Program_Efuse_0(); -} - -/****************************************************************************/ /** - * @brief Program data to efuse region 1 - * - * @param index: index of efuse in word - * @param data: data buffer - * @param len: data length - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Program_Direct_R1(uint32_t index, uint32_t *data, uint32_t len) -{ - uint32_t *pEfuseStart1 = (uint32_t *)(EF_DATA_BASE + 0x80); - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_1(); - - /* Add delay for CLK to be stable */ - arch_delay_us(4); - - if (data != NULL) { - ARCH_MemCpy4(pEfuseStart1 + index, data, len); - } - - EF_Ctrl_Program_Efuse_1(); -} - -/****************************************************************************/ /** - * @brief Read data from efuse region 0 - * - * @param index: index of efuse in word - * @param data: data buffer - * @param len: data length - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Direct_R0(uint32_t index, uint32_t *data, uint32_t len) -{ - uint32_t *pEfuseStart0 = (uint32_t *)(EF_DATA_BASE + 0x00); - - EF_CTRL_LOAD_BEFORE_READ_R0; - - ARCH_MemCpy4(data, pEfuseStart0 + index, len); -} - -/****************************************************************************/ /** - * @brief Read data from efuse region 1 - * - * @param index: index of efuse in word - * @param data: data buffer - * @param len: data length - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Direct_R1(uint32_t index, uint32_t *data, uint32_t len) -{ - uint32_t *pEfuseStart1 = (uint32_t *)(EF_DATA_BASE + 0x80); - - EF_CTRL_LOAD_BEFORE_READ_R1; - - ARCH_MemCpy4(data, pEfuseStart1 + index, len); -} - -/****************************************************************************/ /** - * @brief Program data to efuse entity - * - * @param region: index of efuse region - * @param index: index of efuse in word - * @param data: data buffer - * @param len: data length - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Program_Direct(uint32_t region, uint32_t index, uint32_t *data, uint32_t len) -{ - if (region == 0) { - EF_Ctrl_Program_Direct_R0(index, data, len); - } else if (region == 1) { - EF_Ctrl_Program_Direct_R1(index, data, len); - } -} - -/****************************************************************************/ /** - * @brief Read efuse from register - * - * @param region: index of efuse region - * @param index: index of efuse in word - * @param data: data buffer - * @param len: data length - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Direct(uint32_t region, uint32_t index, uint32_t *data, uint32_t len) -{ - if (region == 0) { - EF_Ctrl_Read_Direct_R0(index, data, len); - } else if (region == 1) { - EF_Ctrl_Read_Direct_R1(index, data, len); - } -} - -/****************************************************************************/ /** - * @brief Clear efuse data register - * - * @param region: index efuse region - * @param index: index of efuse in word - * @param len: data length - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION EF_Ctrl_Clear(uint8_t region, uint32_t index, uint32_t len) -{ - uint32_t *pEfuseStart0 = (uint32_t *)(EF_DATA_BASE + 0x00); - uint32_t *pEfuseStart1 = (uint32_t *)(EF_DATA_BASE + 0x80); - uint32_t i = 0; - - if (region == 0) { - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - /* Clear data */ - for (i = 0; i < len; i++) { - pEfuseStart0[index + i] = 0; - } - } else if (region == 1) { - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_1(); - - /* Clear data */ - for (i = 0; i < len; i++) { - pEfuseStart1[index + i] = 0; - } - } -} -#endif - -/****************************************************************************/ /** - * @brief efuse ctrl crc enable - * - * @param None - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Crc_Enable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_CRC_CTRL_0); - tmpVal = BL_SET_REG_BIT(tmpVal, EF_CTRL_EF_CRC_TRIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_MODE); - tmpVal = BL_SET_REG_BIT(tmpVal, EF_CTRL_EF_CRC_DOUT_INV_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_DOUT_ENDIAN); - tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_DIN_ENDIAN); - tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_INT_CLR); - tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_INT_SET); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_CRC_CTRL_0, tmpVal); - - tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_CRC_CTRL_0); - tmpVal = BL_SET_REG_BIT(tmpVal, EF_CTRL_EF_CRC_EN); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_CRC_CTRL_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief efuse ctrl get crc busy status - * - * @param None - * - * @return DISABLE or ENABLE - * -*******************************************************************************/ -BL_Sts_Type EF_Ctrl_Crc_Is_Busy(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_CRC_CTRL_0); - return (BL_Sts_Type)BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_CRC_BUSY); -} - -/****************************************************************************/ /** - * @brief efuse ctrl set golden value - * - * @param goldenValue: Crc golden value - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Crc_Set_Golden(uint32_t goldenValue) -{ - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_CRC_CTRL_4, goldenValue); -} - -/****************************************************************************/ /** - * @brief efuse ctrl get crc result - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EF_Ctrl_Crc_Result(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_CRC_CTRL_0); - return (BL_Err_Type)BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_CRC_ERROR); -} - -/*@} end of group SEC_EF_CTRL_Public_Functions */ - -/*@} end of group SEC_EF_CTRL */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_emac.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_emac.c deleted file mode 100644 index 8c4a3e62cd..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_emac.c +++ /dev/null @@ -1,785 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_emac.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808.h" -#include "bl808_emac.h" -#include "bl808_glb.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup EMAC - * @{ - */ - -/** @defgroup EMAC_Private_Macros - * @{ - */ -#define PHY_MAX_RETRY (0x3F) - -/*@} end of group EMAC_Private_Macros */ - -/** @defgroup EMAC_Private_Types - * @{ - */ - -/*@} end of group EMAC_Private_Types */ - -/** @defgroup EMAC_Private_Variables - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -static intCallback_Type *emacIntCbfArra[EMAC_ID_MAX][EMAC_INT_CNT] = { {NULL} }; -#endif - -static const uint32_t emacAddr[EMAC_ID_MAX] = { EMAC_BASE }; - -/*@} end of group EMAC_Private_Variables */ - -/** @defgroup EMAC_Global_Variables - * @{ - */ - -/*@} end of group EMAC_Global_Variables */ - -/** @defgroup EMAC_Private_Fun_Declaration - * @{ - */ - -/*@} end of group EMAC_Private_Fun_Declaration */ - -/** @defgroup EMAC_Private_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Set MAC Address - * - * @param emacId: EMAC ID type - * @param macAddr[6]: MAC address buffer array - * - * @return None - * -*******************************************************************************/ -static void EMAC_SetMACAddress(EMAC_ID_Type emacId, uint8_t macAddr[6]) -{ - uint32_t EMACx = emacAddr[emacId]; - BL_WR_REG(EMACx, EMAC_MAC_ADDR1, (macAddr[0] << 8) | macAddr[1]); - BL_WR_REG(EMACx, EMAC_MAC_ADDR0, (macAddr[2] << 24) | (macAddr[3] << 16) | (macAddr[4] << 8) | (macAddr[5] << 0)); -} - -/****************************************************************************/ /** - * @brief Set PHY Address - * - * @param emacId: EMAC ID type - * @param phyAddress: Phy address - * - * @return None - * -*******************************************************************************/ -void EMAC_Phy_SetAddress(EMAC_ID_Type emacId, uint16_t phyAddress) -{ - uint32_t tmpVal; - uint32_t EMACx = emacAddr[emacId]; - - /* Set Phy Address */ - tmpVal = BL_RD_REG(EMACx, EMAC_MIIADDRESS); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_FIAD, phyAddress); - BL_WR_REG(EMACx, EMAC_MIIADDRESS, tmpVal); -} - -/****************************************************************************/ /** - * @brief Set PHY Address - * - * @param emacId: EMAC ID type - * @param phyAddress: Phy address - * - * @return None - * -*******************************************************************************/ -void EMAC_Phy_Set_Full_Duplex(EMAC_ID_Type emacId, uint8_t fullDuplex) -{ - uint32_t tmpVal; - uint32_t EMACx = emacAddr[emacId]; - - /* Set MAC duplex config */ - tmpVal = BL_RD_REG(EMACx, EMAC_MODE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_FULLD, fullDuplex); - BL_WR_REG(EMACx, EMAC_MODE, tmpVal); -} - -/****************************************************************************/ /** - * @brief Read PHY register - * - * @param emacId: EMAC ID type - * @param phyReg: PHY register - * @param regValue: PHY register value pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EMAC_Phy_Read(EMAC_ID_Type emacId, uint16_t phyReg, uint16_t *regValue) -{ - uint32_t tmpVal; - uint32_t EMACx = emacAddr[emacId]; - - /* Set Register Address */ - tmpVal = BL_RD_REG(EMACx, EMAC_MIIADDRESS); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_RGAD, phyReg); - BL_WR_REG(EMACx, EMAC_MIIADDRESS, tmpVal); - - /* Trigger read */ - tmpVal = BL_RD_REG(EMACx, EMAC_MIICOMMAND); - tmpVal = BL_SET_REG_BIT(tmpVal, EMAC_RSTAT); - BL_WR_REG(EMACx, EMAC_MIICOMMAND, tmpVal); - - BL_DRV_DUMMY; - - do { - tmpVal = BL_RD_REG(EMACx, EMAC_MIISTATUS); - arch_delay_us(16); - } while (BL_IS_REG_BIT_SET(tmpVal, EMAC_MIIM_BUSY)); - - *regValue = BL_RD_REG(EMACx, EMAC_MIIRX_DATA); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Write PHY register - * - * @param emacId: EMAC ID type - * @param phyReg: PHY register - * @param regValue: PHY register value - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EMAC_Phy_Write(EMAC_ID_Type emacId, uint16_t phyReg, uint16_t regValue) -{ - uint32_t tmpVal; - uint32_t EMACx = emacAddr[emacId]; - - /* Set Register Address */ - tmpVal = BL_RD_REG(EMACx, EMAC_MIIADDRESS); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_RGAD, phyReg); - BL_WR_REG(EMACx, EMAC_MIIADDRESS, tmpVal); - - /* Set Write data */ - BL_WR_REG(EMACx, EMAC_MIITX_DATA, regValue); - - /* Trigger write */ - tmpVal = BL_RD_REG(EMACx, EMAC_MIICOMMAND); - tmpVal = BL_SET_REG_BIT(tmpVal, EMAC_WCTRLDATA); - BL_WR_REG(EMACx, EMAC_MIICOMMAND, tmpVal); - - BL_DRV_DUMMY; - - do { - tmpVal = BL_RD_REG(EMACx, EMAC_MIISTATUS); - } while (BL_IS_REG_BIT_SET(tmpVal, EMAC_MIIM_BUSY)); - - return SUCCESS; -} - -/*@} end of group EMAC_Private_Functions */ - -/** @defgroup EMAC_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Initialize EMAC module - * - * @param emacId: EMAC ID type - * @param cfg: EMAC configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EMAC_Init(EMAC_ID_Type emacId, EMAC_CFG_Type *cfg) -{ - uint32_t tmpVal; - uint32_t EMACx = emacAddr[emacId]; - - /* Disable clock gate */ - //GLB_AHB_Slave2_Clock_Gate(DISABLE, BL_AHB_SLAVE2_EXT_EMAC); - - /* Set MAC config */ - tmpVal = BL_RD_REG(EMACx, EMAC_MODE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_RMII_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_RECSMALL, cfg->recvSmallFrame); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_PAD, cfg->padEnable); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_HUGEN, cfg->recvHugeFrame); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_CRCEN, cfg->crcEnable); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_NOPRE, cfg->noPreamble); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_BRO, cfg->recvBroadCast); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_PRO, ENABLE); - //tmpVal |= (1 << 7); /* local loopback in emac */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_IFG, cfg->interFrameGapCheck); - BL_WR_REG(EMACx, EMAC_MODE, tmpVal); - - /* Set inter frame gap value */ - BL_WR_REG(EMACx, EMAC_IPGT, cfg->interFrameGapValue); - - /* Set MII interface */ - tmpVal = BL_RD_REG(EMACx, EMAC_MIIMODE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_MIINOPRE, cfg->miiNoPreamble); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_CLKDIV, cfg->miiClkDiv); - BL_WR_REG(EMACx, EMAC_MIIMODE, tmpVal); - - /* Set collision */ - tmpVal = BL_RD_REG(EMACx, EMAC_COLLCONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_MAXRET, cfg->maxTxRetry); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_COLLVALID, cfg->collisionValid); - BL_WR_REG(EMACx, EMAC_COLLCONFIG, tmpVal); - - /* Set frame length */ - tmpVal = BL_RD_REG(EMACx, EMAC_PACKETLEN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_MINFL, cfg->minFrameLen); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_MAXFL, cfg->maxFrameLen); - BL_WR_REG(EMACx, EMAC_PACKETLEN, tmpVal); - - EMAC_SetMACAddress(emacId, cfg->macAddr); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(EMAC_IRQn, EMAC0_IRQHandler); -#endif - return SUCCESS; -} - -/****************************************************************************/ /** - - * @brief DeInitialize EMAC module - * - * @param emacId: EMAC ID type - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EMAC_DeInit(EMAC_ID_Type emacId) -{ - EMAC_Disable(emacId); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Initialize EMAC TX RX MDA buffer - * - * @param emacId: EMAC ID type - * @param handle: EMAC handle pointer - * @param txBuff: TX buffer - * @param txBuffCount: TX buffer count - * @param rxBuff: RX buffer - * @param rxBuffCount: RX buffer count - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EMAC_DMADescListInit(EMAC_ID_Type emacId, EMAC_Handle_Type *handle, uint8_t *txBuff, uint32_t txBuffCount, uint8_t *rxBuff, uint32_t rxBuffCount) -{ - uint32_t i = 0; - uint32_t EMACx = emacAddr[emacId]; - - /* Set the Ethernet handler env */ - handle->bd = (EMAC_BD_Desc_Type *)(uintptr_t)(EMACx + EMAC_DMA_DESC_OFFSET); - handle->txIndexEMAC = 0; - handle->txIndexCPU = 0; - handle->txBuffLimit = txBuffCount - 1; - /* The receive descriptors' address starts right after the last transmit BD. */ - handle->rxIndexEMAC = txBuffCount; - handle->rxIndexCPU = txBuffCount; - handle->rxBuffLimit = txBuffCount + rxBuffCount - 1; - - /* Fill each DMARxDesc descriptor with the right values */ - for (i = 0; i < txBuffCount; i++) { - /* Get the pointer on the ith member of the Tx Desc list */ - handle->bd[i].Buffer = (NULL == txBuff) ? 0 : (uint32_t)(uintptr_t)(txBuff + (ETH_MAX_PACKET_SIZE * i)); - handle->bd[i].C_S_L = 0; - } - - /* For the last TX DMA Descriptor, it should be wrap back */ - handle->bd[handle->txBuffLimit].C_S_L |= EMAC_BD_FIELD_MSK(TX_WR); - - for (i = txBuffCount; i < (txBuffCount + rxBuffCount); i++) { - /* Get the pointer on the ith member of the Rx Desc list */ - handle->bd[i].Buffer = (NULL == rxBuff) ? 0 : (uint32_t)(uintptr_t)(rxBuff + (ETH_MAX_PACKET_SIZE * (i - txBuffCount))); - handle->bd[i].C_S_L = (ETH_MAX_PACKET_SIZE << 16) | - EMAC_BD_FIELD_MSK(RX_IRQ) | - EMAC_BD_FIELD_MSK(RX_E); - } - - /* For the last RX DMA Descriptor, it should be wrap back */ - handle->bd[handle->rxBuffLimit].C_S_L |= EMAC_BD_FIELD_MSK(RX_WR); - - /* For the TX DMA Descriptor, it will wrap to 0 according to EMAC_TX_BD_NUM*/ - BL_WR_REG(EMACx, EMAC_TX_BD_NUM, txBuffCount); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Get TX MDA buffer descripter for data to send - * - * @param handle: EMAC handle pointer - * @param txDMADesc: TX DMA descriptor pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EMAC_DMATxDescGet(EMAC_Handle_Type *handle, EMAC_BD_Desc_Type **txDMADesc) -{ - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Start TX - * - * @param handle: EMAC handle pointer - * @param txDMADesc: TX DMA descriptor pointer - * @param len: len - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EMAC_StartTx(EMAC_Handle_Type *handle, EMAC_BD_Desc_Type *txDMADesc, uint32_t len) -{ - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Enable EMAC module - * - * @param emacId: EMAC ID type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EMAC_Enable(EMAC_ID_Type emacId) -{ - uint32_t tmpVal; - uint32_t EMACx = emacAddr[emacId]; - - /* Enable EMAC */ - tmpVal = BL_RD_REG(EMACx, EMAC_MODE); - tmpVal = BL_SET_REG_BIT(tmpVal, EMAC_TXEN); - tmpVal = BL_SET_REG_BIT(tmpVal, EMAC_RXEN); - BL_WR_REG(EMACx, EMAC_MODE, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief EMAC_Enable_TX - * - * @param emacId: EMAC ID type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EMAC_Enable_TX(EMAC_ID_Type emacId) -{ - uint32_t tmpVal; - uint32_t EMACx = emacAddr[emacId]; - - /* Enable EMAC */ - tmpVal = BL_RD_REG(EMACx, EMAC_MODE); - tmpVal = BL_SET_REG_BIT(tmpVal, EMAC_TXEN); - BL_WR_REG(EMACx, EMAC_MODE, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief EMAC_Disable_TX - * - * @param emacId: EMAC ID type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EMAC_Disable_TX(EMAC_ID_Type emacId) -{ - uint32_t tmpVal; - uint32_t EMACx = emacAddr[emacId]; - - /* Enable EMAC */ - tmpVal = BL_RD_REG(EMACx, EMAC_MODE); - tmpVal = BL_CLR_REG_BIT(tmpVal, EMAC_TXEN); - BL_WR_REG(EMACx, EMAC_MODE, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief EMAC_Enable_RX - * - * @param emacId: EMAC ID type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EMAC_Enable_RX(EMAC_ID_Type emacId) -{ - uint32_t tmpval; - uint32_t EMACx = emacAddr[emacId]; - - /* Enable EMAC TX*/ - tmpval = BL_RD_REG(EMACx, EMAC_MODE); - tmpval = BL_SET_REG_BIT(tmpval, EMAC_RXEN); - BL_WR_REG(EMACx, EMAC_MODE, tmpval); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief EMAC_Disable_RX - * - * @param emacId: EMAC ID type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EMAC_Disable_RX(EMAC_ID_Type emacId) -{ - uint32_t tmpval; - uint32_t EMACx = emacAddr[emacId]; - - /* Disable EMAC RX*/ - tmpval = BL_RD_REG(EMACx, EMAC_MODE); - tmpval = BL_CLR_REG_BIT(tmpval, EMAC_RXEN); - BL_WR_REG(EMACx, EMAC_MODE, tmpval); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Disable EMAC module - * - * @param emacId: EMAC ID type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EMAC_Disable(EMAC_ID_Type emacId) -{ - uint32_t tmpVal; - uint32_t EMACx = emacAddr[emacId]; - - /* Enable EMAC */ - tmpVal = BL_RD_REG(EMACx, EMAC_MODE); - tmpVal = BL_CLR_REG_BIT(tmpVal, EMAC_TXEN); - tmpVal = BL_CLR_REG_BIT(tmpVal, EMAC_RXEN); - BL_WR_REG(EMACx, EMAC_MODE, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief EMAC mask or unmask certain or all interrupt - * - * @param emacId: EMAC ID type - * @param intType: EMAC interrupt type - * @param intMask: EMAC interrupt mask value( MASK:disbale interrupt,UNMASK:enable interrupt ) - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EMAC_IntMask(EMAC_ID_Type emacId, EMAC_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpVal; - uint32_t EMACx = emacAddr[emacId]; - - /* Check the parameters */ - CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); - - tmpVal = BL_RD_REG(EMACx, EMAC_INT_MASK); - - /* Mask or unmask certain or all interrupt */ - if (MASK == intMask) { - tmpVal |= intType; - } else { - tmpVal &= (~intType); - } - - /* Write back */ - BL_WR_REG(EMACx, EMAC_INT_MASK, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Get EMAC interrupt status - * - * @param emacId: EMAC ID type - * @param intType: EMAC interrupt type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Sts_Type EMAC_GetIntStatus(EMAC_ID_Type emacId, EMAC_INT_Type intType) -{ - uint32_t tmpVal; - uint32_t EMACx = emacAddr[emacId]; - - /* Check the parameters */ - CHECK_PARAM(IS_EMAC_INT_TYPE(intType)); - - tmpVal = BL_RD_REG(EMACx, EMAC_INT_SOURCE); - - return (tmpVal & intType) ? SET : RESET; -} - -/****************************************************************************/ /** - * @brief Clear EMAC interrupt - * - * @param emacId: EMAC ID type - * @param intType: EMAC interrupt type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EMAC_ClrIntStatus(EMAC_ID_Type emacId, EMAC_INT_Type intType) -{ - uint32_t tmpVal; - uint32_t EMACx = emacAddr[emacId]; - - /* Check the parameters */ - CHECK_PARAM(IS_EMAC_INT_TYPE(intType)); - - tmpVal = BL_RD_REG(EMACx, EMAC_INT_SOURCE); - - BL_WR_REG(EMACx, EMAC_INT_SOURCE, tmpVal | intType); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief EMAC_Int_Callback_Install - * - * @param emacId: EMAC ID type - * @param intIdx: EMAC_INT_Index - * @param cbFun: call back - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -BL_Err_Type EMAC_Int_Callback_Install(EMAC_ID_Type emacId, EMAC_INT_Index intIdx, intCallback_Type *cbFun) -{ - /* Check the parameters */ - - emacIntCbfArra[emacId][intIdx] = cbFun; - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief EMAC_IRQHandler - * - * @param emacId: EMAC ID type - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void EMAC_IRQHandler(EMAC_ID_Type emacId) -{ - uint32_t tmpVal; - uint32_t EMACx = emacAddr[emacId]; - - tmpVal = BL_RD_REG(EMACx, EMAC_INT_MASK); - - if (SET == EMAC_GetIntStatus(emacId, EMAC_INT_TX_DONE) && !BL_IS_REG_BIT_SET(tmpVal, EMAC_TXB_M)) { - EMAC_ClrIntStatus(emacId, EMAC_INT_TX_DONE); - - if (emacIntCbfArra[emacId][EMAC_INT_TX_DONE_IDX]) { - emacIntCbfArra[emacId][EMAC_INT_TX_DONE_IDX](); - } - } - - if (SET == EMAC_GetIntStatus(emacId, EMAC_INT_TX_ERROR) && !BL_IS_REG_BIT_SET(tmpVal, EMAC_TXE_M)) { - EMAC_ClrIntStatus(emacId, EMAC_INT_TX_ERROR); - - if (emacIntCbfArra[emacId][EMAC_INT_TX_ERROR_IDX]) { - emacIntCbfArra[emacId][EMAC_INT_TX_ERROR_IDX](); - } - } - - if (SET == EMAC_GetIntStatus(emacId, EMAC_INT_RX_DONE) && !BL_IS_REG_BIT_SET(tmpVal, EMAC_RXB_M)) { - EMAC_ClrIntStatus(emacId, EMAC_INT_RX_DONE); - - if (emacIntCbfArra[emacId][EMAC_INT_RX_DONE_IDX]) { - emacIntCbfArra[emacId][EMAC_INT_RX_DONE_IDX](); - } - } - - if (SET == EMAC_GetIntStatus(emacId, EMAC_INT_RX_ERROR) && !BL_IS_REG_BIT_SET(tmpVal, EMAC_RXE_M)) { - EMAC_ClrIntStatus(emacId, EMAC_INT_RX_ERROR); - - if (emacIntCbfArra[emacId][EMAC_INT_RX_ERROR_IDX]) { - emacIntCbfArra[emacId][EMAC_INT_RX_ERROR_IDX](); - } - } - - if (SET == EMAC_GetIntStatus(emacId, EMAC_INT_RX_BUSY) && !BL_IS_REG_BIT_SET(tmpVal, EMAC_BUSY_M)) { - EMAC_ClrIntStatus(emacId, EMAC_INT_RX_BUSY); - - if (emacIntCbfArra[emacId][EMAC_INT_RX_BUSY_IDX]) { - emacIntCbfArra[emacId][EMAC_INT_RX_BUSY_IDX](); - } - } - - if (SET == EMAC_GetIntStatus(emacId, EMAC_INT_TX_CTRL) && !BL_IS_REG_BIT_SET(tmpVal, EMAC_TXC_M)) { - EMAC_ClrIntStatus(emacId, EMAC_INT_TX_CTRL); - - if (emacIntCbfArra[emacId][EMAC_INT_TX_CTRL_IDX]) { - emacIntCbfArra[emacId][EMAC_INT_TX_CTRL_IDX](); - } - } - - if (SET == EMAC_GetIntStatus(emacId, EMAC_INT_RX_CTRL) && !BL_IS_REG_BIT_SET(tmpVal, EMAC_RXC_M)) { - EMAC_ClrIntStatus(emacId, EMAC_INT_RX_CTRL); - - if (emacIntCbfArra[emacId][EMAC_INT_RX_CTRL_IDX]) { - emacIntCbfArra[emacId][EMAC_INT_RX_CTRL_IDX](); - } - } -} -#endif - -/****************************************************************************/ /** - * @brief EMAC0 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void EMAC0_IRQHandler(void) -{ - EMAC_IRQHandler(EMAC0_ID); -} -#endif - -/****************************************************************************/ /** - * @brief Request to pause TX - * - * @param emacId: EMAC ID type - * @param timeCount: Pause time count - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EMAC_TxPauseReq(EMAC_ID_Type emacId, uint16_t timeCount) -{ - uint32_t EMACx = emacAddr[emacId]; - - BL_WR_REG(EMACx, EMAC_TXCTRL, (1 << 16) | timeCount); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Set hash value - * - * @param emacId: EMAC ID type - * @param hash0: Hash value one - * @param hash1: Hash value two - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EMAC_SetHash(EMAC_ID_Type emacId, uint32_t hash0, uint32_t hash1) -{ - uint32_t EMACx = emacAddr[emacId]; - - BL_WR_REG(EMACx, EMAC_HASH0_ADDR, hash0); - - BL_WR_REG(EMACx, EMAC_HASH1_ADDR, hash1); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Get fram maximum len and minimum - * - * @param emacId: EMAC ID type - * @param max: point to maximum fram len - * @param min: point to minimum fram len - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EMAC_GetFramLen(EMAC_ID_Type emacId, uint16_t * max, uint16_t *min) -{ - uint32_t EMACx = emacAddr[emacId]; - uint32_t tmpval; - - tmpval = BL_RD_REG(EMACx, EMAC_PACKETLEN); - *max = BL_GET_REG_BITS_VAL(tmpval, EMAC_MAXFL); - *min = BL_GET_REG_BITS_VAL(tmpval, EMAC_MINFL); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Get BD numbers - * - * @param emacId: EMAC ID type - * @param bd: point to BD num - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EMAC_GetBD(EMAC_ID_Type emacId, uint32_t *bd) -{ - uint32_t EMACx = emacAddr[emacId]; - - *bd = BL_RD_REG(EMACx, EMAC_TX_BD_NUM); - - return SUCCESS; -} -/*@} end of group EMAC_Public_Functions */ - -/*@} end of group EMAC */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_glb_misc.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_glb_misc.c deleted file mode 100644 index 55140d8174..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_glb_misc.c +++ /dev/null @@ -1,2959 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_glb_misc.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_clock.h" -#include "bl808_glb.h" -#include "bl808_aon.h" -#include "bl808_hbn.h" -#include "bl808_pds.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup GLB - * @{ - */ - -/** @defgroup GLB_Private_Macros - * @{ - */ - - - -/*@} end of group GLB_Private_Macros */ - -/** @defgroup GLB_Private_Types - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -static intCallback_Type *glbBmxToIntCbfArra[BMX_TO_INT_ALL] = { NULL }; -#endif - -static BL_Err_Type GLB_Get_And_Clr_First_Set_From_U64(uint64_t *val, uint32_t *bit); - -/*@} end of group GLB_Private_Types */ - -/** @defgroup GLB_Private_Variables - * @{ - */ - -/*@} end of group GLB_Private_Variables */ - -/** @defgroup GLB_Global_Variables - * @{ - */ - -/*@} end of group GLB_Global_Variables */ - -/** @defgroup GLB_Private_Fun_Declaration - * @{ - */ - -/*@} end of group GLB_Private_Fun_Declaration */ - -/** @defgroup GLB_Private_Functions - * @{ - */ - -/*@} end of group GLB_Private_Functions */ - -/** @defgroup GLB_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief GLB set display clock - * - * @param enable: ENABLE or DISABLE - * @param srcClk: source clock type - * @param evenDiv: divider in even number - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_Display_CLK(uint8_t enable, GLB_DISP_CLK_Type srcClk, uint8_t evenDiv) -{ - uint32_t tmpVal = 0; - uint32_t evenNum = 0; - - CHECK_PARAM(IS_GLB_DISP_CLK_TYPE(srcClk)); - CHECK_PARAM((evenDiv <= 0x7F)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_MIPI_PLL_CFG1); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_MIPIPLL_EVEN_DIV_EN); - BL_WR_REG(GLB_BASE, GLB_MIPI_PLL_CFG1, tmpVal); - - if ((evenDiv >= 8) && (evenDiv <= 126)) { - evenNum = evenDiv & ~(1 << 0); - } else { - evenNum = evenDiv; - } - - tmpVal = BL_RD_REG(GLB_BASE, GLB_MIPI_PLL_CFG1); - if(enable){ - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_MIPIPLL_EVEN_DIV_EN); - }else{ - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_MIPIPLL_EVEN_DIV_EN); - } - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_MIPIPLL_EVEN_DIV_RATIO, evenNum); - BL_WR_REG(GLB_BASE, GLB_MIPI_PLL_CFG1, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief GLB enable or disable ethernet clock - * - * @param enable: ENABLE or DISABLE - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_Ethernet_CLK_From_UHSPLL(uint8_t enable) - -{ - uint32_t tmpVal = 0; - - /* uhspll_even_div_en */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_UHS_PLL_CFG1); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_UHSPLL_EVEN_DIV_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_UHSPLL_EVEN_DIV_EN); - } - BL_WR_REG(GLB_BASE, GLB_UHS_PLL_CFG1, tmpVal); - - return SUCCESS; -} - - - -/****************************************************************************/ /** - * @brief DSP get MCU interrupt status - * - * @param intType: MCU interrupt type - * - * @return SET or RESET - * -*******************************************************************************/ -BL_Sts_Type GLB_DSP_Get_MCU_IntStatus(GLB_MCU_ALL_INT_Type intType) -{ - CHECK_PARAM(IS_GLB_MCU_ALL_INT_TYPE(intType)); - - if (intType < 32) { - return (BL_RD_REG(GLB_BASE, GLB_CORE_CFG16) & (1 << intType)) ? SET : RESET; - } else { - return (BL_RD_REG(GLB_BASE, GLB_CORE_CFG17) & (1 << (intType - 32))) ? SET : RESET; - } -} - -/****************************************************************************/ /** - * @brief DSP set MCU interrupt mask - * - * @param intType: MCU interrupt type - * @param intMask: MASK or UNMASK - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_DSP_Set_MCU_IntMask(GLB_MCU_ALL_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_MCU_ALL_INT_TYPE(intType)); - - if (intType < 32) { - tmpVal = BL_RD_REG(GLB_BASE, GLB_CORE_CFG18); - if (UNMASK != intMask) { - tmpVal |= (1 << intType); - } else { - tmpVal &= ~(1 << intType); - } - BL_WR_REG(GLB_BASE, GLB_CORE_CFG18, tmpVal); - } else { - tmpVal = BL_RD_REG(GLB_BASE, GLB_CORE_CFG19); - if (UNMASK != intMask) { - tmpVal |= (1 << (intType - 32)); - } else { - tmpVal &= ~(1 << (intType - 32)); - } - BL_WR_REG(GLB_BASE, GLB_CORE_CFG19, tmpVal); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief DSP clear MCU interrupt status - * - * @param intType: MCU interrupt type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_DSP_Clr_MCU_IntStatus(GLB_MCU_ALL_INT_Type intType) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_MCU_ALL_INT_TYPE(intType)); - - if (intType < 32) { - tmpVal = BL_RD_REG(GLB_BASE, GLB_CORE_CFG20); - tmpVal |= (1 << intType); - BL_WR_REG(GLB_BASE, GLB_CORE_CFG20, tmpVal); - } else { - tmpVal = BL_RD_REG(GLB_BASE, GLB_CORE_CFG21); - tmpVal |= (1 << (intType - 32)); - BL_WR_REG(GLB_BASE, GLB_CORE_CFG21, tmpVal); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief DSP set LP interrupt enable - * - * @param enable: ENABLE or DISABLE - * @param intType: LP interrupt type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_DSP_Set_LP_IntEn(uint8_t enable, GLB_LP_ALL_INT_Type intType) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_LP_ALL_INT_TYPE(intType)); - - if (intType < 32) { - tmpVal = BL_RD_REG(GLB_BASE, GLB_CORE_CFG22); - if (enable) { - tmpVal |= (1 << intType); - } else { - tmpVal &= ~(1 << intType); - } - BL_WR_REG(GLB_BASE, GLB_CORE_CFG22, tmpVal); - } else { - tmpVal = BL_RD_REG(GLB_BASE, GLB_CORE_CFG23); - if (enable) { - tmpVal |= (1 << (intType - 32)); - } else { - tmpVal &= ~(1 << (intType - 32)); - } - BL_WR_REG(GLB_BASE, GLB_CORE_CFG23, tmpVal); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief DSP get LP interrupt status - * - * @param intType: LP interrupt type - * - * @return SET or RESET - * -*******************************************************************************/ -BL_Sts_Type GLB_DSP_Get_LP_IntStatus(GLB_LP_ALL_INT_Type intType) -{ - CHECK_PARAM(IS_GLB_LP_ALL_INT_TYPE(intType)); - - if (intType < 32) { - return (BL_RD_REG(GLB_BASE, GLB_CORE_CFG24) & (1 << intType)) ? SET : RESET; - } else { - return (BL_RD_REG(GLB_BASE, GLB_CORE_CFG25) & (1 << (intType - 32))) ? SET : RESET; - } -} - -/****************************************************************************/ /** - * @brief MCU get DSP interrupt status - * - * @param intType: DSP interrupt type - * - * @return SET or RESET - * -*******************************************************************************/ -BL_Sts_Type GLB_MCU_Get_DSP_IntStatus(GLB_DSP_ALL_INT_Type intType) -{ - CHECK_PARAM(IS_GLB_DSP_ALL_INT_TYPE(intType)); - - if (intType < 32) { - return (BL_RD_REG(MM_MISC_BASE, MM_MISC_MM_INT_STA0) & (1 << intType)) ? SET : RESET; - } else { - return (BL_RD_REG(MM_MISC_BASE, MM_MISC_MM_INT_STA1) & (1 << (intType - 32))) ? SET : RESET; - } -} - -/****************************************************************************/ /** - * @brief MCU set DSP interrupt mask - * - * @param intType: DSP interrupt type - * @param intMask: MASK or UNMASK - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_MCU_Set_DSP_IntMask(GLB_DSP_ALL_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_DSP_ALL_INT_TYPE(intType)); - - if (intType < 32) { - tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_MM_INT_MASK0); - if (UNMASK != intMask) { - tmpVal |= (1 << intType); - } else { - tmpVal &= ~(1 << intType); - } - BL_WR_REG(MM_MISC_BASE, MM_MISC_MM_INT_MASK0, tmpVal); - } else { - tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_MM_INT_MASK1); - if (UNMASK != intMask) { - tmpVal |= (1 << (intType - 32)); - } else { - tmpVal &= ~(1 << (intType - 32)); - } - BL_WR_REG(MM_MISC_BASE, MM_MISC_MM_INT_MASK1, tmpVal); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief MCU clear DSP interrupt status - * - * @param intType: DSP interrupt type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_MCU_Clr_DSP_IntStatus(GLB_DSP_ALL_INT_Type intType) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_DSP_ALL_INT_TYPE(intType)); - - if (intType < 32) { - tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_MM_INT_CLR_0); - tmpVal |= (1 << intType); - BL_WR_REG(MM_MISC_BASE, MM_MISC_MM_INT_CLR_0, tmpVal); - } else { - tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_MM_INT_CLR_1); - tmpVal |= (1 << (intType - 32)); - BL_WR_REG(MM_MISC_BASE, MM_MISC_MM_INT_CLR_1, tmpVal); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set MTimer clock - * - * @param enable: enable or disable MTimer clock - * @param div: divider - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_MCU_MTimer_CLK(uint8_t enable, uint16_t div, uint8_t rst) -{ - uint32_t tmpVal; - - CHECK_PARAM((div <= 0x3FF)); - - /* disable MTimer clock first */ - tmpVal = BL_RD_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC); - tmpVal = BL_CLR_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_EN); - BL_WR_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC, tmpVal); - - tmpVal = BL_RD_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC); - tmpVal = BL_CLR_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_RST); - BL_WR_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC, tmpVal); - tmpVal = BL_RD_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC); - tmpVal = BL_SET_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_RST); - BL_WR_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC, tmpVal); - tmpVal = BL_RD_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC); - tmpVal = BL_CLR_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_RST); - BL_WR_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC, tmpVal); - - tmpVal = BL_RD_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MCU_MISC_REG_MCU_RTC_DIV, div); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_EN); - } - BL_WR_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set MTimer clock - * - * @param enable: enable or disable MTimer clock - * @param div: divider - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_DSP_MTimer_CLK(uint8_t enable, uint16_t div, uint8_t rst) -{ - uint32_t tmpVal; - - CHECK_PARAM((div <= 0x3FF)); - - /* disable MTimer clock first */ - tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_CPU_RTC); - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_MISC_C906_RTC_EN); - BL_WR_REG(MM_MISC_BASE, MM_MISC_CPU_RTC, tmpVal); - - tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_CPU_RTC); - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_MISC_C906_RTC_RST); - BL_WR_REG(MM_MISC_BASE, MM_MISC_CPU_RTC, tmpVal); - tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_CPU_RTC); - tmpVal = BL_SET_REG_BIT(tmpVal, MM_MISC_C906_RTC_RST); - BL_WR_REG(MM_MISC_BASE, MM_MISC_CPU_RTC, tmpVal); - tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_CPU_RTC); - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_MISC_C906_RTC_RST); - BL_WR_REG(MM_MISC_BASE, MM_MISC_CPU_RTC, tmpVal); - - tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_CPU_RTC); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_MISC_C906_RTC_DIV, div); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, MM_MISC_C906_RTC_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_MISC_C906_RTC_EN); - } - BL_WR_REG(MM_MISC_BASE, MM_MISC_CPU_RTC, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set ADC clock - * - * @param enable: enable frequency divider or not - * @param clkSel: ADC clock selection - * @param div: divider - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_ADC_CLK(uint8_t enable, GLB_ADC_CLK_Type clkSel, uint8_t div) -{ - uint32_t tmpVal; - - CHECK_PARAM(IS_GLB_ADC_CLK_TYPE(clkSel)); - CHECK_PARAM((div <= 0x3F)); - - /* disable ADC clock first */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_ADC_CFG0); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPADC_32M_DIV_EN); - BL_WR_REG(GLB_BASE, GLB_ADC_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_ADC_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_DIV, div); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_SEL, clkSel); - BL_WR_REG(GLB_BASE, GLB_ADC_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_ADC_CFG0); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPADC_32M_DIV_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPADC_32M_DIV_EN); - } - BL_WR_REG(GLB_BASE, GLB_ADC_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set DMA clock - * - * @param enable: Enable or disable - * @param clk: DMA clock type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_DMA_CLK(uint8_t enable, GLB_DMA_CLK_ID_Type clk) -{ - uint32_t tmpVal; - uint32_t tmpVal2; - - CHECK_PARAM(IS_GLB_DMA_CLK_ID_TYPE(clk)); - - if (clk >= GLB_DMA1_CLK_CH0) { - /* DMA1 */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_DMA_CFG1); - tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, GLB_DMA2_CLK_EN); - if (enable) { - tmpVal2 |= (1 << (clk - GLB_DMA1_CLK_CH0)); - } else { - tmpVal2 &= (~(1 << (clk - GLB_DMA1_CLK_CH0))); - } - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DMA2_CLK_EN, tmpVal2); - BL_WR_REG(GLB_BASE, GLB_DMA_CFG1, tmpVal); - } else { - /* DMA0 */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_DMA_CFG0); - tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, GLB_DMA_CLK_EN); - if (enable) { - tmpVal2 |= (1 << clk); - } else { - tmpVal2 &= (~(1 << clk)); - } - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DMA_CLK_EN, tmpVal2); - BL_WR_REG(GLB_BASE, GLB_DMA_CFG0, tmpVal); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set peripheral DMA cn - * - * @param peri: peripheral - * @param cn: cn - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_Peripheral_DMA_CN(GLB_PERI_DMA_Type peri, GLB_PERI_DMA_CN_SEL_Type cn) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_PERI_DMA_TYPE(peri)); - CHECK_PARAM(IS_GLB_PERI_DMA_CN_SEL_TYPE(cn)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DMA_CFG2); - switch (cn) { - case GLB_PERI_DMA_CN_SEL_DMA0: - tmpVal &= ~(1 << peri); - break; - case GLB_PERI_DMA_CN_SEL_DMA1: - tmpVal |= (1 << peri); - break; - default: - break; - } - BL_WR_REG(GLB_BASE, GLB_DMA_CFG2, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set IR clock divider - * - * @param enable: enable or disable IR clock - * @param clkSel: IR clock type - * @param div: divider - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_IR_CLK(uint8_t enable, GLB_IR_CLK_SRC_Type clkSel, uint8_t div) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_IR_CLK_SRC_TYPE(clkSel)); - CHECK_PARAM((div <= 0x3F)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG0); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_IR_CLK_EN); - BL_WR_REG(GLB_BASE, GLB_IR_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_IR_CLK_DIV, div); - BL_WR_REG(GLB_BASE, GLB_IR_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG0); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_IR_CLK_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_IR_CLK_EN); - } - BL_WR_REG(GLB_BASE, GLB_IR_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Select ir rx gpio (gpio11~gpio13) - * - * @param gpio: IR gpio selected - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_IR_RX_GPIO_Sel(GLB_GPIO_Type gpio) -{ - uint32_t tmpVal = 0; - - /* Select gpio between gpio9 and gpio23 */ - if (gpio > 8 && gpio < 24) { - tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_IR_RX_GPIO_SEL, gpio - 8); - BL_WR_REG(GLB_BASE, GLB_IR_CFG1, tmpVal); - } - - /* Close ir rx */ - if (gpio == 0) { - tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_IR_RX_GPIO_SEL, 0); - BL_WR_REG(GLB_BASE, GLB_IR_CFG1, tmpVal); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Enable ir led driver - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_IR_LED_Driver_Enable(void) -{ - uint32_t tmpVal = 0; - - /* Enable led driver */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG1); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_PU_LEDDRV); - BL_WR_REG(GLB_BASE, GLB_IR_CFG1, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Disable ir led driver - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_IR_LED_Driver_Disable(void) -{ - uint32_t tmpVal = 0; - - /* Disable led driver */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG1); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_PU_LEDDRV); - BL_WR_REG(GLB_BASE, GLB_IR_CFG1, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Set UART2 IO selection - * - * @param ioType: UART2 IO selection type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_UART2_IO_Sel(GLB_UART2_IO_SEL_Type ioType) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_UART2_IO_SEL_TYPE(ioType)); - - /* Set uart2 io selection */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART2_IO_SEL, ioType); - BL_WR_REG(GLB_BASE, GLB_UART_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Set UART clock - * - * @param enable: Enable or disable UART clock - * @param clkSel: UART clock type - * @param div: UART clock divider - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_UART_CLK(uint8_t enable, HBN_UART_CLK_Type clkSel, uint8_t div) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM((div <= 0x7)); - CHECK_PARAM(IS_HBN_UART_CLK_TYPE(clkSel)); - - /* disable UART clock first */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_CFG0); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_UART_CLK_EN); - BL_WR_REG(GLB_BASE, GLB_UART_CFG0, tmpVal); - - /* Set div */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART_CLK_DIV, div); - BL_WR_REG(GLB_BASE, GLB_UART_CFG0, tmpVal); - - /* Select clock source for uart */ - HBN_Set_UART_CLK_Sel(clkSel); - - /* Set enable or disable */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_CFG0); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_UART_CLK_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_UART_CLK_EN); - } - BL_WR_REG(GLB_BASE, GLB_UART_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Select UART signal function - * - * @param sig: UART signal - * @param fun: UART function - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_UART_Fun_Sel(GLB_UART_SIG_Type sig, GLB_UART_SIG_FUN_Type fun) -{ - uint32_t sig_pos = 0; - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_UART_SIG_TYPE(sig)); - CHECK_PARAM(IS_GLB_UART_SIG_FUN_TYPE(fun)); - - if (sig < GLB_UART_SIG_8) { - tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_CFG1); - sig_pos = (sig * 4); - /* Clear original val */ - tmpVal &= (~(0xf << sig_pos)); - /* Set new value */ - tmpVal |= (fun << sig_pos); - BL_WR_REG(GLB_BASE, GLB_UART_CFG1, tmpVal); - } else { - tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_CFG2); - sig_pos = ((sig - 8) * 4); - /* Clear original val */ - tmpVal &= (~(0xf << sig_pos)); - /* Set new value */ - tmpVal |= (fun << sig_pos); - BL_WR_REG(GLB_BASE, GLB_UART_CFG2, tmpVal); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set sflash clock - * - * @param enable: enable or disable sflash clock - * @param clkSel: sflash clock type - * @param div: divider - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_SF_CLK(uint8_t enable, GLB_SFLASH_CLK_Type clkSel, uint8_t div) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_SFLASH_CLK_TYPE(clkSel)); - CHECK_PARAM((div <= 0x7)); - - /* disable SFLASH clock first */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_SF_CFG0); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SF_CLK_EN); - BL_WR_REG(GLB_BASE, GLB_SF_CFG0, tmpVal); - - if (clkSel == GLB_SFLASH_CLK_100M_CPUPLL) { - GLB_PLL_CGEN_Clock_UnGate(GLB_PLL_CGEN_TOP_CPUPLL_100M); - } - - /* clock divider */ - /* Select flash clock, all Flash CLKs are divied by PLL_480M */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_SF_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_DIV, div); - switch (clkSel) { - case GLB_SFLASH_CLK_120M_WIFIPLL: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2, 0x0); - break; - case GLB_SFLASH_CLK_XTAL: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2, 0x1); - break; - case GLB_SFLASH_CLK_100M_CPUPLL: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2, 0x3); - break; - case GLB_SFLASH_CLK_80M_MUXPLL: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x1); - break; - case GLB_SFLASH_CLK_BCLK: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x2); - break; - case GLB_SFLASH_CLK_96M_WIFIPLL: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x3); - break; - default: - break; - } - BL_WR_REG(GLB_BASE, GLB_SF_CFG0, tmpVal); - - /* enable or disable flash clock */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_SF_CFG0); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SF_CLK_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SF_CLK_EN); - } - BL_WR_REG(GLB_BASE, GLB_SF_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set I2C clock - * - * @param enable: Enable or disable I2C clock - * @param clkSel: clock selection - * @param div: divider - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_I2C_CLK(uint8_t enable, GLB_I2C_CLK_Type clkSel, uint8_t div) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_I2C_CLK_TYPE(clkSel)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_I2C_CFG0); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_I2C_CLK_EN); - BL_WR_REG(GLB_BASE, GLB_I2C_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_I2C_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_SEL, clkSel); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_DIV, div); - BL_WR_REG(GLB_BASE, GLB_I2C_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_I2C_CFG0); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_I2C_CLK_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_I2C_CLK_EN); - } - BL_WR_REG(GLB_BASE, GLB_I2C_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set I2S clock - * - * @param refClkEn: ref clock ENABLE or DISABLE - * @param refClkDiv: divider - * @param inRef: di ref clock - * @param outRef: do ref clock - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_I2S_CLK(uint8_t refClkEn, uint8_t refClkDiv, GLB_I2S_DI_REF_CLK_Type inRef, GLB_I2S_DO_REF_CLK_Type outRef) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM((refClkDiv <= 0x3F)); - CHECK_PARAM(IS_GLB_I2S_DI_REF_CLK_TYPE(inRef)); - CHECK_PARAM(IS_GLB_I2S_DO_REF_CLK_TYPE(outRef)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_I2S_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_I2S_DO_REF_CLK_SEL, outRef); - if (refClkEn) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_I2S_REF_CLK_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_I2S_REF_CLK_EN); - } - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_I2S_DI_REF_CLK_SEL, inRef); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_I2S_REF_CLK_DIV, refClkDiv); - BL_WR_REG(GLB_BASE, GLB_I2S_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set SPI clock - * - * @param enable: Enable or disable SPI clock - * @param clkSel: clock selection - * @param div: divider - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_SPI_CLK(uint8_t enable, GLB_SPI_CLK_Type clkSel, uint8_t div) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_SPI_CLK_TYPE(clkSel)); - CHECK_PARAM((div <= 0x1F)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_SPI_CFG0); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SPI_CLK_EN); - BL_WR_REG(GLB_BASE, GLB_SPI_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_SPI_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_DIV, div); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_SEL, clkSel); - BL_WR_REG(GLB_BASE, GLB_SPI_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_SPI_CFG0); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SPI_CLK_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SPI_CLK_EN); - } - BL_WR_REG(GLB_BASE, GLB_SPI_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set PWM1 clock - * - * @param ioSel: io select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_PWM1_IO_Sel(GLB_PWM1_IO_SEL_Type ioSel) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_PWM1_IO_SEL_TYPE(ioSel)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_PWM_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PWM1_IO_SEL, ioSel); - BL_WR_REG(GLB_BASE, GLB_PWM_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set PWM2 clock - * - * @param ioSel: io select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_PWM2_IO_Sel(GLB_PWM2_IO_SEL_Type ioSel) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_PWM2_IO_SEL_TYPE(ioSel)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_PWM_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PWM2_IO_SEL, ioSel); - BL_WR_REG(GLB_BASE, GLB_PWM_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set PDM clock - * - * @param ioSel: io select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_PDM_IO_Sel(GLB_PDM_IO_SEL_Type ioSel) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_PDM_IO_SEL_TYPE(ioSel)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_PDM_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PDM_IO_SEL, ioSel); - BL_WR_REG(GLB_BASE, GLB_PDM_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief select DIG clock source - * - * @param clkSel: DIG clock selection - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_DIG_CLK_Sel(GLB_DIG_CLK_Type clkSel) -{ - uint32_t tmpVal; - uint32_t dig512kEn; - uint32_t dig32kEn; - - CHECK_PARAM(IS_GLB_DIG_CLK_TYPE(clkSel)); - - /* disable DIG512K and DIG32K clock first */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0); - dig512kEn = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_EN); - dig32kEn = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_32K_EN); - BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_CLK_SRC_SEL, clkSel); - BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG0, tmpVal); - - /* repristinate DIG512K and DIG32K clock */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_EN, dig512kEn); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_EN, dig32kEn); - BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set DIG 512K clock - * - * @param enable: enable or disable DIG 512K clock - * @param compensationEn: enable or disable DIG 512K clock compensation - * @param div: divider - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_DIG_512K_CLK(uint8_t enable, uint8_t compensationEn, uint8_t div) -{ - uint32_t tmpVal; - - CHECK_PARAM((div <= 0x7F)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0); - if (compensationEn) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_512K_COMP); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_COMP); - } - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_DIV, div); - BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_512K_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_EN); - } - BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set DIG 32K clock - * - * @param enable: enable or disable DIG 32K clock - * @param compensationEn: enable or disable DIG 32K clock compensation - * @param div: divider - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_DIG_32K_CLK(uint8_t enable, uint8_t compensationEn, uint16_t div) -{ - uint32_t tmpVal; - - CHECK_PARAM((div <= 0x7FF)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0); - if (compensationEn) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_32K_COMP); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_32K_COMP); - } - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_DIV, div); - BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_32K_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_32K_EN); - } - BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief platform wakeup becomes one of pds_wakeup source - * - * @param enable: ENABLE or DISABLE - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Platform_Wakeup_PDS_Enable(uint8_t enable) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_EN_PLATFORM_WAKEUP); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_EN_PLATFORM_WAKEUP); - } - BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief mcu gpio timer clock select - * - * @param gpioPin: gpio pin number - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Sel_MCU_TMR_GPIO_Clock(GLB_GPIO_Type gpioPin) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2); - switch (gpioPin & 0x3) { - case 0: /* inout_sig_0 */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_0_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPIO_TMR_CLK_SEL, 0); - break; - case 1: /* inout_sig_1 */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_1_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPIO_TMR_CLK_SEL, 1); - break; - case 2: /* inout_sig_2 */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_2_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPIO_TMR_CLK_SEL, 2); - break; - case 3: /* inout_sig_3 */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_3_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPIO_TMR_CLK_SEL, 3); - break; - default: - break; - } - BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief dsp gpio timer clock select - * - * @param gpioPin: gpio pin number - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Sel_DSP_TMR_GPIO_Clock(GLB_GPIO_Type gpioPin) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2); - switch (gpioPin & 0x3) { - case 0: /* inout_sig_0 */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_0_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPIO_MM_TMR_CLK_SEL, 0); - break; - case 1: /* inout_sig_1 */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_1_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPIO_MM_TMR_CLK_SEL, 1); - break; - case 2: /* inout_sig_2 */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_2_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPIO_MM_TMR_CLK_SEL, 2); - break; - case 3: /* inout_sig_3 */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_3_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPIO_MM_TMR_CLK_SEL, 3); - break; - default: - break; - } - BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief chip clock out0 select - * - * @param clkOutType: chip clock out0 output type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_Chip_Clock_Out0_Sel(GLB_CHIP_CLK_OUT_0_Type clkOutType) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2); - /* set clk out0 output enable */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_0_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_0_SEL, clkOutType); - BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief chip clock out1 select - * - * @param clkOutType: chip clock out1 output type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_Chip_Clock_Out1_Sel(GLB_CHIP_CLK_OUT_1_Type clkOutType) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2); - /* set clk out1 output enable */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_1_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_1_SEL, clkOutType); - BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief chip clock out2 select - * - * @param clkOutType: chip clock out2 output type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_Chip_Clock_Out2_Sel(GLB_CHIP_CLK_OUT_2_Type clkOutType) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2); - /* set clk out2 output enable */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_2_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_2_SEL, clkOutType); - BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief chip clock out3 select - * - * @param clkOutType: chip clock out3 output type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_Chip_Clock_Out3_Sel(GLB_CHIP_CLK_OUT_3_Type clkOutType) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2); - /* set clk out3 output enable */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_3_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_3_SEL, clkOutType); - BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief csi dsi clock select - * - * @param csiClkSel: csi clock select - * @param dsiClkSel: dsi clock select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_CSI_DSI_CLK_Sel(GLB_CSI_DSI_CLK_SEL_Type csiClkSel, GLB_CSI_DSI_CLK_SEL_Type dsiClkSel) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CSI_TXCLKESC_SEL, csiClkSel); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DSI_TXCLKESC_SEL, dsiClkSel); - BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG3, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief BMX init - * - * @param BmxCfg: BMX config - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_BMX_TO_Init(BMX_TO_Cfg_Type *BmxCfg) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM((BmxCfg->timeoutEn) <= 0x1F); - CHECK_PARAM(IS_BMX_ARB_TYPE(BmxCfg->arbMod)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BMX_TIMEOUT_EN, BmxCfg->timeoutEn); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BMX_ARB_MODE, BmxCfg->arbMod); - BL_WR_REG(GLB_BASE, GLB_BMX_CFG0, tmpVal); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(BMX_MCU_TO_IRQn, BMX_TO_IRQHandler); -#endif - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Get BMX TO status - * - * @param None - * - * @return BMX TO status - * -*******************************************************************************/ -uint8_t GLB_Get_BMX_TO_Status(void) -{ - return BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_BMX_CFG0), GLB_STS_BMX_TIMEOUT_STS); -} - -/****************************************************************************/ /** - * @brief clear BMX TO status - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Clr_BMX_TO_Status(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG0); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_BMX_TIMEOUT_CLR); - BL_WR_REG(GLB_BASE, GLB_BMX_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG0); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_BMX_TIMEOUT_CLR); - BL_WR_REG(GLB_BASE, GLB_BMX_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG0); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_BMX_TIMEOUT_CLR); - BL_WR_REG(GLB_BASE, GLB_BMX_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief BMX timeout interrupt callback install - * - * @param intType: BMX timeout interrupt type - * @param cbFun: callback - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -BL_Err_Type BMX_TIMEOUT_INT_Callback_Install(BMX_TO_INT_Type intType, intCallback_Type *cbFun) -{ - CHECK_PARAM(IS_BMX_TO_INT_TYPE(intType)); - - glbBmxToIntCbfArra[intType] = cbFun; - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief BMX Time Out interrupt IRQ handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void BMX_TO_IRQHandler(void) -{ - BMX_TO_INT_Type intType; - - for (intType = 0; intType < BMX_TO_INT_ALL; intType++) { - if (glbBmxToIntCbfArra[intType] != NULL) { - glbBmxToIntCbfArra[intType](); - } - } - GLB_Clr_BMX_TO_Status(); -} -#endif - -/****************************************************************************/ /** - * @brief set audio auto clock - * - * @param divEn: ENABLE or DISABLE - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_Audio_AUTO_CLK(uint8_t divEn) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0); - if (divEn) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_AUDIO_AUTO_DIV_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_AUDIO_AUTO_DIV_EN); - } - BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set audio ADC clock - * - * @param enable: ENABLE or DISABLE - * @param div: divider - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_Audio_ADC_CLK(uint8_t enable, uint8_t div) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM((div <= 0x3F)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_AUDIO_ADC_CLK_EN); - BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_AUDIO_ADC_CLK_DIV, div); - BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_AUDIO_ADC_CLK_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_AUDIO_ADC_CLK_EN); - } - BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set audio DAC clock - * - * @param enable: ENABLE or DISABLE - * @param div: divider - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_Audio_DAC_CLK(uint8_t enable, uint8_t div) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM((div <= 0x3F)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_AUDIO_DAC_CLK_EN); - BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_AUDIO_DAC_CLK_DIV, div); - BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_AUDIO_DAC_CLK_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_AUDIO_DAC_CLK_EN); - } - BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set audio PDM clock - * - * @param enable: ENABLE or DISABLE - * @param div: divider - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_Audio_PDM_CLK(uint8_t enable, uint8_t div) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM((div <= 0x3F)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_AUDIO_PDM_CLK_EN); - BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_AUDIO_PDM_CLK_DIV, div); - BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_AUDIO_PDM_CLK_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_AUDIO_PDM_CLK_EN); - } - BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set audio PDM clock - * - * @param enable: ENABLE or DISABLE - * @param div: divider - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_PADC_CLK(uint8_t enable, uint16_t div) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM((div <= 0x3F)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG1); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_PADC_CLK_EN); - BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG1, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PADC_CLK_DIV, div); - BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG1, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG1); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_PADC_CLK_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_PADC_CLK_EN); - } - BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG1, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief invert eth rx clock - * - * @param enable: ENABLE or DISABLE - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Invert_ETH_RX_CLK(uint8_t enable) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_ETH_CFG0); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_INV_ETH_RX_CLK); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_INV_ETH_RX_CLK); - } - BL_WR_REG(GLB_BASE, GLB_ETH_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief invert eth tx clock - * - * @param enable: ENABLE or DISABLE - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Invert_ETH_TX_CLK(uint8_t enable) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_ETH_CFG0); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_INV_ETH_TX_CLK); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_INV_ETH_TX_CLK); - } - BL_WR_REG(GLB_BASE, GLB_ETH_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief invert eth ref clock - * - * @param enable: ENABLE or DISABLE - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Invert_ETH_REF_O_CLK(uint8_t enable) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_ETH_CFG0); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_INV_ETH_REF_CLK_O); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_INV_ETH_REF_CLK_O); - } - BL_WR_REG(GLB_BASE, GLB_ETH_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set eth ref clock select - * - * @param clkSel: clock selection - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_ETH_REF_O_CLK_Sel(GLB_ETH_REF_CLK_OUT_Type clkSel) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_ETH_REF_CLK_OUT_TYPE(clkSel)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_ETH_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CFG_SEL_ETH_REF_CLK_O, clkSel); - BL_WR_REG(GLB_BASE, GLB_ETH_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set CAM clock - * - * @param enable: Enable or disable CAM clock - * @param clkSel: CAM clock type - * @param div: clock divider - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_CAM_CLK(uint8_t enable, GLB_CAM_CLK_Type clkSel, uint8_t div) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_CAM_CLK_TYPE(clkSel)); - CHECK_PARAM((div <= 0x3)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_CAM_CFG0); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CAM_REF_CLK_EN); - BL_WR_REG(GLB_BASE, GLB_CAM_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_CAM_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_SRC_SEL, clkSel); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_DIV, div); - BL_WR_REG(GLB_BASE, GLB_CAM_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_CAM_CFG0); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CAM_REF_CLK_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CAM_REF_CLK_EN); - } - BL_WR_REG(GLB_BASE, GLB_CAM_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set SDH clock - * - * @param enable: Enable or disable - * @param clkSel: SDH clock type - * @param div: clock divider - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_SDH_CLK(uint8_t enable, GLB_SDH_CLK_Type clkSel, uint8_t div) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_SDH_CLK_TYPE(clkSel)); - CHECK_PARAM((div <= 0x7)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_SDH_CFG0); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_SDH_CLK_EN); - BL_WR_REG(GLB_BASE, GLB_SDH_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_SDH_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_SDH_CLK_SEL, clkSel); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_SDH_CLK_DIV, div); - BL_WR_REG(GLB_BASE, GLB_SDH_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_SDH_CFG0); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_SDH_CLK_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_SDH_CLK_EN); - } - BL_WR_REG(GLB_BASE, GLB_SDH_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief swap UART gpio pins sig function - * - * @param group: UART swap set group - * @param swap: swap or no swap - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_UART_Sig_Swap_Set(GLB_UART_SIG_SWAP_GRP_Type group, uint8_t swap) -{ - uint32_t tmpVal = 0; - uint32_t tmpVal2 = 0; - - CHECK_PARAM(IS_GLB_UART_SIG_SWAP_GRP_TYPE(group)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM_CFG0); - tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, GLB_UART_SWAP_SET); - if (swap) { - tmpVal2 |= (1 << group); - } else { - tmpVal2 &= ~(1 << group); - } - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART_SWAP_SET, tmpVal2); - BL_WR_REG(GLB_BASE, GLB_PARM_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief swap DSP SPI0 MOSI with MISO - * - * @param newState: ENABLE or DISABLE - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Swap_DSP_SPI_0_MOSI_With_MISO(BL_Fun_Type newState) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_MM_SPI_SWAP, newState); - BL_WR_REG(GLB_BASE, GLB_PARM_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Select DSP SPI_0 act mode - * - * @param mod: SPI work mode - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_DSP_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_Type mod) -{ - uint32_t tmpVal; - - CHECK_PARAM(IS_GLB_SPI_PAD_ACT_AS_TYPE(mod)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_MM_SPI_MASTER_MODE, mod); - BL_WR_REG(GLB_BASE, GLB_PARM_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Set L2SRAM - * - * @param h2pfSramRel: make pfh_64k0,pfh_64k1,pfh_64k0 writable - * @param vramSramRel: make l2_vram writable - * @param dspl2SramRel: make dspl2_32k0,dspl2_32k1 writable - * @param blaiSramRel: make blai_64k0,blai_64k1 writable - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_DSP_L2SRAM_Available_Size(uint8_t h2pfSramRel, uint8_t vramSramRel, uint8_t dspl2SramRel, uint8_t blaiSramRel) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_MISC_VRAM_CTRL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_MISC_REG_H2PF_SRAM_REL, h2pfSramRel); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_MISC_REG_VRAM_SRAM_REL, vramSramRel); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_MISC_REG_DSPL2_SRAM_REL, dspl2SramRel); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_MISC_REG_BLAI_SRAM_REL, blaiSramRel); - BL_WR_REG(MM_GLB_BASE, MM_MISC_VRAM_CTRL, tmpVal); - - /* Make the above settings effective */ - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_MISC_VRAM_CTRL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_MISC_REG_SYSRAM_SET, 1); - BL_WR_REG(MM_GLB_BASE, MM_MISC_VRAM_CTRL, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Select DSP SPI_0 act mode - * - * @param mod: SPI work mode - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Swap_MCU_SPI_0_MOSI_With_MISO(BL_Fun_Type newState) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_SPI_0_SWAP, newState); - BL_WR_REG(GLB_BASE, GLB_PARM_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Select SPI_0 act mode - * - * @param mod: SPI work mode - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_MCU_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_Type mod) -{ - uint32_t tmpVal; - - CHECK_PARAM(IS_GLB_SPI_PAD_ACT_AS_TYPE(mod)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_SPI_0_MASTER_MODE, mod); - BL_WR_REG(GLB_BASE, GLB_PARM_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set flash io parameter - * - * @param selEmbedded: Select embedded flash pin - * @param swap: Select embedded flash swap io0 with io3 - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION GLB_Set_Flash_IO_PARM(uint8_t selEmbedded, uint8_t swap) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM_CFG0); - if (selEmbedded) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SEL_EMBEDDED_SFLASH); - if (swap) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SWAP_SFLASH_IO_3_IO_0); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SWAP_SFLASH_IO_3_IO_0); - } - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SEL_EMBEDDED_SFLASH); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SWAP_SFLASH_IO_3_IO_0); - } - BL_WR_REG(GLB_BASE, GLB_PARM_CFG0, tmpVal); - - if (selEmbedded) { - GLB_Embedded_Flash_Pad_Enable(); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief gate pll clock cgen - * - * @param clk: pll clock cgen - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_PLL_CGEN_Clock_Gate(GLB_PLL_CGEN_Type clk) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_PLL_CGEN_TYPE(clk)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG3); - tmpVal &= (~(1 << clk)); - BL_WR_REG(GLB_BASE, GLB_CGEN_CFG3, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief gate pll clock cgen - * - * @param clk: pll clock cgen - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_PLL_CGEN_Clock_UnGate(GLB_PLL_CGEN_Type clk) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_PLL_CGEN_TYPE(clk)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG3); - tmpVal |= (1 << clk); - BL_WR_REG(GLB_BASE, GLB_CGEN_CFG3, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief select PKA clock source - * - * @param clkSel: PKA clock selection - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_Type clkSel) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_PKA_CLK_TYPE(clkSel)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PKA_CLK_SEL, clkSel); - BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief mcu system part reset - * - * @param sysPart: mcu reset part - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION GLB_MCU_SW_System_Reset(GLB_MCU_SW_SYSTEM_Type sysPart) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_MCU_SW_SYSTEM_TYPE(sysPart)); - - /* reset=0 */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); - tmpVal &= ~(1 << sysPart); - BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); - BL_DRV_DUMMY; - /* reset=1 */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); - tmpVal |= (1 << sysPart); - BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); - BL_DRV_DUMMY; - /* reset=1 */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); - tmpVal &= ~(1 << sysPart); - BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Software system reset - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION GLB_SW_System_Reset(void) -{ - uint32_t tmpVal; - - /* Swicth DSP clock to RC32M, no divider */ - GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_RC32M); - GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_XCLK); - GLB_Set_DSP_System_CLK_Div(0, 0); - - /* Swicth MCU clock to RC32M, no divider */ - HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M); - HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK); - GLB_Set_MCU_System_CLK_Div(0, 0, 0); - - /* reset M0/M1/LP/SYS(bus+...+D0+D1) */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET); - BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); - tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_PICO_RESET); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET); - BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); - - /* waiting for reset */ - while (1) { - arch_delay_us(10); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Software CPU reset - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION GLB_SW_CPU_Reset(void) -{ - uint32_t tmpVal; - - GLB_CORE_ID_Type core = GLB_CORE_ID_INVALID; - - /* Do reset */ - core = GLB_Get_Core_Type(); - - switch (core) { - case GLB_CORE_ID_M0: - /* Swicth MCU clock to RC32M, no divider */ - HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M); - HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK); - GLB_Set_MCU_System_CLK_Div(0, 0, 0); - tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET); - BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); - tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET); - BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); - tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET); - BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); - break; - case GLB_CORE_ID_D0: - /* Swicth DSP clock to RC32M, no divider */ - GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_RC32M); - GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_XCLK); - GLB_Set_DSP_System_CLK_Div(0, 0); - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET); - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_CTRL_MMCPU0_RESET); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET, tmpVal); - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET); - tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_CTRL_MMCPU0_RESET); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET, tmpVal); - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET); - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_CTRL_MMCPU0_RESET); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET, tmpVal); - break; - case GLB_CORE_ID_LP: - /* Swicth MCU clock to RC32M, no divider */ - HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M); - HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK); - GLB_Set_MCU_System_CLK_Div(0, 0, 0); - tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PICO_RESET); - BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); - tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_PICO_RESET); - BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); - tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PICO_RESET); - BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); - break; - default: - break; - } - - /* waiting for reset */ - while (1) { - arch_delay_us(10); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Software power on reset - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION GLB_SW_POR_Reset(void) -{ - uint32_t tmpVal; - - /* Swicth DSP clock to RC32M, no divider */ - GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_RC32M); - GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_XCLK); - GLB_Set_DSP_System_CLK_Div(0, 0); - - /* Swicth MCU clock to RC32M, no divider */ - HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M); - HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK); - GLB_Set_MCU_System_CLK_Div(0, 0, 0); - - /* Do reset */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST); - BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST); - BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST); - BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); - - /* waiting for reset */ - while (1) { - arch_delay_us(10); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set auto calc xtal type value - * - * @param calcXtalType: auto calc xtal type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_Auto_Calc_Xtal_Type(GLB_XTAL_Type calcXtalType) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_XTAL_TYPE(calcXtalType)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_HW_RSV0); - tmpVal = tmpVal & 0xffff0000; - tmpVal |= GLB_AUTO_CALC_XTAL_FLAG_VALUE; - tmpVal |= calcXtalType; - BL_WR_REG(GLB_BASE, GLB_HW_RSV0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set auto calc xtal type value - * - * @param calcXtalType: auto calc xtal type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Get_Auto_Calc_Xtal_Type(GLB_XTAL_Type *calcXtalType) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_HW_RSV0); - if ((tmpVal & GLB_AUTO_CALC_XTAL_FLAG_MASK) == GLB_AUTO_CALC_XTAL_FLAG_VALUE) { - *calcXtalType = (tmpVal & 0xff); - return SUCCESS; - } else { - *calcXtalType = 0; - return ERROR; - } -} - -/****************************************************************************/ /** - * @brief set flash id value - * - * @param idValue: flash id value - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_Flash_Id_Value(uint32_t idValue) -{ - BL_WR_REG(GLB_BASE, GLB_HW_RSV1, idValue); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get flash id value - * - * @param None - * - * @return flash id - * -*******************************************************************************/ -uint32_t GLB_Get_Flash_Id_Value(void) -{ - return BL_RD_REG(GLB_BASE, GLB_HW_RSV1); -} - -/****************************************************************************/ /** - * @brief set sram_ret value - * - * @param value: value - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_SRAM_RET(uint32_t value) -{ - BL_WR_REG(GLB_BASE, GLB_SRAM_CFG0, value); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get sram_ret value - * - * @param None - * - * @return value - * -*******************************************************************************/ -uint32_t GLB_Get_SRAM_RET(void) -{ - return BL_RD_REG(GLB_BASE, GLB_SRAM_CFG0); -} - -/****************************************************************************/ /** - * @brief set sram_slp value - * - * @param value: value - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_SRAM_SLP(uint32_t value) -{ - BL_WR_REG(GLB_BASE, GLB_SRAM_CFG1, value); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get sram_slp value - * - * @param None - * - * @return value - * -*******************************************************************************/ -uint32_t GLB_Get_SRAM_SLP(void) -{ - return BL_RD_REG(GLB_BASE, GLB_SRAM_CFG1); -} - -/****************************************************************************/ /** - * @brief set sram_param value - * - * @param value: value - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_SRAM_PARM(uint32_t value) -{ - BL_WR_REG(GLB_BASE, GLB_SRAM_CFG2, value); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get sram_parm value - * - * @param None - * - * @return value - * -*******************************************************************************/ -uint32_t GLB_Get_SRAM_PARM(void) -{ - return BL_RD_REG(GLB_BASE, GLB_SRAM_CFG2); -} - -/****************************************************************************/ /** - * @brief select EM type - * - * @param emType: EM type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_EM_Sel(GLB_EM_Type emType) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_EM_TYPE(emType)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_SRAM_CFG3); - switch (emType) { - case GLB_WRAM160KB_EM0KB: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, 0x00); - break; - case GLB_WRAM144KB_EM16KB: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, 0x03); - break; - case GLB_WRAM128KB_EM32KB: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, 0x0F); - break; - case GLB_WRAM112KB_EM48KB: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, 0x3F); - break; - case GLB_WRAM96KB_EM64KB: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, 0xFF); - break; - default: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, 0x03); - break; - } - BL_WR_REG(GLB_BASE, GLB_SRAM_CFG3, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set psram clock - * - * @param id: psram id - * @param enable: enable or disable psram clock - * @param pll: psram pll clock - * @param div: divider - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -__WEAK -BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_PSram_CLK(uint8_t id, uint8_t enable, GLB_PSRAM_PLL_Type pll, uint8_t div) -{ - uint32_t tmpVal = 0; - uint32_t en = 0; - - CHECK_PARAM(IS_GLB_PSRAM_PLL_TYPE(pll)); - CHECK_PARAM((div <= 0x3)); - - en = enable ? 1 : 0; - tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG3); - switch (pll) { - case GLB_PSRAM_EMI_CPUPLL_400M: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CGEN_EMI_CPUPLL_400M, en); - break; - case GLB_PSRAM_EMI_WIFIPLL_320M: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CGEN_EMI_WIFIPLL_320M, en); - break; - case GLB_PSRAM_EMI_AUPLL_DIV1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CGEN_EMI_AUPLL_DIV1, en); - break; - default: - break; - } - BL_WR_REG(GLB_BASE, GLB_CGEN_CFG3, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_PSRAM_CFG0); - if (id == 1) { - /* psram B */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PSRAMB_CLK_EN, en); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PSRAMB_CLK_SEL, pll); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PSRAMB_CLK_DIV, div); - } - BL_WR_REG(GLB_BASE, GLB_PSRAM_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief trim ldo18io vout - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Trim_LDO18IO_Vout(void) -{ - Efuse_Ana_LDO18IO_VOUT_Trim_Type trim; - uint32_t tmpVal = 0; - - EF_Ctrl_Read_LDO18IO_Vout_Trim(&trim); - if (trim.trimLdo18ioVoutEn) { - if (trim.trimLdo18ioVoutParity == EF_Ctrl_Get_Trim_Parity(trim.trimLdo18ioVoutVal, 4)) { - tmpVal = BL_RD_REG(AON_BASE, AON_LDO18IO); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_LDO18IO_VOUT_TRIM_AON, trim.trimLdo18ioVoutVal); - BL_WR_REG(AON_BASE, AON_LDO18IO, tmpVal); - return SUCCESS; - } - } - - return ERROR; -} - -/****************************************************************************/ /** - * @brief trim ldo18flash vout - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Trim_LDO18FLASH_Vout(void) -{ - Efuse_Ana_LDO18FLASH_Trim_Type trim; - uint32_t tmpVal = 0; - - EF_Ctrl_Read_LDO18FLASH_Trim(&trim); - if (trim.trimLdo18flashVoutAonEn) { - if (trim.trimLdo18flashVoutAonParity == EF_Ctrl_Get_Trim_Parity(trim.trimLdo18flashVoutAon, 4)) { - tmpVal = BL_RD_REG(GLB_BASE, GLB_LDO18FLASH); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LDO18FLASH_VOUT_TRIM, trim.trimLdo18flashVoutAon); - BL_WR_REG(GLB_BASE, GLB_LDO18FLASH, tmpVal); - return SUCCESS; - } - } - - return ERROR; -} - -/****************************************************************************/ /** - * @brief set cnn clock - * - * @param enable: ENABLE or DISABLE - * @param clkSel: cnn clock type - * @param div: div - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_DSP_CNN_CLK(uint8_t enable, GLB_DSP_CNN_CLK_Type clkSel, uint8_t div) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_DSP_CNN_CLK_TYPE(clkSel)); - CHECK_PARAM((div <= 0x7)); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CNN_CLK_DIV, div); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CNN_CLK_SEL, clkSel); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_CNN_CLK_DIV_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_CNN_CLK_DIV_EN); - } - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set display clock - * - * @param enable: ENABLE or DISABLE - * @param clkSel: display clock type - * @param div: div - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_DSP_DP_CLK(uint8_t enable, GLB_DSP_DP_CLK_Type clkSel, uint8_t div) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_DSP_DP_CLK_TYPE(clkSel)); - CHECK_PARAM((div <= 0xF)); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_DSP2_DP_CLK); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_DP_CLK_DIV, div); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_DP_CLK_SEL, clkSel); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_DP_CLK_DIV_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_DP_CLK_DIV_EN); - } - BL_WR_REG(MM_GLB_BASE, MM_GLB_DSP2_DP_CLK, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set dsp2 clock - * - * @param enable: ENABLE or DISABLE - * @param clkSel: dsp2 clock type - * @param div: div - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_DSP_DSP2_CLK(uint8_t enable, GLB_DSP_DSP2_CLK_Type clkSel, uint8_t div) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_DSP_DSP2_CLK_TYPE(clkSel)); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_DSP2_DP_CLK); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_DSP2_CLK_DIV, div); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_DSP2_CLK_SEL, clkSel); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_DSP2_CLK_DIV_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_DSP2_CLK_DIV_EN); - } - BL_WR_REG(MM_GLB_BASE, MM_GLB_DSP2_DP_CLK, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set h264 clock - * - * @param enable: ENABLE or DISABLE - * @param clkSel: h264 clock type - * @param div: div - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_DSP_H264_CLK(uint8_t enable, GLB_DSP_H264_CLK_Type clkSel, uint8_t div) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_DSP_H264_CLK_TYPE(clkSel)); - CHECK_PARAM((div <= 0x7)); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_CODEC_CLK); - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_H264_CLK_DIV_EN); - BL_WR_REG(MM_GLB_BASE, MM_GLB_CODEC_CLK, tmpVal); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_CODEC_CLK); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_H264_CLK_DIV, div); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_H264_CLK_SEL, clkSel); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_H264_CLK_DIV_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_H264_CLK_DIV_EN); - } - BL_WR_REG(MM_GLB_BASE, MM_GLB_CODEC_CLK, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set spi clock - * - * @param enable: ENABLE or DISABLE - * @param div: div - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_DSP_SPI_CLK(uint8_t enable, GLB_DSP_SPI_CLK_Type clkSel, uint8_t div) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_DSP_SPI_CLK_TYPE(clkSel)); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI); - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_SPI_CLK_DIV_EN); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI, tmpVal); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_SPI_CLK_SEL, clkSel); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_SPI_CLK_DIV, div); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_SPI_CLK_DIV_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_SPI_CLK_DIV_EN); - } - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set uart0 clock - * - * @param enable: ENABLE or DISABLE - * @param uartClk: mm glb uart clock type - * @param div: div - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_DSP_UART0_CLK(uint8_t enable, GLB_DSP_UART_CLK_Type uartClk, uint8_t div) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_DSP_UART_CLK_TYPE(uartClk)); - CHECK_PARAM((div <= 0x7)); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI); - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_UART0_CLK_DIV_EN); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI, tmpVal); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_UART_CLK_SEL, uartClk); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_UART0_CLK_DIV, div); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_UART0_CLK_DIV_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_UART0_CLK_DIV_EN); - } - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set uart1 clock - * - * @param enable: ENABLE or DISABLE - * @param uartClk: mm glb uart clock type - * @param div: div - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_DSP_UART1_CLK(uint8_t enable, GLB_DSP_UART_CLK_Type uartClk, uint8_t div) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_DSP_UART_CLK_TYPE(uartClk)); - CHECK_PARAM((div <= 0x7)); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI3); - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_UART1_CLK_DIV_EN); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI3, tmpVal); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_UART_CLK_SEL, uartClk); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_UART1_CLK_DIV, div); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_UART1_CLK_DIV_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_UART1_CLK_DIV_EN); - } - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI3, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set i2c0 clock - * - * @param enable: ENABLE or DISABLE - * @param divEn: div enable - * @param div: div - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_DSP_I2C0_CLK(uint8_t enable, GLB_DSP_I2C_CLK_Type clkSel, uint8_t divEn, uint8_t div) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_DSP_I2C_CLK_TYPE(clkSel)); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI); - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_I2C0_CLK_EN); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI, tmpVal); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_I2C_CLK_SEL, clkSel); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_I2C0_CLK_DIV, div); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_I2C0_CLK_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_I2C0_CLK_EN); - } - if (divEn) { - tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_I2C0_CLK_DIV_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_I2C0_CLK_DIV_EN); - } - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set i2c1 clock - * - * @param enable: ENABLE or DISABLE - * @param divEn: div enable - * @param div: div - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_DSP_I2C1_CLK(uint8_t enable, GLB_DSP_I2C_CLK_Type clkSel, uint8_t divEn, uint8_t div) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_DSP_I2C_CLK_TYPE(clkSel)); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI3); - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_I2C1_CLK_EN); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI3, tmpVal); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_I2C_CLK_SEL, clkSel); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_I2C1_CLK_DIV, div); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_I2C1_CLK_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_I2C1_CLK_EN); - } - if (divEn) { - tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_I2C1_CLK_DIV_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_I2C1_CLK_DIV_EN); - } - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI3, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief sw sys reset - * - * @param sysPart: reset type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION GLB_DSP_SW_System_Reset(GLB_DSP_SW_SYSTEM_Type sysPart) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_DSP_SW_SYSTEM_TYPE(sysPart)); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET); - tmpVal &= ~(1 << sysPart); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET, tmpVal); - BL_DRV_DUMMY; - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET); - tmpVal |= (1 << sysPart); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET, tmpVal); - BL_DRV_DUMMY; - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET); - tmpVal &= ~(1 << sysPart); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief peripheral reset - * - * @param periPart: reset type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION GLB_DSP_Peripheral_Reset(GLB_DSP_PERIPHERAL_Type periPart) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_DSP_PERIPHERAL_TYPE(periPart)); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_MM_PERI); - tmpVal &= ~(1 << periPart); - BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_MM_PERI, tmpVal); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_MM_PERI); - tmpVal |= (1 << periPart); - BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_MM_PERI, tmpVal); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_MM_PERI); - tmpVal &= ~(1 << periPart); - BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_MM_PERI, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief dsp2 sub reset - * - * @param dsp2Part: reset type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION GLB_DSP_DSP2_Sub_Reset(GLB_DSP_DSP2_SUB_Type dsp2Part) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_DSP_DSP2_SUB_TYPE(dsp2Part)); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_DSP2_SUB); - tmpVal &= ~(1 << dsp2Part); - BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_DSP2_SUB, tmpVal); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_DSP2_SUB); - tmpVal |= (1 << dsp2Part); - BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_DSP2_SUB, tmpVal); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_DSP2_SUB); - tmpVal &= ~(1 << dsp2Part); - BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_DSP2_SUB, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief codec sub reset - * - * @param codecPart: reset type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION GLB_DSP_Codec_Sub_Reset(GLB_DSP_CODEC_SUB_Type codecPart) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_DSP_CODEC_SUB_TYPE(codecPart)); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_CODEC_SUB); - tmpVal &= ~(1 << codecPart); - BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_CODEC_SUB, tmpVal); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_CODEC_SUB); - tmpVal |= (1 << codecPart); - BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_CODEC_SUB, tmpVal); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_CODEC_SUB); - tmpVal &= ~(1 << codecPart); - BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_CODEC_SUB, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief image sensor reset - * - * @param imageSensorPart: reset type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION GLB_DSP_Image_Sensor_Reset(GLB_DSP_IMAGE_SENSOR_Type imageSensorPart) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_DSP_IMAGE_SENSOR_TYPE(imageSensorPart)); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_IMAGE_SENSOR_CTRL); - tmpVal &= ~(1 << imageSensorPart); - BL_WR_REG(MM_GLB_BASE, MM_GLB_IMAGE_SENSOR_CTRL, tmpVal); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_IMAGE_SENSOR_CTRL); - tmpVal |= (1 << imageSensorPart); - BL_WR_REG(MM_GLB_BASE, MM_GLB_IMAGE_SENSOR_CTRL, tmpVal); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_IMAGE_SENSOR_CTRL); - tmpVal &= ~(1 << imageSensorPart); - BL_WR_REG(MM_GLB_BASE, MM_GLB_IMAGE_SENSOR_CTRL, tmpVal); - - return SUCCESS; -} - -/*@} end of group GLB_Public_Functions */ - -/*@} end of group GLB */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_glb_pll.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_glb_pll.c deleted file mode 100644 index 39bc803983..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_glb_pll.c +++ /dev/null @@ -1,3050 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_glb_pll.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_clock.h" -#include "bl808_glb.h" -#include "bl808_aon.h" -#include "bl808_hbn.h" -#include "bl808_pds.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup GLB - * @{ - */ - -/** @defgroup GLB_Private_Macros - * @{ - */ -#define GLB_CLK_SET_DUMMY_WAIT \ - { \ - __NOP(); \ - __NOP(); \ - __NOP(); \ - __NOP(); \ - __NOP(); \ - __NOP(); \ - __NOP(); \ - __NOP(); \ - } -#define GLB_CLK_SET_DUMMY_TIMEOUT (0xFF) -#define GLB_FREQ_RC32M (32000000) - -/*@} end of group GLB_Private_Macros */ - -/** @defgroup GLB_Private_Types - * @{ - */ - -/*@} end of group GLB_Private_Types */ - -/** @defgroup GLB_Private_Variables - * @{ - */ - - - -/* WiFi PLL Config*/ -const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION wifiPllBasicCfg_32M_38P4M_40M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllIntFracSw = 0, /*!< pll_int_frac_sw */ - .clkpllIcp1u = 0, /*!< pll_icp_1u */ - .clkpllIcp5u = 2, /*!< pll_icp_5u */ - .clkpllRz = 3, /*!< pll_rz */ - .clkpllCz = 1, /*!< pll_cz */ - .clkpllC3 = 2, /*!< pll_c3 */ - .clkpllR4Short = 1, /*!< pll_r4_short */ - .clkpllC4En = 0, /*!< pll_r4_en */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllSdmCtrlHw = 1, /*!< pll_sdm_ctrl_hw */ - .clkpllSdmBypass = 1, /*!< pll_sdm_bypass */ -}; -const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION wifiPllBasicCfg_24M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllIntFracSw = 0, /*!< pll_int_frac_sw */ - .clkpllIcp1u = 0, /*!< pll_icp_1u */ - .clkpllIcp5u = 2, /*!< pll_icp_5u */ - .clkpllRz = 3, /*!< pll_rz */ - .clkpllCz = 1, /*!< pll_cz */ - .clkpllC3 = 2, /*!< pll_c3 */ - .clkpllR4Short = 1, /*!< pll_r4_short */ - .clkpllC4En = 0, /*!< pll_r4_en */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllSdmCtrlHw = 1, /*!< pll_sdm_ctrl_hw */ - .clkpllSdmBypass = 1, /*!< pll_sdm_bypass */ -}; -const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION wifiPllBasicCfg_26M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllIntFracSw = 1, /*!< pll_int_frac_sw */ - .clkpllIcp1u = 1, /*!< pll_icp_1u */ - .clkpllIcp5u = 0, /*!< pll_icp_5u */ - .clkpllRz = 5, /*!< pll_rz */ - .clkpllCz = 2, /*!< pll_cz */ - .clkpllC3 = 2, /*!< pll_c3 */ - .clkpllR4Short = 0, /*!< pll_r4_short */ - .clkpllC4En = 1, /*!< pll_r4_en */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllSdmCtrlHw = 0, /*!< pll_sdm_ctrl_hw */ - .clkpllSdmBypass = 0, /*!< pll_sdm_bypass */ -}; -const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION wifiPllCfg_960M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &wifiPllBasicCfg_24M, 0x1400000 }, /*!< XTAL is 24M */ - { &wifiPllBasicCfg_32M_38P4M_40M, 0x1E00000 }, /*!< XTAL is 32M */ - { &wifiPllBasicCfg_32M_38P4M_40M, 0x1900000 }, /*!< XTAL is 38.4M */ - { &wifiPllBasicCfg_32M_38P4M_40M, 0x1800000 }, /*!< XTAL is 40M */ - { &wifiPllBasicCfg_26M, 0x1276276 }, /*!< XTAL is 26M */ - { &wifiPllBasicCfg_32M_38P4M_40M, 0x1E00000 }, /*!< XTAL is RC32M */ -}; - -/* Audio PLL Config*/ -const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION audioPllBasicCfg_24M_26M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllIntFracSw = 1, /*!< pll_int_frac_sw */ - .clkpllIcp1u = 1, /*!< pll_icp_1u */ - .clkpllIcp5u = 0, /*!< pll_icp_5u */ - .clkpllRz = 5, /*!< pll_rz */ - .clkpllCz = 2, /*!< pll_cz */ - .clkpllC3 = 2, /*!< pll_c3 */ - .clkpllR4Short = 0, /*!< pll_r4_short */ - .clkpllC4En = 1, /*!< pll_r4_en */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 3, /*!< pll_vco_speed */ - .clkpllSdmCtrlHw = 0, /*!< pll_sdm_ctrl_hw */ - .clkpllSdmBypass = 0, /*!< pll_sdm_bypass */ -}; -const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION audioPllBasicCfg_32M_38P4M_40M = { - .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */ - .clkpllIntFracSw = 1, /*!< pll_int_frac_sw */ - .clkpllIcp1u = 1, /*!< pll_icp_1u */ - .clkpllIcp5u = 0, /*!< pll_icp_5u */ - .clkpllRz = 5, /*!< pll_rz */ - .clkpllCz = 2, /*!< pll_cz */ - .clkpllC3 = 2, /*!< pll_c3 */ - .clkpllR4Short = 0, /*!< pll_r4_short */ - .clkpllC4En = 1, /*!< pll_r4_en */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 3, /*!< pll_vco_speed */ - .clkpllSdmCtrlHw = 0, /*!< pll_sdm_ctrl_hw */ - .clkpllSdmBypass = 0, /*!< pll_sdm_bypass */ -}; -const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION audioPllCfg_442P368M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &audioPllBasicCfg_24M_26M, 0x126E9 }, /*!< XTAL is 24M */ - { &audioPllBasicCfg_32M_38P4M_40M, 0x1BA5E }, /*!< XTAL is 32M */ - { &audioPllBasicCfg_32M_38P4M_40M, 0x170A3 }, /*!< XTAL is 38.4M */ - { &audioPllBasicCfg_32M_38P4M_40M, 0x161E5 }, /*!< XTAL is 40M */ - { &audioPllBasicCfg_24M_26M, 0x1103A }, /*!< XTAL is 26M */ - { &audioPllBasicCfg_32M_38P4M_40M, 0x1BA5E }, /*!< XTAL is RC32M */ -}; -const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION audioPllCfg_451P584M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &audioPllBasicCfg_24M_26M, 0x12D0E }, /*!< XTAL is 24M */ - { &audioPllBasicCfg_32M_38P4M_40M, 0x1C395 }, /*!< XTAL is 32M */ - { &audioPllBasicCfg_32M_38P4M_40M, 0x17851 }, /*!< XTAL is 38.4M */ - { &audioPllBasicCfg_32M_38P4M_40M, 0x16944 }, /*!< XTAL is 40M */ - { &audioPllBasicCfg_24M_26M, 0x115E5 }, /*!< XTAL is 26M */ - { &audioPllBasicCfg_32M_38P4M_40M, 0x1C395 }, /*!< XTAL is RC32M */ -}; - -/* CPU PLL Config*/ -const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION cpuPllBasicCfg_24M_26M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllIntFracSw = 1, /*!< pll_int_frac_sw */ - .clkpllIcp1u = 1, /*!< pll_icp_1u */ - .clkpllIcp5u = 0, /*!< pll_icp_5u */ - .clkpllRz = 5, /*!< pll_rz */ - .clkpllCz = 2, /*!< pll_cz */ - .clkpllC3 = 2, /*!< pll_c3 */ - .clkpllR4Short = 0, /*!< pll_r4_short */ - .clkpllC4En = 1, /*!< pll_r4_en */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 3, /*!< pll_vco_speed */ - .clkpllSdmCtrlHw = 0, /*!< pll_sdm_ctrl_hw */ - .clkpllSdmBypass = 0, /*!< pll_sdm_bypass */ -}; -const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION cpuPllBasicCfg_32M_38P4M_40M = { - .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */ - .clkpllIntFracSw = 1, /*!< pll_int_frac_sw */ - .clkpllIcp1u = 1, /*!< pll_icp_1u */ - .clkpllIcp5u = 0, /*!< pll_icp_5u */ - .clkpllRz = 5, /*!< pll_rz */ - .clkpllCz = 2, /*!< pll_cz */ - .clkpllC3 = 2, /*!< pll_c3 */ - .clkpllR4Short = 0, /*!< pll_r4_short */ - .clkpllC4En = 1, /*!< pll_r4_en */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 3, /*!< pll_vco_speed */ - .clkpllSdmCtrlHw = 0, /*!< pll_sdm_ctrl_hw */ - .clkpllSdmBypass = 0, /*!< pll_sdm_bypass */ -}; -const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION cpuPllCfg_380M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &cpuPllBasicCfg_24M_26M, 0xFD55 }, /*!< XTAL is 24M */ - { &cpuPllBasicCfg_32M_38P4M_40M, 0x17C00 }, /*!< XTAL is 32M */ - { &cpuPllBasicCfg_32M_38P4M_40M, 0x13CAA }, /*!< XTAL is 38.4M */ - { &cpuPllBasicCfg_32M_38P4M_40M, 0x13000 }, /*!< XTAL is 40M */ - { &cpuPllBasicCfg_24M_26M, 0xE9D8 }, /*!< XTAL is 26M */ - { &cpuPllBasicCfg_32M_38P4M_40M, 0x17C00 }, /*!< XTAL is RC32M */ -}; -const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION cpuPllCfg_400M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &cpuPllBasicCfg_24M_26M, 0x10AAA }, /*!< XTAL is 24M */ - { &cpuPllBasicCfg_32M_38P4M_40M, 0x19000 }, /*!< XTAL is 32M */ - { &cpuPllBasicCfg_32M_38P4M_40M, 0x14D55 }, /*!< XTAL is 38.4M */ - { &cpuPllBasicCfg_32M_38P4M_40M, 0x14000 }, /*!< XTAL is 40M */ - { &cpuPllBasicCfg_24M_26M, 0xF627 }, /*!< XTAL is 26M */ - { &cpuPllBasicCfg_32M_38P4M_40M, 0x19000 }, /*!< XTAL is RC32M */ -}; -const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION cpuPllCfg_480M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &cpuPllBasicCfg_24M_26M, 0x14000 }, /*!< XTAL is 24M */ - { &cpuPllBasicCfg_32M_38P4M_40M, 0x1E000 }, /*!< XTAL is 32M */ - { &cpuPllBasicCfg_32M_38P4M_40M, 0x19000 }, /*!< XTAL is 38.4M */ - { &cpuPllBasicCfg_32M_38P4M_40M, 0x18000 }, /*!< XTAL is 40M */ - { &cpuPllBasicCfg_24M_26M, 0x12762 }, /*!< XTAL is 26M */ - { &cpuPllBasicCfg_32M_38P4M_40M, 0x1E000 }, /*!< XTAL is RC32M */ -}; - -/* MIPI PLL Config*/ -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION mipiPllBasicCfg_24M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 0, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 0, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION mipiPllBasicCfg_32M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 0, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 0, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION mipiPllBasicCfg_38P4M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 0, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 0, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION mipiPllBasicCfg_40M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 0, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 0, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION mipiPllBasicCfg_26M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 0, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 0, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION mipiPllCfg_1500M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &mipiPllBasicCfg_24M, 0x1F400 }, /*!< XTAL is 24M */ - { &mipiPllBasicCfg_32M, 0x2EE00 }, /*!< XTAL is 32M */ - { &mipiPllBasicCfg_38P4M, 0x27100 }, /*!< XTAL is 38.4M */ - { &mipiPllBasicCfg_40M, 0x25800 }, /*!< XTAL is 40M */ - { &mipiPllBasicCfg_26M, 0x1CD89 }, /*!< XTAL is 26M */ - { &mipiPllBasicCfg_32M, 0x2EE00 }, /*!< XTAL is RC32M */ -}; - -/* uhs PLL 2100 Config*/ -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_24M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_32M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_38P4M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_40M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_26M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_2100M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &uhsPll2100BasicCfg_24M, 0x2BC00 }, /*!< XTAL is 24M */ - { &uhsPll2100BasicCfg_32M, 0x41A00 }, /*!< XTAL is 32M */ - { &uhsPll2100BasicCfg_38P4M, 0x36B00 }, /*!< XTAL is 38.4M */ - { &uhsPll2100BasicCfg_40M, 0x34800 }, /*!< XTAL is 40M */ - { &uhsPll2100BasicCfg_26M, 0x28627 }, /*!< XTAL is 26M */ - { &uhsPll2100BasicCfg_32M, 0x41A00 }, /*!< XTAL is RC32M */ -}; - -/* uhs PLL 1400 Config*/ -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_24M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 4, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1400/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_32M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 4, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1400/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_38P4M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 4, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1400/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_40M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 4, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1400/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_26M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 4, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1400/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1400M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &uhsPll1400MCfg_24M, 0x1D2AA }, /*!< XTAL is 24M */ - { &uhsPll1400MCfg_32M, 0x2BC00 }, /*!< XTAL is 32M */ - { &uhsPll1400MCfg_38P4M, 0x24755 }, /*!< XTAL is 38.4M */ - { &uhsPll1400MCfg_40M, 0x23000 }, /*!< XTAL is 40M */ - { &uhsPll1400MCfg_26M, 0x1AEC4 }, /*!< XTAL is 26M */ - { &uhsPll1400MCfg_32M, 0x2BC00 }, /*!< XTAL is RC32M */ -}; - -/* uhs PLL 1500 Config*/ -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_24M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1500/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_32M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1500/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_38P4M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1500/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_40M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1500/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_26M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1500/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1500M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &uhsPll1500MCfg_24M, 0x1F400 }, /*!< XTAL is 24M */ - { &uhsPll1500MCfg_32M, 0x2EE00 }, /*!< XTAL is 32M */ - { &uhsPll1500MCfg_38P4M, 0x27100 }, /*!< XTAL is 38.4M */ - { &uhsPll1500MCfg_40M, 0x25800 }, /*!< XTAL is 40M */ - { &uhsPll1500MCfg_26M, 0x1CD89 }, /*!< XTAL is 26M */ - { &uhsPll1500MCfg_32M, 0x2EE00 }, /*!< XTAL is RC32M */ -}; - -/* uhs PLL 1600 Config*/ -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_24M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1600/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_32M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1600/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_38P4M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1600/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_40M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1600/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_26M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1600/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1600M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &uhsPll1600BasicCfg_24M, 0x21555 }, /*!< XTAL is 24M */ - { &uhsPll1600BasicCfg_32M, 0x32000 }, /*!< XTAL is 32M */ - { &uhsPll1600BasicCfg_38P4M, 0x29AAA }, /*!< XTAL is 38.4M */ - { &uhsPll1600BasicCfg_40M, 0x28000 }, /*!< XTAL is 40M */ - { &uhsPll1600BasicCfg_26M, 0x1EC4E }, /*!< XTAL is 26M */ - { &uhsPll1600BasicCfg_32M, 0x32000 }, /*!< XTAL is RC32M */ -}; - -/* uhs PLL 400 Config*/ -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_24M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 0, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 400/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_32M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 0, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 400/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_38P4M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 0, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 400/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_40M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 0, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 400/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_26M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 0, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 400/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_400M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &uhsPll400BasicCfg_24M, 0x8555 }, /*!< XTAL is 24M */ - { &uhsPll400BasicCfg_32M, 0xC800 }, /*!< XTAL is 32M */ - { &uhsPll400BasicCfg_38P4M, 0xA6AA }, /*!< XTAL is 38.4M */ - { &uhsPll400BasicCfg_40M, 0xA000 }, /*!< XTAL is 40M */ - { &uhsPll400BasicCfg_26M, 0x7B13 }, /*!< XTAL is 26M */ - { &uhsPll400BasicCfg_32M, 0xC800 }, /*!< XTAL is RC32M */ -}; - -/* uhs PLL 667 Config*/ -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_24M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 0, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 667/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_32M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 667/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_38P4M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 667/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_40M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 667/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_26M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 0, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 667/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_667M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &uhsPll667BasicCfg_24M, 0xDE55 }, /*!< XTAL is 24M */ - { &uhsPll667BasicCfg_32M, 0x14D80 }, /*!< XTAL is 32M */ - { &uhsPll667BasicCfg_38P4M, 0x115EA }, /*!< XTAL is 38.4M */ - { &uhsPll667BasicCfg_40M, 0x10ACC }, /*!< XTAL is 40M */ - { &uhsPll667BasicCfg_26M, 0xCD3B }, /*!< XTAL is 26M */ - { &uhsPll667BasicCfg_32M, 0x14D80 }, /*!< XTAL is RC32M */ -}; - -/* uhs PLL 800 Config*/ -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_24M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 2, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 800/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_32M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 2, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 800/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_38P4M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 2, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 800/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_40M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 2, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 800/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_26M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 0, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 2, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 800/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_800M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &uhsPll800BasicCfg_24M, 0x10AAA }, /*!< XTAL is 24M */ - { &uhsPll800BasicCfg_32M, 0x19000 }, /*!< XTAL is 32M */ - { &uhsPll800BasicCfg_38P4M, 0x14D55 }, /*!< XTAL is 38.4M */ - { &uhsPll800BasicCfg_40M, 0x14000 }, /*!< XTAL is 40M */ - { &uhsPll800BasicCfg_26M, 0xF627 }, /*!< XTAL is 26M */ - { &uhsPll800BasicCfg_32M, 0x19000 }, /*!< XTAL is RC32M */ -}; - -/* uhs PLL 1066 Config*/ -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_24M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 3, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1066/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_32M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 3, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1066/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_38P4M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 3, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1066/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_40M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 3, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1066/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_26M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 3, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1066/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1066M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &uhsPll1066BasicCfg_24M, 0x16355 }, /*!< XTAL is 24M */ - { &uhsPll1066BasicCfg_32M, 0x21500 }, /*!< XTAL is 32M */ - { &uhsPll1066BasicCfg_38P4M, 0x1BC2A }, /*!< XTAL is 38.4M */ - { &uhsPll1066BasicCfg_40M, 0x1AA66 }, /*!< XTAL is 40M */ - { &uhsPll1066BasicCfg_26M, 0x14800 }, /*!< XTAL is 26M */ - { &uhsPll1066BasicCfg_32M, 0x21500 }, /*!< XTAL is RC32M */ -}; - -/* uhs PLL 2000 Config*/ -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_24M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_32M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_38P4M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_40M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_26M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_2000M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &uhsPll2000BasicCfg_24M, 0x29AAA }, /*!< XTAL is 24M */ - { &uhsPll2000BasicCfg_32M, 0x3E800 }, /*!< XTAL is 32M */ - { &uhsPll2000BasicCfg_38P4M, 0x34155 }, /*!< XTAL is 38.4M */ - { &uhsPll2000BasicCfg_40M, 0x32000 }, /*!< XTAL is 40M */ - { &uhsPll2000BasicCfg_26M, 0x26762 }, /*!< XTAL is 26M */ - { &uhsPll2000BasicCfg_32M, 0x3E800 }, /*!< XTAL is RC32M */ -}; - -/*@} end of group GLB_Private_Variables */ - -/** @defgroup GLB_Global_Variables - * @{ - */ - -/*@} end of group GLB_Global_Variables */ - -/** @defgroup GLB_Private_Fun_Declaration - * @{ - */ - -/*@} end of group GLB_Private_Fun_Declaration */ - -/** @defgroup GLB_Private_Functions - * @{ - */ - -/*@} end of group GLB_Private_Functions */ - -/** @defgroup GLB_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief set mcu muxpll 160M selection - * - * @param clkSel: clock selection - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_MCU_Muxpll_160M_Sel(GLB_MCU_MUXPLL_160M_CLK_SEL_Type clkSel) -{ - uint32_t tmpVal; - - CHECK_PARAM(IS_GLB_MCU_MUXPLL_160M_CLK_SEL_TYPE(clkSel)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_TOP_MUXPLL_160M_SEL, clkSel); - BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG1, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get mcu muxpll 160M selection - * - * @param None - * - * @return 160M mux select value - * -*******************************************************************************/ -GLB_MCU_MUXPLL_160M_CLK_SEL_Type ATTR_CLOCK_SECTION GLB_Get_MCU_Muxpll_160M_Sel(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1); - return (GLB_MCU_MUXPLL_160M_CLK_SEL_Type)(BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_TOP_MUXPLL_160M_SEL)); -} - -/****************************************************************************/ /** - * @brief set top muxpll 80M selection - * - * @param clkSel: clock selection - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_MCU_Muxpll_80M_Sel(GLB_MCU_MUXPLL_80M_CLK_SEL_Type clkSel) -{ - uint32_t tmpVal; - - CHECK_PARAM(IS_GLB_MCU_MUXPLL_80M_CLK_SEL_TYPE(clkSel)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_TOP_MUXPLL_80M_SEL, clkSel); - BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG1, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get mcu muxpll 80M selection - * - * @param None - * - * @return 80M mux select value - * -*******************************************************************************/ -GLB_MCU_MUXPLL_80M_CLK_SEL_Type ATTR_CLOCK_SECTION GLB_Get_MCU_Muxpll_80M_Sel(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1); - return (GLB_MCU_MUXPLL_80M_CLK_SEL_Type)(BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_TOP_MUXPLL_80M_SEL)); -} - -/****************************************************************************/ /** - * @brief set dsp muxpll 320M selection - * - * @param clkSel: clock selection - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_Muxpll_320M_Sel(GLB_DSP_MUXPLL_320M_CLK_SEL_Type clkSel) -{ - uint32_t tmpVal; - - CHECK_PARAM(IS_GLB_DSP_MUXPLL_320M_CLK_SEL_TYPE(clkSel)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_MM_MUXPLL_320M_SEL, clkSel); - BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG1, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get dsp muxpll 320M selection - * - * @param None - * - * @return dsp 320M mux select value - * -*******************************************************************************/ -GLB_DSP_MUXPLL_320M_CLK_SEL_Type ATTR_CLOCK_SECTION GLB_Get_DSP_Muxpll_320M_Sel(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1); - return (GLB_DSP_MUXPLL_320M_CLK_SEL_Type)(BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_MM_MUXPLL_320M_SEL)); -} - -/****************************************************************************/ /** - * @brief set dsp muxpll 240M selection - * - * @param clkSel: clock selection - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_Muxpll_240M_Sel(GLB_DSP_MUXPLL_240M_CLK_SEL_Type clkSel) -{ - uint32_t tmpVal; - - CHECK_PARAM(IS_GLB_DSP_MUXPLL_240M_CLK_SEL_TYPE(clkSel)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_MM_MUXPLL_240M_SEL, clkSel); - BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG1, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get dsp muxpll 240M selection - * - * @param None - * - * @return dsp 240M mux select value - * -*******************************************************************************/ -GLB_DSP_MUXPLL_240M_CLK_SEL_Type ATTR_CLOCK_SECTION GLB_Get_DSP_Muxpll_240M_Sel(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1); - return (GLB_DSP_MUXPLL_240M_CLK_SEL_Type)(BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_MM_MUXPLL_240M_SEL)); -} - -/****************************************************************************/ /** - * @brief set dsp muxpll 160M selection - * - * @param clkSel: clock selection - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_Muxpll_160M_Sel(GLB_DSP_MUXPLL_160M_CLK_SEL_Type clkSel) -{ - uint32_t tmpVal; - - CHECK_PARAM(IS_GLB_DSP_MUXPLL_160M_CLK_SEL_TYPE(clkSel)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_MM_MUXPLL_160M_SEL, clkSel); - BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG1, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get dsp muxpll 160M selection - * - * @param None - * - * @return dsp 160M mux select value - * -*******************************************************************************/ -GLB_DSP_MUXPLL_160M_CLK_SEL_Type ATTR_CLOCK_SECTION GLB_Get_DSP_Muxpll_160M_Sel(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1); - return (GLB_DSP_MUXPLL_160M_CLK_SEL_Type)(BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_MM_MUXPLL_160M_SEL)); -} - -/****************************************************************************/ /** - * @brief power on all PLL clock - * - * @param xtalType: XTAL frequency type - * @param pllType: only power on xtal - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Power_On_XTAL_And_PLL_CLK(GLB_XTAL_Type xtalType, GLB_PLL_Type pllType) -{ - uint32_t tmpVal; - GLB_CORE_ID_Type coreType; - HBN_MCU_XCLK_Type mcuXclkSel; - HBN_MCU_ROOT_CLK_Type mcuRootClkSel; - GLB_DSP_XCLK_Type dspXclkSel; - GLB_DSP_ROOT_CLK_Type dspRootClkSel; - volatile GLB_PLL_REF_CLK_Type refClk; - - CHECK_PARAM(IS_GLB_XTAL_TYPE(xtalType)); - CHECK_PARAM((pllType < (GLB_PLL_UHSPLL * 2))); - - if (xtalType == GLB_XTAL_NONE) { - return ERROR; - } - - if (xtalType != GLB_XTAL_RC32M) { - /* power on xtal first */ - AON_Power_On_XTAL(); - } - - coreType = GLB_Get_Core_Type(); - if ((GLB_CORE_ID_D0 == coreType)) { - /* D0 */ - /* Before config XTAL and PLL ,make sure root clk is from RC32M */ - dspXclkSel = GLB_Get_DSP_XCLK_Sel(); - dspRootClkSel = GLB_Get_DSP_ROOT_CLK_Sel(); - if ((dspXclkSel != GLB_DSP_XCLK_RC32M) || (dspRootClkSel != GLB_DSP_ROOT_CLK_XCLK)) { - GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_RC32M); - GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_XCLK); - } - GLB_Set_DSP_System_CLK_Div(0, 0); - } else { - /* M0 or LP or invalid(use M0 instead) */ - /* Before config XTAL and PLL ,make sure root clk is from RC32M */ - mcuXclkSel = HBN_Get_MCU_XCLK_Sel(); - mcuRootClkSel = HBN_Get_MCU_Root_CLK_Sel(); - if ((mcuXclkSel != HBN_MCU_XCLK_RC32M) || (mcuRootClkSel != HBN_MCU_ROOT_CLK_XCLK)) { - HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M); - HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK); - } - GLB_Set_MCU_System_CLK_Div(0, 0, 0); - } - - HBN_Set_Xtal_Type(xtalType); - - if (GLB_PLL_NONE == pllType) { - GLB_CLK_SET_DUMMY_WAIT; - return SUCCESS; - } - - if (xtalType == GLB_XTAL_RC32M) { - refClk = GLB_PLL_REFCLK_RC32M; - } else { - refClk = GLB_PLL_REFCLK_XTAL; - } - - /* power on wifipll */ - if (pllType & GLB_PLL_WIFIPLL) { - GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_WIFIPLL); - GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_WIFIPLL, refClk); - GLB_Power_On_WAC_PLL(GLB_WAC_PLL_WIFIPLL, &wifiPllCfg_960M[xtalType], 0); - } - - /* power on aupll */ - if (pllType & GLB_PLL_AUPLL) { - GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_AUPLL); - GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_AUPLL, refClk); - GLB_Power_On_WAC_PLL(GLB_WAC_PLL_AUPLL, &audioPllCfg_442P368M[xtalType], 0); - } - - /* power on cpupll */ - if (pllType & GLB_PLL_CPUPLL) { - GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_CPUPLL); - GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_CPUPLL, refClk); - GLB_Power_On_WAC_PLL(GLB_WAC_PLL_CPUPLL, &cpuPllCfg_380M[xtalType], 0); - } - - /* power on mipipll */ - if (pllType & GLB_PLL_MIPIPLL) { - GLB_Power_Off_MU_PLL(GLB_MU_PLL_MIPIPLL); - GLB_MU_PLL_Ref_Clk_Sel(GLB_MU_PLL_MIPIPLL, refClk); - GLB_Power_On_MU_PLL(GLB_MU_PLL_MIPIPLL, &mipiPllCfg_1500M[xtalType], 0); - } - - /* power on uhspll */ - if (pllType & GLB_PLL_UHSPLL) { - GLB_Power_Off_MU_PLL(GLB_MU_PLL_UHSPLL); - GLB_MU_PLL_Ref_Clk_Sel(GLB_MU_PLL_UHSPLL, refClk); - GLB_Power_On_MU_PLL(GLB_MU_PLL_UHSPLL, &uhsPllCfg_2100M[xtalType], 0); - } - - arch_delay_us(75); - - if (xtalType != GLB_XTAL_RC32M) { - /* if power on xtal, always set xclk from xtal */ - HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_XTAL); - GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_XTAL); - } - - /* enable all PLL clock output */ - /* GLB reg_pll_en = 1, cannot be zero */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG0); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_PLL_EN); - BL_WR_REG(GLB_BASE, GLB_SYS_CFG0, tmpVal); - /* MM_GLB reg_pll_en = 1, cannot be zero */ - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU); - tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_PLL_EN); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal); - - GLB_CLK_SET_DUMMY_WAIT; - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief GLB power off wifi audio cpu PLL - * - * @param pllType: PLL XTAL type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_Type pllType) -{ - uint32_t REG_PLL_BASE_ADDRESS = 0; - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_WAC_PLL_TYPE(pllType)); - - switch (pllType) { - case GLB_WAC_PLL_WIFIPLL: - REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_WIFI_PLL_CFG0_OFFSET; - break; - case GLB_WAC_PLL_AUPLL: - REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_AUDIO_PLL_CFG0_OFFSET; - break; - case GLB_WAC_PLL_CPUPLL: - REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_CPU_PLL_CFG0_OFFSET; - break; - default: - REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_AUDIO_PLL_CFG0_OFFSET; - break; - } - - /* cfg0 : pu_aupll=0 */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL, 0); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - - /* cfg0 : pu_aupll_sfreg=0 */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL_SFREG, 0); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief GLB wifi audio cpu PLL ref clock select - * - * @param pllType: PLL XTAL type - * @param refClk: PLL ref clock select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_Type pllType, GLB_PLL_REF_CLK_Type refClk) -{ - uint32_t REG_PLL_BASE_ADDRESS = 0; - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_WAC_PLL_TYPE(pllType)); - CHECK_PARAM(IS_GLB_PLL_REF_CLK_TYPE(refClk)); - - switch (pllType) { - case GLB_WAC_PLL_WIFIPLL: - REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_WIFI_PLL_CFG0_OFFSET; - break; - case GLB_WAC_PLL_AUPLL: - REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_AUDIO_PLL_CFG0_OFFSET; - break; - case GLB_WAC_PLL_CPUPLL: - REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_CPU_PLL_CFG0_OFFSET; - break; - default: - REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_AUDIO_PLL_CFG0_OFFSET; - break; - } - - /* xxxpll_refclk_sel */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1); - if ((GLB_WAC_PLL_WIFIPLL == pllType) && (GLB_PLL_REFCLK_XTAL == refClk)) { - /* wifipll_refclk_sel different from other's pll, 1 means xtal */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_REFCLK_SEL, 1); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_REFCLK_SEL, refClk); - } - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief GLB power on PLL - * - * @param pllType: PLL XTAL type - * @param cfg: GLB PLL configuration - * @param waitStable: wait PLL clock stable - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Power_On_WAC_PLL(GLB_WAC_PLL_Type pllType, const GLB_WAC_PLL_Cfg_Type *const cfg, uint8_t waitStable) -{ - uint32_t REG_PLL_BASE_ADDRESS = 0; - uint32_t tmpVal = 0; - - /* unknown */ - CHECK_PARAM(IS_GLB_WAC_PLL_TYPE(pllType)); - - switch (pllType) { - case GLB_WAC_PLL_WIFIPLL: - REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_WIFI_PLL_CFG0_OFFSET; - break; - case GLB_WAC_PLL_AUPLL: - REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_AUDIO_PLL_CFG0_OFFSET; - break; - case GLB_WAC_PLL_CPUPLL: - REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_CPU_PLL_CFG0_OFFSET; - break; - default: - REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_AUDIO_PLL_CFG0_OFFSET; - break; - } - - /* Step1:config parameter */ - /* cfg1:Set aupll_refclk_sel and aupll_refdiv_ratio */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_REFDIV_RATIO, cfg->basicCfg->clkpllRefdivRatio); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal); - - /* cfg2:Set aupll_int_frac_sw,aupll_icp_1u,aupll_icp_5u */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_INT_FRAC_SW, cfg->basicCfg->clkpllIntFracSw); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_ICP_1U, cfg->basicCfg->clkpllIcp1u); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_ICP_5U, cfg->basicCfg->clkpllIcp5u); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 2, tmpVal); - - /* cfg3:Set aupll_rz,aupll_cz,aupll_c3,aupll_r4_short,aupll_r4_en */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_RZ, cfg->basicCfg->clkpllRz); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_CZ, cfg->basicCfg->clkpllCz); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_C3, cfg->basicCfg->clkpllC3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_R4_SHORT, cfg->basicCfg->clkpllR4Short); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_C4_EN, cfg->basicCfg->clkpllC4En); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 3, tmpVal); - - /* cfg4:Set aupll_sel_sample_clk */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SEL_SAMPLE_CLK, cfg->basicCfg->clkpllSelSampleClk); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 4, tmpVal); - - /* cfg5:Set aupll_vco_speed */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 5); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_VCO_SPEED, cfg->basicCfg->clkpllVcoSpeed); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 5, tmpVal); - - /* cfg6:Set aupll_sdm_bypass,aupll_sdmin */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 6); - if (GLB_WAC_PLL_WIFIPLL == pllType) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_SDM_CTRL_HW, cfg->basicCfg->clkpllSdmCtrlHw); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_SDM_BYPASS, cfg->basicCfg->clkpllSdmBypass); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_SDMIN, cfg->clkpllSdmin); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_BYPASS, cfg->basicCfg->clkpllSdmBypass); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDMIN, cfg->clkpllSdmin); - } - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 6, tmpVal); - - /* Step2:config pu */ - /* cfg0 : pu_aupll_sfreg=1 */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL_SFREG, 1); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - - /* delay > 2us */ - arch_delay_us(3); - - /* cfg0 : pu_wifipll=1 */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL, 1); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - - /* delay > 2us */ - arch_delay_us(3); - - /* toggle sdm_reset (pulse 0 > 1us) */ - /* cfg0 : aupll_sdm_reset */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_RSTB, 1); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - arch_delay_us(2); - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_RSTB, 0); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - arch_delay_us(2); - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_RSTB, 1); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - - /* Step3:reset pll */ - /* cfg0 : toggle aupll_reset_fbdv, pulse 0 > 1us */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_FBDV_RSTB, 1); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - arch_delay_us(2); - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_FBDV_RSTB, 0); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - arch_delay_us(2); - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_FBDV_RSTB, 1); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - - /* aupll : cfg1, aupll_postdiv = 0x12 or 0x14 */ - if (GLB_WAC_PLL_AUPLL == pllType) { - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1); - if ((cfg->clkpllSdmin==0x12D0E)||(cfg->clkpllSdmin==0x1C395)||(cfg->clkpllSdmin==0x17851)||(cfg->clkpllSdmin==0x16944)||(cfg->clkpllSdmin==0x115E5)) { - /* 451.548 */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_POSTDIV, 0x14); - } else { - /* 442.368 */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_POSTDIV, 0x12); - } - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal); - } - - /* Step4:enable output clock */ - /* wifipll : cfg5, wifipll_vco_div3_en=1 */ - if (GLB_WAC_PLL_WIFIPLL == pllType) { - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 5); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_VCO_DIV3_EN); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 5, tmpVal); - } - /* cfg8 : wifipll->wifipll_en_ctrl_hw=1 */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 8); - if (GLB_WAC_PLL_WIFIPLL == pllType) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_EN_CTRL_HW, 1); - } - /* cfg8 : wifipll/aupll/cpupll clock enable */ - switch (pllType) { - case GLB_WAC_PLL_WIFIPLL: - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV4); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV5); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV6); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV8); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV10); - break; - case GLB_WAC_PLL_AUPLL: - tmpVal = BL_SET_REG_BIT(tmpVal, CCI_AUPLL_EN_DIV1); - tmpVal = BL_SET_REG_BIT(tmpVal, CCI_AUPLL_EN_DIV2); - tmpVal = BL_SET_REG_BIT(tmpVal, CCI_AUPLL_EN_DIV2P5); - tmpVal = BL_SET_REG_BIT(tmpVal, CCI_AUPLL_EN_DIV5); - tmpVal = BL_SET_REG_BIT(tmpVal, CCI_AUPLL_EN_DIV6); - break; - case GLB_WAC_PLL_CPUPLL: - tmpVal = BL_SET_REG_BIT(tmpVal, CCI_CPUPLL_EN_DIV1); - tmpVal = BL_SET_REG_BIT(tmpVal, CCI_CPUPLL_EN_DIV2); - tmpVal = BL_SET_REG_BIT(tmpVal, CCI_CPUPLL_EN_DIV2P5); - tmpVal = BL_SET_REG_BIT(tmpVal, CCI_CPUPLL_EN_DIV4); - tmpVal = BL_SET_REG_BIT(tmpVal, CCI_CPUPLL_EN_DIV5); - break; - default: - break; - } - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 8, tmpVal); - - if (waitStable) { - /* Wait 1.5*30us */ - arch_delay_us(45); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief GLB enable or disable USB clock - * - * @param enable: ENABLE or DISABLE - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_USB_CLK_From_WIFIPLL(uint8_t enable) -{ - uint32_t tmpVal = 0; - - /* pu_usbpll_mmdiv */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_WIFI_PLL_CFG10); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_PU_USBPLL_MMDIV); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_PU_USBPLL_MMDIV); - } - BL_WR_REG(GLB_BASE, GLB_WIFI_PLL_CFG10, tmpVal); - - /* toggle usbpll_rstb */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_WIFI_PLL_CFG10); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_USBPLL_RSTB); - BL_WR_REG(GLB_BASE, GLB_WIFI_PLL_CFG10, tmpVal); - arch_delay_us(2); - tmpVal = BL_RD_REG(GLB_BASE, GLB_WIFI_PLL_CFG10); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_USBPLL_RSTB); - BL_WR_REG(GLB_BASE, GLB_WIFI_PLL_CFG10, tmpVal); - arch_delay_us(2); - tmpVal = BL_RD_REG(GLB_BASE, GLB_WIFI_PLL_CFG10); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_USBPLL_RSTB); - BL_WR_REG(GLB_BASE, GLB_WIFI_PLL_CFG10, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief GLB power off mipi uhs PLL - * - * @param pllType: PLL XTAL type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Power_Off_MU_PLL(GLB_MU_PLL_Type pllType) -{ - uint32_t REG_PLL_BASE_ADDRESS = 0; - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_Power_Off_MU_TYPE(pllType)); - - switch (pllType) { - case GLB_MU_PLL_MIPIPLL: - REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET; - break; - case GLB_MU_PLL_UHSPLL: - REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_UHS_PLL_CFG0_OFFSET; - break; - default: - REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET; - break; - } - - /* cfg0 : pu_aupll=0 */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL, 0); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - - /* cfg0 : pu_aupll_sfreg=0 */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL_SFREG, 0); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief GLB mipi uhs PLL ref clock select - * - * @param pllType: PLL XTAL type - * @param refClk: PLL ref clock select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_MU_PLL_Ref_Clk_Sel(GLB_MU_PLL_Type pllType, GLB_PLL_REF_CLK_Type refClk) -{ - uint32_t REG_PLL_BASE_ADDRESS = 0; - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_WAC_PLL_TYPE(pllType)); - CHECK_PARAM(IS_GLB_PLL_REF_CLK_TYPE(refClk)); - - switch (pllType) { - case GLB_MU_PLL_MIPIPLL: - REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET; - break; - case GLB_MU_PLL_UHSPLL: - REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_UHS_PLL_CFG0_OFFSET; - break; - default: - REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET; - break; - } - - /* xxxpll_refclk_sel */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_REFCLK_SEL, refClk); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief GLB power on PLL - * - * @param pllType: PLL XTAL type - * @param cfg: GLB PLL configuration - * @param waitStable: wait PLL stable - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Power_On_MU_PLL(GLB_MU_PLL_Type pllType, const GLB_MU_PLL_Cfg_Type *const cfg, uint8_t waitStable) -{ - uint32_t REG_PLL_BASE_ADDRESS = 0; - uint32_t tmpVal = 0; - - /* unknown */ - CHECK_PARAM(IS_GLB_WAC_PLL_TYPE(pllType)); - - switch (pllType) { - case GLB_MU_PLL_MIPIPLL: - REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET; - break; - case GLB_MU_PLL_UHSPLL: - REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_UHS_PLL_CFG0_OFFSET; - break; - default: - REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET; - break; - } - - /* Step1:config parameter */ - /* cfg1:Set aupll_refclk_sel and aupll_refdiv_ratio */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_REFDIV_RATIO, cfg->basicCfg->clkpllRefdivRatio); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal); - - /* cfg4:Set aupll_sel_sample_clk */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SEL_SAMPLE_CLK, cfg->basicCfg->clkpllSelSampleClk); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 4, tmpVal); - - /* cfg5:Set aupll_vco_speed */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 5); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_VCO_SPEED, cfg->basicCfg->clkpllVcoSpeed); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 5, tmpVal); - - /* cfg1: uhspll_even_div_en and uhspll_even_div_ratio */ - if (GLB_MU_PLL_UHSPLL == pllType) { - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UHSPLL_EVEN_DIV_EN, cfg->basicCfg->clkpllEvenDivEn); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UHSPLL_EVEN_DIV_RATIO, cfg->basicCfg->clkpllEvenDivRatio); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal); - } - - /* cfg6:Set aupll_sdm_bypass,aupll_sdmin */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 6); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDMIN, cfg->clkpllSdmin); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 6, tmpVal); - - /* Step2:config pu */ - /* cfg0 : pu_aupll_sfreg=1 */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL_SFREG, 1); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - - /* delay > 2us */ - arch_delay_us(3); - - /* cfg0 : pu_wifipll=1 */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL, 1); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - - /* delay > 2us */ - arch_delay_us(3); - - /* toggle sdm_reset (pulse 0 > 1us) */ - /* cfg0 : aupll_sdm_reset */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_RSTB, 1); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - arch_delay_us(2); - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_RSTB, 0); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - arch_delay_us(2); - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_RSTB, 1); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - - /* Step3:reset pll */ - /* cfg0 : toggle aupll_reset_fbdv, pulse 0 > 1us */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_FBDV_RSTB, 1); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - arch_delay_us(2); - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_FBDV_RSTB, 0); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - arch_delay_us(2); - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_FBDV_RSTB, 1); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - - if (waitStable) { - /* Wait 1.5*30us */ - arch_delay_us(45); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Set System clock divider - * - * @param mcuClkDiv: HCLK divider - * @param mcuPBclkDiv: BCLK divider - * @param lpClkDiv: LP clock divider - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_MCU_System_CLK_Div(uint8_t mcuClkDiv, uint8_t mcuPBclkDiv, uint8_t lpClkDiv) -{ - uint32_t tmpVal; - uint32_t timeout = 1024; - HBN_MCU_XCLK_Type xclkSel; - HBN_MCU_ROOT_CLK_Type rootClkSel; - - /* get root clock */ - xclkSel = HBN_Get_MCU_XCLK_Sel(); - rootClkSel = HBN_Get_MCU_Root_CLK_Sel(); - - if ((xclkSel != HBN_MCU_XCLK_RC32M) || (rootClkSel != HBN_MCU_ROOT_CLK_XCLK)) { - HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M); - HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK); - } - - /* config hclk_div=mcuClkDiv */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV, mcuClkDiv); - BL_WR_REG(GLB_BASE, GLB_SYS_CFG0, tmpVal); - - /* config bclk_div=mcuPBclkDiv */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV, mcuPBclkDiv); - BL_WR_REG(GLB_BASE, GLB_SYS_CFG0, tmpVal); - /* bclk act pulse */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV_ACT_PULSE, 1); - BL_WR_REG(GLB_BASE, GLB_SYS_CFG1, tmpVal); - - timeout = 1024; - do { - tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG1); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, GLB_STS_BCLK_PROT_DONE); - } while ((--timeout) && (!tmpVal)); - if (!timeout) { - return ERROR; - } - - /* config lp clock div=lpClkDiv */ - tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG7); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_REG_PICO_DIV, lpClkDiv); - BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG7, tmpVal); - /* bclk act pulse */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PICO_CLK_DIV_ACT_PULSE, 1); - BL_WR_REG(GLB_BASE, GLB_SYS_CFG1, tmpVal); - - timeout = 1024; - do { - tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG1); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, GLB_STS_PICO_CLK_PROT_DONE); - } while ((--timeout) && (!tmpVal)); - if (!timeout) { - return ERROR; - } - - /* recover root clock */ - HBN_Set_MCU_XCLK_Sel(xclkSel); - HBN_Set_MCU_Root_CLK_Sel(rootClkSel); - - GLB_CLK_SET_DUMMY_WAIT; - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Get System clock divider - * - * @param mcuClkDiv: HCLK divider - * @param mcuPBclkDiv: BCLK divider - * @param lpClkDiv: LP clock divider - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Get_MCU_System_CLK_Div(uint8_t *mcuClkDiv, uint8_t *mcuPBclkDiv, uint8_t *lpClkDiv) -{ - *mcuClkDiv = BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_SYS_CFG0), GLB_REG_HCLK_DIV); - *mcuPBclkDiv = BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_SYS_CFG0), GLB_REG_BCLK_DIV); - *lpClkDiv = BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG7), PDS_REG_PICO_DIV); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Set mcu System clock - * - * @param clkFreq: mcu system clock type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_Type clkFreq) -{ - uint32_t tmpVal; - HBN_MCU_XCLK_Type mcuXclkSel; - - CHECK_PARAM(IS_GLB_MCU_SYS_CLK_TYPE(clkFreq)); - - /* get xclk&&rootclk clock */ - mcuXclkSel = HBN_Get_MCU_XCLK_Sel(); - - /* change root clock to rc32m */ - HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M); - HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK); - GLB_Set_MCU_System_CLK_Div(0, 0, 0); - - /* select pll output clock before select root clock */ - tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG1); - switch (clkFreq) { - case GLB_MCU_SYS_CLK_CPUPLL_400M: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_REG_PLL_SEL, 0); - break; - case GLB_MCU_SYS_CLK_WIFIPLL_240M: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_REG_PLL_SEL, 2); - break; - case GLB_MCU_SYS_CLK_WIFIPLL_320M: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_REG_PLL_SEL, 3); - break; - default: - break; - } - BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG1, tmpVal); - - /* select root clock */ - switch (clkFreq) { - case GLB_MCU_SYS_CLK_RC32M: - GLB_Set_MCU_System_CLK_Div(0, 0, 0); - HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M); - HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK); - break; - case GLB_MCU_SYS_CLK_XTAL: - GLB_Set_MCU_System_CLK_Div(0, 0, 0); - HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_XTAL); - HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK); - break; - case GLB_MCU_SYS_CLK_CPUPLL_400M: - /* For high speed, set DIV first */ - GLB_Set_MCU_System_CLK_Div(1, 2, 1); - /* Set IROM 2T Access 0 since we use RC32M, unuseful now */ - /* MCU_MISC_IROM_2T_Access_Set(0); */ - /* unuseful for mcu, useful for dsp, just for safe */ - HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_PLL); - /* recover xclk */ - HBN_Set_MCU_XCLK_Sel(mcuXclkSel); - break; - case GLB_MCU_SYS_CLK_WIFIPLL_240M: - /* For high speed, set DIV first */ - GLB_Set_MCU_System_CLK_Div(0, 2, 1); - /* Set IROM 2T Access 0 since we use RC32M, unuseful now */ - /* MCU_MISC_IROM_2T_Access_Set(0); */ - /* unuseful for mcu, useful for dsp, just for safe */ - HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_PLL); - /* recover xclk */ - HBN_Set_MCU_XCLK_Sel(mcuXclkSel); - break; - case GLB_MCU_SYS_CLK_WIFIPLL_320M: - /* overclock, not recommended */ - /* For high speed, set DIV first */ - GLB_Set_MCU_System_CLK_Div(0, 3, 1); - /* Set IROM 2T Access 0 since we use RC32M, unuseful now */ - /* MCU_MISC_IROM_2T_Access_Set(0); */ - HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_PLL); - /* recover xclk */ - HBN_Set_MCU_XCLK_Sel(mcuXclkSel); - break; - default: - break; - } - - GLB_CLK_SET_DUMMY_WAIT; - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief select DSP0 DSP1 clock div - * - * @param dspClkDiv: mm glb cpu div - * @param dspBclkDiv: mm glb bclk2x div - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_System_CLK_Div(uint8_t dspClkDiv, uint8_t dspBclkDiv) -{ - uint32_t tmpVal = 0; - uint32_t timeout = 1024; - GLB_DSP_XCLK_Type dspXclkSel; - GLB_DSP_ROOT_CLK_Type dspRootClkSel; - - /* get root clock */ - dspXclkSel = GLB_Get_DSP_XCLK_Sel(); - dspRootClkSel = GLB_Get_DSP_ROOT_CLK_Sel(); - - /* change root clock to rc32m */ - if ((dspXclkSel != GLB_DSP_XCLK_RC32M) || (dspRootClkSel != GLB_DSP_ROOT_CLK_XCLK)) { - GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_RC32M); - GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_XCLK); - } - - /* set div */ - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK2X_DIV, dspBclkDiv); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_CLK_DIV, dspClkDiv); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU, tmpVal); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK2X_DIV_ACT_PULSE, 1); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal); - - do { - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_STS_BCLK2X_PROT_DONE); - } while ((--timeout) && (!tmpVal)); - if (!timeout) { - return ERROR; - } - - /* recover root clock */ - GLB_Set_DSP_XCLK_Sel(dspXclkSel); - GLB_Set_DSP_ROOT_CLK_Sel(dspRootClkSel); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get DSP0 DSP1 clock div - * - * @param dspClkDiv: mm glb cpu div - * @param dspBclkDiv: mm glb bclk2x div - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Get_DSP_System_CLK_Div(uint8_t *dspClkDiv, uint8_t *dspBclkDiv) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU); - *dspBclkDiv = BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK2X_DIV); - *dspClkDiv = BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_CLK_DIV); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Set dsp System clock - * - * @param clkFreq: dsp system clock type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_System_CLK(GLB_DSP_SYS_CLK_Type clkFreq) -{ - GLB_DSP_XCLK_Type dspXclkSel; - - CHECK_PARAM(IS_GLB_DSP_SYS_CLK_TYPE(clkFreq)); - - /* get root clock */ - dspXclkSel = GLB_Get_DSP_XCLK_Sel(); - - /* Before config XTAL and PLL ,make sure root clk is from RC32M */ - GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_RC32M); - GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_XCLK); - GLB_Set_DSP_System_CLK_Div(0, 0); - - /* select pll output clock before select root clock */ - if (GLB_DSP_SYS_CLK_MM_WIFIPLL_240M == clkFreq) { - GLB_Set_DSP_MUXPLL_CLK_Sel(GLB_DSP_PLL_CLK_MUXPLL_240M); - } else if (GLB_DSP_SYS_CLK_MM_WIFIPLL_320M == clkFreq) { - GLB_Set_DSP_MUXPLL_CLK_Sel(GLB_DSP_PLL_CLK_MUXPLL_320M); - } else if (GLB_DSP_SYS_CLK_CPUPLL_400M == clkFreq) { - GLB_Set_DSP_MUXPLL_CLK_Sel(GLB_DSP_PLL_CLK_CPUPLL_400M); - } - - /* select root clock */ - switch (clkFreq) { - case GLB_DSP_SYS_CLK_RC32M: - GLB_Set_DSP_System_CLK_Div(0, 0); - GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_RC32M); - GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_XCLK); - break; - case GLB_DSP_SYS_CLK_XTAL: - GLB_Set_DSP_System_CLK_Div(0, 0); - GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_XTAL); - GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_XCLK); - break; - case GLB_DSP_SYS_CLK_MM_WIFIPLL_240M: - GLB_Set_DSP_System_CLK_Div(0, 1); - GLB_Set_DSP_Muxpll_240M_Sel(GLB_DSP_MUXPLL_SEL_WIFIPLL_240M); - GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_PLL); - /* recover xclk */ - GLB_Set_DSP_XCLK_Sel(dspXclkSel); - break; - case GLB_DSP_SYS_CLK_MM_WIFIPLL_320M: - GLB_Set_DSP_System_CLK_Div(0, 1); - GLB_Set_DSP_Muxpll_320M_Sel(GLB_DSP_MUXPLL_SEL_WIFIPLL_320M); - GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_PLL); - /* recover xclk */ - GLB_Set_DSP_XCLK_Sel(dspXclkSel); - break; - case GLB_DSP_SYS_CLK_CPUPLL_400M: - GLB_Set_DSP_System_CLK_Div(0, 1); - GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_PLL); - /* recover xclk */ - GLB_Set_DSP_XCLK_Sel(dspXclkSel); - break; - default: - break; - } - GLB_CLK_SET_DUMMY_WAIT; - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief select DSP0 pbus clock div - * - * @param dspBclkDiv: mm glb bclk2x div - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_PBCLK_Div(uint8_t dspPBclkDiv) -{ - uint32_t tmpVal = 0; - - /* set div */ - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK1X_DIV, dspPBclkDiv); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get DSP0 pbus clock div - * - * @param dspBclkDiv: mm glb bclk2x div - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Get_DSP_PBCLK_Div(uint8_t *dspPBclkDiv) -{ - *dspPBclkDiv = BL_GET_REG_BITS_VAL(BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU), MM_GLB_REG_BCLK1X_DIV); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Set dsp pbus clock - * - * @param pbClkSel: dsp pbus clock type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_PBCLK(GLB_DSP_SYS_PBCLK_Type pbClkSel) -{ - CHECK_PARAM(IS_GLB_DSP_SYS_PBCLK_TYPE(pbClkSel)); - - GLB_Set_DSP_PBCLK_Div(0); - - /* select pbroot clock */ - switch (pbClkSel) { - case GLB_DSP_SYS_PBCLK_RC32M: - GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_RC32M); - GLB_Set_DSP_PBCLK_Div(0); - GLB_Set_DSP_PBROOT_CLK_Sel(GLB_DSP_PBROOT_CLK_MM_XCLK); - break; - case GLB_DSP_SYS_PBCLK_XTAL: - GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_XTAL); - GLB_Set_DSP_PBCLK_Div(0); - GLB_Set_DSP_PBROOT_CLK_Sel(GLB_DSP_PBROOT_CLK_MM_XCLK); - break; - case GLB_DSP_SYS_PBCLK_MM_WIFIPLL_160M: - GLB_Set_DSP_Muxpll_160M_Sel(GLB_DSP_MUXPLL_SEL_WIFIPLL_160M); - GLB_Set_DSP_PBCLK_Div(0); - GLB_Set_DSP_PBROOT_CLK_Sel(GLB_DSP_PBROOT_CLK_MM_MUXPLL_160M); - break; - case GLB_DSP_SYS_PBCLK_CPUPLL_160M: - GLB_Set_DSP_Muxpll_160M_Sel(GLB_DSP_MUXPLL_SEL_CPUPLL_160M); - GLB_Set_DSP_PBCLK_Div(0); - GLB_Set_DSP_PBROOT_CLK_Sel(GLB_DSP_PBROOT_CLK_MM_MUXPLL_160M); - break; - case GLB_DSP_SYS_PBCLK_MM_WIFIPLL_240M: - GLB_Set_DSP_Muxpll_240M_Sel(GLB_DSP_MUXPLL_SEL_WIFIPLL_240M); - GLB_Set_DSP_PBCLK_Div(1); - GLB_Set_DSP_PBROOT_CLK_Sel(GLB_DSP_PBROOT_CLK_MM_MUXPLL_240M); - break; - default: - break; - } - GLB_CLK_SET_DUMMY_WAIT; - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief DSP0 clock enable - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_DSP0_Clock_Enable(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU); - tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_MMCPU0_CLK_EN); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief DSP0 clock disable - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_DSP0_Clock_Disable(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU); - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_MMCPU0_CLK_EN); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get xclk clock source Select - * - * @param None - * - * @return xclk clock type selection - * -*******************************************************************************/ -GLB_DSP_XCLK_Type ATTR_CLOCK_SECTION GLB_Get_DSP_XCLK_Sel(void) -{ - return (GLB_DSP_XCLK_Type)(BL_GET_REG_BITS_VAL(BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU), MM_GLB_REG_XCLK_CLK_SEL)); -} - -/****************************************************************************/ /** - * @brief Select xclk clock source - * - * @param xclk: xclk clock type selection - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_Type xclk) -{ - uint32_t tmpVal; - - CHECK_PARAM(IS_GLB_DSP_XCLK_TYPE(xclk)); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_XCLK_CLK_SEL, xclk); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal); - GLB_CLK_SET_DUMMY_WAIT; - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get DSP root clock - * - * @param None - * - * @return mm glb root clock type - * -*******************************************************************************/ -GLB_DSP_ROOT_CLK_Type ATTR_CLOCK_SECTION GLB_Get_DSP_ROOT_CLK_Sel(void) -{ - uint32_t tmpVal = 0; - uint32_t rootclk = 0; - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU); - rootclk = BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_ROOT_CLK_SEL); - if (0 == rootclk) { - /* xclk */ - return GLB_DSP_ROOT_CLK_XCLK; - } else { - /* pll */ - return GLB_DSP_ROOT_CLK_PLL; - } -} - -/****************************************************************************/ /** - * @brief select DSP root clock - * - * @param rootClk: mm glb root clock type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_Type rootClk) -{ - uint32_t tmpVal; - - CHECK_PARAM(IS_GLB_DSP_ROOT_CLK_TYPE(rootClk)); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU); - switch (rootClk) { - case GLB_DSP_ROOT_CLK_XCLK: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_ROOT_CLK_SEL, 0); - break; - case GLB_DSP_ROOT_CLK_PLL: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_ROOT_CLK_SEL, 1); - break; - default: - break; - } - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal); - GLB_CLK_SET_DUMMY_WAIT; - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief select DSP muxpll clock - * - * @param pllClk: mm glb pll clock type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_MUXPLL_CLK_Sel(GLB_DSP_PLL_CLK_Type pllClk) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_DSP_PLL_CLK_TYPE(pllClk)); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU); - switch (pllClk) { - case GLB_DSP_PLL_CLK_MUXPLL_240M: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_CLK_SEL, 0); - break; - case GLB_DSP_PLL_CLK_MUXPLL_320M: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_CLK_SEL, 1); - break; - case GLB_DSP_PLL_CLK_CPUPLL_400M: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_CLK_SEL, 2); - break; - default: - break; - } - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get DSP pbroot clock - * - * @param None - * - * @return mm DSP pbroot clock type - * -*******************************************************************************/ -GLB_DSP_PBROOT_CLK_Type ATTR_CLOCK_SECTION GLB_Get_DSP_PBROOT_CLK_Sel(void) -{ - uint32_t tmpVal = 0; - uint32_t pbrootclk = 0; - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU); - pbrootclk = BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK1X_SEL); - switch (pbrootclk) { - case 0: - return GLB_DSP_PBROOT_CLK_MM_XCLK; - case 1: - return GLB_DSP_PBROOT_CLK_MM_XCLK; - case 2: - return GLB_DSP_PBROOT_CLK_MM_MUXPLL_160M; - case 3: - return GLB_DSP_PBROOT_CLK_MM_MUXPLL_240M; - default: - return GLB_DSP_PBROOT_CLK_MM_XCLK; - } -} - -/****************************************************************************/ /** - * @brief select DSP pbroot clock - * - * @param pbrootClk: mm DSP pbroot clock type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_PBROOT_CLK_Sel(GLB_DSP_PBROOT_CLK_Type pbrootClk) -{ - uint32_t tmpVal; - - CHECK_PARAM(IS_GLB_DSP_PBROOT_CLK_TYPE(pbrootClk)); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU); - switch (pbrootClk) { - case GLB_DSP_PBROOT_CLK_MM_XCLK: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK1X_SEL, 0); - break; - case GLB_DSP_PBROOT_CLK_MM_MUXPLL_160M: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK1X_SEL, 2); - break; - case GLB_DSP_PBROOT_CLK_MM_MUXPLL_240M: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK1X_SEL, 3); - break; - default: - break; - } - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal); - GLB_CLK_SET_DUMMY_WAIT; - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set CPU reset address - * - * @param coreID: core type - * @param addr: reset address - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_CPU_Reset_Address(GLB_CORE_ID_Type coreID, uint32_t addr) -{ - CHECK_PARAM(IS_GLB_CORE_ID_TYPE(coreID)); - - switch (coreID) { - case GLB_CORE_ID_M0: - BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG14, addr); - break; - case GLB_CORE_ID_D0: - BL_WR_REG(MM_MISC_BASE, MM_MISC_CPU0_BOOT, addr); - break; - case GLB_CORE_ID_LP: - BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG13, addr); - break; - default: - return ERROR; - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief hold cpu - * - * @param coreID: core type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Halt_CPU(GLB_CORE_ID_Type coreID) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_CORE_ID_TYPE(coreID)); - - switch (coreID) { - case GLB_CORE_ID_M0: - PDS_Set_MCU0_Clock_Disable(); - arch_delay_us(1); - tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET); - BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); - break; - case GLB_CORE_ID_D0: - GLB_DSP0_Clock_Disable(); - arch_delay_us(1); - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET); - tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_CTRL_MMCPU0_RESET); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET, tmpVal); - break; - case GLB_CORE_ID_LP: - PDS_Set_LP_Clock_Disable(); - arch_delay_us(1); - tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_PICO_RESET); - BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); - break; - default: - return ERROR; - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief release cpu - * - * @param coreID: core type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Release_CPU(GLB_CORE_ID_Type coreID) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_CORE_ID_TYPE(coreID)); - - switch (coreID) { - case GLB_CORE_ID_M0: - PDS_Set_MCU0_Clock_Enable(); - arch_delay_us(1); - tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET); - BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); - break; - case GLB_CORE_ID_D0: - GLB_DSP0_Clock_Enable(); - arch_delay_us(1); - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET); - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_CTRL_MMCPU0_RESET); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET, tmpVal); - break; - case GLB_CORE_ID_LP: - PDS_Set_LP_Clock_Enable(); - arch_delay_us(1); - tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PICO_RESET); - BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); - break; - default: - return ERROR; - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set MTimer clock - * - * @param enable: enable or disable - * @param clkSel: clock selection - * @param div: divider - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_EMI_CLK(uint8_t enable, GLB_EMI_CLK_Type clkSel, uint32_t div) -{ - uint32_t tmpVal; - - CHECK_PARAM(IS_GLB_EMI_CLK_TYPE(clkSel)); - CHECK_PARAM((div <= 0x3)); - - /* disable EMI clock first */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_EMI_CFG0); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_EMI_CLK_EN); - BL_WR_REG(GLB_BASE, GLB_EMI_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_EMI_CFG0); - switch (clkSel) { - case GLB_EMI_CLK_MCU_PBCLK: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_EMI_CLK_SEL, 0); - break; - case GLB_EMI_CLK_CPUPLL_200M_CLK: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_EMI_CLK_SEL, 4); - break; - case GLB_EMI_CLK_WIFIPLL_320M_CLK: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_EMI_CLK_SEL, 2); - break; - case GLB_EMI_CLK_CPUPLL_400M_CLK: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_EMI_CLK_SEL, 3); - break; - default: - break; - } - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_EMI_CLK_DIV, div); - BL_WR_REG(GLB_BASE, GLB_EMI_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_EMI_CFG0); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_EMI_CLK_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_EMI_CLK_EN); - } - BL_WR_REG(GLB_BASE, GLB_EMI_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Clr_EMI_Reset_Gate(void) -{ - uint32_t tmpVal; - - /* clear EMI swrst bit */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG0); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SWRST_S1_EXT_EMI_MISC); - BL_WR_REG(GLB_BASE, GLB_SWRST_CFG0, tmpVal); - - /* set EMI cgen bit */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG2); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CGEN_S1_EXT_EMI_MISC); - BL_WR_REG(GLB_BASE, GLB_CGEN_CFG2, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief reconfigure WIFIPLL clock - * - * @param xtalType: XTAL frequency type - * @param pllCfg: PLL configuration - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_WIFI_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type * pllCfgList) -{ - GLB_PLL_REF_CLK_Type refClk; - - if (xtalType == GLB_XTAL_RC32M) { - refClk = GLB_PLL_REFCLK_RC32M; - } else { - refClk = GLB_PLL_REFCLK_XTAL; - } - - GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_WIFIPLL); - GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_WIFIPLL, refClk); - GLB_Power_On_WAC_PLL(GLB_WAC_PLL_WIFIPLL, &(pllCfgList[xtalType]), 0); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief reconfigure AUPLL clock - * - * @param xtalType: XTAL frequency type - * @param pllCfg: PLL configuration - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_AUDIO_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type * pllCfgList) -{ - GLB_PLL_REF_CLK_Type refClk; - - if (xtalType == GLB_XTAL_RC32M) { - refClk = GLB_PLL_REFCLK_RC32M; - } else { - refClk = GLB_PLL_REFCLK_XTAL; - } - - GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_AUPLL); - GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_AUPLL, refClk); - GLB_Power_On_WAC_PLL(GLB_WAC_PLL_AUPLL, &(pllCfgList[xtalType]), 0); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief reconfigure CPUPLL clock - * - * @param xtalType: XTAL frequency type - * @param pllCfg: PLL configuration - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_CPU_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type * pllCfgList) -{ - GLB_PLL_REF_CLK_Type refClk; - - if (xtalType == GLB_XTAL_RC32M) { - refClk = GLB_PLL_REFCLK_RC32M; - } else { - refClk = GLB_PLL_REFCLK_XTAL; - } - - GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_CPUPLL); - GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_CPUPLL, refClk); - GLB_Power_On_WAC_PLL(GLB_WAC_PLL_CPUPLL, &(pllCfgList[xtalType]), 0); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief reconfigure MIPIPLL clock - * - * @param xtalType: XTAL frequency type - * @param pllCfg: PLL configuration - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_MIPI_PLL(GLB_XTAL_Type xtalType, const GLB_MU_PLL_Cfg_Type * pllCfgList) -{ - GLB_PLL_REF_CLK_Type refClk; - - if (xtalType == GLB_XTAL_RC32M) { - refClk = GLB_PLL_REFCLK_RC32M; - } else { - refClk = GLB_PLL_REFCLK_XTAL; - } - - GLB_Power_Off_MU_PLL(GLB_MU_PLL_MIPIPLL); - GLB_MU_PLL_Ref_Clk_Sel(GLB_MU_PLL_MIPIPLL, refClk); - GLB_Power_On_MU_PLL(GLB_MU_PLL_MIPIPLL, &(pllCfgList[xtalType]), 0); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief reconfigure MIPIPLL clock div - * - * @param divEn: div enable - * @param divRatio: div ratio - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_MIPI_PLL_Div(uint8_t divEn, uint8_t divRatio) -{ - uint32_t REG_PLL_BASE_ADDRESS = 0; - uint32_t tmpVal = 0; - - REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET; - - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_MIPIPLL_EVEN_DIV_EN, divEn); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_MIPIPLL_EVEN_DIV_RATIO, divRatio); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief reconfigure UHSPLL clock - * - * @param xtalType: XTAL frequency type - * @param pllCfg: PLL configuration - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_UHS_PLL(GLB_XTAL_Type xtalType, const GLB_MU_PLL_Cfg_Type * pllCfgList) -{ - GLB_PLL_REF_CLK_Type refClk; - - if (xtalType == GLB_XTAL_RC32M) { - refClk = GLB_PLL_REFCLK_RC32M; - } else { - refClk = GLB_PLL_REFCLK_XTAL; - } - - GLB_Power_Off_MU_PLL(GLB_MU_PLL_UHSPLL); - GLB_MU_PLL_Ref_Clk_Sel(GLB_MU_PLL_UHSPLL, refClk); - GLB_Power_On_MU_PLL(GLB_MU_PLL_UHSPLL, &(pllCfgList[xtalType]), 0); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get core type - * - * @param None - * - * @return core type - * -*******************************************************************************/ -GLB_CORE_ID_Type ATTR_CLOCK_SECTION GLB_Get_Core_Type(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_WORD(CORE_ID_ADDRESS); - - switch (tmpVal) { - case CORE_ID_M0: - return GLB_CORE_ID_M0; - case CORE_ID_D0: - return GLB_CORE_ID_D0; - case CORE_ID_LP: - return GLB_CORE_ID_LP; - default: - return GLB_CORE_ID_INVALID; - } - - return GLB_CORE_ID_INVALID; -} - -/****************************************************************************/ /** - * @brief get first 1 from u64, then clear it - * - * @param val: target value - * @param bit: first 1 in bit - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -static BL_Err_Type GLB_Get_And_Clr_First_Set_From_U64(uint64_t *val, uint32_t *bit) -{ - if (!*val) { - return ERROR; - } - - for (uint8_t i = 0; i < 64; i++) { - if ((*val) & ((uint64_t)1 << i)) { - *bit = i; - (*val) &= ~((uint64_t)1 << i); - break; - } - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief hold IPs clock - * - * @param ips: GLB_AHB_CLOCK_IP_xxx | GLB_AHB_CLOCK_IP_xxx | ...... - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_PER_Clock_Gate(uint64_t ips) -{ - /* api request from cjy */ - - uint32_t tmpValCfg0 = 0; - uint32_t tmpValCfg1 = 0; - uint32_t tmpValCfg2 = 0; - uint32_t bitfield = 0; - - tmpValCfg0 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0); - tmpValCfg1 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1); - tmpValCfg2 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG2); - while (ips) { - if (SUCCESS == GLB_Get_And_Clr_First_Set_From_U64(&ips, &bitfield)) { - switch (bitfield) { - case GLB_AHB_CLOCK_IP_CPU: - tmpValCfg0 &= ~(1 << 0); - break; - case GLB_AHB_CLOCK_IP_SDU: - tmpValCfg0 &= ~(1 << 1); - break; - case GLB_AHB_CLOCK_IP_SEC: - tmpValCfg0 &= ~(1 << 2); - tmpValCfg1 &= ~(1 << 3); - tmpValCfg1 &= ~(1 << 4); - break; - case GLB_AHB_CLOCK_IP_DMA_0: - tmpValCfg0 &= ~(1 << 3); - tmpValCfg1 &= ~(1 << 12); - break; - case GLB_AHB_CLOCK_IP_DMA_1: - tmpValCfg0 &= ~(1 << 3); - break; - case GLB_AHB_CLOCK_IP_DMA_2: - tmpValCfg0 &= ~(1 << 3); - tmpValCfg2 &= ~(1 << 24); - break; - case GLB_AHB_CLOCK_IP_CCI: - tmpValCfg0 &= ~(1 << 4); - break; - case GLB_AHB_CLOCK_IP_RF_TOP: - tmpValCfg1 &= ~(1 << 1); - break; - case GLB_AHB_CLOCK_IP_GPIP: - tmpValCfg1 &= ~(1 << 2); - break; - case GLB_AHB_CLOCK_IP_TZC: - tmpValCfg1 &= ~(1 << 5); - break; - case GLB_AHB_CLOCK_IP_EF_CTRL: - tmpValCfg1 &= ~(1 << 7); - break; - case GLB_AHB_CLOCK_IP_SF_CTRL: - tmpValCfg1 &= ~(1 << 11); - break; - case GLB_AHB_CLOCK_IP_EMAC: - tmpValCfg2 &= ~(1 << 19); - tmpValCfg2 &= ~(1 << 23); - break; - case GLB_AHB_CLOCK_IP_UART0: - tmpValCfg1 &= ~(1 << 16); - break; - case GLB_AHB_CLOCK_IP_UART1: - tmpValCfg1 &= ~(1 << 17); - break; - case GLB_AHB_CLOCK_IP_UART2: - tmpValCfg1 &= ~(1 << 26); - break; - case GLB_AHB_CLOCK_IP_UART3: - break; - case GLB_AHB_CLOCK_IP_UART4: - break; - case GLB_AHB_CLOCK_IP_SPI: - tmpValCfg1 &= ~(1 << 18); - break; - case GLB_AHB_CLOCK_IP_I2C: - tmpValCfg1 &= ~(1 << 19); - break; - case GLB_AHB_CLOCK_IP_PWM: - tmpValCfg1 &= ~(1 << 20); - break; - case GLB_AHB_CLOCK_IP_TIMER: - tmpValCfg1 &= ~(1 << 21); - break; - case GLB_AHB_CLOCK_IP_IR: - tmpValCfg1 &= ~(1 << 22); - break; - case GLB_AHB_CLOCK_IP_CHECKSUM: - tmpValCfg1 &= ~(1 << 23); - break; - case GLB_AHB_CLOCK_IP_QDEC: - break; - case GLB_AHB_CLOCK_IP_KYS: - break; - case GLB_AHB_CLOCK_IP_I2S: - tmpValCfg1 &= ~(1 << 27); - break; - case GLB_AHB_CLOCK_IP_USB11: - break; - case GLB_AHB_CLOCK_IP_CAM: - break; - case GLB_AHB_CLOCK_IP_MJPEG: - break; - case GLB_AHB_CLOCK_IP_BT_BLE_NORMAL: - tmpValCfg2 &= ~(1 << 8); - break; - case GLB_AHB_CLOCK_IP_BT_BLE_LP: - break; - case GLB_AHB_CLOCK_IP_ZB_NORMAL: - tmpValCfg2 &= ~(1 << 9); - break; - case GLB_AHB_CLOCK_IP_ZB_LP: - break; - case GLB_AHB_CLOCK_IP_WIFI_NORMAL: - tmpValCfg2 &= ~(1 << 4); - break; - case GLB_AHB_CLOCK_IP_WIFI_LP: - break; - case GLB_AHB_CLOCK_IP_BT_BLE_2_NORMAL: - tmpValCfg2 &= ~(1 << 10); - break; - case GLB_AHB_CLOCK_IP_BT_BLE_2_LP: - break; - case GLB_AHB_CLOCK_IP_EMI_MISC: - tmpValCfg2 &= ~(1 << 16); - break; - case GLB_AHB_CLOCK_IP_PSRAM0_CTRL: - tmpValCfg2 &= ~(1 << 17); - break; - case GLB_AHB_CLOCK_IP_PSRAM1_CTRL: - tmpValCfg2 &= ~(1 << 18); - break; - case GLB_AHB_CLOCK_IP_USB20: - tmpValCfg1 &= ~(1 << 13); - break; - case GLB_AHB_CLOCK_IP_MIX2: - tmpValCfg2 &= ~(1 << 20); - break; - case GLB_AHB_CLOCK_IP_AUDIO: - tmpValCfg2 &= ~(1 << 21); - break; - case GLB_AHB_CLOCK_IP_SDH: - tmpValCfg2 &= ~(1 << 22); - break; - case GLB_AHB_CLOCK_IP_ZB2_NORMAL: - tmpValCfg2 &= ~(1 << 11); - break; - case GLB_AHB_CLOCK_IP_ZB2_LP: - break; - case GLB_AHB_CLOCK_IP_I2C1: - tmpValCfg1 &= ~(1 << 25); - break; - case GLB_AHB_CLOCK_IP_WIFI_PHY: - tmpValCfg0 &= ~(1 << 7); - break; - case GLB_AHB_CLOCK_IP_WIFI_MAC_PHY: - tmpValCfg0 &= ~(1 << 6); - break; - case GLB_AHB_CLOCK_IP_WIFI_PLATFORM: - tmpValCfg0 &= ~(1 << 5); - break; - case GLB_AHB_CLOCK_IP_LZ4: - tmpValCfg1 &= ~(1 << 29); - break; - case GLB_AHB_CLOCK_IP_AUPDM: - tmpValCfg1 &= ~(1 << 28); - break; - case GLB_AHB_CLOCK_IP_GAUGE: - tmpValCfg1 &= ~(1 << 0); - break; - default: - break; - } - } - } - BL_WR_REG(GLB_BASE, GLB_CGEN_CFG0, tmpValCfg0); - BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpValCfg1); - BL_WR_REG(GLB_BASE, GLB_CGEN_CFG2, tmpValCfg2); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief release IPs clock - * - * @param ips: GLB_AHB_CLOCK_xxx | GLB_AHB_CLOCK_xxx | ...... (not GLB_AHB_CLOCK_IP_xxx) - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_PER_Clock_UnGate(uint64_t ips) -{ - /* api request from cjy */ - - uint32_t tmpValCfg0 = 0; - uint32_t tmpValCfg1 = 0; - uint32_t tmpValCfg2 = 0; - uint32_t bitfield = 0; - - tmpValCfg0 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0); - tmpValCfg1 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1); - tmpValCfg2 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG2); - while (ips) { - if (SUCCESS == GLB_Get_And_Clr_First_Set_From_U64(&ips, &bitfield)) { - switch (bitfield) { - case GLB_AHB_CLOCK_IP_CPU: - tmpValCfg0 |= (1 << 0); - break; - case GLB_AHB_CLOCK_IP_SDU: - tmpValCfg0 |= (1 << 1); - break; - case GLB_AHB_CLOCK_IP_SEC: - tmpValCfg0 |= (1 << 2); - tmpValCfg1 |= (1 << 3); - tmpValCfg1 |= (1 << 4); - break; - case GLB_AHB_CLOCK_IP_DMA_0: - tmpValCfg0 |= (1 << 3); - tmpValCfg1 |= (1 << 12); - break; - case GLB_AHB_CLOCK_IP_DMA_1: - tmpValCfg0 |= (1 << 3); - break; - case GLB_AHB_CLOCK_IP_DMA_2: - tmpValCfg0 |= (1 << 3); - tmpValCfg2 |= (1 << 24); - break; - case GLB_AHB_CLOCK_IP_CCI: - tmpValCfg0 |= (1 << 4); - break; - case GLB_AHB_CLOCK_IP_RF_TOP: - tmpValCfg1 |= (1 << 1); - break; - case GLB_AHB_CLOCK_IP_GPIP: - tmpValCfg1 |= (1 << 2); - break; - case GLB_AHB_CLOCK_IP_TZC: - tmpValCfg1 |= (1 << 5); - break; - case GLB_AHB_CLOCK_IP_EF_CTRL: - tmpValCfg1 |= (1 << 7); - break; - case GLB_AHB_CLOCK_IP_SF_CTRL: - tmpValCfg1 |= (1 << 11); - break; - case GLB_AHB_CLOCK_IP_EMAC: - tmpValCfg2 |= (1 << 19); - tmpValCfg2 |= (1 << 23); - break; - case GLB_AHB_CLOCK_IP_UART0: - tmpValCfg1 |= (1 << 16); - break; - case GLB_AHB_CLOCK_IP_UART1: - tmpValCfg1 |= (1 << 17); - break; - case GLB_AHB_CLOCK_IP_UART2: - tmpValCfg1 |= (1 << 26); - break; - case GLB_AHB_CLOCK_IP_UART3: - break; - case GLB_AHB_CLOCK_IP_UART4: - break; - case GLB_AHB_CLOCK_IP_SPI: - tmpValCfg1 |= (1 << 18); - break; - case GLB_AHB_CLOCK_IP_I2C: - tmpValCfg1 |= (1 << 19); - break; - case GLB_AHB_CLOCK_IP_PWM: - tmpValCfg1 |= (1 << 20); - break; - case GLB_AHB_CLOCK_IP_TIMER: - tmpValCfg1 |= (1 << 21); - break; - case GLB_AHB_CLOCK_IP_IR: - tmpValCfg1 |= (1 << 22); - break; - case GLB_AHB_CLOCK_IP_CHECKSUM: - tmpValCfg1 |= (1 << 23); - break; - case GLB_AHB_CLOCK_IP_QDEC: - break; - case GLB_AHB_CLOCK_IP_KYS: - break; - case GLB_AHB_CLOCK_IP_I2S: - tmpValCfg1 |= (1 << 23); - break; - case GLB_AHB_CLOCK_IP_USB11: - break; - case GLB_AHB_CLOCK_IP_CAM: - break; - case GLB_AHB_CLOCK_IP_MJPEG: - break; - case GLB_AHB_CLOCK_IP_BT_BLE_NORMAL: - tmpValCfg2 |= (1 << 8); - break; - case GLB_AHB_CLOCK_IP_BT_BLE_LP: - break; - case GLB_AHB_CLOCK_IP_ZB_NORMAL: - tmpValCfg2 |= (1 << 9); - break; - case GLB_AHB_CLOCK_IP_ZB_LP: - break; - case GLB_AHB_CLOCK_IP_WIFI_NORMAL: - tmpValCfg2 |= (1 << 4); - break; - case GLB_AHB_CLOCK_IP_WIFI_LP: - break; - case GLB_AHB_CLOCK_IP_BT_BLE_2_NORMAL: - tmpValCfg2 |= (1 << 10); - break; - case GLB_AHB_CLOCK_IP_BT_BLE_2_LP: - break; - case GLB_AHB_CLOCK_IP_EMI_MISC: - tmpValCfg2 |= (1 << 16); - break; - case GLB_AHB_CLOCK_IP_PSRAM0_CTRL: - tmpValCfg2 |= (1 << 17); - break; - case GLB_AHB_CLOCK_IP_PSRAM1_CTRL: - tmpValCfg2 |= (1 << 18); - break; - case GLB_AHB_CLOCK_IP_USB20: - tmpValCfg1 |= (1 << 13); - break; - case GLB_AHB_CLOCK_IP_MIX2: - tmpValCfg2 |= (1 << 20); - break; - case GLB_AHB_CLOCK_IP_AUDIO: - tmpValCfg2 |= (1 << 21); - break; - case GLB_AHB_CLOCK_IP_SDH: - tmpValCfg2 |= (1 << 22); - break; - case GLB_AHB_CLOCK_IP_ZB2_NORMAL: - tmpValCfg2 |= (1 << 11); - break; - case GLB_AHB_CLOCK_IP_ZB2_LP: - break; - case GLB_AHB_CLOCK_IP_I2C1: - tmpValCfg1 |= (1 << 25); - break; - case GLB_AHB_CLOCK_IP_WIFI_PHY: - tmpValCfg0 |= (1 << 7); - break; - case GLB_AHB_CLOCK_IP_WIFI_MAC_PHY: - tmpValCfg0 |= (1 << 6); - break; - case GLB_AHB_CLOCK_IP_WIFI_PLATFORM: - tmpValCfg0 |= (1 << 5); - break; - case GLB_AHB_CLOCK_IP_LZ4: - tmpValCfg1 |= (1 << 29); - break; - case GLB_AHB_CLOCK_IP_AUPDM: - tmpValCfg1 |= (1 << 28); - break; - case GLB_AHB_CLOCK_IP_GAUGE: - tmpValCfg1 |= (1 << 0); - break; - default: - break; - } - } - } - BL_WR_REG(GLB_BASE, GLB_CGEN_CFG0, tmpValCfg0); - BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpValCfg1); - BL_WR_REG(GLB_BASE, GLB_CGEN_CFG2, tmpValCfg2); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief software reset - * - * @param swrst: reset num - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_Type swrst) -{ - uint32_t tmpVal = 0; - uint32_t bit = 0; - uint32_t regAddr = 0; - - CHECK_PARAM(IS_GLB_AHB_MCU_SW_TYPE(swrst)); - - if (swrst < 32) { - bit = swrst; - regAddr = GLB_BASE + GLB_SWRST_CFG0_OFFSET; - } else if (swrst < 64) { - bit = swrst - 32; - regAddr = GLB_BASE + GLB_SWRST_CFG1_OFFSET; - } else if (swrst < 96) { - bit = swrst - 64; - regAddr = GLB_BASE + GLB_SWRST_CFG2_OFFSET; - } - - tmpVal = BL_RD_WORD(regAddr); - tmpVal &= ~(1 << bit); - BL_WR_WORD(regAddr, tmpVal); - BL_DRV_DUMMY; - tmpVal = BL_RD_WORD(regAddr); - tmpVal |= (1 << bit); - BL_WR_WORD(regAddr, tmpVal); - BL_DRV_DUMMY; - tmpVal = BL_RD_WORD(regAddr); - tmpVal &= ~(1 << bit); - BL_WR_WORD(regAddr, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief software reset - * - * @param swrst: reset num - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_Type swrst) -{ - uint32_t tmpVal = 0; - uint32_t bit = 0; - uint32_t regAddr = 0; - - CHECK_PARAM(IS_GLB_AHB_DSP_SW_TYPE(swrst)); - - if (swrst < 32) { - bit = swrst; - regAddr = MM_GLB_BASE + MM_GLB_MM_SW_SYS_RESET_OFFSET; - } else if (swrst < 64) { - bit = swrst - 32; - regAddr = MM_GLB_BASE + MM_GLB_SW_RESET_MM_PERI_OFFSET; - } else if (swrst < 96) { - bit = swrst - 64; - regAddr = MM_GLB_BASE + MM_GLB_SW_RESET_DSP2_SUB_OFFSET; - } else if (swrst < 128) { - bit = swrst - 96; - regAddr = MM_GLB_BASE + MM_GLB_SW_RESET_CODEC_SUB_OFFSET; - } else if (swrst < 160) { - bit = swrst - 128; - regAddr = MM_GLB_BASE + MM_GLB_IMAGE_SENSOR_CTRL_OFFSET; - } - - tmpVal = BL_RD_WORD(regAddr); - tmpVal &= ~(1 << bit); - BL_WR_WORD(regAddr, tmpVal); - BL_DRV_DUMMY; - tmpVal = BL_RD_WORD(regAddr); - tmpVal |= (1 << bit); - BL_WR_WORD(regAddr, tmpVal); - BL_DRV_DUMMY; - tmpVal = BL_RD_WORD(regAddr); - tmpVal &= ~(1 << bit); - BL_WR_WORD(regAddr, tmpVal); - - return SUCCESS; -} - -/*@} end of group GLB_Public_Functions */ - -/*@} end of group GLB */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_i2c.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_i2c.c deleted file mode 100644 index 80319fce62..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_i2c.c +++ /dev/null @@ -1,964 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_i2c.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_i2c.h" -#include "bl808_glb.h" -#include "bl808_clock.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup I2C - * @{ - */ - -/** @defgroup I2C_Private_Macros - * @{ - */ -#define I2C_FIFO_STATUS_TIMEOUT (320 * 1000 * 2) -#define PUT_UINT32_LE(n, b, i) \ - { \ - (b)[(i)] = (uint8_t)((n)); \ - (b)[(i) + 1] = (uint8_t)((n) >> 8); \ - (b)[(i) + 2] = (uint8_t)((n) >> 16); \ - (b)[(i) + 3] = (uint8_t)((n) >> 24); \ - } - -/*@} end of group I2C_Private_Macros */ - -/** @defgroup I2C_Private_Types - * @{ - */ - -/*@} end of group I2C_Private_Types */ - -/** @defgroup I2C_Private_Variables - * @{ - */ -static const uint32_t i2cAddr[4] = { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE }; -#ifndef BFLB_USE_HAL_DRIVER -intCallback_Type *i2cIntCbfArra[I2C_ID_MAX][I2C_INT_ALL] = { { NULL } }; -#endif - -/*@} end of group I2C_Private_Variables */ - -/** @defgroup I2C_Global_Variables - * @{ - */ - -/*@} end of group I2C_Global_Variables */ - -/** @defgroup I2C_Private_Fun_Declaration - * @{ - */ - -/*@} end of group I2C_Private_Fun_Declaration */ - -/** @defgroup I2C_Private_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief I2C interrupt handler - * - * @param i2cNo: I2C ID type - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -static void I2C_IntHandler(I2C_ID_Type i2cNo) -{ - uint32_t tmpVal; - uint32_t I2Cx = i2cAddr[i2cNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); - - tmpVal = BL_RD_REG(I2Cx, I2C_INT_STS); - - if (BL_IS_REG_BIT_SET(tmpVal, I2C_END_INT)) { - if (i2cIntCbfArra[i2cNo][I2C_TRANS_END_INT] != NULL) { - /* Call the callback function */ - i2cIntCbfArra[i2cNo][I2C_TRANS_END_INT](); - } - } - - if (BL_IS_REG_BIT_SET(tmpVal, I2C_TXF_INT)) { - if (i2cIntCbfArra[i2cNo][I2C_TX_FIFO_READY_INT] != NULL) { - /* Call the callback function */ - i2cIntCbfArra[i2cNo][I2C_TX_FIFO_READY_INT](); - } - } - - if (BL_IS_REG_BIT_SET(tmpVal, I2C_RXF_INT)) { - if (i2cIntCbfArra[i2cNo][I2C_RX_FIFO_READY_INT] != NULL) { - /* Call the callback function */ - i2cIntCbfArra[i2cNo][I2C_RX_FIFO_READY_INT](); - } - } - - if (BL_IS_REG_BIT_SET(tmpVal, I2C_NAK_INT)) { - if (i2cIntCbfArra[i2cNo][I2C_NACK_RECV_INT] != NULL) { - /* Call the callback function */ - i2cIntCbfArra[i2cNo][I2C_NACK_RECV_INT](); - } - } - - if (BL_IS_REG_BIT_SET(tmpVal, I2C_ARB_INT)) { - if (i2cIntCbfArra[i2cNo][I2C_ARB_LOST_INT] != NULL) { - /* Call the callback function */ - i2cIntCbfArra[i2cNo][I2C_ARB_LOST_INT](); - } - } - - if (BL_IS_REG_BIT_SET(tmpVal, I2C_FER_INT)) { - if (i2cIntCbfArra[i2cNo][I2C_FIFO_ERR_INT] != NULL) { - /* Call the callback function */ - i2cIntCbfArra[i2cNo][I2C_FIFO_ERR_INT](); - } - } -} -#endif - -/*@} end of group I2C_Private_Functions */ - -/** @defgroup I2C_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief I2C write word data - * - * @param i2cNo: I2C ID type - * @param data: Data word - * - * @return None - * -*******************************************************************************/ -BL_Err_Type I2C_SendWord(I2C_ID_Type i2cNo, uint32_t data) -{ - uint32_t I2Cx = i2cAddr[i2cNo]; - uint32_t timeOut = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); - - timeOut = I2C_FIFO_STATUS_TIMEOUT; - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_1), I2C_TX_FIFO_CNT) == 0) { - timeOut--; - if (timeOut == 0) { - return TIMEOUT; - } - } - - BL_WR_REG(I2Cx, I2C_FIFO_WDATA, data); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief I2C read word data - * - * @param i2cNo: I2C ID type - * - * @return word data - * -*******************************************************************************/ -BL_Err_Type I2C_RecieveWord(I2C_ID_Type i2cNo, uint32_t *recvBuff) -{ - uint32_t I2Cx = i2cAddr[i2cNo]; - uint32_t timeOut = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); - - timeOut = I2C_FIFO_STATUS_TIMEOUT; - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_1), I2C_RX_FIFO_CNT) == 0) { - timeOut--; - - if (timeOut == 0) { - return TIMEOUT; - } - } - - *recvBuff = BL_RD_REG(I2Cx, I2C_FIFO_RDATA); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief I2C enable - * - * @param i2cNo: I2C ID type - * - * @return None - * -*******************************************************************************/ -void I2C_Enable(I2C_ID_Type i2cNo) -{ - uint32_t tmpVal; - uint32_t I2Cx = i2cAddr[i2cNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); - - tmpVal = BL_RD_REG(I2Cx, I2C_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_M_EN); - BL_WR_REG(I2Cx, I2C_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief I2C disable - * - * @param i2cNo: I2C ID type - * - * @return None - * -*******************************************************************************/ -void I2C_Disable(I2C_ID_Type i2cNo) -{ - uint32_t tmpVal; - uint32_t I2Cx = i2cAddr[i2cNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); - - tmpVal = BL_RD_REG(I2Cx, I2C_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_M_EN); - BL_WR_REG(I2Cx, I2C_CONFIG, tmpVal); - - /* Clear I2C fifo */ - tmpVal = BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_0); - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_TX_FIFO_CLR); - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_RX_FIFO_CLR); - BL_WR_REG(I2Cx, I2C_FIFO_CONFIG_0, tmpVal); - - /* Clear I2C interrupt status */ - tmpVal = BL_RD_REG(I2Cx, I2C_INT_STS); - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_END_CLR); - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_NAK_CLR); - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_ARB_CLR); - BL_WR_REG(I2Cx, I2C_INT_STS, tmpVal); -} - -/****************************************************************************/ /** - * @brief I2C set global reset function - * - * @param i2cNo: I2C ID type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type I2C_DeInit(I2C_ID_Type i2cNo) -{ - /* Check the parameters */ - CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); - - if (i2cNo == I2C0_ID || i2cNo == I2C1_ID) { - GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_I2C); - } else if (i2cNo == I2C0_MM_ID) { - GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_I2C0); - } else if (i2cNo == I2C1_MM_ID) { - GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_I2C1); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief I2C init function - * - * @param i2cNo: I2C ID type - * @param direct: I2C read or write direct - * @param cfg: I2C transfer config struct - * - * @return None - * -*******************************************************************************/ -void I2C_Init(I2C_ID_Type i2cNo, I2C_Direction_Type direct, I2C_Transfer_Cfg *cfg) -{ - uint32_t tmpVal; - uint32_t I2Cx = i2cAddr[i2cNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); - - /* set i2c clk,default is 400000,max support clk is 400000 */ - if (cfg->clk == 0 || cfg->clk > 400000){ - I2C_ClockSet(i2cNo, 400000); - } else { - I2C_ClockSet(i2cNo, cfg->clk); - } - - /* Disable clock gate when use I2C0 */ - if (I2C0_ID == i2cNo) { - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_I2C); - } else if (I2C1_ID == i2cNo) { - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_I2C1); - } - - /* I2C write config */ - tmpVal = BL_RD_REG(I2Cx, I2C_CONFIG); - - if (direct == I2C_WRITE) { - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_PKT_DIR); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_PKT_DIR); - } - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_SLV_ADDR, cfg->slaveAddr); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_10B_ADDR_EN, cfg->slaveAddr10Bit); - - if (cfg->subAddrSize > 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_SUB_ADDR_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_SUB_ADDR_BC, cfg->subAddrSize - 1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_SUB_ADDR_EN); - } - - /* align clock when 1 master*/ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_SCL_SYNC_EN, DISABLE); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PKT_LEN, cfg->dataSize - 1); - BL_WR_REG(I2Cx, I2C_CONFIG, tmpVal); - - /* Set sub address */ - BL_WR_REG(I2Cx, I2C_SUB_ADDR, cfg->subAddr); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(I2C0_IRQn, I2C0_IRQHandler); - Interrupt_Handler_Register(I2C1_IRQn, I2C1_IRQHandler); - Interrupt_Handler_Register(I2C2_IRQn, I2C2_IRQHandler); - Interrupt_Handler_Register(I2C3_IRQn, I2C2_IRQHandler); -#endif -} - -/****************************************************************************/ /** - * @brief Set de-glitch function cycle count value - * - * @param i2cNo: I2C ID type - * @param cnt: De-glitch function cycle count - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type I2C_SetDeglitchCount(I2C_ID_Type i2cNo, uint8_t cnt) -{ - uint32_t tmpVal; - uint32_t I2Cx = i2cAddr[i2cNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); - - tmpVal = BL_RD_REG(I2Cx, I2C_CONFIG); - - if (cnt > 0) { - /* enable de-glitch function */ - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_DEG_EN); - } else if (cnt == 0) { - /* disable de-glitch function */ - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_DEG_EN); - } else { - return ERROR; - } - - /* Set count value */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_DEG_CNT, cnt); - BL_WR_REG(I2Cx, I2C_CONFIG, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Set i2c prd - * - * @param i2cNo: I2C ID type - * @param phase: I2C phase value - * - * @return None - * -*******************************************************************************/ -void I2C_SetPrd(I2C_ID_Type i2cNo, uint8_t phase) -{ - uint32_t tmpVal; - uint32_t I2Cx = i2cAddr[i2cNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); - - //phase_cycles = (32000000 / phase / 4) - 1; - tmpVal = BL_RD_REG(I2Cx, I2C_PRD_START); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_S_PH_0, phase); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_S_PH_1, phase); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_S_PH_2, phase); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_S_PH_3, phase); - BL_WR_REG(I2Cx, I2C_PRD_START, tmpVal); - tmpVal = BL_RD_REG(I2Cx, I2C_PRD_STOP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_P_PH_0, phase); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_P_PH_1, phase); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_P_PH_2, phase); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_P_PH_3, phase); - BL_WR_REG(I2Cx, I2C_PRD_STOP, tmpVal); - tmpVal = BL_RD_REG(I2Cx, I2C_PRD_DATA); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_D_PH_0, phase); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_D_PH_1, phase); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_D_PH_2, phase); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_D_PH_3, phase); - BL_WR_REG(I2Cx, I2C_PRD_DATA, tmpVal); -} - -/****************************************************************************/ /** - * @brief I2C set scl output clock - * - * @param i2cNo: I2C ID type - * @param clk: Clock set - * - * @return None - * -*******************************************************************************/ -void I2C_ClockSet(I2C_ID_Type i2cNo, uint32_t clk) -{ - uint32_t bclk = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); - - if (i2cNo == I2C0_ID || i2cNo == I2C1_ID) { - bclk = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_PBCLK); - - if (clk >= 100000) { - GLB_Set_I2C_CLK(1, GLB_I2C_CLK_BCLK, 0); - I2C_SetPrd(i2cNo, bclk / (clk * 4) - 1); - } else if (clk >= 8000) { - GLB_Set_I2C_CLK(1, GLB_I2C_CLK_BCLK, 9); - I2C_SetPrd(i2cNo, bclk / 10 / (clk * 4) - 1); - } else if (clk >= 800) { - GLB_Set_I2C_CLK(1, GLB_I2C_CLK_BCLK, 99); - I2C_SetPrd(i2cNo, bclk / 100 / (clk * 4) - 1); - } else { - GLB_Set_I2C_CLK(1, GLB_I2C_CLK_BCLK, 255); - I2C_SetPrd(i2cNo, bclk / 256 / (clk * 4) - 1); - } - } else if (i2cNo == I2C0_MM_ID) { - bclk = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_DSP_PBCLK); - - if (clk >= 100000) { - GLB_Set_DSP_I2C0_CLK(1, 1, 1, 0); - I2C_SetPrd(i2cNo, bclk / (clk * 4) - 1); - } else if (clk >= 8000) { - GLB_Set_DSP_I2C0_CLK(1, 1, 1, 9); - I2C_SetPrd(i2cNo, bclk / 10 / (clk * 4) - 1); - } else if (clk >= 800) { - GLB_Set_DSP_I2C0_CLK(1, 1, 1, 99); - I2C_SetPrd(i2cNo, bclk / 100 / (clk * 4) - 1); - } else { - GLB_Set_DSP_I2C0_CLK(1, 1, 1, 255); - I2C_SetPrd(i2cNo, bclk / 256 / (clk * 4) - 1); - } - } else if (i2cNo == I2C1_MM_ID) { - bclk = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_DSP_PBCLK); - - if (clk >= 100000) { - GLB_Set_DSP_I2C1_CLK(1, 1, 1, 0); - I2C_SetPrd(i2cNo, bclk / (clk * 4) - 1); - } else if (clk >= 8000) { - GLB_Set_DSP_I2C1_CLK(1, 1, 1, 9); - I2C_SetPrd(i2cNo, bclk / 10 / (clk * 4) - 1); - } else if (clk >= 800) { - GLB_Set_DSP_I2C1_CLK(1, 1, 1, 99); - I2C_SetPrd(i2cNo, bclk / 100 / (clk * 4) - 1); - } else { - GLB_Set_DSP_I2C1_CLK(1, 1, 1, 255); - I2C_SetPrd(i2cNo, bclk / 256 / (clk * 4) - 1); - } - } -} - -/****************************************************************************/ /** - * @brief I2C set scl sync - * - * @param i2cNo: I2C ID type - * @param enable: Enable or disable I2C scl sync - * - * @return None - * -*******************************************************************************/ -void I2C_SetSclSync(I2C_ID_Type i2cNo, uint8_t enable) -{ - uint32_t tmpVal; - uint32_t I2Cx = i2cAddr[i2cNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); - - tmpVal = BL_RD_REG(I2Cx, I2C_CONFIG); - - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_SCL_SYNC_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_SCL_SYNC_EN); - } - - BL_WR_REG(I2Cx, I2C_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief Get i2c busy state - * - * @param i2cNo: I2C ID type - * - * @return RESET or SET - * -*******************************************************************************/ -BL_Sts_Type I2C_IsBusy(I2C_ID_Type i2cNo) -{ - uint32_t tmpVal; - uint32_t I2Cx = i2cAddr[i2cNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); - - tmpVal = BL_RD_REG(I2Cx, I2C_BUS_BUSY); - return ((BL_IS_REG_BIT_SET(tmpVal, I2C_STS_I2C_BUS_BUSY)) ? SET : RESET); -} - -/****************************************************************************/ /** - * @brief Get i2c transfer end state - * - * @param i2cNo: I2C ID type - * - * @return RESET or SET - * -*******************************************************************************/ -BL_Sts_Type I2C_TransferEndStatus(I2C_ID_Type i2cNo) -{ - uint32_t tmpVal; - uint32_t I2Cx = i2cAddr[i2cNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); - - tmpVal = BL_RD_REG(I2Cx, I2C_INT_STS); - return ((BL_IS_REG_BIT_SET(tmpVal, I2C_END_INT)) ? SET : RESET); -} - -/****************************************************************************/ /** - * @brief I2C master write block data - * - * @param i2cNo: I2C ID type - * @param cfg: I2C transfer config struct - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type I2C_MasterSendBlocking(I2C_ID_Type i2cNo, I2C_Transfer_Cfg *cfg) -{ - uint8_t i; - uint32_t timeOut = 0; - uint32_t temp = 0; - uint32_t I2Cx = i2cAddr[i2cNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); - - I2C_Disable(i2cNo); - I2C_Init(i2cNo, I2C_WRITE, cfg); - - /* Set I2C write data */ - for (i = 0; i < cfg->dataSize; i++) { - temp += (cfg->data[i] << ((i % 4) * 8)); - - if ((i + 1) % 4 == 0) { - timeOut = I2C_FIFO_STATUS_TIMEOUT; - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_1), I2C_TX_FIFO_CNT) == 0) { - timeOut--; - - if (timeOut == 0) { - I2C_Disable(i2cNo); - return TIMEOUT; - } - } - - BL_WR_REG(I2Cx, I2C_FIFO_WDATA, temp); - if(BL_GET_REG_BITS_VAL(BL_RD_REG(I2Cx, I2C_CONFIG), I2C_CR_I2C_M_EN) == 0) { - I2C_Enable(i2cNo); - } - temp = 0; - } - } - - if ((cfg->dataSize % 4) != 0) { - timeOut = I2C_FIFO_STATUS_TIMEOUT; - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_1), I2C_TX_FIFO_CNT) == 0) { - timeOut--; - - if (timeOut == 0) { - I2C_Disable(i2cNo); - return TIMEOUT; - } - } - - BL_WR_REG(I2Cx, I2C_FIFO_WDATA, temp); - if(BL_GET_REG_BITS_VAL(BL_RD_REG(I2Cx, I2C_CONFIG), I2C_CR_I2C_M_EN) == 0) { - I2C_Enable(i2cNo); - } - } - - timeOut = I2C_FIFO_STATUS_TIMEOUT; - - while (I2C_IsBusy(i2cNo) || !I2C_TransferEndStatus(i2cNo)) { - timeOut--; - - if (timeOut == 0) { - I2C_Disable(i2cNo); - return TIMEOUT; - } - } - - I2C_Disable(i2cNo); - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief I2C master read block data - * - * @param i2cNo: I2C ID type - * @param cfg: I2C transfer config struct - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type I2C_MasterReceiveBlocking(I2C_ID_Type i2cNo, I2C_Transfer_Cfg *cfg) -{ - uint8_t i = 0; - uint32_t timeOut = 0; - uint32_t temp = 0; - uint32_t I2Cx = i2cAddr[i2cNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); - - I2C_Disable(i2cNo); - I2C_Init(i2cNo, I2C_READ, cfg); - I2C_Enable(i2cNo); - - /* Read I2C data */ - while (cfg->dataSize - i >= 4) { - timeOut = I2C_FIFO_STATUS_TIMEOUT; - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_1), I2C_RX_FIFO_CNT) == 0) { - timeOut--; - - if (timeOut == 0) { - I2C_Disable(i2cNo); - return TIMEOUT; - } - } - - temp = BL_RD_REG(I2Cx, I2C_FIFO_RDATA); - PUT_UINT32_LE(temp, cfg->data, i); - i += 4; - } - - if (i < cfg->dataSize) { - timeOut = I2C_FIFO_STATUS_TIMEOUT; - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_1), I2C_RX_FIFO_CNT) == 0) { - timeOut--; - - if (timeOut == 0) { - I2C_Disable(i2cNo); - return TIMEOUT; - } - } - - temp = BL_RD_REG(I2Cx, I2C_FIFO_RDATA); - - while (i < cfg->dataSize) { - cfg->data[i] = (temp & 0xff); - temp = (temp >> 8); - i++; - } - } - - timeOut = I2C_FIFO_STATUS_TIMEOUT; - - while (I2C_IsBusy(i2cNo) || !I2C_TransferEndStatus(i2cNo)) { - timeOut--; - - if (timeOut == 0) { - I2C_Disable(i2cNo); - return TIMEOUT; - } - } - - I2C_Disable(i2cNo); - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Mask/Unmask the I2C interrupt - * - * @param i2cNo: I2C ID type - * @param intType: Specifies the interrupt type - * @param intMask: Enable/Disable Specified interrupt type - * - * @return None - * -*******************************************************************************/ -void I2C_IntMask(I2C_ID_Type i2cNo, I2C_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpVal; - uint32_t I2Cx = i2cAddr[i2cNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); - CHECK_PARAM(IS_I2C_INT_TYPE(intType)); - CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); - - tmpVal = BL_RD_REG(I2Cx, I2C_INT_STS); - - switch (intType) { - case I2C_TRANS_END_INT: - if (intMask == UNMASK) { - /* UNMASK(Enable) this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_END_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_END_MASK); - } else { - /* MASK(Disable) this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_END_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_END_MASK); - } - - break; - - case I2C_TX_FIFO_READY_INT: - if (intMask == UNMASK) { - /* UNMASK(Enable) this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_TXF_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_TXF_MASK); - } else { - /* MASK(Disable) this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_TXF_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_TXF_MASK); - } - - break; - - case I2C_RX_FIFO_READY_INT: - if (intMask == UNMASK) { - /* UNMASK(Enable) this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_RXF_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_RXF_MASK); - } else { - /* MASK(Disable) this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_RXF_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_RXF_MASK); - } - - break; - - case I2C_NACK_RECV_INT: - if (intMask == UNMASK) { - /* UNMASK(Enable) this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_NAK_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_NAK_MASK); - } else { - /* MASK(Disable) this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_NAK_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_NAK_MASK); - } - - break; - - case I2C_ARB_LOST_INT: - if (intMask == UNMASK) { - /* UNMASK(Enable) this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_ARB_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_ARB_MASK); - } else { - /* MASK(Disable) this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_ARB_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_ARB_MASK); - } - - break; - - case I2C_FIFO_ERR_INT: - if (intMask == UNMASK) { - /* UNMASK(Enable) this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_FER_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_FER_MASK); - } else { - /* MASK(Disable) this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_FER_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_FER_MASK); - } - - break; - - case I2C_INT_ALL: - if (intMask == UNMASK) { - /* UNMASK(Enable) this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_END_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_TXF_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_RXF_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_NAK_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_ARB_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_FER_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_END_MASK); - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_TXF_MASK); - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_RXF_MASK); - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_NAK_MASK); - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_ARB_MASK); - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_FER_MASK); - } else { - /* MASK(Disable) this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_END_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_TXF_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_RXF_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_NAK_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_ARB_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_FER_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_END_MASK); - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_TXF_MASK); - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_RXF_MASK); - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_NAK_MASK); - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_ARB_MASK); - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_FER_MASK); - } - - break; - - default: - break; - } - - BL_WR_REG(I2Cx, I2C_INT_STS, tmpVal); -} - -/****************************************************************************/ /** - * @brief Install I2C interrupt callback function - * - * @param i2cNo: I2C ID type - * @param intType: Specifies the interrupt type - * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void I2C_Int_Callback_Install(I2C_ID_Type i2cNo, I2C_INT_Type intType, intCallback_Type *cbFun) -{ - /* Check the parameters */ - CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); - CHECK_PARAM(IS_I2C_INT_TYPE(intType)); - - i2cIntCbfArra[i2cNo][intType] = cbFun; -} -#endif - -/****************************************************************************/ /** - * @brief I2C0 IRQ handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void I2C0_IRQHandler(void) -{ - I2C_IntHandler(I2C0_ID); -} -#endif - -/****************************************************************************/ /** - * @brief I2C1 IRQ handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void I2C1_IRQHandler(void) -{ - I2C_IntHandler(I2C1_ID); -} -#endif - -/****************************************************************************/ /** - * @brief I2C2 IRQ handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void I2C2_IRQHandler(void) -{ - I2C_IntHandler(I2C0_MM_ID); -} -#endif - -/****************************************************************************/ /** - * @brief I2C3 IRQ handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void I2C3_IRQHandler(void) -{ - I2C_IntHandler(I2C1_MM_ID); -} -#endif - -/*@} end of group I2C_Public_Functions */ - -/*@} end of group I2C */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_i2s.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_i2s.c deleted file mode 100644 index 5e8fb35959..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_i2s.c +++ /dev/null @@ -1,508 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_i2s.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_i2s.h" -#include "bl808_glb.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup I2S - * @{ - */ - -/** @defgroup I2S_Private_Macros - * @{ - */ - -static const uint32_t i2sAddr[I2S_ID_MAX] = { I2S_BASE }; -#define I2S_USE_ID I2S0_ID - -/*@} end of group I2S_Private_Macros */ - -/** @defgroup I2S_Private_Types - * @{ - */ - -/*@} end of group I2S_Private_Types */ - -/** @defgroup I2S_Private_Variables - * @{ - */ - -/*@} end of group I2S_Private_Variables */ - -/** @defgroup I2S_Global_Variables - * @{ - */ - -/*@} end of group I2S_Global_Variables */ - -/** @defgroup I2S_Private_Fun_Declaration - * @{ - */ - -/*@} end of group I2S_Private_Fun_Declaration */ - -/** @defgroup I2S_Private_Functions - * @{ - */ - -/*@} end of group I2S_Private_Functions */ - -/** @defgroup I2S_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief I2S BCLK config - * - * @param i2sId: I2S ID type - * @param i2sCfg: I2S configuration pointer - * - * @return NONE - * -*******************************************************************************/ -void I2S_SetBclkPeriod(I2S_ID_Type i2sId, I2S_CFG_Type *i2sCfg) -{ - uint32_t overSampleRate; - uint32_t bclkDivCnt; - uint32_t tmpVal; - uint8_t enumOffset = 2; - uint32_t I2Sx = i2sAddr[i2sId]; - - CHECK_PARAM(IS_I2S_FRAME_SIZE_TYPE(i2sCfg->frameSize)); - - if (i2sCfg->fsChannel == I2S_FS_CHANNELS_6) { - enumOffset = 3; - } - overSampleRate = i2sCfg->audioFreqHz / i2sCfg->sampleFreqHz; - - switch (i2sCfg->frameSize) { - case I2S_SIZE_FRAME_8: - bclkDivCnt = overSampleRate / (8 * (i2sCfg->fsChannel + enumOffset)); - break; - - case I2S_SIZE_FRAME_16: - bclkDivCnt = overSampleRate / (16 * (i2sCfg->fsChannel + enumOffset)); - break; - - case I2S_SIZE_FRAME_24: - bclkDivCnt = overSampleRate / (24 * (i2sCfg->fsChannel + enumOffset)); - break; - - case I2S_SIZE_FRAME_32: - bclkDivCnt = overSampleRate / (32 * (i2sCfg->fsChannel + enumOffset)); - break; - - default: - bclkDivCnt = overSampleRate / (16 * (i2sCfg->fsChannel + enumOffset)); - break; - } - - bclkDivCnt = (bclkDivCnt / 2) - 1; - - tmpVal = (bclkDivCnt << 16) | bclkDivCnt; - BL_WR_REG(I2Sx, I2S_BCLK_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief I2S configuration - * - * @param i2sId: I2S ID type - * @param i2sCfg: I2S configuration pointer - * - * @return NONE - * -*******************************************************************************/ -void I2S_Init(I2S_ID_Type i2sId, I2S_CFG_Type *i2sCfg) -{ - uint32_t tmpVal; - uint32_t I2Sx = i2sAddr[i2sId]; - - /* Check the parameters */ - CHECK_PARAM(IS_I2S_ENDIAN_TYPE(i2sCfg->endianType)); - CHECK_PARAM(IS_I2S_MODE_TYPE(i2sCfg->modeType)); - CHECK_PARAM(IS_I2S_FRAME_SIZE_TYPE(i2sCfg->frameSize)); - CHECK_PARAM(IS_I2S_FS_MODE_TYPE(i2sCfg->fsMode)); - CHECK_PARAM(IS_I2S_FS_CHANNEL_TYPE(i2sCfg->fsChannel)); - CHECK_PARAM(IS_I2S_DATA_SIZE_TYPE(i2sCfg->dataSize)); - CHECK_PARAM(IS_I2S_MONO_MODE_CHANNEL(i2sCfg->monoModeChannel)); - - /* Disable clock gate */ - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_I2S); - - tmpVal = BL_RD_REG(I2Sx, I2S_CONFIG); - - /* Set data endian*/ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_ENDIAN, i2sCfg->endianType); - - /* Set I2S mode */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_I2S_MODE, i2sCfg->modeType); - - /* Set BCLK invert */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_I2S_BCLK_INV, i2sCfg->bclkInvert); - - /* Set FS size */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_FRAME_SIZE, i2sCfg->frameSize); - - /* Set FS invert */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_I2S_FS_INV, i2sCfg->fsInvert); - - /* Set FS mode */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_FS_1T_MODE, i2sCfg->fsMode); - - /* Set FS channel mode */ - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_FS_CH_CNT, i2sCfg->fsChannel); - - /* Set Data size */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_DATA_SIZE, i2sCfg->dataSize); - - /* Set Data offset */ - if (i2sCfg->dataOffset != 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, I2S_CR_OFS_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_OFS_CNT, i2sCfg->dataOffset - 1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_OFS_EN); - } - - /* Set mono mode */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_MONO_MODE, i2sCfg->monoMode); - - /* Set rx mono mode channel left or right */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_MONO_RX_CH, i2sCfg->monoModeChannel); - - /* Clear mute mode */ - tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_MUTE_MODE); - - BL_WR_REG(I2Sx, I2S_CONFIG, tmpVal); - - I2S_SetBclkPeriod(I2S_USE_ID, i2sCfg); -} - -/****************************************************************************/ /** - * @brief I2S configure FIFO function - * - * @param i2sId: I2S ID type - * @param fifoCfg: FIFO configuration structure pointer - * - * @return None - * -*******************************************************************************/ -void I2S_FifoConfig(I2S_ID_Type i2sId, I2S_FifoCfg_Type *fifoCfg) -{ - uint32_t tmpVal; - uint32_t I2Sx = i2sAddr[i2sId]; - - tmpVal = BL_RD_REG(I2Sx, I2S_FIFO_CONFIG_0); - /* Set packed mode */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_FIFO_LR_MERGE, fifoCfg->lRMerge); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_FIFO_LR_EXCHG, fifoCfg->frameDataExchange); - /* Clear tx and rx FIFO signal */ - tmpVal = BL_SET_REG_BIT(tmpVal, I2S_TX_FIFO_CLR); - tmpVal = BL_SET_REG_BIT(tmpVal, I2S_RX_FIFO_CLR); - - /* Set DMA config */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_DMA_TX_EN, fifoCfg->txfifoDmaEnable); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_DMA_RX_EN, fifoCfg->rxfifoDmaEnable); - - BL_WR_REG(I2Sx, I2S_FIFO_CONFIG_0, tmpVal); - - /* Set CLR signal to 0*/ - tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_TX_FIFO_CLR); - tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_RX_FIFO_CLR); - BL_WR_REG(I2Sx, I2S_FIFO_CONFIG_0, tmpVal); - - tmpVal = BL_RD_REG(I2Sx, I2S_FIFO_CONFIG_1); - /* Set TX and RX FIFO threshold */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_TX_FIFO_TH, fifoCfg->txFifoLevel); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_RX_FIFO_TH, fifoCfg->rxFifoLevel); - - BL_WR_REG(I2Sx, I2S_FIFO_CONFIG_1, tmpVal); -} - -/****************************************************************************/ /** - * @brief I2S configure IO function - * - * @param i2sId: I2S ID type - * @param ioCfg: IO configuration structure pointer - * - * @return None - * -*******************************************************************************/ -void I2S_IOConfig(I2S_ID_Type i2sId, I2S_IOCfg_Type *ioCfg) -{ - uint32_t tmpVal; - uint32_t I2Sx = i2sAddr[i2sId]; - - tmpVal = BL_RD_REG(I2Sx, I2S_IO_CONFIG); - /* Enable or disable deglitch */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_DEG_EN, ioCfg->deglitchEn); - - /* Set deglitch cycle count */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_DEG_CNT, ioCfg->deglitchCnt); - - /* Enable or disable inverse BCLK signal */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_I2S_BCLK_INV, ioCfg->inverseBCLK); - - /* Enable or disable inverse FS signal */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_I2S_FS_INV, ioCfg->inverseFS); - - /* Enable or disable inverse RX signal */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_I2S_RXD_INV, ioCfg->inverseRX); - - /* Enable or disable inverse TX signal */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_I2S_TXD_INV, ioCfg->inverseTX); - - BL_WR_REG(I2Sx, I2S_IO_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief Enable I2S - * - * @param i2sId: I2S ID type - * @param roleType: I2S master or slave - * - * @return None - * -*******************************************************************************/ -void I2S_Enable(I2S_ID_Type i2sId, I2S_Role_Type roleType) -{ - uint32_t tmpVal; - uint32_t I2Sx = i2sAddr[i2sId]; - - /* Check the parameters */ - CHECK_PARAM(IS_I2S_ROLE_TYPE(roleType)); - - tmpVal = BL_RD_REG(I2Sx, I2S_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, I2S_CR_I2S_TXD_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, I2S_CR_I2S_RXD_EN); - - /* Set role type */ - if (I2S_ROLE_MASTER == roleType) { - tmpVal = BL_SET_REG_BIT(tmpVal, I2S_CR_I2S_M_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_I2S_S_EN); - } else if (I2S_ROLE_SLAVE == roleType) { - tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_I2S_M_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, I2S_CR_I2S_S_EN); - } - - BL_WR_REG(I2Sx, I2S_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief Disable I2S - * - * @param i2sId: I2S ID type - * - * @return None - * -*******************************************************************************/ -void I2S_Disable(I2S_ID_Type i2sId) -{ - uint32_t tmpVal; - uint32_t I2Sx = i2sAddr[i2sId]; - - tmpVal = BL_RD_REG(I2Sx, I2S_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_I2S_TXD_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_I2S_RXD_EN); - - tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_I2S_M_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_I2S_S_EN); - BL_WR_REG(I2Sx, I2S_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief I2S read data - * - * @param i2sId: I2S ID type - * - * @return Data read - * -*******************************************************************************/ -uint32_t I2S_Read(I2S_ID_Type i2sId) -{ - uint32_t I2Sx = i2sAddr[i2sId]; - - while (0 == BL_GET_REG_BITS_VAL(BL_RD_REG(I2Sx, I2S_FIFO_CONFIG_1), I2S_RX_FIFO_CNT)) { - }; - - return BL_RD_REG(I2Sx, I2S_FIFO_RDATA); -} - -/****************************************************************************/ /** - * @brief I2S write data - * - * @param i2sId: I2S ID type - * @param data: write data - * - * @return None - * -*******************************************************************************/ -void I2S_Write(I2S_ID_Type i2sId, uint32_t data) -{ - uint32_t I2Sx = i2sAddr[i2sId]; - - while (0 == BL_GET_REG_BITS_VAL(BL_RD_REG(I2Sx, I2S_FIFO_CONFIG_1), I2S_TX_FIFO_CNT)) { - }; - - BL_WR_REG(I2Sx, I2S_FIFO_WDATA, data); -} - -/****************************************************************************/ /** - * @brief I2S set mute - * - * @param i2sId: I2S ID type - * @param enabled: mute enabled or not - * - * @return None - * -*******************************************************************************/ -void I2S_Mute(I2S_ID_Type i2sId, BL_Fun_Type enabled) -{ - uint32_t tmpVal; - uint32_t I2Sx = i2sAddr[i2sId]; - - tmpVal = BL_RD_REG(I2Sx, I2S_CONFIG); - - if (enabled ? 1 : 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, I2S_CR_MUTE_MODE); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_MUTE_MODE); - } - - BL_WR_REG(I2Sx, I2S_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief I2S set 24-bit data align mode in fifo - * - * @param i2sId: I2S ID type - * @param justType: Align mode - * - * @return None - * -*******************************************************************************/ -void I2S_SetFifoJustified(I2S_ID_Type i2sId, I2S_FIFO_24_Justified_Type justType) -{ - uint32_t tmpVal; - uint32_t I2Sx = i2sAddr[i2sId]; - - /* Check the parameters */ - CHECK_PARAM(IS_I2S_FIFO_24_JUSTIFIED_TYPE(justType)); - - tmpVal = BL_RD_REG(I2Sx, I2S_FIFO_CONFIG_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_FIFO_24B_LJ, justType); - BL_WR_REG(I2Sx, I2S_FIFO_CONFIG_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief I2S flush - * - * @param i2sId: I2S ID type - * - * @return data count in TX FIFO - * -*******************************************************************************/ -uint32_t I2S_GetTxFIFO_AvlCnt(I2S_ID_Type i2sId) -{ - uint32_t I2Sx = i2sAddr[i2sId]; - - return BL_GET_REG_BITS_VAL(BL_RD_REG(I2Sx, I2S_FIFO_CONFIG_1), I2S_TX_FIFO_CNT); -} - -/****************************************************************************/ /** - * @brief I2S flush - * -* @param i2sId: I2S ID type - * - * @return data count in RX FIFO - * -*******************************************************************************/ -uint32_t I2S_GetRxFIFO_AvlCnt(I2S_ID_Type i2sId) -{ - uint32_t I2Sx = i2sAddr[i2sId]; - - return BL_GET_REG_BITS_VAL(BL_RD_REG(I2Sx, I2S_FIFO_CONFIG_1), I2S_RX_FIFO_CNT); -} - -/****************************************************************************/ /** - * @brief I2S flush - * - * @param i2sId: I2S ID type - * - * @return None - * -*******************************************************************************/ -void I2S_Tx_FIFO_Flush(I2S_ID_Type i2sId) -{ - uint32_t tmpVal; - uint32_t I2Sx = i2sAddr[i2sId]; - - tmpVal = BL_RD_REG(I2Sx, I2S_FIFO_CONFIG_0); - - tmpVal = BL_SET_REG_BIT(tmpVal, I2S_TX_FIFO_CLR); - - BL_WR_REG(I2Sx, I2S_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief I2S flush - * - * @param i2sId: I2S ID type - * - * @return None - * -*******************************************************************************/ -void I2S_Rx_FIFO_Flush(I2S_ID_Type i2sId) -{ - uint32_t tmpVal; - uint32_t I2Sx = i2sAddr[i2sId]; - - tmpVal = BL_RD_REG(I2Sx, I2S_FIFO_CONFIG_0); - - tmpVal = BL_SET_REG_BIT(tmpVal, I2S_RX_FIFO_CLR); - - BL_WR_REG(I2Sx, I2S_FIFO_CONFIG_0, tmpVal); -} - -/*@} end of group I2S_Public_Functions */ - -/*@} end of group I2S */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_ipc.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_ipc.c deleted file mode 100644 index 952504ab10..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_ipc.c +++ /dev/null @@ -1,737 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_ipc.c - * @version V1.2 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2018 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_ipc.h" - -/** @addtogroup BL606P_Peripheral_Driver - * @{ - */ - -/** @addtogroup IPC - * @{ - */ - -/** @defgroup IPC_Private_Macros - * @{ - */ -#define IPC_LP_OFFSET_IN_M0 0 -#define IPC_D0_OFFSET_IN_M0 16 - -#define IPC_M0_OFFSET_IN_LP 0 -#define IPC_D0_OFFSET_IN_LP 16 - -#define IPC_M0_OFFSET_IN_D0 0 -#define IPC_LP_OFFSET_IN_D0 16 - -/*@} end of group IPC_Private_Macros */ - -/** @defgroup IPC_Private_Types - * @{ - */ - -/*@} end of group IPC_Private_Types */ - -/** @defgroup IPC_Private_Variables - * @{ - */ - -ipcIntCallback *m0IpcIntCbfArra[GLB_CORE_ID_MAX - 1] = { NULL }; -ipcIntCallback *lpIpcIntCbfArra[GLB_CORE_ID_MAX - 1] = { NULL }; -ipcIntCallback *d0IpcIntCbfArra[GLB_CORE_ID_MAX - 1] = { NULL }; - -/*@} end of group IPC_Private_Variables */ - -/** @defgroup IPC_Global_Variables - * @{ - */ - -/*@} end of group IPC_Global_Variables */ - -/** @defgroup IPC_Private_Fun_Declaration - * @{ - */ - -/*@} end of group IPC_Private_Fun_Declaration */ - -/** @defgroup IPC_Private_Functions - * @{ - */ - -/*@} end of group IPC_Private_Functions */ - -/** @defgroup IPC_Public_Functions - * @{ - */ -#if defined(CPU_M0) || defined(CPU_LP) -/****************************************************************************/ /** - * @brief M0 IPC interrupt init - * - * @param onLPTriggerCallBack: Callback when LP trigger - * - * @param onD0TriggerCallBack: Callback when D0 trigger - * - * @return None - * -*******************************************************************************/ -void IPC_M0_Init(ipcIntCallback *onLPTriggerCallBack, - ipcIntCallback *onD0TriggerCallBack) -{ - m0IpcIntCbfArra[0] = onLPTriggerCallBack; - m0IpcIntCbfArra[1] = onD0TriggerCallBack; - - IPC_M0_Int_Unmask_By_Word(0xffffffff); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(IPC_M0_IRQn, IPC_M0_IRQHandler); -#endif - CPU_Interrupt_Enable(IPC_M0_IRQn); -} -#endif - -/****************************************************************************/ /** - * @brief M0 unmask IPC interrupt - * - * @param src: M0 IPC interrupt source - * - * @return None - * -*******************************************************************************/ -void IPC_M0_Int_Unmask(IPC_Int_Src_Type src) -{ - uint32_t tmpVal = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_IPC_INT_SRC_TYPE(src)); - - tmpVal = (1 << src); - - BL_WR_REG(IPC0_BASE, IPC_CPU0_IPC_IUSR, tmpVal); -} - -/****************************************************************************/ /** - * @brief M0 unmask IPC interrupt by word - * - * @param src: IPC interrupt source in word,every bit is interrupt source - * - * @return None - * -*******************************************************************************/ -void IPC_M0_Int_Unmask_By_Word(uint32_t src) -{ - BL_WR_REG(IPC0_BASE, IPC_CPU0_IPC_IUSR, src); -} - -/****************************************************************************/ /** - * @brief M0 get IPC interrupt raw status - * - * @param None - * - * @return IPC interrupt raw status - * -*******************************************************************************/ -uint32_t IPC_M0_Get_Int_Raw_Status(void) -{ - return BL_RD_REG(IPC0_BASE, IPC_CPU0_IPC_IRSRR); -} - -/****************************************************************************/ /** - * @brief M0 clear IPC interrupt - * - * @param src: M0 IPC interrupt source - * - * @return None - * -*******************************************************************************/ -void IPC_M0_Clear_Int(IPC_Int_Src_Type src) -{ - uint32_t tmpVal = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_IPC_INT_SRC_TYPE(src)); - - tmpVal = (1 << src); - - BL_WR_REG(IPC0_BASE, IPC_CPU0_IPC_ICR, tmpVal); -} - -/****************************************************************************/ /** - * @brief M0 clear IPC interrupt by word - * - * @param src: IPC interrupt source in word,every bit is interrupt source - * - * @return None - * -*******************************************************************************/ -void IPC_M0_Clear_Int_By_Word(uint32_t src) -{ - BL_WR_REG(IPC0_BASE, IPC_CPU0_IPC_ICR, src); -} - -/****************************************************************************/ /** - * @brief CPUx trigger IPC interrupt to M0 - * - * @param src: IPC interrupt source - * - * @param cpuxOffset: CPU interrupt offset - * - * @return None - * -*******************************************************************************/ -void IPC_CPUx_Trigger_M0(IPC_Grp_Int_Src_Type src, uint8_t cpuxOffset) -{ - uint32_t tmpVal = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_IPC_Grp_Int_Src_Type(src)); - - tmpVal = (1 << (src + cpuxOffset)); - - BL_WR_REG(IPC0_BASE, IPC_CPU1_IPC_ISWR, tmpVal); -} - -/****************************************************************************/ /** - * @brief LP trigger IPC interrupt to M0 - * - * @param src: LP IPC interrupt source - * - * @return None - * -*******************************************************************************/ -void IPC_LP_Trigger_M0(IPC_Grp_Int_Src_Type src) -{ - IPC_CPUx_Trigger_M0(src, IPC_LP_OFFSET_IN_M0); -} - -/****************************************************************************/ /** - * @brief D0 trigger IPC interrupt to M0 - * - * @param src: D0 IPC interrupt source - * - * @return None - * -*******************************************************************************/ -void IPC_D0_Trigger_M0(IPC_Grp_Int_Src_Type src) -{ - IPC_CPUx_Trigger_M0(src, IPC_D0_OFFSET_IN_M0); -} - -#if defined(CPU_M0) || defined(CPU_LP) -/****************************************************************************/ /** - * @brief LP IPC interrupt init - * - * @param onM0TriggerCallBack: Callback when M0 trigger - * - * @param onD0TriggerCallBack: Callback when D0 trigger - * - * @return None - * -*******************************************************************************/ -void IPC_LP_Init(ipcIntCallback *onM0TriggerCallBack, - ipcIntCallback *onD0TriggerCallBack) -{ - lpIpcIntCbfArra[0] = onM0TriggerCallBack; - lpIpcIntCbfArra[1] = onD0TriggerCallBack; - - IPC_LP_Int_Unmask_By_Word(0xffffffff); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(IPC_LP_IRQn, IPC_LP_IRQHandler); -#endif - CPU_Interrupt_Enable(IPC_LP_IRQn); -} -#endif - -/****************************************************************************/ /** - * @brief LP unmask IPC interrupt - * - * @param src: LP IPC interrupt source - * - * @return None - * -*******************************************************************************/ -void IPC_LP_Int_Unmask(IPC_Int_Src_Type src) -{ - uint32_t tmpVal = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_IPC_INT_SRC_TYPE(src)); - - tmpVal = (1 << src); - - BL_WR_REG(IPC1_BASE, IPC_CPU0_IPC_IUSR, tmpVal); -} - -/****************************************************************************/ /** - * @brief LP unmask IPC interrupt by word - * - * @param src: IPC interrupt source in word,every bit is interrupt source - * - * @return None - * -*******************************************************************************/ -void IPC_LP_Int_Unmask_By_Word(uint32_t src) -{ - BL_WR_REG(IPC1_BASE, IPC_CPU0_IPC_IUSR, src); -} - -/****************************************************************************/ /** - * @brief LP get IPC interrupt raw status - * - * @param None - * - * @return IPC interrupt raw status - * -*******************************************************************************/ -uint32_t IPC_LP_Get_Int_Raw_Status(void) -{ - return BL_RD_REG(IPC1_BASE, IPC_CPU0_IPC_IRSRR); -} - -/****************************************************************************/ /** - * @brief LP clear IPC interrupt - * - * @param src: LP IPC interrupt source - * - * @return None - * -*******************************************************************************/ -void IPC_LP_Clear_Int(IPC_Int_Src_Type src) -{ - uint32_t tmpVal = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_IPC_INT_SRC_TYPE(src)); - - tmpVal = (1 << src); - - BL_WR_REG(IPC1_BASE, IPC_CPU0_IPC_ICR, tmpVal); -} - -/****************************************************************************/ /** - * @brief LP clear IPC interrupt by word - * - * @param src: IPC interrupt source in word,every bit is interrupt source - * - * @return None - * -*******************************************************************************/ -void IPC_LP_Clear_Int_By_Word(uint32_t src) -{ - BL_WR_REG(IPC1_BASE, IPC_CPU0_IPC_ICR, src); -} - -/****************************************************************************/ /** - * @brief CPUx trigger IPC interrupt to LP - * - * @param src: IPC interrupt source - * - * @param cpuxOffset: CPU interrupt offset - * - * @return None - * -*******************************************************************************/ -void IPC_CPUx_Trigger_LP(IPC_Grp_Int_Src_Type src, uint8_t cpuxOffset) -{ - uint32_t tmpVal = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_IPC_Grp_Int_Src_Type(src)); - - tmpVal = (1 << (src + cpuxOffset)); - - BL_WR_REG(IPC1_BASE, IPC_CPU1_IPC_ISWR, tmpVal); -} - -/****************************************************************************/ /** - * @brief M0 trigger IPC interrupt to LP - * - * @param src: M0 IPC interrupt source - * - * @return None - * -*******************************************************************************/ -void IPC_M0_Trigger_LP(IPC_Grp_Int_Src_Type src) -{ - IPC_CPUx_Trigger_LP(src, IPC_M0_OFFSET_IN_LP); -} - -/****************************************************************************/ /** - * @brief D0 trigger IPC interrupt to LP - * - * @param src: D0 IPC interrupt source - * - * @return None - * -*******************************************************************************/ -void IPC_D0_Trigger_LP(IPC_Grp_Int_Src_Type src) -{ - IPC_CPUx_Trigger_LP(src, IPC_D0_OFFSET_IN_LP); -} - -#if defined(CPU_D0) || defined(CPU_D1) -/****************************************************************************/ /** - * @brief D0 IPC interrupt init - * - * @param onM0TriggerCallBack: Callback when M0 trigger - * - * @param onLPTriggerCallBack: Callback when LP trigger - * - * @return None - * -*******************************************************************************/ -void IPC_D0_Init(ipcIntCallback *onM0TriggerCallBack, - ipcIntCallback *onLPTriggerCallBack) -{ - d0IpcIntCbfArra[0] = onM0TriggerCallBack; - d0IpcIntCbfArra[1] = onLPTriggerCallBack; - - IPC_D0_Int_Unmask_By_Word(0xffffffff); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(IPC_D0_IRQn, IPC_D0_IRQHandler); -#endif - CPU_Interrupt_Enable(IPC_D0_IRQn); -} -#endif - -/****************************************************************************/ /** - * @brief D0 unmask IPC interrupt - * - * @param src: D0 IPC interrupt source - * - * @return None - * -*******************************************************************************/ -void IPC_D0_Int_Unmask(IPC_Int_Src_Type src) -{ - uint32_t tmpVal = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_IPC_INT_SRC_TYPE(src)); - - tmpVal = (1 << src); - - BL_WR_REG(IPC2_BASE, IPC_CPU0_IPC_IUSR, tmpVal); -} - -/****************************************************************************/ /** - * @brief D0 unmask IPC interrupt by word - * - * @param src: D0 IPC interrupt source - * - * @return None - * -*******************************************************************************/ -void IPC_D0_Int_Unmask_By_Word(uint32_t src) -{ - BL_WR_REG(IPC2_BASE, IPC_CPU0_IPC_IUSR, src); -} - -/****************************************************************************/ /** - * @brief D0 get IPC interrupt raw status - * - * @param None - * - * @return IPC interrupt raw status - * -*******************************************************************************/ -uint32_t IPC_D0_Get_Int_Raw_Status(void) -{ - return BL_RD_REG(IPC2_BASE, IPC_CPU0_IPC_IRSRR); -} - -/****************************************************************************/ /** - * @brief D0 clear IPC interrupt - * - * @param src: D0 IPC interrupt source - * - * @return None - * -*******************************************************************************/ -void IPC_D0_Clear_Int(IPC_Int_Src_Type src) -{ - uint32_t tmpVal = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_IPC_INT_SRC_TYPE(src)); - - tmpVal = (1 << src); - - BL_WR_REG(IPC2_BASE, IPC_CPU0_IPC_ICR, tmpVal); -} - -/****************************************************************************/ /** - * @brief D0 clear IPC interrupt by word - * - * @param src: IPC interrupt source in word,every bit is interrupt source - * - * @return None - * -*******************************************************************************/ -void IPC_D0_Clear_Int_By_Word(uint32_t src) -{ - BL_WR_REG(IPC2_BASE, IPC_CPU0_IPC_ICR, src); -} - -/****************************************************************************/ /** - * @brief CPUx trigger IPC interrupt to D0 - * - * @param src: IPC interrupt source - * - * @param cpuxOffset: CPU interrupt offset - * - * @return None - * -*******************************************************************************/ -void IPC_CPUx_Trigger_D0(IPC_Grp_Int_Src_Type src, uint8_t cpuxOffset) -{ - uint32_t tmpVal = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_IPC_Grp_Int_Src_Type(src)); - - tmpVal = (1 << (src + cpuxOffset)); - - BL_WR_REG(IPC2_BASE, IPC_CPU1_IPC_ISWR, tmpVal); -} - -/****************************************************************************/ /** - * @brief M0 trigger IPC interrupt to D0 - * - * @param src: M0 IPC interrupt source - * - * @return None - * -*******************************************************************************/ -void IPC_M0_Trigger_D0(IPC_Grp_Int_Src_Type src) -{ - IPC_CPUx_Trigger_D0(src, IPC_M0_OFFSET_IN_D0); -} - -/****************************************************************************/ /** - * @brief LP trigger IPC interrupt to D0 - * - * @param src: LP IPC interrupt source - * - * @return None - * -*******************************************************************************/ -void IPC_LP_Trigger_D0(IPC_Grp_Int_Src_Type src) -{ - IPC_CPUx_Trigger_D0(src, IPC_LP_OFFSET_IN_D0); -} - -/****************************************************************************/ /** - * @brief M0 trigger IPC interrupt to CPUx - * - * @param tgtCPU: Target CPU - * - * @param src: IPC interrupt source - * - * @return None - * -*******************************************************************************/ -void IPC_M0_Trigger_CPUx(GLB_CORE_ID_Type tgtCPU, IPC_Grp_Int_Src_Type src) -{ - switch (tgtCPU) { - case GLB_CORE_ID_LP: - IPC_M0_Trigger_LP(src); - break; - case GLB_CORE_ID_D0: - IPC_M0_Trigger_D0(src); - break; - default: - break; - } -} - -/****************************************************************************/ /** - * @brief LP trigger IPC interrupt to CPUx - * - * @param tgtCPU: Target CPU - * - * @param src: IPC interrupt source - * - * @return None - * -*******************************************************************************/ -void IPC_LP_Trigger_CPUx(GLB_CORE_ID_Type tgtCPU, IPC_Grp_Int_Src_Type src) -{ - switch (tgtCPU) { - case GLB_CORE_ID_M0: - IPC_LP_Trigger_M0(src); - break; - case GLB_CORE_ID_D0: - IPC_LP_Trigger_D0(src); - break; - default: - break; - } -} - -/****************************************************************************/ /** - * @brief D0 trigger IPC interrupt to CPUx - * - * @param tgtCPU: Target CPU - * - * @param src: IPC interrupt source - * - * @return None - * -*******************************************************************************/ -void IPC_D0_Trigger_CPUx(GLB_CORE_ID_Type tgtCPU, IPC_Grp_Int_Src_Type src) -{ - switch (tgtCPU) { - case GLB_CORE_ID_M0: - IPC_D0_Trigger_M0(src); - break; - case GLB_CORE_ID_LP: - IPC_D0_Trigger_LP(src); - break; - default: - break; - } -} - -/****************************************************************************/ /** - * @brief D0 trigger IPC interrupt to D1 - * - * @param src: D0 IPC interrupt source - * - * @return None - * -*******************************************************************************/ -void IPC_Trigger_Target_CPU(GLB_CORE_ID_Type tgtCPU, IPC_Grp_Int_Src_Type src) -{ - GLB_CORE_ID_Type localCPU = GLB_Get_Core_Type(); - - switch (localCPU) { - case GLB_CORE_ID_M0: - IPC_M0_Trigger_CPUx(tgtCPU, src); - break; - case GLB_CORE_ID_LP: - IPC_LP_Trigger_CPUx(tgtCPU, src); - break; - case GLB_CORE_ID_D0: - IPC_D0_Trigger_CPUx(tgtCPU, src); - break; - default: - break; - } -} - -/****************************************************************************/ /** - * @brief D0 trigger IPC interrupt to D1 - * - * @param src: D0 IPC interrupt source - * - * @return None - * -*******************************************************************************/ -void IPC_Common_Interrupt_Handler(uint32_t irqStatus, ipcIntCallback *callBack[GLB_CORE_ID_MAX - 1]) -{ - uint32_t tmp; - uint32_t grp = 0; - - for (grp = 0; grp < GLB_CORE_ID_MAX - 1; grp++) { - tmp = (irqStatus >> (16 * grp)) & 0xffff; - if (tmp != 0) { - if (callBack[grp] != NULL) { - callBack[grp](tmp); - } - } - } -} - -/****************************************************************************/ /** - * @brief M0 IPC IRQ handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void IPC_M0_IRQHandler(void) -{ - uint32_t irqStatus; - irqStatus = IPC_M0_Get_Int_Raw_Status(); - IPC_Common_Interrupt_Handler(irqStatus, m0IpcIntCbfArra); - IPC_M0_Clear_Int_By_Word(irqStatus); -} -#endif - -/****************************************************************************/ /** - * @brief LP IPC IRQ handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void IPC_LP_IRQHandler(void) -{ - uint32_t irqStatus; - irqStatus = IPC_LP_Get_Int_Raw_Status(); - IPC_Common_Interrupt_Handler(irqStatus, lpIpcIntCbfArra); - IPC_LP_Clear_Int_By_Word(irqStatus); -} -#endif - -/****************************************************************************/ /** - * @brief D0 IPC IRQ handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void IPC_D0_IRQHandler(void) -{ - uint32_t irqStatus; - irqStatus = IPC_D0_Get_Int_Raw_Status(); - IPC_Common_Interrupt_Handler(irqStatus, d0IpcIntCbfArra); - IPC_D0_Clear_Int_By_Word(irqStatus); -} -#endif - -/*@} end of group IPC_Public_Functions */ - -/*@} end of group IPC */ - -/*@} end of group BL606P_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_ir.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_ir.c deleted file mode 100644 index 1fb74e6277..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_ir.c +++ /dev/null @@ -1,1269 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_ir.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_ir.h" -#include "bl808_glb.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup IR - * @{ - */ - -/** @defgroup IR_Private_Macros - * @{ - */ -#define NEC_HEAD_H_MIN 17000 -#define NEC_HEAD_H_MAX 19000 -#define NEC_HEAD_L_MIN 8400 -#define NEC_HEAD_L_MAX 9600 -#define NEC_BIT0_H_MIN 525 -#define NEC_BIT0_H_MAX 1725 -#define RC5_ONE_PLUSE_MIN 1175 -#define RC5_ONE_PLUSE_MAX 2375 -#define RC5_TWO_PLUSE_MIN 2955 -#define RC5_TWO_PLUSE_MAX 4155 -#define IR_TX_INT_TIMEOUT_COUNT (100 * 320 * 1000) -#define IR_RX_INT_TIMEOUT_COUNT (100 * 320 * 1000) -#define DIVIDE_ROUND(a, b) ((2 * a + b) / (2 * b)) - -/*@} end of group IR_Private_Macros */ - -/** @defgroup IR_Private_Types - * @{ - */ - -/*@} end of group IR_Private_Types */ - -/** @defgroup IR_Private_Variables - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -static intCallback_Type *irIntCbfArra[IR_INT_ALL] = { NULL }; -#endif - -/*@} end of group IR_Private_Variables */ - -/** @defgroup IR_Global_Variables - * @{ - */ - -/*@} end of group IR_Global_Variables */ - -/** @defgroup IR_Private_Fun_Declaration - * @{ - */ - -/*@} end of group IR_Private_Fun_Declaration */ - -/** @defgroup IR_Private_Functions - * @{ - */ - -/*@} end of group IR_Private_Functions */ - -/** @defgroup IR_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief IR RX IRQ handler function - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void IRRX_IRQHandler(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS); - - if (BL_IS_REG_BIT_SET(tmpVal, IRRX_END_INT) && !BL_IS_REG_BIT_SET(tmpVal, IR_CR_IRRX_END_MASK)) { - BL_WR_REG(IR_BASE, IRRX_INT_STS, BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_END_CLR)); - - if (irIntCbfArra[IR_INT_RX_END] != NULL) { - irIntCbfArra[IR_INT_RX_END](); - } - } - - if (BL_IS_REG_BIT_SET(tmpVal, IRRX_FRDY_INT) && !BL_IS_REG_BIT_SET(tmpVal, IR_CR_IRRX_FRDY_MASK)) { - if (irIntCbfArra[IR_INT_RX_FIFO_REQ] != NULL) { - irIntCbfArra[IR_INT_RX_FIFO_REQ](); - } - } - - if (BL_IS_REG_BIT_SET(tmpVal, IRRX_FER_INT) && !BL_IS_REG_BIT_SET(tmpVal, IR_CR_IRRX_FER_MASK)) { - if (irIntCbfArra[IR_INT_RX_FIFO_ERROR] != NULL) { - irIntCbfArra[IR_INT_RX_FIFO_ERROR](); - } - } -} -#endif - -/****************************************************************************/ /** - * @brief IR TX IRQ handler function - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void IRTX_IRQHandler(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(IR_BASE, IRTX_INT_STS); - - if (BL_IS_REG_BIT_SET(tmpVal, IRTX_END_INT) && !BL_IS_REG_BIT_SET(tmpVal, IR_CR_IRTX_END_MASK)) { - BL_WR_REG(IR_BASE, IRTX_INT_STS, BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_END_CLR)); - - if (irIntCbfArra[IR_INT_TX_END] != NULL) { - irIntCbfArra[IR_INT_TX_END](); - } - } - - if (BL_IS_REG_BIT_SET(tmpVal, IRTX_FRDY_INT) && !BL_IS_REG_BIT_SET(tmpVal, IR_CR_IRTX_FRDY_MASK)) { - if (irIntCbfArra[IR_INT_TX_FIFO_REQ] != NULL) { - irIntCbfArra[IR_INT_TX_FIFO_REQ](); - } - } - - if (BL_IS_REG_BIT_SET(tmpVal, IRTX_FER_INT) && !BL_IS_REG_BIT_SET(tmpVal, IR_CR_IRTX_FER_MASK)) { - if (irIntCbfArra[IR_INT_TX_FIFO_ERROR] != NULL) { - irIntCbfArra[IR_INT_TX_FIFO_ERROR](); - } - } -} -#endif - -/****************************************************************************/ /** - * @brief IR tx initialization function - * - * @param irTxCfg: IR tx configuration structure pointer - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type IR_TxInit(IR_TxCfg_Type *irTxCfg) -{ - uint32_t tmpVal; - - /* Disable clock gate */ - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_IR); - - tmpVal = BL_RD_REG(IR_BASE, IRTX_CONFIG); - /* Set data bit */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_DATA_NUM, irTxCfg->dataBits - 1); - /* Set tail pulse */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_TAIL_HL_INV, irTxCfg->tailPulseInverse); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_TAIL_EN, irTxCfg->tailPulse); - /* Set head pulse */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_HEAD_HL_INV, irTxCfg->headPulseInverse); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_HEAD_EN, irTxCfg->headPulse); - /* Enable or disable logic 1 and 0 pulse inverse */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_LOGIC1_HL_INV, irTxCfg->logic1PulseInverse); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_LOGIC0_HL_INV, irTxCfg->logic0PulseInverse); - /* Enable or disable data pulse */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_DATA_EN, irTxCfg->dataPulse); - /* Enable or disable output modulation */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_MOD_EN, irTxCfg->outputModulation); - /* Enable or disable output inverse */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_OUT_INV, irTxCfg->outputInverse); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_FRM_EN, irTxCfg->freerunEnable); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_FRM_CONT_EN, irTxCfg->continueEnable); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_FRM_FRAME_SIZE, irTxCfg->frameSize); - - /* Write back */ - BL_WR_REG(IR_BASE, IRTX_CONFIG, tmpVal); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(IRTX_IRQn, IRTX_IRQHandler); -#endif - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief IR tx pulse width configure function - * - * @param irTxPulseWidthCfg: IR tx pulse width configuration structure pointer - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type IR_TxPulseWidthConfig(IR_TxPulseWidthCfg_Type *irTxPulseWidthCfg) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(IR_BASE, IRTX_PW_0); - /* Set logic 0 pulse phase 0 width */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_LOGIC0_PH0_W, irTxPulseWidthCfg->logic0PulseWidth_0 - 1); - /* Set logic 0 pulse phase 1 width */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_LOGIC0_PH1_W, irTxPulseWidthCfg->logic0PulseWidth_1 - 1); - /* Set logic 1 pulse phase 0 width */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_LOGIC1_PH0_W, irTxPulseWidthCfg->logic1PulseWidth_0 - 1); - /* Set logic 1 pulse phase 1 width */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_LOGIC1_PH1_W, irTxPulseWidthCfg->logic1PulseWidth_1 - 1); - BL_WR_REG(IR_BASE, IRTX_PW_0, tmpVal); - - tmpVal = BL_RD_REG(IR_BASE, IRTX_PW_1); - /* Set head pulse phase 0 width */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_HEAD_PH0_W, irTxPulseWidthCfg->headPulseWidth_0 - 1); - /* Set head pulse phase 1 width */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_HEAD_PH1_W, irTxPulseWidthCfg->headPulseWidth_1 - 1); - /* Set tail pulse phase 0 width */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_TAIL_PH0_W, irTxPulseWidthCfg->tailPulseWidth_0 - 1); - /* Set tail pulse phase 1 width */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_TAIL_PH1_W, irTxPulseWidthCfg->tailPulseWidth_1 - 1); - BL_WR_REG(IR_BASE, IRTX_PW_1, tmpVal); - - tmpVal = BL_RD_REG(IR_BASE, IRTX_PULSE_WIDTH); - /* Set modulation phase 0 width */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_MOD_PH0_W, irTxPulseWidthCfg->moduWidth_0 - 1); - /* Set modulation phase 1 width */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_MOD_PH1_W, irTxPulseWidthCfg->moduWidth_1 - 1); - /* Set pulse width unit */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_PW_UNIT, irTxPulseWidthCfg->pulseWidthUnit - 1); - BL_WR_REG(IR_BASE, IRTX_PULSE_WIDTH, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief IR rx initialization function - * - * @param irRxCfg: IR rx configuration structure pointer - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type IR_RxInit(IR_RxCfg_Type *irRxCfg) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_IR_RXMODE_TYPE(irRxCfg->rxMode)); - - /* Disable clock gate */ - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_IR); - - tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG); - - /* Set rx mode */ - switch (irRxCfg->rxMode) { - case IR_RX_NEC: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE, 0x0); - break; - - case IR_RX_RC5: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE, 0x1); - break; - - case IR_RX_SWM: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE, 0x2); - break; - - default: - break; - } - - /* Enable or disable input inverse */ - ENABLE == irRxCfg->inputInverse ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_IN_INV)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRRX_IN_INV)); - /* Enable or disable rx input de-glitch function */ - ENABLE == irRxCfg->rxDeglitch ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_DEG_EN)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRRX_DEG_EN)); - /* Set de-glitch function cycle count */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_DEG_CNT, irRxCfg->DeglitchCnt); - /* Write back */ - BL_WR_REG(IR_BASE, IRRX_CONFIG, tmpVal); - - tmpVal = BL_RD_REG(IR_BASE, IRRX_PW_CONFIG); - /* Set pulse width threshold to trigger end condition */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_END_TH, irRxCfg->endThreshold - 1); - /* Set pulse width threshold for logic0/1 detection */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_DATA_TH, irRxCfg->dataThreshold - 1); - /* Write back */ - BL_WR_REG(IR_BASE, IRRX_PW_CONFIG, tmpVal); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(IRRX_IRQn, IRRX_IRQHandler); -#endif - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief IR configure fifo function - * - * @param fifoCfg: FIFO configuration structure pointer - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type IR_FifoConfig(IR_FifoCfg_Type *fifoCfg) -{ - uint32_t tmpVal; - - /* Set fifo threshold value */ - tmpVal = BL_RD_REG(IR_BASE, IRTX_FIFO_CONFIG_1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_TX_FIFO_TH, fifoCfg->txFifoThreshold); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_RX_FIFO_TH, fifoCfg->rxFifoThreshold); - BL_WR_REG(IR_BASE, IRTX_FIFO_CONFIG_1, tmpVal); - - /* Enable or disable dma function */ - tmpVal = BL_RD_REG(IR_BASE, IRTX_FIFO_CONFIG_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IRTX_DMA_EN, fifoCfg->txFifoDmaEnable); - BL_WR_REG(IR_BASE, IRTX_FIFO_CONFIG_0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief IR set default value of all registers function - * - * @param None - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type IR_DeInit(void) -{ - GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_IR_REMOTE); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief IR enable function - * - * @param direct: IR direction type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type IR_Enable(IR_Direction_Type direct) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_IR_DIRECTION_TYPE(direct)); - - if (direct == IR_TX || direct == IR_TXRX) { - /* Enable ir tx unit */ - tmpVal = BL_RD_REG(IR_BASE, IRTX_CONFIG); - BL_WR_REG(IR_BASE, IRTX_CONFIG, BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_EN)); - } - - if (direct == IR_RX || direct == IR_TXRX) { - /* Enable ir rx unit */ - tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG); - BL_WR_REG(IR_BASE, IRRX_CONFIG, BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_EN)); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief IR disable function - * - * @param direct: IR direction type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type IR_Disable(IR_Direction_Type direct) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_IR_DIRECTION_TYPE(direct)); - - if (direct == IR_TX || direct == IR_TXRX) { - /* Disable ir tx unit */ - tmpVal = BL_RD_REG(IR_BASE, IRTX_CONFIG); - BL_WR_REG(IR_BASE, IRTX_CONFIG, BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_EN)); - } - - if (direct == IR_RX || direct == IR_TXRX) { - /* Disable ir rx unit */ - tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG); - BL_WR_REG(IR_BASE, IRRX_CONFIG, BL_CLR_REG_BIT(tmpVal, IR_CR_IRRX_EN)); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief IR tx software mode enable or disable function - * - * @param txSWM: Enable or disable - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type IR_TxSWM(BL_Fun_Type txSWM) -{ - uint32_t tmpVal; - - /* Enable or disable tx swm */ - tmpVal = BL_RD_REG(IR_BASE, IRTX_CONFIG); - - if (ENABLE == txSWM) { - BL_WR_REG(IR_BASE, IRTX_CONFIG, BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_SWM_EN)); - } else { - BL_WR_REG(IR_BASE, IRTX_CONFIG, BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_SWM_EN)); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief IR clear rx fifo function - * - * @param None - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type IR_RxFifoClear(void) -{ - uint32_t tmpVal; - - /* Clear rx fifo */ - tmpVal = BL_RD_REG(IR_BASE, IRTX_FIFO_CONFIG_0); - BL_WR_REG(IR_BASE, IRTX_FIFO_CONFIG_0, BL_SET_REG_BIT(tmpVal, IR_RX_FIFO_CLR)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief IR clear tx fifo function - * - * @param None - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type IR_TxFifoClear(void) -{ - uint32_t tmpVal; - - /* Clear rx fifo */ - tmpVal = BL_RD_REG(IR_BASE, IRTX_FIFO_CONFIG_0); - BL_WR_REG(IR_BASE, IRTX_FIFO_CONFIG_0, BL_SET_REG_BIT(tmpVal, IR_TX_FIFO_CLR)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief IR send data function - * - * @param data: data to send - * @param length: Length of send buffer - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type IR_SendData(uint32_t *data, uint8_t length) -{ - uint32_t txLen = 0; - uint32_t timeoutCnt = IR_TX_INT_TIMEOUT_COUNT; - - while (txLen < length) { - if (IR_GetTxFifoCount() > 0) { - BL_WR_REG(IR_BASE, IR_FIFO_WDATA, data[txLen++]); - timeoutCnt = IR_TX_INT_TIMEOUT_COUNT; - } else { - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief IR software mode send pulse width data function - * - * @param data: data to send - * @param length: Length of send buffer - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type IR_SWMSendData(uint16_t *data, uint8_t length) -{ - uint8_t i = 0, j = 0; - uint16_t minData = data[0]; - uint32_t tmpVal; - uint32_t count = (length + 3) / 4; - uint32_t pwVal = 0; - - /* Search for min value */ - for (i = 1; i < length; i++) { - if (minData > data[i] && data[i] != 0) { - minData = data[i]; - } - } - - /* Set min value as pulse width unit */ - tmpVal = BL_RD_REG(IR_BASE, IRTX_PULSE_WIDTH); - BL_WR_REG(IR_BASE, IRTX_PULSE_WIDTH, BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_PW_UNIT, minData)); - - /* Calculate tx SWM pulse width data as multiples of pulse width unit */ - for (i = 0; i < count; i++) { - pwVal = 0; - - if (i < count - 1) { - /* Put every four pulse width together as a 32-bit value to tx fifo */ - for (j = 0; j < 4; j++) { - /* Every pulse width divided by pulse width unit */ - tmpVal = (DIVIDE_ROUND(data[j + i * 4], minData) - 1) & 0xff; - /* Tx fifo 32-bit value: pwVal[7:0]:first pulse width, pwVal[15:8]:second pulse width... */ - pwVal |= tmpVal << (8 * j); - } - } else { - /* Deal with pulse width data remained which is less than 4 */ - for (j = 0; j < length % 4; j++) { - tmpVal = (DIVIDE_ROUND(data[j + i * 4], minData) - 1) & 0xff; - pwVal |= tmpVal << (8 * j); - } - } - - /* Write to tx fifo */ - IR_SendData(&pwVal, 1); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief IR send command function - * - * @param data: data to send - * @param length: Length of send buffer - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type IR_SendCommand(uint32_t *data, uint8_t length) -{ - uint32_t timeoutCnt = IR_TX_INT_TIMEOUT_COUNT; - - /* Write data */ - IR_SendData(data, length); - - /* Mask tx interrupt */ - IR_IntMask(IR_INT_TX_END, MASK); - - /* Clear tx interrupt */ - IR_ClrIntStatus(IR_INT_TX_END); - - /* Enable ir tx */ - IR_Enable(IR_TX); - - /* Wait for tx interrupt */ - while (SET != IR_GetIntStatus(IR_INT_TX_END)) { - timeoutCnt--; - - if (timeoutCnt == 0) { - IR_Disable(IR_TX); - - return TIMEOUT; - } - } - - /* Disable ir tx */ - IR_Disable(IR_TX); - - /* Clear tx interrupt */ - IR_ClrIntStatus(IR_INT_TX_END); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief IR send command in software mode function - * - * @param data: IR fifo data to send - * @param length: Length of data - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type IR_SWMSendCommand(uint16_t *data, uint8_t length) -{ - uint32_t timeoutCnt = IR_TX_INT_TIMEOUT_COUNT; - - /* Mask tx interrupt */ - IR_IntMask(IR_INT_TX_END, MASK); - - /* Clear tx interrupt */ - IR_ClrIntStatus(IR_INT_TX_END); - - /* Enable ir tx */ - IR_Enable(IR_TX); - - /* Write fifo */ - IR_SWMSendData(data, length); - - /* Wait for tx interrupt */ - while (SET != IR_GetIntStatus(IR_INT_TX_END)) { - timeoutCnt--; - - if (timeoutCnt == 0) { - IR_Disable(IR_TX); - - return TIMEOUT; - } - } - - /* Disable ir tx */ - IR_Disable(IR_TX); - - /* Clear tx interrupt */ - IR_ClrIntStatus(IR_INT_TX_END); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief IR send in NEC protocol - * - * @param address: Address - * @param command: Command - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type IR_SendNEC(uint8_t address, uint8_t command) -{ - uint32_t tmpVal = ((~command & 0xff) << 24) + (command << 16) + ((~address & 0xff) << 8) + address; - - IR_SendCommand(&tmpVal, 1); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief IR interrupt mask or unmask function - * - * @param intType: IR interrupt type - * @param intMask: Mask or unmask - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type IR_IntMask(IR_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_IR_INT_TYPE(intType)); - - if (intType < 3) { - /* Mask or unmask tx interrupt */ - tmpVal = BL_RD_REG(IR_BASE, IRTX_INT_STS); - - if (MASK == intMask) { - tmpVal |= 1 << (intType + 8); - } else { - tmpVal &= ~(1 << (intType + 8)); - } - - BL_WR_REG(IR_BASE, IRTX_INT_STS, tmpVal); - } else if (intType < 6) { - /* Mask or unmask rx interrupt */ - tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS); - - if (MASK == intMask) { - tmpVal |= 1 << (intType + 5); - } else { - tmpVal &= ~(1 << (intType + 5)); - } - - BL_WR_REG(IR_BASE, IRRX_INT_STS, tmpVal); - } else { - if (MASK == intMask) { - tmpVal = BL_RD_REG(IR_BASE, IRTX_INT_STS); - tmpVal |= 0x700; - tmpVal = BL_RD_REG(IR_BASE, IRTX_INT_STS); - tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS); - tmpVal |= 0x700; - tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS); - } else { - tmpVal = BL_RD_REG(IR_BASE, IRTX_INT_STS); - tmpVal &= ~0x700; - tmpVal = BL_RD_REG(IR_BASE, IRTX_INT_STS); - tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS); - tmpVal &= ~0x700; - tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS); - } - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Clear ir interrupt function - * - * @param intType: IR interrupt type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type IR_ClrIntStatus(IR_INT_Type intType) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_IR_INT_TYPE(intType)); - - if (intType == IR_INT_TX_END || intType == IR_INT_ALL) { - /* Clear tx interrupt */ - tmpVal = BL_RD_REG(IR_BASE, IRTX_INT_STS); - BL_WR_REG(IR_BASE, IRTX_INT_STS, BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_END_CLR)); - } - - if (intType == IR_INT_RX_END || intType == IR_INT_ALL) { - /* Clear rx interrupt */ - tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS); - BL_WR_REG(IR_BASE, IRRX_INT_STS, BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_END_CLR)); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief IR install interrupt callback function - * - * @param intType: IR interrupt type - * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) - * - * @return SUCCESS - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -BL_Err_Type IR_Int_Callback_Install(IR_INT_Type intType, intCallback_Type *cbFun) -{ - /* Check the parameters */ - CHECK_PARAM(IS_IR_INT_TYPE(intType)); - - irIntCbfArra[intType] = cbFun; - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief IR get interrupt status function - * - * @param intType: IR int type - * - * @return IR tx or rx interrupt status - * -*******************************************************************************/ -BL_Sts_Type IR_GetIntStatus(IR_INT_Type intType) -{ - uint32_t tmpVal = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_IR_INT_TYPE(intType)); - - /* Read tx or rx interrupt status */ - if (intType < 3) { - tmpVal = BL_RD_REG(IR_BASE, IRTX_INT_STS); - tmpVal &= 1 << intType; - } else if (intType < 6) { - tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS); - tmpVal &= 1 << (intType - 3); - } else { - } - - if (tmpVal) { - return SET; - } else { - return RESET; - } -} - -/****************************************************************************/ /** - * @brief IR get tx/rx fifo underflow or overflow status function - * - * @param fifoSts: IR fifo status type - * - * @return IR fifo status - * -*******************************************************************************/ -BL_Sts_Type IR_GetFifoStatus(IR_FifoStatus_Type fifoSts) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_IR_FIFOSTATUS_TYPE(fifoSts)); - - /* Read rx fifo status */ - tmpVal = BL_RD_REG(IR_BASE, IRTX_FIFO_CONFIG_0); - - if ((tmpVal & (1U << (fifoSts + IR_TX_FIFO_OVERFLOW_POS))) != 0) { - return SET; - } else { - return RESET; - } -} - -/****************************************************************************/ /** - * @brief IR receive data function - * - * @param irWord: IR rx data word 0 or 1 - * - * @return Data received - * -*******************************************************************************/ -uint32_t IR_ReceiveData(IR_Word_Type irWord) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_IR_WORD_TYPE(irWord)); - - /* Read word 0 or word 1 */ - if (IR_WORD_0 == irWord) { - tmpVal = BL_RD_REG(IR_BASE, IRRX_DATA_WORD0); - } else { - tmpVal = BL_RD_REG(IR_BASE, IRRX_DATA_WORD1); - } - - return tmpVal; -} - -/****************************************************************************/ /** - * @brief IR software mode receive pulse width data function - * - * @param data: Data received - * @param length: Max length of receive buffer - * - * @return Length of datas received - * -*******************************************************************************/ -uint8_t IR_SWMReceiveData(uint16_t *data, uint8_t length) -{ - uint8_t rxLen = 0; - - while (rxLen < length && IR_GetRxFifoCount() > 0) { - /* Read data */ - data[rxLen++] = BL_RD_REG(IR_BASE, IR_FIFO_RDATA) & 0xffff; - } - - return rxLen; -} - -/****************************************************************************/ /** - * @brief IR receive in NEC protocol - * - * @param address: Address - * @param command: Command - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type IR_ReceiveNEC(uint8_t *address, uint8_t *command) -{ - uint32_t tmpVal = IR_ReceiveData(IR_WORD_0); - - *address = tmpVal & 0xff; - *command = (tmpVal >> 16) & 0xff; - - if ((~(*address) & 0xff) != ((tmpVal >> 8) & 0xff) || (~(*command) & 0xff) != ((tmpVal >> 24) & 0xff)) { - return ERROR; - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief IR get rx data bit count function - * - * @param None - * - * @return IR rx data bit count - * -*******************************************************************************/ -uint8_t IR_GetRxDataBitCount(void) -{ - uint32_t tmpVal; - - /* Read rx data bit count */ - tmpVal = BL_RD_REG(IR_BASE, IRRX_DATA_COUNT); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, IR_STS_IRRX_DATA_CNT); - - return tmpVal; -} - -/****************************************************************************/ /** - * @brief IR get rx fifo count function - * - * @param None - * - * @return IR rx fifo available count - * -*******************************************************************************/ -uint8_t IR_GetRxFifoCount(void) -{ - uint32_t tmpVal; - - /* Read rx fifo count */ - tmpVal = BL_RD_REG(IR_BASE, IRTX_FIFO_CONFIG_1); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, IR_RX_FIFO_CNT); - - return tmpVal; -} - -/****************************************************************************/ /** - * @brief IR get tx fifo count function - * - * @param None - * - * @return IR tx fifo available count - * -*******************************************************************************/ -uint8_t IR_GetTxFifoCount(void) -{ - uint32_t tmpVal; - - /* Read tx fifo count */ - tmpVal = BL_RD_REG(IR_BASE, IRTX_FIFO_CONFIG_1); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, IR_TX_FIFO_CNT); - - return tmpVal; -} - -/****************************************************************************/ /** - * @brief IR learning to set rx and tx mode function - * - * @param data: Buffer to save data - * @param length: Length of data - * - * @return Protocol type - * -*******************************************************************************/ -IR_RxMode_Type IR_LearnToInit(uint32_t *data, uint8_t *length) -{ - uint32_t tmpVal; - uint32_t timeoutCnt = IR_RX_INT_TIMEOUT_COUNT; - - /* Disable clock gate */ - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_IR); - - /* Disable rx,set rx in software mode and enable rx input inverse */ - tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRRX_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE, 0x2); - tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_IN_INV); - BL_WR_REG(IR_BASE, IRRX_CONFIG, tmpVal); - /* Set pulse width threshold to trigger end condition */ - tmpVal = BL_RD_REG(IR_BASE, IRRX_PW_CONFIG); - BL_WR_REG(IR_BASE, IRRX_PW_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_END_TH, 19999)); - - /* Clear and mask rx interrupt */ - tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS); - tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_END_MASK); - BL_WR_REG(IR_BASE, IRRX_INT_STS, BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_END_CLR)); - - /* Enable rx */ - tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG); - BL_WR_REG(IR_BASE, IRRX_CONFIG, BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_EN)); - - /* Wait for rx interrupt */ - while (SET != IR_GetIntStatus(IR_INT_RX_END)) { - timeoutCnt--; - - if (timeoutCnt == 0) { - IR_Disable(IR_RX); - - return IR_RX_SWM; - } - } - - /* Disable rx */ - tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG); - BL_WR_REG(IR_BASE, IRRX_CONFIG, BL_CLR_REG_BIT(tmpVal, IR_CR_IRRX_EN)); - - /* Clear rx interrupt */ - tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS); - BL_WR_REG(IR_BASE, IRRX_INT_STS, BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_END_CLR)); - - /*Receive data */ - *length = IR_GetRxFifoCount(); - *length = IR_SWMReceiveData((uint16_t *)data, *length); - - /* Judge protocol type */ - if (NEC_HEAD_H_MIN < (data[0] & 0xffff) && (data[0] & 0xffff) < NEC_HEAD_H_MAX && NEC_HEAD_L_MIN < (data[0] >> 16) && (data[0] >> 16) < NEC_HEAD_L_MAX && NEC_BIT0_H_MIN < (data[1] & 0xffff) && (data[1] & 0xffff) < NEC_BIT0_H_MAX) { - /* Set rx in NEC mode */ - tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG); - BL_WR_REG(IR_BASE, IRRX_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE, 0x0)); - /* Set pulse width threshold to trigger end condition and pulse width threshold for logic0/1 detection */ - BL_WR_REG(IR_BASE, IRRX_PW_CONFIG, 0x23270d47); - /* Set tx in NEC mode */ - /* Tx configure */ - BL_WR_REG(IR_BASE, IRTX_CONFIG, 0x1fc514); - /* Set logic 0,logic 1,head and tail pulse width */ - BL_WR_REG(IR_BASE, IRTX_PW_0, 0x02000000); - BL_WR_REG(IR_BASE, IRTX_PW_1, 0x0000070f); - /* Set modulation phase width and pulse width unit */ - BL_WR_REG(IR_BASE, IRTX_PULSE_WIDTH, 0x22110464); - - return IR_RX_NEC; - } else if (RC5_ONE_PLUSE_MIN < (data[0] & 0xffff) && (data[0] & 0xffff) < RC5_ONE_PLUSE_MAX && ((RC5_ONE_PLUSE_MIN < (data[0] >> 16) && (data[0] >> 16) < RC5_ONE_PLUSE_MAX) || (RC5_TWO_PLUSE_MIN < (data[0] >> 16) && (data[0] >> 16) < RC5_TWO_PLUSE_MAX)) && - ((RC5_ONE_PLUSE_MIN < (data[1] & 0xffff) && (data[1] & 0xffff) < RC5_ONE_PLUSE_MAX) || (RC5_TWO_PLUSE_MIN < (data[1] & 0xffff) && (data[1] & 0xffff) < RC5_TWO_PLUSE_MAX))) { - /* Set rx in RC-5 mode */ - tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG); - BL_WR_REG(IR_BASE, IRRX_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE, 0x1)); - /* Set pulse width threshold to trigger end condition and pulse width threshold for logic0/1 detection */ - BL_WR_REG(IR_BASE, IRRX_PW_CONFIG, 0x13870a6a); - /* Set tx in RC-5 mode */ - /* Tx configure */ - BL_WR_REG(IR_BASE, IRTX_CONFIG, 0xcc134); - /* Set logic 0,logic 1,head and tail pulse width */ - BL_WR_REG(IR_BASE, IRTX_PW_0, 0); - BL_WR_REG(IR_BASE, IRTX_PW_1, 0); - /* Set modulation phase width and pulse width unit */ - BL_WR_REG(IR_BASE, IRTX_PULSE_WIDTH, 0x221106f1); - - return IR_RX_RC5; - } else if ((data[0] >> 16) != 0) { - /* Set tx in software mode */ - /* Tx configure */ - BL_WR_REG(IR_BASE, IRTX_CONFIG, *length << 16 | 0xc); - /* Set modulation phase width */ - BL_WR_REG(IR_BASE, IRTX_PULSE_WIDTH, 0x22110000); - - return IR_RX_SWM; - } else { - tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE); - - if (tmpVal == 0) { - return IR_RX_NEC; - } else if (tmpVal == 1) { - return IR_RX_RC5; - } else { - return IR_RX_SWM; - } - } -} - -/****************************************************************************/ /** - * @brief IR receive data according to mode which is learned function - * - * @param mode: Protocol type - * @param data: Buffer to save data - * - * @return Length of data - * -*******************************************************************************/ -uint8_t IR_LearnToReceive(IR_RxMode_Type mode, uint32_t *data) -{ - uint8_t length = 0; - uint32_t timeoutCnt = IR_RX_INT_TIMEOUT_COUNT; - - /* Check the parameters */ - CHECK_PARAM(IS_IR_RXMODE_TYPE(mode)); - - /* Disable ir rx */ - IR_Disable(IR_RX); - - /* Clear and mask rx interrupt */ - IR_ClrIntStatus(IR_INT_RX_END); - IR_IntMask(IR_INT_RX_END, MASK); - - /* Enable ir rx */ - IR_Enable(IR_RX); - - /* Wait for rx interrupt */ - while (SET != IR_GetIntStatus(IR_INT_RX_END)) { - timeoutCnt--; - - if (timeoutCnt == 0) { - IR_Disable(IR_RX); - - return TIMEOUT; - } - } - - /* Disable ir rx */ - IR_Disable(IR_RX); - - /* Clear rx interrupt */ - IR_ClrIntStatus(IR_INT_RX_END); - - /* Receive data according to mode */ - if (mode == IR_RX_NEC || mode == IR_RX_RC5) { - /* Get data bit count */ - length = IR_GetRxDataBitCount(); - data[0] = IR_ReceiveData(IR_WORD_0); - } else { - /* Get fifo count */ - length = IR_GetRxFifoCount(); - length = IR_SWMReceiveData((uint16_t *)data, length); - } - - return length; -} - -/****************************************************************************/ /** - * @brief IR send data according to mode which is learned function - * - * @param mode: Protocol type - * @param data: Buffer of data to send - * @param length: Length of data - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type IR_LearnToSend(IR_RxMode_Type mode, uint32_t *data, uint8_t length) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_IR_RXMODE_TYPE(mode)); - - /* Set send length */ - tmpVal = BL_RD_REG(IR_BASE, IRTX_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_DATA_NUM, length - 1); - BL_WR_REG(IR_BASE, IRTX_CONFIG, tmpVal); - - if (mode == IR_RX_NEC || mode == IR_RX_RC5) { - IR_SendCommand(data, 1); - } else { - IR_SWMSendCommand((uint16_t *)data, length); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief IR init to control led function - * - * @param clk: Clock source - * @param div: Clock division(1~64) - * @param unit: Pulse width unit(multiples of clock pulse width, 1~4096) - * @param code0H: code 0 high level time(multiples of pulse width unit, 1~16) - * @param code0L: code 0 low level time(multiples of pulse width unit, 1~16) - * @param code1H: code 1 high level time(multiples of pulse width unit, 1~16) - * @param code1L: code 1 low level time(multiples of pulse width unit, 1~16) - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type IR_LEDInit(HBN_MCU_XCLK_Type clk, uint8_t div, uint8_t unit, uint8_t code0H, uint8_t code0L, uint8_t code1H, uint8_t code1L) -{ - IR_TxCfg_Type txCfg = { - 24, /* 24-bit data */ - DISABLE, /* Disable signal of tail pulse inverse */ - DISABLE, /* Disable signal of tail pulse */ - DISABLE, /* Disable signal of head pulse inverse */ - DISABLE, /* Disable signal of head pulse */ - DISABLE, /* Disable signal of logic 1 pulse inverse */ - DISABLE, /* Disable signal of logic 0 pulse inverse */ - ENABLE, /* Enable signal of data pulse */ - DISABLE, /* Disable signal of output modulation */ - ENABLE, /* Enable signal of output inverse */ - DISABLE, /* Disable tx freerun mode */ - DISABLE, /* Disable tx freerun continuous mode */ - IR_FRAME_SIZE_32 /* Frame size */ - }; - - IR_TxPulseWidthCfg_Type txPWCfg = { - code0L, /* Pulse width of logic 0 pulse phase 1 */ - code0H, /* Pulse width of logic 0 pulse phase 0 */ - code1L, /* Pulse width of logic 1 pulse phase 1 */ - code1H, /* Pulse width of logic 1 pulse phase 0 */ - 1, /* Pulse width of head pulse phase 1 */ - 1, /* Pulse width of head pulse phase 0 */ - 1, /* Pulse width of tail pulse phase 1 */ - 1, /* Pulse width of tail pulse phase 0 */ - 1, /* Modulation phase 1 width */ - 1, /* Modulation phase 0 width */ - unit /* Pulse width unit */ - }; - - HBN_Set_MCU_XCLK_Sel(clk); - GLB_Set_IR_CLK(ENABLE, GLB_IR_CLK_SRC_XCLK, div - 1); - - /* Disable ir before config */ - IR_Disable(IR_TXRX); - - /* IR tx init */ - IR_TxInit(&txCfg); - IR_TxPulseWidthConfig(&txPWCfg); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief IR send 24-bit data to control led function - * - * @param data: Data to send(24-bit) - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type IR_LEDSend(uint32_t data) -{ - /* Change MSB_first to LSB_first */ - data = ((data >> 1) & 0x55555555) | ((data << 1) & 0xaaaaaaaa); - data = ((data >> 2) & 0x33333333) | ((data << 2) & 0xcccccccc); - data = ((data >> 4) & 0x0f0f0f0f) | ((data << 4) & 0xf0f0f0f0); - data = ((data >> 16) & 0xff) | (data & 0xff00) | ((data << 16) & 0xff0000); - IR_SendCommand(&data, 1); - - return SUCCESS; -} - -/*@} end of group IR_Public_Functions */ - -/*@} end of group IR */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_iso11898.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_iso11898.c deleted file mode 100644 index 23fcb419b1..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_iso11898.c +++ /dev/null @@ -1,671 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_iso11898.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_glb.h" -#include "bl808_iso11898.h" -#include "bflb_platform.h" - -#ifndef BFLB_USE_HAL_DRIVER -static intCallback_Type * iso11898IntCbfArra[ISO11898_INT_ALL] = { NULL }; -static void ISO11898_IntHandler(void); -static void ISO11898_IRQHandler(void); -#endif - -void ISO11898_Init(void) -{ - uint32_t tmpVal; - - /* Enable ISO11898 clock witch share with UART2 */ - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_UART2); - - /* Enable UART clock*/ - tmpVal=BL_RD_REG(GLB_BASE,GLB_UART_CFG0); - tmpVal=BL_SET_REG_BIT(tmpVal,GLB_UART_CLK_EN); - BL_WR_REG(GLB_BASE,GLB_UART_CFG0,tmpVal); - - /* UART2 and ISO11898 can not work together */ - GLB_Set_UART2_IO_Sel(GLB_UART2_IO_SEL_ISO11898); - - /* Need to enter reset mode before operating */ - ISO11898_Mode_Set(ISO11898_MODE_TYPE_RESET, ISO11898_MODE_VALUE_RESET); - - /* Force using Peli not Basic ISO11898 */ - tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_CLOCK_DIVIDER); - tmpVal = BL_SET_REG_BIT(tmpVal, ISO11898_MODE); - BL_WR_REG(ISO11898_BASE, ISO11898_CLOCK_DIVIDER, tmpVal); - - /* Disable all interrupts */ - BL_WR_REG(ISO11898_BASE, ISO11898_INTERRUPT_ENABLE, 0); - - /* Set clock and sample point */ - ISO11898_Clock_Div_Set(0); - ISO11898_Synchronization_Jump_Width_Set(3); - ISO11898_Sample_Parameter_Set(1, 8, 5); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(UART2_IRQn, ISO11898_IRQHandler); -#endif -} - -void ISO11898_Mode_Set(ISO11898_MODE_Type type, ISO11898_MODE_VALUE_Type value) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_ISO11898_MODE_TYPE(type)); - CHECK_PARAM(IS_ISO11898_MODE_VALUE_TYPE(value)); - - /* Set mode value */ - tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_MODE); - tmpVal &= ~(1 << type); - tmpVal |= (value << type); - - /* Write back */ - BL_WR_REG(ISO11898_BASE, ISO11898_MODE, tmpVal); -} - -ISO11898_MODE_VALUE_Type ISO11898_Mode_Get(ISO11898_MODE_Type type) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_ISO11898_MODE_TYPE(type)); - - tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_MODE); - tmpVal &= (1 << type); - tmpVal >>= type; - return (ISO11898_MODE_VALUE_Type)tmpVal; -} - -void ISO11898_Int_Enable(ISO11898_INT_Type intType, BL_Fun_Type enable) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_ISO11898_INT_TYPE(intType)); - - tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_INTERRUPT_ENABLE); - /* Enable or Disable certain or all interrupt */ - if(ISO11898_INT_ALL == intType){ - if(ENABLE == enable){ - tmpVal |= 0xFF; - }else{ - tmpVal &= 0; - } - }else{ - if(ENABLE == enable){ - tmpVal |= 1<>= type; - return (ISO11898_STATUS_VALUE_Type)tmpVal; -} - -uint8_t ISO11898_Arbitration_Lost_Position_Get(void) -{ - uint8_t tmpVal; - - tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_ARB_LOST_CAPTURE); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, ISO11898_ALC4_0); - return tmpVal; -} - -void ISO11898_Error_Get(ISO11898_ERROR_Type *const type) -{ - uint8_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_ISO11898_FRAME_FORMAT_TYPE(type)); - - tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_ERROR_CODE_CAPTURE); - type->code = BL_GET_REG_BITS_VAL(tmpVal, ISO11898_ERR_CODE); - type->dir = BL_GET_REG_BITS_VAL(tmpVal, ISO11898_DIR); - type->location = BL_GET_REG_BITS_VAL(tmpVal, ISO11898_SEGMENT4_0); -} - -BL_Err_Type ISO11898_Error_Warning_Limit_Set(uint8_t limit) -{ - if(ISO11898_MODE_VALUE_NORMAL == ISO11898_Mode_Get(ISO11898_MODE_TYPE_RESET)) - { - return ERROR; - } - BL_WR_REG(ISO11898_BASE, ISO11898_ERROR_WARNING_LIMIT, limit); - return SUCCESS; -} - -uint8_t ISO11898_Error_Warning_Limit_Get(void) -{ - return BL_RD_REG(ISO11898_BASE, ISO11898_ERROR_WARNING_LIMIT); -} - -uint8_t ISO11898_Error_Rx_Counter_Get(void) -{ - return BL_RD_REG(ISO11898_BASE, ISO11898_RX_ERR_COUNT); -} - -uint8_t ISO11898_Error_Tx_Counter_Get(void) -{ - return BL_RD_REG(ISO11898_BASE, ISO11898_TX_ERR_COUNT); -} - -BL_Err_Type ISO11898_Transmit(const ISO11898_CFG_Type *cfg) -{ - uint32_t timeOut; - uint32_t tmpVal; - uint32_t i; - volatile uint32_t *pData; - - /* Check the parameters */ - CHECK_PARAM(IS_ISO11898_FRAME_FORMAT_TYPE(cfg->dataAddr)); - CHECK_PARAM(IS_ISO11898_FRAME_TYPE(cfg->frameType)); - CHECK_PARAM(IS_ISO11898_FRAME_FORMAT_TYPE(cfg->frameFormat)); - - timeOut = cfg->timeout; - - /* Chcek Timeout type */ - while(ISO11898_STATUS_TRANSMIT_BUFFER_LOCKED == ISO11898_Status_Get(ISO11898_STATUS_TRANSMIT_BUFFER)) - { - /* Wait no time */ - if (cfg->timeout == 0) - { - return TIMEOUT; - } - /* Wait until transmit buffer accessible */ - if (cfg->timeout >= ISO11898_TIMEOUT_MAX) - { - - } - /* Wait time = cfg->timeOut */ - else - { - if(timeOut == 0) - { - return TIMEOUT; - } - timeOut--; - } - } - - /* Config information register */ - tmpVal = cfg->dataLen; - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, ISO11898_INF_FF, cfg->frameFormat); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, ISO11898_INF_RTR, cfg->frameType); - BL_WR_REG(ISO11898_BASE, ISO11898_INFORMATION, tmpVal); - - tmpVal = cfg->id; - /* Transmit format with 11 bits ID, SFF */ - if(ISO11898_FRAME_FORMAT_STANDARD == cfg->frameFormat) - { - /* Config identifier registers */ - BL_WR_REG(ISO11898_BASE, ISO11898_IDENTIFIER_1, (tmpVal >> 3) & 0xFF); - tmpVal <<= 5; - tmpVal |= (cfg->frameType << 4); - BL_WR_REG(ISO11898_BASE, ISO11898_IDENTIFIER_2, tmpVal & 0xFF); - /* Config SFF data registers start address */ - pData = (uint32_t *)(ISO11898_BASE + ISO11898_SFF_DATA_1_OFFSET); - } - /* Transmit format with 29 bits ID, EFF */ - else - { - /* Config identifier registers */ - BL_WR_REG(ISO11898_BASE, ISO11898_IDENTIFIER_1, (tmpVal >> 21) & 0xFF); - BL_WR_REG(ISO11898_BASE, ISO11898_IDENTIFIER_2, (tmpVal >> 13) & 0xFF); - BL_WR_REG(ISO11898_BASE, ISO11898_IDENTIFIER_3, (tmpVal >> 5) & 0xFF); - tmpVal <<= 3; - tmpVal |= (cfg->frameType << 2); - BL_WR_REG(ISO11898_BASE, ISO11898_IDENTIFIER_4, tmpVal & 0xFF); - /* Config EFF data registers start address */ - pData = (uint32_t *)(ISO11898_BASE + ISO11898_EFF_DATA_1_OFFSET); - } - /* Move data from user buff to registers */ - for (i = 0; i < cfg->dataLen; i++) - { - *(pData + i) = (uint32_t)(*(cfg->dataAddr + i)); - } - - /* Trig a request for transmit */ - if(ISO11898_MODE_VALUE_RESET == ISO11898_Mode_Get(ISO11898_MODE_TYPE_RESET)) - { - return ERROR; - } - else if(ISO11898_MODE_VALUE_LISTEN_ONLY == ISO11898_Mode_Get(ISO11898_MODE_TYPE_LISTEN_ONLY)) - { - return ERROR; - } - else if(ISO11898_MODE_VALUE_SELF_TSET == ISO11898_Mode_Get(ISO11898_MODE_TYPE_SELF_TSET)) - { - ISO11898_Cmd_Request_Self_Reception(); - } - else - { - ISO11898_Cmd_Request_Transmit(); - } - - return SUCCESS; -} - -BL_Err_Type ISO11898_Receive(ISO11898_CFG_Type *cfg) -{ - uint32_t timeOut; - uint32_t tmpVal; - uint32_t i; - uint32_t id; - volatile uint32_t *pData; - - /* Check the parameters */ - CHECK_PARAM(IS_ISO11898_FRAME_FORMAT_TYPE(cfg->dataAddr)); - - timeOut = cfg->timeout; - - /* Chcek Timeout type */ - while(ISO11898_STATUS_RECEIVE_BUFFER_EMPTY == ISO11898_Status_Get(ISO11898_STATUS_RECEIVE_BUFFER)) - { - /* Wait no time */ - if (cfg->timeout == 0) - { - return TIMEOUT; - } - /* Wait until transmit buffer accessible */ - if (cfg->timeout >= ISO11898_TIMEOUT_MAX) - { - - } - /* Wait time = cfg->timeOut */ - else - { - if(timeOut == 0) - { - return TIMEOUT; - } - timeOut--; - } - } - - /* Read information register */ - tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_INFORMATION); - cfg->frameFormat = BL_GET_REG_BITS_VAL(tmpVal, ISO11898_INF_FF); - cfg->frameType = BL_GET_REG_BITS_VAL(tmpVal, ISO11898_INF_RTR); - cfg->dataLen = BL_GET_REG_BITS_VAL(tmpVal, ISO11898_INF_DLC); - - /* Receive with 11 bits ID */ - if(ISO11898_FRAME_FORMAT_STANDARD == cfg->frameFormat) - { - /* Read identifier registers */ - tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_IDENTIFIER_1); - id = ((tmpVal & 0xFF) << 3); - tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_IDENTIFIER_2); - id |= (tmpVal & 0xFF) >> 5; - /* Config SFF data registers start address */ - pData = (uint32_t *)(ISO11898_BASE + ISO11898_SFF_DATA_1_OFFSET); - } - /* Receive with 29 bits ID */ - else - { - /* Read identifier registers */ - tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_IDENTIFIER_1); - id = ((tmpVal & 0xFF) << 21); - tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_IDENTIFIER_2); - id |= (tmpVal & 0xFF) << 13; - tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_IDENTIFIER_3); - id |= (tmpVal & 0xFF) << 5; - tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_IDENTIFIER_4); - id |= (tmpVal & 0xFF) >> 3; - /* Config EFF data registers start address */ - pData = (uint32_t *)(ISO11898_BASE + ISO11898_EFF_DATA_1_OFFSET); - } - cfg->id = id; - - /* Move data from registers to user buff */ - for (i = 0; i < cfg->dataLen; i++) - { - *(cfg->dataAddr + i) = (uint8_t)(*(pData + i) & 0xFF); - } - - ISO11898_Cmd_Release_Recv_Buff(); - - return SUCCESS; -} - -uint8_t ISO11898_Receive_Buff_Frame_Count_Get(void) -{ - volatile uint32_t tmpVal; - - tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_RX_MESSAGE_COUNT); - return (uint8_t)(tmpVal & 0xFF); -} - -BL_Err_Type ISO11898_Clock_Div_Set(uint8_t div) -{ - uint32_t tmpVal; - - /* Must be operated in reset mode */ - if (ISO11898_MODE_VALUE_NORMAL == ISO11898_Mode_Get(ISO11898_MODE_TYPE_RESET)) - { - return ERROR; - } - - tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_BUS_TIMING_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, ISO11898_BAUD_RATE_PRESCALER, div); - BL_WR_REG(ISO11898_BASE, ISO11898_BUS_TIMING_0, tmpVal); - - return SUCCESS; -} - -uint8_t ISO11898_Clock_Div_Get(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_BUS_TIMING_0); - return (uint8_t)BL_GET_REG_BITS_VAL(tmpVal, ISO11898_BAUD_RATE_PRESCALER); -} - -BL_Err_Type ISO11898_Synchronization_Jump_Width_Set(uint8_t width) -{ - uint32_t tmpVal; - - /* Must be operated in reset mode */ - if (ISO11898_MODE_VALUE_NORMAL == ISO11898_Mode_Get(ISO11898_MODE_TYPE_RESET)) - { - return ERROR; - } - - tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_BUS_TIMING_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, ISO11898_SYNC_JUMP_WIDTH, width); - BL_WR_REG(ISO11898_BASE, ISO11898_BUS_TIMING_0, tmpVal); - - return SUCCESS; -} - -uint8_t ISO11898_Synchronization_Jump_Width_Get(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_BUS_TIMING_0); - return (uint8_t)BL_GET_REG_BITS_VAL(tmpVal, ISO11898_SYNC_JUMP_WIDTH); -} - -BL_Err_Type ISO11898_Sample_Parameter_Set(uint8_t num, uint8_t head, uint8_t tail) -{ - uint32_t tmpVal = 0; - - /* Must be operated in reset mode */ - if (ISO11898_MODE_VALUE_NORMAL == ISO11898_Mode_Get(ISO11898_MODE_TYPE_RESET)) - { - return ERROR; - } - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, ISO11898_TIME_SEGMENT_1, head); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, ISO11898_TIME_SEGMENT_2, tail); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, ISO11898_SAMPLING, num); - BL_WR_REG(ISO11898_BASE, ISO11898_BUS_TIMING_1, tmpVal & 0xFF); - - return SUCCESS; -} - -void ISO11898_Sample_Parameter_Get(uint8_t *num, uint8_t *head, uint8_t *tail) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_BUS_TIMING_1); - *head = (uint8_t)BL_GET_REG_BITS_VAL(tmpVal, ISO11898_TIME_SEGMENT_1); - *tail = (uint8_t)BL_GET_REG_BITS_VAL(tmpVal, ISO11898_TIME_SEGMENT_2); - *num = (uint8_t)BL_GET_REG_BITS_VAL(tmpVal, ISO11898_SAMPLING); -} - -void ISO11898_Filter_Set(const ISO11898_FILTER_CFG_Type *cfg) -{ - uint8_t tmpVal[8] = {0}; //tmpVal[0~3] for match, tmpVal[4~7] for mask - - /* Config filter must be in reset mode */ - ISO11898_MODE_VALUE_Type modeReset = ISO11898_Mode_Get(ISO11898_MODE_TYPE_RESET); - ISO11898_Mode_Set(ISO11898_MODE_TYPE_RESET, ISO11898_MODE_VALUE_RESET); - - - /* Single filter mode */ - if (ISO11898_MODE_VALUE_ACCEPTANCE_FILTER_SINGLE == cfg->filterMode) - { - ISO11898_Mode_Set(ISO11898_MODE_TYPE_ACCEPTANCE_FILTER, ISO11898_MODE_VALUE_ACCEPTANCE_FILTER_SINGLE); - /* Filter: ID10~0 + RTR + Data1 + Data2 */ - if (ISO11898_FRAME_FORMAT_STANDARD == cfg->formatType) - { - tmpVal[0] = (uint8_t)(cfg->matchId1 >> 3); - tmpVal[1] = (uint8_t)(cfg->matchId1 << 5); - tmpVal[1] |= (uint8_t)(cfg->matchRtr1 << 4); - tmpVal[2] = cfg->matchData1; - tmpVal[3] = cfg->matchData2; - tmpVal[4] = (uint8_t)(cfg->maskId1 >> 3); - tmpVal[5] = (uint8_t)(cfg->maskId1 << 5); - tmpVal[5] |= (uint8_t)(cfg->maskRtr1 << 4); - tmpVal[5] |= (uint8_t)0x0F;//0b1111 for unused bit 3:0 - tmpVal[6] = cfg->maskData1; - tmpVal[7] = cfg->maskData2; - } - /* Filter: ID28~0 + RTR */ - else if(ISO11898_FRAME_FORMAT_EXTENDED == cfg->formatType) - { - tmpVal[0] = (uint8_t)(cfg->matchId1 >> 21); - tmpVal[1] = (uint8_t)(cfg->matchId1 >> 13); - tmpVal[2] = (uint8_t)(cfg->matchId1 >> 5); - tmpVal[3] = (uint8_t)(cfg->matchId1 << 3); - tmpVal[3] |= (uint8_t)(cfg->matchRtr1 << 2); - tmpVal[4] = (uint8_t)(cfg->maskId1 >> 21); - tmpVal[5] = (uint8_t)(cfg->maskId1 >> 13); - tmpVal[6] = (uint8_t)(cfg->maskId1 >> 5); - tmpVal[7] = (uint8_t)(cfg->maskId1 << 3); - tmpVal[7] |= (uint8_t)(cfg->maskRtr1 << 2); - tmpVal[7] |= (uint8_t)0x03;//0b11 for unused bit 1:0 - } - } - /* Dual filter mode */ - else if (ISO11898_MODE_VALUE_ACCEPTANCE_FILTER_DUAL == cfg->filterMode) - { - ISO11898_Mode_Set(ISO11898_MODE_TYPE_ACCEPTANCE_FILTER, ISO11898_MODE_VALUE_ACCEPTANCE_FILTER_DUAL); - /* Filter1: ID10~0 + RTR + Data1 */ - /* Filter2: ID10~0 + RTR */ - if (ISO11898_FRAME_FORMAT_STANDARD == cfg->formatType) - { - tmpVal[0] = (uint8_t)(cfg->matchId1 >> 3); - tmpVal[1] = (uint8_t)(cfg->matchId1 << 5); - tmpVal[1] |= (uint8_t)(cfg->matchRtr1 << 4); - tmpVal[1] |= (cfg->matchData1 >> 4); - tmpVal[2] = (uint8_t)(cfg->matchId2 >> 3); - tmpVal[3] = (uint8_t)(cfg->matchId2 << 5); - tmpVal[3] |= (uint8_t)(cfg->matchRtr2 << 4); - tmpVal[3] |= (cfg->matchData1 & 0xF); - tmpVal[4] = (uint8_t)(cfg->maskId1 >> 3); - tmpVal[5] = (uint8_t)(cfg->maskId1 << 5); - tmpVal[5] |= (uint8_t)(cfg->maskRtr1 << 4); - tmpVal[5] |= (cfg->maskData1 >> 4); - tmpVal[6] = (uint8_t)(cfg->maskId2 >> 3); - tmpVal[7] = (uint8_t)(cfg->maskId2 << 5); - tmpVal[7] |= (uint8_t)(cfg->maskRtr2 << 4); - tmpVal[7] |= (cfg->maskData1 & 0xF); - } - /* Filter1: ID28~13 */ - /* Filter2: ID28~13 */ - else if (ISO11898_FRAME_FORMAT_EXTENDED == cfg->formatType) - { - tmpVal[0] = (uint8_t)(cfg->matchId1 >> 21); - tmpVal[1] = (uint8_t)(cfg->matchId1 >> 13); - tmpVal[2] = (uint8_t)(cfg->matchId2 >> 21); - tmpVal[3] = (uint8_t)(cfg->matchId2 >> 13); - tmpVal[4] = (uint8_t)(cfg->maskId1 >> 21); - tmpVal[5] = (uint8_t)(cfg->maskId1 >> 13); - tmpVal[6] = (uint8_t)(cfg->maskId2 >> 21); - tmpVal[7] = (uint8_t)(cfg->maskId2 >> 13); - } - } - /* Write configuration to Registers*/ - BL_WR_REG(ISO11898_BASE, ISO11898_FILTER_ACCEPTANCE_0, (uint32_t)tmpVal[0]); - BL_WR_REG(ISO11898_BASE, ISO11898_FILTER_ACCEPTANCE_1, (uint32_t)tmpVal[1]); - BL_WR_REG(ISO11898_BASE, ISO11898_FILTER_ACCEPTANCE_2, (uint32_t)tmpVal[2]); - BL_WR_REG(ISO11898_BASE, ISO11898_FILTER_ACCEPTANCE_3, (uint32_t)tmpVal[3]); - BL_WR_REG(ISO11898_BASE, ISO11898_FILTER_Mask_0, (uint32_t)tmpVal[4]); - BL_WR_REG(ISO11898_BASE, ISO11898_FILTER_Mask_1, (uint32_t)tmpVal[5]); - BL_WR_REG(ISO11898_BASE, ISO11898_FILTER_Mask_2, (uint32_t)tmpVal[6]); - BL_WR_REG(ISO11898_BASE, ISO11898_FILTER_Mask_3, (uint32_t)tmpVal[7]); - - /* Recovery reset mode value */ - ISO11898_Mode_Set(ISO11898_MODE_TYPE_RESET, modeReset); -} - -void ISO11898_Filter_Register_Set(ISO11898_FILTER_REGISTER_Type reg, uint8_t value) -{ - /* Config filter must be in reset mode */ - ISO11898_MODE_VALUE_Type modeReset = ISO11898_Mode_Get(ISO11898_MODE_TYPE_RESET); - ISO11898_Mode_Set(ISO11898_MODE_TYPE_RESET, ISO11898_MODE_VALUE_RESET); - - /* Write configuration to Register*/ - BL_WR_WORD(ISO11898_BASE + ISO11898_FILTER_ACCEPTANCE_0_OFFSET + 4 * reg, value); - - /* Recovery reset mode value */ - ISO11898_Mode_Set(ISO11898_MODE_TYPE_RESET, modeReset); -} - -void ISO11898_Filter_Registers_Set(uint8_t *valueArr) -{ - /* Config filter must be in reset mode */ - ISO11898_MODE_VALUE_Type modeReset = ISO11898_Mode_Get(ISO11898_MODE_TYPE_RESET); - ISO11898_Mode_Set(ISO11898_MODE_TYPE_RESET, ISO11898_MODE_VALUE_RESET); - - /* Write configuration to Registers*/ - BL_WR_REG(ISO11898_BASE, ISO11898_FILTER_ACCEPTANCE_0, (uint32_t)valueArr[0]); - BL_WR_REG(ISO11898_BASE, ISO11898_FILTER_ACCEPTANCE_1, (uint32_t)valueArr[1]); - BL_WR_REG(ISO11898_BASE, ISO11898_FILTER_ACCEPTANCE_2, (uint32_t)valueArr[2]); - BL_WR_REG(ISO11898_BASE, ISO11898_FILTER_ACCEPTANCE_3, (uint32_t)valueArr[3]); - BL_WR_REG(ISO11898_BASE, ISO11898_FILTER_Mask_0, (uint32_t)valueArr[4]); - BL_WR_REG(ISO11898_BASE, ISO11898_FILTER_Mask_1, (uint32_t)valueArr[5]); - BL_WR_REG(ISO11898_BASE, ISO11898_FILTER_Mask_2, (uint32_t)valueArr[6]); - BL_WR_REG(ISO11898_BASE, ISO11898_FILTER_Mask_3, (uint32_t)valueArr[7]); - - /* Recovery reset mode value */ - ISO11898_Mode_Set(ISO11898_MODE_TYPE_RESET, modeReset); -} - -#ifndef BFLB_USE_HAL_DRIVER -BL_Err_Type ISO11898_Int_Callback_Install(ISO11898_INT_Type intType,intCallback_Type* cbFun) -{ - /* Check the parameters */ - CHECK_PARAM(IS_ISO11898_FRAME_FORMAT_TYPE(cbFun)); - CHECK_PARAM(IS_ISO11898_INT_TYPE(intType)); - - iso11898IntCbfArra[intType] = cbFun; - - return SUCCESS; -} - -static void ISO11898_IntHandler(void) -{ - uint32_t tmpVal = 0; - uint32_t i = 0; - - tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_INTERRUPT); - - for(i=0; i
© COPYRIGHT(c) 2020 Bouffalo Lab
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808.h" -#include "bl808_common.h" -#include "bl808_lz4d.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup LZ4D - * @{ - */ - -/** @defgroup LZ4D_Private_Macros - * @{ - */ - -/*@} end of group LZ4D_Private_Macros */ - -/** @defgroup LZ4D_Private_Types - * @{ - */ - -/*@} end of group LZ4D_Private_Types */ - -/** @defgroup LZ4D_Private_Variables - * @{ - */ - -#ifndef BFLB_USE_HAL_DRIVER -static intCallback_Type *lz4dIntCbfArra[LZ4D_INT_ALL] = { NULL }; -#endif - -/*@} end of group LZ4D_Private_Variables */ - -/** @defgroup LZ4D_Global_Variables - * @{ - */ - -/*@} end of group LZ4D_Global_Variables */ - -/** @defgroup LZ4D_Private_Fun_Declaration - * @{ - */ - -/*@} end of group LZ4D_Private_Fun_Declaration */ - -/** @defgroup LZ4D_Private_Functions - * @{ - */ - -/*@} end of group LZ4D_Private_Functions */ - -/** @defgroup LZ4D_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief None - * - * @param None - * - * @return None - * -*******************************************************************************/ -void LZ4D_Stop(void) -{ - LZ4DECOMPRESSOR->lz4_config.BF.lz4_en = 0; -} - -void LZ4D_Start(void) -{ - LZ4DECOMPRESSOR->lz4_config.BF.lz4_en = 1; -} - -uint32_t LZ4D_GetAddrReg(LZ4D_ADDR_REG_Type addr) -{ - uint32_t res = -1; - - switch (addr) { - case LZ4D_ADDR_END_SRC: - res = LZ4DECOMPRESSOR->lz4_src_end.WORD & LZ4D_ADDR_END_MAX; - break; - - case LZ4D_ADDR_END_DST: - res = LZ4DECOMPRESSOR->lz4_dst_end.WORD & LZ4D_ADDR_END_MAX; - break; - - case LZ4D_ADDR_BASE_SRC: - res = LZ4DECOMPRESSOR->lz4_src_start.WORD; - break; - - case LZ4D_ADDR_BASE_DST: - res = LZ4DECOMPRESSOR->lz4_dst_start.WORD; - break; - - default: - break; - } - - return res; -} - -uint32_t LZ4D_GetDecompressLen(void) -{ - uint32_t len = 0; - - len = LZ4D_GetAddrReg(LZ4D_ADDR_END_DST) - - (LZ4D_GetAddrReg(LZ4D_ADDR_BASE_DST) & LZ4D_ADDR_END_MAX); - - return len; -} - -uint32_t LZ4D_GetStatus(LZ4D_STATUS_Type sts) -{ - uint32_t res = 0; - - switch (sts) { - case LZ4D_STATUS_DONE ... LZ4D_STATUS_ERROR: - res = LZ4DECOMPRESSOR->lz4_int_sta.WORD & sts; - break; - - default: - break; - } - - return res; -} - -void LZ4D_Decompress(const void *in, void *out) -{ - LZ4DECOMPRESSOR->lz4_config.BF.lz4_en = 0; - - LZ4DECOMPRESSOR->lz4_src_start.WORD = (uint32_t)(uintptr_t)in; - /* TODO: the out region length must be 4-byte aligned: - * e.g.: the decompressed length is 33, you have to allocate 36 bytes for it. - * or, the HW will overwrite the RAM space from offset 34 to 36. - */ - LZ4DECOMPRESSOR->lz4_dst_start.WORD = (uint32_t)(uintptr_t)out; - - /* flush the CPU D$ in case of data bas been cached, - * e.g., the compressed data is copied by CPU. - */ - //L1C_DCache_Clean_Invalid_All(); - - LZ4DECOMPRESSOR->lz4_config.BF.lz4_en = 1; - - /* after LZ4D doing it's job, CPU has to invalid the cache line for *out */ -} - -/******************************************************************************* - * @brief LZ4D mask or unmask certain or all interrupt - * - * @param intType: interrupt type - * @param intMask: mask or unmask - * - * @return None - * -*******************************************************************************/ -void LZ4D_IntMask(LZ4D_INT_Type intType, BL_Mask_Type intMask) -{ - /* Check the parameters */ - CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); - - switch (intType) { - case LZ4D_INT_DONE: - if (UNMASK == intMask) { - LZ4DECOMPRESSOR->lz4_int_en.BF.lz4_done_en = 1; - } else { - LZ4DECOMPRESSOR->lz4_int_en.BF.lz4_done_en = 0; - } - break; - - case LZ4D_INT_ERROR: - if (UNMASK == intMask) { - LZ4DECOMPRESSOR->lz4_int_en.BF.lz4_err_en = 1; - } else { - LZ4DECOMPRESSOR->lz4_int_en.BF.lz4_err_en = 0; - } - break; - - case LZ4D_INT_ALL: - if (UNMASK == intMask) { - LZ4DECOMPRESSOR->lz4_int_en.BF.lz4_done_en = 1; - LZ4DECOMPRESSOR->lz4_int_en.BF.lz4_err_en = 1; - } else { - LZ4DECOMPRESSOR->lz4_int_en.BF.lz4_done_en = 0; - LZ4DECOMPRESSOR->lz4_int_en.BF.lz4_err_en = 0; - } - break; - - default: - /* invalid param */ - break; - } -} - -/******************************************************************************* - * @brief ADC install interrupt callback - * - * @param intType: ADC interrupt type - * @param cbFun: ADC interrupt callback - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void LZ4D_Int_Callback_Install(LZ4D_INT_Type intType, intCallback_Type *cbFun) -{ - if (intType < LZ4D_INT_ALL) - lz4dIntCbfArra[intType] = cbFun; -} -#endif - -/******************************************************************************* - * @brief LZ4D interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void LZ4D_IRQHandler(void) -{ - if (LZ4D_GetStatus(LZ4D_STATUS_DONE)) { - if (lz4dIntCbfArra[LZ4D_INT_DONE] != NULL) { - lz4dIntCbfArra[LZ4D_INT_DONE](); - } - } - - if (LZ4D_GetStatus(LZ4D_STATUS_ERROR)) { - if (lz4dIntCbfArra[LZ4D_INT_ERROR] != NULL) { - lz4dIntCbfArra[LZ4D_INT_ERROR](); - } - } -} -#endif - -void LZ4D_Init(void) -{ -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(LZ4D_IRQn, LZ4D_IRQHandler); -#endif -} - -/*@} end of group LZ4D_Public_Functions */ - -/*@} end of group LZ4D */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mfg_efuse.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mfg_efuse.c deleted file mode 100644 index cfce979ae9..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mfg_efuse.c +++ /dev/null @@ -1,105 +0,0 @@ -#include "bl808_glb.h" -#include "bl808_mfg_efuse.h" -#include "bl808_ef_ctrl.h" -#include "bl808_ef_cfg.h" - -static uint8_t rf_cal_slots=3; -extern void main(void); -#define RF_CAL_SLOT_CFG_OFFSET (4*13) -#ifdef BFLB_MCU_SDK -#include "bflb_platform.h" -#define mfg_print MSG -#else -#define mfg_print printf -#endif - -uint8_t mfg_efuse_get_rf_cal_slots(void) -{ - return rf_cal_slots; -} - -void mfg_efuse_set_rf_cal_slots(uint8_t slots) -{ - rf_cal_slots=slots; -} - -uint8_t mfg_efuse_is_macaddr_slot_empty(uint8_t reload) -{ - uint8_t empty=0; - - - if(rf_cal_slots>=1&&EF_Ctrl_Is_MAC_Address_Slot_Empty(0,reload)){ - empty=1; - }else if(rf_cal_slots>=2&&EF_Ctrl_Is_MAC_Address_Slot_Empty(1,reload)){ - empty=1; - }else if(rf_cal_slots>=3&&EF_Ctrl_Is_MAC_Address_Slot_Empty(2,reload)){ - empty=1; - }else{ - } - - - return empty; -} - -int8_t mfg_efuse_write_macaddr_pre(uint8_t mac[6],uint8_t program) -{ - BL_Err_Type ret=SUCCESS; - uint8_t slot=0xff; - - if(rf_cal_slots>=1&&EF_Ctrl_Is_MAC_Address_Slot_Empty(0,1)){ - slot=0; - }else if(rf_cal_slots>=2&&EF_Ctrl_Is_MAC_Address_Slot_Empty(1,1)){ - slot=1; - }else if(rf_cal_slots>=3&&EF_Ctrl_Is_MAC_Address_Slot_Empty(2,1)){ - slot=2; - }else{ - mfg_print("No empty slot found\r\n"); - } - - if(slot!=0xff){ - ret=EF_Ctrl_Write_MAC_Address_Opt(slot,mac,program); - mfg_print("Write slot:%d\r\n",slot); - } - - - if(ret==SUCCESS){ - return 0; - }else{ - return -1; - } -} - -void mfg_efuse_write_macaddr(void) -{ - EF_Ctrl_Program_Direct_R0(0,NULL,0); - while(SET==EF_Ctrl_Busy()); -} - -int8_t mfg_efuse_read_macaddr(uint8_t mac[6],uint8_t reload) -{ - uint8_t slot=0xff; - BL_Err_Type ret=ERROR; - - - if(rf_cal_slots>=3&&(!EF_Ctrl_Is_MAC_Address_Slot_Empty(2,reload))){ - slot=2; - }else if(rf_cal_slots>=2&&(!EF_Ctrl_Is_MAC_Address_Slot_Empty(1,reload))){ - slot=1; - }else if(rf_cal_slots>=1&&(!EF_Ctrl_Is_MAC_Address_Slot_Empty(0,reload))){ - slot=0; - } - - if(slot!=0xff){ - mfg_print("Read slot:%d\r\n",slot); - ret=EF_Ctrl_Read_MAC_Address_Opt(slot,mac,reload); - }else{ - mfg_print("No written slot found\r\n"); - } - - - if(ret==SUCCESS){ - return 0; - }else{ - return -1; - } -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mfg_flash.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mfg_flash.c deleted file mode 100644 index 907720aa62..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mfg_flash.c +++ /dev/null @@ -1,241 +0,0 @@ -#include "bl808_mfg_flash.h" -#include "softcrc.h" - -static rf_para_flash_t rf_para; -static uint32_t rf_para_addr=0; -static SPI_Flash_Cfg_Type *pFlashCfg; - -//#define RF_PARA_MAGIC_FLAG 0x41504652 -#define RF_PARA_MAGIC_FLAG 0x41 -#define RF_PARA_VALID_FLAG 0x5A -#define RF_PARA_PART_NAME "rf_para" - - -//PtTable_Stuff_Config ptTableStuff[2]; -//PtTable_Entry_Config ptEntry={0}; - - -static BL_Err_Type PtTable_Flash_Read (uint32_t addr,uint8_t *data, uint32_t len) -{ - //XIP_SFlash_Read_Need_Lock_Ext(pFlashCfg,addr,data,len); - return SUCCESS; -} - -int8_t mfg_flash_init( SPI_Flash_Cfg_Type *flashCfg) -{ -#if 0 - PtTable_ID_Type activeID; - PtTable_Error_Type ret; - - pFlashCfg=flashCfg; - if(pFlashCfg!=NULL){ - PtTable_Set_Flash_Operation(NULL,NULL,PtTable_Flash_Read); - activeID=PtTable_Get_Active_Partition_Need_Lock(ptTableStuff); - if(PT_TABLE_ID_INVALID==activeID){ - //mfg_print("No valid PT\r\n"); - return -1; - } - ret=PtTable_Get_Active_Entries_By_Name(&ptTableStuff[activeID],(uint8_t*)RF_PARA_PART_NAME,&ptEntry); - if(PT_ERROR_SUCCESS==ret){ - rf_para_addr=ptEntry.Address[0]; - //mfg_print("RF para flash address=%08x\r\n",(unsigned int)rf_para_addr); - return 0; - }else{ - //mfg_print("Not found "RF_PARA_PART_NAME"\r\n"); - return -1; - } - } -#endif - return -1; -} - -static int8_t mfg_flash_program(void) -{ -#if 0 - BL_Err_Type ret; - - //mfg_print("mfg_flash_write\r\n"); - - ret=XIP_SFlash_Erase_Need_Lock_Ext(pFlashCfg,rf_para_addr,rf_para_addr+15); - if(ret!=SUCCESS){ - //mfg_print("Flash erase error\r\n"); - return -1; - } - - ret=XIP_SFlash_Write_Need_Lock_Ext(pFlashCfg,rf_para_addr,(uint8_t *)&rf_para,sizeof(rf_para)); - if(ret!=SUCCESS){ - //mfg_print("Flash write error\r\n"); - return -1; - } -#endif - return 0; -} - -static int8_t mfg_flash_read(void) -{ -#if 0 - BL_Err_Type ret; - - //mfg_print("mfg_flash_read\r\n"); - - ret=XIP_SFlash_Read_Need_Lock_Ext(pFlashCfg,rf_para_addr,(uint8_t *)&rf_para,sizeof(rf_para)); - if(ret!=SUCCESS){ - //mfg_print("Flash write error\r\n"); - return -1; - } -#endif - return 0; -} - -int8_t mfg_flash_write_xtal_capcode_pre(uint8_t capcode,uint8_t program) -{ -#if 0 - rf_para.magic=RF_PARA_MAGIC_FLAG; - rf_para.capcode_valid=RF_PARA_VALID_FLAG; - rf_para.capcode=capcode; - rf_para.crc32=BFLB_Soft_CRC32(&rf_para.capcode_valid,sizeof(rf_para)-8); - - if(program){ - return mfg_flash_program(); - }else{ - return 0; - } -#endif - return 0; -} - -void mfg_flash_write_xtal_capcode(void) -{ - //mfg_flash_program(); -} - -int8_t mfg_flash_read_xtal_capcode(uint8_t *capcode,uint8_t reload) -{ -#if 0 - if((reload!=0)&&(mfg_flash_read()!=0)){ - return -1; - } - if(rf_para.magic==RF_PARA_MAGIC_FLAG){ - if(rf_para.crc32==(BFLB_Soft_CRC32(&rf_para.capcode_valid,sizeof(rf_para)-8))){ - if(rf_para.capcode_valid==RF_PARA_VALID_FLAG){ - *capcode=rf_para.capcode; - return 0; - } - } - } -#endif - return -1; -} - -int8_t mfg_flash_write_poweroffset_pre(int8_t pwrOffset[14],uint8_t program) -{ -#if 0 - rf_para.magic=RF_PARA_MAGIC_FLAG; - rf_para.poweroffset_valid=RF_PARA_VALID_FLAG; - rf_para.poweroffset[0]=pwrOffset[0]; - rf_para.poweroffset[1]=pwrOffset[6]; - rf_para.poweroffset[2]=pwrOffset[12]; - rf_para.crc32=BFLB_Soft_CRC32(&rf_para.capcode_valid,sizeof(rf_para)-8); - - if(program){ - return mfg_flash_program(); - }else{ - return 0; - } -#endif - return 0; -} - -void mfg_flash_write_poweroffset(void) -{ - //mfg_flash_program(); -} - -int8_t mfg_flash_read_poweroffset(int8_t pwrOffset[14],uint8_t reload) -{ -#if 0 - int8_t pwrOffsetTmp[3]; - int32_t step=0; - - if((reload!=0)&&(mfg_flash_read()!=0)){ - return -1; - } - if(rf_para.magic==RF_PARA_MAGIC_FLAG){ - if(rf_para.crc32==(BFLB_Soft_CRC32(&rf_para.capcode_valid,sizeof(rf_para)-8))){ - if(rf_para.poweroffset_valid==RF_PARA_VALID_FLAG){ - memset(pwrOffset,0,14); - pwrOffsetTmp[0]=rf_para.poweroffset[0]; - pwrOffsetTmp[1]=rf_para.poweroffset[1]; - pwrOffsetTmp[2]=rf_para.poweroffset[2]; - - pwrOffset[0]=pwrOffsetTmp[0]; - - step=(pwrOffsetTmp[1]-pwrOffsetTmp[0])*100/6; - pwrOffset[1]=(step+50)/100+pwrOffsetTmp[0]; - pwrOffset[2]=(step*2+50)/100+pwrOffsetTmp[0]; - pwrOffset[3]=(step*3+50)/100+pwrOffsetTmp[0]; - pwrOffset[4]=(step*4+50)/100+pwrOffsetTmp[0]; - pwrOffset[5]=(step*5+50)/100+pwrOffsetTmp[0]; - - pwrOffset[6]=pwrOffsetTmp[1]; - - step=(pwrOffsetTmp[2]-pwrOffsetTmp[1])*100/6; - pwrOffset[7]=(step+50)/100+pwrOffsetTmp[1]; - pwrOffset[8]=(step*2+50)/100+pwrOffsetTmp[1]; - pwrOffset[9]=(step*3+50)/100+pwrOffsetTmp[1]; - pwrOffset[10]=(step*4+50)/100+pwrOffsetTmp[1]; - pwrOffset[11]=(step*5+50)/100+pwrOffsetTmp[1]; - - pwrOffset[12]=pwrOffsetTmp[2]; - - pwrOffset[13]=(step*7+50)/100+pwrOffsetTmp[1]; - return 0; - } - } - } -#endif - return -1; - -} - -int8_t mfg_flash_write_macaddr_pre(uint8_t mac[6],uint8_t program) -{ -#if 0 - rf_para.magic=RF_PARA_MAGIC_FLAG; - rf_para.mac_valid=RF_PARA_VALID_FLAG; - memcpy(rf_para.mac,mac,6); - rf_para.crc32=BFLB_Soft_CRC32(&rf_para.capcode_valid,sizeof(rf_para)-8); - - if(program){ - return mfg_flash_program(); - }else{ - return 0; - } -#endif - return 0; -} - -void mfg_flash_write_macaddr(void) -{ - //mfg_flash_program(); -} - -int8_t mfg_flash_read_macaddr(uint8_t mac[6],uint8_t reload) -{ -#if 0 - if((reload!=0)&&(mfg_flash_read()!=0)){ - //mfg_print("mfg_flash_read fail\r\n"); - return -1; - } - if(rf_para.magic==RF_PARA_MAGIC_FLAG){ - if(rf_para.crc32==(BFLB_Soft_CRC32(&rf_para.capcode_valid,sizeof(rf_para)-8))){ - if(rf_para.mac_valid==RF_PARA_VALID_FLAG){ - memcpy(mac,rf_para.mac,6); - return 0; - } - } - } -#endif - return -1; -} - diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mfg_media.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mfg_media.c deleted file mode 100644 index 745c2b91d2..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mfg_media.c +++ /dev/null @@ -1,237 +0,0 @@ -#include "bl808_mfg_media.h" - -static uint8_t rf_para_on_flash=0; - -#if 0 -int8_t mfg_media_init_need_lock( SPI_Flash_Cfg_Type *flashCfg) -{ - if(0==mfg_flash_init(flashCfg)){ - rf_para_on_flash=1; - }else{ - rf_para_on_flash=0; - } - return 0; -} - -int8_t mfg_media_init_with_lock( SPI_Flash_Cfg_Type *flashCfg) -{ - int8_t ret; - - __disable_irq(); - ret=mfg_media_init_need_lock(flashCfg); - __enable_irq(); - - return ret; -} - -uint8_t mfg_media_is_xtal_capcode_slot_empty(uint8_t reload) -{ - if(rf_para_on_flash){ - return 1; - }else{ - return mfg_efuse_is_xtal_capcode_slot_empty(reload); - } -} - -int8_t mfg_media_write_xtal_capcode_pre_need_lock(uint8_t capcode,uint8_t program) -{ - if(rf_para_on_flash){ - return mfg_flash_write_xtal_capcode_pre(capcode,program); - }else{ - return mfg_efuse_write_xtal_capcode_pre(capcode,program); - } -} - -int8_t mfg_media_write_xtal_capcode_pre_with_lock(uint8_t capcode,uint8_t program) -{ - int8_t ret; - - __disable_irq(); - ret=mfg_media_write_xtal_capcode_pre_need_lock(capcode,program); - __enable_irq(); - - return ret; -} - -void mfg_media_write_xtal_capcode_need_lock(void) -{ - if(rf_para_on_flash){ - return mfg_flash_write_xtal_capcode(); - }else{ - return mfg_efuse_write_xtal_capcode(); - } -} - -void mfg_media_write_xtal_capcode_with_lock(void) -{ - __disable_irq(); - mfg_media_write_xtal_capcode_need_lock(); - __enable_irq(); -} - -int8_t mfg_media_read_xtal_capcode_need_lock(uint8_t *capcode,uint8_t reload) -{ - if(rf_para_on_flash){ - return mfg_flash_read_xtal_capcode(capcode,reload); - }else{ - return mfg_efuse_read_xtal_capcode(capcode,reload); - } -} - -int8_t mfg_media_read_xtal_capcode_with_lock(uint8_t *capcode,uint8_t reload) -{ - int8_t ret; - - __disable_irq(); - ret=mfg_media_read_xtal_capcode_need_lock(capcode,reload); - __enable_irq(); - - return ret; -} - -int8_t mfg_media_read_xtal_capcode(uint8_t *capcode,uint8_t reload) -{ - return mfg_media_read_xtal_capcode_need_lock(capcode,reload); -} - -uint8_t mfg_media_is_poweroffset_slot_empty(uint8_t reload) -{ - if(rf_para_on_flash){ - return 1; - }else{ - return mfg_efuse_is_poweroffset_slot_empty(reload); - } -} - -int8_t mfg_media_write_poweroffset_pre_need_lock(int8_t pwrOffset[14],uint8_t program) -{ - if(rf_para_on_flash){ - return mfg_flash_write_poweroffset_pre(pwrOffset,program); - }else{ - return mfg_efuse_write_poweroffset_pre(pwrOffset,program); - } -} - -int8_t mfg_media_write_poweroffset_pre_with_lock(int8_t pwrOffset[14],uint8_t program) -{ - int ret; - - __disable_irq(); - ret=mfg_media_write_poweroffset_pre_need_lock(pwrOffset,program); - __enable_irq(); - - return ret; -} - -void mfg_media_write_poweroffset_need_lock(void) -{ - if(rf_para_on_flash){ - return mfg_flash_write_poweroffset(); - }else{ - return mfg_efuse_write_poweroffset(); - } -} - -void mfg_media_write_poweroffset_with_lock(void) -{ - __disable_irq(); - mfg_media_write_poweroffset_need_lock(); - __enable_irq(); -} - -int8_t mfg_media_read_poweroffset_need_lock(int8_t pwrOffset[14],uint8_t reload) -{ - if(rf_para_on_flash){ - return mfg_flash_read_poweroffset(pwrOffset,reload); - }else{ - return mfg_efuse_read_poweroffset(pwrOffset,reload); - } -} - -int8_t mfg_media_read_poweroffset_with_lock(int8_t pwrOffset[14],uint8_t reload) -{ - int ret; - - __disable_irq(); - ret=mfg_media_read_poweroffset_need_lock(pwrOffset,reload); - __enable_irq(); - - return ret; -} - -int8_t mfg_media_read_poweroffset(int8_t pwrOffset[14],uint8_t reload) -{ - return mfg_media_read_poweroffset_need_lock(pwrOffset,reload); -} -#endif -uint8_t mfg_media_is_macaddr_slot_empty(uint8_t reload) -{ - if(rf_para_on_flash){ - return 1; - }else{ - return mfg_efuse_is_macaddr_slot_empty(reload); - } -} - -int8_t mfg_media_write_macaddr_pre_need_lock(uint8_t mac[6],uint8_t program) -{ - if(rf_para_on_flash){ - return mfg_flash_write_macaddr_pre(mac,program); - }else{ - return mfg_efuse_write_macaddr_pre(mac,program); - } -} - -int8_t mfg_media_write_macaddr_pre_with_lock(uint8_t mac[6],uint8_t program) -{ - int ret; - - __disable_irq(); - ret=mfg_media_write_macaddr_pre_need_lock(mac,program); - __enable_irq(); - - return ret; -} - -void mfg_media_write_macaddr_need_lock(void) -{ - if(rf_para_on_flash){ - return mfg_flash_write_macaddr(); - }else{ - return mfg_efuse_write_macaddr(); - } -} - -void mfg_media_write_macaddr_with_lock(void) -{ - __disable_irq(); - mfg_media_write_macaddr_need_lock(); - __enable_irq(); -} - -int8_t mfg_media_read_macaddr_need_lock(uint8_t mac[6],uint8_t reload) -{ - if(rf_para_on_flash){ - return mfg_flash_read_macaddr(mac,reload); - }else{ - return mfg_efuse_read_macaddr(mac,reload); - } -} - -int8_t mfg_media_read_macaddr_with_lock(uint8_t mac[6],uint8_t reload) -{ - int ret; - - __disable_irq(); - ret=mfg_media_read_macaddr_need_lock(mac,reload); - __enable_irq(); - - return ret; -} - -int8_t mfg_media_read_macaddr(uint8_t mac[6],uint8_t reload) -{ - - return mfg_media_read_macaddr_need_lock(mac,reload); -} - diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mjdec.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mjdec.c deleted file mode 100644 index ca0d7e8dd5..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mjdec.c +++ /dev/null @@ -1,467 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_mjdec.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808.h" -#include "bl808_mjdec.h" -#include "bl808_glb.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup MJDEC - * @{ - */ - -/** @defgroup MJDEC_Private_Macros - * @{ - */ - -/*@} end of group MJDEC_Private_Macros */ - -/** @defgroup MJDEC_Private_Types - * @{ - */ - -/*@} end of group MJDEC_Private_Types */ - -/** @defgroup MJDEC_Private_Variables - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -static intCallback_Type * mjdecIntCbfArra[MJDEC_INT_ALL] = {NULL}; -#endif - -/*@} end of group MJDEC_Private_Variables */ - -/** @defgroup MJDEC_Global_Variables - * @{ - */ - -/*@} end of group MJDEC_Global_Variables */ - -/** @defgroup MJDEC_Private_Fun_Declaration - * @{ - */ - -/*@} end of group MJDEC_Private_Fun_Declaration */ - -/** @defgroup MJDEC_Private_Functions - * @{ - */ - -/*@} end of group MJDEC_Private_Functions */ - -/** @defgroup MJDEC_Public_Functions - * @{ - */ - -/****************************************************************************//** - * @brief Mjdec module init - * - * @param cfg: Mjdec configuration structure pointer - * - * @return None - * -*******************************************************************************/ -void MJDEC_Init(MJDEC_CFG_Type *cfg) -{ - uint32_t tmpVal; - uint32_t q; - - /* disable mjdec */ - tmpVal = BL_RD_REG(MJDEC_BASE, MJDEC_JDEC_CONTROL_1); - tmpVal = BL_CLR_REG_BIT(tmpVal, MJDEC_REG_MJ_DEC_ENABLE); - BL_WR_REG(MJDEC_BASE, MJDEC_JDEC_CONTROL_1, tmpVal); - - if(cfg->picQuality < 1) { - q = 1; - } else if(cfg->picQuality > 75) { - q = 100; - } else { - q = cfg->picQuality; - } - - /* basic configure */ - tmpVal = BL_RD_REG(MJDEC_BASE, MJDEC_JDEC_CONTROL_1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_YUV_MODE, cfg->yuv); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_W_XLEN, cfg->burstWrite); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_R_XLEN, cfg->burstRead); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_U_EVEN, cfg->evenOrderEnable); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_LAST_HF_BLK_DMY, cfg->dmyBlock); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_LAST_HF_HBLK_DMY, cfg->dmyVertical); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_LAST_HF_WBLK_DMY, cfg->dmyHorizational); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_SWAP_MODE, cfg->swapMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_Q_MODE, q); - BL_WR_REG(MJDEC_BASE, MJDEC_JDEC_CONTROL_1, tmpVal); - - tmpVal = BL_RD_REG(MJDEC_BASE, MJDEC_JDEC_CONTROL_3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,MJDEC_REG_FRAME_CNT_TRGR_INT,cfg->intCnt); - BL_WR_REG(MJDEC_BASE, MJDEC_JDEC_CONTROL_3,tmpVal); - - /* align buffer to 16 bytes boundary */ - BL_WR_REG(MJDEC_BASE, MJDEC_JDEC_YY_FRAME_ADDR, (cfg->bufferFrameYY + 0xF) & (~0xF)); - BL_WR_REG(MJDEC_BASE, MJDEC_JDEC_UV_FRAME_ADDR, (cfg->bufferFrameUV + 0xF) & (~0xF)); - - tmpVal = BL_RD_REG(MJDEC_BASE, MJDEC_JDEC_FRAME_SIZE); - switch(cfg->yuv) - { - case MJDEC_YUV422_PLANAR: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_FRAME_WBLK, (cfg->resolutionX+15)>>4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_FRAME_HBLK, (cfg->resolutionY+7)>>3); - break; - case MJDEC_YUV420: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_FRAME_WBLK, (cfg->resolutionX+15)>>4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_FRAME_HBLK, (cfg->resolutionY+15)>>4); - break; - case MJDEC_YUV400: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_FRAME_WBLK, (cfg->resolutionX+7)>>3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_FRAME_HBLK, (cfg->resolutionY+7)>>3); - break; - default: - break; - } - BL_WR_REG(MJDEC_BASE,MJDEC_JDEC_FRAME_SIZE, tmpVal); - - tmpVal = BL_RD_REG(MJDEC_BASE, MJDEC_JDEC_HEADER_SKIP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_HDER_SKIP, cfg->headSkip); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_HDER_SKIP_BYTE, cfg->headByte); - BL_WR_REG(MJDEC_BASE,MJDEC_JDEC_HEADER_SKIP, tmpVal); - - /* Clear interrupt */ - BL_WR_REG(MJDEC_BASE, MJDEC_JDEC_INT_CLR, 0x1); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(MJDEC_IRQn, MJDEC_IRQHandler); -#endif -} - -/****************************************************************************//** - * @brief Deinit mjdec module - * - * @param None - * - * @return None - * -*******************************************************************************/ -void MJDEC_Deinit(void) -{ - GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_MJPEG_DEC); -} - -/****************************************************************************//** - * @brief Enable mjdec module - * - * @param None - * - * @return None - * -*******************************************************************************/ -void MJDEC_Enable(void) -{ - uint32_t tmpVal; - - /* Enable mjdec module */ - tmpVal = BL_RD_REG(MJDEC_BASE, MJDEC_JDEC_CONTROL_1); - tmpVal = BL_SET_REG_BIT(tmpVal, MJDEC_REG_MJ_DEC_ENABLE); - BL_WR_REG(MJDEC_BASE, MJDEC_JDEC_CONTROL_1, tmpVal); -} - -/****************************************************************************//** - * @brief Disable mjdec module - * - * @param None - * - * @return None - * -*******************************************************************************/ -void MJDEC_Disable(void) -{ - uint32_t tmpVal; - - /* Disable mjdec module */ - tmpVal = BL_RD_REG(MJDEC_BASE, MJDEC_JDEC_CONTROL_1); - tmpVal = BL_CLR_REG_BIT(tmpVal, MJDEC_REG_MJ_DEC_ENABLE); - BL_WR_REG(MJDEC_BASE, MJDEC_JDEC_CONTROL_1, tmpVal); -} - -/****************************************************************************/ /** - * @brief Get one mjdec frame - * - * @param info: Mjdec frame infomation pointer - * - * @return None - * -*******************************************************************************/ -void MJDEC_Get_Frame_Info(MJDEC_Frame_Info *info) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(MJDEC_BASE, MJDEC_JDEC_CONTROL_3); - info->validFrames = BL_GET_REG_BITS_VAL(tmpVal, MJDEC_FRAME_VALID_CNT); - info->curFrameAddr = BL_RD_REG(MJDEC_BASE, MJDEC_JP_ADDR0); -} - -/****************************************************************************//** - * @brief Get available count of frames - * - * @param None - * - * @return Frames count - * -*******************************************************************************/ -uint8_t MJDEC_Get_Frame_Count(void) -{ - return (uint8_t)BL_GET_REG_BITS_VAL(BL_RD_REG(MJDEC_BASE, MJDEC_JDEC_CONTROL_3), MJDEC_FRAME_VALID_CNT); -} - -/****************************************************************************/ /** - * @brief Push one jpeg picture frame - * - * @param bufferMjpeg: jpeg picture frame buffer pointer - * - * @return None - * -*******************************************************************************/ -BL_Err_Type MJDEC_Push_Frame(uint32_t bufferJpeg) -{ - /* because of AXI 64bits, bufferJpeg address bit [0:2] must be 0 */ - if((bufferJpeg & 0x07) != 0) - { - return INVALID; - } - BL_WR_REG(MJDEC_BASE, MJDEC_JDEC_FRAM_PUSH, bufferJpeg | 0x1); - return SUCCESS; -} - -/****************************************************************************//** - * @brief Pop one mjdec frame - * - * @param None - * - * @return None - * -*******************************************************************************/ -void MJDEC_Pop_Frame(void) -{ - BL_WR_REG(MJDEC_BASE, MJDEC_JDEC_INT_CLR, 1 << 1); -} - -/****************************************************************************//** - * @brief Set frame threshold to issue normal interrupt - * - * @param count: Frame threshold - * - * @return None - * -*******************************************************************************/ -void MJDEC_Set_Frame_Threshold(uint8_t count) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(MJDEC_BASE, MJDEC_JDEC_CONTROL_3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,MJDEC_REG_FRAME_CNT_TRGR_INT,count); - BL_WR_REG(MJDEC_BASE,MJDEC_JDEC_CONTROL_3,tmpVal); -} - -/****************************************************************************//** - * @brief Set Q value - * - * @param q: Q value, must be in 1-75 or 100 - * - * @return None - * -*******************************************************************************/ -void MJDEC_Set_Q_Value(uint8_t q) -{ - uint32_t tmpVal; - - if(q < 1) { - q = 1; - } else if(q > 75) { - q = 100; - } - tmpVal = BL_RD_REG(MJDEC_BASE, MJDEC_JDEC_CONTROL_1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_Q_MODE, q); - BL_WR_REG(MJDEC_BASE, MJDEC_JDEC_CONTROL_1, tmpVal); -} - -/****************************************************************************//** - * @brief MJDEC Enable Disable Interrupt - * - * @param intType: MJDEC Interrupt Type - * @param intMask: Enable or Disable - * - * @return None - * -*******************************************************************************/ -void MJDEC_IntMask(MJDEC_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_MJDEC_INT_TYPE(intType)); - CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); - - tmpVal = BL_RD_REG(MJDEC_BASE,MJDEC_JDEC_CONTROL_3); - switch(intType) - { - case MJDEC_INT_NORMAL: - if(intMask == UNMASK){ - /* Enable this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal,MJDEC_REG_INT_NORMAL_EN); - }else{ - /* Disable this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal,MJDEC_REG_INT_NORMAL_EN); - } - break; - - case MJDEC_INT_BACK_IDLE: - if(intMask == UNMASK){ - /* Enable this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal,MJDEC_REG_INT_IDLE_EN); - }else{ - /* Disable this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal,MJDEC_REG_INT_IDLE_EN); - } - break; - - case MJDEC_INT_ALL: - if(intMask == UNMASK){ - /* Enable all interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, MJDEC_REG_INT_NORMAL_EN); - tmpVal = BL_SET_REG_BIT(tmpVal,MJDEC_REG_INT_IDLE_EN); - }else{ - /* Disable all interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, MJDEC_REG_INT_NORMAL_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal,MJDEC_REG_INT_IDLE_EN); - } - break; - - default: - break; - } - BL_WR_REG(MJDEC_BASE,MJDEC_JDEC_CONTROL_3,tmpVal); -} - -/****************************************************************************//** - * @brief MJDEC Interrupt Clear - * - * @param intType: MJDEC Interrupt Type - * - * @return None - * -*******************************************************************************/ -void MJDEC_IntClr(MJDEC_INT_Type intType) -{ - uint32_t tmpVal; - - CHECK_PARAM(IS_MJDEC_INT_TYPE(intType)); - - tmpVal = BL_RD_REG(MJDEC_BASE,MJDEC_JDEC_INT_CLR); - switch(intType) - { - case MJDEC_INT_NORMAL: - tmpVal = BL_SET_REG_BIT(tmpVal,MJDEC_REG_INT_CLR); - break; - case MJDEC_INT_BACK_IDLE: - tmpVal = BL_SET_REG_BIT(tmpVal,MJDEC_REG_INT_CLR); - break; - case MJDEC_INT_ALL: - tmpVal = 0x1; - default: - break; - } - BL_WR_REG(MJDEC_BASE,MJDEC_JDEC_INT_CLR,tmpVal); -} - -/****************************************************************************//** - * @brief Install mjdec interrupt callback function - * - * @param intType: MJDEC interrupt type - * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void MJDEC_Int_Callback_Install(MJDEC_INT_Type intType,intCallback_Type* cbFun) -{ - /* Check the parameters */ - CHECK_PARAM(IS_MJDEC_INT_TYPE(intType)); - - mjdecIntCbfArra[intType] = cbFun; -} -#endif - -/****************************************************************************//** - * @brief Mjdec interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void MJDEC_IRQHandler(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(MJDEC_BASE,MJDEC_JDEC_CONTROL_3); - BL_WR_REG(MJDEC_BASE,MJDEC_JDEC_INT_CLR, 0x1); - if( BL_IS_REG_BIT_SET(tmpVal, MJDEC_STS_NORMAL_INT) ){ - // BL_WR_REG(MJDEC_BASE,MJDEC_JDEC_INT_CLR, 0x1); - if(mjdecIntCbfArra[MJDEC_INT_NORMAL] != NULL) { - /* call the callback function */ - mjdecIntCbfArra[MJDEC_INT_NORMAL](); - } - } - if( BL_IS_REG_BIT_SET(tmpVal, MJDEC_STS_IDLE_INT) ){ - // BL_WR_REG(MJDEC_BASE,MJDEC_JDEC_INT_CLR, 0x1); - if(mjdecIntCbfArra[MJDEC_INT_BACK_IDLE] != NULL) { - /* call the callback function */ - mjdecIntCbfArra[MJDEC_INT_BACK_IDLE](); - } - } -} -#endif - - -/*@} end of group MJDEC_Public_Functions */ - -/*@} end of group MJDEC */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mjpeg.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mjpeg.c deleted file mode 100644 index b41bc29a78..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mjpeg.c +++ /dev/null @@ -1,1006 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_mjpeg.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808.h" -#include "bl808_mjpeg.h" -#include "bl808_glb.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup MJPEG - * @{ - */ - -/** @defgroup MJPEG_Private_Macros - * @{ - */ - -/*@} end of group MJPEG_Private_Macros */ - -/** @defgroup MJPEG_Private_Types - * @{ - */ - -/*@} end of group MJPEG_Private_Types */ - -/** @defgroup MJPEG_Private_Variables - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -static intCallback_Type *mjpegIntCbfArra[MJPEG_INT_ALL] = { NULL }; -#endif - -/*@} end of group MJPEG_Private_Variables */ - -/** @defgroup MJPEG_Global_Variables - * @{ - */ - -/*@} end of group MJPEG_Global_Variables */ - -/** @defgroup MJPEG_Private_Fun_Declaration - * @{ - */ - -/*@} end of group MJPEG_Private_Fun_Declaration */ - -/** @defgroup MJPEG_Private_Functions - * @{ - */ - -/*@} end of group MJPEG_Private_Functions */ - -/** @defgroup MJPEG_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Mjpeg module init - * - * @param cfg: Mjpeg configuration structure pointer - * - * @return None - * -*******************************************************************************/ -void MJPEG_Init(MJPEG_CFG_Type *cfg) -{ - uint32_t tmpVal; - - /* Disable clock gate */ - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_MJPEG); - - /* disable mjpeg */ - tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_1); - tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_MJPEG_ENABLE); - BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_1, tmpVal); - - /* basic configure */ - tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_MJPEG_HW_FRAME, cfg->frameCount); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_YUV_MODE, cfg->yuv); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_W_XLEN, cfg->burst); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_MJPEG_BIT_ORDER, cfg->bitOrderEnable); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_ORDER_U_EVEN, cfg->evenOrderEnable); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_READ_FWRAP, cfg->readStartEnable); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_REFLECT_DMY, cfg->reflectDmy); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_LAST_HF_HBLK_DMY, cfg->verticalDmy); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_LAST_HF_WBLK_DMY, cfg->horizationalDmy); - BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_1, tmpVal); - - tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_MJPEG_WAIT_CYCLE, cfg->waitCount); - BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_2, tmpVal); - - tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_FRAME_SIZE); - - switch (cfg->yuv) { - case MJPEG_YUV422_INTERLEAVE: - case MJPEG_YUV422_PLANAR: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_FRAME_WBLK, (cfg->resolutionX + 15) >> 4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_FRAME_HBLK, (cfg->resolutionY + 7) >> 3); - break; - - case MJPEG_YUV420: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_FRAME_WBLK, (cfg->resolutionX + 15) >> 4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_FRAME_HBLK, (cfg->resolutionY + 15) >> 4); - break; - - case MJPEG_YUV400: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_FRAME_WBLK, (cfg->resolutionX + 7) >> 3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_FRAME_HBLK, (cfg->resolutionY + 7) >> 3); - break; - - default: - break; - } - - BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_SIZE, tmpVal); - - tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_SWAP_MODE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_W_SWAP_MODE, cfg->swapModeEnable); - BL_WR_REG(MJPEG_BASE, MJPEG_SWAP_MODE, tmpVal); - - /*align buffer to 16 bytes boundary, should be kept the same as CAM module*/ - BL_WR_REG(MJPEG_BASE, MJPEG_YY_FRAME_ADDR, (cfg->bufferCamYY & 0xFFFFFFF0)); - BL_WR_REG(MJPEG_BASE, MJPEG_UV_FRAME_ADDR, (cfg->bufferCamUV & 0xFFFFFFF0)); - BL_WR_REG(MJPEG_BASE, MJPEG_YUV_MEM, (cfg->sizeCamUV << 16) + cfg->sizeCamYY); - - /*align buffer to 16 bytes boundary*/ - BL_WR_REG(MJPEG_BASE, MJPEG_JPEG_FRAME_ADDR, (cfg->bufferMjpeg & 0xFFFFFFF0)); - - /*Set memory brust size */ - if (cfg->burst == MJPEG_BURST_SINGLE) { - BL_WR_REG(MJPEG_BASE, MJPEG_JPEG_STORE_MEMORY, cfg->sizeMjpeg / 8); - } else if (cfg->burst == MJPEG_BURST_INCR4) { - BL_WR_REG(MJPEG_BASE, MJPEG_JPEG_STORE_MEMORY, cfg->sizeMjpeg / 32); - } else if (cfg->burst == MJPEG_BURST_INCR8) { - BL_WR_REG(MJPEG_BASE, MJPEG_JPEG_STORE_MEMORY, cfg->sizeMjpeg / 64); - } else if (cfg->burst == MJPEG_BURST_INCR16) { - BL_WR_REG(MJPEG_BASE, MJPEG_JPEG_STORE_MEMORY, cfg->sizeMjpeg / 128); - } - - /* Clear interrupt */ - BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 0x3F00); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(MJPEG_IRQn, MJPEG_IRQHandler); -#endif -} - -/****************************************************************************/ /** - * @brief Mjpeg set YUYV order, only work in interleave mode - * - * @param y0: Y0 order - * @param u0: U0 order - * @param y1: Y1 order - * @param v0: V0 order - * - * @return None - * -*******************************************************************************/ -void MJPEG_Set_YUYV_Order_Interleave(uint8_t y0, uint8_t u0, uint8_t y1, uint8_t v0) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_HEADER_BYTE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_Y0_ORDER, y0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_U0_ORDER, u0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_Y1_ORDER, y1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_V0_ORDER, v0); - BL_WR_REG(MJPEG_BASE, MJPEG_HEADER_BYTE, tmpVal); -} - -/****************************************************************************/ /** - * @brief Mjpeg set Y/UV input cam id, only work in planar mode - * - * @param yCamId: Cam id of Y used - * @param uvCamId: Cam id of UV used - * - * @return None - * -*******************************************************************************/ -void MJPEG_Set_Planar_Y_UV_Input(uint8_t yCamId, uint8_t uvCamId) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_YY_DVP2AXI_SEL, yCamId); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_UV_DVP2AXI_SEL, uvCamId); - BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_2, tmpVal); -} - -/****************************************************************************/ /** - * @brief Deinit mjpeg module - * - * @param None - * - * @return None - * -*******************************************************************************/ -void MJPEG_Deinit(void) -{ - GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_MJPEG); -} - -/****************************************************************************/ /** - * @brief Enable mjpeg module - * - * @param None - * - * @return None - * -*******************************************************************************/ -void MJPEG_Enable(void) -{ - uint32_t tmpVal; - - /* Enable mjpeg module */ - tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_1); - tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_MJPEG_ENABLE); - BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_1, tmpVal); -} - -/****************************************************************************/ /** - * @brief Disable mjpeg module - * - * @param None - * - * @return None - * -*******************************************************************************/ -void MJPEG_Disable(void) -{ - uint32_t tmpVal; - - /* Disable mjpeg module */ - tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_1); - tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_MJPEG_ENABLE); - BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_1, tmpVal); -} - -/****************************************************************************/ /** - * @brief Enable&disable mjpeg software mode and set frame count - * - * @param swType: SW mode type - * @param count: Frame count - * - * @return None - * -*******************************************************************************/ -void MJPEG_SW_Enable(MJPEG_SW_Mode_Type swType, uint8_t count) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_SW_FRAME, count); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_SW_KICK_MODE, swType); - BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_2, tmpVal); - tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_MJPEG_SW_MODE); - BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_2, tmpVal); - tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_MJPEG_SW_MODE); - BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_2, tmpVal); -} - -/****************************************************************************/ /** - * @brief MJPEG software mode run, software mode enable first - * - * @param None - * - * @return None - * -*******************************************************************************/ -void MJPEG_SW_Run(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_2); - tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_MJPEG_SW_RUN); - BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_2, tmpVal); - tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_MJPEG_SW_RUN); - BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_2, tmpVal); -} - -/****************************************************************************/ /** - * @brief Set memory to store block line for frame on SW kick - * - * @param count: Block line count - * - * @return None - * -*******************************************************************************/ -void MJPEG_SW_Set_Kick_Block(uint16_t count) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_YUV_MEM_SW); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_SW_KICK_HBLK, count); - BL_WR_REG(MJPEG_BASE, MJPEG_YUV_MEM_SW, tmpVal); -} - -/****************************************************************************/ /** - * @brief MJPEG SW mode kick once - * - * @param None - * - * @return None - * -*******************************************************************************/ -void MJPEG_SW_Kick(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_2); - tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_SW_KICK); - BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_2, tmpVal); -} - -/****************************************************************************/ /** - * @brief Get one mjpeg frame - * - * @param info: Mjpeg frame infomation pointer - * - * @return None - * -*******************************************************************************/ -void MJPEG_Get_Frame_Info(MJPEG_Frame_Info *info) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_3); - - info->validFrames = BL_GET_REG_BITS_VAL(tmpVal, MJPEG_FRAME_VALID_CNT); - info->curFrameId = BL_GET_REG_BITS_VAL(BL_RD_REG(MJPEG_BASE, MJPEG_FRAME_ID_10), MJPEG_FRAME_ID_0); - info->curFrameAddr = BL_RD_REG(MJPEG_BASE, MJPEG_START_ADDR0); - info->curFrameBytes = (BL_RD_REG(MJPEG_BASE, MJPEG_BIT_CNT0) + 7) >> 3; - info->status = tmpVal; -} - -/****************************************************************************/ /** - * @brief Get available count of frames - * - * @param None - * - * @return Frames count - * -*******************************************************************************/ -uint8_t MJPEG_Get_Frame_Count(void) -{ - return BL_GET_REG_BITS_VAL(BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_3), MJPEG_FRAME_VALID_CNT); -} - -/****************************************************************************/ /** - * @brief Pop one mjpeg frame - * - * @param None - * - * @return None - * -*******************************************************************************/ -void MJPEG_Pop_Frame(void) -{ - BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 1); -} - -/****************************************************************************/ /** - * @brief Free current read memory block - * - * @param None - * - * @return None - * -*******************************************************************************/ -void MJPEG_Current_Block_Clear(void) -{ - BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 0x2); -} - -/****************************************************************************/ /** - * @brief Current read memory block index - * - * @param None - * - * @return Block number - * -*******************************************************************************/ -MJPEG_Swap_Block_Type MJPEG_Get_Current_Block(void) -{ - return (MJPEG_Swap_Block_Type)BL_GET_REG_BITS_VAL(BL_RD_REG(MJPEG_BASE, MJPEG_SWAP_MODE), MJPEG_STS_READ_SWAP_IDX); -} - -/****************************************************************************/ /** - * @brief Get block status, full or not full - * - * @param block: Block number - * - * @return Block status - * -*******************************************************************************/ -BL_Sts_Type MJPEG_Block_Is_Full(MJPEG_Swap_Block_Type block) -{ - CHECK_PARAM(IS_MJPEG_SWAP_BLOCK_TYPE(block)); - - if (MJPEG_BLOCK_0 == block) { - return (BL_Sts_Type)BL_GET_REG_BITS_VAL(BL_RD_REG(MJPEG_BASE, MJPEG_SWAP_MODE), MJPEG_STS_SWAP0_FULL); - } else { - return (BL_Sts_Type)BL_GET_REG_BITS_VAL(BL_RD_REG(MJPEG_BASE, MJPEG_SWAP_MODE), MJPEG_STS_SWAP1_FULL); - } -} - -/****************************************************************************/ /** - * @brief Current read memory block is frame start - * - * @param None - * - * @return Set or reset - * -*******************************************************************************/ -BL_Sts_Type MJPEG_Current_Block_Is_Start(void) -{ - return (BL_Sts_Type)BL_GET_REG_BITS_VAL(BL_RD_REG(MJPEG_BASE, MJPEG_SWAP_MODE), MJPEG_STS_SWAP_FSTART); -} - -/****************************************************************************/ /** - * @brief Current read memory block is frame end - * - * @param None - * - * @return Set or reset - * -*******************************************************************************/ -BL_Sts_Type MJPEG_Current_Block_Is_End(void) -{ - return (BL_Sts_Type)BL_GET_REG_BITS_VAL(BL_RD_REG(MJPEG_BASE, MJPEG_SWAP_MODE), MJPEG_STS_SWAP_FEND); -} - -/****************************************************************************/ /** - * @brief Get frame remain bit count in last block, only valid when current read memory block is - * frame end - * - * @param None - * - * @return Bit count - * -*******************************************************************************/ -uint32_t MJPEG_Get_Remain_Bit(void) -{ - return BL_RD_REG(MJPEG_BASE, MJPEG_SWAP_BIT_CNT); -} - -/****************************************************************************/ /** - * @brief Set frame threshold to issue normal interrupt - * - * @param count: Frame threshold - * - * @return None - * -*******************************************************************************/ -void MJPEG_Set_Frame_Threshold(uint8_t count) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_FRAME_CNT_TRGR_INT, count); - BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_3, tmpVal); -} - -/****************************************************************************/ /** - * @brief Set bytes of frame head to preserve - * - * @param size: Bytes of head - * - * @return None - * -*******************************************************************************/ -void MJPEG_Frame_Head_Set_Size(uint16_t size) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_HEADER_BYTE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_HEAD_BYTE, size); - BL_WR_REG(MJPEG_BASE, MJPEG_HEADER_BYTE, tmpVal); -} - -/****************************************************************************/ /** - * @brief Enable or disable auto fill frame tail with 0xff and 0xd9 - * - * @param enable: Enable or disable - * - * @return None - * -*******************************************************************************/ -void MJPEG_Frame_Tail_Auto_Fill(BL_Fun_Type enable) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_HEADER_BYTE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_TAIL_EXP, enable); - BL_WR_REG(MJPEG_BASE, MJPEG_HEADER_BYTE, tmpVal); -} - -/****************************************************************************/ /** - * @brief Set parameter in Y quantize table according to index - * - * @param index: Q parameter index - * @param qParameter: Q parameter value - * - * @return None - * -*******************************************************************************/ -void MJPEG_Set_Quantize_Parameter_Y(uint8_t index, uint16_t qParameter) -{ - uint32_t tmpVal; - - if (index > 63) { - return; - } - - index = index % 8 * 8 + index / 8; - - tmpVal = 2048 / qParameter; - - if (20480 / qParameter % 10 > 4) { - tmpVal++; - } - - qParameter = tmpVal & 0xffff; - - tmpVal = BL_RD_WORD(MJPEG_BASE + MJPEG_Q_PARAM_00_OFFSET + (index >> 1) * 4); - BL_WR_WORD(MJPEG_BASE + MJPEG_Q_PARAM_00_OFFSET + (index >> 1) * 4, (tmpVal & 0xffff0000 >> 16 * (index % 2)) | qParameter << 16 * (index % 2)); -} - -/****************************************************************************/ /** - * @brief Set parameter in UV quantize table according to index - * - * @param index: Q parameter index - * @param qParameter: Q parameter value - * - * @return None - * -*******************************************************************************/ -void MJPEG_Set_Quantize_Parameter_UV(uint8_t index, uint16_t qParameter) -{ - uint32_t tmpVal; - - if (index > 63) { - return; - } - - index = index % 8 * 8 + index / 8; - - tmpVal = 2048 / qParameter; - - if (20480 / qParameter % 10 > 4) { - tmpVal++; - } - - qParameter = tmpVal & 0xffff; - - tmpVal = BL_RD_WORD(MJPEG_BASE + MJPEG_Q_PARAM_40_OFFSET + (index >> 1) * 4); - BL_WR_WORD(MJPEG_BASE + MJPEG_Q_PARAM_40_OFFSET + (index >> 1) * 4, (tmpVal & 0xffff0000 >> 16 * (index % 2)) | qParameter << 16 * (index % 2)); -} - -/****************************************************************************/ /** - * @brief Set Y quantize table - * - * @param qTable: Y table - * - * @return None - * -*******************************************************************************/ -void MJPEG_Set_Quantize_Table_Y(uint16_t *qTable) -{ - uint8_t i, j; - uint16_t tmpVal1; - uint16_t tmpVal2; - - for (i = 0; i < 8; i++) { - for (j = 0; j < 4; j++) { - tmpVal1 = 2048 / qTable[16 * j + i]; - tmpVal2 = 2048 / qTable[16 * j + i + 8]; - - if (20480 / qTable[16 * j + i] % 10 > 4) { - tmpVal1++; - } - - if (20480 / qTable[16 * j + i + 8] % 10 > 4) { - tmpVal2++; - } - - BL_WR_WORD(MJPEG_BASE + MJPEG_Q_PARAM_00_OFFSET + (i * 4 + j) * 4, tmpVal1 | tmpVal2 << 16); - } - } -} - -/****************************************************************************/ /** - * @brief Set UV quantize table - * - * @param qTable: UV table - * - * @return None - * -*******************************************************************************/ -void MJPEG_Set_Quantize_Table_UV(uint16_t *qTable) -{ - uint8_t i, j; - uint16_t tmpVal1; - uint16_t tmpVal2; - - for (i = 0; i < 8; i++) { - for (j = 0; j < 4; j++) { - tmpVal1 = 2048 / qTable[16 * j + i]; - tmpVal2 = 2048 / qTable[16 * j + i + 8]; - - if (20480 / qTable[16 * j + i] % 10 > 4) { - tmpVal1++; - } - - if (20480 / qTable[16 * j + i + 8] % 10 > 4) { - tmpVal2++; - } - - BL_WR_WORD(MJPEG_BASE + MJPEG_Q_PARAM_40_OFFSET + (i * 4 + j) * 4, tmpVal1 | tmpVal2 << 16); - } - } -} - -/****************************************************************************/ /** - * @brief Calculate quantize table according to input table and quality factor - * - * @param inputTable: Pointer of input table - * @param outputTable: Pointer of output table - * @param quality: Quality factor - * - * @return None - * -*******************************************************************************/ -void MJPEG_Calculate_Quantize_Table(uint16_t *inputTable, uint16_t *outputTable, uint8_t quality) -{ - uint32_t scaleFactor, i; - - if (quality == 0) { - quality = 1; - } else if (quality > 100) { - quality = 100; - } - - if (quality < 50) { - scaleFactor = 5000000 / quality; - } else { - scaleFactor = 200000 - quality * 2000; - } - - for (i = 0; i < 64; i++) { - outputTable[i] = (inputTable[i] * scaleFactor + 50000) / 100000; - - if (outputTable[i] == 0) { - outputTable[i] = 1; - } else if (outputTable[i] > 0xff) { - outputTable[i] = 0xff; - } - } -} - -/****************************************************************************/ /** - * @brief Quantize SRAM switch - * - * @param None - * - * @return None - * -*******************************************************************************/ -void MJPEG_Quantize_SRAM_Switch(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_Q_ENC); - tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_Q_SRAM_SW); - BL_WR_REG(MJPEG_BASE, MJPEG_Q_ENC, tmpVal); -} - -/****************************************************************************/ /** - * @brief Get current quantize SRAM selection for encode - * - * @param None - * - * @return Current quantize SRAM - * -*******************************************************************************/ -uint8_t MJPEG_Get_Current_Quantize_SRAM(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_Q_ENC); - return BL_GET_REG_BITS_VAL(tmpVal, MJPEG_STS_Q_SRAM_ENC); -} - -/****************************************************************************/ /** - * @brief Get frame0~3 quantize SRAM selection - * - * @param frameId: Frame id - * - * @return Quantize SRAM - * -*******************************************************************************/ -uint8_t MJPEG_Get_Frame_Quantize_SRAM(MJPEG_Frame_ID_Type frameId) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_Q_ENC); - return (tmpVal >> frameId & 1); -} - -/****************************************************************************/ /** - * @brief MJPEG Enable Disable Interrupt - * - * @param intType: MJPEG Interrupt Type - * @param intMask: Enable or Disable - * - * @return None - * -*******************************************************************************/ -void MJPEG_IntMask(MJPEG_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_MJPEG_INT_TYPE(intType)); - CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); - - tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_3); - - switch (intType) { - case MJPEG_INT_NORMAL: - if (intMask == UNMASK) { - /* Enable this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_NORMAL_EN); - } else { - /* Disable this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_NORMAL_EN); - } - - break; - - case MJPEG_INT_CAM_OVERWRITE: - if (intMask == UNMASK) { - /* Enable this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_CAM_EN); - } else { - /* Disable this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_CAM_EN); - } - - break; - - case MJPEG_INT_MEM_OVERWRITE: - if (intMask == UNMASK) { - /* Enable this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_MEM_EN); - } else { - /* Disable this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_MEM_EN); - } - - break; - - case MJPEG_INT_FRAME_OVERWRITE: - if (intMask == UNMASK) { - /* Enable this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_FRAME_EN); - } else { - /* Disable this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_FRAME_EN); - } - - break; - - case MJPEG_INT_BACK_IDLE: - if (intMask == UNMASK) { - /* Enable this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_IDLE_EN); - } else { - /* Disable this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_IDLE_EN); - } - - break; - - case MJPEG_INT_SWAP: - if (intMask == UNMASK) { - /* Enable this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_SWAP_EN); - } else { - /* Disable this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_SWAP_EN); - } - - break; - - case MJPEG_INT_ALL: - if (intMask == UNMASK) { - /* Enable all interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_NORMAL_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_CAM_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_MEM_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_FRAME_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_IDLE_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_SWAP_EN); - } else { - /* Disable all interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_NORMAL_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_CAM_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_MEM_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_FRAME_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_IDLE_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_SWAP_EN); - } - - break; - - default: - break; - } - - BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_3, tmpVal); -} - -/****************************************************************************/ /** - * @brief MJPEG Interrupt Clear - * - * @param intType: MJPEG Interrupt Type - * - * @return None - * -*******************************************************************************/ -void MJPEG_IntClr(MJPEG_INT_Type intType) -{ - uint32_t tmpVal; - - CHECK_PARAM(IS_MJPEG_INT_TYPE(intType)); - - tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP); - - switch (intType) { - case MJPEG_INT_NORMAL: - tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_NORMAL_CLR); - break; - - case MJPEG_INT_CAM_OVERWRITE: - tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_CAM_CLR); - break; - - case MJPEG_INT_MEM_OVERWRITE: - tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_MEM_CLR); - break; - - case MJPEG_INT_FRAME_OVERWRITE: - tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_FRAME_CLR); - break; - - case MJPEG_INT_BACK_IDLE: - tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_IDLE_CLR); - break; - - case MJPEG_INT_SWAP: - tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_SWAP_CLR); - break; - - case MJPEG_INT_ALL: - tmpVal = 0x3F00; - - default: - break; - } - - BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, tmpVal); -} - -/****************************************************************************/ /** - * @brief Install mjpeg interrupt callback function - * - * @param intType: MJPEG interrupt type - * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void MJPEG_Int_Callback_Install(MJPEG_INT_Type intType, intCallback_Type *cbFun) -{ - /* Check the parameters */ - CHECK_PARAM(IS_MJPEG_INT_TYPE(intType)); - - mjpegIntCbfArra[intType] = cbFun; -} -#endif - -/****************************************************************************/ /** - * @brief Mjpeg interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void MJPEG_IRQHandler(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_3); - - if (BL_IS_REG_BIT_SET(tmpVal, MJPEG_STS_NORMAL_INT)) { - BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 0x100); - - if (mjpegIntCbfArra[MJPEG_INT_NORMAL] != NULL) { - /* call the callback function */ - mjpegIntCbfArra[MJPEG_INT_NORMAL](); - } - } - - if (BL_IS_REG_BIT_SET(tmpVal, MJPEG_STS_CAM_INT)) { - BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 0x200); - - if (mjpegIntCbfArra[MJPEG_INT_CAM_OVERWRITE] != NULL) { - /* call the callback function */ - mjpegIntCbfArra[MJPEG_INT_CAM_OVERWRITE](); - } - } - - if (BL_IS_REG_BIT_SET(tmpVal, MJPEG_STS_MEM_INT)) { - BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 0x400); - - if (mjpegIntCbfArra[MJPEG_INT_MEM_OVERWRITE] != NULL) { - /* call the callback function */ - mjpegIntCbfArra[MJPEG_INT_MEM_OVERWRITE](); - } - } - - if (BL_IS_REG_BIT_SET(tmpVal, MJPEG_STS_FRAME_INT)) { - BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 0x800); - - if (mjpegIntCbfArra[MJPEG_INT_FRAME_OVERWRITE] != NULL) { - /* call the callback function */ - mjpegIntCbfArra[MJPEG_INT_FRAME_OVERWRITE](); - } - } - - if (BL_IS_REG_BIT_SET(tmpVal, MJPEG_STS_IDLE_INT)) { - BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 0x1000); - - if (mjpegIntCbfArra[MJPEG_INT_BACK_IDLE] != NULL) { - /* call the callback function */ - mjpegIntCbfArra[MJPEG_INT_BACK_IDLE](); - } - } - - if (BL_IS_REG_BIT_SET(tmpVal, MJPEG_STS_SWAP_INT)) { - BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 0x2000); - - if (mjpegIntCbfArra[MJPEG_INT_SWAP] != NULL) { - /* call the callback function */ - mjpegIntCbfArra[MJPEG_INT_SWAP](); - } - } -} -#endif - -/*@} end of group MJPEG_Public_Functions */ - -/*@} end of group MJPEG */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_osd_blend.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_osd_blend.c deleted file mode 100644 index 998c6dddab..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_osd_blend.c +++ /dev/null @@ -1,480 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_osd_blend.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2021 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_osd_blend.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup OSD_BLEND - * @{ - */ - -/** @defgroup OSD_BLEND_Private_Macros - * @{ - */ - -/*@} end of group OSD_BLEND_Private_Macros */ - -/** @defgroup OSD_BLEND_Private_Types - * @{ - */ - -/*@} end of group OSD_BLEND_Private_Types */ - -/** @defgroup OSD_BLEND_Private_Variables - * @{ - */ - -/*@} end of group OSD_BLEND_Private_Variables */ - -/** @defgroup OSD_BLEND_Global_Variables - * @{ - */ - -/*@} end of group OSD_BLEND_Global_Variables */ - -/** @defgroup OSD_BLEND_Private_Fun_Declaration - * @{ - */ - -/*@} end of group OSD_BLEND_Private_Fun_Declaration */ - -/** @defgroup OSD_BLEND_Private_Functions - * @{ - */ - -/*@} end of group OSD_BLEND_Private_Functions */ - -/** @defgroup OSD_BLEND_Public_Functions - * @{ - */ - -/****************************************************************************** - * @brief OSD blend layer configuration - * - * @param pblend: pointer to a specific OSD blend layer - * @param xstart: OSD layer start point: x-axis, better to be even. - * @param ystart: OSD layer start point: y-axis, better to be even. - * @param xend: OSD layer end point: x-axis, better to be odd. - * @param yend: OSD layer end point: y-axis, better to be odd. - * @param data: OSD layer data buffer pointer. - * @param dat_len: data length in dword size(8bytes). - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_blend_config_layer(osd_blend_reg_t *pblend, - uint32_t xstart, uint32_t ystart, - uint32_t xend, uint32_t yend, - uintptr_t *data, uint32_t dat_len) -{ - pblend->obnd_layer_xconfig.WORD = (xstart & OSD_BLEND_OBND_X_MIN_MSK) | - ((xend << OSD_BLEND_OBND_X_MAX_POS) & OSD_BLEND_OBND_X_MAX_MSK); - pblend->obnd_layer_yconfig.WORD = (ystart & OSD_BLEND_OBND_Y_MIN_MSK) | - ((yend << OSD_BLEND_OBND_Y_MAX_POS) & OSD_BLEND_OBND_Y_MAX_MSK); - - pblend->obnd_mem_config1.WORD = (uint32_t)(uintptr_t)data; - pblend->obnd_mem_config2.WORD = dat_len; - - return SUCCESS; -} - -/****************************************************************************** - * @brief OSD blend layer mem access timing configuration - * - * @param pblend: pointer to a specific OSD blend layer - * @param req_hlen: memory access timing setting in H-SYNC cycles after V-SYNC. - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_blend_mem_access_line(osd_blend_reg_t *pblend, uint32_t req_hlen) -{ - pblend->obnd_sh.BF.obnd_layer_mem_req_cnt = req_hlen; - - return SUCCESS; -} - -/****************************************************************************** - * @brief OSD blend layer force shadow control: - * call this API before DSP2 streaming on to ensure the OSD layer - * is activated even in frame 0. - * After calling this API, this OSD blending layer has to be enabled. - * - * @param pblend: pointer to a specific OSD blend layer - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_blend_layer_early_commit(osd_blend_reg_t *pblend) -{ - uint32_t val = 0; - - val = pblend->obnd_mem_config0.WORD; - /* disable this layer */ - val &= OSD_BLEND_OBND_LAYER_EN_UMSK; - /* set OSD blend force shadow bit, so that the settings will be loaded - * immediately and mem access will be started after layer is enabled. - */ - val |= OSD_BLEND_OBND_FORCE_SH_MSK; - pblend->obnd_mem_config0.WORD = val; - - return SUCCESS; -} - -/****************************************************************************** - * @brief OSD blend layer enable/disable control - * - * @param pblend: pointer to a specific OSD blend layer - * @param enable: requested state of this blend layer. - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_blend_ctrl_layer(osd_blend_reg_t *pblend, OSD_BLEND_ST_e enable) -{ - uint32_t val = 0; - - val = pblend->obnd_mem_config0.WORD; - val &= OSD_BLEND_OBND_LAYER_EN_UMSK; - val |= (OSD_BLEND_ST_ENABLE == enable) ? OSD_BLEND_OBND_LAYER_EN_MSK : 0; - pblend->obnd_mem_config0.WORD = val; - - return SUCCESS; -} - -/****************************************************************************** - * @brief OSD blend layer color format configuration - * - * @param pblend: pointer to a specific OSD blend layer - * @param fmt: color format. - * @param order_alpha: order of the alpha. - * @param order_r_v: order of the red(RGB) or v(YUV). - * @param order_g_y: order of the green(RGB) or y(YUV). - * @param order_b_u: order of the blue(RGB) or u(YUV). - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_blend_set_color_format(osd_blend_reg_t *pblend, OSD_BLEND_COLOR_FMT_e fmt, - OSD_BLEND_COLOR_ORDER_e order_alpha, - OSD_BLEND_COLOR_ORDER_e order_r_v, - OSD_BLEND_COLOR_ORDER_e order_g_y, - OSD_BLEND_COLOR_ORDER_e order_b_u) -{ - uint32_t val = 0; - - val = pblend->obnd_layer_config0.WORD; - val &= ~(OSD_BLEND_OBND_COLOR_FORMAT_MSK | - OSD_BLEND_OBND_ORDER_A_MSK | - OSD_BLEND_OBND_ORDER_RV_MSK | - OSD_BLEND_OBND_ORDER_GY_MSK | - OSD_BLEND_OBND_ORDER_BU_MSK); - - val |= fmt << OSD_BLEND_OBND_COLOR_FORMAT_POS; - val |= order_alpha << OSD_BLEND_OBND_ORDER_A_POS; - val |= order_r_v << OSD_BLEND_OBND_ORDER_RV_POS; - val |= order_g_y << OSD_BLEND_OBND_ORDER_GY_POS; - val |= order_b_u << OSD_BLEND_OBND_ORDER_BU_POS; - - pblend->obnd_layer_config0.WORD = val; - - return SUCCESS; -} - -/****************************************************************************** - * @brief OSD blend layer global alpha configuration - * - * @param pblend: pointer to a specific OSD blend layer - * @param enable: enable or disable the global alpha for this layer. - * @param alpha: value of the alpha. - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_blend_set_global_alpha(osd_blend_reg_t *pblend, uint32_t enable, - uint8_t alpha) -{ - uint32_t val = 0; - - val = pblend->obnd_layer_config0.WORD; - val &= OSD_BLEND_OBND_GLOBAL_A_UMSK; - val &= OSD_BLEND_OBND_GLOBAL_A_EN_UMSK; - val |= (alpha << OSD_BLEND_OBND_GLOBAL_A_POS) & OSD_BLEND_OBND_GLOBAL_A_MSK; - val |= (OSD_BLEND_ST_ENABLE == enable) ? OSD_BLEND_OBND_GLOBAL_A_EN_MSK : 0; - pblend->obnd_layer_config0.WORD = val; - return SUCCESS; -} - -/****************************************************************************** - * @brief OSD blend layer global color configuration - * - * @param pblend: pointer to a specific OSD blend layer - * @param enable: enable or disable the global color for this layer. - * @param r_v: value of the red(RGB) or v(YUV). - * @param g_y: value of the green(RGB) or y(YUV). - * @param b_u: value of the blue(RGB) or u(YUV). - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_blend_set_global_color(osd_blend_reg_t *pblend, uint32_t enable, - uint8_t r_v, uint8_t g_y, uint8_t b_u) -{ - uint32_t val = 0; - - val = (OSD_BLEND_ST_ENABLE == enable) ? OSD_BLEND_OBND_GLOBAL_COLOR_EN_MSK : 0; - val |= (r_v << OSD_BLEND_OBND_GLOBAL_RV_POS) & OSD_BLEND_OBND_GLOBAL_RV_MSK; - val |= (g_y << OSD_BLEND_OBND_GLOBAL_GY_POS) & OSD_BLEND_OBND_GLOBAL_GY_MSK; - val |= (b_u << OSD_BLEND_OBND_GLOBAL_BU_POS) & OSD_BLEND_OBND_GLOBAL_BU_MSK; - pblend->obnd_layer_config1.WORD = val; - - return SUCCESS; -} - -/****************************************************************************** - * @brief OSD blend layer update palette value according to the index. - * - * @param pblend: pointer to a specific OSD blend layer - * @param color: palette color, can be format ARGB8888 or AYUV8888. - * @param index: the palette index for updating. - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_blend_update_palette(osd_blend_reg_t *pblend, uint32_t color, uint8_t index) -{ - uint32_t val = 0; - - /* palette should be updated when blend is disabled. */ - - pblend->obnd_layer_config7.WORD = color; - val = pblend->obnd_layer_config6.WORD; - val &= OSD_BLEND_OBND_UPDATE_INDEX_UMSK; - val |= index << OSD_BLEND_OBND_UPDATE_INDEX_POS; - - /* trigger update */ - val |= OSD_BLEND_OBND_UPDATE_TRIGGER_MSK; - pblend->obnd_layer_config6.WORD = val; - arch_delay_us(1); - - return SUCCESS; -} - -/****************************************************************************** - * @brief OSD blend layer palette keying control. - * - * @param pblend: pointer to a specific OSD blend layer - * @param enable: enable or disable the palette keying for this layer. - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_blend_palette_keying_ctrl(osd_blend_reg_t *pblend, OSD_BLEND_ST_e enable) -{ - uint32_t val = 0; - - val = pblend->obnd_layer_config2.WORD; - val &= OSD_BLEND_OBND_KEY_PALETTE_EN_UMSK; - - val |= (OSD_BLEND_ST_ENABLE == enable) ? OSD_BLEND_OBND_KEY_PALETTE_EN_MSK : 0; - - pblend->obnd_layer_config2.WORD = val; - return SUCCESS; -} - -/****************************************************************************** - * @brief OSD blend layer palette keying configuration. - * - * @param pblend: pointer to a specific OSD blend layer - * @param enable: enable or disable the palette keying for this layer. - * @param mode: palette keying mode: within or out of the min/max range. - * @param replace_index: the palette index that will be used as the replace color. - * @param min_key_index: min index for the palette keying. - * @param max_key_index: max index for the palette keying. - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_blend_palette_keying(osd_blend_reg_t *pblend, OSD_BLEND_ST_e enable, - OSB_BLEND_KEYING_MODE_e mode, - uint8_t replace_index, - uint8_t min_key_index, uint8_t max_key_index) -{ - uint32_t val = 0; - - /* disable palette keying */ - val = pblend->obnd_layer_config2.WORD; - val &= OSD_BLEND_OBND_KEY_PALETTE_EN_UMSK; - pblend->obnd_layer_config2.WORD = val; - - /* it is done if palette keying mode is disabled */ - if (OSD_BLEND_ST_ENABLE != enable) { - return SUCCESS; - } - - val |= (OSD_BLEND_ST_ENABLE == enable) ? OSD_BLEND_OBND_KEY_PALETTE_EN_MSK : 0; - val |= (OSB_BLEND_KEYING_INVERT == mode) ? OSD_BLEND_OBND_KEY_INDEX_INV_MSK : 0; - val |= (min_key_index << OSD_BLEND_OBND_KEY_INDEX_MIN_POS) & OSD_BLEND_OBND_KEY_INDEX_MIN_MSK; - val |= (max_key_index << OSD_BLEND_OBND_KEY_INDEX_MAX_POS) & OSD_BLEND_OBND_KEY_INDEX_MAX_MSK; - val |= (replace_index << OSD_BLEND_OBND_KEY_REPLACE_INDEX_POS) & - OSD_BLEND_OBND_KEY_REPLACE_INDEX_MSK; - - pblend->obnd_layer_config2.WORD = val; - - return SUCCESS; -} - -/****************************************************************************** - * @brief OSD blend layer palette keying min/max updating control. - * - * @param pblend: pointer to a specific OSD blend layer - * @param min_key_index: min index for the palette keying. - * @param max_key_index: max index for the palette keying. - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_blend_palette_keying_update_range(osd_blend_reg_t *pblend, - uint8_t min_key_index, uint8_t max_key_index) -{ - uint32_t val = 0; - - val = pblend->obnd_layer_config2.WORD; - - val &= OSD_BLEND_OBND_KEY_INDEX_MIN_UMSK; - val &= OSD_BLEND_OBND_KEY_INDEX_MAX_UMSK; - val |= (min_key_index << OSD_BLEND_OBND_KEY_INDEX_MIN_POS) & OSD_BLEND_OBND_KEY_INDEX_MIN_MSK; - val |= (max_key_index << OSD_BLEND_OBND_KEY_INDEX_MAX_POS) & OSD_BLEND_OBND_KEY_INDEX_MAX_MSK; - - pblend->obnd_layer_config2.WORD = val; - - return SUCCESS; -} - -/****************************************************************************** - * @brief OSD blend layer color keying configuration. - * - * @param pblend: pointer to a specific OSD blend layer - * @param enable: enable or disable the color keying for this layer. - * @param pset: point to the color keying setting. - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_blend_color_keying(osd_blend_reg_t *pblend, OSD_BLEND_ST_e enable, - osd_blend_color_keying_set_t *pset) -{ - uint32_t val = 0; - - CHECK_PARAM(NULL != pset); - - /* disable color keying */ - val = pblend->obnd_layer_config6.WORD; - val &= OSD_BLEND_OBND_KEY_COLOR_EN_UMSK; - pblend->obnd_layer_config6.WORD = val; - - /* it is done if color keying mode is disabled */ - if (OSD_BLEND_ST_ENABLE != enable) { - return SUCCESS; - } - - /* layer_config3: min & max for alpha and rv */ - val = pset->min_key_alpha << OSD_BLEND_OBND_KEY_A_MIN_POS; - val |= pset->max_key_alpha << OSD_BLEND_OBND_KEY_A_MAX_POS; - val |= pset->min_key_rv << OSD_BLEND_OBND_KEY_RV_MIN_POS; - val |= pset->max_key_rv << OSD_BLEND_OBND_KEY_RV_MAX_POS; - pblend->obnd_layer_config3.WORD = val; - - /* layer_config4: min & max for gy and bu */ - val = pset->min_key_gy << OSD_BLEND_OBND_KEY_GY_MIN_POS; - val |= pset->max_key_gy << OSD_BLEND_OBND_KEY_GY_MAX_POS; - val |= pset->min_key_bu << OSD_BLEND_OBND_KEY_BU_MIN_POS; - val |= pset->max_key_bu << OSD_BLEND_OBND_KEY_BU_MAX_POS; - pblend->obnd_layer_config4.WORD = val; - - /* layer_config5: replace color */ - val = pset->replace_alpha << OSD_BLEND_OBND_KEY_REPLACE_A_POS; - val |= pset->replace_rv << OSD_BLEND_OBND_KEY_REPLACE_RV_POS; - val |= pset->replace_gy << OSD_BLEND_OBND_KEY_REPLACE_GY_POS; - val |= pset->replace_bu << OSD_BLEND_OBND_KEY_REPLACE_BU_POS; - pblend->obnd_layer_config5.WORD = val; - - /* color range inverted? */ - val = pblend->obnd_layer_config6.WORD; - val &= ~(OSD_BLEND_OBND_KEY_A_INV_MSK | - OSD_BLEND_OBND_KEY_RV_INV_MSK | - OSD_BLEND_OBND_KEY_GY_INV_MSK | - OSD_BLEND_OBND_KEY_BU_INV_MSK); - val |= (OSB_BLEND_KEYING_INVERT == pset->mode_alpha) ? - OSD_BLEND_OBND_KEY_A_INV_MSK : - 0; - val |= (OSB_BLEND_KEYING_INVERT == pset->mode_rv) ? - OSD_BLEND_OBND_KEY_RV_INV_MSK : - 0; - val |= (OSB_BLEND_KEYING_INVERT == pset->mode_gy) ? - OSD_BLEND_OBND_KEY_GY_INV_MSK : - 0; - val |= (OSB_BLEND_KEYING_INVERT == pset->mode_bu) ? - OSD_BLEND_OBND_KEY_BU_INV_MSK : - 0; - - /* enable color keying */ - val |= OSD_BLEND_OBND_KEY_COLOR_EN_MSK; - pblend->obnd_layer_config6.WORD = val; - - return SUCCESS; -} - -/*@} end of group OSD_BLEND_Public_Functions */ - -/*@} end of group OSD_BLEND */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_osd_draw.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_osd_draw.c deleted file mode 100644 index 9e0e42c969..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_osd_draw.c +++ /dev/null @@ -1,335 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_osd_blend.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2021 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_osd_draw.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup OSD_DRAW - * @{ - */ - -/** @defgroup OSD_DRAW_Private_Macros - * @{ - */ - -/*@} end of group OSD_DRAW_Private_Macros */ - -/** @defgroup OSD_DRAW_Private_Types - * @{ - */ - -/*@} end of group OSD_DRAW_Private_Types */ - -/** @defgroup OSD_DRAW_Private_Variables - * @{ - */ - -/*@} end of group OSD_DRAW_Private_Variables */ - -/** @defgroup OSD_DRAW_Global_Variables - * @{ - */ - -/*@} end of group OSD_DRAW_Global_Variables */ - -/** @defgroup OSD_DRAW_Private_Fun_Declaration - * @{ - */ - -/*@} end of group OSD_DRAW_Private_Fun_Declaration */ - -/** @defgroup OSD_DRAW_Private_Functions - * @{ - */ - -/*@} end of group OSD_DRAW_Private_Functions */ - -/** @defgroup OSD_DRAW_Public_Functions - * @{ - */ - -/****************************************************************************** - * @brief OSD draw layer state control - * - * @param odraw: pointer to a specific OSD draw HW IP. - * @param layer: draw layer. - * @param state: enable or disable the layer in this draw HW IP. - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_draw_set_layer_state(osd_draw_reg_t *odraw, uint32_t layer, OSD_RECT_STATE_Type state) -{ - uint32_t tmpval = 0; - uint32_t layer_mask = 1 << OSD_VALID_LAYER(layer); - - tmpval = odraw->osd_draw_config.WORD; - - if (state == OSD_RECT_STATE_ENABLE) { - tmpval |= layer_mask; - } else { - tmpval &= ~layer_mask; - } - - odraw->osd_draw_config.WORD = tmpval; - return SUCCESS; -} - -/****************************************************************************** - * @brief OSD draw layer state get - * - * @param odraw: pointer to a specific OSD draw HW IP. - * @param layer: draw layer. - * @param state: pointer to return the state value. - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_draw_get_layer_state(osd_draw_reg_t *odraw, uint32_t layer, OSD_RECT_STATE_Type *state) -{ - uint32_t tmpval = 0; - uint32_t layer_mask = 1 << OSD_VALID_LAYER(layer); - - CHECK_PARAM(NULL != odraw); - CHECK_PARAM(NULL != state); - - tmpval = odraw->osd_draw_config.WORD; - tmpval &= layer_mask; - *state = (!!tmpval) ? OSD_RECT_STATE_ENABLE : OSD_RECT_STATE_DISABLE; - - return SUCCESS; -} - -/****************************************************************************** - * @brief OSD draw layer style set - * - * @param odraw: pointer to a specific OSD draw HW IP. - * @param layer: draw layer. - * @param style: solid or hollow style. - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_draw_set_layer_style(osd_draw_reg_t *odraw, uint32_t layer, OSD_RECT_STYLE_Type style) -{ - uint32_t tmpval = 0; - uint32_t layer_mask = 1 << OSD_VALID_LAYER(layer); - - if (style == OSD_RECT_STYLE_SOLID) { - tmpval |= layer_mask << OSD_REG_DRAW_TYPE_L_POS; - } else { - tmpval &= ~(layer_mask << OSD_REG_DRAW_TYPE_L_POS); - } - - odraw->osd_draw_config.WORD = tmpval; - return SUCCESS; -} - -/****************************************************************************** - * @brief OSD draw layer style get - * - * @param odraw: pointer to a specific OSD draw HW IP. - * @param layer: draw layer. - * @param style: pointer to return the solid or hollow style. - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_draw_get_layer_style(osd_draw_reg_t *odraw, uint32_t layer, OSD_RECT_STYLE_Type *style) -{ - uint32_t tmpval = 0; - uint32_t layer_mask = 1 << OSD_VALID_LAYER(layer); - - CHECK_PARAM(NULL != odraw); - CHECK_PARAM(NULL != style); - - tmpval = odraw->osd_draw_config.WORD; - tmpval &= layer_mask << OSD_REG_DRAW_TYPE_L_POS; - *style = (!!tmpval) ? OSD_RECT_STYLE_SOLID : OSD_RECT_STYLE_HOLLOW; - - return SUCCESS; -} - -/****************************************************************************** - * @brief OSD draw layer control - * - * @param odraw: pointer to a specific OSD draw HW IP. - * @param layer: draw layer. - * @param state: enable or disable this draw layer. - * @param style: solid or hollow style for this layer. - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_draw_config_rect_layer(osd_draw_reg_t *odraw, uint32_t layer, OSD_RECT_STATE_Type state, OSD_RECT_STYLE_Type style) -{ - uint32_t tmpval = 0; - uint32_t layer_mask = 1 << OSD_VALID_LAYER(layer); - - tmpval = odraw->osd_draw_config.WORD; - - if (state == OSD_RECT_STATE_ENABLE) { - tmpval |= layer_mask; - } else { - tmpval &= ~layer_mask; - } - - if (style == OSD_RECT_STYLE_SOLID) { - tmpval |= layer_mask << OSD_REG_DRAW_TYPE_L_POS; - } else { - tmpval &= ~(layer_mask << OSD_REG_DRAW_TYPE_L_POS); - } - - odraw->osd_draw_config.WORD = tmpval; - return SUCCESS; -} - -/****************************************************************************** - * @brief Draw a specific rectangle with OSD draw HW IP. - * - * @param odraw: pointer to a specific OSD draw HW IP. - * @param rect: pointer to a rectangle setting structure. - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_draw_rectangle(osd_draw_reg_t *odraw, osd_rectangle_t *rect) -{ - osd_rectangle_desc_t *desc = OSD_RECT_DESC((odraw), OSD_VALID_LAYER(rect->layer)); - - CHECK_PARAM(NULL != odraw); - CHECK_PARAM(NULL != rect); - - osd_draw_set_layer_state(odraw, rect->layer, OSD_RECT_STATE_DISABLE); - desc->attr = rect->desc.attr; - - /* EVEN and ODD */ - rect->desc.pos.x.start &= -2; - rect->desc.pos.x.end |= 1; - rect->desc.pos.y.start &= -2; - rect->desc.pos.y.end |= 1; - rect->desc.attr.yuvt.thinkness += (rect->desc.attr.yuvt.thinkness & 1) ? 1 : 0; - - desc->pos.x = rect->desc.pos.x; - desc->pos.y = rect->desc.pos.y; - osd_draw_config_rect_layer(odraw, rect->layer, OSD_RECT_STATE_ENABLE, rect->style); - - return SUCCESS; -} - -/****************************************************************************** - * @brief Draw a specific rectangle with OSD draw HW IP on the top if possible. - * - * @param odraw: pointer to a specific OSD draw HW IP. - * @param rect: pointer to a rectangle setting structure. - * @param layer: pointer to return the current drawing layer. - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_draw_rectangle_onTop(osd_draw_reg_t *odraw, osd_rectangle_t *rect, uint32_t *layer) -{ - uint32_t tmpval = 0; - uint32_t draw_layer = 0; - - CHECK_PARAM(NULL != layer); - CHECK_PARAM(NULL != rect); - - tmpval = odraw->osd_draw_config.WORD; - tmpval &= 0x0000FFFF; - - tmpval = __CLZ(tmpval); - - if (OSD_MAX_LAYER == tmpval) { - /* no available TOP layer since all layers used */ - *layer = (uint32_t)-1; - return NORESC; - } - - draw_layer = sizeof(uintptr_t) * 8 - tmpval; - - rect->layer = draw_layer; - *layer = draw_layer; - osd_draw_rectangle(odraw, rect); - - return SUCCESS; -} - -/****************************************************************************** - * @brief Init the OSD draw HW IP. - * - * @param odraw: pointer to a specific OSD draw HW IP. - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_draw_init(osd_draw_reg_t *odraw) -{ - odraw->osd_draw_config.WORD = 0; - return SUCCESS; -} - -/****************************************************************************** - * @brief DeInit the OSD draw HW IP. - * - * @param odraw: pointer to a specific OSD draw HW IP. - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_draw_deinit(osd_draw_reg_t *odraw) -{ - odraw->osd_draw_config.WORD = 0; - return SUCCESS; -} - -/*@} end of group OSD_DRAW_Public_Functions */ - -/*@} end of group OSD_DRAW */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_osd_probe.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_osd_probe.c deleted file mode 100644 index ecf59a9814..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_osd_probe.c +++ /dev/null @@ -1,245 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_osd_probe.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2021 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_osd_probe.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup OSD_PROBE - * @{ - */ - -/** @defgroup OSD_PROBE_Private_Macros - * @{ - */ - -/*@} end of group OSD_PROBE_Private_Macros */ - -/** @defgroup OSD_PROBE_Private_Types - * @{ - */ - -/*@} end of group OSD_PROBE_Private_Types */ - -/** @defgroup OSD_PROBE_Private_Variables - * @{ - */ - -/*@} end of group OSD_PROBE_Private_Variables */ - -/** @defgroup OSD_PROBE_Global_Variables - * @{ - */ - -/*@} end of group OSD_PROBE_Global_Variables */ - -/** @defgroup OSD_PROBE_Private_Fun_Declaration - * @{ - */ - -/*@} end of group OSD_PROBE_Private_Fun_Declaration */ - -/** @defgroup OSD_PROBE_Private_Functions - * @{ - */ - -/*@} end of group OSD_PROBE_Private_Functions */ - -/** @defgroup OSD_PROBE_Public_Functions - * @{ - */ - -/****************************************************************************** - * @brief OSD probe setup one detect point - * - * @param index: point index in probe. - * @param x: point x-axis. - * @param y: point y-axis. - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_probe_set_addr(uintptr_t index, uintptr_t x, uintptr_t y) -{ - uint32_t addr = 0; - - addr = ((y << OSD_PB_REG_OSD_PB_Y_00_POS) & OSD_PB_REG_OSD_PB_Y_00_MSK) | (x & OSD_PB_REG_OSD_PB_X_00_MSK); - - if (index < OSD_PROBE_ADDR_MAX_INDEX) { - BL_WR_WORD(OSD_PROBE_BASE + OSD_PB_ADDR_00_OFFSET + index * sizeof(uint32_t), addr); - return SUCCESS; - } else { - return INVALID; - } -} - -/****************************************************************************** - * @brief OSD probe get info of one detect point - * - * @param index: point index in probe. - * @param x: return the value of point x-axis. - * @param y: return the value of point y-axis. - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_probe_get_addr(uintptr_t index, uintptr_t *x, uintptr_t *y) -{ - uint32_t addr = 0; - BL_Err_Type err = INVALID; - - CHECK_PARAM(NULL != x); - CHECK_PARAM(NULL != y); - - if (index < OSD_PROBE_ADDR_MAX_INDEX) { - addr = BL_RD_WORD(OSD_PROBE_BASE + OSD_PB_ADDR_00_OFFSET + index * sizeof(uint32_t)); - *x = addr & OSD_PB_REG_OSD_PB_X_00_MSK; - *y = (addr & OSD_PB_REG_OSD_PB_Y_00_MSK) >> OSD_PB_REG_OSD_PB_Y_00_POS; - err = SUCCESS; - } - - return err; -} - -/****************************************************************************** - * @brief OSD probe get result count info - * - * @param cnt: return the count info of the probe result. - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_probe_get_count(uintptr_t *cnt) -{ - CHECK_PARAM(NULL != cnt); - - *cnt = BL_GET_REG_BITS_VAL(BL_RD_REG(OSD_PROBE_BASE, OSD_PB_CTRL_REG), OSD_PB_STS_OSD_PB_W_CNT_R); - - return SUCCESS; -} - -/****************************************************************************** - * @brief OSD probe get result - * - * @param res: return the probe result. - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_probe_get_result(uintptr_t *res) -{ - uint32_t ctrl = 0; - - CHECK_PARAM(NULL != res); - - ctrl = BL_GET_REG_BITS_VAL(BL_RD_REG(OSD_PROBE_BASE, OSD_PB_CTRL_REG), OSD_PB_STS_OSD_PB_IDX_R); - - *res = ctrl ? BL_RD_REG(OSD_PROBE_BASE, OSD_PB_RESULT0) : BL_RD_REG(OSD_PROBE_BASE, OSD_PB_RESULT1); - - return SUCCESS; -} - -/****************************************************************************** - * @brief OSD probe get ctrl reg - * - * @param ctrl: return the value of the ctrl reg. - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_probe_get_ctrl(uintptr_t *ctrl) -{ - CHECK_PARAM(NULL != ctrl); - - *ctrl = BL_RD_REG(OSD_PROBE_BASE, OSD_PB_CTRL_REG); - - return SUCCESS; -} - -/****************************************************************************** - * @brief OSD probe set Y channel threshold. - * - * @param luma: value of the Y threshold. - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_probe_set_threshold(uintptr_t luma) -{ - uint32_t ctrl = 0; - - ctrl = BL_RD_REG(OSD_PROBE_BASE, OSD_PB_CTRL_REG); - ctrl &= ~OSD_PB_REG_OSD_PB_LUMA_TH_MSK; - ctrl |= (luma & OSD_PB_REG_OSD_PB_LUMA_TH_MSK); - BL_WR_REG(OSD_PROBE_BASE, OSD_PB_CTRL_REG, ctrl); - - return SUCCESS; -} - -/****************************************************************************** - * @brief OSD probe get Y channel threshold. - * - * @param luma: return value of the Y threshold in reg. - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_probe_get_threshold(uintptr_t *luma) -{ - uint32_t ctrl = 0; - - CHECK_PARAM(NULL != luma); - - ctrl = BL_RD_REG(OSD_PROBE_BASE, OSD_PB_CTRL_REG); - *luma = ctrl & OSD_PB_REG_OSD_PB_LUMA_TH_MSK; - - return SUCCESS; -} - -/*@} end of group OSD_PROBE_Public_Functions */ - -/*@} end of group OSD_PROBE */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_pwm.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_pwm.c deleted file mode 100644 index fd9451c627..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_pwm.c +++ /dev/null @@ -1,1247 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_pwm.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_pwm.h" -#include "bl808_glb.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup PWM - * @{ - */ - -/** @defgroup PWM_Private_Macros - * @{ - */ -#define PWMx_Get_Reg_Addr(id) (PWM_BASE + PWM_CHANNEL_OFFSET + (id)*0x40) -#define PWM_INT_TIMEOUT_COUNT (320 * 1000) -#define PWM_STOP_TIMEOUT_COUNT (320 * 1000) - -/*@} end of group PWM_Private_Macros */ - -/** @defgroup PWM_Private_Types - * @{ - */ - -/*@} end of group PWM_Private_Types */ - -/** @defgroup PWM_Private_Variables - * @{ - */ - -/** - * @brief PWM interrupt callback function address array -*/ -#ifndef BFLB_USE_HAL_DRIVER -static intCallback_Type *PWMIntCbfArra[PWMx_ID_MAX][PWM_INT_ALL] = { { NULL } }; -#endif -/*@} end of group PWM_Private_Variables */ - -/** @defgroup PWM_Global_Variables - * @{ - */ - -/*@} end of group PWM_Global_Variables */ - -/** @defgroup PWM_Private_Fun_Declaration - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -static BL_Err_Type PWM_IntHandler(IRQn_Type intPeriph); -#endif - -/*@} end of group PWM_Private_Fun_Declaration */ - -/** @defgroup PWM_Private_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief PWM interrupt handle - * - * @param None - * - * @return SUCCESS - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -static BL_Err_Type PWM_IntHandler(IRQn_Type intPeriph) -{ - uint32_t tmpVal = 0; - uint32_t maskVal = 0; - uint32_t PWMx; - uint16_t intIndex; - PWMx_ID_Type id; - - for (id = PWM0_ID; id < PWMx_ID_MAX; id++) { - /* Get PWMx start register address */ - PWMx = PWMx_Get_Reg_Addr(id); - tmpVal = BL_RD_REG(PWMx, PWM_INT_STS); - maskVal = BL_RD_REG(PWMx, PWM_INT_MASK); - for (intIndex = 0; intIndex < PWM_INT_ALL; intIndex++) { - if (((1 << intIndex) & tmpVal) && (((1 << intIndex) & maskVal) == 0)) { - if (intIndex == PWM_INT_REPT) { - if (BL_GET_REG_BITS_VAL(BL_RD_REG(PWMx, PWM_CONFIG0), PWM_STOP_ON_REPT) == 1) { - PWMx_Disable(id); - } - } - BL_WR_REG(PWMx, PWM_INT_CLEAR, 1 << intIndex); - if (PWMIntCbfArra[id][intIndex] != NULL) { - PWMIntCbfArra[id][intIndex](); - } - } - } - } - return SUCCESS; -} - -#endif - -/*@} end of group PWM_Private_Functions */ - -/** @defgroup PWM_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief PWMx init - * - * @param id: PWM ID - * @param chCfg: PWMx configuration - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type PWMx_Init(PWMx_ID_Type id, PWMx_CFG_Type *cfg) -{ - uint32_t tmpVal; - uint32_t timeoutCnt = PWM_STOP_TIMEOUT_COUNT; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - CHECK_PARAM(IS_PWM_CLK_TYPE(cfg->clk)); - CHECK_PARAM(IS_PWM_STOP_MODE_TYPE(cfg->stopMode)); - CHECK_PARAM(IS_PWM_EXT_BREAK_POLARITY_TYPE(cfg->extPol)); - CHECK_PARAM(IS_PWM_TRIGADC_SOURCE_TYPE(cfg->adcSrc)); - - /* Ungate pwm clock gate */ - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_PWM); - - /* Config pwm config0 */ - tmpVal = BL_RD_REG(PWMx, PWM_CONFIG0); - BL_WR_REG(PWMx, PWM_CONFIG0, BL_SET_REG_BIT(tmpVal, PWM_STOP_EN)); - while (!BL_IS_REG_BIT_SET(BL_RD_REG(PWMx, PWM_CONFIG0), PWM_STS_STOP)) { - timeoutCnt--; - if (timeoutCnt == 0) { - return TIMEOUT; - } - } - tmpVal = BL_RD_REG(PWMx, PWM_CONFIG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_REG_CLK_SEL, cfg->clk); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_STOP_MODE, cfg->stopMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_EXT_BREAK_PL, cfg->extPol); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_ADC_TRG_SRC, cfg->adcSrc); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_STOP_ON_REPT, cfg->stpRept); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CLK_DIV, cfg->clkDiv); - BL_WR_REG(PWMx, PWM_CONFIG0, tmpVal); - - /* Config pwm period and rept count */ - tmpVal = BL_RD_REG(PWMx, PWM_PERIOD); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_PERIOD, cfg->period); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_INT_PERIOD_CNT, cfg->intPulseCnt); - BL_WR_REG(PWMx, PWM_PERIOD, tmpVal); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(PWM_IRQn, PWM_IRQHandler); -#endif - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief PWMx update clock divider - * - * @param id: PWM ID - * @param div: Clock divider - * - * @return None - * -*******************************************************************************/ -void PWMx_Div_Set(PWMx_ID_Type id, uint16_t div) -{ - uint32_t tmpVal; - //* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - - tmpVal = BL_RD_REG(PWMx, PWM_CONFIG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CLK_DIV, div); - BL_WR_REG(PWMx, PWM_CONFIG0, tmpVal); -} - -/****************************************************************************/ /** - * @brief PWMx update period - * - * @param id: PWM ID - * @param period: period - * - * @return None - * -*******************************************************************************/ -void PWMx_Period_Set(PWMx_ID_Type id, uint16_t period) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - - /* Config pwm period and duty */ - tmpVal = BL_RD_REG(PWMx, PWM_PERIOD); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_PERIOD, period); - BL_WR_REG(PWMx, PWM_PERIOD, tmpVal); -} - -/****************************************************************************/ /** - * @brief PWMx get configuration - * - * @param id: PWM ID - * @param period: period pointer - * - * @return None - * -*******************************************************************************/ -void PWMx_Period_Get(PWMx_ID_Type id, uint16_t *period) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - - /* get pwm period */ - tmpVal = BL_RD_REG(PWMx, PWM_PERIOD); - *period = BL_GET_REG_BITS_VAL(tmpVal, PWM_PERIOD); -} - -/****************************************************************************/ /** - * @brief PWMx enable - * - * @param id: PWMx ID - * - * @return None - * -*******************************************************************************/ -void PWMx_Enable(PWMx_ID_Type id) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - - /* Config pwm clock to enable pwm */ - tmpVal = BL_RD_REG(PWMx, PWM_CONFIG0); - BL_WR_REG(PWMx, PWM_CONFIG0, BL_CLR_REG_BIT(tmpVal, PWM_STOP_EN)); -} - -/****************************************************************************/ /** - * @brief PWMx disable - * - * @param id: PWMx ID - * - * @return None - * -*******************************************************************************/ -void PWMx_Disable(PWMx_ID_Type id) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWM_CH_ID_TYPE(id)); - - /* Config pwm clock to disable pwm */ - tmpVal = BL_RD_REG(PWMx, PWM_CONFIG0); - BL_WR_REG(PWMx, PWM_CONFIG0, BL_SET_REG_BIT(tmpVal, PWM_STOP_EN)); -} - -void PWM_Channelx_Init(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_CHx_CFG_Type *cfg) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - CHECK_PARAM(IS_PWM_CHx_TYPE(ch)); - CHECK_PARAM(IS_PWM_MODE_TYPE(cfg->modP)); - CHECK_PARAM(IS_PWM_MODE_TYPE(cfg->modN)); - CHECK_PARAM(IS_PWM_POLARITY_TYPE(cfg->polP)); - CHECK_PARAM(IS_PWM_POLARITY_TYPE(cfg->polN)); - CHECK_PARAM(IS_PWM_IDLE_STATE_TYPE(cfg->idlP)); - CHECK_PARAM(IS_PWM_IDLE_STATE_TYPE(cfg->idlN)); - CHECK_PARAM(IS_PWM_BREAK_STATE_TYPE(cfg->brkP)); - CHECK_PARAM(IS_PWM_BREAK_STATE_TYPE(cfg->brkN)); - - /* Config pwm config1 */ - tmpVal = BL_RD_REG(PWMx, PWM_CONFIG1); - switch (ch) { - case PWM_CH0: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_PEN, cfg->modP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_NEN, cfg->modN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_PPL, cfg->polP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_NPL, cfg->polN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_PSI, cfg->idlP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_NSI, cfg->idlN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_PBS, cfg->brkP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_NBS, cfg->brkN); - break; - case PWM_CH1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_PEN, cfg->modP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_NEN, cfg->modN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_PPL, cfg->polP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_NPL, cfg->polN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_PSI, cfg->idlP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_NSI, cfg->idlN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_PBS, cfg->brkP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_NBS, cfg->brkN); - break; - case PWM_CH2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_PEN, cfg->modP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_NEN, cfg->modN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_PPL, cfg->polP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_NPL, cfg->polN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_PSI, cfg->idlP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_NSI, cfg->idlN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_PBS, cfg->brkP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_NBS, cfg->brkN); - break; - case PWM_CH3: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_PEN, cfg->modP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_NEN, cfg->modN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_PPL, cfg->polP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_NPL, cfg->polN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_PSI, cfg->idlP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_NSI, cfg->idlN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_PBS, cfg->brkP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_NBS, cfg->brkN); - break; - default: - break; - } - BL_WR_REG(PWMx, PWM_CONFIG1, tmpVal); - - /* Config pwm thresholdL and thresholdH */ - switch (ch) { - case PWM_CH0: - tmpVal = BL_RD_REG(PWMx, PWM_CH0_THRE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_THREL, cfg->thresholdL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_THREH, cfg->thresholdH); - BL_WR_REG(PWMx, PWM_CH0_THRE, tmpVal); - break; - case PWM_CH1: - tmpVal = BL_RD_REG(PWMx, PWM_CH1_THRE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_THREL, cfg->thresholdL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_THREH, cfg->thresholdH); - BL_WR_REG(PWMx, PWM_CH1_THRE, tmpVal); - break; - case PWM_CH2: - tmpVal = BL_RD_REG(PWMx, PWM_CH2_THRE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_THREL, cfg->thresholdL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_THREH, cfg->thresholdH); - BL_WR_REG(PWMx, PWM_CH2_THRE, tmpVal); - break; - case PWM_CH3: - tmpVal = BL_RD_REG(PWMx, PWM_CH3_THRE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_THREL, cfg->thresholdL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_THREH, cfg->thresholdH); - BL_WR_REG(PWMx, PWM_CH3_THRE, tmpVal); - break; - default: - break; - } - - /* Config pwm dead time */ - tmpVal = BL_RD_REG(PWMx, PWM_DEAD_TIME); - switch (ch) { - case PWM_CH0: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_DTG, cfg->dtg); - break; - case PWM_CH1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_DTG, cfg->dtg); - break; - case PWM_CH2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_DTG, cfg->dtg); - break; - case PWM_CH3: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_DTG, cfg->dtg); - break; - default: - break; - } - BL_WR_REG(PWMx, PWM_DEAD_TIME, tmpVal); -} - -void PWM_Channelx_Threshold_Set(PWMx_ID_Type id, PWM_CHx_Type ch, uint16_t thresholdL, uint16_t thresholdH) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - CHECK_PARAM(IS_PWM_CHx_TYPE(ch)); - - switch (ch) { - case PWM_CH0: - tmpVal = BL_RD_REG(PWMx, PWM_CH0_THRE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_THREL, thresholdL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_THREH, thresholdH); - BL_WR_REG(PWMx, PWM_CH0_THRE, tmpVal); - break; - case PWM_CH1: - tmpVal = BL_RD_REG(PWMx, PWM_CH1_THRE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_THREL, thresholdL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_THREH, thresholdH); - BL_WR_REG(PWMx, PWM_CH1_THRE, tmpVal); - break; - case PWM_CH2: - tmpVal = BL_RD_REG(PWMx, PWM_CH2_THRE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_THREL, thresholdL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_THREH, thresholdH); - BL_WR_REG(PWMx, PWM_CH2_THRE, tmpVal); - break; - case PWM_CH3: - tmpVal = BL_RD_REG(PWMx, PWM_CH3_THRE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_THREL, thresholdL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_THREH, thresholdH); - BL_WR_REG(PWMx, PWM_CH3_THRE, tmpVal); - break; - default: - break; - } -} - -void PWM_Channelx_ThresholdL_Set(PWMx_ID_Type id, PWM_CHx_Type ch, uint16_t thresholdL) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - CHECK_PARAM(IS_PWM_CHx_TYPE(ch)); - - switch (ch) { - case PWM_CH0: - tmpVal = BL_RD_REG(PWMx, PWM_CH0_THRE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_THREL, thresholdL); - BL_WR_REG(PWMx, PWM_CH0_THRE, tmpVal); - break; - case PWM_CH1: - tmpVal = BL_RD_REG(PWMx, PWM_CH1_THRE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_THREL, thresholdL); - BL_WR_REG(PWMx, PWM_CH1_THRE, tmpVal); - break; - case PWM_CH2: - tmpVal = BL_RD_REG(PWMx, PWM_CH2_THRE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_THREL, thresholdL); - BL_WR_REG(PWMx, PWM_CH2_THRE, tmpVal); - break; - case PWM_CH3: - tmpVal = BL_RD_REG(PWMx, PWM_CH3_THRE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_THREL, thresholdL); - BL_WR_REG(PWMx, PWM_CH3_THRE, tmpVal); - break; - default: - break; - } -} - -void PWM_Channelx_ThresholdH_Set(PWMx_ID_Type id, PWM_CHx_Type ch, uint16_t thresholdH) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - CHECK_PARAM(IS_PWM_CHx_TYPE(ch)); - - switch (ch) { - case PWM_CH0: - tmpVal = BL_RD_REG(PWMx, PWM_CH0_THRE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_THREH, thresholdH); - BL_WR_REG(PWMx, PWM_CH0_THRE, tmpVal); - break; - case PWM_CH1: - tmpVal = BL_RD_REG(PWMx, PWM_CH1_THRE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_THREH, thresholdH); - BL_WR_REG(PWMx, PWM_CH1_THRE, tmpVal); - break; - case PWM_CH2: - tmpVal = BL_RD_REG(PWMx, PWM_CH2_THRE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_THREH, thresholdH); - BL_WR_REG(PWMx, PWM_CH2_THRE, tmpVal); - break; - case PWM_CH3: - tmpVal = BL_RD_REG(PWMx, PWM_CH3_THRE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_THREH, thresholdH); - BL_WR_REG(PWMx, PWM_CH3_THRE, tmpVal); - break; - default: - break; - } -} - -void PWM_Channelx_Threshold_Get(PWMx_ID_Type id, PWM_CHx_Type ch, uint16_t *thresholdL, uint16_t *thresholdH) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - CHECK_PARAM(IS_PWM_CHx_TYPE(ch)); - - /* get pwm thresholdL and thresholdH */ - switch (ch) { - case PWM_CH0: - tmpVal = BL_RD_REG(PWMx, PWM_CH0_THRE); - *thresholdL = BL_GET_REG_BITS_VAL(tmpVal, PWM_CH0_THREL); - *thresholdH = BL_GET_REG_BITS_VAL(tmpVal, PWM_CH0_THREH); - break; - case PWM_CH1: - tmpVal = BL_RD_REG(PWMx, PWM_CH1_THRE); - *thresholdL = BL_GET_REG_BITS_VAL(tmpVal, PWM_CH1_THREL); - *thresholdH = BL_GET_REG_BITS_VAL(tmpVal, PWM_CH1_THREH); - break; - case PWM_CH2: - tmpVal = BL_RD_REG(PWMx, PWM_CH2_THRE); - *thresholdL = BL_GET_REG_BITS_VAL(tmpVal, PWM_CH2_THREL); - *thresholdH = BL_GET_REG_BITS_VAL(tmpVal, PWM_CH2_THREH); - break; - case PWM_CH3: - tmpVal = BL_RD_REG(PWMx, PWM_CH3_THRE); - *thresholdL = BL_GET_REG_BITS_VAL(tmpVal, PWM_CH3_THREL); - *thresholdH = BL_GET_REG_BITS_VAL(tmpVal, PWM_CH3_THREH); - break; - default: - break; - } -} - -void PWM_Channelx_Pwm_Mode_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Mode_Type modP, PWM_Mode_Type modN) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - CHECK_PARAM(IS_PWM_CHx_TYPE(ch)); - CHECK_PARAM(IS_PWM_MODE_TYPE(modP)); - CHECK_PARAM(IS_PWM_MODE_TYPE(modN)); - - /* Config pwm config1 */ - tmpVal = BL_RD_REG(PWMx, PWM_CONFIG1); - switch (ch) { - case PWM_CH0: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_PEN, modP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_NEN, modN); - break; - case PWM_CH1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_PEN, modP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_NEN, modN); - break; - case PWM_CH2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_PEN, modP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_NEN, modN); - break; - case PWM_CH3: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_PEN, modP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_NEN, modN); - break; - default: - break; - } - BL_WR_REG(PWMx, PWM_CONFIG1, tmpVal); -} -void PWM_Channelx_Positive_Pwm_Mode_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Mode_Type mod) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - CHECK_PARAM(IS_PWM_CHx_TYPE(ch)); - CHECK_PARAM(IS_PWM_MODE_TYPE(mod)); - - /* Config pwm config1 */ - tmpVal = BL_RD_REG(PWMx, PWM_CONFIG1); - switch (ch) { - case PWM_CH0: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_PEN, mod); - break; - case PWM_CH1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_PEN, mod); - break; - case PWM_CH2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_PEN, mod); - break; - case PWM_CH3: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_PEN, mod); - break; - default: - break; - } - BL_WR_REG(PWMx, PWM_CONFIG1, tmpVal); -} -void PWM_Channelx_Negative_Pwm_Mode_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Mode_Type mod) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - CHECK_PARAM(IS_PWM_CHx_TYPE(ch)); - CHECK_PARAM(IS_PWM_MODE_TYPE(mod)); - - /* Config pwm config1 */ - tmpVal = BL_RD_REG(PWMx, PWM_CONFIG1); - switch (ch) { - case PWM_CH0: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_NEN, mod); - break; - case PWM_CH1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_NEN, mod); - break; - case PWM_CH2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_NEN, mod); - break; - case PWM_CH3: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_NEN, mod); - break; - default: - break; - } - BL_WR_REG(PWMx, PWM_CONFIG1, tmpVal); -} - -void PWM_Channelx_Polarity_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Polarity_Type polP, PWM_Polarity_Type polN) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - CHECK_PARAM(IS_PWM_CHx_TYPE(ch)); - CHECK_PARAM(IS_PWM_POLARITY_TYPE(polP)); - CHECK_PARAM(IS_PWM_POLARITY_TYPE(polN)); - - /* Config pwm config1 */ - tmpVal = BL_RD_REG(PWMx, PWM_CONFIG1); - switch (ch) { - case PWM_CH0: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_PPL, polP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_NPL, polN); - break; - case PWM_CH1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_PPL, polP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_NPL, polN); - break; - case PWM_CH2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_PPL, polP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_NPL, polN); - break; - case PWM_CH3: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_PPL, polP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_NPL, polN); - break; - default: - break; - } - BL_WR_REG(PWMx, PWM_CONFIG1, tmpVal); -} - -void PWM_Channelx_Positive_Polarity_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Polarity_Type pol) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - CHECK_PARAM(IS_PWM_CHx_TYPE(ch)); - CHECK_PARAM(IS_PWM_POLARITY_TYPE(pol)); - - /* Config pwm config1 */ - tmpVal = BL_RD_REG(PWMx, PWM_CONFIG1); - switch (ch) { - case PWM_CH0: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_PPL, pol); - break; - case PWM_CH1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_PPL, pol); - break; - case PWM_CH2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_PPL, pol); - break; - case PWM_CH3: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_PPL, pol); - break; - default: - break; - } - BL_WR_REG(PWMx, PWM_CONFIG1, tmpVal); -} - -void PWM_Channelx_Negative_Polarity_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Polarity_Type pol) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - CHECK_PARAM(IS_PWM_CHx_TYPE(ch)); - CHECK_PARAM(IS_PWM_POLARITY_TYPE(pol)); - - /* Config pwm config1 */ - tmpVal = BL_RD_REG(PWMx, PWM_CONFIG1); - switch (ch) { - case PWM_CH0: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_NPL, pol); - break; - case PWM_CH1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_NPL, pol); - break; - case PWM_CH2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_NPL, pol); - break; - case PWM_CH3: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_NPL, pol); - break; - default: - break; - } - BL_WR_REG(PWMx, PWM_CONFIG1, tmpVal); -} - -void PWM_Channelx_Idle_State_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Idle_State_Type idlP, PWM_Idle_State_Type idlN) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - CHECK_PARAM(IS_PWM_CHx_TYPE(ch)); - CHECK_PARAM(IS_PWM_IDLE_STATE_TYPE(idlP)); - CHECK_PARAM(IS_PWM_IDLE_STATE_TYPE(idlN)); - - /* Config pwm config1 */ - tmpVal = BL_RD_REG(PWMx, PWM_CONFIG1); - switch (ch) { - case PWM_CH0: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_PSI, idlP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_NSI, idlN); - break; - case PWM_CH1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_PSI, idlP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_NSI, idlN); - break; - case PWM_CH2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_PSI, idlP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_NSI, idlN); - break; - case PWM_CH3: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_PSI, idlP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_NSI, idlN); - break; - default: - break; - } - BL_WR_REG(PWMx, PWM_CONFIG1, tmpVal); -} - -void PWM_Channelx_Positive_Idle_State_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Idle_State_Type idl) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - CHECK_PARAM(IS_PWM_CHx_TYPE(ch)); - CHECK_PARAM(IS_PWM_IDLE_STATE_TYPE(idl)); - - /* Config pwm config1 */ - tmpVal = BL_RD_REG(PWMx, PWM_CONFIG1); - switch (ch) { - case PWM_CH0: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_PSI, idl); - break; - case PWM_CH1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_PSI, idl); - break; - case PWM_CH2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_PSI, idl); - break; - case PWM_CH3: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_PSI, idl); - break; - default: - break; - } - BL_WR_REG(PWMx, PWM_CONFIG1, tmpVal); -} - -void PWM_Channelx_Negative_Idle_State_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Idle_State_Type idl) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - CHECK_PARAM(IS_PWM_CHx_TYPE(ch)); - CHECK_PARAM(IS_PWM_IDLE_STATE_TYPE(idl)); - - /* Config pwm config1 */ - tmpVal = BL_RD_REG(PWMx, PWM_CONFIG1); - switch (ch) { - case PWM_CH0: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_NSI, idl); - break; - case PWM_CH1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_NSI, idl); - break; - case PWM_CH2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_NSI, idl); - break; - case PWM_CH3: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_NSI, idl); - break; - default: - break; - } - BL_WR_REG(PWMx, PWM_CONFIG1, tmpVal); -} - -void PWM_Channelx_Break_State_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Break_State_Type brkP, PWM_Break_State_Type brkN) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - CHECK_PARAM(IS_PWM_CHx_TYPE(ch)); - CHECK_PARAM(IS_PWM_BREAK_STATE_TYPE(brkP)); - CHECK_PARAM(IS_PWM_BREAK_STATE_TYPE(brkN)); - - /* Config pwm config1 */ - tmpVal = BL_RD_REG(PWMx, PWM_CONFIG1); - switch (ch) { - case PWM_CH0: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_PBS, brkP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_NBS, brkN); - break; - case PWM_CH1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_PBS, brkP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_NBS, brkN); - break; - case PWM_CH2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_PBS, brkP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_NBS, brkN); - break; - case PWM_CH3: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_PBS, brkP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_NBS, brkN); - break; - default: - break; - } - BL_WR_REG(PWMx, PWM_CONFIG1, tmpVal); -} - -void PWM_Channelx_Positive_Break_State_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Break_State_Type brk) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - CHECK_PARAM(IS_PWM_CHx_TYPE(ch)); - CHECK_PARAM(IS_PWM_BREAK_STATE_TYPE(brk)); - - /* Config pwm config1 */ - tmpVal = BL_RD_REG(PWMx, PWM_CONFIG1); - switch (ch) { - case PWM_CH0: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_PBS, brk); - break; - case PWM_CH1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_PBS, brk); - break; - case PWM_CH2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_PBS, brk); - break; - case PWM_CH3: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_PBS, brk); - break; - default: - break; - } - BL_WR_REG(PWMx, PWM_CONFIG1, tmpVal); -} - -void PWM_Channelx_Negative_Break_State_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Break_State_Type brk) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - CHECK_PARAM(IS_PWM_CHx_TYPE(ch)); - CHECK_PARAM(IS_PWM_BREAK_STATE_TYPE(brk)); - - /* Config pwm config1 */ - tmpVal = BL_RD_REG(PWMx, PWM_CONFIG1); - switch (ch) { - case PWM_CH0: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_NBS, brk); - break; - case PWM_CH1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_NBS, brk); - break; - case PWM_CH2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_NBS, brk); - break; - case PWM_CH3: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_NBS, brk); - break; - default: - break; - } - BL_WR_REG(PWMx, PWM_CONFIG1, tmpVal); -} - -void PWM_Config1_Set(PWMx_ID_Type id, uint32_t cfg) -{ - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - - /* Config pwm config1 */ - BL_WR_REG(PWMx, PWM_CONFIG1, cfg); -} - -void PWM_Config1_Get(PWMx_ID_Type id, uint32_t *cfg) -{ - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - - /* Get pwm config1 value */ - *cfg = BL_RD_REG(PWMx, PWM_CONFIG1); -} - -void PWM_Channelx_Dtg_Set(PWMx_ID_Type id, PWM_CHx_Type ch, uint8_t dtg) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - CHECK_PARAM(IS_PWM_CHx_TYPE(ch)); - - /* Config pwm config1 */ - tmpVal = BL_RD_REG(PWMx, PWM_DEAD_TIME); - switch (ch) { - case PWM_CH0: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_DTG, dtg); - break; - case PWM_CH1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_DTG, dtg); - break; - case PWM_CH2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_DTG, dtg); - break; - case PWM_CH3: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_DTG, dtg); - break; - default: - break; - } - BL_WR_REG(PWMx, PWM_DEAD_TIME, tmpVal); -} - -void PWM_SW_Break_Enable(PWMx_ID_Type id) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - - /* Config pwm config0 */ - tmpVal = BL_RD_REG(PWMx, PWM_CONFIG0); - tmpVal = BL_SET_REG_BIT(tmpVal, PWM_SW_BREAK_EN); - BL_WR_REG(PWMx, PWM_CONFIG0, tmpVal); -} - -void PWM_SW_Break_Disable(PWMx_ID_Type id) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - - /* Config pwm config0 */ - tmpVal = BL_RD_REG(PWMx, PWM_CONFIG0); - tmpVal = BL_CLR_REG_BIT(tmpVal, PWM_SW_BREAK_EN); - BL_WR_REG(PWMx, PWM_CONFIG0, tmpVal); -} - -void PWM_EXT_Break_Enable(PWMx_ID_Type id) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWM_CH_ID_TYPE(id)); - - /* Config pwm config0 */ - tmpVal = BL_RD_REG(PWMx, PWM_CONFIG0); - tmpVal = BL_SET_REG_BIT(tmpVal, PWM_EXT_BREAK_EN); - BL_WR_REG(PWMx, PWM_CONFIG0, tmpVal); -} - -void PWM_EXT_Break_Disable(PWMx_ID_Type id) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWM_CH_ID_TYPE(id)); - - /* Config pwm config0 */ - tmpVal = BL_RD_REG(PWMx, PWM_CONFIG0); - tmpVal = BL_CLR_REG_BIT(tmpVal, PWM_EXT_BREAK_EN); - BL_WR_REG(PWMx, PWM_CONFIG0, tmpVal); -} - -void PWM_EXT_Break_Polarity_Set(PWMx_ID_Type id, PWM_EXT_Break_Polarity_Type pol) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - CHECK_PARAM(IS_PWM_EXT_BREAK_POLARITY_TYPE(pol)); - - /* Config pwm config0 */ - tmpVal = BL_RD_REG(PWMx, PWM_CONFIG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_EXT_BREAK_PL, pol); - BL_WR_REG(PWMx, PWM_CONFIG0, tmpVal); -} - -void PWM_TrigADC_Source_Set(PWMx_ID_Type id, PWM_TrigADC_Source_Type src) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWM_CH_ID_TYPE(id)); - CHECK_PARAM(IS_PWM_TRIGADC_SOURCE_TYPE(src)); - - /* Config pwm config0 */ - tmpVal = BL_RD_REG(PWMx, PWM_CONFIG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_ADC_TRG_SRC, src); - BL_WR_REG(PWMx, PWM_CONFIG0, tmpVal); -} - -/****************************************************************************/ /** - * @brief Mask/Unmask the PWM interrupt - * - * @param id: PWM ID - * @param intType: Specifies the interrupt type - * @param intMask: Enable/Disable Specified interrupt type - * - * @return None - * -*******************************************************************************/ -void PWM_Int_Mask(PWMx_ID_Type id, PWM_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWM_CH_ID_TYPE(id)); - CHECK_PARAM(IS_PWM_INT_TYPE(intType)); - - tmpVal = BL_RD_REG(PWMx, PWM_INT_MASK); - if (intType == PWM_INT_ALL) { - if (intMask == UNMASK) { - tmpVal &= ~((1U << PWM_INT_ALL) - 1); - } else { - tmpVal |= ((1U << PWM_INT_ALL) - 1); - } - } else { - if (intMask == UNMASK) { - tmpVal &= ~(1U << intType); - } else { - tmpVal |= (1U << intType); - } - } - BL_WR_REG(PWMx, PWM_INT_MASK, tmpVal); -} - -void PWM_Int_Clear(PWMx_ID_Type id, PWM_INT_Type intType) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - CHECK_PARAM(IS_PWM_INT_TYPE(intType)); - - tmpVal = BL_RD_REG(PWMx, PWM_INT_CLEAR); - - if (intType == PWM_INT_ALL) { - tmpVal = ((1U << PWM_INT_ALL) - 1); - } else { - tmpVal = (1U << intType); - } - BL_WR_REG(PWMx, PWM_INT_CLEAR, tmpVal); -} - -BL_Sts_Type PWM_Int_Status_Get(PWMx_ID_Type id, PWM_INT_Type intType) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWM_CH_ID_TYPE(id)); - CHECK_PARAM(IS_PWM_INT_TYPE(intType)); - - tmpVal = BL_RD_REG(PWMx, PWM_INT_STS); - - if (intType == PWM_INT_ALL) { - if (tmpVal & ((1 << PWM_CHx_MAX) - 1)) { - return SET; - } else { - return RESET; - } - } else { - if (tmpVal & (1 << intType)) { - return SET; - } else { - return RESET; - } - } -} - -/****************************************************************************/ /** - * @brief Install PWM interrupt callback function - * - * @param id: PWM ID - * @param intType: PWM interrupt type - * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void PWM_Int_Callback_Install(PWMx_ID_Type id, uint32_t intType, intCallback_Type *cbFun) -{ - PWMIntCbfArra[id][intType] = cbFun; -} -#endif - -/****************************************************************************/ /** - * @brief PWM interrupt function - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void PWM_IRQHandler(void) -{ - PWM_IntHandler(PWM_IRQn); -} -#endif - -/*@} end of group PWM_Public_Functions */ - -/*@} end of group PWM */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_romapi_patch.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_romapi_patch.c deleted file mode 100644 index 84af0f57ec..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_romapi_patch.c +++ /dev/null @@ -1,3092 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_romapi_patch.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2021 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_romapi_patch.h" -#include "bl808_romdriver_e907.h" -#error "Not using romndriver now" - -/* WiFi PLL Config*/ -const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION wifiPllBasicCfg_32M_38P4M_40M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllIntFracSw = 0, /*!< pll_int_frac_sw */ - .clkpllIcp1u = 0, /*!< pll_icp_1u */ - .clkpllIcp5u = 2, /*!< pll_icp_5u */ - .clkpllRz = 3, /*!< pll_rz */ - .clkpllCz = 1, /*!< pll_cz */ - .clkpllC3 = 2, /*!< pll_c3 */ - .clkpllR4Short = 1, /*!< pll_r4_short */ - .clkpllC4En = 0, /*!< pll_r4_en */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllSdmCtrlHw = 1, /*!< pll_sdm_ctrl_hw */ - .clkpllSdmBypass = 1, /*!< pll_sdm_bypass */ -}; -const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION wifiPllBasicCfg_24M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllIntFracSw = 0, /*!< pll_int_frac_sw */ - .clkpllIcp1u = 0, /*!< pll_icp_1u */ - .clkpllIcp5u = 2, /*!< pll_icp_5u */ - .clkpllRz = 3, /*!< pll_rz */ - .clkpllCz = 1, /*!< pll_cz */ - .clkpllC3 = 2, /*!< pll_c3 */ - .clkpllR4Short = 1, /*!< pll_r4_short */ - .clkpllC4En = 0, /*!< pll_r4_en */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllSdmCtrlHw = 1, /*!< pll_sdm_ctrl_hw */ - .clkpllSdmBypass = 1, /*!< pll_sdm_bypass */ -}; -const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION wifiPllBasicCfg_26M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllIntFracSw = 1, /*!< pll_int_frac_sw */ - .clkpllIcp1u = 1, /*!< pll_icp_1u */ - .clkpllIcp5u = 0, /*!< pll_icp_5u */ - .clkpllRz = 5, /*!< pll_rz */ - .clkpllCz = 2, /*!< pll_cz */ - .clkpllC3 = 2, /*!< pll_c3 */ - .clkpllR4Short = 0, /*!< pll_r4_short */ - .clkpllC4En = 1, /*!< pll_r4_en */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllSdmCtrlHw = 0, /*!< pll_sdm_ctrl_hw */ - .clkpllSdmBypass = 0, /*!< pll_sdm_bypass */ -}; -const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION wifiPllCfg_960M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &wifiPllBasicCfg_24M, 0x1400000 }, /*!< XTAL is 24M */ - { &wifiPllBasicCfg_32M_38P4M_40M, 0x1E00000 }, /*!< XTAL is 32M */ - { &wifiPllBasicCfg_32M_38P4M_40M, 0x1900000 }, /*!< XTAL is 38.4M */ - { &wifiPllBasicCfg_32M_38P4M_40M, 0x1800000 }, /*!< XTAL is 40M */ - { &wifiPllBasicCfg_26M, 0x1276276 }, /*!< XTAL is 26M */ - { &wifiPllBasicCfg_32M_38P4M_40M, 0x1E00000 }, /*!< XTAL is RC32M */ -}; - -/* Audio PLL Config*/ -const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION audioPllBasicCfg_24M_26M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllIntFracSw = 1, /*!< pll_int_frac_sw */ - .clkpllIcp1u = 1, /*!< pll_icp_1u */ - .clkpllIcp5u = 0, /*!< pll_icp_5u */ - .clkpllRz = 5, /*!< pll_rz */ - .clkpllCz = 2, /*!< pll_cz */ - .clkpllC3 = 2, /*!< pll_c3 */ - .clkpllR4Short = 0, /*!< pll_r4_short */ - .clkpllC4En = 1, /*!< pll_r4_en */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 3, /*!< pll_vco_speed */ - .clkpllSdmCtrlHw = 0, /*!< pll_sdm_ctrl_hw */ - .clkpllSdmBypass = 0, /*!< pll_sdm_bypass */ -}; -const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION audioPllBasicCfg_32M_38P4M_40M = { - .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */ - .clkpllIntFracSw = 1, /*!< pll_int_frac_sw */ - .clkpllIcp1u = 1, /*!< pll_icp_1u */ - .clkpllIcp5u = 0, /*!< pll_icp_5u */ - .clkpllRz = 5, /*!< pll_rz */ - .clkpllCz = 2, /*!< pll_cz */ - .clkpllC3 = 2, /*!< pll_c3 */ - .clkpllR4Short = 0, /*!< pll_r4_short */ - .clkpllC4En = 1, /*!< pll_r4_en */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 3, /*!< pll_vco_speed */ - .clkpllSdmCtrlHw = 0, /*!< pll_sdm_ctrl_hw */ - .clkpllSdmBypass = 0, /*!< pll_sdm_bypass */ -}; -const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION audioPllCfg_442P368M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &audioPllBasicCfg_24M_26M, 0x126E9 }, /*!< XTAL is 24M */ - { &audioPllBasicCfg_32M_38P4M_40M, 0x1BA5E }, /*!< XTAL is 32M */ - { &audioPllBasicCfg_32M_38P4M_40M, 0x170A3 }, /*!< XTAL is 38.4M */ - { &audioPllBasicCfg_32M_38P4M_40M, 0x161E5 }, /*!< XTAL is 40M */ - { &audioPllBasicCfg_24M_26M, 0x1103A }, /*!< XTAL is 26M */ - { &audioPllBasicCfg_32M_38P4M_40M, 0x1BA5E }, /*!< XTAL is RC32M */ -}; -const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION audioPllCfg_451P584M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &audioPllBasicCfg_24M_26M, 0x12D0E }, /*!< XTAL is 24M */ - { &audioPllBasicCfg_32M_38P4M_40M, 0x1C395 }, /*!< XTAL is 32M */ - { &audioPllBasicCfg_32M_38P4M_40M, 0x17851 }, /*!< XTAL is 38.4M */ - { &audioPllBasicCfg_32M_38P4M_40M, 0x16944 }, /*!< XTAL is 40M */ - { &audioPllBasicCfg_24M_26M, 0x115E5 }, /*!< XTAL is 26M */ - { &audioPllBasicCfg_32M_38P4M_40M, 0x1C395 }, /*!< XTAL is RC32M */ -}; - -/* CPU PLL Config*/ -const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION cpuPllBasicCfg_24M_26M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllIntFracSw = 1, /*!< pll_int_frac_sw */ - .clkpllIcp1u = 1, /*!< pll_icp_1u */ - .clkpllIcp5u = 0, /*!< pll_icp_5u */ - .clkpllRz = 5, /*!< pll_rz */ - .clkpllCz = 2, /*!< pll_cz */ - .clkpllC3 = 2, /*!< pll_c3 */ - .clkpllR4Short = 0, /*!< pll_r4_short */ - .clkpllC4En = 1, /*!< pll_r4_en */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 3, /*!< pll_vco_speed */ - .clkpllSdmCtrlHw = 0, /*!< pll_sdm_ctrl_hw */ - .clkpllSdmBypass = 0, /*!< pll_sdm_bypass */ -}; -const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION cpuPllBasicCfg_32M_38P4M_40M = { - .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */ - .clkpllIntFracSw = 1, /*!< pll_int_frac_sw */ - .clkpllIcp1u = 1, /*!< pll_icp_1u */ - .clkpllIcp5u = 0, /*!< pll_icp_5u */ - .clkpllRz = 5, /*!< pll_rz */ - .clkpllCz = 2, /*!< pll_cz */ - .clkpllC3 = 2, /*!< pll_c3 */ - .clkpllR4Short = 0, /*!< pll_r4_short */ - .clkpllC4En = 1, /*!< pll_r4_en */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 3, /*!< pll_vco_speed */ - .clkpllSdmCtrlHw = 0, /*!< pll_sdm_ctrl_hw */ - .clkpllSdmBypass = 0, /*!< pll_sdm_bypass */ -}; -const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION cpuPllCfg_380M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &cpuPllBasicCfg_24M_26M, 0xFD55 }, /*!< XTAL is 24M */ - { &cpuPllBasicCfg_32M_38P4M_40M, 0x17C00 }, /*!< XTAL is 32M */ - { &cpuPllBasicCfg_32M_38P4M_40M, 0x13CAA }, /*!< XTAL is 38.4M */ - { &cpuPllBasicCfg_32M_38P4M_40M, 0x13000 }, /*!< XTAL is 40M */ - { &cpuPllBasicCfg_24M_26M, 0xE9D8 }, /*!< XTAL is 26M */ - { &cpuPllBasicCfg_32M_38P4M_40M, 0x17C00 }, /*!< XTAL is RC32M */ -}; -const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION cpuPllCfg_400M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &cpuPllBasicCfg_24M_26M, 0x10AAA }, /*!< XTAL is 24M */ - { &cpuPllBasicCfg_32M_38P4M_40M, 0x19000 }, /*!< XTAL is 32M */ - { &cpuPllBasicCfg_32M_38P4M_40M, 0x14D55 }, /*!< XTAL is 38.4M */ - { &cpuPllBasicCfg_32M_38P4M_40M, 0x14000 }, /*!< XTAL is 40M */ - { &cpuPllBasicCfg_24M_26M, 0xF627 }, /*!< XTAL is 26M */ - { &cpuPllBasicCfg_32M_38P4M_40M, 0x19000 }, /*!< XTAL is RC32M */ -}; -const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION cpuPllCfg_480M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &cpuPllBasicCfg_24M_26M, 0x14000 }, /*!< XTAL is 24M */ - { &cpuPllBasicCfg_32M_38P4M_40M, 0x1E000 }, /*!< XTAL is 32M */ - { &cpuPllBasicCfg_32M_38P4M_40M, 0x19000 }, /*!< XTAL is 38.4M */ - { &cpuPllBasicCfg_32M_38P4M_40M, 0x18000 }, /*!< XTAL is 40M */ - { &cpuPllBasicCfg_24M_26M, 0x12762 }, /*!< XTAL is 26M */ - { &cpuPllBasicCfg_32M_38P4M_40M, 0x1E000 }, /*!< XTAL is RC32M */ -}; - -/* MIPI PLL Config*/ -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION mipiPllBasicCfg_24M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 0, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 0, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION mipiPllBasicCfg_32M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 0, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 0, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION mipiPllBasicCfg_38P4M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 0, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 0, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION mipiPllBasicCfg_40M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 0, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 0, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION mipiPllBasicCfg_26M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 0, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 0, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION mipiPllCfg_1500M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &mipiPllBasicCfg_24M, 0x3E800 }, /*!< XTAL is 24M */ - { &mipiPllBasicCfg_32M, 0x46500 }, /*!< XTAL is 32M */ - { &mipiPllBasicCfg_38P4M, 0x3A980 }, /*!< XTAL is 38.4M */ - { &mipiPllBasicCfg_40M, 0x38400 }, /*!< XTAL is 40M */ - { &mipiPllBasicCfg_26M, 0x39B13 }, /*!< XTAL is 26M */ - { &mipiPllBasicCfg_32M, 0x46500 }, /*!< XTAL is RC32M */ -}; - -/* uhs PLL 2100 Config*/ -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_24M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_32M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_38P4M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_40M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_26M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_2100M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &uhsPll2100BasicCfg_24M, 0x2BC00 }, /*!< XTAL is 24M */ - { &uhsPll2100BasicCfg_32M, 0x41A00 }, /*!< XTAL is 32M */ - { &uhsPll2100BasicCfg_38P4M, 0x36B00 }, /*!< XTAL is 38.4M */ - { &uhsPll2100BasicCfg_40M, 0x34800 }, /*!< XTAL is 40M */ - { &uhsPll2100BasicCfg_26M, 0x28627 }, /*!< XTAL is 26M */ - { &uhsPll2100BasicCfg_32M, 0x41A00 }, /*!< XTAL is RC32M */ -}; - -/* uhs PLL 1400 Config*/ -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_24M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 4, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1400/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_32M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 4, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1400/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_38P4M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 4, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1400/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_40M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 4, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1400/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_26M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 4, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1400/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1400M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &uhsPll1400MCfg_24M, 0x3A555 }, /*!< XTAL is 24M */ - { &uhsPll1400MCfg_32M, 0x41A00 }, /*!< XTAL is 32M */ - { &uhsPll1400MCfg_38P4M, 0x36B00 }, /*!< XTAL is 38.4M */ - { &uhsPll1400MCfg_40M, 0x34800 }, /*!< XTAL is 40M */ - { &uhsPll1400MCfg_26M, 0x35D89 }, /*!< XTAL is 26M */ - { &uhsPll1400MCfg_32M, 0x41A00 }, /*!< XTAL is RC32M */ -}; - -/* uhs PLL 1500 Config*/ -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_24M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1500/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_32M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1500/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_38P4M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1500/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_40M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1500/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_26M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1500/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1500M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &uhsPll1500MCfg_24M, 0x3E800 }, /*!< XTAL is 24M */ - { &uhsPll1500MCfg_32M, 0x46500 }, /*!< XTAL is 32M */ - { &uhsPll1500MCfg_38P4M, 0x3A980 }, /*!< XTAL is 38.4M */ - { &uhsPll1500MCfg_40M, 0x38400 }, /*!< XTAL is 40M */ - { &uhsPll1500MCfg_26M, 0x39B13 }, /*!< XTAL is 26M */ - { &uhsPll1500MCfg_32M, 0x46500 }, /*!< XTAL is RC32M */ -}; - -/* uhs PLL 1600 Config*/ -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_24M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1600/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_32M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1600/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_38P4M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1600/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_40M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1600/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_26M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1600/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1600M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &uhsPll1600BasicCfg_24M, 0x21555 }, /*!< XTAL is 24M */ - { &uhsPll1600BasicCfg_32M, 0x32000 }, /*!< XTAL is 32M */ - { &uhsPll1600BasicCfg_38P4M, 0x29AAA }, /*!< XTAL is 38.4M */ - { &uhsPll1600BasicCfg_40M, 0x28000 }, /*!< XTAL is 40M */ - { &uhsPll1600BasicCfg_26M, 0x1EC4E }, /*!< XTAL is 26M */ - { &uhsPll1600BasicCfg_32M, 0x32000 }, /*!< XTAL is RC32M */ -}; - -/* uhs PLL 400 Config*/ -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_24M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 400/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_32M = { - .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 400/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_38P4M = { - .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 400/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_40M = { - .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 400/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_26M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 400/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_400M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &uhsPll400BasicCfg_24M, 0x19000 }, /*!< XTAL is 24M */ - { &uhsPll400BasicCfg_32M, 0x19000 }, /*!< XTAL is 32M */ - { &uhsPll400BasicCfg_38P4M, 0x14D55 }, /*!< XTAL is 38.4M */ - { &uhsPll400BasicCfg_40M, 0x14000 }, /*!< XTAL is 40M */ - { &uhsPll400BasicCfg_26M, 0x1713B }, /*!< XTAL is 26M */ - { &uhsPll400BasicCfg_32M, 0x19000 }, /*!< XTAL is RC32M */ -}; - -/* uhs PLL 667 Config*/ -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_24M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 667/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_32M = { - .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 667/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_38P4M = { - .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 667/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_40M = { - .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 667/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_26M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 667/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_667M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &uhsPll667BasicCfg_24M, 0x29B00 }, /*!< XTAL is 24M */ - { &uhsPll667BasicCfg_32M, 0x29B00 }, /*!< XTAL is 32M */ - { &uhsPll667BasicCfg_38P4M, 0x22BD5 }, /*!< XTAL is 38.4M */ - { &uhsPll667BasicCfg_40M, 0x21599 }, /*!< XTAL is 40M */ - { &uhsPll667BasicCfg_26M, 0x267B1 }, /*!< XTAL is 26M */ - { &uhsPll667BasicCfg_32M, 0x29B00 }, /*!< XTAL is RC32M */ -}; - -/* uhs PLL 800 Config*/ -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_24M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 2, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 800/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_32M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 2, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 800/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_38P4M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 2, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 800/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_40M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 2, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 800/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_26M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 2, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 800/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_800M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &uhsPll800BasicCfg_24M, 0x21555 }, /*!< XTAL is 24M */ - { &uhsPll800BasicCfg_32M, 0x25800 }, /*!< XTAL is 32M */ - { &uhsPll800BasicCfg_38P4M, 0x1F400 }, /*!< XTAL is 38.4M */ - { &uhsPll800BasicCfg_40M, 0x1E000 }, /*!< XTAL is 40M */ - { &uhsPll800BasicCfg_26M, 0x1EC4E }, /*!< XTAL is 26M */ - { &uhsPll800BasicCfg_32M, 0x25800 }, /*!< XTAL is RC32M */ -}; - -/* uhs PLL 1066 Config*/ -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_24M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 3, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1066/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_32M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 3, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1066/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_38P4M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 3, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1066/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_40M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 3, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1066/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_26M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 3, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1066/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1066M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &uhsPll1066BasicCfg_24M, 0x2C6AA }, /*!< XTAL is 24M */ - { &uhsPll1066BasicCfg_32M, 0x31F80 }, /*!< XTAL is 32M */ - { &uhsPll1066BasicCfg_38P4M, 0x29A40 }, /*!< XTAL is 38.4M */ - { &uhsPll1066BasicCfg_40M, 0x27F99 }, /*!< XTAL is 40M */ - { &uhsPll1066BasicCfg_26M, 0x29000 }, /*!< XTAL is 26M */ - { &uhsPll1066BasicCfg_32M, 0x31F80 }, /*!< XTAL is RC32M */ -}; - -/* uhs PLL 2000 Config*/ -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_24M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_32M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_38P4M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_40M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_26M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_2000M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &uhsPll2000BasicCfg_24M, 0x29AAA }, /*!< XTAL is 24M */ - { &uhsPll2000BasicCfg_32M, 0x3E800 }, /*!< XTAL is 32M */ - { &uhsPll2000BasicCfg_38P4M, 0x34155 }, /*!< XTAL is 38.4M */ - { &uhsPll2000BasicCfg_40M, 0x32000 }, /*!< XTAL is 40M */ - { &uhsPll2000BasicCfg_26M, 0x26762 }, /*!< XTAL is 26M */ - { &uhsPll2000BasicCfg_32M, 0x3E800 }, /*!< XTAL is RC32M */ -}; - -static intCallback_Type *uartIntCbfArra[UART_ID_MAX][UART_INT_ALL] = { - { NULL } -}; -#ifndef BFLB_USE_HAL_DRIVER -static const uint32_t uartAddr[UART_ID_MAX] = { UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE }; - -typedef struct -{ - uint32_t jedecID; - char *name; - const SPI_Flash_Cfg_Type *cfg; -} Flash_Info_t; -#endif - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_GD_LQ64E = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xc8, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0xa0, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3d, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 500, - .timeE32k = 2000, - .timeE64k = 2000, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 3, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_64JW = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xef, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x31, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 0, - .cReadMode = 0xf0, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 400, - .timeE32k = 1600, - .timeE64k = 2000, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 3, - .qeData = 0, -}; - - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_XM25QH16={ - .resetCreadCmd=0xff, - .resetCreadCmdSize=3, - .mid=0x20, - - .deBurstWrapCmd=0x77, - .deBurstWrapCmdDmyClk=0x3, - .deBurstWrapDataMode=SF_CTRL_DATA_4_LINES, - .deBurstWrapData=0xF0, - - /*reg*/ - .writeEnableCmd=0x06, - .wrEnableIndex=0x00, - .wrEnableBit=0x01, - .wrEnableReadRegLen=0x01, - - .qeIndex=1, - .qeBit=0x01, - .qeWriteRegLen=0x01, - .qeReadRegLen=0x1, - - .busyIndex=0, - .busyBit=0x00, - .busyReadRegLen=0x1, - .releasePowerDown=0xab, - - .readRegCmd[0]=0x05, - .readRegCmd[1]=0x35, - .writeRegCmd[0]=0x01, - .writeRegCmd[1]=0x31, - - .fastReadQioCmd=0xeb, - .frQioDmyClk=16/8, - .cReadSupport=1, - .cReadMode=0x20, - - .burstWrapCmd=0x77, - .burstWrapCmdDmyClk=0x3, - .burstWrapDataMode=SF_CTRL_DATA_4_LINES, - .burstWrapData=0x40, - /*erase*/ - .chipEraseCmd=0xc7, - .sectorEraseCmd=0x20, - .blk32EraseCmd=0x52, - .blk64EraseCmd=0xd8, - /*write*/ - .pageProgramCmd=0x02, - .qpageProgramCmd=0x32, - .qppAddrMode=SF_CTRL_ADDR_1_LINE, - - .ioMode=SF_CTRL_QIO_MODE, - .clkDelay=1, - .clkInvert=0x01, - - .resetEnCmd=0x66, - .resetCmd=0x99, - .cRExit=0xff, - .wrEnableWriteRegLen=0x00, - - /*id*/ - .jedecIdCmd=0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd=0x0b, - .frDmyClk=8/8, - .qpiFastReadCmd =0x0b, - .qpiFrDmyClk=8/8, - .fastReadDoCmd=0x3b, - .frDoDmyClk=8/8, - .fastReadDioCmd=0xbb, - .frDioDmyClk=0, - .fastReadQoCmd=0x6b, - .frQoDmyClk=8/8, - - .qpiFastReadQioCmd=0xeb, - .qpiFrQioDmyClk=16/8, - .qpiPageProgramCmd=0x02, - .writeVregEnableCmd=0x50, - - /* qpi mode */ - .enterQpi=0x38, - .exitQpi=0xff, - - /*AC*/ - .timeEsector=400, - .timeE32k=1600, - .timeE64k=2000, - .timePagePgm=5, - .timeCe=33000, - .pdDelay=3, - .qeData=0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_256FV = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xef, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x31, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0x20, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = 0x24, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 400, - .timeE32k = 1600, - .timeE64k = 2000, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 3, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_16JV = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xef, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x31, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0x20, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 400, - .timeE32k = 1600, - .timeE64k = 2000, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 3, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_Q32E_Q128E = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xc8, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x31, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0xa0, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 20, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_Q80E_Q16E = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xc8, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0xa0, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 500, - .timeE32k = 2000, - .timeE64k = 2000, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 20, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Mxic_25L256 = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xc2, - - .deBurstWrapCmd = 0xC0, - .deBurstWrapCmdDmyClk = 0x00, - .deBurstWrapDataMode = SF_CTRL_DATA_1_LINE, - .deBurstWrapData = 0x10, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 0, - .qeBit = 0x06, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x15, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0xA5, - - .burstWrapCmd = 0xC0, - .burstWrapCmdDmyClk = 0x00, - .burstWrapDataMode = SF_CTRL_DATA_1_LINE, - .burstWrapData = 0x02, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x38, - .qppAddrMode = SF_CTRL_ADDR_4_LINES, - - .ioMode = (SF_CTRL_QIO_MODE | 0x20), - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 400, - .timeE32k = 1000, - .timeE64k = 2000, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 20, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION Flash_Info_t flashInfos[] = { - { - .jedecID = 0x1760c8, - //.name="GD_LQ64E_64_18", - .cfg = &flashCfg_GD_LQ64E, - }, - { - .jedecID = 0x1760ef, - //.name="WB_64JW_64_18", - .cfg = &flashCfg_Winb_64JW, - }, - { - .jedecID=0x144020, - //.name="XM_25QH80_80_33", - .cfg=&flashCfg_XM25QH16, - }, - { - .jedecID=0x154020, - //.name="XM_25QH16_16_33", - .cfg=&flashCfg_XM25QH16, - }, - { - .jedecID=0x164020, - //.name="XM_25QH32_32_33", - .cfg=&flashCfg_XM25QH16, - }, - { - .jedecID=0x174020, - //.name="XM_25QH64_64_33", - .cfg=&flashCfg_XM25QH16, - }, - { - .jedecID = 0x17400B, - //.name="XT_25F64B_32_33", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x1570ef, - //.name="Winb_16JV_16_33", - .cfg = &flashCfg_Winb_16JV, - }, - { - .jedecID = 0x1940ef, - //.name="Winb_256FV_128_33", - .cfg = &flashCfg_Winb_256FV, - }, - { - .jedecID = 0x1860c8, - //.name="GD_LQ128E_64_18", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x15345e, - //.name="ZB_WQ16A_16_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x15405e, - //.name="ZB_Q16B_16_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x16405e, - //.name="ZB_Q32B_32_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x17405e, - //.name="ZB_Q64B_64_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x15605E, - //.name="ZB_VQ16", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x3925C2, - //.name="MX_25U256_256_33", - .cfg = &flashCfg_Mxic_25L256, - }, - { - .jedecID = 0x1740c8, - //.name="GD_Q64E_64_18", - .cfg = &flashCfg_XM25QH16, - } -}; - -static void UART_IntHandler(UART_ID_Type uartId) -{ - uint32_t tmpVal = 0; - uint32_t maskVal = 0; - uint32_t UARTx = uartAddr[uartId]; - - tmpVal = BL_RD_REG(UARTx, UART_INT_STS); - maskVal = BL_RD_REG(UARTx, UART_INT_MASK); - - /* Length of uart tx data transfer arrived interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_END_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_END_MASK)) { - BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_UTX_END_CLR_POS); - - if (uartIntCbfArra[uartId][UART_INT_TX_END] != NULL) { - uartIntCbfArra[uartId][UART_INT_TX_END](); - } - } - - /* Length of uart rx data transfer arrived interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_END_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_END_MASK)) { - BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_END_CLR_POS); - - if (uartIntCbfArra[uartId][UART_INT_RX_END] != NULL) { - uartIntCbfArra[uartId][UART_INT_RX_END](); - } - } - - /* Tx fifo ready interrupt,auto-cleared when data is pushed */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_FRDY_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_FRDY_MASK)) { - if (uartIntCbfArra[uartId][UART_INT_TX_FIFO_REQ] != NULL) { - uartIntCbfArra[uartId][UART_INT_TX_FIFO_REQ](); - } - } - - /* Rx fifo ready interrupt,auto-cleared when data is popped */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_FRDY_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_FRDY_MASK)) { - if (uartIntCbfArra[uartId][UART_INT_RX_FIFO_REQ] != NULL) { - uartIntCbfArra[uartId][UART_INT_RX_FIFO_REQ](); - } - } - - /* Rx time-out interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_RTO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_RTO_MASK)) { - BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_RTO_CLR_POS); - - if (uartIntCbfArra[uartId][UART_INT_RTO] != NULL) { - uartIntCbfArra[uartId][UART_INT_RTO](); - } - } - - /* Rx parity check error interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_PCE_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_PCE_MASK)) { - BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_PCE_CLR_POS); - - if (uartIntCbfArra[uartId][UART_INT_PCE] != NULL) { - uartIntCbfArra[uartId][UART_INT_PCE](); - } - } - - /* Tx fifo overflow/underflow error interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_FER_MASK)) { - if (uartIntCbfArra[uartId][UART_INT_TX_FER] != NULL) { - uartIntCbfArra[uartId][UART_INT_TX_FER](); - } - } - - /* Rx fifo overflow/underflow error interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_FER_MASK)) { - if (uartIntCbfArra[uartId][UART_INT_RX_FER] != NULL) { - uartIntCbfArra[uartId][UART_INT_RX_FER](); - } - } - - /* Rx lin mode sync field error interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_LSE_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_LSE_MASK)) { - BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_LSE_CLR_POS); - - if (uartIntCbfArra[uartId][UART_INT_LSE] != NULL) { - uartIntCbfArra[uartId][UART_INT_LSE](); - } - } - - /* Rx byte count reached interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_BCR_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_BCR_MASK)) { - BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_BCR_CLR_POS); - - if (uartIntCbfArra[uartId][UART_INT_BCR] != NULL) { - uartIntCbfArra[uartId][UART_INT_BCR](); - } - } - - /* Rx auto baud rate detection finish interrupt using start bit */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_ADS_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_ADS_MASK)) { - BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_ADS_CLR_POS); - - if (uartIntCbfArra[uartId][UART_INT_STARTBIT] != NULL) { - uartIntCbfArra[uartId][UART_INT_STARTBIT](); - } - } - - /* Rx auto baud rate detection finish interrupt using codeword 0x55 */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_AD5_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_AD5_MASK)) { - BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_AD5_CLR_POS); - - if (uartIntCbfArra[uartId][UART_INT_0X55] != NULL) { - uartIntCbfArra[uartId][UART_INT_0X55](); - } - } -} - -void UART1_IRQHandler(void) -{ - UART_IntHandler(UART1_ID); -} - -void UART0_IRQHandler(void) -{ - UART_IntHandler(UART0_ID); -} - -#endif - -/****************************************************************************/ /** - * @brief Install uart interrupt callback function - * - * @param uartId: UART ID type - * @param intType: UART interrupt type - * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_Int_Callback_Install(UART_ID_Type uartId, UART_INT_Type intType, intCallback_Type *cbFun) -{ - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - CHECK_PARAM(IS_UART_INT_TYPE(intType)); - - uartIntCbfArra[uartId][intType] = cbFun; - - return SUCCESS; -} -//CLOCK -//EFUSE -//PDS -/****************************************************************************/ /** - * @brief PDS turn on USB - * - * @param waitReady : wait turn on usb finish - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type PDS_Turn_On_USB(uint8_t waitReady) -{ - uint32_t tmpVal = 0; - - /* USB_PHY_CTRL[3:2] reg_usb_phy_xtlsel=0 */ - /* 2000e504 = 0x40; #100; USB_PHY_CTRL[6] reg_pu_usb20_psw=1 (VCC33A) */ - /* 2000e504 = 0x41; #500; USB_PHY_CTRL[0] reg_usb_phy_ponrst=1 */ - /* 2000e500 = 0x20; #100; USB_CTL[0] reg_usb_sw_rst_n=0 */ - /* 2000e500 = 0x22; #500; USB_CTL[1] reg_usb_ext_susp_n=1 */ - /* 2000e500 = 0x23; #100; USB_CTL[0] reg_usb_sw_rst_n=1 */ - /* #1.2ms; wait UCLK */ - /* wait(soc616_b0.usb_uclk); */ - - tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_PHY_CTRL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_REG_USB_PHY_XTLSEL, 0); - BL_WR_REG(PDS_BASE, PDS_USB_PHY_CTRL, tmpVal); - - tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_PHY_CTRL); - tmpVal = BL_SET_REG_BIT(tmpVal, PDS_REG_PU_USB20_PSW); - BL_WR_REG(PDS_BASE, PDS_USB_PHY_CTRL, tmpVal); - - tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_PHY_CTRL); - tmpVal = BL_SET_REG_BIT(tmpVal, PDS_REG_USB_PHY_PONRST); - BL_WR_REG(PDS_BASE, PDS_USB_PHY_CTRL, tmpVal); - - /* greater than 5T */ - arch_delay_us(1); - - tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_CTL); - tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_REG_USB_SW_RST_N); - BL_WR_REG(PDS_BASE, PDS_USB_CTL, tmpVal); - - /* greater than 5T */ - arch_delay_us(1); - - tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_CTL); - tmpVal = BL_SET_REG_BIT(tmpVal, PDS_REG_USB_EXT_SUSP_N); - BL_WR_REG(PDS_BASE, PDS_USB_CTL, tmpVal); - - /* wait UCLK 1.2ms */ - arch_delay_ms(3); - - tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_CTL); - tmpVal = BL_SET_REG_BIT(tmpVal, PDS_REG_USB_SW_RST_N); - BL_WR_REG(PDS_BASE, PDS_USB_CTL, tmpVal); - - if (waitReady) { - arch_delay_ms(2); - } - - return SUCCESS; -} - -//HBN - -/****************************************************************************/ /** - * @brief Power on XTAL 32K - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_On_Xtal_32K(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(HBN_BASE, HBN_XTAL32K); - tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_XTAL32K_HIZ_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_XTAL32K); - tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_XTAL32K_BUF); - BL_WR_REG(HBN_BASE, HBN_XTAL32K, tmpVal); - - /* Delay >1s */ - arch_delay_us(1100); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Power off XTAL 32K - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_Off_Xtal_32K(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(HBN_BASE, HBN_XTAL32K); - tmpVal = BL_SET_REG_BIT(tmpVal, HBN_XTAL32K_HIZ_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_XTAL32K); - tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_XTAL32K_BUF); - BL_WR_REG(HBN_BASE, HBN_XTAL32K, tmpVal); - - return SUCCESS; -} - -/** - * @brief Power Off RC32K in all state - * - * @return BL_Err_Type - */ -BL_Err_Type ATTR_CLOCK_SECTION HBN_PD_RC32K_All_State(void) -{ - int32_t tmpVal = 0; - - tmpVal = BL_RD_REG(HBN_BASE, HBN_RTC_RST_CTRL2); - tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_RC32K); - BL_WR_REG(HBN_BASE, HBN_RTC_RST_CTRL2, tmpVal); - HBN_Power_Off_RC32K(); - return SUCCESS; -} - -/** - * @brief Power Off RC32K In power off state - * - * @return BL_Err_Type - */ -BL_Err_Type ATTR_CLOCK_SECTION HBN_PD_RC32K_In_Poff(void) -{ - int32_t tmpVal = 0; - - tmpVal = BL_RD_REG(HBN_BASE, HBN_RTC_RST_CTRL2); - tmpVal = BL_SET_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_RC32K); - BL_WR_REG(HBN_BASE, HBN_RTC_RST_CTRL2, tmpVal); - HBN_Power_Off_RC32K(); - return SUCCESS; -} - -/**************************************************************************** - * @brief HBN set ldo11_Rtc voltage out - * - * @param ldoLevel: LDO11_Rtc volatge level - * 0:0.60V 1:0.65V 2:0.70V 3:0.75V - * 4:0.80V 5:0.85V 6:0.9V 7:0.95V - * 8:1.0V 9:1.05V 10:1.1V 11:1.15V, - * 12:1.2V 13:1.25V 14:1.3V 15:1.35V - * - * @return SUCCESS or ERROR - * - *******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Rtc_Vout(HBN_LDO_LEVEL_Type ldoLevel) -{ - HBN_RTC_MISC_Type rtcMiscCfg; - - CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel)); - - HBN_Get_RTC_Misc_Cfg(&rtcMiscCfg); - rtcMiscCfg.ldo11RtcVoutSelRtc = ldoLevel; - HBN_Set_RTC_Misc_Cfg(&rtcMiscCfg); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief HBN set ldo11 all voltage out, not include dcdc11 - * - * @param ldoLevel: LDO volatge level - * - * @return SUCCESS or ERROR - * - * @note not support LDO11_Rtc 0.65v & 0.6v -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_All_Vout(HBN_LDO_LEVEL_Type ldoLevel) -{ - uint32_t tmpVal; - HBN_RTC_MISC_Type rtcMiscCfg; - - CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel)); - - tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11_AON_VOUT_SEL, ldoLevel); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11_RT_VOUT_SEL, ldoLevel); - BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); - - HBN_Get_RTC_Misc_Cfg(&rtcMiscCfg); - rtcMiscCfg.ldo11RtcVoutSelRtc = ldoLevel; - HBN_Set_RTC_Misc_Cfg(&rtcMiscCfg); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Get RTC misc config - * - * @param cfg: configuration - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION HBN_Get_RTC_Misc_Cfg(HBN_RTC_MISC_Type *cfg) -{ - uint32_t tmpVal = 0; - uint32_t *pCfg = (uint32_t *)cfg; - - if (!cfg) { - return ERROR; - } - - /* read [31:19] */ - tmpVal = BL_RD_REG(HBN_BASE, HBN_RTC_RST_CTRL); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, HBN_RTC_RST_CTRL_MISC); - - /* use [30:19] */ - *pCfg = tmpVal; - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Set RTC misc config - * - * @param cfg: configuration - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION HBN_Set_RTC_Misc_Cfg(HBN_RTC_MISC_Type *cfg) -{ - uint32_t tmpVal = 0; - - if (!cfg) { - return ERROR; - } - - /* read [31:19] */ - tmpVal = BL_RD_REG(HBN_BASE, HBN_RTC_RST_CTRL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_RTC_RST_CTRL_MISC, ((*(uint32_t *)cfg)<<1)); - BL_WR_REG(HBN_BASE, HBN_RTC_RST_CTRL, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief HBN enable ACOMP0 interrupt - * - * @param edge: HBN acomp interrupt edge type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type HBN_Enable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge) -{ - uint32_t tmpVal; - uint32_t tmpVal2; - - CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge)); - - tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); - tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN); - tmpVal2 = tmpVal2 | (1 << edge); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN, tmpVal2); - BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief HBN disable ACOMP0 interrupt - * - * @param edge: HBN acomp interrupt edge type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type HBN_Disable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge) -{ - uint32_t tmpVal; - uint32_t tmpVal2; - - CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge)); - - tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); - tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN); - tmpVal2 = tmpVal2 & (~(1 << edge)); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN, tmpVal2); - BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief HBN enable ACOMP1 interrupt - * - * @param edge: HBN acomp interrupt edge type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type HBN_Enable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge) -{ - uint32_t tmpVal; - uint32_t tmpVal2; - - CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge)); - - tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); - tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN); - tmpVal2 = tmpVal2 | (1 << edge); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN, tmpVal2); - BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief HBN disable ACOMP1 interrupt - * - * @param edge: HBN acomp interrupt edge type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type HBN_Disable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge) -{ - uint32_t tmpVal; - uint32_t tmpVal2; - - CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge)); - - tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); - tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN); - tmpVal2 = tmpVal2 & (~(1 << edge)); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN, tmpVal2); - BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); - - return SUCCESS; -} - -//AON -/****************************************************************************/ /** - * @brief AON set DCDC11_Top voltage out - * - * @param dcdcLevel: DCDC11_Top volatge level - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION AON_Set_DCDC11_Top_Vout(AON_DCDC_LEVEL_Type dcdcLevel) -{ - uint32_t tmpVal; - - CHECK_PARAM(IS_AON_DCDC_LEVEL_TYPE(dcdcLevel)); - - tmpVal = BL_RD_REG(AON_BASE, AON_DCDC_TOP_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_DCDC11_VOUT_SEL_AON, dcdcLevel); - BL_WR_REG(AON_BASE, AON_DCDC_TOP_0, tmpVal); - - return SUCCESS; -} -/****************************************************************************/ /** - * @brief delay us - * - * @param[in] core: systemcoreclock - * - * @param[in] cnt: delay cnt us - * - * @return none - * - *******************************************************************************/ -void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core, uint32_t cnt, uint32_t loopT) -{ - volatile uint32_t divVal = loopT; - volatile uint32_t speed = 0; - volatile uint32_t cycNum = 0; - - /* 1M=100K*10, so multiple is 10 */ - /* loop function take 4 instructions, so instructionNum is 4 */ - /* divVal = multiple*instructionNum */ - - if (core >= 1 * 1000 * 1000) { - /* CPU clock >= 1MHz */ - speed = core / (100 * 1000); - cycNum = speed * cnt; - cycNum = cycNum / 10; - cycNum = cycNum / divVal; - /* cycNum >= 0 */ - } else { - /* CPU clock < 1MHz */ - speed = core / 1000; - cycNum = speed * cnt; - cycNum = cycNum / 1000; - cycNum = cycNum / divVal; - /* cycNum >= 0 */ - } - - if (!cycNum) { - return; - } - - __asm__ __volatile__( - "mv a4,%0\n\t" - "li a5,0x0\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - ".align 4\n\t" - "1 :\n" - "beq a5,a4,2f\n\t" - "addi a5,a5,0x1\n\t" - "lui a3,0xF0000\n\t" - "lw a3,0(a3)\n\t" - "j 1b\n\t" - "nop\n\t" - "nop\n\t" - "2 :\n\t" - "nop\n" - : /* output */ - : "r"(cycNum) /* input */ - : "a3", "a4", "a5" /* destruct description */ - ); -} - -/****************************************************************************/ /** - * @brief delay us - * - * @param[in] cnt: delay cnt us - * - * @return none - * - *******************************************************************************/ -void ATTR_TCM_SECTION arch_delay_us(uint32_t cnt) -{ - GLB_CORE_ID_Type coreID; - uint32_t coreFreq; - uint32_t loopTick = 5; - uint32_t m0Cyc00[] = { 46, 46, 77, 85 }; - uint32_t m0Cyc10[] = { 10, 10, 77, 85 }; - uint32_t m0Cyc11[] = { 10, 10, 77, 85 }; - uint32_t d0Cyc00[] = { 5, 5, 62, 34 }; - uint32_t d0Cyc11[] = { 5, 5, 13, 13 }; - uint32_t lpCyc00[] = { 6, 6, 55, 85 }; - uint32_t *pCyc = NULL; - uint32_t iCacheEn = 1; - uint32_t dCacheEn = 1; - - /* requirement: icache enable && dcache enable */ - /* otherwise the latency depends on the code address */ - - coreID = GLB_Get_Core_Type(); - - if (GLB_CORE_ID_M0 == coreID) { - coreFreq = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_CLK); -#ifdef __RV32 - iCacheEn = (__get_MHCR() & CLIC_INTIE_IE_Msk) >> CLIC_INTIE_IE_Pos; - dCacheEn = (__get_MHCR() & CACHE_MHCR_DE_Msk) >> CACHE_MHCR_DE_Pos; -#endif - if (iCacheEn && dCacheEn) { - pCyc = m0Cyc11; - } else if (iCacheEn && !dCacheEn) { - pCyc = m0Cyc10; - } else if (!iCacheEn && !dCacheEn) { - pCyc = m0Cyc00; - } else { - pCyc = m0Cyc11; - } - } else if (GLB_CORE_ID_D0 == coreID) { - coreFreq = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_DSP_CLK); -#ifdef __RV64 - iCacheEn = (__get_MHCR() & CACHE_MHCR_IE_Msk) >> CACHE_MHCR_IE_Pos; - dCacheEn = (__get_MHCR() & CACHE_MHCR_DE_Msk) >> CACHE_MHCR_DE_Pos; -#endif - if (iCacheEn && dCacheEn) { - pCyc = d0Cyc11; - } else if (!iCacheEn && !dCacheEn) { - pCyc = d0Cyc00; - } else { - pCyc = d0Cyc11; - } - } else if (GLB_CORE_ID_LP == coreID) { - coreFreq = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_LP_CLK); - pCyc = lpCyc00; - } else { - coreFreq = 32 * 1000 * 1000; - pCyc = lpCyc00; - } - - switch (((uint32_t)&ASM_Delay_Us) >> 24) { - case 0x22: - loopTick = pCyc[0]; - break; - case 0x62: - loopTick = pCyc[0]; - break; - case 0x3F: - loopTick = pCyc[2]; - break; - case 0x3E: - loopTick = pCyc[3]; - break; - default: - break; - } - - coreFreq = coreFreq ? coreFreq : (32 * 1000 * 1000); - - ASM_Delay_Us(coreFreq, cnt, loopTick); -} - -/****************************************************************************/ /** - * @brief delay ms - * - * @param[in] cnt: delay cnt ms - * - * @return none - * - *******************************************************************************/ -void ATTR_TCM_SECTION arch_delay_ms(uint32_t cnt) -{ - uint32_t i = 0; - uint32_t count = 0; - - if (cnt >= 1024) { - /* delay (n*1024) ms */ - for (i = 0; i < (cnt / 1024); i++) { - arch_delay_us(1024 * 1000); - } - } - - count = cnt & 0x3FF; - - if (count) { - /* delay (1-1023)ms */ - arch_delay_us(count * 1000); - } -} - -/****************************************************************************/ /** - * @brief chip clock out0 select - * - * @param clkOutType: chip clock out0 output type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_Chip_Clock_Out0_Sel(GLB_CHIP_CLK_OUT_0_Type clkOutType) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2); - /* set clk out0 output enable */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_0_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_0_SEL, clkOutType); - BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief chip clock out1 select - * - * @param clkOutType: chip clock out1 output type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_Chip_Clock_Out1_Sel(GLB_CHIP_CLK_OUT_1_Type clkOutType) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2); - /* set clk out1 output enable */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_1_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_1_SEL, clkOutType); - BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief chip clock out2 select - * - * @param clkOutType: chip clock out2 output type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_Chip_Clock_Out2_Sel(GLB_CHIP_CLK_OUT_2_Type clkOutType) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2); - /* set clk out2 output enable */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_2_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_2_SEL, clkOutType); - BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief chip clock out3 select - * - * @param clkOutType: chip clock out3 output type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_Chip_Clock_Out3_Sel(GLB_CHIP_CLK_OUT_3_Type clkOutType) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2); - /* set clk out3 output enable */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_3_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_3_SEL, clkOutType); - BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal); - - return SUCCESS; -} - -//FLASH - -/****************************************************************************/ /** - * @brief GLB power on PLL - * - * @param pllType: PLL XTAL type - * @param cfg: GLB PLL configuration - * @param waitStable: wait PLL clock stable - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Power_On_WAC_PLL(GLB_WAC_PLL_Type pllType, const GLB_WAC_PLL_Cfg_Type *const cfg, uint8_t waitStable) -{ - uint32_t REG_PLL_BASE_ADDRESS = 0; - uint32_t tmpVal = 0; - - /* unknown */ - CHECK_PARAM(IS_GLB_WAC_PLL_TYPE(pllType)); - - switch (pllType) { - case GLB_WAC_PLL_WIFIPLL: - REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_WIFI_PLL_CFG0_OFFSET; - break; - case GLB_WAC_PLL_AUPLL: - REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_AUDIO_PLL_CFG0_OFFSET; - break; - case GLB_WAC_PLL_CPUPLL: - REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_CPU_PLL_CFG0_OFFSET; - break; - default: - REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_AUDIO_PLL_CFG0_OFFSET; - break; - } - - /* Step1:config parameter */ - /* cfg1:Set aupll_refclk_sel and aupll_refdiv_ratio */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_REFDIV_RATIO, cfg->basicCfg->clkpllRefdivRatio); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal); - - /* cfg2:Set aupll_int_frac_sw,aupll_icp_1u,aupll_icp_5u */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_INT_FRAC_SW, cfg->basicCfg->clkpllIntFracSw); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_ICP_1U, cfg->basicCfg->clkpllIcp1u); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_ICP_5U, cfg->basicCfg->clkpllIcp5u); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 2, tmpVal); - - /* cfg3:Set aupll_rz,aupll_cz,aupll_c3,aupll_r4_short,aupll_r4_en */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_RZ, cfg->basicCfg->clkpllRz); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_CZ, cfg->basicCfg->clkpllCz); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_C3, cfg->basicCfg->clkpllC3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_R4_SHORT, cfg->basicCfg->clkpllR4Short); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_C4_EN, cfg->basicCfg->clkpllC4En); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 3, tmpVal); - - /* cfg4:Set aupll_sel_sample_clk */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SEL_SAMPLE_CLK, cfg->basicCfg->clkpllSelSampleClk); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 4, tmpVal); - - /* cfg5:Set aupll_vco_speed */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 5); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_VCO_SPEED, cfg->basicCfg->clkpllVcoSpeed); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 5, tmpVal); - - /* cfg6:Set aupll_sdm_bypass,aupll_sdmin */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 6); - if (GLB_WAC_PLL_WIFIPLL == pllType) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_SDM_CTRL_HW, cfg->basicCfg->clkpllSdmCtrlHw); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_SDM_BYPASS, cfg->basicCfg->clkpllSdmBypass); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_SDMIN, cfg->clkpllSdmin); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_BYPASS, cfg->basicCfg->clkpllSdmBypass); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDMIN, cfg->clkpllSdmin); - } - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 6, tmpVal); - - /* Step2:config pu */ - /* cfg0 : pu_aupll_sfreg=1 */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL_SFREG, 1); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - - /* delay > 2us */ - arch_delay_us(3); - - /* cfg0 : pu_wifipll=1 */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL, 1); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - - /* delay > 2us */ - arch_delay_us(3); - - /* toggle sdm_reset (pulse 0 > 1us) */ - /* cfg0 : aupll_sdm_reset */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_RSTB, 1); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - arch_delay_us(2); - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_RSTB, 0); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - arch_delay_us(2); - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_RSTB, 1); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - - /* Step3:reset pll */ - /* cfg0 : toggle aupll_reset_fbdv, pulse 0 > 1us */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_FBDV_RSTB, 1); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - arch_delay_us(2); - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_FBDV_RSTB, 0); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - arch_delay_us(2); - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_FBDV_RSTB, 1); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - - /* aupll : cfg1, aupll_postdiv = 0x12 or 0x14 */ - if (GLB_WAC_PLL_AUPLL == pllType) { - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1); - if ((cfg->clkpllSdmin == 0x12D0E) || (cfg->clkpllSdmin == 0x1C395) || (cfg->clkpllSdmin == 0x17851) || (cfg->clkpllSdmin == 0x16944) || (cfg->clkpllSdmin == 0x115E5)) { - /* 451.548 */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_POSTDIV, 0x14); - } else { - /* 442.368 */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_POSTDIV, 0x12); - } - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal); - } - - /* Step4:enable output clock */ - /* wifipll : cfg5, wifipll_vco_div3_en=1 */ - if (GLB_WAC_PLL_WIFIPLL == pllType) { - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 5); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_VCO_DIV3_EN); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 5, tmpVal); - } - /* cfg8 : wifipll->wifipll_en_ctrl_hw=1 */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 8); - if (GLB_WAC_PLL_WIFIPLL == pllType) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_EN_CTRL_HW, 1); - } - /* cfg8 : wifipll/aupll/cpupll clock enable */ - switch (pllType) { - case GLB_WAC_PLL_WIFIPLL: - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV4); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV5); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV6); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV8); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV10); - break; - case GLB_WAC_PLL_AUPLL: - tmpVal = BL_SET_REG_BIT(tmpVal, CCI_AUPLL_EN_DIV1); - tmpVal = BL_SET_REG_BIT(tmpVal, CCI_AUPLL_EN_DIV2); - tmpVal = BL_SET_REG_BIT(tmpVal, CCI_AUPLL_EN_DIV2P5); - tmpVal = BL_SET_REG_BIT(tmpVal, CCI_AUPLL_EN_DIV5); - tmpVal = BL_SET_REG_BIT(tmpVal, CCI_AUPLL_EN_DIV6); - break; - case GLB_WAC_PLL_CPUPLL: - tmpVal = BL_SET_REG_BIT(tmpVal, CCI_CPUPLL_EN_DIV1); - tmpVal = BL_SET_REG_BIT(tmpVal, CCI_CPUPLL_EN_DIV2); - tmpVal = BL_SET_REG_BIT(tmpVal, CCI_CPUPLL_EN_DIV2P5); - tmpVal = BL_SET_REG_BIT(tmpVal, CCI_CPUPLL_EN_DIV4); - tmpVal = BL_SET_REG_BIT(tmpVal, CCI_CPUPLL_EN_DIV5); - break; - default: - break; - } - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 8, tmpVal); - - if (waitStable) { - /* Wait 1.5*30us */ - arch_delay_us(45); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief GLB wifi audio cpu PLL ref clock select - * - * @param pllType: PLL XTAL type - * @param refClk: PLL ref clock select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_Type pllType, GLB_PLL_REF_CLK_Type refClk) -{ - uint32_t REG_PLL_BASE_ADDRESS = 0; - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_WAC_PLL_TYPE(pllType)); - CHECK_PARAM(IS_GLB_PLL_REF_CLK_TYPE(refClk)); - - switch (pllType) { - case GLB_WAC_PLL_WIFIPLL: - REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_WIFI_PLL_CFG0_OFFSET; - break; - case GLB_WAC_PLL_AUPLL: - REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_AUDIO_PLL_CFG0_OFFSET; - break; - case GLB_WAC_PLL_CPUPLL: - REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_CPU_PLL_CFG0_OFFSET; - break; - default: - REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_AUDIO_PLL_CFG0_OFFSET; - break; - } - - /* xxxpll_refclk_sel */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1); - if ((GLB_WAC_PLL_WIFIPLL == pllType) && (GLB_PLL_REFCLK_XTAL == refClk)) { - /* wifipll_refclk_sel different from other's pll, 1 means xtal */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_REFCLK_SEL, 1); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_REFCLK_SEL, refClk); - } - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief GLB mipi uhs PLL ref clock select - * - * @param pllType: PLL XTAL type - * @param refClk: PLL ref clock select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_MU_PLL_Ref_Clk_Sel(GLB_MU_PLL_Type pllType, GLB_PLL_REF_CLK_Type refClk) -{ - uint32_t REG_PLL_BASE_ADDRESS = 0; - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_WAC_PLL_TYPE(pllType)); - CHECK_PARAM(IS_GLB_PLL_REF_CLK_TYPE(refClk)); - - switch (pllType) { - case GLB_MU_PLL_MIPIPLL: - REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET; - break; - case GLB_MU_PLL_UHSPLL: - REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_UHS_PLL_CFG0_OFFSET; - break; - default: - REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET; - break; - } - - /* xxxpll_refclk_sel */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_REFCLK_SEL, refClk); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief reconfigure WIFIPLL clock - * - * @param xtalType: XTAL frequency type - * @param pllCfg: PLL configuration - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_WIFI_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type * pllCfgList) -{ - GLB_PLL_REF_CLK_Type refClk; - - if (xtalType == GLB_XTAL_RC32M) { - refClk = GLB_PLL_REFCLK_RC32M; - } else { - refClk = GLB_PLL_REFCLK_XTAL; - } - - GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_WIFIPLL); - GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_WIFIPLL, refClk); - GLB_Power_On_WAC_PLL(GLB_WAC_PLL_WIFIPLL, &(pllCfgList[xtalType]), 1); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief reconfigure AUPLL clock - * - * @param xtalType: XTAL frequency type - * @param pllCfg: PLL configuration - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_AUDIO_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type * pllCfgList) -{ - GLB_PLL_REF_CLK_Type refClk; - - if (xtalType == GLB_XTAL_RC32M) { - refClk = GLB_PLL_REFCLK_RC32M; - } else { - refClk = GLB_PLL_REFCLK_XTAL; - } - - GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_AUPLL); - GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_AUPLL, refClk); - GLB_Power_On_WAC_PLL(GLB_WAC_PLL_AUPLL, &(pllCfgList[xtalType]), 1); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief reconfigure CPUPLL clock - * - * @param xtalType: XTAL frequency type - * @param pllCfg: PLL configuration - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_CPU_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type * pllCfgList) -{ - GLB_PLL_REF_CLK_Type refClk; - - if (xtalType == GLB_XTAL_RC32M) { - refClk = GLB_PLL_REFCLK_RC32M; - } else { - refClk = GLB_PLL_REFCLK_XTAL; - } - - GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_CPUPLL); - GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_CPUPLL, refClk); - GLB_Power_On_WAC_PLL(GLB_WAC_PLL_CPUPLL, &(pllCfgList[xtalType]), 1); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief reconfigure MIPIPLL clock - * - * @param xtalType: XTAL frequency type - * @param pllCfg: PLL configuration - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_MIPI_PLL(GLB_XTAL_Type xtalType, const GLB_MU_PLL_Cfg_Type * pllCfgList) -{ - GLB_PLL_REF_CLK_Type refClk; - - if (xtalType == GLB_XTAL_RC32M) { - refClk = GLB_PLL_REFCLK_RC32M; - } else { - refClk = GLB_PLL_REFCLK_XTAL; - } - - GLB_Power_Off_MU_PLL(GLB_MU_PLL_MIPIPLL); - GLB_MU_PLL_Ref_Clk_Sel(GLB_MU_PLL_MIPIPLL, refClk); - GLB_Power_On_MU_PLL(GLB_MU_PLL_MIPIPLL, &(pllCfgList[xtalType]), 1); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief reconfigure MIPIPLL clock div - * - * @param divEn: div enable - * @param divRatio: div ratio - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_MIPI_PLL_Div(uint8_t divEn, uint8_t divRatio) -{ - uint32_t REG_PLL_BASE_ADDRESS = 0; - uint32_t tmpVal = 0; - - REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET; - - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_MIPIPLL_EVEN_DIV_EN, divEn); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_MIPIPLL_EVEN_DIV_RATIO, divRatio); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief reconfigure UHSPLL clock - * - * @param xtalType: XTAL frequency type - * @param pllCfg: PLL configuration - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_UHS_PLL(GLB_XTAL_Type xtalType, const GLB_MU_PLL_Cfg_Type * pllCfgList) -{ - GLB_PLL_REF_CLK_Type refClk; - - if (xtalType == GLB_XTAL_RC32M) { - refClk = GLB_PLL_REFCLK_RC32M; - } else { - refClk = GLB_PLL_REFCLK_XTAL; - } - - GLB_Power_Off_MU_PLL(GLB_MU_PLL_UHSPLL); - GLB_MU_PLL_Ref_Clk_Sel(GLB_MU_PLL_UHSPLL, refClk); - GLB_Power_On_MU_PLL(GLB_MU_PLL_UHSPLL, &(pllCfgList[xtalType]), 1); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief GLB set display clock - * - * @param enable: ENABLE or DISABLE - * @param srcClk: source clock type - * @param evenDiv: divider in even number - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_Display_CLK(uint8_t enable, GLB_DISP_CLK_Type srcClk, uint8_t evenDiv) -{ - uint32_t tmpVal = 0; - uint32_t evenNum = 0; - - CHECK_PARAM(IS_GLB_DISP_CLK_TYPE(srcClk)); - CHECK_PARAM((evenDiv <= 0x7F)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_MIPI_PLL_CFG1); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_MIPIPLL_EVEN_DIV_EN); - BL_WR_REG(GLB_BASE, GLB_MIPI_PLL_CFG1, tmpVal); - - if ((evenDiv >= 8) && (evenDiv <= 126)) { - evenNum = evenDiv & ~(1 << 0); - } else { - evenNum = evenDiv; - } - - tmpVal = BL_RD_REG(GLB_BASE, GLB_MIPI_PLL_CFG1); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_MIPIPLL_EVEN_DIV_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_MIPIPLL_EVEN_DIV_EN); - } - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_MIPIPLL_EVEN_DIV_RATIO, evenNum); - BL_WR_REG(GLB_BASE, GLB_MIPI_PLL_CFG1, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Erase flash one 32K block - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param blkNum: flash 32K block number - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION SFlash_Blk32_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum) -{ - uint32_t cnt = 0; - uint8_t is32BitsAddr = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - BL_Err_Type stat = SFlash_Write_Enable(flashCfg); - - if (stat != SUCCESS) { - return stat; - } - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - is32BitsAddr = (flashCfg->ioMode & 0x20); - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = 3; - - if (is32BitsAddr > 0) { - flashCmd.addrSize++; - flashCmd.cmdBuf[0] = (flashCfg->blk32EraseCmd << 24) | ((BFLB_SPIFLASH_BLK32K_SIZE * blkNum) >> 8); - flashCmd.cmdBuf[1] = ((BFLB_SPIFLASH_BLK32K_SIZE * blkNum) << 24); - } else { - flashCmd.cmdBuf[0] = (flashCfg->blk32EraseCmd << 24) | (BFLB_SPIFLASH_BLK32K_SIZE * blkNum); - } - - SF_Ctrl_SendCmd(&flashCmd); - - while (SET == SFlash_Busy(flashCfg)) { - arch_delay_us(500); - cnt++; - - if (cnt > flashCfg->timeE32k * 3) { - return ERROR; - } - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Erase flash one region - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param startaddr: start address to erase - * @param endaddr: end address(include this address) to erase - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION SFlash_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t startaddr, uint32_t endaddr) -{ - uint32_t len = 0; - uint32_t eraseLen = 0; - BL_Err_Type ret = SUCCESS; - - if (startaddr > endaddr) { - return ERROR; - } - - while (startaddr <= endaddr) { - len = endaddr - startaddr + 1; - - if (flashCfg->blk64EraseCmd != BFLB_SPIFLASH_CMD_INVALID && - (startaddr & (BFLB_SPIFLASH_BLK64K_SIZE - 1)) == 0 && - len > (BFLB_SPIFLASH_BLK64K_SIZE - flashCfg->sectorSize * 1024)) { - /* 64K margin address,and length > 64K-sector size, erase one first */ - ret = SFlash_Blk64_Erase(flashCfg, startaddr / BFLB_SPIFLASH_BLK64K_SIZE); - eraseLen = BFLB_SPIFLASH_BLK64K_SIZE; - } else if (flashCfg->blk32EraseCmd != BFLB_SPIFLASH_CMD_INVALID && - (startaddr & (BFLB_SPIFLASH_BLK32K_SIZE - 1)) == 0 && - len > (BFLB_SPIFLASH_BLK32K_SIZE - flashCfg->sectorSize * 1024)) { - /* 32K margin address,and length > 32K-sector size, erase one first */ - ret = SFlash_Blk32_Erase(flashCfg, startaddr / BFLB_SPIFLASH_BLK32K_SIZE); - eraseLen = BFLB_SPIFLASH_BLK32K_SIZE; - } else { - /* Sector erase */ - startaddr = ((startaddr) & (~(flashCfg->sectorSize * 1024 - 1))); - ret = SFlash_Sector_Erase(flashCfg, startaddr / flashCfg->sectorSize / 1024); - eraseLen = flashCfg->sectorSize * 1024; - } - - startaddr += eraseLen; - - if (ret != SUCCESS) { - return ERROR; - } - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Erase flash one region - * - * @param pFlashCfg: Flash config pointer - * @param startaddr: start address to erase - * @param len: data length to erase - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Erase_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t startaddr, int len, - uint8_t group, SF_Ctrl_Bank_Select bank) -{ - BL_Err_Type stat; - uint32_t offset; - uint8_t aesEnable = 0; - SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf; - - XIP_SFlash_Opt_Enter(&aesEnable); - stat = XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank); - - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank); - } else { - stat = SFlash_Erase(pFlashCfg, startaddr, startaddr + len - 1); - XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank); - } - - XIP_SFlash_Opt_Exit(aesEnable); - - return stat; -} - -/****************************************************************************/ /** - * @brief Get flash config according to flash ID patch - * - * @param flashID: Flash ID - * @param pFlashCfg: Flash config pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg, - uint8_t group, SF_Ctrl_Bank_Select bank) -{ - uint32_t i; - uint8_t buf[sizeof(SPI_Flash_Cfg_Type) + 8]; - uint32_t crc, *pCrc; - uint32_t xipOffset; - char flashCfgMagic[] = "FCFG"; - - if (flashID == 0) { - xipOffset = SF_Ctrl_Get_Flash_Image_Offset(group, bank); - SF_Ctrl_Set_Flash_Image_Offset(0, group, bank); - XIP_SFlash_Read_Via_Cache_Need_Lock(8 + BL808_FLASH_XIP_BASE, buf, sizeof(SPI_Flash_Cfg_Type) + 8, group, bank); - SF_Ctrl_Set_Flash_Image_Offset(xipOffset, group, bank); - - if (ARCH_MemCmp(buf, flashCfgMagic, 4) == 0) { - crc = BFLB_Soft_CRC32((uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type)); - pCrc = (uint32_t *)(buf + 4 + sizeof(SPI_Flash_Cfg_Type)); - - if (*pCrc == crc) { - ARCH_MemCpy_Fast(pFlashCfg, (uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type)); - return SUCCESS; - } - } - } else { - if(RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock(flashID, pFlashCfg, group, bank) == SUCCESS){ - return SUCCESS; - } - for (i = 0; i < sizeof(flashInfos) / sizeof(flashInfos[0]); i++) { - if (flashInfos[i].jedecID == flashID) { - ARCH_MemCpy_Fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type)); - return SUCCESS; - } - } - } - - return ERROR; -} - -/****************************************************************************/ /** - * @brief Identify one flash patch - * - * @param callFromFlash: code run at flash or ram - * @param flashPinCfg: Bit 7: autoscan, Bit6-0: flash GPIO config - * @param restoreDefault: Wether restore default flash GPIO config - * @param pFlashCfg: Flash config pointer - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return Flash ID - * -*******************************************************************************/ -uint32_t ATTR_TCM_SECTION SF_Cfg_Flash_Identify_Ext(uint8_t callFromFlash, uint8_t flashPinCfg, - uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank) -{ - uint32_t jdecId = 0; - uint32_t i = 0; - uint32_t ret = 0; - - ret = SF_Cfg_Flash_Identify(callFromFlash, flashPinCfg, restoreDefault, pFlashCfg, group, bank); - if(callFromFlash){ - SFlash_Set_IDbus_Cfg(pFlashCfg, pFlashCfg->ioMode&0xf , 1, 0, 32, bank); - } - if((ret&BFLB_FLASH_ID_VALID_FLAG) != 0){ - return ret; - } - - jdecId = (ret&0xffffff); - for(i=0; i
© COPYRIGHT(c) 2020 Bouffalo Lab
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "string.h" -#include "bl808_sec_dbg.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup SEC_DBG - * @{ - */ - -/** @defgroup SEC_DBG_Private_Macros - * @{ - */ - -/*@} end of group SEC_DBG_Private_Macros */ - -/** @defgroup SEC_DBG_Private_Types - * @{ - */ - -/*@} end of group SEC_DBG_Private_Types */ - -/** @defgroup SEC_DBG_Private_Variables - * @{ - */ - -/*@} end of group SEC_DBG_Private_Variables */ - -/** @defgroup SEC_DBG_Global_Variables - * @{ - */ - -/*@} end of group SEC_DBG_Global_Variables */ - -/** @defgroup SEC_DBG_Private_Fun_Declaration - * @{ - */ - -/*@} end of group SEC_DBG_Private_Fun_Declaration */ - -/** @defgroup SEC_DBG_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Sec Dbg read chip ID - * - * @param id[8]: chip ID buffer - * - * @return None - * -*******************************************************************************/ -void Sec_Dbg_Read_Chip_ID(uint8_t id[8]) -{ - uint32_t idLow, idHigh; - - idLow = BL_RD_REG(SEC_DBG_BASE, SEC_DBG_SD_CHIP_ID_LOW); - BL_WRWD_TO_BYTEP(id, idLow); - - idHigh = BL_RD_REG(SEC_DBG_BASE, SEC_DBG_SD_CHIP_ID_HIGH); - BL_WRWD_TO_BYTEP((id + 4), idHigh); -} - -/***************************************************************************** / - * @brief Sec Dbg set PWD - * - * @param pwd: PWD buffer - * - * @return None - * -*******************************************************************************/ -void Sec_Dbg_Set_Dbg_Pwd(const uint32_t pwd[4]) -{ - BL_WR_REG(SEC_DBG_BASE, SEC_DBG_SD_DBG_PWD_LOW, pwd[0]); - BL_WR_REG(SEC_DBG_BASE, SEC_DBG_SD_DBG_PWD_HIGH, pwd[1]); - BL_WR_REG(SEC_DBG_BASE, SEC_DBG_SD_DBG_PWD2_LOW, pwd[2]); - BL_WR_REG(SEC_DBG_BASE, SEC_DBG_SD_DBG_PWD2_HIGH, pwd[3]); -} - -/****************************************************************************/ /** - * @brief Sec Dbg read debug mode - * - * @param None - * - * @return debug mode status - * -*******************************************************************************/ -uint32_t Sec_Dbg_Read_Dbg_Mode(void) -{ - return BL_GET_REG_BITS_VAL(BL_RD_REG(SEC_DBG_BASE, SEC_DBG_SD_STATUS), SEC_DBG_SD_DBG_MODE); -} - -/****************************************************************************/ /** - * @brief Sec Dbg read debug enable status - * - * @param None - * - * @return enable status - * -*******************************************************************************/ -uint32_t Sec_Dbg_Read_Dbg_Enable(void) -{ - return BL_GET_REG_BITS_VAL(BL_RD_REG(SEC_DBG_BASE, SEC_DBG_SD_STATUS), SEC_DBG_SD_DBG_ENA); -} - -/****************************************************************************/ /** - * @brief Sec Dbg Set debug trigger status - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Sec_Dbg_Set_Dbg_Trigger(void) -{ - uint32_t tmpVal=0; - tmpVal=BL_RD_REG(SEC_DBG_BASE, SEC_DBG_SD_STATUS); - tmpVal=BL_SET_REG_BIT(tmpVal,SEC_DBG_SD_DBG_PWD_TRIG); - BL_WR_REG(SEC_DBG_BASE, SEC_DBG_SD_STATUS,tmpVal); -} - -/*@} end of group SEC_DBG_Public_Functions */ - -/*@} end of group SEC_DBG */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sec_eng.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sec_eng.c deleted file mode 100644 index 8e12b99b16..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sec_eng.c +++ /dev/null @@ -1,5135 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_sec_eng.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "string.h" -#include "bl808_sec_eng.h" -#include "bl808_tzc_sec.h" -#include "bl808_l1c.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup SEC_ENG - * @{ - */ - -/** @defgroup SEC_ENG_Private_Macros - * @{ - */ -#define PUT_UINT32_BE(n, b, i) \ - { \ - (b)[(i)] = (uint8_t)((n) >> 24); \ - (b)[(i) + 1] = (uint8_t)((n) >> 16); \ - (b)[(i) + 2] = (uint8_t)((n) >> 8); \ - (b)[(i) + 3] = (uint8_t)((n)); \ - } -#define PUT_UINT32(n, b, i) \ - { \ - (b)[(i) + 3] = (uint8_t)((n) >> 24); \ - (b)[(i) + 2] = (uint8_t)((n) >> 16); \ - (b)[(i) + 1] = (uint8_t)((n) >> 8); \ - (b)[(i) + 0] = (uint8_t)((n)); \ - } -#define PUT_UINT64_BE(n, b, i) \ - { \ - (b)[(i)] = (uint8_t)((n) >> 56); \ - (b)[(i) + 1] = (uint8_t)((n) >> 48); \ - (b)[(i) + 2] = (uint8_t)((n) >> 40); \ - (b)[(i) + 3] = (uint8_t)((n) >> 32); \ - (b)[(i) + 4] = (uint8_t)((n) >> 24); \ - (b)[(i) + 5] = (uint8_t)((n) >> 16); \ - (b)[(i) + 6] = (uint8_t)((n) >> 8); \ - (b)[(i) + 7] = (uint8_t)((n)); \ - } -#define SEC_ENG_SHA_BUSY_TIMEOUT_COUNT (100 * 320 * 1000) -#define SEC_ENG_AES_BUSY_TIMEOUT_COUNT (100 * 320 * 1000) -#define SEC_ENG_TRNG_BUSY_TIMEOUT_COUNT (100 * 320 * 1000) -#define SEC_ENG_PKA_INT_TIMEOUT_COUNT (100 * 320 * 1000) -#define SEC_ENG_GMAC_BUSY_TIMEOUT_COUNT (100 * 320 * 1000) - -/*@} end of group SEC_ENG_Private_Macros */ - -/** @defgroup SEC_ENG_Private_Types - * @{ - */ -struct pka0_pld_cfg { - union { - struct - { - uint32_t size : 12; /*[11: 0], r/w, 0x0 */ - uint32_t d_reg_index : 8; /*[19:12], r/w, 0x0 */ - uint32_t d_reg_type : 4; /*[23:20], r/w, 0x0 */ - uint32_t op : 7; /*[30:24], r/w, 0x0 */ - uint32_t last_op : 1; /*[31:31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } value; -}; - -struct pka0_pldi_cfg { - union { - struct - { - uint32_t rsvd : 12; /*[11: 0], r/w, 0x0 */ - uint32_t d_reg_index : 8; /*[19:12], r/w, 0x0 */ - uint32_t d_reg_type : 4; /*[23:20], r/w, 0x0 */ - uint32_t op : 7; /*[30:24], r/w, 0x0 */ - uint32_t last_op : 1; /*[31:31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } value; -}; - -struct pka0_common_op_first_cfg { - union { - struct - { - uint32_t s0_reg_idx : 8; /*[7: 0], r/w, 0x0 */ - uint32_t s0_reg_type : 4; /*[11:8], r/w, 0x0 */ - uint32_t d_reg_idx : 8; /*[19:12], r/w, 0x0 */ - uint32_t d_reg_type : 4; /*[23:20], r/w, 0x0 */ - uint32_t op : 7; /*[30:24], r/w, 0x0 */ - uint32_t last_op : 1; /*[31:31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } value; -}; - -struct pka0_common_op_snd_cfg_S1_only { - union { - struct - { - uint32_t reserved_0_11 : 12; /*[11: 0], rsvd, 0x0 */ - uint32_t s1_reg_idx : 8; /*[19:12], r/w, 0x0 */ - uint32_t s1_reg_type : 4; /*[23:20], r/w, 0x0 */ - uint32_t reserved_24_31 : 8; /*[31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } value; -}; - -struct pka0_common_op_snd_cfg_S2_only { - union { - struct - { - uint32_t s2_reg_idx : 8; /*[7 : 0], r/w, 0x0 */ - uint32_t s2_reg_type : 4; /*[11: 8], r/w, 0x0 */ - uint32_t reserved_12_31 : 20; /*[31:12], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } value; -}; - -struct pka0_common_op_snd_cfg_S1_S2 { - union { - struct - { - uint32_t s2_reg_idx : 8; /*[7 : 0], r/w, 0x0 */ - uint32_t s2_reg_type : 4; /*[11: 8], r/w, 0x0 */ - uint32_t s1_reg_idx : 8; /*[19:12], r/w, 0x0 */ - uint32_t s1_reg_type : 4; /*[23:20], r/w, 0x0 */ - uint32_t reserved_24_31 : 8; /*[31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } value; -}; - -struct pka0_bit_shift_op_cfg { - union { - struct - { - uint32_t bit_shift : 15; /*[14: 0], r/w, 0x0 */ - uint32_t reserved_24_31 : 17; /*[31:15], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } value; -}; - -/*@} end of group SEC_ENG_Private_Types */ - -/** @defgroup SEC_ENG_Private_Variables - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -static intCallback_Type *secEngIntCbfArra[SEC_ENG_INT_ALL] = { NULL }; -#endif - -/*@} end of group SEC_ENG_Private_Variables */ - -/** @defgroup SEC_ENG_Global_Variables - * @{ - */ - -/*@} end of group SEC_ENG_Global_Variables */ - -/** @defgroup SEC_ENG_Private_Fun_Declaration - * @{ - */ - -/*@} end of group SEC_ENG_Private_Fun_Declaration */ - -/** @defgroup SEC_ENG_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief SHA256 initialization function - * - * @param shaCtx: SHA256 context pointer - * @param shaNo: SHA ID type - * @param shaType: SHA type - * @param shaTmpBuf[16]: SHA temp buffer for store data that is less than 64 bytes - * @param padding[16]: SHA padding buffer for store padding data - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_SHA256_Init(SEC_Eng_SHA256_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, SEC_ENG_SHA_Type shaType, uint32_t shaTmpBuf[16], uint32_t padding[16]) -{ - uint32_t SHAx = SEC_ENG_BASE; - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); - CHECK_PARAM(IS_SEC_ENG_SHA_TYPE(shaType)); - - /* Deal SHA control register to set SHA mode */ - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - - if (shaType < 8) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MODE_EXT, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MODE, shaType); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MODE_EXT, shaType - 7); - } - - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal); - - /* Clear context */ - ARCH_MemSet(shaCtx, 0, sizeof(SEC_Eng_SHA256_Ctx)); - - /* Init temp buffer and padding buffer */ - shaCtx->shaBuf = shaTmpBuf; - shaCtx->shaPadding = padding; - ARCH_MemSet(shaCtx->shaPadding, 0, 64); - ARCH_MemSet(shaCtx->shaPadding, 0x80, 1); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(SEC_ENG_ID0_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_SHA_IRQHandler); -#endif -} - -/****************************************************************************/ /** - * @brief SHA512 initialization function - * - * @param shaCtx: SHA512 context pointer - * @param shaNo: SHA ID type - * @param shaType: SHA type - * @param shaTmpBuf[16]: SHA temp buffer for store data that is less that 128 bytes - * @param padding[16]: SHA padding buffer for store padding data - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_SHA512_Init(SEC_Eng_SHA512_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, SEC_ENG_SHA_Type shaType, uint64_t shaTmpBuf[16], uint64_t padding[16]) -{ - uint32_t SHAx = SEC_ENG_BASE; - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); - CHECK_PARAM(IS_SEC_ENG_SHA_TYPE(shaType)); - - /* Deal SHA control register to set SHA mode */ - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - - if (shaType < 8) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MODE_EXT, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MODE, shaType); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MODE_EXT, shaType - 7); - } - - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal); - - /* Clear context */ - ARCH_MemSet(shaCtx, 0, sizeof(SEC_Eng_SHA512_Ctx)); - - /* Init temp buffer and padding buffer */ - shaCtx->shaBuf = shaTmpBuf; - shaCtx->shaPadding = padding; - ARCH_MemSet(shaCtx->shaPadding, 0, 128); - ARCH_MemSet(shaCtx->shaPadding, 0x80, 1); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(SEC_ENG_ID0_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_SHA_IRQHandler); - Interrupt_Handler_Register(SEC_ENG_ID1_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_SHA_IRQHandler); -#endif -} - -/****************************************************************************/ /** - * @brief MD5 initialization function - * - * @param md5Ctx: MD5 context pointer - * @param shaNo: SHA ID type - * @param shaType: SHA type - * @param md5TmpBuf[16]: MD5 temp buffer for store data that is less that 64 bytes - * @param padding[16]: MD5 padding buffer for store padding data - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_MD5_Init(SEC_Eng_MD5_Ctx *md5Ctx, SEC_ENG_SHA_ID_Type shaNo, SEC_ENG_SHA_Type shaType, uint32_t md5TmpBuf[16], uint32_t padding[16]) -{ - uint32_t SHAx = SEC_ENG_BASE; - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); - CHECK_PARAM(IS_SEC_ENG_SHA_TYPE(shaType)); - - /* Deal SHA control register to set SHA mode */ - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - - if (shaType < 8) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MODE_EXT, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MODE, shaType); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MODE_EXT, shaType - 7); - } - - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal); - - /* Clear context */ - ARCH_MemSet(md5Ctx, 0, sizeof(SEC_Eng_MD5_Ctx)); - - /* Init temp buffer and padding buffer */ - md5Ctx->md5Buf = md5TmpBuf; - md5Ctx->md5Padding = padding; - ARCH_MemSet(md5Ctx->md5Padding, 0, 64); - ARCH_MemSet(md5Ctx->md5Padding, 0x80, 1); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(SEC_ENG_ID0_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_SHA_IRQHandler); - Interrupt_Handler_Register(SEC_ENG_ID1_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_SHA_IRQHandler); -#endif -} - -/****************************************************************************/ /** - * @brief SHA start function - * - * @param shaNo: SHA ID type - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_SHA_Start(SEC_ENG_SHA_ID_Type shaNo) -{ - uint32_t SHAx = SEC_ENG_BASE; - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); - - /* Set SHA enable */ - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_EN); - /* Hash sel 0 for new start */ - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_HASH_SEL); - - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal); -} - -/****************************************************************************/ /** - * @brief SHA256 update input data function - * - * @param shaCtx: SHA256 context pointer - * @param shaNo: SHA ID type - * @param input: SHA input data pointer, and the address should be word align - * @param len: SHA input data length - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_SHA256_Update(SEC_Eng_SHA256_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, const uint8_t *input, uint32_t len) -{ - uint32_t SHAx = SEC_ENG_BASE; - uint32_t tmpVal; - uint32_t fill; - uint32_t left; - uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - if (len == 0) { - return SUCCESS; - } - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* SHA need set se_sha_sel to 1 to keep the last SHA state */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_HASH_SEL, shaCtx->shaFeed); - - left = shaCtx->total[0] & 0x3F; - fill = 64 - left; - - shaCtx->total[0] += (uint32_t)len; - shaCtx->total[0] &= 0xFFFFFFFF; - - if (shaCtx->total[0] < (uint32_t)len) { - shaCtx->total[1]++; - } - - if (left && len >= fill) { - ARCH_MemCpy_Fast((void *)((uint8_t *)shaCtx->shaBuf + left), input, fill); - /* Set data source address */ - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_MSA, (uintptr_t)shaCtx->shaBuf); - - /* Set data length */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MSG_LEN, 1); - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal); - - /* Trigger */ - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T); - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal); - - shaCtx->shaFeed = 1; - input += fill; - len -= fill; - left = 0; - } - - fill = len / 64; - len = len % 64; - - if (fill > 0) { - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* SHA need set se_sha_sel to 1 to keep the last sha state */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_HASH_SEL, shaCtx->shaFeed); - - /* Fill data */ - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_MSA, (uintptr_t)input); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MSG_LEN, fill); - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal); - - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T); - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal); - - input += (fill * 64); - shaCtx->shaFeed = 1; - } - - if (len > 0) { - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* Copy left data into temp buffer */ - ARCH_MemCpy_Fast((void *)((uint8_t *)shaCtx->shaBuf + left), input, len); - } - - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief SHA512 update input data function - * - * @param shaCtx: SHA512 context pointer - * @param shaNo: SHA ID type - * @param input: SHA input data pointer, and the address should be word align - * @param len: SHA input data length - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_SHA512_Update(SEC_Eng_SHA512_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, const uint8_t *input, uint64_t len) -{ - uint32_t SHAx = SEC_ENG_BASE; - uint32_t tmpVal; - uint32_t fill; - uint32_t left; - uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - if (len == 0) { - return SUCCESS; - } - - if ((((uintptr_t)input) & 0x07) != 0) { - return ERROR; - } - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* SHA need set se_sha_sel to 1 to keep the last SHA state */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_HASH_SEL, shaCtx->shaFeed); - - left = shaCtx->total[0] & 0x7F; - fill = 128 - left; - - shaCtx->total[0] += (uint64_t)len; - - if (shaCtx->total[0] < (uint64_t)len) { - shaCtx->total[1]++; - } - - if (left && len >= fill) { - ARCH_MemCpy_Fast((void *)((uint8_t *)shaCtx->shaBuf + left), input, fill); - /* Set data source address */ - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_MSA, (uintptr_t)shaCtx->shaBuf); - - /* Set data length */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MSG_LEN, 1); - - /* Trigger */ - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T); - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal); - - shaCtx->shaFeed = 1; - input += fill; - len -= fill; - left = 0; - } - - fill = len / 128; - len = len % 128; - - if (fill > 0) { - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* SHA need set se_sha_sel to 1 to keep the last sha state */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_HASH_SEL, shaCtx->shaFeed); - - /* Fill data */ - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_MSA, (uintptr_t)input); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MSG_LEN, fill); - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T); - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal); - - input += (fill * 128); - shaCtx->shaFeed = 1; - } - - if (len > 0) { - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* Copy left data into temp buffer */ - ARCH_MemCpy_Fast((void *)((uint8_t *)shaCtx->shaBuf + left), input, len); - } - - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief MD5 update input data function - * - * @param md5Ctx: MD5 context pointer - * @param shaNo: SHA ID type - * @param input: SHA input data pointer, and the address should be word align - * @param len: SHA input data length - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_MD5_Update(SEC_Eng_MD5_Ctx *md5Ctx, SEC_ENG_SHA_ID_Type shaNo, const uint8_t *input, uint32_t len) -{ - uint32_t SHAx = SEC_ENG_BASE; - uint32_t tmpVal; - uint32_t fill; - uint32_t left; - uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - if (len == 0) { - return SUCCESS; - } - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* SHA need set se_sha_sel to 1 to keep the last SHA state */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_HASH_SEL, md5Ctx->md5Feed); - - left = md5Ctx->total[0] & 0x3F; - fill = 64 - left; - - md5Ctx->total[0] += (uint32_t)len; - md5Ctx->total[0] &= 0xFFFFFFFF; - - if (md5Ctx->total[0] < (uint32_t)len) { - md5Ctx->total[1]++; - } - - if (left && len >= fill) { - ARCH_MemCpy_Fast((void *)((uint8_t *)md5Ctx->md5Buf + left), input, fill); - - /* Set data source address */ - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_MSA, (uintptr_t)md5Ctx->md5Buf); - - /* Set data length */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MSG_LEN, 1); - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal); - - /* Trigger */ - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T); - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal); - - md5Ctx->md5Feed = 1; - input += fill; - len -= fill; - left = 0; - } - - fill = len / 64; - len = len % 64; - - if (fill > 0) { - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* SHA need set se_sha_sel to 1 to keep the last sha state */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_HASH_SEL, md5Ctx->md5Feed); - - /* Fill data */ - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_MSA, (uintptr_t)input); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MSG_LEN, fill); - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal); - - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T); - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal); - - input += (fill * 64); - md5Ctx->md5Feed = 1; - } - - if (len > 0) { - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* Copy left data into temp buffer */ - ARCH_MemCpy_Fast((void *)((uint8_t *)md5Ctx->md5Buf + left), input, len); - } - - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief SHA256 finish to get output function - * - * @param shaCtx: SHA256 context pointer - * @param shaNo: SHA ID type - * @param hash: SHA output data of SHA result - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_SHA256_Finish(SEC_Eng_SHA256_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint8_t *hash) -{ - uint32_t last, padn; - uint32_t high, low; - uint8_t shaMode; - uint8_t msgLen[8]; - uint8_t *p = (uint8_t *)hash; - uint32_t SHAx = SEC_ENG_BASE; - uint32_t tmpVal; - uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); - - /* Wait finished */ - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - high = (shaCtx->total[0] >> 29) | (shaCtx->total[1] << 3); - low = (shaCtx->total[0] << 3); - - PUT_UINT32_BE(high, msgLen, 0); - PUT_UINT32_BE(low, msgLen, 4); - - last = shaCtx->total[0] & 0x3F; - padn = (last < 56) ? (56 - last) : (120 - last); - - Sec_Eng_SHA256_Update(shaCtx, shaNo, (uint8_t *)shaCtx->shaPadding, padn); - - /* Wait for shaPadding idle */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - ARCH_MemCpy_Fast(shaCtx->shaPadding, msgLen, 8); - Sec_Eng_SHA256_Update(shaCtx, shaNo, (uint8_t *)shaCtx->shaPadding, 8); - - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - shaMode = (SEC_ENG_SHA_Type)BL_GET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MODE); - /* Copy SHA value */ - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_0); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_1); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_2); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_3); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_4); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - - if (shaMode == SEC_ENG_SHA224 || shaMode == SEC_ENG_SHA256) { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_5); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_6); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - - if (shaMode == SEC_ENG_SHA256) { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_7); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - } - } - - /* Disable SHA engine*/ - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_HASH_SEL); - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_EN); - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief SHA512 finish to get output function - * - * @param shaCtx: SHA512 context pointer - * @param shaNo: SHA ID type - * @param hash: SHA output data of SHA result - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_SHA512_Finish(SEC_Eng_SHA512_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint8_t *hash) -{ - uint64_t last, padn; - uint64_t high, low; - uint8_t shaMode; - uint8_t msgLen[16]; - uint8_t *p = (uint8_t *)hash; - uint32_t SHAx = SEC_ENG_BASE; - uint32_t tmpVal; - uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); - - /* Wait finished */ - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - high = (shaCtx->total[0] >> 61) | (shaCtx->total[1] << 3); - low = (shaCtx->total[0] << 3); - - PUT_UINT64_BE(high, msgLen, 0); - PUT_UINT64_BE(low, msgLen, 8); - - last = shaCtx->total[0] & 0x7F; - padn = (last < 112) ? (112 - last) : (240 - last); - - Sec_Eng_SHA512_Update(shaCtx, shaNo, (uint8_t *)shaCtx->shaPadding, padn); - - /* Wait for shaPadding idle */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - ARCH_MemCpy_Fast(shaCtx->shaPadding, msgLen, 16); - Sec_Eng_SHA512_Update(shaCtx, shaNo, (uint8_t *)shaCtx->shaPadding, 16); - - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - shaMode = (SEC_ENG_SHA_Type)BL_GET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MODE); - /* Copy SHA value */ - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_H_0); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_0); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_H_1); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_1); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_H_2); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_2); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_H_3); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - - if (shaMode == SEC_ENG_SHA512T256 || shaMode == SEC_ENG_SHA384 || shaMode == SEC_ENG_SHA512) { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_3); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - - if (shaMode == SEC_ENG_SHA384 || shaMode == SEC_ENG_SHA512) { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_H_4); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_4); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_H_5); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_5); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - - if (shaMode == SEC_ENG_SHA512) { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_H_6); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_6); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_H_7); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_7); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - } - } - } - - /* Disable SHA engine*/ - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_HASH_SEL); - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_EN); - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief MD5 finish to get output function - * - * @param md5Ctx: MD5 context pointer - * @param shaNo: SHA ID type - * @param hash: MD5 output data of SHA result - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_MD5_Finish(SEC_Eng_MD5_Ctx *md5Ctx, SEC_ENG_SHA_ID_Type shaNo, uint8_t *hash) -{ - uint32_t last, padn; - uint32_t high, low; - uint8_t msgLen[8]; - uint8_t *p = (uint8_t *)hash; - uint32_t SHAx = SEC_ENG_BASE; - uint32_t tmpVal; - uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); - - /* Wait finished */ - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - high = (md5Ctx->total[0] >> 29) | (md5Ctx->total[1] << 3); - low = (md5Ctx->total[0] << 3); - - PUT_UINT32(low, msgLen, 0); - PUT_UINT32(high, msgLen, 4); - - last = md5Ctx->total[0] & 0x3F; - padn = (last < 56) ? (56 - last) : (120 - last); - - Sec_Eng_MD5_Update(md5Ctx, shaNo, (uint8_t *)md5Ctx->md5Padding, padn); - - /* Wait for shaPadding idle */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - ARCH_MemCpy_Fast(md5Ctx->md5Padding, msgLen, 8); - Sec_Eng_MD5_Update(md5Ctx, shaNo, (uint8_t *)md5Ctx->md5Padding, 8); - - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - - /* Copy SHA value */ - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_0); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_1); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_2); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_3); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - - /* Disable SHA engine*/ - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_HASH_SEL); - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_EN); - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief SHA enable link mode and set link config address - * - * @param shaNo: SHA ID type - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_SHA_Enable_Link(SEC_ENG_SHA_ID_Type shaNo) -{ - uint32_t SHAx = SEC_ENG_BASE; - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); - - /* Enable sha and enable link mode */ - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_LINK_MODE); - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal); -} - -/****************************************************************************/ /** - * @brief SHA disable link mode - * - * @param shaNo: SHA ID type - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_SHA_Disable_Link(SEC_ENG_SHA_ID_Type shaNo) -{ - uint32_t SHAx = SEC_ENG_BASE; - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); - - /* Disable sha and disable link mode */ - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_LINK_MODE); - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_EN); - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal); -} - -/****************************************************************************/ /** - * @brief SHA256 link mode initialization function - * - * @param shaCtx: SHA256 link mode context pointer - * @param shaNo: SHA ID type - * @param linkAddr: SHA link configure address - * @param shaTmpBuf[16]: SHA temp buffer for store data that is less than 64 bytes - * @param padding[16]: SHA padding buffer for store padding data - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_SHA256_Link_Init(SEC_Eng_SHA256_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint32_t linkAddr, uint32_t shaTmpBuf[16], uint32_t padding[16]) -{ - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); - - /* Clear context */ - ARCH_MemSet(shaCtx, 0, sizeof(SEC_Eng_SHA256_Link_Ctx)); - - /* Init temp buffer,padding buffer and link address */ - shaCtx->shaBuf = shaTmpBuf; - shaCtx->shaPadding = padding; - ARCH_MemSet(shaCtx->shaPadding, 0, 64); - ARCH_MemSet(shaCtx->shaPadding, 0x80, 1); - shaCtx->linkAddr = linkAddr; - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(SEC_ENG_ID0_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_SHA_IRQHandler); - Interrupt_Handler_Register(SEC_ENG_ID1_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_SHA_IRQHandler); -#endif -} - -/****************************************************************************/ /** - * @brief SHA512 link mode initialization function - * - * @param shaCtx: SHA512 link mode context pointer - * @param shaNo: SHA ID type - * @param linkAddr: SHA link configure address - * @param shaTmpBuf[16]: SHA temp buffer for store data that is less than 128 bytes - * @param padding[16]: SHA padding buffer for store padding data - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_SHA512_Link_Init(SEC_Eng_SHA512_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint32_t linkAddr, uint64_t shaTmpBuf[16], uint64_t padding[16]) -{ - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); - - /* Clear context */ - ARCH_MemSet(shaCtx, 0, sizeof(SEC_Eng_SHA512_Link_Ctx)); - - /* Init temp buffer,padding buffer and link address */ - shaCtx->shaBuf = shaTmpBuf; - shaCtx->shaPadding = padding; - ARCH_MemSet(shaCtx->shaPadding, 0, 128); - ARCH_MemSet(shaCtx->shaPadding, 0x80, 1); - shaCtx->linkAddr = linkAddr; - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(SEC_ENG_ID0_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_SHA_IRQHandler); - Interrupt_Handler_Register(SEC_ENG_ID1_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_SHA_IRQHandler); -#endif -} - -/****************************************************************************/ /** - * @brief MD5 link mode initialization function - * - * @param shaCtx: SHA256 link mode context pointer - * @param shaNo: SHA ID type - * @param linkAddr: MD5 link configure address - * @param shaTmpBuf[16]: MD5 temp buffer for store data that is less than 64 bytes - * @param padding[16]: MD5 padding buffer for store padding data - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_MD5_Link_Init(SEC_Eng_MD5_Link_Ctx *md5Ctx, SEC_ENG_SHA_ID_Type shaNo, uint32_t linkAddr, uint32_t md5TmpBuf[16], uint32_t padding[16]) -{ - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); - - /* Clear context */ - ARCH_MemSet(md5Ctx, 0, sizeof(SEC_Eng_MD5_Link_Ctx)); - - /* Init temp buffer,padding buffer and link address */ - md5Ctx->md5Buf = md5TmpBuf; - md5Ctx->md5Padding = padding; - ARCH_MemSet(md5Ctx->md5Padding, 0, 64); - ARCH_MemSet(md5Ctx->md5Padding, 0x80, 1); - md5Ctx->linkAddr = linkAddr; - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(SEC_ENG_ID0_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_SHA_IRQHandler); - Interrupt_Handler_Register(SEC_ENG_ID1_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_SHA_IRQHandler); -#endif -} - -/****************************************************************************/ /** - * @brief SHA256 link mode update input data function - * - * @param shaCtx: SHA256 link mode context pointer - * @param shaNo: SHA ID type - * @param input: SHA input data pointer, and the address should be word align - * @param len: SHA input data length - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_SHA256_Link_Update(SEC_Eng_SHA256_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, const uint8_t *input, uint32_t len) -{ - uint32_t SHAx = SEC_ENG_BASE; - uint32_t tmpVal; - uint32_t fill; - uint32_t left; - uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - if (len == 0) { - return SUCCESS; - } - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* Set link address */ - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_LINK, shaCtx->linkAddr); - - left = shaCtx->total[0] & 0x3F; - fill = 64 - left; - - shaCtx->total[0] += (uint32_t)len; - shaCtx->total[0] &= 0xFFFFFFFF; - - if (shaCtx->total[0] < (uint32_t)len) { - shaCtx->total[1]++; - } - - if (left && len >= fill) { - ARCH_MemCpy_Fast((void *)((uint8_t *)shaCtx->shaBuf + left), input, fill); - /* Set data source address */ - *(uint32_t *)(uintptr_t)(shaCtx->linkAddr + 4) = (uint32_t)(uintptr_t)shaCtx->shaBuf; - - /* Set data length */ - *((uint16_t *)(uintptr_t)shaCtx->linkAddr + 1) = 1; - - /* Trigger */ - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T)); - - /* Choose accumulating last hash in the next time */ - *((uint32_t *)(uintptr_t)shaCtx->linkAddr) |= 0x40; - input += fill; - len -= fill; - left = 0; - } - - fill = len / 64; - len = len % 64; - - if (fill > 0) { - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* Fill data */ - *(uint32_t *)(uintptr_t)(shaCtx->linkAddr + 4) = (uint32_t)(uintptr_t)input; - *((uint16_t *)(uintptr_t)shaCtx->linkAddr + 1) = fill; - - /* Trigger */ - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T)); - - input += (fill * 64); - /* Choose accumulating last hash in the next time */ - *((uint32_t *)(uintptr_t)shaCtx->linkAddr) |= 0x40; - } - - if (len > 0) { - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* Copy left data into temp buffer */ - ARCH_MemCpy_Fast((void *)((uint8_t *)shaCtx->shaBuf + left), input, len); - } - - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief SHA512 link mode update input data function - * - * @param shaCtx: SHA512 link mode context pointer - * @param shaNo: SHA ID type - * @param input: SHA input data pointer, and the address should be word align - * @param len: SHA input data length - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_SHA512_Link_Update(SEC_Eng_SHA512_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, const uint8_t *input, uint64_t len) -{ - uint32_t SHAx = SEC_ENG_BASE; - uint32_t tmpVal; - uint32_t fill; - uint32_t left; - uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - if (len == 0) { - return SUCCESS; - } - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* Set link address */ - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_LINK, shaCtx->linkAddr); - - left = shaCtx->total[0] & 0x7F; - fill = 128 - left; - - shaCtx->total[0] += (uint64_t)len; - - if (shaCtx->total[0] < (uint64_t)len) { - shaCtx->total[1]++; - } - - if (left && len >= fill) { - ARCH_MemCpy_Fast((void *)((uint8_t *)shaCtx->shaBuf + left), input, fill); - /* Set data source address */ - *(uint32_t *)(uintptr_t)(shaCtx->linkAddr + 4) = (uint32_t)(uintptr_t)shaCtx->shaBuf; - - /* Set data length */ - *((uint16_t *)(uintptr_t)shaCtx->linkAddr + 1) = 1; - - /* Trigger */ - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T)); - - /* Choose accumulating last hash in the next time */ - *((uint32_t *)(uintptr_t)shaCtx->linkAddr) |= 0x40; - input += fill; - len -= fill; - left = 0; - } - - fill = len / 128; - len = len % 128; - - if (fill > 0) { - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* Fill data */ - *(uint32_t *)(uintptr_t)(shaCtx->linkAddr + 4) = (uint32_t)(uintptr_t)input; - *((uint16_t *)(uintptr_t)shaCtx->linkAddr + 1) = fill; - - /* Trigger */ - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T)); - - input += (fill * 128); - /* Choose accumulating last hash in the next time */ - *((uint32_t *)(uintptr_t)shaCtx->linkAddr) |= 0x40; - } - - if (len > 0) { - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* Copy left data into temp buffer */ - ARCH_MemCpy_Fast((void *)((uint8_t *)shaCtx->shaBuf + left), input, len); - } - - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief MD5 link mode update input data function - * - * @param md5Ctx: MD5 link mode context pointer - * @param shaNo: SHA ID type - * @param input: MD5 input data pointer, and the address should be word align - * @param len: MD5 input data length - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_MD5_Link_Update(SEC_Eng_MD5_Link_Ctx *md5Ctx, SEC_ENG_SHA_ID_Type shaNo, const uint8_t *input, uint32_t len) -{ - uint32_t SHAx = SEC_ENG_BASE; - uint32_t tmpVal; - uint32_t fill; - uint32_t left; - uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - if (len == 0) { - return SUCCESS; - } - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* Set link address */ - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_LINK, md5Ctx->linkAddr); - - left = md5Ctx->total[0] & 0x3F; - fill = 64 - left; - - md5Ctx->total[0] += (uint32_t)len; - md5Ctx->total[0] &= 0xFFFFFFFF; - - if (md5Ctx->total[0] < (uint32_t)len) { - md5Ctx->total[1]++; - } - - if (left && len >= fill) { - ARCH_MemCpy_Fast((void *)((uint8_t *)md5Ctx->md5Buf + left), input, fill); - - /* Set data source address */ - *(uint32_t *)(uintptr_t)(md5Ctx->linkAddr + 4) = (uint32_t)(uintptr_t)md5Ctx->md5Buf; - - /* Set data length */ - *((uint16_t *)(uintptr_t)md5Ctx->linkAddr + 1) = 1; - - /* Trigger */ - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T)); - - /* Choose accumulating last hash in the next time */ - *((uint32_t *)(uintptr_t)md5Ctx->linkAddr) |= 0x40; - input += fill; - len -= fill; - left = 0; - } - - fill = len / 64; - len = len % 64; - - if (fill > 0) { - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* Fill data */ - *(uint32_t *)(uintptr_t)(md5Ctx->linkAddr + 4) = (uint32_t)(uintptr_t)input; - *((uint16_t *)(uintptr_t)md5Ctx->linkAddr + 1) = fill; - - /* Trigger */ - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T)); - - input += (fill * 64); - /* Choose accumulating last hash in the next time */ - *((uint32_t *)(uintptr_t)md5Ctx->linkAddr) |= 0x40; - } - - if (len > 0) { - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* Copy left data into temp buffer */ - ARCH_MemCpy_Fast((void *)((uint8_t *)md5Ctx->md5Buf + left), input, len); - } - - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief CRC16 link mode work input data function - * - * @param shaNo: SHA ID type - * @param linkAddr: CRC16 link mode address - * @param input: CRC16 input data pointer, and the address should be word align - * @param len: CRC16 input data length - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_CRC16_Link_Work(SEC_ENG_SHA_ID_Type shaNo, uint32_t linkAddr, const uint8_t *in, uint32_t len, uint8_t *out) -{ - uint32_t SHAx = SEC_ENG_BASE; - uint32_t tmpVal; - uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(shaNo)); - - /* Link address should word align */ - if ((linkAddr & 0x03) != 0) { - return ERROR; - } - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* Set link address */ - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_LINK, linkAddr); - - /* Change source buffer address and destination buffer address */ - *(uint32_t *)(uintptr_t)(linkAddr + 4) = (uint32_t)(uintptr_t)in; - - /* Set data length, 16 bits per block */ - *((uint16_t *)(uintptr_t)linkAddr + 1) = len * 8 / 16; - - /* Trigger */ - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T)); - - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* CRC16 code len is 16 bits */ - ARCH_MemCpy_Fast(out, (uint8_t *)(uintptr_t)(linkAddr + 0x10), 2); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief CRC32 link mode work input data function - * - * @param shaNo: SHA ID type - * @param linkAddr: CRC32 link mode address - * @param input: CRC32 input data pointer, and the address should be word align - * @param len: CRC32 input data length - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_CRC32_Link_Work(SEC_ENG_SHA_ID_Type shaNo, uint32_t linkAddr, const uint8_t *in, uint32_t len, uint8_t *out) -{ - uint32_t SHAx = SEC_ENG_BASE; - uint32_t tmpVal; - uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(shaNo)); - - /* Link address should word align */ - if ((linkAddr & 0x03) != 0) { - return ERROR; - } - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* Set link address */ - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_LINK, linkAddr); - - /* Change source buffer address and destination buffer address */ - *(uint32_t *)(uintptr_t)(linkAddr + 4) = (uint32_t)(uintptr_t)in; - - /* Set data length , 32 bits per block*/ - *((uint16_t *)(uintptr_t)linkAddr + 1) = len * 8 / 32; - - /* Trigger */ - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T)); - - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* CRC32 code len is 32 bits */ - ARCH_MemCpy_Fast(out, (uint8_t *)(uintptr_t)(linkAddr + 0x10), 4); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief SHA256 link mode finish to get output function - * - * @param shaCtx: SHA256 link mode context pointer - * @param shaNo: SHA ID type - * @param hash: SHA output data of SHA result - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_SHA256_Link_Finish(SEC_Eng_SHA256_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint8_t *hash) -{ - uint32_t last, padn; - uint32_t high, low; - uint8_t msgLen[8]; - uint32_t SHAx = SEC_ENG_BASE; - uint32_t tmpVal; - uint32_t shaMode = (*(uint32_t *)(uintptr_t)shaCtx->linkAddr) >> 2 & 0x7; - uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); - - /* Wait finished */ - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* Set link address */ - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_LINK, shaCtx->linkAddr); - - high = (shaCtx->total[0] >> 29) | (shaCtx->total[1] << 3); - low = (shaCtx->total[0] << 3); - - PUT_UINT32_BE(high, msgLen, 0); - PUT_UINT32_BE(low, msgLen, 4); - - last = shaCtx->total[0] & 0x3F; - padn = (last < 56) ? (56 - last) : (120 - last); - - Sec_Eng_SHA256_Link_Update(shaCtx, shaNo, (uint8_t *)shaCtx->shaPadding, padn); - - /* Wait for shaPadding idle */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - Sec_Eng_SHA256_Link_Update(shaCtx, shaNo, msgLen, 8); - - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* Get result according to SHA mode,result is placed in (link address + offset:8) */ - switch (shaMode) { - case 0: - ARCH_MemCpy_Fast(hash, (uint8_t *)(uintptr_t)(shaCtx->linkAddr + 8), 32); - break; - - case 1: - ARCH_MemCpy_Fast(hash, (uint8_t *)(uintptr_t)(shaCtx->linkAddr + 8), 28); - break; - - case 2: - ARCH_MemCpy_Fast(hash, (uint8_t *)(uintptr_t)(shaCtx->linkAddr + 8), 20); - break; - - case 3: - ARCH_MemCpy_Fast(hash, (uint8_t *)(uintptr_t)(shaCtx->linkAddr + 8), 20); - break; - - default: - break; - } - - /* Choose new hash in the next time */ - *((uint32_t *)(uintptr_t)shaCtx->linkAddr) &= ~0x40; - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief SHA512 link mode finish to get output function - * - * @param shaCtx: SHA512 link mode context pointer - * @param shaNo: SHA ID type - * @param hash: SHA output data of SHA result - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_SHA512_Link_Finish(SEC_Eng_SHA512_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint8_t *hash) -{ - uint64_t last, padn; - uint64_t high, low; - uint8_t msgLen[16]; - uint32_t SHAx = SEC_ENG_BASE; - uint32_t tmpVal; - uint32_t shaMode = (*(uint32_t *)(uintptr_t)shaCtx->linkAddr) >> 2 & 0x7; - uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); - - /* Wait finished */ - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* Set link address */ - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_LINK, shaCtx->linkAddr); - - high = (shaCtx->total[0] >> 61) | (shaCtx->total[1] << 3); - low = (shaCtx->total[0] << 3); - - PUT_UINT64_BE(high, msgLen, 0); - PUT_UINT64_BE(low, msgLen, 8); - - last = shaCtx->total[0] & 0x7F; - padn = (last < 112) ? (112 - last) : (240 - last); - - Sec_Eng_SHA512_Link_Update(shaCtx, shaNo, (uint8_t *)shaCtx->shaPadding, padn); - - /* Wait for shaPadding idle */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - Sec_Eng_SHA512_Link_Update(shaCtx, shaNo, msgLen, 16); - - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* Get result according to SHA mode,result is placed in (link address + offset:8) */ - switch (shaMode) { - case 4: - ARCH_MemCpy_Fast(hash, (uint8_t *)(uintptr_t)(shaCtx->linkAddr + 8), 64); - break; - - case 5: - ARCH_MemCpy_Fast(hash, (uint8_t *)(uintptr_t)(shaCtx->linkAddr + 8), 48); - break; - - case 6: - ARCH_MemCpy_Fast(hash, (uint8_t *)(uintptr_t)(shaCtx->linkAddr + 8), 28); - break; - - case 7: - ARCH_MemCpy_Fast(hash, (uint8_t *)(uintptr_t)(shaCtx->linkAddr + 8), 32); - break; - - default: - break; - } - - /* Choose new hash in the next time */ - *((uint32_t *)(uintptr_t)shaCtx->linkAddr) &= ~0x40; - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief MD5 link mode finish to get output function - * - * @param md5Ctx: MD5 link mode context pointer - * @param shaNo: SHA ID type - * @param hash: MD5 output data of SHA result - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_MD5_Link_Finish(SEC_Eng_MD5_Link_Ctx *md5Ctx, SEC_ENG_SHA_ID_Type shaNo, uint8_t *hash) -{ - uint32_t last, padn; - uint32_t high, low; - uint8_t msgLen[8]; - uint32_t SHAx = SEC_ENG_BASE; - uint32_t tmpVal; - uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); - - /* Wait finished */ - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* Set link address */ - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_LINK, md5Ctx->linkAddr); - - high = (md5Ctx->total[0] >> 29) | (md5Ctx->total[1] << 3); - low = (md5Ctx->total[0] << 3); - - PUT_UINT32(low, msgLen, 0); - PUT_UINT32(high, msgLen, 4); - - last = md5Ctx->total[0] & 0x3F; - padn = (last < 56) ? (56 - last) : (120 - last); - - Sec_Eng_MD5_Link_Update(md5Ctx, shaNo, (uint8_t *)md5Ctx->md5Padding, padn); - - /* Wait for shaPadding idle */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - Sec_Eng_MD5_Link_Update(md5Ctx, shaNo, msgLen, 8); - - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - ARCH_MemCpy_Fast(hash, (uint8_t *)(uintptr_t)(md5Ctx->linkAddr + 8), 16); - - /* Choose new hash in the next time */ - *((uint32_t *)(uintptr_t)md5Ctx->linkAddr) &= ~0x40; - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Group0 request SHA Access - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_Group0_Request_SHA_Access(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD); - - if ((tmpVal & 0x03) == 0x03) { - /* SHA control idle, write to request*/ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_SHA_0_CTRL_PROT, 0x02); - - /* Check request result */ - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD); - - if ((tmpVal & 0x03) == 0x01) { - return SUCCESS; - } - } - - return ERROR; -} - -/****************************************************************************/ /** - * @brief Group0 release SHA Access - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_Group0_Release_SHA_Access(void) -{ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_SHA_0_CTRL_PROT, 0x06); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Group1 request SHA Access - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_Group1_Request_SHA_Access(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD); - - if ((tmpVal & 0x03) == 0x03) { - /* SHA control idle, write to request*/ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_SHA_0_CTRL_PROT, 0x04); - - /* Check request result */ - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD); - - if ((tmpVal & 0x03) == 0x02) { - return SUCCESS; - } - } - - return ERROR; -} - -/****************************************************************************/ /** - * @brief Group1 release SHA Access - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_Group1_Release_SHA_Access(void) -{ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_SHA_0_CTRL_PROT, 0x06); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief AES initialization function - * - * @param aesCtx: AES context pointer - * @param aesNo: AES ID type - * @param aesType: AES type:ECB,CTR,CBC - * @param keyType: AES key type:128,256,192 - * @param enDecType: AES encryption or decryption - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_AES_Init(SEC_Eng_AES_Ctx *aesCtx, SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Type aesType, SEC_ENG_AES_Key_Type keyType, SEC_ENG_AES_EnDec_Type enDecType) -{ - uint32_t AESx = SEC_ENG_BASE; - uint32_t tmpVal; - uint32_t timeoutCnt = SEC_ENG_AES_BUSY_TIMEOUT_COUNT; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); - CHECK_PARAM(IS_SEC_ENG_AES_TYPE(aesType)); - CHECK_PARAM(IS_SEC_ENG_AES_KEY_TYPE(keyType)); - CHECK_PARAM(IS_SEC_ENG_AES_ENDEC_TYPE(enDecType)); - - /* Wait finished */ - do { - tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_AES_0_BUSY)); - - /* Set AES mode type*/ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_BLOCK_MODE, aesType); - - /* Set AES key type */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_MODE, keyType); - - /* Set AES encryption or decryption */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_DEC_EN, enDecType); - - /* Clear dec_key_sel to select new key */ - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_DEC_KEY_SEL); - - /* Clear aes iv sel to select new iv */ - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_IV_SEL); - - /* Clear AES interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_INT_CLR_1T); - - /* Enable AES */ - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_EN); - - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, tmpVal); - - /* Clear AES context */ - memset(aesCtx, 0, sizeof(SEC_Eng_AES_Ctx)); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(SEC_ENG_ID0_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_AES_IRQHandler); - Interrupt_Handler_Register(SEC_ENG_ID1_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_AES_IRQHandler); -#endif - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief AES enable function,set AES bigendian - * - * @param aesNo: AES ID type - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_AES_Enable_BE(SEC_ENG_AES_ID_Type aesNo) -{ - uint32_t AESx = SEC_ENG_BASE; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); - - /* set 0x0f to 0x1f for xts mode */ - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_ENDIAN, 0x1f); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(SEC_ENG_ID0_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_AES_IRQHandler); - Interrupt_Handler_Register(SEC_ENG_ID1_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_AES_IRQHandler); -#endif -} - -/****************************************************************************/ /** - * @brief AES enable function,set AES littleendian - * - * @param aesNo: AES ID type - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_AES_Enable_LE(SEC_ENG_AES_ID_Type aesNo) -{ - uint32_t AESx = SEC_ENG_BASE; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); - - /* set 0x00 to 0x0f for xts mode */ - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_ENDIAN, 0x10); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(SEC_ENG_ID0_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_AES_IRQHandler); - Interrupt_Handler_Register(SEC_ENG_ID1_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_AES_IRQHandler); -#endif -} - -/****************************************************************************/ /** - * @brief AES enable link mode - * - * @param aesNo: AES ID type - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_AES_Enable_Link(SEC_ENG_AES_ID_Type aesNo) -{ - uint32_t AESx = SEC_ENG_BASE; - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); - - /* Enable aes link mode */ - tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL); - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_LINK_MODE)); -} - -/****************************************************************************/ /** - * @brief AES disable link mode - * - * @param aesNo: AES ID type - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_AES_Disable_Link(SEC_ENG_AES_ID_Type aesNo) -{ - uint32_t AESx = SEC_ENG_BASE; - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); - - /* Disable aes link mode */ - tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL); - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_LINK_MODE)); -} - -/****************************************************************************/ /** - * @brief AES work in link mode - * - * @param aesNo: AES ID type - * @param linkAddr: Address of config structure in link mode - * @param in: AES input data buffer to deal with - * @param len: AES input data length - * @param out: AES output data buffer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_AES_Link_Work(SEC_ENG_AES_ID_Type aesNo, uint32_t linkAddr, const uint8_t *in, uint32_t len, uint8_t *out) -{ - uint32_t AESx = SEC_ENG_BASE; - uint32_t tmpVal; - uint32_t timeoutCnt = SEC_ENG_AES_BUSY_TIMEOUT_COUNT; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); - - /* Link address should word align */ - if ((linkAddr & 0x03) != 0 || len % 16 != 0) { - return ERROR; - } - - /* Wait finished */ - do { - tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_AES_0_BUSY)); - - /* Set link address */ - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_LINK, linkAddr); - - /* Change source buffer address and destination buffer address */ - *(uint32_t *)(uintptr_t)(linkAddr + 4) = (uint32_t)(uintptr_t)in; - *(uint32_t *)(uintptr_t)(linkAddr + 8) = (uint32_t)(uintptr_t)out; - - /* Set data length */ - *((uint16_t *)(uintptr_t)linkAddr + 1) = len / 16; - - /* Enable aes */ - tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL); - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_EN)); - - /* Start aes engine and wait finishing */ - tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL); - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_TRIG_1T)); - - __NOP(); - __NOP(); - timeoutCnt = SEC_ENG_AES_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_AES_0_BUSY)); - - /* Disable aes */ - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_EN)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief AES set hardware key source:efuse region for CPU0 or region efuse for CPU1 - * - * @param aesNo: AES ID type - * @param src: AES key source type - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_AES_Set_Hw_Key_Src(SEC_ENG_AES_ID_Type aesNo, uint8_t src) -{ - uint32_t AESx = SEC_ENG_BASE; - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); - - tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_SBOOT); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_SBOOT_KEY_SEL, src); - - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_SBOOT, tmpVal); -} - -/****************************************************************************/ /** - * @brief AES set KEY and IV - * - * @param aesNo: AES ID type - * @param keySrc: AES KEY type:SEC_ENG_AES_KEY_HW or SEC_ENG_AES_KEY_SW - * @param key: AES KEY pointer - * @param iv: AES IV pointer - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_AES_Set_Key_IV(SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Key_Src_Type keySrc, const uint8_t *key, const uint8_t *iv) -{ - uint32_t AESx = SEC_ENG_BASE; - uint32_t tmpVal; - uint32_t keyType; - uint32_t aesType; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); - CHECK_PARAM(IS_SEC_ENG_AES_KEY_SRC_TYPE(keySrc)); - - tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL); - aesType = BL_GET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_BLOCK_MODE); - - /* Set IV, XTS mode and other mode are different */ - if (aesType == (uint32_t)SEC_ENG_AES_XTS) { - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_IV_0, BL_RDWD_FRM_BYTEP(iv)); - iv += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_IV_1, BL_RDWD_FRM_BYTEP(iv)); - iv += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_IV_2, BL_RDWD_FRM_BYTEP(iv)); - iv += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_IV_3, BL_RDWD_FRM_BYTEP(iv)); - iv += 4; - } else { - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_IV_3, __REV(BL_RDWD_FRM_BYTEP(iv))); - iv += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_IV_2, __REV(BL_RDWD_FRM_BYTEP(iv))); - iv += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_IV_1, __REV(BL_RDWD_FRM_BYTEP(iv))); - iv += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_IV_0, __REV(BL_RDWD_FRM_BYTEP(iv))); - iv += 4; - } - - /* Select hardware key */ - if (keySrc == SEC_ENG_AES_KEY_HW) { - tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_HW_KEY_EN, SEC_ENG_AES_KEY_HW); - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, tmpVal); - - tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_KEY_SEL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_KEY_SEL, *key); - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_SEL, tmpVal); - - tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_1_KEY_SEL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_1_KEY_SEL, *key); - BL_WR_REG(AESx, SEC_ENG_SE_AES_1_KEY_SEL, tmpVal); - - return; - } - - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_7, __REV(BL_RDWD_FRM_BYTEP(key))); - key += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_6, __REV(BL_RDWD_FRM_BYTEP(key))); - key += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_5, __REV(BL_RDWD_FRM_BYTEP(key))); - key += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_4, __REV(BL_RDWD_FRM_BYTEP(key))); - key += 4; - - tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL); - keyType = BL_GET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_MODE); - - if (keyType == (uint32_t)SEC_ENG_AES_KEY_192BITS) { - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_3, __REV(BL_RDWD_FRM_BYTEP(key))); - key += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_2, __REV(BL_RDWD_FRM_BYTEP(key))); - key += 4; - } else if (keyType == (uint32_t)SEC_ENG_AES_KEY_256BITS || keyType == (uint32_t)SEC_ENG_AES_DOUBLE_KEY_128BITS || aesType == (uint32_t)SEC_ENG_AES_XTS) { - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_3, __REV(BL_RDWD_FRM_BYTEP(key))); - key += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_2, __REV(BL_RDWD_FRM_BYTEP(key))); - key += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_1, __REV(BL_RDWD_FRM_BYTEP(key))); - key += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_0, __REV(BL_RDWD_FRM_BYTEP(key))); - key += 4; - } - - /* Select software key */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_HW_KEY_EN, SEC_ENG_AES_KEY_SW); - - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, tmpVal); -} - -/****************************************************************************/ /** - * @brief AES set KEY and IV with bigendian - * - * @param aesNo: AES ID type - * @param keySrc: AES KEY type:SEC_ENG_AES_KEY_HW or SEC_ENG_AES_KEY_SW - * @param key: AES KEY pointer - * @param iv: AES IV pointer - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_AES_Set_Key_IV_BE(SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Key_Src_Type keySrc, const uint8_t *key, const uint8_t *iv) -{ - uint32_t AESx = SEC_ENG_BASE; - uint32_t tmpVal; - uint32_t keyType; - uint32_t aesType; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); - CHECK_PARAM(IS_SEC_ENG_AES_KEY_SRC_TYPE(keySrc)); - - tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL); - aesType = BL_GET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_BLOCK_MODE); - - /* Set IV, XTS mode and other mode are different */ - if (aesType == (uint32_t)SEC_ENG_AES_XTS) { - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_IV_3, __REV(BL_RDWD_FRM_BYTEP(iv))); - iv += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_IV_2, __REV(BL_RDWD_FRM_BYTEP(iv))); - iv += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_IV_1, __REV(BL_RDWD_FRM_BYTEP(iv))); - iv += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_IV_0, __REV(BL_RDWD_FRM_BYTEP(iv))); - iv += 4; - } else { - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_IV_0, BL_RDWD_FRM_BYTEP(iv)); - iv += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_IV_1, BL_RDWD_FRM_BYTEP(iv)); - iv += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_IV_2, BL_RDWD_FRM_BYTEP(iv)); - iv += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_IV_3, BL_RDWD_FRM_BYTEP(iv)); - iv += 4; - } - - /* Select hardware key */ - if (keySrc == SEC_ENG_AES_KEY_HW) { - tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_HW_KEY_EN, SEC_ENG_AES_KEY_HW); - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, tmpVal); - - tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_KEY_SEL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_KEY_SEL, *key); - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_SEL, tmpVal); - - tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_1_KEY_SEL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_1_KEY_SEL, *key); - BL_WR_REG(AESx, SEC_ENG_SE_AES_1_KEY_SEL, tmpVal); - - return; - } - - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_0, BL_RDWD_FRM_BYTEP(key)); - key += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_1, BL_RDWD_FRM_BYTEP(key)); - key += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_2, BL_RDWD_FRM_BYTEP(key)); - key += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_3, BL_RDWD_FRM_BYTEP(key)); - key += 4; - - tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL); - keyType = BL_GET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_MODE); - - if (keyType == (uint32_t)SEC_ENG_AES_KEY_192BITS) { - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_4, BL_RDWD_FRM_BYTEP(key)); - key += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_5, BL_RDWD_FRM_BYTEP(key)); - key += 4; - } else if (keyType == (uint32_t)SEC_ENG_AES_KEY_256BITS || keyType == (uint32_t)SEC_ENG_AES_DOUBLE_KEY_128BITS || aesType == (uint32_t)SEC_ENG_AES_XTS) { - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_4, BL_RDWD_FRM_BYTEP(key)); - key += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_5, BL_RDWD_FRM_BYTEP(key)); - key += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_6, BL_RDWD_FRM_BYTEP(key)); - key += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_7, BL_RDWD_FRM_BYTEP(key)); - key += 4; - } - - /* Select software key */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_HW_KEY_EN, SEC_ENG_AES_KEY_SW); - - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, tmpVal); -} - -/****************************************************************************/ /** - * @brief AES set counter byte type in CTR mode - * - * @param aesNo: AES ID type - * @param counterType: AES counter type - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_AES_Set_Counter_Byte(SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Counter_Type counterType) -{ - uint32_t AESx = SEC_ENG_BASE; - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); - CHECK_PARAM(IS_SEC_ENG_AES_COUNTER_TYPE(counterType)); - - /* Set counter type */ - tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_ENDIAN); - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_ENDIAN, BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_CTR_LEN, counterType)); -} - -/****************************************************************************/ /** - * @brief AES encrypt or decrypt input data - * - * @param aesCtx: AES context pointer - * @param aesNo: AES ID type - * @param in: AES input data buffer to deal with - * @param len: AES input data length - * @param out: AES output data buffer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_AES_Crypt(SEC_Eng_AES_Ctx *aesCtx, SEC_ENG_AES_ID_Type aesNo, const uint8_t *in, uint32_t len, uint8_t *out) -{ - uint32_t AESx = SEC_ENG_BASE; - uint32_t tmpVal; - uint32_t timeoutCnt = SEC_ENG_AES_BUSY_TIMEOUT_COUNT; - - if (len % 16 != 0) { - return ERROR; - } - - /* Wait finished */ - do { - tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_AES_0_BUSY)); - - /* Clear trigger */ - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_TRIG_1T); - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, tmpVal); - - /* Set input and output address */ - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_MSA, (uintptr_t)in); - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_MDA, (uintptr_t)out); - - /* Set message length */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_MSG_LEN, len / 16); - - if (aesCtx->mode == SEC_ENG_AES_CTR) { - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_DEC_KEY_SEL); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_DEC_KEY_SEL); - } - - /* Set IV sel:0 for new, 1 for last */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_IV_SEL, aesCtx->aesFeed); - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, tmpVal); - - /* Trigger AES Engine */ - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_TRIG_1T); - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, tmpVal); - - /* Wait finished */ - timeoutCnt = SEC_ENG_AES_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_AES_0_BUSY)); - - aesCtx->aesFeed = 1; - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief AES finish function, clean register - * - * @param aesNo: AES ID type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_AES_Finish(SEC_ENG_AES_ID_Type aesNo) -{ - uint32_t AESx = SEC_ENG_BASE; - uint32_t tmpVal; - uint32_t timeoutCnt = SEC_ENG_AES_BUSY_TIMEOUT_COUNT; - - /* Wait finished */ - do { - tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_AES_0_BUSY)); - - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_EN); - - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_DEC_KEY_SEL); - - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_IV_SEL); - - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Group0 request access for AES - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_Group0_Request_AES_Access(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD); - - if (((tmpVal >> 2) & 0x03) == 0x03) { - /* SHA control idle, write to request*/ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL_PROT, 0x02); - - /* Check request result */ - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD); - - if (((tmpVal >> 2) & 0x03) == 0x01) { - return SUCCESS; - } - } - - return ERROR; -} - -/****************************************************************************/ /** - * @brief Group0 release AES Access - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_Group0_Release_AES_Access(void) -{ - /* SHA control idle, write to request*/ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL_PROT, 0x06); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Group1 request AES Access - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_Group1_Request_AES_Access(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD); - - if (((tmpVal >> 2) & 0x03) == 0x03) { - /* SHA control idle, write to request*/ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL_PROT, 0x04); - - /* Check request result */ - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD); - - if (((tmpVal >> 2) & 0x03) == 0x02) { - return SUCCESS; - } - } - - return ERROR; -} - -/****************************************************************************/ /** - * @brief Group1 release AES Access - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_Group1_Release_AES_Access(void) -{ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL_PROT, 0x06); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief TRNG enable TRNG interrupt - * - * @param None - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_Trng_Enable(void) -{ - uint32_t TRNGx = SEC_ENG_BASE; - uint32_t tmpVal; - uint32_t timeoutCnt = SEC_ENG_TRNG_BUSY_TIMEOUT_COUNT; - - tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0); - - /* FIXME:default reseed number is 0x1ff, to verify, use 0xa to speed up */ - //tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SEC_ENG_SE_TRNG_0_RESEED_N,0x1ff); - - /* No interrupt as default */ - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_EN); - BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0, tmpVal); - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_INT_CLR_1T); - BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0, tmpVal); - - /* busy will be set to 1 after trigger, the gap is 1T */ - __NOP(); - __NOP(); - __NOP(); - __NOP(); - - do { - tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_TRNG_0_BUSY)); - - /* Clear trng interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_INT_CLR_1T); - BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0, tmpVal); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(SEC_ENG_ID0_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_TRNG_IRQHandler); - Interrupt_Handler_Register(SEC_ENG_ID1_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_TRNG_IRQHandler); -#endif - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief TRNG enable TRNG interrupt - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_Trng_Int_Enable(void) -{ - uint32_t TRNGx = SEC_ENG_BASE; - uint32_t tmpVal; - - tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0); - - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_INT_MASK); - - BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief TRNG disable TRNG interrupt - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_Trng_Int_Disable(void) -{ - uint32_t TRNGx = SEC_ENG_BASE; - uint32_t tmpVal; - - tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0); - - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_INT_MASK); - - BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief TRNG get random data out - * - * @param data[32]: TRNG output data - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_Trng_Read(uint8_t data[32]) -{ - uint8_t *p = (uint8_t *)data; - uint32_t TRNGx = SEC_ENG_BASE; - uint32_t tmpVal; - uint32_t timeoutCnt = SEC_ENG_TRNG_BUSY_TIMEOUT_COUNT; - - tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0); - - /* Trigger */ - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_TRIG_1T); - BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0, tmpVal); - - /* busy will be set to 1 after trigger, the gap is 1T */ - __NOP(); - __NOP(); - __NOP(); - __NOP(); - - do { - tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_TRNG_0_BUSY)); - - /* copy trng value */ - BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_0)); - p += 4; - BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_1)); - p += 4; - BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_2)); - p += 4; - BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_3)); - p += 4; - BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_4)); - p += 4; - BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_5)); - p += 4; - BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_6)); - p += 4; - BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_7)); - p += 4; - - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_TRIG_1T); - BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0, tmpVal); - - /* Clear data */ - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_DOUT_CLR_1T); - BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0, tmpVal); - - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_DOUT_CLR_1T); - BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief TRNG get random data out - * - * @param data: TRNG output data buffer - * - * @param len: total length to get in bytes - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_Trng_Get_Random(uint8_t *data, uint32_t len) -{ - uint8_t tmpBuf[32]; - uint32_t readLen = 0; - uint32_t i = 0, cnt = 0; - - while (readLen < len) { - if (Sec_Eng_Trng_Read(tmpBuf) != SUCCESS) { - return -1; - } - - cnt = len - readLen; - - if (cnt > sizeof(tmpBuf)) { - cnt = sizeof(tmpBuf); - } - - for (i = 0; i < cnt; i++) { - data[readLen + i] = tmpBuf[i]; - } - - readLen += cnt; - } - - return 0; -} - -/****************************************************************************/ /** - * @brief TRNG Interrupt Read Trigger - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_Trng_Int_Read_Trigger(void) -{ - uint32_t TRNGx = SEC_ENG_BASE; - uint32_t tmpVal; - - Sec_Eng_Trng_Int_Enable(); - - tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0); - /* Trigger */ - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_TRIG_1T); - BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief TRNG get random data out with Interrupt - * - * @param data[32]: TRNG output data - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_Trng_Int_Read(uint8_t data[32]) -{ - uint8_t *p = (uint8_t *)data; - uint32_t TRNGx = SEC_ENG_BASE; - uint32_t tmpVal; - - tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0); - - /* copy trng value */ - BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_0)); - p += 4; - BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_1)); - p += 4; - BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_2)); - p += 4; - BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_3)); - p += 4; - BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_4)); - p += 4; - BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_5)); - p += 4; - BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_6)); - p += 4; - BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_7)); - p += 4; - - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_TRIG_1T); - BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0, tmpVal); - - /* Clear data */ - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_DOUT_CLR_1T); - BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0, tmpVal); - - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_DOUT_CLR_1T); - BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief Disable TRNG - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_Trng_Disable(void) -{ - uint32_t TRNGx = SEC_ENG_BASE; - uint32_t tmpVal; - - tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0); - - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_EN); - //tmpVal=BL_CLR_REG_BIT(tmpVal,SEC_ENG_SE_TRNG_0_RESEED_N); - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_INT_CLR_1T); - - BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief Group0 request TRNG Access - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_Group0_Request_Trng_Access(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD); - - if (((tmpVal >> 4) & 0x03) == 0x03) { - /* SHA control idle, write to request*/ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_PROT, 0x02); - - /* Check request result */ - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD); - - if (((tmpVal >> 4) & 0x03) == 0x01) { - return SUCCESS; - } - } - - return ERROR; -} - -/****************************************************************************/ /** - * @brief Group0 release TRNG Access - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_Group0_Release_Trng_Access(void) -{ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_PROT, 0x06); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Group1 request TRNG Access - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_Group1_Request_Trng_Access(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD); - - if (((tmpVal >> 4) & 0x03) == 0x03) { - /* SHA control idle, write to request*/ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_PROT, 0x04); - - /* Check request result */ - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD); - - if (((tmpVal >> 4) & 0x03) == 0x02) { - return SUCCESS; - } - } - - return ERROR; -} - -/****************************************************************************/ /** - * @brief Group1 release TRNG Access - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_Group1_Release_Trng_Access(void) -{ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_PROT, 0x06); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief PKA Reset - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_Reset(void) -{ - uint8_t val; - - //Disable sec engine - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, 0); - - //Enable sec engine - val = 1 << 3; - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, val); -} - -/****************************************************************************/ /** - * @brief PKA Enable big endian - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_BigEndian_Enable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0); - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_PKA_0_ENDIAN); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, tmpVal); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(SEC_ENG_ID0_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_PKA_IRQHandler); - Interrupt_Handler_Register(SEC_ENG_ID1_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_PKA_IRQHandler); -#endif -} - -/****************************************************************************/ /** - * @brief PKA Enable little endian - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_LittleEndian_Enable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0); - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_PKA_0_ENDIAN); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, tmpVal); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(SEC_ENG_ID0_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_PKA_IRQHandler); - Interrupt_Handler_Register(SEC_ENG_ID1_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_PKA_IRQHandler); -#endif -} - -/****************************************************************************/ /** - * @brief PKA get status function - * - * @param status: Structure pointer of PKA status type - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_GetStatus(SEC_Eng_PKA_Status_Type *status) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0); - *(uint16_t *)status = (uint16_t)BL_GET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_PKA_0_STATUS); -} - -/****************************************************************************/ /** - * @brief PKA clear interrupt - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_Clear_Int(void) -{ - uint32_t ctrl; - - ctrl = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0); - ctrl = BL_SET_REG_BIT(ctrl, SEC_ENG_SE_PKA_0_INT_CLR_1T); - - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, ctrl); - - ctrl = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0); - ctrl = BL_CLR_REG_BIT(ctrl, SEC_ENG_SE_PKA_0_INT_CLR_1T); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, ctrl); -} - -/****************************************************************************/ /** - * @brief PKA get Register size according to Register type - * - * @param reg_type: PKA Register type - * - * @return Register size - * -*******************************************************************************/ -static uint16_t Sec_Eng_PKA_Get_Reg_Size(SEC_ENG_PKA_REG_SIZE_Type reg_type) -{ - switch (reg_type) { - case SEC_ENG_PKA_REG_SIZE_8: - return 8; - - case SEC_ENG_PKA_REG_SIZE_16: - return 16; - - case SEC_ENG_PKA_REG_SIZE_32: - return 32; - - case SEC_ENG_PKA_REG_SIZE_64: - return 64; - - case SEC_ENG_PKA_REG_SIZE_96: - return 96; - - case SEC_ENG_PKA_REG_SIZE_128: - return 128; - - case SEC_ENG_PKA_REG_SIZE_192: - return 192; - - case SEC_ENG_PKA_REG_SIZE_256: - return 256; - - case SEC_ENG_PKA_REG_SIZE_384: - return 384; - - case SEC_ENG_PKA_REG_SIZE_512: - return 512; - - default: - return 0; - } -} - -/****************************************************************************/ /** - * @brief PKA set pre-load register configuration - * - * @param size: Data size in word to write - * @param regIndex: Register index - * @param regType: Register type - * @param op: PKA operation - * @param lastOp: Last operation - * - * @return None - * -*******************************************************************************/ -static void Sec_Eng_PKA_Write_Pld_Cfg(uint16_t size, uint8_t regIndex, SEC_ENG_PKA_REG_SIZE_Type regType, SEC_ENG_PKA_OP_Type op, uint8_t lastOp) -{ - struct pka0_pld_cfg cfg; - - cfg.value.BF.size = size; - cfg.value.BF.d_reg_index = regIndex; - cfg.value.BF.d_reg_type = regType; - cfg.value.BF.op = op; - cfg.value.BF.last_op = lastOp; - - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD); -} - -/****************************************************************************/ /** - * @brief PKA write common operation first configuration - * - * @param s0RegIndex: Register index - * @param s0RegType: Register type - * @param dRegIndex: Result Register index - * @param dRegType: Result Register type - * @param op: PKA operation - * @param lastOp: Last operation - * - * @return None - * -*******************************************************************************/ -static void Sec_Eng_PKA_Write_Common_OP_First_Cfg(uint8_t s0RegIndex, uint8_t s0RegType, uint8_t dRegIndex, uint8_t dRegType, - uint8_t op, uint8_t lastOp) -{ - struct pka0_common_op_first_cfg cfg; - - cfg.value.BF.s0_reg_idx = s0RegIndex; - cfg.value.BF.s0_reg_type = s0RegType; - - if (op != SEC_ENG_PKA_OP_LCMP) { - cfg.value.BF.d_reg_idx = dRegIndex; - cfg.value.BF.d_reg_type = dRegType; - } - - cfg.value.BF.op = op; - cfg.value.BF.last_op = lastOp; - - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD); -} - -/****************************************************************************/ /** - * @brief PKA write common operation second configuration1 - * - * @param s1RegIndex: Register index - * @param s1RegType: Register type - * - * @return None - * -*******************************************************************************/ -static void Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1(uint8_t s1RegIndex, uint8_t s1RegType) -{ - struct pka0_common_op_snd_cfg_S1_only cfg; - - cfg.value.BF.s1_reg_idx = s1RegIndex; - cfg.value.BF.s1_reg_type = s1RegType; - - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD); -} - -/****************************************************************************/ /** - * @brief PKA write common operation second configuration2 - * - * @param s2RegIndex: Register index - * @param s2RegType: Register type - * - * @return None - * -*******************************************************************************/ -static void Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S2(uint8_t s2RegIndex, uint8_t s2RegType) -{ - struct pka0_common_op_snd_cfg_S2_only cfg; - - cfg.value.BF.s2_reg_idx = s2RegIndex; - cfg.value.BF.s2_reg_type = s2RegType; - - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD); -} - -/****************************************************************************/ /** - * @brief PKA write common operation second configuration1 and configuration 2 - * - * @param s1RegIndex: Configuration 1 Register index - * @param s1RegType: Configuration 1 Register type - * @param s2RegIndex: Configuration 2 Register index - * @param s2RegType: Configuration 3 Register type - * - * @return None - * -*******************************************************************************/ -static void Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1_S2(uint8_t s1RegIndex, uint8_t s1RegType, uint8_t s2RegIndex, uint8_t s2RegType) -{ - struct pka0_common_op_snd_cfg_S1_S2 cfg; - - cfg.value.BF.s1_reg_idx = s1RegIndex; - cfg.value.BF.s1_reg_type = s1RegType; - cfg.value.BF.s2_reg_idx = s2RegIndex; - cfg.value.BF.s2_reg_type = s2RegType; - - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD); -} - -/****************************************************************************/ /** - * @brief PKA wait for complete interrupt - * - * @param None - * - * @return SUCCESS - * -*******************************************************************************/ -static BL_Err_Type Sec_Eng_PKA_Wait_ISR(void) -{ - uint32_t pka0_ctrl; - uint32_t timeoutCnt = SEC_ENG_PKA_INT_TIMEOUT_COUNT; - - do { - pka0_ctrl = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (!BL_GET_REG_BITS_VAL(pka0_ctrl, SEC_ENG_SE_PKA_0_INT)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief PKA read block data from register - * - * @param dest: Pointer to buffer address - * @param src: Pointer to register address - * @param len: Data len in word - * - * @return None - * -*******************************************************************************/ -#ifdef ARCH_ARM -#ifndef __GNUC__ -__ASM void Sec_Eng_PKA_Read_Block(uint32_t *dest, const uint32_t *src, uint32_t len) -{ - PUSH{ R3 - R6, LR } Start0 - CMP R2, -# 4 BLT Finish0 - LDR R3, - [R1] LDR R4, [R1] LDR R5, [R1] LDR R6, [R1] STMIA R0 !, { R3 - R6 } SUBS R2, R2, #4 B Start0 Finish0 POP - { - R3 - R6, PC - } -} -#else -void Sec_Eng_PKA_Read_Block(uint32_t *dest, const uint32_t *src, uint32_t len) -{ - __asm__ __volatile__("push {r3-r6,lr}\n\t" - "Start0 :" - "cmp r2,#4\n\t" - "blt Finish0\n\t" - "ldr r3,[r1]\n\t" - "ldr r4,[r1]\n\t" - "ldr r5,[r1]\n\t" - "ldr r6,[r1]\n\t" - "stmia r0!,{r3-r6}\n\t" - "sub r2,r2,#4\n\t" - "b Start0\n\t" - "Finish0 :" - "pop {r3-r6,pc}\n\t"); -} -#endif -#endif -#ifdef ARCH_RISCV -void Sec_Eng_PKA_Read_Block(uint32_t *dest, const uint32_t *src, uint32_t len) -{ - uint32_t wrLen = len - len % 4; - uint32_t i; - - for (i = 0; i < wrLen; i++) { - dest[i] = *src; - } -} -#endif - -/****************************************************************************/ /** - * @brief PKA Write block data to register - * - * @param dest: Pointer to register address - * @param src: Pointer to buffer address - * @param len: Data len in word - * - * @return None - * -*******************************************************************************/ -#ifdef ARCH_ARM -#ifndef __GNUC__ -__ASM void Sec_Eng_PKA_Write_Block(uint32_t *dest, const uint32_t *src, uint32_t len) -{ - PUSH{ R3 - R6, LR } Start1 - CMP R2, -# 4 BLT Finish1 - LDMIA R1 !, - { R3 - R6 } STR R3, [R0] STR R4, [R0] STR R5, [R0] STR R6, [R0] SUBS R2, R2, #4 B Start1 Finish1 POP - { - R3 - R6, PC - } -} -#else -void Sec_Eng_PKA_Write_Block(uint32_t *dest, const uint32_t *src, uint32_t len) -{ - __asm__ __volatile__("push {r3-r6,lr}\n\t" - "Start1 :" - "cmp r2,#4\n\t" - "blt Finish1\n\t" - "ldmia r1!,{r3-r6}\n\t" - "str r3,[r0]\n\t" - "str r4,[r0]\n\t" - "str r5,[r0]\n\t" - "str r6,[r0]\n\t" - "sub r2,r2,#4\n\t" - "b Start1\n\t" - "Finish1 :" - "pop {r3-r6,pc}\n\t"); -} -#endif -#endif -#ifdef ARCH_RISCV -void Sec_Eng_PKA_Write_Block(uint32_t *dest, const uint32_t *src, uint32_t len) -{ - uint32_t wrLen = len - len % 4; - uint32_t i; - - for (i = 0; i < wrLen; i++) { - *dest = src[i]; - } -} -#endif - -/****************************************************************************/ /** - * @brief PKA get result - * - * @param result: Pointer to store result - * @param retSize: Result length in word - * @param regLen: register length in byte - * - * @return None - * -*******************************************************************************/ -static void Sec_Eng_PKA_Get_Result(uint32_t *result, uint8_t retSize, uint16_t regLen) -{ - uint32_t ret_data = 0x00; - int index = 0x00; - - /* Wait for the result */ - Sec_Eng_PKA_Wait_ISR(); - Sec_Eng_PKA_Clear_Int(); - Sec_Eng_PKA_Read_Block(result, (uint32_t *)(SEC_ENG_BASE + SEC_ENG_SE_PKA_0_RW_OFFSET), retSize); - index = retSize - (retSize % 4); - - while (index < retSize) { - ret_data = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW); - result[index] = ret_data; - index++; - } -} - -/****************************************************************************/ /** - * @brief PKA load data to register - * - * @param regType: Register type - * @param regIndex: Register index - * @param data: Data buffer - * @param size: Data length in word - * @param lastOp: Last operation - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_Type regType, uint8_t regIndex, const uint32_t *data, uint16_t size, uint8_t lastOp) -{ - int index = 0x00; - uint16_t regLen = Sec_Eng_PKA_Get_Reg_Size(regType); - - Sec_Eng_PKA_Write_Pld_Cfg(size, regIndex, regType, SEC_ENG_PKA_OP_CTLIR_PLD, lastOp); - - if (size > regLen / 4) { - size = regLen / 4; - } - - Sec_Eng_PKA_Write_Block((uint32_t *)(SEC_ENG_BASE + SEC_ENG_SE_PKA_0_RW_OFFSET), data, size); - index = size - (size % 4); - - while (index < size) { - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, data[index]); - index++; - } -} - -/****************************************************************************/ /** - * @brief PKA read data from register - * - * @param regType: Register type - * @param regIdx: Register index - * @param result: Data buffer - * @param retSize: Data length in word - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_Read_Data(SEC_ENG_PKA_REG_SIZE_Type regType, uint8_t regIdx, uint32_t *result, uint8_t retSize) -{ - uint16_t regSize; - uint32_t dummyData = 0; - - regSize = Sec_Eng_PKA_Get_Reg_Size(regType); - - if (retSize > regSize / 4) { - result = NULL; - return; - } - - Sec_Eng_PKA_Write_Pld_Cfg(retSize, regIdx, regType, SEC_ENG_PKA_OP_CFLIR_BUFFER, 1); - - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, dummyData); - - Sec_Eng_PKA_Get_Result(result, retSize, regSize); -} - -/****************************************************************************/ /** - * @brief PKA clear register - * - * @param dRegType: Register type - * @param dRegIdx: Register index - * @param size: Data length in word - * @param lastOp: Last operation - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_CREG(SEC_ENG_PKA_REG_SIZE_Type dRegType, uint8_t dRegIdx, uint8_t size, uint8_t lastOp) -{ - uint32_t dummyData = 0; - - Sec_Eng_PKA_Write_Pld_Cfg(size, dRegIdx, dRegType, SEC_ENG_PKA_OP_CLIR, lastOp); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, dummyData); - - if (lastOp) { - Sec_Eng_PKA_Wait_ISR(); - Sec_Eng_PKA_Clear_Int(); - } -} - -/****************************************************************************/ /** - * @brief PKA load data to register - * - * @param regType: regType: Register type - * @param regIndex: regIndex: Register index - * @param data: data: Data buffer - * @param lastOp: size: Data length in word - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_Write_Immediate(SEC_ENG_PKA_REG_SIZE_Type regType, uint8_t regIndex, uint32_t data, uint8_t lastOp) -{ - struct pka0_pldi_cfg cfg; - - cfg.value.BF.rsvd = 0; - cfg.value.BF.d_reg_index = regIndex; - cfg.value.BF.d_reg_type = regType; - cfg.value.BF.op = SEC_ENG_PKA_OP_SLIR; - cfg.value.BF.last_op = lastOp; - - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, data); - - if (lastOp) { - Sec_Eng_PKA_Wait_ISR(); - Sec_Eng_PKA_Clear_Int(); - } -} - -/****************************************************************************/ /** - * @brief PKA negative source data:D = (1 << SIZE{S0})-S0 - * - * @param dRegType: Destination Register type - * @param dRegIdx: Destination Register index - * @param s0RegType: Source Register type - * @param s0RegIdx: Source Register index - * @param lastOp: Last operation - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_NREG(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp) -{ - uint32_t dummyData = 0; - - Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_NLIR, lastOp); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, dummyData); - - if (lastOp) { - Sec_Eng_PKA_Wait_ISR(); - Sec_Eng_PKA_Clear_Int(); - } -} - -/****************************************************************************/ /** - * @brief PKA move data:D = S0 - * - * @param dRegType: Destination Register type - * @param dRegIdx: Destination Register index - * @param s0RegType: Source Register type - * @param s0RegIdx: Source Register index - * @param lastOp: Last operation - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_Move_Data(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp) -{ - uint32_t dummyData = 0; - - Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MOVDAT, lastOp); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, dummyData); - - if (lastOp) { - Sec_Eng_PKA_Wait_ISR(); - Sec_Eng_PKA_Clear_Int(); - } -} - -/****************************************************************************/ /** - * @brief PKA resize data:D = S0, D.Size = S0.Size - * - * @param dRegType: Destination Register type - * @param dRegIdx: Destination Register index - * @param s0RegType: Source Register type - * @param s0RegIdx: Source Register index - * @param lastOp: Last operation - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_RESIZE(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp) -{ - uint32_t dummyData = 0; - - Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_RESIZE, lastOp); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, dummyData); - - if (lastOp) { - Sec_Eng_PKA_Wait_ISR(); - Sec_Eng_PKA_Clear_Int(); - } -} - -/****************************************************************************/ /** - * @brief PKA mod add:D = (S0 + S1) mod S2 - * - * @param dRegType: Destination Register type - * @param dRegIdx: Destination Register index - * @param s0RegType: Source 0 Register type - * @param s0RegIdx: Source 0 Register index - * @param s1RegType: Source 1 Register type - * @param s1RegIdx: Source 1 Register index - * @param s2RegType: Source 2 Register type - * @param s2RegIdx: Source 2 Register index - * @param lastOp: Last operation - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_MADD(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint8_t s1RegType, uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp) -{ - Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MADD, lastOp); - Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1_S2(s1RegIdx, s1RegType, s2RegIdx, s2RegType); - - if (lastOp) { - Sec_Eng_PKA_Wait_ISR(); - Sec_Eng_PKA_Clear_Int(); - } -} - -/****************************************************************************/ /** - * @brief PKA mod sub:D = (S0 - S1) mod S2 - * - * @param dRegType: Destination Register type - * @param dRegIdx: Destination Register index - * @param s0RegType: Source 0 Register type - * @param s0RegIdx: Source 0 Register index - * @param s1RegType: Source 1 Register type - * @param s1RegIdx: Source 1 Register index - * @param s2RegType: Source 2 Register type - * @param s2RegIdx: Source 2 Register index - * @param lastOp: Last operation - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_MSUB(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint8_t s1RegType, uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp) -{ - Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MSUB, lastOp); - Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1_S2(s1RegIdx, s1RegType, s2RegIdx, s2RegType); - - if (lastOp) { - Sec_Eng_PKA_Wait_ISR(); - Sec_Eng_PKA_Clear_Int(); - } -} - -/****************************************************************************/ /** - * @brief PKA mod :D = S0 mod S2 - * - * @param dRegType: Destination Register type - * @param dRegIdx: Destination Register index - * @param s0RegType: Source 0 Register type - * @param s0RegIdx: Source 0 Register index - * @param s2RegType: Source 2 Register type - * @param s2RegIdx: Source 2 Register index - * @param lastOp: Last operation - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_MREM(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp) -{ - Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MREM, lastOp); - Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S2(s2RegIdx, s2RegType); - - if (lastOp) { - Sec_Eng_PKA_Wait_ISR(); - Sec_Eng_PKA_Clear_Int(); - } -} - -/****************************************************************************/ /** - * @brief PKA mod mul:D = (S0 * S1) mod S2 - * - * @param dRegType: Destination Register type - * @param dRegIdx: Destination Register index - * @param s0RegType: Source 0 Register type - * @param s0RegIdx: Source 0 Register index - * @param s1RegType: Source 1 Register type - * @param s1RegIdx: Source 1 Register index - * @param s2RegType: Source 2 Register type - * @param s2RegIdx: Source 2 Register index - * @param lastOp: Last operation - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_MMUL(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint8_t s1RegType, uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp) -{ - Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MMUL, lastOp); - Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1_S2(s1RegIdx, s1RegType, s2RegIdx, s2RegType); - - if (lastOp) { - Sec_Eng_PKA_Wait_ISR(); - Sec_Eng_PKA_Clear_Int(); - } -} - -/****************************************************************************/ /** - * @brief PKA mod sqr:D = (S0 ^ 2) mod S2 - * - * @param dRegType: Destination Register type - * @param dRegIdx: Destination Register index - * @param s0RegType: Source 0 Register type - * @param s0RegIdx: Source 0 Register index - * @param s2RegType: Source 2 Register type - * @param s2RegIdx: Source 2 Register index - * @param lastOp: Last operation - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_MSQR(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp) -{ - Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MSQR, lastOp); - Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S2(s2RegIdx, s2RegType); - - if (lastOp) { - Sec_Eng_PKA_Wait_ISR(); - Sec_Eng_PKA_Clear_Int(); - } -} - -/****************************************************************************/ /** - * @brief PKA mod exp:D = (S0 ^ S1) mod S2 - * - * @param dRegType: Destination Register type - * @param dRegIdx: Destination Register index - * @param s0RegType: Source 0 Register type - * @param s0RegIdx: Source 0 Register index - * @param s1RegType: Source 1 Register type - * @param s1RegIdx: Source 1 Register index - * @param s2RegType: Source 2 Register type - * @param s2RegIdx: Source 2 Register index - * @param lastOp: Last operation - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_MEXP(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint8_t s1RegType, uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp) -{ - Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MEXP, lastOp); - Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1_S2(s1RegIdx, s1RegType, s2RegIdx, s2RegType); - - if (lastOp) { - Sec_Eng_PKA_Wait_ISR(); - Sec_Eng_PKA_Clear_Int(); - } -} - -/****************************************************************************/ /** - * @brief PKA mod exp:D = (S0 ^ (S2-2) ) mod S2 - * - * @param dRegType: Destination Register type - * @param dRegIdx: Destination Register index - * @param s0RegType: Source 0 Register type - * @param s0RegIdx: Source 0 Register index - * @param s2RegType: Source 2 Register type - * @param s2RegIdx: Source 2 Register index - * @param lastOp: Last operation - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_MINV(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp) -{ - Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MINV, lastOp); - Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S2(s2RegIdx, s2RegType); - - if (lastOp) { - Sec_Eng_PKA_Wait_ISR(); - Sec_Eng_PKA_Clear_Int(); - } -} - -/****************************************************************************/ /** - * @brief PKA Report COUT to 1 when S0 < S1 - * - * @param cout: Compare result - * @param s0RegType: Source 0 Register type - * @param s0RegIdx: Source 0 Register index - * @param s1RegType: Source 1 Register type - * @param s1RegIdx: Source 1 Register index - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_LCMP(uint8_t *cout, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t s1RegType, uint8_t s1RegIdx) -{ - uint32_t pka0_ctrl = 0x00; - - Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, 0, 0, SEC_ENG_PKA_OP_LCMP, 1); - Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1(s1RegIdx, s1RegType); - - Sec_Eng_PKA_Wait_ISR(); - Sec_Eng_PKA_Clear_Int(); - pka0_ctrl = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0); - - *cout = (pka0_ctrl & SEC_ENG_PKA_STATUS_LAST_OPC_MASK) >> SEC_ENG_PKA_STATUS_LAST_OPC_OFFSET; -} - -/****************************************************************************/ /** - * @brief PKA add:D = S0 + S1 - * - * @param dRegType: Destination Register type - * @param dRegIdx: Destination Register index - * @param s0RegType: Source 0 Register type - * @param s0RegIdx: Source 0 Register index - * @param s1RegType: Source 1 Register type - * @param s1RegIdx: Source 1 Register index - * @param lastOp: Last operation - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_LADD(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint8_t s1RegType, uint8_t s1RegIdx, uint8_t lastOp) -{ - Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LADD, lastOp); - Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1(s1RegIdx, s1RegType); - - if (lastOp) { - Sec_Eng_PKA_Wait_ISR(); - Sec_Eng_PKA_Clear_Int(); - } -} - -/****************************************************************************/ /** - * @brief PKA sub:D = S0 - S1 - * - * @param dRegType: Destination Register type - * @param dRegIdx: Destination Register index - * @param s0RegType: Source 0 Register type - * @param s0RegIdx: Source 0 Register index - * @param s1RegType: Source 1 Register type - * @param s1RegIdx: Source 1 Register index - * @param lastOp: Last operation - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_LSUB(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint8_t s1RegType, uint8_t s1RegIdx, uint8_t lastOp) -{ - Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LSUB, lastOp); - Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1(s1RegIdx, s1RegType); - - if (lastOp) { - Sec_Eng_PKA_Wait_ISR(); - Sec_Eng_PKA_Clear_Int(); - } -} - -/****************************************************************************/ /** - * @brief PKA mul:D = S0 * S1 - * - * @param dRegType: Destination Register type - * @param dRegIdx: Destination Register index - * @param s0RegType: Source 0 Register type - * @param s0RegIdx: Source 0 Register index - * @param s1RegType: Source 1 Register type - * @param s1RegIdx: Source 1 Register index - * @param lastOp: Last operation - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_LMUL(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint8_t s1RegType, uint8_t s1RegIdx, uint8_t lastOp) -{ - Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LMUL, lastOp); - Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1(s1RegIdx, s1RegType); - - if (lastOp) { - Sec_Eng_PKA_Wait_ISR(); - Sec_Eng_PKA_Clear_Int(); - } -} - -/****************************************************************************/ /** - * @brief PKA sqr:D = S0^2 - * - * @param dRegType: Destination Register type - * @param dRegIdx: Destination Register index - * @param s0RegType: Source 0 Register type - * @param s0RegIdx: Source 0 Register index - * @param lastOp: Last operation - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_LSQR(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp) -{ - uint32_t dummyData = 0; - - Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LSQR, lastOp); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, dummyData); - - if (lastOp) { - Sec_Eng_PKA_Wait_ISR(); - Sec_Eng_PKA_Clear_Int(); - } -} - -/****************************************************************************/ /** - * @brief PKA div:D = S0 / S2 - * - * @param dRegType: Destination Register type - * @param dRegIdx: Destination Register index - * @param s0RegType: Source 0 Register type - * @param s0RegIdx: Source 0 Register index - * @param s2RegType: Source 2 Register type - * @param s2RegIdx: Source 2 Register index - * @param lastOp: Last operation - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_LDIV(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp) -{ - Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LDIV, lastOp); - Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S2(s2RegIdx, s2RegType); - - if (lastOp) { - Sec_Eng_PKA_Wait_ISR(); - Sec_Eng_PKA_Clear_Int(); - } -} - -/****************************************************************************/ /** - * @brief PKA shift:D = S0 << BIT SHIFT - * - * @param dRegType: Destination Register type - * @param dRegIdx: Destination Register index - * @param s0RegType: Source 0 Register type - * @param s0RegIdx: Source 0 Register index - * @param bit_shift: Bits to shift - * @param lastOp: Last operation - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_LMUL2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint16_t bit_shift, uint8_t lastOp) -{ - struct pka0_bit_shift_op_cfg cfg; - - Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LMUL2N, 0); - - cfg.value.BF.bit_shift = bit_shift; - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD); - - if (lastOp) { - Sec_Eng_PKA_Wait_ISR(); - Sec_Eng_PKA_Clear_Int(); - } -} - -/****************************************************************************/ /** - * @brief PKA shift:D = S0 >> BIT SHIFT - * - * @param dRegType: Destination Register type - * @param dRegIdx: Destination Register index - * @param s0RegType: Source 0 Register type - * @param s0RegIdx: Source 0 Register index - * @param bit_shift: Bits to shift - * @param lastOp: Last operation - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_LDIV2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint16_t bit_shift, uint8_t lastOp) -{ - struct pka0_bit_shift_op_cfg cfg; - - Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LDIV2N, 0); - - cfg.value.BF.bit_shift = bit_shift; - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD); - - if (lastOp) { - Sec_Eng_PKA_Wait_ISR(); - Sec_Eng_PKA_Clear_Int(); - } -} - -/****************************************************************************/ /** - * @brief PKA mod 2N:D = S0 % ((1 << BIT SHIFT)-1) - * - * @param dRegType: Destination Register type - * @param dRegIdx: Destination Register index - * @param s0RegType: Source 0 Register type - * @param s0RegIdx: Source 0 Register index - * @param bit_shift: Bits to shift - * @param lastOp: Last operation - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_LMOD2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint16_t bit_shift, uint8_t lastOp) -{ - struct pka0_bit_shift_op_cfg cfg; - - Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MOD2N, lastOp); - - cfg.value.BF.bit_shift = bit_shift; - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD); - - if (lastOp) { - Sec_Eng_PKA_Wait_ISR(); - Sec_Eng_PKA_Clear_Int(); - } -} - -/****************************************************************************/ /** - * @brief PKA GF to Mont filed 2N:d = (a<> 6) & 0x03) == 0x03) { - /* SHA control idle, write to request*/ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_PROT, 0x02); - - /* Check request result */ - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD); - - if (((tmpVal >> 6) & 0x03) == 0x01) { - return SUCCESS; - } - } - - return ERROR; -} - -/****************************************************************************/ /** - * @brief Group0 release PKA Access - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_Group0_Release_PKA_Access(void) -{ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_PROT, 0x06); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Group1 request PKA Access - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_Group1_Request_PKA_Access(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD); - - if (((tmpVal >> 6) & 0x03) == 0x03) { - /* SHA control idle, write to request*/ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_PROT, 0x04); - - /* Check request result */ - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD); - - if (((tmpVal >> 6) & 0x03) == 0x02) { - return SUCCESS; - } - } - - return ERROR; -} - -/****************************************************************************/ /** - * @brief Group1 release PKA Access - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_Group1_Release_PKA_Access(void) -{ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_PROT, 0x06); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Set gmac little endian - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_GMAC_Enable_LE(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0); - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_GMAC_0_T_ENDIAN); - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_GMAC_0_H_ENDIAN); - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_GMAC_0_X_ENDIAN); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0, tmpVal); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(SEC_ENG_ID0_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_GMAC_IRQHandler); - Interrupt_Handler_Register(SEC_ENG_ID1_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_GMAC_IRQHandler); -#endif -} - -/****************************************************************************/ /** - * @brief Set gmac big endian - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_GMAC_Enable_BE(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0); - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_GMAC_0_T_ENDIAN); - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_GMAC_0_H_ENDIAN); - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_GMAC_0_X_ENDIAN); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0, tmpVal); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(SEC_ENG_ID0_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_GMAC_IRQHandler); - Interrupt_Handler_Register(SEC_ENG_ID1_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_GMAC_IRQHandler); -#endif -} - -/****************************************************************************/ /** - * @brief GMAC enable link mode - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_GMAC_Enable_Link(void) -{ - uint32_t tmpVal; - - /* Enable gmac link mode */ - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_GMAC_0_EN)); -} - -/****************************************************************************/ /** - * @brief GMAC disable link mode - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_GMAC_Disable_Link(void) -{ - uint32_t tmpVal; - - /* Disable gmac link mode */ - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0, BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_GMAC_0_EN)); -} - -/****************************************************************************/ /** - * @brief GMAC work in link mode - * - * @param linkAddr: Address of config structure in link mode - * @param in: GMAC input data buffer to deal with - * @param len: GMAC input data length - * @param out: GMAC output data buffer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_GMAC_Link_Work(uint32_t linkAddr, const uint8_t *in, uint32_t len, uint8_t *out) -{ - uint32_t GMACx = SEC_ENG_BASE; - uint32_t tmpVal; - uint32_t timeoutCnt = SEC_ENG_GMAC_BUSY_TIMEOUT_COUNT; - - /* Link address should word align */ - if ((linkAddr & 0x03) != 0 || len % 16 != 0) { - return ERROR; - } - - /* Wait finished */ - do { - tmpVal = BL_RD_REG(GMACx, SEC_ENG_SE_GMAC_0_CTRL_0); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_GMAC_0_BUSY)); - - /* Set link address */ - BL_WR_REG(GMACx, SEC_ENG_SE_GMAC_0_LCA, linkAddr); - - /* Change source buffer address */ - *(uint32_t *)(uintptr_t)(linkAddr + 4) = (uint32_t)(uintptr_t)in; - - /* Set data length */ - *((uint16_t *)(uintptr_t)linkAddr + 1) = len / 16; - - /* Start gmac engine and wait finishing */ - tmpVal = BL_RD_REG(GMACx, SEC_ENG_SE_GMAC_0_CTRL_0); - BL_WR_REG(GMACx, SEC_ENG_SE_GMAC_0_CTRL_0, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_GMAC_0_TRIG_1T)); - timeoutCnt = SEC_ENG_GMAC_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(GMACx, SEC_ENG_SE_GMAC_0_CTRL_0); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_GMAC_0_BUSY)); - - /* Get result */ - ARCH_MemCpy_Fast(out, (uint8_t *)(uintptr_t)(linkAddr + 0x18), 16); - - return SUCCESS; -} - -#ifndef BFLB_USE_HAL_DRIVER -/****************************************************************************/ /** - * @brief Sec Eng Interrupt Handler - * - * @param intType: IRQ Type - * - * @return None - * -*******************************************************************************/ -static void SEC_Eng_IntHandler(SEC_ENG_INT_Type intType) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_INT_TYPE(intType)); - - switch (intType) { - case SEC_ENG_INT_TRNG: - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_0); - - if (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_TRNG_0_INT)) { - /* Clear interrupt */ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_0, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_INT_CLR_1T)); - - /* Call the callback function */ - if (secEngIntCbfArra[SEC_ENG_INT_TRNG] != NULL) { - secEngIntCbfArra[SEC_ENG_INT_TRNG](); - } - } - - break; - - case SEC_ENG_INT_AES: - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL); - - if (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_AES_0_INT)) { - /* Clear interrupt */ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_INT_CLR_1T)); - - /* Call the callback function */ - if (secEngIntCbfArra[SEC_ENG_INT_AES] != NULL) { - secEngIntCbfArra[SEC_ENG_INT_AES](); - } - } - - break; - - case SEC_ENG_INT_SHA: - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_SHA_0_CTRL); - - if (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_INT)) { - /* Clear interrupt */ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_SHA_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_INT_CLR_1T)); - - /* Call the callback function */ - if (secEngIntCbfArra[SEC_ENG_INT_SHA] != NULL) { - secEngIntCbfArra[SEC_ENG_INT_SHA](); - } - } - - break; - - case SEC_ENG_INT_PKA: - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0); - - if (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_PKA_0_INT)) { - /* Clear interrupt */ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_PKA_0_INT_CLR_1T)); - - /* Call the callback function */ - if (secEngIntCbfArra[SEC_ENG_INT_PKA] != NULL) { - secEngIntCbfArra[SEC_ENG_INT_PKA](); - } - } - - break; - - case SEC_ENG_INT_CDET: - - /* Call the callback function */ - if (secEngIntCbfArra[SEC_ENG_INT_CDET] != NULL) { - secEngIntCbfArra[SEC_ENG_INT_CDET](); - } - - break; - - case SEC_ENG_INT_GMAC: - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0); - - if (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_GMAC_0_INT)) { - /* Clear interrupt */ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_GMAC_0_INT_CLR_1T)); - - /* Call the callback function */ - if (secEngIntCbfArra[SEC_ENG_INT_GMAC] != NULL) { - secEngIntCbfArra[SEC_ENG_INT_GMAC](); - } - } - - break; - - default: - break; - } -} -#endif - -/****************************************************************************/ /** - * @brief Group0 request GMAC Access - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_Group0_Request_GMAC_Access(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD); - - if (((tmpVal >> 10) & 0x03) == 0x03) { - /* SHA control idle, write to request*/ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_PROT, 0x02); - - /* Check request result */ - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD); - - if (((tmpVal >> 10) & 0x03) == 0x01) { - return SUCCESS; - } - } - - return ERROR; -} - -/****************************************************************************/ /** - * @brief Group0 release GMAC Access - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_Group0_Release_GMAC_Access(void) -{ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_PROT, 0x06); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Group1 request GMAC Access - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_Group1_Request_GMAC_Access(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD); - - if (((tmpVal >> 10) & 0x03) == 0x03) { - /* SHA control idle, write to request*/ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_PROT, 0x04); - - /* Check request result */ - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD); - - if (((tmpVal >> 10) & 0x03) == 0x02) { - return SUCCESS; - } - } - - return ERROR; -} - -/****************************************************************************/ /** - * @brief Group1 release GMAC Access - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_Group1_Release_GMAC_Access(void) -{ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_PROT, 0x06); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Sec Eng Interrupt Mask or Unmask - * - * @param intType: Sec Eng Interrupt Type - * @param intMask: MASK or UNMASK - * - * @return None - * -*******************************************************************************/ -void SEC_Eng_IntMask(SEC_ENG_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_INT_TYPE(intType)); - - switch (intType) { - case SEC_ENG_INT_TRNG: - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_0); - - if (intMask == UNMASK) { - /* UNMASK(Enable) this interrupt */ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_0, BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_INT_MASK)); - } else { - /* MASK(Disable) this interrupt */ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_0, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_INT_MASK)); - } - - break; - - case SEC_ENG_INT_AES: - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL); - - if (intMask == UNMASK) { - /* UNMASK(Enable) this interrupt */ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL, BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_INT_MASK)); - } else { - /* MASK(Disable) this interrupt */ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_INT_MASK)); - } - - break; - - case SEC_ENG_INT_SHA: - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_SHA_0_CTRL); - - if (intMask == UNMASK) { - /* UNMASK(Enable) this interrupt */ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_SHA_0_CTRL, BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_INT_MASK)); - } else { - /* MASK(Disable) this interrupt */ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_SHA_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_INT_MASK)); - } - - break; - - case SEC_ENG_INT_PKA: - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0); - - if (intMask == UNMASK) { - /* UNMASK(Enable) this interrupt */ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_PKA_0_INT_MASK)); - } else { - /* MASK(Disable) this interrupt */ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_PKA_0_INT_MASK)); - } - - break; - - case SEC_ENG_INT_CDET: - break; - - case SEC_ENG_INT_GMAC: - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0); - - if (intMask == UNMASK) { - /* UNMASK(Enable) this interrupt */ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0, BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_GMAC_0_INT_MASK)); - } else { - /* MASK(Disable) this interrupt */ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_GMAC_0_INT_MASK)); - } - - break; - - case SEC_ENG_INT_ALL: - if (intMask == UNMASK) { - /* UNMASK(Enable) this interrupt */ - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_0); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_0, BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_INT_MASK)); - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL, BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_INT_MASK)); - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_SHA_0_CTRL); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_SHA_0_CTRL, BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_INT_MASK)); - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_PKA_0_INT_MASK)); - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0, BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_GMAC_0_INT_MASK)); - } else { - /* MASK(Disable) this interrupt */ - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_0); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_0, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_INT_MASK)); - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_INT_MASK)); - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_SHA_0_CTRL); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_SHA_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_INT_MASK)); - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_PKA_0_INT_MASK)); - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_GMAC_0_INT_MASK)); - } - - break; - - default: - break; - } -} - -/****************************************************************************/ /** - * @brief Sec Eng Interrupt clear - * - * @param intType: Sec Eng Interrupt Type - * - * @return None - * -*******************************************************************************/ -void SEC_Eng_ClrIntStatus(SEC_ENG_INT_Type intType) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_INT_TYPE(intType)); - - switch (intType) { - case SEC_ENG_INT_AES: - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_INT_CLR_1T)); - break; - - case SEC_ENG_INT_SHA: - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_SHA_0_CTRL); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_SHA_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_INT_CLR_1T)); - break; - - case SEC_ENG_INT_TRNG: - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_0); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_0, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_INT_CLR_1T)); - break; - - case SEC_ENG_INT_PKA: - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_PKA_0_INT_CLR_1T)); - break; - - case SEC_ENG_INT_CDET: - break; - - case SEC_ENG_INT_GMAC: - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_GMAC_0_INT_CLR_1T)); - break; - - default: - break; - } -} - -/****************************************************************************/ /** - * @brief Sec Eng Interrupt callback function install - * - * @param intType: Sec Eng Interrupt Type - * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void SEC_Eng_Int_Callback_Install(SEC_ENG_INT_Type intType, intCallback_Type *cbFun) -{ - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_INT_TYPE(intType)); - - secEngIntCbfArra[intType] = cbFun; -} -#endif - -/****************************************************************************/ /** - * @brief Sec Eng get interrupt status - * - * @param intType: Sec Eng Interrupt Type - * - * @return status of interrupt - * -*******************************************************************************/ -BL_Sts_Type SEC_Eng_GetIntStatus(SEC_ENG_INT_Type intType) -{ - uint32_t tmpVal; - BL_Sts_Type status = RESET; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_INT_TYPE(intType)); - - switch (intType) { - case SEC_ENG_INT_AES: - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL); - - if (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_AES_0_INT)) { - status = SET; - } - - break; - - case SEC_ENG_INT_SHA: - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_SHA_0_CTRL); - - if (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_INT)) { - status = SET; - } - - break; - - case SEC_ENG_INT_TRNG: - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_0); - - if (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_TRNG_0_INT)) { - status = SET; - } - - break; - - case SEC_ENG_INT_PKA: - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0); - - if (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_PKA_0_INT)) { - status = SET; - } - - break; - - case SEC_ENG_INT_CDET: - break; - - case SEC_ENG_INT_GMAC: - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0); - - if (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_GMAC_0_INT)) { - status = SET; - } - - break; - - default: - break; - } - - return status; -} - -#ifndef BFLB_USE_HAL_DRIVER -/****************************************************************************/ /** - * @brief Sec Eng Trng IRQ Handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -void SEC_TRNG_IRQHandler(void) -{ - SEC_Eng_IntHandler(SEC_ENG_INT_TRNG); -} - -/****************************************************************************/ /** - * @brief Sec Eng Pka IRQ Handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -void SEC_PKA_IRQHandler(void) -{ - SEC_Eng_IntHandler(SEC_ENG_INT_PKA); -} - -/****************************************************************************/ /** - * @brief Sec Eng Aes IRQ Handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -void SEC_AES_IRQHandler(void) -{ - SEC_Eng_IntHandler(SEC_ENG_INT_AES); -} - -/****************************************************************************/ /** - * @brief Sec Eng Sha IRQ Handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -void SEC_SHA_IRQHandler(void) -{ - SEC_Eng_IntHandler(SEC_ENG_INT_SHA); -} - -/****************************************************************************/ /** - * @brief Sec Eng Cdet IRQ Handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -void SEC_CDET_IRQHandler(void) -{ - SEC_Eng_IntHandler(SEC_ENG_INT_CDET); -} - -/****************************************************************************/ /** - * @brief Sec Eng Gmac IRQ Handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -void SEC_GMAC_IRQHandler(void) -{ - SEC_Eng_IntHandler(SEC_ENG_INT_GMAC); -} -#endif - -/****************************************************************************/ /** - * @brief turn on sec ring - * - * @param None - * - * @return None - * -*******************************************************************************/ -void ATTR_TCM_SECTION SEC_Eng_Turn_On_Sec_Ring(void) -{ - uint32_t tmpVal = 0; - - /* Turn-on Sec Ring Oscillation */ - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_3); - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_ROSC_EN); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_3, tmpVal); -} - -/****************************************************************************/ /** - * @brief turn off sec ring - * - * @param None - * - * @return None - * -*******************************************************************************/ -void ATTR_TCM_SECTION SEC_Eng_Turn_Off_Sec_Ring(void) -{ - uint32_t tmpVal = 0; - - /* Turn-off Sec Ring Oscillation */ - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_3); - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_ROSC_EN); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_3, tmpVal); -} - -/*@} end of group SEC_ENG_Public_Functions */ - -/*@} end of group SEC_ENG */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sf_cfg.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sf_cfg.c deleted file mode 100644 index 3d0745eb74..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sf_cfg.c +++ /dev/null @@ -1,1673 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_sf_cfg.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_sf_cfg.h" -#include "softcrc.h" -#include "bl808_xip_sflash.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup SF_CFG - * @{ - */ - -/** @defgroup SF_CFG_Private_Macros - * @{ - */ -#define BFLB_FLASH_CFG_MAGIC "FCFG" - -/*@} end of group SF_CFG_Private_Macros */ - -/** @defgroup SF_CFG_Private_Types - * @{ - */ -#ifndef BFLB_USE_ROM_DRIVER -typedef struct -{ - uint32_t jedecID; - char *name; - const SPI_Flash_Cfg_Type *cfg; -} Flash_Info_t; -#endif - -/*@} end of group SF_CFG_Private_Types */ - -/** @defgroup SF_CFG_Private_Variables - * @{ - */ -#ifndef BFLB_USE_ROM_DRIVER -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_80DV = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xef, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 0, - .cReadMode = 0xFF, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3d, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 3, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_16JV = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xef, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x31, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0x20, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 400, - .timeE32k = 1600, - .timeE64k = 2000, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 3, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_64JW = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xef, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x31, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 0, - .cReadMode = 0xf0, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 400, - .timeE32k = 1600, - .timeE64k = 2000, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 3, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_256FV = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xef, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x31, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0x20, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = 0x24, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 400, - .timeE32k = 1600, - .timeE64k = 2000, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 3, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_Q80E_Q16E = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xc8, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0xa0, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 500, - .timeE32k = 2000, - .timeE64k = 2000, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 20, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_WQ80E_WQ16E = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xc8, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 32 / 8, - .cReadSupport = 1, - .cReadMode = 0xa0, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 8 / 8, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 20, - .qeData = 0x12, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_Q32E_Q128E = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xc8, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x31, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0xa0, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 20, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Mxic_128 = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xC2, - - .deBurstWrapCmd = 0xC0, - .deBurstWrapCmdDmyClk = 0x00, - .deBurstWrapDataMode = SF_CTRL_DATA_1_LINE, - .deBurstWrapData = 0x10, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 0, - .qeBit = 0x06, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0xA5, - - .burstWrapCmd = 0xC0, - .burstWrapCmdDmyClk = 0x00, - .burstWrapDataMode = SF_CTRL_DATA_1_LINE, - .burstWrapData = 0x02, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x38, - .qppAddrMode = SF_CTRL_ADDR_4_LINES, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 45, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Mxic_25L256 = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xc2, - - .deBurstWrapCmd = 0xC0, - .deBurstWrapCmdDmyClk = 0x00, - .deBurstWrapDataMode = SF_CTRL_DATA_1_LINE, - .deBurstWrapData = 0x10, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 0, - .qeBit = 0x06, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x15, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0xA5, - - .burstWrapCmd = 0xC0, - .burstWrapCmdDmyClk = 0x00, - .burstWrapDataMode = SF_CTRL_DATA_1_LINE, - .burstWrapData = 0x02, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x38, - .qppAddrMode = SF_CTRL_ADDR_4_LINES, - - .ioMode = (SF_CTRL_QIO_MODE | 0x20), - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 400, - .timeE32k = 1000, - .timeE64k = 2000, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 20, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION Flash_Info_t flashInfos[] = { - { - .jedecID = 0x1440ef, - //.name="Winb_80DV_08_33", - .cfg = &flashCfg_Winb_80DV, - }, - { - .jedecID = 0x1540ef, - //.name="Winb_16JV_16_33", - .cfg = &flashCfg_Winb_16JV, - }, - { - .jedecID = 0x1640ef, - //.name="Winb_32FV_32_33", - .cfg = &flashCfg_Winb_16JV, - }, - { - .jedecID = 0x1840ef, - //.name="Winb_128JV_128_33", - .cfg = &flashCfg_Winb_64JW, - }, - { - .jedecID = 0x1940ef, - //.name="Winb_256FV_128_33", - .cfg = &flashCfg_Winb_256FV, - }, - { - .jedecID = 0x1460ef, - //.name="Winb_80EW_08_18", - .cfg = &flashCfg_Winb_16JV, - }, - { - .jedecID = 0x1560ef, - //.name="Winb_16FW_16_18", - .cfg = &flashCfg_Winb_16JV, - }, - { - .jedecID = 0x1660ef, - //.name="Winb_32FW_32_18", - .cfg = &flashCfg_Winb_16JV, - }, - { - .jedecID = 0x1760ef, - //.name="WB_64JW_64_18", - .cfg = &flashCfg_Winb_64JW, - }, - { - .jedecID = 0x1860ef, - //.name="Winb_128JW_128_18", - .cfg = &flashCfg_Winb_64JW, - }, - { - .jedecID = 0x1570ef, - //.name="Winb_16JV_16_33", - .cfg = &flashCfg_Winb_16JV, - }, - { - .jedecID = 0x1870ef, - //.name="Winb_128JV_128_33", - .cfg = &flashCfg_Winb_64JW, - }, - { - .jedecID = 0x1680ef, - //.name="Winb_32JW_32_18", - .cfg = &flashCfg_Winb_16JV, - }, - { - .jedecID = 0x1880ef, - //.name="Winb_128JW_128_18", - .cfg = &flashCfg_Winb_64JW, - }, - { - .jedecID = 0x1440C8, - //.name="GD_Q08E_08_33", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x1540C8, - //.name="GD_Q16E_16_33", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x1640C8, - //.name="GD_Q32C_32_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x1740C8, - //.name="GD_Q64E_64_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x1840C8, - //.name="GD_Q128E_128_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x1460C8, - //.name="GD_LQ08C_08_18", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x1560C8, - //.name="GD_LE16C_16_18", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x1660C8, - //.name="GD_LQ32D_32_18", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x1760c8, - //.name="GD_LQ64E_64_18", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x1860c8, - //.name="GD_LQ128E_64_18", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x1465C8, - //.name="GD_WQ80E_80_33", - .cfg = &flashCfg_Gd_WQ80E_WQ16E, - }, - { - .jedecID = 0x1565C8, - //.name="GD_WQ16E_16_33", - .cfg = &flashCfg_Gd_WQ80E_WQ16E, - }, - { - .jedecID = 0x1665C8, - //.name="GD_WQ32E_32_33", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x15345e, - //.name="ZB_WQ16A_16_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x15405e, - //.name="ZB_Q16B_16_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x16405e, - //.name="ZB_Q32B_32_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x17405e, - //.name="ZB_Q64B_64_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x14605E, - //.name="ZB_VQ80", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x15605E, - //.name="ZB_VQ16", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x1820C2, - //.name="MX_25L128_128_33", - .cfg = &flashCfg_Mxic_128, - }, - { - .jedecID = 0x1920C2, - //.name="MX_25L256_256_33", - .cfg = &flashCfg_Mxic_25L256, - }, - { - .jedecID = 0x3925C2, - //.name="MX_25U256_256_33", - .cfg = &flashCfg_Mxic_25L256, - }, - { - .jedecID=0x144020, - //.name="XM_25QH80_80_33", - .cfg=&flashCfg_Winb_16JV, - }, - { - .jedecID=0x154020, - //.name="XM_25QH16_16_33", - .cfg=&flashCfg_Winb_16JV, - }, - { - .jedecID=0x164020, - //.name="XM_25QH32_32_33", - .cfg=&flashCfg_Winb_16JV, - }, - { - .jedecID=0x174020, - //.name="XM_25QH64_64_33", - .cfg=&flashCfg_Winb_16JV, - }, - { - .jedecID = 0x15400B, - //.name="XT_25F16B_16_33", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x16400B, - //.name="XT_25F32B_32_33", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x17400B, - //.name="XT_25F64B_32_33", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x18400B, - //.name="XT_25F128B_128_33", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x14600B, - //.name="XT_25Q80B_08_18", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x16600B, - //.name="XT_25Q32B_32_18", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x144068, - //.name="Boya_Q08B_08_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x154068, - //.name="Boya_Q16B_16_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x164068, - //.name="Boya_Q32B_32_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x174068, - //.name="Boya_Q64A_64_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x184068, - //.name="Boya_Q128A_128_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - } -}; -#endif - -/*@} end of group SF_CFG_Private_Variables */ - -/** @defgroup SF_CFG_Global_Variables - * @{ - */ - -/*@} end of group SF_CFG_Global_Variables */ - -/** @defgroup SF_CFG_Private_Fun_Declaration - * @{ - */ - -/*@} end of group SF_CFG_Private_Fun_Declaration */ - -/** @defgroup SF_CFG_Private_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Init external flash GPIO according to flash GPIO config - * - * @param extFlashPin: Flash GPIO config - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Init_Ext_Flash_Gpio(uint8_t extFlashPin) -{ - GLB_GPIO_Cfg_Type cfg; - uint8_t gpiopins[6]; - uint8_t i = 0; - - cfg.gpioMode = GPIO_MODE_AF; - cfg.pullType = GPIO_PULL_UP; - cfg.drive = 2; - cfg.smtCtrl = 1; - cfg.gpioFun = GPIO_FUN_FLASH; - - if (extFlashPin == 0) { - gpiopins[0] = BFLB_EXTFLASH_CLK0_GPIO; - gpiopins[1] = BFLB_EXTFLASH_CS0_GPIO; - gpiopins[2] = BFLB_EXTFLASH_DATA00_GPIO; - gpiopins[3] = BFLB_EXTFLASH_DATA10_GPIO; - gpiopins[4] = BFLB_EXTFLASH_DATA20_GPIO; - gpiopins[5] = BFLB_EXTFLASH_DATA30_GPIO; - } else { - return ERROR; - } - - for (i = 0; i < sizeof(gpiopins); i++) { - cfg.gpioPin = gpiopins[i]; - - if (i == 0 || i == 1) { - /* flash clk and cs is output */ - cfg.gpioMode = GPIO_MODE_OUTPUT; - } else { - /* data are bidir */ - cfg.gpioMode = GPIO_MODE_AF; - } - - GLB_GPIO_Init(&cfg); - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Deinit external flash GPIO according to flash GPIO config - * - * @param extFlashPin: Flash GPIO config - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Deinit_Ext_Flash_Gpio(uint8_t extFlashPin) -{ - GLB_GPIO_Cfg_Type cfg; - uint8_t gpiopins[6]; - uint8_t i = 0; - - cfg.gpioMode = GPIO_MODE_INPUT; - cfg.pullType = GPIO_PULL_UP; - cfg.drive = 1; - cfg.smtCtrl = 1; - cfg.gpioFun = GPIO_FUN_GPIO; - - if (extFlashPin == 0) { - gpiopins[0] = BFLB_EXTFLASH_CLK0_GPIO; - gpiopins[1] = BFLB_EXTFLASH_CS0_GPIO; - gpiopins[2] = BFLB_EXTFLASH_DATA00_GPIO; - gpiopins[3] = BFLB_EXTFLASH_DATA10_GPIO; - gpiopins[4] = BFLB_EXTFLASH_DATA20_GPIO; - gpiopins[5] = BFLB_EXTFLASH_DATA30_GPIO; - } else { - return ERROR; - } - - for (i = 0; i < sizeof(gpiopins); i++) { - cfg.gpioPin = gpiopins[i]; - GLB_GPIO_Init(&cfg); - } - - return SUCCESS; -} -#endif - -/*@} end of group SF_CFG_Private_Functions */ - -/** @defgroup SF_CFG_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Get flash config according to flash ID - * - * @param flashID: Flash ID - * @param pFlashCfg: Flash config pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Get_Flash_Cfg_Need_Lock(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg, - uint8_t group, SF_Ctrl_Bank_Select bank) -{ - uint32_t i; - uint8_t buf[sizeof(SPI_Flash_Cfg_Type) + 8]; - uint32_t crc, *pCrc; - uint32_t xipOffset; - - if (flashID == 0) { - xipOffset = SF_Ctrl_Get_Flash_Image_Offset(group, bank); - SF_Ctrl_Set_Flash_Image_Offset(0, group, bank); - XIP_SFlash_Read_Via_Cache_Need_Lock(8 + BL808_FLASH_XIP_BASE, buf, sizeof(SPI_Flash_Cfg_Type) + 8, group, bank); - SF_Ctrl_Set_Flash_Image_Offset(xipOffset, group, bank); - - if (ARCH_MemCmp(buf, BFLB_FLASH_CFG_MAGIC, 4) == 0) { - crc = BFLB_Soft_CRC32((uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type)); - pCrc = (uint32_t *)(buf + 4 + sizeof(SPI_Flash_Cfg_Type)); - - if (*pCrc == crc) { - ARCH_MemCpy_Fast(pFlashCfg, (uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type)); - return SUCCESS; - } - } - } else { - for (i = 0; i < sizeof(flashInfos) / sizeof(flashInfos[0]); i++) { - if (flashInfos[i].jedecID == flashID) { - ARCH_MemCpy_Fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type)); - return SUCCESS; - } - } - } - - return ERROR; -} -#endif - -/****************************************************************************/ /** - * @brief Get flash config according to flash ID patch - * - * @param flashID: Flash ID - * @param pFlashCfg: Flash config pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg, - uint8_t group, SF_Ctrl_Bank_Select bank) -{ - return SF_Cfg_Get_Flash_Cfg_Need_Lock(flashID, pFlashCfg, group, bank); -} -#endif - -/****************************************************************************/ /** - * @brief Init flash GPIO according to flash Pin config - * - * @param flashPinCfg: Specify flash Pin config - * @param restoreDefault: Wether to restore default setting - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Init_Flash_Gpio(SF_Ctrl_Pin_Select flashPinCfg, uint8_t restoreDefault) -{ - uint8_t selEmbedded = 0; - uint8_t swap = 0; - - if ((flashPinCfg&(1<<3)) > 0) { - return ERROR; - } - - if (restoreDefault) { - /* Set Default first */ - GLB_Set_Flash_IO_PARM(1, 1); - SF_Ctrl_Select_Pad(SF_IO_EMB_SWAP_IO0_IO3); - - /* Default is set, so return */ - if (flashPinCfg == SF_IO_EMB_SWAP_IO0_IO3) { - return SUCCESS; - } - } - - if (flashPinCfg & (1 << 2)) { - /* Init sf2 gpio */ - SF_Cfg_Init_Ext_Flash_Gpio(0); - selEmbedded = 0; - } else { - selEmbedded = 1; - } - /* if pin select dual flash, embedded is default */ - if ((flashPinCfg & (1 << 4))) { - selEmbedded = 1; - } - - swap = ((flashPinCfg >> 1) & 1); - swap = (!swap); - GLB_Set_Flash_IO_PARM(selEmbedded, swap); - SF_Ctrl_Select_Pad(flashPinCfg); - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Identify one flash - * - * @param callFromFlash: code run at flash or ram - * @param flashPinCfg: Bit 7: autoscan, Bit6-0: flash GPIO config - * @param restoreDefault: Wether restore default flash GPIO config - * @param pFlashCfg: Flash config pointer - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return Flash ID - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -uint32_t ATTR_TCM_SECTION SF_Cfg_Flash_Identify(uint8_t callFromFlash, uint8_t flashPinCfg, - uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank) -{ - uint8_t autoScan = 0; - uint8_t flashPin = 0; - uint32_t jdecId = 0; - uint32_t i = 0; - uint32_t offset; - BL_Err_Type stat; - - autoScan = ((flashPinCfg >> 7) & 1); - flashPin = (flashPinCfg & 0x7F); - - ARCH_MemCpy_Fast(pFlashCfg, &flashCfg_Winb_16JV, sizeof(SPI_Flash_Cfg_Type)); - - if (callFromFlash == 1) { - stat = XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank); - - if (stat != SUCCESS) { - SF_Ctrl_Set_Owner(SF_CTRL_OWNER_IAHB); - return 0; - } - } - - if (autoScan) { - flashPin = 0; - - do { - if (flashPin > SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2) { - jdecId = 0; - break; - } - - if (!IS_SF_CTRL_PIN_SELECT(flashPin) || (flashPin&(1<<3)) > 0) { - flashPin++; - continue; - } - - SF_Cfg_Init_Flash_Gpio(flashPin, restoreDefault); - SFlash_Release_Powerdown(pFlashCfg); - SFlash_Reset_Continue_Read(pFlashCfg); - SFlash_DisableBurstWrap(pFlashCfg); - jdecId = 0; - SFlash_GetJedecId(pFlashCfg, (uint8_t *)&jdecId); - SFlash_DisableBurstWrap(pFlashCfg); - jdecId = jdecId & 0xffffff; - flashPin++; - } while ((jdecId & 0x00ffff) == 0 || (jdecId & 0xffff00) == 0 || (jdecId & 0x00ffff) == 0xffff || (jdecId & 0xffff00) == 0xffff00); - } else { - /* select media gpio */ - SF_Cfg_Init_Flash_Gpio(flashPin, restoreDefault); - SFlash_Release_Powerdown(pFlashCfg); - SFlash_Reset_Continue_Read(pFlashCfg); - SFlash_DisableBurstWrap(pFlashCfg); - SFlash_GetJedecId(pFlashCfg, (uint8_t *)&jdecId); - SFlash_DisableBurstWrap(pFlashCfg); - jdecId = jdecId & 0xffffff; - } - - for (i = 0; i < sizeof(flashInfos) / sizeof(flashInfos[0]); i++) { - if (flashInfos[i].jedecID == jdecId) { - ARCH_MemCpy_Fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type)); - break; - } - } - - if (i == sizeof(flashInfos) / sizeof(flashInfos[0])) { - if (callFromFlash == 1) { - XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank); - } - - return jdecId; - } else { - if (callFromFlash == 1) { - XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank); - } - - return (jdecId | BFLB_FLASH_ID_VALID_FLAG); - } -} -#endif - -/****************************************************************************/ /** - * @brief Identify one flash patch - * - * @param callFromFlash: code run at flash or ram - * @param flashPinCfg: Bit 7: autoscan, Bit6-0: flash GPIO config - * @param restoreDefault: Wether restore default flash GPIO config - * @param pFlashCfg: Flash config pointer - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return Flash ID - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -uint32_t ATTR_TCM_SECTION SF_Cfg_Flash_Identify_Ext(uint8_t callFromFlash, uint8_t flashPinCfg, - uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank) -{ - return SF_Cfg_Flash_Identify(callFromFlash, flashPinCfg, restoreDefault, pFlashCfg, group, bank); -} -#endif - -/****************************************************************************/ /** - * @brief SF Cfg flash init - * - * @param sel: SF pin select - * @param pSfCtrlCfg: Serial flash controller configuration pointer - * @param pBank2Cfg: Serial flash2 controller configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Flash_Init(SF_Ctrl_Pin_Select sel, const SF_Ctrl_Cfg_Type *pSfCtrlCfg, const SF_Ctrl_Bank2_Cfg *pBank2Cfg) -{ - uint8_t selEmbedded = 0; - uint8_t swap = 0; - - if ((sel&(1<<3)) > 0) { - return ERROR; - } - - if (sel & (1 << 2)) { - SF_Cfg_Init_Ext_Flash_Gpio(0); - selEmbedded = 0; - } else { - selEmbedded = 1; - } - /* If pin select dual flash, embedded is default */ - if ((sel & (1 << 4))) { - selEmbedded = 1; - } - - swap = ((sel >> 1) & 1); - swap = (!swap); - GLB_Set_Flash_IO_PARM(selEmbedded, swap); - SF_Ctrl_Select_Pad(sel); - - if (sel <= SF_IO_EMB_SWAP_NONE_DUAL_IO0) { - /* Embedded pad1 io delay set */ - SF_Ctrl_Set_IO_Delay(SF_CTRL_PAD1, pSfCtrlCfg->doDelay, pSfCtrlCfg->diDelay, pSfCtrlCfg->oeDelay); - } else if (sel <= SF_IO_EXT_SF2) { - /* Pad2 or pad3 io delay set */ - SF_Ctrl_Set_IO_Delay((sel >> 2), pSfCtrlCfg->doDelay, pSfCtrlCfg->diDelay, pSfCtrlCfg->oeDelay); - } else if (sel >= SF_IO_EMB_SWAP_IO0_IO3_AND_EXT_SF2 && sel <= SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2) { - /* Dual flash mode, embedded pad1 and pad2 io delay set */ - SF_Ctrl_Set_IO_Delay(SF_CTRL_PAD1, pSfCtrlCfg->doDelay, pSfCtrlCfg->diDelay, pSfCtrlCfg->oeDelay); - SF_Ctrl_Set_IO_Delay(SF_CTRL_PAD2, pBank2Cfg->doDelay, pBank2Cfg->diDelay, pBank2Cfg->oeDelay); - } - - if (pBank2Cfg != NULL) { - if (pBank2Cfg->sbus2Select) { - if (sel >= SF_IO_EMB_SWAP_IO0_IO3_AND_EXT_SF2 && sel <= SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2) { - /* Default sbus2 replace opt flash2 */ - SF_Ctrl_Sbus2_Replace(SF_CTRL_PAD2); - } - } - } - - SFlash_Init(pSfCtrlCfg, pBank2Cfg); - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief SF Cfg system bus 2 flash init - * - * @param sel: SF pin select - * @param pBank2Cfg: Serial flash2 controller configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Sbus2_Flash_Init(SF_Ctrl_Pin_Select sel, const SF_Ctrl_Bank2_Cfg *pBank2Cfg) -{ - if (sel < SF_IO_EMB_SWAP_IO0_IO3_AND_EXT_SF2 || sel > SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2) { - return ERROR; - } - - /* Init flash2 gpio */ - if (sel & (1 << 2)) { - SF_Cfg_Init_Ext_Flash_Gpio(0); - } - - /* Set remap for flash2 xip mode */ - SF_Ctrl_Remap_Set(pBank2Cfg->remap, pBank2Cfg->remapLock); - - /* Dual flash mode, pad2 io delay set */ - SF_Ctrl_Set_IO_Delay(SF_CTRL_PAD2, pBank2Cfg->doDelay, pBank2Cfg->diDelay, pBank2Cfg->oeDelay); - - if (pBank2Cfg->sbus2Select) { - /* Default sbus2 replace opt flash2 */ - SF_Ctrl_Sbus2_Replace(SF_CTRL_PAD2); - } - - SFlash_Init(NULL, pBank2Cfg); - - return SUCCESS; -} -#endif - -/*@} end of group SF_CFG_Public_Functions */ - -/*@} end of group SF_CFG */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sf_cfg_ext.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sf_cfg_ext.c deleted file mode 100644 index 9dd2683e6d..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sf_cfg_ext.c +++ /dev/null @@ -1,295 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_sf_cfg_ext.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "softcrc.h" -#include "bl808_sf_cfg.h" -#include "bl808_sf_cfg_ext.h" -#include "bl808_xip_sflash.h" -#include "bl808_romdriver_e907.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup SF_CFG_EXT - * @{ - */ - -/** @defgroup SF_CFG_EXT_Private_Macros - * @{ - */ -#define BFLB_FLASH_CFG_MAGIC "FCFG" - -/*@} end of group SF_CFG_EXT_Private_Macros */ - -/** @defgroup SF_CFG_EXT_Private_Types - * @{ - */ -typedef struct -{ - uint32_t jedecID; - char *name; - const SPI_Flash_Cfg_Type *cfg; -} Flash_Info_t; - -/*@} end of group SF_CFG_EXT_Private_Types */ - -/** @defgroup SF_CFG_EXT_Private_Variables - * @{ - */ -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_GD_LQ64E = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xc8, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0xa0, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3d, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 500, - .timeE32k = 2000, - .timeE64k = 2000, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 3, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION Flash_Info_t flashInfos[] = { - { - .jedecID = 0x1760c8, - //.name="GD_LQ64E_64_18", - .cfg = &flashCfg_GD_LQ64E, - }, -}; - -/*@} end of group SF_CFG_EXT_Private_Variables */ - -/** @defgroup SF_CFG_EXT_Global_Variables - * @{ - */ - -/*@} end of group SF_CFG_EXT_Global_Variables */ - -/** @defgroup SF_CFG_EXT_Private_Fun_Declaration - * @{ - */ - -/*@} end of group SF_CFG_EXT_Private_Fun_Declaration */ - -/** @defgroup SF_CFG_EXT_Private_Functions - * @{ - */ - - - -/*@} end of group SF_CFG_EXT_Private_Functions */ - -/****************************************************************************/ /** - * @brief Get flash config according to flash ID patch - * - * @param flashID: Flash ID - * @param pFlashCfg: Flash config pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg) -{ - uint32_t i; - uint8_t buf[sizeof(SPI_Flash_Cfg_Type) + 8]; - uint32_t crc, *pCrc; - uint32_t xipOffset; - char flashCfgMagic[] = "FCFG"; - - if (flashID == 0) { - xipOffset = SF_Ctrl_Get_Flash_Image_Offset(0, SF_CTRL_FLASH_BANK0); - SF_Ctrl_Set_Flash_Image_Offset(0, 0, SF_CTRL_FLASH_BANK0); - XIP_SFlash_Read_Via_Cache_Need_Lock(8 + BL808_FLASH_XIP_BASE, buf, sizeof(SPI_Flash_Cfg_Type) + 8); - SF_Ctrl_Set_Flash_Image_Offset(xipOffset, 0, SF_CTRL_FLASH_BANK0); - - if (ARCH_MemCmp(buf, flashCfgMagic, 4) == 0) { - crc = BFLB_Soft_CRC32((uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type)); - pCrc = (uint32_t *)(buf + 4 + sizeof(SPI_Flash_Cfg_Type)); - - if (*pCrc == crc) { - ARCH_MemCpy_Fast(pFlashCfg, (uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type)); - return SUCCESS; - } - } - } else { - if(SF_Cfg_Get_Flash_Cfg_Need_Lock(flashID, pFlashCfg) == SUCCESS){ - return SUCCESS; - } - for (i = 0; i < sizeof(flashInfos) / sizeof(flashInfos[0]); i++) { - if (flashInfos[i].jedecID == flashID) { - ARCH_MemCpy_Fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type)); - return SUCCESS; - } - } - } - - return ERROR; -} - - -/****************************************************************************/ /** - * @brief Identify one flash patch - * - * @param callFromFlash: code run at flash or ram - * @param flashPinCfg: Bit 7: autoscan, Bit6-0: flash GPIO config - * @param restoreDefault: Wether restore default flash GPIO config - * @param pFlashCfg: Flash config pointer - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return Flash ID - * -*******************************************************************************/ -uint32_t ATTR_TCM_SECTION SF_Cfg_Flash_Identify_Ext(uint8_t callFromFlash, uint8_t flashPinCfg, - uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank) -{ - uint32_t jdecId = 0; - uint32_t i = 0; - uint32_t ret = 0; - - ret = SF_Cfg_Flash_Identify(callFromFlash, flashPinCfg, restoreDefault, pFlashCfg, group, bank); - if(callFromFlash){ - SFlash_Set_IDbus_Cfg(pFlashCfg, pFlashCfg->ioMode&0xf , 1, 0, 32, bank); - } - if((ret&BFLB_FLASH_ID_VALID_FLAG) != 0){ - return ret; - } - - jdecId = (ret&0xffffff); - for(i=0; i
© COPYRIGHT(c) 2020 Bouffalo Lab
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_sf_ctrl.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup SF_CTRL - * @{ - */ - -/** @defgroup SF_CTRL_Private_Macros - * @{ - */ - -/*@} end of group SF_CTRL_Private_Macros */ - -/** @defgroup SF_CTRL_Private_Types - * @{ - */ - -/*@} end of group SF_CTRL_Private_Types */ - -/** @defgroup SF_CTRL_Private_Variables - * @{ - */ -#define SF_CTRL_BUSY_STATE_TIMEOUT (5 * 320 * 1000) -#define SF_Ctrl_Get_AES_Region(addr, r) (addr + SF_CTRL_AES_REGION_OFFSET + (r)*0x80) - -/*@} end of group SF_CTRL_Private_Variables */ - -/** @defgroup SF_CTRL_Global_Variables - * @{ - */ - -/*@} end of group SF_CTRL_Global_Variables */ - -/** @defgroup SF_CTRL_Private_Fun_Declaration - * @{ - */ - -/*@} end of group SF_CTRL_Private_Fun_Declaration */ - -/** @defgroup SF_CTRL_Private_Functions - * @{ - */ - -/*@} end of group SF_CTRL_Private_Functions */ - -/** @defgroup SF_CTRL_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Enable serail flash controller - * - * @param cfg: serial flash controller config - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Enable(const SF_Ctrl_Cfg_Type *cfg) -{ - uint32_t tmpVal = 0; - uint32_t timeOut = 0; - - if (cfg == NULL) { - return; - } - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_OWNER_TYPE(cfg->owner)); - - timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); - - if (cfg->en32bAddr) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_32B_ADR_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_32B_ADR_EN); - } - - if (cfg->clkDelay > 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_N, cfg->clkDelay - 1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN); - } - - /* Serail out inverted, so sf ctrl send on negative edge */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CLK_OUT_INV_SEL, cfg->clkInvert); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CLK_SF_RX_INV_SEL, cfg->rxClkInvert); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal); - - /* Enable AHB access sram buffer and enable sf interface */ - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SRAM_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_EN); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_1, tmpVal); - - SF_Ctrl_Set_Owner(cfg->owner); -} -#endif - -/****************************************************************************/ /** - * @brief Enable serail bank2 controller - * - * @param bank2Cfg: serial bank2 controller config - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Bank2_Enable(const SF_Ctrl_Bank2_Cfg *bank2Cfg) -{ - uint32_t tmpVal = 0; - - if (bank2Cfg == NULL) { - return; - } - - /* Select if1 bank2 clock delay */ - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_12); - - if (bank2Cfg->bank2RxClkInvertSrc) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF2_CLK_SF_RX_INV_SRC); - - if (bank2Cfg->bank2RxClkInvertSel) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF2_CLK_SF_RX_INV_SEL); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF2_CLK_SF_RX_INV_SEL); - } - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF2_CLK_SF_RX_INV_SRC); - } - - if (bank2Cfg->bank2DelaySrc) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF2_IF_READ_DLY_SRC); - - if (bank2Cfg->bank2ClkDelay > 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF2_IF_READ_DLY_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IF_READ_DLY_N, bank2Cfg->bank2ClkDelay - 1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF2_IF_READ_DLY_EN); - } - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF2_IF_READ_DLY_SRC); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_12, tmpVal); - - /* Select sbus2 clock delay */ - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_0); - - if (bank2Cfg->bank2RxClkInvertSel) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_CLK_SF_IF2_RX_INV_SEL); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_CLK_SF_IF2_RX_INV_SEL); - } - - if (bank2Cfg->bank2ClkDelay > 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF2_READ_DLY_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF2_READ_DLY_N, bank2Cfg->bank2ClkDelay - 1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_READ_DLY_EN); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_0, tmpVal); - - /* Dual flash mode, enable bank2, select pad1 and pad2 */ - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_2); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_MODE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_PAD_SEL, 0); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_2, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief SF Ctrl set io delay - * - * @param pad: Pad select - * @param doDelay: DO delay select - * @param diDelay: DI delay select - * @param oeDelay: OE delay select - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Set_IO_Delay(SF_Ctrl_Pad_Type pad, uint8_t doDelay, uint8_t diDelay, uint8_t oeDelay) -{ - uint32_t tmpVal = 0; - uint32_t offset = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_PAD_TYPE(pad)); - - if (pad == SF_CTRL_PAD1) { - offset = SF_CTRL_BASE + SF_CTRL_IF_IO_DLY_1_OFFSET; - } else if (pad == SF_CTRL_PAD2) { - offset = SF_CTRL_BASE + SF_CTRL_IF_IO_DLY_2_OFFSET; - } else { - offset = SF_CTRL_BASE + SF_CTRL_IF_IO_DLY_3_OFFSET; - } - - /* Set do di and oe delay */ - tmpVal = BL_RD_REG(offset, SF_CTRL_IO_DLY_1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_0_DO_DLY_SEL, doDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_0_DI_DLY_SEL, diDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_0_OE_DLY_SEL, oeDelay); - BL_WR_REG(offset, SF_CTRL_IO_DLY_1, tmpVal); - - tmpVal = BL_RD_REG(offset, SF_CTRL_IO_DLY_2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_1_DO_DLY_SEL, doDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_1_DI_DLY_SEL, diDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_1_OE_DLY_SEL, oeDelay); - BL_WR_REG(offset, SF_CTRL_IO_DLY_2, tmpVal); - - tmpVal = BL_RD_REG(offset, SF_CTRL_IO_DLY_3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_2_DO_DLY_SEL, doDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_2_DI_DLY_SEL, diDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_2_OE_DLY_SEL, oeDelay); - BL_WR_REG(offset, SF_CTRL_IO_DLY_3, tmpVal); - - tmpVal = BL_RD_REG(offset, SF_CTRL_IO_DLY_4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_3_DO_DLY_SEL, doDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_3_DI_DLY_SEL, diDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_3_OE_DLY_SEL, oeDelay); - BL_WR_REG(offset, SF_CTRL_IO_DLY_4, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Flash controller sbus2 hold sram - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Sbus2_Hold_Sram(void) -{ - uint32_t tmpVal; - - /* Sbus2 hold sram */ - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_1); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF2_FN_SEL); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_1, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Flash controller sbus2 release sram - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Sbus2_Release_Sram(void) -{ - uint32_t tmpVal; - - /* Sbus2 release sram */ - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_1); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_FN_SEL); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_1, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Get flash controller sbus2 status - * - * @param None - * - * @return Wether if2 is enable - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Sts_Type ATTR_TCM_SECTION SF_Ctrl_Is_Sbus2_Enable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_1); - - if (BL_IS_REG_BIT_SET(tmpVal, SF_CTRL_SF_IF2_EN)) { - if (BL_IS_REG_BIT_SET(tmpVal, SF_CTRL_SF_IF2_FN_SEL)) { - return SET; - } else { - return RESET; - } - } - - return RESET; -} -#endif - -/****************************************************************************/ /** - * @brief SF Ctrl set sbus2 repalce - * - * @param pad: SF pad to replace - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Sbus2_Replace(SF_Ctrl_Pad_Type pad) -{ - uint32_t tmpVal = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_PAD_TYPE(pad)); - - /* Sbus2 enable */ - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_1); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF2_EN); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_1, tmpVal); - - SF_Ctrl_Sbus2_Hold_Sram(); - - /* Sbus2 repalce pad */ - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_0); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_REPLACE_SF1); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_REPLACE_SF2); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_REPLACE_SF3); - - if (pad == SF_CTRL_PAD1) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF2_REPLACE_SF1); - } else if (pad == SF_CTRL_PAD2) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF2_REPLACE_SF2); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF2_REPLACE_SF3); - } - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF2_PAD_SEL, pad); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief SF Ctrl sbus2 revoke replace - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Sbus2_Revoke_replace(void) -{ - uint32_t tmpVal = 0; - - SF_Ctrl_Sbus2_Release_Sram(); - - /* Sbus2 clear repalce pad */ - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_0); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_REPLACE_SF1); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_REPLACE_SF2); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_REPLACE_SF3); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_0, tmpVal); - - /* Sbus2 disable */ - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_1); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_EN); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_1, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief SF Ctrl set sbus2 clock delay - * - * @param clkDelay: Sbus2 clock delay - * @param rxClkInvert: Sbus2 rx clock invert - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Sbus2_Set_Delay(uint8_t clkDelay, uint8_t rxClkInvert) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_0); - - if (clkDelay > 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF2_READ_DLY_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF2_READ_DLY_N, clkDelay - 1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_READ_DLY_EN); - } - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CLK_SF_IF2_RX_INV_SEL, rxClkInvert); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Get flash controller clock delay value - * - * @param en32BitsAddr: Serial flash enable or disable 32-bits addr - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_32bits_Addr_En(BL_Fun_Type en32BitsAddr) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); - - if (en32BitsAddr) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_32B_ADR_EN); - - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_32B_ADR_EN); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Get flash controller clock delay value - * - * @param None - * - * @return Clock delay value - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -uint8_t ATTR_TCM_SECTION SF_Ctrl_Get_Clock_Delay(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); - - if (BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN) == 0) { - return 0; - } else { - return BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_N) + 1; - } -} -#endif - -/****************************************************************************/ /** - * @brief Set flash controller clock delay value - * - * @param delay: Clock delay value - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Set_Clock_Delay(uint8_t delay) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); - - if (delay > 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_N, delay - 1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief SF Ctrl get wrap queue value - * - * @param None - * - * @return Wrap queue value - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -uint8_t ATTR_TCM_SECTION SF_Ctrl_Get_Wrap_Queue_Value(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_3); - - return BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CMDS_2_WRAP_Q); -} -#endif - -/****************************************************************************/ /** - * @brief SF Ctrl set cmds config - * - * @param cmdsCfg: SF Ctrl cmds config - * @param bank: bank select type - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Cmds_Set(SF_Ctrl_Cmds_Cfg *cmdsCfg, SF_Ctrl_Bank_Select bank) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_WRAP_MODE(cmdsCfg->cmdsWrapMode)); - CHECK_PARAM(IS_SF_CTRL_WRAP_LEN_TYPE(cmdsCfg->cmdsWrapLen)); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_3); - - if (cmdsCfg->ackLatency) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_1_ACK_LAT); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_1_ACK_LAT); - } - - if (cmdsCfg->cmdsCoreEn) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_CORE_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_CORE_EN); - } - - if (bank == SF_CTRL_FLASH_BANK1) { - if (cmdsCfg->cmdsEn) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_2_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_2_EN); - } - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CMDS_2_WRAP_MODE, cmdsCfg->cmdsWrapMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CMDS_2_WRAP_LEN, cmdsCfg->cmdsWrapLen); - } else { - if (cmdsCfg->cmdsEn) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_1_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_1_EN); - } - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CMDS_1_WRAP_MODE, cmdsCfg->cmdsWrapMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CMDS_1_WRAP_LEN, cmdsCfg->cmdsWrapLen); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_3, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief SF Ctrl pad select - * - * @param sel: Pin select type - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Select_Pad(SF_Ctrl_Pin_Select sel) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_PIN_SELECT(sel)); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_2); - - if (sel <= SF_IO_EXT_SF2) { - /* Single flash mode, disable bank2 */ - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_EN); - - if (sel <= SF_IO_EMB_SWAP_NONE_DUAL_IO0) { - /* Select embedded pad1 */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_PAD_SEL, 0); - } else { - /* Select pad2 or pad3 */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_PAD_SEL, ((sel&0xf) >> 2)); - } - } else if (sel >= SF_IO_EMB_SWAP_IO0_IO3_AND_EXT_SF2 && sel <= SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2) { - /* Dual flash mode, enable bank2, select pad1 and pad2 */ - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_MODE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_PAD_SEL, 0); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_2, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief SF Ctrl dual flash memory remap set - * - * @param remap: Memory remap set type - * @param lock: Memory remap lock - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Remap_Set(SF_Ctrl_Remap_Type remap, uint8_t lock) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_REMAP_TYPE(remap)); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AHB2SIF_REMAP, remap); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_2, tmpVal); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_2); - - if (lock) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SIF_REMAP_LOCK); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SIF_REMAP_LOCK); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_2, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief SF Ctrl select bank on system bus - * - * @param bank: bank select type - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Sbus_Select_Bank(SF_Ctrl_Bank_Select bank) -{ - /* TODO: sf_if_bk_swap */ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_BANK_SELECT(bank)); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_2); - - if (bank == SF_CTRL_FLASH_BANK0) { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_BK_SEL); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_BK_SEL); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_2, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Set flash controller owner:I/D AHB or system AHB - * - * @param owner: owner type - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Set_Owner(SF_Ctrl_Owner_Type owner) -{ - uint32_t tmpVal = 0; - uint32_t timeOut = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_OWNER_TYPE(owner)); - - timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); - - /* Set owner */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_FN_SEL, owner); - - /* Set iahb to flash interface */ - if (owner == SF_CTRL_OWNER_IAHB) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SIF_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SIF_EN); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_1, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Disable flash controller - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Disable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); - - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_EN); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_1, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Enable flash controller AES with big indian - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Enable_BE(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); - - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_KEY_ENDIAN); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_IV_ENDIAN); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_DIN_ENDIAN); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_DOUT_ENDIAN); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Enable flash controller AES with little indian - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Enable_LE(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); - - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_KEY_ENDIAN); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_IV_ENDIAN); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_DIN_ENDIAN); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_DOUT_ENDIAN); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Serial flash controller set AES region - * - * @param region: region number - * @param enable: enable or not - * @param hwKey: hardware key or software key - * @param startAddr: region start address - * @param endAddr: region end address - * @param locked: lock this region or not - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Region(uint8_t region, uint8_t enable, - uint8_t hwKey, uint32_t startAddr, uint32_t endAddr, uint8_t locked) -{ - /* Do flash key eco */ - uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); - uint32_t tmpVal; - - if (!hwKey) { - regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); - } - - tmpVal = BL_RD_REG(regionRegBase, SF_CTRL_SF_AES_END); - /* sf_aes_end =1 means 1,11,1111,1111 */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_END, endAddr / 1024); - BL_WR_REG(regionRegBase, SF_CTRL_SF_AES_END, tmpVal); - - tmpVal = BL_RD_REG(regionRegBase, SF_CTRL_SF_AES_START); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_HW_KEY_EN, hwKey); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_START, startAddr / 1024); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_EN, enable); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_LOCK, locked); - BL_WR_REG(regionRegBase, SF_CTRL_SF_AES_START, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Serial flash controller set AES key - * - * @param region: region number - * @param key: key data pointer - * @param keyType: flash controller AES key type:128 bits,192 bits or 256 bits - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType) -{ - /* Do flash key eco*/ - uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); - uint32_t tmpVal, i = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_AES_KEY_TYPE(keyType)); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_MODE, keyType); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal); - - if (NULL != key) { - if (keyType == SF_CTRL_AES_128BITS) { - i = 4; - /* - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_7,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_6,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - */ - } else if (keyType == SF_CTRL_AES_256BITS) { - i = 8; - /* - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_7,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_6,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_1,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_0,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - */ - } else if (keyType == SF_CTRL_AES_192BITS) { - i = 6; - /* - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_7,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_6,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - */ - } - - tmpVal = SF_CTRL_SF_AES_KEY_7_OFFSET; - - while (i--) { - BL_WR_WORD(regionRegBase + tmpVal, __REV(BL_RDWD_FRM_BYTEP(key))); - key += 4; - tmpVal -= 4; - } - } -} -#endif - -/****************************************************************************/ /** - * @brief Serial flash controller set AES XTS mode key - * - * @param region: region number - * @param key: key data pointer - * @param keyType: flash controller AES key type:128 bits,192 bits or 256 bits - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_XTS_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType) -{ - /* Do flash key eco */ - uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); - uint32_t tmpVal, i = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_AES_KEY_TYPE(keyType)); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_MODE, keyType); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal); - - if (NULL != key) { - i = 8; - tmpVal = SF_CTRL_SF_AES_KEY_7_OFFSET; - - while (i--) { - BL_WR_WORD(regionRegBase + tmpVal, __REV(BL_RDWD_FRM_BYTEP(key))); - key += 4; - tmpVal -= 4; - } - } -} -#endif - -/****************************************************************************/ /** - * @brief Serial flash controller set AES key with big endian - * - * @param region: region number - * @param key: key data pointer - * @param keyType: flash controller AES key type:128 bits,192 bits or 256 bits - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType) -{ - /* Do flash key eco*/ - uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); - uint32_t tmpVal, i = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_AES_KEY_TYPE(keyType)); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_MODE, keyType); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal); - - if (NULL != key) { - if (keyType == SF_CTRL_AES_128BITS) { - i = 4; - /* - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_0,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_1,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,BL_RDWD_FRM_BYTEP(key)); - key+=4; - */ - } else if (keyType == SF_CTRL_AES_256BITS) { - i = 8; - /* - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_0,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_1,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_6,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_7,BL_RDWD_FRM_BYTEP(key)); - key+=4; - */ - } else if (keyType == SF_CTRL_AES_192BITS) { - i = 6; - /* - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_0,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_1,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,BL_RDWD_FRM_BYTEP(key)); - */ - } - - tmpVal = SF_CTRL_SF_AES_KEY_0_OFFSET; - - while (i--) { - BL_WR_WORD(regionRegBase + tmpVal, BL_RDWD_FRM_BYTEP(key)); - key += 4; - tmpVal += 4; - } - } -} -#endif - -/****************************************************************************/ /** - * @brief Serial flash controller set AES XTS mode key with big endian - * - * @param region: region number - * @param key: key data pointer - * @param keyType: flash controller AES key type:128 bits,192 bits or 256 bits - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_XTS_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType) -{ - /* Do flash key eco*/ - uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); - uint32_t tmpVal, i = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_AES_KEY_TYPE(keyType)); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_MODE, keyType); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal); - - if (NULL != key) { - i = 8; - tmpVal = SF_CTRL_SF_AES_KEY_0_OFFSET; - - while (i--) { - BL_WR_WORD(regionRegBase + tmpVal, BL_RDWD_FRM_BYTEP(key)); - key += 4; - tmpVal += 4; - } - } -} -#endif - -/****************************************************************************/ /** - * @brief Serial flash controller set AES iv - * - * @param region: region number - * @param iv: iv data pointer - * @param addrOffset: flash address offset - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset) -{ - /* Do flash key eco*/ - uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); - uint32_t tmpVal, i = 3; - - if (iv != NULL) { - tmpVal = SF_CTRL_SF_AES_IV_W3_OFFSET; - - while (i--) { - BL_WR_WORD(regionRegBase + tmpVal, __REV(BL_RDWD_FRM_BYTEP(iv))); - iv += 4; - tmpVal -= 4; - } - - /* - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W3,__REV(BL_RDWD_FRM_BYTEP(iv))); - iv+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W2,__REV(BL_RDWD_FRM_BYTEP(iv))); - iv+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W1,__REV(BL_RDWD_FRM_BYTEP(iv))); - iv+=4; - */ - BL_WR_REG(regionRegBase, SF_CTRL_SF_AES_IV_W0, addrOffset); - iv += 4; - } -} -#endif - -/****************************************************************************/ /** - * @brief Serial flash controller set AES XTS iv - * - * @param region: region number - * @param iv: iv data pointer - * @param addrOffset: flash address offset - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_XTS_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset) -{ - /* Do flash key eco*/ - uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); - uint32_t tmpVal, i = 3; - - if (iv != NULL) { - tmpVal = SF_CTRL_SF_AES_IV_W1_OFFSET; - - while (i--) { - iv += 4; - BL_WR_WORD(regionRegBase + tmpVal, (BL_RDWD_FRM_BYTEP(iv))); - tmpVal += 4; - } - - BL_WR_REG(regionRegBase, SF_CTRL_SF_AES_IV_W0, addrOffset); - iv += 4; - } -} -#endif - -/****************************************************************************/ /** - * @brief Serial flash controller set AES iv with big endian - * - * @param region: region number - * @param iv: iv data pointer - * @param addrOffset: flash address offset - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset) -{ - /* Do flash key eco*/ - uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); - uint32_t tmpVal, i = 3; - - if (iv != NULL) { - tmpVal = SF_CTRL_SF_AES_IV_W0_OFFSET; - - while (i--) { - BL_WR_WORD(regionRegBase + tmpVal, BL_RDWD_FRM_BYTEP(iv)); - iv += 4; - tmpVal += 4; - } - - /* - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W0,BL_RDWD_FRM_BYTEP(iv)); - iv+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W1,BL_RDWD_FRM_BYTEP(iv)); - iv+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W2,BL_RDWD_FRM_BYTEP(iv)); - iv+=4; - */ - BL_WR_REG(regionRegBase, SF_CTRL_SF_AES_IV_W3, __REV(addrOffset)); - iv += 4; - } -} -#endif - -/****************************************************************************/ /** - * @brief Serial flash controller set AES XTS iv with big endian - * - * @param region: region number - * @param iv: iv data pointer - * @param addrOffset: flash address offset - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_XTS_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset) -{ - /* Do flash key eco*/ - uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); - uint32_t tmpVal, i = 3; - - if (iv != NULL) { - tmpVal = SF_CTRL_SF_AES_IV_W2_OFFSET; - - while (i--) { - iv += 4; - BL_WR_WORD(regionRegBase + tmpVal, __REV(BL_RDWD_FRM_BYTEP(iv))); - tmpVal -= 4; - } - - BL_WR_REG(regionRegBase, SF_CTRL_SF_AES_IV_W3, __REV(addrOffset)); - iv += 4; - } -} -#endif -#ifndef BFLB_USE_ROM_DRIVER - -/****************************************************************************/ /** - * @brief Set serial flash controller AES mode - * - * @param mode: AES mode select - * - * @return None - * -*******************************************************************************/ -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Mode(SF_Ctrl_AES_Mode_Type mode) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_AES_MODE_TYPE(mode)); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); - - if (mode == SF_CTRL_AES_CTR_MODE) { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_BLK_MODE); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_BLK_MODE); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Enable serial flash controller AES - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Enable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_EN); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Disable serial flash controller AES - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Disable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_EN); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Check is serial flash controller AES enable - * - * @param None - * - * @return Wether AES is enable - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Sts_Type ATTR_TCM_SECTION SF_Ctrl_Is_AES_Enable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); - - if (BL_IS_REG_BIT_SET(tmpVal, SF_CTRL_SF_AES_EN)) { - return SET; - } - - return RESET; -} -#endif - -/****************************************************************************/ /** - * @brief Set flash image offset - * - * @param addrOffset: Address offset value - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Set_Flash_Image_Offset(uint32_t addrOffset, uint8_t group, SF_Ctrl_Bank_Select bank) -{ - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_BANK_SELECT(bank)); - - if (group) { - if (bank == SF_CTRL_FLASH_BANK0) { - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_ID1_OFFSET, addrOffset); - } else { - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_BK2_ID1_OFFSET, addrOffset); - } - } else { - if (bank == SF_CTRL_FLASH_BANK0) { - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_ID0_OFFSET, addrOffset); - } else { - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_BK2_ID0_OFFSET, addrOffset); - } - } -} -#endif - -/****************************************************************************/ /** - * @brief Get flash image offset - * - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return :Address offset value - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -uint32_t ATTR_TCM_SECTION SF_Ctrl_Get_Flash_Image_Offset(uint8_t group, SF_Ctrl_Bank_Select bank) -{ - uint32_t tmpVal = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_BANK_SELECT(bank)); - - if (group) { - if (bank == SF_CTRL_FLASH_BANK0) { - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_ID1_OFFSET); - } else { - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_BK2_ID1_OFFSET); - } - } else { - if (bank == SF_CTRL_FLASH_BANK0) { - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_ID0_OFFSET); - } else { - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_BK2_ID0_OFFSET); - } - } - - return tmpVal; -} -#endif - -/****************************************************************************/ /** - * @brief Lock/unlock sf_id0/sf_id1/sf_bk2_id0/sf_bk2_id1 offset - * - * @param lock: lock or unlock - * - * @return :None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Lock_Flash_Image_Offset(uint8_t lock) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_2); - if (lock) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_ID_OFFSET_LOCK); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_ID_OFFSET_LOCK); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_2, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief SF controller send one command - * - * @param cfg: Serial flash controller command configuration pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_SendCmd(SF_Ctrl_Cmd_Cfg_Type *cfg) -{ - uint32_t tmpVal = 0; - uint32_t timeOut = 0; - uint32_t cmdOffset = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_CMD_MODE_TYPE(cfg->cmdMode)); - CHECK_PARAM(IS_SF_CTRL_ADDR_MODE_TYPE(cfg->addrMode)); - CHECK_PARAM(IS_SF_CTRL_DMY_MODE_TYPE(cfg->dummyMode)); - CHECK_PARAM(IS_SF_CTRL_DATA_MODE_TYPE(cfg->dataMode)); - - timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - if (SF_Ctrl_Is_Sbus2_Enable() == RESET) { - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); - - if (BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_FN_SEL) != SF_CTRL_OWNER_SAHB) { - return; - } - - cmdOffset = SF_CTRL_BASE + SF_CTRL_IF1_SAHB_OFFSET; - } else { - cmdOffset = SF_CTRL_BASE + SF_CTRL_IF2_SAHB_OFFSET; - } - - /* Clear trigger */ - tmpVal = BL_RD_REG(cmdOffset, SF_CTRL_IF_SAHB_0); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_IF_0_TRIG); - BL_WR_REG(cmdOffset, SF_CTRL_IF_SAHB_0, tmpVal); - - /* Copy command buffer */ - BL_WR_REG(cmdOffset, SF_CTRL_IF_SAHB_1, cfg->cmdBuf[0]); - BL_WR_REG(cmdOffset, SF_CTRL_IF_SAHB_2, cfg->cmdBuf[1]); - - tmpVal = BL_RD_REG(cmdOffset, SF_CTRL_IF_SAHB_0); - - /* Configure SPI and IO mode*/ - if (SF_CTRL_CMD_1_LINE == cfg->cmdMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_QPI_MODE_EN, SF_CTRL_SPI_MODE); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_QPI_MODE_EN, SF_CTRL_QPI_MODE); - } - - if (SF_CTRL_ADDR_1_LINE == cfg->addrMode) { - if (SF_CTRL_DATA_1_LINE == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_SPI_MODE, SF_CTRL_NIO_MODE); - } else if (SF_CTRL_DATA_2_LINES == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_SPI_MODE, SF_CTRL_DO_MODE); - } else if (SF_CTRL_DATA_4_LINES == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_SPI_MODE, SF_CTRL_QO_MODE); - } - } else if (SF_CTRL_ADDR_2_LINES == cfg->addrMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_SPI_MODE, SF_CTRL_DIO_MODE); - } else if (SF_CTRL_ADDR_4_LINES == cfg->addrMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_SPI_MODE, SF_CTRL_QIO_MODE); - } - - /* Configure cmd */ - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_IF_0_CMD_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_CMD_BYTE, 0); - - /* Configure address */ - if (cfg->addrSize != 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_IF_0_ADR_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_ADR_BYTE, cfg->addrSize - 1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_IF_0_ADR_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_ADR_BYTE, 0); - } - - /* Configure dummy */ - if (cfg->dummyClks != 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_IF_0_DMY_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_DMY_BYTE, cfg->dummyClks - 1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_IF_0_DMY_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_DMY_BYTE, 0); - } - - /* Configure data */ - if (cfg->nbData != 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_IF_0_DAT_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_DAT_BYTE, cfg->nbData - 1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_IF_0_DAT_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_DAT_BYTE, 0); - } - - /* Set read write flag */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_DAT_RW, cfg->rwFlag); - BL_WR_REG(cmdOffset, SF_CTRL_IF_SAHB_0, tmpVal); - - /* Trigger */ - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_IF_0_TRIG); - BL_WR_REG(cmdOffset, SF_CTRL_IF_SAHB_0, tmpVal); - - timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } -} -#endif - -/****************************************************************************/ /** - * @brief SF Ctrl disable iahb to flash wrap access for XTS mode - * - * @param disable: Disable for 1 and enable for 0 - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Disable_Wrap_Access(uint8_t disable) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); - - if (disable) { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SIF_DISWRAP); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SIF_DISWRAP); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_1, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Config SF controller for flash I/D cache read - * - * @param cfg: Serial flash controller command configuration pointer - * @param cmdValid: command valid or not, for continous read, cache may need no command - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Flash_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid) -{ - uint32_t tmpVal = 0; - uint32_t timeOut = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_CMD_MODE_TYPE(cfg->cmdMode)); - CHECK_PARAM(IS_SF_CTRL_ADDR_MODE_TYPE(cfg->addrMode)); - CHECK_PARAM(IS_SF_CTRL_DMY_MODE_TYPE(cfg->dummyMode)); - CHECK_PARAM(IS_SF_CTRL_DATA_MODE_TYPE(cfg->dataMode)); - - timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); - - if (BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_FN_SEL) != SF_CTRL_OWNER_IAHB) { - return; - } - - /* Copy command buffer */ - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_1, cfg->cmdBuf[0]); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_2, cfg->cmdBuf[1]); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_0); - - /* Configure SPI and IO mode*/ - if (SF_CTRL_CMD_1_LINE == cfg->cmdMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_QPI_MODE_EN, SF_CTRL_SPI_MODE); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_QPI_MODE_EN, SF_CTRL_QPI_MODE); - } - - if (SF_CTRL_ADDR_1_LINE == cfg->addrMode) { - if (SF_CTRL_DATA_1_LINE == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_NIO_MODE); - } else if (SF_CTRL_DATA_2_LINES == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_DO_MODE); - } else if (SF_CTRL_DATA_4_LINES == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_QO_MODE); - } - } else if (SF_CTRL_ADDR_2_LINES == cfg->addrMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_DIO_MODE); - } else if (SF_CTRL_ADDR_4_LINES == cfg->addrMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_QIO_MODE); - } - - if (cmdValid) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_BYTE, 0); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_BYTE, 0); - } - - /* Configure address */ - if (cfg->addrSize != 0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_BYTE, cfg->addrSize - 1); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_BYTE, 0); - } - - /* configure dummy */ - if (cfg->dummyClks != 0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_BYTE, cfg->dummyClks - 1); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_BYTE, 0); - } - - /* Configure data */ - if (cfg->nbData != 0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_EN, 1); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_EN, 0); - } - - /* Set read write flag */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_RW, cfg->rwFlag); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Config bank2 controller for flash2 I/D cache read - * - * @param cfg: Serial flash controller command configuration pointer - * @param cmdValid: command valid or not, for continous read, cache may need no command - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Flash2_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid) -{ - uint32_t tmpVal = 0; - uint32_t timeOut = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_CMD_MODE_TYPE(cfg->cmdMode)); - CHECK_PARAM(IS_SF_CTRL_ADDR_MODE_TYPE(cfg->addrMode)); - CHECK_PARAM(IS_SF_CTRL_DMY_MODE_TYPE(cfg->dummyMode)); - CHECK_PARAM(IS_SF_CTRL_DATA_MODE_TYPE(cfg->dataMode)); - - timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); - - if (BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_FN_SEL) != SF_CTRL_OWNER_IAHB) { - return; - } - - /* Copy command buffer */ - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_10, cfg->cmdBuf[0]); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_11, cfg->cmdBuf[1]); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_9); - - /* Configure SPI and IO mode*/ - if (SF_CTRL_CMD_1_LINE == cfg->cmdMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_QPI_MODE_EN, SF_CTRL_SPI_MODE); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_QPI_MODE_EN, SF_CTRL_QPI_MODE); - } - - if (SF_CTRL_ADDR_1_LINE == cfg->addrMode) { - if (SF_CTRL_DATA_1_LINE == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_NIO_MODE); - } else if (SF_CTRL_DATA_2_LINES == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_DO_MODE); - } else if (SF_CTRL_DATA_4_LINES == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_QO_MODE); - } - } else if (SF_CTRL_ADDR_2_LINES == cfg->addrMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_DIO_MODE); - } else if (SF_CTRL_ADDR_4_LINES == cfg->addrMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_QIO_MODE); - } - - if (cmdValid) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_BYTE, 0); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_BYTE, 0); - } - - /* Configure address */ - if (cfg->addrSize != 0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_BYTE, cfg->addrSize - 1); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_BYTE, 0); - } - - /* configure dummy */ - if (cfg->dummyClks != 0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_BYTE, cfg->dummyClks - 1); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_BYTE, 0); - } - - /* Configure data */ - if (cfg->nbData != 0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_EN, 1); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_EN, 0); - } - - /* Set read write flag */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_RW, cfg->rwFlag); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_9, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Get SF Ctrl busy state - * - * @param None - * - * @return SET for SF ctrl busy or RESET for SF ctrl not busy - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Sts_Type ATTR_TCM_SECTION SF_Ctrl_GetBusyState(void) -{ - uint32_t tmpVal = 0; - uint32_t cmdOffset = 0; - - if (SF_Ctrl_Is_Sbus2_Enable() == RESET) { - cmdOffset = SF_CTRL_BASE + SF_CTRL_IF1_SAHB_OFFSET; - } else { - cmdOffset = SF_CTRL_BASE + SF_CTRL_IF2_SAHB_OFFSET; - } - - tmpVal = BL_RD_REG(cmdOffset, SF_CTRL_IF_SAHB_0); - - if (BL_IS_REG_BIT_SET(tmpVal, SF_CTRL_IF_BUSY)) { - return SET; - } - - return RESET; -} -#endif - -/****************************************************************************/ /** - * @brief SF Controller interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void SF_Ctrl_IRQHandler(void) -{ - /* TODO: Not implemented */ -} -#endif - -/*@} end of group SF_CTRL_Public_Functions */ - -/*@} end of group SF_CTRL */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sflash.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sflash.c deleted file mode 100644 index d6dfcb749a..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sflash.c +++ /dev/null @@ -1,2164 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_sflash.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "string.h" -#include "bl808_sflash.h" -#include "bl808_sf_ctrl.h" -#include "bl808_l1c.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup SFLASH - * @{ - */ - -/** @defgroup SFLASH_Private_Macros - * @{ - */ - -/*@} end of group SFLASH_Private_Macros */ - -/** @defgroup SFLASH_Private_Types - * @{ - */ - -/*@} end of group SFLASH_Private_Types */ - -/** @defgroup SFLASH_Private_Variables - * @{ - */ -#define SFCTRL_BUSY_STATE_TIMEOUT (5 * 320 * 1000) - -/*@} end of group SFLASH_Private_Variables */ - -/** @defgroup SFLASH_Global_Variables - * @{ - */ - -/*@} end of group SFLASH_Global_Variables */ - -/** @defgroup SFLASH_Private_Fun_Declaration - * @{ - */ - -/*@} end of group SFLASH_Private_Fun_Declaration */ - -/** @defgroup SFLASH_Private_Functions - * @{ - */ - -/*@} end of group SFLASH_Private_Functions */ - -/** @defgroup SFLASH_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Init serial flash control interface - * - * @param pSfCtrlCfg: Serial flash controller configuration pointer - * @param pBank2Cfg: Serial flash2 controller configuration pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_Init(const SF_Ctrl_Cfg_Type *pSfCtrlCfg, const SF_Ctrl_Bank2_Cfg *pBank2Cfg) -{ - uint8_t clkDelay = 0; - uint8_t rxClkInvert = 0; - - if (pBank2Cfg != NULL) { - if (pBank2Cfg->sbus2Select) { - if (pBank2Cfg->bank2DelaySrc) { - clkDelay = pBank2Cfg->bank2ClkDelay; - } else { - if (pSfCtrlCfg != NULL) { - clkDelay = pSfCtrlCfg->clkDelay; - } else { - clkDelay = 1; - } - } - - if (pBank2Cfg->bank2RxClkInvertSrc) { - rxClkInvert = pBank2Cfg->bank2RxClkInvertSel; - } else { - if (pSfCtrlCfg != NULL) { - rxClkInvert = pSfCtrlCfg->rxClkInvert; - } else { - rxClkInvert = 0; - } - } - - SF_Ctrl_Sbus2_Set_Delay(clkDelay, rxClkInvert); - } else { - SF_Ctrl_Sbus2_Revoke_replace(); - } - - SF_Ctrl_Bank2_Enable(pBank2Cfg); - } else { - SF_Ctrl_Sbus2_Revoke_replace(); - } - - if (pSfCtrlCfg != NULL) { - SF_Ctrl_Enable(pSfCtrlCfg); - } -} -#endif - -/****************************************************************************/ /** - * @brief Set serial flash control interface SPI or QPI mode - * - * @param mode: Serial flash interface mode - * - * @return BFLB_RET:SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_SetSPIMode(SF_Ctrl_Mode_Type mode) -{ - BL_Err_Type stat = SUCCESS; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_MODE_TYPE(mode)); - - return stat; -} -#endif - -/****************************************************************************/ /** - * @brief Read flash register - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param regIndex: register index - * @param regValue: register value pointer to store data - * @param regLen: register value length - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Read_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint32_t cnt = 0; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = (flashCfg->readRegCmd[regIndex]) << 24; - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.nbData = regLen; - - SF_Ctrl_SendCmd(&flashCmd); - - while (SET == SF_Ctrl_GetBusyState()) { - arch_delay_us(1); - cnt++; - - if (cnt > 1000) { - return ERROR; - } - } - - ARCH_MemCpy(regValue, flashCtrlBuf, regLen); - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Write flash register - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param regIndex: register index - * @param regValue: register value pointer storing data - * @param regLen: register value length - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint32_t cnt = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - ARCH_MemCpy(flashCtrlBuf, regValue, regLen); - - flashCmd.cmdBuf[0] = (flashCfg->writeRegCmd[regIndex]) << 24; - flashCmd.rwFlag = SF_CTRL_WRITE; - flashCmd.nbData = regLen; - - SF_Ctrl_SendCmd(&flashCmd); - - /* take 40ms for tw(write status register) as default */ - while (SET == SFlash_Busy(flashCfg)) { - arch_delay_us(100); - cnt++; - - if (cnt > 400) { - return ERROR; - } - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Read flash register with read command - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param readRegCmd: read command - * @param regValue: register value pointer to store data - * @param regLen: register value length - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t readRegCmd, uint8_t *regValue, uint8_t regLen) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint32_t cnt = 0; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = readRegCmd << 24; - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.nbData = regLen; - - SF_Ctrl_SendCmd(&flashCmd); - - while (SET == SF_Ctrl_GetBusyState()) { - arch_delay_us(1); - cnt++; - - if (cnt > 1000) { - return ERROR; - } - } - - ARCH_MemCpy(regValue, flashCtrlBuf, regLen); - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Write flash register with write command - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param writeRegCmd: write command - * @param regValue: register value pointer storing data - * @param regLen: register value length - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue, uint8_t regLen) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint32_t cnt = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - ARCH_MemCpy(flashCtrlBuf, regValue, regLen); - - flashCmd.cmdBuf[0] = writeRegCmd << 24; - flashCmd.rwFlag = SF_CTRL_WRITE; - flashCmd.nbData = regLen; - - SF_Ctrl_SendCmd(&flashCmd); - - /* take 40ms for tw(write status register) as default */ - while (SET == SFlash_Busy(flashCfg)) { - arch_delay_us(100); - cnt++; - - if (cnt > 400) { - return ERROR; - } - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Check flash busy status - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return SET for busy or RESET for not busy - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Sts_Type ATTR_TCM_SECTION SFlash_Busy(SPI_Flash_Cfg_Type *flashCfg) -{ - uint32_t stat = 0; - SFlash_Read_Reg(flashCfg, flashCfg->busyIndex, (uint8_t *)&stat, flashCfg->busyReadRegLen); - - if ((stat & (1 << flashCfg->busyBit)) == 0) { - return RESET; - } - - return SET; -} -#endif - -/****************************************************************************/ /** - * @brief Enable flash write function - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Enable(SPI_Flash_Cfg_Type *flashCfg) -{ - uint32_t stat = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - /* Write enable*/ - flashCmd.cmdBuf[0] = (flashCfg->writeEnableCmd) << 24; - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - SF_Ctrl_SendCmd(&flashCmd); - - SFlash_Read_Reg(flashCfg, flashCfg->wrEnableIndex, (uint8_t *)&stat, flashCfg->wrEnableReadRegLen); - - if ((stat & (1 << flashCfg->wrEnableBit)) != 0) { - return SUCCESS; - } - - return ERROR; -} -#endif - -/****************************************************************************/ /** - * @brief Enable flash flash controller QSPI interface - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Qspi_Enable(SPI_Flash_Cfg_Type *flashCfg) -{ - uint32_t stat = 0, ret; - - if (flashCfg->qeReadRegLen == 0) { - ret = SFlash_Write_Enable(flashCfg); - - if (SUCCESS != ret) { - return ERROR; - } - - SFlash_Write_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeWriteRegLen); - return SUCCESS; - } - - SFlash_Read_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeReadRegLen); - - if (flashCfg->qeData == 0) { - if ((stat & (1 << flashCfg->qeBit)) != 0) { - return SUCCESS; - } - } else { - if (((stat >> (flashCfg->qeBit & 0x08)) & 0xff) == flashCfg->qeData) { - return SUCCESS; - } - } - - if (flashCfg->qeWriteRegLen != 1) { - /* This is read r0,read r1 write r0,r1 case*/ - SFlash_Read_Reg(flashCfg, 0, (uint8_t *)&stat, 1); - SFlash_Read_Reg(flashCfg, 1, ((uint8_t *)&stat) + 1, 1); - - if (flashCfg->qeData == 0) { - stat |= (1 << (flashCfg->qeBit + 8 * flashCfg->qeIndex)); - } else { - stat = stat & (~(0xff << (8 * flashCfg->qeIndex))); - stat |= (flashCfg->qeData << (8 * flashCfg->qeIndex)); - } - } else { - if (flashCfg->qeData == 0) { - stat |= (1 << (flashCfg->qeBit % 8)); - } else { - stat = flashCfg->qeData; - } - } - - ret = SFlash_Write_Enable(flashCfg); - - if (SUCCESS != ret) { - return ERROR; - } - - SFlash_Write_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeWriteRegLen); - SFlash_Read_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeReadRegLen); - - if (flashCfg->qeData == 0) { - if ((stat & (1 << flashCfg->qeBit)) != 0) { - return SUCCESS; - } - } else { - if (((stat >> (flashCfg->qeBit & 0x08)) & 0xff) == flashCfg->qeData) { - return SUCCESS; - } - } - - return ERROR; -} -#endif - -/****************************************************************************/ /** - * @brief Disable flash flash controller QSPI interface - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Qspi_Disable(SPI_Flash_Cfg_Type *flashCfg) -{ - uint32_t stat = 0, ret; - - if (flashCfg->qeReadRegLen == 0) { - ret = SFlash_Write_Enable(flashCfg); - - if (SUCCESS != ret) { - return ERROR; - } - - SFlash_Write_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeWriteRegLen); - return SUCCESS; - } - - SFlash_Read_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeReadRegLen); - - if ((stat & (1 << flashCfg->qeBit)) == 0) { - return SUCCESS; - } - - if (flashCfg->qeWriteRegLen != 1) { - /* This is read r0,read r1 write r0,r1 case*/ - SFlash_Read_Reg(flashCfg, 0, (uint8_t *)&stat, 1); - SFlash_Read_Reg(flashCfg, 1, ((uint8_t *)&stat) + 1, 1); - stat &= (~(1 << (flashCfg->qeBit + 8 * flashCfg->qeIndex))); - } else { - stat &= (~(1 << (flashCfg->qeBit % 8))); - } - - ret = SFlash_Write_Enable(flashCfg); - - if (SUCCESS != ret) { - return ERROR; - } - - SFlash_Write_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeWriteRegLen); - SFlash_Read_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeReadRegLen); - - if ((stat & (1 << flashCfg->qeBit)) == 0) { - return SUCCESS; - } - - return ERROR; -} -#endif - -/****************************************************************************/ /** - * @brief Enable flash volatile register write enable - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_Volatile_Reg_Write_Enable(SPI_Flash_Cfg_Type *flashCfg) -{ - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = (flashCfg->writeVregEnableCmd) << 24; - flashCmd.rwFlag = SF_CTRL_WRITE; - - SF_Ctrl_SendCmd(&flashCmd); -} -#endif - -/****************************************************************************/ /** - * @brief Erase flash whole chip - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Chip_Erase(SPI_Flash_Cfg_Type *flashCfg) -{ - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint32_t cnt = 0; - uint32_t timeout = 0; - BL_Err_Type stat = SFlash_Write_Enable(flashCfg); - - if (stat != SUCCESS) { - return stat; - } - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = (flashCfg->chipEraseCmd) << 24; - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - - SF_Ctrl_SendCmd(&flashCmd); - - timeout = flashCfg->timeCe; - - if ((timeout >> 15) > 0) { - timeout = (timeout & 0x7FFF) * 1000; - } - - while (SET == SFlash_Busy(flashCfg)) { - arch_delay_us(500); - cnt++; - - if (cnt > timeout * 3) { - return ERROR; - } - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Erase flash one sector - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param secNum: flash sector number - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Sector_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t secNum) -{ - uint32_t cnt = 0; - uint8_t is32BitsAddr = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - BL_Err_Type stat = SFlash_Write_Enable(flashCfg); - - if (stat != SUCCESS) { - return stat; - } - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - is32BitsAddr = (flashCfg->ioMode & 0x20); - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = 3; - - if (is32BitsAddr > 0) { - flashCmd.addrSize++; - flashCmd.cmdBuf[0] = (flashCfg->sectorEraseCmd << 24) | ((flashCfg->sectorSize * 1024 * secNum) >> 8); - flashCmd.cmdBuf[1] = ((flashCfg->sectorSize * 1024 * secNum) << 24); - } else { - flashCmd.cmdBuf[0] = (flashCfg->sectorEraseCmd << 24) | (flashCfg->sectorSize * 1024 * secNum); - } - - SF_Ctrl_SendCmd(&flashCmd); - - while (SET == SFlash_Busy(flashCfg)) { - arch_delay_us(500); - cnt++; - - if (cnt > flashCfg->timeEsector * 3) { - return ERROR; - } - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Erase flash one 32K block - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param blkNum: flash 32K block number - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Blk32_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum) -{ - uint32_t cnt = 0; - uint8_t is32BitsAddr = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - BL_Err_Type stat = SFlash_Write_Enable(flashCfg); - - if (stat != SUCCESS) { - return stat; - } - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - is32BitsAddr = (flashCfg->ioMode & 0x20); - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = 3; - - if (is32BitsAddr > 0) { - flashCmd.addrSize++; - flashCmd.cmdBuf[0] = (flashCfg->blk32EraseCmd << 24) | ((BFLB_SPIFLASH_BLK32K_SIZE * blkNum) >> 8); - flashCmd.cmdBuf[1] = ((BFLB_SPIFLASH_BLK32K_SIZE * blkNum) << 24); - } else { - flashCmd.cmdBuf[0] = (flashCfg->blk32EraseCmd << 24) | (BFLB_SPIFLASH_BLK32K_SIZE * blkNum); - } - - SF_Ctrl_SendCmd(&flashCmd); - - while (SET == SFlash_Busy(flashCfg)) { - arch_delay_us(500); - cnt++; - - if (cnt > flashCfg->timeE32k * 3) { - return ERROR; - } - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Erase flash one 64K block - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param blkNum: flash 64K block number - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Blk64_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum) -{ - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint32_t cnt = 0; - uint8_t is32BitsAddr = 0; - BL_Err_Type stat = SFlash_Write_Enable(flashCfg); - - if (stat != SUCCESS) { - return stat; - } - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - is32BitsAddr = (flashCfg->ioMode & 0x20); - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = 3; - - if (is32BitsAddr > 0) { - flashCmd.addrSize++; - flashCmd.cmdBuf[0] = (flashCfg->blk64EraseCmd << 24) | ((BFLB_SPIFLASH_BLK64K_SIZE * blkNum) >> 8); - flashCmd.cmdBuf[1] = ((BFLB_SPIFLASH_BLK64K_SIZE * blkNum) << 24); - } else { - flashCmd.cmdBuf[0] = (flashCfg->blk64EraseCmd << 24) | (BFLB_SPIFLASH_BLK64K_SIZE * blkNum); - } - - SF_Ctrl_SendCmd(&flashCmd); - - while (SET == SFlash_Busy(flashCfg)) { - arch_delay_us(500); - cnt++; - - if (cnt > flashCfg->timeE64k * 3) { - return ERROR; - } - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Erase flash one region - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param startaddr: start address to erase - * @param endaddr: end address(include this address) to erase - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t startaddr, uint32_t endaddr) -{ - uint32_t len = 0; - uint32_t eraseLen = 0; - BL_Err_Type ret = SUCCESS; - - if (startaddr > endaddr) { - return ERROR; - } - - while (startaddr <= endaddr) { - len = endaddr - startaddr + 1; - - if (flashCfg->blk64EraseCmd != BFLB_SPIFLASH_CMD_INVALID && - (startaddr & (BFLB_SPIFLASH_BLK64K_SIZE - 1)) == 0 && - len > (BFLB_SPIFLASH_BLK64K_SIZE - flashCfg->sectorSize * 1024)) { - /* 64K margin address,and length > 64K-sector size, erase one first */ - ret = SFlash_Blk64_Erase(flashCfg, startaddr / BFLB_SPIFLASH_BLK64K_SIZE); - eraseLen = BFLB_SPIFLASH_BLK64K_SIZE; - } else if (flashCfg->blk32EraseCmd != BFLB_SPIFLASH_CMD_INVALID && - (startaddr & (BFLB_SPIFLASH_BLK32K_SIZE - 1)) == 0 && - len > (BFLB_SPIFLASH_BLK32K_SIZE - flashCfg->sectorSize * 1024)) { - /* 32K margin address,and length > 32K-sector size, erase one first */ - ret = SFlash_Blk32_Erase(flashCfg, startaddr / BFLB_SPIFLASH_BLK32K_SIZE); - eraseLen = BFLB_SPIFLASH_BLK32K_SIZE; - } else { - /* Sector erase */ - startaddr = ((startaddr) & (~(flashCfg->sectorSize * 1024 - 1))); - ret = SFlash_Sector_Erase(flashCfg, startaddr / flashCfg->sectorSize / 1024); - eraseLen = flashCfg->sectorSize * 1024; - } - - startaddr += eraseLen; - - if (ret != SUCCESS) { - return ERROR; - } - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Get flash unique ID - * - * @param data: data pointer to store read data - * @param idLen: unique ID len - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_GetUniqueId(uint8_t *data, uint8_t idLen) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint8_t cmd, dummyClks; - uint32_t timeOut = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - dummyClks = 4; - cmd = 0x4B; - flashCmd.cmdBuf[0] = (cmd << 24); - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.dummyClks = dummyClks; - flashCmd.nbData = idLen; - - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - ARCH_MemCpy(data, flashCtrlBuf, idLen); -} -#endif - -/****************************************************************************/ /** - * @brief Get flash jedec ID - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param data: data pointer to store read data - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_GetJedecId(SPI_Flash_Cfg_Type *flashCfg, uint8_t *data) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint8_t cmd, dummyClks; - uint32_t timeOut = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - dummyClks = flashCfg->jedecIdCmdDmyClk; - cmd = flashCfg->jedecIdCmd; - flashCmd.cmdBuf[0] = (cmd << 24); - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.dummyClks = dummyClks; - flashCmd.nbData = 3; - - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - ARCH_MemCpy(data, flashCtrlBuf, 3); -} -#endif - -/****************************************************************************/ /** - * @brief Get flash device ID - * - * @param data: data pointer to store read data - * @param is32BitsAddr: Is flash addr mode in 32-bits - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_GetDeviceId(uint8_t *data, BL_Fun_Type is32BitsAddr) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint8_t cmd, dummyClks; - uint32_t timeOut = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint32_t addr = 0x00000001; - uint8_t readMode = 0xFF; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.addrMode = SF_CTRL_ADDR_4_LINES; - flashCmd.dataMode = SF_CTRL_DATA_4_LINES; - dummyClks = 2; - cmd = 0x94; - flashCmd.addrSize = 4; - - if (is32BitsAddr) { - flashCmd.cmdBuf[0] = (cmd << 24) | (addr >> 8); - flashCmd.cmdBuf[1] = (addr << 24) | (readMode << 16); - flashCmd.addrSize++; - } else { - flashCmd.cmdBuf[0] = (cmd << 24) | (addr); - flashCmd.cmdBuf[1] = (readMode << 24); - } - - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.dummyClks = dummyClks; - flashCmd.nbData = 2; - - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - ARCH_MemCpy(data, flashCtrlBuf, 2); -} -#endif - -/****************************************************************************/ /** - * @brief Set flash power down - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_Powerdown(void) -{ - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint8_t cmd = 0; - uint32_t timeOut = 0; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - cmd = 0xB9; - flashCmd.cmdBuf[0] = (cmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } -} -#endif - -/****************************************************************************/ /** - * @brief Release flash power down for wake up - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_Release_Powerdown(SPI_Flash_Cfg_Type *flashCfg) -{ - uint8_t cmd; - uint32_t timeOut = 0; - - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - cmd = flashCfg->releasePowerDown; - flashCmd.cmdBuf[0] = (cmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } -} -#endif - -/****************************************************************************/ /** - * @brief Sflash restore from power down - * - * @param pFlashCfg: Flash configuration pointer - * @param flashContRead: Whether enable continuous read - * @param bank: bank select type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Restore_From_Powerdown(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t flashContRead, - SF_Ctrl_Bank_Select bank) -{ - BL_Err_Type stat = SUCCESS; - uint32_t jdecId = 0; - uint8_t tmp[8]; - uint8_t ioMode = pFlashCfg->ioMode & 0xf; - - /* Wake flash up from power down */ - SFlash_Release_Powerdown(pFlashCfg); - arch_delay_us(120); - - SFlash_GetJedecId(pFlashCfg, (uint8_t *)&jdecId); - - if (SF_CTRL_QO_MODE == ioMode || SF_CTRL_QIO_MODE == ioMode) { - SFlash_Qspi_Enable(pFlashCfg); - } - - if (((pFlashCfg->ioMode >> 4) & 0x01) == 1) { - /* unwrap */ - L1C_Set_Wrap(DISABLE); - } else { - /* burst wrap */ - L1C_Set_Wrap(ENABLE); - /* For command that is setting register instead of send command, we need write enable */ - SFlash_Write_Enable(pFlashCfg); - SFlash_SetBurstWrap(pFlashCfg); - } - - if (flashContRead) { - stat = SFlash_Read(pFlashCfg, ioMode, 1, 0x00000000, (uint8_t *)tmp, sizeof(tmp)); - stat = SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank); - } else { - stat = SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 0, 0, 32, bank); - } - - return stat; -} -#endif - -/****************************************************************************/ /** - * @brief Set flash burst wrap config - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_SetBurstWrap(SPI_Flash_Cfg_Type *flashCfg) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint8_t cmd, dummyClks; - uint32_t wrapData; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((flashCfg->ioMode >> 4) & 0x01) == 1) { - /* Disable burst wrap ,just return */ - return; - } - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.addrMode = (SF_Ctrl_Addr_Mode_Type)flashCfg->burstWrapDataMode; - flashCmd.dataMode = (SF_Ctrl_Data_Mode_Type)flashCfg->burstWrapDataMode; - dummyClks = flashCfg->burstWrapCmdDmyClk; - cmd = flashCfg->burstWrapCmd; - wrapData = flashCfg->burstWrapData; - ARCH_MemCpy4((uint32_t *)flashCtrlBuf, &wrapData, 4); - flashCmd.cmdBuf[0] = (cmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - flashCmd.dummyClks = dummyClks; - flashCmd.nbData = 1; - - SF_Ctrl_SendCmd(&flashCmd); -} -#endif - -/****************************************************************************/ /** - * @brief Disable flash burst wrap config - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_DisableBurstWrap(SPI_Flash_Cfg_Type *flashCfg) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint8_t cmd, dummyClks; - uint32_t wrapData; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.addrMode = (SF_Ctrl_Addr_Mode_Type)flashCfg->deBurstWrapDataMode; - flashCmd.dataMode = (SF_Ctrl_Data_Mode_Type)flashCfg->deBurstWrapDataMode; - dummyClks = flashCfg->deBurstWrapCmdDmyClk; - cmd = flashCfg->deBurstWrapCmd; - wrapData = flashCfg->deBurstWrapData; - ARCH_MemCpy4((uint32_t *)flashCtrlBuf, &wrapData, 4); - flashCmd.cmdBuf[0] = (cmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - flashCmd.dummyClks = dummyClks; - flashCmd.nbData = 1; - - SF_Ctrl_SendCmd(&flashCmd); -} -#endif - -/****************************************************************************/ /** - * @brief Set flash 24-bits or 32-bits addr mode - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param en32BitsAddr: Serial flash enable or disable 32-bits addr - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Set32BitsAddrMode(SPI_Flash_Cfg_Type *flashCfg, BL_Fun_Type en32BitsAddr) -{ - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint8_t cmd = 0; - - if ((flashCfg->ioMode & 0x20) == 0) { - return ERROR; - } - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - SF_Ctrl_32bits_Addr_En(en32BitsAddr); - - if (en32BitsAddr) { - cmd = flashCfg->enter32BitsAddrCmd; - } else { - cmd = flashCfg->exit32BitsAddrCmd; - } - - flashCmd.cmdBuf[0] = (cmd << 24); - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - - SF_Ctrl_SendCmd(&flashCmd); - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Software reset flash - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Software_Reset(SPI_Flash_Cfg_Type *flashCfg) -{ - uint16_t cnt = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - /* Reset enable */ - flashCmd.cmdBuf[0] = (flashCfg->resetEnCmd) << 24; - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - - /* Wait for write done */ - while (SET == SFlash_Busy(flashCfg)) { - arch_delay_us(100); - cnt++; - - if (cnt > 20) { - return ERROR; - } - } - - SF_Ctrl_SendCmd(&flashCmd); - - /* Reset */ - flashCmd.cmdBuf[0] = (flashCfg->resetCmd) << 24; - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - SF_Ctrl_SendCmd(&flashCmd); - - arch_delay_us(50); - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Reset flash continous read mode - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_Reset_Continue_Read(SPI_Flash_Cfg_Type *flashCfg) -{ - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - /* Reset continous read */ - ARCH_MemSet(&flashCmd.cmdBuf[0], flashCfg->resetCreadCmd, 4); - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = flashCfg->resetCreadCmdSize; - SF_Ctrl_SendCmd(&flashCmd); -} -#endif - -/****************************************************************************/ /** - * @brief Set I/D bus read flash configuration in flash controller - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param ioMode: flash controller interface mode - * @param contRead: Wether enable cont read mode - * @param addr: address to read/write - * @param len: data length to read/write - * @param bank: bank select type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Set_IDbus_Cfg(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, - uint32_t addr, uint32_t len, SF_Ctrl_Bank_Select bank) -{ - uint8_t cmd, dummyClks; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint8_t cmdValid = 1; - uint8_t noReadModeCfg = 0; - uint8_t cReadSupport = 0; - uint8_t is32BitsAddr = 0; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - SF_Ctrl_Set_Owner(SF_CTRL_OWNER_IAHB); - - if (SF_CTRL_NIO_MODE == ioMode) { - cmd = flashCfg->fastReadCmd; - dummyClks = flashCfg->frDmyClk; - } else if (SF_CTRL_DO_MODE == ioMode) { - flashCmd.dataMode = SF_CTRL_DATA_2_LINES; - cmd = flashCfg->fastReadDoCmd; - dummyClks = flashCfg->frDoDmyClk; - } else if (SF_CTRL_DIO_MODE == ioMode) { - flashCmd.addrMode = SF_CTRL_ADDR_2_LINES; - flashCmd.dataMode = SF_CTRL_DATA_2_LINES; - cmd = flashCfg->fastReadDioCmd; - dummyClks = flashCfg->frDioDmyClk; - } else if (SF_CTRL_QO_MODE == ioMode) { - flashCmd.dataMode = SF_CTRL_DATA_4_LINES; - cmd = flashCfg->fastReadQoCmd; - dummyClks = flashCfg->frQoDmyClk; - } else if (SF_CTRL_QIO_MODE == ioMode) { - flashCmd.addrMode = SF_CTRL_ADDR_4_LINES; - flashCmd.dataMode = SF_CTRL_DATA_4_LINES; - cmd = flashCfg->fastReadQioCmd; - dummyClks = flashCfg->frQioDmyClk; - } else { - return ERROR; - } - - is32BitsAddr = (flashCfg->ioMode & 0x20); - /*prepare command**/ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = 3; - - if (is32BitsAddr > 0) { - flashCmd.addrSize++; - flashCmd.cmdBuf[0] = (cmd << 24) | (addr >> 8); - flashCmd.cmdBuf[1] = (addr << 24); - } else { - flashCmd.cmdBuf[0] = (cmd << 24) | addr; - } - - if (SF_CTRL_QIO_MODE == ioMode || SF_CTRL_DIO_MODE == ioMode) { - noReadModeCfg = flashCfg->cReadSupport & 0x02; - cReadSupport = flashCfg->cReadSupport & 0x01; - - if (noReadModeCfg == 0) { - /* Read mode must be set*/ - if (cReadSupport == 0) { - /* Not support cont read,but we still need set read mode(winbond 80dv)*/ - if (is32BitsAddr > 0) { - flashCmd.cmdBuf[1] |= (flashCfg->cReadMode << 16); - } else { - flashCmd.cmdBuf[1] = (flashCfg->cReadMode << 24); - } - } else { - /* Flash support cont read, setting depend on user parameter */ - if (contRead) { - if (is32BitsAddr > 0) { - flashCmd.cmdBuf[0] = addr; - flashCmd.cmdBuf[1] = (flashCfg->cReadMode << 24); - } else { - flashCmd.cmdBuf[0] = (addr << 8) | flashCfg->cReadMode; - } - - cmdValid = 0; - } else { - if (is32BitsAddr > 0) { - flashCmd.cmdBuf[1] |= ((!flashCfg->cReadMode) << 16); - } else { - flashCmd.cmdBuf[1] = ((!flashCfg->cReadMode) << 24); - } - } - } - - flashCmd.addrSize++; - } - } - - flashCmd.dummyClks = dummyClks; - flashCmd.nbData = len; - if (bank == SF_CTRL_FLASH_BANK0) { - SF_Ctrl_Flash_Read_Icache_Set(&flashCmd, cmdValid); - } else { - SF_Ctrl_Flash2_Read_Icache_Set(&flashCmd, cmdValid); - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Enable I/D bus read from flash - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param ioMode: flash controller interface mode - * @param contRead: Wether enable cont read mode - * @param bank: bank select type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_IDbus_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, - uint8_t contRead, SF_Ctrl_Bank_Select bank) -{ - BL_Err_Type stat; - - stat = SFlash_Set_IDbus_Cfg(flashCfg, ioMode, contRead, 0, 32, bank); - - if (SUCCESS != stat) { - return stat; - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Disable read from flash with IDbus - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_IDbus_Read_Disable(void) -{ - //L1C_Cache_Read_Disable(); -} -#endif - -/****************************************************************************/ /** - * @brief Sflash enable RCV mode to recovery for erase while power drop - * - * @param pFlashCfg: Flash configuration pointer - * @param rCmd: Read RCV register cmd - * @param wCmd: Write RCV register cmd - * @param bitPos: RCV register bit pos - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION SFlash_RCV_Enable(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t rCmd, uint8_t wCmd, uint8_t bitPos) -{ - BL_Err_Type stat; - uint32_t cnt = 0; - uint32_t tempVal = 0; - - while (SET == SFlash_Busy(pFlashCfg)) { - arch_delay_us(500); - cnt++; - - if (cnt > 20000 * 3) { - return ERROR; - } - } - - stat = SFlash_Read_Reg_With_Cmd(pFlashCfg, rCmd, (uint8_t *)&tempVal, 1); - - if (SUCCESS != stat) { - stat = ERROR; - } - - if (((tempVal >> bitPos) & 0x01) > 0) { - return SUCCESS; - } - - tempVal |= (uint32_t)(1 << bitPos); - stat = SFlash_Write_Enable(pFlashCfg); - - if (SUCCESS != stat) { - stat = ERROR; - } - - stat = SFlash_Write_Reg_With_Cmd(pFlashCfg, wCmd, (uint8_t *)&tempVal, 1); - - if (SUCCESS != stat) { - return stat; - } - - while (SET == SFlash_Busy(pFlashCfg)) { - arch_delay_us(500); - cnt++; - - if (cnt > 20000 * 3) { - return ERROR; - } - } - - stat = SFlash_Read_Reg_With_Cmd(pFlashCfg, rCmd, (uint8_t *)&tempVal, 1); - - if (SUCCESS != stat) { - stat = ERROR; - } - - if (((tempVal >> bitPos) & 0x01) <= 0) { - return ERROR; - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Erase flash security register one block - * - * @param pFlashCfg: Flash configuration pointer - * @param pSecRegCfg: Security register configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION SFlash_Erase_Security_Register(SPI_Flash_Cfg_Type *pFlashCfg, SFlash_Sec_Reg_Cfg *pSecRegCfg) -{ - uint32_t cnt = 0; - uint8_t cmd = 0; - uint8_t secOptMode = 0; - uint32_t timeOut = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (pSecRegCfg->enterSecOptCmd != 0x00) { - secOptMode = 1; - - if (((uint32_t)(uintptr_t)&flashCmd) % 4 == 0) { - arch_memset4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - arch_memset(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = (pSecRegCfg->enterSecOptCmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return TIMEOUT; - } - } - } - - BL_Err_Type stat = SFlash_Write_Enable(pFlashCfg); - - if (stat != SUCCESS) { - return stat; - } - - if (((uint32_t)(uintptr_t)&flashCmd) % 4 == 0) { - arch_memset4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - arch_memset(&flashCmd, 0, sizeof(flashCmd)); - } - - cmd = pSecRegCfg->eraseCmd; - flashCmd.cmdBuf[0] = (cmd << 24) | (pSecRegCfg->blockNum << 12); - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = 3; - - SF_Ctrl_SendCmd(&flashCmd); - - while (SET == SFlash_Busy(pFlashCfg)) { - arch_delay_us(500); - cnt++; - - if (cnt > pFlashCfg->timeEsector * 3) { - return ERROR; - } - } - - if (secOptMode > 0) { - if (((uint32_t)(uintptr_t)&flashCmd) % 4 == 0) { - arch_memset4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - arch_memset(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = (pSecRegCfg->exitSecOptCmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return TIMEOUT; - } - } - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Program flash security register one block - * - * @param pFlashCfg: Flash configuration pointer - * @param pSecRegCfg: Security register configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION SFlash_Program_Security_Register(SPI_Flash_Cfg_Type *pFlashCfg, SFlash_Sec_Reg_Cfg *pSecRegCfg) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint32_t i = 0, curLen = 0; - uint32_t cnt = 0; - BL_Err_Type stat; - uint8_t cmd; - uint8_t secOptMode = 0; - uint8_t *data = pSecRegCfg->data; - uint32_t addr = pSecRegCfg->addr; - uint32_t len = pSecRegCfg->len; - uint32_t currentAddr = 0; - uint32_t timeOut = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (pSecRegCfg->enterSecOptCmd != 0x00) { - secOptMode = 1; - - if (((uint32_t)(uintptr_t)&flashCmd) % 4 == 0) { - arch_memset4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - arch_memset(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = (pSecRegCfg->enterSecOptCmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return TIMEOUT; - } - } - } - - if (((uint32_t)(uintptr_t)&flashCmd) % 4 == 0) { - arch_memset4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - arch_memset(&flashCmd, 0, sizeof(flashCmd)); - } - - /* Prepare command */ - flashCmd.rwFlag = SF_CTRL_WRITE; - flashCmd.addrSize = 3; - cmd = pSecRegCfg->programCmd; - - for (i = 0; i < len;) { - /* Write enable is needed for every program */ - stat = SFlash_Write_Enable(pFlashCfg); - - if (stat != SUCCESS) { - return stat; - } - - /* Get current programmed length within page size */ - curLen = 256 - addr % 256; - - if (curLen > len - i) { - curLen = len - i; - } - - currentAddr = (pSecRegCfg->blockNum << 12) | addr; - - /* Prepare command */ - arch_memcpy_fast(flashCtrlBuf, data, curLen); - flashCmd.cmdBuf[0] = (cmd << 24) | (currentAddr); - flashCmd.nbData = curLen; - - SF_Ctrl_SendCmd(&flashCmd); - - /* Adjust address and programmed length */ - addr += curLen; - i += curLen; - data += curLen; - - /* Wait for write done */ - cnt = 0; - - while (SET == SFlash_Busy(pFlashCfg)) { - arch_delay_us(100); - cnt++; - - if (cnt > pFlashCfg->timePagePgm * 20) { - return ERROR; - } - } - } - - if (secOptMode > 0) { - if (((uint32_t)(uintptr_t)&flashCmd) % 4 == 0) { - arch_memset4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - arch_memset(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = (pSecRegCfg->exitSecOptCmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return TIMEOUT; - } - } - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Read data from flash security register one block - * - * @param pSecRegCfg: Security register configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION SFlash_Read_Security_Register(SFlash_Sec_Reg_Cfg *pSecRegCfg) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint32_t curLen, i; - uint8_t cmd; - uint8_t secOptMode = 0; - uint8_t *data = pSecRegCfg->data; - uint32_t addr = pSecRegCfg->addr; - uint32_t len = pSecRegCfg->len; - uint32_t currentAddr = 0; - uint32_t timeOut = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (pSecRegCfg->enterSecOptCmd != 0x00) { - secOptMode = 1; - - if (((uint32_t)(uintptr_t)&flashCmd) % 4 == 0) { - arch_memset4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - arch_memset(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = (pSecRegCfg->enterSecOptCmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return TIMEOUT; - } - } - } - - if (((uint32_t)(uintptr_t)&flashCmd) % 4 == 0) { - arch_memset4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - arch_memset(&flashCmd, 0, sizeof(flashCmd)); - } - - /* Prepare command */ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = 3; - flashCmd.dummyClks = 1; - cmd = pSecRegCfg->readCmd; - - /* Read data */ - for (i = 0; i < len;) { - currentAddr = (pSecRegCfg->blockNum << 12) | addr; - /* Prepare command */ - flashCmd.cmdBuf[0] = (cmd << 24) | (currentAddr); - curLen = len - i; - - if (curLen >= NOR_FLASH_CTRL_BUF_SIZE) { - curLen = NOR_FLASH_CTRL_BUF_SIZE; - flashCmd.nbData = curLen; - } else { - /* Make sf_ctrl word read */ - flashCmd.nbData = ((curLen + 3) >> 2) << 2; - } - - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return TIMEOUT; - } - } - - arch_memcpy_fast(data, flashCtrlBuf, curLen); - - addr += curLen; - i += curLen; - data += curLen; - } - - if (secOptMode > 0) { - if (((uint32_t)(uintptr_t)&flashCmd) % 4 == 0) { - arch_memset4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - arch_memset(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = (pSecRegCfg->exitSecOptCmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return TIMEOUT; - } - } - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Read data from flash - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param ioMode: flash controller interface mode - * @param contRead: Wether enable cont read mode - * @param addr: flash read start address - * @param data: data pointer to store data read from flash - * @param len: data length to read - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Read(SPI_Flash_Cfg_Type *flashCfg, - SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint8_t *data, uint32_t len) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint32_t curLen, i; - uint8_t cmd, dummyClks; - uint32_t timeOut = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint8_t noReadModeCfg = 0; - uint8_t cReadSupport = 0; - uint8_t is32BitsAddr = 0; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - if (SF_CTRL_NIO_MODE == ioMode) { - cmd = flashCfg->fastReadCmd; - dummyClks = flashCfg->frDmyClk; - } else if (SF_CTRL_DO_MODE == ioMode) { - flashCmd.dataMode = SF_CTRL_DATA_2_LINES; - cmd = flashCfg->fastReadDoCmd; - dummyClks = flashCfg->frDoDmyClk; - } else if (SF_CTRL_DIO_MODE == ioMode) { - flashCmd.addrMode = SF_CTRL_ADDR_2_LINES; - flashCmd.dataMode = SF_CTRL_DATA_2_LINES; - cmd = flashCfg->fastReadDioCmd; - dummyClks = flashCfg->frDioDmyClk; - } else if (SF_CTRL_QO_MODE == ioMode) { - flashCmd.dataMode = SF_CTRL_DATA_4_LINES; - cmd = flashCfg->fastReadQoCmd; - dummyClks = flashCfg->frQoDmyClk; - } else if (SF_CTRL_QIO_MODE == ioMode) { - flashCmd.addrMode = SF_CTRL_ADDR_4_LINES; - flashCmd.dataMode = SF_CTRL_DATA_4_LINES; - cmd = flashCfg->fastReadQioCmd; - dummyClks = flashCfg->frQioDmyClk; - } else { - return ERROR; - } - - is32BitsAddr = (flashCfg->ioMode & 0x20); - /* Prepare command */ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = 3; - - if (is32BitsAddr > 0) { - flashCmd.addrSize++; - } - - if (SF_CTRL_QIO_MODE == ioMode || SF_CTRL_DIO_MODE == ioMode) { - noReadModeCfg = flashCfg->cReadSupport & 0x02; - cReadSupport = flashCfg->cReadSupport & 0x01; - - if (noReadModeCfg == 0) { - /* Read mode must be set*/ - if (cReadSupport == 0) { - /* Not support cont read,but we still need set read mode(winbond 80dv)*/ - if (is32BitsAddr > 0) { - flashCmd.cmdBuf[1] |= (flashCfg->cReadMode << 16); - } else { - flashCmd.cmdBuf[1] = (flashCfg->cReadMode << 24); - } - } else { - /* Flash support cont read, setting depend on user parameter */ - if (contRead) { - if (is32BitsAddr > 0) { - flashCmd.cmdBuf[1] |= (flashCfg->cReadMode << 16); - } else { - flashCmd.cmdBuf[1] = (flashCfg->cReadMode << 24); - } - } else { - if (is32BitsAddr > 0) { - flashCmd.cmdBuf[1] |= ((!flashCfg->cReadMode) << 16); - } else { - flashCmd.cmdBuf[1] = ((!flashCfg->cReadMode) << 24); - } - } - } - - flashCmd.addrSize++; - } - } - - flashCmd.dummyClks = dummyClks; - - /* Read data */ - for (i = 0; i < len;) { - /* Prepare command */ - if (is32BitsAddr > 0) { - flashCmd.cmdBuf[0] = (cmd << 24) | (addr >> 8); - flashCmd.cmdBuf[1] |= (addr << 24); - } else { - flashCmd.cmdBuf[0] = (cmd << 24) | (addr); - } - - curLen = len - i; - - if (curLen >= NOR_FLASH_CTRL_BUF_SIZE) { - curLen = NOR_FLASH_CTRL_BUF_SIZE; - flashCmd.nbData = curLen; - } else { - /* Make sf_ctrl word read */ - flashCmd.nbData = ((curLen + 3) >> 2) << 2; - } - - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return TIMEOUT; - } - } - - ARCH_MemCpy_Fast(data, flashCtrlBuf, curLen); - - addr += curLen; - i += curLen; - data += curLen; - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Program flash one region - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param ioMode: progran mode:SPI mode or QPI mode - * @param addr: start address to be programed - * @param data: data pointer to be programed - * @param len: data length to be programed - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Program(SPI_Flash_Cfg_Type *flashCfg, - SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint32_t i = 0, curLen = 0; - uint32_t cnt = 0; - uint8_t is32BitsAddr = 0; - BL_Err_Type stat; - uint8_t cmd; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - if (SF_CTRL_NIO_MODE == ioMode || SF_CTRL_DO_MODE == ioMode || SF_CTRL_DIO_MODE == ioMode) { - cmd = flashCfg->pageProgramCmd; - } else if (SF_CTRL_QIO_MODE == ioMode || SF_CTRL_QO_MODE == ioMode) { - flashCmd.addrMode = (SF_Ctrl_Addr_Mode_Type)flashCfg->qppAddrMode; - flashCmd.dataMode = SF_CTRL_DATA_4_LINES; - cmd = flashCfg->qpageProgramCmd; - } else { - return ERROR; - } - - is32BitsAddr = (flashCfg->ioMode & 0x20); - /* Prepare command */ - flashCmd.rwFlag = SF_CTRL_WRITE; - flashCmd.addrSize = 3; - - if (is32BitsAddr > 0) { - flashCmd.addrSize++; - } - - for (i = 0; i < len;) { - /* Write enable is needed for every program */ - stat = SFlash_Write_Enable(flashCfg); - - if (stat != SUCCESS) { - return stat; - } - - /* Get current programmed length within page size */ - curLen = flashCfg->pageSize - addr % flashCfg->pageSize; - - if (curLen > len - i) { - curLen = len - i; - } - - /* Prepare command */ - ARCH_MemCpy_Fast(flashCtrlBuf, data, curLen); - - if (is32BitsAddr > 0) { - flashCmd.cmdBuf[0] = (cmd << 24) | (addr >> 8); - flashCmd.cmdBuf[1] = (addr << 24); - } else { - flashCmd.cmdBuf[0] = (cmd << 24) | (addr); - } - - flashCmd.nbData = curLen; - - SF_Ctrl_SendCmd(&flashCmd); - - /* Adjust address and programmed length */ - addr += curLen; - i += curLen; - data += curLen; - - /* Wait for write done */ - cnt = 0; - - while (SET == SFlash_Busy(flashCfg)) { - arch_delay_us(100); - cnt++; - - if (cnt > flashCfg->timePagePgm * 20) { - return ERROR; - } - } - } - - return SUCCESS; -} -#endif - -/*@} end of group SFLASH_Public_Functions */ - -/*@} end of group SFLASH */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_spi.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_spi.c deleted file mode 100644 index 4776ac4c74..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_spi.c +++ /dev/null @@ -1,1373 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_spi.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_spi.h" -#include "bl808_glb.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup SPI - * @{ - */ - -/** @defgroup SPI_Private_Macros - * @{ - */ -#define SPI_TX_TIMEOUT_COUNT (320 * 1000) -#define SPI_RX_TIMEOUT_COUNT (320 * 1000) - -/*@} end of group SPI_Private_Macros */ - -/** @defgroup SPI_Private_Types - * @{ - */ - -/*@} end of group SPI_Private_Types */ - -/** @defgroup SPI_Private_Variables - * @{ - */ -const uint32_t spiAddr[SPI_ID_MAX] = { SPI0_BASE, SPI1_BASE }; -#ifndef BFLB_USE_HAL_DRIVER -static intCallback_Type *spiIntCbfArra[SPI_ID_MAX][SPI_INT_ALL] = { - { NULL } -}; -#endif - -/*@} end of group SPI_Private_Variables */ - -/** @defgroup SPI_Global_Variables - * @{ - */ - -/*@} end of group SPI_Global_Variables */ - -/** @defgroup SPI_Private_Fun_Declaration - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -static void SPI_IntHandler(SPI_ID_Type spiNo); -#endif - -/*@} end of group SPI_Private_Fun_Declaration */ - -/** @defgroup SPI_Private_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief SPI interrupt common handler function - * - * @param spiNo: SPI ID type - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -static void SPI_IntHandler(SPI_ID_Type spiNo) -{ - uint32_t tmpVal; - uint32_t SPIx = spiAddr[spiNo]; - - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - - tmpVal = BL_RD_REG(SPIx, SPI_INT_STS); - - /* Transfer end interrupt,shared by both master and slave mode */ - if (BL_IS_REG_BIT_SET(tmpVal, SPI_END_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_END_MASK)) { - BL_WR_REG(SPIx, SPI_INT_STS, BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_END_CLR)); - - if (spiIntCbfArra[spiNo][SPI_INT_END] != NULL) { - spiIntCbfArra[spiNo][SPI_INT_END](); - } - } - - /* TX fifo ready interrupt(fifo count > fifo threshold) */ - if (BL_IS_REG_BIT_SET(tmpVal, SPI_TXF_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_TXF_MASK)) { - if (spiIntCbfArra[spiNo][SPI_INT_TX_FIFO_REQ] != NULL) { - spiIntCbfArra[spiNo][SPI_INT_TX_FIFO_REQ](); - } - } - - /* RX fifo ready interrupt(fifo count > fifo threshold) */ - if (BL_IS_REG_BIT_SET(tmpVal, SPI_RXF_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_RXF_MASK)) { - if (spiIntCbfArra[spiNo][SPI_INT_RX_FIFO_REQ] != NULL) { - spiIntCbfArra[spiNo][SPI_INT_RX_FIFO_REQ](); - } - } - - /* Slave mode transfer time-out interrupt,triggered when bus is idle for the given value */ - if (BL_IS_REG_BIT_SET(tmpVal, SPI_STO_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_STO_MASK)) { - BL_WR_REG(SPIx, SPI_INT_STS, BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_STO_CLR)); - - if (spiIntCbfArra[spiNo][SPI_INT_SLAVE_TIMEOUT] != NULL) { - spiIntCbfArra[spiNo][SPI_INT_SLAVE_TIMEOUT](); - } - } - - /* Slave mode tx underrun error interrupt,trigged when tx is not ready during transfer */ - if (BL_IS_REG_BIT_SET(tmpVal, SPI_TXU_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_TXU_MASK)) { - BL_WR_REG(SPIx, SPI_INT_STS, BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_TXU_CLR)); - - if (spiIntCbfArra[spiNo][SPI_INT_SLAVE_UNDERRUN] != NULL) { - spiIntCbfArra[spiNo][SPI_INT_SLAVE_UNDERRUN](); - } - } - - /* TX/RX fifo overflow/underflow interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, SPI_FER_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_FER_MASK)) { - if (spiIntCbfArra[spiNo][SPI_INT_FIFO_ERROR] != NULL) { - spiIntCbfArra[spiNo][SPI_INT_FIFO_ERROR](); - } - } -} -#endif - -/*@} end of group SPI_Private_Functions */ - -/** @defgroup SPI_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief SPI initialization function - * - * @param spiNo: SPI ID type - * @param spiCfg: SPI configuration structure pointer - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type SPI_Init(SPI_ID_Type spiNo, SPI_CFG_Type *spiCfg) -{ - uint32_t tmpVal; - uint32_t SPIx = spiAddr[spiNo]; - - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - CHECK_PARAM(IS_SPI_SLAVE_PIN_TYPE(slavePin)); - CHECK_PARAM(IS_SPI_WORK_MODE_TYPE(spiCfg->mod)); - CHECK_PARAM(IS_SPI_BYTE_INVERSE_TYPE(spiCfg->byteSequence)); - CHECK_PARAM(IS_SPI_BIT_INVERSE_TYPE(spiCfg->bitSequence)); - CHECK_PARAM(IS_SPI_CLK_PHASE_INVERSE_TYPE(spiCfg->clkPhaseInv)); - CHECK_PARAM(IS_SPI_CLK_POLARITY_TYPE(spiCfg->clkPolarity)); - - /* Disable clock gate when use SPI0 */ - if (SPI0_ID == spiNo) { - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_SPI); - } - - /* spi config */ - tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_DEG_EN, spiCfg->deglitchEnable); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_S_3PIN_MODE, spiCfg->slavePin); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_M_CONT_EN, spiCfg->continuousEnable); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_BYTE_INV, spiCfg->byteSequence); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_BIT_INV, spiCfg->bitSequence); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_SCLK_PH, (spiCfg->clkPhaseInv + 1) & 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_SCLK_POL, spiCfg->clkPolarity); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, spiCfg->frameSize); - BL_WR_REG(SPIx, SPI_CONFIG, tmpVal); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(SPI0_IRQn, SPI0_IRQHandler); - Interrupt_Handler_Register(SPI1_IRQn, SPI1_IRQHandler); -#endif - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief SPI set default value of all registers function - * - * @param spiNo: SPI ID type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type SPI_DeInit(SPI_ID_Type spiNo) -{ - /* Check the parameters */ - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - - if (SPI0_ID == spiNo) { - GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_SPI); - } else if (SPI0_MM_ID == spiNo) { - GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_SPI); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Length of data phase1/0,start/stop condition and interval between frame initialization - * function - * - * @param spiNo: SPI ID type - * @param clockCfg: Clock configuration structure pointer - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type SPI_ClockConfig(SPI_ID_Type spiNo, SPI_ClockCfg_Type *clockCfg) -{ - uint32_t tmpVal; - uint32_t SPIx = spiAddr[spiNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - - /* Configure length of data phase1/0 and start/stop condition */ - tmpVal = BL_RD_REG(SPIx, SPI_PRD_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_S, clockCfg->startLen - 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_P, clockCfg->stopLen - 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_D_PH_0, clockCfg->dataPhase0Len - 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_D_PH_1, clockCfg->dataPhase1Len - 1); - BL_WR_REG(SPIx, SPI_PRD_0, tmpVal); - - /* Configure length of interval between frame */ - tmpVal = BL_RD_REG(SPIx, SPI_PRD_1); - BL_WR_REG(SPIx, SPI_PRD_1, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_I, clockCfg->intervalLen - 1)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief SPI configure fifo function - * - * @param spiNo: SPI ID type - * @param fifoCfg: FIFO configuration structure pointer - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type SPI_FifoConfig(SPI_ID_Type spiNo, SPI_FifoCfg_Type *fifoCfg) -{ - uint32_t tmpVal; - uint32_t SPIx = spiAddr[spiNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - - /* Set fifo threshold value */ - tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_TX_FIFO_TH, fifoCfg->txFifoThreshold); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_RX_FIFO_TH, fifoCfg->rxFifoThreshold); - BL_WR_REG(SPIx, SPI_FIFO_CONFIG_1, tmpVal); - - /* Enable or disable dma function */ - tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_DMA_TX_EN, fifoCfg->txFifoDmaEnable); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_DMA_RX_EN, fifoCfg->rxFifoDmaEnable); - BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Set SPI Frame Size - * - * @param spiNo: SPI ID type - * @param frameSize: FrameSize Type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type SPI_SetFrameSize(SPI_ID_Type spiNo, SPI_FrameSize_Type frameSize) -{ - uint32_t tmpVal; - uint32_t SPIx = spiAddr[spiNo]; - - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - CHECK_PARAM(IS_SPI_SLAVE_PIN_TYPE(frameSize)); - - /* The SPI must be clear fifo first */ - SPI_ClrRxFifo(spiNo); - SPI_ClrTxFifo(spiNo); - - /* set framsize*/ - tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, frameSize); - BL_WR_REG(SPIx, SPI_CONFIG, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Set SPI SCK Clcok - * - * @param spiNo: SPI ID type - * @param clk: Clk - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type SPI_SetClock(SPI_ID_Type spiNo, uint32_t clk) -{ - uint32_t glb_div = 0, spi_div = 0; - uint32_t tmpVal; - uint32_t SPIx = spiAddr[spiNo]; - - if (clk > 80000000) { - clk = 80000000; - } else if (clk < 9766) { - clk = 9766; - } - - if (clk >= 312500) { - glb_div = 0; - spi_div = 80000000 / clk - 1; - } else { - glb_div = 31; - spi_div = 2500000 / clk - 1; - } - - if (spiNo == SPI0_ID) { - GLB_Set_SPI_CLK(ENABLE, GLB_SPI_CLK_MCU_MUXPLL_160M, glb_div); - } else { - GLB_Set_DSP_SPI_CLK(ENABLE, GLB_DSP_SPI_CLK_DSP_MUXPLL_160M, glb_div); - } - - /* Configure length of data phase1/0 and start/stop condition */ - tmpVal = BL_RD_REG(SPIx, SPI_PRD_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_S, spi_div); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_P, spi_div); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_D_PH_0, spi_div); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_D_PH_1, spi_div); - BL_WR_REG(SPIx, SPI_PRD_0, tmpVal); - - tmpVal = BL_RD_REG(SPIx, SPI_PRD_1); - BL_WR_REG(SPIx, SPI_PRD_1, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_I, spi_div)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Enable spi transfer - * - * @param spiNo: SPI ID type - * @param modeType: Master or slave mode select - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type SPI_Enable(SPI_ID_Type spiNo, SPI_WORK_MODE_Type modeType) -{ - uint32_t tmpVal; - uint32_t SPIx = spiAddr[spiNo]; - - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - CHECK_PARAM(IS_SPI_WORK_MODE_TYPE(modeType)); - - tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); - - if (modeType != SPI_WORK_MODE_SLAVE) { - /* master mode */ - tmpVal = BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_S_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_M_EN); - } else { - /* slave mode */ - tmpVal = BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_M_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_S_EN); - } - - BL_WR_REG(SPIx, SPI_CONFIG, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Disable spi transfer - * - * @param spiNo: SPI ID type - * @param modeType: Master or slave mode select - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type SPI_Disable(SPI_ID_Type spiNo, SPI_WORK_MODE_Type modeType) -{ - uint32_t tmpVal; - uint32_t SPIx = spiAddr[spiNo]; - - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - CHECK_PARAM(IS_SPI_WORK_MODE_TYPE(modeType)); - - /* close master and slave */ - tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_M_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_S_EN); - BL_WR_REG(SPIx, SPI_CONFIG, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Set time-out value to trigger interrupt when spi bus is idle for the given value - * - * @param spiNo: SPI ID type - * @param value: Time value - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type SPI_SetTimeOutValue(SPI_ID_Type spiNo, uint16_t value) -{ - uint32_t tmpVal; - uint32_t SPIx = spiAddr[spiNo]; - - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - - /* Set time-out value */ - tmpVal = BL_RD_REG(SPIx, SPI_STO_VALUE); - BL_WR_REG(SPIx, SPI_STO_VALUE, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_STO_VALUE, value - 1)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Set de-glitch function cycle count value - * - * @param spiNo: SPI ID type - * @param cnt: De-glitch function cycle count - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type SPI_SetDeglitchCount(SPI_ID_Type spiNo, uint8_t cnt) -{ - uint32_t tmpVal; - uint32_t SPIx = spiAddr[spiNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - - /* Set count value */ - tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_DEG_CNT, cnt); - BL_WR_REG(SPIx, SPI_CONFIG, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Enable rx data ignore function and set start/stop point - * - * @param spiNo: SPI ID type - * @param startPoint: Start point - * @param stopPoint: Stop point - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type SPI_RxIgnoreEnable(SPI_ID_Type spiNo, uint8_t startPoint, uint8_t stopPoint) -{ - uint32_t tmpVal; - uint32_t SPIx = spiAddr[spiNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - - /* Enable rx ignore function */ - tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); - BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN)); - - /* Set start and stop point */ - tmpVal = startPoint << SPI_CR_SPI_RXD_IGNR_S_POS | stopPoint; - BL_WR_REG(SPIx, SPI_RXD_IGNR, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Disable rx data ignore function - * - * @param spiNo: SPI ID type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type SPI_RxIgnoreDisable(SPI_ID_Type spiNo) -{ - uint32_t tmpVal; - uint32_t SPIx = spiAddr[spiNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - - /* Disable rx ignore function */ - tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); - BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Clear tx fifo and tx fifo overflow/underflow status - * - * @param spiNo: SPI ID type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type SPI_ClrTxFifo(SPI_ID_Type spiNo) -{ - uint32_t tmpVal; - uint32_t SPIx = spiAddr[spiNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - - /* Clear tx fifo */ - tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0); - BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Clear rx fifo and rx fifo overflow/underflow status - * - * @param spiNo: SPI ID type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type SPI_ClrRxFifo(SPI_ID_Type spiNo) -{ - uint32_t tmpVal; - uint32_t SPIx = spiAddr[spiNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - - /* Clear rx fifo */ - tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0); - BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Clear spi interrupt status - * - * @param spiNo: SPI ID type - * @param intType: SPI interrupt type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type SPI_ClrIntStatus(SPI_ID_Type spiNo, SPI_INT_Type intType) -{ - uint32_t tmpVal; - uint32_t SPIx = spiAddr[spiNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - - /* Clear certain or all interrupt */ - tmpVal = BL_RD_REG(SPIx, SPI_INT_STS); - - if (SPI_INT_ALL == intType) { - tmpVal |= 0x1f << SPI_CR_SPI_END_CLR_POS; - } else { - tmpVal |= 1 << (intType + SPI_CR_SPI_END_CLR_POS); - } - - BL_WR_REG(SPIx, SPI_INT_STS, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief SPI mask or unmask certain or all interrupt - * - * @param spiNo: SPI ID type - * @param intType: SPI interrupt type - * @param intMask: SPI interrupt mask value( MASK:disbale interrupt,UNMASK:enable interrupt ) - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type SPI_IntMask(SPI_ID_Type spiNo, SPI_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpVal; - uint32_t SPIx = spiAddr[spiNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - CHECK_PARAM(IS_SPI_INT_TYPE(intType)); - CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); - - tmpVal = BL_RD_REG(SPIx, SPI_INT_STS); - - /* Mask or unmask certain or all interrupt */ - if (SPI_INT_ALL == intType) { - if (MASK == intMask) { - tmpVal |= 0x3f << SPI_CR_SPI_END_MASK_POS; - } else { - tmpVal &= ~(0x3f << SPI_CR_SPI_END_MASK_POS); - } - } else { - if (MASK == intMask) { - tmpVal |= 1 << (intType + SPI_CR_SPI_END_MASK_POS); - } else { - tmpVal &= ~(1 << (intType + SPI_CR_SPI_END_MASK_POS)); - } - } - - /* Write back */ - BL_WR_REG(SPIx, SPI_INT_STS, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Install spi interrupt callback function - * - * @param spiNo: SPI ID type - * @param intType: SPI interrupt type - * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) - * - * @return SUCCESS - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -BL_Err_Type SPI_Int_Callback_Install(SPI_ID_Type spiNo, SPI_INT_Type intType, intCallback_Type *cbFun) -{ - /* Check the parameters */ - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - CHECK_PARAM(IS_SPI_INT_TYPE(intType)); - - spiIntCbfArra[spiNo][intType] = cbFun; - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief SPI send datas - * - * @param spiNo: SPI ID type - * @param buff: Buffer of datas - * @param length: Length of buffer - * @param timeoutType: Enable or disable timeout judgment - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type SPI_SendData(SPI_ID_Type spiNo, void *buff, uint32_t length, SPI_Timeout_Type timeoutType) -{ - uint32_t tmpVal; - uint32_t txLen = 0; - uint32_t rData; - uint32_t frameSize = 0; - uint32_t SPIx = spiAddr[spiNo]; - uint32_t timeoutCnt = SPI_TX_TIMEOUT_COUNT; - - /* Check the parameters */ - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType)); - - /* Get fifo valid width */ - tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); - frameSize = BL_GET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE); - - switch (frameSize) { - case 0: - - tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE; - - /* Fill tx fifo */ - for (; txLen < tmpVal; txLen++) { - BL_WR_REG(SPIx, SPI_FIFO_WDATA, ((uint8_t *)buff)[txLen]); - } - - /* Wait receive data and send the rest of the data */ - for (; txLen < length; txLen++) { - timeoutCnt = SPI_RX_TIMEOUT_COUNT; - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) { - if (timeoutType) { - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } - } - - rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA); - BL_WR_REG(SPIx, SPI_FIFO_WDATA, ((uint8_t *)buff)[txLen]); - } - - /* Wait receive the rest of the data */ - for (txLen = 0; txLen < tmpVal; txLen++) { - timeoutCnt = SPI_RX_TIMEOUT_COUNT; - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) { - if (timeoutType) { - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } - } - - rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA); - } - - break; - - case 1: - - tmpVal = length <= (SPI_TX_FIFO_SIZE / 2) ? length : (SPI_TX_FIFO_SIZE / 2); - - /* Fill tx fifo */ - for (; txLen < tmpVal; txLen++) { - BL_WR_REG(SPIx, SPI_FIFO_WDATA, ((uint16_t *)buff)[txLen]); - } - - /* Wait receive data and send the rest of the data */ - for (; txLen < length; txLen++) { - timeoutCnt = SPI_RX_TIMEOUT_COUNT; - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) { - if (timeoutType) { - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } - } - - rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA); - BL_WR_REG(SPIx, SPI_FIFO_WDATA, ((uint16_t *)buff)[txLen]); - } - - /* Wait receive the rest of the data */ - for (txLen = 0; txLen < tmpVal; txLen++) { - timeoutCnt = SPI_RX_TIMEOUT_COUNT; - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) { - if (timeoutType) { - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } - } - - rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA); - } - - break; - - case 2: - - /* Same as case 3 */ - case 3: - - tmpVal = length <= (SPI_TX_FIFO_SIZE / 4) ? length : (SPI_TX_FIFO_SIZE / 4); - - /* Fill tx fifo */ - for (; txLen < tmpVal; txLen++) { - BL_WR_REG(SPIx, SPI_FIFO_WDATA, ((uint32_t *)buff)[txLen]); - } - - /* Wait receive data and send the rest of the data */ - for (; txLen < length; txLen++) { - timeoutCnt = SPI_RX_TIMEOUT_COUNT; - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) { - if (timeoutType) { - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } - } - - rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA); - BL_WR_REG(SPIx, SPI_FIFO_WDATA, ((uint32_t *)buff)[txLen]); - } - - /* Wait receive the rest of the data */ - for (txLen = 0; txLen < tmpVal; txLen++) { - timeoutCnt = SPI_RX_TIMEOUT_COUNT; - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) { - if (timeoutType) { - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } - } - - rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA); - } - - break; - - default: - break; - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief SPI receive datas - * - * @param spiNo: SPI ID type - * @param buff: Buffer of datas - * @param length: Length of buffer - * @param timeoutType: Enable or disable timeout judgment - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type SPI_ReceiveData(SPI_ID_Type spiNo, void *buff, uint32_t length, SPI_Timeout_Type timeoutType) -{ - uint32_t tmpVal; - uint32_t rxLen = 0; - uint32_t frameSize = 0; - uint32_t SPIx = spiAddr[spiNo]; - uint32_t timeoutCnt = SPI_RX_TIMEOUT_COUNT; - - /* Check the parameters */ - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType)); - - /* Get fifo valid width */ - tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); - frameSize = BL_GET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE); - - switch (frameSize) { - case 0: - - tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE; - - /* Fill tx fifo with 0 */ - for (rxLen = 0; rxLen < tmpVal; rxLen++) { - BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0); - } - - /* Wait receive data and send the rest of the data 0 */ - for (rxLen = 0; rxLen < length - tmpVal; rxLen++) { - timeoutCnt = SPI_RX_TIMEOUT_COUNT; - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) { - if (timeoutType) { - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } - } - - ((uint8_t *)buff)[rxLen] = BL_RD_REG(SPIx, SPI_FIFO_RDATA); - BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0); - } - - /* Wait receive the rest of the data */ - for (; rxLen < length; rxLen++) { - timeoutCnt = SPI_RX_TIMEOUT_COUNT; - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) { - if (timeoutType) { - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } - } - - ((uint8_t *)buff)[rxLen] = BL_RD_REG(SPIx, SPI_FIFO_RDATA); - } - - break; - - case 1: - - tmpVal = length <= (SPI_TX_FIFO_SIZE / 2) ? length : (SPI_TX_FIFO_SIZE / 2); - - /* Fill tx fifo with 0 */ - for (rxLen = 0; rxLen < tmpVal; rxLen++) { - BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0); - } - - /* Wait receive data and send the rest of the data 0 */ - for (rxLen = 0; rxLen < length - tmpVal; rxLen++) { - timeoutCnt = SPI_RX_TIMEOUT_COUNT; - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) { - if (timeoutType) { - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } - } - - ((uint16_t *)buff)[rxLen] = BL_RD_REG(SPIx, SPI_FIFO_RDATA); - BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0); - } - - /* Wait receive the rest of the data */ - for (; rxLen < length; rxLen++) { - timeoutCnt = SPI_RX_TIMEOUT_COUNT; - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) { - if (timeoutType) { - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } - } - - ((uint16_t *)buff)[rxLen] = BL_RD_REG(SPIx, SPI_FIFO_RDATA); - } - - break; - - case 2: - - /* Same as case 3 */ - case 3: - - tmpVal = length <= (SPI_TX_FIFO_SIZE / 4) ? length : (SPI_TX_FIFO_SIZE / 4); - - /* Fill tx fifo with 0 */ - for (rxLen = 0; rxLen < tmpVal; rxLen++) { - BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0); - } - - /* Wait receive data and send the rest of the data 0 */ - for (rxLen = 0; rxLen < length - tmpVal; rxLen++) { - timeoutCnt = SPI_RX_TIMEOUT_COUNT; - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) { - if (timeoutType) { - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } - } - - ((uint32_t *)buff)[rxLen] = BL_RD_REG(SPIx, SPI_FIFO_RDATA); - BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0); - } - - /* Wait receive the rest of the data */ - for (; rxLen < length; rxLen++) { - timeoutCnt = SPI_RX_TIMEOUT_COUNT; - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) { - if (timeoutType) { - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } - } - - ((uint32_t *)buff)[rxLen] = BL_RD_REG(SPIx, SPI_FIFO_RDATA); - } - - break; - - default: - break; - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief SPI send and receive datas at the same time - * - * @param spiNo: SPI ID type - * @param sendBuff: Buffer of datas to send - * @param recvBuff: Buffer of datas received - * @param length: Length of buffer - * @param timeoutType: Enable or disable timeout judgment - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type SPI_SendRecvData(SPI_ID_Type spiNo, void *sendBuff, void *recvBuff, uint32_t length, SPI_Timeout_Type timeoutType) -{ - uint32_t tmpVal; - uint32_t txLen = 0; - uint32_t frameSize = 0; - uint32_t SPIx = spiAddr[spiNo]; - uint32_t timeoutCnt = SPI_RX_TIMEOUT_COUNT; - - /* Check the parameters */ - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType)); - - /* Get fifo valid width */ - tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); - frameSize = BL_GET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE); - - switch (frameSize) { - case 0: - - tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE; - - /* Fill tx fifo */ - for (; txLen < tmpVal; txLen++) { - BL_WR_REG(SPIx, SPI_FIFO_WDATA, ((uint8_t *)sendBuff)[txLen]); - } - - /* Wait receive data and send the rest of the data */ - for (; txLen < length; txLen++) { - timeoutCnt = SPI_RX_TIMEOUT_COUNT; - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) { - if (timeoutType) { - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } - } - - ((uint8_t *)recvBuff)[txLen - tmpVal] = BL_RD_REG(SPIx, SPI_FIFO_RDATA); - BL_WR_REG(SPIx, SPI_FIFO_WDATA, ((uint8_t *)sendBuff)[txLen]); - } - - /* Wait receive the rest of the data */ - for (txLen = 0; txLen < tmpVal; txLen++) { - timeoutCnt = SPI_RX_TIMEOUT_COUNT; - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) { - if (timeoutType) { - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } - } - - ((uint8_t *)recvBuff)[length - tmpVal + txLen] = BL_RD_REG(SPIx, SPI_FIFO_RDATA); - } - - break; - - case 1: - - tmpVal = length <= (SPI_TX_FIFO_SIZE / 2) ? length : (SPI_TX_FIFO_SIZE / 2); - - /* Fill tx fifo */ - for (; txLen < tmpVal; txLen++) { - BL_WR_REG(SPIx, SPI_FIFO_WDATA, ((uint16_t *)sendBuff)[txLen]); - } - - /* Wait receive data and send the rest of the data */ - for (; txLen < length; txLen++) { - timeoutCnt = SPI_RX_TIMEOUT_COUNT; - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) { - if (timeoutType) { - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } - } - - ((uint16_t *)recvBuff)[txLen - tmpVal] = BL_RD_REG(SPIx, SPI_FIFO_RDATA); - BL_WR_REG(SPIx, SPI_FIFO_WDATA, ((uint16_t *)sendBuff)[txLen]); - } - - /* Wait receive the rest of the data */ - for (txLen = 0; txLen < tmpVal; txLen++) { - timeoutCnt = SPI_RX_TIMEOUT_COUNT; - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) { - if (timeoutType) { - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } - } - - ((uint16_t *)recvBuff)[length - tmpVal + txLen] = BL_RD_REG(SPIx, SPI_FIFO_RDATA); - } - - break; - - case 2: - - /* Same as case 3 */ - case 3: - - tmpVal = length <= (SPI_TX_FIFO_SIZE / 4) ? length : (SPI_TX_FIFO_SIZE / 4); - - /* Fill tx fifo */ - for (; txLen < tmpVal; txLen++) { - BL_WR_REG(SPIx, SPI_FIFO_WDATA, ((uint32_t *)sendBuff)[txLen]); - } - - /* Wait receive data and send the rest of the data */ - for (; txLen < length; txLen++) { - timeoutCnt = SPI_RX_TIMEOUT_COUNT; - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) { - if (timeoutType) { - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } - } - - ((uint32_t *)recvBuff)[txLen - tmpVal] = BL_RD_REG(SPIx, SPI_FIFO_RDATA); - BL_WR_REG(SPIx, SPI_FIFO_WDATA, ((uint32_t *)sendBuff)[txLen]); - } - - /* Wait receive the rest of the data */ - for (txLen = 0; txLen < tmpVal; txLen++) { - timeoutCnt = SPI_RX_TIMEOUT_COUNT; - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) { - if (timeoutType) { - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } - } - - ((uint32_t *)recvBuff)[length - tmpVal + txLen] = BL_RD_REG(SPIx, SPI_FIFO_RDATA); - } - - break; - - default: - break; - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Get tx fifo available count value function - * - * @param spiNo: SPI ID type - * - * @return Count value - * -*******************************************************************************/ -uint8_t SPI_GetTxFifoCount(SPI_ID_Type spiNo) -{ - uint32_t SPIx = spiAddr[spiNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - - /* Get count value */ - return BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_TX_FIFO_CNT); -} - -/****************************************************************************/ /** - * @brief Get rx fifo available count value function - * - * @param spiNo: SPI ID type - * - * @return Count value - * -*******************************************************************************/ -uint8_t SPI_GetRxFifoCount(SPI_ID_Type spiNo) -{ - uint32_t SPIx = spiAddr[spiNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - - /* Get count value */ - return BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT); -} - -/****************************************************************************/ /** - * @brief Get spi interrupt status - * - * @param spiNo: SPI ID type - * @param intType: SPI interrupt type - * - * @return Status of interrupt - * -*******************************************************************************/ -BL_Sts_Type SPI_GetIntStatus(SPI_ID_Type spiNo, SPI_INT_Type intType) -{ - uint32_t tmpVal; - uint32_t SPIx = spiAddr[spiNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - CHECK_PARAM(IS_SPI_INT_TYPE(intType)); - - /* Get certain or all interrupt status */ - tmpVal = BL_RD_REG(SPIx, SPI_INT_STS); - - if (SPI_INT_ALL == intType) { - if ((tmpVal & 0x3f) != 0) { - return SET; - } else { - return RESET; - } - } else { - if ((tmpVal & (1U << intType)) != 0) { - return SET; - } else { - return RESET; - } - } -} - -/****************************************************************************/ /** - * @brief Get indicator of spi bus busy - * - * @param spiNo: SPI ID type - * - * @return Status of spi bus - * -*******************************************************************************/ -BL_Sts_Type SPI_GetBusyStatus(SPI_ID_Type spiNo) -{ - uint32_t tmpVal; - uint32_t SPIx = spiAddr[spiNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - - /* Get bus busy status */ - tmpVal = BL_RD_REG(SPIx, SPI_BUS_BUSY); - - if (BL_IS_REG_BIT_SET(tmpVal, SPI_STS_SPI_BUS_BUSY)) { - return SET; - } else { - return RESET; - } -} - -/****************************************************************************/ /** - * @brief Get tx/rx fifo overflow or underflow status - * - * @param spiNo: SPI ID type - * @param fifoSts: Select tx/rx overflow or underflow - * - * @return Status of tx/rx fifo - * -*******************************************************************************/ -BL_Sts_Type SPI_GetFifoStatus(SPI_ID_Type spiNo, SPI_FifoStatus_Type fifoSts) -{ - uint32_t tmpVal; - uint32_t SPIx = spiAddr[spiNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - CHECK_PARAM(IS_SPI_FIFOSTATUS_TYPE(fifoSts)); - - /* Get tx/rx fifo overflow or underflow status */ - tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0); - - if ((tmpVal & (1U << (fifoSts + SPI_TX_FIFO_OVERFLOW_POS))) != 0) { - return SET; - } else { - return RESET; - } -} - -/****************************************************************************/ /** - * @brief SPI0 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void SPI0_IRQHandler(void) -{ - SPI_IntHandler(SPI0_ID); -} -#endif - -/****************************************************************************/ /** - * @brief SPI1 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void SPI1_IRQHandler(void) -{ - SPI_IntHandler(SPI0_MM_ID); -} -#endif - -/*@} end of group SPI_Public_Functions */ - -/*@} end of group SPI */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_timer.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_timer.c deleted file mode 100644 index 8d1e6211ea..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_timer.c +++ /dev/null @@ -1,1317 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_timer.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_timer.h" -#include "bl808_glb.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup TIMER - * @{ - */ - -/** @defgroup TIMER_Private_Macros - * @{ - */ -#define TIMER_MAX_MATCH 3 - -/*@} end of group TIMER_Private_Macros */ - -/** @defgroup TIMER_Private_Types - * @{ - */ - -/*@} end of group TIMER_Private_Types */ - -/** @defgroup TIMER_Private_Variables - * @{ - */ -static const uint32_t timerAddr[TIMER_ID_MAX] = { TIMER0_BASE, TIMER1_BASE }; -#ifndef BFLB_USE_HAL_DRIVER -intCallback_Type *timerIntCbfArra[TIMER_ID_MAX][TIMER_CH_MAX][TIMER_INT_ALL] = { NULL }; -intCallback_Type *wdtIntCbfArra[WDT_ID_MAX][WDT_INT_ALL] = { NULL }; -#endif - -/*@} end of group TIMER_Private_Variables */ - -/** @defgroup TIMER_Global_Variables - * @{ - */ - -/*@} end of group TIMER_Global_Variables */ - -/** @defgroup TIMER_Private_Fun_Declaration - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -static void TIMER_IntHandler(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh); -#endif - -/*@} end of group TIMER_Private_Fun_Declaration */ - -/** @defgroup TIMER_Private_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief TIMER interrupt common handler function - * - * @param timerId: Timer ID type - * @param timerCh: TIMER channel type - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void TIMER_IntHandler(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh) -{ - uint32_t intId; - uint32_t tmpVal; - uint32_t tmpAddr; - uint32_t TIMERx = timerAddr[timerId]; - - intId = BL_RD_WORD(TIMERx + TIMER_TSR2_OFFSET + 4 * timerCh); - tmpAddr = TIMERx + TIMER_TICR2_OFFSET + 4 * timerCh; - tmpVal = BL_RD_WORD(tmpAddr); - - /* Comparator 0 match interrupt */ - if (BL_IS_REG_BIT_SET(intId, TIMER_TSR2_0)) { - BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TSR2_0)); - - if (timerIntCbfArra[timerId][timerCh][TIMER_INT_COMP_0] != NULL) { - /* Call the callback function */ - timerIntCbfArra[timerId][timerCh][TIMER_INT_COMP_0](); - } - } - - /* Comparator 1 match interrupt */ - if (BL_IS_REG_BIT_SET(intId, TIMER_TSR2_1)) { - BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TSR2_1)); - - if (timerIntCbfArra[timerId][timerCh][TIMER_INT_COMP_1] != NULL) { - /* Call the callback function */ - timerIntCbfArra[timerId][timerCh][TIMER_INT_COMP_1](); - } - } - - /* Comparator 2 match interrupt */ - if (BL_IS_REG_BIT_SET(intId, TIMER_TSR2_2)) { - BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TSR2_2)); - - if (timerIntCbfArra[timerId][timerCh][TIMER_INT_COMP_2] != NULL) { - /* Call the callback function */ - timerIntCbfArra[timerId][timerCh][TIMER_INT_COMP_2](); - } - } -} -#endif - -/****************************************************************************/ /** - * @brief Get the specified channel and match comparator value - * - * @param timerId: Timer ID type - * @param timerCh: TIMER channel type - * @param cmpNo: TIMER comparator ID type - * - * @return Match comapre register value - * -*******************************************************************************/ -uint32_t TIMER_GetCompValue(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo) -{ - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[timerId]; - - /* Check the parameters */ - CHECK_PARAM(IS_TIMER_ID_TYPE(timerId)); - CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); - CHECK_PARAM(IS_TIMER_COMP_ID_TYPE(cmpNo)); - - tmpVal = BL_RD_WORD(TIMERx + TIMER_TMR2_0_OFFSET + 4 * (TIMER_MAX_MATCH * timerCh + cmpNo)); - return tmpVal; -} - -/****************************************************************************/ /** - * @brief TIMER set specified channel and comparator compare value - * - * @param timerId: Timer ID type - * @param timerCh: TIMER channel type - * @param cmpNo: TIMER comparator ID type - * @param val: TIMER match compare register value - * - * @return None - * -*******************************************************************************/ -void TIMER_SetCompValue(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo, uint32_t val) -{ - uint32_t TIMERx = timerAddr[timerId]; - - /* Check the parameters */ - CHECK_PARAM(IS_TIMER_ID_TYPE(timerId)); - CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); - CHECK_PARAM(IS_TIMER_COMP_ID_TYPE(cmpNo)); - - BL_WR_WORD(TIMERx + TIMER_TMR2_0_OFFSET + 4 * (TIMER_MAX_MATCH * timerCh + cmpNo), val); -} - -/****************************************************************************/ /** - * @brief TIMER enable or disable compare value effect immediately after update - * - * @param timerId: Timer ID type - * @param timerCh: TIMER channel type - * @param enable: Enable or disable - * - * @return None - * -*******************************************************************************/ -void TIMER_CompValueEffectImmediately(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, BL_Fun_Type enable) -{ - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[timerId]; - - /* Check the parameters */ - CHECK_PARAM(IS_TIMER_ID_TYPE(timerId)); - CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); - - tmpVal = BL_RD_REG(TIMERx, TIMER_TCMR); - - if (timerCh == TIMER_CH0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER2_ALIGN, 1 - enable); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER3_ALIGN, 1 - enable); - } - - BL_WR_REG(TIMERx, TIMER_TCMR, tmpVal); -} - -/****************************************************************************/ /** - * @brief TIMER get the specified channel count value - * - * @param timerId: Timer ID type - * @param timerCh: TIMER channel type - * - * @return TIMER count register value - * -*******************************************************************************/ -uint32_t TIMER_GetCounterValue(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh) -{ - uint32_t tmpVal; - uint32_t tmpAddr; - uint32_t TIMERx = timerAddr[timerId]; - - /* Check the parameters */ - CHECK_PARAM(IS_TIMER_ID_TYPE(timerId)); - CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); - - tmpAddr = TIMERx + TIMER_TCR2_OFFSET+ 4 * timerCh; - tmpVal = BL_RD_WORD(tmpAddr); - - return tmpVal; -} - -/****************************************************************************/ /** - * @brief TIMER reset count value - * - * @param timerId: Timer ID type - * @param timerCh: TIMER channel type - * - * @return None - * -*******************************************************************************/ -void TIMER_ResetCounterValue(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh) -{ - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[timerId]; - - /* Check the parameters */ - CHECK_PARAM(IS_TIMER_ID_TYPE(timerId)); - CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); - - tmpVal = BL_RD_REG(TIMERx, TIMER_TCER); - - if (timerCh == TIMER_CH0) { - tmpVal = BL_SET_REG_BIT(tmpVal, TIMER_TCR2_CNT_CLR); - BL_WR_REG(TIMERx, TIMER_TCER, tmpVal); - tmpVal = BL_CLR_REG_BIT(tmpVal, TIMER_TCR2_CNT_CLR); - BL_WR_REG(TIMERx, TIMER_TCER, tmpVal); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, TIMER_TCR3_CNT_CLR); - BL_WR_REG(TIMERx, TIMER_TCER, tmpVal); - tmpVal = BL_CLR_REG_BIT(tmpVal, TIMER_TCR3_CNT_CLR); - BL_WR_REG(TIMERx, TIMER_TCER, tmpVal); - } -} - -/****************************************************************************/ /** - * @brief TIMER get specified channel and comparator match status - * - * @param timerId: Timer ID type - * @param timerCh: TIMER channel type - * @param cmpNo: TIMER comparator ID type - * - * @return SET or RESET - * -*******************************************************************************/ -BL_Sts_Type TIMER_GetMatchStatus(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo) -{ - uint32_t tmpVal; - BL_Sts_Type bitStatus = RESET; - uint32_t TIMERx = timerAddr[timerId]; - - /* Check the parameters */ - CHECK_PARAM(IS_TIMER_ID_TYPE(timerId)); - CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); - CHECK_PARAM(IS_TIMER_COMP_ID_TYPE(cmpNo)); - - tmpVal = BL_RD_WORD(TIMERx + TIMER_TSR2_OFFSET + 4 * timerCh); - - switch (cmpNo) { - case TIMER_COMP_ID_0: - bitStatus = BL_IS_REG_BIT_SET(tmpVal, TIMER_TSR3_0) ? SET : RESET; - break; - - case TIMER_COMP_ID_1: - bitStatus = BL_IS_REG_BIT_SET(tmpVal, TIMER_TSR3_1) ? SET : RESET; - break; - - case TIMER_COMP_ID_2: - bitStatus = BL_IS_REG_BIT_SET(tmpVal, TIMER_TSR3_2) ? SET : RESET; - break; - - default: - break; - } - - return bitStatus; -} - -/****************************************************************************/ /** - * @brief TIMER get specified channel preload value - * - * @param timerId: Timer ID type - * @param timerCh: TIMER channel type - * - * @return Preload register value - * -*******************************************************************************/ -uint32_t TIMER_GetPreloadValue(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh) -{ - uint32_t TIMERx = timerAddr[timerId]; - - /* Check the parameters */ - CHECK_PARAM(IS_TIMER_ID_TYPE(timerId)); - CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); - - return BL_RD_WORD(TIMERx + TIMER_TPLVR2_OFFSET + 4 * timerCh); -} - -/****************************************************************************/ /** - * @brief TIMER set preload register low 32bits value - * - * @param timerId: Timer ID type - * @param timerCh: TIMER channel type - * @param val: Preload register low 32bits value - * - * @return None - * -*******************************************************************************/ -void TIMER_SetPreloadValue(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, uint32_t val) -{ - uint32_t TIMERx = timerAddr[timerId]; - - /* Check the parameters */ - CHECK_PARAM(IS_TIMER_ID_TYPE(timerId)); - CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); - - BL_WR_WORD(TIMERx + TIMER_TPLVR2_OFFSET + 4 * timerCh, val); -} - -/****************************************************************************/ /** - * @brief TIMER set preload trigger source,COMP0,COMP1,COMP2 or None - * - * @param timerId: Timer ID type - * @param timerCh: TIMER channel type - * @param plSrc: TIMER preload source type - * - * @return None - * -*******************************************************************************/ -void TIMER_SetPreloadTrigSrc(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_PreLoad_Trig_Type plSrc) -{ - uint32_t TIMERx = timerAddr[timerId]; - - /* Check the parameters */ - CHECK_PARAM(IS_TIMER_ID_TYPE(timerId)); - CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); - CHECK_PARAM(IS_TIMER_PRELOAD_TRIG_TYPE(plSrc)); - - BL_WR_WORD(TIMERx + TIMER_TPLCR2_OFFSET + 4 * timerCh, plSrc); -} - -/****************************************************************************/ /** - * @brief TIMER set count mode:preload or free run - * - * @param timerId: Timer ID type - * @param timerCh: TIMER channel type - * @param countMode: TIMER count mode: TIMER_COUNT_PRELOAD or TIMER_COUNT_FREERUN - * - * @return None - * -*******************************************************************************/ -void TIMER_SetCountMode(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_CountMode_Type countMode) -{ - uint32_t tmpval; - uint32_t TIMERx = timerAddr[timerId]; - - /* Check the parameters */ - CHECK_PARAM(IS_TIMER_ID_TYPE(timerId)); - CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); - CHECK_PARAM(IS_TIMER_COUNTMODE_TYPE(countMode)); - - tmpval = BL_RD_WORD(TIMERx + TIMER_TCMR_OFFSET); - tmpval &= (~(1 << (timerCh + 1))); - tmpval |= (countMode << (timerCh + 1)); - - BL_WR_WORD(TIMERx + TIMER_TCMR_OFFSET, tmpval); -} - -/****************************************************************************/ /** - * @brief TIMER clear interrupt status - * - * @param timerId: Timer ID type - * @param timerCh: TIMER channel type - * @param cmpNo: TIMER macth comparator ID type - * - * @return None - * -*******************************************************************************/ -void TIMER_ClearIntStatus(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo) -{ - uint32_t tmpAddr; - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[timerId]; - - /* Check the parameters */ - CHECK_PARAM(IS_TIMER_ID_TYPE(timerId)); - CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); - CHECK_PARAM(IS_TIMER_COMP_ID_TYPE(cmpNo)); - - tmpAddr = TIMERx + TIMER_TICR2_OFFSET + 4 * timerCh; - - tmpVal = BL_RD_WORD(tmpAddr); - tmpVal |= (1 << cmpNo); - - BL_WR_WORD(tmpAddr, tmpVal); -} - -/****************************************************************************/ /** - * @brief TIMER initialization function - * - * @param timerId: Timer ID type - * @param timerCfg: TIMER configuration structure pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type TIMER_Init(TIMER_ID_Type timerId, TIMER_CFG_Type *timerCfg) -{ - TIMER_Chan_Type timerCh = timerCfg->timerCh; - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[timerId]; - - /* Check the parameters */ - CHECK_PARAM(IS_TIMER_ID_TYPE(timerId)); - CHECK_PARAM(IS_TIMER_CLKSRC_TYPE(timerCfg->clkSrc)); - CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCfg->timerCh)); - CHECK_PARAM(IS_TIMER_PRELOAD_TRIG_TYPE(timerCfg->plTrigSrc)); - CHECK_PARAM(IS_TIMER_COUNTMODE_TYPE(timerCfg->countMode)); - - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_TIMER); - - /* Configure timer clock source */ - tmpVal = BL_RD_REG(TIMERx, TIMER_TCCR); - - if (timerCh == TIMER_CH0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_CS_2, timerCfg->clkSrc); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_CS_3, timerCfg->clkSrc); - } - - BL_WR_REG(TIMERx, TIMER_TCCR, tmpVal); - - /* Configure timer clock division */ - tmpVal = BL_RD_REG(TIMERx, TIMER_TCDR); - - if (timerCh == TIMER_CH0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_TCDR2, timerCfg->clockDivision); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_TCDR3, timerCfg->clockDivision); - } - - BL_WR_REG(TIMERx, TIMER_TCDR, tmpVal); - - /* Configure timer count mode: preload or free run */ - TIMER_SetCountMode(timerId, timerCh, timerCfg->countMode); - - /* Configure timer preload trigger src */ - TIMER_SetPreloadTrigSrc(timerId, timerCh, timerCfg->plTrigSrc); - - if (timerCfg->countMode == TIMER_COUNT_PRELOAD) { - /* Configure timer preload value */ - TIMER_SetPreloadValue(timerId, timerCh, timerCfg->preLoadVal); - - /* Configure match compare values */ - if (timerCfg->matchVal0 > 1 + timerCfg->preLoadVal) { - TIMER_SetCompValue(timerId, timerCh, TIMER_COMP_ID_0, timerCfg->matchVal0 - 2); - } else { - TIMER_SetCompValue(timerId, timerCh, TIMER_COMP_ID_0, timerCfg->matchVal0); - } - - if (timerCfg->matchVal1 > 1 + timerCfg->preLoadVal) { - TIMER_SetCompValue(timerId, timerCh, TIMER_COMP_ID_1, timerCfg->matchVal1 - 2); - } else { - TIMER_SetCompValue(timerId, timerCh, TIMER_COMP_ID_1, timerCfg->matchVal1); - } - - if (timerCfg->matchVal2 > 1 + timerCfg->preLoadVal) { - TIMER_SetCompValue(timerId, timerCh, TIMER_COMP_ID_2, timerCfg->matchVal2 - 2); - } else { - TIMER_SetCompValue(timerId, timerCh, TIMER_COMP_ID_2, timerCfg->matchVal2); - } - } else { - /* Configure match compare values */ - if (timerCfg->matchVal0 > 1) { - TIMER_SetCompValue(timerId, timerCh, TIMER_COMP_ID_0, timerCfg->matchVal0 - 2); - } else { - TIMER_SetCompValue(timerId, timerCh, TIMER_COMP_ID_0, timerCfg->matchVal0); - } - - if (timerCfg->matchVal1 > 1) { - TIMER_SetCompValue(timerId, timerCh, TIMER_COMP_ID_1, timerCfg->matchVal1 - 2); - } else { - TIMER_SetCompValue(timerId, timerCh, TIMER_COMP_ID_1, timerCfg->matchVal1); - } - - if (timerCfg->matchVal2 > 1) { - TIMER_SetCompValue(timerId, timerCh, TIMER_COMP_ID_2, timerCfg->matchVal2 - 2); - } else { - TIMER_SetCompValue(timerId, timerCh, TIMER_COMP_ID_2, timerCfg->matchVal2); - } - } - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(TIMER0_CH0_IRQn, TIMER0_CH0_IRQHandler); - Interrupt_Handler_Register(TIMER0_CH1_IRQn, TIMER0_CH1_IRQHandler); - Interrupt_Handler_Register(TIMER1_CH0_IRQn, TIMER1_CH0_IRQHandler); - Interrupt_Handler_Register(TIMER1_CH1_IRQn, TIMER1_CH1_IRQHandler); - -#endif - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief TIMER set default value of all registers function - * - * @param timerId: TIMER ID type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type TIMER_DeInit(TIMER_ID_Type timerId) -{ - if (TIMER0_ID == timerId) { - GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_TIMER); - } else if (TIMER1_ID == timerId) { - GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_TIMER); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief TIMER enable one channel function - * - * @param timerId: Timer ID type - * @param timerCh: TIMER channel type - * - * @return None - * -*******************************************************************************/ -void TIMER_Enable(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh) -{ - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[timerId]; - - /* Check the parameters */ - CHECK_PARAM(IS_TIMER_ID_TYPE(timerId)); - CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); - - tmpVal = BL_RD_REG(TIMERx, TIMER_TCER); - tmpVal |= (1 << (timerCh + 1)); - - BL_WR_REG(TIMERx, TIMER_TCER, tmpVal); -} - -/****************************************************************************/ /** - * @brief TIMER disable one channel function - * - * @param timerId: Timer ID type - * @param timerCh: TIMER channel type - * - * @return None - * -*******************************************************************************/ -void TIMER_Disable(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh) -{ - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[timerId]; - - /* Check the parameters */ - CHECK_PARAM(IS_TIMER_ID_TYPE(timerId)); - CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); - - tmpVal = BL_RD_REG(TIMERx, TIMER_TCER); - tmpVal &= (~(1 << (timerCh + 1))); - - BL_WR_REG(TIMERx, TIMER_TCER, tmpVal); -} - -/****************************************************************************/ /** - * @brief TIMER mask or unmask certain or all interrupt - * - * @param timerId: Timer ID type - * @param timerCh: TIMER channel type - * @param intType: TIMER interrupt type - * @param intMask: TIMER interrupt mask value:MASK:disbale interrupt.UNMASK:enable interrupt - * - * @return None - * -*******************************************************************************/ -void TIMER_IntMask(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpAddr; - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[timerId]; - - /* Check the parameters */ - CHECK_PARAM(IS_TIMER_ID_TYPE(timerId)); - CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); - CHECK_PARAM(IS_TIMER_INT_TYPE(intType)); - CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); - - tmpAddr = TIMERx + TIMER_TIER2_OFFSET + 4 * timerCh; - tmpVal = BL_RD_WORD(tmpAddr); - - switch (intType) { - case TIMER_INT_COMP_0: - if (intMask == UNMASK) { - /* Enable this interrupt */ - BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TIER3_0)); - } else { - /* Disable this interrupt */ - BL_WR_WORD(tmpAddr, BL_CLR_REG_BIT(tmpVal, TIMER_TIER3_0)); - } - - break; - - case TIMER_INT_COMP_1: - if (intMask == UNMASK) { - /* Enable this interrupt */ - BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TIER3_1)); - } else { - /* Disable this interrupt */ - BL_WR_WORD(tmpAddr, BL_CLR_REG_BIT(tmpVal, TIMER_TIER3_1)); - } - - break; - - case TIMER_INT_COMP_2: - if (intMask == UNMASK) { - /* Enable this interrupt */ - BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TIER3_2)); - } else { - /* Disable this interrupt */ - BL_WR_WORD(tmpAddr, BL_CLR_REG_BIT(tmpVal, TIMER_TIER3_2)); - } - - break; - - case TIMER_INT_ALL: - if (intMask == UNMASK) { - /* Enable this interrupt */ - BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TIER3_0)); - BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TIER3_1)); - BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TIER3_2)); - } else { - /* Disable this interrupt */ - BL_WR_WORD(tmpAddr, BL_CLR_REG_BIT(tmpVal, TIMER_TIER3_0)); - BL_WR_WORD(tmpAddr, BL_CLR_REG_BIT(tmpVal, TIMER_TIER3_1)); - BL_WR_WORD(tmpAddr, BL_CLR_REG_BIT(tmpVal, TIMER_TIER3_2)); - } - - break; - - default: - break; - } -} - -/****************************************************************************/ /** - * @brief TIMER set gpio polarity - * - * @param timerId: Timer ID type - * @param timerCh: TIMER channel type - * @param polarity: TIMER GPIO polarity - * - * @return None - * -*******************************************************************************/ -void TIMER_GPIOSetPolarity(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_GPIO_Polarity_Type polarity) -{ - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[timerId]; - - /* Check the parameters */ - CHECK_PARAM(IS_TIMER_ID_TYPE(timerId)); - CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); - - tmpVal = BL_RD_REG(TIMERx, TIMER_GPIO); - - if (timerCh == TIMER_CH0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER2_GPIO_INV, polarity); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER3_GPIO_INV, polarity); - } - - BL_WR_REG(TIMERx, TIMER_GPIO, tmpVal); -} - -/****************************************************************************/ /** - * @brief TIMER channel 0 enable or disable measure gpio pulse width function - * - * @param timerId: Timer ID type - * @param enable: Enable or disable - * - * @return None - * -*******************************************************************************/ -void TIMER_CH0_SetMeasurePulseWidth(TIMER_ID_Type timerId, BL_Fun_Type enable) -{ - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[timerId]; - - /* Check the parameters */ - CHECK_PARAM(IS_TIMER_ID_TYPE(timerId)); - - tmpVal = BL_RD_REG(TIMERx, TIMER_GPIO); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER2_GPIO_EN, enable); - BL_WR_REG(TIMERx, TIMER_GPIO, tmpVal); -} - -/****************************************************************************/ /** - * @brief TIMER channel 0 get gpio pulse width value function - * - * @param timerId: Timer ID type - * - * @return Pulse width - * -*******************************************************************************/ -uint32_t TIMER_CH0_GetMeasurePulseWidth(TIMER_ID_Type timerId) -{ - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[timerId]; - - /* Check the parameters */ - CHECK_PARAM(IS_TIMER_ID_TYPE(timerId)); - - do { - tmpVal = BL_RD_REG(TIMERx, TIMER_GPIO); - } while (!BL_IS_REG_BIT_SET(tmpVal, TIMER_GPIO_LAT_OK)); - - return (BL_RD_REG(TIMERx, TIMER_GPIO_LAT2) - BL_RD_REG(TIMERx, TIMER_GPIO_LAT1)); -} - -/****************************************************************************/ /** - * @brief TIMER force clock division - * - * @param timerId: Timer ID type - * @param timerChan: TIMER channel type - * - * @return None - * -*******************************************************************************/ -void TIMER_ForceClockDivision(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh) -{ - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[timerId]; - - /* Check the parameters */ - CHECK_PARAM(IS_TIMER_ID_TYPE(timerId)); - CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerChan)); - - /* write 0 after write 1 to force clock division */ - tmpVal = BL_RD_REG(TIMERx, TIMER_TCDR_FORCE); - - if (timerCh == TIMER_CH0) { - tmpVal = BL_SET_REG_BIT(tmpVal, TIMER_TCDR2_FORCE); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, TIMER_TCDR3_FORCE); - } - - BL_WR_REG(TIMERx, TIMER_TCDR_FORCE, tmpVal); - - tmpVal = BL_RD_REG(TIMERx, TIMER_TCDR_FORCE); - - if (timerCh == TIMER_CH0) { - tmpVal = BL_CLR_REG_BIT(tmpVal, TIMER_TCDR2_FORCE); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, TIMER_TCDR3_FORCE); - } - - BL_WR_REG(TIMERx, TIMER_TCDR_FORCE, tmpVal); -} - -/****************************************************************************/ /** - * @brief TIMER install interrupt callback - * - * @param timerId: Timer ID type - * @param timerChan: TIMER channel type - * @param intType: TIMER interrupt type - * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void TIMER_Int_Callback_Install(TIMER_ID_Type timerId, TIMER_Chan_Type timerChan, TIMER_INT_Type intType, intCallback_Type *cbFun) -{ - /* Check the parameters */ - CHECK_PARAM(IS_TIMER_ID_TYPE(timerId)); - CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerChan)); - CHECK_PARAM(IS_TIMER_INT_TYPE(intType)); - - timerIntCbfArra[timerId][timerChan][intType] = cbFun; -} -#endif - -/****************************************************************************/ /** - * @brief TIMER set watchdog clock source and clock division - * - * @param wdtId: Watchdog ID type - * @param clkSrc: Watchdog timer clock source type - * @param div: Watchdog timer clock division value - * - * @return None - * -*******************************************************************************/ -void WDT_Set_Clock(WDT_ID_Type wdtId, TIMER_ClkSrc_Type clkSrc, uint8_t div) -{ - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[wdtId]; - - /* Check the parameters */ - CHECK_PARAM(IS_WDT_ID_TYPE(wdtId)); - CHECK_PARAM(IS_TIMER_CLKSRC_TYPE(clkSrc)); - - /* Configure watchdog timer clock source */ - tmpVal = BL_RD_REG(TIMERx, TIMER_TCCR); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_CS_WDT, clkSrc); - BL_WR_REG(TIMERx, TIMER_TCCR, tmpVal); - - /* Configure watchdog timer clock divison */ - tmpVal = BL_RD_REG(TIMERx, TIMER_TCDR); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_WCDR, div); - BL_WR_REG(TIMERx, TIMER_TCDR, tmpVal); -} - -/****************************************************************************/ /** - * @brief TIMER get watchdog match compare value - * - * @param wdtId: Watchdog ID type - * - * @return Watchdog match comapre register value - * -*******************************************************************************/ -uint16_t WDT_GetMatchValue(WDT_ID_Type wdtId) -{ - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[wdtId]; - - /* Check the parameters */ - CHECK_PARAM(IS_WDT_ID_TYPE(wdtId)); - - WDT_ENABLE_ACCESS(TIMERx); - - /* Get watchdog timer match register value */ - tmpVal = BL_RD_REG(TIMERx, TIMER_WMR); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, TIMER_WMR); - - return tmpVal; -} - -/****************************************************************************/ /** - * @brief TIMER set watchdog match compare value - * - * @param wdtId: Watchdog ID type - * @param val: Watchdog match compare value - * - * @return None - * -*******************************************************************************/ -void WDT_SetCompValue(WDT_ID_Type wdtId, uint16_t val) -{ - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[wdtId]; - - /* Check the parameters */ - CHECK_PARAM(IS_WDT_ID_TYPE(wdtId)); - - WDT_ENABLE_ACCESS(TIMERx); - - /* Set watchdog timer match register value */ - tmpVal = BL_RD_REG(TIMERx, TIMER_WMR); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_WMR, val); - BL_WR_REG(TIMERx, TIMER_WMR, tmpVal); -} - -/****************************************************************************/ /** - * @brief Watchdog enable or disable compare value effect immediately after update - * - * @param wdtId: Watchdog ID type - * @param enable: Enable or disable - * - * @return None - * -*******************************************************************************/ -void WDT_CompValueEffectImmediately(WDT_ID_Type wdtId, BL_Fun_Type enable) -{ - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[wdtId]; - - /* Check the parameters */ - CHECK_PARAM(IS_WDT_ID_TYPE(wdtId)); - CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); - - tmpVal = BL_RD_REG(TIMERx, TIMER_WMR); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_WDT_ALIGN, 1 - enable); - BL_WR_REG(TIMERx, TIMER_WMR, tmpVal); -} - -/****************************************************************************/ /** - * @brief TIMER get watchdog count register value - * - * @param wdtId: Watchdog ID type - * - * @return Watchdog count register value - * -*******************************************************************************/ -uint16_t WDT_GetCounterValue(WDT_ID_Type wdtId) -{ - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[wdtId]; - - /* Check the parameters */ - CHECK_PARAM(IS_WDT_ID_TYPE(wdtId)); - - WDT_ENABLE_ACCESS(TIMERx); - - /* Get watchdog timer count register value */ - tmpVal = BL_RD_REG(TIMERx, TIMER_WVR); - - return tmpVal; -} - -/****************************************************************************/ /** - * @brief TIMER reset watchdog count register value - * - * @param wdtId: Watchdog ID type - * - * @return None - * -*******************************************************************************/ -void WDT_ResetCounterValue(WDT_ID_Type wdtId) -{ - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[wdtId]; - - /* Check the parameters */ - CHECK_PARAM(IS_WDT_ID_TYPE(wdtId)); - - /* Reset watchdog timer count register value */ - WDT_ENABLE_ACCESS(TIMERx); - - tmpVal = BL_RD_REG(TIMERx, TIMER_WCR); - - /* Set watchdog counter reset register bit0 to 1 */ - BL_WR_REG(TIMERx, TIMER_WCR, BL_SET_REG_BIT(tmpVal, TIMER_WCR)); -} - -/****************************************************************************/ /** - * @brief TIMER get watchdog reset status - * - * @param wdtId: Watchdog ID type - * - * @return SET or RESET - * -*******************************************************************************/ -BL_Sts_Type WDT_GetResetStatus(WDT_ID_Type wdtId) -{ - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[wdtId]; - - /* Check the parameters */ - CHECK_PARAM(IS_WDT_ID_TYPE(wdtId)); - - WDT_ENABLE_ACCESS(TIMERx); - - /* Get watchdog status register */ - tmpVal = BL_RD_REG(TIMERx, TIMER_WSR); - - return (BL_IS_REG_BIT_SET(tmpVal, TIMER_WTS)) ? SET : RESET; -} - -/****************************************************************************/ /** - * @brief TIMER clear watchdog reset status - * - * @param wdtId: Watchdog ID type - * - * @return None - * -*******************************************************************************/ -void WDT_ClearResetStatus(WDT_ID_Type wdtId) -{ - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[wdtId]; - - /* Check the parameters */ - CHECK_PARAM(IS_WDT_ID_TYPE(wdtId)); - - WDT_ENABLE_ACCESS(TIMERx); - - tmpVal = BL_RD_REG(TIMERx, TIMER_WSR); - - /* Set watchdog status register */ - BL_WR_REG(TIMERx, TIMER_WSR, BL_CLR_REG_BIT(tmpVal, TIMER_WTS)); -} - -/****************************************************************************/ /** - * @brief TIMER enable watchdog function - * - * @param wdtId: Watchdog ID type - * - * @return None - * -*******************************************************************************/ -void WDT_Enable(WDT_ID_Type wdtId) -{ - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[wdtId]; - - /* Check the parameters */ - CHECK_PARAM(IS_WDT_ID_TYPE(wdtId)); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(TIMER0_WDT_IRQn, TIMER0_WDT_IRQHandler); - Interrupt_Handler_Register(TIMER1_WDT_IRQn, TIMER1_WDT_IRQHandler); -#endif - - WDT_ENABLE_ACCESS(TIMERx); - - tmpVal = BL_RD_REG(TIMERx, TIMER_WMER); - - BL_WR_REG(TIMERx, TIMER_WMER, BL_SET_REG_BIT(tmpVal, TIMER_WE)); -} - -/****************************************************************************/ /** - * @brief Watchdog timer disable function - * - * @param wdtId: Watchdog ID type - * - * @return None - * -*******************************************************************************/ -void WDT_Disable(WDT_ID_Type wdtId) -{ - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[wdtId]; - - /* Check the parameters */ - CHECK_PARAM(IS_WDT_ID_TYPE(wdtId)); - - WDT_ENABLE_ACCESS(TIMERx); - - tmpVal = BL_RD_REG(TIMERx, TIMER_WMER); - - BL_WR_REG(TIMERx, TIMER_WMER, BL_CLR_REG_BIT(tmpVal, TIMER_WE)); -} - -/****************************************************************************/ /** - * @brief Watchdog timer disable function - * - * @param wdtId: Watchdog ID type - * - * @return None - * -*******************************************************************************/ -void WDT_ForceClockDivision(WDT_ID_Type wdtId) -{ - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[wdtId]; - - /* Check the parameters */ - CHECK_PARAM(IS_WDT_ID_TYPE(wdtId)); - - /* write 0 after write 1 to force clock division */ - tmpVal = BL_RD_REG(TIMERx, TIMER_TCDR_FORCE); - - tmpVal = BL_SET_REG_BIT(tmpVal, TIMER_WCDR_FORCE); - - BL_WR_REG(TIMERx, TIMER_TCDR_FORCE, tmpVal); - - tmpVal = BL_RD_REG(TIMERx, TIMER_TCDR_FORCE); - - tmpVal = BL_CLR_REG_BIT(tmpVal, TIMER_WCDR_FORCE); - - BL_WR_REG(TIMERx, TIMER_TCDR_FORCE, tmpVal); -} - -/****************************************************************************/ /** - * @brief Watchdog timer mask or unmask certain or all interrupt - * - * @param wdtId: Watchdog ID type - * @param intType: Watchdog interrupt type - * @param intMask: Watchdog interrupt mask value:MASK:disbale interrupt.UNMASK:enable interrupt - * - * @return None - * -*******************************************************************************/ -void WDT_IntMask(WDT_ID_Type wdtId, WDT_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[wdtId]; - - /* Check the parameters */ - CHECK_PARAM(IS_WDT_ID_TYPE(wdtId)); - CHECK_PARAM(IS_WDT_INT_TYPE(intType)); - CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); - - WDT_ENABLE_ACCESS(TIMERx); - - /* Deal with watchdog match/interrupt enable register, - WRIE:watchdog reset/interrupt enable */ - tmpVal = BL_RD_REG(TIMERx, TIMER_WMER); - - switch (intType) { - case WDT_INT: - if (intMask == UNMASK) { - /* Enable this interrupt */ - /* 0 means generates a watchdog interrupt, - a watchdog timer reset is not generated*/ - BL_WR_REG(TIMERx, TIMER_WMER, BL_CLR_REG_BIT(tmpVal, TIMER_WRIE)); - } else { - /* Disable this interrupt */ - /* 1 means generates a watchdog timer reset, - a watchdog interrupt is not generated*/ - BL_WR_REG(TIMERx, TIMER_WMER, BL_SET_REG_BIT(tmpVal, TIMER_WRIE)); - } - - break; - - default: - break; - } -} - -/****************************************************************************/ /** - * @brief Watchdog install interrupt callback - * - * @param wdtId: Watchdog ID type - * @param wdtInt: Watchdog interrupt type - * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void WDT_Int_Callback_Install(WDT_ID_Type wdtId, WDT_INT_Type wdtInt, intCallback_Type *cbFun) -{ - /* Check the parameters */ - CHECK_PARAM(IS_WDT_ID_TYPE(wdtId)); - CHECK_PARAM(IS_WDT_INT_TYPE(wdtInt)); - - wdtIntCbfArra[wdtId][wdtInt] = cbFun; -} -#endif - -/****************************************************************************/ /** - * @brief Watchdog set gpio polarity - * - * @param wdtId: Watchdog ID type - * @param polarity: Watchdog GPIO polarity - * - * @return None - * -*******************************************************************************/ -void WDT_GPIOSetPolarity(WDT_ID_Type wdtId, TIMER_GPIO_Polarity_Type polarity) -{ - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[wdtId]; - - /* Check the parameters */ - CHECK_PARAM(IS_WDT_ID_TYPE(wdtId)); - CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); - - tmpVal = BL_RD_REG(TIMERx, TIMER_GPIO); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_WDT_GPIO_INV, polarity); - BL_WR_REG(TIMERx, TIMER_GPIO, tmpVal); -} - -/****************************************************************************/ /** - * @brief TIMER0 channel 0 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void TIMER0_CH0_IRQHandler(void) -{ - TIMER_IntHandler(TIMER0_ID, TIMER_CH0); -} -#endif - -/****************************************************************************/ /** - * @brief TIMER0 channel 1 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void TIMER0_CH1_IRQHandler(void) -{ - TIMER_IntHandler(TIMER0_ID, TIMER_CH1); -} -#endif - -/****************************************************************************/ /** - * @brief TIMER0 watchdog interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void TIMER0_WDT_IRQHandler(void) -{ - uint32_t tmpVal; - - WDT_ENABLE_ACCESS(TIMER0_BASE); - - tmpVal = BL_RD_REG(TIMER0_BASE, TIMER_WICR); - BL_WR_REG(TIMER0_BASE, TIMER_WICR, BL_SET_REG_BIT(tmpVal, TIMER_WICLR)); - - if (wdtIntCbfArra[WDT0_ID][WDT_INT] != NULL) { - /* Call the callback function */ - wdtIntCbfArra[WDT0_ID][WDT_INT](); - } -} -#endif - -/****************************************************************************/ /** - * @brief TIMER1 channel 0 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void TIMER1_CH0_IRQHandler(void) -{ - TIMER_IntHandler(TIMER1_ID, TIMER_CH0); -} -#endif - -/****************************************************************************/ /** - * @brief TIMER1 channel 1 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void TIMER1_CH1_IRQHandler(void) -{ - TIMER_IntHandler(TIMER1_ID, TIMER_CH1); -} -#endif - -/****************************************************************************/ /** - * @brief TIMER1 watchdog interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void TIMER1_WDT_IRQHandler(void) -{ - uint32_t tmpVal; - - WDT_ENABLE_ACCESS(TIMER1_BASE); - - tmpVal = BL_RD_REG(TIMER1_BASE, TIMER_WICR); - BL_WR_REG(TIMER1_BASE, TIMER_WICR, BL_SET_REG_BIT(tmpVal, TIMER_WICLR)); - - if (wdtIntCbfArra[WDT1_ID][WDT_INT] != NULL) { - /* Call the callback function */ - wdtIntCbfArra[WDT1_ID][WDT_INT](); - } -} -#endif -/*@} end of group TIMER_Private_Functions */ - -/*@} end of group TIMER */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_touch.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_touch.c deleted file mode 100644 index 2cea9f2e57..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_touch.c +++ /dev/null @@ -1,906 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_touch.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_touch.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup TOUCH - * @{ - */ - -/** @defgroup TOUCH_Private_Macros - * @{ - */ - -/*@} end of group TOUCH_Private_Macros */ - -/** @defgroup TOUCH_Private_Types - * @{ - */ - -/*@} end of group TOUCH_Private_Types */ - -/** @defgroup TOUCH_Private_Variables - * @{ - */ -static intCallback_Type *touchIntCbfArra[TOUCH_INT_INTERRUPT + 1][TOUCH_CHANNEL_11 + 1] = { { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL } }; - -/*@} end of group TOUCH_Private_Variables */ - -/** @defgroup TOUCH_Global_Variables - * @{ - */ - -/*@} end of group TOUCH_Global_Variables */ - -/** @defgroup TOUCH_Private_Fun_Declaration - * @{ - */ - -/*@} end of group TOUCH_Private_Fun_Declaration */ - -/** @defgroup TOUCH_Private_Functions - * @{ - */ - -/*@} end of group TOUCH_Private_Functions */ - -/** @defgroup TOUCH_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief touch moudle init - * - * @param touchId: touch moudle ID - * @param tCfg: touch moudle config - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type TOUCH_Init(TOUCH_ID_Type touchId, TOUCH_CFG_Type *tCfg) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_TOUCH_ID_TYPE(touchId)); - CHECK_PARAM(IS_TOUCH_CLK_SEL_TYPE(tCfg->clkSel)); - CHECK_PARAM(IS_TOUCH_CLK_DIV_TYPE(tCfg->clkDiv)); - CHECK_PARAM(IS_TOUCH_POWER_SEL_TYPE(tCfg->powerSel)); - CHECK_PARAM(IS_TOUCH_WORK_MODE_TYPE(tCfg->workMode)); - CHECK_PARAM(IS_TOUCH_RUN_MODE_TYPE(tCfg->runMode)); - CHECK_PARAM((tCfg->sleepTime <= 0x7FFFFF)); - CHECK_PARAM(IS_TOUCH_PCHARGE_LOW_TYPE(tCfg->pchargeLow)); - CHECK_PARAM(IS_TOUCH_PCHARGE_HIGH_TYPE(tCfg->pchargeHigh)); - CHECK_PARAM(IS_TOUCH_LDO_VOLTAGE_TYPE(tCfg->ldoVol)); - CHECK_PARAM(IS_TOUCH_VREF_VOLTAGE_TYPE(tCfg->vrefVol)); - CHECK_PARAM(IS_TOUCH_HYSTERSIS_VOLTAGE_TYPE(tCfg->hystersisVol)); - CHECK_PARAM(IS_TOUCH_COMPENSATION_CAP_TYPE(tCfg->compensationCap)); - CHECK_PARAM(IS_TOUCH_FILTER_ORDER_CTRL_TYPE(tCfg->filterCtrl)); - CHECK_PARAM(IS_TOUCH_LTA_ORDER_CTRL_TYPE(tCfg->ltaCtrl)); - CHECK_PARAM((tCfg->dataHysCtrl <= 0x1FF)); - - /* touch1 */ - tmpVal = BL_RD_REG(PDS_BASE, PDS_TOUCH1); - - if (tCfg->powerSel == TOUCH_POWER_SEL_AON) { - /* power from AON bandgap */ - tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_TOUCH_CURRENT_SEL); - } else { - /* power from internal bandgap */ - tmpVal = BL_SET_REG_BIT(tmpVal, PDS_TOUCH_CURRENT_SEL); - } - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_ULP_EN, tCfg->ulpEn); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CYCLE_EN, tCfg->cycleEn); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CONT_EN, tCfg->runMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_PCHARGE_LOW, tCfg->pchargeLow); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_PCHARGE_HIGH, tCfg->pchargeHigh); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CLK_DIV_RATIO, tCfg->clkDiv); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CLK_SEL, tCfg->clkSel); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_COMP_HYS_SEL, tCfg->hystersisVol); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VLDO_SEL, tCfg->ldoVol); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VREF_SEL, tCfg->vrefVol); - tmpVal = BL_WR_REG(PDS_BASE, PDS_TOUCH1, tmpVal); - - /* touch3 */ - tmpVal = BL_RD_REG(PDS_BASE, PDS_TOUCH3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VLDO_CCSEL, tCfg->compensationCap); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_SELF_MUTUAL_SEL, tCfg->workMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_FLT_ORDER, tCfg->filterCtrl); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_FLT_EN, tCfg->filterEn); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_LTA_ORDER, tCfg->ltaCtrl); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_LTA_EN, tCfg->ltaEn); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_DATA_HYS_EN, tCfg->dataHystersisEn); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CHANNEL_CAL_EN, tCfg->calibrationEn); - tmpVal = BL_WR_REG(PDS_BASE, PDS_TOUCH3, tmpVal); - - /* touch_sleep_time */ - tmpVal = BL_RD_REG(PDS_BASE, PDS_TOUCH_SLEEP_TIME); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_SLEEP_CYCLE, tCfg->sleepTime); - tmpVal = BL_WR_REG(PDS_BASE, PDS_TOUCH_SLEEP_TIME, tmpVal); - - /* touch_data_hystersis */ - tmpVal = BL_RD_REG(PDS_BASE, PDS_TOUCH_DATA_HYSTERSIS); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_DATA_HYS, tCfg->dataHysCtrl); - tmpVal = BL_WR_REG(PDS_BASE, PDS_TOUCH_DATA_HYSTERSIS, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief touch moudle channel init - * - * @param touchId: touch moudle ID - * @param tChCfg: touch moudle channel config - * @param tChSel: touch moudle channel select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type TOUCH_CHANNEL_Init(TOUCH_ID_Type touchId, TOUCH_CHANNEL_CFG_Type *tChCfg, TOUCH_CHANNEL_Type tChSel) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_TOUCH_ID_TYPE(touchId)); - CHECK_PARAM(IS_TOUCH_CHANNEL_HIGHZ_CFG_TYPE(tChCfg->ch0)); - CHECK_PARAM(IS_TOUCH_CHANNEL_HIGHZ_CFG_TYPE(tChCfg->ch1)); - CHECK_PARAM(IS_TOUCH_CHANNEL_HIGHZ_CFG_TYPE(tChCfg->ch2)); - CHECK_PARAM(IS_TOUCH_CHANNEL_HIGHZ_CFG_TYPE(tChCfg->ch3)); - CHECK_PARAM(IS_TOUCH_CHANNEL_HIGHZ_CFG_TYPE(tChCfg->ch4)); - CHECK_PARAM(IS_TOUCH_CHANNEL_HIGHZ_CFG_TYPE(tChCfg->ch5)); - CHECK_PARAM(IS_TOUCH_CHANNEL_HIGHZ_CFG_TYPE(tChCfg->ch6)); - CHECK_PARAM(IS_TOUCH_CHANNEL_HIGHZ_CFG_TYPE(tChCfg->ch7)); - CHECK_PARAM(IS_TOUCH_CHANNEL_HIGHZ_CFG_TYPE(tChCfg->ch8)); - CHECK_PARAM(IS_TOUCH_CHANNEL_HIGHZ_CFG_TYPE(tChCfg->ch9)); - CHECK_PARAM(IS_TOUCH_CHANNEL_HIGHZ_CFG_TYPE(tChCfg->ch10)); - CHECK_PARAM(IS_TOUCH_CHANNEL_HIGHZ_CFG_TYPE(tChCfg->ch11)); - CHECK_PARAM(IS_TOUCH_CHANNEL_TYPE(tChSel)); - - /* touch2 */ - tmpVal = BL_RD_REG(PDS_BASE, PDS_TOUCH2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CHANNEL11_HIGHZ_EN, tChCfg->ch11); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CHANNEL10_HIGHZ_EN, tChCfg->ch10); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CHANNEL9_HIGHZ_EN, tChCfg->ch9); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CHANNEL8_HIGHZ_EN, tChCfg->ch8); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CHANNEL7_HIGHZ_EN, tChCfg->ch7); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CHANNEL6_HIGHZ_EN, tChCfg->ch6); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CHANNEL5_HIGHZ_EN, tChCfg->ch5); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CHANNEL4_HIGHZ_EN, tChCfg->ch4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CHANNEL3_HIGHZ_EN, tChCfg->ch3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CHANNEL2_HIGHZ_EN, tChCfg->ch2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CHANNEL1_HIGHZ_EN, tChCfg->ch1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CHANNEL0_HIGHZ_EN, tChCfg->ch0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CHANNEL_SEL, tChSel); - tmpVal = BL_WR_REG(PDS_BASE, PDS_TOUCH2, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief touch moudle start - * - * @param touchId: touch moudle ID - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type TOUCH_Enable(TOUCH_ID_Type touchId) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_TOUCH_ID_TYPE(touchId)); - - /* touch1 */ - tmpVal = BL_RD_REG(PDS_BASE, PDS_TOUCH1); - tmpVal = BL_SET_REG_BIT(tmpVal, PDS_PU_TOUCH); - tmpVal = BL_WR_REG(PDS_BASE, PDS_TOUCH1, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief touch moudle stop - * - * @param touchId: touch moudle ID - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type TOUCH_Disable(TOUCH_ID_Type touchId) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_TOUCH_ID_TYPE(touchId)); - - /* touch1 */ - tmpVal = BL_RD_REG(PDS_BASE, PDS_TOUCH1); - tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_PU_TOUCH); - tmpVal = BL_WR_REG(PDS_BASE, PDS_TOUCH1, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief touch moudle set V threshold value - * - * @param touchId: touch moudle ID - * @param tCh: touch moudle channel - * @param value: vth value - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type TOUCH_SetVthData(TOUCH_ID_Type touchId, TOUCH_CHANNEL_Type tCh, uint8_t value) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_TOUCH_ID_TYPE(touchId)); - CHECK_PARAM(IS_TOUCH_CHANNEL_TYPE(tCh)); - - if (tCh <= TOUCH_CHANNEL_3) { - /* channel 0 - channel 3 */ - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_VTH_DATA_0); - - switch (tCh) { - case TOUCH_CHANNEL_0: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH0, value); - break; - - case TOUCH_CHANNEL_1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH1, value); - break; - - case TOUCH_CHANNEL_2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH2, value); - break; - - case TOUCH_CHANNEL_3: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH3, value); - break; - - default: - break; - } - - tmpVal = BL_WR_REG(PDS_BASE, PDS_CHANNEL_VTH_DATA_0, tmpVal); - } else if (tCh <= TOUCH_CHANNEL_7) { - /* channel 4 - channel 7 */ - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_VTH_DATA_1); - - switch (tCh) { - case TOUCH_CHANNEL_4: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH4, value); - break; - - case TOUCH_CHANNEL_5: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH5, value); - break; - - case TOUCH_CHANNEL_6: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH6, value); - break; - - case TOUCH_CHANNEL_7: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH7, value); - break; - - default: - break; - } - - tmpVal = BL_WR_REG(PDS_BASE, PDS_CHANNEL_VTH_DATA_1, tmpVal); - } else { - /* channel 8 - channel 11 */ - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_VTH_DATA_2); - - switch (tCh) { - case TOUCH_CHANNEL_8: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH8, value); - break; - - case TOUCH_CHANNEL_9: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH9, value); - break; - - case TOUCH_CHANNEL_10: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH10, value); - break; - - case TOUCH_CHANNEL_11: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH11, value); - break; - - default: - break; - } - - tmpVal = BL_WR_REG(PDS_BASE, PDS_CHANNEL_VTH_DATA_2, tmpVal); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get touch moudle vth data - * - * @param touchId: touch moudle ID - * @param tCh: touch moudle channel - * - * @return vth data - * -*******************************************************************************/ -uint32_t TOUCH_GetVthData(TOUCH_ID_Type touchId, TOUCH_CHANNEL_Type tCh) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_TOUCH_ID_TYPE(touchId)); - CHECK_PARAM(IS_TOUCH_CHANNEL_TYPE(tCh)); - - if (tCh <= TOUCH_CHANNEL_3) { - /* channel 0 - channel 3 */ - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_VTH_DATA_0); - - switch (tCh) { - case TOUCH_CHANNEL_0: - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH0); - break; - - case TOUCH_CHANNEL_1: - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH1); - break; - - case TOUCH_CHANNEL_2: - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH2); - break; - - case TOUCH_CHANNEL_3: - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH3); - break; - - default: - break; - } - } else if (tCh <= TOUCH_CHANNEL_7) { - /* channel 4 - channel 7 */ - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_VTH_DATA_1); - - switch (tCh) { - case TOUCH_CHANNEL_4: - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH4); - break; - - case TOUCH_CHANNEL_5: - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH5); - break; - - case TOUCH_CHANNEL_6: - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH6); - break; - - case TOUCH_CHANNEL_7: - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH7); - break; - - default: - break; - } - } else { - /* channel 8 - channel 11 */ - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_VTH_DATA_2); - - switch (tCh) { - case TOUCH_CHANNEL_8: - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH8); - break; - - case TOUCH_CHANNEL_9: - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH9); - break; - - case TOUCH_CHANNEL_10: - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH10); - break; - - case TOUCH_CHANNEL_11: - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH11); - break; - - default: - break; - } - } - - return tmpVal; -} - -/****************************************************************************/ /** - * @brief get touch moudle raw data - * - * @param touchId: touch moudle ID - * @param tCh: touch moudle channel - * - * @return raw data - * -*******************************************************************************/ -uint32_t TOUCH_GetRawData(TOUCH_ID_Type touchId, TOUCH_CHANNEL_Type tCh) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_TOUCH_ID_TYPE(touchId)); - CHECK_PARAM(IS_TOUCH_CHANNEL_TYPE(tCh)); - - switch (tCh) { - case TOUCH_CHANNEL_0: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_RAW_DATA_0); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_RAW_DATA_CH0); - break; - - case TOUCH_CHANNEL_1: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_RAW_DATA_1); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_RAW_DATA_CH1); - break; - - case TOUCH_CHANNEL_2: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_RAW_DATA_2); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_RAW_DATA_CH2); - break; - - case TOUCH_CHANNEL_3: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_RAW_DATA_3); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_RAW_DATA_CH3); - break; - - case TOUCH_CHANNEL_4: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_RAW_DATA_4); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_RAW_DATA_CH4); - break; - - case TOUCH_CHANNEL_5: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_RAW_DATA_5); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_RAW_DATA_CH5); - break; - - case TOUCH_CHANNEL_6: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_RAW_DATA_6); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_RAW_DATA_CH6); - break; - - case TOUCH_CHANNEL_7: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_RAW_DATA_7); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_RAW_DATA_CH7); - break; - - case TOUCH_CHANNEL_8: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_RAW_DATA_8); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_RAW_DATA_CH8); - break; - - case TOUCH_CHANNEL_9: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_RAW_DATA_9); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_RAW_DATA_CH9); - break; - - case TOUCH_CHANNEL_10: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_RAW_DATA_10); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_RAW_DATA_CH10); - break; - - case TOUCH_CHANNEL_11: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_RAW_DATA_11); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_RAW_DATA_CH11); - break; - } - - return tmpVal; -} - -/****************************************************************************/ /** - * @brief get touch moudle LTA data - * - * @param touchId: touch moudle ID - * @param tCh: touch moudle channel - * - * @return LTA data - * -*******************************************************************************/ -uint32_t TOUCH_GetLtaData(TOUCH_ID_Type touchId, TOUCH_CHANNEL_Type tCh) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_TOUCH_ID_TYPE(touchId)); - CHECK_PARAM(IS_TOUCH_CHANNEL_TYPE(tCh)); - - switch (tCh) { - case TOUCH_CHANNEL_0: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_LTA_DATA_0); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_LTA_DATA_CH0); - break; - - case TOUCH_CHANNEL_1: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_LTA_DATA_1); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_LTA_DATA_CH1); - break; - - case TOUCH_CHANNEL_2: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_LTA_DATA_2); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_LTA_DATA_CH2); - break; - - case TOUCH_CHANNEL_3: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_LTA_DATA_3); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_LTA_DATA_CH3); - break; - - case TOUCH_CHANNEL_4: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_LTA_DATA_4); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_LTA_DATA_CH4); - break; - - case TOUCH_CHANNEL_5: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_LTA_DATA_5); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_LTA_DATA_CH5); - break; - - case TOUCH_CHANNEL_6: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_LTA_DATA_6); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_LTA_DATA_CH6); - break; - - case TOUCH_CHANNEL_7: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_LTA_DATA_7); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_LTA_DATA_CH7); - break; - - case TOUCH_CHANNEL_8: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_LTA_DATA_8); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_LTA_DATA_CH8); - break; - - case TOUCH_CHANNEL_9: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_LTA_DATA_9); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_LTA_DATA_CH9); - break; - - case TOUCH_CHANNEL_10: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_LTA_DATA_10); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_LTA_DATA_CH10); - break; - - case TOUCH_CHANNEL_11: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_LTA_DATA_11); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_LTA_DATA_CH11); - break; - } - - return tmpVal; -} - -/****************************************************************************/ /** - * @brief get touch moudle FLT data - * - * @param touchId: touch moudle ID - * @param tCh: touch moudle channel - * - * @return FLT data - * -*******************************************************************************/ -uint32_t TOUCH_GetFltData(TOUCH_ID_Type touchId, TOUCH_CHANNEL_Type tCh) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_TOUCH_ID_TYPE(touchId)); - CHECK_PARAM(IS_TOUCH_CHANNEL_TYPE(tCh)); - - switch (tCh) { - case TOUCH_CHANNEL_0: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_FLT_DATA_0); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_FLT_DATA_CH0); - break; - - case TOUCH_CHANNEL_1: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_FLT_DATA_1); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_FLT_DATA_CH1); - break; - - case TOUCH_CHANNEL_2: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_FLT_DATA_2); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_FLT_DATA_CH2); - break; - - case TOUCH_CHANNEL_3: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_FLT_DATA_3); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_FLT_DATA_CH3); - break; - - case TOUCH_CHANNEL_4: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_FLT_DATA_4); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_FLT_DATA_CH4); - break; - - case TOUCH_CHANNEL_5: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_FLT_DATA_5); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_FLT_DATA_CH5); - break; - - case TOUCH_CHANNEL_6: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_FLT_DATA_6); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_FLT_DATA_CH6); - break; - - case TOUCH_CHANNEL_7: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_FLT_DATA_7); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_FLT_DATA_CH7); - break; - - case TOUCH_CHANNEL_8: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_FLT_DATA_8); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_FLT_DATA_CH8); - break; - - case TOUCH_CHANNEL_9: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_FLT_DATA_9); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_FLT_DATA_CH9); - break; - - case TOUCH_CHANNEL_10: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_FLT_DATA_10); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_FLT_DATA_CH10); - break; - - case TOUCH_CHANNEL_11: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_FLT_DATA_11); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_FLT_DATA_CH11); - break; - } - - return tmpVal; -} - -/****************************************************************************/ /** - * @brief get touch end flag - * - * @param touchId: touch moudle ID - * - * @return SET or RESET - * -*******************************************************************************/ -BL_Sts_Type TOUCH_GetEndStatus(TOUCH_ID_Type touchId) -{ - CHECK_PARAM(IS_TOUCH_ID_TYPE(touchId)); - - return BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_TOUCH_INT_STATUS), PDS_TOUCH_END_FLAG) ? SET : RESET; -} - -/****************************************************************************/ /** - * @brief touch interrupt enable - * - * @param touchId: touch moudle ID - * @param intType: touch moudle interrupt type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type TOUCH_IntEnable(TOUCH_ID_Type touchId, TOUCH_INT_Type intType) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_TOUCH_ID_TYPE(touchId)); - CHECK_PARAM(IS_TOUCH_INT_TYPE(intType)); - - tmpVal = BL_RD_REG(PDS_BASE, PDS_TOUCH_INT_SETTING); - tmpVal = BL_SET_REG_BIT(tmpVal, PDS_TOUCH_INT_EN); - tmpVal = BL_WR_REG(PDS_BASE, PDS_TOUCH_INT_SETTING, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief touch interrupt disable - * - * @param touchId: touch moudle ID - * @param intType: touch moudle interrupt type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type TOUCH_IntDisable(TOUCH_ID_Type touchId, TOUCH_INT_Type intType) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_TOUCH_ID_TYPE(touchId)); - CHECK_PARAM(IS_TOUCH_INT_TYPE(intType)); - - tmpVal = BL_RD_REG(PDS_BASE, PDS_TOUCH_INT_SETTING); - tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_TOUCH_INT_EN); - tmpVal = BL_WR_REG(PDS_BASE, PDS_TOUCH_INT_SETTING, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief touch interrupt mask or not - * - * @param touchId: touch moudle ID - * @param intType: touch moudle interrupt type - * @param tCh: touch moudle channel - * @param intMask: MASK or UNMASK - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type TOUCH_IntMask(TOUCH_ID_Type touchId, TOUCH_INT_Type intType, TOUCH_CHANNEL_Type tCh, BL_Mask_Type intMask) -{ - uint32_t tmpVal = 0; - uint32_t tmpMask = 0; - - CHECK_PARAM(IS_TOUCH_ID_TYPE(touchId)); - CHECK_PARAM(IS_TOUCH_INT_TYPE(intType)); - CHECK_PARAM(IS_TOUCH_CHANNEL_TYPE(tCh)); - - TOUCH_IntEnable(touchId, intType); - - tmpVal = BL_RD_REG(PDS_BASE, PDS_TOUCH_INT_SETTING); - - if (intMask == MASK) { - tmpMask = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_INT_MASK); - tmpMask |= (1 << tCh); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_INT_MASK, tmpMask); - } else { - tmpMask = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_INT_MASK); - tmpMask &= (~(1 << tCh)); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_INT_MASK, tmpMask); - } - - tmpVal = BL_WR_REG(PDS_BASE, PDS_TOUCH_INT_SETTING, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get touch interrupt status - * - * @param touchId: touch moudle ID - * @param intType: touch moudle interrupt type - * @param tCh: touch moudle channel - * - * @return SET or RESET - * -*******************************************************************************/ -BL_Sts_Type TOUCH_GetIntStatus(TOUCH_ID_Type touchId, TOUCH_INT_Type intType, TOUCH_CHANNEL_Type tCh) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_TOUCH_ID_TYPE(touchId)); - CHECK_PARAM(IS_TOUCH_INT_TYPE(intType)); - CHECK_PARAM(IS_TOUCH_CHANNEL_TYPE(tCh)); - - tmpVal = BL_RD_REG(PDS_BASE, PDS_TOUCH_INT_STATUS); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_INT_STATUS); - - if (tmpVal & (1 << tCh)) { - return SET; - } else { - return RESET; - } -} - -/****************************************************************************/ /** - * @brief clear touch interrupt status - * - * @param touchId: touch moudle ID - * @param intType: touch moudle interrupt type - * @param tCh: touch moudle channel - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type TOUCH_ClrIntStatus(TOUCH_ID_Type touchId, TOUCH_INT_Type intType, TOUCH_CHANNEL_Type tCh) -{ - uint32_t tmpVal = 0; - uint32_t tmpClr = 0; - - CHECK_PARAM(IS_TOUCH_ID_TYPE(touchId)); - CHECK_PARAM(IS_TOUCH_INT_TYPE(intType)); - CHECK_PARAM(IS_TOUCH_CHANNEL_TYPE(tCh)); - - /* set */ - tmpVal = BL_RD_REG(PDS_BASE, PDS_TOUCH_INT_SETTING); - tmpClr = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_INT_CLR); - tmpClr |= (1 << tCh); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_INT_CLR, tmpClr); - tmpVal = BL_WR_REG(PDS_BASE, PDS_TOUCH_INT_SETTING, tmpVal); - - /* unset */ - tmpVal = BL_RD_REG(PDS_BASE, PDS_TOUCH_INT_SETTING); - tmpClr = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_INT_CLR); - tmpClr &= (~(1 << tCh)); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_INT_CLR, tmpClr); - tmpVal = BL_WR_REG(PDS_BASE, PDS_TOUCH_INT_SETTING, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief install touch interrupt callback - * - * @param touchId: touch moudle ID - * @param intType: touch moudle interrupt type - * @param tCh: touch moudle channel - * @param cbFun: callback function - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type TOUCH_INT_Callback_Install(TOUCH_ID_Type touchId, TOUCH_INT_Type intType, TOUCH_CHANNEL_Type tCh, intCallback_Type *cbFun) -{ - CHECK_PARAM(IS_TOUCH_INT_TYPE(intType)); - - touchIntCbfArra[intType][tCh] = cbFun; - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief touch IRQ handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -void TOUCH_IRQHandler(void) -{ - TOUCH_CHANNEL_Type tmpCh; - - for (tmpCh = TOUCH_CHANNEL_0; tmpCh <= TOUCH_CHANNEL_11; tmpCh++) { - if (SET == TOUCH_GetIntStatus(TOUCH_ID_0, TOUCH_INT_INTERRUPT, tmpCh)) { - TOUCH_ClrIntStatus(TOUCH_ID_0, TOUCH_INT_INTERRUPT, tmpCh); - - if (touchIntCbfArra[TOUCH_INT_INTERRUPT][tmpCh] != NULL) { - touchIntCbfArra[TOUCH_INT_INTERRUPT][tmpCh](); - } - } - } -} - -/*@} end of group TOUCH_Public_Functions */ - -/*@} end of group TOUCH */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_uart.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_uart.c deleted file mode 100644 index 1b228b6f01..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_uart.c +++ /dev/null @@ -1,1471 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_uart.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_uart.h" -#include "bl808_glb.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup UART - * @{ - */ - -/** @defgroup UART_Private_Macros - * @{ - */ -#define UART_TX_TIMEOUT_COUNT (320 * 1000) - -/*@} end of group UART_Private_Macros */ - -/** @defgroup UART_Private_Types - * @{ - */ - -/*@} end of group UART_Private_Types */ - -/** @defgroup UART_Private_Variables - * @{ - */ -static const uint32_t uartAddr[UART_ID_MAX] = { UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE }; -#if (defined BOOTROM) || (!defined BFLB_USE_HAL_DRIVER) -static intCallback_Type *uartIntCbfArra[UART_ID_MAX][UART_INT_ALL] = { - { NULL } -}; -#endif - -/*@} end of group UART_Private_Variables */ - -/** @defgroup UART_Global_Variables - * @{ - */ - -/*@} end of group UART_Global_Variables */ - -/** @defgroup UART_Private_Fun_Declaration - * @{ - */ -#if (defined BOOTROM) || (!defined BFLB_USE_HAL_DRIVER) -static void UART_IntHandler(UART_ID_Type uartId); -#endif - -/*@} end of group UART_Private_Fun_Declaration */ - -/** @defgroup UART_Private_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief UART interrupt common handler function - * - * @param uartId: UART ID type - * - * @return None - * -*******************************************************************************/ -#if (defined BOOTROM) || (!defined BFLB_USE_HAL_DRIVER) -static void UART_IntHandler(UART_ID_Type uartId) -{ - uint32_t tmpVal = 0; - uint32_t maskVal = 0; - uint32_t UARTx = uartAddr[uartId]; - - tmpVal = BL_RD_REG(UARTx, UART_INT_STS); - maskVal = BL_RD_REG(UARTx, UART_INT_MASK); - - /* Length of uart tx data transfer arrived interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_END_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_END_MASK)) { - BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_UTX_END_CLR_POS); - - if (uartIntCbfArra[uartId][UART_INT_TX_END] != NULL) { - uartIntCbfArra[uartId][UART_INT_TX_END](); - } - } - - /* Length of uart rx data transfer arrived interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_END_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_END_MASK)) { - BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_END_CLR_POS); - - if (uartIntCbfArra[uartId][UART_INT_RX_END] != NULL) { - uartIntCbfArra[uartId][UART_INT_RX_END](); - } - } - - /* Tx fifo ready interrupt,auto-cleared when data is pushed */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_FRDY_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_FRDY_MASK)) { - if (uartIntCbfArra[uartId][UART_INT_TX_FIFO_REQ] != NULL) { - uartIntCbfArra[uartId][UART_INT_TX_FIFO_REQ](); - } - } - - /* Rx fifo ready interrupt,auto-cleared when data is popped */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_FRDY_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_FRDY_MASK)) { - if (uartIntCbfArra[uartId][UART_INT_RX_FIFO_REQ] != NULL) { - uartIntCbfArra[uartId][UART_INT_RX_FIFO_REQ](); - } - } - - /* Rx time-out interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_RTO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_RTO_MASK)) { - BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_RTO_CLR_POS); - - if (uartIntCbfArra[uartId][UART_INT_RTO] != NULL) { - uartIntCbfArra[uartId][UART_INT_RTO](); - } - } - - /* Rx parity check error interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_PCE_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_PCE_MASK)) { - BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_PCE_CLR_POS); - - if (uartIntCbfArra[uartId][UART_INT_PCE] != NULL) { - uartIntCbfArra[uartId][UART_INT_PCE](); - } - } - - /* Tx fifo overflow/underflow error interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_FER_MASK)) { - if (uartIntCbfArra[uartId][UART_INT_TX_FER] != NULL) { - uartIntCbfArra[uartId][UART_INT_TX_FER](); - } - } - - /* Rx fifo overflow/underflow error interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_FER_MASK)) { - if (uartIntCbfArra[uartId][UART_INT_RX_FER] != NULL) { - uartIntCbfArra[uartId][UART_INT_RX_FER](); - } - } - - /* Rx lin mode sync field error interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_LSE_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_LSE_MASK)) { - BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_LSE_CLR_POS); - - if (uartIntCbfArra[uartId][UART_INT_LSE] != NULL) { - uartIntCbfArra[uartId][UART_INT_LSE](); - } - } - - /* Rx byte count reached interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_BCR_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_BCR_MASK)) { - BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_BCR_CLR_POS); - - if (uartIntCbfArra[uartId][UART_INT_BCR] != NULL) { - uartIntCbfArra[uartId][UART_INT_BCR](); - } - } - - /* Rx auto baud rate detection finish interrupt using start bit */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_ADS_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_ADS_MASK)) { - BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_ADS_CLR_POS); - - if (uartIntCbfArra[uartId][UART_INT_STARTBIT] != NULL) { - uartIntCbfArra[uartId][UART_INT_STARTBIT](); - } - } - - /* Rx auto baud rate detection finish interrupt using codeword 0x55 */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_AD5_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_AD5_MASK)) { - BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_AD5_CLR_POS); - - if (uartIntCbfArra[uartId][UART_INT_0X55] != NULL) { - uartIntCbfArra[uartId][UART_INT_0X55](); - } - } -} -#endif - -/*@} end of group UART_Private_Functions */ - -/** @defgroup UART_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief UART set baud rate function - * - * @param uartId: UART ID type - * @param baudRate: baudRate need to set - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type UART_SetBaudRate(UART_ID_Type uartId, uint32_t baudRate) -{ - uint32_t uartClk= 0; - uint32_t fraction = 0; - uint32_t baudRateDivisor = 0; - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Get uart clk */ - if (uartId == UART0_ID || uartId == UART1_ID || uartId == UART2_ID) { - uartClk = Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_UART0); - } else if (uartId == UART0_MM_ID) { - uartClk = Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_UART3); - } else { - return ERROR; - } - - /* Cal the baud rate divisor */ - fraction = uartClk * 10 / baudRate % 10; - baudRateDivisor = uartClk / baudRate; - - if (fraction >= 5) { - ++baudRateDivisor; - } - - /* Set the baud rate register value */ - BL_WR_REG(UARTx, UART_BIT_PRD, ((baudRateDivisor - 1) << 0x10) | ((baudRateDivisor - 1) & 0xFFFF)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART initialization function - * - * @param uartId: UART ID type - * @param uartCfg: UART configuration structure pointer - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_Init(UART_ID_Type uartId, UART_CFG_Type *uartCfg) -{ - uint32_t tmpValTxCfg = 0; - uint32_t tmpValRxCfg = 0; - uint32_t fraction = 0; - uint32_t baudRateDivisor = 0; - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - CHECK_PARAM(IS_UART_PARITY_TYPE(uartCfg->parity)); - CHECK_PARAM(IS_UART_DATABITS_TYPE(uartCfg->dataBits)); - CHECK_PARAM(IS_UART_STOPBITS_TYPE(uartCfg->stopBits)); - CHECK_PARAM(IS_UART_BYTEBITINVERSE_TYPE(uartCfg->byteBitInverse)); - - /* Disable clock gate when use UART2 */ - if(uartId == UART2_ID){ - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_UART2); - } - - /* Cal the baud rate divisor */ - fraction = uartCfg->uartClk * 10 / uartCfg->baudRate % 10; - baudRateDivisor = uartCfg->uartClk / uartCfg->baudRate; - - if (fraction >= 5) { - ++baudRateDivisor; - } - - /* Set the baud rate register value */ - BL_WR_REG(UARTx, UART_BIT_PRD, ((baudRateDivisor - 1) << 0x10) | ((baudRateDivisor - 1) & 0xFFFF)); - - /* Configure parity type */ - tmpValTxCfg = BL_RD_REG(UARTx, UART_UTX_CONFIG); - tmpValRxCfg = BL_RD_REG(UARTx, UART_URX_CONFIG); - - switch (uartCfg->parity) { - case UART_PARITY_NONE: - tmpValTxCfg = BL_CLR_REG_BIT(tmpValTxCfg, UART_CR_UTX_PRT_EN); - tmpValRxCfg = BL_CLR_REG_BIT(tmpValRxCfg, UART_CR_URX_PRT_EN); - break; - - case UART_PARITY_ODD: - tmpValTxCfg = BL_SET_REG_BIT(tmpValTxCfg, UART_CR_UTX_PRT_EN); - tmpValTxCfg = BL_SET_REG_BIT(tmpValTxCfg, UART_CR_UTX_PRT_SEL); - tmpValRxCfg = BL_SET_REG_BIT(tmpValRxCfg, UART_CR_URX_PRT_EN); - tmpValRxCfg = BL_SET_REG_BIT(tmpValRxCfg, UART_CR_URX_PRT_SEL); - break; - - case UART_PARITY_EVEN: - tmpValTxCfg = BL_SET_REG_BIT(tmpValTxCfg, UART_CR_UTX_PRT_EN); - tmpValTxCfg = BL_CLR_REG_BIT(tmpValTxCfg, UART_CR_UTX_PRT_SEL); - tmpValRxCfg = BL_SET_REG_BIT(tmpValRxCfg, UART_CR_URX_PRT_EN); - tmpValRxCfg = BL_CLR_REG_BIT(tmpValRxCfg, UART_CR_URX_PRT_SEL); - break; - - default: - break; - } - - /* Configure data bits */ - tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg, UART_CR_UTX_BIT_CNT_D, (uartCfg->dataBits + 4)); - tmpValRxCfg = BL_SET_REG_BITS_VAL(tmpValRxCfg, UART_CR_URX_BIT_CNT_D, (uartCfg->dataBits + 4)); - - /* Configure tx stop bits */ - tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg, UART_CR_UTX_BIT_CNT_P, uartCfg->stopBits); - - /* Configure tx cts flow control function */ - tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg, UART_CR_UTX_CTS_EN, uartCfg->ctsFlowControl); - - /* Configure rx input de-glitch function */ - tmpValRxCfg = BL_SET_REG_BITS_VAL(tmpValRxCfg, UART_CR_URX_DEG_EN, uartCfg->rxDeglitch); - - /* Configure tx lin mode function */ - tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg, UART_CR_UTX_LIN_EN, uartCfg->txLinMode); - - /* Configure rx lin mode function */ - tmpValRxCfg = BL_SET_REG_BITS_VAL(tmpValRxCfg, UART_CR_URX_LIN_EN, uartCfg->rxLinMode); - - /* Set tx break bit count for lin protocol */ - tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg, UART_CR_UTX_BIT_CNT_B, uartCfg->txBreakBitCnt); - - /* Write back */ - BL_WR_REG(UARTx, UART_UTX_CONFIG, tmpValTxCfg); - BL_WR_REG(UARTx, UART_URX_CONFIG, tmpValRxCfg); - - /* Configure LSB-first or MSB-first */ - tmpValTxCfg = BL_RD_REG(UARTx, UART_DATA_CONFIG); - - if (UART_MSB_FIRST == uartCfg->byteBitInverse) { - tmpValTxCfg = BL_SET_REG_BIT(tmpValTxCfg, UART_CR_UART_BIT_INV); - } else { - tmpValTxCfg = BL_CLR_REG_BIT(tmpValTxCfg, UART_CR_UART_BIT_INV); - } - - BL_WR_REG(UARTx, UART_DATA_CONFIG, tmpValTxCfg); - - tmpValTxCfg = BL_RD_REG(UARTx, UART_SW_MODE); - /* Configure rx rts output SW control mode */ - tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg, UART_CR_URX_RTS_SW_MODE, uartCfg->rtsSoftwareControl); - /* Configure tx output SW control mode */ - tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg, UART_CR_UTX_TXD_SW_MODE, uartCfg->txSoftwareControl); - BL_WR_REG(UARTx, UART_SW_MODE, tmpValTxCfg); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(UART0_IRQn, UART0_IRQHandler); - Interrupt_Handler_Register(UART1_IRQn, UART1_IRQHandler); - Interrupt_Handler_Register(UART2_IRQn, UART2_IRQHandler); - Interrupt_Handler_Register(UART3_IRQn, UART3_IRQHandler); -#endif - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART set default value of all registers function - * - * @param uartId: UART ID type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_DeInit(UART_ID_Type uartId) -{ - switch(uartId){ - case UART0_ID: - GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_UART0); - break; - case UART1_ID: - GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_UART1); - break; - case UART2_ID: - GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_UART2); - break; - case UART0_MM_ID: - GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_UART0); - break; - default: - break; - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART configure fifo function - * - * @param uartId: UART ID type - * @param fifoCfg: FIFO configuration structure pointer - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_FifoConfig(UART_ID_Type uartId, UART_FifoCfg_Type *fifoCfg) -{ - uint32_t tmpVal = 0; - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Deal with uart fifo configure register */ - tmpVal = BL_RD_REG(UARTx, UART_FIFO_CONFIG_1); - /* Configure dma tx fifo threshold */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_TX_FIFO_TH, fifoCfg->txFifoDmaThreshold); - /* Configure dma rx fifo threshold */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_RX_FIFO_TH, fifoCfg->rxFifoDmaThreshold); - /* Write back */ - BL_WR_REG(UARTx, UART_FIFO_CONFIG_1, tmpVal); - - /* Enable or disable uart fifo dma function */ - tmpVal = BL_RD_REG(UARTx, UART_FIFO_CONFIG_0); - - if (ENABLE == fifoCfg->txFifoDmaEnable) { - tmpVal = BL_SET_REG_BIT(tmpVal, UART_DMA_TX_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, UART_DMA_TX_EN); - } - - if (ENABLE == fifoCfg->rxFifoDmaEnable) { - tmpVal = BL_SET_REG_BIT(tmpVal, UART_DMA_RX_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, UART_DMA_RX_EN); - } - - BL_WR_REG(UARTx, UART_FIFO_CONFIG_0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART configure infra function - * - * @param uartId: UART ID type - * @param irCfg: IR configuration structure pointer - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_IrConfig(UART_ID_Type uartId, UART_IrCfg_Type *irCfg) -{ - uint32_t tmpVal = 0; - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Configure tx ir mode */ - tmpVal = BL_RD_REG(UARTx, UART_UTX_CONFIG); - - if (ENABLE == irCfg->txIrEnable) { - tmpVal = BL_SET_REG_BIT(tmpVal, UART_CR_UTX_IR_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, UART_CR_UTX_IR_EN); - } - - if (ENABLE == irCfg->txIrInverse) { - tmpVal = BL_SET_REG_BIT(tmpVal, UART_CR_UTX_IR_INV); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, UART_CR_UTX_IR_INV); - } - - BL_WR_REG(UARTx, UART_UTX_CONFIG, tmpVal); - - /* Configure rx ir mode */ - tmpVal = BL_RD_REG(UARTx, UART_URX_CONFIG); - - if (ENABLE == irCfg->rxIrEnable) { - tmpVal = BL_SET_REG_BIT(tmpVal, UART_CR_URX_IR_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, UART_CR_URX_IR_EN); - } - - if (ENABLE == irCfg->rxIrInverse) { - tmpVal = BL_SET_REG_BIT(tmpVal, UART_CR_URX_IR_INV); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, UART_CR_URX_IR_INV); - } - - BL_WR_REG(UARTx, UART_URX_CONFIG, tmpVal); - - /* Configure tx ir pulse start and stop position */ - BL_WR_REG(UARTx, UART_UTX_IR_POSITION, irCfg->txIrPulseStop << 0x10 | irCfg->txIrPulseStart); - - /* Configure rx ir pulse start position */ - BL_WR_REG(UARTx, UART_URX_IR_POSITION, irCfg->rxIrPulseStart); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Enable UART - * - * @param uartId: UART ID type - * @param direct: UART direction type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_Enable(UART_ID_Type uartId, UART_Direction_Type direct) -{ - uint32_t tmpVal = 0; - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - CHECK_PARAM(IS_UART_DIRECTION_TYPE(direct)); - - if (direct == UART_TX || direct == UART_TXRX) { - /* Enable UART tx unit */ - tmpVal = BL_RD_REG(UARTx, UART_UTX_CONFIG); - BL_WR_REG(UARTx, UART_UTX_CONFIG, BL_SET_REG_BIT(tmpVal, UART_CR_UTX_EN)); - } - - if (direct == UART_RX || direct == UART_TXRX) { - /* Enable UART rx unit */ - tmpVal = BL_RD_REG(UARTx, UART_URX_CONFIG); - BL_WR_REG(UARTx, UART_URX_CONFIG, BL_SET_REG_BIT(tmpVal, UART_CR_URX_EN)); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Disable UART - * - * @param uartId: UART ID type - * @param direct: UART direction type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_Disable(UART_ID_Type uartId, UART_Direction_Type direct) -{ - uint32_t tmpVal = 0; - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - CHECK_PARAM(IS_UART_DIRECTION_TYPE(direct)); - - if (direct == UART_TX || direct == UART_TXRX) { - /* Disable UART tx unit */ - tmpVal = BL_RD_REG(UARTx, UART_UTX_CONFIG); - BL_WR_REG(UARTx, UART_UTX_CONFIG, BL_CLR_REG_BIT(tmpVal, UART_CR_UTX_EN)); - } - - if (direct == UART_RX || direct == UART_TXRX) { - /* Disable UART rx unit */ - tmpVal = BL_RD_REG(UARTx, UART_URX_CONFIG); - BL_WR_REG(UARTx, UART_URX_CONFIG, BL_CLR_REG_BIT(tmpVal, UART_CR_URX_EN)); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART set length of tx data transfer,tx end interrupt will assert when this length is - * reached - * - * @param uartId: UART ID type - * @param length: Length of data (unit:character/byte) - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_SetTxDataLength(UART_ID_Type uartId, uint16_t length) -{ - uint32_t tmpVal = 0; - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Set length */ - tmpVal = BL_RD_REG(UARTx, UART_UTX_CONFIG); - BL_WR_REG(UARTx, UART_UTX_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, UART_CR_UTX_LEN, length - 1)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART set length of rx data transfer,rx end interrupt will assert when this length is - * reached - * - * @param uartId: UART ID type - * @param length: Length of data (unit:character/byte) - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_SetRxDataLength(UART_ID_Type uartId, uint16_t length) -{ - uint32_t tmpVal = 0; - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Set length */ - tmpVal = BL_RD_REG(UARTx, UART_URX_CONFIG); - BL_WR_REG(UARTx, UART_URX_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, UART_CR_URX_LEN, length - 1)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART set rx time-out value for triggering RTO interrupt - * - * @param uartId: UART ID type - * @param time: Time-out value (unit:bit time) - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_SetRxTimeoutValue(UART_ID_Type uartId, uint8_t time) -{ - uint32_t UARTx = uartAddr[uartId]; - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Set time-out value */ - tmpVal = BL_RD_REG(UARTx, UART_URX_RTO_TIMER); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_CR_URX_RTO_VALUE, time - 1); - BL_WR_REG(UARTx, UART_URX_RTO_TIMER, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART set byte count value for bcr interrupt - * - * @param uartId: UART ID type - * @param count: Byte count - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_SetRxByteCount(UART_ID_Type uartId, uint16_t count) -{ - uint32_t UARTx = uartAddr[uartId]; - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Set count value */ - tmpVal = BL_RD_REG(UARTx, UART_URX_BCR_INT_CFG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_CR_URX_BCR_VALUE, count); - BL_WR_REG(UARTx, UART_URX_BCR_INT_CFG, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART set de-glitch function cycle count value - * - * @param uartId: UART ID type - * @param deglitchCnt: De-glitch function cycle count - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_SetDeglitchCount(UART_ID_Type uartId, uint8_t deglitchCnt) -{ - uint32_t UARTx = uartAddr[uartId]; - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Set count value */ - tmpVal = BL_RD_REG(UARTx, UART_URX_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_CR_URX_DEG_CNT, deglitchCnt); - BL_WR_REG(UARTx, UART_URX_CONFIG, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART set tx and rx baudrate according to auto baudrate detection value - * - * @param uartId: UART ID type - * @param autoBaudDet: Choose detection value using codeword 0x55 or start bit - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_ApplyAbrResult(UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet) -{ - uint32_t UARTx = uartAddr[uartId]; - uint16_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Get detection value */ - tmpVal = UART_GetAutoBaudCount(uartId, autoBaudDet); - - /* Set tx baudrate */ - BL_WR_REG(UARTx, UART_BIT_PRD, tmpVal << 0x10 | tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART set rx rts output software control value - * - * @param uartId: UART ID type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_SetRtsValue(UART_ID_Type uartId) -{ - uint32_t UARTx = uartAddr[uartId]; - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Rts set 1*/ - tmpVal = BL_RD_REG(UARTx, UART_SW_MODE); - BL_WR_REG(UARTx, UART_SW_MODE, BL_SET_REG_BIT(tmpVal, UART_CR_URX_RTS_SW_VAL)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART clear rx rts output software control value - * - * @param uartId: UART ID type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_ClrRtsValue(UART_ID_Type uartId) -{ - uint32_t UARTx = uartAddr[uartId]; - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Rts clear 0 */ - tmpVal = BL_RD_REG(UARTx, UART_SW_MODE); - BL_WR_REG(UARTx, UART_SW_MODE, BL_CLR_REG_BIT(tmpVal, UART_CR_URX_RTS_SW_VAL)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART set tx output software control value - * - * @param uartId: UART ID type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_SetTxValue(UART_ID_Type uartId) -{ - uint32_t UARTx = uartAddr[uartId]; - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Tx set 1*/ - tmpVal = BL_RD_REG(UARTx, UART_SW_MODE); - BL_WR_REG(UARTx, UART_SW_MODE, BL_SET_REG_BIT(tmpVal, UART_CR_UTX_TXD_SW_VAL)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART clear tx output software control value - * - * @param uartId: UART ID type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_ClrTxValue(UART_ID_Type uartId) -{ - uint32_t UARTx = uartAddr[uartId]; - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Rts clear 0 */ - tmpVal = BL_RD_REG(UARTx, UART_SW_MODE); - BL_WR_REG(UARTx, UART_SW_MODE, BL_CLR_REG_BIT(tmpVal, UART_CR_UTX_TXD_SW_VAL)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART configure tx free run mode function - * - * @param uartId: UART ID type - * @param txFreeRun: Enable or disable tx free run mode - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_TxFreeRun(UART_ID_Type uartId, BL_Fun_Type txFreeRun) -{ - uint32_t tmpVal = 0; - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Enable or disable tx free run mode */ - tmpVal = BL_RD_REG(UARTx, UART_UTX_CONFIG); - - if (ENABLE == txFreeRun) { - BL_WR_REG(UARTx, UART_UTX_CONFIG, BL_SET_REG_BIT(tmpVal, UART_CR_UTX_FRM_EN)); - } else { - BL_WR_REG(UARTx, UART_UTX_CONFIG, BL_CLR_REG_BIT(tmpVal, UART_CR_UTX_FRM_EN)); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART configure auto baud rate detection function - * - * @param uartId: UART ID type - * @param autoBaud: Enable or disable auto function - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_AutoBaudDetection(UART_ID_Type uartId, BL_Fun_Type autoBaud) -{ - uint32_t tmpVal = 0; - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Enable or disable auto baud rate detection function */ - tmpVal = BL_RD_REG(UARTx, UART_URX_CONFIG); - - if (ENABLE == autoBaud) { - BL_WR_REG(UARTx, UART_URX_CONFIG, BL_SET_REG_BIT(tmpVal, UART_CR_URX_ABR_EN)); - } else { - BL_WR_REG(UARTx, UART_URX_CONFIG, BL_CLR_REG_BIT(tmpVal, UART_CR_URX_ABR_EN)); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART auto baud rate detection pulse width allowable error for using codeword 0x55 - * - * @param uartId: UART ID type - * @param allowableError: Pulse width allowable error - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_SetAllowableError0X55(UART_ID_Type uartId, uint8_t allowableError) -{ - uint32_t tmpVal = 0; - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameter */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - tmpVal = BL_RD_REG(UARTx, UART_URX_ABR_PW_TOL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_CR_URX_ABR_PW_TOL, allowableError); - BL_WR_REG(UARTx, UART_URX_ABR_PW_TOL, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART get bit width of auto baud rate detection for using codeword 0x55 - * - * @param uartId: UART ID type - * @param width: Buffer to save bit width, length:8 - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_GetBitWidth0X55(UART_ID_Type uartId, uint16_t *width) -{ - uint32_t i; - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameter */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - for (i = 0; i < 4; i++) { - width[2 * i] = (uint16_t)BL_RD_WORD(UARTx + UART_URX_ABR_PRD_B01_OFFSET + 4 * i); - width[2 * i + 1] = (uint16_t)(BL_RD_WORD(UARTx + UART_URX_ABR_PRD_B01_OFFSET + 4 * i) >> 16); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART set RS-485 trans ceiver mode - * - * @param uartId: UART ID type - * @param enable: Enable or disable RS-485 mode - * @param polarity: Set DE polarity, active-low or active-high - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_SetRS485(UART_ID_Type uartId, BL_Fun_Type enable, UART_RS485Polarity_Type polarity) -{ - uint32_t tmpVal; - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameter */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - tmpVal = BL_RD_REG(UARTx, UART_UTX_RS485_CFG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_CR_UTX_RS485_EN, enable); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_CR_UTX_RS485_POL, polarity); - BL_WR_REG(UARTx, UART_UTX_RS485_CFG, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART tx fifo clear - * - * @param uartId: UART ID type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_TxFifoClear(UART_ID_Type uartId) -{ - uint32_t tmpVal = 0; - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameter */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Clear tx fifo */ - tmpVal = BL_RD_REG(UARTx, UART_FIFO_CONFIG_0); - BL_WR_REG(UARTx, UART_FIFO_CONFIG_0, BL_SET_REG_BIT(tmpVal, UART_TX_FIFO_CLR)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART rx fifo clear - * - * @param uartId: UART ID type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_RxFifoClear(UART_ID_Type uartId) -{ - uint32_t tmpVal = 0; - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameter */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Clear rx fifo */ - tmpVal = BL_RD_REG(UARTx, UART_FIFO_CONFIG_0); - BL_WR_REG(UARTx, UART_FIFO_CONFIG_0, BL_SET_REG_BIT(tmpVal, UART_RX_FIFO_CLR)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART mask or unmask certain or all interrupt - * - * @param uartId: UART ID type - * @param intType: UART interrupt type - * @param intMask: UART interrupt mask value( MASK:disbale interrupt,UNMASK:enable interrupt ) - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_IntMask(UART_ID_Type uartId, UART_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpVal; - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - CHECK_PARAM(IS_UART_INT_TYPE(intType)); - CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); - - tmpVal = BL_RD_REG(UARTx, UART_INT_MASK); - - /* Mask or unmask certain or all interrupt */ - if (UART_INT_ALL == intType) { - if (MASK == intMask) { - tmpVal |= 0xfff; - } else { - tmpVal &= 0; - } - } else { - if (MASK == intMask) { - tmpVal |= 1 << intType; - } else { - tmpVal &= ~(1 << intType); - } - } - - /* Write back */ - BL_WR_REG(UARTx, UART_INT_MASK, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART clear certain or all interrupt - * - * @param uartId: UART ID type - * @param intType: UART interrupt type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_IntClear(UART_ID_Type uartId, UART_INT_Type intType) -{ - uint32_t tmpVal; - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - CHECK_PARAM(IS_UART_INT_TYPE(intType)); - - tmpVal = BL_RD_REG(UARTx, UART_INT_CLEAR); - - /* Clear certain or all interrupt */ - if (UART_INT_ALL == intType) { - tmpVal |= 0xfff; - } else { - tmpVal |= 1 << intType; - } - - /* Write back */ - BL_WR_REG(UARTx, UART_INT_CLEAR, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Install uart interrupt callback function - * - * @param uartId: UART ID type - * @param intType: UART interrupt type - * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) - * - * @return SUCCESS - * -*******************************************************************************/ -#if (defined BOOTROM) || (!defined BFLB_USE_HAL_DRIVER) -BL_Err_Type UART_Int_Callback_Install(UART_ID_Type uartId, UART_INT_Type intType, intCallback_Type *cbFun) -{ - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - CHECK_PARAM(IS_UART_INT_TYPE(intType)); - - uartIntCbfArra[uartId][intType] = cbFun; - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief UART send data to tx fifo - * - * @param uartId: UART ID type - * @param data: The data to be send - * @param len: The length of the send buffer - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_SendData(UART_ID_Type uartId, uint8_t *data, uint32_t len) -{ - uint32_t txLen = 0; - uint32_t UARTx = uartAddr[uartId]; - uint32_t timeoutCnt = UART_TX_TIMEOUT_COUNT; - - /* Check the parameter */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Send data */ - while (txLen < len) { - if (UART_GetTxFifoCount(uartId) > 0) { - BL_WR_BYTE(UARTx + UART_FIFO_WDATA_OFFSET, data[txLen++]); - timeoutCnt = UART_TX_TIMEOUT_COUNT; - } else { - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART send data to tx fifo in block mode - * - * @param uartId: UART ID type - * @param data: The data to be send - * @param len: The length of the send buffer - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_SendDataBlock(UART_ID_Type uartId, uint8_t *data, uint32_t len) -{ - uint32_t txLen = 0; - uint32_t UARTx = uartAddr[uartId]; - uint32_t timeoutCnt = UART_TX_TIMEOUT_COUNT; - - /* Check the parameter */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Send data */ - while (txLen < len) { - if (UART_GetTxFifoCount(uartId) > 0) { - BL_WR_BYTE(UARTx + UART_FIFO_WDATA_OFFSET, data[txLen++]); - timeoutCnt = UART_TX_TIMEOUT_COUNT; - } else { - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } - } - - timeoutCnt = UART_TX_TIMEOUT_COUNT; - - while (UART_GetTxBusBusyStatus(uartId) == SET) { - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART receive data from rx fifo - * - * @param uartId: UART ID type - * @param data: The receive data buffer - * @param maxLen: The max length of the buffer - * - * @return The length of the received buffer - * -*******************************************************************************/ -uint32_t UART_ReceiveData(UART_ID_Type uartId, uint8_t *data, uint32_t maxLen) -{ - uint32_t rxLen = 0; - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameter */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Receive data */ - while (rxLen < maxLen && UART_GetRxFifoCount(uartId) > 0) { - data[rxLen++] = BL_RD_BYTE(UARTx + UART_FIFO_RDATA_OFFSET); - } - - return rxLen; -} - -/****************************************************************************/ /** - * @brief UART get auto baud count value - * - * @param uartId: UART ID type - * @param autoBaudDet: Detection using codeword 0x55 or start bit - * - * @return Bit period of auto baudrate detection - * -*******************************************************************************/ -uint16_t UART_GetAutoBaudCount(UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet) -{ - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameter */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - CHECK_PARAM(IS_UART_AUTOBAUDDETECTION_TYPE(autoBaudDet)); - - /* Select 0x55 or start bit detection value */ - if (UART_AUTOBAUD_0X55 == autoBaudDet) { - return BL_RD_REG(UARTx, UART_STS_URX_ABR_PRD) >> 0x10 & 0xffff; - } else { - return BL_RD_REG(UARTx, UART_STS_URX_ABR_PRD) & 0xffff; - } -} - -/****************************************************************************/ /** - * @brief UART get rx current byte count value - * - * @param uartId: UART ID type - * - * @return Rx byte count value - * -*******************************************************************************/ -uint16_t UART_GetRxByteCount(UART_ID_Type uartId) -{ - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameter */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - return BL_GET_REG_BITS_VAL(BL_RD_REG(UARTx, UART_URX_BCR_INT_CFG), UART_STS_URX_BCR_COUNT); -} - -/****************************************************************************/ /** - * @brief UART get tx fifo unoccupied count value - * - * @param uartId: UART ID type - * - * @return Tx fifo unoccupied count value - * -*******************************************************************************/ -uint8_t UART_GetTxFifoCount(UART_ID_Type uartId) -{ - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameter */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - return BL_GET_REG_BITS_VAL(BL_RD_REG(UARTx, UART_FIFO_CONFIG_1), UART_TX_FIFO_CNT); -} - -/****************************************************************************/ /** - * @brief UART get rx fifo occupied count value - * - * @param uartId: UART ID type - * - * @return Rx fifo occupied count value - * -*******************************************************************************/ -uint8_t UART_GetRxFifoCount(UART_ID_Type uartId) -{ - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameter */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - return BL_GET_REG_BITS_VAL(BL_RD_REG(UARTx, UART_FIFO_CONFIG_1), UART_RX_FIFO_CNT); -} - -/****************************************************************************/ /** - * @brief Get uart interrupt status - * - * @param uartId: UART ID type - * @param intType: UART interrupt type - * - * @return Status of interrupt - * -*******************************************************************************/ -BL_Sts_Type UART_GetIntStatus(UART_ID_Type uartId, UART_INT_Type intType) -{ - uint32_t tmpVal; - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - CHECK_PARAM(IS_UART_INT_TYPE(intType)); - - /* Get certain or all interrupt status */ - tmpVal = BL_RD_REG(UARTx, UART_INT_STS); - - if (UART_INT_ALL == intType) { - if ((tmpVal & 0xfff) != 0) { - return SET; - } else { - return RESET; - } - } else { - if ((tmpVal & (1U << intType)) != 0) { - return SET; - } else { - return RESET; - } - } -} - -/****************************************************************************/ /** - * @brief Get indicator of uart tx bus busy - * - * @param uartId: UART ID type - * - * @return Status of tx bus - * -*******************************************************************************/ -BL_Sts_Type UART_GetTxBusBusyStatus(UART_ID_Type uartId) -{ - uint32_t tmpVal; - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Get tx bus busy status */ - tmpVal = BL_RD_REG(UARTx, UART_STATUS); - - if (BL_IS_REG_BIT_SET(tmpVal, UART_STS_UTX_BUS_BUSY)) { - return SET; - } else { - return RESET; - } -} - -/****************************************************************************/ /** - * @brief Get indicator of uart rx bus busy - * - * @param uartId: UART ID type - * - * @return Status of rx bus - * -*******************************************************************************/ -BL_Sts_Type UART_GetRxBusBusyStatus(UART_ID_Type uartId) -{ - uint32_t tmpVal; - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Get rx bus busy status */ - tmpVal = BL_RD_REG(UARTx, UART_STATUS); - - if (BL_IS_REG_BIT_SET(tmpVal, UART_STS_URX_BUS_BUSY)) { - return SET; - } else { - return RESET; - } -} - -/****************************************************************************/ /** - * @brief Get tx/rx fifo overflow or underflow status - * - * @param uartId: UART ID type - * @param overflow: Select tx/rx overflow or underflow - * - * @return Status of tx/rx fifo - * -*******************************************************************************/ -BL_Sts_Type UART_GetOverflowStatus(UART_ID_Type uartId, UART_Overflow_Type overflow) -{ - uint32_t tmpVal; - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - CHECK_PARAM(IS_UART_OVERFLOW_TYPE(overflow)); - - /* Get tx/rx fifo overflow or underflow status */ - tmpVal = BL_RD_REG(UARTx, UART_FIFO_CONFIG_0); - - if ((tmpVal & (1U << (overflow + 4))) != 0) { - return SET; - } else { - return RESET; - } -} - -/****************************************************************************/ /** - * @brief UART0 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#if (defined BOOTROM) || (!defined BFLB_USE_HAL_DRIVER) -void UART0_IRQHandler(void) -{ - UART_IntHandler(UART0_ID); -} -#endif - -/****************************************************************************/ /** - * @brief UART1 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#if (defined BOOTROM) || (!defined BFLB_USE_HAL_DRIVER) -void UART1_IRQHandler(void) -{ - UART_IntHandler(UART1_ID); -} -#endif - -/****************************************************************************/ /** - * @brief UART2 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void UART2_IRQHandler(void) -{ - UART_IntHandler(UART2_ID); -} -#endif - -/****************************************************************************/ /** - * @brief UART3 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void UART3_IRQHandler(void) -{ - UART_IntHandler(UART0_MM_ID); -} -#endif - -/*@} end of group UART_Public_Functions */ - -/*@} end of group UART */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_uhs_phy.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_uhs_phy.c deleted file mode 100644 index 6b502dc01d..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_uhs_phy.c +++ /dev/null @@ -1,1500 +0,0 @@ -#include "bl808_uhs_phy.h" -#include -#include -#include -#include "psram_uhs_reg.h" -#include "glb_reg.h" -#include "pds_reg.h" -#include "bl808_common.h" -#include "bl808_psram_uhs.h" -#include "bl808_glb.h" - -#define bl808_DBG_RF (0) -#if bl808_DBG_RF -#define uhs_phy_printf_debug printf // debug mode -#define uhs_phy_printf printf -#else -#define uhs_phy_printf_debug(...) -// #define uhs_phy_printf printf // commit it out in release version -#define uhs_phy_printf(...) // useed in release version -#endif - -uint8_t uhs_latency_code = 1; -int32_t dqs_dq_delta = 0; -uint32_t dcache_original = 0; -uint32_t dcache_current = 0; -uint32_t dcache_end = 0; - - -void uhs_phy_delay_us(uint32_t us) -{ - arch_delay_us(us); -} - -void power_up_mm(void) -{ - // power up MM domain - uint32_t tmpVal = 0; - tmpVal = BL_RD_REG(PDS_BASE,PDS_CTL2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PDS_CR_PDS_FORCE_MM_PWR_OFF,0x0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PDS_CR_PDS_FORCE_MM_ISO_EN,0x0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PDS_CR_PDS_FORCE_MM_GATE_CLK,0x0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PDS_CR_PDS_FORCE_MM_MEM_STBY,0x0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PDS_CR_PDS_FORCE_MM_PDS_RST,0x0); - BL_WR_REG(PDS_BASE,PDS_CTL2,tmpVal); -} - -void power_up_uhspll(void) -{ - // power_up_uhspll - uint32_t tmpVal = 0; - tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_PU_UHSPLL_SFREG,0x1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_PU_UHSPLL,0x1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_UHSPLL_FBDV_RSTB,0x0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_UHSPLL_FBDV_RSTB,0x1); - BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG0,tmpVal); -} - -void power_up_ldo12uhs(void) -{ - // use internal LDO - uint32_t tmpVal = 0; - tmpVal = BL_RD_REG(GLB_BASE,GLB_LDO12UHS); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_PU_LDO12UHS,0x1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_LDO12UHS_VOUT_SEL,0x5); - BL_WR_REG(GLB_BASE,GLB_LDO12UHS,tmpVal); - uhs_phy_delay_us(1); - // use external LDO - // tmpVal = BL_RD_REG(GLB_BASE,GLB_LDO12UHS); - // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_LDO12UHS_PULLDOWN,0x0); - // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_LDO12UHS_PULLDOWN_SEL,0x1); - // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_PU_LDO12UHS,0x0); - // BL_WR_REG(GLB_BASE,GLB_LDO12UHS,tmpVal); -} - -void set_cen_ck_ckn(void) -{ - uint32_t tmpVal = 0; - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ_OE_MID_N_REG,0x0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ_OE_MID_P_REG,0x0); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50,tmpVal); - uhs_phy_delay_us(1); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_40); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_DMY1,0xfc); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_DMY0,0x1); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_40,tmpVal); - uhs_phy_delay_us(1); -} - -void set_or_uhs(void) -{ - uint32_t tmpVal = 0; - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_4C); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_ODT_SEL_HW,0x0); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_4C,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_48); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PSRAM_TYPE,0x2); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_48,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_ODT_SEL,0x0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_VREF_MODE,0x1); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_00); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_CEN_DLY_DRV,0x8); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_CK_DLY_DRV,0xB); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_00,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_04); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DM0_DLY_DRV,0x7); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DM1_DLY_DRV,0x7); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_04,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ15_DLY_DRV,0x7); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ14_DLY_DRV,0x7); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ13_DLY_DRV,0x7); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ12_DLY_DRV,0x7); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ11_DLY_DRV,0x7); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ10_DLY_DRV,0x7); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ9_DLY_DRV,0x7); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ8_DLY_DRV,0x7); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ7_DLY_DRV,0x7); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ6_DLY_DRV,0x7); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ5_DLY_DRV,0x7); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ4_DLY_DRV,0x7); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ3_DLY_DRV,0x7); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ2_DLY_DRV,0x7); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ1_DLY_DRV,0x7); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ0_DLY_DRV,0x7); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_28); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS0_DLY_DRV,0x6); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_28,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS1_DLY_DRV,0x6); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_OE_TIMER,0x3); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_00); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_CEN_SR,0x2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_CK_SR,0x2); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_00,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_04); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DM1_SR,0x2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DM0_SR,0x2); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_04,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ15_SR,0x2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ14_SR,0x2); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ13_SR,0x2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ12_SR,0x2); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ11_SR,0x2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ10_SR,0x2); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ9_SR,0x2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ8_SR,0x2); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ7_SR,0x2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ6_SR,0x2); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ5_SR,0x2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ4_SR,0x2); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ3_SR,0x2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ2_SR,0x2); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ1_SR,0x2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ0_SR,0x2); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ_OE_DN_P_REG,0x3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ_OE_DN_N_REG,0x3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ_OE_UP_P_REG,0x3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ_OE_UP_N_REG,0x3); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ15_DLY_RX,0x0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ14_DLY_RX,0x0); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ13_DLY_RX,0x0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ12_DLY_RX,0x0); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ11_DLY_RX,0x0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ10_DLY_RX,0x0); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ9_DLY_RX,0x0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ8_DLY_RX,0x0); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ7_DLY_RX,0x0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ6_DLY_RX,0x0); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ5_DLY_RX,0x0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ4_DLY_RX,0x0); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ3_DLY_RX,0x0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ2_DLY_RX,0x0); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ1_DLY_RX,0x0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ0_DLY_RX,0x0); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_28); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS0_DLY_RX,0x0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS0N_DLY_RX,0x0); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_28,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS1_DLY_RX,0x0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS1N_DLY_RX,0x0); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C,tmpVal); - uhs_phy_delay_us(300); -} - -void switch_to_ldo12uhs(void) -{ - uint32_t tmpVal = 0; - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_40); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_DMY1,0xcc); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_40,tmpVal); - uhs_phy_delay_us(150); -} - -void release_cen_ck_ckn(void) -{ - uint32_t tmpVal = 0; - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_40); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_DMY1,0xcf); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_DMY0,0x0); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_40,tmpVal); - uhs_phy_delay_us(1); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ_OE_MID_P_REG,0x3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ_OE_MID_N_REG,0x3); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50,tmpVal); - uhs_phy_delay_us(1); -} - -void uhs_phy_pwr_down(void) -{ - uint32_t tmpVal = 0; - tmpVal = BL_RD_REG(GLB_BASE,GLB_LDO12UHS); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_LDO12UHS_PULLDOWN_SEL,0x0); - BL_WR_REG(GLB_BASE,GLB_LDO12UHS,tmpVal); - uhs_phy_delay_us(1); - tmpVal = BL_RD_REG(GLB_BASE,GLB_LDO12UHS); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_PU_LDO12UHS,0x0); - BL_WR_REG(GLB_BASE,GLB_LDO12UHS,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_40); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_DMY1,0xff); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_40,tmpVal); - uhs_phy_delay_us(2); - tmpVal = BL_RD_REG(GLB_BASE,GLB_LDO12UHS); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_PU_UHSPLL_SFREG,0x0); - BL_WR_REG(GLB_BASE,GLB_LDO12UHS,tmpVal); - uhs_phy_delay_us(1); -} - -void psram_init(void) -{ - uint32_t tmpVal = 0; - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_ADDRMB_MSK,0x3f); // 3F -> 512Mb psram, 1F -> 256Mb psram - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_LINEAR_BND_B,0xb); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_INIT_EN,0x1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_REQ,0x1); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal); - uhs_phy_delay_us(1); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_GLBR_PULSE,0x1); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD,tmpVal); - uhs_phy_delay_us(10); // wait for reg_config_gnt - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_REQ,0x0); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal); - - // psram auto refresh at 2000Mbps - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_WIN_CYCLE,0x001E0C4); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_1,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_WIN_REF_CNT,0x1007); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_REFI_CYCLE,0x01d); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_2,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_BUST_CYCLE,0x1); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_4,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_MANUAL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_PCK_T_DIV,0x40); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_MANUAL,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_AF_EN,0x1); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal); - - // psram cmd timing < 2000Mbps - BL_WR_WORD(0x3000F030,0x18090610); -} - -void set_uhspll_freq(uint32_t datarate) -{ - uint32_t tmpVal = 0; - uint32_t uhspll_sdmin = 0; - tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_UHSPLL_SEL_SAMPLE_CLK,0x1); - BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG4,tmpVal); - uhspll_sdmin = (datarate/(40/2))<<11; - if(datarate > 1000) - { - tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG5); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_UHSPLL_VCO_POSTDIV_SEL,0x0); - BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG5,tmpVal); - } - else if(datarate > 500) - { - uhspll_sdmin = uhspll_sdmin<<1; - tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG5); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_UHSPLL_VCO_POSTDIV_SEL,0x1); - BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG5,tmpVal); - } - else - { - uhspll_sdmin = uhspll_sdmin<<2; - tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG5); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_UHSPLL_VCO_POSTDIV_SEL,0x2); - BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG5,tmpVal); - } - tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG6); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_UHSPLL_SDMIN,uhspll_sdmin); - BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG6,tmpVal); - uhs_phy_delay_us(30); - - //reset PLL - /* toggle sdm_reset (pulse 0 > 1us) */ - /* cfg0 : aupll_sdm_reset */ - tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UHSPLL_SDM_RSTB, 1); - BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG0,tmpVal); - arch_delay_us(2); - tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UHSPLL_SDM_RSTB, 0); - BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG0,tmpVal); - arch_delay_us(2); - tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UHSPLL_SDM_RSTB, 1); - BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG0,tmpVal); - - /* Step3:reset pll */ - /* cfg0 : toggle aupll_reset_fbdv, pulse 0 > 1us */ - tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UHSPLL_FBDV_RSTB, 1); - BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG0,tmpVal); - arch_delay_us(2); - tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UHSPLL_FBDV_RSTB, 0); - BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG0,tmpVal); - arch_delay_us(2); - tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UHSPLL_FBDV_RSTB, 1); - BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG0,tmpVal); - - uhs_phy_delay_us(30); -} - -void set_uhs_phy_init(void) -{ - // set phy & controller - uint32_t tmpVal = 0; - // default latency(800MHz) - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_ANA,0x2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_DIG,0x7); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_WL_ANA,0x0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_WL_DIG,0x2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_WL_DQ_ANA,0x1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_WL_DQ_DIG,0x2); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_34,0x09020303); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_38,0x040c0313); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_3C,0x07d11515); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_44,0x060f050c); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_WL_CEN_ANA,0x1); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50,tmpVal); -} - -void set_uhs_phy(void) -{ - // set phy & controller - // latency code=3 (1066MHz) - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,0x0f0a1323); // if fail than use 0x0f391323 - // BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,0x0f0a0313); //for 400Mbps - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_34,0x0b030404); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_38,0x050e0418); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_3C,0x0a6a1c1c); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_44,0x07110710); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50,0x01333333); -} - -void uhs_reg_w(uint32_t uhs_latency,uint32_t uhs_drive,uint32_t ma,uint32_t BL_32) -{ - uint32_t tmpVal = 0; - if(ma == 0) - { - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_PSRAM_CONFIGURE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_LATENCY,uhs_latency); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_DRIVE_ST,uhs_drive); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_PSRAM_CONFIGURE,tmpVal); - } - else if(ma == 2) - { - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_PSRAM_CONFIGURE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_BL_64,0x0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_BL_32,BL_32); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_BL_16,0x0); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_PSRAM_CONFIGURE,tmpVal); - } - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_MODE_REG,ma); //reg_mode_reg - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_REQ,0x1); //reg_config_req - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal); - while (1) - { - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_GNT); - if (tmpVal == 1) - break; - } - - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_REGW_PULSE,0x1); //reg_regw_pulse - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD,tmpVal); - while (1) - { - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal,PSRAM_UHS_STS_REGR_DONE); - if (tmpVal == 1) - break; - } - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_REQ,0x0); //reg_config_req - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal); -} - -void uhs_reg_r(uint32_t ma) -{ - uint32_t tmpVal = 0; - uint32_t tmpInd = 0; - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_MODE_REG,ma); //reg_mode_reg - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_REQ,0x1); //reg_config_req - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal); - - // uhs_phy_delay_us(10); - while (1) - { - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_GNT); - if (tmpVal == 1) - break; - } - - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_REGR_PULSE,0x1); //reg_regw_pulse - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD,tmpVal); - // uhs_phy_delay_us(1); - tmpInd = 0; - while (1) - { - tmpInd++; - uhs_phy_delay_us(1); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal,PSRAM_UHS_STS_REGR_DONE); - if (tmpVal == 1 || tmpInd == 2){ - //debug - if (tmpInd == 2){ - uhs_phy_printf_debug("tmpInd = %ld\r\n",tmpInd); - } - break; - } - } - - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_REQ,0x0); //reg_config_req - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal); -} - - -void cfg_dq_rx(uint8_t dq){ - uint32_t tmpVal = 0; - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ15_DLY_RX,dq); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ14_DLY_RX,dq); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ13_DLY_RX,dq); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ12_DLY_RX,dq); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ11_DLY_RX,dq); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ10_DLY_RX,dq); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ9_DLY_RX,dq); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ8_DLY_RX,dq); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ7_DLY_RX,dq); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ6_DLY_RX,dq); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ5_DLY_RX,dq); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ4_DLY_RX,dq); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ3_DLY_RX,dq); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ2_DLY_RX,dq); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ1_DLY_RX,dq); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ0_DLY_RX,dq); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08,tmpVal); -} - -void cfg_dqs_rx(uint8_t dqs){ - uint32_t tmpVal = 0; - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_28); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS0_DIFF_DLY_RX,dqs); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_28,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS1_DIFF_DLY_RX,dqs); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C,tmpVal); -} - -void cfg_ck_cen_drv(uint8_t array_ck_dly_drv,uint8_t array_cen_dly_drv){ - uint32_t tmpVal = 0; - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_00); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_CK_DLY_DRV,array_ck_dly_drv); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_CEN_DLY_DRV,array_cen_dly_drv); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_00,tmpVal); -} - -void uhs_reset(uint32_t datarate) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_WORD(0x30007044); - tmpVal = tmpVal | 0x00008000; - BL_WR_WORD(0x30007044,tmpVal); - uhs_phy_delay_us(10); - tmpVal = tmpVal & 0xFFFF7FFF; - BL_WR_WORD(0x30007044,tmpVal); - - BL_WR_WORD(0x3000F030,0x18090610); - - PSRAM_UHS_Cfg_Type psramCfg = { - datarate, - PSRAM_MEM_SIZE_64MB, - PSRAM_PAGE_SIZE_2KB, - 0, - }; - Psram_UHS_Init(&psramCfg); //controller init - - set_or_uhs(); - set_uhs_phy(); -} - -void reg_read_cal(uint32_t datarate) -{ - uint32_t tmpVal = 0; - uint32_t tmpVal_1 = 0; - uint32_t uhs_latency = 42; - int32_t i = 0; - uint8_t dqs_dq_flag = 0; - uint32_t reg_dqs = 0; - uint32_t reg_dq = 0; - - for(uhs_latency = 41; uhs_latency > 0; uhs_latency --) - { - if(uhs_latency == 34) - { - uhs_phy_printf("reg read cal error\r\n"); - while(1){ - uhs_phy_printf("."); - uhs_phy_delay_us(100000); - }; - // break; - } - - uhs_phy_printf_debug("reg read cal by latency=%ld\r\n",uhs_latency); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_ANA,uhs_latency%4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_DIG,uhs_latency/4); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal); - - // sweep dqs - cfg_dq_rx(0); - for(i = 15; i >= 0; i --) - { - cfg_dqs_rx(i); - - uhs_reg_r(0); - tmpVal_1 = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD); //high temp failure workaround - tmpVal_1 = BL_GET_REG_BITS_VAL(tmpVal_1,PSRAM_UHS_STS_REGR_DONE); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24; - if(tmpVal == ((2<<3)+uhs_latency_code)&& (tmpVal_1 == 1)) - { - uhs_phy_printf_debug("reg read pass by dqs=%ld\r\n",i); - reg_dqs = i; - dqs_dq_flag = 1; - break; - } - else - { - uhs_phy_printf_debug("reg read fail by dqs=%ld\r\n",i); - } - - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal,PSRAM_UHS_STS_REGR_DONE); - if(tmpVal == 0) - { - uhs_phy_printf_debug("read done not found!!!"); - uhs_reset(datarate); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_ANA,uhs_latency%4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_DIG,uhs_latency/4); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal); - cfg_dq_rx(0); - } - - } - - // sweep dq - cfg_dqs_rx(0); - for(i = 15; i >=0; i --) - { - cfg_dq_rx(i); - - uhs_reg_r(0); - tmpVal_1 = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD); //high temp failure workaround - tmpVal_1 = BL_GET_REG_BITS_VAL(tmpVal_1,PSRAM_UHS_STS_REGR_DONE); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24; - if(tmpVal == ((2<<3)+uhs_latency_code)&& (tmpVal_1 == 1)) - { - uhs_phy_printf_debug("reg read pass by dq=%ld\r\n",i); - reg_dq = i; - dqs_dq_flag = 1; - break; - } - else - { - uhs_phy_printf_debug("reg read fail by dq=%ld\r\n",i); - } - - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal,PSRAM_UHS_STS_REGR_DONE); - if(tmpVal == 0) - { - uhs_phy_printf_debug("read done not found!!!"); - uhs_reset(datarate); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_ANA,uhs_latency%4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_DIG,uhs_latency/4); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal); - cfg_dqs_rx(0); - } - - } - - if (dqs_dq_flag == 1){ - uhs_latency = uhs_latency - 2; - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_ANA,uhs_latency%4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_DIG,uhs_latency/4); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal); - //sweep dqs - cfg_dq_rx(0); - for(i = 15; i >= 0; i --) - { - cfg_dqs_rx(i); - uhs_reg_r(0); - tmpVal_1 = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD); //high temp failure workaround - tmpVal_1 = BL_GET_REG_BITS_VAL(tmpVal_1,PSRAM_UHS_STS_REGR_DONE); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24; - if(tmpVal == ((2<<3)+uhs_latency_code)&& (tmpVal_1 == 1)) - { - uhs_phy_printf_debug("reg read pass by dqs=%ld\r\n",i); - reg_dqs = i; - dqs_dq_flag = 1; - break; - } - else{ - uhs_phy_printf_debug("reg read fail by dqs=%ld\r\n",i); - } - } - // sweep dq - cfg_dqs_rx(0); - for(i = 15; i >=0; i --) - { - cfg_dq_rx(i); - - uhs_reg_r(0); - tmpVal_1 = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD); //high temp failure workaround - tmpVal_1 = BL_GET_REG_BITS_VAL(tmpVal_1,PSRAM_UHS_STS_REGR_DONE); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24; - if(tmpVal == ((2<<3)+uhs_latency_code)&& (tmpVal_1 == 1)) - { - uhs_phy_printf_debug("reg read pass by dq=%ld\r\n",i); - reg_dq = i; - dqs_dq_flag = 1; - break; - } - else{ - uhs_phy_printf_debug("reg read fail by dq=%ld\r\n",i); - } - } - - if(reg_dqs > reg_dq) - { - reg_dqs = (reg_dqs-reg_dq)/2; - reg_dq = 0; - } - else - { - reg_dq = (reg_dq-reg_dqs)/2; - reg_dqs = 0; - } - - // set dqs & dq by register read calibration result - cfg_dqs_rx(reg_dqs); - cfg_dq_rx(reg_dq); - uhs_reg_r(0); - uhs_phy_printf("reg read cal pass, latency=%ld, dqs=%ld, dq=%ld\r\n",uhs_latency,reg_dqs,reg_dq); - - break; - } - } -} - -void cfg_dq_drv(uint32_t dq){ - uint32_t tmpVal = 0; - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_04); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DM0_DLY_DRV,dq); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DM1_DLY_DRV,dq); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_04,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ15_DLY_DRV,dq); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ14_DLY_DRV,dq); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ13_DLY_DRV,dq); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ12_DLY_DRV,dq); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ11_DLY_DRV,dq); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ10_DLY_DRV,dq); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ9_DLY_DRV,dq); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ8_DLY_DRV,dq); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ7_DLY_DRV,dq); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ6_DLY_DRV,dq); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ5_DLY_DRV,dq); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ4_DLY_DRV,dq); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ3_DLY_DRV,dq); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ2_DLY_DRV,dq); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ1_DLY_DRV,dq); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ0_DLY_DRV,dq); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08,tmpVal); -} - -void cfg_dqs_drv(uint32_t dqs){ - uint32_t tmpVal = 0; - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_28); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS0_DLY_DRV,dqs); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_28,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS1_DLY_DRV,dqs); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C,tmpVal); -} - -void reg_write_cal(void) //only need sweep dqs -{ - uint32_t tmpVal = 0; - uint32_t tmpVal_1 = 0; - int32_t i = 0; - uint32_t reg_dqs; - uint32_t reg_dq = 0; - uint32_t reg_dqs1 = 0; - uint32_t reg_dqs2 = 0; - uint8_t dqs_dq_flag = 0; - - // sweep1 dqs - for(i = 15; i >=0; i --) - { - cfg_dqs_drv(i); - uhs_reg_w(uhs_latency_code,2,2,1); //BL_32 == 1 - uhs_reg_r(2); - tmpVal_1 = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD); //high temp failure workaround - tmpVal_1 = BL_GET_REG_BITS_VAL(tmpVal_1,PSRAM_UHS_STS_REGR_DONE); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24; - if((tmpVal == 16) && (tmpVal_1 == 1)) - { - uhs_phy_printf("reg write pass by -- dqs1=%ld\r\n",i); - reg_dqs1 = i; - dqs_dq_flag = 1; - break; - } - else{ - uhs_phy_printf_debug("reg write fail by -- dqs1=%ld\r\n",i); - } - } - // sweep2 dqs - for(i = 0; i <=15; i ++) - { - cfg_dqs_drv(i); - uhs_reg_w(uhs_latency_code,2,2,1); //BL_32 == 1 - uhs_reg_r(2); - tmpVal_1 = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD); //high temp failure workaround - tmpVal_1 = BL_GET_REG_BITS_VAL(tmpVal_1,PSRAM_UHS_STS_REGR_DONE); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24; - if((tmpVal == 16) && (tmpVal_1 == 1)) - { - uhs_phy_printf("reg write pass by ++ dqs2=%ld\r\n",i); - reg_dqs2 = i; - dqs_dq_flag = 1; - break; - } - else{ - uhs_phy_printf_debug("reg write fail by ++ dqs2=%ld\r\n",i); - } - } - - if(dqs_dq_flag == 0) - { - uhs_phy_printf("reg write cal error 0\r\n"); - while(1){ - uhs_phy_printf("."); - uhs_phy_delay_us(100000); - }; - // break; - } - - reg_dqs = (reg_dqs1 + reg_dqs2) / 2 ; - // set dqs by register write cal result - cfg_dqs_drv(reg_dqs); - uhs_reg_w(uhs_latency_code,2,2,0); //BL_32 == 0 - uhs_reg_r(2); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24; - if(tmpVal == 0) - { - uhs_phy_printf("reg write cal pass dqs=%ld, dq=%ld\r\n",reg_dqs,reg_dq); - } - else{ - uhs_phy_printf("reg write cal error 1\r\n"); - while(1){ - uhs_phy_printf("."); - uhs_phy_delay_us(100000); - }; - // break; - } - - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08); - reg_dq = BL_GET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ0_DLY_DRV); - dqs_dq_delta = 16 + reg_dqs - reg_dq; - uhs_phy_printf("reg_write_cal return dqs_dq_delta=%ld\r\n",dqs_dq_delta); - // return dqs_dq_delta; -} - -void array_write_fix(uint32_t addr,uint32_t len,uint32_t data0,uint32_t data1) -{ - uint32_t addr_tmp = addr; - uint32_t data = data0; - int32_t i = 0; - for(i = 0; i < (len>>2); i ++) - { - addr_tmp = (i << 2) + addr; - if(i % 2 == 0) - data = data0 + i; - else - data = data1 + i; - BL_WR_WORD(addr_tmp,data); - } -} -uint32_t array_read_fix(uint32_t addr,uint32_t len,uint32_t data0,uint32_t data1) -{ - uint32_t array_read_pass = 1; - uint32_t addr_tmp = addr; - uint32_t data = data0; - uint32_t data_read = 0; - int32_t i = 0; - - for(i = 0; i < (len>>2); i ++) - { - addr_tmp = (i << 2) + addr; - data_read = BL_RD_WORD(addr_tmp); - if(i % 2 == 0) - data = data0 + i; - else - data = data1 + i; - if(data_read != data){ - array_read_pass = 0; - break; - } - } - return array_read_pass; -} - -void set_ck_dly_drv(uint32_t array_ck_dly_drv) -{ - uint32_t array_dqx_dly_drv = 0; - uint32_t array_dqsx_dly_drv = 0; - uint32_t array_cen_dly_drv = 0; - - arch_delay_us(1); // ck modify need time - - array_dqx_dly_drv = (array_ck_dly_drv >=4) ? (array_ck_dly_drv-4) : 0; - array_cen_dly_drv = array_dqx_dly_drv + 1; - // array_dqsx_dly_drv = ((int32_t)((int32_t)(dqs_dq_delta)+(int32_t)(array_dqx_dly_drv))<0)?0:(array_dqx_dly_drv + dqs_dq_delta); - array_dqsx_dly_drv = (dqs_dq_delta + array_dqx_dly_drv >= 16) ? (dqs_dq_delta + array_dqx_dly_drv - 16) : 0; - - // array_dqsx_dly_drv = (array_dqx_dly_drv > 15) ? 15 : array_dqsx_dly_drv; - array_dqx_dly_drv = (array_dqx_dly_drv > 15) ? 15 : array_dqx_dly_drv; - array_cen_dly_drv = (array_cen_dly_drv > 15) ? 15 : array_cen_dly_drv; - array_dqsx_dly_drv = (array_dqsx_dly_drv > 15) ? 15 : array_dqsx_dly_drv; - - cfg_dq_drv(array_dqx_dly_drv); - cfg_dqs_drv(array_dqsx_dly_drv); - cfg_ck_cen_drv(array_ck_dly_drv,array_cen_dly_drv); - - arch_delay_us(10); // ck modify need time -} - -void array_read_latency_cal(void) -{ - uint32_t tmpVal = 0; - uint32_t uhs_latency = 42; - uint32_t array_ck_dly_drv = 0; - uint32_t flag = 0; - - uint32_t dig = 0; - uint32_t ana = 0; - uint32_t latency = 0; - - array_write_fix(0x50000000,128,0x12345678,0x87654321); - - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30); - dig = (tmpVal >> 16) & 0xF; - ana = (tmpVal >> 20) & 0x7; - latency = (dig<<2) + ana; - - for(uhs_latency = latency; uhs_latency > 0; uhs_latency --) - { - if(uhs_latency == 34) - { - uhs_phy_printf("array read latency cal error\r\n"); - while(1){ - uhs_phy_printf("."); - uhs_phy_delay_us(100000); - }; - // break; - } - - uhs_phy_printf_debug("array read cal by latency=%ld\r\n",uhs_latency); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_ANA,uhs_latency%4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_DIG,uhs_latency/4); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal); - - array_ck_dly_drv = 11; - set_ck_dly_drv(array_ck_dly_drv); - - flag = array_read_fix(0x50000000,128,0x12345678,0x87654321); - - if(flag == 1) - { - uhs_phy_printf_debug("array read pass by ck == 11\r\n"); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_ANA,uhs_latency%4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_DIG,uhs_latency/4); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal); - uhs_phy_printf("array read latency cal pass, latency=%ld, ck=%ld\r\n",uhs_latency,array_ck_dly_drv); - break; - } - else - { - uhs_phy_printf_debug("array read fail by ck == 11\r\n"); - array_ck_dly_drv = 4; - set_ck_dly_drv(array_ck_dly_drv); - flag = array_read_fix(0x50000000,128,0x12345678,0x87654321); - if(flag == 1) - { - uhs_phy_printf_debug("array read pass by ck == 4\r\n"); - // uhs_latency = uhs_latency - 2; - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_ANA,uhs_latency%4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_DIG,uhs_latency/4); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal); - uhs_phy_printf("array read latency cal pass, latency=%ld, ck=%ld\r\n",uhs_latency,array_ck_dly_drv); - break; - } - else{ - uhs_phy_printf_debug("array read fail by ck == 4\r\n"); - } - } - } -} - -void array_write_ck_cal(void) -{ - uint32_t array_ck_dly_drv = 0; - uint32_t array_ck_dly_drv1 = 0; - uint32_t array_ck_dly_drv2 = 0; - uint32_t flag = 0; - - array_write_fix(0x50000000,1024,0x12345678,0x87654321); - - for(array_ck_dly_drv = 15; array_ck_dly_drv >= 4; array_ck_dly_drv --) - { - set_ck_dly_drv(array_ck_dly_drv); - - flag = array_read_fix(0x50000000,1024,0x12345678,0x87654321); - if(flag == 0){ - uhs_phy_printf_debug("array write ck cal fail by ck=%ld\r\n",array_ck_dly_drv); - array_ck_dly_drv1 = array_ck_dly_drv; - break; - } - } - - if(flag == 1){ - array_ck_dly_drv = (15 + 4) / 2; - set_ck_dly_drv(array_ck_dly_drv); - - uhs_phy_printf("array write ck cal pass, ck=%ld\r\n",array_ck_dly_drv); - return; - } - - for(array_ck_dly_drv = 4; array_ck_dly_drv <= 15; array_ck_dly_drv ++) - { - set_ck_dly_drv(array_ck_dly_drv); - - flag = array_read_fix(0x50000000,1024,0x12345678,0x87654321); - if(flag == 0){ - uhs_phy_printf_debug("array write ck cal fail by ck=%ld\r\n",array_ck_dly_drv); - array_ck_dly_drv2 = array_ck_dly_drv; - break; - } - } - - if(array_ck_dly_drv1 == 15 && array_ck_dly_drv2 == 4) - { - uhs_phy_printf_debug("array write ck cal error\r\n"); - while(1){ - uhs_phy_printf("."); - uhs_phy_delay_us(100000); - }; - // break; - } - if ((15 - array_ck_dly_drv1) >= (array_ck_dly_drv2 - 4)) - { - array_ck_dly_drv = 15; - } - else - { - array_ck_dly_drv = 4; - } - - set_ck_dly_drv(array_ck_dly_drv); - - uhs_phy_printf("array write ck cal pass, ck=%ld\r\n",array_ck_dly_drv); - -} - -void array_read_dqs_dq_cal(void) -{ - // uint32_t tmpVal = 0; - int32_t i = 0; - uint32_t array_dqs = 0; - uint32_t array_dq = 0; - uint32_t dqs_flag; - uint32_t dq_flag; - array_write_fix(0x50000000,128,0x12345678,0x87654321); - // sweep dqs - cfg_dq_rx(0); - - for(i = 15; i >= 0; i --) - { - cfg_dqs_rx(i); - dqs_flag = array_read_fix(0x50000000,128,0x12345678,0x87654321); - if(dqs_flag == 1) - { - uhs_phy_printf_debug("array_read_dqs_dq_cal pass by dqs%ld\r\n",i); - array_dqs = i; - break; - } - } - // sweep dq - cfg_dqs_rx(0); - for(i = 15; i >=0; i --) - { - cfg_dq_rx(i); - dq_flag = array_read_fix(0x50000000,128,0x12345678,0x87654321); - if(dq_flag == 1) - { - uhs_phy_printf_debug("array_read_dqs_dq_cal pass by dq%ld\r\n",i); - array_dq = i; - break; - } - } - if(dqs_flag == 0 && dq_flag == 0) - { - uhs_phy_printf("array_read_dqs_dq_cal error\r\n"); - while(1) - { - uhs_phy_printf("."); - uhs_phy_delay_us(100000); - }; - } - if(array_dqs > array_dq) - { - array_dqs = (array_dqs-array_dq)/2; - array_dq = 0; - } - else - { - array_dq = (array_dq-array_dqs)/2; - array_dqs = 0; - } - cfg_dq_rx(array_dq); - cfg_dqs_rx(array_dqs); - uhs_phy_printf("array_read_dqs_dq_cal pass by array_dqs=%ld, array_dq=%ld\r\n",array_dqs,array_dq); -} - -void array_write_dqs_dq_cal(void) -{ - uint32_t tmpVal = 0; - int32_t i = 0; - uint32_t dqs_flag = 0; - uint32_t array_dqs_dly_drv = 0; - uint32_t array_dqs_dly_drv1 = 0; - uint32_t array_dqs_dly_drv2 = 0; - - for(i = 15; i >= 0; i --) - { - cfg_dqs_drv(i); - array_write_fix(0x50000000,128,0x12345678,0x87654321); - dqs_flag = array_read_fix(0x50000000,128,0x12345678,0x87654321); - if(dqs_flag == 1) - { - uhs_phy_printf("array_write_dqs_dq_cal pass by -- dqs1=%ld\r\n",i); - array_dqs_dly_drv1 = i; - break; - } - else - { - uhs_phy_printf_debug("array_write_dqs_dq_cal fail by -- dqs1=%ld\r\n",i); - } - } - for(i = 0; i <= 15; i ++) - { - cfg_dqs_drv(i); - array_write_fix(0x50000000,128,0x12345678,0x87654321); - dqs_flag = array_read_fix(0x50000000,128,0x12345678,0x87654321); - if(dqs_flag == 1) - { - uhs_phy_printf("array_write_dqs_dq_cal pass by ++ dqs2=%ld\r\n",i); - array_dqs_dly_drv2 = i; - break; - } - else - { - uhs_phy_printf_debug("array_write_dqs_dq_cal fail by ++ dqs2=%ld\r\n",i); - } - } - if(dqs_flag == 0) - { - uhs_phy_printf("array_write_dqs_dq_cal error\r\n"); - while(1) - { - uhs_phy_printf("."); - uhs_phy_delay_us(100000); - }; - } - array_dqs_dly_drv = (array_dqs_dly_drv1 + array_dqs_dly_drv2) / 2 ; - // if ck_dly_drv = 4, fix dqsx_dly_drv to 0 - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_00); - tmpVal = (tmpVal >> 16) & 0xF; - if(tmpVal == 4) - { - array_dqs_dly_drv = 0; - } - uhs_phy_printf("array_write_dqs_dq_cal pass by array_dqs_dly_drv=%ld\r\n",array_dqs_dly_drv); - // set dqs by register write cal result - cfg_dqs_drv(array_dqs_dly_drv); -} - -BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_UHS_PLL_Freq(GLB_XTAL_Type xtalType, uint32_t pllFreq) -{ - uint32_t xtalFreq = 0; - uint32_t factor = 0; - GLB_MU_PLL_CFG_BASIC_Type uhsPllMCfg = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */ - }; - GLB_MU_PLL_Cfg_Type uhsPllCfg[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &uhsPllMCfg, 0x0 }, /*!< XTAL is 24M */ - { &uhsPllMCfg, 0x0 }, /*!< XTAL is 32M */ - { &uhsPllMCfg, 0x0 }, /*!< XTAL is 38.4M */ - { &uhsPllMCfg, 0x0 }, /*!< XTAL is 40M */ - { &uhsPllMCfg, 0x0 }, /*!< XTAL is 26M */ - { &uhsPllMCfg, 0x0 }, /*!< XTAL is RC32M */ - }; - GLB_PLL_REF_CLK_Type refClk; - - /* calc clkpllRefdivRatio */ - switch(xtalType){ - case GLB_XTAL_NONE: - return ERROR; - case GLB_XTAL_24M: - xtalFreq = 240; - uhsPllMCfg.clkpllRefdivRatio = 1; - break; - case GLB_XTAL_32M: - xtalFreq = 320; - uhsPllMCfg.clkpllRefdivRatio = 2; - break; - case GLB_XTAL_38P4M: - xtalFreq = 384; - uhsPllMCfg.clkpllRefdivRatio = 2; - break; - case GLB_XTAL_40M: - xtalFreq = 400; - uhsPllMCfg.clkpllRefdivRatio = 2; - break; - case GLB_XTAL_26M: - xtalFreq = 260; - uhsPllMCfg.clkpllRefdivRatio = 1; - break; - case GLB_XTAL_RC32M: - xtalFreq = 320; - uhsPllMCfg.clkpllRefdivRatio = 2; - break; - default : - break; - } - /* calc clkpllSelSampleClk */ - factor = pllFreq*20480/(xtalFreq/uhsPllMCfg.clkpllRefdivRatio); - if(factor<32*2048){ - uhsPllMCfg.clkpllSelSampleClk = 0; - }else if(factor<64*2048){ - uhsPllMCfg.clkpllSelSampleClk = 1; - }else if(factor<128*2048){ - uhsPllMCfg.clkpllSelSampleClk = 2; - }else{ - uhsPllMCfg.clkpllSelSampleClk = 2; - } - /* calc clkpllVcoSpeed */ - if(pllFreq<800){ - uhsPllMCfg.clkpllVcoSpeed = 1; - }else if(pllFreq<1000){ - uhsPllMCfg.clkpllVcoSpeed = 2; - }else if(pllFreq<1200){ - uhsPllMCfg.clkpllVcoSpeed = 3; - }else if(pllFreq<1500){ - uhsPllMCfg.clkpllVcoSpeed = 4; - }else if(pllFreq<1700){ - uhsPllMCfg.clkpllVcoSpeed = 5; - }else if(pllFreq<1900){ - uhsPllMCfg.clkpllVcoSpeed = 6; - }else if(pllFreq<2200){ - uhsPllMCfg.clkpllVcoSpeed = 7; - }else{ - uhsPllMCfg.clkpllVcoSpeed = 8; - } - /* calc clkpllEvenDivRatio */ - uhsPllMCfg.clkpllEvenDivRatio = pllFreq/50; - /* calc clkpllSdmin */ - uhsPllCfg[GLB_XTAL_24M].clkpllSdmin = factor; - uhsPllCfg[GLB_XTAL_32M].clkpllSdmin = factor; - uhsPllCfg[GLB_XTAL_38P4M].clkpllSdmin = factor; - uhsPllCfg[GLB_XTAL_40M].clkpllSdmin = factor; - uhsPllCfg[GLB_XTAL_26M].clkpllSdmin = factor; - uhsPllCfg[GLB_XTAL_RC32M].clkpllSdmin = factor; - - if (xtalType == GLB_XTAL_RC32M) { - refClk = GLB_PLL_REFCLK_RC32M; - } else { - refClk = GLB_PLL_REFCLK_XTAL; - } - - GLB_Power_Off_MU_PLL(GLB_MU_PLL_UHSPLL); - GLB_MU_PLL_Ref_Clk_Sel(GLB_MU_PLL_UHSPLL, refClk); - GLB_Power_On_MU_PLL(GLB_MU_PLL_UHSPLL, &(uhsPllCfg[xtalType]), 1); - - return SUCCESS; -} - -void self_cal(uint32_t datarate) -{ - // int32_t P1= 0; - uint32_t tmpVal = 0; - // uint32_t uhs_latency = 0; - - if (datarate >= 933*2){ - uhs_latency_code = UHS_LATENCY_CODE_1066; - }else if(datarate >= 800*2){ - uhs_latency_code = UHS_LATENCY_CODE_933; - }else if(datarate >= 533*2){ - uhs_latency_code = UHS_LATENCY_CODE_800; - }else if(datarate >= 400*2){ - uhs_latency_code = UHS_LATENCY_CODE_533; - }else if(datarate >= 333*2){ - uhs_latency_code = UHS_LATENCY_CODE_400; - }else if(datarate >= 200*2){ - uhs_latency_code = UHS_LATENCY_CODE_333; - }else{ - uhs_latency_code = UHS_LATENCY_CODE_200; - } - - PSRAM_UHS_Cfg_Type psramCfg = { - datarate, - PSRAM_MEM_SIZE_64MB, - PSRAM_PAGE_SIZE_2KB, - 0, - }; - - // set to 2000Mbps - uhs_reg_w(uhs_latency_code,2,0,0); // BL_32 == 0 - // set_uhspll_freq(datarate); // use SW function later - GLB_Config_UHS_PLL_Freq(GLB_XTAL_40M,datarate); //stuck - Psram_UHS_Init(&psramCfg); //controller init - set_uhs_phy(); - - // check reg read - uhs_reg_r(0); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24; - if(tmpVal == ((2<<3)+uhs_latency_code)){ - uhs_phy_printf("register write pass at 1400Mbps and read pass at %ldMbps\r\n",datarate); - } - else{ - uhs_phy_printf("register write fail at 1400Mbps or read fail at %ldMbps\r\n",datarate); - } - - // register read latency & dqs & dq calibration - reg_read_cal(datarate); - // register write dqs & dq calibration - reg_write_cal(); - uhs_reg_w(uhs_latency_code,2,2,0); // BL_32 == 0 - uhs_reg_r(2); - // array read latency calibration - array_read_latency_cal(); - // array write ck calibration - array_write_ck_cal(); - // array read dqs & dq calibration - array_read_dqs_dq_cal(); - // array write dqs & dq calibration - array_write_dqs_dq_cal(); -} - -void soft_reset(void) -{ - uint32_t tmpVal = 0; - tmpVal = BL_RD_REG(GLB_BASE,GLB_SWRST_CFG2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_REG_CTRL_PWRON_RST,0x1); // soft power on reset - BL_WR_REG(GLB_BASE,GLB_SWRST_CFG2,tmpVal); -} - -void uhs_phy_init(uint32_t datarate) -{ - uhs_phy_printf_debug("uhs phy init\r\n"); - power_up_mm(); - power_up_uhspll(); - - power_up_ldo12uhs(); - set_cen_ck_ckn(); - - set_or_uhs(); - switch_to_ldo12uhs(); - release_cen_ck_ckn(); - - uint32_t tmpVal = 0; - tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG9); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_UHSPLL_SSC_EN,0x0); // uhspll_ssc_en - BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG9,tmpVal); - - PSRAM_UHS_Cfg_Type psramCfg = { - 1400, - PSRAM_MEM_SIZE_64MB, - PSRAM_PAGE_SIZE_2KB, - 0, - }; - - // set_uhspll_freq(1400); // 700MHz is prefer , use SW function later - GLB_Config_UHS_PLL_Freq(GLB_XTAL_40M,1400); //stuck - Psram_UHS_Init(&psramCfg); // controller init - set_uhs_phy_init(); // phy init - psram_init(); // psram init after set freq & set_phy - - uhs_reg_r(0); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24; - if(tmpVal == ((2<<3)+1)) // 1400M --> default uhs_latency_code == 1 - { - uhs_phy_printf_debug("register read pass at datarate at 1400Mbps\r\n"); - } - else{ - uhs_phy_printf_debug("register read fail at datarate at 1400Mbps\r\n"); - } - - //get dcache original state - __DSB(); - __ISB(); - dcache_original = __get_MHCR(); - dcache_original &= (0x1<<1); - __DSB(); - __ISB(); - uhs_phy_printf("dcache_original=%lx\r\n",dcache_original); - - csi_dcache_disable(); - - //get dcache current state - __DSB(); - __ISB(); - dcache_current = __get_MHCR(); - dcache_current &= (0x1<<1); - __DSB(); - __ISB(); - uhs_phy_printf("dcache_current=%lx\r\n",dcache_current); - - if(dcache_current == 0x0) - { - self_cal(datarate); - } - else - { - uhs_phy_printf("dcache disable fail\r\n"); - } - - if (dcache_original == (0x1<<1)) - { - csi_dcache_enable(); - } - - //get dcache end state - __DSB(); - __ISB(); - dcache_end = __get_MHCR(); - dcache_end &= (0x1<<1); - __DSB(); - __ISB(); - if(dcache_end == dcache_original) - { - uhs_phy_printf("dcache state right , dcache_state=%lx\r\n",dcache_end); - } - else - { - uhs_phy_printf("dcache state error\r\n"); - } - - uhs_phy_delay_us(1000); - -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_usb.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_usb.c deleted file mode 100644 index aa0d23b852..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_usb.c +++ /dev/null @@ -1,1939 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_usb.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_usb.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup USB - * @{ - */ - -/** @defgroup USB_Private_Macros - * @{ - */ - -/*@} end of group USB_Private_Macros */ - -/** @defgroup USB_Private_Types - * @{ - */ - -/*@} end of group USB_Private_Types */ - -/** @defgroup USB_Private_Variables - * @{ - */ - -/*@} end of group USB_Private_Variables */ - -/** @defgroup USB_Global_Variables - * @{ - */ - -/*@} end of group USB_Global_Variables */ - -/** @defgroup USB_Private_Fun_Declaration - * @{ - */ - -/*@} end of group USB_Private_Fun_Declaration */ - -/** @defgroup USB_Private_Functions - * @{ - */ - -/*@} end of group USB_Private_Functions */ - -/** @defgroup USB_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief USB global interrupt enable or disable - * - * @param enable: ENABLE or DISABLE - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Global_IntEnable(uint8_t enable) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(USB_BASE, USB_DEV_CTL); - - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, USB_GLINT_EN_HOV); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, USB_GLINT_EN_HOV); - } - - BL_WR_REG(USB_BASE, USB_DEV_CTL, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief USB global interrupt mask or unmask - * - * @param intType: interrupt type - * @param intMask: MASK or UNMASK - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Global_IntMask(USB_GLOBAL_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_USB_GLOBAL_INT_TYPE(intType)); - - tmpVal = BL_RD_REG(USB_BASE, USB_GLB_INT); - - if (intMask == MASK) { - tmpVal = tmpVal | (1 << intType); - } else { - tmpVal = tmpVal & ~(1 << intType); - } - - BL_WR_REG(USB_BASE, USB_GLB_INT, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get USB global interrupt status - * - * @param intType: interrupt type - * - * @return SET or RESET - * -*******************************************************************************/ -BL_Sts_Type USB_Global_IntStatus(USB_GLOBAL_INT_Type intType) -{ - CHECK_PARAM(IS_USB_GLOBAL_INT_TYPE(intType)); - - return (BL_RD_REG(USB_BASE, USB_GLB_ISR) & (1 << intType)) ? SET : RESET; -} - -/****************************************************************************/ /** - * @brief set USB normal configuration - * - * @param cfg: configuration - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Set_Normal_Config(USB_NORMAL_Cfg_Type *cfg) -{ - uint32_t tmpVal = 0; - uint32_t to = 0; - - if (cfg->swRst) { - tmpVal = BL_RD_REG(USB_BASE, USB_DEV_CTL); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_SFRST_HOV); - BL_WR_REG(USB_BASE, USB_DEV_CTL, tmpVal); - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(USB_BASE, USB_DEV_CTL), USB_SFRST_HOV)) { - if (to >= cfg->rstTimeOut) { - return ERROR; - } - - to++; - } - } - - tmpVal = BL_RD_REG(USB_BASE, USB_DEV_CTL); - - if (cfg->forceFullSpeed) { - tmpVal = BL_SET_REG_BIT(tmpVal, USB_FORCE_FS); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, USB_FORCE_FS); - } - - if (cfg->remoteWakeupEn) { - tmpVal = BL_SET_REG_BIT(tmpVal, USB_CAP_RMWAKUP); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CAP_RMWAKUP); - } - - BL_WR_REG(USB_BASE, USB_DEV_CTL, tmpVal); - - tmpVal = BL_RD_REG(USB_BASE, USB_DEV_CTL); - - if (cfg->chipEn) { - tmpVal = BL_SET_REG_BIT(tmpVal, USB_CHIP_EN_HOV); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CHIP_EN_HOV); - } - - BL_WR_REG(USB_BASE, USB_DEV_CTL, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get USB device speed - * - * @param None - * - * @return high speed or full speed - * -*******************************************************************************/ -USB_DEVICE_SPEED_Type USB_Get_Device_Speed_Status(void) -{ - return (USB_DEVICE_SPEED_Type)BL_GET_REG_BITS_VAL(BL_RD_REG(USB_BASE, USB_DEV_CTL), USB_HS_EN_HOV); -} - -/****************************************************************************/ /** - * @brief USB go suspend - * - * @param enable: ENABLE or DISABLE - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Go_Suspend(uint8_t enable) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(USB_BASE, USB_DEV_CTL); - - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, USB_GOSUSP); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, USB_GOSUSP); - } - - BL_WR_REG(USB_BASE, USB_DEV_CTL, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set USB device address - * - * @param addr: address - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Set_Device_Address(uint8_t addr) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM((addr <= 127)); - - tmpVal = BL_RD_REG(USB_BASE, USB_DEV_ADR); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_DEVADR, addr); - BL_WR_REG(USB_BASE, USB_DEV_ADR, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get USB device address - * - * @param None - * - * @return address - * -*******************************************************************************/ -uint8_t USB_Get_Device_Address(void) -{ - return BL_GET_REG_BITS_VAL(BL_RD_REG(USB_BASE, USB_DEV_ADR), USB_DEVADR); -} - -/****************************************************************************/ /** - * @brief USB non-control transfer enable - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Non_Ctrl_Transfer_Enable(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(USB_BASE, USB_DEV_ADR); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_AFT_CONF); - BL_WR_REG(USB_BASE, USB_DEV_ADR, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief USB non-control transfer disable - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Non_Ctrl_Transfer_Disable(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(USB_BASE, USB_DEV_ADR); - tmpVal = BL_CLR_REG_BIT(tmpVal, USB_AFT_CONF); - BL_WR_REG(USB_BASE, USB_DEV_ADR, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief USB FIFO counters and location counters clear - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Clear_FIFO(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(USB_BASE, USB_DEV_TST); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_TST_CLRFF_HOV); - BL_WR_REG(USB_BASE, USB_DEV_TST, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief USB SOF mask timer in high speed - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_SOF_Mask_Time_HighSpeed(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(USB_BASE, USB_DEV_SMT); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_SOFMT, USB_SOF_TIMER_MASK_AFTER_RESET_HS); - BL_WR_REG(USB_BASE, USB_DEV_SMT, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief USB SOF mask timer in full speed - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_SOF_Mask_Time_FullSpeed(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(USB_BASE, USB_DEV_SMT); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_SOFMT, USB_SOF_TIMER_MASK_AFTER_RESET_FS); - BL_WR_REG(USB_BASE, USB_DEV_SMT, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief USB SOF mask timer in full speed - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_SoftDetach_Enable(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(USB_BASE, USB_PHY_TST); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_UNPLUG); - BL_WR_REG(USB_BASE, USB_PHY_TST, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief USB SOF mask timer in full speed - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_SoftDetach_Disable(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(USB_BASE, USB_PHY_TST); - tmpVal = BL_CLR_REG_BIT(tmpVal, USB_UNPLUG); - BL_WR_REG(USB_BASE, USB_PHY_TST, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief is USB FIFOn empty - * - * @param fifoNum: FIFO number - * - * @return SET or RESET - * -*******************************************************************************/ -BL_Sts_Type USB_Is_FIFO_Empty(USB_FIFO_EMPTY_Type fifoNum) -{ - CHECK_PARAM(IS_USB_FIFO_EMPTY_TYPE(fifoNum)); - - return (BL_RD_REG(USB_BASE, USB_DEV_CXCFE) & (1 << fifoNum)) ? SET : RESET; -} - -/****************************************************************************/ /** - * @brief is USB control FIFO empty - * - * @param None - * - * @return SET or RESET - * -*******************************************************************************/ -BL_Sts_Type USB_Is_CTRL_FIFO_Empty(void) -{ - return BL_GET_REG_BITS_VAL(BL_RD_REG(USB_BASE, USB_DEV_CXCFE), USB_CX_EMP) ? SET : RESET; -} - -/****************************************************************************/ /** - * @brief is USB control FIFO full - * - * @param None - * - * @return SET or RESET - * -*******************************************************************************/ -BL_Sts_Type USB_Is_CTRL_FIFO_Full(void) -{ - return BL_GET_REG_BITS_VAL(BL_RD_REG(USB_BASE, USB_DEV_CXCFE), USB_CX_FUL) ? SET : RESET; -} - -/****************************************************************************/ /** - * @brief is USB control FIFO full - * - * @param None - * - * @return SET or RESET - * -*******************************************************************************/ -BL_Err_Type USB_Clear_CTRL_FIFO(void) -{ - BL_WR_REG(USB_BASE, USB_DEV_CXCFE, BL_SET_REG_BIT(0, USB_CX_CLR)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set USB control endpoint stall once - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Set_CTRL_Endpoint_Stall_Once(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(USB_BASE, USB_DEV_CXCFE); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_CX_STL); - BL_WR_REG(USB_BASE, USB_DEV_CXCFE, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set USB control endpoint data transfer done - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_CTRL_Endpoint_Data_Transfer_Done(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(USB_BASE, USB_DEV_CXCFE); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_CX_DONE); - BL_WR_REG(USB_BASE, USB_DEV_CXCFE, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief is USB endpoint receive 0 length data packet - * - * @param epID: endpoint number - * - * @return SET or RESET - * -*******************************************************************************/ -BL_Sts_Type USB_Is_Endpoint_Receive_Zero_Length_Packet(USB_Endpoint_Type epID) -{ - /* cannot be USB_Endpoint_0 */ - CHECK_PARAM(IS_USB_ENDPOINT_TYPE(epID)); - - return (BL_RD_REG(USB_BASE, USB_DEV_RXZ) & (1 << (epID - 1))) ? SET : RESET; -} - -/****************************************************************************/ /** - * @brief clear USB endpoint receive 0 length data packet - * - * @param epID: endpoint number - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Clear_Endpoint_Receive_Zero_Length_Packet_Status(USB_Endpoint_Type epID) -{ - /* cannot be USB_Endpoint_0 */ - CHECK_PARAM(IS_USB_ENDPOINT_TYPE(epID)); - - BL_WR_REG(USB_BASE, USB_DEV_RXZ, 1 << (epID - 1)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief reset USB in endpoint data_toggle_sequence - * - * @param epID: endpoint number - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Reset_Endpoint_IN_Data_Toggle_Sequence(USB_Endpoint_Type epID) -{ - uint32_t tmpVal = 0; - uint32_t regAddr = 0; - - /* cannot be USB_Endpoint_0 */ - CHECK_PARAM(IS_USB_ENDPOINT_TYPE(epID)); - - /* calc reg address */ - regAddr = USB_BASE + USB_DEV_INMPS1_OFFSET + (epID - 1) * 4; - - /* clear RSTG_IEPn bit */ - BL_RD_WORD(regAddr); - tmpVal = BL_CLR_REG_BIT(tmpVal, USB_RSTG_IEP1); - BL_WR_WORD(regAddr, tmpVal); - - /* set RSTG_IEPn bit */ - BL_RD_WORD(regAddr); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_RSTG_IEP1); - BL_WR_WORD(regAddr, tmpVal); - - /* clear RSTG_IEPn bit */ - BL_RD_WORD(regAddr); - tmpVal = BL_CLR_REG_BIT(tmpVal, USB_RSTG_IEP1); - BL_WR_WORD(regAddr, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief reset USB out endpoint data_toggle_sequence - * - * @param epID: endpoint number - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Reset_Endpoint_OUT_Data_Toggle_Sequence(USB_Endpoint_Type epID) -{ - uint32_t tmpVal = 0; - uint32_t regAddr = 0; - - /* cannot be USB_Endpoint_0 */ - CHECK_PARAM(IS_USB_ENDPOINT_TYPE(epID)); - - /* calc reg address */ - regAddr = USB_BASE + USB_DEV_OUTMPS1_OFFSET + (epID - 1) * 4; - - /* clear RSTG_IEPn bit */ - BL_RD_WORD(regAddr); - tmpVal = BL_CLR_REG_BIT(tmpVal, USB_RSTG_OEP1); - BL_WR_WORD(regAddr, tmpVal); - - /* set RSTG_IEPn bit */ - BL_RD_WORD(regAddr); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_RSTG_OEP1); - BL_WR_WORD(regAddr, tmpVal); - - /* clear RSTG_IEPn bit */ - BL_RD_WORD(regAddr); - tmpVal = BL_CLR_REG_BIT(tmpVal, USB_RSTG_OEP1); - BL_WR_WORD(regAddr, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief USB endpoint transmit 0 length data packet - * - * @param epID: endpoint number - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Endpoint_Transmit_Zero_Length_Packet(USB_Endpoint_Type epID) -{ - uint32_t tmpVal = 0; - uint32_t regAddr = 0; - - /* cannot be USB_Endpoint_0 */ - CHECK_PARAM(IS_USB_ENDPOINT_TYPE(epID)); - - regAddr = USB_BASE + USB_DEV_INMPS1_OFFSET + 0x04 * (epID - 1); - - tmpVal = BL_RD_WORD(regAddr); - tmpVal |= (1 << USB_TX0BYTE_IEP1_POS); - BL_WR_WORD(regAddr, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief is USB endpoint receive 0 length data packet - * - * @param epID: endpoint number - * - * @return SET or RESET - * -*******************************************************************************/ -BL_Sts_Type USB_Is_Endpoint_Transfer_Zero_Length_Packet(USB_Endpoint_Type epID) -{ - /* cannot be USB_Endpoint_0 */ - CHECK_PARAM(IS_USB_ENDPOINT_TYPE(epID)); - - return (BL_RD_REG(USB_BASE, USB_DEV_TXZ) & (1 << (epID - 1))) ? SET : RESET; -} - -/****************************************************************************/ /** - * @brief clear USB endpoint transfer 0 length data packet status - * - * @param epID: endpoint number - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Clear_Endpoint_Transfer_Zero_Length_Packet_Status(USB_Endpoint_Type epID) -{ - /* cannot be USB_Endpoint_0 */ - CHECK_PARAM(IS_USB_ENDPOINT_TYPE(epID)); - - BL_WR_REG(USB_BASE, USB_DEV_TXZ, 1 << (epID - 1)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set USB IN endpoint stall - * - * @param epID: endpoint number - * @param enable: ENABLE or DISABLE - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Set_Endpoint_IN_Stall(USB_Endpoint_Type epID, uint8_t enable) -{ - uint32_t tmpVal = 0; - uint32_t regAddr = 0; - - /* cannot be USB_Endpoint_0 */ - CHECK_PARAM(IS_USB_ENDPOINT_TYPE(epID)); - - regAddr = USB_BASE + USB_DEV_INMPS1_OFFSET + 0x04 * (epID - 1); - - tmpVal = BL_RD_WORD(regAddr); - - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, USB_STL_IEP1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, USB_STL_IEP1); - } - - BL_WR_WORD(regAddr, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set USB IN endpoint max packet size - * - * @param epID: endpoint number - * @param max: max packet size - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Set_Endpoint_IN_MaxPacketSize(USB_Endpoint_Type epID, uint16_t max) -{ - uint32_t tmpVal = 0; - uint32_t regAddr = 0; - - /* cannot be USB_Endpoint_0 */ - CHECK_PARAM(IS_USB_ENDPOINT_TYPE(epID)); - CHECK_PARAM((max <= 0x7FF)); - - regAddr = USB_BASE + USB_DEV_INMPS1_OFFSET + 0x04 * (epID - 1); - - tmpVal = BL_RD_WORD(regAddr); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_MAXPS_IEP1, max); - BL_WR_WORD(regAddr, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set USB OUT endpoint stall - * - * @param epID: endpoint number - * @param enable: ENABLE or DISABLE - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Set_Endpoint_OUT_Stall(USB_Endpoint_Type epID, uint8_t enable) -{ - uint32_t tmpVal = 0; - uint32_t regAddr = 0; - - /* cannot be USB_Endpoint_0 */ - CHECK_PARAM(IS_USB_ENDPOINT_TYPE(epID)); - - regAddr = USB_BASE + USB_DEV_OUTMPS1_OFFSET + 0x04 * (epID - 1); - - tmpVal = BL_RD_WORD(regAddr); - - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, USB_STL_OEP1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, USB_STL_OEP1); - } - - BL_WR_WORD(regAddr, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set USB OUT endpoint max packet size - * - * @param epID: endpoint number - * @param max: max packet size - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Set_Endpoint_OUT_MaxPacketSize(USB_Endpoint_Type epID, uint16_t max) -{ - uint32_t tmpVal = 0; - uint32_t regAddr = 0; - - /* cannot be USB_Endpoint_0 */ - CHECK_PARAM(IS_USB_ENDPOINT_TYPE(epID)); - CHECK_PARAM((max <= 0x7FF)); - - regAddr = USB_BASE + USB_DEV_OUTMPS1_OFFSET + 0x04 * (epID - 1); - - tmpVal = BL_RD_WORD(regAddr); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_MAXPS_OEP1, max); - BL_WR_WORD(regAddr, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set USB FIFO ID of IN endpoint - * - * @param epID: endpoint number - * @param fifoID: FIFO ID - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Set_FIFO_Of_Endpoint_IN(USB_Endpoint_Type epID, USB_FIFO_Type fifoID) -{ - uint32_t tmpVal = 0; - uint32_t regAddr = 0; - - /* cannot be USB_Endpoint_0 */ - CHECK_PARAM(IS_USB_ENDPOINT_TYPE(epID)); - CHECK_PARAM(IS_USB_FIFO_TYPE(fifoID)); - - if (epID <= USB_Endpoint_4) { - regAddr = USB_BASE + USB_DEV_EPMAP0_OFFSET; - } else { - regAddr = USB_BASE + USB_DEV_EPMAP1_OFFSET; - } - - tmpVal = BL_RD_WORD(regAddr); - - switch (epID) { - case USB_Endpoint_1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_FNO_IEP1, fifoID); - break; - - case USB_Endpoint_2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_FNO_IEP2, fifoID); - break; - - case USB_Endpoint_3: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_FNO_IEP3, fifoID); - break; - - case USB_Endpoint_4: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_FNO_IEP4, fifoID); - break; - - case USB_Endpoint_5: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_FNO_IEP5, fifoID); - break; - - case USB_Endpoint_6: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_FNO_IEP6, fifoID); - break; - - case USB_Endpoint_7: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_FNO_IEP7, fifoID); - break; - - case USB_Endpoint_8: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_FNO_IEP8, fifoID); - break; - - default: - break; - } - - BL_WR_WORD(regAddr, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set USB FIFO ID of IN endpoint - * - * @param epID: endpoint number - * @param fifoID: FIFO ID - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Set_FIFO_Of_Endpoint_OUT(USB_Endpoint_Type epID, USB_FIFO_Type fifoID) -{ - uint32_t tmpVal = 0; - uint32_t regAddr = 0; - - /* cannot be USB_Endpoint_0 */ - CHECK_PARAM(IS_USB_ENDPOINT_TYPE(epID)); - CHECK_PARAM(IS_USB_FIFO_TYPE(fifoID)); - - if (epID <= USB_Endpoint_4) { - regAddr = USB_BASE + USB_DEV_EPMAP0_OFFSET; - } else { - regAddr = USB_BASE + USB_DEV_EPMAP1_OFFSET; - } - - tmpVal = BL_RD_WORD(regAddr); - - switch (epID) { - case USB_Endpoint_1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_FNO_OEP1, fifoID); - break; - - case USB_Endpoint_2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_FNO_OEP2, fifoID); - break; - - case USB_Endpoint_3: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_FNO_OEP3, fifoID); - break; - - case USB_Endpoint_4: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_FNO_OEP4, fifoID); - break; - - case USB_Endpoint_5: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_FNO_OEP5, fifoID); - break; - - case USB_Endpoint_6: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_FNO_OEP6, fifoID); - break; - - case USB_Endpoint_7: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_FNO_OEP7, fifoID); - break; - - case USB_Endpoint_8: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_FNO_OEP8, fifoID); - break; - - default: - break; - } - - BL_WR_WORD(regAddr, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set USB FIFO configuration - * - * @param fifoID: FIFO ID - * @param cfg: configuration - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Set_FIFO_Config(USB_FIFO_Type fifoID, USB_FIFO_Cfg_Type *cfg) -{ - uint32_t tmpVal1 = 0; - uint32_t tmpVal2 = 0; - uint32_t en = 0; - - CHECK_PARAM(IS_USB_FIFO_TYPE(fifoID)); - CHECK_PARAM(IS_USB_FIFO_DIR_TYPE(cfg->dir)); - CHECK_PARAM(IS_USB_ENDPOINT_TYPE(cfg->epID)); - CHECK_PARAM(IS_USB_FIFO_BLOCK_MAX_SIZE_TYPE(cfg->blockSize)); - CHECK_PARAM(IS_USB_FIFO_BLOCK_CNT_TYPE(cfg->blockType)); - CHECK_PARAM(IS_USB_FIFO_TRANSFER_TYPE(cfg->fifoType)); - - tmpVal1 = BL_RD_REG(USB_BASE, USB_DEV_FMAP); - tmpVal2 = BL_RD_REG(USB_BASE, USB_DEV_FCFG); - - if (cfg->enable) { - en = 1; - } - - switch (fifoID) { - case USB_FIFO_0: - tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, USB_DIR_FIFO0, cfg->dir); - tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, USB_EPNO_FIFO0, cfg->epID); - tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, USB_EN_F0, en); - tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, USB_BLKSZ_F0, cfg->blockSize); - tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, USB_BLKNO_F0, cfg->blockType); - tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, USB_BLK_TYP_F0, cfg->fifoType); - break; - - case USB_FIFO_1: - tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, USB_DIR_FIFO1, cfg->dir); - tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, USB_EPNO_FIFO1, cfg->epID); - tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, USB_EN_F1, en); - tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, USB_BLKSZ_F1, cfg->blockSize); - tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, USB_BLKNO_F1, cfg->blockType); - tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, USB_BLK_TYP_F1, cfg->fifoType); - break; - - case USB_FIFO_2: - tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, USB_DIR_FIFO2, cfg->dir); - tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, USB_EPNO_FIFO2, cfg->epID); - tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, USB_EN_F2, en); - tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, USB_BLKSZ_F2, cfg->blockSize); - tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, USB_BLKNO_F2, cfg->blockType); - tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, USB_BLK_TYP_F2, cfg->fifoType); - break; - - case USB_FIFO_3: - tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, USB_DIR_FIFO3, cfg->dir); - tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, USB_EPNO_FIFO3, cfg->epID); - tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, USB_EN_F3, en); - tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, USB_BLKSZ_F3, cfg->blockSize); - tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, USB_BLKNO_F3, cfg->blockType); - tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, USB_BLK_TYP_F3, cfg->fifoType); - break; - - default: - break; - } - - BL_WR_REG(USB_BASE, USB_DEV_FMAP, tmpVal1); - BL_WR_REG(USB_BASE, USB_DEV_FCFG, tmpVal2); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief reset USB FIFO - * - * @param fifoID: FIFO ID - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Reset_FIFO(USB_FIFO_Type fifoID) -{ - uint32_t tmpVal = 0; - uint32_t regAddr = 0; - - CHECK_PARAM(IS_USB_FIFO_TYPE(fifoID)); - - regAddr = USB_BASE + USB_DEV_FIBC0_OFFSET + 0x04 * fifoID; - - tmpVal = BL_RD_WORD(regAddr); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_FFRST0_HOV); - BL_WR_WORD(regAddr, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get USB out FIFO count - * - * @param fifoID: FIFO ID - * - * @return FIFO count - * -*******************************************************************************/ -uint16_t USB_Get_OUT_FIFO_Count(USB_FIFO_Type fifoID) -{ - uint32_t regAddr = 0; - - CHECK_PARAM(IS_USB_FIFO_TYPE(fifoID)); - - regAddr = USB_BASE + USB_DEV_FIBC0_OFFSET + 0x04 * fifoID; - - return BL_GET_REG_BITS_VAL(BL_RD_WORD(regAddr), USB_BC_F0); -} - -/****************************************************************************/ /** - * @brief set USB dma configuration - * - * @param cfg: configuration - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Set_DMA_Config(USB_DMA_TARGET_FIFO_Type fifoN, USB_DMA_Cfg_Type *cfg) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_USB_DMA_TRANS_DIR_TYPE(cfg->dir)); - CHECK_PARAM(IS_USB_DMA_TARGET_FIFO_TYPE(fifoN)); - CHECK_PARAM(((cfg->length) <= 0x1FFFF)); - - switch (fifoN) { - case USB_DMA_TARGET_FIFO_CTRL: - tmpVal = (1 << 4); - break; - case USB_DMA_TARGET_FIFO_0: - tmpVal = (1 << 0); - break; - case USB_DMA_TARGET_FIFO_1: - tmpVal = (1 << 1); - break; - case USB_DMA_TARGET_FIFO_2: - tmpVal = (1 << 2); - break; - case USB_DMA_TARGET_FIFO_3: - tmpVal = (1 << 3); - break; - default: - break; - } - BL_WR_REG(USB_BASE, USB_DMA_TFN, tmpVal); - - tmpVal = BL_RD_REG(USB_BASE, USB_DMA_CPS1); - - switch (cfg->dir) { - case USB_DMA_TRANS_DIR_FIFO_2_MEM: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_DMA_IO_HOV, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_DMA_TYPE_HOV, 0); - break; - - case USB_DMA_TRANS_DIR_MEM_2_FIFO: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_DMA_IO_HOV, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_DMA_TYPE_HOV, 1); - break; - - case USB_DMA_TRANS_DIR_FIFO_2_FIFO: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_DMA_IO_HOV, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_DMA_TYPE_HOV, 0); - - if ((cfg->length) & 0x3) { - return ERROR; - } - - break; - - default: - break; - } - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_DMA_LEN_HOV, cfg->length); - BL_WR_REG(USB_BASE, USB_DMA_CPS1, tmpVal); - - BL_WR_REG(USB_BASE, USB_DMA_CPS2, cfg->memAddr); - - return SUCCESS; -} -/****************************************************************************/ /** - * @brief reset usb dma accessing fifo - * - * @param cfg: configuration - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -void USB_Reset_DMA_Accessing_Fifo(void) -{ - BL_WR_REG(USB_BASE, USB_DMA_TFN, 0); -} -/****************************************************************************/ /** - * @brief update USB dma transmit configuration - * - * @param memAddr: memory address - * @param length: transmit length - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Update_DMA_Trans(uint32_t memAddr, uint32_t length) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(USB_BASE, USB_DMA_CPS1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_DMA_LEN_HOV, length); - BL_WR_REG(USB_BASE, USB_DMA_CPS1, tmpVal); - - BL_WR_REG(USB_BASE, USB_DMA_CPS2, memAddr); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief USB dma transmit start - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Set_DMA_Start(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(USB_BASE, USB_DMA_CPS1); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_DMA_START_HOV); - BL_WR_REG(USB_BASE, USB_DMA_CPS1, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get USB setup command - * - * @param setup[2]: buffer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Get_Setup_Command(uint32_t setup[2]) -{ - uint32_t tmpVal = 0; - - if (NULL == setup) { - return ERROR; - } - - tmpVal = BL_RD_REG(USB_BASE, USB_DMA_TFN); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_ACC_CXF_HOV); - BL_WR_REG(USB_BASE, USB_DMA_TFN, tmpVal); - - setup[0] = BL_RD_REG(USB_BASE, USB_DMA_CPS3); - setup[1] = BL_RD_REG(USB_BASE, USB_DMA_CPS3); - - tmpVal = BL_RD_REG(USB_BASE, USB_DMA_TFN); - tmpVal = BL_CLR_REG_BIT(tmpVal, USB_ACC_CXF_HOV); - BL_WR_REG(USB_BASE, USB_DMA_TFN, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set USB vdma configuration - * - * @param fifoN: target FIFO - * @param cfg: configuration - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Set_VDMA_Config(USB_VDMA_TARGET_FIFO_Type fifoN, USB_VDMA_Cfg_Type *cfg) -{ - uint32_t tmpVal = 0; - uint32_t setting1Addr = 0; - uint32_t setting2Addr = 0; - - CHECK_PARAM(IS_USB_VDMA_TARGET_FIFO_TYPE(fifoN)); - CHECK_PARAM(IS_USB_VDMA_TRANS_DIR_TYPE(cfg->dir)); - CHECK_PARAM(((cfg->length) <= 0x1FFFF)); - - setting1Addr = USB_BASE + USB_VDMA_CXFPS1_OFFSET + 0x08 * (fifoN); - setting2Addr = USB_BASE + USB_VDMA_CXFPS2_OFFSET + 0x08 * (fifoN); - tmpVal = BL_RD_WORD(setting1Addr); - - switch (cfg->dir) { - case USB_VDMA_TRANS_DIR_FIFO_2_MEM: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_VDMA_IO_CXF, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_VDMA_TYPE_CXF, 0); - break; - - case USB_VDMA_TRANS_DIR_MEM_2_FIFO: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_VDMA_IO_CXF, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_VDMA_TYPE_CXF, 1); - break; - - case USB_VDMA_TRANS_DIR_FIFO_2_FIFO: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_VDMA_IO_CXF, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_VDMA_TYPE_CXF, 0); - - if ((cfg->length) & 0x3) { - return ERROR; - } - - break; - - default: - break; - } - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_VDMA_LEN_CXF, cfg->length); - BL_WR_WORD(setting1Addr, tmpVal); - - BL_WR_WORD(setting2Addr, cfg->memAddr); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief USB vdma transmit start - * - * @param fifoN: target FIFO - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Set_VDMA_Start(USB_VDMA_TARGET_FIFO_Type fifoN) -{ - uint32_t tmpVal = 0; - uint32_t setting1Addr = 0; - - CHECK_PARAM(IS_USB_VDMA_TARGET_FIFO_TYPE(fifoN)); - - setting1Addr = USB_BASE + USB_VDMA_CXFPS1_OFFSET + 0x08 * (fifoN); - - tmpVal = BL_RD_WORD(setting1Addr); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_VDMA_START_CXF); - BL_WR_WORD(setting1Addr, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get USB vdma transmit start status - * - * @param fifoN: target FIFO - * - * @return SET or RESET - * -*******************************************************************************/ -BL_Sts_Type USB_Get_VDMA_Start(USB_VDMA_TARGET_FIFO_Type fifoN) -{ - uint32_t setting1Addr = 0; - - CHECK_PARAM(IS_USB_VDMA_TARGET_FIFO_TYPE(fifoN)); - - setting1Addr = USB_BASE + USB_VDMA_CXFPS1_OFFSET + 8 * (fifoN); - - return BL_GET_REG_BITS_VAL(BL_RD_WORD(setting1Addr), USB_VDMA_START_CXF) ? SET : RESET; -} - -/****************************************************************************/ /** - * @brief USB vdma multi channel function enable - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Set_VDMA_Enable(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(USB_BASE, USB_VDMA_CTRL); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_VDMA_EN); - BL_WR_REG(USB_BASE, USB_VDMA_CTRL, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set USB LPM configuration - * - * @param cfg: configuration - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Set_LPM_Config(USB_LPM_Cfg_Type *cfg) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_USB_LPM_RESP_TYPE(cfg->resp)); - - tmpVal = BL_RD_REG(USB_BASE, USB_LPM_CAP); - - if (cfg->lpmWakeUpEn) { - tmpVal = BL_SET_REG_BIT(tmpVal, USB_LPM_WAKEUP_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, USB_LPM_WAKEUP_EN); - } - - BL_WR_REG(USB_BASE, USB_LPM_CAP, tmpVal); - - tmpVal = BL_RD_REG(USB_BASE, USB_DEV_CTL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_LPM_ACCEPT, cfg->resp); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_LPM_BESL_MIN, cfg->minBesl); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_LPM_BESL_MAX, cfg->maxBesl); - BL_WR_REG(USB_BASE, USB_DEV_CTL, tmpVal); - - tmpVal = BL_RD_REG(USB_BASE, USB_DEV_CTL); - - if (cfg->lpmEn) { - tmpVal = BL_SET_REG_BIT(tmpVal, USB_LPM_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, USB_LPM_EN); - } - - BL_WR_REG(USB_BASE, USB_DEV_CTL, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set USB LPM configuration - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -uint8_t USB_Get_LPM_BESL(void) -{ - return BL_GET_REG_BITS_VAL(BL_RD_REG(USB_BASE, USB_DEV_CTL), USB_LPM_BESL); -} - -/****************************************************************************/ /** - * @brief set suspend delay - * - * @param ms: delay ms count - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Set_Suspend_Delay(uint8_t ms) -{ - uint32_t tmpVal; - - CHECK_PARAM((ms <= 7)); - - tmpVal = BL_RD_REG(USB_BASE, USB_DEV_ICR); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_IDLE_CNT, ms); - BL_WR_REG(USB_BASE, USB_DEV_ICR, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief USB group interrupt mask or unmask - * - * @param intType: interrupt type - * @param intMask: MASK or UNMASK - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Group_IntMask(USB_GRP_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_USB_GRP_INT_TYPE(intType)); - - tmpVal = BL_RD_REG(USB_BASE, USB_DEV_MIGR); - - if (intMask == MASK) { - tmpVal = tmpVal | (1 << intType); - } else { - tmpVal = tmpVal & ~(1 << intType); - } - - BL_WR_REG(USB_BASE, USB_DEV_MIGR, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get USB group interrupt status - * - * @param intType: interrupt type - * - * @return SET or RESET - * -*******************************************************************************/ -BL_Sts_Type USB_Group_IntStatus(USB_GRP_INT_Type intType) -{ - CHECK_PARAM(IS_USB_GRP_INT_TYPE(intType)); - - return (BL_RD_REG(USB_BASE, USB_DEV_IGR) & (1 << intType)) ? SET : RESET; -} - -/****************************************************************************/ /** - * @brief USB mask sub group interrupt - * - * @param intType: interrupt type, USB_INT_CX_SETUP | USB_INT_CX_IN | ... - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Sub_Group_IntMask(uint64_t intType) -{ - uint64_t val = intType; - uint32_t bit = 0; - uint32_t tmpValG0 = BL_RD_WORD(USB_BASE + USB_DEV_MISG0_OFFSET); - uint32_t tmpValG1 = BL_RD_WORD(USB_BASE + USB_DEV_MISG1_OFFSET); - uint32_t tmpValG2 = BL_RD_WORD(USB_BASE + USB_DEV_MISG2_OFFSET); - uint32_t tmpValG3 = BL_RD_WORD(USB_BASE + USB_DEV_MISG3_OFFSET); - uint32_t tmpValG4 = BL_RD_WORD(USB_BASE + USB_DEV_MISG4_OFFSET); - - while (0 == arch_ctzll(&val, &bit)) { - val &= ~(((uint64_t)1) << bit); - switch (bit) { - case USB_SUB_GRP0_INT_CX_SETUP: - tmpValG0 |= (1 << USB_MCX_SETUP_INT_POS); - break; - case USB_SUB_GRP0_INT_CX_IN: - tmpValG0 |= (1 << USB_MCX_IN_INT_POS); - break; - case USB_SUB_GRP0_INT_CX_OUT: - tmpValG0 |= (1 << USB_MCX_OUT_INT_POS); - break; - case USB_SUB_GRP0_INT_CX_COMFAIL: - tmpValG0 |= (1 << USB_MCX_COMFAIL_INT_POS); - break; - case USB_SUB_GRP0_INT_CX_COMABORT: - tmpValG0 |= (1 << USB_MCX_COMABORT_INT_POS); - break; - case USB_SUB_GRP1_INT_F0_OUT: - tmpValG1 |= (1 << USB_MF0_OUT_INT_POS); - break; - case USB_SUB_GRP1_INT_F0_SPK: - tmpValG1 |= (1 << USB_MF0_SPK_INT_POS); - break; - case USB_SUB_GRP1_INT_F1_OUT: - tmpValG1 |= (1 << USB_MF1_OUT_INT_POS); - break; - case USB_SUB_GRP1_INT_F1_SPK: - tmpValG1 |= (1 << USB_MF1_SPK_INT_POS); - break; - case USB_SUB_GRP1_INT_F2_OUT: - tmpValG1 |= (1 << USB_MF2_OUT_INT_POS); - break; - case USB_SUB_GRP1_INT_F2_SPK: - tmpValG1 |= (1 << USB_MF2_SPK_INT_POS); - break; - case USB_SUB_GRP1_INT_F3_OUT: - tmpValG1 |= (1 << USB_MF3_OUT_INT_POS); - break; - case USB_SUB_GRP1_INT_F3_SPK: - tmpValG1 |= (1 << USB_MF3_SPK_INT_POS); - break; - case USB_SUB_GRP1_INT_F0_IN: - tmpValG1 |= (1 << USB_MF0_IN_INT_POS); - break; - case USB_SUB_GRP1_INT_F1_IN: - tmpValG1 |= (1 << USB_MF1_IN_INT_POS); - break; - case USB_SUB_GRP1_INT_F2_IN: - tmpValG1 |= (1 << USB_MF2_IN_INT_POS); - break; - case USB_SUB_GRP1_INT_F3_IN: - tmpValG1 |= (1 << USB_MF3_IN_INT_POS); - break; - case USB_SUB_GRP2_INT_RESET: - tmpValG2 |= (1 << USB_MUSBRST_INT_POS); - break; - case USB_SUB_GRP2_INT_SUSPEND: - tmpValG2 |= (1 << USB_MSUSP_INT_POS); - break; - case USB_SUB_GRP2_INT_RESUME: - tmpValG2 |= (1 << USB_MRESM_INT_POS); - break; - case USB_SUB_GRP2_INT_TX0BYTE: - tmpValG2 |= (1 << USB_MTX0BYTE_INT_POS); - break; - case USB_SUB_GRP2_INT_RX0BYTE: - tmpValG2 |= (1 << USB_MRX0BYTE_INT_POS); - break; - case USB_SUB_GRP2_INT_DMA_CMPLT: - tmpValG2 |= (1 << USB_MDMA_CMPLT_HOV_POS); - break; - case USB_SUB_GRP2_INT_DMA_ERROR: - tmpValG2 |= (1 << USB_MDMA_ERROR_HOV_POS); - break; - case USB_SUB_GRP2_INT_IDLE: - tmpValG2 |= (1 << USB_MDEV_IDLE_HOV_POS); - break; - case USB_SUB_GRP2_INT_WAKEUP_BY_VBUS: - tmpValG2 |= (1 << USB_MDEV_WAKEUP_BYVBUS_POS); - break; - case USB_SUB_GRP3_INT_VDMA_CMPLT_CXF: - tmpValG3 |= (1 << USB_MVDMA_CMPLT_CXF_POS); - break; - case USB_SUB_GRP3_INT_VDMA_CMPLT_F0: - tmpValG3 |= (1 << USB_MVDMA_CMPLT_F0_POS); - break; - case USB_SUB_GRP3_INT_VDMA_CMPLT_F1: - tmpValG3 |= (1 << USB_MVDMA_CMPLT_F1_POS); - break; - case USB_SUB_GRP3_INT_VDMA_CMPLT_F2: - tmpValG3 |= (1 << USB_MVDMA_CMPLT_F2_POS); - break; - case USB_SUB_GRP3_INT_VDMA_CMPLT_F3: - tmpValG3 |= (1 << USB_MVDMA_CMPLT_F3_POS); - break; - case USB_SUB_GRP3_INT_VDMA_ERROR_CXF: - tmpValG3 |= (1 << USB_MVDMA_ERROR_CXF_POS); - break; - case USB_SUB_GRP3_INT_VDMA_ERROR_F0: - tmpValG3 |= (1 << USB_MVDMA_ERROR_F0_POS); - break; - case USB_SUB_GRP3_INT_VDMA_ERROR_F1: - tmpValG3 |= (1 << USB_MVDMA_ERROR_F1_POS); - break; - case USB_SUB_GRP3_INT_VDMA_ERROR_F2: - tmpValG3 |= (1 << USB_MVDMA_ERROR_F2_POS); - break; - case USB_SUB_GRP3_INT_VDMA_ERROR_F3: - tmpValG3 |= (1 << USB_MVDMA_ERROR_F3_POS); - break; - case USB_SUB_GRP4_INT_L1: - tmpValG4 |= (1 << USB_ML1_INT_POS); - break; - default: - break; - } - } - BL_WR_WORD(USB_BASE + USB_DEV_MISG0_OFFSET, tmpValG0); - BL_WR_WORD(USB_BASE + USB_DEV_MISG1_OFFSET, tmpValG1); - BL_WR_WORD(USB_BASE + USB_DEV_MISG2_OFFSET, tmpValG2); - BL_WR_WORD(USB_BASE + USB_DEV_MISG3_OFFSET, tmpValG3); - BL_WR_WORD(USB_BASE + USB_DEV_MISG4_OFFSET, tmpValG4); - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief USB unmask sub group interrupt - * - * @param intType: interrupt type, USB_INT_CX_SETUP | USB_INT_CX_IN | ... - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Sub_Group_IntUnmask(uint64_t intType) -{ - uint64_t val = intType; - uint32_t bit = 0; - uint32_t tmpValG0 = BL_RD_WORD(USB_BASE + USB_DEV_MISG0_OFFSET); - uint32_t tmpValG1 = BL_RD_WORD(USB_BASE + USB_DEV_MISG1_OFFSET); - uint32_t tmpValG2 = BL_RD_WORD(USB_BASE + USB_DEV_MISG2_OFFSET); - uint32_t tmpValG3 = BL_RD_WORD(USB_BASE + USB_DEV_MISG3_OFFSET); - uint32_t tmpValG4 = BL_RD_WORD(USB_BASE + USB_DEV_MISG4_OFFSET); - - while (0 == arch_ctzll(&val, &bit)) { - val &= ~(((uint64_t)1) << bit); - switch (bit) { - case USB_SUB_GRP0_INT_CX_SETUP: - tmpValG0 &= ~(1 << USB_MCX_SETUP_INT_POS); - break; - case USB_SUB_GRP0_INT_CX_IN: - tmpValG0 &= ~(1 << USB_MCX_IN_INT_POS); - break; - case USB_SUB_GRP0_INT_CX_OUT: - tmpValG0 &= ~(1 << USB_MCX_OUT_INT_POS); - break; - case USB_SUB_GRP0_INT_CX_COMFAIL: - tmpValG0 &= ~(1 << USB_MCX_COMFAIL_INT_POS); - break; - case USB_SUB_GRP0_INT_CX_COMABORT: - tmpValG0 &= ~(1 << USB_MCX_COMABORT_INT_POS); - break; - case USB_SUB_GRP1_INT_F0_OUT: - tmpValG1 &= ~(1 << USB_MF0_OUT_INT_POS); - break; - case USB_SUB_GRP1_INT_F0_SPK: - tmpValG1 &= ~(1 << USB_MF0_SPK_INT_POS); - break; - case USB_SUB_GRP1_INT_F1_OUT: - tmpValG1 &= ~(1 << USB_MF1_OUT_INT_POS); - break; - case USB_SUB_GRP1_INT_F1_SPK: - tmpValG1 &= ~(1 << USB_MF1_SPK_INT_POS); - break; - case USB_SUB_GRP1_INT_F2_OUT: - tmpValG1 &= ~(1 << USB_MF2_OUT_INT_POS); - break; - case USB_SUB_GRP1_INT_F2_SPK: - tmpValG1 &= ~(1 << USB_MF2_SPK_INT_POS); - break; - case USB_SUB_GRP1_INT_F3_OUT: - tmpValG1 &= ~(1 << USB_MF3_OUT_INT_POS); - break; - case USB_SUB_GRP1_INT_F3_SPK: - tmpValG1 &= ~(1 << USB_MF3_SPK_INT_POS); - break; - case USB_SUB_GRP1_INT_F0_IN: - tmpValG1 &= ~(1 << USB_MF0_IN_INT_POS); - break; - case USB_SUB_GRP1_INT_F1_IN: - tmpValG1 &= ~(1 << USB_MF1_IN_INT_POS); - break; - case USB_SUB_GRP1_INT_F2_IN: - tmpValG1 &= ~(1 << USB_MF2_IN_INT_POS); - break; - case USB_SUB_GRP1_INT_F3_IN: - tmpValG1 &= ~(1 << USB_MF3_IN_INT_POS); - break; - case USB_SUB_GRP2_INT_RESET: - tmpValG2 &= ~(1 << USB_MUSBRST_INT_POS); - break; - case USB_SUB_GRP2_INT_SUSPEND: - tmpValG2 &= ~(1 << USB_MSUSP_INT_POS); - break; - case USB_SUB_GRP2_INT_RESUME: - tmpValG2 &= ~(1 << USB_MRESM_INT_POS); - break; - case USB_SUB_GRP2_INT_TX0BYTE: - tmpValG2 &= ~(1 << USB_MTX0BYTE_INT_POS); - break; - case USB_SUB_GRP2_INT_RX0BYTE: - tmpValG2 &= ~(1 << USB_MRX0BYTE_INT_POS); - break; - case USB_SUB_GRP2_INT_DMA_CMPLT: - tmpValG2 &= ~(1 << USB_MDMA_CMPLT_HOV_POS); - break; - case USB_SUB_GRP2_INT_DMA_ERROR: - tmpValG2 &= ~(1 << USB_MDMA_ERROR_HOV_POS); - break; - case USB_SUB_GRP2_INT_IDLE: - tmpValG2 &= ~(1 << USB_MDEV_IDLE_HOV_POS); - break; - case USB_SUB_GRP2_INT_WAKEUP_BY_VBUS: - tmpValG2 &= ~(1 << USB_MDEV_WAKEUP_BYVBUS_POS); - break; - case USB_SUB_GRP3_INT_VDMA_CMPLT_CXF: - tmpValG3 &= ~(1 << USB_MVDMA_CMPLT_CXF_POS); - break; - case USB_SUB_GRP3_INT_VDMA_CMPLT_F0: - tmpValG3 &= ~(1 << USB_MVDMA_CMPLT_F0_POS); - break; - case USB_SUB_GRP3_INT_VDMA_CMPLT_F1: - tmpValG3 &= ~(1 << USB_MVDMA_CMPLT_F1_POS); - break; - case USB_SUB_GRP3_INT_VDMA_CMPLT_F2: - tmpValG3 &= ~(1 << USB_MVDMA_CMPLT_F2_POS); - break; - case USB_SUB_GRP3_INT_VDMA_CMPLT_F3: - tmpValG3 &= ~(1 << USB_MVDMA_CMPLT_F3_POS); - break; - case USB_SUB_GRP3_INT_VDMA_ERROR_CXF: - tmpValG3 &= ~(1 << USB_MVDMA_ERROR_CXF_POS); - break; - case USB_SUB_GRP3_INT_VDMA_ERROR_F0: - tmpValG3 &= ~(1 << USB_MVDMA_ERROR_F0_POS); - break; - case USB_SUB_GRP3_INT_VDMA_ERROR_F1: - tmpValG3 &= ~(1 << USB_MVDMA_ERROR_F1_POS); - break; - case USB_SUB_GRP3_INT_VDMA_ERROR_F2: - tmpValG3 &= ~(1 << USB_MVDMA_ERROR_F2_POS); - break; - case USB_SUB_GRP3_INT_VDMA_ERROR_F3: - tmpValG3 &= ~(1 << USB_MVDMA_ERROR_F3_POS); - break; - case USB_SUB_GRP4_INT_L1: - tmpValG4 &= ~(1 << USB_ML1_INT_POS); - break; - default: - break; - } - } - BL_WR_WORD(USB_BASE + USB_DEV_MISG0_OFFSET, tmpValG0); - BL_WR_WORD(USB_BASE + USB_DEV_MISG1_OFFSET, tmpValG1); - BL_WR_WORD(USB_BASE + USB_DEV_MISG2_OFFSET, tmpValG2); - BL_WR_WORD(USB_BASE + USB_DEV_MISG3_OFFSET, tmpValG3); - BL_WR_WORD(USB_BASE + USB_DEV_MISG4_OFFSET, tmpValG4); - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get USB sub group 0 interrupt status - * - * @param None - * - * @return interrupt status - * -*******************************************************************************/ -uint32_t USB_Get_Sub_Group_0_IntStatus(void) -{ - return BL_RD_WORD(USB_BASE + USB_DEV_ISG0_OFFSET); -} - -/****************************************************************************/ /** - * @brief get USB sub group 1 interrupt status - * - * @param None - * - * @return interrupt status - * -*******************************************************************************/ -uint32_t USB_Get_Sub_Group_1_IntStatus(void) -{ - return BL_RD_WORD(USB_BASE + USB_DEV_ISG1_OFFSET); -} - -/****************************************************************************/ /** - * @brief get USB sub group 2 interrupt status - * - * @param None - * - * @return interrupt status - * -*******************************************************************************/ -uint32_t USB_Get_Sub_Group_2_IntStatus(void) -{ - return BL_RD_WORD(USB_BASE + USB_DEV_ISG2_OFFSET); -} - -/****************************************************************************/ /** - * @brief get USB sub group 3 interrupt status - * - * @param None - * - * @return interrupt status - * -*******************************************************************************/ -uint32_t USB_Get_Sub_Group_3_IntStatus(void) -{ - return BL_RD_WORD(USB_BASE + USB_DEV_ISG3_OFFSET); -} - -/****************************************************************************/ /** - * @brief get USB sub group 4 interrupt status - * - * @param None - * - * @return interrupt status - * -*******************************************************************************/ -uint32_t USB_Get_Sub_Group_4_IntStatus(void) -{ - return BL_RD_WORD(USB_BASE + USB_DEV_ISG4_OFFSET); -} - -/****************************************************************************/ /** - * @brief get USB sub group 0 interrupt mask - * - * @param None - * - * @return interrupt mask - * -*******************************************************************************/ -uint32_t USB_Get_Sub_Group_0_IntMask(void) -{ - return BL_RD_WORD(USB_BASE + USB_DEV_MISG0_OFFSET); -} - -/****************************************************************************/ /** - * @brief get USB sub group 1 interrupt mask - * - * @param None - * - * @return interrupt mask - * -*******************************************************************************/ -uint32_t USB_Get_Sub_Group_1_IntMask(void) -{ - return BL_RD_WORD(USB_BASE + USB_DEV_MISG1_OFFSET); -} - -/****************************************************************************/ /** - * @brief get USB sub group 2 interrupt mask - * - * @param None - * - * @return interrupt mask - * -*******************************************************************************/ -uint32_t USB_Get_Sub_Group_2_IntMask(void) -{ - return BL_RD_WORD(USB_BASE + USB_DEV_MISG2_OFFSET); -} - -/****************************************************************************/ /** - * @brief get USB sub group 3 interrupt mask - * - * @param None - * - * @return interrupt mask - * -*******************************************************************************/ -uint32_t USB_Get_Sub_Group_3_IntMask(void) -{ - return BL_RD_WORD(USB_BASE + USB_DEV_MISG3_OFFSET); -} - -/****************************************************************************/ /** - * @brief get USB sub group 4 interrupt mask - * - * @param None - * - * @return interrupt mask - * -*******************************************************************************/ -uint32_t USB_Get_Sub_Group_4_IntMask(void) -{ - return BL_RD_WORD(USB_BASE + USB_DEV_MISG4_OFFSET); -} - -/****************************************************************************/ /** - * @brief clear USB sub group 0 interrupt status - * - * @param clrVal: clear value - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Get_Sub_Group_0_IntClear(uint32_t clrVal) -{ - BL_WR_WORD(USB_BASE + USB_DEV_ISG0_OFFSET, clrVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief clear USB sub group 1 interrupt status - * - * @param clrVal: clear value - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Get_Sub_Group_1_IntClear(uint32_t clrVal) -{ - BL_WR_WORD(USB_BASE + USB_DEV_ISG1_OFFSET, clrVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief clear USB sub group 2 interrupt status - * - * @param clrVal: clear value - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Get_Sub_Group_2_IntClear(uint32_t clrVal) -{ - BL_WR_WORD(USB_BASE + USB_DEV_ISG2_OFFSET, clrVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief clear USB sub group 3 interrupt status - * - * @param clrVal: clear value - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Get_Sub_Group_3_IntClear(uint32_t clrVal) -{ - BL_WR_WORD(USB_BASE + USB_DEV_ISG3_OFFSET, clrVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief clear USB sub group 4 interrupt status - * - * @param clrVal: clear value - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Get_Sub_Group_4_IntClear(uint32_t clrVal) -{ - BL_WR_WORD(USB_BASE + USB_DEV_ISG4_OFFSET, clrVal); - - return SUCCESS; -} - -/*@} end of group USB_Public_Functions */ - -/*@} end of group USB */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_xip_sflash.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_xip_sflash.c deleted file mode 100644 index b6c7b11c98..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_xip_sflash.c +++ /dev/null @@ -1,469 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_xip_sflash.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "string.h" -#include "bl808_xip_sflash.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup XIP_SFLASH - * @{ - */ - -/** @defgroup XIP_SFLASH_Private_Macros - * @{ - */ - -/*@} end of group XIP_SFLASH_Private_Macros */ - -/** @defgroup XIP_SFLASH_Private_Types - * @{ - */ - -/*@} end of group XIP_SFLASH_Private_Types */ - -/** @defgroup XIP_SFLASH_Private_Variables - * @{ - */ - -/*@} end of group XIP_SFLASH_Private_Variables */ - -/** @defgroup XIP_SFLASH_Global_Variables - * @{ - */ - -/*@} end of group XIP_SFLASH_Global_Variables */ - -/** @defgroup XIP_SFLASH_Private_Fun_Declaration - * @{ - */ - -/*@} end of group XIP_SFLASH_Private_Fun_Declaration */ - -/** @defgroup XIP_SFLASH_Private_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Save flash controller state - * - * @param pFlashCfg: Flash config pointer - * @param offset: CPU XIP flash offset pointer - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_State_Save(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t *offset, - uint8_t group, SF_Ctrl_Bank_Select bank) -{ - /* XIP_SFlash_Delay */ - volatile uint32_t i = 32 * 2; - - while (i--) - ; - - if (bank == SF_CTRL_FLASH_BANK1) { - SF_Ctrl_Sbus2_Replace(SF_CTRL_PAD2); - } - SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB); - /* Exit form continous read for accepting command */ - SFlash_Reset_Continue_Read(pFlashCfg); - /* For disable command that is setting register instaed of send command, we need write enable */ - SFlash_DisableBurstWrap(pFlashCfg); - /* Enable 32Bits addr mode again in case reset command make it reset */ - SFlash_Set32BitsAddrMode(pFlashCfg, ENABLE); - if ((pFlashCfg->ioMode & 0x0f) == SF_CTRL_QO_MODE || (pFlashCfg->ioMode & 0x0f) == SF_CTRL_QIO_MODE) { - /* Enable QE again in case reset command make it reset */ - SFlash_Qspi_Enable(pFlashCfg); - } - /* Deburst again to make sure */ - SFlash_DisableBurstWrap(pFlashCfg); - - /* Clear offset setting*/ - *offset = SF_Ctrl_Get_Flash_Image_Offset(group, bank); - SF_Ctrl_Set_Flash_Image_Offset(0, group, bank); - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Restore flash controller state - * - * @param pFlashCfg: Flash config pointer - * @param offset: CPU XIP flash offset - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_State_Restore(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t offset, - uint8_t group, SF_Ctrl_Bank_Select bank) -{ - uint32_t tmp[1]; - SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf; - - SF_Ctrl_Set_Flash_Image_Offset(offset, group, bank); - - if(((pFlashCfg->ioMode>>4)&0x01) == 0) { - if((pFlashCfg->ioMode&0x0f)==SF_CTRL_QO_MODE || (pFlashCfg->ioMode&0x0f)==SF_CTRL_QIO_MODE) { - SFlash_SetBurstWrap(pFlashCfg); - } - } - SFlash_Set32BitsAddrMode(pFlashCfg, ENABLE); - SFlash_Read(pFlashCfg, ioMode, 1, 0x0, (uint8_t *)tmp, sizeof(tmp)); - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank); - if (bank == SF_CTRL_FLASH_BANK1) { - SF_Ctrl_Sbus2_Revoke_replace(); - } - - return SUCCESS; -} -#endif - -/*@} end of group XIP_SFLASH_Private_Functions */ - -/** @defgroup XIP_SFLASH_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Erase flash one region - * - * @param pFlashCfg: Flash config pointer - * @param startaddr: start address to erase - * @param len: data length to erase - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Erase_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t startaddr, int len, - uint8_t group, SF_Ctrl_Bank_Select bank) -{ - BL_Err_Type stat; - uint32_t offset; - uint8_t aesEnable = 0; - SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf; - - XIP_SFlash_Opt_Enter(&aesEnable); - stat = XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank); - - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank); - } else { - stat = SFlash_Erase(pFlashCfg, startaddr, startaddr + len - 1); - XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank); - } - - XIP_SFlash_Opt_Exit(aesEnable); - - return stat; -} -#endif - -/****************************************************************************/ /** - * @brief Program flash one region - * - * @param pFlashCfg: Flash config pointer - * @param addr: start address to be programed - * @param data: data pointer to be programed - * @param len: data length to be programed - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Write_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len, - uint8_t group, SF_Ctrl_Bank_Select bank) -{ - BL_Err_Type stat; - uint32_t offset; - uint8_t aesEnable = 0; - SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf; - - XIP_SFlash_Opt_Enter(&aesEnable); - stat = XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank); - - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank); - } else { - stat = SFlash_Program(pFlashCfg, ioMode, addr, data, len); - XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank); - } - - XIP_SFlash_Opt_Exit(aesEnable); - - return stat; -} -#endif - -/****************************************************************************/ /** - * @brief Read data from flash - * - * @param pFlashCfg: Flash config pointer - * @param addr: flash read start address - * @param data: data pointer to store data read from flash - * @param len: data length to read - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len, - uint8_t group, SF_Ctrl_Bank_Select bank) -{ - BL_Err_Type stat; - uint32_t offset; - uint8_t aesEnable = 0; - SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf; - - XIP_SFlash_Opt_Enter(&aesEnable); - stat = XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank); - - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank); - } else { - stat = SFlash_Read(pFlashCfg, ioMode, 0, addr, data, len); - XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank); - } - - XIP_SFlash_Opt_Exit(aesEnable); - - return stat; -} -#endif - -/****************************************************************************/ /** - * @brief Get Flash Jedec ID - * - * @param pFlashCfg: Flash config pointer - * @param data: data pointer to store Jedec ID Read from flash - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetJedecId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data, - uint8_t group, SF_Ctrl_Bank_Select bank) -{ - BL_Err_Type stat; - uint32_t offset; - uint8_t aesEnable = 0; - SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf; - - XIP_SFlash_Opt_Enter(&aesEnable); - stat = XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank); - - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank); - } else { - SFlash_GetJedecId(pFlashCfg, data); - XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank); - } - - XIP_SFlash_Opt_Exit(aesEnable); - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Get Flash Device ID - * - * @param pFlashCfg: Flash config pointer - * @param is32BitsAddr: Is flash addr mode in 32-bits - * @param data: data pointer to store Device ID Read from flash - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetDeviceId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, BL_Fun_Type is32BitsAddr, uint8_t *data, - uint8_t group, SF_Ctrl_Bank_Select bank) -{ - BL_Err_Type stat; - uint32_t offset; - uint8_t aesEnable = 0; - SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf; - - XIP_SFlash_Opt_Enter(&aesEnable); - stat = XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank); - - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank); - } else { - SFlash_GetDeviceId(data, is32BitsAddr); - XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank); - } - - XIP_SFlash_Opt_Exit(aesEnable); - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Get Flash Unique ID - * - * @param pFlashCfg: Flash config pointer - * @param data: data pointer to store Device ID Read from flash - * @param idLen: Unique id len - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetUniqueId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data, uint8_t idLen, - uint8_t group, SF_Ctrl_Bank_Select bank) -{ - BL_Err_Type stat; - uint32_t offset; - uint8_t aesEnable = 0; - SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf; - - XIP_SFlash_Opt_Enter(&aesEnable); - stat = XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank); - - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank); - } else { - SFlash_GetUniqueId(data, idLen); - XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank); - } - - XIP_SFlash_Opt_Exit(aesEnable); - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Read data from flash via XIP - * - * @param addr: flash read start address - * @param data: data pointer to store data read from flash - * @param len: data length to read - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr, uint8_t *data, uint32_t len, - uint8_t group, SF_Ctrl_Bank_Select bank) -{ - uint32_t offset; - - addr = addr & (BL808_FLASH_XIP_END-BL808_FLASH_XIP_BASE-1); - addr |= BL808_FLASH_XIP_BASE; - - offset = SF_Ctrl_Get_Flash_Image_Offset(group, bank); - SF_Ctrl_Set_Flash_Image_Offset(0, group, bank); - /* Flash read */ - ARCH_MemCpy_Fast(data, (void *)(uintptr_t)(addr), len); - SF_Ctrl_Set_Flash_Image_Offset(offset, group, bank); - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief XIP SFlash option save - * - * @param aesEnable: AES enable status pointer - * - * @return None - * -*******************************************************************************/ -__WEAK -void ATTR_TCM_SECTION XIP_SFlash_Opt_Enter(uint8_t *aesEnable) -{ - *aesEnable = SF_Ctrl_Is_AES_Enable(); - - if (*aesEnable) { - SF_Ctrl_AES_Disable(); - } -} - -/****************************************************************************/ /** - * @brief XIP SFlash option restore - * - * @param aesEnable: AES enable status - * - * @return None - * -*******************************************************************************/ -__WEAK -void ATTR_TCM_SECTION XIP_SFlash_Opt_Exit(uint8_t aesEnable) -{ - if (aesEnable) { - SF_Ctrl_AES_Enable(); - } -} - -/*@} end of group XIP_SFLASH_Public_Functions */ - -/*@} end of group XIP_SFLASH */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/bl_math/arm_dsp_wrapper.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/bl_math/arm_dsp_wrapper.c deleted file mode 100644 index 05c627927f..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/bl_math/arm_dsp_wrapper.c +++ /dev/null @@ -1,50 +0,0 @@ -/** - * @file arm_dsp_wrapper.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ - -#include "arm_dsp_wrapper.h" - -void arm_fill_f32(float32_t value, float32_t *pDst, uint32_t blockSize) -{ - uint32_t blkCnt = blockSize >> 2u; - - float32_t in1 = value; - float32_t in2 = value; - float32_t in3 = value; - float32_t in4 = value; - - while (blkCnt > 0u) { - *pDst++ = in1; - *pDst++ = in2; - *pDst++ = in3; - *pDst++ = in4; - - blkCnt--; - } - - blkCnt = blockSize % 0x4u; - - while (blkCnt > 0u) { - *pDst++ = value; - blkCnt--; - } -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/bl_math/arm_dsp_wrapper.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/bl_math/arm_dsp_wrapper.h deleted file mode 100644 index 45c87cd526..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/bl_math/arm_dsp_wrapper.h +++ /dev/null @@ -1,44 +0,0 @@ -/** - * @file arm_dsp_wrapper.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ - -#ifndef __MY_MATH_F_H__ -#define __MY_MATH_F_H__ - -#include "misc.h" -#include "math.h" - -typedef float float32_t; - -__INLINE__ float32_t arm_sqrt_f32(float32_t x) -{ - return sqrtf(x); -} - -__INLINE__ float32_t arm_cos_f32(float32_t x) -{ - return cosf(x); -} - -void arm_fill_f32(float32_t value, float32_t *pDst, uint32_t blockSize); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/device/drv_device.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/device/drv_device.c deleted file mode 100644 index e746501e0c..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/device/drv_device.c +++ /dev/null @@ -1,294 +0,0 @@ -/** - * @file drv_device.c - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#include "drv_device.h" - -#define DEVICE_CHECK_PARAM - -#define dev_open (dev->open) -#define dev_close (dev->close) -#define dev_read (dev->read) -#define dev_write (dev->write) -#define dev_control (dev->control) - -dlist_t device_head = DLIST_OBJECT_INIT(device_head); - -/** - * This function get device list header - * - * @param None - * - * @return device header - */ -dlist_t *device_get_list_header(void) -{ - return &device_head; -} - -/** - * This function registers a device driver with specified name. - * - * @param dev the pointer of device driver structure - * @param name the device driver's name - * @param flags the capabilities flag of device - * - * @return the error code, DEVICE_EOK on initialization successfully. - */ -int device_register(struct device *dev, const char *name) -{ - dlist_t *node; - - dlist_for_each(node, &device_head) - { - struct device *dev_obj; - dev_obj = dlist_entry(node, struct device, list); - - if (dev_obj == dev) { - return -DEVICE_EEXIST; - } - } - - strcpy(dev->name, name); - - dlist_insert_after(&device_head, &(dev->list)); - dev->status = DEVICE_REGISTERED; - return DEVICE_EOK; -} - -/** - * This function unregisters a device driver with specified name. - * - * @param dev the pointer of device driver structure - * @param name the device driver's name - * @param flags the capabilities flag of device - * - * @return the error code, DEVICE_EOK on initialization successfully. - */ -int device_unregister(const char *name) -{ - struct device *dev = device_find(name); - - if (!dev) { - return -DEVICE_ENODEV; - } - dev->status = DEVICE_UNREGISTER; - /* remove from old list */ - dlist_remove(&(dev->list)); - return DEVICE_EOK; -} - -/** - * This function finds a device driver by specified name. - * - * @param name the device driver's name - * - * @return the registered device driver on successful, or NULL on failure. - */ -struct device *device_find(const char *name) -{ - struct device *dev; - dlist_t *node; - - dlist_for_each(node, &device_head) - { - dev = dlist_entry(node, struct device, list); - - if (strncmp(dev->name, name, DEVICE_NAME_MAX) == 0) { - return dev; - } - } - return NULL; -} - -/** - * This function will open a device - * - * @param dev the pointer of device driver structure - * @param oflag the flags for device open - * - * @return the result - */ -int device_open(struct device *dev, uint16_t oflag) -{ -#ifdef DEVICE_CHECK_PARAM - int retval = DEVICE_EOK; - - if ((dev->status == DEVICE_REGISTERED) || (dev->status == DEVICE_CLOSED)) { - if (dev_open != NULL) { - retval = dev_open(dev, oflag); - dev->status = DEVICE_OPENED; - dev->oflag |= oflag; - } else { - retval = -DEVICE_EFAULT; - } - } else { - retval = -DEVICE_EINVAL; - } - - return retval; -#else - return dev_open(dev, oflag); -#endif -} -/** - * This function will close a device - * - * @param dev the pointer of device driver structure - * - * @return the result - */ -int device_close(struct device *dev) -{ -#ifdef DEVICE_CHECK_PARAM - int retval = DEVICE_EOK; - - if (dev->status == DEVICE_OPENED) { - if (dev_close != NULL) { - retval = dev_close(dev); - dev->status = DEVICE_CLOSED; - dev->oflag = 0; - } else { - retval = -DEVICE_EFAULT; - } - } else { - retval = -DEVICE_EINVAL; - } - - return retval; -#else - return dev_close(dev); -#endif -} -/** - * This function will perform a variety of control functions on devices. - * - * @param dev the pointer of device driver structure - * @param cmd the command sent to device - * @param arg the argument of command - * - * @return the result - */ -int device_control(struct device *dev, int cmd, void *args) -{ -#ifdef DEVICE_CHECK_PARAM - int retval = DEVICE_EOK; - - if (dev->status > DEVICE_UNREGISTER) { - if (dev_control != NULL) { - retval = dev_control(dev, cmd, args); - } else { - retval = -DEVICE_EFAULT; - } - } else { - retval = -DEVICE_EINVAL; - } - - return retval; -#else - return dev_control(dev, cmd, args); -#endif -} -/** - * This function will write some data to a device. - * - * @param dev the pointer of device driver structure - * @param pos the position of written - * @param buffer the data buffer to be written to device - * @param size the size of buffer - * - * @return the actually written size on successful, otherwise negative returned. - */ -int device_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size) -{ -#ifdef DEVICE_CHECK_PARAM - int retval = DEVICE_EOK; - - if (dev->status == DEVICE_OPENED) { - if (dev_write != NULL) { - retval = dev_write(dev, pos, buffer, size); - } else { - retval = -DEVICE_EFAULT; - } - } else { - retval = -DEVICE_EINVAL; - } - - return retval; -#else - return dev_write(dev, pos, buffer, size); -#endif -} -/** - * This function will read some data from a device. - * - * @param dev the pointer of device driver structure - * @param pos the position of reading - * @param buffer the data buffer to save read data - * @param size the size of buffer - * - * @return the actually read size on successful, otherwise negative returned. - */ -int device_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size) -{ -#ifdef DEVICE_CHECK_PARAM - int retval = DEVICE_EOK; - - if (dev->status == DEVICE_OPENED) { - if (dev_read != NULL) { - retval = dev_read(dev, pos, buffer, size); - } else { - retval = -DEVICE_EFAULT; - } - } else { - retval = -DEVICE_EINVAL; - } - - return retval; -#else - return dev_read(dev, pos, buffer, size); -#endif -} -/** - * This function will read some data from a device. - * - * @param dev the pointer of device driver structure - * @param pos the position of reading - * @param buffer the data buffer to save read data - * @param size the size of buffer - * - * @return the actually read size on successful, otherwise negative returned. - */ -int device_set_callback(struct device *dev, void (*callback)(struct device *dev, void *args, uint32_t size, uint32_t event)) -{ - int retval = DEVICE_EOK; - - if (dev->status > DEVICE_UNREGISTER) { - if (callback != NULL) { - dev->callback = callback; - } else { - retval = -DEVICE_EFAULT; - } - } else { - retval = -DEVICE_EINVAL; - } - - return retval; -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/device/drv_device.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/device/drv_device.h deleted file mode 100644 index 82053757a4..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/device/drv_device.h +++ /dev/null @@ -1,135 +0,0 @@ -/** - * @file drv_device.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __DRV_DEVICE_H__ -#define __DRV_DEVICE_H__ - -#include "drv_list.h" -#include "stdio.h" - -#define DEVICE_NAME_MAX 20 /* max device name*/ - -#define DEVICE_OFLAG_DEFAULT 0x000 /* open with default */ -#define DEVICE_OFLAG_STREAM_TX 0x001 /* open with poll tx */ -#define DEVICE_OFLAG_STREAM_RX 0x002 /* open with poll rx */ -#define DEVICE_OFLAG_INT_TX 0x004 /* open with interrupt tx */ -#define DEVICE_OFLAG_INT_RX 0x008 /* open with interrupt rx */ -#define DEVICE_OFLAG_DMA_TX 0x010 /* open with dma tx */ -#define DEVICE_OFLAG_DMA_RX 0x020 /* open with dma rx */ - -#define DEVICE_CTRL_SET_INT 0x01 /* set interrupt */ -#define DEVICE_CTRL_CLR_INT 0x02 /* clear interrupt */ -#define DEVICE_CTRL_GET_INT 0x03 /* get interrupt status*/ -#define DEVICE_CTRL_RESUME 0x04 /* resume device */ -#define DEVICE_CTRL_SUSPEND 0x05 /* suspend device */ -#define DEVICE_CTRL_CONFIG 0x06 /* config device */ -#define DEVICE_CTRL_GET_CONFIG 0x07 /* get device configuration */ -#define DEVICE_CTRL_ATTACH_TX_DMA 0x08 /* deivce link tx dma */ -#define DEVICE_CTRL_ATTACH_RX_DMA 0x09 /* deivce link rx dma */ -#define DEVICE_CTRL_TX_DMA_SUSPEND 0x0a /* deivce suspend tx dma */ -#define DEVICE_CTRL_RX_DMA_SUSPEND 0x0b /* deivce suspend rx dma */ -#define DEVICE_CTRL_TX_DMA_RESUME 0x0c /* deivce resume tx dma */ -#define DEVICE_CTRL_RX_DMA_RESUME 0x0d /* deivce resume rx dma */ -#define DEVICE_CTRL_RESVD1 0x0E -#define DEVICE_CTRL_RESVD2 0x0F - -/* - * POSIX Error codes - */ - -#define DEVICE_EOK 0 -#define DEVICE_EFAULT 14 /* Bad address */ -#define DEVICE_EEXIST 17 /* device exists */ -#define DEVICE_ENODEV 19 /* No such device */ -#define DEVICE_EINVAL 22 /* Invalid argument */ -#define DEVICE_ENOSPACE 23 /* No more Device for Allocate */ - -#define __ASSERT_PRINT(fmt, ...) printf(fmt, ##__VA_ARGS__) - -#define __ASSERT_LOC(test) \ - __ASSERT_PRINT("ASSERTION FAIL [%s] @ %s:%d\n", \ - #test, \ - __FILE__, __LINE__) - -#define DEVICE_ASSERT(test, fmt, ...) \ - do { \ - if (!(test)) { \ - __ASSERT_LOC(test); \ - __ASSERT_PRINT(fmt, ##__VA_ARGS__); \ - } \ - } while (0) - -enum device_class_type { - DEVICE_CLASS_NONE = 0, - DEVICE_CLASS_GPIO, - DEVICE_CLASS_UART, - DEVICE_CLASS_SPI, - DEVICE_CLASS_I2C, - DEVICE_CLASS_ADC, - DEVICE_CLASS_DAC, - DEVICE_CLASS_DMA, - DEVICE_CLASS_TIMER, - DEVICE_CLASS_PWM, - DEVICE_CLASS_QDEC, - DEVICE_CLASS_SDIO, - DEVICE_CLASS_USB, - DEVICE_CLASS_RMII, - DEVICE_CLASS_I2S, - DEVICE_CLASS_CAMERA, - DEVICE_CLASS_SEC_HASH, - DEVICE_CLASS_KEYSCAN, -}; - -enum device_status_type { - DEVICE_UNREGISTER = 0, - DEVICE_REGISTERED, - DEVICE_OPENED, - DEVICE_CLOSED -}; - -struct device { - char name[DEVICE_NAME_MAX]; /*name of device */ - dlist_t list; /*list node of device */ - enum device_status_type status; /*status of device */ - enum device_class_type type; /*type of device */ - uint16_t oflag; /*oflag of device */ - - int (*open)(struct device *dev, uint16_t oflag); - int (*close)(struct device *dev); - int (*control)(struct device *dev, int cmd, void *args); - int (*write)(struct device *dev, uint32_t pos, const void *buffer, uint32_t size); - int (*read)(struct device *dev, uint32_t pos, void *buffer, uint32_t size); - void (*callback)(struct device *dev, void *args, uint32_t size, uint32_t event); - void *handle; -}; - -int device_register(struct device *dev, const char *name); -int device_unregister(const char *name); -struct device *device_find(const char *name); -int device_open(struct device *dev, uint16_t oflag); -int device_close(struct device *dev); -int device_control(struct device *dev, int cmd, void *args); -int device_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size); -int device_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size); -int device_set_callback(struct device *dev, void (*callback)(struct device *dev, void *args, uint32_t size, uint32_t event)); -dlist_t *device_get_list_header(void); -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/list/drv_list.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/list/drv_list.h deleted file mode 100644 index b0b5181d23..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/list/drv_list.h +++ /dev/null @@ -1,472 +0,0 @@ -/** - * @file drv_list.h - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __DRV_LIST_H__ -#define __DRV_LIST_H__ - -#include "string.h" -#include "stdint.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * container_of - return the member address of ptr, if the type of ptr is the - * struct type. - */ -#define container_of(ptr, type, member) \ - ((type *)((char *)(ptr) - (unsigned long)(&((type *)0)->member))) - -/** - * Double List structure - */ -struct dlist_node { - struct dlist_node *next; /**< point to next node. */ - struct dlist_node *prev; /**< point to prev node. */ -}; -typedef struct dlist_node dlist_t; /**< Type for lists. */ - -/** - * @brief initialize a list - * - * @param l list to be initialized - */ -static inline void dlist_init(dlist_t *l) -{ - l->next = l->prev = l; -} - -/** - * @brief insert a node after a list - * - * @param l list to insert it - * @param n new node to be inserted - */ -static inline void dlist_insert_after(dlist_t *l, dlist_t *n) -{ - l->next->prev = n; - n->next = l->next; - - l->next = n; - n->prev = l; -} - -/** - * @brief insert a node before a list - * - * @param n new node to be inserted - * @param l list to insert it - */ -static inline void dlist_insert_before(dlist_t *l, dlist_t *n) -{ - l->prev->next = n; - n->prev = l->prev; - - l->prev = n; - n->next = l; -} - -/** - * @brief remove node from list. - * @param n the node to remove from the list. - */ -static inline void dlist_remove(dlist_t *n) -{ - n->next->prev = n->prev; - n->prev->next = n->next; - - n->next = n->prev = n; -} - -/** - * @brief move node from list. - * @param n the node to remove from the list. - */ -static inline void dlist_move_head(dlist_t *l, dlist_t *n) -{ - dlist_remove(n); - dlist_insert_after(l, n); -} - -/** - * @brief move node from list. - * @param n the node to remove from the list. - */ -static inline void dlist_move_tail(dlist_t *l, dlist_t *n) -{ - dlist_remove(n); - dlist_insert_before(l, n); -} - -/** - * @brief tests whether a list is empty - * @param l the list to test. - */ -static inline int dlist_isempty(const dlist_t *l) -{ - return l->next == l; -} - -/** - * @brief get the list length - * @param l the list to get. - */ -static inline unsigned int dlist_len(const dlist_t *l) -{ - unsigned int len = 0; - const dlist_t *p = l; - - while (p->next != l) { - p = p->next; - len++; - } - - return len; -} - -/** - * @brief initialize a dlist object - */ -#define DLIST_OBJECT_INIT(object) \ - { \ - &(object), &(object) \ - } -/** - * @brief initialize a dlist object - */ -#define DLIST_DEFINE(list) \ - dlist_t list = { &(list), &(list) } - -/** - * dlist_first_entry - get the first element from a list - * @ptr: the list head to take the element from. - * @type: the type of the struct this is embedded in. - * @member: the name of the list_struct within the struct. - * - * Note, that list is expected to be not empty. - */ -#define dlist_first_entry(ptr, type, member) \ - dlist_entry((ptr)->next, type, member) -/** - * dlist_first_entry_or_null - get the first element from a list - * @ptr: the list head to take the element from. - * @type: the type of the struct this is embedded in. - * @member: the name of the list_struct within the struct. - * - * Note, that list is expected to be not empty. - */ -#define dlist_first_entry_or_null(ptr, type, member) \ - (dlist_isempty(ptr) ? NULL : dlist_first_entry(ptr, type, member)) - -/** - * @brief get the struct for this entry - * @param node the entry point - * @param type the type of structure - * @param member the name of list in structure - */ -#define dlist_entry(node, type, member) \ - container_of(node, type, member) - -/** - * dlist_for_each - iterate over a list - * @pos: the dlist_t * to use as a loop cursor. - * @head: the head for your list. - */ -#define dlist_for_each(pos, head) \ - for (pos = (head)->next; pos != (head); pos = pos->next) - -/** - * dlist_for_each_prev - iterate over a list - * @pos: the dlist_t * to use as a loop cursor. - * @head: the head for your list. - */ -#define dlist_for_each_prev(pos, head) \ - for (pos = (head)->prev; pos != (head); pos = pos->prev) - -/** - * dlist_for_each_safe - iterate over a list safe against removal of list entry - * @pos: the dlist_t * to use as a loop cursor. - * @n: another dlist_t * to use as temporary storage - * @head: the head for your list. - */ -#define dlist_for_each_safe(pos, n, head) \ - for (pos = (head)->next, n = pos->next; pos != (head); \ - pos = n, n = pos->next) - -#define dlist_for_each_prev_safe(pos, n, head) \ - for (pos = (head)->prev, n = pos->prev; pos != (head); \ - pos = n, n = pos->prev) -/** - * dlist_for_each_entry - iterate over list of given type - * @pos: the type * to use as a loop cursor. - * @head: the head for your list. - * @member: the name of the list_struct within the struct. - */ -#define dlist_for_each_entry(pos, head, member) \ - for (pos = dlist_entry((head)->next, typeof(*pos), member); \ - &pos->member != (head); \ - pos = dlist_entry(pos->member.next, typeof(*pos), member)) - -/** - * dlist_for_each_entry_reverse - iterate over list of given type - * @pos: the type * to use as a loop cursor. - * @head: the head for your list. - * @member: the name of the list_struct within the struct. - */ -#define dlist_for_each_entry_reverse(pos, head, member) \ - for (pos = dlist_entry((head)->prev, typeof(*pos), member); \ - &pos->member != (head); \ - pos = dlist_entry(pos->member.prev, typeof(*pos), member)) - -/** - * dlist_for_each_entry_safe - iterate over list of given type safe against removal of list entry - * @pos: the type * to use as a loop cursor. - * @n: another type * to use as temporary storage - * @head: the head for your list. - * @member: the name of the list_struct within the struct. - */ -#define dlist_for_each_entry_safe(pos, n, head, member) \ - for (pos = dlist_entry((head)->next, typeof(*pos), member), \ - n = dlist_entry(pos->member.next, typeof(*pos), member); \ - &pos->member != (head); \ - pos = n, n = dlist_entry(n->member.next, typeof(*n), member)) - -/** - * dlist_for_each_entry_safe - iterate over list of given type safe against removal of list entry - * @pos: the type * to use as a loop cursor. - * @n: another type * to use as temporary storage - * @head: the head for your list. - * @member: the name of the list_struct within the struct. - */ -#define dlist_for_each_entry_safe_reverse(pos, n, head, member) \ - for (pos = dlist_entry((head)->prev, typeof(*pos), field), \ - n = dlist_entry(pos->member.prev, typeof(*pos), member); \ - &pos->member != (head); \ - pos = n, n = dlist_entry(pos->member.prev, typeof(*pos), member)) - -/** - * Single List structure - */ -struct slist_node { - struct slist_node *next; /**< point to next node. */ -}; -typedef struct slist_node slist_t; /**< Type for single list. */ - -/** - * @brief initialize a single list - * - * @param l the single list to be initialized - */ -static inline void slist_init(slist_t *l) -{ - l->next = NULL; -} - -static inline void slist_add_head(slist_t *l, slist_t *n) -{ - n->next = l->next; - l->next = n; -} - -static inline void slist_add_tail(slist_t *l, slist_t *n) -{ - while (l->next) { - l = l->next; - } - - /* append the node to the tail */ - l->next = n; - n->next = NULL; -} - -static inline void slist_insert(slist_t *l, slist_t *next, slist_t *n) -{ - if (!next) { - slist_add_tail(next, l); - return; - } - - while (l->next) { - if (l->next == next) { - l->next = n; - n->next = next; - } - - l = l->next; - } -} - -static inline slist_t *slist_remove(slist_t *l, slist_t *n) -{ - /* remove slist head */ - while (l->next && l->next != n) { - l = l->next; - } - - /* remove node */ - if (l->next != (slist_t *)0) { - l->next = l->next->next; - } - - return l; -} - -static inline unsigned int slist_len(const slist_t *l) -{ - unsigned int len = 0; - const slist_t *list = l->next; - - while (list != NULL) { - list = list->next; - len++; - } - - return len; -} - -static inline unsigned int slist_contains(slist_t *l, slist_t *n) -{ - while (l->next) { - if (l->next == n) { - return 0; - } - - l = l->next; - } - - return 1; -} - -static inline slist_t *slist_head(slist_t *l) -{ - return l->next; -} - -static inline slist_t *slist_tail(slist_t *l) -{ - while (l->next) { - l = l->next; - } - - return l; -} - -static inline slist_t *slist_next(slist_t *n) -{ - return n->next; -} - -static inline int slist_isempty(slist_t *l) -{ - return l->next == NULL; -} - -/** - * @brief initialize a slist object - */ -#define SLIST_OBJECT_INIT(object) \ - { \ - NULL \ - } - -/** - * @brief initialize a slist object - */ -#define SLIST_DEFINE(slist) \ - slist_t slist = { NULL } - -/** - * @brief get the struct for this single list node - * @param node the entry point - * @param type the type of structure - * @param member the name of list in structure - */ -#define slist_entry(node, type, member) \ - container_of(node, type, member) - -/** - * slist_first_entry - get the first element from a slist - * @ptr: the slist head to take the element from. - * @type: the type of the struct this is embedded in. - * @member: the name of the slist_struct within the struct. - * - * Note, that slist is expected to be not empty. - */ -#define slist_first_entry(ptr, type, member) \ - slist_entry((ptr)->next, type, member) - -/** - * slist_tail_entry - get the tail element from a slist - * @ptr: the slist head to take the element from. - * @type: the type of the struct this is embedded in. - * @member: the name of the slist_struct within the struct. - * - * Note, that slist is expected to be not empty. - */ -#define slist_tail_entry(ptr, type, member) \ - slist_entry(slist_tail(ptr), type, member) - -/** - * slist_first_entry_or_null - get the first element from a slist - * @ptr: the slist head to take the element from. - * @type: the type of the struct this is embedded in. - * @member: the name of the slist_struct within the struct. - * - * Note, that slist is expected to be not empty. - */ -#define slist_first_entry_or_null(ptr, type, member) \ - (slist_isempty(ptr) ? NULL : slist_first_entry(ptr, type, member)) - -/** - * slist_for_each - iterate over a single list - * @pos: the slist_t * to use as a loop cursor. - * @head: the head for your single list. - */ -#define slist_for_each(pos, head) \ - for (pos = (head)->next; pos != NULL; pos = pos->next) - -#define slist_for_each_safe(pos, next, head) \ - for (pos = (head)->next, next = pos->next; pos; \ - pos = next, next = pos->next) - -/** - * slist_for_each_entry - iterate over single list of given type - * @pos: the type * to use as a loop cursor. - * @head: the head for your single list. - * @member: the name of the list_struct within the struct. - */ -#define slist_for_each_entry(pos, head, member) \ - for (pos = slist_entry((head)->next, typeof(*pos), member); \ - &pos->member != (NULL); \ - pos = slist_entry(pos->member.next, typeof(*pos), member)) - -#define slist_for_each_entry_safe(pos, n, head, member) \ - for (pos = slist_entry((head)->next, typeof(*pos), member), \ - n = slist_entry(pos->member.next, typeof(*pos), member); \ - &pos->member != (NULL); \ - pos = n, n = slist_entry(pos->member.next, typeof(*pos), member)) - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/memheap/drv_mmheap.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/memheap/drv_mmheap.c deleted file mode 100644 index 5e053f2597..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/memheap/drv_mmheap.c +++ /dev/null @@ -1,421 +0,0 @@ -/** - * @file drv_mmheap.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ - -#include "drv_mmheap.h" - -#define MEM_MANAGE_ALIGNMENT_BYTE_DEFAULT 8 -#define MEM_MANAGE_BITS_PER_BYTE 8 -#define MEM_MANAGE_MEM_STRUCT_SIZE mmheap_align_up(sizeof(struct heap_node), MEM_MANAGE_ALIGNMENT_BYTE_DEFAULT) -#define MEM_MANAGE_MINUM_MEM_SIZE (MEM_MANAGE_MEM_STRUCT_SIZE << 1) -#define MEM_MANAGE_ALLOCA_LABAL ((size_t)((size_t)1 << (sizeof(size_t) * MEM_MANAGE_BITS_PER_BYTE - 1))) - -static inline size_t mmheap_align_down(size_t data, size_t align_byte) -{ - return data & ~(align_byte - 1); -} - -static inline size_t mmheap_align_up(size_t data, size_t align_byte) -{ - return (data + align_byte - 1) & ~(align_byte - 1); -} - -static inline struct heap_node *mmheap_addr_sub(const void *addr) -{ - return (struct heap_node *)((const uint8_t *)addr - MEM_MANAGE_MEM_STRUCT_SIZE); -} - -static inline void *mmheap_addr_add(const struct heap_node *mem_node) -{ - return (void *)((const uint8_t *)mem_node + MEM_MANAGE_MEM_STRUCT_SIZE); -} - -/** - * @brief mmheap_insert_node_to_freelist - * - * @param pRoot - * @param pNode - */ -static inline void mmheap_insert_node_to_freelist(struct heap_info *pRoot, struct heap_node *pNode) -{ - struct heap_node *pPriv_Node; - struct heap_node *pNext_Node; - /*Find the node with an address similar to pNode*/ - for (pPriv_Node = pRoot->pStart; pPriv_Node->next_node < pNode; pPriv_Node = pPriv_Node->next_node) { - } - - pNext_Node = pPriv_Node->next_node; - /*Try to merge the pNode with the previous block*/ - if ((uint8_t *)mmheap_addr_add(pPriv_Node) + pPriv_Node->mem_size == (uint8_t *)pNode) { - if (pPriv_Node != pRoot->pStart) { /*can merge if not start block*/ - pPriv_Node->mem_size += MEM_MANAGE_MEM_STRUCT_SIZE + pNode->mem_size; - pNode = pPriv_Node; - } else { - /*The latter is not merged if it is a Start block to avoid wasting memory*/ - pRoot->pStart->next_node = pNode; - } - } else { - /*Insert directly into the free single-chain table when merging is not possible*/ - pPriv_Node->next_node = pNode; - } - /*Try to merge the pNode with the next block*/ - if ((uint8_t *)mmheap_addr_add(pNode) + pNode->mem_size == (uint8_t *)pNext_Node) { - if (pNext_Node != pRoot->pEnd) { - pNode->mem_size += MEM_MANAGE_MEM_STRUCT_SIZE + pNext_Node->mem_size; - pNode->next_node = pNext_Node->next_node; - } else { - pNode->next_node = pRoot->pEnd; - } - } else { - /*Insert directly into the free single-chain table when merging is not possible*/ - pNode->next_node = pNext_Node; - } -} - -/** - * @brief mmheap_get_state - * - * @param pRoot - * @param pState - */ -void mmheap_get_state(struct heap_info *pRoot, struct heap_state *pState) -{ - MMHEAP_ASSERT(pRoot->pStart != NULL); - MMHEAP_ASSERT(pRoot->pEnd != NULL); - pState->max_node_size = pRoot->pStart->next_node->mem_size; - pState->min_node_size = pRoot->pStart->next_node->mem_size; - pState->remain_size = 0; - pState->free_node_num = 0; - MMHEAP_LOCK(); - for (struct heap_node *pNode = pRoot->pStart->next_node; pNode->next_node != NULL; pNode = pNode->next_node) { - pState->remain_size += pNode->mem_size; - pState->free_node_num++; - if (pNode->mem_size > pState->max_node_size) - pState->max_node_size = pNode->mem_size; - if (pNode->mem_size < pState->min_node_size) - pState->min_node_size = pNode->mem_size; - } - MMHEAP_UNLOCK(); -} -/** - * @brief mmheap_align_alloc - * - * @param pRoot - * @param align_size - * @param want_size - * @return void* - */ -void *mmheap_align_alloc(struct heap_info *pRoot, size_t align_size, size_t want_size) -{ - void *pReturn = NULL; - struct heap_node *pPriv_Node, *pNow_Node; - - MMHEAP_ASSERT(pRoot->pStart != NULL); - MMHEAP_ASSERT(pRoot->pEnd != NULL); - - if (want_size == 0) { - return NULL; - } - - if ((want_size & MEM_MANAGE_ALLOCA_LABAL) != 0) { - MMHEAP_MALLOC_FAIL(); - return NULL; - } - - if (align_size & (align_size - 1)) { - MMHEAP_MALLOC_FAIL(); - return NULL; - } - - MMHEAP_LOCK(); - if (want_size < MEM_MANAGE_MINUM_MEM_SIZE) - want_size = MEM_MANAGE_MINUM_MEM_SIZE; - if (align_size < MEM_MANAGE_ALIGNMENT_BYTE_DEFAULT) - align_size = MEM_MANAGE_ALIGNMENT_BYTE_DEFAULT; - - want_size = mmheap_align_up(want_size, MEM_MANAGE_ALIGNMENT_BYTE_DEFAULT); - - pPriv_Node = pRoot->pStart; - pNow_Node = pRoot->pStart->next_node; - - while (pNow_Node->next_node != NULL) { - if (pNow_Node->mem_size >= want_size + MEM_MANAGE_MEM_STRUCT_SIZE) { - size_t use_align_size; - size_t new_size; - pReturn = (void *)mmheap_align_up((size_t)mmheap_addr_add(pNow_Node), align_size); /*Calculate the aligned address*/ - use_align_size = (uint8_t *)pReturn - (uint8_t *)mmheap_addr_add(pNow_Node); /*Calculate the memory consumed by the alignment*/ - if (use_align_size != 0) { /*if Memory misalignment*/ - if (use_align_size < MEM_MANAGE_MINUM_MEM_SIZE + MEM_MANAGE_MEM_STRUCT_SIZE) { /*The unaligned value is too small*/ - pReturn = (void *)mmheap_align_up( - (size_t)mmheap_addr_add(pNow_Node) + MEM_MANAGE_MINUM_MEM_SIZE + MEM_MANAGE_MEM_STRUCT_SIZE, align_size); - use_align_size = (uint8_t *)pReturn - (uint8_t *)mmheap_addr_add(pNow_Node); - } - if (use_align_size <= pNow_Node->mem_size) { - new_size = pNow_Node->mem_size - use_align_size; /*Calculate the remaining memory size by removing the memory consumed by alignment*/ - if (new_size >= want_size) { /*Meet the conditions for distribution*/ - struct heap_node *pNew_Node = mmheap_addr_sub(pReturn); - pNow_Node->mem_size -= new_size + MEM_MANAGE_MEM_STRUCT_SIZE; /*Split Node*/ - pNew_Node->mem_size = new_size; /*The new node is also not in the free chain and does not need to be discharged from the free chain*/ - pNew_Node->next_node = NULL; - pNow_Node = pNew_Node; - break; - } - } - } else { /*Memory is directly aligned*/ - pPriv_Node->next_node = pNow_Node->next_node; - pNow_Node->next_node = NULL; - break; - } - } - pPriv_Node = pNow_Node; - pNow_Node = pNow_Node->next_node; - } - - if (pNow_Node == pRoot->pEnd) { - MMHEAP_UNLOCK(); - MMHEAP_MALLOC_FAIL(); - return NULL; - } - - if (pNow_Node->mem_size >= MEM_MANAGE_MINUM_MEM_SIZE + MEM_MANAGE_MEM_STRUCT_SIZE + want_size) { /*Node memory is still available*/ - struct heap_node *pNew_Node = (struct heap_node *)((uint8_t *)mmheap_addr_add(pNow_Node) + want_size); /*Calculate the address of the node that will be moved into the free chain table*/ - pNew_Node->mem_size = pNow_Node->mem_size - want_size - MEM_MANAGE_MEM_STRUCT_SIZE; - pNew_Node->next_node = NULL; - pNow_Node->mem_size = want_size; - mmheap_insert_node_to_freelist(pRoot, pNew_Node); - } - pNow_Node->mem_size |= MEM_MANAGE_ALLOCA_LABAL; - MMHEAP_UNLOCK(); - return pReturn; -} -/** - * @brief mmheap_alloc - * - * @param pRoot - * @param want_size - * @return void* - */ -void *mmheap_alloc(struct heap_info *pRoot, size_t want_size) -{ - return mmheap_align_alloc(pRoot, MEM_MANAGE_ALIGNMENT_BYTE_DEFAULT, want_size); -} -/** - * @brief mmheap_realloc - * - * @param pRoot - * @param src_addr - * @param want_size - * @return void* - */ -void *mmheap_realloc(struct heap_info *pRoot, void *src_addr, size_t want_size) -{ - void *pReturn = NULL; - struct heap_node *pNext_Node, *pPriv_Node; - struct heap_node *pSrc_Node; - MMHEAP_ASSERT(pRoot->pStart != NULL); - MMHEAP_ASSERT(pRoot->pEnd != NULL); - if (src_addr == NULL) { - return mmheap_align_alloc(pRoot, MEM_MANAGE_ALIGNMENT_BYTE_DEFAULT, want_size); - } - if (want_size == 0) { - mmheap_free(pRoot, src_addr); - return NULL; - } - - MMHEAP_LOCK(); - if ((want_size & MEM_MANAGE_ALLOCA_LABAL) != 0) { - MMHEAP_UNLOCK(); - MMHEAP_MALLOC_FAIL(); - return NULL; - } - - pSrc_Node = mmheap_addr_sub(src_addr); - - if ((pSrc_Node->mem_size & MEM_MANAGE_ALLOCA_LABAL) == 0) { - MMHEAP_UNLOCK(); - MMHEAP_ASSERT((pSrc_Node->mem_size & MEM_MANAGE_ALLOCA_LABAL) != 0); - MMHEAP_MALLOC_FAIL(); - return NULL; - } - - pSrc_Node->mem_size &= ~MEM_MANAGE_ALLOCA_LABAL; - if (pSrc_Node->mem_size >= want_size) { - pSrc_Node->mem_size |= MEM_MANAGE_ALLOCA_LABAL; - pReturn = src_addr; - MMHEAP_UNLOCK(); - return pReturn; - } - /*Start looking in the free list for blocks similar to this block*/ - for (pPriv_Node = pRoot->pStart; pPriv_Node->next_node < pSrc_Node; pPriv_Node = pPriv_Node->next_node) { - } - pNext_Node = pPriv_Node->next_node; - - if (pNext_Node != pRoot->pEnd && - ((uint8_t *)src_addr + pSrc_Node->mem_size == (uint8_t *)pNext_Node) && - (pSrc_Node->mem_size + pNext_Node->mem_size + MEM_MANAGE_MEM_STRUCT_SIZE >= want_size)) { - /*Meet next node non-end, memory contiguous, enough memory left*/ - pReturn = src_addr; - pPriv_Node->next_node = pNext_Node->next_node; - pSrc_Node->mem_size += MEM_MANAGE_MEM_STRUCT_SIZE + pNext_Node->mem_size; - want_size = mmheap_align_up(want_size, MEM_MANAGE_ALIGNMENT_BYTE_DEFAULT); - if (pSrc_Node->mem_size >= MEM_MANAGE_MINUM_MEM_SIZE + MEM_MANAGE_MEM_STRUCT_SIZE + want_size) { /*Removing the remaining space allocated is enough to open new blocks*/ - struct heap_node *pNew_Node = (struct heap_node *)((uint8_t *)mmheap_addr_add(pSrc_Node) + want_size); - pNew_Node->next_node = NULL; - pNew_Node->mem_size = pSrc_Node->mem_size - want_size - MEM_MANAGE_MEM_STRUCT_SIZE; - pSrc_Node->mem_size = want_size; - mmheap_insert_node_to_freelist(pRoot, pNew_Node); - } - pSrc_Node->mem_size |= MEM_MANAGE_ALLOCA_LABAL; - MMHEAP_UNLOCK(); - } else { - MMHEAP_UNLOCK(); - pReturn = mmheap_align_alloc(pRoot, MEM_MANAGE_ALIGNMENT_BYTE_DEFAULT, want_size); - if (pReturn == NULL) { - pSrc_Node->mem_size |= MEM_MANAGE_ALLOCA_LABAL; - MMHEAP_MALLOC_FAIL(); - return NULL; - } - MMHEAP_LOCK(); - memcpy(pReturn, src_addr, pSrc_Node->mem_size); - pSrc_Node->mem_size |= MEM_MANAGE_ALLOCA_LABAL; - MMHEAP_UNLOCK(); - mmheap_free(pRoot, src_addr); - } - return pReturn; -} -/** - * @brief - * - * @param pRoot - * @param num - * @param size - * @return void* - */ -void *mmheap_calloc(struct heap_info *pRoot, size_t num, size_t size) -{ - void *pReturn = NULL; - - pReturn = (void *)mmheap_alloc(pRoot, size * num); - - if (pReturn) { - memset(pReturn, 0, num * size); - } - - return pReturn; -} -/** - * @brief mmheap_free - * - * @param pRoot - * @param addr - */ -void mmheap_free(struct heap_info *pRoot, void *addr) -{ - struct heap_node *pFree_Node; - MMHEAP_ASSERT(pRoot->pStart != NULL); - MMHEAP_ASSERT(pRoot->pEnd != NULL); - MMHEAP_LOCK(); - if (addr == NULL) { - MMHEAP_UNLOCK(); - return; - } - pFree_Node = mmheap_addr_sub(addr); - - if ((pFree_Node->mem_size & MEM_MANAGE_ALLOCA_LABAL) == 0) { - MMHEAP_UNLOCK(); - MMHEAP_ASSERT((pFree_Node->mem_size & MEM_MANAGE_ALLOCA_LABAL) != 0); - return; - } - - if (pFree_Node->next_node != NULL) { - MMHEAP_UNLOCK(); - MMHEAP_ASSERT(pFree_Node->next_node == NULL); - return; - } - pFree_Node->mem_size &= ~MEM_MANAGE_ALLOCA_LABAL; - mmheap_insert_node_to_freelist(pRoot, pFree_Node); - MMHEAP_UNLOCK(); -} -/** - * @brief mmheap_init - * - * @param pRoot - * @param pRegion - */ -void mmheap_init(struct heap_info *pRoot, const struct heap_region *pRegion) -{ - struct heap_node *align_addr; - size_t align_size; - struct heap_node *pPriv_node = NULL; - - pRoot->total_size = 0; - pRoot->pEnd = NULL; - pRoot->pStart = NULL; - - for (; pRegion->addr != NULL; pRegion++) { - align_addr = (struct heap_node *)mmheap_align_up((size_t)pRegion->addr, MEM_MANAGE_ALIGNMENT_BYTE_DEFAULT); /*Calculate the aligned address*/ - if ((uint8_t *)align_addr > pRegion->mem_size + (uint8_t *)pRegion->addr) /*Alignment consumes more memory than the memory area*/ - continue; - align_size = pRegion->mem_size - ((uint8_t *)align_addr - (uint8_t *)pRegion->addr); /*Calculate the size of memory left after alignment*/ - if (align_size < MEM_MANAGE_MINUM_MEM_SIZE + MEM_MANAGE_MEM_STRUCT_SIZE) /*if Aligning the remaining memory is too small*/ - continue; - align_size -= MEM_MANAGE_MEM_STRUCT_SIZE; /*Find the size of the memory block after removing the table header*/ - align_addr->mem_size = align_size; - align_addr->next_node = NULL; - if (pRoot->pStart == NULL) { - pRoot->pStart = align_addr; /*set current addr for start*/ - if (align_size >= MEM_MANAGE_MINUM_MEM_SIZE + MEM_MANAGE_MEM_STRUCT_SIZE) { /*If the remaining blocks are large enough*/ - align_size -= MEM_MANAGE_MEM_STRUCT_SIZE; /*Remove the next block of table headers remaining memory size*/ - align_addr = (struct heap_node *)((uint8_t *)pRoot->pStart + MEM_MANAGE_MEM_STRUCT_SIZE); //the next block addr - align_addr->mem_size = align_size; - align_addr->next_node = NULL; - pRoot->pStart->mem_size = 0; - pRoot->pStart->next_node = align_addr; - pRoot->total_size = align_addr->mem_size; - } else { /*The memory is too small, and the address of the current memory block is recorded as start*/ - pRoot->total_size = 0; - pRoot->pStart->mem_size = 0; - } - } else { - pPriv_node->next_node = align_addr; - pRoot->total_size += align_size; - } - pPriv_node = align_addr; - } - //At this point, pPriv_node is the last block, then place the end of the table at the end of the block, find the address to place the end block, end block is only convenient for traversal, so as small as possible, assigned to MEM_MANAGE_MEM_STRUCT_SIZE - align_addr = (struct heap_node *)mmheap_align_down( - (size_t)mmheap_addr_add(pPriv_node) + pPriv_node->mem_size - MEM_MANAGE_MEM_STRUCT_SIZE, MEM_MANAGE_ALIGNMENT_BYTE_DEFAULT); - align_size = (uint8_t *)align_addr - (uint8_t *)mmheap_addr_add(pPriv_node); /*Find the remaining size of the previous block after the end block is allocated*/ - if (align_size >= MEM_MANAGE_MINUM_MEM_SIZE) { - pRoot->total_size -= pPriv_node->mem_size - align_size; /*Removing memory consumed by allocating end blocks*/ - pRoot->pEnd = align_addr; /*Update the address at the end of the list*/ - pPriv_node->next_node = align_addr; - pPriv_node->mem_size = align_size; - align_addr->next_node = NULL; - align_addr->mem_size = 0; /*The end block is not involved in memory allocation, so a direct 0 is sufficient*/ - } else { /*The last block is too small, directly as the end block*/ - pRoot->pEnd = pPriv_node; - pRoot->total_size -= pPriv_node->mem_size; - } - MMHEAP_ASSERT(pRoot->pStart != NULL); - MMHEAP_ASSERT(pRoot->pEnd != NULL); -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/memheap/drv_mmheap.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/memheap/drv_mmheap.h deleted file mode 100644 index 42a7187ce6..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/memheap/drv_mmheap.h +++ /dev/null @@ -1,159 +0,0 @@ -/** - * @file drv_mmheap.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __DRV_MMHEAP_H -#define __DRV_MMHEAP_H - -#include -#include -#include - -#ifndef MMHEAP_LOCK -#define MMHEAP_LOCK() -#endif - -#ifndef MMHEAP_UNLOCK -#define MMHEAP_UNLOCK() -#endif - -#ifndef MMHEAP_ASSERT -#define MMHEAP_ASSERT(A) \ - if (!(A)) \ - printf("mmheap malloc error:drv_mmheap,%d\r\n", __LINE__) - -#endif - -#ifndef MMHEAP_MALLOC_FAIL -#define MMHEAP_MALLOC_FAIL() printf("mmheap malloc fail:drv_mmheap,%d\r\n", __LINE__) -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -struct heap_region { - void *addr; - size_t mem_size; -}; - -struct heap_node { - struct heap_node *next_node; - size_t mem_size; -}; - -struct heap_info { - struct heap_node *pStart; - struct heap_node *pEnd; - size_t total_size; -}; - -struct heap_state { - size_t remain_size; - size_t free_node_num; - size_t max_node_size; - size_t min_node_size; -}; - -void mmheap_init(struct heap_info *pRoot, const struct heap_region *pRigon); -/** - * @brief Alloc start address aligned memory from the heap. - * Alloc aligned address and specified size memory from the heap. - * - * @attention - * - * @param[in] pRoot heap info. - * @param[in] align_size address align mask of the memory. - * @param[in] want_size size of the memory. - * - * @return the pointer to the allocated memory. - */ -void *mmheap_align_alloc(struct heap_info *pRoot, size_t align_size, size_t want_size); -/** - * @brief Alloc memory. - * Allocate size bytes and returns a pointer to the allocated memory. - * - * @attention size should no bigger than MMHEAP_BLK_SIZE_MAX. - * - * @param[in] pRoot heap info. - * @param[in] want_size size of the memory. - * - * @return the pointer to the allocated memory. - */ -void *mmheap_alloc(struct heap_info *pRoot, size_t want_size); -/** - * @brief Realloc memory from the heap. - * Change the size of the memory block pointed to by ptr to size bytes. - * - * @attention - *
    - *
  • if ptr is NULL, then the call is equivalent to mmheap_alloc(size), for all values of size. - *
  • if ptr is if size is equal to zero, and ptr is not NULL, then the call is equivalent to mmheap_free(ptr). - *
- * - * @param[in] pRoot heap info. - * @param[in] src_addr old pointer to the memory space. - * @param[in] want_size new size of the memory space. - * - * @return the new pointer to the allocated memory. - */ -void *mmheap_realloc(struct heap_info *pRoot, void *src_addr, size_t want_size); -/** - * @brief Cealloc memory from the heap. - * Change the size of the memory block pointed to by ptr to size bytes. - * - * @attention - *
    - *
  • if ptr is NULL, then the call is equivalent to mmheap_alloc(size), for all values of size. - *
  • if ptr is if size is equal to zero, and ptr is not NULL, then the call is equivalent to mmheap_free(ptr). - *
- * - * @param[in] pRoot heap info. - * @param[in] num size number. - * @param[in] size new size of the memory space. - * - * @return the new pointer to the allocated memory. - */ -void *mmheap_calloc(struct heap_info *pRoot, size_t num, size_t size); -/** - * @brief Free the memory. - * Free the memory space pointed to by ptr, which must have been returned by a previous call to mmheap_alloc(), mmheap_aligned_alloc(), or mmheap_realloc(). - * - * @attention - * - * @param[in] pRoot heap info. - * @param[in] addr pointer to the memory. - * - * @return None. - */ -void mmheap_free(struct heap_info *pRoot, void *addr); -/** - * @brief get mmheap state - * - * @param pRoot heap info. - * @param pState heap state - */ -void mmheap_get_state(struct heap_info *pRoot, struct heap_state *pState); -#ifdef __cplusplus -} -#endif - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/misc/compiler/common.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/misc/compiler/common.h deleted file mode 100644 index 29489e3c1d..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/misc/compiler/common.h +++ /dev/null @@ -1,63 +0,0 @@ -#ifndef __COMMON_H -#define __COMMON_H - -/** - * @brief Memory access macro - */ -#define BL_RD_WORD(addr) (*((volatile uint32_t *)(uintptr_t)(addr))) -#define BL_WR_WORD(addr, val) ((*(volatile uint32_t *)(uintptr_t)(addr)) = (val)) -#define BL_RD_SHORT(addr) (*((volatile uint16_t *)(uintptr_t)(addr))) -#define BL_WR_SHORT(addr, val) ((*(volatile uint16_t *)(uintptr_t)(addr)) = (val)) -#define BL_RD_BYTE(addr) (*((volatile uint8_t *)(uintptr_t)(addr))) -#define BL_WR_BYTE(addr, val) ((*(volatile uint8_t *)(uintptr_t)(addr)) = (val)) -#define BL_RDWD_FRM_BYTEP(p) ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | (p[0])) - -#define BL_WRWD_TO_BYTEP(p, val) \ - { \ - p[0] = val & 0xff; \ - p[1] = (val >> 8) & 0xff; \ - p[2] = (val >> 16) & 0xff; \ - p[3] = (val >> 24) & 0xff; \ - } -/** - * @brief Register access macro - */ -#define BL_RD_REG16(addr, regname) BL_RD_SHORT(addr + regname##_OFFSET) -#define BL_WR_REG16(addr, regname, val) BL_WR_SHORT(addr + regname##_OFFSET, val) -#define BL_RD_REG(addr, regname) BL_RD_WORD(addr + regname##_OFFSET) -#define BL_WR_REG(addr, regname, val) BL_WR_WORD(addr + regname##_OFFSET, val) -#define BL_SET_REG_BIT(val, bitname) ((val) | (1U << bitname##_POS)) -#define BL_CLR_REG_BIT(val, bitname) ((val)&bitname##_UMSK) -#define BL_GET_REG_BITS_VAL(val, bitname) (((val)&bitname##_MSK) >> bitname##_POS) -#define BL_SET_REG_BITS_VAL(val, bitname, bitval) (((val)&bitname##_UMSK) | ((uint32_t)(bitval) << bitname##_POS)) -#define BL_IS_REG_BIT_SET(val, bitname) (((val) & (1U << (bitname##_POS))) != 0) -#define BL_DRV_DUMMY \ - { \ - __ASM volatile("nop"); \ - __ASM volatile("nop"); \ - __ASM volatile("nop"); \ - __ASM volatile("nop"); \ - } - -/* Std driver attribute macro*/ -#ifndef BFLB_USE_CUSTOM_LD_SECTIONS -//#define ATTR_UNI_SYMBOL -#define ATTR_STRINGIFY(x) #x -#define ATTR_TOSTRING(x) ATTR_STRINGIFY(x) -#define ATTR_UNI_SYMBOL __FILE__ ATTR_TOSTRING(__LINE__) -#define ATTR_CLOCK_SECTION __attribute__((section(".sclock_rlt_code." ATTR_UNI_SYMBOL))) -#define ATTR_CLOCK_CONST_SECTION __attribute__((section(".sclock_rlt_const." ATTR_UNI_SYMBOL))) -#define ATTR_TCM_SECTION __attribute__((section(".tcm_code." ATTR_UNI_SYMBOL))) -#define ATTR_TCM_CONST_SECTION __attribute__((section(".tcm_const." ATTR_UNI_SYMBOL))) -#define ATTR_DTCM_SECTION __attribute__((section(".tcm_data"))) -#define ATTR_HSRAM_SECTION __attribute__((section(".hsram_code"))) -#define ATTR_DMA_RAM_SECTION __attribute__((section(".system_ram"))) -#define ATTR_HBN_RAM_SECTION __attribute__((section(".hbn_ram_code"))) -#define ATTR_HBN_RAM_CONST_SECTION __attribute__((section(".hbn_ram_data"))) -#define ATTR_EALIGN(x) __attribute__((aligned(x))) -#define ATTR_FALLTHROUGH() __attribute__((fallthrough)) -#define ATTR_USED __attribute__((__used__)) -#else -#include "bl_ld_sections.h" -#endif /* BFLB_USE_CUSTOM_LD_SECTIONS */ -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/misc/misc.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/misc/misc.c deleted file mode 100644 index 3292a68359..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/misc/misc.c +++ /dev/null @@ -1,253 +0,0 @@ -/** - * @file misc.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#include "misc.h" - -#ifndef BFLB_USE_ROM_DRIVER -/****************************************************************************/ /** - * @brief Char memcpy - * - * @param dst: Destination - * @param src: Source - * @param n: Count of char - * - * @return Destination pointer - * - *******************************************************************************/ -__WEAK__ void *ATTR_TCM_SECTION arch_memcpy(void *dst, const void *src, uint32_t n) -{ - const uint8_t *p = src; - uint8_t *q = dst; - - while (n--) { - *q++ = *p++; - } - - return dst; -} - -/****************************************************************************/ /** - * @brief Word memcpy - * - * @param dst: Destination - * @param src: Source - * @param n: Count of words - * - * @return Destination pointer - * - *******************************************************************************/ -__WEAK__ uint32_t *ATTR_TCM_SECTION arch_memcpy4(uint32_t *dst, const uint32_t *src, uint32_t n) -{ - const uint32_t *p = src; - uint32_t *q = dst; - - while (n--) { - *q++ = *p++; - } - - return dst; -} - -/****************************************************************************/ /** - * @brief Fast memcpy - * - * @param dst: Destination - * @param src: Source - * @param n: Count of bytes - * - * @return Destination pointer - * - *******************************************************************************/ -__WEAK__ void *ATTR_TCM_SECTION arch_memcpy_fast(void *pdst, const void *psrc, uint32_t n) -{ - uint32_t left, done, i = 0; - uint8_t *dst = (uint8_t *)pdst; - uint8_t *src = (uint8_t *)psrc; - - if (((uint32_t)(uintptr_t)dst & 0x3) == 0 && ((uint32_t)(uintptr_t)src & 0x3) == 0) { - arch_memcpy4((uint32_t *)dst, (const uint32_t *)src, n >> 2); - left = n % 4; - done = n - left; - - while (i < left) { - dst[done + i] = src[done + i]; - i++; - } - } else { - arch_memcpy(dst, src, n); - } - - return dst; -} - -/****************************************************************************/ /** - * @brief char memset - * - * @param dst: Destination - * @param val: Value to set - * @param n: Count of char - * - * @return Destination pointer - * - *******************************************************************************/ -__WEAK__ void *ATTR_TCM_SECTION arch_memset(void *s, uint8_t c, uint32_t n) -{ - uint8_t *p = (uint8_t *)s; - - while (n > 0) { - *p++ = (uint8_t)c; - --n; - } - - return s; -} -/****************************************************************************/ /** - * @brief Word memset - * - * @param dst: Destination - * @param val: Value to set - * @param n: Count of words - * - * @return Destination pointer - * - *******************************************************************************/ -__WEAK__ uint32_t *ATTR_TCM_SECTION arch_memset4(uint32_t *dst, const uint32_t val, uint32_t n) -{ - uint32_t *q = dst; - - while (n--) { - *q++ = val; - } - - return dst; -} - -/****************************************************************************/ /** - * @brief string compare - * - * @param s1: string 1 - * @param s2: string 2 - * @param n: Count of chars - * - * @return compare result - * - *******************************************************************************/ -__WEAK__ int ATTR_TCM_SECTION arch_memcmp(const void *s1, const void *s2, uint32_t n) -{ - const unsigned char *c1 = s1, *c2 = s2; - int d = 0; - - while (n--) { - d = (int)*c1++ - (int)*c2++; - - if (d) { - break; - } - } - - return d; -} -#endif - -void memcopy_to_fifo(void *fifo_addr, uint8_t *data, uint32_t length) -{ - uint8_t *p = (uint8_t *)fifo_addr; - uint8_t *q = data; - - while (length--) { - *p = *q++; - } -} - -void fifocopy_to_mem(void *fifo_addr, uint8_t *data, uint32_t length) -{ - uint8_t *p = (uint8_t *)fifo_addr; - uint8_t *q = data; - - while (length--) { - *q++ = *p; - } -} - -/****************************************************************************/ /** - * @brief get u64 first number 1 from right to left - * - * @param val: target value - * @param bit: first 1 in bit - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -int arch_ffsll(uint64_t *val, uint32_t *bit) -{ - if (!*val) { - return ERROR; - } - - *bit = __builtin_ffsll(*val) - 1; - *val &= ~((1ULL) << (*bit)); - return 0; -} - -int arch_ctzll(uint64_t *val, uint32_t *bit) -{ - if (!*val) - return -1; - - *bit = __builtin_ctzll(*val); - *val &= ~((1ULL) << (*bit)); - return 0; -} - -int arch_clzll(uint64_t *val, uint32_t *bit) -{ - if (!*val) - return -1; - - *bit = __builtin_clzll(*val); - *val &= ~((1ULL) << (*bit)); - return 0; -} - -#ifdef DEBUG -/******************************************************************************* -* @brief Reports the name of the source file and the source line number -* where the CHECK_PARAM error has occurred. - -* @param file: Pointer to the source file name -* @param line: assert_param error line source number - -* @return None -*******************************************************************************/ -void check_failed(uint8_t *file, uint32_t line) -{ - /* Infinite loop */ - while (1) - ; -} -#endif /* DEBUG */ - -/*@} end of group DRIVER_Public_Functions */ - -/*@} end of group DRIVER_COMMON */ - -/*@} end of group BL602_Periph_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/misc/misc.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/misc/misc.h deleted file mode 100644 index 50ea5cd025..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/misc/misc.h +++ /dev/null @@ -1,131 +0,0 @@ -/** - * @file misc.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef _MISC_H -#define _MISC_H - -#include -#include -#include -#include -#include -#include -#include "compiler/gcc.h" -#include "compiler/common.h" - -#ifdef BIT -#undef BIT -#define BIT(n) (1UL << (n)) -#else -#define BIT(n) (1UL << (n)) -#endif - -/** - * @brief Null Type definition - */ -#ifndef NULL -#define NULL 0 -#endif - -/** - * @brief Error type definition - */ -typedef enum { - SUCCESS = 0, - ERROR = 1, - TIMEOUT = 2, - INVALID = 3, /* invalid arguments */ - NORESC = 4 /* no resource or resource temperary unavailable */ -} BL_Err_Type; - -/** - * @brief Functional type definition - */ -typedef enum { - DISABLE = 0, - ENABLE = 1, -} BL_Fun_Type; - -/** - * @brief Status type definition - */ -typedef enum { - RESET = 0, - SET = 1, -} BL_Sts_Type; - -/** - * @brief Mask type definition - */ -typedef enum { - UNMASK = 0, - MASK = 1 -} BL_Mask_Type; - -/** - * @brief Logical status Type definition - */ -typedef enum { - LOGIC_LO = 0, - LOGIC_HI = !LOGIC_LO -} LogicalStatus; - -/** - * @brief Active status Type definition - */ -typedef enum { - DEACTIVE = 0, - ACTIVE = !DEACTIVE -} ActiveStatus; - -/** - * @brief Interrupt callback function type - */ -typedef void(intCallback_Type)(void); -typedef void (*pFunc)(void); - -#define ARCH_MemCpy arch_memcpy -#define ARCH_MemSet arch_memset -#define ARCH_MemCmp arch_memcmp -#define ARCH_MemCpy4 arch_memcpy4 -#define ARCH_MemCpy_Fast arch_memcpy_fast -#define ARCH_MemSet4 arch_memset4 - -#ifdef DEBUG -void check_failed(uint8_t *file, uint32_t line); -#define CHECK_PARAM(expr) ((expr) ? (void)0 : check_failed((uint8_t *)__FILE__, __LINE__)) -#else -#define CHECK_PARAM(expr) ((void)0) -#endif /* DEBUG */ - -void *arch_memcpy(void *dst, const void *src, uint32_t n); -void *arch_memset(void *s, uint8_t c, uint32_t n); -int arch_memcmp(const void *s1, const void *s2, uint32_t n); -uint32_t *arch_memcpy4(uint32_t *dst, const uint32_t *src, uint32_t n); -void *arch_memcpy_fast(void *pdst, const void *psrc, uint32_t n); -uint32_t *arch_memset4(uint32_t *dst, const uint32_t val, uint32_t n); -void memcopy_to_fifo(void *fifo_addr, uint8_t *data, uint32_t length); -void fifocopy_to_mem(void *fifo_addr, uint8_t *data, uint32_t length); -int arch_ctzll(uint64_t *val, uint32_t *bit); -int arch_clzll(uint64_t *val, uint32_t *bit); -int arch_ffsll(uint64_t *val, uint32_t *bit); -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/partition/partition.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/partition/partition.c deleted file mode 100644 index 673dcbe88b..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/partition/partition.c +++ /dev/null @@ -1,544 +0,0 @@ -/** - ****************************************************************************** - * @file partition.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2019 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "partition.h" -#include "softcrc.h" -#include "bflb_platform.h" - -/** @addtogroup BFLB_Common_Driver - * @{ - */ - -/** @addtogroup PARTITION - * @{ - */ - -/** @defgroup PARTITION_Private_Macros - * @{ - */ - -/*@} end of group PARTITION_Private_Macros */ - -/** @defgroup PARTITION_Private_Types - * @{ - */ - -/*@} end of group PARTITION_Private_Types */ - -/** @defgroup PARTITION_Private_Variables - * @{ - */ -p_pt_table_flash_erase gp_pt_table_flash_erase = NULL; -p_pt_table_flash_write gp_pt_table_flash_write = NULL; -p_pt_table_flash_read gp_pt_table_flash_read = NULL; -pt_table_iap_param_type p_iap_param; - -/*@} end of group PARTITION_Private_Variables */ - -/** @defgroup PARTITION_Global_Variables - * @{ - */ -extern int main(void); - -/*@} end of group PARTITION_Global_Variables */ - -/** @defgroup PARTITION_Private_Fun_Declaration - * @{ - */ - -/*@} end of group PARTITION_Private_Fun_Declaration */ - -/** @defgroup PARTITION_Private_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Judge partition table valid - * - * @param ptStuff: Partition table stuff pointer - * - * @return 0 for invalid and 1 for valid - * -*******************************************************************************/ -static uint8_t pt_table_valid(pt_table_stuff_config *pt_stuff) -{ - pt_table_config *pt_table = &pt_stuff->pt_table; - pt_table_entry_config *pt_entries = pt_stuff->pt_entries; - uint32_t *p_crc32; - uint32_t entriesLen = sizeof(pt_table_entry_config) * pt_table->entryCnt; - - if (pt_table->magicCode == BFLB_PT_MAGIC_CODE) { - if (pt_table->entryCnt > PT_ENTRY_MAX) { - MSG("PT Entry Count Error\r\n"); - return 0; - } - - if (pt_table->crc32 != - BFLB_Soft_CRC32((uint8_t *)pt_table, sizeof(pt_table_config) - 4)) { - MSG("PT CRC Error\r\n"); - return 0; - } - - /* ToDo it is a trap here, when entryCnt > 8, crc32 will overflow, comment by zhangcheng */ - p_crc32 = (uint32_t *)((uintptr_t)pt_entries + entriesLen); - - if (*p_crc32 != BFLB_Soft_CRC32((uint8_t *)pt_entries, entriesLen)) { - MSG("PT Entry CRC Error\r\n"); - return 0; - } - - return 1; - } - - return 0; -} - -/*@} end of group PARTITION_Private_Functions */ - -/** @defgroup PARTITION_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Register partition flash read write erase fucntion - * - * @param erase: Flash erase function - * @param write: Flash write function - * @param read: Flash read function - * - * @return None - * -*******************************************************************************/ -void pt_table_set_flash_operation(p_pt_table_flash_erase erase, p_pt_table_flash_write write, p_pt_table_flash_read read) -{ - gp_pt_table_flash_erase = erase; - gp_pt_table_flash_write = write; - gp_pt_table_flash_read = read; -} - -/****************************************************************************/ /** - * @brief Get active partition table whole stuff - * - * @param ptStuff[2]: Partition table stuff pointer - * - * @return Active partition table ID - * -*******************************************************************************/ -pt_table_id_type pt_table_get_active_partition_need_lock(pt_table_stuff_config ptStuff[2]) -{ - uint32_t pt_valid[2] = { 0, 0 }; - pt_table_id_type activePtID; - - if (ptStuff == NULL) { - return PT_TABLE_ID_INVALID; - } - - activePtID = PT_TABLE_ID_INVALID; - - gp_pt_table_flash_read(BFLB_PT_TABLE0_ADDRESS, (uint8_t *)&ptStuff[0], sizeof(pt_table_stuff_config)); - pt_valid[0] = pt_table_valid(&ptStuff[0]); - - gp_pt_table_flash_read(BFLB_PT_TABLE1_ADDRESS, (uint8_t *)&ptStuff[1], sizeof(pt_table_stuff_config)); - pt_valid[1] = pt_table_valid(&ptStuff[1]); - - if (pt_valid[0] == 1 && pt_valid[1] == 1) { - if (ptStuff[0].pt_table.age >= ptStuff[1].pt_table.age) { - activePtID = PT_TABLE_ID_0; - } else { - activePtID = PT_TABLE_ID_1; - } - } else if (pt_valid[0] == 1) { - activePtID = PT_TABLE_ID_0; - } else if (pt_valid[1] == 1) { - activePtID = PT_TABLE_ID_1; - } - - return activePtID; -} - -/****************************************************************************/ /** - * @brief Get partition entry according to entry ID - * - * @param ptStuff: Partition table stuff pointer - * @param type: Type of partition entry - * @param ptEntry: Partition entry pointer to store read data - * - * @return PT_ERROR_SUCCESS or PT_ERROR_ENTRY_NOT_FOUND or PT_ERROR_PARAMETER - * -*******************************************************************************/ -pt_table_error_type pt_table_get_active_entries_by_id(pt_table_stuff_config *pt_stuff, - pt_table_entry_type type, - pt_table_entry_config *pt_entry) -{ - uint32_t i = 0; - - if (pt_stuff == NULL || pt_entry == NULL) { - return PT_ERROR_PARAMETER; - } - - for (i = 0; i < pt_stuff->pt_table.entryCnt; i++) { - if (pt_stuff->pt_entries[i].type == type) { - ARCH_MemCpy_Fast(pt_entry, &pt_stuff->pt_entries[i], sizeof(pt_table_entry_config)); - return PT_ERROR_SUCCESS; - } - } - - return PT_ERROR_ENTRY_NOT_FOUND; -} - -/****************************************************************************/ /** - * @brief Get partition entry according to entry name - * - * @param ptStuff: Partition table stuff pointer - * @param name: Name of partition entry - * @param ptEntry: Partition entry pointer to store read data - * - * @return PT_ERROR_SUCCESS or PT_ERROR_ENTRY_NOT_FOUND or PT_ERROR_PARAMETER - * -*******************************************************************************/ -pt_table_error_type pt_table_get_active_entries_by_name(pt_table_stuff_config *pt_stuff, - uint8_t *name, - pt_table_entry_config *pt_entry) -{ - uint32_t i = 0; - uint32_t len = strlen((char *)name); - - if (pt_stuff == NULL || pt_entry == NULL) { - return PT_ERROR_PARAMETER; - } - - for (i = 0; i < pt_stuff->pt_table.entryCnt; i++) { - if (strlen((char *)pt_stuff->pt_entries[i].name) == len && - memcmp((char *)pt_stuff->pt_entries[i].name, (char *)name, len) == 0) { - ARCH_MemCpy_Fast(pt_entry, &pt_stuff->pt_entries[i], sizeof(pt_table_entry_config)); - return PT_ERROR_SUCCESS; - } - } - - return PT_ERROR_ENTRY_NOT_FOUND; -} - -/****************************************************************************/ /** - * @brief Update partition entry - * - * @param targetTableID: Target partition table to update - * @param ptStuff: Partition table stuff pointer - * @param ptEntry: Partition entry pointer to update - * - * @return Partition update result - * -*******************************************************************************/ -pt_table_error_type pt_table_update_entry(pt_table_id_type target_table_id, - pt_table_stuff_config *pt_stuff, - pt_table_entry_config *pt_entry) -{ - uint32_t i = 0; - BL_Err_Type ret; - uint32_t write_addr; - uint32_t entries_len; - pt_table_config *pt_table; - pt_table_entry_config *pt_entries; - uint32_t *crc32; - - if (pt_entry == NULL || pt_stuff == NULL) { - return PT_ERROR_PARAMETER; - } - - pt_table = &pt_stuff->pt_table; - pt_entries = pt_stuff->pt_entries; - - if (target_table_id == PT_TABLE_ID_INVALID) { - return PT_ERROR_TABLE_NOT_VALID; - } - - if (target_table_id == PT_TABLE_ID_0) { - write_addr = BFLB_PT_TABLE0_ADDRESS; - } else { - write_addr = BFLB_PT_TABLE1_ADDRESS; - } - - for (i = 0; i < pt_table->entryCnt; i++) { - if (pt_entries[i].type == pt_entry->type) { - ARCH_MemCpy_Fast(&pt_entries[i], pt_entry, sizeof(pt_table_entry_config)); - break; - } - } - - if (i == pt_table->entryCnt) { - /* Not found this entry ,add new one */ - if (pt_table->entryCnt < PT_ENTRY_MAX) { - ARCH_MemCpy_Fast(&pt_entries[pt_table->entryCnt], pt_entry, sizeof(pt_table_entry_config)); - pt_table->entryCnt++; - } else { - return PT_ERROR_ENTRY_UPDATE_FAIL; - } - } - - /* Prepare write back to flash */ - /* Update age */ - pt_table->age++; - pt_table->crc32 = BFLB_Soft_CRC32((uint8_t *)pt_table, sizeof(pt_table_config) - 4); - - /* Update entries CRC */ - entries_len = pt_table->entryCnt * sizeof(pt_table_entry_config); - crc32 = (uint32_t *)((uintptr_t)pt_entries + entries_len); - *crc32 = BFLB_Soft_CRC32((uint8_t *)&pt_entries[0], entries_len); - - /* Write back to flash */ - /* Erase flash first */ - //ret = gp_pt_table_flash_erase(write_addr, write_addr + sizeof(pt_table_config) + entries_len + 4 - 1); - ret = gp_pt_table_flash_erase(write_addr, sizeof(pt_table_config) + entries_len + 4); - - if (ret != SUCCESS) { - MSG_ERR("Flash Erase error\r\n"); - return PT_ERROR_FALSH_WRITE; - } - - /* Write flash */ - ret = gp_pt_table_flash_write(write_addr, (uint8_t *)pt_stuff, sizeof(pt_table_stuff_config)); - - if (ret != SUCCESS) { - MSG_ERR("Flash Write error\r\n"); - return PT_ERROR_FALSH_WRITE; - } - - return PT_ERROR_SUCCESS; -} - -/****************************************************************************/ /** - * @brief Create partition entry - * - * @param ptID: Partition table ID - * - * @return Partition create result - * -*******************************************************************************/ -pt_table_error_type pt_table_create(pt_table_id_type pt_id) -{ - uint32_t write_addr; - BL_Err_Type ret; - pt_table_config pt_table; - - if (pt_id == PT_TABLE_ID_INVALID) { - return PT_ERROR_TABLE_NOT_VALID; - } - - if (pt_id == PT_TABLE_ID_0) { - write_addr = BFLB_PT_TABLE0_ADDRESS; - } else { - write_addr = BFLB_PT_TABLE1_ADDRESS; - } - - /* Prepare write back to flash */ - pt_table.magicCode = BFLB_PT_MAGIC_CODE; - pt_table.version = 0; - pt_table.entryCnt = 0; - pt_table.age = 0; - pt_table.crc32 = BFLB_Soft_CRC32((uint8_t *)&pt_table, sizeof(pt_table_config) - 4); - /* Write back to flash */ - //ret = gp_pt_table_flash_erase(write_addr, write_addr + sizeof(pt_table_config) - 1); - ret = gp_pt_table_flash_erase(write_addr,sizeof(pt_table_config)); - - if (ret != SUCCESS) { - MSG_ERR("Flash Erase error\r\n"); - return PT_ERROR_FALSH_ERASE; - } - - ret = gp_pt_table_flash_write(write_addr, (uint8_t *)&pt_table, sizeof(pt_table_config)); - - if (ret != SUCCESS) { - MSG_ERR("Flash Write error\r\n"); - return PT_ERROR_FALSH_WRITE; - } - - return PT_ERROR_SUCCESS; -} - -pt_table_error_type pt_table_dump(void) -{ - uint32_t pt_valid[2] = { 0, 0 }; - pt_table_stuff_config pt_stuff[2]; - - gp_pt_table_flash_read(BFLB_PT_TABLE0_ADDRESS, (uint8_t *)&pt_stuff[0], sizeof(pt_table_stuff_config)); - pt_valid[0] = pt_table_valid(&pt_stuff[0]); - - gp_pt_table_flash_read(BFLB_PT_TABLE1_ADDRESS, (uint8_t *)&pt_stuff[1], sizeof(pt_table_stuff_config)); - pt_valid[1] = pt_table_valid(&pt_stuff[1]); - - if (pt_valid[0]) { - MSG("PT TABLE0 valid\r\n"); - } else { - MSG("PT TABLE0 invalid\r\n"); - } - - if (pt_valid[1]) { - MSG("PT TABLE1 valid\r\n"); - } else { - MSG("PT TABLE1 invalid\r\n"); - } - - for (int i = 0; i < 2; i++) { - if (pt_valid[i] == 1) { - MSG("ptStuff[%d].pt_table.magicCode 0x%08x\r\n", i, pt_stuff[i].pt_table.magicCode); - MSG("ptStuff[%d].pt_table.version 0x%08x\r\n", i, pt_stuff[i].pt_table.version); - MSG("ptStuff[%d].pt_table.entryCnt 0x%08x\r\n", i, pt_stuff[i].pt_table.entryCnt); - MSG("ptStuff[%d].pt_table.age 0x%08x\r\n", i, pt_stuff[i].pt_table.age); - MSG("ptStuff[%d].pt_table.crc32 0x%08x\r\n", i, pt_stuff[i].pt_table.crc32); - - for (int j = 0; j < pt_stuff[i].pt_table.entryCnt; j++) { - MSG("ptStuff[%d].pt_entries[%d].type 0x%08x\r\n", i, j, pt_stuff[i].pt_entries[j].type); - MSG("ptStuff[%d].pt_entries[%d].device 0x%08x\r\n", i, j, pt_stuff[i].pt_entries[j].device); - MSG("ptStuff[%d].pt_entries[%d].active_index 0x%08x\r\n", i, j, pt_stuff[i].pt_entries[j].active_index); - MSG("ptStuff[%d].pt_entries[%d].Address[0] 0x%08x\r\n", i, j, pt_stuff[i].pt_entries[j].start_address[0]); - MSG("ptStuff[%d].pt_entries[%d].Address[1] 0x%08x\r\n", i, j, pt_stuff[i].pt_entries[j].start_address[1]); - MSG("ptStuff[%d].pt_entries[%d].maxLen[0] 0x%08x\r\n", i, j, pt_stuff[i].pt_entries[j].max_len[0]); - MSG("ptStuff[%d].pt_entries[%d].maxLen[1] 0x%08x\r\n", i, j, pt_stuff[i].pt_entries[j].max_len[1]); - MSG("ptStuff[%d].pt_entries[%d].len 0x%08x\r\n", i, j, pt_stuff[i].pt_entries[j].len); - MSG("ptStuff[%d].pt_entries[%d].age 0x%08x\r\n", i, j, pt_stuff[i].pt_entries[j].age); - } - } - } - - return PT_ERROR_SUCCESS; -} - -pt_table_error_type pt_table_get_iap_para(pt_table_iap_param_type *para) -{ - uint32_t pt_valid[2] = { 0, 0 }; - pt_table_stuff_config pt_stuff[2]; - uint8_t active_index; - - gp_pt_table_flash_read(BFLB_PT_TABLE0_ADDRESS, (uint8_t *)&pt_stuff[0], sizeof(pt_table_stuff_config)); - pt_valid[0] = pt_table_valid(&pt_stuff[0]); - - gp_pt_table_flash_read(BFLB_PT_TABLE1_ADDRESS, (uint8_t *)&pt_stuff[1], sizeof(pt_table_stuff_config)); - pt_valid[1] = pt_table_valid(&pt_stuff[1]); - - if ((pt_valid[0] == 1) && (pt_valid[1] == 1)) { - if (pt_stuff[0].pt_table.age >= pt_stuff[1].pt_table.age) { - active_index = pt_stuff[0].pt_entries[0].active_index; - para->iap_write_addr = para->iap_start_addr = pt_stuff[0].pt_entries[0].start_address[!(active_index & 0x01)]; - para->inactive_index = !(active_index & 0x01); - para->inactive_table_index = 1; - - } else { - active_index = pt_stuff[1].pt_entries[0].active_index; - para->iap_write_addr = para->iap_start_addr = pt_stuff[1].pt_entries[0].start_address[!(active_index & 0x01)]; - para->inactive_index = !(active_index & 0x01); - para->inactive_table_index = 0; - } - - } else if (pt_valid[1] == 1) { - active_index = pt_stuff[1].pt_entries[0].active_index; - para->iap_write_addr = para->iap_start_addr = pt_stuff[1].pt_entries[0].start_address[!(active_index & 0x01)]; - para->inactive_index = !(active_index & 0x01); - para->inactive_table_index = 0; - } else if (pt_valid[0] == 1) { - active_index = pt_stuff[0].pt_entries[0].active_index; - para->iap_write_addr = para->iap_start_addr = pt_stuff[0].pt_entries[0].start_address[!(active_index & 0x01)]; - para->inactive_index = !(active_index & 0x01); - para->inactive_table_index = 1; - } else { - return PT_ERROR_TABLE_NOT_VALID; - } - - MSG("inactive_table_index %d, inactive index %d , IAP start addr %08x \r\n", para->inactive_table_index, para->inactive_index, para->iap_start_addr); - return PT_ERROR_SUCCESS; -} - -pt_table_error_type pt_table_set_iap_para(pt_table_iap_param_type *para) -{ - pt_table_stuff_config pt_stuff, pt_stuff_write; - int32_t ret; - uint32_t *p_crc32; - uint32_t entries_len; - - if (para->inactive_table_index == 1) { - gp_pt_table_flash_read(BFLB_PT_TABLE0_ADDRESS, (uint8_t *)&pt_stuff, sizeof(pt_table_stuff_config)); - } else if (para->inactive_table_index == 0) { - gp_pt_table_flash_read(BFLB_PT_TABLE1_ADDRESS, (uint8_t *)&pt_stuff, sizeof(pt_table_stuff_config)); - } - - ARCH_MemCpy_Fast((void *)&pt_stuff_write, (void *)&pt_stuff, sizeof(pt_table_stuff_config)); - pt_stuff_write.pt_table.age += 1; - pt_stuff_write.pt_entries[0].active_index = !(pt_stuff_write.pt_entries[0].active_index & 0x01); - pt_stuff_write.pt_table.crc32 = BFLB_Soft_CRC32((uint8_t *)&pt_stuff_write, sizeof(pt_table_config) - 4); - entries_len = sizeof(pt_table_entry_config) * pt_stuff_write.pt_table.entryCnt; - //pt_stuff_write.crc32 = BFLB_Soft_CRC32((uint8_t*)pt_stuff_write.pt_entries,entries_len); - p_crc32 = (uint32_t *)((uintptr_t)pt_stuff_write.pt_entries + entries_len); - *p_crc32 = BFLB_Soft_CRC32((uint8_t *)pt_stuff_write.pt_entries, entries_len); - - if (para->inactive_table_index == 1) { - //ret = gp_pt_table_flash_erase(BFLB_PT_TABLE1_ADDRESS, BFLB_PT_TABLE1_ADDRESS + sizeof(pt_table_stuff_config) - 1); - ret = gp_pt_table_flash_erase(BFLB_PT_TABLE1_ADDRESS, sizeof(pt_table_stuff_config)); - - if (ret != SUCCESS) { - MSG_ERR("Flash Erase error\r\n"); - return PT_ERROR_FALSH_ERASE; - } - - ret = gp_pt_table_flash_write(BFLB_PT_TABLE1_ADDRESS, (uint8_t *)&pt_stuff_write, sizeof(pt_table_stuff_config)); - - if (ret != SUCCESS) { - MSG_ERR("Flash Write error\r\n"); - return PT_ERROR_FALSH_WRITE; - } - } else if (para->inactive_table_index == 0) { - //ret = gp_pt_table_flash_erase(BFLB_PT_TABLE0_ADDRESS, BFLB_PT_TABLE0_ADDRESS + sizeof(pt_table_stuff_config) - 1); - ret = gp_pt_table_flash_erase(BFLB_PT_TABLE0_ADDRESS, sizeof(pt_table_stuff_config)); - - if (ret != SUCCESS) { - MSG_ERR("Flash Erase error\r\n"); - return PT_ERROR_FALSH_ERASE; - } - - ret = gp_pt_table_flash_write(BFLB_PT_TABLE0_ADDRESS, (uint8_t *)&pt_stuff_write, sizeof(pt_table_stuff_config)); - - if (ret != SUCCESS) { - MSG_ERR("Flash Write error\r\n"); - return PT_ERROR_FALSH_WRITE; - } - } - - MSG("Update pt_table suss\r\n"); - return PT_ERROR_SUCCESS; -} - -/*@} end of group PARTITION_Public_Functions */ - -/*@} end of group PARTITION */ - -/*@} end of group BFLB_Common_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/partition/partition.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/partition/partition.h deleted file mode 100644 index f20332dcd8..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/partition/partition.h +++ /dev/null @@ -1,209 +0,0 @@ -/** - ****************************************************************************** - * @file partition.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __PARTITION_H__ -#define __PARTITION_H__ - -#include "misc.h" - -/** @addtogroup BFLB_Common_Driver - * @{ - */ - -/** @addtogroup PARTITION - * @{ - */ - -/** @defgroup PARTITION_Public_Types - * @{ - */ - -/** - * @brief Partition table error type definition - */ -typedef enum { - PT_ERROR_SUCCESS, /*!< Partition table error type:success */ - PT_ERROR_TABLE_NOT_VALID, /*!< Partition table error type:table not found */ - PT_ERROR_ENTRY_NOT_FOUND, /*!< Partition table error type:entry not found */ - PT_ERROR_ENTRY_UPDATE_FAIL, /*!< Partition table error type:entry update fail */ - PT_ERROR_CRC32, /*!< Partition table error type:crc32 error */ - PT_ERROR_PARAMETER, /*!< Partition table error type:input parameter error */ - PT_ERROR_FALSH_READ, /*!< Partition table error type:flash read error */ - PT_ERROR_FALSH_WRITE, /*!< Partition table error type:flash write error */ - PT_ERROR_FALSH_ERASE, /*!< Partition table error type:flash erase error */ -} pt_table_error_type; - -/** - * @brief Partition id type definition - */ -typedef enum { - PT_TABLE_ID_0, /*!< Partition table ID 0 */ - PT_TABLE_ID_1, /*!< Partition table ID 1 */ - PT_TABLE_ID_INVALID, /*!< Partition table ID invalid */ -} pt_table_id_type; - -/** - * @brief Partition id type definition - */ -typedef enum { - PT_ENTRY_FW_CPU0, /*!< Partition entry type:CPU0 firmware */ - PT_ENTRY_FW_CPU1, /*!< Partition entry type:CPU1 firmware */ - PT_ENTRY_MAX = 16, /*!< Partition entry type:Max */ -} pt_table_entry_type; - -/** - * @brief Partition table config definition - */ -typedef struct -{ - uint32_t magicCode; /*!< Partition table magic code */ - uint16_t version; /*!< Partition table verdion */ - uint16_t entryCnt; /*!< Partition table entry count */ - uint32_t age; /*!< Partition table age */ - uint32_t crc32; /*!< Partition table CRC32 value */ -} pt_table_config; - -/** - * @brief Partition table entry config definition - */ -typedef struct -{ - uint8_t type; /*!< Partition entry type */ - uint8_t device; /*!< Partition entry device */ - uint8_t active_index; /*!< Partition entry active index */ - uint8_t name[9]; /*!< Partition entry name */ - uint32_t start_address[2]; /*!< Partition entry start address */ - uint32_t max_len[2]; /*!< Partition entry max length */ - uint32_t len; /*!< Partition entry length */ - uint32_t age; /*!< Partition entry age */ -} pt_table_entry_config; - -/** - * @brief Partition table stuff config definition - */ -typedef struct -{ - pt_table_config pt_table; /*!< Partition table */ - pt_table_entry_config pt_entries[PT_ENTRY_MAX]; /*!< Partition entries */ - uint32_t crc32; /*!< Partition entries crc32 */ -} pt_table_stuff_config; - -/** - * @brief Partition table iap param definition - */ -typedef struct -{ - uint32_t iap_start_addr; - uint32_t iap_write_addr; - uint32_t iap_img_len; - uint8_t inactive_index; - uint8_t inactive_table_index; -} pt_table_iap_param_type; - -/*@} end of group PARTITION_Public_Types */ - -/** @defgroup PARTITION_Public_Constants - * @{ - */ - -/** @defgroup pt_table_error_type - * @{ - */ -#define IS_PTTABLE_ERROR_TYPE(type) (((type) == PT_ERROR_SUCCESS) || \ - ((type) == PT_ERROR_TABLE_NOT_VALID) || \ - ((type) == PT_ERROR_ENTRY_NOT_FOUND) || \ - ((type) == PT_ERROR_ENTRY_UPDATE_FAIL) || \ - ((type) == PT_ERROR_CRC32) || \ - ((type) == PT_ERROR_PARAMETER) || \ - ((type) == PT_ERROR_FALSH_READ) || \ - ((type) == PT_ERROR_FALSH_WRITE) || \ - ((type) == PT_ERROR_FALSH_ERASE)) - -/** @defgroup pt_table_id_type - * @{ - */ -#define IS_PTTABLE_ID_TYPE(type) (((type) == PT_TABLE_ID_0) || \ - ((type) == PT_TABLE_ID_1) || \ - ((type) == PT_TABLE_ID_INVALID)) - -/** @defgroup pt_table_entry_type - * @{ - */ -#define IS_PTTABLE_ENTRY_TYPE(type) (((type) == PT_ENTRY_FW_CPU0) || \ - ((type) == PT_ENTRY_FW_CPU1) || \ - ((type) == PT_ENTRY_MAX)) - -/*@} end of group PARTITION_Public_Constants */ - -/** @defgroup PARTITION_Public_Macros - * @{ - */ -#define BFLB_PT_TABLE0_ADDRESS 0xE000 -#define BFLB_PT_TABLE1_ADDRESS 0xF000 -#define BFLB_PT_MAGIC_CODE 0x54504642 -typedef BL_Err_Type (*p_pt_table_flash_erase)(uint32_t startaddr, uint32_t endaddr); -typedef BL_Err_Type (*p_pt_table_flash_write)(uint32_t addr, uint8_t *data, uint32_t len); -typedef BL_Err_Type (*p_pt_table_flash_read)(uint32_t addr, uint8_t *data, uint32_t len); - -/*@} end of group PARTITION_Public_Macros */ - -/** @defgroup PARTITION_Public_Functions - * @{ - */ -void pt_table_set_flash_operation(p_pt_table_flash_erase erase, p_pt_table_flash_write write, p_pt_table_flash_read read); -pt_table_id_type pt_table_get_active_partition_need_lock(pt_table_stuff_config ptStuff[2]); -pt_table_error_type pt_table_get_active_entries_by_id(pt_table_stuff_config *pt_stuff, - pt_table_entry_type type, - pt_table_entry_config *pt_entry); -pt_table_error_type pt_table_get_active_entries_by_name(pt_table_stuff_config *pt_stuff, - uint8_t *name, - pt_table_entry_config *pt_entry); -pt_table_error_type pt_table_update_entry(pt_table_id_type target_table_id, - pt_table_stuff_config *pt_stuff, - pt_table_entry_config *pt_entry); -pt_table_error_type pt_table_create(pt_table_id_type pt_id); -pt_table_error_type pt_table_dump(void); -pt_table_error_type pt_table_get_iap_para(pt_table_iap_param_type *para); -pt_table_error_type pt_table_set_iap_para(pt_table_iap_param_type *para); - -/*@} end of group PARTITION_Public_Functions */ - -/*@} end of group PARTITION */ - -/*@} end of group BFLB_Common_Driver */ - -extern pt_table_iap_param_type p_iap_param; - -#endif /* __PARTITION_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/pid/pid.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/pid/pid.c deleted file mode 100644 index c7d6da8593..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/pid/pid.c +++ /dev/null @@ -1,68 +0,0 @@ -/** - * @file pid.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ - -#include "pid.h" - -void pid_init(pid_alg_t *pid) -{ - pid->set_val = 0.0f; - pid->out_val = 0.0f; - - pid->last_error = 0.0f; - pid->prev_error = 0.0f; - - pid->kp = 3.0f; - pid->ki = 0.0f; - pid->kd = 0.0f; - - pid->i_error = 0.0f; - pid->sum_error = 0.0f; - - pid->max_val = 32; - pid->min_val = -32; -} - -// standard pid -float standard_pid_cal(pid_alg_t *pid, float next_val) -{ - pid->set_val = next_val; - pid->i_error = pid->set_val - pid->out_val; - pid->sum_error += pid->i_error; - pid->out_val = pid->kp * pid->i_error + pid->ki * pid->sum_error + pid->kd * (pid->i_error - pid->last_error); - pid->last_error = pid->i_error; - - return pid->out_val; -} - -// increment pid -float increment_pid_cal(pid_alg_t *pid, float next_val) -{ - pid->set_val = next_val; - pid->i_error = pid->set_val - pid->out_val; - float increment = pid->kp * (pid->i_error - pid->prev_error) + pid->ki * pid->i_error + pid->kd * (pid->i_error - 2 * pid->prev_error + pid->last_error); - pid->out_val += increment; - pid->last_error = pid->prev_error; - pid->prev_error = pid->i_error; - - return pid->out_val; -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/pid/pid.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/pid/pid.h deleted file mode 100644 index 5323790f20..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/pid/pid.h +++ /dev/null @@ -1,50 +0,0 @@ -/** - * @file pid.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ - -#ifndef __PID_H__ -#define __PID_H__ - -#include "stdint.h" - -typedef struct pid_alg { - float set_val; - float out_val; - - float kp; - float ki; - float kd; - - float i_error; - float last_error; - float prev_error; - float sum_error; - - int max_val; - int min_val; -} pid_alg_t; - -void pid_init(pid_alg_t *pid); -float standard_pid_cal(pid_alg_t *pid, float next_val); -float increment_pid_cal(pid_alg_t *pid, float next_val); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/ring_buffer/ring_buffer.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/ring_buffer/ring_buffer.c deleted file mode 100644 index ec91c71578..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/ring_buffer/ring_buffer.c +++ /dev/null @@ -1,679 +0,0 @@ -/** - * @file ring_buffer.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#include "ring_buffer.h" - -/** @addtogroup BL_Common_Component - * @{ - */ - -/** @addtogroup RING_BUFFER - * @{ - */ - -/** @defgroup RING_BUFFER_Private_Macros - * @{ - */ - -/*@} end of group RING_BUFFER_Private_Macros */ - -/** @defgroup RING_BUFFER_Private_Types - * @{ - */ - -/*@} end of group RING_BUFFER_Private_Types */ - -/** @defgroup RING_BUFFER_Private_Fun_Declaration - * @{ - */ - -/*@} end of group RING_BUFFER_Private_Fun_Declaration */ - -/** @defgroup RING_BUFFER_Private_Variables - * @{ - */ - -/*@} end of group RING_BUFFER_Private_Variables */ - -/** @defgroup RING_BUFFER_Global_Variables - * @{ - */ - -/*@} end of group RING_BUFFER_Global_Variables */ - -/** @defgroup RING_BUFFER_Private_Functions - * @{ - */ - -/*@} end of group RING_BUFFER_Private_Functions */ - -/** @defgroup RING_BUFFER_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Ring buffer init function - * - * @param rbType: Ring buffer type structure pointer - * @param buffer: Pointer of ring buffer - * @param size: Size of ring buffer - * @param lockCb: Ring buffer lock callback function pointer - * @param unlockCb: Ring buffer unlock callback function pointer - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type Ring_Buffer_Init(Ring_Buffer_Type *rbType, uint8_t *buffer, uint32_t size, ringBuffer_Lock_Callback *lockCb, ringBuffer_Lock_Callback *unlockCb) -{ - /* Init ring buffer pointer */ - rbType->pointer = buffer; - - /* Init read/write mirror and index */ - rbType->readMirror = 0; - rbType->readIndex = 0; - rbType->writeMirror = 0; - rbType->writeIndex = 0; - - /* Set ring buffer size */ - rbType->size = size; - - /* Set lock and unlock callback function */ - rbType->lock = lockCb; - rbType->unlock = unlockCb; - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Ring buffer reset function - * - * @param rbType: Ring buffer type structure pointer - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type Ring_Buffer_Reset(Ring_Buffer_Type *rbType) -{ - if (rbType->lock != NULL) { - rbType->lock(); - } - - /* Clear read/write mirror and index */ - rbType->readMirror = 0; - rbType->readIndex = 0; - rbType->writeMirror = 0; - rbType->writeIndex = 0; - - if (rbType->unlock != NULL) { - rbType->unlock(); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Use callback function to write ring buffer function - * - * @param rbType: Ring buffer type structure pointer - * @param length: Length of data want to write - * @param writeCb: Callback function pointer - * @param parameter: Parameter that callback function may use - * - * @return Length of data actually write - * -*******************************************************************************/ -uint32_t Ring_Buffer_Write_Callback(Ring_Buffer_Type *rbType, uint32_t length, ringBuffer_Write_Callback *writeCb, void *parameter) -{ - uint32_t sizeRemained = Ring_Buffer_Get_Empty_Length(rbType); - - if (writeCb == NULL) { - return 0; - } - - if (rbType->lock != NULL) { - rbType->lock(); - } - - /* Ring buffer has no space for new data */ - if (sizeRemained == 0) { - if (rbType->unlock != NULL) { - rbType->unlock(); - } - - return 0; - } - - /* Drop part of data when length out of space remained */ - if (length > sizeRemained) { - length = sizeRemained; - } - - /* Get size of space remained in current mirror */ - sizeRemained = rbType->size - rbType->writeIndex; - - if (sizeRemained > length) { - /* Space remained is enough for data in current mirror */ - writeCb(parameter, &rbType->pointer[rbType->writeIndex], length); - rbType->writeIndex += length; - } else { - /* Data is divided to two parts with different mirror */ - writeCb(parameter, &rbType->pointer[rbType->writeIndex], sizeRemained); - writeCb(parameter, &rbType->pointer[0], length - sizeRemained); - rbType->writeIndex = length - sizeRemained; - rbType->writeMirror = ~rbType->writeMirror; - } - - if (rbType->unlock != NULL) { - rbType->unlock(); - } - - return length; -} - -/****************************************************************************/ /** - * @brief Copy data from data buffer to ring buffer function - * - * @param parameter: Pointer to source pointer - * @param dest: Ring buffer to write - * @param length: Length of data to write - * - * @return None - * -*******************************************************************************/ -static void Ring_Buffer_Write_Copy(void *parameter, uint8_t *dest, uint32_t length) -{ - uint8_t **src = (uint8_t **)parameter; - - ARCH_MemCpy_Fast(dest, *src, length); - *src += length; -} - -/****************************************************************************/ /** - * @brief Write ring buffer function - * - * @param rbType: Ring buffer type structure pointer - * @param data: Data to write - * @param length: Length of data - * - * @return Length of data writted actually - * -*******************************************************************************/ -uint32_t Ring_Buffer_Write(Ring_Buffer_Type *rbType, const uint8_t *data, uint32_t length) -{ - return Ring_Buffer_Write_Callback(rbType, length, Ring_Buffer_Write_Copy, &data); -} - -/****************************************************************************/ /** - * @brief Write 1 byte to ring buffer function - * - * @param rbType: Ring buffer type structure pointer - * @param data: Data to write - * - * @return Length of data writted actually - * -*******************************************************************************/ -uint32_t Ring_Buffer_Write_Byte(Ring_Buffer_Type *rbType, const uint8_t data) -{ - if (rbType->lock != NULL) { - rbType->lock(); - } - - /* Ring buffer has no space for new data */ - if (!Ring_Buffer_Get_Empty_Length(rbType)) { - if (rbType->unlock != NULL) { - rbType->unlock(); - } - - return 0; - } - - rbType->pointer[rbType->writeIndex] = data; - - /* Judge to change index and mirror */ - if (rbType->writeIndex != (rbType->size - 1)) { - rbType->writeIndex++; - } else { - rbType->writeIndex = 0; - rbType->writeMirror = ~rbType->writeMirror; - } - - if (rbType->unlock != NULL) { - rbType->unlock(); - } - - return 1; -} - -/****************************************************************************/ /** - * @brief Write ring buffer function, old data will be covered by new data when ring buffer is - * full - * - * @param rbType: Ring buffer type structure pointer - * @param data: Data to write - * @param length: Length of data - * - * @return Length of data writted actually - * -*******************************************************************************/ -uint32_t Ring_Buffer_Write_Force(Ring_Buffer_Type *rbType, const uint8_t *data, uint32_t length) -{ - uint32_t sizeRemained = Ring_Buffer_Get_Empty_Length(rbType); - uint32_t indexRemained = rbType->size - rbType->writeIndex; - - if (rbType->lock != NULL) { - rbType->lock(); - } - - /* Drop extra data when data length is large than size of ring buffer */ - if (length > rbType->size) { - data = &data[length - rbType->size]; - length = rbType->size; - } - - if (indexRemained > length) { - /* Space remained is enough for data in current mirror */ - ARCH_MemCpy_Fast(&rbType->pointer[rbType->writeIndex], data, length); - rbType->writeIndex += length; - - /* Update read index */ - if (length > sizeRemained) { - rbType->readIndex = rbType->writeIndex; - } - } else { - /* Data is divided to two parts with different mirror */ - ARCH_MemCpy_Fast(&rbType->pointer[rbType->writeIndex], data, indexRemained); - ARCH_MemCpy_Fast(&rbType->pointer[0], &data[indexRemained], length - indexRemained); - rbType->writeIndex = length - indexRemained; - rbType->writeMirror = ~rbType->writeMirror; - - /* Update read index and mirror */ - if (length > sizeRemained) { - rbType->readIndex = rbType->writeIndex; - rbType->readMirror = ~rbType->readMirror; - } - } - - if (rbType->unlock != NULL) { - rbType->unlock(); - } - - return length; -} - -/****************************************************************************/ /** - * @brief Write 1 byte to ring buffer function, old data will be covered by new data when ring - * buffer is full - * - * @param rbType: Ring buffer type structure pointer - * @param data: Data to write - * - * @return Length of data writted actually - * -*******************************************************************************/ -uint32_t Ring_Buffer_Write_Byte_Force(Ring_Buffer_Type *rbType, const uint8_t data) -{ - Ring_Buffer_Status_Type status = Ring_Buffer_Get_Status(rbType); - - if (rbType->lock != NULL) { - rbType->lock(); - } - - rbType->pointer[rbType->writeIndex] = data; - - /* Judge to change index and mirror */ - if (rbType->writeIndex == rbType->size - 1) { - rbType->writeIndex = 0; - rbType->writeMirror = ~rbType->writeMirror; - - /* Update read index and mirror */ - if (status == RING_BUFFER_FULL) { - rbType->readIndex = rbType->writeIndex; - rbType->readMirror = ~rbType->readMirror; - } - } else { - rbType->writeIndex++; - - /* Update read index */ - if (status == RING_BUFFER_FULL) { - rbType->readIndex = rbType->writeIndex; - } - } - - if (rbType->unlock != NULL) { - rbType->unlock(); - } - - return 1; -} - -/****************************************************************************/ /** - * @brief Use callback function to read ring buffer function - * - * @param rbType: Ring buffer type structure pointer - * @param length: Length of data want to read - * @param readCb: Callback function pointer - * @param parameter: Parameter that callback function may use - * - * @return Length of data actually read - * -*******************************************************************************/ -uint32_t Ring_Buffer_Read_Callback(Ring_Buffer_Type *rbType, uint32_t length, ringBuffer_Read_Callback *readCb, void *parameter) -{ - uint32_t size = Ring_Buffer_Get_Length(rbType); - - if (readCb == NULL) { - return 0; - } - - if (rbType->lock != NULL) { - rbType->lock(); - } - - /* Ring buffer has no data */ - if (!size) { - if (rbType->unlock != NULL) { - rbType->unlock(); - } - - return 0; - } - - /* Ring buffer do not have enough data */ - if (size < length) { - length = size; - } - - /* Get size of space remained in current mirror */ - size = rbType->size - rbType->readIndex; - - if (size > length) { - /* Read all data needed */ - readCb(parameter, &rbType->pointer[rbType->readIndex], length); - rbType->readIndex += length; - } else { - /* Read two part of data in different mirror */ - readCb(parameter, &rbType->pointer[rbType->readIndex], size); - readCb(parameter, &rbType->pointer[0], length - size); - rbType->readIndex = length - size; - rbType->readMirror = ~rbType->readMirror; - } - - if (rbType->unlock != NULL) { - rbType->unlock(); - } - - return length; -} - -/****************************************************************************/ /** - * @brief Copy data from ring buffer to data buffer function - * - * @param parameter: Pointer to destination pointer - * @param data: Data buffer to copy - * @param length: Length of data to copy - * - * @return None - * -*******************************************************************************/ -static void Ring_Buffer_Read_Copy(void *parameter, uint8_t *data, uint32_t length) -{ - uint8_t **dest = (uint8_t **)parameter; - - ARCH_MemCpy_Fast(*dest, data, length); - *dest += length; -} - -/****************************************************************************/ /** - * @brief Read ring buffer function - * - * @param rbType: Ring buffer type structure pointer - * @param data: Buffer for data read - * @param length: Length of data to read - * - * @return Length of data read actually - * -*******************************************************************************/ -uint32_t Ring_Buffer_Read(Ring_Buffer_Type *rbType, uint8_t *data, uint32_t length) -{ - return Ring_Buffer_Read_Callback(rbType, length, Ring_Buffer_Read_Copy, &data); -} - -/****************************************************************************/ /** - * @brief Read 1 byte from ring buffer function - * - * @param rbType: Ring buffer type structure pointer - * @param data: Data read - * - * @return Length of data actually read - * -*******************************************************************************/ -uint32_t Ring_Buffer_Read_Byte(Ring_Buffer_Type *rbType, uint8_t *data) -{ - if (rbType->lock != NULL) { - rbType->lock(); - } - - /* Ring buffer has no data */ - if (!Ring_Buffer_Get_Length(rbType)) { - if (rbType->unlock != NULL) { - rbType->unlock(); - } - - return 0; - } - - /* Read data */ - *data = rbType->pointer[rbType->readIndex]; - - /* Update read index and mirror */ - if (rbType->readIndex == rbType->size - 1) { - rbType->readIndex = 0; - rbType->readMirror = ~rbType->readMirror; - } else { - rbType->readIndex++; - } - - if (rbType->unlock != NULL) { - rbType->unlock(); - } - - return 1; -} - -/****************************************************************************/ /** - * @brief Read ring buffer function, do not remove from buffer actually - * - * @param rbType: Ring buffer type structure pointer - * @param data: Buffer for data read - * @param length: Length of data to read - * - * @return Length of data read actually - * -*******************************************************************************/ -uint32_t Ring_Buffer_Peek(Ring_Buffer_Type *rbType, uint8_t *data, uint32_t length) -{ - uint32_t size = Ring_Buffer_Get_Length(rbType); - - if (rbType->lock != NULL) { - rbType->lock(); - } - - /* Ring buffer has no data */ - if (!size) { - if (rbType->unlock != NULL) { - rbType->unlock(); - } - - return 0; - } - - /* Ring buffer do not have enough data */ - if (size < length) { - length = size; - } - - /* Get size of space remained in current mirror */ - size = rbType->size - rbType->readIndex; - - if (size > length) { - /* Read all data needed */ - ARCH_MemCpy_Fast(data, &rbType->pointer[rbType->readIndex], length); - } else { - /* Read two part of data in different mirror */ - ARCH_MemCpy_Fast(data, &rbType->pointer[rbType->readIndex], size); - ARCH_MemCpy_Fast(&data[size], &rbType->pointer[0], length - size); - } - - if (rbType->unlock != NULL) { - rbType->unlock(); - } - - return length; -} - -/****************************************************************************/ /** - * @brief Read 1 byte from ring buffer function, do not remove from buffer actually - * - * @param rbType: Ring buffer type structure pointer - * @param data: Data read - * - * @return Length of data actually read - * -*******************************************************************************/ -uint32_t Ring_Buffer_Peek_Byte(Ring_Buffer_Type *rbType, uint8_t *data) -{ - if (rbType->lock != NULL) { - rbType->lock(); - } - - /* Ring buffer has no data */ - if (!Ring_Buffer_Get_Length(rbType)) { - if (rbType->unlock != NULL) { - rbType->unlock(); - } - - return 0; - } - - /* Read data */ - *data = rbType->pointer[rbType->readIndex]; - - if (rbType->unlock != NULL) { - rbType->unlock(); - } - - return 1; -} - -/****************************************************************************/ /** - * @brief Get length of data in ring buffer function - * - * @param rbType: Ring buffer type structure pointer - * - * @return Length of data - * -*******************************************************************************/ -uint32_t Ring_Buffer_Get_Length(Ring_Buffer_Type *rbType) -{ - uint32_t readMirror = 0; - uint32_t writeMirror = 0; - uint32_t readIndex = 0; - uint32_t writeIndex = 0; - uint32_t size = 0; - - if (rbType->lock != NULL) { - rbType->lock(); - } - - readMirror = rbType->readMirror; - writeMirror = rbType->writeMirror; - readIndex = rbType->readIndex; - writeIndex = rbType->writeIndex; - size = rbType->size; - - if (rbType->unlock != NULL) { - rbType->unlock(); - } - - if (readMirror == writeMirror) { - return writeIndex - readIndex; - } else { - return size - (readIndex - writeIndex); - } -} - -/****************************************************************************/ /** - * @brief Get space remained in ring buffer function - * - * @param rbType: Ring buffer type structure pointer - * - * @return Length of space remained - * -*******************************************************************************/ -uint32_t Ring_Buffer_Get_Empty_Length(Ring_Buffer_Type *rbType) -{ - return (rbType->size - Ring_Buffer_Get_Length(rbType)); -} - -/****************************************************************************/ /** - * @brief Get ring buffer status function - * - * @param rbType: Ring buffer type structure pointer - * - * @return Status of ring buffer - * -*******************************************************************************/ -Ring_Buffer_Status_Type Ring_Buffer_Get_Status(Ring_Buffer_Type *rbType) -{ - if (rbType->lock != NULL) { - rbType->lock(); - } - - /* Judge empty or full */ - if (rbType->readIndex == rbType->writeIndex) { - if (rbType->readMirror == rbType->writeMirror) { - if (rbType->unlock != NULL) { - rbType->unlock(); - } - - return RING_BUFFER_EMPTY; - } else { - if (rbType->unlock != NULL) { - rbType->unlock(); - } - - return RING_BUFFER_FULL; - } - } - - if (rbType->unlock != NULL) { - rbType->unlock(); - } - - return RING_BUFFER_PARTIAL; -} - -/*@} end of group RING_BUFFER_Public_Functions */ - -/*@} end of group RING_BUFFER */ - -/*@} end of group BL_Common_Component */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/ring_buffer/ring_buffer.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/ring_buffer/ring_buffer.h deleted file mode 100644 index dbc6681994..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/ring_buffer/ring_buffer.h +++ /dev/null @@ -1,116 +0,0 @@ -/** - * @file ring_buffer.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __RING_BUFFER_H__ -#define __RING_BUFFER_H__ - -#include "misc.h" - -/** @addtogroup BL_Common_Component - * @{ - */ - -/** @addtogroup RING_BUFFER - * @{ - */ - -/** @defgroup RING_BUFFER_Public_Types - * @{ - */ - -/** - * @brief Ring buffer status type definition - */ -typedef enum { - RING_BUFFER_EMPTY, /*!< Ring buffer is empty */ - RING_BUFFER_PARTIAL, /*!< Ring buffer has partial data */ - RING_BUFFER_FULL, /*!< Ring buffer is full */ -} Ring_Buffer_Status_Type; - -/** - * @brief Ring buffer structure definition - */ -typedef struct -{ - uint8_t *pointer; /*!< Pointer of ring buffer */ - uint8_t readMirror; /*!< Read mirror,used to judge empty or full */ - uint32_t readIndex; /*!< Index of read address */ - uint8_t writeMirror; /*!< Write mirror,used to judge empty or full */ - uint32_t writeIndex; /*!< Index of write address */ - uint32_t size; /*!< Size of ring buffer */ - void (*lock)(void); /*!< Lock ring buffer */ - void (*unlock)(void); /*!< Unlock ring buffer */ -} Ring_Buffer_Type; - -/*@} end of group RING_BUFFER_Public_Types */ - -/** @defgroup RING_BUFFER_Public_Constants - * @{ - */ - -/** @defgroup RING_BUFFER_STATUS_TYPE - * @{ - */ -#define IS_RING_BUFFER_STATUS_TYPE(type) (((type) == RING_BUFFER_EMPTY) || \ - ((type) == RING_BUFFER_PARTIAL) || \ - ((type) == RING_BUFFER_FULL)) - -/*@} end of group RING_BUFFER_Public_Constants */ - -/** @defgroup RING_BUFFER_Public_Macros - * @{ - */ -typedef void(ringBuffer_Lock_Callback)(void); -typedef void(ringBuffer_Read_Callback)(void *, uint8_t *, uint32_t); -typedef void(ringBuffer_Write_Callback)(void *, uint8_t *, uint32_t); - -/*@} end of group RING_BUFFER_Public_Macros */ - -/** @defgroup RING_BUFFER_Public_Functions - * @{ - */ -BL_Err_Type Ring_Buffer_Init(Ring_Buffer_Type *rbType, uint8_t *buffer, uint32_t size, ringBuffer_Lock_Callback *lockCb, - ringBuffer_Lock_Callback *unlockCb); -BL_Err_Type Ring_Buffer_Reset(Ring_Buffer_Type *rbType); -uint32_t Ring_Buffer_Write_Callback(Ring_Buffer_Type *rbType, uint32_t length, ringBuffer_Write_Callback *writeCb, - void *parameter); -uint32_t Ring_Buffer_Write(Ring_Buffer_Type *rbType, const uint8_t *data, uint32_t length); -uint32_t Ring_Buffer_Write_Byte(Ring_Buffer_Type *rbType, const uint8_t data); -uint32_t Ring_Buffer_Write_Force(Ring_Buffer_Type *rbType, const uint8_t *data, uint32_t length); -uint32_t Ring_Buffer_Write_Byte_Force(Ring_Buffer_Type *rbType, const uint8_t data); -uint32_t Ring_Buffer_Read_Callback(Ring_Buffer_Type *rbType, uint32_t length, ringBuffer_Read_Callback *readCb, - void *parameter); -uint32_t Ring_Buffer_Read(Ring_Buffer_Type *rbType, uint8_t *data, uint32_t length); -uint32_t Ring_Buffer_Read_Byte(Ring_Buffer_Type *rbType, uint8_t *data); -uint32_t Ring_Buffer_Peek(Ring_Buffer_Type *rbType, uint8_t *data, uint32_t length); -uint32_t Ring_Buffer_Peek_Byte(Ring_Buffer_Type *rbType, uint8_t *data); -uint32_t Ring_Buffer_Get_Length(Ring_Buffer_Type *rbType); -uint32_t Ring_Buffer_Get_Empty_Length(Ring_Buffer_Type *rbType); -Ring_Buffer_Status_Type Ring_Buffer_Get_Status(Ring_Buffer_Type *rbType); - -/*@} end of group RING_BUFFER_Public_Functions */ - -/*@} end of group RING_BUFFER */ - -/*@} end of group BL_Common_Component */ - -#endif /* __RING_BUFFER_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/soft_crc/softcrc.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/soft_crc/softcrc.h deleted file mode 100644 index c56ab26d23..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/soft_crc/softcrc.h +++ /dev/null @@ -1,32 +0,0 @@ -/** - * @file softcrc.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __SOFTCRC_H__ -#define __SOFTCRC_H__ - -#include "stdint.h" - -uint16_t BFLB_Soft_CRC16(void *dataIn, uint32_t len); -uint32_t BFLB_Soft_CRC32_Ex(uint32_t initial, void *dataIn, uint32_t len); -uint32_t BFLB_Soft_CRC32(void *dataIn, uint32_t len); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/timestamp/timestamp.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/timestamp/timestamp.c deleted file mode 100644 index 74a5b2cc3a..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/timestamp/timestamp.c +++ /dev/null @@ -1,136 +0,0 @@ -/** - * @file timestamp.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ - -#include "timestamp.h" - -#define FOUR_YEAR_DAY ((365 << 2) + 1) //The total number of days in a 4-year cycle -#define TIMEZONE (8) //Beijing time Zone adjustment - -#define SEC_NUM_PER_DAY (24 * 60 * 60) -#define SEC_NUM_PER_HOUR (60 * 60) -#define SEC_NUM_PER_MINUTE (60) - -static uint8_t month_day[12] = { 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 }; //平年 -static uint8_t Leap_month_day[12] = { 31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 }; //闰年 - -/** -* @bref judge if it is a leap year -* @para year to be judge -* @return 1：leap year 0： nonleap year -*/ -bool check_leap_year(uint16_t year) -{ - if (year % 4) { - return false; - } else { - if ((year % 100 == 0) && (year % 400 != 0)) { - return false; - } else { - return true; - } - } -} - -void cal_weekday(rtc_time *beijing_time) -{ - uint32_t y,m,d,w; - - y=beijing_time->year; - m=beijing_time->month; - d=beijing_time->day; - - if((m==1)||(m==2)) - { - m+=12; - y--; - } - /* - 把一月和二月看成是上一年的十三月和十四月，例：如果是2004-1-10则换算成：2003-13-10来代入公式计算。 - 以公元元年为参考，公元元年1月1日为星期一
程序如下：
-    利用基姆拉尔森计算日期公式  w=(d+2*m+3*(m+1)/5+y+y/4-y/100+y/400)
-    */
-    w=(d+2*m+3*(m+1)/5+y+y/4-y/100+y/400+1)%7;
-
-    beijing_time->week=(uint8_t)w;
-}
-
-void unixtime2bejingtime(uint32_t unixtime, rtc_time *beijing_time)
-{
-    uint32_t totle_day_num;
-    uint32_t current_sec_num;
-
-    uint16_t remain_day;
-
-    uint16_t temp_year;
-
-    uint8_t *p = NULL;
-
-    totle_day_num = unixtime / SEC_NUM_PER_DAY;   //The total number of days
-    current_sec_num = unixtime % SEC_NUM_PER_DAY; //The number of seconds this day
-
-    /* use the number of seconds this day, To calculate hour\minute\second */
-    beijing_time->hour = current_sec_num / SEC_NUM_PER_HOUR;
-    beijing_time->minute = (current_sec_num % SEC_NUM_PER_HOUR) / SEC_NUM_PER_MINUTE;
-    beijing_time->second = (current_sec_num % SEC_NUM_PER_HOUR) % SEC_NUM_PER_MINUTE;
-
-    /* Adjust the time zone and check whether the date is +1 */
-    beijing_time->hour += 8;
-    if (beijing_time->hour > 23) {
-        beijing_time->hour -= 24;
-        totle_day_num++;
-    }
-
-
-    /* calculate year */
-    beijing_time->year = 1970 + (totle_day_num / FOUR_YEAR_DAY) * 4; // 4-year as a cycle
-    remain_day = totle_day_num % FOUR_YEAR_DAY;                      //remaining day nym( < 4 year )
-
-    /* calculate year & day */
-    temp_year = check_leap_year(beijing_time->year) ? 366 : 365;
-    while (remain_day >= temp_year) {
-        beijing_time->year++;
-        remain_day -= temp_year;
-        temp_year = check_leap_year(beijing_time->year) ? 366 : 365;
-    }
-
-    /* Calculate specific dates(month\day)*/
-    p = check_leap_year(beijing_time->year) ? Leap_month_day : month_day;
-    remain_day++; //The actual day starts at 1
-    beijing_time->month = 0;
-    while (remain_day > *(p + beijing_time->month)) {
-        remain_day -= *(p + beijing_time->month);
-        beijing_time->month++;
-    }
-
-    beijing_time->month++; //The actual month starts at 1
-    beijing_time->day = remain_day;
-
-
-
-    /*利用基姆拉尔森计算日期公式  w=(d+2*m+3*(m+1)/5+y+y/4-y/100+y/400)*/
-
-    beijing_time->week = beijing_time->day + 2*beijing_time->month + 3*(beijing_time->month+1)/5 + \
-    beijing_time->year + beijing_time->year/4 - beijing_time->year/100 +beijing_time->year/400 ;
-
-    cal_weekday(beijing_time);
-}
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/timestamp/timestamp.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/timestamp/timestamp.h
deleted file mode 100644
index 5986baf91c..0000000000
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/timestamp/timestamp.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/**
- * @file timestamp.h
- * @brief
- *
- * Copyright (c) 2021 Bouffalolab team
- *
- * Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements.  See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership.  The
- * ASF licenses this file to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance with the
- * License.  You may obtain a copy of the License at
- *
- *   http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
- * License for the specific language governing permissions and limitations
- * under the License.
- *
- */
-#ifndef _TIMESTAMP_
-#define _TIMESTAMP_
-
-#include "stdint.h"
-#include "stddef.h"
-#include "stdbool.h"
-
-typedef struct _rtc_time_t
-{
-    uint16_t year;
-    uint8_t month;
-    uint8_t day;
-    uint8_t week;
-    uint8_t hour;
-    uint8_t minute;
-    uint8_t second;
-}rtc_time;
-
-void unixtime2bejingtime(uint32_t unixtime,rtc_time* beijing_time);
-
-#endif
-
-
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl606p_flash.ld b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl606p_flash.ld
deleted file mode 100644
index da0ef735e2..0000000000
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl606p_flash.ld
+++ /dev/null
@@ -1,350 +0,0 @@
-/****************************************************************************************
-* @file map.txt
-*
-* @brief This file is the map file (gnuarm or armgcc).
-*
-* Copyright (C) BouffaloLab 2018
-*
-****************************************************************************************
-*/
-
-/* configure the CPU type */
-OUTPUT_ARCH( "riscv" )
-/* link with the standard c library */
-INPUT(-lc)
-/* link with the standard GCC library */
-INPUT(-lgcc)
-/* configure the entry point */
-ENTRY(risc_e906_start)
-
-StackSize = 0x0400; /*  1KB */
-BOOT2_PT_ADDR = 0x62047e00;
-BOOT2_FLASHCFG_ADDR = 0x62047f14;
-
-MEMORY
-{
-    flash    (rxai!w) : ORIGIN = 0x58000000, LENGTH = 4M
-    xram_memory (!rx) : ORIGIN = 0x22020000, LENGTH = 16K 
-    ram_memory  (!rx) : ORIGIN = 0x22024000, LENGTH = 48K
-    ram_wifi    (!rx) : ORIGIN = 0x22030000, LENGTH = 96K 
-    ram_psram  (!rx)  : ORIGIN = 0x54000000, LENGTH = 4M
-    bugkill   (rxai!w) : ORIGIN = 0xD0000000, LENGTH = 16M
-}
-
-SECTIONS
-{
-    PROVIDE(__metal_chicken_bit = 0);
-    
-    .text.boot :
-    {
-        . = ALIGN(4);
-    
-        *(.text.entry)
-
-        . = ALIGN(4);
-    } > flash
-
-    .bugkiller_command :
-    {
-        PROVIDE( __bugkiller_command_start = ADDR(.bugkiller_command) );
-        PROVIDE( __bugkiller_command_end = ADDR(.bugkiller_command) + SIZEOF(.bugkiller_command) );
-        KEEP (*(.static_bugkiller_command))
-    } > bugkill
-
-    .bugkiller :
-    {
-        KEEP (*(.bugkiller_code))
-        KEEP (*bugkiller*.o(.rodata* .text* .data* .sdata* .sbss*))
-    } > bugkill
-
-    .psram_ram_data_region : 
-    {
-        . = ALIGN(4);
-        __psram_ram_data_start__ = .;
- 
-        *(.psram_data.*)
-        *liblwip.a:*.o(.text*)
-        *libwifi.a:*.o(.text*)
-        *libwifi_manager.a:*.o(.text*)
-        *libfreertos_e907.a:*.o(.text*)
-        *libnetutils.a:*.o(.text*)
-        *libutils.a:*.o(.text*)
-        *libstartup_bl808.a:debug.o(.text*)
-
-        *liblwip.a:*.o(.rodata*)
-        *libwifi.a:*.o(.rodata*)
-        *libwifi_manager.a:*.o(.rodata*)
-        *libfreertos_e907.a:*.o(.rodata*)
-        *libnetutils.a:*.o(.rodata*)
-        *libutils.a:*.o(.rodata*)
-        *libstartup_bl808.a:debug.o(.rodata*)
-        
-        . = ALIGN(4);
-        __psram_ram_data_end__ = .;
-    } > ram_psram AT > flash
-
-    .text :
-    {
-        . = ALIGN(4);
-    
-        *(.text)
-        *(.text.*)
-
-        . = ALIGN(4);
-    } > flash
-
-    .rodata :
-    {
-        . = ALIGN(4);
-        
-        *(.rodata)
-        *(.rodata.*)
-    
-        *(.srodata)
-        *(.srodata.*)
-
-        /* static cli cmds */
-        . = ALIGN(4);
-        _bl_static_cli_cmds_start = .;
-        KEEP(*(.static_cli_cmds))
-        *(.static_cli_cmds)
-        _bl_static_cli_cmds_end = .;    
-        
-        /* static blog code1 */
-        . = ALIGN(4);
-        _bl_static_blogcomponent_code_start = .;
-        KEEP(SORT(*)(.static_blogcomponent_code*))
-        *(.static_blogcomponent_code*)
-        _bl_static_blogcomponent_code_end = .;
-    
-        /* static blog code2 */
-        . = ALIGN(4);
-        _bl_static_blogfile_code_start = .;
-        KEEP(SORT(*)(.static_blogfile_code*))
-        *(.static_blogfile_code*)
-        _bl_static_blogfile_code_end = .;
-    
-        /* static blog code3 */
-        . = ALIGN(4);
-        _bl_static_blogpri_code_start = .;
-        KEEP(SORT(*)(.static_blogpri_code*))
-        *(.static_blogpri_code*)
-        _bl_static_blogpri_code_end = .;
-    
-        /* static fw attribute entry */
-        . = ALIGN(4);
-        _bl_static_fw_cfg_entry_start = .;
-        KEEP(*(.wifi.cfg.entry))
-        _bl_static_fw_cfg_entry_end = .;
-        . = ALIGN(4);
-
-    } > flash
-
-    .itcm_region :
-    {
-        . = ALIGN(4);
-        __tcm_code_start__ = .;
-
-        *(.tcm_code)
-        *(.tcm_code.*)
-        *(.tcm_const)
-        *(.tcm_const.*)
-        *(.sclock_rlt_code)
-        *(.sclock_rlt_code.*)
-        *(.sclock_rlt_const)
-        *(.sclock_rlt_const.*)
-        
-        . = ALIGN(4);
-        __tcm_code_end__ = .;
-    } > ram_psram AT > flash
-
-    .dtcm_region : 
-    {
-        . = ALIGN(4);
-        __tcm_data_start__ = .;
-        
-        *(.tcm_data)
-        
-        . = ALIGN(4);
-        __tcm_data_end__ = .;
-    } > ram_psram AT > flash
-
-    .stack_dummy (NOLOAD):
-    {
-	PROVIDE ( _sp_base = . );
-        . = ALIGN(64);
-        __stack_protect_start = .;
-        . = . + 256;
-        __stack_protect_end = .;
-        . = . + StackSize;
-        . = ALIGN(64);
-	PROVIDE( _sp_main = . );
-    } > ram_psram
-
-    .system_ram_data_region : 
-    {
-        . = ALIGN(4);
-        __system_ram_data_start__ = .;
- 
-        *(.system_ram)
-        
-        . = ALIGN(4);
-        __system_ram_data_end__ = .;
-    } > ram_psram AT > flash
-
-    .data : 
-    {
-        . = ALIGN(4);
-        __ram_data_start__ = .;
-
-        PROVIDE( __global_pointer$ = . + 0x800 );
-        
-        *(.data)
-        *(.data.*)
-        *(.sdata)
-        *(.sdata.*)
-        *(.sdata2)
-        *(.sdata2.*)
-        
-        _bt_gatt_service_static_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_gatt_service_static.static.*")))
-        _bt_gatt_service_static_list_end = .;
-        _bt_l2cap_fixed_chan_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_l2cap_fixed_chan.static.*")))
-        _bt_l2cap_fixed_chan_list_end = .;
-        _bt_l2cap_br_fixed_chan_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_l2cap_br_fixed_chan.static.*")))
-        _bt_l2cap_br_fixed_chan_list_end = .;
-
-        . = ALIGN(4);
-        __ram_data_end__ = .;
-    } > ram_psram AT > flash
-
-    .xrambss  (NOLOAD) :
-    {
-        __xram_load_addr = .;
-        
-        . = ALIGN(4);
-        __xram_data_start__ = .;
-
-        *(.static_xram_region)
-
-        __xram_data_end__ = .;
-        . = ALIGN(4);
-    } > xram_memory
-
-    .ocram_bss_region (NOLOAD) :
-    {
-        . = ALIGN(4);
-        __ocram_bss_start__ = .;
-
-        *(.nocache_ram)
-
-        . = ALIGN(4);
-        __ocram_bss_end__ = .;
-    } > ram_memory
-
-    .boot2 (NOLOAD) :
-    {
-        PROVIDE ( __boot2_pt_addr_start = . );
-        *(.bss.boot2_partition_table)
-        PROVIDE ( __boot2_pt_addr_end   = . );
-
-        PROVIDE ( __boot2_flashCfg_start = . );
-        *(.bss.boot2_flashCfg)
-        PROVIDE ( __boot2_flashCfg_end = . );
-
-    } > ram_psram
-    
-    .wifibss  (NOLOAD) :
-    {
-        PROVIDE( __wifi_bss_start = ADDR(.wifibss) );
-        PROVIDE( __wifi_bss_end = ADDR(.wifibss) + SIZEOF(.wifibss) );
-        *ipc_shared.o(COMMON)
-        *sdu_shared.o(COMMON)
-        *hal_desc.o(COMMON)
-        *txl_buffer_shared.o(COMMON)
-        *txl_frame_shared.o(COMMON)
-        *scan_shared.o(COMMON)
-        *scanu_shared.o(COMMON)
-        *mfp_bip.o(COMMON)
-        *me_mic.o(COMMON)
-        *bl_sta_mgmt_others.o(COMMON)
-        *bl_pmk_mgmt.o(COMMON)
-        *bl_pmk_mgmt_internal.o(COMMON)
-        *libwifi_drv.a:bl_utils.o(COMMON)
-        *libwifi_drv.a:bl_utils.o(.bss*)
-        *(.wifi_ram*)
-        . = ALIGN(16);
-    } > ram_wifi
-
-    .bss (NOLOAD) :
-    {
-        . = ALIGN(4);
-        __bss_start__ = .;
-        
-        *(.bss*)
-        *(.sbss*)
-        *(.noinit_data*)
-        *(COMMON)
- 
-        . = ALIGN(4);
-        __bss_end__ = .;
-    } > ram_psram 
-
-    .heap (NOLOAD):
-    {
-        . = ALIGN(4);
-        __HeapBase = .;
-        _heap_start = .;
-        
-        KEEP(*(.heap*))
-        
-        . = ALIGN(4);
-        __HeapLimit = .;
-        _heap_end = .;
-    } > ram_psram 
-
-    __StackTop = ADDR(.stack_dummy) + SIZEOF(.stack_dummy);
-    PROVIDE( __freertos_irq_stack_top = __StackTop);
-    __StackLimit = ADDR(.stack_dummy);
-
-    __HeapLimit = ORIGIN(ram_psram) + LENGTH(ram_psram);
-    _heap_size = __HeapLimit - _heap_start;
-
-    PROVIDE( __itcm_load_addr = LOADADDR(.itcm_region));
-    PROVIDE( __dtcm_load_addr = LOADADDR(.dtcm_region));
-    PROVIDE( __system_ram_load_addr = LOADADDR(.system_ram_data_region));
-    PROVIDE( __psram_ram_load_addr = LOADADDR(.psram_ram_data_region));
-    PROVIDE( __ram_load_addr = LOADADDR(.data));
-
-    /*SYMOBOL used in code*/
-    PROVIDE( _ld_bl_static_cli_cmds_start = _bl_static_cli_cmds_start );
-    PROVIDE( _ld_bl_static_cli_cmds_end   = _bl_static_cli_cmds_end );
-
-    /*BOOT2 sections*/
-    PROVIDE ( __boot2_pt_addr_src = BOOT2_PT_ADDR );
-    PROVIDE ( __boot2_flashCfg_src = BOOT2_FLASHCFG_ADDR );
-    
-    PROVIDE( _ld_ram_size0 = LENGTH(flash) );
-    PROVIDE( _ld_ram_addr0 = ORIGIN(flash) );
-    PROVIDE( _ld_ram_size1 = LENGTH(ram_psram) );
-    PROVIDE( _ld_ram_addr1 = ORIGIN(ram_psram) );
-    PROVIDE( _ld_ram_size2 = LENGTH(ram_wifi) );
-    PROVIDE( _ld_ram_addr2 = ORIGIN(ram_wifi) );
-    PROVIDE( _ld_ram_size3 = LENGTH(ram_memory) );
-    PROVIDE( _ld_ram_addr3 = ORIGIN(ram_memory) );
-    PROVIDE( _ld_ram_size4 = LENGTH(xram_memory) );
-    PROVIDE( _ld_ram_addr4 = ORIGIN(xram_memory) );
- 
-    /* blog */
-    PROVIDE( _ld_bl_static_blogcomponent_code_start = _bl_static_blogcomponent_code_start );
-    PROVIDE( _ld_bl_static_blogcomponent_code_end   = _bl_static_blogcomponent_code_end );
-    PROVIDE( _ld_bl_static_blogfile_code_start = _bl_static_blogfile_code_start );
-    PROVIDE( _ld_bl_static_blogfile_code_end   = _bl_static_blogfile_code_end );
-    PROVIDE( _ld_bl_static_blogpri_code_start = _bl_static_blogpri_code_start );
-    PROVIDE( _ld_bl_static_blogpri_code_end   = _bl_static_blogpri_code_end );
-
-    PROVIDE( _ld_bl_static_cfg_entry_start = _bl_static_fw_cfg_entry_start );
-    PROVIDE( _ld_bl_static_cfg_entry_end   = _bl_static_fw_cfg_entry_end );
-}
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl606p_flash_rom.ld b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl606p_flash_rom.ld
deleted file mode 100644
index d2001b4ffd..0000000000
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl606p_flash_rom.ld
+++ /dev/null
@@ -1,252 +0,0 @@
-/****************************************************************************************
-* @file map.txt
-*
-* @brief This file is the map file (gnuarm or armgcc).
-*
-* Copyright (C) BouffaloLab 2018
-*
-****************************************************************************************
-*/
-
-/* configure the CPU type */
-OUTPUT_ARCH( "riscv" )
-/* link with the standard c library */
-INPUT(-lc)
-/* link with the standard GCC library */
-INPUT(-lgcc)
-/* configure the entry point */
-ENTRY(risc_e906_start)
-
-StackSize = 0x0400; /*  1KB */
-
-MEMORY
-{
-    flash    (rxai!w) : ORIGIN = 0xD8000000, LENGTH = 4M
-    itcm_memory (rx)  : ORIGIN = 0xC2024000, LENGTH = 48K
-    dtcm_memory (rx)  : ORIGIN = 0x62020000, LENGTH = 16K
-    ram_memory  (!rx) : ORIGIN = 0x22010000, LENGTH = 64K
-    ram_wifi    (!rx) : ORIGIN = 0x22030000, LENGTH = 160K
-}
-
-SECTIONS
-{
-    PROVIDE(__metal_chicken_bit = 0);
-    
-    .text :
-    {
-        . = ALIGN(4);
-    
-        KEEP (*(SORT_NONE(_start)))
-        KEEP (*(SORT_NONE(risc_e906_start)))
-        
-        *(.text)
-        *(.text.*)
-
-        . = ALIGN(4);
-    } > flash
-
-    .rodata :
-    {
-        . = ALIGN(4);
-        
-        *(.rodata)
-        *(.rodata.*)
-    
-        *(.srodata)
-        *(.srodata.*)
-
-        /* static cli cmds */
-        . = ALIGN(4);
-        _bl_static_cli_cmds_start = .;
-        KEEP(*(.static_cli_cmds))
-        *(.static_cli_cmds)
-        _bl_static_cli_cmds_end = .;    
-        
-        /* static blog code1 */
-        . = ALIGN(4);
-        _bl_static_blogcomponent_code_start = .;
-        KEEP(SORT(*)(.static_blogcomponent_code*))
-        *(.static_blogcomponent_code*)
-        _bl_static_blogcomponent_code_end = .;
-    
-        /* static blog code2 */
-        . = ALIGN(4);
-        _bl_static_blogfile_code_start = .;
-        KEEP(SORT(*)(.static_blogfile_code*))
-        *(.static_blogfile_code*)
-        _bl_static_blogfile_code_end = .;
-    
-        /* static blog code3 */
-        . = ALIGN(4);
-        _bl_static_blogpri_code_start = .;
-        KEEP(SORT(*)(.static_blogpri_code*))
-        *(.static_blogpri_code*)
-        _bl_static_blogpri_code_end = .;
-    
-        /* static fw attribute entry */
-        . = ALIGN(4);
-        _bl_static_fw_cfg_entry_start = .;
-        KEEP(*(.wifi.cfg.entry))
-        _bl_static_fw_cfg_entry_end = .;
-        . = ALIGN(4);
-
-    } > flash
-
-    .itcm_region :
-    {
-        . = ALIGN(4);
-        __tcm_code_start__ = .;
-
-        *(.tcm_code)
-        *(.tcm_code.*)
-        *(.tcm_const)
-        *(.sclock_rlt_code)
-        *(.sclock_rlt_const)
-        
-        . = ALIGN(4);
-        __tcm_code_end__ = .;
-    } > itcm_memory AT > flash
-
-    .dtcm_region : 
-    {
-        . = ALIGN(4);
-        __tcm_data_start__ = .;
-        
-        *(.tcm_data)
-        
-        . = ALIGN(4);
-        __tcm_data_end__ = .;
-    } > dtcm_memory AT > flash
-
-    .stack_dummy (NOLOAD):
-    {
-        . = ALIGN(4);
-        . = . + StackSize;
-        . = ALIGN(4);
-    } > dtcm_memory
-
-    .system_ram_data_region : 
-    {
-        . = ALIGN(4);
-        __system_ram_data_start__ = .;
- 
-        *(.system_ram)
-        
-        . = ALIGN(4);
-        __system_ram_data_end__ = .;
-    } > ram_memory AT > flash
-
-    .data : 
-    {
-        . = ALIGN(4);
-        __ram_data_start__ = .;
-
-        PROVIDE( __global_pointer$ = . + 0x800 );
-        
-        *(.data)
-        *(.data.*)
-        *(.sdata)
-        *(.sdata.*)
-        *(.sdata2)
-        *(.sdata2.*)
-        
-        _bt_gatt_service_static_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_gatt_service_static.static.*")))
-        _bt_gatt_service_static_list_end = .;
-        _bt_l2cap_fixed_chan_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_l2cap_fixed_chan.static.*")))
-        _bt_l2cap_fixed_chan_list_end = .;
-        _bt_l2cap_br_fixed_chan_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_l2cap_br_fixed_chan.static.*")))
-        _bt_l2cap_br_fixed_chan_list_end = .;
-
-        . = ALIGN(4);
-        __ram_data_end__ = .;
-    } > ram_memory AT > flash
-    
-    .wifibss  (NOLOAD) :
-    {
-        PROVIDE( __wifi_bss_start = ADDR(.wifibss) );
-        PROVIDE( __wifi_bss_end = ADDR(.wifibss) + SIZEOF(.wifibss) );
-        *ipc_shared.o(COMMON)
-        *sdu_shared.o(COMMON)
-        *hal_desc.o(COMMON)
-        *txl_buffer_shared.o(COMMON)
-        *txl_frame_shared.o(COMMON)
-        *scan_shared.o(COMMON)
-        *scanu_shared.o(COMMON)
-        *mfp_bip.o(COMMON)
-        *me_mic.o(COMMON)
-        *bl_sta_mgmt_others.o(COMMON)
-        *bl_pmk_mgmt.o(COMMON)
-        *bl_pmk_mgmt_internal.o(COMMON)
-        *libwifi_drv.a:bl_utils.o(COMMON)
-        *libwifi_drv.a:bl_utils.o(.bss*)
-        *(.wifi_ram*)
-        . = ALIGN(16);
-    } > ram_wifi
-
-    PROVIDE( _heap_wifi_start = . );
-    PROVIDE( _heap_wifi_size = ORIGIN(ram_wifi) + LENGTH(ram_wifi) - _heap_wifi_start );
-
-    .bss (NOLOAD) :
-    {
-        . = ALIGN(4);
-        __bss_start__ = .;
-        
-        *(.bss*)
-        *(.sbss*)
-        *(.noinit_data*)
-        *(COMMON)
- 
-        . = ALIGN(4);
-        __bss_end__ = .;
-    } > ram_memory 
-
-    .heap (NOLOAD):
-    {
-        . = ALIGN(4);
-        __HeapBase = .;
-        _heap_start = .;
-        
-        KEEP(*(.heap*))
-        
-        . = ALIGN(4);
-        __HeapLimit = .;
-        _heap_end = .;
-    } > ram_memory 
-
-    __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);
-    PROVIDE( __freertos_irq_stack_top = __StackTop);
-    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
-
-    __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory);
-    _heap_size = __HeapLimit - _heap_start;
-
-    PROVIDE( __itcm_load_addr = LOADADDR(.itcm_region));
-    PROVIDE( __dtcm_load_addr = LOADADDR(.dtcm_region));
-    PROVIDE( __system_ram_load_addr = LOADADDR(.system_ram_data_region));
-    PROVIDE( __ram_load_addr = LOADADDR(.data));
-
-    /*SYMOBOL used in code*/
-    PROVIDE( _ld_bl_static_cli_cmds_start = _bl_static_cli_cmds_start );
-    PROVIDE( _ld_bl_static_cli_cmds_end   = _bl_static_cli_cmds_end );
-    
-    PROVIDE( _ld_ram_size0 = LENGTH(flash) );
-    PROVIDE( _ld_ram_addr0 = ORIGIN(flash) );
-    PROVIDE( _ld_ram_size1 = LENGTH(ram_memory) );
-    PROVIDE( _ld_ram_addr1 = ORIGIN(ram_memory) );
-    PROVIDE( _ld_ram_size2 = LENGTH(ram_wifi) );
-    PROVIDE( _ld_ram_addr2 = ORIGIN(ram_wifi) );
- 
-    /* blog */
-    PROVIDE( _ld_bl_static_blogcomponent_code_start = _bl_static_blogcomponent_code_start );
-    PROVIDE( _ld_bl_static_blogcomponent_code_end   = _bl_static_blogcomponent_code_end );
-    PROVIDE( _ld_bl_static_blogfile_code_start = _bl_static_blogfile_code_start );
-    PROVIDE( _ld_bl_static_blogfile_code_end   = _bl_static_blogfile_code_end );
-    PROVIDE( _ld_bl_static_blogpri_code_start = _bl_static_blogpri_code_start );
-    PROVIDE( _ld_bl_static_blogpri_code_end   = _bl_static_blogpri_code_end );
-
-    PROVIDE( _ld_bl_static_cfg_entry_start = _bl_static_fw_cfg_entry_start );
-    PROVIDE( _ld_bl_static_cfg_entry_end   = _bl_static_fw_cfg_entry_end );
-}
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl606p_ram.ld b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl606p_ram.ld
deleted file mode 100644
index fe07f7ebe9..0000000000
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl606p_ram.ld
+++ /dev/null
@@ -1,277 +0,0 @@
-/****************************************************************************************
-* @file map.txt
-*
-* @brief This file is the map file (gnuarm or armgcc).
-*
-* Copyright (C) BouffaloLab 2018
-*
-****************************************************************************************
-*/
-
-/* configure the CPU type */
-OUTPUT_ARCH( "riscv" )
-/* link with the standard c library */
-INPUT(-lc)
-/* link with the standard GCC library */
-INPUT(-lgcc)
-/* configure the entry point */
-ENTRY(risc_e906_start)
-
-StackSize = 0x0400; /*  1KB */
-
-MEMORY
-{
-    code_memory (rx)  : ORIGIN = 0x22030000, LENGTH = 128K
-    itcm_memory (rx)  : ORIGIN = 0x22028000, LENGTH = 16K
-    dtcm_memory (rx)  : ORIGIN = 0x2202c000, LENGTH = 16K
-    ram_memory  (!rx) : ORIGIN = 0x22020000, LENGTH = 32K
-    ram_wifi    (!rx) : ORIGIN = 0x22050000, LENGTH = 32K
-}
-
-SECTIONS
-{
-    PROVIDE(__metal_chicken_bit = 0);
-    
-    .text :
-    {
-        . = ALIGN(4);
-        __text_code_start__ = .;
-        
-        KEEP (*(SORT_NONE(_start)))
-        KEEP (*(SORT_NONE(risc_e906_start)))
-        
-        *(.text)
-        *(.text.*)
-        
-        *(.rodata)
-        *(.rodata.*)
-    
-        *(.srodata)
-        *(.srodata.*)
-        
-        *(.tcm_code)
-        *(.tcm_const)
-        *(.sclock_rlt_code)
-        *(.sclock_rlt_const)
-
-        /* static cli cmds */
-        . = ALIGN(4);
-        _bl_static_cli_cmds_start = .;
-        KEEP(*(.static_cli_cmds))
-        *(.static_cli_cmds)
-        _bl_static_cli_cmds_end = .;    
-        
-        /* static blog code1 */
-        . = ALIGN(4);
-        _bl_static_blogcomponent_code_start = .;
-        KEEP(SORT(*)(.static_blogcomponent_code*))
-        *(.static_blogcomponent_code*)
-        _bl_static_blogcomponent_code_end = .;
-    
-        /* static blog code2 */
-        . = ALIGN(4);
-        _bl_static_blogfile_code_start = .;
-        KEEP(SORT(*)(.static_blogfile_code*))
-        *(.static_blogfile_code*)
-        _bl_static_blogfile_code_end = .;
-    
-        /* static blog code3 */
-        . = ALIGN(4);
-        _bl_static_blogpri_code_start = .;
-        KEEP(SORT(*)(.static_blogpri_code*))
-        *(.static_blogpri_code*)
-        _bl_static_blogpri_code_end = .;
-    
-        /* static fw attribute entry */
-        . = ALIGN(4);
-        _bl_static_fw_cfg_entry_start = .;
-        KEEP(*(.wifi.cfg.entry))
-        _bl_static_fw_cfg_entry_end = .;
-        . = ALIGN(4);
-
-        __text_code_end__ = .;
-    } > code_memory
-
-    .wifibss  (NOLOAD) :
-    {
-        PROVIDE( __wifi_bss_start = ADDR(.wifibss) );
-        PROVIDE( __wifi_bss_end = ADDR(.wifibss) + SIZEOF(.wifibss) );
-        *ipc_shared.o(COMMON)
-        *sdu_shared.o(COMMON)
-        *hal_desc.o(COMMON)
-        *txl_buffer_shared.o(COMMON)
-        *txl_frame_shared.o(COMMON)
-        *scan_shared.o(COMMON)
-        *scanu_shared.o(COMMON)
-        *mfp_bip.o(COMMON)
-        *me_mic.o(COMMON)
-        *bl_sta_mgmt_others.o(COMMON)
-        *bl_pmk_mgmt.o(COMMON)
-        *bl_pmk_mgmt_internal.o(COMMON)
-        *libwifi_drv.a:bl_utils.o(COMMON)
-        *libwifi_drv.a:bl_utils.o(.bss*)
-        *(.wifi_ram*)
-        . = ALIGN(16);
-    } > ram_wifi
-
-    PROVIDE( _heap_wifi_start = . );
-    PROVIDE( _heap_wifi_size = ORIGIN(ram_wifi) + LENGTH(ram_wifi) - _heap_wifi_start );
-
- 
-
-    /*SYMOBOL used in code*/
-    PROVIDE( _ld_bl_static_cli_cmds_start = _bl_static_cli_cmds_start );
-    PROVIDE( _ld_bl_static_cli_cmds_end   = _bl_static_cli_cmds_end );
-
-    . = ALIGN(4);
-    __itcm_load_addr = .;
-    
-    .itcm_region : AT (__itcm_load_addr)
-    {
-        . = ALIGN(4);
-        __tcm_code_start__ = .;
-        
-        . = ALIGN(4);
-        __tcm_code_end__ = .;
-    } > itcm_memory
-    
-    __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region);
-    
-    .dtcm_region : AT (__dtcm_load_addr)
-    {
-        . = ALIGN(4);
-        __tcm_data_start__ = .;
-        
-        *(.tcm_data)
-        /* *finger_print.o(.data*) */
-        
-        . = ALIGN(4);
-        __tcm_data_end__ = .;
-    } > dtcm_memory
-    
-    /*************************************************************************/
-    /* .stack_dummy section doesn't contains any symbols. It is only
-     * used for linker to calculate size of stack sections, and assign
-     * values to stack symbols later */
-    .stack_dummy (NOLOAD):
-    {
-        . = ALIGN(0x4);
-        . = . + StackSize;
-        . = ALIGN(0x4);
-    } > dtcm_memory
-    
-    /* Set stack top to end of RAM, and stack limit move down by
-     * size of stack_dummy section */
-    __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);
-    PROVIDE( __freertos_irq_stack_top = __StackTop);
-    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
-    
-    /* Check if data + heap + stack exceeds RAM limit */
-    ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack")
-    /*************************************************************************/
-    
-    __system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
-    
-    .system_ram_data_region : AT (__system_ram_load_addr)
-    {
-        . = ALIGN(4);
-        __system_ram_data_start__ = .;
-        
-        *(.system_ram)
-        
-        . = ALIGN(4);
-        __system_ram_data_end__ = .;
-    } > ram_memory
-    
-    __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region);
-    
-    /* Data section */
-    RAM_DATA : AT (__ram_load_addr)
-    {
-        . = ALIGN(4);
-        __ram_data_start__ = .;
-        
-        PROVIDE( __global_pointer$ = . + 0x800 );
-        
-        *(.data)
-        *(.data.*)
-        *(.sdata)
-        *(.sdata.*)
-        *(.sdata2)
-        *(.sdata2.*)
-        
-        _bt_gatt_service_static_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_gatt_service_static.static.*")))
-        _bt_gatt_service_static_list_end = .;
-        _bt_l2cap_fixed_chan_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_l2cap_fixed_chan.static.*")))
-        _bt_l2cap_fixed_chan_list_end = .;
-        _bt_l2cap_br_fixed_chan_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_l2cap_br_fixed_chan.static.*")))
-        _bt_l2cap_br_fixed_chan_list_end = .;
-
-        . = ALIGN(4);
-        __ram_data_end__ = .;
-    } > ram_memory
-    
-    
-    .noinit_data (NOLOAD) :
-    {
-        . = ALIGN(4);
-        __noinit_data_start__ = .;
-        
-        *(.noinit_data*)
-        
-        . = ALIGN(4);
-        __noinit_data_end__ = .;
-    } > ram_memory
-    
-    .bss (NOLOAD) :
-    {
-        . = ALIGN(4);
-        __bss_start__ = .;
-        
-        *(.bss*)
-        *(.sbss*)
-        *(COMMON)
- 
-        . = ALIGN(4);
-        __bss_end__ = .;
-    } > ram_memory
-
-    .heap (NOLOAD):
-    {
-        . = ALIGN(4);
-        __HeapBase = .;
-        _heap_start = .;
-        
-        /*__end__ = .;*/
-        /*end = __end__;*/
-        KEEP(*(.heap*))
-        
-        . = ALIGN(4);
-        __HeapLimit = .;
-    } > ram_memory
-    __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory);
-    _heap_size = __HeapLimit - __HeapBase;
-}
-
-PROVIDE( _ld_ram_size0 = LENGTH(ram_memory) );
-PROVIDE( _ld_ram_addr0 = ORIGIN(ram_memory) );
-PROVIDE( _ld_ram_size1 = 0);
-PROVIDE( _ld_ram_addr1 = 0);
-PROVIDE( _ld_ram_size2 = LENGTH(ram_wifi) );
-PROVIDE( _ld_ram_addr2 = ORIGIN(ram_wifi) );
-
-/* blog */
-PROVIDE( _ld_bl_static_blogcomponent_code_start = _bl_static_blogcomponent_code_start );
-PROVIDE( _ld_bl_static_blogcomponent_code_end   = _bl_static_blogcomponent_code_end );
-PROVIDE( _ld_bl_static_blogfile_code_start = _bl_static_blogfile_code_start );
-PROVIDE( _ld_bl_static_blogfile_code_end   = _bl_static_blogfile_code_end );
-PROVIDE( _ld_bl_static_blogpri_code_start = _bl_static_blogpri_code_start );
-PROVIDE( _ld_bl_static_blogpri_code_end   = _bl_static_blogpri_code_end );
-
-
-PROVIDE( _ld_bl_static_cfg_entry_start = _bl_static_fw_cfg_entry_start );
-PROVIDE( _ld_bl_static_cfg_entry_end   = _bl_static_fw_cfg_entry_end );
-
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl606p_ram_phyrf.ld b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl606p_ram_phyrf.ld
deleted file mode 100644
index 23ff22baef..0000000000
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl606p_ram_phyrf.ld
+++ /dev/null
@@ -1,288 +0,0 @@
-/****************************************************************************************
-* @file map.txt
-*
-* @brief This file is the map file (gnuarm or armgcc).
-*
-* Copyright (C) BouffaloLab 2018
-*
-****************************************************************************************
-*/
-
-/* configure the CPU type */
-OUTPUT_ARCH( "riscv" )
-/* link with the standard c library */
-INPUT(-lc)
-/* link with the standard GCC library */
-INPUT(-lgcc)
-/* configure the entry point */
-ENTRY(risc_e906_start)
-
-StackSize = 0x0400; /*  1KB */
-
-MEMORY
-{
-    code_memory       (rx)  : ORIGIN = 0x22030000, LENGTH = 128K
-    ram_wifi          (!rx) : ORIGIN = 0x22050000, LENGTH = 32K
-    ram_memory        (!rx) : ORIGIN = 0x22020000, LENGTH = 28K
-    itcm_memory       (rx)  : ORIGIN = 0x22027000, LENGTH = 2K
-    dtcm_memory       (rx)  : ORIGIN = 0x22027800, LENGTH = 2K
-    test_ocram        (!rx) : ORIGIN = 0x22028000, LENGTH = 32K
-}
-
-SECTIONS
-{
-    PROVIDE(__metal_chicken_bit = 0);
-    
-    .text :
-    {
-        . = ALIGN(4);
-        __text_code_start__ = .;
-        
-        KEEP (*(SORT_NONE(_start)))
-        KEEP (*(SORT_NONE(risc_e906_start)))
-        
-        *(.text)
-        *(.text.*)
-        
-        *(.rodata)
-        *(.rodata.*)
-    
-        *(.srodata)
-        *(.srodata.*)
-        
-        *(.tcm_code)
-        *(.tcm_const)
-        *(.sclock_rlt_code)
-        *(.sclock_rlt_const)
-
-        /* static cli cmds */
-        . = ALIGN(4);
-        _bl_static_cli_cmds_start = .;
-        KEEP(*(.static_cli_cmds))
-        *(.static_cli_cmds)
-        _bl_static_cli_cmds_end = .;    
-        
-        /* static blog code1 */
-        . = ALIGN(4);
-        _bl_static_blogcomponent_code_start = .;
-        KEEP(SORT(*)(.static_blogcomponent_code*))
-        *(.static_blogcomponent_code*)
-        _bl_static_blogcomponent_code_end = .;
-    
-        /* static blog code2 */
-        . = ALIGN(4);
-        _bl_static_blogfile_code_start = .;
-        KEEP(SORT(*)(.static_blogfile_code*))
-        *(.static_blogfile_code*)
-        _bl_static_blogfile_code_end = .;
-    
-        /* static blog code3 */
-        . = ALIGN(4);
-        _bl_static_blogpri_code_start = .;
-        KEEP(SORT(*)(.static_blogpri_code*))
-        *(.static_blogpri_code*)
-        _bl_static_blogpri_code_end = .;
-    
-        /* static fw attribute entry */
-        . = ALIGN(4);
-        _bl_static_fw_cfg_entry_start = .;
-        KEEP(*(.wifi.cfg.entry))
-        _bl_static_fw_cfg_entry_end = .;
-        . = ALIGN(4);
-
-        __text_code_end__ = .;
-    } > code_memory
-
-    .wifibss  (NOLOAD) :
-    {
-        PROVIDE( __wifi_bss_start = ADDR(.wifibss) );
-        PROVIDE( __wifi_bss_end = ADDR(.wifibss) + SIZEOF(.wifibss) );
-        *ipc_shared.o(COMMON)
-        *sdu_shared.o(COMMON)
-        *hal_desc.o(COMMON)
-        *txl_buffer_shared.o(COMMON)
-        *txl_frame_shared.o(COMMON)
-        *scan_shared.o(COMMON)
-        *scanu_shared.o(COMMON)
-        *mfp_bip.o(COMMON)
-        *me_mic.o(COMMON)
-        *bl_sta_mgmt_others.o(COMMON)
-        *bl_pmk_mgmt.o(COMMON)
-        *bl_pmk_mgmt_internal.o(COMMON)
-        *libwifi_drv.a:bl_utils.o(COMMON)
-        *libwifi_drv.a:bl_utils.o(.bss*)
-        *(.wifi_ram*)
-        . = ALIGN(16);
-    } > ram_wifi
-
-    PROVIDE( _heap_wifi_start = . );
-    PROVIDE( _heap_wifi_size = ORIGIN(ram_wifi) + LENGTH(ram_wifi) - _heap_wifi_start );
-
-    /*SYMOBOL used in code*/
-    PROVIDE( _ld_bl_static_cli_cmds_start = _bl_static_cli_cmds_start );
-    PROVIDE( _ld_bl_static_cli_cmds_end   = _bl_static_cli_cmds_end );
-
-    . = ALIGN(4);
-    __itcm_load_addr = .;
-    
-    .itcm_region : AT (__itcm_load_addr)
-    {
-        . = ALIGN(4);
-        __tcm_code_start__ = .;
-        
-        . = ALIGN(4);
-        __tcm_code_end__ = .;
-    } > itcm_memory
-    
-    __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region);
-    
-    .dtcm_region : AT (__dtcm_load_addr)
-    {
-        . = ALIGN(4);
-        __tcm_data_start__ = .;
-        
-        *(.tcm_data)
-        /* *finger_print.o(.data*) */
-        
-        . = ALIGN(4);
-        __tcm_data_end__ = .;
-    } > dtcm_memory
-    
-    /*************************************************************************/
-    /* .stack_dummy section doesn't contains any symbols. It is only
-     * used for linker to calculate size of stack sections, and assign
-     * values to stack symbols later */
-    .stack_dummy (NOLOAD):
-    {
-        . = ALIGN(0x4);
-        . = . + StackSize;
-        . = ALIGN(0x4);
-    } > dtcm_memory
-    
-    /* Set stack top to end of RAM, and stack limit move down by
-     * size of stack_dummy section */
-    __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);
-    PROVIDE( __freertos_irq_stack_top = __StackTop);
-    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
-    
-    /* Check if data + heap + stack exceeds RAM limit */
-    ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack")
-    /*************************************************************************/
-    
-    __system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
-    
-    .system_ram_data_region : AT (__system_ram_load_addr)
-    {
-        . = ALIGN(4);
-        __system_ram_data_start__ = .;
-        
-        *(.system_ram)
-        
-        . = ALIGN(4);
-        __system_ram_data_end__ = .;
-    } > ram_memory
-    
-    __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region);
-    
-    /* Data section */
-    RAM_DATA : AT (__ram_load_addr)
-    {
-        . = ALIGN(4);
-        __ram_data_start__ = .;
-        
-        PROVIDE( __global_pointer$ = . + 0x800 );
-        
-        *(.data)
-        *(.data.*)
-        *(.sdata)
-        *(.sdata.*)
-        *(.sdata2)
-        *(.sdata2.*)
-        
-        _bt_gatt_service_static_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_gatt_service_static.static.*")))
-        _bt_gatt_service_static_list_end = .;
-        _bt_l2cap_fixed_chan_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_l2cap_fixed_chan.static.*")))
-        _bt_l2cap_fixed_chan_list_end = .;
-        _bt_l2cap_br_fixed_chan_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_l2cap_br_fixed_chan.static.*")))
-        _bt_l2cap_br_fixed_chan_list_end = .;
-
-        . = ALIGN(4);
-        __ram_data_end__ = .;
-    } > ram_memory
-    
-    .noinit_data (NOLOAD) :
-    {
-        . = ALIGN(4);
-        __noinit_data_start__ = .;
-        
-        *(.noinit_data*)
-        
-        . = ALIGN(4);
-        __noinit_data_end__ = .;
-    } > ram_memory
-    
-    .bss (NOLOAD) :
-    {
-        . = ALIGN(4);
-        __bss_start__ = .;
-        
-        *(.bss*)
-        *(.sbss*)
-        *(COMMON)
- 
-        . = ALIGN(4);
-        __bss_end__ = .;
-    } > ram_memory
-
-    .heap (NOLOAD):
-    {
-        . = ALIGN(4);
-        __HeapBase = .;
-        _heap_start = .;
-        
-        /*__end__ = .;*/
-        /*end = __end__;*/
-        KEEP(*(.heap*))
-        
-        . = ALIGN(4);
-        __HeapLimit = .;
-    } > ram_memory
-    __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory);
-    _heap_size = __HeapLimit - __HeapBase;
-
-    /* keep my variable even if not referenced */
-    /* .testmem_at_ocram (NOLOAD) : 
-    {
-        PROVIDE( __testmem_at_ocram_start_addr = ADDR(.testmem_at_ocram) );
-        PROVIDE( __testmem_at_wram_start_addr = ADDR(.testmem_at_ocram) + SIZEOF(.testmem_at_ocram) );
-        KEEP(*(.testmem_at_ocram))
-    } > ram_test */
-
-    /* __testmem_at_ocram_start_addr = ORIGIN(ram_test);
-    __testmem_at_wram_start_addr = ORIGIN(wifi_ram); */
-
-    __testmem_at_ocram_start_addr = ORIGIN(test_ocram);
-    __testmem_at_wram_start_addr = ORIGIN(ram_wifi);
-}
-
-PROVIDE( _ld_ram_size0 = LENGTH(ram_memory) );
-PROVIDE( _ld_ram_addr0 = ORIGIN(ram_memory) );
-PROVIDE( _ld_ram_size1 = 0);
-PROVIDE( _ld_ram_addr1 = 0);
-PROVIDE( _ld_ram_size2 = LENGTH(ram_wifi) );
-PROVIDE( _ld_ram_addr2 = ORIGIN(ram_wifi) );
-
-/* blog */
-PROVIDE( _ld_bl_static_blogcomponent_code_start = _bl_static_blogcomponent_code_start );
-PROVIDE( _ld_bl_static_blogcomponent_code_end   = _bl_static_blogcomponent_code_end );
-PROVIDE( _ld_bl_static_blogfile_code_start = _bl_static_blogfile_code_start );
-PROVIDE( _ld_bl_static_blogfile_code_end   = _bl_static_blogfile_code_end );
-PROVIDE( _ld_bl_static_blogpri_code_start = _bl_static_blogpri_code_start );
-PROVIDE( _ld_bl_static_blogpri_code_end   = _bl_static_blogpri_code_end );
-
-
-PROVIDE( _ld_bl_static_cfg_entry_start = _bl_static_fw_cfg_entry_start );
-PROVIDE( _ld_bl_static_cfg_entry_end   = _bl_static_fw_cfg_entry_end );
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_flash.ld b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_flash.ld
deleted file mode 100644
index abb4c12666..0000000000
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_flash.ld
+++ /dev/null
@@ -1,374 +0,0 @@
-/****************************************************************************************
-* @file map.txt
-*
-* @brief This file is the map file (gnuarm or armgcc).
-*
-* Copyright (C) BouffaloLab 2018
-*
-****************************************************************************************
-*/
-
-/* configure the CPU type */
-OUTPUT_ARCH( "riscv" )
-/* link with the standard c library */
-INPUT(-lc)
-/* link with the standard GCC library */
-INPUT(-lgcc)
-/* configure the entry point */
-ENTRY(risc_e906_start)
-
-StackSize = 0x0400; /*  1KB */
-BOOT2_PT_ADDR = 0x22057C00;
-BOOT2_FLASHCFG_ADDR = 0x22057c18;
-
-MEMORY
-{
-    flash    (rxai!w) : ORIGIN = 0x58000000, LENGTH = 4M
-    xram_memory (!rx) : ORIGIN = 0x22020000, LENGTH = 16K 
-    ram_memory  (!rx) : ORIGIN = 0x22024000, LENGTH = 48K
-    ram_wifi    (!rx) : ORIGIN = 0x22030000, LENGTH = 96K 
-    ram_psram  (!rx)  : ORIGIN = 0x50000000, LENGTH = 1M
-    bugkill   (rxai!w) : ORIGIN = 0xD0000000, LENGTH = 16M
-}
-
-SECTIONS
-{
-    PROVIDE(__metal_chicken_bit = 0);
-    
-    .text.boot :
-    {
-        . = ALIGN(4);
-    
-        *(.text.startup)
-
-        . = ALIGN(4);
-    } > flash
-
-    .bugkiller_command :
-    {
-        PROVIDE( __bugkiller_command_start = ADDR(.bugkiller_command) );
-        PROVIDE( __bugkiller_command_end = ADDR(.bugkiller_command) + SIZEOF(.bugkiller_command) );
-        KEEP (*(.static_bugkiller_command))
-    } > bugkill
-
-    .bugkiller :
-    {
-        KEEP (*(.bugkiller_code))
-        KEEP (*bugkiller*.o(.rodata* .text* .data* .sdata* .sbss*))
-    } > bugkill
-
-    .psram_ram_data_region : 
-    {
-        . = ALIGN(4);
-        __psram_ram_data_start__ = .;
- 
-        *(.psram_data.*)
-        *liblwip.a:*.o(.text*)
-        *libwifi.a:*.o(.text*)
-        *libwifi_manager.a:*.o(.text*)
-        *libfreertos_e907.a:*.o(.text*)
-        *libnetutils.a:*.o(.text*)
-        *libutils.a:*.o(.text*)
-        *libstartup_bl808.a:debug.o(.text*)
-
-        *liblwip.a:*.o(.rodata*)
-        *libwifi.a:*.o(.rodata*)
-        *libwifi_manager.a:*.o(.rodata*)
-        *libfreertos_e907.a:*.o(.rodata*)
-        *libnetutils.a:*.o(.rodata*)
-        *libutils.a:*.o(.rodata*)
-        *libstartup_bl808.a:debug.o(.rodata*)
-        
-        . = ALIGN(4);
-        __psram_ram_data_end__ = .;
-    } > ram_psram AT > flash
-
-    .text :
-    {
-        . = ALIGN(4);
-    
-        *(.text)
-        *(.text.*)
-
-        . = ALIGN(4);
-
-        /* section information for finsh shell */
-        . = ALIGN(4);
-        __fsymtab_start = .;
-        KEEP(*(FSymTab))
-        __fsymtab_end = .;
-        . = ALIGN(4);
-        __vsymtab_start = .;
-        KEEP(*(VSymTab))
-        __vsymtab_end = .;
-        . = ALIGN(4);
-
-        /* section information for modules */
-        . = ALIGN(4);
-        __rtmsymtab_start = .;
-        KEEP(*(RTMSymTab))
-        __rtmsymtab_end = .;
-
-        /* section information for initialization */
-        . = ALIGN(4);
-        __rt_init_start = .;
-        KEEP(*(SORT(.rti_fn*)))
-        __rt_init_end = .;
-
-    } > flash
-
-    .rodata :
-    {
-        . = ALIGN(4);
-        
-        *(.rodata)
-        *(.rodata.*)
-    
-        *(.srodata)
-        *(.srodata.*)
-
-        /* static cli cmds */
-        . = ALIGN(4);
-        _bl_static_cli_cmds_start = .;
-        KEEP(*(.static_cli_cmds))
-        *(.static_cli_cmds)
-        _bl_static_cli_cmds_end = .;    
-        
-        /* static blog code1 */
-        . = ALIGN(4);
-        _bl_static_blogcomponent_code_start = .;
-        KEEP(SORT(*)(.static_blogcomponent_code*))
-        *(.static_blogcomponent_code*)
-        _bl_static_blogcomponent_code_end = .;
-    
-        /* static blog code2 */
-        . = ALIGN(4);
-        _bl_static_blogfile_code_start = .;
-        KEEP(SORT(*)(.static_blogfile_code*))
-        *(.static_blogfile_code*)
-        _bl_static_blogfile_code_end = .;
-    
-        /* static blog code3 */
-        . = ALIGN(4);
-        _bl_static_blogpri_code_start = .;
-        KEEP(SORT(*)(.static_blogpri_code*))
-        *(.static_blogpri_code*)
-        _bl_static_blogpri_code_end = .;
-    
-        /* static fw attribute entry */
-        . = ALIGN(4);
-        _bl_static_fw_cfg_entry_start = .;
-        KEEP(*(.wifi.cfg.entry))
-        _bl_static_fw_cfg_entry_end = .;
-        . = ALIGN(4);
-
-    } > flash
-
-    .itcm_region :
-    {
-        . = ALIGN(4);
-        __tcm_code_start__ = .;
-
-        *(.tcm_code)
-        *(.tcm_code.*)
-        *(.tcm_const)
-        *(.tcm_const.*)
-        *(.sclock_rlt_code)
-        *(.sclock_rlt_code.*)
-        *(.sclock_rlt_const)
-        *(.sclock_rlt_const.*)
-        
-        . = ALIGN(4);
-        __tcm_code_end__ = .;
-    } > ram_psram AT > flash
-
-    .dtcm_region : 
-    {
-        . = ALIGN(4);
-        __tcm_data_start__ = .;
-        
-        *(.tcm_data)
-        
-        . = ALIGN(4);
-        __tcm_data_end__ = .;
-    } > ram_psram AT > flash
-
-    .stack_dummy (NOLOAD):
-    {
-	PROVIDE ( _sp_base = . );
-        . = ALIGN(64);
-        __stack_protect_start = .;
-        . = . + 256;
-        __stack_protect_end = .;
-        . = . + StackSize;
-        . = ALIGN(64);
-	PROVIDE( _sp_main = . );
-    } > ram_psram
-
-    .system_ram_data_region : 
-    {
-        . = ALIGN(4);
-        __system_ram_data_start__ = .;
- 
-        *(.system_ram)
-        
-        . = ALIGN(4);
-        __system_ram_data_end__ = .;
-    } > ram_psram AT > flash
-
-    .data : 
-    {
-        . = ALIGN(4);
-        __ram_data_start__ = .;
-
-        PROVIDE( __global_pointer$ = . + 0x800 );
-        
-        *(.data)
-        *(.data.*)
-        *(.sdata)
-        *(.sdata.*)
-        *(.sdata2)
-        *(.sdata2.*)
-        
-        _bt_gatt_service_static_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_gatt_service_static.static.*")))
-        _bt_gatt_service_static_list_end = .;
-        _bt_l2cap_fixed_chan_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_l2cap_fixed_chan.static.*")))
-        _bt_l2cap_fixed_chan_list_end = .;
-        _bt_l2cap_br_fixed_chan_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_l2cap_br_fixed_chan.static.*")))
-        _bt_l2cap_br_fixed_chan_list_end = .;
-
-        . = ALIGN(4);
-        __ram_data_end__ = .;
-    } > ram_psram AT > flash
-
-    .xrambss  (NOLOAD) :
-    {
-        __xram_load_addr = .;
-        
-        . = ALIGN(4);
-        __xram_data_start__ = .;
-
-        *(.static_xram_region)
-
-        __xram_data_end__ = .;
-        . = ALIGN(4);
-    } > xram_memory
-
-    .ocram_bss_region (NOLOAD) :
-    {
-        . = ALIGN(4);
-        __ocram_bss_start__ = .;
-
-        *(.nocache_ram)
-
-        . = ALIGN(4);
-        __ocram_bss_end__ = .;
-    } > ram_memory
-
-    .boot2 (NOLOAD) :
-    {
-        PROVIDE ( __boot2_pt_addr_start = . );
-        *(.bss.boot2_partition_table)
-        PROVIDE ( __boot2_pt_addr_end   = . );
-
-        PROVIDE ( __boot2_flashCfg_start = . );
-        *(.bss.boot2_flashCfg)
-        PROVIDE ( __boot2_flashCfg_end = . );
-
-    } > ram_psram
-    
-    .wifibss  (NOLOAD) :
-    {
-        PROVIDE( __wifi_bss_start = ADDR(.wifibss) );
-        PROVIDE( __wifi_bss_end = ADDR(.wifibss) + SIZEOF(.wifibss) );
-        *ipc_shared.o(COMMON)
-        *sdu_shared.o(COMMON)
-        *hal_desc.o(COMMON)
-        *txl_buffer_shared.o(COMMON)
-        *txl_frame_shared.o(COMMON)
-        *scan_shared.o(COMMON)
-        *scanu_shared.o(COMMON)
-        *mfp_bip.o(COMMON)
-        *me_mic.o(COMMON)
-        *bl_sta_mgmt_others.o(COMMON)
-        *bl_pmk_mgmt.o(COMMON)
-        *bl_pmk_mgmt_internal.o(COMMON)
-        *libwifi_drv.a:bl_utils.o(COMMON)
-        *libwifi_drv.a:bl_utils.o(.bss*)
-        *(.wifi_ram*)
-        . = ALIGN(16);
-    } > ram_wifi
-
-    .bss (NOLOAD) :
-    {
-        . = ALIGN(4);
-        __bss_start__ = .;
-        
-        *(.bss*)
-        *(.sbss*)
-        *(.noinit_data*)
-        *(COMMON)
- 
-        . = ALIGN(4);
-        __bss_end__ = .;
-    } > ram_psram 
-
-    .heap (NOLOAD):
-    {
-        . = ALIGN(4);
-        __HeapBase = .;
-        _heap_start = .;
-        
-        KEEP(*(.heap*))
-        
-        . = ALIGN(4);
-        __HeapLimit = .;
-        _heap_end = .;
-    } > ram_psram 
-
-    __StackTop = ADDR(.stack_dummy) + SIZEOF(.stack_dummy);
-    PROVIDE( __freertos_irq_stack_top = __StackTop);
-    __StackLimit = ADDR(.stack_dummy);
-
-    __HeapLimit = ORIGIN(ram_psram) + LENGTH(ram_psram);
-    _heap_size = __HeapLimit - _heap_start;
-
-    PROVIDE( __itcm_load_addr = LOADADDR(.itcm_region));
-    PROVIDE( __dtcm_load_addr = LOADADDR(.dtcm_region));
-    PROVIDE( __system_ram_load_addr = LOADADDR(.system_ram_data_region));
-    PROVIDE( __psram_ram_load_addr = LOADADDR(.psram_ram_data_region));
-    PROVIDE( __ram_load_addr = LOADADDR(.data));
-
-    /*SYMOBOL used in code*/
-    PROVIDE( _ld_bl_static_cli_cmds_start = _bl_static_cli_cmds_start );
-    PROVIDE( _ld_bl_static_cli_cmds_end   = _bl_static_cli_cmds_end );
-
-    /*BOOT2 sections*/
-    PROVIDE ( __boot2_pt_addr_src = BOOT2_PT_ADDR );
-    PROVIDE ( __boot2_flashCfg_src = BOOT2_FLASHCFG_ADDR );
-    
-    PROVIDE( _ld_ram_size0 = LENGTH(flash) );
-    PROVIDE( _ld_ram_addr0 = ORIGIN(flash) );
-    PROVIDE( _ld_ram_size1 = LENGTH(ram_psram) );
-    PROVIDE( _ld_ram_addr1 = ORIGIN(ram_psram) );
-    PROVIDE( _ld_ram_size2 = LENGTH(ram_wifi) );
-    PROVIDE( _ld_ram_addr2 = ORIGIN(ram_wifi) );
-    PROVIDE( _ld_ram_size3 = LENGTH(ram_memory) );
-    PROVIDE( _ld_ram_addr3 = ORIGIN(ram_memory) );
-    PROVIDE( _ld_ram_size4 = LENGTH(xram_memory) );
-    PROVIDE( _ld_ram_addr4 = ORIGIN(xram_memory) );
- 
-    /* blog */
-    PROVIDE( _ld_bl_static_blogcomponent_code_start = _bl_static_blogcomponent_code_start );
-    PROVIDE( _ld_bl_static_blogcomponent_code_end   = _bl_static_blogcomponent_code_end );
-    PROVIDE( _ld_bl_static_blogfile_code_start = _bl_static_blogfile_code_start );
-    PROVIDE( _ld_bl_static_blogfile_code_end   = _bl_static_blogfile_code_end );
-    PROVIDE( _ld_bl_static_blogpri_code_start = _bl_static_blogpri_code_start );
-    PROVIDE( _ld_bl_static_blogpri_code_end   = _bl_static_blogpri_code_end );
-
-    PROVIDE( _ld_bl_static_cfg_entry_start = _bl_static_fw_cfg_entry_start );
-    PROVIDE( _ld_bl_static_cfg_entry_end   = _bl_static_fw_cfg_entry_end );
-}
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_flash_no_wifi.ld b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_flash_no_wifi.ld
deleted file mode 100644
index 1a9a7a5105..0000000000
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_flash_no_wifi.ld
+++ /dev/null
@@ -1,357 +0,0 @@
-/****************************************************************************************
-* @file map.txt
-*
-* @brief This file is the map file (gnuarm or armgcc).
-*
-* Copyright (C) BouffaloLab 2018
-*
-****************************************************************************************
-*/
-
-/* configure the CPU type */
-OUTPUT_ARCH( "riscv" )
-/* link with the standard c library */
-INPUT(-lc)
-/* link with the standard GCC library */
-INPUT(-lgcc)
-/* configure the entry point */
-ENTRY(risc_e906_start)
-
-StackSize = 0x0400; /*  1KB */
-BOOT2_PT_ADDR = 0x22057C00;
-BOOT2_FLASHCFG_ADDR = 0x22057c18;
-
-MEMORY
-{
-    flash    (rxai!w) : ORIGIN = 0x58000000, LENGTH = 4M
-    xram_memory (!rx) : ORIGIN = 0x22020000, LENGTH = 16K 
-    ram_memory  (!rx) : ORIGIN = 0x22024000, LENGTH = 208K
-    ram_wifi    (!rx) : ORIGIN = 0x22058000, LENGTH = 0K
-    ram_psram  (!rx)  : ORIGIN = 0x50000000, LENGTH = 1M
-    bugkill   (rxai!w) : ORIGIN = 0xD0000000, LENGTH = 16M
-}
-
-SECTIONS
-{
-    PROVIDE(__metal_chicken_bit = 0);
-    
-    .text.boot :
-    {
-        . = ALIGN(4);
-    
-        *(.text.startup)
-
-        . = ALIGN(4);
-    } > flash
-
-    .bugkiller_command :
-    {
-        PROVIDE( __bugkiller_command_start = ADDR(.bugkiller_command) );
-        PROVIDE( __bugkiller_command_end = ADDR(.bugkiller_command) + SIZEOF(.bugkiller_command) );
-        KEEP (*(.static_bugkiller_command))
-    } > bugkill
-
-    .bugkiller :
-    {
-        KEEP (*(.bugkiller_code))
-        KEEP (*bugkiller*.o(.rodata* .text* .data* .sdata* .sbss*))
-    } > bugkill
-
-    .psram_ram_data_region : 
-    {
-        . = ALIGN(4);
-        __psram_ram_data_start__ = .;
- 
-        *(.psram_data.*)
-        *liblwip.a:*.o(.text*)
-        *libwifi.a:*.o(.text*)
-        *libwifi_manager.a:*.o(.text*)
-        *libfreertos_e907.a:*.o(.text*)
-        *libnetutils.a:*.o(.text*)
-        *libutils.a:*.o(.text*)
-        *libstartup_bl808.a:debug.o(.text*)
-
-        *liblwip.a:*.o(.rodata*)
-        *libwifi.a:*.o(.rodata*)
-        *libwifi_manager.a:*.o(.rodata*)
-        *libfreertos_e907.a:*.o(.rodata*)
-        *libnetutils.a:*.o(.rodata*)
-        *libutils.a:*.o(.rodata*)
-        *libstartup_bl808.a:debug.o(.rodata*)
-        
-        . = ALIGN(4);
-        __psram_ram_data_end__ = .;
-    } > ram_memory AT > flash
-
-    .text :
-    {
-        . = ALIGN(4);
-    
-        *(.text)
-        *(.text.*)
-
-        . = ALIGN(4);
-    } > flash
-
-    .rodata :
-    {
-        . = ALIGN(4);
-        
-        *(.rodata)
-        *(.rodata.*)
-    
-        *(.srodata)
-        *(.srodata.*)
-
-        /* static cli cmds */
-        . = ALIGN(4);
-        _bl_static_cli_cmds_start = .;
-        KEEP(*(.static_cli_cmds))
-        *(.static_cli_cmds)
-        _bl_static_cli_cmds_end = .;    
-        
-        /* static blog code1 */
-        . = ALIGN(4);
-        _bl_static_blogcomponent_code_start = .;
-        KEEP(SORT(*)(.static_blogcomponent_code*))
-        *(.static_blogcomponent_code*)
-        _bl_static_blogcomponent_code_end = .;
-    
-        /* static blog code2 */
-        . = ALIGN(4);
-        _bl_static_blogfile_code_start = .;
-        KEEP(SORT(*)(.static_blogfile_code*))
-        *(.static_blogfile_code*)
-        _bl_static_blogfile_code_end = .;
-    
-        /* static blog code3 */
-        . = ALIGN(4);
-        _bl_static_blogpri_code_start = .;
-        KEEP(SORT(*)(.static_blogpri_code*))
-        *(.static_blogpri_code*)
-        _bl_static_blogpri_code_end = .;
-    
-        /* static fw attribute entry */
-        . = ALIGN(4);
-        _bl_static_fw_cfg_entry_start = .;
-        KEEP(*(.wifi.cfg.entry))
-        _bl_static_fw_cfg_entry_end = .;
-        . = ALIGN(4);
-
-    } > flash
-
-    .itcm_region :
-    {
-        . = ALIGN(4);
-        __tcm_code_start__ = .;
-
-        *(.tcm_code)
-        *(.tcm_code.*)
-        *(.tcm_const)
-        *(.tcm_const.*)
-        *(.sclock_rlt_code)
-        *(.sclock_rlt_code.*)
-        *(.sclock_rlt_const)
-        *(.sclock_rlt_const.*)
-        
-        . = ALIGN(4);
-        __tcm_code_end__ = .;
-    } > ram_memory AT > flash
-
-    .dtcm_region : 
-    {
-        . = ALIGN(4);
-        __tcm_data_start__ = .;
-        
-        *(.tcm_data)
-        
-        . = ALIGN(4);
-        __tcm_data_end__ = .;
-    } > ram_memory AT > flash
-
-    .system_ram_data_region : 
-    {
-        . = ALIGN(4);
-        __system_ram_data_start__ = .;
- 
-        *(.system_ram)
-        
-        . = ALIGN(4);
-        __system_ram_data_end__ = .;
-    } > ram_memory AT > flash
-
-    .data : 
-    {
-        . = ALIGN(4);
-        __ram_data_start__ = .;
-
-        PROVIDE( __global_pointer$ = . + 0x800 );
-        
-        *(.data)
-        *(.data.*)
-        *(.sdata)
-        *(.sdata.*)
-        *(.sdata2)
-        *(.sdata2.*)
-        
-        _bt_gatt_service_static_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_gatt_service_static.static.*")))
-        _bt_gatt_service_static_list_end = .;
-        _bt_l2cap_fixed_chan_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_l2cap_fixed_chan.static.*")))
-        _bt_l2cap_fixed_chan_list_end = .;
-        _bt_l2cap_br_fixed_chan_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_l2cap_br_fixed_chan.static.*")))
-        _bt_l2cap_br_fixed_chan_list_end = .;
-
-        . = ALIGN(4);
-        __ram_data_end__ = .;
-    } > ram_memory AT > flash
-
-    .xrambss  (NOLOAD) :
-    {
-        __xram_load_addr = .;
-        
-        . = ALIGN(4);
-        __xram_data_start__ = .;
-
-        *(.static_xram_region)
-
-        __xram_data_end__ = .;
-        . = ALIGN(4);
-    } > xram_memory
-
-    .ocram_bss_region (NOLOAD) :
-    {
-        . = ALIGN(4);
-        __ocram_bss_start__ = .;
-
-        *(.nocache_ram)
-
-        . = ALIGN(4);
-        __ocram_bss_end__ = .;
-    } > ram_memory
-
-    .boot2 (NOLOAD) :
-    {
-        PROVIDE ( __boot2_pt_addr_start = . );
-        *(.bss.boot2_partition_table)
-        PROVIDE ( __boot2_pt_addr_end   = . );
-
-        PROVIDE ( __boot2_flashCfg_start = . );
-        *(.bss.boot2_flashCfg)
-        PROVIDE ( __boot2_flashCfg_end = . );
-
-    } > ram_memory
-    
-    .wifibss  (NOLOAD) :
-    {
-        PROVIDE( __wifi_bss_start = ADDR(.wifibss) );
-        PROVIDE( __wifi_bss_end = ADDR(.wifibss) + SIZEOF(.wifibss) );
-        *ipc_shared.o(COMMON)
-        *sdu_shared.o(COMMON)
-        *hal_desc.o(COMMON)
-        *txl_buffer_shared.o(COMMON)
-        *txl_frame_shared.o(COMMON)
-        *scan_shared.o(COMMON)
-        *scanu_shared.o(COMMON)
-        *mfp_bip.o(COMMON)
-        *me_mic.o(COMMON)
-        *bl_sta_mgmt_others.o(COMMON)
-        *bl_pmk_mgmt.o(COMMON)
-        *bl_pmk_mgmt_internal.o(COMMON)
-        *libwifi_drv.a:bl_utils.o(COMMON)
-        *libwifi_drv.a:bl_utils.o(.bss*)
-        *(.wifi_ram*)
-        . = ALIGN(16);
-    } > ram_memory
-
-    .psram_bss (NOLOAD) :
-    {
-        . = ALIGN(4);
-        *(.custom_psram_bss*)
-        . = ALIGN(4);
-    } > ram_psram
-
-    .bss (NOLOAD) :
-    {
-        . = ALIGN(4);
-        __bss_start__ = .;
-        
-        *(.bss*)
-        *(.sbss*)
-        *(.noinit_data*)
-        *(COMMON)
- 
-        . = ALIGN(4);
-        __bss_end__ = .;
-    } > ram_memory
-
-    .stack_dummy (NOLOAD):
-    {
-	PROVIDE ( _sp_base = . );
-        . = ALIGN(64);
-        __stack_protect_start = .;
-        . = . + 256;
-        __stack_protect_end = .;
-        . = . + StackSize;
-        . = ALIGN(64);
-	PROVIDE( _sp_main = . );
-    } > ram_memory
-
-    .heap (NOLOAD):
-    {
-        . = ALIGN(4);
-        __HeapBase = .;
-        _heap_start = .;
-        
-        KEEP(*(.heap*))
-        
-        . = ALIGN(4);
-        __HeapLimit = .;
-        _heap_end = .;
-    } > ram_memory
-
-    __StackTop = ADDR(.stack_dummy) + SIZEOF(.stack_dummy);
-    PROVIDE( __freertos_irq_stack_top = __StackTop);
-    __StackLimit = ADDR(.stack_dummy);
-
-    __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory);
-    _heap_size = __HeapLimit - _heap_start;
-
-    PROVIDE( __itcm_load_addr = LOADADDR(.itcm_region));
-    PROVIDE( __dtcm_load_addr = LOADADDR(.dtcm_region));
-    PROVIDE( __system_ram_load_addr = LOADADDR(.system_ram_data_region));
-    PROVIDE( __psram_ram_load_addr = LOADADDR(.psram_ram_data_region));
-    PROVIDE( __ram_load_addr = LOADADDR(.data));
-
-    /*SYMOBOL used in code*/
-    PROVIDE( _ld_bl_static_cli_cmds_start = _bl_static_cli_cmds_start );
-    PROVIDE( _ld_bl_static_cli_cmds_end   = _bl_static_cli_cmds_end );
-
-    /*BOOT2 sections*/
-    PROVIDE ( __boot2_pt_addr_src = BOOT2_PT_ADDR );
-    PROVIDE ( __boot2_flashCfg_src = BOOT2_FLASHCFG_ADDR );
-    
-    PROVIDE( _ld_ram_size0 = LENGTH(flash) );
-    PROVIDE( _ld_ram_addr0 = ORIGIN(flash) );
-    PROVIDE( _ld_ram_size1 = LENGTH(ram_psram) );
-    PROVIDE( _ld_ram_addr1 = ORIGIN(ram_psram) );
-    PROVIDE( _ld_ram_size2 = LENGTH(ram_wifi) );
-    PROVIDE( _ld_ram_addr2 = ORIGIN(ram_wifi) );
-    PROVIDE( _ld_ram_size3 = LENGTH(ram_memory) );
-    PROVIDE( _ld_ram_addr3 = ORIGIN(ram_memory) );
-    PROVIDE( _ld_ram_size4 = LENGTH(xram_memory) );
-    PROVIDE( _ld_ram_addr4 = ORIGIN(xram_memory) );
- 
-    /* blog */
-    PROVIDE( _ld_bl_static_blogcomponent_code_start = _bl_static_blogcomponent_code_start );
-    PROVIDE( _ld_bl_static_blogcomponent_code_end   = _bl_static_blogcomponent_code_end );
-    PROVIDE( _ld_bl_static_blogfile_code_start = _bl_static_blogfile_code_start );
-    PROVIDE( _ld_bl_static_blogfile_code_end   = _bl_static_blogfile_code_end );
-    PROVIDE( _ld_bl_static_blogpri_code_start = _bl_static_blogpri_code_start );
-    PROVIDE( _ld_bl_static_blogpri_code_end   = _bl_static_blogpri_code_end );
-
-    PROVIDE( _ld_bl_static_cfg_entry_start = _bl_static_fw_cfg_entry_start );
-    PROVIDE( _ld_bl_static_cfg_entry_end   = _bl_static_fw_cfg_entry_end );
-}
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_flash_rom.ld b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_flash_rom.ld
deleted file mode 100644
index d2001b4ffd..0000000000
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_flash_rom.ld
+++ /dev/null
@@ -1,252 +0,0 @@
-/****************************************************************************************
-* @file map.txt
-*
-* @brief This file is the map file (gnuarm or armgcc).
-*
-* Copyright (C) BouffaloLab 2018
-*
-****************************************************************************************
-*/
-
-/* configure the CPU type */
-OUTPUT_ARCH( "riscv" )
-/* link with the standard c library */
-INPUT(-lc)
-/* link with the standard GCC library */
-INPUT(-lgcc)
-/* configure the entry point */
-ENTRY(risc_e906_start)
-
-StackSize = 0x0400; /*  1KB */
-
-MEMORY
-{
-    flash    (rxai!w) : ORIGIN = 0xD8000000, LENGTH = 4M
-    itcm_memory (rx)  : ORIGIN = 0xC2024000, LENGTH = 48K
-    dtcm_memory (rx)  : ORIGIN = 0x62020000, LENGTH = 16K
-    ram_memory  (!rx) : ORIGIN = 0x22010000, LENGTH = 64K
-    ram_wifi    (!rx) : ORIGIN = 0x22030000, LENGTH = 160K
-}
-
-SECTIONS
-{
-    PROVIDE(__metal_chicken_bit = 0);
-    
-    .text :
-    {
-        . = ALIGN(4);
-    
-        KEEP (*(SORT_NONE(_start)))
-        KEEP (*(SORT_NONE(risc_e906_start)))
-        
-        *(.text)
-        *(.text.*)
-
-        . = ALIGN(4);
-    } > flash
-
-    .rodata :
-    {
-        . = ALIGN(4);
-        
-        *(.rodata)
-        *(.rodata.*)
-    
-        *(.srodata)
-        *(.srodata.*)
-
-        /* static cli cmds */
-        . = ALIGN(4);
-        _bl_static_cli_cmds_start = .;
-        KEEP(*(.static_cli_cmds))
-        *(.static_cli_cmds)
-        _bl_static_cli_cmds_end = .;    
-        
-        /* static blog code1 */
-        . = ALIGN(4);
-        _bl_static_blogcomponent_code_start = .;
-        KEEP(SORT(*)(.static_blogcomponent_code*))
-        *(.static_blogcomponent_code*)
-        _bl_static_blogcomponent_code_end = .;
-    
-        /* static blog code2 */
-        . = ALIGN(4);
-        _bl_static_blogfile_code_start = .;
-        KEEP(SORT(*)(.static_blogfile_code*))
-        *(.static_blogfile_code*)
-        _bl_static_blogfile_code_end = .;
-    
-        /* static blog code3 */
-        . = ALIGN(4);
-        _bl_static_blogpri_code_start = .;
-        KEEP(SORT(*)(.static_blogpri_code*))
-        *(.static_blogpri_code*)
-        _bl_static_blogpri_code_end = .;
-    
-        /* static fw attribute entry */
-        . = ALIGN(4);
-        _bl_static_fw_cfg_entry_start = .;
-        KEEP(*(.wifi.cfg.entry))
-        _bl_static_fw_cfg_entry_end = .;
-        . = ALIGN(4);
-
-    } > flash
-
-    .itcm_region :
-    {
-        . = ALIGN(4);
-        __tcm_code_start__ = .;
-
-        *(.tcm_code)
-        *(.tcm_code.*)
-        *(.tcm_const)
-        *(.sclock_rlt_code)
-        *(.sclock_rlt_const)
-        
-        . = ALIGN(4);
-        __tcm_code_end__ = .;
-    } > itcm_memory AT > flash
-
-    .dtcm_region : 
-    {
-        . = ALIGN(4);
-        __tcm_data_start__ = .;
-        
-        *(.tcm_data)
-        
-        . = ALIGN(4);
-        __tcm_data_end__ = .;
-    } > dtcm_memory AT > flash
-
-    .stack_dummy (NOLOAD):
-    {
-        . = ALIGN(4);
-        . = . + StackSize;
-        . = ALIGN(4);
-    } > dtcm_memory
-
-    .system_ram_data_region : 
-    {
-        . = ALIGN(4);
-        __system_ram_data_start__ = .;
- 
-        *(.system_ram)
-        
-        . = ALIGN(4);
-        __system_ram_data_end__ = .;
-    } > ram_memory AT > flash
-
-    .data : 
-    {
-        . = ALIGN(4);
-        __ram_data_start__ = .;
-
-        PROVIDE( __global_pointer$ = . + 0x800 );
-        
-        *(.data)
-        *(.data.*)
-        *(.sdata)
-        *(.sdata.*)
-        *(.sdata2)
-        *(.sdata2.*)
-        
-        _bt_gatt_service_static_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_gatt_service_static.static.*")))
-        _bt_gatt_service_static_list_end = .;
-        _bt_l2cap_fixed_chan_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_l2cap_fixed_chan.static.*")))
-        _bt_l2cap_fixed_chan_list_end = .;
-        _bt_l2cap_br_fixed_chan_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_l2cap_br_fixed_chan.static.*")))
-        _bt_l2cap_br_fixed_chan_list_end = .;
-
-        . = ALIGN(4);
-        __ram_data_end__ = .;
-    } > ram_memory AT > flash
-    
-    .wifibss  (NOLOAD) :
-    {
-        PROVIDE( __wifi_bss_start = ADDR(.wifibss) );
-        PROVIDE( __wifi_bss_end = ADDR(.wifibss) + SIZEOF(.wifibss) );
-        *ipc_shared.o(COMMON)
-        *sdu_shared.o(COMMON)
-        *hal_desc.o(COMMON)
-        *txl_buffer_shared.o(COMMON)
-        *txl_frame_shared.o(COMMON)
-        *scan_shared.o(COMMON)
-        *scanu_shared.o(COMMON)
-        *mfp_bip.o(COMMON)
-        *me_mic.o(COMMON)
-        *bl_sta_mgmt_others.o(COMMON)
-        *bl_pmk_mgmt.o(COMMON)
-        *bl_pmk_mgmt_internal.o(COMMON)
-        *libwifi_drv.a:bl_utils.o(COMMON)
-        *libwifi_drv.a:bl_utils.o(.bss*)
-        *(.wifi_ram*)
-        . = ALIGN(16);
-    } > ram_wifi
-
-    PROVIDE( _heap_wifi_start = . );
-    PROVIDE( _heap_wifi_size = ORIGIN(ram_wifi) + LENGTH(ram_wifi) - _heap_wifi_start );
-
-    .bss (NOLOAD) :
-    {
-        . = ALIGN(4);
-        __bss_start__ = .;
-        
-        *(.bss*)
-        *(.sbss*)
-        *(.noinit_data*)
-        *(COMMON)
- 
-        . = ALIGN(4);
-        __bss_end__ = .;
-    } > ram_memory 
-
-    .heap (NOLOAD):
-    {
-        . = ALIGN(4);
-        __HeapBase = .;
-        _heap_start = .;
-        
-        KEEP(*(.heap*))
-        
-        . = ALIGN(4);
-        __HeapLimit = .;
-        _heap_end = .;
-    } > ram_memory 
-
-    __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);
-    PROVIDE( __freertos_irq_stack_top = __StackTop);
-    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
-
-    __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory);
-    _heap_size = __HeapLimit - _heap_start;
-
-    PROVIDE( __itcm_load_addr = LOADADDR(.itcm_region));
-    PROVIDE( __dtcm_load_addr = LOADADDR(.dtcm_region));
-    PROVIDE( __system_ram_load_addr = LOADADDR(.system_ram_data_region));
-    PROVIDE( __ram_load_addr = LOADADDR(.data));
-
-    /*SYMOBOL used in code*/
-    PROVIDE( _ld_bl_static_cli_cmds_start = _bl_static_cli_cmds_start );
-    PROVIDE( _ld_bl_static_cli_cmds_end   = _bl_static_cli_cmds_end );
-    
-    PROVIDE( _ld_ram_size0 = LENGTH(flash) );
-    PROVIDE( _ld_ram_addr0 = ORIGIN(flash) );
-    PROVIDE( _ld_ram_size1 = LENGTH(ram_memory) );
-    PROVIDE( _ld_ram_addr1 = ORIGIN(ram_memory) );
-    PROVIDE( _ld_ram_size2 = LENGTH(ram_wifi) );
-    PROVIDE( _ld_ram_addr2 = ORIGIN(ram_wifi) );
- 
-    /* blog */
-    PROVIDE( _ld_bl_static_blogcomponent_code_start = _bl_static_blogcomponent_code_start );
-    PROVIDE( _ld_bl_static_blogcomponent_code_end   = _bl_static_blogcomponent_code_end );
-    PROVIDE( _ld_bl_static_blogfile_code_start = _bl_static_blogfile_code_start );
-    PROVIDE( _ld_bl_static_blogfile_code_end   = _bl_static_blogfile_code_end );
-    PROVIDE( _ld_bl_static_blogpri_code_start = _bl_static_blogpri_code_start );
-    PROVIDE( _ld_bl_static_blogpri_code_end   = _bl_static_blogpri_code_end );
-
-    PROVIDE( _ld_bl_static_cfg_entry_start = _bl_static_fw_cfg_entry_start );
-    PROVIDE( _ld_bl_static_cfg_entry_end   = _bl_static_fw_cfg_entry_end );
-}
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_ram.ld b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_ram.ld
deleted file mode 100644
index fe07f7ebe9..0000000000
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_ram.ld
+++ /dev/null
@@ -1,277 +0,0 @@
-/****************************************************************************************
-* @file map.txt
-*
-* @brief This file is the map file (gnuarm or armgcc).
-*
-* Copyright (C) BouffaloLab 2018
-*
-****************************************************************************************
-*/
-
-/* configure the CPU type */
-OUTPUT_ARCH( "riscv" )
-/* link with the standard c library */
-INPUT(-lc)
-/* link with the standard GCC library */
-INPUT(-lgcc)
-/* configure the entry point */
-ENTRY(risc_e906_start)
-
-StackSize = 0x0400; /*  1KB */
-
-MEMORY
-{
-    code_memory (rx)  : ORIGIN = 0x22030000, LENGTH = 128K
-    itcm_memory (rx)  : ORIGIN = 0x22028000, LENGTH = 16K
-    dtcm_memory (rx)  : ORIGIN = 0x2202c000, LENGTH = 16K
-    ram_memory  (!rx) : ORIGIN = 0x22020000, LENGTH = 32K
-    ram_wifi    (!rx) : ORIGIN = 0x22050000, LENGTH = 32K
-}
-
-SECTIONS
-{
-    PROVIDE(__metal_chicken_bit = 0);
-    
-    .text :
-    {
-        . = ALIGN(4);
-        __text_code_start__ = .;
-        
-        KEEP (*(SORT_NONE(_start)))
-        KEEP (*(SORT_NONE(risc_e906_start)))
-        
-        *(.text)
-        *(.text.*)
-        
-        *(.rodata)
-        *(.rodata.*)
-    
-        *(.srodata)
-        *(.srodata.*)
-        
-        *(.tcm_code)
-        *(.tcm_const)
-        *(.sclock_rlt_code)
-        *(.sclock_rlt_const)
-
-        /* static cli cmds */
-        . = ALIGN(4);
-        _bl_static_cli_cmds_start = .;
-        KEEP(*(.static_cli_cmds))
-        *(.static_cli_cmds)
-        _bl_static_cli_cmds_end = .;    
-        
-        /* static blog code1 */
-        . = ALIGN(4);
-        _bl_static_blogcomponent_code_start = .;
-        KEEP(SORT(*)(.static_blogcomponent_code*))
-        *(.static_blogcomponent_code*)
-        _bl_static_blogcomponent_code_end = .;
-    
-        /* static blog code2 */
-        . = ALIGN(4);
-        _bl_static_blogfile_code_start = .;
-        KEEP(SORT(*)(.static_blogfile_code*))
-        *(.static_blogfile_code*)
-        _bl_static_blogfile_code_end = .;
-    
-        /* static blog code3 */
-        . = ALIGN(4);
-        _bl_static_blogpri_code_start = .;
-        KEEP(SORT(*)(.static_blogpri_code*))
-        *(.static_blogpri_code*)
-        _bl_static_blogpri_code_end = .;
-    
-        /* static fw attribute entry */
-        . = ALIGN(4);
-        _bl_static_fw_cfg_entry_start = .;
-        KEEP(*(.wifi.cfg.entry))
-        _bl_static_fw_cfg_entry_end = .;
-        . = ALIGN(4);
-
-        __text_code_end__ = .;
-    } > code_memory
-
-    .wifibss  (NOLOAD) :
-    {
-        PROVIDE( __wifi_bss_start = ADDR(.wifibss) );
-        PROVIDE( __wifi_bss_end = ADDR(.wifibss) + SIZEOF(.wifibss) );
-        *ipc_shared.o(COMMON)
-        *sdu_shared.o(COMMON)
-        *hal_desc.o(COMMON)
-        *txl_buffer_shared.o(COMMON)
-        *txl_frame_shared.o(COMMON)
-        *scan_shared.o(COMMON)
-        *scanu_shared.o(COMMON)
-        *mfp_bip.o(COMMON)
-        *me_mic.o(COMMON)
-        *bl_sta_mgmt_others.o(COMMON)
-        *bl_pmk_mgmt.o(COMMON)
-        *bl_pmk_mgmt_internal.o(COMMON)
-        *libwifi_drv.a:bl_utils.o(COMMON)
-        *libwifi_drv.a:bl_utils.o(.bss*)
-        *(.wifi_ram*)
-        . = ALIGN(16);
-    } > ram_wifi
-
-    PROVIDE( _heap_wifi_start = . );
-    PROVIDE( _heap_wifi_size = ORIGIN(ram_wifi) + LENGTH(ram_wifi) - _heap_wifi_start );
-
- 
-
-    /*SYMOBOL used in code*/
-    PROVIDE( _ld_bl_static_cli_cmds_start = _bl_static_cli_cmds_start );
-    PROVIDE( _ld_bl_static_cli_cmds_end   = _bl_static_cli_cmds_end );
-
-    . = ALIGN(4);
-    __itcm_load_addr = .;
-    
-    .itcm_region : AT (__itcm_load_addr)
-    {
-        . = ALIGN(4);
-        __tcm_code_start__ = .;
-        
-        . = ALIGN(4);
-        __tcm_code_end__ = .;
-    } > itcm_memory
-    
-    __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region);
-    
-    .dtcm_region : AT (__dtcm_load_addr)
-    {
-        . = ALIGN(4);
-        __tcm_data_start__ = .;
-        
-        *(.tcm_data)
-        /* *finger_print.o(.data*) */
-        
-        . = ALIGN(4);
-        __tcm_data_end__ = .;
-    } > dtcm_memory
-    
-    /*************************************************************************/
-    /* .stack_dummy section doesn't contains any symbols. It is only
-     * used for linker to calculate size of stack sections, and assign
-     * values to stack symbols later */
-    .stack_dummy (NOLOAD):
-    {
-        . = ALIGN(0x4);
-        . = . + StackSize;
-        . = ALIGN(0x4);
-    } > dtcm_memory
-    
-    /* Set stack top to end of RAM, and stack limit move down by
-     * size of stack_dummy section */
-    __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);
-    PROVIDE( __freertos_irq_stack_top = __StackTop);
-    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
-    
-    /* Check if data + heap + stack exceeds RAM limit */
-    ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack")
-    /*************************************************************************/
-    
-    __system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
-    
-    .system_ram_data_region : AT (__system_ram_load_addr)
-    {
-        . = ALIGN(4);
-        __system_ram_data_start__ = .;
-        
-        *(.system_ram)
-        
-        . = ALIGN(4);
-        __system_ram_data_end__ = .;
-    } > ram_memory
-    
-    __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region);
-    
-    /* Data section */
-    RAM_DATA : AT (__ram_load_addr)
-    {
-        . = ALIGN(4);
-        __ram_data_start__ = .;
-        
-        PROVIDE( __global_pointer$ = . + 0x800 );
-        
-        *(.data)
-        *(.data.*)
-        *(.sdata)
-        *(.sdata.*)
-        *(.sdata2)
-        *(.sdata2.*)
-        
-        _bt_gatt_service_static_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_gatt_service_static.static.*")))
-        _bt_gatt_service_static_list_end = .;
-        _bt_l2cap_fixed_chan_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_l2cap_fixed_chan.static.*")))
-        _bt_l2cap_fixed_chan_list_end = .;
-        _bt_l2cap_br_fixed_chan_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_l2cap_br_fixed_chan.static.*")))
-        _bt_l2cap_br_fixed_chan_list_end = .;
-
-        . = ALIGN(4);
-        __ram_data_end__ = .;
-    } > ram_memory
-    
-    
-    .noinit_data (NOLOAD) :
-    {
-        . = ALIGN(4);
-        __noinit_data_start__ = .;
-        
-        *(.noinit_data*)
-        
-        . = ALIGN(4);
-        __noinit_data_end__ = .;
-    } > ram_memory
-    
-    .bss (NOLOAD) :
-    {
-        . = ALIGN(4);
-        __bss_start__ = .;
-        
-        *(.bss*)
-        *(.sbss*)
-        *(COMMON)
- 
-        . = ALIGN(4);
-        __bss_end__ = .;
-    } > ram_memory
-
-    .heap (NOLOAD):
-    {
-        . = ALIGN(4);
-        __HeapBase = .;
-        _heap_start = .;
-        
-        /*__end__ = .;*/
-        /*end = __end__;*/
-        KEEP(*(.heap*))
-        
-        . = ALIGN(4);
-        __HeapLimit = .;
-    } > ram_memory
-    __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory);
-    _heap_size = __HeapLimit - __HeapBase;
-}
-
-PROVIDE( _ld_ram_size0 = LENGTH(ram_memory) );
-PROVIDE( _ld_ram_addr0 = ORIGIN(ram_memory) );
-PROVIDE( _ld_ram_size1 = 0);
-PROVIDE( _ld_ram_addr1 = 0);
-PROVIDE( _ld_ram_size2 = LENGTH(ram_wifi) );
-PROVIDE( _ld_ram_addr2 = ORIGIN(ram_wifi) );
-
-/* blog */
-PROVIDE( _ld_bl_static_blogcomponent_code_start = _bl_static_blogcomponent_code_start );
-PROVIDE( _ld_bl_static_blogcomponent_code_end   = _bl_static_blogcomponent_code_end );
-PROVIDE( _ld_bl_static_blogfile_code_start = _bl_static_blogfile_code_start );
-PROVIDE( _ld_bl_static_blogfile_code_end   = _bl_static_blogfile_code_end );
-PROVIDE( _ld_bl_static_blogpri_code_start = _bl_static_blogpri_code_start );
-PROVIDE( _ld_bl_static_blogpri_code_end   = _bl_static_blogpri_code_end );
-
-
-PROVIDE( _ld_bl_static_cfg_entry_start = _bl_static_fw_cfg_entry_start );
-PROVIDE( _ld_bl_static_cfg_entry_end   = _bl_static_fw_cfg_entry_end );
-
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_ram_phyrf.ld b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_ram_phyrf.ld
deleted file mode 100644
index 23ff22baef..0000000000
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_ram_phyrf.ld
+++ /dev/null
@@ -1,288 +0,0 @@
-/****************************************************************************************
-* @file map.txt
-*
-* @brief This file is the map file (gnuarm or armgcc).
-*
-* Copyright (C) BouffaloLab 2018
-*
-****************************************************************************************
-*/
-
-/* configure the CPU type */
-OUTPUT_ARCH( "riscv" )
-/* link with the standard c library */
-INPUT(-lc)
-/* link with the standard GCC library */
-INPUT(-lgcc)
-/* configure the entry point */
-ENTRY(risc_e906_start)
-
-StackSize = 0x0400; /*  1KB */
-
-MEMORY
-{
-    code_memory       (rx)  : ORIGIN = 0x22030000, LENGTH = 128K
-    ram_wifi          (!rx) : ORIGIN = 0x22050000, LENGTH = 32K
-    ram_memory        (!rx) : ORIGIN = 0x22020000, LENGTH = 28K
-    itcm_memory       (rx)  : ORIGIN = 0x22027000, LENGTH = 2K
-    dtcm_memory       (rx)  : ORIGIN = 0x22027800, LENGTH = 2K
-    test_ocram        (!rx) : ORIGIN = 0x22028000, LENGTH = 32K
-}
-
-SECTIONS
-{
-    PROVIDE(__metal_chicken_bit = 0);
-    
-    .text :
-    {
-        . = ALIGN(4);
-        __text_code_start__ = .;
-        
-        KEEP (*(SORT_NONE(_start)))
-        KEEP (*(SORT_NONE(risc_e906_start)))
-        
-        *(.text)
-        *(.text.*)
-        
-        *(.rodata)
-        *(.rodata.*)
-    
-        *(.srodata)
-        *(.srodata.*)
-        
-        *(.tcm_code)
-        *(.tcm_const)
-        *(.sclock_rlt_code)
-        *(.sclock_rlt_const)
-
-        /* static cli cmds */
-        . = ALIGN(4);
-        _bl_static_cli_cmds_start = .;
-        KEEP(*(.static_cli_cmds))
-        *(.static_cli_cmds)
-        _bl_static_cli_cmds_end = .;    
-        
-        /* static blog code1 */
-        . = ALIGN(4);
-        _bl_static_blogcomponent_code_start = .;
-        KEEP(SORT(*)(.static_blogcomponent_code*))
-        *(.static_blogcomponent_code*)
-        _bl_static_blogcomponent_code_end = .;
-    
-        /* static blog code2 */
-        . = ALIGN(4);
-        _bl_static_blogfile_code_start = .;
-        KEEP(SORT(*)(.static_blogfile_code*))
-        *(.static_blogfile_code*)
-        _bl_static_blogfile_code_end = .;
-    
-        /* static blog code3 */
-        . = ALIGN(4);
-        _bl_static_blogpri_code_start = .;
-        KEEP(SORT(*)(.static_blogpri_code*))
-        *(.static_blogpri_code*)
-        _bl_static_blogpri_code_end = .;
-    
-        /* static fw attribute entry */
-        . = ALIGN(4);
-        _bl_static_fw_cfg_entry_start = .;
-        KEEP(*(.wifi.cfg.entry))
-        _bl_static_fw_cfg_entry_end = .;
-        . = ALIGN(4);
-
-        __text_code_end__ = .;
-    } > code_memory
-
-    .wifibss  (NOLOAD) :
-    {
-        PROVIDE( __wifi_bss_start = ADDR(.wifibss) );
-        PROVIDE( __wifi_bss_end = ADDR(.wifibss) + SIZEOF(.wifibss) );
-        *ipc_shared.o(COMMON)
-        *sdu_shared.o(COMMON)
-        *hal_desc.o(COMMON)
-        *txl_buffer_shared.o(COMMON)
-        *txl_frame_shared.o(COMMON)
-        *scan_shared.o(COMMON)
-        *scanu_shared.o(COMMON)
-        *mfp_bip.o(COMMON)
-        *me_mic.o(COMMON)
-        *bl_sta_mgmt_others.o(COMMON)
-        *bl_pmk_mgmt.o(COMMON)
-        *bl_pmk_mgmt_internal.o(COMMON)
-        *libwifi_drv.a:bl_utils.o(COMMON)
-        *libwifi_drv.a:bl_utils.o(.bss*)
-        *(.wifi_ram*)
-        . = ALIGN(16);
-    } > ram_wifi
-
-    PROVIDE( _heap_wifi_start = . );
-    PROVIDE( _heap_wifi_size = ORIGIN(ram_wifi) + LENGTH(ram_wifi) - _heap_wifi_start );
-
-    /*SYMOBOL used in code*/
-    PROVIDE( _ld_bl_static_cli_cmds_start = _bl_static_cli_cmds_start );
-    PROVIDE( _ld_bl_static_cli_cmds_end   = _bl_static_cli_cmds_end );
-
-    . = ALIGN(4);
-    __itcm_load_addr = .;
-    
-    .itcm_region : AT (__itcm_load_addr)
-    {
-        . = ALIGN(4);
-        __tcm_code_start__ = .;
-        
-        . = ALIGN(4);
-        __tcm_code_end__ = .;
-    } > itcm_memory
-    
-    __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region);
-    
-    .dtcm_region : AT (__dtcm_load_addr)
-    {
-        . = ALIGN(4);
-        __tcm_data_start__ = .;
-        
-        *(.tcm_data)
-        /* *finger_print.o(.data*) */
-        
-        . = ALIGN(4);
-        __tcm_data_end__ = .;
-    } > dtcm_memory
-    
-    /*************************************************************************/
-    /* .stack_dummy section doesn't contains any symbols. It is only
-     * used for linker to calculate size of stack sections, and assign
-     * values to stack symbols later */
-    .stack_dummy (NOLOAD):
-    {
-        . = ALIGN(0x4);
-        . = . + StackSize;
-        . = ALIGN(0x4);
-    } > dtcm_memory
-    
-    /* Set stack top to end of RAM, and stack limit move down by
-     * size of stack_dummy section */
-    __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);
-    PROVIDE( __freertos_irq_stack_top = __StackTop);
-    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
-    
-    /* Check if data + heap + stack exceeds RAM limit */
-    ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack")
-    /*************************************************************************/
-    
-    __system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
-    
-    .system_ram_data_region : AT (__system_ram_load_addr)
-    {
-        . = ALIGN(4);
-        __system_ram_data_start__ = .;
-        
-        *(.system_ram)
-        
-        . = ALIGN(4);
-        __system_ram_data_end__ = .;
-    } > ram_memory
-    
-    __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region);
-    
-    /* Data section */
-    RAM_DATA : AT (__ram_load_addr)
-    {
-        . = ALIGN(4);
-        __ram_data_start__ = .;
-        
-        PROVIDE( __global_pointer$ = . + 0x800 );
-        
-        *(.data)
-        *(.data.*)
-        *(.sdata)
-        *(.sdata.*)
-        *(.sdata2)
-        *(.sdata2.*)
-        
-        _bt_gatt_service_static_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_gatt_service_static.static.*")))
-        _bt_gatt_service_static_list_end = .;
-        _bt_l2cap_fixed_chan_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_l2cap_fixed_chan.static.*")))
-        _bt_l2cap_fixed_chan_list_end = .;
-        _bt_l2cap_br_fixed_chan_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_l2cap_br_fixed_chan.static.*")))
-        _bt_l2cap_br_fixed_chan_list_end = .;
-
-        . = ALIGN(4);
-        __ram_data_end__ = .;
-    } > ram_memory
-    
-    .noinit_data (NOLOAD) :
-    {
-        . = ALIGN(4);
-        __noinit_data_start__ = .;
-        
-        *(.noinit_data*)
-        
-        . = ALIGN(4);
-        __noinit_data_end__ = .;
-    } > ram_memory
-    
-    .bss (NOLOAD) :
-    {
-        . = ALIGN(4);
-        __bss_start__ = .;
-        
-        *(.bss*)
-        *(.sbss*)
-        *(COMMON)
- 
-        . = ALIGN(4);
-        __bss_end__ = .;
-    } > ram_memory
-
-    .heap (NOLOAD):
-    {
-        . = ALIGN(4);
-        __HeapBase = .;
-        _heap_start = .;
-        
-        /*__end__ = .;*/
-        /*end = __end__;*/
-        KEEP(*(.heap*))
-        
-        . = ALIGN(4);
-        __HeapLimit = .;
-    } > ram_memory
-    __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory);
-    _heap_size = __HeapLimit - __HeapBase;
-
-    /* keep my variable even if not referenced */
-    /* .testmem_at_ocram (NOLOAD) : 
-    {
-        PROVIDE( __testmem_at_ocram_start_addr = ADDR(.testmem_at_ocram) );
-        PROVIDE( __testmem_at_wram_start_addr = ADDR(.testmem_at_ocram) + SIZEOF(.testmem_at_ocram) );
-        KEEP(*(.testmem_at_ocram))
-    } > ram_test */
-
-    /* __testmem_at_ocram_start_addr = ORIGIN(ram_test);
-    __testmem_at_wram_start_addr = ORIGIN(wifi_ram); */
-
-    __testmem_at_ocram_start_addr = ORIGIN(test_ocram);
-    __testmem_at_wram_start_addr = ORIGIN(ram_wifi);
-}
-
-PROVIDE( _ld_ram_size0 = LENGTH(ram_memory) );
-PROVIDE( _ld_ram_addr0 = ORIGIN(ram_memory) );
-PROVIDE( _ld_ram_size1 = 0);
-PROVIDE( _ld_ram_addr1 = 0);
-PROVIDE( _ld_ram_size2 = LENGTH(ram_wifi) );
-PROVIDE( _ld_ram_addr2 = ORIGIN(ram_wifi) );
-
-/* blog */
-PROVIDE( _ld_bl_static_blogcomponent_code_start = _bl_static_blogcomponent_code_start );
-PROVIDE( _ld_bl_static_blogcomponent_code_end   = _bl_static_blogcomponent_code_end );
-PROVIDE( _ld_bl_static_blogfile_code_start = _bl_static_blogfile_code_start );
-PROVIDE( _ld_bl_static_blogfile_code_end   = _bl_static_blogfile_code_end );
-PROVIDE( _ld_bl_static_blogpri_code_start = _bl_static_blogpri_code_start );
-PROVIDE( _ld_bl_static_blogpri_code_end   = _bl_static_blogpri_code_end );
-
-
-PROVIDE( _ld_bl_static_cfg_entry_start = _bl_static_fw_cfg_entry_start );
-PROVIDE( _ld_bl_static_cfg_entry_end   = _bl_static_fw_cfg_entry_end );
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/boot/gcc/start_load.c b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/boot/gcc/start_load.c
deleted file mode 100644
index 705babcd15..0000000000
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/boot/gcc/start_load.c
+++ /dev/null
@@ -1,109 +0,0 @@
-#include 
-#include 
-#define __STARTUP_CLEAR_BSS             1
-
-/*----------------------------------------------------------------------------
-  Linker generated Symbols
- *----------------------------------------------------------------------------*/
-extern uint32_t __itcm_load_addr;
-extern uint32_t __dtcm_load_addr;
-extern uint32_t __system_ram_load_addr;
-extern uint32_t __psram_ram_load_addr;
-extern uint32_t __ram_load_addr;
-
-extern uint32_t __text_code_start__;
-extern uint32_t __text_code_end__;
-extern uint32_t __tcm_code_start__;
-extern uint32_t __tcm_code_end__;
-extern uint32_t __tcm_data_start__;
-extern uint32_t __tcm_data_end__;
-extern uint32_t __system_ram_data_start__;
-extern uint32_t __system_ram_data_end__;
-extern uint32_t __psram_ram_data_start__;
-extern uint32_t __psram_ram_data_end__;
-extern uint32_t __ram_data_start__;
-extern uint32_t __ram_data_end__;
-extern uint32_t __wifi_bss_start;
-extern uint32_t __wifi_bss_end;
-extern uint32_t __bss_start__;
-extern uint32_t __bss_end__;
-extern uint32_t __ocram_bss_start__;
-extern uint32_t __ocram_bss_end__;
-extern uint32_t __noinit_data_start__;
-extern uint32_t __noinit_data_end__;
-
-extern uint32_t __StackTop;
-extern uint32_t __StackLimit;
-extern uint32_t __HeapBase;
-extern uint32_t __HeapLimit;
-
-//extern uint32_t __copy_table_start__;
-//extern uint32_t __copy_table_end__;
-//extern uint32_t __zero_table_start__;
-//extern uint32_t __zero_table_end__;
-
-
-void start_load(void) {
-    uint32_t *pSrc, *pDest;
-    /*boot2 dcache is enable need disable*/
-    csi_dcache_disable();
-
-    /* Copy ITCM code */
-    pSrc  = &__itcm_load_addr;
-    pDest = &__tcm_code_start__;
-    for ( ; pDest < &__tcm_code_end__ ; ) {
-        *pDest++ = *pSrc++;
-    }
-
-    /* Copy DTCM code */
-    pSrc  = &__dtcm_load_addr;
-    pDest = &__tcm_data_start__;
-    for( ; pDest < &__tcm_data_end__; ){
-        *pDest++ = *pSrc++;
-    }
-
-    /* BF Add system RAM data copy */
-    pSrc  = &__system_ram_load_addr;
-    pDest = &__system_ram_data_start__;
-    for ( ; pDest < &__system_ram_data_end__ ; ) {
-        *pDest++ = *pSrc++;
-    }
-
-    /* BF Add OCARAM data copy */
-    pSrc  = &__ram_load_addr;
-    pDest = &__ram_data_start__;
-    for ( ; pDest < &__ram_data_end__ ; ) {
-        *pDest++ = *pSrc++;
-    }
-
-#ifdef __STARTUP_CLEAR_BSS
-    /*
-     *  The BSS section is specified by following symbols
-     *    __bss_start__: start of the BSS section.
-     *    __bss_end__: end of the BSS section.
-     *
-     *  Both addresses must be aligned to 4 bytes boundary.
-     */
-    pDest = &__bss_start__;
-    for ( ; pDest < &__bss_end__ ; ) {
-        *pDest++ = 0ul;
-    }
-
-    pDest = &__wifi_bss_start;
-    for ( ; pDest < &__wifi_bss_end ; ) {
-        *pDest++ = 0ul;
-    }
-
-    pDest = &__ocram_bss_start__;
-    for ( ; pDest < &__ocram_bss_end__ ; ) {
-        *pDest++ = 0ul;
-    }
-#endif
-
-    /* BF Add PSRAM RAM data copy */
-    pSrc  = &__psram_ram_load_addr;
-    pDest = &__psram_ram_data_start__;
-    for ( ; pDest < &__psram_ram_data_end__ ; ) {
-        *pDest++ = *pSrc++;
-    }
-}
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/boot/gcc/startup.S b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/boot/gcc/startup.S
deleted file mode 100644
index cb74576c0e..0000000000
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/boot/gcc/startup.S
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * Copyright (C) 2016-2020 Bouffalo Lab
- */
-
-_start:
-    .section      .text.startup
-    .align  2
-    .globl  risc_e906_start
-    .type   risc_e906_start, %function
-risc_e906_start:
-.option push
-.option norelax
-    la      gp, __global_pointer$
-.option pop
-    la      a0, IRQ_Handler
-    ori     a0, a0, 3
-    csrw    mtvec, a0 
-#1:
-#    j       1b
-
-    la      a0, __Vectors
-    csrw    mtvt, a0
-
-    .weak __StackTop
-    la      sp, __StackTop
-    csrw    mscratch, sp
-
-#ifndef RUN_IN_RAM
-	/* Load boot2 partition address */
-	la a0, __boot2_pt_addr_src
-	la a1, __boot2_pt_addr_start
-	la a2, __boot2_pt_addr_end
-	bgeu a1, a2, 2f
-1:
-	lw t0, (a0)
-	sw t0, (a1)
-	addi a0, a0, 4
-	addi a1, a1, 4
-	bltu a1, a2, 1b
-2:
-
-
-	/* Load boot2 flashCfg address */
-	la a0, hal_boot2_get_flash_addr
-	jalr a0
-	la a1, __boot2_flashCfg_start
-	la a2, __boot2_flashCfg_end
-	bgeu a1, a2, 2f
-1:
-	lw t0, (a0)
-	sw t0, (a1)
-	addi a0, a0, 4
-	addi a1, a1, 4
-	bltu a1, a2, 1b
-2:
-#endif
-
-    /* Load data section removed */
-    
-    /* start load code to itcm like. */
-    la a0,  start_load
-    jalr    a0
- 
-    /* Clear bss section removed */
-
-#ifndef __NO_SYSTEM_INIT
-    la a0,  system_init_bl606p
-    jalr    a0
-#endif
-
-#ifndef __NO_BOARD_INIT
-    la a0,  board_init
-    jalr    a0
-#endif
-   
-	//la a0,  bfl_main
-	la a0,  entry
-    jalr    a0
-
-    .size   risc_e906_start, . - risc_e906_start
-
-__exit:
-    j      __exit
-
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/boot/gcc/vectors.S b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/boot/gcc/vectors.S
deleted file mode 100644
index 94f538fdae..0000000000
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/boot/gcc/vectors.S
+++ /dev/null
@@ -1,327 +0,0 @@
-/*
- * Copyright (C) 2017-2019 Alibaba Group Holding Limited
- */
- /******************************************************************************
- * @file     vectors.S
- * @brief    define default vector handlers. Should use with
- *           GCC for CSKY Embedded Processors
- * @version  V1.0
- * @date     28. Nove 2017
- ******************************************************************************/
-
-/* Enable interrupts when returning from the handler */
-#define MSTATUS_PRV1 0x1880
-
-.section .bss
-    .align  2
-    .globl  g_trapstackalloc
-    .global g_trapstackbase
-    .global g_top_trapstack
-g_trapstackalloc:
-g_trapstackbase:
-    .space 768
-g_top_trapstack:
-
-    .align 2
-    .globl g_trap_sp
-    .type  g_trap_sp, object
-g_trap_sp:
-    .long 0
-    .size g_trap_sp, .-g_trap_sp
-
-irq_nested_level:
-.long 0
-irq_mstatus_fs_flag:
-.long 0
-
-.text
-
-    .align  2
-    .global Default_IRQHandler
-    .weak   Default_IRQHandler
-    .type   Default_IRQHandler, %function
-Default_IRQHandler:
-    ipush
-
-#if 0
-    csrr    t1, mstatus
-    srli    t1, t1, 13
-    andi    t1, t1, 0x3
-    la      t3, irq_mstatus_fs_flag
-    sw      t1, (t3)
-    li      t0, 0x3
-    bne     t1, t0,  .F_RegNotSave1
-
-
-    addi    sp,  sp, -80
-    fsw     ft0, 0(sp)
-    fsw     ft1, 4(sp)
-    fsw     ft2, 8(sp)
-    fsw     ft3, 12(sp)
-    fsw     ft4, 16(sp)
-    fsw     ft5, 20(sp)
-    fsw     ft6, 24(sp)
-    fsw     ft7, 28(sp)
-    fsw     fa0, 32(sp)
-    fsw     fa1, 36(sp)
-    fsw     fa2, 40(sp)
-    fsw     fa3, 44(sp)
-    fsw     fa4, 48(sp)
-    fsw     fa5, 52(sp)
-    fsw     fa6, 56(sp)
-    fsw     fa7, 60(sp)
-    fsw     ft8, 64(sp)
-    fsw     ft9, 68(sp)
-    fsw     ft10,72(sp)
-    fsw     ft11,76(sp)
-.F_RegNotSave1:
-#endif
-    
-    /* disable irq */
-    csrc    mstatus, 8 
-
-    /* Set IRQ stack pointer */
-    la      t0, __freertos_irq_stack_top
-    addi    t1, sp, 0
-    addi    sp, t0, -8
-    /* save t1 to stack */
-    sw      t1, 4(sp)
-
-    csrr    t1, mcause
-    andi    t1, t1, 0x3FF
-    slli    t1, t1, 2
-    la      t0, g_irqvector
-    add     t0, t0, t1
-    lw      t2, (t0)
-    jalr    t2
- 
-    la      t0, __freertos_irq_stack_top
-    lw      sp, t0, -4
-
-    /* enable irq */
-    csrs    mstatus, 8 
-
-    li      t0, MSTATUS_PRV1
-    csrs    mstatus, t0
-
-#if 0
-    la      t0, irq_mstatus_fs_flag
-    lw      t1, (t0)
-    li      t0, 0x3
-    bne     t1, t0,  .F_RegNotLoad
-
-    flw     ft0, 0(sp)
-    flw     ft1, 4(sp)
-    flw     ft2, 8(sp)
-    flw     ft3, 12(sp)
-    flw     ft4, 16(sp)
-    flw     ft5, 20(sp)
-    flw     ft6, 24(sp)
-    flw     ft7, 28(sp)
-    flw     fa0, 32(sp)
-    flw     fa1, 36(sp)
-    flw     fa2, 40(sp)
-    flw     fa3, 44(sp)
-    flw     fa4, 48(sp)
-    flw     fa5, 52(sp)
-    flw     fa6, 56(sp)
-    flw     fa7, 60(sp)
-    flw     ft8, 64(sp)
-    flw     ft9, 68(sp)
-    flw     ft10,72(sp)
-    flw     ft11,76(sp)
-    addi    sp, sp, 80
-
-.F_RegNotLoad:
-#endif
-
-    ipop
-
-
-/******************************************************************************
- * Functions:
- *     void trap(void);
- * default exception handler
- ******************************************************************************/
-    .align  2
-    .global trap
-    .type   trap, %function
-trap:
-    /* Check for interrupt */
-    addi    sp, sp, -4
-    sw      t0, 0x0(sp)
-    csrr    t0, mcause
-
-    blt     t0, x0, .Lirq
-
-    addi    sp, sp, 4
-
-    la      t0, g_trap_sp
-    addi    t0, t0, -132
-    sw      x1, 0(t0)
-    sw      x2, 4(t0)
-    sw      x3, 8(t0)
-    sw      x4, 12(t0)
-    sw      x6, 20(t0)
-    sw      x7, 24(t0)
-    sw      x8, 28(t0)
-    sw      x9, 32(t0)
-    sw      x10, 36(t0)
-    sw      x11, 40(t0)
-    sw      x12, 44(t0)
-    sw      x13, 48(t0)
-    sw      x14, 52(t0)
-    sw      x15, 56(t0)
-    sw      x16, 60(t0)
-    sw      x17, 64(t0)
-    sw      x18, 68(t0)
-    sw      x19, 72(t0)
-    sw      x20, 76(t0)
-    sw      x21, 80(t0)
-    sw      x22, 84(t0)
-    sw      x23, 88(t0)
-    sw      x24, 92(t0)
-    sw      x25, 96(t0)
-    sw      x26, 100(t0)
-    sw      x27, 104(t0)
-    sw      x28, 108(t0)
-    sw      x29, 112(t0)
-    sw      x30, 116(t0)
-    sw      x31, 120(t0)
-    csrr    a0, mepc
-    sw      a0, 124(t0)
-    csrr    a0, mstatus
-    sw      a0, 128(t0)
-
-    mv      a0, t0
-    lw      t0, -4(sp)
-    mv      sp, a0
-    sw      t0, 16(sp)
-
-    jal     trap_c
-
-
-.Lirq:
-    lw      t0, 0x0(sp)
-    addi    sp, sp, 4
-    j       Default_IRQHandler
-
-    .align  6
-    .weak   Default_Handler
-    .global Default_Handler
-    .type   Default_Handler, %function
-Default_Handler:
-    /* Check for nmi */
-    addi    sp, sp, -8
-    sw      t0, 0x0(sp)
-    sw      t1, 0x4(sp)
-    csrr    t0, mcause
-    andi    t0, t0, 0x3FF
-    li      t1, 24
-    beq     t0, t1, .NMI_Handler
-    lw      t0, 0x0(sp)
-    lw      t1, 0x4(sp)
-    addi    sp, sp, 8
-    j      trap
-
-.NMI_Handler:
-    lw      t0, 0x0(sp)
-    lw      t1, 0x4(sp)
-    addi    sp, sp, 8
-
-    addi    sp, sp, -64
-    sw      ra, 0(sp)
-    sw      t0, 4(sp)
-    sw      t1, 8(sp)
-    sw      t2, 12(sp)
-    sw      a0, 16(sp)
-    sw      a1, 20(sp)
-    sw      a2, 24(sp)
-    sw      a3, 28(sp)
-    sw      a4, 32(sp)
-    sw      a5, 36(sp)
-    sw      a6, 40(sp)
-    sw      a7, 44(sp)
-    sw      t3, 48(sp)
-    sw      t4, 52(sp)
-    sw      t5, 56(sp)
-    sw      t6, 60(sp)
-
-    addi    sp,  sp, -80
-    fsw     ft0, 0(sp)
-    fsw     ft1, 4(sp)
-    fsw     ft2, 8(sp)
-    fsw     ft3, 12(sp)
-    fsw     ft4, 16(sp)
-    fsw     ft5, 20(sp)
-    fsw     ft6, 24(sp)
-    fsw     ft7, 28(sp)
-    fsw     fa0, 32(sp)
-    fsw     fa1, 36(sp)
-    fsw     fa2, 40(sp)
-    fsw     fa3, 44(sp)
-    fsw     fa4, 48(sp)
-    fsw     fa5, 52(sp)
-    fsw     fa6, 56(sp)
-    fsw     fa7, 60(sp)
-    fsw     ft8, 64(sp)
-    fsw     ft9, 68(sp)
-    fsw     ft10,72(sp)
-    fsw     ft11,76(sp)
-
-    la      t0, g_nmivector
-    lw      t0, (t0)
-    jalr    t0
-
-    flw     ft0, 0(sp)
-    flw     ft1, 4(sp)
-    flw     ft2, 8(sp)
-    flw     ft3, 12(sp)
-    flw     ft4, 16(sp)
-    flw     ft5, 20(sp)
-    flw     ft6, 24(sp)
-    flw     ft7, 28(sp)
-    flw     fa0, 32(sp)
-    flw     fa1, 36(sp)
-    flw     fa2, 40(sp)
-    flw     fa3, 44(sp)
-    flw     fa4, 48(sp)
-    flw     fa5, 52(sp)
-    flw     fa6, 56(sp)
-    flw     fa7, 60(sp)
-    flw     ft8, 64(sp)
-    flw     ft9, 68(sp)
-    flw     ft10,72(sp)
-    flw     ft11,76(sp)
-
-    addi    sp, sp, 80
-
-    lw      ra, 0(sp)
-    lw      t0, 4(sp)
-    lw      t1, 8(sp)
-    lw      t2, 12(sp)
-    lw      a0, 16(sp)
-    lw      a1, 20(sp)
-    lw      a2, 24(sp)
-    lw      a3, 28(sp)
-    lw      a4, 32(sp)
-    lw      a5, 36(sp)
-    lw      a6, 40(sp)
-    lw      a7, 44(sp)
-    lw      t3, 48(sp)
-    lw      t4, 52(sp)
-    lw      t5, 56(sp)
-    lw      t6, 60(sp)
-    addi    sp, sp, 64
-    mret
-
-    .size   Default_Handler, . - Default_Handler
-
-/*    Macro to define default handlers. Default handler
- *    will be weak symbol and just dead loops. They can be
- *    overwritten by other handlers */
-    .macro  def_irq_handler handler_name
-    .weak   \handler_name
-    .globl  \handler_name
-    .set    \handler_name, Default_Handler
-    .endm
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/debug.c b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/debug.c
deleted file mode 100644
index b8e720f65e..0000000000
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/debug.c
+++ /dev/null
@@ -1,914 +0,0 @@
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#define DEFAULT_UART_ID 0
-
-uint32_t debug_uart_id = DEFAULT_UART_ID;
-
-//#define CHAR_BIT  8
-//FIXME no ugly declare
-extern int bl_uart_data_send(uint8_t id, uint8_t data);
-
-volatile bool sys_log_all_enable = true;
-
-enum flag {
-    FL_ZERO     = 0x01, /* Zero modifier */
-    FL_MINUS    = 0x02, /* Minus modifier */
-    FL_PLUS     = 0x04, /* Plus modifier */
-    FL_TICK     = 0x08, /* ' modifier */
-    FL_SPACE    = 0x10, /* Space modifier */
-    FL_HASH     = 0x20, /* # modifier */
-    FL_SIGNED   = 0x40, /* Number is signed */
-    FL_UPPER    = 0x80  /* Upper case digits */
-};
-
-/* These may have to be adjusted on certain implementations */
-enum ranks {
-    rank_char   = -2,
-    rank_short  = -1,
-    rank_int    =  0,
-    rank_long   =  1,
-    rank_longlong   =  2
-};
-
-#define MIN_RANK    rank_char
-#define MAX_RANK    rank_longlong
-
-#define INTMAX_RANK rank_longlong
-#define SIZE_T_RANK rank_long
-#define PTRDIFF_T_RANK  rank_long
-
-#define EMIT(x) { if (o < n) { *q++ = (x); } o++; }
-
-void debug_uart_id_set(uint8_t id)
-{
-    debug_uart_id = id;
-}
-
-static size_t
-format_int(char *q, size_t n, uintmax_t val, unsigned int flags,
-       int base, int width, int prec)
-{
-    char *qq;
-    size_t o = 0, oo;
-    static const char lcdigits[] = "0123456789abcdef";
-    static const char ucdigits[] = "0123456789ABCDEF";
-    const char *digits;
-    uintmax_t tmpval;
-    int minus = 0;
-    int ndigits = 0, nchars;
-    int tickskip, b4tick;
-
-    /* Select type of digits */
-    digits = (flags & FL_UPPER) ? ucdigits : lcdigits;
-
-    /* If signed, separate out the minus */
-    if (flags & FL_SIGNED && (intmax_t) val < 0) {
-        minus = 1;
-        val = (uintmax_t) (-(intmax_t) val);
-    }
-
-    /* Count the number of digits needed.  This returns zero for 0. */
-    tmpval = val;
-    while (tmpval) {
-        tmpval /= base;
-        ndigits++;
-    }
-
-    /* Adjust ndigits for size of output */
-
-    if (flags & FL_HASH && base == 8) {
-        if (prec < ndigits + 1)
-            prec = ndigits + 1;
-    }
-
-    if (ndigits < prec) {
-        ndigits = prec; /* Mandatory number padding */
-    } else if (val == 0) {
-        ndigits = 1;    /* Zero still requires space */
-    }
-
-    /* For ', figure out what the skip should be */
-    if (flags & FL_TICK) {
-        tickskip = (base == 16) ? 4 : 3;
-    } else {
-        tickskip = ndigits; /* No tick marks */
-    }
-
-    /* Tick marks aren't digits, but generated by the number converter */
-    ndigits += (ndigits - 1) / tickskip;
-
-    /* Now compute the number of nondigits */
-    nchars = ndigits;
-
-    if (minus || (flags & (FL_PLUS | FL_SPACE)))
-        nchars++;   /* Need space for sign */
-    if ((flags & FL_HASH) && base == 16) {
-        nchars += 2;    /* Add 0x for hex */
-    }
-
-    /* Emit early space padding */
-    if (!(flags & (FL_MINUS | FL_ZERO)) && width > nchars) {
-        while (width > nchars) {
-            EMIT(' ');
-            width--;
-        }
-    }
-
-    /* Emit nondigits */
-    if (minus) {
-        EMIT('-');
-    } else if (flags & FL_PLUS) {
-        EMIT('+');
-    } else if (flags & FL_SPACE) {
-        EMIT(' ');
-    }
-
-    if ((flags & FL_HASH) && base == 16) {
-        EMIT('0');
-        EMIT((flags & FL_UPPER) ? 'X' : 'x');
-    }
-
-    /* Emit zero padding */
-    if ((flags & (FL_MINUS | FL_ZERO)) == FL_ZERO && width > ndigits) {
-        while (width > nchars) {
-            EMIT('0');
-            width--;
-        }
-    }
-
-    /* Generate the number.  This is done from right to left. */
-    q += ndigits;       /* Advance the pointer to end of number */
-    o += ndigits;
-    qq = q;
-    oo = o;         /* Temporary values */
-
-    b4tick = tickskip;
-    while (ndigits > 0) {
-        if (!b4tick--) {
-            qq--;
-            oo--;
-            ndigits--;
-            if (oo < n)
-                *qq = '_';
-            b4tick = tickskip - 1;
-        }
-        qq--;
-        oo--;
-        ndigits--;
-        if (oo < n)
-            *qq = digits[val % base];
-        val /= base;
-    }
-
-    /* Emit late space padding */
-    while ((flags & FL_MINUS) && width > nchars) {
-        EMIT(' ');
-        width--;
-    }
-
-    return o;
-}
-
-#define ZEROPAD     (1<<0)  /* Pad with zero */
-#define SIGN        (1<<1)  /* Unsigned/signed long */
-#define PLUS        (1<<2)  /* Show plus */
-#define SPACE       (1<<3)  /* Spacer */
-#define LEFT        (1<<4)  /* Left justified */
-#define HEX_PREP    (1<<5)  /* 0x */
-#define UPPERCASE   (1<<6)  /* 'ABCDEF' */
-
-#include 
-#define CVTBUFSIZE 80
-
-static char *cvt(double arg, int ndigits, int *decpt, int *sign, char *buf, int eflag)
-{
-  int r2;
-  double fi, fj;
-  char *p, *p1;
-
-  if (ndigits < 0) ndigits = 0;
-  if (ndigits >= CVTBUFSIZE - 1) ndigits = CVTBUFSIZE - 2;
-  r2 = 0;
-  *sign = 0;
-  p = &buf[0];
-  if (arg < 0)
-  {
-    *sign = 1;
-    arg = -arg;
-  }
-  arg = modf(arg, &fi);
-  p1 = &buf[CVTBUFSIZE];
-
-  if (fi != 0)
-  {
-    p1 = &buf[CVTBUFSIZE];
-    while (fi != 0)
-    {
-      fj = modf(fi / 10, &fi);
-      *--p1 = (int)((fj + 0.03) * 10) + '0';
-      r2++;
-    }
-    while (p1 < &buf[CVTBUFSIZE]) *p++ = *p1++;
-  }
-  else if (arg > 0)
-  {
-    while ((fj = arg * 10) < 1)
-    {
-      arg = fj;
-      r2--;
-    }
-  }
-  p1 = &buf[ndigits];
-  if (eflag == 0) p1 += r2;
-  *decpt = r2;
-  if (p1 < &buf[0])
-  {
-    buf[0] = '\0';
-    return buf;
-  }
-  while (p <= p1 && p < &buf[CVTBUFSIZE])
-  {
-    arg *= 10;
-    arg = modf(arg, &fj);
-    *p++ = (int) fj + '0';
-  }
-  if (p1 >= &buf[CVTBUFSIZE])
-  {
-    buf[CVTBUFSIZE - 1] = '\0';
-    return buf;
-  }
-  p = p1;
-  *p1 += 5;
-  while (*p1 > '9')
-  {
-    *p1 = '0';
-    if (p1 > buf)
-      ++*--p1;
-    else
-    {
-      *p1 = '1';
-      (*decpt)++;
-      if (eflag == 0)
-      {
-        if (p > buf) *p = '0';
-        p++;
-      }
-    }
-  }
-  *p = '\0';
-  return buf;
-}
-
-char *ecvtbuf(double arg, int ndigits, int *decpt, int *sign, char *buf)
-{
-  return cvt(arg, ndigits, decpt, sign, buf, 1);
-}
-
-char *fcvtbuf(double arg, int ndigits, int *decpt, int *sign, char *buf)
-{
-  return cvt(arg, ndigits, decpt, sign, buf, 0);
-}
-
-static void ee_bufcpy(char *d, char *s, int count);
-
-void ee_bufcpy(char *pd, char *ps, int count) {
-    char *pe=ps+count;
-    while (ps!=pe)
-        *pd++=*ps++;
-}
-
-static void parse_float(double value, char *buffer, char fmt, int precision)
-{
-  int decpt, sign, exp, pos;
-  char *digits = NULL;
-  char cvtbuf[80];
-  int capexp = 0;
-  int magnitude;
-
-  if (fmt == 'G' || fmt == 'E')
-  {
-    capexp = 1;
-    fmt += 'a' - 'A';
-  }
-
-  if (fmt == 'g')
-  {
-    digits = ecvtbuf(value, precision, &decpt, &sign, cvtbuf);
-    magnitude = decpt - 1;
-    if (magnitude < -4  ||  magnitude > precision - 1)
-    {
-      fmt = 'e';
-      precision -= 1;
-    }
-    else
-    {
-      fmt = 'f';
-      precision -= decpt;
-    }
-  }
-
-  if (fmt == 'e')
-  {
-    digits = ecvtbuf(value, precision + 1, &decpt, &sign, cvtbuf);
-
-    if (sign) *buffer++ = '-';
-    *buffer++ = *digits;
-    if (precision > 0) *buffer++ = '.';
-    ee_bufcpy(buffer, digits + 1, precision);
-    buffer += precision;
-    *buffer++ = capexp ? 'E' : 'e';
-
-    if (decpt == 0)
-    {
-      if (value == 0.0)
-        exp = 0;
-      else
-        exp = -1;
-    }
-    else
-      exp = decpt - 1;
-
-    if (exp < 0)
-    {
-      *buffer++ = '-';
-      exp = -exp;
-    }
-    else
-      *buffer++ = '+';
-
-    buffer[2] = (exp % 10) + '0';
-    exp = exp / 10;
-    buffer[1] = (exp % 10) + '0';
-    exp = exp / 10;
-    buffer[0] = (exp % 10) + '0';
-    buffer += 3;
-  }
-  else if (fmt == 'f')
-  {
-    digits = fcvtbuf(value, precision, &decpt, &sign, cvtbuf);
-    if (sign) *buffer++ = '-';
-    if (*digits)
-    {
-      if (decpt <= 0)
-      {
-        *buffer++ = '0';
-        *buffer++ = '.';
-        for (pos = 0; pos < -decpt; pos++) *buffer++ = '0';
-        while (*digits) *buffer++ = *digits++;
-      }
-      else
-      {
-        pos = 0;
-        while (*digits)
-        {
-          if (pos++ == decpt) *buffer++ = '.';
-          *buffer++ = *digits++;
-        }
-      }
-    }
-    else
-    {
-      *buffer++ = '0';
-      if (precision > 0)
-      {
-        *buffer++ = '.';
-        for (pos = 0; pos < precision; pos++) *buffer++ = '0';
-      }
-    }
-  }
-
-  *buffer = '\0';
-}
-
-static void decimal_point(char *buffer)
-{
-  while (*buffer)
-  {
-    if (*buffer == '.') return;
-    if (*buffer == 'e' || *buffer == 'E') break;
-    buffer++;
-  }
-
-  if (*buffer)
-  {
-    int n = strnlen(buffer,256);
-    while (n > 0)
-    {
-      buffer[n + 1] = buffer[n];
-      n--;
-    }
-
-    *buffer = '.';
-  }
-  else
-  {
-    *buffer++ = '.';
-    *buffer = '\0';
-  }
-}
-
-static void cropzeros(char *buffer)
-{
-  char *stop;
-
-  while (*buffer && *buffer != '.') buffer++;
-  if (*buffer++)
-  {
-    while (*buffer && *buffer != 'e' && *buffer != 'E') buffer++;
-    stop = buffer--;
-    while (*buffer == '0') buffer--;
-    if (*buffer == '.') buffer--;
-    while (buffer!=stop)
-        *++buffer=0;
-  }
-}
-
-static char *flt(char *str, double num, int size, int precision, char fmt, int flags)
-{
-  char tmp[80];
-  char c, sign;
-  int n, i;
-
-  // Left align means no zero padding
-  if (flags & LEFT) flags &= ~ZEROPAD;
-
-  // Determine padding and sign char
-  c = (flags & ZEROPAD) ? '0' : ' ';
-  sign = 0;
-  if (flags & SIGN)
-  {
-    if (num < 0.0)
-    {
-      sign = '-';
-      num = -num;
-      size--;
-    }
-    else if (flags & PLUS)
-    {
-      sign = '+';
-      size--;
-    }
-    else if (flags & SPACE)
-    {
-      sign = ' ';
-      size--;
-    }
-  }
-
-  // Compute the precision value
-  if (precision < 0)
-    precision = 6; // Default precision: 6
-
-  // Convert floating point number to text
-  parse_float(num, tmp, fmt, precision);
-
-  if ((flags & HEX_PREP) && precision == 0) decimal_point(tmp);
-  if (fmt == 'g' && !(flags & HEX_PREP)) cropzeros(tmp);
-
-  n = strnlen(tmp,256);
-
-  // Output number with alignment and padding
-  size -= n;
-  if (!(flags & (ZEROPAD | LEFT))) while (size-- > 0) *str++ = ' ';
-  if (sign) *str++ = sign;
-  if (!(flags & LEFT)) while (size-- > 0) *str++ = c;
-  for (i = 0; i < n; i++) *str++ = tmp[i];
-  while (size-- > 0) *str++ = ' ';
-
-  return str;
-}
-
-
-/*use O0 preventing consuming more stack*/
-int __attribute__((optimize("O1"))) vsnprintf(char *buffer, size_t n, const char *format, va_list ap)
-{
-    const char *p = format;
-    char ch;
-    char *q = buffer;
-    char *tmp;
-    size_t o = 0;       /* Number of characters output */
-    uintmax_t val = 0;
-    int rank = rank_int;    /* Default rank */
-    int width = 0;
-    int prec = -1;
-    int base;
-    size_t sz;
-    unsigned int flags = 0;
-    enum {
-        st_normal,  /* Ground state */
-        st_flags,   /* Special flags */
-        st_width,   /* Field width */
-        st_prec,    /* Field precision */
-        st_modifiers    /* Length or conversion modifiers */
-    } state = st_normal;
-    const char *sarg;   /* %s string argument */
-    char carg;      /* %c char argument */
-    int slen;       /* String length */
-
-    while ((ch = *p++)) {
-        switch (state) {
-        case st_normal:
-            if (ch == '%') {
-                state = st_flags;
-                flags = 0;
-                rank = rank_int;
-                width = 0;
-                prec = -1;
-            } else {
-                EMIT(ch);
-            }
-            break;
-
-        case st_flags:
-            switch (ch) {
-            case '-':
-                flags |= FL_MINUS;
-                break;
-            case '+':
-                flags |= FL_PLUS;
-                break;
-            case '\'':
-                flags |= FL_TICK;
-                break;
-            case ' ':
-                flags |= FL_SPACE;
-                break;
-            case '#':
-                flags |= FL_HASH;
-                break;
-            case '0':
-                flags |= FL_ZERO;
-                break;
-            default:
-                state = st_width;
-                p--;    /* Process this character again */
-                break;
-            }
-            break;
-
-        case st_width:
-            if (ch >= '0' && ch <= '9') {
-                width = width * 10 + (ch - '0');
-            } else if (ch == '*') {
-                width = va_arg(ap, int);
-                if (width < 0) {
-                    width = -width;
-                    flags |= FL_MINUS;
-                }
-            } else if (ch == '.') {
-                prec = 0;   /* Precision given */
-                state = st_prec;
-            } else {
-                state = st_modifiers;
-                p--;    /* Process this character again */
-            }
-            break;
-
-        case st_prec:
-            if (ch >= '0' && ch <= '9') {
-                prec = prec * 10 + (ch - '0');
-            } else if (ch == '*') {
-                prec = va_arg(ap, int);
-                if (prec < 0)
-                    prec = -1;
-            } else {
-                state = st_modifiers;
-                p--;    /* Process this character again */
-            }
-            break;
-
-        case st_modifiers:
-            switch (ch) {
-                /* Length modifiers - nonterminal sequences */
-            case 'h':
-                rank--; /* Shorter rank */
-                break;
-            case 'l':
-                rank++; /* Longer rank */
-                break;
-            case 'j':
-                rank = INTMAX_RANK;
-                break;
-            case 'z':
-                rank = SIZE_T_RANK;
-                break;
-            case 't':
-                rank = PTRDIFF_T_RANK;
-                break;
-            case 'L':
-            case 'q':
-                rank += 2;
-                break;
-            default:
-                /* Output modifiers - terminal sequences */
-
-                /* Next state will be normal */
-                state = st_normal;
-
-                /* Canonicalize rank */
-                if (rank < MIN_RANK)
-                    rank = MIN_RANK;
-                else if (rank > MAX_RANK)
-                    rank = MAX_RANK;
-
-                switch (ch) {
-                case 'P':   /* Upper case pointer */
-                    flags |= FL_UPPER;
-                    __attribute__ ((fallthrough));
-                    /* fall through */
-                case 'p':   /* Pointer */
-                    base = 16;
-                    prec = (CHAR_BIT*sizeof(void *)+3)/4;
-                    flags |= FL_HASH;
-                    val = (uintmax_t)(uintptr_t)
-                        va_arg(ap, void *);
-                    goto is_integer;
-
-                case 'd':   /* Signed decimal output */
-                case 'i':
-                    base = 10;
-                    flags |= FL_SIGNED;
-                    switch (rank) {
-                    case rank_char:
-                        /* Yes, all these casts are
-                           needed... */
-                        val = (uintmax_t)(intmax_t)
-                            (signed char)
-                            va_arg(ap, signed int);
-                        break;
-                    case rank_short:
-                        val = (uintmax_t)(intmax_t)
-                            (signed short)
-                            va_arg(ap, signed int);
-                        break;
-                    case rank_int:
-                        val = (uintmax_t)(intmax_t)
-                            va_arg(ap, signed int);
-                        break;
-                    case rank_long:
-                        val = (uintmax_t)(intmax_t)
-                            va_arg(ap, signed long);
-                        break;
-                    case rank_longlong:
-                        val = (uintmax_t)(intmax_t)
-                            va_arg(ap,
-                               signed long long);
-                        break;
-                    }
-                    goto is_integer;
-                case 'o':   /* Octal */
-                    base = 8;
-                    goto is_unsigned;
-                case 'u':   /* Unsigned decimal */
-                    base = 10;
-                    goto is_unsigned;
-                case 'X':   /* Upper case hexadecimal */
-                    flags |= FL_UPPER;
-                    __attribute__ ((fallthrough));
-                    /* fall through */
-                case 'x':   /* Hexadecimal */
-                    base = 16;
-                    goto is_unsigned;
-
-                is_unsigned:
-                    switch (rank) {
-                    case rank_char:
-                        val = (uintmax_t)
-                            (unsigned char)
-                            va_arg(ap, unsigned
-                                   int);
-                        break;
-                    case rank_short:
-                        val = (uintmax_t)
-                            (unsigned short)
-                            va_arg(ap, unsigned
-                                   int);
-                        break;
-                    case rank_int:
-                        val = (uintmax_t)
-                            va_arg(ap, unsigned
-                                   int);
-                        break;
-                    case rank_long:
-                        val = (uintmax_t)
-                            va_arg(ap, unsigned
-                                   long);
-                        break;
-                    case rank_longlong:
-                        val = (uintmax_t)
-                            va_arg(ap, unsigned
-                                   long long);
-                        break;
-                    }
-                    /* fall through */
-
-                is_integer:
-                    sz = format_int(q, (o < n) ? n - o : 0,
-                            val, flags, base,
-                            width, prec);
-                    q += sz;
-                    o += sz;
-                    break;
-
-                case 'c':   /* Character */
-                    carg = (char)va_arg(ap, int);
-                    sarg = &carg;
-                    slen = 1;
-                    goto is_string;
-                case 's':   /* String */
-                    sarg = va_arg(ap, const char *);
-                    sarg = sarg ? sarg : "(null)";
-                    slen = strlen(sarg);
-                    goto is_string;
-
-                is_string:
-                    {
-                        char sch;
-                        int i;
-
-                        if (prec != -1 && slen > prec)
-                            slen = prec;
-
-                        if (width > slen
-                            && !(flags & FL_MINUS)) {
-                            char pad =
-                                (flags & FL_ZERO) ?
-                                '0' : ' ';
-                            while (width > slen) {
-                                EMIT(pad);
-                                width--;
-                            }
-                        }
-                        for (i = slen; i; i--) {
-                            sch = *sarg++;
-                            EMIT(sch);
-                        }
-                        if (width > slen
-                            && (flags & FL_MINUS)) {
-                            while (width > slen) {
-                                EMIT(' ');
-                                width--;
-                            }
-                        }
-                    }
-                    break;
-
-                case 'n':
-                    {
-                        /* Output the number of
-                           characters written */
-
-                        switch (rank) {
-                        case rank_char:
-                            *va_arg(ap,
-                                signed char *)
-                                = o;
-                            break;
-                        case rank_short:
-                            *va_arg(ap,
-                                signed short *)
-                                = o;
-                            break;
-                        case rank_int:
-                            *va_arg(ap,
-                                signed int *)
-                                = o;
-                            break;
-                        case rank_long:
-                            *va_arg(ap,
-                                signed long *)
-                                = o;
-                            break;
-                        case rank_longlong:
-                            *va_arg(ap,
-                                signed long long *)
-                                = o;
-                            break;
-                        }
-                    }
-                    break;
-#ifndef DISABLE_PRINT_FLOAT
-                case 'f':
-                    {
-                            tmp = q;
-                        q = flt(q, va_arg(ap, double), width, prec, ch, SIGN);
-                            o += q - tmp;
-                        continue;
-                    }
-#endif
-                default:    /* Anything else, including % */
-                    EMIT(ch);
-                    break;
-                }
-            }
-        }
-    }
-
-    /* Null-terminate the string */
-    if (o < n)
-        *q = '\0';  /* No overflow */
-    else if (n > 0)
-        buffer[n - 1] = '\0';   /* Overflow - terminate at end of buffer */
-
-    return o;
-}
-
-#ifdef SYS_BIG_DEBUG_BUFFER
-static char string[2048];
-#else
-static char string[512];
-#endif
-
-int vsprintf(char *buffer, const char *format, va_list ap)
-{
-    return vsnprintf(buffer, sizeof(string) - 32, format, ap);
-}
-
-extern volatile bool sys_log_all_enable;
-
-void vprint(const char *fmt, va_list argp)
-{
-    char *str;
-    int ch;
-
-    if (sys_log_all_enable) {
-        str = string;
-        if (0 < vsprintf(string, fmt, argp)) {
-            while ('\0' != (ch = *(str++))) {
-#if !defined(DISABLE_PRINT)
-                bl_uart_data_send(debug_uart_id, ch);
-#endif
-            }
-        }
-    }
-}
-
-int bl_putchar(int c)
-{
-#if !defined(DISABLE_PRINT)
-    bl_uart_data_send(debug_uart_id, c);
-#endif
-    return 0;
-}
-
-int puts(const char *s)
-{
-    int counter = 0;
-    char c;
-
-    if (sys_log_all_enable) {
-        while ('\0' != (c = *(s++))) {
-#if !defined(DISABLE_PRINT)
-            bl_uart_data_send(debug_uart_id, c);
-#endif
-            counter++;
-        }
-    }
-    return counter;
-}
-
-int printf(const char *fmt, ...)
-{
-    va_list argp;
-
-    if (sys_log_all_enable) {
-        va_start(argp, fmt);
-        vprint(fmt, argp);
-        va_end(argp);
-    }
-
-    return 0;
-}
-
-int sprintf(char *buffer, const char *format, ...)
-{
-    va_list ap;
-    int rv;
-
-    va_start(ap, format);
-    rv = vsnprintf(buffer, ~(size_t) 0, format, ap);
-    va_end(ap);
-
-    return rv;
-}
-
-int snprintf(char *buffer, size_t n, const char *format, ...)
-{
-    va_list ap;
-    int rv;
-
-    va_start(ap, format);
-    rv = vsnprintf(buffer, n, format, ap);
-    va_end(ap);
-    return rv;
-}
-
-void vMainUARTPrintString(char *pcString)
-{
-    puts(pcString);
-}
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/startup_bl606p.c b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/startup_bl606p.c
deleted file mode 100644
index 524439edc5..0000000000
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/startup_bl606p.c
+++ /dev/null
@@ -1,399 +0,0 @@
-#ifdef BL808
-#include "bl808.h"
-#include "bl808_clock.h"
-#include "bl808_pds.h"
-#include "bl808_glb.h"
-#elif defined(BL606P)
-#include "bl606p.h"
-#include "bl606p_clock.h"
-#include "bl606p_pds.h"
-#include "bl606p_glb.h"
-#else
-#error "Use CHIP BL808/BL606P for this module"
-#endif
-
-/*----------------------------------------------------------------------------
-  Define clocks
- *----------------------------------------------------------------------------*/
-#define SYSTEM_CLOCK (32000000UL)
-
-/*----------------------------------------------------------------------------
-  System initialization function
- *----------------------------------------------------------------------------*/
-
-void System_BOR_Init(void)
-{
-    //HBN_BOR_CFG_Type borCfg = {1/* pu_bor */, 0/* irq_bor_en */, 1/* bor_vth */, 1/* bor_sel */};
-    //HBN_Set_BOR_Cfg(&borCfg);
-}
-
-void System_Core_Clock_Set(BL_System_Clock_Type type, uint32_t clock)
-{
-    Clock_Cfg_Type *pClk = (Clock_Cfg_Type *)SYS_CLOCK_CFG_ADDR;
-
-    CHECK_PARAM(IS_BL_SYSTEM_CLOCK_TYPE(type));
-
-    if (type < BL_SYSTEM_CLOCK_MAX) {
-        pClk->systemClock[type] = clock;
-        pClk->magic = SYS_CLOCK_CFG_MAGIC;
-    }
-}
-
-void board_init(void)
-{
-
-}
-
-void system_init_bl606p(void)
-#if 0
-{
-    uint32_t i = 0;
-
-    /* enable mstatus FS */
-    uint32_t mstatus = __get_MSTATUS();
-    mstatus |= (1 << 13);
-    __set_MSTATUS(mstatus);
-
-    /* enable mxstatus THEADISAEE */
-    uint32_t mxstatus = __get_MXSTATUS();
-    mxstatus |= (1 << 22);
-    /* enable mxstatus MM */
-    mxstatus |= (1 << 15);
-    __set_MXSTATUS(mxstatus);
-
-    /* get interrupt level from info */
-    CLIC->CLICCFG = (((CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos) << CLIC_CLICCFG_NLBIT_Pos);
-
-    /* Every interrupt should be clear by software*/
-    for (i = 0; i < IRQn_LAST; i++) {
-        CLIC->CLICINT[i].IP = 0;
-        CLIC->CLICINT[i].IE = 0;
-        CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */
-    }
-
-    /* tspend interrupt will be clear auto*/
-    /* tspend use positive interrupt */
-    CLIC->CLICINT[MSOFT_IRQn].ATTR = 0x3;
-
-#ifdef BOOTROM
-    /* i cache enable d cache disable*/
-    uint32_t cache;
-    __DSB();
-    __ISB();
-    __ICACHE_IALL();
-    cache = __get_MHCR();
-    cache |= CACHE_MHCR_IE_Msk;
-    //cache &= ~(uint32_t)CACHE_MHCR_DE_Msk; /* disable all Cache */
-    cache |= (CACHE_MHCR_DE_Msk | CACHE_MHCR_WB_Msk | CACHE_MHCR_WA_Msk | CACHE_MHCR_RS_Msk | CACHE_MHCR_BPE_Msk | CACHE_MHCR_L0BTB_Msk); /* enable all Cache */
-    __set_MHCR(cache);
-    __DCACHE_IALL(); /* invalidate all Cache */
-    __DSB();
-    __ISB();
-    //csi_dcache_disable();
-#else
-    csi_icache_enable();
-    csi_dcache_enable();
-    /* enable preload $ AMR for D$ */
-    __set_MHINT(0x000c);
-#endif
-
-#ifndef CONFIG_OS_SUPPORT
-    /* enable mexstatus SPUSHEN and SPSWAPEN for ipush/ipop and irq stack */
-    uint32_t mexstatus = __get_MEXSTATUS();
-    mexstatus |= (0x03 << 16);
-    __set_MEXSTATUS(mexstatus);
-#else
-    /* enable mexstatus SPUSHEN and SPSWAPEN for ipush/ipop and irq stack*/
-    uint32_t mexstatus = __get_MEXSTATUS();
-    mexstatus |= (0x3 << 16);
-    __set_MEXSTATUS(mexstatus);
-#endif
-
-#ifdef BOOTROM
-    extern void GLB_Power_On_LDO18_IO(void);
-    extern void WDT_Disable(void);
-    extern BL_Err_Type HBN_Clear_RTC_INT(void);
-    uint32_t *p;
-    BMX_TO_Cfg_Type bmxCfg = {
-        .arbMod = BMX_ARB_FIX,
-        .timeoutEn = 0x1F,
-        //.errEn=DISABLE,
-    };
-
-    /* M0 boot log Flag */
-    extern uint32_t __bootrom_data_section_end;
-    p = (uint32_t *)(&__bootrom_data_section_end);
-    *p = 0x5A5AA5A5;
-    /*diable BMX error incase Sbooten=0xf,while user send vector(core) reset and CPU read deadbeef,
-    if not disable this bit, CPU will also get hardfault at the same time*/
-    GLB_BMX_TO_Init(&bmxCfg);
-    //GLB_BMX_Addr_Monitor_Disable();
-
-    /* Do the same for L1C BMX*/
-    //L1C_BMX_Init(&l1cBmxCfg);
-    //L1C_BMX_Addr_Monitor_Disable();
-
-    /* make ram max*/
-    //L1C_Set_Way_Disable(0x0f);
-    //GLB_Set_EM_Sel(GLB_EM_0KB);
-
-    /* Disable Watchdog */
-    WDT_Disable();
-    /* Clear RTC */
-    HBN_Clear_RTC_INT();
-
-    /*TODO*/
-    /* Make OCRAM Idle from retention or sleep */
-    //GLB_Set_OCRAM_Idle();
-    //GLB_Set_SRAM_RET(0x0);
-    //GLB_Set_SRAM_SLP(0x0);
-    /* Disable embedded flash power up*/
-    //HBN_Set_Embedded_Flash_Pullup(DISABLE);
-#if 0
-    /* disable hardware_pullup_pull_down (reg_en_hw_pu_pd = 0) */
-    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
-    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD);
-    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
-
-    /* Restore default setting*/
-    GLB_UART_Sig_Swap_Set(UART_SIG_SWAP_NONE);
-    GLB_JTAG_Sig_Swap_Set(JTAG_SIG_SWAP_NONE);
-
-    /*Power up soc 11 power domain,TODO: This should be optional */
-    //AON_Power_On_SOC_11();
-    /* Record LDO18 pu flag before power up. This maybe not neccessary but copy from 606*/
-    //BL_WR_WORD(BFLB_BOOTROM_AP_BOOT_LOG_ADDR,GLB->ldo18io.BF.pu_ldo18io);
-    /* Power up flash power*/
-    //GLB_Power_On_LDO18_IO();
-
-#endif
-#endif
-
-    GLB_UART_Sig_Swap_Set(GLB_UART_SIG_SWAP_GRP_GPIO12_GPIO23, 1);
-    GLB_UART_Sig_Swap_Set(GLB_UART_SIG_SWAP_GRP_GPIO36_GPIO45, 1);
-
-    /* init bor for all platform */
-    System_BOR_Init();
-}
-#else
-{
-    uint32_t i=0;
-
-    /* enable mstatus FS */
-    uint32_t mstatus = __get_MSTATUS();
-    mstatus |= (1 << 13);
-    __set_MSTATUS(mstatus);
-
-    /* enable mxstatus THEADISAEE */
-    uint32_t mxstatus = __get_MXSTATUS();
-    mxstatus |= (1 << 22);
-    /* enable mxstatus MM */
-    mxstatus |= (1 << 15);
-    __set_MXSTATUS(mxstatus);
-
-    /* get interrupt level from info */
-    CLIC->CLICCFG = (((CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos) << CLIC_CLICCFG_NLBIT_Pos);
-
-    /* Every interrupt should be clear by software*/
-    for (i = 0; i < IRQn_LAST; i++) {
-        CLIC->CLICINT[i].IP = 0;
-        CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */
-    }
-
-    /* tspend interrupt will be clear auto*/
-    /* tspend use positive interrupt */
-    CLIC->CLICINT[MSOFT_IRQn].ATTR = 0x3;
-
-    csi_dcache_enable();
-    csi_icache_enable();
-    /* enable preload $ AMR for D$*/
-    __set_MHINT(0x0004);
-    CPU_Interrupt_Enable(MSOFT_IRQn);
-
-    /* disable mexstatus SPUSHEN and SPSWAPEN for ipush/ipop*/
-    uint32_t mexstatus = __get_MEXSTATUS();
-    mexstatus &= ~(0x3 << 16);
-    __set_MEXSTATUS(mexstatus);
-
-#ifdef BOOTROM
-    extern void GLB_Power_On_LDO18_IO(void);
-    extern void WDT_Disable(void);
-    extern void HBN_Clear_RTC_INT(void);
-
-    BMX_Cfg_Type bmxCfg={
-            .timeoutEn=0,
-            .errEn=DISABLE,
-            .arbMod=BMX_ARB_FIX
-    };
-    L1C_BMX_Cfg_Type  l1cBmxCfg={
-            .timeoutEn=0,
-            .errEn=DISABLE,
-            .arbMod=L1C_BMX_ARB_FIX,
-    };
-
-    /* NP boot log Flag */
-    p= (uint32_t *)(BFLB_BOOTROM_NP_BOOT_LOG_ADDR);
-    *p=0x5A5AA5A5;
-    /*diable BMX error incase Sbooten=0xf,while user send vector(core) reset and CPU read deadbeef,
-    if not disable this bit, CPU will also get hardfault at the same time*/
-    //GLB->bmx_cfg1.BF.bmx_err_en=0;
-    //GLB->bmx_cfg1.BF.bmx_timeout_en=0;
-    //GLB->bmx_cfg2.BF.bmx_err_addr_dis=1;
-    GLB_BMX_Init(&bmxCfg);
-    GLB_BMX_Addr_Monitor_Disable();
-    //L1C->l1c_config.BF.l1c_bmx_err_en=0;
-    //L1C->l1c_config.BF.l1c_bmx_timeout_en=0;
-    //L1C->l1c_bmx_err_addr_en.BF.l1c_bmx_err_addr_dis=1;
-    L1C_BMX_Init(&l1cBmxCfg);
-    L1C_BMX_Addr_Monitor_Disable();
-    //L1C->l1c_config.BF.l1c_way_dis=0xf;
-    L1C_Set_Way_Disable(0x0f);
-    /* Disable Watchdog */
-    WDT_Disable();
-    /* Clear RTC */
-    HBN_Clear_RTC_INT();
-    /* Make OCRAM Idle from retention or sleep */
-    GLB_Set_OCRAM_Idle();
-    /* Disable embedded flash power up*/
-    HBN_Set_Embedded_Flash_Pullup(DISABLE);
-#endif
-
-#if 0
-    /* disable hardware_pullup_pull_down (reg_en_hw_pu_pd = 0) */
-    tmpVal=BL_RD_REG(HBN_BASE,HBN_IRQ_MODE);
-    tmpVal=BL_CLR_REG_BIT(tmpVal,HBN_REG_EN_HW_PU_PD);
-    BL_WR_REG(HBN_BASE,HBN_IRQ_MODE,tmpVal);
-
-    GLB_Set_EM_Sel(GLB_EM_0KB);
-
-    /* Fix 26M xtal clkpll_sdmin */
-    tmpVal=BL_RD_REG(PDS_BASE,PDS_CLKPLL_SDM);
-    if(0x49D39D==BL_GET_REG_BITS_VAL(tmpVal,PDS_CLKPLL_SDMIN)){
-        tmpVal=BL_SET_REG_BITS_VAL(tmpVal,PDS_CLKPLL_SDMIN,0x49D89E);
-        BL_WR_REG(PDS_BASE,PDS_CLKPLL_SDM,tmpVal);
-    }
-
-    /* Restore default setting*/
-    GLB_UART_Sig_Swap_Set(UART_SIG_SWAP_NONE);
-    GLB_JTAG_Sig_Swap_Set(JTAG_SIG_SWAP_NONE);
-
-    /* CLear all interrupt */
-    p=(uint32_t *)(CLIC_HART0_ADDR+CLIC_INTIE);
-    for(i=0;i<(IRQn_LAST+3)/4;i++){
-        p[i]=0;
-    }
-    p=(uint32_t *)(CLIC_HART0_ADDR+CLIC_INTIP);
-    for(i=0;i<(IRQn_LAST+3)/4;i++){
-        p[i]=0;
-    }
-#endif
-    /* global IRQ disable */
-    __disable_irq();
-
-    //__asm volatile("csrw mnxti, %0" : : "i"(0x1 << 3));
-    /* init bor for all platform */
-    //system_bor_init();
-
-#ifdef BOOTROM
-    /*Power up soc 11 power domain,TODO: This should be optional */
-    //AON_Power_On_SOC_11();
-    /* Record LDO18 pu flag before power up. This maybe not neccessary but copy from 606*/
-    //BL_WR_WORD(BFLB_BOOTROM_AP_BOOT_LOG_ADDR,GLB->ldo18io.BF.pu_ldo18io);
-    /* Power up flash power*/
-    //GLB_Power_On_LDO18_IO();
-#endif
-
-}
-#endif
-
-void System_Post_Init(void)
-{
-#ifndef BOOTROM
-    //PDS_Power_On_MM_System();
-    //FIXME
-    GLB_Set_EM_Sel(1);
-#endif
-
-    System_Interrupt_Init();
-
-    CPU_Interrupt_Enable(MSOFT_IRQn);
-
-#ifndef BOOTROM
-    /* global IRQ enable */
-    __enable_irq();
-#endif
-}
-
-void System_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-    csi_vic_set_prio(IRQn, PreemptPriority);
-}
-
-int32_t drv_get_cpu_id(void)
-{
-    return __get_MHARTID();
-}
-
-int32_t drv_get_cpu_freq(int32_t idx)
-{
-    return 32 * 1000 * 1000UL;
-}
-
-#if defined(DUAL_CORE)
-extern void Reset_Handler(void);
-#endif
-
-/**
-  \brief       enable irq.
-  \param[in]   irq_num Number of IRQ.
-  \return      None.
-*/
-__attribute__((weak)) void CPU_Interrupt_Enable(uint32_t irq_num)
-{
-    if (irq_num >= IRQn_LAST) {
-        // MSG("Error! This interrupt don't support!\n");
-    } else {
-#ifdef CONFIG_SYSTEM_SECURE
-        csi_vic_enable_sirq(irq_num);
-#else
-        csi_vic_enable_irq(irq_num);
-#endif
-    }
-}
-
-/**
-  \brief       disable irq.
-  \param[in]   irq_num Number of IRQ.
-  \return      None.
-*/
-__attribute__((weak)) void CPU_Interrupt_Disable(uint32_t irq_num)
-{
-    if (irq_num >= IRQn_LAST) {
-        //MSG("Error! This interrupt don't support!\n");
-    } else {
-#ifdef CONFIG_SYSTEM_SECURE
-        csi_vic_disable_sirq(irq_num);
-#else
-        csi_vic_disable_irq(irq_num);
-#endif
-    }
-}
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clear the pending bit of an external interrupt.
-  \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__attribute__((weak)) void CPU_Interrupt_Pending_Clear(uint32_t irq_num)
-{
-    if (irq_num >= IRQn_LAST) {
-        //MSG("Error! This interrupt don't support!\n");
-        return;
-    } else {
-#ifdef CONFIG_SYSTEM_SECURE
-        csi_vic_clear_pending_irq(irq_num);
-#else
-        csi_vic_clear_pending_irq(irq_num);
-#endif
-    }
-}
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/startup_interrupt.c b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/startup_interrupt.c
deleted file mode 100644
index dff511ad05..0000000000
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/startup_interrupt.c
+++ /dev/null
@@ -1,180 +0,0 @@
-
-#include 
-#include 
-#include 
-#ifdef BL808
-#include "bl808.h"
-#elif defined(BL606P)
-#include "bl606p.h"
-#else
-#error "Use CHIP BL808/BL606P for this module"
-#endif
-
-
-#define MSG(...)
-
-typedef void( *pFunc )( void );
-void NMI_Handler(void);
-
-pFunc g_irqvector[IRQn_LAST]={0};
-pFunc g_nmivector=NMI_Handler;
-
-extern void Default_IRQHandler(void);
-extern void Default_Handler(void);
-extern void IRQ_Handler(void);
-
-const pFunc __Vectors[] __attribute__ ((section(".init"),aligned(64))) = {
-    IRQ_Handler,                         /*         */
-    IRQ_Handler,                         /*         */
-    IRQ_Handler,                         /*         */
-    IRQ_Handler,                         /*         */
-    IRQ_Handler,                         /*         */
-    IRQ_Handler,                         /*         */
-    IRQ_Handler,                         /*         */
-    IRQ_Handler,            /*         */
-    IRQ_Handler,                         /*         */
-    IRQ_Handler,                         /*         */
-    IRQ_Handler,                         /*         */
-    IRQ_Handler,                         /*         */
-    IRQ_Handler,                         /*         */
-    IRQ_Handler,                         /*         */
-    IRQ_Handler,                         /*         */
-    IRQ_Handler,                         /*         */
-
-    IRQ_Handler,//BMX_ERR_IRQHandler_Wrapper,              /* 16 +  0 */
-    IRQ_Handler,//BMX_TO_IRQHandler_Wrapper,               /* 16 +  1 */
-    IRQ_Handler,//L1C_BMX_ERR_IRQHandler_Wrapper,          /* 16 +  2 */
-    IRQ_Handler,//L1C_BMX_TO_IRQHandler_Wrapper,           /* 16 +  3 */
-    IRQ_Handler,//SEC_BMX_ERR_IRQHandler_Wrapper,          /* 16 +  4 */
-    IRQ_Handler,//RF_TOP_INT0_IRQHandler_Wrapper,          /* 16 +  5 */
-    IRQ_Handler,//RF_TOP_INT1_IRQHandler_Wrapper,          /* 16 +  6 */
-    IRQ_Handler,//SDIO_IRQHandler_Wrapper,                 /* 16 +  7 */
-    IRQ_Handler,//DMA_BMX_ERR_IRQHandler_Wrapper,          /* 16 +  8 */
-    IRQ_Handler,//SEC_GMAC_IRQHandler_Wrapper,             /* 16 +  9 */
-    IRQ_Handler,//SEC_CDET_IRQHandler_Wrapper,             /* 16 + 10 */
-    IRQ_Handler,//SEC_PKA_IRQHandler_Wrapper,              /* 16 + 11 */
-    IRQ_Handler,//SEC_TRNG_IRQHandler_Wrapper,             /* 16 + 12 */
-    IRQ_Handler,//SEC_AES_IRQHandler_Wrapper,              /* 16 + 13 */
-    IRQ_Handler,//SEC_SHA_IRQHandler_Wrapper,              /* 16 + 14 */
-    IRQ_Handler,//DMA_ALL_IRQHandler_Wrapper,              /* 16 + 15 */
-    IRQ_Handler,//0,                                       /* 16 + 16 */
-    IRQ_Handler,//0,                                       /* 16 + 17 */
-    IRQ_Handler,//0,                                       /* 16 + 18 */
-    IRQ_Handler,//IRTX_IRQHandler_Wrapper,                 /* 16 + 19 */
-    IRQ_Handler,//IRRX_IRQHandler_Wrapper,                 /* 16 + 20 */
-    IRQ_Handler,//0,                                       /* 16 + 21 */
-    IRQ_Handler,//0,                                       /* 16 + 22 */
-    IRQ_Handler,//SF_CTRL_IRQHandler_Wrapper,              /* 16 + 23 */
-    IRQ_Handler,//0,                                       /* 16 + 24 */
-    IRQ_Handler,//GPADC_DMA_IRQHandler_Wrapper,            /* 16 + 25 */
-    IRQ_Handler,//EFUSE_IRQHandler_Wrapper,                /* 16 + 26 */
-    IRQ_Handler,//SPI_IRQHandler_Wrapper,                  /* 16 + 27 */
-    IRQ_Handler,//0,                                       /* 16 + 28 */
-    IRQ_Handler,//UART0_IRQHandler_Wrapper,                /* 16 + 29 */
-    IRQ_Handler,//UART1_IRQHandler_Wrapper,                /* 16 + 30 */
-    IRQ_Handler,//0,                                       /* 16 + 31 */
-    IRQ_Handler,//I2C_IRQHandler_Wrapper,                  /* 16 + 32 */
-    IRQ_Handler,//0,                                       /* 16 + 33 */
-    IRQ_Handler,//PWM_IRQHandler_Wrapper,                  /* 16 + 34 */
-    IRQ_Handler,//0,                                       /* 16 + 35 */
-    IRQ_Handler,//TIMER_CH0_IRQHandler_Wrapper,            /* 16 + 36 */
-    IRQ_Handler,//TIMER_CH1_IRQHandler_Wrapper,            /* 16 + 37 */
-    IRQ_Handler,//TIMER_WDT_IRQHandler_Wrapper,            /* 16 + 38 */
-    IRQ_Handler,//0,                                       /* 16 + 39 */
-    IRQ_Handler,//0,                                       /* 16 + 40 */
-    IRQ_Handler,//0,                                       /* 16 + 41 */
-    IRQ_Handler,//0,                                       /* 16 + 42 */
-    IRQ_Handler,//0,                                       /* 16 + 43 */
-    IRQ_Handler,//GPIO_INT0_IRQHandler_Wrapper,            /* 16 + 44 */
-    IRQ_Handler,//0,                                       /* 16 + 45 */
-    IRQ_Handler,//0,                                       /* 16 + 46 */
-    IRQ_Handler,//0,                                       /* 16 + 47 */
-    IRQ_Handler,//0,                                       /* 16 + 48 */
-    IRQ_Handler,//0,                                       /* 16 + 49 */
-    IRQ_Handler,//PDS_WAKEUP_IRQHandler_Wrapper,           /* 16 + 50 */
-    IRQ_Handler,//HBN_OUT0_IRQHandler_Wrapper,             /* 16 + 51 */
-    IRQ_Handler,//HBN_OUT1_IRQHandler_Wrapper,             /* 16 + 52 */
-    IRQ_Handler,//BOR_IRQHandler_Wrapper,                  /* 16 + 53 */
-    IRQ_Handler,//WIFI_IRQHandler_Wrapper,                 /* 16 + 54 */
-    IRQ_Handler,//BZ_PHY_IRQHandler_Wrapper,               /* 16 + 55 */
-    IRQ_Handler,//BLE_IRQHandler_Wrapper,                  /* 16 + 56 */
-    IRQ_Handler,//MAC_TXRX_TIMER_IRQHandler_Wrapper,       /* 16 + 57 */
-    IRQ_Handler,//MAC_TXRX_MISC_IRQHandler_Wrapper,        /* 16 + 58 */
-    IRQ_Handler,//MAC_RX_TRG_IRQHandler_Wrapper,           /* 16 + 59 */
-    IRQ_Handler,//MAC_TX_TRG_IRQHandler_Wrapper,           /* 16 + 60 */
-    IRQ_Handler,//MAC_GEN_IRQHandler_Wrapper,              /* 16 + 61 */
-    IRQ_Handler,//MAC_PORT_TRG_IRQHandler_Wrapper,         /* 16 + 62 */
-    IRQ_Handler,//WIFI_IPC_PUBLIC_IRQHandler_Wrapper,      /* 16 + 63 */
-};
-
-void trap_c(uint32_t *regs)
-{
-    int i;
-    uint32_t vec = 0;
-
-    vec = __get_MCAUSE() & 0x3FF;
-
-    MSG("CPU Exception: NO.%d", vec);
-    MSG("\n");
-
-    for (i = 0; i < 31; i++) {
-        MSG("x%d: %08x\t", i + 1, regs[i]);
-
-        if ((i % 4) == 3) {
-            MSG("\n");
-        }
-    }
-
-    MSG("\n");
-    MSG("mepc   : %08x\n", regs[31]);
-    MSG("mstatus: %08x\n", regs[32]);
-
-    //if (trap_c_callback) {
-    //    trap_c_callback();
-    //}
-
-    while (1);
-}
-
-void NMI_Handler(void)
-{
-
-    MSG("NMI_Handler\r\n");
-
-    while (1);
-}
-
-void Interrupt_Handler_Register(IRQn_Type irq,pFunc interruptFun)
-{
-    if(irq
-#include 
-
-#define FDT_FIRST_SUPPORTED_VERSION 0x02
-#define FDT_LAST_SUPPORTED_VERSION  0x11
-
-/* Error codes: informative error codes */
-#define FDT_ERR_NOTFOUND    1
-    /* FDT_ERR_NOTFOUND: The requested node or property does not exist */
-#define FDT_ERR_EXISTS      2
-    /* FDT_ERR_EXISTS: Attempted to create a node or property which
-     * already exists */
-#define FDT_ERR_NOSPACE     3
-    /* FDT_ERR_NOSPACE: Operation needed to expand the device
-     * tree, but its buffer did not have sufficient space to
-     * contain the expanded tree. Use fdt_open_into() to move the
-     * device tree to a buffer with more space. */
-
-/* Error codes: codes for bad parameters */
-#define FDT_ERR_BADOFFSET   4
-    /* FDT_ERR_BADOFFSET: Function was passed a structure block
-     * offset which is out-of-bounds, or which points to an
-     * unsuitable part of the structure for the operation. */
-#define FDT_ERR_BADPATH     5
-    /* FDT_ERR_BADPATH: Function was passed a badly formatted path
-     * (e.g. missing a leading / for a function which requires an
-     * absolute path) */
-#define FDT_ERR_BADPHANDLE  6
-    /* FDT_ERR_BADPHANDLE: Function was passed an invalid phandle.
-     * This can be caused either by an invalid phandle property
-     * length, or the phandle value was either 0 or -1, which are
-     * not permitted. */
-#define FDT_ERR_BADSTATE    7
-    /* FDT_ERR_BADSTATE: Function was passed an incomplete device
-     * tree created by the sequential-write functions, which is
-     * not sufficiently complete for the requested operation. */
-
-/* Error codes: codes for bad device tree blobs */
-#define FDT_ERR_TRUNCATED   8
-    /* FDT_ERR_TRUNCATED: FDT or a sub-block is improperly
-     * terminated (overflows, goes outside allowed bounds, or
-     * isn't properly terminated).  */
-#define FDT_ERR_BADMAGIC    9
-    /* FDT_ERR_BADMAGIC: Given "device tree" appears not to be a
-     * device tree at all - it is missing the flattened device
-     * tree magic number. */
-#define FDT_ERR_BADVERSION  10
-    /* FDT_ERR_BADVERSION: Given device tree has a version which
-     * can't be handled by the requested operation.  For
-     * read-write functions, this may mean that fdt_open_into() is
-     * required to convert the tree to the expected version. */
-#define FDT_ERR_BADSTRUCTURE    11
-    /* FDT_ERR_BADSTRUCTURE: Given device tree has a corrupt
-     * structure block or other serious error (e.g. misnested
-     * nodes, or subnodes preceding properties). */
-#define FDT_ERR_BADLAYOUT   12
-    /* FDT_ERR_BADLAYOUT: For read-write functions, the given
-     * device tree has it's sub-blocks in an order that the
-     * function can't handle (memory reserve map, then structure,
-     * then strings).  Use fdt_open_into() to reorganize the tree
-     * into a form suitable for the read-write operations. */
-
-/* "Can't happen" error indicating a bug in libfdt */
-#define FDT_ERR_INTERNAL    13
-    /* FDT_ERR_INTERNAL: libfdt has failed an internal assertion.
-     * Should never be returned, if it is, it indicates a bug in
-     * libfdt itself. */
-
-/* Errors in device tree content */
-#define FDT_ERR_BADNCELLS   14
-    /* FDT_ERR_BADNCELLS: Device tree has a #address-cells, #size-cells
-     * or similar property with a bad format or value */
-
-#define FDT_ERR_BADVALUE    15
-    /* FDT_ERR_BADVALUE: Device tree has a property with an unexpected
-     * value. For example: a property expected to contain a string list
-     * is not NUL-terminated within the length of its value. */
-
-#define FDT_ERR_BADOVERLAY  16
-    /* FDT_ERR_BADOVERLAY: The device tree overlay, while
-     * correctly structured, cannot be applied due to some
-     * unexpected or missing value, property or node. */
-
-#define FDT_ERR_NOPHANDLES  17
-    /* FDT_ERR_NOPHANDLES: The device tree doesn't have any
-     * phandle available anymore without causing an overflow */
-
-#define FDT_ERR_MAX     17
-
-/**********************************************************************/
-/* Low-level functions (you probably don't need these)                */
-/**********************************************************************/
-
-#ifndef SWIG /* This function is not useful in Python */
-const void *fdt_offset_ptr(const void *fdt, int offset, unsigned int checklen);
-#endif
-static inline void *fdt_offset_ptr_w(void *fdt, int offset, int checklen)
-{
-    return (void *)(uintptr_t)fdt_offset_ptr(fdt, offset, checklen);
-}
-
-uint32_t fdt_next_tag(const void *fdt, int offset, int *nextoffset);
-
-/*
- * Alignment helpers:
- *     These helpers access words from a device tree blob.  They're
- *     built to work even with unaligned pointers on platforms (ike
- *     ARM) that don't like unaligned loads and stores
- */
-
-static inline uint32_t fdt32_ld(const fdt32_t *p)
-{
-    const uint8_t *bp = (const uint8_t *)p;
-
-    return ((uint32_t)bp[0] << 24)
-        | ((uint32_t)bp[1] << 16)
-        | ((uint32_t)bp[2] << 8)
-        | bp[3];
-}
-
-static inline uint64_t fdt64_ld(const fdt64_t *p)
-{
-    const uint8_t *bp = (const uint8_t *)p;
-
-    return ((uint64_t)bp[0] << 56)
-        | ((uint64_t)bp[1] << 48)
-        | ((uint64_t)bp[2] << 40)
-        | ((uint64_t)bp[3] << 32)
-        | ((uint64_t)bp[4] << 24)
-        | ((uint64_t)bp[5] << 16)
-        | ((uint64_t)bp[6] << 8)
-        | bp[7];
-}
-
-/**********************************************************************/
-/* Traversal functions                                                */
-/**********************************************************************/
-
-int fdt_next_node(const void *fdt, int offset, int *depth);
-
-/**
- * fdt_first_subnode() - get offset of first direct subnode
- *
- * @fdt:    FDT blob
- * @offset: Offset of node to check
- * @return offset of first subnode, or -FDT_ERR_NOTFOUND if there is none
- */
-int fdt_first_subnode(const void *fdt, int offset);
-
-/**
- * fdt_next_subnode() - get offset of next direct subnode
- *
- * After first calling fdt_first_subnode(), call this function repeatedly to
- * get direct subnodes of a parent node.
- *
- * @fdt:    FDT blob
- * @offset: Offset of previous subnode
- * @return offset of next subnode, or -FDT_ERR_NOTFOUND if there are no more
- * subnodes
- */
-int fdt_next_subnode(const void *fdt, int offset);
-
-/**
- * fdt_for_each_subnode - iterate over all subnodes of a parent
- *
- * @node:   child node (int, lvalue)
- * @fdt:    FDT blob (const void *)
- * @parent: parent node (int)
- *
- * This is actually a wrapper around a for loop and would be used like so:
- *
- *  fdt_for_each_subnode(node, fdt, parent) {
- *      Use node
- *      ...
- *  }
- *
- *  if ((node < 0) && (node != -FDT_ERR_NOTFOUND)) {
- *      Error handling
- *  }
- *
- * Note that this is implemented as a macro and @node is used as
- * iterator in the loop. The parent variable be constant or even a
- * literal.
- *
- */
-#define fdt_for_each_subnode(node, fdt, parent)     \
-    for (node = fdt_first_subnode(fdt, parent); \
-         node >= 0;                 \
-         node = fdt_next_subnode(fdt, node))
-
-/**********************************************************************/
-/* General functions                                                  */
-/**********************************************************************/
-#define fdt_get_header(fdt, field) \
-    (fdt32_ld(&((const struct fdt_header *)(fdt))->field))
-#define fdt_magic(fdt)          (fdt_get_header(fdt, magic))
-#define fdt_totalsize(fdt)      (fdt_get_header(fdt, totalsize))
-#define fdt_off_dt_struct(fdt)      (fdt_get_header(fdt, off_dt_struct))
-#define fdt_off_dt_strings(fdt)     (fdt_get_header(fdt, off_dt_strings))
-#define fdt_off_mem_rsvmap(fdt)     (fdt_get_header(fdt, off_mem_rsvmap))
-#define fdt_version(fdt)        (fdt_get_header(fdt, version))
-#define fdt_last_comp_version(fdt)  (fdt_get_header(fdt, last_comp_version))
-#define fdt_boot_cpuid_phys(fdt)    (fdt_get_header(fdt, boot_cpuid_phys))
-#define fdt_size_dt_strings(fdt)    (fdt_get_header(fdt, size_dt_strings))
-#define fdt_size_dt_struct(fdt)     (fdt_get_header(fdt, size_dt_struct))
-
-#define fdt_set_hdr_(name) \
-    static inline void fdt_set_##name(void *fdt, uint32_t val) \
-    { \
-        struct fdt_header *fdth = (struct fdt_header *)fdt; \
-        fdth->name = cpu_to_fdt32(val); \
-    }
-fdt_set_hdr_(magic);
-fdt_set_hdr_(totalsize);
-fdt_set_hdr_(off_dt_struct);
-fdt_set_hdr_(off_dt_strings);
-fdt_set_hdr_(off_mem_rsvmap);
-fdt_set_hdr_(version);
-fdt_set_hdr_(last_comp_version);
-fdt_set_hdr_(boot_cpuid_phys);
-fdt_set_hdr_(size_dt_strings);
-fdt_set_hdr_(size_dt_struct);
-#undef fdt_set_hdr_
-
-/**
- * fdt_header_size - return the size of the tree's header
- * @fdt: pointer to a flattened device tree
- */
-size_t fdt_header_size_(uint32_t version);
-static inline size_t fdt_header_size(const void *fdt)
-{
-    return fdt_header_size_(fdt_version(fdt));
-}
-
-/**
- * fdt_check_header - sanity check a device tree header
-
- * @fdt: pointer to data which might be a flattened device tree
- *
- * fdt_check_header() checks that the given buffer contains what
- * appears to be a flattened device tree, and that the header contains
- * valid information (to the extent that can be determined from the
- * header alone).
- *
- * returns:
- *     0, if the buffer appears to contain a valid device tree
- *     -FDT_ERR_BADMAGIC,
- *     -FDT_ERR_BADVERSION,
- *     -FDT_ERR_BADSTATE,
- *     -FDT_ERR_TRUNCATED, standard meanings, as above
- */
-int fdt_check_header(const void *fdt);
-
-/**
- * fdt_move - move a device tree around in memory
- * @fdt: pointer to the device tree to move
- * @buf: pointer to memory where the device is to be moved
- * @bufsize: size of the memory space at buf
- *
- * fdt_move() relocates, if possible, the device tree blob located at
- * fdt to the buffer at buf of size bufsize.  The buffer may overlap
- * with the existing device tree blob at fdt.  Therefore,
- *     fdt_move(fdt, fdt, fdt_totalsize(fdt))
- * should always succeed.
- *
- * returns:
- *     0, on success
- *     -FDT_ERR_NOSPACE, bufsize is insufficient to contain the device tree
- *     -FDT_ERR_BADMAGIC,
- *     -FDT_ERR_BADVERSION,
- *     -FDT_ERR_BADSTATE, standard meanings
- */
-int fdt_move(const void *fdt, void *buf, int bufsize);
-
-/**********************************************************************/
-/* Read-only functions                                                */
-/**********************************************************************/
-
-int fdt_check_full(const void *fdt, size_t bufsize);
-
-/**
- * fdt_get_string - retrieve a string from the strings block of a device tree
- * @fdt: pointer to the device tree blob
- * @stroffset: offset of the string within the strings block (native endian)
- * @lenp: optional pointer to return the string's length
- *
- * fdt_get_string() retrieves a pointer to a single string from the
- * strings block of the device tree blob at fdt, and optionally also
- * returns the string's length in *lenp.
- *
- * returns:
- *     a pointer to the string, on success
- *     NULL, if stroffset is out of bounds, or doesn't point to a valid string
- */
-const char *fdt_get_string(const void *fdt, int stroffset, int *lenp);
-
-/**
- * fdt_string - retrieve a string from the strings block of a device tree
- * @fdt: pointer to the device tree blob
- * @stroffset: offset of the string within the strings block (native endian)
- *
- * fdt_string() retrieves a pointer to a single string from the
- * strings block of the device tree blob at fdt.
- *
- * returns:
- *     a pointer to the string, on success
- *     NULL, if stroffset is out of bounds, or doesn't point to a valid string
- */
-const char *fdt_string(const void *fdt, int stroffset);
-
-/**
- * fdt_get_max_phandle - retrieves the highest phandle in a tree
- * @fdt: pointer to the device tree blob
- *
- * fdt_get_max_phandle retrieves the highest phandle in the given
- * device tree. This will ignore badly formatted phandles, or phandles
- * with a value of 0 or -1.
- *
- * returns:
- *      the highest phandle on success
- *      0, if no phandle was found in the device tree
- *      -1, if an error occurred
- */
-uint32_t fdt_get_max_phandle(const void *fdt);
-
-/**
- * fdt_num_mem_rsv - retrieve the number of memory reserve map entries
- * @fdt: pointer to the device tree blob
- *
- * Returns the number of entries in the device tree blob's memory
- * reservation map.  This does not include the terminating 0,0 entry
- * or any other (0,0) entries reserved for expansion.
- *
- * returns:
- *     the number of entries
- */
-int fdt_num_mem_rsv(const void *fdt);
-
-/**
- * fdt_get_mem_rsv - retrieve one memory reserve map entry
- * @fdt: pointer to the device tree blob
- * @address, @size: pointers to 64-bit variables
- *
- * On success, *address and *size will contain the address and size of
- * the n-th reserve map entry from the device tree blob, in
- * native-endian format.
- *
- * returns:
- *     0, on success
- *     -FDT_ERR_BADMAGIC,
- *     -FDT_ERR_BADVERSION,
- *     -FDT_ERR_BADSTATE, standard meanings
- */
-int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size);
-
-/**
- * fdt_subnode_offset_namelen - find a subnode based on substring
- * @fdt: pointer to the device tree blob
- * @parentoffset: structure block offset of a node
- * @name: name of the subnode to locate
- * @namelen: number of characters of name to consider
- *
- * Identical to fdt_subnode_offset(), but only examine the first
- * namelen characters of name for matching the subnode name.  This is
- * useful for finding subnodes based on a portion of a larger string,
- * such as a full path.
- */
-#ifndef SWIG /* Not available in Python */
-int fdt_subnode_offset_namelen(const void *fdt, int parentoffset,
-                   const char *name, int namelen);
-#endif
-/**
- * fdt_subnode_offset - find a subnode of a given node
- * @fdt: pointer to the device tree blob
- * @parentoffset: structure block offset of a node
- * @name: name of the subnode to locate
- *
- * fdt_subnode_offset() finds a subnode of the node at structure block
- * offset parentoffset with the given name.  name may include a unit
- * address, in which case fdt_subnode_offset() will find the subnode
- * with that unit address, or the unit address may be omitted, in
- * which case fdt_subnode_offset() will find an arbitrary subnode
- * whose name excluding unit address matches the given name.
- *
- * returns:
- *  structure block offset of the requested subnode (>=0), on success
- *  -FDT_ERR_NOTFOUND, if the requested subnode does not exist
- *  -FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE
- *      tag
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_TRUNCATED, standard meanings.
- */
-int fdt_subnode_offset(const void *fdt, int parentoffset, const char *name);
-
-/**
- * fdt_path_offset_namelen - find a tree node by its full path
- * @fdt: pointer to the device tree blob
- * @path: full path of the node to locate
- * @namelen: number of characters of path to consider
- *
- * Identical to fdt_path_offset(), but only consider the first namelen
- * characters of path as the path name.
- */
-#ifndef SWIG /* Not available in Python */
-int fdt_path_offset_namelen(const void *fdt, const char *path, int namelen);
-#endif
-
-/**
- * fdt_path_offset - find a tree node by its full path
- * @fdt: pointer to the device tree blob
- * @path: full path of the node to locate
- *
- * fdt_path_offset() finds a node of a given path in the device tree.
- * Each path component may omit the unit address portion, but the
- * results of this are undefined if any such path component is
- * ambiguous (that is if there are multiple nodes at the relevant
- * level matching the given component, differentiated only by unit
- * address).
- *
- * returns:
- *  structure block offset of the node with the requested path (>=0), on
- *      success
- *  -FDT_ERR_BADPATH, given path does not begin with '/' or is invalid
- *  -FDT_ERR_NOTFOUND, if the requested node does not exist
- *      -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_TRUNCATED, standard meanings.
- */
-int fdt_path_offset(const void *fdt, const char *path);
-
-/**
- * fdt_get_name - retrieve the name of a given node
- * @fdt: pointer to the device tree blob
- * @nodeoffset: structure block offset of the starting node
- * @lenp: pointer to an integer variable (will be overwritten) or NULL
- *
- * fdt_get_name() retrieves the name (including unit address) of the
- * device tree node at structure block offset nodeoffset.  If lenp is
- * non-NULL, the length of this name is also returned, in the integer
- * pointed to by lenp.
- *
- * returns:
- *  pointer to the node's name, on success
- *      If lenp is non-NULL, *lenp contains the length of that name
- *          (>=0)
- *  NULL, on error
- *      if lenp is non-NULL *lenp contains an error code (<0):
- *      -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE
- *          tag
- *      -FDT_ERR_BADMAGIC,
- *      -FDT_ERR_BADVERSION,
- *      -FDT_ERR_BADSTATE, standard meanings
- */
-const char *fdt_get_name(const void *fdt, int nodeoffset, int *lenp);
-
-/**
- * fdt_first_property_offset - find the offset of a node's first property
- * @fdt: pointer to the device tree blob
- * @nodeoffset: structure block offset of a node
- *
- * fdt_first_property_offset() finds the first property of the node at
- * the given structure block offset.
- *
- * returns:
- *  structure block offset of the property (>=0), on success
- *  -FDT_ERR_NOTFOUND, if the requested node has no properties
- *  -FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_BEGIN_NODE tag
- *      -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_TRUNCATED, standard meanings.
- */
-int fdt_first_property_offset(const void *fdt, int nodeoffset);
-
-/**
- * fdt_next_property_offset - step through a node's properties
- * @fdt: pointer to the device tree blob
- * @offset: structure block offset of a property
- *
- * fdt_next_property_offset() finds the property immediately after the
- * one at the given structure block offset.  This will be a property
- * of the same node as the given property.
- *
- * returns:
- *  structure block offset of the next property (>=0), on success
- *  -FDT_ERR_NOTFOUND, if the given property is the last in its node
- *  -FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_PROP tag
- *      -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_TRUNCATED, standard meanings.
- */
-int fdt_next_property_offset(const void *fdt, int offset);
-
-/**
- * fdt_for_each_property_offset - iterate over all properties of a node
- *
- * @property_offset:    property offset (int, lvalue)
- * @fdt:        FDT blob (const void *)
- * @node:       node offset (int)
- *
- * This is actually a wrapper around a for loop and would be used like so:
- *
- *  fdt_for_each_property_offset(property, fdt, node) {
- *      Use property
- *      ...
- *  }
- *
- *  if ((property < 0) && (property != -FDT_ERR_NOTFOUND)) {
- *      Error handling
- *  }
- *
- * Note that this is implemented as a macro and property is used as
- * iterator in the loop. The node variable can be constant or even a
- * literal.
- */
-#define fdt_for_each_property_offset(property, fdt, node)   \
-    for (property = fdt_first_property_offset(fdt, node);   \
-         property >= 0;                 \
-         property = fdt_next_property_offset(fdt, property))
-
-/**
- * fdt_get_property_by_offset - retrieve the property at a given offset
- * @fdt: pointer to the device tree blob
- * @offset: offset of the property to retrieve
- * @lenp: pointer to an integer variable (will be overwritten) or NULL
- *
- * fdt_get_property_by_offset() retrieves a pointer to the
- * fdt_property structure within the device tree blob at the given
- * offset.  If lenp is non-NULL, the length of the property value is
- * also returned, in the integer pointed to by lenp.
- *
- * Note that this code only works on device tree versions >= 16. fdt_getprop()
- * works on all versions.
- *
- * returns:
- *  pointer to the structure representing the property
- *      if lenp is non-NULL, *lenp contains the length of the property
- *      value (>=0)
- *  NULL, on error
- *      if lenp is non-NULL, *lenp contains an error code (<0):
- *      -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag
- *      -FDT_ERR_BADMAGIC,
- *      -FDT_ERR_BADVERSION,
- *      -FDT_ERR_BADSTATE,
- *      -FDT_ERR_BADSTRUCTURE,
- *      -FDT_ERR_TRUNCATED, standard meanings
- */
-const struct fdt_property *fdt_get_property_by_offset(const void *fdt,
-                              int offset,
-                              int *lenp);
-
-/**
- * fdt_get_property_namelen - find a property based on substring
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to find
- * @name: name of the property to find
- * @namelen: number of characters of name to consider
- * @lenp: pointer to an integer variable (will be overwritten) or NULL
- *
- * Identical to fdt_get_property(), but only examine the first namelen
- * characters of name for matching the property name.
- */
-#ifndef SWIG /* Not available in Python */
-const struct fdt_property *fdt_get_property_namelen(const void *fdt,
-                            int nodeoffset,
-                            const char *name,
-                            int namelen, int *lenp);
-#endif
-
-/**
- * fdt_get_property - find a given property in a given node
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to find
- * @name: name of the property to find
- * @lenp: pointer to an integer variable (will be overwritten) or NULL
- *
- * fdt_get_property() retrieves a pointer to the fdt_property
- * structure within the device tree blob corresponding to the property
- * named 'name' of the node at offset nodeoffset.  If lenp is
- * non-NULL, the length of the property value is also returned, in the
- * integer pointed to by lenp.
- *
- * returns:
- *  pointer to the structure representing the property
- *      if lenp is non-NULL, *lenp contains the length of the property
- *      value (>=0)
- *  NULL, on error
- *      if lenp is non-NULL, *lenp contains an error code (<0):
- *      -FDT_ERR_NOTFOUND, node does not have named property
- *      -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE
- *          tag
- *      -FDT_ERR_BADMAGIC,
- *      -FDT_ERR_BADVERSION,
- *      -FDT_ERR_BADSTATE,
- *      -FDT_ERR_BADSTRUCTURE,
- *      -FDT_ERR_TRUNCATED, standard meanings
- */
-const struct fdt_property *fdt_get_property(const void *fdt, int nodeoffset,
-                        const char *name, int *lenp);
-static inline struct fdt_property *fdt_get_property_w(void *fdt, int nodeoffset,
-                              const char *name,
-                              int *lenp)
-{
-    return (struct fdt_property *)(uintptr_t)
-        fdt_get_property(fdt, nodeoffset, name, lenp);
-}
-
-/**
- * fdt_getprop_by_offset - retrieve the value of a property at a given offset
- * @fdt: pointer to the device tree blob
- * @offset: offset of the property to read
- * @namep: pointer to a string variable (will be overwritten) or NULL
- * @lenp: pointer to an integer variable (will be overwritten) or NULL
- *
- * fdt_getprop_by_offset() retrieves a pointer to the value of the
- * property at structure block offset 'offset' (this will be a pointer
- * to within the device blob itself, not a copy of the value).  If
- * lenp is non-NULL, the length of the property value is also
- * returned, in the integer pointed to by lenp.  If namep is non-NULL,
- * the property's namne will also be returned in the char * pointed to
- * by namep (this will be a pointer to within the device tree's string
- * block, not a new copy of the name).
- *
- * returns:
- *  pointer to the property's value
- *      if lenp is non-NULL, *lenp contains the length of the property
- *      value (>=0)
- *      if namep is non-NULL *namep contiains a pointer to the property
- *      name.
- *  NULL, on error
- *      if lenp is non-NULL, *lenp contains an error code (<0):
- *      -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag
- *      -FDT_ERR_BADMAGIC,
- *      -FDT_ERR_BADVERSION,
- *      -FDT_ERR_BADSTATE,
- *      -FDT_ERR_BADSTRUCTURE,
- *      -FDT_ERR_TRUNCATED, standard meanings
- */
-#ifndef SWIG /* This function is not useful in Python */
-const void *fdt_getprop_by_offset(const void *fdt, int offset,
-                  const char **namep, int *lenp);
-#endif
-
-/**
- * fdt_getprop_namelen - get property value based on substring
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to find
- * @name: name of the property to find
- * @namelen: number of characters of name to consider
- * @lenp: pointer to an integer variable (will be overwritten) or NULL
- *
- * Identical to fdt_getprop(), but only examine the first namelen
- * characters of name for matching the property name.
- */
-#ifndef SWIG /* Not available in Python */
-const void *fdt_getprop_namelen(const void *fdt, int nodeoffset,
-                const char *name, int namelen, int *lenp);
-static inline void *fdt_getprop_namelen_w(void *fdt, int nodeoffset,
-                      const char *name, int namelen,
-                      int *lenp)
-{
-    return (void *)(uintptr_t)fdt_getprop_namelen(fdt, nodeoffset, name,
-                              namelen, lenp);
-}
-#endif
-
-/**
- * fdt_getprop - retrieve the value of a given property
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to find
- * @name: name of the property to find
- * @lenp: pointer to an integer variable (will be overwritten) or NULL
- *
- * fdt_getprop() retrieves a pointer to the value of the property
- * named 'name' of the node at offset nodeoffset (this will be a
- * pointer to within the device blob itself, not a copy of the value).
- * If lenp is non-NULL, the length of the property value is also
- * returned, in the integer pointed to by lenp.
- *
- * returns:
- *  pointer to the property's value
- *      if lenp is non-NULL, *lenp contains the length of the property
- *      value (>=0)
- *  NULL, on error
- *      if lenp is non-NULL, *lenp contains an error code (<0):
- *      -FDT_ERR_NOTFOUND, node does not have named property
- *      -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE
- *          tag
- *      -FDT_ERR_BADMAGIC,
- *      -FDT_ERR_BADVERSION,
- *      -FDT_ERR_BADSTATE,
- *      -FDT_ERR_BADSTRUCTURE,
- *      -FDT_ERR_TRUNCATED, standard meanings
- */
-const void *fdt_getprop(const void *fdt, int nodeoffset,
-            const char *name, int *lenp);
-static inline void *fdt_getprop_w(void *fdt, int nodeoffset,
-                  const char *name, int *lenp)
-{
-    return (void *)(uintptr_t)fdt_getprop(fdt, nodeoffset, name, lenp);
-}
-
-/**
- * fdt_get_phandle - retrieve the phandle of a given node
- * @fdt: pointer to the device tree blob
- * @nodeoffset: structure block offset of the node
- *
- * fdt_get_phandle() retrieves the phandle of the device tree node at
- * structure block offset nodeoffset.
- *
- * returns:
- *  the phandle of the node at nodeoffset, on success (!= 0, != -1)
- *  0, if the node has no phandle, or another error occurs
- */
-uint32_t fdt_get_phandle(const void *fdt, int nodeoffset);
-
-/**
- * fdt_get_alias_namelen - get alias based on substring
- * @fdt: pointer to the device tree blob
- * @name: name of the alias th look up
- * @namelen: number of characters of name to consider
- *
- * Identical to fdt_get_alias(), but only examine the first namelen
- * characters of name for matching the alias name.
- */
-#ifndef SWIG /* Not available in Python */
-const char *fdt_get_alias_namelen(const void *fdt,
-                  const char *name, int namelen);
-#endif
-
-/**
- * fdt_get_alias - retrieve the path referenced by a given alias
- * @fdt: pointer to the device tree blob
- * @name: name of the alias th look up
- *
- * fdt_get_alias() retrieves the value of a given alias.  That is, the
- * value of the property named 'name' in the node /aliases.
- *
- * returns:
- *  a pointer to the expansion of the alias named 'name', if it exists
- *  NULL, if the given alias or the /aliases node does not exist
- */
-const char *fdt_get_alias(const void *fdt, const char *name);
-
-/**
- * fdt_get_path - determine the full path of a node
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose path to find
- * @buf: character buffer to contain the returned path (will be overwritten)
- * @buflen: size of the character buffer at buf
- *
- * fdt_get_path() computes the full path of the node at offset
- * nodeoffset, and records that path in the buffer at buf.
- *
- * NOTE: This function is expensive, as it must scan the device tree
- * structure from the start to nodeoffset.
- *
- * returns:
- *  0, on success
- *      buf contains the absolute path of the node at
- *      nodeoffset, as a NUL-terminated string.
- *  -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
- *  -FDT_ERR_NOSPACE, the path of the given node is longer than (bufsize-1)
- *      characters and will not fit in the given buffer.
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE, standard meanings
- */
-int fdt_get_path(const void *fdt, int nodeoffset, char *buf, int buflen);
-
-/**
- * fdt_supernode_atdepth_offset - find a specific ancestor of a node
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose parent to find
- * @supernodedepth: depth of the ancestor to find
- * @nodedepth: pointer to an integer variable (will be overwritten) or NULL
- *
- * fdt_supernode_atdepth_offset() finds an ancestor of the given node
- * at a specific depth from the root (where the root itself has depth
- * 0, its immediate subnodes depth 1 and so forth).  So
- *  fdt_supernode_atdepth_offset(fdt, nodeoffset, 0, NULL);
- * will always return 0, the offset of the root node.  If the node at
- * nodeoffset has depth D, then:
- *  fdt_supernode_atdepth_offset(fdt, nodeoffset, D, NULL);
- * will return nodeoffset itself.
- *
- * NOTE: This function is expensive, as it must scan the device tree
- * structure from the start to nodeoffset.
- *
- * returns:
- *  structure block offset of the node at node offset's ancestor
- *      of depth supernodedepth (>=0), on success
- *  -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
- *  -FDT_ERR_NOTFOUND, supernodedepth was greater than the depth of
- *      nodeoffset
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE, standard meanings
- */
-int fdt_supernode_atdepth_offset(const void *fdt, int nodeoffset,
-                 int supernodedepth, int *nodedepth);
-
-/**
- * fdt_node_depth - find the depth of a given node
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose parent to find
- *
- * fdt_node_depth() finds the depth of a given node.  The root node
- * has depth 0, its immediate subnodes depth 1 and so forth.
- *
- * NOTE: This function is expensive, as it must scan the device tree
- * structure from the start to nodeoffset.
- *
- * returns:
- *  depth of the node at nodeoffset (>=0), on success
- *  -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE, standard meanings
- */
-int fdt_node_depth(const void *fdt, int nodeoffset);
-
-/**
- * fdt_parent_offset - find the parent of a given node
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose parent to find
- *
- * fdt_parent_offset() locates the parent node of a given node (that
- * is, it finds the offset of the node which contains the node at
- * nodeoffset as a subnode).
- *
- * NOTE: This function is expensive, as it must scan the device tree
- * structure from the start to nodeoffset, *twice*.
- *
- * returns:
- *  structure block offset of the parent of the node at nodeoffset
- *      (>=0), on success
- *  -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE, standard meanings
- */
-int fdt_parent_offset(const void *fdt, int nodeoffset);
-
-/**
- * fdt_node_offset_by_prop_value - find nodes with a given property value
- * @fdt: pointer to the device tree blob
- * @startoffset: only find nodes after this offset
- * @propname: property name to check
- * @propval: property value to search for
- * @proplen: length of the value in propval
- *
- * fdt_node_offset_by_prop_value() returns the offset of the first
- * node after startoffset, which has a property named propname whose
- * value is of length proplen and has value equal to propval; or if
- * startoffset is -1, the very first such node in the tree.
- *
- * To iterate through all nodes matching the criterion, the following
- * idiom can be used:
- *  offset = fdt_node_offset_by_prop_value(fdt, -1, propname,
- *                         propval, proplen);
- *  while (offset != -FDT_ERR_NOTFOUND) {
- *      // other code here
- *      offset = fdt_node_offset_by_prop_value(fdt, offset, propname,
- *                             propval, proplen);
- *  }
- *
- * Note the -1 in the first call to the function, if 0 is used here
- * instead, the function will never locate the root node, even if it
- * matches the criterion.
- *
- * returns:
- *  structure block offset of the located node (>= 0, >startoffset),
- *       on success
- *  -FDT_ERR_NOTFOUND, no node matching the criterion exists in the
- *      tree after startoffset
- *  -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE, standard meanings
- */
-int fdt_node_offset_by_prop_value(const void *fdt, int startoffset,
-                  const char *propname,
-                  const void *propval, int proplen);
-
-/**
- * fdt_node_offset_by_phandle - find the node with a given phandle
- * @fdt: pointer to the device tree blob
- * @phandle: phandle value
- *
- * fdt_node_offset_by_phandle() returns the offset of the node
- * which has the given phandle value.  If there is more than one node
- * in the tree with the given phandle (an invalid tree), results are
- * undefined.
- *
- * returns:
- *  structure block offset of the located node (>= 0), on success
- *  -FDT_ERR_NOTFOUND, no node with that phandle exists
- *  -FDT_ERR_BADPHANDLE, given phandle value was invalid (0 or -1)
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE, standard meanings
- */
-int fdt_node_offset_by_phandle(const void *fdt, uint32_t phandle);
-
-/**
- * fdt_node_check_compatible: check a node's compatible property
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of a tree node
- * @compatible: string to match against
- *
- *
- * fdt_node_check_compatible() returns 0 if the given node contains a
- * 'compatible' property with the given string as one of its elements,
- * it returns non-zero otherwise, or on error.
- *
- * returns:
- *  0, if the node has a 'compatible' property listing the given string
- *  1, if the node has a 'compatible' property, but it does not list
- *      the given string
- *  -FDT_ERR_NOTFOUND, if the given node has no 'compatible' property
- *  -FDT_ERR_BADOFFSET, if nodeoffset does not refer to a BEGIN_NODE tag
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE, standard meanings
- */
-int fdt_node_check_compatible(const void *fdt, int nodeoffset,
-                  const char *compatible);
-
-/**
- * fdt_node_offset_by_compatible - find nodes with a given 'compatible' value
- * @fdt: pointer to the device tree blob
- * @startoffset: only find nodes after this offset
- * @compatible: 'compatible' string to match against
- *
- * fdt_node_offset_by_compatible() returns the offset of the first
- * node after startoffset, which has a 'compatible' property which
- * lists the given compatible string; or if startoffset is -1, the
- * very first such node in the tree.
- *
- * To iterate through all nodes matching the criterion, the following
- * idiom can be used:
- *  offset = fdt_node_offset_by_compatible(fdt, -1, compatible);
- *  while (offset != -FDT_ERR_NOTFOUND) {
- *      // other code here
- *      offset = fdt_node_offset_by_compatible(fdt, offset, compatible);
- *  }
- *
- * Note the -1 in the first call to the function, if 0 is used here
- * instead, the function will never locate the root node, even if it
- * matches the criterion.
- *
- * returns:
- *  structure block offset of the located node (>= 0, >startoffset),
- *       on success
- *  -FDT_ERR_NOTFOUND, no node matching the criterion exists in the
- *      tree after startoffset
- *  -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE, standard meanings
- */
-int fdt_node_offset_by_compatible(const void *fdt, int startoffset,
-                  const char *compatible);
-
-/**
- * fdt_stringlist_contains - check a string list property for a string
- * @strlist: Property containing a list of strings to check
- * @listlen: Length of property
- * @str: String to search for
- *
- * This is a utility function provided for convenience. The list contains
- * one or more strings, each terminated by \0, as is found in a device tree
- * "compatible" property.
- *
- * @return: 1 if the string is found in the list, 0 not found, or invalid list
- */
-int fdt_stringlist_contains(const char *strlist, int listlen, const char *str);
-
-/**
- * fdt_stringlist_count - count the number of strings in a string list
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of a tree node
- * @property: name of the property containing the string list
- * @return:
- *   the number of strings in the given property
- *   -FDT_ERR_BADVALUE if the property value is not NUL-terminated
- *   -FDT_ERR_NOTFOUND if the property does not exist
- */
-int fdt_stringlist_count(const void *fdt, int nodeoffset, const char *property);
-
-/**
- * fdt_stringlist_search - find a string in a string list and return its index
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of a tree node
- * @property: name of the property containing the string list
- * @string: string to look up in the string list
- *
- * Note that it is possible for this function to succeed on property values
- * that are not NUL-terminated. That's because the function will stop after
- * finding the first occurrence of @string. This can for example happen with
- * small-valued cell properties, such as #address-cells, when searching for
- * the empty string.
- *
- * @return:
- *   the index of the string in the list of strings
- *   -FDT_ERR_BADVALUE if the property value is not NUL-terminated
- *   -FDT_ERR_NOTFOUND if the property does not exist or does not contain
- *                     the given string
- */
-int fdt_stringlist_search(const void *fdt, int nodeoffset, const char *property,
-              const char *string);
-
-/**
- * fdt_stringlist_get() - obtain the string at a given index in a string list
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of a tree node
- * @property: name of the property containing the string list
- * @index: index of the string to return
- * @lenp: return location for the string length or an error code on failure
- *
- * Note that this will successfully extract strings from properties with
- * non-NUL-terminated values. For example on small-valued cell properties
- * this function will return the empty string.
- *
- * If non-NULL, the length of the string (on success) or a negative error-code
- * (on failure) will be stored in the integer pointer to by lenp.
- *
- * @return:
- *   A pointer to the string at the given index in the string list or NULL on
- *   failure. On success the length of the string will be stored in the memory
- *   location pointed to by the lenp parameter, if non-NULL. On failure one of
- *   the following negative error codes will be returned in the lenp parameter
- *   (if non-NULL):
- *     -FDT_ERR_BADVALUE if the property value is not NUL-terminated
- *     -FDT_ERR_NOTFOUND if the property does not exist
- */
-const char *fdt_stringlist_get(const void *fdt, int nodeoffset,
-                   const char *property, int index,
-                   int *lenp);
-
-/**********************************************************************/
-/* Read-only functions (addressing related)                           */
-/**********************************************************************/
-
-/**
- * FDT_MAX_NCELLS - maximum value for #address-cells and #size-cells
- *
- * This is the maximum value for #address-cells, #size-cells and
- * similar properties that will be processed by libfdt.  IEE1275
- * requires that OF implementations handle values up to 4.
- * Implementations may support larger values, but in practice higher
- * values aren't used.
- */
-#define FDT_MAX_NCELLS      4
-
-/**
- * fdt_address_cells - retrieve address size for a bus represented in the tree
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node to find the address size for
- *
- * When the node has a valid #address-cells property, returns its value.
- *
- * returns:
- *  0 <= n < FDT_MAX_NCELLS, on success
- *      2, if the node has no #address-cells property
- *      -FDT_ERR_BADNCELLS, if the node has a badly formatted or invalid
- *      #address-cells property
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_TRUNCATED, standard meanings
- */
-int fdt_address_cells(const void *fdt, int nodeoffset);
-
-/**
- * fdt_size_cells - retrieve address range size for a bus represented in the
- *                  tree
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node to find the address range size for
- *
- * When the node has a valid #size-cells property, returns its value.
- *
- * returns:
- *  0 <= n < FDT_MAX_NCELLS, on success
- *      1, if the node has no #size-cells property
- *      -FDT_ERR_BADNCELLS, if the node has a badly formatted or invalid
- *      #size-cells property
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_TRUNCATED, standard meanings
- */
-int fdt_size_cells(const void *fdt, int nodeoffset);
-
-
-/**********************************************************************/
-/* Write-in-place functions                                           */
-/**********************************************************************/
-
-/**
- * fdt_setprop_inplace_namelen_partial - change a property's value,
- *                                       but not its size
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to change
- * @name: name of the property to change
- * @namelen: number of characters of name to consider
- * @idx: index of the property to change in the array
- * @val: pointer to data to replace the property value with
- * @len: length of the property value
- *
- * Identical to fdt_setprop_inplace(), but modifies the given property
- * starting from the given index, and using only the first characters
- * of the name. It is useful when you want to manipulate only one value of
- * an array and you have a string that doesn't end with \0.
- */
-#ifndef SWIG /* Not available in Python */
-int fdt_setprop_inplace_namelen_partial(void *fdt, int nodeoffset,
-                    const char *name, int namelen,
-                    uint32_t idx, const void *val,
-                    int len);
-#endif
-
-/**
- * fdt_setprop_inplace - change a property's value, but not its size
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to change
- * @name: name of the property to change
- * @val: pointer to data to replace the property value with
- * @len: length of the property value
- *
- * fdt_setprop_inplace() replaces the value of a given property with
- * the data in val, of length len.  This function cannot change the
- * size of a property, and so will only work if len is equal to the
- * current length of the property.
- *
- * This function will alter only the bytes in the blob which contain
- * the given property value, and will not alter or move any other part
- * of the tree.
- *
- * returns:
- *  0, on success
- *  -FDT_ERR_NOSPACE, if len is not equal to the property's current length
- *  -FDT_ERR_NOTFOUND, node does not have the named property
- *  -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_TRUNCATED, standard meanings
- */
-#ifndef SWIG /* Not available in Python */
-int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name,
-            const void *val, int len);
-#endif
-
-/**
- * fdt_setprop_inplace_u32 - change the value of a 32-bit integer property
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to change
- * @name: name of the property to change
- * @val: 32-bit integer value to replace the property with
- *
- * fdt_setprop_inplace_u32() replaces the value of a given property
- * with the 32-bit integer value in val, converting val to big-endian
- * if necessary.  This function cannot change the size of a property,
- * and so will only work if the property already exists and has length
- * 4.
- *
- * This function will alter only the bytes in the blob which contain
- * the given property value, and will not alter or move any other part
- * of the tree.
- *
- * returns:
- *  0, on success
- *  -FDT_ERR_NOSPACE, if the property's length is not equal to 4
- *  -FDT_ERR_NOTFOUND, node does not have the named property
- *  -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_TRUNCATED, standard meanings
- */
-static inline int fdt_setprop_inplace_u32(void *fdt, int nodeoffset,
-                      const char *name, uint32_t val)
-{
-    fdt32_t tmp = cpu_to_fdt32(val);
-    return fdt_setprop_inplace(fdt, nodeoffset, name, &tmp, sizeof(tmp));
-}
-
-/**
- * fdt_setprop_inplace_u64 - change the value of a 64-bit integer property
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to change
- * @name: name of the property to change
- * @val: 64-bit integer value to replace the property with
- *
- * fdt_setprop_inplace_u64() replaces the value of a given property
- * with the 64-bit integer value in val, converting val to big-endian
- * if necessary.  This function cannot change the size of a property,
- * and so will only work if the property already exists and has length
- * 8.
- *
- * This function will alter only the bytes in the blob which contain
- * the given property value, and will not alter or move any other part
- * of the tree.
- *
- * returns:
- *  0, on success
- *  -FDT_ERR_NOSPACE, if the property's length is not equal to 8
- *  -FDT_ERR_NOTFOUND, node does not have the named property
- *  -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_TRUNCATED, standard meanings
- */
-static inline int fdt_setprop_inplace_u64(void *fdt, int nodeoffset,
-                      const char *name, uint64_t val)
-{
-    fdt64_t tmp = cpu_to_fdt64(val);
-    return fdt_setprop_inplace(fdt, nodeoffset, name, &tmp, sizeof(tmp));
-}
-
-/**
- * fdt_setprop_inplace_cell - change the value of a single-cell property
- *
- * This is an alternative name for fdt_setprop_inplace_u32()
- */
-static inline int fdt_setprop_inplace_cell(void *fdt, int nodeoffset,
-                       const char *name, uint32_t val)
-{
-    return fdt_setprop_inplace_u32(fdt, nodeoffset, name, val);
-}
-
-/**
- * fdt_nop_property - replace a property with nop tags
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to nop
- * @name: name of the property to nop
- *
- * fdt_nop_property() will replace a given property's representation
- * in the blob with FDT_NOP tags, effectively removing it from the
- * tree.
- *
- * This function will alter only the bytes in the blob which contain
- * the property, and will not alter or move any other part of the
- * tree.
- *
- * returns:
- *  0, on success
- *  -FDT_ERR_NOTFOUND, node does not have the named property
- *  -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_TRUNCATED, standard meanings
- */
-int fdt_nop_property(void *fdt, int nodeoffset, const char *name);
-
-/**
- * fdt_nop_node - replace a node (subtree) with nop tags
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node to nop
- *
- * fdt_nop_node() will replace a given node's representation in the
- * blob, including all its subnodes, if any, with FDT_NOP tags,
- * effectively removing it from the tree.
- *
- * This function will alter only the bytes in the blob which contain
- * the node and its properties and subnodes, and will not alter or
- * move any other part of the tree.
- *
- * returns:
- *  0, on success
- *  -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_TRUNCATED, standard meanings
- */
-int fdt_nop_node(void *fdt, int nodeoffset);
-
-/**********************************************************************/
-/* Sequential write functions                                         */
-/**********************************************************************/
-
-int fdt_create(void *buf, int bufsize);
-int fdt_resize(void *fdt, void *buf, int bufsize);
-int fdt_add_reservemap_entry(void *fdt, uint64_t addr, uint64_t size);
-int fdt_finish_reservemap(void *fdt);
-int fdt_begin_node(void *fdt, const char *name);
-int fdt_property(void *fdt, const char *name, const void *val, int len);
-static inline int fdt_property_u32(void *fdt, const char *name, uint32_t val)
-{
-    fdt32_t tmp = cpu_to_fdt32(val);
-    return fdt_property(fdt, name, &tmp, sizeof(tmp));
-}
-static inline int fdt_property_u64(void *fdt, const char *name, uint64_t val)
-{
-    fdt64_t tmp = cpu_to_fdt64(val);
-    return fdt_property(fdt, name, &tmp, sizeof(tmp));
-}
-
-#ifndef SWIG /* Not available in Python */
-static inline int fdt_property_cell(void *fdt, const char *name, uint32_t val)
-{
-    return fdt_property_u32(fdt, name, val);
-}
-#endif
-
-/**
- * fdt_property_placeholder - add a new property and return a ptr to its value
- *
- * @fdt: pointer to the device tree blob
- * @name: name of property to add
- * @len: length of property value in bytes
- * @valp: returns a pointer to where where the value should be placed
- *
- * returns:
- *  0, on success
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_NOSPACE, standard meanings
- */
-int fdt_property_placeholder(void *fdt, const char *name, int len, void **valp);
-
-#define fdt_property_string(fdt, name, str) \
-    fdt_property(fdt, name, str, strlen(str)+1)
-int fdt_end_node(void *fdt);
-int fdt_finish(void *fdt);
-
-/**********************************************************************/
-/* Read-write functions                                               */
-/**********************************************************************/
-
-int fdt_create_empty_tree(void *buf, int bufsize);
-int fdt_open_into(const void *fdt, void *buf, int bufsize);
-int fdt_pack(void *fdt);
-
-/**
- * fdt_add_mem_rsv - add one memory reserve map entry
- * @fdt: pointer to the device tree blob
- * @address, @size: 64-bit values (native endian)
- *
- * Adds a reserve map entry to the given blob reserving a region at
- * address address of length size.
- *
- * This function will insert data into the reserve map and will
- * therefore change the indexes of some entries in the table.
- *
- * returns:
- *  0, on success
- *  -FDT_ERR_NOSPACE, there is insufficient free space in the blob to
- *      contain the new reservation entry
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_TRUNCATED, standard meanings
- */
-int fdt_add_mem_rsv(void *fdt, uint64_t address, uint64_t size);
-
-/**
- * fdt_del_mem_rsv - remove a memory reserve map entry
- * @fdt: pointer to the device tree blob
- * @n: entry to remove
- *
- * fdt_del_mem_rsv() removes the n-th memory reserve map entry from
- * the blob.
- *
- * This function will delete data from the reservation table and will
- * therefore change the indexes of some entries in the table.
- *
- * returns:
- *  0, on success
- *  -FDT_ERR_NOTFOUND, there is no entry of the given index (i.e. there
- *      are less than n+1 reserve map entries)
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_TRUNCATED, standard meanings
- */
-int fdt_del_mem_rsv(void *fdt, int n);
-
-/**
- * fdt_set_name - change the name of a given node
- * @fdt: pointer to the device tree blob
- * @nodeoffset: structure block offset of a node
- * @name: name to give the node
- *
- * fdt_set_name() replaces the name (including unit address, if any)
- * of the given node with the given string.  NOTE: this function can't
- * efficiently check if the new name is unique amongst the given
- * node's siblings; results are undefined if this function is invoked
- * with a name equal to one of the given node's siblings.
- *
- * This function may insert or delete data from the blob, and will
- * therefore change the offsets of some existing nodes.
- *
- * returns:
- *  0, on success
- *  -FDT_ERR_NOSPACE, there is insufficient free space in the blob
- *      to contain the new name
- *  -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE, standard meanings
- */
-int fdt_set_name(void *fdt, int nodeoffset, const char *name);
-
-/**
- * fdt_setprop - create or change a property
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to change
- * @name: name of the property to change
- * @val: pointer to data to set the property value to
- * @len: length of the property value
- *
- * fdt_setprop() sets the value of the named property in the given
- * node to the given value and length, creating the property if it
- * does not already exist.
- *
- * This function may insert or delete data from the blob, and will
- * therefore change the offsets of some existing nodes.
- *
- * returns:
- *  0, on success
- *  -FDT_ERR_NOSPACE, there is insufficient free space in the blob to
- *      contain the new property value
- *  -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_TRUNCATED, standard meanings
- */
-int fdt_setprop(void *fdt, int nodeoffset, const char *name,
-        const void *val, int len);
-
-/**
- * fdt_setprop_placeholder - allocate space for a property
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to change
- * @name: name of the property to change
- * @len: length of the property value
- * @prop_data: return pointer to property data
- *
- * fdt_setprop_placeholer() allocates the named property in the given node.
- * If the property exists it is resized. In either case a pointer to the
- * property data is returned.
- *
- * This function may insert or delete data from the blob, and will
- * therefore change the offsets of some existing nodes.
- *
- * returns:
- *  0, on success
- *  -FDT_ERR_NOSPACE, there is insufficient free space in the blob to
- *      contain the new property value
- *  -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_TRUNCATED, standard meanings
- */
-int fdt_setprop_placeholder(void *fdt, int nodeoffset, const char *name,
-                int len, void **prop_data);
-
-/**
- * fdt_setprop_u32 - set a property to a 32-bit integer
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to change
- * @name: name of the property to change
- * @val: 32-bit integer value for the property (native endian)
- *
- * fdt_setprop_u32() sets the value of the named property in the given
- * node to the given 32-bit integer value (converting to big-endian if
- * necessary), or creates a new property with that value if it does
- * not already exist.
- *
- * This function may insert or delete data from the blob, and will
- * therefore change the offsets of some existing nodes.
- *
- * returns:
- *  0, on success
- *  -FDT_ERR_NOSPACE, there is insufficient free space in the blob to
- *      contain the new property value
- *  -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_TRUNCATED, standard meanings
- */
-static inline int fdt_setprop_u32(void *fdt, int nodeoffset, const char *name,
-                  uint32_t val)
-{
-    fdt32_t tmp = cpu_to_fdt32(val);
-    return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp));
-}
-
-/**
- * fdt_setprop_u64 - set a property to a 64-bit integer
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to change
- * @name: name of the property to change
- * @val: 64-bit integer value for the property (native endian)
- *
- * fdt_setprop_u64() sets the value of the named property in the given
- * node to the given 64-bit integer value (converting to big-endian if
- * necessary), or creates a new property with that value if it does
- * not already exist.
- *
- * This function may insert or delete data from the blob, and will
- * therefore change the offsets of some existing nodes.
- *
- * returns:
- *  0, on success
- *  -FDT_ERR_NOSPACE, there is insufficient free space in the blob to
- *      contain the new property value
- *  -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_TRUNCATED, standard meanings
- */
-static inline int fdt_setprop_u64(void *fdt, int nodeoffset, const char *name,
-                  uint64_t val)
-{
-    fdt64_t tmp = cpu_to_fdt64(val);
-    return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp));
-}
-
-/**
- * fdt_setprop_cell - set a property to a single cell value
- *
- * This is an alternative name for fdt_setprop_u32()
- */
-static inline int fdt_setprop_cell(void *fdt, int nodeoffset, const char *name,
-                   uint32_t val)
-{
-    return fdt_setprop_u32(fdt, nodeoffset, name, val);
-}
-
-/**
- * fdt_setprop_string - set a property to a string value
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to change
- * @name: name of the property to change
- * @str: string value for the property
- *
- * fdt_setprop_string() sets the value of the named property in the
- * given node to the given string value (using the length of the
- * string to determine the new length of the property), or creates a
- * new property with that value if it does not already exist.
- *
- * This function may insert or delete data from the blob, and will
- * therefore change the offsets of some existing nodes.
- *
- * returns:
- *  0, on success
- *  -FDT_ERR_NOSPACE, there is insufficient free space in the blob to
- *      contain the new property value
- *  -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_TRUNCATED, standard meanings
- */
-#define fdt_setprop_string(fdt, nodeoffset, name, str) \
-    fdt_setprop((fdt), (nodeoffset), (name), (str), strlen(str)+1)
-
-
-/**
- * fdt_setprop_empty - set a property to an empty value
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to change
- * @name: name of the property to change
- *
- * fdt_setprop_empty() sets the value of the named property in the
- * given node to an empty (zero length) value, or creates a new empty
- * property if it does not already exist.
- *
- * This function may insert or delete data from the blob, and will
- * therefore change the offsets of some existing nodes.
- *
- * returns:
- *  0, on success
- *  -FDT_ERR_NOSPACE, there is insufficient free space in the blob to
- *      contain the new property value
- *  -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_TRUNCATED, standard meanings
- */
-#define fdt_setprop_empty(fdt, nodeoffset, name) \
-    fdt_setprop((fdt), (nodeoffset), (name), NULL, 0)
-
-/**
- * fdt_appendprop - append to or create a property
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to change
- * @name: name of the property to append to
- * @val: pointer to data to append to the property value
- * @len: length of the data to append to the property value
- *
- * fdt_appendprop() appends the value to the named property in the
- * given node, creating the property if it does not already exist.
- *
- * This function may insert data into the blob, and will therefore
- * change the offsets of some existing nodes.
- *
- * returns:
- *  0, on success
- *  -FDT_ERR_NOSPACE, there is insufficient free space in the blob to
- *      contain the new property value
- *  -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_TRUNCATED, standard meanings
- */
-int fdt_appendprop(void *fdt, int nodeoffset, const char *name,
-           const void *val, int len);
-
-/**
- * fdt_appendprop_u32 - append a 32-bit integer value to a property
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to change
- * @name: name of the property to change
- * @val: 32-bit integer value to append to the property (native endian)
- *
- * fdt_appendprop_u32() appends the given 32-bit integer value
- * (converting to big-endian if necessary) to the value of the named
- * property in the given node, or creates a new property with that
- * value if it does not already exist.
- *
- * This function may insert data into the blob, and will therefore
- * change the offsets of some existing nodes.
- *
- * returns:
- *  0, on success
- *  -FDT_ERR_NOSPACE, there is insufficient free space in the blob to
- *      contain the new property value
- *  -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_TRUNCATED, standard meanings
- */
-static inline int fdt_appendprop_u32(void *fdt, int nodeoffset,
-                     const char *name, uint32_t val)
-{
-    fdt32_t tmp = cpu_to_fdt32(val);
-    return fdt_appendprop(fdt, nodeoffset, name, &tmp, sizeof(tmp));
-}
-
-/**
- * fdt_appendprop_u64 - append a 64-bit integer value to a property
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to change
- * @name: name of the property to change
- * @val: 64-bit integer value to append to the property (native endian)
- *
- * fdt_appendprop_u64() appends the given 64-bit integer value
- * (converting to big-endian if necessary) to the value of the named
- * property in the given node, or creates a new property with that
- * value if it does not already exist.
- *
- * This function may insert data into the blob, and will therefore
- * change the offsets of some existing nodes.
- *
- * returns:
- *  0, on success
- *  -FDT_ERR_NOSPACE, there is insufficient free space in the blob to
- *      contain the new property value
- *  -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_TRUNCATED, standard meanings
- */
-static inline int fdt_appendprop_u64(void *fdt, int nodeoffset,
-                     const char *name, uint64_t val)
-{
-    fdt64_t tmp = cpu_to_fdt64(val);
-    return fdt_appendprop(fdt, nodeoffset, name, &tmp, sizeof(tmp));
-}
-
-/**
- * fdt_appendprop_cell - append a single cell value to a property
- *
- * This is an alternative name for fdt_appendprop_u32()
- */
-static inline int fdt_appendprop_cell(void *fdt, int nodeoffset,
-                      const char *name, uint32_t val)
-{
-    return fdt_appendprop_u32(fdt, nodeoffset, name, val);
-}
-
-/**
- * fdt_appendprop_string - append a string to a property
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to change
- * @name: name of the property to change
- * @str: string value to append to the property
- *
- * fdt_appendprop_string() appends the given string to the value of
- * the named property in the given node, or creates a new property
- * with that value if it does not already exist.
- *
- * This function may insert data into the blob, and will therefore
- * change the offsets of some existing nodes.
- *
- * returns:
- *  0, on success
- *  -FDT_ERR_NOSPACE, there is insufficient free space in the blob to
- *      contain the new property value
- *  -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_TRUNCATED, standard meanings
- */
-#define fdt_appendprop_string(fdt, nodeoffset, name, str) \
-    fdt_appendprop((fdt), (nodeoffset), (name), (str), strlen(str)+1)
-
-/**
- * fdt_delprop - delete a property
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to nop
- * @name: name of the property to nop
- *
- * fdt_del_property() will delete the given property.
- *
- * This function will delete data from the blob, and will therefore
- * change the offsets of some existing nodes.
- *
- * returns:
- *  0, on success
- *  -FDT_ERR_NOTFOUND, node does not have the named property
- *  -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_TRUNCATED, standard meanings
- */
-int fdt_delprop(void *fdt, int nodeoffset, const char *name);
-
-/**
- * fdt_add_subnode_namelen - creates a new node based on substring
- * @fdt: pointer to the device tree blob
- * @parentoffset: structure block offset of a node
- * @name: name of the subnode to locate
- * @namelen: number of characters of name to consider
- *
- * Identical to fdt_add_subnode(), but use only the first namelen
- * characters of name as the name of the new node.  This is useful for
- * creating subnodes based on a portion of a larger string, such as a
- * full path.
- */
-#ifndef SWIG /* Not available in Python */
-int fdt_add_subnode_namelen(void *fdt, int parentoffset,
-                const char *name, int namelen);
-#endif
-
-/**
- * fdt_add_subnode - creates a new node
- * @fdt: pointer to the device tree blob
- * @parentoffset: structure block offset of a node
- * @name: name of the subnode to locate
- *
- * fdt_add_subnode() creates a new node as a subnode of the node at
- * structure block offset parentoffset, with the given name (which
- * should include the unit address, if any).
- *
- * This function will insert data into the blob, and will therefore
- * change the offsets of some existing nodes.
-
- * returns:
- *  structure block offset of the created nodeequested subnode (>=0), on
- *      success
- *  -FDT_ERR_NOTFOUND, if the requested subnode does not exist
- *  -FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE
- *      tag
- *  -FDT_ERR_EXISTS, if the node at parentoffset already has a subnode of
- *      the given name
- *  -FDT_ERR_NOSPACE, if there is insufficient free space in the
- *      blob to contain the new node
- *  -FDT_ERR_NOSPACE
- *  -FDT_ERR_BADLAYOUT
- *      -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_TRUNCATED, standard meanings.
- */
-int fdt_add_subnode(void *fdt, int parentoffset, const char *name);
-
-/**
- * fdt_del_node - delete a node (subtree)
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node to nop
- *
- * fdt_del_node() will remove the given node, including all its
- * subnodes if any, from the blob.
- *
- * This function will delete data from the blob, and will therefore
- * change the offsets of some existing nodes.
- *
- * returns:
- *  0, on success
- *  -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_TRUNCATED, standard meanings
- */
-int fdt_del_node(void *fdt, int nodeoffset);
-
-/**
- * fdt_overlay_apply - Applies a DT overlay on a base DT
- * @fdt: pointer to the base device tree blob
- * @fdto: pointer to the device tree overlay blob
- *
- * fdt_overlay_apply() will apply the given device tree overlay on the
- * given base device tree.
- *
- * Expect the base device tree to be modified, even if the function
- * returns an error.
- *
- * returns:
- *  0, on success
- *  -FDT_ERR_NOSPACE, there's not enough space in the base device tree
- *  -FDT_ERR_NOTFOUND, the overlay points to some inexistant nodes or
- *      properties in the base DT
- *  -FDT_ERR_BADPHANDLE,
- *  -FDT_ERR_BADOVERLAY,
- *  -FDT_ERR_NOPHANDLES,
- *  -FDT_ERR_INTERNAL,
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADOFFSET,
- *  -FDT_ERR_BADPATH,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_TRUNCATED, standard meanings
- */
-int fdt_overlay_apply(void *fdt, void *fdto);
-
-/**********************************************************************/
-/* Debugging / informational functions                                */
-/**********************************************************************/
-
-const char *fdt_strerror(int errval);
-
-#endif /* LIBFDT_H */
diff --git a/bsp/bl808/m0/libraries/stage/blfdt/inc/libfdt_env.h b/bsp/bl808/m0/libraries/stage/blfdt/inc/libfdt_env.h
deleted file mode 100644
index e7a0e02f55..0000000000
--- a/bsp/bl808/m0/libraries/stage/blfdt/inc/libfdt_env.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef LIBFDT_ENV_H
-#define LIBFDT_ENV_H
-/*
- * libfdt - Flat Device Tree manipulation
- * Copyright (C) 2006 David Gibson, IBM Corporation.
- * Copyright 2012 Kim Phillips, Freescale Semiconductor.
- *
- * libfdt is dual licensed: you can use it either under the terms of
- * the GPL, or the BSD license, at your option.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- *     You should have received a copy of the GNU General Public
- *     License along with this library; if not, write to the Free
- *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- *     MA 02110-1301 USA
- *
- * Alternatively,
- *
- *  b) Redistribution and use in source and binary forms, with or
- *     without modification, are permitted provided that the following
- *     conditions are met:
- *
- *     1. Redistributions of source code must retain the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer.
- *     2. Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials
- *        provided with the distribution.
- *
- *     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
- *     CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
- *     INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- *     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- *     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
- *     CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- *     SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *     NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- *     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *     HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- *     OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- *     EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#ifdef __CHECKER__
-#define FDT_FORCE __attribute__((force))
-#define FDT_BITWISE __attribute__((bitwise))
-#else
-#define FDT_FORCE
-#define FDT_BITWISE
-#endif
-
-typedef uint16_t FDT_BITWISE fdt16_t;
-typedef uint32_t FDT_BITWISE fdt32_t;
-typedef uint64_t FDT_BITWISE fdt64_t;
-
-#define EXTRACT_BYTE(x, n)  ((unsigned long long)((uint8_t *)&x)[n])
-#define CPU_TO_FDT16(x) ((EXTRACT_BYTE(x, 0) << 8) | EXTRACT_BYTE(x, 1))
-#define CPU_TO_FDT32(x) ((EXTRACT_BYTE(x, 0) << 24) | (EXTRACT_BYTE(x, 1) << 16) | \
-             (EXTRACT_BYTE(x, 2) << 8) | EXTRACT_BYTE(x, 3))
-#define CPU_TO_FDT64(x) ((EXTRACT_BYTE(x, 0) << 56) | (EXTRACT_BYTE(x, 1) << 48) | \
-             (EXTRACT_BYTE(x, 2) << 40) | (EXTRACT_BYTE(x, 3) << 32) | \
-             (EXTRACT_BYTE(x, 4) << 24) | (EXTRACT_BYTE(x, 5) << 16) | \
-             (EXTRACT_BYTE(x, 6) << 8) | EXTRACT_BYTE(x, 7))
-
-static inline uint16_t fdt16_to_cpu(fdt16_t x)
-{
-    return (FDT_FORCE uint16_t)CPU_TO_FDT16(x);
-}
-static inline fdt16_t cpu_to_fdt16(uint16_t x)
-{
-    return (FDT_FORCE fdt16_t)CPU_TO_FDT16(x);
-}
-
-static inline uint32_t fdt32_to_cpu(fdt32_t x)
-{
-    return (FDT_FORCE uint32_t)CPU_TO_FDT32(x);
-}
-static inline fdt32_t cpu_to_fdt32(uint32_t x)
-{
-    return (FDT_FORCE fdt32_t)CPU_TO_FDT32(x);
-}
-
-static inline uint64_t fdt64_to_cpu(fdt64_t x)
-{
-    return (FDT_FORCE uint64_t)CPU_TO_FDT64(x);
-}
-static inline fdt64_t cpu_to_fdt64(uint64_t x)
-{
-    return (FDT_FORCE fdt64_t)CPU_TO_FDT64(x);
-}
-#undef CPU_TO_FDT64
-#undef CPU_TO_FDT32
-#undef CPU_TO_FDT16
-#undef EXTRACT_BYTE
-
-#ifdef __APPLE__
-#include 
-
-/* strnlen() is not available on Mac OS < 10.7 */
-# if !defined(MAC_OS_X_VERSION_10_7) || (MAC_OS_X_VERSION_MAX_ALLOWED < \
-                                         MAC_OS_X_VERSION_10_7)
-
-#define strnlen fdt_strnlen
-
-/*
- * fdt_strnlen: returns the length of a string or max_count - which ever is
- * smallest.
- * Input 1 string: the string whose size is to be determined
- * Input 2 max_count: the maximum value returned by this function
- * Output: length of the string or max_count (the smallest of the two)
- */
-static inline size_t fdt_strnlen(const char *string, size_t max_count)
-{
-    const char *p = memchr(string, 0, max_count);
-    return p ? p - string : max_count;
-}
-
-#endif /* !defined(MAC_OS_X_VERSION_10_7) || (MAC_OS_X_VERSION_MAX_ALLOWED <
-          MAC_OS_X_VERSION_10_7) */
-
-#endif /* __APPLE__ */
-
-#endif /* LIBFDT_ENV_H */
diff --git a/bsp/bl808/m0/libraries/stage/blfdt/inc/libfdt_internal.h b/bsp/bl808/m0/libraries/stage/blfdt/inc/libfdt_internal.h
deleted file mode 100644
index dec0382a0c..0000000000
--- a/bsp/bl808/m0/libraries/stage/blfdt/inc/libfdt_internal.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef LIBFDT_INTERNAL_H
-#define LIBFDT_INTERNAL_H
-/*
- * libfdt - Flat Device Tree manipulation
- * Copyright (C) 2006 David Gibson, IBM Corporation.
- *
- * libfdt is dual licensed: you can use it either under the terms of
- * the GPL, or the BSD license, at your option.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- *     You should have received a copy of the GNU General Public
- *     License along with this library; if not, write to the Free
- *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- *     MA 02110-1301 USA
- *
- * Alternatively,
- *
- *  b) Redistribution and use in source and binary forms, with or
- *     without modification, are permitted provided that the following
- *     conditions are met:
- *
- *     1. Redistributions of source code must retain the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer.
- *     2. Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials
- *        provided with the distribution.
- *
- *     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
- *     CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
- *     INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- *     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- *     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
- *     CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- *     SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *     NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- *     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *     HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- *     OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- *     EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include 
-
-#define FDT_ALIGN(x, a)     (((x) + (a) - 1) & ~((a) - 1))
-#define FDT_TAGALIGN(x)     (FDT_ALIGN((x), FDT_TAGSIZE))
-
-int fdt_ro_probe_(const void *fdt);
-#define FDT_RO_PROBE(fdt)           \
-    { \
-        int err_; \
-        if ((err_ = fdt_ro_probe_(fdt)) != 0)   \
-            return err_; \
-    }
-
-int fdt_check_node_offset_(const void *fdt, int offset);
-int fdt_check_prop_offset_(const void *fdt, int offset);
-const char *fdt_find_string_(const char *strtab, int tabsize, const char *s);
-int fdt_node_end_offset_(void *fdt, int nodeoffset);
-
-static inline const void *fdt_offset_ptr_(const void *fdt, int offset)
-{
-    return (const char *)fdt + fdt_off_dt_struct(fdt) + offset;
-}
-
-static inline void *fdt_offset_ptr_w_(void *fdt, int offset)
-{
-    return (void *)(uintptr_t)fdt_offset_ptr_(fdt, offset);
-}
-
-static inline const struct fdt_reserve_entry *fdt_mem_rsv_(const void *fdt, int n)
-{
-    const struct fdt_reserve_entry *rsv_table =
-        (const struct fdt_reserve_entry *)
-        ((const char *)fdt + fdt_off_mem_rsvmap(fdt));
-
-    return rsv_table + n;
-}
-static inline struct fdt_reserve_entry *fdt_mem_rsv_w_(void *fdt, int n)
-{
-    return (void *)(uintptr_t)fdt_mem_rsv_(fdt, n);
-}
-
-#define FDT_SW_MAGIC        (~FDT_MAGIC)
-
-#endif /* LIBFDT_INTERNAL_H */
diff --git a/bsp/bl808/m0/libraries/stage/blfdt/src/fdt.c b/bsp/bl808/m0/libraries/stage/blfdt/src/fdt.c
deleted file mode 100644
index f77dc17a6c..0000000000
--- a/bsp/bl808/m0/libraries/stage/blfdt/src/fdt.c
+++ /dev/null
@@ -1,310 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include "libfdt_env.h"
-
-#include 
-#include 
-
-#include "libfdt_internal.h"
-
-/*
- * Minimal sanity check for a read-only tree. fdt_ro_probe_() checks
- * that the given buffer contains what appears to be a flattened
- * device tree with sane information in its header.
- */
-int fdt_ro_probe_(const void *fdt)
-{
-    if (fdt_magic(fdt) == FDT_MAGIC) {
-        /* Complete tree */
-        if (fdt_version(fdt) < FDT_FIRST_SUPPORTED_VERSION)
-            return -FDT_ERR_BADVERSION;
-        if (fdt_last_comp_version(fdt) > FDT_LAST_SUPPORTED_VERSION)
-            return -FDT_ERR_BADVERSION;
-    } else if (fdt_magic(fdt) == FDT_SW_MAGIC) {
-        /* Unfinished sequential-write blob */
-        if (fdt_size_dt_struct(fdt) == 0)
-            return -FDT_ERR_BADSTATE;
-    } else {
-        return -FDT_ERR_BADMAGIC;
-    }
-
-    return 0;
-}
-
-static int check_off_(uint32_t hdrsize, uint32_t totalsize, uint32_t off)
-{
-    return (off >= hdrsize) && (off <= totalsize);
-}
-
-static int check_block_(uint32_t hdrsize, uint32_t totalsize,
-            uint32_t base, uint32_t size)
-{
-    if (!check_off_(hdrsize, totalsize, base))
-        return 0; /* block start out of bounds */
-    if ((base + size) < base)
-        return 0; /* overflow */
-    if (!check_off_(hdrsize, totalsize, base + size))
-        return 0; /* block end out of bounds */
-    return 1;
-}
-
-size_t fdt_header_size_(uint32_t version)
-{
-    if (version <= 1)
-        return FDT_V1_SIZE;
-    else if (version <= 2)
-        return FDT_V2_SIZE;
-    else if (version <= 3)
-        return FDT_V3_SIZE;
-    else if (version <= 16)
-        return FDT_V16_SIZE;
-    else
-        return FDT_V17_SIZE;
-}
-
-int fdt_check_header(const void *fdt)
-{
-    size_t hdrsize;
-
-    if (fdt_magic(fdt) != FDT_MAGIC)
-        return -FDT_ERR_BADMAGIC;
-    hdrsize = fdt_header_size(fdt);
-    if ((fdt_version(fdt) < FDT_FIRST_SUPPORTED_VERSION)
-        || (fdt_last_comp_version(fdt) > FDT_LAST_SUPPORTED_VERSION))
-        return -FDT_ERR_BADVERSION;
-    if (fdt_version(fdt) < fdt_last_comp_version(fdt))
-        return -FDT_ERR_BADVERSION;
-
-    if ((fdt_totalsize(fdt) < hdrsize)
-        || (fdt_totalsize(fdt) > INT_MAX))
-        return -FDT_ERR_TRUNCATED;
-
-    /* Bounds check memrsv block */
-    if (!check_off_(hdrsize, fdt_totalsize(fdt), fdt_off_mem_rsvmap(fdt)))
-        return -FDT_ERR_TRUNCATED;
-
-    /* Bounds check structure block */
-    if (fdt_version(fdt) < 17) {
-        if (!check_off_(hdrsize, fdt_totalsize(fdt),
-                fdt_off_dt_struct(fdt)))
-            return -FDT_ERR_TRUNCATED;
-    } else {
-        if (!check_block_(hdrsize, fdt_totalsize(fdt),
-                  fdt_off_dt_struct(fdt),
-                  fdt_size_dt_struct(fdt)))
-            return -FDT_ERR_TRUNCATED;
-    }
-
-    /* Bounds check strings block */
-    if (!check_block_(hdrsize, fdt_totalsize(fdt),
-              fdt_off_dt_strings(fdt), fdt_size_dt_strings(fdt)))
-        return -FDT_ERR_TRUNCATED;
-
-    return 0;
-}
-
-const void *fdt_offset_ptr(const void *fdt, int offset, unsigned int len)
-{
-    unsigned absoffset = offset + fdt_off_dt_struct(fdt);
-
-    if ((absoffset < offset)
-        || ((absoffset + len) < absoffset)
-        || (absoffset + len) > fdt_totalsize(fdt))
-        return NULL;
-
-    if (fdt_version(fdt) >= 0x11)
-        if (((offset + len) < offset)
-            || ((offset + len) > fdt_size_dt_struct(fdt)))
-            return NULL;
-
-    return fdt_offset_ptr_(fdt, offset);
-}
-
-uint32_t fdt_next_tag(const void *fdt, int startoffset, int *nextoffset)
-{
-    const fdt32_t *tagp, *lenp;
-    uint32_t tag;
-    int offset = startoffset;
-    const char *p;
-
-    *nextoffset = -FDT_ERR_TRUNCATED;
-    tagp = fdt_offset_ptr(fdt, offset, FDT_TAGSIZE);
-    if (!tagp)
-        return FDT_END; /* premature end */
-    tag = fdt32_to_cpu(*tagp);
-    offset += FDT_TAGSIZE;
-
-    *nextoffset = -FDT_ERR_BADSTRUCTURE;
-    switch (tag) {
-    case FDT_BEGIN_NODE:
-        /* skip name */
-        do {
-            p = fdt_offset_ptr(fdt, offset++, 1);
-        } while (p && (*p != '\0'));
-        if (!p)
-            return FDT_END; /* premature end */
-        break;
-
-    case FDT_PROP:
-        lenp = fdt_offset_ptr(fdt, offset, sizeof(*lenp));
-        if (!lenp)
-            return FDT_END; /* premature end */
-        /* skip-name offset, length and value */
-        offset += sizeof(struct fdt_property) - FDT_TAGSIZE
-            + fdt32_to_cpu(*lenp);
-        if (fdt_version(fdt) < 0x10 && fdt32_to_cpu(*lenp) >= 8 &&
-            ((offset - fdt32_to_cpu(*lenp)) % 8) != 0)
-            offset += 4;
-        break;
-
-    case FDT_END:
-    case FDT_END_NODE:
-    case FDT_NOP:
-        break;
-
-    default:
-        return FDT_END;
-    }
-
-    if (!fdt_offset_ptr(fdt, startoffset, offset - startoffset))
-        return FDT_END; /* premature end */
-
-    *nextoffset = FDT_TAGALIGN(offset);
-    return tag;
-}
-
-int fdt_check_node_offset_(const void *fdt, int offset)
-{
-    if ((offset < 0) || (offset % FDT_TAGSIZE)
-        || (fdt_next_tag(fdt, offset, &offset) != FDT_BEGIN_NODE))
-        return -FDT_ERR_BADOFFSET;
-
-    return offset;
-}
-
-int fdt_check_prop_offset_(const void *fdt, int offset)
-{
-    if ((offset < 0) || (offset % FDT_TAGSIZE)
-        || (fdt_next_tag(fdt, offset, &offset) != FDT_PROP))
-        return -FDT_ERR_BADOFFSET;
-
-    return offset;
-}
-
-int fdt_next_node(const void *fdt, int offset, int *depth)
-{
-    int nextoffset = 0;
-    uint32_t tag;
-
-    if (offset >= 0)
-        if ((nextoffset = fdt_check_node_offset_(fdt, offset)) < 0)
-            return nextoffset;
-
-    do {
-        offset = nextoffset;
-        tag = fdt_next_tag(fdt, offset, &nextoffset);
-
-        switch (tag) {
-        case FDT_PROP:
-        case FDT_NOP:
-            break;
-
-        case FDT_BEGIN_NODE:
-            if (depth)
-                (*depth)++;
-            break;
-
-        case FDT_END_NODE:
-            if (depth && ((--(*depth)) < 0))
-                return nextoffset;
-            break;
-
-        case FDT_END:
-            if ((nextoffset >= 0)
-                || ((nextoffset == -FDT_ERR_TRUNCATED) && !depth))
-                return -FDT_ERR_NOTFOUND;
-            else
-                return nextoffset;
-        }
-    } while (tag != FDT_BEGIN_NODE);
-
-    return offset;
-}
-
-int fdt_first_subnode(const void *fdt, int offset)
-{
-    int depth = 0;
-
-    offset = fdt_next_node(fdt, offset, &depth);
-    if (offset < 0 || depth != 1)
-        return -FDT_ERR_NOTFOUND;
-
-    return offset;
-}
-
-int fdt_next_subnode(const void *fdt, int offset)
-{
-    int depth = 1;
-
-    /*
-     * With respect to the parent, the depth of the next subnode will be
-     * the same as the last.
-     */
-    do {
-        offset = fdt_next_node(fdt, offset, &depth);
-        if (offset < 0 || depth < 1)
-            return -FDT_ERR_NOTFOUND;
-    } while (depth > 1);
-
-    return offset;
-}
-
-const char *fdt_find_string_(const char *strtab, int tabsize, const char *s)
-{
-    int len = strlen(s) + 1;
-    const char *last = strtab + tabsize - len;
-    const char *p;
-
-    for (p = strtab; p <= last; p++)
-        if (memcmp(p, s, len) == 0)
-            return p;
-    return NULL;
-}
-
-int fdt_move(const void *fdt, void *buf, int bufsize)
-{
-    FDT_RO_PROBE(fdt);
-
-    if (fdt_totalsize(fdt) > bufsize)
-        return -FDT_ERR_NOSPACE;
-
-    memmove(buf, fdt, fdt_totalsize(fdt));
-    return 0;
-}
diff --git a/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_addresses.c b/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_addresses.c
deleted file mode 100644
index c854c90e12..0000000000
--- a/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_addresses.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include "libfdt_env.h"
-
-#include 
-#include 
-
-#include "libfdt_internal.h"
-
-static int fdt_cells(const void *fdt, int nodeoffset, const char *name)
-{
-    const fdt32_t *c;
-    int val;
-    int len;
-
-    c = fdt_getprop(fdt, nodeoffset, name, &len);
-    if (!c)
-        return len;
-
-    if (len != sizeof(*c))
-        return -FDT_ERR_BADNCELLS;
-
-    val = fdt32_to_cpu(*c);
-    if ((val <= 0) || (val > FDT_MAX_NCELLS))
-        return -FDT_ERR_BADNCELLS;
-
-    return val;
-}
-
-int fdt_address_cells(const void *fdt, int nodeoffset)
-{
-    int val;
-
-    val = fdt_cells(fdt, nodeoffset, "#address-cells");
-    if (val == -FDT_ERR_NOTFOUND)
-        return 2;
-    return val;
-}
-
-int fdt_size_cells(const void *fdt, int nodeoffset)
-{
-    int val;
-
-    val = fdt_cells(fdt, nodeoffset, "#size-cells");
-    if (val == -FDT_ERR_NOTFOUND)
-        return 1;
-    return val;
-}
diff --git a/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_empty_tree.c b/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_empty_tree.c
deleted file mode 100644
index 8c9a9f5e57..0000000000
--- a/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_empty_tree.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include "libfdt_env.h"
-
-#include 
-#include 
-
-#include "libfdt_internal.h"
-
-int fdt_create_empty_tree(void *buf, int bufsize)
-{
-    int err;
-
-    err = fdt_create(buf, bufsize);
-    if (err)
-        return err;
-
-    err = fdt_finish_reservemap(buf);
-    if (err)
-        return err;
-
-    err = fdt_begin_node(buf, "");
-    if (err)
-        return err;
-
-    err =  fdt_end_node(buf);
-    if (err)
-        return err;
-
-    err = fdt_finish(buf);
-    if (err)
-        return err;
-
-    return fdt_open_into(buf, buf, bufsize);
-}
diff --git a/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_overlay.c b/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_overlay.c
deleted file mode 100644
index e7d14b1e4c..0000000000
--- a/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_overlay.c
+++ /dev/null
@@ -1,890 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include "libfdt_env.h"
-
-#include 
-#include 
-
-#include "libfdt_internal.h"
-
-/**
- * overlay_get_target_phandle - retrieves the target phandle of a fragment
- * @fdto: pointer to the device tree overlay blob
- * @fragment: node offset of the fragment in the overlay
- *
- * overlay_get_target_phandle() retrieves the target phandle of an
- * overlay fragment when that fragment uses a phandle (target
- * property) instead of a path (target-path property).
- *
- * returns:
- *      the phandle pointed by the target property
- *      0, if the phandle was not found
- *  -1, if the phandle was malformed
- */
-static uint32_t overlay_get_target_phandle(const void *fdto, int fragment)
-{
-    const fdt32_t *val;
-    int len;
-
-    val = fdt_getprop(fdto, fragment, "target", &len);
-    if (!val)
-        return 0;
-
-    if ((len != sizeof(*val)) || (fdt32_to_cpu(*val) == (uint32_t)-1))
-        return (uint32_t)-1;
-
-    return fdt32_to_cpu(*val);
-}
-
-/**
- * overlay_get_target - retrieves the offset of a fragment's target
- * @fdt: Base device tree blob
- * @fdto: Device tree overlay blob
- * @fragment: node offset of the fragment in the overlay
- * @pathp: pointer which receives the path of the target (or NULL)
- *
- * overlay_get_target() retrieves the target offset in the base
- * device tree of a fragment, no matter how the actual targetting is
- * done (through a phandle or a path)
- *
- * returns:
- *      the targetted node offset in the base device tree
- *      Negative error code on error
- */
-static int overlay_get_target(const void *fdt, const void *fdto,
-                  int fragment, char const **pathp)
-{
-    uint32_t phandle;
-    const char *path = NULL;
-    int path_len = 0, ret;
-
-    /* Try first to do a phandle based lookup */
-    phandle = overlay_get_target_phandle(fdto, fragment);
-    if (phandle == (uint32_t)-1)
-        return -FDT_ERR_BADPHANDLE;
-
-    /* no phandle, try path */
-    if (!phandle) {
-        /* And then a path based lookup */
-        path = fdt_getprop(fdto, fragment, "target-path", &path_len);
-        if (path)
-            ret = fdt_path_offset(fdt, path);
-        else
-            ret = path_len;
-    } else
-        ret = fdt_node_offset_by_phandle(fdt, phandle);
-
-    /*
-    * If we haven't found either a target or a
-    * target-path property in a node that contains a
-    * __overlay__ subnode (we wouldn't be called
-    * otherwise), consider it a improperly written
-    * overlay
-    */
-    if (ret < 0 && path_len == -FDT_ERR_NOTFOUND)
-        ret = -FDT_ERR_BADOVERLAY;
-
-    /* return on error */
-    if (ret < 0)
-        return ret;
-
-    /* return pointer to path (if available) */
-    if (pathp)
-        *pathp = path ? path : NULL;
-
-    return ret;
-}
-
-/**
- * overlay_phandle_add_offset - Increases a phandle by an offset
- * @fdt: Base device tree blob
- * @node: Device tree overlay blob
- * @name: Name of the property to modify (phandle or linux,phandle)
- * @delta: offset to apply
- *
- * overlay_phandle_add_offset() increments a node phandle by a given
- * offset.
- *
- * returns:
- *      0 on success.
- *      Negative error code on error
- */
-static int overlay_phandle_add_offset(void *fdt, int node,
-                      const char *name, uint32_t delta)
-{
-    const fdt32_t *val;
-    uint32_t adj_val;
-    int len;
-
-    val = fdt_getprop(fdt, node, name, &len);
-    if (!val)
-        return len;
-
-    if (len != sizeof(*val))
-        return -FDT_ERR_BADPHANDLE;
-
-    adj_val = fdt32_to_cpu(*val);
-    if ((adj_val + delta) < adj_val)
-        return -FDT_ERR_NOPHANDLES;
-
-    adj_val += delta;
-    if (adj_val == (uint32_t)-1)
-        return -FDT_ERR_NOPHANDLES;
-
-    return fdt_setprop_inplace_u32(fdt, node, name, adj_val);
-}
-
-/**
- * overlay_adjust_node_phandles - Offsets the phandles of a node
- * @fdto: Device tree overlay blob
- * @node: Offset of the node we want to adjust
- * @delta: Offset to shift the phandles of
- *
- * overlay_adjust_node_phandles() adds a constant to all the phandles
- * of a given node. This is mainly use as part of the overlay
- * application process, when we want to update all the overlay
- * phandles to not conflict with the overlays of the base device tree.
- *
- * returns:
- *      0 on success
- *      Negative error code on failure
- */
-static int overlay_adjust_node_phandles(void *fdto, int node,
-                    uint32_t delta)
-{
-    int child;
-    int ret;
-
-    ret = overlay_phandle_add_offset(fdto, node, "phandle", delta);
-    if (ret && ret != -FDT_ERR_NOTFOUND)
-        return ret;
-
-    ret = overlay_phandle_add_offset(fdto, node, "linux,phandle", delta);
-    if (ret && ret != -FDT_ERR_NOTFOUND)
-        return ret;
-
-    fdt_for_each_subnode(child, fdto, node) {
-        ret = overlay_adjust_node_phandles(fdto, child, delta);
-        if (ret)
-            return ret;
-    }
-
-    return 0;
-}
-
-/**
- * overlay_adjust_local_phandles - Adjust the phandles of a whole overlay
- * @fdto: Device tree overlay blob
- * @delta: Offset to shift the phandles of
- *
- * overlay_adjust_local_phandles() adds a constant to all the
- * phandles of an overlay. This is mainly use as part of the overlay
- * application process, when we want to update all the overlay
- * phandles to not conflict with the overlays of the base device tree.
- *
- * returns:
- *      0 on success
- *      Negative error code on failure
- */
-static int overlay_adjust_local_phandles(void *fdto, uint32_t delta)
-{
-    /*
-     * Start adjusting the phandles from the overlay root
-     */
-    return overlay_adjust_node_phandles(fdto, 0, delta);
-}
-
-/**
- * overlay_update_local_node_references - Adjust the overlay references
- * @fdto: Device tree overlay blob
- * @tree_node: Node offset of the node to operate on
- * @fixup_node: Node offset of the matching local fixups node
- * @delta: Offset to shift the phandles of
- *
- * overlay_update_local_nodes_references() update the phandles
- * pointing to a node within the device tree overlay by adding a
- * constant delta.
- *
- * This is mainly used as part of a device tree application process,
- * where you want the device tree overlays phandles to not conflict
- * with the ones from the base device tree before merging them.
- *
- * returns:
- *      0 on success
- *      Negative error code on failure
- */
-static int overlay_update_local_node_references(void *fdto,
-                        int tree_node,
-                        int fixup_node,
-                        uint32_t delta)
-{
-    int fixup_prop;
-    int fixup_child;
-    int ret;
-
-    fdt_for_each_property_offset(fixup_prop, fdto, fixup_node) {
-        const fdt32_t *fixup_val;
-        const char *tree_val;
-        const char *name;
-        int fixup_len;
-        int tree_len;
-        int i;
-
-        fixup_val = fdt_getprop_by_offset(fdto, fixup_prop,
-                          &name, &fixup_len);
-        if (!fixup_val)
-            return fixup_len;
-
-        if (fixup_len % sizeof(uint32_t))
-            return -FDT_ERR_BADOVERLAY;
-
-        tree_val = fdt_getprop(fdto, tree_node, name, &tree_len);
-        if (!tree_val) {
-            if (tree_len == -FDT_ERR_NOTFOUND)
-                return -FDT_ERR_BADOVERLAY;
-
-            return tree_len;
-        }
-
-        for (i = 0; i < (fixup_len / sizeof(uint32_t)); i++) {
-            fdt32_t adj_val;
-            uint32_t poffset;
-
-            poffset = fdt32_to_cpu(fixup_val[i]);
-
-            /*
-             * phandles to fixup can be unaligned.
-             *
-             * Use a memcpy for the architectures that do
-             * not support unaligned accesses.
-             */
-            memcpy(&adj_val, tree_val + poffset, sizeof(adj_val));
-
-            adj_val = cpu_to_fdt32(fdt32_to_cpu(adj_val) + delta);
-
-            ret = fdt_setprop_inplace_namelen_partial(fdto,
-                                  tree_node,
-                                  name,
-                                  strlen(name),
-                                  poffset,
-                                  &adj_val,
-                                  sizeof(adj_val));
-            if (ret == -FDT_ERR_NOSPACE)
-                return -FDT_ERR_BADOVERLAY;
-
-            if (ret)
-                return ret;
-        }
-    }
-
-    fdt_for_each_subnode(fixup_child, fdto, fixup_node) {
-        const char *fixup_child_name = fdt_get_name(fdto, fixup_child,
-                                NULL);
-        int tree_child;
-
-        tree_child = fdt_subnode_offset(fdto, tree_node,
-                        fixup_child_name);
-        if (tree_child == -FDT_ERR_NOTFOUND)
-            return -FDT_ERR_BADOVERLAY;
-        if (tree_child < 0)
-            return tree_child;
-
-        ret = overlay_update_local_node_references(fdto,
-                               tree_child,
-                               fixup_child,
-                               delta);
-        if (ret)
-            return ret;
-    }
-
-    return 0;
-}
-
-/**
- * overlay_update_local_references - Adjust the overlay references
- * @fdto: Device tree overlay blob
- * @delta: Offset to shift the phandles of
- *
- * overlay_update_local_references() update all the phandles pointing
- * to a node within the device tree overlay by adding a constant
- * delta to not conflict with the base overlay.
- *
- * This is mainly used as part of a device tree application process,
- * where you want the device tree overlays phandles to not conflict
- * with the ones from the base device tree before merging them.
- *
- * returns:
- *      0 on success
- *      Negative error code on failure
- */
-static int overlay_update_local_references(void *fdto, uint32_t delta)
-{
-    int fixups;
-
-    fixups = fdt_path_offset(fdto, "/__local_fixups__");
-    if (fixups < 0) {
-        /* There's no local phandles to adjust, bail out */
-        if (fixups == -FDT_ERR_NOTFOUND)
-            return 0;
-
-        return fixups;
-    }
-
-    /*
-     * Update our local references from the root of the tree
-     */
-    return overlay_update_local_node_references(fdto, 0, fixups,
-                            delta);
-}
-
-/**
- * overlay_fixup_one_phandle - Set an overlay phandle to the base one
- * @fdt: Base Device Tree blob
- * @fdto: Device tree overlay blob
- * @symbols_off: Node offset of the symbols node in the base device tree
- * @path: Path to a node holding a phandle in the overlay
- * @path_len: number of path characters to consider
- * @name: Name of the property holding the phandle reference in the overlay
- * @name_len: number of name characters to consider
- * @poffset: Offset within the overlay property where the phandle is stored
- * @label: Label of the node referenced by the phandle
- *
- * overlay_fixup_one_phandle() resolves an overlay phandle pointing to
- * a node in the base device tree.
- *
- * This is part of the device tree overlay application process, when
- * you want all the phandles in the overlay to point to the actual
- * base dt nodes.
- *
- * returns:
- *      0 on success
- *      Negative error code on failure
- */
-static int overlay_fixup_one_phandle(void *fdt, void *fdto,
-                     int symbols_off,
-                     const char *path, uint32_t path_len,
-                     const char *name, uint32_t name_len,
-                     int poffset, const char *label)
-{
-    const char *symbol_path;
-    uint32_t phandle;
-    fdt32_t phandle_prop;
-    int symbol_off, fixup_off;
-    int prop_len;
-
-    if (symbols_off < 0)
-        return symbols_off;
-
-    symbol_path = fdt_getprop(fdt, symbols_off, label,
-                  &prop_len);
-    if (!symbol_path)
-        return prop_len;
-
-    symbol_off = fdt_path_offset(fdt, symbol_path);
-    if (symbol_off < 0)
-        return symbol_off;
-
-    phandle = fdt_get_phandle(fdt, symbol_off);
-    if (!phandle)
-        return -FDT_ERR_NOTFOUND;
-
-    fixup_off = fdt_path_offset_namelen(fdto, path, path_len);
-    if (fixup_off == -FDT_ERR_NOTFOUND)
-        return -FDT_ERR_BADOVERLAY;
-    if (fixup_off < 0)
-        return fixup_off;
-
-    phandle_prop = cpu_to_fdt32(phandle);
-    return fdt_setprop_inplace_namelen_partial(fdto, fixup_off,
-                           name, name_len, poffset,
-                           &phandle_prop,
-                           sizeof(phandle_prop));
-};
-
-/**
- * overlay_fixup_phandle - Set an overlay phandle to the base one
- * @fdt: Base Device Tree blob
- * @fdto: Device tree overlay blob
- * @symbols_off: Node offset of the symbols node in the base device tree
- * @property: Property offset in the overlay holding the list of fixups
- *
- * overlay_fixup_phandle() resolves all the overlay phandles pointed
- * to in a __fixups__ property, and updates them to match the phandles
- * in use in the base device tree.
- *
- * This is part of the device tree overlay application process, when
- * you want all the phandles in the overlay to point to the actual
- * base dt nodes.
- *
- * returns:
- *      0 on success
- *      Negative error code on failure
- */
-static int overlay_fixup_phandle(void *fdt, void *fdto, int symbols_off,
-                 int property)
-{
-    const char *value;
-    const char *label;
-    int len;
-
-    value = fdt_getprop_by_offset(fdto, property,
-                      &label, &len);
-    if (!value) {
-        if (len == -FDT_ERR_NOTFOUND)
-            return -FDT_ERR_INTERNAL;
-
-        return len;
-    }
-
-    do {
-        const char *path, *name, *fixup_end;
-        const char *fixup_str = value;
-        uint32_t path_len, name_len;
-        uint32_t fixup_len;
-        char *sep, *endptr;
-        int poffset, ret;
-
-        fixup_end = memchr(value, '\0', len);
-        if (!fixup_end)
-            return -FDT_ERR_BADOVERLAY;
-        fixup_len = fixup_end - fixup_str;
-
-        len -= fixup_len + 1;
-        value += fixup_len + 1;
-
-        path = fixup_str;
-        sep = memchr(fixup_str, ':', fixup_len);
-        if (!sep || *sep != ':')
-            return -FDT_ERR_BADOVERLAY;
-
-        path_len = sep - path;
-        if (path_len == (fixup_len - 1))
-            return -FDT_ERR_BADOVERLAY;
-
-        fixup_len -= path_len + 1;
-        name = sep + 1;
-        sep = memchr(name, ':', fixup_len);
-        if (!sep || *sep != ':')
-            return -FDT_ERR_BADOVERLAY;
-
-        name_len = sep - name;
-        if (!name_len)
-            return -FDT_ERR_BADOVERLAY;
-
-        poffset = strtoul(sep + 1, &endptr, 10);
-        if ((*endptr != '\0') || (endptr <= (sep + 1)))
-            return -FDT_ERR_BADOVERLAY;
-
-        ret = overlay_fixup_one_phandle(fdt, fdto, symbols_off,
-                        path, path_len, name, name_len,
-                        poffset, label);
-        if (ret)
-            return ret;
-    } while (len > 0);
-
-    return 0;
-}
-
-/**
- * overlay_fixup_phandles - Resolve the overlay phandles to the base
- *                          device tree
- * @fdt: Base Device Tree blob
- * @fdto: Device tree overlay blob
- *
- * overlay_fixup_phandles() resolves all the overlay phandles pointing
- * to nodes in the base device tree.
- *
- * This is one of the steps of the device tree overlay application
- * process, when you want all the phandles in the overlay to point to
- * the actual base dt nodes.
- *
- * returns:
- *      0 on success
- *      Negative error code on failure
- */
-static int overlay_fixup_phandles(void *fdt, void *fdto)
-{
-    int fixups_off, symbols_off;
-    int property;
-
-    /* We can have overlays without any fixups */
-    fixups_off = fdt_path_offset(fdto, "/__fixups__");
-    if (fixups_off == -FDT_ERR_NOTFOUND)
-        return 0; /* nothing to do */
-    if (fixups_off < 0)
-        return fixups_off;
-
-    /* And base DTs without symbols */
-    symbols_off = fdt_path_offset(fdt, "/__symbols__");
-    if ((symbols_off < 0 && (symbols_off != -FDT_ERR_NOTFOUND)))
-        return symbols_off;
-
-    fdt_for_each_property_offset(property, fdto, fixups_off) {
-        int ret;
-
-        ret = overlay_fixup_phandle(fdt, fdto, symbols_off, property);
-        if (ret)
-            return ret;
-    }
-
-    return 0;
-}
-
-/**
- * overlay_apply_node - Merges a node into the base device tree
- * @fdt: Base Device Tree blob
- * @target: Node offset in the base device tree to apply the fragment to
- * @fdto: Device tree overlay blob
- * @node: Node offset in the overlay holding the changes to merge
- *
- * overlay_apply_node() merges a node into a target base device tree
- * node pointed.
- *
- * This is part of the final step in the device tree overlay
- * application process, when all the phandles have been adjusted and
- * resolved and you just have to merge overlay into the base device
- * tree.
- *
- * returns:
- *      0 on success
- *      Negative error code on failure
- */
-static int overlay_apply_node(void *fdt, int target,
-                  void *fdto, int node)
-{
-    int property;
-    int subnode;
-
-    fdt_for_each_property_offset(property, fdto, node) {
-        const char *name;
-        const void *prop;
-        int prop_len;
-        int ret;
-
-        prop = fdt_getprop_by_offset(fdto, property, &name,
-                         &prop_len);
-        if (prop_len == -FDT_ERR_NOTFOUND)
-            return -FDT_ERR_INTERNAL;
-        if (prop_len < 0)
-            return prop_len;
-
-        ret = fdt_setprop(fdt, target, name, prop, prop_len);
-        if (ret)
-            return ret;
-    }
-
-    fdt_for_each_subnode(subnode, fdto, node) {
-        const char *name = fdt_get_name(fdto, subnode, NULL);
-        int nnode;
-        int ret;
-
-        nnode = fdt_add_subnode(fdt, target, name);
-        if (nnode == -FDT_ERR_EXISTS) {
-            nnode = fdt_subnode_offset(fdt, target, name);
-            if (nnode == -FDT_ERR_NOTFOUND)
-                return -FDT_ERR_INTERNAL;
-        }
-
-        if (nnode < 0)
-            return nnode;
-
-        ret = overlay_apply_node(fdt, nnode, fdto, subnode);
-        if (ret)
-            return ret;
-    }
-
-    return 0;
-}
-
-/**
- * overlay_merge - Merge an overlay into its base device tree
- * @fdt: Base Device Tree blob
- * @fdto: Device tree overlay blob
- *
- * overlay_merge() merges an overlay into its base device tree.
- *
- * This is the next to last step in the device tree overlay application
- * process, when all the phandles have been adjusted and resolved and
- * you just have to merge overlay into the base device tree.
- *
- * returns:
- *      0 on success
- *      Negative error code on failure
- */
-static int overlay_merge(void *fdt, void *fdto)
-{
-    int fragment;
-
-    fdt_for_each_subnode(fragment, fdto, 0) {
-        int overlay;
-        int target;
-        int ret;
-
-        /*
-         * Each fragments will have an __overlay__ node. If
-         * they don't, it's not supposed to be merged
-         */
-        overlay = fdt_subnode_offset(fdto, fragment, "__overlay__");
-        if (overlay == -FDT_ERR_NOTFOUND)
-            continue;
-
-        if (overlay < 0)
-            return overlay;
-
-        target = overlay_get_target(fdt, fdto, fragment, NULL);
-        if (target < 0)
-            return target;
-
-        ret = overlay_apply_node(fdt, target, fdto, overlay);
-        if (ret)
-            return ret;
-    }
-
-    return 0;
-}
-
-static int get_path_len(const void *fdt, int nodeoffset)
-{
-    int len = 0, namelen;
-    const char *name;
-
-    FDT_RO_PROBE(fdt);
-
-    for (;;) {
-        name = fdt_get_name(fdt, nodeoffset, &namelen);
-        if (!name)
-            return namelen;
-
-        /* root? we're done */
-        if (namelen == 0)
-            break;
-
-        nodeoffset = fdt_parent_offset(fdt, nodeoffset);
-        if (nodeoffset < 0)
-            return nodeoffset;
-        len += namelen + 1;
-    }
-
-    /* in case of root pretend it's "/" */
-    if (len == 0)
-        len++;
-    return len;
-}
-
-/**
- * overlay_symbol_update - Update the symbols of base tree after a merge
- * @fdt: Base Device Tree blob
- * @fdto: Device tree overlay blob
- *
- * overlay_symbol_update() updates the symbols of the base tree with the
- * symbols of the applied overlay
- *
- * This is the last step in the device tree overlay application
- * process, allowing the reference of overlay symbols by subsequent
- * overlay operations.
- *
- * returns:
- *      0 on success
- *      Negative error code on failure
- */
-static int overlay_symbol_update(void *fdt, void *fdto)
-{
-    int root_sym, ov_sym, prop, path_len, fragment, target;
-    int len, frag_name_len, ret, rel_path_len;
-    const char *s, *e;
-    const char *path;
-    const char *name;
-    const char *frag_name;
-    const char *rel_path;
-    const char *target_path;
-    char *buf;
-    void *p;
-
-    ov_sym = fdt_subnode_offset(fdto, 0, "__symbols__");
-
-    /* if no overlay symbols exist no problem */
-    if (ov_sym < 0)
-        return 0;
-
-    root_sym = fdt_subnode_offset(fdt, 0, "__symbols__");
-
-    /* it no root symbols exist we should create them */
-    if (root_sym == -FDT_ERR_NOTFOUND)
-        root_sym = fdt_add_subnode(fdt, 0, "__symbols__");
-
-    /* any error is fatal now */
-    if (root_sym < 0)
-        return root_sym;
-
-    /* iterate over each overlay symbol */
-    fdt_for_each_property_offset(prop, fdto, ov_sym) {
-        path = fdt_getprop_by_offset(fdto, prop, &name, &path_len);
-        if (!path)
-            return path_len;
-
-        /* verify it's a string property (terminated by a single \0) */
-        if (path_len < 1 || memchr(path, '\0', path_len) != &path[path_len - 1])
-            return -FDT_ERR_BADVALUE;
-
-        /* keep end marker to avoid strlen() */
-        e = path + path_len;
-
-        /* format: //__overlay__/ */
-
-        if (*path != '/')
-            return -FDT_ERR_BADVALUE;
-
-        /* get fragment name first */
-        s = strchr(path + 1, '/');
-        if (!s)
-            return -FDT_ERR_BADOVERLAY;
-
-        frag_name = path + 1;
-        frag_name_len = s - path - 1;
-
-        /* verify format; safe since "s" lies in \0 terminated prop */
-        len = sizeof("/__overlay__/") - 1;
-        if ((e - s) < len || memcmp(s, "/__overlay__/", len))
-            return -FDT_ERR_BADOVERLAY;
-
-        rel_path = s + len;
-        rel_path_len = e - rel_path;
-
-        /* find the fragment index in which the symbol lies */
-        ret = fdt_subnode_offset_namelen(fdto, 0, frag_name,
-                           frag_name_len);
-        /* not found? */
-        if (ret < 0)
-            return -FDT_ERR_BADOVERLAY;
-        fragment = ret;
-
-        /* an __overlay__ subnode must exist */
-        ret = fdt_subnode_offset(fdto, fragment, "__overlay__");
-        if (ret < 0)
-            return -FDT_ERR_BADOVERLAY;
-
-        /* get the target of the fragment */
-        ret = overlay_get_target(fdt, fdto, fragment, &target_path);
-        if (ret < 0)
-            return ret;
-        target = ret;
-
-        /* if we have a target path use */
-        if (!target_path) {
-            ret = get_path_len(fdt, target);
-            if (ret < 0)
-                return ret;
-            len = ret;
-        } else {
-            len = strlen(target_path);
-        }
-
-        ret = fdt_setprop_placeholder(fdt, root_sym, name,
-                len + (len > 1) + rel_path_len + 1, &p);
-        if (ret < 0)
-            return ret;
-
-        if (!target_path) {
-            /* again in case setprop_placeholder changed it */
-            ret = overlay_get_target(fdt, fdto, fragment, &target_path);
-            if (ret < 0)
-                return ret;
-            target = ret;
-        }
-
-        buf = p;
-        if (len > 1) { /* target is not root */
-            if (!target_path) {
-                ret = fdt_get_path(fdt, target, buf, len + 1);
-                if (ret < 0)
-                    return ret;
-            } else
-                memcpy(buf, target_path, len + 1);
-
-        } else
-            len--;
-
-        buf[len] = '/';
-        memcpy(buf + len + 1, rel_path, rel_path_len);
-        buf[len + 1 + rel_path_len] = '\0';
-    }
-
-    return 0;
-}
-
-int fdt_overlay_apply(void *fdt, void *fdto)
-{
-    uint32_t delta = fdt_get_max_phandle(fdt);
-    int ret;
-
-    FDT_RO_PROBE(fdt);
-    FDT_RO_PROBE(fdto);
-
-    ret = overlay_adjust_local_phandles(fdto, delta);
-    if (ret)
-        goto err;
-
-    ret = overlay_update_local_references(fdto, delta);
-    if (ret)
-        goto err;
-
-    ret = overlay_fixup_phandles(fdt, fdto);
-    if (ret)
-        goto err;
-
-    ret = overlay_merge(fdt, fdto);
-    if (ret)
-        goto err;
-
-    ret = overlay_symbol_update(fdt, fdto);
-    if (ret)
-        goto err;
-
-    /*
-     * The overlay has been damaged, erase its magic.
-     */
-    fdt_set_magic(fdto, ~0);
-
-    return 0;
-
-err:
-    /*
-     * The overlay might have been damaged, erase its magic.
-     */
-    fdt_set_magic(fdto, ~0);
-
-    /*
-     * The base device tree might have been damaged, erase its
-     * magic.
-     */
-    fdt_set_magic(fdt, ~0);
-
-    return ret;
-}
diff --git a/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_ro.c b/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_ro.c
deleted file mode 100644
index 64aff00b79..0000000000
--- a/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_ro.c
+++ /dev/null
@@ -1,901 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include "libfdt_env.h"
-
-#include 
-#include 
-
-#include "libfdt_internal.h"
-
-static int fdt_nodename_eq_(const void *fdt, int offset,
-                const char *s, int len)
-{
-    int olen;
-    const char *p = fdt_get_name(fdt, offset, &olen);
-
-    if (!p || olen < len)
-        /* short match */
-        return 0;
-
-    if (memcmp(p, s, len) != 0)
-        return 0;
-
-    if (p[len] == '\0')
-        return 1;
-    else if (!memchr(s, '@', len) && (p[len] == '@'))
-        return 1;
-    else
-        return 0;
-}
-
-const char *fdt_get_string(const void *fdt, int stroffset, int *lenp)
-{
-    uint32_t absoffset = stroffset + fdt_off_dt_strings(fdt);
-    size_t len;
-    int err;
-    const char *s, *n;
-
-    err = fdt_ro_probe_(fdt);
-    if (err != 0)
-        goto fail;
-
-    err = -FDT_ERR_BADOFFSET;
-    if (absoffset >= fdt_totalsize(fdt))
-        goto fail;
-    len = fdt_totalsize(fdt) - absoffset;
-
-    if (fdt_magic(fdt) == FDT_MAGIC) {
-        if (stroffset < 0)
-            goto fail;
-        if (fdt_version(fdt) >= 17) {
-            if (stroffset >= fdt_size_dt_strings(fdt))
-                goto fail;
-            if ((fdt_size_dt_strings(fdt) - stroffset) < len)
-                len = fdt_size_dt_strings(fdt) - stroffset;
-        }
-    } else if (fdt_magic(fdt) == FDT_SW_MAGIC) {
-        if ((stroffset >= 0)
-            || (stroffset < -fdt_size_dt_strings(fdt)))
-            goto fail;
-        if ((-stroffset) < len)
-            len = -stroffset;
-    } else {
-        err = -FDT_ERR_INTERNAL;
-        goto fail;
-    }
-
-    s = (const char *)fdt + absoffset;
-    n = memchr(s, '\0', len);
-    if (!n) {
-        /* missing terminating NULL */
-        err = -FDT_ERR_TRUNCATED;
-        goto fail;
-    }
-
-    if (lenp)
-        *lenp = n - s;
-    return s;
-
-fail:
-    if (lenp)
-        *lenp = err;
-    return NULL;
-}
-
-const char *fdt_string(const void *fdt, int stroffset)
-{
-    return fdt_get_string(fdt, stroffset, NULL);
-}
-
-static int fdt_string_eq_(const void *fdt, int stroffset,
-              const char *s, int len)
-{
-    int slen;
-    const char *p = fdt_get_string(fdt, stroffset, &slen);
-
-    return p && (slen == len) && (memcmp(p, s, len) == 0);
-}
-
-uint32_t fdt_get_max_phandle(const void *fdt)
-{
-    uint32_t max_phandle = 0;
-    int offset;
-
-    for (offset = fdt_next_node(fdt, -1, NULL);;
-         offset = fdt_next_node(fdt, offset, NULL)) {
-        uint32_t phandle;
-
-        if (offset == -FDT_ERR_NOTFOUND)
-            return max_phandle;
-
-        if (offset < 0)
-            return (uint32_t)-1;
-
-        phandle = fdt_get_phandle(fdt, offset);
-        if (phandle == (uint32_t)-1)
-            continue;
-
-        if (phandle > max_phandle)
-            max_phandle = phandle;
-    }
-
-    return 0;
-}
-
-static const struct fdt_reserve_entry *fdt_mem_rsv(const void *fdt, int n)
-{
-    int offset = n * sizeof(struct fdt_reserve_entry);
-    int absoffset = fdt_off_mem_rsvmap(fdt) + offset;
-
-    if (absoffset < fdt_off_mem_rsvmap(fdt))
-        return NULL;
-    if (absoffset > fdt_totalsize(fdt) - sizeof(struct fdt_reserve_entry))
-        return NULL;
-    return fdt_mem_rsv_(fdt, n);
-}
-
-int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size)
-{
-    const struct fdt_reserve_entry *re;
-
-    FDT_RO_PROBE(fdt);
-    re = fdt_mem_rsv(fdt, n);
-    if (!re)
-        return -FDT_ERR_BADOFFSET;
-
-    *address = fdt64_ld(&re->address);
-    *size = fdt64_ld(&re->size);
-    return 0;
-}
-
-int fdt_num_mem_rsv(const void *fdt)
-{
-    int i;
-    const struct fdt_reserve_entry *re;
-
-    for (i = 0; (re = fdt_mem_rsv(fdt, i)) != NULL; i++) {
-        if (fdt64_ld(&re->size) == 0)
-            return i;
-    }
-    return -FDT_ERR_TRUNCATED;
-}
-
-static int nextprop_(const void *fdt, int offset)
-{
-    uint32_t tag;
-    int nextoffset;
-
-    do {
-        tag = fdt_next_tag(fdt, offset, &nextoffset);
-
-        switch (tag) {
-        case FDT_END:
-            if (nextoffset >= 0)
-                return -FDT_ERR_BADSTRUCTURE;
-            else
-                return nextoffset;
-
-        case FDT_PROP:
-            return offset;
-        }
-        offset = nextoffset;
-    } while (tag == FDT_NOP);
-
-    return -FDT_ERR_NOTFOUND;
-}
-
-int fdt_subnode_offset_namelen(const void *fdt, int offset,
-                   const char *name, int namelen)
-{
-    int depth;
-
-    FDT_RO_PROBE(fdt);
-
-    for (depth = 0;
-         (offset >= 0) && (depth >= 0);
-         offset = fdt_next_node(fdt, offset, &depth))
-        if ((depth == 1)
-            && fdt_nodename_eq_(fdt, offset, name, namelen))
-            return offset;
-
-    if (depth < 0)
-        return -FDT_ERR_NOTFOUND;
-    return offset; /* error */
-}
-
-int fdt_subnode_offset(const void *fdt, int parentoffset,
-               const char *name)
-{
-    return fdt_subnode_offset_namelen(fdt, parentoffset, name, strlen(name));
-}
-
-int fdt_path_offset_namelen(const void *fdt, const char *path, int namelen)
-{
-    const char *end = path + namelen;
-    const char *p = path;
-    int offset = 0;
-
-    FDT_RO_PROBE(fdt);
-
-    /* see if we have an alias */
-    if (*path != '/') {
-        const char *q = memchr(path, '/', end - p);
-
-        if (!q)
-            q = end;
-
-        p = fdt_get_alias_namelen(fdt, p, q - p);
-        if (!p)
-            return -FDT_ERR_BADPATH;
-        offset = fdt_path_offset(fdt, p);
-
-        p = q;
-    }
-
-    while (p < end) {
-        const char *q;
-
-        while (*p == '/') {
-            p++;
-            if (p == end)
-                return offset;
-        }
-        q = memchr(p, '/', end - p);
-        if (! q)
-            q = end;
-
-        offset = fdt_subnode_offset_namelen(fdt, offset, p, q-p);
-        if (offset < 0)
-            return offset;
-
-        p = q;
-    }
-
-    return offset;
-}
-
-int fdt_path_offset(const void *fdt, const char *path)
-{
-    return fdt_path_offset_namelen(fdt, path, strlen(path));
-}
-
-const char *fdt_get_name(const void *fdt, int nodeoffset, int *len)
-{
-    const struct fdt_node_header *nh = fdt_offset_ptr_(fdt, nodeoffset);
-    const char *nameptr;
-    int err;
-
-    if (((err = fdt_ro_probe_(fdt)) != 0)
-        || ((err = fdt_check_node_offset_(fdt, nodeoffset)) < 0))
-            goto fail;
-
-    nameptr = nh->name;
-
-    if (fdt_version(fdt) < 0x10) {
-        /*
-         * For old FDT versions, match the naming conventions of V16:
-         * give only the leaf name (after all /). The actual tree
-         * contents are loosely checked.
-         */
-        const char *leaf;
-        leaf = strrchr(nameptr, '/');
-        if (leaf == NULL) {
-            err = -FDT_ERR_BADSTRUCTURE;
-            goto fail;
-        }
-        nameptr = leaf+1;
-    }
-
-    if (len)
-        *len = strlen(nameptr);
-
-    return nameptr;
-
- fail:
-    if (len)
-        *len = err;
-    return NULL;
-}
-
-int fdt_first_property_offset(const void *fdt, int nodeoffset)
-{
-    int offset;
-
-    if ((offset = fdt_check_node_offset_(fdt, nodeoffset)) < 0)
-        return offset;
-
-    return nextprop_(fdt, offset);
-}
-
-int fdt_next_property_offset(const void *fdt, int offset)
-{
-    if ((offset = fdt_check_prop_offset_(fdt, offset)) < 0)
-        return offset;
-
-    return nextprop_(fdt, offset);
-}
-
-static const struct fdt_property *fdt_get_property_by_offset_(const void *fdt,
-                                      int offset,
-                                      int *lenp)
-{
-    int err;
-    const struct fdt_property *prop;
-
-    if ((err = fdt_check_prop_offset_(fdt, offset)) < 0) {
-        if (lenp)
-            *lenp = err;
-        return NULL;
-    }
-
-    prop = fdt_offset_ptr_(fdt, offset);
-
-    if (lenp)
-        *lenp = fdt32_ld(&prop->len);
-
-    return prop;
-}
-
-const struct fdt_property *fdt_get_property_by_offset(const void *fdt,
-                              int offset,
-                              int *lenp)
-{
-    /* Prior to version 16, properties may need realignment
-     * and this API does not work. fdt_getprop_*() will, however. */
-
-    if (fdt_version(fdt) < 0x10) {
-        if (lenp)
-            *lenp = -FDT_ERR_BADVERSION;
-        return NULL;
-    }
-
-    return fdt_get_property_by_offset_(fdt, offset, lenp);
-}
-
-static const struct fdt_property *fdt_get_property_namelen_(const void *fdt,
-                                    int offset,
-                                    const char *name,
-                                    int namelen,
-                                int *lenp,
-                                int *poffset)
-{
-    for (offset = fdt_first_property_offset(fdt, offset);
-         (offset >= 0);
-         (offset = fdt_next_property_offset(fdt, offset))) {
-        const struct fdt_property *prop;
-
-        if (!(prop = fdt_get_property_by_offset_(fdt, offset, lenp))) {
-            offset = -FDT_ERR_INTERNAL;
-            break;
-        }
-        if (fdt_string_eq_(fdt, fdt32_ld(&prop->nameoff),
-                   name, namelen)) {
-            if (poffset)
-                *poffset = offset;
-            return prop;
-        }
-    }
-
-    if (lenp)
-        *lenp = offset;
-    return NULL;
-}
-
-
-const struct fdt_property *fdt_get_property_namelen(const void *fdt,
-                            int offset,
-                            const char *name,
-                            int namelen, int *lenp)
-{
-    /* Prior to version 16, properties may need realignment
-     * and this API does not work. fdt_getprop_*() will, however. */
-    if (fdt_version(fdt) < 0x10) {
-        if (lenp)
-            *lenp = -FDT_ERR_BADVERSION;
-        return NULL;
-    }
-
-    return fdt_get_property_namelen_(fdt, offset, name, namelen, lenp,
-                     NULL);
-}
-
-
-const struct fdt_property *fdt_get_property(const void *fdt,
-                        int nodeoffset,
-                        const char *name, int *lenp)
-{
-    return fdt_get_property_namelen(fdt, nodeoffset, name,
-                    strlen(name), lenp);
-}
-
-const void *fdt_getprop_namelen(const void *fdt, int nodeoffset,
-                const char *name, int namelen, int *lenp)
-{
-    int poffset;
-    const struct fdt_property *prop;
-
-    prop = fdt_get_property_namelen_(fdt, nodeoffset, name, namelen, lenp,
-                     &poffset);
-    if (!prop)
-        return NULL;
-
-    /* Handle realignment */
-    if (fdt_version(fdt) < 0x10 && (poffset + sizeof(*prop)) % 8 &&
-        fdt32_ld(&prop->len) >= 8)
-        return prop->data + 4;
-    return prop->data;
-}
-
-const void *fdt_getprop_by_offset(const void *fdt, int offset,
-                  const char **namep, int *lenp)
-{
-    const struct fdt_property *prop;
-
-    prop = fdt_get_property_by_offset_(fdt, offset, lenp);
-    if (!prop)
-        return NULL;
-    if (namep) {
-        const char *name;
-        int namelen;
-        name = fdt_get_string(fdt, fdt32_ld(&prop->nameoff),
-                      &namelen);
-        if (!name) {
-            if (lenp)
-                *lenp = namelen;
-            return NULL;
-        }
-        *namep = name;
-    }
-
-    /* Handle realignment */
-    if (fdt_version(fdt) < 0x10 && (offset + sizeof(*prop)) % 8 &&
-        fdt32_ld(&prop->len) >= 8)
-        return prop->data + 4;
-    return prop->data;
-}
-
-const void *fdt_getprop(const void *fdt, int nodeoffset,
-            const char *name, int *lenp)
-{
-    return fdt_getprop_namelen(fdt, nodeoffset, name, strlen(name), lenp);
-}
-
-uint32_t fdt_get_phandle(const void *fdt, int nodeoffset)
-{
-    const fdt32_t *php;
-    int len;
-
-    /* FIXME: This is a bit sub-optimal, since we potentially scan
-     * over all the properties twice. */
-    php = fdt_getprop(fdt, nodeoffset, "phandle", &len);
-    if (!php || (len != sizeof(*php))) {
-        php = fdt_getprop(fdt, nodeoffset, "linux,phandle", &len);
-        if (!php || (len != sizeof(*php)))
-            return 0;
-    }
-
-    return fdt32_ld(php);
-}
-
-const char *fdt_get_alias_namelen(const void *fdt,
-                  const char *name, int namelen)
-{
-    int aliasoffset;
-
-    aliasoffset = fdt_path_offset(fdt, "/aliases");
-    if (aliasoffset < 0)
-        return NULL;
-
-    return fdt_getprop_namelen(fdt, aliasoffset, name, namelen, NULL);
-}
-
-const char *fdt_get_alias(const void *fdt, const char *name)
-{
-    return fdt_get_alias_namelen(fdt, name, strlen(name));
-}
-
-int fdt_get_path(const void *fdt, int nodeoffset, char *buf, int buflen)
-{
-    int pdepth = 0, p = 0;
-    int offset, depth, namelen;
-    const char *name;
-
-    FDT_RO_PROBE(fdt);
-
-    if (buflen < 2)
-        return -FDT_ERR_NOSPACE;
-
-    for (offset = 0, depth = 0;
-         (offset >= 0) && (offset <= nodeoffset);
-         offset = fdt_next_node(fdt, offset, &depth)) {
-        while (pdepth > depth) {
-            do {
-                p--;
-            } while (buf[p-1] != '/');
-            pdepth--;
-        }
-
-        if (pdepth >= depth) {
-            name = fdt_get_name(fdt, offset, &namelen);
-            if (!name)
-                return namelen;
-            if ((p + namelen + 1) <= buflen) {
-                memcpy(buf + p, name, namelen);
-                p += namelen;
-                buf[p++] = '/';
-                pdepth++;
-            }
-        }
-
-        if (offset == nodeoffset) {
-            if (pdepth < (depth + 1))
-                return -FDT_ERR_NOSPACE;
-
-            if (p > 1) /* special case so that root path is "/", not "" */
-                p--;
-            buf[p] = '\0';
-            return 0;
-        }
-    }
-
-    if ((offset == -FDT_ERR_NOTFOUND) || (offset >= 0))
-        return -FDT_ERR_BADOFFSET;
-    else if (offset == -FDT_ERR_BADOFFSET)
-        return -FDT_ERR_BADSTRUCTURE;
-
-    return offset; /* error from fdt_next_node() */
-}
-
-int fdt_supernode_atdepth_offset(const void *fdt, int nodeoffset,
-                 int supernodedepth, int *nodedepth)
-{
-    int offset, depth;
-    int supernodeoffset = -FDT_ERR_INTERNAL;
-
-    FDT_RO_PROBE(fdt);
-
-    if (supernodedepth < 0)
-        return -FDT_ERR_NOTFOUND;
-
-    for (offset = 0, depth = 0;
-         (offset >= 0) && (offset <= nodeoffset);
-         offset = fdt_next_node(fdt, offset, &depth)) {
-        if (depth == supernodedepth)
-            supernodeoffset = offset;
-
-        if (offset == nodeoffset) {
-            if (nodedepth)
-                *nodedepth = depth;
-
-            if (supernodedepth > depth)
-                return -FDT_ERR_NOTFOUND;
-            else
-                return supernodeoffset;
-        }
-    }
-
-    if ((offset == -FDT_ERR_NOTFOUND) || (offset >= 0))
-        return -FDT_ERR_BADOFFSET;
-    else if (offset == -FDT_ERR_BADOFFSET)
-        return -FDT_ERR_BADSTRUCTURE;
-
-    return offset; /* error from fdt_next_node() */
-}
-
-int fdt_node_depth(const void *fdt, int nodeoffset)
-{
-    int nodedepth;
-    int err;
-
-    err = fdt_supernode_atdepth_offset(fdt, nodeoffset, 0, &nodedepth);
-    if (err)
-        return (err < 0) ? err : -FDT_ERR_INTERNAL;
-    return nodedepth;
-}
-
-int fdt_parent_offset(const void *fdt, int nodeoffset)
-{
-    int nodedepth = fdt_node_depth(fdt, nodeoffset);
-
-    if (nodedepth < 0)
-        return nodedepth;
-    return fdt_supernode_atdepth_offset(fdt, nodeoffset,
-                        nodedepth - 1, NULL);
-}
-
-int fdt_node_offset_by_prop_value(const void *fdt, int startoffset,
-                  const char *propname,
-                  const void *propval, int proplen)
-{
-    int offset;
-    const void *val;
-    int len;
-
-    FDT_RO_PROBE(fdt);
-
-    /* FIXME: The algorithm here is pretty horrible: we scan each
-     * property of a node in fdt_getprop(), then if that didn't
-     * find what we want, we scan over them again making our way
-     * to the next node.  Still it's the easiest to implement
-     * approach; performance can come later. */
-    for (offset = fdt_next_node(fdt, startoffset, NULL);
-         offset >= 0;
-         offset = fdt_next_node(fdt, offset, NULL)) {
-        val = fdt_getprop(fdt, offset, propname, &len);
-        if (val && (len == proplen)
-            && (memcmp(val, propval, len) == 0))
-            return offset;
-    }
-
-    return offset; /* error from fdt_next_node() */
-}
-
-int fdt_node_offset_by_phandle(const void *fdt, uint32_t phandle)
-{
-    int offset;
-
-    if ((phandle == 0) || (phandle == -1))
-        return -FDT_ERR_BADPHANDLE;
-
-    FDT_RO_PROBE(fdt);
-
-    /* FIXME: The algorithm here is pretty horrible: we
-     * potentially scan each property of a node in
-     * fdt_get_phandle(), then if that didn't find what
-     * we want, we scan over them again making our way to the next
-     * node.  Still it's the easiest to implement approach;
-     * performance can come later. */
-    for (offset = fdt_next_node(fdt, -1, NULL);
-         offset >= 0;
-         offset = fdt_next_node(fdt, offset, NULL)) {
-        if (fdt_get_phandle(fdt, offset) == phandle)
-            return offset;
-    }
-
-    return offset; /* error from fdt_next_node() */
-}
-
-int fdt_stringlist_contains(const char *strlist, int listlen, const char *str)
-{
-    int len = strlen(str);
-    const char *p;
-
-    while (listlen >= len) {
-        if (memcmp(str, strlist, len+1) == 0)
-            return 1;
-        p = memchr(strlist, '\0', listlen);
-        if (!p)
-            return 0; /* malformed strlist.. */
-        listlen -= (p-strlist) + 1;
-        strlist = p + 1;
-    }
-    return 0;
-}
-
-int fdt_stringlist_count(const void *fdt, int nodeoffset, const char *property)
-{
-    const char *list, *end;
-    int length, count = 0;
-
-    list = fdt_getprop(fdt, nodeoffset, property, &length);
-    if (!list)
-        return length;
-
-    end = list + length;
-
-    while (list < end) {
-        length = strnlen(list, end - list) + 1;
-
-        /* Abort if the last string isn't properly NUL-terminated. */
-        if (list + length > end)
-            return -FDT_ERR_BADVALUE;
-
-        list += length;
-        count++;
-    }
-
-    return count;
-}
-
-int fdt_stringlist_search(const void *fdt, int nodeoffset, const char *property,
-              const char *string)
-{
-    int length, len, idx = 0;
-    const char *list, *end;
-
-    list = fdt_getprop(fdt, nodeoffset, property, &length);
-    if (!list)
-        return length;
-
-    len = strlen(string) + 1;
-    end = list + length;
-
-    while (list < end) {
-        length = strnlen(list, end - list) + 1;
-
-        /* Abort if the last string isn't properly NUL-terminated. */
-        if (list + length > end)
-            return -FDT_ERR_BADVALUE;
-
-        if (length == len && memcmp(list, string, length) == 0)
-            return idx;
-
-        list += length;
-        idx++;
-    }
-
-    return -FDT_ERR_NOTFOUND;
-}
-
-const char *fdt_stringlist_get(const void *fdt, int nodeoffset,
-                   const char *property, int idx,
-                   int *lenp)
-{
-    const char *list, *end;
-    int length;
-
-    list = fdt_getprop(fdt, nodeoffset, property, &length);
-    if (!list) {
-        if (lenp)
-            *lenp = length;
-
-        return NULL;
-    }
-
-    end = list + length;
-
-    while (list < end) {
-        length = strnlen(list, end - list) + 1;
-
-        /* Abort if the last string isn't properly NUL-terminated. */
-        if (list + length > end) {
-            if (lenp)
-                *lenp = -FDT_ERR_BADVALUE;
-
-            return NULL;
-        }
-
-        if (idx == 0) {
-            if (lenp)
-                *lenp = length - 1;
-
-            return list;
-        }
-
-        list += length;
-        idx--;
-    }
-
-    if (lenp)
-        *lenp = -FDT_ERR_NOTFOUND;
-
-    return NULL;
-}
-
-int fdt_node_check_compatible(const void *fdt, int nodeoffset,
-                  const char *compatible)
-{
-    const void *prop;
-    int len;
-
-    prop = fdt_getprop(fdt, nodeoffset, "compatible", &len);
-    if (!prop)
-        return len;
-
-    return !fdt_stringlist_contains(prop, len, compatible);
-}
-
-int fdt_node_offset_by_compatible(const void *fdt, int startoffset,
-                  const char *compatible)
-{
-    int offset, err;
-
-    FDT_RO_PROBE(fdt);
-
-    /* FIXME: The algorithm here is pretty horrible: we scan each
-     * property of a node in fdt_node_check_compatible(), then if
-     * that didn't find what we want, we scan over them again
-     * making our way to the next node.  Still it's the easiest to
-     * implement approach; performance can come later. */
-    for (offset = fdt_next_node(fdt, startoffset, NULL);
-         offset >= 0;
-         offset = fdt_next_node(fdt, offset, NULL)) {
-        err = fdt_node_check_compatible(fdt, offset, compatible);
-        if ((err < 0) && (err != -FDT_ERR_NOTFOUND))
-            return err;
-        else if (err == 0)
-            return offset;
-    }
-
-    return offset; /* error from fdt_next_node() */
-}
-
-int fdt_check_full(const void *fdt, size_t bufsize)
-{
-    int err;
-    int num_memrsv;
-    int offset, nextoffset = 0;
-    uint32_t tag;
-    unsigned depth = 0;
-    const void *prop;
-    const char *propname;
-
-    if (bufsize < FDT_V1_SIZE)
-        return -FDT_ERR_TRUNCATED;
-    err = fdt_check_header(fdt);
-    if (err != 0)
-        return err;
-    if (bufsize < fdt_totalsize(fdt))
-        return -FDT_ERR_TRUNCATED;
-
-    num_memrsv = fdt_num_mem_rsv(fdt);
-    if (num_memrsv < 0)
-        return num_memrsv;
-
-    while (1) {
-        offset = nextoffset;
-        tag = fdt_next_tag(fdt, offset, &nextoffset);
-
-        if (nextoffset < 0)
-            return nextoffset;
-
-        switch (tag) {
-        case FDT_NOP:
-            break;
-
-        case FDT_END:
-            if (depth != 0)
-                return -FDT_ERR_BADSTRUCTURE;
-            return 0;
-
-        case FDT_BEGIN_NODE:
-            depth++;
-            if (depth > INT_MAX)
-                return -FDT_ERR_BADSTRUCTURE;
-            break;
-
-        case FDT_END_NODE:
-            if (depth == 0)
-                return -FDT_ERR_BADSTRUCTURE;
-            depth--;
-            break;
-
-        case FDT_PROP:
-            prop = fdt_getprop_by_offset(fdt, offset, &propname,
-                             &err);
-            if (!prop)
-                return err;
-            break;
-
-        default:
-            return -FDT_ERR_INTERNAL;
-        }
-    }
-}
diff --git a/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_rw.c b/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_rw.c
deleted file mode 100644
index e9b446b99f..0000000000
--- a/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_rw.c
+++ /dev/null
@@ -1,484 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include "libfdt_env.h"
-
-#include 
-#include 
-
-#include "libfdt_internal.h"
-
-static int fdt_blocks_misordered_(const void *fdt,
-                  int mem_rsv_size, int struct_size)
-{
-    return (fdt_off_mem_rsvmap(fdt) < FDT_ALIGN(sizeof(struct fdt_header), 8))
-        || (fdt_off_dt_struct(fdt) <
-            (fdt_off_mem_rsvmap(fdt) + mem_rsv_size))
-        || (fdt_off_dt_strings(fdt) <
-            (fdt_off_dt_struct(fdt) + struct_size))
-        || (fdt_totalsize(fdt) <
-            (fdt_off_dt_strings(fdt) + fdt_size_dt_strings(fdt)));
-}
-
-static int fdt_rw_probe_(void *fdt)
-{
-    FDT_RO_PROBE(fdt);
-
-    if (fdt_version(fdt) < 17)
-        return -FDT_ERR_BADVERSION;
-    if (fdt_blocks_misordered_(fdt, sizeof(struct fdt_reserve_entry),
-                   fdt_size_dt_struct(fdt)))
-        return -FDT_ERR_BADLAYOUT;
-    if (fdt_version(fdt) > 17)
-        fdt_set_version(fdt, 17);
-
-    return 0;
-}
-
-#define FDT_RW_PROBE(fdt) \
-    { \
-        int err_; \
-        if ((err_ = fdt_rw_probe_(fdt)) != 0) \
-            return err_; \
-    }
-
-static inline int fdt_data_size_(void *fdt)
-{
-    return fdt_off_dt_strings(fdt) + fdt_size_dt_strings(fdt);
-}
-
-static int fdt_splice_(void *fdt, void *splicepoint, int oldlen, int newlen)
-{
-    char *p = splicepoint;
-    char *end = (char *)fdt + fdt_data_size_(fdt);
-
-    if (((p + oldlen) < p) || ((p + oldlen) > end))
-        return -FDT_ERR_BADOFFSET;
-    if ((p < (char *)fdt) || ((end - oldlen + newlen) < (char *)fdt))
-        return -FDT_ERR_BADOFFSET;
-    if ((end - oldlen + newlen) > ((char *)fdt + fdt_totalsize(fdt)))
-        return -FDT_ERR_NOSPACE;
-    memmove(p + newlen, p + oldlen, end - p - oldlen);
-    return 0;
-}
-
-static int fdt_splice_mem_rsv_(void *fdt, struct fdt_reserve_entry *p,
-                   int oldn, int newn)
-{
-    int delta = (newn - oldn) * sizeof(*p);
-    int err;
-    err = fdt_splice_(fdt, p, oldn * sizeof(*p), newn * sizeof(*p));
-    if (err)
-        return err;
-    fdt_set_off_dt_struct(fdt, fdt_off_dt_struct(fdt) + delta);
-    fdt_set_off_dt_strings(fdt, fdt_off_dt_strings(fdt) + delta);
-    return 0;
-}
-
-static int fdt_splice_struct_(void *fdt, void *p,
-                  int oldlen, int newlen)
-{
-    int delta = newlen - oldlen;
-    int err;
-
-    if ((err = fdt_splice_(fdt, p, oldlen, newlen)))
-        return err;
-
-    fdt_set_size_dt_struct(fdt, fdt_size_dt_struct(fdt) + delta);
-    fdt_set_off_dt_strings(fdt, fdt_off_dt_strings(fdt) + delta);
-    return 0;
-}
-
-static int fdt_splice_string_(void *fdt, int newlen)
-{
-    void *p = (char *)fdt
-        + fdt_off_dt_strings(fdt) + fdt_size_dt_strings(fdt);
-    int err;
-
-    if ((err = fdt_splice_(fdt, p, 0, newlen)))
-        return err;
-
-    fdt_set_size_dt_strings(fdt, fdt_size_dt_strings(fdt) + newlen);
-    return 0;
-}
-
-static int fdt_find_add_string_(void *fdt, const char *s)
-{
-    char *strtab = (char *)fdt + fdt_off_dt_strings(fdt);
-    const char *p;
-    char *new;
-    int len = strlen(s) + 1;
-    int err;
-
-    p = fdt_find_string_(strtab, fdt_size_dt_strings(fdt), s);
-    if (p)
-        /* found it */
-        return (p - strtab);
-
-    new = strtab + fdt_size_dt_strings(fdt);
-    err = fdt_splice_string_(fdt, len);
-    if (err)
-        return err;
-
-    memcpy(new, s, len);
-    return (new - strtab);
-}
-
-int fdt_add_mem_rsv(void *fdt, uint64_t address, uint64_t size)
-{
-    struct fdt_reserve_entry *re;
-    int err;
-
-    FDT_RW_PROBE(fdt);
-
-    re = fdt_mem_rsv_w_(fdt, fdt_num_mem_rsv(fdt));
-    err = fdt_splice_mem_rsv_(fdt, re, 0, 1);
-    if (err)
-        return err;
-
-    re->address = cpu_to_fdt64(address);
-    re->size = cpu_to_fdt64(size);
-    return 0;
-}
-
-int fdt_del_mem_rsv(void *fdt, int n)
-{
-    struct fdt_reserve_entry *re = fdt_mem_rsv_w_(fdt, n);
-
-    FDT_RW_PROBE(fdt);
-
-    if (n >= fdt_num_mem_rsv(fdt))
-        return -FDT_ERR_NOTFOUND;
-
-    return fdt_splice_mem_rsv_(fdt, re, 1, 0);
-}
-
-static int fdt_resize_property_(void *fdt, int nodeoffset, const char *name,
-                int len, struct fdt_property **prop)
-{
-    int oldlen;
-    int err;
-
-    *prop = fdt_get_property_w(fdt, nodeoffset, name, &oldlen);
-    if (!*prop)
-        return oldlen;
-
-    if ((err = fdt_splice_struct_(fdt, (*prop)->data, FDT_TAGALIGN(oldlen),
-                      FDT_TAGALIGN(len))))
-        return err;
-
-    (*prop)->len = cpu_to_fdt32(len);
-    return 0;
-}
-
-static int fdt_add_property_(void *fdt, int nodeoffset, const char *name,
-                 int len, struct fdt_property **prop)
-{
-    int proplen;
-    int nextoffset;
-    int namestroff;
-    int err;
-
-    if ((nextoffset = fdt_check_node_offset_(fdt, nodeoffset)) < 0)
-        return nextoffset;
-
-    namestroff = fdt_find_add_string_(fdt, name);
-    if (namestroff < 0)
-        return namestroff;
-
-    *prop = fdt_offset_ptr_w_(fdt, nextoffset);
-    proplen = sizeof(**prop) + FDT_TAGALIGN(len);
-
-    err = fdt_splice_struct_(fdt, *prop, 0, proplen);
-    if (err)
-        return err;
-
-    (*prop)->tag = cpu_to_fdt32(FDT_PROP);
-    (*prop)->nameoff = cpu_to_fdt32(namestroff);
-    (*prop)->len = cpu_to_fdt32(len);
-    return 0;
-}
-
-int fdt_set_name(void *fdt, int nodeoffset, const char *name)
-{
-    char *namep;
-    int oldlen, newlen;
-    int err;
-
-    FDT_RW_PROBE(fdt);
-
-    namep = (char *)(uintptr_t)fdt_get_name(fdt, nodeoffset, &oldlen);
-    if (!namep)
-        return oldlen;
-
-    newlen = strlen(name);
-
-    err = fdt_splice_struct_(fdt, namep, FDT_TAGALIGN(oldlen+1),
-                 FDT_TAGALIGN(newlen+1));
-    if (err)
-        return err;
-
-    memcpy(namep, name, newlen+1);
-    return 0;
-}
-
-int fdt_setprop_placeholder(void *fdt, int nodeoffset, const char *name,
-                int len, void **prop_data)
-{
-    struct fdt_property *prop;
-    int err;
-
-    FDT_RW_PROBE(fdt);
-
-    err = fdt_resize_property_(fdt, nodeoffset, name, len, &prop);
-    if (err == -FDT_ERR_NOTFOUND)
-        err = fdt_add_property_(fdt, nodeoffset, name, len, &prop);
-    if (err)
-        return err;
-
-    *prop_data = prop->data;
-    return 0;
-}
-
-int fdt_setprop(void *fdt, int nodeoffset, const char *name,
-        const void *val, int len)
-{
-    void *prop_data;
-    int err;
-
-    err = fdt_setprop_placeholder(fdt, nodeoffset, name, len, &prop_data);
-    if (err)
-        return err;
-
-    if (len)
-        memcpy(prop_data, val, len);
-    return 0;
-}
-
-int fdt_appendprop(void *fdt, int nodeoffset, const char *name,
-           const void *val, int len)
-{
-    struct fdt_property *prop;
-    int err, oldlen, newlen;
-
-    FDT_RW_PROBE(fdt);
-
-    prop = fdt_get_property_w(fdt, nodeoffset, name, &oldlen);
-    if (prop) {
-        newlen = len + oldlen;
-        err = fdt_splice_struct_(fdt, prop->data,
-                     FDT_TAGALIGN(oldlen),
-                     FDT_TAGALIGN(newlen));
-        if (err)
-            return err;
-        prop->len = cpu_to_fdt32(newlen);
-        memcpy(prop->data + oldlen, val, len);
-    } else {
-        err = fdt_add_property_(fdt, nodeoffset, name, len, &prop);
-        if (err)
-            return err;
-        memcpy(prop->data, val, len);
-    }
-    return 0;
-}
-
-int fdt_delprop(void *fdt, int nodeoffset, const char *name)
-{
-    struct fdt_property *prop;
-    int len, proplen;
-
-    FDT_RW_PROBE(fdt);
-
-    prop = fdt_get_property_w(fdt, nodeoffset, name, &len);
-    if (!prop)
-        return len;
-
-    proplen = sizeof(*prop) + FDT_TAGALIGN(len);
-    return fdt_splice_struct_(fdt, prop, proplen, 0);
-}
-
-int fdt_add_subnode_namelen(void *fdt, int parentoffset,
-                const char *name, int namelen)
-{
-    struct fdt_node_header *nh;
-    int offset, nextoffset;
-    int nodelen;
-    int err;
-    uint32_t tag;
-    fdt32_t *endtag;
-
-    FDT_RW_PROBE(fdt);
-
-    offset = fdt_subnode_offset_namelen(fdt, parentoffset, name, namelen);
-    if (offset >= 0)
-        return -FDT_ERR_EXISTS;
-    else if (offset != -FDT_ERR_NOTFOUND)
-        return offset;
-
-    /* Try to place the new node after the parent's properties */
-    fdt_next_tag(fdt, parentoffset, &nextoffset); /* skip the BEGIN_NODE */
-    do {
-        offset = nextoffset;
-        tag = fdt_next_tag(fdt, offset, &nextoffset);
-    } while ((tag == FDT_PROP) || (tag == FDT_NOP));
-
-    nh = fdt_offset_ptr_w_(fdt, offset);
-    nodelen = sizeof(*nh) + FDT_TAGALIGN(namelen+1) + FDT_TAGSIZE;
-
-    err = fdt_splice_struct_(fdt, nh, 0, nodelen);
-    if (err)
-        return err;
-
-    nh->tag = cpu_to_fdt32(FDT_BEGIN_NODE);
-    memset(nh->name, 0, FDT_TAGALIGN(namelen+1));
-    memcpy(nh->name, name, namelen);
-    endtag = (fdt32_t *)((char *)nh + nodelen - FDT_TAGSIZE);
-    *endtag = cpu_to_fdt32(FDT_END_NODE);
-
-    return offset;
-}
-
-int fdt_add_subnode(void *fdt, int parentoffset, const char *name)
-{
-    return fdt_add_subnode_namelen(fdt, parentoffset, name, strlen(name));
-}
-
-int fdt_del_node(void *fdt, int nodeoffset)
-{
-    int endoffset;
-
-    FDT_RW_PROBE(fdt);
-
-    endoffset = fdt_node_end_offset_(fdt, nodeoffset);
-    if (endoffset < 0)
-        return endoffset;
-
-    return fdt_splice_struct_(fdt, fdt_offset_ptr_w_(fdt, nodeoffset),
-                  endoffset - nodeoffset, 0);
-}
-
-static void fdt_packblocks_(const char *old, char *new,
-                int mem_rsv_size, int struct_size)
-{
-    int mem_rsv_off, struct_off, strings_off;
-
-    mem_rsv_off = FDT_ALIGN(sizeof(struct fdt_header), 8);
-    struct_off = mem_rsv_off + mem_rsv_size;
-    strings_off = struct_off + struct_size;
-
-    memmove(new + mem_rsv_off, old + fdt_off_mem_rsvmap(old), mem_rsv_size);
-    fdt_set_off_mem_rsvmap(new, mem_rsv_off);
-
-    memmove(new + struct_off, old + fdt_off_dt_struct(old), struct_size);
-    fdt_set_off_dt_struct(new, struct_off);
-    fdt_set_size_dt_struct(new, struct_size);
-
-    memmove(new + strings_off, old + fdt_off_dt_strings(old),
-        fdt_size_dt_strings(old));
-    fdt_set_off_dt_strings(new, strings_off);
-    fdt_set_size_dt_strings(new, fdt_size_dt_strings(old));
-}
-
-int fdt_open_into(const void *fdt, void *buf, int bufsize)
-{
-    int err;
-    int mem_rsv_size, struct_size;
-    int newsize;
-    const char *fdtstart = fdt;
-    const char *fdtend = fdtstart + fdt_totalsize(fdt);
-    char *tmp;
-
-    FDT_RO_PROBE(fdt);
-
-    mem_rsv_size = (fdt_num_mem_rsv(fdt)+1)
-        * sizeof(struct fdt_reserve_entry);
-
-    if (fdt_version(fdt) >= 17) {
-        struct_size = fdt_size_dt_struct(fdt);
-    } else {
-        struct_size = 0;
-        while (fdt_next_tag(fdt, struct_size, &struct_size) != FDT_END)
-            ;
-        if (struct_size < 0)
-            return struct_size;
-    }
-
-    if (!fdt_blocks_misordered_(fdt, mem_rsv_size, struct_size)) {
-        /* no further work necessary */
-        err = fdt_move(fdt, buf, bufsize);
-        if (err)
-            return err;
-        fdt_set_version(buf, 17);
-        fdt_set_size_dt_struct(buf, struct_size);
-        fdt_set_totalsize(buf, bufsize);
-        return 0;
-    }
-
-    /* Need to reorder */
-    newsize = FDT_ALIGN(sizeof(struct fdt_header), 8) + mem_rsv_size
-        + struct_size + fdt_size_dt_strings(fdt);
-
-    if (bufsize < newsize)
-        return -FDT_ERR_NOSPACE;
-
-    /* First attempt to build converted tree at beginning of buffer */
-    tmp = buf;
-    /* But if that overlaps with the old tree... */
-    if (((tmp + newsize) > fdtstart) && (tmp < fdtend)) {
-        /* Try right after the old tree instead */
-        tmp = (char *)(uintptr_t)fdtend;
-        if ((tmp + newsize) > ((char *)buf + bufsize))
-            return -FDT_ERR_NOSPACE;
-    }
-
-    fdt_packblocks_(fdt, tmp, mem_rsv_size, struct_size);
-    memmove(buf, tmp, newsize);
-
-    fdt_set_magic(buf, FDT_MAGIC);
-    fdt_set_totalsize(buf, bufsize);
-    fdt_set_version(buf, 17);
-    fdt_set_last_comp_version(buf, 16);
-    fdt_set_boot_cpuid_phys(buf, fdt_boot_cpuid_phys(fdt));
-
-    return 0;
-}
-
-int fdt_pack(void *fdt)
-{
-    int mem_rsv_size;
-
-    FDT_RW_PROBE(fdt);
-
-    mem_rsv_size = (fdt_num_mem_rsv(fdt)+1)
-        * sizeof(struct fdt_reserve_entry);
-    fdt_packblocks_(fdt, fdt, mem_rsv_size, fdt_size_dt_struct(fdt));
-    fdt_set_totalsize(fdt, fdt_data_size_(fdt));
-
-    return 0;
-}
diff --git a/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_strerror.c b/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_strerror.c
deleted file mode 100644
index 92853fe6a2..0000000000
--- a/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_strerror.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include "libfdt_env.h"
-
-#include 
-#include 
-
-#include "libfdt_internal.h"
-
-struct fdt_errtabent {
-    const char *str;
-};
-
-#define FDT_ERRTABENT(val) \
-    [(val)] = { .str = #val, }
-
-static struct fdt_errtabent fdt_errtable[] = {
-    FDT_ERRTABENT(FDT_ERR_NOTFOUND),
-    FDT_ERRTABENT(FDT_ERR_EXISTS),
-    FDT_ERRTABENT(FDT_ERR_NOSPACE),
-
-    FDT_ERRTABENT(FDT_ERR_BADOFFSET),
-    FDT_ERRTABENT(FDT_ERR_BADPATH),
-    FDT_ERRTABENT(FDT_ERR_BADPHANDLE),
-    FDT_ERRTABENT(FDT_ERR_BADSTATE),
-
-    FDT_ERRTABENT(FDT_ERR_TRUNCATED),
-    FDT_ERRTABENT(FDT_ERR_BADMAGIC),
-    FDT_ERRTABENT(FDT_ERR_BADVERSION),
-    FDT_ERRTABENT(FDT_ERR_BADSTRUCTURE),
-    FDT_ERRTABENT(FDT_ERR_BADLAYOUT),
-    FDT_ERRTABENT(FDT_ERR_INTERNAL),
-    FDT_ERRTABENT(FDT_ERR_BADNCELLS),
-    FDT_ERRTABENT(FDT_ERR_BADVALUE),
-    FDT_ERRTABENT(FDT_ERR_BADOVERLAY),
-    FDT_ERRTABENT(FDT_ERR_NOPHANDLES),
-};
-#define FDT_ERRTABSIZE  (sizeof(fdt_errtable) / sizeof(fdt_errtable[0]))
-
-const char *fdt_strerror(int errval)
-{
-    if (errval > 0)
-        return "";
-    else if (errval == 0)
-        return "";
-    else if (errval > -FDT_ERRTABSIZE) {
-        const char *s = fdt_errtable[-errval].str;
-
-        if (s)
-            return s;
-    }
-
-    return "";
-}
diff --git a/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_sw.c b/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_sw.c
deleted file mode 100644
index a16d4c3f38..0000000000
--- a/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_sw.c
+++ /dev/null
@@ -1,344 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include "libfdt_env.h"
-
-#include 
-#include 
-
-#include "libfdt_internal.h"
-
-static int fdt_sw_probe_(void *fdt)
-{
-    if (fdt_magic(fdt) == FDT_MAGIC)
-        return -FDT_ERR_BADSTATE;
-    else if (fdt_magic(fdt) != FDT_SW_MAGIC)
-        return -FDT_ERR_BADMAGIC;
-    return 0;
-}
-
-#define FDT_SW_PROBE(fdt) \
-    { \
-        int err; \
-        if ((err = fdt_sw_probe_(fdt)) != 0) \
-            return err; \
-    }
-
-/* 'memrsv' state:  Initial state after fdt_create()
- *
- * Allowed functions:
- *  fdt_add_reservmap_entry()
- *  fdt_finish_reservemap()     [moves to 'struct' state]
- */
-static int fdt_sw_probe_memrsv_(void *fdt)
-{
-    int err = fdt_sw_probe_(fdt);
-    if (err)
-        return err;
-
-    if (fdt_off_dt_strings(fdt) != 0)
-        return -FDT_ERR_BADSTATE;
-    return 0;
-}
-
-#define FDT_SW_PROBE_MEMRSV(fdt) \
-    { \
-        int err; \
-        if ((err = fdt_sw_probe_memrsv_(fdt)) != 0) \
-            return err; \
-    }
-
-/* 'struct' state:  Enter this state after fdt_finish_reservemap()
- *
- * Allowed functions:
- *  fdt_begin_node()
- *  fdt_end_node()
- *  fdt_property*()
- *  fdt_finish()            [moves to 'complete' state]
- */
-static int fdt_sw_probe_struct_(void *fdt)
-{
-    int err = fdt_sw_probe_(fdt);
-    if (err)
-        return err;
-
-    if (fdt_off_dt_strings(fdt) != fdt_totalsize(fdt))
-        return -FDT_ERR_BADSTATE;
-    return 0;
-}
-
-#define FDT_SW_PROBE_STRUCT(fdt) \
-    { \
-        int err; \
-        if ((err = fdt_sw_probe_struct_(fdt)) != 0) \
-            return err; \
-    }
-
-/* 'complete' state:    Enter this state after fdt_finish()
- *
- * Allowed functions: none
- */
-
-static void *fdt_grab_space_(void *fdt, size_t len)
-{
-    int offset = fdt_size_dt_struct(fdt);
-    int spaceleft;
-
-    spaceleft = fdt_totalsize(fdt) - fdt_off_dt_struct(fdt)
-        - fdt_size_dt_strings(fdt);
-
-    if ((offset + len < offset) || (offset + len > spaceleft))
-        return NULL;
-
-    fdt_set_size_dt_struct(fdt, offset + len);
-    return fdt_offset_ptr_w_(fdt, offset);
-}
-
-int fdt_create(void *buf, int bufsize)
-{
-    const size_t hdrsize = FDT_ALIGN(sizeof(struct fdt_header),
-                     sizeof(struct fdt_reserve_entry));
-    void *fdt = buf;
-
-    if (bufsize < hdrsize)
-        return -FDT_ERR_NOSPACE;
-
-    memset(buf, 0, bufsize);
-
-    fdt_set_magic(fdt, FDT_SW_MAGIC);
-    fdt_set_version(fdt, FDT_LAST_SUPPORTED_VERSION);
-    fdt_set_last_comp_version(fdt, FDT_FIRST_SUPPORTED_VERSION);
-    fdt_set_totalsize(fdt,  bufsize);
-
-    fdt_set_off_mem_rsvmap(fdt, hdrsize);
-    fdt_set_off_dt_struct(fdt, fdt_off_mem_rsvmap(fdt));
-    fdt_set_off_dt_strings(fdt, 0);
-
-    return 0;
-}
-
-int fdt_resize(void *fdt, void *buf, int bufsize)
-{
-    size_t headsize, tailsize;
-    char *oldtail, *newtail;
-
-    FDT_SW_PROBE(fdt);
-
-    headsize = fdt_off_dt_struct(fdt) + fdt_size_dt_struct(fdt);
-    tailsize = fdt_size_dt_strings(fdt);
-
-    if ((headsize + tailsize) > fdt_totalsize(fdt))
-        return -FDT_ERR_INTERNAL;
-
-    if ((headsize + tailsize) > bufsize)
-        return -FDT_ERR_NOSPACE;
-
-    oldtail = (char *)fdt + fdt_totalsize(fdt) - tailsize;
-    newtail = (char *)buf + bufsize - tailsize;
-
-    /* Two cases to avoid clobbering data if the old and new
-     * buffers partially overlap */
-    if (buf <= fdt) {
-        memmove(buf, fdt, headsize);
-        memmove(newtail, oldtail, tailsize);
-    } else {
-        memmove(newtail, oldtail, tailsize);
-        memmove(buf, fdt, headsize);
-    }
-
-    fdt_set_totalsize(buf, bufsize);
-    if (fdt_off_dt_strings(buf))
-        fdt_set_off_dt_strings(buf, bufsize);
-
-    return 0;
-}
-
-int fdt_add_reservemap_entry(void *fdt, uint64_t addr, uint64_t size)
-{
-    struct fdt_reserve_entry *re;
-    int offset;
-
-    FDT_SW_PROBE_MEMRSV(fdt);
-
-    offset = fdt_off_dt_struct(fdt);
-    if ((offset + sizeof(*re)) > fdt_totalsize(fdt))
-        return -FDT_ERR_NOSPACE;
-
-    re = (struct fdt_reserve_entry *)((char *)fdt + offset);
-    re->address = cpu_to_fdt64(addr);
-    re->size = cpu_to_fdt64(size);
-
-    fdt_set_off_dt_struct(fdt, offset + sizeof(*re));
-
-    return 0;
-}
-
-int fdt_finish_reservemap(void *fdt)
-{
-    int err = fdt_add_reservemap_entry(fdt, 0, 0);
-
-    if (err)
-        return err;
-
-    fdt_set_off_dt_strings(fdt, fdt_totalsize(fdt));
-    return 0;
-}
-
-int fdt_begin_node(void *fdt, const char *name)
-{
-    struct fdt_node_header *nh;
-    int namelen;
-
-    FDT_SW_PROBE_STRUCT(fdt);
-
-    namelen = strlen(name) + 1;
-    nh = fdt_grab_space_(fdt, sizeof(*nh) + FDT_TAGALIGN(namelen));
-    if (! nh)
-        return -FDT_ERR_NOSPACE;
-
-    nh->tag = cpu_to_fdt32(FDT_BEGIN_NODE);
-    memcpy(nh->name, name, namelen);
-    return 0;
-}
-
-int fdt_end_node(void *fdt)
-{
-    fdt32_t *en;
-
-    FDT_SW_PROBE_STRUCT(fdt);
-
-    en = fdt_grab_space_(fdt, FDT_TAGSIZE);
-    if (! en)
-        return -FDT_ERR_NOSPACE;
-
-    *en = cpu_to_fdt32(FDT_END_NODE);
-    return 0;
-}
-
-static int fdt_find_add_string_(void *fdt, const char *s)
-{
-    char *strtab = (char *)fdt + fdt_totalsize(fdt);
-    const char *p;
-    int strtabsize = fdt_size_dt_strings(fdt);
-    int len = strlen(s) + 1;
-    int struct_top, offset;
-
-    p = fdt_find_string_(strtab - strtabsize, strtabsize, s);
-    if (p)
-        return p - strtab;
-
-    /* Add it */
-    offset = -strtabsize - len;
-    struct_top = fdt_off_dt_struct(fdt) + fdt_size_dt_struct(fdt);
-    if (fdt_totalsize(fdt) + offset < struct_top)
-        return 0; /* no more room :( */
-
-    memcpy(strtab + offset, s, len);
-    fdt_set_size_dt_strings(fdt, strtabsize + len);
-    return offset;
-}
-
-int fdt_property_placeholder(void *fdt, const char *name, int len, void **valp)
-{
-    struct fdt_property *prop;
-    int nameoff;
-
-    FDT_SW_PROBE_STRUCT(fdt);
-
-    nameoff = fdt_find_add_string_(fdt, name);
-    if (nameoff == 0)
-        return -FDT_ERR_NOSPACE;
-
-    prop = fdt_grab_space_(fdt, sizeof(*prop) + FDT_TAGALIGN(len));
-    if (! prop)
-        return -FDT_ERR_NOSPACE;
-
-    prop->tag = cpu_to_fdt32(FDT_PROP);
-    prop->nameoff = cpu_to_fdt32(nameoff);
-    prop->len = cpu_to_fdt32(len);
-    *valp = prop->data;
-    return 0;
-}
-
-int fdt_property(void *fdt, const char *name, const void *val, int len)
-{
-    void *ptr;
-    int ret;
-
-    ret = fdt_property_placeholder(fdt, name, len, &ptr);
-    if (ret)
-        return ret;
-    memcpy(ptr, val, len);
-    return 0;
-}
-
-int fdt_finish(void *fdt)
-{
-    char *p = (char *)fdt;
-    fdt32_t *end;
-    int oldstroffset, newstroffset;
-    uint32_t tag;
-    int offset, nextoffset;
-
-    FDT_SW_PROBE_STRUCT(fdt);
-
-    /* Add terminator */
-    end = fdt_grab_space_(fdt, sizeof(*end));
-    if (! end)
-        return -FDT_ERR_NOSPACE;
-    *end = cpu_to_fdt32(FDT_END);
-
-    /* Relocate the string table */
-    oldstroffset = fdt_totalsize(fdt) - fdt_size_dt_strings(fdt);
-    newstroffset = fdt_off_dt_struct(fdt) + fdt_size_dt_struct(fdt);
-    memmove(p + newstroffset, p + oldstroffset, fdt_size_dt_strings(fdt));
-    fdt_set_off_dt_strings(fdt, newstroffset);
-
-    /* Walk the structure, correcting string offsets */
-    offset = 0;
-    while ((tag = fdt_next_tag(fdt, offset, &nextoffset)) != FDT_END) {
-        if (tag == FDT_PROP) {
-            struct fdt_property *prop =
-                fdt_offset_ptr_w_(fdt, offset);
-            int nameoff;
-
-            nameoff = fdt32_to_cpu(prop->nameoff);
-            nameoff += fdt_size_dt_strings(fdt);
-            prop->nameoff = cpu_to_fdt32(nameoff);
-        }
-        offset = nextoffset;
-    }
-    if (nextoffset < 0)
-        return nextoffset;
-
-    /* Finally, adjust the header */
-    fdt_set_totalsize(fdt, newstroffset + fdt_size_dt_strings(fdt));
-    fdt_set_magic(fdt, FDT_MAGIC);
-    return 0;
-}
diff --git a/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_wip.c b/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_wip.c
deleted file mode 100644
index e97f282851..0000000000
--- a/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_wip.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include "libfdt_env.h"
-
-#include 
-#include 
-
-#include "libfdt_internal.h"
-
-int fdt_setprop_inplace_namelen_partial(void *fdt, int nodeoffset,
-                    const char *name, int namelen,
-                    uint32_t idx, const void *val,
-                    int len)
-{
-    void *propval;
-    int proplen;
-
-    propval = fdt_getprop_namelen_w(fdt, nodeoffset, name, namelen,
-                    &proplen);
-    if (!propval)
-        return proplen;
-
-    if (proplen < (len + idx))
-        return -FDT_ERR_NOSPACE;
-
-    memcpy((char *)propval + idx, val, len);
-    return 0;
-}
-
-int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name,
-            const void *val, int len)
-{
-    const void *propval;
-    int proplen;
-
-    propval = fdt_getprop(fdt, nodeoffset, name, &proplen);
-    if (!propval)
-        return proplen;
-
-    if (proplen != len)
-        return -FDT_ERR_NOSPACE;
-
-    return fdt_setprop_inplace_namelen_partial(fdt, nodeoffset, name,
-                           strlen(name), 0,
-                           val, len);
-}
-
-static void fdt_nop_region_(void *start, int len)
-{
-    fdt32_t *p;
-
-    for (p = start; (char *)p < ((char *)start + len); p++)
-        *p = cpu_to_fdt32(FDT_NOP);
-}
-
-int fdt_nop_property(void *fdt, int nodeoffset, const char *name)
-{
-    struct fdt_property *prop;
-    int len;
-
-    prop = fdt_get_property_w(fdt, nodeoffset, name, &len);
-    if (!prop)
-        return len;
-
-    fdt_nop_region_(prop, len + sizeof(*prop));
-
-    return 0;
-}
-
-int fdt_node_end_offset_(void *fdt, int offset)
-{
-    int depth = 0;
-
-    while ((offset >= 0) && (depth >= 0))
-        offset = fdt_next_node(fdt, offset, &depth);
-
-    return offset;
-}
-
-int fdt_nop_node(void *fdt, int nodeoffset)
-{
-    int endoffset;
-
-    endoffset = fdt_node_end_offset_(fdt, nodeoffset);
-    if (endoffset < 0)
-        return endoffset;
-
-    fdt_nop_region_(fdt_offset_ptr_w(fdt, nodeoffset, 0),
-            endoffset - nodeoffset);
-    return 0;
-}
diff --git a/bsp/bl808/m0/libraries/stage/blfdt/test/blfdt_cli_test.c b/bsp/bl808/m0/libraries/stage/blfdt/test/blfdt_cli_test.c
deleted file mode 100644
index e0e7ddd421..0000000000
--- a/bsp/bl808/m0/libraries/stage/blfdt/test/blfdt_cli_test.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#ifdef CONFIG_CLI_CMD_ENABLE
-#include 
-#endif
-
-#include 
-#include 
-
-static void blfdt(char *buf, int len, int argc, char **argv)
-{
-    int tc_fdt_wifi(void);
-    int tc_blfdtdump(void);
-
-    tc_fdt_wifi();
-    tc_blfdtdump();
-}
-
-#ifdef CONFIG_CLI_CMD_ENABLE
-// STATIC_CLI_CMD_ATTRIBUTE makes this(these) command(s) static
-const static struct cli_command cmds_user[] STATIC_CLI_CMD_ATTRIBUTE = {
-    { "blfdt", "blfdt", blfdt}
-};
-#endif
-
-int blfdt_cli_init(void)
-{
-    // static command(s) do NOT need to call aos_cli_register_command(s) to register.
-    // However, calling aos_cli_register_command(s) here is OK but is of no effect as cmds_user are included in cmds list.
-    // XXX NOTE: Calling this *empty* function is necessary to make cmds_user in this file to be kept in the final link.
-    //return aos_cli_register_commands(cmds_user, sizeof(cmds_user)/sizeof(cmds_user[0]));
-    return 0;
-}
diff --git a/bsp/bl808/m0/libraries/stage/blfdt/test/tc_blfdt_dump.c b/bsp/bl808/m0/libraries/stage/blfdt/test/tc_blfdt_dump.c
deleted file mode 100644
index a352974456..0000000000
--- a/bsp/bl808/m0/libraries/stage/blfdt/test/tc_blfdt_dump.c
+++ /dev/null
@@ -1,766 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/*
- * fdtdump.c - Contributed by Pantelis Antoniou 
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#include 
-
-#include 
-// #include "log/log.h"
-
-#define FDT_MAGIC_SIZE    4
-#define MAX_VERSION 17
-
-#define ALIGN(x, a)    (((x) + ((a) - 1)) & ~((a) - 1))
-#define PALIGN(p, a)    ((void *)(ALIGN((unsigned long)(p), (a))))
-#define GET_CELL(p)    (p += 4, *((const fdt32_t *)(p-4)))
-
-#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
-
-static const char *tagname(uint32_t tag)
-{
-    static const char * const names[] = {
-#define TN(t) [t] = #t
-        TN(FDT_BEGIN_NODE),
-        TN(FDT_END_NODE),
-        TN(FDT_PROP),
-        TN(FDT_NOP),
-        TN(FDT_END),
-#undef TN
-    };
-    if (tag < ARRAY_SIZE(names)) {
-        if (names[tag]) {
-            return names[tag];
-        }
-    }
-
-    return "FDT_???";
-}
-
-#define dumpf(fmt, args...) \
-    do { if (debug) printf("// " fmt, ## args); } while (0)
-
-bool util_is_printable_string(const void *data, int len)
-{
-    const char *s = data;
-    const char *ss, *se;
-
-    /* zero length is not */
-    if (len == 0) {
-        return 0;
-    }
-
-    /* must terminate with zero */
-    if (s[len - 1] != '\0') {
-        return 0;
-    }
-
-    se = s + len;
-
-    while (s < se) {
-        ss = s;
-        while (s < se && *s && isprint((unsigned char)*s)) {
-            s++;
-        }
-
-        /* not zero, or not done yet */
-        if (*s != '\0' || s == ss) {
-            return 0;
-        }
-
-        s++;
-    }
-
-    return 1;
-}
-
-void utilfdt_print_data(const char *data, int len)
-{
-    int i;
-    const char *s;
-
-    /* no data, don't print */
-    if (len == 0) {
-        return;
-    }
-
-    if (util_is_printable_string(data, len)) {
-        printf(" = ");
-
-        s = data;
-        do {
-            printf("\"%s\"", s);
-            s += strlen(s) + 1;
-            if (s < data + len)
-                printf(", ");
-        } while (s < data + len);
-
-    } else if ((len % 4) == 0) {
-        const fdt32_t *cell = (const fdt32_t *)data;
-
-        printf(" = <");
-        for (i = 0, len /= 4; i < len; i++) {
-            printf("0x%08x%s", (unsigned int)fdt32_to_cpu(cell[i]),
-                   i < (len - 1) ? " " : "");
-        }
-        printf(">");
-    } else {
-        const unsigned char *p = (const unsigned char *)data;
-        printf(" = [");
-        for (i = 0; i < len; i++) {
-            printf("%02x%s", *p++, i < len - 1 ? " " : "");
-        }
-        printf("]");
-    }
-}
-
-static void dump_blob(void *blob, bool debug)
-{
-    uintptr_t blob_off = (uintptr_t)blob;
-    struct fdt_header *bph = blob;
-    uint32_t off_mem_rsvmap = fdt32_to_cpu(bph->off_mem_rsvmap);
-    uint32_t off_dt = fdt32_to_cpu(bph->off_dt_struct);
-    uint32_t off_str = fdt32_to_cpu(bph->off_dt_strings);
-    struct fdt_reserve_entry *p_rsvmap =
-        (struct fdt_reserve_entry *)((char *)blob + off_mem_rsvmap);
-    const char *p_struct = (const char *)blob + off_dt;
-    const char *p_strings = (const char *)blob + off_str;
-    uint32_t version = fdt32_to_cpu(bph->version);
-    uint32_t totalsize = fdt32_to_cpu(bph->totalsize);
-    uint32_t tag;
-    const char *p, *s, *t;
-    int depth, sz, shift;
-    int i;
-    uint64_t addr, size;
-
-    depth = 0;
-    shift = 4;
-
-    printf("/dts-v1/;\r\n");
-    printf("// magic:\t\t0x%"PRIx32"\r\n", fdt32_to_cpu(bph->magic));
-    printf("// totalsize:\t\t0x%"PRIx32" (%"PRIu32")\r\n",
-           totalsize, totalsize);
-    printf("// off_dt_struct:\t0x%"PRIx32"\r\n", off_dt);
-    printf("// off_dt_strings:\t0x%"PRIx32"\r\n", off_str);
-    printf("// off_mem_rsvmap:\t0x%"PRIx32"\r\n", off_mem_rsvmap);
-    printf("// version:\t\t%"PRIu32"\r\n", version);
-    printf("// last_comp_version:\t%"PRIu32"\r\n",
-           fdt32_to_cpu(bph->last_comp_version));
-    if (version >= 2) {
-        printf("// boot_cpuid_phys:\t0x%"PRIx32"\r\n",
-               fdt32_to_cpu(bph->boot_cpuid_phys));
-    }
-
-    if (version >= 3) {
-        printf("// size_dt_strings:\t0x%"PRIx32"\r\n",
-               fdt32_to_cpu(bph->size_dt_strings));
-    }
-
-    if (version >= 17) {
-        printf("// size_dt_struct:\t0x%"PRIx32"\r\n",
-               fdt32_to_cpu(bph->size_dt_struct));
-    }
-
-    printf("\r\n");
-
-    for (i = 0; ; i++) {
-        addr = fdt64_to_cpu(p_rsvmap[i].address);
-        size = fdt64_to_cpu(p_rsvmap[i].size);
-        if (addr == 0 && size == 0)
-            break;
-
-        printf("/memreserve/ %#"PRIx64" %#"PRIx64";\r\n",
-               addr, size);
-    }
-
-    p = p_struct;
-
-    // uint32_t index = 0;
-    while ((tag = fdt32_to_cpu(GET_CELL(p))) != FDT_END) {
-
-        // printf("index = %d\r\n", index++);
-        dumpf("%04"PRIxPTR": tag: 0x%08"PRIx32" (%s)\r\n",
-                (uintptr_t)p - blob_off - 4, tag, tagname(tag));
-
-        if (tag == FDT_BEGIN_NODE) {
-            s = p;
-            p = PALIGN(p + strlen(s) + 1, 4);
-
-            if (*s == '\0')
-                s = "/";
-
-            printf("%*s%s {\r\n", depth * shift, "", s);
-
-            depth++;
-            continue;
-        }
-
-        if (tag == FDT_END_NODE) {
-            depth--;
-
-            printf("%*s};\r\n", depth * shift, "");
-            continue;
-        }
-
-        if (tag == FDT_NOP) {
-            printf("%*s// [NOP]\r\n", depth * shift, "");
-            continue;
-        }
-
-        if (tag != FDT_PROP) {
-            log_error("%*s ** Unknown tag 0x%08"PRIx32"\r\n", depth * shift, "", tag);
-            break;
-        }
-        sz = fdt32_to_cpu(GET_CELL(p));
-        s = p_strings + fdt32_to_cpu(GET_CELL(p));
-        if (version < 16 && sz >= 8)
-            p = PALIGN(p, 8);
-        t = p;
-
-        p = PALIGN(p + sz, 4);
-
-        dumpf("%04"PRIxPTR": string: %s\r\n", (uintptr_t)s - blob_off, s);
-        dumpf("%04"PRIxPTR": value\r\n", (uintptr_t)t - blob_off);
-        printf("%*s%s", depth * shift, "", s);
-        utilfdt_print_data(t, sz);
-        printf(";\r\n");
-    }
-}
-
-
-static bool valid_header(char *p, uint32_t len)
-{
-    if (len < sizeof(struct fdt_header) ||
-        fdt_magic(p) != FDT_MAGIC ||
-        fdt_version(p) > MAX_VERSION ||
-        fdt_last_comp_version(p) > MAX_VERSION ||
-        fdt_totalsize(p) >= len ||
-        fdt_off_dt_struct(p) >= len ||
-        fdt_off_dt_strings(p) >= len) {
-            return 0;
-        }
-        return 1;
-}
-/*
-  input_buf
-  input_len
-  debug   Dump debug information while decoding the file
-  scan    Scan for an embedded fdt in file
-*/
-
-static int blfdtdump(const unsigned char *input_buf, const uint32_t input_len, uint8_t arg_debug, uint8_t arg_scan)
-{
-    const char *file = "fdtbuff";
-    char *buf = (char *)input_buf;
-    uint8_t debug = arg_debug;
-    uint8_t scan = arg_scan;
-    uint32_t len = (uint32_t)input_len;
-    uint32_t this_len = 0;
-
-    // log_info("**** fdtdump is a low-level debugging tool, not meant for general use.\r\n"
-    //         "**** If you want to decompile a dtb, you probably want\r\n"
-    //         "****     dtc -I dtb -O dts \r\n\r\n"
-    //     );
-
-    /* try and locate an embedded fdt in a bigger blob */
-    if (scan) {
-        unsigned char smagic[FDT_MAGIC_SIZE];
-        char *p = buf;
-        char *endp = buf + len;
-
-        fdt_set_magic(smagic, FDT_MAGIC);
-
-        /* poor man's memmem */
-        while ((endp - p) >= FDT_MAGIC_SIZE) {
-            p = memchr(p, smagic[0], endp - p - FDT_MAGIC_SIZE);
-            if (!p) {
-                break;
-            }
-            if (fdt_magic(p) == FDT_MAGIC) {
-                /* try and validate the main struct */
-                this_len = endp - p;
-                if (valid_header(p, this_len)) {
-                    break;
-                }
-                if (debug) {
-                    printf("%s: skipping fdt magic at offset %#tx\r\n",
-                        file, p - buf);
-                }
-            }
-            ++p;
-        }
-        if (!p || endp - p < sizeof(struct fdt_header)) {
-            log_error("%s: could not locate fdt magic\r\n", file);
-            return -1;
-        }
-        printf("%s: found fdt at offset %#tx\r\n", file, p - buf);
-        buf = p;
-    } else if (!valid_header(buf, len)) {
-        log_error("%s: header is not valid\r\n", file);
-        return -1;
-    }
-
-    log_info("dump_blob.");
-
-    dump_blob(buf, debug);
-
-    return 0;
-}
-
-#define TC_WIFI_DTB_LEN    (4779 + 4)
-const uint8_t tc_wifi_dtb[TC_WIFI_DTB_LEN] = {
-  0xd0, 0x0d, 0xfe, 0xed, 0x00, 0x00, 0x12, 0xab, 0x00, 0x00, 0x00, 0x38,
-  0x00, 0x00, 0x10, 0xc0, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x11,
-  0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xeb,
-  0x00, 0x00, 0x10, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x13,
-  0x00, 0x00, 0x00, 0x00, 0x62, 0x6c, 0x20, 0x62, 0x6c, 0x36, 0x30, 0x78,
-  0x20, 0x41, 0x56, 0x42, 0x20, 0x62, 0x6f, 0x61, 0x72, 0x64, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x06,
-  0x62, 0x6c, 0x2c, 0x62, 0x6c, 0x36, 0x30, 0x78, 0x2d, 0x73, 0x61, 0x6d,
-  0x70, 0x6c, 0x65, 0x00, 0x62, 0x6c, 0x2c, 0x62, 0x6c, 0x36, 0x30, 0x78,
-  0x2d, 0x63, 0x6f, 0x6d, 0x6d, 0x6f, 0x6e, 0x00, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x01,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x20,
-  0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x69, 0x70, 0x63, 0x00,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x11,
-  0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
-  0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01,
-  0x69, 0x70, 0x63, 0x40, 0x34, 0x30, 0x30, 0x31, 0x43, 0x30, 0x30, 0x30,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08,
-  0x00, 0x00, 0x00, 0x2c, 0x64, 0x69, 0x73, 0x61, 0x62, 0x6c, 0x65, 0x00,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x33,
-  0x40, 0x01, 0xc0, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x02,
-  0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, 0x69, 0x32, 0x73, 0x00,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x11,
-  0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
-  0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01,
-  0x69, 0x32, 0x73, 0x40, 0x34, 0x30, 0x30, 0x31, 0x37, 0x30, 0x30, 0x30,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x05,
-  0x00, 0x00, 0x00, 0x2c, 0x6f, 0x6b, 0x61, 0x79, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x06,
-  0x62, 0x6c, 0x36, 0x30, 0x78, 0x5f, 0x69, 0x32, 0x73, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x33,
-  0x40, 0x01, 0x70, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x37, 0x6f, 0x6b, 0x61, 0x79,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x70, 0x69, 0x6e, 0x00,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x41,
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-  0x63, 0x68, 0x61, 0x6e, 0x5f, 0x64, 0x65, 0x74, 0x65, 0x63, 0x74, 0x00,
-  0x78, 0x74, 0x61, 0x6c, 0x00, 0x70, 0x77, 0x72, 0x5f, 0x74, 0x61, 0x62,
-  0x6c, 0x65, 0x00, 0x63, 0x68, 0x61, 0x6e, 0x6e, 0x65, 0x6c, 0x5f, 0x64,
-  0x69, 0x76, 0x5f, 0x74, 0x61, 0x62, 0x6c, 0x65, 0x00, 0x63, 0x68, 0x61,
-  0x6e, 0x6e, 0x65, 0x6c, 0x5f, 0x63, 0x6e, 0x74, 0x5f, 0x74, 0x61, 0x62,
-  0x6c, 0x65, 0x00, 0x6c, 0x6f, 0x5f, 0x66, 0x63, 0x61, 0x6c, 0x5f, 0x64,
-  0x69, 0x76, 0x00
-};
-
-int tc_blfdtdump(void)
-{
-    int result;
-
-    result = blfdtdump(tc_wifi_dtb, TC_WIFI_DTB_LEN, true, true);
-
-    if (result) {
-        printf("dump failed\r\n");
-    } else {
-        printf("dump successed\r\n");
-    }
-
-    return result;
-
-    // blfdtdump(tc_wifi_dtb, TC_WIFI_DTB_LEN, false, true);
-    // blfdtdump(tc_wifi_dtb, TC_WIFI_DTB_LEN, false, false);
-}
diff --git a/bsp/bl808/m0/libraries/stage/blfdt/test/tc_blfdt_wifi.c b/bsp/bl808/m0/libraries/stage/blfdt/test/tc_blfdt_wifi.c
deleted file mode 100644
index 2fd04af164..0000000000
--- a/bsp/bl808/m0/libraries/stage/blfdt/test/tc_blfdt_wifi.c
+++ /dev/null
@@ -1,239 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include 
-
-#include 
-// #include "log/log.h"
-
-#define TC_WIFI_DTB_LEN    (4779 + 4)
-extern const uint8_t tc_wifi_dtb[];
-
-static int tc_fdt_wifi_module(void)
-{
-    const void *fdt = (const void *)tc_wifi_dtb;/* const tc_wifi_dtb */
-
-    int wifi_offset = 0;
-    int offset1 = 0;
-
-    const uint32_t *addr_prop = 0;
-    const char *result = 0;
-    int lentmp = 0;
-    int countindex = 0;
-    int i;
-
-    /* get wifi offset */
-    wifi_offset = fdt_subnode_offset(fdt, 0, "wifi");
-    // wifi
-    if (!(wifi_offset > 0)) {
-        log_error("wifi NULL.\r\n");
-        return -1;
-    }
-
-    // wifi->region->country_code = u32
-    offset1 = fdt_subnode_offset(fdt, wifi_offset, "region");
-    if (offset1 > 0) {
-        addr_prop = fdt_getprop(fdt, offset1, "country_code", &lentmp);
-        if (addr_prop) {
-            log_info("value = %ld, lentmp = %d\r\n", fdt32_to_cpu(*addr_prop), lentmp);
-        } else {
-            log_error("country_code NULL.\r\n");
-            return -1;
-        }
-    }
-    // wifi->mac
-    offset1 = fdt_subnode_offset(fdt, wifi_offset, "mac");
-    if (offset1 > 0) {
-        // wifi->mac->sta_mac_addr = hex dump
-        addr_prop = fdt_getprop(fdt, offset1, "sta_mac_addr", &lentmp);
-        if (lentmp == 6) {
-            uint8_t sta_mac[6];
-
-            memcpy(sta_mac, addr_prop, 6);
-            log_info("sta_mac :\r\n");
-            log_buf(sta_mac, 6);
-        } else {
-            log_error("sta_mac_addr NULL.\r\n");
-            return -1;
-        }
-
-        // wifi->mac->ap_mac_addr = hex dump
-        addr_prop = fdt_getprop(fdt, offset1, "ap_mac_addr", &lentmp);
-        if (lentmp == 6) {
-            uint8_t ap_mac[6];
-
-            memcpy(ap_mac, addr_prop, 6);
-            log_info("ap_mac :\r\n");
-            log_buf(ap_mac, 6);
-        }
-    }
-
-    // wifi -> ap
-    offset1 = fdt_subnode_offset(fdt, wifi_offset, "ap");
-    if (offset1 > 0) {
-        // wifi->ap->ssid = string
-        countindex = fdt_stringlist_count(fdt, offset1, "ssid");
-        if (countindex > 0) {
-            for (i = 0; i < countindex; i++) {
-                result = fdt_stringlist_get(fdt, offset1, "ssid", i, &lentmp);
-                if (lentmp > 0) {/* !NULL */
-                    log_info("ap string[%d] = %s, lentmp = %d\r\n", i, result, lentmp);
-                }
-            }
-        } else {
-            log_error("ap NULL.\r\n");
-            return -1;
-        }
-
-        // wifi->ap->pwd = string
-        countindex = fdt_stringlist_count(fdt, offset1, "pwd");
-        if (countindex > 0) {
-            for (i = 0; i < countindex; i++) {
-                result = fdt_stringlist_get(fdt, offset1, "pwd", i, &lentmp);
-                if (lentmp > 0) {/* !NULL */
-
-                    log_info("pwd string[%d] = %s, lentmp = %d\r\n", i, result, lentmp);
-                }
-            }
-        } else {
-            log_error("pwd NULL.\r\n");
-            return -1;
-        }
-
-        // wifi->ap->ap_channel = u32
-        addr_prop = fdt_getprop(fdt, offset1, "ap_channel", &lentmp);
-        if (addr_prop) {
-            log_info("ap_channel = %ld\r\n", fdt32_to_cpu(*addr_prop));
-        } else {
-            log_error("ap_channel NULL.\r\n");
-            return -1;
-        }
-
-        // wifi->ap->auto_chan_detect = dis ? en
-        countindex = fdt_stringlist_count(fdt, offset1, "auto_chan_detect");
-        if (countindex > 0) {
-            for (i = 0; i < countindex; i++) {
-                result = fdt_stringlist_get(fdt, offset1, "auto_chan_detect", i, &lentmp);
-                if (lentmp > 0) {/* !NULL */
-                    log_info("auto_chan_detect string[%d] = %s, lentmp = %d\r\n", i, result, lentmp);
-                }
-            }
-        } else {
-            log_error("auto_chan_detect NULL.\r\n");
-            return -1;
-        }
-    } else {
-        log_error("ap NULL.\r\n");
-        return -1;
-    }
-
-    // wifi -> brd_rf
-    offset1 = fdt_subnode_offset(fdt, wifi_offset, "brd_rf");
-    if (offset1 > 0) {
-        // wifi->brd_rf->xtal = u32 []
-        addr_prop = fdt_getprop(fdt, offset1, "xtal", &lentmp);
-        if (lentmp == 5*4) {
-            uint8_t xtal[5*4];
-
-            memcpy(xtal, addr_prop, 5*4);
-            log_info("xtal :\r\n");
-            log_buf(xtal, 5*4);
-        } else {
-            log_error("xtal NULL.");
-            return -1;
-        }
-        // wifi->brd_rf->pwr_table = u32 []
-        addr_prop = fdt_getprop(fdt, offset1, "pwr_table", &lentmp);
-        if (lentmp == 16*4*4) {
-            uint8_t pwr_table[16*4*4];
-
-            memcpy(pwr_table, addr_prop, 16*4*4);
-            log_info("pwr_table :\r\n");
-            log_buf(pwr_table, 16*4*4);
-        } else {
-            log_error("pwr_table NULL. lentmp = %d.\r\n", lentmp);
-            return -1;
-        }
-        // wifi->brd_rf->channel_div_table = u32 []
-        addr_prop = fdt_getprop(fdt, offset1, "channel_div_table", &lentmp);
-        if (lentmp == 15*4) {
-            uint8_t channel_div_table[15*4];
-
-            memcpy(channel_div_table, addr_prop, 15*4);
-            log_info("channel_div_table :\r\n");
-            log_buf(channel_div_table, 15*4);
-        }  else {
-            log_error("channel_div_table NULL.\r\n");
-            return -1;
-        }
-        // wifi->brd_rf->channel_cnt_table = u32 []
-        addr_prop = fdt_getprop(fdt, offset1, "channel_cnt_table", &lentmp);
-        if (lentmp == 14*4) {
-            uint8_t channel_cnt_table[14*4];
-
-            memcpy(channel_cnt_table, addr_prop, 14*4);
-            log_info("channel_cnt_table :\r\n");
-            log_buf(channel_cnt_table, 14*4);
-        }  else {
-            log_error("channel_cnt_table NULL.\r\n");
-            return -1;
-        }
-        // wifi->brd_rf->lo_fcal_div = u32
-        addr_prop = fdt_getprop(fdt, offset1, "lo_fcal_div", &lentmp);
-        if (lentmp == 1*4) {
-            uint8_t lo_fcal_div[1*4];
-
-            memcpy(lo_fcal_div, addr_prop, 1*4);
-            log_info("lo_fcal_div :\r\n");
-            log_buf(lo_fcal_div, 1*4);
-        }  else {
-            log_error("lo_fcal_div NULL.\r\n");
-            return -1;
-        }
-    } else {
-        log_error("brd_rf NULL.\r\n");
-        return -1;
-    }
-
-    return 0;
-}
-
-int tc_fdt_wifi(void)
-{
-    int result;
-    result = tc_fdt_wifi_module();
-
-    if (result) {
-        printf("fdt wifi module failed\r\n");
-    } else {
-        printf("fdt wifi module successed\r\n");
-    }
-
-    return result;
-}
diff --git a/bsp/bl808/m0/libraries/stage/blfdt/test/tc_dts2dtb.sh b/bsp/bl808/m0/libraries/stage/blfdt/test/tc_dts2dtb.sh
deleted file mode 100644
index 9052b8496e..0000000000
--- a/bsp/bl808/m0/libraries/stage/blfdt/test/tc_dts2dtb.sh
+++ /dev/null
@@ -1,40 +0,0 @@
-#!/bin/sh
-##
-## Copyright (c) 2016-2022 Bouffalolab.
-##
-## This file is part of
-##     *** Bouffalolab Software Dev Kit ***
-##      (see www.bouffalolab.com).
-##
-## Redistribution and use in source and binary forms, with or without modification,
-## are permitted provided that the following conditions are met:
-##   1. Redistributions of source code must retain the above copyright notice,
-##      this list of conditions and the following disclaimer.
-##   2. Redistributions in binary form must reproduce the above copyright notice,
-##      this list of conditions and the following disclaimer in the documentation
-##      and/or other materials provided with the distribution.
-##   3. Neither the name of Bouffalo Lab nor the names of its contributors
-##      may be used to endorse or promote products derived from this software
-##      without specific prior written permission.
-##
-## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-## FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-## DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-## SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-## CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-## OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-## OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-##
-
-curent_dir=$(pwd)
-cd $curent_dir
-echo $curent_dir
-
-echo "tc_wifi.  dts -> dtb"
-dtc -I dts -O dtb -o tc_wifi.dtb tc_wifi.dts
-
-echo "tc_wifi.  dtb -> c"
-xxd -i tc_wifi.dtb tc_wifi.c
diff --git a/bsp/bl808/m0/libraries/stage/blfdt/test/tc_wifi.dts b/bsp/bl808/m0/libraries/stage/blfdt/test/tc_wifi.dts
deleted file mode 100644
index e6a4e0dda6..0000000000
--- a/bsp/bl808/m0/libraries/stage/blfdt/test/tc_wifi.dts
+++ /dev/null
@@ -1,310 +0,0 @@
-
-/*
-    echo "tc_wifi.  dts -> dtb"
-    dtc -I dts -O dtb -o tc_wifi.dtb tc_wifi.dts
-
-    echo "tc_wifi.  dtb -> c"
-    xxd -i tc_wifi.dtb tc_wifi.c
-*/
-
-/dts-v1/;
-
-/ {
-    model = "bl bl60x AVB board";
-    compatible = "bl,bl60x-sample", "bl,bl60x-common";
-    #address-cells = <1>;
-    #size-cells = <1>;
-
-    ipc {
-        #address-cells = <1>;
-        #size-cells = <1>;
-        ipc@4001C000 {
-            status = "disable";
-            reg = <0x4001C000 0x100>;
-        };
-    };
-    i2s {
-        #address-cells = <1>;
-        #size-cells = <1>;
-        i2s@40017000 {
-            status = "okay";
-            compatible = "bl60x_i2s";
-            reg = <0x40017000 0x100>;
-            mclk_only = "okay";
-            pin {
-                mclk = <11>;
-            };
-        };
-        i2s@40017100 {
-            status = "okay";
-            compatible = "bl60x_i2s";
-            reg = <0x40017100 0x100>;
-            mclk_only = "disable";
-            pin {
-                bclk = <12>;
-                fs = <29>;
-                do = <30>;
-                di = <31>;
-            };
-        };
-    };
-    i2c {
-        #address-cells = <1>;
-        #size-cells = <1>;
-        i2c@40011000 {
-            status = "okay";
-            compatible = "bl60x_i2c";
-            reg = <0x40011000 0x100>;
-            pin {
-                scl = <32>;
-                sda = <13>;
-            };
-            devices {
-                list_addr = <0x18 0x21>;
-                list_driver = "i2c_es8311", "i2c_gc0308>";
-            };
-        };
-        i2c@40011100 {
-            status = "disable";
-            compatible = "bl60x_i2c";
-            reg = <0x40011100 0x100>;
-            pin {
-                /*empty here*/
-            };
-        };
-    };
-    mjpeg {
-        #address-cells = <1>;
-        #size-cells = <1>;
-        mjpeg@40016000 {
-            status = "okay";
-            compatible = "bl60x_mjpeg";
-            reg = <0x40016000 0x100>;
-        };
-    };
-    timer {
-        #address-cells = <1>;
-        #size-cells = <1>;
-        timer@40014000 {
-            status = "disable";
-            compatible = "bl60x_timer";
-            reg = <0x40014000 0x100>;
-        };
-        timer@40014100 {
-            status = "disable";
-            compatible = "bl60x_timer";
-            reg = <0x40014100 0x100>;
-        };
-    };
-    pwm {
-        #address-cells = <1>;
-        #size-cells = <1>;
-        pwm@40012000 {
-            status = "disable";
-            compatible = "bl60x_pwm";
-            reg = <0x40012000 0x100>;
-            pin {
-                /*empty here*/
-            };
-        };
-    };
-    uart {
-        #address-cells = <1>;
-        #size-cells = <1>;
-        uart@40010000 {
-            status = "disable";
-            id = <0>;
-            compatible = "bl60x_uart";
-            path = "/dev/ttyS0";
-            reg = <0x40010000 0x100>;
-            baudrate = <115200>;
-            pin {
-                /*empty here*/
-            };
-            feature {
-                rts = "disable";
-                cts = "disable";
-                rx = "disable";
-                tx = "disable";
-            };
-        };
-        uart@40010100 {
-            status = "disable";
-            id = <1>;
-            compatible = "bl60x_uart";
-            path = "/dev/ttyS1";
-            reg = <0x40010100 0x100>;
-            baudrate = <115200>;
-            pin {
-                /*empty here*/
-            };
-            feature {
-                rts = "disable";
-                cts = "disable";
-                rx = "disable";
-                tx = "disable";
-            };
-        };
-        uart@40010200 {
-            status = "okay";
-            id = <2>;
-            compatible = "bl60x_uart";
-            path = "/dev/ttyS2";
-            reg = <0x40010200 0x100>;
-            baudrate = <5000000>;
-            pin {
-                tx = <14>;
-                rx = <7>;
-            };
-            feature {
-                tx = "okay";
-                rx = "okay";
-                cts = "disable";
-                rts = "disable";
-            };
-        };
-    };
-    spi {
-        #address-cells = <1>;
-        #size-cells = <1>;
-        spi@4000F000 {
-            status = "disable";
-            reg = <0x4000F000 0x100>;/* 4KB */
-        };
-    };
-    gpip {
-        #address-cells = <1>;
-        #size-cells = <1>;
-        adc_key {
-            status = "okay";
-            pin = <9>;
-            interrupt  = <3>;
-            key_vol = <0 100 400 300 500>;
-            key_pcb = "SW1", "SW2", "SW3", "SW4","SW5";
-            key_event = "Usr1", "Usr2", "Start", "Up", "Down";
-            key_raw = <1 2 3 4 5>;
-        };
-    };
-    pdm {
-        #address-cells = <1>;
-        #size-cells = <1>;
-        pdm@4000C000 {
-            status = "disable";
-            reg = <0x4000C000 0x100>;/* 256B */
-        };
-    };
-    cam {
-        #address-cells = <1>;
-        #size-cells = <1>;
-        cam@4000B000 {
-            status = "okay";
-            compatible = "bl60x_cam";
-            reg = <0x4000B000 0x1000>;/* 4KB */
-            pin {
-                PIX_CLK = <0>;
-                FRAME_VLD = <1>;
-                LINE_VLD = <2>;
-                PIX_DAT0 = <3>;
-                PIX_DAT1 = <4>;
-                PIX_DAT2 = <5>;
-                PIX_DAT3 = <6>;
-                PIX_DAT4 = <25>;
-                PIX_DAT5 = <26>;
-                PIX_DAT6 = <27>;
-                PIX_DAT7 = <28>;
-                CAM_PWDN = <15>;
-                CAM_REF_CLK = <24>;
-            };
-            feature {
-                mode = "HARDWARE";
-            };
-            conf {
-                sensor = "auto";
-            };
-        };
-    };
-    qspi {
-        #address-cells = <1>;
-        #size-cells = <1>;
-        qspi@4000A000 {
-            status = "disable";
-            reg = <0x4000A000 0x1000>;/* 4KB */
-        };
-    };
-    sdh {
-        #address-cells = <1>;
-        #size-cells = <1>;
-        sdh@40003000 {
-            status = "okay";
-            compatible = "bl60x_sdh";
-            reg = <0x40003000 0x1000>;/* 4KB */
-            pin {
-                clk = <16>;
-                cmd = <17>;
-                dat0 = <18>;
-                dat1 = <19>;
-                dat2 = <20>;
-                dat3 = <21>;
-            };
-        };
-    };
-    wifi {
-        #address-cells = <1>;
-        #size-cells = <1>;
-        region {
-            country_code = <86>;
-        };
-        mac {
-            sta_mac_addr = [C8 43 57 82 73 40];
-            ap_mac_addr = [C8 43 57 82 73 02];
-        };
-        ap {
-            ssid = "BL60x_Camera03";
-            pwd = "1234567890a";
-            ap_channel = <11>;
-            auto_chan_detect = "disable";
-        };
-        brd_rf {
-            xtal = <41 41 0 63 63>;
-            pwr_table = <4 3 3 186>,
-                        <4 3 4 176>,
-                        <4 3 5 167>,
-                        <3 3 0 159>,
-                        <3 3 1 149>,
-                        <3 3 2 140>,
-                        <3 3 3 129>,
-                        <3 3 4 119>,
-                        <3 3 5 110>,
-                        <2 3 0 101>,
-                        <2 3 1 91>,
-                        <2 3 2 82>,
-                        <2 3 3 72>,
-                        <2 3 4 62>,
-                        <2 3 5 52>,
-                        <1 3 3 10>;
-            channel_div_table = <0x14F00000
-                                 0x14FB1C71
-                                 0x150638E3
-                                 0x15115555
-                                 0x151C71C7
-                                 0x15278E38
-                                 0x1532AAAA
-                                 0x153DC71C
-                                 0x1548E38E
-                                 0x15540000
-                                 0x155F1C71
-                                 0x156A38E3
-                                 0x15755555
-                                 0x15900000
-                                 0x15C00000>;
-            channel_cnt_table = <0xa780 0xa7d8
-                                 0xa831 0xa88a
-                                 0xa8e3 0xa93c
-                                 0xa995 0xa9ee
-                                 0xaa47 0xaaa0
-                                 0xaaf8 0xab51
-                                 0xabaa 0xac80>;
-            lo_fcal_div = <0x800>;
-        };
-    };
-};
diff --git a/bsp/bl808/m0/libraries/stage/blog/blog.c b/bsp/bl808/m0/libraries/stage/blog/blog.c
deleted file mode 100644
index fdbcf2b404..0000000000
--- a/bsp/bl808/m0/libraries/stage/blog/blog.c
+++ /dev/null
@@ -1,369 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include 
-#include 
-
-#ifdef CONFIG_CLI_CMD_ENABLE
-#include 
-#endif
-
-#include "blog_type.h"
-#include "blog_cfg.h"
-
-#include 
-
-#if BLOG_TEST
-#include 
-#endif
-
-/* every line log's buffer */
-static char log_buf[BLOG_LINE_BUF_SIZE] = { 0 };
-
-static int findch_sum(const char *str, char ch)
-{
-    int i = 0;
-    int len = strlen(str);
-    int ret = 0;
-
-    for (i = 0; i < len; i++) {
-        if (str[i] == ch) {
-            ret++;
-        }
-    }
-
-    return ret;
-}
-static int set_level(int argc, char **argv)
-{
-    extern char _ld_bl_static_blogcomponent_code_start;
-    extern char _ld_bl_static_blogcomponent_code_end;
-    extern char _ld_bl_static_blogfile_code_start;
-    extern char _ld_bl_static_blogfile_code_end;
-    extern char _ld_bl_static_blogpri_code_start;
-    extern char _ld_bl_static_blogpri_code_end;
-
-    blog_info_t *start;
-    blog_info_t *end;
-    blog_info_t *info;
-
-    int          left;
-    int          right;
-    uint32_t     mid;
-    int          cmp_val;
-    blog_level_t level;
-
-    int ch_sum;
-
-    if (argc != 3) {
-        __blog_printf("arg error.\r\n");
-        return -1;
-    }
-
-    /* get component level */
-    if (0 == strcmp(argv[1], "all")) {
-        level = BLOG_LEVEL_ALL;
-    } else if (0 == strcmp(argv[1], "debug")) {
-        level = BLOG_LEVEL_DEBUG;
-    } else if (0 == strcmp(argv[1], "info")) {
-        level = BLOG_LEVEL_INFO;
-    } else if (0 == strcmp(argv[1], "warn")) {
-        level = BLOG_LEVEL_WARN;
-    } else if (0 == strcmp(argv[1], "error")) {
-        level = BLOG_LEVEL_ERROR;
-    } else if (0 == strcmp(argv[1], "assert")) {
-        level = BLOG_LEVEL_ASSERT;
-    } else if (0 == strcmp(argv[1], "never")) {
-        level = BLOG_LEVEL_NEVER;
-    } else {
-        __blog_printf("input level = %s not support.\r\n", argv[1]);
-        return -1;
-    }
-
-    /* component_name.file_name.pri_name */
-    ch_sum = findch_sum(argv[2], '.');
-
-    if (0 == ch_sum) {
-        start = (blog_info_t *)(&_ld_bl_static_blogcomponent_code_start);
-        end = (blog_info_t *)(&_ld_bl_static_blogcomponent_code_end);
-    } else if (1 == ch_sum) {
-        start = (blog_info_t *)(&_ld_bl_static_blogfile_code_start);
-        end = (blog_info_t *)(&_ld_bl_static_blogfile_code_end);
-    } else if (2 == ch_sum) {
-        start = (blog_info_t *)(&_ld_bl_static_blogpri_code_start);
-        end = (blog_info_t *)(&_ld_bl_static_blogpri_code_end);
-    } else {
-        __blog_printf("input name = %s not support.\r\n", argv[2]);
-        return -1;
-    }
-
-    left  = 0;
-    right = end - start - 1;
-    while (left <= right) {
-        mid = (left + right) >> 1;
-        cmp_val = strcmp(start[mid].name, argv[2]);
-        if (cmp_val < 0) {
-            left = mid + 1;
-        } else if (cmp_val > 0) {
-            right = mid - 1;
-        } else {
-            info = &start[mid];
-            break;
-        }
-    }
-
-    if (left > right) {
-        __blog_printf("input name = %s not find.\r\n", argv[2]);
-        return -1;
-    }
-
-    /* set level */
-    *(info->level) = level;
-    __blog_printf("set %s = %d\r\n", info->name, *(info->level));
-    return 0;
-}
-
-void cmd_blog_set_level(char *buf, int len, int argc, char **argv)
-{
-    if (0 != set_level(argc, argv)) {
-        __blog_printf("set blog error.\r\n");
-    }
-}
-
-void cmd_blog_info_dump(char *buf, int len, int argc, char **argv)
-{
-    blog_info_t *info_c, *info_f, *info_p;
-    char         name_buf[BLOG_NAMELEN_MAX] = {0};
-
-    extern char _ld_bl_static_blogcomponent_code_start;
-    extern char _ld_bl_static_blogcomponent_code_end;
-    extern char _ld_bl_static_blogfile_code_start;
-    extern char _ld_bl_static_blogfile_code_end;
-    extern char _ld_bl_static_blogpri_code_start;
-    extern char _ld_bl_static_blogpri_code_end;
-
-    __blog_printf("blog code1 = %p - %p\r\n", &_ld_bl_static_blogcomponent_code_start, &_ld_bl_static_blogcomponent_code_end);
-    __blog_printf("blog code2 = %p - %p\r\n", &_ld_bl_static_blogfile_code_start, &_ld_bl_static_blogfile_code_end);
-    __blog_printf("blog code3 = %p - %p\r\n", &_ld_bl_static_blogpri_code_start, &_ld_bl_static_blogpri_code_end);
-
-    for (info_c = (blog_info_t *)&_ld_bl_static_blogcomponent_code_start;
-         (uint32_t)info_c < (uint32_t)&_ld_bl_static_blogcomponent_code_end; info_c++) {
-        if (strlen(info_c->name) > BLOG_NAMELEN_MAX) {
-            __blog_printf("name too long.\r\n");
-            return;
-        }
-        if (name_buf[0] != 0) {
-            if (0 == strcmp(name_buf, info_c->name)) {
-#if BLOG_DUMP_DEDUPLICATE
-              continue;
-#endif
-            } else {
-                memset(name_buf, 0, strlen(name_buf));
-            }
-        }
-
-        __blog_printf("[%-48s] = [%d]\r\n", info_c->name, *(info_c->level));
-
-        if ((name_buf[0] != 0) && (strcmp(info_c->name, name_buf) == 0)) {
-            continue;
-        }
-        strcpy(name_buf, info_c->name);
-
-        for (info_f = (blog_info_t *)&_ld_bl_static_blogfile_code_start;
-            (uint32_t)info_f < (uint32_t)&_ld_bl_static_blogfile_code_end; info_f++) {
-
-            if (strstr(info_f->name, info_c->name) == info_f->name) {
-
-                __blog_printf("[%-48s] = [%d]\r\n", info_f->name, *(info_f->level));
-
-                for (info_p = (blog_info_t *)&_ld_bl_static_blogpri_code_start;
-                    (uint32_t)info_p < (uint32_t)&_ld_bl_static_blogpri_code_end; info_p++) {
-
-                    if (strstr(info_p->name, info_f->name) == info_p->name) {
-                        __blog_printf("[%-48s] = [%d]\r\n", info_p->name, *(info_p->level));
-                    }
-                }
-            }
-        }
-    }
-}
-
-#if BLOG_TEST
-void cmd_blog_test(char *buf, int len, int argc, char **argv)
-{
-    blog_testc_init();
-}
-#endif
-
-static void blog_set_poweron_softlevel(void)
-{
-    blog_info_t *info;
-
-    extern char _ld_bl_static_blogcomponent_code_start;
-    extern char _ld_bl_static_blogcomponent_code_end;
-    extern char _ld_bl_static_blogfile_code_start;
-    extern char _ld_bl_static_blogfile_code_end;
-    extern char _ld_bl_static_blogpri_code_start;
-    extern char _ld_bl_static_blogpri_code_end;
-
-    __blog_printf("\r\nblog init set power on level %d, %d, %d.\r\n", BLOG_POWERON_SOFTLEVEL_COMPONENT,
-            BLOG_POWERON_SOFTLEVEL_FILE, BLOG_POWERON_SOFTLEVEL_PRI);
-    for ( info = (blog_info_t *)&_ld_bl_static_blogcomponent_code_start;
-          (uint32_t)info < (uint32_t)&_ld_bl_static_blogcomponent_code_end; info++ ) {
-        *(info->level) = BLOG_POWERON_SOFTLEVEL_COMPONENT;
-    }
-
-    for ( info = (blog_info_t *)&_ld_bl_static_blogfile_code_start;
-          (uint32_t)info < (uint32_t)&_ld_bl_static_blogfile_code_end; info++ ) {
-        *(info->level) = BLOG_POWERON_SOFTLEVEL_FILE;
-    }
-
-    for ( info = (blog_info_t *)&_ld_bl_static_blogpri_code_start;
-          (uint32_t)info < (uint32_t)&_ld_bl_static_blogpri_code_end; info++ ) {
-        *(info->level) = BLOG_POWERON_SOFTLEVEL_PRI;
-    }
-}
-
-/**
- * output log port interface
- *
- * @param log output of log
- * @param size log size
- */
-void blog_port_output(const char *log, size_t size) {
-    /* output to terminal */
-    __blog_printf("%.*s", size, log);
-    //TODO output to flash
-}
-
-/**
- * another copy string function
- *
- * @param cur_len current copied log length, max size is BLOG_LINE_BUF_SIZE
- * @param dst destination
- * @param src source
- *
- * @return copied length
- */
-size_t blog_strcpy(size_t cur_len, char *dst, const char *src) {
-    const char *src_old = src;
-
-    if ((!dst) || (!src)) {
-        __blog_printf("assert.\r\n");
-        return 0;
-    }
-
-    while (*src != 0) {
-        /* make sure destination has enough space */
-        if (cur_len++ < BLOG_LINE_BUF_SIZE) {
-            *dst++ = *src++;
-        } else {
-            break;
-        }
-    }
-    return src - src_old;
-}
-/**
- * dump the hex format data to log
- *
- * @param name name for hex object, it will show on log header
- * @param width hex number for every line, such as: 16, 32
- * @param buf hex buffer
- * @param size buffer size
- */
-void blog_hexdump_out(const char *name, uint8_t width, const uint8_t *buf, uint16_t size)
-{
-#define __is_print(ch)       ((unsigned int)((ch) - ' ') < 127u - ' ')
-
-    uint16_t i, j;
-    uint16_t log_len = 0;
-    char dump_string[8] = {0};
-    int fmt_result;
-
-    /* lock output */
-
-    for (i = 0; i < size; i += width) {
-        /* package header */
-        fmt_result = snprintf(log_buf, BLOG_LINE_BUF_SIZE, "[%s]: %04X-%04X: ", name, i, i + width - 1);
-        /* calculate log length */
-        if ((fmt_result > -1) && (fmt_result <= BLOG_LINE_BUF_SIZE)) {
-            log_len = fmt_result;
-        } else {
-            log_len = BLOG_LINE_BUF_SIZE;
-        }
-        /* dump hex */
-        for (j = 0; j < width; j++) {
-            if (i + j < size) {
-                snprintf(dump_string, sizeof(dump_string), "%02X ", buf[i + j]);
-            } else {
-                strncpy(dump_string, "   ", sizeof(dump_string));
-            }
-            log_len += blog_strcpy(log_len, log_buf + log_len, dump_string);
-            if ((j + 1) % 8 == 0) {
-                log_len += blog_strcpy(log_len, log_buf + log_len, " ");
-            }
-        }
-        log_len += blog_strcpy(log_len, log_buf + log_len, "  ");
-        /* dump char for hex */
-        for (j = 0; j < width; j++) {
-            if (i + j < size) {
-                snprintf(dump_string, sizeof(dump_string), "%c", __is_print(buf[i + j]) ? buf[i + j] : '.');
-                log_len += blog_strcpy(log_len, log_buf + log_len, dump_string);
-            }
-        }
-        /* overflow check and reserve some space for newline sign */
-        if (log_len + strlen("\r\n") > BLOG_LINE_BUF_SIZE) {
-            log_len = BLOG_LINE_BUF_SIZE - strlen("\r\n");
-        }
-        /* package newline sign */
-        log_len += blog_strcpy(log_len, log_buf + log_len, "\r\n");
-
-        /* do log output */
-        blog_port_output(log_buf, log_len);
-    }
-
-    /* unlock output */
-}
-
-void blog_init(void)
-{
-    blog_set_poweron_softlevel();
-}
-
-#ifdef CONFIG_CLI_CMD_ENABLE
-const static struct cli_command cmds_user[] STATIC_CLI_CMD_ATTRIBUTE = {
-    { "blogset", "blog pri set level", cmd_blog_set_level},
-    { "blogdump", "blog info dump", cmd_blog_info_dump},
-#if BLOG_TEST
-    { "blogtest", "blog test", cmd_blog_test},
-#endif
-};
-#endif
-
diff --git a/bsp/bl808/m0/libraries/stage/blog/blog.h b/bsp/bl808/m0/libraries/stage/blog/blog.h
deleted file mode 100644
index 242578bdac..0000000000
--- a/bsp/bl808/m0/libraries/stage/blog/blog.h
+++ /dev/null
@@ -1,268 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __BLOG_H__
-#define __BLOG_H__
-
-#include 
-#include 
-#include 
-
-// #include 
-// #include 
-
-#include 
-
-#include "blog_type.h"
-#include "blog_cfg.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#if (CFG_COMPONENT_BLOG_ENABLE == 1)
-#define ATTR_BLOG_CODE1(name)        __attribute__((used, section(".static_blogcomponent_code." #name)))
-#define ATTR_BLOG_CODE2(name)        __attribute__((used, section(".static_blogfile_code." #name)))
-#define ATTR_BLOG_CODE3(name)        __attribute__((used, section(".static_blogpri_code." #name)))
-
-/* for hard debug level */
-const static uint32_t BLOG_HARD_DECLARE_DISABLE __attribute__((used)) = 0;
-
-/* component level */
-#define _REFC_LEVEL(name)            _fsymc_level_##name
-#define REFC_LEVEL(name)             _REFC_LEVEL(name)
-#define _DEFC_LEVEL(name)            blog_level_t REFC_LEVEL(name) __attribute__((weak))
-#define DECLARE_C_LEVEL(name)        _DEFC_LEVEL(name)
-/* component info */
-#define _REFC_INFO(name)             _fsymc_info_##name
-#define REFC_INFO(name)              _REFC_INFO(name)
-#define _DEFC_INFO(name)             static const blog_info_t REFC_INFO(name) ATTR_BLOG_CODE1(name) = {\
-                                         (blog_level_t *)(&REFC_LEVEL(name)), (char *)(#name)}
-#define DECLARE_C_INFO(name)         _DEFC_INFO(name)
-DECLARE_C_LEVEL(__COMPONENT_NAME_DEQUOTED__);
-DECLARE_C_INFO(__COMPONENT_NAME_DEQUOTED__);
-
-/* file level */
-#define _REFF_LEVEL(name)            _fsymf_level_##name
-#define REFF_LEVEL(name)             _REFF_LEVEL(name)
-#define _DEFF_LEVEL(name)            blog_level_t REFF_LEVEL(name)
-#define DECLARE_F_LEVEL(name)        _DEFF_LEVEL(name)
-/* file info */
-#define _REFF_INFO(name)             _fsymf_info_##name
-#define REFF_INFO(name)              _REFF_INFO(name)
-#define _DEFF_INFO(name, named)      const blog_info_t REFF_INFO(name) ATTR_BLOG_CODE2(name) = {\
-                                        (blog_level_t *)(&REFF_LEVEL(name)), (char *)(#named)}
-#define DECLARE_F_INFO(name, named) _DEFF_INFO(name, named)
-DECLARE_F_LEVEL(__COMPONENT_FILE_NAME_DEQUOTED__);
-DECLARE_F_INFO(__COMPONENT_FILE_NAME_DEQUOTED__, __COMPONENT_FILE_NAMED__);
-
-/* pri level */
-#define _REFP_LEVEL(name)            _fsymp_level_##name
-#define REFP_LEVEL(name)             _REFP_LEVEL(name)
-#define _DEFP_LEVEL(name)            blog_level_t REFP_LEVEL(name)
-#define DECLARE_P_LEVEL(name)        _DEFP_LEVEL(name)
-/* pri info */
-#define _REFP_INFO(name)             _fsymp_info_##name
-#define REFP_INFO(name)              _REFP_INFO(name)
-#define _DEFP_INFO(name, prefix)     const blog_info_t REFP_INFO(name) ATTR_BLOG_CODE3(name) = {\
-                                        (blog_level_t *)(&REFP_LEVEL(name)), (char *)(#prefix"."#name)}
-#define DECLARE_P_INFO(name, prefix) _DEFP_INFO(name, prefix)
-
-#define BLOG_DECLARE(name)           DECLARE_P_LEVEL(name);\
-                                     DECLARE_P_INFO(name, __COMPONENT_FILE_NAMED__);
-
-#define custom_cflog(lowlevel, N, M, ...) do {\
-    if ( (lowlevel >= REFC_LEVEL(__COMPONENT_NAME_DEQUOTED__)) && \
-         (lowlevel >= REFF_LEVEL(__COMPONENT_FILE_NAME_DEQUOTED__))\
-       ) {\
-            __blog_printf("[%10u][%s: %s:%4d] " M,\
-            (xPortIsInsideInterrupt())?(xTaskGetTickCountFromISR()):(xTaskGetTickCount()),\
-            N, __FILENAME__, __LINE__,\
-            ##__VA_ARGS__);\
-    }\
-} while(0==1)
-
-#define custom_cflog_raw(lowlevel, N, M, ...) do {\
-    if ( (lowlevel >= REFC_LEVEL(__COMPONENT_NAME_DEQUOTED__)) && \
-         (lowlevel >= REFF_LEVEL(__COMPONENT_FILE_NAME_DEQUOTED__))\
-       ) {\
-            __blog_printf(M,\
-            ##__VA_ARGS__);\
-    }\
-} while(0==1)
-
-#define custom_plog(priname, lowlevel, N, M, ...) do {\
-    if ( (lowlevel >= REFC_LEVEL(__COMPONENT_NAME_DEQUOTED__)) && \
-         (lowlevel >= REFF_LEVEL(__COMPONENT_FILE_NAME_DEQUOTED__)) && \
-         (lowlevel >= REFP_LEVEL(priname)) \
-       ) {\
-            __blog_printf("[%10u][%s: %s:%4d] " M,\
-            (xPortIsInsideInterrupt())?(xTaskGetTickCountFromISR()):(xTaskGetTickCount()),\
-            N, __FILENAME__, __LINE__,\
-            ##__VA_ARGS__);\
-    }\
-} while(0==1)
-
-#define custom_plog_raw(priname, lowlevel, N, M, ...) do {\
-    if ( (lowlevel >= REFC_LEVEL(__COMPONENT_NAME_DEQUOTED__)) && \
-         (lowlevel >= REFF_LEVEL(__COMPONENT_FILE_NAME_DEQUOTED__)) && \
-         (lowlevel >= REFP_LEVEL(priname)) \
-       ) {\
-            __blog_printf(M,\
-            ##__VA_ARGS__);\
-    }\
-} while(0==1)
-
-#define custom_hexdumplog(name, lowlevel, logo, buf, size) do {\
-    if ( (lowlevel >= REFC_LEVEL(__COMPONENT_NAME_DEQUOTED__)) && \
-         (lowlevel >= REFF_LEVEL(__COMPONENT_FILE_NAME_DEQUOTED__))\
-       ) {\
-            __blog_printf("[%10u][%s: %s:%4d] %s:\r\n",\
-            (xPortIsInsideInterrupt())?(xTaskGetTickCountFromISR()):(xTaskGetTickCount()),\
-            logo, __FILENAME__, __LINE__,\
-            name);\
-            blog_hexdump_out(name, 16, buf, size);\
-    }\
-} while(0==1)
-
-#define BLOG_USE_COLOR (0)
-
-#if LOG_USE_COLOR
-#define BLOG_PREFIX_INFO  "\x1b[32mINFO  \x1b[0m"
-#define BLOG_PREFIX_WARN  "\x1b[33mWARN  \x1b[0m"
-#define BLOG_PREFIX_ERROR "\x1b[31mERROR \x1b[0m"
-#define BLOG_PREFIX_USER  "\x1b[35mASSERT\x1b[0m"
-#define BLOG_PREFIX_DUMP  "\x1b[35mDUMP\x1b[0m"
-#else
-#define BLOG_PREFIX_INFO  "INFO"
-#define BLOG_PREFIX_WARN  "WARN"
-#define BLOG_PREFIX_ERROR "ERROR"
-#define BLOG_PREFIX_USER  "ASSERT"
-#define BLOG_PREFIX_DUMP  "DUMP"
-#endif
-
-#define blog_debug(M, ...)              if (0 == BLOG_HARD_DECLARE_DISABLE) {\
-                                            custom_cflog(BLOG_LEVEL_DEBUG,"DEBUG ", M, ##__VA_ARGS__);}                 // NULL
-#define blog_info(M, ...)               if (0 == BLOG_HARD_DECLARE_DISABLE) {\
-                                            custom_cflog(BLOG_LEVEL_INFO,BLOG_PREFIX_INFO, M, ##__VA_ARGS__);}    // F_GREEN
-#define blog_warn(M, ...)               if (0 == BLOG_HARD_DECLARE_DISABLE) {\
-                                            custom_cflog(BLOG_LEVEL_WARN,BLOG_PREFIX_WARN, M, ##__VA_ARGS__);}    // F_YELLOW
-#define blog_error(M, ...)              if (0 == BLOG_HARD_DECLARE_DISABLE) {\
-                                            custom_cflog(BLOG_LEVEL_ERROR,BLOG_PREFIX_ERROR, M, ##__VA_ARGS__);}  // F_RED
-#define blog_assert(assertion)          if (0 == (assertion)) {\
-                                                __blog_printf("assert, %s:%d\r\n", __FILENAME__, __LINE__);\
-                                                while(1);\
-                                            }
-#define blog_debug_raw(M, ...)              if (0 == BLOG_HARD_DECLARE_DISABLE) {\
-                                            custom_cflog_raw(BLOG_LEVEL_DEBUG,"DEBUG ", M, ##__VA_ARGS__);}                 // NULL
-#define blog_info_raw(M, ...)               if (0 == BLOG_HARD_DECLARE_DISABLE) {\
-                                            custom_cflog_raw(BLOG_LEVEL_INFO,BLOG_PREFIX_INFO, M, ##__VA_ARGS__);}    // F_GREEN
-#define blog_warn_raw(M, ...)               if (0 == BLOG_HARD_DECLARE_DISABLE) {\
-                                            custom_cflog_raw(BLOG_LEVEL_WARN,BLOG_PREFIX_WARN, M, ##__VA_ARGS__);}    // F_YELLOW
-#define blog_error_raw(M, ...)              if (0 == BLOG_HARD_DECLARE_DISABLE) {\
-                                            custom_cflog_raw(BLOG_LEVEL_ERROR,BLOG_PREFIX_ERROR, M, ##__VA_ARGS__);}  // F_RED
-
-#define blog_debug_user(name, M, ...)   if (0 == BLOG_HARD_DECLARE_DISABLE) {\
-                                            custom_plog(name,BLOG_LEVEL_DEBUG, "DEBUG ", M, ##__VA_ARGS__);}
-#define blog_info_user(name, M, ...)    if (0 == BLOG_HARD_DECLARE_DISABLE) {\
-                                            custom_plog(name,BLOG_LEVEL_INFO, BLOG_PREFIX_INFO, M, ##__VA_ARGS__);}
-#define blog_warn_user(name, M, ...)    if (0 == BLOG_HARD_DECLARE_DISABLE) {\
-                                            custom_plog(name,BLOG_LEVEL_WARN, BLOG_PREFIX_WARN, M, ##__VA_ARGS__);}
-#define blog_error_user(name, M, ...)   if (0 == BLOG_HARD_DECLARE_DISABLE) {\
-                                            custom_plog(name,BLOG_LEVEL_ERROR, BLOG_PREFIX_ERROR, M, ##__VA_ARGS__);}
-#define blog_debug_user_raw(name, M, ...)   if (0 == BLOG_HARD_DECLARE_DISABLE) {\
-                                            custom_plog_raw(name,BLOG_LEVEL_DEBUG, "DEBUG ", M, ##__VA_ARGS__);}
-#define blog_info_user_raw(name, M, ...)    if (0 == BLOG_HARD_DECLARE_DISABLE) {\
-                                            custom_plog_raw(name,BLOG_LEVEL_INFO, BLOG_PREFIX_INFO, M, ##__VA_ARGS__);}
-#define blog_warn_user_raw(name, M, ...)    if (0 == BLOG_HARD_DECLARE_DISABLE) {\
-                                            custom_plog_raw(name,BLOG_LEVEL_WARN, BLOG_PREFIX_WARN,M, ##__VA_ARGS__);}
-#define blog_error_user_raw(name, M, ...)   if (0 == BLOG_HARD_DECLARE_DISABLE) {\
-                                            custom_plog_raw(name,BLOG_LEVEL_ERROR, BLOG_PREFIX_ERROR, M, ##__VA_ARGS__);}
-#define blog_assert_user(name, M, ...)  if (0 == BLOG_HARD_DECLARE_DISABLE) {\
-                                            custom_plog(name,BLOG_LEVEL_ASSERT, BLOG_PREFIX_USER, M, ##__VA_ARGS__);}
-
-#define blog_debug_hexdump(name, buf, size)   if (0 == BLOG_HARD_DECLARE_DISABLE) {\
-                                              custom_hexdumplog(name,BLOG_LEVEL_DEBUG, "DEBUG ", buf, size);}
-#define blog_info_hexdump(name, buf, size)    if (0 == BLOG_HARD_DECLARE_DISABLE) {\
-                                              custom_hexdumplog(name,BLOG_LEVEL_INFO, BLOG_PREFIX_INFO, buf, size);}
-#define blog_warn_hexdump(name, buf, size)    if (0 == BLOG_HARD_DECLARE_DISABLE) {\
-                                              custom_hexdumplog(name,BLOG_LEVEL_WARN, BLOG_PREFIX_WARN, buf, size);}
-#define blog_error_hexdump(name, buf, size)   if (0 == BLOG_HARD_DECLARE_DISABLE) {\
-                                              custom_hexdumplog(name,BLOG_LEVEL_ERROR, BLOG_PREFIX_ERROR, buf, size);}
-#define blog_assert_hexdump(name, buf, size)  if (0 == BLOG_HARD_DECLARE_DISABLE) {\
-                                              custom_hexdumplog(name,BLOG_LEVEL_ASSERT, BLOG_PREFIX_DUMP, buf, size);}
-#define blog_print          __blog_printf
-#define blog_buf            log_buf//unsupport
-
-#else
-
-//#define BLOG_HARD_DECLARE_DISABLE 1
-#define BLOG_DECLARE(name)
-
-#define blog_debug(M, ...)
-#define blog_info(M, ...)
-#define blog_warn(M, ...)
-#define blog_error(M, ...)
-#define blog_debug_raw(M, ...)
-#define blog_info_raw(M, ...)
-#define blog_warn_raw(M, ...)
-#define blog_error_raw(M, ...)
-#define blog_assert(M, ...)
-
-#define blog_debug_user(name, M, ...)
-#define blog_info_user(name, M, ...)
-#define blog_warn_user(name, M, ...)
-#define blog_error_user(name, M, ...)
-#define blog_debug_user_raw(name, M, ...)
-#define blog_info_user_raw(name, M, ...)
-#define blog_warn_user_raw(name, M, ...)
-#define blog_error_user_raw(name, M, ...)
-#define blog_assert_user(name, M, ...)
-
-#define blog_debug_hexdump(name, buf, size)
-#define blog_info_hexdump(name, buf, size)
-#define blog_warn_hexdump(name, buf, size)
-#define blog_error_hexdump(name, buf, size)
-#define blog_assert_hexdump(name, buf, size)
-
-#define blog_print(...)
-#define blog_buf(...)
-
-#endif
-
-void blog_init(void);
-
-void blog_hexdump_out(const char *name, uint8_t width, uint8_t *buf, uint16_t size);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
diff --git a/bsp/bl808/m0/libraries/stage/blog/blog_cfg.h b/bsp/bl808/m0/libraries/stage/blog/blog_cfg.h
deleted file mode 100644
index 41ad4f0dc5..0000000000
--- a/bsp/bl808/m0/libraries/stage/blog/blog_cfg.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef __BLOG_CFG_H__
-#define __BLOG_CFG_H__
-
-#define BLOG_POWERON_SOFTLEVEL_COMPONENT    (BLOG_LEVEL_INFO)
-#define BLOG_POWERON_SOFTLEVEL_FILE         (BLOG_LEVEL_INFO)
-#define BLOG_POWERON_SOFTLEVEL_PRI          (BLOG_LEVEL_INFO)
-#define BLOG_NAMELEN_MAX                    (128)
-#define BLOG_DUMP_DEDUPLICATE               (1)
-#define BLOG_TEST                           (0)
-
-#define BLOG_LINE_BUF_SIZE                  (256)
-
-#define __blog_printf                       bl_printk
-
-#endif
diff --git a/bsp/bl808/m0/libraries/stage/blog/blog_type.h b/bsp/bl808/m0/libraries/stage/blog/blog_type.h
deleted file mode 100644
index 538ad60ff6..0000000000
--- a/bsp/bl808/m0/libraries/stage/blog/blog_type.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef __BLOG_TYPE_H__
-#define __BLOG_TYPE_H__
-
-typedef enum _blog_leve {
-    BLOG_LEVEL_ALL = 0,
-    BLOG_LEVEL_DEBUG,
-    BLOG_LEVEL_INFO,
-    BLOG_LEVEL_WARN,
-    BLOG_LEVEL_ERROR,
-    BLOG_LEVEL_ASSERT,
-    BLOG_LEVEL_NEVER,
-} blog_level_t;
-
-typedef struct _blog_info {
-    blog_level_t *level; //default 0
-    char *name;
-} blog_info_t;
-
-#endif
diff --git a/bsp/bl808/m0/libraries/utils/include/utils_base64.h b/bsp/bl808/m0/libraries/utils/include/utils_base64.h
deleted file mode 100644
index 7c7db40874..0000000000
--- a/bsp/bl808/m0/libraries/utils/include/utils_base64.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-
-
-
-#ifndef _IOTX_COMMON_BASE64_H_
-#define _IOTX_COMMON_BASE64_H_
-
-#include 
-
-#define UTILS_BASE64_TEST
-
-typedef enum iotx_err
-{
-    FAIL_RETURN = 0,
-    SUCCESS_RETURN
-}iotx_err_t;
-
-iotx_err_t utils_base64encode(const uint8_t *data, uint32_t inputLength, uint32_t outputLenMax,
-                              uint8_t *encodedData, uint32_t *outputLength);
-iotx_err_t utils_base64decode(const uint8_t *data, uint32_t inputLength, uint32_t outputLenMax,
-                              uint8_t *decodedData, uint32_t *outputLength);
-
-void utils_base64_encode_stream(int (*read_data)(uint8_t *data, void *opaque), void (*write_data)(const uint8_t data[4], void *opaque), void *opaque);
-int base64_cli_init(void);
-
-#endif
diff --git a/bsp/bl808/m0/libraries/utils/include/utils_bitmap_window.h b/bsp/bl808/m0/libraries/utils/include/utils_bitmap_window.h
deleted file mode 100644
index 20a24439fd..0000000000
--- a/bsp/bl808/m0/libraries/utils/include/utils_bitmap_window.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include 
-
-struct utils_bitmap_ctx {
-    int ssn;
-    int ssn_duration;
-    union {
-        uint8_t bytes[8];
-        uint64_t map64;
-    } bitmap;
-};
-
-int utils_bitmap_window_init(struct utils_bitmap_ctx *ctx, int ssn, int ssn_max);
-int utils_bitmap_window_bit_set(struct utils_bitmap_ctx *ctx, int bit_pos);
-uint64_t utils_bitmap_window_map_get(struct utils_bitmap_ctx *ctx);
-int utils_bitmap_window_ssn_get(struct utils_bitmap_ctx *ctx);
-int utils_bitmap_window_cli_init(void);
diff --git a/bsp/bl808/m0/libraries/utils/include/utils_crc.h b/bsp/bl808/m0/libraries/utils/include/utils_crc.h
deleted file mode 100644
index 10f62d4c17..0000000000
--- a/bsp/bl808/m0/libraries/utils/include/utils_crc.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef __UTILS_CRC_H__
-#define __UTILS_CRC_H__
-#include 
-
-uint16_t utils_crc16(void *dataIn, uint32_t len);
-uint32_t utils_crc32(void *dataIn, uint32_t len);
-uint16_t utils_crc16_ccitt(void *dataIn, uint32_t len);
-
-struct crc32_stream_ctx {
-  uint32_t crc;
-};
-
-void utils_crc32_stream_init(struct crc32_stream_ctx *ctx);
-void utils_crc32_stream_feed(struct crc32_stream_ctx *ctx, uint8_t data);
-void utils_crc32_stream_feed_block(struct crc32_stream_ctx *ctx, uint8_t *data, uint32_t len);
-uint32_t utils_crc32_stream_results(struct crc32_stream_ctx *ctx);
-
-#endif
diff --git a/bsp/bl808/m0/libraries/utils/include/utils_debug.h b/bsp/bl808/m0/libraries/utils/include/utils_debug.h
deleted file mode 100644
index 8f5dcecc75..0000000000
--- a/bsp/bl808/m0/libraries/utils/include/utils_debug.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef __UTILS_DEBUG_H__
-#define __UTILS_DEBUG_H__
-#include 
-#define BL_ASSERT_ERROR(cond) do {\
-    if (!(cond)) { \
-        printf("[ASSERT] [ERR] %s:%d\r\n", __FILENAME__, __LINE__); \
-        while (1) { \
-        } \
-    } \
-} while (0)
-
-#endif
diff --git a/bsp/bl808/m0/libraries/utils/include/utils_dns.h b/bsp/bl808/m0/libraries/utils/include/utils_dns.h
deleted file mode 100644
index 19eeb2bc02..0000000000
--- a/bsp/bl808/m0/libraries/utils/include/utils_dns.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef __UTILS_DNS_H__
-#define __UTILS_DNS_H__
-#include 
-int utils_dns_domain_get(uint8_t *records, uint8_t *buf, int *len);
-#endif
diff --git a/bsp/bl808/m0/libraries/utils/include/utils_fec.h b/bsp/bl808/m0/libraries/utils/include/utils_fec.h
deleted file mode 100644
index 114b332368..0000000000
--- a/bsp/bl808/m0/libraries/utils/include/utils_fec.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __UTILS_FEC_H__
-#define __UTILS_FEC_H__
-
-#include 
-#include 
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define FEC_MSG_LENGTH  128
-#define FEC_ECC_LENGTH  126
-
-#define bl_assert(expr)
-
-typedef struct
-{
-    int dummy[1120];
-} fec_t;
-
-int  reedsolomon_getmemsize(void);
-void reedsolomon_init(void *context);
-void reedsolomon_encode(void *context, void* src, void* dst);
-char reedsolomon_decode(void *context, void* src, void* dst);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
diff --git a/bsp/bl808/m0/libraries/utils/include/utils_getopt.h b/bsp/bl808/m0/libraries/utils/include/utils_getopt.h
deleted file mode 100644
index 026640e0a3..0000000000
--- a/bsp/bl808/m0/libraries/utils/include/utils_getopt.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef __GETOPT_H__
-#define __GETOPT_H__
-/**
- * @brief Parameters needed to parse the command line
- *
- */
-typedef struct getopt_env {
-    char *optarg;    /*!< if the option accepts parameters, then optarg point to the option parameter*/
-    int optind;      /*!< current index of argv*/
-    int opterr;      /*!< non-zero enable error message output, while 0,no error message output*/
-    int optopt;      /*!< contain unrecognized option character*/
-    int __optpos;
-} getopt_env_t;
-
-/**
- * @brief Initialize struct getopt_env
- *
- * @param env pointer to struct getopt_env
- * @param opterr set error message output method
- *
- * @return
- *     -  0: success
- *     - -1: fail
- */
-int utils_getopt_init(getopt_env_t *env, int opterr);
-
-/**
- * @brief Parses the command-line arguments
- *
- * @param env pointer to struct getopt_env
- * @param argc the argument count
- * @param argv the argument array
- *
- * @return
- *     -  option character : an option was successfully found
- *     - -1 : all command-line options have been parsed
- *     - '?' : option character was not in optstring
- *     - ':' or '?' : If utils_getopt() encounters an option with a missing argument, then the return value depends on the first character in optstring: if it is ':', then ':' is returned; otherwise '?' is returned
- *
- * @note Example
- * @code
- *
- * #include 
- * #include 
- *
- * void cmd(char *buf, int len, int argc, char **argv)
- * {
- *     int opt;
-       getopt_env_t getopt_env;
-       utils_getopt_init(&getopt_env, 0);
- *     //put ':' in the starting of the string so that program can distinguish between '?' and ':'
- *     while ((opt = utils_getopt(&getopt_env, argc, argv, ":if:lr")) != -1) {
- *         switch(opt)
- *         {
- *             case 'i':
- *             case 'l':
- *             case 'r':
- *                 printf("option: %c\r\n", opt);
- *                 break;
- *             case 'f':
- *                 printf("filename: %s\r\n", getopt_env.optarg);
- *                 break;
- *             case ':':
-                   printf("%s: %c requires an argument\r\n", *argv, getopt_env.optopt);
- *                 break;
- *             case '?':
- *                 printf("unknow option: %c\r\n", getopt_env.optopt);
- *                 break;
- *          }
- *      }
- *      //optind is for the extra arguments which are not parsed
- *      for(; getopt_env.optind < argc; getopt_env.optind++){
- *          printf("extra arguments: %s\r\n", argv[getopt_env.optind]);
- *      }
- *
- *  }
- *  @endcode
- */
-int utils_getopt(getopt_env_t *env, int argc, char * const argv[], const char *optstring);
-
-#endif /* __GETOPT_H__ */
diff --git a/bsp/bl808/m0/libraries/utils/include/utils_hex.h b/bsp/bl808/m0/libraries/utils/include/utils_hex.h
deleted file mode 100644
index 6361fdad07..0000000000
--- a/bsp/bl808/m0/libraries/utils/include/utils_hex.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef __UTILS_HEX_H__
-#define __UTILS_HEX_H__
-char *utils_bin2hex(char *dst, const void *src, size_t count);
-size_t utils_hex2bin(const char *hex, size_t hexlen, uint8_t *buf, size_t buflen);
-#endif
diff --git a/bsp/bl808/m0/libraries/utils/include/utils_hexdump.h b/bsp/bl808/m0/libraries/utils/include/utils_hexdump.h
deleted file mode 100644
index 4cbde0c711..0000000000
--- a/bsp/bl808/m0/libraries/utils/include/utils_hexdump.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef __UTILS_HEXDUMP_H__
-#define __UTILS_HEXDUMP_H__
-void utils_hexdump(void *mem, unsigned int len);
-#endif
diff --git a/bsp/bl808/m0/libraries/utils/include/utils_hmac.h b/bsp/bl808/m0/libraries/utils/include/utils_hmac.h
deleted file mode 100644
index 7949a190c6..0000000000
--- a/bsp/bl808/m0/libraries/utils/include/utils_hmac.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-
-
-
-#ifndef _IOTX_COMMON_HMAC_H_
-#define _IOTX_COMMON_HMAC_H_
-
-#include 
-
-#define KEY_IOPAD_SIZE        (64)
-#define MD5_DIGEST_SIZE       (16)
-#define SHA1_DIGEST_SIZE      (20)
-#define SHA256_DIGEST_SIZE    (32)
-
-#ifdef UTILS_MD5
-void utils_hmac_md5(const char *msg, int msg_len, char *digest, const char *key, int key_len);
-#endif
-
-#ifdef UTILS_SHA1
-void utils_hmac_sha1(const char *msg, int msg_len, char *digest, const char *key, int key_len);
-
-void utils_hmac_sha1_hex(const char *msg, int msg_len, char *digest, const char *key, int key_len);
-#endif
-
-#ifdef UTILS_SHA256
-void utils_hmac_sha256(const char *msg, int msg_len, char *digest, const char *key, int key_len);
-#endif
-
-#endif
-
diff --git a/bsp/bl808/m0/libraries/utils/include/utils_hmac_sha1_fast.h b/bsp/bl808/m0/libraries/utils/include/utils_hmac_sha1_fast.h
deleted file mode 100644
index e6f9de7a77..0000000000
--- a/bsp/bl808/m0/libraries/utils/include/utils_hmac_sha1_fast.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef __UTILS_HMAC_SHA1_FASH_H__
-#define __UTILS_HMAC_SHA1_FASH_H__
-
-void utils_hmac_sha1_fast(unsigned char ** ppText,
-                    int * pTextLen,
-                    int textNum,
-                    unsigned char *key,
-                    int key_len,
-                    unsigned char *output,
-                    int outputLen);
-
-#endif
diff --git a/bsp/bl808/m0/libraries/utils/include/utils_list.h b/bsp/bl808/m0/libraries/utils/include/utils_list.h
deleted file mode 100644
index 6248b1b1c2..0000000000
--- a/bsp/bl808/m0/libraries/utils/include/utils_list.h
+++ /dev/null
@@ -1,621 +0,0 @@
-
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-
-#ifndef _UTILS_LIST_H_
-#define _UTILS_LIST_H_
-
-#include 
-
-struct utils_list_hdr
-{
-    struct utils_list_hdr *next;
-};
-
-struct utils_list
-{
-    /// pointer to first element of the list
-    struct utils_list_hdr *first;
-    /// pointer to the last element
-    struct utils_list_hdr *last;
-};
-
-
-/*
- * FUNCTION DECLARATIONS
- ****************************************************************************************
- */
-/**
- ****************************************************************************************
- * @brief Initialize a list to defaults values.
- * @param[in] list           Pointer to the list structure.
- ****************************************************************************************
- */
-void utils_list_init(struct utils_list *list);
-
-/**
- ****************************************************************************************
- * @brief Initialize a pool to default values, and initialize the relative free list.
- *
- * @param[in] list           Pointer to the list structure
- * @param[in] pool           Pointer to the pool to be initialized
- * @param[in] elmt_size      Size of one element of the pool
- * @param[in] elmt_cnt       Nb of elements available in the pool
- * @param[in] default_value  Pointer to the default value of each element (may be NULL)
- ****************************************************************************************
- */
-void utils_list_pool_init(struct utils_list *list, void *pool, size_t elmt_size, unsigned int elmt_cnt, void *default_value);
-
-/**
- ****************************************************************************************
- * @brief Add an element as last on the list.
- *
- * @param[in] list           Pointer to the list structure
- * @param[in] list_hdr       Pointer to the header to add at the end of the list
- ****************************************************************************************
- */
-void utils_list_push_back(struct utils_list *list,
-                       struct utils_list_hdr *list_hdr);
-
-/**
- ****************************************************************************************
- * @brief Add an element as first on the list.
- *
- * @param[in] list           Pointer to the list structure
- * @param[in] list_hdr       Pointer to the header to add at the beginning of the list
- ****************************************************************************************
- */
-void utils_list_push_front(struct utils_list *list, struct utils_list_hdr *list_hdr);
-/**
- ****************************************************************************************
- * @brief Extract the first element of the list.
- *
- * @param[in] list           Pointer to the list structure
- *
- * @return The pointer to the element extracted, and NULL if the list is empty.
- ****************************************************************************************
- */
-struct utils_list_hdr *utils_list_pop_front(struct utils_list *list);
-
-/**
- ****************************************************************************************
- * @brief Search for a given element in the list, and extract it if found.
- *
- * @param[in] list           Pointer to the list structure
- * @param[in] list_hdr       Pointer to the searched element
- *
- * @return CO_EMPTY if the list is empty, CO_FAIL if the element not found in the list,
- * CO_OK else.
- ****************************************************************************************
- */
-void utils_list_extract(struct utils_list *list, struct utils_list_hdr *list_hdr);
-
-/**
- ****************************************************************************************
- * @brief Searched a given element in the list.
- *
- * @param[in] list           Pointer to the list structure
- * @param[in] list_hdr       Pointer to the searched element
- *
- * @return true if the element is found in the list, false otherwise
- ****************************************************************************************
- */
-int utils_list_find(struct utils_list *list, struct utils_list_hdr *list_hdr);
-
-/**
- ****************************************************************************************
- * @brief Insert an element in a sorted list.
- *
- * This primitive use a comparison function from the parameter list to select where the
- * element must be inserted.
- *
- * @param[in]  list     Pointer to the list.
- * @param[in]  element  Pointer to the element to insert.
- * @param[in]  cmp      Comparison function (return true if first element has to be inserted
- *                      before the second one).
- *
- * @return              Pointer to the element found and removed (NULL otherwise).
- ****************************************************************************************
- */
-void utils_list_insert(struct utils_list * const list, struct utils_list_hdr * const element,
-        int (*cmp)(struct utils_list_hdr const *elementA,
-        struct utils_list_hdr const *elementB));
-
-/**
- ****************************************************************************************
- * @brief Insert an element in a sorted list after the provided element.
- *
- * This primitive use a comparison function from the parameter list to select where the
- * element must be inserted.
- *
- * @param[in]  list           Pointer to the list.
- * @param[in]  prev_element   Pointer to the element to find in the list
- * @param[in]  element        Pointer to the element to insert.
- *
- * If prev_element is not found, the provided element is not inserted
- ****************************************************************************************
- */
-void utils_list_insert_after(struct utils_list * const list, struct utils_list_hdr * const prev_element, struct utils_list_hdr * const element);
-
-/**
- ****************************************************************************************
- * @brief Insert an element in a sorted list before the provided element.
- *
- * This primitive use a comparison function from the parameter list to select where the
- * element must be inserted.
- *
- * @param[in]  list           Pointer to the list.
- * @param[in]  next_element   Pointer to the element to find in the list
- * @param[in]  element        Pointer to the element to insert.
- *
- * If next_element is not found, the provided element is not inserted
- ****************************************************************************************
- */
-void utils_list_insert_before(struct utils_list * const list, struct utils_list_hdr * const next_element, struct utils_list_hdr * const element);
-
-/**
- ****************************************************************************************
- * @brief Concatenate two lists.
- * The resulting list is the list passed as the first parameter. The second list is
- * emptied.
- *
- * @param[in]  list1          First list (will get the result of the concatenation)
- * @param[in]  list2          Second list (will be emptied after the concatenation)
- ****************************************************************************************
- */
-void utils_list_concat(struct utils_list *list1, struct utils_list *list2);
-
-/**
- ****************************************************************************************
- * @brief Remove the element in the list after the provided element.
- *
- * This primitive removes an element in the list. It is assume that element is part of
- * the list.
- *
- * @param[in] list          Pointer to the list.
- * @param[in] prev_element  Pointer to the previous element.
- *                          NULL if @p element is the first element in the list
- * @param[in] element       Pointer to the element to remove.
- *
- ****************************************************************************************
- */
-void utils_list_remove(struct utils_list *list, struct utils_list_hdr *prev_element, struct utils_list_hdr *element);
-/**
- ****************************************************************************************
- * @brief Test if the list is empty.
- *
- * @param[in] list           Pointer to the list structure.
- *
- * @return true if the list is empty, false else otherwise.
- ****************************************************************************************
- */
-static inline int utils_list_is_empty(const struct utils_list *const list)
-{
-    return (NULL == list->first);
-}
-
-/**
- ****************************************************************************************
- * @brief Return the number of element of the list.
- *
- * @param[in] list           Pointer to the list structure.
- *
- * @return The number of elements in the list.
- ****************************************************************************************
- */
-unsigned int utils_list_cnt(const struct utils_list *const list);
-
-/**
- ****************************************************************************************
- * @brief Pick the first element from the list without removing it.
- *
- * @param[in] list           Pointer to the list structure.
- *
- * @return First element address. Returns NULL pointer if the list is empty.
- ****************************************************************************************
- */
-static inline struct utils_list_hdr *utils_list_pick(const struct utils_list *const list)
-{
-    return list->first;
-}
-
-static inline struct utils_list_hdr *utils_list_pick_last(const struct utils_list *const list)
-{
-    return list->last;
-}
-
-static inline struct utils_list_hdr *utils_list_next(const struct utils_list_hdr *const list_hdr)
-{
-    return list_hdr->next;
-}
-
-
-/*
- * Get offset of a member variable.
- *
- * @param[in]   type     the type of the struct this is embedded in.
- * @param[in]   member   the name of the variable within the struct.
- */
-#define utils_offsetof(type, member)   ((size_t)&(((type *)0)->member))
-
-/*
- * Get the struct for this entry.
- *
- * @param[in]   ptr     the list head to take the element from.
- * @param[in]   type    the type of the struct this is embedded in.
- * @param[in]   member  the name of the variable within the struct.
- */
-#define utils_container_of(ptr, type, member) \
-    ((type *) ((char *) (ptr) - utils_offsetof(type, member)))
-
-/* for double link list */
-typedef struct utils_dlist_s {
-    struct utils_dlist_s *prev;
-    struct utils_dlist_s *next;
-} utils_dlist_t;
-
-static inline void __utils_dlist_add(utils_dlist_t *node, utils_dlist_t *prev, utils_dlist_t *next)
-{
-    node->next = next;
-    node->prev = prev;
-
-    prev->next = node;
-    next->prev = node;
-}
-
-/*
- * Get the struct for this entry.
- *
- * @param[in]   addr    the list head to take the element from.
- * @param[in]   type    the type of the struct this is embedded in.
- * @param[in]   member  the name of the utils_dlist_t within the struct.
- */
-#define utils_dlist_entry(addr, type, member) \
-    ((type *)((long)addr - utils_offsetof(type, member)))
-
-
-static inline void utils_dlist_add(utils_dlist_t *node, utils_dlist_t *queue)
-{
-    __utils_dlist_add(node, queue, queue->next);
-}
-
-static inline void utils_dlist_add_tail(utils_dlist_t *node, utils_dlist_t *queue)
-{
-    __utils_dlist_add(node, queue->prev, queue);
-}
-
-static inline void utils_dlist_del(utils_dlist_t *node)
-{
-    utils_dlist_t *prev = node->prev;
-    utils_dlist_t *next = node->next;
-
-    prev->next = next;
-    next->prev = prev;
-}
-
-static inline void utils_dlist_init(utils_dlist_t *node)
-{
-    node->next = node->prev = node;
-}
-
-static inline void INIT_UTILS_DLIST_HEAD(utils_dlist_t *list)
-{
-    list->next = list;
-    list->prev = list;
-}
-
-static inline int utils_dlist_empty(const utils_dlist_t *head)
-{
-    return head->next == head;
-}
-
-/*
- * Initialise the list.
- *
- * @param[in]   list    the list to be inited.
- */
-#define UTILS_DLIST_INIT(list)  {&(list), &(list)}
-
-/*
- * Get the first element from a list
- *
- * @param[in]   ptr     the list head to take the element from.
- * @param[in]   type    the type of the struct this is embedded in.
- * @param[in]   member  the name of the utils_dlist_t within the struct.
- */
-#define utils_dlist_first_entry(ptr, type, member) \
-    utils_dlist_entry((ptr)->next, type, member)
-
-/*
- * Iterate over a list.
- *
- * @param[in]   pos     the &struct utils_dlist_t to use as a loop cursor.
- * @param[in]   head    he head for your list.
- */
-#define utils_dlist_for_each(pos, head) \
-    for (pos = (head)->next; pos != (head); pos = pos->next)
-
-/*
- * Iterate over a list safe against removal of list entry.
- *
- * @param[in]   pos     the &struct utils_dlist_t to use as a loop cursor.
- * @param[in]   n       another &struct utils_dlist_t to use as temporary storage.
- * @param[in]   head    he head for your list.
- */
-#define utils_dlist_for_each_safe(pos, n, head) \
-    for (pos = (head)->next, n = pos->next; pos != (head); \
-    pos = n, n = pos->next)
-
-/*
- * Iterate over list of given type.
- *
- * @param[in]   queue   he head for your list.
- * @param[in]   node    the &struct utils_dlist_t to use as a loop cursor.
- * @param[in]   type    the type of the struct this is embedded in.
- * @param[in]   member  the name of the utils_dlist_t within the struct.
- */
-#define utils_dlist_for_each_entry(queue, node, type, member) \
-    for (node = utils_container_of((queue)->next, type, member); \
-         &node->member != (queue); \
-         node = utils_container_of(node->member.next, type, member))
-
-/*
- * Iterate over list of given type safe against removal of list entry.
- *
- * @param[in]   queue   the head for your list.
- * @param[in]   n       the type * to use as a temp.
- * @param[in]   node    the type * to use as a loop cursor.
- * @param[in]   type    the type of the struct this is embedded in.
- * @param[in]   member  the name of the utils_dlist_t within the struct.
- */
-#define utils_dlist_for_each_entry_safe(queue, n, node, type, member) \
-    for (node = utils_container_of((queue)->next, type, member),  \
-         n = (queue)->next ? (queue)->next->next : NULL;        \
-         &node->member != (queue);                              \
-         node = utils_container_of(n, type, member), n = n ? n->next : NULL)
-
-/*
- * Get the struct for this entry.
- * @param[in]   ptr     the list head to take the element from.
- * @param[in]   type    the type of the struct this is embedded in.
- * @param[in]   member  the name of the variable within the struct.
- */
-#define utils_list_entry(ptr, type, member) \
-        utils_container_of(ptr, type, member)
-
-
-/*
- * Iterate backwards over list of given type.
- *
- * @param[in]   pos     the type * to use as a loop cursor.
- * @param[in]   head    he head for your list.
- * @param[in]   member  the name of the utils_dlist_t within the struct.
- * @param[in]   type    the type of the struct this is embedded in.
- */
-#define utils_dlist_for_each_entry_reverse(pos, head, member, type) \
-    for (pos = utils_list_entry((head)->prev, type, member);        \
-         &pos->member != (head);                              \
-         pos = utils_list_entry(pos->member.prev, type, member))
-
-
-/*
- * Get the list length.
- *
- * @param[in]  queue  the head for your list.
- */
-static inline int utils_dlist_entry_number(utils_dlist_t *queue)
-{
-    int num;
-    utils_dlist_t *cur = queue;
-    for (num=0;cur->next != queue;cur=cur->next, num++)
-        ;
-
-    return num;
-}
-
-
-
-/*
- * Initialise the list.
- *
- * @param[in]   name    the list to be initialized.
- */
-#define UTILS_DLIST_HEAD_INIT(name) { &(name), &(name) }
-
-/*
- * Initialise the list.
- *
- * @param[in]   name    the list to be initialized.
- */
-#define UTILS_DLIST_HEAD(name) \
-        utils_dlist_t name = UTILS_DLIST_HEAD_INIT(name)
-
-/* for single link list */
-typedef struct utils_slist_s {
-    struct utils_slist_s *next;
-} utils_slist_t;
-
-static inline void utils_slist_add(utils_slist_t *node, utils_slist_t *head)
-{
-    node->next = head->next;
-    head->next = node;
-}
-
-static inline void utils_slist_add_tail(utils_slist_t *node, utils_slist_t *head)
-{
-    while (head->next) {
-        head = head->next;
-    }
-
-    utils_slist_add(node, head);
-}
-
-static inline void utils_slist_append(utils_slist_t *l, utils_slist_t *n)
-{
-    utils_slist_t *node;
-
-    node = l;
-    while (node->next) node = node->next;
-
-    /* append the node to the tail */
-    node->next = n;
-    n->next = NULL;
-}
-
-static inline void utils_slist_del(utils_slist_t *node, utils_slist_t *head)
-{
-    while (head->next) {
-        if (head->next == node) {
-            head->next = node->next;
-            break;
-        }
-
-        head = head->next;
-    }
-}
-
-static inline int utils_slist_empty(const utils_slist_t *head)
-{
-    return !head->next;
-}
-
-static inline void utils_slist_init(utils_slist_t *head)
-{
-    head->next = 0;
-}
-
-static inline utils_slist_t* utils_slist_first(utils_slist_t *l)
-{
-    return l->next;
-}
-
-static inline utils_slist_t* utils_slist_tail(utils_slist_t *l)
-{
-    while (l->next) l = l->next;
-
-    return l;
-}
-
-static inline utils_slist_t* utils_slist_next(utils_slist_t *l)
-{
-    return l->next;
-}
-
-/*
-* Iterate over list of given type.
-*
-* @param[in]   queue   he head for your list.
-* @param[in]   node    the type * to use as a loop cursor.
-* @param[in]   type    the type of the struct this is embedded in.
-* @param[in]   member  the name of the utils_slist_t within the struct.
-*/
-#define utils_slist_for_each_entry(queue, node, type, member)        \
-    for (node = utils_container_of((queue)->next, type, member); \
-         &node->member;                                        \
-         node = utils_container_of(node->member.next, type, member))
-
-/*
- * Iterate over list of given type safe against removal of list entry.
- *
- * @param[in]   queue   the head for your list.
- * @param[in]   tmp     the type * to use as a temp.
- * @param[in]   node    the type * to use as a loop cursor.
- * @param[in]   type    the type of the struct this is embedded in.
- * @param[in]   member  the name of the utils_slist_t within the struct.
- */
-#define utils_slist_for_each_entry_safe(queue, tmp, node, type, member) \
-    for (node = utils_container_of((queue)->next, type, member),    \
-         tmp = (queue)->next ? (queue)->next->next : NULL;        \
-         &node->member;                                           \
-         node = utils_container_of(tmp, type, member), tmp = tmp ? tmp->next : tmp)
-
-/*
- * Initialise the list.
- *
- * @param[in]   name    the list to be initialized.
- */
-#define UTILS_SLIST_HEAD_INIT(name) {0}
-
-/*
- * Initialise the list.
- *
- * @param[in]   name    the list to be initialized.
- */
-#define UTILS_SLIST_HEAD(name) \
-        utils_slist_t name = UTILS_SLIST_HEAD_INIT(name)
-
-/*
- * Get the struct for this entry.
- * @param[in]   addr     the list head to take the element from.
- * @param[in]   type     the type of the struct this is embedded in.
- * @param[in]   member   the name of the utils_slist_t within the struct.
- */
-#define utils_slist_entry(addr, type, member) (                                   \
-    addr ? (type *)((long)addr - utils_offsetof(type, member)) : (type *)addr \
-)
-
-/*
-* Get the first element from a list.
-*
-* @param[in]   ptr     the list head to take the element from.
-* @param[in]   type    the type of the struct this is embedded in.
-* @param[in]   member  the name of the utils_slist_t within the struct.
-*/
-#define utils_slist_first_entry(ptr, type, member) \
-    utils_slist_entry(utils_slist_next(ptr), type, member)
-
-
-/*
-* Get the last element from a list.
-*
-* @param[in]   ptr     the list head to take the element from.
-* @param[in]   type    the type of the struct this is embedded in.
-* @param[in]   member  the name of the utils_slist_t within the struct.
-*/
-#define utils_slist_tail_entry(ptr, type, member) \
-    utils_slist_entry(utils_slist_tail(ptr), type, member)
-
-
-/*
- * Get the list length.
- *
- * @param[in]   queue    the head for your list.
- */
-static inline int utils_slist_entry_number(utils_slist_t *queue)
-{
-    int num;
-    utils_slist_t *cur = queue;
-    for (num=0;cur->next;cur=cur->next, num++)
-        ;
-
-    return num;
-}
-#endif
diff --git a/bsp/bl808/m0/libraries/utils/include/utils_log.h b/bsp/bl808/m0/libraries/utils/include/utils_log.h
deleted file mode 100644
index bbf73a7c49..0000000000
--- a/bsp/bl808/m0/libraries/utils/include/utils_log.h
+++ /dev/null
@@ -1,168 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __UTILS_LOG_H__
-#define __UTILS_LOG_H__
-
-#include 
-#include 
-#include 
-#include 
-
-// #include 
-// #include 
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define __utils_printf              bl_printk
-
-/* cc */
-/* define compiler specific symbols */
-#if defined (__ICCARM__)
-#define BL_PACK_STRUCT_BEGIN
-#define BL_PACK_STRUCT_STRUCT
-#define BL_PACK_STRUCT_END
-#define BL_PACK_STRUCT_FIELD(x) x
-#define BL_PACK_STRUCT_USE_INCLUDES
-#elif defined (__CC_ARM)
-#define BL_PACK_STRUCT_BEGIN __packed
-#define BL_PACK_STRUCT_STRUCT
-#define BL_PACK_STRUCT_END
-#define BL_PACK_STRUCT_FIELD(x) x
-#elif defined (__GNUC__)
-#define BL_PACK_STRUCT_BEGIN    //#pragma pack(push, 1)
-#define BL_PACK_STRUCT_STRUCT //__attribute__ ((__packed__))
-#define BL_PACK_STRUCT_END      //#pragma pack(pop)
-#define BL_PACK_STRUCT_FIELD(x)
-#elif defined (__TASKING__)
-#define BL_PACK_STRUCT_BEGIN
-#define BL_PACK_STRUCT_STRUCT
-#define BL_PACK_STRUCT_END
-#define BL_PACK_STRUCT_FIELD(x) x
-#endif
-
-#if 0
-#define BL_ASSERT(condition)    \
-    do { \
-        if (!(condition)) { \
-            log_assert("ASSERT: %s:%d\r\n", __FILENAME__, __LINE__); \
-            while (1) { \
-                /*deap loop now*/ \
-            } \
-        } \
-    } while (0)
-#endif
-#define BL_ASSERT(condition)
-
-#define LOG_USE_COLOR  (0)
-typedef enum LOG_BUF_OUT_DATA_TYPE {
-    LOG_BUF_OUT_DATA_TYPE_HEX,
-    LOG_BUF_OUT_DATA_TYPE_INT8,
-    LOG_BUF_OUT_DATA_TYPE_UNT8,
-} LOG_BUF_OUT_DATA_TYPE_T;
-//#define LOG_USE_LINE_FEED
-#define LOG_LOCK_LOCK    /* reserved, must diffrent with buf lock */
-#define LOG_LOCK_UNLOCK  /* reserved, must diffrent with buf lock */
-//#define SHORT_FILE __FILENAME__
-#define SHORT_FILE __FILE__
-
-#ifdef LOG_USE_LINE_FEED
-#define custom_log(N, M, ...) do {  LOG_LOCK_LOCK;\
-                                    __utils_printf("[%10u][%s: %s:%4d] " M "\r\n",\
-                                    (xPortIsInsideInterrupt())?(xTaskGetTickCountFromISR()):(xTaskGetTickCount()),\
-                                    N, SHORT_FILE, __LINE__,\
-                                    ##__VA_ARGS__);\
-                                    LOG_LOCK_UNLOCK;\
-                                    } while(0==1)
-#define custom_buf_pri(file, line, N, M, ...) do {  LOG_LOCK_LOCK;\
-                                    __utils_printf("[%10u][%s: %s:%4d] " M, "\r\n",\
-                                    (xPortIsInsideInterrupt())?(xTaskGetTickCountFromISR()):(xTaskGetTickCount()),\
-                                    N, file, line,\
-                                    ##__VA_ARGS__);\
-                                    LOG_LOCK_UNLOCK;\
-                                    } while(0==1)
-#else
-#define custom_log(N, M, ...) do {  LOG_LOCK_LOCK;\
-                                    __utils_printf("[%10u][%s: %s:%4d] " M,\
-                                    (xPortIsInsideInterrupt())?(xTaskGetTickCountFromISR()):(xTaskGetTickCount()),\
-                                    N, SHORT_FILE, __LINE__,\
-                                    ##__VA_ARGS__);\
-                                    LOG_LOCK_UNLOCK;\
-                                    } while(0==1)
-#define custom_buf_pri(file, line, N, M, ...) do {  LOG_LOCK_LOCK;\
-                                    __utils_printf("[%10u][%s: %s:%4d] " M,\
-                                    (xPortIsInsideInterrupt())?(xTaskGetTickCountFromISR()):(xTaskGetTickCount()),\
-                                    N, file, line,\
-                                    ##__VA_ARGS__);\
-                                    LOG_LOCK_UNLOCK;\
-                                    } while(0==1)
-#endif
-
-#if LOG_USE_COLOR
-#define log_buf_pri(file, line, M, ...)   custom_buf_pri(file, line, "\x1b[36mBUF\x1b[0m", M, ##__VA_ARGS__)
-#else
-#define log_buf_pri(file, line, M, ...)   custom_buf_pri(file, line, "BUF", M, ##__VA_ARGS__)
-#endif
-
-#if LOG_USE_COLOR
-#define log_trace(M, ...)   custom_log("\x1b[94mTRACE \x1b[0m", M, ##__VA_ARGS__)
-#define log_debug(M, ...)   custom_log("\x1b[36mDEBUG \x1b[0m", M, ##__VA_ARGS__)
-#define log_info(M, ...)    custom_log("\x1b[32mINFO  \x1b[0m", M, ##__VA_ARGS__)
-#define log_warn(M, ...)    custom_log("\x1b[33mWARN  \x1b[0m", M, ##__VA_ARGS__)
-#define log_error(M, ...)   custom_log("\x1b[31mERROR \x1b[0m", M, ##__VA_ARGS__)
-#define log_assert(M, ...)  custom_log("\x1b[35mASSERT\x1b[0m", M, ##__VA_ARGS__)
-#else
-#define log_trace(M, ...)   custom_log("TRACE ", M, ##__VA_ARGS__)
-#define log_debug(M, ...)   custom_log("DEBUG ", M, ##__VA_ARGS__)
-#define log_info(M, ...)    custom_log("INFO  ", M, ##__VA_ARGS__)
-#define log_warn(M, ...)    custom_log("WARN  ", M, ##__VA_ARGS__)
-#define log_error(M, ...)   custom_log("ERROR ", M, ##__VA_ARGS__)
-#define log_assert(M, ...)  custom_log("ASSERT", M, ##__VA_ARGS__)
-#endif
-#define log_buf(pbuf, len)  log_buf_out(SHORT_FILE, __LINE__, pbuf, len, LOG_BUF_OUT_DATA_TYPE_HEX)
-#define log_buf_int8(pbuf, len)  log_buf_out(SHORT_FILE, __LINE__, pbuf, len, LOG_BUF_OUT_DATA_TYPE_INT8)
-#define log_buf_unt8(pbuf, len)  log_buf_out(SHORT_FILE, __LINE__, pbuf, len, LOG_BUF_OUT_DATA_TYPE_UNT8)
-#define log_compile_time()  do {\
-                            log_info("compile date = %s\r\n", __DATE__);\
-                            log_info("compile time = %s\r\n", __TIME__);\
-                            } while (0 == 1);
-
-int log_buf_out(const char *file, int line, const void *inbuf, int len, LOG_BUF_OUT_DATA_TYPE_T type);
-
-void bl_printk(const char *format, ...);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
diff --git a/bsp/bl808/m0/libraries/utils/include/utils_md5.h b/bsp/bl808/m0/libraries/utils/include/utils_md5.h
deleted file mode 100644
index 2ac9461e9f..0000000000
--- a/bsp/bl808/m0/libraries/utils/include/utils_md5.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-
-
-
-#ifndef _IOTX_COMMON_MD5_H_
-#define _IOTX_COMMON_MD5_H_
-
-#include "iot_import.h"
-
-typedef struct {
-    uint32_t total[2];          /*!< number of bytes processed  */
-    uint32_t state[4];          /*!< intermediate digest state  */
-    unsigned char buffer[64];   /*!< data block being processed */
-} iot_md5_context;
-
-/**
- * \brief          Initialize MD5 context
- *
- * \param ctx      MD5 context to be initialized
- */
-void utils_md5_init(iot_md5_context *ctx);
-
-/**
- * \brief          Clear MD5 context
- *
- * \param ctx      MD5 context to be cleared
- */
-void utils_md5_free(iot_md5_context *ctx);
-
-/**
- * \brief          Clone (the state of) an MD5 context
- *
- * \param dst      The destination context
- * \param src      The context to be cloned
- */
-void utils_md5_clone(iot_md5_context *dst,
-                     const iot_md5_context *src);
-
-/**
- * \brief          MD5 context setup
- *
- * \param ctx      context to be initialized
- */
-void utils_md5_starts(iot_md5_context *ctx);
-
-/**
- * \brief          MD5 process buffer
- *
- * \param ctx      MD5 context
- * \param input    buffer holding the  data
- * \param ilen     length of the input data
- */
-void utils_md5_update(iot_md5_context *ctx, const unsigned char *input, size_t ilen);
-
-/**
- * \brief          MD5 final digest
- *
- * \param ctx      MD5 context
- * \param output   MD5 checksum result
- */
-void utils_md5_finish(iot_md5_context *ctx, unsigned char output[16]);
-
-/* Internal use */
-void utils_md5_process(iot_md5_context *ctx, const unsigned char data[64]);
-
-/**
- * \brief          Output = MD5( input buffer )
- *
- * \param input    buffer holding the  data
- * \param ilen     length of the input data
- * \param output   MD5 checksum result
- */
-void utils_md5(const unsigned char *input, size_t ilen, unsigned char output[16]);
-
-#endif
-
diff --git a/bsp/bl808/m0/libraries/utils/include/utils_memp.h b/bsp/bl808/m0/libraries/utils/include/utils_memp.h
deleted file mode 100644
index e89951d7e4..0000000000
--- a/bsp/bl808/m0/libraries/utils/include/utils_memp.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef __UTILS_MEMP_H__
-#define __UTILS_MEMP_H__
-
-
-struct utils_memp_node {
-    struct utils_memp_node *next;
-};
-
-typedef struct pool {
-    uint32_t node_size;
-    uint32_t pool_cap;
-    uint32_t pool_size;
-    uint8_t align_req;
-    uint32_t padded_node_size;
-    void *first_node;
-    void *last_node;
-    struct utils_memp_node *mem;
-}utils_memp_pool_t;
-
-int utils_memp_init(utils_memp_pool_t **pool, uint16_t node_size, uint16_t pool_cap, uint8_t align_req);
-int utils_memp_init_alloced(utils_memp_pool_t *pool, uint16_t node_size, uint16_t pool_cap, uint8_t align_req);
-int utils_memp_deinit(utils_memp_pool_t *pool);
-void *utils_memp_malloc(utils_memp_pool_t *pool);
-int utils_memp_free(utils_memp_pool_t *pool, void *node);
-
-#endif
diff --git a/bsp/bl808/m0/libraries/utils/include/utils_notifier.h b/bsp/bl808/m0/libraries/utils/include/utils_notifier.h
deleted file mode 100644
index 3120cb004c..0000000000
--- a/bsp/bl808/m0/libraries/utils/include/utils_notifier.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __NOTIFIER_H__
-#define __NOTIFIER_H__
-
-#include 
-
-typedef struct utils_list ntf_list_t;
-typedef int (*utils_notifier_fn_t)(void *cb_arg, void *env);
-
-typedef struct utils_notifier {
-    struct utils_list_hdr node;
-    utils_notifier_fn_t cb;
-    void *cb_arg;
-    int priority;
-} utils_notifier_t;
-
-int utils_notifier_chain_init(ntf_list_t *nl);
-int utils_notifier_chain_register(ntf_list_t *nl, utils_notifier_t *node);
-int utils_notifier_chain_call(ntf_list_t *nl, void *env);
-
-#endif
-
diff --git a/bsp/bl808/m0/libraries/utils/include/utils_psk_fast.h b/bsp/bl808/m0/libraries/utils/include/utils_psk_fast.h
deleted file mode 100644
index d178344b0b..0000000000
--- a/bsp/bl808/m0/libraries/utils/include/utils_psk_fast.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef __UTILS_PSK_FAST_H__
-#define __UTILS_PSK_FAST_H__
-
-int utils_wifi_psk_cal_fast(char *password, char *ssid, int ssid_len, char *output);
-int utils_wifi_psk_cal_fast_bin(char *password, unsigned char *ssid, int ssidlength, unsigned char *output);
-
-#endif /* __UTILS_PSK_FAST_H__ */
diff --git a/bsp/bl808/m0/libraries/utils/include/utils_rbtree.h b/bsp/bl808/m0/libraries/utils/include/utils_rbtree.h
deleted file mode 100644
index 068b3daa4a..0000000000
--- a/bsp/bl808/m0/libraries/utils/include/utils_rbtree.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __UTILS_RBTREE_H__
-#define __UTILS_RBTREE_H__
-
-#include 
-#include 
-#include 
-
-#ifndef RB_ITER_MAX_HEIGHT
-#define RB_ITER_MAX_HEIGHT 64 // Tallest allowable tree to iterate
-#endif
-
-struct rb_node;
-struct rb_tree;
-
-typedef int  (*rb_tree_node_cmp_f) (struct rb_tree *self, struct rb_node *a, struct rb_node *b);
-typedef void (*rb_tree_node_f)     (struct rb_tree *self, struct rb_node *node);
-
-struct rb_node {
-    int             red;     // Color red (1), black (0)
-    struct rb_node *link[2]; // Link left [0] and right [1]
-    void           *value;   // User provided, used indirectly via rb_tree_node_cmp_f.
-};
-
-struct rb_tree {
-    struct rb_node    *root;
-    rb_tree_node_cmp_f cmp;
-    size_t             size;
-    void              *info; // User provided, not used by rb_tree.
-};
-
-struct rb_iter {
-    struct rb_tree *tree;
-    struct rb_node *node;                     // Current node
-    struct rb_node *path[RB_ITER_MAX_HEIGHT]; // Traversal path
-    size_t          top;                      // Top of stack
-    void           *info;                     // User provided, not used by rb_iter.
-};
-
-int             rb_tree_node_cmp_ptr_cb (struct rb_tree *self, struct rb_node *a, struct rb_node *b);
-void            rb_tree_node_dealloc_cb (struct rb_tree *self, struct rb_node *node);
-
-struct rb_node *rb_node_alloc           ();
-struct rb_node *rb_node_create          (void *value);
-struct rb_node *rb_node_init            (struct rb_node *self, void *value);
-void            rb_node_dealloc         (struct rb_node *self);
-
-struct rb_tree *rb_tree_alloc           ();
-struct rb_tree *rb_tree_create          (rb_tree_node_cmp_f cmp);
-struct rb_tree *rb_tree_init            (struct rb_tree *self, rb_tree_node_cmp_f cmp);
-void            rb_tree_dealloc         (struct rb_tree *self, rb_tree_node_f node_cb);
-void           *rb_tree_find            (struct rb_tree *self, void *value);
-int             rb_tree_insert          (struct rb_tree *self, void *value);
-int             rb_tree_remove          (struct rb_tree *self, void *value);
-size_t          rb_tree_size            (struct rb_tree *self);
-
-int             rb_tree_insert_node     (struct rb_tree *self, struct rb_node *node);
-int             rb_tree_remove_with_cb  (struct rb_tree *self, void *value, rb_tree_node_f node_cb);
-
-int             rb_tree_test            (struct rb_tree *self, struct rb_node *root);
-
-struct rb_iter *rb_iter_alloc           ();
-struct rb_iter *rb_iter_init            ();
-struct rb_iter *rb_iter_create          ();
-void            rb_iter_dealloc         (struct rb_iter *self);
-void           *rb_iter_first           (struct rb_iter *self, struct rb_tree *tree);
-void           *rb_iter_last            (struct rb_iter *self, struct rb_tree *tree);
-void           *rb_iter_next            (struct rb_iter *self);
-void           *rb_iter_prev            (struct rb_iter *self);
-
-#endif
diff --git a/bsp/bl808/m0/libraries/utils/include/utils_ringblk.h b/bsp/bl808/m0/libraries/utils/include/utils_ringblk.h
deleted file mode 100644
index 91526bccf1..0000000000
--- a/bsp/bl808/m0/libraries/utils/include/utils_ringblk.h
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _UTILS_RINGBLK_H_
-#define _UTILS_RINGBLK_H_
-
-
-#include "stddef.h"
-#include 
-#include "utils_list.h"
-
-
-#define UTILS_RINGBLK_TEST
-
-/*
- * Introduction:
- * The rbb is the ring buffer which is composed with many blocks. It is different from the ring buffer.
- * The ring buffer is only composed with chars. The rbb put and get supported zero copies. So the rbb
- * is very suitable for put block and get block by a certain order. Such as DMA block transmit,
- * communicate frame send/recv, and so on.
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-enum utils_rbb_status
-{
-    /* unused status when first initialize or after blk_free() */
-    RBB_BLK_UNUSED,
-    /* initialized status after blk_alloc() */
-    RBB_BLK_INITED,
-    /* put status after blk_put() */
-    RBB_BLK_PUT,
-    /* get status after blk_get() */
-    RBB_BLK_GET,
-};
-typedef enum utils_rbb_status utils_rbb_status_t;
-
-/**
- * the block of rbb
- */
-struct utils_rbb_blk
-{
-    utils_rbb_status_t status :8;
-    /* less then 2^24 */
-    uint32_t size :24;
-    uint8_t *buf;
-    utils_slist_t list;
-};
-typedef struct utils_rbb_blk *utils_rbb_blk_t;
-
-/**
- * Rbb block queue: the blocks (from block1->buf to blockn->buf) memory which on this queue is continuous.
- */
-struct utils_rbb_blk_queue
-{
-    utils_rbb_blk_t blocks;
-    uint32_t blk_num;
-};
-typedef struct utils_rbb_blk_queue *utils_rbb_blk_queue_t;
-
-/**
- * ring block buffer
- */
-struct utils_rbb
-{
-    uint8_t *buf;
-    uint32_t buf_size;
-    /* all of blocks */
-    utils_rbb_blk_t blk_set;
-    uint32_t blk_max_num;
-    /* saved the initialized and put status blocks */
-    utils_slist_t blk_list;
-};
-typedef struct utils_rbb *utils_rbb_t;
-
-/* rbb (ring block buffer) API */
-void utils_rbb_init(utils_rbb_t rbb, uint8_t *buf, uint32_t buf_size, utils_rbb_blk_t block_set, uint32_t blk_max_num);
-uint32_t utils_rbb_get_buf_size(utils_rbb_t rbb);
-
-utils_rbb_t utils_rbb_create(uint32_t buf_size, uint32_t blk_max_num);
-void utils_rbb_destroy(utils_rbb_t rbb);
-
-/* rbb block API */
-utils_rbb_blk_t utils_rbb_blk_alloc(utils_rbb_t rbb, uint32_t blk_size);
-void utils_rbb_blk_put(utils_rbb_blk_t block);
-utils_rbb_blk_t utils_rbb_blk_get(utils_rbb_t rbb);
-uint32_t utils_rbb_blk_size(utils_rbb_blk_t block);
-uint8_t *utils_rbb_blk_buf(utils_rbb_blk_t block);
-void utils_rbb_blk_free(utils_rbb_t rbb, utils_rbb_blk_t block);
-utils_rbb_blk_t utils_rbb_find_empty_blk(utils_rbb_t rbb);
-utils_rbb_blk_t utils_rbb_find_used_blk(utils_rbb_t rbb);
-
-/* rbb block queue API */
-uint32_t utils_rbb_blk_queue_get(utils_rbb_t rbb, uint32_t queue_data_len, utils_rbb_blk_queue_t blk_queue);
-uint32_t utils_rbb_blk_queue_len(utils_rbb_blk_queue_t blk_queue);
-uint8_t *utils_rbb_blk_queue_buf(utils_rbb_blk_queue_t blk_queue);
-void utils_rbb_blk_queue_free(utils_rbb_t rbb, utils_rbb_blk_queue_t blk_queue);
-uint32_t utils_rbb_next_blk_queue_len(utils_rbb_t rbb);
-
-
-int utils_rbb_cli_init(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _UTILS_RINGBLK_H_ */
diff --git a/bsp/bl808/m0/libraries/utils/include/utils_sha1.h b/bsp/bl808/m0/libraries/utils/include/utils_sha1.h
deleted file mode 100644
index 422ee3d59e..0000000000
--- a/bsp/bl808/m0/libraries/utils/include/utils_sha1.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-
-
-
-#ifndef _IOTX_COMMON_SHA1_H_
-#define _IOTX_COMMON_SHA1_H_
-
-#include "iot_import.h"
-
-
-/**
- * \brief          SHA-1 context structure
- */
-typedef struct {
-    uint32_t total[2];          /*!< number of bytes processed  */
-    uint32_t state[5];          /*!< intermediate digest state  */
-    unsigned char buffer[64];   /*!< data block being processed */
-} iot_sha1_context;
-
-/**
- * \brief          Initialize SHA-1 context
- *
- * \param ctx      SHA-1 context to be initialized
- */
-void utils_sha1_init(iot_sha1_context *ctx);
-
-/**
- * \brief          Clear SHA-1 context
- *
- * \param ctx      SHA-1 context to be cleared
- */
-void utils_sha1_free(iot_sha1_context *ctx);
-
-/**
- * \brief          Clone (the state of) a SHA-1 context
- *
- * \param dst      The destination context
- * \param src      The context to be cloned
- */
-void utils_sha1_clone(iot_sha1_context *dst,
-                      const iot_sha1_context *src);
-
-/**
- * \brief          SHA-1 context setup
- *
- * \param ctx      context to be initialized
- */
-void utils_sha1_starts(iot_sha1_context *ctx);
-
-/**
- * \brief          SHA-1 process buffer
- *
- * \param ctx      SHA-1 context
- * \param input    buffer holding the  data
- * \param ilen     length of the input data
- */
-void utils_sha1_update(iot_sha1_context *ctx, const unsigned char *input, size_t ilen);
-
-/**
- * \brief          SHA-1 final digest
- *
- * \param ctx      SHA-1 context
- * \param output   SHA-1 checksum result
- */
-void utils_sha1_finish(iot_sha1_context *ctx, unsigned char output[20]);
-
-/* Internal use */
-void utils_sha1_process(iot_sha1_context *ctx, const unsigned char data[64]);
-
-/**
- * \brief          Output = SHA-1( input buffer )
- *
- * \param input    buffer holding the  data
- * \param ilen     length of the input data
- * \param output   SHA-1 checksum result
- */
-void utils_sha1(const unsigned char *input, size_t ilen, unsigned char output[20]);
-
-#endif
diff --git a/bsp/bl808/m0/libraries/utils/include/utils_sha256.h b/bsp/bl808/m0/libraries/utils/include/utils_sha256.h
deleted file mode 100644
index 42379eba45..0000000000
--- a/bsp/bl808/m0/libraries/utils/include/utils_sha256.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-
-
-
-#ifndef _IOTX_COMMON_SHA256_H_
-#define _IOTX_COMMON_SHA256_H_
-
-#include 
-
-#define SHA256_DIGEST_LENGTH            (32)
-#define SHA256_BLOCK_LENGTH             (64)
-#define SHA256_SHORT_BLOCK_LENGTH       (SHA256_BLOCK_LENGTH - 8)
-#define SHA256_DIGEST_STRING_LENGTH     (SHA256_DIGEST_LENGTH * 2 + 1)
-
-/**
- * \brief          SHA-256 context structure
- */
-typedef struct {
-    uint32_t total[2];          /*!< number of bytes processed  */
-    uint32_t state[8];          /*!< intermediate digest state  */
-    unsigned char buffer[64];   /*!< data block being processed */
-    int is224;                  /*!< 0 => SHA-256, else SHA-224 */
-} iot_sha256_context;
-
-typedef union {
-    char sptr[8];
-    uint64_t lint;
-} u_retLen;
-
-/**
- * \brief          Initialize SHA-256 context
- *
- * \param ctx      SHA-256 context to be initialized
- */
-void utils_sha256_init(iot_sha256_context *ctx);
-
-/**
- * \brief          Clear SHA-256 context
- *
- * \param ctx      SHA-256 context to be cleared
- */
-void utils_sha256_free(iot_sha256_context *ctx);
-
-/**
- * \brief          Clone (the state of) a SHA-256 context
- *
- * \param dst      The destination context
- * \param src      The context to be cloned
- */
-void utils_sha256_clone(iot_sha256_context *dst,
-                        const iot_sha256_context *src);
-
-/**
- * \brief          SHA-256 context setup
- *
- * \param ctx      context to be initialized
- */
-void utils_sha256_starts(iot_sha256_context *ctx);
-
-/**
- * \brief          SHA-256 process buffer
- *
- * \param ctx      SHA-256 context
- * \param input    buffer holding the  data
- * \param ilen     length of the input data
- */
-void utils_sha256_update(iot_sha256_context *ctx, const unsigned char *input, uint32_t ilen);
-
-/**
- * \brief          SHA-256 final digest
- *
- * \param ctx      SHA-256 context
- * \param output   SHA-256 checksum result
- */
-void utils_sha256_finish(iot_sha256_context *ctx, uint8_t output[32]);
-
-/* Internal use */
-void utils_sha256_process(iot_sha256_context *ctx, const unsigned char data[64]);
-
-/**
- * \brief          Output = SHA-256( input buffer )
- *
- * \param input    buffer holding the  data
- * \param ilen     length of the input data
- * \param output   SHA-256 checksum result
- */
-void utils_sha256(const uint8_t *input, uint32_t ilen, uint8_t output[32]);
-
-
-#endif
diff --git a/bsp/bl808/m0/libraries/utils/include/utils_string.h b/bsp/bl808/m0/libraries/utils/include/utils_string.h
deleted file mode 100644
index 6a7626ade6..0000000000
--- a/bsp/bl808/m0/libraries/utils/include/utils_string.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef __UTILS_STRING_H__
-#define __UTILS_STRING_H__
-void get_bytearray_from_string(char** params, uint8_t *result,int array_size);
-void get_uint8_from_string(char** params, uint8_t *result);
-void get_uint16_from_string(char** params, uint16_t *result);
-void get_uint32_from_string(char** params, uint32_t *result);
-void utils_parse_number(const char *str, char sep, uint8_t *buf, int buflen, int base);
-void utils_parse_number_adv(const char *str, char sep, uint8_t *buf, int buflen, int base, int *count);
-unsigned long long convert_arrayToU64(uint8_t* inputArray);
-void convert_u64ToArray(unsigned long long inputU64, uint8_t result[8]);
-void utils_memcpy8(void *dst, void *src, size_t len);
-void utils_memcpy16(void *dst, void *src, size_t len);
-void utils_memcpy32(void *dst, void *src, size_t len);
-void utils_memcpy64(void *dst, void *src, size_t len);
-void utils_memset8(void *src, uint8_t n, size_t len);
-void utils_memset16(void *src, uint16_t n, size_t len);
-void utils_memset32(void *src, uint32_t n, size_t len);
-void utils_memset64(void *src, uint64_t n, size_t len);
-void utils_memset8_with_seq(void *src, uint8_t seq, size_t len);
-void utils_memset16_with_seq(void *src, uint16_t seq, size_t len);
-void utils_memset32_with_seq(void *src, uint32_t seq, size_t len);
-void utils_memset64_with_seq(void *src, uint64_t seq, size_t len);
-void utils_memdrain8(void *src, size_t len);
-void utils_memdrain16(void *src, size_t len);
-void utils_memdrain32(void *src, size_t len);
-void utils_memdrain64(void *src, size_t len);
-void * utils_memdrain8_with_check(void *src, size_t len, uint8_t seq);
-void * utils_memdrain16_with_check(void *src, size_t len, uint16_t seq);
-void * utils_memdrain32_with_check(void *src, size_t len, uint32_t seq);
-void * utils_memdrain64_with_check(void *src, size_t len, uint64_t seq);
-#endif
diff --git a/bsp/bl808/m0/libraries/utils/include/utils_time.h b/bsp/bl808/m0/libraries/utils/include/utils_time.h
deleted file mode 100644
index 3c3466c535..0000000000
--- a/bsp/bl808/m0/libraries/utils/include/utils_time.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef __UTILS_TIME_H__
-#define __UTILS_TIME_H__
-typedef struct {
-    unsigned char ntp_hour;
-    unsigned char ntp_minute;
-    unsigned char ntp_second;
-    unsigned char ntp_week_day;
-    unsigned char ntp_date;
-    unsigned char ntp_month;
-    unsigned char leap_days;
-    unsigned char leap_year_ind;
-    unsigned int ntp_year;
-    unsigned int days_since_epoch;
-    unsigned int day_of_year;
-} utils_time_date_t;
-
-int utils_time_date_from_epoch(unsigned int epoch, utils_time_date_t *date);
-
-#endif
diff --git a/bsp/bl808/m0/libraries/utils/include/utils_tlv_bl.h b/bsp/bl808/m0/libraries/utils/include/utils_tlv_bl.h
deleted file mode 100644
index 8ee870f6c6..0000000000
--- a/bsp/bl808/m0/libraries/utils/include/utils_tlv_bl.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef __UTILS_TLV_BL_H__
-#define __UTILS_TLV_BL_H__
-#include 
-#include 
-
-#define CFG_ELEMENT_TYPE_SIZE_BOOLEAN                 (4)
-#define CFG_ELEMENT_TYPE_SIZE_UINT32                  (4)
-#define UTILS_TLV_BL_ERROR_CODE_BUF_TOO_SMALL         (-1)
-#define UTILS_TLV_BL_ERROR_CODE_UNKOWN                (-2)
-// Wi-Fi CFG API
-enum CFG_ELEMENT_TYPE {
-    CFG_ELEMENT_TYPE_UNKNOWN,
-    CFG_ELEMENT_TYPE_BOOLEAN,
-    CFG_ELEMENT_TYPE_SINT8,
-    CFG_ELEMENT_TYPE_UINT8,
-    CFG_ELEMENT_TYPE_SINT16,
-    CFG_ELEMENT_TYPE_UINT16,
-    CFG_ELEMENT_TYPE_SINT32,
-    CFG_ELEMENT_TYPE_UINT32,
-    CFG_ELEMENT_TYPE_STRING,
-};
-
-enum CFG_ELEMENT_TYPE_OPS
-{
-    CFG_ELEMENT_TYPE_OPS_SET,
-    CFG_ELEMENT_TYPE_OPS_GET,
-    CFG_ELEMENT_TYPE_OPS_RESET,
-    CFG_ELEMENT_TYPE_OPS_DUMP_DEBUG,
-    CFG_ELEMENT_TYPE_OPS_UNKNOWN,
-};
-
-int utils_tlv_bl_pack_bool(uint32_t *buf, int buf_sz, bool val);
-int utils_tlv_bl_pack_uint8(uint32_t *buf, int buf_sz, uint8_t val);
-int utils_tlv_bl_pack_int8(uint32_t *buf, int buf_sz, int8_t val);
-int utils_tlv_bl_pack_uint16(uint32_t *buf, int buf_sz, uint16_t val);
-int utils_tlv_bl_pack_int16(uint32_t *buf, int buf_sz, int16_t val);
-int utils_tlv_bl_pack_uint32(uint32_t *buf, int buf_sz, uint32_t val);
-int utils_tlv_bl_pack_int32(uint32_t *buf, int buf_sz, int32_t val);
-int utils_tlv_bl_pack_string(uint32_t *buf, int buf_sz, const char *str);
-int utils_tlv_bl_pack_auto(uint32_t *buf, int buf_sz, uint16_t type, void *arg1);
-
-int utils_tlv_bl_unpack_bool(uint32_t *buf, int buf_sz, bool *val);
-int utils_tlv_bl_unpack_uint8(uint32_t *buf, int buf_sz, uint8_t *val);
-int utils_tlv_bl_unpack_int8(uint32_t *buf, int buf_sz, int8_t *val);
-int utils_tlv_bl_unpack_uint16(uint32_t *buf, int buf_sz, uint16_t *val);
-int utils_tlv_bl_unpack_int16(uint32_t *buf, int buf_sz, int16_t *val);
-int utils_tlv_bl_unpack_uint32(uint32_t *buf, int buf_sz, uint32_t *val);
-int utils_tlv_bl_unpack_int32(uint32_t *buf, int buf_sz, int32_t *val);
-int utils_tlv_bl_unpack_string(uint32_t *buf, int buf_sz, char *str, int size);
-int utils_tlv_bl_unpack_auto(uint32_t *buf, int buf_sz, uint16_t type, void *arg1);
-#endif
diff --git a/bsp/bl808/m0/libraries/utils/src/test/test_utils_base64.c b/bsp/bl808/m0/libraries/utils/src/test/test_utils_base64.c
deleted file mode 100644
index 0dee7bc1fc..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/test/test_utils_base64.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include 
-#include 
-#include 
-#include 
-#include 
-#ifdef CONFIG_CLI_CMD_ENABLE
-#include 
-#endif
-#include "utils_base64.h"
-#include 
-
-#ifdef UTILS_BASE64_TEST
-
-static void cmd_encode(char *buf, int len, int argc, char **argv)
-{
-    uint32_t input_len, output_len = 0;
-    char *inbuf, *outbuf = NULL;
-
-    if (argc != 3)
-    {
-        log_error("Usage:\r\n");
-        log_error("encode_base64 0x420c0000 512\r\n");
-        return;
-    }
-
-    inbuf = (char *)strtol(argv[1], NULL, 0);
-    input_len = strtol(argv[2], NULL, 0);
-    if (inbuf != NULL && input_len != 0)
-    {
-        output_len = 4 * ((input_len + 2) / 3);
-        outbuf = calloc(1, output_len);
-
-        if (outbuf)
-        {
-            if (SUCCESS_RETURN == utils_base64encode((uint8_t *)inbuf, input_len, output_len, (uint8_t *)outbuf, &output_len))
-            {
-                uint32_t i = 0;
-                char *addr = outbuf;
-                for (i = 0; i < output_len; i++)
-                {
-                #ifdef CONFIG_CLI_CMD_ENABLE
-                    aos_cli_printf("%c", *(char *)addr);
-                #endif
-                    addr += 1;
-                }
-            }
-            else
-            {
-                log_error("base64 encode error\r\n");
-            }
-
-            free(outbuf);
-        }
-        else
-        {
-            log_error("base64 encode mem not enough %d\r\n", output_len);
-        }
-    }
-    else
-    {
-        log_error("base64 encode argc error\r\n");
-    }
-
-}
-
-#ifdef CONFIG_CLI_CMD_ENABLE
-const static struct cli_command cmds_user[] STATIC_CLI_CMD_ATTRIBUTE = {
-        { "encode_base64", "base64 encode", cmd_encode},
-};
-#endif
-
-int base64_cli_init(void)
-{
-    // static command(s) do NOT need to call aos_cli_register_command(s) to register.
-    // However, calling aos_cli_register_command(s) here is OK but is of no effect as cmds_user are included in cmds list.
-    // XXX NOTE: Calling this *empty* function is necessary to make cmds_user in this file to be kept in the final link.
-    //return aos_cli_register_commands(cmds_user, sizeof(cmds_user) / sizeof(cmds_user[0]));
-    return 0;
-}
-#endif
diff --git a/bsp/bl808/m0/libraries/utils/src/test/test_utils_bitmap_window.c b/bsp/bl808/m0/libraries/utils/src/test/test_utils_bitmap_window.c
deleted file mode 100644
index f2cc9e9146..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/test/test_utils_bitmap_window.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include 
-
-#ifdef CONFIG_CLI_CMD_ENABLE
-#include 
-#endif
-#include 
-
-static void cmd_bitmap_window_test(char *buf, int len, int argc, char **argv)
-{
-    int ret;
-    struct utils_bitmap_ctx ctx;
-
-    utils_bitmap_window_init(&ctx, 0, 4095);
-
-    printf("Set Seq 1 2 3 4 5 6 7...\r\n");
-    utils_bitmap_window_bit_set(&ctx, 1);
-    utils_bitmap_window_bit_set(&ctx, 2);
-    utils_bitmap_window_bit_set(&ctx, 3);
-    utils_bitmap_window_bit_set(&ctx, 4);
-    utils_bitmap_window_bit_set(&ctx, 5);
-    utils_bitmap_window_bit_set(&ctx, 6);
-    ret = utils_bitmap_window_bit_set(&ctx, 7);
-    printf("  Got ssn %d(0) Bitmap %llx(0), ret %x\r\n",
-        utils_bitmap_window_ssn_get(&ctx),
-        utils_bitmap_window_map_get(&ctx),
-        ret
-    );
-
-    printf("Set Seq 0 ...\r\n");
-    ret = utils_bitmap_window_bit_set(&ctx, 0);
-    printf("  Got ssn %d(8) Bitmap %llx(0), ret %x\r\n",
-        utils_bitmap_window_ssn_get(&ctx),
-        utils_bitmap_window_map_get(&ctx),
-        ret
-    );
-
-    printf("Set Seq 0 ...\r\n");
-    ret = utils_bitmap_window_bit_set(&ctx, 0);
-    printf("  Got ssn %d(8) Bitmap %llx(0), ret %x\r\n",
-        utils_bitmap_window_ssn_get(&ctx),
-        utils_bitmap_window_map_get(&ctx),
-        ret
-    );
-
-    printf("Set Seq 9 ...\r\n");
-    ret = utils_bitmap_window_bit_set(&ctx, 9);
-    printf("  Got ssn %d(8) Bitmap %llx(2), ret %x\r\n",
-        utils_bitmap_window_ssn_get(&ctx),
-        utils_bitmap_window_map_get(&ctx),
-        ret
-    );
-
-    printf("Set Seq 9 ...\r\n");
-    ret = utils_bitmap_window_bit_set(&ctx, 9);
-    printf("  Got ssn %d(8) Bitmap %llx(2), ret %d\r\n",
-        utils_bitmap_window_ssn_get(&ctx),
-        utils_bitmap_window_map_get(&ctx),
-        ret
-    );
-
-}
-
-#ifdef CONFIG_CLI_CMD_ENABLE
-const static struct cli_command cmds_user[] STATIC_CLI_CMD_ATTRIBUTE = {
-  {"utils_bitmap_widow_test", "bitmap window test", cmd_bitmap_window_test},
-};
-#endif
-
-int utils_bitmap_window_cli_init(void)
-{
-    // static command(s) do NOT need to call aos_cli_register_command(s) to register.
-    // However, calling aos_cli_register_command(s) here is OK but is of no effect as cmds_user are included in cmds list.
-    // XXX NOTE: Calling this *empty* function is necessary to make cmds_user in this file to be kept in the final link.
-    //return aos_cli_register_commands(cmds_user, sizeof(cmds_user) / sizeof(cmds_user[0]));
-    return 0;
-}
diff --git a/bsp/bl808/m0/libraries/utils/src/test/test_utils_rbtree.c b/bsp/bl808/m0/libraries/utils/src/test/test_utils_rbtree.c
deleted file mode 100644
index 25c68fe710..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/test/test_utils_rbtree.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include "../../include/utils_rbtree.h"
-#include 
-#include 
-
-struct iovec {
-    void  *iov_base; // [XSI] Base address of I/O memory region
-    size_t iov_len;  // [XSI] Size of region iov_base points to
-};
-
-static int my_cmp_cb(struct rb_tree *self, struct rb_node *node_a, struct rb_node *node_b)
-{
-    struct iovec *a = (struct iovec *) node_a->value;
-    struct iovec *b = (struct iovec *) node_b->value;
-
-    return (a->iov_len > b->iov_len) - (a->iov_len < b->iov_len);
-}
-
-int main(int argc, char *argv[])
-{
-    struct rb_tree *tree = rb_tree_create(my_cmp_cb);
-    if (tree) {
-        // Use the tree here...
-        for (int i = 0; i < 10; i++) {
-            struct iovec *v = malloc(sizeof *v);
-            v->iov_base = (void *) i;
-            v->iov_len = i * i;
-            // Default insert, which allocates internal rb_nodes for you.
-            printf("[rb_tree_insert] insert %p with base %p len %d\r\n",
-                    v,
-                    v->iov_base,
-                    v->iov_len
-            );
-            rb_tree_insert(tree, v);
-        }
-
-        // To f
-        struct iovec *f = rb_tree_find(tree,
-                & (struct iovec) { .iov_base = (void *) 7, .iov_len = 0 }
-        );
-        if (f) {
-            printf("[rb_tree_find] found iovec %p(.iov_base = %p, .iov_len = %zu)\n", f, f->iov_base, f->iov_len);
-        } else {
-            printf("[rb_tree_find] iov_len 9 not found\n");
-        }
-
-        printf("[rb_tree_test] testing...\r\n");
-        rb_tree_test(tree, f);
-
-        f = rb_tree_find(tree,
-                & (struct iovec) { .iov_base = (void *) 7, .iov_len = 10 }
-        );
-        if (f) {
-            printf("[rb_tree_find] found iovec %p(.iov_base = %p, .iov_len = %zu)\n", f, f->iov_base, f->iov_len);
-        } else {
-            printf("[rb_tree_find] iov_len 10 not found\n");
-        }
-
-        printf("[rb_tree_size] is %d\r\n", rb_tree_size(tree));
-
-        // Dealloc call can take optional parameter to notify on each node
-        // being deleted so you can free the node and/or your object:
-        rb_tree_dealloc(tree, NULL);
-    }
-}
-
diff --git a/bsp/bl808/m0/libraries/utils/src/test/test_utils_ringblk.c b/bsp/bl808/m0/libraries/utils/src/test/test_utils_ringblk.c
deleted file mode 100644
index b79f7cd5ac..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/test/test_utils_ringblk.c
+++ /dev/null
@@ -1,388 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#include 
-#include 
-
-#ifdef CONFIG_CLI_CMD_ENABLE
-#include 
-#endif
-#include "utils_ringblk.h"
-
-#ifdef UTILS_RINGBLK_TEST
-
-
-static void cmd_ringblk_test(char *buf, int len, int argc, char **argv)
-{
-    utils_rbb_t rbb;
-    utils_rbb_blk_t blk1, blk2, blk3, blk4, blk5, blk6, _blk1, _blk2;
-    uint32_t i, j, k, req_size, size;
-    struct utils_rbb_blk_queue blk_queue1;
-
-    /* create ring block buffer */
-    printf("\n====================== rbb create test =====================\r\n");
-    rbb = utils_rbb_create(52, 6);
-    if (rbb)
-    {
-        printf("6 blocks in 52 bytes ring block buffer object create success.\r\n");
-    }
-    else
-    {
-        printf("Test error: 6 blocks in 52 bytes ring block buffer object create failed.\r\n");
-    }
-    /* allocate block */
-    printf("\n====================== rbb alloc test =====================\r\n");
-    blk1 = utils_rbb_blk_alloc(rbb, 2);
-    if (blk1 && blk1->size == 2)
-    {
-        memset(blk1->buf, 1, blk1->size);
-        printf("Block1 (2 bytes) allocate success.\r\n");
-    }
-    else
-    {
-        printf("Test error: block1 (2 bytes) allocate failed.\r\n");
-        goto __exit;
-    }
-    blk2 = utils_rbb_blk_alloc(rbb, 4);
-    if (blk2 && blk2->size == 4)
-    {
-        memset(blk2->buf, 2, blk2->size);
-        printf("Block2 (4 bytes) allocate success.\r\n");
-    }
-    else
-    {
-        printf("Test error: block2 (4 bytes) allocate failed.\r\n");
-        goto __exit;
-    }
-    blk3 = utils_rbb_blk_alloc(rbb, 8);
-    if (blk3 && blk3->size == 8)
-    {
-        memset(blk3->buf, 3, blk3->size);
-        printf("Block3 (8 bytes) allocate success.\r\n");
-    }
-    else
-    {
-        printf("Test error: block3 (8 bytes) allocate failed.\r\n");
-        goto __exit;
-    }
-    blk4 = utils_rbb_blk_alloc(rbb, 16);
-    if (blk4 && blk4->size == 16)
-    {
-        memset(blk4->buf, 4, blk4->size);
-        printf("Block4 (16 bytes) allocate success.\r\n");
-    }
-    else
-    {
-        printf("Test error: block4 (16 bytes) allocate failed.\r\n");
-        goto __exit;
-    }
-    blk5 = utils_rbb_blk_alloc(rbb, 32);
-    if (blk5 && blk5->size == 32)
-    {
-        memset(blk5->buf, 5, blk5->size);
-        printf("Block5 (32 bytes) allocate success.\r\n");
-    }
-    else
-    {
-        printf("Block5 (32 bytes) allocate failed.\r\n");
-    }
-    blk5 = utils_rbb_blk_alloc(rbb, 18);
-    if (blk5 && blk5->size == 18)
-    {
-        memset(blk5->buf, 5, blk5->size);
-        printf("Block5 (18 bytes) allocate success.\r\n");
-    }
-    else
-    {
-        printf("Test error: block5 (18 bytes) allocate failed.\r\n");
-        goto __exit;
-    }
-    printf("Ring block buffer current status:\r\n");
-    printf("next block queue length: %"PRIu32"\r\n", utils_rbb_next_blk_queue_len(rbb));
-    printf("block list length: %d\r\n", utils_slist_entry_number(&rbb->blk_list));
-    printf("|<- 2 -->|<-- 4 -->|<---- 8 ----->|<------- 16 -------->|<------ 18 ------>|<---- 4 ---->|\r\n");
-    printf("+--------+---------+--------------+---------------------+------------------+-------------+\r\n");
-    printf("| blcok1 | block2  |    block3    |       block4        |       block5     |    empty    |\r\n");
-    printf("+--------+---------+--------------+---------------------+------------------+-------------+\r\n");
-    printf("| inited | inited  |    inited    |       inited        |       inited     |             |\r\n");
-    //
-    /* put block */
-    printf("\n====================== rbb put test =====================\r\n");
-    utils_rbb_blk_put(blk1);
-    utils_rbb_blk_put(blk2);
-    utils_rbb_blk_put(blk3);
-    utils_rbb_blk_put(blk4);
-    utils_rbb_blk_put(blk5);
-    printf("Block1 to block5 put success.\r\n");
-    printf("Ring block buffer current status:\r\n");
-    printf("next block queue length: %"PRIu32"\r\n", utils_rbb_next_blk_queue_len(rbb));
-    printf("block list length: %d\r\n", utils_slist_entry_number(&rbb->blk_list));
-    printf("|<- 2 -->|<-- 4 -->|<---- 8 ----->|<------- 16 -------->|<------ 18 ------>|<---- 4 ---->|\r\n");
-    printf("+--------+---------+--------------+---------------------+------------------+-------------+\r\n");
-    printf("| blcok1 | block2  |    block3    |       block4        |       block5     |    empty    |\r\n");
-    printf("+--------+---------+--------------+---------------------+------------------+-------------+\r\n");
-    printf("|  put   |  put    |     put      |        put          |        put       |             |\r\n");
-    //
-    /* get block */
-    printf("\n====================== rbb get test =====================\r\n");
-    _blk1 = utils_rbb_blk_get(rbb);
-    _blk2 = utils_rbb_blk_get(rbb);
-    for (i = 0; i < _blk1->size; i++)
-    {
-        if (_blk1->buf[i] != 1) break;
-    }
-    for (j = 0; j < _blk2->size; j++)
-    {
-        if (_blk2->buf[j] != 2) break;
-    }
-    if (blk1 == _blk1 && blk2 == _blk2 && i == _blk1->size && j == _blk2->size)
-    {
-        printf("Block1 and block2 get success.\r\n");
-    }
-    else
-    {
-        printf("Test error: block1 and block2 get failed.\r\n");
-        goto __exit;
-    }
-    printf("Ring block buffer current status:\r\n");
-    printf("next block queue length: %"PRIu32"\r\n", utils_rbb_next_blk_queue_len(rbb));
-    printf("block list length: %d\r\n", utils_slist_entry_number(&rbb->blk_list));
-    printf("|<- 2 -->|<-- 4 -->|<---- 8 ----->|<------- 16 -------->|<------ 18 ------>|<---- 4 ---->|\r\n");
-    printf("+--------+---------+--------------+---------------------+------------------+-------------+\r\n");
-    printf("| blcok1 | block2  |    block3    |       block4        |       block5     |    empty    |\r\n");
-    printf("+--------+---------+--------------+---------------------+------------------+-------------+\r\n");
-    printf("|  get   |   get   |     put      |        put          |        put       |             |\r\n");
-    //
-    /* free block */
-    printf("\n====================== rbb free test =====================\r\n");
-    utils_rbb_blk_free(rbb, blk2);
-    printf("Block2 free success.\r\n");
-    utils_rbb_blk_free(rbb, blk1);
-    printf("Block1 free success.\r\n");
-    printf("Ring block buffer current status:\r\n");
-    printf("next block queue length: %"PRIu32"\r\n", utils_rbb_next_blk_queue_len(rbb));
-    printf("block list length: %d\r\n", utils_slist_entry_number(&rbb->blk_list));
-    printf("|<------- 6 ------>|<---- 8 ----->|<------- 16 -------->|<------ 18 ------>|<---- 4 ---->|\r\n");
-    printf("+------------------+--------------+---------------------+------------------+-------------+\r\n");
-    printf("|      empty2      |    block3    |       block4        |       block5     |    empty1   |\r\n");
-    printf("+------------------+--------------+---------------------+------------------+-------------+\r\n");
-    printf("|                  |     put      |        put          |        put       |             |\r\n");
-
-    blk6 = utils_rbb_blk_alloc(rbb, 5);
-    if (blk6)
-    {
-        printf("Block6 (5 bytes) allocate success.\r\n");
-    }
-    else
-    {
-        printf("Test error: block6 (5 bytes) allocate failed.\r\n");
-        goto __exit;
-    }
-
-    utils_rbb_blk_put(blk6);
-    printf("Block6 put success.\r\n");
-    printf("Ring block buffer current status:\r\n");
-    printf("next block queue length: %"PRIu32"\r\n", utils_rbb_next_blk_queue_len(rbb));
-    printf("block list length: %d\r\n", utils_slist_entry_number(&rbb->blk_list));
-    printf("|<--- 5 ---->|< 1 >|<---- 8 ----->|<------- 16 -------->|<------ 18 ------>|<---- 4 ---->|\r\n");
-    printf("+------------+-----+--------------+---------------------+------------------+-------------+\r\n");
-    printf("|   block6   |empty|    block3    |       block4        |       block5     |   fragment  |\r\n");
-    printf("+------------+-----+--------------+---------------------+------------------+-------------+\r\n");
-    printf("|     put    |     |     put      |        put          |        put       |             |\r\n");
-
-    /* get block queue */
-    printf("\n====================== rbb block queue get test =====================\r\n");
-    req_size = utils_rbb_next_blk_queue_len(rbb) + 5;
-    size = utils_rbb_blk_queue_get(rbb, req_size, &blk_queue1);
-    i = j = k = 0;
-    for (; i < blk3->size; i++)
-    {
-        if (utils_rbb_blk_queue_buf(&blk_queue1)[i] != 3) break;
-    }
-    for (; j < blk4->size; j++)
-    {
-        if (utils_rbb_blk_queue_buf(&blk_queue1)[i + j] != 4) break;
-    }
-    for (; k < blk5->size; k++)
-    {
-        if (utils_rbb_blk_queue_buf(&blk_queue1)[i + j + k] != 5) break;
-    }
-    if (size && size == 42 && utils_rbb_blk_queue_len(&blk_queue1) == 42 && k == blk5->size)
-    {
-        printf("Block queue (request %"PRIu32" bytes, actual %"PRIu32") get success.\r\n", req_size, size);
-    }
-    else
-    {
-        printf("Test error: Block queue (request %"PRIu32" bytes, actual %"PRIu32") get failed.\r\n", req_size, size);
-        goto __exit;
-    }
-    printf("Ring block buffer current status:\r\n");
-    printf("next block queue length: %"PRIu32"\r\n", utils_rbb_next_blk_queue_len(rbb));
-    printf("block list length: %d\r\n", utils_slist_entry_number(&rbb->blk_list));
-    printf("|            |     |<----- block queue1 (42 bytes continuous buffer) ----->|             |\r\n");
-    printf("|<--- 5 ---->|< 1 >|<---- 8 ----->|<------- 16 -------->|<------ 18 ------>|<---- 4 ---->|\r\n");
-    printf("+------------+-----+--------------+---------------------+------------------+-------------+\r\n");
-    printf("|   block6   |empty|    block3    |       block4        |       block5     |   fragment  |\r\n");
-    printf("+------------+-----+--------------+---------------------+------------------+-------------+\r\n");
-    printf("|     put    |     |     get      |        get          |        get       |             |\r\n");
-
-    /* free block queue */
-    printf("\n====================== rbb block queue free test =====================\r\n");
-    utils_rbb_blk_queue_free(rbb, &blk_queue1);
-    printf("Block queue1 free success.\r\n");
-    printf("Ring block buffer current status:\r\n");
-    printf("next block queue length: %"PRIu32"\r\n", utils_rbb_next_blk_queue_len(rbb));
-    printf("block list length: %d\r\n", utils_slist_entry_number(&rbb->blk_list));
-    printf("|<--- 5 ---->|<--------------------------------- 47 ------------------------------------>|\r\n");
-    printf("+------------+---------------------------------------------------------------------------+\r\n");
-    printf("|   block6   |                                 empty                                     |\r\n");
-    printf("+------------+---------------------------------------------------------------------------+\r\n");
-    printf("|     put    |                                                                           |\r\n");
-    utils_rbb_blk_free(rbb, blk6);
-
-    printf("\n====================== rbb static test SUCCESS =====================\r\n");
-
-    printf("\n====================== rbb dynamic test =====================\r\n");
-
-__exit :
-
-    utils_rbb_destroy(rbb);
-}
-
-
-static uint8_t put_finish = 0;
-
-static void put_thread(void *param)
-{
-  utils_rbb_t rbb = (utils_rbb_t)param;
-  utils_rbb_blk_t block;
-  uint32_t put_count = 0;
-
-  put_finish = 0;
-
-  while (put_count < 10000)
-  {
-    block = utils_rbb_blk_alloc(rbb, rand() % 10 + 4);
-    if (block)
-    {
-      memcpy(&block->buf[0], (void *)&put_count, 4);
-      utils_rbb_blk_put(block);
-      printf("put block size %d count %" PRId32 "\r\n", block->size, put_count++);
-    }
-    else
-    {
-      printf("block alloc failed\r\n");
-    }
-    vTaskDelay(rand() % 10);
-  }
-  printf("Put block data finish.\r\n");
-
-  put_finish = 1;
-
-  vTaskDelete(NULL);
-}
-
-static void get_thread(void *param)
-{
-  utils_rbb_t rbb = (utils_rbb_t)param;
-  utils_rbb_blk_t block;
-  uint32_t get_count = 0;
-
-  while (get_count < 10000)
-  {
-    block = utils_rbb_blk_get(rbb);
-
-    if (block)
-    {
-      if (memcmp(&block->buf[0], (void *)&get_count, 4) != 0)
-      {
-        printf("Error: get data (times %" PRId32 ") has an error!\r\n", get_count);
-        goto exit_;
-      }
-      utils_rbb_blk_free(rbb, block);
-      printf("free block size %d count %" PRId32 "\r\n", block->size, get_count++);
-    }
-    else if (put_finish)
-    {
-      break;
-    }
-    vTaskDelay(rand() % 10);
-  }
-  printf("Get block data finish.\r\n");
-
-  utils_rbb_blk_t new_rbb = utils_rbb_find_used_blk(rbb);
-  if (new_rbb != NULL)
-  {
-    printf("\n====================== rbb blk not free =====================\r\n");
-  }
-
-exit_:
-  printf("\n====================== rbb dynamic test finish =====================\r\n");
-
-  utils_rbb_destroy(rbb);
-
-  vTaskDelete(NULL);
-}
-
-static void cmd_ringblk_through_test(char *buf, int len, int argc, char **argv)
-{
-  utils_rbb_t rbb;
-
-  rbb = utils_rbb_create(100, 10);
-
-  xTaskCreate(put_thread, "rbb_put", 1024, rbb, 10, NULL);
-
-  xTaskCreate(get_thread, "rbb_get", 1024, rbb, 10, NULL);
-}
-
-#ifdef CONFIG_CLI_CMD_ENABLE
-const static struct cli_command cmds_user[] STATIC_CLI_CMD_ATTRIBUTE = {
-  {"rbb_static_test", "ringblk static test", cmd_ringblk_test},
-  {"rbb_through_test", "ringblk dynamic test", cmd_ringblk_through_test},
-};
-#endif
-
-int utils_rbb_cli_init(void)
-{
-    // static command(s) do NOT need to call aos_cli_register_command(s) to register.
-    // However, calling aos_cli_register_command(s) here is OK but is of no effect as cmds_user are included in cmds list.
-    // XXX NOTE: Calling this *empty* function is necessary to make cmds_user in this file to be kept in the final link.
-    //return aos_cli_register_commands(cmds_user, sizeof(cmds_user) / sizeof(cmds_user[0]));
-    return 0;
-}
-
-#endif
diff --git a/bsp/bl808/m0/libraries/utils/src/utils_base64.c b/bsp/bl808/m0/libraries/utils/src/utils_base64.c
deleted file mode 100644
index c17b77e988..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/utils_base64.c
+++ /dev/null
@@ -1,206 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include 
-#include 
-#include "utils_base64.h"
-#include 
-
-static int8_t g_encodingTable[] = {'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H',
-                                   'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P',
-                                   'Q', 'R', 'S', 'T', 'U', 'V', 'W', 'X',
-                                   'Y', 'Z', 'a', 'b', 'c', 'd', 'e', 'f',
-                                   'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n',
-                                   'o', 'p', 'q', 'r', 's', 't', 'u', 'v',
-                                   'w', 'x', 'y', 'z', '0', '1', '2', '3',
-                                   '4', '5', '6', '7', '8', '9', '+', '/'
-                                  };
-
-static int8_t g_decodingTable[256];
-static int32_t g_modTable[] = { 0, 2, 1 };
-
-static void build_decoding_table()
-{
-    static int32_t signal = 0;
-    int32_t i = 0;
-
-    if (signal != 0) {
-        return;
-    }
-
-    for (i = 0; i < 64; i++) {
-        g_decodingTable[(uint8_t) g_encodingTable[i]] = i;
-    }
-
-    signal = 1;
-    return;
-}
-
-iotx_err_t utils_base64encode(const uint8_t *data, uint32_t inputLength, uint32_t outputLenMax,
-                              uint8_t *encodedData, uint32_t *outputLength)
-{
-    uint32_t i = 0;
-    uint32_t j = 0;
-
-    if (NULL == encodedData) {
-        log_error("pointer of encodedData is NULL!\r\n");
-        return FAIL_RETURN;
-    }
-
-    *outputLength = 4 * ((inputLength + 2) / 3);
-
-    if (outputLenMax < *outputLength) {
-        log_error("the length of output memory is not enough!\r\n");
-        return FAIL_RETURN;
-    }
-
-    for (i = 0, j = 0; i < inputLength;) {
-        uint32_t octet_a = i < inputLength ? (uint8_t) data[i++] : 0;
-        uint32_t octet_b = i < inputLength ? (uint8_t) data[i++] : 0;
-        uint32_t octet_c = i < inputLength ? (uint8_t) data[i++] : 0;
-
-        uint32_t triple = (octet_a << 0x10) + (octet_b << 0x08) + octet_c;
-
-        encodedData[j++] = g_encodingTable[(triple >> 3 * 6) & 0x3F];
-        encodedData[j++] = g_encodingTable[(triple >> 2 * 6) & 0x3F];
-        encodedData[j++] = g_encodingTable[(triple >> 1 * 6) & 0x3F];
-        encodedData[j++] = g_encodingTable[(triple >> 0 * 6) & 0x3F];
-    }
-
-    for (i = 0; i < g_modTable[inputLength % 3]; i++) {
-        encodedData[*outputLength - 1 - i] = '=';
-    }
-
-    return SUCCESS_RETURN;
-}
-
-/*
- * Streaming Base64 encoder
- * param:
- *  read_data: The callback function when the encoder absorbs data.
- *             A non-zero return indicates the end of the data.
- *  write_data: The callback function when the encoder releases data.
- *  opaque: Callback function context.
- */
-void utils_base64_encode_stream(int (*read_data)(uint8_t *data, void *opaque), void (*write_data)(const uint8_t data[4], void *opaque), void *opaque)
-{
-  uint8_t encodedData[4], c;
-  int end = 0, remainder = -1, i;
-
-  while (!end) {
-    uint32_t octet_a = (end = read_data(&c, opaque)) ? (remainder = (remainder >= 0 ? remainder : 0), 0) : c;
-    uint32_t octet_b = (end = read_data(&c, opaque)) ? (remainder = (remainder >= 0 ? remainder : 1), 0) : c;
-    uint32_t octet_c = (end = read_data(&c, opaque)) ? (remainder = (remainder >= 0 ? remainder : 2), 0) : c;
-
-    uint32_t triple = (octet_a << 0x10) + (octet_b << 0x08) + octet_c;
-
-    if (end && remainder == 0) {
-      return;
-    }
-
-    encodedData[0] = g_encodingTable[(triple >> 3 * 6) & 0x3F];
-    encodedData[1] = g_encodingTable[(triple >> 2 * 6) & 0x3F];
-    encodedData[2] = g_encodingTable[(triple >> 1 * 6) & 0x3F];
-    encodedData[3] = g_encodingTable[(triple >> 0 * 6) & 0x3F];
-
-    if (!end) {
-      write_data(encodedData, opaque);
-    }
-  }
-
-  for (i = 0; i < g_modTable[remainder]; i++) {
-    encodedData[3 - i] = '=';
-  }
-
-  write_data(encodedData, opaque);
-
-  return;
-}
-
-iotx_err_t utils_base64decode(const uint8_t *data, uint32_t inputLength, uint32_t outputLenMax,
-                              uint8_t *decodedData, uint32_t *outputLength)
-{
-    uint32_t i = 0;
-    uint32_t j = 0;
-
-    build_decoding_table();
-
-    if (inputLength % 4 != 0) {
-        log_error("the input length is error!\r\n");
-        return FAIL_RETURN;
-    }
-
-    *outputLength = inputLength / 4 * 3;
-
-
-    if (data[inputLength - 1] == '=') {
-        (*outputLength)--;
-    }
-
-    if (data[inputLength - 2] == '=') {
-        (*outputLength)--;
-    }
-
-    if (outputLenMax < *outputLength) {
-        log_error("the length of output memory is not enough!\r\n");
-        return FAIL_RETURN;
-    }
-
-    uint32_t sextet_a = 0;
-    uint32_t sextet_b = 0;
-    uint32_t sextet_c = 0;
-    uint32_t sextet_d = 0;
-    uint32_t triple = 0;
-
-    for (i = 0, j = 0; i < inputLength;) {
-        sextet_a = data[i] == '=' ? 0 & i++ : g_decodingTable[data[i++]];
-        sextet_b = data[i] == '=' ? 0 & i++ : g_decodingTable[data[i++]];
-        sextet_c = data[i] == '=' ? 0 & i++ : g_decodingTable[data[i++]];
-        sextet_d = data[i] == '=' ? 0 & i++ : g_decodingTable[data[i++]];
-
-        triple = (sextet_a << 3 * 6) + (sextet_b << 2 * 6) + (sextet_c << 1 * 6) + (sextet_d << 0 * 6);
-
-        if (j < *outputLength) {
-            decodedData[j++] = (triple >> 2 * 8) & 0xFF;
-        }
-
-        if (j < *outputLength) {
-            decodedData[j++] = (triple >> 1 * 8) & 0xFF;
-        }
-
-        if (j < *outputLength) {
-            decodedData[j++] = (triple >> 0 * 8) & 0xFF;
-        }
-    }
-
-    return SUCCESS_RETURN;
-}
-
-
diff --git a/bsp/bl808/m0/libraries/utils/src/utils_bitmap_window.c b/bsp/bl808/m0/libraries/utils/src/utils_bitmap_window.c
deleted file mode 100644
index 3feb69c765..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/utils_bitmap_window.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include 
-#include 
-#include 
-#include 
-
-int utils_bitmap_window_init(struct utils_bitmap_ctx *ctx, int ssn, int ssn_max)
-{
-    memset(ctx, 0, sizeof(struct utils_bitmap_ctx));
-    ctx->ssn = ssn;
-    ctx->ssn_duration = ssn_max + 1;//ssn start from 0
-
-    return 0;
-}
-
-int utils_bitmap_window_bit_set(struct utils_bitmap_ctx *ctx, int bit_pos)
-{
-    int i;
-    int pos_offset;
-
-    if (bit_pos < ctx->ssn) {
-        /*failed case*/
-        if (ctx->ssn_duration - ctx->ssn + bit_pos + 1 > sizeof(ctx->bitmap) * 8) {
-            printf("small ssn %d\r\n", bit_pos);
-            return -INT_MAX;
-        }
-    }
-    pos_offset = bit_pos + ctx->ssn_duration - ctx->ssn;
-    if (pos_offset >= ctx->ssn_duration) {
-        pos_offset -= ctx->ssn_duration;
-    }
-
-    if (ctx->bitmap.map64 & (1 << pos_offset)) {
-        printf("Dup bit_pos %d with pos_offset %d\r\n", bit_pos, pos_offset);
-        return -bit_pos;
-    }
-    ctx->bitmap.map64 |= (1 << pos_offset);//TODO use bytearray
-
-    for (i = 0; i < sizeof(ctx->bitmap.bytes) * 8; i++) {
-        if (ctx->bitmap.map64 & 0x1) {
-            ctx->bitmap.map64 >>= 1;
-            ctx->ssn += 1;
-            if (ctx->ssn == ctx->ssn_duration) {
-                ctx->ssn = 0;
-            }
-        }
-    }
-    return pos_offset;
-}
-
-uint64_t utils_bitmap_window_map_get(struct utils_bitmap_ctx *ctx)
-{
-    return ctx->bitmap.map64;
-}
-
-int utils_bitmap_window_ssn_get(struct utils_bitmap_ctx *ctx)
-{
-    return ctx->ssn;
-}
diff --git a/bsp/bl808/m0/libraries/utils/src/utils_crc.c b/bsp/bl808/m0/libraries/utils/src/utils_crc.c
deleted file mode 100644
index 237bb581b1..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/utils_crc.c
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include 
-#include 
-#include 
-
-#include 
-
-// ---------------- POPULAR POLYNOMIALS ----------------
-// CCITT:      x^16 + x^12 + x^5 + x^0                 (0x1021,init 0x0000)
-// CRC-16:     x^16 + x^15 + x^2 + x^0                 (0x8005,init 0xFFFF)
-// we use 0x8005 here and
-
-static const uint8_t chCRCHTalbe[] =
-{
-0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
-0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
-0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
-0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
-0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
-0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
-0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
-0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
-0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
-0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
-0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
-0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
-0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
-0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
-0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
-0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
-0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
-0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
-0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
-0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
-0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
-0x00, 0xC1, 0x81, 0x40
-};
-
-static const uint8_t chCRCLTalbe[] =
-{
-0x00, 0xC0, 0xC1, 0x01, 0xC3, 0x03, 0x02, 0xC2, 0xC6, 0x06, 0x07, 0xC7,
-0x05, 0xC5, 0xC4, 0x04, 0xCC, 0x0C, 0x0D, 0xCD, 0x0F, 0xCF, 0xCE, 0x0E,
-0x0A, 0xCA, 0xCB, 0x0B, 0xC9, 0x09, 0x08, 0xC8, 0xD8, 0x18, 0x19, 0xD9,
-0x1B, 0xDB, 0xDA, 0x1A, 0x1E, 0xDE, 0xDF, 0x1F, 0xDD, 0x1D, 0x1C, 0xDC,
-0x14, 0xD4, 0xD5, 0x15, 0xD7, 0x17, 0x16, 0xD6, 0xD2, 0x12, 0x13, 0xD3,
-0x11, 0xD1, 0xD0, 0x10, 0xF0, 0x30, 0x31, 0xF1, 0x33, 0xF3, 0xF2, 0x32,
-0x36, 0xF6, 0xF7, 0x37, 0xF5, 0x35, 0x34, 0xF4, 0x3C, 0xFC, 0xFD, 0x3D,
-0xFF, 0x3F, 0x3E, 0xFE, 0xFA, 0x3A, 0x3B, 0xFB, 0x39, 0xF9, 0xF8, 0x38,
-0x28, 0xE8, 0xE9, 0x29, 0xEB, 0x2B, 0x2A, 0xEA, 0xEE, 0x2E, 0x2F, 0xEF,
-0x2D, 0xED, 0xEC, 0x2C, 0xE4, 0x24, 0x25, 0xE5, 0x27, 0xE7, 0xE6, 0x26,
-0x22, 0xE2, 0xE3, 0x23, 0xE1, 0x21, 0x20, 0xE0, 0xA0, 0x60, 0x61, 0xA1,
-0x63, 0xA3, 0xA2, 0x62, 0x66, 0xA6, 0xA7, 0x67, 0xA5, 0x65, 0x64, 0xA4,
-0x6C, 0xAC, 0xAD, 0x6D, 0xAF, 0x6F, 0x6E, 0xAE, 0xAA, 0x6A, 0x6B, 0xAB,
-0x69, 0xA9, 0xA8, 0x68, 0x78, 0xB8, 0xB9, 0x79, 0xBB, 0x7B, 0x7A, 0xBA,
-0xBE, 0x7E, 0x7F, 0xBF, 0x7D, 0xBD, 0xBC, 0x7C, 0xB4, 0x74, 0x75, 0xB5,
-0x77, 0xB7, 0xB6, 0x76, 0x72, 0xB2, 0xB3, 0x73, 0xB1, 0x71, 0x70, 0xB0,
-0x50, 0x90, 0x91, 0x51, 0x93, 0x53, 0x52, 0x92, 0x96, 0x56, 0x57, 0x97,
-0x55, 0x95, 0x94, 0x54, 0x9C, 0x5C, 0x5D, 0x9D, 0x5F, 0x9F, 0x9E, 0x5E,
-0x5A, 0x9A, 0x9B, 0x5B, 0x99, 0x59, 0x58, 0x98, 0x88, 0x48, 0x49, 0x89,
-0x4B, 0x8B, 0x8A, 0x4A, 0x4E, 0x8E, 0x8F, 0x4F, 0x8D, 0x4D, 0x4C, 0x8C,
-0x44, 0x84, 0x85, 0x45, 0x87, 0x47, 0x46, 0x86, 0x82, 0x42, 0x43, 0x83,
-0x41, 0x81, 0x80, 0x40
-};
-
-uint16_t utils_crc16(void * dataIn, uint32_t len)
-{
-    uint8_t chCRCHi = 0xFF;
-    uint8_t chCRCLo = 0xFF;
-    uint16_t wIndex;
-  uint8_t* data=(uint8_t *) dataIn;
-
-    while (len--)
-    {
-        wIndex = chCRCLo ^ *data++ ;
-        chCRCLo = chCRCHi ^ chCRCHTalbe[wIndex];
-        chCRCHi = chCRCLTalbe[wIndex] ;
-    }
-
-    return ((chCRCHi << 8) | chCRCLo) ;
-}
-
-/*
-x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1
-*/
-static const uint32_t crc32Tab[256] = {
-    0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f,
-    0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,
-    0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, 0x1db71064, 0x6ab020f2,
-    0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
-    0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9,
-    0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,
-    0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, 0x35b5a8fa, 0x42b2986c,
-    0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
-    0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423,
-    0xcfba9599, 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,
-    0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190, 0x01db7106,
-    0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,
-    0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d,
-    0x91646c97, 0xe6635c01, 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,
-    0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950,
-    0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
-    0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7,
-    0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,
-    0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa,
-    0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
-    0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81,
-    0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,
-    0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, 0xe3630b12, 0x94643b84,
-    0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,
-    0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb,
-    0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,
-    0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, 0xd6d6a3e8, 0xa1d1937e,
-    0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
-    0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55,
-    0x316e8eef, 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,
-    0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe, 0xb2bd0b28,
-    0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
-    0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f,
-    0x72076785, 0x05005713, 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,
-    0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242,
-    0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
-    0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69,
-    0x616bffd3, 0x166ccf45, 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,
-    0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc,
-    0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
-    0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693,
-    0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,
-    0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d
-};
-
-uint32_t utils_crc32(void *dataIn, uint32_t len)
-{
-    uint32_t crc=0;
-  uint8_t *data=(uint8_t *)dataIn;
-
-    crc = crc ^ 0xffffffff;
-
-    while (len--)
-        crc = crc32Tab[(crc ^ *data++) & 0xFF] ^ (crc >> 8);
-
-    return crc ^ 0xffffffff;
-}
-
-void utils_crc32_stream_init(struct crc32_stream_ctx *ctx)
-{
-  ctx->crc = 0xffffffff;
-}
-
-void utils_crc32_stream_feed(struct crc32_stream_ctx *ctx, uint8_t data)
-{
-    ctx->crc = crc32Tab[(ctx->crc ^ data) & 0xFF] ^ (ctx->crc >> 8);
-}
-
-void utils_crc32_stream_feed_block(struct crc32_stream_ctx *ctx, uint8_t *data, uint32_t len)
-{
-  while (len--)
-      ctx->crc = crc32Tab[(ctx->crc ^ *data++) & 0xFF] ^ (ctx->crc >> 8);
-}
-
-uint32_t utils_crc32_stream_results(struct crc32_stream_ctx *ctx)
-{
-  return ctx->crc ^ 0xffffffff;
-}
-
-#define POLY 0x8408
-uint16_t utils_crc16_ccitt(void *dataIn, uint32_t len)
-{
-    uint8_t *data_p=(uint8_t *)dataIn;
-    uint8_t i;
-    uint8_t data;
-    uint16_t crc;
-
-    crc = 0xFFFF;
-
-    if (len == 0)
-        return (~crc);
-
-    do {
-        for (i = 0, data = (unsigned int)0xff & *data_p++;
-            i < 8;
-            i++, data >>= 1) {
-        if ((crc & 0x0001) ^ (data & 0x0001))
-            crc = (crc >> 1) ^ POLY;
-        else
-            crc >>= 1;
-        }
-    } while (--len);
-
-    crc = ~crc;
-
-    data = crc;
-
-    return (crc);
-}
-
diff --git a/bsp/bl808/m0/libraries/utils/src/utils_dns.c b/bsp/bl808/m0/libraries/utils/src/utils_dns.c
deleted file mode 100644
index 0228adb662..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/utils_dns.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include 
-
-int utils_dns_domain_get(uint8_t *records, uint8_t *buf, int *len)
-{
-    int i, pos_in, pos_out, size_buf;
-
-    size_buf = *len;
-
-    pos_in = 0;
-    pos_out = 0;
-    i = records[pos_in++];
-    while (i > 0 && size_buf > 0) {
-        buf[pos_out++] = records[pos_in++];
-        i--;
-        size_buf--;
-
-        if (0 == i && size_buf > 0) {
-            /*current record is empty*/
-            buf[pos_out++] = '.';
-            i = records[pos_in++];
-        }
-    }
-    *len = pos_out;
-
-    return 0;
-}
diff --git a/bsp/bl808/m0/libraries/utils/src/utils_fec.c b/bsp/bl808/m0/libraries/utils/src/utils_fec.c
deleted file mode 100644
index cc2efa4999..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/utils_fec.c
+++ /dev/null
@@ -1,880 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-
-#include 
-#include 
-#include "utils_log.h"
-#include "stdio.h"
-
-#include "utils_fec.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define MSG_CNT     3      /* message-length polynomials count */
-#define POLY_CNT    14     /* (FEC_ECC_LENGTH*2)-length polynomialc count */
-
-typedef struct {
-    uint8_t   _id;
-    uint8_t   _size;    /* Size of reserved memory for this polynomial */
-    uint16_t  _offset;  /* Offset in memory */
-    uint8_t*  _memory;  /* Pointer to pointer to memory */
-    uint8_t   length;
-} blpoly_t;
-
-typedef struct {
-    blpoly_t g_polynoms[MSG_CNT + POLY_CNT];
-    uint8_t g_stack_memory[MSG_CNT * FEC_MSG_LENGTH + POLY_CNT * FEC_ECC_LENGTH * 2];
-    uint8_t g_generator_cache[FEC_ECC_LENGTH + 1];
-    uint8_t g_generator_cached_flag;/* false */
-} fec_context_t;
-
-enum POLY_ID {
-    ID_MSG_IN = 0,
-    ID_MSG_OUT,
-    ID_GENERATOR,
-    ID_TPOLY1,
-    ID_TPOLY2,
-
-    ID_MSG_E,
-
-    ID_TPOLY3,
-    ID_TPOLY4,
-
-    ID_SYNDROMES,
-    ID_FORNEY,
-
-    ID_ERASURES_LOC,
-    ID_ERRORS_LOC,
-
-    ID_ERASURES,
-    ID_ERRORS,
-
-    ID_COEF_POS,
-    ID_ERR_EVAL
-};
-
-/* GF tables pre-calculated for 0x11d primitive polynomial */
-const uint8_t code_exp[512] = {
-    0x1, 0x2, 0x4, 0x8, 0x10, 0x20, 0x40, 0x80, 0x1d, 0x3a, 0x74, 0xe8, 0xcd, 0x87, 0x13, 0x26, 0x4c,
-    0x98, 0x2d, 0x5a, 0xb4, 0x75, 0xea, 0xc9, 0x8f, 0x3, 0x6, 0xc, 0x18, 0x30, 0x60, 0xc0, 0x9d,
-    0x27, 0x4e, 0x9c, 0x25, 0x4a, 0x94, 0x35, 0x6a, 0xd4, 0xb5, 0x77, 0xee, 0xc1, 0x9f, 0x23, 0x46,
-    0x8c, 0x5, 0xa, 0x14, 0x28, 0x50, 0xa0, 0x5d, 0xba, 0x69, 0xd2, 0xb9, 0x6f, 0xde, 0xa1, 0x5f,
-    0xbe, 0x61, 0xc2, 0x99, 0x2f, 0x5e, 0xbc, 0x65, 0xca, 0x89, 0xf, 0x1e, 0x3c, 0x78, 0xf0, 0xfd,
-    0xe7, 0xd3, 0xbb, 0x6b, 0xd6, 0xb1, 0x7f, 0xfe, 0xe1, 0xdf, 0xa3, 0x5b, 0xb6, 0x71, 0xe2, 0xd9,
-    0xaf, 0x43, 0x86, 0x11, 0x22, 0x44, 0x88, 0xd, 0x1a, 0x34, 0x68, 0xd0, 0xbd, 0x67, 0xce, 0x81,
-    0x1f, 0x3e, 0x7c, 0xf8, 0xed, 0xc7, 0x93, 0x3b, 0x76, 0xec, 0xc5, 0x97, 0x33, 0x66, 0xcc, 0x85,
-    0x17, 0x2e, 0x5c, 0xb8, 0x6d, 0xda, 0xa9, 0x4f, 0x9e, 0x21, 0x42, 0x84, 0x15, 0x2a, 0x54, 0xa8,
-    0x4d, 0x9a, 0x29, 0x52, 0xa4, 0x55, 0xaa, 0x49, 0x92, 0x39, 0x72, 0xe4, 0xd5, 0xb7, 0x73, 0xe6,
-    0xd1, 0xbf, 0x63, 0xc6, 0x91, 0x3f, 0x7e, 0xfc, 0xe5, 0xd7, 0xb3, 0x7b, 0xf6, 0xf1, 0xff, 0xe3,
-    0xdb, 0xab, 0x4b, 0x96, 0x31, 0x62, 0xc4, 0x95, 0x37, 0x6e, 0xdc, 0xa5, 0x57, 0xae, 0x41, 0x82,
-    0x19, 0x32, 0x64, 0xc8, 0x8d, 0x7, 0xe, 0x1c, 0x38, 0x70, 0xe0, 0xdd, 0xa7, 0x53, 0xa6, 0x51,
-    0xa2, 0x59, 0xb2, 0x79, 0xf2, 0xf9, 0xef, 0xc3, 0x9b, 0x2b, 0x56, 0xac, 0x45, 0x8a, 0x9, 0x12,
-    0x24, 0x48, 0x90, 0x3d, 0x7a, 0xf4, 0xf5, 0xf7, 0xf3, 0xfb, 0xeb, 0xcb, 0x8b, 0xb, 0x16, 0x2c,
-    0x58, 0xb0, 0x7d, 0xfa, 0xe9, 0xcf, 0x83, 0x1b, 0x36, 0x6c, 0xd8, 0xad, 0x47, 0x8e, 0x1, 0x2,
-    0x4, 0x8, 0x10, 0x20, 0x40, 0x80, 0x1d, 0x3a, 0x74, 0xe8, 0xcd, 0x87, 0x13, 0x26, 0x4c, 0x98,
-    0x2d, 0x5a, 0xb4, 0x75, 0xea, 0xc9, 0x8f, 0x3, 0x6, 0xc, 0x18, 0x30, 0x60, 0xc0, 0x9d, 0x27,
-    0x4e, 0x9c, 0x25, 0x4a, 0x94, 0x35, 0x6a, 0xd4, 0xb5, 0x77, 0xee, 0xc1, 0x9f, 0x23, 0x46, 0x8c,
-    0x5, 0xa, 0x14, 0x28, 0x50, 0xa0, 0x5d, 0xba, 0x69, 0xd2, 0xb9, 0x6f, 0xde, 0xa1, 0x5f, 0xbe,
-    0x61, 0xc2, 0x99, 0x2f, 0x5e, 0xbc, 0x65, 0xca, 0x89, 0xf, 0x1e, 0x3c, 0x78, 0xf0, 0xfd, 0xe7,
-    0xd3, 0xbb, 0x6b, 0xd6, 0xb1, 0x7f, 0xfe, 0xe1, 0xdf, 0xa3, 0x5b, 0xb6, 0x71, 0xe2, 0xd9, 0xaf,
-    0x43, 0x86, 0x11, 0x22, 0x44, 0x88, 0xd, 0x1a, 0x34, 0x68, 0xd0, 0xbd, 0x67, 0xce, 0x81, 0x1f,
-    0x3e, 0x7c, 0xf8, 0xed, 0xc7, 0x93, 0x3b, 0x76, 0xec, 0xc5, 0x97, 0x33, 0x66, 0xcc, 0x85, 0x17,
-    0x2e, 0x5c, 0xb8, 0x6d, 0xda, 0xa9, 0x4f, 0x9e, 0x21, 0x42, 0x84, 0x15, 0x2a, 0x54, 0xa8, 0x4d,
-    0x9a, 0x29, 0x52, 0xa4, 0x55, 0xaa, 0x49, 0x92, 0x39, 0x72, 0xe4, 0xd5, 0xb7, 0x73, 0xe6, 0xd1,
-    0xbf, 0x63, 0xc6, 0x91, 0x3f, 0x7e, 0xfc, 0xe5, 0xd7, 0xb3, 0x7b, 0xf6, 0xf1, 0xff, 0xe3, 0xdb,
-    0xab, 0x4b, 0x96, 0x31, 0x62, 0xc4, 0x95, 0x37, 0x6e, 0xdc, 0xa5, 0x57, 0xae, 0x41, 0x82, 0x19,
-    0x32, 0x64, 0xc8, 0x8d, 0x7, 0xe, 0x1c, 0x38, 0x70, 0xe0, 0xdd, 0xa7, 0x53, 0xa6, 0x51, 0xa2,
-    0x59, 0xb2, 0x79, 0xf2, 0xf9, 0xef, 0xc3, 0x9b, 0x2b, 0x56, 0xac, 0x45, 0x8a, 0x9, 0x12, 0x24,
-    0x48, 0x90, 0x3d, 0x7a, 0xf4, 0xf5, 0xf7, 0xf3, 0xfb, 0xeb, 0xcb, 0x8b, 0xb, 0x16, 0x2c, 0x58,
-    0xb0, 0x7d, 0xfa, 0xe9, 0xcf, 0x83, 0x1b, 0x36, 0x6c, 0xd8, 0xad, 0x47, 0x8e, 0x1, 0x2
-};
-
-const uint8_t code_log[256] = {
-    0x0, 0x0, 0x1, 0x19, 0x2, 0x32, 0x1a, 0xc6, 0x3, 0xdf, 0x33, 0xee, 0x1b, 0x68, 0xc7, 0x4b, 0x4,
-    0x64, 0xe0, 0xe, 0x34, 0x8d, 0xef, 0x81, 0x1c, 0xc1, 0x69, 0xf8, 0xc8, 0x8, 0x4c, 0x71, 0x5,
-    0x8a, 0x65, 0x2f, 0xe1, 0x24, 0xf, 0x21, 0x35, 0x93, 0x8e, 0xda, 0xf0, 0x12, 0x82, 0x45, 0x1d,
-    0xb5, 0xc2, 0x7d, 0x6a, 0x27, 0xf9, 0xb9, 0xc9, 0x9a, 0x9, 0x78, 0x4d, 0xe4, 0x72, 0xa6, 0x6,
-    0xbf, 0x8b, 0x62, 0x66, 0xdd, 0x30, 0xfd, 0xe2, 0x98, 0x25, 0xb3, 0x10, 0x91, 0x22, 0x88, 0x36,
-    0xd0, 0x94, 0xce, 0x8f, 0x96, 0xdb, 0xbd, 0xf1, 0xd2, 0x13, 0x5c, 0x83, 0x38, 0x46, 0x40, 0x1e,
-    0x42, 0xb6, 0xa3, 0xc3, 0x48, 0x7e, 0x6e, 0x6b, 0x3a, 0x28, 0x54, 0xfa, 0x85, 0xba, 0x3d, 0xca,
-    0x5e, 0x9b, 0x9f, 0xa, 0x15, 0x79, 0x2b, 0x4e, 0xd4, 0xe5, 0xac, 0x73, 0xf3, 0xa7, 0x57, 0x7,
-    0x70, 0xc0, 0xf7, 0x8c, 0x80, 0x63, 0xd, 0x67, 0x4a, 0xde, 0xed, 0x31, 0xc5, 0xfe, 0x18, 0xe3,
-    0xa5, 0x99, 0x77, 0x26, 0xb8, 0xb4, 0x7c, 0x11, 0x44, 0x92, 0xd9, 0x23, 0x20, 0x89, 0x2e, 0x37,
-    0x3f, 0xd1, 0x5b, 0x95, 0xbc, 0xcf, 0xcd, 0x90, 0x87, 0x97, 0xb2, 0xdc, 0xfc, 0xbe, 0x61, 0xf2,
-    0x56, 0xd3, 0xab, 0x14, 0x2a, 0x5d, 0x9e, 0x84, 0x3c, 0x39, 0x53, 0x47, 0x6d, 0x41, 0xa2, 0x1f,
-    0x2d, 0x43, 0xd8, 0xb7, 0x7b, 0xa4, 0x76, 0xc4, 0x17, 0x49, 0xec, 0x7f, 0xc, 0x6f, 0xf6, 0x6c,
-    0xa1, 0x3b, 0x52, 0x29, 0x9d, 0x55, 0xaa, 0xfb, 0x60, 0x86, 0xb1, 0xbb, 0xcc, 0x3e, 0x5a, 0xcb,
-    0x59, 0x5f, 0xb0, 0x9c, 0xa9, 0xa0, 0x51, 0xb, 0xf5, 0x16, 0xeb, 0x7a, 0x75, 0x2c, 0xd7, 0x4f,
-    0xae, 0xd5, 0xe9, 0xe6, 0xe7, 0xad, 0xe8, 0x74, 0xd6, 0xf4, 0xea, 0xa8, 0x50, 0x58, 0xaf
-};
-
-void poly_init(blpoly_t *dev, uint8_t id, uint16_t offset, uint8_t size, uint8_t *memory_ptr)
-{
-    bl_assert(memory_ptr && dev);
-
-    dev->_id = id;
-    dev->_size = size;
-    dev->_offset = offset;
-    dev->_memory = memory_ptr;
-    dev->length = 0;
-}
-
-uint8_t *poly_ptr(blpoly_t *dev)
-{
-    bl_assert(dev);
-
-    return (dev->_memory + dev->_offset);
-}
-
-void poly_reset(blpoly_t *dev)
-{
-    bl_assert(dev->_memory && dev);
-
-    memset(poly_ptr(dev), 0, dev->_size);
-}
-
-void poly_set(blpoly_t *dev, uint8_t* src, uint8_t len, uint8_t offset)/* offset=0 */
-{
-    bl_assert(src && len <= dev->_size - offset);
-
-    memcpy(poly_ptr(dev)+offset, src, len * sizeof(uint8_t));
-
-    dev->length = len + offset;
-}
-
-uint8_t *poly_at(blpoly_t *dev, uint8_t i)
-{
-    uint8_t *pt;
-
-    bl_assert(dev);
-
-    pt = poly_ptr(dev);
-
-    return (pt + i);
-}
-
-uint8_t poly_get_size(blpoly_t *dev)
-{
-    bl_assert(dev);
-
-    return dev->_size;
-}
-
-uint8_t poly_get_id(blpoly_t *dev)
-{
-    bl_assert(dev);
-
-    return dev->_id;
-}
-
-void poly_copy(blpoly_t *dev, blpoly_t *src)
-{
-    bl_assert(dev && src);
-
-    dev->length = ((dev->length) > (src->length) ? (dev->length) : (src->length));
-    poly_set(dev, poly_ptr(src), dev->length, 0);
-}
-
-uint8_t poly_append(blpoly_t *dev, uint8_t num)
-{
-    uint8_t *pt;
-    bl_assert(dev->length + 1 < dev->_size);
-
-    pt = poly_ptr(dev);
-    pt[dev->length++] = num;
-
-    return 1;/* true */
-}
-
-/*****************************************************/
-uint8_t gf_add(uint8_t x, uint8_t y)
-{
-    return x + y;
-}
-
-uint8_t gf_sub(uint8_t x, uint8_t y)
-{
-    return x^y;
-}
-
-uint8_t gf_mul(uint16_t x, uint16_t y)
-{
-    if (x == 0 || y == 0) {
-        return 0;
-    }
-
-    return code_exp[code_log[x] + code_log[y]];
-}
-
-uint8_t gf_div(uint8_t x, uint8_t y)
-{
-    bl_assert(y != 0);
-
-    if (x == 0) {
-        return 0;
-    }
-    return code_exp[(code_log[x] + 255 - code_log[y]) % 255];
-}
-
-uint8_t gf_pow(uint8_t x, intmax_t power)
-{
-    intmax_t i = code_log[x];
-
-    i *= power;
-    i %= 255;
-
-    if (i < 0) {
-        i = i + 255;
-    }
-
-    return code_exp[i];
-}
-
-uint8_t gf_inverse(uint8_t x)
-{
-    return code_exp[255 - code_log[x]]; /* == div(1, x); */
-}
-
-/* POLYNOMIALS OPERATIONS */
-void poly_scale(blpoly_t *p, blpoly_t *newp, uint16_t x)
-{
-    uint16_t i;
-
-    newp->length = p->length;
-    for (i = 0; i < p->length; i++)
-    {
-        *poly_at(newp, i) = gf_mul(*poly_at(p, i), x);
-    }
-}
-
-void poly_add(blpoly_t *p, blpoly_t *q, blpoly_t *newp)
-{
-    uint8_t i;
-
-    newp->length = ((p->length) > (q->length) ? (p->length) : (q->length));
-    memset(poly_ptr(newp), 0, newp->length * sizeof(uint8_t));
-
-    for (i = 0; i < p->length; i++)
-    {
-        *poly_at(newp, i + newp->length - p->length) = *poly_at(p, i);
-    }
-
-    for (i = 0; i < q->length; i++)
-    {
-        *poly_at(newp, i + newp->length - q->length) ^= *poly_at(q, i);
-    }
-}
-
-void poly_mul(blpoly_t *p, blpoly_t *q, blpoly_t *newp)
-{
-    uint8_t i,j;
-
-    newp->length = p->length + q->length - 1;
-    memset(poly_ptr(newp), 0, newp->length * sizeof(uint8_t));
-    /* Compute the polynomial multiplication (just like the outer product of two vectors,
-     * we multiply each coefficients of p with all coefficients of q) */
-    for (j = 0; j < q->length; j++) {
-        for (i = 0; i < p->length; i++) {
-            *poly_at(newp, i+j) ^= gf_mul(*poly_at(p, i), *poly_at(q, j)); /* == r[i + j] = gf_add(r[i+j], gf_mul(p[i], q[j])) */
-        }
-    }
-}
-
-void poly_div(blpoly_t *p, blpoly_t *q, blpoly_t *newp)
-{
-    uint8_t coef;
-    unsigned long sep;
-    long i;
-
-    if (poly_ptr(p) != poly_ptr(newp)) {
-        memcpy(poly_ptr(newp), poly_ptr(p), p->length*sizeof(uint8_t));
-    }
-
-    newp->length = p->length;
-
-    for (i = 0; i < (p->length-(q->length-1)); i++) {
-        coef = *poly_at(newp, i);
-        if (coef != 0) {
-            for (uint8_t j = 1; j < q->length; j++) {
-                if (*poly_at(q, j) != 0) {
-                    *poly_at(newp, i+j) ^= gf_mul(*poly_at(q, j), coef);
-                }
-            }
-        }
-    }
-
-    sep = p->length-(q->length-1);
-    memmove(poly_ptr(newp), poly_ptr(newp)+sep, (newp->length-sep) * sizeof(uint8_t));
-    newp->length = newp->length-sep;
-}
-
-int8_t poly_eval(blpoly_t *p, uint16_t x)
-{
-    uint8_t y = *poly_at(p, 0);
-
-    for (uint8_t i = 1; i < p->length; i++)
-    {
-        y = gf_mul(y, x) ^ (*poly_at(p, i));
-    }
-    return y;
-}
-
-/*****************************************************/
-void generator_poly(fec_context_t *context)
-{
-    uint8_t i;
-    blpoly_t *gen = context->g_polynoms + ID_GENERATOR;
-    blpoly_t *mulp = context->g_polynoms + ID_TPOLY1;
-    blpoly_t *temp = context->g_polynoms + ID_TPOLY2;
-
-    *poly_at(gen, 0) = 1;
-    gen->length = 1;
-
-    mulp->length = 2;
-
-    for (i = 0; i < FEC_ECC_LENGTH; i++)
-    {
-        *poly_at(mulp, 0) = 1;
-        *poly_at(mulp, 1) = gf_pow(2, i);
-
-        poly_mul(gen, mulp, temp);
-        poly_copy(gen, temp);
-    }
-}
-
-void calc_syndromes(fec_context_t *context, blpoly_t *msg)
-{
-    uint8_t i;
-    blpoly_t *synd = &context->g_polynoms[ID_SYNDROMES];
-
-    synd->length = FEC_ECC_LENGTH + 1;
-    *poly_at(synd, 0) = 0;
-
-    for (i = 1; i < FEC_ECC_LENGTH + 1; i++)
-    {
-        *poly_at(synd, i) = poly_eval(msg, gf_pow(2, i - 1));
-    }
-}
-
-void find_errata_locator(fec_context_t *context, blpoly_t *epos)
-{
-    blpoly_t *errata_loc = &context->g_polynoms[ID_ERASURES_LOC];
-    blpoly_t *mulp = &context->g_polynoms[ID_TPOLY1];
-    blpoly_t *addp = &context->g_polynoms[ID_TPOLY2];
-    blpoly_t *apol = &context->g_polynoms[ID_TPOLY3];
-    blpoly_t *temp = &context->g_polynoms[ID_TPOLY4];
-
-    errata_loc->length = 1;
-    *poly_at(errata_loc, 0) = 1;
-
-    mulp->length = 1;
-    addp->length = 2;
-
-    for (uint8_t i = 0; i < epos->length; i++)
-    {
-        *poly_at(mulp, 0) = 1;
-        *poly_at(addp, 0) = gf_pow(2, *poly_at(epos           , i));
-        *poly_at(addp, 1) = 0;
-
-        poly_add(mulp, addp, apol);
-        poly_mul(errata_loc, apol, temp);
-
-        poly_copy(errata_loc, temp);
-    }
-}
-
-void find_error_evaluator(fec_context_t *context, blpoly_t *synd, blpoly_t *errata_loc, blpoly_t *dst, uint8_t ecclen)
-{
-    blpoly_t *mulp = &context->g_polynoms[ID_TPOLY1];
-    poly_mul(synd, errata_loc, mulp);
-
-    blpoly_t *divisor = &context->g_polynoms[ID_TPOLY2];
-    divisor->length = ecclen + 2;
-
-    poly_reset(divisor);
-    *poly_at(divisor, 0) = 1;
-
-    poly_div(mulp, divisor, dst);
-}
-
-void correct_errata(fec_context_t *context, blpoly_t *synd, blpoly_t *err_pos, blpoly_t *msg_in)
-{
-    uint8_t i;
-    int8_t s_i;
-    int16_t l;
-    uint8_t Xi_inv;
-    uint8_t err_loc_prime;
-    uint8_t y;
-    uint8_t j;
-
-    blpoly_t *c_pos     = &context->g_polynoms[ID_COEF_POS];
-    blpoly_t *corrected = &context->g_polynoms[ID_MSG_OUT];
-    blpoly_t *errata_loc = &context->g_polynoms[ID_ERASURES_LOC];
-    blpoly_t *rsynd = &context->g_polynoms[ID_TPOLY3];
-    blpoly_t *re_eval = &context->g_polynoms[ID_TPOLY4];
-    blpoly_t *e_eval = &context->g_polynoms[ID_ERR_EVAL];
-    blpoly_t *X = &context->g_polynoms[ID_TPOLY1]; /* this will store errors positions */
-    blpoly_t *E = &context->g_polynoms[ID_MSG_E];
-    blpoly_t *err_loc_prime_temp = &context->g_polynoms[ID_TPOLY2];
-
-    c_pos->length = err_pos->length;
-
-    for (i = 0; i < err_pos->length; i++)
-        *poly_at(c_pos, i) = msg_in->length - 1 - *poly_at(err_pos, i);
-
-    /* uses t_poly 1, 2, 3, 4 */
-    find_errata_locator(context, c_pos);
-
-
-    /* reversing syndromes */
-    rsynd->length = synd->length;
-
-    for (s_i = synd->length-1, j = 0; s_i >= 0; s_i--, j++)
-    {
-        *poly_at(rsynd, j) = *poly_at(synd, s_i);
-    }
-
-    /* getting reversed error evaluator polynomial */
-
-    /* uses T_POLY 1, 2 */
-    find_error_evaluator(context, rsynd, errata_loc, re_eval, errata_loc->length-1);
-
-    /* reversing it back */
-    e_eval->length = re_eval->length;
-    for (s_i = re_eval->length-1, j = 0; s_i >= 0; s_i--, j++)
-    {
-        *poly_at(e_eval, j) = *poly_at(re_eval, s_i);
-    }
-
-
-    X->length = 0;
-
-    for (i = 0; i < c_pos->length; i++)
-    {
-        l = 255 - *poly_at(c_pos, i);
-        poly_append(X, gf_pow(2, -l));
-    }
-
-    /* Magnitude polynomial
-        Shit just got real */
-    poly_reset(E);
-    E->length = msg_in->length;
-
-
-    for (i = 0; i < X->length; i++) {
-        Xi_inv = gf_inverse(*poly_at(X, i));
-
-        err_loc_prime_temp->length = 0;
-        for (j = 0; j < X->length; j++) {
-            if (j != i) {
-                poly_append(err_loc_prime_temp, gf_sub(1, gf_mul(Xi_inv, *poly_at(X, j))));
-            }
-        }
-
-        err_loc_prime = 1;
-        for (j = 0; j < err_loc_prime_temp->length; j++) {
-            err_loc_prime = gf_mul(err_loc_prime, *poly_at(err_loc_prime_temp, j));
-        }
-
-        y = poly_eval(re_eval, Xi_inv);
-        y = gf_mul(gf_pow(*poly_at(X, i), 1), y);
-
-        *poly_at(E, *poly_at(err_pos, i)) = gf_div(y, err_loc_prime);
-    }
-
-    poly_add(msg_in, E, corrected);
-}
-
-uint8_t find_error_locator(fec_context_t *context, blpoly_t *synd, blpoly_t *erase_loc, unsigned long erase_count)
-{
-    uint8_t i;
-    uint8_t synd_shift = 0;
-    uint8_t K = 0;
-    uint8_t delta = 0;
-    uint8_t index;
-    uint8_t j;
-    uint32_t shift = 0;
-    uint32_t errs;
-
-    blpoly_t *error_loc = &context->g_polynoms[ID_ERRORS_LOC];
-    blpoly_t *err_loc   = &context->g_polynoms[ID_TPOLY1];
-    blpoly_t *old_loc   = &context->g_polynoms[ID_TPOLY2];
-    blpoly_t *temp      = &context->g_polynoms[ID_TPOLY3];
-    blpoly_t *temp2     = &context->g_polynoms[ID_TPOLY4];
-
-    if (erase_loc != NULL) {
-        poly_copy(err_loc, erase_loc);
-        poly_copy(old_loc, erase_loc);
-    } else {
-        err_loc->length = 1;
-        old_loc->length = 1;
-        *poly_at(err_loc, 0)  = 1;
-        *poly_at(old_loc, 0)  = 1;
-    }
-
-
-    if (synd->length > FEC_ECC_LENGTH) {
-        synd_shift = synd->length - FEC_ECC_LENGTH;
-    }
-
-    for (i = 0; i < FEC_ECC_LENGTH - erase_count; i++)
-    {
-        if (erase_loc != NULL) {
-            K = erase_count + i + synd_shift;
-        } else {
-            K = i + synd_shift;
-        }
-
-        delta = *poly_at(synd, K);
-        for (j = 1; j < err_loc->length; j++) {
-            index = err_loc->length - j - 1;
-            delta ^= gf_mul(*poly_at(err_loc, index), *poly_at(synd, K-j));
-        }
-
-        poly_append(old_loc, 0);
-
-        if (delta != 0) {
-            if (old_loc->length > err_loc->length) {
-                poly_scale(old_loc, temp, delta);
-                poly_scale(err_loc, old_loc, gf_inverse(delta));
-                poly_copy(err_loc, temp);
-            }
-            poly_scale(old_loc, temp, delta);
-            poly_add(err_loc, temp, temp2);
-            poly_copy(err_loc, temp2);
-        }
-    }
-
-    while(err_loc->length && *poly_at(err_loc, shift) == 0) shift++;
-
-    errs = err_loc->length - shift - 1;
-    if (((errs - erase_count) * 2 + erase_count) > FEC_ECC_LENGTH) {
-        return 0;/* false */ /* Error count is greater then we can fix! */
-    }
-
-    memcpy(poly_ptr(error_loc), poly_ptr(err_loc) + shift, (err_loc->length - shift) * sizeof(uint8_t));
-    error_loc->length = (err_loc->length - shift);
-    return 1;/* true */
-}
-
-uint8_t find_errors(fec_context_t *context, blpoly_t *error_loc, unsigned long msg_in_size)
-{
-    uint8_t i;
-
-    blpoly_t *err = &context->g_polynoms[ID_ERRORS];
-    uint8_t errs = error_loc->length - 1;
-
-    err->length = 0;
-
-    for (i = 0; i < msg_in_size; i++)
-    {
-        if (poly_eval(error_loc, gf_pow(2, i)) == 0)
-        {
-            poly_append(err, msg_in_size - 1 - i);
-        }
-    }
-
-    /* Sanity check:
-        * the number of err/errata positions found
-        * should be exactly the same as the length of the errata locator polynomial */
-    if (err->length != errs) {
-        /* couldn't find error locations */
-        return 0;/* false */
-    }
-
-    return 1;/* true */
-}
-
-void calc_forney_syndromes(fec_context_t *context, blpoly_t *synd, blpoly_t *erasures_pos, unsigned long msg_in_size)
-{
-    uint8_t i;
-    uint8_t x;
-    uint8_t j;
-
-    blpoly_t *erase_pos_reversed = &context->g_polynoms[ID_TPOLY1];
-    blpoly_t *forney_synd = &context->g_polynoms[ID_FORNEY];
-
-    erase_pos_reversed->length = 0;
-
-    for (i = 0; i < erasures_pos->length; i++)
-    {
-        poly_append(erase_pos_reversed, msg_in_size - 1 - *poly_at(erasures_pos, i));
-    }
-
-    poly_reset(forney_synd);
-    poly_set(forney_synd, poly_ptr(synd)+1, synd->length-1, 0);
-
-    for (i = 0; i < erasures_pos->length; i++)
-    {
-        x = gf_pow(2, *poly_at(erase_pos_reversed, i));
-        for (j = 0; j < forney_synd->length - 1; j++)
-        {
-            *poly_at(forney_synd, j) = gf_mul(*poly_at(forney_synd, j), x) ^ *poly_at(forney_synd, j+1);
-        }
-    }
-}
-
-void reedsolomon_init(void *context)
-{
-    fec_context_t *p = (fec_context_t *)context;
-    uint16_t offset = 0;
-    uint8_t i;
-    uint8_t enc_len = FEC_MSG_LENGTH + FEC_ECC_LENGTH;
-    uint8_t poly_len = FEC_ECC_LENGTH * 2;
-
-    bl_assert(p);
-
-    log_info("reedsolomon_init.\r\n");
-
-    poly_init(&p->g_polynoms[0], ID_MSG_IN, offset, enc_len, p->g_stack_memory);
-    offset += enc_len;
-
-    poly_init(&p->g_polynoms[1], ID_MSG_OUT, offset, enc_len, p->g_stack_memory);
-    offset += enc_len;
-
-    for (i = ID_GENERATOR; i < ID_MSG_E; i++)
-    {
-        poly_init(&p->g_polynoms[i], i, offset, poly_len, p->g_stack_memory);
-        offset += poly_len;
-    }
-
-    poly_init(&p->g_polynoms[5], ID_MSG_E, offset, enc_len, p->g_stack_memory);
-    offset += enc_len;
-
-    for (i = ID_TPOLY3; i < ID_ERR_EVAL+2; i++)
-    {
-        poly_init(&p->g_polynoms[i], i, offset, poly_len, p->g_stack_memory);
-        offset += poly_len;
-    }
-}
-
-void encode_block(fec_context_t *context, void *src, void *dst)
-{
-    /* Generator cache, it dosn't change for one template parameters */
-
-    uint8_t coef = 0; /* cache */
-    uint8_t i;
-    uint32_t j;
-
-    uint8_t* src_ptr = (uint8_t*) src;
-    uint8_t* dst_ptr = (uint8_t*) dst;
-
-    blpoly_t *msg_in  = &context->g_polynoms[ID_MSG_IN];
-    blpoly_t *msg_out = &context->g_polynoms[ID_MSG_OUT];
-    blpoly_t *gen     = &context->g_polynoms[ID_GENERATOR];
-
-    bl_assert(FEC_MSG_LENGTH + FEC_ECC_LENGTH < 256);
-
-    poly_reset(msg_in);
-    poly_reset(msg_out);
-
-    if (context->g_generator_cached_flag) {
-        poly_set(gen, context->g_generator_cache, (FEC_ECC_LENGTH + 1), 0);
-    } else {
-        generator_poly(context);
-        memcpy(context->g_generator_cache, poly_ptr(gen), gen->length);
-        context->g_generator_cached_flag = 1;/* true */
-    }
-
-    /* Copying input message to internal polynomial */
-    poly_set(msg_in, src_ptr, FEC_MSG_LENGTH, 0);
-    poly_set(msg_out, src_ptr, FEC_MSG_LENGTH, 0);
-    msg_out->length = msg_in->length + FEC_ECC_LENGTH;
-
-    /* Here all the magic happens */
-
-    for (i = 0; i < FEC_MSG_LENGTH; i++) {
-        coef = *poly_at(msg_out, i);
-        if (coef != 0) {
-            for (j = 1; j < gen->length; j++) {
-                *poly_at(msg_out, i+j) ^= gf_mul(*poly_at(gen, j), coef);
-            }
-        }
-    }
-
-    /* Copying ECC to the output buffer */
-    memcpy(dst_ptr, poly_ptr(msg_out)+FEC_MSG_LENGTH, FEC_ECC_LENGTH * sizeof(uint8_t));
-
-}
-
-void reedsolomon_encode(void *context, void* src, void* dst)
-{
-    fec_context_t *p = (fec_context_t *)context;
-    uint8_t* dst_ptr = (uint8_t*) dst;
-
-    /* Copying message to the output buffer */
-    memcpy(dst_ptr, src, FEC_MSG_LENGTH * sizeof(uint8_t));
-
-    /* Calling EncodeBlock to write ecc to out[ut buffer */
-    encode_block(p, src, dst_ptr+FEC_MSG_LENGTH);
-}
-
-char decode_block(fec_context_t *context, void* src, const void* ecc, void* dst, uint8_t* erase_pos, unsigned long erase_count)
-{
-    uint8_t i, j;
-    int8_t s_i;
-    bl_assert(FEC_MSG_LENGTH + FEC_ECC_LENGTH < 256);
-
-    uint8_t *src_ptr = (uint8_t*) src;
-    uint8_t *ecc_ptr = (uint8_t*) ecc;
-    uint8_t *dst_ptr = (uint8_t*) dst;
-
-    uint8_t src_len = FEC_MSG_LENGTH + FEC_ECC_LENGTH;
-    uint8_t dst_len = FEC_MSG_LENGTH;
-
-    uint8_t ok;
-
-    blpoly_t *msg_in  = &context->g_polynoms[ID_MSG_IN];
-    blpoly_t *msg_out = &context->g_polynoms[ID_MSG_OUT];
-    blpoly_t *epos    = &context->g_polynoms[ID_ERASURES];
-    blpoly_t *synd   = &context->g_polynoms[ID_SYNDROMES];
-    blpoly_t *eloc   = &context->g_polynoms[ID_ERRORS_LOC];
-    blpoly_t *reloc  = &context->g_polynoms[ID_TPOLY1];
-    blpoly_t *err    = &context->g_polynoms[ID_ERRORS];
-    blpoly_t *forney = &context->g_polynoms[ID_FORNEY];
-
-    uint8_t has_errors;
-
-    /* Copying message to polynomials memory */
-    poly_set(msg_in, src_ptr, FEC_MSG_LENGTH, 0);
-    poly_set(msg_in, ecc_ptr, FEC_ECC_LENGTH, FEC_MSG_LENGTH);
-    poly_copy(msg_out, msg_in);
-
-    /* Copying known errors to polynomial */
-    if (erase_pos == NULL) {
-        epos->length = 0;
-    } else {
-        poly_set(epos, erase_pos, (uint8_t)erase_count, 0);
-        for (i = 0; i < epos->length; i++){
-            *poly_at(msg_in, *poly_at(epos, i)) = 0;
-        }
-    }
-
-    /* Too many errors */
-    if (epos->length > FEC_ECC_LENGTH) return 1;
-
-
-    /* Calculating syndrome */
-    calc_syndromes(context, msg_in);
-
-    /* Checking for errors */
-    has_errors = 0;/* false */
-    for (i = 0; i < synd->length; i++) {
-        if (*poly_at(synd, i) != 0) {
-            has_errors = 1;/* true */
-            break;
-        }
-    }
-
-    /* Going to exit if no errors */
-    if (!has_errors) {
-        goto return_corrected_msg;
-    }
-
-    calc_forney_syndromes(context, synd, epos, src_len);
-    find_error_locator(context, forney, NULL, epos->length);
-
-    /*
-        Reversing syndrome
-        TODO optimize through special Poly flag
-    */
-    reloc->length = eloc->length;
-
-    for (s_i = eloc->length-1, j = 0; s_i >= 0; s_i--, j++) {
-        *poly_at(reloc, j) = *poly_at(eloc, s_i);
-    }
-
-    /* Fing errors */
-    ok = find_errors(context, reloc, src_len);
-    if (!ok) {
-        return 1;
-    }
-
-    /* Error happened while finding errors (so helpfull :D) */
-    if (err->length == 0) {
-        return 1;
-    }
-
-    /* Adding found errors with known */
-    for (uint8_t i = 0; i < err->length; i++) {
-        poly_append(epos, *poly_at(err, i));
-    }
-
-    /* Correcting errors */
-    correct_errata(context, synd, epos, msg_in);
-
-return_corrected_msg:
-    /* Wrighting corrected message to output buffer */
-    msg_out->length = dst_len;
-    memcpy(dst_ptr, poly_ptr(msg_out), msg_out->length * sizeof(uint8_t));
-    return 0;
-}
-
-/*
-    old:
-        reedsolomon_decode(void *context, void* src, void* dst, uint8_t* erase_pos, uint32_t erase_count)
-        return decode_block(p, src, ecc_ptr, dst, erase_pos, erase_count);
-*/
-char reedsolomon_decode(void *context, void* src, void* dst)
-{
-    fec_context_t *p = (fec_context_t *)context;
-    uint8_t *src_ptr = (uint8_t*) src;
-    uint8_t *ecc_ptr = src_ptr + FEC_MSG_LENGTH;
-
-    return decode_block(p, src, ecc_ptr, dst, 0, 0);
-}
-
-/* which compiles with no warnings, and produces no code. */
-#define BUILD_BUG_ON(condition) ((void)sizeof(char [1 - 2 * !!(condition)]))
-int reedsolomon_getmemsize(void)
-{
-    /*
-        which compiles with no warnings, and produces no code.
-        err ? too waste mem ? pleas set fec_t.dummy size to (sizeof(fec_context_t)/sizeof(int) + 1)!
-    */
-    BUILD_BUG_ON((sizeof(fec_t) - sizeof(fec_context_t) > 512) ||
-                (sizeof(fec_t) - sizeof(fec_context_t) < 0));
-
-    log_info("sizeof(fec_t) = %d   sizeof(fec_context_t) = %d\r\n", sizeof(fec_t), sizeof(fec_context_t));
-    return (int)sizeof(fec_context_t);
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-
-
-
diff --git a/bsp/bl808/m0/libraries/utils/src/utils_getopt.c b/bsp/bl808/m0/libraries/utils/src/utils_getopt.c
deleted file mode 100644
index 7e91ebc703..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/utils_getopt.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include 
-#include 
-
-/*
- * This file is derived from musl v1.2.0.
- * Modifications are applied.
- * Copyright (C) Bouffalo Lab 2016-2020
- */
-
-/*
- * Copyright © 2005-2020 Rich Felker, et al.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-int utils_getopt_init(getopt_env_t *env, int opterr)
-{
-    if (!env) {
-        return -1;
-    }
-    env->optarg = NULL;
-    env->optind = 1;
-    env->opterr = opterr;
-    env->optopt = 0;
-    env->__optpos = 0;
-    return 0;
-}
-
-#define NEWLINE "\r\n"
-
-int utils_getopt(getopt_env_t *env, int argc, char * const argv[], const char *optstring)
-{
-    int i;
-    char c, d;
-    char *optchar;
-
-    if (!env) {
-        return -1;
-    }
-
-    if (env->optind >= argc || !argv[env->optind])
-        return -1;
-
-    if (argv[env->optind][0] != '-') {
-        if (optstring[0] == '-') {
-            env->optarg = argv[env->optind++];
-            return 1;
-        }
-        return -1;
-    }
-
-    if (!argv[env->optind][1])
-        return -1;
-
-    if (argv[env->optind][1] == '-' && !argv[env->optind][2])
-        return env->optind++, -1;
-
-    if (!env->__optpos) env->__optpos++;
-    c = argv[env->optind][env->__optpos];
-    optchar = argv[env->optind] + env->__optpos;
-    env->__optpos += !!c;
-
-    if (!argv[env->optind][env->__optpos]) {
-        env->optind++;
-        env->__optpos = 0;
-    }
-
-    if (optstring[0] == '-' || optstring[0] == '+')
-        optstring++;
-
-    i = 0;
-    do d = optstring[i++]; while (d && d != c);
-
-    if (d != c || c == ':') {
-        env->optopt = c;
-        if (optstring[0] != ':' && env->opterr)
-            printf("%s: unrecognized option: %c"NEWLINE, argv[0], *optchar);
-        return '?';
-    }
-    if (optstring[i] == ':') {
-        env->optarg = 0;
-        if (optstring[i+1] != ':' || env->__optpos) {
-            env->optarg = argv[env->optind++] + env->__optpos;
-            env->__optpos = 0;
-        }
-        if (env->optind > argc) {
-            env->optopt = c;
-            if (optstring[0] == ':') return ':';
-            if (env->opterr) {
-                printf("%s: option requires an argument: %c"NEWLINE, argv[0], *optchar);
-            }
-            return '?';
-        }
-    }
-    return c;
-}
diff --git a/bsp/bl808/m0/libraries/utils/src/utils_hex.c b/bsp/bl808/m0/libraries/utils/src/utils_hex.c
deleted file mode 100644
index e403f9e9a2..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/utils_hex.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include 
-#include 
-#include 
-
-const char hex_asc[] = "0123456789abcdef";
-const char hex_asc_upper[] = "0123456789ABCDEF";
-#define hex_asc_lo(x)   hex_asc_upper[((x) & 0x0f)]
-#define hex_asc_hi(x)   hex_asc_upper[((x) & 0xf0) >> 4]
-
-static inline char *hex_byte_pack(char *buf, uint8_t byte)
-{
-    *buf++ = hex_asc_hi(byte);
-    *buf++ = hex_asc_lo(byte);
-    return buf;
-}
-
-static int char2hex(char c, uint8_t *x)
-{
-    if (c >= '0' && c <= '9') {
-        *x = c - '0';
-    } else if (c >= 'a' && c <= 'f') {
-        *x = c - 'a' + 10;
-    } else if (c >= 'A' && c <= 'F') {
-        *x = c - 'A' + 10;
-    } else {
-        return -1;
-    }
-
-    return 0;
-}
-
-char *utils_bin2hex(char *dst, const void *src, size_t count)
-{
-    const unsigned char *_src = src;
-
-    while (count--) {
-        dst = hex_byte_pack(dst, *_src++);
-    }
-
-    return dst;
-}
-
-size_t utils_hex2bin(const char *hex, size_t hexlen, uint8_t *buf, size_t buflen)
-{
-    uint8_t dec;
-
-    if (buflen < hexlen / 2 + hexlen % 2) {
-        return 0;
-    }
-
-    /* if hexlen is uneven, insert leading zero nibble */
-    if (hexlen % 2) {
-        if (char2hex(hex[0], &dec) < 0) {
-            return 0;
-        }
-        buf[0] = dec;
-        hex++;
-        buf++;
-    }
-
-    /* regular hex conversion */
-    for (size_t i = 0; i < hexlen / 2; i++) {
-        if (char2hex(hex[2 * i], &dec) < 0) {
-            return 0;
-        }
-        buf[i] = dec << 4;
-
-        if (char2hex(hex[2 * i + 1], &dec) < 0) {
-            return 0;
-        }
-        buf[i] += dec;
-    }
-
-    return hexlen / 2 + hexlen % 2;
-}
diff --git a/bsp/bl808/m0/libraries/utils/src/utils_hexdump.c b/bsp/bl808/m0/libraries/utils/src/utils_hexdump.c
deleted file mode 100644
index 0320fbe04b..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/utils_hexdump.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include 
-#include 
-
-#include 
-
-#ifndef HEXDUMP_COLS
-#define HEXDUMP_COLS 16
-#endif
-//FIXME fix putchar
-extern int bl_putchar(int c);
-
-void utils_hexdump(void *mem, unsigned int len)
-{
-    unsigned int i, j;
-
-    for (i = 0; i < len + ((len % HEXDUMP_COLS) ? (HEXDUMP_COLS - len % HEXDUMP_COLS) : 0); i++) {
-        /* print offset */
-        if (i % HEXDUMP_COLS == 0) {
-            printf("0x%06x: ", i);
-        }
-
-        /* print hex data */
-        if (i < len) {
-            printf("%02x ", 0xFF & ((char*)mem)[i]);
-        } else {
-            /* end of block, just aligning for ASCII dump */
-            printf("   ");
-        }
-
-        /* print ASCII dump */
-        if (i % HEXDUMP_COLS == (HEXDUMP_COLS - 1)) {
-            for (j = i - (HEXDUMP_COLS - 1); j <= i; j++) {
-                if (j >= len) {
-                    /* end of block, not really printing */
-                    bl_putchar(' ');
-                } else if(isprint((int)((char*)mem)[j])) {
-                    /* printable char */
-                    bl_putchar(0xFF & ((char*)mem)[j]);
-                } else {
-                    /* other char */
-                    bl_putchar('.');
-                }
-            }
-            puts("\r\n");
-        }
-    }
-}
-
diff --git a/bsp/bl808/m0/libraries/utils/src/utils_hmac.c b/bsp/bl808/m0/libraries/utils/src/utils_hmac.c
deleted file mode 100644
index ce763397aa..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/utils_hmac.c
+++ /dev/null
@@ -1,239 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include 
-#include "iotx_utils_internal.h"
-#include "utils_md5.h"
-#include "utils_sha1.h"
-#include "utils_sha256.h"
-#include "utils_hmac.h"
-#include "utils_base64.h"
-
-#ifdef UTILS_MD5
-void utils_hmac_md5(const char *msg, int msg_len, char *digest, const char *key, int key_len)
-{
-    if ((NULL == msg) || (NULL == digest) || (NULL == key)) {
-        utils_err("parameter is Null,failed!");
-        return;
-    }
-
-    if (key_len > KEY_IOPAD_SIZE) {
-        utils_err("key_len > size(%d) of array", KEY_IOPAD_SIZE);
-        return;
-    }
-
-    iot_md5_context context;
-    unsigned char k_ipad[KEY_IOPAD_SIZE];    /* inner padding - key XORd with ipad  */
-    unsigned char k_opad[KEY_IOPAD_SIZE];    /* outer padding - key XORd with opad */
-    unsigned char out[MD5_DIGEST_SIZE];
-    int i;
-
-    /* start out by storing key in pads */
-    memset(k_ipad, 0, sizeof(k_ipad));
-    memset(k_opad, 0, sizeof(k_opad));
-    memcpy(k_ipad, key, key_len);
-    memcpy(k_opad, key, key_len);
-
-    /* XOR key with ipad and opad values */
-    for (i = 0; i < KEY_IOPAD_SIZE; i++) {
-        k_ipad[i] ^= 0x36;
-        k_opad[i] ^= 0x5c;
-    }
-
-    /* perform inner MD5 */
-    utils_md5_init(&context);                                      /* init context for 1st pass */
-    utils_md5_starts(&context);                                    /* setup context for 1st pass */
-    utils_md5_update(&context, k_ipad, KEY_IOPAD_SIZE);            /* start with inner pad */
-    utils_md5_update(&context, (unsigned char *) msg, msg_len);    /* then text of datagram */
-    utils_md5_finish(&context, out);                               /* finish up 1st pass */
-
-    /* perform outer MD5 */
-    utils_md5_init(&context);                              /* init context for 2nd pass */
-    utils_md5_starts(&context);                            /* setup context for 2nd pass */
-    utils_md5_update(&context, k_opad, KEY_IOPAD_SIZE);    /* start with outer pad */
-    utils_md5_update(&context, out, MD5_DIGEST_SIZE);      /* then results of 1st hash */
-    utils_md5_finish(&context, out);                       /* finish up 2nd pass */
-
-    for (i = 0; i < MD5_DIGEST_SIZE; ++i) {
-        digest[i * 2] = utils_hb2hex(out[i] >> 4);
-        digest[i * 2 + 1] = utils_hb2hex(out[i]);
-    }
-}
-#endif  /* #ifdef UTILS_MD5 */
-
-#ifdef UTILS_SHA256
-void utils_hmac_sha256(const char *msg, int msg_len, char *digest, const char *key, int key_len)
-{
-    if ((NULL == msg) || (NULL == digest) || (NULL == key)) {
-        utils_err("parameter is Null,failed!");
-        return;
-    }
-
-    if (key_len > KEY_IOPAD_SIZE) {
-        utils_err("key_len > size(%d) of array", KEY_IOPAD_SIZE);
-        return;
-    }
-
-    iot_sha256_context context;
-    unsigned char k_ipad[KEY_IOPAD_SIZE];    /* inner padding - key XORd with ipad  */
-    unsigned char k_opad[KEY_IOPAD_SIZE];    /* outer padding - key XORd with opad */
-    unsigned char out[SHA256_DIGEST_SIZE];
-    int i;
-
-    /* start out by storing key in pads */
-    memset(k_ipad, 0, sizeof(k_ipad));
-    memset(k_opad, 0, sizeof(k_opad));
-    memcpy(k_ipad, key, key_len);
-    memcpy(k_opad, key, key_len);
-
-    /* XOR key with ipad and opad values */
-    for (i = 0; i < KEY_IOPAD_SIZE; i++) {
-        k_ipad[i] ^= 0x36;
-        k_opad[i] ^= 0x5c;
-    }
-
-    /* perform inner SHA */
-    utils_sha256_init(&context);                                      /* init context for 1st pass */
-    utils_sha256_starts(&context);                                    /* setup context for 1st pass */
-    utils_sha256_update(&context, k_ipad, KEY_IOPAD_SIZE);            /* start with inner pad */
-    utils_sha256_update(&context, (unsigned char *) msg, msg_len);    /* then text of datagram */
-    utils_sha256_finish(&context, out);                               /* finish up 1st pass */
-
-    /* perform outer SHA */
-    utils_sha256_init(&context);                              /* init context for 2nd pass */
-    utils_sha256_starts(&context);                            /* setup context for 2nd pass */
-    utils_sha256_update(&context, k_opad, KEY_IOPAD_SIZE);    /* start with outer pad */
-    utils_sha256_update(&context, out, SHA256_DIGEST_SIZE);     /* then results of 1st hash */
-    utils_sha256_finish(&context, out);                       /* finish up 2nd pass */
-
-    for (i = 0; i < SHA256_DIGEST_SIZE; ++i) {
-        digest[i * 2] = utils_hb2hex(out[i] >> 4);
-        digest[i * 2 + 1] = utils_hb2hex(out[i]);
-    }
-}
-#endif /* #ifdef UTILS_SHA256 */
-
-#ifdef UTILS_SHA1
-void utils_hmac_sha1(const char *msg, int msg_len, char *digest, const char *key, int key_len)
-{
-    if ((NULL == msg) || (NULL == digest) || (NULL == key)) {
-        utils_err("parameter is Null,failed!");
-        return;
-    }
-
-    if (key_len > KEY_IOPAD_SIZE) {
-        utils_err("key_len > size(%d) of array", KEY_IOPAD_SIZE);
-        return;
-    }
-
-    iot_sha1_context context;
-    unsigned char k_ipad[KEY_IOPAD_SIZE];    /* inner padding - key XORd with ipad  */
-    unsigned char k_opad[KEY_IOPAD_SIZE];    /* outer padding - key XORd with opad */
-    unsigned char out[SHA1_DIGEST_SIZE];
-    int i;
-
-    /* start out by storing key in pads */
-    memset(k_ipad, 0, sizeof(k_ipad));
-    memset(k_opad, 0, sizeof(k_opad));
-    memcpy(k_ipad, key, key_len);
-    memcpy(k_opad, key, key_len);
-
-    /* XOR key with ipad and opad values */
-    for (i = 0; i < KEY_IOPAD_SIZE; i++) {
-        k_ipad[i] ^= 0x36;
-        k_opad[i] ^= 0x5c;
-    }
-
-    /* perform inner SHA */
-    utils_sha1_init(&context);                                      /* init context for 1st pass */
-    utils_sha1_starts(&context);                                    /* setup context for 1st pass */
-    utils_sha1_update(&context, k_ipad, KEY_IOPAD_SIZE);            /* start with inner pad */
-    utils_sha1_update(&context, (unsigned char *) msg, msg_len);    /* then text of datagram */
-    utils_sha1_finish(&context, out);                               /* finish up 1st pass */
-
-    /* perform outer SHA */
-    utils_sha1_init(&context);                              /* init context for 2nd pass */
-    utils_sha1_starts(&context);                            /* setup context for 2nd pass */
-    utils_sha1_update(&context, k_opad, KEY_IOPAD_SIZE);    /* start with outer pad */
-    utils_sha1_update(&context, out, SHA1_DIGEST_SIZE);     /* then results of 1st hash */
-    utils_sha1_finish(&context, out);                       /* finish up 2nd pass */
-
-    for (i = 0; i < SHA1_DIGEST_SIZE; ++i) {
-        digest[i * 2] = utils_hb2hex(out[i] >> 4);
-        digest[i * 2 + 1] = utils_hb2hex(out[i]);
-    }
-}
-
-void utils_hmac_sha1_hex(const char *msg, int msg_len, char *digest, const char *key, int key_len)
-{
-    if ((NULL == msg) || (NULL == digest) || (NULL == key)) {
-        utils_err("parameter is Null,failed!");
-        return;
-    }
-
-    if (key_len > KEY_IOPAD_SIZE) {
-        utils_err("key_len > size(%d) of array", KEY_IOPAD_SIZE);
-        return;
-    }
-
-    iot_sha1_context context;
-    unsigned char k_ipad[KEY_IOPAD_SIZE];    /* inner padding - key XORd with ipad  */
-    unsigned char k_opad[KEY_IOPAD_SIZE];    /* outer padding - key XORd with opad */
-    unsigned char out[SHA1_DIGEST_SIZE];
-    int i;
-
-    /* start out by storing key in pads */
-    memset(k_ipad, 0, sizeof(k_ipad));
-    memset(k_opad, 0, sizeof(k_opad));
-    memcpy(k_ipad, key, key_len);
-    memcpy(k_opad, key, key_len);
-
-    /* XOR key with ipad and opad values */
-    for (i = 0; i < KEY_IOPAD_SIZE; i++) {
-        k_ipad[i] ^= 0x36;
-        k_opad[i] ^= 0x5c;
-    }
-
-    /* perform inner SHA */
-    utils_sha1_init(&context);                                      /* init context for 1st pass */
-    utils_sha1_starts(&context);                                    /* setup context for 1st pass */
-    utils_sha1_update(&context, k_ipad, KEY_IOPAD_SIZE);            /* start with inner pad */
-    utils_sha1_update(&context, (unsigned char *) msg, msg_len);    /* then text of datagram */
-    utils_sha1_finish(&context, out);                               /* finish up 1st pass */
-
-    /* perform outer SHA */
-    utils_sha1_init(&context);                              /* init context for 2nd pass */
-    utils_sha1_starts(&context);                            /* setup context for 2nd pass */
-    utils_sha1_update(&context, k_opad, KEY_IOPAD_SIZE);    /* start with outer pad */
-    utils_sha1_update(&context, out, SHA1_DIGEST_SIZE);     /* then results of 1st hash */
-    utils_sha1_finish(&context, out);                       /* finish up 2nd pass */
-    memcpy(digest, out, SHA1_DIGEST_SIZE);
-}
-#endif  /* #ifdef UTILS_SHA1 */
diff --git a/bsp/bl808/m0/libraries/utils/src/utils_hmac_sha1_fast.c b/bsp/bl808/m0/libraries/utils/src/utils_hmac_sha1_fast.c
deleted file mode 100644
index 4e24d6485a..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/utils_hmac_sha1_fast.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include 
-#include 
-
-#include 
-#include 
-
-
-void utils_hmac_sha1_fast(unsigned char ** ppText,
-                    int * pTextLen,
-                    int textNum,
-                    unsigned char *key,
-                    int key_len,
-                    unsigned char *output,
-                    int outputLen)
-{
-    uint64_t pBuf[(64 + 20) / 8 + 1]; /*BIG stack*/
-    bl_sha_ctx_t sha_ctx;
-    unsigned char *k_pad; /* padding - key XORd with i/opad */
-    unsigned char *digest;
-    int i;
-
-    /* k_pad start at a UINT32 boundary */
-    k_pad = (unsigned char *)pBuf;
-    digest = k_pad + 64;
-
-    /* if key is longer than 64 bytes reset it to key=SHA1(key) */
-    if (key_len > 64)
-    {
-        bl_sha_init(&sha_ctx, BL_SHA1);
-        bl_sha_update(&sha_ctx, key, key_len);
-        bl_sha_finish(&sha_ctx, key);
-
-        key_len = 20;
-    }
-
-    /*
-     * the HMAC_SHA1 transform looks like:
-     *
-     * SHA1(K XOR opad, SHA1(K XOR ipad, text))
-     *
-     * where K is an n byte key
-     * ipad is the byte 0x36 repeated 64 times
-     * opad is the byte 0x5c repeated 64 times
-     * and text is the data being protected
-     */
-
-    /* perform inner SHA1*/
-    /* start out by storing key in pads */
-    memset(k_pad, 0, 64);
-    memcpy(k_pad, key, key_len);
-
-    /* XOR key with ipad and opad values */
-    for (i = 0; i < 8; i++)
-    {
-        ((uint64_t *)k_pad)[i] ^= 0x3636363636363636;
-    }
-
-    bl_sha_init(&sha_ctx, BL_SHA1); /* init context for 1st pass */
-    bl_sha_update(&sha_ctx, k_pad, 64); /* start with inner pad */
-    for (i = 0; i < textNum; i++)
-    {
-        /* then text of datagram */
-        bl_sha_update(&sha_ctx, ppText[i], pTextLen[i]);
-    }
-
-    bl_sha_finish(&sha_ctx, digest); /* finish up 1st pass */
-
-    /* perform outer SHA1 */
-    /* start out by storing key in pads */
-    memset(k_pad, 0, 64);
-    memcpy(k_pad, key, key_len);
-
-    /* XOR key with ipad and opad values */
-    for (i = 0; i < 8; i++)
-    {
-        ((uint64_t *)k_pad)[i] ^= 0x5c5c5c5c5c5c5c5c;
-    }
-
-    bl_sha_init(&sha_ctx, BL_SHA1); /* init context for 2nd pass */
-    bl_sha_update(&sha_ctx, k_pad, 64); /* start with outer pad */
-    bl_sha_update(&sha_ctx, digest, 20); /* then results of 1st hash */
-    bl_sha_finish(&sha_ctx, digest); /* finish up 2nd pass */
-    memcpy(output, digest, outputLen);
-}
diff --git a/bsp/bl808/m0/libraries/utils/src/utils_list.c b/bsp/bl808/m0/libraries/utils/src/utils_list.c
deleted file mode 100644
index 59c6d3a0a2..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/utils_list.c
+++ /dev/null
@@ -1,365 +0,0 @@
-
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-
-#include 
-#include 
-#include 
-
-void utils_list_init(struct utils_list *list)
-{
-    list->first = NULL;
-    list->last = NULL;
-}
-
-void utils_list_pool_init(struct utils_list *list, void *pool, size_t elmt_size, unsigned int elmt_cnt, void *default_value)
-{
-    unsigned int i;
-
-    // initialize the free list relative to the pool
-    utils_list_init(list);
-
-    // Add each element of the pool to this list, and init them one by one
-    for (i = 0; i < elmt_cnt; i++) {
-        if (default_value)
-        {
-            memcpy(pool, default_value, elmt_size);
-        }
-        utils_list_push_back(list, (struct utils_list_hdr *) pool);
-
-        // move to the next pool element
-        pool = (void *)((uint8_t *)pool + (unsigned int)elmt_size);
-    }
-}
-
-void utils_list_push_back(struct utils_list *list, struct utils_list_hdr *list_hdr)
-{
-    // Sanity check
-    // FIXME assert error here
-    //ASSERT_ERR(list_hdr != NULL);
-
-    // check if list is empty
-    if (utils_list_is_empty(list))
-    {
-        // list empty => pushed element is also head
-        list->first = list_hdr;
-    }
-    else
-    {
-        // list not empty => update next of last
-        list->last->next = list_hdr;
-    }
-
-    // add element at the end of the list
-    list->last = list_hdr;
-    list_hdr->next = NULL;
-}
-
-void utils_list_push_front(struct utils_list *list, struct utils_list_hdr *list_hdr)
-{
-    // Sanity check
-    // FIXME assert error here
-    //ASSERT_ERR(list_hdr != NULL);
-
-    // check if list is empty
-    if (utils_list_is_empty(list))
-    {
-        // list empty => pushed element is also head
-        list->last = list_hdr;
-    }
-
-    // add element at the beginning of the list
-    list_hdr->next = list->first;
-    list->first = list_hdr;
-}
-
-struct utils_list_hdr *utils_list_pop_front(struct utils_list *list)
-{
-    struct utils_list_hdr *element;
-
-    // check if list is empty
-    element = list->first;
-    if (element != NULL)
-    {
-        // The list isn't empty : extract the first element
-        list->first = list->first->next;
-    }
-
-    return element;
-}
-
-void utils_list_extract(struct utils_list *list, struct utils_list_hdr *list_hdr)
-{
-    struct utils_list_hdr *scan_list;
-
-    // sanity check
-    // FIXME assert error here
-    //ASSERT_ERR(list != NULL);
-
-    scan_list = list->first;
-
-    // Check if list is empty or not
-    if (scan_list == NULL)
-        return;
-
-    // check if searched element is first
-    if (scan_list == list_hdr)
-    {
-        // Extract first element
-        list->first = scan_list->next;
-    }
-    else
-    {
-        // Look for the element in the list
-        while ((scan_list->next != NULL) && (scan_list->next != list_hdr))
-        {
-            scan_list = scan_list->next;
-        }
-
-        // Check if element was found in the list
-        if (scan_list->next != NULL)
-        {
-            // check if the removed element is the last in the list
-            if (list->last == list_hdr)
-            {
-                // Last element will be extracted
-                list->last = scan_list;
-            }
-            // Extract the element from the list
-            scan_list->next = list_hdr->next;
-        }
-    }
-}
-
-int utils_list_find(struct utils_list *list, struct utils_list_hdr *list_hdr)
-{
-    struct utils_list_hdr *tmp_list_hdr;
-
-    // Go through the list to find the element
-    tmp_list_hdr = list->first;
-    while((tmp_list_hdr != list_hdr) && (tmp_list_hdr != NULL))
-    {
-        tmp_list_hdr = tmp_list_hdr->next;
-    }
-
-    return (tmp_list_hdr == list_hdr);
-}
-
-unsigned int utils_list_cnt(const struct utils_list *const list)
-{
-    unsigned int cnt = 0;
-    struct utils_list_hdr *elt = utils_list_pick(list);
-
-    // Go through the list to count the number of elements
-    while (elt != NULL)
-    {
-        cnt++;
-        elt = utils_list_next(elt);
-    }
-
-    return(cnt);
-}
-
-/**
- ****************************************************************************************
- * @brief Insert an element in a sorted list.
- *
- * This primitive use a comparison function from the parameter list to select where the
- * element must be inserted.
- *
- * @param[in]  list     Pointer to the list.
- * @param[in]  element  Pointer to the element to insert.
- * @param[in]  cmp      Comparison function (return true if first element has to be inserted
- *                      before the second one).
- *
- * @return              Pointer to the element found and removed (NULL otherwise).
- ****************************************************************************************
- */
-void utils_list_insert(struct utils_list * const list, struct utils_list_hdr * const element,
-                    int (*cmp)(struct utils_list_hdr const *elementA, struct utils_list_hdr const *elementB))
-{
-    struct utils_list_hdr *prev = NULL;
-    struct utils_list_hdr *scan = list->first;
-
-    for(;;)
-    {
-        // scan the list until the end or cmp() returns true
-        if (scan)
-        {
-            if (cmp(element, scan))
-            {
-                // insert now
-                break;
-            }
-            prev = scan;
-            scan = scan->next;
-        }
-        else
-        {
-            // end of list
-            list->last = element;
-            break;
-        }
-    }
-
-    element->next = scan;
-
-    if (prev)
-    {
-        // second or more
-        prev->next = element;
-    }
-    else
-    {
-        // first message
-        list->first = element;
-    }
-}
-
-void utils_list_insert_after(struct utils_list * const list, struct utils_list_hdr * const prev_element, struct utils_list_hdr * const element)
-{
-    struct utils_list_hdr *scan = list->first;
-
-    if (prev_element == NULL)
-    {
-        // Insert the element in front on the list
-        utils_list_push_front(list, element);
-    }
-    else
-    {
-        // Look for prev_element in the list
-        while (scan)
-        {
-            if (scan == prev_element)
-            {
-                break;
-            }
-
-            // Get next element
-            scan = scan->next;
-        }
-
-        // If prev_element has been found, insert element
-        if (scan)
-        {
-            element->next = prev_element->next;
-            prev_element->next = element;
-
-            if (element->next == NULL)
-            {
-                list->last = element;
-            }
-        }
-    }
-}
-
-void utils_list_insert_before(struct utils_list * const list, struct utils_list_hdr * const next_element, struct utils_list_hdr * const element)
-{
-    if (next_element == NULL)
-    {
-        // Insert the element at the end of the list
-        utils_list_push_back(list, element);
-    }
-    else if (next_element == list->first)
-    {
-        // Insert the element in front of the list
-        utils_list_push_front(list, element);
-    }
-    else
-    {
-        struct utils_list_hdr *scan = list->first;
-
-        // Look for next_element in the list
-        while (scan)
-        {
-            if (scan->next == next_element)
-            {
-                break;
-            }
-
-            // Get next element
-            scan = scan->next;
-        }
-
-        // Insert element after scan
-        if (scan)
-        {
-            element->next = next_element;
-            scan->next = element;
-        }
-    }
-}
-
-void utils_list_concat(struct utils_list *list1, struct utils_list *list2)
-{
-    // If list2 is empty, don't do anything
-    if (list2->first != NULL)
-    {
-        // Check if list1 is empty
-        if (list1->first == NULL)
-        {
-            // If list1 is empty, list1 becomes list2
-            *list1 = *list2;
-        }
-        else
-        {
-            // Otherwise, append list2 to list1
-            list1->last->next = list2->first;
-            list1->last = list2->last;
-        }
-        // Clear list2
-        list2->first = NULL;
-    }
-}
-
-
-void utils_list_remove(struct utils_list *list, struct utils_list_hdr *prev_element, struct utils_list_hdr *element)
-{
-    // sanity check
-    // FIXME assert error here
-    //ASSERT_ERR(list != NULL);
-    //ASSERT_ERR((prev_element == NULL) || (prev_element->next == element));
-    //ASSERT_ERR(element != NULL);
-
-
-    if (prev_element == NULL)
-    {
-        list->first = element->next;
-    }
-    else
-    {
-        prev_element->next = element->next;
-        if (list->last == element)
-            list->last = prev_element;
-    }
-
-    element->next = NULL;
-}
diff --git a/bsp/bl808/m0/libraries/utils/src/utils_log.c b/bsp/bl808/m0/libraries/utils/src/utils_log.c
deleted file mode 100644
index 73fbeec762..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/utils_log.c
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include 
-#include 
-#include 
-
-#include "utils_log.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define ONE_LINE_MAX_NUM        (50)/* for print_buf log length */
-#define MODULE_LOG_LOCK_LOCK    /* reserved */
-#define MODULE_LOG_LOCK_UNLOCK  /* reserved */
-static char log_buf[512];
-int log_buf_out(const char *file, int line, const void *inbuf, int len, LOG_BUF_OUT_DATA_TYPE_T type)
-{
-    char *buf = (char *)inbuf;
-    char *pbuffer = NULL;
-
-#if defined(BL702) || defined(BL702L)
-    pbuffer = (char *)pvPortMalloc(sizeof(log_buf));
-    if(pbuffer == NULL){
-        return -1;
-    }
-#else
-    pbuffer = (char *)log_buf;
-#endif
-    int m = 0, n = 0;
-    int j = 0, k = 0, tmp = 0;
-
-    MODULE_LOG_LOCK_LOCK;
-
-    tmp = (sizeof(log_buf))/3;/* 数组最大长度 */
-    if ((ONE_LINE_MAX_NUM > tmp) || (len < 1))
-    {
-        MODULE_LOG_LOCK_UNLOCK;
-        return -1;
-    }
-
-    m = len / ONE_LINE_MAX_NUM;
-    n = len % ONE_LINE_MAX_NUM;
-    if (n > 0) {
-        m++;
-    }
-
-
-    if (n > 0) {
-        /* 非整数倍 */
-        for (k = 0; k < m; k++) {
-            if ((k+1) == m) {
-                /* 最后一帧数据 */
-                tmp = 0;
-                for (j = 0; j < n; j++) {
-                    switch (type) {
-                        case LOG_BUF_OUT_DATA_TYPE_INT8:
-                        {
-                            tmp += sprintf(pbuffer + tmp, "%3d ", (int8_t)buf[k*ONE_LINE_MAX_NUM+j]);
-                        }
-                        break;
-                        case LOG_BUF_OUT_DATA_TYPE_UNT8:
-                        {
-                            tmp += sprintf(pbuffer + tmp, "%3u ", (uint8_t)buf[k*ONE_LINE_MAX_NUM+j]);
-                        }
-                        break;
-                        case LOG_BUF_OUT_DATA_TYPE_HEX:
-                        default:
-                        {
-                            tmp += sprintf(pbuffer + tmp, "%02x ", (uint8_t)buf[k*ONE_LINE_MAX_NUM+j]);
-                        }
-                    }
-                }
-                log_buf_pri(file, line, "%.*s\r\n", tmp, pbuffer);
-            } else {
-                tmp = 0;
-                for (j = 0; j < ONE_LINE_MAX_NUM; j++) {
-                    switch (type) {
-                        case LOG_BUF_OUT_DATA_TYPE_INT8:
-                        {
-                            tmp += sprintf(pbuffer + tmp, "%3d ", (int8_t)buf[k*ONE_LINE_MAX_NUM+j]);
-                        }
-                        break;
-                        case LOG_BUF_OUT_DATA_TYPE_UNT8:
-                        {
-                            tmp += sprintf(pbuffer + tmp, "%3u ", (uint8_t)buf[k*ONE_LINE_MAX_NUM+j]);
-                        }
-                        break;
-                        case LOG_BUF_OUT_DATA_TYPE_HEX:
-                        default:
-                        {
-                            tmp += sprintf(pbuffer + tmp, "%02x ", (uint8_t)buf[k*ONE_LINE_MAX_NUM+j]);
-                        }
-                    }
-                }
-                log_buf_pri(file, line, "%.*s\r\n", tmp, pbuffer);
-            }
-        }
-    } else {
-        /* 整数倍 */
-        for (k = 0; k < m; k++) {
-            tmp = 0;
-            for (j = 0; j < ONE_LINE_MAX_NUM; j++) {
-                switch (type) {
-                    case LOG_BUF_OUT_DATA_TYPE_INT8:
-                    {
-                        tmp += sprintf(pbuffer + tmp, "%3d ", (int8_t)buf[k*ONE_LINE_MAX_NUM+j]);
-                    }
-                    break;
-                    case LOG_BUF_OUT_DATA_TYPE_UNT8:
-                    {
-                        tmp += sprintf(pbuffer + tmp, "%3u ", (uint8_t)buf[k*ONE_LINE_MAX_NUM+j]);
-                    }
-                    break;
-                    case LOG_BUF_OUT_DATA_TYPE_HEX:
-                    default:
-                    {
-                        tmp += sprintf(pbuffer + tmp, "%02x ", (uint8_t)buf[k*ONE_LINE_MAX_NUM+j]);
-                    }
-                }
-            }
-            log_buf_pri(file, line, "%.*s\r\n", tmp, pbuffer);
-        }
-    }
-
-    MODULE_LOG_LOCK_UNLOCK;
-
-#if defined(BL702) || defined(BL702L)
-    vPortFree(pbuffer);
-#endif
-
-    return 0;
-}
-
-extern void vprint(const char *fmt, va_list argp);
-
-extern volatile bool sys_log_all_enable;
-
-void bl_printk(const char *format, ...)
-{
-    va_list args;
-
-    if (sys_log_all_enable) {
-        /* args point to the first variable parameter */
-        va_start(args, format);
-
-        /* You can add your code under here. */
-        vprint(format, args);
-
-        va_end(args);
-    }
-}
-
-#ifdef __cplusplus
-}
-#endif
-
diff --git a/bsp/bl808/m0/libraries/utils/src/utils_md5.c b/bsp/bl808/m0/libraries/utils/src/utils_md5.c
deleted file mode 100644
index a5dd329265..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/utils_md5.c
+++ /dev/null
@@ -1,324 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifdef UTILS_MD5
-
-
-#include 
-#include 
-#include "iot_import.h"
-#include "iot_export.h"
-#include "iotx_log.h"
-#include "utils_md5.h"
-
-#define MD5_DIGEST_SIZE 16
-
-
-/* Implementation that should never be optimized out by the compiler */
-static void utils_md5_zeroize(void *v, size_t n)
-{
-    volatile unsigned char *p = v;
-    while (n--) {
-        *p++ = 0;
-    }
-}
-
-/*
- * 32-bit integer manipulation macros (little endian)
- */
-#ifndef IOT_MD5_GET_UINT32_LE
-#define IOT_MD5_GET_UINT32_LE(n,b,i)                            \
-    {                                                       \
-        (n) = ( (uint32_t) (b)[(i)    ]       )             \
-              | ( (uint32_t) (b)[(i) + 1] <<  8 )             \
-              | ( (uint32_t) (b)[(i) + 2] << 16 )             \
-              | ( (uint32_t) (b)[(i) + 3] << 24 );            \
-    }
-#endif
-
-#ifndef IOT_MD5_PUT_UINT32_LE
-#define IOT_MD5_PUT_UINT32_LE(n,b,i)                                    \
-    {                                                               \
-        (b)[(i)    ] = (unsigned char) ( ( (n)       ) & 0xFF );    \
-        (b)[(i) + 1] = (unsigned char) ( ( (n) >>  8 ) & 0xFF );    \
-        (b)[(i) + 2] = (unsigned char) ( ( (n) >> 16 ) & 0xFF );    \
-        (b)[(i) + 3] = (unsigned char) ( ( (n) >> 24 ) & 0xFF );    \
-    }
-#endif
-
-void utils_md5_init(iot_md5_context *ctx)
-{
-    memset(ctx, 0, sizeof(iot_md5_context));
-}
-
-void utils_md5_free(iot_md5_context *ctx)
-{
-    if (ctx == NULL) {
-        return;
-    }
-
-    utils_md5_zeroize(ctx, sizeof(iot_md5_context));
-}
-
-void utils_md5_clone(iot_md5_context *dst,
-                     const iot_md5_context *src)
-{
-    *dst = *src;
-}
-
-/*
- * MD5 context setup
- */
-void utils_md5_starts(iot_md5_context *ctx)
-{
-    ctx->total[0] = 0;
-    ctx->total[1] = 0;
-
-    ctx->state[0] = 0x67452301;
-    ctx->state[1] = 0xEFCDAB89;
-    ctx->state[2] = 0x98BADCFE;
-    ctx->state[3] = 0x10325476;
-}
-
-void utils_md5_process(iot_md5_context *ctx, const unsigned char data[64])
-{
-    uint32_t X[16], A, B, C, D;
-
-    IOT_MD5_GET_UINT32_LE(X[ 0], data,  0);
-    IOT_MD5_GET_UINT32_LE(X[ 1], data,  4);
-    IOT_MD5_GET_UINT32_LE(X[ 2], data,  8);
-    IOT_MD5_GET_UINT32_LE(X[ 3], data, 12);
-    IOT_MD5_GET_UINT32_LE(X[ 4], data, 16);
-    IOT_MD5_GET_UINT32_LE(X[ 5], data, 20);
-    IOT_MD5_GET_UINT32_LE(X[ 6], data, 24);
-    IOT_MD5_GET_UINT32_LE(X[ 7], data, 28);
-    IOT_MD5_GET_UINT32_LE(X[ 8], data, 32);
-    IOT_MD5_GET_UINT32_LE(X[ 9], data, 36);
-    IOT_MD5_GET_UINT32_LE(X[10], data, 40);
-    IOT_MD5_GET_UINT32_LE(X[11], data, 44);
-    IOT_MD5_GET_UINT32_LE(X[12], data, 48);
-    IOT_MD5_GET_UINT32_LE(X[13], data, 52);
-    IOT_MD5_GET_UINT32_LE(X[14], data, 56);
-    IOT_MD5_GET_UINT32_LE(X[15], data, 60);
-
-#define S(x,n) ((x << n) | ((x & 0xFFFFFFFF) >> (32 - n)))
-
-#define P(a,b,c,d,k,s,t)                                \
-    {                                                       \
-        a += F(b,c,d) + X[k] + t; a = S(a,s) + b;           \
-    }
-
-    A = ctx->state[0];
-    B = ctx->state[1];
-    C = ctx->state[2];
-    D = ctx->state[3];
-
-#define F(x,y,z) (z ^ (x & (y ^ z)))
-
-    P(A, B, C, D,  0,  7, 0xD76AA478);
-    P(D, A, B, C,  1, 12, 0xE8C7B756);
-    P(C, D, A, B,  2, 17, 0x242070DB);
-    P(B, C, D, A,  3, 22, 0xC1BDCEEE);
-    P(A, B, C, D,  4,  7, 0xF57C0FAF);
-    P(D, A, B, C,  5, 12, 0x4787C62A);
-    P(C, D, A, B,  6, 17, 0xA8304613);
-    P(B, C, D, A,  7, 22, 0xFD469501);
-    P(A, B, C, D,  8,  7, 0x698098D8);
-    P(D, A, B, C,  9, 12, 0x8B44F7AF);
-    P(C, D, A, B, 10, 17, 0xFFFF5BB1);
-    P(B, C, D, A, 11, 22, 0x895CD7BE);
-    P(A, B, C, D, 12,  7, 0x6B901122);
-    P(D, A, B, C, 13, 12, 0xFD987193);
-    P(C, D, A, B, 14, 17, 0xA679438E);
-    P(B, C, D, A, 15, 22, 0x49B40821);
-
-#undef F
-
-#define F(x,y,z) (y ^ (z & (x ^ y)))
-
-    P(A, B, C, D,  1,  5, 0xF61E2562);
-    P(D, A, B, C,  6,  9, 0xC040B340);
-    P(C, D, A, B, 11, 14, 0x265E5A51);
-    P(B, C, D, A,  0, 20, 0xE9B6C7AA);
-    P(A, B, C, D,  5,  5, 0xD62F105D);
-    P(D, A, B, C, 10,  9, 0x02441453);
-    P(C, D, A, B, 15, 14, 0xD8A1E681);
-    P(B, C, D, A,  4, 20, 0xE7D3FBC8);
-    P(A, B, C, D,  9,  5, 0x21E1CDE6);
-    P(D, A, B, C, 14,  9, 0xC33707D6);
-    P(C, D, A, B,  3, 14, 0xF4D50D87);
-    P(B, C, D, A,  8, 20, 0x455A14ED);
-    P(A, B, C, D, 13,  5, 0xA9E3E905);
-    P(D, A, B, C,  2,  9, 0xFCEFA3F8);
-    P(C, D, A, B,  7, 14, 0x676F02D9);
-    P(B, C, D, A, 12, 20, 0x8D2A4C8A);
-
-#undef F
-
-#define F(x,y,z) (x ^ y ^ z)
-
-    P(A, B, C, D,  5,  4, 0xFFFA3942);
-    P(D, A, B, C,  8, 11, 0x8771F681);
-    P(C, D, A, B, 11, 16, 0x6D9D6122);
-    P(B, C, D, A, 14, 23, 0xFDE5380C);
-    P(A, B, C, D,  1,  4, 0xA4BEEA44);
-    P(D, A, B, C,  4, 11, 0x4BDECFA9);
-    P(C, D, A, B,  7, 16, 0xF6BB4B60);
-    P(B, C, D, A, 10, 23, 0xBEBFBC70);
-    P(A, B, C, D, 13,  4, 0x289B7EC6);
-    P(D, A, B, C,  0, 11, 0xEAA127FA);
-    P(C, D, A, B,  3, 16, 0xD4EF3085);
-    P(B, C, D, A,  6, 23, 0x04881D05);
-    P(A, B, C, D,  9,  4, 0xD9D4D039);
-    P(D, A, B, C, 12, 11, 0xE6DB99E5);
-    P(C, D, A, B, 15, 16, 0x1FA27CF8);
-    P(B, C, D, A,  2, 23, 0xC4AC5665);
-
-#undef F
-
-#define F(x,y,z) (y ^ (x | ~z))
-
-    P(A, B, C, D,  0,  6, 0xF4292244);
-    P(D, A, B, C,  7, 10, 0x432AFF97);
-    P(C, D, A, B, 14, 15, 0xAB9423A7);
-    P(B, C, D, A,  5, 21, 0xFC93A039);
-    P(A, B, C, D, 12,  6, 0x655B59C3);
-    P(D, A, B, C,  3, 10, 0x8F0CCC92);
-    P(C, D, A, B, 10, 15, 0xFFEFF47D);
-    P(B, C, D, A,  1, 21, 0x85845DD1);
-    P(A, B, C, D,  8,  6, 0x6FA87E4F);
-    P(D, A, B, C, 15, 10, 0xFE2CE6E0);
-    P(C, D, A, B,  6, 15, 0xA3014314);
-    P(B, C, D, A, 13, 21, 0x4E0811A1);
-    P(A, B, C, D,  4,  6, 0xF7537E82);
-    P(D, A, B, C, 11, 10, 0xBD3AF235);
-    P(C, D, A, B,  2, 15, 0x2AD7D2BB);
-    P(B, C, D, A,  9, 21, 0xEB86D391);
-
-#undef F
-
-    ctx->state[0] += A;
-    ctx->state[1] += B;
-    ctx->state[2] += C;
-    ctx->state[3] += D;
-}
-
-/*
- * MD5 process buffer
- */
-void utils_md5_update(iot_md5_context *ctx, const unsigned char *input, size_t ilen)
-{
-    size_t fill;
-    uint32_t left;
-
-    if (ilen == 0) {
-        return;
-    }
-
-    left = ctx->total[0] & 0x3F;
-    fill = 64 - left;
-
-    ctx->total[0] += (uint32_t) ilen;
-    ctx->total[0] &= 0xFFFFFFFF;
-
-    if (ctx->total[0] < (uint32_t) ilen) {
-        ctx->total[1]++;
-    }
-
-    if (left && ilen >= fill) {
-        memcpy((void *)(ctx->buffer + left), input, fill);
-        utils_md5_process(ctx, ctx->buffer);
-        input += fill;
-        ilen  -= fill;
-        left = 0;
-    }
-
-    while (ilen >= 64) {
-        utils_md5_process(ctx, input);
-        input += 64;
-        ilen  -= 64;
-    }
-
-    if (ilen > 0) {
-        memcpy((void *)(ctx->buffer + left), input, ilen);
-    }
-}
-
-static const unsigned char iot_md5_padding[64] = {
-    0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
-};
-
-/*
- * MD5 final digest
- */
-void utils_md5_finish(iot_md5_context *ctx, unsigned char output[16])
-{
-    uint32_t last, padn;
-    uint32_t high, low;
-    unsigned char msglen[8];
-
-    high = (ctx->total[0] >> 29)
-           | (ctx->total[1] <<  3);
-    low  = (ctx->total[0] <<  3);
-
-    IOT_MD5_PUT_UINT32_LE(low,  msglen, 0);
-    IOT_MD5_PUT_UINT32_LE(high, msglen, 4);
-
-    last = ctx->total[0] & 0x3F;
-    padn = (last < 56) ? (56 - last) : (120 - last);
-
-    utils_md5_update(ctx, iot_md5_padding, padn);
-    utils_md5_update(ctx, msglen, 8);
-
-    IOT_MD5_PUT_UINT32_LE(ctx->state[0], output,  0);
-    IOT_MD5_PUT_UINT32_LE(ctx->state[1], output,  4);
-    IOT_MD5_PUT_UINT32_LE(ctx->state[2], output,  8);
-    IOT_MD5_PUT_UINT32_LE(ctx->state[3], output, 12);
-}
-
-
-/*
- * output = MD5( input buffer )
- */
-void utils_md5(const unsigned char *input, size_t ilen, unsigned char output[16])
-{
-    iot_md5_context ctx;
-
-    utils_md5_init(&ctx);
-    utils_md5_starts(&ctx);
-    utils_md5_update(&ctx, input, ilen);
-    utils_md5_finish(&ctx, output);
-    utils_md5_free(&ctx);
-}
-
-#endif
diff --git a/bsp/bl808/m0/libraries/utils/src/utils_memp.c b/bsp/bl808/m0/libraries/utils/src/utils_memp.c
deleted file mode 100644
index 43d56f9ca1..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/utils_memp.c
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include 
-#include 
-#include 
-
-#define UTILS_MEMP_ALLOCED_NODE_PATTERN 0XA5
-#define MEM_ALIGN(addr, align) (((addr) + (align) -1) & ~((align)-1))
-
-int utils_memp_init(utils_memp_pool_t **pool, uint16_t node_size, uint16_t pool_cap, uint8_t align_req)
-{
-    utils_memp_pool_t *npool;
-    struct utils_memp_node *node;
-    struct utils_memp_node *pool_mem;
-    size_t size;
-    uint16_t padded_node_size;
-    uint16_t i;
-
-    align_req = MEM_ALIGN(align_req, sizeof(void *));
-    padded_node_size = MEM_ALIGN(node_size + sizeof(struct utils_memp_node), align_req);
-
-    size = sizeof(utils_memp_pool_t);
-    size = MEM_ALIGN(size, align_req);
-    size += padded_node_size * pool_cap;
-
-    npool = pvPortMalloc(size);
-
-    if (!npool) {
-        return -1;
-    }
-
-    node = (struct utils_memp_node *)((uint8_t *)npool + (size - padded_node_size * pool_cap));
-    npool->first_node = node;
-    npool->node_size = node_size;
-    npool->pool_cap = pool_cap;
-    npool->pool_size = 0;
-    npool->align_req = align_req;
-    npool->padded_node_size = padded_node_size;
-    npool->mem = NULL;
-    pool_mem = npool->mem;
-
-    for(i = 0; i < pool_cap; ++i) {
-        node->next = pool_mem;
-        pool_mem = node;
-        node = (struct utils_memp_node *)((uint8_t *)node + padded_node_size);
-    }
-    npool->mem = pool_mem;
-    npool->last_node = npool->mem;
-    *pool = npool;
-
-    return 0;
-}
-
-int utils_memp_init_alloced(utils_memp_pool_t *pool, uint16_t node_size, uint16_t pool_cap, uint8_t align_req)
-{
-    utils_memp_pool_t *npool = pool;
-    struct utils_memp_node *node;
-    struct utils_memp_node *pool_mem;
-    size_t size;
-    uint16_t padded_node_size;
-    uint16_t i;
-
-    align_req = MEM_ALIGN(align_req, sizeof(void *));
-    padded_node_size = MEM_ALIGN(node_size + sizeof(struct utils_memp_node), align_req);
-
-    size = sizeof(utils_memp_pool_t);
-    size = MEM_ALIGN(size, align_req);
-    size += padded_node_size * pool_cap;
-
-    node = (struct utils_memp_node *)((uint8_t *)npool + (size - padded_node_size * pool_cap));
-    npool->first_node = node;
-    npool->node_size = node_size;
-    npool->pool_cap = pool_cap;
-    npool->pool_size = 0;
-    npool->align_req = align_req;
-    npool->padded_node_size = padded_node_size;
-    npool->mem = NULL;
-    pool_mem = npool->mem;
-
-    for(i = 0; i < pool_cap; ++i) {
-        node->next = pool_mem;
-        pool_mem = node;
-        node = (struct utils_memp_node *)((uint8_t *)node + padded_node_size);
-    }
-    npool->mem = pool_mem;
-    npool->last_node = npool->mem;
-
-    return 0;
-}
-
-int utils_memp_deinit(utils_memp_pool_t *pool)
-{
-    if (!pool) {
-        return -1;
-    }
-    vPortFree(pool);
-
-    return 0;
-}
-
-void *utils_memp_malloc(utils_memp_pool_t *pool)
-{
-    struct utils_memp_node *node;
-    uint32_t *pat;
-    if (!pool) {
-        return NULL;
-    }
-    if (pool->pool_size == pool->pool_cap) {
-        return NULL;
-    }
-    node = pool->mem;
-    if (node != NULL) {
-        pool->mem = node->next;
-        pool->pool_size++;
-        pat = (uint32_t *)&node->next;
-        *pat = UTILS_MEMP_ALLOCED_NODE_PATTERN;
-        return (void *)node + sizeof(struct utils_memp_node);
-    } else {
-        return NULL;
-    }
-}
-
-int utils_memp_free(utils_memp_pool_t *pool, void *node)
-{
-    struct utils_memp_node *utils_memp_node;
-    node = node - sizeof(struct utils_memp_node);
-    uint32_t *pat;
-    int diff;
-
-    if (!pool || !node) {
-        return -1;
-    }
-    if (pool->pool_size == 0) {
-        return -1;
-    }
-    if (!(node >= pool->first_node && node <= pool->last_node)) {
-        return -1;
-    }
-    diff = node - pool->first_node;
-    if (diff % pool->padded_node_size) {
-        return -1;
-    }
-
-    pat = (uint32_t *)(&((struct utils_memp_node *)node)->next);
-    if (*pat != UTILS_MEMP_ALLOCED_NODE_PATTERN) {
-        return -1;
-    }
-    utils_memp_node = (struct utils_memp_node*)node;
-    utils_memp_node->next = pool->mem;
-    pool->mem = utils_memp_node;
-    pool->pool_size--;
-    return 0;
-}
diff --git a/bsp/bl808/m0/libraries/utils/src/utils_notifier.c b/bsp/bl808/m0/libraries/utils/src/utils_notifier.c
deleted file mode 100644
index c6ab60240f..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/utils_notifier.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "utils_notifier.h"
-
-int utils_notifier_chain_init(ntf_list_t *nl)
-{
-    utils_list_init((struct utils_list *)nl);
-
-    return 0;
-}
-
-int utils_notifier_chain_register(ntf_list_t *nl, utils_notifier_t *node)
-{
-    if (!nl || !node) {
-        return -1;
-    }
-    utils_list_push_back((struct utils_list *)nl, (struct utils_list_hdr *)node);
-
-    return 0;
-}
-
-int utils_notifier_chain_call(ntf_list_t *nl, void *env)
-{
-    utils_notifier_t *raw;
-
-    if (!nl) {
-        return 0;
-    }
-
-    raw = (utils_notifier_t *)nl->first;
-
-    while (raw) {
-        if (raw->cb) {
-            raw->cb(raw->cb_arg, env);
-        }
-        raw = (utils_notifier_t *)raw->node.next;
-    }
-
-    return 0;
-}
-
diff --git a/bsp/bl808/m0/libraries/utils/src/utils_psk_fast.c b/bsp/bl808/m0/libraries/utils/src/utils_psk_fast.c
deleted file mode 100644
index 87485e76a3..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/utils_psk_fast.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include 
-#include 
-
-#include 
-#include 
-#include 
-#include 
-
-#define A_SHA_DIGEST_LEN 20
-static void Bl_F_fast(unsigned char digest[36], unsigned char digest1[A_SHA_DIGEST_LEN], char *password, unsigned char *ssid, int ssidlength, int iterations, int count, unsigned char *output)
-{
-    int i, j;
-    int len = strlen(password);
-    int tmpLen = ssidlength + 4;
-    unsigned char * pTemp = digest;
-
-    /* U1 = PRF(P, S || int(i)) */
-    memcpy(digest, ssid, ssidlength);
-    digest[ssidlength] = (unsigned char)((count>>24) & 0xff);
-    digest[ssidlength+1] = (unsigned char)((count>>16) & 0xff);
-    digest[ssidlength+2] = (unsigned char)((count>>8) & 0xff);
-    digest[ssidlength+3] = (unsigned char)(count & 0xff);
-
-    bl_sha_mutex_take();
-    utils_hmac_sha1_fast(&pTemp,
-                   &tmpLen,
-                   1,
-                   (unsigned char*) password,
-                   len,
-                   digest1,
-                   A_SHA_DIGEST_LEN);
-
-    /* output = U1 */
-    memcpy(output, digest1, A_SHA_DIGEST_LEN);
-    pTemp = digest1;
-    for (i = 1; i < iterations; i++)
-    {
-        tmpLen = A_SHA_DIGEST_LEN;
-
-        /* Un = PRF(P, Un-1) */
-        utils_hmac_sha1_fast(&pTemp,
-                       &tmpLen,
-                       1,
-                       (unsigned char*) password,
-                       len,
-                       digest,
-                       A_SHA_DIGEST_LEN);
-
-        memcpy(digest1, digest, A_SHA_DIGEST_LEN);
-
-        /* output = output xor Un */
-        for (j = 0; j < A_SHA_DIGEST_LEN; j++)
-        {
-            output[j] ^= digest[j];
-        }
-    }
-    bl_sha_mutex_give();
-}
-
-int utils_wifi_psk_cal_fast_bin(char *password, unsigned char *ssid, int ssidlength, unsigned char *output)
-{
-    unsigned char digest[36], digest1[A_SHA_DIGEST_LEN];
-
-    if ((strlen(password) > 63) || (ssidlength > 32)) {
-        return -1;
-    }
-
-    Bl_F_fast(digest, digest1, password, ssid, ssidlength, 4096, 2, output);
-    memcpy(output + A_SHA_DIGEST_LEN, output, 12);
-    Bl_F_fast(digest, digest1, password, ssid, ssidlength, 4096, 1, output);
-
-    return 0;
-}
-
-int utils_wifi_psk_cal_fast(char *password, char *ssid, int ssid_len, char *output)
-{
-    int ret;
-    char psk[32];
-
-    ret = utils_wifi_psk_cal_fast_bin(password, (unsigned char *)ssid, ssid_len, (unsigned char *)psk);
-    if (0 == ret) {
-        utils_bin2hex(output, psk, 32);
-    }
-
-    return ret;
-}
diff --git a/bsp/bl808/m0/libraries/utils/src/utils_rbtree.c b/bsp/bl808/m0/libraries/utils/src/utils_rbtree.c
deleted file mode 100644
index 4a39ee0091..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/utils_rbtree.c
+++ /dev/null
@@ -1,526 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include 
-#include "utils_rbtree.h"
-
-// rb_node
-
-struct rb_node * rb_node_alloc ()
-{
-    return pvPortMalloc(sizeof(struct rb_node));
-}
-
-struct rb_node * rb_node_init (struct rb_node *self, void *value)
-{
-    if (self) {
-        self->red = 1;
-        self->link[0] = self->link[1] = NULL;
-        self->value = value;
-    }
-    return self;
-}
-
-struct rb_node * rb_node_create (void *value)
-{
-    return rb_node_init(rb_node_alloc(), value);
-}
-
-void rb_node_dealloc (struct rb_node *self)
-{
-    if (self) {
-        vPortFree(self);
-    }
-}
-
-static int rb_node_is_red (const struct rb_node *self)
-{
-    return self ? self->red : 0;
-}
-
-static struct rb_node * rb_node_rotate (struct rb_node *self, int dir)
-{
-    struct rb_node *result = NULL;
-
-    if (self) {
-        result = self->link[!dir];
-        self->link[!dir] = result->link[dir];
-        result->link[dir] = self;
-        self->red = 1;
-        result->red = 0;
-    }
-    return result;
-}
-
-static struct rb_node * rb_node_rotate2 (struct rb_node *self, int dir)
-{
-    struct rb_node *result = NULL;
-
-    if (self) {
-        self->link[!dir] = rb_node_rotate(self->link[!dir], !dir);
-        result = rb_node_rotate(self, dir);
-    }
-    return result;
-}
-
-// rb_tree - default callbacks
-int rb_tree_node_cmp_ptr_cb (struct rb_tree *self, struct rb_node *a, struct rb_node *b)
-{
-    return (a->value > b->value) - (a->value < b->value);
-}
-
-void rb_tree_node_dealloc_cb (struct rb_tree *self, struct rb_node *node)
-{
-    if (self) {
-        if (node) {
-            rb_node_dealloc(node);
-        }
-    }
-}
-
-// rb_tree
-struct rb_tree * rb_tree_alloc ()
-{
-    return pvPortMalloc(sizeof(struct rb_tree));
-}
-
-struct rb_tree * rb_tree_init (struct rb_tree *self, rb_tree_node_cmp_f node_cmp_cb)
-{
-    if (self) {
-        self->root = NULL;
-        self->size = 0;
-        self->cmp = node_cmp_cb ? node_cmp_cb : rb_tree_node_cmp_ptr_cb;
-    }
-
-    return self;
-}
-
-struct rb_tree * rb_tree_create (rb_tree_node_cmp_f node_cb)
-{
-    return rb_tree_init(rb_tree_alloc(), node_cb);
-}
-
-void rb_tree_dealloc(struct rb_tree *self, rb_tree_node_f node_cb)
-{
-    if (self) {
-        if (node_cb) {
-            struct rb_node *node = self->root;
-            struct rb_node *save = NULL;
-
-            // Rotate away the left links so that
-            // we can treat this like the destruction
-            // of a linked list
-            while (node) {
-                if (node->link[0] == NULL) {
-
-                    // No left links, just kill the node and move on
-                    save = node->link[1];
-                    node_cb(self, node);
-                    node = NULL;
-                } else {
-
-                    // Rotate away the left link and check again
-                    save = node->link[0];
-                    node->link[0] = save->link[1];
-                    save->link[1] = node;
-                }
-                node = save;
-            }
-        }
-        vPortFree(self);
-    }
-}
-
-int rb_tree_test(struct rb_tree *self, struct rb_node *root)
-{
-    int lh, rh;
-
-    if (NULL == root) {
-        return 1;
-    } else {
-        struct rb_node *ln = root->link[0];
-        struct rb_node *rn = root->link[1];
-
-        /* Consecutive red links */
-        if (rb_node_is_red(root)) {
-            if (rb_node_is_red(ln) || rb_node_is_red(rn)) {
-                printf("Red violation");
-                return 0;
-            }
-        }
-
-        lh = rb_tree_test(self, ln);
-        rh = rb_tree_test(self, rn);
-
-        /* Invalid binary search tree */
-        if ( ( ln != NULL && self->cmp(self, ln, root) >= 0 )
-            || ( rn != NULL && self->cmp(self, rn, root) <= 0))
-        {
-            puts ( "Binary tree violation" );
-            return 0;
-        }
-
-        /* Black height mismatch */
-        if ( lh != 0 && rh != 0 && lh != rh ) {
-            puts ( "Black violation" );
-            return 0;
-        }
-
-        /* Only count black links */
-        if ( lh != 0 && rh != 0 )
-            return rb_node_is_red ( root ) ? lh : lh + 1;
-        else
-            return 0;
-    }
-}
-
-void * rb_tree_find(struct rb_tree *self, void *value)
-{
-    void *result = NULL;
-
-    if (self) {
-        struct rb_node node = { .value = value };
-        struct rb_node *it = self->root;
-        int cmp = 0;
-        while (it) {
-            if ((cmp = self->cmp(self, it, &node))) {
-
-                // If the tree supports duplicates, they should be
-                // chained to the right subtree for this to work
-                it = it->link[cmp < 0];
-            } else {
-                break;
-            }
-        }
-        result = it ? it->value : NULL;
-    }
-    return result;
-}
-
-// Creates (malloc'ates)
-int rb_tree_insert(struct rb_tree *self, void *value)
-{
-    struct rb_node *node;
-
-    if (NULL == self) {
-        return 0;
-    }
-
-    node = rb_node_create(value);
-
-    if (NULL == node) {
-        return 0;
-    }
-
-    return rb_tree_insert_node(self, node);
-}
-
-// Returns 1 on success, 0 otherwise.
-int rb_tree_insert_node (struct rb_tree *self, struct rb_node *node)
-{
-    if (self && node) {
-        if (self->root == NULL) {
-            self->root = node;
-        } else {
-            struct rb_node head = { 0 }; // False tree root
-            struct rb_node *g, *t;       // Grandparent & parent
-            struct rb_node *p, *q;       // Iterator & parent
-            int dir = 0, last = 0;
-
-            // Set up our helpers
-            t = &head;
-            g = p = NULL;
-            q = t->link[1] = self->root;
-
-            // Search down the tree for a place to insert
-            while (1) {
-                if (q == NULL) {
-
-                    // Insert node at the first null link.
-                    p->link[dir] = q = node;
-                } else if (rb_node_is_red(q->link[0]) && rb_node_is_red(q->link[1])) {
-
-                    // Simple red violation: color flip
-                    q->red = 1;
-                    q->link[0]->red = 0;
-                    q->link[1]->red = 0;
-                }
-
-                if (rb_node_is_red(q) && rb_node_is_red(p)) {
-
-                    // Hard red violation: rotations necessary
-                    int dir2 = t->link[1] == g;
-                    if (q == p->link[last]) {
-                        t->link[dir2] = rb_node_rotate(g, !last);
-                    } else {
-                        t->link[dir2] = rb_node_rotate2(g, !last);
-                    }
-                }
-
-                // Stop working if we inserted a node. This
-                // check also disallows duplicates in the tree
-                if (self->cmp(self, q, node) == 0) {
-                    break;
-                }
-
-                last = dir;
-                dir = self->cmp(self, q, node) < 0;
-
-                // Move the helpers down
-                if (g != NULL) {
-                    t = g;
-                }
-
-                g = p, p = q;
-                q = q->link[dir];
-            }
-
-            // Update the root (it may be different)
-            self->root = head.link[1];
-        }
-
-        // Make the root black for simplified logic
-        self->root->red = 0;
-        ++self->size;
-    } else {
-        return 0;
-    }
-
-    return 1;
-}
-
-// Returns 1 if the value was removed, 0 otherwise. Optional node callback
-// can be provided to dealloc node and/or user data. Use rb_tree_node_dealloc
-// default callback to deallocate node created by rb_tree_insert(...).
-int rb_tree_remove_with_cb (struct rb_tree *self, void *value, rb_tree_node_f node_cb)
-{
-    if (self->root != NULL) {
-        struct rb_node head = {0}; // False tree root
-        struct rb_node node = { .value = value }; // Value wrapper node
-        struct rb_node *q, *p, *g; // Helpers
-        struct rb_node *f = NULL;  // Found item
-        int dir = 1;
-
-        // Set up our helpers
-        q = &head;
-        g = p = NULL;
-        q->link[1] = self->root;
-
-        // Search and push a red node down
-        // to fix red violations as we go
-        while (q->link[dir] != NULL) {
-            int last = dir;
-
-            // Move the helpers down
-            g = p, p = q;
-            q = q->link[dir];
-            dir = self->cmp(self, q, &node) < 0;
-
-            // Save the node with matching value and keep
-            // going; we'll do removal tasks at the end
-            if (self->cmp(self, q, &node) == 0) {
-                f = q;
-            }
-
-            // Push the red node down with rotations and color flips
-            if (!rb_node_is_red(q) && !rb_node_is_red(q->link[dir])) {
-                if (rb_node_is_red(q->link[!dir])) {
-                    p = p->link[last] = rb_node_rotate(q, dir);
-                } else if (!rb_node_is_red(q->link[!dir])) {
-                    struct rb_node *s = p->link[!last];
-                    if (s) {
-                        if (!rb_node_is_red(s->link[!last]) && !rb_node_is_red(s->link[last])) {
-
-                            // Color flip
-                            p->red = 0;
-                            s->red = 1;
-                            q->red = 1;
-                        } else {
-                            int dir2 = g->link[1] == p;
-                            if (rb_node_is_red(s->link[last])) {
-                                g->link[dir2] = rb_node_rotate2(p, last);
-                            } else if (rb_node_is_red(s->link[!last])) {
-                                g->link[dir2] = rb_node_rotate(p, last);
-                            }
-
-                            // Ensure correct coloring
-                            q->red = g->link[dir2]->red = 1;
-                            g->link[dir2]->link[0]->red = 0;
-                            g->link[dir2]->link[1]->red = 0;
-                        }
-                    }
-                }
-            }
-        }
-
-        // Replace and remove the saved node
-        if (f) {
-            void *tmp = f->value;
-            f->value = q->value;
-            q->value = tmp;
-
-            p->link[p->link[1] == q] = q->link[q->link[0] == NULL];
-
-            if (node_cb) {
-                node_cb(self, q);
-            }
-            q = NULL;
-        }
-
-        // Update the root (it may be different)
-        self->root = head.link[1];
-
-        // Make the root black for simplified logic
-        if (self->root != NULL) {
-            self->root->red = 0;
-        }
-
-        --self->size;
-    }
-    return 1;
-}
-
-int rb_tree_remove (struct rb_tree *self, void *value)
-{
-    int result = 0;
-
-    if (self) {
-        result = rb_tree_remove_with_cb(self, value, rb_tree_node_dealloc_cb);
-    }
-    return result;
-}
-
-size_t rb_tree_size (struct rb_tree *self)
-{
-    size_t result = 0;
-
-    if (self) {
-        result = self->size;
-    }
-    return result;
-}
-
-// rb_iter
-struct rb_iter * rb_iter_alloc ()
-{
-    return pvPortMalloc(sizeof(struct rb_iter));
-}
-
-struct rb_iter * rb_iter_init (struct rb_iter *self)
-{
-    if (self) {
-        self->tree = NULL;
-        self->node = NULL;
-        self->top = 0;
-    }
-    return self;
-}
-
-struct rb_iter * rb_iter_create ()
-{
-    return rb_iter_init(rb_iter_alloc());
-}
-
-void rb_iter_dealloc (struct rb_iter *self)
-{
-    if (self) {
-        vPortFree(self);
-    }
-}
-
-// Internal function, init traversal object, dir determines whether
-// to begin traversal at the smallest or largest valued node.
-static void * rb_iter_start (struct rb_iter *self, struct rb_tree *tree, int dir)
-{
-    void *result = NULL;
-
-    if (self) {
-        self->tree = tree;
-        self->node = tree->root;
-        self->top = 0;
-
-        // Save the path for later selfersal
-        if (self->node != NULL) {
-            while (self->node->link[dir] != NULL) {
-                self->path[self->top++] = self->node;
-                self->node = self->node->link[dir];
-            }
-        }
-        result = self->node == NULL ? NULL : self->node->value;
-    }
-
-    return result;
-}
-
-// Traverse a red black tree in the user-specified direction (0 asc, 1 desc)
-static void * rb_iter_move(struct rb_iter *self, int dir)
-{
-    if (self->node->link[dir] != NULL) {
-        // Continue down this branch
-        self->path[self->top++] = self->node;
-        self->node = self->node->link[dir];
-        while ( self->node->link[!dir] != NULL ) {
-            self->path[self->top++] = self->node;
-            self->node = self->node->link[!dir];
-        }
-    } else {
-        // Move to the next branch
-        struct rb_node *last = NULL;
-        do {
-            if (self->top == 0) {
-                self->node = NULL;
-                break;
-            }
-            last = self->node;
-            self->node = self->path[--self->top];
-        } while (last == self->node->link[dir]);
-    }
-    return self->node == NULL ? NULL : self->node->value;
-}
-
-void *rb_iter_first(struct rb_iter *self, struct rb_tree *tree)
-{
-    return rb_iter_start(self, tree, 0);
-}
-
-void * rb_iter_last(struct rb_iter *self, struct rb_tree *tree)
-{
-    return rb_iter_start(self, tree, 1);
-}
-
-void * rb_iter_next(struct rb_iter *self)
-{
-    return rb_iter_move(self, 1);
-}
-
-void * rb_iter_prev(struct rb_iter *self)
-{
-    return rb_iter_move(self, 0);
-}
diff --git a/bsp/bl808/m0/libraries/utils/src/utils_ringblk.c b/bsp/bl808/m0/libraries/utils/src/utils_ringblk.c
deleted file mode 100644
index 7a9b3da047..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/utils_ringblk.c
+++ /dev/null
@@ -1,578 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-
-#include 
-#include 
-
-#include "FreeRTOS.h"
-#include "utils_list.h"
-#include "utils_ringblk.h"
-
-/**
- * ring block buffer object initialization
- *
- * @param rbb ring block buffer object
- * @param buf buffer
- * @param buf_size buffer size
- * @param block_set block set
- * @param blk_max_num max block number
- *
- * @note When your application need align access, please make the buffer address is aligned.
- */
-void utils_rbb_init(utils_rbb_t rbb, uint8_t *buf, uint32_t buf_size, utils_rbb_blk_t block_set, uint32_t blk_max_num)
-{
-    uint32_t i;
-
-    assert(rbb);
-    assert(buf);
-    assert(block_set);
-
-    rbb->buf = buf;
-    rbb->buf_size = buf_size;
-    rbb->blk_set = block_set;
-    rbb->blk_max_num = blk_max_num;
-    utils_slist_init(&rbb->blk_list);
-    /* initialize block status */
-    for (i = 0; i < blk_max_num; i++)
-    {
-        block_set[i].status = RBB_BLK_UNUSED;
-    }
-}
-
-
-/**
- * ring block buffer object create
- *
- * @param buf_size buffer size
- * @param blk_max_num max block number
- *
- * @return != NULL: ring block buffer object
- *            NULL: create failed
- */
-utils_rbb_t utils_rbb_create(uint32_t buf_size, uint32_t blk_max_num)
-{
-    utils_rbb_t rbb = NULL;
-    uint8_t *buf;
-    utils_rbb_blk_t blk_set;
-
-    rbb = (utils_rbb_t)pvPortMalloc(sizeof(struct utils_rbb));
-    if (!rbb)
-    {
-        return NULL;
-    }
-
-    buf = (uint8_t *)pvPortMalloc(buf_size);
-    if (!buf)
-    {
-        vPortFree(rbb);
-        return NULL;
-    }
-
-    blk_set = (utils_rbb_blk_t)pvPortMalloc(sizeof(struct utils_rbb_blk) * blk_max_num);
-    if (!blk_set)
-    {
-        vPortFree(buf);
-        vPortFree(rbb);
-        return NULL;
-    }
-
-    utils_rbb_init(rbb, buf, buf_size, blk_set, blk_max_num);
-
-    return rbb;
-}
-
-/**
- * ring block buffer object destroy
- *
- * @param rbb ring block buffer object
- */
-void utils_rbb_destroy(utils_rbb_t rbb)
-{
-    assert(rbb);
-
-    vPortFree(rbb->buf);
-    vPortFree(rbb->blk_set);
-    vPortFree(rbb);
-
-}
-
-utils_rbb_blk_t utils_rbb_find_used_blk(utils_rbb_t rbb)
-{
-    uint32_t i;
-
-    assert(rbb);
-
-    for (i = 0; i < rbb->blk_max_num; i ++)
-    {
-        if (rbb->blk_set[i].status != RBB_BLK_UNUSED)
-        {
-            return &rbb->blk_set[i];
-        }
-    }
-
-    return NULL;
-}
-
-utils_rbb_blk_t utils_rbb_find_empty_blk(utils_rbb_t rbb)
-{
-    uint32_t i;
-
-    assert(rbb);
-
-    for (i = 0; i < rbb->blk_max_num; i ++)
-    {
-        if (rbb->blk_set[i].status == RBB_BLK_UNUSED)
-        {
-            return &rbb->blk_set[i];
-        }
-    }
-
-    return NULL;
-}
-
-/**
- * Allocate a block by given size. The block will add to blk_list when allocate success.
- *
- * @param rbb ring block buffer object
- * @param blk_size block size
- *
- * @note When your application need align access, please make the blk_szie is aligned.
- *
- * @return != NULL: allocated block
- *            NULL: allocate failed
- */
-utils_rbb_blk_t utils_rbb_blk_alloc(utils_rbb_t rbb, uint32_t blk_size)
-{
-    uint32_t empty1 = 0, empty2 = 0;
-    utils_rbb_blk_t head, tail, new_rbb = NULL;
-    int list_num = 0;
-
-    assert(rbb);
-    assert(blk_size < (1L << 24));
-
-    portENTER_CRITICAL();
-
-    new_rbb = utils_rbb_find_empty_blk(rbb);
-
-    list_num = utils_slist_entry_number(&rbb->blk_list);
-
-    if (list_num < rbb->blk_max_num && new_rbb)
-    {
-        if (list_num > 0)
-        {
-            head = utils_slist_first_entry(&rbb->blk_list, struct utils_rbb_blk, list);
-            tail = utils_slist_tail_entry(&rbb->blk_list, struct utils_rbb_blk, list);
-            if (head->buf <= tail->buf)
-            {
-                /**
-                 *                      head                     tail
-                 * +--------------------------------------+-----------------+------------------+
-                 * |      empty2     | block1 |   block2  |      block3     |       empty1     |
-                 * +--------------------------------------+-----------------+------------------+
-                 *                            rbb->buf
-                 */
-                empty1 = (rbb->buf + rbb->buf_size) - (tail->buf + tail->size);
-                empty2 = head->buf - rbb->buf;
-
-                if (empty1 >= blk_size)
-                {
-                    utils_slist_append(&rbb->blk_list, &new_rbb->list);
-                    new_rbb->status = RBB_BLK_INITED;
-                    new_rbb->buf = tail->buf + tail->size;
-                    new_rbb->size = blk_size;
-                }
-                else if (empty2 >= blk_size)
-                {
-                    utils_slist_append(&rbb->blk_list, &new_rbb->list);
-                    new_rbb->status = RBB_BLK_INITED;
-                    new_rbb->buf = rbb->buf;
-                    new_rbb->size = blk_size;
-                }
-                else
-                {
-                    /* no space */
-                    new_rbb = NULL;
-                }
-            }
-            else
-            {
-                /**
-                 *        tail                                              head
-                 * +----------------+-------------------------------------+--------+-----------+
-                 * |     block3     |                empty1               | block1 |  block2   |
-                 * +----------------+-------------------------------------+--------+-----------+
-                 *                            rbb->buf
-                 */
-                empty1 = head->buf - (tail->buf + tail->size);
-
-                if (empty1 >= blk_size)
-                {
-                    utils_slist_append(&rbb->blk_list, &new_rbb->list);
-                    new_rbb->status = RBB_BLK_INITED;
-                    new_rbb->buf = tail->buf + tail->size;
-                    new_rbb->size = blk_size;
-                }
-                else
-                {
-                    /* no space */
-                    new_rbb = NULL;
-                }
-            }
-        }
-        else
-        {
-            /* the list is empty */
-            utils_slist_append(&rbb->blk_list, &new_rbb->list);
-            new_rbb->status = RBB_BLK_INITED;
-            new_rbb->buf = rbb->buf;
-            new_rbb->size = blk_size;
-        }
-    }
-    else
-    {
-        new_rbb = NULL;
-    }
-
-    portEXIT_CRITICAL();
-
-    return new_rbb;
-}
-
-/**
- * put a block to ring block buffer object
- *
- * @param block the block
- */
-void utils_rbb_blk_put(utils_rbb_blk_t block)
-{
-    assert(block);
-    assert(block->status == RBB_BLK_INITED);
-
-    block->status = RBB_BLK_PUT;
-}
-
-/**
- * get a block from the ring block buffer object
- *
- * @param rbb ring block buffer object
- *
- * @return != NULL: block
- *            NULL: get failed
- */
-utils_rbb_blk_t utils_rbb_blk_get(utils_rbb_t rbb)
-{
-    utils_rbb_blk_t block = NULL;
-    utils_slist_t *node;
-
-    assert(rbb);
-
-    if (utils_slist_empty(&rbb->blk_list))
-        return 0;
-
-    portENTER_CRITICAL();
-
-    for (node = utils_slist_first(&rbb->blk_list); node; node = utils_slist_next(node))
-    {
-        block = utils_slist_entry(node, struct utils_rbb_blk, list);
-        if (block->status == RBB_BLK_PUT)
-        {
-            block->status = RBB_BLK_GET;
-            goto __exit;
-        }
-    }
-    /* not found */
-    block = NULL;
-
-__exit:
-
-    portEXIT_CRITICAL();
-
-    return block;
-}
-
-/**
- * return the block size
- *
- * @param block the block
- *
- * @return block size
- */
-uint32_t utils_rbb_blk_size(utils_rbb_blk_t block)
-{
-    assert(block);
-
-    return block->size;
-}
-
-/**
- * return the block buffer
- *
- * @param block the block
- *
- * @return block buffer
- */
-uint8_t *utils_rbb_blk_buf(utils_rbb_blk_t block)
-{
-    assert(block);
-
-    return block->buf;
-}
-
-/**
- * free the block
- *
- * @param rbb ring block buffer object
- * @param block the block
- */
-void utils_rbb_blk_free(utils_rbb_t rbb, utils_rbb_blk_t block)
-{
-    assert(rbb);
-    assert(block);
-    assert(block->status != RBB_BLK_UNUSED);
-
-    portENTER_CRITICAL();
-
-    /* remove it on rbb block list */
-    utils_slist_del(&block->list, &rbb->blk_list);
-
-    block->status = RBB_BLK_UNUSED;
-
-    portEXIT_CRITICAL();
-}
-
-/**
- * get a continuous block to queue by given size
- *
- *          tail                         head
- * +------------------+---------------+--------+----------+--------+
- * |      block3      |  empty1       | block1 |  block2  |fragment|
- * +------------------+------------------------+----------+--------+
- *                                    |<-- return_size -->|    |
- *                                    |<--- queue_data_len --->|
- *
- *         tail                          head
- * +------------------+---------------+--------+----------+--------+
- * |      block3      |  empty1       | block1 |  block2  |fragment|
- * +------------------+------------------------+----------+--------+
- *                                    |<-- return_size -->|              out of len(b1+b2+b3)    |
- *                                    |<-------------------- queue_data_len -------------------->|
- *
- * @param rbb ring block buffer object
- * @param queue_data_len The max queue data size, and the return size must less then it.
- * @param queue continuous block queue
- *
- * @return the block queue data total size
- */
-uint32_t utils_rbb_blk_queue_get(utils_rbb_t rbb, uint32_t queue_data_len, utils_rbb_blk_queue_t blk_queue)
-{
-    uint32_t data_total_size = 0;
-    utils_slist_t *node;
-    utils_rbb_blk_t last_block = NULL, block;
-
-    assert(rbb);
-    assert(blk_queue);
-
-    if (utils_slist_empty(&rbb->blk_list))
-        return 0;
-
-    portENTER_CRITICAL();
-
-    for (node = utils_slist_first(&rbb->blk_list); node; node = utils_slist_next(node))
-    {
-        if (!last_block)
-        {
-            last_block = utils_slist_entry(node, struct utils_rbb_blk, list);
-            if (last_block->status == RBB_BLK_PUT)
-            {
-                /* save the first put status block to queue */
-                blk_queue->blocks = last_block;
-                blk_queue->blk_num = 0;
-            }
-            else
-            {
-                /* the first block must be put status */
-                last_block = NULL;
-                continue;
-            }
-        }
-        else
-        {
-            block = utils_slist_entry(node, struct utils_rbb_blk, list);
-            /*
-             * these following conditions will break the loop:
-             * 1. the current block is not put status
-             * 2. the last block and current block is not continuous
-             * 3. the data_total_size will out of range
-             */
-            if (block->status != RBB_BLK_PUT ||
-                last_block->buf > block->buf ||
-                data_total_size + block->size > queue_data_len)
-            {
-                break;
-            }
-            /* backup last block */
-            last_block = block;
-        }
-        /* remove current block */
-        utils_slist_del(&last_block->list, &rbb->blk_list);
-        data_total_size += last_block->size;
-        last_block->status = RBB_BLK_GET;
-        blk_queue->blk_num++;
-    }
-
-    portEXIT_CRITICAL();
-
-    return data_total_size;
-}
-
-/**
- * get all block length on block queue
- *
- * @param blk_queue the block queue
- *
- * @return total length
- */
-uint32_t utils_rbb_blk_queue_len(utils_rbb_blk_queue_t blk_queue)
-{
-    uint32_t i, data_total_size = 0;
-
-    assert(blk_queue);
-
-    for (i = 0; i < blk_queue->blk_num; i++)
-    {
-        data_total_size += blk_queue->blocks[i].size;
-    }
-
-    return data_total_size;
-}
-
-/**
- * return the block queue buffer
- *
- * @param blk_queue the block queue
- *
- * @return block queue buffer
- */
-uint8_t *utils_rbb_blk_queue_buf(utils_rbb_blk_queue_t blk_queue)
-{
-    assert(blk_queue);
-
-    return blk_queue->blocks[0].buf;
-}
-
-/**
- * free the block queue
- *
- * @param rbb ring block buffer object
- * @param blk_queue the block queue
- */
-void utils_rbb_blk_queue_free(utils_rbb_t rbb, utils_rbb_blk_queue_t blk_queue)
-{
-    uint32_t i;
-
-    assert(rbb);
-    assert(blk_queue);
-
-    for (i = 0; i < blk_queue->blk_num; i++)
-    {
-        utils_rbb_blk_free(rbb, &blk_queue->blocks[i]);
-    }
-}
-
-/**
- * The put status and buffer continuous blocks can be make a block queue.
- * This function will return the length which from next can be make block queue.
- *
- * @param rbb ring block buffer object
- *
- * @return the next can be make block queue's length
- */
-uint32_t utils_rbb_next_blk_queue_len(utils_rbb_t rbb)
-{
-    uint32_t data_len = 0;
-    utils_slist_t *node;
-    utils_rbb_blk_t last_block = NULL, block;
-
-    assert(rbb);
-
-    if (utils_slist_empty(&rbb->blk_list))
-        return 0;
-
-    portENTER_CRITICAL();
-
-    for (node = utils_slist_first(&rbb->blk_list); node; node = utils_slist_next(node))
-    {
-        if (!last_block)
-        {
-            last_block = utils_slist_entry(node, struct utils_rbb_blk, list);
-            if (last_block->status != RBB_BLK_PUT)
-            {
-                /* the first block must be put status */
-                last_block = NULL;
-                continue;
-            }
-        }
-        else
-        {
-            block = utils_slist_entry(node, struct utils_rbb_blk, list);
-            /*
-             * these following conditions will break the loop:
-             * 1. the current block is not put status
-             * 2. the last block and current block is not continuous
-             */
-            if (block->status != RBB_BLK_PUT || last_block->buf > block->buf)
-            {
-                break;
-            }
-            /* backup last block */
-            last_block = block;
-        }
-        data_len += last_block->size;
-    }
-
-    portEXIT_CRITICAL();
-
-    return data_len;
-}
-
-/**
- * get the ring block buffer object buffer size
- *
- * @param rbb ring block buffer object
- *
- * @return buffer size
- */
-uint32_t utils_rbb_get_buf_size(utils_rbb_t rbb)
-{
-    assert(rbb);
-
-    return rbb->buf_size;
-}
diff --git a/bsp/bl808/m0/libraries/utils/src/utils_sha1.c b/bsp/bl808/m0/libraries/utils/src/utils_sha1.c
deleted file mode 100644
index 74b50940fe..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/utils_sha1.c
+++ /dev/null
@@ -1,355 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifdef UTILS_SHA1
-
-
-#include 
-#include 
-#include "iot_import.h"
-#include "iotx_log.h"
-#include "utils_sha1.h"
-
-/* Implementation that should never be optimized out by the compiler */
-static void utils_sha1_zeroize(void *v, size_t n)
-{
-    volatile unsigned char *p = v;
-    while (n--) {
-        *p++ = 0;
-    }
-}
-
-/*
- * 32-bit integer manipulation macros (big endian)
- */
-#ifndef IOT_SHA1_GET_UINT32_BE
-#define IOT_SHA1_GET_UINT32_BE(n,b,i)                            \
-    {                                                       \
-        (n) = ( (uint32_t) (b)[(i)    ] << 24 )             \
-              | ( (uint32_t) (b)[(i) + 1] << 16 )             \
-              | ( (uint32_t) (b)[(i) + 2] <<  8 )             \
-              | ( (uint32_t) (b)[(i) + 3]       );            \
-    }
-#endif
-
-#ifndef IOT_SHA1_PUT_UINT32_BE
-#define IOT_SHA1_PUT_UINT32_BE(n,b,i)                            \
-    {                                                       \
-        (b)[(i)    ] = (unsigned char) ( (n) >> 24 );       \
-        (b)[(i) + 1] = (unsigned char) ( (n) >> 16 );       \
-        (b)[(i) + 2] = (unsigned char) ( (n) >>  8 );       \
-        (b)[(i) + 3] = (unsigned char) ( (n)       );       \
-    }
-#endif
-
-void utils_sha1_init(iot_sha1_context *ctx)
-{
-    memset(ctx, 0, sizeof(iot_sha1_context));
-}
-
-void utils_sha1_free(iot_sha1_context *ctx)
-{
-    if (ctx == NULL) {
-        return;
-    }
-
-    utils_sha1_zeroize(ctx, sizeof(iot_sha1_context));
-}
-
-void utils_sha1_clone(iot_sha1_context *dst,
-                      const iot_sha1_context *src)
-{
-    *dst = *src;
-}
-
-/*
- * SHA-1 context setup
- */
-void utils_sha1_starts(iot_sha1_context *ctx)
-{
-    ctx->total[0] = 0;
-    ctx->total[1] = 0;
-
-    ctx->state[0] = 0x67452301;
-    ctx->state[1] = 0xEFCDAB89;
-    ctx->state[2] = 0x98BADCFE;
-    ctx->state[3] = 0x10325476;
-    ctx->state[4] = 0xC3D2E1F0;
-}
-
-void utils_sha1_process(iot_sha1_context *ctx, const unsigned char data[64])
-{
-    uint32_t temp, W[16], A, B, C, D, E;
-
-    IOT_SHA1_GET_UINT32_BE(W[ 0], data,  0);
-    IOT_SHA1_GET_UINT32_BE(W[ 1], data,  4);
-    IOT_SHA1_GET_UINT32_BE(W[ 2], data,  8);
-    IOT_SHA1_GET_UINT32_BE(W[ 3], data, 12);
-    IOT_SHA1_GET_UINT32_BE(W[ 4], data, 16);
-    IOT_SHA1_GET_UINT32_BE(W[ 5], data, 20);
-    IOT_SHA1_GET_UINT32_BE(W[ 6], data, 24);
-    IOT_SHA1_GET_UINT32_BE(W[ 7], data, 28);
-    IOT_SHA1_GET_UINT32_BE(W[ 8], data, 32);
-    IOT_SHA1_GET_UINT32_BE(W[ 9], data, 36);
-    IOT_SHA1_GET_UINT32_BE(W[10], data, 40);
-    IOT_SHA1_GET_UINT32_BE(W[11], data, 44);
-    IOT_SHA1_GET_UINT32_BE(W[12], data, 48);
-    IOT_SHA1_GET_UINT32_BE(W[13], data, 52);
-    IOT_SHA1_GET_UINT32_BE(W[14], data, 56);
-    IOT_SHA1_GET_UINT32_BE(W[15], data, 60);
-
-#define S(x,n) ((x << n) | ((x & 0xFFFFFFFF) >> (32 - n)))
-
-#define R(t)                                            \
-    (                                                       \
-            temp = W[( t -  3 ) & 0x0F] ^ W[( t - 8 ) & 0x0F] ^ \
-                   W[( t - 14 ) & 0x0F] ^ W[  t       & 0x0F],  \
-            ( W[t & 0x0F] = S(temp,1) )                         \
-    )
-
-#define P(a,b,c,d,e,x)                                  \
-    {                                                       \
-        e += S(a,5) + F(b,c,d) + K + x; b = S(b,30);        \
-    }
-
-    A = ctx->state[0];
-    B = ctx->state[1];
-    C = ctx->state[2];
-    D = ctx->state[3];
-    E = ctx->state[4];
-
-#define F(x,y,z) (z ^ (x & (y ^ z)))
-#define K 0x5A827999
-
-    P(A, B, C, D, E, W[0]);
-    P(E, A, B, C, D, W[1]);
-    P(D, E, A, B, C, W[2]);
-    P(C, D, E, A, B, W[3]);
-    P(B, C, D, E, A, W[4]);
-    P(A, B, C, D, E, W[5]);
-    P(E, A, B, C, D, W[6]);
-    P(D, E, A, B, C, W[7]);
-    P(C, D, E, A, B, W[8]);
-    P(B, C, D, E, A, W[9]);
-    P(A, B, C, D, E, W[10]);
-    P(E, A, B, C, D, W[11]);
-    P(D, E, A, B, C, W[12]);
-    P(C, D, E, A, B, W[13]);
-    P(B, C, D, E, A, W[14]);
-    P(A, B, C, D, E, W[15]);
-    P(E, A, B, C, D, R(16));
-    P(D, E, A, B, C, R(17));
-    P(C, D, E, A, B, R(18));
-    P(B, C, D, E, A, R(19));
-
-#undef K
-#undef F
-
-#define F(x,y,z) (x ^ y ^ z)
-#define K 0x6ED9EBA1
-
-    P(A, B, C, D, E, R(20));
-    P(E, A, B, C, D, R(21));
-    P(D, E, A, B, C, R(22));
-    P(C, D, E, A, B, R(23));
-    P(B, C, D, E, A, R(24));
-    P(A, B, C, D, E, R(25));
-    P(E, A, B, C, D, R(26));
-    P(D, E, A, B, C, R(27));
-    P(C, D, E, A, B, R(28));
-    P(B, C, D, E, A, R(29));
-    P(A, B, C, D, E, R(30));
-    P(E, A, B, C, D, R(31));
-    P(D, E, A, B, C, R(32));
-    P(C, D, E, A, B, R(33));
-    P(B, C, D, E, A, R(34));
-    P(A, B, C, D, E, R(35));
-    P(E, A, B, C, D, R(36));
-    P(D, E, A, B, C, R(37));
-    P(C, D, E, A, B, R(38));
-    P(B, C, D, E, A, R(39));
-
-#undef K
-#undef F
-
-#define F(x,y,z) ((x & y) | (z & (x | y)))
-#define K 0x8F1BBCDC
-
-    P(A, B, C, D, E, R(40));
-    P(E, A, B, C, D, R(41));
-    P(D, E, A, B, C, R(42));
-    P(C, D, E, A, B, R(43));
-    P(B, C, D, E, A, R(44));
-    P(A, B, C, D, E, R(45));
-    P(E, A, B, C, D, R(46));
-    P(D, E, A, B, C, R(47));
-    P(C, D, E, A, B, R(48));
-    P(B, C, D, E, A, R(49));
-    P(A, B, C, D, E, R(50));
-    P(E, A, B, C, D, R(51));
-    P(D, E, A, B, C, R(52));
-    P(C, D, E, A, B, R(53));
-    P(B, C, D, E, A, R(54));
-    P(A, B, C, D, E, R(55));
-    P(E, A, B, C, D, R(56));
-    P(D, E, A, B, C, R(57));
-    P(C, D, E, A, B, R(58));
-    P(B, C, D, E, A, R(59));
-
-#undef K
-#undef F
-
-#define F(x,y,z) (x ^ y ^ z)
-#define K 0xCA62C1D6
-
-    P(A, B, C, D, E, R(60));
-    P(E, A, B, C, D, R(61));
-    P(D, E, A, B, C, R(62));
-    P(C, D, E, A, B, R(63));
-    P(B, C, D, E, A, R(64));
-    P(A, B, C, D, E, R(65));
-    P(E, A, B, C, D, R(66));
-    P(D, E, A, B, C, R(67));
-    P(C, D, E, A, B, R(68));
-    P(B, C, D, E, A, R(69));
-    P(A, B, C, D, E, R(70));
-    P(E, A, B, C, D, R(71));
-    P(D, E, A, B, C, R(72));
-    P(C, D, E, A, B, R(73));
-    P(B, C, D, E, A, R(74));
-    P(A, B, C, D, E, R(75));
-    P(E, A, B, C, D, R(76));
-    P(D, E, A, B, C, R(77));
-    P(C, D, E, A, B, R(78));
-    P(B, C, D, E, A, R(79));
-
-#undef K
-#undef F
-
-    ctx->state[0] += A;
-    ctx->state[1] += B;
-    ctx->state[2] += C;
-    ctx->state[3] += D;
-    ctx->state[4] += E;
-}
-
-/*
- * SHA-1 process buffer
- */
-void utils_sha1_update(iot_sha1_context *ctx, const unsigned char *input, size_t ilen)
-{
-    size_t fill;
-    uint32_t left;
-
-    if (ilen == 0) {
-        return;
-    }
-
-    left = ctx->total[0] & 0x3F;
-    fill = 64 - left;
-
-    ctx->total[0] += (uint32_t) ilen;
-    ctx->total[0] &= 0xFFFFFFFF;
-
-    if (ctx->total[0] < (uint32_t) ilen) {
-        ctx->total[1]++;
-    }
-
-    if (left && ilen >= fill) {
-        memcpy((void *)(ctx->buffer + left), input, fill);
-        utils_sha1_process(ctx, ctx->buffer);
-        input += fill;
-        ilen  -= fill;
-        left = 0;
-    }
-
-    while (ilen >= 64) {
-        utils_sha1_process(ctx, input);
-        input += 64;
-        ilen  -= 64;
-    }
-
-    if (ilen > 0) {
-        memcpy((void *)(ctx->buffer + left), input, ilen);
-    }
-}
-
-static const unsigned char iot_sha1_padding[64] = {
-    0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
-};
-
-/*
- * SHA-1 final digest
- */
-void utils_sha1_finish(iot_sha1_context *ctx, unsigned char output[20])
-{
-    uint32_t last, padn;
-    uint32_t high, low;
-    unsigned char msglen[8];
-
-    high = (ctx->total[0] >> 29)
-           | (ctx->total[1] <<  3);
-    low  = (ctx->total[0] <<  3);
-
-    IOT_SHA1_PUT_UINT32_BE(high, msglen, 0);
-    IOT_SHA1_PUT_UINT32_BE(low,  msglen, 4);
-
-    last = ctx->total[0] & 0x3F;
-    padn = (last < 56) ? (56 - last) : (120 - last);
-
-    utils_sha1_update(ctx, iot_sha1_padding, padn);
-    utils_sha1_update(ctx, msglen, 8);
-
-    IOT_SHA1_PUT_UINT32_BE(ctx->state[0], output,  0);
-    IOT_SHA1_PUT_UINT32_BE(ctx->state[1], output,  4);
-    IOT_SHA1_PUT_UINT32_BE(ctx->state[2], output,  8);
-    IOT_SHA1_PUT_UINT32_BE(ctx->state[3], output, 12);
-    IOT_SHA1_PUT_UINT32_BE(ctx->state[4], output, 16);
-}
-
-
-/*
- * output = SHA-1( input buffer )
- */
-void utils_sha1(const unsigned char *input, size_t ilen, unsigned char output[20])
-{
-    iot_sha1_context ctx;
-
-    utils_sha1_init(&ctx);
-    utils_sha1_starts(&ctx);
-    utils_sha1_update(&ctx, input, ilen);
-    utils_sha1_finish(&ctx, output);
-    utils_sha1_free(&ctx);
-}
-
-#endif
diff --git a/bsp/bl808/m0/libraries/utils/src/utils_sha256.c b/bsp/bl808/m0/libraries/utils/src/utils_sha256.c
deleted file mode 100644
index 98b4e2d28d..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/utils_sha256.c
+++ /dev/null
@@ -1,299 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include 
-#include 
-#include 
-#include "utils_sha256.h"
-
-#define SHA256_KEY_IOPAD_SIZE (64)
-#define SHA256_DIGEST_SIZE    (32)
-
-/*
- * 32-bit integer manipulation macros (big endian)
- */
-#ifndef GET_UINT32_BE
-#define GET_UINT32_BE(n,b,i)                            \
-    do {                                                    \
-        (n) = ( (uint32_t) (b)[(i)    ] << 24 )             \
-              | ( (uint32_t) (b)[(i) + 1] << 16 )             \
-              | ( (uint32_t) (b)[(i) + 2] <<  8 )             \
-              | ( (uint32_t) (b)[(i) + 3]       );            \
-    } while( 0 )
-#endif
-
-#ifndef PUT_UINT32_BE
-#define PUT_UINT32_BE(n,b,i)                            \
-    do {                                                    \
-        (b)[(i)    ] = (unsigned char) ( (n) >> 24 );       \
-        (b)[(i) + 1] = (unsigned char) ( (n) >> 16 );       \
-        (b)[(i) + 2] = (unsigned char) ( (n) >>  8 );       \
-        (b)[(i) + 3] = (unsigned char) ( (n)       );       \
-    } while( 0 )
-#endif
-
-
-static void utils_sha256_zeroize(void *v, uint32_t n)
-{
-    volatile unsigned char *p = v;
-    while (n--) {
-        *p++ = 0;
-    }
-}
-void utils_sha256_init(iot_sha256_context *ctx)
-{
-    memset(ctx, 0, sizeof(iot_sha256_context));
-}
-void utils_sha256_free(iot_sha256_context *ctx)
-{
-    if (NULL == ctx) {
-        return;
-    }
-
-    utils_sha256_zeroize(ctx, sizeof(iot_sha256_context));
-}
-void utils_sha256_clone(iot_sha256_context *dst,
-                        const iot_sha256_context *src)
-{
-    *dst = *src;
-}
-void utils_sha256_starts(iot_sha256_context *ctx)
-{
-    int is224 = 0;
-    ctx->total[0] = 0;
-    ctx->total[1] = 0;
-
-    if (is224 == 0) {
-        /* SHA-256 */
-        ctx->state[0] = 0x6A09E667;
-        ctx->state[1] = 0xBB67AE85;
-        ctx->state[2] = 0x3C6EF372;
-        ctx->state[3] = 0xA54FF53A;
-        ctx->state[4] = 0x510E527F;
-        ctx->state[5] = 0x9B05688C;
-        ctx->state[6] = 0x1F83D9AB;
-        ctx->state[7] = 0x5BE0CD19;
-    }
-
-    ctx->is224 = is224;
-}
-
-static const uint32_t K[] = {
-    0x428A2F98, 0x71374491, 0xB5C0FBCF, 0xE9B5DBA5,
-    0x3956C25B, 0x59F111F1, 0x923F82A4, 0xAB1C5ED5,
-    0xD807AA98, 0x12835B01, 0x243185BE, 0x550C7DC3,
-    0x72BE5D74, 0x80DEB1FE, 0x9BDC06A7, 0xC19BF174,
-    0xE49B69C1, 0xEFBE4786, 0x0FC19DC6, 0x240CA1CC,
-    0x2DE92C6F, 0x4A7484AA, 0x5CB0A9DC, 0x76F988DA,
-    0x983E5152, 0xA831C66D, 0xB00327C8, 0xBF597FC7,
-    0xC6E00BF3, 0xD5A79147, 0x06CA6351, 0x14292967,
-    0x27B70A85, 0x2E1B2138, 0x4D2C6DFC, 0x53380D13,
-    0x650A7354, 0x766A0ABB, 0x81C2C92E, 0x92722C85,
-    0xA2BFE8A1, 0xA81A664B, 0xC24B8B70, 0xC76C51A3,
-    0xD192E819, 0xD6990624, 0xF40E3585, 0x106AA070,
-    0x19A4C116, 0x1E376C08, 0x2748774C, 0x34B0BCB5,
-    0x391C0CB3, 0x4ED8AA4A, 0x5B9CCA4F, 0x682E6FF3,
-    0x748F82EE, 0x78A5636F, 0x84C87814, 0x8CC70208,
-    0x90BEFFFA, 0xA4506CEB, 0xBEF9A3F7, 0xC67178F2,
-};
-
-#define  SHR(x,n) ((x & 0xFFFFFFFF) >> n)
-#define ROTR(x,n) (SHR(x,n) | (x << (32 - n)))
-
-#define S0(x) (ROTR(x, 7) ^ ROTR(x,18) ^  SHR(x, 3))
-#define S1(x) (ROTR(x,17) ^ ROTR(x,19) ^  SHR(x,10))
-
-#define S2(x) (ROTR(x, 2) ^ ROTR(x,13) ^ ROTR(x,22))
-#define S3(x) (ROTR(x, 6) ^ ROTR(x,11) ^ ROTR(x,25))
-
-#define F0(x,y,z) ((x & y) | (z & (x | y)))
-#define F1(x,y,z) (z ^ (x & (y ^ z)))
-
-#define R(t)                                    \
-    (                                               \
-            W[t] = S1(W[t -  2]) + W[t -  7] +          \
-                   S0(W[t - 15]) + W[t - 16]            \
-    )
-
-#define P(a,b,c,d,e,f,g,h,x,K)                  \
-    {                                               \
-        temp1 = h + S3(e) + F1(e,f,g) + K + x;      \
-        temp2 = S2(a) + F0(a,b,c);                  \
-        d += temp1; h = temp1 + temp2;              \
-    }
-
-void utils_sha256_process(iot_sha256_context *ctx, const unsigned char data[64])
-{
-    uint32_t temp1, temp2, W[64];
-    uint32_t A[8];
-    unsigned int i;
-
-    for (i = 0; i < 8; i++) {
-        A[i] = ctx->state[i];
-    }
-
-#if defined(INFRA_SHA256_SMALLER)
-    for (i = 0; i < 64; i++) {
-        if (i < 16) {
-            GET_UINT32_BE(W[i], data, 4 * i);
-        } else {
-            R(i);
-        }
-
-        P(A[0], A[1], A[2], A[3], A[4], A[5], A[6], A[7], W[i], K[i]);
-
-        temp1 = A[7];
-        A[7] = A[6];
-        A[6] = A[5];
-        A[5] = A[4];
-        A[4] = A[3];
-        A[3] = A[2];
-        A[2] = A[1];
-        A[1] = A[0];
-        A[0] = temp1;
-    }
-#else /* INFRA_SHA256_SMALLER */
-    for (i = 0; i < 16; i++) {
-        GET_UINT32_BE(W[i], data, 4 * i);
-    }
-
-    for (i = 0; i < 16; i += 8) {
-        P(A[0], A[1], A[2], A[3], A[4], A[5], A[6], A[7], W[i + 0], K[i + 0]);
-        P(A[7], A[0], A[1], A[2], A[3], A[4], A[5], A[6], W[i + 1], K[i + 1]);
-        P(A[6], A[7], A[0], A[1], A[2], A[3], A[4], A[5], W[i + 2], K[i + 2]);
-        P(A[5], A[6], A[7], A[0], A[1], A[2], A[3], A[4], W[i + 3], K[i + 3]);
-        P(A[4], A[5], A[6], A[7], A[0], A[1], A[2], A[3], W[i + 4], K[i + 4]);
-        P(A[3], A[4], A[5], A[6], A[7], A[0], A[1], A[2], W[i + 5], K[i + 5]);
-        P(A[2], A[3], A[4], A[5], A[6], A[7], A[0], A[1], W[i + 6], K[i + 6]);
-        P(A[1], A[2], A[3], A[4], A[5], A[6], A[7], A[0], W[i + 7], K[i + 7]);
-    }
-
-    for (i = 16; i < 64; i += 8) {
-        P(A[0], A[1], A[2], A[3], A[4], A[5], A[6], A[7], R(i + 0), K[i + 0]);
-        P(A[7], A[0], A[1], A[2], A[3], A[4], A[5], A[6], R(i + 1), K[i + 1]);
-        P(A[6], A[7], A[0], A[1], A[2], A[3], A[4], A[5], R(i + 2), K[i + 2]);
-        P(A[5], A[6], A[7], A[0], A[1], A[2], A[3], A[4], R(i + 3), K[i + 3]);
-        P(A[4], A[5], A[6], A[7], A[0], A[1], A[2], A[3], R(i + 4), K[i + 4]);
-        P(A[3], A[4], A[5], A[6], A[7], A[0], A[1], A[2], R(i + 5), K[i + 5]);
-        P(A[2], A[3], A[4], A[5], A[6], A[7], A[0], A[1], R(i + 6), K[i + 6]);
-        P(A[1], A[2], A[3], A[4], A[5], A[6], A[7], A[0], R(i + 7), K[i + 7]);
-    }
-#endif /* INFRA_SHA256_SMALLER */
-
-    for (i = 0; i < 8; i++) {
-        ctx->state[i] += A[i];
-    }
-}
-void utils_sha256_update(iot_sha256_context *ctx, const unsigned char *input, uint32_t ilen)
-{
-    size_t fill;
-    uint32_t left;
-
-    if (ilen == 0) {
-        return;
-    }
-
-    left = ctx->total[0] & 0x3F;
-    fill = 64 - left;
-
-    ctx->total[0] += (uint32_t) ilen;
-    ctx->total[0] &= 0xFFFFFFFF;
-
-    if (ctx->total[0] < (uint32_t) ilen) {
-        ctx->total[1]++;
-    }
-
-    if (left && ilen >= fill) {
-        memcpy((void *)(ctx->buffer + left), input, fill);
-        utils_sha256_process(ctx, ctx->buffer);
-        input += fill;
-        ilen  -= fill;
-        left = 0;
-    }
-
-    while (ilen >= 64) {
-        utils_sha256_process(ctx, input);
-        input += 64;
-        ilen  -= 64;
-    }
-
-    if (ilen > 0) {
-        memcpy((void *)(ctx->buffer + left), input, ilen);
-    }
-}
-
-static const unsigned char sha256_padding[64] = {
-    0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
-};
-
-void utils_sha256_finish(iot_sha256_context *ctx, uint8_t output[32])
-{
-    uint32_t last, padn;
-    uint32_t high, low;
-    unsigned char msglen[8];
-
-    high = (ctx->total[0] >> 29)
-           | (ctx->total[1] <<  3);
-    low  = (ctx->total[0] <<  3);
-
-    PUT_UINT32_BE(high, msglen, 0);
-    PUT_UINT32_BE(low,  msglen, 4);
-
-    last = ctx->total[0] & 0x3F;
-    padn = (last < 56) ? (56 - last) : (120 - last);
-
-    utils_sha256_update(ctx, sha256_padding, padn);
-    utils_sha256_update(ctx, msglen, 8);
-
-    PUT_UINT32_BE(ctx->state[0], output,  0);
-    PUT_UINT32_BE(ctx->state[1], output,  4);
-    PUT_UINT32_BE(ctx->state[2], output,  8);
-    PUT_UINT32_BE(ctx->state[3], output, 12);
-    PUT_UINT32_BE(ctx->state[4], output, 16);
-    PUT_UINT32_BE(ctx->state[5], output, 20);
-    PUT_UINT32_BE(ctx->state[6], output, 24);
-
-    if (ctx->is224 == 0) {
-        PUT_UINT32_BE(ctx->state[7], output, 28);
-    }
-}
-
-void utils_sha256(const uint8_t *input, uint32_t ilen, uint8_t output[32])
-{
-    iot_sha256_context ctx;
-
-    utils_sha256_init(&ctx);
-    utils_sha256_starts(&ctx);
-    utils_sha256_update(&ctx, input, ilen);
-    utils_sha256_finish(&ctx, output);
-    utils_sha256_free(&ctx);
-}
diff --git a/bsp/bl808/m0/libraries/utils/src/utils_string.c b/bsp/bl808/m0/libraries/utils/src/utils_string.c
deleted file mode 100644
index e6af56d1bd..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/utils_string.c
+++ /dev/null
@@ -1,427 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include 
-#include 
-#include 
-#include 
-#include 
-
-static int params_filter(char** params,uint32_t *r)
-{
-    char *p ;
-    uint32_t result=0;
-    uint8_t base=0;
-
-    p = *params;
-
-    if((*p == '0') && ((*(p+1) == 'x') || (*(p+1) == 'X')) ){
-        p = p + 2;
-        base = 16;
-
-    }else{
-        base = 10;
-    }
-
-    while(*p){
-        result *= base;
-        if(*p >= '0' && *p<='9')
-            result += *p-'0';
-        else if(base==10)
-            return -1;
-
-        if(base==16){
-            if(*p >= 'a' && *p<='f')
-                result += *p-'a' + 10;
-            else if(*p >= 'A' && *p<='F')
-                result += *p-'A' + 10;
-
-        }
-        p++;
-    }
-
-    *r = result;
-    return 0;
-
-}
-
-
-void get_bytearray_from_string(char** params, uint8_t *result,int array_size)
-{
-
-    int i = 0;
-    char rand[3];
-
-    for(i=0; i < array_size; i++){
-        strncpy(rand, (const char*)*params, 2);
-        rand[2]='\0';
-        result[i] = strtol(rand, NULL, 16);
-        *params = *params + 2;
-    }
-}
-
-void get_uint8_from_string(char** params, uint8_t *result)
-{
-    uint32_t p = 0;
-    int state=0;
-
-    state = params_filter(params,&p);
-    if(!state){
-        *result = p & 0xff;
-    }else
-        *result = 0;
-}
-
-void get_uint16_from_string(char** params, uint16_t *result)
-{
-    uint32_t p = 0;
-    int state=0;
-
-    state = params_filter(params,&p);
-    if(!state){
-        *result = p & 0xffff;
-    }else
-        *result = 0;
-}
-
-void get_uint32_from_string(char** params, uint32_t *result)
-{
-    uint32_t p = 0;
-    int state=0;
-
-    state = params_filter(params,&p);
-    if(!state){
-        *result = p;
-    }else
-        *result = 0;
-}
-
-void utils_parse_number(const char *str, char sep, uint8_t *buf, int buflen, int base)
-{
-  int i;
-  for (i = 0; i < buflen; i++) {
-    buf[i] = (uint8_t)strtol(str, NULL, base);
-    str = strchr(str, sep);
-    if (str == NULL || *str == '\0') {
-      break;
-    }
-    str++;
-  }
-}
-
-void utils_parse_number_adv(const char *str, char sep, uint8_t *buf, int buflen, int base, int *count)
-{
-  int i;
-
-  for (i = 0; i < buflen; i++) {
-    buf[i] = (uint8_t)strtol(str, NULL, base);
-    str = strchr(str, sep);
-    if (str == NULL || *str == '\0') {
-      break;
-    }
-    str++;
-  }
-  *count = (i + 1);
-}
-
-
-unsigned long long convert_arrayToU64(uint8_t* inputArray)
-{
-    unsigned long long result = 0;
-    for(uint8_t i = 0; i < 8; i++)
-    {
-        result <<= 8;
-        result |= (unsigned long long)inputArray[7-i];
-    }
-
-    return result;
-}
-
-void convert_u64ToArray(unsigned long long inputU64, uint8_t result[8])
-{
-    for(int i = 0; i < 8; i++)
-    {
-        result[i] = inputU64>>(i*8);
-    }
-}
-
-void utils_memcpy8(void *dst, void *src, size_t len)
-{
-    uint8_t *d = (uint8_t *)dst;
-    uint8_t *s = (uint8_t *)src;
-
-    while (len--) {
-        *d++ = *s++;
-    }
-}
-
-void utils_memcpy16(void *dst, void *src, size_t len)
-{
-    uint16_t *d = (uint16_t *)dst;
-    uint16_t *s = (uint16_t *)src;
-
-    len >>= 1;//convert to half words
-
-    while (len--) {
-        *d++ = *s++;
-    }
-}
-
-void utils_memcpy32(void *dst, void *src, size_t len)
-{
-    uint32_t *d = (uint32_t *)dst;
-    uint32_t *s = (uint32_t *)src;
-
-    len >>= 2;//convert to words
-
-    while (len--) {
-        *d++ = *s++;
-    }
-}
-
-void utils_memcpy64(void *dst, void *src, size_t len)
-{
-    uint64_t *d = (uint64_t *)dst;
-    uint64_t *s = (uint64_t *)src;
-
-    len >>= 3;//convert to two words
-
-    while (len--) {
-        *d++ = *s++;
-    }
-}
-
-void utils_memset8(void *src, uint8_t n, size_t len)
-{
-    uint8_t *s = (uint8_t *)src;
-
-    while (len--) {
-        *s++ = n;
-    }
-}
-
-void utils_memset16(void *src, uint16_t n, size_t len)
-{
-    uint16_t *s = (uint16_t *)src;
-
-    len >>= 1;//convert to half words
-
-    while (len--) {
-        *s++ = n;
-    }
-}
-
-void utils_memset32(void *src, uint32_t n, size_t len)
-{
-    uint32_t *s = (uint32_t *)src;
-
-    len >>= 2;//convert to words
-
-    while (len--) {
-        *s++ = n;
-    }
-}
-
-void utils_memset64(void *src, uint64_t n, size_t len)
-{
-    uint64_t *s = (uint64_t *)src;
-
-    len >>= 3;//convert to two words
-
-    while (len--) {
-        *s++ = n;
-    }
-}
-
-void utils_memset8_with_seq(void *src, uint8_t seq, size_t len)
-{
-    uint8_t *s = (uint8_t *)src;
-
-    while (len--) {
-        *s++ = (seq++);
-    }
-}
-
-void utils_memset16_with_seq(void *src, uint16_t seq, size_t len)
-{
-    uint16_t *s = (uint16_t *)src;
-
-    len >>= 1;//convert to half words
-
-    while (len--) {
-        *s++ = (seq++);
-    }
-}
-
-void utils_memset32_with_seq(void *src, uint32_t seq, size_t len)
-{
-    uint32_t *s = (uint32_t *)src;
-
-    len >>= 2;//convert to words
-
-    while (len--) {
-        *s++ = (seq++);
-    }
-}
-
-void utils_memset64_with_seq(void *src, uint64_t seq, size_t len)
-{
-    uint64_t *s = (uint64_t *)src;
-
-    len >>= 3;//convert to two words
-
-    while (len--) {
-        *s++ = (seq++);
-    }
-}
-
-void utils_memdrain8(void *src, size_t len)
-{
-    volatile uint8_t *s = (uint8_t *)src;
-    uint8_t tmp;
-
-    while (len--) {
-        tmp = *s++;
-    }
-
-    (void)tmp;
-}
-
-void utils_memdrain16(void *src, size_t len)
-{
-    volatile uint16_t *s = (uint16_t *)src;
-    uint16_t tmp;
-
-    len >>= 1;//convert to half words
-
-    while (len--) {
-        tmp = *s++;
-    }
-
-    (void)tmp;
-}
-
-void utils_memdrain32(void *src, size_t len)
-{
-    volatile uint32_t *s = (uint32_t *)src;
-    uint32_t tmp;
-
-    len >>= 2;//convert to words
-
-    while (len--) {
-        tmp = *s++;
-    }
-
-    (void)tmp;
-}
-
-void utils_memdrain64(void *src, size_t len)
-{
-    volatile uint64_t *s = (uint64_t *)src;
-    uint64_t tmp;
-
-    len >>= 3;//convert to two words
-
-    while (len--) {
-        tmp = *s++;
-    }
-
-    (void)tmp;
-}
-
-void * utils_memdrain8_with_check(void *src, size_t len, uint8_t seq)
-{
-    volatile uint8_t *s = (uint8_t *)src;
-    uint8_t tmp;
-
-    (void)tmp;
-
-    while (len--) {
-        tmp = *s++;
-        if((seq++) != tmp){
-            return (uint8_t *)s-1;
-        }
-    }
-
-    return NULL;
-}
-
-void * utils_memdrain16_with_check(void *src, size_t len, uint16_t seq)
-{
-    volatile uint16_t *s = (uint16_t *)src;
-    uint16_t tmp;
-    (void)tmp;
-
-    len >>= 1;//convert to half words
-
-    while (len--) {
-        tmp = *s++;
-        if((seq++) != tmp){
-            return (uint16_t *)s-1;
-        }
-    }
-
-    return NULL;
-}
-
-void * utils_memdrain32_with_check(void *src, size_t len, uint32_t seq)
-{
-    volatile uint32_t *s = (uint32_t *)src;
-    uint32_t tmp;
-    (void)tmp;
-
-    len >>= 2;//convert to words
-
-    while (len--) {
-        tmp = *s++;
-        if((seq++) != tmp){
-            return (uint32_t *)s-1;
-        }
-    }
-
-    return NULL;
-}
-
-void * utils_memdrain64_with_check(void *src, size_t len, uint64_t seq)
-{
-    volatile uint64_t *s = (uint64_t *)src;
-    uint64_t tmp;
-    (void)tmp;
-
-    len >>= 3;//convert to two words
-
-    while (len--) {
-        tmp = *s++;
-        if((seq++) != tmp){
-            return (uint64_t *)s-1;
-        }
-    }
-
-    return NULL;
-}
diff --git a/bsp/bl808/m0/libraries/utils/src/utils_time.c b/bsp/bl808/m0/libraries/utils/src/utils_time.c
deleted file mode 100644
index 0e8dd1dd73..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/utils_time.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include 
-#include 
-//Thu=4, Fri=5, Sat=6, Sun=0, Mon=1, Tue=2, Wed=3
-
-int utils_time_date_from_epoch(unsigned int epoch, utils_time_date_t *date)
-{
-    int i;
-    unsigned short temp_days;
-    unsigned char month_days[12]={31,28,31,30,31,30,31,31,30,31,30,31};
-    unsigned char week_days[7] = {4,5,6,0,1,2,3};
-
-    date->leap_days = 0;
-    date->leap_year_ind = 0;
-
-    // Add or substract time zone here.
-    //epoch += 19800; //GMT +5:30 = +19800 seconds
-
-    date->ntp_second = epoch%60;
-    epoch /= 60;
-    date->ntp_minute = epoch%60;
-    epoch /= 60;
-    date->ntp_hour  = epoch%24;
-    epoch /= 24;
-
-    date->days_since_epoch = epoch;      //number of days since epoch
-    date->ntp_week_day = week_days[date->days_since_epoch%7];  //Calculating WeekDay
-
-    date->ntp_year = 1970 + (date->days_since_epoch/365); // ball parking year, may not be accurate!
-    for (i = 1972, date->leap_days = 0; i < date->ntp_year; i+=4) {
-        // Calculating number of leap days since epoch/1970
-        if(((i%4==0) && (i%100!=0)) || (i%400==0)) {
-            date->leap_days++;
-        }
-    }
-
-    date->ntp_year = 1970 + ((date->days_since_epoch - date->leap_days)/365); // Calculating accurate current year by (days_since_epoch - extra leap days)
-    if (((date->ntp_year%4==0) && (date->ntp_year%100!=0)) || (date->ntp_year%400==0))  {
-        month_days[1]=29;     //February = 29 days for leap years
-        date->leap_year_ind = 1;    //if current year is leap, set indicator to 1
-    } else {
-        month_days[1]=28; //February = 28 days for non-leap years
-        date->leap_year_ind = 0;    //if current year is leap, set indicator to 1
-    }
-    for (i = 1972, date->leap_days = 0; i < date->ntp_year; i+=4) {
-        // Calculating number of leap days since epoch/1970
-        if(((i%4==0) && (i%100!=0)) || (i%400==0)) {
-            date->leap_days++;
-        }
-    }
-    date->day_of_year = date->days_since_epoch - date->leap_days - (date->ntp_year - 1970) * 365 + 1;
-
-
-    temp_days = 0;
-
-    for (date->ntp_month = 0; date->ntp_month <= 11; date->ntp_month++) {
-        //calculating current Month
-        if (date->day_of_year <= temp_days) {
-            break;
-        }
-        temp_days = temp_days + month_days[date->ntp_month];
-    }
-
-    temp_days = temp_days - month_days[date->ntp_month-1]; //calculating current Date
-    date->ntp_date = date->day_of_year - temp_days;
-
-    return 0;
-}
diff --git a/bsp/bl808/m0/libraries/utils/src/utils_tlv_bl.c b/bsp/bl808/m0/libraries/utils/src/utils_tlv_bl.c
deleted file mode 100644
index 0ec23c4daa..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/utils_tlv_bl.c
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include "utils_tlv_bl.h"
-
-int utils_tlv_bl_pack_bool(uint32_t *buf, int buf_sz, bool val)
-{
-    if (buf_sz < CFG_ELEMENT_TYPE_SIZE_BOOLEAN) {
-        return UTILS_TLV_BL_ERROR_CODE_BUF_TOO_SMALL;
-    }
-    *buf = val;//XXX caution for unaligned access
-
-    return CFG_ELEMENT_TYPE_SIZE_BOOLEAN;
-}
-
-int utils_tlv_bl_pack_uint32(uint32_t *buf, int buf_sz, uint32_t val)
-{
-    if (buf_sz < CFG_ELEMENT_TYPE_SIZE_UINT32) {
-        return UTILS_TLV_BL_ERROR_CODE_BUF_TOO_SMALL;
-    }
-    *buf = val;//XXX caution for unaligned access
-
-    return CFG_ELEMENT_TYPE_SIZE_UINT32;
-}
-
-int utils_tlv_bl_unpack_bool(uint32_t *buf, int buf_sz, bool *val)
-{
-    if (buf_sz < CFG_ELEMENT_TYPE_SIZE_BOOLEAN) {
-        return UTILS_TLV_BL_ERROR_CODE_BUF_TOO_SMALL;
-    }
-    *val = (*buf) ? true : false;// XXX caution for unaligned access
-
-    return CFG_ELEMENT_TYPE_SIZE_BOOLEAN;
-}
-
-int utils_tlv_bl_unpack_uint32(uint32_t *buf, int buf_sz, uint32_t *val)
-{
-    if (buf_sz < CFG_ELEMENT_TYPE_SIZE_UINT32) {
-        return UTILS_TLV_BL_ERROR_CODE_BUF_TOO_SMALL;
-    }
-    *val = (*buf);//XXX caution for unaligned access
-
-    return CFG_ELEMENT_TYPE_SIZE_BOOLEAN;
-}
-
-int utils_tlv_bl_pack_auto(uint32_t *buf, int buf_sz, uint16_t type, void *arg1)
-{
-    int ret = UTILS_TLV_BL_ERROR_CODE_UNKOWN;
-
-    switch (type) {
-        case CFG_ELEMENT_TYPE_BOOLEAN:
-        {
-            ret = utils_tlv_bl_pack_bool(buf, buf_sz, *(bool*)arg1 ? true : false);
-        }
-        break;
-        case CFG_ELEMENT_TYPE_SINT8:
-        {
-            //TODO
-        }
-        break;
-        case CFG_ELEMENT_TYPE_UINT8:
-        {
-            //TODO
-        }
-        break;
-        case CFG_ELEMENT_TYPE_SINT16:
-        {
-            //TODO
-        }
-        break;
-        case CFG_ELEMENT_TYPE_UINT16:
-        {
-            //TODO
-        }
-        break;
-        case CFG_ELEMENT_TYPE_SINT32:
-        {
-            //TODO
-        }
-        break;
-        case CFG_ELEMENT_TYPE_UINT32:
-        {
-            ret = utils_tlv_bl_pack_uint32(buf, buf_sz, *(uint32_t*)arg1);
-        }
-        break;
-        case CFG_ELEMENT_TYPE_STRING:
-        {
-            //TODO
-        }
-        break;
-        default:
-        {
-            /*empty*/
-        }
-    }
-
-    return ret;
-}
-
-int utils_tlv_bl_unpack_auto(uint32_t *buf, int buf_sz, uint16_t type, void *arg1)
-{
-    int ret = UTILS_TLV_BL_ERROR_CODE_UNKOWN;
-
-    switch (type) {
-        case CFG_ELEMENT_TYPE_BOOLEAN:
-        {
-            bool val = true;
-
-            ret = utils_tlv_bl_unpack_bool(buf, buf_sz, &val);
-            *(bool*)arg1 = val;
-        }
-        break;
-        case CFG_ELEMENT_TYPE_SINT8:
-        {
-            //TODO
-        }
-        break;
-        case CFG_ELEMENT_TYPE_UINT8:
-        {
-            //TODO
-        }
-        break;
-        case CFG_ELEMENT_TYPE_SINT16:
-        {
-            //TODO
-        }
-        break;
-        case CFG_ELEMENT_TYPE_UINT16:
-        {
-            //TODO
-        }
-        break;
-        case CFG_ELEMENT_TYPE_SINT32:
-        {
-            //TODO
-        }
-        break;
-        case CFG_ELEMENT_TYPE_UINT32:
-        {
-            uint32_t val = 0;
-
-            ret = utils_tlv_bl_unpack_uint32(buf, buf_sz, &val);
-            *(uint32_t*)arg1 = val;
-        }
-        break;
-        case CFG_ELEMENT_TYPE_STRING:
-        {
-            //TODO
-        }
-        break;
-        default:
-        {
-            /*empty*/
-        }
-    }
-
-    return ret;
-}
diff --git a/bsp/bl808/m0/link_stacksize.lds b/bsp/bl808/m0/link_stacksize.lds
deleted file mode 100644
index 28438c7da1..0000000000
--- a/bsp/bl808/m0/link_stacksize.lds
+++ /dev/null
@@ -1 +0,0 @@
-__STACKSIZE__ = 4096;
diff --git a/bsp/bouffalo_lab/.gitignore b/bsp/bouffalo_lab/.gitignore
new file mode 100755
index 0000000000..9b96be28e1
--- /dev/null
+++ b/bsp/bouffalo_lab/.gitignore
@@ -0,0 +1,8 @@
+*.ota
+*.xz
+*.xz.ota
+*.bin
+*.asm
+*.exe
+*-ubuntu
+*-macos
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/README.md b/bsp/bouffalo_lab/README.md
new file mode 100755
index 0000000000..e0d8600961
--- /dev/null
+++ b/bsp/bouffalo_lab/README.md
@@ -0,0 +1,193 @@
+# bouffalo_lab bsp
+
+## 1. 简介
+
+bouffalo_lab bsp针对bouffalo_lab的系列AIoT芯片，采用bouffalo_lab最新**LHAL** 驱动库，驱动库与[bl_mcu_sdk](https://github.com/bouffalolab/bl_mcu_sdk) 代码同步，当前commitid:`47c662afae69309fd49d2721b5c9b93219a91af7`
+
+目前支持以下芯片：
+
+|      | 芯片型号                 | 内核                                     |
+| ---- | :----------------------- | ---------------------------------------- |
+| 1    | bl60x(bl602/bl604)       | RISC-V SiFive E24                        |
+| 2    | bl70x(bl702/bl704/bl706) | RISC-V SiFive E24                        |
+| 3    | bl61x(bl616/bl618)       | RISC-V T-Head E907                       |
+| 4    | bl808                    | RISC-V T-Head E902(lp)+E907(m0)+C906(d0) |
+
+**LHAL** 是博流为统一通用外设接口而设计的驱动库，代码精炼并且支持博流所有系列芯片。
+
+|   外设   | BL602/BL604 | BL702/BL704/BL706 | BL616/BL618 | BL808 |
+| :------: | :---------: | :---------------: | :---------: | :---: |
+|   ADC    |      ○      |         √         |      √      |   ○   |
+|   CAM    |      -      |         ×         |      ×      |   ×   |
+|   CKS    |      ○      |         √         |      √      |   ○   |
+|   DAC    |      ○      |         √         |      √      |   ○   |
+|   DMA    |      ○      |         √         |      √      |   √   |
+|  EFUSE   |      ×      |         √         |      √      |   √   |
+|   EMAC   |      -      |         √         |      √      |   √   |
+|  FLASH   |      √      |         √         |      √      |   √   |
+|   GPIO   |      ○      |         √         |      √      |   √   |
+|   I2C    |      ○      |         √         |      √      |   ○   |
+|   I2S    |      ○      |         ○         |      √      |   ○   |
+|    IR    |      ○      |         √         |      √      |   ○   |
+|  MJPEG   |      ×      |         ×         |      √      |   √   |
+|  PWM_v1  |      ○      |         √         |      -      |   -   |
+|  PWM_v2  |      -      |         -         |      √      |   √   |
+|   RTC    |      ○      |         √         |      √      |   √   |
+| SEC_AES  |      ○      |         √         |      √      |   √   |
+| SEC_SHA  |      ○      |         √         |      √      |   √   |
+| SEC_TRNG |      ○      |         √         |      √      |   √   |
+| SEC_PKA  |      ○      |         √         |      √      |   √   |
+|   SPI    |      ○      |         √         |      √      |   √   |
+|  TIMER   |      ○      |         √         |      √      |   √   |
+|   UART   |      √      |         √         |      √      |   √   |
+|  USB_v1  |      -      |         √         |      -      |   -   |
+|  USB_v2  |      -      |         -         |      √      |   √   |
+|   WDG    |      ○      |         √         |      √      |   ○   |
+
+备注：**√** 表示已支持；**×** 表示未支持；**○** 表示已支持但未测试；**-** 表示没有该外设。
+
+
+
+## 2.  环境搭建及编译
+
+bl60x/bl70x/bl61x可在对应芯片直接编译；bl808是多核异构架构，分为m0、lp、d0（适配中，敬请期待），每个核需要单独编译并烧录到对应的位置。
+
+以下操作以bl61x为例，其他芯片操作类同。
+
+### 2.1. 下载
+
+请至对应下载链接下载芯片的工具链
+
+| 芯片型号    | 下载地址                                                     |
+| ----------- | ------------------------------------------------------------ |
+| bl60x/bl70x | [Linux](https://gitee.com/bouffalolab/toolchain_gcc_sifive_linux)/[windows](https://gitee.com/bouffalolab/toolchain_gcc_sifive_windows) |
+| bl61x/bl808 | [T-Head官网](https://occ.t-head.cn/community/download?id=4073475960903634944)或[Linux](https://gitee.com/bouffalolab/linuxtoolchain_gcc_t-head)/[windows](https://gitee.com/bouffalolab/toolchain_gcc_t-head_windows) |
+
+### 2.2. 设置
+
+Windows下请使用使用[env工具][1]，使用命令 `tar -xvf Xuantie-900-gcc-elf-newlib-mingw-V2.6.1-20220906.tar.gz` 解压交叉编译器，使用Windows下解压工具直接解压可能出现Windows下编译错误。
+
+在`rtconfig.py`中将risc-v工具链的本地路径加入 `EXEC_PATH` 或通过 `RTT_EXEC_PATH` 环境变量指定路径
+
+Windows：
+
+```
+set RTT_EXEC_PATH=C:\Users\xxxx\Downloads\Xuantie-900-gcc-elf-newlib-x86_64-V2.6.1\bin
+```
+
+Linux:
+
+```
+export RTT_EXEC_PATH=/opt/Xuantie-900-gcc-elf-newlib-x86_64-V2.6.1/bin
+```
+
+### 2.3. 编译
+
+Windows下推荐使用[env工具][1]，在console下进入bsp/bouffalo_lab/bl61x目录中，运行：
+
+    cd bsp/bouffalo_lab/bl61x
+    menuconfig
+    pkgs --update
+
+如果在Linux平台下，可以先执行：
+
+    scons --menuconfig
+
+它会自动下载env相关脚本到~/.env目录，然后执行
+
+    source ~/.env/env.sh
+    
+    cd bsp/bouffalo_lab/bl61x
+    pkgs --update
+
+更新完软件包后，执行 `scons -j10` 或 `scons -j10 --verbose` 来编译这个板级支持包。或者通过 `scons --exec-path="GCC工具链路径"` 命令，在指定工具链位置的同时直接编译。
+
+如果编译正确无误，会产生rtthread.elf、rtthread.bin文件；编译完成后自动调用`libraries/bl_mcu_sdk/tools/bflb_tools/bflb_fw_post_proc`对rtthread.bin进行打包处理以用于后续`bouffalo_flash_cube`工具烧录。
+
+脚本会自动采用curl命令行方式下载`bflb_fw_post_proc`，如自动下载失败，可采用手工方式下载对应操作系统文件后保存至`libraries/bl_mcu_sdk/tools/bflb_tools/bflb_fw_post_proc`
+
+[windows](https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc.exe)
+
+[Linux](https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc-ubuntu)
+
+[macos](https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc-macos)
+
+## 3. 下载烧录
+
+### 3.1. GUI方式下载
+
+当前bsp必须使用`bouffalo_flash_cube-1.0.4](https://pan.baidu.com/s/1eG9pkxf3riAqQAu9aXiOjw?pwd=miv1)工具进行烧录，否则无法正常运行。
+
+1. 连接好串口并在工具上选择对应的串口号
+
+2. 打开对应芯片文件夹下的flash_prog_cfg.ini文件
+
+3. 按住开发板上的boot按钮后重新上电，进入下载状态
+
+4. 点击"Download"开始下载
+
+![Flash Download](figures/bouffalo_flash_cube.jpg)
+
+### 3.2. 命令行下载
+
+或者可使用`bsp/bouffalo_lab`目录下的`bouffalo_flash_cube.sh`脚本通过命令行下载，输入`./`bouffalo_flash_cube.sh bl616 /dev/ttyUSB1`，使用前先确定脚本中bouffalo_flash_cube工具路径，需手工修改为工具所在目录。
+
+其中：
+
+- bl616：芯片名称
+- /dev/ttyUSB1：下载串口号，linux下为/dev/ttyUSBx或/dev/ttyACMx，windows下为COMx
+
+
+
+### 4.  运行
+
+如果编译 & 烧写无误，当复位设备后，会在串口上看到RT-Thread的启动logo信息：
+
+![terminal](figures/rt-thread.jpg)
+
+
+
+## 5. 支持开发板列表
+
+|       | 开发板型号             |
+| ----- | ---------------------- |
+| bl602 | BL602-IoT-3S/BL-HWC-G1 |
+| bl702 | Maix Zero Sense        |
+| bl616 | M0S Dock               |
+| bl808 | M1s Dock               |
+
+
+
+## 6. 驱动支持列表
+
+| 驱动 | 支持情况 | 备注              |
+| :--- | :------- | :---------------- |
+| UART | 支持     | 默认波特率2000000 |
+| GPIO | 支持     |                   |
+| I2C  | 开发中   |                   |
+| SPI  | 开发中   |                   |
+
+
+
+## 7. 联系人信息
+
+维护人：[flyingcys](https://github.com/flyingcys)
+
+
+
+## 8. 参考
+
+* 芯片[datasheet][2]
+
+  [1]: https://www.rt-thread.org/page/download.html
+  [2]: https://github.com/bouffalolab/bl_docs
+
+
+
+## 9. FAQ
+
+|      | M1s Dock                                                     |
+| ---- | :----------------------------------------------------------- |
+| 1    | 在 windows 环境下，通过 UART 接口将开发板连接至电脑时，仅能识别到两个 USB converter 设备，但是识别不到对应的串口设备。  
进入到设备管理器中，右击对应的 USB converter 设备，进入到属性中的高级设置，钩选 vcp 选项，刷新后即可看到对应的串口设备。
 也可通过安装以下驱动解决问题： https://dl.sipeed.com/shareURL/MAIX/tools/ftdi_vcp_driver |
+| 2    | 使用 TypeC 数据线将电脑与板子的 UART 口连接起来，此时电脑上会出现两个串口 （如果出现鼠标不能动的现象请拔掉 USB 并且查看 [更新板载 bl702 固件](https://wiki.sipeed.com/hardware/zh/maix/m1s/other/start.html#给板载-bl702-进行烧录) 相关内容来修复问题)。 |
+
diff --git a/bsp/bouffalo_lab/bl60x/.config b/bsp/bouffalo_lab/bl60x/.config
new file mode 100755
index 0000000000..a62ef1cdef
--- /dev/null
+++ b/bsp/bouffalo_lab/bl60x/.config
@@ -0,0 +1,1000 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Project Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=8
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=1000
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_HOOK_USING_FUNC_PTR=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=1024
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
+
+#
+# kservice optimization
+#
+CONFIG_RT_KSERVICE_USING_STDLIB=y
+# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_TINY_FFS is not set
+# CONFIG_RT_KPRINTF_USING_LONGLONG is not set
+CONFIG_RT_DEBUG=y
+# CONFIG_RT_DEBUG_COLOR is not set
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_PAGE_MAX_ORDER=11
+CONFIG_RT_USING_MEMPOOL=y
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMHEAP is not set
+CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_SLAB_AS_HEAP is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+# CONFIG_RT_USING_HEAP_ISR is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_DM is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
+CONFIG_RT_VER_NUM=0x50000
+# CONFIG_RT_USING_CACHE is not set
+# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+# CONFIG_RT_USING_CPU_FFS is not set
+CONFIG_ARCH_RISCV=y
+CONFIG_ARCH_RISCV_FPU=y
+CONFIG_ARCH_RISCV_FPU_S=y
+CONFIG_ARCH_RISCV32=y
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+# CONFIG_RT_USING_LEGACY is not set
+CONFIG_RT_USING_MSH=y
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_ARG_MAX=10
+# CONFIG_RT_USING_DFS is not set
+# CONFIG_RT_USING_FAL is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_UNAMED_PIPE_NUMBER=64
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_USING_SERIAL_V1=y
+# CONFIG_RT_USING_SERIAL_V2 is not set
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+# CONFIG_RT_USING_NULL is not set
+# CONFIG_RT_USING_ZERO is not set
+# CONFIG_RT_USING_RANDOM is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_FDT is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_LCD is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_DEV_BUS is not set
+# CONFIG_RT_USING_WIFI is not set
+# CONFIG_RT_USING_VIRTIO is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB is not set
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# C/C++ and POSIX layer
+#
+CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
+
+#
+# POSIX (Portable Operating System Interface) layer
+#
+# CONFIG_RT_USING_POSIX_FS is not set
+# CONFIG_RT_USING_POSIX_DELAY is not set
+# CONFIG_RT_USING_POSIX_CLOCK is not set
+# CONFIG_RT_USING_POSIX_TIMER is not set
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Interprocess Communication (IPC)
+#
+# CONFIG_RT_USING_POSIX_PIPE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
+
+#
+# Socket is in the 'Network' category
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Network
+#
+# CONFIG_RT_USING_SAL is not set
+# CONFIG_RT_USING_NETDEV is not set
+# CONFIG_RT_USING_LWIP is not set
+# CONFIG_RT_USING_AT is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_VAR_EXPORT is not set
+# CONFIG_RT_USING_ADT is not set
+# CONFIG_RT_USING_RT_LINK is not set
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LWIP is not set
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_EZ_IOT_OS is not set
+# CONFIG_PKG_USING_IOTSHARP_SDK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_RYANMQTT is not set
+# CONFIG_PKG_USING_RYANW5500 is not set
+# CONFIG_PKG_USING_LORA_PKT_FWD is not set
+# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
+# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
+# CONFIG_PKG_USING_HM is not set
+# CONFIG_PKG_USING_SMALL_MODBUS is not set
+# CONFIG_PKG_USING_NET_SERVER is not set
+# CONFIG_PKG_USING_ZFTP is not set
+# CONFIG_PKG_USING_WOL is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_LIBSODIUM is not set
+# CONFIG_PKG_USING_LIBHYDROGEN is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+
+#
+# language packages
+#
+
+#
+# JSON: JavaScript Object Notation, a lightweight data-interchange format
+#
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PARSON is not set
+
+#
+# XML: Extensible Markup Language
+#
+# CONFIG_PKG_USING_SIMPLE_XML is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_LUATOS_SOC is not set
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
+# CONFIG_PKG_USING_RTT_RUST is not set
+
+#
+# multimedia packages
+#
+
+#
+# LVGL: powerful and easy-to-use embedded GUI library
+#
+# CONFIG_PKG_USING_LVGL is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
+# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
+
+#
+# u8g2: a monochrome graphic library
+#
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+# CONFIG_PKG_USING_UGUI is not set
+
+#
+# PainterEngine: A cross-platform graphics application framework written in C language
+#
+# CONFIG_PKG_USING_PAINTERENGINE is not set
+# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_GUIENGINE is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
+# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+# CONFIG_PKG_USING_FDT is not set
+# CONFIG_PKG_USING_CBOX is not set
+# CONFIG_PKG_USING_SNOWFLAKE is not set
+# CONFIG_PKG_USING_HASH_MATCH is not set
+# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
+# CONFIG_PKG_USING_VOFA_PLUS is not set
+
+#
+# system packages
+#
+
+#
+# enhanced kernel services
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+
+#
+# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+#
+# CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_PERF_COUNTER is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+# CONFIG_PKG_USING_TINYUSB is not set
+# CONFIG_PKG_USING_CHERRYUSB is not set
+# CONFIG_PKG_USING_KMULTI_RTIMER is not set
+# CONFIG_PKG_USING_TFDB is not set
+# CONFIG_PKG_USING_QPC is not set
+# CONFIG_PKG_USING_AGILE_UPGRADE is not set
+# CONFIG_PKG_USING_FLASH_BLOB is not set
+
+#
+# peripheral libraries and drivers
+#
+
+#
+# sensors drivers
+#
+# CONFIG_PKG_USING_LSM6DSM is not set
+# CONFIG_PKG_USING_LSM6DSL is not set
+# CONFIG_PKG_USING_LPS22HB is not set
+# CONFIG_PKG_USING_HTS221 is not set
+# CONFIG_PKG_USING_LSM303AGR is not set
+# CONFIG_PKG_USING_BME280 is not set
+# CONFIG_PKG_USING_BME680 is not set
+# CONFIG_PKG_USING_BMA400 is not set
+# CONFIG_PKG_USING_BMI160_BMX160 is not set
+# CONFIG_PKG_USING_SPL0601 is not set
+# CONFIG_PKG_USING_MS5805 is not set
+# CONFIG_PKG_USING_DA270 is not set
+# CONFIG_PKG_USING_DF220 is not set
+# CONFIG_PKG_USING_HSHCAL001 is not set
+# CONFIG_PKG_USING_BH1750 is not set
+# CONFIG_PKG_USING_MPU6XXX is not set
+# CONFIG_PKG_USING_AHT10 is not set
+# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_TSL4531 is not set
+# CONFIG_PKG_USING_DS18B20 is not set
+# CONFIG_PKG_USING_DHT11 is not set
+# CONFIG_PKG_USING_DHTXX is not set
+# CONFIG_PKG_USING_GY271 is not set
+# CONFIG_PKG_USING_GP2Y10 is not set
+# CONFIG_PKG_USING_SGP30 is not set
+# CONFIG_PKG_USING_HDC1000 is not set
+# CONFIG_PKG_USING_BMP180 is not set
+# CONFIG_PKG_USING_BMP280 is not set
+# CONFIG_PKG_USING_SHTC1 is not set
+# CONFIG_PKG_USING_BMI088 is not set
+# CONFIG_PKG_USING_HMC5883 is not set
+# CONFIG_PKG_USING_MAX6675 is not set
+# CONFIG_PKG_USING_TMP1075 is not set
+# CONFIG_PKG_USING_SR04 is not set
+# CONFIG_PKG_USING_CCS811 is not set
+# CONFIG_PKG_USING_PMSXX is not set
+# CONFIG_PKG_USING_RT3020 is not set
+# CONFIG_PKG_USING_MLX90632 is not set
+# CONFIG_PKG_USING_MLX90393 is not set
+# CONFIG_PKG_USING_MLX90392 is not set
+# CONFIG_PKG_USING_MLX90397 is not set
+# CONFIG_PKG_USING_MS5611 is not set
+# CONFIG_PKG_USING_MAX31865 is not set
+# CONFIG_PKG_USING_VL53L0X is not set
+# CONFIG_PKG_USING_INA260 is not set
+# CONFIG_PKG_USING_MAX30102 is not set
+# CONFIG_PKG_USING_INA226 is not set
+# CONFIG_PKG_USING_LIS2DH12 is not set
+# CONFIG_PKG_USING_HS300X is not set
+# CONFIG_PKG_USING_ZMOD4410 is not set
+# CONFIG_PKG_USING_ISL29035 is not set
+# CONFIG_PKG_USING_MMC3680KJ is not set
+# CONFIG_PKG_USING_QMP6989 is not set
+# CONFIG_PKG_USING_BALANCE is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_ADT74XX is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_CW2015 is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_STHS34PF80 is not set
+
+#
+# touch drivers
+#
+# CONFIG_PKG_USING_GT9147 is not set
+# CONFIG_PKG_USING_GT1151 is not set
+# CONFIG_PKG_USING_GT917S is not set
+# CONFIG_PKG_USING_GT911 is not set
+# CONFIG_PKG_USING_FT6206 is not set
+# CONFIG_PKG_USING_FT5426 is not set
+# CONFIG_PKG_USING_FT6236 is not set
+# CONFIG_PKG_USING_XPT2046_TOUCH is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ESP_IDF is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+
+#
+# Kendryte SDK
+#
+# CONFIG_PKG_USING_K210_SDK is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_MULTI_INFRARED is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_NUCLEI_SDK is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
+# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
+# CONFIG_PKG_USING_BL_MCU_SDK is not set
+# CONFIG_PKG_USING_SOFT_SERIAL is not set
+# CONFIG_PKG_USING_MB85RS16 is not set
+# CONFIG_PKG_USING_RFM300 is not set
+# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
+# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
+# CONFIG_PKG_USING_FINGERPRINT is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+
+#
+# Signal Processing and Control Algorithm Packages
+#
+# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
+# CONFIG_PKG_USING_UKAL is not set
+
+#
+# miscellaneous packages
+#
+
+#
+# project laboratory
+#
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_HEATSHRINK is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
+# CONFIG_PKG_USING_MFBD is not set
+# CONFIG_PKG_USING_SLCAN2RTT is not set
+# CONFIG_PKG_USING_SOEM is not set
+# CONFIG_PKG_USING_QPARAM is not set
+# CONFIG_PKG_USING_CorevMCU_CLI is not set
+
+#
+# Arduino libraries
+#
+# CONFIG_PKG_USING_RTDUINO is not set
+
+#
+# Projects
+#
+# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
+# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
+
+#
+# Sensors
+#
+# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
+# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
+# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
+# CONFIG_PKG_USING_SEEED_ITG3200 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
+# CONFIG_PKG_USING_SEEED_MP503 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
+
+#
+# Display
+#
+# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
+# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set
+# CONFIG_PKG_USING_SEEED_TM1637 is not set
+
+#
+# Timing
+#
+# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
+
+#
+# Data Processing
+#
+# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
+# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
+
+#
+# Data Storage
+#
+
+#
+# Communication
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
+
+#
+# Device Control
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
+
+#
+# Other
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
+# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
+
+#
+# Signal IO
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
+
+#
+# Uncategorized
+#
+CONFIG_BSP_USING_BL60X=y
+CONFIG_BSP_USING_ROMAPI=y
+
+#
+# General Drivers Configuration
+#
+CONFIG_BSP_USING_GPIO=y
+
+#
+# General Purpose UARTs
+#
+CONFIG_BSP_USING_UART0=y
+# CONFIG_UART0_TX_USING_GPIO14 is not set
+CONFIG_UART0_TX_USING_GPIO16=y
+# CONFIG_UART0_TX_USING_GPIO21 is not set
+CONFIG_UART0_RX_USING_GPIO7=y
+# CONFIG_UART0_RX_USING_GPIO15 is not set
+# CONFIG_UART0_RX_USING_GPIO22 is not set
+# CONFIG_UART0_RX_USING_GPIO23 is not set
+CONFIG_BSP_USING_UART1=y
+CONFIG_UART1_TX_USING_GPIO4=y
+# CONFIG_UART1_TX_USING_GPIO16 is not set
+# CONFIG_UART1_TX_USING_GPIO18 is not set
+# CONFIG_UART1_TX_USING_GPIO26 is not set
+CONFIG_UART1_RX_USING_GPIO3=y
+# CONFIG_UART1_RX_USING_GPIO5 is not set
+# CONFIG_UART1_RX_USING_GPIO17 is not set
+# CONFIG_UART1_RX_USING_GPIO19 is not set
+# CONFIG_UART1_RX_USING_GPIO27 is not set
diff --git a/bsp/bl808/m0/Kconfig b/bsp/bouffalo_lab/bl60x/Kconfig
old mode 100644
new mode 100755
similarity index 68%
rename from bsp/bl808/m0/Kconfig
rename to bsp/bouffalo_lab/bl60x/Kconfig
index eaacad85ce..c6ee6e58f8
--- a/bsp/bl808/m0/Kconfig
+++ b/bsp/bouffalo_lab/bl60x/Kconfig
@@ -15,6 +15,12 @@ config PKGS_DIR
     option env="PKGS_ROOT"
     default "packages"
 
+config LIBRARIES_DIR
+    string
+    option env="LIBRARIES_DIR"
+    default "../libraries"
+
 source "$RTT_DIR/Kconfig"
 source "$PKGS_DIR/Kconfig"
-source "drivers/Kconfig"
+source "board/Kconfig"
+source "$LIBRARIES_DIR/Kconfig"
diff --git a/bsp/bl808/m0/SConscript b/bsp/bouffalo_lab/bl60x/SConscript
old mode 100644
new mode 100755
similarity index 100%
rename from bsp/bl808/m0/SConscript
rename to bsp/bouffalo_lab/bl60x/SConscript
diff --git a/bsp/bouffalo_lab/bl60x/SConstruct b/bsp/bouffalo_lab/bl60x/SConstruct
new file mode 100755
index 0000000000..da9ba9a91a
--- /dev/null
+++ b/bsp/bouffalo_lab/bl60x/SConstruct
@@ -0,0 +1,46 @@
+import os
+import sys
+import rtconfig
+
+from rtconfig import RTT_ROOT
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+env['ASCOM'] = env['ASPPCOM']
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+    libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False)
+
+# include libraries
+objs.extend(SConscript(libraries_path_prefix + '/bl_mcu_sdk/SConscript', variant_dir='build/libraries/bl_mcu_sdk', duplicate=0))
+
+# include drivers
+objs.extend(SConscript(libraries_path_prefix + '/rt_drivers/SConscript', variant_dir='build/libraries/rt_drivers', duplicate=0))
+
+
+# make a building
+DoBuilding(TARGET, objs)
diff --git a/bsp/bl808/m0/applications/SConscript b/bsp/bouffalo_lab/bl60x/applications/SConscript
old mode 100644
new mode 100755
similarity index 100%
rename from bsp/bl808/m0/applications/SConscript
rename to bsp/bouffalo_lab/bl60x/applications/SConscript
diff --git a/bsp/bouffalo_lab/bl60x/applications/main.c b/bsp/bouffalo_lab/bl60x/applications/main.c
new file mode 100644
index 0000000000..55495688b0
--- /dev/null
+++ b/bsp/bouffalo_lab/bl60x/applications/main.c
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023/03/25     flyingcys    first version
+ */
+
+#include 
+#include 
+
+int main(void)
+{
+    rt_kprintf("Hello, RISC-V!\n");
+
+    return 0;
+}
diff --git a/bsp/bouffalo_lab/bl60x/board/Kconfig b/bsp/bouffalo_lab/bl60x/board/Kconfig
new file mode 100755
index 0000000000..b25faf2847
--- /dev/null
+++ b/bsp/bouffalo_lab/bl60x/board/Kconfig
@@ -0,0 +1,12 @@
+config BSP_USING_BL60X
+    bool
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    select ARCH_RISCV32
+    select ARCH_RISCV_FPU_S
+    select BSP_USING_ROMAPI
+    default y
+
+config BSP_USING_ROMAPI
+    bool 
+    default y
diff --git a/bsp/bouffalo_lab/bl60x/board/SConscript b/bsp/bouffalo_lab/bl60x/board/SConscript
new file mode 100755
index 0000000000..c0653a14cc
--- /dev/null
+++ b/bsp/bouffalo_lab/bl60x/board/SConscript
@@ -0,0 +1,9 @@
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*.S')
+CPPPATH = [cwd]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/bouffalo_lab/bl60x/board/board.c b/bsp/bouffalo_lab/bl60x/board/board.c
new file mode 100644
index 0000000000..413a39bc32
--- /dev/null
+++ b/bsp/bouffalo_lab/bl60x/board/board.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023/03/15     flyingcys    first version
+ */
+#include 
+#include 
+
+#include "board.h"
+#include "drv_uart.h"
+
+static void system_clock_init(void)
+{
+    GLB_Set_System_CLK(GLB_PLL_XTAL_40M, GLB_SYS_CLK_PLL192M);
+    GLB_Set_MTimer_CLK(1, GLB_MTIMER_CLK_BCLK, 95);
+}
+
+static void peripheral_clock_init(void)
+{
+    PERIPHERAL_CLOCK_ADC_DAC_ENABLE();
+    PERIPHERAL_CLOCK_SEC_ENABLE();
+    PERIPHERAL_CLOCK_DMA0_ENABLE();
+    PERIPHERAL_CLOCK_UART0_ENABLE();
+    PERIPHERAL_CLOCK_UART1_ENABLE();
+    PERIPHERAL_CLOCK_SPI0_ENABLE();
+    PERIPHERAL_CLOCK_I2C0_ENABLE();
+    PERIPHERAL_CLOCK_PWM0_ENABLE();
+    PERIPHERAL_CLOCK_TIMER0_1_WDG_ENABLE();
+
+    GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_160M, 0);
+    GLB_Set_SPI_CLK(ENABLE, 0);
+    GLB_Set_I2C_CLK(ENABLE, 0);
+
+    GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, 1);
+    GLB_Set_DAC_CLK(ENABLE, GLB_DAC_CLK_XCLK, 0x3E);
+}
+
+/* This is the timer interrupt service routine. */
+static void systick_isr(void)
+{
+    rt_tick_increase();
+}
+
+void rt_hw_board_init(void)
+{
+    bflb_flash_init();
+
+    system_clock_init();
+    peripheral_clock_init();
+    bflb_irq_initialize();
+
+    bflb_mtimer_config(HW_MTIMER_CLOCK / RT_TICK_PER_SECOND, systick_isr);
+
+#ifdef RT_USING_HEAP
+    /* initialize memory system */
+    rt_kprintf("RT_HW_HEAP_BEGIN:%x RT_HW_HEAP_END:%x\r\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
+    rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
+#endif
+
+    /* UART driver initialization is open by default */
+#ifdef RT_USING_SERIAL
+    rt_hw_uart_init();
+#endif
+
+    /* Set the shell console output device */
+#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}
+
+void rt_hw_cpu_reset(void)
+{
+    GLB_SW_POR_Reset();
+}
+
+MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reset machine);
diff --git a/bsp/bouffalo_lab/bl60x/board/board.h b/bsp/bouffalo_lab/bl60x/board/board.h
new file mode 100644
index 0000000000..d58d575f33
--- /dev/null
+++ b/bsp/bouffalo_lab/bl60x/board/board.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022/03/15     flyingcys    first version
+ */
+
+#ifndef BOARD_H__
+#define BOARD_H__
+
+#include 
+
+#include "bflb_uart.h"
+#include "bflb_gpio.h"
+#include "bflb_clock.h"
+#include "bflb_rtc.h"
+#include "bflb_flash.h"
+#include "bl602_glb.h"
+
+#define     HW_MTIMER_CLOCK     1000000
+
+extern uint8_t __HeapBase;
+extern uint8_t __HeapLimit;
+
+#define RT_HW_HEAP_BEGIN    (void*)&__HeapBase
+#define RT_HW_HEAP_END      (void*)&__HeapLimit
+
+void rt_hw_board_init(void);
+
+#endif
diff --git a/bsp/bouffalo_lab/bl60x/board/builtin_imgs/boot2_bl602_debug_v8.0.7.bin b/bsp/bouffalo_lab/bl60x/board/builtin_imgs/boot2_bl602_debug_v8.0.7.bin
new file mode 100755
index 0000000000..28ee214554
Binary files /dev/null and b/bsp/bouffalo_lab/bl60x/board/builtin_imgs/boot2_bl602_debug_v8.0.7.bin differ
diff --git a/bsp/bouffalo_lab/bl60x/board/builtin_imgs/boot2_bl602_release_v8.0.7.bin b/bsp/bouffalo_lab/bl60x/board/builtin_imgs/boot2_bl602_release_v8.0.7.bin
new file mode 100755
index 0000000000..c3008f36d0
Binary files /dev/null and b/bsp/bouffalo_lab/bl60x/board/builtin_imgs/boot2_bl602_release_v8.0.7.bin differ
diff --git a/bsp/bouffalo_lab/bl60x/board/builtin_imgs/mfg_bl602_gu_33c89c10b_40m_autoboot_v2.71.bin b/bsp/bouffalo_lab/bl60x/board/builtin_imgs/mfg_bl602_gu_33c89c10b_40m_autoboot_v2.71.bin
new file mode 100755
index 0000000000..1e4262b22f
Binary files /dev/null and b/bsp/bouffalo_lab/bl60x/board/builtin_imgs/mfg_bl602_gu_33c89c10b_40m_autoboot_v2.71.bin differ
diff --git a/bsp/bouffalo_lab/bl60x/board/builtin_imgs/mfg_bl602_gu_33c89c10b_40m_v2.71.bin b/bsp/bouffalo_lab/bl60x/board/builtin_imgs/mfg_bl602_gu_33c89c10b_40m_v2.71.bin
new file mode 100755
index 0000000000..36bcc07cd5
Binary files /dev/null and b/bsp/bouffalo_lab/bl60x/board/builtin_imgs/mfg_bl602_gu_33c89c10b_40m_v2.71.bin differ
diff --git a/bsp/bouffalo_lab/bl60x/board/config/.gitkeep b/bsp/bouffalo_lab/bl60x/board/config/.gitkeep
new file mode 100755
index 0000000000..e69de29bb2
diff --git a/bsp/bouffalo_lab/bl60x/board/fw_header.c b/bsp/bouffalo_lab/bl60x/board/fw_header.c
new file mode 100644
index 0000000000..fdfbd8687b
--- /dev/null
+++ b/bsp/bouffalo_lab/bl60x/board/fw_header.c
@@ -0,0 +1,122 @@
+#include "fw_header.h"
+
+__attribute__((section(".fw_header"))) struct bootheader_t fw_header = {
+    .magiccode = 0x504e4642,
+    .rivison = 0x00000001,
+    /*flash config */
+    .flash_cfg.magiccode = 0x47464346,
+    .flash_cfg.cfg.ioMode = 0x11,               /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
+    .flash_cfg.cfg.cReadSupport = 0x00,         /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
+    .flash_cfg.cfg.clkDelay = 0x01,             /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
+    .flash_cfg.cfg.clkInvert = 0x01,            /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
+    .flash_cfg.cfg.resetEnCmd = 0x66,           /*!< Flash enable reset command */
+    .flash_cfg.cfg.resetCmd = 0x99,             /*!< Flash reset command */
+    .flash_cfg.cfg.resetCreadCmd = 0xff,        /*!< Flash reset continuous read command */
+    .flash_cfg.cfg.resetCreadCmdSize = 0x03,    /*!< Flash reset continuous read command size */
+    .flash_cfg.cfg.jedecIdCmd = 0x9f,           /*!< JEDEC ID command */
+    .flash_cfg.cfg.jedecIdCmdDmyClk = 0x00,     /*!< JEDEC ID command dummy clock */
+    .flash_cfg.cfg.enter32BitsAddrCmd = 0xb7,   /*!< Enter 32-bits addr command */
+    .flash_cfg.cfg.exit32BitsAddrCmd = 0xe9,    /*!< Exit 32-bits addr command */
+    .flash_cfg.cfg.sectorSize = 0x04,           /*!< *1024bytes */
+    .flash_cfg.cfg.mid = 0xff,                  /*!< Manufacturer ID */
+    .flash_cfg.cfg.pageSize = 0x100,            /*!< Page size */
+    .flash_cfg.cfg.chipEraseCmd = 0xc7,         /*!< Chip erase cmd */
+    .flash_cfg.cfg.sectorEraseCmd = 0x20,       /*!< Sector erase command */
+    .flash_cfg.cfg.blk32EraseCmd = 0x52,        /*!< Block 32K erase command,some Micron not support */
+    .flash_cfg.cfg.blk64EraseCmd = 0xd8,        /*!< Block 64K erase command */
+    .flash_cfg.cfg.writeEnableCmd = 0x06,       /*!< Need before every erase or program */
+    .flash_cfg.cfg.pageProgramCmd = 0x02,       /*!< Page program cmd */
+    .flash_cfg.cfg.qpageProgramCmd = 0x32,      /*!< QIO page program cmd */
+    .flash_cfg.cfg.qppAddrMode = 0x00,          /*!< QIO page program address mode */
+    .flash_cfg.cfg.fastReadCmd = 0x0b,          /*!< Fast read command */
+    .flash_cfg.cfg.frDmyClk = 0x01,             /*!< Fast read command dummy clock */
+    .flash_cfg.cfg.qpiFastReadCmd = 0x0b,       /*!< QPI fast read command */
+    .flash_cfg.cfg.qpiFrDmyClk = 0x01,          /*!< QPI fast read command dummy clock */
+    .flash_cfg.cfg.fastReadDoCmd = 0x3b,        /*!< Fast read dual output command */
+    .flash_cfg.cfg.frDoDmyClk = 0x01,           /*!< Fast read dual output command dummy clock */
+    .flash_cfg.cfg.fastReadDioCmd = 0xbb,       /*!< Fast read dual io comamnd */
+    .flash_cfg.cfg.frDioDmyClk = 0x00,          /*!< Fast read dual io command dummy clock */
+    .flash_cfg.cfg.fastReadQoCmd = 0x6b,        /*!< Fast read quad output comamnd */
+    .flash_cfg.cfg.frQoDmyClk = 0x01,           /*!< Fast read quad output comamnd dummy clock */
+    .flash_cfg.cfg.fastReadQioCmd = 0xeb,       /*!< Fast read quad io comamnd */
+    .flash_cfg.cfg.frQioDmyClk = 0x02,          /*!< Fast read quad io comamnd dummy clock */
+    .flash_cfg.cfg.qpiFastReadQioCmd = 0xeb,    /*!< QPI fast read quad io comamnd */
+    .flash_cfg.cfg.qpiFrQioDmyClk = 0x02,       /*!< QPI fast read QIO dummy clock */
+    .flash_cfg.cfg.qpiPageProgramCmd = 0x02,    /*!< QPI program command */
+    .flash_cfg.cfg.writeVregEnableCmd = 0x50,   /*!< Enable write reg */
+    .flash_cfg.cfg.wrEnableIndex = 0x00,        /*!< Write enable register index */
+    .flash_cfg.cfg.qeIndex = 0x01,              /*!< Quad mode enable register index */
+    .flash_cfg.cfg.busyIndex = 0x00,            /*!< Busy status register index */
+    .flash_cfg.cfg.wrEnableBit = 0x01,          /*!< Write enable bit pos */
+    .flash_cfg.cfg.qeBit = 0x01,                /*!< Quad enable bit pos */
+    .flash_cfg.cfg.busyBit = 0x00,              /*!< Busy status bit pos */
+    .flash_cfg.cfg.wrEnableWriteRegLen = 0x02,  /*!< Register length of write enable */
+    .flash_cfg.cfg.wrEnableReadRegLen = 0x01,   /*!< Register length of write enable status */
+    .flash_cfg.cfg.qeWriteRegLen = 0x02,        /*!< Register length of contain quad enable */
+    .flash_cfg.cfg.qeReadRegLen = 0x01,         /*!< Register length of contain quad enable status */
+    .flash_cfg.cfg.releasePowerDown = 0xab,     /*!< Release power down command */
+    .flash_cfg.cfg.busyReadRegLen = 0x01,       /*!< Register length of contain busy status */
+    .flash_cfg.cfg.readRegCmd[0] = 0x05,        /*!< Read register command buffer */
+    .flash_cfg.cfg.readRegCmd[1] = 0x35,        /*!< Read register command buffer */
+    .flash_cfg.cfg.readRegCmd[2] = 0x00,        /*!< Read register command buffer */
+    .flash_cfg.cfg.readRegCmd[3] = 0x00,        /*!< Read register command buffer */
+    .flash_cfg.cfg.writeRegCmd[0] = 0x01,       /*!< Write register command buffer */
+    .flash_cfg.cfg.writeRegCmd[1] = 0x01,       /*!< Write register command buffer */
+    .flash_cfg.cfg.writeRegCmd[2] = 0x00,       /*!< Write register command buffer */
+    .flash_cfg.cfg.writeRegCmd[3] = 0x00,       /*!< Write register command buffer */
+    .flash_cfg.cfg.enterQpi = 0x38,             /*!< Enter qpi command */
+    .flash_cfg.cfg.exitQpi = 0xff,              /*!< Exit qpi command */
+    .flash_cfg.cfg.cReadMode = 0xa0,            /*!< Config data for continuous read mode */
+    .flash_cfg.cfg.cRExit = 0xff,               /*!< Config data for exit continuous read mode */
+    .flash_cfg.cfg.burstWrapCmd = 0x77,         /*!< Enable burst wrap command */
+    .flash_cfg.cfg.burstWrapCmdDmyClk = 0x03,   /*!< Enable burst wrap command dummy clock */
+    .flash_cfg.cfg.burstWrapDataMode = 0x02,    /*!< Data and address mode for this command */
+    .flash_cfg.cfg.burstWrapData = 0x40,        /*!< Data to enable burst wrap */
+    .flash_cfg.cfg.deBurstWrapCmd = 0x77,       /*!< Disable burst wrap command */
+    .flash_cfg.cfg.deBurstWrapCmdDmyClk = 0x03, /*!< Disable burst wrap command dummy clock */
+    .flash_cfg.cfg.deBurstWrapDataMode = 0x02,  /*!< Data and address mode for this command */
+    .flash_cfg.cfg.deBurstWrapData = 0xf0,      /*!< Data to disable burst wrap */
+    .flash_cfg.cfg.timeEsector = 300,           /*!< 4K erase time */
+    .flash_cfg.cfg.timeE32k = 1200,             /*!< 32K erase time */
+    .flash_cfg.cfg.timeE64k = 1200,             /*!< 64K erase time */
+    .flash_cfg.cfg.timePagePgm = 50,            /*!< Page program time */
+    .flash_cfg.cfg.timeCe = 30000,              /*!< Chip erase time in ms */
+    .flash_cfg.cfg.pdDelay = 20,                /*!< Release power down command delay time for wake up */
+    .flash_cfg.cfg.qeData = 0,                  /*!< QE set data */
+    .flash_cfg.crc32 = 0xdeadbeef,
+    /* clock cfg */
+    .clk_cfg.magiccode = 0x47464350,
+    .clk_cfg.cfg.xtal_type = 0x04, /*!<  0:None,1:24M,2:32M,3:38.4M,4:40M,5:26M,6:RC32M  */
+    .clk_cfg.cfg.pll_clk = 0x04,   /*!< mcu_clk 0:RC32M,1:XTAL,2:PLL 48M,3:PLL 120M,4:PLL 160M,5:PLL 192M */
+    .clk_cfg.cfg.hclk_div = 0x00,
+    .clk_cfg.cfg.bclk_div = 0x01,
+    .clk_cfg.cfg.flash_clk_type = 0x03, /*!< 0:120M,1:XCLK(RC32M or XTAL),2:48M,3:80M,4:BCLK,5:96M */
+    .clk_cfg.cfg.flash_clk_div = 0x01,
+    .clk_cfg.crc32 = 0xdeadbeef,
+
+    /* boot cfg */
+    .boot_cfg.bval.sign = 0x0,               /* [1: 0]      for sign*/
+    .boot_cfg.bval.encrypt_type = 0x0,       /* [3: 2]      for encrypt */
+    .boot_cfg.bval.key_sel = 0x0,            /* [5: 4]      for key sel in boot interface*/
+    .boot_cfg.bval.rsvd6_7 = 0x0,            /* [7: 6]      for encrypt*/
+    .boot_cfg.bval.no_segment = 0x1,         /* [8]         no segment info */
+    .boot_cfg.bval.cache_select = 0x1,       /* [9]         for cache */
+    .boot_cfg.bval.notload_in_bootrom = 0x0, /* [10]        not load this img in bootrom */
+    .boot_cfg.bval.aes_region_lock = 0x0,    /* [11]        aes region lock */
+    .boot_cfg.bval.cache_way_disable = 0x3,  /* [15: 12]    cache way disable info*/
+    .boot_cfg.bval.crc_ignore = 0x1,         /* [16]        ignore crc */
+    .boot_cfg.bval.hash_ignore = 0x1,        /* [17]        hash crc */
+    .boot_cfg.bval.halt_ap = 0x0,            /* [18]        halt ap */
+    .boot_cfg.bval.rsvd19_31 = 0x0,          /* [31:19]     rsvd */
+
+    .img_segment_info.img_len = 0x00010000, /* image length or segment count */
+    .rsvd0 = 0x00000000,
+#ifdef BFLB_BOOT2
+    .img_start.flashoffset = 0x00002000, /* flash controller offset */
+#else
+    .img_start.flashoffset = 0x00001000, /* flash controller offset */
+#endif
+    .hash = { 0xdeadbeef },              /* hash of the image */
+
+    .crc32 = 0xdeadbeef /* 4 */
+};
diff --git a/bsp/bouffalo_lab/bl60x/board/fw_header.h b/bsp/bouffalo_lab/bl60x/board/fw_header.h
new file mode 100644
index 0000000000..b6746ad076
--- /dev/null
+++ b/bsp/bouffalo_lab/bl60x/board/fw_header.h
@@ -0,0 +1,168 @@
+#ifndef __FW_HEADER_H__
+#define __FW_HEADER_H__
+
+#include "stdint.h"
+#include "stdio.h"
+
+struct __attribute__((packed, aligned(4))) spi_flash_cfg_t {
+    uint8_t ioMode;               /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
+    uint8_t cReadSupport;         /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
+    uint8_t clkDelay;             /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
+    uint8_t clkInvert;            /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
+    uint8_t resetEnCmd;           /*!< Flash enable reset command */
+    uint8_t resetCmd;             /*!< Flash reset command */
+    uint8_t resetCreadCmd;        /*!< Flash reset continuous read command */
+    uint8_t resetCreadCmdSize;    /*!< Flash reset continuous read command size */
+    uint8_t jedecIdCmd;           /*!< JEDEC ID command */
+    uint8_t jedecIdCmdDmyClk;     /*!< JEDEC ID command dummy clock */
+    uint8_t enter32BitsAddrCmd;   /*!< Enter 32-bits addr command */
+    uint8_t exit32BitsAddrCmd;    /*!< Exit 32-bits addr command */
+    uint8_t sectorSize;           /*!< *1024bytes */
+    uint8_t mid;                  /*!< Manufacturer ID */
+    uint16_t pageSize;            /*!< Page size */
+    uint8_t chipEraseCmd;         /*!< Chip erase cmd */
+    uint8_t sectorEraseCmd;       /*!< Sector erase command */
+    uint8_t blk32EraseCmd;        /*!< Block 32K erase command,some Micron not support */
+    uint8_t blk64EraseCmd;        /*!< Block 64K erase command */
+    uint8_t writeEnableCmd;       /*!< Need before every erase or program */
+    uint8_t pageProgramCmd;       /*!< Page program cmd */
+    uint8_t qpageProgramCmd;      /*!< QIO page program cmd */
+    uint8_t qppAddrMode;          /*!< QIO page program address mode */
+    uint8_t fastReadCmd;          /*!< Fast read command */
+    uint8_t frDmyClk;             /*!< Fast read command dummy clock */
+    uint8_t qpiFastReadCmd;       /*!< QPI fast read command */
+    uint8_t qpiFrDmyClk;          /*!< QPI fast read command dummy clock */
+    uint8_t fastReadDoCmd;        /*!< Fast read dual output command */
+    uint8_t frDoDmyClk;           /*!< Fast read dual output command dummy clock */
+    uint8_t fastReadDioCmd;       /*!< Fast read dual io comamnd */
+    uint8_t frDioDmyClk;          /*!< Fast read dual io command dummy clock */
+    uint8_t fastReadQoCmd;        /*!< Fast read quad output comamnd */
+    uint8_t frQoDmyClk;           /*!< Fast read quad output comamnd dummy clock */
+    uint8_t fastReadQioCmd;       /*!< Fast read quad io comamnd */
+    uint8_t frQioDmyClk;          /*!< Fast read quad io comamnd dummy clock */
+    uint8_t qpiFastReadQioCmd;    /*!< QPI fast read quad io comamnd */
+    uint8_t qpiFrQioDmyClk;       /*!< QPI fast read QIO dummy clock */
+    uint8_t qpiPageProgramCmd;    /*!< QPI program command */
+    uint8_t writeVregEnableCmd;   /*!< Enable write reg */
+    uint8_t wrEnableIndex;        /*!< Write enable register index */
+    uint8_t qeIndex;              /*!< Quad mode enable register index */
+    uint8_t busyIndex;            /*!< Busy status register index */
+    uint8_t wrEnableBit;          /*!< Write enable bit pos */
+    uint8_t qeBit;                /*!< Quad enable bit pos */
+    uint8_t busyBit;              /*!< Busy status bit pos */
+    uint8_t wrEnableWriteRegLen;  /*!< Register length of write enable */
+    uint8_t wrEnableReadRegLen;   /*!< Register length of write enable status */
+    uint8_t qeWriteRegLen;        /*!< Register length of contain quad enable */
+    uint8_t qeReadRegLen;         /*!< Register length of contain quad enable status */
+    uint8_t releasePowerDown;     /*!< Release power down command */
+    uint8_t busyReadRegLen;       /*!< Register length of contain busy status */
+    uint8_t readRegCmd[4];        /*!< Read register command buffer */
+    uint8_t writeRegCmd[4];       /*!< Write register command buffer */
+    uint8_t enterQpi;             /*!< Enter qpi command */
+    uint8_t exitQpi;              /*!< Exit qpi command */
+    uint8_t cReadMode;            /*!< Config data for continuous read mode */
+    uint8_t cRExit;               /*!< Config data for exit continuous read mode */
+    uint8_t burstWrapCmd;         /*!< Enable burst wrap command */
+    uint8_t burstWrapCmdDmyClk;   /*!< Enable burst wrap command dummy clock */
+    uint8_t burstWrapDataMode;    /*!< Data and address mode for this command */
+    uint8_t burstWrapData;        /*!< Data to enable burst wrap */
+    uint8_t deBurstWrapCmd;       /*!< Disable burst wrap command */
+    uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */
+    uint8_t deBurstWrapDataMode;  /*!< Data and address mode for this command */
+    uint8_t deBurstWrapData;      /*!< Data to disable burst wrap */
+    uint16_t timeEsector;         /*!< 4K erase time */
+    uint16_t timeE32k;            /*!< 32K erase time */
+    uint16_t timeE64k;            /*!< 64K erase time */
+    uint16_t timePagePgm;         /*!< Page program time */
+    uint16_t timeCe;              /*!< Chip erase time in ms */
+    uint8_t pdDelay;              /*!< Release power down command delay time for wake up */
+    uint8_t qeData;               /*!< QE set data */
+};
+
+struct __attribute__((packed, aligned(4))) boot_flash_cfg_t {
+    uint32_t magiccode;
+    struct spi_flash_cfg_t cfg;
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) sys_clk_cfg_t {
+    uint8_t xtal_type;
+    uint8_t pll_clk;
+    uint8_t hclk_div;
+    uint8_t bclk_div;
+
+    uint8_t flash_clk_type;
+    uint8_t flash_clk_div;
+    uint8_t rsvd[2];
+};
+
+struct __attribute__((packed, aligned(4))) boot_clk_cfg_t {
+    uint32_t magiccode;
+    struct sys_clk_cfg_t cfg;
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) aesiv_cfg_t {
+    uint8_t aesiv[16];
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) pkey_cfg_t {
+    uint8_t eckeyx[32]; /* ec key in boot header */
+    uint8_t eckeyy[32]; /* ec key in boot header */
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) sign_cfg_t {
+    uint32_t sig_len;
+    uint8_t signature[32];
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) bootheader_t {
+    uint32_t magiccode;                /* 4 */
+    uint32_t rivison;                  /* 4 */
+    struct boot_flash_cfg_t flash_cfg; /* 4 + 84 + 4 */
+    struct boot_clk_cfg_t clk_cfg;     /* 4 + 8 + 4 */
+    union __attribute__((packed, aligned(1))) {
+        struct __attribute__((packed, aligned(1))) {
+            uint32_t sign               : 2;  /* [1: 0]      for sign*/
+            uint32_t encrypt_type       : 2;  /* [3: 2]      for encrypt */
+            uint32_t key_sel            : 2;  /* [5: 4]      for key sel in boot interface*/
+            uint32_t rsvd6_7            : 2;  /* [7: 6]      for encrypt*/
+            uint32_t no_segment         : 1;  /* [8]         no segment info */
+            uint32_t cache_select       : 1;  /* [9]         for cache */
+            uint32_t notload_in_bootrom : 1;  /* [10]        not load this img in bootrom */
+            uint32_t aes_region_lock    : 1;  /* [11]        aes region lock */
+            uint32_t cache_way_disable  : 4;  /* [15: 12]    cache way disable info*/
+            uint32_t crc_ignore         : 1;  /* [16]        ignore crc */
+            uint32_t hash_ignore        : 1;  /* [17]        hash crc */
+            uint32_t halt_ap            : 1;  /* [18]        halt ap */
+            uint32_t rsvd19_31          : 13; /* [31:19]     rsvd */
+        } bval;
+        uint32_t wval;
+    } boot_cfg; /* 4 */
+
+    union __attribute__((packed, aligned(1))) {
+        uint32_t segment_cnt;
+        uint32_t img_len;
+    } img_segment_info; /* 4 */
+
+    uint32_t rsvd0; /* rsvd */
+
+    union __attribute__((packed, aligned(1))) {
+        uint32_t ramaddr;
+        uint32_t flashoffset;
+    } img_start; /* 4 */
+
+    uint32_t hash[32 / 4]; /*hash of the image*/
+
+    uint32_t rsv1;
+    uint32_t rsv2;
+    uint32_t crc32;
+};
+
+#define BFLB_FW_LENGTH_OFFSET 120
+#define BFLB_FW_HASH_OFFSET   132
+
+#endif
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/bl808_fpga.ld b/bsp/bouffalo_lab/bl60x/board/linker_scripts/bl602_flash.ld
old mode 100644
new mode 100755
similarity index 61%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/bl808_fpga.ld
rename to bsp/bouffalo_lab/bl60x/board/linker_scripts/bl602_flash.ld
index c61185f7fe..d8e8cb5b9d
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/bl808_fpga.ld
+++ b/bsp/bouffalo_lab/bl60x/board/linker_scripts/bl602_flash.ld
@@ -11,104 +11,133 @@
 /* configure the CPU type */
 OUTPUT_ARCH( "riscv" )
 /* link with the standard c library */
-INPUT(-lc)
+/*INPUT(-lc)*/
 /* link with the standard GCC library */
-INPUT(-lgcc)
+/*INPUT(-lgcc)*/
 /* configure the entry point */
-ENTRY(Reset_Handler)
+ENTRY(__start)
 
 StackSize = 0x0400; /*  1KB */
-HeapSize  = 0x0400; /*  1KB */
+HeapSize  = 0x1000; /*  4KB */
 
 MEMORY
 {
-    code_memory (rx)  : ORIGIN = 0x3eff0000, LENGTH = 64K
-    itcm_memory (rx)  : ORIGIN = 0x3eff0000, LENGTH = 64K
-    dtcm_memory (rx)  : ORIGIN = 0x3f000000, LENGTH = 32K
-    ram_memory  (!rx) : ORIGIN = 0x3f008000, LENGTH = 32K
-    xram_memory (!rx) : ORIGIN = 0x40004000, LENGTH = 16K
+    fw_header_memory  (rx)  : ORIGIN = 0x23000000 - 0x1000, LENGTH = 4K
+    xip_memory  (rx)  : ORIGIN = 0x23000000, LENGTH = 1024K
+    itcm_memory (rx)  : ORIGIN = 0x22010000, LENGTH = 16K
+    dtcm_memory (rx)  : ORIGIN = 0x42014000, LENGTH = 48K
+    ram_memory  (!rx) : ORIGIN = 0x42020000, LENGTH = 176K
 }
 
 SECTIONS
 {
     PROVIDE(__metal_chicken_bit = 0);
-    
+
+    .fw_header :
+    {
+        KEEP(*(.fw_header))
+    } > fw_header_memory
+
     .text :
     {
         . = ALIGN(4);
         __text_code_start__ = .;
-        
-        KEEP (*(SORT_NONE(_start)))
-        KEEP (*(SORT_NONE(Reset_Handler)))
-        
+
+        KEEP (*(SORT_NONE(.init)))
+        KEEP (*(SORT_NONE(.vector)))
+
         *(.text)
         *(.text.*)
-        
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        /* section information for modules */
+        . = ALIGN(4);
+        __rtmsymtab_start = .;
+        KEEP(*(RTMSymTab))
+        __rtmsymtab_end = .;
+
+        /* section information for initialization */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+
         /*put .rodata**/
-        *(EXCLUDE_FILE( *bl808_glb*.o* \
-                        *bl808_pds*.o* \
-                        *bl808_common*.o* \
-                        *bl808_sf_cfg*.o* \
-                        *bl808_sf_ctrl*.o* \
-                        *bl808_sflash*.o* \
-                        *bl808_xip_sflash*.o* \
-                        *bl808_ef_ctrl*.o* \
-                        *bl808_sf_cfg_ext*.o* \
-                        *bl808_sflash_ext*.o* \
-                        *bl808_xip_sflash_ext*.o*) .rodata*)
-        
+        *(EXCLUDE_FILE( *bl602_glb*.o* \
+                        *bl602_pds*.o* \
+                        *bl602_common*.o* \
+                        *bl602_sf_cfg*.o* \
+                        *bl602_sf_cfg_ext*.o* \
+                        *bl602_sf_ctrl*.o* \
+                        *bl602_sflash*.o* \
+                        *bl602_sflash_ext*.o* \
+                        *bl602_xip_sflash*.o* \
+                        *bl602_xip_sflash_ext*.o* \
+                        *bl602_ef_ctrl*.o*) .rodata*)
+        *(.rodata)
+        *(.rodata.*)
+
         *(.srodata)
         *(.srodata.*)
-        
-        *(.tcm_code)
-        *(.tcm_const)
-        *(.sclock_rlt_code)
-        *(.sclock_rlt_const)
-        
+
         . = ALIGN(4);
         __text_code_end__ = .;
-    } > code_memory
-    
+
+    } > xip_memory
+
     . = ALIGN(4);
     __itcm_load_addr = .;
-    
+
     .itcm_region : AT (__itcm_load_addr)
     {
         . = ALIGN(4);
         __tcm_code_start__ = .;
 
         *(.tcm_code.*)
-        *(.tcm_cons.t*)
+        *(.tcm_const.*)
         *(.sclock_rlt_code.*)
         *(.sclock_rlt_const.*)
 
-        *bl808_glb*.o*(.rodata*)
-        *bl808_pds*.o*(.rodata*)
-        *bl808_common*.o*(.rodata*)
-        *bl808_sf_cfg*.o*(.rodata*)
-        *bl808_sf_ctrl*.o*(.rodata*)
-        *bl808_sflash*.o*(.rodata*)
-        *bl808_xip_sflash*.o*(.rodata*)
-        *bl808_ef_ctrl*.o*(.rodata*)
+        *bl602_glb*.o*(.rodata*)
+        *bl602_pds*.o*(.rodata*)
+        *bl602_common*.o*(.rodata*)
+        *bl602_sf_cfg*.o*(.rodata*)
+        *bl602_sf_cfg_ext*.o*(.rodata*)
+        *bl602_sf_ctrl*.o*(.rodata*)
+        *bl602_sflash*.o*(.rodata*)
+        *bl602_sflash_ext*.o*(.rodata*)
+        *bl602_xip_sflash*.o*(.rodata*)
+        *bl602_xip_sflash_ext*.o*(.rodata*)
+        *bl602_ef_ctrl*.o*(.rodata*)
 
         . = ALIGN(4);
         __tcm_code_end__ = .;
     } > itcm_memory
-    
+
     __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region);
-    
+
     .dtcm_region : AT (__dtcm_load_addr)
     {
         . = ALIGN(4);
         __tcm_data_start__ = .;
-        
+
         *(.tcm_data)
-        /* *finger_print.o(.data*) */
-        
+
         . = ALIGN(4);
         __tcm_data_end__ = .;
     } > dtcm_memory
 
+
     /* .heap_dummy section doesn't contains any symbols. It is only
      * used for linker to calculate size of heap sections, and assign
      * values to heap symbols later */
@@ -119,9 +148,9 @@ SECTIONS
         . = ALIGN(0x4);
     } > dtcm_memory
 
-    _HeapBase = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory) - StackSize - HeapSize;  
+    _HeapBase = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory) - StackSize - HeapSize;
     _HeapSize = HeapSize;
-    
+
     /* Check if data + heap + stack exceeds RAM limit */
     ASSERT(_HeapBase >= __tcm_data_end__, "region RAM overflowed with stack")
 
@@ -135,91 +164,83 @@ SECTIONS
         . = . + StackSize;
         . = ALIGN(0x4);
     } > dtcm_memory
-    
+
     /* Set stack top to end of RAM, and stack limit move down by
      * size of stack_dummy section */
     __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);
     PROVIDE( __freertos_irq_stack_top = __StackTop);
+    PROVIDE( __rt_rvstack = . );
     __StackLimit = __StackTop - SIZEOF(.stack_dummy);
-    
+
     /* Check if data + heap + stack exceeds RAM limit */
     ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack")
     /*************************************************************************/
-    
-    __system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
-    
-    .system_ram_data_region : AT (__system_ram_load_addr)
-    {
-        . = ALIGN(4);
-        __system_ram_data_start__ = .;
-        
-        *(.system_ram)
-        
-        . = ALIGN(4);
-        __system_ram_data_end__ = .;
-    } > ram_memory
-    
-    __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region);
-    
+
+    __ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
+
     /* Data section */
     RAM_DATA : AT (__ram_load_addr)
     {
         . = ALIGN(4);
         __ram_data_start__ = .;
-        
+
         PROVIDE( __global_pointer$ = . + 0x800 );
-        
+
         *(.data)
         *(.data.*)
         *(.sdata)
         *(.sdata.*)
         *(.sdata2)
         *(.sdata2.*)
-        
+
+        *(.nocache_ram)
+
         . = ALIGN(4);
+        __bflog_tags_start__ = .;
+        *(.bflog_tags_array)
+        . = ALIGN(4);
+        __bflog_tags_end__ = .;
         __ram_data_end__ = .;
     } > ram_memory
-    
-    __etext_final = (__ram_load_addr + SIZEOF (RAM_DATA));
-    ASSERT(__etext_final <= ORIGIN(code_memory) + LENGTH(code_memory), "code memory overflow")
 
     .bss (NOLOAD) :
     {
         . = ALIGN(4);
         __bss_start__ = .;
-        
+
         *(.bss*)
         *(.sbss*)
         *(COMMON)
-        
+
         . = ALIGN(4);
         __bss_end__ = .;
     } > ram_memory
-    
+
     .noinit_data (NOLOAD) :
     {
         . = ALIGN(4);
         __noinit_data_start__ = .;
-        
+
         *(.noinit_data*)
-        
+        *(.nocache_noinit_ram)
+
         . = ALIGN(4);
         __noinit_data_end__ = .;
     } > ram_memory
-    
+
     .heap (NOLOAD):
     {
         . = ALIGN(4);
         __HeapBase = .;
-        
+
         /*__end__ = .;*/
         /*end = __end__;*/
         KEEP(*(.heap*))
-        
+
         . = ALIGN(4);
         __HeapLimit = .;
     } > ram_memory
     __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory);
-    
+
 }
 
diff --git a/bsp/bouffalo_lab/bl60x/board/trap_gcc.S b/bsp/bouffalo_lab/bl60x/board/trap_gcc.S
new file mode 100755
index 0000000000..a255ed7d09
--- /dev/null
+++ b/bsp/bouffalo_lab/bl60x/board/trap_gcc.S
@@ -0,0 +1,17 @@
+#include "cpuport.h"
+
+	.globl rt_hw_do_after_save_above
+	.type rt_hw_do_after_save_above,@function
+rt_hw_do_after_save_above:
+    addi  sp, sp,  -4
+    STORE ra,  0 * REGBYTES(sp)
+
+	csrr    t1, mcause
+    andi    t1, t1, 0x3FF
+    /* get ISR */
+    la      t2, interrupt_entry
+    jalr    t2
+    
+    LOAD  ra,  0 * REGBYTES(sp)
+    addi  sp, sp,  4
+    ret
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/bl60x/combine.sh b/bsp/bouffalo_lab/bl60x/combine.sh
new file mode 100755
index 0000000000..198f6dccf2
--- /dev/null
+++ b/bsp/bouffalo_lab/bl60x/combine.sh
@@ -0,0 +1,35 @@
+#/bin/sh
+CHIPNAME=$1
+BIN_FILE=$2
+
+set -e
+
+SYSTEM=`uname -s`
+echo "system: $SYSTEM"
+
+CONFIG=./board/config
+TOOL_DIR=../libraries/bl_mcu_sdk/tools/bflb_tools/bflb_fw_post_proc
+
+if [ $SYSTEM = "Darwin" ]
+then
+    TOOL_NAME=bflb_fw_post_proc-macos
+    TOOL_ADDR=https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc-macos
+elif [ $SYSTEM = "Linux" ]
+then
+    TOOL_NAME=bflb_fw_post_proc-ubuntu
+    TOOL_ADDR=https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc-ubuntu
+else
+    TOOL_NAME=bflb_fw_post_proc.exe
+    TOOL_ADDR=https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc.exe
+fi
+
+if [ -f "$TOOL_DIR/$TOOL_NAME" ]
+then
+    echo "bflb_fw_post_proc exist"
+else
+    echo "bflb_fw_post_proc not exist, try download... url:$TOOL_ADDR"
+    curl $TOOL_ADDR -o $TOOL_DIR/$TOOL_NAME
+    chmod +x $TOOL_DIR/$TOOL_NAME
+fi
+
+./$TOOL_DIR/$TOOL_NAME --chipname=$CHIPNAME --brdcfgdir=$CONFIG --imgfile=$BIN_FILE
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/bl60x/flash_prog_cfg.ini b/bsp/bouffalo_lab/bl60x/flash_prog_cfg.ini
new file mode 100755
index 0000000000..9dacfa8a0c
--- /dev/null
+++ b/bsp/bouffalo_lab/bl60x/flash_prog_cfg.ini
@@ -0,0 +1,12 @@
+[cfg]
+# 0: no erase, 1:programmed section erase, 2: chip erase
+erase = 1
+# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated
+skip_mode = 0x0, 0x0
+# 0: not use isp mode, #1: isp mode
+boot2_isp_mode = 0
+
+[FW]
+filedir = ./rtthread.bin
+address = 0x000000
+
diff --git a/bsp/bouffalo_lab/bl60x/rtconfig.h b/bsp/bouffalo_lab/bl60x/rtconfig.h
new file mode 100644
index 0000000000..f405d74fdd
--- /dev/null
+++ b/bsp/bouffalo_lab/bl60x/rtconfig.h
@@ -0,0 +1,244 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Project Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 8
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 1000
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_HOOK_USING_FUNC_PTR
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 1024
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 512
+
+/* kservice optimization */
+
+#define RT_KSERVICE_USING_STDLIB
+#define RT_DEBUG
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_PAGE_MAX_ORDER 11
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_SMALL_MEM_AS_HEAP
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart0"
+#define RT_VER_NUM 0x50000
+#define ARCH_RISCV
+#define ARCH_RISCV_FPU
+#define ARCH_RISCV_FPU_S
+#define ARCH_RISCV32
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+#define RT_USING_MSH
+#define RT_USING_FINSH
+#define FINSH_USING_MSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_CMD_SIZE 80
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
+#define FINSH_ARG_MAX 10
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_UNAMED_PIPE_NUMBER 64
+#define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+
+/* Using USB */
+
+
+/* C/C++ and POSIX layer */
+
+#define RT_LIBC_DEFAULT_TIMEZONE 8
+
+/* POSIX (Portable Operating System Interface) layer */
+
+
+/* Interprocess Communication (IPC) */
+
+
+/* Socket is in the 'Network' category */
+
+
+/* Network */
+
+
+/* Utilities */
+
+
+/* RT-Thread Utestcases */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
+
+
+/* XML: Extensible Markup Language */
+
+
+/* multimedia packages */
+
+/* LVGL: powerful and easy-to-use embedded GUI library */
+
+
+/* u8g2: a monochrome graphic library */
+
+
+/* PainterEngine: A cross-platform graphics application framework written in C language */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+/* enhanced kernel services */
+
+
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+
+/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
+/* peripheral libraries and drivers */
+
+/* sensors drivers */
+
+
+/* touch drivers */
+
+
+/* Kendryte SDK */
+
+
+/* AI packages */
+
+
+/* Signal Processing and Control Algorithm Packages */
+
+
+/* miscellaneous packages */
+
+/* project laboratory */
+
+/* samples: kernel and components samples */
+
+
+/* entertainment: terminal games and other interesting software packages */
+
+
+/* Arduino libraries */
+
+
+/* Projects */
+
+
+/* Sensors */
+
+
+/* Display */
+
+
+/* Timing */
+
+
+/* Data Processing */
+
+
+/* Data Storage */
+
+/* Communication */
+
+
+/* Device Control */
+
+
+/* Other */
+
+
+/* Signal IO */
+
+
+/* Uncategorized */
+
+#define BSP_USING_BL60X
+#define BSP_USING_ROMAPI
+
+/* General Drivers Configuration */
+
+#define BSP_USING_GPIO
+
+/* General Purpose UARTs */
+
+#define BSP_USING_UART0
+#define UART0_TX_USING_GPIO16
+#define UART0_RX_USING_GPIO7
+#define BSP_USING_UART1
+#define UART1_TX_USING_GPIO4
+#define UART1_RX_USING_GPIO3
+
+#endif
diff --git a/bsp/bouffalo_lab/bl60x/rtconfig.py b/bsp/bouffalo_lab/bl60x/rtconfig.py
new file mode 100755
index 0000000000..b714aa719b
--- /dev/null
+++ b/bsp/bouffalo_lab/bl60x/rtconfig.py
@@ -0,0 +1,62 @@
+import os
+
+# toolchains options
+ARCH        ='risc-v'
+CPU         ='e24'
+CROSS_TOOL  ='gcc'
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = r'../../..'
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+if  CROSS_TOOL == 'gcc':
+    PLATFORM    = 'gcc'
+    EXEC_PATH   = r'/opt/toolchain_riscv_sifive_linux/bin'
+else:
+    print('Please make sure your toolchains is GNU GCC!')
+    exit(0)
+
+if os.getenv('RTT_EXEC_PATH'):
+    EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX  = 'riscv64-unknown-elf-'
+    CC      = PREFIX + 'gcc'
+    CXX     = PREFIX + 'g++'
+    AS      = PREFIX + 'gcc'
+    AR      = PREFIX + 'ar'
+    LINK    = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE    = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY  = PREFIX + 'objcopy'
+
+    DEVICE  = ' -march=rv32imafc -mabi=ilp32f'
+    CFLAGS  = DEVICE + ' -std=gnu99 -fno-jump-tables -fno-common -fms-extensions -ffunction-sections -fdata-sections -fmessage-length=0 -Wall -Wchar-subscripts -Wformat -Wundef -Wuninitialized -Winit-self -Wignored-qualifiers'
+    CFLAGS += ' -fstrict-volatile-bitfields -fshort-enums -Wno-error=unused-variable -Wno-error=format= -Wno-error=unused-function -Wno-error=implicit-function-declaration -Wno-error=deprecated-declarations -Wno-format'
+
+    LINKER_SCRIPTS = r'board/linker_scripts/bl602_flash.ld'
+
+    AFLAGS  = ' -c' + DEVICE + ' -x assembler-with-cpp'
+    LFLAGS  = DEVICE + ' -nostartfiles -ufw_header -fms-extensions -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T ' + LINKER_SCRIPTS
+    CPATH   = ''
+    LPATH   = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O2 -g3'
+        AFLAGS += ' -g3'
+    else:
+        CFLAGS += ' -O3'
+
+    CXXFLAGS = CFLAGS + ' -std=gnu++17 -Wno-multichar'
+
+DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
+POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+POST_ACTION += 'sh combine.sh bl602 ./rtthread.bin\n'
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/bl61x/.config b/bsp/bouffalo_lab/bl61x/.config
new file mode 100755
index 0000000000..1904fc04c8
--- /dev/null
+++ b/bsp/bouffalo_lab/bl61x/.config
@@ -0,0 +1,1001 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Project Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=8
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=1000
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_HOOK_USING_FUNC_PTR=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=512
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
+
+#
+# kservice optimization
+#
+CONFIG_RT_KSERVICE_USING_STDLIB=y
+# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_TINY_FFS is not set
+# CONFIG_RT_KPRINTF_USING_LONGLONG is not set
+CONFIG_RT_DEBUG=y
+# CONFIG_RT_DEBUG_COLOR is not set
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_PAGE_MAX_ORDER=11
+CONFIG_RT_USING_MEMPOOL=y
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMHEAP is not set
+CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_SLAB_AS_HEAP is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+# CONFIG_RT_USING_HEAP_ISR is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_DM is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
+CONFIG_RT_VER_NUM=0x50000
+# CONFIG_RT_USING_CACHE is not set
+# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+# CONFIG_RT_USING_CPU_FFS is not set
+CONFIG_ARCH_RISCV=y
+CONFIG_ARCH_RISCV_FPU=y
+CONFIG_ARCH_RISCV_FPU_S=y
+CONFIG_ARCH_RISCV32=y
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+# CONFIG_RT_USING_LEGACY is not set
+CONFIG_RT_USING_MSH=y
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_ARG_MAX=10
+# CONFIG_RT_USING_DFS is not set
+# CONFIG_RT_USING_FAL is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_UNAMED_PIPE_NUMBER=64
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_USING_SERIAL_V1=y
+# CONFIG_RT_USING_SERIAL_V2 is not set
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+# CONFIG_RT_USING_NULL is not set
+# CONFIG_RT_USING_ZERO is not set
+# CONFIG_RT_USING_RANDOM is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_FDT is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_LCD is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_DEV_BUS is not set
+# CONFIG_RT_USING_WIFI is not set
+# CONFIG_RT_USING_VIRTIO is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB is not set
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# C/C++ and POSIX layer
+#
+CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
+
+#
+# POSIX (Portable Operating System Interface) layer
+#
+# CONFIG_RT_USING_POSIX_FS is not set
+# CONFIG_RT_USING_POSIX_DELAY is not set
+# CONFIG_RT_USING_POSIX_CLOCK is not set
+# CONFIG_RT_USING_POSIX_TIMER is not set
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Interprocess Communication (IPC)
+#
+# CONFIG_RT_USING_POSIX_PIPE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
+
+#
+# Socket is in the 'Network' category
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Network
+#
+# CONFIG_RT_USING_SAL is not set
+# CONFIG_RT_USING_NETDEV is not set
+# CONFIG_RT_USING_LWIP is not set
+# CONFIG_RT_USING_AT is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_VAR_EXPORT is not set
+# CONFIG_RT_USING_ADT is not set
+# CONFIG_RT_USING_RT_LINK is not set
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LWIP is not set
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_EZ_IOT_OS is not set
+# CONFIG_PKG_USING_IOTSHARP_SDK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_RYANMQTT is not set
+# CONFIG_PKG_USING_RYANW5500 is not set
+# CONFIG_PKG_USING_LORA_PKT_FWD is not set
+# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
+# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
+# CONFIG_PKG_USING_HM is not set
+# CONFIG_PKG_USING_SMALL_MODBUS is not set
+# CONFIG_PKG_USING_NET_SERVER is not set
+# CONFIG_PKG_USING_ZFTP is not set
+# CONFIG_PKG_USING_WOL is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_LIBSODIUM is not set
+# CONFIG_PKG_USING_LIBHYDROGEN is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+
+#
+# language packages
+#
+
+#
+# JSON: JavaScript Object Notation, a lightweight data-interchange format
+#
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PARSON is not set
+
+#
+# XML: Extensible Markup Language
+#
+# CONFIG_PKG_USING_SIMPLE_XML is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_LUATOS_SOC is not set
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
+# CONFIG_PKG_USING_RTT_RUST is not set
+
+#
+# multimedia packages
+#
+
+#
+# LVGL: powerful and easy-to-use embedded GUI library
+#
+# CONFIG_PKG_USING_LVGL is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
+# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
+
+#
+# u8g2: a monochrome graphic library
+#
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+# CONFIG_PKG_USING_UGUI is not set
+
+#
+# PainterEngine: A cross-platform graphics application framework written in C language
+#
+# CONFIG_PKG_USING_PAINTERENGINE is not set
+# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_GUIENGINE is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
+# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+# CONFIG_PKG_USING_FDT is not set
+# CONFIG_PKG_USING_CBOX is not set
+# CONFIG_PKG_USING_SNOWFLAKE is not set
+# CONFIG_PKG_USING_HASH_MATCH is not set
+# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
+# CONFIG_PKG_USING_VOFA_PLUS is not set
+
+#
+# system packages
+#
+
+#
+# enhanced kernel services
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+
+#
+# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+#
+# CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_PERF_COUNTER is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+# CONFIG_PKG_USING_TINYUSB is not set
+# CONFIG_PKG_USING_CHERRYUSB is not set
+# CONFIG_PKG_USING_KMULTI_RTIMER is not set
+# CONFIG_PKG_USING_TFDB is not set
+# CONFIG_PKG_USING_QPC is not set
+# CONFIG_PKG_USING_AGILE_UPGRADE is not set
+# CONFIG_PKG_USING_FLASH_BLOB is not set
+
+#
+# peripheral libraries and drivers
+#
+
+#
+# sensors drivers
+#
+# CONFIG_PKG_USING_LSM6DSM is not set
+# CONFIG_PKG_USING_LSM6DSL is not set
+# CONFIG_PKG_USING_LPS22HB is not set
+# CONFIG_PKG_USING_HTS221 is not set
+# CONFIG_PKG_USING_LSM303AGR is not set
+# CONFIG_PKG_USING_BME280 is not set
+# CONFIG_PKG_USING_BME680 is not set
+# CONFIG_PKG_USING_BMA400 is not set
+# CONFIG_PKG_USING_BMI160_BMX160 is not set
+# CONFIG_PKG_USING_SPL0601 is not set
+# CONFIG_PKG_USING_MS5805 is not set
+# CONFIG_PKG_USING_DA270 is not set
+# CONFIG_PKG_USING_DF220 is not set
+# CONFIG_PKG_USING_HSHCAL001 is not set
+# CONFIG_PKG_USING_BH1750 is not set
+# CONFIG_PKG_USING_MPU6XXX is not set
+# CONFIG_PKG_USING_AHT10 is not set
+# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_TSL4531 is not set
+# CONFIG_PKG_USING_DS18B20 is not set
+# CONFIG_PKG_USING_DHT11 is not set
+# CONFIG_PKG_USING_DHTXX is not set
+# CONFIG_PKG_USING_GY271 is not set
+# CONFIG_PKG_USING_GP2Y10 is not set
+# CONFIG_PKG_USING_SGP30 is not set
+# CONFIG_PKG_USING_HDC1000 is not set
+# CONFIG_PKG_USING_BMP180 is not set
+# CONFIG_PKG_USING_BMP280 is not set
+# CONFIG_PKG_USING_SHTC1 is not set
+# CONFIG_PKG_USING_BMI088 is not set
+# CONFIG_PKG_USING_HMC5883 is not set
+# CONFIG_PKG_USING_MAX6675 is not set
+# CONFIG_PKG_USING_TMP1075 is not set
+# CONFIG_PKG_USING_SR04 is not set
+# CONFIG_PKG_USING_CCS811 is not set
+# CONFIG_PKG_USING_PMSXX is not set
+# CONFIG_PKG_USING_RT3020 is not set
+# CONFIG_PKG_USING_MLX90632 is not set
+# CONFIG_PKG_USING_MLX90393 is not set
+# CONFIG_PKG_USING_MLX90392 is not set
+# CONFIG_PKG_USING_MLX90397 is not set
+# CONFIG_PKG_USING_MS5611 is not set
+# CONFIG_PKG_USING_MAX31865 is not set
+# CONFIG_PKG_USING_VL53L0X is not set
+# CONFIG_PKG_USING_INA260 is not set
+# CONFIG_PKG_USING_MAX30102 is not set
+# CONFIG_PKG_USING_INA226 is not set
+# CONFIG_PKG_USING_LIS2DH12 is not set
+# CONFIG_PKG_USING_HS300X is not set
+# CONFIG_PKG_USING_ZMOD4410 is not set
+# CONFIG_PKG_USING_ISL29035 is not set
+# CONFIG_PKG_USING_MMC3680KJ is not set
+# CONFIG_PKG_USING_QMP6989 is not set
+# CONFIG_PKG_USING_BALANCE is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_ADT74XX is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_CW2015 is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_STHS34PF80 is not set
+
+#
+# touch drivers
+#
+# CONFIG_PKG_USING_GT9147 is not set
+# CONFIG_PKG_USING_GT1151 is not set
+# CONFIG_PKG_USING_GT917S is not set
+# CONFIG_PKG_USING_GT911 is not set
+# CONFIG_PKG_USING_FT6206 is not set
+# CONFIG_PKG_USING_FT5426 is not set
+# CONFIG_PKG_USING_FT6236 is not set
+# CONFIG_PKG_USING_XPT2046_TOUCH is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ESP_IDF is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+
+#
+# Kendryte SDK
+#
+# CONFIG_PKG_USING_K210_SDK is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_MULTI_INFRARED is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_NUCLEI_SDK is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
+# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
+# CONFIG_PKG_USING_BL_MCU_SDK is not set
+# CONFIG_PKG_USING_SOFT_SERIAL is not set
+# CONFIG_PKG_USING_MB85RS16 is not set
+# CONFIG_PKG_USING_RFM300 is not set
+# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
+# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
+# CONFIG_PKG_USING_FINGERPRINT is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+
+#
+# Signal Processing and Control Algorithm Packages
+#
+# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
+# CONFIG_PKG_USING_UKAL is not set
+
+#
+# miscellaneous packages
+#
+
+#
+# project laboratory
+#
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_HEATSHRINK is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
+# CONFIG_PKG_USING_MFBD is not set
+# CONFIG_PKG_USING_SLCAN2RTT is not set
+# CONFIG_PKG_USING_SOEM is not set
+# CONFIG_PKG_USING_QPARAM is not set
+# CONFIG_PKG_USING_CorevMCU_CLI is not set
+
+#
+# Arduino libraries
+#
+# CONFIG_PKG_USING_RTDUINO is not set
+
+#
+# Projects
+#
+# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
+# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
+
+#
+# Sensors
+#
+# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
+# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
+# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
+# CONFIG_PKG_USING_SEEED_ITG3200 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
+# CONFIG_PKG_USING_SEEED_MP503 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
+
+#
+# Display
+#
+# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
+# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set
+# CONFIG_PKG_USING_SEEED_TM1637 is not set
+
+#
+# Timing
+#
+# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
+
+#
+# Data Processing
+#
+# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
+# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
+
+#
+# Data Storage
+#
+
+#
+# Communication
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
+
+#
+# Device Control
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
+
+#
+# Other
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
+# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
+
+#
+# Signal IO
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
+
+#
+# Uncategorized
+#
+CONFIG_BSP_USING_BL61X=y
+CONFIG_BSP_USING_ROMAPI=y
+# CONFIG_BSP_USING_PSRAM is not set
+
+#
+# General Drivers Configuration
+#
+CONFIG_BSP_USING_GPIO=y
+
+#
+# General Purpose UARTs
+#
+CONFIG_BSP_USING_UART0=y
+# CONFIG_UART0_TX_USING_GPIO14 is not set
+# CONFIG_UART0_TX_USING_GPIO16 is not set
+CONFIG_UART0_TX_USING_GPIO21=y
+# CONFIG_UART0_RX_USING_GPIO7 is not set
+# CONFIG_UART0_RX_USING_GPIO15 is not set
+CONFIG_UART0_RX_USING_GPIO22=y
+# CONFIG_UART0_RX_USING_GPIO23 is not set
+CONFIG_BSP_USING_UART1=y
+# CONFIG_UART1_TX_USING_GPIO4 is not set
+CONFIG_UART1_TX_USING_GPIO16=y
+# CONFIG_UART1_TX_USING_GPIO18 is not set
+# CONFIG_UART1_TX_USING_GPIO26 is not set
+# CONFIG_UART1_RX_USING_GPIO3 is not set
+# CONFIG_UART1_RX_USING_GPIO5 is not set
+CONFIG_UART1_RX_USING_GPIO17=y
+# CONFIG_UART1_RX_USING_GPIO19 is not set
+# CONFIG_UART1_RX_USING_GPIO27 is not set
diff --git a/bsp/bouffalo_lab/bl61x/Kconfig b/bsp/bouffalo_lab/bl61x/Kconfig
new file mode 100755
index 0000000000..c6ee6e58f8
--- /dev/null
+++ b/bsp/bouffalo_lab/bl61x/Kconfig
@@ -0,0 +1,26 @@
+mainmenu "RT-Thread Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+config LIBRARIES_DIR
+    string
+    option env="LIBRARIES_DIR"
+    default "../libraries"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "board/Kconfig"
+source "$LIBRARIES_DIR/Kconfig"
diff --git a/bsp/bouffalo_lab/bl61x/SConscript b/bsp/bouffalo_lab/bl61x/SConscript
new file mode 100755
index 0000000000..c7ef7659ec
--- /dev/null
+++ b/bsp/bouffalo_lab/bl61x/SConscript
@@ -0,0 +1,14 @@
+# for module compiling
+import os
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/bl808/m0/SConstruct b/bsp/bouffalo_lab/bl61x/SConstruct
old mode 100644
new mode 100755
similarity index 60%
rename from bsp/bl808/m0/SConstruct
rename to bsp/bouffalo_lab/bl61x/SConstruct
index 7966251fa1..4b958f7cbe
--- a/bsp/bl808/m0/SConstruct
+++ b/bsp/bouffalo_lab/bl61x/SConstruct
@@ -22,15 +22,21 @@ env['ASCOM'] = env['ASPPCOM']
 Export('RTT_ROOT')
 Export('rtconfig')
 
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+    libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
 # prepare building environment
 objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False)
 
-stack_size = 4096
+# include libraries
+objs.extend(SConscript(libraries_path_prefix + '/bl_mcu_sdk/SConscript', variant_dir='build/libraries/bl_mcu_sdk', duplicate=0))
 
-stack_lds = open('link_stacksize.lds', 'w')
-if GetDepend('__STACKSIZE__'): stack_size = GetDepend('__STACKSIZE__')
-stack_lds.write('__STACKSIZE__ = %d;' % stack_size)
-stack_lds.close()
+# include drivers
+objs.extend(SConscript(libraries_path_prefix + '/rt_drivers/SConscript', variant_dir='build/libraries/rt_drivers', duplicate=0))
 
 # make a building
 DoBuilding(TARGET, objs)
diff --git a/bsp/bouffalo_lab/bl61x/applications/SConscript b/bsp/bouffalo_lab/bl61x/applications/SConscript
new file mode 100755
index 0000000000..c583d3016e
--- /dev/null
+++ b/bsp/bouffalo_lab/bl61x/applications/SConscript
@@ -0,0 +1,9 @@
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/bouffalo_lab/bl61x/applications/main.c b/bsp/bouffalo_lab/bl61x/applications/main.c
new file mode 100644
index 0000000000..4d11a45f4c
--- /dev/null
+++ b/bsp/bouffalo_lab/bl61x/applications/main.c
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022/12/25     flyingcys    first version
+ */
+
+#include 
+#include 
+#include 
+#include "drv_gpio.h"
+
+int main(void)
+{
+    rt_kprintf("Hello, RISC-V!\n");
+
+    return 0;
+}
diff --git a/bsp/bouffalo_lab/bl61x/board/Kconfig b/bsp/bouffalo_lab/bl61x/board/Kconfig
new file mode 100755
index 0000000000..03b674a334
--- /dev/null
+++ b/bsp/bouffalo_lab/bl61x/board/Kconfig
@@ -0,0 +1,16 @@
+config BSP_USING_BL61X
+    bool
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    select ARCH_RISCV32
+    select ARCH_RISCV_FPU_S
+    select BSP_USING_ROMAPI
+    default y
+
+config BSP_USING_ROMAPI
+    bool 
+    default y
+
+config BSP_USING_PSRAM
+    bool "Enable PSRAM"
+    default n
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/bl61x/board/SConscript b/bsp/bouffalo_lab/bl61x/board/SConscript
new file mode 100755
index 0000000000..c0653a14cc
--- /dev/null
+++ b/bsp/bouffalo_lab/bl61x/board/SConscript
@@ -0,0 +1,9 @@
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*.S')
+CPPPATH = [cwd]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/bouffalo_lab/bl61x/board/board.c b/bsp/bouffalo_lab/bl61x/board/board.c
new file mode 100644
index 0000000000..1216b77be0
--- /dev/null
+++ b/bsp/bouffalo_lab/bl61x/board/board.c
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023/03/15     flyingcys    first version
+ */
+#include 
+#include 
+
+#include "board.h"
+#include "drv_uart.h"
+
+static void system_clock_init(void)
+{
+#if 1
+    /* wifipll/audiopll */
+    GLB_Power_On_XTAL_And_PLL_CLK(GLB_XTAL_40M, GLB_PLL_WIFIPLL | GLB_PLL_AUPLL);
+    GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_TOP_WIFIPLL_320M);
+#else
+    GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_RC32M);
+    GLB_Power_On_XTAL_And_PLL_CLK(GLB_XTAL_40M, GLB_PLL_WIFIPLL);
+    GLB_Config_AUDIO_PLL_To_384M();
+    GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_TOP_AUPLL_DIV1);
+    GLB_Set_MCU_System_CLK_Div(0, 3);
+#endif
+    CPU_Set_MTimer_CLK(ENABLE, BL_MTIMER_SOURCE_CLOCK_MCU_XCLK, Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK) / 1000000 - 1);
+}
+
+static void peripheral_clock_init(void)
+{
+    PERIPHERAL_CLOCK_ADC_DAC_ENABLE();
+    PERIPHERAL_CLOCK_SEC_ENABLE();
+    PERIPHERAL_CLOCK_DMA0_ENABLE();
+    PERIPHERAL_CLOCK_UART0_ENABLE();
+    PERIPHERAL_CLOCK_UART1_ENABLE();
+    PERIPHERAL_CLOCK_SPI0_ENABLE();
+    PERIPHERAL_CLOCK_I2C0_ENABLE();
+    PERIPHERAL_CLOCK_PWM0_ENABLE();
+    PERIPHERAL_CLOCK_TIMER0_1_WDG_ENABLE();
+    PERIPHERAL_CLOCK_IR_ENABLE();
+    PERIPHERAL_CLOCK_I2S_ENABLE();
+    PERIPHERAL_CLOCK_USB_ENABLE();
+    PERIPHERAL_CLOCK_CAN_ENABLE();
+
+    GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_XCLK, 0);
+    GLB_Set_SPI_CLK(ENABLE, GLB_SPI_CLK_MCU_MUXPLL_160M, 0);
+    GLB_Set_I2C_CLK(ENABLE, GLB_I2C_CLK_XCLK, 0);
+    GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, 1);
+    GLB_Set_DIG_CLK_Sel(GLB_DIG_CLK_XCLK);
+    GLB_Set_DIG_512K_CLK(ENABLE, ENABLE, 0x4E);
+    GLB_Set_PWM1_IO_Sel(GLB_PWM1_IO_DIFF_END);
+    GLB_Set_IR_CLK(ENABLE, GLB_IR_CLK_SRC_XCLK, 19);
+    GLB_Set_CAM_CLK(ENABLE, GLB_CAM_CLK_WIFIPLL_96M, 3);
+
+    GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_MCU_MUXPLL_160M);
+#ifdef CONFIG_BSP_SDH_SDCARD
+    PERIPHERAL_CLOCK_SDH_ENABLE();
+    GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_EXT_SDH);
+#endif
+
+    GLB_Set_USB_CLK_From_WIFIPLL(1);
+    GLB_Swap_MCU_SPI_0_MOSI_With_MISO(0);
+}
+
+#ifdef BSP_USING_PSRAM
+static void bflb_init_psram_gpio(void)
+{
+    struct bflb_device_s *gpio;
+
+    gpio = bflb_device_get_by_name("gpio");
+    for (uint8_t i = 0; i < 12; i++) {
+        bflb_gpio_init(gpio, (41 + i), GPIO_INPUT | GPIO_FLOAT | GPIO_SMT_EN | GPIO_DRV_0);
+    }
+}
+
+static void psram_winbond_default_init(void)
+{
+    PSRAM_Ctrl_Cfg_Type default_psram_ctrl_cfg = {
+        .vendor = PSRAM_CTRL_VENDOR_WINBOND,
+        .ioMode = PSRAM_CTRL_X8_MODE,
+        .size = PSRAM_SIZE_4MB,
+        .dqs_delay = 0xfff0,
+    };
+
+    PSRAM_Winbond_Cfg_Type default_winbond_cfg = {
+        .rst = DISABLE,
+        .clockType = PSRAM_CLOCK_DIFF,
+        .inputPowerDownMode = DISABLE,
+        .hybridSleepMode = DISABLE,
+        .linear_dis = ENABLE,
+        .PASR = PSRAM_PARTIAL_REFRESH_FULL,
+        .disDeepPowerDownMode = ENABLE,
+        .fixedLatency = DISABLE,
+        .brustLen = PSRAM_WINBOND_BURST_LENGTH_64_BYTES,
+        .brustType = PSRAM_WRAPPED_BURST,
+        .latency = PSRAM_WINBOND_6_CLOCKS_LATENCY,
+        .driveStrength = PSRAM_WINBOND_DRIVE_STRENGTH_35_OHMS_FOR_4M_115_OHMS_FOR_8M,
+    };
+
+    PSram_Ctrl_Init(PSRAM0_ID, &default_psram_ctrl_cfg);
+    // PSram_Ctrl_Winbond_Reset(PSRAM0_ID);
+    PSram_Ctrl_Winbond_Write_Reg(PSRAM0_ID, PSRAM_WINBOND_REG_CR0, &default_winbond_cfg);
+}
+
+static uint32_t board_psram_x8_init(void)
+{
+    uint16_t reg_read = 0;
+
+    GLB_Set_PSRAMB_CLK_Sel(ENABLE, GLB_PSRAMB_EMI_WIFIPLL_320M, 0);
+
+    bflb_init_psram_gpio();
+
+    /* psram init*/
+    psram_winbond_default_init();
+    /* check psram work or not */
+    PSram_Ctrl_Winbond_Read_Reg(PSRAM0_ID, PSRAM_WINBOND_REG_ID0, ®_read);
+    return reg_read;
+}
+#endif
+
+/* This is the timer interrupt service routine. */
+static void systick_isr(void)
+{
+    rt_tick_increase();
+}
+
+void rt_hw_board_init(void)
+{
+    bflb_flash_init();
+
+    system_clock_init();
+    peripheral_clock_init();
+    bflb_irq_initialize();
+
+    bflb_mtimer_config(HW_MTIMER_CLOCK / RT_TICK_PER_SECOND, systick_isr);
+
+#ifdef RT_USING_HEAP
+    /* initialize memory system */
+    rt_kprintf("RT_HW_HEAP_BEGIN:%x RT_HW_HEAP_END:%x size: %d\r\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END, RT_HW_HEAP_END - RT_HW_HEAP_BEGIN);
+    rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
+#endif
+
+
+    /* UART driver initialization is open by default */
+#ifdef RT_USING_SERIAL
+    rt_hw_uart_init();
+#endif
+
+#ifdef BSP_USING_PSRAM
+    board_psram_x8_init();
+    Tzc_Sec_PSRAMB_Access_Release();
+#endif
+
+    /* Set the shell console output device */
+#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}
+
+void rt_hw_cpu_reset(void)
+{
+    GLB_SW_POR_Reset();
+}
+MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reset machine);
diff --git a/bsp/bouffalo_lab/bl61x/board/board.h b/bsp/bouffalo_lab/bl61x/board/board.h
new file mode 100644
index 0000000000..e2a0acbb6e
--- /dev/null
+++ b/bsp/bouffalo_lab/bl61x/board/board.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022/03/15     flyingcys    first version
+ */
+
+#ifndef BOARD_H__
+#define BOARD_H__
+
+#include 
+
+#include "bflb_uart.h"
+#include "bflb_gpio.h"
+#include "bflb_clock.h"
+#include "bflb_rtc.h"
+#include "bflb_flash.h"
+#include "bl616_tzc_sec.h"
+#include "bl616_psram.h"
+#include "bl616_glb.h"
+
+#define     HW_MTIMER_CLOCK     1000000
+
+extern uint8_t __HeapBase;
+extern uint8_t __HeapLimit;
+
+#define RT_HW_HEAP_BEGIN    (void*)&__HeapBase
+#define RT_HW_HEAP_END      (void*)&__HeapLimit
+
+void rt_hw_board_init(void);
+
+#endif
diff --git a/bsp/bouffalo_lab/bl61x/board/builtin_imgs/boot2_bl616_debug_v8.0.7.bin b/bsp/bouffalo_lab/bl61x/board/builtin_imgs/boot2_bl616_debug_v8.0.7.bin
new file mode 100755
index 0000000000..b9cf792b19
Binary files /dev/null and b/bsp/bouffalo_lab/bl61x/board/builtin_imgs/boot2_bl616_debug_v8.0.7.bin differ
diff --git a/bsp/bouffalo_lab/bl61x/board/builtin_imgs/boot2_bl616_release_v8.0.7.bin b/bsp/bouffalo_lab/bl61x/board/builtin_imgs/boot2_bl616_release_v8.0.7.bin
new file mode 100755
index 0000000000..93b15b2092
Binary files /dev/null and b/bsp/bouffalo_lab/bl61x/board/builtin_imgs/boot2_bl616_release_v8.0.7.bin differ
diff --git a/bsp/bouffalo_lab/bl61x/board/builtin_imgs/mfg_bl616_gu_af8b0946f_autoboot_v2.26.bin b/bsp/bouffalo_lab/bl61x/board/builtin_imgs/mfg_bl616_gu_af8b0946f_autoboot_v2.26.bin
new file mode 100755
index 0000000000..c8b8957ec3
Binary files /dev/null and b/bsp/bouffalo_lab/bl61x/board/builtin_imgs/mfg_bl616_gu_af8b0946f_autoboot_v2.26.bin differ
diff --git a/bsp/bouffalo_lab/bl61x/board/builtin_imgs/mfg_bl616_gu_af8b0946f_v2.26.bin b/bsp/bouffalo_lab/bl61x/board/builtin_imgs/mfg_bl616_gu_af8b0946f_v2.26.bin
new file mode 100755
index 0000000000..ee2ad9acff
Binary files /dev/null and b/bsp/bouffalo_lab/bl61x/board/builtin_imgs/mfg_bl616_gu_af8b0946f_v2.26.bin differ
diff --git a/bsp/bouffalo_lab/bl61x/board/config/bl_factory_params_IoTKitA_auto.dts b/bsp/bouffalo_lab/bl61x/board/config/bl_factory_params_IoTKitA_auto.dts
new file mode 100755
index 0000000000..92228f5ba6
--- /dev/null
+++ b/bsp/bouffalo_lab/bl61x/board/config/bl_factory_params_IoTKitA_auto.dts
@@ -0,0 +1,352 @@
+/dts-v1/;
+/include/ "bl602_base.dtsi";
+// version: 17
+// last_comp_version: 16
+// boot_cpuid_phys: 0x0
+
+/ {
+    model = "bl bl602 IOT board";
+    compatible = "bl,bl602-sample", "bl,bl602-common";
+    #address-cells = <0x1>;
+    #size-cells = <0x1>;
+    gpio {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        max_num = <40>;
+        gpio0 {                                  
+            status = "okay";                     
+            pin  = <5>;                          
+            feature = "led";                     
+            active = "Hi"; //Hi or Lo
+            mode = "blink"; //blink or hearbeat
+            time = <100>; //duration for this mode
+        };
+        gpio1 {                                  
+            status = "disable";                     
+            pin  = <6>;                          
+            feature = "led";                     
+            active = "Hi"; //Hi or Lo
+            mode = "blink"; //blink or hearbeat
+            time = <100>; //duration for this mode
+        };
+        gpio2 {
+            status = "okay";
+            pin = <2>;
+            feature = "button";
+            active = "Hi";
+            mode = "multipress";
+            button {
+                debounce = <10>;
+                short_press_ms {
+                    start = <100>;
+                    end = <3000>;
+                    kevent = <2>;
+                };
+                long_press_ms {
+                    start = <6000>;
+                    end = <10000>;
+                    kevent = <3>;
+                };
+                longlong_press_ms {
+                    start = <15000>;
+                    kevent = <4>;
+                };
+                trig_level = "Hi";
+            };
+            hbn_use = "disable";
+        };
+    };
+    i2s {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        i2s@40017000 {
+            status = "okay";
+            compatible = "bl602_i2s";
+            reg = <0x40017000 0x100>;
+            mclk_only = "okay";
+            pin {
+                mclk = <11>;
+            };
+        };
+        i2s@40017100 {
+            status = "okay";
+            compatible = "bl602_i2s";
+            reg = <0x40017100 0x100>;
+            mclk_only = "disable";
+            pin {
+                bclk = <12>;
+                fs = <29>;
+                do = <30>;
+                di = <31>;
+            };
+        };
+    };
+    i2c {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        i2c@40011000 {
+            status = "okay";
+            compatible = "bl602_i2c";
+            reg = <0x40011000 0x100>;
+            pin {
+                scl = <32>;
+                sda = <13>;
+            };
+            devices {
+                list_addr = <0x18 0x21>;
+                list_driver = "i2c_es8311", "i2c_gc0308>";
+            };
+        };
+        i2c@40011100 {
+            status = "disable";
+            compatible = "bl602_i2c";
+            reg = <0x40011100 0x100>;
+            pin {
+                /*empty here*/
+            };
+        };
+    };
+    timer {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        timer@40014000 {
+            status = "disable";
+            compatible = "bl602_timer";
+            reg = <0x40014000 0x100>;
+        };
+        timer@40014100 {
+            status = "disable";
+            compatible = "bl602_timer";
+            reg = <0x40014100 0x100>;
+        };
+    };
+    pwm {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        pwm@4000A420 {
+            status = "okay";
+            compatible = "bl602_pwm";
+            reg = <0x4000A420 0x20>;
+            path = "/dev/pwm0";
+            id = <0>;
+            pin = <0>;
+            freq = <800000>;
+            duty = <50>;
+        };
+        pwm@4000A440 {
+            status = "disable";
+            reg = <0x4000A440 0x20>;
+            path = "/dev/pwm1";
+            id = <1>;
+            pin = <1>;
+            freq = <5000>;
+            duty = <50>;
+        };
+        pwm@4000A460 {
+            status = "disable";
+            reg = <0x4000A460 0x20>;
+            path = "/dev/pwm2";
+            id = <2>;
+            pin = <2>;
+            freq = <5000>;
+            duty = <50>;
+        };
+        pwm@4000A480 {
+            status = "disable";
+            reg = <0x4000A480 0x20>;
+            path = "/dev/pwm3";
+            id = <3>;
+            pin = <3>;
+            freq = <5000>;
+            duty = <50>;
+        };
+        pwm@4000A4A0 {
+            status = "disable";
+            reg = <0x4000A4A0 0x20>;
+            path = "/dev/pwm4";
+            id = <4>;
+            pin = <4>;
+            freq = <5000>;
+            duty = <50>;
+        };
+    };
+    ir {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        ctrltype = <0>;
+        tx {
+            status = "disable";
+            pin = <11>;         // only support 11
+            mode = "NEC";       // NEC,ExtenedNEC,RC5,SWM
+            interval = <100>;   // ms
+            active_mode = "Hi"; //Hi,Lo
+        };
+        rx {
+            status = "okay";
+            pin = <12>;         // only support 12 13
+            mode = "NEC";       // NEC,ExtenedNEC,RC5,SWM
+            active_mode = "Hi"; //Hi,Lo
+            data_check = <2>;   //bit 0:check cmd, bit 1:check addr
+        };
+    };
+    uart {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        uart@4000A000 {
+            status = "okay";
+            id = <0>;
+            compatible = "bl602_uart";
+            path = "/dev/ttyS0";
+            baudrate = <2000000>;
+            pin {
+                rx = <7>;
+                tx = <16>;
+            };
+            buf_size {
+                rx_size = <512>;
+                tx_size = <512>;
+            };
+            feature {
+                tx = "okay";
+                rx = "okay";
+                cts = "disable";
+                rts = "disable";
+            };
+        };
+        uart@4000A100 {
+            status = "okay";
+            id = <1>;
+            compatible = "bl602_uart";
+            path = "/dev/ttyS1";
+            baudrate = <115200>;
+            pin {
+                rx = <3>;
+                tx = <4>;
+            };
+            buf_size {
+                rx_size = <512>;
+                tx_size = <512>;
+            };
+            feature {
+                tx = "okay";
+                rx = "okay";
+                cts = "disable";
+                rts = "disable";
+            };
+        };
+    };
+    spi {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        spi@4000F000 {
+            status = "okay";         /* okay disable */
+            mode = "master";
+            reg = <0x4000F000 0x100>;   /* 4KB */
+            path = "/dev/spi0";
+            port = <0>;
+            polar_phase = <1>;                 /* 0,1,2,3 */
+            freq = <6000000>;
+            pin {
+                clk = <3>;
+                cs = <2>;
+                mosi = <1>;
+                miso = <0>;
+            };
+            dma_cfg {
+                tx_dma_ch = <2>;
+                rx_dma_ch = <3>;
+            };
+        };
+    };
+    gpip {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        adc_key {
+            status = "disable";
+            pin = <9>;
+            interrupt  = <3>;
+            key_vol = <0 100 400 300 500>;
+            key_pcb = "SW1", "SW2", "SW3", "SW4","SW5";
+            key_event = "Usr1", "Usr2", "Start", "Up", "Down";
+            key_raw = <1 2 3 4 5>;
+        };
+    };
+    qspi {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        qspi@4000A000 {
+            status = "disable";
+            reg = <0x4000A000 0x1000>;/* 4KB */
+        };
+    };
+    wifi {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        region {
+            country_code = <86>;
+        };
+        mac {
+            mode = "MBF";
+            sta_mac_addr = [C8 43 57 82 73 40];
+            ap_mac_addr = [C8 43 57 82 73 02];
+        };
+        sta {
+            ssid = "yourssid";
+            pwd = "yourapssword";
+            auto_connect_enable = <0>;
+        };
+        ap {
+            ssid = "bl_test_005";
+            pwd = "12345678";
+            ap_channel = <11>;
+            auto_chan_detect = "disable";
+        };
+        brd_rf {
+            xtal_mode = "MF";
+            xtal = <36 36 0 60 60>;
+            pwr_mode = "bf";//B: only use power offset in EFUSE; b: use power offset in EFUSE with incremental mode; F: only use power offset in Flash; f: use power offset in Flash with incremental mode
+            pwr_table_11b        = <20 20 20 20>;//1Mbps 2Mbps 5.5Mbps 11Mbps
+            pwr_table_11g        = <18 18 18 18 18 18 16 16>; //6Mbps 9Mbps 12Mbps 18MBps 24Mbps 36Mbps 48Mbps 54Mbps
+            pwr_table_11n_ht20  = <18 18 18 18 18 16 15 15>; //MCS0~MCS7
+            pwr_table_11n_ht40  = <18 18 18 18 18 16 15 14>; //MCS0~MCS7
+            pwr_table_11ac_vht20 = <18 18 18 18 18 16 15 15 15 14>; //MSC0~MSC9
+            pwr_table_11ac_vht40 = <18 18 18 18 18 16 15 14 14 13>; //MSC0~MSC9
+            pwr_table_11ac_vht80 = <18 18 18 18 18 15 14 13 13 12>; //MSC0~MSC9
+            pwr_table_11ax_he20  = <18 18 18 18 18 16 15 15 15 14 13 13>; //MSC0~MSC11
+            pwr_table_11ax_he40  = <18 18 18 18 18 16 15 14 14 13 12 12>; //MSC0~MSC11
+            pwr_table_11ax_he80  = <18 18 18 18 18 15 14 13 13 12 11 11>; //MSC0~MSC11
+            pwr_table_11ax_he160 = <18 18 18 18 18 15 14 13 12 11 10 10>; //MSC0~MSC11
+            
+            pwr_offset = <16 16 16 16 16 16 16 16 16 16 16 16 16 16>;//due to the limit of current DTC, negative value is used. So we work around by adding all the poweroffset with 16.
+            pwr_offset_lp = <16 16 16 16 16 16 16 16 16 16 16 16 16 16>;   
+            //so 14 represents -0.5dBm; 16 represents 0dBm; 20 represents 1dBm;(step is 0.25dBm)
+        };
+        rf_temp {
+            en_tcal = <0>;
+            linear_or_follow = <1>;
+            Tchannels       = <2412 2427 2442 2457 2472>;
+            Tchannel_os     = <180  168  163  160  157>;
+            Tchannel_os_low = <199  186  170  165  160>;
+            Troom_os        = <255>;
+            //negative value is NOT supported. So we use '256' for 0, '255' for -1, '257' for 1,'511' for 256
+        };
+    };
+    bluetooth_zigbee {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        brd_rf {
+            pwr_table_ble = <13>; //range:0~15dbm
+            pwr_table_bt = <10 8 8>; //BR 1M,EDR 2M,EDR 3M
+            pwr_table_zigbee = <13>; //range:0~15dbm
+            pwr_offset = <16 16 16 16 16>; //step is 0.25dBm
+            
+        };
+    };
+    info {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        brd {
+            country_code = <86>; 
+        };
+    };
+};
diff --git a/bsp/bl808/partition/partition_cfg_16M_m1sdock.toml b/bsp/bouffalo_lab/bl61x/board/config/partition_cfg_4M.toml
old mode 100644
new mode 100755
similarity index 50%
rename from bsp/bl808/partition/partition_cfg_16M_m1sdock.toml
rename to bsp/bouffalo_lab/bl61x/board/config/partition_cfg_4M.toml
index 7b75961470..f9ade510d7
--- a/bsp/bl808/partition/partition_cfg_16M_m1sdock.toml
+++ b/bsp/bouffalo_lab/bl61x/board/config/partition_cfg_4M.toml
@@ -17,69 +17,110 @@ size1 = 0
 len = 0
 # If header is 1, it will add the header.
 header = 1
+# If header is 1 and security is 1, It will be encrypted.
+security = 1
 
 [[pt_entry]]
 type = 0
 name = "FW"
 device = 0
 address0 = 0x10000
-size0 = 0xF0000
+size0 = 0x200000
+address1 = 0x210000
+size1 = 0x168000
+# compressed image must set len,normal image can left it to 0
+len = 0
+# If header is 1, it will add the header.
+header = 1
+# If header is 1 and security is 1, It will be encrypted.
+security= 1
+
+[[pt_entry]]
+type = 10
+name = "mfg"
+device = 0
+address0 = 0x210000
+size0 = 0x168000
 address1 = 0
 size1 = 0
 # compressed image must set len,normal image can left it to 0
 len = 0
 # If header is 1, it will add the header.
 header = 1
+# If header is 1 and security is 1, It will be encrypted.
+security= 1
 
 [[pt_entry]]
 type = 2
-name = "D0FW"
+name = "media"
 device = 0
-address0 = 0x100000
-size0 = 0x200000
+address0 = 0x378000
+size0 = 0x71000
 address1 = 0
 size1 = 0
 # compressed image must set len,normal image can left it to 0
 len = 0
 # If header is 1, it will add the header.
-header = 1
+header = 0
+# If header is 1 and security is 1, It will be encrypted.
+security= 0
+
+[[pt_entry]]
+type = 3
+name = "PSM"
+device = 0
+address0 = 0x3E9000
+size0 = 0x8000
+address1 = 0
+size1 = 0
+# compressed image must set len,normal image can left it to 0
+len = 0
+# If header is 1, it will add the header.
+header = 0
+# If header is 1 and security is 1, It will be encrypted.
+security= 0
+
+[[pt_entry]]
+type = 4
+name = "KEY"
+device = 0
+address0 = 0x3F1000
+size0 = 0x2000
+address1 = 0
+size1 = 0
+# compressed image must set len,normal image can left it to 0
+len = 0
+# If header is 1, it will add the header.
+header = 0
+# If header is 1 and security is 1, It will be encrypted.
+security= 0
 
 [[pt_entry]]
 type = 5
-name = "media"
+name = "DATA"
 device = 0
-address0 = 0x300000
-size0 = 0xC00000
+address0 = 0x3F3000
+size0 = 0x5000
 address1 = 0
 size1 = 0
 # compressed image must set len,normal image can left it to 0
 len = 0
 # If header is 1, it will add the header.
-header = 1
+header = 0
+# If header is 1 and security is 1, It will be encrypted.
+security = 0
 
 [[pt_entry]]
-type = 11
-name = "unused"
-device = 0
-address0 = 0xF00000
-size0 = 0x100000
-address1 = 0
-size1 = 0
-# compressed image must set len,normal image can left it to 0
-len = 0
-# If header is 1, it will add the header.
-header = 1
-
-[[pt_entry]]
-type = 8
-# It shows Dts in DevCube 
+type = 6
 name = "factory"
 device = 0
-address0 = 0x910000
-size0 = 0
+address0 = 0x3F8000
+size0 = 0x8000
 address1 = 0
 size1 = 0
 # compressed image must set len,normal image can left it to 0
 len = 0
 # If header is 1, it will add the header.
-header = 1
+header = 0
+# If header is 1 and security is 1, It will be encrypted.
+security= 0
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/bl61x/board/fw_header.c b/bsp/bouffalo_lab/bl61x/board/fw_header.c
new file mode 100644
index 0000000000..caac91b0f0
--- /dev/null
+++ b/bsp/bouffalo_lab/bl61x/board/fw_header.c
@@ -0,0 +1,165 @@
+#include "fw_header.h"
+
+__attribute__((section(".fw_header"))) struct bootheader_t fw_header = {
+    .magiccode = 0x504e4642,
+    .rivison = 0x00000001,
+    /*flash config */
+    .flash_cfg.magiccode = 0x47464346,
+    .flash_cfg.cfg.ioMode = 0x11,               /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
+    .flash_cfg.cfg.cReadSupport = 0x00,         /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
+    .flash_cfg.cfg.clkDelay = 0x01,             /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
+    .flash_cfg.cfg.clkInvert = 0x01,            /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
+    .flash_cfg.cfg.resetEnCmd = 0x66,           /*!< Flash enable reset command */
+    .flash_cfg.cfg.resetCmd = 0x99,             /*!< Flash reset command */
+    .flash_cfg.cfg.resetCreadCmd = 0xff,        /*!< Flash reset continuous read command */
+    .flash_cfg.cfg.resetCreadCmdSize = 0x03,    /*!< Flash reset continuous read command size */
+    .flash_cfg.cfg.jedecIdCmd = 0x9f,           /*!< JEDEC ID command */
+    .flash_cfg.cfg.jedecIdCmdDmyClk = 0x00,     /*!< JEDEC ID command dummy clock */
+    .flash_cfg.cfg.enter32BitsAddrCmd = 0xb7,   /*!< Enter 32-bits addr command */
+    .flash_cfg.cfg.exit32BitsAddrCmd = 0xe9,    /*!< Exit 32-bits addr command */
+    .flash_cfg.cfg.sectorSize = 0x04,           /*!< *1024bytes */
+    .flash_cfg.cfg.mid = 0x00,                  /*!< Manufacturer ID */
+    .flash_cfg.cfg.pageSize = 0x100,            /*!< Page size */
+    .flash_cfg.cfg.chipEraseCmd = 0xc7,         /*!< Chip erase cmd */
+    .flash_cfg.cfg.sectorEraseCmd = 0x20,       /*!< Sector erase command */
+    .flash_cfg.cfg.blk32EraseCmd = 0x52,        /*!< Block 32K erase command,some Micron not support */
+    .flash_cfg.cfg.blk64EraseCmd = 0xd8,        /*!< Block 64K erase command */
+    .flash_cfg.cfg.writeEnableCmd = 0x06,       /*!< Need before every erase or program */
+    .flash_cfg.cfg.pageProgramCmd = 0x02,       /*!< Page program cmd */
+    .flash_cfg.cfg.qpageProgramCmd = 0x32,      /*!< QIO page program cmd */
+    .flash_cfg.cfg.qppAddrMode = 0x00,          /*!< QIO page program address mode */
+    .flash_cfg.cfg.fastReadCmd = 0x0b,          /*!< Fast read command */
+    .flash_cfg.cfg.frDmyClk = 0x01,             /*!< Fast read command dummy clock */
+    .flash_cfg.cfg.qpiFastReadCmd = 0x0b,       /*!< QPI fast read command */
+    .flash_cfg.cfg.qpiFrDmyClk = 0x01,          /*!< QPI fast read command dummy clock */
+    .flash_cfg.cfg.fastReadDoCmd = 0x3b,        /*!< Fast read dual output command */
+    .flash_cfg.cfg.frDoDmyClk = 0x01,           /*!< Fast read dual output command dummy clock */
+    .flash_cfg.cfg.fastReadDioCmd = 0xbb,       /*!< Fast read dual io comamnd */
+    .flash_cfg.cfg.frDioDmyClk = 0x00,          /*!< Fast read dual io command dummy clock */
+    .flash_cfg.cfg.fastReadQoCmd = 0x6b,        /*!< Fast read quad output comamnd */
+    .flash_cfg.cfg.frQoDmyClk = 0x01,           /*!< Fast read quad output comamnd dummy clock */
+    .flash_cfg.cfg.fastReadQioCmd = 0xeb,       /*!< Fast read quad io comamnd */
+    .flash_cfg.cfg.frQioDmyClk = 0x02,          /*!< Fast read quad io comamnd dummy clock */
+    .flash_cfg.cfg.qpiFastReadQioCmd = 0xeb,    /*!< QPI fast read quad io comamnd */
+    .flash_cfg.cfg.qpiFrQioDmyClk = 0x02,       /*!< QPI fast read QIO dummy clock */
+    .flash_cfg.cfg.qpiPageProgramCmd = 0x02,    /*!< QPI program command */
+    .flash_cfg.cfg.writeVregEnableCmd = 0x50,   /*!< Enable write reg */
+    .flash_cfg.cfg.wrEnableIndex = 0x00,        /*!< Write enable register index */
+    .flash_cfg.cfg.qeIndex = 0x01,              /*!< Quad mode enable register index */
+    .flash_cfg.cfg.busyIndex = 0x00,            /*!< Busy status register index */
+    .flash_cfg.cfg.wrEnableBit = 0x01,          /*!< Write enable bit pos */
+    .flash_cfg.cfg.qeBit = 0x01,                /*!< Quad enable bit pos */
+    .flash_cfg.cfg.busyBit = 0x00,              /*!< Busy status bit pos */
+    .flash_cfg.cfg.wrEnableWriteRegLen = 0x02,  /*!< Register length of write enable */
+    .flash_cfg.cfg.wrEnableReadRegLen = 0x01,   /*!< Register length of write enable status */
+    .flash_cfg.cfg.qeWriteRegLen = 0x02,        /*!< Register length of contain quad enable */
+    .flash_cfg.cfg.qeReadRegLen = 0x01,         /*!< Register length of contain quad enable status */
+    .flash_cfg.cfg.releasePowerDown = 0xab,     /*!< Release power down command */
+    .flash_cfg.cfg.busyReadRegLen = 0x01,       /*!< Register length of contain busy status */
+    .flash_cfg.cfg.readRegCmd[0] = 0x05,        /*!< Read register command buffer */
+    .flash_cfg.cfg.readRegCmd[1] = 0x35,        /*!< Read register command buffer */
+    .flash_cfg.cfg.readRegCmd[2] = 0x00,        /*!< Read register command buffer */
+    .flash_cfg.cfg.readRegCmd[3] = 0x00,        /*!< Read register command buffer */
+    .flash_cfg.cfg.writeRegCmd[0] = 0x01,       /*!< Write register command buffer */
+    .flash_cfg.cfg.writeRegCmd[1] = 0x01,       /*!< Write register command buffer */
+    .flash_cfg.cfg.writeRegCmd[2] = 0x00,       /*!< Write register command buffer */
+    .flash_cfg.cfg.writeRegCmd[3] = 0x00,       /*!< Write register command buffer */
+    .flash_cfg.cfg.enterQpi = 0x38,             /*!< Enter qpi command */
+    .flash_cfg.cfg.exitQpi = 0xff,              /*!< Exit qpi command */
+    .flash_cfg.cfg.cReadMode = 0x20,            /*!< Config data for continuous read mode */
+    .flash_cfg.cfg.cRExit = 0xf0,               /*!< Config data for exit continuous read mode */
+    .flash_cfg.cfg.burstWrapCmd = 0x77,         /*!< Enable burst wrap command */
+    .flash_cfg.cfg.burstWrapCmdDmyClk = 0x03,   /*!< Enable burst wrap command dummy clock */
+    .flash_cfg.cfg.burstWrapDataMode = 0x02,    /*!< Data and address mode for this command */
+    .flash_cfg.cfg.burstWrapData = 0x40,        /*!< Data to enable burst wrap */
+    .flash_cfg.cfg.deBurstWrapCmd = 0x77,       /*!< Disable burst wrap command */
+    .flash_cfg.cfg.deBurstWrapCmdDmyClk = 0x03, /*!< Disable burst wrap command dummy clock */
+    .flash_cfg.cfg.deBurstWrapDataMode = 0x02,  /*!< Data and address mode for this command */
+    .flash_cfg.cfg.deBurstWrapData = 0xf0,      /*!< Data to disable burst wrap */
+    .flash_cfg.cfg.timeEsector = 300,           /*!< 4K erase time */
+    .flash_cfg.cfg.timeE32k = 1200,             /*!< 32K erase time */
+    .flash_cfg.cfg.timeE64k = 1200,             /*!< 64K erase time */
+    .flash_cfg.cfg.timePagePgm = 50,            /*!< Page program time */
+    .flash_cfg.cfg.timeCe = 30000,              /*!< Chip erase time in ms */
+    .flash_cfg.cfg.pdDelay = 20,                /*!< Release power down command delay time for wake up */
+    .flash_cfg.cfg.qeData = 0,                  /*!< QE set data */
+    .flash_cfg.crc32 = 0xdeadbeef,
+    /* clock cfg */
+    .clk_cfg.magiccode = 0x47464350,
+    .clk_cfg.cfg.xtal_type = 0x07,      /*!< 0:None,1:24M,2:32M,3:38.4M,4:40M,5:26M,6:RC32M  */
+    .clk_cfg.cfg.mcu_clk = 0x05,        /*!< mcu_clk 0:RC32M;1:XTAL;2:aupll_div2;3:aupll_div1;4:wifipll_240M;5:wifipll_320M */
+    .clk_cfg.cfg.mcu_clk_div = 0x00,    /*!< mcu_clk divider */
+    .clk_cfg.cfg.mcu_bclk_div = 0x00,   /*!< mcu_bclk divider */
+    .clk_cfg.cfg.mcu_pbclk_div = 0x03,  /*!< mcu_pclk divider */
+    .clk_cfg.cfg.emi_clk = 0x02,        /*!< 0:mcu pbclk,1:cpupll 200M,2:wifipll 320M,3:cpupll 400M */
+    .clk_cfg.cfg.emi_clk_div = 0x01,    /*!< emi clock divider */
+    .clk_cfg.cfg.flash_clk_type = 0x01, /*!< 0:wifipll_120M;1:xtal;2:aupll_div5;3:muxpll_80M;4:bclk;5:wifipll_96M */
+    .clk_cfg.cfg.flash_clk_div = 0x00,
+    .clk_cfg.cfg.wifipll_pu = 0x01,
+    .clk_cfg.cfg.aupll_pu = 0x00,
+    .clk_cfg.crc32 = 0xdeadbeef,
+    /* basic cfg */
+    .basic_cfg.sign_type = 0x0,          /* [1: 0]   for sign */
+    .basic_cfg.encrypt_type = 0x0,       /* [3: 2]   for encrypt */
+    .basic_cfg.key_sel = 0x0,            /* [5: 4]   key slot */
+    .basic_cfg.xts_mode = 0x0,           /* [6]      for xts mode */
+    .basic_cfg.aes_region_lock = 0x0,    /* [7]      rsvd */
+    .basic_cfg.no_segment = 0x1,         /* [8]      no segment info */
+    .basic_cfg.rsvd_0 = 0x0,             /* [9]      boot2 enable(rsvd_0) */
+    .basic_cfg.rsvd_1 = 0x0,             /* [10]     boot2 rollback(rsvd_1) */
+    .basic_cfg.cpu_master_id = 0x0,      /* [14: 11] master id */
+    .basic_cfg.notload_in_bootrom = 0x0, /* [15]     notload in bootrom */
+    .basic_cfg.crc_ignore = 0x1,         /* [16]     ignore crc */
+    .basic_cfg.hash_ignore = 0x1,        /* [17]     hash ignore */
+    .basic_cfg.power_on_mm = 0x1,        /* [18]     power on mm */
+    .basic_cfg.em_sel = 0x1,             /* [21: 19] em_sel */
+    .basic_cfg.cmds_en = 0x1,            /* [22]     command spliter enable */
+#if 0
+# 0 : cmds bypass wrap commands to macro, original mode;
+# 1 : cmds handle wrap commands, original mode;
+# 2 : cmds bypass wrap commands to macro, cmds force wrap16 * 4 splitted into two wrap8 * 4;
+# 3 : cmds handle wrap commands, cmds force wrap16 * 4 splitted into two wrap8 * 4
+#endif
+    .basic_cfg.cmds_wrap_mode = 0x1, /* [24: 23] cmds wrap mode */
+#if 0
+# 0 : SF_CTRL_WRAP_LEN_8, 1 : SF_CTRL_WRAP_LEN_16, 2 : SF_CTRL_WRAP_LEN_32,
+# 3 : SF_CTRL_WRAP_LEN_64, 9 : SF_CTRL_WRAP_LEN_4096
+#endif
+    .basic_cfg.cmds_wrap_len = 0x9,  /* [28: 25] cmds wrap len */
+    .basic_cfg.icache_invalid = 0x1, /* [29] icache invalid */
+    .basic_cfg.dcache_invalid = 0x1, /* [30] dcache invalid */
+    .basic_cfg.rsvd_3 = 0x0,         /* [31] rsvd_3 */
+
+    .basic_cfg.group_image_offset = 0x00001000, /* flash controller offset */
+    .basic_cfg.aes_region_len = 0x00000000,     /* aes region length */
+
+    .basic_cfg.img_len_cnt = 0x00010000, /* image length or segment count */
+    .basic_cfg.hash = { 0xdeadbeef },    /* hash of the image */
+
+    /* cpu cfg */
+    .cpu_cfg.config_enable = 0x01, /* coinfig this cpu */
+    .cpu_cfg.halt_cpu = 0x0,       /* halt this cpu */
+    .cpu_cfg.cache_enable = 0x0,   /* cache setting :only for BL Cache */
+    .cpu_cfg.cache_wa = 0x0,       /* cache setting :only for BL Cache*/
+    .cpu_cfg.cache_wb = 0x0,       /* cache setting :only for BL Cache*/
+    .cpu_cfg.cache_wt = 0x0,       /* cache setting :only for BL Cache*/
+    .cpu_cfg.cache_way_dis = 0x0,  /* cache setting :only for BL Cache*/
+    .cpu_cfg.rsvd = 0x0,
+
+    /* image_address_offset */
+    .cpu_cfg.image_address_offset = 0x0,
+    .cpu_cfg.rsvd1 = 0xA0000000,   /* rsvd */
+    .cpu_cfg.msp_val = 0x00000000, /* msp value */
+
+    /* address of partition table 0 */
+    .boot2_pt_table_0_rsvd = 0x00000000,
+    /* address of partition table 1 */
+    .boot2_pt_table_1_rsvd = 0x00000000,
+
+    /* address of flashcfg table list */
+    .flash_cfg_table_addr = 0x00000000,
+    /* flashcfg table list len */
+    .flash_cfg_table_len = 0x00000000,
+
+    .crc32 = 0xdeadbeef
+};
diff --git a/bsp/bouffalo_lab/bl61x/board/fw_header.h b/bsp/bouffalo_lab/bl61x/board/fw_header.h
new file mode 100644
index 0000000000..fd230929dd
--- /dev/null
+++ b/bsp/bouffalo_lab/bl61x/board/fw_header.h
@@ -0,0 +1,197 @@
+#ifndef __FW_HEADER_H__
+#define __FW_HEADER_H__
+
+#include "stdint.h"
+#include "stdio.h"
+
+struct __attribute__((packed, aligned(4))) spi_flash_cfg_t {
+    uint8_t ioMode;               /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
+    uint8_t cReadSupport;         /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
+    uint8_t clkDelay;             /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
+    uint8_t clkInvert;            /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
+    uint8_t resetEnCmd;           /*!< Flash enable reset command */
+    uint8_t resetCmd;             /*!< Flash reset command */
+    uint8_t resetCreadCmd;        /*!< Flash reset continuous read command */
+    uint8_t resetCreadCmdSize;    /*!< Flash reset continuous read command size */
+    uint8_t jedecIdCmd;           /*!< JEDEC ID command */
+    uint8_t jedecIdCmdDmyClk;     /*!< JEDEC ID command dummy clock */
+    uint8_t enter32BitsAddrCmd;   /*!< Enter 32-bits addr command */
+    uint8_t exit32BitsAddrCmd;    /*!< Exit 32-bits addr command */
+    uint8_t sectorSize;           /*!< *1024bytes */
+    uint8_t mid;                  /*!< Manufacturer ID */
+    uint16_t pageSize;            /*!< Page size */
+    uint8_t chipEraseCmd;         /*!< Chip erase cmd */
+    uint8_t sectorEraseCmd;       /*!< Sector erase command */
+    uint8_t blk32EraseCmd;        /*!< Block 32K erase command,some Micron not support */
+    uint8_t blk64EraseCmd;        /*!< Block 64K erase command */
+    uint8_t writeEnableCmd;       /*!< Need before every erase or program */
+    uint8_t pageProgramCmd;       /*!< Page program cmd */
+    uint8_t qpageProgramCmd;      /*!< QIO page program cmd */
+    uint8_t qppAddrMode;          /*!< QIO page program address mode */
+    uint8_t fastReadCmd;          /*!< Fast read command */
+    uint8_t frDmyClk;             /*!< Fast read command dummy clock */
+    uint8_t qpiFastReadCmd;       /*!< QPI fast read command */
+    uint8_t qpiFrDmyClk;          /*!< QPI fast read command dummy clock */
+    uint8_t fastReadDoCmd;        /*!< Fast read dual output command */
+    uint8_t frDoDmyClk;           /*!< Fast read dual output command dummy clock */
+    uint8_t fastReadDioCmd;       /*!< Fast read dual io comamnd */
+    uint8_t frDioDmyClk;          /*!< Fast read dual io command dummy clock */
+    uint8_t fastReadQoCmd;        /*!< Fast read quad output comamnd */
+    uint8_t frQoDmyClk;           /*!< Fast read quad output comamnd dummy clock */
+    uint8_t fastReadQioCmd;       /*!< Fast read quad io comamnd */
+    uint8_t frQioDmyClk;          /*!< Fast read quad io comamnd dummy clock */
+    uint8_t qpiFastReadQioCmd;    /*!< QPI fast read quad io comamnd */
+    uint8_t qpiFrQioDmyClk;       /*!< QPI fast read QIO dummy clock */
+    uint8_t qpiPageProgramCmd;    /*!< QPI program command */
+    uint8_t writeVregEnableCmd;   /*!< Enable write reg */
+    uint8_t wrEnableIndex;        /*!< Write enable register index */
+    uint8_t qeIndex;              /*!< Quad mode enable register index */
+    uint8_t busyIndex;            /*!< Busy status register index */
+    uint8_t wrEnableBit;          /*!< Write enable bit pos */
+    uint8_t qeBit;                /*!< Quad enable bit pos */
+    uint8_t busyBit;              /*!< Busy status bit pos */
+    uint8_t wrEnableWriteRegLen;  /*!< Register length of write enable */
+    uint8_t wrEnableReadRegLen;   /*!< Register length of write enable status */
+    uint8_t qeWriteRegLen;        /*!< Register length of contain quad enable */
+    uint8_t qeReadRegLen;         /*!< Register length of contain quad enable status */
+    uint8_t releasePowerDown;     /*!< Release power down command */
+    uint8_t busyReadRegLen;       /*!< Register length of contain busy status */
+    uint8_t readRegCmd[4];        /*!< Read register command buffer */
+    uint8_t writeRegCmd[4];       /*!< Write register command buffer */
+    uint8_t enterQpi;             /*!< Enter qpi command */
+    uint8_t exitQpi;              /*!< Exit qpi command */
+    uint8_t cReadMode;            /*!< Config data for continuous read mode */
+    uint8_t cRExit;               /*!< Config data for exit continuous read mode */
+    uint8_t burstWrapCmd;         /*!< Enable burst wrap command */
+    uint8_t burstWrapCmdDmyClk;   /*!< Enable burst wrap command dummy clock */
+    uint8_t burstWrapDataMode;    /*!< Data and address mode for this command */
+    uint8_t burstWrapData;        /*!< Data to enable burst wrap */
+    uint8_t deBurstWrapCmd;       /*!< Disable burst wrap command */
+    uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */
+    uint8_t deBurstWrapDataMode;  /*!< Data and address mode for this command */
+    uint8_t deBurstWrapData;      /*!< Data to disable burst wrap */
+    uint16_t timeEsector;         /*!< 4K erase time */
+    uint16_t timeE32k;            /*!< 32K erase time */
+    uint16_t timeE64k;            /*!< 64K erase time */
+    uint16_t timePagePgm;         /*!< Page program time */
+    uint16_t timeCe;              /*!< Chip erase time in ms */
+    uint8_t pdDelay;              /*!< Release power down command delay time for wake up */
+    uint8_t qeData;               /*!< QE set data */
+};
+
+struct __attribute__((packed, aligned(4))) boot_flash_cfg_t {
+    uint32_t magiccode;
+    struct spi_flash_cfg_t cfg;
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) sys_clk_cfg_t {
+    uint8_t xtal_type;
+    uint8_t mcu_clk;
+    uint8_t mcu_clk_div;
+    uint8_t mcu_bclk_div;
+
+    uint8_t mcu_pbclk_div;
+    uint8_t emi_clk;
+    uint8_t emi_clk_div;
+    uint8_t flash_clk_type;
+
+    uint8_t flash_clk_div;
+    uint8_t wifipll_pu;
+    uint8_t aupll_pu;
+    uint8_t rsvd0;
+};
+
+struct __attribute__((packed, aligned(4))) boot_clk_cfg_t {
+    uint32_t magiccode;
+    struct sys_clk_cfg_t cfg;
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) boot_basic_cfg_t {
+    uint32_t sign_type          : 2; /* [1: 0]   for sign */
+    uint32_t encrypt_type       : 2; /* [3: 2]   for encrypt */
+    uint32_t key_sel            : 2; /* [5: 4]   key slot */
+    uint32_t xts_mode           : 1; /* [6]      for xts mode */
+    uint32_t aes_region_lock    : 1; /* [7]      rsvd */
+    uint32_t no_segment         : 1; /* [8]      no segment info */
+    uint32_t rsvd_0             : 1; /* [9]      boot2 enable(rsvd_0) */
+    uint32_t rsvd_1             : 1; /* [10]     boot2 rollback(rsvd_1) */
+    uint32_t cpu_master_id      : 4; /* [14: 11] master id */
+    uint32_t notload_in_bootrom : 1; /* [15]     notload in bootrom */
+    uint32_t crc_ignore         : 1; /* [16]     ignore crc */
+    uint32_t hash_ignore        : 1; /* [17]     hash ignore */
+    uint32_t power_on_mm        : 1; /* [18]     power on mm */
+    uint32_t em_sel             : 3; /* [21: 19] em_sel */
+    uint32_t cmds_en            : 1; /* [22]     command spliter enable */
+    uint32_t cmds_wrap_mode     : 2; /* [24: 23] cmds wrap mode */
+    uint32_t cmds_wrap_len      : 4; /* [28: 25] cmds wrap len */
+    uint32_t icache_invalid     : 1; /* [29] icache invalid */
+    uint32_t dcache_invalid     : 1; /* [30] dcache invalid */
+    uint32_t rsvd_3             : 1; /* [31] rsvd_3 */
+
+    uint32_t group_image_offset; /* flash controller offset */
+    uint32_t aes_region_len;     /* aes region length */
+
+    uint32_t img_len_cnt;  /* image length or segment count */
+    uint32_t hash[32 / 4]; /* hash of the image */
+};
+
+struct __attribute__((packed, aligned(4))) boot_cpu_cfg_t {
+    uint8_t config_enable;     /* coinfig this cpu */
+    uint8_t halt_cpu;          /* halt this cpu */
+    uint8_t cache_enable  : 1; /* cache setting */
+    uint8_t cache_wa      : 1; /* cache setting */
+    uint8_t cache_wb      : 1; /* cache setting */
+    uint8_t cache_wt      : 1; /* cache setting */
+    uint8_t cache_way_dis : 4; /* cache setting */
+    uint8_t rsvd;
+
+    uint32_t image_address_offset; /* image_address_offset */
+    uint32_t rsvd1;                /* rsvd */
+    uint32_t msp_val;              /* msp value */
+};
+
+struct __attribute__((packed, aligned(4))) aesiv_cfg_t {
+    uint8_t aesiv[16];
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) pkey_cfg_t {
+    uint8_t eckeyx[32]; /* ec key in boot header */
+    uint8_t eckeyy[32]; /* ec key in boot header */
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) sign_cfg_t {
+    uint32_t sig_len;
+    uint8_t signature[32];
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) bootheader_t {
+    uint32_t magiccode; /* 4 */
+    uint32_t rivison;   /* 4 */
+
+    struct boot_flash_cfg_t flash_cfg; /* 4 + 84 + 4 */
+    struct boot_clk_cfg_t clk_cfg;     /* 4 + 12 + 4 */
+
+    struct boot_basic_cfg_t basic_cfg; /* 4 + 4 + 4 + 4 + 4*8 */
+
+    struct boot_cpu_cfg_t cpu_cfg; /* 16 */
+
+    uint32_t boot2_pt_table_0_rsvd; /* address of partition table 0 */ /* 4 */
+    uint32_t boot2_pt_table_1_rsvd; /* address of partition table 1 */ /* 4 */
+
+    uint32_t flash_cfg_table_addr; /* address of flashcfg table list */ /* 4 */
+    uint32_t flash_cfg_table_len; /* flashcfg table list len */         /* 4 */
+
+    uint32_t rsvd0[6]; /* rsvd */
+    uint32_t rsvd1[6]; /* rsvd */
+
+    uint32_t rsvd; /* 4 */
+
+    uint32_t crc32; /* 4 */
+};
+
+#endif
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/bl808_flash.ld b/bsp/bouffalo_lab/bl61x/board/linker_scripts/bl616_flash.ld
old mode 100644
new mode 100755
similarity index 52%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/bl808_flash.ld
rename to bsp/bouffalo_lab/bl61x/board/linker_scripts/bl616_flash.ld
index 3b24a2e65d..ef77620e6c
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/bl808_flash.ld
+++ b/bsp/bouffalo_lab/bl61x/board/linker_scripts/bl616_flash.ld
@@ -15,68 +15,103 @@ INPUT(-lc)
 /* link with the standard GCC library */
 INPUT(-lgcc)
 /* configure the entry point */
-ENTRY(Reset_Handler)
+ENTRY(__start)
 
-StackSize    = 0x0400; /*  1KB */
+StackSize    = 0x1000; /*  4KB */
 HeapMinSize  = 0x1000; /*  4KB */
 
+__EM_SIZE = DEFINED(btble_controller_init) ? 32K : 0K;
+__RFTLV_SIZE_OFFSET = 1K;
+__RFTLV_SIZE_HOLE = 2K;
+__RFTLV_HEAD1_H = (0x46524C42); /* BLRF */
+__RFTLV_HEAD1_L = (0x41524150); /* PAPA */
+
 MEMORY
 {
-    xip_memory  (rx)  : ORIGIN = 0x58000000, LENGTH = 32M
-    itcm_memory (rx)  : ORIGIN = 0x3eff0000, LENGTH = 28K
-    dtcm_memory (rx)  : ORIGIN = 0x3eff7000, LENGTH = 4K
-    nocache_ram_memory (!rx) : ORIGIN = 0x3eff8000, LENGTH = 0K
-    ram_memory  (!rx) : ORIGIN = 0x3eff8000, LENGTH = 64K
-    xram_memory (!rx) : ORIGIN = 0x40004000, LENGTH = 16K
+    fw_header_memory  (rx)  : ORIGIN = 0xA0000000 - 0x1000, LENGTH = 4K
+    xip_memory  (rx)  : ORIGIN = 0xA0000000, LENGTH = 4M
+    ram_code  (wxa)   : ORIGIN = 0xA8000000, LENGTH = 4M
+    itcm_memory (rx)  : ORIGIN = 0x62FC0000, LENGTH = 20K
+    dtcm_memory (rx)  : ORIGIN = 0x62FC5000, LENGTH = 4K
+    nocache_ram_memory (!rx) : ORIGIN = 0x22FC6000, LENGTH = 44K+60K
+    ram_memory  (!rx) : ORIGIN = 0x62FE0000, LENGTH = 320K-20K-4K-44K-60K
+    ram_wifi  (wxa)   : ORIGIN = 0x23010000, LENGTH = 160K - __EM_SIZE
 }
 
 SECTIONS
 {
 
+    BOOT2_PT_ADDR = 0x63027c00;
+
+    .fw_header :
+    {
+        KEEP(*(.fw_header))
+    } > fw_header_memory
+
+    .init :
+    {
+        KEEP (*(SORT_NONE(.init)))
+        KEEP (*(SORT_NONE(.vector)))
+
+    } > xip_memory
+
+    .rftlv.tool :
+    {
+        . = ORIGIN(xip_memory) + __RFTLV_SIZE_OFFSET;
+        PROVIDE( _ld_symbol_rftlv_address = . );
+        LONG(__RFTLV_HEAD1_H);
+        LONG(__RFTLV_HEAD1_L);
+        . = ORIGIN(xip_memory) + __RFTLV_SIZE_OFFSET + __RFTLV_SIZE_HOLE;
+    } > xip_memory
+
     .text :
     {
         . = ALIGN(4);
         __text_code_start__ = .;
-        KEEP(*startup*.*o(*.text*))
-        KEEP (*(SORT_NONE(_start)))
-        KEEP (*(SORT_NONE(Reset_Handler)))
 
         *(.text)
         *(.text.*)
 
-        /* section information for shell */
-        . = ALIGN(8);
+        /* section information for finsh shell */
+        . = ALIGN(4);
         __fsymtab_start = .;
         KEEP(*(FSymTab))
         __fsymtab_end = .;
-
         . = ALIGN(4);
         __vsymtab_start = .;
         KEEP(*(VSymTab))
         __vsymtab_end = .;
+        . = ALIGN(4);
 
-        /* section information for usb desc */
+        /* section information for modules */
         . = ALIGN(4);
-        _usb_desc_start = .;
-        KEEP(*(usb_desc))
+        __rtmsymtab_start = .;
+        KEEP(*(RTMSymTab))
+        __rtmsymtab_end = .;
+
+        /* section information for initialization */
         . = ALIGN(4);
-        _usb_desc_end = .;
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+
+        /* section information for usb usbh_class_info */
+        . = ALIGN(4);
+        __usbh_class_info_start__ = .;
+        KEEP(*(.usbh_class_info))
+        . = ALIGN(4);
+        __usbh_class_info_end__ = .;
 
         /*put .rodata**/
-        *(EXCLUDE_FILE( *bl808_glb*.o* \
-                        *bl808_glb_gpio*.o* \
-                        *bl808_pds*.o* \
-                        *bl808_aon*.o* \
-                        *bl808_hbn*.o* \
-                        *bl808_l1c*.o* \
-                        *bl808_common*.o* \
-                        *bl808_clock*.o* \
-                        *bl808_ef_ctrl*.o* \
-                        *bl808_sf_cfg*.o* \
-                        *bl808_sf_ctrl*.o* \
-                        *bl808_sflash*.o* \
-                        *bl808_xip_sflash*.o* \
-                        *bl808_romapi_patch*.o* ) .rodata*)
+        *(EXCLUDE_FILE( *bl616_glb*.o* \
+                        *bl616_pds*.o* \
+                        *bl616_common*.o* \
+                        *bl616_sf_cfg*.o* \
+                        *bl616_sf_ctrl*.o* \
+                        *bl616_sflash*.o* \
+                        *bl616_xip_sflash*.o* \
+                        *bl616_ef_ctrl*.o* \
+                        *bl616_romapi_patch*.o* ).rodata*)
 
         *(.srodata)
         *(.srodata.*)
@@ -98,20 +133,15 @@ SECTIONS
         *(.sclock_rlt_code.*)
         *(.sclock_rlt_const.*)
 
-        *bl808_glb*.o*(.rodata*)
-        *bl808_glb_gpio*.o*(.rodata*)
-        *bl808_pds*.o*(.rodata*)
-        *bl808_aon*.o*(.rodata*)
-        *bl808_hbn*.o*(.rodata*)
-        *bl808_l1c*.o*(.rodata*)
-        *bl808_common*.o*(.rodata*)
-        *bl808_clock*.o*(.rodata*)
-        *bl808_ef_ctrl*.o*(.rodata*)
-        *bl808_sf_cfg*.o*(.rodata*)
-        *bl808_sf_ctrl*.o*(.rodata*)
-        *bl808_sflash*.o*(.rodata*)
-        *bl808_xip_sflash*.o*(.rodata*)
-        *bl808_romapi_patch*.o*(.rodata*)
+        *bl616_glb*.o*(.rodata*)
+        *bl616_pds*.o*(.rodata*)
+        *bl616_common*.o*(.rodata*)
+        *bl616_sf_cfg*.o*(.rodata*)
+        *bl616_sf_ctrl*.o*(.rodata*)
+        *bl616_sflash*.o*(.rodata*)
+        *bl616_xip_sflash*.o*(.rodata*)
+        *bl616_ef_ctrl*.o*(.rodata*)
+        *bl616_romapi_patch*.o*(.rodata*)
 
         . = ALIGN(4);
         __tcm_code_end__ = .;
@@ -146,14 +176,17 @@ SECTIONS
      * size of stack_dummy section */
     __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);
     PROVIDE( __freertos_irq_stack_top = __StackTop);
+    PROVIDE( __rt_rvstack = . );
     __StackLimit = __StackTop - SIZEOF(.stack_dummy);
 
     /* Check if data + heap + stack exceeds RAM limit */
     ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack")
+
     /*************************************************************************/
+
     __nocache_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
 
-    .nocache_ram_region (NOLOAD) : AT (__nocache_ram_load_addr)
+    .nocache_ram_region  : AT (__nocache_ram_load_addr)
     {
         . = ALIGN(4);
         __nocache_ram_data_start__ = .;
@@ -164,28 +197,7 @@ SECTIONS
         __nocache_ram_data_end__ = .;
     } > nocache_ram_memory
 
-    __system_ram_load_addr = __nocache_ram_load_addr + SIZEOF(.nocache_ram_region);
-
-    .system_ram_data_region : AT (__system_ram_load_addr)
-    {
-        . = ALIGN(4);
-        __system_ram_data_start__ = .;
-
-        *(.system_ram)
-
-        . = ALIGN(4);
-        __system_ram_data_end__ = .;
-    } > ram_memory
-
-    .system_ram_noinit_data_region (NOLOAD) :
-    {
-        . = ALIGN(4);
-        *(.system_ram_noinit)
-
-        . = ALIGN(4);
-    } > ram_memory
-
-    __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region);
+    __ram_load_addr = __nocache_ram_load_addr + SIZEOF(.nocache_ram_region);
 
     /* Data section */
     RAM_DATA : AT (__ram_load_addr)
@@ -203,6 +215,10 @@ SECTIONS
         *(.sdata2.*)
 
         . = ALIGN(4);
+        __bflog_tags_start__ = .;
+        *(.bflog_tags_array)
+        . = ALIGN(4);
+        __bflog_tags_end__ = .;
         __ram_data_end__ = .;
     } > ram_memory
 
@@ -236,12 +252,13 @@ SECTIONS
     .nocache_noinit_ram_region (NOLOAD) :
     {
         . = ALIGN(4);
-        __nocache_ram_data_start__ = .;
+        __nocache_noinit_ram_data_start__ = .;
 
         *(.nocache_noinit_ram)
+        *(.noncacheable)
 
         . = ALIGN(4);
-        __nocache_ram_data_end__ = .;
+        __nocache_noinit_ram_data_end__ = .;
     } > nocache_ram_memory
 
     .heap (NOLOAD):
@@ -260,5 +277,43 @@ SECTIONS
     __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory);
     ASSERT(__HeapLimit - __HeapBase >= HeapMinSize, "heap region overflow")
 
+    .psmram_data (NOLOAD):
+    {
+        . = ALIGN(4);
+        __psram_data_start__ = .;
+
+        /*__end__ = .;*/
+        /*end = __end__;*/
+        KEEP(*(.psram_data*))
+        KEEP(*(.img_buf*))
+
+        . = ALIGN(4);
+        __psram_data_end__ = .;
+    } > ram_code
+
+    .wifibss (NOLOAD) :
+    {
+      PROVIDE( __wifi_bss_start = ADDR(.wifibss) );
+      PROVIDE( __wifi_bss_end = ADDR(.wifibss) + SIZEOF(.wifibss) );
+      _sshram = . ;
+      *(SHAREDRAMIPC)
+      *(SHAREDRAM)
+      _eshram = . ;
+      *ipc_shared.o(COMMON)
+      *sdu_shared.o(COMMON)
+      *hal_desc.o(COMMON)
+      *txl_buffer_shared.o(COMMON)
+      *txl_frame_shared.o(COMMON)
+      *scan_shared.o(COMMON)
+      *scanu_shared.o(COMMON)
+      *mfp_bip.o(COMMON)
+      *me_mic.o(COMMON)
+      *(.wifi_ram*)
+      . = ALIGN(16);
+    } > ram_wifi
+
+    PROVIDE( _heap_wifi_start = . );
+    PROVIDE( _heap_wifi_size = ORIGIN(ram_wifi) + LENGTH(ram_wifi) - _heap_wifi_start );
+
 }
 
diff --git a/bsp/bouffalo_lab/bl61x/board/trap_gcc.S b/bsp/bouffalo_lab/bl61x/board/trap_gcc.S
new file mode 100755
index 0000000000..a255ed7d09
--- /dev/null
+++ b/bsp/bouffalo_lab/bl61x/board/trap_gcc.S
@@ -0,0 +1,17 @@
+#include "cpuport.h"
+
+	.globl rt_hw_do_after_save_above
+	.type rt_hw_do_after_save_above,@function
+rt_hw_do_after_save_above:
+    addi  sp, sp,  -4
+    STORE ra,  0 * REGBYTES(sp)
+
+	csrr    t1, mcause
+    andi    t1, t1, 0x3FF
+    /* get ISR */
+    la      t2, interrupt_entry
+    jalr    t2
+    
+    LOAD  ra,  0 * REGBYTES(sp)
+    addi  sp, sp,  4
+    ret
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/bl61x/combine.sh b/bsp/bouffalo_lab/bl61x/combine.sh
new file mode 100755
index 0000000000..11a925dff0
--- /dev/null
+++ b/bsp/bouffalo_lab/bl61x/combine.sh
@@ -0,0 +1,39 @@
+#/bin/sh
+CHIPNAME=$1
+BIN_FILE=$2
+
+set -e
+
+SYSTEM=`uname -s`
+echo "system: $SYSTEM"
+
+CONFIG=./board/config
+TOOL_DIR=../libraries/bl_mcu_sdk/tools/bflb_tools/bflb_fw_post_proc
+
+if [ $SYSTEM = "Darwin" ]
+then
+    TOOL_NAME=bflb_fw_post_proc-macos
+    TOOL_ADDR=https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc-macos
+elif [ $SYSTEM = "Linux" ]
+then
+    TOOL_NAME=bflb_fw_post_proc-ubuntu
+    TOOL_ADDR=https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc-ubuntu
+else
+    TOOL_NAME=bflb_fw_post_proc.exe
+    TOOL_ADDR=https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc.exe
+fi
+
+if [ -f "$TOOL_DIR/$TOOL_NAME" ]
+then
+    echo "bflb_fw_post_proc exist"
+else
+    echo "bflb_fw_post_proc not exist, try download... url:$TOOL_ADDR"
+    curl $TOOL_ADDR -o $TOOL_DIR/$TOOL_NAME
+    if [ $SYSTEM = "Darwin" ]; then
+        chmod +x $TOOL_DIR/$TOOL_NAME
+    elif [ $SYSTEM = "Linux" ]; then
+        chmod +x $TOOL_DIR/$TOOL_NAME
+    fi
+fi
+
+./$TOOL_DIR/$TOOL_NAME --chipname=$CHIPNAME --brdcfgdir=$CONFIG --imgfile=$BIN_FILE
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/bl61x/flash_prog_cfg.ini b/bsp/bouffalo_lab/bl61x/flash_prog_cfg.ini
new file mode 100755
index 0000000000..41aaca3979
--- /dev/null
+++ b/bsp/bouffalo_lab/bl61x/flash_prog_cfg.ini
@@ -0,0 +1,12 @@
+[cfg]
+# 0: no erase, 1:programmed section erase, 2: chip erase
+erase = 2
+# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated
+skip_mode = 0x0, 0x0
+# 0: not use isp mode, #1: isp mode
+boot2_isp_mode = 0
+
+[FW]
+filedir = ./rtthread.bin
+address = 0x000000
+
diff --git a/bsp/bouffalo_lab/bl61x/rtconfig.h b/bsp/bouffalo_lab/bl61x/rtconfig.h
new file mode 100644
index 0000000000..76ba4e227d
--- /dev/null
+++ b/bsp/bouffalo_lab/bl61x/rtconfig.h
@@ -0,0 +1,244 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Project Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 8
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 1000
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_HOOK_USING_FUNC_PTR
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 512
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 512
+
+/* kservice optimization */
+
+#define RT_KSERVICE_USING_STDLIB
+#define RT_DEBUG
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_PAGE_MAX_ORDER 11
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_SMALL_MEM_AS_HEAP
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart0"
+#define RT_VER_NUM 0x50000
+#define ARCH_RISCV
+#define ARCH_RISCV_FPU
+#define ARCH_RISCV_FPU_S
+#define ARCH_RISCV32
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+#define RT_USING_MSH
+#define RT_USING_FINSH
+#define FINSH_USING_MSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_CMD_SIZE 80
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
+#define FINSH_ARG_MAX 10
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_UNAMED_PIPE_NUMBER 64
+#define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+
+/* Using USB */
+
+
+/* C/C++ and POSIX layer */
+
+#define RT_LIBC_DEFAULT_TIMEZONE 8
+
+/* POSIX (Portable Operating System Interface) layer */
+
+
+/* Interprocess Communication (IPC) */
+
+
+/* Socket is in the 'Network' category */
+
+
+/* Network */
+
+
+/* Utilities */
+
+
+/* RT-Thread Utestcases */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
+
+
+/* XML: Extensible Markup Language */
+
+
+/* multimedia packages */
+
+/* LVGL: powerful and easy-to-use embedded GUI library */
+
+
+/* u8g2: a monochrome graphic library */
+
+
+/* PainterEngine: A cross-platform graphics application framework written in C language */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+/* enhanced kernel services */
+
+
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+
+/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
+/* peripheral libraries and drivers */
+
+/* sensors drivers */
+
+
+/* touch drivers */
+
+
+/* Kendryte SDK */
+
+
+/* AI packages */
+
+
+/* Signal Processing and Control Algorithm Packages */
+
+
+/* miscellaneous packages */
+
+/* project laboratory */
+
+/* samples: kernel and components samples */
+
+
+/* entertainment: terminal games and other interesting software packages */
+
+
+/* Arduino libraries */
+
+
+/* Projects */
+
+
+/* Sensors */
+
+
+/* Display */
+
+
+/* Timing */
+
+
+/* Data Processing */
+
+
+/* Data Storage */
+
+/* Communication */
+
+
+/* Device Control */
+
+
+/* Other */
+
+
+/* Signal IO */
+
+
+/* Uncategorized */
+
+#define BSP_USING_BL61X
+#define BSP_USING_ROMAPI
+
+/* General Drivers Configuration */
+
+#define BSP_USING_GPIO
+
+/* General Purpose UARTs */
+
+#define BSP_USING_UART0
+#define UART0_TX_USING_GPIO21
+#define UART0_RX_USING_GPIO22
+#define BSP_USING_UART1
+#define UART1_TX_USING_GPIO16
+#define UART1_RX_USING_GPIO17
+
+#endif
diff --git a/bsp/bouffalo_lab/bl61x/rtconfig.py b/bsp/bouffalo_lab/bl61x/rtconfig.py
new file mode 100755
index 0000000000..1e198c0943
--- /dev/null
+++ b/bsp/bouffalo_lab/bl61x/rtconfig.py
@@ -0,0 +1,62 @@
+import os
+
+# toolchains options
+ARCH        ='risc-v'
+CPU         ='e9xx'
+CROSS_TOOL  ='gcc'
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = r'../../..'
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+if  CROSS_TOOL == 'gcc':
+    PLATFORM    = 'gcc'
+    EXEC_PATH   = r'/opt/Xuantie-900-gcc-elf-newlib-x86_64-V2.6.1/bin'
+else:
+    print('Please make sure your toolchains is GNU GCC!')
+    exit(0)
+
+if os.getenv('RTT_EXEC_PATH'):
+    EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX  = 'riscv64-unknown-elf-'
+    CC      = PREFIX + 'gcc'
+    CXX     = PREFIX + 'g++'
+    AS      = PREFIX + 'gcc'
+    AR      = PREFIX + 'ar'
+    LINK    = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE    = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY  = PREFIX + 'objcopy'
+
+    DEVICE  = ' -march=rv32imafcpzpsfoperand_xtheade -mabi=ilp32f -mtune=e907'
+    CFLAGS  = DEVICE + ' -std=gnu99 -fno-jump-tables -fno-common -fms-extensions -ffunction-sections -fdata-sections -fmessage-length=0 -Wall -Wchar-subscripts -Wformat -Wundef -Wuninitialized -Winit-self -Wignored-qualifiers'
+    CFLAGS += ' -fstrict-volatile-bitfields -fshort-enums -Wno-error=unused-variable -Wno-error=format= -Wno-error=unused-function -Wno-error=implicit-function-declaration -Wno-error=deprecated-declarations -Wno-format'
+
+    LINKER_SCRIPTS = r'board/linker_scripts/bl616_flash.ld'
+
+    AFLAGS  = ' -c' + DEVICE + ' -x assembler-with-cpp'
+    LFLAGS  = DEVICE + ' -nostartfiles -ufw_header -fms-extensions -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T ' + LINKER_SCRIPTS
+    CPATH   = ''
+    LPATH   = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -g3'
+        AFLAGS += ' -g3'
+    else:
+        CFLAGS += ' -O3'
+
+    CXXFLAGS = CFLAGS + ' -std=gnu++17 -Wno-multichar'
+
+DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
+POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+POST_ACTION += 'sh combine.sh bl616 ./rtthread.bin\n'
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/bl70x/.config b/bsp/bouffalo_lab/bl70x/.config
new file mode 100755
index 0000000000..65389f321a
--- /dev/null
+++ b/bsp/bouffalo_lab/bl70x/.config
@@ -0,0 +1,1001 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Project Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=8
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=1000
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_HOOK_USING_FUNC_PTR=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=1024
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
+
+#
+# kservice optimization
+#
+CONFIG_RT_KSERVICE_USING_STDLIB=y
+# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_TINY_FFS is not set
+# CONFIG_RT_KPRINTF_USING_LONGLONG is not set
+CONFIG_RT_DEBUG=y
+# CONFIG_RT_DEBUG_COLOR is not set
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_PAGE_MAX_ORDER=11
+CONFIG_RT_USING_MEMPOOL=y
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMHEAP is not set
+CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_SLAB_AS_HEAP is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+# CONFIG_RT_USING_HEAP_ISR is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_DM is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
+CONFIG_RT_VER_NUM=0x50000
+# CONFIG_RT_USING_CACHE is not set
+# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+# CONFIG_RT_USING_CPU_FFS is not set
+CONFIG_ARCH_RISCV=y
+CONFIG_ARCH_RISCV_FPU=y
+CONFIG_ARCH_RISCV_FPU_S=y
+CONFIG_ARCH_RISCV32=y
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+# CONFIG_RT_USING_LEGACY is not set
+CONFIG_RT_USING_MSH=y
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_ARG_MAX=10
+# CONFIG_RT_USING_DFS is not set
+# CONFIG_RT_USING_FAL is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_UNAMED_PIPE_NUMBER=64
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_USING_SERIAL_V1=y
+# CONFIG_RT_USING_SERIAL_V2 is not set
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+# CONFIG_RT_USING_NULL is not set
+# CONFIG_RT_USING_ZERO is not set
+# CONFIG_RT_USING_RANDOM is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_FDT is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_LCD is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_DEV_BUS is not set
+# CONFIG_RT_USING_WIFI is not set
+# CONFIG_RT_USING_VIRTIO is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB is not set
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# C/C++ and POSIX layer
+#
+CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
+
+#
+# POSIX (Portable Operating System Interface) layer
+#
+# CONFIG_RT_USING_POSIX_FS is not set
+# CONFIG_RT_USING_POSIX_DELAY is not set
+# CONFIG_RT_USING_POSIX_CLOCK is not set
+# CONFIG_RT_USING_POSIX_TIMER is not set
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Interprocess Communication (IPC)
+#
+# CONFIG_RT_USING_POSIX_PIPE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
+
+#
+# Socket is in the 'Network' category
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Network
+#
+# CONFIG_RT_USING_SAL is not set
+# CONFIG_RT_USING_NETDEV is not set
+# CONFIG_RT_USING_LWIP is not set
+# CONFIG_RT_USING_AT is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_VAR_EXPORT is not set
+# CONFIG_RT_USING_ADT is not set
+# CONFIG_RT_USING_RT_LINK is not set
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LWIP is not set
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_EZ_IOT_OS is not set
+# CONFIG_PKG_USING_IOTSHARP_SDK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_RYANMQTT is not set
+# CONFIG_PKG_USING_RYANW5500 is not set
+# CONFIG_PKG_USING_LORA_PKT_FWD is not set
+# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
+# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
+# CONFIG_PKG_USING_HM is not set
+# CONFIG_PKG_USING_SMALL_MODBUS is not set
+# CONFIG_PKG_USING_NET_SERVER is not set
+# CONFIG_PKG_USING_ZFTP is not set
+# CONFIG_PKG_USING_WOL is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_LIBSODIUM is not set
+# CONFIG_PKG_USING_LIBHYDROGEN is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+
+#
+# language packages
+#
+
+#
+# JSON: JavaScript Object Notation, a lightweight data-interchange format
+#
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PARSON is not set
+
+#
+# XML: Extensible Markup Language
+#
+# CONFIG_PKG_USING_SIMPLE_XML is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_LUATOS_SOC is not set
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
+# CONFIG_PKG_USING_RTT_RUST is not set
+
+#
+# multimedia packages
+#
+
+#
+# LVGL: powerful and easy-to-use embedded GUI library
+#
+# CONFIG_PKG_USING_LVGL is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
+# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
+
+#
+# u8g2: a monochrome graphic library
+#
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+# CONFIG_PKG_USING_UGUI is not set
+
+#
+# PainterEngine: A cross-platform graphics application framework written in C language
+#
+# CONFIG_PKG_USING_PAINTERENGINE is not set
+# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_GUIENGINE is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
+# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+# CONFIG_PKG_USING_FDT is not set
+# CONFIG_PKG_USING_CBOX is not set
+# CONFIG_PKG_USING_SNOWFLAKE is not set
+# CONFIG_PKG_USING_HASH_MATCH is not set
+# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
+# CONFIG_PKG_USING_VOFA_PLUS is not set
+
+#
+# system packages
+#
+
+#
+# enhanced kernel services
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+
+#
+# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+#
+# CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_PERF_COUNTER is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+# CONFIG_PKG_USING_TINYUSB is not set
+# CONFIG_PKG_USING_CHERRYUSB is not set
+# CONFIG_PKG_USING_KMULTI_RTIMER is not set
+# CONFIG_PKG_USING_TFDB is not set
+# CONFIG_PKG_USING_QPC is not set
+# CONFIG_PKG_USING_AGILE_UPGRADE is not set
+# CONFIG_PKG_USING_FLASH_BLOB is not set
+
+#
+# peripheral libraries and drivers
+#
+
+#
+# sensors drivers
+#
+# CONFIG_PKG_USING_LSM6DSM is not set
+# CONFIG_PKG_USING_LSM6DSL is not set
+# CONFIG_PKG_USING_LPS22HB is not set
+# CONFIG_PKG_USING_HTS221 is not set
+# CONFIG_PKG_USING_LSM303AGR is not set
+# CONFIG_PKG_USING_BME280 is not set
+# CONFIG_PKG_USING_BME680 is not set
+# CONFIG_PKG_USING_BMA400 is not set
+# CONFIG_PKG_USING_BMI160_BMX160 is not set
+# CONFIG_PKG_USING_SPL0601 is not set
+# CONFIG_PKG_USING_MS5805 is not set
+# CONFIG_PKG_USING_DA270 is not set
+# CONFIG_PKG_USING_DF220 is not set
+# CONFIG_PKG_USING_HSHCAL001 is not set
+# CONFIG_PKG_USING_BH1750 is not set
+# CONFIG_PKG_USING_MPU6XXX is not set
+# CONFIG_PKG_USING_AHT10 is not set
+# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_TSL4531 is not set
+# CONFIG_PKG_USING_DS18B20 is not set
+# CONFIG_PKG_USING_DHT11 is not set
+# CONFIG_PKG_USING_DHTXX is not set
+# CONFIG_PKG_USING_GY271 is not set
+# CONFIG_PKG_USING_GP2Y10 is not set
+# CONFIG_PKG_USING_SGP30 is not set
+# CONFIG_PKG_USING_HDC1000 is not set
+# CONFIG_PKG_USING_BMP180 is not set
+# CONFIG_PKG_USING_BMP280 is not set
+# CONFIG_PKG_USING_SHTC1 is not set
+# CONFIG_PKG_USING_BMI088 is not set
+# CONFIG_PKG_USING_HMC5883 is not set
+# CONFIG_PKG_USING_MAX6675 is not set
+# CONFIG_PKG_USING_TMP1075 is not set
+# CONFIG_PKG_USING_SR04 is not set
+# CONFIG_PKG_USING_CCS811 is not set
+# CONFIG_PKG_USING_PMSXX is not set
+# CONFIG_PKG_USING_RT3020 is not set
+# CONFIG_PKG_USING_MLX90632 is not set
+# CONFIG_PKG_USING_MLX90393 is not set
+# CONFIG_PKG_USING_MLX90392 is not set
+# CONFIG_PKG_USING_MLX90397 is not set
+# CONFIG_PKG_USING_MS5611 is not set
+# CONFIG_PKG_USING_MAX31865 is not set
+# CONFIG_PKG_USING_VL53L0X is not set
+# CONFIG_PKG_USING_INA260 is not set
+# CONFIG_PKG_USING_MAX30102 is not set
+# CONFIG_PKG_USING_INA226 is not set
+# CONFIG_PKG_USING_LIS2DH12 is not set
+# CONFIG_PKG_USING_HS300X is not set
+# CONFIG_PKG_USING_ZMOD4410 is not set
+# CONFIG_PKG_USING_ISL29035 is not set
+# CONFIG_PKG_USING_MMC3680KJ is not set
+# CONFIG_PKG_USING_QMP6989 is not set
+# CONFIG_PKG_USING_BALANCE is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_ADT74XX is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_CW2015 is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_STHS34PF80 is not set
+
+#
+# touch drivers
+#
+# CONFIG_PKG_USING_GT9147 is not set
+# CONFIG_PKG_USING_GT1151 is not set
+# CONFIG_PKG_USING_GT917S is not set
+# CONFIG_PKG_USING_GT911 is not set
+# CONFIG_PKG_USING_FT6206 is not set
+# CONFIG_PKG_USING_FT5426 is not set
+# CONFIG_PKG_USING_FT6236 is not set
+# CONFIG_PKG_USING_XPT2046_TOUCH is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ESP_IDF is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+
+#
+# Kendryte SDK
+#
+# CONFIG_PKG_USING_K210_SDK is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_MULTI_INFRARED is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_NUCLEI_SDK is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
+# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
+# CONFIG_PKG_USING_BL_MCU_SDK is not set
+# CONFIG_PKG_USING_SOFT_SERIAL is not set
+# CONFIG_PKG_USING_MB85RS16 is not set
+# CONFIG_PKG_USING_RFM300 is not set
+# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
+# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
+# CONFIG_PKG_USING_FINGERPRINT is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+
+#
+# Signal Processing and Control Algorithm Packages
+#
+# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
+# CONFIG_PKG_USING_UKAL is not set
+
+#
+# miscellaneous packages
+#
+
+#
+# project laboratory
+#
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_HEATSHRINK is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
+# CONFIG_PKG_USING_MFBD is not set
+# CONFIG_PKG_USING_SLCAN2RTT is not set
+# CONFIG_PKG_USING_SOEM is not set
+# CONFIG_PKG_USING_QPARAM is not set
+# CONFIG_PKG_USING_CorevMCU_CLI is not set
+
+#
+# Arduino libraries
+#
+# CONFIG_PKG_USING_RTDUINO is not set
+
+#
+# Projects
+#
+# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
+# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
+
+#
+# Sensors
+#
+# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
+# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
+# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
+# CONFIG_PKG_USING_SEEED_ITG3200 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
+# CONFIG_PKG_USING_SEEED_MP503 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
+
+#
+# Display
+#
+# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
+# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set
+# CONFIG_PKG_USING_SEEED_TM1637 is not set
+
+#
+# Timing
+#
+# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
+
+#
+# Data Processing
+#
+# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
+# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
+
+#
+# Data Storage
+#
+
+#
+# Communication
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
+
+#
+# Device Control
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
+
+#
+# Other
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
+# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
+
+#
+# Signal IO
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
+
+#
+# Uncategorized
+#
+CONFIG_BSP_USING_BL70X=y
+CONFIG_BSP_USING_ROMAPI=y
+# CONFIG_BSP_USING_PSRAM is not set
+
+#
+# General Drivers Configuration
+#
+CONFIG_BSP_USING_GPIO=y
+
+#
+# General Purpose UARTs
+#
+CONFIG_BSP_USING_UART0=y
+CONFIG_UART0_TX_USING_GPIO14=y
+# CONFIG_UART0_TX_USING_GPIO16 is not set
+# CONFIG_UART0_TX_USING_GPIO21 is not set
+# CONFIG_UART0_RX_USING_GPIO7 is not set
+# CONFIG_UART0_RX_USING_GPIO15 is not set
+# CONFIG_UART0_RX_USING_GPIO22 is not set
+CONFIG_UART0_RX_USING_GPIO23=y
+CONFIG_BSP_USING_UART1=y
+# CONFIG_UART1_TX_USING_GPIO4 is not set
+# CONFIG_UART1_TX_USING_GPIO16 is not set
+# CONFIG_UART1_TX_USING_GPIO18 is not set
+CONFIG_UART1_TX_USING_GPIO26=y
+# CONFIG_UART1_RX_USING_GPIO3 is not set
+# CONFIG_UART1_RX_USING_GPIO5 is not set
+# CONFIG_UART1_RX_USING_GPIO17 is not set
+# CONFIG_UART1_RX_USING_GPIO19 is not set
+CONFIG_UART1_RX_USING_GPIO27=y
diff --git a/bsp/bouffalo_lab/bl70x/Kconfig b/bsp/bouffalo_lab/bl70x/Kconfig
new file mode 100755
index 0000000000..c6ee6e58f8
--- /dev/null
+++ b/bsp/bouffalo_lab/bl70x/Kconfig
@@ -0,0 +1,26 @@
+mainmenu "RT-Thread Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+config LIBRARIES_DIR
+    string
+    option env="LIBRARIES_DIR"
+    default "../libraries"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "board/Kconfig"
+source "$LIBRARIES_DIR/Kconfig"
diff --git a/bsp/bouffalo_lab/bl70x/SConscript b/bsp/bouffalo_lab/bl70x/SConscript
new file mode 100755
index 0000000000..c7ef7659ec
--- /dev/null
+++ b/bsp/bouffalo_lab/bl70x/SConscript
@@ -0,0 +1,14 @@
+# for module compiling
+import os
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/bouffalo_lab/bl70x/SConstruct b/bsp/bouffalo_lab/bl70x/SConstruct
new file mode 100755
index 0000000000..da9ba9a91a
--- /dev/null
+++ b/bsp/bouffalo_lab/bl70x/SConstruct
@@ -0,0 +1,46 @@
+import os
+import sys
+import rtconfig
+
+from rtconfig import RTT_ROOT
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+env['ASCOM'] = env['ASPPCOM']
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+    libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False)
+
+# include libraries
+objs.extend(SConscript(libraries_path_prefix + '/bl_mcu_sdk/SConscript', variant_dir='build/libraries/bl_mcu_sdk', duplicate=0))
+
+# include drivers
+objs.extend(SConscript(libraries_path_prefix + '/rt_drivers/SConscript', variant_dir='build/libraries/rt_drivers', duplicate=0))
+
+
+# make a building
+DoBuilding(TARGET, objs)
diff --git a/bsp/bouffalo_lab/bl70x/applications/SConscript b/bsp/bouffalo_lab/bl70x/applications/SConscript
new file mode 100755
index 0000000000..c583d3016e
--- /dev/null
+++ b/bsp/bouffalo_lab/bl70x/applications/SConscript
@@ -0,0 +1,9 @@
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/bl808/m0/applications/main.c b/bsp/bouffalo_lab/bl70x/applications/main.c
similarity index 88%
rename from bsp/bl808/m0/applications/main.c
rename to bsp/bouffalo_lab/bl70x/applications/main.c
index 46101be0ad..6897456dde 100644
--- a/bsp/bl808/m0/applications/main.c
+++ b/bsp/bouffalo_lab/bl70x/applications/main.c
@@ -13,7 +13,7 @@
 
 int main(void)
 {
-    rt_kprintf("Hello, world\n");
+    rt_kprintf("Hello, RISC-V!\n");
 
     return 0;
 }
diff --git a/bsp/bouffalo_lab/bl70x/board/Kconfig b/bsp/bouffalo_lab/bl70x/board/Kconfig
new file mode 100755
index 0000000000..9bc940982c
--- /dev/null
+++ b/bsp/bouffalo_lab/bl70x/board/Kconfig
@@ -0,0 +1,16 @@
+config BSP_USING_BL70X
+    bool
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    select ARCH_RISCV32
+    select ARCH_RISCV_FPU_S
+    select BSP_USING_ROMAPI
+    default y
+
+config BSP_USING_ROMAPI
+    bool 
+    default y
+
+config BSP_USING_PSRAM
+    bool "Enable PSRAM"
+    default n
diff --git a/bsp/bouffalo_lab/bl70x/board/SConscript b/bsp/bouffalo_lab/bl70x/board/SConscript
new file mode 100755
index 0000000000..c0653a14cc
--- /dev/null
+++ b/bsp/bouffalo_lab/bl70x/board/SConscript
@@ -0,0 +1,9 @@
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*.S')
+CPPPATH = [cwd]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/bouffalo_lab/bl70x/board/board.c b/bsp/bouffalo_lab/bl70x/board/board.c
new file mode 100644
index 0000000000..0d2c02fe0c
--- /dev/null
+++ b/bsp/bouffalo_lab/bl70x/board/board.c
@@ -0,0 +1,197 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023/03/25     flyingcys    first version
+ */
+#include 
+#include 
+
+#include "board.h"
+#include "drv_uart.h"
+
+static void system_clock_init(void)
+{
+    GLB_Set_System_CLK(GLB_DLL_XTAL_32M, GLB_SYS_CLK_DLL144M);
+    GLB_Set_MTimer_CLK(1, GLB_MTIMER_CLK_BCLK, 71);
+}
+
+static void peripheral_clock_init(void)
+{
+    PERIPHERAL_CLOCK_ADC_DAC_ENABLE();
+    PERIPHERAL_CLOCK_SEC_ENABLE();
+    PERIPHERAL_CLOCK_DMA0_ENABLE();
+    PERIPHERAL_CLOCK_UART0_ENABLE();
+    PERIPHERAL_CLOCK_UART1_ENABLE();
+    PERIPHERAL_CLOCK_SPI0_ENABLE();
+    PERIPHERAL_CLOCK_I2C0_ENABLE();
+    PERIPHERAL_CLOCK_PWM0_ENABLE();
+    PERIPHERAL_CLOCK_TIMER0_1_WDG_ENABLE();
+    PERIPHERAL_CLOCK_IR_ENABLE();
+    PERIPHERAL_CLOCK_I2S_ENABLE();
+    PERIPHERAL_CLOCK_USB_ENABLE();
+    GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_CAM);
+
+    GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_96M, 0);
+    GLB_Set_SPI_CLK(ENABLE, 0);
+    GLB_Set_I2C_CLK(ENABLE, 0);
+    GLB_Set_IR_CLK(ENABLE, GLB_IR_CLK_SRC_XCLK, 15);
+
+    GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, 1);
+    GLB_Set_DAC_CLK(ENABLE, GLB_DAC_CLK_XCLK, 0x3E);
+
+    GLB_Set_USB_CLK(ENABLE);
+}
+
+#ifdef BSP_USING_PSRAM
+struct spi_psram_cfg_type ap_memory1604 = {
+    .read_id_cmd = 0x9F,
+    .read_id_dmy_clk = 0,
+    .burst_toggle_cmd = 0xC0,
+    .reset_enable_cmd = 0x66,
+    .reset_cmd = 0x99,
+    .enter_quad_mode_cmd = 0x35,
+    .exit_quad_mode_cmd = 0xF5,
+    .read_reg_cmd = 0xB5,
+    .read_reg_dmy_clk = 1,
+    .write_reg_cmd = 0xB1,
+    .read_cmd = 0x03,
+    .read_dmy_clk = 0,
+    .f_read_cmd = 0x0B,
+    .f_read_dmy_clk = 1,
+    .f_read_quad_cmd = 0xEB,
+    .f_read_quad_dmy_clk = 3,
+    .write_cmd = 0x02,
+    .quad_write_cmd = 0x38,
+    .page_size = 512,
+    .ctrl_mode = PSRAM_SPI_CTRL_MODE,
+    .drive_strength = PSRAM_DRIVE_STRENGTH_50_OHMS,
+    .burst_length = PSRAM_BURST_LENGTH_512_BYTES,
+};
+
+struct sf_ctrl_cmds_cfg cmds_cfg = {
+    .cmds_core_en = 1,
+    .cmds_en = 1,
+    .burst_toggle_en = 1,
+    .cmds_wrap_mode = 0,
+    .cmds_wrap_len = SF_CTRL_WRAP_LEN_512,
+};
+struct sf_ctrl_psram_cfg psram_cfg = {
+    .owner = SF_CTRL_OWNER_SAHB,
+    .pad_sel = SF_CTRL_SEL_DUAL_CS_SF2,
+    .bank_sel = SF_CTRL_SEL_PSRAM,
+    .psram_rx_clk_invert_src = 1,
+    .psram_rx_clk_invert_sel = 0,
+    .psram_delay_src = 1,
+    .psram_clk_delay = 1,
+};
+
+#define BFLB_EXTFLASH_CS_GPIO    GLB_GPIO_PIN_25
+#define BFLB_EXTPSRAM_CLK_GPIO   GLB_GPIO_PIN_27
+#define BFLB_EXTPSRAM_CS_GPIO    GLB_GPIO_PIN_17
+#define BFLB_EXTPSRAM_DATA0_GPIO GLB_GPIO_PIN_28
+#define BFLB_EXTPSRAM_DATA1_GPIO GLB_GPIO_PIN_24
+#define BFLB_EXTPSRAM_DATA2_GPIO GLB_GPIO_PIN_23
+#define BFLB_EXTPSRAM_DATA3_GPIO GLB_GPIO_PIN_26
+
+void ATTR_TCM_SECTION psram_gpio_init(void)
+{
+    GLB_GPIO_Cfg_Type cfg;
+    uint8_t gpiopins[7];
+    uint8_t i = 0;
+
+    cfg.gpioMode = GPIO_MODE_AF;
+    cfg.pullType = GPIO_PULL_UP;
+    cfg.drive = 3;
+    cfg.smtCtrl = 1;
+    cfg.gpioFun = GPIO_FUN_FLASH_PSRAM;
+
+    gpiopins[0] = BFLB_EXTPSRAM_CLK_GPIO;
+    gpiopins[1] = BFLB_EXTPSRAM_CS_GPIO;
+    gpiopins[2] = BFLB_EXTPSRAM_DATA0_GPIO;
+    gpiopins[3] = BFLB_EXTPSRAM_DATA1_GPIO;
+    gpiopins[4] = BFLB_EXTPSRAM_DATA2_GPIO;
+    gpiopins[5] = BFLB_EXTPSRAM_DATA3_GPIO;
+    gpiopins[6] = BFLB_EXTFLASH_CS_GPIO;
+
+    for (i = 0; i < sizeof(gpiopins); i++) {
+        cfg.gpioPin = gpiopins[i];
+
+        if (i == 0 || i == 1 || i == 6) {
+            /*flash clk and cs is output*/
+            cfg.gpioMode = GPIO_MODE_OUTPUT;
+        } else {
+            /*data are bidir*/
+            cfg.gpioMode = GPIO_MODE_AF;
+        }
+
+        GLB_GPIO_Init(&cfg);
+    }
+}
+
+uint8_t psramId[8] = { 0 };
+
+void ATTR_TCM_SECTION board_psram_init(void)
+{
+    psram_gpio_init();
+
+    bflb_psram_init(&ap_memory1604, &cmds_cfg, &psram_cfg);
+
+    bflb_psram_softwarereset(&ap_memory1604, ap_memory1604.ctrl_mode);
+
+    bflb_psram_readid(&ap_memory1604, psramId);
+    bflb_psram_cache_write_set(&ap_memory1604, SF_CTRL_QIO_MODE, ENABLE, DISABLE, DISABLE);
+    L1C_Cache_Enable_Set(L1C_WAY_DISABLE_NONE);
+}
+#endif
+
+/* This is the timer interrupt service routine. */
+static void systick_isr(void)
+{
+    rt_tick_increase();
+}
+
+void rt_hw_board_init(void)
+{
+    bflb_flash_init();
+
+    system_clock_init();
+    peripheral_clock_init();
+    bflb_irq_initialize();
+
+    bflb_mtimer_config(HW_MTIMER_CLOCK / RT_TICK_PER_SECOND, systick_isr);
+
+#ifdef RT_USING_HEAP
+    /* initialize memory system */
+    rt_kprintf("RT_HW_HEAP_BEGIN:%x RT_HW_HEAP_END:%x\r\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
+    rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
+#endif
+
+    /* UART driver initialization is open by default */
+#ifdef RT_USING_SERIAL
+    rt_hw_uart_init();
+#endif
+
+#ifdef BSP_USING_PSRAM
+    board_psram_init();
+#endif
+
+    /* Set the shell console output device */
+#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}
+
+void rt_hw_cpu_reset(void)
+{
+    GLB_SW_POR_Reset();
+}
+
+MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reset machine);
diff --git a/bsp/bouffalo_lab/bl70x/board/board.h b/bsp/bouffalo_lab/bl70x/board/board.h
new file mode 100644
index 0000000000..4d337e73d6
--- /dev/null
+++ b/bsp/bouffalo_lab/bl70x/board/board.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023/03/15     flyingcys    first version
+ */
+
+#ifndef BOARD_H__
+#define BOARD_H__
+
+#include 
+
+#include "bflb_uart.h"
+#include "bflb_gpio.h"
+#include "bflb_clock.h"
+#include "bflb_rtc.h"
+#include "bflb_flash.h"
+#include "bflb_spi_psram.h"
+#include "bl702_glb.h"
+
+#define     HW_MTIMER_CLOCK     1000000
+
+extern uint8_t __HeapBase;
+extern uint8_t __HeapLimit;
+
+#define RT_HW_HEAP_BEGIN    (void*)&__HeapBase
+#define RT_HW_HEAP_END      (void*)&__HeapLimit
+
+void rt_hw_board_init(void);
+
+#endif
diff --git a/bsp/bouffalo_lab/bl70x/board/builtin_imgs/boot2_bl702_debug_v8.0.7.bin b/bsp/bouffalo_lab/bl70x/board/builtin_imgs/boot2_bl702_debug_v8.0.7.bin
new file mode 100755
index 0000000000..6434eb8957
Binary files /dev/null and b/bsp/bouffalo_lab/bl70x/board/builtin_imgs/boot2_bl702_debug_v8.0.7.bin differ
diff --git a/bsp/bouffalo_lab/bl70x/board/builtin_imgs/boot2_bl702_release_v8.0.7.bin b/bsp/bouffalo_lab/bl70x/board/builtin_imgs/boot2_bl702_release_v8.0.7.bin
new file mode 100755
index 0000000000..00555439c1
Binary files /dev/null and b/bsp/bouffalo_lab/bl70x/board/builtin_imgs/boot2_bl702_release_v8.0.7.bin differ
diff --git a/bsp/bouffalo_lab/bl70x/board/builtin_imgs/mfg_bl702_stdfw.bin b/bsp/bouffalo_lab/bl70x/board/builtin_imgs/mfg_bl702_stdfw.bin
new file mode 100755
index 0000000000..cd374773f0
Binary files /dev/null and b/bsp/bouffalo_lab/bl70x/board/builtin_imgs/mfg_bl702_stdfw.bin differ
diff --git a/bsp/bouffalo_lab/bl70x/board/config/.gitkeep b/bsp/bouffalo_lab/bl70x/board/config/.gitkeep
new file mode 100755
index 0000000000..e69de29bb2
diff --git a/bsp/bouffalo_lab/bl70x/board/fw_header.c b/bsp/bouffalo_lab/bl70x/board/fw_header.c
new file mode 100644
index 0000000000..942edd6889
--- /dev/null
+++ b/bsp/bouffalo_lab/bl70x/board/fw_header.c
@@ -0,0 +1,126 @@
+#include "fw_header.h"
+
+__attribute__((section(".fw_header"))) struct bootheader_t fw_header = {
+    .magiccode = 0x504e4642,
+    .rivison = 0x00000001,
+    /*flash config */
+    .flash_cfg.magiccode = 0x47464346,
+    .flash_cfg.cfg.ioMode = 0x11,               /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
+    .flash_cfg.cfg.cReadSupport = 0x00,         /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
+    .flash_cfg.cfg.clkDelay = 0x01,             /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
+    .flash_cfg.cfg.clkInvert = 0x01,            /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
+    .flash_cfg.cfg.resetEnCmd = 0x66,           /*!< Flash enable reset command */
+    .flash_cfg.cfg.resetCmd = 0x99,             /*!< Flash reset command */
+    .flash_cfg.cfg.resetCreadCmd = 0xff,        /*!< Flash reset continuous read command */
+    .flash_cfg.cfg.resetCreadCmdSize = 0x03,    /*!< Flash reset continuous read command size */
+    .flash_cfg.cfg.jedecIdCmd = 0x9f,           /*!< JEDEC ID command */
+    .flash_cfg.cfg.jedecIdCmdDmyClk = 0x00,     /*!< JEDEC ID command dummy clock */
+    .flash_cfg.cfg.enter32BitsAddrCmd = 0xb7,   /*!< Enter 32-bits addr command */
+    .flash_cfg.cfg.exit32BitsAddrCmd = 0xe9,    /*!< Exit 32-bits addr command */
+    .flash_cfg.cfg.sectorSize = 0x04,           /*!< *1024bytes */
+    .flash_cfg.cfg.mid = 0xff,                  /*!< Manufacturer ID */
+    .flash_cfg.cfg.pageSize = 0x100,            /*!< Page size */
+    .flash_cfg.cfg.chipEraseCmd = 0xc7,         /*!< Chip erase cmd */
+    .flash_cfg.cfg.sectorEraseCmd = 0x20,       /*!< Sector erase command */
+    .flash_cfg.cfg.blk32EraseCmd = 0x52,        /*!< Block 32K erase command,some Micron not support */
+    .flash_cfg.cfg.blk64EraseCmd = 0xd8,        /*!< Block 64K erase command */
+    .flash_cfg.cfg.writeEnableCmd = 0x06,       /*!< Need before every erase or program */
+    .flash_cfg.cfg.pageProgramCmd = 0x02,       /*!< Page program cmd */
+    .flash_cfg.cfg.qpageProgramCmd = 0x32,      /*!< QIO page program cmd */
+    .flash_cfg.cfg.qppAddrMode = 0x00,          /*!< QIO page program address mode */
+    .flash_cfg.cfg.fastReadCmd = 0x0b,          /*!< Fast read command */
+    .flash_cfg.cfg.frDmyClk = 0x01,             /*!< Fast read command dummy clock */
+    .flash_cfg.cfg.qpiFastReadCmd = 0x0b,       /*!< QPI fast read command */
+    .flash_cfg.cfg.qpiFrDmyClk = 0x01,          /*!< QPI fast read command dummy clock */
+    .flash_cfg.cfg.fastReadDoCmd = 0x3b,        /*!< Fast read dual output command */
+    .flash_cfg.cfg.frDoDmyClk = 0x01,           /*!< Fast read dual output command dummy clock */
+    .flash_cfg.cfg.fastReadDioCmd = 0xbb,       /*!< Fast read dual io comamnd */
+    .flash_cfg.cfg.frDioDmyClk = 0x00,          /*!< Fast read dual io command dummy clock */
+    .flash_cfg.cfg.fastReadQoCmd = 0x6b,        /*!< Fast read quad output comamnd */
+    .flash_cfg.cfg.frQoDmyClk = 0x01,           /*!< Fast read quad output comamnd dummy clock */
+    .flash_cfg.cfg.fastReadQioCmd = 0xeb,       /*!< Fast read quad io comamnd */
+    .flash_cfg.cfg.frQioDmyClk = 0x02,          /*!< Fast read quad io comamnd dummy clock */
+    .flash_cfg.cfg.qpiFastReadQioCmd = 0xeb,    /*!< QPI fast read quad io comamnd */
+    .flash_cfg.cfg.qpiFrQioDmyClk = 0x02,       /*!< QPI fast read QIO dummy clock */
+    .flash_cfg.cfg.qpiPageProgramCmd = 0x02,    /*!< QPI program command */
+    .flash_cfg.cfg.writeVregEnableCmd = 0x50,   /*!< Enable write reg */
+    .flash_cfg.cfg.wrEnableIndex = 0x00,        /*!< Write enable register index */
+    .flash_cfg.cfg.qeIndex = 0x01,              /*!< Quad mode enable register index */
+    .flash_cfg.cfg.busyIndex = 0x00,            /*!< Busy status register index */
+    .flash_cfg.cfg.wrEnableBit = 0x01,          /*!< Write enable bit pos */
+    .flash_cfg.cfg.qeBit = 0x01,                /*!< Quad enable bit pos */
+    .flash_cfg.cfg.busyBit = 0x00,              /*!< Busy status bit pos */
+    .flash_cfg.cfg.wrEnableWriteRegLen = 0x02,  /*!< Register length of write enable */
+    .flash_cfg.cfg.wrEnableReadRegLen = 0x01,   /*!< Register length of write enable status */
+    .flash_cfg.cfg.qeWriteRegLen = 0x02,        /*!< Register length of contain quad enable */
+    .flash_cfg.cfg.qeReadRegLen = 0x01,         /*!< Register length of contain quad enable status */
+    .flash_cfg.cfg.releasePowerDown = 0xab,     /*!< Release power down command */
+    .flash_cfg.cfg.busyReadRegLen = 0x01,       /*!< Register length of contain busy status */
+    .flash_cfg.cfg.readRegCmd[0] = 0x05,        /*!< Read register command buffer */
+    .flash_cfg.cfg.readRegCmd[1] = 0x35,        /*!< Read register command buffer */
+    .flash_cfg.cfg.readRegCmd[2] = 0x00,        /*!< Read register command buffer */
+    .flash_cfg.cfg.readRegCmd[3] = 0x00,        /*!< Read register command buffer */
+    .flash_cfg.cfg.writeRegCmd[0] = 0x01,       /*!< Write register command buffer */
+    .flash_cfg.cfg.writeRegCmd[1] = 0x01,       /*!< Write register command buffer */
+    .flash_cfg.cfg.writeRegCmd[2] = 0x00,       /*!< Write register command buffer */
+    .flash_cfg.cfg.writeRegCmd[3] = 0x00,       /*!< Write register command buffer */
+    .flash_cfg.cfg.enterQpi = 0x38,             /*!< Enter qpi command */
+    .flash_cfg.cfg.exitQpi = 0xff,              /*!< Exit qpi command */
+    .flash_cfg.cfg.cReadMode = 0xa0,            /*!< Config data for continuous read mode */
+    .flash_cfg.cfg.cRExit = 0xff,               /*!< Config data for exit continuous read mode */
+    .flash_cfg.cfg.burstWrapCmd = 0x77,         /*!< Enable burst wrap command */
+    .flash_cfg.cfg.burstWrapCmdDmyClk = 0x03,   /*!< Enable burst wrap command dummy clock */
+    .flash_cfg.cfg.burstWrapDataMode = 0x02,    /*!< Data and address mode for this command */
+    .flash_cfg.cfg.burstWrapData = 0x40,        /*!< Data to enable burst wrap */
+    .flash_cfg.cfg.deBurstWrapCmd = 0x77,       /*!< Disable burst wrap command */
+    .flash_cfg.cfg.deBurstWrapCmdDmyClk = 0x03, /*!< Disable burst wrap command dummy clock */
+    .flash_cfg.cfg.deBurstWrapDataMode = 0x02,  /*!< Data and address mode for this command */
+    .flash_cfg.cfg.deBurstWrapData = 0xf0,      /*!< Data to disable burst wrap */
+    .flash_cfg.cfg.timeEsector = 300,           /*!< 4K erase time */
+    .flash_cfg.cfg.timeE32k = 1200,             /*!< 32K erase time */
+    .flash_cfg.cfg.timeE64k = 1200,             /*!< 64K erase time */
+    .flash_cfg.cfg.timePagePgm = 50,            /*!< Page program time */
+    .flash_cfg.cfg.timeCe = 30000,              /*!< Chip erase time in ms */
+    .flash_cfg.cfg.pdDelay = 20,                /*!< Release power down command delay time for wake up */
+    .flash_cfg.cfg.qeData = 0,                  /*!< QE set data */
+    .flash_cfg.crc32 = 0xdeadbeef,
+    /* clock cfg */
+    .clk_cfg.magiccode = 0x47464350,
+    .clk_cfg.cfg.xtal_type = 0x01, /*!<  0:Not use XTAL to set PLL, 1:XTAL is 32M, 2:XTAL is RC32M  */
+    .clk_cfg.cfg.pll_clk = 0x04,   /*!< mcu_clk 0:RC32M, 1:XTAL, 2:PLL 57.6M, 3:PLL 96M, 4:PLL 144M */
+    .clk_cfg.cfg.hclk_div = 0x00,
+    .clk_cfg.cfg.bclk_div = 0x01,
+    .clk_cfg.cfg.flash_clk_type = 0x01, /*!< 0:144M, 1:XCLK(RC32M or XTAL), 2:57.6M, 3:72M, 4:BCLK, 5:96M */
+    .clk_cfg.cfg.flash_clk_div = 0x00,
+    .clk_cfg.crc32 = 0xdeadbeef,
+
+    /* boot cfg */
+    .boot_cfg.bval.sign = 0x0,               /* [1: 0]      for sign*/
+    .boot_cfg.bval.encrypt_type = 0x0,       /* [3: 2]      for encrypt */
+    .boot_cfg.bval.key_sel = 0x01,           /* [5: 4]      for key sel in boot interface*/
+    .boot_cfg.bval.rsvd_7_6 = 0x0,           /* [7: 6]      for encrypt*/
+    .boot_cfg.bval.no_segment = 0x1,         /* [8]         no segment info */
+    .boot_cfg.bval.cache_select = 0x1,       /* [9]         for cache */
+    .boot_cfg.bval.notload_in_bootrom = 0x0, /* [10]        not load this img in bootrom */
+    .boot_cfg.bval.aes_region_lock = 0x0,    /* [11]        aes region lock */
+    .boot_cfg.bval.cache_way_disable = 0x0,  /* [15: 12]    cache way disable info*/
+    .boot_cfg.bval.crc_ignore = 0x1,         /* [16]        ignore crc */
+    .boot_cfg.bval.hash_ignore = 0x1,        /* [17]        hash crc */
+    .boot_cfg.bval.halt_ap = 0x0,            /* [18]        halt ap */
+    .boot_cfg.bval.boot2_enable = 0x00,      /* [19]     boot2 enable */
+    .boot_cfg.bval.boot2_rollback = 0x00,    /* [20]     boot2 rollback */
+    .boot_cfg.bval.rsvd_31_21 = 0x0,         /* [31:21]     rsvd */
+
+    .img_segment_info.img_len = 0x00010000, /* image length or segment count */
+    .rsvd0 = 0x00000000,
+#ifdef BFLB_BOOT2
+    .img_start.flashoffset = 0x00002000, /* flash controller offset */
+#else
+    .img_start.flashoffset = 0x00001000, /* flash controller offset */
+#endif
+    .hash = { 0xdeadbeef },              /* hash of the image */
+
+    .boot2_pt_table_0 = 0x1000, /* address of partition table 0 */
+    .boot2_pt_table_1 = 0x2000, /* address of partition table 1 */
+    .crc32 = 0xdeadbeef         /* 4 */
+};
diff --git a/bsp/bouffalo_lab/bl70x/board/fw_header.h b/bsp/bouffalo_lab/bl70x/board/fw_header.h
new file mode 100644
index 0000000000..bf0b90fa7c
--- /dev/null
+++ b/bsp/bouffalo_lab/bl70x/board/fw_header.h
@@ -0,0 +1,170 @@
+#ifndef __FW_HEADER_H__
+#define __FW_HEADER_H__
+
+#include "stdint.h"
+#include "stdio.h"
+
+struct __attribute__((packed, aligned(4))) spi_flash_cfg_t {
+    uint8_t ioMode;               /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
+    uint8_t cReadSupport;         /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
+    uint8_t clkDelay;             /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
+    uint8_t clkInvert;            /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
+    uint8_t resetEnCmd;           /*!< Flash enable reset command */
+    uint8_t resetCmd;             /*!< Flash reset command */
+    uint8_t resetCreadCmd;        /*!< Flash reset continuous read command */
+    uint8_t resetCreadCmdSize;    /*!< Flash reset continuous read command size */
+    uint8_t jedecIdCmd;           /*!< JEDEC ID command */
+    uint8_t jedecIdCmdDmyClk;     /*!< JEDEC ID command dummy clock */
+    uint8_t enter32BitsAddrCmd;   /*!< Enter 32-bits addr command */
+    uint8_t exit32BitsAddrCmd;    /*!< Exit 32-bits addr command */
+    uint8_t sectorSize;           /*!< *1024bytes */
+    uint8_t mid;                  /*!< Manufacturer ID */
+    uint16_t pageSize;            /*!< Page size */
+    uint8_t chipEraseCmd;         /*!< Chip erase cmd */
+    uint8_t sectorEraseCmd;       /*!< Sector erase command */
+    uint8_t blk32EraseCmd;        /*!< Block 32K erase command,some Micron not support */
+    uint8_t blk64EraseCmd;        /*!< Block 64K erase command */
+    uint8_t writeEnableCmd;       /*!< Need before every erase or program */
+    uint8_t pageProgramCmd;       /*!< Page program cmd */
+    uint8_t qpageProgramCmd;      /*!< QIO page program cmd */
+    uint8_t qppAddrMode;          /*!< QIO page program address mode */
+    uint8_t fastReadCmd;          /*!< Fast read command */
+    uint8_t frDmyClk;             /*!< Fast read command dummy clock */
+    uint8_t qpiFastReadCmd;       /*!< QPI fast read command */
+    uint8_t qpiFrDmyClk;          /*!< QPI fast read command dummy clock */
+    uint8_t fastReadDoCmd;        /*!< Fast read dual output command */
+    uint8_t frDoDmyClk;           /*!< Fast read dual output command dummy clock */
+    uint8_t fastReadDioCmd;       /*!< Fast read dual io comamnd */
+    uint8_t frDioDmyClk;          /*!< Fast read dual io command dummy clock */
+    uint8_t fastReadQoCmd;        /*!< Fast read quad output comamnd */
+    uint8_t frQoDmyClk;           /*!< Fast read quad output comamnd dummy clock */
+    uint8_t fastReadQioCmd;       /*!< Fast read quad io comamnd */
+    uint8_t frQioDmyClk;          /*!< Fast read quad io comamnd dummy clock */
+    uint8_t qpiFastReadQioCmd;    /*!< QPI fast read quad io comamnd */
+    uint8_t qpiFrQioDmyClk;       /*!< QPI fast read QIO dummy clock */
+    uint8_t qpiPageProgramCmd;    /*!< QPI program command */
+    uint8_t writeVregEnableCmd;   /*!< Enable write reg */
+    uint8_t wrEnableIndex;        /*!< Write enable register index */
+    uint8_t qeIndex;              /*!< Quad mode enable register index */
+    uint8_t busyIndex;            /*!< Busy status register index */
+    uint8_t wrEnableBit;          /*!< Write enable bit pos */
+    uint8_t qeBit;                /*!< Quad enable bit pos */
+    uint8_t busyBit;              /*!< Busy status bit pos */
+    uint8_t wrEnableWriteRegLen;  /*!< Register length of write enable */
+    uint8_t wrEnableReadRegLen;   /*!< Register length of write enable status */
+    uint8_t qeWriteRegLen;        /*!< Register length of contain quad enable */
+    uint8_t qeReadRegLen;         /*!< Register length of contain quad enable status */
+    uint8_t releasePowerDown;     /*!< Release power down command */
+    uint8_t busyReadRegLen;       /*!< Register length of contain busy status */
+    uint8_t readRegCmd[4];        /*!< Read register command buffer */
+    uint8_t writeRegCmd[4];       /*!< Write register command buffer */
+    uint8_t enterQpi;             /*!< Enter qpi command */
+    uint8_t exitQpi;              /*!< Exit qpi command */
+    uint8_t cReadMode;            /*!< Config data for continuous read mode */
+    uint8_t cRExit;               /*!< Config data for exit continuous read mode */
+    uint8_t burstWrapCmd;         /*!< Enable burst wrap command */
+    uint8_t burstWrapCmdDmyClk;   /*!< Enable burst wrap command dummy clock */
+    uint8_t burstWrapDataMode;    /*!< Data and address mode for this command */
+    uint8_t burstWrapData;        /*!< Data to enable burst wrap */
+    uint8_t deBurstWrapCmd;       /*!< Disable burst wrap command */
+    uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */
+    uint8_t deBurstWrapDataMode;  /*!< Data and address mode for this command */
+    uint8_t deBurstWrapData;      /*!< Data to disable burst wrap */
+    uint16_t timeEsector;         /*!< 4K erase time */
+    uint16_t timeE32k;            /*!< 32K erase time */
+    uint16_t timeE64k;            /*!< 64K erase time */
+    uint16_t timePagePgm;         /*!< Page program time */
+    uint16_t timeCe;              /*!< Chip erase time in ms */
+    uint8_t pdDelay;              /*!< Release power down command delay time for wake up */
+    uint8_t qeData;               /*!< QE set data */
+};
+
+struct __attribute__((packed, aligned(4))) boot_flash_cfg_t {
+    uint32_t magiccode;
+    struct spi_flash_cfg_t cfg;
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) sys_clk_cfg_t {
+    uint8_t xtal_type;
+    uint8_t pll_clk;
+    uint8_t hclk_div;
+    uint8_t bclk_div;
+
+    uint8_t flash_clk_type;
+    uint8_t flash_clk_div;
+    uint8_t rsvd[2];
+};
+
+struct __attribute__((packed, aligned(4))) boot_clk_cfg_t {
+    uint32_t magiccode;
+    struct sys_clk_cfg_t cfg;
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) aesiv_cfg_t {
+    uint8_t aesiv[16];
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) pkey_cfg_t {
+    uint8_t eckeyx[32]; /* ec key in boot header */
+    uint8_t eckeyy[32]; /* ec key in boot header */
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) sign_cfg_t {
+    uint32_t sig_len;
+    uint8_t signature[32];
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) bootheader_t {
+    uint32_t magiccode; /*'BFXP'*/
+    uint32_t rivison;
+    struct boot_flash_cfg_t flash_cfg;
+    struct boot_clk_cfg_t clk_cfg;
+    union __attribute__((packed, aligned(1))) {
+        struct __attribute__((packed, aligned(1))) {
+            uint32_t sign               : 2;  /* [1: 0]   for sign */
+            uint32_t encrypt_type       : 2;  /* [3: 2]   for encrypt */
+            uint32_t key_sel            : 2;  /* [5: 4]   for key sel in boot interface */
+            uint32_t rsvd_7_6           : 2;  /* [7: 6]   rsvd */
+            uint32_t no_segment         : 1;  /* [8]      no segment info */
+            uint32_t cache_select       : 1;  /* [9]      cache enable */
+            uint32_t notload_in_bootrom : 1;  /* [10]     not load this img in bootrom */
+            uint32_t aes_region_lock    : 1;  /* [11]     aes region lock */
+            uint32_t cache_way_disable  : 4;  /* [15: 12] cache way disable info */
+            uint32_t crc_ignore         : 1;  /* [16]     ignore crc */
+            uint32_t hash_ignore        : 1;  /* [17]     ignore hash */
+            uint32_t halt_ap            : 1;  /* [18]     halt ap */
+            uint32_t boot2_enable       : 1;  /* [19]     boot2 enable */
+            uint32_t boot2_rollback     : 1;  /* [20]     boot2 rollback */
+            uint32_t rsvd_31_21         : 11; /* [31: 21] rsvd */
+        } bval;
+        uint32_t wval;
+    } boot_cfg;
+
+    union __attribute__((packed, aligned(1))) {
+        uint32_t segment_cnt;
+        uint32_t img_len;
+    } img_segment_info;
+
+    uint32_t rsvd0; /* rsvd */
+
+    union __attribute__((packed, aligned(1))) {
+        uint32_t ramaddr;
+        uint32_t flashoffset;
+    } img_start;
+
+    uint32_t hash[32 / 4]; /*hash of the image*/
+
+    uint32_t boot2_pt_table_0; /* address of partition table 0 */
+    uint32_t boot2_pt_table_1; /* address of partition table 1 */
+    uint32_t crc32;
+};
+
+#define BFLB_FW_LENGTH_OFFSET 120
+#define BFLB_FW_HASH_OFFSET   132
+
+#endif
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/bl808_ram.ld b/bsp/bouffalo_lab/bl70x/board/linker_scripts/bl702_flash.ld
old mode 100644
new mode 100755
similarity index 53%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/bl808_ram.ld
rename to bsp/bouffalo_lab/bl70x/board/linker_scripts/bl702_flash.ld
index 5d6b8c3636..d999c423b3
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/bl808_ram.ld
+++ b/bsp/bouffalo_lab/bl70x/board/linker_scripts/bl702_flash.ld
@@ -1,7 +1,7 @@
 /****************************************************************************************
-* @file ram.ld
+* @file bl702_flash.ld
 *
-* @brief This file is the link script file (gnuarm or armgcc).
+* @brief This file is the map file (gnuarm or armgcc).
 *
 * Copyright (C) BouffaloLab 2021
 *
@@ -11,92 +11,143 @@
 /* configure the CPU type */
 OUTPUT_ARCH( "riscv" )
 /* link with the standard c library */
-INPUT(-lc)
+/* INPUT(-lc) */
 /* link with the standard GCC library */
-INPUT(-lgcc)
+/* INPUT(-lgcc) */
 /* configure the entry point */
-ENTRY(Reset_Handler)
+ENTRY(__start)
 
-StackSize    = 0x0400; /*  1KB */
-HeapMinSize  = 0x1000; /*  4KB */
+StackSize = 0x1000; /*  4KB */
 
 MEMORY
 {
-    code_memory (rx)  : ORIGIN = 0x3eff0000, LENGTH = 64K
-    itcm_memory (rx)  : ORIGIN = 0x3eff0000, LENGTH = 64K
-    dtcm_memory (rx)  : ORIGIN = 0x3f000000, LENGTH = 4K
-    nocache_ram_memory (!rx) : ORIGIN = 0x3f001000, LENGTH = 0K
-    ram_memory  (!rx) : ORIGIN = 0x3f001000, LENGTH = 60K
-    xram_memory (!rx) : ORIGIN = 0x40004000, LENGTH = 16K
+    fw_header_memory  (rx)  : ORIGIN = 0x23000000 - 0x1000, LENGTH = 4K
+    xip_memory  (rx)  : ORIGIN = 0x23000000, LENGTH = 1024K
+    itcm_memory (rx)  : ORIGIN = 0x22014000, LENGTH = 12K
+    dtcm_memory (rx)  : ORIGIN = 0x42017000, LENGTH = 4K
+    ram_memory  (!rx) : ORIGIN = 0x42018000, LENGTH = 96K
+    hbn_memory  (rx)  : ORIGIN = 0x40010000, LENGTH = 0xE00     /* hbn ram 4K used 3.5K*/
 }
 
 SECTIONS
 {
+    PROVIDE(__metal_chicken_bit = 0);
+
+    .fw_header :
+    {
+        KEEP(*(.fw_header))
+    } > fw_header_memory
 
     .text :
     {
         . = ALIGN(4);
         __text_code_start__ = .;
-        KEEP(*startup*.*o(*.text*))
-        KEEP (*(SORT_NONE(_start)))
-        KEEP (*(SORT_NONE(Reset_Handler)))
+
+        KEEP (*(SORT_NONE(.init)))
+        KEEP (*(SORT_NONE(.vector)))
 
         *(.text)
         *(.text.*)
 
-        /* section information for shell */
+        /* section information for finsh shell */
         . = ALIGN(4);
         __fsymtab_start = .;
         KEEP(*(FSymTab))
         __fsymtab_end = .;
-
         . = ALIGN(4);
         __vsymtab_start = .;
         KEEP(*(VSymTab))
         __vsymtab_end = .;
+        . = ALIGN(4);
 
-        /* section information for usb desc */
+        /* section information for modules */
         . = ALIGN(4);
-        _usb_desc_start = .;
-        KEEP(*(usb_desc))
+        __rtmsymtab_start = .;
+        KEEP(*(RTMSymTab))
+        __rtmsymtab_end = .;
+
+        /* section information for initialization */
         . = ALIGN(4);
-        _usb_desc_end = .;
-        *(.rodata)
-        *(.rodata.*)
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+
+        /*put .rodata**/
+        *(EXCLUDE_FILE( *bl702_glb*.o* \
+                        *bl702_pds*.o* \
+                        *bl702_common*.o* \
+                        *bl702_sf_cfg*.o* \
+                        *bl702_sf_cfg_ext*.o* \
+                        *bl702_sf_ctrl*.o* \
+                        *bl702_sflash*.o* \
+                        *bl702_sflash_ext*.o* \
+                        *bl702_xip_sflash*.o* \
+                        *bl702_xip_sflash_ext*.o* \
+                        *bl702_ef_ctrl*.o*) .rodata*)
 
         *(.srodata)
         *(.srodata.*)
 
         . = ALIGN(4);
         __text_code_end__ = .;
-    } > code_memory
-    
+    } > xip_memory
+
     . = ALIGN(4);
     __itcm_load_addr = .;
-    
+
     .itcm_region : AT (__itcm_load_addr)
     {
         . = ALIGN(4);
         __tcm_code_start__ = .;
 
+        *(.tcm_code.*)
+        *(.tcm_const.*)
+        *(.sclock_rlt_code.*)
+        *(.sclock_rlt_const.*)
+
+        *bl702_glb*.o*(.rodata*)
+        *bl702_pds*.o*(.rodata*)
+        *bl702_common*.o*(.rodata*)
+        *bl702_sf_cfg*.o*(.rodata*)
+        *bl702_sf_cfg_ext*.o*(.rodata*)
+        *bl702_sf_ctrl*.o*(.rodata*)
+        *bl702_sflash*.o*(.rodata*)
+        *bl702_sflash_ext*.o*(.rodata*)
+        *bl702_xip_sflash*.o*(.rodata*)
+        *bl702_xip_sflash_ext*.o*(.rodata*)
+        *bl702_ef_ctrl*.o*(.rodata*)
+
         . = ALIGN(4);
         __tcm_code_end__ = .;
     } > itcm_memory
-    
-    __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region);
-    
+
+    __hbn_load_addr = __itcm_load_addr + SIZEOF(.itcm_region);
+
+    .hbn_ram_region : AT (__hbn_load_addr)
+    {
+        . = ALIGN(4);
+        __hbn_ram_start__ = .;
+        *bl702_hbn_wakeup*.o*(.rodata*)
+        *(.hbn_ram_code*)
+        *(.hbn_ram_data)
+        . = ALIGN(4);
+        __hbn_ram_end__ = .;
+    } > hbn_memory
+
+    __dtcm_load_addr = __hbn_load_addr + SIZEOF(.hbn_ram_region);
+
     .dtcm_region : AT (__dtcm_load_addr)
     {
         . = ALIGN(4);
         __tcm_data_start__ = .;
-        
+
         *(.tcm_data)
         /* *finger_print.o(.data*) */
-        
+
         . = ALIGN(4);
         __tcm_data_end__ = .;
     } > dtcm_memory
-    
+
     /*************************************************************************/
     /* .stack_dummy section doesn't contains any symbols. It is only
      * used for linker to calculate size of stack sections, and assign
@@ -107,83 +158,54 @@ SECTIONS
         . = . + StackSize;
         . = ALIGN(0x4);
     } > dtcm_memory
-    
+
     /* Set stack top to end of RAM, and stack limit move down by
      * size of stack_dummy section */
     __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);
     PROVIDE( __freertos_irq_stack_top = __StackTop);
+    PROVIDE( __rt_rvstack = . );
     __StackLimit = __StackTop - SIZEOF(.stack_dummy);
-    
+
     /* Check if data + heap + stack exceeds RAM limit */
     ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack")
     /*************************************************************************/
-    __nocache_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
 
-    .nocache_ram_region (NOLOAD) : AT (__nocache_ram_load_addr)
-    {
-        . = ALIGN(4);
-        __nocache_ram_data_start__ = .;
+    __ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
 
-        *(.nocache_ram)
-
-        . = ALIGN(4);
-        __nocache_ram_data_end__ = .;
-    } > nocache_ram_memory
-
-    __system_ram_load_addr = __nocache_ram_load_addr + SIZEOF(.nocache_ram_region);
-
-    .system_ram_data_region : AT (__system_ram_load_addr)
-    {
-        . = ALIGN(4);
-        __system_ram_data_start__ = .;
-        
-        *(.system_ram)
-        
-        . = ALIGN(4);
-        __system_ram_data_end__ = .;
-    } > ram_memory
-    
-    .system_ram_noinit_data_region (NOLOAD) :
-    {
-        . = ALIGN(4);
-        *(.system_ram_noinit)
-        
-        . = ALIGN(4);
-    } > ram_memory
-    
-    __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region);
-    
     /* Data section */
     RAM_DATA : AT (__ram_load_addr)
     {
         . = ALIGN(4);
         __ram_data_start__ = .;
-        
+
         PROVIDE( __global_pointer$ = . + 0x800 );
-        
+
         *(.data)
         *(.data.*)
         *(.sdata)
         *(.sdata.*)
         *(.sdata2)
         *(.sdata2.*)
+
+        *(.nocache_ram)
         
         . = ALIGN(4);
+        __bflog_tags_start__ = .;
+        *(.bflog_tags_array)
+        . = ALIGN(4);
+        __bflog_tags_end__ = .;
         __ram_data_end__ = .;
     } > ram_memory
 
-    __etext_final = (__ram_load_addr + SIZEOF (RAM_DATA));
-    ASSERT(__etext_final <= ORIGIN(code_memory) + LENGTH(code_memory), "code memory overflow")
-    
     .bss (NOLOAD) :
     {
         . = ALIGN(4);
         __bss_start__ = .;
-        
+
         *(.bss*)
         *(.sbss*)
         *(COMMON)
-        
+
         . = ALIGN(4);
         __bss_end__ = .;
     } > ram_memory
@@ -192,28 +214,29 @@ SECTIONS
     {
         . = ALIGN(4);
         __noinit_data_start__ = .;
-        
+
         *(.noinit_data*)
-        
+        *(.nocache_noinit_ram)
+
         . = ALIGN(4);
         __noinit_data_end__ = .;
     } > ram_memory
-    
+
     .heap (NOLOAD):
     {
         . = ALIGN(4);
         __HeapBase = .;
-        
-        /*__end__ = .;*/
-        /*end = __end__;*/
+
         KEEP(*(.heap*))
-        
+
         . = ALIGN(4);
         __HeapLimit = .;
     } > ram_memory
 
+    PROVIDE (__heap_min_size = 0x400);
     __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory);
-    ASSERT(__HeapLimit - __HeapBase >= HeapMinSize, "heap region overflow")
-    
+
+    ASSERT((__HeapLimit -  __HeapBase ) >= __heap_min_size, "heap size is too short.")
+
 }
 
diff --git a/bsp/bouffalo_lab/bl70x/board/trap_gcc.S b/bsp/bouffalo_lab/bl70x/board/trap_gcc.S
new file mode 100755
index 0000000000..a255ed7d09
--- /dev/null
+++ b/bsp/bouffalo_lab/bl70x/board/trap_gcc.S
@@ -0,0 +1,17 @@
+#include "cpuport.h"
+
+	.globl rt_hw_do_after_save_above
+	.type rt_hw_do_after_save_above,@function
+rt_hw_do_after_save_above:
+    addi  sp, sp,  -4
+    STORE ra,  0 * REGBYTES(sp)
+
+	csrr    t1, mcause
+    andi    t1, t1, 0x3FF
+    /* get ISR */
+    la      t2, interrupt_entry
+    jalr    t2
+    
+    LOAD  ra,  0 * REGBYTES(sp)
+    addi  sp, sp,  4
+    ret
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/bl70x/combine.sh b/bsp/bouffalo_lab/bl70x/combine.sh
new file mode 100755
index 0000000000..11a925dff0
--- /dev/null
+++ b/bsp/bouffalo_lab/bl70x/combine.sh
@@ -0,0 +1,39 @@
+#/bin/sh
+CHIPNAME=$1
+BIN_FILE=$2
+
+set -e
+
+SYSTEM=`uname -s`
+echo "system: $SYSTEM"
+
+CONFIG=./board/config
+TOOL_DIR=../libraries/bl_mcu_sdk/tools/bflb_tools/bflb_fw_post_proc
+
+if [ $SYSTEM = "Darwin" ]
+then
+    TOOL_NAME=bflb_fw_post_proc-macos
+    TOOL_ADDR=https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc-macos
+elif [ $SYSTEM = "Linux" ]
+then
+    TOOL_NAME=bflb_fw_post_proc-ubuntu
+    TOOL_ADDR=https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc-ubuntu
+else
+    TOOL_NAME=bflb_fw_post_proc.exe
+    TOOL_ADDR=https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc.exe
+fi
+
+if [ -f "$TOOL_DIR/$TOOL_NAME" ]
+then
+    echo "bflb_fw_post_proc exist"
+else
+    echo "bflb_fw_post_proc not exist, try download... url:$TOOL_ADDR"
+    curl $TOOL_ADDR -o $TOOL_DIR/$TOOL_NAME
+    if [ $SYSTEM = "Darwin" ]; then
+        chmod +x $TOOL_DIR/$TOOL_NAME
+    elif [ $SYSTEM = "Linux" ]; then
+        chmod +x $TOOL_DIR/$TOOL_NAME
+    fi
+fi
+
+./$TOOL_DIR/$TOOL_NAME --chipname=$CHIPNAME --brdcfgdir=$CONFIG --imgfile=$BIN_FILE
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/bl70x/flash_prog_cfg.ini b/bsp/bouffalo_lab/bl70x/flash_prog_cfg.ini
new file mode 100755
index 0000000000..9dacfa8a0c
--- /dev/null
+++ b/bsp/bouffalo_lab/bl70x/flash_prog_cfg.ini
@@ -0,0 +1,12 @@
+[cfg]
+# 0: no erase, 1:programmed section erase, 2: chip erase
+erase = 1
+# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated
+skip_mode = 0x0, 0x0
+# 0: not use isp mode, #1: isp mode
+boot2_isp_mode = 0
+
+[FW]
+filedir = ./rtthread.bin
+address = 0x000000
+
diff --git a/bsp/bouffalo_lab/bl70x/rtconfig.h b/bsp/bouffalo_lab/bl70x/rtconfig.h
new file mode 100644
index 0000000000..fec25d6a91
--- /dev/null
+++ b/bsp/bouffalo_lab/bl70x/rtconfig.h
@@ -0,0 +1,244 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Project Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 8
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 1000
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_HOOK_USING_FUNC_PTR
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 1024
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 512
+
+/* kservice optimization */
+
+#define RT_KSERVICE_USING_STDLIB
+#define RT_DEBUG
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_PAGE_MAX_ORDER 11
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_SMALL_MEM_AS_HEAP
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart0"
+#define RT_VER_NUM 0x50000
+#define ARCH_RISCV
+#define ARCH_RISCV_FPU
+#define ARCH_RISCV_FPU_S
+#define ARCH_RISCV32
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+#define RT_USING_MSH
+#define RT_USING_FINSH
+#define FINSH_USING_MSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_CMD_SIZE 80
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
+#define FINSH_ARG_MAX 10
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_UNAMED_PIPE_NUMBER 64
+#define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+
+/* Using USB */
+
+
+/* C/C++ and POSIX layer */
+
+#define RT_LIBC_DEFAULT_TIMEZONE 8
+
+/* POSIX (Portable Operating System Interface) layer */
+
+
+/* Interprocess Communication (IPC) */
+
+
+/* Socket is in the 'Network' category */
+
+
+/* Network */
+
+
+/* Utilities */
+
+
+/* RT-Thread Utestcases */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
+
+
+/* XML: Extensible Markup Language */
+
+
+/* multimedia packages */
+
+/* LVGL: powerful and easy-to-use embedded GUI library */
+
+
+/* u8g2: a monochrome graphic library */
+
+
+/* PainterEngine: A cross-platform graphics application framework written in C language */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+/* enhanced kernel services */
+
+
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+
+/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
+/* peripheral libraries and drivers */
+
+/* sensors drivers */
+
+
+/* touch drivers */
+
+
+/* Kendryte SDK */
+
+
+/* AI packages */
+
+
+/* Signal Processing and Control Algorithm Packages */
+
+
+/* miscellaneous packages */
+
+/* project laboratory */
+
+/* samples: kernel and components samples */
+
+
+/* entertainment: terminal games and other interesting software packages */
+
+
+/* Arduino libraries */
+
+
+/* Projects */
+
+
+/* Sensors */
+
+
+/* Display */
+
+
+/* Timing */
+
+
+/* Data Processing */
+
+
+/* Data Storage */
+
+/* Communication */
+
+
+/* Device Control */
+
+
+/* Other */
+
+
+/* Signal IO */
+
+
+/* Uncategorized */
+
+#define BSP_USING_BL70X
+#define BSP_USING_ROMAPI
+
+/* General Drivers Configuration */
+
+#define BSP_USING_GPIO
+
+/* General Purpose UARTs */
+
+#define BSP_USING_UART0
+#define UART0_TX_USING_GPIO14
+#define UART0_RX_USING_GPIO23
+#define BSP_USING_UART1
+#define UART1_TX_USING_GPIO26
+#define UART1_RX_USING_GPIO27
+
+#endif
diff --git a/bsp/bouffalo_lab/bl70x/rtconfig.py b/bsp/bouffalo_lab/bl70x/rtconfig.py
new file mode 100755
index 0000000000..ea1198b93b
--- /dev/null
+++ b/bsp/bouffalo_lab/bl70x/rtconfig.py
@@ -0,0 +1,62 @@
+import os
+
+# toolchains options
+ARCH        ='risc-v'
+CPU         ='e24'
+CROSS_TOOL  ='gcc'
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = r'../../..'
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+if  CROSS_TOOL == 'gcc':
+    PLATFORM    = 'gcc'
+    EXEC_PATH   = r'/opt/toolchain_riscv_sifive_linux/bin'
+else:
+    print('Please make sure your toolchains is GNU GCC!')
+    exit(0)
+
+if os.getenv('RTT_EXEC_PATH'):
+    EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX  = 'riscv64-unknown-elf-'
+    CC      = PREFIX + 'gcc'
+    CXX     = PREFIX + 'g++'
+    AS      = PREFIX + 'gcc'
+    AR      = PREFIX + 'ar'
+    LINK    = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE    = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY  = PREFIX + 'objcopy'
+
+    DEVICE  = ' -march=rv32imafc -mabi=ilp32f'
+    CFLAGS  = DEVICE + ' -std=gnu99 -fno-jump-tables -fno-common -fms-extensions -ffunction-sections -fdata-sections -fmessage-length=0 -Wall -Wchar-subscripts -Wformat -Wundef -Wuninitialized -Winit-self -Wignored-qualifiers'
+    CFLAGS += ' -fstrict-volatile-bitfields -fshort-enums -Wno-error=unused-variable -Wno-error=format= -Wno-error=unused-function -Wno-error=implicit-function-declaration -Wno-error=deprecated-declarations -Wno-format'
+
+    LINKER_SCRIPTS = r'board/linker_scripts/bl702_flash.ld'
+
+    AFLAGS  = ' -c' + DEVICE + ' -x assembler-with-cpp'
+    LFLAGS  = DEVICE + ' -nostartfiles -ufw_header -fms-extensions -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T ' + LINKER_SCRIPTS
+    CPATH   = ''
+    LPATH   = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O2 -g3'
+        AFLAGS += ' -g3'
+    else:
+        CFLAGS += ' -O3'
+
+    CXXFLAGS = CFLAGS + ' -std=gnu++17 -Wno-multichar'
+
+DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
+POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+POST_ACTION += 'sh combine.sh bl702 ./rtthread.bin\n'
diff --git a/bsp/bouffalo_lab/bl808/build_bl808.sh b/bsp/bouffalo_lab/bl808/build_bl808.sh
new file mode 100755
index 0000000000..3a03b6285d
--- /dev/null
+++ b/bsp/bouffalo_lab/bl808/build_bl808.sh
@@ -0,0 +1,5 @@
+#!/usr/bin/sh
+
+scons -C m0
+scons -C lp
+
diff --git a/bsp/bouffalo_lab/bl808/builtin_imgs/boot2_bl808_debug_v8.0.7.bin b/bsp/bouffalo_lab/bl808/builtin_imgs/boot2_bl808_debug_v8.0.7.bin
new file mode 100755
index 0000000000..21d90a07cb
Binary files /dev/null and b/bsp/bouffalo_lab/bl808/builtin_imgs/boot2_bl808_debug_v8.0.7.bin differ
diff --git a/bsp/bouffalo_lab/bl808/builtin_imgs/boot2_bl808_release_v8.0.7.bin b/bsp/bouffalo_lab/bl808/builtin_imgs/boot2_bl808_release_v8.0.7.bin
new file mode 100755
index 0000000000..71ad7a7b30
Binary files /dev/null and b/bsp/bouffalo_lab/bl808/builtin_imgs/boot2_bl808_release_v8.0.7.bin differ
diff --git a/bsp/bouffalo_lab/bl808/builtin_imgs/mfg_bl808_gu_7c2526e09_autoboot_v0.56.bin b/bsp/bouffalo_lab/bl808/builtin_imgs/mfg_bl808_gu_7c2526e09_autoboot_v0.56.bin
new file mode 100755
index 0000000000..33555dbcd8
Binary files /dev/null and b/bsp/bouffalo_lab/bl808/builtin_imgs/mfg_bl808_gu_7c2526e09_autoboot_v0.56.bin differ
diff --git a/bsp/bouffalo_lab/bl808/builtin_imgs/mfg_bl808_gu_7c2526e09_v0.56.bin b/bsp/bouffalo_lab/bl808/builtin_imgs/mfg_bl808_gu_7c2526e09_v0.56.bin
new file mode 100755
index 0000000000..d4bbe28abc
Binary files /dev/null and b/bsp/bouffalo_lab/bl808/builtin_imgs/mfg_bl808_gu_7c2526e09_v0.56.bin differ
diff --git a/bsp/bouffalo_lab/bl808/config/.gitkeep b/bsp/bouffalo_lab/bl808/config/.gitkeep
new file mode 100755
index 0000000000..e69de29bb2
diff --git a/bsp/bouffalo_lab/bl808/flash_prog_cfg.ini b/bsp/bouffalo_lab/bl808/flash_prog_cfg.ini
new file mode 100755
index 0000000000..1ab976b384
--- /dev/null
+++ b/bsp/bouffalo_lab/bl808/flash_prog_cfg.ini
@@ -0,0 +1,11 @@
+[cfg]
+# 0: no erase, 1:programmed section erase, 2: chip erase
+erase = 1
+# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated
+skip_mode = 0x0, 0x0
+# 0: not use isp mode, #1: isp mode
+boot2_isp_mode = 0
+
+[FW1]
+filedir = ./m0/rtthread_m0.bin
+address = 0x000000
diff --git a/bsp/bl808/m0/.config b/bsp/bouffalo_lab/bl808/m0/.config
old mode 100644
new mode 100755
similarity index 96%
rename from bsp/bl808/m0/.config
rename to bsp/bouffalo_lab/bl808/m0/.config
index da3f2db410..0d1e0a0b5a
--- a/bsp/bl808/m0/.config
+++ b/bsp/bouffalo_lab/bl808/m0/.config
@@ -23,7 +23,7 @@ CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
 CONFIG_IDLE_THREAD_STACK_SIZE=1024
 CONFIG_RT_USING_TIMER_SOFT=y
 CONFIG_RT_TIMER_THREAD_PRIO=4
-CONFIG_RT_TIMER_THREAD_STACK_SIZE=1024
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
 
 #
 # kservice optimization
@@ -59,7 +59,8 @@ CONFIG_RT_USING_MESSAGEQUEUE=y
 #
 # Memory Management
 #
-# CONFIG_RT_USING_MEMPOOL is not set
+CONFIG_RT_PAGE_MAX_ORDER=11
+CONFIG_RT_USING_MEMPOOL=y
 CONFIG_RT_USING_SMALL_MEM=y
 # CONFIG_RT_USING_SLAB is not set
 # CONFIG_RT_USING_MEMHEAP is not set
@@ -68,7 +69,7 @@ CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
 # CONFIG_RT_USING_SLAB_AS_HEAP is not set
 # CONFIG_RT_USING_USERHEAP is not set
 # CONFIG_RT_USING_NOHEAP is not set
-CONFIG_RT_USING_MEMTRACE=y
+# CONFIG_RT_USING_MEMTRACE is not set
 # CONFIG_RT_USING_HEAP_ISR is not set
 CONFIG_RT_USING_HEAP=y
 
@@ -87,8 +88,10 @@ CONFIG_RT_VER_NUM=0x50000
 # CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
 # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
 # CONFIG_RT_USING_CPU_FFS is not set
+CONFIG_ARCH_RISCV=y
 CONFIG_ARCH_RISCV_FPU=y
 CONFIG_ARCH_RISCV_FPU_S=y
+CONFIG_ARCH_RISCV32=y
 
 #
 # RT-Thread Components
@@ -207,6 +210,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_RT_USING_ULOG is not set
 # CONFIG_RT_USING_UTEST is not set
 # CONFIG_RT_USING_VAR_EXPORT is not set
+# CONFIG_RT_USING_ADT is not set
 # CONFIG_RT_USING_RT_LINK is not set
 # CONFIG_RT_USING_VBUS is not set
 
@@ -399,6 +403,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_EASYLOGGER is not set
 # CONFIG_PKG_USING_SYSTEMVIEW is not set
 # CONFIG_PKG_USING_SEGGER_RTT is not set
+# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
 # CONFIG_PKG_USING_RDB is not set
 # CONFIG_PKG_USING_ULOG_EASYFLASH is not set
 # CONFIG_PKG_USING_LOGMGR is not set
@@ -506,6 +511,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_TFDB is not set
 # CONFIG_PKG_USING_QPC is not set
 # CONFIG_PKG_USING_AGILE_UPGRADE is not set
+# CONFIG_PKG_USING_FLASH_BLOB is not set
 
 #
 # peripheral libraries and drivers
@@ -577,6 +583,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_CW2015 is not set
 # CONFIG_PKG_USING_ICM20608 is not set
 # CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_STHS34PF80 is not set
 
 #
 # touch drivers
@@ -628,6 +635,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_BEEP is not set
 # CONFIG_PKG_USING_EASYBLINK is not set
 # CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_NUCLEI_SDK is not set
 # CONFIG_PKG_USING_CAN_YMODEM is not set
 # CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
 # CONFIG_PKG_USING_QLED is not set
@@ -748,7 +756,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_SOEM is not set
 # CONFIG_PKG_USING_QPARAM is not set
 # CONFIG_PKG_USING_CorevMCU_CLI is not set
-# CONFIG_PKG_USING_GET_IRQ_PRIORITY is not set
 
 #
 # Arduino libraries
@@ -905,6 +912,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # Display
 #
 # CONFIG_PKG_USING_ARDUINO_U8G2 is not set
+# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set
 # CONFIG_PKG_USING_SEEED_TM1637 is not set
 
 #
@@ -934,10 +942,17 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
 
 #
 # Other
 #
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
+# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
 
 #
 # Signal IO
@@ -954,18 +969,23 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 #
 # Uncategorized
 #
+CONFIG_BSP_USING_BL808=y
+CONFIG_BL808_CORE_M0=y
+# CONFIG_BSP_USING_PSRAM is not set
 
 #
-# BL808_M0 Hardware Drivers Config
+# General Drivers Configuration
 #
-CONFIG_SOC_BL808=y
-# CONFIG_BSP_USING_JTAG_M0 is not set
+# CONFIG_BSP_USING_GPIO is not set
 
 #
-# On-chip Peripheral Drivers
+# General Purpose UARTs
 #
-CONFIG_BSP_USING_GPIO=y
-CONFIG_BSP_USING_UART=y
 CONFIG_BSP_USING_UART0=y
-CONFIG_BSP_UART0_TXD_PIN=14
-CONFIG_BSP_UART0_RXD_PIN=15
+CONFIG_UART0_TX_USING_GPIO14=y
+# CONFIG_UART0_TX_USING_GPIO16 is not set
+# CONFIG_UART0_TX_USING_GPIO21 is not set
+# CONFIG_UART0_RX_USING_GPIO7 is not set
+CONFIG_UART0_RX_USING_GPIO15=y
+# CONFIG_UART0_RX_USING_GPIO22 is not set
+# CONFIG_UART0_RX_USING_GPIO23 is not set
diff --git a/bsp/bouffalo_lab/bl808/m0/Kconfig b/bsp/bouffalo_lab/bl808/m0/Kconfig
new file mode 100755
index 0000000000..0de06b6788
--- /dev/null
+++ b/bsp/bouffalo_lab/bl808/m0/Kconfig
@@ -0,0 +1,26 @@
+mainmenu "RT-Thread Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+config LIBRARIES_DIR
+    string
+    option env="LIBRARIES_DIR"
+    default "../../libraries"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "board/Kconfig"
+source "$LIBRARIES_DIR/Kconfig"
diff --git a/bsp/bouffalo_lab/bl808/m0/SConscript b/bsp/bouffalo_lab/bl808/m0/SConscript
new file mode 100755
index 0000000000..c7ef7659ec
--- /dev/null
+++ b/bsp/bouffalo_lab/bl808/m0/SConscript
@@ -0,0 +1,14 @@
+# for module compiling
+import os
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/bouffalo_lab/bl808/m0/SConstruct b/bsp/bouffalo_lab/bl808/m0/SConstruct
new file mode 100755
index 0000000000..6914fd4251
--- /dev/null
+++ b/bsp/bouffalo_lab/bl808/m0/SConstruct
@@ -0,0 +1,45 @@
+import os
+import sys
+import rtconfig
+
+from rtconfig import RTT_ROOT
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+env['ASCOM'] = env['ASPPCOM']
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/../libraries'):
+    libraries_path_prefix = SDK_ROOT + '/../libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/../libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False)
+
+# include libraries
+objs.extend(SConscript(libraries_path_prefix + '/bl_mcu_sdk/SConscript', variant_dir='build/libraries/bl_mcu_sdk', duplicate=0))
+
+# include drivers
+objs.extend(SConscript(libraries_path_prefix + '/rt_drivers/SConscript', variant_dir='build/libraries/rt_drivers', duplicate=0))
+
+# make a building
+DoBuilding(TARGET, objs)
diff --git a/bsp/bouffalo_lab/bl808/m0/applications/SConscript b/bsp/bouffalo_lab/bl808/m0/applications/SConscript
new file mode 100755
index 0000000000..c583d3016e
--- /dev/null
+++ b/bsp/bouffalo_lab/bl808/m0/applications/SConscript
@@ -0,0 +1,9 @@
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/bouffalo_lab/bl808/m0/applications/main.c b/bsp/bouffalo_lab/bl808/m0/applications/main.c
new file mode 100644
index 0000000000..6897456dde
--- /dev/null
+++ b/bsp/bouffalo_lab/bl808/m0/applications/main.c
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022/12/25     flyingcys    first version
+ */
+
+#include 
+#include 
+
+int main(void)
+{
+    rt_kprintf("Hello, RISC-V!\n");
+
+    return 0;
+}
diff --git a/bsp/bouffalo_lab/bl808/m0/board/Kconfig b/bsp/bouffalo_lab/bl808/m0/board/Kconfig
new file mode 100755
index 0000000000..d9ec26766e
--- /dev/null
+++ b/bsp/bouffalo_lab/bl808/m0/board/Kconfig
@@ -0,0 +1,16 @@
+config BSP_USING_BL808
+    bool
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    select ARCH_RISCV32
+    select ARCH_RISCV_FPU_S
+    select BL808_CORE_M0
+    default y
+
+config BL808_CORE_M0
+    bool
+    default y
+
+config BSP_USING_PSRAM
+    bool "Enable PSRAM"
+    default n
diff --git a/bsp/bouffalo_lab/bl808/m0/board/SConscript b/bsp/bouffalo_lab/bl808/m0/board/SConscript
new file mode 100755
index 0000000000..c0653a14cc
--- /dev/null
+++ b/bsp/bouffalo_lab/bl808/m0/board/SConscript
@@ -0,0 +1,9 @@
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*.S')
+CPPPATH = [cwd]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/bouffalo_lab/bl808/m0/board/board.c b/bsp/bouffalo_lab/bl808/m0/board/board.c
new file mode 100644
index 0000000000..5494c69eaf
--- /dev/null
+++ b/bsp/bouffalo_lab/bl808/m0/board/board.c
@@ -0,0 +1,221 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022/12/25     flyingcys    first version
+ * 2023/01/17     chushicheng  add pin and i2c
+ * 2023/03/15     flyingcys    update bsp file structure
+ */
+#include 
+#include 
+
+#include "board.h"
+#include "drv_uart.h"
+
+#ifdef BSP_USING_SDH_SDCARD
+#include "sdh_sdcard.h"
+#endif
+
+static void system_clock_init(void)
+{
+    /* wifipll/audiopll */
+    GLB_Power_On_XTAL_And_PLL_CLK(GLB_XTAL_40M, GLB_PLL_WIFIPLL |
+                                                    GLB_PLL_CPUPLL |
+                                                    GLB_PLL_UHSPLL |
+                                                    GLB_PLL_MIPIPLL);
+
+    GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_WIFIPLL_320M);
+    GLB_Set_DSP_System_CLK(GLB_DSP_SYS_CLK_CPUPLL_400M);
+    GLB_Config_CPU_PLL(GLB_XTAL_40M, cpuPllCfg_480M);
+
+    CPU_Set_MTimer_CLK(ENABLE, CPU_Get_MTimer_Source_Clock() / 1000 / 1000 - 1);
+}
+
+static void peripheral_clock_init(void)
+{
+    PERIPHERAL_CLOCK_ADC_DAC_ENABLE();
+    PERIPHERAL_CLOCK_SEC_ENABLE();
+    PERIPHERAL_CLOCK_DMA0_ENABLE();
+    PERIPHERAL_CLOCK_UART0_ENABLE();
+    PERIPHERAL_CLOCK_UART1_ENABLE();
+    PERIPHERAL_CLOCK_SPI0_1_ENABLE();
+    PERIPHERAL_CLOCK_I2C0_ENABLE();
+    PERIPHERAL_CLOCK_PWM0_ENABLE();
+    PERIPHERAL_CLOCK_TIMER0_1_WDG_ENABLE();
+    PERIPHERAL_CLOCK_IR_ENABLE();
+    PERIPHERAL_CLOCK_I2S_ENABLE();
+    PERIPHERAL_CLOCK_USB_ENABLE();
+    PERIPHERAL_CLOCK_CAN_UART2_ENABLE();
+
+    GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, 4);
+    GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_XCLK, 0);
+    GLB_Set_DSP_UART0_CLK(ENABLE, GLB_DSP_UART_CLK_DSP_XCLK, 0);
+    GLB_Set_SPI_CLK(ENABLE, GLB_SPI_CLK_MCU_MUXPLL_160M, 0);
+    GLB_Set_I2C_CLK(ENABLE, GLB_I2C_CLK_XCLK, 0);
+    GLB_Set_IR_CLK(ENABLE, GLB_IR_CLK_SRC_XCLK, 19);
+    GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, 1);
+    GLB_Set_DIG_CLK_Sel(GLB_DIG_CLK_XCLK);
+    GLB_Set_DIG_512K_CLK(ENABLE, ENABLE, 0x4E);
+    GLB_Set_PWM1_IO_Sel(GLB_PWM1_IO_DIFF_END);
+    GLB_Set_CAM_CLK(ENABLE, GLB_CAM_CLK_WIFIPLL_96M, 3);
+
+    GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_MCU_MUXPLL_160M);
+
+#ifdef BSP_USING_SDH_SDCARD
+    PERIPHERAL_CLOCK_SDH_ENABLE();
+    uint32_t tmp_val;
+    tmp_val = BL_RD_REG(PDS_BASE, PDS_CTL5);
+    uint32_t tmp_val2 = BL_GET_REG_BITS_VAL(tmp_val, PDS_CR_PDS_GPIO_KEEP_EN);
+    tmp_val2 &= ~(1 << 0);
+    tmp_val = BL_SET_REG_BITS_VAL(tmp_val, PDS_CR_PDS_GPIO_KEEP_EN, tmp_val2);
+    BL_WR_REG(PDS_BASE, PDS_CTL5, tmp_val);
+    GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_SDH);
+#endif
+
+#ifdef BSP_USING_CSI
+    GLB_CSI_Config_MIPIPLL(2, 0x21000);
+    GLB_CSI_Power_Up_MIPIPLL();
+    GLB_Set_DSP_CLK(ENABLE, GLB_DSP_CLK_MUXPLL_160M, 1);
+#endif
+    GLB_Set_USB_CLK_From_WIFIPLL(1);
+}
+
+#ifdef BSP_USING_PSRAM
+#define WB_4MB_PSRAM   (1)
+#define UHS_32MB_PSRAM (2)
+#define UHS_64MB_PSRAM (3)
+#define WB_32MB_PSRAM  (4)
+#define NONE_UHS_PSRAM (-1)
+
+int uhs_psram_init(void)
+{
+    PSRAM_UHS_Cfg_Type psramDefaultCfg = {
+        2000,
+        PSRAM_MEM_SIZE_32MB,
+        PSRAM_PAGE_SIZE_2KB,
+        PSRAM_UHS_NORMAL_TEMP,
+    };
+
+    bflb_efuse_device_info_type chip_info;
+    bflb_ef_ctrl_get_device_info(&chip_info);
+    if (chip_info.psramInfo == UHS_32MB_PSRAM) {
+        psramDefaultCfg.psramMemSize = PSRAM_MEM_SIZE_32MB;
+    } else if (chip_info.psramInfo == UHS_64MB_PSRAM) {
+        psramDefaultCfg.psramMemSize = PSRAM_MEM_SIZE_64MB;
+    } else {
+        return -1;
+    }
+
+    //init uhs PLL; Must open uhs pll first, and then initialize uhs psram
+    GLB_Config_UHS_PLL(GLB_XTAL_40M, uhsPllCfg_2000M);
+    //init uhs psram ;
+    // Psram_UHS_x16_Init(Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_PSRAMA) / 1000000);
+    Psram_UHS_x16_Init_Override(&psramDefaultCfg);
+    Tzc_Sec_PSRAMA_Access_Release();
+
+    // example: 2000Mbps typical cal values
+    uhs_phy_cal_res->rl = 39;
+    uhs_phy_cal_res->rdqs = 3;
+    uhs_phy_cal_res->rdq = 0;
+    uhs_phy_cal_res->wl = 13;
+    uhs_phy_cal_res->wdqs = 4;
+    uhs_phy_cal_res->wdq = 5;
+    uhs_phy_cal_res->ck = 9;
+    /* TODO: use uhs psram trim update */
+    set_uhs_latency_r(uhs_phy_cal_res->rl);
+    cfg_dqs_rx(uhs_phy_cal_res->rdqs);
+    cfg_dq_rx(uhs_phy_cal_res->rdq);
+    set_uhs_latency_w(uhs_phy_cal_res->wl);
+    cfg_dq_drv(uhs_phy_cal_res->wdq);
+    cfg_ck_cen_drv(uhs_phy_cal_res->wdq + 4, uhs_phy_cal_res->wdq + 1);
+    cfg_dqs_drv(uhs_phy_cal_res->wdqs);
+    // set_odt_en();
+    mr_read_back();
+    return 0;
+}
+#endif
+
+/* This is the timer interrupt service routine. */
+static void systick_isr(void)
+{
+    rt_tick_increase();
+}
+
+void rt_hw_board_init(void)
+{
+    GLB_Halt_CPU(GLB_CORE_ID_D0);
+    GLB_Halt_CPU(GLB_CORE_ID_LP);
+
+    bflb_flash_init();
+
+    system_clock_init();
+    peripheral_clock_init();
+    bflb_irq_initialize();
+
+    bflb_mtimer_config(CPU_Get_MTimer_Clock() / RT_TICK_PER_SECOND, systick_isr);
+
+#ifdef RT_USING_HEAP
+    /* initialize memory system */
+    rt_kprintf("RT_HW_HEAP_BEGIN:%x RT_HW_HEAP_END:%x size: %d\r\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END, RT_HW_HEAP_END - RT_HW_HEAP_BEGIN);
+    rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
+#endif
+
+    /* UART driver initialization is open by default */
+#ifdef RT_USING_SERIAL
+    rt_hw_uart_init();
+#endif
+
+#ifdef BSP_USING_PSRAM
+    if (uhs_psram_init() < 0)
+    {
+        rt_kprintf("uhs_psram_init failed!\n");
+    }
+#endif
+
+    /* GPIO driver initialization is open by default */
+#ifdef BSP_USING_PIN
+    rt_hw_pin_init();
+#endif
+
+    /* I2C driver initialization is open by default */
+#ifdef BSP_USING_I2C
+    rt_hw_i2c_init();
+#endif
+
+    /* Set the shell console output device */
+#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+
+    /* set CPU D0 boot XIP address and flash address */
+    Tzc_Sec_Set_CPU_Group(GLB_CORE_ID_D0, 1);
+    /* D0 boot from 0x58000000 */
+    GLB_Set_CPU_Reset_Address(GLB_CORE_ID_D0, 0x58000000);
+    /* D0 image offset on flash is CONFIG_D0_FLASH_ADDR+0x1000(header) */
+    bflb_sf_ctrl_set_flash_image_offset(CONFIG_D0_FLASH_ADDR + 0x1000, 1, SF_CTRL_FLASH_BANK0);
+
+    Tzc_Sec_Set_CPU_Group(GLB_CORE_ID_LP, 0);
+    /* LP boot from 0x580C0000 */
+    GLB_Set_CPU_Reset_Address(GLB_CORE_ID_LP, 0x580C0000);
+
+    GLB_Release_CPU(GLB_CORE_ID_D0);
+    GLB_Release_CPU(GLB_CORE_ID_LP);
+
+    /* release d0 and then do can run */
+    BL_WR_WORD(IPC_SYNC_ADDR1, IPC_SYNC_FLAG);
+    BL_WR_WORD(IPC_SYNC_ADDR2, IPC_SYNC_FLAG);
+    L1C_DCache_Clean_By_Addr(IPC_SYNC_ADDR1, 8);
+}
+
+void rt_hw_cpu_reset(void)
+{
+    GLB_SW_POR_Reset();
+}
+MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reset machine);
diff --git a/bsp/bouffalo_lab/bl808/m0/board/board.h b/bsp/bouffalo_lab/bl808/m0/board/board.h
new file mode 100644
index 0000000000..87b65931e7
--- /dev/null
+++ b/bsp/bouffalo_lab/bl808/m0/board/board.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022/12/25     flyingcys    first version
+ * 2023/03/15     flyingcys    update bsp file structure
+ */
+
+#ifndef BOARD_H__
+#define BOARD_H__
+
+#include 
+
+#include "bflb_uart.h"
+#include "bflb_gpio.h"
+#include "bflb_clock.h"
+#include "bflb_rtc.h"
+#include "bflb_flash.h"
+#include "bl808_glb.h"
+#include "bl808_psram_uhs.h"
+#include "bl808_tzc_sec.h"
+#include "bl808_ef_cfg.h"
+#include "bl808_uhs_phy.h"
+
+#define CONFIG_D0_FLASH_ADDR             0x100000
+
+extern uint8_t __HeapBase;
+extern uint8_t __HeapLimit;
+
+#define RT_HW_HEAP_BEGIN    (void*)&__HeapBase
+#define RT_HW_HEAP_END      (void*)&__HeapLimit
+
+void rt_hw_board_init(void);
+
+#endif
diff --git a/bsp/bouffalo_lab/bl808/m0/board/fw_header.c b/bsp/bouffalo_lab/bl808/m0/board/fw_header.c
new file mode 100644
index 0000000000..73f7948497
--- /dev/null
+++ b/bsp/bouffalo_lab/bl808/m0/board/fw_header.c
@@ -0,0 +1,208 @@
+#include "fw_header.h"
+
+__attribute__((section(".fw_header"))) struct bootheader_t fw_header = {
+    .magiccode = 0x504e4642,
+    .rivison = 0x00000001,
+    /*flash config */
+    .flash_cfg.magiccode = 0x47464346,
+    .flash_cfg.cfg.ioMode = 0x11,               /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
+    .flash_cfg.cfg.cReadSupport = 0x00,         /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
+    .flash_cfg.cfg.clkDelay = 0x01,             /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
+    .flash_cfg.cfg.clkInvert = 0x01,            /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
+    .flash_cfg.cfg.resetEnCmd = 0x66,           /*!< Flash enable reset command */
+    .flash_cfg.cfg.resetCmd = 0x99,             /*!< Flash reset command */
+    .flash_cfg.cfg.resetCreadCmd = 0xff,        /*!< Flash reset continuous read command */
+    .flash_cfg.cfg.resetCreadCmdSize = 0x03,    /*!< Flash reset continuous read command size */
+    .flash_cfg.cfg.jedecIdCmd = 0x9f,           /*!< JEDEC ID command */
+    .flash_cfg.cfg.jedecIdCmdDmyClk = 0x00,     /*!< JEDEC ID command dummy clock */
+    .flash_cfg.cfg.enter32BitsAddrCmd = 0xb7,   /*!< Enter 32-bits addr command */
+    .flash_cfg.cfg.exit32BitsAddrCmd = 0xe9,    /*!< Exit 32-bits addr command */
+    .flash_cfg.cfg.sectorSize = 0x04,           /*!< *1024bytes */
+    .flash_cfg.cfg.mid = 0x00,                  /*!< Manufacturer ID */
+    .flash_cfg.cfg.pageSize = 0x100,            /*!< Page size */
+    .flash_cfg.cfg.chipEraseCmd = 0xc7,         /*!< Chip erase cmd */
+    .flash_cfg.cfg.sectorEraseCmd = 0x20,       /*!< Sector erase command */
+    .flash_cfg.cfg.blk32EraseCmd = 0x52,        /*!< Block 32K erase command,some Micron not support */
+    .flash_cfg.cfg.blk64EraseCmd = 0xd8,        /*!< Block 64K erase command */
+    .flash_cfg.cfg.writeEnableCmd = 0x06,       /*!< Need before every erase or program */
+    .flash_cfg.cfg.pageProgramCmd = 0x02,       /*!< Page program cmd */
+    .flash_cfg.cfg.qpageProgramCmd = 0x32,      /*!< QIO page program cmd */
+    .flash_cfg.cfg.qppAddrMode = 0x00,          /*!< QIO page program address mode */
+    .flash_cfg.cfg.fastReadCmd = 0x0b,          /*!< Fast read command */
+    .flash_cfg.cfg.frDmyClk = 0x01,             /*!< Fast read command dummy clock */
+    .flash_cfg.cfg.qpiFastReadCmd = 0x0b,       /*!< QPI fast read command */
+    .flash_cfg.cfg.qpiFrDmyClk = 0x01,          /*!< QPI fast read command dummy clock */
+    .flash_cfg.cfg.fastReadDoCmd = 0x3b,        /*!< Fast read dual output command */
+    .flash_cfg.cfg.frDoDmyClk = 0x01,           /*!< Fast read dual output command dummy clock */
+    .flash_cfg.cfg.fastReadDioCmd = 0xbb,       /*!< Fast read dual io comamnd */
+    .flash_cfg.cfg.frDioDmyClk = 0x00,          /*!< Fast read dual io command dummy clock */
+    .flash_cfg.cfg.fastReadQoCmd = 0x6b,        /*!< Fast read quad output comamnd */
+    .flash_cfg.cfg.frQoDmyClk = 0x01,           /*!< Fast read quad output comamnd dummy clock */
+    .flash_cfg.cfg.fastReadQioCmd = 0xeb,       /*!< Fast read quad io comamnd */
+    .flash_cfg.cfg.frQioDmyClk = 0x02,          /*!< Fast read quad io comamnd dummy clock */
+    .flash_cfg.cfg.qpiFastReadQioCmd = 0xeb,    /*!< QPI fast read quad io comamnd */
+    .flash_cfg.cfg.qpiFrQioDmyClk = 0x02,       /*!< QPI fast read QIO dummy clock */
+    .flash_cfg.cfg.qpiPageProgramCmd = 0x02,    /*!< QPI program command */
+    .flash_cfg.cfg.writeVregEnableCmd = 0x50,   /*!< Enable write reg */
+    .flash_cfg.cfg.wrEnableIndex = 0x00,        /*!< Write enable register index */
+    .flash_cfg.cfg.qeIndex = 0x01,              /*!< Quad mode enable register index */
+    .flash_cfg.cfg.busyIndex = 0x00,            /*!< Busy status register index */
+    .flash_cfg.cfg.wrEnableBit = 0x01,          /*!< Write enable bit pos */
+    .flash_cfg.cfg.qeBit = 0x01,                /*!< Quad enable bit pos */
+    .flash_cfg.cfg.busyBit = 0x00,              /*!< Busy status bit pos */
+    .flash_cfg.cfg.wrEnableWriteRegLen = 0x02,  /*!< Register length of write enable */
+    .flash_cfg.cfg.wrEnableReadRegLen = 0x01,   /*!< Register length of write enable status */
+    .flash_cfg.cfg.qeWriteRegLen = 0x02,        /*!< Register length of contain quad enable */
+    .flash_cfg.cfg.qeReadRegLen = 0x01,         /*!< Register length of contain quad enable status */
+    .flash_cfg.cfg.releasePowerDown = 0xab,     /*!< Release power down command */
+    .flash_cfg.cfg.busyReadRegLen = 0x01,       /*!< Register length of contain busy status */
+    .flash_cfg.cfg.readRegCmd[0] = 0x05,        /*!< Read register command buffer */
+    .flash_cfg.cfg.readRegCmd[1] = 0x35,        /*!< Read register command buffer */
+    .flash_cfg.cfg.readRegCmd[2] = 0x00,        /*!< Read register command buffer */
+    .flash_cfg.cfg.readRegCmd[3] = 0x00,        /*!< Read register command buffer */
+    .flash_cfg.cfg.writeRegCmd[0] = 0x01,       /*!< Write register command buffer */
+    .flash_cfg.cfg.writeRegCmd[1] = 0x01,       /*!< Write register command buffer */
+    .flash_cfg.cfg.writeRegCmd[2] = 0x00,       /*!< Write register command buffer */
+    .flash_cfg.cfg.writeRegCmd[3] = 0x00,       /*!< Write register command buffer */
+    .flash_cfg.cfg.enterQpi = 0x38,             /*!< Enter qpi command */
+    .flash_cfg.cfg.exitQpi = 0xff,              /*!< Exit qpi command */
+    .flash_cfg.cfg.cReadMode = 0x20,            /*!< Config data for continuous read mode */
+    .flash_cfg.cfg.cRExit = 0xf0,               /*!< Config data for exit continuous read mode */
+    .flash_cfg.cfg.burstWrapCmd = 0x77,         /*!< Enable burst wrap command */
+    .flash_cfg.cfg.burstWrapCmdDmyClk = 0x03,   /*!< Enable burst wrap command dummy clock */
+    .flash_cfg.cfg.burstWrapDataMode = 0x02,    /*!< Data and address mode for this command */
+    .flash_cfg.cfg.burstWrapData = 0x40,        /*!< Data to enable burst wrap */
+    .flash_cfg.cfg.deBurstWrapCmd = 0x77,       /*!< Disable burst wrap command */
+    .flash_cfg.cfg.deBurstWrapCmdDmyClk = 0x03, /*!< Disable burst wrap command dummy clock */
+    .flash_cfg.cfg.deBurstWrapDataMode = 0x02,  /*!< Data and address mode for this command */
+    .flash_cfg.cfg.deBurstWrapData = 0xf0,      /*!< Data to disable burst wrap */
+    .flash_cfg.cfg.timeEsector = 300,           /*!< 4K erase time */
+    .flash_cfg.cfg.timeE32k = 1200,             /*!< 32K erase time */
+    .flash_cfg.cfg.timeE64k = 1200,             /*!< 64K erase time */
+    .flash_cfg.cfg.timePagePgm = 50,            /*!< Page program time */
+    .flash_cfg.cfg.timeCe = 30000,              /*!< Chip erase time in ms */
+    .flash_cfg.cfg.pdDelay = 20,                /*!< Release power down command delay time for wake up */
+    .flash_cfg.cfg.qeData = 0,                  /*!< QE set data */
+    .flash_cfg.crc32 = 0xdeadbeef,
+    /* clock cfg */
+    .clk_cfg.magiccode = 0x47464350,
+    .clk_cfg.cfg.xtal_type = 0x07, /*!<  0:None,1:24M,2:32M,3:38.4M,4:40M,5:26M,6:RC32M  */
+    .clk_cfg.cfg.mcu_clk = 0x04,   /*!< mcu_clk 0:RC32M,1:Xtal,2:cpupll 400M,3:wifipll 192M,4:wifipll 320M */
+    .clk_cfg.cfg.mcu_clk_div = 0x00,
+    .clk_cfg.cfg.mcu_bclk_div = 0x00,
+
+    .clk_cfg.cfg.mcu_pbclk_div = 0x03,
+    .clk_cfg.cfg.lp_div = 0x01,
+    .clk_cfg.cfg.dsp_clk = 0x03, /* 0:RC32M,1:Xtal,2:wifipll 240M,3:wifipll 320M,4:cpupll 400M */
+    .clk_cfg.cfg.dsp_clk_div = 0x00,
+
+    .clk_cfg.cfg.dsp_bclk_div = 0x01,
+    .clk_cfg.cfg.dsp_pbclk = 0x02, /* 0:RC32M,1:Xtal,2:wifipll 160M,3:cpupll 160M,4:wifipll 240M */
+    .clk_cfg.cfg.dsp_pbclk_div = 0x00,
+    .clk_cfg.cfg.emi_clk = 0x02, /*!<  0:mcu pbclk,1:cpupll 200M,2:wifipll 320M,3:cpupll 400M */
+
+    .clk_cfg.cfg.emi_clk_div = 0x01,
+    .clk_cfg.cfg.flash_clk_type = 0x01, /*!< 0:wifipll 120M,1:xtal,2:cpupll 100M,3:wifipll 80M,4:bclk,5:wifipll 96M */
+    .clk_cfg.cfg.flash_clk_div = 0x00,
+    .clk_cfg.cfg.wifipll_pu = 0x01,
+
+    .clk_cfg.cfg.aupll_pu = 0x01,
+    .clk_cfg.cfg.cpupll_pu = 0x01,
+    .clk_cfg.cfg.mipipll_pu = 0x01,
+    .clk_cfg.cfg.uhspll_pu = 0x01,
+
+    .clk_cfg.crc32 = 0xdeadbeef,
+
+    /* basic cfg */
+    .basic_cfg.sign_type = 0x0,          /* [1: 0]   for sign */
+    .basic_cfg.encrypt_type = 0x0,       /* [3: 2]   for encrypt */
+    .basic_cfg.key_sel = 0x0,            /* [5: 4]   key slot */
+    .basic_cfg.xts_mode = 0x0,           /* [6]      for xts mode */
+    .basic_cfg.aes_region_lock = 0x0,    /* [7]      rsvd */
+    .basic_cfg.no_segment = 0x1,         /* [8]      no segment info */
+    .basic_cfg.rsvd_0 = 0x0,             /* [9]      boot2 enable(rsvd_0) */
+    .basic_cfg.rsvd_1 = 0x0,             /* [10]     boot2 rollback(rsvd_1) */
+    .basic_cfg.cpu_master_id = 0x0,      /* [14: 11] master id */
+    .basic_cfg.notload_in_bootrom = 0x0, /* [15]     notload in bootrom */
+    .basic_cfg.crc_ignore = 0x1,         /* [16]     ignore crc */
+    .basic_cfg.hash_ignore = 0x1,        /* [17]     hash ignore */
+    .basic_cfg.power_on_mm = 0x1,        /* [18]     power on mm */
+    .basic_cfg.em_sel = 0x1,             /* [21: 19] em_sel */
+    .basic_cfg.cmds_en = 0x1,            /* [22]     command spliter enable */
+#if 0
+# 0 : cmds bypass wrap commands to macro, original mode;
+# 1 : cmds handle wrap commands, original mode;
+# 2 : cmds bypass wrap commands to macro, cmds force wrap16 * 4 splitted into two wrap8 * 4;
+# 3 : cmds handle wrap commands, cmds force wrap16 * 4 splitted into two wrap8 * 4
+#endif
+    .basic_cfg.cmds_wrap_mode = 0x1, /* [24: 23] cmds wrap mode */
+#if 0
+# 0 : SF_CTRL_WRAP_LEN_8, 1 : SF_CTRL_WRAP_LEN_16, 2 : SF_CTRL_WRAP_LEN_32,
+# 3 : SF_CTRL_WRAP_LEN_64, 9 : SF_CTRL_WRAP_LEN_4096
+#endif
+    .basic_cfg.cmds_wrap_len = 0x9,  /* [28: 25] cmds wrap len */
+    .basic_cfg.icache_invalid = 0x1, /* [29] icache invalid */
+    .basic_cfg.dcache_invalid = 0x1, /* [30] dcache invalid */
+    .basic_cfg.rsvd_3 = 0x0,         /* [31] rsvd_3 */
+
+#ifdef BFLB_BOOT2
+    .basic_cfg.group_image_offset = 0x00002000, /* flash controller offset */
+#else
+    .basic_cfg.group_image_offset = 0x00001000, /* flash controller offset */
+#endif
+    .basic_cfg.aes_region_len = 0x00000000,     /* aes region length */
+
+    .basic_cfg.img_len_cnt = 0x00010000, /* image length or segment count */
+    .basic_cfg.hash = { 0xdeadbeef },    /* hash of the image */
+
+    /* cpu cfg */
+    .cpu_cfg[0].config_enable = 0x01, /* coinfig this cpu */
+    .cpu_cfg[0].halt_cpu = 0x0,       /* halt this cpu */
+    .cpu_cfg[0].cache_enable = 0x0,   /* cache setting :only for BL Cache */
+    .cpu_cfg[0].cache_wa = 0x0,       /* cache setting :only for BL Cache*/
+    .cpu_cfg[0].cache_wb = 0x0,       /* cache setting :only for BL Cache*/
+    .cpu_cfg[0].cache_wt = 0x0,       /* cache setting :only for BL Cache*/
+    .cpu_cfg[0].cache_way_dis = 0x0,  /* cache setting :only for BL Cache*/
+    .cpu_cfg[0].rsvd = 0x0,
+
+    .cpu_cfg[0].cache_range_h = 0x00000000,
+    .cpu_cfg[0].cache_range_l = 0x00000000,
+    /* image_address_offset */
+    .cpu_cfg[0].image_address_offset = 0x0,
+    .cpu_cfg[0].rsvd0 = 0x58000000,   /* rsvd0 */
+    .cpu_cfg[0].msp_val = 0x00000000, /* msp value */
+
+    /* cpu cfg */
+    .cpu_cfg[1].config_enable = 0x0, /* coinfig this cpu */
+    .cpu_cfg[1].halt_cpu = 0x0,      /* halt this cpu */
+    .cpu_cfg[1].cache_enable = 0x0,  /* cache setting :only for BL Cache */
+    .cpu_cfg[1].cache_wa = 0x0,      /* cache setting :only for BL Cache*/
+    .cpu_cfg[1].cache_wb = 0x0,      /* cache setting :only for BL Cache*/
+    .cpu_cfg[1].cache_wt = 0x0,      /* cache setting :only for BL Cache*/
+    .cpu_cfg[1].cache_way_dis = 0x0, /* cache setting :only for BL Cache*/
+    .cpu_cfg[1].rsvd = 0x0,
+
+    .cpu_cfg[1].cache_range_h = 0x00000000,
+    .cpu_cfg[1].cache_range_l = 0x00000000,
+    /* image_address_offset */
+    .cpu_cfg[1].image_address_offset = 0x0,
+    .cpu_cfg[1].rsvd0 = 0x58000000,   /* rsvd0 */
+    .cpu_cfg[1].msp_val = 0x00000000, /* msp value */
+
+    /* address of partition table 0 */ /* 4 */
+    .boot2_pt_table_0_rsvd = 0x00000000,
+    /* address of partition table 1 */ /* 4 */
+    .boot2_pt_table_1_rsvd = 0x00000000,
+
+    /* address of flashcfg table list */ /* 4 */
+    .flash_cfg_table_addr = 0x00000000,
+    /* flashcfg table list len */ /* 4 */
+    .flash_cfg_table_len = 0x00000000,
+
+    .rsvd1[0] = 0x20000320,
+    .rsvd1[1] = 0x00000000,
+    .rsvd1[2] = 0x2000F038,
+    .rsvd1[3] = 0x18000000,
+
+    .crc32 = 0xdeadbeef /* 4 */
+};
diff --git a/bsp/bouffalo_lab/bl808/m0/board/fw_header.h b/bsp/bouffalo_lab/bl808/m0/board/fw_header.h
new file mode 100644
index 0000000000..85fc1db38f
--- /dev/null
+++ b/bsp/bouffalo_lab/bl808/m0/board/fw_header.h
@@ -0,0 +1,213 @@
+#ifndef __FW_HEADER_H__
+#define __FW_HEADER_H__
+
+#include "stdint.h"
+#include "stdio.h"
+
+struct __attribute__((packed, aligned(4))) spi_flash_cfg_t {
+    uint8_t ioMode;               /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
+    uint8_t cReadSupport;         /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
+    uint8_t clkDelay;             /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
+    uint8_t clkInvert;            /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
+    uint8_t resetEnCmd;           /*!< Flash enable reset command */
+    uint8_t resetCmd;             /*!< Flash reset command */
+    uint8_t resetCreadCmd;        /*!< Flash reset continuous read command */
+    uint8_t resetCreadCmdSize;    /*!< Flash reset continuous read command size */
+    uint8_t jedecIdCmd;           /*!< JEDEC ID command */
+    uint8_t jedecIdCmdDmyClk;     /*!< JEDEC ID command dummy clock */
+    uint8_t enter32BitsAddrCmd;   /*!< Enter 32-bits addr command */
+    uint8_t exit32BitsAddrCmd;    /*!< Exit 32-bits addr command */
+    uint8_t sectorSize;           /*!< *1024bytes */
+    uint8_t mid;                  /*!< Manufacturer ID */
+    uint16_t pageSize;            /*!< Page size */
+    uint8_t chipEraseCmd;         /*!< Chip erase cmd */
+    uint8_t sectorEraseCmd;       /*!< Sector erase command */
+    uint8_t blk32EraseCmd;        /*!< Block 32K erase command,some Micron not support */
+    uint8_t blk64EraseCmd;        /*!< Block 64K erase command */
+    uint8_t writeEnableCmd;       /*!< Need before every erase or program */
+    uint8_t pageProgramCmd;       /*!< Page program cmd */
+    uint8_t qpageProgramCmd;      /*!< QIO page program cmd */
+    uint8_t qppAddrMode;          /*!< QIO page program address mode */
+    uint8_t fastReadCmd;          /*!< Fast read command */
+    uint8_t frDmyClk;             /*!< Fast read command dummy clock */
+    uint8_t qpiFastReadCmd;       /*!< QPI fast read command */
+    uint8_t qpiFrDmyClk;          /*!< QPI fast read command dummy clock */
+    uint8_t fastReadDoCmd;        /*!< Fast read dual output command */
+    uint8_t frDoDmyClk;           /*!< Fast read dual output command dummy clock */
+    uint8_t fastReadDioCmd;       /*!< Fast read dual io comamnd */
+    uint8_t frDioDmyClk;          /*!< Fast read dual io command dummy clock */
+    uint8_t fastReadQoCmd;        /*!< Fast read quad output comamnd */
+    uint8_t frQoDmyClk;           /*!< Fast read quad output comamnd dummy clock */
+    uint8_t fastReadQioCmd;       /*!< Fast read quad io comamnd */
+    uint8_t frQioDmyClk;          /*!< Fast read quad io comamnd dummy clock */
+    uint8_t qpiFastReadQioCmd;    /*!< QPI fast read quad io comamnd */
+    uint8_t qpiFrQioDmyClk;       /*!< QPI fast read QIO dummy clock */
+    uint8_t qpiPageProgramCmd;    /*!< QPI program command */
+    uint8_t writeVregEnableCmd;   /*!< Enable write reg */
+    uint8_t wrEnableIndex;        /*!< Write enable register index */
+    uint8_t qeIndex;              /*!< Quad mode enable register index */
+    uint8_t busyIndex;            /*!< Busy status register index */
+    uint8_t wrEnableBit;          /*!< Write enable bit pos */
+    uint8_t qeBit;                /*!< Quad enable bit pos */
+    uint8_t busyBit;              /*!< Busy status bit pos */
+    uint8_t wrEnableWriteRegLen;  /*!< Register length of write enable */
+    uint8_t wrEnableReadRegLen;   /*!< Register length of write enable status */
+    uint8_t qeWriteRegLen;        /*!< Register length of contain quad enable */
+    uint8_t qeReadRegLen;         /*!< Register length of contain quad enable status */
+    uint8_t releasePowerDown;     /*!< Release power down command */
+    uint8_t busyReadRegLen;       /*!< Register length of contain busy status */
+    uint8_t readRegCmd[4];        /*!< Read register command buffer */
+    uint8_t writeRegCmd[4];       /*!< Write register command buffer */
+    uint8_t enterQpi;             /*!< Enter qpi command */
+    uint8_t exitQpi;              /*!< Exit qpi command */
+    uint8_t cReadMode;            /*!< Config data for continuous read mode */
+    uint8_t cRExit;               /*!< Config data for exit continuous read mode */
+    uint8_t burstWrapCmd;         /*!< Enable burst wrap command */
+    uint8_t burstWrapCmdDmyClk;   /*!< Enable burst wrap command dummy clock */
+    uint8_t burstWrapDataMode;    /*!< Data and address mode for this command */
+    uint8_t burstWrapData;        /*!< Data to enable burst wrap */
+    uint8_t deBurstWrapCmd;       /*!< Disable burst wrap command */
+    uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */
+    uint8_t deBurstWrapDataMode;  /*!< Data and address mode for this command */
+    uint8_t deBurstWrapData;      /*!< Data to disable burst wrap */
+    uint16_t timeEsector;         /*!< 4K erase time */
+    uint16_t timeE32k;            /*!< 32K erase time */
+    uint16_t timeE64k;            /*!< 64K erase time */
+    uint16_t timePagePgm;         /*!< Page program time */
+    uint16_t timeCe;              /*!< Chip erase time in ms */
+    uint8_t pdDelay;              /*!< Release power down command delay time for wake up */
+    uint8_t qeData;               /*!< QE set data */
+};
+
+struct __attribute__((packed, aligned(4))) boot_flash_cfg_t {
+    uint32_t magiccode;
+    struct spi_flash_cfg_t cfg;
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) sys_clk_cfg_t {
+    uint8_t xtal_type;
+    uint8_t mcu_clk;
+    uint8_t mcu_clk_div;
+    uint8_t mcu_bclk_div;
+
+    uint8_t mcu_pbclk_div;
+    uint8_t lp_div;
+    uint8_t dsp_clk;
+    uint8_t dsp_clk_div;
+
+    uint8_t dsp_bclk_div;
+    uint8_t dsp_pbclk;
+    uint8_t dsp_pbclk_div;
+    uint8_t emi_clk;
+
+    uint8_t emi_clk_div;
+    uint8_t flash_clk_type;
+    uint8_t flash_clk_div;
+    uint8_t wifipll_pu;
+
+    uint8_t aupll_pu;
+    uint8_t cpupll_pu;
+    uint8_t mipipll_pu;
+    uint8_t uhspll_pu;
+};
+
+struct __attribute__((packed, aligned(4))) boot_clk_cfg_t {
+    uint32_t magiccode;
+    struct sys_clk_cfg_t cfg;
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) boot_basic_cfg_t {
+    uint32_t sign_type          : 2; /* [1: 0]   for sign */
+    uint32_t encrypt_type       : 2; /* [3: 2]   for encrypt */
+    uint32_t key_sel            : 2; /* [5: 4]   key slot */
+    uint32_t xts_mode           : 1; /* [6]      for xts mode */
+    uint32_t aes_region_lock    : 1; /* [7]      rsvd */
+    uint32_t no_segment         : 1; /* [8]      no segment info */
+    uint32_t rsvd_0             : 1; /* [9]      boot2 enable(rsvd_0) */
+    uint32_t rsvd_1             : 1; /* [10]     boot2 rollback(rsvd_1) */
+    uint32_t cpu_master_id      : 4; /* [14: 11] master id */
+    uint32_t notload_in_bootrom : 1; /* [15]     notload in bootrom */
+    uint32_t crc_ignore         : 1; /* [16]     ignore crc */
+    uint32_t hash_ignore        : 1; /* [17]     hash ignore */
+    uint32_t power_on_mm        : 1; /* [18]     power on mm */
+    uint32_t em_sel             : 3; /* [21: 19] em_sel */
+    uint32_t cmds_en            : 1; /* [22]     command spliter enable */
+    uint32_t cmds_wrap_mode     : 2; /* [24: 23] cmds wrap mode */
+    uint32_t cmds_wrap_len      : 4; /* [28: 25] cmds wrap len */
+    uint32_t icache_invalid     : 1; /* [29] icache invalid */
+    uint32_t dcache_invalid     : 1; /* [30] dcache invalid */
+    uint32_t rsvd_3             : 1; /* [31] rsvd_3 */
+
+    uint32_t group_image_offset; /* flash controller offset */
+    uint32_t aes_region_len;     /* aes region length */
+
+    uint32_t img_len_cnt;  /* image length or segment count */
+    uint32_t hash[32 / 4]; /* hash of the image */
+};
+
+struct __attribute__((packed, aligned(4))) boot_cpu_cfg_t {
+    uint8_t config_enable;     /* coinfig this cpu */
+    uint8_t halt_cpu;          /* halt this cpu */
+    uint8_t cache_enable  : 1; /* cache setting */
+    uint8_t cache_wa      : 1; /* cache setting */
+    uint8_t cache_wb      : 1; /* cache setting */
+    uint8_t cache_wt      : 1; /* cache setting */
+    uint8_t cache_way_dis : 4; /* cache setting */
+    uint8_t rsvd;
+
+    uint32_t cache_range_h; /* cache range high */
+    uint32_t cache_range_l; /* cache range low */
+
+    uint32_t image_address_offset; /* image_address_offset */
+    uint32_t rsvd0;                /* rsvd0 */
+    uint32_t msp_val;              /* msp value */
+};
+
+struct __attribute__((packed, aligned(4))) aesiv_cfg_t {
+    uint8_t aesiv[16];
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) pkey_cfg_t {
+    uint8_t eckeyx[32]; /* ec key in boot header */
+    uint8_t eckeyy[32]; /* ec key in boot header */
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) sign_cfg_t {
+    uint32_t sig_len;
+    uint8_t signature[32];
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) bootheader_t {
+    uint32_t magiccode; /* 4 */
+    uint32_t rivison;   /* 4 */
+
+    struct boot_flash_cfg_t flash_cfg; /* 4 + 84 + 4 */
+    struct boot_clk_cfg_t clk_cfg;     /* 4 + 20 + 4 */
+
+    struct boot_basic_cfg_t basic_cfg; /* 4 + 4 + 4 + 4 + 4*8 */
+
+    struct boot_cpu_cfg_t cpu_cfg[3]; /*24*3 */
+
+    uint32_t boot2_pt_table_0_rsvd; /* address of partition table 0 */ /* 4 */
+    uint32_t boot2_pt_table_1_rsvd; /* address of partition table 1 */ /* 4 */
+
+    uint32_t flash_cfg_table_addr; /* address of flashcfg table list */ /* 4 */
+    uint32_t flash_cfg_table_len; /* flashcfg table list len */         /* 4 */
+
+    uint32_t rsvd0[8]; /* rsvd */
+    uint32_t rsvd1[8]; /* rsvd */
+
+    uint32_t rsvd3[5]; /* 20 */
+
+    uint32_t crc32; /* 4 */
+};
+
+#define BFLB_FW_LENGTH_OFFSET 140
+#define BFLB_FW_HASH_OFFSET   144
+
+#endif
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/bl808_flash.ld b/bsp/bouffalo_lab/bl808/m0/board/linker_scripts/bl808_flash_m0.ld
old mode 100644
new mode 100755
similarity index 79%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/bl808_flash.ld
rename to bsp/bouffalo_lab/bl808/m0/board/linker_scripts/bl808_flash_m0.ld
index 6090dd6f1a..2dc1f8fa37
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/bl808_flash.ld
+++ b/bsp/bouffalo_lab/bl808/m0/board/linker_scripts/bl808_flash_m0.ld
@@ -15,52 +15,69 @@ INPUT(-lc)
 /* link with the standard GCC library */
 INPUT(-lgcc)
 /* configure the entry point */
-ENTRY(Reset_Handler)
+ENTRY(__start)
 
 StackSize    = 0x0400; /*  1KB */
 HeapMinSize  = 0x1000; /*  4KB */
 
 MEMORY
 {
+    fw_header_memory  (rx)  : ORIGIN = 0x58000000 - 0x1000, LENGTH = 4K
     xip_memory  (rx)  : ORIGIN = 0x58000000, LENGTH = 32M
-    itcm_memory (rx)  : ORIGIN = 0x62028000, LENGTH = 28K
-    dtcm_memory (rx)  : ORIGIN = 0x6202F000, LENGTH = 4K
-    nocache_ram_memory (!rx) : ORIGIN = 0x22030000, LENGTH = 0K
-    ram_memory  (!rx) : ORIGIN = 0x62030000, LENGTH = 160K
+    itcm_memory (rx)  : ORIGIN = 0x62020000, LENGTH = 20K
+    dtcm_memory (rx)  : ORIGIN = 0x62025000, LENGTH = 4K
+    nocache_ram_memory (!rx) : ORIGIN = 0x22026000, LENGTH = 40K
+    ram_memory  (!rx) : ORIGIN = 0x62030000, LENGTH = 160K + 64K - 20K - 4K - 40K
     xram_memory  (!rx) : ORIGIN = 0x40000000, LENGTH = 16K
 }
 
 SECTIONS
 {
+    .fw_header :
+    {
+        KEEP(*(.fw_header))
+    } > fw_header_memory
 
     .text :
     {
         . = ALIGN(4);
         __text_code_start__ = .;
-        KEEP(*startup*.*o(*.text*))
-        KEEP (*(SORT_NONE(_start)))
-        KEEP (*(SORT_NONE(Reset_Handler)))
+
+        KEEP (*(SORT_NONE(.init)))
+        KEEP (*(SORT_NONE(.vector)))
 
         *(.text)
         *(.text.*)
 
-        /* section information for shell */
+        /* section information for finsh shell */
         . = ALIGN(4);
         __fsymtab_start = .;
         KEEP(*(FSymTab))
         __fsymtab_end = .;
-
         . = ALIGN(4);
         __vsymtab_start = .;
         KEEP(*(VSymTab))
         __vsymtab_end = .;
+        . = ALIGN(4);
 
-        /* section information for usb desc */
+        /* section information for modules */
         . = ALIGN(4);
-        _usb_desc_start = .;
-        KEEP(*(usb_desc))
+        __rtmsymtab_start = .;
+        KEEP(*(RTMSymTab))
+        __rtmsymtab_end = .;
+
+        /* section information for initialization */
         . = ALIGN(4);
-        _usb_desc_end = .;
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+
+        /* section information for usb usbh_class_info */
+        . = ALIGN(4);
+        __usbh_class_info_start__ = .;
+        KEEP(*(.usbh_class_info))
+        . = ALIGN(4);
+        __usbh_class_info_end__ = .;
 
         /*put .rodata**/
         *(EXCLUDE_FILE( *bl808_glb*.o* \
@@ -145,6 +162,7 @@ SECTIONS
      * size of stack_dummy section */
     __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);
     PROVIDE( __freertos_irq_stack_top = __StackTop);
+    PROVIDE( __rt_rvstack = . );
     __StackLimit = __StackTop - SIZEOF(.stack_dummy);
 
     /* Check if data + heap + stack exceeds RAM limit */
@@ -152,7 +170,7 @@ SECTIONS
     /*************************************************************************/
     __nocache_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
 
-    .nocache_ram_region (NOLOAD) : AT (__nocache_ram_load_addr)
+    .nocache_ram_region  : AT (__nocache_ram_load_addr)
     {
         . = ALIGN(4);
         __nocache_ram_data_start__ = .;
@@ -163,28 +181,7 @@ SECTIONS
         __nocache_ram_data_end__ = .;
     } > nocache_ram_memory
 
-    __system_ram_load_addr = __nocache_ram_load_addr + SIZEOF(.nocache_ram_region);
-
-    .system_ram_data_region : AT (__system_ram_load_addr)
-    {
-        . = ALIGN(4);
-        __system_ram_data_start__ = .;
-
-        *(.system_ram)
-
-        . = ALIGN(4);
-        __system_ram_data_end__ = .;
-    } > ram_memory
-
-    .system_ram_noinit_data_region (NOLOAD) :
-    {
-        . = ALIGN(4);
-        *(.system_ram_noinit)
-
-        . = ALIGN(4);
-    } > ram_memory
-
-    __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region);
+    __ram_load_addr = __nocache_ram_load_addr + SIZEOF(.nocache_ram_region);
 
     /* Data section */
     RAM_DATA : AT (__ram_load_addr)
@@ -202,6 +199,10 @@ SECTIONS
         *(.sdata2.*)
 
         . = ALIGN(4);
+        __bflog_tags_start__ = .;
+        *(.bflog_tags_array)
+        . = ALIGN(4);
+        __bflog_tags_end__ = .;
         __ram_data_end__ = .;
     } > ram_memory
 
@@ -232,17 +233,18 @@ SECTIONS
         __noinit_data_end__ = .;
     } > ram_memory
 
-    .nocache_noinit_ram_region (NOLOAD) : 
+    .nocache_noinit_ram_region (NOLOAD) :
     {
         . = ALIGN(4);
-        __nocache_ram_data_start__ = .;
+        __nocache_noinit_ram_data_start__ = .;
 
         *(.nocache_noinit_ram)
+        *(.noncacheable)
 
         . = ALIGN(4);
-        __nocache_ram_data_end__ = .;
+        __nocache_noinit_ram_data_end__ = .;
     } > nocache_ram_memory
-    
+
     .heap (NOLOAD):
     {
         . = ALIGN(4);
diff --git a/bsp/bouffalo_lab/bl808/m0/board/trap_gcc.S b/bsp/bouffalo_lab/bl808/m0/board/trap_gcc.S
new file mode 100755
index 0000000000..a255ed7d09
--- /dev/null
+++ b/bsp/bouffalo_lab/bl808/m0/board/trap_gcc.S
@@ -0,0 +1,17 @@
+#include "cpuport.h"
+
+	.globl rt_hw_do_after_save_above
+	.type rt_hw_do_after_save_above,@function
+rt_hw_do_after_save_above:
+    addi  sp, sp,  -4
+    STORE ra,  0 * REGBYTES(sp)
+
+	csrr    t1, mcause
+    andi    t1, t1, 0x3FF
+    /* get ISR */
+    la      t2, interrupt_entry
+    jalr    t2
+    
+    LOAD  ra,  0 * REGBYTES(sp)
+    addi  sp, sp,  4
+    ret
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/bl808/m0/combine.sh b/bsp/bouffalo_lab/bl808/m0/combine.sh
new file mode 100755
index 0000000000..ee1436b881
--- /dev/null
+++ b/bsp/bouffalo_lab/bl808/m0/combine.sh
@@ -0,0 +1,39 @@
+#/bin/sh
+CHIPNAME=$1
+BIN_FILE=$2
+
+set -e
+
+SYSTEM=`uname -s`
+echo "system: $SYSTEM"
+
+CONFIG=../config
+TOOL_DIR=../../libraries/bl_mcu_sdk/tools/bflb_tools/bflb_fw_post_proc
+
+if [ $SYSTEM = "Darwin" ]
+then
+    TOOL_NAME=bflb_fw_post_proc-macos
+    TOOL_ADDR=https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc-macos
+elif [ $SYSTEM = "Linux" ]
+then
+    TOOL_NAME=bflb_fw_post_proc-ubuntu
+    TOOL_ADDR=https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc-ubuntu
+else
+    TOOL_NAME=bflb_fw_post_proc.exe
+    TOOL_ADDR=https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc.exe
+fi
+
+if [ -f "$TOOL_DIR/$TOOL_NAME" ]
+then
+    echo "bflb_fw_post_proc exist"
+else
+    echo "bflb_fw_post_proc not exist, try download... url:$TOOL_ADDR"
+    curl $TOOL_ADDR -o $TOOL_DIR/$TOOL_NAME
+    if [ $SYSTEM = "Darwin" ]; then
+        chmod +x $TOOL_DIR/$TOOL_NAME
+    elif [ $SYSTEM = "Linux" ]; then
+        chmod +x $TOOL_DIR/$TOOL_NAME
+    fi
+fi
+
+./$TOOL_DIR/$TOOL_NAME --chipname=$CHIPNAME --brdcfgdir=$CONFIG --imgfile=$BIN_FILE
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/bl808/m0/flash_prog_cfg.ini b/bsp/bouffalo_lab/bl808/m0/flash_prog_cfg.ini
new file mode 100755
index 0000000000..090dc7a363
--- /dev/null
+++ b/bsp/bouffalo_lab/bl808/m0/flash_prog_cfg.ini
@@ -0,0 +1,12 @@
+[cfg]
+# 0: no erase, 1:programmed section erase, 2: chip erase
+erase = 1
+# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated
+skip_mode = 0x0, 0x0
+# 0: not use isp mode, #1: isp mode
+boot2_isp_mode = 0
+
+[FW]
+filedir = ./rtthread_m0.bin
+# since D0 is boot by M0，this address should consistent with m0's board_init in board.c
+address = 0x000000
\ No newline at end of file
diff --git a/bsp/bl808/m0/rtconfig.h b/bsp/bouffalo_lab/bl808/m0/rtconfig.h
similarity index 92%
rename from bsp/bl808/m0/rtconfig.h
rename to bsp/bouffalo_lab/bl808/m0/rtconfig.h
index c8d155b675..7d7e932214 100644
--- a/bsp/bl808/m0/rtconfig.h
+++ b/bsp/bouffalo_lab/bl808/m0/rtconfig.h
@@ -19,7 +19,7 @@
 #define IDLE_THREAD_STACK_SIZE 1024
 #define RT_USING_TIMER_SOFT
 #define RT_TIMER_THREAD_PRIO 4
-#define RT_TIMER_THREAD_STACK_SIZE 1024
+#define RT_TIMER_THREAD_STACK_SIZE 512
 
 /* kservice optimization */
 
@@ -36,9 +36,10 @@
 
 /* Memory Management */
 
+#define RT_PAGE_MAX_ORDER 11
+#define RT_USING_MEMPOOL
 #define RT_USING_SMALL_MEM
 #define RT_USING_SMALL_MEM_AS_HEAP
-#define RT_USING_MEMTRACE
 #define RT_USING_HEAP
 
 /* Kernel Device Object */
@@ -48,8 +49,10 @@
 #define RT_CONSOLEBUF_SIZE 128
 #define RT_CONSOLE_DEVICE_NAME "uart0"
 #define RT_VER_NUM 0x50000
+#define ARCH_RISCV
 #define ARCH_RISCV_FPU
 #define ARCH_RISCV_FPU_S
+#define ARCH_RISCV32
 
 /* RT-Thread Components */
 
@@ -216,21 +219,22 @@
 
 /* Other */
 
+
 /* Signal IO */
 
 
 /* Uncategorized */
 
-/* BL808_M0 Hardware Drivers Config */
+#define BSP_USING_BL808
+#define BL808_CORE_M0
 
-#define SOC_BL808
+/* General Drivers Configuration */
 
-/* On-chip Peripheral Drivers */
 
-#define BSP_USING_GPIO
-#define BSP_USING_UART
+/* General Purpose UARTs */
+
 #define BSP_USING_UART0
-#define BSP_UART0_TXD_PIN 14
-#define BSP_UART0_RXD_PIN 15
+#define UART0_TX_USING_GPIO14
+#define UART0_RX_USING_GPIO15
 
 #endif
diff --git a/bsp/bl808/m0/rtconfig.py b/bsp/bouffalo_lab/bl808/m0/rtconfig.py
old mode 100644
new mode 100755
similarity index 55%
rename from bsp/bl808/m0/rtconfig.py
rename to bsp/bouffalo_lab/bl808/m0/rtconfig.py
index a9c7ad4d54..f8d18aa968
--- a/bsp/bl808/m0/rtconfig.py
+++ b/bsp/bouffalo_lab/bl808/m0/rtconfig.py
@@ -2,14 +2,13 @@ import os
 
 # toolchains options
 ARCH        ='risc-v'
-VENDOR      ='t-head'
 CPU         ='e9xx'
 CROSS_TOOL  ='gcc'
 
 if os.getenv('RTT_ROOT'):
     RTT_ROOT = os.getenv('RTT_ROOT')
 else:
-    RTT_ROOT = r'../../..'
+    RTT_ROOT = r'../../../..'
 
 if os.getenv('RTT_CC'):
     CROSS_TOOL = os.getenv('RTT_CC')
@@ -39,23 +38,20 @@ if PLATFORM == 'gcc':
     OBJDUMP = PREFIX + 'objdump'
     OBJCPY  = PREFIX + 'objcopy'
 
-    DEVICE  = ' -march=rv32imafcxthead -mabi=ilp32f -mtune=e907 -mcmodel=medany'
-    CFLAGS  = DEVICE + ' -Wall -Wno-error=unused-function -Wno-error=unused-but-set-variable -Wno-error=unused-variable -Wno-error=deprecated-declarations -Wextra -Wno-unused-parameter -Wno-sign-compare'
-    CFLAGS += ' -Wno-old-style-declaration -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -fshort-enums -fcommon -ffreestanding -fno-strict-aliasing -fno-jump-tables -save-temps=obj'
+    DEVICE  = ' -march=rv32imafcpzpsfoperand_xtheade -mabi=ilp32f -mtune=e907'
+    CFLAGS  = DEVICE + ' -std=gnu99 -fno-jump-tables -fno-common -fms-extensions -ffunction-sections -fdata-sections -fmessage-length=0 -Wall -Wchar-subscripts -Wformat -Wundef -Wuninitialized -Winit-self -Wignored-qualifiers'
+    CFLAGS += ' -fstrict-volatile-bitfields -fshort-enums -Wno-error=unused-variable -Wno-error=format= -Wno-error=unused-function -Wno-error=implicit-function-declaration -Wno-error=deprecated-declarations -Wno-format'
 
-    LINKER_SCRIPTS_PATH = r'libraries/platform/soc/bl808/startup_bl808/evb/ld/'
-    LINKER_SCRIPTS = 'bl808_flash.ld'
-
-    CFLAGS += ' -DCFG_COMPONENT_BLOG_ENABLE=0 -DARCH_RISCV -DBFLB_USE_HAL_DRIVER -DCPU_M0 -DBL808'
+    LINKER_SCRIPTS = r'board/linker_scripts/bl808_flash_m0.ld'
 
     AFLAGS  = ' -c' + DEVICE + ' -x assembler-with-cpp'
-    LFLAGS  = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T ' + LINKER_SCRIPTS_PATH + LINKER_SCRIPTS
+    LFLAGS  = DEVICE + ' -nostartfiles -ufw_header -fms-extensions -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T ' + LINKER_SCRIPTS
     CPATH   = ''
     LPATH   = ''
 
     if BUILD == 'debug':
-        CFLAGS += ' -O0 -gdwarf'
-        AFLAGS += ' -gdwarf'
+        CFLAGS += ' -O2 -g3'
+        AFLAGS += ' -g3'
     else:
         CFLAGS += ' -O3'
 
@@ -63,3 +59,4 @@ if PLATFORM == 'gcc':
 
 DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
 POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread_m0.bin\n' + SIZE + ' $TARGET \n'
+POST_ACTION += 'sh combine.sh bl808 ./rtthread_m0.bin\n'
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/bouffalo_flash_cube.sh b/bsp/bouffalo_lab/bouffalo_flash_cube.sh
new file mode 100755
index 0000000000..07c7974681
--- /dev/null
+++ b/bsp/bouffalo_lab/bouffalo_flash_cube.sh
@@ -0,0 +1,42 @@
+#/bin/sh
+CHIPNAME=$1
+PORT=$2
+
+set -e
+
+SYSTEM=`uname -s`
+TOOL_SUFFIX=-ubuntu
+echo "system: $SYSTEM"
+
+if [ $SYSTEM = "Darwin" ]
+then
+    TOOL_SUFFIX=-macos
+elif [ $SYSTEM = "Linux" ]
+then
+    TOOL_SUFFIX=-ubuntu
+else
+    TOOL_SUFFIX=.exe
+fi
+
+CONFIG_DIR=./bl60x
+if [ $CHIPNAME = 'bl602' ]
+then
+    CONFIG_DIR=./bl60x
+elif [ $CHIPNAME = 'bl616' ]
+then
+    CONFIG_DIR=./bl61x
+elif [ $CHIPNAME = 'bl702' ]
+then
+    CONFIG_DIR=./bl70x
+elif [ $CHIPNAME = 'bl808' ]
+then
+    CONFIG_DIR=./bl808
+else
+    echo "chip name error"
+fi
+
+TOOL_DIR=./libraries/bl_mcu_sdk/tools/bflb_tools/bouffalo_flash_cube
+TOOL_NAME='BLFlashCommand'$TOOL_SUFFIX
+CONFIG_FILE=$CONFIG_DIR'/flash_prog_cfg.ini'
+
+./$TOOL_DIR/$TOOL_NAME --interface=uart --baudrate=2000000 --chipname=$CHIPNAME --config=$CONFIG_FILE --port=$PORT
diff --git a/bsp/bouffalo_lab/figures/bouffalo_flash_cube.jpg b/bsp/bouffalo_lab/figures/bouffalo_flash_cube.jpg
new file mode 100755
index 0000000000..ddaeaa5e75
Binary files /dev/null and b/bsp/bouffalo_lab/figures/bouffalo_flash_cube.jpg differ
diff --git a/bsp/bl808/figures/bl808.jpg b/bsp/bouffalo_lab/figures/rt-thread.jpg
old mode 100644
new mode 100755
similarity index 100%
rename from bsp/bl808/figures/bl808.jpg
rename to bsp/bouffalo_lab/figures/rt-thread.jpg
diff --git a/bsp/bouffalo_lab/libraries/Kconfig b/bsp/bouffalo_lab/libraries/Kconfig
new file mode 100755
index 0000000000..f9c6d3e44c
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/Kconfig
@@ -0,0 +1,2 @@
+source "$BSP_DIR/$LIBRARIES_DIR/rt_drivers/Kconfig"
+
diff --git a/bsp/bl808/m0/libraries/.ignore_format.yml b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/.ignore_format.yml
old mode 100644
new mode 100755
similarity index 90%
rename from bsp/bl808/m0/libraries/.ignore_format.yml
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/.ignore_format.yml
index 526edb3898..5ed52d4c4f
--- a/bsp/bl808/m0/libraries/.ignore_format.yml
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/.ignore_format.yml
@@ -3,6 +3,5 @@
 # If you need to exclude a file, add the path to the file in file_path.
 
 dir_path:
-- platform
-- stage
-- utils
\ No newline at end of file
+- drivers
+- tools
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/SConscript b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/SConscript
new file mode 100755
index 0000000000..4c815c49b8
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/SConscript
@@ -0,0 +1,15 @@
+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/SConscript b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/SConscript
new file mode 100755
index 0000000000..4c815c49b8
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/SConscript
@@ -0,0 +1,15 @@
+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/Doxyfile b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/Doxyfile
new file mode 100755
index 0000000000..40709eb270
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/Doxyfile
@@ -0,0 +1,2768 @@
+# Doxyfile 1.9.5
+
+# This file describes the settings to be used by the documentation system
+# doxygen (www.doxygen.org) for a project.
+#
+# All text after a double hash (##) is considered a comment and is placed in
+# front of the TAG it is preceding.
+#
+# All text after a single hash (#) is considered a comment and will be ignored.
+# The format is:
+# TAG = value [value, ...]
+# For lists, items can also be appended using:
+# TAG += value [value, ...]
+# Values that contain spaces should be placed between quotes (\" \").
+#
+# Note:
+#
+# Use doxygen to compare the used configuration file with the template
+# configuration file:
+# doxygen -x [configFile]
+# Use doxygen to compare the used configuration file with the template
+# configuration file without replacing the environment variables or CMake type
+# replacement variables:
+# doxygen -x_noenv [configFile]
+
+#---------------------------------------------------------------------------
+# Project related configuration options
+#---------------------------------------------------------------------------
+
+# This tag specifies the encoding used for all characters in the configuration
+# file that follow. The default is UTF-8 which is also the encoding used for all
+# text before the first occurrence of this tag. Doxygen uses libiconv (or the
+# iconv built into libc) for the transcoding. See
+# https://www.gnu.org/software/libiconv/ for the list of possible encodings.
+# The default value is: UTF-8.
+
+DOXYFILE_ENCODING      = UTF-8
+
+# The PROJECT_NAME tag is a single word (or a sequence of words surrounded by
+# double-quotes, unless you are using Doxywizard) that should identify the
+# project for which the documentation is generated. This name is used in the
+# title of most generated pages and in a few other places.
+# The default value is: My Project.
+
+PROJECT_NAME           = "LHAL Driver"
+
+# The PROJECT_NUMBER tag can be used to enter a project or revision number. This
+# could be handy for archiving the generated documentation or if some version
+# control system is used.
+
+PROJECT_NUMBER         = 1.0
+
+# Using the PROJECT_BRIEF tag one can provide an optional one line description
+# for a project that appears at the top of each page and should give viewer a
+# quick idea about the purpose of the project. Keep the description short.
+
+PROJECT_BRIEF          = "LHAL Drivers for bouffalolab Series MicroController"
+
+# With the PROJECT_LOGO tag one can specify a logo or an icon that is included
+# in the documentation. The maximum height of the logo should not exceed 55
+# pixels and the maximum width should not exceed 200 pixels. Doxygen will copy
+# the logo to the output directory.
+
+PROJECT_LOGO           =
+
+# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) path
+# into which the generated documentation will be written. If a relative path is
+# entered, it will be relative to the location where doxygen was started. If
+# left blank the current directory will be used.
+
+OUTPUT_DIRECTORY       = doc
+
+# If the CREATE_SUBDIRS tag is set to YES then doxygen will create up to 4096
+# sub-directories (in 2 levels) under the output directory of each output format
+# and will distribute the generated files over these directories. Enabling this
+# option can be useful when feeding doxygen a huge amount of source files, where
+# putting all generated files in the same directory would otherwise causes
+# performance problems for the file system. Adapt CREATE_SUBDIRS_LEVEL to
+# control the number of sub-directories.
+# The default value is: NO.
+
+CREATE_SUBDIRS         = NO
+
+# Controls the number of sub-directories that will be created when
+# CREATE_SUBDIRS tag is set to YES. Level 0 represents 16 directories, and every
+# level increment doubles the number of directories, resulting in 4096
+# directories at level 8 which is the default and also the maximum value. The
+# sub-directories are organized in 2 levels, the first level always has a fixed
+# numer of 16 directories.
+# Minimum value: 0, maximum value: 8, default value: 8.
+# This tag requires that the tag CREATE_SUBDIRS is set to YES.
+
+CREATE_SUBDIRS_LEVEL   = 8
+
+# If the ALLOW_UNICODE_NAMES tag is set to YES, doxygen will allow non-ASCII
+# characters to appear in the names of generated files. If set to NO, non-ASCII
+# characters will be escaped, for example _xE3_x81_x84 will be used for Unicode
+# U+3044.
+# The default value is: NO.
+
+ALLOW_UNICODE_NAMES    = NO
+
+# The OUTPUT_LANGUAGE tag is used to specify the language in which all
+# documentation generated by doxygen is written. Doxygen will use this
+# information to generate all constant output in the proper language.
+# Possible values are: Afrikaans, Arabic, Armenian, Brazilian, Bulgarian,
+# Catalan, Chinese, Chinese-Traditional, Croatian, Czech, Danish, Dutch, English
+# (United States), Esperanto, Farsi (Persian), Finnish, French, German, Greek,
+# Hindi, Hungarian, Indonesian, Italian, Japanese, Japanese-en (Japanese with
+# English messages), Korean, Korean-en (Korean with English messages), Latvian,
+# Lithuanian, Macedonian, Norwegian, Persian (Farsi), Polish, Portuguese,
+# Romanian, Russian, Serbian, Serbian-Cyrillic, Slovak, Slovene, Spanish,
+# Swedish, Turkish, Ukrainian and Vietnamese.
+# The default value is: English.
+
+OUTPUT_LANGUAGE        = Chinese
+
+# If the BRIEF_MEMBER_DESC tag is set to YES, doxygen will include brief member
+# descriptions after the members that are listed in the file and class
+# documentation (similar to Javadoc). Set to NO to disable this.
+# The default value is: YES.
+
+BRIEF_MEMBER_DESC      = YES
+
+# If the REPEAT_BRIEF tag is set to YES, doxygen will prepend the brief
+# description of a member or function before the detailed description
+#
+# Note: If both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the
+# brief descriptions will be completely suppressed.
+# The default value is: YES.
+
+REPEAT_BRIEF           = YES
+
+# This tag implements a quasi-intelligent brief description abbreviator that is
+# used to form the text in various listings. Each string in this list, if found
+# as the leading text of the brief description, will be stripped from the text
+# and the result, after processing the whole list, is used as the annotated
+# text. Otherwise, the brief description is used as-is. If left blank, the
+# following values are used ($name is automatically replaced with the name of
+# the entity):The $name class, The $name widget, The $name file, is, provides,
+# specifies, contains, represents, a, an and the.
+
+ABBREVIATE_BRIEF       = "The $name class" \
+                         "The $name widget" \
+                         "The $name file" \
+                         is \
+                         provides \
+                         specifies \
+                         contains \
+                         represents \
+                         a \
+                         an \
+                         the
+
+# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then
+# doxygen will generate a detailed section even if there is only a brief
+# description.
+# The default value is: NO.
+
+ALWAYS_DETAILED_SEC    = NO
+
+# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all
+# inherited members of a class in the documentation of that class as if those
+# members were ordinary class members. Constructors, destructors and assignment
+# operators of the base classes will not be shown.
+# The default value is: NO.
+
+INLINE_INHERITED_MEMB  = NO
+
+# If the FULL_PATH_NAMES tag is set to YES, doxygen will prepend the full path
+# before files name in the file list and in the header files. If set to NO the
+# shortest path that makes the file name unique will be used
+# The default value is: YES.
+
+FULL_PATH_NAMES        = YES
+
+# The STRIP_FROM_PATH tag can be used to strip a user-defined part of the path.
+# Stripping is only done if one of the specified strings matches the left-hand
+# part of the path. The tag can be used to show relative paths in the file list.
+# If left blank the directory from which doxygen is run is used as the path to
+# strip.
+#
+# Note that you can specify absolute paths here, but also relative paths, which
+# will be relative from the directory where doxygen is started.
+# This tag requires that the tag FULL_PATH_NAMES is set to YES.
+
+STRIP_FROM_PATH        =
+
+# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of the
+# path mentioned in the documentation of a class, which tells the reader which
+# header file to include in order to use a class. If left blank only the name of
+# the header file containing the class definition is used. Otherwise one should
+# specify the list of include paths that are normally passed to the compiler
+# using the -I flag.
+
+STRIP_FROM_INC_PATH    =
+
+# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter (but
+# less readable) file names. This can be useful is your file systems doesn't
+# support long names like on DOS, Mac, or CD-ROM.
+# The default value is: NO.
+
+SHORT_NAMES            = NO
+
+# If the JAVADOC_AUTOBRIEF tag is set to YES then doxygen will interpret the
+# first line (until the first dot) of a Javadoc-style comment as the brief
+# description. If set to NO, the Javadoc-style will behave just like regular Qt-
+# style comments (thus requiring an explicit @brief command for a brief
+# description.)
+# The default value is: NO.
+
+JAVADOC_AUTOBRIEF      = NO
+
+# If the JAVADOC_BANNER tag is set to YES then doxygen will interpret a line
+# such as
+# /***************
+# as being the beginning of a Javadoc-style comment "banner". If set to NO, the
+# Javadoc-style will behave just like regular comments and it will not be
+# interpreted by doxygen.
+# The default value is: NO.
+
+JAVADOC_BANNER         = NO
+
+# If the QT_AUTOBRIEF tag is set to YES then doxygen will interpret the first
+# line (until the first dot) of a Qt-style comment as the brief description. If
+# set to NO, the Qt-style will behave just like regular Qt-style comments (thus
+# requiring an explicit \brief command for a brief description.)
+# The default value is: NO.
+
+QT_AUTOBRIEF           = NO
+
+# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make doxygen treat a
+# multi-line C++ special comment block (i.e. a block of //! or /// comments) as
+# a brief description. This used to be the default behavior. The new default is
+# to treat a multi-line C++ comment block as a detailed description. Set this
+# tag to YES if you prefer the old behavior instead.
+#
+# Note that setting this tag to YES also means that rational rose comments are
+# not recognized any more.
+# The default value is: NO.
+
+MULTILINE_CPP_IS_BRIEF = NO
+
+# By default Python docstrings are displayed as preformatted text and doxygen's
+# special commands cannot be used. By setting PYTHON_DOCSTRING to NO the
+# doxygen's special commands can be used and the contents of the docstring
+# documentation blocks is shown as doxygen documentation.
+# The default value is: YES.
+
+PYTHON_DOCSTRING       = YES
+
+# If the INHERIT_DOCS tag is set to YES then an undocumented member inherits the
+# documentation from any documented member that it re-implements.
+# The default value is: YES.
+
+INHERIT_DOCS           = YES
+
+# If the SEPARATE_MEMBER_PAGES tag is set to YES then doxygen will produce a new
+# page for each member. If set to NO, the documentation of a member will be part
+# of the file/class/namespace that contains it.
+# The default value is: NO.
+
+SEPARATE_MEMBER_PAGES  = NO
+
+# The TAB_SIZE tag can be used to set the number of spaces in a tab. Doxygen
+# uses this value to replace tabs by spaces in code fragments.
+# Minimum value: 1, maximum value: 16, default value: 4.
+
+TAB_SIZE               = 4
+
+# This tag can be used to specify a number of aliases that act as commands in
+# the documentation. An alias has the form:
+# name=value
+# For example adding
+# "sideeffect=@par Side Effects:^^"
+# will allow you to put the command \sideeffect (or @sideeffect) in the
+# documentation, which will result in a user-defined paragraph with heading
+# "Side Effects:". Note that you cannot put \n's in the value part of an alias
+# to insert newlines (in the resulting output). You can put ^^ in the value part
+# of an alias to insert a newline as if a physical newline was in the original
+# file. When you need a literal { or } or , in the value part of an alias you
+# have to escape them by means of a backslash (\), this can lead to conflicts
+# with the commands \{ and \} for these it is advised to use the version @{ and
+# @} or use a double escape (\\{ and \\})
+
+ALIASES                =
+
+# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C sources
+# only. Doxygen will then generate output that is more tailored for C. For
+# instance, some of the names that are used will be different. The list of all
+# members will be omitted, etc.
+# The default value is: NO.
+
+OPTIMIZE_OUTPUT_FOR_C  = YES
+
+# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java or
+# Python sources only. Doxygen will then generate output that is more tailored
+# for that language. For instance, namespaces will be presented as packages,
+# qualified scopes will look different, etc.
+# The default value is: NO.
+
+OPTIMIZE_OUTPUT_JAVA   = NO
+
+# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran
+# sources. Doxygen will then generate output that is tailored for Fortran.
+# The default value is: NO.
+
+OPTIMIZE_FOR_FORTRAN   = NO
+
+# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL
+# sources. Doxygen will then generate output that is tailored for VHDL.
+# The default value is: NO.
+
+OPTIMIZE_OUTPUT_VHDL   = NO
+
+# Set the OPTIMIZE_OUTPUT_SLICE tag to YES if your project consists of Slice
+# sources only. Doxygen will then generate output that is more tailored for that
+# language. For instance, namespaces will be presented as modules, types will be
+# separated into more groups, etc.
+# The default value is: NO.
+
+OPTIMIZE_OUTPUT_SLICE  = NO
+
+# Doxygen selects the parser to use depending on the extension of the files it
+# parses. With this tag you can assign which parser to use for a given
+# extension. Doxygen has a built-in mapping, but you can override or extend it
+# using this tag. The format is ext=language, where ext is a file extension, and
+# language is one of the parsers supported by doxygen: IDL, Java, JavaScript,
+# Csharp (C#), C, C++, Lex, D, PHP, md (Markdown), Objective-C, Python, Slice,
+# VHDL, Fortran (fixed format Fortran: FortranFixed, free formatted Fortran:
+# FortranFree, unknown formatted Fortran: Fortran. In the later case the parser
+# tries to guess whether the code is fixed or free formatted code, this is the
+# default for Fortran type files). For instance to make doxygen treat .inc files
+# as Fortran files (default is PHP), and .f files as C (default is Fortran),
+# use: inc=Fortran f=C.
+#
+# Note: For files without extension you can use no_extension as a placeholder.
+#
+# Note that for custom extensions you also need to set FILE_PATTERNS otherwise
+# the files are not read by doxygen. When specifying no_extension you should add
+# * to the FILE_PATTERNS.
+#
+# Note see also the list of default file extension mappings.
+
+EXTENSION_MAPPING      =
+
+# If the MARKDOWN_SUPPORT tag is enabled then doxygen pre-processes all comments
+# according to the Markdown format, which allows for more readable
+# documentation. See https://daringfireball.net/projects/markdown/ for details.
+# The output of markdown processing is further processed by doxygen, so you can
+# mix doxygen, HTML, and XML commands with Markdown formatting. Disable only in
+# case of backward compatibilities issues.
+# The default value is: YES.
+
+MARKDOWN_SUPPORT       = YES
+
+# When the TOC_INCLUDE_HEADINGS tag is set to a non-zero value, all headings up
+# to that level are automatically included in the table of contents, even if
+# they do not have an id attribute.
+# Note: This feature currently applies only to Markdown headings.
+# Minimum value: 0, maximum value: 99, default value: 5.
+# This tag requires that the tag MARKDOWN_SUPPORT is set to YES.
+
+TOC_INCLUDE_HEADINGS   = 5
+
+# When enabled doxygen tries to link words that correspond to documented
+# classes, or namespaces to their corresponding documentation. Such a link can
+# be prevented in individual cases by putting a % sign in front of the word or
+# globally by setting AUTOLINK_SUPPORT to NO.
+# The default value is: YES.
+
+AUTOLINK_SUPPORT       = YES
+
+# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want
+# to include (a tag file for) the STL sources as input, then you should set this
+# tag to YES in order to let doxygen match functions declarations and
+# definitions whose arguments contain STL classes (e.g. func(std::string);
+# versus func(std::string) {}). This also make the inheritance and collaboration
+# diagrams that involve STL classes more complete and accurate.
+# The default value is: NO.
+
+BUILTIN_STL_SUPPORT    = NO
+
+# If you use Microsoft's C++/CLI language, you should set this option to YES to
+# enable parsing support.
+# The default value is: NO.
+
+CPP_CLI_SUPPORT        = NO
+
+# Set the SIP_SUPPORT tag to YES if your project consists of sip (see:
+# https://www.riverbankcomputing.com/software/sip/intro) sources only. Doxygen
+# will parse them like normal C++ but will assume all classes use public instead
+# of private inheritance when no explicit protection keyword is present.
+# The default value is: NO.
+
+SIP_SUPPORT            = NO
+
+# For Microsoft's IDL there are propget and propput attributes to indicate
+# getter and setter methods for a property. Setting this option to YES will make
+# doxygen to replace the get and set methods by a property in the documentation.
+# This will only work if the methods are indeed getting or setting a simple
+# type. If this is not the case, or you want to show the methods anyway, you
+# should set this option to NO.
+# The default value is: YES.
+
+IDL_PROPERTY_SUPPORT   = YES
+
+# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC
+# tag is set to YES then doxygen will reuse the documentation of the first
+# member in the group (if any) for the other members of the group. By default
+# all members of a group must be documented explicitly.
+# The default value is: NO.
+
+DISTRIBUTE_GROUP_DOC   = NO
+
+# If one adds a struct or class to a group and this option is enabled, then also
+# any nested class or struct is added to the same group. By default this option
+# is disabled and one has to add nested compounds explicitly via \ingroup.
+# The default value is: NO.
+
+GROUP_NESTED_COMPOUNDS = NO
+
+# Set the SUBGROUPING tag to YES to allow class member groups of the same type
+# (for instance a group of public functions) to be put as a subgroup of that
+# type (e.g. under the Public Functions section). Set it to NO to prevent
+# subgrouping. Alternatively, this can be done per class using the
+# \nosubgrouping command.
+# The default value is: YES.
+
+SUBGROUPING            = YES
+
+# When the INLINE_GROUPED_CLASSES tag is set to YES, classes, structs and unions
+# are shown inside the group in which they are included (e.g. using \ingroup)
+# instead of on a separate page (for HTML and Man pages) or section (for LaTeX
+# and RTF).
+#
+# Note that this feature does not work in combination with
+# SEPARATE_MEMBER_PAGES.
+# The default value is: NO.
+
+INLINE_GROUPED_CLASSES = NO
+
+# When the INLINE_SIMPLE_STRUCTS tag is set to YES, structs, classes, and unions
+# with only public data fields or simple typedef fields will be shown inline in
+# the documentation of the scope in which they are defined (i.e. file,
+# namespace, or group documentation), provided this scope is documented. If set
+# to NO, structs, classes, and unions are shown on a separate page (for HTML and
+# Man pages) or section (for LaTeX and RTF).
+# The default value is: NO.
+
+INLINE_SIMPLE_STRUCTS  = NO
+
+# When TYPEDEF_HIDES_STRUCT tag is enabled, a typedef of a struct, union, or
+# enum is documented as struct, union, or enum with the name of the typedef. So
+# typedef struct TypeS {} TypeT, will appear in the documentation as a struct
+# with name TypeT. When disabled the typedef will appear as a member of a file,
+# namespace, or class. And the struct will be named TypeS. This can typically be
+# useful for C code in case the coding convention dictates that all compound
+# types are typedef'ed and only the typedef is referenced, never the tag name.
+# The default value is: NO.
+
+TYPEDEF_HIDES_STRUCT   = NO
+
+# The size of the symbol lookup cache can be set using LOOKUP_CACHE_SIZE. This
+# cache is used to resolve symbols given their name and scope. Since this can be
+# an expensive process and often the same symbol appears multiple times in the
+# code, doxygen keeps a cache of pre-resolved symbols. If the cache is too small
+# doxygen will become slower. If the cache is too large, memory is wasted. The
+# cache size is given by this formula: 2^(16+LOOKUP_CACHE_SIZE). The valid range
+# is 0..9, the default is 0, corresponding to a cache size of 2^16=65536
+# symbols. At the end of a run doxygen will report the cache usage and suggest
+# the optimal cache size from a speed point of view.
+# Minimum value: 0, maximum value: 9, default value: 0.
+
+LOOKUP_CACHE_SIZE      = 0
+
+# The NUM_PROC_THREADS specifies the number of threads doxygen is allowed to use
+# during processing. When set to 0 doxygen will based this on the number of
+# cores available in the system. You can set it explicitly to a value larger
+# than 0 to get more control over the balance between CPU load and processing
+# speed. At this moment only the input processing can be done using multiple
+# threads. Since this is still an experimental feature the default is set to 1,
+# which effectively disables parallel processing. Please report any issues you
+# encounter. Generating dot graphs in parallel is controlled by the
+# DOT_NUM_THREADS setting.
+# Minimum value: 0, maximum value: 32, default value: 1.
+
+NUM_PROC_THREADS       = 1
+
+#---------------------------------------------------------------------------
+# Build related configuration options
+#---------------------------------------------------------------------------
+
+# If the EXTRACT_ALL tag is set to YES, doxygen will assume all entities in
+# documentation are documented, even if no documentation was available. Private
+# class members and static file members will be hidden unless the
+# EXTRACT_PRIVATE respectively EXTRACT_STATIC tags are set to YES.
+# Note: This will also disable the warnings about undocumented members that are
+# normally produced when WARNINGS is set to YES.
+# The default value is: NO.
+
+EXTRACT_ALL            = YES
+
+# If the EXTRACT_PRIVATE tag is set to YES, all private members of a class will
+# be included in the documentation.
+# The default value is: NO.
+
+EXTRACT_PRIVATE        = YES
+
+# If the EXTRACT_PRIV_VIRTUAL tag is set to YES, documented private virtual
+# methods of a class will be included in the documentation.
+# The default value is: NO.
+
+EXTRACT_PRIV_VIRTUAL   = YES
+
+# If the EXTRACT_PACKAGE tag is set to YES, all members with package or internal
+# scope will be included in the documentation.
+# The default value is: NO.
+
+EXTRACT_PACKAGE        = YES
+
+# If the EXTRACT_STATIC tag is set to YES, all static members of a file will be
+# included in the documentation.
+# The default value is: NO.
+
+EXTRACT_STATIC         = YES
+
+# If the EXTRACT_LOCAL_CLASSES tag is set to YES, classes (and structs) defined
+# locally in source files will be included in the documentation. If set to NO,
+# only classes defined in header files are included. Does not have any effect
+# for Java sources.
+# The default value is: YES.
+
+EXTRACT_LOCAL_CLASSES  = YES
+
+# This flag is only useful for Objective-C code. If set to YES, local methods,
+# which are defined in the implementation section but not in the interface are
+# included in the documentation. If set to NO, only methods in the interface are
+# included.
+# The default value is: NO.
+
+EXTRACT_LOCAL_METHODS  = NO
+
+# If this flag is set to YES, the members of anonymous namespaces will be
+# extracted and appear in the documentation as a namespace called
+# 'anonymous_namespace{file}', where file will be replaced with the base name of
+# the file that contains the anonymous namespace. By default anonymous namespace
+# are hidden.
+# The default value is: NO.
+
+EXTRACT_ANON_NSPACES   = NO
+
+# If this flag is set to YES, the name of an unnamed parameter in a declaration
+# will be determined by the corresponding definition. By default unnamed
+# parameters remain unnamed in the output.
+# The default value is: YES.
+
+RESOLVE_UNNAMED_PARAMS = YES
+
+# If the HIDE_UNDOC_MEMBERS tag is set to YES, doxygen will hide all
+# undocumented members inside documented classes or files. If set to NO these
+# members will be included in the various overviews, but no documentation
+# section is generated. This option has no effect if EXTRACT_ALL is enabled.
+# The default value is: NO.
+
+HIDE_UNDOC_MEMBERS     = NO
+
+# If the HIDE_UNDOC_CLASSES tag is set to YES, doxygen will hide all
+# undocumented classes that are normally visible in the class hierarchy. If set
+# to NO, these classes will be included in the various overviews. This option
+# has no effect if EXTRACT_ALL is enabled.
+# The default value is: NO.
+
+HIDE_UNDOC_CLASSES     = NO
+
+# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, doxygen will hide all friend
+# declarations. If set to NO, these declarations will be included in the
+# documentation.
+# The default value is: NO.
+
+HIDE_FRIEND_COMPOUNDS  = NO
+
+# If the HIDE_IN_BODY_DOCS tag is set to YES, doxygen will hide any
+# documentation blocks found inside the body of a function. If set to NO, these
+# blocks will be appended to the function's detailed documentation block.
+# The default value is: NO.
+
+HIDE_IN_BODY_DOCS      = NO
+
+# The INTERNAL_DOCS tag determines if documentation that is typed after a
+# \internal command is included. If the tag is set to NO then the documentation
+# will be excluded. Set it to YES to include the internal documentation.
+# The default value is: NO.
+
+INTERNAL_DOCS          = NO
+
+# With the correct setting of option CASE_SENSE_NAMES doxygen will better be
+# able to match the capabilities of the underlying filesystem. In case the
+# filesystem is case sensitive (i.e. it supports files in the same directory
+# whose names only differ in casing), the option must be set to YES to properly
+# deal with such files in case they appear in the input. For filesystems that
+# are not case sensitive the option should be set to NO to properly deal with
+# output files written for symbols that only differ in casing, such as for two
+# classes, one named CLASS and the other named Class, and to also support
+# references to files without having to specify the exact matching casing. On
+# Windows (including Cygwin) and MacOS, users should typically set this option
+# to NO, whereas on Linux or other Unix flavors it should typically be set to
+# YES.
+# Possible values are: SYSTEM, NO and YES.
+# The default value is: SYSTEM.
+
+CASE_SENSE_NAMES       = NO
+
+# If the HIDE_SCOPE_NAMES tag is set to NO then doxygen will show members with
+# their full class and namespace scopes in the documentation. If set to YES, the
+# scope will be hidden.
+# The default value is: NO.
+
+HIDE_SCOPE_NAMES       = YES
+
+# If the HIDE_COMPOUND_REFERENCE tag is set to NO (default) then doxygen will
+# append additional text to a page's title, such as Class Reference. If set to
+# YES the compound reference will be hidden.
+# The default value is: NO.
+
+HIDE_COMPOUND_REFERENCE= NO
+
+# If the SHOW_HEADERFILE tag is set to YES then the documentation for a class
+# will show which file needs to be included to use the class.
+# The default value is: YES.
+
+SHOW_HEADERFILE        = YES
+
+# If the SHOW_INCLUDE_FILES tag is set to YES then doxygen will put a list of
+# the files that are included by a file in the documentation of that file.
+# The default value is: YES.
+
+SHOW_INCLUDE_FILES     = YES
+
+# If the SHOW_GROUPED_MEMB_INC tag is set to YES then Doxygen will add for each
+# grouped member an include statement to the documentation, telling the reader
+# which file to include in order to use the member.
+# The default value is: NO.
+
+SHOW_GROUPED_MEMB_INC  = NO
+
+# If the FORCE_LOCAL_INCLUDES tag is set to YES then doxygen will list include
+# files with double quotes in the documentation rather than with sharp brackets.
+# The default value is: NO.
+
+FORCE_LOCAL_INCLUDES   = NO
+
+# If the INLINE_INFO tag is set to YES then a tag [inline] is inserted in the
+# documentation for inline members.
+# The default value is: YES.
+
+INLINE_INFO            = YES
+
+# If the SORT_MEMBER_DOCS tag is set to YES then doxygen will sort the
+# (detailed) documentation of file and class members alphabetically by member
+# name. If set to NO, the members will appear in declaration order.
+# The default value is: YES.
+
+SORT_MEMBER_DOCS       = YES
+
+# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the brief
+# descriptions of file, namespace and class members alphabetically by member
+# name. If set to NO, the members will appear in declaration order. Note that
+# this will also influence the order of the classes in the class list.
+# The default value is: NO.
+
+SORT_BRIEF_DOCS        = NO
+
+# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen will sort the
+# (brief and detailed) documentation of class members so that constructors and
+# destructors are listed first. If set to NO the constructors will appear in the
+# respective orders defined by SORT_BRIEF_DOCS and SORT_MEMBER_DOCS.
+# Note: If SORT_BRIEF_DOCS is set to NO this option is ignored for sorting brief
+# member documentation.
+# Note: If SORT_MEMBER_DOCS is set to NO this option is ignored for sorting
+# detailed member documentation.
+# The default value is: NO.
+
+SORT_MEMBERS_CTORS_1ST = NO
+
+# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the hierarchy
+# of group names into alphabetical order. If set to NO the group names will
+# appear in their defined order.
+# The default value is: NO.
+
+SORT_GROUP_NAMES       = NO
+
+# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be sorted by
+# fully-qualified names, including namespaces. If set to NO, the class list will
+# be sorted only by class name, not including the namespace part.
+# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES.
+# Note: This option applies only to the class list, not to the alphabetical
+# list.
+# The default value is: NO.
+
+SORT_BY_SCOPE_NAME     = NO
+
+# If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to do proper
+# type resolution of all parameters of a function it will reject a match between
+# the prototype and the implementation of a member function even if there is
+# only one candidate or it is obvious which candidate to choose by doing a
+# simple string match. By disabling STRICT_PROTO_MATCHING doxygen will still
+# accept a match between prototype and implementation in such cases.
+# The default value is: NO.
+
+STRICT_PROTO_MATCHING  = NO
+
+# The GENERATE_TODOLIST tag can be used to enable (YES) or disable (NO) the todo
+# list. This list is created by putting \todo commands in the documentation.
+# The default value is: YES.
+
+GENERATE_TODOLIST      = YES
+
+# The GENERATE_TESTLIST tag can be used to enable (YES) or disable (NO) the test
+# list. This list is created by putting \test commands in the documentation.
+# The default value is: YES.
+
+GENERATE_TESTLIST      = YES
+
+# The GENERATE_BUGLIST tag can be used to enable (YES) or disable (NO) the bug
+# list. This list is created by putting \bug commands in the documentation.
+# The default value is: YES.
+
+GENERATE_BUGLIST       = YES
+
+# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or disable (NO)
+# the deprecated list. This list is created by putting \deprecated commands in
+# the documentation.
+# The default value is: YES.
+
+GENERATE_DEPRECATEDLIST= YES
+
+# The ENABLED_SECTIONS tag can be used to enable conditional documentation
+# sections, marked by \if  ... \endif and \cond 
+# ... \endcond blocks.
+
+ENABLED_SECTIONS       =
+
+# The MAX_INITIALIZER_LINES tag determines the maximum number of lines that the
+# initial value of a variable or macro / define can have for it to appear in the
+# documentation. If the initializer consists of more lines than specified here
+# it will be hidden. Use a value of 0 to hide initializers completely. The
+# appearance of the value of individual variables and macros / defines can be
+# controlled using \showinitializer or \hideinitializer command in the
+# documentation regardless of this setting.
+# Minimum value: 0, maximum value: 10000, default value: 30.
+
+MAX_INITIALIZER_LINES  = 30
+
+# Set the SHOW_USED_FILES tag to NO to disable the list of files generated at
+# the bottom of the documentation of classes and structs. If set to YES, the
+# list will mention the files that were used to generate the documentation.
+# The default value is: YES.
+
+SHOW_USED_FILES        = YES
+
+# Set the SHOW_FILES tag to NO to disable the generation of the Files page. This
+# will remove the Files entry from the Quick Index and from the Folder Tree View
+# (if specified).
+# The default value is: YES.
+
+SHOW_FILES             = YES
+
+# Set the SHOW_NAMESPACES tag to NO to disable the generation of the Namespaces
+# page. This will remove the Namespaces entry from the Quick Index and from the
+# Folder Tree View (if specified).
+# The default value is: YES.
+
+SHOW_NAMESPACES        = YES
+
+# The FILE_VERSION_FILTER tag can be used to specify a program or script that
+# doxygen should invoke to get the current version for each file (typically from
+# the version control system). Doxygen will invoke the program by executing (via
+# popen()) the command command input-file, where command is the value of the
+# FILE_VERSION_FILTER tag, and input-file is the name of an input file provided
+# by doxygen. Whatever the program writes to standard output is used as the file
+# version. For an example see the documentation.
+
+FILE_VERSION_FILTER    =
+
+# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed
+# by doxygen. The layout file controls the global structure of the generated
+# output files in an output format independent way. To create the layout file
+# that represents doxygen's defaults, run doxygen with the -l option. You can
+# optionally specify a file name after the option, if omitted DoxygenLayout.xml
+# will be used as the name of the layout file. See also section "Changing the
+# layout of pages" for information.
+#
+# Note that if you run doxygen from a directory containing a file called
+# DoxygenLayout.xml, doxygen will parse it automatically even if the LAYOUT_FILE
+# tag is left empty.
+
+LAYOUT_FILE            =
+
+# The CITE_BIB_FILES tag can be used to specify one or more bib files containing
+# the reference definitions. This must be a list of .bib files. The .bib
+# extension is automatically appended if omitted. This requires the bibtex tool
+# to be installed. See also https://en.wikipedia.org/wiki/BibTeX for more info.
+# For LaTeX the style of the bibliography can be controlled using
+# LATEX_BIB_STYLE. To use this feature you need bibtex and perl available in the
+# search path. See also \cite for info how to create references.
+
+CITE_BIB_FILES         =
+
+#---------------------------------------------------------------------------
+# Configuration options related to warning and progress messages
+#---------------------------------------------------------------------------
+
+# The QUIET tag can be used to turn on/off the messages that are generated to
+# standard output by doxygen. If QUIET is set to YES this implies that the
+# messages are off.
+# The default value is: NO.
+
+QUIET                  = NO
+
+# The WARNINGS tag can be used to turn on/off the warning messages that are
+# generated to standard error (stderr) by doxygen. If WARNINGS is set to YES
+# this implies that the warnings are on.
+#
+# Tip: Turn warnings on while writing the documentation.
+# The default value is: YES.
+
+WARNINGS               = YES
+
+# If the WARN_IF_UNDOCUMENTED tag is set to YES then doxygen will generate
+# warnings for undocumented members. If EXTRACT_ALL is set to YES then this flag
+# will automatically be disabled.
+# The default value is: YES.
+
+WARN_IF_UNDOCUMENTED   = YES
+
+# If the WARN_IF_DOC_ERROR tag is set to YES, doxygen will generate warnings for
+# potential errors in the documentation, such as documenting some parameters in
+# a documented function twice, or documenting parameters that don't exist or
+# using markup commands wrongly.
+# The default value is: YES.
+
+WARN_IF_DOC_ERROR      = YES
+
+# If WARN_IF_INCOMPLETE_DOC is set to YES, doxygen will warn about incomplete
+# function parameter documentation. If set to NO, doxygen will accept that some
+# parameters have no documentation without warning.
+# The default value is: YES.
+
+WARN_IF_INCOMPLETE_DOC = YES
+
+# This WARN_NO_PARAMDOC option can be enabled to get warnings for functions that
+# are documented, but have no documentation for their parameters or return
+# value. If set to NO, doxygen will only warn about wrong parameter
+# documentation, but not about the absence of documentation. If EXTRACT_ALL is
+# set to YES then this flag will automatically be disabled. See also
+# WARN_IF_INCOMPLETE_DOC
+# The default value is: NO.
+
+WARN_NO_PARAMDOC       = NO
+
+# If the WARN_AS_ERROR tag is set to YES then doxygen will immediately stop when
+# a warning is encountered. If the WARN_AS_ERROR tag is set to FAIL_ON_WARNINGS
+# then doxygen will continue running as if WARN_AS_ERROR tag is set to NO, but
+# at the end of the doxygen process doxygen will return with a non-zero status.
+# Possible values are: NO, YES and FAIL_ON_WARNINGS.
+# The default value is: NO.
+
+WARN_AS_ERROR          = NO
+
+# The WARN_FORMAT tag determines the format of the warning messages that doxygen
+# can produce. The string should contain the $file, $line, and $text tags, which
+# will be replaced by the file and line number from which the warning originated
+# and the warning text. Optionally the format may contain $version, which will
+# be replaced by the version of the file (if it could be obtained via
+# FILE_VERSION_FILTER)
+# See also: WARN_LINE_FORMAT
+# The default value is: $file:$line: $text.
+
+WARN_FORMAT            = "$file:$line: $text"
+
+# In the $text part of the WARN_FORMAT command it is possible that a reference
+# to a more specific place is given. To make it easier to jump to this place
+# (outside of doxygen) the user can define a custom "cut" / "paste" string.
+# Example:
+# WARN_LINE_FORMAT = "'vi $file +$line'"
+# See also: WARN_FORMAT
+# The default value is: at line $line of file $file.
+
+WARN_LINE_FORMAT       = "at line $line of file $file"
+
+# The WARN_LOGFILE tag can be used to specify a file to which warning and error
+# messages should be written. If left blank the output is written to standard
+# error (stderr). In case the file specified cannot be opened for writing the
+# warning and error messages are written to standard error. When as file - is
+# specified the warning and error messages are written to standard output
+# (stdout).
+
+WARN_LOGFILE           =
+
+#---------------------------------------------------------------------------
+# Configuration options related to the input files
+#---------------------------------------------------------------------------
+
+# The INPUT tag is used to specify the files and/or directories that contain
+# documented source files. You may enter file names like myfile.cpp or
+# directories like /usr/src/myproject. Separate the files or directories with
+# spaces. See also FILE_PATTERNS and EXTENSION_MAPPING
+# Note: If this tag is empty the current directory is searched.
+
+INPUT                  = include
+
+# This tag can be used to specify the character encoding of the source files
+# that doxygen parses. Internally doxygen uses the UTF-8 encoding. Doxygen uses
+# libiconv (or the iconv built into libc) for the transcoding. See the libiconv
+# documentation (see:
+# https://www.gnu.org/software/libiconv/) for the list of possible encodings.
+# See also: INPUT_FILE_ENCODING
+# The default value is: UTF-8.
+
+INPUT_ENCODING         = UTF-8
+
+# This tag can be used to specify the character encoding of the source files
+# that doxygen parses The INPUT_FILE_ENCODING tag can be used to specify
+# character encoding on a per file pattern basis. Doxygen will compare the file
+# name with each pattern and apply the encoding instead of the default
+# INPUT_ENCODING) if there is a match. The character encodings are a list of the
+# form: pattern=encoding (like *.php=ISO-8859-1). See cfg_input_encoding
+# "INPUT_ENCODING" for further information on supported encodings.
+
+INPUT_FILE_ENCODING    =
+
+# If the value of the INPUT tag contains directories, you can use the
+# FILE_PATTERNS tag to specify one or more wildcard patterns (like *.cpp and
+# *.h) to filter out the source-files in the directories.
+#
+# Note that for custom extensions or not directly supported extensions you also
+# need to set EXTENSION_MAPPING for the extension otherwise the files are not
+# read by doxygen.
+#
+# Note the list of default checked file patterns might differ from the list of
+# default file extension mappings.
+#
+# If left blank the following patterns are tested:*.c, *.cc, *.cxx, *.cpp,
+# *.c++, *.java, *.ii, *.ixx, *.ipp, *.i++, *.inl, *.idl, *.ddl, *.odl, *.h,
+# *.hh, *.hxx, *.hpp, *.h++, *.l, *.cs, *.d, *.php, *.php4, *.php5, *.phtml,
+# *.inc, *.m, *.markdown, *.md, *.mm, *.dox (to be provided as doxygen C
+# comment), *.py, *.pyw, *.f90, *.f95, *.f03, *.f08, *.f18, *.f, *.for, *.vhd,
+# *.vhdl, *.ucf, *.qsf and *.ice.
+
+FILE_PATTERNS          = *.c \
+                         *.cc \
+                         *.cxx \
+                         *.cpp \
+                         *.c++ \
+                         *.java \
+                         *.ii \
+                         *.ixx \
+                         *.ipp \
+                         *.i++ \
+                         *.inl \
+                         *.idl \
+                         *.ddl \
+                         *.odl \
+                         *.h \
+                         *.hh \
+                         *.hxx \
+                         *.hpp \
+                         *.h++ \
+                         *.cs \
+                         *.d \
+                         *.php \
+                         *.php4 \
+                         *.php5 \
+                         *.phtml \
+                         *.inc \
+                         *.m \
+                         *.markdown \
+                         *.md \
+                         *.mm \
+                         *.dox \
+                         *.py \
+                         *.pyw \
+                         *.f90 \
+                         *.f95 \
+                         *.f03 \
+                         *.f08 \
+                         *.f18 \
+                         *.f \
+                         *.for \
+                         *.vhd \
+                         *.vhdl \
+                         *.ucf \
+                         *.qsf \
+                         *.ice
+
+# The RECURSIVE tag can be used to specify whether or not subdirectories should
+# be searched for input files as well.
+# The default value is: NO.
+
+RECURSIVE              = NO
+
+# The EXCLUDE tag can be used to specify files and/or directories that should be
+# excluded from the INPUT source files. This way you can easily exclude a
+# subdirectory from a directory tree whose root is specified with the INPUT tag.
+#
+# Note that relative paths are relative to the directory from which doxygen is
+# run.
+
+EXCLUDE                =
+
+# The EXCLUDE_SYMLINKS tag can be used to select whether or not files or
+# directories that are symbolic links (a Unix file system feature) are excluded
+# from the input.
+# The default value is: NO.
+
+EXCLUDE_SYMLINKS       = NO
+
+# If the value of the INPUT tag contains directories, you can use the
+# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude
+# certain files from those directories.
+#
+# Note that the wildcards are matched against the file with absolute path, so to
+# exclude all test directories for example use the pattern */test/*
+
+EXCLUDE_PATTERNS       =
+
+# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names
+# (namespaces, classes, functions, etc.) that should be excluded from the
+# output. The symbol name can be a fully qualified name, a word, or if the
+# wildcard * is used, a substring. Examples: ANamespace, AClass,
+# ANamespace::AClass, ANamespace::*Test
+#
+# Note that the wildcards are matched against the file with absolute path, so to
+# exclude all test directories use the pattern */test/*
+
+EXCLUDE_SYMBOLS        =
+
+# The EXAMPLE_PATH tag can be used to specify one or more files or directories
+# that contain example code fragments that are included (see the \include
+# command).
+
+EXAMPLE_PATH           =
+
+# If the value of the EXAMPLE_PATH tag contains directories, you can use the
+# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp and
+# *.h) to filter out the source-files in the directories. If left blank all
+# files are included.
+
+EXAMPLE_PATTERNS       = *
+
+# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be
+# searched for input files to be used with the \include or \dontinclude commands
+# irrespective of the value of the RECURSIVE tag.
+# The default value is: NO.
+
+EXAMPLE_RECURSIVE      = NO
+
+# The IMAGE_PATH tag can be used to specify one or more files or directories
+# that contain images that are to be included in the documentation (see the
+# \image command).
+
+IMAGE_PATH             =
+
+# The INPUT_FILTER tag can be used to specify a program that doxygen should
+# invoke to filter for each input file. Doxygen will invoke the filter program
+# by executing (via popen()) the command:
+#
+#  
+#
+# where  is the value of the INPUT_FILTER tag, and  is the
+# name of an input file. Doxygen will then use the output that the filter
+# program writes to standard output. If FILTER_PATTERNS is specified, this tag
+# will be ignored.
+#
+# Note that the filter must not add or remove lines; it is applied before the
+# code is scanned, but not when the output code is generated. If lines are added
+# or removed, the anchors will not be placed correctly.
+#
+# Note that doxygen will use the data processed and written to standard output
+# for further processing, therefore nothing else, like debug statements or used
+# commands (so in case of a Windows batch file always use @echo OFF), should be
+# written to standard output.
+#
+# Note that for custom extensions or not directly supported extensions you also
+# need to set EXTENSION_MAPPING for the extension otherwise the files are not
+# properly processed by doxygen.
+
+INPUT_FILTER           =
+
+# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern
+# basis. Doxygen will compare the file name with each pattern and apply the
+# filter if there is a match. The filters are a list of the form: pattern=filter
+# (like *.cpp=my_cpp_filter). See INPUT_FILTER for further information on how
+# filters are used. If the FILTER_PATTERNS tag is empty or if none of the
+# patterns match the file name, INPUT_FILTER is applied.
+#
+# Note that for custom extensions or not directly supported extensions you also
+# need to set EXTENSION_MAPPING for the extension otherwise the files are not
+# properly processed by doxygen.
+
+FILTER_PATTERNS        =
+
+# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using
+# INPUT_FILTER) will also be used to filter the input files that are used for
+# producing the source files to browse (i.e. when SOURCE_BROWSER is set to YES).
+# The default value is: NO.
+
+FILTER_SOURCE_FILES    = NO
+
+# The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file
+# pattern. A pattern will override the setting for FILTER_PATTERN (if any) and
+# it is also possible to disable source filtering for a specific pattern using
+# *.ext= (so without naming a filter).
+# This tag requires that the tag FILTER_SOURCE_FILES is set to YES.
+
+FILTER_SOURCE_PATTERNS =
+
+# If the USE_MDFILE_AS_MAINPAGE tag refers to the name of a markdown file that
+# is part of the input, its contents will be placed on the main page
+# (index.html). This can be useful if you have a project on for instance GitHub
+# and want to reuse the introduction page also for the doxygen output.
+
+USE_MDFILE_AS_MAINPAGE =
+
+# The Fortran standard specifies that for fixed formatted Fortran code all
+# characters from position 72 are to be considered as comment. A common
+# extension is to allow longer lines before the automatic comment starts. The
+# setting FORTRAN_COMMENT_AFTER will also make it possible that longer lines can
+# be processed before the automatic comment starts.
+# Minimum value: 7, maximum value: 10000, default value: 72.
+
+FORTRAN_COMMENT_AFTER  = 72
+
+#---------------------------------------------------------------------------
+# Configuration options related to source browsing
+#---------------------------------------------------------------------------
+
+# If the SOURCE_BROWSER tag is set to YES then a list of source files will be
+# generated. Documented entities will be cross-referenced with these sources.
+#
+# Note: To get rid of all source code in the generated output, make sure that
+# also VERBATIM_HEADERS is set to NO.
+# The default value is: NO.
+
+SOURCE_BROWSER         = YES
+
+# Setting the INLINE_SOURCES tag to YES will include the body of functions,
+# classes and enums directly into the documentation.
+# The default value is: NO.
+
+INLINE_SOURCES         = NO
+
+# Setting the STRIP_CODE_COMMENTS tag to YES will instruct doxygen to hide any
+# special comment blocks from generated source code fragments. Normal C, C++ and
+# Fortran comments will always remain visible.
+# The default value is: YES.
+
+STRIP_CODE_COMMENTS    = YES
+
+# If the REFERENCED_BY_RELATION tag is set to YES then for each documented
+# entity all documented functions referencing it will be listed.
+# The default value is: NO.
+
+REFERENCED_BY_RELATION = NO
+
+# If the REFERENCES_RELATION tag is set to YES then for each documented function
+# all documented entities called/used by that function will be listed.
+# The default value is: NO.
+
+REFERENCES_RELATION    = NO
+
+# If the REFERENCES_LINK_SOURCE tag is set to YES and SOURCE_BROWSER tag is set
+# to YES then the hyperlinks from functions in REFERENCES_RELATION and
+# REFERENCED_BY_RELATION lists will link to the source code. Otherwise they will
+# link to the documentation.
+# The default value is: YES.
+
+REFERENCES_LINK_SOURCE = YES
+
+# If SOURCE_TOOLTIPS is enabled (the default) then hovering a hyperlink in the
+# source code will show a tooltip with additional information such as prototype,
+# brief description and links to the definition and documentation. Since this
+# will make the HTML file larger and loading of large files a bit slower, you
+# can opt to disable this feature.
+# The default value is: YES.
+# This tag requires that the tag SOURCE_BROWSER is set to YES.
+
+SOURCE_TOOLTIPS        = YES
+
+# If the USE_HTAGS tag is set to YES then the references to source code will
+# point to the HTML generated by the htags(1) tool instead of doxygen built-in
+# source browser. The htags tool is part of GNU's global source tagging system
+# (see https://www.gnu.org/software/global/global.html). You will need version
+# 4.8.6 or higher.
+#
+# To use it do the following:
+# - Install the latest version of global
+# - Enable SOURCE_BROWSER and USE_HTAGS in the configuration file
+# - Make sure the INPUT points to the root of the source tree
+# - Run doxygen as normal
+#
+# Doxygen will invoke htags (and that will in turn invoke gtags), so these
+# tools must be available from the command line (i.e. in the search path).
+#
+# The result: instead of the source browser generated by doxygen, the links to
+# source code will now point to the output of htags.
+# The default value is: NO.
+# This tag requires that the tag SOURCE_BROWSER is set to YES.
+
+USE_HTAGS              = NO
+
+# If the VERBATIM_HEADERS tag is set the YES then doxygen will generate a
+# verbatim copy of the header file for each class for which an include is
+# specified. Set to NO to disable this.
+# See also: Section \class.
+# The default value is: YES.
+
+VERBATIM_HEADERS       = YES
+
+# If the CLANG_ASSISTED_PARSING tag is set to YES then doxygen will use the
+# clang parser (see:
+# http://clang.llvm.org/) for more accurate parsing at the cost of reduced
+# performance. This can be particularly helpful with template rich C++ code for
+# which doxygen's built-in parser lacks the necessary type information.
+# Note: The availability of this option depends on whether or not doxygen was
+# generated with the -Duse_libclang=ON option for CMake.
+# The default value is: NO.
+
+CLANG_ASSISTED_PARSING = NO
+
+# If the CLANG_ASSISTED_PARSING tag is set to YES and the CLANG_ADD_INC_PATHS
+# tag is set to YES then doxygen will add the directory of each input to the
+# include path.
+# The default value is: YES.
+# This tag requires that the tag CLANG_ASSISTED_PARSING is set to YES.
+
+CLANG_ADD_INC_PATHS    = YES
+
+# If clang assisted parsing is enabled you can provide the compiler with command
+# line options that you would normally use when invoking the compiler. Note that
+# the include paths will already be set by doxygen for the files and directories
+# specified with INPUT and INCLUDE_PATH.
+# This tag requires that the tag CLANG_ASSISTED_PARSING is set to YES.
+
+CLANG_OPTIONS          =
+
+# If clang assisted parsing is enabled you can provide the clang parser with the
+# path to the directory containing a file called compile_commands.json. This
+# file is the compilation database (see:
+# http://clang.llvm.org/docs/HowToSetupToolingForLLVM.html) containing the
+# options used when the source files were built. This is equivalent to
+# specifying the -p option to a clang tool, such as clang-check. These options
+# will then be passed to the parser. Any options specified with CLANG_OPTIONS
+# will be added as well.
+# Note: The availability of this option depends on whether or not doxygen was
+# generated with the -Duse_libclang=ON option for CMake.
+
+CLANG_DATABASE_PATH    =
+
+#---------------------------------------------------------------------------
+# Configuration options related to the alphabetical class index
+#---------------------------------------------------------------------------
+
+# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index of all
+# compounds will be generated. Enable this if the project contains a lot of
+# classes, structs, unions or interfaces.
+# The default value is: YES.
+
+ALPHABETICAL_INDEX     = YES
+
+# In case all classes in a project start with a common prefix, all classes will
+# be put under the same header in the alphabetical index. The IGNORE_PREFIX tag
+# can be used to specify a prefix (or a list of prefixes) that should be ignored
+# while generating the index headers.
+# This tag requires that the tag ALPHABETICAL_INDEX is set to YES.
+
+IGNORE_PREFIX          =
+
+#---------------------------------------------------------------------------
+# Configuration options related to the HTML output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_HTML tag is set to YES, doxygen will generate HTML output
+# The default value is: YES.
+
+GENERATE_HTML          = YES
+
+# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. If a
+# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of
+# it.
+# The default directory is: html.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_OUTPUT            = html
+
+# The HTML_FILE_EXTENSION tag can be used to specify the file extension for each
+# generated HTML page (for example: .htm, .php, .asp).
+# The default value is: .html.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_FILE_EXTENSION    = .html
+
+# The HTML_HEADER tag can be used to specify a user-defined HTML header file for
+# each generated HTML page. If the tag is left blank doxygen will generate a
+# standard header.
+#
+# To get valid HTML the header file that includes any scripts and style sheets
+# that doxygen needs, which is dependent on the configuration options used (e.g.
+# the setting GENERATE_TREEVIEW). It is highly recommended to start with a
+# default header using
+# doxygen -w html new_header.html new_footer.html new_stylesheet.css
+# YourConfigFile
+# and then modify the file new_header.html. See also section "Doxygen usage"
+# for information on how to generate the default header that doxygen normally
+# uses.
+# Note: The header is subject to change so you typically have to regenerate the
+# default header when upgrading to a newer version of doxygen. For a description
+# of the possible markers and block names see the documentation.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_HEADER            =
+
+# The HTML_FOOTER tag can be used to specify a user-defined HTML footer for each
+# generated HTML page. If the tag is left blank doxygen will generate a standard
+# footer. See HTML_HEADER for more information on how to generate a default
+# footer and what special commands can be used inside the footer. See also
+# section "Doxygen usage" for information on how to generate the default footer
+# that doxygen normally uses.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_FOOTER            =
+
+# The HTML_STYLESHEET tag can be used to specify a user-defined cascading style
+# sheet that is used by each HTML page. It can be used to fine-tune the look of
+# the HTML output. If left blank doxygen will generate a default style sheet.
+# See also section "Doxygen usage" for information on how to generate the style
+# sheet that doxygen normally uses.
+# Note: It is recommended to use HTML_EXTRA_STYLESHEET instead of this tag, as
+# it is more robust and this tag (HTML_STYLESHEET) will in the future become
+# obsolete.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_STYLESHEET        =
+
+# The HTML_EXTRA_STYLESHEET tag can be used to specify additional user-defined
+# cascading style sheets that are included after the standard style sheets
+# created by doxygen. Using this option one can overrule certain style aspects.
+# This is preferred over using HTML_STYLESHEET since it does not replace the
+# standard style sheet and is therefore more robust against future updates.
+# Doxygen will copy the style sheet files to the output directory.
+# Note: The order of the extra style sheet files is of importance (e.g. the last
+# style sheet in the list overrules the setting of the previous ones in the
+# list). For an example see the documentation.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_EXTRA_STYLESHEET  =
+
+# The HTML_EXTRA_FILES tag can be used to specify one or more extra images or
+# other source files which should be copied to the HTML output directory. Note
+# that these files will be copied to the base HTML output directory. Use the
+# $relpath^ marker in the HTML_HEADER and/or HTML_FOOTER files to load these
+# files. In the HTML_STYLESHEET file, use the file name only. Also note that the
+# files will be copied as-is; there are no commands or markers available.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_EXTRA_FILES       =
+
+# The HTML_COLORSTYLE tag can be used to specify if the generated HTML output
+# should be rendered with a dark or light theme. Default setting AUTO_LIGHT
+# enables light output unless the user preference is dark output. Other options
+# are DARK to always use dark mode, LIGHT to always use light mode, AUTO_DARK to
+# default to dark mode unless the user prefers light mode, and TOGGLE to let the
+# user toggle between dark and light mode via a button.
+# Possible values are: LIGHT Always generate light output., DARK Always generate
+# dark output., AUTO_LIGHT Automatically set the mode according to the user
+# preference, use light mode if no preference is set (the default)., AUTO_DARK
+# Automatically set the mode according to the user preference, use dark mode if
+# no preference is set. and TOGGLE Allow to user to switch between light and
+# dark mode via a button..
+# The default value is: AUTO_LIGHT.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_COLORSTYLE        = AUTO_LIGHT
+
+# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. Doxygen
+# will adjust the colors in the style sheet and background images according to
+# this color. Hue is specified as an angle on a color-wheel, see
+# https://en.wikipedia.org/wiki/Hue for more information. For instance the value
+# 0 represents red, 60 is yellow, 120 is green, 180 is cyan, 240 is blue, 300
+# purple, and 360 is red again.
+# Minimum value: 0, maximum value: 359, default value: 220.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_COLORSTYLE_HUE    = 234
+
+# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of the colors
+# in the HTML output. For a value of 0 the output will use gray-scales only. A
+# value of 255 will produce the most vivid colors.
+# Minimum value: 0, maximum value: 255, default value: 100.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_COLORSTYLE_SAT    = 35
+
+# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to the
+# luminance component of the colors in the HTML output. Values below 100
+# gradually make the output lighter, whereas values above 100 make the output
+# darker. The value divided by 100 is the actual gamma applied, so 80 represents
+# a gamma of 0.8, The value 220 represents a gamma of 2.2, and 100 does not
+# change the gamma.
+# Minimum value: 40, maximum value: 240, default value: 80.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_COLORSTYLE_GAMMA  = 110
+
+# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML
+# page will contain the date and time when the page was generated. Setting this
+# to YES can help to show when doxygen was last run and thus if the
+# documentation is up to date.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_TIMESTAMP         = NO
+
+# If the HTML_DYNAMIC_MENUS tag is set to YES then the generated HTML
+# documentation will contain a main index with vertical navigation menus that
+# are dynamically created via JavaScript. If disabled, the navigation index will
+# consists of multiple levels of tabs that are statically embedded in every HTML
+# page. Disable this option to support browsers that do not have JavaScript,
+# like the Qt help browser.
+# The default value is: YES.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_DYNAMIC_MENUS     = YES
+
+# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML
+# documentation will contain sections that can be hidden and shown after the
+# page has loaded.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_DYNAMIC_SECTIONS  = NO
+
+# With HTML_INDEX_NUM_ENTRIES one can control the preferred number of entries
+# shown in the various tree structured indices initially; the user can expand
+# and collapse entries dynamically later on. Doxygen will expand the tree to
+# such a level that at most the specified number of entries are visible (unless
+# a fully collapsed tree already exceeds this amount). So setting the number of
+# entries 1 will produce a full collapsed tree by default. 0 is a special value
+# representing an infinite number of entries and will result in a full expanded
+# tree by default.
+# Minimum value: 0, maximum value: 9999, default value: 100.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_INDEX_NUM_ENTRIES = 100
+
+# If the GENERATE_DOCSET tag is set to YES, additional index files will be
+# generated that can be used as input for Apple's Xcode 3 integrated development
+# environment (see:
+# https://developer.apple.com/xcode/), introduced with OSX 10.5 (Leopard). To
+# create a documentation set, doxygen will generate a Makefile in the HTML
+# output directory. Running make will produce the docset in that directory and
+# running make install will install the docset in
+# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find it at
+# startup. See https://developer.apple.com/library/archive/featuredarticles/Doxy
+# genXcode/_index.html for more information.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+GENERATE_DOCSET        = NO
+
+# This tag determines the name of the docset feed. A documentation feed provides
+# an umbrella under which multiple documentation sets from a single provider
+# (such as a company or product suite) can be grouped.
+# The default value is: Doxygen generated docs.
+# This tag requires that the tag GENERATE_DOCSET is set to YES.
+
+DOCSET_FEEDNAME        = "Doxygen generated docs"
+
+# This tag determines the URL of the docset feed. A documentation feed provides
+# an umbrella under which multiple documentation sets from a single provider
+# (such as a company or product suite) can be grouped.
+# This tag requires that the tag GENERATE_DOCSET is set to YES.
+
+DOCSET_FEEDURL         =
+
+# This tag specifies a string that should uniquely identify the documentation
+# set bundle. This should be a reverse domain-name style string, e.g.
+# com.mycompany.MyDocSet. Doxygen will append .docset to the name.
+# The default value is: org.doxygen.Project.
+# This tag requires that the tag GENERATE_DOCSET is set to YES.
+
+DOCSET_BUNDLE_ID       = org.doxygen.Project
+
+# The DOCSET_PUBLISHER_ID tag specifies a string that should uniquely identify
+# the documentation publisher. This should be a reverse domain-name style
+# string, e.g. com.mycompany.MyDocSet.documentation.
+# The default value is: org.doxygen.Publisher.
+# This tag requires that the tag GENERATE_DOCSET is set to YES.
+
+DOCSET_PUBLISHER_ID    = org.doxygen.Publisher
+
+# The DOCSET_PUBLISHER_NAME tag identifies the documentation publisher.
+# The default value is: Publisher.
+# This tag requires that the tag GENERATE_DOCSET is set to YES.
+
+DOCSET_PUBLISHER_NAME  = Publisher
+
+# If the GENERATE_HTMLHELP tag is set to YES then doxygen generates three
+# additional HTML index files: index.hhp, index.hhc, and index.hhk. The
+# index.hhp is a project file that can be read by Microsoft's HTML Help Workshop
+# on Windows. In the beginning of 2021 Microsoft took the original page, with
+# a.o. the download links, offline the HTML help workshop was already many years
+# in maintenance mode). You can download the HTML help workshop from the web
+# archives at Installation executable (see:
+# http://web.archive.org/web/20160201063255/http://download.microsoft.com/downlo
+# ad/0/A/9/0A939EF6-E31C-430F-A3DF-DFAE7960D564/htmlhelp.exe).
+#
+# The HTML Help Workshop contains a compiler that can convert all HTML output
+# generated by doxygen into a single compiled HTML file (.chm). Compiled HTML
+# files are now used as the Windows 98 help format, and will replace the old
+# Windows help format (.hlp) on all Windows platforms in the future. Compressed
+# HTML files also contain an index, a table of contents, and you can search for
+# words in the documentation. The HTML workshop also contains a viewer for
+# compressed HTML files.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+GENERATE_HTMLHELP      = NO
+
+# The CHM_FILE tag can be used to specify the file name of the resulting .chm
+# file. You can add a path in front of the file if the result should not be
+# written to the html output directory.
+# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
+
+CHM_FILE               =
+
+# The HHC_LOCATION tag can be used to specify the location (absolute path
+# including file name) of the HTML help compiler (hhc.exe). If non-empty,
+# doxygen will try to run the HTML help compiler on the generated index.hhp.
+# The file has to be specified with full path.
+# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
+
+HHC_LOCATION           =
+
+# The GENERATE_CHI flag controls if a separate .chi index file is generated
+# (YES) or that it should be included in the main .chm file (NO).
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
+
+GENERATE_CHI           = NO
+
+# The CHM_INDEX_ENCODING is used to encode HtmlHelp index (hhk), content (hhc)
+# and project file content.
+# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
+
+CHM_INDEX_ENCODING     =
+
+# The BINARY_TOC flag controls whether a binary table of contents is generated
+# (YES) or a normal table of contents (NO) in the .chm file. Furthermore it
+# enables the Previous and Next buttons.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
+
+BINARY_TOC             = NO
+
+# The TOC_EXPAND flag can be set to YES to add extra items for group members to
+# the table of contents of the HTML help documentation and to the tree view.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
+
+TOC_EXPAND             = NO
+
+# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and
+# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated that
+# can be used as input for Qt's qhelpgenerator to generate a Qt Compressed Help
+# (.qch) of the generated HTML documentation.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+GENERATE_QHP           = NO
+
+# If the QHG_LOCATION tag is specified, the QCH_FILE tag can be used to specify
+# the file name of the resulting .qch file. The path specified is relative to
+# the HTML output folder.
+# This tag requires that the tag GENERATE_QHP is set to YES.
+
+QCH_FILE               =
+
+# The QHP_NAMESPACE tag specifies the namespace to use when generating Qt Help
+# Project output. For more information please see Qt Help Project / Namespace
+# (see:
+# https://doc.qt.io/archives/qt-4.8/qthelpproject.html#namespace).
+# The default value is: org.doxygen.Project.
+# This tag requires that the tag GENERATE_QHP is set to YES.
+
+QHP_NAMESPACE          = org.doxygen.Project
+
+# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating Qt
+# Help Project output. For more information please see Qt Help Project / Virtual
+# Folders (see:
+# https://doc.qt.io/archives/qt-4.8/qthelpproject.html#virtual-folders).
+# The default value is: doc.
+# This tag requires that the tag GENERATE_QHP is set to YES.
+
+QHP_VIRTUAL_FOLDER     = doc
+
+# If the QHP_CUST_FILTER_NAME tag is set, it specifies the name of a custom
+# filter to add. For more information please see Qt Help Project / Custom
+# Filters (see:
+# https://doc.qt.io/archives/qt-4.8/qthelpproject.html#custom-filters).
+# This tag requires that the tag GENERATE_QHP is set to YES.
+
+QHP_CUST_FILTER_NAME   =
+
+# The QHP_CUST_FILTER_ATTRS tag specifies the list of the attributes of the
+# custom filter to add. For more information please see Qt Help Project / Custom
+# Filters (see:
+# https://doc.qt.io/archives/qt-4.8/qthelpproject.html#custom-filters).
+# This tag requires that the tag GENERATE_QHP is set to YES.
+
+QHP_CUST_FILTER_ATTRS  =
+
+# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this
+# project's filter section matches. Qt Help Project / Filter Attributes (see:
+# https://doc.qt.io/archives/qt-4.8/qthelpproject.html#filter-attributes).
+# This tag requires that the tag GENERATE_QHP is set to YES.
+
+QHP_SECT_FILTER_ATTRS  =
+
+# The QHG_LOCATION tag can be used to specify the location (absolute path
+# including file name) of Qt's qhelpgenerator. If non-empty doxygen will try to
+# run qhelpgenerator on the generated .qhp file.
+# This tag requires that the tag GENERATE_QHP is set to YES.
+
+QHG_LOCATION           =
+
+# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files will be
+# generated, together with the HTML files, they form an Eclipse help plugin. To
+# install this plugin and make it available under the help contents menu in
+# Eclipse, the contents of the directory containing the HTML and XML files needs
+# to be copied into the plugins directory of eclipse. The name of the directory
+# within the plugins directory should be the same as the ECLIPSE_DOC_ID value.
+# After copying Eclipse needs to be restarted before the help appears.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+GENERATE_ECLIPSEHELP   = NO
+
+# A unique identifier for the Eclipse help plugin. When installing the plugin
+# the directory name containing the HTML and XML files should also have this
+# name. Each documentation set should have its own identifier.
+# The default value is: org.doxygen.Project.
+# This tag requires that the tag GENERATE_ECLIPSEHELP is set to YES.
+
+ECLIPSE_DOC_ID         = org.doxygen.Project
+
+# If you want full control over the layout of the generated HTML pages it might
+# be necessary to disable the index and replace it with your own. The
+# DISABLE_INDEX tag can be used to turn on/off the condensed index (tabs) at top
+# of each HTML page. A value of NO enables the index and the value YES disables
+# it. Since the tabs in the index contain the same information as the navigation
+# tree, you can set this option to YES if you also set GENERATE_TREEVIEW to YES.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+DISABLE_INDEX          = NO
+
+# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index
+# structure should be generated to display hierarchical information. If the tag
+# value is set to YES, a side panel will be generated containing a tree-like
+# index structure (just like the one that is generated for HTML Help). For this
+# to work a browser that supports JavaScript, DHTML, CSS and frames is required
+# (i.e. any modern browser). Windows users are probably better off using the
+# HTML help feature. Via custom style sheets (see HTML_EXTRA_STYLESHEET) one can
+# further fine tune the look of the index (see "Fine-tuning the output"). As an
+# example, the default style sheet generated by doxygen has an example that
+# shows how to put an image at the root of the tree instead of the PROJECT_NAME.
+# Since the tree basically has the same information as the tab index, you could
+# consider setting DISABLE_INDEX to YES when enabling this option.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+GENERATE_TREEVIEW      = YES
+
+# When both GENERATE_TREEVIEW and DISABLE_INDEX are set to YES, then the
+# FULL_SIDEBAR option determines if the side bar is limited to only the treeview
+# area (value NO) or if it should extend to the full height of the window (value
+# YES). Setting this to YES gives a layout similar to
+# https://docs.readthedocs.io with more room for contents, but less room for the
+# project logo, title, and description. If either GENERATE_TREEVIEW or
+# DISABLE_INDEX is set to NO, this option has no effect.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+FULL_SIDEBAR           = NO
+
+# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values that
+# doxygen will group on one line in the generated HTML documentation.
+#
+# Note that a value of 0 will completely suppress the enum values from appearing
+# in the overview section.
+# Minimum value: 0, maximum value: 20, default value: 4.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+ENUM_VALUES_PER_LINE   = 4
+
+# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be used
+# to set the initial width (in pixels) of the frame in which the tree is shown.
+# Minimum value: 0, maximum value: 1500, default value: 250.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+TREEVIEW_WIDTH         = 250
+
+# If the EXT_LINKS_IN_WINDOW option is set to YES, doxygen will open links to
+# external symbols imported via tag files in a separate window.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+EXT_LINKS_IN_WINDOW    = NO
+
+# If the OBFUSCATE_EMAILS tag is set to YES, doxygen will obfuscate email
+# addresses.
+# The default value is: YES.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+OBFUSCATE_EMAILS       = YES
+
+# If the HTML_FORMULA_FORMAT option is set to svg, doxygen will use the pdf2svg
+# tool (see https://github.com/dawbarton/pdf2svg) or inkscape (see
+# https://inkscape.org) to generate formulas as SVG images instead of PNGs for
+# the HTML output. These images will generally look nicer at scaled resolutions.
+# Possible values are: png (the default) and svg (looks nicer but requires the
+# pdf2svg or inkscape tool).
+# The default value is: png.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_FORMULA_FORMAT    = png
+
+# Use this tag to change the font size of LaTeX formulas included as images in
+# the HTML documentation. When you change the font size after a successful
+# doxygen run you need to manually remove any form_*.png images from the HTML
+# output directory to force them to be regenerated.
+# Minimum value: 8, maximum value: 50, default value: 10.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+FORMULA_FONTSIZE       = 10
+
+# The FORMULA_MACROFILE can contain LaTeX \newcommand and \renewcommand commands
+# to create new LaTeX commands to be used in formulas as building blocks. See
+# the section "Including formulas" for details.
+
+FORMULA_MACROFILE      =
+
+# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see
+# https://www.mathjax.org) which uses client side JavaScript for the rendering
+# instead of using pre-rendered bitmaps. Use this if you do not have LaTeX
+# installed or if you want to formulas look prettier in the HTML output. When
+# enabled you may also need to install MathJax separately and configure the path
+# to it using the MATHJAX_RELPATH option.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+USE_MATHJAX            = NO
+
+# With MATHJAX_VERSION it is possible to specify the MathJax version to be used.
+# Note that the different versions of MathJax have different requirements with
+# regards to the different settings, so it is possible that also other MathJax
+# settings have to be changed when switching between the different MathJax
+# versions.
+# Possible values are: MathJax_2 and MathJax_3.
+# The default value is: MathJax_2.
+# This tag requires that the tag USE_MATHJAX is set to YES.
+
+MATHJAX_VERSION        = MathJax_2
+
+# When MathJax is enabled you can set the default output format to be used for
+# the MathJax output. For more details about the output format see MathJax
+# version 2 (see:
+# http://docs.mathjax.org/en/v2.7-latest/output.html) and MathJax version 3
+# (see:
+# http://docs.mathjax.org/en/latest/web/components/output.html).
+# Possible values are: HTML-CSS (which is slower, but has the best
+# compatibility. This is the name for Mathjax version 2, for MathJax version 3
+# this will be translated into chtml), NativeMML (i.e. MathML. Only supported
+# for NathJax 2. For MathJax version 3 chtml will be used instead.), chtml (This
+# is the name for Mathjax version 3, for MathJax version 2 this will be
+# translated into HTML-CSS) and SVG.
+# The default value is: HTML-CSS.
+# This tag requires that the tag USE_MATHJAX is set to YES.
+
+MATHJAX_FORMAT         = HTML-CSS
+
+# When MathJax is enabled you need to specify the location relative to the HTML
+# output directory using the MATHJAX_RELPATH option. The destination directory
+# should contain the MathJax.js script. For instance, if the mathjax directory
+# is located at the same level as the HTML output directory, then
+# MATHJAX_RELPATH should be ../mathjax. The default value points to the MathJax
+# Content Delivery Network so you can quickly see the result without installing
+# MathJax. However, it is strongly recommended to install a local copy of
+# MathJax from https://www.mathjax.org before deployment. The default value is:
+# - in case of MathJax version 2: https://cdn.jsdelivr.net/npm/mathjax@2
+# - in case of MathJax version 3: https://cdn.jsdelivr.net/npm/mathjax@3
+# This tag requires that the tag USE_MATHJAX is set to YES.
+
+MATHJAX_RELPATH        = https://cdn.jsdelivr.net/npm/mathjax@2
+
+# The MATHJAX_EXTENSIONS tag can be used to specify one or more MathJax
+# extension names that should be enabled during MathJax rendering. For example
+# for MathJax version 2 (see
+# https://docs.mathjax.org/en/v2.7-latest/tex.html#tex-and-latex-extensions):
+# MATHJAX_EXTENSIONS = TeX/AMSmath TeX/AMSsymbols
+# For example for MathJax version 3 (see
+# http://docs.mathjax.org/en/latest/input/tex/extensions/index.html):
+# MATHJAX_EXTENSIONS = ams
+# This tag requires that the tag USE_MATHJAX is set to YES.
+
+MATHJAX_EXTENSIONS     =
+
+# The MATHJAX_CODEFILE tag can be used to specify a file with javascript pieces
+# of code that will be used on startup of the MathJax code. See the MathJax site
+# (see:
+# http://docs.mathjax.org/en/v2.7-latest/output.html) for more details. For an
+# example see the documentation.
+# This tag requires that the tag USE_MATHJAX is set to YES.
+
+MATHJAX_CODEFILE       =
+
+# When the SEARCHENGINE tag is enabled doxygen will generate a search box for
+# the HTML output. The underlying search engine uses javascript and DHTML and
+# should work on any modern browser. Note that when using HTML help
+# (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets (GENERATE_DOCSET)
+# there is already a search function so this one should typically be disabled.
+# For large projects the javascript based search engine can be slow, then
+# enabling SERVER_BASED_SEARCH may provide a better solution. It is possible to
+# search using the keyboard; to jump to the search box use  + S
+# (what the  is depends on the OS and browser, but it is typically
+# , /