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support context switch load/store FPU register.

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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1901 bbd45198-f89e-11dd-88c7-29a3b14d5316
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wuyangyong
2011-12-31 20:25:44 +00:00
parent 1097104c7f
commit aad32f8546
4 changed files with 174 additions and 84 deletions
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11
libcpu/arm/cortex-m4/context_gcc.S
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@@ -10,6 +10,7 @@
* Change Logs:
* Date Author Notes
* 2009-10-11 Bernard first version
* 2012-01-01 aozima support context switch load/store FPU register.
*/
/**
@@ -17,8 +18,8 @@
*/
/*@{*/
.cpu cortex-m3
.fpu softvfp
.cpu cortex-m4
.fpu vfpv4
.syntax unified
.thumb
.text
@@ -104,7 +105,8 @@ PendSV_Handler:
CBZ r1, swtich_to_thread /* skip register save at the first time */
MRS r1, psp /* get from thread stack pointer */
STMFD r1!, {r4 - r11} /* push r4 - r11 register */
VSTMDB r1!, {d8 - d15} /* push FPU register s16~s31 */
STMFD r1!, {r4 - r11} /* push r4 - r11 register */
LDR r0, [r0]
STR r1, [r0] /* update from thread stack pointer */
@@ -113,7 +115,8 @@ swtich_to_thread:
LDR r1, [r1]
LDR r1, [r1] /* load thread stack pointer */
LDMFD r1!, {r4 - r11} /* pop r4 - r11 register */
LDMFD r1!, {r4 - r11} /* pop r4 - r11 register */
VLDMIA r1!, {d8 - d15} /* pop FPU register s16~s31 */
MSR psp, r1 /* update stack pointer */
pendsv_exit: