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Meco Man
2023-01-08 21:16:47 -05:00
committed by Man, Jianting (Meco)
parent 9bc68d26a4
commit 592284c66c
869 changed files with 24161 additions and 23968 deletions
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28
bsp/CME_M7/CME_M7.sct
View File

@@ -2,21 +2,21 @@
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
; load region size_region
LR_IROM1 (0) (1024 * 128)
; load region size_region
LR_IROM1 (0) (1024 * 128)
{
; load address = execution address
ER_IROM1 (0) (1024 * 128)
{
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; load address = execution address
ER_IROM1 (0) (1024 * 128)
{
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; RW data
RW_IRAM1 0x20000000 (1024 * 48)
{
.ANY (+RW +ZI)
}
; RW data
RW_IRAM1 0x20000000 (1024 * 48)
{
.ANY (+RW +ZI)
}
}

2
bsp/allwinner/d1/link.lds
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/allwinner/d1s/link.lds
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

62
bsp/allwinner_tina/link.lds
View File

@@ -12,7 +12,7 @@ SECTIONS
*(.vectors)
*(.text)
*(.text.*)
KEEP(*(.fini))
KEEP(*(.fini))
/* section information for finsh shell */
. = ALIGN(4);
@@ -47,17 +47,17 @@ SECTIONS
.ctors :
{
PROVIDE(__ctors_start__ = .);
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
PROVIDE(__ctors_end__ = .);
}
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
}
/* The .ARM.exidx section is used for C++ exception handling. */
/* .ARM.exidx is sorted, so has to go in its own output section. */
@@ -75,10 +75,10 @@ SECTIONS
{
PROVIDE(__dtors_start__ = .);
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
PROVIDE(__dtors_end__ = .);
}
@@ -89,30 +89,30 @@ SECTIONS
*(.data)
*(.data.*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
/* All data end */
KEEP(*(.jcr*))
. = ALIGN(4);
/* All data end */
*(.gnu.linkonce.d*)
}

124
bsp/amebaz/image2.icf
View File

@@ -9,24 +9,24 @@ include "rom_symbol_v01_iar.icf";
/****************************************
* Memory Regions *
****************************************/
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF;
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF;
define symbol __ICFEDIT_region_ROMBSS_RAM_start__ = 0x10000000;
define symbol __ICFEDIT_region_ROMBSS_RAM_end__ = 0x10001FFF;
define symbol __ICFEDIT_region_ROMBSS_RAM_end__ = 0x10001FFF;
define symbol __ICFEDIT_region_BOOTLOADER_RAM_start__ = 0x10002000;
define symbol __ICFEDIT_region_BOOTLOADER_RAM_end__ = 0x10004FFF;
define symbol __ICFEDIT_region_BD_RAM_start__ = 0x10005000;
define symbol __ICFEDIT_region_BD_RAM_end__ = 0x1002FFFF;
define symbol __ICFEDIT_region_MSP_RAM_start__ = 0x1003E000;
define symbol __ICFEDIT_region_MSP_RAM_end__ = 0x1003EFFF;
define symbol __ICFEDIT_region_RDP_RAM_start__ = 0x1003F000;
define symbol __ICFEDIT_region_RDP_RAM_end__ = 0x1003FFEF;
define symbol __ICFEDIT_region_IMG2_TEMP_start__ = 0x10006000;
define symbol __ICFEDIT_region_IMG2_TEMP_end__ = 0x1000BFFF;
define symbol __ICFEDIT_region_XIP_BOOT_start__ = 0x08000000+0x20;
define symbol __ICFEDIT_region_XIP_BOOT_end__ = 0x08003FFF;
define symbol __ICFEDIT_region_XIP_OTA1_start__ = 0x0800B000+0x20;
define symbol __ICFEDIT_region_XIP_OTA1_end__ = 0x080FFFFF;
define symbol __ICFEDIT_region_BD_RAM_start__ = 0x10005000;
define symbol __ICFEDIT_region_BD_RAM_end__ = 0x1002FFFF;
define symbol __ICFEDIT_region_MSP_RAM_start__ = 0x1003E000;
define symbol __ICFEDIT_region_MSP_RAM_end__ = 0x1003EFFF;
define symbol __ICFEDIT_region_RDP_RAM_start__ = 0x1003F000;
define symbol __ICFEDIT_region_RDP_RAM_end__ = 0x1003FFEF;
define symbol __ICFEDIT_region_IMG2_TEMP_start__ = 0x10006000;
define symbol __ICFEDIT_region_IMG2_TEMP_end__ = 0x1000BFFF;
define symbol __ICFEDIT_region_XIP_BOOT_start__ = 0x08000000+0x20;
define symbol __ICFEDIT_region_XIP_BOOT_end__ = 0x08003FFF;
define symbol __ICFEDIT_region_XIP_OTA1_start__ = 0x0800B000+0x20;
define symbol __ICFEDIT_region_XIP_OTA1_end__ = 0x080FFFFF;
/****************************************
* Sizes *
****************************************/
@@ -86,19 +86,19 @@ place at start of ROM_BSS_region { readwrite,
keep { section .image1.entry.data* };
keep { section .image1.validate.rodata* };
define block .ram_image1.entry with fixed order{section .image1.entry.data*,
section .image1.validate.rodata*,
};
section .image1.validate.rodata*,
};
keep { section .boot.ram.text* };
keep { section .boot.rodata* };
define block .ram_image1.text with fixed order{section .boot.ram.text*,
section .boot.rodata*,
};
section .boot.rodata*,
};
keep { section .boot.ram.data* };
define block .ram_image1.data with fixed order{section .boot.ram.data*,
};
};
keep { section .boot.ram.bss* };
define block .ram_image1.bss with fixed order{section .boot.ram.bss*,
};
};
define block IMAGE1 with fixed order { block .ram_image1.entry, block .ram_image1.text, block .ram_image1.data, block .ram_image1.bss};
place at start of BOOT_RAM_region { readwrite,
block IMAGE1,
@@ -109,39 +109,39 @@ place at start of BOOT_RAM_region { readwrite,
keep { section .image2.entry.data* };
keep { section .image2.validate.rodata* };
define block .ram_image2.entry with fixed order{ section .image2.entry.data*,
section .image2.validate.rodata*,
};
section .image2.validate.rodata*,
};
define block SHT$$PREINIT_ARRAY { preinit_array };
define block SHT$$INIT_ARRAY { init_array };
define block CPP_INIT with fixed order { block SHT$$PREINIT_ARRAY,
block SHT$$INIT_ARRAY };
block SHT$$INIT_ARRAY };
define block .ram.data with fixed order{ section .data*,
section DATA,
section .iar.init_table,
section __DLIB_PERTHREAD,
block CPP_INIT,
section .mdns.data,
section .mdns.text
};
section DATA,
section .iar.init_table,
section __DLIB_PERTHREAD,
block CPP_INIT,
section .mdns.data,
section .mdns.text
};
define block .ram.text with fixed order{ section .image2.ram.text*,
};
};
define block IMAGE2 with fixed order { block .ram_image2.entry,
block .ram.data,
block .ram.text,
};
block .ram.data,
block .ram.text,
};
define block .ram_image2.bss with fixed order{ section .bss*,
section COMMON,
};
define block .ram_image2.skb.bss with fixed order{ section .bdsram.data* };
define block .ram_heap.data with fixed order{ section .bfsram.data* };
place in BD_RAM_region { readwrite,
block IMAGE2,
block .ram_image2.bss,
block .ram_image2.skb.bss,
block .ram_heap.data,
section .heap.stdlib,
block IMAGE2,
block .ram_image2.bss,
block .ram_image2.skb.bss,
block .ram_heap.data,
section .heap.stdlib,
last block HEAP,
};
};
/****************************************
* XIP BOOT Section config *
****************************************/
@@ -149,8 +149,8 @@ keep { section .flashboot.text* };
define block .xip_image1.text with fixed order{ section .flashboot.text* };
define block Bootloader with fixed order { section LOADER };
place at start of XIP_BOOT_region { block Bootloader,
readwrite,
block .xip_image1.text };
readwrite,
block .xip_image1.text };
/****************************************
* XIP OTA1 Section config *
****************************************/
@@ -158,30 +158,30 @@ keep { section FSymTab };
keep { section VSymTab };
keep { section .rti_fn* };
define block .xip_image2.text with fixed order{ section .img2_custom_signature*,
section .text*,
section .rodata*,
section .debug_trace,
section CODE,
section Veneer, // object startup.o,
section FSymTab,
section VSymTab,
section .rti_fn*,
};
section .text*,
section .rodata*,
section .debug_trace,
section CODE,
section Veneer, // object startup.o,
section FSymTab,
section VSymTab,
section .rti_fn*,
};
place at start of XIP_OTA1_region { readwrite,
block .xip_image2.text };
block .xip_image2.text };
/****************************************
* RDP Section config *
****************************************/
keep { section .rdp.ram.text* };
keep { section .rdp.ram.data* };
keep { section .rdp.ram.text* };
keep { section .rdp.ram.data* };
define block .RDP_RAM with fixed order {
section .rdp.ram.text*,
section .rdp.ram.data* };
section .rdp.ram.text*,
section .rdp.ram.data* };
place at start of RDP_RAM_region{
readwrite,
block .RDP_RAM };
define exported symbol __ram_start_table_start__= 0x10002000; // use in rom
define exported symbol __image1_validate_code__= 0x10002018; // needed by ram code
define exported symbol __rom_top_4k_start_= 0x1003F000; // needed by ram code
readwrite,
block .RDP_RAM };
define exported symbol __ram_start_table_start__= 0x10002000; // use in rom
define exported symbol __image1_validate_code__= 0x10002018; // needed by ram code
define exported symbol __rom_top_4k_start_= 0x1003F000; // needed by ram code
define exported symbol __flash_text_start__= 0x0800b020; // needed by ram code
define exported symbol boot_export_symbol = 0x10002020;

12
bsp/apm32/apm32f072vb-miniboard/board/linker_scripts/link.lds
View File

@@ -65,7 +65,7 @@ SECTIONS
/* This is used by the startup in order to initialize the .data secion */
_sidata = .;
_start_address_init_data = .;
_start_address_init_data = .;
} > ROM
__exidx_end = .;
@@ -76,7 +76,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_sdata = . ;
_start_address_data = .;
_start_address_data = .;
*(.data)
*(.data.*)
@@ -91,7 +91,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_edata = . ;
_end_address_data = .;
_end_address_data = .;
} >RAM
.stack :
@@ -101,11 +101,11 @@ SECTIONS
. = . + _system_stack_size;
. = ALIGN(4);
_estack = .;
_end_stack = .;
_end_stack = .;
} >RAM
__bss_start = .;
_start_address_bss = .;
_start_address_bss = .;
.bss :
{
. = ALIGN(4);
@@ -123,7 +123,7 @@ SECTIONS
*(.bss.init)
} > RAM
__bss_end = .;
_end_address_bss = .;
_end_address_bss = .;
_end = .;

18
bsp/avr32uc3b0/avr32elf_uc3b0256.lds
View File

@@ -1,6 +1,6 @@
/* Default linker script, for normal executables */
OUTPUT_FORMAT("elf32-avr32", "elf32-avr32",
"elf32-avr32")
"elf32-avr32")
OUTPUT_ARCH(avr32:uc)
ENTRY(_start)
SEARCH_DIR("/home/mingwbuild/mingwavr32/avr32/lib");
@@ -37,10 +37,10 @@ SECTIONS
.rela.data.rel.ro : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH
.rel.data : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } >FLASH AT>FLASH
.rela.data : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } >FLASH AT>FLASH
.rel.tdata : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH
.rela.tdata : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } >FLASH AT>FLASH
.rel.tbss : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH
.rela.tbss : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } >FLASH AT>FLASH
.rel.tdata : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH
.rela.tdata : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } >FLASH AT>FLASH
.rel.tbss : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH
.rela.tbss : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } >FLASH AT>FLASH
.rel.ctors : { *(.rel.ctors) } >FLASH AT>FLASH
.rela.ctors : { *(.rela.ctors) } >FLASH AT>FLASH
.rel.dtors : { *(.rel.dtors) } >FLASH AT>FLASH
@@ -85,15 +85,15 @@ SECTIONS
.eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH
.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH
.gcc_except_table : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH
.dalign : { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH
.dalign : { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH
PROVIDE (_data = ORIGIN(CPUSRAM));
. = ORIGIN(CPUSRAM);
/* Exception handling */
.eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) } >CPUSRAM AT>FLASH
.gcc_except_table : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >CPUSRAM AT>FLASH
/* Thread Local Storage sections */
.tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >CPUSRAM AT>FLASH
.tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >CPUSRAM
.tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >CPUSRAM AT>FLASH
.tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >CPUSRAM
/* Ensure the __preinit_array_start label is properly aligned. We
could instead move the label definition inside the section, but
the linker would then create the section even if it turns out to
@@ -145,7 +145,7 @@ SECTIONS
SORT(CONSTRUCTORS)
} >CPUSRAM AT>FLASH
.data1 : { *(.data1) } >CPUSRAM AT>FLASH
.balign : { . = ALIGN(8); _edata = .; } >CPUSRAM AT>FLASH
.balign : { . = ALIGN(8); _edata = .; } >CPUSRAM AT>FLASH
_edata = .;
PROVIDE (edata = .);
__bss_start = .;

6
bsp/essemi/es32f365x/drivers/linker_scripts/link.icf
View File

@@ -26,9 +26,9 @@ do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, last block HEAP };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, last block HEAP };
export symbol __ICFEDIT_region_RAM_start__;
export symbol __ICFEDIT_region_RAM_end__;

6
bsp/essemi/es32f369x/drivers/linker_scripts/link.icf
View File

@@ -26,9 +26,9 @@ do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, last block HEAP };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, last block HEAP };
export symbol __ICFEDIT_region_RAM_start__;
export symbol __ICFEDIT_region_RAM_end__;

12
bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/RISCV/env_Eclipse/GD32VF103x4.lds
View File

@@ -4,13 +4,13 @@ ENTRY( _start )
MEMORY
{
/* Run in FLASH */
flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 16k
ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 6k
/* Run in FLASH */
flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 16k
ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 6k
/* Run in RAM */
/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 4k
ram (wxa!ri) : ORIGIN = 0x20001000, LENGTH = 2K
/* Run in RAM */
/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 4k
ram (wxa!ri) : ORIGIN = 0x20001000, LENGTH = 2K
*/
}

12
bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/RISCV/env_Eclipse/GD32VF103x6.lds
View File

@@ -4,13 +4,13 @@ ENTRY( _start )
MEMORY
{
/* Run in FLASH */
flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 32k
ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 10k
/* Run in FLASH */
flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 32k
ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 10k
/* Run in RAM */
/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 7k
ram (wxa!ri) : ORIGIN = 0x20001C00, LENGTH = 3K
/* Run in RAM */
/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 7k
ram (wxa!ri) : ORIGIN = 0x20001C00, LENGTH = 3K
*/
}

12
bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/RISCV/env_Eclipse/GD32VF103x8.lds
View File

@@ -4,13 +4,13 @@ ENTRY( _start )
MEMORY
{
/* Run in FLASH */
flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 64k
ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 20k
/* Run in FLASH */
flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 64k
ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 20k
/* Run in RAM */
/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 15k
ram (wxa!ri) : ORIGIN = 0x20003C00, LENGTH = 5K
/* Run in RAM */
/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 15k
ram (wxa!ri) : ORIGIN = 0x20003C00, LENGTH = 5K
*/
}

12
bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103x4.lds
View File

@@ -4,13 +4,13 @@ ENTRY( _start )
MEMORY
{
/* Run in FLASH */
flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 16k
ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 6k
/* Run in FLASH */
flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 16k
ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 6k
/* Run in RAM */
/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 4k
ram (wxa!ri) : ORIGIN = 0x20001000, LENGTH = 2K
/* Run in RAM */
/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 4k
ram (wxa!ri) : ORIGIN = 0x20001000, LENGTH = 2K
*/
}

12
bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103x6.lds
View File

@@ -4,13 +4,13 @@ ENTRY( _start )
MEMORY
{
/* Run in FLASH */
flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 32k
ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 10k
/* Run in FLASH */
flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 32k
ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 10k
/* Run in RAM */
/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 7k
ram (wxa!ri) : ORIGIN = 0x20001C00, LENGTH = 3K
/* Run in RAM */
/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 7k
ram (wxa!ri) : ORIGIN = 0x20001C00, LENGTH = 3K
*/
}

12
bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103x8.lds
View File

@@ -4,13 +4,13 @@ ENTRY( _start )
MEMORY
{
/* Run in FLASH */
flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 64k
ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 20k
/* Run in FLASH */
flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 64k
ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 20k
/* Run in RAM */
/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 15k
ram (wxa!ri) : ORIGIN = 0x20003C00, LENGTH = 5K
/* Run in RAM */
/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 15k
ram (wxa!ri) : ORIGIN = 0x20003C00, LENGTH = 5K
*/
}

14
bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103xB_I2S.lds
View File

@@ -4,13 +4,13 @@ ENTRY( _start )
MEMORY
{
/* Run in FLASH */
flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 128k
ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 32K
/* Run in FLASH */
flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 128k
ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 32K
/* Run in RAM */
/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 24k
ram (wxa!ri) : ORIGIN = 0x20006000, LENGTH = 8K
/* Run in RAM */
/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 24k
ram (wxa!ri) : ORIGIN = 0x20006000, LENGTH = 8K
*/
}
@@ -38,7 +38,7 @@ SECTIONS
.PrgData ALIGN(0x08004000,4) : AT(ALIGN(0x08004000,4))
{
KEEP(*(.PrgData))
KEEP(*(.PrgData))
}
.text :

16
bsp/imxrt/imxrt1021-nxp-evk/board/linker_scripts/link.sct
View File

@@ -123,12 +123,12 @@ LR_IROM1 m_text_start m_text_size
* (NonCacheable)
}
ITCM 0x400 0xFBFF {
;drv_flexspi_hyper.o(+RO)
;fsl_flexspi.o(+RO)
* (*CLOCK_DisableClock)
* (*CLOCK_ControlGate)
* (*CLOCK_EnableClock)
* (*CLOCK_SetDiv)
* (itcm)
}
;drv_flexspi_hyper.o(+RO)
;fsl_flexspi.o(+RO)
* (*CLOCK_DisableClock)
* (*CLOCK_ControlGate)
* (*CLOCK_EnableClock)
* (*CLOCK_SetDiv)
* (itcm)
}
}

6
bsp/imxrt/imxrt1052-fire-pro/board/linker_scripts/link.lds
View File

@@ -86,9 +86,9 @@ SECTIONS
.ivt : AT(ivt_begin)
{
. = ALIGN(4);
KEEP(* (.boot_hdr.ivt)) /* ivt section */
KEEP(* (.boot_hdr.boot_data)) /* boot section */
KEEP(* (.boot_hdr.dcd_data)) /* dcd section */
KEEP(* (.boot_hdr.ivt)) /* ivt section */
KEEP(* (.boot_hdr.boot_data)) /* boot section */
KEEP(* (.boot_hdr.dcd_data)) /* dcd section */
. = ALIGN(4);
} > m_ivt

16
bsp/imxrt/imxrt1052-nxp-evk/board/linker_scripts/link.sct
View File

@@ -123,12 +123,12 @@ LR_IROM1 m_text_start m_text_size
* (NonCacheable)
}
ITCM 0x400 0xFBFF {
;drv_flexspi_hyper.o(+RO)
;fsl_flexspi.o(+RO)
* (*CLOCK_DisableClock)
* (*CLOCK_ControlGate)
* (*CLOCK_EnableClock)
* (*CLOCK_SetDiv)
* (itcm)
}
;drv_flexspi_hyper.o(+RO)
;fsl_flexspi.o(+RO)
* (*CLOCK_DisableClock)
* (*CLOCK_ControlGate)
* (*CLOCK_EnableClock)
* (*CLOCK_SetDiv)
* (itcm)
}
}

6
bsp/imxrt/libraries/templates/imxrt1050xxx/board/linker_scripts/link.lds
View File

@@ -86,9 +86,9 @@ SECTIONS
.ivt : AT(ivt_begin)
{
. = ALIGN(4);
KEEP(* (.boot_hdr.ivt)) /* ivt section */
KEEP(* (.boot_hdr.boot_data)) /* boot section */
KEEP(* (.boot_hdr.dcd_data)) /* dcd section */
KEEP(* (.boot_hdr.ivt)) /* ivt section */
KEEP(* (.boot_hdr.boot_data)) /* boot section */
KEEP(* (.boot_hdr.dcd_data)) /* dcd section */
. = ALIGN(4);
} > m_ivt

2
bsp/juicevm/link.lds
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/k210/link.lds
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/loongson/ls1bdev/ls1b_ram.lds
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/loongson/ls1cdev/ls1c_ram.lds
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/loongson/ls2kdev/ls2k_ram.lds
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

6
bsp/lpc2478/lpc2478_ram.lds
View File

@@ -18,13 +18,13 @@ SECTIONS
.rodata : { *(.rodata) *(.rodata.*) }
__rodata_end = .;
. = 0xa0100000;
. = 0xa0100000;
. = ALIGN(8);
__data_start = .;
.data :
{
*(.data)
*(.data.*)
*(.data)
*(.data.*)
}
__data_end = .;

8
bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_flash_s.icf
View File

@@ -62,8 +62,8 @@ if (isdefinedsymbol(__use_shmem__)) {
}
/* 512B - memory for veneer table (NSC - secure, non-secure callable memory) */
define symbol m_veneer_table_start = 0x1000FE00;
define symbol m_veneer_table_size = 0x200;
define symbol m_veneer_table_start = 0x1000FE00;
define symbol m_veneer_table_size = 0x200;
define symbol m_usb_sram_start = 0x50100000;
define symbol m_usb_sram_end = 0x50103FFF;
@@ -78,7 +78,7 @@ if (isdefinedsymbol(__use_shmem__)) {
define region rpmsg_sh_mem_region = mem:[from rpmsg_sh_mem_start to rpmsg_sh_mem_end];
}
define region VENEER_TABLE_region = mem:[from m_veneer_table_start to m_veneer_table_start + m_veneer_table_size - 1];
define region VENEER_TABLE_region = mem:[from m_veneer_table_start to m_veneer_table_start + m_veneer_table_size - 1];
define block CSTACK with alignment = 8, size = __size_cstack__ { };
define block HEAP with alignment = 8, size = __size_heap__ { };
@@ -113,7 +113,7 @@ place in DATA_region { block RW };
place in DATA_region { block ZI };
place in DATA_region { last block HEAP };
place in CSTACK_region { block CSTACK };
place in VENEER_TABLE_region { section Veneer$$CMSE };
place in VENEER_TABLE_region { section Veneer$$CMSE };
if (isdefinedsymbol(__use_shmem__)) {
place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section };

20
bsp/mini4020/rtthread-mini4020.sct
View File

@@ -9,16 +9,16 @@
LR_ROM1 0x30000000 0x0FFD00 ; load region size_region
{
ER_ROM1 0x30000000 0x0FFD00 ; load address = execution address
{
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_RAM1 0x30100000 0x100000 ; RW data
{
.ANY (+RW +ZI)
}
ER_ROM1 0x30000000 0x0FFD00 ; load address = execution address
{
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_RAM1 0x30100000 0x100000 ; RW data
{
.ANY (+RW +ZI)
}
}

2
bsp/mipssim/mipssim_ram.lds
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/nrf5x/nrf51822/board/linker_scripts/link.lds
View File

@@ -38,7 +38,7 @@ SECTIONS
*(.rodata*)
KEEP(*(.eh_frame*))
/* section information for finsh shell */
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))

2
bsp/nrf5x/nrf52833/board/linker_scripts/link.lds
View File

@@ -38,7 +38,7 @@ SECTIONS
*(.rodata*)
KEEP(*(.eh_frame*))
/* section information for finsh shell */
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))

2
bsp/nrf5x/nrf52840/board/linker_scripts/link.lds
View File

@@ -38,7 +38,7 @@ SECTIONS
*(.rodata*)
KEEP(*(.eh_frame*))
/* section information for finsh shell */
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))

14
bsp/nrf5x/nrf5340/board/linker_scripts/link.lds
View File

@@ -38,7 +38,7 @@ SECTIONS
*(.rodata*)
KEEP(*(.eh_frame*))
/* section information for finsh shell */
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
@@ -64,12 +64,12 @@ SECTIONS
} > FLASH
.nrf_queue :
{
PROVIDE(__start_nrf_queue = .);
KEEP(*(.nrf_balloc))
PROVIDE(__stop_nrf_queue = .);
} > FLASH
.nrf_queue :
{
PROVIDE(__start_nrf_queue = .);
KEEP(*(.nrf_balloc))
PROVIDE(__stop_nrf_queue = .);
} > FLASH
.ARM.extab :
{

2
bsp/phytium/aarch64/link.lds
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/qemu-virt64-riscv/link.lds
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/raspberry-pi/raspi2/link.lds
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/raspberry-pi/raspi3-32/link.lds
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/raspberry-pi/raspi3-64/link.lds
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/raspberry-pi/raspi4-32/link.lds
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/raspberry-pi/raspi4-64/link.lds
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/rockchip/rk3568/link.lds
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

12
bsp/rx/lnkr5f562n8.icf
View File

@@ -34,17 +34,17 @@ place at address mem:0xFFFFFF80 { ro section .nmivec };
ro section .data24* };
"RAM24":place in RAM_region24 { rw section .data24* };
"ROM32":place in ROM_region32 { ro,
ro section FSymTab,
ro section VSymTab,
ro section .rti_fn*,
};
ro section FSymTab,
ro section VSymTab,
ro section .rti_fn*,
};
"RAM32":place in RAM_region32 { rw,
ro section D,
ro section D_1,
ro section D_2,
block STACKS,
block HEAP,
};
block HEAP,
};
"DATAFLASH":place in DATA_FLASH_region
{ ro section .dataflash* };

2
bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_execute_in_place.sct
View File

@@ -30,7 +30,7 @@ FLASH_LOAD 0x00000000 0x40000
; All R only code/data is located in ENVM
ER_RO 0x00000000 0x40000
{
*.o (RESET, +First)
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}

6
bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_relocate_to_external_ram.sct
View File

@@ -36,9 +36,9 @@ FLASH_LOAD 0x60000000 0x40000
system_m2sxxx.o
sys_config.o
low_level_init.o
sys_config_SERDESIF_?.o
mscc_post_hw_cfg_init.o
ecc_error_handler.o
sys_config_SERDESIF_?.o
mscc_post_hw_cfg_init.o
ecc_error_handler.o
}
; MDDR_RAM 0xA0000000 0x4000000
; -MDDR is mapped to address space from 0 on startup

16
bsp/stm32/stm32l4r5-st-nucleo/board/linker_scripts/link.icf
View File

@@ -4,14 +4,14 @@
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x08200000;
define symbol __ICFEDIT_region_RAM1_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM1_end__ = 0x20030000;
define symbol __ICFEDIT_region_RAM2_start__ = 0x20040000;
define symbol __ICFEDIT_region_RAM2_end__ = 0x200A0000;
define symbol __ICFEDIT_region_RAM3_start__ = 0x10000000;
define symbol __ICFEDIT_region_RAM3_end__ = 0x10010000;
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x08200000;
define symbol __ICFEDIT_region_RAM1_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM1_end__ = 0x20030000;
define symbol __ICFEDIT_region_RAM2_start__ = 0x20040000;
define symbol __ICFEDIT_region_RAM2_end__ = 0x200A0000;
define symbol __ICFEDIT_region_RAM3_start__ = 0x10000000;
define symbol __ICFEDIT_region_RAM3_end__ = 0x10010000;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x0800;

18
bsp/stm32/stm32l4r5-st-nucleo/board/linker_scripts/link.sct
View File

@@ -2,16 +2,16 @@
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x08000000 0x00200000 { ; load region size_region
ER_IROM1 0x08000000 0x00200000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
LR_IROM1 0x08000000 0x00200000 { ; load region size_region
ER_IROM1 0x08000000 0x00200000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 0x20000000 0x00030000 { ; RW data
.ANY (+RW +ZI)
}
RW_IRAM1 0x20000000 0x00030000 { ; RW data
.ANY (+RW +ZI)
}

18
bsp/stm32/stm32l4r9-st-eval/board/linker_scripts/link.sct
View File

@@ -2,16 +2,16 @@
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x08000000 0x00200000 { ; load region size_region
ER_IROM1 0x08000000 0x00200000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
LR_IROM1 0x08000000 0x00200000 { ; load region size_region
ER_IROM1 0x08000000 0x00200000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 0x20000000 0x00040000 { ; RW data
.ANY (+RW +ZI)
}
RW_IRAM1 0x20000000 0x00040000 { ; RW data
.ANY (+RW +ZI)
}

2
bsp/stm32/stm32l4r9-st-sensortile-box/board/linker_scripts/link.icf
View File

@@ -24,7 +24,7 @@ define region IROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __IC
define region IRAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
| mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]
| mem:[from IRAM3_region_start to IRAM3_region_end ];
| mem:[from IRAM3_region_start to IRAM3_region_end ];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };

18
bsp/stm32/stm32l4r9-st-sensortile-box/board/linker_scripts/link.sct
View File

@@ -2,16 +2,16 @@
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x08000000 0x00200000 { ; load region size_region
ER_IROM1 0x08000000 0x00200000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
LR_IROM1 0x08000000 0x00200000 { ; load region size_region
ER_IROM1 0x08000000 0x00200000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 0x20000000 0x000A0000 { ; RW data
.ANY (+RW +ZI)
}
RW_IRAM1 0x20000000 0x000A0000 { ; RW data
.ANY (+RW +ZI)
}

6
bsp/tae32f5300/Libraries/CMSIS/Device/Tai_action/TAE32F53xx/Source/ARM/tae32f53xx_ac5_sram.sct
View File

@@ -80,16 +80,16 @@ LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
.ANY (+XO)
}
RW_RAMA __RW_BASE __RW_SIZE { ; RWA data
RW_RAMA __RW_BASE __RW_SIZE { ; RWA data
*.o (SECTION_RAMA)
.ANY (+RW +ZI)
}
RW_RAMB __RAMB_BASE __RAMB_SIZE { ; RWB region
RW_RAMB __RAMB_BASE __RAMB_SIZE { ; RWB region
*.o (SECTION_RAMB)
}
RW_RAMC __RAMC_BASE __RAMC_SIZE { ; RWC region
RW_RAMC __RAMC_BASE __RAMC_SIZE { ; RWC region
*.o (SECTION_RAMC)
}

2
bsp/tae32f5300/board/linker_scripts/link.icf
View File

@@ -51,7 +51,7 @@ define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to
| mem:[from __ICFEDIT_region_IRAM3_start__ to __ICFEDIT_region_IRAM3_end__]
| mem:[from __ICFEDIT_region_IRAM4_start__ to __ICFEDIT_region_IRAM4_end__]
| mem:[from __ICFEDIT_region_IRAM5_start__ to __ICFEDIT_region_IRAM5_end__]
| mem:[from __ICFEDIT_region_IRAM6_start__ to __ICFEDIT_region_IRAM6_end__];
| mem:[from __ICFEDIT_region_IRAM6_start__ to __ICFEDIT_region_IRAM6_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };

195
bsp/wch/risc-v/ch32v103r-evt/board/linker_scripts/link.lds
View File

@@ -1 +1,194 @@
ENTRY( _start )
ENTRY( _start )
__stack_size = 2048;
PROVIDE( _stack_size = __stack_size );
MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K
}
SECTIONS
{
.init :
{
_sinit = .;
. = ALIGN(4);
KEEP(*(SORT_NONE(.init)))
. = ALIGN(4);
_einit = .;
} >FLASH AT>FLASH
.vector :
{
*(.vector);
. = ALIGN(64);
} >FLASH AT>FLASH
.text :
{
. = ALIGN(4);
*(.text)
*(.text.*)
*(.rodata)
*(.rodata*)
*(.glue_7)
*(.glue_7t)
*(.gnu.linkonce.t.*)
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
/* section information for initial. */
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(4);
/* section information for modules */
. = ALIGN(4);
__rtmsymtab_start = .;
KEEP(*(RTMSymTab))
__rtmsymtab_end = .;
. = ALIGN(4);
} >FLASH AT>FLASH
.fini :
{
KEEP(*(SORT_NONE(.fini)))
. = ALIGN(4);
} >FLASH AT>FLASH
PROVIDE( _etext = . );
PROVIDE( _eitcm = . );
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >FLASH AT>FLASH
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
PROVIDE_HIDDEN (__init_array_end = .);
} >FLASH AT>FLASH
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
PROVIDE_HIDDEN (__fini_array_end = .);
} >FLASH AT>FLASH
.ctors :
{
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from
the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
} >FLASH AT>FLASH
.dtors :
{
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
} >FLASH AT>FLASH
.dalign :
{
. = ALIGN(4);
PROVIDE(_data_vma = .);
} >RAM AT>FLASH
.dlalign :
{
. = ALIGN(4);
PROVIDE(_data_lma = .);
} >FLASH AT>FLASH
.data :
{
*(.gnu.linkonce.r.*)
*(.data .data.*)
*(.gnu.linkonce.d.*)
. = ALIGN(8);
PROVIDE( __global_pointer$ = . + 0x800 );
*(.sdata .sdata.*)
*(.sdata2.*)
*(.gnu.linkonce.s.*)
. = ALIGN(8);
*(.srodata.cst16)
*(.srodata.cst8)
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata .srodata.*)
. = ALIGN(4);
PROVIDE( _edata = .);
} >RAM AT>FLASH
.bss :
{
. = ALIGN(4);
PROVIDE( _sbss = .);
*(.sbss*)
*(.gnu.linkonce.sb.*)
*(.bss*)
*(.gnu.linkonce.b.*)
*(COMMON*)
. = ALIGN(4);
PROVIDE( _ebss = .);
} >RAM AT>FLASH
PROVIDE( _end = _ebss);
PROVIDE( end = . );
.stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size :
{
PROVIDE( _heap_end = . );
. = ALIGN(4);
PROVIDE(_susrstack = . );
. = . + __stack_size;
PROVIDE( _eusrstack = .);
} >RAM
}

244
bsp/wch/risc-v/ch32v208w-r0/board/linker_scripts/link.lds
View File

@@ -7,41 +7,41 @@ PROVIDE( _stack_size = __stack_size );
MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K
}
SECTIONS
{
.init :
{
_sinit = .;
. = ALIGN(4);
KEEP(*(SORT_NONE(.init)))
. = ALIGN(4);
_einit = .;
} >FLASH AT>FLASH
.init :
{
_sinit = .;
. = ALIGN(4);
KEEP(*(SORT_NONE(.init)))
. = ALIGN(4);
_einit = .;
} >FLASH AT>FLASH
.vector :
{
*(.vector);
. = ALIGN(64);
. = ALIGN(64);
} >FLASH AT>FLASH
.text :
{
. = ALIGN(4);
*(.text)
*(.text.*)
*(.rodata)
*(.rodata*)
*(.glue_7)
*(.glue_7t)
*(.gnu.linkonce.t.*)
.text :
{
. = ALIGN(4);
*(.text)
*(.text.*)
*(.rodata)
*(.rodata*)
*(.glue_7)
*(.glue_7t)
*(.gnu.linkonce.t.*)
/* section information for finsh shell */
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
@@ -64,120 +64,120 @@ SECTIONS
__rtmsymtab_start = .;
KEEP(*(RTMSymTab))
__rtmsymtab_end = .;
. = ALIGN(4);
. = ALIGN(4);
} >FLASH AT>FLASH
} >FLASH AT>FLASH
.fini :
{
KEEP(*(SORT_NONE(.fini)))
. = ALIGN(4);
} >FLASH AT>FLASH
.fini :
{
KEEP(*(SORT_NONE(.fini)))
. = ALIGN(4);
} >FLASH AT>FLASH
PROVIDE( _etext = . );
PROVIDE( _eitcm = . );
PROVIDE( _etext = . );
PROVIDE( _eitcm = . );
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >FLASH AT>FLASH
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >FLASH AT>FLASH
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
PROVIDE_HIDDEN (__init_array_end = .);
} >FLASH AT>FLASH
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
PROVIDE_HIDDEN (__init_array_end = .);
} >FLASH AT>FLASH
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
PROVIDE_HIDDEN (__fini_array_end = .);
} >FLASH AT>FLASH
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
PROVIDE_HIDDEN (__fini_array_end = .);
} >FLASH AT>FLASH
.ctors :
{
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from
the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
} >FLASH AT>FLASH
.ctors :
{
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from
the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
} >FLASH AT>FLASH
.dtors :
{
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
} >FLASH AT>FLASH
.dtors :
{
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
} >FLASH AT>FLASH
.dalign :
{
. = ALIGN(4);
PROVIDE(_data_vma = .);
} >RAM AT>FLASH
.dalign :
{
. = ALIGN(4);
PROVIDE(_data_vma = .);
} >RAM AT>FLASH
.dlalign :
{
. = ALIGN(4);
PROVIDE(_data_lma = .);
} >FLASH AT>FLASH
.dlalign :
{
. = ALIGN(4);
PROVIDE(_data_lma = .);
} >FLASH AT>FLASH
.data :
{
*(.gnu.linkonce.r.*)
*(.data .data.*)
*(.gnu.linkonce.d.*)
. = ALIGN(8);
PROVIDE( __global_pointer$ = . + 0x800 );
*(.sdata .sdata.*)
*(.sdata2.*)
*(.gnu.linkonce.s.*)
. = ALIGN(8);
*(.srodata.cst16)
*(.srodata.cst8)
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata .srodata.*)
. = ALIGN(4);
PROVIDE( _edata = .);
} >RAM AT>FLASH
.data :
{
*(.gnu.linkonce.r.*)
*(.data .data.*)
*(.gnu.linkonce.d.*)
. = ALIGN(8);
PROVIDE( __global_pointer$ = . + 0x800 );
*(.sdata .sdata.*)
*(.sdata2.*)
*(.gnu.linkonce.s.*)
. = ALIGN(8);
*(.srodata.cst16)
*(.srodata.cst8)
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata .srodata.*)
. = ALIGN(4);
PROVIDE( _edata = .);
} >RAM AT>FLASH
.bss :
{
. = ALIGN(4);
PROVIDE( _sbss = .);
*(.sbss*)
.bss :
{
. = ALIGN(4);
PROVIDE( _sbss = .);
*(.sbss*)
*(.gnu.linkonce.sb.*)
*(.bss*)
*(.gnu.linkonce.b.*)
*(COMMON*)
. = ALIGN(4);
PROVIDE( _ebss = .);
} >RAM AT>FLASH
*(.bss*)
*(.gnu.linkonce.b.*)
*(COMMON*)
. = ALIGN(4);
PROVIDE( _ebss = .);
} >RAM AT>FLASH
PROVIDE( _end = _ebss);
PROVIDE( end = . );
PROVIDE( _end = _ebss);
PROVIDE( end = . );
.stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size :
{

60
bsp/wh44b0/wh44b0_ram.lds
View File

@@ -3,41 +3,41 @@ OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
. = 0x0c000000;
. = 0x0c000000;
. = ALIGN(4);
.text : {
*(.init)
*(.text)
}
. = ALIGN(4);
.text : {
*(.init)
*(.text)
}
. = ALIGN(4);
.rodata : { *(.rodata) }
. = ALIGN(4);
.rodata : { *(.rodata) }
. = ALIGN(4);
.data : { *(.data) }
. = ALIGN(4);
.data : { *(.data) }
. = ALIGN(4);
.nobss : { *(.nobss) }
. = ALIGN(4);
.nobss : { *(.nobss) }
. = ALIGN(4);
__bss_start = .;
.bss : { *(.bss) }
__bss_end = .;
. = ALIGN(4);
__bss_start = .;
.bss : { *(.bss) }
__bss_end = .;
/* stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_info 0 : { *(.debug_info) }
.debug_line 0 : { *(.debug_line) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
/* stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_info 0 : { *(.debug_info) }
.debug_line 0 : { *(.debug_line) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
_end = .;
_end = .;
}

60
bsp/wh44b0/wh44b0_rom.lds
View File

@@ -3,41 +3,41 @@ OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
. = 0x0c000000;
. = 0x0c000000;
. = ALIGN(4);
.text : {
*(.init)
*(.text)
}
. = ALIGN(4);
.text : {
*(.init)
*(.text)
}
. = ALIGN(4);
.rodata : { *(.rodata) }
. = ALIGN(4);
.rodata : { *(.rodata) }
. = ALIGN(4);
.data : { *(.data) }
. = ALIGN(4);
.data : { *(.data) }
. = ALIGN(4);
.nobss : { *(.nobss) }
. = ALIGN(4);
.nobss : { *(.nobss) }
. = ALIGN(4);
__bss_start = .;
.bss : { *(.bss) }
__bss_end = .;
. = ALIGN(4);
__bss_start = .;
.bss : { *(.bss) }
__bss_end = .;
/* stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_info 0 : { *(.debug_info) }
.debug_line 0 : { *(.debug_line) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
/* stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_info 0 : { *(.debug_info) }
.debug_line 0 : { *(.debug_line) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
_end = .;
_end = .;
}

178
bsp/yichip/yc3121-pos/drivers/linker_scripts/link.lds
View File

@@ -45,117 +45,117 @@ ENTRY(Reset_Handler)
SECTIONS
{
.text :
{
*flash_start*.o
*(.text*)
.text :
{
*flash_start*.o
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
. = ALIGN(4);
__exidx_start = .;
. = ALIGN(4);
__exidx_start = .;
__etext = .;
__etext = .;
.data : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data*)
.data : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
/* All data end */
__data_end__ = .;
KEEP(*(.jcr*))
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > RAM
} > RAM
.bss :
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > RAM
.bss :
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > RAM
.heap (COPY):
{
__end__ = .;
PROVIDE(end = .);
*(.heap*)
__HeapLimit = .;
} > RAM
.heap (COPY):
{
__end__ = .;
PROVIDE(end = .);
*(.heap*)
__HeapLimit = .;
} > RAM
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (COPY):
{
*(.stack*)
} > RAM
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (COPY):
{
*(.stack*)
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}

24
bsp/yichip/yc3121-pos/drivers/linker_scripts/link.sct
View File

@@ -11,22 +11,22 @@ LR_IROM1 0x00000000 0x0007fff { ; load region size_region
}
LR_IROM3 0x1000200 0x200{
ER_IROM3 0x1000200 {
flash_start.o (|.flash_start|,+RO)
}
ER_IROM3 0x1000200 {
flash_start.o (|.flash_start|,+RO)
}
ER_IROM3_1 0x1000340 {
startup.o (|.INIT_STACK_HEAP|,+RO)
}
startup.o (|.INIT_STACK_HEAP|,+RO)
}
}
LR_IROM4 0x1000400 0x1000000{
ER_IROM4 0x1000400 {
*(InRoot$$Sections)
.ANY (+RO)
}
ER_IROM4 0x1000400 {
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 0x00020000 0x010000 { ; RW data
.ANY (+RW +ZI)
}
RW_IRAM1 0x00020000 0x010000 { ; RW data
.ANY (+RW +ZI)
}
}