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Meco Man
2023-01-08 21:16:47 -05:00
committed by Man, Jianting (Meco)
parent 9bc68d26a4
commit 592284c66c
869 changed files with 24161 additions and 23968 deletions
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44
bsp/CME_M7/CME_M7.sct
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@@ -1,22 +1,22 @@
; ************************************************************* ; *************************************************************
; *** Scatter-Loading Description File generated by uVision *** ; *** Scatter-Loading Description File generated by uVision ***
; ************************************************************* ; *************************************************************
; load region size_region ; load region size_region
LR_IROM1 (0) (1024 * 128) LR_IROM1 (0) (1024 * 128)
{ {
; load address = execution address ; load address = execution address
ER_IROM1 (0) (1024 * 128) ER_IROM1 (0) (1024 * 128)
{ {
*.o (RESET, +First) *.o (RESET, +First)
*(InRoot$$Sections) *(InRoot$$Sections)
.ANY (+RO) .ANY (+RO)
} }
; RW data ; RW data
RW_IRAM1 0x20000000 (1024 * 48) RW_IRAM1 0x20000000 (1024 * 48)
{ {
.ANY (+RW +ZI) .ANY (+RW +ZI)
} }
} }

544
bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct
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@@ -1,272 +1,272 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cy8c6xxa_cm0plus.sct ;* \file cy8c6xxa_cm0plus.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM0+ core. ; The following defines control RAM and flash memory allocation for the CM0+ core.
; You can change the memory allocation by editing the RAM and Flash defines. ; You can change the memory allocation by editing the RAM and Flash defines.
; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. ; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior. ; Using this memory region for other purposes will lead to unexpected behavior.
; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', ; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. ; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
; RAM ; RAM
#define RAM_START 0x08000000 #define RAM_START 0x08000000
#define RAM_SIZE 0x00002000 #define RAM_SIZE 0x00002000
; Flash ; Flash
#define FLASH_START 0x10000000 #define FLASH_START 0x10000000
#define FLASH_SIZE 0x00002000 #define FLASH_SIZE 0x00002000
; The size of the stack section at the end of CM0+ SRAM ; The size of the stack section at the end of CM0+ SRAM
#define STACK_SIZE 0x00001000 #define STACK_SIZE 0x00001000
; The following defines describe a 32K flash region used for EEPROM emulation. ; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash. ; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores. ; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation. ; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000 #define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000 #define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data ; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800 #define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800 #define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00 #define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200 #define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key ; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00 #define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 #define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00 #define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200 #define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00 #define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200 #define SFLASH_RTOC_2_SIZE 0x00000200
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; eFuse ; eFuse
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Public RAM ; Public RAM
; This is an unprotected public RAM region, with the placed .cy_sharedmem section. ; This is an unprotected public RAM region, with the placed .cy_sharedmem section.
; This region is used to place objects that require full access from both cores. ; This region is used to place objects that require full access from both cores.
; Uncomment the following lines, define the region size and uncomment placement of ; Uncomment the following lines, define the region size and uncomment placement of
; .cy_sharedmem section below. ; .cy_sharedmem section below.
; #define PUBLIC_RAM_SIZE %REGION_SIZE% ; #define PUBLIC_RAM_SIZE %REGION_SIZE%
; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE) ; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
; Cortex-M0+ application flash area ; Cortex-M0+ application flash area
LR_IROM1 FLASH_START FLASH_SIZE LR_IROM1 FLASH_START FLASH_SIZE
{ {
.cy_app_header +0 .cy_app_header +0
{ {
* (.cy_app_header) * (.cy_app_header)
} }
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address. ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address.
;RW_IRAM2 PUBLIC_RAM_START UNINIT ;RW_IRAM2 PUBLIC_RAM_START UNINIT
;{ ;{
; * (.cy_sharedmem) ; * (.cy_sharedmem)
;} ;}
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
{ {
} }
} }
; Emulated EEPROM Flash area ; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{ {
.cy_em_eeprom +0 .cy_em_eeprom +0
{ {
* (.cy_em_eeprom) * (.cy_em_eeprom)
} }
} }
; Supervisory flash: User data ; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{ {
.cy_sflash_user_data +0 .cy_sflash_user_data +0
{ {
* (.cy_sflash_user_data) * (.cy_sflash_user_data)
} }
} }
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{ {
.cy_sflash_nar +0 .cy_sflash_nar +0
{ {
* (.cy_sflash_nar) * (.cy_sflash_nar)
} }
} }
; Supervisory flash: Public Key ; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{ {
.cy_sflash_public_key +0 .cy_sflash_public_key +0
{ {
* (.cy_sflash_public_key) * (.cy_sflash_public_key)
} }
} }
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{ {
.cy_toc_part2 +0 .cy_toc_part2 +0
{ {
* (.cy_toc_part2) * (.cy_toc_part2)
} }
} }
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{ {
.cy_rtoc_part2 +0 .cy_rtoc_part2 +0
{ {
* (.cy_rtoc_part2) * (.cy_rtoc_part2)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
; eFuse ; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE LR_EFUSE EFUSE_START EFUSE_SIZE
{ {
.cy_efuse +0 .cy_efuse +0
{ {
* (.cy_efuse) * (.cy_efuse)
} }
} }
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. ; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000 CYMETA 0x90500000
{ {
.cymeta +0 { * (.cymeta) } .cymeta +0 { * (.cymeta) }
} }
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
#define __cy_memory_0_start 0x10000000 #define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x00200000 #define __cy_memory_0_length 0x00200000
#define __cy_memory_0_row_size 0x200 #define __cy_memory_0_row_size 0x200
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
#define __cy_memory_1_start 0x14000000 #define __cy_memory_1_start 0x14000000
#define __cy_memory_1_length 0x8000 #define __cy_memory_1_length 0x8000
#define __cy_memory_1_row_size 0x200 #define __cy_memory_1_row_size 0x200
/* Supervisory Flash */ /* Supervisory Flash */
#define __cy_memory_2_start 0x16000000 #define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000 #define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200 #define __cy_memory_2_row_size 0x200
/* XIP */ /* XIP */
#define __cy_memory_3_start 0x18000000 #define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000 #define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200 #define __cy_memory_3_row_size 0x200
/* eFuse */ /* eFuse */
#define __cy_memory_4_start 0x90700000 #define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000 #define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1 #define __cy_memory_4_row_size 1
/* [] END OF FILE */ /* [] END OF FILE */

506
bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf
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@@ -1,253 +1,253 @@
/******************************************************************************* /*******************************************************************************
* \file cy8c6xxa_cm0plus.icf * \file cy8c6xxa_cm0plus.icf
* \version 2.91 * \version 2.91
* *
* Linker file for the IAR compiler. * Linker file for the IAR compiler.
* *
* The main purpose of the linker script is to describe how the sections in the * The main purpose of the linker script is to describe how the sections in the
* input files should be mapped into the output file, and to control the memory * input files should be mapped into the output file, and to control the memory
* layout of the output file. * layout of the output file.
* *
* \note The entry point is fixed and starts at 0x10000000. The valid application * \note The entry point is fixed and starts at 0x10000000. The valid application
* image should be placed there. * image should be placed there.
* *
* \note The linker files included with the PDL template projects must be generic * \note The linker files included with the PDL template projects must be generic
* and handle all common use cases. Your project may not use every section * and handle all common use cases. Your project may not use every section
* defined in the linker files. In that case you may see warnings during the * defined in the linker files. In that case you may see warnings during the
* build process. In your project, you can simply comment out or remove the * build process. In your project, you can simply comment out or remove the
* relevant code in the linker file. * relevant code in the linker file.
* *
******************************************************************************** ********************************************************************************
* \copyright * \copyright
* Copyright 2016-2021 Cypress Semiconductor Corporation * Copyright 2016-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Licensed under the Apache License, Version 2.0 (the "License"); * Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License. * you may not use this file except in compliance with the License.
* You may obtain a copy of the License at * You may obtain a copy of the License at
* *
* http://www.apache.org/licenses/LICENSE-2.0 * http://www.apache.org/licenses/LICENSE-2.0
* *
* Unless required by applicable law or agreed to in writing, software * Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, * distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and * See the License for the specific language governing permissions and
* limitations under the License. * limitations under the License.
*******************************************************************************/ *******************************************************************************/
/*###ICF### Section handled by ICF editor, don't touch! ****/ /*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/ /*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
/*-Specials-*/ /*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000; define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Sizes-*/ /*-Sizes-*/
if (!isdefinedsymbol(__STACK_SIZE)) { if (!isdefinedsymbol(__STACK_SIZE)) {
define symbol __ICFEDIT_size_cstack__ = 0x1000; define symbol __ICFEDIT_size_cstack__ = 0x1000;
} else { } else {
define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
} }
define symbol __ICFEDIT_size_proc_stack__ = 0x0; define symbol __ICFEDIT_size_proc_stack__ = 0x0;
/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ /* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
if (!isdefinedsymbol(__HEAP_SIZE)) { if (!isdefinedsymbol(__HEAP_SIZE)) {
define symbol __ICFEDIT_size_heap__ = 0x0400; define symbol __ICFEDIT_size_heap__ = 0x0400;
} else { } else {
define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
} }
/* The symbols below define the location and size of blocks of memory in the target. /* The symbols below define the location and size of blocks of memory in the target.
* Use these symbols to specify the memory regions available for allocation. * Use these symbols to specify the memory regions available for allocation.
*/ */
/* The following symbols control RAM and flash memory allocation for the CM0+ core. /* The following symbols control RAM and flash memory allocation for the CM0+ core.
* You can change the memory allocation by editing RAM and Flash symbols. * You can change the memory allocation by editing RAM and Flash symbols.
* Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
* Using this memory region for other purposes will lead to unexpected behavior. * Using this memory region for other purposes will lead to unexpected behavior.
* Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf', * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf',
* where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.icf'. * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.icf'.
*/ */
/* RAM */ /* RAM */
define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000;
define symbol __ICFEDIT_region_IRAM1_end__ = 0x08001FFF; define symbol __ICFEDIT_region_IRAM1_end__ = 0x08001FFF;
/* Flash */ /* Flash */
define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
define symbol __ICFEDIT_region_IROM1_end__ = 0x10001FFF; define symbol __ICFEDIT_region_IROM1_end__ = 0x10001FFF;
/* The following symbols define a 32K flash region used for EEPROM emulation. /* The following symbols define a 32K flash region used for EEPROM emulation.
* This region can also be used as the general purpose flash. * This region can also be used as the general purpose flash.
* You can assign sections to this memory region for only one of the cores. * You can assign sections to this memory region for only one of the cores.
* Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
* Therefore, repurposing this memory region will prevent such middleware from operation. * Therefore, repurposing this memory region will prevent such middleware from operation.
*/ */
define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF;
/* The following symbols define device specific memory regions and must not be changed. */ /* The following symbols define device specific memory regions and must not be changed. */
/* Supervisory FLASH - User Data */ /* Supervisory FLASH - User Data */
define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF;
/* Supervisory FLASH - Normal Access Restrictions (NAR) */ /* Supervisory FLASH - Normal Access Restrictions (NAR) */
define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF;
/* Supervisory FLASH - Public Key */ /* Supervisory FLASH - Public Key */
define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF;
/* Supervisory FLASH - Table of Content # 2 */ /* Supervisory FLASH - Table of Content # 2 */
define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF;
/* Supervisory FLASH - Table of Content # 2 Copy */ /* Supervisory FLASH - Table of Content # 2 Copy */
define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF;
/* eFuse */ /* eFuse */
define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF;
/* XIP */ /* XIP */
define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF;
define symbol __ICFEDIT_region_EROM2_start__ = 0x0; define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
define symbol __ICFEDIT_region_EROM2_end__ = 0x0; define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM3_start__ = 0x0; define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
define symbol __ICFEDIT_region_EROM3_end__ = 0x0; define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
/**** End of ICF editor section. ###ICF###*/ /**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G; define memory mem with size = 4G;
define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
/* Public RAM /* Public RAM
* This is an unprotected public RAM region, with the placed .cy_sharedmem section. * This is an unprotected public RAM region, with the placed .cy_sharedmem section.
* This region is used to place objects that require full access from both cores. * This region is used to place objects that require full access from both cores.
* Uncomment the following lines, define region size, and uncomment the placement of * Uncomment the following lines, define region size, and uncomment the placement of
* .cy_sharedmem section below in the IRAM2_region. Also define the __ICFEDIT_region_IRAM2_start__ * .cy_sharedmem section below in the IRAM2_region. Also define the __ICFEDIT_region_IRAM2_start__
* and __ICFEDIT_region_IRAM2_end__ to place the IRAM2_region. * and __ICFEDIT_region_IRAM2_end__ to place the IRAM2_region.
*/ */
/* /*
define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
*/ */
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
define block RO {first section .intvec, readonly}; define block RO {first section .intvec, readonly};
define block cy_xip { section .cy_xip }; define block cy_xip { section .cy_xip };
/*-Initializations-*/ /*-Initializations-*/
initialize by copy { readwrite }; initialize by copy { readwrite };
do not initialize { section .noinit, section .intvec_ram }; do not initialize { section .noinit, section .intvec_ram };
/*-Placement-*/ /*-Placement-*/
/* Flash - Cortex-M0+ application */ /* Flash - Cortex-M0+ application */
".cy_app_header" : place at start of IROM1_region { section .cy_app_header }; ".cy_app_header" : place at start of IROM1_region { section .cy_app_header };
place in IROM1_region { block RO }; place in IROM1_region { block RO };
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; ".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom };
/* Supervisory Flash - User Data */ /* Supervisory Flash - User Data */
".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; ".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data };
/* Supervisory Flash - NAR */ /* Supervisory Flash - NAR */
".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; ".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar };
/* Supervisory Flash - Public Key */ /* Supervisory Flash - Public Key */
".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; ".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key };
/* Supervisory Flash - TOC2 */ /* Supervisory Flash - TOC2 */
".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; ".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 };
/* Supervisory Flash - RTOC2 */ /* Supervisory Flash - RTOC2 */
".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; ".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 };
/* eFuse */ /* eFuse */
".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; ".cy_efuse" : place at start of IROM8_region { section .cy_efuse };
/* Execute in Place (XIP). See the smif driver documentation for details. */ /* Execute in Place (XIP). See the smif driver documentation for details. */
"cy_xip" : place at start of EROM1_region { block cy_xip }; "cy_xip" : place at start of EROM1_region { block cy_xip };
/* RAM */ /* RAM */
place at start of IRAM1_region { readwrite section .intvec_ram}; place at start of IRAM1_region { readwrite section .intvec_ram};
place in IRAM1_region { readwrite }; place in IRAM1_region { readwrite };
place at end of IRAM1_region { block HSTACK }; place at end of IRAM1_region { block HSTACK };
/* Public RAM /* Public RAM
*To use unprotected public RAM, uncomment the following .cy_sharedmem section placement. *To use unprotected public RAM, uncomment the following .cy_sharedmem section placement.
*/ */
/* /*
place at start of IRAM2_region { section .cy_sharedmem }; place at start of IRAM2_region { section .cy_sharedmem };
*/ */
/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ /* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; ".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
keep { section .cy_app_header, keep { section .cy_app_header,
section .cy_em_eeprom, section .cy_em_eeprom,
section .cy_sflash_user_data, section .cy_sflash_user_data,
section .cy_sflash_nar, section .cy_sflash_nar,
section .cy_sflash_public_key, section .cy_sflash_public_key,
section .cy_toc_part2, section .cy_toc_part2,
section .cy_rtoc_part2, section .cy_rtoc_part2,
section .cy_efuse, section .cy_efuse,
section .cy_xip, section .cy_xip,
section .cymeta, section .cymeta,
}; };
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
define exported symbol __cy_memory_0_start = 0x10000000; define exported symbol __cy_memory_0_start = 0x10000000;
define exported symbol __cy_memory_0_length = 0x00200000; define exported symbol __cy_memory_0_length = 0x00200000;
define exported symbol __cy_memory_0_row_size = 0x200; define exported symbol __cy_memory_0_row_size = 0x200;
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
define exported symbol __cy_memory_1_start = 0x14000000; define exported symbol __cy_memory_1_start = 0x14000000;
define exported symbol __cy_memory_1_length = 0x8000; define exported symbol __cy_memory_1_length = 0x8000;
define exported symbol __cy_memory_1_row_size = 0x200; define exported symbol __cy_memory_1_row_size = 0x200;
/* Supervisory Flash */ /* Supervisory Flash */
define exported symbol __cy_memory_2_start = 0x16000000; define exported symbol __cy_memory_2_start = 0x16000000;
define exported symbol __cy_memory_2_length = 0x8000; define exported symbol __cy_memory_2_length = 0x8000;
define exported symbol __cy_memory_2_row_size = 0x200; define exported symbol __cy_memory_2_row_size = 0x200;
/* XIP */ /* XIP */
define exported symbol __cy_memory_3_start = 0x18000000; define exported symbol __cy_memory_3_start = 0x18000000;
define exported symbol __cy_memory_3_length = 0x08000000; define exported symbol __cy_memory_3_length = 0x08000000;
define exported symbol __cy_memory_3_row_size = 0x200; define exported symbol __cy_memory_3_row_size = 0x200;
/* eFuse */ /* eFuse */
define exported symbol __cy_memory_4_start = 0x90700000; define exported symbol __cy_memory_4_start = 0x90700000;
define exported symbol __cy_memory_4_length = 0x100000; define exported symbol __cy_memory_4_length = 0x100000;
define exported symbol __cy_memory_4_row_size = 1; define exported symbol __cy_memory_4_row_size = 1;
/* EOF */ /* EOF */

554
bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct
View File

@@ -1,277 +1,277 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cy8c6xxa_cm4_dual.sct ;* \file cy8c6xxa_cm4_dual.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM4 core. ; The following defines control RAM and flash memory allocation for the CM4 core.
; You can change the memory allocation by editing RAM and Flash defines. ; You can change the memory allocation by editing RAM and Flash defines.
; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. ; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior. ; Using this memory region for other purposes will lead to unexpected behavior.
; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', ; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. ; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
; RAM ; RAM
#define RAM_START 0x08002000 #define RAM_START 0x08002000
#define RAM_SIZE 0x000FD800 #define RAM_SIZE 0x000FD800
; Flash ; Flash
#define FLASH_START 0x10000000 #define FLASH_START 0x10000000
#define FLASH_SIZE 0x00200000 #define FLASH_SIZE 0x00200000
; The size of the stack section at the end of CM4 SRAM ; The size of the stack section at the end of CM4 SRAM
#define STACK_SIZE 0x00001000 #define STACK_SIZE 0x00001000
; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. ; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
; More about CM0+ prebuilt images, see here: ; More about CM0+ prebuilt images, see here:
; https://github.com/cypresssemiconductorco/psoc6cm0p ; https://github.com/cypresssemiconductorco/psoc6cm0p
; The size of the Cortex-M0+ application flash image ; The size of the Cortex-M0+ application flash image
#define FLASH_CM0P_SIZE 0x2000 #define FLASH_CM0P_SIZE 0x2000
; The following defines describe a 32K flash region used for EEPROM emulation. ; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash. ; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores. ; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation. ; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000 #define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000 #define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data ; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800 #define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800 #define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00 #define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200 #define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key ; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00 #define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 #define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00 #define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200 #define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00 #define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200 #define SFLASH_RTOC_2_SIZE 0x00000200
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; eFuse ; eFuse
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Cortex-M0+ application flash image area ; Cortex-M0+ application flash image area
LR_IROM FLASH_START FLASH_CM0P_SIZE LR_IROM FLASH_START FLASH_CM0P_SIZE
{ {
.cy_m0p_image +0 FLASH_CM0P_SIZE .cy_m0p_image +0 FLASH_CM0P_SIZE
{ {
* (.cy_m0p_image) * (.cy_m0p_image)
} }
} }
; Cortex-M4 application flash area ; Cortex-M4 application flash area
LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
{ {
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
{ {
} }
; Used for the digital signature of the secure application and the ; Used for the digital signature of the secure application and the
; Bootloader SDK application. The size of the section depends on the required ; Bootloader SDK application. The size of the section depends on the required
; data size. ; data size.
.cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
{ {
* (.cy_app_signature) * (.cy_app_signature)
} }
} }
; Emulated EEPROM Flash area ; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{ {
.cy_em_eeprom +0 .cy_em_eeprom +0
{ {
* (.cy_em_eeprom) * (.cy_em_eeprom)
} }
} }
; Supervisory flash: User data ; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{ {
.cy_sflash_user_data +0 .cy_sflash_user_data +0
{ {
* (.cy_sflash_user_data) * (.cy_sflash_user_data)
} }
} }
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{ {
.cy_sflash_nar +0 .cy_sflash_nar +0
{ {
* (.cy_sflash_nar) * (.cy_sflash_nar)
} }
} }
; Supervisory flash: Public Key ; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{ {
.cy_sflash_public_key +0 .cy_sflash_public_key +0
{ {
* (.cy_sflash_public_key) * (.cy_sflash_public_key)
} }
} }
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{ {
.cy_toc_part2 +0 .cy_toc_part2 +0
{ {
* (.cy_toc_part2) * (.cy_toc_part2)
} }
} }
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{ {
.cy_rtoc_part2 +0 .cy_rtoc_part2 +0
{ {
* (.cy_rtoc_part2) * (.cy_rtoc_part2)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
; eFuse ; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE LR_EFUSE EFUSE_START EFUSE_SIZE
{ {
.cy_efuse +0 .cy_efuse +0
{ {
* (.cy_efuse) * (.cy_efuse)
} }
} }
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. ; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000 CYMETA 0x90500000
{ {
.cymeta +0 { * (.cymeta) } .cymeta +0 { * (.cymeta) }
} }
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
#define __cy_memory_0_start 0x10000000 #define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x00200000 #define __cy_memory_0_length 0x00200000
#define __cy_memory_0_row_size 0x200 #define __cy_memory_0_row_size 0x200
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
#define __cy_memory_1_start 0x14000000 #define __cy_memory_1_start 0x14000000
#define __cy_memory_1_length 0x8000 #define __cy_memory_1_length 0x8000
#define __cy_memory_1_row_size 0x200 #define __cy_memory_1_row_size 0x200
/* Supervisory Flash */ /* Supervisory Flash */
#define __cy_memory_2_start 0x16000000 #define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000 #define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200 #define __cy_memory_2_row_size 0x200
/* XIP */ /* XIP */
#define __cy_memory_3_start 0x18000000 #define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000 #define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200 #define __cy_memory_3_row_size 0x200
/* eFuse */ /* eFuse */
#define __cy_memory_4_start 0x90700000 #define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000 #define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1 #define __cy_memory_4_row_size 1
/* [] END OF FILE */ /* [] END OF FILE */

494
bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf
View File

@@ -1,247 +1,247 @@
/******************************************************************************* /*******************************************************************************
* \file cy8c6xxa_cm4_dual.icf * \file cy8c6xxa_cm4_dual.icf
* \version 2.91 * \version 2.91
* *
* Linker file for the IAR compiler. * Linker file for the IAR compiler.
* *
* The main purpose of the linker script is to describe how the sections in the * The main purpose of the linker script is to describe how the sections in the
* input files should be mapped into the output file, and to control the memory * input files should be mapped into the output file, and to control the memory
* layout of the output file. * layout of the output file.
* *
* \note The entry point is fixed and starts at 0x10000000. The valid application * \note The entry point is fixed and starts at 0x10000000. The valid application
* image should be placed there. * image should be placed there.
* *
* \note The linker files included with the PDL template projects must be generic * \note The linker files included with the PDL template projects must be generic
* and handle all common use cases. Your project may not use every section * and handle all common use cases. Your project may not use every section
* defined in the linker files. In that case you may see warnings during the * defined in the linker files. In that case you may see warnings during the
* build process. In your project, you can simply comment out or remove the * build process. In your project, you can simply comment out or remove the
* relevant code in the linker file. * relevant code in the linker file.
* *
******************************************************************************** ********************************************************************************
* \copyright * \copyright
* Copyright 2016-2021 Cypress Semiconductor Corporation * Copyright 2016-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Licensed under the Apache License, Version 2.0 (the "License"); * Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License. * you may not use this file except in compliance with the License.
* You may obtain a copy of the License at * You may obtain a copy of the License at
* *
* http://www.apache.org/licenses/LICENSE-2.0 * http://www.apache.org/licenses/LICENSE-2.0
* *
* Unless required by applicable law or agreed to in writing, software * Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, * distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and * See the License for the specific language governing permissions and
* limitations under the License. * limitations under the License.
*******************************************************************************/ *******************************************************************************/
/*###ICF### Section handled by ICF editor, don't touch! ****/ /*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/ /*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
/*-Specials-*/ /*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000; define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/* The symbols below define the location and size of blocks of memory in the target. /* The symbols below define the location and size of blocks of memory in the target.
* Use these symbols to specify the memory regions available for allocation. * Use these symbols to specify the memory regions available for allocation.
*/ */
/* The following symbols control RAM and flash memory allocation for the CM4 core. /* The following symbols control RAM and flash memory allocation for the CM4 core.
* You can change the memory allocation by editing RAM and Flash symbols. * You can change the memory allocation by editing RAM and Flash symbols.
* Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
* Using this memory region for other purposes will lead to unexpected behavior. * Using this memory region for other purposes will lead to unexpected behavior.
* Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf',
* where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'. * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'.
*/ */
/* RAM */ /* RAM */
define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000; define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000;
define symbol __ICFEDIT_region_IRAM1_end__ = 0x080FF7FF; define symbol __ICFEDIT_region_IRAM1_end__ = 0x080FF7FF;
/* Flash */ /* Flash */
define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
define symbol __ICFEDIT_region_IROM1_end__ = 0x101FFFFF; define symbol __ICFEDIT_region_IROM1_end__ = 0x101FFFFF;
/* The following symbols define a 32K flash region used for EEPROM emulation. /* The following symbols define a 32K flash region used for EEPROM emulation.
* This region can also be used as the general purpose flash. * This region can also be used as the general purpose flash.
* You can assign sections to this memory region for only one of the cores. * You can assign sections to this memory region for only one of the cores.
* Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
* Therefore, repurposing this memory region will prevent such middleware from operation. * Therefore, repurposing this memory region will prevent such middleware from operation.
*/ */
define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF;
/* The following symbols define device specific memory regions and must not be changed. */ /* The following symbols define device specific memory regions and must not be changed. */
/* Supervisory FLASH - User Data */ /* Supervisory FLASH - User Data */
define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF;
/* Supervisory FLASH - Normal Access Restrictions (NAR) */ /* Supervisory FLASH - Normal Access Restrictions (NAR) */
define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF;
/* Supervisory FLASH - Public Key */ /* Supervisory FLASH - Public Key */
define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF;
/* Supervisory FLASH - Table of Content # 2 */ /* Supervisory FLASH - Table of Content # 2 */
define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF;
/* Supervisory FLASH - Table of Content # 2 Copy */ /* Supervisory FLASH - Table of Content # 2 Copy */
define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF;
/* eFuse */ /* eFuse */
define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF;
/* XIP */ /* XIP */
define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF;
define symbol __ICFEDIT_region_EROM2_start__ = 0x0; define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
define symbol __ICFEDIT_region_EROM2_end__ = 0x0; define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM3_start__ = 0x0; define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
define symbol __ICFEDIT_region_EROM3_end__ = 0x0; define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
/*-Sizes-*/ /*-Sizes-*/
if (!isdefinedsymbol(__STACK_SIZE)) { if (!isdefinedsymbol(__STACK_SIZE)) {
define symbol __ICFEDIT_size_cstack__ = 0x1000; define symbol __ICFEDIT_size_cstack__ = 0x1000;
} else { } else {
define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
} }
define symbol __ICFEDIT_size_proc_stack__ = 0x0; define symbol __ICFEDIT_size_proc_stack__ = 0x0;
/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ /* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
if (!isdefinedsymbol(__HEAP_SIZE)) { if (!isdefinedsymbol(__HEAP_SIZE)) {
define symbol __ICFEDIT_size_heap__ = 0x0400; define symbol __ICFEDIT_size_heap__ = 0x0400;
} else { } else {
define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
} }
/**** End of ICF editor section. ###ICF###*/ /**** End of ICF editor section. ###ICF###*/
/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. /* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
* More about CM0+ prebuilt images, see here: * More about CM0+ prebuilt images, see here:
* https://github.com/cypresssemiconductorco/psoc6cm0p * https://github.com/cypresssemiconductorco/psoc6cm0p
*/ */
/* The size of the Cortex-M0+ application image */ /* The size of the Cortex-M0+ application image */
define symbol FLASH_CM0P_SIZE = 0x2000; define symbol FLASH_CM0P_SIZE = 0x2000;
define memory mem with size = 4G; define memory mem with size = 4G;
define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image }; define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image };
define block RO {first section .intvec, readonly}; define block RO {first section .intvec, readonly};
define block cy_xip { section .cy_xip }; define block cy_xip { section .cy_xip };
/*-Initializations-*/ /*-Initializations-*/
initialize by copy { readwrite }; initialize by copy { readwrite };
do not initialize { section .noinit, section .intvec_ram }; do not initialize { section .noinit, section .intvec_ram };
/*-Placement-*/ /*-Placement-*/
/* Flash - Cortex-M0+ application image */ /* Flash - Cortex-M0+ application image */
place at start of IROM1_region { block CM0P_RO }; place at start of IROM1_region { block CM0P_RO };
/* Flash - Cortex-M4 application */ /* Flash - Cortex-M4 application */
place in IROM1_region { block RO }; place in IROM1_region { block RO };
/* Used for the digital signature of the secure application and the Bootloader SDK application. */ /* Used for the digital signature of the secure application and the Bootloader SDK application. */
".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; ".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; ".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom };
/* Supervisory Flash - User Data */ /* Supervisory Flash - User Data */
".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; ".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data };
/* Supervisory Flash - NAR */ /* Supervisory Flash - NAR */
".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; ".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar };
/* Supervisory Flash - Public Key */ /* Supervisory Flash - Public Key */
".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; ".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key };
/* Supervisory Flash - TOC2 */ /* Supervisory Flash - TOC2 */
".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; ".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 };
/* Supervisory Flash - RTOC2 */ /* Supervisory Flash - RTOC2 */
".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; ".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 };
/* eFuse */ /* eFuse */
".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; ".cy_efuse" : place at start of IROM8_region { section .cy_efuse };
/* Execute in Place (XIP). See the smif driver documentation for details. */ /* Execute in Place (XIP). See the smif driver documentation for details. */
"cy_xip" : place at start of EROM1_region { block cy_xip }; "cy_xip" : place at start of EROM1_region { block cy_xip };
/* RAM */ /* RAM */
place at start of IRAM1_region { readwrite section .intvec_ram}; place at start of IRAM1_region { readwrite section .intvec_ram};
place in IRAM1_region { readwrite }; place in IRAM1_region { readwrite };
place at end of IRAM1_region { block HSTACK }; place at end of IRAM1_region { block HSTACK };
/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ /* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; ".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
keep { section .cy_m0p_image, keep { section .cy_m0p_image,
section .cy_app_signature, section .cy_app_signature,
section .cy_em_eeprom, section .cy_em_eeprom,
section .cy_sflash_user_data, section .cy_sflash_user_data,
section .cy_sflash_nar, section .cy_sflash_nar,
section .cy_sflash_public_key, section .cy_sflash_public_key,
section .cy_toc_part2, section .cy_toc_part2,
section .cy_rtoc_part2, section .cy_rtoc_part2,
section .cy_efuse, section .cy_efuse,
section .cy_xip, section .cy_xip,
section .cymeta, section .cymeta,
}; };
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
define exported symbol __cy_memory_0_start = 0x10000000; define exported symbol __cy_memory_0_start = 0x10000000;
define exported symbol __cy_memory_0_length = 0x00200000; define exported symbol __cy_memory_0_length = 0x00200000;
define exported symbol __cy_memory_0_row_size = 0x200; define exported symbol __cy_memory_0_row_size = 0x200;
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
define exported symbol __cy_memory_1_start = 0x14000000; define exported symbol __cy_memory_1_start = 0x14000000;
define exported symbol __cy_memory_1_length = 0x8000; define exported symbol __cy_memory_1_length = 0x8000;
define exported symbol __cy_memory_1_row_size = 0x200; define exported symbol __cy_memory_1_row_size = 0x200;
/* Supervisory Flash */ /* Supervisory Flash */
define exported symbol __cy_memory_2_start = 0x16000000; define exported symbol __cy_memory_2_start = 0x16000000;
define exported symbol __cy_memory_2_length = 0x8000; define exported symbol __cy_memory_2_length = 0x8000;
define exported symbol __cy_memory_2_row_size = 0x200; define exported symbol __cy_memory_2_row_size = 0x200;
/* XIP */ /* XIP */
define exported symbol __cy_memory_3_start = 0x18000000; define exported symbol __cy_memory_3_start = 0x18000000;
define exported symbol __cy_memory_3_length = 0x08000000; define exported symbol __cy_memory_3_length = 0x08000000;
define exported symbol __cy_memory_3_row_size = 0x200; define exported symbol __cy_memory_3_row_size = 0x200;
/* eFuse */ /* eFuse */
define exported symbol __cy_memory_4_start = 0x90700000; define exported symbol __cy_memory_4_start = 0x90700000;
define exported symbol __cy_memory_4_length = 0x100000; define exported symbol __cy_memory_4_length = 0x100000;
define exported symbol __cy_memory_4_row_size = 1; define exported symbol __cy_memory_4_row_size = 1;
/* EOF */ /* EOF */

584
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx4_cm0plus.sct
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@@ -1,292 +1,292 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cy8c6xx4_cm0plus.sct ;* \file cy8c6xx4_cm0plus.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
#if !defined(MBED_ROM_START) #if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x10000000 #define MBED_ROM_START 0x10000000
#endif #endif
;* MBED_APP_START is being used by the bootloader build script and ;* MBED_APP_START is being used by the bootloader build script and
;* will be calculate by the system. Without bootloader the MBED_APP_START ;* will be calculate by the system. Without bootloader the MBED_APP_START
;* is equal to MBED_ROM_START ;* is equal to MBED_ROM_START
;* ;*
#if !defined(MBED_APP_START) #if !defined(MBED_APP_START)
#define MBED_APP_START MBED_ROM_START #define MBED_APP_START MBED_ROM_START
#endif #endif
#if !defined(MBED_ROM_SIZE) #if !defined(MBED_ROM_SIZE)
#define MBED_ROM_SIZE 0x80000 #define MBED_ROM_SIZE 0x80000
#endif #endif
;* MBED_APP_SIZE is being used by the bootloader build script and ;* MBED_APP_SIZE is being used by the bootloader build script and
;* will be calculate by the system. Without bootloader the MBED_APP_SIZE ;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
;* is equal to MBED_ROM_SIZE ;* is equal to MBED_ROM_SIZE
;* ;*
#if !defined(MBED_APP_SIZE) #if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE MBED_ROM_SIZE #define MBED_APP_SIZE MBED_ROM_SIZE
#endif #endif
#if !defined(MBED_RAM_START) #if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x08000000 #define MBED_RAM_START 0x08000000
#endif #endif
#if !defined(MBED_RAM_SIZE) #if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x00010000 #define MBED_RAM_SIZE 0x00010000
#endif #endif
#if !defined(MBED_PUBLIC_RAM_SIZE) #if !defined(MBED_PUBLIC_RAM_SIZE)
#define MBED_PUBLIC_RAM_SIZE 0x200 #define MBED_PUBLIC_RAM_SIZE 0x200
#endif #endif
; The size of the stack section at the end of CM0+ SRAM ; The size of the stack section at the end of CM0+ SRAM
#if !defined(MBED_BOOT_STACK_SIZE) #if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400 #define MBED_BOOT_STACK_SIZE 0x400
#endif #endif
#define STACK_SIZE MBED_BOOT_STACK_SIZE #define STACK_SIZE MBED_BOOT_STACK_SIZE
#if !defined(MBED_PUBLIC_RAM_START) #if !defined(MBED_PUBLIC_RAM_START)
#define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)
#endif #endif
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM0+ core. ; The following defines control RAM and flash memory allocation for the CM0+ core.
; You can change the memory allocation by editing the RAM and Flash defines. ; You can change the memory allocation by editing the RAM and Flash defines.
; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. ; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior. ; Using this memory region for other purposes will lead to unexpected behavior.
; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', ; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. ; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
; RAM ; RAM
#define RAM_START MBED_RAM_START #define RAM_START MBED_RAM_START
#define RAM_SIZE MBED_RAM_SIZE #define RAM_SIZE MBED_RAM_SIZE
; Public RAM ; Public RAM
#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START #define PUBLIC_RAM_START MBED_PUBLIC_RAM_START
#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE #define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE
; Flash ; Flash
#define FLASH_START MBED_APP_START #define FLASH_START MBED_APP_START
#define FLASH_SIZE MBED_APP_SIZE #define FLASH_SIZE MBED_APP_SIZE
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data ; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800 #define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800 #define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00 #define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200 #define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key ; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00 #define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 #define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00 #define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200 #define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00 #define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200 #define SFLASH_RTOC_2_SIZE 0x00000200
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; eFuse ; eFuse
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Cortex-M0+ application flash area ; Cortex-M0+ application flash area
LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
{ {
.cy_app_header +0 .cy_app_header +0
{ {
* (.cy_app_header) * (.cy_app_header)
} }
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
RW_IRAM2 PUBLIC_RAM_START UNINIT RW_IRAM2 PUBLIC_RAM_START UNINIT
{ {
* (.cy_sharedmem) * (.cy_sharedmem)
} }
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
{ {
} }
} }
; Supervisory flash: User data ; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{ {
.cy_sflash_user_data +0 .cy_sflash_user_data +0
{ {
* (.cy_sflash_user_data) * (.cy_sflash_user_data)
} }
} }
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{ {
.cy_sflash_nar +0 .cy_sflash_nar +0
{ {
* (.cy_sflash_nar) * (.cy_sflash_nar)
} }
} }
; Supervisory flash: Public Key ; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{ {
.cy_sflash_public_key +0 .cy_sflash_public_key +0
{ {
* (.cy_sflash_public_key) * (.cy_sflash_public_key)
} }
} }
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{ {
.cy_toc_part2 +0 .cy_toc_part2 +0
{ {
* (.cy_toc_part2) * (.cy_toc_part2)
} }
} }
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{ {
.cy_rtoc_part2 +0 .cy_rtoc_part2 +0
{ {
* (.cy_rtoc_part2) * (.cy_rtoc_part2)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
; eFuse ; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE LR_EFUSE EFUSE_START EFUSE_SIZE
{ {
.cy_efuse +0 .cy_efuse +0
{ {
* (.cy_efuse) * (.cy_efuse)
} }
} }
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. ; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000 CYMETA 0x90500000
{ {
.cymeta +0 { * (.cymeta) } .cymeta +0 { * (.cymeta) }
} }
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
#define __cy_memory_0_start 0x10000000 #define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x00040000 #define __cy_memory_0_length 0x00040000
#define __cy_memory_0_row_size 0x200 #define __cy_memory_0_row_size 0x200
/* Supervisory Flash */ /* Supervisory Flash */
#define __cy_memory_2_start 0x16000000 #define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000 #define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200 #define __cy_memory_2_row_size 0x200
/* XIP */ /* XIP */
#define __cy_memory_3_start 0x18000000 #define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000 #define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200 #define __cy_memory_3_row_size 0x200
/* eFuse */ /* eFuse */
#define __cy_memory_4_start 0x90700000 #define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000 #define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1 #define __cy_memory_4_row_size 1
/* [] END OF FILE */ /* [] END OF FILE */

622
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct
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@@ -1,311 +1,311 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cy8c6xx5_cm0plus.sct ;* \file cy8c6xx5_cm0plus.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
#if !defined(MBED_ROM_START) #if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x10000000 #define MBED_ROM_START 0x10000000
#endif #endif
;* MBED_APP_START is being used by the bootloader build script and ;* MBED_APP_START is being used by the bootloader build script and
;* will be calculate by the system. Without bootloader the MBED_APP_START ;* will be calculate by the system. Without bootloader the MBED_APP_START
;* is equal to MBED_ROM_START ;* is equal to MBED_ROM_START
;* ;*
#if !defined(MBED_APP_START) #if !defined(MBED_APP_START)
#define MBED_APP_START MBED_ROM_START #define MBED_APP_START MBED_ROM_START
#endif #endif
#if !defined(MBED_ROM_SIZE) #if !defined(MBED_ROM_SIZE)
#define MBED_ROM_SIZE 0x80000 #define MBED_ROM_SIZE 0x80000
#endif #endif
;* MBED_APP_SIZE is being used by the bootloader build script and ;* MBED_APP_SIZE is being used by the bootloader build script and
;* will be calculate by the system. Without bootloader the MBED_APP_SIZE ;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
;* is equal to MBED_ROM_SIZE ;* is equal to MBED_ROM_SIZE
;* ;*
#if !defined(MBED_APP_SIZE) #if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE MBED_ROM_SIZE #define MBED_APP_SIZE MBED_ROM_SIZE
#endif #endif
#if !defined(MBED_RAM_START) #if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x08000000 #define MBED_RAM_START 0x08000000
#endif #endif
#if !defined(MBED_RAM_SIZE) #if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x00010000 #define MBED_RAM_SIZE 0x00010000
#endif #endif
#if !defined(MBED_PUBLIC_RAM_SIZE) #if !defined(MBED_PUBLIC_RAM_SIZE)
#define MBED_PUBLIC_RAM_SIZE 0x200 #define MBED_PUBLIC_RAM_SIZE 0x200
#endif #endif
; The size of the stack section at the end of CM0+ SRAM ; The size of the stack section at the end of CM0+ SRAM
#if !defined(MBED_BOOT_STACK_SIZE) #if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400 #define MBED_BOOT_STACK_SIZE 0x400
#endif #endif
#define STACK_SIZE MBED_BOOT_STACK_SIZE #define STACK_SIZE MBED_BOOT_STACK_SIZE
#if !defined(MBED_PUBLIC_RAM_START) #if !defined(MBED_PUBLIC_RAM_START)
#define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)
#endif #endif
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM0+ core. ; The following defines control RAM and flash memory allocation for the CM0+ core.
; You can change the memory allocation by editing the RAM and Flash defines. ; You can change the memory allocation by editing the RAM and Flash defines.
; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. ; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior. ; Using this memory region for other purposes will lead to unexpected behavior.
; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', ; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. ; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
; RAM ; RAM
#define RAM_START MBED_RAM_START #define RAM_START MBED_RAM_START
#define RAM_SIZE MBED_RAM_SIZE #define RAM_SIZE MBED_RAM_SIZE
; Public RAM ; Public RAM
#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START #define PUBLIC_RAM_START MBED_PUBLIC_RAM_START
#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE #define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE
; Flash ; Flash
#define FLASH_START MBED_APP_START #define FLASH_START MBED_APP_START
#define FLASH_SIZE MBED_APP_SIZE #define FLASH_SIZE MBED_APP_SIZE
; The following defines describe a 32K flash region used for EEPROM emulation. ; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash. ; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores. ; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation. ; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000 #define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000 #define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data ; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800 #define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800 #define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00 #define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200 #define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key ; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00 #define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 #define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00 #define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200 #define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00 #define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200 #define SFLASH_RTOC_2_SIZE 0x00000200
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; eFuse ; eFuse
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Cortex-M0+ application flash area ; Cortex-M0+ application flash area
LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
{ {
.cy_app_header +0 .cy_app_header +0
{ {
* (.cy_app_header) * (.cy_app_header)
} }
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
RW_IRAM2 PUBLIC_RAM_START UNINIT RW_IRAM2 PUBLIC_RAM_START UNINIT
{ {
* (.cy_sharedmem) * (.cy_sharedmem)
} }
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
{ {
} }
} }
; Emulated EEPROM Flash area ; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{ {
.cy_em_eeprom +0 .cy_em_eeprom +0
{ {
* (.cy_em_eeprom) * (.cy_em_eeprom)
} }
} }
; Supervisory flash: User data ; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{ {
.cy_sflash_user_data +0 .cy_sflash_user_data +0
{ {
* (.cy_sflash_user_data) * (.cy_sflash_user_data)
} }
} }
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{ {
.cy_sflash_nar +0 .cy_sflash_nar +0
{ {
* (.cy_sflash_nar) * (.cy_sflash_nar)
} }
} }
; Supervisory flash: Public Key ; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{ {
.cy_sflash_public_key +0 .cy_sflash_public_key +0
{ {
* (.cy_sflash_public_key) * (.cy_sflash_public_key)
} }
} }
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{ {
.cy_toc_part2 +0 .cy_toc_part2 +0
{ {
* (.cy_toc_part2) * (.cy_toc_part2)
} }
} }
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{ {
.cy_rtoc_part2 +0 .cy_rtoc_part2 +0
{ {
* (.cy_rtoc_part2) * (.cy_rtoc_part2)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
; eFuse ; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE LR_EFUSE EFUSE_START EFUSE_SIZE
{ {
.cy_efuse +0 .cy_efuse +0
{ {
* (.cy_efuse) * (.cy_efuse)
} }
} }
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. ; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000 CYMETA 0x90500000
{ {
.cymeta +0 { * (.cymeta) } .cymeta +0 { * (.cymeta) }
} }
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
#define __cy_memory_0_start 0x10000000 #define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x00080000 #define __cy_memory_0_length 0x00080000
#define __cy_memory_0_row_size 0x200 #define __cy_memory_0_row_size 0x200
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
#define __cy_memory_1_start 0x14000000 #define __cy_memory_1_start 0x14000000
#define __cy_memory_1_length 0x8000 #define __cy_memory_1_length 0x8000
#define __cy_memory_1_row_size 0x200 #define __cy_memory_1_row_size 0x200
/* Supervisory Flash */ /* Supervisory Flash */
#define __cy_memory_2_start 0x16000000 #define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000 #define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200 #define __cy_memory_2_row_size 0x200
/* XIP */ /* XIP */
#define __cy_memory_3_start 0x18000000 #define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000 #define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200 #define __cy_memory_3_row_size 0x200
/* eFuse */ /* eFuse */
#define __cy_memory_4_start 0x90700000 #define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000 #define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1 #define __cy_memory_4_row_size 1
/* [] END OF FILE */ /* [] END OF FILE */

622
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct
View File

@@ -1,311 +1,311 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cy8c6xx6_cm0plus.sct ;* \file cy8c6xx6_cm0plus.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
#if !defined(MBED_ROM_START) #if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x10000000 #define MBED_ROM_START 0x10000000
#endif #endif
;* MBED_APP_START is being used by the bootloader build script and ;* MBED_APP_START is being used by the bootloader build script and
;* will be calculate by the system. Without bootloader the MBED_APP_START ;* will be calculate by the system. Without bootloader the MBED_APP_START
;* is equal to MBED_ROM_START ;* is equal to MBED_ROM_START
;* ;*
#if !defined(MBED_APP_START) #if !defined(MBED_APP_START)
#define MBED_APP_START MBED_ROM_START #define MBED_APP_START MBED_ROM_START
#endif #endif
#if !defined(MBED_ROM_SIZE) #if !defined(MBED_ROM_SIZE)
#define MBED_ROM_SIZE 0x80000 #define MBED_ROM_SIZE 0x80000
#endif #endif
;* MBED_APP_SIZE is being used by the bootloader build script and ;* MBED_APP_SIZE is being used by the bootloader build script and
;* will be calculate by the system. Without bootloader the MBED_APP_SIZE ;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
;* is equal to MBED_ROM_SIZE ;* is equal to MBED_ROM_SIZE
;* ;*
#if !defined(MBED_APP_SIZE) #if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE MBED_ROM_SIZE #define MBED_APP_SIZE MBED_ROM_SIZE
#endif #endif
#if !defined(MBED_RAM_START) #if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x08000000 #define MBED_RAM_START 0x08000000
#endif #endif
#if !defined(MBED_RAM_SIZE) #if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x00010000 #define MBED_RAM_SIZE 0x00010000
#endif #endif
#if !defined(MBED_PUBLIC_RAM_SIZE) #if !defined(MBED_PUBLIC_RAM_SIZE)
#define MBED_PUBLIC_RAM_SIZE 0x200 #define MBED_PUBLIC_RAM_SIZE 0x200
#endif #endif
; The size of the stack section at the end of CM0+ SRAM ; The size of the stack section at the end of CM0+ SRAM
#if !defined(MBED_BOOT_STACK_SIZE) #if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400 #define MBED_BOOT_STACK_SIZE 0x400
#endif #endif
#define STACK_SIZE MBED_BOOT_STACK_SIZE #define STACK_SIZE MBED_BOOT_STACK_SIZE
#if !defined(MBED_PUBLIC_RAM_START) #if !defined(MBED_PUBLIC_RAM_START)
#define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)
#endif #endif
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM0+ core. ; The following defines control RAM and flash memory allocation for the CM0+ core.
; You can change the memory allocation by editing the RAM and Flash defines. ; You can change the memory allocation by editing the RAM and Flash defines.
; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. ; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior. ; Using this memory region for other purposes will lead to unexpected behavior.
; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', ; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. ; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
; RAM ; RAM
#define RAM_START MBED_RAM_START #define RAM_START MBED_RAM_START
#define RAM_SIZE MBED_RAM_SIZE #define RAM_SIZE MBED_RAM_SIZE
; Public RAM ; Public RAM
#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START #define PUBLIC_RAM_START MBED_PUBLIC_RAM_START
#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE #define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE
; Flash ; Flash
#define FLASH_START MBED_APP_START #define FLASH_START MBED_APP_START
#define FLASH_SIZE MBED_APP_SIZE #define FLASH_SIZE MBED_APP_SIZE
; The following defines describe a 32K flash region used for EEPROM emulation. ; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash. ; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores. ; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation. ; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000 #define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000 #define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data ; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800 #define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800 #define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00 #define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200 #define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key ; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00 #define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 #define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00 #define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200 #define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00 #define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200 #define SFLASH_RTOC_2_SIZE 0x00000200
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; eFuse ; eFuse
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Cortex-M0+ application flash area ; Cortex-M0+ application flash area
LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
{ {
.cy_app_header +0 .cy_app_header +0
{ {
* (.cy_app_header) * (.cy_app_header)
} }
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
RW_IRAM2 PUBLIC_RAM_START UNINIT RW_IRAM2 PUBLIC_RAM_START UNINIT
{ {
* (.cy_sharedmem) * (.cy_sharedmem)
} }
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
{ {
} }
} }
; Emulated EEPROM Flash area ; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{ {
.cy_em_eeprom +0 .cy_em_eeprom +0
{ {
* (.cy_em_eeprom) * (.cy_em_eeprom)
} }
} }
; Supervisory flash: User data ; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{ {
.cy_sflash_user_data +0 .cy_sflash_user_data +0
{ {
* (.cy_sflash_user_data) * (.cy_sflash_user_data)
} }
} }
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{ {
.cy_sflash_nar +0 .cy_sflash_nar +0
{ {
* (.cy_sflash_nar) * (.cy_sflash_nar)
} }
} }
; Supervisory flash: Public Key ; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{ {
.cy_sflash_public_key +0 .cy_sflash_public_key +0
{ {
* (.cy_sflash_public_key) * (.cy_sflash_public_key)
} }
} }
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{ {
.cy_toc_part2 +0 .cy_toc_part2 +0
{ {
* (.cy_toc_part2) * (.cy_toc_part2)
} }
} }
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{ {
.cy_rtoc_part2 +0 .cy_rtoc_part2 +0
{ {
* (.cy_rtoc_part2) * (.cy_rtoc_part2)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
; eFuse ; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE LR_EFUSE EFUSE_START EFUSE_SIZE
{ {
.cy_efuse +0 .cy_efuse +0
{ {
* (.cy_efuse) * (.cy_efuse)
} }
} }
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. ; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000 CYMETA 0x90500000
{ {
.cymeta +0 { * (.cymeta) } .cymeta +0 { * (.cymeta) }
} }
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
#define __cy_memory_0_start 0x10000000 #define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x00080000 #define __cy_memory_0_length 0x00080000
#define __cy_memory_0_row_size 0x200 #define __cy_memory_0_row_size 0x200
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
#define __cy_memory_1_start 0x14000000 #define __cy_memory_1_start 0x14000000
#define __cy_memory_1_length 0x8000 #define __cy_memory_1_length 0x8000
#define __cy_memory_1_row_size 0x200 #define __cy_memory_1_row_size 0x200
/* Supervisory Flash */ /* Supervisory Flash */
#define __cy_memory_2_start 0x16000000 #define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000 #define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200 #define __cy_memory_2_row_size 0x200
/* XIP */ /* XIP */
#define __cy_memory_3_start 0x18000000 #define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000 #define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200 #define __cy_memory_3_row_size 0x200
/* eFuse */ /* eFuse */
#define __cy_memory_4_start 0x90700000 #define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000 #define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1 #define __cy_memory_4_row_size 1
/* [] END OF FILE */ /* [] END OF FILE */

622
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct
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@@ -1,311 +1,311 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cy8c6xx7_cm0plus.sct ;* \file cy8c6xx7_cm0plus.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
#if !defined(MBED_ROM_START) #if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x10000000 #define MBED_ROM_START 0x10000000
#endif #endif
;* MBED_APP_START is being used by the bootloader build script and ;* MBED_APP_START is being used by the bootloader build script and
;* will be calculate by the system. Without bootloader the MBED_APP_START ;* will be calculate by the system. Without bootloader the MBED_APP_START
;* is equal to MBED_ROM_START ;* is equal to MBED_ROM_START
;* ;*
#if !defined(MBED_APP_START) #if !defined(MBED_APP_START)
#define MBED_APP_START MBED_ROM_START #define MBED_APP_START MBED_ROM_START
#endif #endif
#if !defined(MBED_ROM_SIZE) #if !defined(MBED_ROM_SIZE)
#define MBED_ROM_SIZE 0x80000 #define MBED_ROM_SIZE 0x80000
#endif #endif
;* MBED_APP_SIZE is being used by the bootloader build script and ;* MBED_APP_SIZE is being used by the bootloader build script and
;* will be calculate by the system. Without bootloader the MBED_APP_SIZE ;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
;* is equal to MBED_ROM_SIZE ;* is equal to MBED_ROM_SIZE
;* ;*
#if !defined(MBED_APP_SIZE) #if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE MBED_ROM_SIZE #define MBED_APP_SIZE MBED_ROM_SIZE
#endif #endif
#if !defined(MBED_RAM_START) #if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x08000000 #define MBED_RAM_START 0x08000000
#endif #endif
#if !defined(MBED_RAM_SIZE) #if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x00010000 #define MBED_RAM_SIZE 0x00010000
#endif #endif
#if !defined(MBED_PUBLIC_RAM_SIZE) #if !defined(MBED_PUBLIC_RAM_SIZE)
#define MBED_PUBLIC_RAM_SIZE 0x200 #define MBED_PUBLIC_RAM_SIZE 0x200
#endif #endif
; The size of the stack section at the end of CM0+ SRAM ; The size of the stack section at the end of CM0+ SRAM
#if !defined(MBED_BOOT_STACK_SIZE) #if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400 #define MBED_BOOT_STACK_SIZE 0x400
#endif #endif
#define STACK_SIZE MBED_BOOT_STACK_SIZE #define STACK_SIZE MBED_BOOT_STACK_SIZE
#if !defined(MBED_PUBLIC_RAM_START) #if !defined(MBED_PUBLIC_RAM_START)
#define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)
#endif #endif
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM0+ core. ; The following defines control RAM and flash memory allocation for the CM0+ core.
; You can change the memory allocation by editing the RAM and Flash defines. ; You can change the memory allocation by editing the RAM and Flash defines.
; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. ; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior. ; Using this memory region for other purposes will lead to unexpected behavior.
; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', ; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. ; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
; RAM ; RAM
#define RAM_START MBED_RAM_START #define RAM_START MBED_RAM_START
#define RAM_SIZE MBED_RAM_SIZE #define RAM_SIZE MBED_RAM_SIZE
; Public RAM ; Public RAM
#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START #define PUBLIC_RAM_START MBED_PUBLIC_RAM_START
#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE #define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE
; Flash ; Flash
#define FLASH_START MBED_APP_START #define FLASH_START MBED_APP_START
#define FLASH_SIZE MBED_APP_SIZE #define FLASH_SIZE MBED_APP_SIZE
; The following defines describe a 32K flash region used for EEPROM emulation. ; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash. ; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores. ; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation. ; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000 #define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000 #define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data ; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800 #define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800 #define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00 #define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200 #define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key ; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00 #define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 #define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00 #define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200 #define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00 #define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200 #define SFLASH_RTOC_2_SIZE 0x00000200
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; eFuse ; eFuse
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Cortex-M0+ application flash area ; Cortex-M0+ application flash area
LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
{ {
.cy_app_header +0 .cy_app_header +0
{ {
* (.cy_app_header) * (.cy_app_header)
} }
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
RW_IRAM2 PUBLIC_RAM_START UNINIT RW_IRAM2 PUBLIC_RAM_START UNINIT
{ {
* (.cy_sharedmem) * (.cy_sharedmem)
} }
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
{ {
} }
} }
; Emulated EEPROM Flash area ; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{ {
.cy_em_eeprom +0 .cy_em_eeprom +0
{ {
* (.cy_em_eeprom) * (.cy_em_eeprom)
} }
} }
; Supervisory flash: User data ; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{ {
.cy_sflash_user_data +0 .cy_sflash_user_data +0
{ {
* (.cy_sflash_user_data) * (.cy_sflash_user_data)
} }
} }
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{ {
.cy_sflash_nar +0 .cy_sflash_nar +0
{ {
* (.cy_sflash_nar) * (.cy_sflash_nar)
} }
} }
; Supervisory flash: Public Key ; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{ {
.cy_sflash_public_key +0 .cy_sflash_public_key +0
{ {
* (.cy_sflash_public_key) * (.cy_sflash_public_key)
} }
} }
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{ {
.cy_toc_part2 +0 .cy_toc_part2 +0
{ {
* (.cy_toc_part2) * (.cy_toc_part2)
} }
} }
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{ {
.cy_rtoc_part2 +0 .cy_rtoc_part2 +0
{ {
* (.cy_rtoc_part2) * (.cy_rtoc_part2)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
; eFuse ; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE LR_EFUSE EFUSE_START EFUSE_SIZE
{ {
.cy_efuse +0 .cy_efuse +0
{ {
* (.cy_efuse) * (.cy_efuse)
} }
} }
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. ; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000 CYMETA 0x90500000
{ {
.cymeta +0 { * (.cymeta) } .cymeta +0 { * (.cymeta) }
} }
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
#define __cy_memory_0_start 0x10000000 #define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x00100000 #define __cy_memory_0_length 0x00100000
#define __cy_memory_0_row_size 0x200 #define __cy_memory_0_row_size 0x200
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
#define __cy_memory_1_start 0x14000000 #define __cy_memory_1_start 0x14000000
#define __cy_memory_1_length 0x8000 #define __cy_memory_1_length 0x8000
#define __cy_memory_1_row_size 0x200 #define __cy_memory_1_row_size 0x200
/* Supervisory Flash */ /* Supervisory Flash */
#define __cy_memory_2_start 0x16000000 #define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000 #define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200 #define __cy_memory_2_row_size 0x200
/* XIP */ /* XIP */
#define __cy_memory_3_start 0x18000000 #define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000 #define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200 #define __cy_memory_3_row_size 0x200
/* eFuse */ /* eFuse */
#define __cy_memory_4_start 0x90700000 #define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000 #define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1 #define __cy_memory_4_row_size 1
/* [] END OF FILE */ /* [] END OF FILE */

622
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct
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@@ -1,311 +1,311 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cy8c6xx8_cm0plus.sct ;* \file cy8c6xx8_cm0plus.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
#if !defined(MBED_ROM_START) #if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x10000000 #define MBED_ROM_START 0x10000000
#endif #endif
;* MBED_APP_START is being used by the bootloader build script and ;* MBED_APP_START is being used by the bootloader build script and
;* will be calculate by the system. Without bootloader the MBED_APP_START ;* will be calculate by the system. Without bootloader the MBED_APP_START
;* is equal to MBED_ROM_START ;* is equal to MBED_ROM_START
;* ;*
#if !defined(MBED_APP_START) #if !defined(MBED_APP_START)
#define MBED_APP_START MBED_ROM_START #define MBED_APP_START MBED_ROM_START
#endif #endif
#if !defined(MBED_ROM_SIZE) #if !defined(MBED_ROM_SIZE)
#define MBED_ROM_SIZE 0x80000 #define MBED_ROM_SIZE 0x80000
#endif #endif
;* MBED_APP_SIZE is being used by the bootloader build script and ;* MBED_APP_SIZE is being used by the bootloader build script and
;* will be calculate by the system. Without bootloader the MBED_APP_SIZE ;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
;* is equal to MBED_ROM_SIZE ;* is equal to MBED_ROM_SIZE
;* ;*
#if !defined(MBED_APP_SIZE) #if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE MBED_ROM_SIZE #define MBED_APP_SIZE MBED_ROM_SIZE
#endif #endif
#if !defined(MBED_RAM_START) #if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x08000000 #define MBED_RAM_START 0x08000000
#endif #endif
#if !defined(MBED_RAM_SIZE) #if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x00010000 #define MBED_RAM_SIZE 0x00010000
#endif #endif
#if !defined(MBED_PUBLIC_RAM_SIZE) #if !defined(MBED_PUBLIC_RAM_SIZE)
#define MBED_PUBLIC_RAM_SIZE 0x200 #define MBED_PUBLIC_RAM_SIZE 0x200
#endif #endif
; The size of the stack section at the end of CM0+ SRAM ; The size of the stack section at the end of CM0+ SRAM
#if !defined(MBED_BOOT_STACK_SIZE) #if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400 #define MBED_BOOT_STACK_SIZE 0x400
#endif #endif
#define STACK_SIZE MBED_BOOT_STACK_SIZE #define STACK_SIZE MBED_BOOT_STACK_SIZE
#if !defined(MBED_PUBLIC_RAM_START) #if !defined(MBED_PUBLIC_RAM_START)
#define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)
#endif #endif
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM0+ core. ; The following defines control RAM and flash memory allocation for the CM0+ core.
; You can change the memory allocation by editing the RAM and Flash defines. ; You can change the memory allocation by editing the RAM and Flash defines.
; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. ; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior. ; Using this memory region for other purposes will lead to unexpected behavior.
; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', ; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. ; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
; RAM ; RAM
#define RAM_START MBED_RAM_START #define RAM_START MBED_RAM_START
#define RAM_SIZE MBED_RAM_SIZE #define RAM_SIZE MBED_RAM_SIZE
; Public RAM ; Public RAM
#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START #define PUBLIC_RAM_START MBED_PUBLIC_RAM_START
#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE #define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE
; Flash ; Flash
#define FLASH_START MBED_APP_START #define FLASH_START MBED_APP_START
#define FLASH_SIZE MBED_APP_SIZE #define FLASH_SIZE MBED_APP_SIZE
; The following defines describe a 32K flash region used for EEPROM emulation. ; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash. ; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores. ; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation. ; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000 #define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000 #define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data ; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800 #define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800 #define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00 #define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200 #define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key ; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00 #define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 #define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00 #define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200 #define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00 #define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200 #define SFLASH_RTOC_2_SIZE 0x00000200
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; eFuse ; eFuse
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Cortex-M0+ application flash area ; Cortex-M0+ application flash area
LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
{ {
.cy_app_header +0 .cy_app_header +0
{ {
* (.cy_app_header) * (.cy_app_header)
} }
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
RW_IRAM2 PUBLIC_RAM_START UNINIT RW_IRAM2 PUBLIC_RAM_START UNINIT
{ {
* (.cy_sharedmem) * (.cy_sharedmem)
} }
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
{ {
} }
} }
; Emulated EEPROM Flash area ; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{ {
.cy_em_eeprom +0 .cy_em_eeprom +0
{ {
* (.cy_em_eeprom) * (.cy_em_eeprom)
} }
} }
; Supervisory flash: User data ; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{ {
.cy_sflash_user_data +0 .cy_sflash_user_data +0
{ {
* (.cy_sflash_user_data) * (.cy_sflash_user_data)
} }
} }
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{ {
.cy_sflash_nar +0 .cy_sflash_nar +0
{ {
* (.cy_sflash_nar) * (.cy_sflash_nar)
} }
} }
; Supervisory flash: Public Key ; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{ {
.cy_sflash_public_key +0 .cy_sflash_public_key +0
{ {
* (.cy_sflash_public_key) * (.cy_sflash_public_key)
} }
} }
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{ {
.cy_toc_part2 +0 .cy_toc_part2 +0
{ {
* (.cy_toc_part2) * (.cy_toc_part2)
} }
} }
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{ {
.cy_rtoc_part2 +0 .cy_rtoc_part2 +0
{ {
* (.cy_rtoc_part2) * (.cy_rtoc_part2)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
; eFuse ; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE LR_EFUSE EFUSE_START EFUSE_SIZE
{ {
.cy_efuse +0 .cy_efuse +0
{ {
* (.cy_efuse) * (.cy_efuse)
} }
} }
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. ; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000 CYMETA 0x90500000
{ {
.cymeta +0 { * (.cymeta) } .cymeta +0 { * (.cymeta) }
} }
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
#define __cy_memory_0_start 0x10000000 #define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x00100000 #define __cy_memory_0_length 0x00100000
#define __cy_memory_0_row_size 0x200 #define __cy_memory_0_row_size 0x200
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
#define __cy_memory_1_start 0x14000000 #define __cy_memory_1_start 0x14000000
#define __cy_memory_1_length 0x8000 #define __cy_memory_1_length 0x8000
#define __cy_memory_1_row_size 0x200 #define __cy_memory_1_row_size 0x200
/* Supervisory Flash */ /* Supervisory Flash */
#define __cy_memory_2_start 0x16000000 #define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000 #define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200 #define __cy_memory_2_row_size 0x200
/* XIP */ /* XIP */
#define __cy_memory_3_start 0x18000000 #define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000 #define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200 #define __cy_memory_3_row_size 0x200
/* eFuse */ /* eFuse */
#define __cy_memory_4_start 0x90700000 #define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000 #define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1 #define __cy_memory_4_row_size 1
/* [] END OF FILE */ /* [] END OF FILE */

622
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct
View File

@@ -1,311 +1,311 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cy8c6xxa_cm0plus.sct ;* \file cy8c6xxa_cm0plus.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
#if !defined(MBED_ROM_START) #if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x10000000 #define MBED_ROM_START 0x10000000
#endif #endif
;* MBED_APP_START is being used by the bootloader build script and ;* MBED_APP_START is being used by the bootloader build script and
;* will be calculate by the system. Without bootloader the MBED_APP_START ;* will be calculate by the system. Without bootloader the MBED_APP_START
;* is equal to MBED_ROM_START ;* is equal to MBED_ROM_START
;* ;*
#if !defined(MBED_APP_START) #if !defined(MBED_APP_START)
#define MBED_APP_START MBED_ROM_START #define MBED_APP_START MBED_ROM_START
#endif #endif
#if !defined(MBED_ROM_SIZE) #if !defined(MBED_ROM_SIZE)
#define MBED_ROM_SIZE 0x80000 #define MBED_ROM_SIZE 0x80000
#endif #endif
;* MBED_APP_SIZE is being used by the bootloader build script and ;* MBED_APP_SIZE is being used by the bootloader build script and
;* will be calculate by the system. Without bootloader the MBED_APP_SIZE ;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
;* is equal to MBED_ROM_SIZE ;* is equal to MBED_ROM_SIZE
;* ;*
#if !defined(MBED_APP_SIZE) #if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE MBED_ROM_SIZE #define MBED_APP_SIZE MBED_ROM_SIZE
#endif #endif
#if !defined(MBED_RAM_START) #if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x08000000 #define MBED_RAM_START 0x08000000
#endif #endif
#if !defined(MBED_RAM_SIZE) #if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x00010000 #define MBED_RAM_SIZE 0x00010000
#endif #endif
#if !defined(MBED_PUBLIC_RAM_SIZE) #if !defined(MBED_PUBLIC_RAM_SIZE)
#define MBED_PUBLIC_RAM_SIZE 0x200 #define MBED_PUBLIC_RAM_SIZE 0x200
#endif #endif
; The size of the stack section at the end of CM0+ SRAM ; The size of the stack section at the end of CM0+ SRAM
#if !defined(MBED_BOOT_STACK_SIZE) #if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400 #define MBED_BOOT_STACK_SIZE 0x400
#endif #endif
#define STACK_SIZE MBED_BOOT_STACK_SIZE #define STACK_SIZE MBED_BOOT_STACK_SIZE
#if !defined(MBED_PUBLIC_RAM_START) #if !defined(MBED_PUBLIC_RAM_START)
#define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)
#endif #endif
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM0+ core. ; The following defines control RAM and flash memory allocation for the CM0+ core.
; You can change the memory allocation by editing the RAM and Flash defines. ; You can change the memory allocation by editing the RAM and Flash defines.
; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. ; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior. ; Using this memory region for other purposes will lead to unexpected behavior.
; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', ; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. ; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
; RAM ; RAM
#define RAM_START MBED_RAM_START #define RAM_START MBED_RAM_START
#define RAM_SIZE MBED_RAM_SIZE #define RAM_SIZE MBED_RAM_SIZE
; Public RAM ; Public RAM
#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START #define PUBLIC_RAM_START MBED_PUBLIC_RAM_START
#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE #define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE
; Flash ; Flash
#define FLASH_START MBED_APP_START #define FLASH_START MBED_APP_START
#define FLASH_SIZE MBED_APP_SIZE #define FLASH_SIZE MBED_APP_SIZE
; The following defines describe a 32K flash region used for EEPROM emulation. ; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash. ; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores. ; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation. ; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000 #define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000 #define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data ; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800 #define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800 #define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00 #define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200 #define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key ; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00 #define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 #define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00 #define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200 #define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00 #define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200 #define SFLASH_RTOC_2_SIZE 0x00000200
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; eFuse ; eFuse
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Cortex-M0+ application flash area ; Cortex-M0+ application flash area
LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000) LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
{ {
.cy_app_header +0 .cy_app_header +0
{ {
* (.cy_app_header) * (.cy_app_header)
} }
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
RW_IRAM2 PUBLIC_RAM_START UNINIT RW_IRAM2 PUBLIC_RAM_START UNINIT
{ {
* (.cy_sharedmem) * (.cy_sharedmem)
} }
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
{ {
} }
} }
; Emulated EEPROM Flash area ; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{ {
.cy_em_eeprom +0 .cy_em_eeprom +0
{ {
* (.cy_em_eeprom) * (.cy_em_eeprom)
} }
} }
; Supervisory flash: User data ; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{ {
.cy_sflash_user_data +0 .cy_sflash_user_data +0
{ {
* (.cy_sflash_user_data) * (.cy_sflash_user_data)
} }
} }
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{ {
.cy_sflash_nar +0 .cy_sflash_nar +0
{ {
* (.cy_sflash_nar) * (.cy_sflash_nar)
} }
} }
; Supervisory flash: Public Key ; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{ {
.cy_sflash_public_key +0 .cy_sflash_public_key +0
{ {
* (.cy_sflash_public_key) * (.cy_sflash_public_key)
} }
} }
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{ {
.cy_toc_part2 +0 .cy_toc_part2 +0
{ {
* (.cy_toc_part2) * (.cy_toc_part2)
} }
} }
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{ {
.cy_rtoc_part2 +0 .cy_rtoc_part2 +0
{ {
* (.cy_rtoc_part2) * (.cy_rtoc_part2)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
; eFuse ; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE LR_EFUSE EFUSE_START EFUSE_SIZE
{ {
.cy_efuse +0 .cy_efuse +0
{ {
* (.cy_efuse) * (.cy_efuse)
} }
} }
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. ; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000 CYMETA 0x90500000
{ {
.cymeta +0 { * (.cymeta) } .cymeta +0 { * (.cymeta) }
} }
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
#define __cy_memory_0_start 0x10000000 #define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x00200000 #define __cy_memory_0_length 0x00200000
#define __cy_memory_0_row_size 0x200 #define __cy_memory_0_row_size 0x200
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
#define __cy_memory_1_start 0x14000000 #define __cy_memory_1_start 0x14000000
#define __cy_memory_1_length 0x8000 #define __cy_memory_1_length 0x8000
#define __cy_memory_1_row_size 0x200 #define __cy_memory_1_row_size 0x200
/* Supervisory Flash */ /* Supervisory Flash */
#define __cy_memory_2_start 0x16000000 #define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000 #define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200 #define __cy_memory_2_row_size 0x200
/* XIP */ /* XIP */
#define __cy_memory_3_start 0x18000000 #define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000 #define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200 #define __cy_memory_3_row_size 0x200
/* eFuse */ /* eFuse */
#define __cy_memory_4_start 0x90700000 #define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000 #define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1 #define __cy_memory_4_row_size 1
/* [] END OF FILE */ /* [] END OF FILE */

576
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx5_cm0plus.sct
View File

@@ -1,288 +1,288 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cyb06xx5_cm0plus.sct ;* \file cyb06xx5_cm0plus.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
#if !defined(MBED_ROM_START) #if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x10000000 #define MBED_ROM_START 0x10000000
#endif #endif
;* MBED_APP_START is being used by the bootloader build script and ;* MBED_APP_START is being used by the bootloader build script and
;* will be calculate by the system. Without bootloader the MBED_APP_START ;* will be calculate by the system. Without bootloader the MBED_APP_START
;* is equal to MBED_ROM_START ;* is equal to MBED_ROM_START
;* ;*
#if !defined(MBED_APP_START) #if !defined(MBED_APP_START)
#define MBED_APP_START MBED_ROM_START #define MBED_APP_START MBED_ROM_START
#endif #endif
#if !defined(MBED_ROM_SIZE) #if !defined(MBED_ROM_SIZE)
#define MBED_ROM_SIZE 0x00010000 #define MBED_ROM_SIZE 0x00010000
#endif #endif
;* MBED_APP_SIZE is being used by the bootloader build script and ;* MBED_APP_SIZE is being used by the bootloader build script and
;* will be calculate by the system. Without bootloader the MBED_APP_SIZE ;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
;* is equal to MBED_ROM_SIZE ;* is equal to MBED_ROM_SIZE
;* ;*
#if !defined(MBED_APP_SIZE) #if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE MBED_ROM_SIZE #define MBED_APP_SIZE MBED_ROM_SIZE
#endif #endif
#if !defined(MBED_RAM_START) #if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x08020000 #define MBED_RAM_START 0x08020000
#endif #endif
#if !defined(MBED_RAM_SIZE) #if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x0000C000 #define MBED_RAM_SIZE 0x0000C000
#endif #endif
#if !defined(MBED_PUBLIC_RAM_SIZE) #if !defined(MBED_PUBLIC_RAM_SIZE)
#define MBED_PUBLIC_RAM_SIZE 0x200 #define MBED_PUBLIC_RAM_SIZE 0x200
#endif #endif
; The size of the stack section at the end of CM0+ SRAM ; The size of the stack section at the end of CM0+ SRAM
#if !defined(MBED_BOOT_STACK_SIZE) #if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400 #define MBED_BOOT_STACK_SIZE 0x400
#endif #endif
#define STACK_SIZE MBED_BOOT_STACK_SIZE #define STACK_SIZE MBED_BOOT_STACK_SIZE
#if !defined(MBED_PUBLIC_RAM_START) #if !defined(MBED_PUBLIC_RAM_START)
#define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)
#endif #endif
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM0+ core. ; The following defines control RAM and flash memory allocation for the CM0+ core.
; You can change the memory allocation by editing the RAM and Flash defines. ; You can change the memory allocation by editing the RAM and Flash defines.
; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', ; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'. ; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'.
; RAM ; RAM
#define RAM_START MBED_RAM_START #define RAM_START MBED_RAM_START
#define RAM_SIZE MBED_RAM_SIZE #define RAM_SIZE MBED_RAM_SIZE
; Public RAM ; Public RAM
#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START #define PUBLIC_RAM_START MBED_PUBLIC_RAM_START
#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE #define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE
; Flash ; Flash
#define FLASH_START MBED_APP_START #define FLASH_START MBED_APP_START
#define FLASH_SIZE MBED_APP_SIZE #define FLASH_SIZE MBED_APP_SIZE
; The size of the MCU boot header area at the start of FLASH ; The size of the MCU boot header area at the start of FLASH
#define BOOT_HEADER_SIZE 0x00000400 #define BOOT_HEADER_SIZE 0x00000400
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data ; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800 #define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800 #define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00 #define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200 #define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key ; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00 #define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 #define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00 #define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200 #define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00 #define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200 #define SFLASH_RTOC_2_SIZE 0x00000200
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; eFuse ; eFuse
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Cortex-M0+ application flash area ; Cortex-M0+ application flash area
LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE - 0x8000) LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE - 0x8000)
{ {
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
RW_IRAM2 PUBLIC_RAM_START UNINIT RW_IRAM2 PUBLIC_RAM_START UNINIT
{ {
* (.cy_sharedmem) * (.cy_sharedmem)
} }
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
{ {
} }
} }
; Supervisory flash: User data ; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{ {
.cy_sflash_user_data +0 .cy_sflash_user_data +0
{ {
* (.cy_sflash_user_data) * (.cy_sflash_user_data)
} }
} }
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{ {
.cy_sflash_nar +0 .cy_sflash_nar +0
{ {
* (.cy_sflash_nar) * (.cy_sflash_nar)
} }
} }
; Supervisory flash: Public Key ; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{ {
.cy_sflash_public_key +0 .cy_sflash_public_key +0
{ {
* (.cy_sflash_public_key) * (.cy_sflash_public_key)
} }
} }
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{ {
.cy_toc_part2 +0 .cy_toc_part2 +0
{ {
* (.cy_toc_part2) * (.cy_toc_part2)
} }
} }
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{ {
.cy_rtoc_part2 +0 .cy_rtoc_part2 +0
{ {
* (.cy_rtoc_part2) * (.cy_rtoc_part2)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
; eFuse ; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE LR_EFUSE EFUSE_START EFUSE_SIZE
{ {
.cy_efuse +0 .cy_efuse +0
{ {
* (.cy_efuse) * (.cy_efuse)
} }
} }
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. ; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000 CYMETA 0x90500000
{ {
.cymeta +0 { * (.cymeta) } .cymeta +0 { * (.cymeta) }
} }
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
#define __cy_memory_0_start 0x10000000 #define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x00070000 #define __cy_memory_0_length 0x00070000
#define __cy_memory_0_row_size 0x200 #define __cy_memory_0_row_size 0x200
/* Supervisory Flash */ /* Supervisory Flash */
#define __cy_memory_2_start 0x16000000 #define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000 #define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200 #define __cy_memory_2_row_size 0x200
/* XIP */ /* XIP */
#define __cy_memory_3_start 0x18000000 #define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000 #define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200 #define __cy_memory_3_row_size 0x200
/* eFuse */ /* eFuse */
#define __cy_memory_4_start 0x90700000 #define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000 #define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1 #define __cy_memory_4_row_size 1
/* [] END OF FILE */ /* [] END OF FILE */

614
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct
View File

@@ -1,307 +1,307 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cyb06xx7_cm0plus.sct ;* \file cyb06xx7_cm0plus.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
#if !defined(MBED_ROM_START) #if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x10000000 #define MBED_ROM_START 0x10000000
#endif #endif
;* MBED_APP_START is being used by the bootloader build script and ;* MBED_APP_START is being used by the bootloader build script and
;* will be calculate by the system. Without bootloader the MBED_APP_START ;* will be calculate by the system. Without bootloader the MBED_APP_START
;* is equal to MBED_ROM_START ;* is equal to MBED_ROM_START
;* ;*
#if !defined(MBED_APP_START) #if !defined(MBED_APP_START)
#define MBED_APP_START MBED_ROM_START #define MBED_APP_START MBED_ROM_START
#endif #endif
#if !defined(MBED_ROM_SIZE) #if !defined(MBED_ROM_SIZE)
#define MBED_ROM_SIZE 0x00010000 #define MBED_ROM_SIZE 0x00010000
#endif #endif
;* MBED_APP_SIZE is being used by the bootloader build script and ;* MBED_APP_SIZE is being used by the bootloader build script and
;* will be calculate by the system. Without bootloader the MBED_APP_SIZE ;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
;* is equal to MBED_ROM_SIZE ;* is equal to MBED_ROM_SIZE
;* ;*
#if !defined(MBED_APP_SIZE) #if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE MBED_ROM_SIZE #define MBED_APP_SIZE MBED_ROM_SIZE
#endif #endif
#if !defined(MBED_RAM_START) #if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x08020000 #define MBED_RAM_START 0x08020000
#endif #endif
#if !defined(MBED_RAM_SIZE) #if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x0000C000 #define MBED_RAM_SIZE 0x0000C000
#endif #endif
#if !defined(MBED_PUBLIC_RAM_SIZE) #if !defined(MBED_PUBLIC_RAM_SIZE)
#define MBED_PUBLIC_RAM_SIZE 0x200 #define MBED_PUBLIC_RAM_SIZE 0x200
#endif #endif
; The size of the stack section at the end of CM0+ SRAM ; The size of the stack section at the end of CM0+ SRAM
#if !defined(MBED_BOOT_STACK_SIZE) #if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400 #define MBED_BOOT_STACK_SIZE 0x400
#endif #endif
#define STACK_SIZE MBED_BOOT_STACK_SIZE #define STACK_SIZE MBED_BOOT_STACK_SIZE
#if !defined(MBED_PUBLIC_RAM_START) #if !defined(MBED_PUBLIC_RAM_START)
#define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)
#endif #endif
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM0+ core. ; The following defines control RAM and flash memory allocation for the CM0+ core.
; You can change the memory allocation by editing the RAM and Flash defines. ; You can change the memory allocation by editing the RAM and Flash defines.
; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', ; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'. ; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'.
; RAM ; RAM
#define RAM_START MBED_RAM_START #define RAM_START MBED_RAM_START
#define RAM_SIZE MBED_RAM_SIZE #define RAM_SIZE MBED_RAM_SIZE
; Public RAM ; Public RAM
#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START #define PUBLIC_RAM_START MBED_PUBLIC_RAM_START
#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE #define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE
; Flash ; Flash
#define FLASH_START MBED_APP_START #define FLASH_START MBED_APP_START
#define FLASH_SIZE MBED_APP_SIZE #define FLASH_SIZE MBED_APP_SIZE
; The size of the MCU boot header area at the start of FLASH ; The size of the MCU boot header area at the start of FLASH
#define BOOT_HEADER_SIZE 0x00000400 #define BOOT_HEADER_SIZE 0x00000400
; The following defines describe a 32K flash region used for EEPROM emulation. ; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash. ; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores. ; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation. ; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000 #define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000 #define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data ; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800 #define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800 #define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00 #define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200 #define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key ; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00 #define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 #define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00 #define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200 #define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00 #define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200 #define SFLASH_RTOC_2_SIZE 0x00000200
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; eFuse ; eFuse
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Cortex-M0+ application flash area ; Cortex-M0+ application flash area
LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE - 0x8000) LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE - 0x8000)
{ {
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
RW_IRAM2 PUBLIC_RAM_START UNINIT RW_IRAM2 PUBLIC_RAM_START UNINIT
{ {
* (.cy_sharedmem) * (.cy_sharedmem)
} }
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
{ {
} }
} }
; Emulated EEPROM Flash area ; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{ {
.cy_em_eeprom +0 .cy_em_eeprom +0
{ {
* (.cy_em_eeprom) * (.cy_em_eeprom)
} }
} }
; Supervisory flash: User data ; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{ {
.cy_sflash_user_data +0 .cy_sflash_user_data +0
{ {
* (.cy_sflash_user_data) * (.cy_sflash_user_data)
} }
} }
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{ {
.cy_sflash_nar +0 .cy_sflash_nar +0
{ {
* (.cy_sflash_nar) * (.cy_sflash_nar)
} }
} }
; Supervisory flash: Public Key ; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{ {
.cy_sflash_public_key +0 .cy_sflash_public_key +0
{ {
* (.cy_sflash_public_key) * (.cy_sflash_public_key)
} }
} }
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{ {
.cy_toc_part2 +0 .cy_toc_part2 +0
{ {
* (.cy_toc_part2) * (.cy_toc_part2)
} }
} }
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{ {
.cy_rtoc_part2 +0 .cy_rtoc_part2 +0
{ {
* (.cy_rtoc_part2) * (.cy_rtoc_part2)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
; eFuse ; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE LR_EFUSE EFUSE_START EFUSE_SIZE
{ {
.cy_efuse +0 .cy_efuse +0
{ {
* (.cy_efuse) * (.cy_efuse)
} }
} }
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. ; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000 CYMETA 0x90500000
{ {
.cymeta +0 { * (.cymeta) } .cymeta +0 { * (.cymeta) }
} }
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
#define __cy_memory_0_start 0x10000000 #define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x000D0000 #define __cy_memory_0_length 0x000D0000
#define __cy_memory_0_row_size 0x200 #define __cy_memory_0_row_size 0x200
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
#define __cy_memory_1_start 0x14000000 #define __cy_memory_1_start 0x14000000
#define __cy_memory_1_length 0x8000 #define __cy_memory_1_length 0x8000
#define __cy_memory_1_row_size 0x200 #define __cy_memory_1_row_size 0x200
/* Supervisory Flash */ /* Supervisory Flash */
#define __cy_memory_2_start 0x16000000 #define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000 #define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200 #define __cy_memory_2_row_size 0x200
/* XIP */ /* XIP */
#define __cy_memory_3_start 0x18000000 #define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000 #define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200 #define __cy_memory_3_row_size 0x200
/* eFuse */ /* eFuse */
#define __cy_memory_4_start 0x90700000 #define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000 #define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1 #define __cy_memory_4_row_size 1
/* [] END OF FILE */ /* [] END OF FILE */

614
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct
View File

@@ -1,307 +1,307 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cyb06xxa_cm0plus.sct ;* \file cyb06xxa_cm0plus.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
#if !defined(MBED_ROM_START) #if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x10000000 #define MBED_ROM_START 0x10000000
#endif #endif
;* MBED_APP_START is being used by the bootloader build script and ;* MBED_APP_START is being used by the bootloader build script and
;* will be calculate by the system. Without bootloader the MBED_APP_START ;* will be calculate by the system. Without bootloader the MBED_APP_START
;* is equal to MBED_ROM_START ;* is equal to MBED_ROM_START
;* ;*
#if !defined(MBED_APP_START) #if !defined(MBED_APP_START)
#define MBED_APP_START MBED_ROM_START #define MBED_APP_START MBED_ROM_START
#endif #endif
#if !defined(MBED_ROM_SIZE) #if !defined(MBED_ROM_SIZE)
#define MBED_ROM_SIZE 0x00010000 #define MBED_ROM_SIZE 0x00010000
#endif #endif
;* MBED_APP_SIZE is being used by the bootloader build script and ;* MBED_APP_SIZE is being used by the bootloader build script and
;* will be calculate by the system. Without bootloader the MBED_APP_SIZE ;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
;* is equal to MBED_ROM_SIZE ;* is equal to MBED_ROM_SIZE
;* ;*
#if !defined(MBED_APP_SIZE) #if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE MBED_ROM_SIZE #define MBED_APP_SIZE MBED_ROM_SIZE
#endif #endif
#if !defined(MBED_RAM_START) #if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x080E0000 #define MBED_RAM_START 0x080E0000
#endif #endif
#if !defined(MBED_RAM_SIZE) #if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x0000C000 #define MBED_RAM_SIZE 0x0000C000
#endif #endif
#if !defined(MBED_PUBLIC_RAM_SIZE) #if !defined(MBED_PUBLIC_RAM_SIZE)
#define MBED_PUBLIC_RAM_SIZE 0x200 #define MBED_PUBLIC_RAM_SIZE 0x200
#endif #endif
; The size of the stack section at the end of CM0+ SRAM ; The size of the stack section at the end of CM0+ SRAM
#if !defined(MBED_BOOT_STACK_SIZE) #if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400 #define MBED_BOOT_STACK_SIZE 0x400
#endif #endif
#define STACK_SIZE MBED_BOOT_STACK_SIZE #define STACK_SIZE MBED_BOOT_STACK_SIZE
#if !defined(MBED_PUBLIC_RAM_START) #if !defined(MBED_PUBLIC_RAM_START)
#define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)
#endif #endif
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM0+ core. ; The following defines control RAM and flash memory allocation for the CM0+ core.
; You can change the memory allocation by editing the RAM and Flash defines. ; You can change the memory allocation by editing the RAM and Flash defines.
; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', ; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'. ; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'.
; RAM ; RAM
#define RAM_START MBED_RAM_START #define RAM_START MBED_RAM_START
#define RAM_SIZE MBED_RAM_SIZE #define RAM_SIZE MBED_RAM_SIZE
; Public RAM ; Public RAM
#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START #define PUBLIC_RAM_START MBED_PUBLIC_RAM_START
#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE #define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE
; Flash ; Flash
#define FLASH_START MBED_APP_START #define FLASH_START MBED_APP_START
#define FLASH_SIZE MBED_APP_SIZE #define FLASH_SIZE MBED_APP_SIZE
; The size of the MCU boot header area at the start of FLASH ; The size of the MCU boot header area at the start of FLASH
#define BOOT_HEADER_SIZE 0x00000400 #define BOOT_HEADER_SIZE 0x00000400
; The following defines describe a 32K flash region used for EEPROM emulation. ; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash. ; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores. ; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation. ; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000 #define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000 #define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data ; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800 #define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800 #define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00 #define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200 #define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key ; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00 #define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 #define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00 #define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200 #define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00 #define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200 #define SFLASH_RTOC_2_SIZE 0x00000200
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; eFuse ; eFuse
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Cortex-M0+ application flash area ; Cortex-M0+ application flash area
LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE - 0x8000) LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE - 0x8000)
{ {
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
RW_IRAM2 PUBLIC_RAM_START UNINIT RW_IRAM2 PUBLIC_RAM_START UNINIT
{ {
* (.cy_sharedmem) * (.cy_sharedmem)
} }
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
{ {
} }
} }
; Emulated EEPROM Flash area ; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{ {
.cy_em_eeprom +0 .cy_em_eeprom +0
{ {
* (.cy_em_eeprom) * (.cy_em_eeprom)
} }
} }
; Supervisory flash: User data ; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{ {
.cy_sflash_user_data +0 .cy_sflash_user_data +0
{ {
* (.cy_sflash_user_data) * (.cy_sflash_user_data)
} }
} }
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{ {
.cy_sflash_nar +0 .cy_sflash_nar +0
{ {
* (.cy_sflash_nar) * (.cy_sflash_nar)
} }
} }
; Supervisory flash: Public Key ; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{ {
.cy_sflash_public_key +0 .cy_sflash_public_key +0
{ {
* (.cy_sflash_public_key) * (.cy_sflash_public_key)
} }
} }
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{ {
.cy_toc_part2 +0 .cy_toc_part2 +0
{ {
* (.cy_toc_part2) * (.cy_toc_part2)
} }
} }
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{ {
.cy_rtoc_part2 +0 .cy_rtoc_part2 +0
{ {
* (.cy_rtoc_part2) * (.cy_rtoc_part2)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
; eFuse ; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE LR_EFUSE EFUSE_START EFUSE_SIZE
{ {
.cy_efuse +0 .cy_efuse +0
{ {
* (.cy_efuse) * (.cy_efuse)
} }
} }
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. ; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000 CYMETA 0x90500000
{ {
.cymeta +0 { * (.cymeta) } .cymeta +0 { * (.cymeta) }
} }
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
#define __cy_memory_0_start 0x10000000 #define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x001D0000 #define __cy_memory_0_length 0x001D0000
#define __cy_memory_0_row_size 0x200 #define __cy_memory_0_row_size 0x200
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
#define __cy_memory_1_start 0x14000000 #define __cy_memory_1_start 0x14000000
#define __cy_memory_1_length 0x8000 #define __cy_memory_1_length 0x8000
#define __cy_memory_1_row_size 0x200 #define __cy_memory_1_row_size 0x200
/* Supervisory Flash */ /* Supervisory Flash */
#define __cy_memory_2_start 0x16000000 #define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000 #define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200 #define __cy_memory_2_row_size 0x200
/* XIP */ /* XIP */
#define __cy_memory_3_start 0x18000000 #define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000 #define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200 #define __cy_memory_3_row_size 0x200
/* eFuse */ /* eFuse */
#define __cy_memory_4_start 0x90700000 #define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000 #define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1 #define __cy_memory_4_row_size 1
/* [] END OF FILE */ /* [] END OF FILE */

590
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx4_cm4_dual.sct
View File

@@ -1,295 +1,295 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cy8c6xx4_cm4_dual.sct ;* \file cy8c6xx4_cm4_dual.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. ; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
; More about CM0+ prebuilt images, see here: ; More about CM0+ prebuilt images, see here:
; https://github.com/cypresssemiconductorco/psoc6cm0p ; https://github.com/cypresssemiconductorco/psoc6cm0p
; The size of the Cortex-M0+ application flash image ; The size of the Cortex-M0+ application flash image
#define FLASH_CM0P_SIZE 0x2000 #define FLASH_CM0P_SIZE 0x2000
#if !defined(MBED_ROM_START) #if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x10000000 #define MBED_ROM_START 0x10000000
#endif #endif
;* MBED_APP_START is being used by the bootloader build script and ;* MBED_APP_START is being used by the bootloader build script and
;* will be calculate by the system. In case if MBED_APP_START address is ;* will be calculate by the system. In case if MBED_APP_START address is
;* customized by the bootloader config, the application image should not ;* customized by the bootloader config, the application image should not
;* include CM0p prebuilt image. ;* include CM0p prebuilt image.
;* ;*
#if !defined(MBED_APP_START) #if !defined(MBED_APP_START)
#define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE)
#endif #endif
#if !defined(MBED_ROM_SIZE) #if !defined(MBED_ROM_SIZE)
#define MBED_ROM_SIZE 0x00040000 #define MBED_ROM_SIZE 0x00040000
#endif #endif
;* MBED_APP_SIZE is being used by the bootloader build script and ;* MBED_APP_SIZE is being used by the bootloader build script and
;* will be calculate by the system. ;* will be calculate by the system.
;* ;*
#if !defined(MBED_APP_SIZE) #if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
#endif #endif
#if !defined(MBED_RAM_START) #if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x08002000 #define MBED_RAM_START 0x08002000
#endif #endif
#if !defined(MBED_RAM_SIZE) #if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x0001D800 #define MBED_RAM_SIZE 0x0001D800
#endif #endif
#if !defined(MBED_BOOT_STACK_SIZE) #if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400 #define MBED_BOOT_STACK_SIZE 0x400
#endif #endif
; The size of the stack section at the end of CM4 SRAM ; The size of the stack section at the end of CM4 SRAM
#define STACK_SIZE MBED_BOOT_STACK_SIZE #define STACK_SIZE MBED_BOOT_STACK_SIZE
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM4 core. ; The following defines control RAM and flash memory allocation for the CM4 core.
; You can change the memory allocation by editing RAM and Flash defines. ; You can change the memory allocation by editing RAM and Flash defines.
; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. ; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior. ; Using this memory region for other purposes will lead to unexpected behavior.
; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', ; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. ; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
; RAM ; RAM
#define RAM_START MBED_RAM_START #define RAM_START MBED_RAM_START
#define RAM_SIZE MBED_RAM_SIZE #define RAM_SIZE MBED_RAM_SIZE
; Flash ; Flash
#define FLASH_START MBED_APP_START #define FLASH_START MBED_APP_START
#define FLASH_SIZE MBED_APP_SIZE #define FLASH_SIZE MBED_APP_SIZE
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data ; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800 #define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800 #define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00 #define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200 #define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key ; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00 #define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 #define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00 #define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200 #define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00 #define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200 #define SFLASH_RTOC_2_SIZE 0x00000200
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; eFuse ; eFuse
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Cortex-M0+ application flash image area ; Cortex-M0+ application flash image area
LR_IROM MBED_ROM_START FLASH_CM0P_SIZE LR_IROM MBED_ROM_START FLASH_CM0P_SIZE
{ {
.cy_m0p_image +0 FLASH_CM0P_SIZE .cy_m0p_image +0 FLASH_CM0P_SIZE
{ {
* (.cy_m0p_image) * (.cy_m0p_image)
} }
} }
; Cortex-M4 application flash area ; Cortex-M4 application flash area
LR_IROM1 FLASH_START FLASH_SIZE LR_IROM1 FLASH_START FLASH_SIZE
{ {
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
{ {
} }
; Used for the digital signature of the secure application and the ; Used for the digital signature of the secure application and the
; Bootloader SDK application. The size of the section depends on the required ; Bootloader SDK application. The size of the section depends on the required
; data size. ; data size.
.cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256 .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
{ {
* (.cy_app_signature) * (.cy_app_signature)
} }
} }
; Supervisory flash: User data ; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{ {
.cy_sflash_user_data +0 .cy_sflash_user_data +0
{ {
* (.cy_sflash_user_data) * (.cy_sflash_user_data)
} }
} }
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{ {
.cy_sflash_nar +0 .cy_sflash_nar +0
{ {
* (.cy_sflash_nar) * (.cy_sflash_nar)
} }
} }
; Supervisory flash: Public Key ; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{ {
.cy_sflash_public_key +0 .cy_sflash_public_key +0
{ {
* (.cy_sflash_public_key) * (.cy_sflash_public_key)
} }
} }
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{ {
.cy_toc_part2 +0 .cy_toc_part2 +0
{ {
* (.cy_toc_part2) * (.cy_toc_part2)
} }
} }
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{ {
.cy_rtoc_part2 +0 .cy_rtoc_part2 +0
{ {
* (.cy_rtoc_part2) * (.cy_rtoc_part2)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
; eFuse ; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE LR_EFUSE EFUSE_START EFUSE_SIZE
{ {
.cy_efuse +0 .cy_efuse +0
{ {
* (.cy_efuse) * (.cy_efuse)
} }
} }
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. ; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000 CYMETA 0x90500000
{ {
.cymeta +0 { * (.cymeta) } .cymeta +0 { * (.cymeta) }
} }
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
#define __cy_memory_0_start 0x10000000 #define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x00040000 #define __cy_memory_0_length 0x00040000
#define __cy_memory_0_row_size 0x200 #define __cy_memory_0_row_size 0x200
/* Supervisory Flash */ /* Supervisory Flash */
#define __cy_memory_2_start 0x16000000 #define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000 #define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200 #define __cy_memory_2_row_size 0x200
/* XIP */ /* XIP */
#define __cy_memory_3_start 0x18000000 #define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000 #define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200 #define __cy_memory_3_row_size 0x200
/* eFuse */ /* eFuse */
#define __cy_memory_4_start 0x90700000 #define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000 #define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1 #define __cy_memory_4_row_size 1
/* [] END OF FILE */ /* [] END OF FILE */

628
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct
View File

@@ -1,314 +1,314 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cy8c6xx5_cm4_dual.sct ;* \file cy8c6xx5_cm4_dual.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. ; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
; More about CM0+ prebuilt images, see here: ; More about CM0+ prebuilt images, see here:
; https://github.com/cypresssemiconductorco/psoc6cm0p ; https://github.com/cypresssemiconductorco/psoc6cm0p
; The size of the Cortex-M0+ application flash image ; The size of the Cortex-M0+ application flash image
#define FLASH_CM0P_SIZE 0x2000 #define FLASH_CM0P_SIZE 0x2000
#if !defined(MBED_ROM_START) #if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x10000000 #define MBED_ROM_START 0x10000000
#endif #endif
;* MBED_APP_START is being used by the bootloader build script and ;* MBED_APP_START is being used by the bootloader build script and
;* will be calculate by the system. In case if MBED_APP_START address is ;* will be calculate by the system. In case if MBED_APP_START address is
;* customized by the bootloader config, the application image should not ;* customized by the bootloader config, the application image should not
;* include CM0p prebuilt image. ;* include CM0p prebuilt image.
;* ;*
#if !defined(MBED_APP_START) #if !defined(MBED_APP_START)
#define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE)
#endif #endif
#if !defined(MBED_ROM_SIZE) #if !defined(MBED_ROM_SIZE)
#define MBED_ROM_SIZE 0x00080000 #define MBED_ROM_SIZE 0x00080000
#endif #endif
;* MBED_APP_SIZE is being used by the bootloader build script and ;* MBED_APP_SIZE is being used by the bootloader build script and
;* will be calculate by the system. ;* will be calculate by the system.
;* ;*
#if !defined(MBED_APP_SIZE) #if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
#endif #endif
#if !defined(MBED_RAM_START) #if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x08002000 #define MBED_RAM_START 0x08002000
#endif #endif
#if !defined(MBED_RAM_SIZE) #if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x0003D800 #define MBED_RAM_SIZE 0x0003D800
#endif #endif
#if !defined(MBED_BOOT_STACK_SIZE) #if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400 #define MBED_BOOT_STACK_SIZE 0x400
#endif #endif
; The size of the stack section at the end of CM4 SRAM ; The size of the stack section at the end of CM4 SRAM
#define STACK_SIZE MBED_BOOT_STACK_SIZE #define STACK_SIZE MBED_BOOT_STACK_SIZE
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM4 core. ; The following defines control RAM and flash memory allocation for the CM4 core.
; You can change the memory allocation by editing RAM and Flash defines. ; You can change the memory allocation by editing RAM and Flash defines.
; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. ; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior. ; Using this memory region for other purposes will lead to unexpected behavior.
; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', ; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. ; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
; RAM ; RAM
#define RAM_START MBED_RAM_START #define RAM_START MBED_RAM_START
#define RAM_SIZE MBED_RAM_SIZE #define RAM_SIZE MBED_RAM_SIZE
; Flash ; Flash
#define FLASH_START MBED_APP_START #define FLASH_START MBED_APP_START
#define FLASH_SIZE MBED_APP_SIZE #define FLASH_SIZE MBED_APP_SIZE
; The following defines describe a 32K flash region used for EEPROM emulation. ; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash. ; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores. ; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation. ; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000 #define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000 #define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data ; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800 #define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800 #define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00 #define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200 #define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key ; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00 #define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 #define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00 #define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200 #define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00 #define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200 #define SFLASH_RTOC_2_SIZE 0x00000200
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; eFuse ; eFuse
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Cortex-M0+ application flash image area ; Cortex-M0+ application flash image area
LR_IROM MBED_ROM_START FLASH_CM0P_SIZE LR_IROM MBED_ROM_START FLASH_CM0P_SIZE
{ {
.cy_m0p_image +0 FLASH_CM0P_SIZE .cy_m0p_image +0 FLASH_CM0P_SIZE
{ {
* (.cy_m0p_image) * (.cy_m0p_image)
} }
} }
; Cortex-M4 application flash area ; Cortex-M4 application flash area
LR_IROM1 FLASH_START FLASH_SIZE LR_IROM1 FLASH_START FLASH_SIZE
{ {
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
{ {
} }
; Used for the digital signature of the secure application and the ; Used for the digital signature of the secure application and the
; Bootloader SDK application. The size of the section depends on the required ; Bootloader SDK application. The size of the section depends on the required
; data size. ; data size.
.cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256 .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
{ {
* (.cy_app_signature) * (.cy_app_signature)
} }
} }
; Emulated EEPROM Flash area ; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{ {
.cy_em_eeprom +0 .cy_em_eeprom +0
{ {
* (.cy_em_eeprom) * (.cy_em_eeprom)
} }
} }
; Supervisory flash: User data ; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{ {
.cy_sflash_user_data +0 .cy_sflash_user_data +0
{ {
* (.cy_sflash_user_data) * (.cy_sflash_user_data)
} }
} }
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{ {
.cy_sflash_nar +0 .cy_sflash_nar +0
{ {
* (.cy_sflash_nar) * (.cy_sflash_nar)
} }
} }
; Supervisory flash: Public Key ; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{ {
.cy_sflash_public_key +0 .cy_sflash_public_key +0
{ {
* (.cy_sflash_public_key) * (.cy_sflash_public_key)
} }
} }
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{ {
.cy_toc_part2 +0 .cy_toc_part2 +0
{ {
* (.cy_toc_part2) * (.cy_toc_part2)
} }
} }
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{ {
.cy_rtoc_part2 +0 .cy_rtoc_part2 +0
{ {
* (.cy_rtoc_part2) * (.cy_rtoc_part2)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
; eFuse ; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE LR_EFUSE EFUSE_START EFUSE_SIZE
{ {
.cy_efuse +0 .cy_efuse +0
{ {
* (.cy_efuse) * (.cy_efuse)
} }
} }
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. ; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000 CYMETA 0x90500000
{ {
.cymeta +0 { * (.cymeta) } .cymeta +0 { * (.cymeta) }
} }
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
#define __cy_memory_0_start 0x10000000 #define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x00080000 #define __cy_memory_0_length 0x00080000
#define __cy_memory_0_row_size 0x200 #define __cy_memory_0_row_size 0x200
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
#define __cy_memory_1_start 0x14000000 #define __cy_memory_1_start 0x14000000
#define __cy_memory_1_length 0x8000 #define __cy_memory_1_length 0x8000
#define __cy_memory_1_row_size 0x200 #define __cy_memory_1_row_size 0x200
/* Supervisory Flash */ /* Supervisory Flash */
#define __cy_memory_2_start 0x16000000 #define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000 #define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200 #define __cy_memory_2_row_size 0x200
/* XIP */ /* XIP */
#define __cy_memory_3_start 0x18000000 #define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000 #define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200 #define __cy_memory_3_row_size 0x200
/* eFuse */ /* eFuse */
#define __cy_memory_4_start 0x90700000 #define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000 #define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1 #define __cy_memory_4_row_size 1
/* [] END OF FILE */ /* [] END OF FILE */

628
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct
View File

@@ -1,314 +1,314 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cy8c6xx6_cm4_dual.sct ;* \file cy8c6xx6_cm4_dual.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. ; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
; More about CM0+ prebuilt images, see here: ; More about CM0+ prebuilt images, see here:
; https://github.com/cypresssemiconductorco/psoc6cm0p ; https://github.com/cypresssemiconductorco/psoc6cm0p
; The size of the Cortex-M0+ application flash image ; The size of the Cortex-M0+ application flash image
#define FLASH_CM0P_SIZE 0x2000 #define FLASH_CM0P_SIZE 0x2000
#if !defined(MBED_ROM_START) #if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x10000000 #define MBED_ROM_START 0x10000000
#endif #endif
;* MBED_APP_START is being used by the bootloader build script and ;* MBED_APP_START is being used by the bootloader build script and
;* will be calculate by the system. In case if MBED_APP_START address is ;* will be calculate by the system. In case if MBED_APP_START address is
;* customized by the bootloader config, the application image should not ;* customized by the bootloader config, the application image should not
;* include CM0p prebuilt image. ;* include CM0p prebuilt image.
;* ;*
#if !defined(MBED_APP_START) #if !defined(MBED_APP_START)
#define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE)
#endif #endif
#if !defined(MBED_ROM_SIZE) #if !defined(MBED_ROM_SIZE)
#define MBED_ROM_SIZE 0x00080000 #define MBED_ROM_SIZE 0x00080000
#endif #endif
;* MBED_APP_SIZE is being used by the bootloader build script and ;* MBED_APP_SIZE is being used by the bootloader build script and
;* will be calculate by the system. ;* will be calculate by the system.
;* ;*
#if !defined(MBED_APP_SIZE) #if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
#endif #endif
#if !defined(MBED_RAM_START) #if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x08002000 #define MBED_RAM_START 0x08002000
#endif #endif
#if !defined(MBED_RAM_SIZE) #if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x0001D800 #define MBED_RAM_SIZE 0x0001D800
#endif #endif
#if !defined(MBED_BOOT_STACK_SIZE) #if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400 #define MBED_BOOT_STACK_SIZE 0x400
#endif #endif
; The size of the stack section at the end of CM4 SRAM ; The size of the stack section at the end of CM4 SRAM
#define STACK_SIZE MBED_BOOT_STACK_SIZE #define STACK_SIZE MBED_BOOT_STACK_SIZE
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM4 core. ; The following defines control RAM and flash memory allocation for the CM4 core.
; You can change the memory allocation by editing RAM and Flash defines. ; You can change the memory allocation by editing RAM and Flash defines.
; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. ; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior. ; Using this memory region for other purposes will lead to unexpected behavior.
; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', ; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. ; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
; RAM ; RAM
#define RAM_START MBED_RAM_START #define RAM_START MBED_RAM_START
#define RAM_SIZE MBED_RAM_SIZE #define RAM_SIZE MBED_RAM_SIZE
; Flash ; Flash
#define FLASH_START MBED_APP_START #define FLASH_START MBED_APP_START
#define FLASH_SIZE MBED_APP_SIZE #define FLASH_SIZE MBED_APP_SIZE
; The following defines describe a 32K flash region used for EEPROM emulation. ; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash. ; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores. ; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation. ; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000 #define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000 #define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data ; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800 #define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800 #define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00 #define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200 #define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key ; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00 #define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 #define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00 #define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200 #define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00 #define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200 #define SFLASH_RTOC_2_SIZE 0x00000200
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; eFuse ; eFuse
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Cortex-M0+ application flash image area ; Cortex-M0+ application flash image area
LR_IROM MBED_ROM_START FLASH_CM0P_SIZE LR_IROM MBED_ROM_START FLASH_CM0P_SIZE
{ {
.cy_m0p_image +0 FLASH_CM0P_SIZE .cy_m0p_image +0 FLASH_CM0P_SIZE
{ {
* (.cy_m0p_image) * (.cy_m0p_image)
} }
} }
; Cortex-M4 application flash area ; Cortex-M4 application flash area
LR_IROM1 FLASH_START FLASH_SIZE LR_IROM1 FLASH_START FLASH_SIZE
{ {
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
{ {
} }
; Used for the digital signature of the secure application and the ; Used for the digital signature of the secure application and the
; Bootloader SDK application. The size of the section depends on the required ; Bootloader SDK application. The size of the section depends on the required
; data size. ; data size.
.cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256 .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
{ {
* (.cy_app_signature) * (.cy_app_signature)
} }
} }
; Emulated EEPROM Flash area ; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{ {
.cy_em_eeprom +0 .cy_em_eeprom +0
{ {
* (.cy_em_eeprom) * (.cy_em_eeprom)
} }
} }
; Supervisory flash: User data ; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{ {
.cy_sflash_user_data +0 .cy_sflash_user_data +0
{ {
* (.cy_sflash_user_data) * (.cy_sflash_user_data)
} }
} }
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{ {
.cy_sflash_nar +0 .cy_sflash_nar +0
{ {
* (.cy_sflash_nar) * (.cy_sflash_nar)
} }
} }
; Supervisory flash: Public Key ; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{ {
.cy_sflash_public_key +0 .cy_sflash_public_key +0
{ {
* (.cy_sflash_public_key) * (.cy_sflash_public_key)
} }
} }
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{ {
.cy_toc_part2 +0 .cy_toc_part2 +0
{ {
* (.cy_toc_part2) * (.cy_toc_part2)
} }
} }
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{ {
.cy_rtoc_part2 +0 .cy_rtoc_part2 +0
{ {
* (.cy_rtoc_part2) * (.cy_rtoc_part2)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
; eFuse ; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE LR_EFUSE EFUSE_START EFUSE_SIZE
{ {
.cy_efuse +0 .cy_efuse +0
{ {
* (.cy_efuse) * (.cy_efuse)
} }
} }
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. ; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000 CYMETA 0x90500000
{ {
.cymeta +0 { * (.cymeta) } .cymeta +0 { * (.cymeta) }
} }
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
#define __cy_memory_0_start 0x10000000 #define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x00080000 #define __cy_memory_0_length 0x00080000
#define __cy_memory_0_row_size 0x200 #define __cy_memory_0_row_size 0x200
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
#define __cy_memory_1_start 0x14000000 #define __cy_memory_1_start 0x14000000
#define __cy_memory_1_length 0x8000 #define __cy_memory_1_length 0x8000
#define __cy_memory_1_row_size 0x200 #define __cy_memory_1_row_size 0x200
/* Supervisory Flash */ /* Supervisory Flash */
#define __cy_memory_2_start 0x16000000 #define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000 #define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200 #define __cy_memory_2_row_size 0x200
/* XIP */ /* XIP */
#define __cy_memory_3_start 0x18000000 #define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000 #define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200 #define __cy_memory_3_row_size 0x200
/* eFuse */ /* eFuse */
#define __cy_memory_4_start 0x90700000 #define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000 #define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1 #define __cy_memory_4_row_size 1
/* [] END OF FILE */ /* [] END OF FILE */

628
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct
View File

@@ -1,314 +1,314 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cy8c6xx7_cm4_dual.sct ;* \file cy8c6xx7_cm4_dual.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. ; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
; More about CM0+ prebuilt images, see here: ; More about CM0+ prebuilt images, see here:
; https://github.com/cypresssemiconductorco/psoc6cm0p ; https://github.com/cypresssemiconductorco/psoc6cm0p
; The size of the Cortex-M0+ application flash image ; The size of the Cortex-M0+ application flash image
#define FLASH_CM0P_SIZE 0x2000 #define FLASH_CM0P_SIZE 0x2000
#if !defined(MBED_ROM_START) #if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x10000000 #define MBED_ROM_START 0x10000000
#endif #endif
;* MBED_APP_START is being used by the bootloader build script and ;* MBED_APP_START is being used by the bootloader build script and
;* will be calculate by the system. In case if MBED_APP_START address is ;* will be calculate by the system. In case if MBED_APP_START address is
;* customized by the bootloader config, the application image should not ;* customized by the bootloader config, the application image should not
;* include CM0p prebuilt image. ;* include CM0p prebuilt image.
;* ;*
#if !defined(MBED_APP_START) #if !defined(MBED_APP_START)
#define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE)
#endif #endif
#if !defined(MBED_ROM_SIZE) #if !defined(MBED_ROM_SIZE)
#define MBED_ROM_SIZE 0x00100000 #define MBED_ROM_SIZE 0x00100000
#endif #endif
;* MBED_APP_SIZE is being used by the bootloader build script and ;* MBED_APP_SIZE is being used by the bootloader build script and
;* will be calculate by the system. ;* will be calculate by the system.
;* ;*
#if !defined(MBED_APP_SIZE) #if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
#endif #endif
#if !defined(MBED_RAM_START) #if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x08002000 #define MBED_RAM_START 0x08002000
#endif #endif
#if !defined(MBED_RAM_SIZE) #if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x00045800 #define MBED_RAM_SIZE 0x00045800
#endif #endif
#if !defined(MBED_BOOT_STACK_SIZE) #if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400 #define MBED_BOOT_STACK_SIZE 0x400
#endif #endif
; The size of the stack section at the end of CM4 SRAM ; The size of the stack section at the end of CM4 SRAM
#define STACK_SIZE MBED_BOOT_STACK_SIZE #define STACK_SIZE MBED_BOOT_STACK_SIZE
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM4 core. ; The following defines control RAM and flash memory allocation for the CM4 core.
; You can change the memory allocation by editing RAM and Flash defines. ; You can change the memory allocation by editing RAM and Flash defines.
; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. ; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior. ; Using this memory region for other purposes will lead to unexpected behavior.
; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', ; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. ; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
; RAM ; RAM
#define RAM_START MBED_RAM_START #define RAM_START MBED_RAM_START
#define RAM_SIZE MBED_RAM_SIZE #define RAM_SIZE MBED_RAM_SIZE
; Flash ; Flash
#define FLASH_START MBED_APP_START #define FLASH_START MBED_APP_START
#define FLASH_SIZE MBED_APP_SIZE #define FLASH_SIZE MBED_APP_SIZE
; The following defines describe a 32K flash region used for EEPROM emulation. ; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash. ; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores. ; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation. ; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000 #define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000 #define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data ; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800 #define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800 #define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00 #define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200 #define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key ; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00 #define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 #define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00 #define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200 #define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00 #define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200 #define SFLASH_RTOC_2_SIZE 0x00000200
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; eFuse ; eFuse
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Cortex-M0+ application flash image area ; Cortex-M0+ application flash image area
LR_IROM MBED_ROM_START FLASH_CM0P_SIZE LR_IROM MBED_ROM_START FLASH_CM0P_SIZE
{ {
.cy_m0p_image +0 FLASH_CM0P_SIZE .cy_m0p_image +0 FLASH_CM0P_SIZE
{ {
* (.cy_m0p_image) * (.cy_m0p_image)
} }
} }
; Cortex-M4 application flash area ; Cortex-M4 application flash area
LR_IROM1 FLASH_START FLASH_SIZE LR_IROM1 FLASH_START FLASH_SIZE
{ {
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
{ {
} }
; Used for the digital signature of the secure application and the ; Used for the digital signature of the secure application and the
; Bootloader SDK application. The size of the section depends on the required ; Bootloader SDK application. The size of the section depends on the required
; data size. ; data size.
.cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256 .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
{ {
* (.cy_app_signature) * (.cy_app_signature)
} }
} }
; Emulated EEPROM Flash area ; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{ {
.cy_em_eeprom +0 .cy_em_eeprom +0
{ {
* (.cy_em_eeprom) * (.cy_em_eeprom)
} }
} }
; Supervisory flash: User data ; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{ {
.cy_sflash_user_data +0 .cy_sflash_user_data +0
{ {
* (.cy_sflash_user_data) * (.cy_sflash_user_data)
} }
} }
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{ {
.cy_sflash_nar +0 .cy_sflash_nar +0
{ {
* (.cy_sflash_nar) * (.cy_sflash_nar)
} }
} }
; Supervisory flash: Public Key ; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{ {
.cy_sflash_public_key +0 .cy_sflash_public_key +0
{ {
* (.cy_sflash_public_key) * (.cy_sflash_public_key)
} }
} }
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{ {
.cy_toc_part2 +0 .cy_toc_part2 +0
{ {
* (.cy_toc_part2) * (.cy_toc_part2)
} }
} }
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{ {
.cy_rtoc_part2 +0 .cy_rtoc_part2 +0
{ {
* (.cy_rtoc_part2) * (.cy_rtoc_part2)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
; eFuse ; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE LR_EFUSE EFUSE_START EFUSE_SIZE
{ {
.cy_efuse +0 .cy_efuse +0
{ {
* (.cy_efuse) * (.cy_efuse)
} }
} }
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. ; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000 CYMETA 0x90500000
{ {
.cymeta +0 { * (.cymeta) } .cymeta +0 { * (.cymeta) }
} }
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
#define __cy_memory_0_start 0x10000000 #define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x00100000 #define __cy_memory_0_length 0x00100000
#define __cy_memory_0_row_size 0x200 #define __cy_memory_0_row_size 0x200
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
#define __cy_memory_1_start 0x14000000 #define __cy_memory_1_start 0x14000000
#define __cy_memory_1_length 0x8000 #define __cy_memory_1_length 0x8000
#define __cy_memory_1_row_size 0x200 #define __cy_memory_1_row_size 0x200
/* Supervisory Flash */ /* Supervisory Flash */
#define __cy_memory_2_start 0x16000000 #define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000 #define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200 #define __cy_memory_2_row_size 0x200
/* XIP */ /* XIP */
#define __cy_memory_3_start 0x18000000 #define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000 #define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200 #define __cy_memory_3_row_size 0x200
/* eFuse */ /* eFuse */
#define __cy_memory_4_start 0x90700000 #define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000 #define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1 #define __cy_memory_4_row_size 1
/* [] END OF FILE */ /* [] END OF FILE */

628
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct
View File

@@ -1,314 +1,314 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cy8c6xx8_cm4_dual.sct ;* \file cy8c6xx8_cm4_dual.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. ; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
; More about CM0+ prebuilt images, see here: ; More about CM0+ prebuilt images, see here:
; https://github.com/cypresssemiconductorco/psoc6cm0p ; https://github.com/cypresssemiconductorco/psoc6cm0p
; The size of the Cortex-M0+ application flash image ; The size of the Cortex-M0+ application flash image
#define FLASH_CM0P_SIZE 0x2000 #define FLASH_CM0P_SIZE 0x2000
#if !defined(MBED_ROM_START) #if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x10000000 #define MBED_ROM_START 0x10000000
#endif #endif
;* MBED_APP_START is being used by the bootloader build script and ;* MBED_APP_START is being used by the bootloader build script and
;* will be calculate by the system. In case if MBED_APP_START address is ;* will be calculate by the system. In case if MBED_APP_START address is
;* customized by the bootloader config, the application image should not ;* customized by the bootloader config, the application image should not
;* include CM0p prebuilt image. ;* include CM0p prebuilt image.
;* ;*
#if !defined(MBED_APP_START) #if !defined(MBED_APP_START)
#define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE)
#endif #endif
#if !defined(MBED_ROM_SIZE) #if !defined(MBED_ROM_SIZE)
#define MBED_ROM_SIZE 0x00100000 #define MBED_ROM_SIZE 0x00100000
#endif #endif
;* MBED_APP_SIZE is being used by the bootloader build script and ;* MBED_APP_SIZE is being used by the bootloader build script and
;* will be calculate by the system. ;* will be calculate by the system.
;* ;*
#if !defined(MBED_APP_SIZE) #if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
#endif #endif
#if !defined(MBED_RAM_START) #if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x08002000 #define MBED_RAM_START 0x08002000
#endif #endif
#if !defined(MBED_RAM_SIZE) #if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x0007D800 #define MBED_RAM_SIZE 0x0007D800
#endif #endif
#if !defined(MBED_BOOT_STACK_SIZE) #if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400 #define MBED_BOOT_STACK_SIZE 0x400
#endif #endif
; The size of the stack section at the end of CM4 SRAM ; The size of the stack section at the end of CM4 SRAM
#define STACK_SIZE MBED_BOOT_STACK_SIZE #define STACK_SIZE MBED_BOOT_STACK_SIZE
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM4 core. ; The following defines control RAM and flash memory allocation for the CM4 core.
; You can change the memory allocation by editing RAM and Flash defines. ; You can change the memory allocation by editing RAM and Flash defines.
; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. ; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior. ; Using this memory region for other purposes will lead to unexpected behavior.
; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', ; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. ; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
; RAM ; RAM
#define RAM_START MBED_RAM_START #define RAM_START MBED_RAM_START
#define RAM_SIZE MBED_RAM_SIZE #define RAM_SIZE MBED_RAM_SIZE
; Flash ; Flash
#define FLASH_START MBED_APP_START #define FLASH_START MBED_APP_START
#define FLASH_SIZE MBED_APP_SIZE #define FLASH_SIZE MBED_APP_SIZE
; The following defines describe a 32K flash region used for EEPROM emulation. ; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash. ; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores. ; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation. ; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000 #define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000 #define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data ; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800 #define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800 #define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00 #define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200 #define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key ; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00 #define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 #define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00 #define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200 #define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00 #define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200 #define SFLASH_RTOC_2_SIZE 0x00000200
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; eFuse ; eFuse
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Cortex-M0+ application flash image area ; Cortex-M0+ application flash image area
LR_IROM MBED_ROM_START FLASH_CM0P_SIZE LR_IROM MBED_ROM_START FLASH_CM0P_SIZE
{ {
.cy_m0p_image +0 FLASH_CM0P_SIZE .cy_m0p_image +0 FLASH_CM0P_SIZE
{ {
* (.cy_m0p_image) * (.cy_m0p_image)
} }
} }
; Cortex-M4 application flash area ; Cortex-M4 application flash area
LR_IROM1 FLASH_START FLASH_SIZE LR_IROM1 FLASH_START FLASH_SIZE
{ {
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
{ {
} }
; Used for the digital signature of the secure application and the ; Used for the digital signature of the secure application and the
; Bootloader SDK application. The size of the section depends on the required ; Bootloader SDK application. The size of the section depends on the required
; data size. ; data size.
.cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256 .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
{ {
* (.cy_app_signature) * (.cy_app_signature)
} }
} }
; Emulated EEPROM Flash area ; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{ {
.cy_em_eeprom +0 .cy_em_eeprom +0
{ {
* (.cy_em_eeprom) * (.cy_em_eeprom)
} }
} }
; Supervisory flash: User data ; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{ {
.cy_sflash_user_data +0 .cy_sflash_user_data +0
{ {
* (.cy_sflash_user_data) * (.cy_sflash_user_data)
} }
} }
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{ {
.cy_sflash_nar +0 .cy_sflash_nar +0
{ {
* (.cy_sflash_nar) * (.cy_sflash_nar)
} }
} }
; Supervisory flash: Public Key ; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{ {
.cy_sflash_public_key +0 .cy_sflash_public_key +0
{ {
* (.cy_sflash_public_key) * (.cy_sflash_public_key)
} }
} }
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{ {
.cy_toc_part2 +0 .cy_toc_part2 +0
{ {
* (.cy_toc_part2) * (.cy_toc_part2)
} }
} }
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{ {
.cy_rtoc_part2 +0 .cy_rtoc_part2 +0
{ {
* (.cy_rtoc_part2) * (.cy_rtoc_part2)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
; eFuse ; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE LR_EFUSE EFUSE_START EFUSE_SIZE
{ {
.cy_efuse +0 .cy_efuse +0
{ {
* (.cy_efuse) * (.cy_efuse)
} }
} }
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. ; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000 CYMETA 0x90500000
{ {
.cymeta +0 { * (.cymeta) } .cymeta +0 { * (.cymeta) }
} }
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
#define __cy_memory_0_start 0x10000000 #define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x00100000 #define __cy_memory_0_length 0x00100000
#define __cy_memory_0_row_size 0x200 #define __cy_memory_0_row_size 0x200
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
#define __cy_memory_1_start 0x14000000 #define __cy_memory_1_start 0x14000000
#define __cy_memory_1_length 0x8000 #define __cy_memory_1_length 0x8000
#define __cy_memory_1_row_size 0x200 #define __cy_memory_1_row_size 0x200
/* Supervisory Flash */ /* Supervisory Flash */
#define __cy_memory_2_start 0x16000000 #define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000 #define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200 #define __cy_memory_2_row_size 0x200
/* XIP */ /* XIP */
#define __cy_memory_3_start 0x18000000 #define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000 #define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200 #define __cy_memory_3_row_size 0x200
/* eFuse */ /* eFuse */
#define __cy_memory_4_start 0x90700000 #define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000 #define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1 #define __cy_memory_4_row_size 1
/* [] END OF FILE */ /* [] END OF FILE */

628
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct
View File

@@ -1,314 +1,314 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cy8c6xxa_cm4_dual.sct ;* \file cy8c6xxa_cm4_dual.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. ; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
; More about CM0+ prebuilt images, see here: ; More about CM0+ prebuilt images, see here:
; https://github.com/cypresssemiconductorco/psoc6cm0p ; https://github.com/cypresssemiconductorco/psoc6cm0p
; The size of the Cortex-M0+ application flash image ; The size of the Cortex-M0+ application flash image
#define FLASH_CM0P_SIZE 0x2000 #define FLASH_CM0P_SIZE 0x2000
#if !defined(MBED_ROM_START) #if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x10000000 #define MBED_ROM_START 0x10000000
#endif #endif
;* MBED_APP_START is being used by the bootloader build script and ;* MBED_APP_START is being used by the bootloader build script and
;* will be calculate by the system. In case if MBED_APP_START address is ;* will be calculate by the system. In case if MBED_APP_START address is
;* customized by the bootloader config, the application image should not ;* customized by the bootloader config, the application image should not
;* include CM0p prebuilt image. ;* include CM0p prebuilt image.
;* ;*
#if !defined(MBED_APP_START) #if !defined(MBED_APP_START)
#define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE)
#endif #endif
#if !defined(MBED_ROM_SIZE) #if !defined(MBED_ROM_SIZE)
#define MBED_ROM_SIZE 0x00200000 #define MBED_ROM_SIZE 0x00200000
#endif #endif
;* MBED_APP_SIZE is being used by the bootloader build script and ;* MBED_APP_SIZE is being used by the bootloader build script and
;* will be calculate by the system. ;* will be calculate by the system.
;* ;*
#if !defined(MBED_APP_SIZE) #if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
#endif #endif
#if !defined(MBED_RAM_START) #if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x08002000 #define MBED_RAM_START 0x08002000
#endif #endif
#if !defined(MBED_RAM_SIZE) #if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x000FD800 #define MBED_RAM_SIZE 0x000FD800
#endif #endif
#if !defined(MBED_BOOT_STACK_SIZE) #if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400 #define MBED_BOOT_STACK_SIZE 0x400
#endif #endif
; The size of the stack section at the end of CM4 SRAM ; The size of the stack section at the end of CM4 SRAM
#define STACK_SIZE MBED_BOOT_STACK_SIZE #define STACK_SIZE MBED_BOOT_STACK_SIZE
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM4 core. ; The following defines control RAM and flash memory allocation for the CM4 core.
; You can change the memory allocation by editing RAM and Flash defines. ; You can change the memory allocation by editing RAM and Flash defines.
; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. ; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior. ; Using this memory region for other purposes will lead to unexpected behavior.
; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', ; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. ; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
; RAM ; RAM
#define RAM_START MBED_RAM_START #define RAM_START MBED_RAM_START
#define RAM_SIZE MBED_RAM_SIZE #define RAM_SIZE MBED_RAM_SIZE
; Flash ; Flash
#define FLASH_START MBED_APP_START #define FLASH_START MBED_APP_START
#define FLASH_SIZE MBED_APP_SIZE #define FLASH_SIZE MBED_APP_SIZE
; The following defines describe a 32K flash region used for EEPROM emulation. ; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash. ; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores. ; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation. ; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000 #define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000 #define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data ; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800 #define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800 #define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00 #define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200 #define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key ; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00 #define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 #define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00 #define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200 #define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00 #define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200 #define SFLASH_RTOC_2_SIZE 0x00000200
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; eFuse ; eFuse
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Cortex-M0+ application flash image area ; Cortex-M0+ application flash image area
LR_IROM MBED_ROM_START FLASH_CM0P_SIZE LR_IROM MBED_ROM_START FLASH_CM0P_SIZE
{ {
.cy_m0p_image +0 FLASH_CM0P_SIZE .cy_m0p_image +0 FLASH_CM0P_SIZE
{ {
* (.cy_m0p_image) * (.cy_m0p_image)
} }
} }
; Cortex-M4 application flash area ; Cortex-M4 application flash area
LR_IROM1 FLASH_START FLASH_SIZE LR_IROM1 FLASH_START FLASH_SIZE
{ {
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
{ {
} }
; Used for the digital signature of the secure application and the ; Used for the digital signature of the secure application and the
; Bootloader SDK application. The size of the section depends on the required ; Bootloader SDK application. The size of the section depends on the required
; data size. ; data size.
.cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256 .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
{ {
* (.cy_app_signature) * (.cy_app_signature)
} }
} }
; Emulated EEPROM Flash area ; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{ {
.cy_em_eeprom +0 .cy_em_eeprom +0
{ {
* (.cy_em_eeprom) * (.cy_em_eeprom)
} }
} }
; Supervisory flash: User data ; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{ {
.cy_sflash_user_data +0 .cy_sflash_user_data +0
{ {
* (.cy_sflash_user_data) * (.cy_sflash_user_data)
} }
} }
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{ {
.cy_sflash_nar +0 .cy_sflash_nar +0
{ {
* (.cy_sflash_nar) * (.cy_sflash_nar)
} }
} }
; Supervisory flash: Public Key ; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{ {
.cy_sflash_public_key +0 .cy_sflash_public_key +0
{ {
* (.cy_sflash_public_key) * (.cy_sflash_public_key)
} }
} }
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{ {
.cy_toc_part2 +0 .cy_toc_part2 +0
{ {
* (.cy_toc_part2) * (.cy_toc_part2)
} }
} }
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{ {
.cy_rtoc_part2 +0 .cy_rtoc_part2 +0
{ {
* (.cy_rtoc_part2) * (.cy_rtoc_part2)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
; eFuse ; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE LR_EFUSE EFUSE_START EFUSE_SIZE
{ {
.cy_efuse +0 .cy_efuse +0
{ {
* (.cy_efuse) * (.cy_efuse)
} }
} }
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. ; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000 CYMETA 0x90500000
{ {
.cymeta +0 { * (.cymeta) } .cymeta +0 { * (.cymeta) }
} }
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
#define __cy_memory_0_start 0x10000000 #define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x00200000 #define __cy_memory_0_length 0x00200000
#define __cy_memory_0_row_size 0x200 #define __cy_memory_0_row_size 0x200
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
#define __cy_memory_1_start 0x14000000 #define __cy_memory_1_start 0x14000000
#define __cy_memory_1_length 0x8000 #define __cy_memory_1_length 0x8000
#define __cy_memory_1_row_size 0x200 #define __cy_memory_1_row_size 0x200
/* Supervisory Flash */ /* Supervisory Flash */
#define __cy_memory_2_start 0x16000000 #define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000 #define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200 #define __cy_memory_2_row_size 0x200
/* XIP */ /* XIP */
#define __cy_memory_3_start 0x18000000 #define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000 #define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200 #define __cy_memory_3_row_size 0x200
/* eFuse */ /* eFuse */
#define __cy_memory_4_start 0x90700000 #define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000 #define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1 #define __cy_memory_4_row_size 1
/* [] END OF FILE */ /* [] END OF FILE */

596
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4_dual.sct
View File

@@ -1,298 +1,298 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cyb06xx5_cm4_dual.sct ;* \file cyb06xx5_cm4_dual.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. ; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
; More about CM0+ prebuilt images, see here: ; More about CM0+ prebuilt images, see here:
; https://github.com/cypresssemiconductorco/psoc6cm0p ; https://github.com/cypresssemiconductorco/psoc6cm0p
; The size of the Cortex-M0+ application flash image ; The size of the Cortex-M0+ application flash image
#define FLASH_CM0P_SIZE 0x10000 #define FLASH_CM0P_SIZE 0x10000
#if !defined(MBED_ROM_START) #if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x10000000 #define MBED_ROM_START 0x10000000
#endif #endif
;* MBED_APP_START is being used by the bootloader build script and ;* MBED_APP_START is being used by the bootloader build script and
;* will be calculate by the system. In case if MBED_APP_START address is ;* will be calculate by the system. In case if MBED_APP_START address is
;* customized by the bootloader config, the application image should not ;* customized by the bootloader config, the application image should not
;* include CM0p prebuilt image. ;* include CM0p prebuilt image.
;* ;*
#if !defined(MBED_APP_START) #if !defined(MBED_APP_START)
#define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE)
#endif #endif
; The size of the MCU boot header area at the start of FLASH ; The size of the MCU boot header area at the start of FLASH
#define BOOT_HEADER_SIZE 0x00000400 #define BOOT_HEADER_SIZE 0x00000400
#if !defined(MBED_ROM_SIZE) #if !defined(MBED_ROM_SIZE)
#define MBED_ROM_SIZE 0x00030000 #define MBED_ROM_SIZE 0x00030000
#endif #endif
;* MBED_APP_SIZE is being used by the bootloader build script and ;* MBED_APP_SIZE is being used by the bootloader build script and
;* will be calculate by the system. ;* will be calculate by the system.
;* ;*
#if !defined(MBED_APP_SIZE) #if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
#endif #endif
#if !defined(MBED_RAM_START) #if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x08000800 #define MBED_RAM_START 0x08000800
#endif #endif
#if !defined(MBED_RAM_SIZE) #if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x0001F800 #define MBED_RAM_SIZE 0x0001F800
#endif #endif
#if !defined(MBED_BOOT_STACK_SIZE) #if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400 #define MBED_BOOT_STACK_SIZE 0x400
#endif #endif
; The size of the stack section at the end of CM4 SRAM ; The size of the stack section at the end of CM4 SRAM
#define STACK_SIZE MBED_BOOT_STACK_SIZE #define STACK_SIZE MBED_BOOT_STACK_SIZE
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM4 core. ; The following defines control RAM and flash memory allocation for the CM4 core.
; You can change the memory allocation by editing RAM and Flash defines. ; You can change the memory allocation by editing RAM and Flash defines.
; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. ; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior. ; Using this memory region for other purposes will lead to unexpected behavior.
; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', ; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'. ; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'.
; RAM ; RAM
#define RAM_START MBED_RAM_START #define RAM_START MBED_RAM_START
#define RAM_SIZE MBED_RAM_SIZE #define RAM_SIZE MBED_RAM_SIZE
; Flash ; Flash
#define FLASH_START MBED_APP_START #define FLASH_START MBED_APP_START
#define FLASH_SIZE MBED_APP_SIZE #define FLASH_SIZE MBED_APP_SIZE
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data ; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800 #define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800 #define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00 #define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200 #define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key ; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00 #define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 #define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00 #define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200 #define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00 #define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200 #define SFLASH_RTOC_2_SIZE 0x00000200
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; eFuse ; eFuse
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Cortex-M0+ application flash image area ; Cortex-M0+ application flash image area
LR_IROM (MBED_ROM_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE) LR_IROM (MBED_ROM_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE)
{ {
.cy_m0p_image +0 FLASH_CM0P_SIZE .cy_m0p_image +0 FLASH_CM0P_SIZE
{ {
* (.cy_m0p_image) * (.cy_m0p_image)
} }
} }
; Cortex-M4 application flash area ; Cortex-M4 application flash area
LR_IROM1 FLASH_START FLASH_SIZE LR_IROM1 FLASH_START FLASH_SIZE
{ {
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
{ {
} }
; Used for the digital signature of the secure application and the ; Used for the digital signature of the secure application and the
; Bootloader SDK application. The size of the section depends on the required ; Bootloader SDK application. The size of the section depends on the required
; data size. ; data size.
.cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256 .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
{ {
* (.cy_app_signature) * (.cy_app_signature)
} }
} }
; Supervisory flash: User data ; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{ {
.cy_sflash_user_data +0 .cy_sflash_user_data +0
{ {
* (.cy_sflash_user_data) * (.cy_sflash_user_data)
} }
} }
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{ {
.cy_sflash_nar +0 .cy_sflash_nar +0
{ {
* (.cy_sflash_nar) * (.cy_sflash_nar)
} }
} }
; Supervisory flash: Public Key ; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{ {
.cy_sflash_public_key +0 .cy_sflash_public_key +0
{ {
* (.cy_sflash_public_key) * (.cy_sflash_public_key)
} }
} }
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{ {
.cy_toc_part2 +0 .cy_toc_part2 +0
{ {
* (.cy_toc_part2) * (.cy_toc_part2)
} }
} }
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{ {
.cy_rtoc_part2 +0 .cy_rtoc_part2 +0
{ {
* (.cy_rtoc_part2) * (.cy_rtoc_part2)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
; eFuse ; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE LR_EFUSE EFUSE_START EFUSE_SIZE
{ {
.cy_efuse +0 .cy_efuse +0
{ {
* (.cy_efuse) * (.cy_efuse)
} }
} }
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. ; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000 CYMETA 0x90500000
{ {
.cymeta +0 { * (.cymeta) } .cymeta +0 { * (.cymeta) }
} }
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
#define __cy_memory_0_start 0x10000000 #define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x00070000 #define __cy_memory_0_length 0x00070000
#define __cy_memory_0_row_size 0x200 #define __cy_memory_0_row_size 0x200
/* Supervisory Flash */ /* Supervisory Flash */
#define __cy_memory_2_start 0x16000000 #define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000 #define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200 #define __cy_memory_2_row_size 0x200
/* XIP */ /* XIP */
#define __cy_memory_3_start 0x18000000 #define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000 #define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200 #define __cy_memory_3_row_size 0x200
/* eFuse */ /* eFuse */
#define __cy_memory_4_start 0x90700000 #define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000 #define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1 #define __cy_memory_4_row_size 1
/* [] END OF FILE */ /* [] END OF FILE */

634
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct
View File

@@ -1,317 +1,317 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cyb06xx7_cm4_dual.sct ;* \file cyb06xx7_cm4_dual.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. ; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
; More about CM0+ prebuilt images, see here: ; More about CM0+ prebuilt images, see here:
; https://github.com/cypresssemiconductorco/psoc6cm0p ; https://github.com/cypresssemiconductorco/psoc6cm0p
; The size of the Cortex-M0+ application flash image ; The size of the Cortex-M0+ application flash image
#define FLASH_CM0P_SIZE 0x10000 #define FLASH_CM0P_SIZE 0x10000
#if !defined(MBED_ROM_START) #if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x10000000 #define MBED_ROM_START 0x10000000
#endif #endif
;* MBED_APP_START is being used by the bootloader build script and ;* MBED_APP_START is being used by the bootloader build script and
;* will be calculate by the system. In case if MBED_APP_START address is ;* will be calculate by the system. In case if MBED_APP_START address is
;* customized by the bootloader config, the application image should not ;* customized by the bootloader config, the application image should not
;* include CM0p prebuilt image. ;* include CM0p prebuilt image.
;* ;*
#if !defined(MBED_APP_START) #if !defined(MBED_APP_START)
#define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE)
#endif #endif
; The size of the MCU boot header area at the start of FLASH ; The size of the MCU boot header area at the start of FLASH
#define BOOT_HEADER_SIZE 0x00000400 #define BOOT_HEADER_SIZE 0x00000400
#if !defined(MBED_ROM_SIZE) #if !defined(MBED_ROM_SIZE)
#define MBED_ROM_SIZE 0x00068000 #define MBED_ROM_SIZE 0x00068000
#endif #endif
;* MBED_APP_SIZE is being used by the bootloader build script and ;* MBED_APP_SIZE is being used by the bootloader build script and
;* will be calculate by the system. ;* will be calculate by the system.
;* ;*
#if !defined(MBED_APP_SIZE) #if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
#endif #endif
#if !defined(MBED_RAM_START) #if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x08000800 #define MBED_RAM_START 0x08000800
#endif #endif
#if !defined(MBED_RAM_SIZE) #if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x0001F800 #define MBED_RAM_SIZE 0x0001F800
#endif #endif
#if !defined(MBED_BOOT_STACK_SIZE) #if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400 #define MBED_BOOT_STACK_SIZE 0x400
#endif #endif
; The size of the stack section at the end of CM4 SRAM ; The size of the stack section at the end of CM4 SRAM
#define STACK_SIZE MBED_BOOT_STACK_SIZE #define STACK_SIZE MBED_BOOT_STACK_SIZE
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM4 core. ; The following defines control RAM and flash memory allocation for the CM4 core.
; You can change the memory allocation by editing RAM and Flash defines. ; You can change the memory allocation by editing RAM and Flash defines.
; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. ; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior. ; Using this memory region for other purposes will lead to unexpected behavior.
; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', ; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'. ; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'.
; RAM ; RAM
#define RAM_START MBED_RAM_START #define RAM_START MBED_RAM_START
#define RAM_SIZE MBED_RAM_SIZE #define RAM_SIZE MBED_RAM_SIZE
; Flash ; Flash
#define FLASH_START MBED_APP_START #define FLASH_START MBED_APP_START
#define FLASH_SIZE MBED_APP_SIZE #define FLASH_SIZE MBED_APP_SIZE
; The following defines describe a 32K flash region used for EEPROM emulation. ; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash. ; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores. ; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation. ; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000 #define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000 #define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data ; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800 #define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800 #define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00 #define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200 #define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key ; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00 #define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 #define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00 #define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200 #define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00 #define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200 #define SFLASH_RTOC_2_SIZE 0x00000200
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; eFuse ; eFuse
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Cortex-M0+ application flash image area ; Cortex-M0+ application flash image area
LR_IROM (MBED_ROM_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE) LR_IROM (MBED_ROM_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE)
{ {
.cy_m0p_image +0 FLASH_CM0P_SIZE .cy_m0p_image +0 FLASH_CM0P_SIZE
{ {
* (.cy_m0p_image) * (.cy_m0p_image)
} }
} }
; Cortex-M4 application flash area ; Cortex-M4 application flash area
LR_IROM1 FLASH_START FLASH_SIZE LR_IROM1 FLASH_START FLASH_SIZE
{ {
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
{ {
} }
; Used for the digital signature of the secure application and the ; Used for the digital signature of the secure application and the
; Bootloader SDK application. The size of the section depends on the required ; Bootloader SDK application. The size of the section depends on the required
; data size. ; data size.
.cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256 .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
{ {
* (.cy_app_signature) * (.cy_app_signature)
} }
} }
; Emulated EEPROM Flash area ; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{ {
.cy_em_eeprom +0 .cy_em_eeprom +0
{ {
* (.cy_em_eeprom) * (.cy_em_eeprom)
} }
} }
; Supervisory flash: User data ; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{ {
.cy_sflash_user_data +0 .cy_sflash_user_data +0
{ {
* (.cy_sflash_user_data) * (.cy_sflash_user_data)
} }
} }
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{ {
.cy_sflash_nar +0 .cy_sflash_nar +0
{ {
* (.cy_sflash_nar) * (.cy_sflash_nar)
} }
} }
; Supervisory flash: Public Key ; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{ {
.cy_sflash_public_key +0 .cy_sflash_public_key +0
{ {
* (.cy_sflash_public_key) * (.cy_sflash_public_key)
} }
} }
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{ {
.cy_toc_part2 +0 .cy_toc_part2 +0
{ {
* (.cy_toc_part2) * (.cy_toc_part2)
} }
} }
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{ {
.cy_rtoc_part2 +0 .cy_rtoc_part2 +0
{ {
* (.cy_rtoc_part2) * (.cy_rtoc_part2)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
; eFuse ; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE LR_EFUSE EFUSE_START EFUSE_SIZE
{ {
.cy_efuse +0 .cy_efuse +0
{ {
* (.cy_efuse) * (.cy_efuse)
} }
} }
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. ; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000 CYMETA 0x90500000
{ {
.cymeta +0 { * (.cymeta) } .cymeta +0 { * (.cymeta) }
} }
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
#define __cy_memory_0_start 0x10000000 #define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x000D0000 #define __cy_memory_0_length 0x000D0000
#define __cy_memory_0_row_size 0x200 #define __cy_memory_0_row_size 0x200
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
#define __cy_memory_1_start 0x14000000 #define __cy_memory_1_start 0x14000000
#define __cy_memory_1_length 0x8000 #define __cy_memory_1_length 0x8000
#define __cy_memory_1_row_size 0x200 #define __cy_memory_1_row_size 0x200
/* Supervisory Flash */ /* Supervisory Flash */
#define __cy_memory_2_start 0x16000000 #define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000 #define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200 #define __cy_memory_2_row_size 0x200
/* XIP */ /* XIP */
#define __cy_memory_3_start 0x18000000 #define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000 #define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200 #define __cy_memory_3_row_size 0x200
/* eFuse */ /* eFuse */
#define __cy_memory_4_start 0x90700000 #define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000 #define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1 #define __cy_memory_4_row_size 1
/* [] END OF FILE */ /* [] END OF FILE */

634
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct
View File

@@ -1,317 +1,317 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cyb06xxa_cm4_dual.sct ;* \file cyb06xxa_cm4_dual.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. ; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
; More about CM0+ prebuilt images, see here: ; More about CM0+ prebuilt images, see here:
; https://github.com/cypresssemiconductorco/psoc6cm0p ; https://github.com/cypresssemiconductorco/psoc6cm0p
; The size of the Cortex-M0+ application flash image ; The size of the Cortex-M0+ application flash image
#define FLASH_CM0P_SIZE 0x10000 #define FLASH_CM0P_SIZE 0x10000
#if !defined(MBED_ROM_START) #if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x10000000 #define MBED_ROM_START 0x10000000
#endif #endif
;* MBED_APP_START is being used by the bootloader build script and ;* MBED_APP_START is being used by the bootloader build script and
;* will be calculate by the system. In case if MBED_APP_START address is ;* will be calculate by the system. In case if MBED_APP_START address is
;* customized by the bootloader config, the application image should not ;* customized by the bootloader config, the application image should not
;* include CM0p prebuilt image. ;* include CM0p prebuilt image.
;* ;*
#if !defined(MBED_APP_START) #if !defined(MBED_APP_START)
#define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE)
#endif #endif
; The size of the MCU boot header area at the start of FLASH ; The size of the MCU boot header area at the start of FLASH
#define BOOT_HEADER_SIZE 0x00000400 #define BOOT_HEADER_SIZE 0x00000400
#if !defined(MBED_ROM_SIZE) #if !defined(MBED_ROM_SIZE)
#define MBED_ROM_SIZE 0x000E0000 #define MBED_ROM_SIZE 0x000E0000
#endif #endif
;* MBED_APP_SIZE is being used by the bootloader build script and ;* MBED_APP_SIZE is being used by the bootloader build script and
;* will be calculate by the system. ;* will be calculate by the system.
;* ;*
#if !defined(MBED_APP_SIZE) #if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
#endif #endif
#if !defined(MBED_RAM_START) #if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x08000800 #define MBED_RAM_START 0x08000800
#endif #endif
#if !defined(MBED_RAM_SIZE) #if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x000DF800 #define MBED_RAM_SIZE 0x000DF800
#endif #endif
#if !defined(MBED_BOOT_STACK_SIZE) #if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400 #define MBED_BOOT_STACK_SIZE 0x400
#endif #endif
; The size of the stack section at the end of CM4 SRAM ; The size of the stack section at the end of CM4 SRAM
#define STACK_SIZE MBED_BOOT_STACK_SIZE #define STACK_SIZE MBED_BOOT_STACK_SIZE
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM4 core. ; The following defines control RAM and flash memory allocation for the CM4 core.
; You can change the memory allocation by editing RAM and Flash defines. ; You can change the memory allocation by editing RAM and Flash defines.
; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. ; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior. ; Using this memory region for other purposes will lead to unexpected behavior.
; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', ; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'. ; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'.
; RAM ; RAM
#define RAM_START MBED_RAM_START #define RAM_START MBED_RAM_START
#define RAM_SIZE MBED_RAM_SIZE #define RAM_SIZE MBED_RAM_SIZE
; Flash ; Flash
#define FLASH_START MBED_APP_START #define FLASH_START MBED_APP_START
#define FLASH_SIZE MBED_APP_SIZE #define FLASH_SIZE MBED_APP_SIZE
; The following defines describe a 32K flash region used for EEPROM emulation. ; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash. ; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores. ; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation. ; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000 #define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000 #define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data ; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800 #define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800 #define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00 #define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200 #define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key ; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00 #define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 #define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00 #define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200 #define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00 #define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200 #define SFLASH_RTOC_2_SIZE 0x00000200
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; eFuse ; eFuse
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Cortex-M0+ application flash image area ; Cortex-M0+ application flash image area
LR_IROM (MBED_ROM_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE) LR_IROM (MBED_ROM_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE)
{ {
.cy_m0p_image +0 FLASH_CM0P_SIZE .cy_m0p_image +0 FLASH_CM0P_SIZE
{ {
* (.cy_m0p_image) * (.cy_m0p_image)
} }
} }
; Cortex-M4 application flash area ; Cortex-M4 application flash area
LR_IROM1 FLASH_START FLASH_SIZE LR_IROM1 FLASH_START FLASH_SIZE
{ {
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
{ {
} }
; Used for the digital signature of the secure application and the ; Used for the digital signature of the secure application and the
; Bootloader SDK application. The size of the section depends on the required ; Bootloader SDK application. The size of the section depends on the required
; data size. ; data size.
.cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256 .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
{ {
* (.cy_app_signature) * (.cy_app_signature)
} }
} }
; Emulated EEPROM Flash area ; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{ {
.cy_em_eeprom +0 .cy_em_eeprom +0
{ {
* (.cy_em_eeprom) * (.cy_em_eeprom)
} }
} }
; Supervisory flash: User data ; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{ {
.cy_sflash_user_data +0 .cy_sflash_user_data +0
{ {
* (.cy_sflash_user_data) * (.cy_sflash_user_data)
} }
} }
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{ {
.cy_sflash_nar +0 .cy_sflash_nar +0
{ {
* (.cy_sflash_nar) * (.cy_sflash_nar)
} }
} }
; Supervisory flash: Public Key ; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{ {
.cy_sflash_public_key +0 .cy_sflash_public_key +0
{ {
* (.cy_sflash_public_key) * (.cy_sflash_public_key)
} }
} }
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{ {
.cy_toc_part2 +0 .cy_toc_part2 +0
{ {
* (.cy_toc_part2) * (.cy_toc_part2)
} }
} }
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{ {
.cy_rtoc_part2 +0 .cy_rtoc_part2 +0
{ {
* (.cy_rtoc_part2) * (.cy_rtoc_part2)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
; eFuse ; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE LR_EFUSE EFUSE_START EFUSE_SIZE
{ {
.cy_efuse +0 .cy_efuse +0
{ {
* (.cy_efuse) * (.cy_efuse)
} }
} }
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. ; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000 CYMETA 0x90500000
{ {
.cymeta +0 { * (.cymeta) } .cymeta +0 { * (.cymeta) }
} }
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
#define __cy_memory_0_start 0x10000000 #define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x001D0000 #define __cy_memory_0_length 0x001D0000
#define __cy_memory_0_row_size 0x200 #define __cy_memory_0_row_size 0x200
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
#define __cy_memory_1_start 0x14000000 #define __cy_memory_1_start 0x14000000
#define __cy_memory_1_length 0x8000 #define __cy_memory_1_length 0x8000
#define __cy_memory_1_row_size 0x200 #define __cy_memory_1_row_size 0x200
/* Supervisory Flash */ /* Supervisory Flash */
#define __cy_memory_2_start 0x16000000 #define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000 #define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200 #define __cy_memory_2_row_size 0x200
/* XIP */ /* XIP */
#define __cy_memory_3_start 0x18000000 #define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000 #define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200 #define __cy_memory_3_row_size 0x200
/* eFuse */ /* eFuse */
#define __cy_memory_4_start 0x90700000 #define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000 #define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1 #define __cy_memory_4_row_size 1
/* [] END OF FILE */ /* [] END OF FILE */

506
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx4_cm0plus.sct
View File

@@ -1,253 +1,253 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cy8c6xx4_cm0plus.sct ;* \file cy8c6xx4_cm0plus.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM0+ core. ; The following defines control RAM and flash memory allocation for the CM0+ core.
; You can change the memory allocation by editing the RAM and Flash defines. ; You can change the memory allocation by editing the RAM and Flash defines.
; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. ; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior. ; Using this memory region for other purposes will lead to unexpected behavior.
; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', ; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. ; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
; RAM ; RAM
#define RAM_START 0x08000000 #define RAM_START 0x08000000
#define RAM_SIZE 0x00002000 #define RAM_SIZE 0x00002000
; Flash ; Flash
#define FLASH_START 0x10000000 #define FLASH_START 0x10000000
#define FLASH_SIZE 0x00002000 #define FLASH_SIZE 0x00002000
; The size of the stack section at the end of CM0+ SRAM ; The size of the stack section at the end of CM0+ SRAM
#define STACK_SIZE 0x00001000 #define STACK_SIZE 0x00001000
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data ; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800 #define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800 #define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00 #define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200 #define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key ; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00 #define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 #define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00 #define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200 #define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00 #define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200 #define SFLASH_RTOC_2_SIZE 0x00000200
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; eFuse ; eFuse
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Public RAM ; Public RAM
; This is an unprotected public RAM region, with the placed .cy_sharedmem section. ; This is an unprotected public RAM region, with the placed .cy_sharedmem section.
; This region is used to place objects that require full access from both cores. ; This region is used to place objects that require full access from both cores.
; Uncomment the following lines, define the region size and uncomment placement of ; Uncomment the following lines, define the region size and uncomment placement of
; .cy_sharedmem section below. ; .cy_sharedmem section below.
; #define PUBLIC_RAM_SIZE %REGION_SIZE% ; #define PUBLIC_RAM_SIZE %REGION_SIZE%
; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE) ; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
; Cortex-M0+ application flash area ; Cortex-M0+ application flash area
LR_IROM1 FLASH_START FLASH_SIZE LR_IROM1 FLASH_START FLASH_SIZE
{ {
.cy_app_header +0 .cy_app_header +0
{ {
* (.cy_app_header) * (.cy_app_header)
} }
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address. ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address.
;RW_IRAM2 PUBLIC_RAM_START UNINIT ;RW_IRAM2 PUBLIC_RAM_START UNINIT
;{ ;{
; * (.cy_sharedmem) ; * (.cy_sharedmem)
;} ;}
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
{ {
} }
} }
; Supervisory flash: User data ; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{ {
.cy_sflash_user_data +0 .cy_sflash_user_data +0
{ {
* (.cy_sflash_user_data) * (.cy_sflash_user_data)
} }
} }
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{ {
.cy_sflash_nar +0 .cy_sflash_nar +0
{ {
* (.cy_sflash_nar) * (.cy_sflash_nar)
} }
} }
; Supervisory flash: Public Key ; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{ {
.cy_sflash_public_key +0 .cy_sflash_public_key +0
{ {
* (.cy_sflash_public_key) * (.cy_sflash_public_key)
} }
} }
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{ {
.cy_toc_part2 +0 .cy_toc_part2 +0
{ {
* (.cy_toc_part2) * (.cy_toc_part2)
} }
} }
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{ {
.cy_rtoc_part2 +0 .cy_rtoc_part2 +0
{ {
* (.cy_rtoc_part2) * (.cy_rtoc_part2)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
; eFuse ; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE LR_EFUSE EFUSE_START EFUSE_SIZE
{ {
.cy_efuse +0 .cy_efuse +0
{ {
* (.cy_efuse) * (.cy_efuse)
} }
} }
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. ; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000 CYMETA 0x90500000
{ {
.cymeta +0 { * (.cymeta) } .cymeta +0 { * (.cymeta) }
} }
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
#define __cy_memory_0_start 0x10000000 #define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x00040000 #define __cy_memory_0_length 0x00040000
#define __cy_memory_0_row_size 0x200 #define __cy_memory_0_row_size 0x200
/* Supervisory Flash */ /* Supervisory Flash */
#define __cy_memory_2_start 0x16000000 #define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000 #define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200 #define __cy_memory_2_row_size 0x200
/* XIP */ /* XIP */
#define __cy_memory_3_start 0x18000000 #define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000 #define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200 #define __cy_memory_3_row_size 0x200
/* eFuse */ /* eFuse */
#define __cy_memory_4_start 0x90700000 #define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000 #define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1 #define __cy_memory_4_row_size 1
/* [] END OF FILE */ /* [] END OF FILE */

544
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct
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@@ -1,272 +1,272 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cy8c6xx5_cm0plus.sct ;* \file cy8c6xx5_cm0plus.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM0+ core. ; The following defines control RAM and flash memory allocation for the CM0+ core.
; You can change the memory allocation by editing the RAM and Flash defines. ; You can change the memory allocation by editing the RAM and Flash defines.
; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. ; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior. ; Using this memory region for other purposes will lead to unexpected behavior.
; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', ; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. ; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
; RAM ; RAM
#define RAM_START 0x08000000 #define RAM_START 0x08000000
#define RAM_SIZE 0x00002000 #define RAM_SIZE 0x00002000
; Flash ; Flash
#define FLASH_START 0x10000000 #define FLASH_START 0x10000000
#define FLASH_SIZE 0x00002000 #define FLASH_SIZE 0x00002000
; The size of the stack section at the end of CM0+ SRAM ; The size of the stack section at the end of CM0+ SRAM
#define STACK_SIZE 0x00001000 #define STACK_SIZE 0x00001000
; The following defines describe a 32K flash region used for EEPROM emulation. ; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash. ; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores. ; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation. ; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000 #define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000 #define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data ; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800 #define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800 #define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00 #define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200 #define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key ; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00 #define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 #define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00 #define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200 #define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00 #define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200 #define SFLASH_RTOC_2_SIZE 0x00000200
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; eFuse ; eFuse
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Public RAM ; Public RAM
; This is an unprotected public RAM region, with the placed .cy_sharedmem section. ; This is an unprotected public RAM region, with the placed .cy_sharedmem section.
; This region is used to place objects that require full access from both cores. ; This region is used to place objects that require full access from both cores.
; Uncomment the following lines, define the region size and uncomment placement of ; Uncomment the following lines, define the region size and uncomment placement of
; .cy_sharedmem section below. ; .cy_sharedmem section below.
; #define PUBLIC_RAM_SIZE %REGION_SIZE% ; #define PUBLIC_RAM_SIZE %REGION_SIZE%
; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE) ; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
; Cortex-M0+ application flash area ; Cortex-M0+ application flash area
LR_IROM1 FLASH_START FLASH_SIZE LR_IROM1 FLASH_START FLASH_SIZE
{ {
.cy_app_header +0 .cy_app_header +0
{ {
* (.cy_app_header) * (.cy_app_header)
} }
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address. ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address.
;RW_IRAM2 PUBLIC_RAM_START UNINIT ;RW_IRAM2 PUBLIC_RAM_START UNINIT
;{ ;{
; * (.cy_sharedmem) ; * (.cy_sharedmem)
;} ;}
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
{ {
} }
} }
; Emulated EEPROM Flash area ; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{ {
.cy_em_eeprom +0 .cy_em_eeprom +0
{ {
* (.cy_em_eeprom) * (.cy_em_eeprom)
} }
} }
; Supervisory flash: User data ; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{ {
.cy_sflash_user_data +0 .cy_sflash_user_data +0
{ {
* (.cy_sflash_user_data) * (.cy_sflash_user_data)
} }
} }
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{ {
.cy_sflash_nar +0 .cy_sflash_nar +0
{ {
* (.cy_sflash_nar) * (.cy_sflash_nar)
} }
} }
; Supervisory flash: Public Key ; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{ {
.cy_sflash_public_key +0 .cy_sflash_public_key +0
{ {
* (.cy_sflash_public_key) * (.cy_sflash_public_key)
} }
} }
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{ {
.cy_toc_part2 +0 .cy_toc_part2 +0
{ {
* (.cy_toc_part2) * (.cy_toc_part2)
} }
} }
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{ {
.cy_rtoc_part2 +0 .cy_rtoc_part2 +0
{ {
* (.cy_rtoc_part2) * (.cy_rtoc_part2)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
; eFuse ; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE LR_EFUSE EFUSE_START EFUSE_SIZE
{ {
.cy_efuse +0 .cy_efuse +0
{ {
* (.cy_efuse) * (.cy_efuse)
} }
} }
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. ; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000 CYMETA 0x90500000
{ {
.cymeta +0 { * (.cymeta) } .cymeta +0 { * (.cymeta) }
} }
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
#define __cy_memory_0_start 0x10000000 #define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x00080000 #define __cy_memory_0_length 0x00080000
#define __cy_memory_0_row_size 0x200 #define __cy_memory_0_row_size 0x200
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
#define __cy_memory_1_start 0x14000000 #define __cy_memory_1_start 0x14000000
#define __cy_memory_1_length 0x8000 #define __cy_memory_1_length 0x8000
#define __cy_memory_1_row_size 0x200 #define __cy_memory_1_row_size 0x200
/* Supervisory Flash */ /* Supervisory Flash */
#define __cy_memory_2_start 0x16000000 #define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000 #define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200 #define __cy_memory_2_row_size 0x200
/* XIP */ /* XIP */
#define __cy_memory_3_start 0x18000000 #define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000 #define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200 #define __cy_memory_3_row_size 0x200
/* eFuse */ /* eFuse */
#define __cy_memory_4_start 0x90700000 #define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000 #define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1 #define __cy_memory_4_row_size 1
/* [] END OF FILE */ /* [] END OF FILE */

544
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct
View File

@@ -1,272 +1,272 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cy8c6xx6_cm0plus.sct ;* \file cy8c6xx6_cm0plus.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM0+ core. ; The following defines control RAM and flash memory allocation for the CM0+ core.
; You can change the memory allocation by editing the RAM and Flash defines. ; You can change the memory allocation by editing the RAM and Flash defines.
; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. ; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior. ; Using this memory region for other purposes will lead to unexpected behavior.
; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', ; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. ; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
; RAM ; RAM
#define RAM_START 0x08000000 #define RAM_START 0x08000000
#define RAM_SIZE 0x00002000 #define RAM_SIZE 0x00002000
; Flash ; Flash
#define FLASH_START 0x10000000 #define FLASH_START 0x10000000
#define FLASH_SIZE 0x00002000 #define FLASH_SIZE 0x00002000
; The size of the stack section at the end of CM0+ SRAM ; The size of the stack section at the end of CM0+ SRAM
#define STACK_SIZE 0x00001000 #define STACK_SIZE 0x00001000
; The following defines describe a 32K flash region used for EEPROM emulation. ; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash. ; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores. ; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation. ; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000 #define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000 #define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data ; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800 #define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800 #define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00 #define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200 #define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key ; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00 #define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 #define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00 #define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200 #define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00 #define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200 #define SFLASH_RTOC_2_SIZE 0x00000200
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; eFuse ; eFuse
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Public RAM ; Public RAM
; This is an unprotected public RAM region, with the placed .cy_sharedmem section. ; This is an unprotected public RAM region, with the placed .cy_sharedmem section.
; This region is used to place objects that require full access from both cores. ; This region is used to place objects that require full access from both cores.
; Uncomment the following lines, define the region size and uncomment placement of ; Uncomment the following lines, define the region size and uncomment placement of
; .cy_sharedmem section below. ; .cy_sharedmem section below.
; #define PUBLIC_RAM_SIZE %REGION_SIZE% ; #define PUBLIC_RAM_SIZE %REGION_SIZE%
; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE) ; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
; Cortex-M0+ application flash area ; Cortex-M0+ application flash area
LR_IROM1 FLASH_START FLASH_SIZE LR_IROM1 FLASH_START FLASH_SIZE
{ {
.cy_app_header +0 .cy_app_header +0
{ {
* (.cy_app_header) * (.cy_app_header)
} }
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address. ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address.
;RW_IRAM2 PUBLIC_RAM_START UNINIT ;RW_IRAM2 PUBLIC_RAM_START UNINIT
;{ ;{
; * (.cy_sharedmem) ; * (.cy_sharedmem)
;} ;}
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
{ {
} }
} }
; Emulated EEPROM Flash area ; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{ {
.cy_em_eeprom +0 .cy_em_eeprom +0
{ {
* (.cy_em_eeprom) * (.cy_em_eeprom)
} }
} }
; Supervisory flash: User data ; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{ {
.cy_sflash_user_data +0 .cy_sflash_user_data +0
{ {
* (.cy_sflash_user_data) * (.cy_sflash_user_data)
} }
} }
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{ {
.cy_sflash_nar +0 .cy_sflash_nar +0
{ {
* (.cy_sflash_nar) * (.cy_sflash_nar)
} }
} }
; Supervisory flash: Public Key ; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{ {
.cy_sflash_public_key +0 .cy_sflash_public_key +0
{ {
* (.cy_sflash_public_key) * (.cy_sflash_public_key)
} }
} }
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{ {
.cy_toc_part2 +0 .cy_toc_part2 +0
{ {
* (.cy_toc_part2) * (.cy_toc_part2)
} }
} }
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{ {
.cy_rtoc_part2 +0 .cy_rtoc_part2 +0
{ {
* (.cy_rtoc_part2) * (.cy_rtoc_part2)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
; eFuse ; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE LR_EFUSE EFUSE_START EFUSE_SIZE
{ {
.cy_efuse +0 .cy_efuse +0
{ {
* (.cy_efuse) * (.cy_efuse)
} }
} }
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. ; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000 CYMETA 0x90500000
{ {
.cymeta +0 { * (.cymeta) } .cymeta +0 { * (.cymeta) }
} }
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
#define __cy_memory_0_start 0x10000000 #define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x00080000 #define __cy_memory_0_length 0x00080000
#define __cy_memory_0_row_size 0x200 #define __cy_memory_0_row_size 0x200
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
#define __cy_memory_1_start 0x14000000 #define __cy_memory_1_start 0x14000000
#define __cy_memory_1_length 0x8000 #define __cy_memory_1_length 0x8000
#define __cy_memory_1_row_size 0x200 #define __cy_memory_1_row_size 0x200
/* Supervisory Flash */ /* Supervisory Flash */
#define __cy_memory_2_start 0x16000000 #define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000 #define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200 #define __cy_memory_2_row_size 0x200
/* XIP */ /* XIP */
#define __cy_memory_3_start 0x18000000 #define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000 #define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200 #define __cy_memory_3_row_size 0x200
/* eFuse */ /* eFuse */
#define __cy_memory_4_start 0x90700000 #define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000 #define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1 #define __cy_memory_4_row_size 1
/* [] END OF FILE */ /* [] END OF FILE */

544
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct
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@@ -1,272 +1,272 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cy8c6xx7_cm0plus.sct ;* \file cy8c6xx7_cm0plus.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM0+ core. ; The following defines control RAM and flash memory allocation for the CM0+ core.
; You can change the memory allocation by editing the RAM and Flash defines. ; You can change the memory allocation by editing the RAM and Flash defines.
; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. ; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior. ; Using this memory region for other purposes will lead to unexpected behavior.
; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', ; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. ; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
; RAM ; RAM
#define RAM_START 0x08000000 #define RAM_START 0x08000000
#define RAM_SIZE 0x00002000 #define RAM_SIZE 0x00002000
; Flash ; Flash
#define FLASH_START 0x10000000 #define FLASH_START 0x10000000
#define FLASH_SIZE 0x00002000 #define FLASH_SIZE 0x00002000
; The size of the stack section at the end of CM0+ SRAM ; The size of the stack section at the end of CM0+ SRAM
#define STACK_SIZE 0x00001000 #define STACK_SIZE 0x00001000
; The following defines describe a 32K flash region used for EEPROM emulation. ; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash. ; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores. ; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation. ; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000 #define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000 #define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data ; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800 #define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800 #define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00 #define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200 #define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key ; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00 #define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 #define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00 #define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200 #define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00 #define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200 #define SFLASH_RTOC_2_SIZE 0x00000200
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; eFuse ; eFuse
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Public RAM ; Public RAM
; This is an unprotected public RAM region, with the placed .cy_sharedmem section. ; This is an unprotected public RAM region, with the placed .cy_sharedmem section.
; This region is used to place objects that require full access from both cores. ; This region is used to place objects that require full access from both cores.
; Uncomment the following lines, define the region size and uncomment placement of ; Uncomment the following lines, define the region size and uncomment placement of
; .cy_sharedmem section below. ; .cy_sharedmem section below.
; #define PUBLIC_RAM_SIZE %REGION_SIZE% ; #define PUBLIC_RAM_SIZE %REGION_SIZE%
; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE) ; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
; Cortex-M0+ application flash area ; Cortex-M0+ application flash area
LR_IROM1 FLASH_START FLASH_SIZE LR_IROM1 FLASH_START FLASH_SIZE
{ {
.cy_app_header +0 .cy_app_header +0
{ {
* (.cy_app_header) * (.cy_app_header)
} }
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address. ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address.
;RW_IRAM2 PUBLIC_RAM_START UNINIT ;RW_IRAM2 PUBLIC_RAM_START UNINIT
;{ ;{
; * (.cy_sharedmem) ; * (.cy_sharedmem)
;} ;}
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
{ {
} }
} }
; Emulated EEPROM Flash area ; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{ {
.cy_em_eeprom +0 .cy_em_eeprom +0
{ {
* (.cy_em_eeprom) * (.cy_em_eeprom)
} }
} }
; Supervisory flash: User data ; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{ {
.cy_sflash_user_data +0 .cy_sflash_user_data +0
{ {
* (.cy_sflash_user_data) * (.cy_sflash_user_data)
} }
} }
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{ {
.cy_sflash_nar +0 .cy_sflash_nar +0
{ {
* (.cy_sflash_nar) * (.cy_sflash_nar)
} }
} }
; Supervisory flash: Public Key ; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{ {
.cy_sflash_public_key +0 .cy_sflash_public_key +0
{ {
* (.cy_sflash_public_key) * (.cy_sflash_public_key)
} }
} }
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{ {
.cy_toc_part2 +0 .cy_toc_part2 +0
{ {
* (.cy_toc_part2) * (.cy_toc_part2)
} }
} }
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{ {
.cy_rtoc_part2 +0 .cy_rtoc_part2 +0
{ {
* (.cy_rtoc_part2) * (.cy_rtoc_part2)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
; eFuse ; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE LR_EFUSE EFUSE_START EFUSE_SIZE
{ {
.cy_efuse +0 .cy_efuse +0
{ {
* (.cy_efuse) * (.cy_efuse)
} }
} }
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. ; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000 CYMETA 0x90500000
{ {
.cymeta +0 { * (.cymeta) } .cymeta +0 { * (.cymeta) }
} }
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
#define __cy_memory_0_start 0x10000000 #define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x00100000 #define __cy_memory_0_length 0x00100000
#define __cy_memory_0_row_size 0x200 #define __cy_memory_0_row_size 0x200
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
#define __cy_memory_1_start 0x14000000 #define __cy_memory_1_start 0x14000000
#define __cy_memory_1_length 0x8000 #define __cy_memory_1_length 0x8000
#define __cy_memory_1_row_size 0x200 #define __cy_memory_1_row_size 0x200
/* Supervisory Flash */ /* Supervisory Flash */
#define __cy_memory_2_start 0x16000000 #define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000 #define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200 #define __cy_memory_2_row_size 0x200
/* XIP */ /* XIP */
#define __cy_memory_3_start 0x18000000 #define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000 #define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200 #define __cy_memory_3_row_size 0x200
/* eFuse */ /* eFuse */
#define __cy_memory_4_start 0x90700000 #define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000 #define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1 #define __cy_memory_4_row_size 1
/* [] END OF FILE */ /* [] END OF FILE */

544
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct
View File

@@ -1,272 +1,272 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cy8c6xx8_cm0plus.sct ;* \file cy8c6xx8_cm0plus.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM0+ core. ; The following defines control RAM and flash memory allocation for the CM0+ core.
; You can change the memory allocation by editing the RAM and Flash defines. ; You can change the memory allocation by editing the RAM and Flash defines.
; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. ; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior. ; Using this memory region for other purposes will lead to unexpected behavior.
; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', ; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. ; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
; RAM ; RAM
#define RAM_START 0x08000000 #define RAM_START 0x08000000
#define RAM_SIZE 0x00002000 #define RAM_SIZE 0x00002000
; Flash ; Flash
#define FLASH_START 0x10000000 #define FLASH_START 0x10000000
#define FLASH_SIZE 0x00002000 #define FLASH_SIZE 0x00002000
; The size of the stack section at the end of CM0+ SRAM ; The size of the stack section at the end of CM0+ SRAM
#define STACK_SIZE 0x00001000 #define STACK_SIZE 0x00001000
; The following defines describe a 32K flash region used for EEPROM emulation. ; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash. ; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores. ; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation. ; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000 #define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000 #define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data ; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800 #define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800 #define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00 #define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200 #define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key ; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00 #define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 #define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00 #define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200 #define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00 #define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200 #define SFLASH_RTOC_2_SIZE 0x00000200
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; eFuse ; eFuse
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Public RAM ; Public RAM
; This is an unprotected public RAM region, with the placed .cy_sharedmem section. ; This is an unprotected public RAM region, with the placed .cy_sharedmem section.
; This region is used to place objects that require full access from both cores. ; This region is used to place objects that require full access from both cores.
; Uncomment the following lines, define the region size and uncomment placement of ; Uncomment the following lines, define the region size and uncomment placement of
; .cy_sharedmem section below. ; .cy_sharedmem section below.
; #define PUBLIC_RAM_SIZE %REGION_SIZE% ; #define PUBLIC_RAM_SIZE %REGION_SIZE%
; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE) ; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
; Cortex-M0+ application flash area ; Cortex-M0+ application flash area
LR_IROM1 FLASH_START FLASH_SIZE LR_IROM1 FLASH_START FLASH_SIZE
{ {
.cy_app_header +0 .cy_app_header +0
{ {
* (.cy_app_header) * (.cy_app_header)
} }
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address. ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address.
;RW_IRAM2 PUBLIC_RAM_START UNINIT ;RW_IRAM2 PUBLIC_RAM_START UNINIT
;{ ;{
; * (.cy_sharedmem) ; * (.cy_sharedmem)
;} ;}
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
{ {
} }
} }
; Emulated EEPROM Flash area ; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{ {
.cy_em_eeprom +0 .cy_em_eeprom +0
{ {
* (.cy_em_eeprom) * (.cy_em_eeprom)
} }
} }
; Supervisory flash: User data ; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{ {
.cy_sflash_user_data +0 .cy_sflash_user_data +0
{ {
* (.cy_sflash_user_data) * (.cy_sflash_user_data)
} }
} }
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{ {
.cy_sflash_nar +0 .cy_sflash_nar +0
{ {
* (.cy_sflash_nar) * (.cy_sflash_nar)
} }
} }
; Supervisory flash: Public Key ; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{ {
.cy_sflash_public_key +0 .cy_sflash_public_key +0
{ {
* (.cy_sflash_public_key) * (.cy_sflash_public_key)
} }
} }
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{ {
.cy_toc_part2 +0 .cy_toc_part2 +0
{ {
* (.cy_toc_part2) * (.cy_toc_part2)
} }
} }
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{ {
.cy_rtoc_part2 +0 .cy_rtoc_part2 +0
{ {
* (.cy_rtoc_part2) * (.cy_rtoc_part2)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
; eFuse ; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE LR_EFUSE EFUSE_START EFUSE_SIZE
{ {
.cy_efuse +0 .cy_efuse +0
{ {
* (.cy_efuse) * (.cy_efuse)
} }
} }
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. ; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000 CYMETA 0x90500000
{ {
.cymeta +0 { * (.cymeta) } .cymeta +0 { * (.cymeta) }
} }
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
#define __cy_memory_0_start 0x10000000 #define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x00100000 #define __cy_memory_0_length 0x00100000
#define __cy_memory_0_row_size 0x200 #define __cy_memory_0_row_size 0x200
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
#define __cy_memory_1_start 0x14000000 #define __cy_memory_1_start 0x14000000
#define __cy_memory_1_length 0x8000 #define __cy_memory_1_length 0x8000
#define __cy_memory_1_row_size 0x200 #define __cy_memory_1_row_size 0x200
/* Supervisory Flash */ /* Supervisory Flash */
#define __cy_memory_2_start 0x16000000 #define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000 #define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200 #define __cy_memory_2_row_size 0x200
/* XIP */ /* XIP */
#define __cy_memory_3_start 0x18000000 #define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000 #define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200 #define __cy_memory_3_row_size 0x200
/* eFuse */ /* eFuse */
#define __cy_memory_4_start 0x90700000 #define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000 #define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1 #define __cy_memory_4_row_size 1
/* [] END OF FILE */ /* [] END OF FILE */

544
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct
View File

@@ -1,272 +1,272 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cy8c6xxa_cm0plus.sct ;* \file cy8c6xxa_cm0plus.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM0+ core. ; The following defines control RAM and flash memory allocation for the CM0+ core.
; You can change the memory allocation by editing the RAM and Flash defines. ; You can change the memory allocation by editing the RAM and Flash defines.
; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. ; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior. ; Using this memory region for other purposes will lead to unexpected behavior.
; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', ; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. ; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
; RAM ; RAM
#define RAM_START 0x08000000 #define RAM_START 0x08000000
#define RAM_SIZE 0x00002000 #define RAM_SIZE 0x00002000
; Flash ; Flash
#define FLASH_START 0x10000000 #define FLASH_START 0x10000000
#define FLASH_SIZE 0x00002000 #define FLASH_SIZE 0x00002000
; The size of the stack section at the end of CM0+ SRAM ; The size of the stack section at the end of CM0+ SRAM
#define STACK_SIZE 0x00001000 #define STACK_SIZE 0x00001000
; The following defines describe a 32K flash region used for EEPROM emulation. ; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash. ; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores. ; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation. ; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000 #define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000 #define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data ; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800 #define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800 #define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00 #define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200 #define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key ; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00 #define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 #define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00 #define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200 #define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00 #define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200 #define SFLASH_RTOC_2_SIZE 0x00000200
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; eFuse ; eFuse
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Public RAM ; Public RAM
; This is an unprotected public RAM region, with the placed .cy_sharedmem section. ; This is an unprotected public RAM region, with the placed .cy_sharedmem section.
; This region is used to place objects that require full access from both cores. ; This region is used to place objects that require full access from both cores.
; Uncomment the following lines, define the region size and uncomment placement of ; Uncomment the following lines, define the region size and uncomment placement of
; .cy_sharedmem section below. ; .cy_sharedmem section below.
; #define PUBLIC_RAM_SIZE %REGION_SIZE% ; #define PUBLIC_RAM_SIZE %REGION_SIZE%
; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE) ; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
; Cortex-M0+ application flash area ; Cortex-M0+ application flash area
LR_IROM1 FLASH_START FLASH_SIZE LR_IROM1 FLASH_START FLASH_SIZE
{ {
.cy_app_header +0 .cy_app_header +0
{ {
* (.cy_app_header) * (.cy_app_header)
} }
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address. ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address.
;RW_IRAM2 PUBLIC_RAM_START UNINIT ;RW_IRAM2 PUBLIC_RAM_START UNINIT
;{ ;{
; * (.cy_sharedmem) ; * (.cy_sharedmem)
;} ;}
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
{ {
} }
} }
; Emulated EEPROM Flash area ; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{ {
.cy_em_eeprom +0 .cy_em_eeprom +0
{ {
* (.cy_em_eeprom) * (.cy_em_eeprom)
} }
} }
; Supervisory flash: User data ; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{ {
.cy_sflash_user_data +0 .cy_sflash_user_data +0
{ {
* (.cy_sflash_user_data) * (.cy_sflash_user_data)
} }
} }
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{ {
.cy_sflash_nar +0 .cy_sflash_nar +0
{ {
* (.cy_sflash_nar) * (.cy_sflash_nar)
} }
} }
; Supervisory flash: Public Key ; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{ {
.cy_sflash_public_key +0 .cy_sflash_public_key +0
{ {
* (.cy_sflash_public_key) * (.cy_sflash_public_key)
} }
} }
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{ {
.cy_toc_part2 +0 .cy_toc_part2 +0
{ {
* (.cy_toc_part2) * (.cy_toc_part2)
} }
} }
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{ {
.cy_rtoc_part2 +0 .cy_rtoc_part2 +0
{ {
* (.cy_rtoc_part2) * (.cy_rtoc_part2)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
; eFuse ; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE LR_EFUSE EFUSE_START EFUSE_SIZE
{ {
.cy_efuse +0 .cy_efuse +0
{ {
* (.cy_efuse) * (.cy_efuse)
} }
} }
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. ; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000 CYMETA 0x90500000
{ {
.cymeta +0 { * (.cymeta) } .cymeta +0 { * (.cymeta) }
} }
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
#define __cy_memory_0_start 0x10000000 #define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x00200000 #define __cy_memory_0_length 0x00200000
#define __cy_memory_0_row_size 0x200 #define __cy_memory_0_row_size 0x200
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
#define __cy_memory_1_start 0x14000000 #define __cy_memory_1_start 0x14000000
#define __cy_memory_1_length 0x8000 #define __cy_memory_1_length 0x8000
#define __cy_memory_1_row_size 0x200 #define __cy_memory_1_row_size 0x200
/* Supervisory Flash */ /* Supervisory Flash */
#define __cy_memory_2_start 0x16000000 #define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000 #define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200 #define __cy_memory_2_row_size 0x200
/* XIP */ /* XIP */
#define __cy_memory_3_start 0x18000000 #define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000 #define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200 #define __cy_memory_3_row_size 0x200
/* eFuse */ /* eFuse */
#define __cy_memory_4_start 0x90700000 #define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000 #define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1 #define __cy_memory_4_row_size 1
/* [] END OF FILE */ /* [] END OF FILE */

488
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx5_cm0plus.sct
View File

@@ -1,244 +1,244 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cyb06xx5_cm0plus.sct ;* \file cyb06xx5_cm0plus.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM0+ core. ; The following defines control RAM and flash memory allocation for the CM0+ core.
; You can change the memory allocation by editing the RAM and Flash defines. ; You can change the memory allocation by editing the RAM and Flash defines.
; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', ; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'. ; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'.
; RAM ; RAM
#define RAM_START 0x08020000 #define RAM_START 0x08020000
#define RAM_SIZE 0x0000C000 #define RAM_SIZE 0x0000C000
; Flash ; Flash
#define FLASH_START 0x10000000 #define FLASH_START 0x10000000
#define FLASH_SIZE 0x00010000 #define FLASH_SIZE 0x00010000
; The size of the stack section at the end of CM0+ SRAM ; The size of the stack section at the end of CM0+ SRAM
#define STACK_SIZE 0x00001000 #define STACK_SIZE 0x00001000
; The size of the MCU boot header area at the start of FLASH ; The size of the MCU boot header area at the start of FLASH
#define BOOT_HEADER_SIZE 0x00000400 #define BOOT_HEADER_SIZE 0x00000400
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data ; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800 #define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800 #define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00 #define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200 #define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key ; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00 #define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 #define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00 #define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200 #define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00 #define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200 #define SFLASH_RTOC_2_SIZE 0x00000200
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; eFuse ; eFuse
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Public RAM ; Public RAM
#define PUBLIC_RAM_SIZE 0x800 #define PUBLIC_RAM_SIZE 0x800
#define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE) #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
; Cortex-M0+ application flash area ; Cortex-M0+ application flash area
LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE) LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE)
{ {
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
RW_IRAM2 PUBLIC_RAM_START UNINIT RW_IRAM2 PUBLIC_RAM_START UNINIT
{ {
* (.cy_sharedmem) * (.cy_sharedmem)
} }
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-AlignExpr(ImageLimit(RW_IRAM2), 8) ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-AlignExpr(ImageLimit(RW_IRAM2), 8)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
{ {
} }
} }
; Supervisory flash: User data ; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{ {
.cy_sflash_user_data +0 .cy_sflash_user_data +0
{ {
* (.cy_sflash_user_data) * (.cy_sflash_user_data)
} }
} }
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{ {
.cy_sflash_nar +0 .cy_sflash_nar +0
{ {
* (.cy_sflash_nar) * (.cy_sflash_nar)
} }
} }
; Supervisory flash: Public Key ; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{ {
.cy_sflash_public_key +0 .cy_sflash_public_key +0
{ {
* (.cy_sflash_public_key) * (.cy_sflash_public_key)
} }
} }
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{ {
.cy_toc_part2 +0 .cy_toc_part2 +0
{ {
* (.cy_toc_part2) * (.cy_toc_part2)
} }
} }
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{ {
.cy_rtoc_part2 +0 .cy_rtoc_part2 +0
{ {
* (.cy_rtoc_part2) * (.cy_rtoc_part2)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
; eFuse ; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE LR_EFUSE EFUSE_START EFUSE_SIZE
{ {
.cy_efuse +0 .cy_efuse +0
{ {
* (.cy_efuse) * (.cy_efuse)
} }
} }
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. ; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000 CYMETA 0x90500000
{ {
.cymeta +0 { * (.cymeta) } .cymeta +0 { * (.cymeta) }
} }
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
#define __cy_memory_0_start 0x10000000 #define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x00070000 #define __cy_memory_0_length 0x00070000
#define __cy_memory_0_row_size 0x200 #define __cy_memory_0_row_size 0x200
/* Supervisory Flash */ /* Supervisory Flash */
#define __cy_memory_2_start 0x16000000 #define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000 #define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200 #define __cy_memory_2_row_size 0x200
/* XIP */ /* XIP */
#define __cy_memory_3_start 0x18000000 #define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000 #define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200 #define __cy_memory_3_row_size 0x200
/* eFuse */ /* eFuse */
#define __cy_memory_4_start 0x90700000 #define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000 #define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1 #define __cy_memory_4_row_size 1
/* [] END OF FILE */ /* [] END OF FILE */

526
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct
View File

@@ -1,263 +1,263 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cyb06xx7_cm0plus.sct ;* \file cyb06xx7_cm0plus.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM0+ core. ; The following defines control RAM and flash memory allocation for the CM0+ core.
; You can change the memory allocation by editing the RAM and Flash defines. ; You can change the memory allocation by editing the RAM and Flash defines.
; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', ; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'. ; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'.
; RAM ; RAM
#define RAM_START 0x08020000 #define RAM_START 0x08020000
#define RAM_SIZE 0x0000C000 #define RAM_SIZE 0x0000C000
; Flash ; Flash
#define FLASH_START 0x10000000 #define FLASH_START 0x10000000
#define FLASH_SIZE 0x00010000 #define FLASH_SIZE 0x00010000
; The size of the stack section at the end of CM0+ SRAM ; The size of the stack section at the end of CM0+ SRAM
#define STACK_SIZE 0x00001000 #define STACK_SIZE 0x00001000
; The size of the MCU boot header area at the start of FLASH ; The size of the MCU boot header area at the start of FLASH
#define BOOT_HEADER_SIZE 0x00000400 #define BOOT_HEADER_SIZE 0x00000400
; The following defines describe a 32K flash region used for EEPROM emulation. ; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash. ; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores. ; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation. ; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000 #define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000 #define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data ; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800 #define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800 #define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00 #define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200 #define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key ; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00 #define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 #define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00 #define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200 #define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00 #define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200 #define SFLASH_RTOC_2_SIZE 0x00000200
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; eFuse ; eFuse
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Public RAM ; Public RAM
#define PUBLIC_RAM_SIZE 0x800 #define PUBLIC_RAM_SIZE 0x800
#define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE) #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
; Cortex-M0+ application flash area ; Cortex-M0+ application flash area
LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE) LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE)
{ {
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
RW_IRAM2 PUBLIC_RAM_START UNINIT RW_IRAM2 PUBLIC_RAM_START UNINIT
{ {
* (.cy_sharedmem) * (.cy_sharedmem)
} }
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-AlignExpr(ImageLimit(RW_IRAM2), 8) ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-AlignExpr(ImageLimit(RW_IRAM2), 8)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
{ {
} }
} }
; Emulated EEPROM Flash area ; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{ {
.cy_em_eeprom +0 .cy_em_eeprom +0
{ {
* (.cy_em_eeprom) * (.cy_em_eeprom)
} }
} }
; Supervisory flash: User data ; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{ {
.cy_sflash_user_data +0 .cy_sflash_user_data +0
{ {
* (.cy_sflash_user_data) * (.cy_sflash_user_data)
} }
} }
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{ {
.cy_sflash_nar +0 .cy_sflash_nar +0
{ {
* (.cy_sflash_nar) * (.cy_sflash_nar)
} }
} }
; Supervisory flash: Public Key ; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{ {
.cy_sflash_public_key +0 .cy_sflash_public_key +0
{ {
* (.cy_sflash_public_key) * (.cy_sflash_public_key)
} }
} }
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{ {
.cy_toc_part2 +0 .cy_toc_part2 +0
{ {
* (.cy_toc_part2) * (.cy_toc_part2)
} }
} }
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{ {
.cy_rtoc_part2 +0 .cy_rtoc_part2 +0
{ {
* (.cy_rtoc_part2) * (.cy_rtoc_part2)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
; eFuse ; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE LR_EFUSE EFUSE_START EFUSE_SIZE
{ {
.cy_efuse +0 .cy_efuse +0
{ {
* (.cy_efuse) * (.cy_efuse)
} }
} }
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. ; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000 CYMETA 0x90500000
{ {
.cymeta +0 { * (.cymeta) } .cymeta +0 { * (.cymeta) }
} }
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
#define __cy_memory_0_start 0x10000000 #define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x000D0000 #define __cy_memory_0_length 0x000D0000
#define __cy_memory_0_row_size 0x200 #define __cy_memory_0_row_size 0x200
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
#define __cy_memory_1_start 0x14000000 #define __cy_memory_1_start 0x14000000
#define __cy_memory_1_length 0x8000 #define __cy_memory_1_length 0x8000
#define __cy_memory_1_row_size 0x200 #define __cy_memory_1_row_size 0x200
/* Supervisory Flash */ /* Supervisory Flash */
#define __cy_memory_2_start 0x16000000 #define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000 #define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200 #define __cy_memory_2_row_size 0x200
/* XIP */ /* XIP */
#define __cy_memory_3_start 0x18000000 #define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000 #define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200 #define __cy_memory_3_row_size 0x200
/* eFuse */ /* eFuse */
#define __cy_memory_4_start 0x90700000 #define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000 #define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1 #define __cy_memory_4_row_size 1
/* [] END OF FILE */ /* [] END OF FILE */

526
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct
View File

@@ -1,263 +1,263 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cyb06xxa_cm0plus.sct ;* \file cyb06xxa_cm0plus.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM0+ core. ; The following defines control RAM and flash memory allocation for the CM0+ core.
; You can change the memory allocation by editing the RAM and Flash defines. ; You can change the memory allocation by editing the RAM and Flash defines.
; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', ; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'. ; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'.
; RAM ; RAM
#define RAM_START 0x080E0000 #define RAM_START 0x080E0000
#define RAM_SIZE 0x0000C000 #define RAM_SIZE 0x0000C000
; Flash ; Flash
#define FLASH_START 0x10000000 #define FLASH_START 0x10000000
#define FLASH_SIZE 0x00010000 #define FLASH_SIZE 0x00010000
; The size of the stack section at the end of CM0+ SRAM ; The size of the stack section at the end of CM0+ SRAM
#define STACK_SIZE 0x00001000 #define STACK_SIZE 0x00001000
; The size of the MCU boot header area at the start of FLASH ; The size of the MCU boot header area at the start of FLASH
#define BOOT_HEADER_SIZE 0x00000400 #define BOOT_HEADER_SIZE 0x00000400
; The following defines describe a 32K flash region used for EEPROM emulation. ; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash. ; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores. ; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation. ; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000 #define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000 #define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data ; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800 #define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800 #define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00 #define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200 #define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key ; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00 #define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 #define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00 #define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200 #define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00 #define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200 #define SFLASH_RTOC_2_SIZE 0x00000200
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; eFuse ; eFuse
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Public RAM ; Public RAM
#define PUBLIC_RAM_SIZE 0x800 #define PUBLIC_RAM_SIZE 0x800
#define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE) #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
; Cortex-M0+ application flash area ; Cortex-M0+ application flash area
LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE) LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE)
{ {
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
RW_IRAM2 PUBLIC_RAM_START UNINIT RW_IRAM2 PUBLIC_RAM_START UNINIT
{ {
* (.cy_sharedmem) * (.cy_sharedmem)
} }
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-AlignExpr(ImageLimit(RW_IRAM2), 8) ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-AlignExpr(ImageLimit(RW_IRAM2), 8)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
{ {
} }
} }
; Emulated EEPROM Flash area ; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{ {
.cy_em_eeprom +0 .cy_em_eeprom +0
{ {
* (.cy_em_eeprom) * (.cy_em_eeprom)
} }
} }
; Supervisory flash: User data ; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{ {
.cy_sflash_user_data +0 .cy_sflash_user_data +0
{ {
* (.cy_sflash_user_data) * (.cy_sflash_user_data)
} }
} }
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{ {
.cy_sflash_nar +0 .cy_sflash_nar +0
{ {
* (.cy_sflash_nar) * (.cy_sflash_nar)
} }
} }
; Supervisory flash: Public Key ; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{ {
.cy_sflash_public_key +0 .cy_sflash_public_key +0
{ {
* (.cy_sflash_public_key) * (.cy_sflash_public_key)
} }
} }
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{ {
.cy_toc_part2 +0 .cy_toc_part2 +0
{ {
* (.cy_toc_part2) * (.cy_toc_part2)
} }
} }
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{ {
.cy_rtoc_part2 +0 .cy_rtoc_part2 +0
{ {
* (.cy_rtoc_part2) * (.cy_rtoc_part2)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
; eFuse ; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE LR_EFUSE EFUSE_START EFUSE_SIZE
{ {
.cy_efuse +0 .cy_efuse +0
{ {
* (.cy_efuse) * (.cy_efuse)
} }
} }
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. ; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000 CYMETA 0x90500000
{ {
.cymeta +0 { * (.cymeta) } .cymeta +0 { * (.cymeta) }
} }
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
#define __cy_memory_0_start 0x10000000 #define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x001D0000 #define __cy_memory_0_length 0x001D0000
#define __cy_memory_0_row_size 0x200 #define __cy_memory_0_row_size 0x200
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
#define __cy_memory_1_start 0x14000000 #define __cy_memory_1_start 0x14000000
#define __cy_memory_1_length 0x8000 #define __cy_memory_1_length 0x8000
#define __cy_memory_1_row_size 0x200 #define __cy_memory_1_row_size 0x200
/* Supervisory Flash */ /* Supervisory Flash */
#define __cy_memory_2_start 0x16000000 #define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000 #define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200 #define __cy_memory_2_row_size 0x200
/* XIP */ /* XIP */
#define __cy_memory_3_start 0x18000000 #define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000 #define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200 #define __cy_memory_3_row_size 0x200
/* eFuse */ /* eFuse */
#define __cy_memory_4_start 0x90700000 #define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000 #define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1 #define __cy_memory_4_row_size 1
/* [] END OF FILE */ /* [] END OF FILE */

4
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx4_cm0plus.icf
View File

@@ -142,7 +142,7 @@ define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFED
define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
/* Public RAM /* Public RAM
* This is an unprotected public RAM region, with the placed .cy_sharedmem section. * This is an unprotected public RAM region, with the placed .cy_sharedmem section.
* This region is used to place objects that require full access from both cores. * This region is used to place objects that require full access from both cores.
* Uncomment the following lines, define region size, and uncomment the placement of * Uncomment the following lines, define region size, and uncomment the placement of
@@ -198,7 +198,7 @@ place at start of IRAM1_region { readwrite section .intvec_ram};
place in IRAM1_region { readwrite }; place in IRAM1_region { readwrite };
place at end of IRAM1_region { block HSTACK }; place at end of IRAM1_region { block HSTACK };
/* Public RAM /* Public RAM
*To use unprotected public RAM, uncomment the following .cy_sharedmem section placement. *To use unprotected public RAM, uncomment the following .cy_sharedmem section placement.
*/ */
/* /*

4
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf
View File

@@ -142,7 +142,7 @@ define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFED
define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
/* Public RAM /* Public RAM
* This is an unprotected public RAM region, with the placed .cy_sharedmem section. * This is an unprotected public RAM region, with the placed .cy_sharedmem section.
* This region is used to place objects that require full access from both cores. * This region is used to place objects that require full access from both cores.
* Uncomment the following lines, define region size, and uncomment the placement of * Uncomment the following lines, define region size, and uncomment the placement of
@@ -200,7 +200,7 @@ place at start of IRAM1_region { readwrite section .intvec_ram};
place in IRAM1_region { readwrite }; place in IRAM1_region { readwrite };
place at end of IRAM1_region { block HSTACK }; place at end of IRAM1_region { block HSTACK };
/* Public RAM /* Public RAM
*To use unprotected public RAM, uncomment the following .cy_sharedmem section placement. *To use unprotected public RAM, uncomment the following .cy_sharedmem section placement.
*/ */
/* /*

4
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx6_cm0plus.icf
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@@ -142,7 +142,7 @@ define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFED
define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
/* Public RAM /* Public RAM
* This is an unprotected public RAM region, with the placed .cy_sharedmem section. * This is an unprotected public RAM region, with the placed .cy_sharedmem section.
* This region is used to place objects that require full access from both cores. * This region is used to place objects that require full access from both cores.
* Uncomment the following lines, define region size, and uncomment the placement of * Uncomment the following lines, define region size, and uncomment the placement of
@@ -200,7 +200,7 @@ place at start of IRAM1_region { readwrite section .intvec_ram};
place in IRAM1_region { readwrite }; place in IRAM1_region { readwrite };
place at end of IRAM1_region { block HSTACK }; place at end of IRAM1_region { block HSTACK };
/* Public RAM /* Public RAM
*To use unprotected public RAM, uncomment the following .cy_sharedmem section placement. *To use unprotected public RAM, uncomment the following .cy_sharedmem section placement.
*/ */
/* /*

4
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf
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@@ -142,7 +142,7 @@ define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFED
define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
/* Public RAM /* Public RAM
* This is an unprotected public RAM region, with the placed .cy_sharedmem section. * This is an unprotected public RAM region, with the placed .cy_sharedmem section.
* This region is used to place objects that require full access from both cores. * This region is used to place objects that require full access from both cores.
* Uncomment the following lines, define region size, and uncomment the placement of * Uncomment the following lines, define region size, and uncomment the placement of
@@ -200,7 +200,7 @@ place at start of IRAM1_region { readwrite section .intvec_ram};
place in IRAM1_region { readwrite }; place in IRAM1_region { readwrite };
place at end of IRAM1_region { block HSTACK }; place at end of IRAM1_region { block HSTACK };
/* Public RAM /* Public RAM
*To use unprotected public RAM, uncomment the following .cy_sharedmem section placement. *To use unprotected public RAM, uncomment the following .cy_sharedmem section placement.
*/ */
/* /*

4
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx8_cm0plus.icf
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@@ -142,7 +142,7 @@ define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFED
define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
/* Public RAM /* Public RAM
* This is an unprotected public RAM region, with the placed .cy_sharedmem section. * This is an unprotected public RAM region, with the placed .cy_sharedmem section.
* This region is used to place objects that require full access from both cores. * This region is used to place objects that require full access from both cores.
* Uncomment the following lines, define region size, and uncomment the placement of * Uncomment the following lines, define region size, and uncomment the placement of
@@ -200,7 +200,7 @@ place at start of IRAM1_region { readwrite section .intvec_ram};
place in IRAM1_region { readwrite }; place in IRAM1_region { readwrite };
place at end of IRAM1_region { block HSTACK }; place at end of IRAM1_region { block HSTACK };
/* Public RAM /* Public RAM
*To use unprotected public RAM, uncomment the following .cy_sharedmem section placement. *To use unprotected public RAM, uncomment the following .cy_sharedmem section placement.
*/ */
/* /*

4
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf
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@@ -142,7 +142,7 @@ define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFED
define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
/* Public RAM /* Public RAM
* This is an unprotected public RAM region, with the placed .cy_sharedmem section. * This is an unprotected public RAM region, with the placed .cy_sharedmem section.
* This region is used to place objects that require full access from both cores. * This region is used to place objects that require full access from both cores.
* Uncomment the following lines, define region size, and uncomment the placement of * Uncomment the following lines, define region size, and uncomment the placement of
@@ -200,7 +200,7 @@ place at start of IRAM1_region { readwrite section .intvec_ram};
place in IRAM1_region { readwrite }; place in IRAM1_region { readwrite };
place at end of IRAM1_region { block HSTACK }; place at end of IRAM1_region { block HSTACK };
/* Public RAM /* Public RAM
*To use unprotected public RAM, uncomment the following .cy_sharedmem section placement. *To use unprotected public RAM, uncomment the following .cy_sharedmem section placement.
*/ */
/* /*

480
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx4_cm4.sct
View File

@@ -1,240 +1,240 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cy8c6xx4_cm4.sct ;* \file cy8c6xx4_cm4.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM4 core. ; The following defines control RAM and flash memory allocation for the CM4 core.
; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use. ; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior. ; Using this memory region for other purposes will lead to unexpected behavior.
; RAM ; RAM
#define RAM_START 0x08000000 #define RAM_START 0x08000000
#define RAM_SIZE 0x0001F780 #define RAM_SIZE 0x0001F780
; Flash ; Flash
#define FLASH_START 0x10000000 #define FLASH_START 0x10000000
#define FLASH_SIZE 0x00040000 #define FLASH_SIZE 0x00040000
; The size of the stack section at the end of CM4 SRAM ; The size of the stack section at the end of CM4 SRAM
#define STACK_SIZE 0x00001000 #define STACK_SIZE 0x00001000
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data ; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800 #define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800 #define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00 #define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200 #define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key ; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00 #define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 #define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00 #define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200 #define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00 #define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200 #define SFLASH_RTOC_2_SIZE 0x00000200
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; eFuse ; eFuse
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Cortex-M4 application flash area ; Cortex-M4 application flash area
LR_IROM1 FLASH_START FLASH_SIZE LR_IROM1 FLASH_START FLASH_SIZE
{ {
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
{ {
} }
; Used for the digital signature of the secure application and the ; Used for the digital signature of the secure application and the
; Bootloader SDK application. The size of the section depends on the required ; Bootloader SDK application. The size of the section depends on the required
; data size. ; data size.
.cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
{ {
* (.cy_app_signature) * (.cy_app_signature)
} }
} }
; Supervisory flash: User data ; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{ {
.cy_sflash_user_data +0 .cy_sflash_user_data +0
{ {
* (.cy_sflash_user_data) * (.cy_sflash_user_data)
} }
} }
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{ {
.cy_sflash_nar +0 .cy_sflash_nar +0
{ {
* (.cy_sflash_nar) * (.cy_sflash_nar)
} }
} }
; Supervisory flash: Public Key ; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{ {
.cy_sflash_public_key +0 .cy_sflash_public_key +0
{ {
* (.cy_sflash_public_key) * (.cy_sflash_public_key)
} }
} }
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{ {
.cy_toc_part2 +0 .cy_toc_part2 +0
{ {
* (.cy_toc_part2) * (.cy_toc_part2)
} }
} }
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{ {
.cy_rtoc_part2 +0 .cy_rtoc_part2 +0
{ {
* (.cy_rtoc_part2) * (.cy_rtoc_part2)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
; eFuse ; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE LR_EFUSE EFUSE_START EFUSE_SIZE
{ {
.cy_efuse +0 .cy_efuse +0
{ {
* (.cy_efuse) * (.cy_efuse)
} }
} }
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. ; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000 CYMETA 0x90500000
{ {
.cymeta +0 { * (.cymeta) } .cymeta +0 { * (.cymeta) }
} }
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
#define __cy_memory_0_start 0x10000000 #define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x00040000 #define __cy_memory_0_length 0x00040000
#define __cy_memory_0_row_size 0x200 #define __cy_memory_0_row_size 0x200
/* Supervisory Flash */ /* Supervisory Flash */
#define __cy_memory_2_start 0x16000000 #define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000 #define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200 #define __cy_memory_2_row_size 0x200
/* XIP */ /* XIP */
#define __cy_memory_3_start 0x18000000 #define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000 #define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200 #define __cy_memory_3_row_size 0x200
/* eFuse */ /* eFuse */
#define __cy_memory_4_start 0x90700000 #define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000 #define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1 #define __cy_memory_4_row_size 1
/* [] END OF FILE */ /* [] END OF FILE */

516
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx4_cm4_dual.sct
View File

@@ -1,258 +1,258 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cy8c6xx4_cm4_dual.sct ;* \file cy8c6xx4_cm4_dual.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM4 core. ; The following defines control RAM and flash memory allocation for the CM4 core.
; You can change the memory allocation by editing RAM and Flash defines. ; You can change the memory allocation by editing RAM and Flash defines.
; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. ; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior. ; Using this memory region for other purposes will lead to unexpected behavior.
; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', ; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. ; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
; RAM ; RAM
#define RAM_START 0x08002000 #define RAM_START 0x08002000
#define RAM_SIZE 0x0001D800 #define RAM_SIZE 0x0001D800
; Flash ; Flash
#define FLASH_START 0x10000000 #define FLASH_START 0x10000000
#define FLASH_SIZE 0x00040000 #define FLASH_SIZE 0x00040000
; The size of the stack section at the end of CM4 SRAM ; The size of the stack section at the end of CM4 SRAM
#define STACK_SIZE 0x00001000 #define STACK_SIZE 0x00001000
; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. ; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
; More about CM0+ prebuilt images, see here: ; More about CM0+ prebuilt images, see here:
; https://github.com/cypresssemiconductorco/psoc6cm0p ; https://github.com/cypresssemiconductorco/psoc6cm0p
; The size of the Cortex-M0+ application flash image ; The size of the Cortex-M0+ application flash image
#define FLASH_CM0P_SIZE 0x2000 #define FLASH_CM0P_SIZE 0x2000
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data ; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800 #define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800 #define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00 #define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200 #define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key ; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00 #define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 #define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00 #define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200 #define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00 #define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200 #define SFLASH_RTOC_2_SIZE 0x00000200
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; eFuse ; eFuse
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Cortex-M0+ application flash image area ; Cortex-M0+ application flash image area
LR_IROM FLASH_START FLASH_CM0P_SIZE LR_IROM FLASH_START FLASH_CM0P_SIZE
{ {
.cy_m0p_image +0 FLASH_CM0P_SIZE .cy_m0p_image +0 FLASH_CM0P_SIZE
{ {
* (.cy_m0p_image) * (.cy_m0p_image)
} }
} }
; Cortex-M4 application flash area ; Cortex-M4 application flash area
LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
{ {
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
{ {
} }
; Used for the digital signature of the secure application and the ; Used for the digital signature of the secure application and the
; Bootloader SDK application. The size of the section depends on the required ; Bootloader SDK application. The size of the section depends on the required
; data size. ; data size.
.cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
{ {
* (.cy_app_signature) * (.cy_app_signature)
} }
} }
; Supervisory flash: User data ; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{ {
.cy_sflash_user_data +0 .cy_sflash_user_data +0
{ {
* (.cy_sflash_user_data) * (.cy_sflash_user_data)
} }
} }
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{ {
.cy_sflash_nar +0 .cy_sflash_nar +0
{ {
* (.cy_sflash_nar) * (.cy_sflash_nar)
} }
} }
; Supervisory flash: Public Key ; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{ {
.cy_sflash_public_key +0 .cy_sflash_public_key +0
{ {
* (.cy_sflash_public_key) * (.cy_sflash_public_key)
} }
} }
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{ {
.cy_toc_part2 +0 .cy_toc_part2 +0
{ {
* (.cy_toc_part2) * (.cy_toc_part2)
} }
} }
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{ {
.cy_rtoc_part2 +0 .cy_rtoc_part2 +0
{ {
* (.cy_rtoc_part2) * (.cy_rtoc_part2)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
; eFuse ; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE LR_EFUSE EFUSE_START EFUSE_SIZE
{ {
.cy_efuse +0 .cy_efuse +0
{ {
* (.cy_efuse) * (.cy_efuse)
} }
} }
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. ; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000 CYMETA 0x90500000
{ {
.cymeta +0 { * (.cymeta) } .cymeta +0 { * (.cymeta) }
} }
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
#define __cy_memory_0_start 0x10000000 #define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x00040000 #define __cy_memory_0_length 0x00040000
#define __cy_memory_0_row_size 0x200 #define __cy_memory_0_row_size 0x200
/* Supervisory Flash */ /* Supervisory Flash */
#define __cy_memory_2_start 0x16000000 #define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000 #define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200 #define __cy_memory_2_row_size 0x200
/* XIP */ /* XIP */
#define __cy_memory_3_start 0x18000000 #define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000 #define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200 #define __cy_memory_3_row_size 0x200
/* eFuse */ /* eFuse */
#define __cy_memory_4_start 0x90700000 #define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000 #define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1 #define __cy_memory_4_row_size 1
/* [] END OF FILE */ /* [] END OF FILE */

518
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4.sct
View File

@@ -1,259 +1,259 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cy8c6xx5_cm4.sct ;* \file cy8c6xx5_cm4.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM4 core. ; The following defines control RAM and flash memory allocation for the CM4 core.
; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use. ; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior. ; Using this memory region for other purposes will lead to unexpected behavior.
; RAM ; RAM
#define RAM_START 0x08000000 #define RAM_START 0x08000000
#define RAM_SIZE 0x0003F780 #define RAM_SIZE 0x0003F780
; Flash ; Flash
#define FLASH_START 0x10000000 #define FLASH_START 0x10000000
#define FLASH_SIZE 0x00080000 #define FLASH_SIZE 0x00080000
; The size of the stack section at the end of CM4 SRAM ; The size of the stack section at the end of CM4 SRAM
#define STACK_SIZE 0x00001000 #define STACK_SIZE 0x00001000
; The following defines describe a 32K flash region used for EEPROM emulation. ; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash. ; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores. ; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation. ; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000 #define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000 #define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data ; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800 #define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800 #define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00 #define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200 #define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key ; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00 #define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 #define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00 #define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200 #define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00 #define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200 #define SFLASH_RTOC_2_SIZE 0x00000200
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; eFuse ; eFuse
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Cortex-M4 application flash area ; Cortex-M4 application flash area
LR_IROM1 FLASH_START FLASH_SIZE LR_IROM1 FLASH_START FLASH_SIZE
{ {
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
{ {
} }
; Used for the digital signature of the secure application and the ; Used for the digital signature of the secure application and the
; Bootloader SDK application. The size of the section depends on the required ; Bootloader SDK application. The size of the section depends on the required
; data size. ; data size.
.cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
{ {
* (.cy_app_signature) * (.cy_app_signature)
} }
} }
; Emulated EEPROM Flash area ; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{ {
.cy_em_eeprom +0 .cy_em_eeprom +0
{ {
* (.cy_em_eeprom) * (.cy_em_eeprom)
} }
} }
; Supervisory flash: User data ; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{ {
.cy_sflash_user_data +0 .cy_sflash_user_data +0
{ {
* (.cy_sflash_user_data) * (.cy_sflash_user_data)
} }
} }
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{ {
.cy_sflash_nar +0 .cy_sflash_nar +0
{ {
* (.cy_sflash_nar) * (.cy_sflash_nar)
} }
} }
; Supervisory flash: Public Key ; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{ {
.cy_sflash_public_key +0 .cy_sflash_public_key +0
{ {
* (.cy_sflash_public_key) * (.cy_sflash_public_key)
} }
} }
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{ {
.cy_toc_part2 +0 .cy_toc_part2 +0
{ {
* (.cy_toc_part2) * (.cy_toc_part2)
} }
} }
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{ {
.cy_rtoc_part2 +0 .cy_rtoc_part2 +0
{ {
* (.cy_rtoc_part2) * (.cy_rtoc_part2)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
; eFuse ; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE LR_EFUSE EFUSE_START EFUSE_SIZE
{ {
.cy_efuse +0 .cy_efuse +0
{ {
* (.cy_efuse) * (.cy_efuse)
} }
} }
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. ; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000 CYMETA 0x90500000
{ {
.cymeta +0 { * (.cymeta) } .cymeta +0 { * (.cymeta) }
} }
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
#define __cy_memory_0_start 0x10000000 #define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x00080000 #define __cy_memory_0_length 0x00080000
#define __cy_memory_0_row_size 0x200 #define __cy_memory_0_row_size 0x200
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
#define __cy_memory_1_start 0x14000000 #define __cy_memory_1_start 0x14000000
#define __cy_memory_1_length 0x8000 #define __cy_memory_1_length 0x8000
#define __cy_memory_1_row_size 0x200 #define __cy_memory_1_row_size 0x200
/* Supervisory Flash */ /* Supervisory Flash */
#define __cy_memory_2_start 0x16000000 #define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000 #define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200 #define __cy_memory_2_row_size 0x200
/* XIP */ /* XIP */
#define __cy_memory_3_start 0x18000000 #define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000 #define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200 #define __cy_memory_3_row_size 0x200
/* eFuse */ /* eFuse */
#define __cy_memory_4_start 0x90700000 #define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000 #define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1 #define __cy_memory_4_row_size 1
/* [] END OF FILE */ /* [] END OF FILE */

554
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct
View File

@@ -1,277 +1,277 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cy8c6xx5_cm4_dual.sct ;* \file cy8c6xx5_cm4_dual.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM4 core. ; The following defines control RAM and flash memory allocation for the CM4 core.
; You can change the memory allocation by editing RAM and Flash defines. ; You can change the memory allocation by editing RAM and Flash defines.
; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. ; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior. ; Using this memory region for other purposes will lead to unexpected behavior.
; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', ; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. ; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
; RAM ; RAM
#define RAM_START 0x08002000 #define RAM_START 0x08002000
#define RAM_SIZE 0x0003D800 #define RAM_SIZE 0x0003D800
; Flash ; Flash
#define FLASH_START 0x10000000 #define FLASH_START 0x10000000
#define FLASH_SIZE 0x00080000 #define FLASH_SIZE 0x00080000
; The size of the stack section at the end of CM4 SRAM ; The size of the stack section at the end of CM4 SRAM
#define STACK_SIZE 0x00001000 #define STACK_SIZE 0x00001000
; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. ; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
; More about CM0+ prebuilt images, see here: ; More about CM0+ prebuilt images, see here:
; https://github.com/cypresssemiconductorco/psoc6cm0p ; https://github.com/cypresssemiconductorco/psoc6cm0p
; The size of the Cortex-M0+ application flash image ; The size of the Cortex-M0+ application flash image
#define FLASH_CM0P_SIZE 0x2000 #define FLASH_CM0P_SIZE 0x2000
; The following defines describe a 32K flash region used for EEPROM emulation. ; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash. ; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores. ; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation. ; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000 #define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000 #define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data ; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800 #define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800 #define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00 #define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200 #define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key ; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00 #define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 #define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00 #define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200 #define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00 #define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200 #define SFLASH_RTOC_2_SIZE 0x00000200
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; eFuse ; eFuse
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Cortex-M0+ application flash image area ; Cortex-M0+ application flash image area
LR_IROM FLASH_START FLASH_CM0P_SIZE LR_IROM FLASH_START FLASH_CM0P_SIZE
{ {
.cy_m0p_image +0 FLASH_CM0P_SIZE .cy_m0p_image +0 FLASH_CM0P_SIZE
{ {
* (.cy_m0p_image) * (.cy_m0p_image)
} }
} }
; Cortex-M4 application flash area ; Cortex-M4 application flash area
LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
{ {
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
{ {
} }
; Used for the digital signature of the secure application and the ; Used for the digital signature of the secure application and the
; Bootloader SDK application. The size of the section depends on the required ; Bootloader SDK application. The size of the section depends on the required
; data size. ; data size.
.cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
{ {
* (.cy_app_signature) * (.cy_app_signature)
} }
} }
; Emulated EEPROM Flash area ; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{ {
.cy_em_eeprom +0 .cy_em_eeprom +0
{ {
* (.cy_em_eeprom) * (.cy_em_eeprom)
} }
} }
; Supervisory flash: User data ; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{ {
.cy_sflash_user_data +0 .cy_sflash_user_data +0
{ {
* (.cy_sflash_user_data) * (.cy_sflash_user_data)
} }
} }
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{ {
.cy_sflash_nar +0 .cy_sflash_nar +0
{ {
* (.cy_sflash_nar) * (.cy_sflash_nar)
} }
} }
; Supervisory flash: Public Key ; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{ {
.cy_sflash_public_key +0 .cy_sflash_public_key +0
{ {
* (.cy_sflash_public_key) * (.cy_sflash_public_key)
} }
} }
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{ {
.cy_toc_part2 +0 .cy_toc_part2 +0
{ {
* (.cy_toc_part2) * (.cy_toc_part2)
} }
} }
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{ {
.cy_rtoc_part2 +0 .cy_rtoc_part2 +0
{ {
* (.cy_rtoc_part2) * (.cy_rtoc_part2)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
; eFuse ; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE LR_EFUSE EFUSE_START EFUSE_SIZE
{ {
.cy_efuse +0 .cy_efuse +0
{ {
* (.cy_efuse) * (.cy_efuse)
} }
} }
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. ; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000 CYMETA 0x90500000
{ {
.cymeta +0 { * (.cymeta) } .cymeta +0 { * (.cymeta) }
} }
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
#define __cy_memory_0_start 0x10000000 #define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x00080000 #define __cy_memory_0_length 0x00080000
#define __cy_memory_0_row_size 0x200 #define __cy_memory_0_row_size 0x200
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
#define __cy_memory_1_start 0x14000000 #define __cy_memory_1_start 0x14000000
#define __cy_memory_1_length 0x8000 #define __cy_memory_1_length 0x8000
#define __cy_memory_1_row_size 0x200 #define __cy_memory_1_row_size 0x200
/* Supervisory Flash */ /* Supervisory Flash */
#define __cy_memory_2_start 0x16000000 #define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000 #define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200 #define __cy_memory_2_row_size 0x200
/* XIP */ /* XIP */
#define __cy_memory_3_start 0x18000000 #define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000 #define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200 #define __cy_memory_3_row_size 0x200
/* eFuse */ /* eFuse */
#define __cy_memory_4_start 0x90700000 #define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000 #define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1 #define __cy_memory_4_row_size 1
/* [] END OF FILE */ /* [] END OF FILE */

518
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4.sct
View File

@@ -1,259 +1,259 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cy8c6xx6_cm4.sct ;* \file cy8c6xx6_cm4.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM4 core. ; The following defines control RAM and flash memory allocation for the CM4 core.
; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use. ; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior. ; Using this memory region for other purposes will lead to unexpected behavior.
; RAM ; RAM
#define RAM_START 0x08000000 #define RAM_START 0x08000000
#define RAM_SIZE 0x0001F780 #define RAM_SIZE 0x0001F780
; Flash ; Flash
#define FLASH_START 0x10000000 #define FLASH_START 0x10000000
#define FLASH_SIZE 0x00080000 #define FLASH_SIZE 0x00080000
; The size of the stack section at the end of CM4 SRAM ; The size of the stack section at the end of CM4 SRAM
#define STACK_SIZE 0x00001000 #define STACK_SIZE 0x00001000
; The following defines describe a 32K flash region used for EEPROM emulation. ; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash. ; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores. ; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation. ; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000 #define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000 #define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data ; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800 #define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800 #define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00 #define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200 #define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key ; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00 #define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 #define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00 #define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200 #define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00 #define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200 #define SFLASH_RTOC_2_SIZE 0x00000200
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; eFuse ; eFuse
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Cortex-M4 application flash area ; Cortex-M4 application flash area
LR_IROM1 FLASH_START FLASH_SIZE LR_IROM1 FLASH_START FLASH_SIZE
{ {
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
{ {
} }
; Used for the digital signature of the secure application and the ; Used for the digital signature of the secure application and the
; Bootloader SDK application. The size of the section depends on the required ; Bootloader SDK application. The size of the section depends on the required
; data size. ; data size.
.cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
{ {
* (.cy_app_signature) * (.cy_app_signature)
} }
} }
; Emulated EEPROM Flash area ; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{ {
.cy_em_eeprom +0 .cy_em_eeprom +0
{ {
* (.cy_em_eeprom) * (.cy_em_eeprom)
} }
} }
; Supervisory flash: User data ; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{ {
.cy_sflash_user_data +0 .cy_sflash_user_data +0
{ {
* (.cy_sflash_user_data) * (.cy_sflash_user_data)
} }
} }
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{ {
.cy_sflash_nar +0 .cy_sflash_nar +0
{ {
* (.cy_sflash_nar) * (.cy_sflash_nar)
} }
} }
; Supervisory flash: Public Key ; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{ {
.cy_sflash_public_key +0 .cy_sflash_public_key +0
{ {
* (.cy_sflash_public_key) * (.cy_sflash_public_key)
} }
} }
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{ {
.cy_toc_part2 +0 .cy_toc_part2 +0
{ {
* (.cy_toc_part2) * (.cy_toc_part2)
} }
} }
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{ {
.cy_rtoc_part2 +0 .cy_rtoc_part2 +0
{ {
* (.cy_rtoc_part2) * (.cy_rtoc_part2)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
; eFuse ; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE LR_EFUSE EFUSE_START EFUSE_SIZE
{ {
.cy_efuse +0 .cy_efuse +0
{ {
* (.cy_efuse) * (.cy_efuse)
} }
} }
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. ; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000 CYMETA 0x90500000
{ {
.cymeta +0 { * (.cymeta) } .cymeta +0 { * (.cymeta) }
} }
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
#define __cy_memory_0_start 0x10000000 #define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x00080000 #define __cy_memory_0_length 0x00080000
#define __cy_memory_0_row_size 0x200 #define __cy_memory_0_row_size 0x200
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
#define __cy_memory_1_start 0x14000000 #define __cy_memory_1_start 0x14000000
#define __cy_memory_1_length 0x8000 #define __cy_memory_1_length 0x8000
#define __cy_memory_1_row_size 0x200 #define __cy_memory_1_row_size 0x200
/* Supervisory Flash */ /* Supervisory Flash */
#define __cy_memory_2_start 0x16000000 #define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000 #define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200 #define __cy_memory_2_row_size 0x200
/* XIP */ /* XIP */
#define __cy_memory_3_start 0x18000000 #define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000 #define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200 #define __cy_memory_3_row_size 0x200
/* eFuse */ /* eFuse */
#define __cy_memory_4_start 0x90700000 #define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000 #define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1 #define __cy_memory_4_row_size 1
/* [] END OF FILE */ /* [] END OF FILE */

554
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct
View File

@@ -1,277 +1,277 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cy8c6xx6_cm4_dual.sct ;* \file cy8c6xx6_cm4_dual.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM4 core. ; The following defines control RAM and flash memory allocation for the CM4 core.
; You can change the memory allocation by editing RAM and Flash defines. ; You can change the memory allocation by editing RAM and Flash defines.
; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. ; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior. ; Using this memory region for other purposes will lead to unexpected behavior.
; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', ; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. ; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
; RAM ; RAM
#define RAM_START 0x08002000 #define RAM_START 0x08002000
#define RAM_SIZE 0x0001D800 #define RAM_SIZE 0x0001D800
; Flash ; Flash
#define FLASH_START 0x10000000 #define FLASH_START 0x10000000
#define FLASH_SIZE 0x00080000 #define FLASH_SIZE 0x00080000
; The size of the stack section at the end of CM4 SRAM ; The size of the stack section at the end of CM4 SRAM
#define STACK_SIZE 0x00001000 #define STACK_SIZE 0x00001000
; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. ; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
; More about CM0+ prebuilt images, see here: ; More about CM0+ prebuilt images, see here:
; https://github.com/cypresssemiconductorco/psoc6cm0p ; https://github.com/cypresssemiconductorco/psoc6cm0p
; The size of the Cortex-M0+ application flash image ; The size of the Cortex-M0+ application flash image
#define FLASH_CM0P_SIZE 0x2000 #define FLASH_CM0P_SIZE 0x2000
; The following defines describe a 32K flash region used for EEPROM emulation. ; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash. ; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores. ; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation. ; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000 #define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000 #define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data ; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800 #define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800 #define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00 #define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200 #define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key ; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00 #define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 #define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00 #define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200 #define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00 #define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200 #define SFLASH_RTOC_2_SIZE 0x00000200
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; eFuse ; eFuse
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Cortex-M0+ application flash image area ; Cortex-M0+ application flash image area
LR_IROM FLASH_START FLASH_CM0P_SIZE LR_IROM FLASH_START FLASH_CM0P_SIZE
{ {
.cy_m0p_image +0 FLASH_CM0P_SIZE .cy_m0p_image +0 FLASH_CM0P_SIZE
{ {
* (.cy_m0p_image) * (.cy_m0p_image)
} }
} }
; Cortex-M4 application flash area ; Cortex-M4 application flash area
LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
{ {
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
{ {
} }
; Used for the digital signature of the secure application and the ; Used for the digital signature of the secure application and the
; Bootloader SDK application. The size of the section depends on the required ; Bootloader SDK application. The size of the section depends on the required
; data size. ; data size.
.cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
{ {
* (.cy_app_signature) * (.cy_app_signature)
} }
} }
; Emulated EEPROM Flash area ; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{ {
.cy_em_eeprom +0 .cy_em_eeprom +0
{ {
* (.cy_em_eeprom) * (.cy_em_eeprom)
} }
} }
; Supervisory flash: User data ; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{ {
.cy_sflash_user_data +0 .cy_sflash_user_data +0
{ {
* (.cy_sflash_user_data) * (.cy_sflash_user_data)
} }
} }
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{ {
.cy_sflash_nar +0 .cy_sflash_nar +0
{ {
* (.cy_sflash_nar) * (.cy_sflash_nar)
} }
} }
; Supervisory flash: Public Key ; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{ {
.cy_sflash_public_key +0 .cy_sflash_public_key +0
{ {
* (.cy_sflash_public_key) * (.cy_sflash_public_key)
} }
} }
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{ {
.cy_toc_part2 +0 .cy_toc_part2 +0
{ {
* (.cy_toc_part2) * (.cy_toc_part2)
} }
} }
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{ {
.cy_rtoc_part2 +0 .cy_rtoc_part2 +0
{ {
* (.cy_rtoc_part2) * (.cy_rtoc_part2)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
; eFuse ; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE LR_EFUSE EFUSE_START EFUSE_SIZE
{ {
.cy_efuse +0 .cy_efuse +0
{ {
* (.cy_efuse) * (.cy_efuse)
} }
} }
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. ; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000 CYMETA 0x90500000
{ {
.cymeta +0 { * (.cymeta) } .cymeta +0 { * (.cymeta) }
} }
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
#define __cy_memory_0_start 0x10000000 #define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x00080000 #define __cy_memory_0_length 0x00080000
#define __cy_memory_0_row_size 0x200 #define __cy_memory_0_row_size 0x200
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
#define __cy_memory_1_start 0x14000000 #define __cy_memory_1_start 0x14000000
#define __cy_memory_1_length 0x8000 #define __cy_memory_1_length 0x8000
#define __cy_memory_1_row_size 0x200 #define __cy_memory_1_row_size 0x200
/* Supervisory Flash */ /* Supervisory Flash */
#define __cy_memory_2_start 0x16000000 #define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000 #define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200 #define __cy_memory_2_row_size 0x200
/* XIP */ /* XIP */
#define __cy_memory_3_start 0x18000000 #define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000 #define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200 #define __cy_memory_3_row_size 0x200
/* eFuse */ /* eFuse */
#define __cy_memory_4_start 0x90700000 #define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000 #define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1 #define __cy_memory_4_row_size 1
/* [] END OF FILE */ /* [] END OF FILE */

518
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4.sct
View File

@@ -1,259 +1,259 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cy8c6xx7_cm4.sct ;* \file cy8c6xx7_cm4.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM4 core. ; The following defines control RAM and flash memory allocation for the CM4 core.
; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use. ; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior. ; Using this memory region for other purposes will lead to unexpected behavior.
; RAM ; RAM
#define RAM_START 0x08000000 #define RAM_START 0x08000000
#define RAM_SIZE 0x00047780 #define RAM_SIZE 0x00047780
; Flash ; Flash
#define FLASH_START 0x10000000 #define FLASH_START 0x10000000
#define FLASH_SIZE 0x00100000 #define FLASH_SIZE 0x00100000
; The size of the stack section at the end of CM4 SRAM ; The size of the stack section at the end of CM4 SRAM
#define STACK_SIZE 0x00001000 #define STACK_SIZE 0x00001000
; The following defines describe a 32K flash region used for EEPROM emulation. ; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash. ; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores. ; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation. ; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000 #define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000 #define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data ; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800 #define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800 #define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00 #define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200 #define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key ; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00 #define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 #define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00 #define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200 #define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00 #define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200 #define SFLASH_RTOC_2_SIZE 0x00000200
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; eFuse ; eFuse
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Cortex-M4 application flash area ; Cortex-M4 application flash area
LR_IROM1 FLASH_START FLASH_SIZE LR_IROM1 FLASH_START FLASH_SIZE
{ {
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
{ {
} }
; Used for the digital signature of the secure application and the ; Used for the digital signature of the secure application and the
; Bootloader SDK application. The size of the section depends on the required ; Bootloader SDK application. The size of the section depends on the required
; data size. ; data size.
.cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
{ {
* (.cy_app_signature) * (.cy_app_signature)
} }
} }
; Emulated EEPROM Flash area ; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{ {
.cy_em_eeprom +0 .cy_em_eeprom +0
{ {
* (.cy_em_eeprom) * (.cy_em_eeprom)
} }
} }
; Supervisory flash: User data ; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{ {
.cy_sflash_user_data +0 .cy_sflash_user_data +0
{ {
* (.cy_sflash_user_data) * (.cy_sflash_user_data)
} }
} }
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{ {
.cy_sflash_nar +0 .cy_sflash_nar +0
{ {
* (.cy_sflash_nar) * (.cy_sflash_nar)
} }
} }
; Supervisory flash: Public Key ; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{ {
.cy_sflash_public_key +0 .cy_sflash_public_key +0
{ {
* (.cy_sflash_public_key) * (.cy_sflash_public_key)
} }
} }
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{ {
.cy_toc_part2 +0 .cy_toc_part2 +0
{ {
* (.cy_toc_part2) * (.cy_toc_part2)
} }
} }
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{ {
.cy_rtoc_part2 +0 .cy_rtoc_part2 +0
{ {
* (.cy_rtoc_part2) * (.cy_rtoc_part2)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
; eFuse ; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE LR_EFUSE EFUSE_START EFUSE_SIZE
{ {
.cy_efuse +0 .cy_efuse +0
{ {
* (.cy_efuse) * (.cy_efuse)
} }
} }
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. ; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000 CYMETA 0x90500000
{ {
.cymeta +0 { * (.cymeta) } .cymeta +0 { * (.cymeta) }
} }
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
#define __cy_memory_0_start 0x10000000 #define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x00100000 #define __cy_memory_0_length 0x00100000
#define __cy_memory_0_row_size 0x200 #define __cy_memory_0_row_size 0x200
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
#define __cy_memory_1_start 0x14000000 #define __cy_memory_1_start 0x14000000
#define __cy_memory_1_length 0x8000 #define __cy_memory_1_length 0x8000
#define __cy_memory_1_row_size 0x200 #define __cy_memory_1_row_size 0x200
/* Supervisory Flash */ /* Supervisory Flash */
#define __cy_memory_2_start 0x16000000 #define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000 #define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200 #define __cy_memory_2_row_size 0x200
/* XIP */ /* XIP */
#define __cy_memory_3_start 0x18000000 #define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000 #define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200 #define __cy_memory_3_row_size 0x200
/* eFuse */ /* eFuse */
#define __cy_memory_4_start 0x90700000 #define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000 #define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1 #define __cy_memory_4_row_size 1
/* [] END OF FILE */ /* [] END OF FILE */

554
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct
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@@ -1,277 +1,277 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cy8c6xx7_cm4_dual.sct ;* \file cy8c6xx7_cm4_dual.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM4 core. ; The following defines control RAM and flash memory allocation for the CM4 core.
; You can change the memory allocation by editing RAM and Flash defines. ; You can change the memory allocation by editing RAM and Flash defines.
; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. ; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior. ; Using this memory region for other purposes will lead to unexpected behavior.
; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', ; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. ; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
; RAM ; RAM
#define RAM_START 0x08002000 #define RAM_START 0x08002000
#define RAM_SIZE 0x00045800 #define RAM_SIZE 0x00045800
; Flash ; Flash
#define FLASH_START 0x10000000 #define FLASH_START 0x10000000
#define FLASH_SIZE 0x00100000 #define FLASH_SIZE 0x00100000
; The size of the stack section at the end of CM4 SRAM ; The size of the stack section at the end of CM4 SRAM
#define STACK_SIZE 0x00001000 #define STACK_SIZE 0x00001000
; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. ; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
; More about CM0+ prebuilt images, see here: ; More about CM0+ prebuilt images, see here:
; https://github.com/cypresssemiconductorco/psoc6cm0p ; https://github.com/cypresssemiconductorco/psoc6cm0p
; The size of the Cortex-M0+ application flash image ; The size of the Cortex-M0+ application flash image
#define FLASH_CM0P_SIZE 0x2000 #define FLASH_CM0P_SIZE 0x2000
; The following defines describe a 32K flash region used for EEPROM emulation. ; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash. ; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores. ; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation. ; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000 #define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000 #define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data ; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800 #define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800 #define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00 #define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200 #define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key ; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00 #define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 #define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00 #define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200 #define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00 #define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200 #define SFLASH_RTOC_2_SIZE 0x00000200
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; eFuse ; eFuse
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Cortex-M0+ application flash image area ; Cortex-M0+ application flash image area
LR_IROM FLASH_START FLASH_CM0P_SIZE LR_IROM FLASH_START FLASH_CM0P_SIZE
{ {
.cy_m0p_image +0 FLASH_CM0P_SIZE .cy_m0p_image +0 FLASH_CM0P_SIZE
{ {
* (.cy_m0p_image) * (.cy_m0p_image)
} }
} }
; Cortex-M4 application flash area ; Cortex-M4 application flash area
LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
{ {
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
{ {
} }
; Used for the digital signature of the secure application and the ; Used for the digital signature of the secure application and the
; Bootloader SDK application. The size of the section depends on the required ; Bootloader SDK application. The size of the section depends on the required
; data size. ; data size.
.cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
{ {
* (.cy_app_signature) * (.cy_app_signature)
} }
} }
; Emulated EEPROM Flash area ; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{ {
.cy_em_eeprom +0 .cy_em_eeprom +0
{ {
* (.cy_em_eeprom) * (.cy_em_eeprom)
} }
} }
; Supervisory flash: User data ; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{ {
.cy_sflash_user_data +0 .cy_sflash_user_data +0
{ {
* (.cy_sflash_user_data) * (.cy_sflash_user_data)
} }
} }
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{ {
.cy_sflash_nar +0 .cy_sflash_nar +0
{ {
* (.cy_sflash_nar) * (.cy_sflash_nar)
} }
} }
; Supervisory flash: Public Key ; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{ {
.cy_sflash_public_key +0 .cy_sflash_public_key +0
{ {
* (.cy_sflash_public_key) * (.cy_sflash_public_key)
} }
} }
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{ {
.cy_toc_part2 +0 .cy_toc_part2 +0
{ {
* (.cy_toc_part2) * (.cy_toc_part2)
} }
} }
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{ {
.cy_rtoc_part2 +0 .cy_rtoc_part2 +0
{ {
* (.cy_rtoc_part2) * (.cy_rtoc_part2)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
; eFuse ; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE LR_EFUSE EFUSE_START EFUSE_SIZE
{ {
.cy_efuse +0 .cy_efuse +0
{ {
* (.cy_efuse) * (.cy_efuse)
} }
} }
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. ; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000 CYMETA 0x90500000
{ {
.cymeta +0 { * (.cymeta) } .cymeta +0 { * (.cymeta) }
} }
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
#define __cy_memory_0_start 0x10000000 #define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x00100000 #define __cy_memory_0_length 0x00100000
#define __cy_memory_0_row_size 0x200 #define __cy_memory_0_row_size 0x200
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
#define __cy_memory_1_start 0x14000000 #define __cy_memory_1_start 0x14000000
#define __cy_memory_1_length 0x8000 #define __cy_memory_1_length 0x8000
#define __cy_memory_1_row_size 0x200 #define __cy_memory_1_row_size 0x200
/* Supervisory Flash */ /* Supervisory Flash */
#define __cy_memory_2_start 0x16000000 #define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000 #define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200 #define __cy_memory_2_row_size 0x200
/* XIP */ /* XIP */
#define __cy_memory_3_start 0x18000000 #define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000 #define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200 #define __cy_memory_3_row_size 0x200
/* eFuse */ /* eFuse */
#define __cy_memory_4_start 0x90700000 #define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000 #define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1 #define __cy_memory_4_row_size 1
/* [] END OF FILE */ /* [] END OF FILE */

560
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual_cm0p_bless.sct
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@@ -1,280 +1,280 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cy8c6xx7_cm4_dual_cm0p_bless.sct ;* \file cy8c6xx7_cm4_dual_cm0p_bless.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* This linker script is modified from cy8c6xx7_cm4_dual.sct for CM0P_BLESS image. ;* This linker script is modified from cy8c6xx7_cm4_dual.sct for CM0P_BLESS image.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM4 core. ; The following defines control RAM and flash memory allocation for the CM4 core.
; You can change the memory allocation by editing RAM and Flash defines. ; You can change the memory allocation by editing RAM and Flash defines.
; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. ; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior. ; Using this memory region for other purposes will lead to unexpected behavior.
; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', ; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. ; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
; RAM ; RAM
#define RAM_START 0x08003000 #define RAM_START 0x08003000
#define RAM_SIZE 0x00044800 #define RAM_SIZE 0x00044800
; Flash ; Flash
#define FLASH_START 0x10000000 #define FLASH_START 0x10000000
#define FLASH_SIZE 0x00100000 #define FLASH_SIZE 0x00100000
; The size of the stack section at the end of CM4 SRAM ; The size of the stack section at the end of CM4 SRAM
#define STACK_SIZE 0x00001000 #define STACK_SIZE 0x00001000
; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. ; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
; More about CM0+ prebuilt images, see here: ; More about CM0+ prebuilt images, see here:
; https://github.com/cypresssemiconductorco/psoc6cm0p ; https://github.com/cypresssemiconductorco/psoc6cm0p
; The size of the Cortex-M0+ application flash image ; The size of the Cortex-M0+ application flash image
; Size and start address of the Cortex-M0+ application image ; Size and start address of the Cortex-M0+ application image
FLASH_CM0P_SIZE = 0x20000; FLASH_CM0P_SIZE = 0x20000;
; The following defines describe a 32K flash region used for EEPROM emulation. ; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash. ; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores. ; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation. ; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000 #define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000 #define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data ; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800 #define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800 #define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00 #define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200 #define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key ; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00 #define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 #define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00 #define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200 #define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00 #define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200 #define SFLASH_RTOC_2_SIZE 0x00000200
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; eFuse ; eFuse
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Cortex-M0+ application flash image area ; Cortex-M0+ application flash image area
LR_IROM FLASH_START FLASH_CM0P_SIZE LR_IROM FLASH_START FLASH_CM0P_SIZE
{ {
.cy_m0p_image +0 FLASH_CM0P_SIZE .cy_m0p_image +0 FLASH_CM0P_SIZE
{ {
* (.cy_m0p_image) * (.cy_m0p_image)
} }
} }
; Cortex-M4 application flash area ; Cortex-M4 application flash area
LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
{ {
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
{ {
} }
; Used for the digital signature of the secure application and the ; Used for the digital signature of the secure application and the
; Bootloader SDK application. The size of the section depends on the required ; Bootloader SDK application. The size of the section depends on the required
; data size. ; data size.
.cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
{ {
* (.cy_app_signature) * (.cy_app_signature)
} }
} }
; Emulated EEPROM Flash area ; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{ {
.cy_em_eeprom +0 .cy_em_eeprom +0
{ {
* (.cy_em_eeprom) * (.cy_em_eeprom)
} }
} }
; Supervisory flash: User data ; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{ {
.cy_sflash_user_data +0 .cy_sflash_user_data +0
{ {
* (.cy_sflash_user_data) * (.cy_sflash_user_data)
} }
} }
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{ {
.cy_sflash_nar +0 .cy_sflash_nar +0
{ {
* (.cy_sflash_nar) * (.cy_sflash_nar)
} }
} }
; Supervisory flash: Public Key ; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{ {
.cy_sflash_public_key +0 .cy_sflash_public_key +0
{ {
* (.cy_sflash_public_key) * (.cy_sflash_public_key)
} }
} }
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{ {
.cy_toc_part2 +0 .cy_toc_part2 +0
{ {
* (.cy_toc_part2) * (.cy_toc_part2)
} }
} }
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{ {
.cy_rtoc_part2 +0 .cy_rtoc_part2 +0
{ {
* (.cy_rtoc_part2) * (.cy_rtoc_part2)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
; eFuse ; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE LR_EFUSE EFUSE_START EFUSE_SIZE
{ {
.cy_efuse +0 .cy_efuse +0
{ {
* (.cy_efuse) * (.cy_efuse)
} }
} }
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. ; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000 CYMETA 0x90500000
{ {
.cymeta +0 { * (.cymeta) } .cymeta +0 { * (.cymeta) }
} }
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
#define __cy_memory_0_start 0x10000000 #define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x00100000 #define __cy_memory_0_length 0x00100000
#define __cy_memory_0_row_size 0x200 #define __cy_memory_0_row_size 0x200
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
#define __cy_memory_1_start 0x14000000 #define __cy_memory_1_start 0x14000000
#define __cy_memory_1_length 0x8000 #define __cy_memory_1_length 0x8000
#define __cy_memory_1_row_size 0x200 #define __cy_memory_1_row_size 0x200
/* Supervisory Flash */ /* Supervisory Flash */
#define __cy_memory_2_start 0x16000000 #define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000 #define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200 #define __cy_memory_2_row_size 0x200
/* XIP */ /* XIP */
#define __cy_memory_3_start 0x18000000 #define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000 #define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200 #define __cy_memory_3_row_size 0x200
/* eFuse */ /* eFuse */
#define __cy_memory_4_start 0x90700000 #define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000 #define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1 #define __cy_memory_4_row_size 1
/* [] END OF FILE */ /* [] END OF FILE */

518
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4.sct
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@@ -1,259 +1,259 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cy8c6xx8_cm4.sct ;* \file cy8c6xx8_cm4.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM4 core. ; The following defines control RAM and flash memory allocation for the CM4 core.
; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use. ; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior. ; Using this memory region for other purposes will lead to unexpected behavior.
; RAM ; RAM
#define RAM_START 0x08000000 #define RAM_START 0x08000000
#define RAM_SIZE 0x0007F780 #define RAM_SIZE 0x0007F780
; Flash ; Flash
#define FLASH_START 0x10000000 #define FLASH_START 0x10000000
#define FLASH_SIZE 0x00100000 #define FLASH_SIZE 0x00100000
; The size of the stack section at the end of CM4 SRAM ; The size of the stack section at the end of CM4 SRAM
#define STACK_SIZE 0x00001000 #define STACK_SIZE 0x00001000
; The following defines describe a 32K flash region used for EEPROM emulation. ; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash. ; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores. ; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation. ; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000 #define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000 #define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data ; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800 #define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800 #define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00 #define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200 #define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key ; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00 #define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 #define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00 #define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200 #define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00 #define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200 #define SFLASH_RTOC_2_SIZE 0x00000200
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; eFuse ; eFuse
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Cortex-M4 application flash area ; Cortex-M4 application flash area
LR_IROM1 FLASH_START FLASH_SIZE LR_IROM1 FLASH_START FLASH_SIZE
{ {
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
{ {
} }
; Used for the digital signature of the secure application and the ; Used for the digital signature of the secure application and the
; Bootloader SDK application. The size of the section depends on the required ; Bootloader SDK application. The size of the section depends on the required
; data size. ; data size.
.cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
{ {
* (.cy_app_signature) * (.cy_app_signature)
} }
} }
; Emulated EEPROM Flash area ; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{ {
.cy_em_eeprom +0 .cy_em_eeprom +0
{ {
* (.cy_em_eeprom) * (.cy_em_eeprom)
} }
} }
; Supervisory flash: User data ; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{ {
.cy_sflash_user_data +0 .cy_sflash_user_data +0
{ {
* (.cy_sflash_user_data) * (.cy_sflash_user_data)
} }
} }
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{ {
.cy_sflash_nar +0 .cy_sflash_nar +0
{ {
* (.cy_sflash_nar) * (.cy_sflash_nar)
} }
} }
; Supervisory flash: Public Key ; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{ {
.cy_sflash_public_key +0 .cy_sflash_public_key +0
{ {
* (.cy_sflash_public_key) * (.cy_sflash_public_key)
} }
} }
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{ {
.cy_toc_part2 +0 .cy_toc_part2 +0
{ {
* (.cy_toc_part2) * (.cy_toc_part2)
} }
} }
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{ {
.cy_rtoc_part2 +0 .cy_rtoc_part2 +0
{ {
* (.cy_rtoc_part2) * (.cy_rtoc_part2)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
; eFuse ; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE LR_EFUSE EFUSE_START EFUSE_SIZE
{ {
.cy_efuse +0 .cy_efuse +0
{ {
* (.cy_efuse) * (.cy_efuse)
} }
} }
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. ; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000 CYMETA 0x90500000
{ {
.cymeta +0 { * (.cymeta) } .cymeta +0 { * (.cymeta) }
} }
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
#define __cy_memory_0_start 0x10000000 #define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x00100000 #define __cy_memory_0_length 0x00100000
#define __cy_memory_0_row_size 0x200 #define __cy_memory_0_row_size 0x200
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
#define __cy_memory_1_start 0x14000000 #define __cy_memory_1_start 0x14000000
#define __cy_memory_1_length 0x8000 #define __cy_memory_1_length 0x8000
#define __cy_memory_1_row_size 0x200 #define __cy_memory_1_row_size 0x200
/* Supervisory Flash */ /* Supervisory Flash */
#define __cy_memory_2_start 0x16000000 #define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000 #define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200 #define __cy_memory_2_row_size 0x200
/* XIP */ /* XIP */
#define __cy_memory_3_start 0x18000000 #define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000 #define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200 #define __cy_memory_3_row_size 0x200
/* eFuse */ /* eFuse */
#define __cy_memory_4_start 0x90700000 #define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000 #define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1 #define __cy_memory_4_row_size 1
/* [] END OF FILE */ /* [] END OF FILE */

554
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct
View File

@@ -1,277 +1,277 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cy8c6xx8_cm4_dual.sct ;* \file cy8c6xx8_cm4_dual.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM4 core. ; The following defines control RAM and flash memory allocation for the CM4 core.
; You can change the memory allocation by editing RAM and Flash defines. ; You can change the memory allocation by editing RAM and Flash defines.
; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. ; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior. ; Using this memory region for other purposes will lead to unexpected behavior.
; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', ; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. ; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
; RAM ; RAM
#define RAM_START 0x08002000 #define RAM_START 0x08002000
#define RAM_SIZE 0x0007D800 #define RAM_SIZE 0x0007D800
; Flash ; Flash
#define FLASH_START 0x10000000 #define FLASH_START 0x10000000
#define FLASH_SIZE 0x00100000 #define FLASH_SIZE 0x00100000
; The size of the stack section at the end of CM4 SRAM ; The size of the stack section at the end of CM4 SRAM
#define STACK_SIZE 0x00001000 #define STACK_SIZE 0x00001000
; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. ; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
; More about CM0+ prebuilt images, see here: ; More about CM0+ prebuilt images, see here:
; https://github.com/cypresssemiconductorco/psoc6cm0p ; https://github.com/cypresssemiconductorco/psoc6cm0p
; The size of the Cortex-M0+ application flash image ; The size of the Cortex-M0+ application flash image
#define FLASH_CM0P_SIZE 0x2000 #define FLASH_CM0P_SIZE 0x2000
; The following defines describe a 32K flash region used for EEPROM emulation. ; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash. ; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores. ; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation. ; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000 #define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000 #define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data ; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800 #define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800 #define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00 #define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200 #define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key ; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00 #define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 #define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00 #define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200 #define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00 #define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200 #define SFLASH_RTOC_2_SIZE 0x00000200
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; eFuse ; eFuse
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Cortex-M0+ application flash image area ; Cortex-M0+ application flash image area
LR_IROM FLASH_START FLASH_CM0P_SIZE LR_IROM FLASH_START FLASH_CM0P_SIZE
{ {
.cy_m0p_image +0 FLASH_CM0P_SIZE .cy_m0p_image +0 FLASH_CM0P_SIZE
{ {
* (.cy_m0p_image) * (.cy_m0p_image)
} }
} }
; Cortex-M4 application flash area ; Cortex-M4 application flash area
LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
{ {
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
{ {
} }
; Used for the digital signature of the secure application and the ; Used for the digital signature of the secure application and the
; Bootloader SDK application. The size of the section depends on the required ; Bootloader SDK application. The size of the section depends on the required
; data size. ; data size.
.cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
{ {
* (.cy_app_signature) * (.cy_app_signature)
} }
} }
; Emulated EEPROM Flash area ; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{ {
.cy_em_eeprom +0 .cy_em_eeprom +0
{ {
* (.cy_em_eeprom) * (.cy_em_eeprom)
} }
} }
; Supervisory flash: User data ; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{ {
.cy_sflash_user_data +0 .cy_sflash_user_data +0
{ {
* (.cy_sflash_user_data) * (.cy_sflash_user_data)
} }
} }
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{ {
.cy_sflash_nar +0 .cy_sflash_nar +0
{ {
* (.cy_sflash_nar) * (.cy_sflash_nar)
} }
} }
; Supervisory flash: Public Key ; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{ {
.cy_sflash_public_key +0 .cy_sflash_public_key +0
{ {
* (.cy_sflash_public_key) * (.cy_sflash_public_key)
} }
} }
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{ {
.cy_toc_part2 +0 .cy_toc_part2 +0
{ {
* (.cy_toc_part2) * (.cy_toc_part2)
} }
} }
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{ {
.cy_rtoc_part2 +0 .cy_rtoc_part2 +0
{ {
* (.cy_rtoc_part2) * (.cy_rtoc_part2)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
; eFuse ; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE LR_EFUSE EFUSE_START EFUSE_SIZE
{ {
.cy_efuse +0 .cy_efuse +0
{ {
* (.cy_efuse) * (.cy_efuse)
} }
} }
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. ; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000 CYMETA 0x90500000
{ {
.cymeta +0 { * (.cymeta) } .cymeta +0 { * (.cymeta) }
} }
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
#define __cy_memory_0_start 0x10000000 #define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x00100000 #define __cy_memory_0_length 0x00100000
#define __cy_memory_0_row_size 0x200 #define __cy_memory_0_row_size 0x200
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
#define __cy_memory_1_start 0x14000000 #define __cy_memory_1_start 0x14000000
#define __cy_memory_1_length 0x8000 #define __cy_memory_1_length 0x8000
#define __cy_memory_1_row_size 0x200 #define __cy_memory_1_row_size 0x200
/* Supervisory Flash */ /* Supervisory Flash */
#define __cy_memory_2_start 0x16000000 #define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000 #define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200 #define __cy_memory_2_row_size 0x200
/* XIP */ /* XIP */
#define __cy_memory_3_start 0x18000000 #define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000 #define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200 #define __cy_memory_3_row_size 0x200
/* eFuse */ /* eFuse */
#define __cy_memory_4_start 0x90700000 #define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000 #define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1 #define __cy_memory_4_row_size 1
/* [] END OF FILE */ /* [] END OF FILE */

518
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4.sct
View File

@@ -1,259 +1,259 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cy8c6xxa_cm4.sct ;* \file cy8c6xxa_cm4.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM4 core. ; The following defines control RAM and flash memory allocation for the CM4 core.
; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use. ; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior. ; Using this memory region for other purposes will lead to unexpected behavior.
; RAM ; RAM
#define RAM_START 0x08000000 #define RAM_START 0x08000000
#define RAM_SIZE 0x000FF780 #define RAM_SIZE 0x000FF780
; Flash ; Flash
#define FLASH_START 0x10000000 #define FLASH_START 0x10000000
#define FLASH_SIZE 0x00200000 #define FLASH_SIZE 0x00200000
; The size of the stack section at the end of CM4 SRAM ; The size of the stack section at the end of CM4 SRAM
#define STACK_SIZE 0x00001000 #define STACK_SIZE 0x00001000
; The following defines describe a 32K flash region used for EEPROM emulation. ; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash. ; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores. ; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation. ; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000 #define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000 #define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data ; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800 #define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800 #define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00 #define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200 #define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key ; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00 #define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 #define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00 #define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200 #define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00 #define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200 #define SFLASH_RTOC_2_SIZE 0x00000200
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; eFuse ; eFuse
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Cortex-M4 application flash area ; Cortex-M4 application flash area
LR_IROM1 FLASH_START FLASH_SIZE LR_IROM1 FLASH_START FLASH_SIZE
{ {
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
{ {
} }
; Used for the digital signature of the secure application and the ; Used for the digital signature of the secure application and the
; Bootloader SDK application. The size of the section depends on the required ; Bootloader SDK application. The size of the section depends on the required
; data size. ; data size.
.cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
{ {
* (.cy_app_signature) * (.cy_app_signature)
} }
} }
; Emulated EEPROM Flash area ; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{ {
.cy_em_eeprom +0 .cy_em_eeprom +0
{ {
* (.cy_em_eeprom) * (.cy_em_eeprom)
} }
} }
; Supervisory flash: User data ; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{ {
.cy_sflash_user_data +0 .cy_sflash_user_data +0
{ {
* (.cy_sflash_user_data) * (.cy_sflash_user_data)
} }
} }
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{ {
.cy_sflash_nar +0 .cy_sflash_nar +0
{ {
* (.cy_sflash_nar) * (.cy_sflash_nar)
} }
} }
; Supervisory flash: Public Key ; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{ {
.cy_sflash_public_key +0 .cy_sflash_public_key +0
{ {
* (.cy_sflash_public_key) * (.cy_sflash_public_key)
} }
} }
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{ {
.cy_toc_part2 +0 .cy_toc_part2 +0
{ {
* (.cy_toc_part2) * (.cy_toc_part2)
} }
} }
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{ {
.cy_rtoc_part2 +0 .cy_rtoc_part2 +0
{ {
* (.cy_rtoc_part2) * (.cy_rtoc_part2)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
; eFuse ; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE LR_EFUSE EFUSE_START EFUSE_SIZE
{ {
.cy_efuse +0 .cy_efuse +0
{ {
* (.cy_efuse) * (.cy_efuse)
} }
} }
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. ; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000 CYMETA 0x90500000
{ {
.cymeta +0 { * (.cymeta) } .cymeta +0 { * (.cymeta) }
} }
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
#define __cy_memory_0_start 0x10000000 #define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x00200000 #define __cy_memory_0_length 0x00200000
#define __cy_memory_0_row_size 0x200 #define __cy_memory_0_row_size 0x200
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
#define __cy_memory_1_start 0x14000000 #define __cy_memory_1_start 0x14000000
#define __cy_memory_1_length 0x8000 #define __cy_memory_1_length 0x8000
#define __cy_memory_1_row_size 0x200 #define __cy_memory_1_row_size 0x200
/* Supervisory Flash */ /* Supervisory Flash */
#define __cy_memory_2_start 0x16000000 #define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000 #define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200 #define __cy_memory_2_row_size 0x200
/* XIP */ /* XIP */
#define __cy_memory_3_start 0x18000000 #define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000 #define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200 #define __cy_memory_3_row_size 0x200
/* eFuse */ /* eFuse */
#define __cy_memory_4_start 0x90700000 #define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000 #define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1 #define __cy_memory_4_row_size 1
/* [] END OF FILE */ /* [] END OF FILE */

554
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct
View File

@@ -1,277 +1,277 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cy8c6xxa_cm4_dual.sct ;* \file cy8c6xxa_cm4_dual.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM4 core. ; The following defines control RAM and flash memory allocation for the CM4 core.
; You can change the memory allocation by editing RAM and Flash defines. ; You can change the memory allocation by editing RAM and Flash defines.
; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. ; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior. ; Using this memory region for other purposes will lead to unexpected behavior.
; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', ; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. ; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
; RAM ; RAM
#define RAM_START 0x08002000 #define RAM_START 0x08002000
#define RAM_SIZE 0x000FD800 #define RAM_SIZE 0x000FD800
; Flash ; Flash
#define FLASH_START 0x10000000 #define FLASH_START 0x10000000
#define FLASH_SIZE 0x00200000 #define FLASH_SIZE 0x00200000
; The size of the stack section at the end of CM4 SRAM ; The size of the stack section at the end of CM4 SRAM
#define STACK_SIZE 0x00001000 #define STACK_SIZE 0x00001000
; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. ; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
; More about CM0+ prebuilt images, see here: ; More about CM0+ prebuilt images, see here:
; https://github.com/cypresssemiconductorco/psoc6cm0p ; https://github.com/cypresssemiconductorco/psoc6cm0p
; The size of the Cortex-M0+ application flash image ; The size of the Cortex-M0+ application flash image
#define FLASH_CM0P_SIZE 0x2000 #define FLASH_CM0P_SIZE 0x2000
; The following defines describe a 32K flash region used for EEPROM emulation. ; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash. ; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores. ; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation. ; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000 #define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000 #define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data ; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800 #define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800 #define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00 #define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200 #define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key ; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00 #define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 #define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00 #define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200 #define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00 #define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200 #define SFLASH_RTOC_2_SIZE 0x00000200
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; eFuse ; eFuse
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Cortex-M0+ application flash image area ; Cortex-M0+ application flash image area
LR_IROM FLASH_START FLASH_CM0P_SIZE LR_IROM FLASH_START FLASH_CM0P_SIZE
{ {
.cy_m0p_image +0 FLASH_CM0P_SIZE .cy_m0p_image +0 FLASH_CM0P_SIZE
{ {
* (.cy_m0p_image) * (.cy_m0p_image)
} }
} }
; Cortex-M4 application flash area ; Cortex-M4 application flash area
LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
{ {
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
{ {
} }
; Used for the digital signature of the secure application and the ; Used for the digital signature of the secure application and the
; Bootloader SDK application. The size of the section depends on the required ; Bootloader SDK application. The size of the section depends on the required
; data size. ; data size.
.cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
{ {
* (.cy_app_signature) * (.cy_app_signature)
} }
} }
; Emulated EEPROM Flash area ; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{ {
.cy_em_eeprom +0 .cy_em_eeprom +0
{ {
* (.cy_em_eeprom) * (.cy_em_eeprom)
} }
} }
; Supervisory flash: User data ; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{ {
.cy_sflash_user_data +0 .cy_sflash_user_data +0
{ {
* (.cy_sflash_user_data) * (.cy_sflash_user_data)
} }
} }
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{ {
.cy_sflash_nar +0 .cy_sflash_nar +0
{ {
* (.cy_sflash_nar) * (.cy_sflash_nar)
} }
} }
; Supervisory flash: Public Key ; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{ {
.cy_sflash_public_key +0 .cy_sflash_public_key +0
{ {
* (.cy_sflash_public_key) * (.cy_sflash_public_key)
} }
} }
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{ {
.cy_toc_part2 +0 .cy_toc_part2 +0
{ {
* (.cy_toc_part2) * (.cy_toc_part2)
} }
} }
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{ {
.cy_rtoc_part2 +0 .cy_rtoc_part2 +0
{ {
* (.cy_rtoc_part2) * (.cy_rtoc_part2)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
; eFuse ; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE LR_EFUSE EFUSE_START EFUSE_SIZE
{ {
.cy_efuse +0 .cy_efuse +0
{ {
* (.cy_efuse) * (.cy_efuse)
} }
} }
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. ; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000 CYMETA 0x90500000
{ {
.cymeta +0 { * (.cymeta) } .cymeta +0 { * (.cymeta) }
} }
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
#define __cy_memory_0_start 0x10000000 #define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x00200000 #define __cy_memory_0_length 0x00200000
#define __cy_memory_0_row_size 0x200 #define __cy_memory_0_row_size 0x200
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
#define __cy_memory_1_start 0x14000000 #define __cy_memory_1_start 0x14000000
#define __cy_memory_1_length 0x8000 #define __cy_memory_1_length 0x8000
#define __cy_memory_1_row_size 0x200 #define __cy_memory_1_row_size 0x200
/* Supervisory Flash */ /* Supervisory Flash */
#define __cy_memory_2_start 0x16000000 #define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000 #define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200 #define __cy_memory_2_row_size 0x200
/* XIP */ /* XIP */
#define __cy_memory_3_start 0x18000000 #define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000 #define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200 #define __cy_memory_3_row_size 0x200
/* eFuse */ /* eFuse */
#define __cy_memory_4_start 0x90700000 #define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000 #define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1 #define __cy_memory_4_row_size 1
/* [] END OF FILE */ /* [] END OF FILE */

266
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4.sct
View File

@@ -1,133 +1,133 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cyb06xx5_cm4.sct ;* \file cyb06xx5_cm4.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10020000. The valid ;* \note The entry point location is fixed and starts at 0x10020000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM4 core. ; The following defines control RAM and flash memory allocation for the CM4 core.
; RAM ; RAM
#define RAM_START 0x08001800 #define RAM_START 0x08001800
#define RAM_SIZE 0x0001E800 #define RAM_SIZE 0x0001E800
; Flash ; Flash
#define FLASH_START 0x10020000 #define FLASH_START 0x10020000
#define FLASH_SIZE 0x00020000 #define FLASH_SIZE 0x00020000
; The size of the stack section at the end of CM4 SRAM ; The size of the stack section at the end of CM4 SRAM
#define STACK_SIZE 0x00001000 #define STACK_SIZE 0x00001000
; The size of the MCU boot header area at the start of FLASH ; The size of the MCU boot header area at the start of FLASH
#define BOOT_HEADER_SIZE 0x00000400 #define BOOT_HEADER_SIZE 0x00000400
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; Cortex-M4 application flash area ; Cortex-M4 application flash area
LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE) LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE)
{ {
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
{ {
} }
; Used for the digital signature of the secure application and the ; Used for the digital signature of the secure application and the
; Bootloader SDK application. The size of the section depends on the required ; Bootloader SDK application. The size of the section depends on the required
; data size. ; data size.
.cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
{ {
* (.cy_app_signature) * (.cy_app_signature)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
/* [] END OF FILE */ /* [] END OF FILE */

294
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4_dual.sct
View File

@@ -1,147 +1,147 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cyb06xx5_cm4_dual.sct ;* \file cyb06xx5_cm4_dual.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM4 core. ; The following defines control RAM and flash memory allocation for the CM4 core.
; You can change the memory allocation by editing RAM and Flash defines. ; You can change the memory allocation by editing RAM and Flash defines.
; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', ; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'. ; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'.
; RAM ; RAM
#define RAM_START 0x08000800 #define RAM_START 0x08000800
#define RAM_SIZE 0x0001F800 #define RAM_SIZE 0x0001F800
; Flash ; Flash
#define FLASH_START 0x10000000 #define FLASH_START 0x10000000
#define FLASH_SIZE 0x00030000 #define FLASH_SIZE 0x00030000
; The size of the stack section at the end of CM4 SRAM ; The size of the stack section at the end of CM4 SRAM
#define STACK_SIZE 0x00001000 #define STACK_SIZE 0x00001000
; The size of the MCU boot header area at the start of FLASH ; The size of the MCU boot header area at the start of FLASH
#define BOOT_HEADER_SIZE 0x00000400 #define BOOT_HEADER_SIZE 0x00000400
; The size of the Cortex-M0+ application image (including MCU boot header area) ; The size of the Cortex-M0+ application image (including MCU boot header area)
#define FLASH_CM0P_SIZE 0x10000 #define FLASH_CM0P_SIZE 0x10000
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; Cortex-M0+ application flash image area ; Cortex-M0+ application flash image area
LR_IROM (FLASH_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE) LR_IROM (FLASH_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE)
{ {
.cy_m0p_image +0 .cy_m0p_image +0
{ {
* (.cy_m0p_image) * (.cy_m0p_image)
} }
} }
; Cortex-M4 application flash area ; Cortex-M4 application flash area
LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
{ {
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
{ {
} }
; Used for the digital signature of the secure application and the ; Used for the digital signature of the secure application and the
; Bootloader SDK application. The size of the section depends on the required ; Bootloader SDK application. The size of the section depends on the required
; data size. ; data size.
.cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
{ {
* (.cy_app_signature) * (.cy_app_signature)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
/* [] END OF FILE */ /* [] END OF FILE */

296
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4.sct
View File

@@ -1,148 +1,148 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cyb06xx7_cm4.sct ;* \file cyb06xx7_cm4.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10060000. The valid ;* \note The entry point location is fixed and starts at 0x10060000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM4 core. ; The following defines control RAM and flash memory allocation for the CM4 core.
; RAM ; RAM
#define RAM_START 0x08001800 #define RAM_START 0x08001800
#define RAM_SIZE 0x0001E800 #define RAM_SIZE 0x0001E800
; Flash ; Flash
#define FLASH_START 0x10060000 #define FLASH_START 0x10060000
#define FLASH_SIZE 0x00030000 #define FLASH_SIZE 0x00030000
; The size of the stack section at the end of CM4 SRAM ; The size of the stack section at the end of CM4 SRAM
#define STACK_SIZE 0x00001000 #define STACK_SIZE 0x00001000
; The size of the MCU boot header area at the start of FLASH ; The size of the MCU boot header area at the start of FLASH
#define BOOT_HEADER_SIZE 0x00000400 #define BOOT_HEADER_SIZE 0x00000400
; The following defines describe a 32K flash region used for EEPROM emulation. ; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash. ; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores. ; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation. ; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000 #define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000 #define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; Cortex-M4 application flash area ; Cortex-M4 application flash area
LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE) LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE)
{ {
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
{ {
} }
; Used for the digital signature of the secure application and the ; Used for the digital signature of the secure application and the
; Bootloader SDK application. The size of the section depends on the required ; Bootloader SDK application. The size of the section depends on the required
; data size. ; data size.
.cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
{ {
* (.cy_app_signature) * (.cy_app_signature)
} }
} }
; Emulated EEPROM Flash area ; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{ {
.cy_em_eeprom +0 .cy_em_eeprom +0
{ {
* (.cy_em_eeprom) * (.cy_em_eeprom)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
/* [] END OF FILE */ /* [] END OF FILE */

324
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct
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@@ -1,162 +1,162 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cyb06xx7_cm4_dual.sct ;* \file cyb06xx7_cm4_dual.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM4 core. ; The following defines control RAM and flash memory allocation for the CM4 core.
; You can change the memory allocation by editing RAM and Flash defines. ; You can change the memory allocation by editing RAM and Flash defines.
; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', ; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'. ; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'.
; RAM ; RAM
#define RAM_START 0x08000800 #define RAM_START 0x08000800
#define RAM_SIZE 0x0001F800 #define RAM_SIZE 0x0001F800
; Flash ; Flash
#define FLASH_START 0x10000000 #define FLASH_START 0x10000000
#define FLASH_SIZE 0x00068000 #define FLASH_SIZE 0x00068000
; The size of the stack section at the end of CM4 SRAM ; The size of the stack section at the end of CM4 SRAM
#define STACK_SIZE 0x00001000 #define STACK_SIZE 0x00001000
; The size of the MCU boot header area at the start of FLASH ; The size of the MCU boot header area at the start of FLASH
#define BOOT_HEADER_SIZE 0x00000400 #define BOOT_HEADER_SIZE 0x00000400
; The size of the Cortex-M0+ application image (including MCU boot header area) ; The size of the Cortex-M0+ application image (including MCU boot header area)
#define FLASH_CM0P_SIZE 0x10000 #define FLASH_CM0P_SIZE 0x10000
; The following defines describe a 32K flash region used for EEPROM emulation. ; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash. ; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores. ; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation. ; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000 #define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000 #define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; Cortex-M0+ application flash image area ; Cortex-M0+ application flash image area
LR_IROM (FLASH_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE) LR_IROM (FLASH_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE)
{ {
.cy_m0p_image +0 .cy_m0p_image +0
{ {
* (.cy_m0p_image) * (.cy_m0p_image)
} }
} }
; Cortex-M4 application flash area ; Cortex-M4 application flash area
LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
{ {
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
{ {
} }
; Used for the digital signature of the secure application and the ; Used for the digital signature of the secure application and the
; Bootloader SDK application. The size of the section depends on the required ; Bootloader SDK application. The size of the section depends on the required
; data size. ; data size.
.cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
{ {
* (.cy_app_signature) * (.cy_app_signature)
} }
} }
; Emulated EEPROM Flash area ; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{ {
.cy_em_eeprom +0 .cy_em_eeprom +0
{ {
* (.cy_em_eeprom) * (.cy_em_eeprom)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
/* [] END OF FILE */ /* [] END OF FILE */

296
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct
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@@ -1,148 +1,148 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cyb06xxa_cm4.sct ;* \file cyb06xxa_cm4.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x100E0000. The valid ;* \note The entry point location is fixed and starts at 0x100E0000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM4 core. ; The following defines control RAM and flash memory allocation for the CM4 core.
; RAM ; RAM
#define RAM_START 0x08001800 #define RAM_START 0x08001800
#define RAM_SIZE 0x000DE800 #define RAM_SIZE 0x000DE800
; Flash ; Flash
#define FLASH_START 0x100E0000 #define FLASH_START 0x100E0000
#define FLASH_SIZE 0x00070000 #define FLASH_SIZE 0x00070000
; The size of the stack section at the end of CM4 SRAM ; The size of the stack section at the end of CM4 SRAM
#define STACK_SIZE 0x00001000 #define STACK_SIZE 0x00001000
; The size of the MCU boot header area at the start of FLASH ; The size of the MCU boot header area at the start of FLASH
#define BOOT_HEADER_SIZE 0x00000400 #define BOOT_HEADER_SIZE 0x00000400
; The following defines describe a 32K flash region used for EEPROM emulation. ; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash. ; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores. ; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation. ; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000 #define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000 #define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; Cortex-M4 application flash area ; Cortex-M4 application flash area
LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE) LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE)
{ {
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
{ {
} }
; Used for the digital signature of the secure application and the ; Used for the digital signature of the secure application and the
; Bootloader SDK application. The size of the section depends on the required ; Bootloader SDK application. The size of the section depends on the required
; data size. ; data size.
.cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
{ {
* (.cy_app_signature) * (.cy_app_signature)
} }
} }
; Emulated EEPROM Flash area ; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{ {
.cy_em_eeprom +0 .cy_em_eeprom +0
{ {
* (.cy_em_eeprom) * (.cy_em_eeprom)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
/* [] END OF FILE */ /* [] END OF FILE */

324
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct
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@@ -1,162 +1,162 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cyb06xxa_cm4_dual.sct ;* \file cyb06xxa_cm4_dual.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM4 core. ; The following defines control RAM and flash memory allocation for the CM4 core.
; You can change the memory allocation by editing RAM and Flash defines. ; You can change the memory allocation by editing RAM and Flash defines.
; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', ; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'. ; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'.
; RAM ; RAM
#define RAM_START 0x08000800 #define RAM_START 0x08000800
#define RAM_SIZE 0x000DF800 #define RAM_SIZE 0x000DF800
; Flash ; Flash
#define FLASH_START 0x10000000 #define FLASH_START 0x10000000
#define FLASH_SIZE 0x000E0000 #define FLASH_SIZE 0x000E0000
; The size of the stack section at the end of CM4 SRAM ; The size of the stack section at the end of CM4 SRAM
#define STACK_SIZE 0x00001000 #define STACK_SIZE 0x00001000
; The size of the MCU boot header area at the start of FLASH ; The size of the MCU boot header area at the start of FLASH
#define BOOT_HEADER_SIZE 0x00000400 #define BOOT_HEADER_SIZE 0x00000400
; The size of the Cortex-M0+ application image (including MCU boot header area) ; The size of the Cortex-M0+ application image (including MCU boot header area)
#define FLASH_CM0P_SIZE 0x10000 #define FLASH_CM0P_SIZE 0x10000
; The following defines describe a 32K flash region used for EEPROM emulation. ; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash. ; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores. ; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation. ; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000 #define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000 #define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; Cortex-M0+ application flash image area ; Cortex-M0+ application flash image area
LR_IROM (FLASH_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE) LR_IROM (FLASH_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE)
{ {
.cy_m0p_image +0 .cy_m0p_image +0
{ {
* (.cy_m0p_image) * (.cy_m0p_image)
} }
} }
; Cortex-M4 application flash area ; Cortex-M4 application flash area
LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
{ {
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
{ {
} }
; Used for the digital signature of the secure application and the ; Used for the digital signature of the secure application and the
; Bootloader SDK application. The size of the section depends on the required ; Bootloader SDK application. The size of the section depends on the required
; data size. ; data size.
.cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
{ {
* (.cy_app_signature) * (.cy_app_signature)
} }
} }
; Emulated EEPROM Flash area ; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{ {
.cy_em_eeprom +0 .cy_em_eeprom +0
{ {
* (.cy_em_eeprom) * (.cy_em_eeprom)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
/* [] END OF FILE */ /* [] END OF FILE */

296
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cys06xxa_cm4.sct
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@@ -1,148 +1,148 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cys06xxa_cm4.sct ;* \file cys06xxa_cm4.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10050000. The valid ;* \note The entry point location is fixed and starts at 0x10050000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM4 core. ; The following defines control RAM and flash memory allocation for the CM4 core.
; RAM ; RAM
#define RAM_START 0x08030000 #define RAM_START 0x08030000
#define RAM_SIZE 0x000B7000 #define RAM_SIZE 0x000B7000
; Flash ; Flash
#define FLASH_START 0x10050000 #define FLASH_START 0x10050000
#define FLASH_SIZE 0x0011C000 #define FLASH_SIZE 0x0011C000
; The size of the stack section at the end of CM4 SRAM ; The size of the stack section at the end of CM4 SRAM
#define STACK_SIZE 0x00001000 #define STACK_SIZE 0x00001000
; The size of the MCU boot header area at the start of FLASH ; The size of the MCU boot header area at the start of FLASH
#define BOOT_HEADER_SIZE 0x00000400 #define BOOT_HEADER_SIZE 0x00000400
; The following defines describe a 32K flash region used for EEPROM emulation. ; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash. ; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores. ; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation. ; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000 #define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000 #define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; Cortex-M4 application flash area ; Cortex-M4 application flash area
LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE) LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE)
{ {
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
{ {
} }
; Used for the digital signature of the secure application and the ; Used for the digital signature of the secure application and the
; Bootloader SDK application. The size of the section depends on the required ; Bootloader SDK application. The size of the section depends on the required
; data size. ; data size.
.cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
{ {
* (.cy_app_signature) * (.cy_app_signature)
} }
} }
; Emulated EEPROM Flash area ; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{ {
.cy_em_eeprom +0 .cy_em_eeprom +0
{ {
* (.cy_em_eeprom) * (.cy_em_eeprom)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
/* [] END OF FILE */ /* [] END OF FILE */

318
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1B/templates/COMPONENT_MTB/COMPONENT_CM33/TOOLCHAIN_ARM/cyw20829_ns_flash_cbus.sct
View File

@@ -1,159 +1,159 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m33 -march=armv8-m.main #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m33 -march=armv8-m.main
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
/***************************************************************************//** /***************************************************************************//**
* \file cyw20829_ns_flash_cbus.sct * \file cyw20829_ns_flash_cbus.sct
* \version 1.0.0 * \version 1.0.0
* *
* Linker file for the ARMCC compiler. * Linker file for the ARMCC compiler.
* *
* The main purpose of the linker script is to describe how the sections in the * The main purpose of the linker script is to describe how the sections in the
* input files should be mapped into the output file, and to control the memory * input files should be mapped into the output file, and to control the memory
* layout of the output file. * layout of the output file.
* *
* \note The entry point location starts at 0x0401e000. The valid * \note The entry point location starts at 0x0401e000. The valid
* application image should be placed there. * application image should be placed there.
* *
* \note The linker files included with the PDL template projects must be generic * \note The linker files included with the PDL template projects must be generic
* and handle all common use cases. Your project may not use every section * and handle all common use cases. Your project may not use every section
* defined in the linker files. In that case you may see warnings during the * defined in the linker files. In that case you may see warnings during the
* build process. In your project, you can simply comment out or remove the * build process. In your project, you can simply comment out or remove the
* relevant code in the linker file. * relevant code in the linker file.
* *
******************************************************************************** ********************************************************************************
* \copyright * \copyright
* Copyright (c) (2020-2022), Cypress Semiconductor Corporation (an Infineon company) or * Copyright (c) (2020-2022), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation. * an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Licensed under the Apache License, Version 2.0 (the "License"); * Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License. * you may not use this file except in compliance with the License.
* You may obtain a copy of the License at * You may obtain a copy of the License at
* *
* http://www.apache.org/licenses/LICENSE-2.0 * http://www.apache.org/licenses/LICENSE-2.0
* *
* Unless required by applicable law or agreed to in writing, software * Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, * distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and * See the License for the specific language governing permissions and
* limitations under the License. * limitations under the License.
*******************************************************************************/ *******************************************************************************/
#define flash_start_addr_cbus 0x08000000 #define flash_start_addr_cbus 0x08000000
#define ram_start_addr_sahb 0x20000000 #define ram_start_addr_sahb 0x20000000
#define ram_start_addr_cbus 0x04000000 #define ram_start_addr_cbus 0x04000000
#define ram_end_addr_sahb 0x20020000 #define ram_end_addr_sahb 0x20020000
#define app_code_offset_flash 0x00002200 #define app_code_offset_flash 0x00002200
#define bootstrap_offset_ram 0x0001E000 #define bootstrap_offset_ram 0x0001E000
; The size of the stack section at the end of CM33 SRAM ; The size of the stack section at the end of CM33 SRAM
#define STACK_SIZE 0x00001000 #define STACK_SIZE 0x00001000
/* VMA for bootstrap Text */ /* VMA for bootstrap Text */
#define bootstrapText_vma ram_start_addr_cbus + bootstrap_offset_ram /* 0x0401E000 */ #define bootstrapText_vma ram_start_addr_cbus + bootstrap_offset_ram /* 0x0401E000 */
/* Size of bootstrap section */ /* Size of bootstrap section */
#define bootstrapText_size 0x00002000 #define bootstrapText_size 0x00002000
/* VMA for bootstrap Data */ /* VMA for bootstrap Data */
#define bootstrapRamVect_vma ram_start_addr_sahb + STACK_SIZE /* 0x20001000 */ #define bootstrapRamVect_vma ram_start_addr_sahb + STACK_SIZE /* 0x20001000 */
/* VMA for flash */ /* VMA for flash */
#define appText_vma flash_start_addr_cbus + app_code_offset_flash /* 0x08002200 */ #define appText_vma flash_start_addr_cbus + app_code_offset_flash /* 0x08002200 */
/* Memory reserved for Bootstrap code and data */ /* Memory reserved for Bootstrap code and data */
#define BOOTSTRAP_SIZE ram_end_addr_sahb - ram_start_addr_sahb - bootstrap_offset_ram; /* 0x00002000 */ #define BOOTSTRAP_SIZE ram_end_addr_sahb - ram_start_addr_sahb - bootstrap_offset_ram; /* 0x00002000 */
; Cortex-M33 application flash area ; Cortex-M33 application flash area
LR_1 bootstrapText_vma BOOTSTRAP_SIZE LR_1 bootstrapText_vma BOOTSTRAP_SIZE
{ {
bootstrap bootstrapText_vma bootstrapText_size bootstrap bootstrapText_vma bootstrapText_size
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
* (InRoot$$Sections) * (InRoot$$Sections)
ns_start_cyw20829.o (+RO) ns_start_cyw20829.o (+RO)
ns_system_cyw20829.o (+RO) ns_system_cyw20829.o (+RO)
/* drivers */ /* drivers */
cy_device.o (+RO) cy_device.o (+RO)
cy_btss.o (+RO) cy_btss.o (+RO)
cy_sysclk_v2.o (+RO) cy_sysclk_v2.o (+RO)
cy_syspm_v2.o (+RO) cy_syspm_v2.o (+RO)
cy_sysint_v2.o (+RO) cy_sysint_v2.o (+RO)
cy_syslib*.o (+RO) cy_syslib*.o (+RO)
ppu_v1.o (+RO) ppu_v1.o (+RO)
cy_mpc.o (+RO) cy_mpc.o (+RO)
cy_pd_ppu.o (+RO) cy_pd_ppu.o (+RO)
*(.cy_l1func*) *(.cy_l1func*)
} }
/* converting c-bus to sahb address */ /* converting c-bus to sahb address */
#define bootstrapData_vma AlignExpr((ImageLimit(bootstrap) - ram_start_addr_cbus) + ram_start_addr_sahb, 4) #define bootstrapData_vma AlignExpr((ImageLimit(bootstrap) - ram_start_addr_cbus) + ram_start_addr_sahb, 4)
bootstrapData bootstrapData_vma ALIGN 4 bootstrapData bootstrapData_vma ALIGN 4
{ {
ns_start_cyw20829.o (+RW, +ZI) ns_start_cyw20829.o (+RW, +ZI)
ns_system_cyw20829.o (+RW, +ZI) ns_system_cyw20829.o (+RW, +ZI)
/* drivers */ /* drivers */
cy_device.o (+RW, +ZI) cy_device.o (+RW, +ZI)
cy_btss.o (+RW, +ZI) cy_btss.o (+RW, +ZI)
cy_sysclk_v2.o (+RW, +ZI) cy_sysclk_v2.o (+RW, +ZI)
cy_syspm_v2.o (+RW, +ZI) cy_syspm_v2.o (+RW, +ZI)
cy_sysint_v2.o (+RW, +ZI) cy_sysint_v2.o (+RW, +ZI)
cy_syslib*.o (+RW, +ZI) cy_syslib*.o (+RW, +ZI)
ppu_v1.o (+RW, +ZI) ppu_v1.o (+RW, +ZI)
cy_mpc.o (+RW, +ZI) cy_mpc.o (+RW, +ZI)
cy_pd_ppu.o (+RW, +ZI) cy_pd_ppu.o (+RW, +ZI)
} }
bootstrap_vector bootstrapRamVect_vma UNINIT bootstrap_vector bootstrapRamVect_vma UNINIT
{ {
* (.bss.noinit.RESET_RAM, +FIRST) * (.bss.noinit.RESET_RAM, +FIRST)
} }
} }
#define appTextRam_vma AlignExpr(ImageLimit( bootstrap_vector), 8) #define appTextRam_vma AlignExpr(ImageLimit( bootstrap_vector), 8)
LR_2 appText_vma LR_2 appText_vma
{ {
app appText_vma app appText_vma
{ {
* (+RO) * (+RO)
} }
appTextRam appTextRam_vma appTextRam appTextRam_vma
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
cy_smif.o (+RO) cy_smif.o (+RO)
cy_smif_memslot.o (+RO) cy_smif_memslot.o (+RO)
} }
#define appData_vma AlignExpr((ImageLimit(appTextRam) - ImageBase(appTextRam) + ImageLimit(bootstrap_vector)), 8) #define appData_vma AlignExpr((ImageLimit(appTextRam) - ImageBase(appTextRam) + ImageLimit(bootstrap_vector)), 8)
appData appData_vma appData appData_vma
{ {
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
appData_noinit +0 UNINIT appData_noinit +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 ALIGN 8 EMPTY ((ram_start_addr_sahb + bootstrap_offset_ram)-AlignExpr(ImageLimit(appData_noinit), 8)) ARM_LIB_HEAP +0 ALIGN 8 EMPTY ((ram_start_addr_sahb + bootstrap_offset_ram)-AlignExpr(ImageLimit(appData_noinit), 8))
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK (ram_start_addr_sahb + STACK_SIZE) ALIGN 32 EMPTY -STACK_SIZE ARM_LIB_STACK (ram_start_addr_sahb + STACK_SIZE) ALIGN 32 EMPTY -STACK_SIZE
{ {
} }
} }
/* [] END OF FILE */ /* [] END OF FILE */

326
bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1B/templates/COMPONENT_MTB/COMPONENT_CM33/TOOLCHAIN_ARM/cyw20829_ns_ram_cbus.sct
View File

@@ -1,163 +1,163 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m33 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m33
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cyw20829_ns.sct ;* \file cyw20829_ns.sct
;* \version 1.0.0 ;* \version 1.0.0
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* Copyright 2016-2020 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM33 core. ; The following defines control RAM and flash memory allocation for the CM33 core.
; RAM ; RAM
#define CODE_ROM_NS_CBUS_START 0x00000000 #define CODE_ROM_NS_CBUS_START 0x00000000
#define CODE_ROM_NS_CBUS_SIZE 0x00010000 #define CODE_ROM_NS_CBUS_SIZE 0x00010000
#define CODE_SRAM0_NS_CBUS_START 0x04004200 #define CODE_SRAM0_NS_CBUS_START 0x04004200
#define CODE_SRAM0_NS_CBUS_SIZE 0x0000E000 #define CODE_SRAM0_NS_CBUS_SIZE 0x0000E000
#define CODE_XIP_NS_CBUS_START 0x08000000 #define CODE_XIP_NS_CBUS_START 0x08000000
#define CODE_XIP_NS_CBUS_SIZE 0x08000000 #define CODE_XIP_NS_CBUS_SIZE 0x08000000
#define DATA_ROM_NS_SAHB_START 0x00000000 #define DATA_ROM_NS_SAHB_START 0x00000000
#define DATA_ROM_NS_SAHB_SIZE 0x00000000 #define DATA_ROM_NS_SAHB_SIZE 0x00000000
#define BSS_ROM_NS_SAHB_START 0x00000000 #define BSS_ROM_NS_SAHB_START 0x00000000
#define BSS_ROM_NS_SAHB_SIZE 0x00000000 #define BSS_ROM_NS_SAHB_SIZE 0x00000000
#define DATA_SRAM0_NS_SAHB_START 0x20012200 #define DATA_SRAM0_NS_SAHB_START 0x20012200
#define DATA_SRAM0_NS_SAHB_SIZE 0x0000DE00 #define DATA_SRAM0_NS_SAHB_SIZE 0x0000DE00
#define BSS_SRAM0_NS_SAHB_START 0x20000000 #define BSS_SRAM0_NS_SAHB_START 0x20000000
#define BSS_SRAM0_NS_SAHB_SIZE 0x00000000 #define BSS_SRAM0_NS_SAHB_SIZE 0x00000000
#define DATA_XIP_NS_SAHB_START 0x60000000 #define DATA_XIP_NS_SAHB_START 0x60000000
#define DATA_XIP_NS_SAHB_SIZE 0x00000000 #define DATA_XIP_NS_SAHB_SIZE 0x00000000
#define BSS_XIP_NS_SAHB_START 0x60000000 #define BSS_XIP_NS_SAHB_START 0x60000000
#define BSS_XIP_NS_SAHB_SIZE 0x00000000 #define BSS_XIP_NS_SAHB_SIZE 0x00000000
/* /*
#define RAM_START 0x20004200 #define RAM_START 0x20004200
#define RAM_SIZE 0x0001BE00 #define RAM_SIZE 0x0001BE00
*/ */
#define RAM_START DATA_SRAM0_NS_SAHB_START #define RAM_START DATA_SRAM0_NS_SAHB_START
#define RAM_SIZE DATA_SRAM0_NS_SAHB_SIZE #define RAM_SIZE DATA_SRAM0_NS_SAHB_SIZE
; Flash ; Flash
/* /*
#define FLASH_START 0x60000000 #define FLASH_START 0x60000000
#define FLASH_SIZE 0x00010000 #define FLASH_SIZE 0x00010000
*/ */
#define FLASH_START CODE_SRAM0_NS_CBUS_START #define FLASH_START CODE_SRAM0_NS_CBUS_START
#define FLASH_SIZE CODE_SRAM0_NS_CBUS_SIZE #define FLASH_SIZE CODE_SRAM0_NS_CBUS_SIZE
; The size of the stack section at the end of CM33 SRAM ; The size of the stack section at the end of CM33 SRAM
#define STACK_SIZE 0x00001000 #define STACK_SIZE 0x00001000
; The size of the MCU boot header area at the start of FLASH ; The size of the MCU boot header area at the start of FLASH
#define BOOT_HEADER_SIZE 0x00000000 #define BOOT_HEADER_SIZE 0x00000000
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; External memory ; External memory
#define XIP_START CODE_XIP_NS_CBUS_START #define XIP_START CODE_XIP_NS_CBUS_START
#define XIP_SIZE CODE_XIP_NS_CBUS_SIZE #define XIP_SIZE CODE_XIP_NS_CBUS_SIZE
; Cortex-M33 application flash area ; Cortex-M33 application flash area
LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE) LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE)
{ {
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (.bss.noinit.RESET_RAM, +FIRST) * (.bss.noinit.RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 ALIGN 8 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) ARM_LIB_HEAP +0 ALIGN 8 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK (RAM_START+RAM_SIZE) ALIGN 32 EMPTY -STACK_SIZE ARM_LIB_STACK (RAM_START+RAM_SIZE) ALIGN 32 EMPTY -STACK_SIZE
{ {
} }
; Used for the digital signature of the secure application and the ; Used for the digital signature of the secure application and the
; Bootloader SDK application. The size of the section depends on the required ; Bootloader SDK application. The size of the section depends on the required
; data size. ; data size.
.cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
{ {
* (.cy_app_signature) * (.cy_app_signature)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
/* [] END OF FILE */ /* [] END OF FILE */

494
bsp/Infineon/libraries/templates/PSOC62/board/linker_scripts/link.icf
View File

@@ -1,247 +1,247 @@
/******************************************************************************* /*******************************************************************************
* \file cy8c6xxa_cm4_dual.icf * \file cy8c6xxa_cm4_dual.icf
* \version 2.91 * \version 2.91
* *
* Linker file for the IAR compiler. * Linker file for the IAR compiler.
* *
* The main purpose of the linker script is to describe how the sections in the * The main purpose of the linker script is to describe how the sections in the
* input files should be mapped into the output file, and to control the memory * input files should be mapped into the output file, and to control the memory
* layout of the output file. * layout of the output file.
* *
* \note The entry point is fixed and starts at 0x10000000. The valid application * \note The entry point is fixed and starts at 0x10000000. The valid application
* image should be placed there. * image should be placed there.
* *
* \note The linker files included with the PDL template projects must be generic * \note The linker files included with the PDL template projects must be generic
* and handle all common use cases. Your project may not use every section * and handle all common use cases. Your project may not use every section
* defined in the linker files. In that case you may see warnings during the * defined in the linker files. In that case you may see warnings during the
* build process. In your project, you can simply comment out or remove the * build process. In your project, you can simply comment out or remove the
* relevant code in the linker file. * relevant code in the linker file.
* *
******************************************************************************** ********************************************************************************
* \copyright * \copyright
* Copyright 2016-2021 Cypress Semiconductor Corporation * Copyright 2016-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Licensed under the Apache License, Version 2.0 (the "License"); * Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License. * you may not use this file except in compliance with the License.
* You may obtain a copy of the License at * You may obtain a copy of the License at
* *
* http://www.apache.org/licenses/LICENSE-2.0 * http://www.apache.org/licenses/LICENSE-2.0
* *
* Unless required by applicable law or agreed to in writing, software * Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, * distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and * See the License for the specific language governing permissions and
* limitations under the License. * limitations under the License.
*******************************************************************************/ *******************************************************************************/
/*###ICF### Section handled by ICF editor, don't touch! ****/ /*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/ /*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
/*-Specials-*/ /*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000; define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/* The symbols below define the location and size of blocks of memory in the target. /* The symbols below define the location and size of blocks of memory in the target.
* Use these symbols to specify the memory regions available for allocation. * Use these symbols to specify the memory regions available for allocation.
*/ */
/* The following symbols control RAM and flash memory allocation for the CM4 core. /* The following symbols control RAM and flash memory allocation for the CM4 core.
* You can change the memory allocation by editing RAM and Flash symbols. * You can change the memory allocation by editing RAM and Flash symbols.
* Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
* Using this memory region for other purposes will lead to unexpected behavior. * Using this memory region for other purposes will lead to unexpected behavior.
* Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf',
* where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'. * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'.
*/ */
/* RAM */ /* RAM */
define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000; define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000;
define symbol __ICFEDIT_region_IRAM1_end__ = 0x080FF7FF; define symbol __ICFEDIT_region_IRAM1_end__ = 0x080FF7FF;
/* Flash */ /* Flash */
define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
define symbol __ICFEDIT_region_IROM1_end__ = 0x101FFFFF; define symbol __ICFEDIT_region_IROM1_end__ = 0x101FFFFF;
/* The following symbols define a 32K flash region used for EEPROM emulation. /* The following symbols define a 32K flash region used for EEPROM emulation.
* This region can also be used as the general purpose flash. * This region can also be used as the general purpose flash.
* You can assign sections to this memory region for only one of the cores. * You can assign sections to this memory region for only one of the cores.
* Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
* Therefore, repurposing this memory region will prevent such middleware from operation. * Therefore, repurposing this memory region will prevent such middleware from operation.
*/ */
define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF;
/* The following symbols define device specific memory regions and must not be changed. */ /* The following symbols define device specific memory regions and must not be changed. */
/* Supervisory FLASH - User Data */ /* Supervisory FLASH - User Data */
define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF;
/* Supervisory FLASH - Normal Access Restrictions (NAR) */ /* Supervisory FLASH - Normal Access Restrictions (NAR) */
define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF;
/* Supervisory FLASH - Public Key */ /* Supervisory FLASH - Public Key */
define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF;
/* Supervisory FLASH - Table of Content # 2 */ /* Supervisory FLASH - Table of Content # 2 */
define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF;
/* Supervisory FLASH - Table of Content # 2 Copy */ /* Supervisory FLASH - Table of Content # 2 Copy */
define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF;
/* eFuse */ /* eFuse */
define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF;
/* XIP */ /* XIP */
define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF;
define symbol __ICFEDIT_region_EROM2_start__ = 0x0; define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
define symbol __ICFEDIT_region_EROM2_end__ = 0x0; define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM3_start__ = 0x0; define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
define symbol __ICFEDIT_region_EROM3_end__ = 0x0; define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
/*-Sizes-*/ /*-Sizes-*/
if (!isdefinedsymbol(__STACK_SIZE)) { if (!isdefinedsymbol(__STACK_SIZE)) {
define symbol __ICFEDIT_size_cstack__ = 0x1000; define symbol __ICFEDIT_size_cstack__ = 0x1000;
} else { } else {
define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
} }
define symbol __ICFEDIT_size_proc_stack__ = 0x0; define symbol __ICFEDIT_size_proc_stack__ = 0x0;
/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ /* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
if (!isdefinedsymbol(__HEAP_SIZE)) { if (!isdefinedsymbol(__HEAP_SIZE)) {
define symbol __ICFEDIT_size_heap__ = 0x0400; define symbol __ICFEDIT_size_heap__ = 0x0400;
} else { } else {
define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
} }
/**** End of ICF editor section. ###ICF###*/ /**** End of ICF editor section. ###ICF###*/
/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. /* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
* More about CM0+ prebuilt images, see here: * More about CM0+ prebuilt images, see here:
* https://github.com/cypresssemiconductorco/psoc6cm0p * https://github.com/cypresssemiconductorco/psoc6cm0p
*/ */
/* The size of the Cortex-M0+ application image */ /* The size of the Cortex-M0+ application image */
define symbol FLASH_CM0P_SIZE = 0x2000; define symbol FLASH_CM0P_SIZE = 0x2000;
define memory mem with size = 4G; define memory mem with size = 4G;
define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image }; define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image };
define block RO {first section .intvec, readonly}; define block RO {first section .intvec, readonly};
define block cy_xip { section .cy_xip }; define block cy_xip { section .cy_xip };
/*-Initializations-*/ /*-Initializations-*/
initialize by copy { readwrite }; initialize by copy { readwrite };
do not initialize { section .noinit, section .intvec_ram }; do not initialize { section .noinit, section .intvec_ram };
/*-Placement-*/ /*-Placement-*/
/* Flash - Cortex-M0+ application image */ /* Flash - Cortex-M0+ application image */
place at start of IROM1_region { block CM0P_RO }; place at start of IROM1_region { block CM0P_RO };
/* Flash - Cortex-M4 application */ /* Flash - Cortex-M4 application */
place in IROM1_region { block RO }; place in IROM1_region { block RO };
/* Used for the digital signature of the secure application and the Bootloader SDK application. */ /* Used for the digital signature of the secure application and the Bootloader SDK application. */
".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; ".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; ".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom };
/* Supervisory Flash - User Data */ /* Supervisory Flash - User Data */
".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; ".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data };
/* Supervisory Flash - NAR */ /* Supervisory Flash - NAR */
".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; ".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar };
/* Supervisory Flash - Public Key */ /* Supervisory Flash - Public Key */
".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; ".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key };
/* Supervisory Flash - TOC2 */ /* Supervisory Flash - TOC2 */
".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; ".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 };
/* Supervisory Flash - RTOC2 */ /* Supervisory Flash - RTOC2 */
".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; ".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 };
/* eFuse */ /* eFuse */
".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; ".cy_efuse" : place at start of IROM8_region { section .cy_efuse };
/* Execute in Place (XIP). See the smif driver documentation for details. */ /* Execute in Place (XIP). See the smif driver documentation for details. */
"cy_xip" : place at start of EROM1_region { block cy_xip }; "cy_xip" : place at start of EROM1_region { block cy_xip };
/* RAM */ /* RAM */
place at start of IRAM1_region { readwrite section .intvec_ram}; place at start of IRAM1_region { readwrite section .intvec_ram};
place in IRAM1_region { readwrite }; place in IRAM1_region { readwrite };
place at end of IRAM1_region { block HSTACK }; place at end of IRAM1_region { block HSTACK };
/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ /* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; ".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
keep { section .cy_m0p_image, keep { section .cy_m0p_image,
section .cy_app_signature, section .cy_app_signature,
section .cy_em_eeprom, section .cy_em_eeprom,
section .cy_sflash_user_data, section .cy_sflash_user_data,
section .cy_sflash_nar, section .cy_sflash_nar,
section .cy_sflash_public_key, section .cy_sflash_public_key,
section .cy_toc_part2, section .cy_toc_part2,
section .cy_rtoc_part2, section .cy_rtoc_part2,
section .cy_efuse, section .cy_efuse,
section .cy_xip, section .cy_xip,
section .cymeta, section .cymeta,
}; };
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
define exported symbol __cy_memory_0_start = 0x10000000; define exported symbol __cy_memory_0_start = 0x10000000;
define exported symbol __cy_memory_0_length = 0x00200000; define exported symbol __cy_memory_0_length = 0x00200000;
define exported symbol __cy_memory_0_row_size = 0x200; define exported symbol __cy_memory_0_row_size = 0x200;
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
define exported symbol __cy_memory_1_start = 0x14000000; define exported symbol __cy_memory_1_start = 0x14000000;
define exported symbol __cy_memory_1_length = 0x8000; define exported symbol __cy_memory_1_length = 0x8000;
define exported symbol __cy_memory_1_row_size = 0x200; define exported symbol __cy_memory_1_row_size = 0x200;
/* Supervisory Flash */ /* Supervisory Flash */
define exported symbol __cy_memory_2_start = 0x16000000; define exported symbol __cy_memory_2_start = 0x16000000;
define exported symbol __cy_memory_2_length = 0x8000; define exported symbol __cy_memory_2_length = 0x8000;
define exported symbol __cy_memory_2_row_size = 0x200; define exported symbol __cy_memory_2_row_size = 0x200;
/* XIP */ /* XIP */
define exported symbol __cy_memory_3_start = 0x18000000; define exported symbol __cy_memory_3_start = 0x18000000;
define exported symbol __cy_memory_3_length = 0x08000000; define exported symbol __cy_memory_3_length = 0x08000000;
define exported symbol __cy_memory_3_row_size = 0x200; define exported symbol __cy_memory_3_row_size = 0x200;
/* eFuse */ /* eFuse */
define exported symbol __cy_memory_4_start = 0x90700000; define exported symbol __cy_memory_4_start = 0x90700000;
define exported symbol __cy_memory_4_length = 0x100000; define exported symbol __cy_memory_4_length = 0x100000;
define exported symbol __cy_memory_4_row_size = 1; define exported symbol __cy_memory_4_row_size = 1;
/* EOF */ /* EOF */

554
bsp/Infineon/libraries/templates/PSOC62/board/linker_scripts/link.sct
View File

@@ -1,277 +1,277 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cy8c6xxa_cm4_dual.sct ;* \file cy8c6xxa_cm4_dual.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM4 core. ; The following defines control RAM and flash memory allocation for the CM4 core.
; You can change the memory allocation by editing RAM and Flash defines. ; You can change the memory allocation by editing RAM and Flash defines.
; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. ; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior. ; Using this memory region for other purposes will lead to unexpected behavior.
; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', ; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. ; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
; RAM ; RAM
#define RAM_START 0x08002000 #define RAM_START 0x08002000
#define RAM_SIZE 0x000FD800 #define RAM_SIZE 0x000FD800
; Flash ; Flash
#define FLASH_START 0x10000000 #define FLASH_START 0x10000000
#define FLASH_SIZE 0x00200000 #define FLASH_SIZE 0x00200000
; The size of the stack section at the end of CM4 SRAM ; The size of the stack section at the end of CM4 SRAM
#define STACK_SIZE 0x00001000 #define STACK_SIZE 0x00001000
; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. ; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
; More about CM0+ prebuilt images, see here: ; More about CM0+ prebuilt images, see here:
; https://github.com/cypresssemiconductorco/psoc6cm0p ; https://github.com/cypresssemiconductorco/psoc6cm0p
; The size of the Cortex-M0+ application flash image ; The size of the Cortex-M0+ application flash image
#define FLASH_CM0P_SIZE 0x2000 #define FLASH_CM0P_SIZE 0x2000
; The following defines describe a 32K flash region used for EEPROM emulation. ; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash. ; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores. ; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation. ; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000 #define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000 #define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data ; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800 #define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800 #define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00 #define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200 #define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key ; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00 #define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 #define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00 #define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200 #define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00 #define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200 #define SFLASH_RTOC_2_SIZE 0x00000200
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; eFuse ; eFuse
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Cortex-M0+ application flash image area ; Cortex-M0+ application flash image area
LR_IROM FLASH_START FLASH_CM0P_SIZE LR_IROM FLASH_START FLASH_CM0P_SIZE
{ {
.cy_m0p_image +0 FLASH_CM0P_SIZE .cy_m0p_image +0 FLASH_CM0P_SIZE
{ {
* (.cy_m0p_image) * (.cy_m0p_image)
} }
} }
; Cortex-M4 application flash area ; Cortex-M4 application flash area
LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
{ {
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
{ {
} }
; Used for the digital signature of the secure application and the ; Used for the digital signature of the secure application and the
; Bootloader SDK application. The size of the section depends on the required ; Bootloader SDK application. The size of the section depends on the required
; data size. ; data size.
.cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
{ {
* (.cy_app_signature) * (.cy_app_signature)
} }
} }
; Emulated EEPROM Flash area ; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{ {
.cy_em_eeprom +0 .cy_em_eeprom +0
{ {
* (.cy_em_eeprom) * (.cy_em_eeprom)
} }
} }
; Supervisory flash: User data ; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{ {
.cy_sflash_user_data +0 .cy_sflash_user_data +0
{ {
* (.cy_sflash_user_data) * (.cy_sflash_user_data)
} }
} }
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{ {
.cy_sflash_nar +0 .cy_sflash_nar +0
{ {
* (.cy_sflash_nar) * (.cy_sflash_nar)
} }
} }
; Supervisory flash: Public Key ; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{ {
.cy_sflash_public_key +0 .cy_sflash_public_key +0
{ {
* (.cy_sflash_public_key) * (.cy_sflash_public_key)
} }
} }
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{ {
.cy_toc_part2 +0 .cy_toc_part2 +0
{ {
* (.cy_toc_part2) * (.cy_toc_part2)
} }
} }
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{ {
.cy_rtoc_part2 +0 .cy_rtoc_part2 +0
{ {
* (.cy_rtoc_part2) * (.cy_rtoc_part2)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
; eFuse ; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE LR_EFUSE EFUSE_START EFUSE_SIZE
{ {
.cy_efuse +0 .cy_efuse +0
{ {
* (.cy_efuse) * (.cy_efuse)
} }
} }
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. ; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000 CYMETA 0x90500000
{ {
.cymeta +0 { * (.cymeta) } .cymeta +0 { * (.cymeta) }
} }
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
#define __cy_memory_0_start 0x10000000 #define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x00200000 #define __cy_memory_0_length 0x00200000
#define __cy_memory_0_row_size 0x200 #define __cy_memory_0_row_size 0x200
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
#define __cy_memory_1_start 0x14000000 #define __cy_memory_1_start 0x14000000
#define __cy_memory_1_length 0x8000 #define __cy_memory_1_length 0x8000
#define __cy_memory_1_row_size 0x200 #define __cy_memory_1_row_size 0x200
/* Supervisory Flash */ /* Supervisory Flash */
#define __cy_memory_2_start 0x16000000 #define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000 #define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200 #define __cy_memory_2_row_size 0x200
/* XIP */ /* XIP */
#define __cy_memory_3_start 0x18000000 #define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000 #define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200 #define __cy_memory_3_row_size 0x200
/* eFuse */ /* eFuse */
#define __cy_memory_4_start 0x90700000 #define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000 #define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1 #define __cy_memory_4_row_size 1
/* [] END OF FILE */ /* [] END OF FILE */

494
bsp/Infineon/psoc6-cy8ckit-062S2-43012/board/linker_scripts/link.icf
View File

@@ -1,247 +1,247 @@
/******************************************************************************* /*******************************************************************************
* \file cy8c6xxa_cm4_dual.icf * \file cy8c6xxa_cm4_dual.icf
* \version 2.91 * \version 2.91
* *
* Linker file for the IAR compiler. * Linker file for the IAR compiler.
* *
* The main purpose of the linker script is to describe how the sections in the * The main purpose of the linker script is to describe how the sections in the
* input files should be mapped into the output file, and to control the memory * input files should be mapped into the output file, and to control the memory
* layout of the output file. * layout of the output file.
* *
* \note The entry point is fixed and starts at 0x10000000. The valid application * \note The entry point is fixed and starts at 0x10000000. The valid application
* image should be placed there. * image should be placed there.
* *
* \note The linker files included with the PDL template projects must be generic * \note The linker files included with the PDL template projects must be generic
* and handle all common use cases. Your project may not use every section * and handle all common use cases. Your project may not use every section
* defined in the linker files. In that case you may see warnings during the * defined in the linker files. In that case you may see warnings during the
* build process. In your project, you can simply comment out or remove the * build process. In your project, you can simply comment out or remove the
* relevant code in the linker file. * relevant code in the linker file.
* *
******************************************************************************** ********************************************************************************
* \copyright * \copyright
* Copyright 2016-2021 Cypress Semiconductor Corporation * Copyright 2016-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Licensed under the Apache License, Version 2.0 (the "License"); * Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License. * you may not use this file except in compliance with the License.
* You may obtain a copy of the License at * You may obtain a copy of the License at
* *
* http://www.apache.org/licenses/LICENSE-2.0 * http://www.apache.org/licenses/LICENSE-2.0
* *
* Unless required by applicable law or agreed to in writing, software * Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, * distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and * See the License for the specific language governing permissions and
* limitations under the License. * limitations under the License.
*******************************************************************************/ *******************************************************************************/
/*###ICF### Section handled by ICF editor, don't touch! ****/ /*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/ /*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
/*-Specials-*/ /*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000; define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/* The symbols below define the location and size of blocks of memory in the target. /* The symbols below define the location and size of blocks of memory in the target.
* Use these symbols to specify the memory regions available for allocation. * Use these symbols to specify the memory regions available for allocation.
*/ */
/* The following symbols control RAM and flash memory allocation for the CM4 core. /* The following symbols control RAM and flash memory allocation for the CM4 core.
* You can change the memory allocation by editing RAM and Flash symbols. * You can change the memory allocation by editing RAM and Flash symbols.
* Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
* Using this memory region for other purposes will lead to unexpected behavior. * Using this memory region for other purposes will lead to unexpected behavior.
* Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf',
* where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'. * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'.
*/ */
/* RAM */ /* RAM */
define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000; define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000;
define symbol __ICFEDIT_region_IRAM1_end__ = 0x080FF7FF; define symbol __ICFEDIT_region_IRAM1_end__ = 0x080FF7FF;
/* Flash */ /* Flash */
define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
define symbol __ICFEDIT_region_IROM1_end__ = 0x101FFFFF; define symbol __ICFEDIT_region_IROM1_end__ = 0x101FFFFF;
/* The following symbols define a 32K flash region used for EEPROM emulation. /* The following symbols define a 32K flash region used for EEPROM emulation.
* This region can also be used as the general purpose flash. * This region can also be used as the general purpose flash.
* You can assign sections to this memory region for only one of the cores. * You can assign sections to this memory region for only one of the cores.
* Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
* Therefore, repurposing this memory region will prevent such middleware from operation. * Therefore, repurposing this memory region will prevent such middleware from operation.
*/ */
define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF;
/* The following symbols define device specific memory regions and must not be changed. */ /* The following symbols define device specific memory regions and must not be changed. */
/* Supervisory FLASH - User Data */ /* Supervisory FLASH - User Data */
define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF;
/* Supervisory FLASH - Normal Access Restrictions (NAR) */ /* Supervisory FLASH - Normal Access Restrictions (NAR) */
define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF;
/* Supervisory FLASH - Public Key */ /* Supervisory FLASH - Public Key */
define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF;
/* Supervisory FLASH - Table of Content # 2 */ /* Supervisory FLASH - Table of Content # 2 */
define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF;
/* Supervisory FLASH - Table of Content # 2 Copy */ /* Supervisory FLASH - Table of Content # 2 Copy */
define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF;
/* eFuse */ /* eFuse */
define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF;
/* XIP */ /* XIP */
define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF;
define symbol __ICFEDIT_region_EROM2_start__ = 0x0; define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
define symbol __ICFEDIT_region_EROM2_end__ = 0x0; define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM3_start__ = 0x0; define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
define symbol __ICFEDIT_region_EROM3_end__ = 0x0; define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
/*-Sizes-*/ /*-Sizes-*/
if (!isdefinedsymbol(__STACK_SIZE)) { if (!isdefinedsymbol(__STACK_SIZE)) {
define symbol __ICFEDIT_size_cstack__ = 0x1000; define symbol __ICFEDIT_size_cstack__ = 0x1000;
} else { } else {
define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
} }
define symbol __ICFEDIT_size_proc_stack__ = 0x0; define symbol __ICFEDIT_size_proc_stack__ = 0x0;
/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ /* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
if (!isdefinedsymbol(__HEAP_SIZE)) { if (!isdefinedsymbol(__HEAP_SIZE)) {
define symbol __ICFEDIT_size_heap__ = 0x0400; define symbol __ICFEDIT_size_heap__ = 0x0400;
} else { } else {
define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
} }
/**** End of ICF editor section. ###ICF###*/ /**** End of ICF editor section. ###ICF###*/
/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. /* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
* More about CM0+ prebuilt images, see here: * More about CM0+ prebuilt images, see here:
* https://github.com/cypresssemiconductorco/psoc6cm0p * https://github.com/cypresssemiconductorco/psoc6cm0p
*/ */
/* The size of the Cortex-M0+ application image */ /* The size of the Cortex-M0+ application image */
define symbol FLASH_CM0P_SIZE = 0x2000; define symbol FLASH_CM0P_SIZE = 0x2000;
define memory mem with size = 4G; define memory mem with size = 4G;
define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image }; define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image };
define block RO {first section .intvec, readonly}; define block RO {first section .intvec, readonly};
define block cy_xip { section .cy_xip }; define block cy_xip { section .cy_xip };
/*-Initializations-*/ /*-Initializations-*/
initialize by copy { readwrite }; initialize by copy { readwrite };
do not initialize { section .noinit, section .intvec_ram }; do not initialize { section .noinit, section .intvec_ram };
/*-Placement-*/ /*-Placement-*/
/* Flash - Cortex-M0+ application image */ /* Flash - Cortex-M0+ application image */
place at start of IROM1_region { block CM0P_RO }; place at start of IROM1_region { block CM0P_RO };
/* Flash - Cortex-M4 application */ /* Flash - Cortex-M4 application */
place in IROM1_region { block RO }; place in IROM1_region { block RO };
/* Used for the digital signature of the secure application and the Bootloader SDK application. */ /* Used for the digital signature of the secure application and the Bootloader SDK application. */
".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; ".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; ".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom };
/* Supervisory Flash - User Data */ /* Supervisory Flash - User Data */
".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; ".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data };
/* Supervisory Flash - NAR */ /* Supervisory Flash - NAR */
".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; ".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar };
/* Supervisory Flash - Public Key */ /* Supervisory Flash - Public Key */
".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; ".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key };
/* Supervisory Flash - TOC2 */ /* Supervisory Flash - TOC2 */
".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; ".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 };
/* Supervisory Flash - RTOC2 */ /* Supervisory Flash - RTOC2 */
".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; ".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 };
/* eFuse */ /* eFuse */
".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; ".cy_efuse" : place at start of IROM8_region { section .cy_efuse };
/* Execute in Place (XIP). See the smif driver documentation for details. */ /* Execute in Place (XIP). See the smif driver documentation for details. */
"cy_xip" : place at start of EROM1_region { block cy_xip }; "cy_xip" : place at start of EROM1_region { block cy_xip };
/* RAM */ /* RAM */
place at start of IRAM1_region { readwrite section .intvec_ram}; place at start of IRAM1_region { readwrite section .intvec_ram};
place in IRAM1_region { readwrite }; place in IRAM1_region { readwrite };
place at end of IRAM1_region { block HSTACK }; place at end of IRAM1_region { block HSTACK };
/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ /* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; ".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
keep { section .cy_m0p_image, keep { section .cy_m0p_image,
section .cy_app_signature, section .cy_app_signature,
section .cy_em_eeprom, section .cy_em_eeprom,
section .cy_sflash_user_data, section .cy_sflash_user_data,
section .cy_sflash_nar, section .cy_sflash_nar,
section .cy_sflash_public_key, section .cy_sflash_public_key,
section .cy_toc_part2, section .cy_toc_part2,
section .cy_rtoc_part2, section .cy_rtoc_part2,
section .cy_efuse, section .cy_efuse,
section .cy_xip, section .cy_xip,
section .cymeta, section .cymeta,
}; };
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
define exported symbol __cy_memory_0_start = 0x10000000; define exported symbol __cy_memory_0_start = 0x10000000;
define exported symbol __cy_memory_0_length = 0x00200000; define exported symbol __cy_memory_0_length = 0x00200000;
define exported symbol __cy_memory_0_row_size = 0x200; define exported symbol __cy_memory_0_row_size = 0x200;
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
define exported symbol __cy_memory_1_start = 0x14000000; define exported symbol __cy_memory_1_start = 0x14000000;
define exported symbol __cy_memory_1_length = 0x8000; define exported symbol __cy_memory_1_length = 0x8000;
define exported symbol __cy_memory_1_row_size = 0x200; define exported symbol __cy_memory_1_row_size = 0x200;
/* Supervisory Flash */ /* Supervisory Flash */
define exported symbol __cy_memory_2_start = 0x16000000; define exported symbol __cy_memory_2_start = 0x16000000;
define exported symbol __cy_memory_2_length = 0x8000; define exported symbol __cy_memory_2_length = 0x8000;
define exported symbol __cy_memory_2_row_size = 0x200; define exported symbol __cy_memory_2_row_size = 0x200;
/* XIP */ /* XIP */
define exported symbol __cy_memory_3_start = 0x18000000; define exported symbol __cy_memory_3_start = 0x18000000;
define exported symbol __cy_memory_3_length = 0x08000000; define exported symbol __cy_memory_3_length = 0x08000000;
define exported symbol __cy_memory_3_row_size = 0x200; define exported symbol __cy_memory_3_row_size = 0x200;
/* eFuse */ /* eFuse */
define exported symbol __cy_memory_4_start = 0x90700000; define exported symbol __cy_memory_4_start = 0x90700000;
define exported symbol __cy_memory_4_length = 0x100000; define exported symbol __cy_memory_4_length = 0x100000;
define exported symbol __cy_memory_4_row_size = 1; define exported symbol __cy_memory_4_row_size = 1;
/* EOF */ /* EOF */

554
bsp/Infineon/psoc6-cy8ckit-062S2-43012/board/linker_scripts/link.sct
View File

@@ -1,277 +1,277 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cy8c6xxa_cm4_dual.sct ;* \file cy8c6xxa_cm4_dual.sct
;* \version 2.91 ;* \version 2.91
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation ;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM4 core. ; The following defines control RAM and flash memory allocation for the CM4 core.
; You can change the memory allocation by editing RAM and Flash defines. ; You can change the memory allocation by editing RAM and Flash defines.
; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. ; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior. ; Using this memory region for other purposes will lead to unexpected behavior.
; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', ; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. ; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
; RAM ; RAM
#define RAM_START 0x08002000 #define RAM_START 0x08002000
#define RAM_SIZE 0x000FD800 #define RAM_SIZE 0x000FD800
; Flash ; Flash
#define FLASH_START 0x10000000 #define FLASH_START 0x10000000
#define FLASH_SIZE 0x00200000 #define FLASH_SIZE 0x00200000
; The size of the stack section at the end of CM4 SRAM ; The size of the stack section at the end of CM4 SRAM
#define STACK_SIZE 0x00001000 #define STACK_SIZE 0x00001000
; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. ; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
; More about CM0+ prebuilt images, see here: ; More about CM0+ prebuilt images, see here:
; https://github.com/cypresssemiconductorco/psoc6cm0p ; https://github.com/cypresssemiconductorco/psoc6cm0p
; The size of the Cortex-M0+ application flash image ; The size of the Cortex-M0+ application flash image
#define FLASH_CM0P_SIZE 0x2000 #define FLASH_CM0P_SIZE 0x2000
; The following defines describe a 32K flash region used for EEPROM emulation. ; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash. ; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores. ; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation. ; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000 #define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000 #define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data ; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800 #define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800 #define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00 #define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200 #define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key ; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00 #define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 #define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00 #define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200 #define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00 #define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200 #define SFLASH_RTOC_2_SIZE 0x00000200
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; eFuse ; eFuse
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Cortex-M0+ application flash image area ; Cortex-M0+ application flash image area
LR_IROM FLASH_START FLASH_CM0P_SIZE LR_IROM FLASH_START FLASH_CM0P_SIZE
{ {
.cy_m0p_image +0 FLASH_CM0P_SIZE .cy_m0p_image +0 FLASH_CM0P_SIZE
{ {
* (.cy_m0p_image) * (.cy_m0p_image)
} }
} }
; Cortex-M4 application flash area ; Cortex-M4 application flash area
LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
{ {
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
{ {
} }
; Used for the digital signature of the secure application and the ; Used for the digital signature of the secure application and the
; Bootloader SDK application. The size of the section depends on the required ; Bootloader SDK application. The size of the section depends on the required
; data size. ; data size.
.cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
{ {
* (.cy_app_signature) * (.cy_app_signature)
} }
} }
; Emulated EEPROM Flash area ; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{ {
.cy_em_eeprom +0 .cy_em_eeprom +0
{ {
* (.cy_em_eeprom) * (.cy_em_eeprom)
} }
} }
; Supervisory flash: User data ; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{ {
.cy_sflash_user_data +0 .cy_sflash_user_data +0
{ {
* (.cy_sflash_user_data) * (.cy_sflash_user_data)
} }
} }
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{ {
.cy_sflash_nar +0 .cy_sflash_nar +0
{ {
* (.cy_sflash_nar) * (.cy_sflash_nar)
} }
} }
; Supervisory flash: Public Key ; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{ {
.cy_sflash_public_key +0 .cy_sflash_public_key +0
{ {
* (.cy_sflash_public_key) * (.cy_sflash_public_key)
} }
} }
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{ {
.cy_toc_part2 +0 .cy_toc_part2 +0
{ {
* (.cy_toc_part2) * (.cy_toc_part2)
} }
} }
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{ {
.cy_rtoc_part2 +0 .cy_rtoc_part2 +0
{ {
* (.cy_rtoc_part2) * (.cy_rtoc_part2)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
cy_xip +0 cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
; eFuse ; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE LR_EFUSE EFUSE_START EFUSE_SIZE
{ {
.cy_efuse +0 .cy_efuse +0
{ {
* (.cy_efuse) * (.cy_efuse)
} }
} }
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. ; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000 CYMETA 0x90500000
{ {
.cymeta +0 { * (.cymeta) } .cymeta +0 { * (.cymeta) }
} }
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
#define __cy_memory_0_start 0x10000000 #define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x00200000 #define __cy_memory_0_length 0x00200000
#define __cy_memory_0_row_size 0x200 #define __cy_memory_0_row_size 0x200
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
#define __cy_memory_1_start 0x14000000 #define __cy_memory_1_start 0x14000000
#define __cy_memory_1_length 0x8000 #define __cy_memory_1_length 0x8000
#define __cy_memory_1_row_size 0x200 #define __cy_memory_1_row_size 0x200
/* Supervisory Flash */ /* Supervisory Flash */
#define __cy_memory_2_start 0x16000000 #define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000 #define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200 #define __cy_memory_2_row_size 0x200
/* XIP */ /* XIP */
#define __cy_memory_3_start 0x18000000 #define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000 #define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200 #define __cy_memory_3_row_size 0x200
/* eFuse */ /* eFuse */
#define __cy_memory_4_start 0x90700000 #define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000 #define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1 #define __cy_memory_4_row_size 1
/* [] END OF FILE */ /* [] END OF FILE */

548
bsp/Infineon/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/linker/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct
View File

@@ -1,274 +1,274 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 #! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
; The first line specifies a preprocessor command that the linker invokes ; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor. ; to pass a scatter file through a C preprocessor.
;******************************************************************************* ;*******************************************************************************
;* \file cy8c6xx7_cm4_dual.sct ;* \file cy8c6xx7_cm4_dual.sct
;* \version 2.60 ;* \version 2.60
;* ;*
;* Linker file for the ARMCC. ;* Linker file for the ARMCC.
;* ;*
;* The main purpose of the linker script is to describe how the sections in the ;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory ;* input files should be mapped into the output file, and to control the memory
;* layout of the output file. ;* layout of the output file.
;* ;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid ;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there. ;* application image should be placed there.
;* ;*
;* \note The linker files included with the PDL template projects must be ;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every ;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings ;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W ;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can ;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to ;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker ;* the linker, simply comment out or remove the relevant code in the linker
;* file. ;* file.
;* ;*
;******************************************************************************* ;*******************************************************************************
;* \copyright ;* \copyright
;* Copyright 2016-2019 Cypress Semiconductor Corporation ;* Copyright 2016-2019 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0 ;* SPDX-License-Identifier: Apache-2.0
;* ;*
;* Licensed under the Apache License, Version 2.0 (the "License"); ;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License. ;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at ;* You may obtain a copy of the License at
;* ;*
;* http://www.apache.org/licenses/LICENSE-2.0 ;* http://www.apache.org/licenses/LICENSE-2.0
;* ;*
;* Unless required by applicable law or agreed to in writing, software ;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS, ;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and ;* See the License for the specific language governing permissions and
;* limitations under the License. ;* limitations under the License.
;******************************************************************************/ ;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target. ; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation. ; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM4 core. ; The following defines control RAM and flash memory allocation for the CM4 core.
; You can change the memory allocation by editing RAM and Flash defines. ; You can change the memory allocation by editing RAM and Flash defines.
; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. ; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior. ; Using this memory region for other purposes will lead to unexpected behavior.
; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', ; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. ; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
; RAM ; RAM
#define RAM_START 0x08002000 #define RAM_START 0x08002000
#define RAM_SIZE 0x00045800 #define RAM_SIZE 0x00045800
; Flash ; Flash
#define FLASH_START 0x10000000 #define FLASH_START 0x10000000
#define FLASH_SIZE 0x00100000 #define FLASH_SIZE 0x00100000
; Size of the stack section at the end of CM4 SRAM ; Size of the stack section at the end of CM4 SRAM
#define STACK_SIZE 0x00001000 #define STACK_SIZE 0x00001000
; Size of the Cortex-M0+ application flash image ; Size of the Cortex-M0+ application flash image
#define FLASH_CM0P_SIZE 0x2000 #define FLASH_CM0P_SIZE 0x2000
; The following defines describe a 32K flash region used for EEPROM emulation. ; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash. ; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores. ; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation. ; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000 #define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000 #define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed. ; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data ; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800 #define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800 #define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00 #define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200 #define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key ; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00 #define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 #define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00 #define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200 #define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00 #define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200 #define SFLASH_RTOC_2_SIZE 0x00000200
; External memory ; External memory
#define XIP_START 0x18000000 #define XIP_START 0x18000000
#define XIP_SIZE 0x08000000 #define XIP_SIZE 0x08000000
; eFuse ; eFuse
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Cortex-M0+ application flash image area ; Cortex-M0+ application flash image area
LR_IROM FLASH_START FLASH_CM0P_SIZE LR_IROM FLASH_START FLASH_CM0P_SIZE
{ {
.cy_m0p_image +0 FLASH_CM0P_SIZE .cy_m0p_image +0 FLASH_CM0P_SIZE
{ {
* (.cy_m0p_image) * (.cy_m0p_image)
} }
} }
; Cortex-M4 application flash area ; Cortex-M4 application flash area
LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
{ {
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {
* (RESET, +FIRST) * (RESET, +FIRST)
} }
ER_FLASH_CODE +0 FIXED ER_FLASH_CODE +0 FIXED
{ {
* (InRoot$$Sections) * (InRoot$$Sections)
* (+RO) * (+RO)
} }
ER_RAM_VECTORS RAM_START UNINIT ER_RAM_VECTORS RAM_START UNINIT
{ {
* (RESET_RAM, +FIRST) * (RESET_RAM, +FIRST)
} }
RW_RAM_DATA +0 RW_RAM_DATA +0
{ {
* (.cy_ramfunc) * (.cy_ramfunc)
* (+RW, +ZI) * (+RW, +ZI)
} }
; Place variables in the section that should not be initialized during the ; Place variables in the section that should not be initialized during the
; device startup. ; device startup.
RW_IRAM1 +0 UNINIT RW_IRAM1 +0 UNINIT
{ {
* (.noinit) * (.noinit)
} }
; Application heap area (HEAP) ; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
{ {
} }
; Stack region growing down ; Stack region growing down
ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
{ {
} }
; Used for the digital signature of the secure application and the ; Used for the digital signature of the secure application and the
; Bootloader SDK application. The size of the section depends on the required ; Bootloader SDK application. The size of the section depends on the required
; data size. ; data size.
.cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
{ {
* (.cy_app_signature) * (.cy_app_signature)
} }
} }
; Emulated EEPROM Flash area ; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{ {
.cy_em_eeprom +0 .cy_em_eeprom +0
{ {
* (.cy_em_eeprom) * (.cy_em_eeprom)
} }
} }
; Supervisory flash: User data ; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{ {
.cy_sflash_user_data +0 .cy_sflash_user_data +0
{ {
* (.cy_sflash_user_data) * (.cy_sflash_user_data)
} }
} }
; Supervisory flash: Normal Access Restrictions (NAR) ; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{ {
.cy_sflash_nar +0 .cy_sflash_nar +0
{ {
* (.cy_sflash_nar) * (.cy_sflash_nar)
} }
} }
; Supervisory flash: Public Key ; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{ {
.cy_sflash_public_key +0 .cy_sflash_public_key +0
{ {
* (.cy_sflash_public_key) * (.cy_sflash_public_key)
} }
} }
; Supervisory flash: Table of Content # 2 ; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{ {
.cy_toc_part2 +0 .cy_toc_part2 +0
{ {
* (.cy_toc_part2) * (.cy_toc_part2)
} }
} }
; Supervisory flash: Table of Content # 2 Copy ; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{ {
.cy_rtoc_part2 +0 .cy_rtoc_part2 +0
{ {
* (.cy_rtoc_part2) * (.cy_rtoc_part2)
} }
} }
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. ; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE LR_EROM XIP_START XIP_SIZE
{ {
.cy_xip +0 .cy_xip +0
{ {
* (.cy_xip) * (.cy_xip)
} }
} }
; eFuse ; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE LR_EFUSE EFUSE_START EFUSE_SIZE
{ {
.cy_efuse +0 .cy_efuse +0
{ {
* (.cy_efuse) * (.cy_efuse)
} }
} }
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. ; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000 CYMETA 0x90500000
{ {
.cymeta +0 { * (.cymeta) } .cymeta +0 { * (.cymeta) }
} }
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
#define __cy_memory_0_start 0x10000000 #define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x00100000 #define __cy_memory_0_length 0x00100000
#define __cy_memory_0_row_size 0x200 #define __cy_memory_0_row_size 0x200
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
#define __cy_memory_1_start 0x14000000 #define __cy_memory_1_start 0x14000000
#define __cy_memory_1_length 0x8000 #define __cy_memory_1_length 0x8000
#define __cy_memory_1_row_size 0x200 #define __cy_memory_1_row_size 0x200
/* Supervisory Flash */ /* Supervisory Flash */
#define __cy_memory_2_start 0x16000000 #define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000 #define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200 #define __cy_memory_2_row_size 0x200
/* XIP */ /* XIP */
#define __cy_memory_3_start 0x18000000 #define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000 #define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200 #define __cy_memory_3_row_size 0x200
/* eFuse */ /* eFuse */
#define __cy_memory_4_start 0x90700000 #define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000 #define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1 #define __cy_memory_4_row_size 1
/* [] END OF FILE */ /* [] END OF FILE */

480
bsp/Infineon/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/linker/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf
View File

@@ -1,240 +1,240 @@
/***************************************************************************//** /***************************************************************************//**
* \file cy8c6xx7_cm4_dual.icf * \file cy8c6xx7_cm4_dual.icf
* \version 2.60 * \version 2.60
* *
* Linker file for the IAR compiler. * Linker file for the IAR compiler.
* *
* The main purpose of the linker script is to describe how the sections in the * The main purpose of the linker script is to describe how the sections in the
* input files should be mapped into the output file, and to control the memory * input files should be mapped into the output file, and to control the memory
* layout of the output file. * layout of the output file.
* *
* \note The entry point is fixed and starts at 0x10000000. The valid application * \note The entry point is fixed and starts at 0x10000000. The valid application
* image should be placed there. * image should be placed there.
* *
* \note The linker files included with the PDL template projects must be generic * \note The linker files included with the PDL template projects must be generic
* and handle all common use cases. Your project may not use every section * and handle all common use cases. Your project may not use every section
* defined in the linker files. In that case you may see warnings during the * defined in the linker files. In that case you may see warnings during the
* build process. In your project, you can simply comment out or remove the * build process. In your project, you can simply comment out or remove the
* relevant code in the linker file. * relevant code in the linker file.
* *
******************************************************************************** ********************************************************************************
* \copyright * \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation * Copyright 2016-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Licensed under the Apache License, Version 2.0 (the "License"); * Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License. * you may not use this file except in compliance with the License.
* You may obtain a copy of the License at * You may obtain a copy of the License at
* *
* http://www.apache.org/licenses/LICENSE-2.0 * http://www.apache.org/licenses/LICENSE-2.0
* *
* Unless required by applicable law or agreed to in writing, software * Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, * distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and * See the License for the specific language governing permissions and
* limitations under the License. * limitations under the License.
*******************************************************************************/ *******************************************************************************/
/*###ICF### Section handled by ICF editor, don't touch! ****/ /*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/ /*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
/*-Specials-*/ /*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000; define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/* The symbols below define the location and size of blocks of memory in the target. /* The symbols below define the location and size of blocks of memory in the target.
* Use these symbols to specify the memory regions available for allocation. * Use these symbols to specify the memory regions available for allocation.
*/ */
/* The following symbols control RAM and flash memory allocation for the CM4 core. /* The following symbols control RAM and flash memory allocation for the CM4 core.
* You can change the memory allocation by editing RAM and Flash symbols. * You can change the memory allocation by editing RAM and Flash symbols.
* Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
* Using this memory region for other purposes will lead to unexpected behavior. * Using this memory region for other purposes will lead to unexpected behavior.
* Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf',
* where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'. * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'.
*/ */
/* RAM */ /* RAM */
define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000; define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000;
define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800; define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800;
/* Flash */ /* Flash */
define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000; define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000;
/* The following symbols define a 32K flash region used for EEPROM emulation. /* The following symbols define a 32K flash region used for EEPROM emulation.
* This region can also be used as the general purpose flash. * This region can also be used as the general purpose flash.
* You can assign sections to this memory region for only one of the cores. * You can assign sections to this memory region for only one of the cores.
* Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
* Therefore, repurposing this memory region will prevent such middleware from operation. * Therefore, repurposing this memory region will prevent such middleware from operation.
*/ */
define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF;
/* The following symbols define device specific memory regions and must not be changed. */ /* The following symbols define device specific memory regions and must not be changed. */
/* Supervisory FLASH - User Data */ /* Supervisory FLASH - User Data */
define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF; define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF;
/* Supervisory FLASH - Normal Access Restrictions (NAR) */ /* Supervisory FLASH - Normal Access Restrictions (NAR) */
define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF;
/* Supervisory FLASH - Public Key */ /* Supervisory FLASH - Public Key */
define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF;
/* Supervisory FLASH - Table of Content # 2 */ /* Supervisory FLASH - Table of Content # 2 */
define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF;
/* Supervisory FLASH - Table of Content # 2 Copy */ /* Supervisory FLASH - Table of Content # 2 Copy */
define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF;
/* eFuse */ /* eFuse */
define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF;
/* XIP */ /* XIP */
define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF;
define symbol __ICFEDIT_region_EROM2_start__ = 0x0; define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
define symbol __ICFEDIT_region_EROM2_end__ = 0x0; define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM3_start__ = 0x0; define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
define symbol __ICFEDIT_region_EROM3_end__ = 0x0; define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
/*-Sizes-*/ /*-Sizes-*/
if (!isdefinedsymbol(__STACK_SIZE)) { if (!isdefinedsymbol(__STACK_SIZE)) {
define symbol __ICFEDIT_size_cstack__ = 0x1000; define symbol __ICFEDIT_size_cstack__ = 0x1000;
} else { } else {
define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
} }
define symbol __ICFEDIT_size_proc_stack__ = 0x0; define symbol __ICFEDIT_size_proc_stack__ = 0x0;
/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ /* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
if (!isdefinedsymbol(__HEAP_SIZE)) { if (!isdefinedsymbol(__HEAP_SIZE)) {
define symbol __ICFEDIT_size_heap__ = 0x0400; define symbol __ICFEDIT_size_heap__ = 0x0400;
} else { } else {
define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
} }
/**** End of ICF editor section. ###ICF###*/ /**** End of ICF editor section. ###ICF###*/
/* Size of the Cortex-M0+ application image */ /* Size of the Cortex-M0+ application image */
define symbol FLASH_CM0P_SIZE = 0x2000; define symbol FLASH_CM0P_SIZE = 0x2000;
define memory mem with size = 4G; define memory mem with size = 4G;
define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image }; define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image };
define block RO {first section .intvec, readonly}; define block RO {first section .intvec, readonly};
/*-Initializations-*/ /*-Initializations-*/
initialize by copy { readwrite }; initialize by copy { readwrite };
do not initialize { section .noinit, section .intvec_ram }; do not initialize { section .noinit, section .intvec_ram };
/*-Placement-*/ /*-Placement-*/
/* Flash - Cortex-M0+ application image */ /* Flash - Cortex-M0+ application image */
place at start of IROM1_region { block CM0P_RO }; place at start of IROM1_region { block CM0P_RO };
/* Flash - Cortex-M4 application */ /* Flash - Cortex-M4 application */
place in IROM1_region { block RO }; place in IROM1_region { block RO };
/* Used for the digital signature of the secure application and the Bootloader SDK application. */ /* Used for the digital signature of the secure application and the Bootloader SDK application. */
".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; ".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; ".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom };
/* Supervisory Flash - User Data */ /* Supervisory Flash - User Data */
".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; ".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data };
/* Supervisory Flash - NAR */ /* Supervisory Flash - NAR */
".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; ".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar };
/* Supervisory Flash - Public Key */ /* Supervisory Flash - Public Key */
".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; ".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key };
/* Supervisory Flash - TOC2 */ /* Supervisory Flash - TOC2 */
".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; ".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 };
/* Supervisory Flash - RTOC2 */ /* Supervisory Flash - RTOC2 */
".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; ".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 };
/* eFuse */ /* eFuse */
".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; ".cy_efuse" : place at start of IROM8_region { section .cy_efuse };
/* Execute in Place (XIP). See the smif driver documentation for details. */ /* Execute in Place (XIP). See the smif driver documentation for details. */
".cy_xip" : place at start of EROM1_region { section .cy_xip }; ".cy_xip" : place at start of EROM1_region { section .cy_xip };
/* RAM */ /* RAM */
place at start of IRAM1_region { readwrite section .intvec_ram}; place at start of IRAM1_region { readwrite section .intvec_ram};
place in IRAM1_region { readwrite }; place in IRAM1_region { readwrite };
place at end of IRAM1_region { block HSTACK }; place at end of IRAM1_region { block HSTACK };
/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ /* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; ".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
keep { section .cy_m0p_image, keep { section .cy_m0p_image,
section .cy_app_signature, section .cy_app_signature,
section .cy_em_eeprom, section .cy_em_eeprom,
section .cy_sflash_user_data, section .cy_sflash_user_data,
section .cy_sflash_nar, section .cy_sflash_nar,
section .cy_sflash_public_key, section .cy_sflash_public_key,
section .cy_toc_part2, section .cy_toc_part2,
section .cy_rtoc_part2, section .cy_rtoc_part2,
section .cy_efuse, section .cy_efuse,
section .cy_xip, section .cy_xip,
section .cymeta, section .cymeta,
}; };
/* The following symbols used by the cymcuelftool. */ /* The following symbols used by the cymcuelftool. */
/* Flash */ /* Flash */
define exported symbol __cy_memory_0_start = 0x10000000; define exported symbol __cy_memory_0_start = 0x10000000;
define exported symbol __cy_memory_0_length = 0x00100000; define exported symbol __cy_memory_0_length = 0x00100000;
define exported symbol __cy_memory_0_row_size = 0x200; define exported symbol __cy_memory_0_row_size = 0x200;
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
define exported symbol __cy_memory_1_start = 0x14000000; define exported symbol __cy_memory_1_start = 0x14000000;
define exported symbol __cy_memory_1_length = 0x8000; define exported symbol __cy_memory_1_length = 0x8000;
define exported symbol __cy_memory_1_row_size = 0x200; define exported symbol __cy_memory_1_row_size = 0x200;
/* Supervisory Flash */ /* Supervisory Flash */
define exported symbol __cy_memory_2_start = 0x16000000; define exported symbol __cy_memory_2_start = 0x16000000;
define exported symbol __cy_memory_2_length = 0x8000; define exported symbol __cy_memory_2_length = 0x8000;
define exported symbol __cy_memory_2_row_size = 0x200; define exported symbol __cy_memory_2_row_size = 0x200;
/* XIP */ /* XIP */
define exported symbol __cy_memory_3_start = 0x18000000; define exported symbol __cy_memory_3_start = 0x18000000;
define exported symbol __cy_memory_3_length = 0x08000000; define exported symbol __cy_memory_3_length = 0x08000000;
define exported symbol __cy_memory_3_row_size = 0x200; define exported symbol __cy_memory_3_row_size = 0x200;
/* eFuse */ /* eFuse */
define exported symbol __cy_memory_4_start = 0x90700000; define exported symbol __cy_memory_4_start = 0x90700000;
define exported symbol __cy_memory_4_length = 0x100000; define exported symbol __cy_memory_4_length = 0x100000;
define exported symbol __cy_memory_4_row_size = 1; define exported symbol __cy_memory_4_row_size = 1;
/* EOF */ /* EOF */

2
bsp/Vango/v85xx/Target_FLASH.icf
View File

@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text };
place in ROM_region { readonly }; place in ROM_region { readonly };
place in RAM_region { readwrite, place in RAM_region { readwrite,
block CSTACK, block HEAP }; block CSTACK, block HEAP };

68
bsp/acm32/acm32f0x0-nucleo/drivers/linker_scripts/link.icf
View File

@@ -1,34 +1,34 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/ /*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/ /*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/ /*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000; define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Memory Regions-*/ /*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0001FFFF; define symbol __ICFEDIT_region_ROM_end__ = 0x0001FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
/*-Sizes-*/ /*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x0800; define symbol __ICFEDIT_size_cstack__ = 0x0800;
define symbol __ICFEDIT_size_heap__ = 0x0000; define symbol __ICFEDIT_size_heap__ = 0x0000;
/**** End of ICF editor section. ###ICF###*/ /**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G; define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite }; initialize by copy { readwrite };
do not initialize { section .noinit }; do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly }; place in ROM_region { readonly };
place in RAM_region { readwrite, place in RAM_region { readwrite,
block CSTACK, block HEAP }; block CSTACK, block HEAP };
export symbol __ICFEDIT_region_RAM_start__; export symbol __ICFEDIT_region_RAM_start__;
export symbol __ICFEDIT_region_RAM_end__; export symbol __ICFEDIT_region_RAM_end__;

68
bsp/acm32/acm32f4xx-nucleo/drivers/linker_scripts/link.icf
View File

@@ -1,34 +1,34 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/ /*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/ /*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/ /*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000; define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Memory Regions-*/ /*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF; define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF;
/*-Sizes-*/ /*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x0800; define symbol __ICFEDIT_size_cstack__ = 0x0800;
define symbol __ICFEDIT_size_heap__ = 0x0000; define symbol __ICFEDIT_size_heap__ = 0x0000;
/**** End of ICF editor section. ###ICF###*/ /**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G; define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite }; initialize by copy { readwrite };
do not initialize { section .noinit }; do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly }; place in ROM_region { readonly };
place in RAM_region { readwrite, place in RAM_region { readwrite,
block CSTACK, block HEAP }; block CSTACK, block HEAP };
export symbol __ICFEDIT_region_RAM_start__; export symbol __ICFEDIT_region_RAM_start__;
export symbol __ICFEDIT_region_RAM_end__; export symbol __ICFEDIT_region_RAM_end__;

4
bsp/airm2m/air105/board/linker_scripts/link.lds
View File

@@ -90,7 +90,7 @@ SECTIONS
_edata = . ; _edata = . ;
} >RAM } >RAM
.stack : .stack :
{ {
. = ALIGN(4); . = ALIGN(4);
_sstack = .; _sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
. = ALIGN(4); . = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */ /* This is used by the startup in order to initialize the .bss secion */
_ebss = . ; _ebss = . ;
*(.bss.init) *(.bss.init)
} > RAM } > RAM
__bss_end = .; __bss_end = .;

2
bsp/airm2m/air32f103/board/linker_scripts/link.icf
View File

@@ -25,4 +25,4 @@ do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly }; place in ROM_region { readonly };
place in RAM_region { readwrite, last block CSTACK}; place in RAM_region { readwrite, last block CSTACK};

8
bsp/airm2m/air32f103/board/linker_scripts/link.lds
View File

@@ -52,7 +52,7 @@ SECTIONS
KEEP (*(.init_array)) KEEP (*(.init_array))
PROVIDE(__ctors_end__ = .); PROVIDE(__ctors_end__ = .);
. = ALIGN(4); . = ALIGN(4);
_etext = .; _etext = .;
} > ROM = 0 } > ROM = 0
@@ -84,13 +84,13 @@ SECTIONS
KEEP(*(SORT(.dtors.*))) KEEP(*(SORT(.dtors.*)))
KEEP(*(.dtors)) KEEP(*(.dtors))
PROVIDE(__dtors_end__ = .); PROVIDE(__dtors_end__ = .);
. = ALIGN(4); . = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */ /* This is used by the startup in order to initialize the .data secion */
_edata = . ; _edata = . ;
} >RAM } >RAM
.stack : .stack :
{ {
. = ALIGN(4); . = ALIGN(4);
_sstack = .; _sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
. = ALIGN(4); . = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */ /* This is used by the startup in order to initialize the .bss secion */
_ebss = . ; _ebss = . ;
*(.bss.init) *(.bss.init)
} > RAM } > RAM
__bss_end = .; __bss_end = .;

20
bsp/allwinner/d1/link.lds
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2020, RT-Thread Development Team * Copyright (c) 2006-2023, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
@@ -38,7 +38,7 @@ SECTIONS
. = ALIGN(8); . = ALIGN(8);
.text : .text :
{ {
*(.text) /* remaining code */ *(.text) /* remaining code */
*(.text.*) /* remaining code */ *(.text.*) /* remaining code */
@@ -47,7 +47,7 @@ SECTIONS
*(.glue_7) *(.glue_7)
*(.glue_7t) *(.glue_7t)
*(.gnu.linkonce.t*) *(.gnu.linkonce.t*)
/* section information for finsh shell */ /* section information for finsh shell */
. = ALIGN(8); . = ALIGN(8);
__fsymtab_start = .; __fsymtab_start = .;
@@ -74,20 +74,20 @@ SECTIONS
_etext = .; _etext = .;
} > SRAM } > SRAM
.eh_frame_hdr : .eh_frame_hdr :
{ {
*(.eh_frame_hdr) *(.eh_frame_hdr)
*(.eh_frame_entry) *(.eh_frame_entry)
} > SRAM } > SRAM
.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } > SRAM .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } > SRAM
. = ALIGN(8); . = ALIGN(8);
.data : .data :
{ {
*(.data) *(.data)
*(.data.*) *(.data.*)
*(.data1) *(.data1)
*(.data1.*) *(.data1.*)
@@ -97,7 +97,7 @@ SECTIONS
*(.sdata) *(.sdata)
*(.sdata.*) *(.sdata.*)
} > SRAM } > SRAM
. = ALIGN(8); . = ALIGN(8);
.ctors : .ctors :
{ {
@@ -139,7 +139,7 @@ SECTIONS
. = ALIGN(8); . = ALIGN(8);
.sbss : .sbss :
{ {
__bss_start = .; __bss_start = .;
*(.sbss) *(.sbss)

2
bsp/allwinner/d1/link_stacksize.lds
View File

@@ -1 +1 @@
__STACKSIZE__ = 16384; __STACKSIZE__ = 16384;

18
bsp/allwinner/d1s/link.lds
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2020, RT-Thread Development Team * Copyright (c) 2006-2023, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
@@ -38,7 +38,7 @@ SECTIONS
. = ALIGN(8); . = ALIGN(8);
.text : .text :
{ {
*(.text) /* remaining code */ *(.text) /* remaining code */
*(.text.*) /* remaining code */ *(.text.*) /* remaining code */
@@ -47,7 +47,7 @@ SECTIONS
*(.glue_7) *(.glue_7)
*(.glue_7t) *(.glue_7t)
*(.gnu.linkonce.t*) *(.gnu.linkonce.t*)
/* section information for finsh shell */ /* section information for finsh shell */
. = ALIGN(8); . = ALIGN(8);
__fsymtab_start = .; __fsymtab_start = .;
@@ -74,9 +74,9 @@ SECTIONS
_etext = .; _etext = .;
} > SRAM } > SRAM
.eh_frame_hdr : .eh_frame_hdr :
{ {
*(.eh_frame_hdr) *(.eh_frame_hdr)
*(.eh_frame_entry) *(.eh_frame_entry)
} > SRAM } > SRAM
.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } > SRAM .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } > SRAM
@@ -85,11 +85,11 @@ SECTIONS
__text_end = .; __text_end = .;
__text_size = __text_end - __text_start; __text_size = __text_end - __text_start;
.data : .data :
{ {
*(.data) *(.data)
*(.data.*) *(.data.*)
*(.data1) *(.data1)
*(.data1.*) *(.data1.*)
@@ -141,7 +141,7 @@ SECTIONS
. = ALIGN(8); . = ALIGN(8);
.sbss : .sbss :
{ {
__bss_start = .; __bss_start = .;
*(.sbss) *(.sbss)

2
bsp/allwinner/d1s/link_stacksize.lds
View File

@@ -1 +1 @@
__STACKSIZE__ = 16384; __STACKSIZE__ = 16384;

72
bsp/allwinner_tina/link.lds
View File

@@ -4,7 +4,7 @@ OUTPUT_ARCH(arm)
SECTIONS SECTIONS
{ {
. = 0x80000000; . = 0x80000000;
. = ALIGN(4); . = ALIGN(4);
__text_start = .; __text_start = .;
.text : .text :
@@ -12,7 +12,7 @@ SECTIONS
*(.vectors) *(.vectors)
*(.text) *(.text)
*(.text.*) *(.text.*)
KEEP(*(.fini)) KEEP(*(.fini))
/* section information for finsh shell */ /* section information for finsh shell */
. = ALIGN(4); . = ALIGN(4);
@@ -47,18 +47,18 @@ SECTIONS
.ctors : .ctors :
{ {
PROVIDE(__ctors_start__ = .); PROVIDE(__ctors_start__ = .);
*crtbegin.o(.ctors) *crtbegin.o(.ctors)
*crtbegin?.o(.ctors) *crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*)) *(SORT(.ctors.*))
*(.ctors) *(.ctors)
PROVIDE(__ctors_end__ = .); PROVIDE(__ctors_end__ = .);
} }
.ARM.extab : .ARM.extab :
{ {
*(.ARM.extab* .gnu.linkonce.armextab.*) *(.ARM.extab* .gnu.linkonce.armextab.*)
} }
/* The .ARM.exidx section is used for C++ exception handling. */ /* The .ARM.exidx section is used for C++ exception handling. */
/* .ARM.exidx is sorted, so has to go in its own output section. */ /* .ARM.exidx is sorted, so has to go in its own output section. */
__exidx_start = .; __exidx_start = .;
@@ -70,15 +70,15 @@ SECTIONS
_sidata = .; _sidata = .;
} }
__exidx_end = .; __exidx_end = .;
.dtors : .dtors :
{ {
PROVIDE(__dtors_start__ = .); PROVIDE(__dtors_start__ = .);
*crtbegin.o(.dtors) *crtbegin.o(.dtors)
*crtbegin?.o(.dtors) *crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*)) *(SORT(.dtors.*))
*(.dtors) *(.dtors)
PROVIDE(__dtors_end__ = .); PROVIDE(__dtors_end__ = .);
} }
@@ -89,30 +89,30 @@ SECTIONS
*(.data) *(.data)
*(.data.*) *(.data.*)
. = ALIGN(4); . = ALIGN(4);
/* preinit data */ /* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .); PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array)) KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .); PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4); . = ALIGN(4);
/* init data */ /* init data */
PROVIDE_HIDDEN (__init_array_start = .); PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*))) KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array)) KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .); PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4); . = ALIGN(4);
/* finit data */ /* finit data */
PROVIDE_HIDDEN (__fini_array_start = .); PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*))) KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array)) KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .); PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*)) KEEP(*(.jcr*))
. = ALIGN(4); . = ALIGN(4);
/* All data end */ /* All data end */
*(.gnu.linkonce.d*) *(.gnu.linkonce.d*)
} }

26
bsp/amebaz/bootloader_symbol.icf
View File

@@ -1,13 +1,13 @@
/* Bootloader symbol list */ /* Bootloader symbol list */
define exported symbol BOOT_FLASH_RDP_VALID = 0x08000123; define exported symbol BOOT_FLASH_RDP_VALID = 0x08000123;
define exported symbol BOOT_FLASH_SetStatusReg = 0x080003f5; define exported symbol BOOT_FLASH_SetStatusReg = 0x080003f5;
define exported symbol BOOT_FLASH_Image1 = 0x0800043b; define exported symbol BOOT_FLASH_Image1 = 0x0800043b;
define exported symbol IMAGE1$$Base = 0x10002001; define exported symbol IMAGE1$$Base = 0x10002001;
define exported symbol RamStartTable = 0x10002001; define exported symbol RamStartTable = 0x10002001;
define exported symbol RAM_IMG1_VALID_PATTEN = 0x10002019; define exported symbol RAM_IMG1_VALID_PATTEN = 0x10002019;
define exported symbol boot_export_symbol = 0x10002021; define exported symbol boot_export_symbol = 0x10002021;
define exported symbol BOOT_System_Init1 = 0x10002251; define exported symbol BOOT_System_Init1 = 0x10002251;
define exported symbol BOOT_System_Init2 = 0x10002263; define exported symbol BOOT_System_Init2 = 0x10002263;
define exported symbol BOOT_Swd_Off = 0x10002275; define exported symbol BOOT_Swd_Off = 0x10002275;
define exported symbol boot_ram_end = 0x10002455; define exported symbol boot_ram_end = 0x10002455;
define exported symbol IMAGE1$$Limit = 0x10002459; define exported symbol IMAGE1$$Limit = 0x10002459;

140
bsp/amebaz/image2.icf
View File

@@ -9,24 +9,24 @@ include "rom_symbol_v01_iar.icf";
/**************************************** /****************************************
* Memory Regions * * Memory Regions *
****************************************/ ****************************************/
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF;
define symbol __ICFEDIT_region_ROMBSS_RAM_start__ = 0x10000000; define symbol __ICFEDIT_region_ROMBSS_RAM_start__ = 0x10000000;
define symbol __ICFEDIT_region_ROMBSS_RAM_end__ = 0x10001FFF; define symbol __ICFEDIT_region_ROMBSS_RAM_end__ = 0x10001FFF;
define symbol __ICFEDIT_region_BOOTLOADER_RAM_start__ = 0x10002000; define symbol __ICFEDIT_region_BOOTLOADER_RAM_start__ = 0x10002000;
define symbol __ICFEDIT_region_BOOTLOADER_RAM_end__ = 0x10004FFF; define symbol __ICFEDIT_region_BOOTLOADER_RAM_end__ = 0x10004FFF;
define symbol __ICFEDIT_region_BD_RAM_start__ = 0x10005000; define symbol __ICFEDIT_region_BD_RAM_start__ = 0x10005000;
define symbol __ICFEDIT_region_BD_RAM_end__ = 0x1002FFFF; define symbol __ICFEDIT_region_BD_RAM_end__ = 0x1002FFFF;
define symbol __ICFEDIT_region_MSP_RAM_start__ = 0x1003E000; define symbol __ICFEDIT_region_MSP_RAM_start__ = 0x1003E000;
define symbol __ICFEDIT_region_MSP_RAM_end__ = 0x1003EFFF; define symbol __ICFEDIT_region_MSP_RAM_end__ = 0x1003EFFF;
define symbol __ICFEDIT_region_RDP_RAM_start__ = 0x1003F000; define symbol __ICFEDIT_region_RDP_RAM_start__ = 0x1003F000;
define symbol __ICFEDIT_region_RDP_RAM_end__ = 0x1003FFEF; define symbol __ICFEDIT_region_RDP_RAM_end__ = 0x1003FFEF;
define symbol __ICFEDIT_region_IMG2_TEMP_start__ = 0x10006000; define symbol __ICFEDIT_region_IMG2_TEMP_start__ = 0x10006000;
define symbol __ICFEDIT_region_IMG2_TEMP_end__ = 0x1000BFFF; define symbol __ICFEDIT_region_IMG2_TEMP_end__ = 0x1000BFFF;
define symbol __ICFEDIT_region_XIP_BOOT_start__ = 0x08000000+0x20; define symbol __ICFEDIT_region_XIP_BOOT_start__ = 0x08000000+0x20;
define symbol __ICFEDIT_region_XIP_BOOT_end__ = 0x08003FFF; define symbol __ICFEDIT_region_XIP_BOOT_end__ = 0x08003FFF;
define symbol __ICFEDIT_region_XIP_OTA1_start__ = 0x0800B000+0x20; define symbol __ICFEDIT_region_XIP_OTA1_start__ = 0x0800B000+0x20;
define symbol __ICFEDIT_region_XIP_OTA1_end__ = 0x080FFFFF; define symbol __ICFEDIT_region_XIP_OTA1_end__ = 0x080FFFFF;
/**************************************** /****************************************
* Sizes * * Sizes *
****************************************/ ****************************************/
@@ -68,16 +68,16 @@ keep { section .hal.rom.bss* };
keep { section .wlan_ram_map* }; keep { section .wlan_ram_map* };
keep { section .libc.ram.bss* }; keep { section .libc.ram.bss* };
keep { section .ssl_ram_map* }; keep { section .ssl_ram_map* };
define block .hal.rom.bss with fixed order{ section .ram_vector_table1, define block .hal.rom.bss with fixed order{ section .ram_vector_table1,
section .ram_vector_table2, section .ram_vector_table2,
section .ram_vector_table3, section .ram_vector_table3,
section .hal.rom.bss*, section .hal.rom.bss*,
section .wlan_ram_map*, section .wlan_ram_map*,
section .libc.ram.bss*, section .libc.ram.bss*,
section .ssl_ram_map*, section .ssl_ram_map*,
}; };
define block ROM_BSS with fixed order { block .hal.rom.bss}; define block ROM_BSS with fixed order { block .hal.rom.bss};
place at start of ROM_BSS_region { readwrite, place at start of ROM_BSS_region { readwrite,
block ROM_BSS, block ROM_BSS,
}; };
/**************************************** /****************************************
@@ -86,21 +86,21 @@ place at start of ROM_BSS_region { readwrite,
keep { section .image1.entry.data* }; keep { section .image1.entry.data* };
keep { section .image1.validate.rodata* }; keep { section .image1.validate.rodata* };
define block .ram_image1.entry with fixed order{section .image1.entry.data*, define block .ram_image1.entry with fixed order{section .image1.entry.data*,
section .image1.validate.rodata*, section .image1.validate.rodata*,
}; };
keep { section .boot.ram.text* }; keep { section .boot.ram.text* };
keep { section .boot.rodata* }; keep { section .boot.rodata* };
define block .ram_image1.text with fixed order{section .boot.ram.text*, define block .ram_image1.text with fixed order{section .boot.ram.text*,
section .boot.rodata*, section .boot.rodata*,
}; };
keep { section .boot.ram.data* }; keep { section .boot.ram.data* };
define block .ram_image1.data with fixed order{section .boot.ram.data*, define block .ram_image1.data with fixed order{section .boot.ram.data*,
}; };
keep { section .boot.ram.bss* }; keep { section .boot.ram.bss* };
define block .ram_image1.bss with fixed order{section .boot.ram.bss*, define block .ram_image1.bss with fixed order{section .boot.ram.bss*,
}; };
define block IMAGE1 with fixed order { block .ram_image1.entry, block .ram_image1.text, block .ram_image1.data, block .ram_image1.bss}; define block IMAGE1 with fixed order { block .ram_image1.entry, block .ram_image1.text, block .ram_image1.data, block .ram_image1.bss};
place at start of BOOT_RAM_region { readwrite, place at start of BOOT_RAM_region { readwrite,
block IMAGE1, block IMAGE1,
}; };
/**************************************** /****************************************
@@ -109,39 +109,39 @@ place at start of BOOT_RAM_region { readwrite,
keep { section .image2.entry.data* }; keep { section .image2.entry.data* };
keep { section .image2.validate.rodata* }; keep { section .image2.validate.rodata* };
define block .ram_image2.entry with fixed order{ section .image2.entry.data*, define block .ram_image2.entry with fixed order{ section .image2.entry.data*,
section .image2.validate.rodata*, section .image2.validate.rodata*,
}; };
define block SHT$$PREINIT_ARRAY { preinit_array }; define block SHT$$PREINIT_ARRAY { preinit_array };
define block SHT$$INIT_ARRAY { init_array }; define block SHT$$INIT_ARRAY { init_array };
define block CPP_INIT with fixed order { block SHT$$PREINIT_ARRAY, define block CPP_INIT with fixed order { block SHT$$PREINIT_ARRAY,
block SHT$$INIT_ARRAY }; block SHT$$INIT_ARRAY };
define block .ram.data with fixed order{ section .data*, define block .ram.data with fixed order{ section .data*,
section DATA, section DATA,
section .iar.init_table, section .iar.init_table,
section __DLIB_PERTHREAD, section __DLIB_PERTHREAD,
block CPP_INIT, block CPP_INIT,
section .mdns.data, section .mdns.data,
section .mdns.text section .mdns.text
}; };
define block .ram.text with fixed order{ section .image2.ram.text*, define block .ram.text with fixed order{ section .image2.ram.text*,
}; };
define block IMAGE2 with fixed order { block .ram_image2.entry, define block IMAGE2 with fixed order { block .ram_image2.entry,
block .ram.data, block .ram.data,
block .ram.text, block .ram.text,
}; };
define block .ram_image2.bss with fixed order{ section .bss*, define block .ram_image2.bss with fixed order{ section .bss*,
section COMMON, section COMMON,
}; };
define block .ram_image2.skb.bss with fixed order{ section .bdsram.data* }; define block .ram_image2.skb.bss with fixed order{ section .bdsram.data* };
define block .ram_heap.data with fixed order{ section .bfsram.data* }; define block .ram_heap.data with fixed order{ section .bfsram.data* };
place in BD_RAM_region { readwrite, place in BD_RAM_region { readwrite,
block IMAGE2, block IMAGE2,
block .ram_image2.bss, block .ram_image2.bss,
block .ram_image2.skb.bss, block .ram_image2.skb.bss,
block .ram_heap.data, block .ram_heap.data,
section .heap.stdlib, section .heap.stdlib,
last block HEAP, last block HEAP,
}; };
/**************************************** /****************************************
* XIP BOOT Section config * * XIP BOOT Section config *
****************************************/ ****************************************/
@@ -149,8 +149,8 @@ keep { section .flashboot.text* };
define block .xip_image1.text with fixed order{ section .flashboot.text* }; define block .xip_image1.text with fixed order{ section .flashboot.text* };
define block Bootloader with fixed order { section LOADER }; define block Bootloader with fixed order { section LOADER };
place at start of XIP_BOOT_region { block Bootloader, place at start of XIP_BOOT_region { block Bootloader,
readwrite, readwrite,
block .xip_image1.text }; block .xip_image1.text };
/**************************************** /****************************************
* XIP OTA1 Section config * * XIP OTA1 Section config *
****************************************/ ****************************************/
@@ -158,30 +158,30 @@ keep { section FSymTab };
keep { section VSymTab }; keep { section VSymTab };
keep { section .rti_fn* }; keep { section .rti_fn* };
define block .xip_image2.text with fixed order{ section .img2_custom_signature*, define block .xip_image2.text with fixed order{ section .img2_custom_signature*,
section .text*, section .text*,
section .rodata*, section .rodata*,
section .debug_trace, section .debug_trace,
section CODE, section CODE,
section Veneer, // object startup.o, section Veneer, // object startup.o,
section FSymTab, section FSymTab,
section VSymTab, section VSymTab,
section .rti_fn*, section .rti_fn*,
}; };
place at start of XIP_OTA1_region { readwrite, place at start of XIP_OTA1_region { readwrite,
block .xip_image2.text }; block .xip_image2.text };
/**************************************** /****************************************
* RDP Section config * * RDP Section config *
****************************************/ ****************************************/
keep { section .rdp.ram.text* }; keep { section .rdp.ram.text* };
keep { section .rdp.ram.data* }; keep { section .rdp.ram.data* };
define block .RDP_RAM with fixed order { define block .RDP_RAM with fixed order {
section .rdp.ram.text*, section .rdp.ram.text*,
section .rdp.ram.data* }; section .rdp.ram.data* };
place at start of RDP_RAM_region{ place at start of RDP_RAM_region{
readwrite, readwrite,
block .RDP_RAM }; block .RDP_RAM };
define exported symbol __ram_start_table_start__= 0x10002000; // use in rom define exported symbol __ram_start_table_start__= 0x10002000; // use in rom
define exported symbol __image1_validate_code__= 0x10002018; // needed by ram code define exported symbol __image1_validate_code__= 0x10002018; // needed by ram code
define exported symbol __rom_top_4k_start_= 0x1003F000; // needed by ram code define exported symbol __rom_top_4k_start_= 0x1003F000; // needed by ram code
define exported symbol __flash_text_start__= 0x0800b020; // needed by ram code define exported symbol __flash_text_start__= 0x0800b020; // needed by ram code
define exported symbol boot_export_symbol = 0x10002020; define exported symbol boot_export_symbol = 0x10002020;

2848
bsp/amebaz/rom_symbol_v01_iar.icf
View File

File diff suppressed because it is too large Load Diff

16
bsp/apm32/apm32f072vb-miniboard/board/linker_scripts/link.lds
View File

@@ -65,7 +65,7 @@ SECTIONS
/* This is used by the startup in order to initialize the .data secion */ /* This is used by the startup in order to initialize the .data secion */
_sidata = .; _sidata = .;
_start_address_init_data = .; _start_address_init_data = .;
} > ROM } > ROM
__exidx_end = .; __exidx_end = .;
@@ -76,7 +76,7 @@ SECTIONS
. = ALIGN(4); . = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */ /* This is used by the startup in order to initialize the .data secion */
_sdata = . ; _sdata = . ;
_start_address_data = .; _start_address_data = .;
*(.data) *(.data)
*(.data.*) *(.data.*)
@@ -91,21 +91,21 @@ SECTIONS
. = ALIGN(4); . = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */ /* This is used by the startup in order to initialize the .data secion */
_edata = . ; _edata = . ;
_end_address_data = .; _end_address_data = .;
} >RAM } >RAM
.stack : .stack :
{ {
. = ALIGN(4); . = ALIGN(4);
_sstack = .; _sstack = .;
. = . + _system_stack_size; . = . + _system_stack_size;
. = ALIGN(4); . = ALIGN(4);
_estack = .; _estack = .;
_end_stack = .; _end_stack = .;
} >RAM } >RAM
__bss_start = .; __bss_start = .;
_start_address_bss = .; _start_address_bss = .;
.bss : .bss :
{ {
. = ALIGN(4); . = ALIGN(4);
@@ -119,11 +119,11 @@ SECTIONS
. = ALIGN(4); . = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */ /* This is used by the startup in order to initialize the .bss secion */
_ebss = . ; _ebss = . ;
*(.bss.init) *(.bss.init)
} > RAM } > RAM
__bss_end = .; __bss_end = .;
_end_address_bss = .; _end_address_bss = .;
_end = .; _end = .;

4
bsp/apm32/apm32f103xe-minibroard/board/linker_scripts/link.lds
View File

@@ -80,7 +80,7 @@ SECTIONS
_end_address_data = .; _end_address_data = .;
} >DATA } >DATA
.stack : .stack :
{ {
. = . + _system_stack_size; . = . + _system_stack_size;
. = ALIGN(4); . = ALIGN(4);
@@ -102,7 +102,7 @@ SECTIONS
. = ALIGN(4); . = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */ /* This is used by the startup in order to initialize the .bss secion */
_ebss = . ; _ebss = . ;
*(.bss.init) *(.bss.init)
} > DATA } > DATA
__bss_end = .; __bss_end = .;

4
bsp/apm32/apm32f407ig-minibroard/board/linker_scripts/link.lds
View File

@@ -77,7 +77,7 @@ SECTIONS
_edata = . ; _edata = . ;
} >DATA } >DATA
.stack : .stack :
{ {
. = . + _system_stack_size; . = . + _system_stack_size;
. = ALIGN(4); . = ALIGN(4);
@@ -98,7 +98,7 @@ SECTIONS
. = ALIGN(4); . = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */ /* This is used by the startup in order to initialize the .bss secion */
_ebss = . ; _ebss = . ;
*(.bss.init) *(.bss.init)
} > DATA } > DATA
__bss_end = .; __bss_end = .;

2
bsp/at32/at32f403a-start/board/linker_scripts/link.icf
View File

@@ -25,4 +25,4 @@ do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly }; place in ROM_region { readonly };
place in RAM_region { readwrite, last block CSTACK}; place in RAM_region { readwrite, last block CSTACK};

8
bsp/at32/at32f403a-start/board/linker_scripts/link.lds
View File

@@ -52,7 +52,7 @@ SECTIONS
KEEP (*(.init_array)) KEEP (*(.init_array))
PROVIDE(__ctors_end__ = .); PROVIDE(__ctors_end__ = .);
. = ALIGN(4); . = ALIGN(4);
_etext = .; _etext = .;
} > ROM = 0 } > ROM = 0
@@ -84,13 +84,13 @@ SECTIONS
KEEP(*(SORT(.dtors.*))) KEEP(*(SORT(.dtors.*)))
KEEP(*(.dtors)) KEEP(*(.dtors))
PROVIDE(__dtors_end__ = .); PROVIDE(__dtors_end__ = .);
. = ALIGN(4); . = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */ /* This is used by the startup in order to initialize the .data secion */
_edata = . ; _edata = . ;
} >RAM } >RAM
.stack : .stack :
{ {
. = ALIGN(4); . = ALIGN(4);
_sstack = .; _sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
. = ALIGN(4); . = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */ /* This is used by the startup in order to initialize the .bss secion */
_ebss = . ; _ebss = . ;
*(.bss.init) *(.bss.init)
} > RAM } > RAM
__bss_end = .; __bss_end = .;

2
bsp/at32/at32f407-start/board/linker_scripts/link.icf
View File

@@ -25,4 +25,4 @@ do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly }; place in ROM_region { readonly };
place in RAM_region { readwrite, last block CSTACK}; place in RAM_region { readwrite, last block CSTACK};

8
bsp/at32/at32f407-start/board/linker_scripts/link.lds
View File

@@ -52,7 +52,7 @@ SECTIONS
KEEP (*(.init_array)) KEEP (*(.init_array))
PROVIDE(__ctors_end__ = .); PROVIDE(__ctors_end__ = .);
. = ALIGN(4); . = ALIGN(4);
_etext = .; _etext = .;
} > ROM = 0 } > ROM = 0
@@ -84,13 +84,13 @@ SECTIONS
KEEP(*(SORT(.dtors.*))) KEEP(*(SORT(.dtors.*)))
KEEP(*(.dtors)) KEEP(*(.dtors))
PROVIDE(__dtors_end__ = .); PROVIDE(__dtors_end__ = .);
. = ALIGN(4); . = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */ /* This is used by the startup in order to initialize the .data secion */
_edata = . ; _edata = . ;
} >RAM } >RAM
.stack : .stack :
{ {
. = ALIGN(4); . = ALIGN(4);
_sstack = .; _sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
. = ALIGN(4); . = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */ /* This is used by the startup in order to initialize the .bss secion */
_ebss = . ; _ebss = . ;
*(.bss.init) *(.bss.init)
} > RAM } > RAM
__bss_end = .; __bss_end = .;

2
bsp/at32/at32f413-start/board/linker_scripts/link.icf
View File

@@ -25,4 +25,4 @@ do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly }; place in ROM_region { readonly };
place in RAM_region { readwrite, last block CSTACK}; place in RAM_region { readwrite, last block CSTACK};

8
bsp/at32/at32f413-start/board/linker_scripts/link.lds
View File

@@ -52,7 +52,7 @@ SECTIONS
KEEP (*(.init_array)) KEEP (*(.init_array))
PROVIDE(__ctors_end__ = .); PROVIDE(__ctors_end__ = .);
. = ALIGN(4); . = ALIGN(4);
_etext = .; _etext = .;
} > ROM = 0 } > ROM = 0
@@ -84,13 +84,13 @@ SECTIONS
KEEP(*(SORT(.dtors.*))) KEEP(*(SORT(.dtors.*)))
KEEP(*(.dtors)) KEEP(*(.dtors))
PROVIDE(__dtors_end__ = .); PROVIDE(__dtors_end__ = .);
. = ALIGN(4); . = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */ /* This is used by the startup in order to initialize the .data secion */
_edata = . ; _edata = . ;
} >RAM } >RAM
.stack : .stack :
{ {
. = ALIGN(4); . = ALIGN(4);
_sstack = .; _sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
. = ALIGN(4); . = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */ /* This is used by the startup in order to initialize the .bss secion */
_ebss = . ; _ebss = . ;
*(.bss.init) *(.bss.init)
} > RAM } > RAM
__bss_end = .; __bss_end = .;

2
bsp/at32/at32f415-start/board/linker_scripts/link.icf
View File

@@ -25,4 +25,4 @@ do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly }; place in ROM_region { readonly };
place in RAM_region { readwrite, last block CSTACK}; place in RAM_region { readwrite, last block CSTACK};

8
bsp/at32/at32f415-start/board/linker_scripts/link.lds
View File

@@ -52,7 +52,7 @@ SECTIONS
KEEP (*(.init_array)) KEEP (*(.init_array))
PROVIDE(__ctors_end__ = .); PROVIDE(__ctors_end__ = .);
. = ALIGN(4); . = ALIGN(4);
_etext = .; _etext = .;
} > ROM = 0 } > ROM = 0
@@ -84,13 +84,13 @@ SECTIONS
KEEP(*(SORT(.dtors.*))) KEEP(*(SORT(.dtors.*)))
KEEP(*(.dtors)) KEEP(*(.dtors))
PROVIDE(__dtors_end__ = .); PROVIDE(__dtors_end__ = .);
. = ALIGN(4); . = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */ /* This is used by the startup in order to initialize the .data secion */
_edata = . ; _edata = . ;
} >RAM } >RAM
.stack : .stack :
{ {
. = ALIGN(4); . = ALIGN(4);
_sstack = .; _sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
. = ALIGN(4); . = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */ /* This is used by the startup in order to initialize the .bss secion */
_ebss = . ; _ebss = . ;
*(.bss.init) *(.bss.init)
} > RAM } > RAM
__bss_end = .; __bss_end = .;

2
bsp/at32/at32f435-start/board/linker_scripts/link.icf
View File

@@ -25,4 +25,4 @@ do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly }; place in ROM_region { readonly };
place in RAM_region { readwrite, last block CSTACK}; place in RAM_region { readwrite, last block CSTACK};

8
bsp/at32/at32f435-start/board/linker_scripts/link.lds
View File

@@ -52,7 +52,7 @@ SECTIONS
KEEP (*(.init_array)) KEEP (*(.init_array))
PROVIDE(__ctors_end__ = .); PROVIDE(__ctors_end__ = .);
. = ALIGN(4); . = ALIGN(4);
_etext = .; _etext = .;
} > ROM = 0 } > ROM = 0
@@ -84,13 +84,13 @@ SECTIONS
KEEP(*(SORT(.dtors.*))) KEEP(*(SORT(.dtors.*)))
KEEP(*(.dtors)) KEEP(*(.dtors))
PROVIDE(__dtors_end__ = .); PROVIDE(__dtors_end__ = .);
. = ALIGN(4); . = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */ /* This is used by the startup in order to initialize the .data secion */
_edata = . ; _edata = . ;
} >RAM } >RAM
.stack : .stack :
{ {
. = ALIGN(4); . = ALIGN(4);
_sstack = .; _sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
. = ALIGN(4); . = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */ /* This is used by the startup in order to initialize the .bss secion */
_ebss = . ; _ebss = . ;
*(.bss.init) *(.bss.init)
} > RAM } > RAM
__bss_end = .; __bss_end = .;

2
bsp/at32/at32f437-start/board/linker_scripts/link.icf
View File

@@ -25,4 +25,4 @@ do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly }; place in ROM_region { readonly };
place in RAM_region { readwrite, last block CSTACK}; place in RAM_region { readwrite, last block CSTACK};

8
bsp/at32/at32f437-start/board/linker_scripts/link.lds
View File

@@ -52,7 +52,7 @@ SECTIONS
KEEP (*(.init_array)) KEEP (*(.init_array))
PROVIDE(__ctors_end__ = .); PROVIDE(__ctors_end__ = .);
. = ALIGN(4); . = ALIGN(4);
_etext = .; _etext = .;
} > ROM = 0 } > ROM = 0
@@ -84,13 +84,13 @@ SECTIONS
KEEP(*(SORT(.dtors.*))) KEEP(*(SORT(.dtors.*)))
KEEP(*(.dtors)) KEEP(*(.dtors))
PROVIDE(__dtors_end__ = .); PROVIDE(__dtors_end__ = .);
. = ALIGN(4); . = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */ /* This is used by the startup in order to initialize the .data secion */
_edata = . ; _edata = . ;
} >RAM } >RAM
.stack : .stack :
{ {
. = ALIGN(4); . = ALIGN(4);
_sstack = .; _sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
. = ALIGN(4); . = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */ /* This is used by the startup in order to initialize the .bss secion */
_ebss = . ; _ebss = . ;
*(.bss.init) *(.bss.init)
} > RAM } > RAM
__bss_end = .; __bss_end = .;

2
bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F403AxC.icf
View File

@@ -27,4 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly }; place in ROM_region { readonly };
place in RAM_region { readwrite, place in RAM_region { readwrite,
block CSTACK, block HEAP }; block CSTACK, block HEAP };

2
bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F403AxE.icf
View File

@@ -27,4 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly }; place in ROM_region { readonly };
place in RAM_region { readwrite, place in RAM_region { readwrite,
block CSTACK, block HEAP }; block CSTACK, block HEAP };

2
bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F403AxG.icf
View File

@@ -27,4 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly }; place in ROM_region { readonly };
place in RAM_region { readwrite, place in RAM_region { readwrite,
block CSTACK, block HEAP }; block CSTACK, block HEAP };

2
bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F407xC.icf
View File

@@ -27,4 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly }; place in ROM_region { readonly };
place in RAM_region { readwrite, place in RAM_region { readwrite,
block CSTACK, block HEAP }; block CSTACK, block HEAP };

2
bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F407xE.icf
View File

@@ -27,4 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly }; place in ROM_region { readonly };
place in RAM_region { readwrite, place in RAM_region { readwrite,
block CSTACK, block HEAP }; block CSTACK, block HEAP };

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