mirror of
https://github.com/plctlab/riscv-operating-system-mooc.git
synced 2025-12-05 15:15:49 +00:00
fd1d098906
The purpose is to facilitate porting to RV64. Signed-off-by: Wang Chen <wangchen20@iscas.ac.cn>
107 lines
2.0 KiB
C
107 lines
2.0 KiB
C
#ifndef __RISCV_H__
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#define __RISCV_H__
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#include "types.h"
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/*
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* ref: https://github.com/mit-pdos/xv6-riscv/blob/riscv/kernel/riscv.h
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*/
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static inline reg_t r_tp()
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{
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reg_t x;
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asm volatile("mv %0, tp" : "=r" (x) );
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return x;
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}
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/* which hart (core) is this? */
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static inline reg_t r_mhartid()
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{
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reg_t x;
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asm volatile("csrr %0, mhartid" : "=r" (x) );
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return x;
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}
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/* Machine Status Register, mstatus */
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#define MSTATUS_MPP (3 << 11)
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#define MSTATUS_SPP (1 << 8)
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#define MSTATUS_MPIE (1 << 7)
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#define MSTATUS_SPIE (1 << 5)
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#define MSTATUS_UPIE (1 << 4)
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#define MSTATUS_MIE (1 << 3)
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#define MSTATUS_SIE (1 << 1)
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#define MSTATUS_UIE (1 << 0)
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static inline reg_t r_mstatus()
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{
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reg_t x;
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asm volatile("csrr %0, mstatus" : "=r" (x) );
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return x;
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}
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static inline void w_mstatus(reg_t x)
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{
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asm volatile("csrw mstatus, %0" : : "r" (x));
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}
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/*
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* machine exception program counter, holds the
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* instruction address to which a return from
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* exception will go.
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*/
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static inline void w_mepc(reg_t x)
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{
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asm volatile("csrw mepc, %0" : : "r" (x));
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}
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static inline reg_t r_mepc()
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{
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reg_t x;
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asm volatile("csrr %0, mepc" : "=r" (x));
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return x;
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}
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/* Machine Scratch register, for early trap handler */
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static inline void w_mscratch(reg_t x)
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{
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asm volatile("csrw mscratch, %0" : : "r" (x));
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}
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/* Machine-mode interrupt vector */
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static inline void w_mtvec(reg_t x)
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{
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asm volatile("csrw mtvec, %0" : : "r" (x));
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}
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/* Machine-mode Interrupt Enable */
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#define MIE_MEIE (1 << 11) // external
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#define MIE_MTIE (1 << 7) // timer
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#define MIE_MSIE (1 << 3) // software
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static inline reg_t r_mie()
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{
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reg_t x;
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asm volatile("csrr %0, mie" : "=r" (x) );
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return x;
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}
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static inline void w_mie(reg_t x)
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{
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asm volatile("csrw mie, %0" : : "r" (x));
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}
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/* Machine-mode Cause Masks */
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#define MCAUSE_MASK_INTERRUPT (reg_t)0x80000000
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#define MCAUSE_MASK_ECODE (reg_t)0x7FFFFFFF
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static inline reg_t r_mcause()
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{
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reg_t x;
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asm volatile("csrr %0, mcause" : "=r" (x) );
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return x;
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}
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#endif /* __RISCV_H__ */
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