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https://github.com/plctlab/riscv-operating-system-mooc.git
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ae10d3e698
- https://gitee.com/unicornx/riscv-operating-system-mooc/issues/I4QLTP - https://gitee.com/unicornx/riscv-operating-system-mooc/issues/I4PJTQ - https://gitee.com/unicornx/riscv-operating-system-mooc/issues/I49VW5 Signed-off-by: Wang Chen <wangchen20@iscas.ac.cn>
120 lines
3.4 KiB
C
120 lines
3.4 KiB
C
#include "os.h"
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/*
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* The UART control registers are memory-mapped at address UART0.
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* This macro returns the address of one of the registers.
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*/
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#define UART_REG(reg) ((volatile uint8_t *)(UART0 + reg))
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/*
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* Reference
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* [1]: TECHNICAL DATA ON 16550, http://byterunner.com/16550.html
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*/
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/*
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* UART control registers map. see [1] "PROGRAMMING TABLE"
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* note some are reused by multiple functions
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* 0 (write mode): THR/DLL
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* 1 (write mode): IER/DLM
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*/
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#define RHR 0 // Receive Holding Register (read mode)
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#define THR 0 // Transmit Holding Register (write mode)
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#define DLL 0 // LSB of Divisor Latch (write mode)
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#define IER 1 // Interrupt Enable Register (write mode)
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#define DLM 1 // MSB of Divisor Latch (write mode)
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#define FCR 2 // FIFO Control Register (write mode)
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#define ISR 2 // Interrupt Status Register (read mode)
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#define LCR 3 // Line Control Register
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#define MCR 4 // Modem Control Register
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#define LSR 5 // Line Status Register
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#define MSR 6 // Modem Status Register
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#define SPR 7 // ScratchPad Register
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/*
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* POWER UP DEFAULTS
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* IER = 0: TX/RX holding register interrupts are both disabled
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* ISR = 1: no interrupt penting
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* LCR = 0
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* MCR = 0
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* LSR = 60 HEX
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* MSR = BITS 0-3 = 0, BITS 4-7 = inputs
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* FCR = 0
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* TX = High
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* OP1 = High
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* OP2 = High
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* RTS = High
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* DTR = High
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* RXRDY = High
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* TXRDY = Low
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* INT = Low
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*/
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/*
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* LINE STATUS REGISTER (LSR)
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* LSR BIT 0:
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* 0 = no data in receive holding register or FIFO.
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* 1 = data has been receive and saved in the receive holding register or FIFO.
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* ......
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* LSR BIT 5:
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* 0 = transmit holding register is full. 16550 will not accept any data for transmission.
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* 1 = transmitter hold register (or FIFO) is empty. CPU can load the next character.
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* ......
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*/
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#define LSR_RX_READY (1 << 0)
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#define LSR_TX_IDLE (1 << 5)
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#define uart_read_reg(reg) (*(UART_REG(reg)))
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#define uart_write_reg(reg, v) (*(UART_REG(reg)) = (v))
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void uart_init()
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{
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/* disable interrupts. */
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uart_write_reg(IER, 0x00);
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/*
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* Setting baud rate. Just a demo here if we care about the divisor,
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* but for our purpose [QEMU-virt], this doesn't really do anything.
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*
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* Notice that the divisor register DLL (divisor latch least) and DLM (divisor
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* latch most) have the same base address as the receiver/transmitter and the
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* interrupt enable register. To change what the base address points to, we
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* open the "divisor latch" by writing 1 into the Divisor Latch Access Bit
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* (DLAB), which is bit index 7 of the Line Control Register (LCR).
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*
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* Regarding the baud rate value, see [1] "BAUD RATE GENERATOR PROGRAMMING TABLE".
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* We use 38.4K when 1.8432 MHZ crystal, so the corresponding value is 3.
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* And due to the divisor register is two bytes (16 bits), so we need to
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* split the value of 3(0x0003) into two bytes, DLL stores the low byte,
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* DLM stores the high byte.
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*/
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uint8_t lcr = uart_read_reg(LCR);
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uart_write_reg(LCR, lcr | (1 << 7));
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uart_write_reg(DLL, 0x03);
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uart_write_reg(DLM, 0x00);
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/*
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* Continue setting the asynchronous data communication format.
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* - number of the word length: 8 bits
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* - number of stop bits：1 bit when word length is 8 bits
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* - no parity
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* - no break control
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* - disabled baud latch
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*/
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lcr = 0;
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uart_write_reg(LCR, lcr | (3 << 0));
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}
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int uart_putc(char ch)
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{
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while ((uart_read_reg(LSR) & LSR_TX_IDLE) == 0);
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return uart_write_reg(THR, ch);
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}
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void uart_puts(char *s)
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{
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while (*s) {
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uart_putc(*s++);
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}
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}
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