mirror of
https://github.com/plctlab/riscv-operating-system-mooc.git
synced 2025-11-16 12:34:47 +00:00
fd1d098906
The purpose is to facilitate porting to RV64. Signed-off-by: Wang Chen <wangchen20@iscas.ac.cn>
155 lines
4.2 KiB
ArmAsm
155 lines
4.2 KiB
ArmAsm
#define LOAD lw
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#define STORE sw
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#define SIZE_REG 4
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# Save all General-Purpose(GP) registers to context.
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# struct context *base = &ctx_task;
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# base->ra = ra;
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# ......
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# These GP registers to be saved don't include gp
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# and tp, because they are not caller-saved or
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# callee-saved. These two registers are often used
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# for special purpose. For example, in RVOS, 'tp'
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# (aka "thread pointer") is used to store hartid,
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# which is a global value and would not be changed
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# during context-switch.
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.macro reg_save base
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STORE ra, 0*SIZE_REG(\base)
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STORE sp, 1*SIZE_REG(\base)
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STORE t0, 4*SIZE_REG(\base)
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STORE t1, 5*SIZE_REG(\base)
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STORE t2, 6*SIZE_REG(\base)
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STORE s0, 7*SIZE_REG(\base)
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STORE s1, 8*SIZE_REG(\base)
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STORE a0, 9*SIZE_REG(\base)
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STORE a1, 10*SIZE_REG(\base)
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STORE a2, 11*SIZE_REG(\base)
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STORE a3, 12*SIZE_REG(\base)
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STORE a4, 13*SIZE_REG(\base)
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STORE a5, 14*SIZE_REG(\base)
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STORE a6, 15*SIZE_REG(\base)
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STORE a7, 16*SIZE_REG(\base)
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STORE s2, 17*SIZE_REG(\base)
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STORE s3, 18*SIZE_REG(\base)
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STORE s4, 19*SIZE_REG(\base)
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STORE s5, 20*SIZE_REG(\base)
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STORE s6, 21*SIZE_REG(\base)
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STORE s7, 22*SIZE_REG(\base)
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STORE s8, 23*SIZE_REG(\base)
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STORE s9, 24*SIZE_REG(\base)
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STORE s10, 25*SIZE_REG(\base)
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STORE s11, 26*SIZE_REG(\base)
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STORE t3, 27*SIZE_REG(\base)
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STORE t4, 28*SIZE_REG(\base)
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STORE t5, 29*SIZE_REG(\base)
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# we don't save t6 here, due to we have used
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# it as base, we have to save t6 in an extra step
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# outside of reg_save
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.endm
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# restore all General-Purpose(GP) registers from the context
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# except gp & tp.
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# struct context *base = &ctx_task;
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# ra = base->ra;
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# ......
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.macro reg_restore base
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LOAD ra, 0*SIZE_REG(\base)
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LOAD sp, 1*SIZE_REG(\base)
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LOAD t0, 4*SIZE_REG(\base)
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LOAD t1, 5*SIZE_REG(\base)
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LOAD t2, 6*SIZE_REG(\base)
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LOAD s0, 7*SIZE_REG(\base)
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LOAD s1, 8*SIZE_REG(\base)
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LOAD a0, 9*SIZE_REG(\base)
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LOAD a1, 10*SIZE_REG(\base)
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LOAD a2, 11*SIZE_REG(\base)
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LOAD a3, 12*SIZE_REG(\base)
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LOAD a4, 13*SIZE_REG(\base)
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LOAD a5, 14*SIZE_REG(\base)
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LOAD a6, 15*SIZE_REG(\base)
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LOAD a7, 16*SIZE_REG(\base)
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LOAD s2, 17*SIZE_REG(\base)
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LOAD s3, 18*SIZE_REG(\base)
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LOAD s4, 19*SIZE_REG(\base)
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LOAD s5, 20*SIZE_REG(\base)
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LOAD s6, 21*SIZE_REG(\base)
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LOAD s7, 22*SIZE_REG(\base)
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LOAD s8, 23*SIZE_REG(\base)
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LOAD s9, 24*SIZE_REG(\base)
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LOAD s10, 25*SIZE_REG(\base)
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LOAD s11, 26*SIZE_REG(\base)
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LOAD t3, 27*SIZE_REG(\base)
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LOAD t4, 28*SIZE_REG(\base)
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LOAD t5, 29*SIZE_REG(\base)
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LOAD t6, 30*SIZE_REG(\base)
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.endm
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# Something to note about save/restore:
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# - We use mscratch to hold a pointer to context of current task
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# - We use t6 as the 'base' for reg_save/reg_restore, because it is the
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# very bottom register (x31) and would not be overwritten during loading.
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# Note: CSRs(mscratch) can not be used as 'base' due to load/restore
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# instruction only accept general purpose registers.
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.text
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# interrupts and exceptions while in machine mode come here.
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.globl trap_vector
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# the trap vector base address must always be aligned on a 4-byte boundary
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.balign 4
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trap_vector:
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# save context(registers).
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csrrw t6, mscratch, t6 # swap t6 and mscratch
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reg_save t6
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# Save the actual t6 register, which we swapped into
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# mscratch
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mv t5, t6 # t5 points to the context of current task
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csrr t6, mscratch # read t6 back from mscratch
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STORE t6, 30*SIZE_REG(t5) # save t6 with t5 as base
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# save mepc to context of current task
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csrr a0, mepc
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STORE a0, 31*SIZE_REG(t5)
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# Restore the context pointer into mscratch
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csrw mscratch, t5
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# call the C trap handler in trap.c
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csrr a0, mepc
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csrr a1, mcause
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call trap_handler
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# trap_handler will return the return address via a0.
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csrw mepc, a0
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# restore context(registers).
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csrr t6, mscratch
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reg_restore t6
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# return to whatever we were doing before trap.
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mret
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# void switch_to(struct context *next);
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# a0: pointer to the context of the next task
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.globl switch_to
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.balign 4
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switch_to:
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# switch mscratch to point to the context of the next task
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csrw mscratch, a0
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# set mepc to the pc of the next task
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LOAD a1, 31*SIZE_REG(a0)
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csrw mepc, a1
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# Restore all GP registers
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# Use t6 to point to the context of the new task
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mv t6, a0
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reg_restore t6
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# Do actual context switching.
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# Notice this will enable global interrupt
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mret
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.end
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