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67 lines
2.0 KiB
C
67 lines
2.0 KiB
C
#ifndef __PLATFORM_H__
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#define __PLATFORM_H__
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/*
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* QEMU RISC-V Virt machine with 16550a UART and VirtIO MMIO
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*/
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/*
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* maximum number of CPUs
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* see https://github.com/qemu/qemu/blob/master/include/hw/riscv/virt.h
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* #define VIRT_CPUS_MAX 8
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*/
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#define MAXNUM_CPU 8
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/* used in os.ld */
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#define LENGTH_RAM 128*1024*1024
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/*
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* MemoryMap
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* see https://github.com/qemu/qemu/blob/master/hw/riscv/virt.c, virt_memmap[]
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* 0x00001000 -- boot ROM, provided by qemu
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* 0x02000000 -- CLINT
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* 0x0C000000 -- PLIC
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* 0x10000000 -- UART0
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* 0x10001000 -- virtio disk
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* 0x80000000 -- boot ROM jumps here in machine mode, where we load our kernel
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*/
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/* This machine puts UART registers here in physical memory. */
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#define UART0 0x10000000L
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/*
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* UART0 interrupt source
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* see https://github.com/qemu/qemu/blob/master/include/hw/riscv/virt.h
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* enum {
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* UART0_IRQ = 10,
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* ......
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* };
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*/
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#define UART0_IRQ 10
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/*
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* This machine puts platform-level interrupt controller (PLIC) here.
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* Here only list PLIC registers in Machine mode.
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* see https://github.com/qemu/qemu/blob/master/include/hw/riscv/virt.h
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* #define VIRT_PLIC_HART_CONFIG "MS"
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* #define VIRT_PLIC_NUM_SOURCES 127
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* #define VIRT_PLIC_NUM_PRIORITIES 7
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* #define VIRT_PLIC_PRIORITY_BASE 0x00
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* #define VIRT_PLIC_PENDING_BASE 0x1000
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* #define VIRT_PLIC_ENABLE_BASE 0x2000
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* #define VIRT_PLIC_ENABLE_STRIDE 0x80
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* #define VIRT_PLIC_CONTEXT_BASE 0x200000
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* #define VIRT_PLIC_CONTEXT_STRIDE 0x1000
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* #define VIRT_PLIC_SIZE(__num_context) \
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* (VIRT_PLIC_CONTEXT_BASE + (__num_context) * VIRT_PLIC_CONTEXT_STRIDE)
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*/
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#define PLIC_BASE 0x0c000000L
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#define PLIC_PRIORITY(id) (PLIC_BASE + (id) * 4)
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#define PLIC_PENDING(id) (PLIC_BASE + 0x1000 + ((id) / 32) * 4)
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#define PLIC_MENABLE(hart, id) (PLIC_BASE + 0x2000 + (hart) * 0x80 + ((id) / 32) * 4)
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#define PLIC_MTHRESHOLD(hart) (PLIC_BASE + 0x200000 + (hart) * 0x1000)
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#define PLIC_MCLAIM(hart) (PLIC_BASE + 0x200004 + (hart) * 0x1000)
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#define PLIC_MCOMPLETE(hart) (PLIC_BASE + 0x200004 + (hart) * 0x1000)
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#endif /* __PLATFORM_H__ */
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