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4698c95063
Learn from https://github.com/LiuJiLan/RVOS_On_VisionFive2. Thanks. Signed-off-by: Wang Chen <wangchen20@iscas.ac.cn>
79 lines
2.4 KiB
C
79 lines
2.4 KiB
C
#include "os.h"
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void plic_init(void)
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{
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int hart = r_tp();
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/*
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* Set priority for UART0.
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*
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* Each PLIC interrupt source can be assigned a priority by writing
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* to its 32-bit memory-mapped priority register.
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* The QEMU-virt (the same as FU540-C000) supports 7 levels of priority.
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* A priority value of 0 is reserved to mean "never interrupt" and
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* effectively disables the interrupt.
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* Priority 1 is the lowest active priority, and priority 7 is the highest.
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* Ties between global interrupts of the same priority are broken by
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* the Interrupt ID; interrupts with the lowest ID have the highest
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* effective priority.
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*/
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*(uint32_t*)PLIC_PRIORITY(UART0_IRQ) = 1;
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/*
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* Enable UART0
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*
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* Each global interrupt can be enabled by setting the corresponding
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* bit in the enables registers.
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*/
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*(uint32_t*)PLIC_MENABLE(hart, UART0_IRQ)= (1 << (UART0_IRQ % 32));
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/*
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* Set priority threshold for UART0.
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*
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* PLIC will mask all interrupts of a priority less than or equal to threshold.
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* Maximum threshold is 7.
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* For example, a threshold value of zero permits all interrupts with
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* non-zero priority, whereas a value of 7 masks all interrupts.
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* Notice, the threshold is global for PLIC, not for each interrupt source.
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*/
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*(uint32_t*)PLIC_MTHRESHOLD(hart) = 0;
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/* enable machine-mode external interrupts. */
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w_mie(r_mie() | MIE_MEIE);
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}
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/*
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* DESCRIPTION:
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* Query the PLIC what interrupt we should serve.
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* Perform an interrupt claim by reading the claim register, which
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* returns the ID of the highest-priority pending interrupt or zero if there
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* is no pending interrupt.
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* A successful claim also atomically clears the corresponding pending bit
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* on the interrupt source.
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* RETURN VALUE:
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* the ID of the highest-priority pending interrupt or zero if there
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* is no pending interrupt.
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*/
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int plic_claim(void)
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{
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int hart = r_tp();
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int irq = *(uint32_t*)PLIC_MCLAIM(hart);
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return irq;
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}
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/*
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* DESCRIPTION:
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* Writing the interrupt ID it received from the claim (irq) to the
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* complete register would signal the PLIC we've served this IRQ.
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* The PLIC does not check whether the completion ID is the same as the
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* last claim ID for that target. If the completion ID does not match an
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* interrupt source that is currently enabled for the target, the completion
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* is silently ignored.
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* RETURN VALUE: none
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*/
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void plic_complete(int irq)
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{
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int hart = r_tp();
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*(uint32_t*)PLIC_MCOMPLETE(hart) = irq;
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}
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