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Encapsulate some types related to cpu word length.

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The purpose is to facilitate porting to RV64.

Signed-off-by: Wang Chen <wangchen20@iscas.ac.cn>
This commit is contained in:
Wang Chen
2024-03-27 14:11:18 +08:00
committed by Chen Wang
parent 1976f03d28
commit fd1d098906
63 changed files with 960 additions and 864 deletions
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130
code/os/06-interrupts/entry.S
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@@ -1,3 +1,7 @@
#define LOAD lw
#define STORE sw
#define SIZE_REG 4
# Save all General-Purpose(GP) registers to context.
# struct context *base = &ctx_task;
# base->ra = ra;
@@ -10,34 +14,34 @@
# which is a global value and would not be changed
# during context-switch.
.macro reg_save base
sw ra, 0(\base)
sw sp, 4(\base)
sw t0, 16(\base)
sw t1, 20(\base)
sw t2, 24(\base)
sw s0, 28(\base)
sw s1, 32(\base)
sw a0, 36(\base)
sw a1, 40(\base)
sw a2, 44(\base)
sw a3, 48(\base)
sw a4, 52(\base)
sw a5, 56(\base)
sw a6, 60(\base)
sw a7, 64(\base)
sw s2, 68(\base)
sw s3, 72(\base)
sw s4, 76(\base)
sw s5, 80(\base)
sw s6, 84(\base)
sw s7, 88(\base)
sw s8, 92(\base)
sw s9, 96(\base)
sw s10, 100(\base)
sw s11, 104(\base)
sw t3, 108(\base)
sw t4, 112(\base)
sw t5, 116(\base)
STORE ra, 0*SIZE_REG(\base)
STORE sp, 1*SIZE_REG(\base)
STORE t0, 4*SIZE_REG(\base)
STORE t1, 5*SIZE_REG(\base)
STORE t2, 6*SIZE_REG(\base)
STORE s0, 7*SIZE_REG(\base)
STORE s1, 8*SIZE_REG(\base)
STORE a0, 9*SIZE_REG(\base)
STORE a1, 10*SIZE_REG(\base)
STORE a2, 11*SIZE_REG(\base)
STORE a3, 12*SIZE_REG(\base)
STORE a4, 13*SIZE_REG(\base)
STORE a5, 14*SIZE_REG(\base)
STORE a6, 15*SIZE_REG(\base)
STORE a7, 16*SIZE_REG(\base)
STORE s2, 17*SIZE_REG(\base)
STORE s3, 18*SIZE_REG(\base)
STORE s4, 19*SIZE_REG(\base)
STORE s5, 20*SIZE_REG(\base)
STORE s6, 21*SIZE_REG(\base)
STORE s7, 22*SIZE_REG(\base)
STORE s8, 23*SIZE_REG(\base)
STORE s9, 24*SIZE_REG(\base)
STORE s10, 25*SIZE_REG(\base)
STORE s11, 26*SIZE_REG(\base)
STORE t3, 27*SIZE_REG(\base)
STORE t4, 28*SIZE_REG(\base)
STORE t5, 29*SIZE_REG(\base)
# we don't save t6 here, due to we have used
# it as base, we have to save t6 in an extra step
# outside of reg_save
@@ -49,35 +53,35 @@
# ra = base->ra;
# ......
.macro reg_restore base
lw ra, 0(\base)
lw sp, 4(\base)
lw t0, 16(\base)
lw t1, 20(\base)
lw t2, 24(\base)
lw s0, 28(\base)
lw s1, 32(\base)
lw a0, 36(\base)
lw a1, 40(\base)
lw a2, 44(\base)
lw a3, 48(\base)
lw a4, 52(\base)
lw a5, 56(\base)
lw a6, 60(\base)
lw a7, 64(\base)
lw s2, 68(\base)
lw s3, 72(\base)
lw s4, 76(\base)
lw s5, 80(\base)
lw s6, 84(\base)
lw s7, 88(\base)
lw s8, 92(\base)
lw s9, 96(\base)
lw s10, 100(\base)
lw s11, 104(\base)
lw t3, 108(\base)
lw t4, 112(\base)
lw t5, 116(\base)
lw t6, 120(\base)
LOAD ra, 0*SIZE_REG(\base)
LOAD sp, 1*SIZE_REG(\base)
LOAD t0, 4*SIZE_REG(\base)
LOAD t1, 5*SIZE_REG(\base)
LOAD t2, 6*SIZE_REG(\base)
LOAD s0, 7*SIZE_REG(\base)
LOAD s1, 8*SIZE_REG(\base)
LOAD a0, 9*SIZE_REG(\base)
LOAD a1, 10*SIZE_REG(\base)
LOAD a2, 11*SIZE_REG(\base)
LOAD a3, 12*SIZE_REG(\base)
LOAD a4, 13*SIZE_REG(\base)
LOAD a5, 14*SIZE_REG(\base)
LOAD a6, 15*SIZE_REG(\base)
LOAD a7, 16*SIZE_REG(\base)
LOAD s2, 17*SIZE_REG(\base)
LOAD s3, 18*SIZE_REG(\base)
LOAD s4, 19*SIZE_REG(\base)
LOAD s5, 20*SIZE_REG(\base)
LOAD s6, 21*SIZE_REG(\base)
LOAD s7, 22*SIZE_REG(\base)
LOAD s8, 23*SIZE_REG(\base)
LOAD s9, 24*SIZE_REG(\base)
LOAD s10, 25*SIZE_REG(\base)
LOAD s11, 26*SIZE_REG(\base)
LOAD t3, 27*SIZE_REG(\base)
LOAD t4, 28*SIZE_REG(\base)
LOAD t5, 29*SIZE_REG(\base)
LOAD t6, 30*SIZE_REG(\base)
.endm
# Something to note about save/restore:
@@ -100,9 +104,9 @@ trap_vector:
# Save the actual t6 register, which we swapped into
# mscratch
mv t5, t6 # t5 points to the context of current task
csrr t6, mscratch # read t6 back from mscratch
sw t6, 120(t5) # save t6 with t5 as base
mv t5, t6 # t5 points to the context of current task
csrr t6, mscratch # read t6 back from mscratch
STORE t6, 30*SIZE_REG(t5) # save t6 with t5 as base
# Restore the context pointer into mscratch
csrw mscratch, t5
@@ -137,9 +141,9 @@ switch_to:
# Save the actual t6 register, which we swapped into
# mscratch
mv t5, t6 # t5 points to the context of current task
csrr t6, mscratch # read t6 back from mscratch
sw t6, 120(t5) # save t6 with t5 as base
mv t5, t6 # t5 points to the context of current task
csrr t6, mscratch # read t6 back from mscratch
STORE t6, 30*SIZE_REG(t5) # save t6 with t5 as base
1:
# switch mscratch to point to the context of the next task