Imagelibrary/riscv-operating-system-mooc
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fixed some minor issues.

Browse Source 
- https://gitee.com/unicornx/riscv-operating-system-mooc/issues/I4QLTP
- https://gitee.com/unicornx/riscv-operating-system-mooc/issues/I4PJTQ
- https://gitee.com/unicornx/riscv-operating-system-mooc/issues/I49VW5

Signed-off-by: Wang Chen <wangchen20@iscas.ac.cn>
This commit is contained in:
Wang Chen
2022-01-27 11:06:33 +08:00
parent ca2629bebc
commit ae10d3e698
16 changed files with 194 additions and 194 deletions
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code/os/11-syscall/uart.c
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@@ -32,7 +32,7 @@
/*
* POWER UP DEFAULTS
* IER = 0: TX/RX holding register interrupts are bith disabled
* IER = 0: TX/RX holding register interrupts are both disabled
* ISR = 1: no interrupt penting
* LCR = 0
* MCR = 0