This commitment contains following changes:

- updated openday report
- fixed I41BDM
- I3ZLLK, code part & errata part fixing
- fixed I3XWKC, ppt & errata part
- fixed I418VG

code/os/11-syscall/platform.h

@@ -5,7 +5,7 @@
  * QEMU RISC-V Virt machine with 16550a UART and VirtIO MMIO
  */
 
-/* 
+/*
  * maximum number of CPUs
  * see https://github.com/qemu/qemu/blob/master/include/hw/riscv/virt.h
  * #define VIRT_CPUS_MAX 8
@@ -14,7 +14,7 @@
 
 /*
  * MemoryMap
- * see https://github.com/qemu/qemu/blob/master/hw/riscv/virt.c, virt_memmap[] 
+ * see https://github.com/qemu/qemu/blob/master/hw/riscv/virt.c, virt_memmap[]
  * 0x00001000 -- boot ROM, provided by qemu
  * 0x02000000 -- CLINT
  * 0x0C000000 -- PLIC
@@ -26,7 +26,7 @@
 /* This machine puts UART registers here in physical memory. */
 #define UART0 0x10000000L
 
-/* 
+/*
  * UART0 interrupt source
  * see https://github.com/qemu/qemu/blob/master/include/hw/riscv/virt.h
  * enum {
@@ -36,7 +36,7 @@
  */
 #define UART0_IRQ 10
 
-/* 
+/*
  * This machine puts platform-level interrupt controller (PLIC) here.
  * Here only list PLIC registers in Machine mode.
  * see https://github.com/qemu/qemu/blob/master/include/hw/riscv/virt.h
@@ -54,14 +54,14 @@
  */
 #define PLIC_BASE 0x0c000000L
 #define PLIC_PRIORITY(id) (PLIC_BASE + (id) * 4)
-#define PLIC_PENDING(id) (PLIC_BASE + 0x1000 + ((id) / 32))
+#define PLIC_PENDING(id) (PLIC_BASE + 0x1000 + ((id) / 32) * 4)
 #define PLIC_MENABLE(hart) (PLIC_BASE + 0x2000 + (hart) * 0x80)
 #define PLIC_MTHRESHOLD(hart) (PLIC_BASE + 0x200000 + (hart) * 0x1000)
 #define PLIC_MCLAIM(hart) (PLIC_BASE + 0x200004 + (hart) * 0x1000)
 #define PLIC_MCOMPLETE(hart) (PLIC_BASE + 0x200004 + (hart) * 0x1000)
 
- /* 
-  * The Core Local INTerruptor (CLINT) block holds memory-mapped control and 
+ /*
+  * The Core Local INTerruptor (CLINT) block holds memory-mapped control and
   * status registers associated with software and timer interrupts.
   * QEMU-virt reuses sifive configuration for CLINT.
   * see https://gitee.com/qemu/qemu/blob/master/include/hw/riscv/sifive_clint.h
@@ -70,17 +70,17 @@
   * 	SIFIVE_TIMECMP_BASE = 0x4000,
   * 	SIFIVE_TIME_BASE    = 0xBFF8
   * };
-  * 
+  *
   * enum {
   * 	SIFIVE_CLINT_TIMEBASE_FREQ = 10000000
   * };
-  * 
+  *
   * Notice:
-  * The machine-level MSIP bit of mip register are written by accesses to 
+  * The machine-level MSIP bit of mip register are written by accesses to
   * memory-mapped control registers, which are used by remote harts to provide
   * machine-mode interprocessor interrupts.
-  * For QEMU-virt machine, Each msip register is a 32-bit wide WARL register 
-  * where the upper 31 bits are tied to 0. The least significant bit is 
+  * For QEMU-virt machine, Each msip register is a 32-bit wide WARL register
+  * where the upper 31 bits are tied to 0. The least significant bit is
   * reflected in the MSIP bit of the mip CSR. We can write msip to generate
   * machine-mode software interrupts. A pending machine-level software
   * interrupt can be cleared by writing 0 to the MSIP bit in mip.

code/os/11-syscall/start.S

@@ -1,7 +1,7 @@
 #include "platform.h"
 
 	# size of each hart's stack is 1024 bytes
-	.equ	STACK_SIZE, MAXNUM_CPU * 1024
+	.equ	STACK_SIZE, 1024
 
 	.global	_start
 
@@ -26,7 +26,7 @@ _start:
 	# stack pointer to the very end of the stack range.
 	slli	t0, t0, 10		# shift left the hart id by 1024
 	la	sp, stacks + STACK_SIZE	# set the initial stack pointer
-					# to the end of the stack space
+					# to the end of the first stack space
 	add	sp, sp, t0		# move the current hart stack pointer
 					# to its place in the stack space
 
@@ -53,6 +53,6 @@ park:
 	j	park
 
 stacks:
-	.skip	STACK_SIZE		# allocate space for all the harts stacks
+	.skip	STACK_SIZE * MAXNUM_CPU # allocate space for all the harts stacks
 
 	.end				# End of file