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16 lines
372 B
ArmAsm
16 lines
372 B
ArmAsm
# This Code derived from xv6-riscv (64bit)
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# -- https://github.com/mit-pdos/xv6-riscv/blob/riscv/kernel/swtch.S
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.globl sys_timer
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.align 4
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sys_timer:
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# call the C timer_handler(reg_t epc, reg_t cause)
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csrr a0, mepc
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csrr a1, mcause
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call timer_handler
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# timer_handler will return the return address via a0.
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csrw mepc, a0
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mret # back to interrupt location (pc=mepc)
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