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https://github.com/cccriscv/mini-riscv-os.git
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164 lines
4.3 KiB
ArmAsm
164 lines
4.3 KiB
ArmAsm
# This Code derived from xv6-riscv (64bit)
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# -- https://github.com/mit-pdos/xv6-riscv/blob/riscv/kernel/swtch.S
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# ============ MACRO ==================
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.macro ctx_save base
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sw ra, 0(\base)
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sw sp, 4(\base)
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sw s0, 8(\base)
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sw s1, 12(\base)
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sw s2, 16(\base)
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sw s3, 20(\base)
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sw s4, 24(\base)
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sw s5, 28(\base)
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sw s6, 32(\base)
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sw s7, 36(\base)
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sw s8, 40(\base)
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sw s9, 44(\base)
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sw s10, 48(\base)
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sw s11, 52(\base)
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.endm
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.macro ctx_load base
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lw ra, 0(\base)
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lw sp, 4(\base)
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lw s0, 8(\base)
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lw s1, 12(\base)
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lw s2, 16(\base)
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lw s3, 20(\base)
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lw s4, 24(\base)
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lw s5, 28(\base)
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lw s6, 32(\base)
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lw s7, 36(\base)
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lw s8, 40(\base)
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lw s9, 44(\base)
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lw s10, 48(\base)
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lw s11, 52(\base)
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.endm
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.macro reg_save base
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# save the registers.
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sw ra, 0(\base)
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sw sp, 4(\base)
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sw gp, 8(\base)
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sw tp, 12(\base)
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sw t0, 16(\base)
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sw t1, 20(\base)
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sw t2, 24(\base)
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sw s0, 28(\base)
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sw s1, 32(\base)
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sw a0, 36(\base)
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sw a1, 40(\base)
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sw a2, 44(\base)
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sw a3, 48(\base)
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sw a4, 52(\base)
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sw a5, 56(\base)
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sw a6, 60(\base)
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sw a7, 64(\base)
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sw s2, 68(\base)
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sw s3, 72(\base)
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sw s4, 76(\base)
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sw s5, 80(\base)
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sw s6, 84(\base)
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sw s7, 88(\base)
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sw s8, 92(\base)
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sw s9, 96(\base)
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sw s10, 100(\base)
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sw s11, 104(\base)
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sw t3, 108(\base)
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sw t4, 112(\base)
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sw t5, 116(\base)
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sw t6, 120(\base)
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.endm
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.macro reg_load base
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# restore registers.
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lw ra, 0(\base)
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lw sp, 4(\base)
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lw gp, 8(\base)
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# not this, in case we moved CPUs: lw tp, 12(\base)
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lw t0, 16(\base)
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lw t1, 20(\base)
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lw t2, 24(\base)
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lw s0, 28(\base)
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lw s1, 32(\base)
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lw a0, 36(\base)
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lw a1, 40(\base)
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lw a2, 44(\base)
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lw a3, 48(\base)
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lw a4, 52(\base)
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lw a5, 56(\base)
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lw a6, 60(\base)
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lw a7, 64(\base)
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lw s2, 68(\base)
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lw s3, 72(\base)
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lw s4, 76(\base)
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lw s5, 80(\base)
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lw s6, 84(\base)
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lw s7, 88(\base)
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lw s8, 92(\base)
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lw s9, 96(\base)
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lw s10, 100(\base)
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lw s11, 104(\base)
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lw t3, 108(\base)
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lw t4, 112(\base)
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lw t5, 116(\base)
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lw t6, 120(\base)
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.endm
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# ============ Macro END ==================
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# Context switch
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#
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# void sys_switch(struct context *old, struct context *new);
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#
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# Save current registers in old. Load from new.
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.globl sys_switch
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.align 4
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sys_switch:
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ctx_save a0 # a0 => struct context *old
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ctx_load a1 # a1 => struct context *new
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ret # pc=ra; swtch to new task (new->ra)
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.globl sys_kernel
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.align 4
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sys_kernel:
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addi sp, sp, -128 # alloc stack space
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reg_save sp # save all registers
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call timer_handler # call timer.c:timer_handler
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reg_load sp # restore all registers
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addi sp, sp, 128 # restore stack pointer
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jr a7 # jump to a7=mepc , return to timer break point
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.globl sys_timer
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.align 4
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sys_timer:
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# timer_init() has set up the memory that mscratch points to:
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# scratch[0,4,8] : register save area.
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# scratch[12] : address of CLINT's MTIMECMP register.
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# scratch[16] : desired interval between interrupts.
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csrrw a0, mscratch, a0 # exchange(mscratch,a0)
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sw a1, 0(a0)
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sw a2, 4(a0)
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sw a3, 8(a0)
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# schedule the next timer interrupt
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# by adding interval to mtimecmp.
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lw a1, 12(a0) # CLINT_MTIMECMP(hart)
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lw a2, 16(a0) # interval
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lw a3, 0(a1) # a3 = CLINT_MTIMECMP(hart)
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add a3, a3, a2 # a3 += interval
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sw a3, 0(a1) # CLINT_MTIMECMP(hart) = a3
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csrr a7, mepc # a7 = mepc, for sys_kernel jump back to interrupted point
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la a1, sys_kernel # mepc = sys_kernel
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csrw mepc, a1 # mret : will jump to sys_kernel
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lw a3, 8(a0)
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lw a2, 4(a0)
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lw a1, 0(a0)
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csrrw a0, mscratch, a0 # exchange(mscratch,a0)
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mret # jump to mepc (=sys_kernel)
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