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https://github.com/cccriscv/mini-riscv-os.git
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117 lines
2.6 KiB
C
117 lines
2.6 KiB
C
#ifndef __RISCV_H__
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#define __RISCV_H__
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#include <stdint.h>
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#define reg_t uint32_t // RISCV32: register is 32bits
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// define reg_t as uint64_t // RISCV64: register is 64bits
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// ref: https://www.activexperts.com/serial-port-component/tutorials/uart/
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#define UART 0x10000000
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#define UART_THR (uint8_t*)(UART+0x00) // THR:transmitter holding register
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#define UART_LSR (uint8_t*)(UART+0x05) // LSR:line status register
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#define UART_LSR_EMPTY_MASK 0x40 // LSR Bit 6: Transmitter empty; both the THR and LSR are empty
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// Saved registers for kernel context switches.
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struct context {
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reg_t ra;
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reg_t sp;
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// callee-saved
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reg_t s0;
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reg_t s1;
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reg_t s2;
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reg_t s3;
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reg_t s4;
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reg_t s5;
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reg_t s6;
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reg_t s7;
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reg_t s8;
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reg_t s9;
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reg_t s10;
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reg_t s11;
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};
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// ref: https://github.com/mit-pdos/xv6-riscv/blob/riscv/kernel/riscv.h
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//
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// local interrupt controller, which contains the timer.
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// ================== Timer Interrput ====================
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#define NCPU 8 // maximum number of CPUs
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#define CLINT 0x2000000
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#define CLINT_MTIMECMP(hartid) (CLINT + 0x4000 + 4*(hartid))
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#define CLINT_MTIME (CLINT + 0xBFF8) // cycles since boot.
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// which hart (core) is this?
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static inline reg_t r_mhartid()
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{
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reg_t x;
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asm volatile("csrr %0, mhartid" : "=r" (x) );
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return x;
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}
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// Machine Status Register, mstatus
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#define MSTATUS_MPP_MASK (3 << 11) // previous mode.
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#define MSTATUS_MPP_M (3 << 11)
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#define MSTATUS_MPP_S (1 << 11)
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#define MSTATUS_MPP_U (0 << 11)
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#define MSTATUS_MIE (1 << 3) // machine-mode interrupt enable.
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static inline reg_t r_mstatus()
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{
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reg_t x;
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asm volatile("csrr %0, mstatus" : "=r" (x) );
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return x;
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}
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static inline void w_mstatus(reg_t x)
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{
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asm volatile("csrw mstatus, %0" : : "r" (x));
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}
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// machine exception program counter, holds the
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// instruction address to which a return from
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// exception will go.
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static inline void w_mepc(reg_t x)
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{
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asm volatile("csrw mepc, %0" : : "r" (x));
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}
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static inline reg_t r_mepc()
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{
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reg_t x;
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asm volatile("csrr %0, mepc" : "=r" (x));
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return x;
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}
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// Machine Scratch register, for early trap handler
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static inline void w_mscratch(reg_t x)
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{
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asm volatile("csrw mscratch, %0" : : "r" (x));
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}
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// Machine-mode interrupt vector
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static inline void w_mtvec(reg_t x)
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{
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asm volatile("csrw mtvec, %0" : : "r" (x));
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}
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// Machine-mode Interrupt Enable
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#define MIE_MEIE (1 << 11) // external
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#define MIE_MTIE (1 << 7) // timer
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#define MIE_MSIE (1 << 3) // software
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static inline reg_t r_mie()
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{
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reg_t x;
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asm volatile("csrr %0, mie" : "=r" (x) );
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return x;
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}
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static inline void w_mie(reg_t x)
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{
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asm volatile("csrw mie, %0" : : "r" (x));
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}
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#endif
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