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5ea1eec52f
The Linaro CI reported a regression [1] in test-case
gdb.base/step-over-syscall.exp due to commit 674d485673 ("[gdb/testsuite] Fix
gdb.base/step-over-syscall.exp with glibc 2.41").
Investigation shows that it's a progression in the sense that the test-case
fails at a later point than before.
The cause for the test-case failure is that an atomic sequence
ldaex/adds/strex is not skipped over when instruction stepping, leading to a
hang (in the sense of not being able to instruction-step out of the loop
containing the atomic sequence).
The arm target does have support for recognizing atomic sequences, but it
fails because it doesn't recognize the ldaex insn.
Fix this by:
- adding a new function ldaex_p which recognizes ldaex instructions, based
on information found in opcodes/arm-dis.c, and
- using ldaex_p in thumb_deal_with_atomic_sequence_raw.
I was not able to reproduce the failure in its original setting, but I
was able to do so using a test.c:
...
static void exit (int status) {
while (1)
;
}
void _start (void) {
int a = 0;
__atomic_fetch_add (&a, 1, __ATOMIC_ACQUIRE);
exit (0);
}
...
compiled like this:
...
$ gcc test.c -march=armv8-a -mfloat-abi=soft -nostdlib -static
...
giving this atomic sequence of 32-bit Thumb-2 instructions:
...
100ce: e8d3 1fef ldaex r1, [r3]
100d2: f101 0101 add.w r1, r1, #1
100d6: e843 1200 strex r2, r1, [r3]
...
Without the fix, after 100 stepi's we're still in _start (and likewise with
10.000 stepi's):
...
$ gdb -q -batch a.out -ex 'display /i $pc' -ex starti -ex "stepi 100"
...
0x000100dc in _start ()
1: x/i $pc
=> 0x100dc <_start+26>: bne.n 0x100ce <_start+12>
...
but with the fix we've managed to progress to exit:
...
$ gdb -q -batch a.out -ex 'display /i $pc' -ex starti -ex "stepi 100"
...
0x000100c0 in exit ()
1: x/i $pc
=> 0x100c0 <exit+8>: b.n 0x100c0 <exit+8>
...
Having addressed the "-mthumb" case, do we need a similar fix for "-marm"?
Adding "-marm" in the compilation line mentioned above gives the following
atomic sequence:
...
100e4: e1931e9f ldaex r1, [r3]
100e8: e2811001 add r1, r1, #1
100ec: e1832f91 strex r2, r1, [r3]
...
and gdb already recognizes it as such because of this statement:
...
if ((insn & 0xff9000f0) != 0xe1900090)
return {};
...
The trouble with this statement is that it requires knowledge of arm
instruction encoding to understand which cases it does and doesn't cover.
Note that the corresponding comment only mentions ldrex:
...
/* Assume all atomic sequences start with a ldrex{,b,h,d} instruction. ... */
...
but evidently at least some forms of ldaex are also detected.
So, also use ldaex_p in arm_deal_with_atomic_sequence_raw. This may or may
not be redundant, but at least ldaex_p is explicit and precise about what it
supports.
Likewise for stlex (generated when using __ATOMIC_RELEASE instead of
__ATOMIC_ACQUIRE in the example above).
Tested in arm-linux chroot on aarch64-linux.
Reviewed-By: Thiago Jung Bauermann <thiago.bauermann@linaro.org>
Co-Authored-By: Thiago Jung Bauermann <thiago.bauermann@linaro.org>
Approved-By: Luis Machado <luis.machado@arm.com>
PR tdep/32796
Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=32796
[1] https://linaro.atlassian.net/browse/GNU-1541
248 lines
8.0 KiB
C
248 lines
8.0 KiB
C
/* Common target dependent code for GDB on ARM systems.
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Copyright (C) 1988-2025 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef GDB_ARCH_ARM_H
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#define GDB_ARCH_ARM_H
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#include "gdbsupport/tdesc.h"
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/* Prologue helper macros for ARMv8.1-m PACBTI. */
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#define IS_PAC(instruction) (instruction == 0xf3af801d)
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#define IS_PACBTI(instruction) (instruction == 0xf3af800d)
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#define IS_BTI(instruction) (instruction == 0xf3af800f)
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#define IS_PACG(instruction) ((instruction & 0xfff0f0f0) == 0xfb60f000)
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#define IS_AUT(instruction) (instruction == 0xf3af802d)
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#define IS_AUTG(instruction) ((instruction & 0xfff00ff0) == 0xfb500f00)
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/* DWARF register numbers according to the AADWARF32 document. */
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enum arm_dwarf_regnum {
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ARM_DWARF_RA_AUTH_CODE = 143
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};
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/* Register numbers of various important registers. */
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enum gdb_regnum {
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ARM_A1_REGNUM = 0, /* first integer-like argument */
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ARM_A4_REGNUM = 3, /* last integer-like argument */
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ARM_AP_REGNUM = 11,
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ARM_IP_REGNUM = 12,
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ARM_SP_REGNUM = 13, /* Contains address of top of stack */
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ARM_LR_REGNUM = 14, /* address to return to from a function call */
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ARM_PC_REGNUM = 15, /* Contains program counter */
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/* F0..F7 are the fp registers for the (obsolete) FPA architecture. */
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ARM_F0_REGNUM = 16, /* first floating point register */
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ARM_F3_REGNUM = 19, /* last floating point argument register */
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ARM_F7_REGNUM = 23, /* last floating point register */
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ARM_FPS_REGNUM = 24, /* floating point status register */
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ARM_PS_REGNUM = 25, /* Contains processor status */
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ARM_WR0_REGNUM, /* WMMX data registers. */
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ARM_WR15_REGNUM = ARM_WR0_REGNUM + 15,
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ARM_WC0_REGNUM, /* WMMX control registers. */
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ARM_WCSSF_REGNUM = ARM_WC0_REGNUM + 2,
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ARM_WCASF_REGNUM = ARM_WC0_REGNUM + 3,
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ARM_WC7_REGNUM = ARM_WC0_REGNUM + 7,
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ARM_WCGR0_REGNUM, /* WMMX general purpose registers. */
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ARM_WCGR3_REGNUM = ARM_WCGR0_REGNUM + 3,
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ARM_WCGR7_REGNUM = ARM_WCGR0_REGNUM + 7,
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ARM_D0_REGNUM, /* VFP double-precision registers. */
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ARM_D31_REGNUM = ARM_D0_REGNUM + 31,
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ARM_FPSCR_REGNUM,
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/* Other useful registers. */
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ARM_FP_REGNUM = 11, /* Frame register in ARM code, if used. */
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THUMB_FP_REGNUM = 7, /* Frame register in Thumb code, if used. */
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ARM_LAST_ARG_REGNUM = ARM_A4_REGNUM,
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ARM_LAST_FP_ARG_REGNUM = ARM_F3_REGNUM
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};
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/* Register count constants. */
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enum arm_register_counts {
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/* Number of Q registers for MVE. */
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ARM_MVE_NUM_Q_REGS = 8,
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/* Number of argument registers. */
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ARM_NUM_ARG_REGS = 4,
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/* Number of floating point argument registers. */
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ARM_NUM_FP_ARG_REGS = 4,
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/* Number of registers (old, defined as ARM_FPSCR_REGNUM + 1. */
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ARM_NUM_REGS = ARM_FPSCR_REGNUM + 1
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};
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/* Enum describing the different kinds of breakpoints. */
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enum arm_breakpoint_kinds
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{
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ARM_BP_KIND_THUMB = 2,
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ARM_BP_KIND_THUMB2 = 3,
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ARM_BP_KIND_ARM = 4,
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};
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/* Supported Arm FP hardware types. */
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enum arm_fp_type {
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ARM_FP_TYPE_NONE = 0,
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ARM_FP_TYPE_VFPV2,
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ARM_FP_TYPE_VFPV3,
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ARM_FP_TYPE_IWMMXT,
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ARM_FP_TYPE_INVALID
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};
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/* Supported M-profile Arm types. */
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enum arm_m_profile_type {
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ARM_M_TYPE_M_PROFILE,
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ARM_M_TYPE_VFP_D16,
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ARM_M_TYPE_WITH_FPA,
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ARM_M_TYPE_MVE,
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ARM_M_TYPE_SYSTEM,
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ARM_M_TYPE_INVALID
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};
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/* System control registers accessible through an addresses. */
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enum system_register_address : CORE_ADDR
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{
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/* M-profile Floating-Point Context Control Register address, defined in
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ARMv7-M (Section B3.2.2) and ARMv8-M (Section D1.2.99) reference
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manuals. */
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FPCCR = 0xe000ef34,
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/* M-profile Floating-Point Context Address Register address, defined in
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ARMv7-M (Section B3.2.2) and ARMv8-M (Section D1.2.98) reference
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manuals. */
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FPCAR = 0xe000ef38
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};
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/* Instruction condition field values. */
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#define INST_EQ 0x0
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#define INST_NE 0x1
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#define INST_CS 0x2
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#define INST_CC 0x3
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#define INST_MI 0x4
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#define INST_PL 0x5
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#define INST_VS 0x6
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#define INST_VC 0x7
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#define INST_HI 0x8
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#define INST_LS 0x9
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#define INST_GE 0xa
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#define INST_LT 0xb
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#define INST_GT 0xc
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#define INST_LE 0xd
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#define INST_AL 0xe
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#define INST_NV 0xf
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#define FLAG_N 0x80000000
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#define FLAG_Z 0x40000000
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#define FLAG_C 0x20000000
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#define FLAG_V 0x10000000
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#define CPSR_T 0x20
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#define XPSR_T 0x01000000
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/* Size of registers. */
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#define ARM_INT_REGISTER_SIZE 4
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/* IEEE extended doubles are 80 bits. DWORD aligned they use 96 bits. */
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#define ARM_FP_REGISTER_SIZE 12
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#define ARM_VFP_REGISTER_SIZE 8
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#define IWMMXT_VEC_REGISTER_SIZE 8
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/* Size of register sets. */
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/* r0-r12,sp,lr,pc,cpsr. */
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#define ARM_CORE_REGS_SIZE (17 * ARM_INT_REGISTER_SIZE)
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/* f0-f8,fps. */
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#define ARM_FP_REGS_SIZE (8 * ARM_FP_REGISTER_SIZE + ARM_INT_REGISTER_SIZE)
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/* d0-d15,fpscr. */
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#define ARM_VFP2_REGS_SIZE (16 * ARM_VFP_REGISTER_SIZE + ARM_INT_REGISTER_SIZE)
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/* d0-d31,fpscr. */
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#define ARM_VFP3_REGS_SIZE (32 * ARM_VFP_REGISTER_SIZE + ARM_INT_REGISTER_SIZE)
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/* wR0-wR15,fpscr. */
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#define IWMMXT_REGS_SIZE (16 * IWMMXT_VEC_REGISTER_SIZE \
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+ 6 * ARM_INT_REGISTER_SIZE)
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/* Addresses for calling Thumb functions have the bit 0 set.
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Here are some macros to test, set, or clear bit 0 of addresses. */
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#define IS_THUMB_ADDR(addr) ((addr) & 1)
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#define MAKE_THUMB_ADDR(addr) ((addr) | 1)
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#define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
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/* Support routines for instruction parsing. */
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#define submask(x) ((1L << ((x) + 1)) - 1)
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#define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
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#define bit(obj,st) (((obj) >> (st)) & 1)
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#define sbits(obj,st,fn) \
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((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
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#define BranchDest(addr,instr) \
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((CORE_ADDR) (((unsigned long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
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/* Forward declaration. */
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struct reg_buffer_common;
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/* Return the size in bytes of the complete Thumb instruction whose
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first halfword is INST1. */
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int thumb_insn_size (unsigned short inst1);
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/* Returns true if COND always evaluates to true. */
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static inline bool
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condition_always_true (unsigned long cond)
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{
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return cond == INST_AL || cond == INST_NV;
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}
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/* Returns true if cond of INSN always evaluates to true. */
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static inline bool
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insn_condition_always_true (uint32_t insn)
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{
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unsigned long cond = bits (insn, 28, 31);
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return condition_always_true (cond);
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}
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/* Returns true if the condition evaluates to true. */
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int condition_true (unsigned long cond, unsigned long status_reg);
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/* Return 1 if THIS_INSTR might change control flow, 0 otherwise. */
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int arm_instruction_changes_pc (uint32_t this_instr);
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/* Return 1 if the 16-bit Thumb instruction INST might change
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control flow, 0 otherwise. */
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int thumb_instruction_changes_pc (unsigned short inst);
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/* Return 1 if the 32-bit Thumb instruction in INST1 and INST2
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might change control flow, 0 otherwise. */
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int thumb2_instruction_changes_pc (unsigned short inst1, unsigned short inst2);
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/* Advance the state of the IT block and return that state. */
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int thumb_advance_itstate (unsigned int itstate);
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/* Decode shifted register value. */
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unsigned long shifted_reg_val (reg_buffer_common *regcache,
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unsigned long inst,
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int carry,
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unsigned long pc_val,
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unsigned long status_reg);
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/* Create an Arm target description with the given FP hardware type. */
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target_desc *arm_create_target_description (arm_fp_type fp_type, bool tls);
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/* Create an Arm M-profile target description with the given hardware type. */
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target_desc *arm_create_mprofile_target_description (arm_m_profile_type m_type);
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#endif /* GDB_ARCH_ARM_H */
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