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582e12bf76
This patch supports some additions to the SVE architecture prior to
its public release.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4x16)
(AARCH64_OPND_SVE_IMM_ROT1, AARCH64_OPND_SVE_IMM_ROT2)
(AARCH64_OPND_SVE_Zm3_INDEX, AARCH64_OPND_SVE_Zm3_22_INDEX)
(AARCH64_OPND_SVE_Zm4_INDEX): New aarch64_opnds.
opcodes/
* aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
(OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
(OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
(OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
(OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
(OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
(OP_SVE_V_HSD): New macros.
(OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
(OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
(OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
(aarch64_opcode_table): Add new SVE instructions.
(aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
for rotation operands. Add new SVE operands.
* aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
(ins_sve_quad_index): Likewise.
(ins_imm_rotate): Split into...
(ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
* aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
(aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
functions.
(aarch64_ins_sve_addr_ri_s4): New function.
(aarch64_ins_sve_quad_index): Likewise.
(do_misc_encoding): Handle "MOV Zn.Q, Qm".
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
(ext_sve_quad_index): Likewise.
(ext_imm_rotate): Split into...
(ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
* aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
(aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
functions.
(aarch64_ext_sve_addr_ri_s4): New function.
(aarch64_ext_sve_quad_index): Likewise.
(aarch64_ext_sve_index): Allow quad indices.
(do_misc_decoding): Likewise.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
aarch64_field_kinds.
(OPD_F_OD_MASK): Widen by one bit.
(OPD_F_NO_ZR): Bump accordingly.
(get_operand_field_width): New function.
* aarch64-opc.c (fields): Add new SVE fields.
(operand_general_constraint_met_p): Handle new SVE operands.
(aarch64_print_operand): Likewise.
* aarch64-opc-2.c: Regenerate.
gas/
* doc/c-aarch64.texi: Document that sve implies fp16, simd and compnum.
* config/tc-aarch64.c (parse_vector_type_for_operand): Allow .q
to be used with SVE registers.
(parse_operands): Handle new SVE operands.
(aarch64_features): Make "sve" require F16 rather than FP. Also
require COMPNUM.
* testsuite/gas/aarch64/sve.s: Add tests for new instructions.
Include compnum tests.
* testsuite/gas/aarch64/sve.d: Update accordingly.
* testsuite/gas/aarch64/sve-invalid.s: Add tests for new instructions.
* testsuite/gas/aarch64/sve-invalid.l: Update accordingly. Also
update expected output for new FMOV and MOV alternatives.
103 lines
4.0 KiB
C
103 lines
4.0 KiB
C
/* aarch64-asm.h -- Header file for aarch64-asm.c and aarch64-asm-2.c.
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Copyright (C) 2012-2017 Free Software Foundation, Inc.
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Contributed by ARM Ltd.
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; see the file COPYING3. If not,
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see <http://www.gnu.org/licenses/>. */
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#ifndef OPCODES_AARCH64_ASM_H
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#define OPCODES_AARCH64_ASM_H
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#include "aarch64-opc.h"
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/* Given OPCODE, return the opcode entry that OPCODE aliases to, e.g.
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given LSL, return UBFM. */
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const aarch64_opcode* aarch64_find_real_opcode (const aarch64_opcode *);
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/* Switch-table-based high-level operand inserter. */
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const char* aarch64_insert_operand (const aarch64_operand *,
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const aarch64_opnd_info *, aarch64_insn *,
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const aarch64_inst *);
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/* Operand inserters. */
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#define AARCH64_DECL_OPD_INSERTER(x) \
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const char* aarch64_##x (const aarch64_operand *, const aarch64_opnd_info *, \
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aarch64_insn *, const aarch64_inst *)
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AARCH64_DECL_OPD_INSERTER (ins_regno);
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AARCH64_DECL_OPD_INSERTER (ins_reglane);
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AARCH64_DECL_OPD_INSERTER (ins_reglist);
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AARCH64_DECL_OPD_INSERTER (ins_ldst_reglist);
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AARCH64_DECL_OPD_INSERTER (ins_ldst_reglist_r);
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AARCH64_DECL_OPD_INSERTER (ins_ldst_elemlist);
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AARCH64_DECL_OPD_INSERTER (ins_advsimd_imm_shift);
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AARCH64_DECL_OPD_INSERTER (ins_imm);
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AARCH64_DECL_OPD_INSERTER (ins_imm_half);
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AARCH64_DECL_OPD_INSERTER (ins_advsimd_imm_modified);
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AARCH64_DECL_OPD_INSERTER (ins_fpimm);
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AARCH64_DECL_OPD_INSERTER (ins_fbits);
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AARCH64_DECL_OPD_INSERTER (ins_aimm);
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AARCH64_DECL_OPD_INSERTER (ins_limm);
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AARCH64_DECL_OPD_INSERTER (ins_inv_limm);
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AARCH64_DECL_OPD_INSERTER (ins_ft);
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AARCH64_DECL_OPD_INSERTER (ins_addr_simple);
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AARCH64_DECL_OPD_INSERTER (ins_addr_regoff);
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AARCH64_DECL_OPD_INSERTER (ins_addr_simm);
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AARCH64_DECL_OPD_INSERTER (ins_addr_simm10);
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AARCH64_DECL_OPD_INSERTER (ins_addr_uimm12);
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AARCH64_DECL_OPD_INSERTER (ins_simd_addr_post);
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AARCH64_DECL_OPD_INSERTER (ins_cond);
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AARCH64_DECL_OPD_INSERTER (ins_sysreg);
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AARCH64_DECL_OPD_INSERTER (ins_pstatefield);
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AARCH64_DECL_OPD_INSERTER (ins_sysins_op);
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AARCH64_DECL_OPD_INSERTER (ins_barrier);
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AARCH64_DECL_OPD_INSERTER (ins_hint);
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AARCH64_DECL_OPD_INSERTER (ins_prfop);
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AARCH64_DECL_OPD_INSERTER (ins_reg_extended);
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AARCH64_DECL_OPD_INSERTER (ins_reg_shifted);
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AARCH64_DECL_OPD_INSERTER (ins_sve_addr_ri_s4);
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AARCH64_DECL_OPD_INSERTER (ins_sve_addr_ri_s4xvl);
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AARCH64_DECL_OPD_INSERTER (ins_sve_addr_ri_s6xvl);
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AARCH64_DECL_OPD_INSERTER (ins_sve_addr_ri_s9xvl);
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AARCH64_DECL_OPD_INSERTER (ins_sve_addr_ri_u6);
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AARCH64_DECL_OPD_INSERTER (ins_sve_addr_rr_lsl);
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AARCH64_DECL_OPD_INSERTER (ins_sve_addr_rz_xtw);
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AARCH64_DECL_OPD_INSERTER (ins_sve_addr_zi_u5);
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AARCH64_DECL_OPD_INSERTER (ins_sve_addr_zz_lsl);
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AARCH64_DECL_OPD_INSERTER (ins_sve_addr_zz_sxtw);
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AARCH64_DECL_OPD_INSERTER (ins_sve_addr_zz_uxtw);
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AARCH64_DECL_OPD_INSERTER (ins_sve_aimm);
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AARCH64_DECL_OPD_INSERTER (ins_sve_asimm);
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AARCH64_DECL_OPD_INSERTER (ins_sve_float_half_one);
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AARCH64_DECL_OPD_INSERTER (ins_sve_float_half_two);
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AARCH64_DECL_OPD_INSERTER (ins_sve_float_zero_one);
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AARCH64_DECL_OPD_INSERTER (ins_sve_index);
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AARCH64_DECL_OPD_INSERTER (ins_sve_limm_mov);
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AARCH64_DECL_OPD_INSERTER (ins_sve_quad_index);
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AARCH64_DECL_OPD_INSERTER (ins_sve_reglist);
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AARCH64_DECL_OPD_INSERTER (ins_sve_scale);
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AARCH64_DECL_OPD_INSERTER (ins_sve_shlimm);
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AARCH64_DECL_OPD_INSERTER (ins_sve_shrimm);
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AARCH64_DECL_OPD_INSERTER (ins_imm_rotate1);
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AARCH64_DECL_OPD_INSERTER (ins_imm_rotate2);
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#undef AARCH64_DECL_OPD_INSERTER
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#endif /* OPCODES_AARCH64_ASM_H */
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