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https://github.com/bminor/binutils-gdb.git
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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
120 lines
1.9 KiB
ArmAsm
120 lines
1.9 KiB
ArmAsm
# sh testcase for pshl <imm>
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# mach: all
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# as(sh): -defsym sim_cpu=0
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# as(shdsp): -defsym sim_cpu=1 -dsp
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.include "testutils.inc"
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start
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pshl_imm: ! shift logical, immediate operand
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set_grs_a5a5
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lds r0, a0
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pcopy a0, a1
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lds r0, x0
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lds r0, x1
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lds r0, y0
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lds r0, y1
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pcopy x0, m0
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pcopy y1, m1
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set_sreg 0x10000, a0
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pshl #0, a0
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assert_sreg 0x10000, a0
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pshl #-0, a0
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assert_sreg 0x10000, a0
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pshl #1, a0
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assert_sreg 0x20000, a0
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pshl #-1, a0
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assert_sreg 0x10000, a0
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pshl #2, a0
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assert_sreg 0x40000, a0
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pshl #-2, a0
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assert_sreg 0x10000, a0
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pshl #3, a0
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assert_sreg 0x80000, a0
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pshl #-3, a0
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assert_sreg 0x10000, a0
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pshl #4, a0
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assert_sreg 0x100000, a0
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pshl #-4, a0
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assert_sreg 0x10000, a0
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pshl #5, a0
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assert_sreg 0x200000, a0
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pshl #-5, a0
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assert_sreg 0x10000, a0
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pshl #6, a0
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assert_sreg 0x400000, a0
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pshl #-6, a0
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assert_sreg 0x10000, a0
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pshl #7, a0
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assert_sreg 0x800000, a0
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pshl #-7, a0
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assert_sreg 0x10000, a0
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pshl #8, a0
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assert_sreg 0x1000000, a0
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pshl #-8, a0
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assert_sreg 0x10000, a0
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pshl #9, a0
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assert_sreg 0x2000000, a0
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pshl #-9, a0
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assert_sreg 0x10000, a0
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pshl #10, a0
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assert_sreg 0x4000000, a0
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pshl #-10, a0
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assert_sreg 0x10000, a0
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pshl #11, a0
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assert_sreg 0x8000000, a0
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pshl #-11, a0
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assert_sreg 0x10000, a0
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pshl #12, a0
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assert_sreg 0x10000000, a0
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pshl #-12, a0
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assert_sreg 0x10000, a0
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pshl #13, a0
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assert_sreg 0x20000000, a0
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pshl #-13, a0
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assert_sreg 0x10000, a0
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pshl #14, a0
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assert_sreg 0x40000000, a0
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pshl #-14, a0
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assert_sreg 0x10000, a0
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pshl #15, a0
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assert_sreg 0x80000000, a0
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pshl #-15, a0
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assert_sreg 0x10000, a0
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pshl #16, a0
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assert_sreg 0x00000000, a0
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pshl #-16, a0
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assert_sreg 0x0, a0
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test_grs_a5a5
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assert_sreg2 0xa5a5a5a5, a1
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assert_sreg 0xa5a5a5a5, x0
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assert_sreg 0xa5a5a5a5, x1
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assert_sreg 0xa5a5a5a5, y0
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assert_sreg 0xa5a5a5a5, y1
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assert_sreg2 0xa5a5a5a5, m0
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assert_sreg2 0xa5a5a5a5, m1
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pass
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exit 0
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