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63b862be76
This patch adds the user mode register PL3_SSP which is part of the
Intel(R) Control-Flow Enforcement Technology (CET) feature for support
of shadow stack.
For now, only native and remote debugging support for shadow stack
userspace on amd64 linux are covered by this patch including 64 bit and
x32 support. 32 bit support is not covered due to missing Linux kernel
support.
This patch requires fixing the test gdb.base/inline-frame-cycle-unwind
which is failing in case the shadow stack pointer is unavailable.
Such a state is possible if shadow stack is disabled for the current thread
but supported by HW.
This test uses the Python unwinder inline-frame-cycle-unwind.py which fakes
the cyclic stack cycle by reading the pending frame's registers and adding
them to the unwinder:
~~~
for reg in pending_frame.architecture().registers("general"):
val = pending_frame.read_register(reg)
unwinder.add_saved_register(reg, val)
return unwinder
~~~
However, in case the python unwinder is used we add a register (pl3_ssp) that is
unavailable. This leads to a NOT_AVAILABLE_ERROR caught in
gdb/frame-unwind.c:frame_unwind_try_unwinder and it is continued with standard
unwinders. This destroys the faked cyclic behavior and the stack is
further unwinded after frame 5.
In the working scenario an error should be triggered:
~~~
bt
0 inline_func () at /tmp/gdb.base/inline-frame-cycle-unwind.c:49^M
1 normal_func () at /tmp/gdb.base/inline-frame-cycle-unwind.c:32^M
2 0x000055555555516e in inline_func () at /tmp/gdb.base/inline-frame-cycle-unwind.c:45^M
3 normal_func () at /tmp/gdb.base/inline-frame-cycle-unwind.c:32^M
4 0x000055555555516e in inline_func () at /tmp/gdb.base/inline-frame-cycle-unwind.c:45^M
5 normal_func () at /tmp/gdb.base/inline-frame-cycle-unwind.c:32^M
Backtrace stopped: previous frame identical to this frame (corrupt stack?)
(gdb) PASS: gdb.base/inline-frame-cycle-unwind.exp: cycle at level 5: backtrace when the unwind is broken at frame 5
~~~
To fix the Python unwinder, we simply skip the unavailable registers.
Also it makes the test gdb.dap/scopes.exp fail. The shadow stack feature is
disabled by default, so the pl3_ssp register which is added with my CET
shadow stack series will be shown as unavailable and we see a TCL error:
~~
>>> {"seq": 12, "type": "request", "command": "variables", "arguments": {"variablesReference": 2, "count": 85}}
Content-Length: 129^M
^M
{"request_seq": 12, "type": "response", "command": "variables", "success": false, "message": "value is not available", "seq": 25}FAIL: gdb.dap/scopes.exp: fetch all registers success
ERROR: tcl error sourcing /tmp/gdb/testsuite/gdb.dap/scopes.exp.
ERROR: tcl error code TCL LOOKUP DICT body
ERROR: key "body" not known in dictionary
while executing
"dict get $val body variables"
(file "/tmp/gdb/testsuite/gdb.dap/scopes.exp" line 152)
invoked from within
"source /tmp/gdb/testsuite/gdb.dap/scopes.exp"
("uplevel" body line 1)
invoked from within
"uplevel #0 source /tmp/gdb/testsuite/gdb.dap/scopes.exp"
invoked from within
"catch "uplevel #0 source $test_file_name" msg"
UNRESOLVED: gdb.dap/scopes.exp: testcase '/tmp/gdb/testsuite/gdb.dap/scopes.exp' aborted due to Tcl error
~~
I am fixing this by enabling the test for CET shadow stack, in case we
detect that the HW supports it:
~~~
# If x86 shadow stack is supported we need to configure GLIBC_TUNABLES
# such that the feature is enabled and the register pl3_ssp is
# available. Otherwise the reqeust to fetch all registers will fail
# with "message": "value is not available".
if { [allow_ssp_tests] } {
append_environment GLIBC_TUNABLES "glibc.cpu.hwcaps" "SHSTK"
}
~~~
Reviewed-by: Thiago Jung Bauermann <thiago.bauermann@linaro.org>
Reviewed-By: Eli Zaretskii <eliz@gnu.org>
Approved-By: Luis Machado <luis.machado@arm.com>
Approved-By: Andrew Burgess <aburgess@redhat.com>
136 lines
4.6 KiB
C++
136 lines
4.6 KiB
C++
/* Common code for x86 XSAVE extended state.
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Copyright (C) 2010-2025 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef GDBSUPPORT_X86_XSTATE_H
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#define GDBSUPPORT_X86_XSTATE_H
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/* The extended state feature IDs in the state component bitmap. */
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#define X86_XSTATE_X87_ID 0
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#define X86_XSTATE_SSE_ID 1
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#define X86_XSTATE_AVX_ID 2
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#define X86_XSTATE_K_ID 5
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#define X86_XSTATE_ZMM_H_ID 6
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#define X86_XSTATE_ZMM_ID 7
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#define X86_XSTATE_PKRU_ID 9
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#define X86_XSTATE_CET_U_ID 11
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/* The extended state feature bits. */
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#define X86_XSTATE_X87 (1ULL << X86_XSTATE_X87_ID)
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#define X86_XSTATE_SSE (1ULL << X86_XSTATE_SSE_ID)
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#define X86_XSTATE_AVX (1ULL << X86_XSTATE_AVX_ID)
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/* AVX 512 adds three feature bits. All three must be enabled. */
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#define X86_XSTATE_K (1ULL << X86_XSTATE_K_ID)
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#define X86_XSTATE_ZMM_H (1ULL << X86_XSTATE_ZMM_H_ID)
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#define X86_XSTATE_ZMM (1ULL << X86_XSTATE_ZMM_ID)
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#define X86_XSTATE_AVX512 (X86_XSTATE_K | X86_XSTATE_ZMM_H \
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| X86_XSTATE_ZMM)
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#define X86_XSTATE_PKRU (1ULL << X86_XSTATE_PKRU_ID)
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#define X86_XSTATE_CET_U (1ULL << X86_XSTATE_CET_U_ID)
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/* Total size of the XSAVE area extended region and offsets of
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register states within the region. Offsets are set to 0 to
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indicate the absence of the associated registers. */
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struct x86_xsave_layout
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{
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int sizeof_xsave = 0;
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int avx_offset = 0;
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int k_offset = 0;
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int zmm_h_offset = 0;
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int zmm_offset = 0;
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int pkru_offset = 0;
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};
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constexpr bool operator== (const x86_xsave_layout &lhs,
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const x86_xsave_layout &rhs)
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{
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return lhs.sizeof_xsave == rhs.sizeof_xsave
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&& lhs.avx_offset == rhs.avx_offset
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&& lhs.k_offset == rhs.k_offset
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&& lhs.zmm_h_offset == rhs.zmm_h_offset
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&& lhs.zmm_offset == rhs.zmm_offset
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&& lhs.pkru_offset == rhs.pkru_offset;
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}
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constexpr bool operator!= (const x86_xsave_layout &lhs,
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const x86_xsave_layout &rhs)
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{
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return !(lhs == rhs);
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}
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/* Supported mask and size of the extended state. */
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#define X86_XSTATE_X87_MASK X86_XSTATE_X87
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#define X86_XSTATE_SSE_MASK (X86_XSTATE_X87 | X86_XSTATE_SSE)
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#define X86_XSTATE_AVX_MASK (X86_XSTATE_SSE_MASK | X86_XSTATE_AVX)
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#define X86_XSTATE_AVX_AVX512_MASK (X86_XSTATE_AVX_MASK | X86_XSTATE_AVX512)
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#define X86_XSTATE_AVX_AVX512_PKU_MASK (X86_XSTATE_AVX_MASK\
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| X86_XSTATE_AVX512 | X86_XSTATE_PKRU)
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/* Supported mask of state-component bitmap xstate_bv. The SDM defines
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xstate_bv as XCR0 | IA32_XSS. */
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#define X86_XSTATE_ALL_MASK (X86_XSTATE_AVX_AVX512_PKU_MASK\
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| X86_XSTATE_CET_U)
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#define X86_XSTATE_SSE_SIZE 576
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#define X86_XSTATE_AVX_SIZE 832
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#define HAS_AVX(XCR0) (((XCR0) & X86_XSTATE_AVX) != 0)
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#define HAS_AVX512(XCR0) (((XCR0) & X86_XSTATE_AVX512) != 0)
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#define HAS_PKRU(XCR0) (((XCR0) & X86_XSTATE_PKRU) != 0)
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/* Initial value for fctrl register, as defined in the X86 manual, and
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confirmed in the (Linux) kernel source. When the x87 floating point
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feature is not enabled in an inferior we use this as the value of the
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fcrtl register. */
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#define I387_FCTRL_INIT_VAL 0x037f
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/* Initial value for mxcsr register. When the avx and sse floating point
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features are not enabled in an inferior we use this as the value of the
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mxcsr register. */
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#define I387_MXCSR_INIT_VAL 0x1f80
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/* Format of XSAVE extended state is:
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struct
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{
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fxsave_bytes[0..463]
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sw_usable_bytes[464..511]
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xstate_hdr_bytes[512..575]
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extended state regions (AVX, MPX, AVX512, PKRU, etc.)
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};
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Same memory layout will be used for the coredump NT_X86_XSTATE
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representing the XSAVE extended state registers.
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The first 8 bytes of the sw_usable_bytes[464..467] is the OS enabled
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extended state mask, which is the same as the extended control register
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0 (the XFEATURE_ENABLED_MASK register), XCR0. We can use this mask
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together with the mask saved in the xstate_hdr_bytes to determine what
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states the processor/OS supports and what state, used or initialized,
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the process/thread is in. */
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#define I386_LINUX_XSAVE_XCR0_OFFSET 464
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#endif /* GDBSUPPORT_X86_XSTATE_H */
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